- MFi386: sys/i386/i386/intr_machdep.c rev. 1.11

  Don't use atomic ops to increment interrupt stats.
  On sparc64 this reduces delay until tick interrupts are service by 1/10th
  on average. In turn this reduces the clock drift caused by these delays
  so there's less drift which has to be compensated in tick_hardclock().
  This includes switching from atomically incrementing the global cnt.v_intr
  to the asm equivalent of PCPU_LAZY_INC(cnt.v_intr) in exception.S
- Correct some comments to match the registers actually used.
- Correct some format specifiers, interrupt levels passed in are u_int.
- Use FBSDID.

Ok'ed by:	jhb

1 files changed, 1 insertions, 1 deletions

diff --git a/sys/sparc64/sparc64/intr_machdep.c b/sys/sparc64/sparc64/intr_machdep.c
index f460f20989cd..24f71daa24b2 100644
--- a/sys/sparc64/sparc64/intr_machdep.c
+++ b/sys/sparc64/sparc64/intr_machdep.c
@@ -199,7 +199,7 @@ intr_stray_vector(void *cookie)
 	iv = cookie;
 	if (intr_stray_count[iv->iv_vec] < MAX_STRAY_LOG) {
 		printf("stray vector interrupt %d\n", iv->iv_vec);
-		atomic_add_long(&intr_stray_count[iv->iv_vec], 1);
+		intr_stray_count[iv->iv_vec]++;
 		if (intr_stray_count[iv->iv_vec] >= MAX_STRAY_LOG)
 			printf("got %d stray interrupt %d's: not logging "
 			    "anymore\n", MAX_STRAY_LOG, iv->iv_vec);