e1000: Limit the TSO sentinel to lem(4) controllersHEADmain

The TSO workaround splits the final DMA segment to create a four byte
sentinel descriptor.  Intel documents the premature descriptor writeback
erratum and this workaround in the 82540EP and 82545GM specification
updates (erratum 3) and the 82546GB specification update (erratum 1).

Limit the workaround and its preceding TSO state to the legacy PCI and
PCI-X controllers so PCIe controllers retain their natural descriptor
layout using one fewer descriptor per TSO packet, no split of the final
segment, and one less four byte DMA.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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