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| author | Konstantin Belousov <kib@FreeBSD.org> | 2015-02-09 21:00:56 +0000 |
|---|---|---|
| committer | Konstantin Belousov <kib@FreeBSD.org> | 2015-02-09 21:00:56 +0000 |
| commit | 4c918926cd538a36bb2d54a0f4eb4ca3ebbe16e4 (patch) | |
| tree | d2e88c87f150ce7e0dfe34e37fbc902c5f84fd8a /sys/x86/include/specialreg.h | |
| parent | 2575fbb82713dcfca8a5a8794119a7cd4c713405 (diff) | |
| download | src-4c918926cd538a36bb2d54a0f4eb4ca3ebbe16e4.tar.gz src-4c918926cd538a36bb2d54a0f4eb4ca3ebbe16e4.zip | |
Add x2APIC support. Enable it by default if CPU is capable. The
hw.x2apic_enable tunable allows disabling it from the loader prompt.
To closely repeat effects of the uncached memory ops when accessing
registers in the xAPIC mode, the x2APIC writes to MSRs are preceeded
by mfence, except for the EOI notifications. This is probably too
strict, only ICR writes to send IPI require serialization to ensure
that other CPUs see the previous actions when IPI is delivered. This
may be changed later.
In vmm justreturn IPI handler, call doreti_iret instead of doing iretd
inline, to handle corner conditions.
Note that the patch only switches LAPICs into x2APIC mode. It does not
enables FreeBSD to support > 255 CPUs, which requires parsing x2APIC
MADT entries and doing interrupts remapping, but is the required step
on the way.
Reviewed by: neel
Tested by: pho (real hardware), neel (on bhyve)
Discussed with: jhb, grehan
Sponsored by: The FreeBSD Foundation
MFC after: 2 months
Notes
Notes:
svn path=/head/; revision=278473
Diffstat (limited to 'sys/x86/include/specialreg.h')
| -rw-r--r-- | sys/x86/include/specialreg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 4d1086eeae60..60f46fb68e59 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -470,6 +470,7 @@ /* * X2APIC MSRs */ +#define MSR_APIC_000 0x800 #define MSR_APIC_ID 0x802 #define MSR_APIC_VERSION 0x803 #define MSR_APIC_TPR 0x808 |