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| author | Neel Natu <neel@FreeBSD.org> | 2015-05-06 05:12:29 +0000 |
|---|---|---|
| committer | Neel Natu <neel@FreeBSD.org> | 2015-05-06 05:12:29 +0000 |
| commit | 712bd51ada550e639e88ebfe954143681e94b030 (patch) | |
| tree | c36c8b068fb118d8250f2c012156b9b55ab09e0d /sys/x86 | |
| parent | 618223117eef6a3e594d6cb442623ad7e5e35afd (diff) | |
| download | src-712bd51ada550e639e88ebfe954143681e94b030.tar.gz src-712bd51ada550e639e88ebfe954143681e94b030.zip | |
Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE.
AMDID_FFXSR is at bit 25 so correct its value to 0x02000000.
MFC after: 1 week
Notes
Notes:
svn path=/head/; revision=282519
Diffstat (limited to 'sys/x86')
| -rw-r--r-- | sys/x86/include/specialreg.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 60f46fb68e59..a771fffaea57 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -82,6 +82,9 @@ #define EFER_LMA 0x000000400 /* Long mode active (R) */ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ +#define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ +#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ +#define EFER_TCE 0x000008000 /* Translation Cache Extension */ /* * Intel Extended Features registers @@ -191,7 +194,7 @@ #define AMDID_MP 0x00080000 #define AMDID_NX 0x00100000 #define AMDID_EXT_MMX 0x00400000 -#define AMDID_FFXSR 0x01000000 +#define AMDID_FFXSR 0x02000000 #define AMDID_PAGE1GB 0x04000000 #define AMDID_RDTSCP 0x08000000 #define AMDID_LM 0x20000000 |