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| author | Adrian Chadd <adrian@FreeBSD.org> | 2015-03-04 03:51:54 +0000 |
|---|---|---|
| committer | Adrian Chadd <adrian@FreeBSD.org> | 2015-03-04 03:51:54 +0000 |
| commit | 4f1cbb2fdce0b0f2552635358dab38bb1978a9ad (patch) | |
| tree | 56ec465cdf02165d732d8cc29efa58bde79c4609 /sys | |
| parent | 1d556f272c5044e9a8c879acd52dc8b551aaf684 (diff) | |
| download | src-4f1cbb2fdce0b0f2552635358dab38bb1978a9ad.tar.gz src-4f1cbb2fdce0b0f2552635358dab38bb1978a9ad.zip | |
Add DDR flush registers for QCA955x.
Notes
Notes:
svn path=/head/; revision=279578
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/mips/atheros/qca955xreg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sys/mips/atheros/qca955xreg.h b/sys/mips/atheros/qca955xreg.h index 905b296d2c29..555070d69217 100644 --- a/sys/mips/atheros/qca955xreg.h +++ b/sys/mips/atheros/qca955xreg.h @@ -198,4 +198,11 @@ #define QCA955X_PLL_VAL_100 0x00000101 #define QCA955X_PLL_VAL_10 0x00001616 +/* DDR block */ +#define QCA955X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c) +#define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0) +#define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) +#define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) +#define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) + #endif /* __QCA955XREG_H__ */ |