Exar driver for X3100 10GbE Server/Storage adapters

Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
          TSO (TCP segmentation offload), RTH (Receive Traffic Hash).

Submitted by: Sriram Rapuru at Exar
MFC after:	2 weeks

69 files changed, 107644 insertions, 0 deletions

diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index ecaa0774620e..08d1f3cb0881 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -2094,6 +2094,7 @@ device		nxge		# Neterion Xframe 10GbE Server/Storage Adapter
 device		ti		# Alteon Networks Tigon I/II gigabit Ethernet
 device		txp		# 3Com 3cR990 (``Typhoon'')
 device		vx		# 3Com 3c590, 3c595 (``Vortex'')
+device		vxge		# Exar/Neterion XFrame 3100 10GbE
 
 # PCI FDDI NICs.
 device		fpa
diff --git a/sys/conf/files b/sys/conf/files
index d403f71e0381..8d46d7db88bc 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1970,6 +1970,24 @@ dev/vte/if_vte.c		optional vte pci
 dev/vx/if_vx.c			optional vx
 dev/vx/if_vx_eisa.c		optional vx eisa
 dev/vx/if_vx_pci.c		optional vx pci
+dev/vxge/vxge.c				optional vxge
+dev/vxge/vxgehal/vxgehal-ifmsg.c	optional vxge
+dev/vxge/vxgehal/vxgehal-mrpcim.c	optional vxge
+dev/vxge/vxgehal/vxge-queue.c		optional vxge
+dev/vxge/vxgehal/vxgehal-ring.c		optional vxge
+dev/vxge/vxgehal/vxgehal-swapper.c	optional vxge
+dev/vxge/vxgehal/vxgehal-mgmt.c		optional vxge
+dev/vxge/vxgehal/vxgehal-srpcim.c	optional vxge
+dev/vxge/vxgehal/vxgehal-config.c	optional vxge
+dev/vxge/vxgehal/vxgehal-blockpool.c	optional vxge
+dev/vxge/vxgehal/vxgehal-doorbells.c	optional vxge
+dev/vxge/vxgehal/vxgehal-mgmtaux.c	optional vxge
+dev/vxge/vxgehal/vxgehal-device.c	optional vxge
+dev/vxge/vxgehal/vxgehal-mm.c		optional vxge
+dev/vxge/vxgehal/vxgehal-driver.c	optional vxge
+dev/vxge/vxgehal/vxgehal-virtualpath.c	optional vxge
+dev/vxge/vxgehal/vxgehal-channel.c	optional vxge
+dev/vxge/vxgehal/vxgehal-fifo.c		optional vxge
 dev/watchdog/watchdog.c		standard
 dev/wb/if_wb.c			optional wb pci
 dev/wds/wd7000.c		optional wds isa
diff --git a/sys/dev/vxge/LICENSE b/sys/dev/vxge/LICENSE
new file mode 100644
index 000000000000..6dcbdeb86979
--- /dev/null
+++ b/sys/dev/vxge/LICENSE
@@ -0,0 +1,31 @@
+/*-
+ *  Copyright (c) 2002-2010 Exar Corp.
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
\ No newline at end of file
diff --git a/sys/dev/vxge/README b/sys/dev/vxge/README
new file mode 100644
index 000000000000..ed1c1c005326
--- /dev/null
+++ b/sys/dev/vxge/README
@@ -0,0 +1,450 @@
+$FreeBSD$
+''_Readme for FreeBSD X3100 Series 10GbE PCIe I/O Virtualized Server Adapter Drivers_'''
+
+=== Introduction ===
+FreeBSD Driver for X3100 10GbE Server/Storage adapters 
+* Drivers support all X3100 10GbE adapters with FreeBSD version 7.x, 8.x and 9.x
+* Supports both i386 and amd64 architectures
+* Features:	Jumbo frames (up to 9600),
+		LRO (Large Receive Offload),
+		TSO (TCP segmentation offload),
+		RTH (Receive Traffic Hash).
+   Also, Extended Message Signaled Interrupts (MSI-X).
+
+
+''Features''
+
+    a.	Jumbo frames:
+	X3110 and X3120 supports MTU up to 9600 bytes, modifiable using ifconfig command.
+
+    b.	LRO (Large Receive Offload):
+	LRO can be enabled/disabled before loading driver.
+	Set lro_enable in vxge.conf to 1 before loading driver.
+
+    c.	TSO (TCP Segmentation Offload)
+	TSO can be enabled/disabled before loading driver.
+	Set tso_enable in vxge.conf to 1 before loading driver.
+
+    d.	RTH (Receive Traffic Hash)
+	Receive side steering for better scaling.
+	Set rth_enable in vxge.conf to 1 before loading driver.
+
+    e.	MSI-X
+	Can be enabled on platforms which support it, resulting in noticeable
+	performance improvement. 
+
+    f.	Multi-VPaths
+	Up to 17 hardware based transmit and receive data channels, with
+	multiple steering options.
+
+
+''X3100 & Driver configuration: vxge.conf''
+
+The vxge.conf contains following attributes.
+
+
+''msix_enable''
+
+Enable MSI (Message Signaled Interrupts) feature in driver.
+0 - INTA
+1 - MSI-X
+Default: 1
+
+
+''rth_enable''
+
+Enables Receive side steering for better scaling (RTH - Receive Traffic Hash)
+Range: 0 - 1
+Default: 1
+
+
+''lro_enable''
+
+Enables LRO (Large Receive Offload) feature in driver.
+Range: 0 - 1
+Default: 1
+
+
+''tso_enable''
+
+Enables TSO (TCP Segmentaton Offload) feature in driver.
+Range: 0 - 1
+Default: 1
+
+
+''no_of_vpath''
+
+Specifies maximum VPATH(s) configured for each device function.
+Valid range: 1-17
+Default: Optimized by driver
+
+
+''func_mode''
+
+Change PCI function mode
+    0  - SF1_VP17 (1 function with 17 VPATHs)
+    1  - MF8_VP2  (8 functions with 2 VPATHs per function)
+    8  - MF2_VP8  (2 functions, 8 Paths/Function)
+    9  - MF4_VP4  (4 Functions, 4 Paths/Function)
+    11 - MF8P_VP2 (8 functions with 2 VPATHS per function required for DirectIO)
+    Default: -1
+
+
+''port_mode''
+
+Change the default dual port mode
+    2 - Active Passive
+    3 - Single Port
+    4 - Dual Port
+
+
+''l2_switch''
+
+Turn on/off the inter function traffic through l2 switch
+    0 - Disallow inter function traffic
+    1 - Allow inter function traffic
+    Default: -1
+
+
+''bandwidth_0 - bandwidth_7''
+
+    Desired max receive/transmit bandwidth,in Mbps for function 0 to function 7
+    Minimum value is 100 Mbps, for 1 Gbps specify a value of 1024.
+
+
+''priority_0 - priority_7''
+
+    Desired receive/transmit priority for function 0 to function 7 
+
+
+''intr_coalesce''
+
+    Adaptive interrupt coalescing
+    0 - Disable
+    1 - Enable
+
+
+''Low Latency''
+
+   0 - Disable
+   1 - Enable
+
+=== Installation Instructions ===
+
+''Identifying the Adapter''
+
+    The X3100 adapter is identified by the board ID number on the adapter.
+
+    Look for a label that has a barcode and a number, for example,
+    SXT0425072. The factory-burned MAC address (hardware address)
+    shows up on the board above the serial number, 
+    (similar to 000CFC000449 -- 00:0C:FC:00:04:49).
+
+
+''Kernel Driver Source Package''
+
+This package contains kernel_update.sh script which is to be used to copy driver sources to kernel path.
+It creates vxge folder with source code in /usr/src/sys/dev and Makefile in /usr/src/sys/modules.
+
+Loadable parameters can be changed by putting below lines in /boot/device.hints and set values as desired.
+	hint.vxge.0.msix_enable="1"
+	hint.vxge.0.rth_enable="1"
+	hint.vxge.0.lro_enable="1"
+	hint.vxge.0.tso_enable="1"
+	hint.vxge.0.tx_steering="1"
+	hint.vxge.0.no_of_vpath="-1"
+	hint.vxge.0.func_mode="-1"
+	hint.vxge.0.port_mode="-1"
+	hint.vxge.0.fw_upgrade="1"
+	hint.vxge.0.bandwidth_0="-1"
+	hint.vxge.0.bandwidth_1="-1"
+	hint.vxge.0.bandwidth_2="-1"
+	hint.vxge.0.bandwidth_3="-1"
+	hint.vxge.0.bandwidth_4="-1"
+	hint.vxge.0.bandwidth_5="-1"
+	hint.vxge.0.bandwidth_6="-1"
+	hint.vxge.0.bandwidth_7="-1"
+	hint.vxge.0.priority_0="-1"
+	hint.vxge.0.priority_1="-1"
+	hint.vxge.0.priority_2="-1"
+	hint.vxge.0.priority_3="-1"
+	hint.vxge.0.priority_4="-1"
+	hint.vxge.0.priority_5="-1"
+	hint.vxge.0.priority_6="-1"
+	hint.vxge.0.priority_7="-1"
+	hint.vxge.0.intr_coalesce="0"
+	hint.vxge.0.low_latency="0"
+
+	e.g., set hint.vxge.0.msix_enable to 0 to load driver in INTA mode.
+	Then reboot the system to add loadable parameters to kenv.
+
+
+''Standalone Driver Source Package''
+
+vxge (FreeBSD package)
+    This directory contains FreeBSD driver sources for X3100 device(s),
+    Makefile, and X3100 Hardware Abstraction headers and sources
+    (vxgehal and include folders)
+
+vxgehal
+    This directory contains the X3100 HAL sources.
+    The driver uses HAL to perform operations on the X3100 hardware.
+
+include
+    The include subdirectory contains HAL header files.
+ 
+Source code for vxge-manage tool (used to get statistics, pciconfig and
+register dump) are included in the freebsd directory.
+
+
+''Building the driver''
+
+    The driver is distributed in the source form. Driver and installation
+    utility executables need to be built for the target platform. 
+
+    In the directory containing Makefile for building Exar driver for FreeBSD, 
+	#make clean
+	#make
+
+    Please unload previously installed Exar drivers before proceeding with following steps.
+	#make uninstall
+
+
+''Loading the driver''
+
+     Use "kldload" to load driver module vxge.ko.
+	#kldload ./vxge.ko
+
+    Run "kldstat" and find an entry for vxge kernel module to ensure driver installation
+    was successful.
+	#kldstat | grep vxge
+	3 1 0xc22cc000 26000   vxge.ko
+
+
+''Enabling interface and assigning IP address''
+
+    #ifconfig <INTERFACE> <IP_ADDRESS> up
+    <INTERFACE> will be similar to vxge0, vxge1 etc. and can be
+    found by executing "ifconfig -a".
+    Neterion adapters typically have MAC addresses starting with
+    "00:0C:FC" or "00:11:25".
+
+    Example:
+	#ifconfig vxge0 10.2.2.40 up
+	Enables vxge0 interface and assigns to it the IP address 10.2.2.40.
+
+	vxge0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> metric 0 mtu 1500
+	options=53b<RXCSUM,TXCSUM,VLAN_MTU,VLAN_HWTAGGING,JUMBO_MTU,TSO4,LRO>
+	ether 00:0c:fc:00:da:47
+	inet6 fe80::20c:fcff:fe00:da47%vxge0 prefixlen 64 scopeid 0x3
+	inet 10.2.2.40 netmask 0xff000000 broadcast 17.255.255.255
+	media: Ethernet autoselect (10Gbase-SR <full-duplex>)
+	status: active
+
+
+''Disabling the interface''
+
+    #ifconfig <INTERFACE> down
+    Example:
+	#ifconfig vxge0 down
+
+
+''Unloading the Driver''
+	#kldunload vxge.ko
+
+
+=== Performance Suggestions ===
+
+Sysctl Tuning Parameters
+	#sysctl net.inet.tcp.sendspace=786432
+	#sysctl net.inet.tcp.recvspace=786432
+	#sysctl net.inet.tcp.recvbuf_max=16777216
+	#sysctl net.inet.tcp.sendbuf_max=16777216
+	#sysctl net.inet.tcp.blackhole=1
+	#sysctl net.inet.tcp.rfc1323=1
+	#sysctl net.inet.tcp.path_mtu_discovery=1
+	#sysctl net.inet.tcp.inflight.enable=0
+	#sysctl net.inet.ip.maxfragsperpacket=2147483647
+	#sysctl kern.ipc.maxsockbuf=8388608
+	#sysctl kern.ipc.nmbclusters=2147483647
+	#sysctl kern.ipc.nmbjumbop=262144
+	#sysctl kern.ipc.maxsockets=81920
+	#sysctl hw.intr_storm_threshold=9000
+
+
+''Usage & Troubleshooting''
+
+For general information and support, please visit Neterion support website at 
+http://www.neterion.com/support/support.html
+
+Make sure that the operating system identifies the X3100 adapter. Note that
+Neterion vendor ID is 0x17D5 and X3110 and X3120 adapters can be fixed to both PCIe slots.
+
+The rest of this section details troubleshooting tips and information. Some of
+them are general and some are more specific. For online Troubleshooting tips 
+and faqs, please visit
+http://trac.neterion.com/cgi-bin/trac.cgi/wiki/TitleIndex?anonymous
+
+
+''Loading the driver and initializing the device''
+
+The first time FreeBSD identifies the device it stores the corresponding
+device/vendor IDs in an enumerated tree of PCI devices. Note that Neterion
+vendor id is 0x17d5.
+
+After cold reboot FreeBSD finds the device and tries to load the corresponding
+driver. If it fails, try to switch the card and/or cable. And, in parallel, send
+us the "tail" of the "/var/log/messages". We also need traces, register dump and
+statistics(Use vxge-manage tool).
+
+
+''Collect information''
+
+If you're reporting a problem to Neterion, please describe:
+host(s) and adapter(s), switch (if used), software version.
+
+
+''ARP''
+
+If this is a basic connectivity issue (e.g., cannot connect, cannot ping),
+make sure first that ARP works
+Do you see ARPs coming through a switch (in case switch is used)?
+Do you see frame drops at the switch when pinging?
+Do you see frame counts increasing via statistics?
+
+
+''Have you tried''
+
+    a. A previous driver release;
+    b. A different adapter in the same PCI slot;
+    c. A different PCI slot;
+    d. Back-to-back setup so that the switch is excluded from the equation.
+    e. To replace the cables?
+    f. To use a different PCI slot?
+
+
+''Start clean''
+
+    a. Have you tried to reboot the switch? Cold-reboot the host?
+    b. Make sure that the latest released driver gets loaded after the host
+    reboot, and that the 10GE interface shows up via ifconfig.
+
+
+''LEDs''
+
+Do you see LED going green after everything is connected and drivers loaded?
+How/when does the color changes?
+
+
+''ifconfig''
+
+Run "ifconfig -a" at the command prompt and check whether the output Looks as
+expected. Include the output in your problem report.
+
+Note for instance that "all-foxes" i.e, FF:FF:FF:FF:FF:FF MAC address could
+explain a general connectivity issue, if that's what you see.
+
+
+''Log''
+
+Please attach the generated log, with traces enabled.
+
+Note that the driver's logging facility is configurable at compile-time. Errors
+and traces can be compiled out on a per-component basis. The components are: HAL
+fifos and rings, device, etc., see VXGE_COMPONENT_HAL_??? in the Makefile.
+
+Here's how you enable all except data path traces:
+CFLAGS_VXGE = -DVXGE_DEBUG_MODULE_MASK=0xffffffbf  \
+-DVXGE_DEBUG_ERR_MASK=0xffffffbf
+Recompile with traces and include the log in the report.
+
+
+=== Utilities ===
+
+''Statistics''
+
+ To print hardware and software statistics for interface instance 0
+       (i.e., vxge0), run:
+	#vxge-manage vxgeX stats common
+	#vxge-manage vxgeX stats mrpcim
+	#vxge-manage vxgeX stats driver
+	#vxge-manage vxgeX pciconfig
+	#vxge-manage vxgeX hwinfo
+	#vxge-manage vxgeX bw_pri_get
+	#vxge-manage vxgeX bw_pri_get vf_id
+	#vxge-manage vxgeX port_mode_get
+
+The vxge-manage tool generates log file in the working directory. Once done, ping a
+few times, and collect the statistics again (Ping both from this and the remote
+machines).
+
+Many counters could be of interest. For example, "rx_vld_frms" counts all
+valid incoming Ethernet frames seen by the adapter. Information could be derived
+from the fact that (for instance) counter stay constant during ping, if that is
+what happening. For detailed description of the X3100 counters, please refer
+to the "X3100 User Guide".
+
+Please include the statistics into your problem report.
+
+
+''X3100 registers''
+
+       Use vxge-manage to dump all X3100 BAR0 space registers. Include this register dump
+       into your problem report.
+       #vxge-manage vxgeX regs
+
+
+''PCI configuration space''
+
+Use vxge-manage to retrieve PCI vendor, device, etc. Include the PCI configutation
+space in your problem report.
+	#vxge-manage vxgeX pciconfig
+
+
+''Hardware Info''
+
+To retrieve hardware info of device, e.g, serial / part number and function mode etc.
+use vxge-manage 
+	#vxge-manage vxgeX hwinfo
+
+
+''Bandwidth and Priority''
+
+Use vxge-manage to display Bandwidth and Priority information.
+	#vxge-manage vxgeX bw_pri_get
+	or
+	#vxge-manage vxgeX bw_pri_get vf_id
+
+vxge-manage can also be used to set bandwidth and priority for individual VF.
+	#vxge-manage vxgeX bw_pri_set vf_id bandwidth 
+	or
+	#vxge-manage vxgeX bw_pri_set vf_id bandwidth priority
+
+	Example:
+	#vxge-manage vxge0 bw_pri_set 0 1500
+	or
+	#vxge-manage vxge0 bw_pri_set 0 1500 1
+
+''Port mode''
+
+Use vxge-manage to display Port mode setting
+	#vxge-manage vxgeX port_mode_get
+
+vxge-manage can also be used to set Port mode.
+	#vxge-manage vxgeX port_mode_set port_mode_value
+
+	Example:
+	#vxge-manage vxge0 port_mode_set 2
+
+=== Known Issues ===
+
+
+=== Available Downloads ===
+
+   For latest available drivers or further support please contact your network
+   adapter provider or neterionsupport@exar.com.
+
+
+===================================================================
+ Exar Corp., Proprietary
+ COPYRIGHT (c) 2002-2011 Exar corp., ALL RIGHTS RESERVED
diff --git a/sys/dev/vxge/include/build-version.h b/sys/dev/vxge/include/build-version.h
new file mode 100644
index 000000000000..9eca7b2a673f
--- /dev/null
+++ b/sys/dev/vxge/include/build-version.h
@@ -0,0 +1,7 @@
+/* $FreeBSD$ */
+
+#ifndef	BUILD_VERSION_H
+#define	BUILD_VERSION_H
+/* Do not edit! Automatically generated when released. */
+#define	GENERATED_BUILD_VERSION 22708
+#endif /* BUILD_VERSION_H */
diff --git a/sys/dev/vxge/include/vxge-debug.h b/sys/dev/vxge/include/vxge-debug.h
new file mode 100644
index 000000000000..a4ba89443a3a
--- /dev/null
+++ b/sys/dev/vxge/include/vxge-debug.h
@@ -0,0 +1,159 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_DEBUG_H
+#define	VXGE_DEBUG_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * __FUNCTION__ is, together with __PRETTY_FUNCTION__ or something similar,
+ * a gcc extension. we'll have to #if defined around that, and provide some
+ * meaningful replacement for those, so to make some gcc versions happier
+ */
+#ifndef	__func__
+#if defined(__FUNCTION__)
+#define	__func__ __FUNCTION__
+#else
+#define	__func__ " "
+#endif
+#endif
+
+#define	NULL_HLDEV					NULL
+#define	NULL_VPID					0xFFFFFFFF
+
+#define	VXGE_DEBUG_MODULE_MASK_DEF			0xFFFFFFFF
+#define	VXGE_DEBUG_LEVEL_DEF				VXGE_TRACE
+
+extern u32 g_debug_level;
+
+#ifndef	VXGE_DEBUG_MODULE_MASK
+#define	VXGE_DEBUG_MODULE_MASK				0
+#endif
+
+/*
+ * enum vxge_debug_level_e
+ * @VXGE_NONE: debug disabled
+ * @VXGE_ERR: all errors going to be logged out
+ * @VXGE_INFO: all errors plus all kind of info tracing print outs
+ *		going to be logged out. noisy.
+ * @VXGE_TRACE: all errors, all info plus all function entry and exit
+ *		and parameters. Very noisy
+ *
+ * This enumeration going to be used to switch between different
+ * debug levels during runtime if DEBUG macro defined during
+ * compilation. If DEBUG macro not defined than code will be
+ * compiled out.
+ */
+typedef enum vxge_debug_level_e {
+	VXGE_NONE   = 0x0,
+	VXGE_ERR    = 0x1,
+	VXGE_INFO   = 0x2,
+	VXGE_TRACE  = 0x4,
+} vxge_debug_level_e;
+
+/*
+ * @VXGE_COMPONENT_HAL_DEVICE: do debug for vxge core device module
+ * @VXGE_COMPONENT_HAL_DEVICE_IRQ: do debug for vxge core device module in ISR
+ * @VXGE_COMPONENT_HAL_VAPTH: do debug for vxge core virtual path module
+ * @VXGE_COMPONENT_HAL_VAPTH_ISR: do debug for vxge core virtual path module in
+ *		ISR
+ * @VXGE_COMPONENT_HAL_CONFIG: do debug for vxge core config module
+ * @VXGE_COMPONENT_HAL_MM: do debug for vxge core memory module
+ * @VXGE_COMPONENT_HAL_POOL: do debug for vxge core memory pool module
+ * @VXGE_COMPONENT_HAL_QUEUE: do debug for vxge core queue module
+ * @VXGE_COMPONENT_HAL_BITMAP: do debug for vxge core BITMAP module
+ * @VXGE_COMPONENT_HAL_CHANNEL: do debug for vxge core channel module
+ * @VXGE_COMPONENT_HAL_FIFO: do debug for vxge core fifo module
+ * @VXGE_COMPONENT_HAL_RING: do debug for vxge core ring module
+ * @VXGE_COMPONENT_HAL_DMQ: do debug for vxge core DMQ module
+ * @VXGE_COMPONENT_HAL_UMQ: do debug for vxge core UMQ module
+ * @VXGE_COMPONENT_HAL_SQ: do debug for vxge core SQ module
+ * @VXGE_COMPONENT_HAL_SRQ: do debug for vxge core SRQ module
+ * @VXGE_COMPONENT_HAL_CQRQ: do debug for vxge core CRQ module
+ * @VXGE_COMPONENT_HAL_NCE: do debug for vxge core NCE module
+ * @VXGE_COMPONENT_HAL_STAG: do debug for vxge core STAG module
+ * @VXGE_COMPONENT_HAL_TCP: do debug for vxge core TCP module
+ * @VXGE_COMPONENT_HAL_LRO: do debug for vxge core LRO module
+ * @VXGE_COMPONENT_HAL_SPDM: do debug for vxge core SPDM module
+ * @VXGE_COMPONENT_HAL_SESSION: do debug for vxge core SESSION module
+ * @VXGE_COMPONENT_HAL_STATS: do debug for vxge core statistics module
+ * @VXGE_COMPONENT_HAL_MRPCIM: do debug for vxge KMA core mrpcim module
+ * @VXGE_COMPONENT_HAL_SRPCIM: do debug for vxge KMA core srpcim module
+ * @VXGE_COMPONENT_OSDEP: do debug for vxge KMA os dependent parts
+ * @VXGE_COMPONENT_LL: do debug for vxge link layer module
+ * @VXGE_COMPONENT_ULD: do debug for vxge upper layer driver
+ * @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions
+ *
+ * This enumeration going to be used to distinguish modules
+ * or libraries during compilation and runtime.  Makefile must declare
+ * VXGE_DEBUG_MODULE_MASK macro and set it to proper value.
+ */
+#define	VXGE_COMPONENT_HAL_DEVICE			0x00000001
+#define	VXGE_COMPONENT_HAL_DEVICE_IRQ			0x00000002
+#define	VXGE_COMPONENT_HAL_VPATH			0x00000004
+#define	VXGE_COMPONENT_HAL_VPATH_IRQ			0x00000008
+#define	VXGE_COMPONENT_HAL_CONFIG			0x00000010
+#define	VXGE_COMPONENT_HAL_MM				0x00000020
+#define	VXGE_COMPONENT_HAL_POOL				0x00000040
+#define	VXGE_COMPONENT_HAL_QUEUE			0x00000080
+#define	VXGE_COMPONENT_HAL_BITMAP			0x00000100
+#define	VXGE_COMPONENT_HAL_CHANNEL			0x00000200
+#define	VXGE_COMPONENT_HAL_FIFO				0x00000400
+#define	VXGE_COMPONENT_HAL_RING				0x00000800
+#define	VXGE_COMPONENT_HAL_DMQ				0x00001000
+#define	VXGE_COMPONENT_HAL_UMQ				0x00002000
+#define	VXGE_COMPONENT_HAL_SQ				0x00004000
+#define	VXGE_COMPONENT_HAL_SRQ				0x00008000
+#define	VXGE_COMPONENT_HAL_CQRQ				0x00010000
+#define	VXGE_COMPONENT_HAL_NCE				0x00020000
+#define	VXGE_COMPONENT_HAL_STAG				0x00040000
+#define	VXGE_COMPONENT_HAL_TCP				0x00080000
+#define	VXGE_COMPONENT_HAL_LRO				0x00100000
+#define	VXGE_COMPONENT_HAL_SPDM				0x00200000
+#define	VXGE_COMPONENT_HAL_SESSION			0x00400000
+#define	VXGE_COMPONENT_HAL_STATS			0x00800000
+#define	VXGE_COMPONENT_HAL_MRPCIM			0x01000000
+#define	VXGE_COMPONENT_HAL_MRPCIM_IRQ			0x02000000
+#define	VXGE_COMPONENT_HAL_SRPCIM			0x04000000
+#define	VXGE_COMPONENT_HAL_SRPCIM_IRQ			0x08000000
+#define	VXGE_COMPONENT_HAL_DRIVER			0x10000000
+
+/* space for CORE_XXX */
+#define	VXGE_COMPONENT_OSDEP				0x20000000
+#define	VXGE_COMPONENT_LL				0x40000000
+#define	VXGE_COMPONENT_ULD				0x80000000
+#define	VXGE_COMPONENT_ALL				0xffffffff
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_DEBUG_H */
diff --git a/sys/dev/vxge/include/vxge-defs.h b/sys/dev/vxge/include/vxge-defs.h
new file mode 100644
index 000000000000..a533a903211e
--- /dev/null
+++ b/sys/dev/vxge/include/vxge-defs.h
@@ -0,0 +1,251 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_DEFS_H
+#define	VXGE_DEFS_H
+
+#define	VXGE_PCI_VENDOR_ID			0x17D5
+#define	VXGE_PCI_DEVICE_ID_TITAN_1		0x5833
+#define	VXGE_PCI_REVISION_TITAN_1		1
+#define	VXGE_PCI_DEVICE_ID_TITAN_1A		0x5833
+#define	VXGE_PCI_REVISION_TITAN_1A		2
+#define	VXGE_PCI_DEVICE_ID_TITAN_2		0x5834
+#define	VXGE_PCI_REVISION_TITAN_2		1
+
+#define	VXGE_MIN_FW_MAJOR_VERSION		1
+#define	VXGE_MIN_FW_MINOR_VERSION		8
+#define	VXGE_MIN_FW_BUILD_NUMBER		1
+
+#define	VXGE_DRIVER_VENDOR			"Exar Corp."
+#define	VXGE_CHIP_FAMILY			"X3100"
+#define	VXGE_SUPPORTED_MEDIA_0			"Fiber"
+
+#define	VXGE_DRIVER_NAME			\
+	"Neterion X3100 10GbE PCIe Server Adapter Driver"
+/*
+ * mBIT(loc) - set bit at offset
+ */
+#define	mBIT(loc)		(0x8000000000000000ULL >> (loc))
+
+/*
+ * vBIT(val, loc, sz) - set bits at offset
+ */
+#define	vBIT(val, loc, sz)	(((u64)(val)) << (64-(loc)-(sz)))
+#define	vBIT32(val, loc, sz)	(((u32)(val)) << (32-(loc)-(sz)))
+
+/*
+ * bVALx(bits, loc) - Get the value of x bits at location
+ */
+#define	bVAL1(bits, loc)  ((((u64)bits) >> (64-(loc+1))) & 0x1)
+#define	bVAL2(bits, loc)  ((((u64)bits) >> (64-(loc+2))) & 0x3)
+#define	bVAL3(bits, loc)  ((((u64)bits) >> (64-(loc+3))) & 0x7)
+#define	bVAL4(bits, loc)  ((((u64)bits) >> (64-(loc+4))) & 0xF)
+#define	bVAL5(bits, loc)  ((((u64)bits) >> (64-(loc+5))) & 0x1F)
+#define	bVAL6(bits, loc)  ((((u64)bits) >> (64-(loc+6))) & 0x3F)
+#define	bVAL7(bits, loc)  ((((u64)bits) >> (64-(loc+7))) & 0x7F)
+#define	bVAL8(bits, loc)  ((((u64)bits) >> (64-(loc+8))) & 0xFF)
+#define	bVAL9(bits, loc)  ((((u64)bits) >> (64-(loc+9))) & 0x1FF)
+#define	bVAL11(bits, loc) ((((u64)bits) >> (64-(loc+11))) & 0x7FF)
+#define	bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF)
+#define	bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF)
+#define	bVAL15(bits, loc) ((((u64)bits) >> (64-(loc+15))) & 0x7FFF)
+#define	bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF)
+#define	bVAL17(bits, loc) ((((u64)bits) >> (64-(loc+17))) & 0x1FFFF)
+#define	bVAL18(bits, loc) ((((u64)bits) >> (64-(loc+18))) & 0x3FFFF)
+#define	bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF)
+#define	bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF)
+#define	bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF)
+#define	bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF)
+#define	bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF)
+#define	bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFFULL)
+#define	bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFFULL)
+#define	bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFFULL)
+#define	bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFFULL)
+#define	bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFFULL)
+#define	bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFFULL)
+#define	bVAL60(bits, loc)   \
+		((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFFULL)
+#define	bVAL61(bits, loc)   \
+		((((u64)bits) >> (64-(loc+61))) & 0x1FFFFFFFFFFFFFFFULL)
+
+#define	VXGE_HAL_VPATH_BMAP_START	47
+#define	VXGE_HAL_VPATH_BMAP_END		63
+
+#define	VXGE_HAL_ALL_FOXES		0xFFFFFFFFFFFFFFFFULL
+
+#define	VXGE_HAL_INTR_MASK_ALL		0xFFFFFFFFFFFFFFFFULL
+
+#define	VXGE_HAL_MAX_VIRTUAL_PATHS	17
+
+#define	VXGE_HAL_MAX_FUNCTIONS		8
+
+#define	VXGE_HAL_MAX_ITABLE_ENTRIES	256
+
+#define	VXGE_HAL_MAX_RSS_KEY_SIZE	40
+
+#define	VXGE_HAL_MAC_MAX_WIRE_PORTS	2
+
+#define	VXGE_HAL_MAC_SWITCH_PORT	2
+
+#define	VXGE_HAL_MAC_MAX_AGGR_PORTS	2
+
+#define	VXGE_HAL_MAC_MAX_PORTS		3
+
+#define	VXGE_HAL_INTR_ALARM		(1<<4)
+
+#define	VXGE_HAL_INTR_TX		(1<<(3-VXGE_HAL_VPATH_INTR_TX))
+
+#define	VXGE_HAL_INTR_RX		(1<<(3-VXGE_HAL_VPATH_INTR_RX))
+
+#define	VXGE_HAL_INTR_EINTA		(1<<(3-VXGE_HAL_VPATH_INTR_EINTA))
+
+#define	VXGE_HAL_INTR_BMAP		(1<<(3-VXGE_HAL_VPATH_INTR_BMAP))
+
+#define	VXGE_HAL_PCI_CONFIG_SPACE_SIZE	VXGE_OS_PCI_CONFIG_SIZE
+
+#define	VXGE_HAL_DEFAULT_32		0xffffffff
+
+#define	VXGE_HAL_DEFAULT_64		0xffffffffffffffff
+
+#define	VXGE_HAL_DUMP_BUF_SIZE		0x10000
+
+#define	VXGE_HAL_VPD_BUFFER_SIZE	128
+
+#define	VXGE_HAL_VPD_LENGTH		80
+
+/* Check whether an address is multicast. */
+#define	VXGE_HAL_IS_NULL(Address)	(Address == 0x0000000000000000ULL)
+
+/* Check whether an address is multicast. */
+#define	VXGE_HAL_IS_MULTICAST(Address)	(Address & 0x0000010000000000ULL)
+
+/* Check whether an address is broadcast. */
+#define	VXGE_HAL_IS_BROADCAST(Address)	\
+	((Address & 0x0000FFFF00000000ULL) == 0x0000FFFF00000000ULL)
+
+#define	VXGE_HAL_IS_UNICAST(Address)		\
+	(!(VXGE_HAL_IS_NULL(Address) ||		\
+	VXGE_HAL_IS_MULTICAST(Address) ||	\
+	VXGE_HAL_IS_BROADCAST(Address)))
+
+/* frames sizes */
+#define	VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE		14
+#define	VXGE_HAL_HEADER_802_2_SIZE			3
+#define	VXGE_HAL_HEADER_SNAP_SIZE			5
+#define	VXGE_HAL_HEADER_VLAN_SIZE			4
+#define	VXGE_HAL_MAC_HEADER_MAX_SIZE \
+			(VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \
+			VXGE_HAL_HEADER_802_2_SIZE + \
+			VXGE_HAL_HEADER_SNAP_SIZE)
+
+#define	VXGE_HAL_TCPIP_HEADER_MAX_SIZE			(64 + 64)
+
+/* 32bit alignments */
+
+/* A receive data corruption can occur resulting in either a single-bit or
+double-bit ECC error being flagged in the ASIC if starting offset of a
+buffer in single buffer mode is 0x2 to 0xa. Single bit ECC error will not
+lock up the card but can hide the data corruption while the double-bit ECC
+error will lock up the card. Limiting the starting offset of the buffers to
+0x0, 0x1 or to a value greater than 0xF will workaround this issue.
+VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
+buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
+aligned. The start of buffer of 0x2 will cause this problem to occur.
+To avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start
+of buffer is outside of the problem causing offsets.
+*/
+
+#define	VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN		0x12
+#define	VXGE_HAL_HEADER_802_2_SNAP_ALIGN		2
+#define	VXGE_HAL_HEADER_802_2_ALIGN			3
+#define	VXGE_HAL_HEADER_SNAP_ALIGN			1
+
+#define	VXGE_HAL_MIN_MTU				46
+#define	VXGE_HAL_MAX_MTU				9600
+#define	VXGE_HAL_DEFAULT_MTU				1500
+
+#define	VXGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE		81920
+
+#if defined(__EXTERN_BEGIN_DECLS)
+#undef __EXTERN_BEGIN_DECLS
+#endif
+
+#if defined(__EXTERN_END_DECLS)
+#undef __EXTERN_END_DECLS
+#endif
+
+#if defined(__cplusplus)
+#define	__EXTERN_BEGIN_DECLS		extern "C" {
+#define	__EXTERN_END_DECLS			}
+#else
+#define	__EXTERN_BEGIN_DECLS
+#define	__EXTERN_END_DECLS
+#endif
+
+__EXTERN_BEGIN_DECLS
+
+/* --------------------------- common stuffs ------------------------------ */
+/*
+ * VXGE_OS_DMA_REQUIRES_SYNC  - should be defined or
+ * NOT defined in the Makefile
+ */
+#define	VXGE_OS_DMA_CACHELINE_ALIGNED		0x1
+
+/*
+ * Either STREAMING or CONSISTENT should be used.
+ * The combination of both or none is invalid
+ */
+#define	VXGE_OS_DMA_STREAMING			0x2
+#define	VXGE_OS_DMA_CONSISTENT			0x4
+#define	VXGE_OS_SPRINTF_STRLEN			64
+
+/* --------------------------- common stuffs ------------------------------ */
+#ifndef	VXGE_OS_LLXFMT
+#define	VXGE_OS_LLXFMT				"%llx"
+#endif
+
+#ifndef	VXGE_OS_LLDFMT
+#define	VXGE_OS_LLDFMT				"%lld"
+#endif
+
+#ifndef	VXGE_OS_STXFMT
+#define	VXGE_OS_STXFMT				"%zx"
+#endif
+
+#ifndef	VXGE_OS_STDFMT
+#define	VXGE_OS_STDFMT				"%zd"
+#endif
+
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_DEFS_H */
diff --git a/sys/dev/vxge/include/vxge-list.h b/sys/dev/vxge/include/vxge-list.h
new file mode 100644
index 000000000000..56ad02c6e508
--- /dev/null
+++ b/sys/dev/vxge/include/vxge-list.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_LIST_H
+#define	VXGE_LIST_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * struct vxge_list_t - List item.
+ * @prev: Previous list item.
+ * @next: Next list item.
+ *
+ * Item of a bi-directional linked list.
+ */
+typedef struct vxge_list_t {
+	struct vxge_list_t		 *prev;
+	struct vxge_list_t		 *next;
+} vxge_list_t;
+
+/*
+ * vxge_list_init - Initialize linked list.
+ * @header: first element of the list (head)
+ *
+ * Initialize linked list.
+ * See also: vxge_list_t {}.
+ */
+static inline void vxge_list_init(vxge_list_t *header)
+{
+	vxge_assert(header != NULL);
+
+	header->next = header;
+	header->prev = header;
+}
+
+/*
+ * vxge_list_is_empty - Is the list empty?
+ * @header: first element of the list (head)
+ *
+ * Determine whether the bi-directional list is empty. Return '1' in
+ * case of 'empty'.
+ * See also: vxge_list_t {}.
+ */
+static inline int vxge_list_is_empty(vxge_list_t *header)
+{
+	vxge_assert(header != NULL);
+
+	return (header->next == header);
+}
+
+/*
+ * vxge_list_first_get - Return the first item from the linked list.
+ * @header: first element of the list (head)
+ *
+ * Returns the next item from the header.
+ * Returns NULL if the next item is header itself
+ * See also: vxge_list_remove(), vxge_list_insert(), vxge_list_t {}.
+ */
+static inline vxge_list_t *vxge_list_first_get(vxge_list_t *header)
+{
+	vxge_assert(header != NULL);
+	vxge_assert(header->next != NULL);
+	vxge_assert(header->prev != NULL);
+
+	if (header->next == header)
+		return (NULL);
+	else
+		return (header->next);
+}
+
+/*
+ * vxge_list_remove - Remove the specified item from the linked list.
+ * @item: element of the list
+ *
+ * Remove item from a list.
+ * See also: vxge_list_insert(), vxge_list_t {}.
+ */
+static inline void vxge_list_remove(vxge_list_t *item)
+{
+	vxge_assert(item != NULL);
+	vxge_assert(item->next != NULL);
+	vxge_assert(item->prev != NULL);
+
+	item->next->prev = item->prev;
+	item->prev->next = item->next;
+#if defined(VXGE_DEBUG_ASSERT)
+	item->next = item->prev = NULL;
+#endif
+}
+
+/*
+ * vxge_list_insert - Insert a new item after the specified item.
+ * @new_item: new element of the list
+ * @prev_item: element of the list after which the new element is
+ *		inserted
+ *
+ * Insert new item (new_item) after given item (prev_item).
+ * See also: vxge_list_remove(), vxge_list_insert_before(), vxge_list_t {}.
+ */
+static inline void vxge_list_insert(vxge_list_t *new_item,
+    vxge_list_t *prev_item)
+{
+	vxge_assert(new_item != NULL);
+	vxge_assert(prev_item != NULL);
+	vxge_assert(prev_item->next != NULL);
+
+	new_item->next = prev_item->next;
+	new_item->prev = prev_item;
+	prev_item->next->prev = new_item;
+	prev_item->next = new_item;
+}
+
+/*
+ * vxge_list_insert_before - Insert a new item before the specified item.
+ * @new_item: new element of the list
+ * @next_item: element of the list after which the new element is inserted
+ *
+ * Insert new item (new_item) before given item (next_item).
+ */
+static inline void vxge_list_insert_before(vxge_list_t *new_item,
+    vxge_list_t * next_item)
+{
+	vxge_assert(new_item != NULL);
+	vxge_assert(next_item != NULL);
+	vxge_assert(next_item->next != NULL);
+
+	new_item->next = next_item;
+	new_item->prev = next_item->prev;
+	next_item->prev->next = new_item;
+	next_item->prev = new_item;
+}
+
+#define	vxge_list_for_each(_p, _h) \
+	for (_p = (_h)->next, vxge_os_prefetch(_p->next); _p != (_h); \
+		_p = _p->next, vxge_os_prefetch(_p->next))
+
+#define	vxge_list_for_each_safe(_p, _n, _h) \
+	for (_p = (_h)->next, _n = _p->next; _p != (_h); \
+		_p = _n, _n = _p->next)
+
+#define	vxge_list_for_each_prev_safe(_p, _n, _h) \
+	for (_p = (_h)->prev, _n = _p->prev; _p != (_h); \
+		_p = _n, _n = _p->prev)
+
+#if defined(__GNUC__)
+/*
+ * vxge_container_of - Given a member, return the containing structure.
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ *
+ * Cast a member of a structure out to the containing structure.
+ */
+#define	vxge_container_of(ptr, type, member) (\
+	{ __typeof(((type *)0)->member) *__mptr = (ptr);	\
+	(type *)(void *)((char *)__mptr - ((ptr_t)&((type *)0)->member)); })
+#else
+/* type unsafe version */
+#define	vxge_container_of(ptr, type, member) \
+	((type *)(void *)((char *)(ptr) - ((ptr_t)&((type *)0)->member)))
+#endif
+
+/*
+ * vxge_offsetof - Offset of the member in the containing structure.
+ * @t:	struct name.
+ * @m:	the name of the member within the struct.
+ *
+ * Return the offset of the member @m in the structure @t.
+ */
+#define	vxge_offsetof(t, m)			((ptr_t)(&((t *)0)->m))
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_LIST_H */
diff --git a/sys/dev/vxge/include/vxge-os-debug.h b/sys/dev/vxge/include/vxge-os-debug.h
new file mode 100644
index 000000000000..1608ddbcfe96
--- /dev/null
+++ b/sys/dev/vxge/include/vxge-os-debug.h
@@ -0,0 +1,261 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_OS_DEBUG_H
+#define	VXGE_OS_DEBUG_H
+
+__EXTERN_BEGIN_DECLS
+
+#ifndef	VXGE_DEBUG_INLINE_FUNCTIONS
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+#define	vxge_trace_aux(hldev, vpid, fmt, ...)				\
+		vxge_os_vasprintf(hldev, vpid, fmt, __VA_ARGS__)
+#else
+#define	vxge_trace_aux(hldev, vpid, fmt, ...)				\
+		vxge_os_vaprintf(hldev, vpid, fmt, __VA_ARGS__)
+#endif
+
+#define	vxge_debug(module, level, hldev, vpid, fmt, ...)		\
+{									\
+	if (((u32)level <=						\
+		((vxge_hal_device_t *)hldev)->debug_level) &&		\
+	    ((u32)module &						\
+		((vxge_hal_device_t *)hldev)->debug_module_mask))	\
+			vxge_trace_aux((vxge_hal_device_h)hldev,	\
+					vpid, fmt, __VA_ARGS__);	\
+}
+
+/*
+ * vxge_debug_driver
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for OS Dependent functions. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+#if (VXGE_COMPONENT_HAL_DRIVER & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_debug_driver(level, hldev, vpid, fmt, ...)		    \
+	if ((u32)level <= g_debug_level)			    \
+		vxge_os_vaprintf((vxge_hal_device_h)hldev,	    \
+				vpid, fmt, __VA_ARGS__);
+#else
+#define	vxge_debug_driver(level, hldev, vpid, fmt, ...)
+#endif
+
+/*
+ * vxge_debug_osdep
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for OS Dependent functions. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+#if (VXGE_COMPONENT_OSDEP & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_debug_osdep(level, hldev, vpid, fmt, ...) \
+	vxge_debug(VXGE_COMPONENT_OSDEP, level, hldev, vpid, fmt, __VA_ARGS__)
+#else
+#define	vxge_debug_osdep(level, hldev, vpid, fmt, ...)
+#endif
+
+/*
+ * vxge_debug_ll
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for LL driver. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_debug_ll(level, hldev, vpid, fmt, ...) \
+	vxge_debug(VXGE_COMPONENT_LL, level, hldev, vpid, fmt, __VA_ARGS__)
+#else
+#define	vxge_debug_ll(level, hldev, vpid, fmt, ...)
+#endif
+
+/*
+ * vxge_debug_uld
+ * @component: The Component mask
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for LL driver. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+#if (VXGE_COMPONENT_ULD & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_debug_uld(component, level, hldev, vpid, fmt, ...) \
+	vxge_debug(component, level, hldev, vpid, fmt, __VA_ARGS__)
+#else
+#define	vxge_debug_uld(level, hldev, vpid, fmt, ...)
+#endif
+
+#else	/* VXGE_DEBUG_INLINE_FUNCTIONS */
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+#define	vxge_trace_aux(hldev, vpid, fmt)				\
+		vxge_os_vasprintf(hldev, vpid, fmt)
+#else
+#define	vxge_trace_aux(hldev, vpid, fmt)				\
+		vxge_os_vaprintf(hldev, vpid, fmt)
+#endif
+
+#define	vxge_debug(module, level, hldev, vpid, fmt)			    \
+{									    \
+	if (((u32)level <= ((vxge_hal_device_t *)hldev)->debug_level) &&    \
+	    ((u32)module & ((vxge_hal_device_t *)hldev)->debug_module_mask))\
+		vxge_trace_aux((vxge_hal_device_h)hldev, vpid, fmt);	    \
+}
+
+/*
+ * vxge_debug_driver
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for OS Dependent functions. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+static inline void vxge_debug_driver(
+    vxge_debug_level_e level,
+    vxge_hal_device_h hldev,
+    u32 vpid,
+    char *fmt, ...)
+{
+#if (VXGE_COMPONENT_HAL_DRIVER & VXGE_DEBUG_MODULE_MASK)
+	if ((u32) level <= g_debug_level)
+		vxge_os_vaprintf((vxge_hal_device_h) hldev, vpid, fmt);
+#endif
+}
+
+/*
+ * vxge_debug_osdep
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for OS Dependent functions. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+static inline void vxge_debug_osdep(
+    vxge_debug_level_e level,
+    vxge_hal_device_h hldev,
+    u32 vpid,
+    char *fmt, ...)
+{
+#if (VXGE_COMPONENT_OSDEP & VXGE_DEBUG_MODULE_MASK)
+	vxge_debug(VXGE_COMPONENT_OSDEP, level, hldev, vpid, fmt)
+#endif
+}
+
+/*
+ * vxge_debug_ll
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for LL driver. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+static inline void vxge_debug_ll(
+    vxge_debug_level_e level,
+    vxge_hal_device_h hldev,
+    u32 vpid,
+    char *fmt, ...)
+{
+#if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
+	vxge_debug(VXGE_COMPONENT_LL, level, hldev, vpid, fmt)
+#endif
+}
+
+/*
+ * vxge_debug_uld
+ * @component: The Component mask
+ * @level: level of debug verbosity.
+ * @hldev: HAL Device
+ * @vpid: Vpath id
+ * @fmt: printf like format string
+ *
+ * Provides logging facilities for LL driver. Can be customized
+ * with debug levels. Input parameters, except level, are the same
+ * as posix printf. This function may be compiled out if DEBUG macro
+ * was never defined.
+ * See also: vxge_debug_level_e{}.
+ */
+static inline void vxge_debug_uld(
+    u32 component,
+    vxge_debug_level_e level,
+    vxge_hal_device_h hldev,
+    u32 vpid,
+    char *fmt, ...)
+{
+#if (VXGE_COMPONENT_ULD & VXGE_DEBUG_MODULE_MASK)
+	vxge_debug(component, level, hldev, vpid, fmt)
+#endif
+}
+
+#endif	/* end of VXGE_DEBUG_INLINE_FUNCTIONS */
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_OS_DEBUG_H */
diff --git a/sys/dev/vxge/include/vxge-os-pal.h b/sys/dev/vxge/include/vxge-os-pal.h
new file mode 100644
index 000000000000..32a64dfeb4fb
--- /dev/null
+++ b/sys/dev/vxge/include/vxge-os-pal.h
@@ -0,0 +1,80 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_OS_PAL_H
+#define	VXGE_OS_PAL_H
+
+__EXTERN_BEGIN_DECLS
+
+/* --------------------------- platform switch ------------------------------ */
+
+/* platform specific header */
+#include <dev/vxge/vxge-osdep.h>
+#define	IN
+#define	OUT
+
+#if !defined(VXGE_OS_PLATFORM_64BIT) && !defined(VXGE_OS_PLATFORM_32BIT)
+#error "either 32bit or 64bit switch must be defined!"
+#endif
+
+#if !defined(VXGE_OS_HOST_BIG_ENDIAN) && !defined(VXGE_OS_HOST_LITTLE_ENDIAN)
+#error "either little endian or big endian switch must be defined!"
+#endif
+
+#if defined(VXGE_OS_PLATFORM_64BIT)
+#define	VXGE_OS_MEMORY_DEADCODE_PAT		0x5a5a5a5a5a5a5a5a
+#else
+#define	VXGE_OS_MEMORY_DEADCODE_PAT		0x5a5a5a5a
+#endif
+
+#if defined(VXGE_DEBUG_ASSERT)
+
+/*
+ * vxge_assert
+ * @test: C-condition to check
+ * @fmt: printf like format string
+ *
+ * This function implements traditional assert. By default assertions
+ * are enabled. It can be disabled by defining VXGE_DEBUG_ASSERT macro in
+ * compilation
+ * time.
+ */
+#define	vxge_assert(test) { \
+	if (!(test)) vxge_os_bug("bad cond: "#test" at %s:%d\n", \
+	__FILE__, __LINE__); }
+#else
+#define	vxge_assert(test)
+#endif	/* end of VXGE_DEBUG_ASSERT */
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_OS_PAL_H */
diff --git a/sys/dev/vxge/include/vxge-queue.h b/sys/dev/vxge/include/vxge-queue.h
new file mode 100644
index 000000000000..2ff5e220b4a6
--- /dev/null
+++ b/sys/dev/vxge/include/vxge-queue.h
@@ -0,0 +1,312 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_QUEUE_H
+#define	VXGE_QUEUE_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	VXGE_QUEUE_BUF_SIZE				0x1000
+#define	VXGE_DEFAULT_EVENT_MAX_DATA_SIZE		16
+
+/*
+ * enum vxge_queue_status_e - Enumerates return codes of the vxge_queue
+ * manipulation APIs.
+ * @VXGE_QUEUE_IS_FULL: Queue is full, need to grow.
+ * @VXGE_QUEUE_IS_EMPTY: Queue is empty.
+ * @VXGE_QUEUE_OUT_OF_MEMORY: Out of memory.
+ * @VXGE_QUEUE_NOT_ENOUGH_SPACE: Exceeded specified event size,
+ * see vxge_queue_consume().
+ * @VXGE_QUEUE_OK: Neither one of the codes listed above.
+ *
+ * Enumerates return codes of vxge_queue_consume()
+ * and vxge_queue_produce() APIs.
+ */
+typedef enum vxge_queue_status_e {
+	VXGE_QUEUE_OK			= 0,
+	VXGE_QUEUE_IS_FULL		= 1,
+	VXGE_QUEUE_IS_EMPTY		= 2,
+	VXGE_QUEUE_OUT_OF_MEMORY	= 3,
+	VXGE_QUEUE_NOT_ENOUGH_SPACE	= 4
+} vxge_queue_status_e;
+
+typedef void *vxge_queue_h;
+
+/*
+ * struct vxge_queue_item_t - Queue item.
+ * @item: List item. Note that the queue is "built" on top of
+ *	the bi-directional linked list.
+ * @event_type: Event type. Includes (but is not restricted to)
+ * one of the vxge_hal_event_e {} enumerated types.
+ * @data_size: Size of the enqueued user data. Note that vxge_queue_t
+ * items are allowed to have variable sizes.
+ * @is_critical: For critical events, e.g. ECC.
+ * @context: Opaque (void *) "context", for instance event producer object.
+ *
+ * Item of the vxge_queue_t {}. The queue is protected
+ * in terms of multi-threaded concurrent access.
+ * See also: vxge_queue_t {}.
+ */
+typedef struct vxge_queue_item_t {
+	vxge_list_t		item;
+	vxge_hal_event_e	event_type;
+	u32			data_size;
+	u32			is_critical;
+	void			*context;
+} vxge_queue_item_t;
+
+/*
+ * function vxge_queued_f - Item-enqueued callback.
+ * @data: Per-queue context independent of the event. E.g., device handle.
+ * @event_type: HAL or ULD-defined event type. Note that HAL own
+ *	events are enumerated by vxge_hal_event_e {}.
+ *
+ * Per-queue optional callback. If not NULL, called by HAL each
+ * time an event gets added to the queue.
+ */
+typedef void (*vxge_queued_f) (void *data, u32 event_type);
+
+/*
+ * struct vxge_queue_t - Protected dynamic queue of variable-size items.
+ * @start_ptr: Points to the start of the queue.
+ * @end_ptr: Points to the end of the queue.
+ * @head_ptr: Points to the head of the queue. It gets changed during queue
+ *	   produce/consume operations.
+ * @tail_ptr: Points to the tail of the queue. It gets changed during queue
+ *	   produce/consume operations.
+ * @lock: Lock for queue operations(syncronization purpose).
+ * @pages_initial:Number of pages to be initially allocated at the time
+ *		 of queue creation.
+ * @pages_max: Max number of pages that can be allocated in the queue.
+ * @pages_current: Number of pages currently allocated
+ * @list_head: Points to the list of queue elements that are produced, but yet
+ *		to be consumed.
+ * @hldev: HAL device handle
+ * @pdev: PCI device handle
+ * @irqh: PCI device IRQ handle.
+ * @queued_func: Optional callback function to be called each time a new
+ * item is added to the queue.
+ * @queued_data: Arguments to the callback function.
+ * @has_critical_event: Non-zero, if the queue contains a critical event,
+ * see vxge_hal_event_e {}.
+ * Protected dynamically growing queue. The queue is used to support multiple
+ * producer/consumer type scenarios. The queue is a strict FIFO: first come
+ * first served.
+ * Queue users may "produce" (see vxge_queue_produce()) and "consume"
+ * (see vxge_queue_consume()) items (a.k.a. events) variable sizes.
+ * See also: vxge_queue_item_t {}.
+ */
+typedef struct vxge_queue_t {
+	void			*start_ptr;
+	void			*end_ptr;
+	void			*head_ptr;
+	void			*tail_ptr;
+	spinlock_t		lock;
+	u32			pages_initial;
+	u32			pages_max;
+	u32			pages_current;
+	vxge_list_t		list_head;
+	vxge_hal_device_h	hldev;
+	pci_dev_h		pdev;
+	pci_irq_h		irqh;
+	vxge_queued_f		queued_func;
+	void			*queued_data;
+	u32			has_critical_event;
+} vxge_queue_t;
+
+/* ========================== PUBLIC API ================================= */
+
+/*
+ * vxge_queue_create - Create protected first-in-first-out queue.
+ * @devh: HAL device handle.
+ * @pages_initial: Number of pages to be initially allocated at the
+ * time of queue creation.
+ * @pages_max: Max number of pages that can be allocated in the queue.
+ * @queued_func: Optional callback function to be called each time a new item is
+ * added to the queue.
+ * @queued_data: Argument to the callback function.
+ *
+ * Create protected (fifo) queue.
+ *
+ * Returns: Pointer to vxge_queue_t structure,
+ * NULL - on failure.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_destroy().
+ */
+vxge_queue_h
+vxge_queue_create(vxge_hal_device_h devh,
+    u32 pages_initial,
+    u32 pages_max,
+    vxge_queued_f queued_func,
+    void *queued_data);
+
+/*
+ * vxge_queue_destroy - Destroy vxge_queue_t object.
+ * @queueh: Queue handle.
+ *
+ * Destroy the specified vxge_queue_t object.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_create().
+ */
+void
+vxge_queue_destroy(vxge_queue_h queueh);
+
+/*
+ * vxge_queue_item_data - Get item's data.
+ * @item: Queue item.
+ *
+ * Returns:  item data(variable size). Note that vxge_queue_t
+ * contains items comprized of a fixed vxge_queue_item_t "header"
+ * and a variable size data. This function returns the variable
+ * user-defined portion of the queue item.
+ */
+void *
+vxge_queue_item_data(vxge_queue_item_t *item);
+
+/*
+ * vxge_queue_produce - Enqueue an item (see vxge_queue_item_t {})
+ *			 into the specified queue.
+ * @queueh: Queue handle.
+ * @event_type: Event type. One of the enumerated event types
+ *		 that both consumer and producer "understand".
+ *		 For an example, please refer to vxge_hal_event_e.
+ * @context: Opaque (void *) "context", for instance event producer object.
+ * @is_critical: For critical event, e.g. ECC.
+ * @data_size: Size of the @data.
+ * @data: User data of variable @data_size that is _copied_ into
+ *	the new queue item (see vxge_queue_item_t {}). Upon return
+ *	from the call the @data memory can be re-used or released.
+ *
+ * Enqueue a new item.
+ *
+ * Returns: VXGE_QUEUE_OK - success.
+ * VXGE_QUEUE_IS_FULL - Queue is full.
+ * VXGE_QUEUE_OUT_OF_MEMORY - Memory allocation failed.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_consume().
+ */
+vxge_queue_status_e
+vxge_queue_produce(vxge_queue_h queueh,
+    u32 event_type,
+    void *context,
+    u32 is_critical,
+    const u32 data_size,
+    void *data);
+
+/*
+ * vxge_queue_produce_context - Enqueue context.
+ * @queueh: Queue handle.
+ * @event_type: Event type. One of the enumerated event types
+ *		 that both consumer and producer "understand".
+ *		 For an example, please refer to vxge_hal_event_e.
+ * @context: Opaque (void *) "context", for instance event producer object.
+ *
+ * Enqueue Context.
+ *
+ * Returns: VXGE_QUEUE_OK - success.
+ * VXGE_QUEUE_IS_EMPTY - Queue is empty.
+ * VXGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size)
+ * is too small to accomodate an item from the queue.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_produce().
+ */
+static inline vxge_queue_status_e
+/* LINTED */
+vxge_queue_produce_context(vxge_queue_h queueh,
+    u32 event_type,
+    void *context)
+{
+	return (vxge_queue_produce(queueh, event_type, context, 0, 0, 0));
+}
+
+/*
+ * vxge_queue_consume - Dequeue an item from the specified queue.
+ * @queueh: Queue handle.
+ * @data_max_size: Maximum expected size of the item.
+ * @item: Memory area into which the item is _copied_ upon return
+ *	from the function.
+ *
+ * Dequeue an item from the queue. The caller is required to provide
+ * enough space for the item.
+ *
+ * Returns: VXGE_QUEUE_OK - success.
+ * VXGE_QUEUE_IS_EMPTY - Queue is empty.
+ * VXGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size)
+ * is too small to accomodate an item from the queue.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_produce().
+ */
+vxge_queue_status_e
+vxge_queue_consume(vxge_queue_h queueh,
+    u32 data_max_size,
+    vxge_queue_item_t *item);
+
+/*
+ * vxge_queue_flush - Flush, or empty, the queue.
+ * @queueh: Queue handle.
+ *
+ * Flush the queue, i.e. make it empty by consuming all events
+ * without invoking the event processing logic (callbacks, etc.)
+ */
+void
+vxge_queue_flush(vxge_queue_h queueh);
+
+/*
+ * vxge_io_queue_grow - Dynamically increases the size of the queue.
+ * @queueh: Queue handle.
+ *
+ * This function is called in the case of no slot avaialble in the queue
+ * to accomodate the newly received event.
+ * Note that queue cannot grow beyond the max size specified for the
+ * queue.
+ *
+ * Returns VXGE_QUEUE_OK: On success.
+ * VXGE_QUEUE_OUT_OF_MEMORY : No memory is available.
+ */
+vxge_queue_status_e
+vxge_io_queue_grow(vxge_queue_h qh);
+
+/*
+ * vxge_queue_get_reset_critical - Check for critical events in the queue,
+ * @queueh: Queue handle.
+ *
+ * Check for critical event(s) in the queue, and reset the
+ * "has-critical-event" flag upon return.
+ * Returns: 1 - if the queue contains atleast one critical event.
+ * 0 - If there are no critical events in the queue.
+ */
+u32
+vxge_queue_get_reset_critical(vxge_queue_h queueh);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_QUEUE_H */
diff --git a/sys/dev/vxge/include/vxgehal-config.h b/sys/dev/vxge/include/vxgehal-config.h
new file mode 100644
index 000000000000..f2d8ed363f77
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-config.h
@@ -0,0 +1,2564 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_CONFIG_H
+#define	VXGE_HAL_CONFIG_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	VXGE_HAL_USE_FLASH_DEFAULT			VXGE_HAL_DEFAULT_32
+
+#define	VXGE_HAL_MAX_INTR_PER_VP			4
+
+#define	VXGE_HAL_VPATH_MSIX_MAX				4
+
+#define	VXGE_HAL_VPATH_INTR_TX				0
+
+#define	VXGE_HAL_VPATH_INTR_RX				1
+
+#define	VXGE_HAL_VPATH_INTR_EINTA			2
+
+#define	VXGE_HAL_VPATH_INTR_BMAP			3
+
+#define	WAIT_FACTOR					1
+/*
+ * struct vxge_hal_driver_config_t - HAL driver object configuration.
+ *
+ * @level: Debug Level. See vxge_debug_level_e {}
+ *
+ * Currently this structure contains just a few basic values.
+ */
+typedef struct vxge_hal_driver_config_t {
+	vxge_debug_level_e level;
+} vxge_hal_driver_config_t;
+
+/*
+ * struct vxge_hal_wire_port_config_t - Wire Port configuration (Physical ports)
+ * @port_id: Port number
+ * @media: Transponder type.
+ * @mtu: mtu size used on this port.
+ * @autoneg_mode: The device supports several mechanisms to auto-negotiate the
+ *		port data rate. The Fixed mode essentially means no
+ *		auto-negotiation and the data rate is determined by the RATE
+ *		field of this register. The MDIO-based mode determines the data
+ *		rate by reading MDIO registers in the external PHY chip. The
+ *		Backplane Ethernet mode using parallel detect and/or
+ *		DME-signaled exchange of page information with the PHY chip in
+ *		order to figure out the proper rate.
+ *		00 - Fixed
+ *		01 - MDIO-based
+ *		10 - Backplane Ethernet
+ *		11 - Reserved
+ * @autoneg_rate: When MODE is set to Fixed, then this field determines the data
+ *		rate of the port.
+ *		0 - 1G
+ *		1 - 10G
+ * @fixed_use_fsm: When MODE is set to Fixed, then this field determines whether
+ *		a processor (i.e. F/W or host driver) or hardware-based state
+ *		machine is used to run the auto-negotiation.
+ *		0 - Use processor. Either on-chip F/W or host-based driver used.
+ *		1 - Use H/W state machine
+ * @antp_use_fsm: When MODE is set to ANTP (Auto-Negotiation for Twisted Pair),
+ *		this field determines whether a processor (F/W or host driver)
+ *		or hardware-based state machine is used to talk to the PHY chip
+ *		via the MDIO interface.
+ *		0 - Use processor. Either on-chip F/W or host-based driver used.
+ *		1 - Use H/W state machine
+ * @anbe_use_fsm: When MODE is set to ANBE-based, then this field determines
+ *		whether a processor (i.e. F/W or host driver) or hardware-based
+ *		state machine is used to talk to the Backplane Ethernet logic
+ *		inside the device
+ *		0 - Use processor. Either on-chip F/W or host-based driver used.
+ *		1 - Use H/W state machine
+ * @link_stability_period: Timeout for the link stability
+ * @port_stability_period: Timeout for the port stability
+ * @tmac_en: TMAC enable. 0 - Disable; 1 - Enable
+ * @rmac_en: RMAC enable. 0 - Disable; 1 - Enable
+ * @tmac_pad: Determines whether padding is appended to transmitted frames.
+ *		0 - No padding appended
+ *		1 - Pad to 64 bytes (not including preamble/SFD)
+ * @tmac_pad_byte: The byte that is used to pad
+ * @tmac_util_period: The sampling period over which the transmit utilization
+ *		   is calculated.
+ * @rmac_strip_fcs: Determines whether FCS of received frames is removed by the
+ *		MAC or sent to the host.
+ *		0 - Send FCS to host.
+ *		1 - FCS removed by MAC.
+ * @rmac_prom_en: Enable/Disable promiscuous mode. In promiscuous mode all
+ *		received frames are passed to the host. PROM_EN overrules the
+ *		configuration determined by the UCAST_ALL_ADDR_EN,
+ *		MCAST_ALL_ADDR_EN and ALL_VID_EN fields of RXMAC_VCFG, as well
+ *		as the configurable discard fields in RMAC_ERR_CFG_PORTn.
+ *		Note: PROM_EN does not overrule DISCARD_PFRM (i.e. discard of
+ *		pause frames by receive MAC is controlled solely by
+ *		DISCARD_PFRM).
+ *		0 - Disable
+ *		1 - Enable
+ * @rmac_discard_pfrm: Determines whether received pause frames are discarded at
+ *		the receive MAC or passed to the host.
+ *		Note: Other MAC control frames are always passed to the host.
+ *		0 - Send to host.
+ *		1 - Pause frames discarded by MAC.
+ * @rmac_util_period: The sampling period over which the receive utilization
+ *		   is calculated.
+ * @rmac_strip_pad: Determines whether padding of received frames is removed by
+ *		 the MAC or sent to the host.
+ * @rmac_bcast_en: Enable frames containing broadcast address to be
+ *		passed to the host.
+ * @rmac_pause_gen_en: Received pause generation enable.
+ * @rmac_pause_rcv_en: Receive pause enable.
+ * @rmac_pause_time: The value to be inserted in outgoing pause frames.
+ *		Has units of pause quanta (one pause quanta = 512 bit times).
+ * @limiter_en: Enables logic that limits the contribution that any one receive
+ *		queue can have on the transmission of pause frames. This avoids
+ *		a situation where the adapter will permanently send pause frames
+ *		due to a receive VPATH that is either undergoing a long reset or
+ *		is in a dead state.
+ *		0 - Don't limit the contribution of any queue. If any queue's
+ *		fill level sits above the high threshold, then a pause frame
+ *		is sent.
+ *		1 - Place a cap on the number of pause frames that are sent
+ *		because any one queue has crossed its high threshold.
+ *		See MAX_LIMIT for more details.
+ * @max_limit: Contains the value that is loaded into the per-queue limiting
+ *		counters that exist in the flow control logic. Essentially,
+ *		this represents the maximum number of pause frames that are sent
+ *		due to any one particular queue having crossed its high
+ *		threshold. Each counter is set to this max limit the first time
+ *		the corresponding queue's high threshold is crossed. The counter
+ *		decrements each time the queue remains above the high threshold
+ *		and the adapter requests pause frame transmission. Once the
+ *		counter expires that queue no longer contributes to pause frame
+ *		transmission requests. The queue's fill level must drop below
+ *		the low pause threshold before it is once again allowed to
+ *		contribute. Note: This field is only used when LIMITER_EN is set
+ *		to 1.
+ *
+ * Wire Port Configuration
+ */
+typedef struct vxge_hal_wire_port_config_t {
+
+		u32				port_id;
+#define	VXGE_HAL_WIRE_PORT_PORT0				0
+#define	VXGE_HAL_WIRE_PORT_PORT1				1
+#define	VXGE_HAL_WIRE_PORT_MAX_PORTS		    VXGE_HAL_MAC_MAX_WIRE_PORTS
+
+		u32				media;
+#define	VXGE_HAL_WIRE_PORT_MIN_MEDIA				0
+#define	VXGE_HAL_WIRE_PORT_MEDIA_SR				0
+#define	VXGE_HAL_WIRE_PORT_MEDIA_SW				1
+#define	VXGE_HAL_WIRE_PORT_MEDIA_LR				2
+#define	VXGE_HAL_WIRE_PORT_MEDIA_LW				3
+#define	VXGE_HAL_WIRE_PORT_MEDIA_ER				4
+#define	VXGE_HAL_WIRE_PORT_MEDIA_EW				5
+#define	VXGE_HAL_WIRE_PORT_MAX_MEDIA				5
+#define	VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				mtu;
+#define	VXGE_HAL_WIRE_PORT_MIN_INITIAL_MTU	    VXGE_HAL_MIN_MTU
+#define	VXGE_HAL_WIRE_PORT_MAX_INITIAL_MTU	    VXGE_HAL_MAX_MTU
+#define	VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				autoneg_mode;
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_MODE_FIXED			0
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_MODE_ANTP			1
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_MODE_ANBE			2
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_MODE_RESERVED		3
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				autoneg_rate;
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_RATE_1G			0
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_RATE_10G			1
+#define	VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				fixed_use_fsm;
+#define	VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_PROCESSOR		0
+#define	VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_HW			1
+#define	VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				antp_use_fsm;
+#define	VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_PROCESSOR		0
+#define	VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_HW			1
+#define	VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				anbe_use_fsm;
+#define	VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_PROCESSOR		0
+#define	VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_HW			1
+#define	VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				link_stability_period;
+#define	VXGE_HAL_WIRE_PORT_MIN_LINK_STABILITY_PERIOD		0x0 /* 0s */
+#define	VXGE_HAL_WIRE_PORT_MAX_LINK_STABILITY_PERIOD		0xF /* 2s */
+#define	VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				port_stability_period;
+#define	VXGE_HAL_WIRE_PORT_MIN_PORT_STABILITY_PERIOD		0x0 /* 0s */
+#define	VXGE_HAL_WIRE_PORT_MAX_PORT_STABILITY_PERIOD		0xF /* 2s */
+#define	VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_en;
+#define	VXGE_HAL_WIRE_PORT_TMAC_ENABLE				1
+#define	VXGE_HAL_WIRE_PORT_TMAC_DISABLE				0
+#define	VXGE_HAL_WIRE_PORT_TMAC_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_en;
+#define	VXGE_HAL_WIRE_PORT_RMAC_ENABLE				1
+#define	VXGE_HAL_WIRE_PORT_RMAC_DISABLE				0
+#define	VXGE_HAL_WIRE_PORT_RMAC_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_pad;
+#define	VXGE_HAL_WIRE_PORT_TMAC_NO_PAD				0
+#define	VXGE_HAL_WIRE_PORT_TMAC_64B_PAD				1
+#define	VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_pad_byte;
+#define	VXGE_HAL_WIRE_PORT_MIN_TMAC_PAD_BYTE			0
+#define	VXGE_HAL_WIRE_PORT_MAX_TMAC_PAD_BYTE			255
+#define	VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_util_period;
+#define	VXGE_HAL_WIRE_PORT_MIN_TMAC_UTIL_PERIOD			0
+#define	VXGE_HAL_WIRE_PORT_MAX_TMAC_UTIL_PERIOD			15
+#define	VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_strip_fcs;
+#define	VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS			1
+#define	VXGE_HAL_WIRE_PORT_RMAC_SEND_FCS_TO_HOST		0
+#define	VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_prom_en;
+#define	VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_ENABLE			1
+#define	VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DISABLE			0
+#define	VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_discard_pfrm;
+#define	VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM			1
+#define	VXGE_HAL_WIRE_PORT_RMAC_SEND_PFRM_TO_HOST		0
+#define	VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_util_period;
+#define	VXGE_HAL_WIRE_PORT_MIN_RMAC_UTIL_PERIOD			0
+#define	VXGE_HAL_WIRE_PORT_MAX_RMAC_UTIL_PERIOD			15
+#define	VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_pause_gen_en;
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_ENABLE		1
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DISABLE		0
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_pause_rcv_en;
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_ENABLE		1
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DISABLE		0
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_pause_time;
+#define	VXGE_HAL_WIRE_PORT_MIN_RMAC_HIGH_PTIME			16
+#define	VXGE_HAL_WIRE_PORT_MAX_RMAC_HIGH_PTIME			65535
+#define	VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				limiter_en;
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_ENABLE		1
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DISABLE		0
+#define	VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				max_limit;
+#define	VXGE_HAL_WIRE_PORT_MIN_RMAC_MAX_LIMIT			0
+#define	VXGE_HAL_WIRE_PORT_MAX_RMAC_MAX_LIMIT			255
+#define	VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_wire_port_config_t;
+
+/*
+ * struct vxge_hal_switch_port_config_t - Switch Port configuration(vm-vm port)
+ * @mtu: mtu size used on this port.
+ * @tmac_en: TMAC enable. 0 - Disable; 1 - Enable
+ * @rmac_en: RMAC enable. 0 - Disable; 1 - Enable
+ * @tmac_pad: Determines whether padding is appended to transmitted frames.
+ *		0 - No padding appended
+ *		1 - Pad to 64 bytes (not including preamble/SFD)
+ * @tmac_pad_byte: The byte that is used to pad
+ * @tmac_util_period: The sampling period over which the transmit utilization
+ *		   is calculated.
+ * @rmac_strip_fcs: Determines whether FCS of received frames is removed by the
+ *		MAC or sent to the host.
+ *		0 - Send FCS to host.
+ *		1 - FCS removed by MAC.
+ * @rmac_prom_en: Enable/Disable promiscuous mode. In promiscuous mode all
+ *		received frames are passed to the host. PROM_EN overrules the
+ *		configuration determined by the UCAST_ALL_ADDR_EN,
+ *		MCAST_ALL_ADDR_EN and ALL_VID_EN fields of RXMAC_VCFG, as well
+ *		as the configurable discard fields in RMAC_ERR_CFG_PORTn.
+ *		Note: PROM_EN does not overrule DISCARD_PFRM (i.e. discard of
+ *		pause frames by receive MAC is controlled solely by
+ *              DISCARD_PFRM).
+ *		0 - Disable
+ *		1 - Enable
+ * @rmac_discard_pfrm: Determines whether received pause frames are discarded at
+ *		the receive MAC or passed to the host.
+ *		Note: Other MAC control frames are always passed to the host.
+ *		0 - Send to host.
+ *		1 - Pause frames discarded by MAC.
+ * @rmac_util_period: The sampling period over which the receive utilization
+ *		   is calculated.
+ * @rmac_strip_pad: Determines whether padding of received frames is removed by
+ *		 the MAC or sent to the host.
+ * @rmac_bcast_en: Enable frames containing broadcast address to be
+ *		passed to the host.
+ * @rmac_pause_gen_en: Received pause generation enable.
+ * @rmac_pause_rcv_en: Receive pause enable.
+ * @rmac_pause_time: The value to be inserted in outgoing pause frames.
+ *		Has units of pause quanta (one pause quanta = 512 bit times).
+ * @limiter_en: Enables logic that limits the contribution that any one receive
+ *		queue can have on the transmission of pause frames. This avoids
+ *		a situation where the adapter will permanently send pause frames
+ *		due to a receive VPATH that is either undergoing a long reset or
+ *		is in a dead state.
+ *		0 - Don't limit the contribution of any queue. If any queue's
+ *		fill level sits above the high threshold, then a pause frame
+ *		is sent.
+ *		1 - Place a cap on the number of pause frames that are sent
+ *		because any one queue has crossed its high threshold.
+ *		See MAX_LIMIT for more details.
+ * @max_limit: Contains the value that is loaded into the per-queue limiting
+ *		counters that exist in the flow control logic. Essentially,
+ *		this represents the maximum number of pause frames that are sent
+ *		due to any one particular queue having crossed its high
+ *		threshold. Each counter is set to this max limit the first time
+ *		the corresponding queue's high threshold is crossed. The counter
+ *		decrements each time the queue remains above the high threshold
+ *		and the adapter requests pause frame transmission. Once the
+ *		counter expires that queue no longer contributes to pause frame
+ *		transmission requests. The queue's fill level must drop below
+ *		the low pause threshold before it is once again allowed to
+ *		contribute. Note: This field is only used when LIMITER_EN is set
+ *		to 1.
+ *
+ * Switch Port Configuration
+ */
+typedef struct vxge_hal_switch_port_config_t {
+
+		u32				mtu;
+#define	VXGE_HAL_SWITCH_PORT_MIN_INITIAL_MTU		    VXGE_HAL_MIN_MTU
+#define	VXGE_HAL_SWITCH_PORT_MAX_INITIAL_MTU		    VXGE_HAL_MAX_MTU
+#define	VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_en;
+#define	VXGE_HAL_SWITCH_PORT_TMAC_ENABLE				1
+#define	VXGE_HAL_SWITCH_PORT_TMAC_DISABLE				0
+#define	VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_en;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_ENABLE				1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_DISABLE				0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_pad;
+#define	VXGE_HAL_SWITCH_PORT_TMAC_NO_PAD				0
+#define	VXGE_HAL_SWITCH_PORT_TMAC_64B_PAD				1
+#define	VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_pad_byte;
+#define	VXGE_HAL_SWITCH_PORT_MIN_TMAC_PAD_BYTE			0
+#define	VXGE_HAL_SWITCH_PORT_MAX_TMAC_PAD_BYTE			255
+#define	VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE	    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				tmac_util_period;
+#define	VXGE_HAL_SWITCH_PORT_MIN_TMAC_UTIL_PERIOD			0
+#define	VXGE_HAL_SWITCH_PORT_MAX_TMAC_UTIL_PERIOD			15
+#define	VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD   VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_strip_fcs;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS			1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_SEND_FCS_TO_HOST		0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_prom_en;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_ENABLE			1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DISABLE			0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT   VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_discard_pfrm;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM			1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_SEND_PFRM_TO_HOST		0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_util_period;
+#define	VXGE_HAL_SWITCH_PORT_MIN_RMAC_UTIL_PERIOD			0
+#define	VXGE_HAL_SWITCH_PORT_MAX_RMAC_UTIL_PERIOD			15
+#define	VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD   VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_pause_gen_en;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_ENABLE		1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DISABLE		0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_pause_rcv_en;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_ENABLE		1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DISABLE		0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				rmac_pause_time;
+#define	VXGE_HAL_SWITCH_PORT_MIN_RMAC_HIGH_PTIME			16
+#define	VXGE_HAL_SWITCH_PORT_MAX_RMAC_HIGH_PTIME			65535
+#define	VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				limiter_en;
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_ENABLE		1
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DISABLE		0
+#define	VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+		u32				max_limit;
+#define	VXGE_HAL_SWITCH_PORT_MIN_RMAC_MAX_LIMIT			0
+#define	VXGE_HAL_SWITCH_PORT_MAX_RMAC_MAX_LIMIT			255
+#define	VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_switch_port_config_t;
+
+/*
+ * struct vxge_hal_mac_config_t - MAC configuration (Physical ports).
+ * @wire_port_config: Wire Port configuration
+ * @switch_port_config: Switch Port configuration
+ * @network_stability_period: The wait period for network stability
+ * @mc_pause_threshold: Contains thresholds for pause frame generation
+ *		  for queues 0 through 15. The threshold value indicates portion
+ *		of the individual receive buffer queue size. Thresholds have a
+ *		range of 0 to 255, allowing 256 possible watermarks in a queue.
+ * @tmac_perma_stop_en: Controls TMAC reaction to double ECC errors on its
+ *		internal SRAMs.
+ *		0 - Disable TMAC permanent stop
+ *		1 - Enable TMAC permanent stop whenever double ECC errors are
+ *		detected on the internal transmit SRAMs.
+ * @tmac_tx_switch_dis: Allows the user to disable the switching of transmit
+ *		frames back to the receive path.
+ *		0 - Tx frames are switched based on the result of the DA lookup
+ *		1 - The DA lookup result is ignored and all traffic is sent to
+ *		the wire.
+ *		Note that this register field does not impact the multicast
+ *		replication on the receive side.
+ * @tmac_lossy_switch_en: Controls the behaviour of the internal Tx to Rx switch
+ *		in the event of back-pressure on the receive path due to
+ *		priority given to traffic arriving off the wire or simply due to
+ *		a full receive external buffer. br>
+ *		0 - No frames are dropped on the switch path. Instead, in the
+ *		event of back-pressure, the transmit path is backed up.
+ *		1 - Whenever back-pressure is present and the next frame is
+ *		bound for the switch path, then the frame is dropped.
+ *		If it is also destined for the transmit wire, it is still
+ *		sent there.
+ *		Note: HIP traffic that is bound for the switch path is never
+ *		dropped - the transmit path is forced to backup.
+ * @tmac_lossy_wire_en: Controls the behaviour of the TMAC when the wire path
+ *		is unavailable. This occurs when the target wire port is down.
+ *		0 - No frames are dropped on the wire path. Instead,in the event
+ *		of port failure, the transmit path is backed up.
+ *		1 - Whenever a wire port is down and the next frame is bound for
+ *		that port, then the frame is dropped. If it is also destined
+ *		for the switch path, it is still sent there.
+ * @tmac_bcast_to_wire_dis: Suppresses the transmission of broadcast frames to
+ *		the wire.
+ *		0 - Transmit broadcast frames are sent out the wire and also
+ *		sent along the switch path.
+ *		1 - Transmit broadcast frame are only sent along the switch path
+ * @tmac_bcast_to_switch_dis: Suppresses the transmission of broadcast frames
+ *		along the switch path.
+ *		0 - Transmit broadcast frames are sent out the wire and also
+ *		sent along the switch path.
+ *		1 - Transmit broadcast frame are only sent out the wire.
+ * @tmac_host_append_fcs_en: Suppresses the H/W from appending the FCS to the
+ *		end of transmitted frames. The host is responsible for tacking
+ *		on the 4-byte FCS at the end of the frame.
+ *		0 - Normal operation. H/W appends FCS to all transmitted frames.
+ *		1 - Host appends FCS to frame. Transmit MAC passes it through
+ * @tpa_support_snap_ab_n: When set to 0, the TPA will accept LLC-SAP values of
+ *		0xAB as valid. If set to 1, the TPA rejects LLC-SAP values of
+ *		0xAB (only 0xAA is accepted).
+ * @tpa_ecc_enable_n: Allows ECC protection of TPA internal memories to be
+ *		disabled without having to disable ECC protection for entire
+ *		chip.
+ *		0 - Disable TPA ECC protection
+ *		1 - Enable TPA ECC protection.
+ *		Note: If chip-wide ECC protection is disabled, then so is TPA
+ *		ECC protection.
+ * @rpa_ignore_frame_err: Ignore Frame Error. The RPA may detect frame integrity
+ *		errors as it processes each received frame. If this bit is set
+ *		to '0', the RPA will tag such frames as "errored" in the RxDMA
+ *		descriptor. If the bit is set to '1', the frame will not be
+ *		tagged as "errored".
+ *		Detectable errors include:
+ *		1) early end-of-frame error, which occurs when the frame ends
+ *		before the number of bytes predicted by the IP "total length"
+ *		field have been received;
+ *		2) IP version mismatches;
+ *		3) IPv6 packets that include routing headers that are not type 0
+ *		4) Frames which contain IP packets but have an illegal SNAP-OUI
+ *		or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL
+ *		are set
+ * @rpa_support_snap_ab_n: When set to 0, the RPA will accept LLC-SAP values of
+ *		0xAB as valid. If set to 1, the RPA rejects LLC-SAP values of
+ *		0xAB (only 0xAA is accepted).
+ * @rpa_search_for_hao: Enable searching for the Home Address Option.If this bit
+ *		is set, the RPA will parse through Destination Address Headers
+ *		searching for the H.A.O. If the bit is not set, the RPA will not
+ *		perform a search and these headers will effectively be ignored.
+ * @rpa_support_ipv6_mobile_hdrs: Enable/disable support for the mobile-ipv6
+ *		Home Address Option (HAO) and Route 2 Routing Headers,as defined
+ *		in RFC 3775.
+ *		0 - Do not support mobile IPv6.
+ *		1 - Support mobile IPv6
+ * @rpa_ipv6_stop_searching: Enable/disable unknown IPv6 extension header
+ *		parsing. If the adapter discovers an unknown extension header,
+ *		it can either continue to search for a L4 protocol, or stop
+ *		searching.
+ *		0 - do not stop searching for L4 when an unknown header is
+ *		encountered.
+ *		1 - stop searching when an unknown header is encountered.
+ * @rpa_no_ps_if_unknown: Enable/disable pseudo-header inclusion if an unknown
+ *		IPv6 extension header is encountered.
+ *		If this bit is set to '1' and an unknown routing header or IPv6
+ *		extension header is discovered, the L4 checksum will not include
+ *		a pseudo-header.
+ *		If it is set to '0', the adapter will use the addresses found
+ *		in the IPv6 base header, and/or the addresses found in a Routing
+ *		Header or Home Address Option (if it is enabled).
+ *		This applies to frames not on LRO sessions only. For frames on
+ *		LRO sessions, the pseudo-header is always included in the L4
+ *		checksum
+ * @rpa_search_for_etype: For receive traffic steering purposes, indicates
+ *		whether the RPA should parse through the LLC header to find the
+ *		Ethertype of the packet.
+ *		0 - RPA presents the 802.3 length/type field, which for an
+ *		LLC-encoded frame is interpreted as a length.
+ *		1 - RPA parses the LLC-header and presents the Ethertype to the
+ *		traffic steering logic. When SEARCH_FOR_ETYPE is set and a jumbo
+ *		snap frame is received then GLOBAL_PA_CFG.EN_JS determines the
+ *		value that is presented to the traffic steering logic. If EN_JS
+ *		is set, then the RPA parses inside the header to find the
+ *		Ethertype, while if EN_JS is not set the RPA presents 0x8870.
+ * @rpa_repl_l4_comp_csum: Controls whether or not to complement the L4 checksum
+ *		after the final calculation.
+ *		0: Do not complement the L4 checksum.
+ *		1: Complement the L4 checksum.
+ *		For the behaviour on non-replicated frames see FAU_RPA_VCFG.
+ * @rpa_repl_l3_incl_cf: Controls whether or not to include the L3 checksum
+ *		field in the checksum calculation.
+ *		0: Do not include the L3 checksum field in checksum calculation
+ *		1: Include the L4 checksum field in the checksum calculation.
+ *		For the behaviour on non-replicated frames see FAU_RPA_VCFG.
+ * @rpa_repl_l3_comp_csum: Controls whether or not to complement the L3 checksum
+ *		after the final calculation.
+ *		0: Do not complement the L3 checksum.
+ *		1: Complement the L3 checksum.
+ *		For the behaviour on non-replicated frames see FAU_RPA_VCFG.
+ * @rpa_repl_ipv4_tcp_incl_ph: For received frames that are replicated at the
+ *		internal L2 switch, determines whether the pseudo-header is
+ *		included in the calculation of the L4 checksum that is passed to
+ *		the host.
+ * @rpa_repl_ipv6_tcp_incl_ph: For received frames that are replicated at the
+ *		internal L2 switch, determines whether the pseudo-header is
+ *		included in the calculation of the L4 checksum that is passed to
+ *		the host.
+ * @rpa_repl_ipv4_udp_incl_ph: For received frames that are replicated at the
+ *		internal L2 switch, determines whether the pseudo-header is
+ *		included in the calculation of the L4 checksum that is passed to
+ *		the host.
+ * @rpa_repl_ipv6_udp_incl_ph: For received frames that are replicated at the
+ *		internal L2 switch, determines whether the pseudo-header is
+ *		included in the calculation of the L4 checksum that is passed to
+ *		the host.
+ * @rpa_repl_l4_incl_cf: For received frames that are replicated at the internal
+ *		L2 switch, determines whether the checksum field (CF) of the
+ *		received frame is included in the calculation of the L4
+ *		checksum that is passed to the host.
+ * @rpa_repl_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device
+ *		to remove the VLAN tag from all received tagged frames that
+ *		are replicated at the internal L2 switch (i.e. multicast frames
+ *		that are placed in the replication queue).
+ *		0 - Do not strip the VLAN tag.
+ *		1 - Strip the VLAN tag.
+ *		Regardless of this setting, VLAN tags are always placed into
+ *		the RxDMA descriptor.
+ *
+ * MAC configuration. This includes various aspects of configuration, including:
+ * - Pause frame threshold;
+ * - sampling rate to calculate link utilization;
+ * - enabling/disabling broadcasts.
+ *
+ * See X3100 ER User Guide for more details.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the vxge_hal_mac_config_t {} structure. Please refer to the
+ * corresponding include file.
+ */
+typedef struct vxge_hal_mac_config_t {
+
+	vxge_hal_wire_port_config_t	wire_port_config[	\
+						VXGE_HAL_MAC_MAX_WIRE_PORTS];
+	vxge_hal_switch_port_config_t	switch_port_config;
+
+	u32				network_stability_period;
+#define	VXGE_HAL_MAC_MIN_NETWORK_STABILITY_PERIOD		0x0 /* 0s */
+#define	VXGE_HAL_MAC_MAX_NETWORK_STABILITY_PERIOD		0x7 /* 2s */
+#define	VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD   VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				mc_pause_threshold[16];
+#define	VXGE_HAL_MAC_MIN_MC_PAUSE_THRESHOLD			0
+#define	VXGE_HAL_MAC_MAX_MC_PAUSE_THRESHOLD			254
+#define	VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_perma_stop_en;
+#define	VXGE_HAL_MAC_TMAC_PERMA_STOP_ENABLE			1
+#define	VXGE_HAL_MAC_TMAC_PERMA_STOP_DISABLE			0
+#define	VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_tx_switch_dis;
+#define	VXGE_HAL_MAC_TMAC_TX_SWITCH_ENABLE			0
+#define	VXGE_HAL_MAC_TMAC_TX_SWITCH_DISABLE			1
+#define	VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_lossy_switch_en;
+#define	VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_ENABLE			1
+#define	VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DISABLE			0
+#define	VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_lossy_wire_en;
+#define	VXGE_HAL_MAC_TMAC_LOSSY_WIRE_ENABLE			1
+#define	VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DISABLE			0
+#define	VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_bcast_to_wire_dis;
+#define	VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DISABLE			1
+#define	VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_ENABLE			0
+#define	VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_bcast_to_switch_dis;
+#define	VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DISABLE		1
+#define	VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_ENABLE		0
+#define	VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tmac_host_append_fcs_en;
+#define	VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_ENABLE		1
+#define	VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DISABLE		0
+#define	VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_support_snap_ab_n;
+#define	VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AB		0
+#define	VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AA		1
+#define	VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_ecc_enable_n;
+#define	VXGE_HAL_MAC_TPA_ECC_ENABLE_N_ENABLE			1
+#define	VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DISABLE			0
+#define	VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_ignore_frame_err;
+#define	VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_support_snap_ab_n;
+#define	VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_search_for_hao;
+#define	VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_ENABLE			1
+#define	VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DISABLE			0
+#define	VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_support_ipv6_mobile_hdrs;
+#define	VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_ENABLE	1
+#define	VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DISABLE	0
+#define	VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT	\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_ipv6_stop_searching;
+#define	VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING			1
+#define	VXGE_HAL_MAC_RPA_IPV6_DONT_STOP_SEARCHING		0
+#define	VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_no_ps_if_unknown;
+#define	VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT   VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_search_for_etype;
+#define	VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT   VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_l4_comp_csum;
+#define	VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_l3_incl_cf;
+#define	VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_ENABLE			1
+#define	VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_l3_comp_csum;
+#define	VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_ipv4_tcp_incl_ph;
+#define	VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_ipv6_tcp_incl_ph;
+#define	VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_ipv4_udp_incl_ph;
+#define	VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_ipv6_udp_incl_ph;
+#define	VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_l4_incl_cf;
+#define	VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_ENABLE			1
+#define	VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_repl_strip_vlan_tag;
+#define	VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE		1
+#define	VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE		0
+#define	VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_mac_config_t;
+
+/*
+ * struct vxge_hal_lag_port_config_t - LAG Port configuration(For privileged
+ *				  mode driver only)
+ *
+ * @port_id: Port Id
+ * @lag_en: Enables or disables the port from joining a link aggregation group.
+ *		If link aggregation is enabled and this port is disabled, then
+ *		this port does not carry traffic (it is not associated with an
+ *		Aggregator). Both this bit and port_enabled from the physical
+ *		layer logic must be asserted to permit the Receive machine to
+ *		move beyond the PORT_DISABLED state.
+ *		0 - Disable;
+ *		1 - Enable;
+ * @discard_slow_proto: Discard received frames that contain the Slow Protocols
+ *		Multicast address (IEEE 802.3-2005 Clause 43B) -- Such frames
+ *		are used for link aggregation Marker Protocol and for LACP.
+ *		0 - Pass to host;
+ *		1 - Discard;
+ * @host_chosen_aggr: When the host is running the Link Aggregation Control
+ *		algorithm, this field determines which aggregator is attached
+ *		to this port. This field is only valid when LAG_LACP_CFG.EN is 0
+ *		0 - Aggregator 0 is attached to this port.
+ *		1 - Aggregator 1 is attached to this port.
+ * @discard_unknown_slow_proto: Discard received frames that contain the Slow
+ *		Protocols Multicast address (IEEE 802.3-2005 Clause 43B),
+ *		but have an unknown Slow Protocols PDU.
+ *		0 - Pass to host
+ *		1 - Discard
+ *		Note: This field is only relevant when DISCARD_SLOW_PROTO
+ *		is set to 0.
+ * @actor_port_num: The port number assigned to the port. Port Number 0 is
+ *		reserved and must not be assigned to any port.
+ * @actor_port_priority: The priority value assigned to the port.
+ * @actor_key_10g: The port's administrative Key when auto-negotiated to 10Gbps
+ *		The null (all zeros) Key value is not available for local use.
+ * @actor_key_1g: The port's administrative Key when auto-negotiated to 1Gbps.
+ *		The null (all zeros) Key value is not available for local use.
+ * @actor_lacp_activity: Indicates the Activity control value for this port.
+ *		0 - Passive LACP
+ *		1 - Active LACP
+ * @actor_lacp_timeout: Indicates the Timeout control value for this port.
+ *		0 - Long Timeout
+ *		1 - Short Timeout
+ * @actor_aggregation: Indicates if the port is a potential candidate for
+ *		aggregation.
+ *		0 - Link is Individual
+ *		1 - Link is Aggregateable
+ * @actor_synchronization: Indicates if the port is in sync.
+ *		0 - Link is out of sync; it is in the wrong Aggregation
+ *		1 - Link is in sync (allocated to the correct Link Aggregation
+ *		Group, the group is associated with a compatible Aggregator,
+ *		and the identity of the Link Aggregation Group is consistent
+ *		with the System ID and operational Key information transmitted)
+ * @actor_collecting: Indicates whether collecting of incoming frames is enabled
+ *		on this port.
+ *		0 - Not collecting
+ *		1 - Collection is enabled
+ * @actor_distributing: Indicates whether distribution of outgoing frames is
+ *		enabled on this port.
+ *		0 - Not distributing
+ *		1 - Distribution is enabled
+ * @actor_defaulted: Indicates whether the Actor's Receive state machine is
+ *		using administratively configured information for the Partner.
+ *		0 - The operational Partner info has been received in a LACPDU
+ *		1 - The operation Partner info is using administrative defaults
+ * @actor_expired: Indicates whether the Actor's Receive state machine is in the
+ *		EXPIRED state.
+ *		0 - Not in the EXPIRED state
+ *		1 - Is in the EXPIRED state
+ * @partner_sys_pri: The administrative default for the System Priority
+ *		component of the System Identifier of the Partner.
+ * @partner_key: The administrative default for the Partner's Key. The null
+ *		(all zeros) Key value is not available for local use.
+ * @partner_port_num: The administrative default for the Port Number component
+ *		of the Partner's Port Identifier.
+ * @partner_port_priority: The administrative default for the Port Identifier
+ *		component of the Partner's Port Identifier.
+ * @partner_lacp_activity: Indicates the Activity control value for this port.
+ *		0 - Passive LACP
+ *		1 - Active LACP
+ * @partner_lacp_timeout: Indicates the Timeout control value for this port.
+ *		0 - Long Timeout
+ *		1 - Short Timeout
+ * @partner_aggregation: Indicates if the port is a potential candidate for
+ *		aggregation.
+ *		0 - Link is Individual
+ *		1 - Link is Aggregateable
+ * @partner_synchronization: Indicates if the port is in sync.
+ *		0 - Link is out of sync; it is in the wrong Aggregation
+ *		1 - Link is in sync (allocated to the correct Link Aggregation
+ *		Group, the group is associated with a compatible Aggregator,
+ *		and the identity of the Link Aggregation Group is consistent
+ *		with the System ID and operational Key information transmitted)
+ * @partner_collecting: Indicates whether collecting of incoming frames is
+ *		enabled on this port.
+ *		0 - Not collecting
+ *		1 - Collection is enabled.
+ *		Note: According to IEEE 802.3-2005, the value of the
+ *		partner_collecting field of this register must be the same as
+ *		the value of the partner_synchronization field of this register
+ * @partner_distributing: Indicates whether distribution of outgoing frames is
+ *		enabled on this port.
+ *		0 - Not distributing
+ *		1 - Distribution is enabled
+ * @partner_defaulted: Indicates whether the Actor's Receive state machine is
+ *		using administratively configured information for the Partner.
+ *		0 - The operational Partner information has been received in
+ *		    a LACPDU
+ *		1 - The operation Partner information is using administrative
+ *		    defaults
+ * @partner_expired: Indicates whether the Actor's Receive state machine is in
+ *		the expired state.
+ *		0 - Not in the EXPIRED state
+ *		1 - Is in the EXPIRED state
+ * @partner_mac_addr: Default value for the MAC address of the Partner.
+ *
+ * This structure is configuration for LAG Port of device
+ */
+typedef struct vxge_hal_lag_port_config_t {
+	u32	port_id;
+#define	VXGE_HAL_LAG_PORT_PORT_ID_0				1
+#define	VXGE_HAL_LAG_PORT_PORT_ID_1				2
+#define	VXGE_HAL_LAG_PORT_MAX_PORTS		    VXGE_HAL_MAC_MAX_WIRE_PORTS
+
+	u32	lag_en;
+#define	VXGE_HAL_LAG_PORT_LAG_EN_DISABLE			0
+#define	VXGE_HAL_LAG_PORT_LAG_EN_ENABLE				1
+#define	VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	discard_slow_proto;
+#define	VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DISABLE		0
+#define	VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE		1
+#define	VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	host_chosen_aggr;
+#define	VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_0			0
+#define	VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1			1
+#define	VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	discard_unknown_slow_proto;
+#define	VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DISABLE	0
+#define	VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE	1
+#define	VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT	\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_port_num;
+#define	VXGE_HAL_LAG_PORT_MIN_ACTOR_PORT_NUM			0
+#define	VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_NUM			65535
+#define	VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_port_priority;
+#define	VXGE_HAL_LAG_PORT_MIN_ACTOR_PORT_PRIORITY		0
+#define	VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_PRIORITY		65535
+#define	VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_key_10g;
+#define	VXGE_HAL_LAG_PORT_MIN_ACTOR_KEY_10G			0
+#define	VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_10G			65535
+#define	VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_key_1g;
+#define	VXGE_HAL_LAG_PORT_MIN_ACTOR_KEY_1G			0
+#define	VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_1G			65535
+#define	VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_lacp_activity;
+#define	VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_PASSIVE		0
+#define	VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE		1
+#define	VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_lacp_timeout;
+#define	VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_LONG		0
+#define	VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT		1
+#define	VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_aggregation;
+#define	VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_INDIVIDUAL		0
+#define	VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE	1
+#define	VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_synchronization;
+#define	VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_OUT_OF_SYNC	0
+#define	VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC		1
+#define	VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_collecting;
+#define	VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DISABLE		0
+#define	VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE		1
+#define	VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_distributing;
+#define	VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE		0
+#define	VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE		1
+#define	VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_defaulted;
+#define	VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED			0
+#define	VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED			1
+#define	VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT   VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	actor_expired;
+#define	VXGE_HAL_LAG_PORT_ACTOR_EXPIRED			0
+#define	VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED			1
+#define	VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_sys_pri;
+#define	VXGE_HAL_LAG_PORT_MIN_PARTNER_SYS_PRI			0
+#define	VXGE_HAL_LAG_PORT_MAX_PARTNER_SYS_PRI			65535
+#define	VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_key;
+#define	VXGE_HAL_LAG_PORT_MIN_PARTNER_KEY			0
+#define	VXGE_HAL_LAG_PORT_MAX_PARTNER_KEY			65535
+#define	VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_port_num;
+#define	VXGE_HAL_LAG_PORT_MIN_PARTNER_PORT_NUM			0
+#define	VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_NUM			65535
+#define	VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_port_priority;
+#define	VXGE_HAL_LAG_PORT_MIN_PARTNER_PORT_PRIORITY		0
+#define	VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_PRIORITY		65535
+#define	VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_lacp_activity;
+#define	VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_PASSIVE		0
+#define	VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE		1
+#define	VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_lacp_timeout;
+#define	VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_LONG		0
+#define	VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT		1
+#define	VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_aggregation;
+#define	VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_INDIVIDUAL	0
+#define	VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE	1
+#define	VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_synchronization;
+#define	VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_OUT_OF_SYNC	0
+#define	VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC	1
+#define	VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT	\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_collecting;
+#define	VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DISABLE		0
+#define	VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE		1
+#define	VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_distributing;
+#define	VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE		0
+#define	VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE		1
+#define	VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_defaulted;
+#define	VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED			0
+#define	VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED			1
+#define	VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	partner_expired;
+#define	VXGE_HAL_LAG_PORT_PARTNER_EXPIRED			0
+#define	VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED			1
+#define	VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT   VXGE_HAL_USE_FLASH_DEFAULT
+
+	macaddr_t partner_mac_addr;
+
+} vxge_hal_lag_port_config_t;
+
+/*
+ * struct vxge_hal_lag_aggr_config_t - LAG Aggregator configuration
+ *				  (For privileged mode driver only)
+ *
+ * @aggr_id: Aggregator Id
+ * @mac_addr: The MAC address assigned to the Aggregator.
+ * @use_port_mac_addr: Indicates whether the Aggregator should use:
+ *		0 - the address specified in this register
+ *		1 - the station address of one of the ports to which
+ *		    it is attached
+ * @mac_addr_sel: Indicates which port address to use, if use_port_mac_addr
+ *		is set and two ports are attached to the aggregator:
+ *		0 - the station address of port 0
+ *		1 - the station address of port 1.
+ * @admin_key: The Aggregator's administrative Key under most circumstances
+ *		(see alt_admin_key for exceptions). The null (all zeros) Key
+ *		value is not available for local use.
+ * This structure is configuration for LAG Aggregators of device
+ */
+typedef struct vxge_hal_lag_aggr_config_t {
+	u32	aggr_id;
+#define	VXGE_HAL_LAG_AGGR_AGGR_ID_1				1
+#define	VXGE_HAL_LAG_AGGR_AGGR_ID_2				2
+#define	VXGE_HAL_LAG_AGGR_MAX_PORTS		    VXGE_HAL_MAC_MAX_AGGR_PORTS
+
+	macaddr_t mac_addr;
+
+	u32	use_port_mac_addr;
+#define	VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DISBALE		0
+#define	VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE		1
+#define	VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	mac_addr_sel;
+#define	VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_0			0
+#define	VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1			1
+#define	VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	admin_key;
+#define	VXGE_HAL_LAG_AGGR_MIN_ADMIN_KEY				0
+#define	VXGE_HAL_LAG_AGGR_MAX_ADMIN_KEY				65535
+#define	VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY		    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_lag_aggr_config_t;
+
+/*
+ * struct vxge_hal_lag_la_config_t - LAG Link Aggregator mode configuration(
+ *				For privileged mode driver only)
+ *
+ * @tx_discard: When the state of the port state attached to the Tx Aggregator
+ *		is not Distributing, this field determines whether frames from
+ *		the Frame Distributor are discarded by the Aggregator Mux
+ * @distrib_alg_sel: Configures the link aggregation distribution algorithm,
+ *		which determines the destination port of each wire-bound frame.
+ *		0x0 - The source VPATH determines the target port and the
+ *		   mapping is controlled by the MAP_VPATHn fields of this
+ *		   register.
+ *		0x1 - Even parity over the frame's MAC destination address
+ *		0x2 - Even parity over the frame's MAC source address
+ *		0x3 - Even parity over the frame's MAC destination address and
+ *		  MAC source address
+ *		Note: If the host changes this mapping while traffic is flowing,
+ *		then (to avoid mis-ordering at the receiver) host must either
+ *		enable the Marker protocol or assume responsibility for ensuring
+ *		that no frames pertaining to the conversations (that are moving
+ *		to a new port) are in flight.
+ * @distrib_dest: When LAG_TX_CFG.DISTRIB_ALG_SEL is set to use the source
+ *              VPATH, then this field indicates the target adapter port for
+ *              frames that come from a particular VPATH.
+ *              0 - Send frames from this VPATH to port 0
+ *              1 - Send frames from this VPATH to port 1
+ *              Note: If the host updates this mapping while traffic is flowing,
+ *              then (to avoid mis-ordering at the receiver) the host must
+ *              either enable the Marker protocol or assume responsibility for
+ *              ensuring that no frames pertaining to the conversations (that
+ *              are moving to a new port) are in flight.
+ * @distrib_remap_if_fail: When lag_mode is Link Aggregated, this field controls
+ *		whether frames are re-distributed to the working port if one
+ *		port goes down.
+ *		0 - Don't remap. Enforce frames destined for port 'x' to remain
+ *		destined for it and let LAG_CFG.TX_DISCARD_BEHAV determine
+ *		what happens to the frames.
+ *		1 - Remap the frames to the working port, essentially ignoring
+ *		the mapping table.
+ * @coll_max_delay: Collector Max Delay - the maximum amount of time (measured
+ *		in units of tens of microseconds) that the Frame Collector is
+ *		allowed to delay delivery of frames to the host. The contents
+ *		of this field are placed into the transmitted LACPDU.
+ * @rx_discard: When the state of the port state attached to the Rx Aggregator
+ *		is not Collecting, this field determines whether frames to the
+ *		Frame Collector are discarded by the Aggregator Parser
+ *
+ * Link Aggregation Link Aggregator Mode Configuration
+ */
+typedef struct vxge_hal_lag_la_config_t {
+	u32	tx_discard;
+#define	VXGE_HAL_LAG_TX_DISCARD_DISBALE				0
+#define	VXGE_HAL_LAG_TX_DISCARD_ENABLE				1
+#define	VXGE_HAL_LAG_TX_DISCARD_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	distrib_alg_sel;
+#define	VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_VPATH			0
+#define	VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEST_MAC_ADDR		1
+#define	VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_MAC_ADDR		2
+#define	VXGE_HAL_LAG_DISTRIB_ALG_SEL_BOTH_MAC_ADDR		3
+#define	VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u64	distrib_dest;
+#define	VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT0(vpid)	0
+#define	VXGE_HAL_LAG_DISTRIB_DEST_VPATH_TO_PORT_PORT1(vpid)	mBIT(vpid)
+#define	VXGE_HAL_LAG_DISTRIB_DEST_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	distrib_remap_if_fail;
+#define	VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DISBALE		0
+#define	VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE		1
+#define	VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	coll_max_delay;
+#define	VXGE_HAL_LAG_MIN_COLL_MAX_DELAY				0
+#define	VXGE_HAL_LAG_MAX_COLL_MAX_DELAY				65535
+#define	VXGE_HAL_LAG_DEF_COLL_MAX_DELAY		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	rx_discard;
+#define	VXGE_HAL_LAG_RX_DISCARD_DISBALE				0
+#define	VXGE_HAL_LAG_RX_DISCARD_ENABLE				1
+#define	VXGE_HAL_LAG_RX_DISCARD_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+
+} vxge_hal_lag_la_config_t;
+
+/*
+ * struct vxge_hal_lag_ap_config_t - LAG Active Passive Failover mode
+ *			    configuration(For privileged mode driver only)
+ *
+ * @hot_standby: Keep the standby port alive even when it is not carrying
+ *		traffic
+ *		0 - Standby port disabled until needed. The hardware behaves as
+ *		if XGMAC_CFG_PORTn.PORT_EN has disabled the port.
+ *		1 - Standby port kept up
+ * @lacp_decides: This field determines whether or not the LACP Selection logic
+ *		handles hot standby port interaction. This field is only used
+ *		when hot_standby is 1.
+ *		0 - LACP Selection logic does not explicitly determine standby
+ *		port, instead internal logic changes the aggregator's key
+ *		using information found in the alt_admin_key
+ *		field. Note that this does not disable LACP.
+ *		1 - LACP Selection logic explicitly determines standby port by
+ *		enforcing a rule that if one port is already attached to any
+ *		aggregator, then the other port is put into STANDBY. Assuming
+ *		both ports have the same Key, at startup (or anytime both
+ *		ports have become UNSELECTED) the Selection logic uses
+ *		pref_active_port to choose the active (and consequently
+ *		standby) port. After that it only selects a new port when
+ *		the active port goes down.
+ * @pref_active_port: Indicates the preferred active port number.
+ *		If hot_standby is disabled (i.e. "cold standby"), then
+ *		pref_active_port determines which port remains powered up
+ *		(and consequently which one is powered down). If hot_standby is
+ *		enabled, then pref_active_port is used by the Selection logic
+ *		whenever both ports have become UNSELECTED and the Selection
+ *		logic must decide which to make SELECTED and which to make
+ *		STANDBY.
+ *		0 - Link0 is preferred (Link1 becomes the standby port).
+ *		1 - Link1 is preferred
+ * @auto_failback: When LACP Selection logic is not handling standby port
+ *		interaction, this register provides additional user flexibility
+ *		for standby port handling. The AUTO_FAILBACK field controls
+ *		whether the device automatically fails back to the preferred
+ *		(i.e. non-alternate) Aggregator+Port pair in the event that the
+ *		preferred port comes back up after a failure. Only used when
+ *		hot_standby is set to 1 and lacp_decides is set to 0.
+ *		0 - After a failure on the preferred port, stay on alternate
+ *		port even if the preferred port comes back up. Return to
+ *		preferred port only when host indicates to return
+ *		(via FAILBACK_EN)
+ *		1 - After a failure on the preferred port,automatically failback
+ *		to preferred port whenever it comes back up.
+ * @failback_en: This field is used when hot_standby is set to 1,lacp_decides is
+ *		set to 0, and AUTO_FAILBACK is set to 0. The field is also used
+ *		when hot_standby is set to 0. The failback_en field allow the
+ *		host to control when the adapter is allowed to fail back to the
+ *		preferred port. The driver sets this field to indicate to the
+ *		adapter that it okay to fail back to the preferred port (i.e.
+ *		attempt to acquire a good port on the preferred port). This
+ *		field is self-clearing -- the adapter clears it immediately.
+ *		Note that the host can use waiting_to_fallback to tell if the
+ *		adapter is waiting for host intervention.
+ *		0 - Adapter has acknowledged the request to fail back.
+ *		1 - Host requests that the adapter fail back to preferred port.
+ * @cold_failover_timeout: When cold standby mode is entered, this field
+ *		controls how long (in msec) the adapter waits for the preferred
+ *		port to come alive (assuming it isn't alreay alive. It the
+ *		preferred port does not come up, then the adapter fails over
+ *		to the standby port when the timer expires. At the time of
+ *		standby port initialization, the timer is started again and
+ *		if the standby port does not come up after the timer expires,
+ *		then both ports are shut down.
+ * @alt_admin_key: The Aggregator's administrative Key whenever the device is in
+ *		active-passive failover mode and both ports are up. This
+ *		prevents both ports from becoming active in this case.
+ *		The H/W is responsible for choosing the proper key to use in
+ *		this case. The null (all zeros) Key value is not available for
+ *		local use.
+ * @alt_aggr: Identifies which Aggregator is designated as the alternate
+ *		(i.e. unused) Aggregator, when both ports are up.
+ *		0 - Aggregator0 is the alternate
+ *		1 - Aggregator1 is the alternate
+ *
+ * Link Aggregation Active Passive failover mode Configuration
+ */
+typedef struct vxge_hal_lag_ap_config_t {
+	u32	hot_standby;
+#define	VXGE_HAL_LAG_HOT_STANDBY_DISBALE_PORT			0
+#define	VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT			1
+#define	VXGE_HAL_LAG_HOT_STANDBY_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	lacp_decides;
+#define	VXGE_HAL_LAG_LACP_DECIDES_DISBALE			0
+#define	VXGE_HAL_LAG_LACP_DECIDES_ENBALE			1
+#define	VXGE_HAL_LAG_LACP_DECIDES_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	pref_active_port;
+#define	VXGE_HAL_LAG_PREF_ACTIVE_PORT_0				0
+#define	VXGE_HAL_LAG_PREF_ACTIVE_PORT_1				1
+#define	VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	auto_failback;
+#define	VXGE_HAL_LAG_AUTO_FAILBACK_DISBALE			0
+#define	VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE			1
+#define	VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	failback_en;
+#define	VXGE_HAL_LAG_FAILBACK_EN_DISBALE			0
+#define	VXGE_HAL_LAG_FAILBACK_EN_ENBALE				1
+#define	VXGE_HAL_LAG_FAILBACK_EN_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	cold_failover_timeout;
+#define	VXGE_HAL_LAG_MIN_COLD_FAILOVER_TIMEOUT			0
+#define	VXGE_HAL_LAG_MAX_COLD_FAILOVER_TIMEOUT			65535
+#define	VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	alt_admin_key;
+#define	VXGE_HAL_LAG_MIN_ALT_ADMIN_KEY				0
+#define	VXGE_HAL_LAG_MAX_ALT_ADMIN_KEY				65535
+#define	VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	alt_aggr;
+#define	VXGE_HAL_LAG_ALT_AGGR_0					0
+#define	VXGE_HAL_LAG_ALT_AGGR_1					1
+#define	VXGE_HAL_LAG_ALT_AGGR_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_lag_ap_config_t;
+
+/*
+ * struct vxge_hal_lag_sl_config_t - LAG Single Link configuration(For
+ *		privileged mode driver only)
+ *
+ * @pref_indiv_port: For Single Link mode, this field indicates the preferred
+ *		active port number. It is used by the Selection logic whenever
+ *		both ports have become UNSELECTED and the Selection logic must
+ *		decide which to make SELECTED and which to keep UNSELECTED.
+ *		This field is only valid when the MODE field is set to
+ *		'Single Link'.
+ *
+ * Link Aggregation Single Link Configuration
+ */
+typedef struct vxge_hal_lag_sl_config_t {
+	u32	pref_indiv_port;
+#define	VXGE_HAL_LAG_PREF_INDIV_PORT_0				0
+#define	VXGE_HAL_LAG_PREF_INDIV_PORT_1				1
+#define	VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+} vxge_hal_lag_sl_config_t;
+
+/*
+ * struct vxge_hal_lag_lacp_config_t - LAG LACP configuration(For privileged
+ *				  mode driver only)
+ *
+ * @lacp_en: Enables use of the on-chip LACP implementation.
+ * @lacp_begin: Re-initializes the LACP protocol state machines.
+ * @discard_lacp: If LACP is not enabled on the device, then all LACP frames
+ *		are passed to the host. However, when LACP is enabled,this field
+ *		determines whether the LACP frames are still passed to the host.
+ * @liberal_len_chk: Controls the length checks that are performed on the
+ *		received LACPDU by the RX FSM. Normally, the received value of
+ *		the following length fields is a known constant and(as suggested
+ *		by IEEE 802.3-2005 43.4.12) the hardware validates them:
+ *		Actor_Information_Length, Partner_Information_Length,
+ *		Collector_Information_Length, and Terminator_Information_Length.
+ * @marker_gen_recv_en: Enables marker generator/receiver. If this functionality
+ *		is disabled, then the host must assume responsibility for
+ *		ensuring that no frames pertaining to the conversations (that
+ *		are moving to a new port) are in flight, whenever the transmit
+ *		distribution algorithm is updated.
+ * @marker_resp_en: Enables the transmission of Marker Response PDUs. Adapter
+ *		sends a Marker Response PDU in response to a received Marker PDU
+ * @marker_resp_timeout: Timeout value for response to Marker frame - number
+ *		of milliseconds that the frame distribution logic will wait
+ *		before assuming that all frames transmitted on a particular
+ *		conversation have been successfully received. If a Marker
+ *		Response PDU comes back before the timer expires, then the
+ *		same assumption is made.
+ * @slow_proto_mrkr_min_interval: Minimum interval (in milliseconds) between
+ *		Marker PDU transmissions. Includes both Marker PDUs and Marker
+ *		Response PDUs. According to IEEE 802.3-2005 Annex 43B.2, the
+ *		device should send no more than 10 frames in any one-second
+ *		period. Thus, waiting 100ms between successive transmission
+ *		of Slow Protocol frames for the Marker Protocol (i.e. those
+ *		that are sourced by our Marker Generator), guarantee that we
+ *		satisfy this requirement. To be overly conservative the default
+ *		value of this register allows for 200ms between frames.
+ * @throttle_mrkr_resp: Permits the adapter to throttle the tranmission of
+ *		Marker Response PDUs to satisfy the Slow Protocols transmission
+ *		rate (see IEEE 802.3-2005 Annex 43B).
+ *		0 - Transmission of Marker Response PDUs is not moderated.
+ *		A Marker Response PDU is sent in response to every received
+ *		Marker frame, regardless of whether the Marker frames are
+ *		being received at a rate below the Slow Protocols rate.
+ *		1 - Limit the transmission of Marker Response PDUs to the Slow
+ *		Protocols transmission rate. If a remote host is generating
+ *		Marker frames too quickly, then some of these frames will
+ *		have no corresponding Marker Response PDU generated by the
+ *		adapter.
+ *
+ * Link Aggregation LACP Configuration
+ */
+typedef struct vxge_hal_lag_lacp_config_t {
+	u32	lacp_en;
+#define	VXGE_HAL_LAG_LACP_EN_DISBALE				0
+#define	VXGE_HAL_LAG_LACP_EN_ENABLE				1
+#define	VXGE_HAL_LAG_LACP_EN_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	lacp_begin;
+#define	VXGE_HAL_LAG_LACP_BEGIN_NORMAL				0
+#define	VXGE_HAL_LAG_LACP_BEGIN_RESET				1
+#define	VXGE_HAL_LAG_LACP_BEGIN_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	discard_lacp;
+#define	VXGE_HAL_LAG_DISCARD_LACP_DISBALE			0
+#define	VXGE_HAL_LAG_DISCARD_LACP_ENABLE			1
+#define	VXGE_HAL_LAG_DISCARD_LACP_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	liberal_len_chk;
+#define	VXGE_HAL_LAG_LIBERAL_LEN_CHK_DISBALE			0
+#define	VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE			1
+#define	VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	marker_gen_recv_en;
+#define	VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DISBALE			0
+#define	VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE			1
+#define	VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	marker_resp_en;
+#define	VXGE_HAL_LAG_MARKER_RESP_EN_DISBALE			0
+#define	VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE			1
+#define	VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	marker_resp_timeout;
+#define	VXGE_HAL_LAG_MIN_MARKER_RESP_TIMEOUT			0
+#define	VXGE_HAL_LAG_MAX_MARKER_RESP_TIMEOUT			65535
+#define	VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	slow_proto_mrkr_min_interval;
+#define	VXGE_HAL_LAG_MIN_SLOW_PROTO_MRKR_MIN_INTERVAL		0
+#define	VXGE_HAL_LAG_MAX_SLOW_PROTO_MRKR_MIN_INTERVAL		65535
+#define	VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	throttle_mrkr_resp;
+#define	VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DISBALE			0
+#define	VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE			1
+#define	VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_lag_lacp_config_t;
+
+/*
+ * struct vxge_hal_lag_config_t - LAG configuration(For privileged
+ *				  mode driver only)
+ *
+ * @lag_en: Enables link aggregation
+ * @lag_mode: Select the mode of operation for link aggregation. The options:
+ *		00 - Link Aggregated
+ *		01 - Active/Passive Failover
+ *		10 - Single Link
+ * @la_mode_config: LAG Link Aggregator mode config
+ * @ap_mode_config: LAG Active Passive Failover mode config
+ * @sl_mode_config: LAG Single Link mode config
+ * @lacp_config: LAG LACP config
+ * @incr_tx_aggr_stats: Controls whether Tx aggregator stats are incremented
+ *		when Link Aggregation is disabled.
+ *		0 - Don't increment
+ *		1 - Increment
+ *		Note: When LAG is enabled, aggregator stats are always
+ *		incremented.
+ * @port_config: Lag Port configuration. See vxge_hal_lag_port_config_t {}
+ * @aggr_config: Lag Aggregator configuration. See vxge_hal_lag_aggr_config_t {}
+ * @sys_pri: The System Priority of the System. Numerically lower values have
+ *		higher priority.
+ * @mac_addr: The MAC address assigned to the System. Should be non-zero.
+ * @use_port_mac_addr: Indicates whether the Aggregator should use:
+ *		0 - the address specified in this register.
+ *		1 - the station address of one of the ports in the System
+ * @mac_addr_sel: Indicates which port address to use, if USE_PORT_ADDR is set:
+ *		0 - the station address of port 0
+ *		1 - the station address of port 1.
+ * @fast_per_time: Fast Periodic Time - number of seconds between periodic
+ *		transmissions of Short Timeouts.
+ * @slow_per_time: Slow Periodic Time - number of seconds between periodic
+ *		transmissions of Long Timeouts.
+ * @short_timeout: Short Timeout Time - number of seconds before
+ *		invalidating received LACPDU information using Short
+ *		Timeouts (3 x Fast Periodic Time).
+ * @long_timeout: Long Timeout Time - number of seconds before invalidating
+ *		received LACPDU information using Long Timeouts
+ *		(3 x Slow Periodic Time).
+ * @churn_det_time: Churn Detection Time - number of seconds that the
+ *		Actor and Partner Churn state machines wait for the Actor
+ *		or Partner Sync state to stabilize.
+ * @aggr_wait_time: Aggregate Wait Time - number of seconds to delay
+ *		aggregation,to allow multiple links to aggregate simultaneously
+ * @short_timer_scale: For simulation purposes, this field allows scaling of
+ *		link aggregation timers. Specifically, the included timers are
+ *		short (programmed with units of msec) and include 'Emptied Link
+ *		Timer', 'Slow Proto Timer for Marker PDU', 'Slow Proto Timer for
+ *		Marker Response PDU', and 'Cold Failover Timer'.
+ *		0x0 - No scaling
+ *		0x1 - Scale by 10X (counter expires 10 times faster)
+ *		0x2 - Scale by 100X
+ *		0x3 - Scale by 1000X
+ * @long_timer_scale: For simulation purposes, this field allows scaling of link
+ *		aggregation timers. Specifically, the included timers are long
+ *		(programmed with units of seconds) and include 'Current While
+ *		Timer', 'Periodic Timer', 'Wait While Timer', 'Transmit LACP
+ *		Timer', 'Actor Churn Timer', 'Partner Churn Timer',
+ *		0x0 - No scaling
+ *		0x1 - Scale by 10X (counter expires 10 times faster)
+ *		0x2 - Scale by 100X
+ *		0x3 - Scale by 1000X
+ *		0x4 - Scale by 10000X
+ *		0x5 - Scale by 100000X
+ *		0x6 - Scale by 1000000X
+ *
+ * Link Aggregation Configuration
+ */
+typedef struct vxge_hal_lag_config_t {
+	u32	lag_en;
+#define	VXGE_HAL_LAG_LAG_EN_DISABLE				0
+#define	VXGE_HAL_LAG_LAG_EN_ENABLE				1
+#define	VXGE_HAL_LAG_LAG_EN_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	lag_mode;
+#define	VXGE_HAL_LAG_LAG_MODE_LAG				0
+#define	VXGE_HAL_LAG_LAG_MODE_ACTIVE_PASSIVE_FAILOVER		1
+#define	VXGE_HAL_LAG_LAG_MODE_SINGLE_LINK			2
+#define	VXGE_HAL_LAG_LAG_MODE_DEFAULT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	vxge_hal_lag_la_config_t	la_mode_config;
+	vxge_hal_lag_ap_config_t	ap_mode_config;
+	vxge_hal_lag_sl_config_t	sl_mode_config;
+	vxge_hal_lag_lacp_config_t	lacp_config;
+
+	u32	incr_tx_aggr_stats;
+#define	VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DISBALE			0
+#define	VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE			1
+#define	VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	vxge_hal_lag_port_config_t port_config[VXGE_HAL_LAG_PORT_MAX_PORTS];
+	vxge_hal_lag_aggr_config_t aggr_config[VXGE_HAL_LAG_AGGR_MAX_PORTS];
+
+	u32	sys_pri;
+#define	VXGE_HAL_LAG_MIN_SYS_PRI				0
+#define	VXGE_HAL_LAG_MAX_SYS_PRI				65535
+#define	VXGE_HAL_LAG_DEF_SYS_PRI		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	macaddr_t mac_addr;
+
+	u32	use_port_mac_addr;
+#define	VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DISBALE			0
+#define	VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE			1
+#define	VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	mac_addr_sel;
+#define	VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_0			0
+#define	VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1			1
+#define	VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	fast_per_time;
+#define	VXGE_HAL_LAG_MIN_FAST_PER_TIME				0
+#define	VXGE_HAL_LAG_MAX_FAST_PER_TIME				65535
+#define	VXGE_HAL_LAG_DEF_FAST_PER_TIME		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	slow_per_time;
+#define	VXGE_HAL_LAG_MIN_SLOW_PER_TIME				0
+#define	VXGE_HAL_LAG_MAX_SLOW_PER_TIME				65535
+#define	VXGE_HAL_LAG_DEF_SLOW_PER_TIME		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	short_timeout;
+#define	VXGE_HAL_LAG_MIN_SHORT_TIMEOUT				0
+#define	VXGE_HAL_LAG_MAX_SHORT_TIMEOUT				65535
+#define	VXGE_HAL_LAG_DEF_SHORT_TIMEOUT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	long_timeout;
+#define	VXGE_HAL_LAG_MIN_LONG_TIMEOUT				0
+#define	VXGE_HAL_LAG_MAX_LONG_TIMEOUT				65535
+#define	VXGE_HAL_LAG_DEF_LONG_TIMEOUT		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	churn_det_time;
+#define	VXGE_HAL_LAG_MIN_CHURN_DET_TIME				0
+#define	VXGE_HAL_LAG_MAX_CHURN_DET_TIME				65535
+#define	VXGE_HAL_LAG_DEF_CHURN_DET_TIME		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	aggr_wait_time;
+#define	VXGE_HAL_LAG_MIN_AGGR_WAIT_TIME				0
+#define	VXGE_HAL_LAG_MAX_AGGR_WAIT_TIME				65535
+#define	VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME		    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	short_timer_scale;
+#define	VXGE_HAL_LAG_SHORT_TIMER_SCALE_1X			0
+#define	VXGE_HAL_LAG_SHORT_TIMER_SCALE_10X			1
+#define	VXGE_HAL_LAG_SHORT_TIMER_SCALE_100X			2
+#define	VXGE_HAL_LAG_SHORT_TIMER_SCALE_1000X			3
+#define	VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32	long_timer_scale;
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_1X			0
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_10X			1
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_100X			2
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_1000X			3
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_10000X			4
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_100000X			5
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_1000000X			6
+#define	VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_lag_config_t;
+
+/*
+ * struct vxge_hal_vpath_qos_config_t - Vpath qos(For privileged
+ *				  mode driver only)
+ * @priority: The priority of vpath
+ * @min_bandwidth: Minimum Guaranteed bandwidth
+ * @max_bandwidth: Maximum allowed bandwidth
+ *
+ * This structure is vpath qos configuration for MRPCIM section of device
+ */
+typedef struct vxge_hal_vpath_qos_config_t {
+	u32				priority;
+#define	VXGE_HAL_VPATH_QOS_PRIORITY_MIN				0
+#define	VXGE_HAL_VPATH_QOS_PRIORITY_MAX				16
+#define	VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT			0
+
+	u32				min_bandwidth;
+#define	VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MIN			0
+#define	VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MAX			100
+#define	VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT		0
+
+	u32				max_bandwidth;
+#define	VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MIN			0
+#define	VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MAX			100
+#define	VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT		0
+
+} vxge_hal_vpath_qos_config_t;
+
+/*
+ * struct vxge_hal_mrpcim_config_t - MRPCIM secion configuration(For privileged
+ *				  mode driver only)
+ *
+ * @mac_config: MAC Port Config. See vxge_hal_mac_config_t {}
+ * @lag_config: MAC Port Config. See vxge_hal_lag_config_t {}
+ * @vp_qos: Vpath QOS
+ * @vpath_to_wire_port_map_en: Mask to enable vpath to wire port mapping.
+ * @vpath_to_wire_port_map: If LAG is not enabled or lag_distrib_dest is not set
+ *		then vpath_to_wire_port_map is used to assign independent ports
+ *		to vpath
+ *
+ * This structure is configuration for MRPCIM section of device
+ */
+typedef struct vxge_hal_mrpcim_config_t {
+	vxge_hal_mac_config_t mac_config;
+	vxge_hal_lag_config_t lag_config;
+	u64	vpath_to_wire_port_map_en;
+#define	VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_DISABLE(vpid)	0
+#define	VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_ENABLE(vpid)		mBIT(vpid)
+#define	VXGE_HAL_VPATH_WIRE_PORTS_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+	u64	vpath_to_wire_port_map;
+#define	VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT0(vpid)		0
+#define	VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_PORT1(vpid)		mBIT(vpid)
+#define	VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+	vxge_hal_vpath_qos_config_t vp_qos[VXGE_HAL_MAX_VIRTUAL_PATHS];
+} vxge_hal_mrpcim_config_t;
+
+/*
+ * struct vxge_hal_tim_intr_config_t - X3100 Tim interrupt configuration.
+ * @intr_enable: Set to 1, if interrupt is enabled.
+ * @btimer_val: Boundary Timer Initialization value in units of 272 ns.
+ * @timer_ac_en: Timer Automatic Cancel. 1 : Automatic Canceling Enable: when
+ *		asserted, other interrupt-generating entities will cancel the
+ *		scheduled timer interrupt.
+ * @timer_ci_en: Timer Continuous Interrupt. 1 : Continuous Interrupting Enable:
+ *		When asserted, an interrupt will be generated every time the
+ *		boundary timer expires, even if no traffic has been transmitted
+ *		on this interrupt.
+ * @timer_ri_en: Timer Consecutive (Re-) Interrupt 1 : Consecutive
+ *		(Re-) Interrupt Enable: When asserted, an interrupt will be
+ *		generated the next time the timer expires,even if no traffic has
+ *		been transmitted on this interrupt. (This will only happen once
+ *		each time that this value is written to the TIM.) This bit is
+ *		cleared by H/W at the end of the current-timer-interval when
+ *		the interrupt is triggered.
+ * @rtimer_event_sf: Restriction Timer Event Scale Factor. A scale factor that
+ *		is to be applied to the current event count before it is added
+ *		to the restriction timer value when the the restriction timer
+ *		is started.
+ *		The scale factor is applied as a right or left shift to multiply
+ *		or divide by the event count. The programmable values are as
+ *		follows:
+ *		0-disable restriction timer and use the base timer value.
+ *		1-Multiply the event count by 2, shift left by 1.
+ *		2-Multiply the event count by 4, shift left by 2.
+ *		3-Multiply the event count by 8, shift left by 3.
+ *		4-Multiply the event count by 16, shift left by 4.
+ *		5-Multiply the event count by 32, shift left by 5.
+ *		6-Multiply the event count by 64, shift  left by 6.
+ *		7-Multiply the event count by 128, shift left by 7.
+ *		8-add the event count, no shifting.
+ *		9-Divide the event count by 128, shift right by 7.
+ *		10-Divide the event count by 64, shift right by 6.
+ *		11-Divide the event count by 32, shift right by 5.
+ *		12-Divide the event count by 16, shift right by 4.
+ *		13-Divide the event count by 8, shift right by 3.
+ *		14-Divide the event count by 4, shift right by 2.
+ *		15-Divide the event count by 2, shift right by 1.
+ * @rtimer_val: Restriction Timer Initialization value in units of 272 ns.
+ * @util_sel: Utilization Selector. Selects which of the workload approximations
+ *		to use (e.g. legacy Tx utilization, Tx/Rx utilization, host
+ *		specified utilization etc.),selects one of the 17 host
+ *		configured values.
+ *		0-Virtual Path 0
+ *		1-Virtual Path 1
+ *		...
+ *		16-Virtual Path 17
+ *		17-Legacy Tx network utilization, provided by TPA
+ *		18-Legacy Rx network utilization, provided by FAU
+ *		19-Average of legacy Rx and Tx utilization calculated from link
+ *		utilization values.
+ *		20-31-Invalid configurations
+ *		32-Host utilization for Virtual Path 0
+ *		33-Host utilization for Virtual Path 1
+ *		...
+ *		48-Host utilization for Virtual Path 17
+ *		49-Legacy Tx network utilization, provided by TPA
+ *		50-Legacy Rx network utilization, provided by FAU
+ *		51-Average of legacy Rx and Tx utilization calculated from
+ *		link utilization values.
+ *		52-63-Invalid configurations
+ * @ltimer_val: Latency Timer Initialization Value in units of 272 ns.
+ * @txfrm_cnt_en: Transmit Frame Event Count Enable. This configuration bit
+ *		when set to 1 enables counting of transmit frame's(signalled by
+ *		SM), towards utilization event count values.
+ * @txd_cnt_en: TxD Return Event Count Enable. This configuration bit when set
+ *		to 1 enables counting of TxD0 returns (signalled by PCC's),
+ *		towards utilization event count values.
+ * @urange_a: Defines the upper limit (in percent) for this utilization range
+ *		to be active. This range is considered active
+ *		 if 0 = UTIL = URNG_A and the UEC_A field (below) is non-zero.
+ * @uec_a: Utilization Event Count A. If this range is active, the adapter will
+ *		wait until UEC_A events have occurred on the interrupt before
+ *		generating an interrupt.
+ * @urange_b: Link utilization range B.
+ * @uec_b: Utilization Event Count B.
+ * @urange_c: Link utilization range C.
+ * @uec_c: Utilization Event Count C.
+ * @urange_d: Link utilization range D.
+ * @uec_d: Utilization Event Count D.
+ * @ufca_intr_thres
+ * @ufca_lo_lim
+ * @ufca_hi_lim
+ * @ufca_lbolt_period:
+ *
+ * Traffic Interrupt Controller Module interrupt configuration.
+ */
+typedef struct vxge_hal_tim_intr_config_t {
+
+	u32				intr_enable;
+#define	VXGE_HAL_TIM_INTR_ENABLE				1
+#define	VXGE_HAL_TIM_INTR_DISABLE				0
+#define	VXGE_HAL_TIM_INTR_DEFAULT				0
+
+	u32				btimer_val;
+#define	VXGE_HAL_MIN_TIM_BTIMER_VAL				0
+#define	VXGE_HAL_MAX_TIM_BTIMER_VAL				67108864
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				timer_ac_en;
+#define	VXGE_HAL_TIM_TIMER_AC_ENABLE				1
+#define	VXGE_HAL_TIM_TIMER_AC_DISABLE				0
+#define	VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				timer_ci_en;
+#define	VXGE_HAL_TIM_TIMER_CI_ENABLE				1
+#define	VXGE_HAL_TIM_TIMER_CI_DISABLE				0
+#define	VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				timer_ri_en;
+#define	VXGE_HAL_TIM_TIMER_RI_ENABLE				1
+#define	VXGE_HAL_TIM_TIMER_RI_DISABLE				0
+#define	VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rtimer_event_sf;
+#define	VXGE_HAL_MIN_TIM_RTIMER_EVENT_SF			0
+#define	VXGE_HAL_MAX_TIM_RTIMER_EVENT_SF			15
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rtimer_val;
+#define	VXGE_HAL_MIN_TIM_RTIMER_VAL				0
+#define	VXGE_HAL_MAX_TIM_RTIMER_VAL				67108864
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				util_sel;
+#define	VXGE_HAL_TIM_UTIL_SEL_VPATH(n)				n
+#define	VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL		17
+#define	VXGE_HAL_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL		18
+#define	VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL		19
+#define	VXGE_HAL_TIM_UTIL_SEL_VPATH(n)				n
+#define	VXGE_HAL_TIM_UTIL_SEL_VPATH(n)				n
+#define	VXGE_HAL_TIM_UTIL_SEL_HOST_UTIL_VPATH(n)		(32+n)
+#define	VXGE_HAL_TIM_UTIL_SEL_TIM_UTIL_VPATH(n)			63
+#define	VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				ltimer_val;
+#define	VXGE_HAL_MIN_TIM_LTIMER_VAL				0
+#define	VXGE_HAL_MAX_TIM_LTIMER_VAL				67108864
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL    VXGE_HAL_USE_FLASH_DEFAULT
+
+	/* Line utilization interrupts */
+	u32				txfrm_cnt_en;
+#define	VXGE_HAL_TXFRM_CNT_EN_ENABLE				1
+#define	VXGE_HAL_TXFRM_CNT_EN_DISABLE				0
+#define	VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				txd_cnt_en;
+#define	VXGE_HAL_TXD_CNT_EN_ENABLE				1
+#define	VXGE_HAL_TXD_CNT_EN_DISABLE				0
+#define	VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				urange_a;
+#define	VXGE_HAL_MIN_TIM_URANGE_A				0
+#define	VXGE_HAL_MAX_TIM_URANGE_A				100
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				uec_a;
+#define	VXGE_HAL_MIN_TIM_UEC_A					0
+#define	VXGE_HAL_MAX_TIM_UEC_A					65535
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				urange_b;
+#define	VXGE_HAL_MIN_TIM_URANGE_B				0
+#define	VXGE_HAL_MAX_TIM_URANGE_B				100
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				uec_b;
+#define	VXGE_HAL_MIN_TIM_UEC_B					0
+#define	VXGE_HAL_MAX_TIM_UEC_B					65535
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				urange_c;
+#define	VXGE_HAL_MIN_TIM_URANGE_C				0
+#define	VXGE_HAL_MAX_TIM_URANGE_C				100
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				uec_c;
+#define	VXGE_HAL_MIN_TIM_UEC_C					0
+#define	VXGE_HAL_MAX_TIM_UEC_C					65535
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				uec_d;
+#define	VXGE_HAL_MIN_TIM_UEC_D					0
+#define	VXGE_HAL_MAX_TIM_UEC_D					65535
+#define	VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				ufca_intr_thres;
+#define	VXGE_HAL_MIN_UFCA_INTR_THRES				1
+#define	VXGE_HAL_MAX_UFCA_INTR_THRES				4096
+#define	VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				ufca_lo_lim;
+#define	VXGE_HAL_MIN_UFCA_LO_LIM				1
+#define	VXGE_HAL_MAX_UFCA_LO_LIM				16
+#define	VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				ufca_hi_lim;
+#define	VXGE_HAL_MIN_UFCA_HI_LIM				1
+#define	VXGE_HAL_MAX_UFCA_HI_LIM				256
+#define	VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				ufca_lbolt_period;
+#define	VXGE_HAL_MIN_UFCA_LBOLT_PERIOD				1
+#define	VXGE_HAL_MAX_UFCA_LBOLT_PERIOD				1024
+#define	VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_tim_intr_config_t;
+
+/*
+ * struct vxge_hal_fifo_config_t - Configuration of fifo.
+ * @enable: Is this fifo to be commissioned
+ * @fifo_length: Numbers of TxDLs (that is, lists of Tx descriptors)per queue.
+ * @max_frags: Max number of Tx buffers per TxDL (that is, per single
+ *		transmit operation).
+ *		No more than 256 transmit buffers can be specified.
+ * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
+ *		(e.g., to align on a cache line).
+ * @max_aligned_frags: Number of fragments to be aligned out of
+ *		maximum fragments (see @max_frags).
+ * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL.
+ *		Use 0 otherwise.
+ * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
+ *		which generally improves latency of the host bridge operation
+ *		(see PCI specification). For valid values please refer
+ *		to vxge_hal_fifo_config_t {} in the driver sources.
+ * Configuration of all X3100 fifos.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the vxge_hal_fifo_config_t {} structure.
+ */
+typedef struct vxge_hal_fifo_config_t {
+	u32				enable;
+#define	VXGE_HAL_FIFO_ENABLE					1
+#define	VXGE_HAL_FIFO_DISABLE					0
+#define	VXGE_HAL_FIFO_DEFAULT					1
+
+	u32				fifo_length;
+#define	VXGE_HAL_MIN_FIFO_LENGTH				1
+#define	VXGE_HAL_MAX_FIFO_LENGTH				12*1024
+#define	VXGE_HAL_DEF_FIFO_LENGTH				512
+
+	u32				max_frags;
+#define	VXGE_HAL_MIN_FIFO_FRAGS					1
+#define	VXGE_HAL_MAX_FIFO_FRAGS					256
+#define	VXGE_HAL_DEF_FIFO_FRAGS					256
+
+	u32				alignment_size;
+#define	VXGE_HAL_MIN_FIFO_ALIGNMENT_SIZE			0
+#define	VXGE_HAL_MAX_FIFO_ALIGNMENT_SIZE			65536
+#define	VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE	    __vxge_os_cacheline_size
+
+	u32				max_aligned_frags;
+	/* range: (1, @max_frags) */
+
+	u32				intr;
+#define	VXGE_HAL_FIFO_QUEUE_INTR_ENABLE				1
+#define	VXGE_HAL_FIFO_QUEUE_INTR_DISABLE			0
+#define	VXGE_HAL_FIFO_QUEUE_INTR_DEFAULT			0
+
+	u32				no_snoop_bits;
+#define	VXGE_HAL_FIFO_NO_SNOOP_DISABLED				0
+#define	VXGE_HAL_FIFO_NO_SNOOP_TXD				1
+#define	VXGE_HAL_FIFO_NO_SNOOP_FRM				2
+#define	VXGE_HAL_FIFO_NO_SNOOP_ALL				3
+#define	VXGE_HAL_FIFO_NO_SNOOP_DEFAULT				0
+
+} vxge_hal_fifo_config_t;
+
+/*
+ * struct vxge_hal_ring_config_t - Ring configurations.
+ * @enable: Is this ring to be commissioned
+ * @ring_length: Numbers of RxDs in the ring
+ * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
+ *		to X3100 User Guide.
+ * @scatter_mode: X3100 supports two receive scatter modes: A and B.
+ *		For details please refer to X3100 User Guide.
+ * @post_mode: The RxD post mode.
+ * @max_frm_len: Maximum frame length that can be received on _that_ ring.
+ *		Setting this field to VXGE_HAL_USE_FLASH_DEFAULT ensures that
+ *		the ring will "accept"
+ *		MTU-size frames (note that MTU can be changed at runtime).
+ *		Any value other than (VXGE_HAL_USE_FLASH_DEFAULT) specifies a
+ *		certain "hard" limit on the receive frame sizes. The field can
+ *		be used to activate receive frame-length based steering.
+ * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
+ *		which generally improves latency of the host bridge operation
+ *		(see PCI specification). For valid values please refer
+ *		to vxge_hal_ring_config_t {} in the driver sources.
+ * @rx_timer_val: The number of 32ns periods that would be counted between two
+ *		timer interrupts.
+ * @greedy_return: If Set it forces the device to return absolutely all RxD
+ *		that are consumed and still on board when a timer interrupt
+ *		triggers. If Clear, then if the device has already returned
+ *		RxD before current timer interrupt trigerred and after the
+ *		previous timer interrupt triggered, then the device is not
+ *		forced to returned the rest of the consumed RxD that it has
+ *		on board which account for a byte count less than the one
+ *		programmed into PRC_CFG6.RXD_CRXDT field
+ * @rx_timer_ci: TBD
+ * @backoff_interval_us: Time (in microseconds), after which X3100
+ *		tries to download RxDs posted by the host.
+ *		Note that the "backoff" does not happen if host posts receive
+ *		descriptors in the timely fashion.
+ * @indicate_max_pkts: Sets maximum number of received frames to be processed
+ *		within single interrupt.
+ * @sw_lro_sessions: Number of LRO Sessions
+ * @sw_lro_sg_size: Size of LROable segment
+ * @sw_lro_frm_len: Length of LROable frame
+ *
+ * Ring configuration.
+ */
+typedef struct vxge_hal_ring_config_t {
+	u32				enable;
+#define	VXGE_HAL_RING_ENABLE					1
+#define	VXGE_HAL_RING_DISABLE					0
+#define	VXGE_HAL_RING_DEFAULT					1
+
+	u32				ring_length;
+#define	VXGE_HAL_MIN_RING_LENGTH				1
+#define	VXGE_HAL_MAX_RING_LENGTH				8096
+#define	VXGE_HAL_DEF_RING_LENGTH				512
+
+	u32				buffer_mode;
+#define	VXGE_HAL_RING_RXD_BUFFER_MODE_1				1
+#define	VXGE_HAL_RING_RXD_BUFFER_MODE_3				3
+#define	VXGE_HAL_RING_RXD_BUFFER_MODE_5				5
+#define	VXGE_HAL_RING_RXD_BUFFER_MODE_DEFAULT			1
+
+	u32				scatter_mode;
+#define	VXGE_HAL_RING_SCATTER_MODE_A				0
+#define	VXGE_HAL_RING_SCATTER_MODE_B				1
+#define	VXGE_HAL_RING_SCATTER_MODE_C				2
+#define	VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				post_mode;
+#define	VXGE_HAL_RING_POST_MODE_LEGACY				0
+#define	VXGE_HAL_RING_POST_MODE_DOORBELL			1
+#define	VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT   VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				max_frm_len;
+#define	VXGE_HAL_MIN_RING_MAX_FRM_LEN			    VXGE_HAL_MIN_MTU
+#define	VXGE_HAL_MAX_RING_MAX_FRM_LEN			    VXGE_HAL_MAX_MTU
+#define	VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU	    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				no_snoop_bits;
+#define	VXGE_HAL_RING_NO_SNOOP_DISABLED				0
+#define	VXGE_HAL_RING_NO_SNOOP_RXD				1
+#define	VXGE_HAL_RING_NO_SNOOP_FRM				2
+#define	VXGE_HAL_RING_NO_SNOOP_ALL				3
+#define	VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rx_timer_val;
+#define	VXGE_HAL_RING_MIN_RX_TIMER_VAL				0
+#define	VXGE_HAL_RING_MAX_RX_TIMER_VAL				536870912
+#define	VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				greedy_return;
+#define	VXGE_HAL_RING_GREEDY_RETURN_ENABLE			1
+#define	VXGE_HAL_RING_GREEDY_RETURN_DISABLE			0
+#define	VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rx_timer_ci;
+#define	VXGE_HAL_RING_RX_TIMER_CI_ENABLE			1
+#define	VXGE_HAL_RING_RX_TIMER_CI_DISABLE			0
+#define	VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				backoff_interval_us;
+#define	VXGE_HAL_MIN_BACKOFF_INTERVAL_US			1
+#define	VXGE_HAL_MAX_BACKOFF_INTERVAL_US			125000
+#define	VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				indicate_max_pkts;
+#define	VXGE_HAL_MIN_RING_INDICATE_MAX_PKTS			1
+#define	VXGE_HAL_MAX_RING_INDICATE_MAX_PKTS			65536
+#define	VXGE_HAL_DEF_RING_INDICATE_MAX_PKTS			65536
+
+
+} vxge_hal_ring_config_t;
+
+
+/*
+ * struct vxge_hal_vp_config_t - Configuration of virtual path
+ * @vp_id: Virtual Path Id
+ * @wire_port: Wire port to be associated with the vpath
+ * @bandwidth_limit: Desired bandwidth limit for this vpath.
+ *		0 = Disable limit, 1 = 8192 kBps, 2 = 16384 kBps, ... ,
+ *		>152588 = 1 GBps
+ * @no_snoop: Enable or disable no snoop for vpath
+ * @ring: See vxge_hal_ring_config_t {}.
+ * @fifo: See vxge_hal_fifo_config_t {}.
+ * @dmq: See vxge_hal_dmq_config_t {};
+ * @umq: See vxge_hal_umq_config_t {};
+ * @lro: See vxge_hal_lro_config_t {};
+ * @tti: Configuration of interrupt associated with Transmit.
+ *		see vxge_hal_tim_intr_config_t();
+ * @rti: Configuration of interrupt associated with Receive.
+ *		 see vxge_hal_tim_intr_config_t();
+ * @mtu: mtu size used on this port.
+ * @tpa_lsov2_en: LSOv2 Behaviour for IP ID roll-over
+ * @tpa_ignore_frame_error: Ignore Frame Error. TPA may detect frame integrity
+ *		errors as it processes each frame. If this bit is set to '0',
+ *		the TPA will tag such frames as invalid and they will be dropped
+ *		by the transmit MAC. If the bit is set to '1',the frame will not
+ *		be tagged as "errored".  Detectable errors include:
+ *		1) early end-of-frame error, which occurs when the frame ends
+ *		before the number of bytes predicted by the IP "total length"
+ *		field have been received;
+ *		2) IP version mismatches;
+ *		3) IPv6 packets that include routing headers that are not type 0
+ *		4) Frames which contain IP packets but have an illegal SNAP-OUI
+ *		or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL
+ *		are set (see below).
+ * @tpa_ipv6_keep_searching: If unknown IPv6 header is found,
+ *		0 - stop searching for TCP
+ *		1 - keep searching for TCP
+ * @tpa_l4_pshdr_present: If asserted true, indicates the host has provided a
+ *		valid pseudo header for TCP or UDP running over IPv4 or IPv6
+ * @tpa_support_mobile_ipv6_hdrs: This register is somewhat equivalent to
+ *		asserting both Hercules register fields LSO_RT2_EN and
+ *		LSO_IPV6_HAO_EN. Enable/disable support for Type 2 Routing
+ *		Headers, and for Mobile-IPv6 Home Address Option (HAO),
+ *		as defined by mobile-ipv6.
+ * @rpa_ipv4_tcp_incl_ph: Determines if the pseudo-header is included in the
+ *		calculation of the L4 checksum that is passed to the host. This
+ *		field applies to TCP/IPv4 packets only. This field affects both
+ *		non-offload and LRO traffic. Note that the RPA always includes
+ *		the pseudo-header in the "Checksum Ok" L4 checksum calculation
+ *		i.e. the checksum that decides whether a frame is a candidate to
+ *		be offloaded.
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ * @rpa_ipv6_tcp_incl_ph: Determines whether the pseudo-header is included in
+ *		the calculation of the L4 checksum that is passed to the host.
+ *		This field applies to TCP/IPv6 packets only. This field affects
+ *		both non-offload and LRO traffic. Note that the RPA always
+ *		includes the pseudo-header in the "Checksum Ok" L4 checksum
+ *		calculation. i.e. the checksum that decides whether a frame
+ *		is a candidate to be offloaded.
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ * @rpa_ipv4_udp_incl_ph: Determines whether the pseudo-header is included in
+ *		the calculation of the L4 checksum that is passed to the host.
+ *		This field applies to UDP/IPv4 packets only. It only affects
+ *		non-offload traffic(since UDP frames are not candidates for LRO)
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ * @rpa_ipv6_udp_incl_ph: Determines if the pseudo-header is included in the
+ *		calculation of the L4 checksum that is passed to the host. This
+ *		field applies to UDP/IPv6 packets only. It only affects
+ *		non-offload traffic(since UDP frames are not candidates for LRO)
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ * @rpa_l4_incl_cf: Determines whether the checksum field (CF) of the received
+ *		frame is included in the calculation of the L4 checksum that is
+ *		passed to the host. This field affects both non-offload and LRO
+ *		traffic. Note that the RPA always includes the checksum field in
+ *		the "Checksum Ok" L4 checksum calculation -- i.e. the checksum
+ *		that decides whether a frame is a candidate to be offloaded.
+ *		0 - Do not include the checksum field in L4 checksum calculation
+ *		1 - Include the checksum field in L4 checksum calculation
+ * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to
+ *		remove the VLAN tag from all received tagged frames that are not
+ *		replicated at the internal L2 switch.
+ *		0 - Do not strip the VLAN tag.
+ *		1 - Strip the VLAN tag. Regardless of this setting,VLAN tags are
+ *		always placed into the RxDMA descriptor.
+ * @rpa_l4_comp_csum: Determines whether the calculated L4 checksum should be
+ *		complemented before it is passed to the host This field affects
+ *		both non-offload and LRO traffic.
+ *		0 - Do not complement the calculated L4 checksum.
+ *		1 - Complement the calculated L4 checksum
+ * @rpa_l3_incl_cf: Determines whether the checksum field (CF) of the received
+ *		frame is included in the calculation of the L3 checksum that is
+ *		passed to the host. This field affects both non-offload and LRO
+ *		traffic. Note that the RPA always includes the checksum field in
+ *		the "Checksum Ok" L3 checksum calculation--i.e. the checksum
+ *		that decides whether a frame is a candidate to be offloaded.
+ *		0 - Do not include the checksum field in L3 checksum calculation
+ *		1 - Include the checksum field in L3 checksum calculation
+ * @rpa_l3_comp_csum: Determines whether the calculated L3 checksum should be
+ *		complemented before it is passed to the host This field affects
+ *		both non-offload and LRO traffic.
+ *		0 - Do not complement the calculated L3 checksum.
+ *		1 - Complement the calculated L3 checksum
+ * @rpa_ucast_all_addr_en: Enables frames with any unicast address (as its
+ *		destination address) to be passed to the host.
+ * @rpa_mcast_all_addr_en: Enables frames with any multicast address (as its
+ *		destination address) to be passed to the host.
+ * @rpa_bcast_en: Enables frames with any broadicast address (as its
+ *		destination address) to be passed to the host.
+ * @rpa_all_vid_en: romiscuous mode, it overrides the value held in this field.
+ *		0 - Disable;
+ *		1 - Enable
+ *		Note: RXMAC_GLOBAL_CFG.AUTHORIZE_VP_ALL_VID must be set to
+ *		allow this.
+ * @vp_queue_l2_flow: Allows per-VPATH receive queue from
+ *		contributing to L2 flow control. Has precedence over
+ *		RMAC_PAUSE_CFG_PORTn.LIMITER_EN.
+ *		0 - Queue is not allowed to contribute to L2 flow control.
+ *		1 - Queue is allowed to contribute to L2 flow control.
+ *
+ * This structure is used by the driver to pass the configuration parameters to
+ * configure Virtual Path.
+ */
+typedef struct vxge_hal_vp_config_t {
+	u32				vp_id;
+
+	u32				wire_port;
+#define	VXGE_HAL_VPATH_USE_DEFAULT_PORT		VXGE_HAL_FIFO_HOST_STEER_NORMAL
+#define	VXGE_HAL_VPATH_USE_PORT0		VXGE_HAL_FIFO_HOST_STEER_PORT0
+#define	VXGE_HAL_VPATH_USE_PORT1		VXGE_HAL_FIFO_HOST_STEER_PORT1
+#define	VXGE_HAL_VPATH_USE_BOTH			VXGE_HAL_FIFO_HOST_STEER_BOTH
+
+	u32				bandwidth;
+#define	VXGE_HAL_VPATH_BW_LIMIT_MAX			10000
+#define	VXGE_HAL_VPATH_BW_LIMIT_MIN			100
+#define	VXGE_HAL_VPATH_BW_LIMIT_DEFAULT			0XFFFFFFFF
+#define	VXGE_HAL_TX_BW_VPATH_LIMIT			8
+
+	u32				priority;
+#define	VXGE_HAL_VPATH_PRIORITY_MIN			0
+#define	VXGE_HAL_VPATH_PRIORITY_MAX			3
+#define	VXGE_HAL_VPATH_PRIORITY_DEFAULT			0XFFFFFFFF
+
+	u32				no_snoop;
+#define	VXGE_HAL_VPATH_NO_SNOOP_ENABLE			1
+#define	VXGE_HAL_VPATH_NO_SNOOP_DISABLE			0
+#define	VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT			\
+						VXGE_HAL_USE_FLASH_DEFAULT
+
+	vxge_hal_ring_config_t		ring;
+	vxge_hal_fifo_config_t		fifo;
+
+	vxge_hal_tim_intr_config_t	tti;
+	vxge_hal_tim_intr_config_t	rti;
+
+	u32				mtu;
+#define	VXGE_HAL_VPATH_MIN_INITIAL_MTU			VXGE_HAL_MIN_MTU
+#define	VXGE_HAL_VPATH_MAX_INITIAL_MTU			VXGE_HAL_MAX_MTU
+#define	VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU			\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_lsov2_en;
+#define	VXGE_HAL_VPATH_TPA_LSOV2_EN_ENABLE				1
+#define	VXGE_HAL_VPATH_TPA_LSOV2_EN_DISABLE				0
+#define	VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT			\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_ignore_frame_error;
+#define	VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_ENABLE			1
+#define	VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_DISABLE			0
+#define	VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_ipv6_keep_searching;
+#define	VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_ENABLE			1
+#define	VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_DISABLE			0
+#define	VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT	\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_l4_pshdr_present;
+#define	VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_ENABLE			1
+#define	VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_DISABLE			0
+#define	VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				tpa_support_mobile_ipv6_hdrs;
+#define	VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_ENABLE		1
+#define	VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DISABLE		0
+#define	VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT	\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+#define	VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT		\
+		VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT
+
+	u32				rpa_ipv4_tcp_incl_ph;
+#define	VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_ipv6_tcp_incl_ph;
+#define	VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_ipv4_udp_incl_ph;
+#define	VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_ipv6_udp_incl_ph;
+#define	VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_l4_incl_cf;
+#define	VXGE_HAL_VPATH_RPA_L4_INCL_CF_ENABLE				1
+#define	VXGE_HAL_VPATH_RPA_L4_INCL_CF_DISABLE				0
+#define	VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT			\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_strip_vlan_tag;
+#define	VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_l4_comp_csum;
+#define	VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_ENABLE				1
+#define	VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_DISABLE				0
+#define	VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_l3_incl_cf;
+#define	VXGE_HAL_VPATH_RPA_L3_INCL_CF_ENABLE				1
+#define	VXGE_HAL_VPATH_RPA_L3_INCL_CF_DISABLE				0
+#define	VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT			\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_l3_comp_csum;
+#define	VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_ENABLE				1
+#define	VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_DISABLE				0
+#define	VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_ucast_all_addr_en;
+#define	VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_mcast_all_addr_en;
+#define	VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE			1
+#define	VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE			0
+#define	VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT		\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_bcast_en;
+#define	VXGE_HAL_VPATH_RPA_BCAST_ENABLE					1
+#define	VXGE_HAL_VPATH_RPA_BCAST_DISABLE				0
+#define	VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT  VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				rpa_all_vid_en;
+#define	VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE				1
+#define	VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE				0
+#define	VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT			\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+	u32				vp_queue_l2_flow;
+#define	VXGE_HAL_VPATH_VP_Q_L2_FLOW_ENABLE				1
+#define	VXGE_HAL_VPATH_VP_Q_L2_FLOW_DISABLE				0
+#define	VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT			\
+						    VXGE_HAL_USE_FLASH_DEFAULT
+
+} vxge_hal_vp_config_t;
+
+/*
+ * struct vxge_hal_device_config_t - Device configuration.
+ * @dma_blockpool_min: Minimum blocks in the DMA pool
+ * @dma_blockpool_initial: Initial size of DMA Pool
+ * @dma_blockpool_incr: Number of blocks to request each time number of blocks
+ *		in the pool reaches dma_pool_min
+ * @dma_blockpool_max: Maximum blocks in DMA pool
+ * @mrpcim_config: MRPCIM section config. Used only for the privileged mode ULD
+ *		instance.
+ * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx
+ *		completions. Used in vxge_hal_device_handle_irq().
+ * @max_payload_size: Maximum TLP payload size for the device/fFunction.
+ *		As a Receiver, the Function/device must handle TLPs as large
+ *		as the set value; as . As a Transmitter, the Function/device
+ *		must not generate TLPs exceeding the set value. Permissible
+ *		values that can be programmed are indicated by the
+ *		Max_Payload_Size Supported in the Device Capabilities register
+ * @mmrb_count: Maximum Memory Read Byte Count. Use (VXGE_HAL_USE_FLASH_DEFAULT)
+ *		to use default BIOS value.
+ * @stats_refresh_time_sec: Sets the default interval for automatic stats
+ *		transfer to the host. This includes MAC stats as well as
+ *		PCI stats.
+ * @intr_mode: Line, or MSI-X interrupt.
+ *
+ * @dump_on_unknown: Dump adapter state ("about", statistics, registers)
+ *		on UNKNWON#.
+ * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#.
+ * @dump_on_critical: Dump adapter state ("about", statistics, registers)
+ *		on CRITICAL#.
+ * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on
+ *		 ECC error.
+ * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
+ * @rth_it_type: RTH IT table programming type
+ * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
+ * @rts_qos_en: TBD
+ * @rts_port_en: TBD
+ * @vp_config: Configuration for virtual paths
+ * @max_cqe_groups:  The maximum number of adapter CQE group blocks a CQRQ
+ *		can own at any one time.
+ * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that
+ *		this S-RQ can own at any one time.
+ * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for
+ *		WQEs before generating a message or interrupt.
+ * @refill_threshold_high:This field provides a hysteresis upper bound for
+ *		automatic adapter refill operations.
+ * @refill_threshold_low:This field provides a hysteresis lower bound for
+ *		automatic adapter refill operations.
+ * @eol_policy: This field sets the policy for handling the end of list
+ *		condition.
+ *		2'b00 - When EOL is reached, poll until last block wrapper
+ *			size is no longer 0.
+ *		2'b01 - Send UMQ message when EOL is reached.
+ *		2'b1x - Poll until the poll_count_max is reached and
+ *			if still EOL, send UMQ message
+ * @eol_poll_count_max:sets the maximum number of times the queue manager will
+ *		poll fora non-zero block wrapper before giving up and sending
+ *		a UMQ message
+ * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be
+ *		held by a session at any one time.
+ * @poll_or_doorbell: TBD
+ * @stats_read_method: Stats read method.(DMA or PIO)
+ * @device_poll_millis: Specify the interval (in mulliseconds) to wait for
+ *		register reads
+ * @debug_level: Debug logging level. see vxge_debug_level_e {}
+ * @debug_mask: Module mask for debug logging level. for masks see vxge_debug.h
+ * @lro_enable: SW LRO enable mask
+ * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable.
+ *
+ * X3100 configuration.
+ * Contains per-device configuration parameters, including:
+ * - latency timer (settable via PCI configuration space);
+ * - maximum number of split transactions;
+ * - maximum number of shared splits;
+ * - stats sampling interval, etc.
+ *
+ * In addition, vxge_hal_device_config_t {} includes "subordinate"
+ * configurations, including:
+ * - fifos and rings;
+ * - MAC (done at firmware level).
+ *
+ * See X3100 User Guide for more details.
+ * Note: Valid (min, max) range for each attribute is specified in the body of
+ * the vxge_hal_device_config_t {} structure. Please refer to the
+ * corresponding include file.
+ * See also: vxge_hal_tim_intr_config_t {}.
+ */
+typedef struct vxge_hal_device_config_t {
+	u32				dma_blockpool_min;
+	u32				dma_blockpool_initial;
+	u32				dma_blockpool_incr;
+	u32				dma_blockpool_max;
+#define	VXGE_HAL_MIN_DMA_BLOCK_POOL_SIZE		0
+#define	VXGE_HAL_INITIAL_DMA_BLOCK_POOL_SIZE		0
+#define	VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE		4
+#define	VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE		4096
+
+	vxge_hal_mrpcim_config_t	mrpcim_config;
+
+	u32				isr_polling_cnt;
+#define	VXGE_HAL_MIN_ISR_POLLING_CNT			0
+#define	VXGE_HAL_MAX_ISR_POLLING_CNT			65536
+#define	VXGE_HAL_DEF_ISR_POLLING_CNT			1
+
+	u32				max_payload_size;
+#define	VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE	    VXGE_HAL_USE_FLASH_DEFAULT
+#define	VXGE_HAL_MAX_PAYLOAD_SIZE_128			0
+#define	VXGE_HAL_MAX_PAYLOAD_SIZE_256			1
+#define	VXGE_HAL_MAX_PAYLOAD_SIZE_512			2
+#define	VXGE_HAL_MAX_PAYLOAD_SIZE_1024			3
+#define	VXGE_HAL_MAX_PAYLOAD_SIZE_2048			4
+#define	VXGE_HAL_MAX_PAYLOAD_SIZE_4096			5
+
+	u32				mmrb_count;
+#define	VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT	    VXGE_HAL_USE_FLASH_DEFAULT
+#define	VXGE_HAL_MMRB_COUNT_128				0
+#define	VXGE_HAL_MMRB_COUNT_256				1
+#define	VXGE_HAL_MMRB_COUNT_512				2
+#define	VXGE_HAL_MMRB_COUNT_1024			3
+#define	VXGE_HAL_MMRB_COUNT_2048			4
+#define	VXGE_HAL_MMRB_COUNT_4096			5
+
+	u32				stats_refresh_time_sec;
+#define	VXGE_HAL_STATS_REFRESH_DISABLE			0
+#define	VXGE_HAL_MIN_STATS_REFRESH_TIME			1
+#define	VXGE_HAL_MAX_STATS_REFRESH_TIME			300
+#define	VXGE_HAL_USE_FLASH_DEFAULT_STATS_REFRESH_TIME	30
+
+	u32				intr_mode;
+#define	VXGE_HAL_INTR_MODE_IRQLINE			0
+#define	VXGE_HAL_INTR_MODE_MSIX				1
+#define	VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT		2
+#define	VXGE_HAL_INTR_MODE_EMULATED_INTA		3
+#define	VXGE_HAL_INTR_MODE_DEF				0
+
+	u32				dump_on_unknown;
+#define	VXGE_HAL_DUMP_ON_UNKNOWN_DISABLE		0
+#define	VXGE_HAL_DUMP_ON_UNKNOWN_ENABLE			1
+#define	VXGE_HAL_DUMP_ON_UNKNOWN_DEFAULT		0
+
+	u32				dump_on_serr;
+#define	VXGE_HAL_DUMP_ON_SERR_DISABLE			0
+#define	VXGE_HAL_DUMP_ON_SERR_ENABLE			1
+#define	VXGE_HAL_DUMP_ON_SERR_DEFAULT			0
+
+	u32				dump_on_critical;
+#define	VXGE_HAL_DUMP_ON_CRITICAL_DISABLE		0
+#define	VXGE_HAL_DUMP_ON_CRITICAL_ENABLE		1
+#define	VXGE_HAL_DUMP_ON_CRITICAL_DEFAULT		0
+
+	u32				dump_on_eccerr;
+#define	VXGE_HAL_DUMP_ON_ECCERR_DISABLE			0
+#define	VXGE_HAL_DUMP_ON_ECCERR_ENABLE			1
+#define	VXGE_HAL_DUMP_ON_ECCERR_DEFAULT			0
+
+	u32				rth_en;
+#define	VXGE_HAL_RTH_DISABLE				0
+#define	VXGE_HAL_RTH_ENABLE				1
+#define	VXGE_HAL_RTH_DEFAULT				0
+
+	u32				rth_it_type;
+#define	VXGE_HAL_RTH_IT_TYPE_SOLO_IT			0
+#define	VXGE_HAL_RTH_IT_TYPE_MULTI_IT			1
+#define	VXGE_HAL_RTH_IT_TYPE_DEFAULT			0
+
+	u32				rts_mac_en;
+#define	VXGE_HAL_RTS_MAC_DISABLE			0
+#define	VXGE_HAL_RTS_MAC_ENABLE				1
+#define	VXGE_HAL_RTS_MAC_DEFAULT			0
+
+	u32				rts_qos_en;
+#define	VXGE_HAL_RTS_QOS_DISABLE			0
+#define	VXGE_HAL_RTS_QOS_ENABLE				1
+#define	VXGE_HAL_RTS_QOS_DEFAULT			0
+
+	u32				rts_port_en;
+#define	VXGE_HAL_RTS_PORT_DISABLE			0
+#define	VXGE_HAL_RTS_PORT_ENABLE			1
+#define	VXGE_HAL_RTS_PORT_DEFAULT			0
+
+	vxge_hal_vp_config_t		vp_config[VXGE_HAL_MAX_VIRTUAL_PATHS];
+
+	u32				max_cqe_groups;
+#define	VXGE_HAL_MIN_MAX_CQE_GROUPS			1
+#define	VXGE_HAL_MAX_MAX_CQE_GROUPS			16
+#define	VXGE_HAL_DEF_MAX_CQE_GROUPS			16
+
+	u32				max_num_wqe_od_groups;
+#define	VXGE_HAL_MIN_MAX_NUM_OD_GROUPS			1
+#define	VXGE_HAL_MAX_MAX_NUM_OD_GROUPS			16
+#define	VXGE_HAL_DEF_MAX_NUM_OD_GROUPS			16
+
+	u32				no_wqe_threshold;
+#define	VXGE_HAL_MIN_NO_WQE_THRESHOLD			1
+#define	VXGE_HAL_MAX_NO_WQE_THRESHOLD			16
+#define	VXGE_HAL_DEF_NO_WQE_THRESHOLD			16
+
+	u32				refill_threshold_high;
+#define	VXGE_HAL_MIN_REFILL_THRESHOLD_HIGH		1
+#define	VXGE_HAL_MAX_REFILL_THRESHOLD_HIGH		16
+#define	VXGE_HAL_DEF_REFILL_THRESHOLD_HIGH		16
+
+	u32				refill_threshold_low;
+#define	VXGE_HAL_MIN_REFILL_THRESHOLD_LOW		1
+#define	VXGE_HAL_MAX_REFILL_THRESHOLD_LOW		16
+#define	VXGE_HAL_DEF_REFILL_THRESHOLD_LOW		16
+
+	u32				ack_blk_limit;
+#define	VXGE_HAL_MIN_ACK_BLOCK_LIMIT			1
+#define	VXGE_HAL_MAX_ACK_BLOCK_LIMIT			16
+#define	VXGE_HAL_DEF_ACK_BLOCK_LIMIT			16
+
+	u32				poll_or_doorbell;
+#define	VXGE_HAL_POLL_OR_DOORBELL_POLL			1
+#define	VXGE_HAL_POLL_OR_DOORBELL_DOORBELL		0
+#define	VXGE_HAL_POLL_OR_DOORBELL_DEFAULT		1
+
+	u32				stats_read_method;
+#define	VXGE_HAL_STATS_READ_METHOD_DMA			1
+#define	VXGE_HAL_STATS_READ_METHOD_PIO			0
+#define	VXGE_HAL_STATS_READ_METHOD_DEFAULT		1
+
+	u32				device_poll_millis;
+#define	VXGE_HAL_MIN_DEVICE_POLL_MILLIS			1
+#define	VXGE_HAL_MAX_DEVICE_POLL_MILLIS			100000
+#define	VXGE_HAL_DEF_DEVICE_POLL_MILLIS			1000
+
+	vxge_debug_level_e		debug_level;
+
+	u32				debug_mask;
+
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+	u32				tracebuf_size;
+#define	VXGE_HAL_MIN_CIRCULAR_ARR			4096
+#define	VXGE_HAL_MAX_CIRCULAR_ARR			65536
+#define	VXGE_HAL_DEF_CIRCULAR_ARR			16384
+#endif
+} vxge_hal_device_config_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_CONFIG_H */
diff --git a/sys/dev/vxge/include/vxgehal-ll.h b/sys/dev/vxge/include/vxgehal-ll.h
new file mode 100644
index 000000000000..9fc416fa9c31
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-ll.h
@@ -0,0 +1,6121 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_LL_H
+#define	VXGE_HAL_LL_H
+
+#include <dev/vxge/include/vxgehal-version.h>
+#include <dev/vxge/include/vxge-defs.h>
+#include <dev/vxge/include/vxge-os-pal.h>
+#include "vxgehal-status.h"
+#include <dev/vxge/include/vxgehal-types.h>
+#include <dev/vxge/include/vxge-debug.h>
+#include <dev/vxge/include/vxge-list.h>
+#include <dev/vxge/include/vxge-queue.h>
+#include <dev/vxge/include/vxgehal-config.h>
+#include <dev/vxge/include/vxgehal-stats.h>
+#include <dev/vxge/include/vxgehal-mgmt.h>
+#include <dev/vxge/include/vxgehal-mgmtaux.h>
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * Driver
+ */
+
+/*
+ * enum vxge_hal_xpak_alarm_type_e - XPAK Alarm types
+ * @VXGE_HAL_XPAK_ALARM_EXCESS_TEMP: Excess temparature alarm
+ * @VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT: Excess bias current alarm
+ * @VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT: Excess laser output alarm
+ *
+ * XPAK alarm types
+ */
+typedef enum vxge_hal_xpak_alarm_type_e {
+	VXGE_HAL_XPAK_ALARM_EXCESS_TEMP		= 1,
+	VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT	= 2,
+	VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT	= 3,
+} vxge_hal_xpak_alarm_type_e;
+
+/*
+ * function vxge_uld_sched_timer_cb_f - Per-device periodic timer
+ * callback.
+ * @devh: HAL device handle.
+ * @userdata: Per-device user data (a.k.a. context) specified via
+ * vxge_hal_device_initialize().
+ *
+ * Periodic or one-shot timer callback. If specified (that is, not NULL)
+ * HAL invokes this callback periodically. The call is performed in the
+ * interrupt context, or more exactly, in the context of HAL's ISR
+ * vxge_hal_device_continue_irq().
+ *
+ * See also: vxge_hal_device_initialize {}
+ */
+typedef void (*vxge_uld_sched_timer_cb_f) (
+    vxge_hal_device_h devh,
+    void *userdata);
+
+/*
+ * function vxge_uld_link_up_f - Link-Up callback provided by upper-layer
+ * driver.
+ * @devh: HAL device handle.
+ * @userdata: Opaque context set by the ULD via
+ * vxge_hal_device_private_set()
+ * (typically - at HAL device iinitialization time).
+ *
+ * Link-up notification callback provided by the ULD.
+ * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}.
+ *
+ * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_down_f {},
+ * vxge_hal_driver_initialize(), vxge_hal_device_private_set().
+ */
+typedef void (*vxge_uld_link_up_f) (
+    vxge_hal_device_h devh,
+    void *userdata);
+
+/*
+ * function vxge_uld_link_down_f - Link-Down callback provided by
+ * upper-layer driver.
+ * @devh: HAL device handle.
+ * @userdata: Opaque context set by the ULD via
+ * vxge_hal_device_private_set()
+ * (typically - at HAL device iinitialization time).
+ *
+ * Link-Down notification callback provided by the upper-layer driver.
+ * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}.
+ *
+ * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_up_f {},
+ * vxge_hal_driver_initialize(), vxge_hal_device_private_set().
+ */
+typedef void (*vxge_uld_link_down_f) (
+    vxge_hal_device_h devh,
+    void *userdata);
+
+/*
+ * function vxge_uld_crit_err_f - Critical Error notification callback.
+ * @devh: HAL device handle.
+ * @userdata: Opaque context set by the ULD via
+ * vxge_hal_device_private_set()
+ * (typically - at HAL device iinitialization time).
+ * @type: Enumerated hw error, e.g.: double ECC.
+ * @serr_data: X3100 status.
+ * @ext_data: Extended data. The contents depends on the @type.
+ *
+ * Critical error notification callback provided by the upper-layer driver.
+ * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}.
+ *
+ * See also: vxge_hal_uld_cbs_t {}, vxge_hal_event_e {},
+ * vxge_hal_device_private_set(), vxge_hal_driver_initialize().
+ */
+typedef void (*vxge_uld_crit_err_f) (
+    vxge_hal_device_h devh,
+    void *userdata,
+    vxge_hal_event_e type,
+    u64 ext_data);
+
+/*
+ * function vxge_uld_xpak_alarm_log_f - ULD "XPAK alarm log" callback.
+ * @devh: HAL device handle.
+ * @port: Port number
+ * @type: XPAK Alarm type
+ *
+ * Unless NULL is specified, HAL invokes the callback after checking XPAK
+ * counters
+ */
+typedef void (*vxge_uld_xpak_alarm_log_f) (
+    vxge_hal_device_h devh,
+    u32 port,
+    vxge_hal_xpak_alarm_type_e type);
+
+/*
+ * struct vxge_hal_uld_cbs_t - Upper-layer driver "slow-path" callbacks.
+ * @link_up: See vxge_uld_link_up_f {}.
+ * @link_down: See vxge_uld_link_down_f {}.
+ * @crit_err: See vxge_uld_crit_err_f {}.
+ * @sched_timer: See vxge_uld_sched_timer_cb_f {}.
+ * @xpak_alarm_log:
+ *
+ * Upper layer driver slow-path (per-driver) callbacks.
+ * Implemented by ULD and provided to HAL via
+ * vxge_hal_driver_initialize().
+ * Note that these callbacks are not mandatory: HAL will not invoke
+ * a callback if NULL is specified.
+ *
+ * See also: vxge_hal_driver_initialize().
+ */
+typedef struct vxge_hal_uld_cbs_t {
+	vxge_uld_link_up_f		link_up;
+	vxge_uld_link_down_f		link_down;
+	vxge_uld_crit_err_f		crit_err;
+	vxge_uld_sched_timer_cb_f	sched_timer;
+	vxge_uld_xpak_alarm_log_f	xpak_alarm_log;
+} vxge_hal_uld_cbs_t;
+
+/*
+ * vxge_hal_driver_initialize - Initialize HAL.
+ * @config: HAL configuration, see vxge_hal_driver_config_t {}.
+ * @uld_callbacks: Upper-layer driver callbacks, e.g. link-up.
+ *
+ * HAL initialization entry point. Not to confuse with device initialization
+ * (note that HAL "contains" zero or more X3100 devices).
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_BAD_DRIVER_CONFIG - Driver configuration params invalid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_driver_initialize(
+    vxge_hal_driver_config_t *config,
+    vxge_hal_uld_cbs_t *uld_callbacks);
+
+/*
+ * vxge_hal_driver_debug_set - Set the debug module, level and timestamp
+ * @level: Debug level as defined in enum vxge_debug_level_e
+ *
+ * This routine is used to dynamically change the debug output
+ */
+void
+vxge_hal_driver_debug_set(
+    vxge_debug_level_e level);
+
+/*
+ * vxge_hal_driver_debug_get - Get the debug level
+ *
+ * This routine returns the current debug level set
+ */
+u32
+vxge_hal_driver_debug_get(void);
+
+/*
+ * vxge_hal_driver_terminate - Terminate HAL.
+ *
+ * HAL termination entry point.
+ */
+void
+vxge_hal_driver_terminate(void);
+
+void *
+vxge_hal_device_get_legacy_reg(pci_dev_h pdev, pci_reg_h regh, u8 *bar0);
+
+/*
+ * RX Descriptor
+ */
+/*
+ * enum vxge_hal_rxd_state_e - Descriptor (RXD) state.
+ * @VXGE_HAL_RXD_STATE_NONE: Invalid state.
+ * @VXGE_HAL_RXD_STATE_AVAIL: Descriptor is available for reservation.
+ * @VXGE_HAL_RXD_STATE_POSTED: Descriptor is posted for processing by the
+ * device.
+ * @VXGE_HAL_RXD_STATE_FREED: Descriptor is free and can be reused for
+ * filling-in and posting later.
+ *
+ * X3100/HAL descriptor states.
+ *
+ */
+typedef enum vxge_hal_rxd_state_e {
+	VXGE_HAL_RXD_STATE_NONE		= 0,
+	VXGE_HAL_RXD_STATE_AVAIL	= 1,
+	VXGE_HAL_RXD_STATE_POSTED	= 2,
+	VXGE_HAL_RXD_STATE_FREED	= 3
+} vxge_hal_rxd_state_e;
+
+/*
+ * Ring
+ */
+
+/*
+ * struct vxge_hal_ring_rxd_info_t - Extended information associated with a
+ *			  completed ring descriptor.
+ * @syn_flag: SYN flag
+ * @is_icmp: Is ICMP
+ * @fast_path_eligible: Fast Path Eligible flag
+ * @l3_cksum_valid: in L3 checksum is valid
+ * @l3_cksum: Result of IP checksum check (by X3100 hardware).
+ *	    This field containing VXGE_HAL_L3_CKSUM_OK would mean that
+ *	    the checksum is correct, otherwise - the datagram is
+ *	    corrupted.
+ * @l4_cksum_valid: in L4 checksum is valid
+ * @l4_cksum: Result of TCP/UDP checksum check (by X3100 hardware).
+ *	    This field containing VXGE_HAL_L4_CKSUM_OK would mean that
+ *	    the checksum is correct. Otherwise - the packet is
+ *	    corrupted.
+ * @frame: Zero or more of vxge_hal_frame_type_e flags.
+ *	    See vxge_hal_frame_type_e {}.
+ * @proto: zero or more of vxge_hal_frame_proto_e flags.  Reporting bits for
+ *	    various higher-layer protocols, including (but note restricted to)
+ *	    TCP and UDP. See vxge_hal_frame_proto_e {}.
+ * @is_vlan: If vlan tag is valid
+ * @vlan: VLAN tag extracted from the received frame.
+ * @rth_bucket: RTH bucket
+ * @rth_it_hit: Set, If RTH hash value calculated by the X3100 hardware
+ *	    has a matching entry in the Indirection table.
+ * @rth_spdm_hit: Set, If RTH hash value calculated by the X3100 hardware
+ *	    has a matching entry in the Socket Pair Direct Match table.
+ * @rth_hash_type: RTH hash code of the function used to calculate the hash.
+ * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by X3100
+ *	    hardware if RTH is enabled.
+ */
+typedef struct vxge_hal_ring_rxd_info_t {
+	u32	syn_flag;
+	u32	is_icmp;
+	u32	fast_path_eligible;
+	u32	l3_cksum_valid;
+	u32	l3_cksum;
+	u32	l4_cksum_valid;
+	u32	l4_cksum;
+	u32	frame;
+	u32	proto;
+	u32	is_vlan;
+#define	VXGE_HAL_VLAN_VID_MASK 0xfff
+	u32	vlan;
+	u32	rth_bucket;
+	u32	rth_it_hit;
+	u32	rth_spdm_hit;
+	u32	rth_hash_type;
+	u32	rth_value;
+} vxge_hal_ring_rxd_info_t;
+
+/*
+ * enum vxge_hal_frame_type_e - Ethernet frame format.
+ * @VXGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format.
+ * @VXGE_HAL_FRAME_TYPE_LLC: LLC format.
+ * @VXGE_HAL_FRAME_TYPE_SNAP: SNAP format.
+ * @VXGE_HAL_FRAME_TYPE_IPX: IPX format.
+ *
+ * Ethernet frame format.
+ */
+typedef enum vxge_hal_frame_type_e {
+	VXGE_HAL_FRAME_TYPE_DIX			= 0x0,
+	VXGE_HAL_FRAME_TYPE_LLC			= 0x1,
+	VXGE_HAL_FRAME_TYPE_SNAP		= 0x2,
+	VXGE_HAL_FRAME_TYPE_IPX			= 0x3,
+} vxge_hal_frame_type_e;
+
+typedef enum vxge_hal_tcp_option_e {
+
+	VXGE_HAL_TCPOPT_NOP = 1,	/* Padding */
+	VXGE_HAL_TCPOPT_EOL = 0,	/* End of options */
+	VXGE_HAL_TCPOPT_MSS = 2,	/* Segment size negotiating */
+	VXGE_HAL_TCPOPT_WINDOW = 3,	/* Window scaling */
+	VXGE_HAL_TCPOPT_SACK_PERM = 4,	/* SACK Permitted */
+	VXGE_HAL_TCPOPT_SACK = 5,	/* SACK Block */
+	VXGE_HAL_TCPOPT_TIMESTAMP = 8,	/* Better RTT estimations/PAWS */
+	VXGE_HAL_TCPOPT_MD5SIG = 19,	/* MD5 Signature (RFC2385) */
+	VXGE_HAL_TCPOLEN_TIMESTAMP = 10,
+	VXGE_HAL_TCPOLEN_TSTAMP_ALIGNED = 12
+
+} vxge_hal_tcp_option_e;
+
+/*
+ * enum vxge_hal_frame_proto_e - Higher-layer ethernet protocols.
+ * @VXGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN.
+ * @VXGE_HAL_FRAME_PROTO_IPV4: IPv4.
+ * @VXGE_HAL_FRAME_PROTO_IPV6: IPv6.
+ * @VXGE_HAL_FRAME_PROTO_IP_FRAG: IP fragmented.
+ * @VXGE_HAL_FRAME_PROTO_TCP: TCP.
+ * @VXGE_HAL_FRAME_PROTO_UDP: UDP.
+ * @VXGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
+ *
+ * Higher layer ethernet protocols and options.
+ */
+typedef enum vxge_hal_frame_proto_e {
+	VXGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80,
+	VXGE_HAL_FRAME_PROTO_IPV4		= 0x10,
+	VXGE_HAL_FRAME_PROTO_IPV6		= 0x08,
+	VXGE_HAL_FRAME_PROTO_IP_FRAG		= 0x04,
+	VXGE_HAL_FRAME_PROTO_TCP		= 0x02,
+	VXGE_HAL_FRAME_PROTO_UDP		= 0x01,
+	VXGE_HAL_FRAME_PROTO_TCP_OR_UDP		= (VXGE_HAL_FRAME_PROTO_TCP | \
+						VXGE_HAL_FRAME_PROTO_UDP)
+} vxge_hal_frame_proto_e;
+
+/*
+ * enum vxge_hal_ring_tcode_e - Transfer codes returned by adapter
+ * @VXGE_HAL_RING_T_CODE_OK: Transfer ok.
+ * @VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation
+ *		configuration mismatch.
+ * @VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation
+ *		configuration mismatch.
+ * @VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum
+ *		presentation configuration mismatch.
+ * @VXGE_HAL_RING_T_CODE_L3_PKT_ERR: Layer 3 error¸unparseable packet,
+ *		such as unknown IPv6 header.
+ * @VXGE_HAL_RING_T_CODE_L2_FRM_ERR: Layer 2 error¸frame integrity
+ *		error, such as FCS or ECC).
+ * @VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR: Buffer size error¸the RxD buffer(
+ *		s) were not appropriately sized and data loss occurred.
+ * @VXGE_HAL_RING_T_CODE_INT_ECC_ERR: Internal ECC error¸RxD corrupted.
+ * @VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW: Benign overflow¸the contents of
+ *		Segment1 exceeded the capacity of Buffer1 and the remainder
+ *		was placed in Buffer2. Segment2 now starts in Buffer3.
+ *		No data loss or errors occurred.
+ * @VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0¸one of the RxDs
+ *		assigned buffers has a size of 0 bytes.
+ * @VXGE_HAL_RING_T_CODE_FRM_DROP: Frame dropped¸either due to
+ *		VPath Reset or because of a VPIN mismatch.
+ * @VXGE_HAL_RING_T_CODE_UNUSED: Unused
+ * @VXGE_HAL_RING_T_CODE_MULTI_ERR: Multiple errors¸more than one
+ *		transfer code condition occurred.
+ *
+ * Transfer codes returned by adapter.
+ */
+typedef enum vxge_hal_ring_tcode_e {
+	VXGE_HAL_RING_T_CODE_OK				= 0x0,
+	VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH		= 0x1,
+	VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH		= 0x2,
+	VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH	= 0x3,
+	VXGE_HAL_RING_T_CODE_L3_PKT_ERR			= 0x5,
+	VXGE_HAL_RING_T_CODE_L2_FRM_ERR			= 0x6,
+	VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR		= 0x7,
+	VXGE_HAL_RING_T_CODE_INT_ECC_ERR		= 0x8,
+	VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW		= 0x9,
+	VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF		= 0xA,
+	VXGE_HAL_RING_T_CODE_FRM_DROP			= 0xC,
+	VXGE_HAL_RING_T_CODE_UNUSED			= 0xE,
+	VXGE_HAL_RING_T_CODE_MULTI_ERR			= 0xF
+} vxge_hal_ring_tcode_e;
+
+/*
+ * enum vxge_hal_ring_hash_type_e - RTH hash types
+ * @VXGE_HAL_RING_HASH_TYPE_NONE: No Hash
+ * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV4: TCP IPv4
+ * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV4: UDP IPv4
+ * @VXGE_HAL_RING_HASH_TYPE_IPV4: IPv4
+ * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV6: TCP IPv6
+ * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV6: UDP IPv6
+ * @VXGE_HAL_RING_HASH_TYPE_IPV6: IPv6
+ * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX: TCP IPv6 extension
+ * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX: UDP IPv6 extension
+ * @VXGE_HAL_RING_HASH_TYPE_IPV6_EX: IPv6 extension
+ *
+ * RTH hash types
+ */
+typedef enum vxge_hal_ring_hash_type_e {
+	VXGE_HAL_RING_HASH_TYPE_NONE			= 0x0,
+	VXGE_HAL_RING_HASH_TYPE_TCP_IPV4		= 0x1,
+	VXGE_HAL_RING_HASH_TYPE_UDP_IPV4		= 0x2,
+	VXGE_HAL_RING_HASH_TYPE_IPV4			= 0x3,
+	VXGE_HAL_RING_HASH_TYPE_TCP_IPV6		= 0x4,
+	VXGE_HAL_RING_HASH_TYPE_UDP_IPV6		= 0x5,
+	VXGE_HAL_RING_HASH_TYPE_IPV6			= 0x6,
+	VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX		= 0x7,
+	VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX		= 0x8,
+	VXGE_HAL_RING_HASH_TYPE_IPV6_EX			= 0x9
+} vxge_hal_ring_hash_type_e;
+
+/*
+ * struct vxge_hal_ring_rxd_1_t - One buffer mode RxD for ring
+ * @host_control: This field is exclusively for host use and is "readonly"
+ *	    from the adapter's perspective.
+ * @control_0:Bits 0 to 6 - RTH_Bucket get
+ *	    Bit 7 - Own Descriptor ownership bit. This bit is set to 1 by the
+ *	    host, and is set to 0 by the adapter.
+ *		 0 - Host owns RxD and buffer.
+ *		 1 - The adapter owns RxD and buffer.
+ *	    Bit 8 - Fast_Path_Eligible When set, indicates that the received
+ *	   frame meets all of the criteria for fast path processing.
+ *	   The required criteria are as follows:
+ *	   !SYN &
+ *	   (Transfer_Code == "Transfer OK") &
+ *	   (!Is_IP_Fragment) &
+ *	   ((Is_IPv4 & computed_L3_checksum == 0xFFFF) |
+ *	   (Is_IPv6)) &
+ *	   ((Is_TCP & computed_L4_checksum == 0xFFFF) |
+ *	   (Is_UDP & (computed_L4_checksum == 0xFFFF |
+ *	   computed _L4_checksum == 0x0000)))
+ *	   (same meaning for all RxD buffer modes)
+ *		 Bit 9 - L3 Checksum Correct
+ *		 Bit 10 - L4 Checksum Correct
+ *		 Bit 11 - Reserved
+ *		 Bit 12 to 15 - This field is written by the adapter. It is used
+ *		 to report the status of the frame transfer to the host.
+ *		 0x0 - Transfer OK
+ *		 0x4 - RDA Failure During Transfer
+ *		 0x5 - Unparseable Packet, such as unknown IPv6 header.
+ *		 0x6 - Frame integrity error (FCS or ECC).
+ *		 0x7 - Buffer Size Error. The provided buffer(s) were not
+ *		 appropriately sized and data loss occurred.
+ *		 0x8 - Internal ECC Error. RxD corrupted.
+ *		 0x9 - IPv4 Checksum error
+ *		 0xA - TCP/UDP Checksum error
+ *		 0xF - Unknown Error or Multiple Error. Indicates an unknown
+ *		 problem or that more than one of transfer codes is set.
+ *		 Bit 16 - SYN The adapter sets this field to indicate that the
+ *		 incoming frame contained a TCP segment with its SYN bit set
+ *	   and its ACK bit NOT set. (same meaning for all RxD buffer modes)
+ *		 Bit 17 - Is ICMP
+ *		 Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the
+ *		 Socket
+ *	   Pair Direct Match Table and the frame was steered based on SPDM.
+ *		 Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the
+ *	   Indirection Table and the frame was steered based on hash
+ *	   indirection.
+ *		 Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type)
+ *	   that was used to calculate the hash.
+ *		 Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged.
+ *		 Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation
+ *	   of the received frame.
+ *		 0x0 - Ethernet DIX
+ *		 0x1 - LLC
+ *		 0x2 - SNAP (includes Jumbo-SNAP)
+ *		 0x3 - IPX
+ *		 Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet.
+ *		 Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet.
+ *		 Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a
+ *		 fragmented IP packet.
+ *		 Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment.
+ *		 Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message.
+ *		 Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that
+ *	   arrived with the frame. If the resulting computed IPv4 header
+ *	   checksum for the frame did not produce the expected 0xFFFF value,
+ *	   then the transfer code would be set to 0x9.
+ *		 Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that
+ *	   arrived with the frame. If the resulting computed TCP/UDP checksum
+ *	   for the frame did not produce the expected 0xFFFF value, then the
+ *	   transfer code would be set to 0xA.
+ * @control_1:Bits 0 to 1 - Reserved
+ *	   Bits 2 to 15 - Buffer0_Size.This field is set by the host and
+ *	   eventually overwritten by the adapter. The host writes the
+ *	   available buffer size in bytes when it passes the descriptor to
+ *	   the adapter. When a frame is delivered the host, the adapter
+ *	   populates this field with the number of bytes written into the
+ *	   buffer. The largest supported buffer is 16, 383 bytes.
+ *		 Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid
+ *		 if RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero.
+ *		 Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable
+ *	   portion of the VLAN tag, if one was detected by the adapter.
+ *	   This field is populated even if VLAN-tag stripping is enabled.
+ * @buffer0_ptr: Pointer to buffer. This field is populated by the driver.
+ *
+ * One buffer mode RxD for ring structure
+ */
+typedef struct vxge_hal_ring_rxd_1_t {
+	u64 host_control;
+	u64 control_0;
+#define	VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0)		    bVAL7(ctrl0, 0)
+#define	VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER		    vBIT(val, 0, 7)
+
+#define	VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0)		    bVAL1(ctrl0, 7)
+#define	VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER		    mBIT(7)
+
+#define	VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0)	    bVAL1(ctrl0, 8)
+#define	VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE		    mBIT(8)
+
+#define	VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0)	    bVAL1(ctrl0, 9)
+#define	VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT		    mBIT(9)
+
+#define	VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0)	    bVAL1(ctrl0, 10)
+#define	VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT		    mBIT(10)
+
+#define	VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0)		    bVAL4(ctrl0, 12)
+#define	VXGE_HAL_RING_RXD_T_CODE(val)			    vBIT(val, 12, 4)
+#define	VXGE_HAL_RING_RXD_T_CODE_OK			VXGE_HAL_RING_T_CODE_OK
+#define	VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH		\
+				    VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH
+#define	VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH		\
+				    VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH
+#define	VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH		\
+				    VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH
+#define	VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR	VXGE_HAL_RING_T_CODE_L3_PKT_ERR
+#define	VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR	VXGE_HAL_RING_T_CODE_L2_FRM_ERR
+#define	VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR			\
+				    VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR
+#define	VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR	VXGE_HAL_RING_T_CODE_INT_ECC_ERR
+#define	VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW			\
+				    VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW
+#define	VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF			\
+				    VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF
+#define	VXGE_HAL_RING_RXD_T_CODE_FRM_DROP	VXGE_HAL_RING_T_CODE_FRM_DROP
+#define	VXGE_HAL_RING_RXD_T_CODE_UNUSED		VXGE_HAL_RING_T_CODE_UNUSED
+#define	VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR	VXGE_HAL_RING_T_CODE_MULTI_ERR
+
+#define	VXGE_HAL_RING_RXD_SYN_GET(ctrl0)		    bVAL1(ctrl0, 16)
+#define	VXGE_HAL_RING_RXD_SYN				    mBIT(16)
+
+#define	VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0)		    bVAL1(ctrl0, 17)
+#define	VXGE_HAL_RING_RXD_IS_ICMP			    mBIT(17)
+
+#define	VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0)	    bVAL1(ctrl0, 18)
+#define	VXGE_HAL_RING_RXD_RTH_SPDM_HIT			    mBIT(18)
+
+#define	VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0)		    bVAL1(ctrl0, 19)
+#define	VXGE_HAL_RING_RXD_RTH_IT_HIT			    mBIT(19)
+
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0)	    bVAL4(ctrl0, 20)
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val)		    vBIT(val, 20, 4)
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE	VXGE_HAL_RING_HASH_TYPE_NONE
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4		\
+						VXGE_HAL_RING_HASH_TYPE_TCP_IPV4
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4		\
+						VXGE_HAL_RING_HASH_TYPE_UDP_IPV4
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4	VXGE_HAL_RING_HASH_TYPE_IPV4
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6		\
+						VXGE_HAL_RING_HASH_TYPE_TCP_IPV6
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6		\
+						VXGE_HAL_RING_HASH_TYPE_UDP_IPV6
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6	VXGE_HAL_RING_HASH_TYPE_IPV6
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \
+					    VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \
+					    VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX
+#define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX	VXGE_HAL_RING_HASH_TYPE_IPV6_EX
+
+#define	VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0)		    bVAL1(ctrl0, 24)
+#define	VXGE_HAL_RING_RXD_IS_VLAN			    mBIT(24)
+
+#define	VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0)	    bVAL2(ctrl0, 25)
+#define	VXGE_HAL_RING_RXD_ETHER_ENCAP(val)		    vBIT(val, 25, 2)
+#define	VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX		VXGE_HAL_FRAME_TYPE_DIX
+#define	VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC		VXGE_HAL_FRAME_TYPE_LLC
+#define	VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP		VXGE_HAL_FRAME_TYPE_SNAP
+#define	VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX		VXGE_HAL_FRAME_TYPE_IPX
+
+#define	VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0)		    bVAL1(ctrl0, 27)
+#define	VXGE_HAL_RING_RXD_IS_IPV4			    mBIT(27)
+
+#define	VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0)		    bVAL1(ctrl0, 28)
+#define	VXGE_HAL_RING_RXD_IS_IPV6			    mBIT(28)
+
+#define	VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0)	    bVAL1(ctrl0, 29)
+#define	VXGE_HAL_RING_RXD_IS_IPV_FRAG			    mBIT(29)
+
+#define	VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0)		    bVAL1(ctrl0, 30)
+#define	VXGE_HAL_RING_RXD_IS_TCP				mBIT(30)
+
+#define	VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0)		    bVAL1(ctrl0, 31)
+#define	VXGE_HAL_RING_RXD_IS_UDP				mBIT(31)
+
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0)	    bVAL5(ctrl0, 27)
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO(val)		    vBIT(val, 27, 5)
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4	    VXGE_HAL_FRAME_PROTO_IPV4
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6	    VXGE_HAL_FRAME_PROTO_IPV6
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG	    VXGE_HAL_FRAME_PROTO_IP_FRAG
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_TCP	    VXGE_HAL_FRAME_PROTO_TCP
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_UDP	    VXGE_HAL_FRAME_PROTO_UDP
+#define	VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP    (VXGE_HAL_FRAME_PROTO_TCP |\
+						    VXGE_HAL_FRAME_PROTO_UDP)
+
+#define	VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0)		    bVAL16(ctrl0, 32)
+#define	VXGE_HAL_RING_RXD_L3_CKSUM(val)			    vBIT(val, 32, 16)
+
+#define	VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0)		    bVAL16(ctrl0, 48)
+#define	VXGE_HAL_RING_RXD_L4_CKSUM(val)			    vBIT(val, 48, 16)
+
+	u64 control_1;
+#define	VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER			mBIT(0)
+
+#define	VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 2)
+#define	VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(val)		    vBIT(val, 2, 14)
+#define	VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK		    vBIT(0x3FFF, 2, 14)
+
+#define	VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1)	    bVAL32(ctrl1, 16)
+#define	VXGE_HAL_RING_RXD_1_RTH_HASH_VAL(val)		    vBIT(val, 16, 32)
+
+#define	VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1)		    bVAL16(ctrl1, 48)
+#define	VXGE_HAL_RING_RXD_VLAN_TAG(val)			    vBIT(val, 48, 16)
+
+	u64 buffer0_ptr;
+
+} vxge_hal_ring_rxd_1_t;
+
+/*
+ * struct vxge_hal_ring_rxd_3_t - Three buffer mode RxD for ring
+ * @host_control: This field is exclusively for host use and is "readonly"
+ *		from the adapter's perspective.
+ * @control_0:Bits 0 to 6 - RTH_Bucket get
+ *		 Bit 7 - Own Descriptor ownership bit. This bit is set to 1
+ *		 by the host, and is set to 0 by the adapter.
+ *		 0 - Host owns RxD and buffer.
+ *		 1 - The adapter owns RxD and buffer.
+ *		 Bit 8 - Fast_Path_Eligible When set, indicates that the
+ *	    received frame meets all of the criteria for fast path processing.
+ *	   The required criteria are as follows:
+ *	   !SYN &
+ *	   (Transfer_Code == "Transfer OK") &
+ *	   (!Is_IP_Fragment) &
+ *	   ((Is_IPv4 & computed_L3_checksum == 0xFFFF) |
+ *	   (Is_IPv6)) &
+ *	   ((Is_TCP & computed_L4_checksum == 0xFFFF) |
+ *	   (Is_UDP & (computed_L4_checksum == 0xFFFF |
+ *	   computed _L4_checksum == 0x0000)))
+ *	   (same meaning for all RxD buffer modes)
+ *		 Bit 9 - L3 Checksum Correct
+ *		 Bit 10 - L4 Checksum Correct
+ *		 Bit 11 - Reserved
+ *		 Bit 12 to 15 - This field is written by the adapter. It is used
+ *		 to report the status of the frame transfer to the host.
+ *		 0x0 - Transfer OK
+ *		 0x4 - RDA Failure During Transfer
+ *		 0x5 - Unparseable Packet, such as unknown IPv6 header.
+ *		 0x6 - Frame integrity error (FCS or ECC).
+ *		 0x7 - Buffer Size Error. The provided buffer(s) were not
+ *		 appropriately sized and data loss occurred.
+ *		 0x8 - Internal ECC Error. RxD corrupted.
+ *		 0x9 - IPv4 Checksum error
+ *		 0xA - TCP/UDP Checksum error
+ *		 0xF - Unknown Error or Multiple Error. Indicates an unknown
+ *		 problem or that more than one of transfer codes is set.
+ *		 Bit 16 - SYN The adapter sets this field to indicate that the
+ *		 incoming frame contained a TCP segment with its SYN bit set
+ *	   and its ACK bit NOT set. (same meaning for all RxD buffer modes)
+ *		 Bit 17 - Is ICMP
+ *		 Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the
+ *	   Socket
+ *	   Pair Direct Match Table and the frame was steered based on SPDM.
+ *		 Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the
+ *	   Indirection Table and the frame was steered based on hash
+ *	   indirection.
+ *		 Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type)
+ *	   that was used to calculate the hash.
+ *		 Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged.
+ *		 Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation
+ *	   of the received frame.
+ *		 0x0 - Ethernet DIX
+ *		 0x1 - LLC
+ *		 0x2 - SNAP (includes Jumbo-SNAP)
+ *		 0x3 - IPX
+ *		 Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet.
+ *		 Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet.
+ *		 Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a
+ *	   fragmented IP packet.
+ *		 Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment.
+ *		 Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message.
+ *		 Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that
+ *	   arrived with the frame. If the resulting computed IPv4 header
+ *	   checksum for the frame did not produce the expected 0xFFFF value,
+ *	   then the transfer code would be set to 0x9.
+ *		 Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that
+ *	   arrived with the frame. If the resulting computed TCP/UDP checksum
+ *	   for the frame did not produce the expected 0xFFFF value, then the
+ *	   transfer code would be set to 0xA.
+ * @control_1:Bit 0 - This field must be used in conjunction with the Ownership
+ *	   field (above).
+ *	   1 - Set by the host to indicate that the RxD points to fresh
+ *	   buffers.
+ *	   0 - Cleared by the adapter to indicate that frame data has been
+ *	   placed into the assigned buffers, and that the host once again
+ *	   owns the descriptor.
+ *	   (Note: Please observe the usage guidelines outlined in the
+ *	   Ownership field (above)).
+ *		 Bit 1  - Unused. Ignored by Adapter on RxD read. Set to 0
+ *		 by Adapter on RxD write.
+ *	   Bits 2 to 15 - This field is written by the host and by X3100.
+ *	   The host writes the available buffer 0 size in bytes when it
+ *	   passes the descriptor to the X3100. The X3100 writes the number
+ *	   of bytes written to the buffer when it passes the descriptor back
+ *	   to the host.
+ *		 Bits 16 to 17 - Reserved
+ *		 Bits 18 to 31 - This field is set by the host and eventually
+ *		 overwritten by the adapter. The host writes the available
+ *	   buffer 1size in bytes when it passes the descriptor to the adapter.
+ *	   When a frame is delivered the host, the adapter populates this field
+ *	   with the number of bytes written into the buffer 1. The largest
+ *	   supported buffer is 16, 383 bytes.
+ *		 Bits 32 to 33 - Reserved
+ *		 Bits 34 to 47 - This field is set by the host and eventually
+ *		 overwritten by the adapter. The host writes the available
+ *	   buffer 2 size in bytes when it passes the descriptor to the adapter.
+ *	   When a frame is delivered the host, the adapter populates this field
+ *	   with the number of bytes written into the buffer 2. The largest
+ *	   supported buffer is 16, 383 bytes.
+ *		 Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable
+ *	   portion of the VLAN tag, if one was detected by the adapter. This
+ *	   field is populated even if VLAN-tag stripping is enabled.
+ * @buffer0_ptr: Pointer to buffer 0. This field is populated by the driver.
+ *	   In 3-buffer mode, when the RxD is returned to the host,
+ *	   buffer0_ptr field will be overwritten if the following conditions
+ *	   are met:
+ *	   1 - RTH_Disable in the PRC_CTRL register is not set.
+ *	   2 - RTH is enabled and a valid hash value was calculated for the
+ *	   frame. This will be indicated by a non-zero value in the
+ *	   RTH_HASH_TYPE field (Control_0, bits 20:23). In the event that the
+ *	   pointer is overwritten on return to the host, bits 0:31 will be
+ *	   all zeroes while bits 32:63 will contain the calculated hash value.
+ * @buffer1_ptr: Pointer to buffer 1. This field is populated by the driver.
+ * @buffer2_ptr: Pointer to buffer 2. This field is populated by the driver.
+ *
+ * Three buffer mode RxD for ring structure
+ */
+typedef struct vxge_hal_ring_rxd_3_t {
+	u64 host_control;
+	u64 control_0;
+/*
+ * The following bit fields are common in all the three buffer modes and are
+ * defined in vxge_hal_ring_rxd_1_t
+ * #define	VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0)	    bVAL7(ctrl0, 0)
+ * #define	VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER	    vBIT(val, 0, 7)
+ *
+ * #define	VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0)	    bVAL1(ctrl0, 7)
+ * #define	VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER	    mBIT(7)
+ *
+ * #define	VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0)		\
+ *							    bVAL1(ctrl0, 8)
+ * #define	VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE	    mBIT(8)
+ *
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0)		\
+ *							    bVAL1(ctrl0, 9)
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT	    mBIT(9)
+ *
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0)		\
+ *							    bVAL1(ctrl0, 10)
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT	    mBIT(10)
+ *
+ * #define	VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0)	    bVAL4(ctrl0, 12)
+ * #define	VXGE_HAL_RING_RXD_T_CODE(val)		    vBIT(val, 12, 4)
+ * #define	VXGE_HAL_RING_RXD_T_CODE_OK	    VXGE_HAL_RING_T_CODE_OK
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH		\
+ *				VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH		\
+ *				VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH		\
+ *				VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR			\
+ *				VXGE_HAL_RING_T_CODE_L3_PKT_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR			\
+ *				VXGE_HAL_RING_T_CODE_L2_FRM_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR			\
+ *				VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR			\
+ *				VXGE_HAL_RING_T_CODE_INT_ECC_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW			\
+ *				VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW
+ * #define	VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF			\
+ *				VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF
+ * #define	VXGE_HAL_RING_RXD_T_CODE_FRM_DROP VXGE_HAL_RING_T_CODE_FRM_DROP
+ * #define	VXGE_HAL_RING_RXD_T_CODE_UNUSED	  VXGE_HAL_RING_T_CODE_UNUSED
+ * #define	VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR			\
+ *				VXGE_HAL_RING_T_CODE_MULTI_ERR
+ *
+ * #define	VXGE_HAL_RING_RXD_SYN_GET(ctrl0)	    bVAL1(ctrl0, 16)
+ * #define	VXGE_HAL_RING_RXD_SYN			    mBIT(16)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0)	    bVAL1(ctrl0, 17)
+ * #define	VXGE_HAL_RING_RXD_IS_ICMP		    mBIT(17)
+ *
+ * #define	VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0)   bVAL1(ctrl0, 18)
+ * #define	VXGE_HAL_RING_RXD_RTH_SPDM_HIT		    mBIT(18)
+ *
+ * #define	VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0)	    bVAL1(ctrl0, 19)
+ * #define	VXGE_HAL_RING_RXD_RTH_IT_HIT		    mBIT(19)
+ *
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0)  bVAL4(ctrl0, 20)
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val)	    vBIT(val, 20, 4)
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE			\
+ *				VXGE_HAL_RING_HASH_TYPE_NONE
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4		\
+ *				VXGE_HAL_RING_HASH_TYPE_TCP_IPV4
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4		\
+ *				VXGE_HAL_RING_HASH_TYPE_UDP_IPV4
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4			\
+ *				VXGE_HAL_RING_HASH_TYPE_IPV4
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6		\
+ *				VXGE_HAL_RING_HASH_TYPE_TCP_IPV6
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6		\
+ *				VXGE_HAL_RING_HASH_TYPE_UDP_IPV6
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6			\
+ *				VXGE_HAL_RING_HASH_TYPE_IPV6
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX		\
+ *				VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX		\
+ *				VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX			\
+ *				VXGE_HAL_RING_HASH_TYPE_IPV6_EX
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0)	    bVAL1(ctrl0, 24)
+ * #define	VXGE_HAL_RING_RXD_IS_VLAN		    mBIT(24)
+ *
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0)    bVAL2(ctrl0, 25)
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP(val)	    vBIT(val, 25, 2)
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX	VXGE_HAL_FRAME_TYPE_DIX
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC	VXGE_HAL_FRAME_TYPE_LLC
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP	VXGE_HAL_FRAME_TYPE_SNAP
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX	VXGE_HAL_FRAME_TYPE_IPX
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0)	    bVAL1(ctrl0, 27)
+ * #define	VXGE_HAL_RING_RXD_IS_IPV4		    mBIT(27)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0)	    bVAL1(ctrl0, 28)
+ * #define	VXGE_HAL_RING_RXD_IS_IPV6		    mBIT(28)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0)    bVAL1(ctrl0, 29)
+ * #define	VXGE_HAL_RING_RXD_IS_IPV_FRAG		    mBIT(29)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0)	    bVAL1(ctrl0, 30)
+ * #define	VXGE_HAL_RING_RXD_IS_TCP		    mBIT(30)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0)	    bVAL1(ctrl0, 31)
+ * #define	VXGE_HAL_RING_RXD_IS_UDP		    mBIT(31)
+ *
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0)    bVAL5(ctrl0, 27)
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO(val)	    vBIT(val, 27, 5)
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4		    \
+ *				VXGE_HAL_FRAME_PROTO_IPV4
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6		    \
+ *				VXGE_HAL_FRAME_PROTO_IPV6
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG		    \
+ *				VXGE_HAL_FRAME_PROTO_IP_FRAG
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_TCP		    \
+ *				VXGE_HAL_FRAME_PROTO_TCP
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_UDP		    \
+ *				VXGE_HAL_FRAME_PROTO_UDP
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP	    \
+ *			(VXGE_HAL_FRAME_PROTO_TCP | VXGE_HAL_FRAME_PROTO_UDP)
+ *
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0)	    bVAL16(ctrl0, 32)
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM(val)		    vBIT(val, 32, 16)
+ *
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0)	    bVAL16(ctrl0, 48)
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM(val)		    vBIT(val, 48, 16)
+ */
+
+	u64 control_1;
+#define	VXGE_HAL_RING_RXD_3_BUFFER_EMPTY_GET(ctrl1)	    bVAL1(ctrl1, 0)
+#define	VXGE_HAL_RING_RXD_3_BUFFER_EMPTY		    mBIT(0)
+
+#define	VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 2)
+#define	VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(val)		    vBIT(val, 2, 14)
+#define	VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK		    vBIT(0x3FFc, 2, 14)
+
+#define	VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 18)
+#define	VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK		    vBIT(0x3FFc, 18, 14)
+
+#define	VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 34)
+#define	VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(val)		    vBIT(val, 34, 14)
+#define	VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK		    vBIT(0x3FFc, 34, 14)
+
+/*
+ * The following bit fields are common in all the three buffer modes and are
+ * defined in vxge_hal_ring_rxd_1_t
+ * #define	VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1)	    bVAL16(ctrl1, 48)
+ * #define	VXGE_HAL_RING_RXD_VLAN_TAG(val)		    vBIT(val, 48, 16)
+ */
+	u64 buffer0_ptr;
+#define	VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE_GET(b0_ptr)	    bVAL32(b0_ptr, 32)
+#define	VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE(val)		    vBIT(val, 32, 32)
+
+	u64 buffer1_ptr;
+
+	u64 buffer2_ptr;
+
+} vxge_hal_ring_rxd_3_t;
+
+/*
+ * struct vxge_hal_ring_rxd_5_t - Five buffer mode RxD for ring
+ * @host_control: This 32 bitfield is exclusively for host use and is "readonly"
+ *		from the adapter's perspective.
+ * @control_2: Bits 0 to 1 - Reserved
+ *	       Bits 2 to 15 - This field is set by the host and eventually
+ *		overwritten by the adapter. The host writes the available buffer
+ *		3 size in bytes when it pas ses the descriptor to the adapter.
+ *		When a frame is delivered the host, the adapter populates this
+ *		field with the number of bytes written into the buffer. The
+ *		largest supported buffer is 16, 383 bytes.
+ *	       Bits 16 to 17 - Reserved
+ *	       Bits 18 to 31 - This field is set by the host and eventually
+ *		overwritten by the adapter. The host writes the available buffer
+ *		4 size in bytes when it passes the descriptor to the adapter.
+ *		When a frame is delivered the host, the adapter populates this
+ *		field with the number of bytes written into the buffer.
+ *		The largest supported buffer is 16, 383 bytes.
+ * @control_0: Bits 0 to 6 - RTH_Bucket get
+ *		 Bit 7 - Own Descriptor ownership bit. This bit is set to 1 by
+ *		 the host, and is set to 0 by the adapter.
+ *		 0 - Host owns RxD and buffer.
+ *		 1 - The adapter owns RxD and buffer.
+ *		 Bit 8 - Fast_Path_Eligible When set,indicates that the received
+ *	   frame meets all of the criteria for fast path processing.
+ *	   The required criteria are as follows:
+ *	   !SYN &
+ *	   (Transfer_Code == "Transfer OK") &
+ *	   (!Is_IP_Fragment) &
+ *	   ((Is_IPv4 & computed_L3_checksum == 0xFFFF) |
+ *	   (Is_IPv6)) &
+ *	   ((Is_TCP & computed_L4_checksum == 0xFFFF) |
+ *	   (Is_UDP & (computed_L4_checksum == 0xFFFF |
+ *	   computed _L4_checksum == 0x0000)))
+ *	   (same meaning for all RxD buffer modes)
+ *		 Bit 9 - L3 Checksum Correct
+ *		 Bit 10 - L4 Checksum Correct
+ *		 Bit 11 - Reserved
+ *		 Bit 12 to 15 - This field is written by the adapter. It is used
+ *		 to report the status of the frame transfer to the host.
+ *		 0x0 - Transfer OK
+ *		 0x4 - RDA Failure During Transfer
+ *		 0x5 - Unparseable Packet, such as unknown IPv6 header.
+ *		 0x6 - Frame integrity error (FCS or ECC).
+ *		 0x7 - Buffer Size Error. The provided buffer(s) were not
+ *		 appropriately sized and data loss occurred.
+ *		 0x8 - Internal ECC Error. RxD corrupted.
+ *		 0x9 - IPv4 Checksum error
+ *		 0xA - TCP/UDP Checksum error
+ *		 0xF - Unknown Error or Multiple Error. Indicates an unknown
+ *		 problem or that more than one of transfer codes is set.
+ *		 Bit 16 - SYN The adapter sets this field to indicate that the
+ *		 incoming frame contained a TCP segment with its SYN bit set
+ *	   and its ACK bit NOT set. (same meaning for all RxD buffer modes)
+ *		 Bit 17 - Is ICMP
+ *		 Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the
+ *	   Socket Pair Direct Match Table and the frame was steered based on
+ *	   SPDM.
+ *		 Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the
+ *	   Indirection Table and the frame was steered based on hash
+ *	   indirection.
+ *		 Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type)
+ *	   that was used to calculate the hash.
+ *		 Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged.
+ *		 Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation
+ *	   of the received frame.
+ *		 0x0 - Ethernet DIX
+ *		 0x1 - LLC
+ *		 0x2 - SNAP (includes Jumbo-SNAP)
+ *		 0x3 - IPX
+ *		 Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet.
+ *		 Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet.
+ *		 Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a
+ *	   fragmented IP packet.
+ *		 Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment.
+ *		 Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message.
+ *		 Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that
+ *	   arrived with the frame. If the resulting computed IPv4 header
+ *	   checksum for the frame did not produce the expected 0xFFFF value,
+ *	   then the transfer code would be set to 0x9.
+ *		 Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that
+ *	   arrived with the frame. If the resulting computed TCP/UDP checksum
+ *	   for the frame did not produce the expected 0xFFFF value, then the
+ *	   transfer code would be set to 0xA.
+ * @control_1: Bits 0 to 1 - Reserved.
+ *	   Bits 2 to 15 - This field is written by the host and by X3100.
+ *	   The host writes the available buffer 0 size in bytes when it
+ *	   passes the descriptor to the X3100. The X3100 writes the number
+ *	   of bytes written to the buffer when it passes the descriptor back
+ *	   to the host.
+ *		 Bits 16 to 17 - Reserved
+ *		 Bits 18 to 31 - This field is set by the host and eventually
+ *		 overwritten by the adapter. The host writes the available
+ *	   buffer 1 size in bytes when it passes the descriptor to the adapter.
+ *	   When a frame is delivered the host, the adapter populates this field
+ *	   with the number of bytes written into the buffer 1. The largest
+ *	   supported buffer is 16, 383 bytes.
+ *		 Bits 32 to 33 - Reserved
+ *		 Bits 34 to 47 - This field is set by the host and eventually
+ *		 overwritten by the adapter. The host writes the available
+ *	   buffer 2 size in bytes when it passes the descriptor to the adapter.
+ *	   When a frame is delivered the host, the adapter populates this field
+ *	   with the number of bytes written into the buffer 2. The largest
+ *	   supported buffer is 16, 383 bytes.
+ *		 Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable
+ *	   portion of the VLAN tag, if one was detected by the adapter. This
+ *	   field is populated even if VLAN-tag stripping is enabled.
+ * @buffer0_ptr: Pointer to buffer 0. This field is populated by the driver.
+ *	   In 5-buffer mode, when the RxD is returned to the host,
+ *	   buffer0_ptr field will be overwritten if the following conditions
+ *	   are met:
+ *	   1 - RTH_Disable in the PRC_CTRL register is not set.
+ *	   2 - RTH is enabled and a valid hash value was calculated for the
+ *	   frame. This will be indicated by a non-zero value in the
+ *	   RTH_HASH_TYPE field (Control_0, bits 20:23). In the event that the
+ *	   pointer is overwritten on return to the host, bits 0:31 will be
+ *	   all zeroes while bits 32:63 will contain the calculated hash value.
+ * @buffer1_ptr: Pointer to buffer 1. This field is populated by the driver.
+ * @buffer2_ptr: Pointer to buffer 2. This field is populated by the driver.
+ * @buffer3_ptr: Pointer to buffer 3. This field is populated by the driver.
+ * @buffer4_ptr: Pointer to buffer 4. This field is populated by the driver.
+ * @pad: Pad to align at cache line boundary
+ *
+ * Three buffer mode RxD for ring structure
+ */
+typedef struct vxge_hal_ring_rxd_5_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u32 host_control;
+	u32 control_2;
+#else
+	u32 control_2;
+	u32 host_control;
+#endif
+
+#define	VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(ctrl2)	    bVAL14(ctrl2, 34)
+#define	VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(val)		    vBIT(val, 34, 14)
+#define	VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK		    vBIT(0x3FFF, 34, 14)
+
+#define	VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_GET(ctrl2)	    bVAL14(ctrl2, 50)
+#define	VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(val)		    vBIT(val, 50, 14)
+#define	VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK		    vBIT(0x3FFF, 50, 14)
+
+
+	u64 control_0;
+/*
+ * The following bit fields are common in all the three buffer modes and are
+ * defined in vxge_hal_ring_rxd_1_t
+ * #define	VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0)	    bVAL7(ctrl0, 0)
+ * #define	VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER	    vBIT(val, 0, 7)
+ *
+ * #define	VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0)	    bVAL1(ctrl0, 7)
+ * #define	VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER	    mBIT(7)
+ *
+ * #define	VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0		\
+ *				bVAL1(ctrl0, 8)
+ * #define	VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE	    mBIT(8)
+ *
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0)		\
+ *				bVAL1(ctrl0, 9)
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT	    mBIT(9)
+ *
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0)		\
+ *				bVAL1(ctrl0, 10)
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT	    mBIT(10)
+ *
+ * #define	VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0)	    bVAL4(ctrl0, 12)
+ * #define	VXGE_HAL_RING_RXD_T_CODE(val)		    vBIT(val, 12, 4)
+ * #define	VXGE_HAL_RING_RXD_T_CODE_OK				\
+ *				VXGE_HAL_RING_T_CODE_OK
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH		\
+ *				VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH		\
+ *				VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH		\
+ *				VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR			\
+ *				VXGE_HAL_RING_T_CODE_L3_PKT_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR			\
+ *				VXGE_HAL_RING_T_CODE_L2_FRM_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR			\
+ *				VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR			\
+ *				VXGE_HAL_RING_T_CODE_INT_ECC_ERR
+ * #define	VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW			\
+ *				VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW
+ * #define	VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF			\
+ *				VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF
+ * #define	VXGE_HAL_RING_RXD_T_CODE_FRM_DROP			\
+ *				VXGE_HAL_RING_T_CODE_FRM_DROP
+ * #define	VXGE_HAL_RING_RXD_T_CODE_UNUSED				\
+ *				VXGE_HAL_RING_T_CODE_UNUSED
+ * #define	VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR			\
+ *				VXGE_HAL_RING_T_CODE_MULTI_ERR
+ *
+ * #define	VXGE_HAL_RING_RXD_SYN_GET(ctrl0)	    bVAL1(ctrl0, 16)
+ * #define	VXGE_HAL_RING_RXD_SYN			    mBIT(16)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0)	    bVAL1(ctrl0, 17)
+ * #define	VXGE_HAL_RING_RXD_IS_ICMP		    mBIT(17)
+ *
+ * #define	VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0)   bVAL1(ctrl0, 18)
+ * #define	VXGE_HAL_RING_RXD_RTH_SPDM_HIT		    mBIT(18)
+ *
+ * #define	VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0)	    bVAL1(ctrl0, 19)
+ * #define	VXGE_HAL_RING_RXD_RTH_IT_HIT		    mBIT(19)
+ *
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0)  bVAL4(ctrl0, 20)
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val)	    vBIT(val, 20, 4)
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE		    \
+ *				VXGE_HAL_RING_HASH_TYPE_NONE
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4	    \
+ *				VXGE_HAL_RING_HASH_TYPE_TCP_IPV4
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4	    \
+ *				VXGE_HAL_RING_HASH_TYPE_UDP_IPV4
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4		    \
+ *				VXGE_HAL_RING_HASH_TYPE_IPV4
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6	    \
+ *				VXGE_HAL_RING_HASH_TYPE_TCP_IPV6
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6	    \
+ *				VXGE_HAL_RING_HASH_TYPE_UDP_IPV6
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6		    \
+ *				VXGE_HAL_RING_HASH_TYPE_IPV6
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX	    \
+ *				VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX	    \
+ *				VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX
+ * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX		    \
+ *				VXGE_HAL_RING_HASH_TYPE_IPV6_EX
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0)	    bVAL1(ctrl0, 24)
+ * #define	VXGE_HAL_RING_RXD_IS_VLAN		    mBIT(24)
+ *
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0)    bVAL2(ctrl0, 25)
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP(val)	    vBIT(val, 25, 2)
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX   VXGE_HAL_FRAME_TYPE_DIX
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC   VXGE_HAL_FRAME_TYPE_LLC
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP  VXGE_HAL_FRAME_TYPE_SNAP
+ * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX   VXGE_HAL_FRAME_TYPE_IPX
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0)	    bVAL1(ctrl0, 27)
+ * #define	VXGE_HAL_RING_RXD_IS_IPV4		    mBIT(27)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0)	    bVAL1(ctrl0, 28)
+ * #define	VXGE_HAL_RING_RXD_IS_IPV6		    mBIT(28)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0)    bVAL1(ctrl0, 29)
+ * #define	VXGE_HAL_RING_RXD_IS_IPV_FRAG		    mBIT(29)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0)	    bVAL1(ctrl0, 30)
+ * #define	VXGE_HAL_RING_RXD_IS_TCP		    mBIT(30)
+ *
+ * #define	VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0)	    bVAL1(ctrl0, 31)
+ * #define	VXGE_HAL_RING_RXD_IS_UDP		    mBIT(31)
+ *
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0)    bVAL5(ctrl0, 27)
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO(val)	    vBIT(val, 27, 5)
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4  VXGE_HAL_FRAME_PROTO_IPV4
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6  VXGE_HAL_FRAME_PROTO_IPV6
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG		\
+ *				VXGE_HAL_FRAME_PROTO_IP_FRAG
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_TCP   VXGE_HAL_FRAME_PROTO_TCP
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_UDP   VXGE_HAL_FRAME_PROTO_UDP
+ * #define	VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP	\
+ *			(VXGE_HAL_FRAME_PROTO_TCP | VXGE_HAL_FRAME_PROTO_UDP)
+ *
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0)	    bVAL16(ctrl0, 32)
+ * #define	VXGE_HAL_RING_RXD_L3_CKSUM(val)		    vBIT(val, 32, 16)
+ *
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0)	    bVAL16(ctrl0, 48)
+ * #define	VXGE_HAL_RING_RXD_L4_CKSUM(val)		    vBIT(val, 48, 16)
+ */
+
+	u64 control_1;
+
+#define	VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 2)
+#define	VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(val)		    vBIT(val, 2, 14)
+#define	VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK		    vBIT(0x3FFF, 2, 14)
+
+#define	VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 18)
+#define	VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK		    vBIT(0x3FFF, 18, 14)
+
+#define	VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(ctrl1)	    bVAL14(ctrl1, 34)
+#define	VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(val)		    vBIT(val, 34, 14)
+#define	VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK		    vBIT(0xFFFF, 34, 14)
+
+/*
+ * The following bit fields are common in all the three buffer modes and are
+ * defined in vxge_hal_ring_rxd_1_t
+ * #define	VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1)	    bVAL16(ctrl1, 48)
+ * #define	VXGE_HAL_RING_RXD_VLAN_TAG(val)		    vBIT(val, 48, 16)
+ */
+
+	u64 buffer0_ptr;
+#define	VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE_GET(b0_ptr)	    bVAL32(b0_ptr, 32)
+#define	VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE(val)		    vBIT(val, 32, 32)
+
+	u64 buffer1_ptr;
+	u64 buffer2_ptr;
+	u64 buffer3_ptr;
+	u64 buffer4_ptr;
+} vxge_hal_ring_rxd_5_t;
+
+/*
+ * function vxge_hal_ring_callback_f - Ring callback.
+ * @vpath_handle: Virtual Path whose Ring "containing" 1 or more completed
+ *		descriptors.
+ * @rxdh: First completed descriptor.
+ * @rxd_priv: Pointer to per rxd space allocated
+ * @t_code: Transfer code, as per X3100 User Guide.
+ *	 Returned by HAL.
+ * @userdata: Opaque per-ring data specified at ring open
+ *	   time, via vxge_hal_vpath_open().
+ *
+ * ring completion callback (type declaration). A single per-ring
+ * callback is specified at virtual path open time, via
+ * vxge_hal_vpath_open().
+ * Typically gets called as part of the processing of the Interrupt
+ * Service Routine.
+ *
+ * ring callback gets called by HAL if, and only if, there is at least
+ * one new completion on a given ring . Upon processing the first @rxdh
+ * ULD is _supposed_ to continue consuming completions
+ * using - vxge_hal_ring_rxd_next_completed().
+ *
+ * Note that failure to process new completions in a timely fashion
+ * leads to VXGE_HAL_INF_OUT_OF_DESCRIPTORS condition.
+ *
+ * Non-zero @t_code means failure to process receive descriptor.
+ *
+ * In the "transmit" case the failure could happen, for instance, when the
+ * link is down, in which case X3100 completes the descriptor because it
+ * is not able to send the data out.
+ *
+ * For details please refer to X3100 User Guide.
+ *
+ * See also: vxge_hal_ring_rxd_next_completed(), vxge_hal_ring_rxd_term_f {}.
+ */
+typedef vxge_hal_status_e(*vxge_hal_ring_callback_f) (
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    void *rxd_priv,
+    u8 t_code,
+    void *userdata);
+
+/*
+ * function vxge_hal_ring_rxd_init_f - Initialize descriptor callback.
+ * @vpath_handle: Virtual path whose ring "containing" the @rxdh descriptor.
+ * @rxdh: Descriptor.
+ * @rxd_priv: Pointer to per rxd space allocated
+ * @index: Index of the descriptor in the ring's set of descriptors.
+ * @userdata: Per-ring user data (a.k.a. context) specified at
+ * ring open time, via vxge_hal_vpath_open().
+ * @reopen: See  vxge_hal_reopen_e {}.
+ *
+ * Initialize descriptor callback. Unless NULL is specified in the
+ * vxge_hal_ring_attr_t {} structure passed to vxge_hal_vpath_open()),
+ * HAL invokes the callback as part of the ring create in vxge_hal_vpath_open()
+ * implementation.
+ * The ULD is expected to fill in this descriptor with buffer(s)
+ * and control information.
+ *
+ * See also: vxge_hal_ring_attr_t {}, vxge_hal_ring_rxd_term_f {}.
+ */
+typedef vxge_hal_status_e(*vxge_hal_ring_rxd_init_f) (
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    void *rxd_priv,
+    u32 index,
+    void *userdata,
+    vxge_hal_reopen_e reopen);
+
+/*
+ * function vxge_hal_ring_rxd_term_f - Terminate descriptor callback.
+ * @vpath_handle: Virtual path whose ring "containing" the @rxdh descriptor.
+ * @rxdh: First completed descriptor.
+ * @rxd_priv: Pointer to per rxd space allocated
+ * @state: One of the vxge_hal_rxd_state_e {} enumerated states.
+ * @userdata: Per-ring user data (a.k.a. context) specified at
+ * ring open time, via vxge_hal_vpath_open().
+ * @reopen: See  vxge_hal_reopen_e {}.
+ *
+ * Terminate descriptor callback. Unless NULL is specified in the
+ * vxge_hal_ring_attr_t {} structure passed to vxge_hal_vpath_open()),
+ * HAL invokes the callback as part of closing the corresponding
+ * ring, prior to de-allocating the ring and associated data
+ * structures (including descriptors).
+ * ULD should utilize the callback to (for instance) unmap
+ * and free DMA data buffers associated with the posted (state =
+ * VXGE_HAL_RXD_STATE_POSTED) descriptors,
+ * as well as other relevant cleanup functions.
+ *
+ * See also: vxge_hal_ring_attr_t {}, vxge_hal_ring_rxd_init_f {}.
+ */
+typedef void (*vxge_hal_ring_rxd_term_f) (
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    void *rxd_priv,
+    vxge_hal_rxd_state_e state,
+    void *userdata,
+    vxge_hal_reopen_e reopen);
+
+/*
+ * struct vxge_hal_ring_attr_t - Ring open "template".
+ * @callback: Ring completion callback. HAL invokes the callback when there
+ *	   are new completions on that ring. In many implementations
+ *	   the @callback executes in the hw interrupt context.
+ * @rxd_init: Ring's descriptor-initialize callback.
+ *	   See vxge_hal_ring_rxd_init_f {}.
+ *	   If not NULL, HAL invokes the callback when opening
+ *	   the ring.
+ * @rxd_term: Ring's descriptor-terminate callback. If not NULL,
+ *	   HAL invokes the callback when closing the corresponding ring.
+ *	   See also vxge_hal_ring_rxd_term_f {}.
+ * @userdata: User-defined "context" of _that_ ring. Passed back to the
+ *	   user as one of the @callback, @rxd_init, and @rxd_term arguments.
+ * @per_rxd_space: If specified (i.e., greater than zero): extra space
+ *	    reserved by HAL per each receive descriptor. Can be used to store,
+ *	    and retrieve on completion, information specific
+ *	    to the upper-layer.
+ *
+ * Ring open "template". User fills the structure with ring
+ * attributes and passes it to vxge_hal_vpath_open().
+ */
+typedef struct vxge_hal_ring_attr_t {
+	vxge_hal_ring_callback_f		callback;
+	vxge_hal_ring_rxd_init_f		rxd_init;
+	vxge_hal_ring_rxd_term_f		rxd_term;
+	void					*userdata;
+	u32					per_rxd_space;
+} vxge_hal_ring_attr_t;
+
+
+/*
+ * vxge_hal_ring_rxd_size_get	- Get the size of ring descriptor.
+ * @buf_mode: Buffer mode (1, 3 or 5)
+ *
+ * This function returns the size of RxD for given buffer mode
+ */
+static inline u32
+/* LINTED */
+vxge_hal_ring_rxd_size_get(
+    u32 buf_mode)
+{
+	return ((u32) (buf_mode == 1 ? sizeof(vxge_hal_ring_rxd_1_t) : \
+	    (buf_mode == 3 ? sizeof(vxge_hal_ring_rxd_3_t) : \
+	    sizeof(vxge_hal_ring_rxd_5_t))));
+
+}
+
+/*
+ * vxge_hal_ring_rxds_per_block_get - Get the number of rxds per block.
+ * @buf_mode: Buffer mode (1, 3 or 5)
+ *
+ * This function returns the number of RxD for RxD block for given buffer mode
+ */
+static inline u32
+/* LINTED */
+vxge_hal_ring_rxds_per_block_get(
+    u32 buf_mode)
+{
+	return ((u32) ((VXGE_OS_HOST_PAGE_SIZE - 16) /
+	    ((buf_mode == 1) ? sizeof(vxge_hal_ring_rxd_1_t) :
+	    ((buf_mode == 3) ? sizeof(vxge_hal_ring_rxd_3_t) :
+	    sizeof(vxge_hal_ring_rxd_5_t)))));
+}
+
+/*
+ * vxge_hal_ring_rxd_reserve	- Reserve ring descriptor.
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Reserved descriptor. On success HAL fills this "out" parameter
+ *		 with a valid handle.
+ * @rxd_priv: Buffer to return the pointer to per rxd space allocated
+ *
+ * Reserve Rx descriptor for the subsequent filling-in (by upper layer
+ * driver (ULD)) and posting on	the corresponding ring
+ * via vxge_hal_ring_rxd_post().
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_ring_rxd_reserve(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h *rxdh,
+    void **rxd_priv);
+
+/*
+ * vxge_hal_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
+ * @rxdh: Descriptor handle.
+ * @dma_pointer: DMA address of	a single receive buffer	this descriptor
+ *		should	carry. Note that by the	time
+ *		vxge_hal_ring_rxd_1b_set is called, the
+ *		receive buffer should be already mapped
+ *		to the	corresponding X3100 device.
+ * @size: Size of the receive @dma_pointer buffer.
+ *
+ * Prepare 1-buffer-mode Rx	descriptor for posting
+ * (via	vxge_hal_ring_rxd_post()).
+ *
+ * This	inline helper-function does not	return any parameters and always
+ * succeeds.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_1b_set(
+    vxge_hal_rxd_h rxdh,
+    dma_addr_t dma_pointer,
+    int size)
+{
+	vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+	rxdp->buffer0_ptr = dma_pointer;
+	rxdp->control_1 &= ~VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK;
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(size);
+}
+
+/*
+ * vxge_hal_ring_rxd_3b_set - Prepare 3-buffer-mode descriptor.
+ * @rxdh: Descriptor handle.
+ * @dma_pointers: Array	of DMA addresses. Contains exactly 3 receive buffers
+ *		_this_ descriptor should carry. Note that by the time
+ *		vxge_hal_ring_rxd_3b_set is called, the receive	buffers	should
+ *		be mapped to the corresponding X3100 device.
+ * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per
+ *		buffer from @dma_pointers.
+ *
+ * Prepare 3-buffer-mode Rx descriptor for posting (via
+ * vxge_hal_ring_rxd_post()).
+ * This	inline helper-function does not	return any parameters and always
+ * succeeds.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_3b_set(
+    vxge_hal_rxd_h rxdh,
+    dma_addr_t dma_pointers[],
+    u32 sizes[])
+{
+	vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh;
+	rxdp->buffer0_ptr = dma_pointers[0];
+	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK);
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(sizes[0]);
+	rxdp->buffer1_ptr = dma_pointers[1];
+	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK);
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(sizes[1]);
+	rxdp->buffer2_ptr = dma_pointers[2];
+	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK);
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(sizes[2]);
+}
+
+/*
+ * vxge_hal_ring_rxd_5b_set - Prepare 5-buffer-mode descriptor.
+ * @rxdh: Descriptor handle.
+ * @dma_pointers: Array	of DMA addresses. Contains exactly 5 receive buffers
+ *		_this_ descriptor should carry. Note that by the time
+ *		vxge_hal_ring_rxd_5b_set is called, the receive buffers should
+ *		be mapped to the corresponding X3100 device.
+ * @sizes: Array of receive buffer sizes. Contains 5 sizes: one	size per buffer
+ *		from @dma_pointers.
+ *
+ * Prepare 5-buffer-mode Rx descriptor for posting
+ * (via vxge_hal_ring_rxd_post()).
+ * This	inline helper-function does not	return any
+ * values and always succeeds.
+ *
+ * See also: vxge_hal_ring_rxd_1b_set(), vxge_hal_ring_rxd_3b_set().
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_5b_set(
+    vxge_hal_rxd_h rxdh,
+    dma_addr_t dma_pointers[],
+    u32 sizes[])
+{
+	vxge_hal_ring_rxd_5_t *rxdp = (vxge_hal_ring_rxd_5_t *) rxdh;
+
+	rxdp->buffer0_ptr = dma_pointers[0];
+	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK);
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(sizes[0]);
+	rxdp->buffer1_ptr = dma_pointers[1];
+	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK);
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(sizes[1]);
+	rxdp->buffer2_ptr = dma_pointers[2];
+	rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK);
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(sizes[2]);
+	rxdp->buffer3_ptr = dma_pointers[3];
+	rxdp->control_2 &= (~VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK);
+	rxdp->control_2 |= VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(sizes[3]);
+	rxdp->buffer4_ptr = dma_pointers[4];
+	rxdp->control_2 &= (~VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK);
+	rxdp->control_2 |= VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(sizes[4]);
+}
+
+/*
+ * vxge_hal_ring_rxd_pre_post - Prepare rxd and post
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * This routine prepares a rxd and posts
+ */
+void
+vxge_hal_ring_rxd_pre_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh);
+
+/*
+ * vxge_hal_ring_rxd_post_post - Process rxd after post.
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Processes rxd after post
+ */
+void
+vxge_hal_ring_rxd_post_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh);
+
+/*
+ * vxge_hal_ring_rxd_post_post_db - Post Doorbell after posting the rxd(s).
+ * @vpath_handle: virtual Path handle.
+ *
+ * Post Doorbell after posting the rxd(s).
+ */
+void
+vxge_hal_ring_rxd_post_post_db(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_ring_rxd_post_post_wmb - Process rxd after post with memory barrier
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Processes rxd after post with memory barrier.
+ */
+void
+vxge_hal_ring_rxd_post_post_wmb(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh);
+
+/*
+ * vxge_hal_ring_rxd_post - Post descriptor on the ring.
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor obtained via vxge_hal_ring_rxd_reserve().
+ *
+ * Post	descriptor on the ring.
+ * Prior to posting the	descriptor should be filled in accordance with
+ * Host/X3100 interface specification for a given service (LL,	etc.).
+ *
+ */
+void
+vxge_hal_ring_rxd_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh);
+
+/*
+ * vxge_hal_ring_is_next_rxd_completed - Check if the next rxd is completed
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Checks if the the _next_	completed descriptor is	in host	memory
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed	descriptors
+ * are currently available for processing.
+ */
+vxge_hal_status_e
+vxge_hal_ring_is_next_rxd_completed(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_ring_rxd_next_completed - Get the _next_ completed descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @rxdh: Descriptor handle. Returned by HAL.
+ * @rxd_priv: Buffer to return a pointer to the per rxd space allocated
+ * @t_code:	Transfer code, as per X3100 User Guide,
+ *			Receive	Descriptor Format. Returned	by HAL.
+ *
+ * Retrieve the	_next_ completed descriptor.
+ * HAL uses ring callback (*vxge_hal_ring_callback_f) to notifiy
+ * upper-layer driver (ULD) of new completed descriptors. After that
+ * the ULD can use vxge_hal_ring_rxd_next_completed to retrieve the rest
+ * completions (the very first completion is passed by HAL via
+ * vxge_hal_ring_callback_f).
+ *
+ * Implementation-wise,	the upper-layer	driver is free to call
+ * vxge_hal_ring_rxd_next_completed either immediately from inside the
+ * ring callback, or in a deferred fashion and separate (from HAL)
+ * context.
+ *
+ * Non-zero @t_code means failure to fill-in receive buffer(s)
+ * of the descriptor.
+ * For instance, parity error detected during the data transfer.
+ * In this case X3100 will complete the descriptor and indicate
+ * for the host that the received data is not to be used.
+ * For details please refer to X3100 User Guide.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
+ * are currently available for processing.
+ *
+ * See also: vxge_hal_ring_callback_f {},
+ * vxge_hal_fifo_txdl_next_completed(), vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_ring_rxd_next_completed(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h *rxdh,
+    void **rxd_priv,
+    u8 *t_code);
+
+/*
+ * vxge_hal_ring_handle_tcode - Handle transfer code.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @t_code: One of the enumerated (and documented in the X3100 user guide)
+ *	 "transfer codes".
+ *
+ * Handle descriptor's transfer code. The latter comes with each completed
+ * descriptor.
+ *
+ * Returns: one of the vxge_hal_status_e {} enumerated types.
+ * VXGE_HAL_OK			- for success.
+ * VXGE_HAL_ERR_CRITICAL	- when encounters critical error.
+ */
+vxge_hal_status_e
+vxge_hal_ring_handle_tcode(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    u8 t_code);
+
+/*
+ * vxge_hal_ring_rxd_1b_get - Get data from the completed 1-buf
+ * descriptor.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @dma_pointer: DMA address of	a single receive buffer	_this_ descriptor
+ *				carries. Returned by HAL.
+ * @pkt_length:	Length (in bytes) of the data in the buffer pointed	by
+ *				@dma_pointer. Returned by HAL.
+ *
+ * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor.
+ * This	inline helper-function uses completed descriptor to populate receive
+ * buffer pointer and other "out" parameters. The function always succeeds.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_1b_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    dma_addr_t *dma_pointer,
+    u32 *pkt_length)
+{
+	vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+
+	*pkt_length =
+	    (u32) VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1);
+	*dma_pointer = rxdp->buffer0_ptr;
+}
+
+/*
+ * vxge_hal_ring_rxd_3b_get - Get data from the completed 3-buf
+ * descriptor.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @dma_pointers: DMA addresses	of the 3 receive buffers _this_	descriptor
+ *			carries. The first two buffers contain ethernet and
+ *			(IP + transport) headers. The 3rd buffer contains packet
+ *			data.
+ * @sizes: Array of receive buffer sizes. Contains 3 sizes: one	size per
+ * buffer from @dma_pointers. Returned by HAL.
+ *
+ * Retrieve	protocol data from the completed 3-buffer-mode Rx descriptor.
+ * This	inline helper-function uses completed descriptor to populate receive
+ * buffer pointer and other "out" parameters. The function always succeeds.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_3b_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    dma_addr_t dma_pointers[],
+    u32 sizes[])
+{
+	vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh;
+
+	dma_pointers[0] = rxdp->buffer0_ptr;
+	sizes[0] = (u32) VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(rxdp->control_1);
+
+	dma_pointers[1] = rxdp->buffer1_ptr;
+	sizes[1] = (u32) VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(rxdp->control_1);
+
+	dma_pointers[2] = rxdp->buffer2_ptr;
+	sizes[2] = (u32) VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(rxdp->control_1);
+}
+
+/*
+ * vxge_hal_ring_rxd_5b_get - Get data from the completed 5-buf descriptor.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @dma_pointers: DMA addresses	of the 5 receive buffers _this_	descriptor
+ *		carries. The first 4 buffers contains L2 (ethernet) through
+ *		  L5 headers. The 5th buffer contain received (applicaion)
+ *		  data. Returned by HAL.
+ * @sizes: Array of receive buffer sizes. Contains 5 sizes: one	size per
+ * buffer from @dma_pointers. Returned by HAL.
+ *
+ * Retrieve	protocol data from the completed 5-buffer-mode Rx descriptor.
+ * This	inline helper-function uses completed descriptor to populate receive
+ * buffer pointer and other "out" parameters. The function always succeeds.
+ *
+ * See also: vxge_hal_ring_rxd_3b_get(),	vxge_hal_ring_rxd_5b_get().
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_5b_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    dma_addr_t dma_pointers[],
+    int sizes[])
+{
+	vxge_hal_ring_rxd_5_t *rxdp = (vxge_hal_ring_rxd_5_t *) rxdh;
+
+	dma_pointers[0] = rxdp->buffer0_ptr;
+	sizes[0] = (u32) VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(rxdp->control_1);
+
+	dma_pointers[1] = rxdp->buffer1_ptr;
+	sizes[1] = (u32) VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(rxdp->control_1);
+
+	dma_pointers[2] = rxdp->buffer2_ptr;
+	sizes[2] = (u32) VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(rxdp->control_1);
+
+	dma_pointers[3] = rxdp->buffer3_ptr;
+	sizes[3] = (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(rxdp->control_2);
+
+	dma_pointers[4] = rxdp->buffer4_ptr;
+	sizes[4] = (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(rxdp->control_2);
+}
+
+/*
+ * vxge_hal_ring_rxd_1b_info_get - Get extended information associated with
+ *				  a completed receive descriptor for 1b mode.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @rxd_info: Descriptor information
+ *
+ * Retrieve extended information associated with a completed receive descriptor.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_1b_info_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    vxge_hal_ring_rxd_info_t *rxd_info)
+{
+	vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+
+	rxd_info->syn_flag =
+	    (u32) VXGE_HAL_RING_RXD_SYN_GET(rxdp->control_0);
+	rxd_info->is_icmp =
+	    (u32) VXGE_HAL_RING_RXD_IS_ICMP_GET(rxdp->control_0);
+	rxd_info->fast_path_eligible =
+	    (u32) VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0);
+	rxd_info->l3_cksum_valid =
+	    (u32) VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0);
+	rxd_info->l3_cksum =
+	    (u32) VXGE_HAL_RING_RXD_L3_CKSUM_GET(rxdp->control_0);
+	rxd_info->l4_cksum_valid =
+	    (u32) VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0);
+	rxd_info->l4_cksum =
+	    (u32) VXGE_HAL_RING_RXD_L4_CKSUM_GET(rxdp->control_0);
+	rxd_info->frame =
+	    (u32) VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0);
+	rxd_info->proto =
+	    (u32) VXGE_HAL_RING_RXD_FRAME_PROTO_GET(rxdp->control_0);
+	rxd_info->is_vlan =
+	    (u32) VXGE_HAL_RING_RXD_IS_VLAN_GET(rxdp->control_0);
+	rxd_info->vlan =
+	    (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1);
+	rxd_info->rth_bucket =
+	    (u32) VXGE_HAL_RING_RXD_RTH_BUCKET_GET(rxdp->control_0);
+	rxd_info->rth_it_hit =
+	    (u32) VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0);
+	rxd_info->rth_spdm_hit =
+	    (u32) VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0);
+	rxd_info->rth_hash_type =
+	    (u32) VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0);
+	rxd_info->rth_value =
+	    (u32) VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1);
+}
+
+/*
+ * vxge_hal_ring_rxd_3b_5b_info_get - Get extended information associated with
+ *			    a completed receive descriptor for 3b & 5b mode.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @rxd_info: Descriptor information
+ *
+ * Retrieve extended information associated with a completed receive descriptor.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_ring_rxd_3b_5b_info_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    vxge_hal_ring_rxd_info_t *rxd_info)
+{
+	vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh;
+
+	rxd_info->syn_flag =
+	    (u32) VXGE_HAL_RING_RXD_SYN_GET(rxdp->control_0);
+	rxd_info->is_icmp =
+	    (u32) VXGE_HAL_RING_RXD_IS_ICMP_GET(rxdp->control_0);
+	rxd_info->fast_path_eligible =
+	    (u32) VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0);
+	rxd_info->l3_cksum_valid =
+	    (u32) VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0);
+	rxd_info->l3_cksum =
+	    (u32) VXGE_HAL_RING_RXD_L3_CKSUM_GET(rxdp->control_0);
+	rxd_info->l4_cksum_valid =
+	    (u32) VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0);
+	rxd_info->l4_cksum =
+	    (u32) VXGE_HAL_RING_RXD_L4_CKSUM_GET(rxdp->control_0);
+	rxd_info->frame =
+	    (u32) VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0);
+	rxd_info->proto =
+	    (u32) VXGE_HAL_RING_RXD_FRAME_PROTO_GET(rxdp->control_0);
+	rxd_info->is_vlan =
+	    (u32) VXGE_HAL_RING_RXD_IS_VLAN_GET(rxdp->control_0);
+	rxd_info->vlan =
+	    (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1);
+	rxd_info->rth_bucket =
+	    (u32) VXGE_HAL_RING_RXD_RTH_BUCKET_GET(rxdp->control_0);
+	rxd_info->rth_it_hit =
+	    (u32) VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0);
+	rxd_info->rth_spdm_hit =
+	    (u32) VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0);
+	rxd_info->rth_hash_type =
+	    (u32) VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0);
+	rxd_info->rth_value = (u32) VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE_GET(
+	    rxdp->buffer0_ptr);
+}
+
+/*
+ * vxge_hal_device_is_privileged 
+ * @host_type: host type.
+ * @func_id: function id.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_is_privileged(
+    u32 host_type,
+    u32 func_id);
+
+/*
+ * vxge_hal_ring_rxd_private_get - Get ULD private per-descriptor data
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Returns: private ULD	info associated	with the descriptor.
+ * ULD requests	per-descriptor space via vxge_hal_ring_attr.
+ *
+ */
+void *
+vxge_hal_ring_rxd_private_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh);
+
+/*
+ * vxge_hal_ring_rxd_free - Free descriptor.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Free	the reserved descriptor. This operation is "symmetrical" to
+ * vxge_hal_ring_rxd_reserve. The "free-ing" completes the descriptor's
+ * lifecycle.
+ *
+ * After free-ing (see vxge_hal_ring_rxd_free()) the descriptor again can
+ * be:
+ *
+ * - reserved (vxge_hal_ring_rxd_reserve);
+ *
+ * - posted	(vxge_hal_ring_rxd_post);
+ *
+ * - completed (vxge_hal_ring_rxd_next_completed);
+ *
+ * - and recycled again	(vxge_hal_ring_rxd_free).
+ *
+ * For alternative state transitions and more details please refer to
+ * the design doc.
+ *
+ */
+void
+vxge_hal_ring_rxd_free(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh);
+
+
+/*
+ * Fifo
+ */
+/*
+ * TX Descriptor
+ */
+/*
+ * enum vxge_hal_txdl_state_e - Descriptor (TXDL) state.
+ * @VXGE_HAL_TXDL_STATE_NONE: Invalid state.
+ * @VXGE_HAL_TXDL_STATE_AVAIL: Descriptor is available for reservation.
+ * @VXGE_HAL_TXDL_STATE_POSTED: Descriptor is posted for processing by the
+ * device.
+ * @VXGE_HAL_TXDL_STATE_FREED: Descriptor is free and can be reused for
+ * filling-in and posting later.
+ *
+ * X3100/HAL descriptor states.
+ *
+ */
+typedef enum vxge_hal_txdl_state_e {
+	VXGE_HAL_TXDL_STATE_NONE	= 0,
+	VXGE_HAL_TXDL_STATE_AVAIL	= 1,
+	VXGE_HAL_TXDL_STATE_POSTED	= 2,
+	VXGE_HAL_TXDL_STATE_FREED	= 3
+} vxge_hal_txdl_state_e;
+
+/*
+ * enum vxge_hal_fifo_tcode_e - tcodes used in fifo
+ * @VXGE_HAL_FIFO_T_CODE_OK: Transfer OK
+ * @VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or
+ *		frame data) returned with corrupt data.
+ * @VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned
+ *		with no data.
+ * @VXGE_HAL_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a
+ *		frame or LSO MSS that was too long (>9800B).
+ * @VXGE_HAL_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send
+ *		  Offload operation, due to improper header template,
+ *		  unsupported protocol, etc.
+ * @VXGE_HAL_FIFO_T_CODE_UNUSED: Unused
+ * @VXGE_HAL_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple
+ *		data buffer transfer errors are encountered (see below).
+ *		Otherwise it is set to 0.
+ *
+ * These tcodes are returned in various API for TxD status
+ */
+typedef enum vxge_hal_fifo_tcode_e {
+	VXGE_HAL_FIFO_T_CODE_OK			= 0x0,
+	VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT	= 0x1,
+	VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL	= 0x2,
+	VXGE_HAL_FIFO_T_CODE_INVALID_MSS	= 0x3,
+	VXGE_HAL_FIFO_T_CODE_LSO_ERROR		= 0x4,
+	VXGE_HAL_FIFO_T_CODE_UNUSED		= 0x7,
+	VXGE_HAL_FIFO_T_CODE_MULTI_ERROR	= 0x8
+} vxge_hal_fifo_tcode_e;
+
+/*
+ * enum vxge_hal_fifo_host_steer_e - Host steer type
+ * @VXGE_HAL_FIFO_HOST_STEER_NORMAL: Normal. Use Destination/MAC Address
+ *		lookup to determine the transmit porte
+ * @VXGE_HAL_FIFO_HOST_STEER_PORT1: Send on physical Port1
+ * @VXGE_HAL_FIFO_HOST_STEER_PORT0: Send on physical Port0
+ * @VXGE_HAL_FIFO_HOST_STEER_BOTH: Send on both ports.
+ *
+ * Host steer type
+ */
+typedef enum vxge_hal_fifo_host_steer_e {
+	VXGE_HAL_FIFO_HOST_STEER_NORMAL		= 0x0,
+	VXGE_HAL_FIFO_HOST_STEER_PORT1		= 0x1,
+	VXGE_HAL_FIFO_HOST_STEER_PORT0		= 0x2,
+	VXGE_HAL_FIFO_HOST_STEER_BOTH		= 0x3
+} vxge_hal_fifo_host_steer_e;
+
+/*
+ * enum vxge_hal_fifo_gather_code_e - Gather codes used in fifo TxD
+ * @VXGE_HAL_FIFO_GATHER_CODE_FIRST: First TxDL
+ * @VXGE_HAL_FIFO_GATHER_CODE_MIDDLE: Middle TxDL
+ * @VXGE_HAL_FIFO_GATHER_CODE_LAST: Last TxDL
+ * @VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.
+ *
+ * These gather codes are used to indicate the position of a TxD in a TxD list
+ */
+typedef enum vxge_hal_fifo_gather_code_e {
+	VXGE_HAL_FIFO_GATHER_CODE_FIRST		= 0x2,
+	VXGE_HAL_FIFO_GATHER_CODE_MIDDLE	= 0x0,
+	VXGE_HAL_FIFO_GATHER_CODE_LAST		= 0x1,
+	VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST	= 0x3
+} vxge_hal_fifo_gather_code_e;
+
+/*
+ * enum vxge_hal_fifo_lso_frm_encap_e - LSO Frame Encapsulation
+ * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO: auto mode (best guess)
+ * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC: LLC
+ * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP: SNAP
+ * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX: DIX
+ *
+ * LSO Frame Encapsulation type
+ */
+typedef enum vxge_hal_fifo_lso_frm_encap_e {
+	VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO	= 0x0,
+	VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC		= 0x1,
+	VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP	= 0x2,
+	VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX		= 0x3
+} vxge_hal_fifo_lso_frm_encap_e;
+
+/*
+ * struct vxge_hal_fifo_txd_t - Transmit Descriptor
+ * @control_0: Bits 0 to 6 - Reserved.
+ *	       Bit 7 - List Ownership. This field should be initialized
+ *		to '1' by the driver before the transmit list pointer is
+ *		written to the adapter. This field will be set to '0' by the
+ *		adapter once it has completed transmitting the frame or frames
+ *		in the list. Note - This field is only valid in TxD0.
+ *		Additionally, for multi-list sequences, the driver should not
+ *		release any buffers until the ownership of the last list in the
+ *		multi-list sequence has been returned to the host.
+ *	       Bits 8 to 11 - Reserved
+ *	       Bits 12 to 15 - Transfer_Code. This field is only valid in
+ *		TxD0. It is used to describe the status of the transmit data
+ *		buffer transfer. This field is always overwritten by the
+ *		adapter, so this field may be initialized to any value.
+ *	       Bits 16 to 17 - Host steering. This field allows the host to
+ *		override the selection of the physical transmit port.
+ *		Attention:
+ *		Normal sounds as if learned from the switch rather than from
+ *		the aggregation algorythms.
+ *		00: Normal. Use Destination/MAC Address
+ *		lookup to determine the transmit port.
+ *		01: Send on physical Port1.
+ *		10: Send on physical Port0.
+ *		11: Send on both ports.
+ *	       Bits 18 to 21 - Reserved
+ *	       Bits 22 to 23 - Gather_Code. This field is set by the host and
+ *		is used to describe how individual buffers comprise a frame.
+ *		10: First descriptor of a frame.
+ *		00: Middle of a multi-descriptor frame.
+ *		01: Last descriptor of a frame.
+ *		11: First and last descriptor of a frame (the entire frame
+ *		resides in a single buffer).
+ *		For multi-descriptor frames, the only valid gather code sequence
+ *		is {10, [00], 01}. In other words,the descriptors must be placed
+ *		in the list in the correct order.
+ *	       Bits 24 to 27 - Reserved
+ *	       Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation
+ *		definition. Only valid in TxD0. This field allows the host to
+ *		indicate the Ethernet encapsulation of an outbound LSO packet.
+ *		00 - classic mode (best guess)
+ *		01 - LLC
+ *		10 - SNAP
+ *		11 - DIX
+ *		If "classic mode" is selected, the adapter will attempt to
+ *		decode the frame's Ethernet encapsulation by examining the L/T
+ *		field as follows:
+ *		<= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine
+ *		if packet is IPv4 or IPv6.
+ *		0x8870 Jumbo-SNAP encoding.
+ *		0x0800 IPv4 DIX encoding
+ *		0x86DD IPv6 DIX encoding
+ *		others illegal encapsulation
+ *	       Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag.
+ *		Set to 1 to perform segmentation offload for TCP/UDP.
+ *		This field is valid only in TxD0.
+ *	       Bits 31 to 33 - Reserved.
+ *	       Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size
+ *		This field is meaningful only when LSO_Control is non-zero.
+ *		When LSO_Control is set to TCP_LSO, the single (possibly large)
+ *		TCP segment described by this TxDL will be sent as a series of
+ *		TCP segments each of which contains no more than LSO_MSS
+ *		payload bytes.
+ *		When LSO_Control is set to UDP_LSO, the single (possibly large)
+ *		UDP datagram described by this TxDL will be sent as a series of
+ *		UDP datagrams each of which contains no more than LSO_MSS
+ *		payload bytes.
+ *		All outgoing frames from this TxDL will have LSO_MSS bytes of
+ *		UDP or TCP payload, with the exception of the last, which will
+ *		have <= LSO_MSS bytes of payload.
+ *	       Bits 48 to 63 - Buffer_Size. Number of valid bytes in the
+ *		buffer to be read by the adapter. This field is written by the
+ *		host. A value of 0 is illegal.
+ *	       Bits 32 to 63 - This value is written by the adapter upon
+ *		completion of a UDP or TCP LSO operation and indicates the
+ *		number of UDP or TCP payload bytes that were transmitted.
+ *		0x0000 will bereturned for any non-LSO operation.
+ * @control_1: Bits 0 to 4 - Reserved.
+ *	       Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum
+ *		offload. This field is only valid in the first TxD of a frame.
+ *	       Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload.
+ *		This field is only valid in the first TxD of a frame (the TxD's
+ *		gather code must be 10 or 11). The driver should only set this
+ *	       Bit if it can guarantee that TCP is present.
+ *	       Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload.
+ *		This field is only valid in the first TxD of a frame (the TxD's
+ *		gather code must be 10 or 11). The driver should only set this
+ *	       Bit if it can guarantee that UDP is present.
+ *	       Bits 8 to 14 - Reserved.
+ *	       Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to
+ *		instruct the adapter to insert the VLAN tag specified by the
+ *		Tx_VLAN_Tag field. This field is only valid in the first TxD of
+ *		a frame.
+ *	       Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag
+ *		to be inserted into the frame by the adapter(the first two bytes
+ *		of a VLAN tag are always 0x8100).This field is only valid if the
+ *		Tx_VLAN_Enable field is set to '1'.
+ *	       Bits 32 to 33 - Reserved.
+ *	       Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt
+ *		number the frame associated with. This field is written by the
+ *		host. It is only valid in the first TxD of a frame.
+ *	       Bits 40 to 42 - Reserved.
+ *	       Bit 43 - Set to 1 to exclude the frame from bandwidth metering
+ *		functions. This field is valid only in the first TxD
+ *		of a frame.
+ *	       Bits 44 to 45 - Reserved.
+ *	       Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to
+ *		generate an interrupt as soon as all of the frames in the list
+ *		have been transmitted. In order to have per-frame interrupts,
+ *		the driver should place a maximum of one frame per list. This
+ *		field is only valid in the first TxD of a frame.
+ *	       Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter
+ *		to count the frame toward the utilization interrupt specified in
+ *		the Tx_Int_Number field. This field is only valid in the first
+ *		TxD of a frame.
+ *	       Bits 48 to 63 - Reserved.
+ * @buffer_pointer: Buffer start address.
+ * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the X3100
+ *	   descriptor prior to posting the latter on the fifo
+ *	   via vxge_hal_fifo_txdl_post().The %host_control is returned as is to
+ *	   the ULD with each completed descriptor.
+ *
+ * Transmit descriptor (TxD).Fifo descriptor contains configured number
+ * (list) of TxDs. * For more details please refer to X3100 User Guide,
+ * Section 5.4.2 "Transmit Descriptor (TxD) Format".
+ */
+typedef struct vxge_hal_fifo_txd_t {
+	u64 control_0;
+#define	VXGE_HAL_FIFO_TXD_LIST_OWN_GET(ctrl0)		    bVAL1(ctrl0, 7)
+#define	VXGE_HAL_FIFO_TXD_LIST_OWN_ADAPTER			mBIT(7)
+
+#define	VXGE_HAL_FIFO_TXD_T_CODE_GET(ctrl0)		    bVAL4(ctrl0, 12)
+#define	VXGE_HAL_FIFO_TXD_T_CODE(val)			    vBIT(val, 12, 4)
+#define	VXGE_HAL_FIFO_TXD_T_CODE_OK		VXGE_HAL_FIFO_T_CODE_OK
+#define	VXGE_HAL_FIFO_TXD_T_CODE_PCI_READ_CORRUPT		    \
+			VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT
+#define	VXGE_HAL_FIFO_TXD_T_CODE_PCI_READ_FAIL			    \
+			VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL
+#define	VXGE_HAL_FIFO_TXD_T_CODE_INVALID_MSS	VXGE_HAL_FIFO_T_CODE_INVALID_MSS
+#define	VXGE_HAL_FIFO_TXD_T_CODE_LSO_ERROR	VXGE_HAL_FIFO_T_CODE_LSO_ERROR
+#define	VXGE_HAL_FIFO_TXD_T_CODE_UNUSED		VXGE_HAL_FIFO_T_CODE_UNUSED
+#define	VXGE_HAL_FIFO_TXD_T_CODE_MULTI_ERROR	VXGE_HAL_FIFO_T_CODE_MULTI_ERROR
+
+#define	VXGE_HAL_FIFO_TXD_HOST_STEER_GET(ctrl0)		    bVAL2(ctrl0, 16)
+#define	VXGE_HAL_FIFO_TXD_HOST_STEER(val)		    vBIT(val, 16, 2)
+#define	VXGE_HAL_FIFO_TXD_HOST_STEER_NORMAL	VXGE_HAL_FIFO_HOST_STEER_NORMAL
+#define	VXGE_HAL_FIFO_TXD_HOST_STEER_PORT1	VXGE_HAL_FIFO_HOST_STEER_PORT1
+#define	VXGE_HAL_FIFO_TXD_HOST_STEER_PORT0	VXGE_HAL_FIFO_HOST_STEER_PORT0
+#define	VXGE_HAL_FIFO_TXD_HOST_STEER_BOTH	VXGE_HAL_FIFO_HOST_STEER_BOTH
+
+#define	VXGE_HAL_FIFO_TXD_GATHER_CODE_GET(ctrl0)	    bVAL2(ctrl0, 22)
+#define	VXGE_HAL_FIFO_TXD_GATHER_CODE(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST	VXGE_HAL_FIFO_GATHER_CODE_FIRST
+#define	VXGE_HAL_FIFO_TXD_GATHER_CODE_MIDDLE	VXGE_HAL_FIFO_GATHER_CODE_MIDDLE
+#define	VXGE_HAL_FIFO_TXD_GATHER_CODE_LAST	VXGE_HAL_FIFO_GATHER_CODE_LAST
+#define	VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST_LAST		    \
+			VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST
+
+#define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_GET(ctrl0)	    bVAL2(ctrl0, 28)
+#define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(val)		    vBIT(val, 28, 2)
+#define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_AUTO	VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO
+#define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_LLC	VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC
+#define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_SNAP	VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP
+#define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_DIX	VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX
+
+#define	VXGE_HAL_FIFO_TXD_LSO_FLAG_GET(ctrl0)		    bVAL1(ctrl0, 30)
+#define	VXGE_HAL_FIFO_TXD_LSO_FLAG			    mBIT(30)
+
+#define	VXGE_HAL_FIFO_TXD_LSO_MSS_GET(ctrl0)		    bVAL14(ctrl0, 34)
+#define	VXGE_HAL_FIFO_TXD_LSO_MSS(val)			    vBIT(val, 34, 14)
+
+#define	VXGE_HAL_FIFO_TXD_BUFFER_SIZE_GET(ctrl0)	    bVAL16(ctrl0, 48)
+#define	VXGE_HAL_FIFO_TXD_BUFFER_SIZE(val)		    vBIT(val, 48, 16)
+
+#define	VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT_GET(ctrl0)	    bVAL32(ctrl0, 32)
+#define	VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT(val)		    vBIT(val, 32, 32)
+
+	u64 control_1;
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN_GET(ctrl1)	    bVAL1(ctrl1, 5)
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN		    mBIT(5)
+
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN_GET(ctrl1)	    bVAL1(ctrl1, 6)
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN			    mBIT(6)
+
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN_GET(ctrl1)	    bVAL1(ctrl1, 7)
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN			    mBIT(7)
+
+#define	VXGE_HAL_FIFO_TXD_TX_CKO_CONTROL	(mBIT(5)|mBIT(6)|mBIT(7))
+
+#define	VXGE_HAL_FIFO_TXD_VLAN_ENABLE_GET(ctrl1)	    bVAL1(ctrl1, 15)
+#define	VXGE_HAL_FIFO_TXD_VLAN_ENABLE			    mBIT(15)
+
+#define	VXGE_HAL_FIFO_TXD_VLAN_TAG_GET(ctrl1)		    bVAL16(ctrl1, 16)
+#define	VXGE_HAL_FIFO_TXD_VLAN_TAG(val)			    vBIT(val, 16, 16)
+
+#define	VXGE_HAL_FIFO_TXD_INT_NUMBER_GET(ctrl1)		    bVAL6(ctrl1, 34)
+#define	VXGE_HAL_FIFO_TXD_INT_NUMBER(val)		    vBIT(val, 34, 6)
+
+#define	VXGE_HAL_FIFO_TXD_NO_BW_LIMIT_GET(ctrl1)	    bVAL1(ctrl1, 43)
+#define	VXGE_HAL_FIFO_TXD_NO_BW_LIMIT			    mBIT(43)
+
+#define	VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST_GET(ctrl1)	    bVAL1(ctrl1, 46)
+#define	VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST		    mBIT(46)
+
+#define	VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ_GET(ctrl1)	    bVAL1(ctrl1, 47)
+#define	VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ		    mBIT(47)
+
+	u64 buffer_pointer;
+
+	u64 host_control;
+
+} vxge_hal_fifo_txd_t;
+
+typedef vxge_hal_fifo_txd_t *vxge_hal_fifo_txdl_t;
+
+/*
+ * function vxge_hal_fifo_callback_f - FIFO callback.
+ * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed
+ *		descriptors.
+ * @txdlh: First completed descriptor.
+ * @txdl_priv: Pointer to per txdl space allocated
+ * @t_code: Transfer code, as per X3100 User Guide.
+ *	 Returned by HAL.
+ * @host_control: Opaque 64bit data stored by ULD inside the X3100
+ *	   descriptor prior to posting the latter on the fifo
+ *	   via vxge_hal_fifo_txdl_post(). The @host_control is returned
+ *	   as is to the ULD with each completed descriptor.
+ * @userdata: Opaque per-fifo data specified at fifo open
+ *	   time, via vxge_hal_vpath_open().
+ *
+ * Fifo completion callback (type declaration). A single per-fifo
+ * callback is specified at fifo open time, via
+ * vxge_hal_vpath_open(). Typically gets called as part of the processing
+ * of the Interrupt Service Routine.
+ *
+ * Fifo callback gets called by HAL if, and only if, there is at least
+ * one new completion on a given fifo. Upon processing the first @txdlh ULD
+ * is _supposed_ to continue consuming completions using:
+ *	- vxge_hal_fifo_txdl_next_completed()
+ *
+ * Note that failure to process new completions in a timely fashion
+ * leads to VXGE_HAL_INF_OUT_OF_DESCRIPTORS condition.
+ *
+ * Non-zero @t_code means failure to process transmit descriptor.
+ *
+ * In the "transmit" case the failure could happen, for instance, when the
+ * link is down, in which case X3100 completes the descriptor because it
+ * is not able to send the data out.
+ *
+ * For details please refer to X3100 User Guide.
+ *
+ * See also: vxge_hal_fifo_txdl_next_completed(), vxge_hal_fifo_txdl_term_f {}.
+ */
+typedef vxge_hal_status_e(*vxge_hal_fifo_callback_f) (
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    void *txdl_priv,
+    vxge_hal_fifo_tcode_e t_code,
+    void *userdata);
+
+/*
+ * function vxge_hal_fifo_txdl_init_f - Initialize descriptor callback.
+ * @vpath_handle: Virtual path whose Fifo "containing" the @txdlh descriptor.
+ * @txdlh: Descriptor.
+ * @txdl_priv: Pointer to per txdl space allocated
+ * @index: Index of the descriptor in the fifo's set of descriptors.
+ * @userdata: Per-fifo user data (a.k.a. context) specified at
+ * fifo open time, via vxge_hal_vpath_open().
+ * @reopen: See  vxge_hal_reopen_e {}.
+ *
+ * Initialize descriptor callback. Unless NULL is specified in the
+ * vxge_hal_fifo_attr_t {} structure passed to vxge_hal_vpath_open()),
+ * HAL invokes the callback as part of the vxge_hal_vpath_open()
+ * implementation.
+ * The ULD could use the callback to pre-set DMA mappings and/or alignment
+ * buffers.
+ *
+ * See also: vxge_hal_fifo_attr_t {}, vxge_hal_fifo_txdl_term_f {}.
+ */
+typedef vxge_hal_status_e(*vxge_hal_fifo_txdl_init_f) (
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    void *txdl_priv,
+    u32 index,
+    void *userdata,
+    vxge_hal_reopen_e reopen);
+
+/*
+ * function vxge_hal_fifo_txdl_term_f - Terminate descriptor callback.
+ * @vpath_handle: Virtual path whose Fifo "containing" the @txdlh descriptor.
+ * @txdlh: First completed descriptor.
+ * @txdl_priv: Pointer to per txdl space allocated
+ * @state: One of the vxge_hal_txdl_state_e {} enumerated states.
+ * @userdata: Per-fifo user data (a.k.a. context) specified at
+ * fifo open time, via vxge_hal_vpath_open().
+ * @reopen: See  vxge_hal_reopen_e {}.
+ *
+ * Terminate descriptor callback. Unless NULL is specified in the
+ * vxge_hal_fifo_attr_t {} structure passed to vxge_hal_vpath_open()),
+ * HAL invokes the callback as part of closing fifo, prior to
+ * de-allocating the ring and associated data structures
+ * (including descriptors).
+ * ULD should utilize the callback to (for instance) unmap
+ * and free DMA data buffers associated with the posted (state =
+ * VXGE_HAL_TXDL_STATE_POSTED) descriptors,
+ * as well as other relevant cleanup functions.
+ *
+ * See also: vxge_hal_fifo_attr_t {}, vxge_hal_fifo_txdl_init_f {}.
+ */
+typedef void (*vxge_hal_fifo_txdl_term_f) (
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    void *txdl_priv,
+    vxge_hal_txdl_state_e state,
+    void *userdata,
+    vxge_hal_reopen_e reopen);
+
+/*
+ * struct vxge_hal_fifo_attr_t - Fifo open "template".
+ * @callback: Fifo completion callback. HAL invokes the callback when there
+ *	   are new completions on that fifo. In many implementations
+ *	   the @callback executes in the hw interrupt context.
+ * @txdl_init: Fifo's descriptor-initialize callback.
+ *	   See vxge_hal_fifo_txdl_init_f {}.
+ *	   If not NULL, HAL invokes the callback when opening
+ *	   the fifo via vxge_hal_vpath_open().
+ * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
+ *	 HAL invokes the callback when closing the corresponding fifo.
+ *	 See also vxge_hal_fifo_txdl_term_f {}.
+ * @userdata: User-defined "context" of _that_ fifo. Passed back to the
+ *	   user as one of the @callback, @txdl_init, and @txdl_term arguments.
+ * @per_txdl_space: If specified (i.e., greater than zero): extra space
+ *		 reserved by HAL per each transmit descriptor. Can be used to
+ *		 store, and retrieve on completion, information specific
+ *		 to the upper-layer.
+ *
+ * Fifo open "template". User fills the structure with fifo
+ * attributes and passes it to vxge_hal_vpath_open().
+ */
+typedef struct vxge_hal_fifo_attr_t {
+	vxge_hal_fifo_callback_f		callback;
+	vxge_hal_fifo_txdl_init_f		txdl_init;
+	vxge_hal_fifo_txdl_term_f		txdl_term;
+	void					*userdata;
+	u32					per_txdl_space;
+} vxge_hal_fifo_attr_t;
+
+/*
+ * vxge_hal_fifo_doorbell_reset - Resets the doorbell fifo
+ * @vpath_handle: Vpath Handle
+ *
+ * This function resets the doorbell fifo during if fifo error occurs
+ */
+vxge_hal_status_e
+vxge_hal_fifo_doorbell_reset(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_fifo_txdl_reserve - Reserve fifo descriptor.
+ * @vpath_handle: virtual path handle.
+ * @txdlh: Reserved descriptor. On success HAL fills this "out" parameter
+ *	with a valid handle.
+ * @txdl_priv: Buffer to return the pointer to per txdl space allocated
+ *
+ * Reserve a single TxDL (that is, fifo descriptor)
+ * for the subsequent filling-in by upper layerdriver (ULD))
+ * and posting on the corresponding fifo
+ * via vxge_hal_fifo_txdl_post().
+ *
+ * Note: it is the responsibility of ULD to reserve multiple descriptors
+ * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
+ * carries up to configured number (fifo.max_frags) of contiguous buffers.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
+ *
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_reserve(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h *txdlh,
+    void **txdl_priv);
+
+
+/*
+ * vxge_hal_fifo_txdl_cksum_set_bits - Offload checksum.
+ * @txdlh: Descriptor handle.
+ * @cksum_bits: Specifies which checksums are to be offloaded: IPv4,
+ *		 and/or TCP and/or UDP.
+ *
+ * Ask X3100 to calculate IPv4 & transport checksums for _this_ transmit
+ * descriptor.
+ * This API is part of the preparation of the transmit descriptor for posting
+ * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include
+ * vxge_hal_fifo_txdl_mss_set(), vxge_hal_fifo_txdl_buffer_set_aligned(),
+ * and vxge_hal_fifo_txdl_buffer_set().
+ * All these APIs fill in the fields of the fifo descriptor,
+ * in accordance with the X3100 specification.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_fifo_txdl_cksum_set_bits(
+    vxge_hal_txdl_h txdlh,
+    u64 cksum_bits)
+{
+	vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh;
+
+	txdp->control_1 |= cksum_bits;
+
+}
+
+/*
+ * vxge_hal_fifo_txdl_interrupt_type_set - Set the interrupt type for the txdl
+ * @txdlh: Descriptor handle.
+ * @interrupt_type: utiliz based interupt or List interrupt
+ *
+ * vxge_hal_fifo_txdl_interrupt_type_set is used to set the interrupt type for
+ * each xmit txdl dynamically
+ */
+static	inline
+/* LINTED */
+void vxge_hal_fifo_txdl_interrupt_type_set(
+    vxge_hal_txdl_h txdlh,
+    u64 interrupt_type)
+{
+	vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh;
+
+	txdp->control_1 |= interrupt_type;
+}
+
+/*
+ * vxge_hal_fifo_txdl_lso_set - Set LSO Parameters.
+ * @txdlh: Descriptor handle.
+ * @encap: LSO Encapsulation
+ * @mss: MSS size for LSO.
+ *
+ * This API is part of the preparation of the transmit descriptor for posting
+ * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include
+ * vxge_hal_fifo_txdl_buffer_set(), vxge_hal_fifo_txdl_buffer_set_aligned(),
+ * and vxge_hal_fifo_txdl_cksum_set_bits().
+ * All these APIs fill in the fields of the fifo descriptor,
+ * in accordance with the X3100 specification.
+ *
+ */
+static	inline
+/* LINTED */
+void vxge_hal_fifo_txdl_lso_set(
+    vxge_hal_txdl_h txdlh,
+    u32 encap,
+    u32 mss)
+{
+	vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh;
+
+	txdp->control_0 |= VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(encap) |
+	    VXGE_HAL_FIFO_TXD_LSO_FLAG | VXGE_HAL_FIFO_TXD_LSO_MSS(mss);
+}
+
+/*
+ * vxge_hal_fifo_txdl_lso_bytes_sent - Get the lso bytes sent.
+ * @txdlh: Descriptor handle.
+ *
+ * Returns the lso bytes sent
+ */
+static	inline
+/* LINTED */
+u32 vxge_hal_fifo_txdl_lso_bytes_sent(
+    vxge_hal_txdl_h txdlh)
+{
+	vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh;
+
+	return (u32) VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT_GET(txdp->control_0);
+}
+
+/*
+ * vxge_hal_fifo_txdl_vlan_set - Set VLAN tag.
+ * @txdlh: Descriptor handle.
+ * @vlan_tag: 16bit VLAN tag.
+ *
+ * Insert VLAN tag into specified transmit descriptor.
+ * The actual insertion of the tag into outgoing frame is done by the hardware.
+ */
+static	inline
+/* LINTED */
+void vxge_hal_fifo_txdl_vlan_set(
+    vxge_hal_txdl_h txdlh,
+    u16 vlan_tag)
+{
+	vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh;
+
+	txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_ENABLE;
+	txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_TAG(vlan_tag);
+}
+
+/*
+ * vxge_hal_fifo_txdl_buffer_set - Set transmit buffer pointer in the
+ * descriptor.
+ * @vpath_handle: virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @frag_idx: Index of the data buffer in the caller's scatter-gather list¤
+ *	   (of buffers).
+ * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
+ * @size: Size of the data buffer (in bytes).
+ *
+ * This API is part of the preparation of the transmit descriptor for posting
+ * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include
+ * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits().
+ * All three APIs fill in the fields of the fifo descriptor,
+ * in accordance with the X3100 specification.
+ *
+ */
+void
+vxge_hal_fifo_txdl_buffer_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 frag_idx,
+    dma_addr_t dma_pointer,
+    unsigned long size);
+
+/*
+ * vxge_hal_fifo_txdl_buffer_set_aligned - Align transmit buffer and fill
+ * in fifo descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @frag_idx: Index of the data buffer in the caller's scatter-gather list¤
+ *	   (of buffers).
+ * @vaddr: Virtual address of the data buffer.
+ * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
+ * @size: Size of the data buffer (in bytes).
+ * @misaligned_size: Size (in bytes) of the misaligned portion of the
+ * data buffer. Calculated by the caller, based on the platform/OS/other
+ * specific criteria, which is outside of HAL's domain. See notes below.
+ *
+ * This API is part of the transmit descriptor preparation for posting
+ * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include
+ * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits().
+ * All three APIs fill in the fields of the fifo descriptor,
+ * in accordance with the X3100 specification.
+ * On the PCI-X based systems aligning transmit data typically provides better
+ * transmit performance. The typical alignment granularity: L2 cacheline size.
+ * However, HAL does not make assumptions in terms of the alignment granularity;
+ * this is specified via additional @misaligned_size parameter described above.
+ * Prior to calling vxge_hal_fifo_txdl_buffer_set_aligned(),
+ * ULD is supposed to check alignment of a given fragment/buffer. For this HAL
+ * provides a separate vxge_hal_check_alignment() API sufficient to cover
+ * most (but not all) possible alignment criteria.
+ * If the buffer appears to be aligned, the ULD calls
+ * vxge_hal_fifo_txdl_buffer_set().
+ * Otherwise, ULD calls vxge_hal_fifo_txdl_buffer_set_aligned().
+ *
+ * Note; This API is a "superset" of vxge_hal_fifo_txdl_buffer_set(). In
+ * addition to filling in the specified descriptor it aligns transmit data on
+ * the specified boundary.
+ * Note: Decision on whether to align or not to align a given contiguous
+ * transmit buffer is outside of HAL's domain. To this end ULD can use any
+ * programmable criteria, which can help to 1) boost transmit performance,
+ * and/or 2) provide a workaround for PCI bridge bugs, if any.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_buffer_set_aligned(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 frag_idx,
+    void *vaddr,
+    dma_addr_t dma_pointer,
+    u32 size,
+    u32 misaligned_size);
+
+/*
+ * vxge_hal_fifo_txdl_buffer_append - Append the contents of virtually
+ *		contiguous data buffer to a single physically contiguous buffer.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @vaddr: Virtual address of the data buffer.
+ * @size: Size of the data buffer (in bytes).
+ *
+ * This API is part of the transmit descriptor preparation for posting
+ * (via vxge_hal_fifo_txdl_post()).
+ * The main difference of this API wrt to the APIs
+ * vxge_hal_fifo_txdl_buffer_set_aligned() is that this API appends the
+ * contents of virtually contiguous data buffers received from
+ * upper layer into a single physically contiguous data buffer and the
+ * device will do a DMA from this buffer.
+ *
+ * See Also: vxge_hal_fifo_txdl_buffer_finalize(),
+ * vxge_hal_fifo_txdl_buffer_set(),
+ * vxge_hal_fifo_txdl_buffer_set_aligned().
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_buffer_append(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    void *vaddr,
+    u32 size);
+/*
+ * vxge_hal_fifo_txdl_buffer_finalize - Prepares a descriptor that contains the
+ * single physically contiguous buffer.
+ *
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @frag_idx: Index of the data buffer in the Txdl list.
+ *
+ * This API in conjuction with vxge_hal_fifo_txdl_buffer_append() prepares
+ * a descriptor that consists of a single physically contiguous buffer
+ * which inturn contains the contents of one or more virtually contiguous
+ * buffers received from the upper layer.
+ *
+ * See Also: vxge_hal_fifo_txdl_buffer_append().
+ */
+void
+vxge_hal_fifo_txdl_buffer_finalize(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 frag_idx);
+
+/*
+ * vxge_hal_fifo_txdl_new_frame_set - Start the new packet by setting TXDL flags
+ * @vpath_handle: virtual path handle.
+ * @txdlh: Descriptor handle.
+ *
+ * This API is part of the preparation of the transmit descriptor for posting
+ * (via vxge_hal_fifo_txdl_post()). This api is used to mark the end of previous
+ * frame and start of a new frame.
+ *
+ */
+void
+vxge_hal_fifo_txdl_new_frame_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 tagged);
+
+/*
+ * vxge_hal_fifo_txdl_post - Post descriptor on the fifo.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor obtained via vxge_hal_fifo_txdl_reserve()
+ *
+ * Post descriptor on the fifo for transmission.
+ * Prior to posting the descriptor should be filled in accordance with
+ * Host/X3100 interface specification for a given service (LL, etc.).
+ *
+ */
+void
+vxge_hal_fifo_txdl_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 tagged);
+
+/*
+ * vxge_hal_fifo_is_next_txdl_completed - Checks if the next txdl is completed
+ * @vpath_handle: Virtual path handle.
+ */
+vxge_hal_status_e
+vxge_hal_fifo_is_next_txdl_completed(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_fifo_free_txdl_count_get - returns the number of txdls available
+ *                   in the fifo
+ * @vpath_handle: Virtual path handle.
+ */
+u32
+vxge_hal_fifo_free_txdl_count_get(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_fifo_txdl_next_completed - Retrieve next completed descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle. Returned by HAL.
+ * @txdl_priv: Buffer to return the pointer to per txdl space allocated
+ * @t_code: Transfer code, as per X3100 User Guide,
+ *	 Transmit Descriptor Format.
+ *	 Returned by HAL.
+ *
+ * Retrieve the _next_ completed descriptor.
+ * HAL uses fifo callback (*vxge_hal_fifo_callback_f) to notifiy
+ * upper-layer driver (ULD) of new completed descriptors. After that
+ * the ULD can use vxge_hal_fifo_txdl_next_completed to retrieve the rest
+ * completions (the very first completion is passed by HAL via
+ * vxge_hal_fifo_callback_f).
+ *
+ * Implementation-wise, the upper-layer driver is free to call
+ * vxge_hal_fifo_txdl_next_completed either immediately from inside the
+ * fifo callback, or in a deferred fashion and separate (from HAL)
+ * context.
+ *
+ * Non-zero @t_code means failure to process the descriptor.
+ * The failure could happen, for instance, when the link is
+ * down, in which case X3100 completes the descriptor because it
+ * is not able to send the data out.
+ *
+ * For details please refer to X3100 User Guide.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
+ * are currently available for processing.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_next_completed(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h *txdlh,
+    void **txdl_priv,
+    vxge_hal_fifo_tcode_e *t_code);
+
+/*
+ * vxge_hal_fifo_handle_tcode - Handle transfer code.
+ * @vpath_handle: Virtual Path handle.
+ * @txdlh: Descriptor handle.
+ * @t_code: One of the enumerated (and documented in the X3100 user guide)
+ *	 "transfer codes".
+ *
+ * Handle descriptor's transfer code. The latter comes with each completed
+ * descriptor.
+ *
+ * Returns: one of the vxge_hal_status_e {} enumerated types.
+ * VXGE_HAL_OK			- for success.
+ * VXGE_HAL_ERR_CRITICAL	- when encounters critical error.
+ */
+vxge_hal_status_e
+vxge_hal_fifo_handle_tcode(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    vxge_hal_fifo_tcode_e t_code);
+
+/*
+ * vxge_hal_fifo_txdl_private_get - Retrieve per-descriptor private data.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ *
+ * Retrieve per-descriptor private data.
+ * Note that ULD requests per-descriptor space via
+ * vxge_hal_fifo_attr_t passed to
+ * vxge_hal_vpath_open().
+ *
+ * Returns: private ULD data associated with the descriptor.
+ */
+void *
+vxge_hal_fifo_txdl_private_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh);
+
+/*
+ * vxge_hal_fifo_txdl_free - Free descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ *
+ * Free the reserved descriptor. This operation is "symmetrical" to
+ * vxge_hal_fifo_txdl_reserve. The "free-ing" completes the descriptor's
+ * lifecycle.
+ *
+ * After free-ing (see vxge_hal_fifo_txdl_free()) the descriptor again can
+ * be:
+ *
+ * - reserved (vxge_hal_fifo_txdl_reserve);
+ *
+ * - posted (vxge_hal_fifo_txdl_post);
+ *
+ * - completed (vxge_hal_fifo_txdl_next_completed);
+ *
+ * - and recycled again (vxge_hal_fifo_txdl_free).
+ *
+ * For alternative state transitions and more details please refer to
+ * the design doc.
+ *
+ */
+void
+vxge_hal_fifo_txdl_free(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh);
+
+/*
+ * Device
+ */
+
+/*
+ * enum vxge_hal_card_e - X3100 adapter type.
+ * @VXGE_HAL_CARD_UNKNOWN: Unknown device.
+ * @VXGE_HAL_CARD_TITAN: X3100 device.
+ *
+ * Enumerates X3100 adapter types.
+ *
+ * See also: vxge_hal_device_check_id().
+ */
+typedef enum vxge_hal_card_e {
+	VXGE_HAL_CARD_UNKNOWN	= 0,
+	VXGE_HAL_CARD_TITAN_1	= 1,
+	VXGE_HAL_CARD_TITAN_1A	= 2,
+	VXGE_HAL_CARD_TITAN_2	= 3
+} vxge_hal_card_e;
+
+/*
+ * struct vxge_hal_device_attr_t - Device memory spaces.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @regh1: BAR1 mapped memory handle. Same comment as above.
+ * @regh2: BAR2 mapped memory handle. Same comment as above.
+ * @bar0: BAR0 virtual address.
+ * @bar1: BAR1 virtual address.
+ * @bar2: BAR2 virtual address.
+ * @irqh: IRQ handle (Solaris).
+ * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
+ * @pdev: PCI device object.
+ *
+ * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
+ * mapped memories. Also, includes a pointer to OS-specific PCI device object.
+ */
+typedef struct vxge_hal_device_attr_t {
+	pci_reg_h		regh0;
+	pci_reg_h		regh1;
+	pci_reg_h		regh2;
+	u8			*bar0;
+	u8			*bar1;
+	u8			*bar2;
+	pci_irq_h		irqh;
+	pci_cfg_h		cfgh;
+	pci_dev_h		pdev;
+} vxge_hal_device_attr_t;
+
+/*
+ * enum vxge_hal_device_link_state_e - Link state enumeration.
+ * @VXGE_HAL_LINK_NONE: Invalid link state.
+ * @VXGE_HAL_LINK_DOWN: Link is down.
+ * @VXGE_HAL_LINK_UP: Link is up.
+ *
+ */
+typedef enum vxge_hal_device_link_state_e {
+	VXGE_HAL_LINK_NONE,
+	VXGE_HAL_LINK_DOWN,
+	VXGE_HAL_LINK_UP
+} vxge_hal_device_link_state_e;
+
+/*
+ * enum vxge_hal_device_data_rate_e - Data rate enumeration.
+ * @VXGE_HAL_DATA_RATE_UNKNOWN: Unknown .
+ * @VXGE_HAL_DATA_RATE_1G: 1G.
+ * @VXGE_HAL_DATA_RATE_10G: 10G.
+ *
+ */
+typedef enum vxge_hal_device_data_rate_e {
+	VXGE_HAL_DATA_RATE_UNKNOWN,
+	VXGE_HAL_DATA_RATE_1G,
+	VXGE_HAL_DATA_RATE_10G
+} vxge_hal_device_data_rate_e;
+
+/*
+ * enum vxge_hal_device_lag_mode_e - X3100 adapter lag mode
+ * @VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN: Unknown mode.
+ * @VXGE_HAL_DEVICE_LAG_MODE_HW_LACP: Hardware Link Aggregation.
+ * @VXGE_HAL_DEVICE_LAG_MODE_ACTIVE_PASSIVE: Active Passive.
+ * @VXGE_HAL_DEVICE_LAG_MODE_SINGLE_PORT: Single Port.
+ * @VXGE_HAL_DEVICE_LAG_MODE_DUAL_PORT: Dual Port.
+ * @VXGE_HAL_DEVICE_LAG_MODE_DISABLED: Disabled.
+ *
+ * Enumerates X3100 adapter lag modes.
+ *
+ */
+typedef enum vxge_hal_device_lag_mode_e {
+	VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN = 0,
+	VXGE_HAL_DEVICE_LAG_MODE_HW_LACP,
+	VXGE_HAL_DEVICE_LAG_MODE_ACTIVE_PASSIVE,
+	VXGE_HAL_DEVICE_LAG_MODE_SINGLE_PORT,
+	VXGE_HAL_DEVICE_LAG_MODE_DUAL_PORT,
+	VXGE_HAL_DEVICE_LAG_MODE_DISABLED
+} vxge_hal_device_lag_mode_e;
+
+/*
+ * enum vxge_hal_pci_e_signalling_rate_e -  PCI-E Lane signalling rate
+ * @VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB:   PCI-E signalling rate 2.5 GB
+ * @VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB:	    PCI-E signalling rate 5 GB
+ * @VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN: Unrecognized PCI bus frequency
+ *
+ * PCI-E Lane signalling rate
+ */
+typedef enum vxge_hal_pci_e_signalling_rate_e {
+	VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB	= 1,
+	VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB	= 2,
+	VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN	= 0
+} vxge_hal_pci_e_signalling_rate_e;
+
+/*
+ * enum vxge_hal_pci_e_link_width_e - PCI-E Link width enumeration.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X1:	1 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X2:	2 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X4:	4 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X8:	8 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X12:	12 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X16:	16 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_X32:	32 Lane.
+ * @VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN:	Unknown
+ *
+ * PCI-E Link width enumeration.
+ */
+typedef enum vxge_hal_pci_e_link_width_e {
+	VXGE_HAL_PCI_E_LINK_WIDTH_X1		= 1,
+	VXGE_HAL_PCI_E_LINK_WIDTH_X2		= 2,
+	VXGE_HAL_PCI_E_LINK_WIDTH_X4		= 4,
+	VXGE_HAL_PCI_E_LINK_WIDTH_X8		= 8,
+	VXGE_HAL_PCI_E_LINK_WIDTH_X12		= 12,
+	VXGE_HAL_PCI_E_LINK_WIDTH_X16		= 16,
+	VXGE_HAL_PCI_E_LINK_WIDTH_X32		= 32,
+	VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN	= 0
+} vxge_hal_pci_e_link_width_e;
+
+#define	VXGE_HAL_DEVICE_STATS_SW_INFO_NOT_TRAFFIC_INTR(hldev)	\
+	((vxge_hal_device_t *)hldev)->not_traffic_intr_cnt++
+
+#define	VXGE_HAL_DEVICE_STATS_SW_INFO_TRAFFIC_INTR(hldev)	\
+	((vxge_hal_device_t *)hldev)->traffic_intr_cnt++
+
+/*
+ * struct vxge_hal_device_t - Hal device object
+ * @magic: Magic Number
+ * @device_id: PCI Device Id of the adapter
+ * @revision: PCI Device major revision
+ * @upper_layer_data: Private data set by LL driver
+ * @signalling_rate: PCI-E signalling rate
+ * @link_width: see vxge_hal_pci_e_link_width_e {}
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @regh1: BAR1 mapped memory handle. Same comment as above.
+ * @regh2: BAR2 mapped memory handle. Same comment as above.
+ * @bar0: BAR0 virtual address.
+ * @bar1: BAR1 virtual address.
+ * @bar2: BAR2 virtual address.
+ * @irqh: IRQ handle
+ * @cfgh: Configuration space handle
+ * @pdev: Physical device handle
+ * @config: Confguration passed by the LL driver at initialization
+ * @is_initialized: Flag to specify if device is initialized
+ * @msix_enabled: Flag to indicate if msix is enabled
+ * @terminating: Flag to specify if the device is terminating
+ * @link_state: Link state
+ * @data_rate: Data rate
+ * @not_traffic_intr_cnt: Number of times the host was interrupted
+ *			without new completions.
+ *		    "Non-traffic interrupt counter".
+ * @traffic_intr_cnt: Number of traffic interrupts for the device.
+ * @debug_module_mask: Debug module mask
+ * @debug_level: Debug Level
+ *
+ * HAL device object. Represents Titan adapter
+ */
+typedef struct vxge_hal_device_t {
+	u32					magic;
+#define	VXGE_HAL_DEVICE_MAGIC					0x12345678
+#define	VXGE_HAL_DEVICE_DEAD					0xDEADDEAD
+	u16					device_id;
+	u16					revision;
+	void					*upper_layer_data;
+	vxge_hal_pci_e_signalling_rate_e	signalling_rate;
+	vxge_hal_pci_e_link_width_e		link_width;
+	pci_reg_h				regh0;
+	pci_reg_h				regh1;
+	pci_reg_h				regh2;
+	u8					*bar0;
+	u8					*bar1;
+	u8					*bar2;
+	pci_irq_h				irqh;
+	pci_cfg_h				cfgh;
+	pci_dev_h				pdev;
+	vxge_hal_device_config_t		config;
+	volatile u32				is_initialized;
+	volatile u32				msix_enabled;
+	volatile u32				terminating;
+	volatile vxge_hal_device_link_state_e	link_state;
+	volatile vxge_hal_device_data_rate_e	data_rate;
+	volatile u32				not_traffic_intr_cnt;
+	volatile u32				traffic_intr_cnt;
+	u32					debug_module_mask;
+	u32					debug_level;
+} vxge_hal_device_t;
+
+/*
+ * struct vxge_hal_device_date_t - Date Format
+ * @day: Day
+ * @month: Month
+ * @year: Year
+ * @date: Date in string format
+ *
+ * Structure for returning date
+ */
+typedef struct vxge_hal_device_date_t {
+	u32	day;
+	u32	month;
+	u32	year;
+	char	date[16];
+} vxge_hal_device_date_t;
+
+/*
+ * struct vxge_hal_device_version_t - Version Format
+ * @major: Major Version
+ * @minor: Minor Version
+ * @build: Build Number
+ * @version: Version in string format
+ *
+ * Structure for returning version
+ */
+typedef struct vxge_hal_device_version_t {
+	u32	major;
+	u32	minor;
+	u32	build;
+	char	version[32];
+} vxge_hal_device_version_t;
+
+/*
+ * struct vxge_hal_device_pmd_info_t - PMD Information
+ * @type: PMD Type
+ * @vendor: Vender name
+ * @part_num: PMD Part Number
+ * @ser_num: PMD Serial Number
+ *
+ * Structure for returning PMD info
+ */
+typedef struct vxge_hal_device_pmd_info_t {
+	u32	type;
+#define	VXGE_HAL_DEVICE_PMD_TYPE_UNKNOWN	0
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_SR		1
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_LR		2
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_LRM	3
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_DIRECT	4
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_CX4	5
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_BASE_T	6
+#define	VXGE_HAL_DEVICE_PMD_TYPE_10G_OTHER	7
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_SX		8
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_LX		9
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_CX		10
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_DIRECT	11
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_CX4		12
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_BASE_T	13
+#define	VXGE_HAL_DEVICE_PMD_TYPE_1G_OTHER	14
+	u32	unused;
+	char	vendor[24];
+	char	part_num[24];
+	char	ser_num[24];
+} vxge_hal_device_pmd_info_t;
+
+
+/*
+ * struct vxge_hal_device_hw_info_t - Device information
+ * @host_type: Host Type
+ * @function_mode: PCI Function Mode
+ * @func_id: Function Id
+ * @vpath_mask: vpath bit mask
+ * @fw_version: Firmware version
+ * @fw_date: Firmware Date
+ * @flash_version: Firmware version
+ * @flash_date: Firmware Date
+ * @serial_number: Card Serial Number
+ * @part_number: Card Part Number
+ * @product_description: Card Product Description
+ * @unused: For Solaris alignment purpose
+ * @ports: Number of ports present
+ * @pmd_port0: Port 0 PMD Info
+ * @pmd_port1: Port 1 PMD Info
+ * @mac_addrs: Mac addresses for each vpath
+ * @mac_addr_masks: Mac address masks for each vpath
+ *
+ * Returns the vpath mask that has the bits set for each vpath allocated
+ * for the driver and teh first mac addresse for each vpath
+ */
+typedef struct vxge_hal_device_hw_info_t {
+	u32			 host_type;
+#define	VXGE_HAL_NO_MR_NO_SR_NORMAL_FUNCTION			0
+#define	VXGE_HAL_MR_NO_SR_VH0_BASE_FUNCTION			1
+#define	VXGE_HAL_NO_MR_SR_VH0_FUNCTION0				2
+#define	VXGE_HAL_NO_MR_SR_VH0_VIRTUAL_FUNCTION			3
+#define	VXGE_HAL_MR_SR_VH0_INVALID_CONFIG			4
+#define	VXGE_HAL_SR_VH_FUNCTION0				5
+#define	VXGE_HAL_SR_VH_VIRTUAL_FUNCTION				6
+#define	VXGE_HAL_VH_NORMAL_FUNCTION				7
+	u64			 function_mode;
+	u32			 func_id;
+	u64			 vpath_mask;
+	vxge_hal_device_version_t fw_version;
+	vxge_hal_device_date_t	 fw_date;
+	vxge_hal_device_version_t flash_version;
+	vxge_hal_device_date_t	 flash_date;
+	u8			 serial_number[24];
+	u8			 part_number[24];
+	u8			 product_description[72];
+	u32			 unused;
+	u32			 ports;
+	vxge_hal_device_pmd_info_t pmd_port0;
+	vxge_hal_device_pmd_info_t pmd_port1;
+	macaddr_t		 mac_addrs[VXGE_HAL_MAX_VIRTUAL_PATHS];
+	macaddr_t		 mac_addr_masks[VXGE_HAL_MAX_VIRTUAL_PATHS];
+} vxge_hal_device_hw_info_t;
+
+/*
+ * vxge_hal_device_hw_info_get - Get the hw information
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @bar0: Address of BAR0 in PCI config
+ * @hw_info: Buffer to return vxge_hal_device_hw_info_t {} structure
+ *
+ * Returns the vpath mask that has the bits set for each vpath allocated
+ * for the driver, FW version information and the first mac addresse for
+ * each vpath
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_info_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u8 *bar0,
+    vxge_hal_device_hw_info_t *hw_info);
+
+/*
+ * vxge_hal_device_config_default_get - Initialize device config with defaults.
+ * @device_config: Configuration structure to be initialized,
+ *		For the X3100 configuration "knobs" please
+ *		refer to vxge_hal_device_config_t and X3100
+ *		User Guide.
+ *
+ * Initialize X3100 device config with default values.
+ *
+ * See also: vxge_hal_device_initialize(), vxge_hal_device_terminate(),
+ * vxge_hal_status_e {} vxge_hal_device_attr_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_config_default_get(
+    vxge_hal_device_config_t *device_config);
+
+/*
+ * vxge_hal_device_initialize - Initialize X3100 device.
+ * @devh: Buffer to return HAL device handle.
+ * @attr: pointer to vxge_hal_device_attr_t structure
+ * @device_config: Configuration to be _applied_ to the device,
+ * For the X3100 configuration "knobs" please refer to
+ * vxge_hal_device_config_t and X3100 User Guide.
+ *
+ * Initialize X3100 device. Note that all the arguments of this public API
+ * are 'IN', except @hldev. Upper-layer driver (ULD) cooperates with
+ * OS to find new X3100 device, locate its PCI and memory spaces.
+ *
+ * When done, the ULD allocates sizeof(vxge_hal_device_t) bytes for HAL
+ * to enable the latter to perform X3100 hardware initialization.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - Driver is not initialized.
+ * VXGE_HAL_ERR_BAD_DEVICE_CONFIG - Device configuration params are not
+ * valid.
+ * VXGE_HAL_ERR_OUT_OF_MEMORY - Memory allocation failed.
+ * VXGE_HAL_ERR_BAD_SUBSYSTEM_ID - Device subsystem id is invalid.
+ * VXGE_HAL_ERR_INVALID_MAC_ADDRESS - Device mac address in not valid.
+ * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to retrieve the mac
+ * address within the time(timeout) or TTI/RTI initialization failed.
+ * VXGE_HAL_ERR_SWAPPER_CTRL - Failed to configure swapper control.
+ *
+ * See also: vxge_hal_device_terminate(), vxge_hal_status_e {}
+ * vxge_hal_device_attr_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_initialize(
+    vxge_hal_device_h *devh,
+    vxge_hal_device_attr_t *attr,
+    vxge_hal_device_config_t *device_config);
+
+/*
+ * vxge_hal_device_check_id - Verify device ID.
+ * @devh: HAL device handle.
+ *
+ * Verify device ID.
+ * Returns: one of the vxge_hal_card_e {} enumerated types.
+ * See also: vxge_hal_card_e {}.
+ */
+static	inline
+/* LINTED */
+vxge_hal_card_e vxge_hal_device_check_id(
+    vxge_hal_device_h devh)
+{
+	vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
+	switch (hldev->device_id) {
+	case VXGE_PCI_DEVICE_ID_TITAN_1:
+		if (hldev->revision == VXGE_PCI_REVISION_TITAN_1)
+			return (VXGE_HAL_CARD_TITAN_1);
+		else if (hldev->revision == VXGE_PCI_REVISION_TITAN_1A)
+			return (VXGE_HAL_CARD_TITAN_1A);
+		else
+			break;
+
+	case VXGE_PCI_DEVICE_ID_TITAN_2:
+		if (hldev->revision == VXGE_PCI_REVISION_TITAN_2)
+			return (VXGE_HAL_CARD_TITAN_2);
+		else
+			break;
+	default:
+		break;
+	}
+
+	return (VXGE_HAL_CARD_UNKNOWN);
+}
+
+/*
+ * vxge_hal_device_revision_get - Get Device revision number.
+ * @devh: HAL device handle.
+ *
+ * Returns: Device revision	number
+ */
+static	inline
+/* LINTED */
+u32 vxge_hal_device_revision_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->revision);
+}
+
+/*
+ * vxge_hal_device_pciconfig_get - Read the content of given address
+ *			 in pci config space.
+ * @devh: Device handle.
+ * @offset: Configuration address(offset)to read from
+ * @length: Length of the data (1, 2 or 4 bytes)
+ * @val: Pointer to a buffer to return the content of the address
+ *
+ * Read from the pci config space.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_pciconfig_get(
+    vxge_hal_device_h devh,
+    u32 offset,
+    u32 length,
+    void *val);
+
+/*
+ * vxge_hal_device_bar0_get - Get BAR0 mapped address.
+ * @devh: HAL device handle.
+ *
+ * Returns: BAR0 address of the	specified device.
+ */
+static	inline
+/* LINTED */
+u8 *vxge_hal_device_bar0_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->bar0);
+}
+
+/*
+ * vxge_hal_device_bar1_get - Get BAR1 mapped address.
+ * @devh: HAL device handle.
+ *
+ * Returns: BAR1 address of	the	specified device.
+ */
+static	inline
+/* LINTED */
+u8 *vxge_hal_device_bar1_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->bar1);
+}
+
+/*
+ * vxge_hal_device_bar2_get - Get BAR2 mapped address.
+ * @devh: HAL device handle.
+ *
+ * Returns: BAR2 address of the	specified device.
+ */
+static	inline
+/* LINTED */
+u8 *vxge_hal_device_bar2_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->bar2);
+}
+
+/*
+ * vxge_hal_device_bar0_set - Set BAR0 mapped address.
+ * @devh: HAL device handle.
+ * @bar0: BAR0 mapped address.
+ * * Set BAR0 address in the HAL device	object.
+ */
+static	inline
+/* LINTED */
+void
+vxge_hal_device_bar0_set(
+    vxge_hal_device_h devh,
+    u8 *bar0)
+{
+	((vxge_hal_device_t *) devh)->bar0 = bar0;
+}
+
+/*
+ * vxge_hal_device_bar1_set - Set BAR1 mapped address.
+ * @devh: HAL device handle.
+ * @bar1: BAR1 mapped address.
+ *
+ * Set BAR1 address in	the HAL Device Object.
+ */
+static	inline
+/* LINTED */
+void
+vxge_hal_device_bar1_set(
+    vxge_hal_device_h devh,
+    u8 *bar1)
+{
+	((vxge_hal_device_t *) devh)->bar1 = bar1;
+}
+
+/*
+ * vxge_hal_device_bar2_set - Set BAR2 mapped address.
+ * @devh: HAL device handle.
+ * @bar2: BAR2 mapped address.
+ *
+ * Set BAR2 address in	the HAL Device Object.
+ */
+static	inline
+/* LINTED */
+void
+vxge_hal_device_bar2_set(
+    vxge_hal_device_h devh,
+    u8 *bar2)
+{
+	((vxge_hal_device_t *) devh)->bar2 = bar2;
+}
+
+/*
+ * vxge_hal_device_enable - Enable device.
+ * @devh: HAL device handle.
+ *
+ * Enable the specified device: bring up the link/interface.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_enable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_disable - Disable X3100 adapter.
+ * @devh: HAL device handle.
+ *
+ * Disable this device. To gracefully reset the adapter, the host should:
+ *
+ *	- call vxge_hal_device_disable();
+ *
+ *	- call vxge_hal_device_intr_disable();
+ *
+ *	- do some work (error recovery, change mtu, reset, etc);
+ *
+ *	- call vxge_hal_device_enable();
+ *
+ *	- call vxge_hal_device_intr_enable().
+ *
+ * Note: Disabling the device does _not_ include disabling of interrupts.
+ * After disabling the device stops receiving new frames but those frames
+ * that were already in the pipe will keep coming for some few milliseconds.
+ *
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_disable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_pci_info_get - Get PCI bus informations such as width,
+ *			frequency, and mode from previously stored values.
+ * @devh:		HAL device handle.
+ * @signalling_rate:	pointer to a variable of enumerated type
+ *			vxge_hal_pci_e_signalling_rate_e {}.
+ * @link_width:		pointer to a variable of enumerated type
+ *			vxge_hal_pci_e_link_width_e {}.
+ *
+ * Get pci-e signalling rate and link width.
+ *
+ * Returns: one of the vxge_hal_status_e {} enumerated types.
+ * VXGE_HAL_OK			- for success.
+ * VXGE_HAL_ERR_INVALID_DEVICE	- for invalid device handle.
+ */
+static inline
+/* LINTED */
+vxge_hal_status_e vxge_hal_device_pci_info_get(
+    vxge_hal_device_h devh,
+    vxge_hal_pci_e_signalling_rate_e *signalling_rate,
+    vxge_hal_pci_e_link_width_e *link_width)
+{
+	vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
+
+	if (!hldev || !hldev->is_initialized ||
+	    (hldev->magic != VXGE_HAL_DEVICE_MAGIC)) {
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+	*signalling_rate = hldev->signalling_rate;
+	*link_width = hldev->link_width;
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_link_state_test - Test the link state.
+ * @devh: HAL device handle.
+ *
+ * Test link state.
+ * Returns: link state.
+ */
+vxge_hal_device_link_state_e
+vxge_hal_device_link_state_test(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_link_state_get - Get link state.
+ * @devh: HAL device handle.
+ *
+ * Get link state.
+ * Returns: link state.
+ */
+static inline
+/* LINTED */
+vxge_hal_device_link_state_e vxge_hal_device_link_state_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->link_state);
+}
+
+/*
+ * vxge_hal_device_link_state_poll - Poll for the link state.
+ * @devh: HAL device handle.
+ *
+ * Get link state.
+ * Returns: link state.
+ */
+vxge_hal_device_link_state_e
+vxge_hal_device_link_state_poll(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_data_rate_get - Get data rate.
+ * @devh: HAL device handle.
+ *
+ * Get data rate.
+ * Returns: data rate(1G or 10G).
+ */
+static inline
+/* LINTED */
+vxge_hal_device_data_rate_e vxge_hal_device_data_rate_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->data_rate);
+}
+
+/*
+ * vxge_hal_device_data_rate_poll - Poll for the data rate.
+ * @devh: HAL device handle.
+ *
+ * Get data rate.
+ * Returns: data rate.
+ */
+vxge_hal_device_data_rate_e
+vxge_hal_device_data_rate_poll(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_lag_mode_get - Get Current LAG Mode
+ * @devh: HAL device handle.
+ *
+ * Get Current LAG Mode
+ */
+vxge_hal_device_lag_mode_e
+vxge_hal_device_lag_mode_get(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_reset - Reset device.
+ * @devh: HAL device handle.
+ *
+ * Soft-reset the device, reset the device stats except reset_cnt.
+ *
+ * After reset is done, will try to re-initialize HW.
+ *
+ * Returns:  VXGE_HAL_PENDING - successfully sent reset to device.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_reset(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_reset_poll - Poll the device for reset complete.
+ * @devh: HAL device handle.
+ *
+ * Poll the device for reset complete
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_reset_poll(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_mrpcim_reset_poll - Poll the device for mrpcim reset
+ *			 complete.
+ * @devh: HAL device handle.
+ *
+ * Poll the device for mrpcim reset complete
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ * VXGE_HAL_ERR_MANAGER_NOT_FOUND - MRPCIM/SRPCIM manager not found
+ * VXGE_HAL_ERR_TIME_OUT - Device Reset timed out
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_mrpcim_reset_poll(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_terminating - Mark the device as 'terminating'.
+ * @devh: HAL device handle.
+ *
+ * Mark the device as 'terminating', going to terminate. Can be used
+ * to serialize termination with other running processes/contexts.
+ *
+ * See also: vxge_hal_device_terminate().
+ */
+static inline void
+/* LINTED */
+vxge_hal_device_terminating(vxge_hal_device_h devh)
+{
+	((vxge_hal_device_t *) devh)->terminating = 1;
+}
+
+/*
+ * vxge_hal_device_terminate - Terminate X3100 device.
+ * @devh: HAL device handle.
+ *
+ * Terminate HAL device.
+ *
+ * See also: vxge_hal_device_initialize().
+ */
+void
+vxge_hal_device_terminate(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_private_set - Set ULD context.
+ * @devh: HAL device handle.
+ * @data: pointer to ULD context
+ *
+ * Use HAL device to set upper-layer driver (ULD) context.
+ *
+ * See also: vxge_hal_device_private_get()
+ */
+static inline
+/* LINTED */
+void vxge_hal_device_private_set(
+    vxge_hal_device_h devh,
+    void *data)
+{
+	((vxge_hal_device_t *) devh)->upper_layer_data = data;
+}
+
+/*
+ * vxge_hal_device_private_get - Get ULD context.
+ * @devh: HAL device handle.
+ *
+ * Use HAL device to set upper-layer driver (ULD) context.
+ *
+ * See also: vxge_hal_device_private_get()
+ */
+static inline
+/* LINTED */
+void *vxge_hal_device_private_get(
+    vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->upper_layer_data);
+}
+
+/*
+ * vxge_hal_device_status - Check whether X3100 hardware is ready for
+ * operation.
+ * @devh: HAL device handle.
+ * @hw_status: X3100 status register. Returned by HAL.
+ *
+ * Check whether X3100 hardware is ready for operation.
+ * The checking includes TDMA, RDMA, PFC, PIC, MC_DRAM, and the rest
+ * hardware functional blocks.
+ *
+ * Returns: VXGE_HAL_OK if the device is ready for operation. Otherwise
+ * returns VXGE_HAL_FAIL. Also, fills in  adapter status (in @hw_status).
+ *
+ * See also: vxge_hal_status_e {}.
+ * Usage: See ex_open {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_status(vxge_hal_device_h devh, u64 *hw_status);
+
+/*
+ * vxge_hal_device_is_slot_freeze
+ * @devh: the device
+ *
+ * Returns non-zero if the slot is freezed.
+ * The determination is made based on the adapter_status
+ * register which will never give all FFs, unless PCI read
+ * cannot go through.
+ */
+int
+vxge_hal_device_is_slot_freeze(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_is_traffic_interrupt
+ * @reason: The reason returned by the vxge)hal_device_begin_irq
+ * @vp_id: Id of vpath for which to check the interrupt
+ *
+ * Returns non-zero if traffic interrupt raised, 0 otherwise
+ */
+static inline u64
+/* LINTED */
+vxge_hal_device_is_traffic_interrupt(u64 reason, u32 vp_id)
+{
+	return (reason & mBIT(vp_id + 3));
+}
+
+/*
+ * vxge_hal_device_intr_enable - Enable X3100 interrupts.
+ * @devh: HAL device handle.
+ * @op: One of the vxge_hal_device_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to enable.
+ *
+ * Enable X3100 interrupts. The function is to be executed the last in
+ * X3100 initialization sequence.
+ *
+ * See also: vxge_hal_device_intr_disable()
+ */
+void
+vxge_hal_device_intr_enable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_intr_disable - Disable X3100 interrupts.
+ * @devh: HAL device handle.
+ * @op: One of the vxge_hal_device_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to disable.
+ *
+ * Disable X3100 interrupts.
+ *
+ * See also: vxge_hal_device_intr_enable()
+ */
+void
+vxge_hal_device_intr_disable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_mask_all - Mask all device interrupts.
+ * @devh: HAL device handle.
+ *
+ * Mask	all	device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_all()
+ */
+void
+vxge_hal_device_mask_all(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_unmask_all - Unmask all device interrupts.
+ * @devh: HAL device handle.
+ *
+ * Unmask all device interrupts.
+ *
+ * See also: vxge_hal_device_mask_all()
+ */
+void
+vxge_hal_device_unmask_all(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_begin_irq - Begin IRQ processing.
+ * @devh: HAL device handle.
+ * @skip_alarms: Do not clear the alarms
+ * @reason: "Reason" for the interrupt,	the value of X3100's
+ *			general_int_status register.
+ *
+ * The function	performs two actions, It first checks whether (shared IRQ) the
+ * interrupt was raised	by the device. Next, it	masks the device interrupts.
+ *
+ * Note:
+ * vxge_hal_device_begin_irq() does not flush MMIO writes through the
+ * bridge. Therefore, two back-to-back interrupts are potentially possible.
+ * It is the responsibility	of the ULD to make sure	that only one
+ * vxge_hal_device_continue_irq() runs at a time.
+ *
+ * Returns: 0, if the interrupt	is not "ours" (note that in this case the
+ * device remain enabled).
+ * Otherwise, vxge_hal_device_begin_irq() returns 64bit general adapter
+ * status.
+ * See also: vxge_hal_device_handle_irq()
+ */
+vxge_hal_status_e
+vxge_hal_device_begin_irq(
+    vxge_hal_device_h devh,
+    u32 skip_alarms,
+    u64 *reason);
+
+/*
+ * vxge_hal_device_continue_irq - Continue handling IRQ:	process	all
+ *				completed descriptors.
+ * @devh: HAL device handle.
+ *
+ * Process completed descriptors and unmask the	device interrupts.
+ *
+ * The vxge_hal_device_continue_irq() walks all open virtual paths
+ * and calls upper-layer driver	(ULD) via supplied completion
+ * callback.
+ *
+ * Note	that the vxge_hal_device_continue_irq is	part of	the _fast_ path.
+ * To optimize the processing, the function does _not_ check for
+ * errors and alarms.
+ *
+ * Returns: VXGE_HAL_OK.
+ *
+ * See also: vxge_hal_device_handle_irq(),
+ * vxge_hal_ring_rxd_next_completed(),
+ * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {},
+ * vxge_hal_fifo_callback_f {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_continue_irq(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_handle_irq - Handle device IRQ.
+ * @devh: HAL device handle.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Perform the complete	handling of the	line interrupt.	The function
+ * performs two	calls.
+ * First it uses vxge_hal_device_begin_irq() to check the reason for
+ * the interrupt and mask the device interrupts.
+ * Second, it calls vxge_hal_device_continue_irq() to process all
+ * completed descriptors and re-enable the interrupts.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_WRONG_IRQ - (shared)	IRQ	produced by	other device.
+ *
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq().
+ */
+vxge_hal_status_e
+vxge_hal_device_handle_irq(
+    vxge_hal_device_h devh,
+    u32 skip_alarms);
+
+/*
+ * vxge_hal_device_mask_tx - Mask Tx interrupts.
+ * @devh: HAL device.
+ *
+ * Mask	Tx device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_tx(), vxge_hal_device_mask_rx(),
+ * vxge_hal_device_clear_tx().
+ */
+void
+vxge_hal_device_mask_tx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_clear_tx - Acknowledge (that is, clear) the
+ * condition that has caused the TX	interrupt.
+ * @devh: HAL device.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Tx interrupt.
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(),
+ * vxge_hal_device_clear_rx(), vxge_hal_device_mask_tx().
+ */
+void
+vxge_hal_device_clear_tx(
+    vxge_hal_device_h devh);
+
+
+/*
+ * vxge_hal_device_unmask_tx - Unmask Tx	interrupts.
+ * @devh: HAL device.
+ *
+ * Unmask Tx device interrupts.
+ *
+ * See also: vxge_hal_device_mask_tx(), vxge_hal_device_clear_tx().
+ */
+void
+vxge_hal_device_unmask_tx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_mask_rx - Mask Rx	interrupts.
+ * @devh: HAL device.
+ *
+ * Mask	Rx device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_rx(), vxge_hal_device_mask_tx(),
+ * vxge_hal_device_clear_rx().
+ */
+void
+vxge_hal_device_mask_rx(
+    vxge_hal_device_h devh);
+
+
+/*
+ * vxge_hal_device_clear_rx - Acknowledge (that is, clear) the
+ * condition that has caused the RX	interrupt.
+ * @devh: HAL device.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Rx interrupt.
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(),
+ * vxge_hal_device_clear_tx(), vxge_hal_device_mask_rx().
+ */
+void
+vxge_hal_device_clear_rx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_unmask_rx - Unmask Rx	interrupts.
+ * @devh: HAL device.
+ *
+ * Unmask Rx device interrupts.
+ *
+ * See also: vxge_hal_device_mask_rx(), vxge_hal_device_clear_rx().
+ */
+void
+vxge_hal_device_unmask_rx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_mask_tx_rx - Mask Tx and Rx interrupts.
+ * @devh: HAL device.
+ *
+ * Mask Tx and Rx device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_tx_rx(), vxge_hal_device_clear_tx_rx().
+ */
+void
+vxge_hal_device_mask_tx_rx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_clear_tx_rx - Acknowledge (that is, clear) the
+ * condition that has caused the Tx and RX interrupt.
+ * @devh: HAL device.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Tx and Rx interrupt.
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(),
+ * vxge_hal_device_mask_tx_rx(), vxge_hal_device_unmask_tx_rx().
+ */
+void
+vxge_hal_device_clear_tx_rx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_unmask_tx_rx - Unmask Tx and Rx interrupts.
+ * @devh: HAL device.
+ *
+ * Unmask Tx and Rx device interrupts.
+ *
+ * See also: vxge_hal_device_mask_tx_rx(), vxge_hal_device_clear_tx_rx().
+ */
+void
+vxge_hal_device_unmask_tx_rx(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_msix_mode - Is MSIX enabled?
+ * @devh: HAL device handle.
+ *
+ * Returns 0 if MSIX is enabled for the specified device,
+ * non-zero otherwise.
+ */
+static inline int
+/* LINTED */
+vxge_hal_device_msix_mode(vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->msix_enabled);
+}
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+
+/*
+ * vxge_hal_device_trace_write - Write the trace from the given buffer into
+ *				 circular trace buffer
+ * @devh: HAL device handle.
+ * @trace_buf: Buffer containing the trace.
+ * @trace_len: Length of the trace in the buffer
+ *
+ * Writes the trace from the given buffer into the circular trace buffer
+ *
+ */
+void
+vxge_hal_device_trace_write(vxge_hal_device_h devh,
+    u8 *trace_buf,
+    u32 trace_len);
+
+/*
+ * vxge_hal_device_trace_dump - Dump the trace buffer.
+ * @devh: HAL device handle.
+ *
+ * Dump the trace buffer contents.
+ */
+void
+	vxge_hal_device_trace_dump(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_trace_read - Read trace buffer contents.
+ * @devh: HAL device handle.
+ * @buffer: Buffer to store the trace buffer contents.
+ * @buf_size: Size of the buffer.
+ * @read_length: Size of the valid data in the buffer.
+ *
+ * Read  HAL trace buffer contents starting from the offset
+ * upto the size of the buffer or till EOF is reached.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_trace_read(vxge_hal_device_h devh,
+    char *buffer,
+    unsigned buf_size,
+    unsigned *read_length);
+
+#endif
+
+/*
+ * vxge_hal_device_debug_set - Set the debug module, level and timestamp
+ * @devh: Hal device object
+ * @level: Debug level as defined in enum vxge_debug_level_e
+ * @mask: An or value of component masks as defined in vxge_debug.h
+ *
+ * This routine is used to dynamically change the debug output
+ */
+void
+vxge_hal_device_debug_set(
+    vxge_hal_device_h devh,
+    vxge_debug_level_e level,
+    u32 mask);
+
+/*
+ * vxge_hal_device_debug_level_get - Get the debug level
+ * @devh: Hal device object
+ *
+ * This routine returns the current debug level set
+ */
+static inline u32
+/* LINTED */
+vxge_hal_device_debug_level_get(vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->debug_level);
+}
+
+/*
+ * vxge_hal_device_debug_mask_get - Get the debug mask
+ * @devh: Hal device object
+ *
+ * This routine returns the current debug mask set
+ */
+static inline u32
+/* LINTED */
+vxge_hal_device_debug_mask_get(vxge_hal_device_h devh)
+{
+	return (((vxge_hal_device_t *) devh)->debug_module_mask);
+}
+
+/*
+ * vxge_hal_device_flick_link_led - Flick (blink) link LED.
+ * @devh: HAL device handle.
+ * @port : Port number 0, or 1
+ * @on_off: TRUE if flickering to be on, FALSE to be off
+ *
+ * Flicker the link LED.
+ */
+vxge_hal_status_e
+vxge_hal_device_flick_link_led(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 on_off);
+
+/*
+ * vxge_hal_device_getpause_data -Pause frame frame generation and reception.
+ * @devh: HAL device handle.
+ * @port : Port number 0, 1, or 2
+ * @tx : A field to return the pause generation capability of the NIC.
+ * @rx : A field to return the pause reception capability of the NIC.
+ *
+ * Returns the Pause frame generation and reception capability of the NIC.
+ * Return value:
+ * status
+ */
+vxge_hal_status_e
+vxge_hal_device_getpause_data(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 *tx,
+    u32 *rx);
+
+/*
+ * Privileged operations
+ */
+
+/*
+ * enum vxge_hal_pcie_function_mode_e - PCIE Function modes
+ * @VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17: Single Function
+ *             - 1 function with 17 VPATHs
+ * @VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2: Multi Function
+ *             - 8 functions with 2 VPATHs per function
+ * @VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1: SRIOV
+ *             - 17 VFs with 1 VPATH per VF
+ * @VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1: MRIOV
+ *             - 17 Virtual Hierarchies, 1 Path/Function/Hierarchy
+ * @VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2: MRIOV
+ *             - 8 Virtual Hierarchies, 2 Path/Function/Hierarchy
+ * @VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1: Multi Function
+ *             - 17 functions, 1 Path/Function (PCIe ARI)
+ * @VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2: SRIOV
+ *             - 1 PF, 7 VF, 2 Paths/Function
+ * @VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4: SRIOV
+ *             - 1 PF, 3 VF, 4 Paths/Function
+ * @VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8: Multi Function
+ *             - 2 functions, 8 Paths/Function (funcs 2-7 have no resources)
+ */
+typedef enum vxge_hal_pcie_function_mode_e {
+	VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17,
+	VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2,
+	VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1,
+	VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1,
+	VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2,
+	VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1,
+	VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2,
+	VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4,
+	VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8,
+	VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4,
+	VXGE_HAL_PCIE_FUNC_MODE_MR4_VP4,
+	VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2
+
+} vxge_hal_pcie_function_mode_e;
+
+/* Behavior on failure */
+typedef enum vxge_hal_xmac_nwif_behavior_on_failure {
+	VXGE_HAL_XMAC_NWIF_OnFailure_NoMove,
+	VXGE_HAL_XMAC_NWIF_OnFailure_OtherPort,
+	VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore
+} vxge_hal_xmac_nwif_behavior_on_failure;
+
+/*
+ * Network Port configuration cmds
+ */
+typedef enum vxge_hal_nwif_cmds {
+	VXGE_HAL_XMAC_NWIF_Cmd_Version				= 0x0,
+	VXGE_HAL_XMAC_NWIF_Cmd_SetMode				= 0x1,
+	VXGE_HAL_XMAC_NWIF_Cmd_CfgSnglPort			= 0x4,
+	VXGE_HAL_XMAC_NWIF_Cmd_Avail				= 0x6,
+	VXGE_HAL_XMAC_NWIF_Cmd_CfgSetActPassPreferredPort	= 0x7,
+	VXGE_HAL_XMAC_NWIF_Cmd_CfgSetBehaviourOnFailure		= 0x8,
+	VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_L2SwitchEnable	= 0x9,
+	VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_VPathVector		= 0xa,
+	VXGE_HAL_XMAC_NWIF_Cmd_Get_Active_Config		= 0xb
+} vxge_hal_nwif_cmds;
+
+/* Network port get active config options */
+typedef enum vxge_hal_xmac_nwif_actconfig {
+	VXGE_HAL_XMAC_NWIF_ActConfig_Avail			= 0,
+	VXGE_HAL_XMAC_NWIF_ActConfig_NWPortMode			= 1,
+	VXGE_HAL_XMAC_NWIF_ActConfig_PreferredPort		= 2,
+	VXGE_HAL_XMAC_NWIF_ActConfig_BehaviourOnFail		= 3,
+	VXGE_HAL_XMAC_NWIF_ActConfig_ActivePort			= 4,
+	VXGE_HAL_XMAC_NWIF_ActConfig_L2SwitchEnabled		= 5,
+	VXGE_HAL_XMAC_NWIF_ActConfig_DualPortPath		= 6
+} vxge_hal_xmac_nwif_actconfig;
+
+/* Dual port modes */
+typedef enum vxge_hal_xmac_nwif_dp_mode {
+	VXGE_HAL_DP_NP_MODE_DEFAULT,
+	VXGE_HAL_DP_NP_MODE_LINK_AGGR,
+	VXGE_HAL_DP_NP_MODE_ACTIVE_PASSIVE,
+	VXGE_HAL_DP_NP_MODE_SINGLE_PORT,
+	VXGE_HAL_DP_NP_MODE_DUAL_PORT,
+	VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT
+} vxge_hal_xmac_nwif_dp_mode;
+
+/* L2 switch status */
+typedef enum vxge_hal_xmac_nwif_l2_switch_status {
+	VXGE_HAL_XMAC_NWIF_L2_SWITCH_DISABLE,
+	VXGE_HAL_XMAC_NWIF_L2_SWITCH_ENABLE
+} vxge_hal_xmac_nwif_l2_switch_status;
+
+/*
+ * vxge_hal_srpcim_alarm_process - Process srpcim Alarms.
+ * @devh: Device Handle.
+ * @skip_alarms: Flasg to indicate not to clear alarms
+ *
+ * Process srpcim alarms.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_alarm_process(vxge_hal_device_h devh, u32 skip_alarms);
+
+/*
+ * vxge_hal_srpcim_intr_enable - Enable srpcim interrupts.
+ * @devh: Device Handle.
+ *
+ * Enable srpcim interrupts.
+ *
+ * See also: vxge_hal_srpcim_intr_disable()
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_intr_enable(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_srpcim_intr_disable - Disable srpcim interrupts.
+ * @devh: Device Handle.
+ *
+ * Disable srpcim interrupts.
+ *
+ * See also: vxge_hal_srpcim_intr_enable()
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_intr_disable(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm
+ * @devh: Device Handle.
+ * @alarm_msix_id: MSIX vector for alarm.
+ *
+ * This API will associate a given MSIX vector numbers with srpcim alarm
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id);
+
+/*
+ * vxge_hal_srpcim_msix_mask - Mask MSIX Vector.
+ * @devh: Device Handle.
+ *
+ * The function masks the srpcim msix interrupt
+ *
+ */
+void
+vxge_hal_srpcim_msix_mask(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_srpcim_msix_clear - Clear MSIX Vector.
+ * @devh: Device Handle.
+ *
+ * The function clears the srpcim msix interrupt
+ *
+ */
+void
+vxge_hal_srpcim_msix_clear(vxge_hal_device_h devh);
+
+
+/*
+ * vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector.
+ * @devh: Device Handle.
+ *
+ * The function unmasks the srpcim msix interrupt
+ *
+ */
+void
+vxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh);
+
+vxge_hal_status_e
+vxge_hal_func_mode_count(vxge_hal_device_h devh,
+    u32 func_mode, u32 *num_funcs);
+
+vxge_hal_status_e
+vxge_hal_send_message(vxge_hal_device_h devh, u64 vp_id, u8 msg_type,
+    u8 msg_dst, u32 msg_data, u64 *msg_sent_to_vpaths);
+
+/*
+ * vxge_hal_func_mode_set - Set PCI-E function mode
+ * @devh: Device Handle.
+ * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{}
+ *
+ * Set PCI-E function mode.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_func_mode_get(vxge_hal_device_h devh, u32 *func_mode);
+/*
+ * vxge_hal_func_mode_set - Set PCI-E function mode
+ * @devh: Device Handle.
+ * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{}
+ *
+ * Set PCI-E function mode.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_pcie_func_mode_set(vxge_hal_device_h devh,
+    vxge_hal_pcie_function_mode_e func_mode);
+
+/*
+ * vxge_hal_get_active_config - Get active configuration
+ * @devh: Device Handle.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_get_active_config(vxge_hal_device_h devh,
+    vxge_hal_xmac_nwif_actconfig req_config, u64 *cur_config);
+
+/*
+ * vxge_hw_set_port_mode - Set dual port mode
+ * override the default dual port mode
+ * @devh: Device Handle.
+ *
+ */
+
+vxge_hal_status_e
+vxge_hal_set_port_mode(vxge_hal_device_h devh,
+    vxge_hal_xmac_nwif_dp_mode port_mode);
+
+/*
+ * vxge_hal_set_behavior_on_failure - Set port behaviour
+ * change port behavior on failure
+ * @devh: Device Handle.
+ */
+vxge_hal_status_e
+vxge_hal_set_behavior_on_failure(vxge_hal_device_h devh,
+    vxge_hal_xmac_nwif_behavior_on_failure behave_on_failure);
+
+
+/*
+ * vxge_hal_set_l2switch_mode - Set port behaviour
+ * set l2switch mode
+ * @devh: Device Handle.
+ */
+vxge_hal_status_e
+vxge_hal_set_l2switch_mode(vxge_hal_device_h devh,
+    enum vxge_hal_xmac_nwif_l2_switch_status l2_switch);
+/*
+ * vxge_hal_set_fw_api - Setup FW api
+ * @devh: Device Handle.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_set_fw_api(vxge_hal_device_h devh, u64 vp_id, u32 action,
+    u32 offset, u64 data0, u64 data1);
+
+vxge_hal_status_e
+vxge_hal_config_vpath_map(vxge_hal_device_h devh, u64 port_map);
+
+vxge_hal_status_e
+vxge_hal_get_vpath_mask(vxge_hal_device_h devh, u32 vf_id,
+    u32 *no_of_vpath, u64 *vpath_mask);
+
+vxge_hal_status_e
+vxge_hal_get_vpath_list(vxge_hal_device_h devh, u32 vf_id,
+    u64 *vpath_list, u32 *vpath_count);
+
+vxge_hal_status_e
+vxge_hal_rx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id);
+
+vxge_hal_status_e
+vxge_hal_tx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id);
+
+vxge_hal_status_e
+vxge_hal_bw_priority_get(vxge_hal_device_h devh, u64 vp_id,
+    u32 *bandwidth, u32 *priority);
+
+vxge_hal_status_e
+vxge_hal_vf_rx_bw_get(vxge_hal_device_h devh, u64 func_id,
+    u32 *bandwidth, u32 *priority);
+/*
+ * vxge_hal_mrpcim_serial_number_get - Returns the serial number
+ * @devh: Device Handle.
+ *
+ * Return the serial number
+ */
+const u8 *
+vxge_hal_mrpcim_serial_number_get(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_fw_upgrade - Upgrade firmware
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @bar0: Address of BAR0 in PCI config
+ * @buffer: Buffer containing F/W image
+ * @length: F/W image length
+ *
+ * Upgrade firmware
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_fw_upgrade(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u8 *bar0,
+    u8 *buffer,
+    u32 length);
+
+/*
+ * vxge_hal_mrpcim_vpath_map_get - Returns the assigned vpaths map
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @bar0: Address of BAR0 in PCI config
+ * @func: Function Number
+ *
+ * Returns the assigned vpaths map
+ */
+u64
+vxge_hal_mrpcim_vpath_map_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u8 *bar0,
+    u32 func);
+
+/*
+ * vxge_hal_mrpcim_vpath_qos_set - Set the priority, Guaranteed and maximum
+ *				 bandwidth for a vpath.
+ * @devh: HAL device handle.
+ * @vp_id: Vpath Id.
+ * @priority: Priority
+ * @min_bandwidth: Minimum Bandwidth
+ * @max_bandwidth: Maximum Bandwidth
+ *
+ * Set the Priority, Guaranteed and maximum bandwidth for a given vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_vpath_qos_set(
+    vxge_hal_device_h devh,
+    u32 vp_id,
+    u32 priority,
+    u32 min_bandwidth,
+    u32 max_bandwidth);
+
+/*
+ * vxge_hal_mrpcim_vpath_qos_get - Get the priority, Guaranteed and maximum
+ *				 bandwidth for a vpath.
+ * @devh: HAL device handle.
+ * @vp_id: Vpath Id.
+ * @priority: Buffer to return Priority
+ * @min_bandwidth: Buffer to return Minimum Bandwidth
+ * @max_bandwidth: Buffer to return Maximum Bandwidth
+ *
+ * Get the Priority, Guaranteed and maximum bandwidth for a given vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_vpath_qos_get(
+    vxge_hal_device_h devh,
+    u32 vp_id,
+    u32 *priority,
+    u32 *min_bandwidth,
+    u32 *max_bandwidth);
+
+/*
+ * vxge_hal_mrpcim_mac_addr_add - Add the mac address entry
+ *		    into MAC address table.
+ * @devh: Device handle.
+ * @offset: Index into the DA table to add the mac address.
+ * @macaddr: MAC address to be added for this vpath into the list
+ * @macaddr_mask: MAC address mask for macaddr
+ * @vpath_vector: Bit mask specifying the vpaths to which the mac address
+ *		applies
+ * @duplicate_mode: Duplicate MAC address add mode. Please see
+ *		vxge_hal_vpath_mac_addr_add_mode_e {}
+ *
+ * Adds the given mac address, mac address mask and vpath vector into the list
+ *
+ * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and
+ * vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_mac_addr_add(
+    vxge_hal_device_h devh,
+    u32 offset,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask,
+    u64 vpath_vector,
+    u32 duplicate_mode);
+
+/*
+ * vxge_hal_mrpcim_mac_addr_get - Read the mac address entry
+ *				 into MAC address table.
+ * @devh: Device handle.
+ * @offset: Index into the DA table to execute the command on.
+ * @macaddr: Buffer to return MAC address to be added for this vpath
+ * @macaddr_mask: Buffer to return MAC address mask for macaddr
+ * @vpath_vector: Buffer to return Bit mask specifying the vpaths to which
+ *		the mac address applies
+ *
+ * Reads the mac address,mac address mask and vpath vector from the given offset
+ *
+ * see also: vxge_hal_mrpcim_mac_addr_add
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_mac_addr_get(
+    vxge_hal_device_h devh,
+    u32 offset,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask,
+    u64 *vpath_vector);
+
+/*
+ * vxge_hal_mrpcim_reset - Reset the entire device.
+ * @devh: HAL device handle.
+ *
+ * Soft-reset the device, reset the device stats except reset_cnt.
+ *
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_reset(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_reset_poll - Poll the device for reset complete.
+ * @devh: HAL device handle.
+ *
+ * Soft-reset the device, reset the device stats except reset_cnt.
+ *
+ * After reset is done, will try to re-initialize HW.
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_reset_poll(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_strip_repl_vlan_tag_enable - Enable strip Repl vlan tag.
+ * @devh: Device handle.
+ *
+ * Enable X3100 strip Repl vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_strip_repl_vlan_tag_enable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_strip_repl_vlan_tag_disable - Disable strip Repl vlan tag.
+ * @devh: Device handle.
+ *
+ * Disable X3100 strip Repl vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_strip_repl_vlan_tag_disable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_intr_enable - Enable the interrupts on mrpcim.
+ * @devh: HAL device handle.
+ *
+ * Enable mrpcim interrupts
+ *
+ * See also: vxge_hal_mrpcim_intr_disable().
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_intr_enable(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_intr_disable - Disable the interrupts on mrpcim.
+ * @devh: HAL device handle.
+ *
+ * Disable mrpcim interrupts
+ *
+ * See also: vxge_hal_mrpcim_intr_enable().
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_intr_disable(vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_lag_config_get - Get the LAG config.
+ * @devh: Device handle.
+ * @lconfig: LAG Configuration
+ *
+ * Returns the current LAG configuration.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_lag_config_get(
+    vxge_hal_device_h devh,
+    vxge_hal_lag_config_t *lconfig);
+
+/*
+ * vxge_hal_mrpcim_lag_config_set - Set the LAG config.
+ * @devh: Device handle.
+ * @lconfig: LAG Configuration
+ *
+ * Sets the LAG configuration.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_lag_config_set(
+    vxge_hal_device_h devh,
+    vxge_hal_lag_config_t *lconfig);
+
+/*
+ * vxge_hal_mrpcim_getpause_data -Pause frame frame generation and reception.
+ * @devh: HAL device handle.
+ * @port : Port number 0, 1, or 2
+ * @tx : A field to return the pause generation capability of the NIC.
+ * @rx : A field to return the pause reception capability of the NIC.
+ *
+ * Returns the Pause frame generation and reception capability of the NIC.
+ * Return value:
+ * status
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_getpause_data(vxge_hal_device_h devh,
+    u32 port,
+    u32 *tx,
+    u32 *rx);
+
+/*
+ * vxge_hal_mrpcim_setpause_data -  set/reset pause frame generation.
+ * @devh: HAL device handle.
+ * @port : Port number 0, 1, or 2
+ * @tx: A field that indicates the pause generation capability to be
+ * set on the NIC.
+ * @rx: A field that indicates the pause reception capability to be
+ * set on the NIC.
+ *
+ * It can be used to set or reset Pause frame generation or reception
+ * support of the NIC.
+ * Return value:
+ * int, returns 0 on Success
+ */
+
+vxge_hal_status_e
+vxge_hal_mrpcim_setpause_data(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 tx,
+    u32 rx);
+
+/*
+ * vxge_hal_mrpcim_bist_test - invokes the MemBist test of the card .
+ * @devh: HAL device handle.
+ * @data:variable that returns the result of each of the test conducted by
+ * the driver.
+ *
+ * This invokes the MemBist test of the card. We give around
+ * 2 secs time for the Test to complete. If it's still not complete
+ * within this peiod, we consider that the test failed.
+ * Return value:
+ * 0 on success and -1 on failure.
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_bist_test(vxge_hal_device_h devh, u64 *data);
+
+/*
+ * vxge_hal_mrpcim_udp_rth_enable - Enable UDP/RTH.
+ * @devh: HAL device handle.
+ *
+ * enable udp rth
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_udp_rth_enable(
+    vxge_hal_device_h devh);
+
+/*
+ * Virtual Paths
+ */
+
+/*
+ * struct vxge_hal_vpath_attr_t - Attributes of virtual path
+ * @vp_id: Identifier of Virtual Path
+ * @ring_attr: Attributes of ring for non-offload receive
+ * @fifo_attr: Attributes of fifo for non-offload transmit
+ *
+ * Attributes of virtual path.  This structure is passed as parameter
+ * to the vxge_hal_vpath_open() routine to set the attributes of DMQ, UMQ,
+ * ring and fifo. After virtual path is open, iWARP/RDMA module can attach
+ * to virtual path.
+ */
+typedef struct vxge_hal_vpath_attr_t {
+	u32				vp_id;
+	vxge_hal_ring_attr_t		ring_attr;
+	vxge_hal_fifo_attr_t		fifo_attr;
+} vxge_hal_vpath_attr_t;
+
+/*
+ * vxge_hal_vpath_open - Open a virtual path on a given adapter
+ * @devh: handle to device object
+ * @attr: Virtual path attributes
+ * @cb_fn: Call back to be called to complete an asynchronous function call
+ * @client_handle: handle to be returned in the callback
+ * @vpath_handle: Buffer to return a handle to the vpath
+ *
+ * This function is used to open access to virtual path of an
+ * adapter for offload, LRO and SPDM operations. This function returns
+ * synchronously.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_open(
+    vxge_hal_device_h devh,
+    vxge_hal_vpath_attr_t *attr,
+    vxge_hal_vpath_callback_f cb_fn,
+    vxge_hal_client_h client_handle,
+    vxge_hal_vpath_h *vpath_handle);
+
+/*
+ * vxge_hal_vpath_enable
+ * @vpath_handle: Handle to the vpath object
+ *
+ * This routine clears the vpath reset and puts vpath in service
+ */
+vxge_hal_status_e
+vxge_hal_vpath_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_id - Get virtual path ID
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function returns virtual path id
+ */
+u32
+vxge_hal_vpath_id(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_close - Close the handle got from previous vpath (vpath) open
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function is used to close access to virtual path opened
+ * earlier. This function returns synchronously.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_close(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_reset - Resets vpath
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function is used to request a reset of vpath
+ */
+vxge_hal_status_e
+vxge_hal_vpath_reset(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_reset_poll - Poll for reset complete
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function is used to poll for the vpath reset completion
+ */
+vxge_hal_status_e
+vxge_hal_vpath_reset_poll(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_obj_count_get - Get the Object usage count for a given
+ *		 virtual path
+ * @vpath_handle: Virtal path handle
+ * @obj_counts: Buffer to return object counts
+ *
+ * This function returns the object counts for virtual path. This function
+ * returns synchronously.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_obj_count_get(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_sw_obj_count_t *obj_counts);
+
+/*
+ * vxge_hal_vpath_mtu_check - check MTU value for ranges
+ * @vpath_handle: Virtal path handle
+ * @new_mtu: new MTU value to check
+ *
+ * Will do sanity check for new MTU value.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
+ *
+ * See also: vxge_hal_vpath_mtu_set()
+ */
+vxge_hal_status_e
+vxge_hal_device_mtu_check(vxge_hal_vpath_h vpath_handle,
+    unsigned long new_mtu);
+
+/*
+ * vxge_hal_vpath_mtu_set - Set MTU.
+ * @vpath_handle: Virtal path handle
+ * @new_mtu: New MTU size to configure.
+ *
+ * Set new MTU value. Example, to use jumbo frames:
+ * vxge_hal_vpath_mtu_set(my_device, 9600);
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mtu_set(vxge_hal_vpath_h vpath_handle,
+    unsigned long new_mtu);
+
+typedef enum vxge_hal_vpath_mac_addr_add_mode_e {
+	VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE = 0,
+	VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE = 1,
+	VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE = 2
+} vxge_hal_vpath_mac_addr_add_mode_e;
+
+/*
+ * vxge_hal_vpath_mac_addr_add - Add the mac address entry for this vpath
+ *		  to MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: MAC address to be added for this vpath into the list
+ * @macaddr_mask: MAC address mask for mac_addr
+ * @duplicate_mode: Duplicate MAC address add mode. Please see
+ *		vxge_hal_vpath_mac_addr_add_mode_e {}
+ *
+ * Adds the given mac address and mac address mask into the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and
+ * vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_add(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask,
+    vxge_hal_vpath_mac_addr_add_mode_e duplicate_mode);
+
+/*
+ * vxge_hal_vpath_mac_addr_get - Get the first mac address entry for this vpath
+ *		  from MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: First MAC address entry for this vpath in the list
+ * @macaddr_mask: MAC address mask for mac_addr
+ *
+ * Returns the first mac address and mac address mask in the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_get(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask);
+
+/*
+ * vxge_hal_vpath_mac_addr_get_next - Get the next mac address entry for this
+ *		   vpath from MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: Next MAC address entry for this vpath in the list
+ * @macaddr_mask: MAC address mask for mac_addr
+ *
+ * Returns the next mac address and mac address mask in the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask);
+
+/*
+ * vxge_hal_vpath_mac_addr_delete - Delete the mac address entry for this vpath
+ *		  to MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: MAC address to be added for this vpath into the list
+ * @macaddr_mask: MAC address mask for macaddr
+ *
+ * Delete the given mac address and mac address mask into the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_add, vxge_hal_vpath_mac_addr_get and
+ * vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_delete(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask);
+
+/*
+ * vxge_hal_vpath_vid_add - Add the vlan id entry for this vpath
+ *		  to vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: vlan id to be added for this vpath into the list
+ *
+ * Adds the given vlan id into the list for this  vpath.
+ * see also: vxge_hal_vpath_vid_delete, vxge_hal_vpath_vid_get and
+ * vxge_hal_vpath_vid_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_add(
+    vxge_hal_vpath_h vpath_handle,
+    u64 vid);
+
+/*
+ * vxge_hal_vpath_vid_get - Get the first vid entry for this vpath
+ *		  from vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: Buffer to return vlan id
+ *
+ * Returns the first vlan id in the list for this vpath.
+ * see also: vxge_hal_vpath_vid_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_get(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *vid);
+
+/*
+ * vxge_hal_vpath_vid_get_next - Get the next vid entry for this vpath
+ *		  from vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: Buffer to return vlan id
+ *
+ * Returns the next vlan id in the list for this vpath.
+ * see also: vxge_hal_vpath_vid_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *vid);
+
+/*
+ * vxge_hal_vpath_vid_delete - Delete the vlan id entry for this vpath
+ *		  to vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: vlan id to be added for this vpath into the list
+ *
+ * Adds the given vlan id into the list for this  vpath.
+ * see also: vxge_hal_vpath_vid_add, vxge_hal_vpath_vid_get and
+ * vxge_hal_vpath_vid_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_delete(
+    vxge_hal_vpath_h vpath_handle,
+    u64 vid);
+
+/*
+ * vxge_hal_vpath_etype_add - Add the Ethertype entry for this vpath
+ *		  to Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: ethertype to be added for this vpath into the list
+ *
+ * Adds the given Ethertype into the list for this  vpath.
+ * see also: vxge_hal_vpath_etype_delete, vxge_hal_vpath_etype_get and
+ * vxge_hal_vpath_etype_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_add(
+    vxge_hal_vpath_h vpath_handle,
+    u64 etype);
+
+/*
+ * vxge_hal_vpath_etype_get - Get the first ethertype entry for this vpath
+ *		  from Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: Buffer to return Ethertype
+ *
+ * Returns the first ethype entry in the list for this vpath.
+ * see also: vxge_hal_vpath_etype_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_get(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *etype);
+
+/*
+ * vxge_hal_vpath_etype_get_next - Get the next Ethertype entry for this vpath
+ *		  from Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: Buffer to return Ethwrtype
+ *
+ * Returns the next Ethwrtype in the list for this vpath.
+ * see also: vxge_hal_vpath_etype_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *etype);
+
+/*
+ * vxge_hal_vpath_etype_delete - Delete the Ethertype entry for this vpath
+ *		  to Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: ethertype to be added for this vpath into the list
+ *
+ * Adds the given Ethertype into the list for this  vpath.
+ * see also: vxge_hal_vpath_etype_add, vxge_hal_vpath_etype_get and
+ * vxge_hal_vpath_etype_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_delete(
+    vxge_hal_vpath_h vpath_handle,
+    u64 etype);
+
+/*
+ * vxge_hal_vpath_port_add - Add the port entry for this vpath
+ *		  to port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: if 0 - Src port or 1 - Dest port
+ * @protocol: if 0 - TCP or 1 - UDP
+ * @port: port to be added for this vpath into the list
+ *
+ * Adds the given port into the list for this  vpath.
+ * see also: vxge_hal_vpath_port_delete, vxge_hal_vpath_port_get and
+ * vxge_hal_vpath_port_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_add(
+    vxge_hal_vpath_h vpath_handle,
+    u32 port_type,
+    u32 protocol,
+    u32 port);
+
+/*
+ * vxge_hal_vpath_port_get - Get the first port number entry for this vpath
+ *		  from port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: Buffer to return if 0 - Src port or 1 - Dest port
+ * @protocol: Buffer to return if 0 - TCP or 1 - UDP
+ * @port: Buffer to return port number
+ *
+ * Returns the first port number entry in the list for this vpath.
+ * see also: vxge_hal_vpath_port_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_get(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *port_type,
+    u32 *protocol,
+    u32 *port);
+
+/*
+ * vxge_hal_vpath_port_get_next - Get the next port number entry for this vpath
+ *		  from port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: Buffer to return if 0 - Src port or 1 - Dest port
+ * @protocol: Buffer to return if 0 - TCP or 1 - UDP
+ * @port: Buffer to return port number
+ *
+ * Returns the next port number entry in the list for this vpath.
+ * see also: vxge_hal_vpath_port_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *port_type,
+    u32 *protocol,
+    u32 *port);
+
+/*
+ * vxge_hal_vpath_port_delete - Delete the port entry for this vpath
+ *		  to port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: if 0 - Src port or 1 - Dest port
+ * @protocol: if 0 - TCP or 1 - UDP
+ * @port: port to be added for this vpath into the list
+ *
+ * Adds the given port into the list for this  vpath.
+ * see also: vxge_hal_vpath_port_add, vxge_hal_vpath_port_get and
+ * vxge_hal_vpath_port_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_delete(
+    vxge_hal_vpath_h vpath_handle,
+    u32 port_type,
+    u32 protocol,
+    u32 port);
+
+typedef enum vxge_hal_rth_algoritms_t {
+	RTH_ALG_NONE	= -1,
+	RTH_ALG_JENKINS = 0,
+	RTH_ALG_MS_RSS	= 1,
+	RTH_ALG_CRC32C	= 2
+} vxge_hal_rth_algoritms_t;
+
+/*
+ * struct vxge_hal_rth_hash_types_t - RTH hash types.
+ * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4
+ * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4
+ * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6
+ * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6
+ * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex
+ * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex
+ *
+ * Used to pass RTH hash types to rts_rts_set.
+ *
+ * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_get().
+ */
+typedef struct vxge_hal_rth_hash_types_t {
+	u8 hash_type_tcpipv4_en;
+	u8 hash_type_ipv4_en;
+	u8 hash_type_tcpipv6_en;
+	u8 hash_type_ipv6_en;
+	u8 hash_type_tcpipv6ex_en;
+	u8 hash_type_ipv6ex_en;
+} vxge_hal_rth_hash_types_t;
+
+/*
+ * vxge_hal_vpath_udp_rth_disable - Disable UDP/RTH.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable udp rth
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_udp_rth_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_rts_rth_set - Set/configure RTS hashing.
+ * @vpath_handle: Virtual Path handle.
+ * @algorithm: Algorithm Select
+ * @hash_type: Hash Type
+ * @bucket_size: no of least significant bits to be used for hashing.
+ * @it_switch: Itable switch required
+ *
+ * Used to set/configure all RTS hashing related stuff.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rth_algoritms_t algorithm,
+    vxge_hal_rth_hash_types_t *hash_type,
+    u16 bucket_size,
+    u16 it_switch);
+
+/*
+ * vxge_hal_vpath_rts_rth_get - Read RTS hashing.
+ * @vpath_handle: Virtual Path handle.
+ * @algorithm: Buffer to return Algorithm Select
+ * @hash_type: Buffer to return Hash Type
+ * @table_select: Buffer to return active Table
+ * @bucket_size: Buffer to return no of least significant bits used for hashing.
+ *
+ * Used to read all RTS hashing related stuff.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(),
+ *		vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rth_algoritms_t *algorithm,
+    vxge_hal_rth_hash_types_t *hash_type,
+    u8 *table_select,
+    u16 *bucket_size);
+
+/*
+ * vxge_hal_vpath_rts_rth_key_set - Configure 40byte secret for hash calc.
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @KeySize: Number of 64-bit words
+ * @Key: upto 40-byte array of 64-bit values
+ * This function configures the 40-byte secret which is used for hash
+ * calculation.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_key_set(
+    vxge_hal_vpath_h vpath_handle,
+    u8 KeySize,
+    u64 *Key);
+
+/*
+ * vxge_hal_vpath_rts_rth_key_get - Read 40byte secret for hash calc.
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @KeySize: Number of 64-bit words
+ * @Key: Buffer to return the key
+ * This function reads the 40-byte secret which is used for hash
+ * calculation.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *		vxge_hal_vpath_rts_rth_key_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_key_get(
+    vxge_hal_vpath_h vpath_handle,
+    u8 KeySize,
+    u64 *Key);
+
+/*
+ * vxge_hal_vpath_rts_rth_jhash_cfg_set - Configure JHASH algorithm
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @golden_ratio: Golden ratio
+ * @init_value: Initial value
+ * This function configures JENKIN's HASH algorithm
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_jhash_cfg_set(
+    vxge_hal_vpath_h vpath_handle,
+    u32 golden_ratio,
+    u32 init_value);
+
+/*
+ * vxge_hal_vpath_rts_rth_jhash_cfg_get - Read JHASH algorithm
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @golden_ratio: Buffer to return Golden ratio
+ * @init_value: Buffer to return Initial value
+ * This function reads JENKIN's HASH algorithm
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *		vxge_hal_vpath_rts_rth_jhash_cfg_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_jhash_cfg_get(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *golden_ratio,
+    u32 *init_value);
+
+/*
+ * vxge_hal_vpath_rts_rth_mask_set - Set/configure JHASH mask.
+ * @vpath_handle: Virtual Path ahandle.
+ * @table_size: Size of the mask table
+ * @hash_mask_ipv6sa: IPv6SA Hash Mask
+ * @hash_mask_ipv6da: IPv6DA Hash Mask
+ * @hash_mask_ipv4sa: IPv4SA Hash Mask
+ * @hash_mask_ipv4da: IPv4DA Hash Mask
+ * @hash_mask_l4sp: L4SP Hash Mask
+ * @hash_mask_l4dp: L4DP Hash Mask
+ *
+ * Used to set/configure indirection table masks.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_mask_set(
+    vxge_hal_vpath_h vpath_handle,
+    u32 table_size,
+    u32 *hash_mask_ipv6sa,
+    u32 *hash_mask_ipv6da,
+    u32 *hash_mask_ipv4sa,
+    u32 *hash_mask_ipv4da,
+    u32 *hash_mask_l4sp,
+    u32 *hash_mask_l4dp);
+
+/*
+ * vxge_hal_vpath_rts_rth_mask_get - Read JHASH mask.
+ * @vpath_handle: Virtual Path ahandle.
+ * @table_size: Size of the mask table
+ * @hash_mask_ipv6sa: Buffer to return IPv6SA Hash Mask
+ * @hash_mask_ipv6da: Buffer to return IPv6DA Hash Mask
+ * @hash_mask_ipv4sa: Buffer to return IPv4SA Hash Mask
+ * @hash_mask_ipv4da: Buffer to return IPv4DA Hash Mask
+ * @hash_mask_l4sp: Buffer to return L4SP Hash Mask
+ * @hash_mask_l4dp: Buffer to return L4DP Hash Mask
+ *
+ * Used to read rth mask.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *	  vxge_hal_vpath_rts_rth_mask_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_mask_get(
+    vxge_hal_vpath_h vpath_handle,
+    u32 table_size,
+    u32 *hash_mask_ipv6sa,
+    u32 *hash_mask_ipv6da,
+    u32 *hash_mask_ipv4sa,
+    u32 *hash_mask_ipv4da,
+    u32 *hash_mask_l4sp,
+    u32 *hash_mask_l4dp);
+
+/*
+ * vxge_hal_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
+ * @vpath_handles: Virtual Path handles.
+ * @vpath_count: Number of vpath handles passed in vpath_handles
+ * @itable: Pointer to indirection table
+ * @itable_size: Number of entries in itable
+ *
+ * Used to set/configure indirection table.
+ * It enables the required no of entries in the IT.
+ * It adds entries to the IT.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_itable_set(
+    vxge_hal_vpath_h *vpath_handles,
+    u32 vpath_count,
+    u8 *itable,
+    u32 itable_size);
+
+/*
+ * vxge_hal_vpath_rts_rth_itable_get - Read indirection table (IT).
+ * @vpath_handles: Virtual Path handles.
+ * @vpath_count: Number of vpath handles passed in vpath_handles
+ * @itable: Pointer to the buffer to return indirection table
+ * @itable_size: pointer to buffer to return Number of entries in itable
+ *
+ * Used to read indirection table.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *		vxge_hal_vpath_rts_rth_itable_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_itable_get(
+    vxge_hal_vpath_h *vpath_handles,
+    u32 vpath_count,
+    u8 *itable,
+    u32 itable_size);
+
+/*
+ * vxge_hal_vpath_rts_rth_clr - Clear RTS hashing.
+ * @vpath_handles: Virtual Path handles.
+ * @vpath_count: Number of vpath handles passed in vpath_handles
+ *
+ * This function is used to clear all RTS hashing related stuff.
+ *
+ * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_itable_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_clr(
+    vxge_hal_vpath_h *vpath_handles,
+    u32 vpath_count);
+
+/*
+ * vxge_hal_vpath_promisc_enable - Enable promiscuous mode.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable promiscuous mode of X3100 operation.
+ *
+ * See also: vxge_hal_vpath_promisc_disable().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_promisc_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_promisc_disable - Disable promiscuous mode.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable promiscuous mode of X3100 operation.
+ *
+ * See also: vxge_hal_vpath_promisc_enable().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_promisc_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_bcast_enable - Enable broadcast
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable receiving broadcasts.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_bcast_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_bcast_disable - Disable broadcast
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable receiving broadcasts.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_bcast_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_mcast_enable - Enable multicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100 multicast addresses.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mcast_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_mcast_disable - Disable  multicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100 multicast addresses.
+ * Returns: VXGE_HAL_OK - success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mcast_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_ucast_enable - Enable unicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100 unicast addresses.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_ucast_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_ucast_disable - Disable  unicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100 unicast addresses.
+ * Returns: VXGE_HAL_OK - success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_ucast_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_all_vid_enable - Enable all Vlan Ids.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100 vlan ids.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_all_vid_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_all_vid_disable - Disable all Vlan Ids.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100  vlan ids.
+ * Returns: VXGE_HAL_OK - success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_all_vid_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_strip_vlan_tag_enable - Enable strip vlan tag.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100  strip vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_strip_vlan_tag_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_strip_vlan_tag_disable - Disable strip vlan tag.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100  strip vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_strip_vlan_tag_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+void
+vxge_hal_vpath_dynamic_tti_rtimer_set(vxge_hal_vpath_h vpath_handle,
+    u32 timer_val);
+
+void
+vxge_hal_vpath_dynamic_rti_rtimer_set(vxge_hal_vpath_h vpath_handle,
+    u32 timer_val);
+
+void
+vxge_hal_vpath_tti_ci_set(vxge_hal_vpath_h vpath_handle);
+
+void
+vxge_hal_vpath_tti_ci_reset(vxge_hal_vpath_h vpath_handle);
+
+void
+vxge_hal_vpath_rti_ci_set(vxge_hal_vpath_h vpath_handle);
+
+void
+vxge_hal_vpath_rti_ci_reset(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * struct vxge_hal_vpath_tpa_params - Vpath TPA Parameters.
+ * @tpa_lsov2_en: LSOv2 Behaviour for IP ID roll-over
+ *		1 - enable, 0 - disable,
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @tpa_ignore_frame_error: Ignore Frame Error. TPA may detect frame integrity
+ *		errors as it processes each frame. If this bit is set to '0',
+ *		the TPA will tag such frames as invalid and they will be dropped
+ *		by the transmit MAC. If the bit is set to '1',the frame will not
+ *		be tagged as "errored".  Detectable errors include:
+ *		1) early end-of-frame error, which occurs when the frame ends
+ *		before the number of bytes predicted by the IP "total length"
+ *		field have been received;
+ *		2) IP version mismatches;
+ *		3) IPv6 packets that include routing headers that are not type 0
+ *		4) Frames which contain IP packets but have an illegal SNAP-OUI
+ *		or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL
+ *		are set (see below).
+ *		setting the value of this field to VXGE_HAL_DEFAULT_32 - don't
+ *		change current setting
+ * @tpa_ipv6_keep_searching: If unknown IPv6 header is found,
+ *		 0 - stop searching for TCP
+ *		 1 - keep searching for TCP
+ *		 VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @tpa_l4_pshdr_present: If asserted true, indicates the host has provided a
+ *		 valid pseudo header for TCP or UDP running over IPv4 or IPv6
+ *		 if set to VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @tpa_support_mobile_ipv6_hdrs: This register is somewhat equivalent to
+ *		 asserting both Hercules register fields LSO_RT2_EN and
+ *		 LSO_IPV6_HAO_EN. Enable/disable support for Type 2 Routing
+ *		 Headers, and for Mobile-IPv6 Home Address Option (HAO), as
+ *		 defined by mobile-ipv6. if set to VXGE_HAL_DEFAULT_32 -
+ *		 don't change current setting
+ *
+ * See also: vxge_hal_vpath_tpa_set()
+ */
+typedef struct vxge_hal_vpath_tpa_params {
+	u32	tpa_lsov2_en;
+	u32	tpa_ignore_frame_error;
+	u32	tpa_ipv6_keep_searching;
+	u32	tpa_l4_pshdr_present;
+	u32	tpa_support_mobile_ipv6_hdrs;
+} vxge_hal_vpath_tpa_params;
+
+/*
+ * vxge_hal_vpath_tpa_set - Set tpa parameters.
+ * @vpath_handle: Virtual Path ahandle.
+ * @params: vxge_hal_vpath_tpa_params {} structure with parameters
+ *
+ * The function	sets the tpa parametrs for the vpath.
+ *
+ * See also: vxge_hal_vpath_tpa_params {}
+ */
+vxge_hal_status_e
+vxge_hal_vpath_tpa_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_tpa_params *params);
+
+/*
+ * struct vxge_hal_vpath_rpa_params - Vpath RPA Parameters.
+ *
+ * @rpa_ipv4_tcp_incl_ph: Determines if the pseudo-header is included in the
+ *		calculation of the L4 checksum that is passed to the host. This
+ *		field applies to TCP/IPv4 packets only. This field affects both
+ *		non-offload and LRO traffic. Note that the RPA always includes
+ *		the pseudo-header in the "Checksum Ok" L4 checksum calculation
+ *		i.e. the checksum that decides whether a frame is a candidate to
+ *		be offloaded.
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_ipv6_tcp_incl_ph: Determines whether the pseudo-header is included in
+ *		the calculation of the L4 checksum that is passed to the host.
+ *		This field applies to TCP/IPv6 packets only. This field affects
+ *		both non-offload and LRO traffic. Note that the RPA always
+ *		includes the pseudo-header in the "Checksum Ok" L4 checksum
+ *		calculation. i.e. the checksum that decides whether a frame
+ *		is a candidate to be offloaded.
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_ipv4_udp_incl_ph: Determines whether the pseudo-header is included in
+ *		the calculation of the L4 checksum that is passed to the host.
+ *		This field applies to UDP/IPv4 packets only. It only affects
+ *		non-offload traffic(since UDP frames are not candidates for LRO)
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_ipv6_udp_incl_ph: Determines if the pseudo-header is included in the
+ *		calculation of the L4 checksum that is passed to the host. This
+ *		field applies to UDP/IPv6 packets only. It only affects
+ *		non-offload traffic(since UDP frames are not candidates for LRO)
+ *		0 - Do not include the pseudo-header in L4 checksum calculation.
+ *		This setting should be used if the adapter is incorrectly
+ *		calculating the pseudo-header.
+ *		1 - Include the pseudo-header in L4 checksum calculation
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_l4_incl_cf: Determines whether the checksum field (CF) of the received
+ *		frame is included in the calculation of the L4 checksum that is
+ *		passed to the host. This field affects both non-offload and LRO
+ *		traffic. Note that the RPA always includes the checksum field in
+ *		the "Checksum Ok" L4 checksum calculation -- i.e. the checksum
+ *		that decides whether a frame is a candidate to be offloaded.
+ *		0 - Do not include the checksum field in L4 checksum calculation
+ *		1 - Include the checksum field in L4 checksum calculation
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to
+ *		remove the VLAN tag from all received tagged frames that are not
+ *		replicated at the internal L2 switch.
+ *		0 - Do not strip the VLAN tag.
+ *		1 - Strip the VLAN tag. Regardless of this setting,VLAN tags are
+ *		always placed into the RxDMA descriptor.
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_l4_comp_csum: Determines whether the calculated L4 checksum should be
+ *		complemented before it is passed to the host This field affects
+ *		both non-offload and LRO traffic.
+ *		0 - Do not complement the calculated L4 checksum.
+ *		1 - Complement the calculated L4 checksum
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_l3_incl_cf: Determines whether the checksum field (CF) of the received
+ *		frame is included in the calculation of the L3 checksum that is
+ *		passed to the host. This field affects both non-offload and LRO
+ *		traffic. Note that the RPA always includes the checksum field in
+ *		the "Checksum Ok" L3 checksum calculation -- i.e. the checksum
+ *		that decides whether a frame is a candidate to be offloaded.
+ *		0 - Do not include the checksum field in L3 checksum calculation
+ *		1 - Include the checksum field in L3 checksum calculation
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_l3_comp_csum: Determines whether the calculated L3 checksum should be
+ *		complemented before it is passed to the host This field affects
+ *		both non-offload and LRO traffic.
+ *		0 - Do not complement the calculated L3 checksum.
+ *		1 - Complement the calculated L3 checksum
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ * @rpa_ucast_all_addr_en: Enables frames with any unicast address (as its
+ *		destination address) to be passed to the host.
+ *		Setting this field to VXGE_HAL_DEFAULT_32 - don't change current
+ *		setting
+ * @rpa_mcast_all_addr_en: Enables frames with any multicast address (as its
+ *		destination address) to be passed to the host.
+ *		Setting this field to VXGE_HAL_DEFAULT_32 - don't change current
+ *		setting
+ * @rpa_bcast_en: Enables frames with any broadicast address (as its
+ *		destination address) to be passed to the host.
+ *		Setting this field to VXGE_HAL_DEFAULT_32 - don't change current
+ *		setting
+ * @rpa_all_vid_en: romiscuous mode, it overrides the value held in this field.
+ *		0 - Disable;
+ *		1 - Enable
+ *		VXGE_HAL_DEFAULT_32 - don't change current setting
+ *		Note: RXMAC_GLOBAL_CFG.AUTHORIZE_VP_ALL_VID must be set to
+ *		allow this.
+ *
+ * See also: vxge_hal_vpath_rpa_set()
+ */
+typedef struct vxge_hal_vpath_rpa_params {
+	u32	rpa_ipv4_tcp_incl_ph;
+	u32	rpa_ipv6_tcp_incl_ph;
+	u32	rpa_ipv4_udp_incl_ph;
+	u32	rpa_ipv6_udp_incl_ph;
+	u32	rpa_l4_incl_cf;
+	u32	rpa_strip_vlan_tag;
+	u32	rpa_l4_comp_csum;
+	u32	rpa_l3_incl_cf;
+	u32	rpa_l3_comp_csum;
+	u32	rpa_ucast_all_addr_en;
+	u32	rpa_mcast_all_addr_en;
+	u32	rpa_bcast_en;
+	u32	rpa_all_vid_en;
+} vxge_hal_vpath_rpa_params;
+
+/*
+ * vxge_hal_vpath_rpa_set - Set rpa parameters.
+ * @vpath_handle: Virtual Path ahandle.
+ * @params: vxge_hal_vpath_rpa_params {} structure with parameters
+ *
+ * The function	sets the rpa parametrs for the vpath.
+ *
+ * See also: vxge_hal_vpath_rpa_params {}
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rpa_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_rpa_params *params);
+
+/*
+ * vxge_hal_vpath_poll_rx - Poll Rx	od Virtual Path	for completed
+ *			 descriptors and process the same.
+ * @vpath_handle: Virtual Path ahandle.
+ * @got_rx: Buffer to return the flag set if receive interrupt is occured
+ *
+ * The function	polls the Rx for the completed	descriptors and	calls
+ * the upper-layer driver (ULD)	via supplied completion	callback.
+ *
+ * Returns: VXGE_HAL_OK, if the polling is completed successful.
+ * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed
+ * descriptors available which are yet to be processed.
+ *
+ * See also: vxge_hal_vpath_poll_tx()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_poll_rx(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *got_rx);
+
+/*
+ * vxge_hal_vpath_poll_tx - Poll Tx	for completed descriptors and process
+ *			 the same.
+ * @vpath_handle: Virtual Path ahandle.
+ * @got_tx: Buffer to return the flag set if transmit interrupt is occured
+ *
+ * The function	polls the Tx for the completed	descriptors and	calls
+ * the upper-layer driver (ULD)	via supplied completion callback.
+ *
+ * Returns: VXGE_HAL_OK, if the polling is completed successful.
+ * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed
+ * descriptors available which are yet to be processed.
+ *
+ * See also: vxge_hal_vpath_poll_rx().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_poll_tx(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *got_tx);
+
+
+/*
+ * vxge_hal_vpath_intr_enable - Enable vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to enable.
+ *
+ * Enable vpath interrupts. The function is to be executed the last in
+ * vpath initialization sequence.
+ *
+ * See also: vxge_hal_vpath_intr_disable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_intr_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_intr_disable - Disable vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to disable.
+ *
+ * Disable vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_intr_enable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_intr_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_mask_all - Mask all vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	all vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_all()
+ */
+void
+vxge_hal_vpath_mask_all(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_unmask_all - Unmask all vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask all vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_all()
+ */
+void
+vxge_hal_vpath_unmask_all(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_begin_irq - Begin IRQ processing.
+ * @vpath_handle: Virtual Path handle.
+ * @skip_alarms: Do not clear the alarms
+ * @reason: "Reason" for the interrupt,	the value of vpath's
+ *			general_int_status register.
+ *
+ * The function	performs two actions, It first checks whether (shared IRQ) the
+ * interrupt was raised	by the device. Next, it	masks the device interrupts.
+ *
+ * Note:
+ * vxge_hal_vpath_begin_irq() does not flush MMIO writes through the
+ * bridge. Therefore, two back-to-back interrupts are potentially possible.
+ * It is the responsibility	of the ULD to make sure	that only one
+ * vxge_hal_vpath_continue_irq() runs at a time.
+ *
+ * Returns: 0, if the interrupt	is not "ours" (note that in this case the
+ * vpath remain enabled).
+ * Otherwise, vxge_hal_vpath_begin_irq() returns 64bit general adapter
+ * status.
+ * See also: vxge_hal_vpath_handle_irq()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_begin_irq(
+    vxge_hal_vpath_h vpath_handle,
+    u32 skip_alarms,
+    u64 *reason);
+
+/*
+ * vxge_hal_vpath_continue_irq - Continue handling IRQ:	process	all
+ *				completed descriptors.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Process completed descriptors and unmask the	vpath interrupts.
+ *
+ * The vxge_hal_vpath_continue_irq() calls upper-layer driver (ULD)
+ * via supplied completion callback.
+ *
+ * Note	that the vxge_hal_vpath_continue_irq is	part of	the _fast_ path.
+ * To optimize the processing, the function does _not_ check for
+ * errors and alarms.
+ *
+ * Returns: VXGE_HAL_OK.
+ *
+ * See also: vxge_hal_vpath_handle_irq(),
+ * vxge_hal_ring_rxd_next_completed(),
+ * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {},
+ * vxge_hal_fifo_callback_f {}.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_continue_irq(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpathe_handle_irq - Handle vpath IRQ.
+ * @vpath_handle: Virtual Path handle.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Perform the complete	handling of the	line interrupt.	The function
+ * performs two	calls.
+ * First it uses vxge_hal_vpath_begin_irq() to check the reason for
+ * the interrupt and mask the vpath interrupts.
+ * Second, it calls vxge_hal_vpath_continue_irq() to process all
+ * completed descriptors and re-enable the interrupts.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_WRONG_IRQ - (shared)	IRQ	produced by	other device.
+ *
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_handle_irq(
+    vxge_hal_vpath_h vpath_handle,
+    u32 skip_alarms);
+
+/*
+ * vxge_hal_vpath_mask_tx - Mask Tx interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	Tx device interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_tx(), vxge_hal_vpath_mask_rx(),
+ * vxge_hal_vpath_clear_tx().
+ */
+void
+vxge_hal_vpath_mask_tx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_clear_tx - Acknowledge (that is, clear) the
+ * condition that has caused the TX	interrupt.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Tx interrupt.
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
+ * vxge_hal_vpath_clear_rx(), vxge_hal_vpath_mask_tx().
+ */
+void
+vxge_hal_vpath_clear_tx(
+    vxge_hal_vpath_h vpath_handle);
+
+
+/*
+ * vxge_hal_vpath_unmask_tx - Unmask Tx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask Tx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_tx(), vxge_hal_vpath_clear_tx().
+ */
+void
+vxge_hal_vpath_unmask_tx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_mask_rx - Mask Rx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_rx(), vxge_hal_vpath_mask_tx(),
+ * vxge_hal_vpath_clear_rx().
+ */
+void
+vxge_hal_vpath_mask_rx(
+    vxge_hal_vpath_h vpath_handle);
+
+
+/*
+ * vxge_hal_vpath_clear_rx - Acknowledge (that is, clear) the
+ * condition that has caused the RX	interrupt.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Acknowledge (that is, clear)	the condition that has caused
+ * the Rx interrupt.
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
+ * vxge_hal_vpath_clear_tx(), vxge_hal_vpath_mask_rx().
+ */
+void
+vxge_hal_vpath_clear_rx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_unmask_rx - Unmask Rx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_rx(), vxge_hal_vpath_clear_rx().
+ */
+void
+vxge_hal_vpath_unmask_rx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_mask_tx_rx - Mask Tx and Rx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	Tx and Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_tx_rx(), vxge_hal_vpath_clear_tx_rx().
+ */
+void
+vxge_hal_vpath_mask_tx_rx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_clear_tx_rx - Acknowledge (that is, clear) the
+ * condition that has caused the Tx and RX interrupt.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Acknowledge (that is, clear)	the condition that has caused
+ * the Tx and Rx interrupt.
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
+ * vxge_hal_vpath_clear_tx_rx(), vxge_hal_vpath_mask_tx_rx().
+ */
+void
+vxge_hal_vpath_clear_tx_rx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_unmask_tx_rx - Unmask Tx and Rx interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask Tx and Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_tx_rx(), vxge_hal_vpath_clear_tx_rx().
+ */
+void
+vxge_hal_vpath_unmask_tx_rx(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_alarm_process - Process Alarms.
+ * @vpath: Virtual Path.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Process vpath alarms.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_alarm_process(
+    vxge_hal_vpath_h vpath_handle,
+    u32 skip_alarms);
+
+/* NEWCODE */
+
+vxge_hal_status_e
+vxge_hal_vpath_mf_msix_set(vxge_hal_vpath_h vpath_handle,
+    int *tim_msix_id, int alarm_msix_id);
+void
+vxge_hal_vpath_mf_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id);
+void
+vxge_hal_vpath_mf_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id);
+void
+vxge_hal_vpath_mf_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id);
+
+/* NEWCODE */
+
+/*
+ * vxge_hal_vpath_msix_mode - Is MSIX enabled?
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Returns 0 if MSI is enabled for the specified device,
+ * non-zero otherwise.
+ */
+u32
+vxge_hal_vpath_msix_mode(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_msix_set - Associate MSIX vectors with TIM interrupts and
+ *			   alrms
+ * @vpath_handle: Virtual Path handle.
+ * @tim_msix_id: MSIX vectors associated with VXGE_HAL_VPATH_MSIX_MAX number of
+ *		interrupts(Valid numbers 0 to 3).
+ * @alarm_msix_id: MSIX vector for alarm (Valid numbers 0 to 3).
+ *
+ * This API will associate a given MSIX vector numbers with the four TIM
+ * interrupts and alarm interrupt.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_msix_set(vxge_hal_vpath_h vpath_handle,
+    int *tim_msix_id,
+    int alarm_msix_id);
+
+/*
+ * vxge_hal_vpath_msix_mask - Mask MSIX Vector.
+ * @vpath_handle: Virtual Path handle.
+ * @msix_id:  MSIX ID
+ *
+ * The function masks the msix interrupt for the given msix_id
+ *
+ * Note:
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id);
+
+/*
+ * vxge_hal_vpath_msix_clear - Clear MSIX Vector.
+ * @vpath_handle: Virtual Path handle.
+ * @msix_id:  MSI ID
+ *
+ * The function clears the msix interrupt for the given msix_id
+ *
+ * Note:
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id);
+
+/*
+ * vxge_hal_vpath_msix_unmask - Unmask MSIX Vector.
+ * @vpath_handle: Virtual Path handle.
+ * @msix_id:  MSI ID
+ *
+ * The function unmasks the msix interrupt for the given msix_id
+ *
+ * Note:
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id);
+
+/*
+ * vxge_hal_vpath_msix_mask_all - Mask all MSIX vectors for the vpath.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * The function masks the msix interrupt for the given vpath
+ *
+ */
+void
+vxge_hal_vpath_msix_mask_all(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_msix_unmask_all - Unmask all MSIX vectors for the vpath.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * The function unmasks the msix interrupt for the given vpath
+ *
+ */
+void
+vxge_hal_vpath_msix_unmask_all(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_is_rxdmem_leak - Check for the rxd memory leak.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * The function checks for the rxd memory leak.
+ *
+ */
+u32
+vxge_hal_vpath_is_rxdmem_leak(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_rldram_test - offline test for access to the RldRam chip on
+ *			the NIC
+ * @devh: HAL device handle.
+ * @data: variable that returns the result of each of the test
+ * conducted by the driver.
+ *
+ * This is one of the offline test that tests the read and write
+ * access to the RldRam chip on the NIC.
+ * Return value:
+ * 0 on success.
+ */
+vxge_hal_status_e
+vxge_hal_rldram_test(
+    vxge_hal_device_h devh,
+    u64 *data);
+
+/*
+ * vxge_hal_check_alignment - Check buffer alignment and	calculate the
+ *		    "misaligned"	portion.
+ * @dma_pointer: DMA address of	the	buffer.
+ * @size: Buffer size, in bytes.
+ * @alignment: Alignment "granularity" (see	below),	in bytes.
+ * @copy_size: Maximum number of bytes to "extract"	from the buffer
+ * (in order to	spost it as	a separate scatter-gather entry). See below.
+ *
+ * Check buffer	alignment and calculate	"misaligned" portion, if exists.
+ * The buffer is considered	aligned	if its address is multiple of
+ * the specified @alignment. If	this is	the case,
+ * vxge_hal_check_alignment() returns zero.
+ * Otherwise, vxge_hal_check_alignment() uses the last argument,
+ * @copy_size,
+ * to calculate	the	size to	"extract" from the buffer. The @copy_size
+ * may or may not be equal @alignment. The difference between these two
+ * arguments is	that the @alignment is used to make the	decision: aligned
+ * or not aligned. While the @copy_size	is used	to calculate the portion
+ * of the buffer to "extract", i.e. to post as a separate entry in the
+ * transmit descriptor.	For example, the combination
+ * @alignment=8	and @copy_size=64 will work okay on AMD Opteron boxes.
+ *
+ * Note: @copy_size should be a	multiple of @alignment. In many	practical
+ * cases @copy_size and	@alignment will	probably be equal.
+ *
+ * See also: vxge_hal_fifo_txdl_buffer_set_aligned().
+ */
+u32
+vxge_hal_check_alignment(
+    dma_addr_t dma_pointer,
+    u32 size,
+    u32 alignment,
+    u32 copy_size);
+
+
+void
+vxge_hw_vpath_set_zero_rx_frm_len(vxge_hal_device_h devh, u32 vp_id);
+
+void
+vxge_hw_vpath_wait_receive_idle(vxge_hal_device_h devh, u32 vp_id,
+    u32 *count, u32 *total_count);
+
+#define	VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT	5
+#define	VXGE_HW_MAX_POLLING_COUNT		160
+
+
+__EXTERN_END_DECLS
+
+#include <dev/vxge/include/vxge-os-debug.h>
+
+#endif	/* VXGE_HAL_LL_H */
diff --git a/sys/dev/vxge/include/vxgehal-mgmt.h b/sys/dev/vxge/include/vxgehal-mgmt.h
new file mode 100644
index 000000000000..682e81ed8891
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-mgmt.h
@@ -0,0 +1,688 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_MGMT_H
+#define	VXGE_HAL_MGMT_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * struct vxge_hal_mgmt_about_info_t - About info.
+ * @vendor: PCI Vendor ID.
+ * @device: PCI Device ID.
+ * @subsys_vendor: PCI Subsystem Vendor ID.
+ * @subsys_device: PCI Subsystem Device ID.
+ * @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
+ * @vendor_name: Exar Corp.
+ * @chip_name: X3100.
+ * @media: Fiber, copper.
+ * @hal_major: HAL major version number.
+ * @hal_minor: HAL minor version number.
+ * @hal_fix: HAL fix number.
+ * @hal_build: HAL build number.
+ * @ll_major: Link-layer ULD major version number.
+ * @ll_minor: Link-layer ULD minor version number.
+ * @ll_fix: Link-layer ULD fix version number.
+ * @ll_build: Link-layer ULD build number.
+ */
+typedef struct vxge_hal_mgmt_about_info_t {
+	u16		vendor;
+	u16		device;
+	u16		subsys_vendor;
+	u16		subsys_device;
+	u8		board_rev;
+	char		vendor_name[16];
+	char		chip_name[16];
+	char		media[16];
+	char		hal_major[4];
+	char		hal_minor[4];
+	char		hal_fix[4];
+	char		hal_build[16];
+	char		ll_major[4];
+	char		ll_minor[4];
+	char		ll_fix[4];
+	char		ll_build[16];
+} vxge_hal_mgmt_about_info_t;
+
+
+/*
+ * vxge_hal_mgmt_about - Retrieve about info.
+ * @devh: HAL device handle.
+ * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}.
+ * @size: Pointer to buffer containing the Size of the @buffer_info.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field
+ *
+ * Retrieve information such as PCI device and vendor IDs, board
+ * revision number, HAL version number, etc.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ * VXGE_HAL_FAIL - Failed to retrieve the information.
+ *
+ * See also: vxge_hal_mgmt_about_info_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_about(vxge_hal_device_h devh,
+    vxge_hal_mgmt_about_info_t *about_info,
+    u32 *size);
+
+/*
+ * vxge_hal_mgmt_pci_config - Retrieve PCI configuration.
+ * @devh: HAL device handle.
+ * @buffer: Buffer for PCI configuration space.
+ * @size: Pointer to buffer containing the Size of the @buffer.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_pci_config_t) and returns required size in this field
+ *
+ * Get PCI configuration. Permits to retrieve at run-time configuration
+ * values that were used to configure the device at load-time.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size);
+
+/*
+ * struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities
+ * @pm_cap_ver: Version
+ * @pm_cap_pme_clock: PME clock required
+ * @pm_cap_aux_power: Auxilliary power support
+ * @pm_cap_dsi: Device specific initialization
+ * @pm_cap_aux_current: auxiliary current requirements
+ * @pm_cap_cap_d0: D1 power state support
+ * @pm_cap_cap_d1: D2 power state support
+ * @pm_cap_pme_d0: PME# can be asserted from D3hot
+ * @pm_cap_pme_d1: PME# can be asserted from D3hot
+ * @pm_cap_pme_d2: PME# can be asserted from D3hot
+ * @pm_cap_pme_d3_hot: PME# can be asserted from D3hot
+ * @pm_cap_pme_d3_cold: PME# can be asserted from D3cold
+ * @pm_ctrl_state: Current power state (D0 to D3)
+ * @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0
+ * @pm_ctrl_pme_enable: PME pin enable
+ * @pm_ctrl_pme_data_sel: Data select
+ * @pm_ctrl_pme_data_scale: Data scale
+ * @pm_ctrl_pme_status: PME pin status
+ * @pm_ppb_ext_b2_b3: Stop clock when in D3hot
+ * @pm_ppb_ext_ecc_en: Bus power/clock control enable
+ * @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel
+ *
+ * Power Management Capabilities structure
+ */
+typedef struct vxge_hal_mgmt_pm_cap_t {
+	u32	pm_cap_ver;
+	u32	pm_cap_pme_clock;
+	u32	pm_cap_aux_power;
+	u32	pm_cap_dsi;
+	u32	pm_cap_aux_current;
+	u32	pm_cap_cap_d0;
+	u32	pm_cap_cap_d1;
+	u32	pm_cap_pme_d0;
+	u32	pm_cap_pme_d1;
+	u32	pm_cap_pme_d2;
+	u32	pm_cap_pme_d3_hot;
+	u32	pm_cap_pme_d3_cold;
+	u32	pm_ctrl_state;
+	u32	pm_ctrl_no_soft_reset;
+	u32	pm_ctrl_pme_enable;
+	u32	pm_ctrl_pme_data_sel;
+	u32	pm_ctrl_pme_data_scale;
+	u32	pm_ctrl_pme_status;
+	u32	pm_ppb_ext_b2_b3;
+	u32	pm_ppb_ext_ecc_en;
+	u32	pm_data_reg;
+} vxge_hal_mgmt_pm_cap_t;
+
+/*
+ * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities
+ * @devh: HAL device handle.
+ * @pm_cap: Power Management Capabilities
+ *
+ * Return the pm capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_pm_cap_t *pm_cap);
+
+/*
+ * struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities
+ * @sid_number_of_slots: Number of solts
+ * @sid_first_in_chasis: First in chasis flag
+ * @sid_chasis_number: Chasis Number
+ *
+ * Slot ID Capabilities structure
+ */
+typedef struct vxge_hal_mgmt_sid_cap_t {
+	u32	sid_number_of_slots;
+	u32	sid_first_in_chasis;
+	u32	sid_chasis_number;
+} vxge_hal_mgmt_sid_cap_t;
+
+/*
+ * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities
+ * @devh: HAL device handle.
+ * @sid_cap: Slot Id Capabilities
+ *
+ * Return the pm capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_sid_cap_t *sid_cap);
+
+/*
+ * struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities
+ * @enable: 1 - MSI enabled, 0 - MSI not enabled
+ * @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only)
+ * @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only
+ *		(valid for get only)
+ * @vectors_allocated: Number of vectors allocated
+ *		000-1 vectors
+ *		001-2 vectors
+ *		010-4 vectors
+ *		011-8 vectors
+ *		100-16 vectors
+ *		101-32 vectors
+ * @max_vectors_capable: Maximum number of vectors that can be allocated
+ *		(valid for get only)
+ *		000-1 vectors
+ *		001-2 vectors
+ *		010-4 vectors
+ *		011-8 vectors
+ *		100-16 vectors
+ *		101-32 vectors
+ * @address: MSI address
+ * @data: MSI Data
+ * @mask_bits: For each Mask bit that is set, the function is prohibited from
+ *		sending the associated message
+ * @pending_bits: For each Pending bit that is set, the function has a
+ *		pending associated message.
+ *
+ * MSI Capabilities structure
+ */
+typedef struct vxge_hal_mgmt_msi_cap_t {
+	u32	enable;
+	u32	is_pvm_capable;
+	u32	is_64bit_addr_capable;
+	u32	vectors_allocated;
+	u32	max_vectors_capable;
+#define	VXGE_HAL_MGMT_MSI_CAP_VECTORS_1		0
+#define	VXGE_HAL_MGMT_MSI_CAP_VECTORS_2		1
+#define	VXGE_HAL_MGMT_MSI_CAP_VECTORS_4		2
+#define	VXGE_HAL_MGMT_MSI_CAP_VECTORS_8		3
+#define	VXGE_HAL_MGMT_MSI_CAP_VECTORS_16	4
+#define	VXGE_HAL_MGMT_MSI_CAP_VECTORS_32	5
+	u64	address;
+	u16	data;
+	u32	mask_bits;
+	u32	pending_bits;
+} vxge_hal_mgmt_msi_cap_t;
+
+/*
+ * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities
+ * @devh: HAL device handle.
+ * @msi_cap: MSI Capabilities
+ *
+ * Return the msi capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_msi_cap_t *msi_cap);
+
+/*
+ * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities
+ * @devh: HAL device handle.
+ * @msi_cap: MSI Capabilities
+ *
+ * Sets the msi capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
+    vxge_hal_mgmt_msi_cap_t *msi_cap);
+
+/*
+ * struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities
+ * @enable: 1 - MSIX enabled, 0 - MSIX not enabled
+ * @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors
+ * @table_size: MSIX Table Size-1
+ * @table_offset: Offset of the table from the table_bir
+ * @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
+ * @pba_offset: Offset of the PBA from the pba_bir
+ * @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
+ *
+ * MSIS Capabilities structure
+ */
+typedef struct vxge_hal_mgmt_msix_cap_t {
+	u32	enable;
+	u32	mask_all_vect;
+	u32	table_size;
+	u32	table_offset;
+	u32	table_bir;
+#define	VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0	0
+#define	VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1	2
+#define	VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2	4
+	u32	pba_offset;
+	u32	pba_bir;
+#define	VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0		0
+#define	VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1		2
+#define	VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2		4
+} vxge_hal_mgmt_msix_cap_t;
+
+/*
+ * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities
+ * @devh: HAL device handle.
+ * @msix_cap: MSIX Capabilities
+ *
+ * Return the msix capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_msix_cap_t *msix_cap);
+
+/*
+ * struct vxge_hal_pci_err_cap_t - PCI Error Capabilities
+ * @pci_err_header: Error header
+ * @pci_err_uncor_status: Uncorrectable error status
+ *		0x00000001 - Training
+ *		0x00000010 - Data Link Protocol
+ *		0x00001000 - Poisoned TLP
+ *		0x00002000 - Flow Control Protocol
+ *		0x00004000 - Completion Timeout
+ *		0x00008000 - Completer Abort
+ *		0x00010000 - Unexpected Completion
+ *		0x00020000 - Receiver Overflow
+ *		0x00040000 - Malformed TLP
+ *		0x00080000 - ECRC Error Status
+ *		0x00100000 - Unsupported Request
+ * @pci_err_uncor_mask: Uncorrectable mask
+ * @pci_err_uncor_server: Uncorrectable server
+ * @pci_err_cor_status: Correctable status
+ *		0x00000001 - Receiver Error Status
+ *		0x00000040 - Bad TLP Status
+ *		0x00000080 - Bad DLLP Status
+ *		0x00000100 - REPLAY_NUM Rollover
+ *		0x00001000 - Replay Timer Timeout
+ *		VXGE_HAL_PCI_ERR_COR_MASK	20
+ * @pci_err_cap: Error capability
+ *		0x00000020 - ECRC Generation Capable
+ *		0x00000040 - ECRC Generation Enable
+ *		0x00000080 - ECRC Check Capable
+ *		0x00000100 - ECRC Check Enable
+ * @err_header_log: Error header log
+ * @unused: Reserved
+ * @pci_err_root_command: Error root command
+ * @pci_err_root_status: Error root status
+ * @pci_err_root_cor_src:  Error root correctible source
+ * @pci_err_root_src: Error root source
+ *
+ * MSIS Capabilities structure
+ */
+typedef struct vxge_hal_pci_err_cap_t {
+	u32	pci_err_header;
+	u32	pci_err_uncor_status;
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN	    0x00000001	/* Training */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_DLP	    0x00000010	/* Data Link Protocol */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000	/* Poisoned TLP */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_FCP	    0x00002000	/* Flow Ctrl Protocol */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME  0x00004000	/* Completion Timeout */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000	/* Completer Abort */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP   0x00010000	/* Unexpected Compl */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER    0x00020000	/* Receiver Overflow */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP   0x00040000	/* Malformed TLP */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_ECRC	    0x00080000	/* ECRC Error Status */
+#define	VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP	    0x00100000 /* Unsupported Request */
+	u32	pci_err_uncor_mask;
+	u32	pci_err_uncor_server;
+	u32	pci_err_cor_status;
+#define	VXGE_HAL_PCI_ERR_CAP_COR_RCVR	    0x00000001	/* Recv Err Status */
+#define	VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP    0x00000040	/* Bad TLP Status */
+#define	VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP   0x00000080	/* Bad DLLP Status */
+#define	VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL   0x00000100	/* REPLAY Rollover */
+#define	VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER  0x00001000	/* Replay Timeout */
+#define	VXGE_HAL_PCI_ERR_CAP_COR_MASK	20	/* Corrble Err Mask */
+	u32	pci_err_cap;
+#define	VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x)	 ((x) & 31)	/* First Err Ptr */
+#define	VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC  0x00000020	/* ECRC Gen Capable */
+#define	VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE  0x00000040	/* ECRC Gen Enable */
+#define	VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC  0x00000080	/* ECRC Chk Capable */
+#define	VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE  0x00000100	/* ECRC Chk Enable */
+	u32	err_header_log;
+#define	VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x)  ((x) >> 31)	/* Error Hdr Log */
+	u32	unused[3];
+	u32	pci_err_root_command;
+	u32	pci_err_root_status;
+	u32	pci_err_root_cor_src;
+	u32	pci_err_root_src;
+} vxge_hal_pci_err_cap_t;
+
+/*
+ * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities
+ * @devh: HAL device handle.
+ * @err_cap: PCI-E Extended Error Capabilities
+ *
+ * Return the PCI-E Extended Error capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_pci_err_cap_t *err_cap);
+
+/*
+ * vxge_hal_mgmt_driver_config - Retrieve driver configuration.
+ * @drv_config: Device configuration, see vxge_hal_driver_config_t {}.
+ * @size: Pointer to buffer containing the Size of the @drv_config.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_driver_config_t) and returns required size in this field
+ *
+ * Get driver configuration. Permits to retrieve at run-time configuration
+ * values that were used to configure the device at load-time.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config().
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size);
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+
+/*
+ * vxge_hal_mgmt_trace_read - Read trace buffer contents.
+ * @buffer: Buffer to store the trace buffer contents.
+ * @buf_size: Size of the buffer.
+ * @offset: Offset in the internal trace buffer to read data.
+ * @read_length: Size of the valid data in the buffer.
+ *
+ * Read  HAL trace buffer contents starting from the offset
+ * upto the size of the buffer or till EOF is reached.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_trace_read(char *buffer,
+    unsigned buf_size,
+    unsigned *offset,
+    unsigned *read_length);
+
+#endif
+
+/*
+ * vxge_hal_mgmt_device_config - Retrieve device configuration.
+ * @devh: HAL device handle.
+ * @dev_config: Device configuration, see vxge_hal_device_config_t {}.
+ * @size: Pointer to buffer containing the Size of the @dev_config.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_device_config_t) and returns required size in this field
+ *
+ * Get device configuration. Permits to retrieve at run-time configuration
+ * values that were used to initialize and configure the device.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config().
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
+    vxge_hal_device_config_t *dev_config, u32 *size);
+
+
+/*
+ * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified
+ * offset.
+ * @devh: HAL device handle.
+ * @offset: Offset in the 256 byte PCI configuration space.
+ * @value_bits: 8, 16, or 32 (bits) to read.
+ * @value: Value returned by HAL.
+ *
+ * Read PCI configuration, given device and offset in the PCI space.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid
+ * values(8/16/32).
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
+    int value_bits, u32 *value);
+
+/*
+ * enum vxge_hal_mgmt_reg_type_e - Register types.
+ *
+ * @vxge_hal_mgmt_reg_type_legacy: Legacy registers
+ * @vxge_hal_mgmt_reg_type_toc: TOC Registers
+ * @vxge_hal_mgmt_reg_type_common: Common Registers
+ * @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers
+ * @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers
+ * @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers
+ * @vxge_hal_mgmt_reg_type_srpcim: srpcim registers
+ * @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers
+ * @vxge_hal_mgmt_reg_type_vpath: vpath registers
+ *
+ * Register type enumaration
+ */
+typedef enum vxge_hal_mgmt_reg_type_e {
+	vxge_hal_mgmt_reg_type_legacy = 0,
+	vxge_hal_mgmt_reg_type_toc = 1,
+	vxge_hal_mgmt_reg_type_common = 2,
+	vxge_hal_mgmt_reg_type_memrepair = 3,
+	vxge_hal_mgmt_reg_type_pcicfgmgmt = 4,
+	vxge_hal_mgmt_reg_type_mrpcim = 5,
+	vxge_hal_mgmt_reg_type_srpcim = 6,
+	vxge_hal_mgmt_reg_type_vpmgmt = 7,
+	vxge_hal_mgmt_reg_type_vpath = 8
+} vxge_hal_mgmt_reg_type_e;
+
+/*
+ * vxge_hal_mgmt_reg_read - Read X3100 register.
+ * @devh: HAL device handle.
+ * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
+ * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
+ *		ignored for others
+ * @offset: Register offset in the register space qualified by the type and
+ *		index.
+ * @value: Register value. Returned by HAL.
+ * Read X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
+ * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
+    vxge_hal_mgmt_reg_type_e type,
+    u32 index,
+    u32 offset,
+    u64 *value);
+
+/*
+ * vxge_hal_mgmt_reg_Write - Write X3100 register.
+ * @devh: HAL device handle.
+ * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
+ * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
+ *		ignored for others
+ * @offset: Register offset in the register space qualified by the type and
+ *		index.
+ * @value: Register value to be written.
+ * Write X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
+ * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
+    vxge_hal_mgmt_reg_type_e type,
+    u32 index,
+    u32 offset,
+    u64 value);
+
+/*
+ * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset
+ *			     from bar0.
+ * @devh: HAL device handle.
+ * @offset: Register offset from bar0
+ * @value: Register value. Returned by HAL.
+ * Read X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
+    u32 offset,
+    u64 *value);
+
+/*
+ * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset
+ *			     from bar1.
+ * @devh: HAL device handle.
+ * @offset: Register offset from bar1
+ * @value: Register value. Returned by HAL.
+ * Read X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
+    u32 offset,
+    u64 *value);
+
+/*
+ * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset
+ *			     from bar0.
+ * @devh: HAL device handle.
+ * @offset: Register offset from bar0
+ * @value: Register value to be written.
+ * Write X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
+    u32 offset,
+    u64 value);
+
+/*
+ * vxge_hal_mgmt_register_config - Retrieve register configuration.
+ * @devh: HAL device handle.
+ * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
+ * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
+ *		ignored for others
+ * @config: Device configuration, see vxge_hal_device_config_t {}.
+ * @size: Pointer to buffer containing the Size of the @reg_config.
+ * HAL will return an error if the size is smaller than
+ * requested register space and returns required size in this field
+ *
+ * Get register configuration. Permits to retrieve register values.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
+ * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
+    vxge_hal_mgmt_reg_type_e type,
+    u32 vp_id,
+    u8 *config,
+    u32 *size);
+
+/*
+ * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port
+ * @devh: HAL device handle.
+ * @port: Port number
+ *
+ * This routine only gets the temperature for XFP modules. Also, updating of the
+ * NVRAM can sometimes fail and so the reading we might get may not be uptodate.
+ */
+u32	vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port);
+
+/*
+ * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback
+ * @devh: HAL device handle.
+ * @port: Port number
+ * @enable:Boolean set to 1 to enable and 0 to disable.
+ *
+ * Enable or disable PMA loopback.
+ * Return value:
+ * 0 on success.
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
+
+/*
+ * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback
+ * @devh: HAL device handle.
+ * @port: Port number
+ * @enable:Boolean set to 1 to enable and 0 to disable.
+ *
+ * Enable or disable xgmii loopback.
+ * Return value:
+ * 0 on success.
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_MGMT_H */
diff --git a/sys/dev/vxge/include/vxgehal-mgmtaux.h b/sys/dev/vxge/include/vxgehal-mgmtaux.h
new file mode 100644
index 000000000000..6eba36abc0ac
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-mgmtaux.h
@@ -0,0 +1,389 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_MGMTAUX_H
+#define	VXGE_HAL_MGMTAUX_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * vxge_hal_aux_about_read - Retrieve and format about info.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Retrieve about info (using vxge_hal_mgmt_about()) and sprintf it
+ * into the provided @retbuf.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_FAIL - Failed to retrieve the information.
+ *
+ * See also: vxge_hal_mgmt_about(), vxge_hal_aux_device_dump().
+ */
+vxge_hal_status_e vxge_hal_aux_about_read(vxge_hal_device_h devh, int bufsize,
+    char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_driver_config_read - Read Driver configuration.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read driver configuration,
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ *
+ * See also: vxge_hal_aux_device_config_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_driver_config_read(int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_pci_config_read - Retrieve and format PCI Configuration
+ * info.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Retrieve about info (using vxge_hal_mgmt_pci_config()) and sprintf it
+ * into the provided @retbuf.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ *
+ * See also: vxge_hal_mgmt_pci_config(), vxge_hal_aux_device_dump().
+ */
+vxge_hal_status_e
+vxge_hal_aux_pci_config_read(vxge_hal_device_h devh,
+    int bufsize,
+    char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_device_config_read - Read device configuration.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device configuration,
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ *
+ * See also: vxge_hal_aux_driver_config_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_device_config_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_bar0_read - Read and format X3100 BAR0 register.
+ * @devh: HAL device handle.
+ * @offset: Register offset in the BAR0 space.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read X3100 register from BAR0 space. The result is formatted as an
+ * ascii string.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ *
+ * See also: vxge_hal_mgmt_reg_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_bar0_read(vxge_hal_device_h devh,
+    unsigned int offset, int bufsize, char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_bar1_read - Read and format X3100 BAR1 register.
+ * @devh: HAL device handle.
+ * @offset: Register offset in the BAR1 space.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read X3100 register from BAR1 space. The result is formatted as ascii string
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_bar1_read(vxge_hal_device_h devh,
+    unsigned int offset, int bufsize, char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_bar0_write - Write BAR0 register.
+ * @devh: HAL device handle.
+ * @offset: Register offset in the BAR0 space.
+ * @value: Regsister value (to write).
+ *
+ * Write BAR0 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ *
+ * See also: vxge_hal_mgmt_reg_write().
+ */
+vxge_hal_status_e
+vxge_hal_aux_bar0_write(vxge_hal_device_h devh,
+    unsigned int offset, u64 value);
+
+/*
+ * vxge_hal_aux_stats_vpath_hw_read - Read vpath hardware statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath hardware statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_hw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_hw_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_stats_device_hw_read - Read device hardware statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device hardware statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_hw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_hw_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_fifo_read - Read vpath fifo software statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath fifo software statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_fifo_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_fifo_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_ring_read - Read vpath ring software statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath ring software statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_ring_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_ring_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize);
+
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_err_read - Read vpath err software statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath err software statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_err_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_err_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_read - Read vpath soft statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device hardware statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize);
+
+/*
+ * vxge_hal_aux_stats_device_sw_read - Read device software statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device software statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_sw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_sw_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_stats_device_sw_err_read - Read device software error statistics
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device software error statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_sw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_sw_err_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_stats_device_read - Read device statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_stats_xpak_read - Read device xpak statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device xpak statistics. This is valid for function 0 device only
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_xpak_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_stats_mrpcim_read - Read device mrpcim statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read mrpcim statistics. This is valid for function 0 device only
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_mrpcim_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize);
+
+/*
+ * vxge_hal_aux_vpath_ring_dump - Dump vpath ring.
+ * @vpath_handle: Vpath handle.
+ *
+ * Dump vpath ring.
+ */
+vxge_hal_status_e
+vxge_hal_aux_vpath_ring_dump(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_aux_vpath_fifo_dump - Dump vpath fifo.
+ * @vpath_handle: Vpath handle.
+ *
+ * Dump vpath fifo.
+ */
+vxge_hal_status_e
+vxge_hal_aux_vpath_fifo_dump(vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_aux_device_dump - Dump driver "about" info and device state.
+ * @devh: HAL device handle.
+ *
+ * Dump driver & device "about" info and device state,
+ * including all BAR0 registers, hardware and software statistics, PCI
+ * configuration space.
+ */
+vxge_hal_status_e vxge_hal_aux_device_dump(vxge_hal_device_h devh);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_MGMTAUX_H */
diff --git a/sys/dev/vxge/include/vxgehal-stats.h b/sys/dev/vxge/include/vxgehal-stats.h
new file mode 100644
index 000000000000..3697471fc929
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-stats.h
@@ -0,0 +1,2352 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_STATS_H
+#define	VXGE_HAL_STATS_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	VXGE_HAL_STATS_OP_READ						0
+#define	VXGE_HAL_STATS_OP_CLEAR_STAT					1
+#define	VXGE_HAL_STATS_OP_CLEAR_ALL_VPATH_STATS				2
+#define	VXGE_HAL_STATS_OP_CLEAR_ALL_STATS_OF_LOC			2
+#define	VXGE_HAL_STATS_OP_CLEAR_ALL_STATS				3
+
+#define	VXGE_HAL_STATS_LOC_VPATH(n)					n
+#define	VXGE_HAL_STATS_LOC_AGGR						17
+#define	VXGE_HAL_STATS_LOC_PORT						17
+
+#define	VXGE_HAL_STATS_AGGRn_TX_FRMS_OFFSET(n)		    ((0x720+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_TX_FRMS(bits)		    bits
+
+#define	VXGE_HAL_STATS_AGGRn_TX_DATA_OCTETS_OFFSET(n)	    ((0x728+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_TX_DATA_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_TX_MCAST_FRMS_OFFSET(n)	    ((0x730+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_TX_MCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_TX_BCAST_FRMS_OFFSET(n)	    ((0x738+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_TX_BCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_TX_DISCARDED_FRMS_OFFSET(n)    ((0x740+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_TX_DISCARDED_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_AGGRn_TX_ERRORED_FRMS_OFFSET(n)	    ((0x748+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_TX_ERRORED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_FRMS_OFFSET(n)		    ((0x750+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_FRMS(bits)		    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_DATA_OCTETS_OFFSET(n)	    ((0x758+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_DATA_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_MCAST_FRMS_OFFSET(n)	    ((0x760+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_MCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_BCAST_FRMS_OFFSET(n)	    ((0x768+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_BCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_DISCARDED_FRMS_OFFSET(n)    ((0x770+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_DISCARDED_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_ERRORED_FRMS_OFFSET(n)	    ((0x778+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_ERRORED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_AGGRn_RX_U_SLOW_PROTO_FRMS_OFFSET(n) ((0x780+(104*n))>>3)
+#define	VXGE_HAL_STATS_GET_AGGRn_RX_U_SLOW_PROTO_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM0_OFFSET	    (0x7f0>>3)
+#define	VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM0(bits)    bits
+
+#define	VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM1_OFFSET	    (0x7f8>>3)
+#define	VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM1(bits)    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(n)	    ((0x000+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_TTL_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_TTL_OCTETS_OFFSET(n)	    ((0x008+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_TTL_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_DATA_OCTETS_OFFSET(n)	    ((0x010+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_DATA_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_MCAST_FRMS_OFFSET(n)	    ((0x018+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_MCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_BCAST_FRMS_OFFSET(n)	    ((0x020+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_BCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_UCAST_FRMS_OFFSET(n)	    ((0x028+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_UCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_TAGGED_FRMS_OFFSET(n)	    ((0x030+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_TAGGED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_VLD_IP_OFFSET(n)	    ((0x038+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_VLD_IP_OCTETS_OFFSET(n)	    ((0x040+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_ICMP_OFFSET(n)		    ((0x048+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_ICMP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_TCP_OFFSET(n)		    ((0x050+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_TCP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_RST_TCP_OFFSET(n)	    ((0x058+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_RST_TCP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_UDP_OFFSET(n)		    ((0x060+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_UDP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_UNKNOWN_PROTOCOL_OFFSET(n)  ((0x068+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_UNKNOWN_PROTOCOL(bits)  bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_PARSE_ERROR_OFFSET(n)	    ((0x068+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_PARSE_ERROR(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_PAUSE_CTRL_FRMS_OFFSET(n)   ((0x070+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_PAUSE_CTRL_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_LACPDU_FRMS_OFFSET(n)	    ((0x078+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_LACPDU_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_MRKR_PDU_FRMS_OFFSET(n)	   ((0x078+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_MRKR_PDU_FRMS(bits)	   bits
+
+#define	VXGE_HAL_STATS_PORTn_TX_MRKR_RESP_PDU_FRMS_OFFSET(n)\
+							    ((0x080+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_MRKR_RESP_PDU_FRMS(bits) bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_TX_DROP_IP_OFFSET(n)	    ((0x080+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_DROP_IP(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR1_MATCH_OFFSET(n) ((0x088+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR1_MATCH(bits) bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR2_MATCH_OFFSET(n) ((0x088+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR2_MATCH(bits) bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_TX_XGMII_COL1_MATCH_OFFSET(n)  ((0x090+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL1_MATCH(bits)  bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_TX_XGMII_COL2_MATCH_OFFSET(n)  ((0x090+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL2_MATCH(bits)  bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_TX_DROP_FRMS_OFFSET(n)	    ((0x098+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_DROP_FRMS(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_TX_ANY_ERR_FRMS_OFFSET(n)	    ((0x098+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_TX_ANY_ERR_FRMS(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_FRMS_OFFSET(n)	    ((0x0a0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_VLD_FRMS_OFFSET(n)	    ((0x0a8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_VLD_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_OFFLOAD_FRMS_OFFSET(n)	    ((0x0b0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_OCTETS_OFFSET(n)	    ((0x0b8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_DATA_OCTETS_OFFSET(n)	    ((0x0c0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_DATA_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_OFFLOAD_OCTETS_OFFSET(n)    ((0x0c8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_OCTETS(bits)    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_VLD_MCAST_FRMS_OFFSET(n)    ((0x0d0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_VLD_MCAST_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_VLD_BCAST_FRMS_OFFSET(n)    ((0x0d8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_VLD_BCAST_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_ACC_UCAST_FRMS_OFFSET(n)    ((0x0e0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ACC_UCAST_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_ACC_NUCAST_FRMS_OFFSET(n)   ((0x0e8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ACC_NUCAST_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TAGGED_FRMS_OFFSET(n)	    ((0x0f0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TAGGED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_LONG_FRMS_OFFSET(n)	    ((0x0f8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_LONG_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_USIZED_FRMS_OFFSET(n)	    ((0x100+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_USIZED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_OSIZED_FRMS_OFFSET(n)	    ((0x108+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_OSIZED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_FRAG_FRMS_OFFSET(n)	    ((0x110+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_FRAG_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_JABBER_FRMS_OFFSET(n)	    ((0x118+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_JABBER_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_64_FRMS_OFFSET(n)	    ((0x120+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_64_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_65_127_FRMS_OFFSET(n)   ((0x128+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_65_127_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_128_255_FRMS_OFFSET(n)  ((0x130+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_128_255_FRMS(bits)  bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_256_511_FRMS_OFFSET(n)  ((0x138+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_256_511_FRMS(bits)  bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_512_1023_FRMS_OFFSET(n) ((0x140+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_512_1023_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_1024_1518_FRMS_OFFSET(n)\
+							    ((0x148+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_1024_1518_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_1519_4095_FRMS_OFFSET(n)\
+							    ((0x150+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_1519_4095_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_4096_81915_FRMS_OFFSET(n)\
+							    ((0x158+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_4096_8191_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_8192_MAX_FRMS_OFFSET(n) ((0x160+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_8192_MAX_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TTL_GT_MAX_FRMS_OFFSET(n)   ((0x168+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TTL_GT_MAX_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_IP_OFFSET(n)		    ((0x170+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_IP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_ACC_IP_OFFSET(n)	    ((0x178+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ACC_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_IP_OCTETS_OFFSET(n)	    ((0x180+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_IP_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_ERR_IP_OFFSET(n)	    ((0x188+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ERR_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_ICMP_OFFSET(n)		    ((0x190+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ICMP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_TCP_OFFSET(n)		    ((0x198+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TCP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_UDP_OFFSET(n)		    ((0x1a0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_UDP(bits)		    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_ERR_TCP_OFFSET(n)	    ((0x1a8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ERR_TCP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_PAUSE_CNT_OFFSET(n)	    ((0x1b0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CNT(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_PAUSE_CTRL_FRMS_OFFSET(n)   ((0x1b8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CTRL_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_UNSUP_CTRL_FRMS_OFFSET(n)   ((0x1c0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_UNSUP_CTRL_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_FCS_ERR_FRMS_OFFSET(n)	    ((0x1c8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_FCS_ERR_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_IN_RNG_LEN_ERR_FRMS_OFFSET(n)\
+							    ((0x1d0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_IN_RNG_LEN_ERR_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_OUT_RNG_LEN_ERR_FRMS_OFFSET(n)\
+							    ((0x1d8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_OUT_RNG_LEN_ERR_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_DROP_FRMS_OFFSET(n)	    ((0x1e0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_DROP_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_DISCARDED_FRMS_OFFSET(n)    ((0x1e8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_DISCARDED_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_DROP_IP_OFFSET(n)	    ((0x1f0+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_DROP_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_DRP_UDP_OFFSET(n)	    ((0x1f8+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_DRP_UDP(bits)	    bits
+
+#define	VXGE_HAL_STATS_PORTn_RX_LACPDU_FRMS_OFFSET(n)	    ((0x200+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_LACPDU_FRMS(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_MRKR_PDU_FRMS_OFFSET(n)	    ((0x200+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_MRKR_PDU_FRMS(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_MRKR_RESP_PDU_FRMS_OFFSET(n)\
+							    ((0x208+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_MRKR_RESP_PDU_FRMS(bits) bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_UNKNOWN_PDU_FRMS_OFFSET(n)  ((0x208+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_UNKNOWN_PDU_FRMS(bits)  bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_ILLEGAL_PDU_FRMS_OFFSET(n)  ((0x210+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_ILLEGAL_PDU_FRMS(bits)  bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_FCS_DISCARD_OFFSET(n)	    ((0x210+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_FCS_DISCARD(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_LEN_DISCARD_OFFSET(n)	    ((0x218+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_LEN_DISCARD(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_SWITCH_DISCARD_OFFSET(n)    ((0x218+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_SWITCH_DISCARD(bits)    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_L2_MGMT_DISCARD_OFFSET(n)   ((0x220+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_L2_MGMT_DISCARD(bits)   bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_RPA_DISCARD_OFFSET(n)	    ((0x220+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_RPA_DISCARD(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_TRASH_DISCARD_OFFSET(n)	    ((0x228+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_TRASH_DISCARD(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_RTS_DISCARD_OFFSET(n)	    ((0x228+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_RTS_DISCARD(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_RED_DISCARD_OFFSET(n)	    ((0x230+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_RED_DISCARD(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_BUFF_FULL_DISCARD_OFFSET(n) ((0x230+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_BUFF_FULL_DISCARD(bits) bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_DATA_ERR_CNT_OFFSET(n)\
+							    ((0x238+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_DATA_ERR_CNT(bits) bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_CTRL_ERR_CNT_OFFSET(n)\
+							    ((0x238+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CTRL_ERR_CNT(bits) bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_ERR_SYM_OFFSET(n)	    ((0x240+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_ERR_SYM(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR1_MATCH_OFFSET(n) ((0x240+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR1_MATCH(bits) bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR2_MATCH_OFFSET(n) ((0x248+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR2_MATCH(bits) bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_COL1_MATCH_OFFSET(n)  ((0x248+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL1_MATCH(bits)  bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_XGMII_COL2_MATCH_OFFSET(n)  ((0x250+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL2_MATCH(bits)  bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_LOCAL_FAULT_OFFSET(n)	    ((0x250+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_LOCAL_FAULT(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_PORTn_RX_REMOTE_FAULT_OFFSET(n)	    ((0x258+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_REMOTE_FAULT(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_PORTn_RX_JETTISON_OFFSET(n)	    ((0x258+(608*n))>>3)
+#define	VXGE_HAL_STATS_GET_PORTn_RX_JETTISON(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_VPATH_TX_TTL_ETH_FRMS_OFFSET	    (0x000>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_TTL_ETH_OCTETS_OFFSET	    (0x008>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_OCTETS(bits)    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_DATA_OCTETS_OFFSET	    (0x010>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_DATA_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_MCAST_FRMS_OFFSET	    (0x018>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_MCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_BCAST_FRMS_OFFSET	    (0x020>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_BCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_UCAST_FRMS_OFFSET	    (0x028>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_UCAST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_TAGGED_FRMS_OFFSET	    (0x030>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_TAGGED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_VLD_IP_OFFSET		    (0x038>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_VLD_IP_OCTETS_OFFSET	    (0x040>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_ICMP_OFFSET		    (0x048>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_ICMP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_TCP_OFFSET		    (0x050>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_TCP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_RST_TCP_OFFSET		    (0x058>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_RST_TCP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_UDP_OFFSET		    (0x060>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_UDP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_LOST_IP_OFFSET		    (0x068>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_UNKNOWN_PROTOCOL_OFFSET	    (0x068>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_UNKNOWN_PROTOCOL(bits)  bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_PARSE_ERROR_OFFSET	    (0x070>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_PARSE_ERROR(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_TCP_OFFLOAD_OFFSET	    (0x078>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_TCP_OFFLOAD(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_RETX_TCP_OFFLOAD_OFFSET	    (0x080>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_RETX_TCP_OFFLOAD(bits)  bits
+
+#define	VXGE_HAL_STATS_VPATH_TX_LOST_IP_OFFLOAD_OFFSET	    (0x088>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP_OFFLOAD(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_ETH_FRMS_OFFSET	    (0x090>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_VLD_FRMS_OFFSET		    (0x098>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_VLD_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_OFFLOAD_FRMS_OFFSET	    (0x0a0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_ETH_OCTETS_OFFSET	    (0x0a8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_OCTETS(bits)    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_DATA_OCTETS_OFFSET	    (0x0b0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_DATA_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_OFFLOAD_OCTETS_OFFSET	    (0x0b8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_OCTETS(bits)    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_VLD_MCAST_FRMS_OFFSET	    (0x0c0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_VLD_MCAST_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_VLD_BCAST_FRMS_OFFSET	    (0x0c8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_VLD_BCAST_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_ACC_UCAST_FRMS_OFFSET	    (0x0d0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_ACC_UCAST_FRMS(bits)    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_ACC_NUCAST_FRMS_OFFSET	    (0x0d8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_ACC_NUCAST_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TAGGED_FRMS_OFFSET	    (0x0e0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TAGGED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_LONG_FRMS_OFFSET	    (0x0e8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_LONG_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_USIZED_FRMS_OFFSET	    (0x0f0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_USIZED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_OSIZED_FRMS_OFFSET	    (0x0f8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_OSIZED_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_FRAG_FRMS_OFFSET	    (0x100>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_FRAG_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_JABBER_FRMS_OFFSET	    (0x108>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_JABBER_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_64_FRMS_OFFSET	    (0x110>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_64_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_65_127_FRMS_OFFSET	    (0x118>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_65_127_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_128_255_FRMS_OFFSET	    (0x120>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_128_255_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_256_511_FRMS_OFFSET	    (0x128>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_256_511_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_512_1023_FRMS_OFFSET    (0x130>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_512_1023_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_1024_1518_FRMS_OFFSET   (0x138>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_1024_1518_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_1519_4095_FRMS_OFFSET   (0x140>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_1519_4095_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_4096_8191_FRMS_OFFSET   (0x148>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_4096_8191_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_8192_MAX_FRMS_OFFSET    (0x150>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_8192_MAX_FRMS(bits) bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TTL_GT_MAX_FRMS_OFFSET	    (0x158>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TTL_GT_MAX_FRMS(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_IP_OFFSET		    (0x160>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_IP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_ACC_IP_OFFSET		    (0x168>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_ACC_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_IP_OCTETS_OFFSET	    (0x170>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_IP_OCTETS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_ERR_IP_OFFSET		    (0x178>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_ERR_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_ICMP_OFFSET		    (0x180>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_ICMP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_TCP_OFFSET		    (0x188>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_TCP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_UDP_OFFSET		    (0x190>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_UDP(bits)		    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_ERR_TCP_OFFSET		    (0x198>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_ERR_TCP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_LOST_FRMS_OFFSET	    (0x1a0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_LOST_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_LOST_IP_OFFSET		    (0x1a8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_LOST_IP_OFFLOAD_OFFSET	    (0x1b0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP_OFFLOAD(bits)   bits
+
+#define	VXGE_HAL_STATS_VPATH_RX_QUEUE_FULL_DISCARD_OFFSET   (0x1b8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_QUEUE_FULL_DISCARD(bits) bVAL16(bits, 8)
+
+#define	VXGE_HAL_STATS_VPATH_RX_RED_DISCARD_OFFSET	    (0x1b8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_RED_DISCARD(bits)	    bVAL16(bits, 24)
+
+#define	VXGE_HAL_STATS_VPATH_RX_SLEEP_DISCARD_OFFSET	    (0x1b8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_SLEEP_DISCARD(bits)	    bVAL16(bits, 42)
+
+#define	VXGE_HAL_STATS_VPATH_RX_MPA_OK_FRMS_OFFSET	    (0x1c0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_RX_MPA_OK_FRMS(bits)	    bits
+
+#define	VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET	    (0x1d0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM0(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM1_OFFSET	    (0x1d0>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM1(bits)	    bVAL32(bits, 32)
+
+#define	VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET	    (0x1d8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM2(bits)	    bVAL32(bits, 0)
+
+#define	VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM3_OFFSET	    (0x1d8>>3)
+#define	VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM3(bits)	    bVAL32(bits, 32)
+
+/*
+ * struct vxge_hal_xmac_aggr_stats_t - Per-Aggregator XMAC Statistics
+ *
+ * @tx_frms: Count of data frames transmitted on this Aggregator on all
+ *		its Aggregation ports. Does not include LACPDUs or Marker PDUs.
+ *		However, does include frames discarded by the Distribution
+ *		function.
+ * @tx_data_octets: Count of data and padding octets of frames transmitted
+ *		on this Aggregator on all its Aggregation ports.Does not include
+ *		octets of LACPDUs or Marker PDUs. However,does include octets of
+ *		frames discarded by the Distribution function.
+ * @tx_mcast_frms: Count of data frames transmitted (to a group destination
+ *		address other than the broadcast address) on this Aggregator on
+ *		all its Aggregation ports. Does not include LACPDUs or Marker
+ *		PDUs. However, does include frames discarded by the Distribution
+ *		function.
+ * @tx_bcast_frms: Count of broadcast data frames transmitted on this Aggregator
+ *		on all its Aggregation ports. Does not include LACPDUs or Marker
+ *		PDUs. However, does include frames discarded by the Distribution
+ *		function.
+ * @tx_discarded_frms: Count of data frames to be transmitted on this Aggregator
+ *		that are discarded by the Distribution function.This occurs when
+ *		conversation are allocated to different ports and have to be
+ *		flushed on old ports
+ * @tx_errored_frms: Count of data frames transmitted on this Aggregator that
+ *		experience transmission errors on its Aggregation ports.
+ * @rx_frms: Count of data frames received on this Aggregator on all its
+ *		Aggregation ports. Does not include LACPDUs or Marker PDUs.
+ *		Also, does not include frames discarded by the Collection
+ *		function.
+ * @rx_data_octets: Count of data and padding octets of frames received on this
+ *		Aggregator on all its Aggregation ports. Does not include octets
+ *		of LACPDUs or Marker PDUs.Also,does not include octets of frames
+ *		discarded by the Collection function.
+ * @rx_mcast_frms: Count of data frames received (from a group destination
+ *		address other than the broadcast address) on this Aggregator on
+ *		all its Aggregation ports. Does not include LACPDUs or Marker
+ *		PDUs. Also, does not include frames discarded by the Collection
+ *		function.
+ * @rx_bcast_frms: Count of broadcast data frames received on this Aggregator on
+ *		all its Aggregation ports. Does not include LACPDUs or Marker
+ *		PDUs. Also, does not include frames discarded by the Collection
+ *		function.
+ * @rx_discarded_frms: Count of data frames received on this Aggregator that are
+ *		discarded by the Collection function because the Collection
+ *		function was disabled on the port which the frames are received.
+ * @rx_errored_frms: Count of data frames received on this Aggregator that are
+ *		discarded by its Aggregation ports, or are discarded by the
+ *		Collection function of the Aggregator, or that are discarded by
+ *		the Aggregator due to detection of an illegal Slow Protocols PDU
+ * @rx_unknown_slow_proto_frms: Count of data frames received on this Aggregator
+ *		that are discarded by its Aggregation ports due to detection of
+ *		an unknown Slow Protocols PDU.
+ *
+ * Per aggregator XMAC RX statistics.
+ */
+#pragma pack(1)
+typedef struct vxge_hal_xmac_aggr_stats_t {
+/* 0x000 */		u64	tx_frms;
+/* 0x008 */		u64	tx_data_octets;
+/* 0x010 */		u64	tx_mcast_frms;
+/* 0x018 */		u64	tx_bcast_frms;
+/* 0x020 */		u64	tx_discarded_frms;
+/* 0x028 */		u64	tx_errored_frms;
+/* 0x030 */		u64	rx_frms;
+/* 0x038 */		u64	rx_data_octets;
+/* 0x040 */		u64	rx_mcast_frms;
+/* 0x048 */		u64	rx_bcast_frms;
+/* 0x050 */		u64	rx_discarded_frms;
+/* 0x058 */		u64	rx_errored_frms;
+/* 0x060 */		u64	rx_unknown_slow_proto_frms;
+} vxge_hal_xmac_aggr_stats_t;
+
+#pragma pack()
+
+/*
+ * struct vxge_hal_xmac_port_stats_t - XMAC Port Statistics
+ *
+ * @tx_ttl_frms: Count of successfully transmitted MAC frames
+ * @tx_ttl_octets: Count of total octets of transmitted frames, not including
+ *	   framing characters (i.e. less framing bits). To determine the
+ *	   total octets of transmitted frames, including framing characters,
+ *	   multiply PORTn_TX_TTL_FRMS by 8 and add it to this stat (unless
+ *	   otherwise configured, this stat only counts frames that have
+ *	   8 bytes of preamble for each frame). This stat can be configured
+ *	   (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything
+ *	   including the preamble octets.
+ * @tx_data_octets: Count of data and padding octets of successfully transmitted
+ *	   frames.
+ * @tx_mcast_frms: Count of successfully transmitted frames to a group address
+ *	   other than the broadcast address.
+ * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast
+ *	   group address.
+ * @tx_ucast_frms: Count of transmitted frames containing a unicast address.
+ *	   Includes discarded frames that are not sent to the network.
+ * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag.
+ * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network.
+ * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that
+ *	   are passed to the network.
+ * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent
+ *	   due to problems within ICMP.
+ * @tx_tcp: Count of transmitted TCP segments. Does not include segments
+ *	   containing retransmitted octets.
+ * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag.
+ * @tx_udp: Count of transmitted UDP datagrams.
+ * @tx_parse_error: Increments when the TPA is unable to parse a packet. This
+ *	   generally occurs when a packet is corrupt somehow, including
+ *	   packets that have IP version mismatches, invalid Layer 2 control
+ *	   fields, etc. L3/L4 checksums are not offloaded, but the packet
+ *	   is still be transmitted.
+ * @tx_unknown_protocol: Increments when the TPA encounters an unknown
+ *	   protocol, such as a new IPv6 extension header, or an unsupported
+ *	   Routing Type. The packet still has a checksum calculated but it
+ *	   may be incorrect.
+ * @tx_pause_ctrl_frms: Count of MAC PAUSE control frames that are transmitted.
+ *	   Since, the only control frames supported by this device are
+ *	   PAUSE frames, this register is a count of all transmitted MAC
+ *	   control frames.
+ * @tx_marker_pdu_frms: Count of Marker PDUs transmitted on this Aggr port
+ * @tx_lacpdu_frms: Count of LACPDUs transmitted on this Aggregation port.
+ * @tx_drop_ip: Count of transmitted IP datagrams that could not be passed to
+ *	   the network. Increments because of: 1) An internal processing error
+ *	   (such as an uncorrectable ECC error). 2) A frame parsing error
+ *	   during IP checksum calculation.
+ * @tx_marker_resp_pdu_frms: Count of Marker Response PDUs transmitted on this
+ *	   Aggregation port.
+ * @tx_xgmii_char2_match: Maintains a count of the number of transmitted XGMII
+ *	   characters that match a pattern that is programmable through
+ *	   register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern
+ *	   is set to /T/ (i.e. the terminate character), thus the statistic
+ *	   tracks the number of transmitted Terminate characters.
+ * @tx_xgmii_char1_match: Maintains a count of the number of transmitted XGMII
+ *	   characters that match a pattern that is programmable through
+ *	   register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern
+ *	   is set to /S/ (i.e. the start character), thus the statistic tracks
+ *	   the number of transmitted Start characters.
+ * @tx_xgmii_column2_match: Maintains a count of the number of transmitted XGMII
+ *	   columns that match a pattern that is programmable through register
+ *	   XMAC_STATS_TX_XGMII_COLUMN2_PORTn. By default, the pattern is set
+ *	   to 4 x /E/ (i.e. a column containing all error characters), thus
+ *	   the statistic tracks the number of Error columns transmitted at
+ *	   any time. If XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is
+ *	   set to 1, then this stat increments when COLUMN2 is found within
+ *	   'n' clocks after COLUMN1. Here, 'n' is defined by
+ *	   XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set
+ *	   to 0, then it means to search anywhere for COLUMN2).
+ * @tx_xgmii_column1_match: Maintains a count of the number of transmitted XGMII
+ *	   columns that match a pattern that is programmable through register
+ *	   XMAC_STATS_TX_XGMII_COLUMN1_PORTn. By default, the pattern is set
+ *	   to 4 x /I/ (i.e. a column containing all idle characters), thus the
+ *	   statistic tracks the number of transmitted Idle columns.
+ * @unused1: Reserved
+ * @tx_any_err_frms: Count of transmitted frames containing any error that
+ *	   prevents them from being passed to the network. Increments if
+ *	   there is an ECC while reading the frame out of the transmit
+ *	   buffer. Also increments if the transmit protocol assist (TPA)
+ *	   block determines that the frame should not be sent.
+ * @tx_drop_frms: Count of frames that could not be sent for no other reason
+ *	   than internal MAC processing. Increments once whenever the
+ *	   transmit buffer is flushed (due to an ECC error on a memory
+ *	   descriptor).
+ * @rx_ttl_frms: Count of total received MAC frames, including frames received
+ *	   with frame-too-long, FCS, or length errors. This stat can be
+ *	   configured (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count
+ *	   everything, even "frames" as small one byte of preamble.
+ * @rx_vld_frms: Count of successfully received MAC frames. Does not include
+ *	   frames received with frame-too-long, FCS, or length errors.
+ * @rx_offload_frms: Count of offloaded received frames that are passed to
+ *	   the host.
+ * @rx_ttl_octets: Count of total octets of received frames, not including
+ *	   framing characters (i.e. less framing bits). To determine the
+ *	   total octets of received frames, including framing characters,
+ *	   multiply PORTn_RX_TTL_FRMS by 8 and add it to this stat (unless
+ *	   otherwise configured, this stat only counts frames that have 8
+ *	   bytes of preamble for each frame). This stat can be configured
+ *	   (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything,
+ *	   even the preamble octets of "frames" as small one byte of preamble.
+ * @rx_data_octets: Count of data and padding octets of successfully received
+ *	   frames. Does not include frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_offload_octets: Count of total octets, not including framing
+ *	   characters, of offloaded received frames that are passed
+ *	   to the host.
+ * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a
+ *		 nonbroadcast group address. Does not include frames received
+ *	   with frame-too-long, FCS, or length errors.
+ * @rx_vld_bcast_frms: Count of successfully received MAC frames containing
+ *	   the broadcast group address. Does not include frames received
+ *	   with frame-too-long, FCS, or length errors.
+ * @rx_accepted_ucast_frms: Count of successfully received frames containing
+ *	   a unicast address. Only includes frames that are passed to
+ *	   the system.
+ * @rx_accepted_nucast_frms: Count of successfully received frames containing
+ *	   a non-unicast (broadcast or multicast) address. Only includes
+ *	   frames that are passed to the system. Could include, for instance,
+ *	   non-unicast frames that contain FCS errors if the MAC_ERROR_CFG
+ *	   register is set to pass FCS-errored frames to the host.
+ * @rx_tagged_frms: Count of received frames containing a VLAN tag.
+ * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN
+ *	   + 18 bytes (+ 22 bytes if VLAN-tagged).
+ * @rx_usized_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) less than 64 octets, that are otherwise well-formed.
+ *	   In other words, counts runts.
+ * @rx_osized_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) more than 1518 octets, that are otherwise
+ *	   well-formed. Note: If register XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING
+ *	   is set to 1, then "more than 1518 octets" becomes "more than 1518
+ *	   (1522 if VLAN-tagged) octets".
+ * @rx_frag_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) less than 64 octets that had bad FCS. In other
+ *	   words, counts fragments.
+ * @rx_jabber_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) more than 1518 octets that had bad FCS. In other
+ *	   words, counts jabbers. Note: If register
+ *	   XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING is set to 1, then "more than
+ *	   1518 octets" becomes "more than 1518 (1522 if VLAN-tagged) octets".
+ * @rx_ttl_64_frms: Count of total received MAC frames with length (including
+ *	   FCS, but not framing bits) of exactly 64 octets. Includes frames
+ *	   received with frame-too-long, FCS, or length errors.
+ * @rx_ttl_65_127_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 65 and 127
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_128_255_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 128 and 255
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_256_511_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 256 and 511
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_512_1023_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 512 and 1023
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 1024 and 1518
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 1519 and 4095
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 4096 and 8191
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_8192_max_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 8192 and
+ *	   RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received
+ *	   with frame-too-long, FCS, or length errors.
+ * @rx_ttl_gt_max_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) exceeding
+ *	   RX_MAX_PYLD_LEN+18 (+22 bytes if VLAN-tagged) octets inclusive.
+ *	   Includes frames received with frame-too-long, FCS, or length errors.
+ * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams.
+ * @rx_accepted_ip: Count of received IP datagrams that are passed to the system
+ * @rx_ip_octets: Count of number of octets in received IP datagrams. Includes
+ *	   errored IP datagrams.
+ * @rx_err_ip:	Count of received IP datagrams containing errors. For example,
+ *	   bad IP checksum.
+ * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages.
+ * @rx_tcp: Count of received TCP segments. Includes errored TCP segments.
+ *	   Note: This stat contains a count of all received TCP segments,
+ *	   regardless of whether or not they pertain to an established
+ *	   connection.
+ * @rx_udp: Count of received UDP datagrams.
+ * @rx_err_tcp: Count of received TCP segments containing errors. For example,
+ *	   bad TCP checksum.
+ * @rx_pause_count: Count of number of pause quanta that the MAC has been in
+ *	   the paused state. Recall, one pause quantum equates to 512
+ *	   bit times.
+ * @rx_pause_ctrl_frms: Count of received MAC PAUSE control frames.
+ * @rx_unsup_ctrl_frms: Count of received MAC control frames that do not
+ *	   contain the PAUSE opcode. The sum of RX_PAUSE_CTRL_FRMS and
+ *	   this register is a count of all received MAC control frames.
+ *	   Note: This stat may be configured to count all layer 2 errors
+ *	   (i.e. length errors and FCS errors).
+ * @rx_fcs_err_frms: Count of received MAC frames that do not pass FCS. Does
+ *	   not include frames received with frame-too-long or
+ *	   frame-too-short error.
+ * @rx_in_rng_len_err_frms: Count of received frames with a length/type field
+ *	   value between 46 (42 for VLAN-tagged frames) and 1500 (also 1500
+ *	   for VLAN-tagged frames), inclusive, that does not match the
+ *	   number of data octets (including pad) received. Also contains
+ *	   a count of received frames with a length/type field less than
+ *	   46 (42 for VLAN-tagged frames) and the number of data octets
+ *	   (including pad) received is greater than 46 (42 for VLAN-tagged
+ *	   frames).
+ * @rx_out_rng_len_err_frms:  Count of received frames with length/type field
+ *	   between 1501 and 1535 decimal, inclusive.
+ * @rx_drop_frms: Count of received frames that could not be passed to the host.
+ *	   See PORTn_RX_L2_MGMT_DISCARD, PORTn_RX_RPA_DISCARD,
+ *	   PORTn_RX_TRASH_DISCARD, PORTn_RX_RTS_DISCARD, PORTn_RX_RED_DISCARD
+ *	   for a list of reasons. Because the RMAC drops one frame at a time,
+ *	   this stat also indicates the number of drop events.
+ * @rx_discarded_frms: Count of received frames containing error that prevents
+ *	   them from being passed to the system. See PORTn_RX_FCS_DISCARD,
+ *	   PORTn_RX_LEN_DISCARD, and PORTn_RX_SWITCH_DISCARD for a list of
+ *	   reasons.
+ * @rx_drop_ip: Count of received IP datagrams that could not be passed to the
+ *	   host. See PORTn_RX_DROP_FRMS for a list of reasons.
+ * @rx_drop_udp: Count of received UDP datagrams that are not delivered to the
+ *	   host. See PORTn_RX_DROP_FRMS for a list of reasons.
+ * @rx_marker_pdu_frms: Count of valid Marker PDUs received on this Aggregation
+ *	   port.
+ * @rx_lacpdu_frms: Count of valid LACPDUs received on this Aggregation port.
+ * @rx_unknown_pdu_frms: Count of received frames (on this Aggregation port)
+ *	   that carry the Slow Protocols EtherType, but contain an unknown
+ *	   PDU. Or frames that contain the Slow Protocols group MAC address,
+ *	   but do not carry the Slow Protocols EtherType.
+ * @rx_marker_resp_pdu_frms: Count of valid Marker Response PDUs received on
+ *	   this Aggregation port.
+ * @rx_fcs_discard: Count of received frames that are discarded because the
+ *	   FCS check failed.
+ * @rx_illegal_pdu_frms: Count of received frames (on this Aggregation port)
+ *	   that carry the Slow Protocols EtherType, but contain a badly
+ *	   formed PDU. Or frames that carry the Slow Protocols EtherType,
+ *	   but contain an illegal value of Protocol Subtype.
+ * @rx_switch_discard: Count of received frames that are discarded by the
+ *	   internal switch because they did not have an entry in the
+ *	   Filtering Database. This includes frames that had an invalid
+ *	   destination MAC address or VLAN ID. It also includes frames are
+ *	   discarded because they did not satisfy the length requirements
+ *	   of the target VPATH.
+ * @rx_len_discard: Count of received frames that are discarded because of an
+ *	   invalid frame length (includes fragments, oversized frames and
+ *	   mismatch between frame length and length/type field). This stat
+ *	   can be configured (see XMAC_STATS_GLOBAL_CFG.LEN_DISCARD_HANDLING).
+ * @rx_rpa_discard: Count of received frames that were discarded because the
+ *	   receive protocol assist (RPA) discovered and error in the frame
+ *	   or was unable to parse the frame.
+ * @rx_l2_mgmt_discard: Count of Layer 2 management frames (eg. pause frames,
+ *	   Link Aggregation Control Protocol (LACP) frames, etc.) that are
+ *	   discarded.
+ * @rx_rts_discard: Count of received frames that are discarded by the receive
+ *	   traffic steering (RTS) logic. Includes those frame discarded
+ *	   because the SSC response contradicted the switch table, because
+ *	   the SSC timed out, or because the target queue could not fit the
+ *	   frame.
+ * @rx_trash_discard: Count of received frames that are discarded because
+ *	   receive traffic steering (RTS) steered the frame to the trash
+ *	   queue.
+ * @rx_buff_full_discard: Count of received frames that are discarded because
+ *	   internal buffers are full. Includes frames discarded because the
+ *	   RTS logic is waiting for an SSC lookup that has no timeout bound.
+ *	   Also, includes frames that are dropped because the MAC2FAU buffer
+ *	   is nearly full -- this can happen if the external receive buffer
+ *	   is full and the receive path is backing up.
+ * @rx_red_discard: Count of received frames that are discarded because of RED
+ *	   (Random Early Discard).
+ * @rx_xgmii_ctrl_err_cnt: Maintains a count of unexpected or misplaced control
+ *	   characters occuring between times of normal data transmission
+ *	   (i.e. not included in RX_XGMII_DATA_ERR_CNT). This counter is
+ *	   incremented when either -
+ *	   1) The Reconciliation Sublayer (RS) is expecting one control
+ *		  character and gets another (i.e. is expecting a Start
+ *		  character, but gets another control character).
+ *	   2) Start control character is not in lane 0
+ *	   Only increments the count by one for each XGMII column.
+ * @rx_xgmii_data_err_cnt: Maintains a count of unexpected control characters
+ *	   during normal data transmission. If the Reconciliation Sublayer
+ *	   (RS) receives a control character, other than a terminate control
+ *	   character, during receipt of data octets then this register is
+ *	   incremented. Also increments if the start frame delimiter is not
+ *	   found in the correct location. Only increments the count by one
+ *	   for each XGMII column.
+ * @rx_xgmii_char1_match: Maintains a count of the number of XGMII characters
+ *	   that match a pattern that is programmable through register
+ *	   XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set
+ *	   to /E/ (i.e. the error character), thus the statistic tracks the
+ *	   number of Error characters received at any time.
+ * @rx_xgmii_err_sym: Count of the number of symbol errors in the received
+ *	   XGMII data (i.e. PHY indicates "Receive Error" on the XGMII).
+ *	   Only includes symbol errors that are observed between the XGMII
+ *	   Start Frame Delimiter and End Frame Delimiter, inclusive. And
+ *	   only increments the count by one for each frame.
+ * @rx_xgmii_column1_match: Maintains a count of the number of XGMII columns
+ *	   that match a pattern that is programmable through register
+ *	   XMAC_STATS_RX_XGMII_COLUMN1_PORTn. By default, the pattern is set
+ *	   to 4 x /E/ (i.e. a column containing all error characters), thus
+ *	   the statistic tracks the number of Error columns received at any
+ *	   time.
+ * @rx_xgmii_char2_match: Maintains a count of the number of XGMII characters
+ *	   that match a pattern that is programmable through register
+ *	   XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set
+ *	   to /E/ (i.e. the error character), thus the statistic tracks the
+ *	   number of Error characters received at any time.
+ * @rx_local_fault: Maintains a count of the number of times that link
+ *	   transitioned from "up" to "down" due to a local fault.
+ * @rx_xgmii_column2_match: Maintains a count of the number of XGMII columns
+ *	   that match a pattern that is programmable through register
+ *	   XMAC_STATS_RX_XGMII_COLUMN2_PORTn. By default, the pattern is set
+ *	   to 4 x /E/ (i.e. a column containing all error characters), thus
+ *	   the statistic tracks the number of Error columns received at any
+ *	   time. If XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is set
+ *	   to 1, then this stat increments when COLUMN2 is found within 'n'
+ *	   clocks after COLUMN1. Here, 'n' is defined by
+ *	   XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set to
+ *	   0, then it means to search anywhere for COLUMN2).
+ * @rx_jettison: Count of received frames that are jettisoned because internal
+ *	   buffers are full.
+ * @rx_remote_fault: Maintains a count of the number of times that link
+ *	   transitioned from "up" to "down" due to a remote fault.
+ *
+ * XMAC Port Statistics.
+ */
+#pragma pack(1)
+typedef struct vxge_hal_xmac_port_stats_t {
+/* 0x000 */		u64	tx_ttl_frms;
+/* 0x008 */		u64	tx_ttl_octets;
+/* 0x010 */		u64	tx_data_octets;
+/* 0x018 */		u64	tx_mcast_frms;
+/* 0x020 */		u64	tx_bcast_frms;
+/* 0x028 */		u64	tx_ucast_frms;
+/* 0x030 */		u64	tx_tagged_frms;
+/* 0x038 */		u64	tx_vld_ip;
+/* 0x040 */		u64	tx_vld_ip_octets;
+/* 0x048 */		u64	tx_icmp;
+/* 0x050 */		u64	tx_tcp;
+/* 0x058 */		u64	tx_rst_tcp;
+/* 0x060 */		u64	tx_udp;
+/* 0x068 */		u32	tx_parse_error;
+/* 0x06c */		u32	tx_unknown_protocol;
+/* 0x070 */		u64	tx_pause_ctrl_frms;
+/* 0x078 */		u32	tx_marker_pdu_frms;
+/* 0x07c */		u32	tx_lacpdu_frms;
+/* 0x080 */		u32	tx_drop_ip;
+/* 0x084 */		u32	tx_marker_resp_pdu_frms;
+/* 0x088 */		u32	tx_xgmii_char2_match;
+/* 0x08c */		u32	tx_xgmii_char1_match;
+/* 0x090 */		u32	tx_xgmii_column2_match;
+/* 0x094 */		u32	tx_xgmii_column1_match;
+/* 0x098 */		u32	unused1;
+/* 0x09c */		u16	tx_any_err_frms;
+/* 0x09e */		u16	tx_drop_frms;
+/* 0x0a0 */		u64	rx_ttl_frms;
+/* 0x0a8 */		u64	rx_vld_frms;
+/* 0x0b0 */		u64	rx_offload_frms;
+/* 0x0b8 */		u64	rx_ttl_octets;
+/* 0x0c0 */		u64	rx_data_octets;
+/* 0x0c8 */		u64	rx_offload_octets;
+/* 0x0d0 */		u64	rx_vld_mcast_frms;
+/* 0x0d8 */		u64	rx_vld_bcast_frms;
+/* 0x0e0 */		u64	rx_accepted_ucast_frms;
+/* 0x0e8 */		u64	rx_accepted_nucast_frms;
+/* 0x0f0 */		u64	rx_tagged_frms;
+/* 0x0f8 */		u64	rx_long_frms;
+/* 0x100 */		u64	rx_usized_frms;
+/* 0x108 */		u64	rx_osized_frms;
+/* 0x110 */		u64	rx_frag_frms;
+/* 0x118 */		u64	rx_jabber_frms;
+/* 0x120 */		u64	rx_ttl_64_frms;
+/* 0x128 */		u64	rx_ttl_65_127_frms;
+/* 0x130 */		u64	rx_ttl_128_255_frms;
+/* 0x138 */		u64	rx_ttl_256_511_frms;
+/* 0x140 */		u64	rx_ttl_512_1023_frms;
+/* 0x148 */		u64	rx_ttl_1024_1518_frms;
+/* 0x150 */		u64	rx_ttl_1519_4095_frms;
+/* 0x158 */		u64	rx_ttl_4096_8191_frms;
+/* 0x160 */		u64	rx_ttl_8192_max_frms;
+/* 0x168 */		u64	rx_ttl_gt_max_frms;
+/* 0x170 */		u64	rx_ip;
+/* 0x178 */		u64	rx_accepted_ip;
+/* 0x180 */		u64	rx_ip_octets;
+/* 0x188 */		u64	rx_err_ip;
+/* 0x190 */		u64	rx_icmp;
+/* 0x198 */		u64	rx_tcp;
+/* 0x1a0 */		u64	rx_udp;
+/* 0x1a8 */		u64	rx_err_tcp;
+/* 0x1b0 */		u64	rx_pause_count;
+/* 0x1b8 */		u64	rx_pause_ctrl_frms;
+/* 0x1c0 */		u64	rx_unsup_ctrl_frms;
+/* 0x1c8 */		u64	rx_fcs_err_frms;
+/* 0x1d0 */		u64	rx_in_rng_len_err_frms;
+/* 0x1d8 */		u64	rx_out_rng_len_err_frms;
+/* 0x1e0 */		u64	rx_drop_frms;
+/* 0x1e8 */		u64	rx_discarded_frms;
+/* 0x1f0 */		u64	rx_drop_ip;
+/* 0x1f8 */		u64	rx_drop_udp;
+/* 0x200 */		u32	rx_marker_pdu_frms;
+/* 0x204 */		u32	rx_lacpdu_frms;
+/* 0x208 */		u32	rx_unknown_pdu_frms;
+/* 0x20c */		u32	rx_marker_resp_pdu_frms;
+/* 0x210 */		u32	rx_fcs_discard;
+/* 0x214 */		u32	rx_illegal_pdu_frms;
+/* 0x218 */		u32	rx_switch_discard;
+/* 0x21c */		u32	rx_len_discard;
+/* 0x220 */		u32	rx_rpa_discard;
+/* 0x224 */		u32	rx_l2_mgmt_discard;
+/* 0x228 */		u32	rx_rts_discard;
+/* 0x22c */		u32	rx_trash_discard;
+/* 0x230 */		u32	rx_buff_full_discard;
+/* 0x234 */		u32	rx_red_discard;
+/* 0x238 */		u32	rx_xgmii_ctrl_err_cnt;
+/* 0x23c */		u32	rx_xgmii_data_err_cnt;
+/* 0x240 */		u32	rx_xgmii_char1_match;
+/* 0x244 */		u32	rx_xgmii_err_sym;
+/* 0x248 */		u32	rx_xgmii_column1_match;
+/* 0x24c */		u32	rx_xgmii_char2_match;
+/* 0x250 */		u32	rx_local_fault;
+/* 0x254 */		u32	rx_xgmii_column2_match;
+/* 0x258 */		u32	rx_jettison;
+/* 0x25c */		u32	rx_remote_fault;
+} vxge_hal_xmac_port_stats_t;
+
+#pragma pack()
+
+/*
+ * struct vxge_hal_mrpcim_xmac_stats_t - XMAC Statistics
+ *
+ * @aggr_stats: Statistics on aggregate port(port 0, port 1)
+ * @port_stats: Staticstics on ports(wire 0, wire 1, lag)
+ *
+ * XMAC Statistics.
+ */
+typedef struct vxge_hal_mrpcim_xmac_stats_t {
+	vxge_hal_xmac_aggr_stats_t	aggr_stats[VXGE_HAL_MAC_MAX_AGGR_PORTS];
+	vxge_hal_xmac_port_stats_t	port_stats[VXGE_HAL_MAC_MAX_PORTS];
+} vxge_hal_mrpcim_xmac_stats_t;
+
+/*
+ * struct vxge_hal_xmac_vpath_tx_stats_t - XMAC Vpath Tx Statistics
+ *
+ * @tx_ttl_eth_frms: Count of successfully transmitted MAC frames.
+ * @tx_ttl_eth_octets: Count of total octets of transmitted frames,
+ *		not including framing characters (i.e. less framing bits).
+ *		To determine the total octets of transmitted frames, including
+ *		framing characters, multiply TX_TTL_ETH_FRMS by 8 and add it to
+ *		this stat (the device always prepends 8 bytes of preamble for
+ *		each frame)
+ * @tx_data_octets: Count of data and padding octets of successfully transmitted
+ *		frames.
+ * @tx_mcast_frms: Count of successfully transmitted frames to a group address
+ *		other than the broadcast address.
+ * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast
+ *		group address.
+ * @tx_ucast_frms: Count of transmitted frames containing a unicast address.
+ *		Includes discarded frames that are not sent to the network.
+ * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag.
+ * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network.
+ * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that
+ *	   are passed to the network.
+ * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent due
+ *	   to problems within ICMP.
+ * @tx_tcp: Count of transmitted TCP segments. Does not include segments
+ *	   containing retransmitted octets.
+ * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag.
+ * @tx_udp: Count of transmitted UDP datagrams.
+ * @tx_unknown_protocol: Increments when the TPA encounters an unknown protocol,
+ *	   such as a new IPv6 extension header, or an unsupported Routing
+ *	   Type. The packet still has a checksum calculated but it may be
+ *	   incorrect.
+ * @tx_lost_ip: Count of transmitted IP datagrams that could not be passed
+ *	   to the network. Increments because of: 1) An internal processing
+ *	   error (such as an uncorrectable ECC error). 2) A frame parsing
+ *	   error during IP checksum calculation.
+ * @unused1: Reserved.
+ * @tx_parse_error: Increments when the TPA is unable to parse a packet. This
+ *	   generally occurs when a packet is corrupt somehow, including
+ *	   packets that have IP version mismatches, invalid Layer 2 control
+ *	   fields, etc. L3/L4 checksums are not offloaded, but the packet
+ *	   is still be transmitted.
+ * @tx_tcp_offload: For frames belonging to offloaded sessions only, a count
+ *	   of transmitted TCP segments. Does not include segments containing
+ *	   retransmitted octets.
+ * @tx_retx_tcp_offload: For frames belonging to offloaded sessions only, the
+ *	   total number of segments retransmitted. Retransmitted segments
+ *	   that are sourced by the host are counted by the host.
+ * @tx_lost_ip_offload: For frames belonging to offloaded sessions only, a count
+ *	   of transmitted IP datagrams that could not be passed to the
+ *	   network.
+ *
+ * XMAC Vpath TX Statistics.
+ */
+#pragma pack(1)
+typedef struct vxge_hal_xmac_vpath_tx_stats_t {
+	u64	tx_ttl_eth_frms;
+	u64	tx_ttl_eth_octets;
+	u64	tx_data_octets;
+	u64	tx_mcast_frms;
+	u64	tx_bcast_frms;
+	u64	tx_ucast_frms;
+	u64	tx_tagged_frms;
+	u64	tx_vld_ip;
+	u64	tx_vld_ip_octets;
+	u64	tx_icmp;
+	u64	tx_tcp;
+	u64	tx_rst_tcp;
+	u64	tx_udp;
+	u32	tx_unknown_protocol;
+	u32	tx_lost_ip;
+	u32	unused1;
+	u32	tx_parse_error;
+	u64	tx_tcp_offload;
+	u64	tx_retx_tcp_offload;
+	u64	tx_lost_ip_offload;
+} vxge_hal_xmac_vpath_tx_stats_t;
+
+#pragma pack()
+
+/*
+ * struct vxge_hal_xmac_vpath_rx_stats_t - XMAC Vpath RX Statistics
+ *
+ * @rx_ttl_eth_frms: Count of successfully received MAC frames.
+ * @rx_vld_frms: Count of successfully received MAC frames. Does not include
+ *	   frames received with frame-too-long, FCS, or length errors.
+ * @rx_offload_frms: Count of offloaded received frames that are passed to
+ *	   the host.
+ * @rx_ttl_eth_octets: Count of total octets of received frames, not including
+ *	   framing characters (i.e. less framing bits). Only counts octets
+ *	   of frames that are at least 14 bytes (18 bytes for VLAN-tagged)
+ *	   before FCS. To determine the total octets of received frames,
+ *	   including framing characters, multiply RX_TTL_ETH_FRMS by 8 and
+ *	   add it to this stat (the stat RX_TTL_ETH_FRMS only counts frames
+ *	   that have the required 8 bytes of preamble).
+ * @rx_data_octets: Count of data and padding octets of successfully received
+ *	   frames. Does not include frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_offload_octets: Count of total octets, not including framing characters,
+ *	   of offloaded received frames that are passed to the host.
+ * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a
+ *	   nonbroadcast group address. Does not include frames received with
+ *	   frame-too-long, FCS, or length errors.
+ * @rx_vld_bcast_frms: Count of successfully received MAC frames containing the
+ *	   broadcast group address. Does not include frames received with
+ *	   frame-too-long, FCS, or length errors.
+ * @rx_accepted_ucast_frms: Count of successfully received frames containing
+ *	   a unicast address. Only includes frames that are passed to the
+ *	   system.
+ * @rx_accepted_nucast_frms: Count of successfully received frames containing
+ *	   a non-unicast (broadcast or multicast) address. Only includes
+ *	   frames that are passed to the system. Could include, for instance,
+ *	   non-unicast frames that contain FCS errors if the MAC_ERROR_CFG
+ *	   register is set to pass FCS-errored frames to the host.
+ * @rx_tagged_frms: Count of received frames containing a VLAN tag.
+ * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN
+ *	   + 18 bytes (+ 22 bytes if VLAN-tagged).
+ * @rx_usized_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) less than 64 octets, that are otherwise well-formed.
+ *	   In other words, counts runts.
+ * @rx_osized_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) more than 1518 octets, that are otherwise
+ *	   well-formed.
+ * @rx_frag_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) less than 64 octets that had bad FCS. In other words,
+ *	   counts fragments.
+ * @rx_jabber_frms: Count of received frames of length (including FCS, but not
+ *	   framing bits) more than 1518 octets that had bad FCS. In other
+ *	   words, counts jabbers.
+ * @rx_ttl_64_frms: Count of total received MAC frames with length (including
+ *	   FCS, but not framing bits) of exactly 64 octets. Includes frames
+ *	   received with frame-too-long, FCS, or length errors.
+ * @rx_ttl_65_127_frms: Count of total received MAC frames with length(including
+ *	   FCS, but not framing bits) of between 65 and 127 octets inclusive.
+ *	   Includes frames received with frame-too-long, FCS, or length errors.
+ * @rx_ttl_128_255_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 128 and 255 octets
+ *	   inclusive. Includes frames received with frame-too-long, FCS,
+ *	   or length errors.
+ * @rx_ttl_256_511_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 256 and 511 octets
+ *	   inclusive. Includes frames received with frame-too-long, FCS, or
+ *	   length errors.
+ * @rx_ttl_512_1023_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 512 and 1023
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 1024 and 1518
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 1519 and 4095
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 4096 and 8191
+ *	   octets inclusive. Includes frames received with frame-too-long,
+ *	   FCS, or length errors.
+ * @rx_ttl_8192_max_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) of between 8192 and
+ *	   RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received
+ *	   with frame-too-long, FCS, or length errors.
+ * @rx_ttl_gt_max_frms: Count of total received MAC frames with length
+ *	   (including FCS, but not framing bits) exceeding RX_MAX_PYLD_LEN+18
+ *	   (+22 bytes if VLAN-tagged) octets inclusive. Includes frames
+ *	   received with frame-too-long, FCS, or length errors.
+ * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams.
+ * @rx_accepted_ip: Count of received IP datagrams that are passed to the system
+ * @rx_ip_octets: Count of number of octets in received IP datagrams.
+ *	   Includes errored IP datagrams.
+ * @rx_err_ip: Count of received IP datagrams containing errors. For example,
+ *	   bad IP checksum.
+ * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages.
+ * @rx_tcp: Count of received TCP segments. Includes errored TCP segments.
+ *		Note: This stat contains a count of all received TCP segments,
+ *		regardless of whether or not they pertain to an established
+ *		connection.
+ * @rx_udp: Count of received UDP datagrams.
+ * @rx_err_tcp: Count of received TCP segments containing errors. For example,
+ *		bad TCP checksum.
+ * @rx_lost_frms: Count of received frames that could not be passed to the host.
+ *		See RX_QUEUE_FULL_DISCARD and RX_RED_DISCARD for list of reasons
+ * @rx_lost_ip: Count of received IP datagrams that could not be passed to
+ *		the host. See RX_LOST_FRMS for a list of reasons.
+ * @rx_lost_ip_offload: For frames belonging to offloaded sessions only, a count
+ *		of received IP datagrams that could not be passed to the host.
+ *		See RX_LOST_FRMS for a list of reasons.
+ * @rx_various_discard: Count of received frames that are discarded because
+ *		the target receive queue is full.
+ * @rx_sleep_discard: Count of received frames that are discarded because the
+ *	   target VPATH is asleep (a Wake-on-LAN magic packet can be used
+ *	   to awaken the VPATH).
+ * @rx_red_discard: Count of received frames that are discarded because of RED
+ *	   (Random Early Discard).
+ * @rx_queue_full_discard: Count of received frames that are discarded because
+ *		the target receive queue is full.
+ * @rx_mpa_ok_frms: Count of received frames that pass the MPA checks.
+ *
+ * XMAC Vpath RX Statistics.
+ */
+#pragma pack(1)
+typedef struct vxge_hal_xmac_vpath_rx_stats_t {
+	u64	rx_ttl_eth_frms;
+	u64	rx_vld_frms;
+	u64	rx_offload_frms;
+	u64	rx_ttl_eth_octets;
+	u64	rx_data_octets;
+	u64	rx_offload_octets;
+	u64	rx_vld_mcast_frms;
+	u64	rx_vld_bcast_frms;
+	u64	rx_accepted_ucast_frms;
+	u64	rx_accepted_nucast_frms;
+	u64	rx_tagged_frms;
+	u64	rx_long_frms;
+	u64	rx_usized_frms;
+	u64	rx_osized_frms;
+	u64	rx_frag_frms;
+	u64	rx_jabber_frms;
+	u64	rx_ttl_64_frms;
+	u64	rx_ttl_65_127_frms;
+	u64	rx_ttl_128_255_frms;
+	u64	rx_ttl_256_511_frms;
+	u64	rx_ttl_512_1023_frms;
+	u64	rx_ttl_1024_1518_frms;
+	u64	rx_ttl_1519_4095_frms;
+	u64	rx_ttl_4096_8191_frms;
+	u64	rx_ttl_8192_max_frms;
+	u64	rx_ttl_gt_max_frms;
+	u64	rx_ip;
+	u64	rx_accepted_ip;
+	u64	rx_ip_octets;
+	u64	rx_err_ip;
+	u64	rx_icmp;
+	u64	rx_tcp;
+	u64	rx_udp;
+	u64	rx_err_tcp;
+	u64	rx_lost_frms;
+	u64	rx_lost_ip;
+	u64	rx_lost_ip_offload;
+	u16	rx_various_discard;
+	u16	rx_sleep_discard;
+	u16	rx_red_discard;
+	u16	rx_queue_full_discard;
+	u64	rx_mpa_ok_frms;
+} vxge_hal_xmac_vpath_rx_stats_t;
+
+#pragma pack()
+
+/*
+ * struct vxge_hal_device_xmac_stats_t - XMAC Statistics
+ *
+ * @vpath_tx_stats: Per vpath XMAC TX stats
+ * @vpath_rx_stats: Per vpath XMAC RX stats
+ *
+ * XMAC Statistics.
+ */
+typedef struct vxge_hal_device_xmac_stats_t {
+	vxge_hal_xmac_vpath_tx_stats_t vpath_tx_stats[VXGE_HAL_MAX_VIRTUAL_PATHS];
+	vxge_hal_xmac_vpath_rx_stats_t vpath_rx_stats[VXGE_HAL_MAX_VIRTUAL_PATHS];
+} vxge_hal_device_xmac_stats_t;
+
+/*
+ * struct vxge_hal_vpath_stats_hw_info_t - X3100 vpath hardware statistics.
+ * @ini_num_mwr_sent: The number of PCI memory writes initiated by the PIC block
+ *		for the given VPATH
+ * @unused1: Reserved
+ * @ini_num_mrd_sent: The number of PCI memory reads initiated by the PIC block
+ * @unused2: Reserved
+ * @ini_num_cpl_rcvd: The number of PCI read completions received by the
+ *		PIC block
+ * @unused3: Reserved
+ * @ini_num_mwr_byte_sent: The number of PCI memory write bytes sent by the PIC
+ *		block to the host
+ * @ini_num_cpl_byte_rcvd: The number of PCI read completion bytes received by
+ *		the PIC block
+ * @wrcrdtarb_xoff: TBD
+ * @unused4: Reserved
+ * @rdcrdtarb_xoff: TBD
+ * @unused5: Reserved
+ * @vpath_genstats_count0: Configurable statistic #1. Refer to the GENSTATS0_CFG
+ *		for information on configuring this statistic
+ * @vpath_genstats_count1: Configurable statistic #2. Refer to the GENSTATS1_CFG
+ *		for information on configuring this statistic
+ * @vpath_genstats_count2: Configurable statistic #3. Refer to the GENSTATS2_CFG
+ *		for information on configuring this statistic
+ * @vpath_genstats_count3: Configurable statistic #4. Refer to the GENSTATS3_CFG
+ *		for information on configuring this statistic
+ * @vpath_genstats_count4: Configurable statistic #5. Refer to the GENSTATS4_CFG
+ *		for information on configuring this statistic
+ * @unused6: Reserved
+ * @vpath_gennstats_count5: Configurable statistic #6. Refer to the
+ *		GENSTATS5_CFG for information on configuring this statistic
+ * @unused7: Reserved
+ * @tx_stats: Transmit stats
+ * @rx_stats: Receive stats
+ * @unused9: Reserved
+ * @prog_event_vnum1: Programmable statistic. Increments when internal logic
+ *		detects a certain event. See register
+ *		XMAC_STATS_CFG.EVENT_VNUM1_CFG for more information.
+ * @prog_event_vnum0: Programmable statistic. Increments when internal logic
+ *		detects a certain event. See register
+ *		XMAC_STATS_CFG.EVENT_VNUM0_CFG for more information.
+ * @prog_event_vnum3: Programmable statistic. Increments when internal logic
+ *		detects a certain event. See register
+ *		XMAC_STATS_CFG.EVENT_VNUM3_CFG for more information.
+ * @prog_event_vnum2: Programmable statistic. Increments when internal logic
+ *		detects a certain event. See register
+ *		XMAC_STATS_CFG.EVENT_VNUM2_CFG for more information.
+ * @rx_multi_cast_frame_discard: TBD
+ * @unused10: Reserved
+ * @rx_frm_transferred: TBD
+ * @unused11: Reserved
+ * @rxd_returned: TBD
+ * @unused12: Reserved
+ * @rx_mpa_len_fail_frms: Count of received frames failed the MPA length check
+ * @rx_mpa_mrk_fail_frms: Count of received frames failed the MPA marker check
+ * @rx_mpa_crc_fail_frms: Count of received frames failed the MPA CRC check
+ * @rx_permitted_frms: Count of frames that pass through the FAU and on to the
+ *		frame buffer (and subsequently to the host).
+ * @rx_vp_reset_discarded_frms: Count of receive frames that are discarded
+ *		because the VPATH is in reset
+ * @rx_wol_frms: Count of received "magic packet" frames. Stat increments
+ *		whenever the received frame matches the VPATH's Wake-on-LAN
+ *		signature(s) CRC.
+ * @tx_vp_reset_discarded_frms: Count of transmit frames that are discarded
+ *		because the VPATH is in reset.Includes frames that are discarded
+ *		because the current VPIN does not match that VPIN of the frame
+ *
+ * X3100 vpath hardware statistics.
+ */
+#pragma pack(1)
+typedef struct vxge_hal_vpath_stats_hw_info_t {
+/* 0x000 */	u32 ini_num_mwr_sent;
+/* 0x004 */	u32 unused1;
+/* 0x008 */	u32 ini_num_mrd_sent;
+/* 0x00c */	u32 unused2;
+/* 0x010 */	u32 ini_num_cpl_rcvd;
+/* 0x014 */	u32 unused3;
+/* 0x018 */	u64 ini_num_mwr_byte_sent;
+/* 0x020 */	u64 ini_num_cpl_byte_rcvd;
+/* 0x028 */	u32 wrcrdtarb_xoff;
+/* 0x02c */	u32 unused4;
+/* 0x030 */	u32 rdcrdtarb_xoff;
+/* 0x034 */	u32 unused5;
+/* 0x038 */	u32 vpath_genstats_count0;
+/* 0x03c */	u32 vpath_genstats_count1;
+/* 0x040 */	u32 vpath_genstats_count2;
+/* 0x044 */	u32 vpath_genstats_count3;
+/* 0x048 */	u32 vpath_genstats_count4;
+/* 0x04c */	u32 unused6;
+/* 0x050 */	u32 vpath_genstats_count5;
+/* 0x054 */	u32 unused7;
+/* 0x058 */	vxge_hal_xmac_vpath_tx_stats_t tx_stats;
+/* 0x0e8 */	vxge_hal_xmac_vpath_rx_stats_t rx_stats;
+/* 0x220 */	u64 unused9;
+/* 0x228 */	u32 prog_event_vnum1;
+/* 0x22c */	u32 prog_event_vnum0;
+/* 0x230 */	u32 prog_event_vnum3;
+/* 0x234 */	u32 prog_event_vnum2;
+/* 0x238 */	u16 rx_multi_cast_frame_discard;
+/* 0x23a */	u8 unused10[6];
+/* 0x240 */	u32 rx_frm_transferred;
+/* 0x244 */	u32 unused11;
+/* 0x248 */	u16 rxd_returned;
+/* 0x24a */	u8 unused12[6];
+/* 0x252 */	u16 rx_mpa_len_fail_frms;
+/* 0x254 */	u16 rx_mpa_mrk_fail_frms;
+/* 0x256 */	u16 rx_mpa_crc_fail_frms;
+/* 0x258 */	u16 rx_permitted_frms;
+/* 0x25c */	u64 rx_vp_reset_discarded_frms;
+/* 0x25e */	u64 rx_wol_frms;
+/* 0x260 */	u64 tx_vp_reset_discarded_frms;
+} vxge_hal_vpath_stats_hw_info_t;
+
+#pragma pack()
+
+/*
+ * struct vxge_hal_device_stats_mrpcim_info_t - X3100 mrpcim hardware
+ *					    statistics.
+ * @pic_ini_rd_drop: Number of DMA reads initiated by the adapter that were
+ *		discarded because the VPATH is out of service
+ * @pic_ini_wr_drop: Number of DMA writes initiated by the adapter that were
+ *		discared because the VPATH is out of service
+ * @pic_wrcrdtarb_ph_crdt_depleted: Number of times the posted header credits
+ *		for upstream PCI writes were depleted
+ * @unused1: Reserved
+ * @pic_wrcrdtarb_ph_crdt_depleted_vplane: Array of structures containing above
+ *		two fields.
+ * @pic_wrcrdtarb_pd_crdt_depleted: Number of times the posted data credits for
+ *		upstream PCI writes were depleted
+ * @unused2: Reserved
+ * @pic_wrcrdtarb_pd_crdt_depleted_vplane: Array of structures containing above
+ *		two fields.
+ * @pic_rdcrdtarb_nph_crdt_depleted: Number of times the non-posted header
+ *		credits for upstream PCI reads were depleted
+ * @unused3: Reserved
+ * @pic_rdcrdtarb_nph_crdt_depleted_vplane: Array of structures containing above
+ *		two fields.
+ * @pic_ini_rd_vpin_drop: Number of DMA reads initiated by the adapter that were
+ *		discarded because the VPATH instance number does not match
+ * @pic_ini_wr_vpin_drop: Number of DMA writes initiated by the adapter that
+ *		were discarded because the VPATH instance number does not match
+ * @pic_genstats_count0: Configurable statistic #1. Refer to the GENSTATS0_CFG
+ *		for information on configuring this statistic
+ * @pic_genstats_count1: Configurable statistic #2. Refer to the GENSTATS1_CFG
+ *		for information on configuring this statistic
+ * @pic_genstats_count2: Configurable statistic #3. Refer to the GENSTATS2_CFG
+ *		for information on configuring this statistic
+ * @pic_genstats_count3: Configurable statistic #4. Refer to the GENSTATS3_CFG
+ *		for information on configuring this statistic
+ * @pic_genstats_count4: Configurable statistic #5. Refer to the GENSTATS4_CFG
+ *		for information on configuring this statistic
+ * @unused4: Reserved
+ * @pic_genstats_count5: Configurable statistic #6. Refer to the GENSTATS5_CFG
+ *		for information on configuring this statistic
+ * @unused5: Reserved
+ * @pci_rstdrop_cpl: TBD
+ * @pci_rstdrop_msg: TBD
+ * @pci_rstdrop_client1: TBD
+ * @pci_rstdrop_client0: TBD
+ * @pci_rstdrop_client2: TBD
+ * @unused6: Reserved
+ * @unused7: Reserved
+ * @pci_depl_cplh: Number of times completion header credits were depleted
+ * @pci_depl_nph: Number of times non posted header credits were depleted
+ * @pci_depl_ph: Number of times the posted header credits were depleted
+ * @pci_depl_h_vplane: Array of structures containing above four fields.
+ * @unused8: Reserved
+ * @pci_depl_cpld: Number of times completion data credits were depleted
+ * @pci_depl_npd: Number of times non posted data credits were depleted
+ * @pci_depl_pd: Number of times the posted data credits were depleted
+ * @pci_depl_d_vplane: Array of structures containing above four fields.
+ * @xgmac_port: Array of xmac port stats
+ * @xgmac_aggr: Array of aggr port stats
+ * @xgmac_global_prog_event_gnum0: Programmable statistic. Increments when
+ *		internal logic detects a certain event. See register
+ *		XMAC_STATS_GLOBAL_CFG.EVENT_GNUM0_CFG for more information.
+ * @xgmac_global_prog_event_gnum1: Programmable statistic. Increments when
+ *		internal logic detects a certain event. See register
+ *		XMAC_STATS_GLOBAL_CFG.EVENT_GNUM1_CFG for more information.
+ * @unused9: Reserved
+ * @xgmac.orp_lro_events: TBD
+ * @xgmac.orp_bs_events: TBD
+ * @xgmac.orp_iwarp_events: TBD
+ * @unused10: Reserved
+ * @xgmac.tx_permitted_frms: TBD
+ * @unused11: Reserved
+ * @unused12: Reserved
+ * @xgmac.port2_tx_any_frms: TBD
+ * @xgmac.port1_tx_any_frms: TBD
+ * @xgmac.port0_tx_any_frms: TBD
+ * @unused13: Reserved
+ * @unused14: Reserved
+ * @xgmac.port2_rx_any_frms: TBD
+ * @xgmac.port1_rx_any_frms: TBD
+ * @xgmac.port0_rx_any_frms: TBD
+ *
+ * X3100 mrpcim hardware statistics.
+ */
+#pragma pack(1)
+typedef struct vxge_hal_mrpcim_stats_hw_info_t {
+/* 0x0000 */	u32	pic_ini_rd_drop;
+/* 0x0004 */	u32	pic_ini_wr_drop;
+/* 0x0008 */	struct {
+	/* 0x0000 */	u32	pic_wrcrdtarb_ph_crdt_depleted;
+	/* 0x0004 */	u32	unused1;
+		} pic_wrcrdtarb_ph_crdt_depleted_vplane[17];
+/* 0x0090 */	struct {
+	/* 0x0000 */	u32	pic_wrcrdtarb_pd_crdt_depleted;
+	/* 0x0004 */	u32	unused2;
+		} pic_wrcrdtarb_pd_crdt_depleted_vplane[17];
+/* 0x0118 */	struct {
+	/* 0x0000 */	u32	pic_rdcrdtarb_nph_crdt_depleted;
+	/* 0x0004 */	u32	unused3;
+		} pic_rdcrdtarb_nph_crdt_depleted_vplane[17];
+/* 0x01a0 */	u32	pic_ini_rd_vpin_drop;
+/* 0x01a4 */	u32	pic_ini_wr_vpin_drop;
+/* 0x01a8 */	u32	pic_genstats_count0;
+/* 0x01ac */	u32	pic_genstats_count1;
+/* 0x01b0 */	u32	pic_genstats_count2;
+/* 0x01b4 */	u32	pic_genstats_count3;
+/* 0x01b8 */	u32	pic_genstats_count4;
+/* 0x01bc */	u32	unused4;
+/* 0x01c0 */	u32	pic_genstats_count5;
+/* 0x01c4 */	u32	unused5;
+/* 0x01c8 */	u32	pci_rstdrop_cpl;
+/* 0x01cc */	u32	pci_rstdrop_msg;
+/* 0x01d0 */	u32	pci_rstdrop_client1;
+/* 0x01d4 */	u32	pci_rstdrop_client0;
+/* 0x01d8 */	u32	pci_rstdrop_client2;
+/* 0x01dc */	u32	unused6;
+/* 0x01e0 */	struct {
+	/* 0x0000 */	u16	unused7;
+	/* 0x0002 */	u16	pci_depl_cplh;
+	/* 0x0004 */	u16	pci_depl_nph;
+	/* 0x0006 */	u16	pci_depl_ph;
+		} pci_depl_h_vplane[17];
+/* 0x0268 */	struct {
+	/* 0x0000 */	u16	unused8;
+	/* 0x0002 */	u16	pci_depl_cpld;
+	/* 0x0004 */	u16	pci_depl_npd;
+	/* 0x0006 */	u16	pci_depl_pd;
+		} pci_depl_d_vplane[17];
+/* 0x02f0 */	vxge_hal_xmac_port_stats_t xgmac_port[3];
+/* 0x0a10 */	vxge_hal_xmac_aggr_stats_t xgmac_aggr[2];
+/* 0x0ae0 */	u64	xgmac_global_prog_event_gnum0;
+/* 0x0ae8 */	u64	xgmac_global_prog_event_gnum1;
+/* 0x0af0 */	u64	unused9;
+/* 0x0af8 */	u64	xgmac_orp_lro_events;
+/* 0x0b00 */	u64	xgmac_orp_bs_events;
+/* 0x0b08 */	u64	xgmac_orp_iwarp_events;
+/* 0x0b10 */	u32	unused10;
+/* 0x0b14 */	u32	xgmac_tx_permitted_frms;
+/* 0x0b18 */	u32	unused11;
+/* 0x0b1c */	u8	unused12;
+/* 0x0b1d */	u8	xgmac_port2_tx_any_frms;
+/* 0x0b1e */	u8	xgmac_port1_tx_any_frms;
+/* 0x0b1f */	u8	xgmac_port0_tx_any_frms;
+/* 0x0b20 */	u32	unused13;
+/* 0x0b24 */	u8	unused14;
+/* 0x0b25 */	u8	xgmac_port2_rx_any_frms;
+/* 0x0b26 */	u8	xgmac_port1_rx_any_frms;
+/* 0x0b27 */	u8	xgmac_port0_rx_any_frms;
+} vxge_hal_mrpcim_stats_hw_info_t;
+
+#pragma pack()
+
+/*
+ * struct vxge_hal_mrpcim_xpak_stats_t - HAL xpak stats
+ * @excess_temp: excess transceiver_temperature count
+ * @excess_bias_current: excess laser_bias_current count
+ * @excess_laser_output: excess laser_output_power count
+ * @alarm_transceiver_temp_high: alarm_transceiver_temp_high count value
+ * @alarm_transceiver_temp_low : alarm_transceiver_temp_low count value
+ * @alarm_laser_bias_current_high: alarm_laser_bias_current_high count value
+ * @alarm_laser_bias_current_low: alarm_laser_bias_current_low count value
+ * @alarm_laser_output_power_high: alarm_laser_output_power_high count value
+ * @alarm_laser_output_power_low: alarm_laser_output_power_low count value
+ * @warn_transceiver_temp_high: warn_transceiver_temp_high count value
+ * @warn_transceiver_temp_low: warn_transceiver_temp_low count value
+ * @warn_laser_bias_current_high: warn_laser_bias_current_high count value
+ * @warn_laser_bias_current_low: warn_laser_bias_current_low count value
+ * @warn_laser_output_power_high: warn_laser_output_power_high count value
+ * @warn_laser_output_power_low: warn_laser_output_power_low count value
+ */
+typedef struct vxge_hal_mrpcim_xpak_stats_t {
+	u32	 excess_temp;
+	u32	 excess_bias_current;
+	u32	 excess_laser_output;
+	u16	 alarm_transceiver_temp_high;
+	u16	 alarm_transceiver_temp_low;
+	u16	 alarm_laser_bias_current_high;
+	u16	 alarm_laser_bias_current_low;
+	u16	 alarm_laser_output_power_high;
+	u16	 alarm_laser_output_power_low;
+	u16	 warn_transceiver_temp_high;
+	u16	 warn_transceiver_temp_low;
+	u16	 warn_laser_bias_current_high;
+	u16	 warn_laser_bias_current_low;
+	u16	 warn_laser_output_power_high;
+	u16	 warn_laser_output_power_low;
+} vxge_hal_mrpcim_xpak_stats_t;
+
+/*
+ * struct vxge_hal_device_stats_hw_info_t - X3100 hardware statistics.
+ * @vpath_info: VPath statistics
+ * @vpath_info_sav: Vpath statistics saved
+ *
+ * X3100 hardware statistics.
+ */
+typedef struct vxge_hal_device_stats_hw_info_t {
+	vxge_hal_vpath_stats_hw_info_t *vpath_info[VXGE_HAL_MAX_VIRTUAL_PATHS];
+	vxge_hal_vpath_stats_hw_info_t vpath_info_sav[VXGE_HAL_MAX_VIRTUAL_PATHS];
+} vxge_hal_device_stats_hw_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_common_info_t - HAL common stats for queues.
+ * @full_cnt: Number of times the queue was full
+ * @usage_cnt: usage count.
+ * @usage_max: Maximum usage
+ * @avg_compl_per_intr_cnt: Average number of completions per interrupt.
+ *	   Note that a total number of completed descriptors
+ *	   for the given channel can be calculated as
+ *	   (@traffic_intr_cnt * @avg_compl_per_intr_cnt).
+ * @total_compl_cnt: Total completion count.
+ *	    @total_compl_cnt == (@traffic_intr_cnt * @avg_compl_per_intr_cnt).
+ *
+ * HAL common counters for queues
+ * See also: vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	  vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	  vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	  vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	  vxge_hal_vpath_stats_sw_srq_info_t {},
+ *	  vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_common_info_t {
+	u32	full_cnt;
+	u32	usage_cnt;
+	u32	usage_max;
+	u32	avg_compl_per_intr_cnt;
+	u32	total_compl_cnt;
+} vxge_hal_vpath_stats_sw_common_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_fifo_info_t - HAL fifo statistics
+ * @common_stats: Common counters for all queues
+ * @total_posts: Total number of postings on the queue.
+ * @total_buffers: Total number of buffers posted.
+ * @avg_buffers_per_post: Average number of buffers transferred in a single
+ *	post operation. Calculated as @total_buffers/@total_posts.
+ * @copied_buffers: Number of buffers copied
+ * @avg_buffer_size: Average buffer size transferred by a single post
+ *		operation. Calculated as a total number of transmitted octets
+ *		divided by @total_buffers.
+ * @avg_post_size: Average amount of data transferred by a single post.
+ *		Calculated as a total number of transmitted octets divided by
+ *		@total_posts.
+ * @total_frags: Total number of fragments
+ * @copied_frags: Number of fragments copied
+ * @total_posts_dang_dtrs: Total number of posts involving dangling descriptors.
+ * @total_posts_dang_frags: Total number of dangling fragments posted during
+ *		 post request containing multiple descriptors.
+ * @txd_t_code_err_cnt: Array of transmit transfer codes. The position
+ * (index) in this array reflects the transfer code type, for instance
+ * 0xA - "loss of link".
+ * Value txd_t_code_err_cnt[i] reflects the
+ * number of times the corresponding transfer code was encountered.
+ *
+ * HAL fifo counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	     vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_sq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_srq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_fifo_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+	u32	total_posts;
+	u32	total_buffers;
+	u32	avg_buffers_per_post;
+	u32	copied_buffers;
+	u32	avg_buffer_size;
+	u32	avg_post_size;
+	u32	total_frags;
+	u32	copied_frags;
+	u32	total_posts_dang_dtrs;
+	u32	total_posts_dang_frags;
+	u32	txd_t_code_err_cnt[16];
+} vxge_hal_vpath_stats_sw_fifo_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_ring_info_t - HAL ring statistics
+ * @common_stats: Common counters for all queues
+ * @rxd_t_code_err_cnt: Array of receive transfer codes. The position
+ *		(index) in this array reflects the transfer code type,
+ *		for instance
+ *		0x7 - for "invalid receive buffer size", or 0x8 - for ECC.
+ *		Value rxd_t_code_err_cnt[i] reflects the
+ *		number of times the corresponding transfer code was encountered.
+ * @lro_clubbed_frms_cnt: Total no of Aggregated packets
+ * @lro_sending_both: Number of times the aggregation of packets broken
+ * @lro_outof_sequence_pkts: Number of out of order packets
+ * @lro_flush_max_pkts: Number of times we reached upper packet limit for
+ *		aggregation per session
+ * @lro_sum_avg_pkts_aggregated: Total number of packets considered for
+ *		aggregation
+ * @lro_num_aggregations: Number of packets sent to the stack
+ * @lro_max_pkts_aggr: Max number of aggr packet  per ring
+ * @lro_avg_agr_pkts: Average Aggregate packet
+ *
+ * HAL ring counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	     vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_sq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_srq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_ring_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+	u32	rxd_t_code_err_cnt[16];
+} vxge_hal_vpath_stats_sw_ring_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_dmq_info_t - HAL dmq statistics
+ * @common_stats: Common counters for all queues
+ *
+ * HAL dmq counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	     vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	     vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_sq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_srq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_dmq_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+} vxge_hal_vpath_stats_sw_dmq_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_umq_info_t - HAL umq statistics
+ * @common_stats: Common counters for all queues
+ *
+ * HAL dmq counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	     vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	     vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_sq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_srq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_umq_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+} vxge_hal_vpath_stats_sw_umq_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_sq_info_t - HAL sq statistics
+ * @common_stats: Common counters for all queues
+ *
+ * HAL srq counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	     vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	     vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_srq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_sq_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+} vxge_hal_vpath_stats_sw_sq_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_srq_info_t - HAL srq statistics
+ * @common_stats: Common counters for all queues
+ *
+ * HAL srq counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	     vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	     vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_sq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_cqrq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_srq_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+} vxge_hal_vpath_stats_sw_srq_info_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_cqrq_info_t - HAL cqrq statistics
+ * @common_stats: Common counters for all queues
+ *
+ * HAL cqrq counters
+ * See also: vxge_hal_vpath_stats_sw_common_info_t {},
+ *	     vxge_hal_vpath_stats_sw_fifo_info_t {},
+ *	     vxge_hal_vpath_stats_sw_ring_info_t {},
+ *	     vxge_hal_vpath_stats_sw_dmq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_umq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_sq_info_t {},
+ *	     vxge_hal_vpath_stats_sw_srq_info_t {}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_cqrq_info_t {
+	vxge_hal_vpath_stats_sw_common_info_t common_stats;
+} vxge_hal_vpath_stats_sw_cqrq_info_t;
+
+/*
+ * struct vxge_hal_vpath_sw_obj_count_t - Usage count of obj ids in virtual path
+ *
+ * @no_nces: Number of NCEs on Adapter in this VP
+ * @no_sqs: Number of SQs on Adapter in this VP
+ * @no_srqs: Number of SRQs on Adapter in this VP
+ * @no_cqrqs: Number of CQRQs on Adapter in this VP
+ * @no_sessions: Number of sessions on Adapter in this VP
+ *
+ * This structure contains fields to keep the usage count of objects in
+ * a virtual path
+ */
+typedef struct vxge_hal_vpath_sw_obj_count_t {
+	u32	no_nces;
+	u32	no_sqs;
+	u32	no_srqs;
+	u32	no_cqrqs;
+	u32	no_sessions;
+} vxge_hal_vpath_sw_obj_count_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_err_t - HAL vpath error statistics
+ * @unknown_alarms: Unknown Alarm count
+ * @network_sustained_fault: Network sustained fault count
+ * @network_sustained_ok: Network sustained ok count
+ * @kdfcctl_fifo0_overwrite: Fifo 0 overwrite count
+ * @kdfcctl_fifo0_poison: Fifo 0 poison count
+ * @kdfcctl_fifo0_dma_error: Fifo 0 dma error count
+ * @kdfcctl_fifo1_overwrite: Fifo 1 overwrite count
+ * @kdfcctl_fifo1_poison: Fifo 1 poison count
+ * @kdfcctl_fifo1_dma_error: Fifo 1 dma error count
+ * @kdfcctl_fifo2_overwrite: Fifo 2 overwrite count
+ * @kdfcctl_fifo2_poison: Fifo 2 overwrite count
+ * @kdfcctl_fifo2_dma_error: Fifo 2 dma error count
+ * @dblgen_fifo0_overflow: Dblgen Fifo 0 overflow count
+ * @dblgen_fifo1_overflow: Dblgen Fifo 1 overflow count
+ * @dblgen_fifo2_overflow: Dblgen Fifo 2 overflow count
+ * @statsb_pif_chain_error: Statsb pif chain error count
+ * @statsb_drop_timeout: Statsb drop timeout count
+ * @target_illegal_access: Target illegal access count
+ * @ini_serr_det: Serious error detected count
+ * @pci_config_status_err: PCI config status error count
+ * @pci_config_uncor_err: PCI config uncorrectable error count
+ * @pci_config_cor_err: PCI config correctable error count
+ * @mrpcim_to_vpath_alarms: MRPCIM to vpath alarm count
+ * @srpcim_to_vpath_alarms: SRPCIM to vpath alarm count
+ * @srpcim_msg_to_vpath: SRPCIM to vpath message count
+ * @prc_ring_bumps: Ring controller ring bumps count
+ * @prc_rxdcm_sc_err: Ring controller rxdsm sc error count
+ * @prc_rxdcm_sc_abort: Ring controller rxdsm sc abort count
+ * @prc_quanta_size_err: Ring controller quanta size count
+ *
+ * HAL vpath error statistics
+ */
+typedef struct vxge_hal_vpath_stats_sw_err_t {
+	u32	unknown_alarms;
+	u32	network_sustained_fault;
+	u32	network_sustained_ok;
+	u32	kdfcctl_fifo0_overwrite;
+	u32	kdfcctl_fifo0_poison;
+	u32	kdfcctl_fifo0_dma_error;
+	u32	kdfcctl_fifo1_overwrite;
+	u32	kdfcctl_fifo1_poison;
+	u32	kdfcctl_fifo1_dma_error;
+	u32	kdfcctl_fifo2_overwrite;
+	u32	kdfcctl_fifo2_poison;
+	u32	kdfcctl_fifo2_dma_error;
+	u32	dblgen_fifo0_overflow;
+	u32	dblgen_fifo1_overflow;
+	u32	dblgen_fifo2_overflow;
+	u32	statsb_pif_chain_error;
+	u32	statsb_drop_timeout;
+	u32	target_illegal_access;
+	u32	ini_serr_det;
+	u32	pci_config_status_err;
+	u32	pci_config_uncor_err;
+	u32	pci_config_cor_err;
+	u32	mrpcim_to_vpath_alarms;
+	u32	srpcim_to_vpath_alarms;
+	u32	srpcim_msg_to_vpath;
+	u32	prc_ring_bumps;
+	u32	prc_rxdcm_sc_err;
+	u32	prc_rxdcm_sc_abort;
+	u32	prc_quanta_size_err;
+} vxge_hal_vpath_stats_sw_err_t;
+
+/*
+ * struct vxge_hal_vpath_stats_sw_info_t - HAL vpath sw statistics
+ * @soft_reset_cnt: Number of times soft reset is done on this vpath.
+ * @obj_counts: Statistics for the VP
+ * @error_stats: error counters for the vpath
+ * @ring_stats: counters for ring belonging to the vpath
+ * @fifo_stats: counters for fifo belonging to the vpath
+ * @dmq_stats: counters for dmq belonging to the vpath
+ * @umq_stats: counters for umq belonging to the vpath
+ *
+ * HAL vpath sw statistics
+ * See also: vxge_hal_device_info_t {}}.
+ */
+typedef struct vxge_hal_vpath_stats_sw_info_t {
+	u32					soft_reset_cnt;
+	vxge_hal_vpath_sw_obj_count_t		obj_counts;
+	vxge_hal_vpath_stats_sw_err_t		error_stats;
+	vxge_hal_vpath_stats_sw_ring_info_t	ring_stats;
+	vxge_hal_vpath_stats_sw_fifo_info_t	fifo_stats;
+	vxge_hal_vpath_stats_sw_dmq_info_t	dmq_stats;
+	vxge_hal_vpath_stats_sw_umq_info_t	umq_stats;
+} vxge_hal_vpath_stats_sw_info_t;
+
+/*
+ * struct vxge_hal_device_stats_sw_info_t - HAL own per-device statistics.
+ *
+ * @soft_reset_cnt: Number of times soft reset is done on this device.
+ * @vpath_info: please see vxge_hal_vpath_stats_sw_info_t {}
+ * HAL per-device statistics.
+ */
+typedef struct vxge_hal_device_stats_sw_info_t {
+	u32	soft_reset_cnt;
+	vxge_hal_vpath_stats_sw_info_t vpath_info[VXGE_HAL_MAX_VIRTUAL_PATHS];
+} vxge_hal_device_stats_sw_info_t;
+
+/*
+ * struct vxge_hal_device_stats_sw_err_t - HAL device error statistics.
+ * @mrpcim_alarms: Number of mrpcim alarms
+ * @srpcim_alarms: Number of srpcim alarms
+ * @vpath_alarms: Number of vpath alarms
+ *
+ * HAL Device error stats
+ */
+typedef struct vxge_hal_device_stats_sw_err_t {
+	u32	mrpcim_alarms;
+	u32	srpcim_alarms;
+	u32	vpath_alarms;
+} vxge_hal_device_stats_sw_err_t;
+
+/*
+ * struct vxge_hal_device_stats_t - Contains HAL per-device statistics,
+ * including hw.
+ * @devh: HAL device handle.
+ *
+ * @hw_dev_info_stats: X3100 statistics maintained by the hardware.
+ * @sw_dev_err_stats: HAL's "soft" device error statistics.
+ * @sw_dev_info_stats: HAL's "soft" device informational statistics, e.g. number
+ *			of completions per interrupt.
+ *
+ * @is_enabled: True, if device stats collection is enabled.
+ *
+ * Structure-container of HAL per-device statistics. Note that per-channel
+ * statistics are kept in separate structures under HAL's fifo and ring
+ * channels.
+ */
+typedef struct vxge_hal_device_stats_t {
+	/* handles */
+	vxge_hal_device_h		devh;
+
+	/* HAL device hardware statistics */
+	vxge_hal_device_stats_hw_info_t	hw_dev_info_stats;
+
+	/* HAL device "soft" stats */
+	vxge_hal_device_stats_sw_err_t  sw_dev_err_stats;
+	vxge_hal_device_stats_sw_info_t sw_dev_info_stats;
+
+	/* flags */
+	int				is_enabled;
+} vxge_hal_device_stats_t;
+
+/*
+ * vxge_hal_vpath_hw_stats_enable - Enable vpath h/w statistics.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Enable the DMA vpath statistics. The function is to be called to re-enable
+ * the adapter to update stats into the host memory
+ *
+ * See also: vxge_hal_vpath_hw_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_hw_stats_enable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_hw_stats_disable - Disable vpath h/w statistics.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Enable the DMA vpath statistics. The function is to be called to disable
+ * the adapter to update stats into the host memory. This function is not
+ * needed to be called, normally.
+ *
+ * See also: vxge_hal_vpath_hw_stats_enable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_hw_stats_disable(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_vpath_hw_stats_get - Get the vpath hw statistics.
+ * @vpath_handle: Virtual Path handle.
+ * @hw_stats: Hardware stats
+ *
+ * Returns the vpath h/w stats.
+ *
+ * See also: vxge_hal_vpath_hw_stats_enable(), vxge_hal_vpath_hw_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_hw_stats_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_stats_hw_info_t *hw_stats);
+
+/*
+ * vxge_hal_vpath_sw_stats_get - Get the vpath sw statistics.
+ * @vpath_handle: Virtual Path handle.
+ * @sw_stats: Software stats
+ *
+ * Returns the vpath s/w stats.
+ *
+ * See also: vxge_hal_vpath_hw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_sw_stats_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_stats_sw_info_t *sw_stats);
+
+/*
+ * vxge_hal_vpath_stats_access - Get the statistics from the given location
+ *			  and offset and perform an operation
+ * @vpath_handle: Virtual path handle.
+ * @operation: Operation to be performed
+ * @offset: Offset with in the location
+ * @stat: Pointer to a buffer to return the value
+ *
+ * Get the statistics from the given location and offset.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_stats_access(
+    vxge_hal_vpath_h vpath_handle,
+    u32 operation,
+    u32 offset,
+    u64 *stat);
+
+/*
+ * vxge_hal_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
+ * @virtual_path: vpath handle.
+ * @vpath_tx_stats: Buffer to return TX Statistics of vpath.
+ *
+ * Get the TX Statistics of a vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_xmac_tx_stats_get(vxge_hal_vpath_h virtual_path,
+    vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats);
+
+/*
+ * vxge_hal_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
+ * @virtual_path: vpath handle.
+ * @vpath_rx_stats: Buffer to return RX Statistics of vpath.
+ *
+ * Get the RX Statistics of a vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_xmac_rx_stats_get(vxge_hal_vpath_h virtual_path,
+    vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats);
+
+/*
+ * vxge_hal_vpath_stats_clear - Clear all the statistics of vpath
+ * @vpath_handle: Virtual path handle.
+ *
+ * Clear the statistics of the given vpath.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_stats_clear(
+    vxge_hal_vpath_h vpath_handle);
+
+/*
+ * vxge_hal_device_hw_stats_enable - Enable device h/w statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA vpath statistics for the device. The function is to be called
+ * to re-enable the adapter to update stats into the host memory
+ *
+ * See also: vxge_hal_device_hw_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_stats_enable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_hw_stats_disable - Disable device h/w statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA vpath statistics for the device. The function is to be called
+ * to disable the adapter to update stats into the host memory. This function
+ * is not needed to be called, normally.
+ *
+ * See also: vxge_hal_device_hw_stats_enable()
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_stats_disable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_device_hw_stats_get - Get the device hw statistics.
+ * @devh: HAL Device.
+ * @hw_stats: Hardware stats
+ *
+ * Returns the vpath h/w stats for the device.
+ *
+ * See also: vxge_hal_device_hw_stats_enable(),
+ *	     vxge_hal_device_hw_stats_disable(),
+ *	     vxge_hal_device_sw_stats_get(),
+ *	     vxge_hal_device_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_device_stats_hw_info_t *hw_stats);
+
+/*
+ * vxge_hal_device_sw_stats_get - Get the device sw statistics.
+ * @devh: HAL Device.
+ * @sw_stats: Software stats
+ *
+ * Returns the device s/w stats for the device.
+ *
+ * See also: vxge_hal_device_hw_stats_get(), vxge_hal_device_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_device_sw_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_device_stats_sw_info_t *sw_stats);
+
+/*
+ * vxge_hal_device_stats_get - Get the device statistics.
+ * @devh: HAL Device.
+ * @stats: Device stats
+ *
+ * Returns the device stats for the device.
+ *
+ * See also: vxge_hal_device_hw_stats_get(), vxge_hal_device_sw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_device_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_device_stats_t *stats);
+
+/*
+ * vxge_hal_device_xmac_stats_get - Get the XMAC Statistics
+ * @devh: HAL device handle.
+ * @xmac_stats: Buffer to return XMAC Statistics.
+ *
+ * Get the XMAC Statistics
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_xmac_stats_get(vxge_hal_device_h devh,
+    vxge_hal_device_xmac_stats_t *xmac_stats);
+
+/*
+ * vxge_hal_mrpcim_stats_enable - Enable mrpcim statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA mrpcim statistics for the device. The function is to be called
+ * to re-enable the adapter to update stats into the host memory
+ *
+ * See also: vxge_hal_mrpcim_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_enable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_stats_disable - Disable mrpcim statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA mrpcim statistics for the device. The function is to be called
+ * to disable the adapter to update stats into the host memory. This function
+ * is not needed to be called, normally.
+ *
+ * See also: vxge_hal_mrpcim_stats_enable()
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_disable(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_stats_get - Get the mrpcim statistics.
+ * @devh: HAL Device.
+ * @stats: mrpcim stats
+ *
+ * Returns the device mrpcim stats for the device.
+ *
+ * See also: vxge_hal_device_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_mrpcim_stats_hw_info_t *stats);
+
+/*
+ * vxge_hal_mrpcim_stats_access - Access the statistics from the given location
+ *			  and offset and perform an operation
+ * @devh: HAL Device handle.
+ * @operation: Operation to be performed
+ * @location: Location (one of vpath id, aggregate or port)
+ * @offset: Offset with in the location
+ * @stat: Pointer to a buffer to return the value
+ *
+ * Get the statistics from the given location and offset.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_access(
+    vxge_hal_device_h devh,
+    u32 operation,
+    u32 location,
+    u32 offset,
+    u64 *stat);
+
+/*
+ * vxge_hal_mrpcim_xmac_aggr_stats_get - Get the Statistics on aggregate port
+ * @devh: HAL device handle.
+ * @port: Number of the port (0 or 1)
+ * @aggr_stats: Buffer to return Statistics on aggregate port.
+ *
+ * Get the Statistics on aggregate port
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xmac_aggr_stats_get(vxge_hal_device_h devh,
+    u32 port,
+    vxge_hal_xmac_aggr_stats_t *aggr_stats);
+
+/*
+ * vxge_hal_mrpcim_xmac_port_stats_get - Get the Statistics on a port
+ * @devh: HAL device handle.
+ * @port: Number of the port (wire 0, wire 1 or LAG)
+ * @port_stats: Buffer to return Statistics on a port.
+ *
+ * Get the Statistics on port
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xmac_port_stats_get(vxge_hal_device_h devh,
+    u32 port,
+    vxge_hal_xmac_port_stats_t *port_stats);
+
+/*
+ * vxge_hal_mrpcim_xmac_stats_get - Get the XMAC Statistics
+ * @devh: HAL device handle.
+ * @xmac_stats: Buffer to return XMAC Statistics.
+ *
+ * Get the XMAC Statistics
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xmac_stats_get(vxge_hal_device_h devh,
+    vxge_hal_mrpcim_xmac_stats_t *xmac_stats);
+
+/*
+ * vxge_hal_mrpcim_stats_clear - Clear the statistics of the device
+ * @devh: HAL Device handle.
+ *
+ * Clear the statistics of the given Device.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_clear(
+    vxge_hal_device_h devh);
+
+/*
+ * vxge_hal_mrpcim_xpak_stats_poll -  Poll and update the Xpak error count.
+ * @devh: HAL device handle
+ * @port: Port number
+ *
+ * It is used to update the xpak stats value. Called by ULD periodically
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xpak_stats_poll(
+    vxge_hal_device_h devh, u32 port);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_STATS_H */
diff --git a/sys/dev/vxge/include/vxgehal-status.h b/sys/dev/vxge/include/vxgehal-status.h
new file mode 100644
index 000000000000..851974f9dfbe
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-status.h
@@ -0,0 +1,1112 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_STATUS_H
+#define	VXGE_HAL_STATUS_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	VXGE_HAL_EVENT_BASE				0
+#define	VXGE_LL_EVENT_BASE				100
+
+/*
+ * enum vxge_hal_event_e - Enumerates slow-path HAL events.
+ * @VXGE_HAL_EVENT_UNKNOWN: Unknown (and invalid) event.
+ * @VXGE_HAL_EVENT_SERR: Serious hardware error event.
+ * @VXGE_HAL_EVENT_CRITICAL: Critical vpath hardware error event.
+ * @VXGE_HAL_EVENT_ECCERR: vpath ECC error event.
+ * @VXGE_HAL_EVENT_KDFCCTL: FIFO Doorbell fifo error.
+ * @VXGE_HAL_EVENT_SRPCIM_CRITICAL: srpcim hardware error event.
+ * @VXGE_HAL_EVENT_MRPCIM_CRITICAL: mrpcim hardware error event.
+ * @VXGE_HAL_EVENT_MRPCIM_ECCERR: mrpcim ecc error event.
+ * @VXGE_HAL_EVENT_DEVICE_RESET_START: Privileged entity starting device reset
+ * @VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE: Device reset has been completed
+ * @VXGE_HAL_EVENT_VPATH_RESET_START: A function is starting vpath reset
+ * @VXGE_HAL_EVENT_VPATH_RESET_COMPLETE: vpath reset has been completed
+ * @VXGE_HAL_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
+ * slot-freeze from the rest critical events (e.g. ECC) when it is
+ * impossible to PIO read "through" the bus, i.e. when getting all-foxes.
+ *
+ * vxge_hal_event_e enumerates slow-path HAL eventis.
+ *
+ * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_up_f {},
+ * vxge_uld_link_down_f {}.
+ */
+typedef enum vxge_hal_event_e {
+	VXGE_HAL_EVENT_UNKNOWN			= 0,
+	/* HAL events */
+	VXGE_HAL_EVENT_SERR			= VXGE_HAL_EVENT_BASE + 1,
+	VXGE_HAL_EVENT_CRITICAL			= VXGE_HAL_EVENT_BASE + 2,
+	VXGE_HAL_EVENT_ECCERR			= VXGE_HAL_EVENT_BASE + 3,
+	VXGE_HAL_EVENT_KDFCCTL			= VXGE_HAL_EVENT_BASE + 4,
+	VXGE_HAL_EVENT_SRPCIM_CRITICAL		= VXGE_HAL_EVENT_BASE + 5,
+	VXGE_HAL_EVENT_MRPCIM_CRITICAL		= VXGE_HAL_EVENT_BASE + 6,
+	VXGE_HAL_EVENT_MRPCIM_ECCERR		= VXGE_HAL_EVENT_BASE + 7,
+	VXGE_HAL_EVENT_DEVICE_RESET_START	= VXGE_HAL_EVENT_BASE + 8,
+	VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE	= VXGE_HAL_EVENT_BASE + 9,
+	VXGE_HAL_EVENT_VPATH_RESET_START	= VXGE_HAL_EVENT_BASE + 10,
+	VXGE_HAL_EVENT_VPATH_RESET_COMPLETE	= VXGE_HAL_EVENT_BASE + 11,
+	VXGE_HAL_EVENT_SLOT_FREEZE		= VXGE_HAL_EVENT_BASE + 12
+} vxge_hal_event_e;
+
+#define	VXGE_HAL_BASE_INF	100
+#define	VXGE_HAL_BASE_ERR	200
+#define	VXGE_HAL_BASE_BADCFG	300
+
+/*
+ * enum vxge_hal_status_e - HAL return codes.
+ * @VXGE_HAL_OK: Success.
+ * @VXGE_HAL_FAIL: Failure.
+ * @VXGE_HAL_PENDING: Opearation is pending
+ * @VXGE_HAL_CONTINUE: Continue processing
+ * @VXGE_HAL_RETURN: Stop processing and return
+ * @VXGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel.
+ *	  (specific to polling mode completion processing).
+ * @VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed
+ * descriptors. See vxge_hal_fifo_txdl_next_completed().
+ * @VXGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel
+ * descriptors
+ *	  are reserved (via vxge_hal_fifo_txdl_reserve(),
+ *	  vxge_hal_ring_rxd_reserve())
+ *	  and not yet freed (via vxge_hal_fifo_txdl_free(),
+ *	  vxge_hal_ring_rxd_free()).
+ * @VXGE_HAL_INF_QUEUE_IS_NOT_READY: A descriptor was reserved and not posted
+ * @VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to
+ * poll until PIO is executed.
+ * @VXGE_HAL_INF_STATS_IS_NOT_READY: Queue is not ready for
+ * operation.
+ * @VXGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to
+ * reserve. Internal use only.
+ * @VXGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel
+ * callback when instructed to exit descriptor processing loop
+ * prematurely. Typical usage: polling mode of processing completed
+ * descriptors.
+ *	  Upon getting LRO_ISED, ll driver shall
+ *	  1) initialise lro struct with mbuf if sg_num == 1.
+ *	  2) else it will update m_data_ptr_of_mbuf to tcp pointer and
+ *	  append the new mbuf to the tail of mbuf chain in lro struct.
+ * @VXGE_HAL_INF_SW_LRO_BEGIN: Returned by ULD LRO module, when new LRO is
+ * being initiated.
+ * @VXGE_HAL_INF_SW_LRO_CONT: Returned by ULD LRO module, when new frame
+ * is appended at the end of existing LRO.
+ * @VXGE_HAL_INF_SW_LRO_UNCAPABLE: Returned by ULD LRO module, when new
+ * frame is not LRO capable.
+ * @VXGE_HAL_INF_SW_LRO_FLUSH_SESSION: Returned by ULD LRO module,
+ * when new frame triggers LRO flush.
+ * @VXGE_HAL_INF_SW_LRO_FLUSH_BOTH: Returned by ULD LRO module, when new
+ * frame triggers LRO flush. Lro frame should be flushed first then
+ * new frame should be flushed next.
+ * @VXGE_HAL_INF_SW_LRO_END_3: Returned by ULD LRO module, when new
+ * frame triggers close of current LRO session and opening of new LRO session
+ * with the frame.
+ * @VXGE_HAL_INF_SW_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no
+ * more LRO sessions can be added.
+ * @VXGE_HAL_INF_NOT_ENOUGH_HW_CQES: Enough CQEs are available
+ * @VXGE_HAL_INF_LINK_UP_DOWN: Link up down indication received
+ * @VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized.
+ * @VXGE_HAL_ERR_INVALID_HANDLE: The handle passed is invalid.
+ * @VXGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and
+ * allocating descriptors).
+ * @VXGE_HAL_ERR_VPATH_NOT_AVAILABLE: Vpath is not allocated to this
+ * function
+ * @VXGE_HAL_ERR_VPATH_NOT_OPEN: Vpath is not opened i.e put in service.
+ * @VXGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is
+ * invoked not because of the X3100-generated interrupt.
+ * @VXGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to
+ * configure more than VXGE_HAL_MAX_MAC_ADDRESSES  mac addresses.
+ * @VXGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed
+ * to set X3100 byte swapper in accordnace with the host
+ * endian-ness.
+ * @VXGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to
+ * a "quiescent" state.
+ * @VXGE_HAL_ERR_INVALID_MTU_SIZE:Returned when MTU size specified by
+ * caller is not in the (64, 9600) range.
+ * @VXGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory.
+ * @VXGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we
+ * check for zero/non-zero only.)
+ * @VXGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. X3100 supports two Base
+ * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1).
+ * @VXGE_HAL_ERR_INVALID_INDEX: Invalid index. Example, attempt to read
+ * register value from the register section that is out of range.
+ * @VXGE_HAL_ERR_INVALID_TYPE: Invalid register section.
+ * @VXGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read
+ * register value (with offset) outside of the register section range
+ * @VXGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle
+ * (passed by ULD) is invalid.
+ * @VXGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by
+ * management "get" routines when the retrieved information does
+ * not fit into the provided buffer.
+ * @VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size.
+ * @VXGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions)
+ * are not compatible.
+ * @VXGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address.
+ * @VXGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID.
+ * @VXGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments
+ * in a scatter-gather list.
+ * @VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized.
+ * Typically means wrong sequence of API calls.
+ * @VXGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled.
+ * @VXGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full.
+ * @VXGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry.
+ * @VXGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the
+ * SPDM table.
+ * @VXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in
+ * synch ith the actual one.
+ * @VXGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI  parameters.
+ * @VXGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs
+ * (including vxge_hal_fifo_handle_tcode() and vxge_hal_ring_handle_tcode())
+ * on: ECC, parity, SERR.
+ * Also returned when PIO read does not go through ("all-foxes")
+ * because of "slot-freeze".
+ * @VXGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device.
+ * Returned by vxge_hal_device_reset(). One circumstance when it could
+ * happen: slot freeze by the system (see @VXGE_HAL_ERR_CRITICAL).
+ * @VXGE_HAL_ERR_TOO_MANY: This error is returned if there were laready
+ * maximum number of sessions or queues allocated
+ * @VXGE_HAL_ERR_PKT_DROP: Packet got dropped
+ * @VXGE_HAL_ERR_INVALID_BLOCK_SIZE: Invalid block size
+ * @VXGE_HAL_ERR_INVALID_STATE: Invalid state
+ * @VXGE_HAL_ERR_PRIVILAGED_OPEARATION: A previleged operation is attempted
+ * @VXGE_HAL_ERR_RESET_IN_PROGRESS: Reset is currently in progress
+ * @VXGE_HAL_ERR_MAC_TABLE_FULL: DA table is full
+ * @VXGE_HAL_ERR_MAC_TABLE_EMPTY: DA table is empty
+ * @VXGE_HAL_ERR_MAC_TABLE_NO_MORE_ENTRIES: There are no more entries in the
+ *		DA table
+ * @VXGE_HAL_ERR_RTDMA_RTDMA_READY: RTDMA is ready
+ * @VXGE_HAL_ERR_WRDMA_WRDMA_READY: WRDMA is ready
+ * @VXGE_HAL_ERR_KDFC_KDFC_READY: Kernel mode doorbell controller ready
+ * @VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY: Transmit Protocol Assist TMAC buffer empty
+ * @VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT: PIC block is quiescent
+ * @VXGE_HAL_ERR_XGMAC_NETWORK_FAULT: Network Fault
+ * @VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT: ROCRC offload quiescent
+ * @VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY: G3DDR Interface FB Ready
+ * @VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY: G3DDR Interface CM Ready
+ * @VXGE_HAL_ERR_RIC_RIC_RUNNING: Adapter RIC is still programming flash
+ *		settings to device
+ * @VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK: CMG C PLL in lock
+ * @VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK: XGMAC X PLL in Lock
+ * @VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK: FBUF M PLL in Lock
+ * @VXGE_HAL_ERR_PCC_PCC_IDLE: PCC is idle
+ * @VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT: ROCRC RC PCC quiescent
+ * @VXGE_HAL_ERR_SLOT_FREEZE: PCI Slot frozen
+ * @VXGE_HAL_ERR_INVALID_TCODE: The t-code returned is invalid
+ * @VXGE_HAL_ERR_INVALID_PORT: The port number specified is invalid
+ * @VXGE_HAL_ERR_INVALID_PRIORITY: Proiority specified is invalid
+ * @VXGE_HAL_ERR_INVALID_MIN_BANDWIDTH: Minimum bandwidth specified is invalid
+ * @VXGE_HAL_ERR_INVALID_MAX_BANDWIDTH: Maximum bandwidth specified is invalid
+ * @VXGE_HAL_ERR_INVALID_BANDWIDTH_LIMIT: Bandwidth limit specified is invalid
+ * @VXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTH: Total bandwidth specified is invalid
+ * @VXGE_HAL_ERR_MANAGER_NOT_FOUND: The Function 0 driver or MRPCIM manager is
+ *		down
+ * @VXGE_HAL_ERR_TIME_OUT: Timeout occurred
+ * @VXGE_HAL_ERR_EVENT_UNKNOWN: Unknown alarm
+ * @VXGE_HAL_ERR_EVENT_SERR: Serious error on device
+ * @VXGE_HAL_ERR_EVENT_CRITICAL: Critical error in the vpath
+ * @VXGE_HAL_ERR_EVENT_ECCERR: Ecc Error returned in t-code
+ * @VXGE_HAL_ERR_EVENT_KDFCCTL: Kdfcctl error on the device
+ * @VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL: Critical error in SRPCIM
+ * @VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL: Critical error in MRPCIM
+ * @VXGE_HAL_ERR_EVENT_MRPCIM_ECCERR: ECC error in MRPCIM
+ * @VXGE_HAL_ERR_EVENT_RESET_START: Device is going to be reset
+ * @VXGE_HAL_ERR_EVENT_RESET_COMPLETE: Device reset is complete
+ * @VXGE_HAL_ERR_EVENT_SLOT_FREEZE: PCI Slot freeze
+ * @VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID: Invalid port id in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA: Invalid media type in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU: Invalid initial MTU size
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE: Invalid autonegotiation mode
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE: Invalid autonegotiation rate
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM: Invalid fixed use fsm in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM: Invalid ANTP use FSM in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM: Invalid ANBE use FSM in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD: Invalid link stability
+ *		period in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD: Invalid port stability
+ *		period in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN: Invalid Transmit MAC enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN: Invalid Receive MAC enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD: Invalid Transmit MAC PAD enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE: Invalid Transmit MAC PAD Byte
+ *		setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD: Invalid Transmit MAC utilization
+ *		period in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS: Invalid Receive MAC strip FCS
+ *		setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN: Invalid Receive MAC PROM enable
+ *		in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM: Invalid Receive MAC discard
+ *		pfrm setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD: Invalid Receive MAC utilization
+ *		period in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN: Invalid Receive MAC pause
+ *		generation enable setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN: Invalid Receive MAC pause
+ *		receive enable setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME: Invalid Receive MAC high ptime
+ *		setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN: Invalid Receive MAC pause
+ *		limitter enable setting in config
+ * @VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT: Invalid Receive MAC max limit
+ *		setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU: Invalid initial MTU size
+ *		in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN: Invalid Transmit MAC enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN: Invalid Receive MAC enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD: Invalid Transmit MAC PAD enable
+ *		setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE: Invalid Transmit MAC PAD Byte
+ *		setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD: Invalid Transmit MAC
+ *		utilization period in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS: Invalid Receive MAC strip FCS
+ *		setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN: Invalid Receive MAC PROM enable
+ *		in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM: Invalid Receive MAC discard
+ *		pfrm setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD: Invalid Receive MAC
+ *		utilization period in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN: Invalid Receive MAC
+ *		pause generation enable setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN: Invalid Receive MAC
+ *		pause receive enable setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME: Invalid Receive MAC
+ *		high ptime setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN: Invalid Receive MAC pause
+ *		limitter enable setting in config
+ * @VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT: Invalid Receive MAC
+ *		max limit setting in config
+ * @VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD: Invalid network
+ *		stability period setting in config
+ * @VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD: Invalid MC pause threshold
+ *		setting in config
+ * @VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN: Invalid perma stop enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS: Invalid Transmit MAC
+ *		tx switch disable in config
+ * @VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN: Invalid Transmit MAC
+ *		lossy switch enable in config
+ * @VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN: Invalid Transmit MAC
+ *		lossy wire enable in config
+ * @VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS: Invalid Transmit
+ *		MAC broadcast to wire disable in config
+ * @VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS: Invalid Transmit
+ *		MAC broadcast to switch disable in config
+ * @VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN: Invalid Transmit MAC
+ *		host append fcs in config
+ * @VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N: Invalid Transmit Protocol
+ *		Assist support SNAP AB N setting in config
+ * @VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N: Invalid Transmit Protocol
+ *		Assist ecc enable N setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR: Invalid Receive Protocol
+ *		Assist ignore frame error in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N: Invalid Receive Protocol Assist
+ *		SNAP AB N in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO: Invalid Receive Protocol
+ *		Assist search for HAO in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS: Invalid Receive
+ *		Protocol support ipv6 mobile headers in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING: Invalid Receive Protocol
+ *		Assist ipv6 stop searching in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN: Invalid Receive Protocol
+ *		Assist no ps if unknown in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE: Invalid Receive Protocol
+ *		Assist search for etype in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM: Invalid Receive Protocol
+ *		Assist replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF: Invalid Receive Protocol Assist
+ *		replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM: Invalid Receive Protocol Assist
+ *		replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH: Invalid Receive Protocol
+ *		Assist replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH: Invalid Receive Protocol
+ *		Assist replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH: Invalid Receive Protocol
+ *		Assist replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH: Invalid Receive Protocol
+ *		Assist replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF: Invalid Receive Protocol Assist
+ *		replication setting in config
+ * @VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG: Invalid Receive Protocol
+ *		Assist replication setting in config
+ * @VXGE_HAL_BADCFG_LAG_LAG_EN: Invalid option for lag_en in config
+ * @VXGE_HAL_BADCFG_LAG_LAG_MODE: Invalid option for lag_mode in config
+ * @VXGE_HAL_BADCFG_LAG_TX_DISCARD: Invalid option for tx_discard in config
+ * @VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS: Invalid option for incr_tx_aggr_stats
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL: Invalid option for distrib_alg_sel
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL: Invalid option for
+ *		distrib_remap_if_fail in config
+ * @VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY: Invalid Collector Max Delay in config
+ * @VXGE_HAL_BADCFG_LAG_RX_DISCARD: Invalid option for rx_discard in config
+ * @VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT: Invalid option for pref_indiv_port
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_HOT_STANDBY: Invalid option for hot_standby in config
+ * @VXGE_HAL_BADCFG_LAG_LACP_DECIDES: Invalid option for lacp_decides in config
+ * @VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT: Invalid option for pref_active_port
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK: Invalid option for auto_failback
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_FAILBACK_EN: Invalid option for failback_en in config
+ * @VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT: Invalid cold_failover_timeout
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_LACP_EN: Invalid option for lacp_en in config
+ * @VXGE_HAL_BADCFG_LAG_LACP_BEGIN: Invalid option for lacp_begin in config
+ * @VXGE_HAL_BADCFG_LAG_DISCARD_LACP: Invalid option for discard_lacp in config
+ * @VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK: Invalid option for liberal_len_chk
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN: Invalid option for
+ *		marker_gen_recv_en in config
+ * @VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN: Invalid option for marker_resp_en
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT: Invalid option for
+ *		marker_resp_timeout in config
+ * @VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL: Invalid option for
+ *		slow_proto_mrkr_min_interval in config
+ * @VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP: Invalid option for
+ *		throttle_mrkr_resp in config
+ * @VXGE_HAL_BADCFG_LAG_SYS_PRI: Invalid system priority in config
+ * @VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR: Invalid option for
+ *		use_port_mac_addr in config
+ * @VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL: Invalid option for mac_addr_sel in config
+ * @VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY: Invalid alterneate admin key in config
+ * @VXGE_HAL_BADCFG_LAG_ALT_AGGR: Invalid option for alt_aggr in config
+ * @VXGE_HAL_BADCFG_LAG_FAST_PER_TIME: Invalid fast periodic time in config
+ * @VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME: Invalid slow periodic time in config
+ * @VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT: Invalid short timeout in config
+ * @VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT: Invalid long timeout in config
+ * @VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME: Invalid churn detection time in config
+ * @VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME: Invalid Aggregator wait time in config
+ * @VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE: Invalid short timer scale in config
+ * @VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE: Invalid long timer scale in config
+ * @VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID: Invalid Aggregator Id in config
+ * @VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR: Invalid option for
+ *		use_port_mac_addr in config
+ * @VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL: Invalid option for mac_addr_sel
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY: Invalid admin key in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PORT_ID: Invalid port id in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_LAG_EN: Invalid option for lag_en in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO: Invalid option for
+ *		discard_slow_proto in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR: Invalid option for
+ *		host_chosen_aggr in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO: Invalid option
+ *		for discard unknown slow proto in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM: Invalid Actor port number in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY: Invalid Actor port priority
+ *		in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G: Invalid Actor 10G key in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G: Invalid Actor 1G key in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY: Invalid option for
+ *		actor_lacp_activity in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT: Invalid option for
+ *		actor_lacp_timeout in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION: Invalid option for
+ *		actor_aggregation in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION: Invalid option
+ *		for actor_synchronization in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING: Invalid option for
+ *		actor_collecting in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING: Invalid option for
+ *		actor_distributing in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED: Invalid option for
+ *		actor_defaulted in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED: Invalid option for
+ *		actor_expired in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI: Invalid option for
+ *		partner_sys_pri in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY: Invalid option for
+ *		partner_key in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM: Invalid option for
+ *		partner_port_num in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY: Invalid option for
+ *		partner_port_pri in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY: Invalid option for
+ *		partner_lacp_activity in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT: Invalid option for
+ *		partner_lacp_timeout in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION: Invalid option for
+ *		partner_aggregation in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION: Invalid option for
+ *		partner_synchronization in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING: Invalid option for
+ *		partner_collecting in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING: Invalid option for
+ *		partner_distributing in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED: Invalid option for
+ *		partner_defaulted in config
+ * @VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED: Invalid option for
+ *		partner_expired in config
+ * @VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY: Invalid vpath priority
+ * @VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH: Invalid minimum bandwidth
+ * @VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH: Invalid maximum bandwidth
+ * @VXGE_HAL_BADCFG_LOG_LEVEL: Invalid option for partner_mac_addr in config
+ * @VXGE_HAL_BADCFG_RING_ENABLE: Invalid option for ring enable in config
+ * @VXGE_HAL_BADCFG_RING_LENGTH: Invalid ring length in config in config
+ * @VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE: Invalid receive buffer mode in config
+ * @VXGE_HAL_BADCFG_RING_SCATTER_MODE: Invalid scatter mode setting in config
+ * @VXGE_HAL_BADCFG_RING_POST_MODE: Invalid post mode setting in config
+ * @VXGE_HAL_BADCFG_RING_MAX_FRM_LEN: Invalid max frame length setting in config
+ * @VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL: Invalid no snoop all setting in config
+ * @VXGE_HAL_BADCFG_RING_TIMER_VAL: Invalid timer value setting in config
+ * @VXGE_HAL_BADCFG_RING_GREEDY_RETURN: Invalid grredy return setting in config
+ * @VXGE_HAL_BADCFG_RING_TIMER_CI: Invalid timer ci setting in config
+ * @VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US: Invalid backoff interval
+ *		in microseconds setting in config
+ * @VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid indicate maximum packets
+ *		setting in config
+ * @VXGE_HAL_BADCFG_FIFO_ENABLE: Invalid option for FIFO enable in config
+ * @VXGE_HAL_BADCFG_FIFO_LENGTH: Invalid FIFO length in config
+ * @VXGE_HAL_BADCFG_FIFO_FRAGS: Invalid number of transmit frame fragments
+ *		in config
+ * @VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE: Invalid alignment size in config
+ * @VXGE_HAL_BADCFG_FIFO_MAX_FRAGS: Invalid maximum number of transmit frame
+ *		fragments in config
+ * @VXGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid FIFO queue interrupt setting
+ *		in config
+ * @VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL: Invalid FIFO no snoop all setting
+ *		in config
+ * @VXGE_HAL_BADCFG_DMQ_LENGTH: Invalid DMQ length setting in config
+ * @VXGE_HAL_BADCFG_DMQ_IMMED_EN: Invalid DMQ immediate enable setting in config
+ * @VXGE_HAL_BADCFG_DMQ_EVENT_EN: Invalid DMQ event enable setting in config
+ * @VXGE_HAL_BADCFG_DMQ_INTR_CTRL: Invalid DMQ interrupt control setting
+ *		in config
+ * @VXGE_HAL_BADCFG_DMQ_GEN_COMPL: Invalid DMQ general completion setting
+ *		in config
+ * @VXGE_HAL_BADCFG_UMQ_LENGTH: Invalid UMQ length setting in config
+ * @VXGE_HAL_BADCFG_UMQ_IMMED_EN: Invalid UMQ immediate enable setting in config
+ * @VXGE_HAL_BADCFG_UMQ_EVENT_EN: Invalid UMQ event enable setting in config
+ * @VXGE_HAL_BADCFG_UMQ_INTR_CTRL: Invalid UMQ interrupt control setting
+ *		in config
+ * @VXGE_HAL_BADCFG_UMQ_GEN_COMPL: Invalid UMQ general completion setting
+ *		in config
+ * @VXGE_HAL_BADCFG_SW_LRO_SESSIONS: Invalid number of SW LRO sessions
+ *		setting in config
+ * @VXGE_HAL_BADCFG_SW_LRO_SG_SIZE: Invalid SW LRO Segment size
+ * @VXGE_HAL_BADCFG_SW_LRO_FRM_LEN: Invalid SW LRO Frame Length
+ * @VXGE_HAL_BADCFG_SW_LRO_MODE: Invalid SW LRO mode setting in config
+ * @VXGE_HAL_BADCFG_LRO_SESSIONS_MAX: Invalid maximum number of LRO sessions
+ *		setting in config
+ * @VXGE_HAL_BADCFG_LRO_SESSIONS_THRESHOLD: Invalid sessions number threshold
+ *		setting in config
+ * @VXGE_HAL_BADCFG_LRO_SESSIONS_TIMEOUT: Invalid sessions timeout setting
+ *		in config
+ * @VXGE_HAL_BADCFG_LRO_NO_WQE_THRESHOLD: Invalid lower limit for number
+ *		of WQEs in config
+ * @VXGE_HAL_BADCFG_LRO_DUPACK_DETECTION: Invalid option for
+ *		dupack_detection_enabled in config
+ * @VXGE_HAL_BADCFG_LRO_DATA_MERGING: Invalid option for
+ *		data_merging_enabled in config
+ * @VXGE_HAL_BADCFG_LRO_ACK_MERGING: Invalid option for
+ *		ack_merging_enabled in config
+ * @VXGE_HAL_BADCFG_LRO_LLC_HDR_MODE: Invalid LLC Header Mode
+ * @VXGE_HAL_BADCFG_LRO_SNAP_HDR_MODE: Invalid SNAP Header Mode
+ * @VXGE_HAL_BADCFG_LRO_SESSION_ECN: Invalid option for session_ecn_enabled
+ * @VXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCE: Invalid option for
+ *		session_ecn_enabled_nonce
+ * @VXGE_HAL_BADCFG_LRO_RXD_BUFFER_MODE: Invalid buffer mode
+ * @VXGE_HAL_BADCFG_LRO_SCATTER_MODE: Invalid scatter mode
+ * @VXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZE: Invalid IP Datagram size
+ * @VXGE_HAL_BADCFG_LRO_FRAME_THRESHOLD: Invalid Frame Threshold
+ * @VXGE_HAL_BADCFG_LRO_PSH_THRESHOLD: Invalid push Threshold
+ * @VXGE_HAL_BADCFG_LRO_MTU_THRESHOLD: Invalid MTU Threshold
+ * @VXGE_HAL_BADCFG_LRO_MSS_THRESHOLD: Invalid MSS Threshold
+ * @VXGE_HAL_BADCFG_LRO_TCP_TSVAL_DELTA: Invalid TXP TSVAL DELTA
+ * @VXGE_HAL_BADCFG_LRO_ACK_NBR_DELTA: Invalid Acknowledgement delta
+ * @VXGE_HAL_BADCFG_LRO_SPARE_WQE_CAPACITY: Invalid Spare WQE Capacity
+ * @VXGE_HAL_BADCFG_TIM_INTR_ENABLE: Invalid TIM interrupt enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_TIM_BTIMER_VAL: Invalid TIM btimer value setting in config
+ * @VXGE_HAL_BADCFG_TIM_TIMER_AC_EN: Invalid TIM timer ac enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_TIM_TIMER_CI_EN: Invalid Tx timer continuous interrupt
+ * enable. See the structure vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_TIMER_RI_EN: Invalid TIM timer ri enable setting
+ *		in config
+ * @VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF: Invalid TIM btimer event sf seting
+ *		in config
+ * @VXGE_HAL_BADCFG_TIM_RTIMER_VAL: Invalid TIM rtimer setting in config
+ * @VXGE_HAL_BADCFG_TIM_UTIL_SEL: Invalid TIM utilization setting in config
+ * @VXGE_HAL_BADCFG_TIM_LTIMER_VAL: Invalid TIM ltimer value setting in config
+ * @VXGE_HAL_BADCFG_TXFRM_CNT_EN: Invalid transmit frame count enable in config
+ * @VXGE_HAL_BADCFG_TXD_CNT_EN: Invalid transmit count enable in config
+ * @VXGE_HAL_BADCFG_TIM_URANGE_A: Invalid link utilization range A. See
+ * the structure vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_UEC_A: Invalid frame count for link utilization
+ * range A. See the structure vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_URANGE_B: Invalid link utilization range B. See
+ * the structure vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_UEC_B: Invalid frame count for link utilization
+ * range B. See the strucuture  vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_URANGE_C: Invalid link utilization range C. See
+ * the structure  vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_UEC_C: Invalid frame count for link utilization
+ * range C. See the structure vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_TIM_UEC_D: Invalid frame count for link utilization
+ * range D. See the structure  vxge_hal_tim_intr_config_t {} for valid values.
+ * @VXGE_HAL_BADCFG_VPATH_ID: Invalid vpath id in config
+ * @VXGE_HAL_BADCFG_VPATH_WIRE_PORT: Invalid wire port to be used
+ * @VXGE_HAL_BADCFG_VPATH_NO_SNOOP: Invalid vpath no snoop setting in config
+ * @VXGE_HAL_BADCFG_VPATH_MTU: Invalid vpath mtu size setting in config
+ * @VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN: Invalid vpath transmit protocol assist
+ *		lso v2 en setting in config
+ * @VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR: Invalid vpath transmit
+ *		protocol assist ignore frame error setting in config
+ * @VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING: Invalid vpath transmit
+ *		protocol assist ipv6 keep searching setting in config
+ * @VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT: Invalid vpath transmit protocol
+ *		assist L4 pseudo header present setting in config
+ * @VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS: Invalid vpath transmit
+ *		protocol assist support mobile ipv6 headers setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH: Invalid vpath receive protocol
+ *		assist ipv4 tcp include pseudo header setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH: Invalid vpath receive protocol
+ *		assist ipv6 tcp include pseudo header setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH: Invalid vpath receive protocol
+ *		assist ipv4 udp include pseudo header setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_IPV6_UDP_INCL_PH: Invalid vpath receive protocol
+ *		assist ipv6 udp include pseudo header setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF: Invalid vpath receive protocol assist
+ *		layer 4 include cf setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG: Invalid vpath receive protocol
+ *		assist strip vlan tag setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM: Invalid vpath receive protocol
+ *		assist layer 4 compute check sum setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF: Invalid vpath receive protocol
+ *		assist layer 3 include cf setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM: Invalid vpath receive protocol
+ *		assist layer 3 compute check sum setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN: Invalid vpath receive protocol
+ *		assist unicast all address enable setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN: Invalid vpath receive protocol
+ *		assist multi-icast all address enable setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN: Invalid vpath receive protocol assist
+ *		cast enable setting in config
+ * @VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN: Invalid vpath receive protocol
+ *		assist all vlan ids enable setting in config
+ * @VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW: Invalid Q l2 flow setting in config
+ * @VXGE_HAL_BADCFG_VPATH_VP_STATS_READ_METHOD: Invalid Stats read method
+ * @VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT: Invalid bandwidth limit
+ * @VXGE_HAL_BADCFG_BLOCKPOOL_MIN: Invalid minimum number of block pool blocks
+ *		setting in config
+ * @VXGE_HAL_BADCFG_BLOCKPOOL_INITIAL: Invalid initial number of block pool
+ *		blocks setting in config
+ * @VXGE_HAL_BADCFG_BLOCKPOOL_INCR: Invalid number of block pool blocks
+ *		increment setting in config
+ * @VXGE_HAL_BADCFG_BLOCKPOOL_MAX: Invalid maximum number of block pool
+ *		blocks setting in config
+ * @VXGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count setting in config
+ * @VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE: Invalid maximum payload size setting
+ *		in config
+ * @VXGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count setting in config
+ * @VXGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid stats refresh time setting
+ *		in config
+ * @VXGE_HAL_BADCFG_DUMP_ON_SERR: Invalid dump on serr setting in config
+ * @VXGE_HAL_BADCFG_DUMP_ON_CRITICAL: Invalid dump on critical error setting
+ *		config
+ * @VXGE_HAL_BADCFG_DUMP_ON_ECCERR: Invalid dump on ecc error setting config
+ * @VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN: Invalid dump on unknown alarm setting
+ *		config
+ * @VXGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode setting in config
+ * @VXGE_HAL_BADCFG_RTH_EN: Invalid rth enable setting in config
+ * @VXGE_HAL_BADCFG_RTH_IT_TYPE: Invalid rth it type setting in config
+ * @VXGE_HAL_BADCFG_UFCA_INTR_THRES: Invalid rxufca interrupt threshold
+ *		setting in config
+ * @VXGE_HAL_BADCFG_UFCA_LO_LIM: Invalid rxufca low limit setting in config
+ * @VXGE_HAL_BADCFG_UFCA_HI_LIM: Invalid rxufca high limit setting in config
+ * @VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD: Invalid rxufca lbolt period in config
+ * @VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll timeout
+ *		in milliseconds setting in config
+ * @VXGE_HAL_BADCFG_RTS_MAC_EN: Invalid rts mac enable setting in config
+ * @VXGE_HAL_BADCFG_RTS_QOS_EN: Invalid rts qos enable setting in config
+ * @VXGE_HAL_BADCFG_RTS_PORT_EN: Invalid rts port enable setting in config
+ * @VXGE_HAL_BADCFG_MAX_CQE_GROUPS: Invalid maximum number of CQE groups
+ *		in config
+ * @VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS: Invalid maximum number of OD groups
+ *		in config
+ * @VXGE_HAL_BADCFG_NO_WQE_THRESHOLD: Invalid no wqe threshold setting
+ *		in config
+ * @VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH: Invalid refill threshold setting
+ *		in config
+ * @VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW: Invalid refill threshold setting
+ *		in config
+ * @VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT: Invalid acknowledgement block setting
+ *		in config
+ * @VXGE_HAL_BADCFG_STATS_READ_METHOD: Invalid stats read method
+ * @VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL: Invalid poll or doorbell setting
+ *		in config
+ * @VXGE_HAL_BADCFG_MSIX_ID: Invalid MSIX Id
+ * @VXGE_HAL_EOF_TRACE_BUF: Invalid end of trace buffer setting in config
+ *
+ */
+typedef enum vxge_hal_status_e {
+	VXGE_HAL_OK				 = 0,
+	VXGE_HAL_FAIL				 = 1,
+	VXGE_HAL_PENDING			 = 2,
+	VXGE_HAL_CONTINUE			 = 3,
+	VXGE_HAL_RETURN				 = 4,
+	VXGE_HAL_COMPLETIONS_REMAIN		 = 5,
+	VXGE_HAL_TRAFFIC_INTERRUPT		 = 6,
+
+	VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HAL_BASE_INF + 1,
+	VXGE_HAL_INF_OUT_OF_DESCRIPTORS		 = VXGE_HAL_BASE_INF + 2,
+	VXGE_HAL_INF_QUEUE_IS_NOT_READY		 = VXGE_HAL_BASE_INF + 4,
+	VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING	 = VXGE_HAL_BASE_INF + 5,
+	VXGE_HAL_INF_STATS_IS_NOT_READY		 = VXGE_HAL_BASE_INF + 6,
+	VXGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS	 = VXGE_HAL_BASE_INF + 7,
+	VXGE_HAL_INF_IRQ_POLLING_CONTINUE	 = VXGE_HAL_BASE_INF + 8,
+	VXGE_HAL_INF_SW_LRO_BEGIN		 = VXGE_HAL_BASE_INF + 9,
+	VXGE_HAL_INF_SW_LRO_CONT		 = VXGE_HAL_BASE_INF + 10,
+	VXGE_HAL_INF_SW_LRO_UNCAPABLE		 = VXGE_HAL_BASE_INF + 11,
+	VXGE_HAL_INF_SW_LRO_FLUSH_SESSION	 = VXGE_HAL_BASE_INF + 12,
+	VXGE_HAL_INF_SW_LRO_FLUSH_BOTH		 = VXGE_HAL_BASE_INF + 13,
+	VXGE_HAL_INF_SW_LRO_END_3		 = VXGE_HAL_BASE_INF + 14,
+	VXGE_HAL_INF_SW_LRO_SESSIONS_XCDED	 = VXGE_HAL_BASE_INF + 15,
+	VXGE_HAL_INF_NOT_ENOUGH_HW_CQES		 = VXGE_HAL_BASE_INF + 16,
+	VXGE_HAL_INF_LINK_UP_DOWN		 = VXGE_HAL_BASE_INF + 17,
+
+	VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED	 = VXGE_HAL_BASE_ERR + 1,
+	VXGE_HAL_ERR_INVALID_HANDLE		 = VXGE_HAL_BASE_ERR + 2,
+	VXGE_HAL_ERR_OUT_OF_MEMORY		 = VXGE_HAL_BASE_ERR + 3,
+	VXGE_HAL_ERR_VPATH_NOT_AVAILABLE	 = VXGE_HAL_BASE_ERR + 4,
+	VXGE_HAL_ERR_VPATH_NOT_OPEN		 = VXGE_HAL_BASE_ERR + 5,
+	VXGE_HAL_ERR_WRONG_IRQ			 = VXGE_HAL_BASE_ERR + 6,
+	VXGE_HAL_ERR_OUT_OF_MAC_ADDRESSES	 = VXGE_HAL_BASE_ERR + 7,
+	VXGE_HAL_ERR_SWAPPER_CTRL		 = VXGE_HAL_BASE_ERR + 8,
+	VXGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT	 = VXGE_HAL_BASE_ERR + 9,
+	VXGE_HAL_ERR_INVALID_MTU_SIZE		 = VXGE_HAL_BASE_ERR + 10,
+	VXGE_HAL_ERR_OUT_OF_MAPPING		 = VXGE_HAL_BASE_ERR + 11,
+	VXGE_HAL_ERR_BAD_SUBSYSTEM_ID		 = VXGE_HAL_BASE_ERR + 12,
+	VXGE_HAL_ERR_INVALID_BAR_ID		 = VXGE_HAL_BASE_ERR + 13,
+	VXGE_HAL_ERR_INVALID_INDEX		 = VXGE_HAL_BASE_ERR + 14,
+	VXGE_HAL_ERR_INVALID_TYPE		 = VXGE_HAL_BASE_ERR + 15,
+	VXGE_HAL_ERR_INVALID_OFFSET		 = VXGE_HAL_BASE_ERR + 16,
+	VXGE_HAL_ERR_INVALID_DEVICE		 = VXGE_HAL_BASE_ERR + 17,
+	VXGE_HAL_ERR_OUT_OF_SPACE		 = VXGE_HAL_BASE_ERR + 18,
+	VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE	 = VXGE_HAL_BASE_ERR + 19,
+	VXGE_HAL_ERR_VERSION_CONFLICT		 = VXGE_HAL_BASE_ERR + 20,
+	VXGE_HAL_ERR_INVALID_MAC_ADDRESS	 = VXGE_HAL_BASE_ERR + 21,
+	VXGE_HAL_ERR_BAD_DEVICE_ID		 = VXGE_HAL_BASE_ERR + 22,
+	VXGE_HAL_ERR_OUT_ALIGNED_FRAGS		 = VXGE_HAL_BASE_ERR + 23,
+	VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED	 = VXGE_HAL_BASE_ERR + 24,
+	VXGE_HAL_ERR_SPDM_NOT_ENABLED		 = VXGE_HAL_BASE_ERR + 25,
+	VXGE_HAL_ERR_SPDM_TABLE_FULL		 = VXGE_HAL_BASE_ERR + 26,
+	VXGE_HAL_ERR_SPDM_INVALID_ENTRY		 = VXGE_HAL_BASE_ERR + 27,
+	VXGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND	 = VXGE_HAL_BASE_ERR + 28,
+	VXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT = VXGE_HAL_BASE_ERR + 29,
+	VXGE_HAL_ERR_INVALID_PCI_INFO		 = VXGE_HAL_BASE_ERR + 30,
+	VXGE_HAL_ERR_CRITICAL			 = VXGE_HAL_BASE_ERR + 31,
+	VXGE_HAL_ERR_RESET_FAILED		 = VXGE_HAL_BASE_ERR + 32,
+	VXGE_HAL_ERR_TOO_MANY			 = VXGE_HAL_BASE_ERR + 33,
+	VXGE_HAL_ERR_PKT_DROP			 = VXGE_HAL_BASE_ERR + 34,
+	VXGE_HAL_ERR_INVALID_BLOCK_SIZE		 = VXGE_HAL_BASE_ERR + 35,
+	VXGE_HAL_ERR_INVALID_STATE		 = VXGE_HAL_BASE_ERR + 36,
+	VXGE_HAL_ERR_PRIVILAGED_OPEARATION	 = VXGE_HAL_BASE_ERR + 37,
+	VXGE_HAL_ERR_RESET_IN_PROGRESS		 = VXGE_HAL_BASE_ERR + 38,
+	VXGE_HAL_ERR_MAC_TABLE_FULL		 = VXGE_HAL_BASE_ERR + 39,
+	VXGE_HAL_ERR_MAC_TABLE_EMPTY		 = VXGE_HAL_BASE_ERR + 40,
+	VXGE_HAL_ERR_MAC_TABLE_NO_MORE_ENTRIES	 = VXGE_HAL_BASE_ERR + 41,
+	VXGE_HAL_ERR_RTDMA_RTDMA_READY		 = VXGE_HAL_BASE_ERR + 42,
+	VXGE_HAL_ERR_WRDMA_WRDMA_READY		 = VXGE_HAL_BASE_ERR + 43,
+	VXGE_HAL_ERR_KDFC_KDFC_READY		 = VXGE_HAL_BASE_ERR + 44,
+	VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY		 = VXGE_HAL_BASE_ERR + 45,
+	VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT	 = VXGE_HAL_BASE_ERR + 46,
+	VXGE_HAL_ERR_XGMAC_NETWORK_FAULT	 = VXGE_HAL_BASE_ERR + 47,
+	VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT	 = VXGE_HAL_BASE_ERR + 48,
+	VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY  = VXGE_HAL_BASE_ERR + 49,
+	VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY  = VXGE_HAL_BASE_ERR + 50,
+	VXGE_HAL_ERR_RIC_RIC_RUNNING		 = VXGE_HAL_BASE_ERR + 51,
+	VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK		 = VXGE_HAL_BASE_ERR + 52,
+	VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK	 = VXGE_HAL_BASE_ERR + 53,
+	VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK		 = VXGE_HAL_BASE_ERR + 54,
+	VXGE_HAL_ERR_PCC_PCC_IDLE		 = VXGE_HAL_BASE_ERR + 55,
+	VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT	 = VXGE_HAL_BASE_ERR + 56,
+	VXGE_HAL_ERR_SLOT_FREEZE		 = VXGE_HAL_BASE_ERR + 57,
+	VXGE_HAL_ERR_INVALID_TCODE		 = VXGE_HAL_BASE_ERR + 58,
+	VXGE_HAL_ERR_INVALID_PORT		 = VXGE_HAL_BASE_ERR + 59,
+	VXGE_HAL_ERR_INVALID_WIRE_PORT		 = VXGE_HAL_BASE_ERR + 60,
+	VXGE_HAL_ERR_INVALID_PRIORITY		 = VXGE_HAL_BASE_ERR + 61,
+	VXGE_HAL_ERR_INVALID_MIN_BANDWIDTH	 = VXGE_HAL_BASE_ERR + 62,
+	VXGE_HAL_ERR_INVALID_MAX_BANDWIDTH	 = VXGE_HAL_BASE_ERR + 63,
+	VXGE_HAL_ERR_INVALID_BANDWIDTH_LIMIT	 = VXGE_HAL_BASE_ERR + 64,
+	VXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTH	 = VXGE_HAL_BASE_ERR + 65,
+	VXGE_HAL_ERR_MANAGER_NOT_FOUND		 = VXGE_HAL_BASE_ERR + 66,
+	VXGE_HAL_ERR_TIME_OUT			 = VXGE_HAL_BASE_ERR + 67,
+	VXGE_HAL_ERR_EVENT_UNKNOWN		 = VXGE_HAL_BASE_ERR + 68,
+	VXGE_HAL_ERR_EVENT_SERR			 = VXGE_HAL_BASE_ERR + 69,
+	VXGE_HAL_ERR_EVENT_CRITICAL		 = VXGE_HAL_BASE_ERR + 70,
+	VXGE_HAL_ERR_EVENT_ECCERR		 = VXGE_HAL_BASE_ERR + 71,
+	VXGE_HAL_ERR_EVENT_KDFCCTL		 = VXGE_HAL_BASE_ERR + 72,
+	VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL	 = VXGE_HAL_BASE_ERR + 73,
+	VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL	 = VXGE_HAL_BASE_ERR + 74,
+	VXGE_HAL_ERR_EVENT_MRPCIM_ECCERR	 = VXGE_HAL_BASE_ERR + 75,
+	VXGE_HAL_ERR_EVENT_RESET_START		 = VXGE_HAL_BASE_ERR + 76,
+	VXGE_HAL_ERR_EVENT_RESET_COMPLETE	 = VXGE_HAL_BASE_ERR + 77,
+	VXGE_HAL_ERR_EVENT_SLOT_FREEZE		 = VXGE_HAL_BASE_ERR + 78,
+	VXGE_HAL_ERR_INVALID_DP_MODE		 = VXGE_HAL_BASE_ERR + 79,
+	VXGE_HAL_ERR_INVALID_L2_SWITCH_STATE	 = VXGE_HAL_BASE_ERR + 79,
+
+	VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID	 = VXGE_HAL_BASE_BADCFG + 1,
+	VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA	 = VXGE_HAL_BASE_BADCFG + 2,
+	VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU = VXGE_HAL_BASE_BADCFG + 3,
+	VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE	 = VXGE_HAL_BASE_BADCFG + 4,
+	VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE	 = VXGE_HAL_BASE_BADCFG + 5,
+	VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM	 = VXGE_HAL_BASE_BADCFG + 6,
+	VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM	 = VXGE_HAL_BASE_BADCFG + 7,
+	VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM	 = VXGE_HAL_BASE_BADCFG + 8,
+	VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD =
+						    VXGE_HAL_BASE_BADCFG + 9,
+	VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD =
+						    VXGE_HAL_BASE_BADCFG + 10,
+	VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN	 = VXGE_HAL_BASE_BADCFG + 11,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN	 = VXGE_HAL_BASE_BADCFG + 12,
+	VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD	 = VXGE_HAL_BASE_BADCFG + 13,
+	VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE	 = VXGE_HAL_BASE_BADCFG + 14,
+	VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD = VXGE_HAL_BASE_BADCFG + 15,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS  = VXGE_HAL_BASE_BADCFG + 16,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN	 = VXGE_HAL_BASE_BADCFG + 18,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM = VXGE_HAL_BASE_BADCFG + 19,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD = VXGE_HAL_BASE_BADCFG + 20,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN = VXGE_HAL_BASE_BADCFG + 21,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN = VXGE_HAL_BASE_BADCFG + 22,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME = VXGE_HAL_BASE_BADCFG + 23,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN =
+						    VXGE_HAL_BASE_BADCFG + 24,
+	VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT  = VXGE_HAL_BASE_BADCFG + 25,
+	VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU = VXGE_HAL_BASE_BADCFG + 26,
+	VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN	 = VXGE_HAL_BASE_BADCFG + 27,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN	 = VXGE_HAL_BASE_BADCFG + 28,
+	VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD	 = VXGE_HAL_BASE_BADCFG + 29,
+	VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE  = VXGE_HAL_BASE_BADCFG + 30,
+	VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD =
+						    VXGE_HAL_BASE_BADCFG + 31,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS  = VXGE_HAL_BASE_BADCFG + 32,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN  = VXGE_HAL_BASE_BADCFG + 33,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM =
+						    VXGE_HAL_BASE_BADCFG + 34,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD =
+						    VXGE_HAL_BASE_BADCFG + 35,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN =
+						    VXGE_HAL_BASE_BADCFG + 36,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN =
+						    VXGE_HAL_BASE_BADCFG + 37,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME = VXGE_HAL_BASE_BADCFG + 38,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN =
+						    VXGE_HAL_BASE_BADCFG + 39,
+	VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT  = VXGE_HAL_BASE_BADCFG + 40,
+	VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD =
+						    VXGE_HAL_BASE_BADCFG + 41,
+	VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 42,
+	VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN	 = VXGE_HAL_BASE_BADCFG + 43,
+	VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS	 = VXGE_HAL_BASE_BADCFG + 44,
+	VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN  = VXGE_HAL_BASE_BADCFG + 45,
+	VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN	 = VXGE_HAL_BASE_BADCFG + 46,
+	VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS = VXGE_HAL_BASE_BADCFG + 47,
+	VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS =
+						    VXGE_HAL_BASE_BADCFG + 48,
+	VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN = VXGE_HAL_BASE_BADCFG + 49,
+	VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N  = VXGE_HAL_BASE_BADCFG + 50,
+	VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N	 = VXGE_HAL_BASE_BADCFG + 51,
+	VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR  = VXGE_HAL_BASE_BADCFG + 52,
+	VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N	 = VXGE_HAL_BASE_BADCFG + 53,
+	VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO	 = VXGE_HAL_BASE_BADCFG + 54,
+	VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS =
+						    VXGE_HAL_BASE_BADCFG + 55,
+	VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING = VXGE_HAL_BASE_BADCFG + 56,
+	VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN  = VXGE_HAL_BASE_BADCFG + 57,
+	VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE  = VXGE_HAL_BASE_BADCFG + 58,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM  = VXGE_HAL_BASE_BADCFG + 59,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF	 = VXGE_HAL_BASE_BADCFG + 60,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM  = VXGE_HAL_BASE_BADCFG + 61,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH =
+						    VXGE_HAL_BASE_BADCFG + 62,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH =
+						    VXGE_HAL_BASE_BADCFG + 63,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH =
+						    VXGE_HAL_BASE_BADCFG + 64,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH =
+						    VXGE_HAL_BASE_BADCFG + 65,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF	= VXGE_HAL_BASE_BADCFG + 66,
+	VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG = VXGE_HAL_BASE_BADCFG + 67,
+
+	VXGE_HAL_BADCFG_LAG_LAG_EN		 = VXGE_HAL_BASE_BADCFG + 101,
+	VXGE_HAL_BADCFG_LAG_LAG_MODE		 = VXGE_HAL_BASE_BADCFG + 102,
+	VXGE_HAL_BADCFG_LAG_TX_DISCARD		 = VXGE_HAL_BASE_BADCFG + 103,
+	VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS	 = VXGE_HAL_BASE_BADCFG + 104,
+	VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL	 = VXGE_HAL_BASE_BADCFG + 105,
+	VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL = VXGE_HAL_BASE_BADCFG + 106,
+	VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY	= VXGE_HAL_BASE_BADCFG + 107,
+	VXGE_HAL_BADCFG_LAG_RX_DISCARD		 = VXGE_HAL_BASE_BADCFG + 108,
+	VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT	 = VXGE_HAL_BASE_BADCFG + 109,
+	VXGE_HAL_BADCFG_LAG_HOT_STANDBY		 = VXGE_HAL_BASE_BADCFG + 110,
+	VXGE_HAL_BADCFG_LAG_LACP_DECIDES	 = VXGE_HAL_BASE_BADCFG + 111,
+	VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT	 = VXGE_HAL_BASE_BADCFG + 112,
+	VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK	 = VXGE_HAL_BASE_BADCFG + 113,
+	VXGE_HAL_BADCFG_LAG_FAILBACK_EN		 = VXGE_HAL_BASE_BADCFG + 114,
+	VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT = VXGE_HAL_BASE_BADCFG + 115,
+	VXGE_HAL_BADCFG_LAG_LACP_EN		 = VXGE_HAL_BASE_BADCFG + 116,
+	VXGE_HAL_BADCFG_LAG_LACP_BEGIN		 = VXGE_HAL_BASE_BADCFG + 117,
+	VXGE_HAL_BADCFG_LAG_DISCARD_LACP	 = VXGE_HAL_BASE_BADCFG + 118,
+	VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK	 = VXGE_HAL_BASE_BADCFG + 119,
+	VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN	 = VXGE_HAL_BASE_BADCFG + 120,
+	VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN	 = VXGE_HAL_BASE_BADCFG + 121,
+	VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT	 = VXGE_HAL_BASE_BADCFG + 122,
+	VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL =
+						VXGE_HAL_BASE_BADCFG + 123,
+	VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP	 = VXGE_HAL_BASE_BADCFG + 124,
+	VXGE_HAL_BADCFG_LAG_SYS_PRI		 = VXGE_HAL_BASE_BADCFG + 125,
+	VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR	 = VXGE_HAL_BASE_BADCFG + 126,
+	VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL	 = VXGE_HAL_BASE_BADCFG + 127,
+	VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY	 = VXGE_HAL_BASE_BADCFG + 128,
+	VXGE_HAL_BADCFG_LAG_ALT_AGGR		 = VXGE_HAL_BASE_BADCFG + 129,
+	VXGE_HAL_BADCFG_LAG_FAST_PER_TIME	 = VXGE_HAL_BASE_BADCFG + 130,
+	VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME	 = VXGE_HAL_BASE_BADCFG + 131,
+	VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT	 = VXGE_HAL_BASE_BADCFG + 132,
+	VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT	 = VXGE_HAL_BASE_BADCFG + 133,
+	VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME	 = VXGE_HAL_BASE_BADCFG + 134,
+	VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME	 = VXGE_HAL_BASE_BADCFG + 135,
+	VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE	 = VXGE_HAL_BASE_BADCFG + 136,
+	VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE	 = VXGE_HAL_BASE_BADCFG + 137,
+	VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID	 = VXGE_HAL_BASE_BADCFG + 138,
+	VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR = VXGE_HAL_BASE_BADCFG + 139,
+	VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL	 = VXGE_HAL_BASE_BADCFG + 140,
+	VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY	 = VXGE_HAL_BASE_BADCFG + 141,
+	VXGE_HAL_BADCFG_LAG_PORT_PORT_ID	 = VXGE_HAL_BASE_BADCFG + 142,
+	VXGE_HAL_BADCFG_LAG_PORT_LAG_EN		 = VXGE_HAL_BASE_BADCFG + 143,
+	VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO =
+						VXGE_HAL_BASE_BADCFG + 144,
+	VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR = VXGE_HAL_BASE_BADCFG + 145,
+	VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO =
+						VXGE_HAL_BASE_BADCFG + 146,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM = VXGE_HAL_BASE_BADCFG + 147,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY =
+						VXGE_HAL_BASE_BADCFG + 148,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G	= VXGE_HAL_BASE_BADCFG + 149,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G	 = VXGE_HAL_BASE_BADCFG + 150,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY =
+						VXGE_HAL_BASE_BADCFG + 151,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT =
+						VXGE_HAL_BASE_BADCFG + 152,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION = VXGE_HAL_BASE_BADCFG + 153,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION =
+						VXGE_HAL_BASE_BADCFG + 154,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING = VXGE_HAL_BASE_BADCFG + 155,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING =
+						VXGE_HAL_BASE_BADCFG + 156,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED  = VXGE_HAL_BASE_BADCFG + 157,
+	VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED	= VXGE_HAL_BASE_BADCFG + 158,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI  = VXGE_HAL_BASE_BADCFG + 159,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY	  = VXGE_HAL_BASE_BADCFG + 160,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM	  = VXGE_HAL_BASE_BADCFG + 161,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY =
+						VXGE_HAL_BASE_BADCFG + 162,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY =
+						VXGE_HAL_BASE_BADCFG + 163,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT =
+						VXGE_HAL_BASE_BADCFG + 164,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION =
+						VXGE_HAL_BASE_BADCFG + 165,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION =
+						VXGE_HAL_BASE_BADCFG + 166,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING =
+						VXGE_HAL_BASE_BADCFG + 167,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING =
+						VXGE_HAL_BASE_BADCFG + 168,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED  =
+						VXGE_HAL_BASE_BADCFG + 169,
+	VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED  =
+						VXGE_HAL_BASE_BADCFG + 170,
+	VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY	 = VXGE_HAL_BASE_BADCFG + 171,
+	VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH  = VXGE_HAL_BASE_BADCFG + 172,
+	VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH  = VXGE_HAL_BASE_BADCFG + 173,
+
+	VXGE_HAL_BADCFG_LOG_LEVEL		 = VXGE_HAL_BASE_BADCFG + 202,
+	VXGE_HAL_BADCFG_RING_ENABLE		 = VXGE_HAL_BASE_BADCFG + 203,
+	VXGE_HAL_BADCFG_RING_LENGTH		 = VXGE_HAL_BASE_BADCFG + 204,
+	VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE	 = VXGE_HAL_BASE_BADCFG + 205,
+	VXGE_HAL_BADCFG_RING_SCATTER_MODE	 = VXGE_HAL_BASE_BADCFG + 206,
+	VXGE_HAL_BADCFG_RING_POST_MODE		 = VXGE_HAL_BASE_BADCFG + 207,
+	VXGE_HAL_BADCFG_RING_MAX_FRM_LEN	 = VXGE_HAL_BASE_BADCFG + 208,
+	VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL	 = VXGE_HAL_BASE_BADCFG + 209,
+	VXGE_HAL_BADCFG_RING_TIMER_VAL		 = VXGE_HAL_BASE_BADCFG + 210,
+	VXGE_HAL_BADCFG_RING_GREEDY_RETURN	 = VXGE_HAL_BASE_BADCFG + 211,
+	VXGE_HAL_BADCFG_RING_TIMER_CI		 = VXGE_HAL_BASE_BADCFG + 212,
+	VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US  = VXGE_HAL_BASE_BADCFG + 213,
+	VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS	 = VXGE_HAL_BASE_BADCFG + 214,
+	VXGE_HAL_BADCFG_FIFO_ENABLE		 = VXGE_HAL_BASE_BADCFG + 215,
+	VXGE_HAL_BADCFG_FIFO_LENGTH		 = VXGE_HAL_BASE_BADCFG + 216,
+	VXGE_HAL_BADCFG_FIFO_FRAGS		 = VXGE_HAL_BASE_BADCFG + 217,
+	VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE	 = VXGE_HAL_BASE_BADCFG + 218,
+	VXGE_HAL_BADCFG_FIFO_MAX_FRAGS		 = VXGE_HAL_BASE_BADCFG + 219,
+	VXGE_HAL_BADCFG_FIFO_QUEUE_INTR		 = VXGE_HAL_BASE_BADCFG + 220,
+	VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL	 = VXGE_HAL_BASE_BADCFG + 221,
+	VXGE_HAL_BADCFG_DMQ_LENGTH		 = VXGE_HAL_BASE_BADCFG + 222,
+	VXGE_HAL_BADCFG_DMQ_IMMED_EN		 = VXGE_HAL_BASE_BADCFG + 223,
+	VXGE_HAL_BADCFG_DMQ_EVENT_EN		 = VXGE_HAL_BASE_BADCFG + 224,
+	VXGE_HAL_BADCFG_DMQ_INTR_CTRL		 = VXGE_HAL_BASE_BADCFG + 225,
+	VXGE_HAL_BADCFG_DMQ_GEN_COMPL		 = VXGE_HAL_BASE_BADCFG + 226,
+	VXGE_HAL_BADCFG_UMQ_LENGTH		 = VXGE_HAL_BASE_BADCFG + 227,
+	VXGE_HAL_BADCFG_UMQ_IMMED_EN		 = VXGE_HAL_BASE_BADCFG + 228,
+	VXGE_HAL_BADCFG_UMQ_EVENT_EN		 = VXGE_HAL_BASE_BADCFG + 229,
+	VXGE_HAL_BADCFG_UMQ_INTR_CTRL		 = VXGE_HAL_BASE_BADCFG + 230,
+	VXGE_HAL_BADCFG_UMQ_GEN_COMPL		 = VXGE_HAL_BASE_BADCFG + 231,
+	VXGE_HAL_BADCFG_SW_LRO_SESSIONS		 = VXGE_HAL_BASE_BADCFG + 232,
+	VXGE_HAL_BADCFG_SW_LRO_SG_SIZE		 = VXGE_HAL_BASE_BADCFG + 333,
+	VXGE_HAL_BADCFG_SW_LRO_FRM_LEN		 = VXGE_HAL_BASE_BADCFG + 334,
+	VXGE_HAL_BADCFG_SW_LRO_MODE		 = VXGE_HAL_BASE_BADCFG + 235,
+	VXGE_HAL_BADCFG_LRO_SESSIONS_MAX	 = VXGE_HAL_BASE_BADCFG + 236,
+	VXGE_HAL_BADCFG_LRO_SESSIONS_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 237,
+	VXGE_HAL_BADCFG_LRO_SESSIONS_TIMEOUT	 = VXGE_HAL_BASE_BADCFG + 238,
+	VXGE_HAL_BADCFG_LRO_NO_WQE_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 239,
+	VXGE_HAL_BADCFG_LRO_DUPACK_DETECTION	 = VXGE_HAL_BASE_BADCFG + 242,
+	VXGE_HAL_BADCFG_LRO_DATA_MERGING	 = VXGE_HAL_BASE_BADCFG + 243,
+	VXGE_HAL_BADCFG_LRO_ACK_MERGING		 = VXGE_HAL_BASE_BADCFG + 244,
+	VXGE_HAL_BADCFG_LRO_LLC_HDR_MODE	 = VXGE_HAL_BASE_BADCFG + 245,
+	VXGE_HAL_BADCFG_LRO_SNAP_HDR_MODE	 = VXGE_HAL_BASE_BADCFG + 246,
+	VXGE_HAL_BADCFG_LRO_SESSION_ECN		 = VXGE_HAL_BASE_BADCFG + 247,
+	VXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCE	 = VXGE_HAL_BASE_BADCFG + 248,
+	VXGE_HAL_BADCFG_LRO_RXD_BUFFER_MODE	 = VXGE_HAL_BASE_BADCFG + 249,
+	VXGE_HAL_BADCFG_LRO_SCATTER_MODE	 = VXGE_HAL_BASE_BADCFG + 250,
+	VXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZE	 = VXGE_HAL_BASE_BADCFG + 251,
+	VXGE_HAL_BADCFG_LRO_FRAME_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 252,
+	VXGE_HAL_BADCFG_LRO_PSH_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 253,
+	VXGE_HAL_BADCFG_LRO_MTU_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 254,
+	VXGE_HAL_BADCFG_LRO_MSS_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 255,
+	VXGE_HAL_BADCFG_LRO_TCP_TSVAL_DELTA	 = VXGE_HAL_BASE_BADCFG + 256,
+	VXGE_HAL_BADCFG_LRO_ACK_NBR_DELTA	 = VXGE_HAL_BASE_BADCFG + 257,
+	VXGE_HAL_BADCFG_LRO_SPARE_WQE_CAPACITY	 = VXGE_HAL_BASE_BADCFG + 258,
+	VXGE_HAL_BADCFG_TIM_INTR_ENABLE		 = VXGE_HAL_BASE_BADCFG + 259,
+	VXGE_HAL_BADCFG_TIM_BTIMER_VAL		 = VXGE_HAL_BASE_BADCFG + 261,
+	VXGE_HAL_BADCFG_TIM_TIMER_AC_EN		 = VXGE_HAL_BASE_BADCFG + 262,
+	VXGE_HAL_BADCFG_TIM_TIMER_CI_EN		 = VXGE_HAL_BASE_BADCFG + 263,
+	VXGE_HAL_BADCFG_TIM_TIMER_RI_EN		 = VXGE_HAL_BASE_BADCFG + 264,
+	VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF	 = VXGE_HAL_BASE_BADCFG + 265,
+	VXGE_HAL_BADCFG_TIM_RTIMER_VAL		 = VXGE_HAL_BASE_BADCFG + 266,
+	VXGE_HAL_BADCFG_TIM_UTIL_SEL		 = VXGE_HAL_BASE_BADCFG + 267,
+	VXGE_HAL_BADCFG_TIM_LTIMER_VAL		 = VXGE_HAL_BASE_BADCFG + 268,
+	VXGE_HAL_BADCFG_TXFRM_CNT_EN		 = VXGE_HAL_BASE_BADCFG + 269,
+	VXGE_HAL_BADCFG_TXD_CNT_EN		 = VXGE_HAL_BASE_BADCFG + 270,
+	VXGE_HAL_BADCFG_TIM_URANGE_A		 = VXGE_HAL_BASE_BADCFG + 271,
+	VXGE_HAL_BADCFG_TIM_UEC_A		 = VXGE_HAL_BASE_BADCFG + 272,
+	VXGE_HAL_BADCFG_TIM_URANGE_B		 = VXGE_HAL_BASE_BADCFG + 273,
+	VXGE_HAL_BADCFG_TIM_UEC_B		 = VXGE_HAL_BASE_BADCFG + 274,
+	VXGE_HAL_BADCFG_TIM_URANGE_C		 = VXGE_HAL_BASE_BADCFG + 275,
+	VXGE_HAL_BADCFG_TIM_UEC_C		 = VXGE_HAL_BASE_BADCFG + 276,
+	VXGE_HAL_BADCFG_TIM_UEC_D		 = VXGE_HAL_BASE_BADCFG + 277,
+	VXGE_HAL_BADCFG_VPATH_ID		 = VXGE_HAL_BASE_BADCFG + 278,
+	VXGE_HAL_BADCFG_VPATH_WIRE_PORT		 = VXGE_HAL_BASE_BADCFG + 279,
+	VXGE_HAL_BADCFG_VPATH_NO_SNOOP		 = VXGE_HAL_BASE_BADCFG + 281,
+	VXGE_HAL_BADCFG_VPATH_MTU		 = VXGE_HAL_BASE_BADCFG + 282,
+	VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN	 = VXGE_HAL_BASE_BADCFG + 283,
+	VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR =
+						VXGE_HAL_BASE_BADCFG + 284,
+	VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING =
+						VXGE_HAL_BASE_BADCFG + 285,
+	VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT = VXGE_HAL_BASE_BADCFG + 286,
+	VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS =
+						VXGE_HAL_BASE_BADCFG + 287,
+	VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH = VXGE_HAL_BASE_BADCFG + 288,
+	VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH = VXGE_HAL_BASE_BADCFG + 289,
+	VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH = VXGE_HAL_BASE_BADCFG + 290,
+	VXGE_HAL_BADCFG_VPATH_RPA_IPV6_UDP_INCL_PH = VXGE_HAL_BASE_BADCFG + 291,
+	VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF	 = VXGE_HAL_BASE_BADCFG + 292,
+	VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG  = VXGE_HAL_BASE_BADCFG + 293,
+	VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM	 = VXGE_HAL_BASE_BADCFG + 294,
+	VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF	 = VXGE_HAL_BASE_BADCFG + 295,
+	VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM	 = VXGE_HAL_BASE_BADCFG + 296,
+	VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN =
+						VXGE_HAL_BASE_BADCFG + 297,
+	VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN =
+						VXGE_HAL_BASE_BADCFG + 298,
+	VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN	 = VXGE_HAL_BASE_BADCFG + 299,
+	VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN	 = VXGE_HAL_BASE_BADCFG + 300,
+	VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW	 = VXGE_HAL_BASE_BADCFG + 301,
+	VXGE_HAL_BADCFG_VPATH_VP_STATS_READ_METHOD = VXGE_HAL_BASE_BADCFG + 302,
+	VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT	 = VXGE_HAL_BASE_BADCFG + 305,
+	VXGE_HAL_BADCFG_BLOCKPOOL_MIN		 = VXGE_HAL_BASE_BADCFG + 306,
+	VXGE_HAL_BADCFG_BLOCKPOOL_INITIAL	 = VXGE_HAL_BASE_BADCFG + 307,
+	VXGE_HAL_BADCFG_BLOCKPOOL_INCR		 = VXGE_HAL_BASE_BADCFG + 308,
+	VXGE_HAL_BADCFG_BLOCKPOOL_MAX		 = VXGE_HAL_BASE_BADCFG + 309,
+	VXGE_HAL_BADCFG_ISR_POLLING_CNT		 = VXGE_HAL_BASE_BADCFG + 310,
+	VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE	 = VXGE_HAL_BASE_BADCFG + 312,
+	VXGE_HAL_BADCFG_MMRB_COUNT		 = VXGE_HAL_BASE_BADCFG + 313,
+	VXGE_HAL_BADCFG_STATS_REFRESH_TIME	 = VXGE_HAL_BASE_BADCFG + 314,
+	VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN		 = VXGE_HAL_BASE_BADCFG + 315,
+	VXGE_HAL_BADCFG_DUMP_ON_SERR		 = VXGE_HAL_BASE_BADCFG + 316,
+	VXGE_HAL_BADCFG_DUMP_ON_CRITICAL	 = VXGE_HAL_BASE_BADCFG + 317,
+	VXGE_HAL_BADCFG_DUMP_ON_ECCERR		 = VXGE_HAL_BASE_BADCFG + 318,
+	VXGE_HAL_BADCFG_INTR_MODE		 = VXGE_HAL_BASE_BADCFG + 319,
+	VXGE_HAL_BADCFG_RTH_EN			 = VXGE_HAL_BASE_BADCFG + 320,
+	VXGE_HAL_BADCFG_RTH_IT_TYPE		 = VXGE_HAL_BASE_BADCFG + 321,
+	VXGE_HAL_BADCFG_UFCA_INTR_THRES		 = VXGE_HAL_BASE_BADCFG + 323,
+	VXGE_HAL_BADCFG_UFCA_LO_LIM		 = VXGE_HAL_BASE_BADCFG + 324,
+	VXGE_HAL_BADCFG_UFCA_HI_LIM		 = VXGE_HAL_BASE_BADCFG + 325,
+	VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD	 = VXGE_HAL_BASE_BADCFG + 326,
+	VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS	 = VXGE_HAL_BASE_BADCFG + 327,
+	VXGE_HAL_BADCFG_RTS_MAC_EN		 = VXGE_HAL_BASE_BADCFG + 330,
+	VXGE_HAL_BADCFG_RTS_QOS_EN		 = VXGE_HAL_BASE_BADCFG + 331,
+	VXGE_HAL_BADCFG_RTS_PORT_EN		 = VXGE_HAL_BASE_BADCFG + 332,
+	VXGE_HAL_BADCFG_MAX_CQE_GROUPS		 = VXGE_HAL_BASE_BADCFG + 333,
+	VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS	 = VXGE_HAL_BASE_BADCFG + 334,
+	VXGE_HAL_BADCFG_NO_WQE_THRESHOLD	 = VXGE_HAL_BASE_BADCFG + 335,
+	VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH	 = VXGE_HAL_BASE_BADCFG + 336,
+	VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW	 = VXGE_HAL_BASE_BADCFG + 337,
+	VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT		 = VXGE_HAL_BASE_BADCFG + 338,
+	VXGE_HAL_BADCFG_STATS_READ_METHOD	 = VXGE_HAL_BASE_BADCFG + 339,
+	VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL	 = VXGE_HAL_BASE_BADCFG + 340,
+	VXGE_HAL_BADCFG_MSIX_ID			 = VXGE_HAL_BASE_BADCFG + 341,
+	VXGE_HAL_BADCFG_VPATH_PRIORITY		 = VXGE_HAL_BASE_BADCFG + 342,
+	VXGE_HAL_EOF_TRACE_BUF			 = -1
+
+} vxge_hal_status_e;
+
+/*
+ * enum vxge_hal_result_e - HAL Up Message result codes.
+ * @VXGE_HAL_RESULT_OK: Success
+ */
+typedef enum vxge_hal_result_e {
+	VXGE_HAL_RESULT_OK			 = 0
+} vxge_hal_result_e;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_STATUS_H */
diff --git a/sys/dev/vxge/include/vxgehal-types.h b/sys/dev/vxge/include/vxgehal-types.h
new file mode 100644
index 000000000000..04cb1284c604
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-types.h
@@ -0,0 +1,766 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_TYPES_H
+#define	VXGE_HAL_TYPES_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * enum vxge_hal_reopen_e - Open, close, or reopen option.
+ * @VXGE_HAL_RESET_ONLY: Do not (de)allocate
+ * @VXGE_HAL_OPEN_NORMAL: Do (de)allocate
+ *
+ * Enumerates options used with ring, fifo, sq, srq, cqrq, dmq and umq
+ * open and close operations. The @VXGE_HAL_RESET_ONLY can be used when
+ * resetting the device; in this case there is actually no need to free
+ * and then again malloc the memory (including DMA-able memory).
+ */
+typedef enum vxge_hal_reopen_e {
+	VXGE_HAL_RESET_ONLY	= 1,
+	VXGE_HAL_OPEN_NORMAL	= 2
+} vxge_hal_reopen_e;
+
+/*
+ * struct vxge_hal_version_t - HAL version info
+ * @version_major: Major version
+ * @version_minor: Minor version
+ * @version_fix: version fix
+ * @version_build: Version Build
+ *
+ * Structure to store version info
+ */
+typedef struct vxge_hal_version_t {
+	u32	version_major;
+	u32	version_minor;
+	u32	version_fix;
+	u32	version_build;
+} vxge_hal_version_t;
+
+/*
+ * VXGE_HAL_ETH_ALEN
+ */
+#define	VXGE_HAL_ETH_ALEN				6
+
+/*
+ * typedef macaddr_t - Ethernet address type
+ */
+typedef u8 macaddr_t[VXGE_HAL_ETH_ALEN];
+
+/*
+ * struct vxge_hal_ipv4 - IP version 4 address type
+ * @addr: IP address
+ */
+typedef struct vxge_hal_ipv4 {
+	u32	addr;
+} vxge_hal_ipv4;
+
+/*
+ * struct vxge_hal_ipv6 - IP version 6 address type
+ * @addr: IP address
+ */
+typedef struct vxge_hal_ipv6 {
+	u64	addr[2];
+} vxge_hal_ipv6;
+
+/*
+ * union vxge_hal_ipaddr_t - IP address type
+ * @ipv4: IP V4 address
+ * @ipv6: IP V6 address
+ */
+typedef union vxge_hal_ipaddr_t {
+	vxge_hal_ipv4 ipv4;
+	vxge_hal_ipv6 ipv6;
+} vxge_hal_ipaddr_t;
+
+/*
+ * typedef vxge_hal_obj_id_t - Object Id type used for Session,
+ *		  SRQ, CQRQ, STAG, LRO, SPDM etc objects
+ */
+typedef u64 vxge_hal_obj_id_t;
+
+/* basic handles */
+
+/*
+ * typedef vxge_hal_device_h - Handle to the adapter object
+ */
+typedef void *vxge_hal_device_h;
+
+/*
+ * typedef vxge_hal_vpath_h - Handle to the virtual path object returned to LL
+ */
+typedef void *vxge_hal_vpath_h;
+
+/*
+ * typedef vxge_hal_client_h - Handle passed by client for client's private data
+ */
+typedef void *vxge_hal_client_h;
+
+/*
+ * typedef vxge_hal_ring_h - Handle to the ring object used for non offload
+ *		receive
+ */
+typedef void *vxge_hal_ring_h;
+
+/*
+ * typedef vxge_hal_fifo_h - Handle to the fifo object used for non offload send
+ */
+typedef void *vxge_hal_fifo_h;
+
+
+/*
+ * typedef vxge_hal_txdl_h - Handle to the transmit desriptor list object used
+ *		for nonoffload send
+ */
+typedef void *vxge_hal_txdl_h;
+
+/*
+ * typedef vxge_hal_rxd_h - Handle to the receive desriptor object used for
+ *		nonoffload receive
+ */
+typedef void *vxge_hal_rxd_h;
+
+/*
+ * typedef vxge_hal_up_msg_h - Handle to the up message queue
+ */
+typedef void *vxge_hal_up_msg_h;
+
+/*
+ * typedef vxge_hal_down_msg_h - Handle to the down message queue
+ */
+typedef void *vxge_hal_down_msg_h;
+
+
+/*
+ * typedef vxge_hal_callback_h - Handle to callback function
+ */
+typedef void *vxge_hal_callback_h;
+
+/*
+ * enum vxge_hal_message_type_e - Enumerated message types.
+ *
+ * @VXGE_HAL_MSG_TYPE_NCE_CREATE_REQ: The NCE Create Request
+ *		 message is used by the host to create an NCE on the adapter.
+ * @VXGE_HAL_MSG_TYPE_NCE_CREATE_RESP:The NCE Create Response
+ *		 message is sent in response to the NCE Create Request
+ *		 message from the host to indicate the status of the operation
+ *		 and return the NCE ID.
+ * @VXGE_HAL_MSG_TYPE_NCE_DELETE_REQ:The NCE Delete Request
+ *		 messag is sent by the host to delete an NCE after it is no
+ *		 longer required.
+ * @VXGE_HAL_MSG_TYPE_NCE_DELETE_RESP:The NCE Delete Response
+ *		 message is sent in response to the NCE Delete Request
+ *		 message from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_REQ:The NCE Update MAC Request
+ *		  message is used by the host to modify the MAC address for
+ *		 an NCE on the adapter.
+ * @VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_RESP:The NCE Update MAC Response
+ *		  message is sent in response to the NCE Update MAC Request
+ *		  message from the host to indicate the status of the
+ *		 operation.
+ * @VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_REQ:The NCE Update Rch Time
+ *		 Request  message is used by the host to update the
+ *		 Reachability time for an NCE on the adapter.
+ * @VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_RESP:The NCE Update
+ *		 Rch Time Response  message is sent in response to the NCE
+ *		 Update Rch Time Request  message from the host to indicate
+ *		 the status of updating the reachability time for the NCE.
+ * @VXGE_HAL_MSG_TYPE_NCE_QUERY_REQ:The NCE Query Request  message
+ *		 is used by the host to query an NCE on the adapter.
+ * @VXGE_HAL_MSG_TYPE_NCE_QUERY_RESP:The NCE Query Response
+ *		 message is sent in response to the NCE Query Request  message
+ *		 from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_NCE_RCH_TIME_EXCEEDED:This is an unsolicited message
+ *		 sent to the host by the adapter when the NCE Reach Time has
+ *		 been exceeded.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_CREATE_REQ:The CQRQ Create Request
+ *		 message is used by the host to create a CQRQ on the adapter.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_CREATE_RESP:The CQRQ Create Response
+ *		 message is sent in response to the CQRQ Create Request
+ *		 message from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_DELETE_REQ:The CQRQ Delete Request
+ *		 message is used by the host to destroy a CQRQ on the adapter.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_DELETE_RESP:The CQRQ Delete Response
+ *		 message is sent in response to the CQRQ Delete Request
+ *		 message from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_REQ:The CQRQ Modify Request
+ *		 message is used by the host to modify fields for an
+ *		 CQRQ on the adapter. The adapter will make the following
+ *		 checks
+ *		 - The CQRQ ID is valid
+ *		 All other checks must be performed by the host software.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_RESP:The CQRQ Modify Response
+ *		 message is sent in response to the CQRQ Modify Request
+ *		 message from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_QUERY_REQ:The CQRQ Query Request
+ *		 message is used by the host to query the properties of a CQRQ
+ *		 on the adapter
+ * @VXGE_HAL_MSG_TYPE_CQRQ_QUERY_RESP:The CQRQ Query Response
+ *		 message is sent in response to the CQRQ Query Request
+ *		 message from the host to indicate the status of the operation
+ *		 and return any CQRQ properties to the host.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_ARM_REQ:The CQRQ Arm Request  message
+ *		 is used by the host to change the armed state of a CQRQ on the
+ *		 adapter. The armed state determines how the adapter will
+ *		 interrupt the host when RDMA messages arrive.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_ARM_RESP:The CQRQ Arm Response  message
+ *		 is sent in response to the CQRQ Arm Request  message from the
+ *		 host to indicate the status of arming the CQRQ
+ * @VXGE_HAL_MSG_TYPE_CQRQ_EVENT_NOTIF:The CQRQ Event Notification
+ *		  message is sent to host when the adapter encounters a
+ *		 problem when DMAing CQEs from host memory. There are three
+ *		 conditions, EOL, Low Threshold, Drained
+ * @VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_REQ:The CQRQ
+ *		 First CQE BW Notification Request  message is used by the
+ *		 host to notify the adapter after it has configured the first
+ *		 CQE block wrapper(s). It is required to pass the host address
+ *		 and number of bytes of the first CQE block wrapper in host
+ *		 memory.
+ * @VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_RESP:The CQRQ
+ *		 First CQE BW Notification Response  message is sent in
+ *		 response to the CQRQ First CQE BW Notification Request
+ *		 message from the host to acknowledge the notification from
+ *		 host and return the status of updating the CQRQ record with
+ *		 the address and bytes of the first CQE block wrapper.
+ * @VXGE_HAL_MSG_TYPE_SRQ_CREATE_REQ:The SRQ Create Request
+ *		 message is used by the host to create an SRQ on the adapter.
+ * @VXGE_HAL_MSG_TYPE_SRQ_CREATE_RESP:The SRQ Create Response
+ *		 message is sent in response to the SRQ Create Request
+ *		 message from the host to indicate the status of the operation
+ *		 and return the SRQ ID to the host.
+ * @VXGE_HAL_MSG_TYPE_SRQ_DELETE_REQ:The SRQ Delete Request
+ *		 message is used by the host to delete an SRQ on the adapter.
+ * @VXGE_HAL_MSG_TYPE_SRQ_DELETE_RESP:The SRQ Delete Response
+ *		 message is sent in response to the SRQ Delete Request
+ *		 message from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_SRQ_MODIFY_REQ:The SRQ Modify Request
+ *		 message is used by the host to modify an SRQ on the adapter.
+ *		 The host must send down all the fields to modify. To simplify
+ *		 the adapter firmware there will be no mask to modify individual
+ *		 fields.
+ * @VXGE_HAL_MSG_TYPE_SRQ_MODIFY_RESP:The SRQ Modify Response
+ *		 message is sent in response to the SRQ Modify Request
+ *		 message from the host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_SRQ_QUERY_REQ:The SRQ Query Request  message
+ *		 is used by the host to query the properties of an SRQ on the
+ *		 adapter.
+ * @VXGE_HAL_MSG_TYPE_SRQ_QUERY_RESP:The SRQ Query Response
+ *		 message is sent in response to the SRQ Query Request  message
+ *		 from the host to indicate the status of the operation and
+ *		 return any SRQ properties to the host
+ * @VXGE_HAL_MSG_TYPE_SRQ_ARM_REQ:The SRQ Arm Request  message is
+ *		 sent to the adapter to arm or re-arm the SRQ limit.
+ * @VXGE_HAL_MSG_TYPE_SRQ_ARM_RESP:The SRQ Arm Response  is sent
+ *		 to the host to acknowledge the SRQ Arm Request  and indicate
+ *		 the status of arming or re-arming the SRQ limit.
+ * @VXGE_HAL_MSG_TYPE_SRQ_EVENT_NOTIF:The SRQ Event Notification
+ *		 iMSG is used to alert the host that the adapter has encountered
+ *		 one of the following conditions when DMAing WQEs from host
+ *		 memory - EOL (End of list of WQEs in host memory),Low Threshold
+ *		 (The adapter is running low on available WQEs),Drained (Adapter
+ *		 out of WQEs because of EOL condition or adapter use faster than
+ *		 DMA), SRQ Limit (The number of available WQEs on adapter + host
+ *		 less than SRQ limit and the SRQ limit is armed).
+ * @VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_REQ:The SRQ First
+ *		 WQE BW Notification Request  is used to alert the adapter of
+ *		 the location of the first WQE block wrapper after initially
+ *		 creating the SRQ. It is required because the host cannot
+ *		 pre-post WQEs when creating the SRQ.
+ * @VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_RESP:The SRQ First
+ *		 WQE BW Notification Response  message is sent in response to
+ *		 the SRQ First WQE BW Notification Request  message from the
+ *		 host to indicate the status of the operation.
+ * @VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_REQ:The SRQ
+ *		 WQE Blocks Added Notification Request  is used to alert the
+ *		 adapter that new WQEs have been posted in host memory. This is
+ *		 required in order for the adapter to support the concept of SRQ
+ *		 limit.
+ * @VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_RESP:The SRQ
+ *		 WQE Blocks Added Notification Response  is sent by the adapter
+ *		 in response to the SRQ WQE Blocks Added Notification Request
+ *		 to acknowledge the notification from the host and to return any
+ *		 status in the event a problem occurred.
+ * @VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_REQ:The SRQ Return WQEs
+ *		 Request  message may be sent by the host to reclaim unused
+ *		 WQEs from the head of the WQE block wrapper list. Its purpose
+ *		 is to reclaim over-provisioned WQEs for an SRQ. The host may
+ *		 choose to reclaim WQEs from an SRQ at any time.
+ * @VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_RESP:The SRQ Return WQEs
+ *		  is sent in reply to the SRQ Return WQEs Request  message
+ *		 to reclaim unused WQEs from an over-provisioned SRQ.
+ * @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_REQ:This downward message
+ *		 commands the adapter to create a new non-shared memory region
+ *		 (NSMR) in the invalid state. This message is used to implement
+ *		 the Allocate Non-Shared Memory Region memory management verb.
+ * @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_RESP:This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG Allocate NSMR Request  message
+ * @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_REQ:This downward message
+ *		 commands the adapter to allocate a new memory window (MW).
+ *		 This message is used to implement the Allocate Memory Window
+ *		 memory management verb.
+ * @VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_RESP:This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG Allocate MW Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_REQ:This downward message
+ *		 commands the adapter to deallocate the specified STag, freeing
+ *		 up any on-adapter resources
+ * @VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_RESP:This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG De-allocate Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_REQ:This downward message
+ *		 commands the adapter to register a non-shared memory region.
+ *		 This message is used to implement Register NSMR memory
+ *		 management verb Fast registration cannot be performed with
+ *		 this . It can only be done via the PostSQ TOWI.
+ * @VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_RESP:This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG Register NSMR Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_REQ:This downward
+ *		 message commands the adapter to change the memory registration
+ *		 of an existing NSMR to create a new NSMR in the valid state.
+ *		 This message is used to implement the Reregister Non-Shared
+ *		 Memory Region memory management verb.
+ * @VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_RESP:This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG Re-register NSMR Request  message
+ * @VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_REQ:This downward message
+ *		 commands the adapter to create a shared memory region (SMR)
+ *		 based on an existing memory region, either shared(SMR) or
+ *		 non-shared(NSMR). This message is used to implement the
+ *		 Register Shared Memory Region verb.
+ * @VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_RESP:This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG Re-register NSMR Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_QUERY_REQ:This downward message commands
+ *		 the adapter to return the specifics of the specified STag.
+ *		 This message is used to implement the Query Memory Region
+ *		 memory management verb and the Query Memory Window memory
+ *		 management verb. Memory region and memory window querying
+ *		 could be handled entirely by the host software without any
+ *		 adapter involvement. The STAG Query Request  and STAG
+ *		 Query Response  messages allow the host to implement
+ *		 adapter-based STag querying.
+ * @VXGE_HAL_MSG_TYPE_STAG_QUERY_RESP:This upward message
+ *		 communicates to the host the specifics of the queried STag.
+ *		 The response message does not return the underlying the PBL.
+ * @VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_REQ:This message
+ *		 commands the adapter to transition an invalid STag to the
+ *		 valid state without changing any of its other attributes.
+ *		 The Validate-STag-/Validate-STag-Response- messages
+ *		 allow a Neterion-proprietary ability to revalidate an invalid
+ *		 STag without changing any of its attributes or its PBL. This
+ *		 is expected to be useful in situations where an STag is
+ *		 invalidated and then revalidated with the same attributes
+ *		 including PBL. Using this message, rather than the more
+ *		 general Reregister NSMR, saves the overhead of transferring
+ *		 the PBL to the adapter.
+ * @VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_RESP:This upward message
+ *		 communicates to the host the success of failure of the
+ *		 corresponding STAG Validate Local Tag Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_REQ: The STAG
+ *		 Invalidate Local Tag Request  message is used by the host to
+ *		 invalidate a local STAG. This message provides an alternative
+ *		 route for the normal TOWI based STAG Invalidation. It allows a
+ *		 kernel mode process to invalidate an STAG without writing
+ *		 a TOWI.
+ * @VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_RESP: This upward
+ *		 message communicates to the host the success or failure of the
+ *		 corresponding STAG Invalidate Local Tag Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_BIND_MW_REQ: This downward message commands
+ *		 the adapter to bind an existing (invalid) MW to an existing
+ *		 (valid) MR.  This message provides an alternative to the TOWI
+ *		 based implementation allowing the  path be used for MW binding
+ * @VXGE_HAL_MSG_TYPE_STAG_BIND_MW_RESP: This upward message
+ *		 communicates to the host the success or failure of the
+ *		 corresponding STAG Bind MW Request  message.
+ * @VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_REQ: The STAG Fast
+ *		 Register NSMR Request  provides an alternative way to fast
+ *		 register an NSMR instead of going to the TOWI path.
+ * @VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_RESP:  The STag Fast
+ *		 Register NSMR Response  message is sent to the host from
+ *		 the adapter in response to the original  message. It
+ *		 indicates the status of fast registering the NSMR.
+ * @VXGE_HAL_MSG_TYPE_TCP_OPEN_REQ:The TCP Open Request  message
+ *		 is sent by the host to open a TCP connection on the adapter.
+ * @VXGE_HAL_MSG_TYPE_TCP_OPEN_RESP:The TCP Open Response  message
+ *		 is sent in response to a TCP Open Request  message to indicate
+ *		 that the TCP session has been opened
+ * @VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_REQ:The TCP Promote to
+ *		 iWARP Request  message is sent from the host to the adapter
+ *		 in order to migrate an existing bytestream session to iWARP
+ *		 mode.
+ * @VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_RESP:The TCP Promote to
+ *		 iWARP Response  message is sent to the host to indicate the
+ *		 status of promoting an existing bytestream session to iWARP
+ *		 mode.
+ * @VXGE_HAL_MSG_TYPE_TCP_MODIFY_REQ:The TCP Modify Request  message
+ *		 is sent by the host to modify the attributes associated with a
+ *		 bytestream or iWARP session.
+ * @VXGE_HAL_MSG_TYPE_TCP_MODIFY_RESP:The TCP Modify Response  message
+ *		 is sent to the host in response to a TCP Modify Request message
+ *		 to indicate the status of changing the attributes associated
+ *		 with the bytestream or iWARP session.
+ * @VXGE_HAL_MSG_TYPE_TCP_DELETE_REQ:The TCP Delete Request
+ *		 message is sent by the host to delete a bytestream TCP session
+ *		 on the adapter.
+ * @VXGE_HAL_MSG_TYPE_TCP_DELETE_RESP:The TCP Delete Response
+ *		 message is sent in response to a TCP Delete Request  message
+ *		 to indicate that the TCP session has been deleted.
+ * @VXGE_HAL_MSG_TYPE_TCP_ABORT_REQ: The TCP Abort Request  message
+ *		 is used to abort a bytestream or iWARP session.
+ * @VXGE_HAL_MSG_TYPE_TCP_ABORT_RESP: The TCP Abort Response
+ *		 message is sent to the host from the adapter after aborting the
+ *		 bytestream or iWARP session.
+ * @VXGE_HAL_MSG_TYPE_TCP_ESTABLISHED: The TCP Established  message is
+ *		 an un-solicited event sent from the adapter to the host when
+ *		 the SYN+ACK segment arrives (active opener) or the ACK segment
+ *		(passive opener) arrives at the adapter.
+ * @VXGE_HAL_MSG_TYPE_TCP_FIN_RECEIVED: The TCP FIN Received  message
+ *		 is an un-solicited event sent from the adapter to the host on
+ *		 session teardown. It indicates that the FIN segment has been
+ *		 received from the remote end and the session is now in TIME
+ *		 WAIT state.
+ * @VXGE_HAL_MSG_TYPE_TCP_TIME_WAIT_DONE: The TCP Time Wait Done  message
+ *		 is sent from the adapter to the host to indicate when the TCP
+ *		 session leaves the TIME WAIT state.
+ * @VXGE_HAL_MSG_TYPE_TCP_UPDATE_RXWIN: This message is used for receive
+ *		 window updates, both for rx window flow control updates(updates
+ *		 to rcv_buf as data is consumed by the application on the host)
+ *		 and for maximum receive window size updates (when the receive
+ *		 buffer size changes on the host)
+ * @VXGE_HAL_MSG_TYPE_TCP_UPDATE_MSS: This  is sent by the host to the
+ *		 adapter to update the MSS for the session.
+ * @VXGE_HAL_MSG_TYPE_TCP_UPDATE_IP_HEADER: The TCP Update IP Header
+ *		 is used to update the IP TOS and IP flow label in the IP header
+ * @VXGE_HAL_MSG_TYPE_TCP_UPDATE_KEEPALIVE: The TCP Update Keepalive
+ *		 message is sent from the host to the adapter to update the
+ *		 keep-alive timer for the session.
+ * @VXGE_HAL_MSG_TYPE_TCP_UPDATE_FAILURE: The TCP Update Failure
+ *		 message is sent to the host from the adapter in the event that
+ *		 one of the TCP update messages failed for the session. Normally
+ *		 these messages do not require a reply and therefore there is no
+ *		 response from the adapter. The TCP Update messages include:
+ *		 VXGE_HAL_MSG_TYPE_TCP_UPDATE_RXWIN
+ *		 VXGE_HAL_MSG_TYPE_TCP_UPDATE_MSS
+ *		 VXGE_HAL_MSG_TYPE_TCP_UPDATE_IP_HEADER
+ *		 VXGE_HAL_MSG_TYPE_TCP_UPDATE_KEEPALIVE
+ * @VXGE_HAL_MSG_TYPE_TCP_FIN_ACK_RECEIVED:The TCP FIN ACK Received
+ *		 message is an unsolicited message sent to the host from the
+ *		 adapter on received of the ACK segment acknowledging that the
+ *		 remote end has received the FIN. It is required for Sun's KPI
+ *		 interface.
+ * @VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_REQ:The TCP Relink to NCE
+ *		 Request  would be used to change the NCE entry associated
+ *		 with a particular bytestream or iWARP session. This message
+ *		 could be used to change the NCE of a group of sessions if a
+ *		 particular path went down and need to be replaced by a new path
+ *		 The host is responsible for tracking the mapping of sessions to
+ *		 NCEs so that when de-allocating an NCE it does not de-allocate
+ *		 on that is still in use by a particular session.
+ * @VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_RESP:This message is sent in
+ *		 response to the TCP Relink to NCE Request  to indicate the
+ *		 status of re-linking the TCP session to a particular NCE.
+ * @VXGE_HAL_MSG_TYPE_TCP_QP_LIMIT_EXCEEDED:The TCP QP Limit Exceeded
+ *		 Notification  message is sent to the host when an iWARP
+ *		 session has reached its QP Limit and the QP limit was armed.
+ * @VXGE_HAL_MSG_TYPE_TCP_RDMA_TERMINATE_RECEIVED:The TCP RDMA Terminate
+ *		 Received  message is an un-solicited event sent from the
+ *		 adapter to the host when an RDMA terminate message has been
+ *		 received from the remote end.
+ * @VXGE_HAL_MSG_TYPE_LRO_OPEN_REQ:The LRO Open Request  message
+ *		 is sent by the host to open an LRO connection on the adapter.
+ *		 There is no PE context for an LRO session. The PE is involved
+ *		 for timer purposes and transferring messages to the RPE but it
+ *		 contains no session context.
+ * @VXGE_HAL_MSG_TYPE_LRO_OPEN_RESP:The LRO Open Response  message
+ *		 is sent in response to a LRO Open Request  message to
+ *		 indicate that the LRO session has been opened.
+ * @VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_REQ:The LRO End
+ *		 Classification Request  is sent by the host before the LRO
+ *		 Delete Request  to tell the adapter to stop steering Rx
+ *		 frames from that session into the LRO path. The host would
+ *		 later call LRO Delete Request . Separating these two calls
+ *		 allows enough time to pass so that frames already in the FB can
+ *		 be drained out, thereby avoiding the need for frame reversion.
+ * @VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_RESP:The LRO End
+ *		 Classification Response  message is sent in response to a
+ *		 LRO End Classification Request  message to indicate that
+ *		 classification has been stopped for the LRO session and the
+ *		 host can proceed with deleting the LRO session.
+ * @VXGE_HAL_MSG_TYPE_LRO_DELETE_REQ:The LRO Delete Request
+ *		 message is sent by the host to delete a LRO session on the
+ *		 adapter.It might be possible in the future to replace this
+ *		 message and the TCP Delete Request  with a single common
+ *		 message since there doesn't seem to be any difference between
+ *		 the two anymore.
+ * @VXGE_HAL_MSG_TYPE_LRO_DELETE_RESP:The LRO Delete Response
+ *		 message is sent in response to a LRO Delete Request  message
+ *		 to indicate that the LRO session has been deleted.
+ * @VXGE_HAL_MSG_TYPE_LRO_SESSION_CANDIDATE_NOTIF:This msg
+ *		 indicates to the host that the adapter's autoLRO feature has
+ *		 identified a candidate LRO session. No response from the host
+ *		 is required. (If the host did decide to act on this information
+ *		 from the adapter, the host would use the usual LRO Open Request
+ *		).
+ * @VXGE_HAL_MSG_TYPE_SPDM_OPEN_REQ:The SPDM Open Request  message
+ *		 is sent by the host to open an SPDM connection on the adapter.
+ *		 There is no RPE or PE context for an SPDM session. The ONE is
+ *		 not involved in this type of classification.
+ * @VXGE_HAL_MSG_TYPE_SPDM_OPEN_RESP:The SPDM Open Response
+ *		 message is sent in response to a SPDM Open Request  message
+ *		 to indicate the status of creating the SPDM session.
+ * @VXGE_HAL_MSG_TYPE_SPDM_DELETE_REQ:The SPDM Delete Request
+ *		 message is sent by the host to delete an SPDM session on the
+ *		 adapter. It might be possible in the future to replace this
+ *		 message and the LRO/TCP Delete Request  with a single common
+ *		 message since there doesn't seem to be any difference between
+ *		 the two anymore.
+ * @VXGE_HAL_MSG_TYPE_SPDM_DELETE_RESP:The SPDM Delete Response
+ *		 message is sent in response to a SPDM Delete Request  message
+ *		 to indicate that the SPDM session has been deleted.
+ * @VXGE_HAL_MSG_TYPE_SESSION_EVENT_NOTIF:The Session Event
+ *		 Notification  message is an unsolicited message from the
+ *		 adapter used to inform the host about an unexpected condition
+ *		 on a bytestream or iWARP session.
+ * @VXGE_HAL_MSG_TYPE_SESSION_QUERY_REQ:The Session Query Request
+ *		 message is sent by the host to query the attributes of an
+ *		 existing offloaded session. This message may be used to query
+ *		 the attributes of an SPDM, LRO, bytestream or iWARP session.
+ *		 Initially this will be a single message used for all purposes.
+ *		 In the future this may be split up into multiple messages
+ *		 allowing the user to query the pecific context for an SPDM,
+ *		 LRO, iWARP, or bytestream session.
+ * @VXGE_HAL_MSG_TYPE_SESSION_QUERY_RESP:The Session Query Response
+ *		  message is sent in response to a Session Query Request
+ *		 message to return the attributes associated with the specified
+ *		 session
+ * @VXGE_HAL_MSG_TYPE_SESSION_RETURN_IN_PROG_WQES: This message is
+ *		 generated by the adapter during deletion of a session to return
+ *		 any WQEs that may be in the in-progress list for the session.If
+ *		 a WQE is in the in-progress list it is owned by the session and
+ *		 cannot be returned to the head of WQE list for an SRQ because
+ *		 of ordering issues. Therefore, it must be returned to the host
+ *		 at which point the host may choose to destroy the resource or
+ *		 simply re-post the WQE for re-use.
+ * @VXGE_HAL_MSG_TYPE_SESSION_FRAME_WRITE:The Frame Write  message is
+ *		 generated by the adapter in order to send certain frames to the
+ *		 host via the  path instead of the normal path. Frames will be
+ *		 sent to the host under the following conditions:
+ *		 1) mis-aligned frames that the adapter cannot place
+ *		 2) during debugging to look at the contents of the frame
+ *		 In addition to this,a RDMA terminate message will also be sent
+ *		 via a  message but in this case it will be sent in a TCP RDMA
+ *		 Terminate Received  message. Frames arriving in the  will
+ *		 not have markers stripped. Instead the host will be responsible
+ *		 for stripping markers and taking appropriate action on the
+ *		 received frame.
+ * @VXGE_HAL_MSG_TYPE_SQ_CREATE_REQ: This is HAL private message for.
+ *		 SQ create. Never used.
+ * @VXGE_HAL_MSG_TYPE_SQ_CREATE_RESP: This is HAL private message
+ *		 for SQ create response. This is reported to clients by HAL.
+ * @VXGE_HAL_MSG_TYPE_SQ_DELETE_REQ: This is HAL private message for.
+ *		 SQ delete. Never used.
+ * @VXGE_HAL_MSG_TYPE_SQ_DELETE_RESP:This is HAL private message
+ *		 for SQ delete response. This is reported to clients by HAL.
+ *
+ * Message types supported by the adapter and HAL Private messages.
+ */
+typedef enum vxge_hal_message_type_e {
+	VXGE_HAL_MSG_TYPE_NCE_CREATE_REQ			= 1,
+	VXGE_HAL_MSG_TYPE_NCE_CREATE_RESP			= 2,
+	VXGE_HAL_MSG_TYPE_NCE_DELETE_REQ			= 3,
+	VXGE_HAL_MSG_TYPE_NCE_DELETE_RESP			= 4,
+	VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_REQ			= 5,
+	VXGE_HAL_MSG_TYPE_NCE_UPDATE_MAC_RESP			= 6,
+	VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_REQ		= 7,
+	VXGE_HAL_MSG_TYPE_NCE_UPDATE_RCH_TIME_RESP		= 8,
+	VXGE_HAL_MSG_TYPE_NCE_QUERY_REQ				= 9,
+	VXGE_HAL_MSG_TYPE_NCE_QUERY_RESP			= 10,
+	VXGE_HAL_MSG_TYPE_NCE_RCH_TIME_EXCEEDED			= 86,
+	VXGE_HAL_MSG_TYPE_CQRQ_CREATE_REQ			= 11,
+	VXGE_HAL_MSG_TYPE_CQRQ_CREATE_RESP			= 12,
+	VXGE_HAL_MSG_TYPE_CQRQ_DELETE_REQ			= 13,
+	VXGE_HAL_MSG_TYPE_CQRQ_DELETE_RESP			= 14,
+	VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_REQ			= 16,
+	VXGE_HAL_MSG_TYPE_CQRQ_MODIFY_RESP			= 17,
+	VXGE_HAL_MSG_TYPE_CQRQ_QUERY_REQ			= 18,
+	VXGE_HAL_MSG_TYPE_CQRQ_QUERY_RESP			= 19,
+	VXGE_HAL_MSG_TYPE_CQRQ_ARM_REQ				= 20,
+	VXGE_HAL_MSG_TYPE_CQRQ_ARM_RESP				= 21,
+	VXGE_HAL_MSG_TYPE_CQRQ_EVENT_NOTIF			= 22,
+	VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_REQ		= 23,
+	VXGE_HAL_MSG_TYPE_CQRQ_FIRST_CQE_BW_NOTIF_RESP		= 24,
+	VXGE_HAL_MSG_TYPE_SRQ_CREATE_REQ			= 27,
+	VXGE_HAL_MSG_TYPE_SRQ_CREATE_RESP			= 28,
+	VXGE_HAL_MSG_TYPE_SRQ_DELETE_REQ			= 29,
+	VXGE_HAL_MSG_TYPE_SRQ_DELETE_RESP			= 30,
+	VXGE_HAL_MSG_TYPE_SRQ_MODIFY_REQ			= 31,
+	VXGE_HAL_MSG_TYPE_SRQ_MODIFY_RESP			= 32,
+	VXGE_HAL_MSG_TYPE_SRQ_QUERY_REQ				= 33,
+	VXGE_HAL_MSG_TYPE_SRQ_QUERY_RESP			= 34,
+	VXGE_HAL_MSG_TYPE_SRQ_ARM_REQ				= 35,
+	VXGE_HAL_MSG_TYPE_SRQ_ARM_RESP				= 36,
+	VXGE_HAL_MSG_TYPE_SRQ_EVENT_NOTIF			= 37,
+	VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_REQ		= 38,
+	VXGE_HAL_MSG_TYPE_SRQ_FIRST_WQE_BW_NOTIF_RESP		= 39,
+	VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_REQ	= 40,
+	VXGE_HAL_MSG_TYPE_SRQ_WQE_BLOCKS_ADDED_NOTIF_RESP	= 41,
+	VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_REQ		= 96,
+	VXGE_HAL_MSG_TYPE_SRQ_RETURN_UNUSED_WQES_RESP		= 42,
+	VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_REQ		= 43,
+	VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_NSMR_RESP		= 44,
+	VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_REQ			= 45,
+	VXGE_HAL_MSG_TYPE_STAG_ALLOCATE_MW_RESP			= 46,
+	VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_REQ			= 47,
+	VXGE_HAL_MSG_TYPE_STAG_DE_ALLOCATE_RESP			= 48,
+	VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_REQ		= 49,
+	VXGE_HAL_MSG_TYPE_STAG_REGISTER_NSMR_RESP		= 50,
+	VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_REQ		= 51,
+	VXGE_HAL_MSG_TYPE_STAG_RE_REGISTER_NSMR_RESP		= 52,
+	VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_REQ			= 53,
+	VXGE_HAL_MSG_TYPE_STAG_REGISTER_SMR_RESP		= 54,
+	VXGE_HAL_MSG_TYPE_STAG_QUERY_REQ			= 55,
+	VXGE_HAL_MSG_TYPE_STAG_QUERY_RESP			= 56,
+	VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_REQ		= 57,
+	VXGE_HAL_MSG_TYPE_STAG_VALID_LOCAL_TAG_RESP		= 58,
+	VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_REQ		= 87,
+	VXGE_HAL_MSG_TYPE_STAG_INVALID_LOCAL_TAG_RESP		= 88,
+	VXGE_HAL_MSG_TYPE_STAG_BIND_MW_REQ			= 89,
+	VXGE_HAL_MSG_TYPE_STAG_BIND_MW_RESP			= 90,
+	VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_REQ		= 91,
+	VXGE_HAL_MSG_TYPE_STAG_FAST_REGISTER_NSMR_RESP		= 92,
+	VXGE_HAL_MSG_TYPE_TCP_OPEN_REQ				= 59,
+	VXGE_HAL_MSG_TYPE_TCP_OPEN_RESP				= 60,
+	VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_REQ		= 61,
+	VXGE_HAL_MSG_TYPE_TCP_PROMOTE_TO_IWARP_RESP		= 62,
+	VXGE_HAL_MSG_TYPE_TCP_MODIFY_REQ			= 98,
+	VXGE_HAL_MSG_TYPE_TCP_MODIFY_RESP			= 99,
+	VXGE_HAL_MSG_TYPE_TCP_DELETE_REQ			= 63,
+	VXGE_HAL_MSG_TYPE_TCP_DELETE_RESP			= 64,
+	VXGE_HAL_MSG_TYPE_TCP_ABORT_REQ				= 65,
+	VXGE_HAL_MSG_TYPE_TCP_ABORT_RESP			= 66,
+	VXGE_HAL_MSG_TYPE_TCP_ESTABLISHED			= 78,
+	VXGE_HAL_MSG_TYPE_TCP_FIN_RECEIVED			= 79,
+	VXGE_HAL_MSG_TYPE_TCP_TIME_WAIT_DONE			= 80,
+	VXGE_HAL_MSG_TYPE_TCP_UPDATE_RXWIN			= 81,
+	VXGE_HAL_MSG_TYPE_TCP_UPDATE_MSS			= 82,
+	VXGE_HAL_MSG_TYPE_TCP_UPDATE_IP_HEADER			= 83,
+	VXGE_HAL_MSG_TYPE_TCP_UPDATE_KEEPALIVE			= 84,
+	VXGE_HAL_MSG_TYPE_TCP_UPDATE_FAILURE			= 85,
+	VXGE_HAL_MSG_TYPE_TCP_FIN_ACK_RECEIVED			= 87,
+	VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_REQ			= 88,
+	VXGE_HAL_MSG_TYPE_TCP_RELINK_TO_NCE_RESP		= 89,
+	VXGE_HAL_MSG_TYPE_TCP_QP_LIMIT_EXCEEDED			= 100,
+	VXGE_HAL_MSG_TYPE_TCP_RDMA_TERMINATE_RECEIVED		= 101,
+	VXGE_HAL_MSG_TYPE_LRO_OPEN_REQ				= 67,
+	VXGE_HAL_MSG_TYPE_LRO_OPEN_RESP				= 68,
+	VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_REQ			= 69,
+	VXGE_HAL_MSG_TYPE_LRO_END_CLASSIF_RESP			= 70,
+	VXGE_HAL_MSG_TYPE_LRO_DELETE_REQ			= 71,
+	VXGE_HAL_MSG_TYPE_LRO_DELETE_RESP			= 72,
+	VXGE_HAL_MSG_TYPE_LRO_SESSION_CANDIDATE_NOTIF		= 73,
+	VXGE_HAL_MSG_TYPE_SPDM_OPEN_REQ				= 74,
+	VXGE_HAL_MSG_TYPE_SPDM_OPEN_RESP			= 75,
+	VXGE_HAL_MSG_TYPE_SPDM_DELETE_REQ			= 76,
+	VXGE_HAL_MSG_TYPE_SPDM_DELETE_RESP			= 77,
+	VXGE_HAL_MSG_TYPE_SESSION_EVENT_NOTIF			= 102,
+	VXGE_HAL_MSG_TYPE_SESSION_QUERY_REQ			= 103,
+	VXGE_HAL_MSG_TYPE_SESSION_QUERY_RESP			= 104,
+	VXGE_HAL_MSG_TYPE_SESSION_RETURN_IN_PROG_WQES		= 97,
+	VXGE_HAL_MSG_TYPE_SESSION_FRAME_WRITE			= 105,
+	/* The following are private for HAL */
+	VXGE_HAL_MSG_TYPE_SQ_CREATE_REQ				= 65537,
+	VXGE_HAL_MSG_TYPE_SQ_CREATE_RESP			= 65538,
+	VXGE_HAL_MSG_TYPE_SQ_DELETE_REQ				= 65539,
+	VXGE_HAL_MSG_TYPE_SQ_DELETE_RESP			= 65540
+} vxge_hal_message_type_e;
+
+
+/*
+ * struct vxge_hal_opaque_handle_t - Opaque handle used by the hal and clients
+ *				  to save their contexts
+ * @vpath_handle: Virtual path handle
+ * @hal_priv: Private data which HAL assigns
+ * @client_priv: Client assigned private data
+ *
+ * This structure is used to store the client and hal data and pass as
+ * opaque handle in the messages.
+ */
+typedef struct vxge_hal_opaque_handle_t {
+	vxge_hal_vpath_h		vpath_handle;
+#define	VXGE_HAL_OPAQUE_HANDLE_GET_VPATH_HANDLE(op) ((op)->vpath_handle)
+#define	VXGE_HAL_OPAQUE_HANDLE_VPATH_HANDLE(op, vrh) (op)->vpath_handle = vrh
+
+	u64				hal_priv;
+#define	VXGE_HAL_OPAQUE_HANDLE_GET_HAL_PRIV(op)	    ((op)->hal_priv)
+#define	VXGE_HAL_OPAQUE_HANDLE_HAL_PRIV(op, priv)   (op)->hal_priv = (u64)priv
+
+	u64				client_priv;
+#define	VXGE_HAL_OPAQUE_HANDLE_GET_CLIENT_PRIV(op)  ((op)->client_priv)
+#define	VXGE_HAL_OPAQUE_HANDLE_CLIENT_PRIV(op, priv)	\
+					    (op)->client_priv = (u64)priv
+
+} vxge_hal_opaque_handle_t;
+
+/*
+ * vxge_hal_vpath_callback_f - Callback to receive up messages.
+ * @client_handle: handle passed by client in attach or open function
+ * @msgh: Message handle.
+ * @msg_type: Type of message
+ * @obj_id: Object Id of object to which message belongs
+ * @result: Result code
+ * @opaque_handle: Opaque handle passed when the request was made.
+ *
+ * Callback function registered when opening vpath to receive the messages
+ * This callback function passed to vxge_hal_vpath_open and
+ * vxge_hal_vpath_attach routine to get replys to all asynchronous functions.
+ * The format of the reply is a message along with the parameters that are
+ * common fro all replys. The message handle passed to this callback is
+ * opaque for the iWARP/RDMA module and the information from the message can
+ * be got by calling appropriate get function depending on the message type
+ * passed as one of the parameter to the callback. The message types that
+ * are to be passed to the callback are the ones that are responses and
+ * notifications
+ */
+typedef vxge_hal_status_e(*vxge_hal_vpath_callback_f) (
+    vxge_hal_client_h client_handle,
+    vxge_hal_up_msg_h msgh,
+    vxge_hal_message_type_e msg_type,
+    vxge_hal_obj_id_t obj_id,
+    vxge_hal_status_e result,
+    vxge_hal_opaque_handle_t *opaque_handle);
+
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_TYPES_H */
diff --git a/sys/dev/vxge/include/vxgehal-version.h b/sys/dev/vxge/include/vxgehal-version.h
new file mode 100644
index 000000000000..e58f0a1fc6fb
--- /dev/null
+++ b/sys/dev/vxge/include/vxgehal-version.h
@@ -0,0 +1,73 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_VERSION_H
+#define	VXGE_HAL_VERSION_H
+
+#include <dev/vxge/include/build-version.h>
+
+
+/*
+ * VXGE_HAL_VERSION_MAJOR - HAL major version
+ */
+#define	VXGE_HAL_VERSION_MAJOR		0
+
+/*
+ * VXGE_HAL_VERSION_MINOR - HAL minor version
+ */
+#define	VXGE_HAL_VERSION_MINOR		0
+
+/*
+ * VXGE_HAL_VERSION_FIX - HAL version fix
+ */
+#define	VXGE_HAL_VERSION_FIX		0
+
+/*
+ * VXGE_HAL_VERSION_BUILD - HAL build version
+ */
+#define	VXGE_HAL_VERSION_BUILD	GENERATED_BUILD_VERSION
+
+/*
+ * VXGE_HAL_VERSION - HAL version
+ */
+#define	VXGE_HAL_VERSION "VXGE_HAL_VERSION_MAJOR.VXGE_HAL_VERSION_MINOR.\
+			VXGE_HAL_VERSION_FIX.VXGE_HAL_VERSION_BUILD"
+
+/*
+ * VXGE_HAL_DESC - HAL Description
+ */
+#define	VXGE_HAL_DESC	VXGE_DRIVER_NAME" v."VXGE_HAL_VERSION
+
+/* Link Layer versioning */
+#include <dev/vxge/vxgell-version.h>
+
+#endif	/* VXGE_HAL_VERSION_H */
diff --git a/sys/dev/vxge/vxge-firmware.h b/sys/dev/vxge/vxge-firmware.h
new file mode 100644
index 000000000000..61eb440ac744
--- /dev/null
+++ b/sys/dev/vxge/vxge-firmware.h
@@ -0,0 +1,29955 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+unsigned char X3fw_ncf[] = {
+	0x50, 0x4b, 0x03, 0x04, 0x14, 0x00, 0x01, 0x00, 0x08, 0x00, 0xf7, 0x89,
+	0x59, 0x3d, 0xec, 0x91, 0x1c, 0xcd, 0x21, 0x00, 0x00, 0x00, 0x13, 0x00,
+	0x00, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x54, 0x31, 0x3a, 0x58, 0x33, 0x5f,
+	0x31, 0x30, 0x31, 0x30, 0x32, 0x35, 0x5f, 0x31, 0x5f, 0x38, 0x5f, 0x31,
+	0x5f, 0x65, 0x78, 0x70, 0x52, 0x4f, 0x4d, 0x5f, 0x46, 0x57, 0x5f, 0x75,
+	0x6e, 0x69, 0x5f, 0x74, 0x65, 0x6d, 0x70, 0x6c, 0x61, 0x74, 0x65, 0x5f,
+	0x72, 0x6d, 0x74, 0x5f, 0x63, 0x6d, 0x64, 0x5f, 0x6c, 0x69, 0x6e, 0x65,
+	0x2e, 0x74, 0x78, 0x74, 0xd0, 0x59, 0x04, 0x94, 0xaa, 0xb0, 0x1f, 0xc6,
+	0x67, 0x8a, 0xbe, 0xbf, 0xb8, 0x54, 0xec, 0x06, 0xf7, 0x74, 0xf9, 0xfe,
+	0x46, 0xb5, 0xb0, 0x57, 0x62, 0x7f, 0xed, 0x60, 0x60, 0x67, 0x80, 0xdf,
+	0x8c, 0x50, 0x4b, 0x03, 0x04, 0x14, 0x00, 0x01, 0x00, 0x08, 0x00, 0xf7,
+	0x89, 0x59, 0x3d, 0xa2, 0xcb, 0x96, 0x76, 0x4c, 0xba, 0x02, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x34, 0x00, 0x00, 0x00, 0x54, 0x31, 0x3a, 0x58, 0x33,
+	0x5f, 0x31, 0x30, 0x31, 0x30, 0x32, 0x35, 0x5f, 0x31, 0x5f, 0x38, 0x5f,
+	0x31, 0x5f, 0x65, 0x78, 0x70, 0x52, 0x4f, 0x4d, 0x5f, 0x46, 0x57, 0x5f,
+	0x75, 0x6e, 0x69, 0x5f, 0x74, 0x65, 0x6d, 0x70, 0x6c, 0x61, 0x74, 0x65,
+	0x5f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x30, 0x2e, 0x62, 0x69, 0x6e, 0x5d,
+	0x6b, 0xe1, 0x46, 0xd9, 0x2f, 0xc2, 0xbd, 0x6e, 0xd8, 0xd6, 0x9b, 0xa3,
+	0xcf, 0xbb, 0x2f, 0x62, 0x9b, 0x9d, 0xac, 0xc6, 0xb6, 0x2b, 0x47, 0x60,
+	0x88, 0x1a, 0xef, 0xfe, 0x50, 0xe2, 0x4e, 0x8b, 0x2d, 0x4d, 0x72, 0xcc,
+	0x1c, 0xe8, 0x02, 0xf7, 0x1f, 0x9b, 0xa7, 0x77, 0xbe, 0x34, 0xaa, 0xb2,
+	0xc7, 0x22, 0xf1, 0x87, 0xf0, 0x73, 0xae, 0x29, 0x1f, 0x8f, 0x3c, 0x71,
+	0x4d, 0x72, 0x7b, 0x71, 0xd9, 0x32, 0x3f, 0x0b, 0x40, 0x6f, 0x1e, 0x8c,
+	0xca, 0x49, 0x5e, 0x83, 0xf9, 0x92, 0x63, 0x92, 0x74, 0x0c, 0xe7, 0xc1,
+	0xa6, 0x78, 0x71, 0xd2, 0x08, 0x0c, 0x46, 0xbd, 0x74, 0x5a, 0xf5, 0x4f,
+	0xc1, 0x51, 0x37, 0xee, 0xcf, 0x9d, 0x47, 0x66, 0xdd, 0xb5, 0xd9, 0xf2,
+	0x4a, 0xe8, 0xab, 0xdf, 0x48, 0x91, 0x09, 0x8d, 0x32, 0xc8, 0xf1, 0x1d,
+	0x20, 0xe3, 0x81, 0x8b, 0xd1, 0x27, 0x3c, 0x01, 0x06, 0xed, 0xd0, 0x98,
+	0x1b, 0xbf, 0xc2, 0xa5, 0x83, 0xad, 0xce, 0x0c, 0x82, 0x5a, 0x0f, 0x54,
+	0x8a, 0xb7, 0xfb, 0xfd, 0xf0, 0x05, 0xaf, 0x92, 0x4b, 0xbd, 0xdc, 0x04,
+	0xc6, 0xb5, 0xb3, 0xda, 0xd4, 0x3e, 0xb1, 0x30, 0x08, 0xa9, 0x9c, 0x49,
+	0x7a, 0xd2, 0xba, 0x59, 0xff, 0xb2, 0x61, 0xcc, 0xb1, 0x77, 0x69, 0x4b,
+	0x28, 0x58, 0xcf, 0x76, 0x46, 0x96, 0x17, 0x73, 0x57, 0x70, 0xb3, 0x5e,
+	0x49, 0xeb, 0xed, 0xf0, 0x9a, 0x56, 0x65, 0x1c, 0x28, 0x71, 0xe9, 0xd9,
+	0x9a, 0x69, 0x27, 0x87, 0xd4, 0xde, 0xe3, 0x54, 0x49, 0x2d, 0xb9, 0xd3,
+	0x9d, 0x20, 0xa8, 0x30, 0xa0, 0x4d, 0x7d, 0xdd, 0xbb, 0x33, 0x4d, 0x8e,
+	0x7a, 0x32, 0xc1, 0xe7, 0xaa, 0x7e, 0x13, 0x5e, 0x04, 0x1f, 0x26, 0xdf,
+	0x40, 0x22, 0x27, 0x99, 0x57, 0x0f, 0xbc, 0xaf, 0x6b, 0x30, 0xf6, 0x41,
+	0x47, 0xd6, 0xb5, 0xf2, 0xf0, 0xc8, 0x7c, 0x2b, 0x65, 0x9a, 0xb8, 0xd2,
+	0x06, 0x5c, 0x47, 0xac, 0xd5, 0xed, 0x05, 0xe6, 0xbc, 0x60, 0x6e, 0x45,
+	0x5c, 0x07, 0xa8, 0xae, 0xca, 0x1a, 0x8a, 0xfb, 0xf1, 0x2a, 0xe5, 0x74,
+	0x02, 0xb8, 0x48, 0xac, 0xb2, 0x54, 0xaa, 0xeb, 0xfc, 0xde, 0xe0, 0xa9,
+	0x20, 0xd1, 0xac, 0x83, 0x69, 0xd4, 0xe0, 0xf7, 0x75, 0xfe, 0x8f, 0xd4,
+	0xa6, 0xfa, 0xa6, 0x39, 0xe1, 0xd1, 0xf5, 0xa5, 0x3a, 0x06, 0x2d, 0xa8,
+	0x74, 0x98, 0x13, 0x53, 0xfd, 0xd3, 0x45, 0x02, 0xed, 0xa4, 0x7b, 0xa5,
+	0x36, 0xbd, 0x69, 0x5b, 0x33, 0x0d, 0x59, 0xa6, 0x3c, 0xd4, 0x8b, 0xa2,
+	0xaa, 0x2c, 0x6c, 0xd0, 0x00, 0x98, 0x67, 0xc1, 0xde, 0x6c, 0x8d, 0xf1,
+	0xcb, 0xdd, 0x78, 0x06, 0xc3, 0x21, 0xe0, 0x4d, 0xd2, 0x0b, 0x6f, 0x94,
+	0x0f, 0xa9, 0x06, 0x4c, 0xd7, 0xe8, 0x54, 0xf7, 0x39, 0xc6, 0x72, 0xa3,
+	0x8b, 0xef, 0x18, 0xeb, 0xc7, 0xd2, 0x16, 0x7e, 0x47, 0xd3, 0x03, 0xf1,
+	0x3f, 0xe5, 0xf0, 0x9e, 0x6c, 0xe0, 0x94, 0x1c, 0xa0, 0xae, 0xdb, 0x5d,
+	0x7a, 0x4d, 0x3c, 0xc1, 0x08, 0x4c, 0x77, 0xa0, 0x63, 0x3c, 0x31, 0x30,
+	0xe9, 0x15, 0x92, 0xd4, 0x3e, 0x5d, 0xe7, 0x76, 0xee, 0xb7, 0xc4, 0x9f,
+	0xb6, 0x8d, 0x3a, 0xd2, 0x4f, 0xcf, 0xb0, 0x2e, 0xbc, 0x9f, 0x27, 0x38,
+	0xeb, 0x24, 0x35, 0xcb, 0xf9, 0x2c, 0xe1, 0xcb, 0xc9, 0x35, 0xdb, 0xb6,
+	0x7c, 0x9e, 0x8f, 0x6c, 0x6e, 0x8c, 0x64, 0x2c, 0x62, 0x0f, 0xe2, 0x35,
+	0xc6, 0xb1, 0x80, 0xf0, 0x62, 0x7c, 0xea, 0x9d, 0x71, 0x50, 0xe1, 0x41,
+	0x90, 0x19, 0x9c, 0x1c, 0xf6, 0x36, 0xda, 0x94, 0x21, 0x7c, 0x36, 0x8d,
+	0xf5, 0x73, 0xbe, 0xd4, 0x9f, 0x69, 0x20, 0x9e, 0xe2, 0x50, 0x3e, 0x2a,
+	0xb1, 0x3c, 0xb2, 0x66, 0xc4, 0x74, 0x1d, 0xc4, 0x1d, 0xc9, 0xcb, 0xa8,
+	0x4d, 0x22, 0x2e, 0x23, 0x0e, 0xa4, 0x77, 0xb1, 0x54, 0xc5, 0x92, 0x70,
+	0x57, 0xa8, 0x91, 0x1f, 0x49, 0x5c, 0xe3, 0xbe, 0x35, 0x52, 0xf0, 0x07,
+	0xfb, 0x05, 0x11, 0x12, 0x2b, 0xd9, 0xed, 0x18, 0x29, 0x58, 0xc7, 0x00,
+	0x61, 0x4d, 0x92, 0xb8, 0x6e, 0x73, 0x08, 0x5c, 0x4d, 0x34, 0x71, 0xd6,
+	0xdb, 0xcd, 0x17, 0xf1, 0xb4, 0x1c, 0x22, 0x73, 0x0f, 0x2b, 0x8c, 0x52,
+	0xfc, 0x43, 0xe7, 0x64, 0x24, 0xea, 0x1c, 0xb0, 0x93, 0xde, 0xe3, 0x09,
+	0xd6, 0xe6, 0xfb, 0x9c, 0xab, 0x7e, 0xd0, 0xa1, 0xb4, 0xe5, 0x8d, 0x9b,
+	0x60, 0x9d, 0x7f, 0x5d, 0x99, 0xe0, 0xa5, 0x36, 0x5e, 0xb9, 0xe9, 0xe4,
+	0xf6, 0x17, 0x05, 0x1f, 0x8d, 0xf2, 0x05, 0xa3, 0xc3, 0xe1, 0xa2, 0x3c,
+	0xf4, 0xe8, 0x29, 0x90, 0x26, 0xb7, 0xc2, 0x83, 0xab, 0x03, 0x1c, 0x31,
+	0x05, 0xb0, 0x45, 0x3e, 0x8e, 0xf9, 0x22, 0x96, 0xab, 0xf2, 0x39, 0x2a,
+	0x4e, 0x5c, 0x98, 0x59, 0x07, 0x19, 0x09, 0x57, 0xcf, 0x2a, 0x74, 0x12,
+	0xe9, 0xdc, 0x4b, 0x13, 0xe3, 0x44, 0x5a, 0x52, 0x38, 0x31, 0x93, 0x84,
+	0x43, 0x8b, 0x6e, 0xaa, 0x49, 0x16, 0xbd, 0x5c, 0xc1, 0xb1, 0x39, 0xc5,
+	0xd3, 0x6c, 0xcf, 0x9b, 0xfd, 0x54, 0xe1, 0xc3, 0x57, 0x2e, 0x04, 0xed,
+	0x8f, 0x1a, 0x65, 0x93, 0xcd, 0x33, 0x18, 0xb8, 0x09, 0x9b, 0x97, 0xe2,
+	0xce, 0xd9, 0xa5, 0x47, 0x01, 0x37, 0x98, 0xf6, 0xa7, 0xb7, 0x76, 0x3d,
+	0x82, 0xbf, 0xda, 0xfe, 0x74, 0xeb, 0xb2, 0x4f, 0xa7, 0x3a, 0x57, 0x3c,
+	0x16, 0x61, 0x88, 0x85, 0xca, 0xcb, 0x6f, 0x15, 0xd7, 0x46, 0x4a, 0x09,
+	0xff, 0x59, 0x38, 0x2a, 0xcb, 0x4d, 0x03, 0x08, 0x4b, 0x6b, 0xe3, 0x0c,
+	0xbb, 0x28, 0x51, 0x75, 0xb6, 0x17, 0x54, 0x61, 0xe5, 0xe1, 0x60, 0xf5,
+	0xd8, 0x5f, 0x88, 0xe1, 0x54, 0xce, 0xff, 0x03, 0x2d, 0xc2, 0x01, 0xc7,
+	0xb2, 0x32, 0xdb, 0x69, 0x5f, 0x84, 0x45, 0xbe, 0x4c, 0x7f, 0xdb, 0x88,
+	0x81, 0xc2, 0x30, 0x44, 0xe1, 0xab, 0x9d, 0x9a, 0xd8, 0xa1, 0xbf, 0xfd,
+	0x43, 0x6f, 0xd4, 0x1e, 0x0b, 0x74, 0xdf, 0xce, 0x68, 0x77, 0xfb, 0x4b,
+	0xb6, 0x55, 0x7f, 0xb1, 0xb4, 0x98, 0xc2, 0x9d, 0x73, 0x99, 0x05, 0x98,
+	0xff, 0x69, 0xce, 0x86, 0x02, 0xa4, 0x8f, 0x86, 0xdc, 0xe6, 0xac, 0x08,
+	0xc8, 0x2b, 0x1b, 0x2f, 0x7d, 0x47, 0xee, 0xfe, 0x27, 0xed, 0xc3, 0x5d,
+	0x90, 0x67, 0xf3, 0xe8, 0xbb, 0xc5, 0x88, 0xf1, 0xb0, 0xf8, 0xa1, 0x20,
+	0x7c, 0x22, 0x29, 0x3f, 0x8b, 0xa8, 0xc4, 0x3d, 0x8e, 0xb9, 0xaf, 0x95,
+	0xb6, 0xbd, 0x63, 0xe4, 0x11, 0x71, 0x5d, 0x0c, 0x6c, 0x83, 0x06, 0x9a,
+	0xba, 0x64, 0x17, 0xe2, 0xef, 0x71, 0xd7, 0x37, 0xee, 0xd8, 0x07, 0x72,
+	0x8f, 0xeb, 0xc7, 0x18, 0xb4, 0x0a, 0xa5, 0xac, 0xf1, 0x65, 0x01, 0x6f,
+	0xdd, 0xa9, 0x20, 0xa8, 0xb7, 0x81, 0x9d, 0x56, 0x43, 0x1f, 0x36, 0xce,
+	0xed, 0x92, 0xf2, 0x71, 0x22, 0x93, 0x33, 0x44, 0xfd, 0x45, 0xa3, 0xcc,
+	0xb8, 0xcd, 0x46, 0x1b, 0x93, 0x6e, 0x65, 0x30, 0x03, 0xea, 0x06, 0xda,
+	0xb6, 0x37, 0xc3, 0x7a, 0x1a, 0x89, 0x1f, 0xae, 0x63, 0x01, 0x6d, 0xf1,
+	0x3d, 0x3c, 0xc6, 0x9c, 0x81, 0xb4, 0x00, 0x4c, 0xef, 0xd2, 0xcc, 0xda,
+	0x9a, 0x48, 0x7b, 0xb9, 0x68, 0x09, 0x51, 0xf5, 0x7b, 0xf9, 0x09, 0x66,
+	0x1d, 0x27, 0x24, 0x06, 0xf4, 0x23, 0x64, 0x85, 0x56, 0xbb, 0x8e, 0xe2,
+	0xea, 0x33, 0x49, 0x13, 0x7a, 0x5e, 0x45, 0xf8, 0xf2, 0xd5, 0xd1, 0x62,
+	0x99, 0xee, 0x35, 0x58, 0x61, 0x61, 0xbf, 0x7c, 0xce, 0x29, 0xd4, 0x43,
+	0xfe, 0x7a, 0x1c, 0xa7, 0xd5, 0xa4, 0x11, 0x7e, 0xac, 0x50, 0x77, 0x6b,
+	0xff, 0xa6, 0xd9, 0xe7, 0x0c, 0x72, 0xcd, 0xdf, 0x63, 0x9b, 0xac, 0xc6,
+	0x15, 0x2a, 0x0c, 0x52, 0xb4, 0x42, 0x7b, 0xa8, 0x51, 0xae, 0xfc, 0x15,
+	0xcd, 0xce, 0x6c, 0xf4, 0xf8, 0x83, 0xdb, 0xcb, 0x59, 0x9e, 0xa5, 0x5c,
+	0x3b, 0xb1, 0x24, 0xbe, 0x6a, 0x2f, 0x3b, 0x8f, 0x1f, 0xd2, 0x16, 0x6f,
+	0xcb, 0x54, 0x97, 0x3b, 0x2a, 0x40, 0x04, 0x38, 0xb8, 0x1c, 0x31, 0xaa,
+	0xde, 0x65, 0x1c, 0x43, 0x1c, 0x2b, 0x4d, 0x92, 0x9e, 0x19, 0xb3, 0x4f,
+	0xb7, 0xec, 0x0a, 0x40, 0xb5, 0xc9, 0x3e, 0x26, 0xfe, 0x92, 0xbf, 0xe7,
+	0x1b, 0xdc, 0xef, 0x73, 0x06, 0xfa, 0x85, 0xdf, 0x7d, 0x5a, 0x9e, 0x82,
+	0x6b, 0x6a, 0x22, 0x94, 0xcf, 0x14, 0xff, 0x79, 0x94, 0x7d, 0x98, 0x00,
+	0xcd, 0x53, 0x59, 0xb4, 0x8e, 0xbb, 0x63, 0x58, 0xc4, 0x7f, 0x00, 0x28,
+	0x0f, 0x73, 0x12, 0xf4, 0xd1, 0xdf, 0xd0, 0x24, 0x37, 0xd4, 0xb4, 0x35,
+	0x9a, 0xeb, 0x88, 0x4d, 0x5e, 0xca, 0x8c, 0xc1, 0xd5, 0x70, 0xe1, 0xb3,
+	0xf0, 0x30, 0x7a, 0xfd, 0xb3, 0xef, 0x25, 0x09, 0xb3, 0xaa, 0xa3, 0xf8,
+	0xf3, 0x41, 0x2a, 0xcd, 0x74, 0xeb, 0x0f, 0x90, 0x36, 0x62, 0xf5, 0x48,
+	0x02, 0xd8, 0xd6, 0x9a, 0x05, 0x33, 0x43, 0xdb, 0xcb, 0x98, 0xd8, 0xb6,
+	0x83, 0xa4, 0x88, 0xdb, 0xee, 0x76, 0xef, 0xd4, 0xc8, 0x85, 0xf7, 0xc1,
+	0x10, 0x95, 0xf9, 0x57, 0xfb, 0x2d, 0xb7, 0x12, 0x49, 0x6e, 0xe0, 0xaf,
+	0x98, 0xd6, 0x3e, 0xc3, 0x85, 0x20, 0x8f, 0xf4, 0x83, 0xf4, 0x8a, 0x0a,
+	0xf6, 0x82, 0xec, 0x01, 0x02, 0x34, 0xc3, 0xe4, 0x14, 0x3f, 0x97, 0x8b,
+	0xa8, 0xc3, 0x42, 0x19, 0x4f, 0xfb, 0x31, 0x1a, 0xd3, 0x3a, 0xc7, 0x91,
+	0x60, 0x28, 0xda, 0xdb, 0x4a, 0xe8, 0x8c, 0xb0, 0xcc, 0xee, 0x0a, 0x4f,
+	0x33, 0x7f, 0x43, 0x6b, 0x7b, 0x50, 0xd0, 0xbf, 0xcf, 0xb4, 0x99, 0xfb,
+	0x5e, 0x7b, 0x0c, 0xc6, 0x4c, 0x81, 0x4f, 0xf1, 0xfa, 0xf2, 0x85, 0x44,
+	0x8b, 0x35, 0x1d, 0x3c, 0x42, 0xa1, 0x27, 0x1e, 0x7c, 0x1b, 0x05, 0x56,
+	0xa2, 0x7e, 0x08, 0xc8, 0x3f, 0x99, 0x2d, 0x64, 0xb7, 0x6b, 0x1c, 0x9e,
+	0xac, 0xd4, 0x95, 0xc7, 0x5d, 0xa7, 0x89, 0x0c, 0xed, 0x48, 0xf5, 0xc6,
+	0x21, 0x2c, 0x0c, 0xd1, 0xa9, 0x3c, 0x9e, 0xab, 0x17, 0xc2, 0xe4, 0xc8,
+	0x58, 0x1c, 0x1a, 0x9e, 0x2f, 0x07, 0x07, 0x29, 0x32, 0xeb, 0xb8, 0xac,
+	0xdd, 0x00, 0xf4, 0x8a, 0x3a, 0x66, 0x35, 0x27, 0x36, 0xdf, 0x46, 0x15,
+	0x68, 0xb7, 0x80, 0x30, 0xe0, 0x5a, 0x5e, 0x7e, 0x1d, 0x44, 0xa4, 0x0e,
+	0x5a, 0x65, 0x09, 0x1b, 0x6a, 0xb8, 0x88, 0x04, 0xcb, 0xb4, 0x14, 0xd9,
+	0x0e, 0xdd, 0xc8, 0x49, 0x10, 0x96, 0x9b, 0x38, 0x1a, 0xbf, 0x61, 0xb2,
+	0x69, 0x8e, 0xb2, 0xcd, 0xff, 0xab, 0xa3, 0x49, 0xa0, 0x7b, 0x2f, 0x58,
+	0xa8, 0x02, 0xc5, 0x79, 0x28, 0xca, 0xc1, 0xc5, 0x0f, 0x75, 0xa4, 0x32,
+	0x1b, 0xb4, 0x2e, 0xe9, 0x43, 0x91, 0x48, 0x13, 0x94, 0xa0, 0xa8, 0xc8,
+	0x90, 0xe9, 0x22, 0x20, 0xce, 0x50, 0x44, 0x76, 0xc8, 0x1b, 0x50, 0xbd,
+	0x59, 0x6f, 0xbd, 0xa9, 0x1e, 0x9e, 0x05, 0xa0, 0x23, 0x38, 0x68, 0x30,
+	0xef, 0x20, 0xff, 0x82, 0x11, 0xe3, 0x39, 0xc4, 0x98, 0x74, 0xdf, 0x1d,
+	0x0b, 0xeb, 0x9a, 0xc3, 0xb8, 0x4a, 0x90, 0x10, 0xde, 0x54, 0xef, 0x8a,
+	0xf0, 0x28, 0xe2, 0xba, 0x34, 0x94, 0xf2, 0x08, 0x04, 0x63, 0x94, 0x2f,
+	0xca, 0x9b, 0x64, 0xb6, 0x5f, 0xe7, 0xd7, 0x17, 0x01, 0xc9, 0xa4, 0x4d,
+	0x10, 0xff, 0xb9, 0xc7, 0x42, 0xf9, 0x34, 0xb6, 0x67, 0x50, 0x6c, 0x9e,
+	0xaa, 0x10, 0x2a, 0xac, 0x6a, 0x1e, 0xeb, 0xad, 0xf0, 0xb4, 0x0c, 0x08,
+	0xe7, 0x0e, 0xa6, 0xab, 0x23, 0x15, 0x77, 0x8f, 0xc5, 0x63, 0x5c, 0x8f,
+	0x8c, 0xd8, 0x68, 0x94, 0xaa, 0x3c, 0x5f, 0x6a, 0x2c, 0x48, 0x21, 0x7b,
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+	0x5f, 0x31, 0x30, 0x31, 0x30, 0x32, 0x35, 0x5f, 0x31, 0x5f, 0x38, 0x5f,
+	0x31, 0x5f, 0x65, 0x78, 0x70, 0x52, 0x4f, 0x4d, 0x5f, 0x46, 0x57, 0x5f,
+	0x75, 0x6e, 0x69, 0x5f, 0x74, 0x65, 0x6d, 0x70, 0x6c, 0x61, 0x74, 0x65,
+	0x5f, 0x65, 0x65, 0x70, 0x72, 0x6f, 0x6d, 0x30, 0x2e, 0x62, 0x69, 0x6e,
+	0x69, 0x51, 0x01, 0xe6, 0xb1, 0xf3, 0xe6, 0x0a, 0x5d, 0x59, 0x0a, 0x29,
+	0x3b, 0xdb, 0xab, 0xa8, 0x14, 0x25, 0xb9, 0x39, 0x25, 0x94, 0x4f, 0xfb,
+	0x45, 0xd1, 0x2f, 0x97, 0x1b, 0xa1, 0xc3, 0x53, 0x27, 0x5d, 0xd1, 0x23,
+	0x43, 0x7b, 0x46, 0x4c, 0x6d, 0xeb, 0x13, 0x91, 0xa3, 0x1a, 0x09, 0x18,
+	0x10, 0xf1, 0xaf, 0xf4, 0x59, 0xea, 0xf8, 0x3f, 0x1c, 0x7b, 0x6d, 0xed,
+	0xed, 0x04, 0x2d, 0x9e, 0x8c, 0xdc, 0xa8, 0xfc, 0x1d, 0x66, 0x0d, 0x03,
+	0xac, 0xcf, 0xb5, 0xd8, 0x0b, 0x0b, 0x66, 0x71, 0x28, 0x3a, 0x09, 0xe5,
+	0xe6, 0x79, 0xe8, 0xea, 0x72, 0xfc, 0xc6, 0x2e, 0x3c, 0x3f, 0xe5, 0xf5,
+	0x86, 0xa6, 0x12, 0x54, 0x28, 0x4c, 0xa2, 0xca, 0x66, 0x91, 0xa2, 0x46,
+	0x54, 0x29, 0xa0, 0xb8, 0x9c, 0x40, 0xd6, 0xbe, 0x36, 0xfd, 0xca, 0xae,
+	0x66, 0x3d, 0x43, 0xd1, 0xd8, 0x07, 0x04, 0x95, 0xd5, 0x79, 0xbd, 0x0f,
+	0xfe, 0xeb, 0x45, 0x7c, 0x52, 0x75, 0x6f, 0xab, 0x7b, 0xa0, 0xef, 0x18,
+	0x3f, 0x92, 0x38, 0x32, 0x79, 0x3d, 0x5b, 0x41, 0xe5, 0x15, 0x5c, 0x37,
+	0x42, 0x48, 0xe8, 0x50, 0x4b, 0x01, 0x02, 0x00, 0x00, 0x14, 0x00, 0x01,
+	0x00, 0x08, 0x00, 0xf7, 0x89, 0x59, 0x3d, 0xec, 0x91, 0x1c, 0xcd, 0x21,
+	0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x54, 0x31, 0x3a, 0x58, 0x33, 0x5f, 0x31, 0x30, 0x31, 0x30, 0x32,
+	0x35, 0x5f, 0x31, 0x5f, 0x38, 0x5f, 0x31, 0x5f, 0x65, 0x78, 0x70, 0x52,
+	0x4f, 0x4d, 0x5f, 0x46, 0x57, 0x5f, 0x75, 0x6e, 0x69, 0x5f, 0x74, 0x65,
+	0x6d, 0x70, 0x6c, 0x61, 0x74, 0x65, 0x5f, 0x72, 0x6d, 0x74, 0x5f, 0x63,
+	0x6d, 0x64, 0x5f, 0x6c, 0x69, 0x6e, 0x65, 0x2e, 0x74, 0x78, 0x74, 0x50,
+	0x4b, 0x01, 0x02, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00, 0x08, 0x00, 0xf7,
+	0x89, 0x59, 0x3d, 0xa2, 0xcb, 0x96, 0x76, 0x4c, 0xba, 0x02, 0x00, 0x00,
+	0x00, 0x20, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x00, 0x00, 0x54, 0x31, 0x3a,
+	0x58, 0x33, 0x5f, 0x31, 0x30, 0x31, 0x30, 0x32, 0x35, 0x5f, 0x31, 0x5f,
+	0x38, 0x5f, 0x31, 0x5f, 0x65, 0x78, 0x70, 0x52, 0x4f, 0x4d, 0x5f, 0x46,
+	0x57, 0x5f, 0x75, 0x6e, 0x69, 0x5f, 0x74, 0x65, 0x6d, 0x70, 0x6c, 0x61,
+	0x74, 0x65, 0x5f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x30, 0x2e, 0x62, 0x69,
+	0x6e, 0x50, 0x4b, 0x01, 0x02, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00, 0x08,
+	0x00, 0xf7, 0x89, 0x59, 0x3d, 0x49, 0x55, 0xd3, 0xe3, 0x9e, 0x00, 0x00,
+	0x00, 0x00, 0x04, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0xbb, 0x02, 0x00, 0x54,
+	0x31, 0x3a, 0x58, 0x33, 0x5f, 0x31, 0x30, 0x31, 0x30, 0x32, 0x35, 0x5f,
+	0x31, 0x5f, 0x38, 0x5f, 0x31, 0x5f, 0x65, 0x78, 0x70, 0x52, 0x4f, 0x4d,
+	0x5f, 0x46, 0x57, 0x5f, 0x75, 0x6e, 0x69, 0x5f, 0x74, 0x65, 0x6d, 0x70,
+	0x6c, 0x61, 0x74, 0x65, 0x5f, 0x65, 0x65, 0x70, 0x72, 0x6f, 0x6d, 0x30,
+	0x2e, 0x62, 0x69, 0x6e, 0x50, 0x4b, 0x01, 0x02, 0x00, 0x00, 0x14, 0x00,
+	0x01, 0x00, 0x08, 0x00, 0xf7, 0x89, 0x59, 0x3d, 0xec, 0x91, 0x1c, 0xcd,
+	0x21, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xbc,
+	0x02, 0x00, 0x54, 0x31, 0x41, 0x3a, 0x58, 0x33, 0x5f, 0x31, 0x30, 0x31,
+	0x30, 0x32, 0x35, 0x5f, 0x31, 0x5f, 0x38, 0x5f, 0x31, 0x5f, 0x65, 0x78,
+	0x70, 0x52, 0x4f, 0x4d, 0x5f, 0x46, 0x57, 0x5f, 0x75, 0x6e, 0x69, 0x5f,
+	0x74, 0x65, 0x6d, 0x70, 0x6c, 0x61, 0x74, 0x65, 0x5f, 0x72, 0x6d, 0x74,
+	0x5f, 0x63, 0x6d, 0x64, 0x5f, 0x6c, 0x69, 0x6e, 0x65, 0x2e, 0x74, 0x78,
+	0x74, 0x50, 0x4b, 0x01, 0x02, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00, 0x08,
+	0x00, 0xf7, 0x89, 0x59, 0x3d, 0x83, 0xee, 0x9e, 0xbf, 0x4b, 0xba, 0x02,
+	0x00, 0x00, 0x00, 0x20, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0xbc, 0x02, 0x00, 0x54,
+	0x31, 0x41, 0x3a, 0x58, 0x33, 0x5f, 0x31, 0x30, 0x31, 0x30, 0x32, 0x35,
+	0x5f, 0x31, 0x5f, 0x38, 0x5f, 0x31, 0x5f, 0x65, 0x78, 0x70, 0x52, 0x4f,
+	0x4d, 0x5f, 0x46, 0x57, 0x5f, 0x75, 0x6e, 0x69, 0x5f, 0x74, 0x65, 0x6d,
+	0x70, 0x6c, 0x61, 0x74, 0x65, 0x5f, 0x66, 0x6c, 0x61, 0x73, 0x68, 0x30,
+	0x2e, 0x62, 0x69, 0x6e, 0x50, 0x4b, 0x01, 0x02, 0x00, 0x00, 0x14, 0x00,
+	0x01, 0x00, 0x08, 0x00, 0xf7, 0x89, 0x59, 0x3d, 0x09, 0x33, 0x35, 0x25,
+	0x9f, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x77,
+	0x05, 0x00, 0x54, 0x31, 0x41, 0x3a, 0x58, 0x33, 0x5f, 0x31, 0x30, 0x31,
+	0x30, 0x32, 0x35, 0x5f, 0x31, 0x5f, 0x38, 0x5f, 0x31, 0x5f, 0x65, 0x78,
+	0x70, 0x52, 0x4f, 0x4d, 0x5f, 0x46, 0x57, 0x5f, 0x75, 0x6e, 0x69, 0x5f,
+	0x74, 0x65, 0x6d, 0x70, 0x6c, 0x61, 0x74, 0x65, 0x5f, 0x65, 0x65, 0x70,
+	0x72, 0x6f, 0x6d, 0x30, 0x2e, 0x62, 0x69, 0x6e, 0x50, 0x4b, 0x05, 0x06,
+	0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x5d, 0x02, 0x00, 0x00,
+	0x13, 0x78, 0x05, 0x00, 0x00, 0x00
+};
+unsigned int X3fw_ncf_len = 359046;
diff --git a/sys/dev/vxge/vxge-osdep.h b/sys/dev/vxge/vxge-osdep.h
new file mode 100644
index 000000000000..cc1dbd62a718
--- /dev/null
+++ b/sys/dev/vxge/vxge-osdep.h
@@ -0,0 +1,697 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+/* LINTLIBRARY */
+
+#ifndef	_VXGE_OSDEP_H_
+#define	_VXGE_OSDEP_H_
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#if __FreeBSD_version >= 800000
+#include <sys/buf_ring.h>
+#endif
+
+#include <sys/mbuf.h>
+#include <sys/protosw.h>
+#include <sys/socket.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/sockio.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/stddef.h>
+#include <sys/proc.h>
+#include <sys/endian.h>
+#include <sys/sysctl.h>
+#include <sys/pcpu.h>
+#include <sys/smp.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/bpf.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_var.h>
+#include <net/if_vlan_var.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip.h>
+#include <netinet/ip6.h>
+#include <netinet/tcp.h>
+#include <netinet/tcp_lro.h>
+#include <netinet/udp.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <machine/clock.h>
+#include <machine/stdarg.h>
+#include <machine/in_cksum.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pci_private.h>
+
+#include <dev/vxge/include/vxge-defs.h>
+
+/*
+ * ------------------------- includes and defines -------------------------
+ */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define	VXGE_OS_HOST_BIG_ENDIAN
+#else
+#define	VXGE_OS_HOST_LITTLE_ENDIAN
+#endif
+
+#if __LONG_BIT == 64
+#define	VXGE_OS_PLATFORM_64BIT
+#else
+#define	VXGE_OS_PLATFORM_32BIT
+#endif
+
+#define	VXGE_OS_PCI_CONFIG_SIZE		256
+#define	VXGE_OS_HOST_PAGE_SIZE		4096
+#define	VXGE_LL_IP_FAST_CSUM(hdr, len)	0
+
+#ifndef	__DECONST
+#define	__DECONST(type, var)	((type)(uintrptr_t)(const void *)(var))
+#endif
+
+typedef struct ifnet *ifnet_t;
+typedef struct mbuf *mbuf_t;
+typedef struct mbuf *OS_NETSTACK_BUF;
+
+typedef struct _vxge_bus_res_t {
+
+	u_long			bus_res_len;
+	bus_space_tag_t		bus_space_tag;		/* DMA Tag */
+	bus_space_handle_t	bus_space_handle;	/* Bus handle */
+	struct resource		*bar_start_addr;	/* BAR address */
+
+} vxge_bus_res_t;
+
+typedef struct _vxge_dma_alloc_t {
+
+	bus_addr_t		dma_paddr;		/* Physical Address */
+	caddr_t			dma_vaddr;		/* Virtual Address */
+	bus_dma_tag_t		dma_tag;		/* DMA Tag */
+	bus_dmamap_t		dma_map;		/* DMA Map */
+	bus_dma_segment_t	dma_segment;		/* DMA Segment */
+	bus_size_t		dma_size;		/* Size */
+	int			dma_nseg;		/* scatter-gather */
+
+} vxge_dma_alloc_t;
+
+typedef struct _vxge_pci_info {
+
+	device_t	ndev;		/* Device */
+	void		*reg_map[3];	/* BAR Resource */
+	struct resource	*bar_info[3];	/* BAR tag and handle */
+
+} vxge_pci_info_t;
+
+/*
+ * ---------------------- fixed size primitive types -----------------------
+ */
+typedef size_t			ptr_t;
+typedef int8_t			s8;
+typedef uint8_t			u8;
+typedef uint16_t		u16;
+typedef int32_t			s32;
+typedef uint32_t		u32;
+typedef unsigned long long int	u64;
+typedef boolean_t		bool;
+typedef bus_addr_t		dma_addr_t;
+typedef struct mtx		spinlock_t;
+typedef struct resource		*pci_irq_h;
+typedef vxge_pci_info_t		*pci_dev_h;
+typedef vxge_pci_info_t		*pci_cfg_h;
+typedef vxge_bus_res_t		*pci_reg_h;
+typedef vxge_dma_alloc_t	pci_dma_h;
+typedef vxge_dma_alloc_t	pci_dma_acc_h;
+
+/*
+ * -------------------------- "libc" functionality -------------------------
+ */
+#define	vxge_os_curr_time		systime
+#define	vxge_os_strcpy			strcpy
+#define	vxge_os_strlcpy			strlcpy
+#define	vxge_os_strlen			strlen
+#define	vxge_os_sprintf			sprintf
+#define	vxge_os_snprintf		snprintf
+#define	vxge_os_println(buf)		printf("%s\n", buf)
+#define	vxge_os_memzero			bzero
+#define	vxge_os_memcmp			memcmp
+#define	vxge_os_memcpy(dst, src, size)	bcopy(src, dst, size)
+
+#define	vxge_os_timestamp(buff) {			\
+	struct timeval cur_time;			\
+	gettimeofday(&cur_time, 0);			\
+	snprintf(buff, sizeof(buff), "%08li.%08li: ",	\
+		cur_time.tv_sec, cur_time.tv_usec);	\
+}
+
+#define	vxge_os_printf(fmt...) {			\
+	printf(fmt);					\
+	printf("\n");					\
+}
+
+#define	vxge_os_vaprintf(fmt...)			\
+	vxge_os_printf(fmt);
+
+#define	vxge_os_vasprintf(fmt...) {			\
+	vxge_os_printf(fmt);				\
+}
+
+#define	vxge_trace(trace, fmt, args...)			\
+	vxge_debug_uld(VXGE_COMPONENT_ULD,		\
+		trace, hldev, vpid, fmt, ## args)
+
+/*
+ * -------------------- synchronization primitives -------------------------
+ */
+/* Initialize the spin lock */
+#define	vxge_os_spin_lock_init(lockp, ctxh) {			\
+	if (mtx_initialized(lockp) == 0)			\
+		mtx_init((lockp), "vxge", NULL, MTX_DEF);	\
+}
+
+/* Initialize the spin lock (IRQ version) */
+#define	vxge_os_spin_lock_init_irq(lockp, ctxh) {		\
+	if (mtx_initialized(lockp) == 0)			\
+		mtx_init((lockp), "vxge", NULL, MTX_DEF);	\
+}
+
+/* Destroy the lock */
+#define	vxge_os_spin_lock_destroy(lockp, ctxh) {		\
+	if (mtx_initialized(lockp) != 0)			\
+		mtx_destroy(lockp);				\
+}
+
+/* Destroy the lock (IRQ version) */
+#define	vxge_os_spin_lock_destroy_irq(lockp, ctxh) {		\
+	if (mtx_initialized(lockp) != 0)			\
+		mtx_destroy(lockp);				\
+}
+
+/* Acquire the lock */
+#define	vxge_os_spin_lock(lockp) {				\
+	if (mtx_owned(lockp) == 0)				\
+		mtx_lock(lockp);				\
+}
+
+/* Release the lock */
+#define	vxge_os_spin_unlock(lockp)	mtx_unlock(lockp)
+
+/* Acquire the lock (IRQ version) */
+#define	vxge_os_spin_lock_irq(lockp, flags) {			\
+	flags = MTX_QUIET;					\
+	if (mtx_owned(lockp) == 0)				\
+		mtx_lock_flags(lockp, flags);			\
+}
+
+/* Release the lock (IRQ version) */
+#define	vxge_os_spin_unlock_irq(lockp, flags) {			\
+	flags = MTX_QUIET;					\
+	mtx_unlock_flags(lockp, flags);				\
+}
+
+/* Write memory	barrier	*/
+#if __FreeBSD_version <	800000
+#if defined(__i386__) || defined(__amd64__)
+#define	mb()  __asm volatile("mfence" ::: "memory")
+#define	wmb() __asm volatile("sfence" ::: "memory")
+#define	rmb() __asm volatile("lfence" ::: "memory")
+#else
+#define	mb()
+#define	rmb()
+#define	wmb()
+#endif
+#endif
+
+#define	vxge_os_wmb()		wmb()
+#define	vxge_os_udelay(x)	DELAY(x)
+#define	vxge_os_stall(x)	DELAY(x)
+#define	vxge_os_mdelay(x)	DELAY(x * 1000)
+#define	vxge_os_xchg		(targetp, newval)
+
+/*
+ * ------------------------- misc primitives -------------------------------
+ */
+#define	vxge_os_be32		u32
+#define	vxge_os_unlikely(x)	(x)
+#define	vxge_os_prefetch(x)	(x = x)
+#define	vxge_os_prefetchw(x)	(x = x)
+#define	vxge_os_bug		vxge_os_printf
+
+#define	vxge_os_ntohs		ntohs
+#define	vxge_os_ntohl		ntohl
+#define	vxge_os_ntohll		be64toh
+
+#define	vxge_os_htons		htons
+#define	vxge_os_htonl		htonl
+#define	vxge_os_htonll		htobe64
+
+#define	vxge_os_in_multicast		IN_MULTICAST
+#define	VXGE_OS_INADDR_BROADCAST	INADDR_BROADCAST
+/*
+ * -------------------------- compiler stuff ------------------------------
+ */
+#define	__vxge_os_cacheline_size	CACHE_LINE_SIZE
+#define	__vxge_os_attr_cacheline_aligned __aligned(__vxge_os_cacheline_size)
+
+/*
+ * ---------------------- memory primitives --------------------------------
+ */
+#if defined(VXGE_OS_MEMORY_CHECK)
+
+typedef struct _vxge_os_malloc_t {
+
+	u_long		line;
+	u_long		size;
+	void		*ptr;
+	const char	*file;
+
+} vxge_os_malloc_t;
+
+#define	VXGE_OS_MALLOC_CNT_MAX	64*1024
+
+extern u32 g_malloc_cnt;
+extern vxge_os_malloc_t g_malloc_arr[VXGE_OS_MALLOC_CNT_MAX];
+
+#define	VXGE_OS_MEMORY_CHECK_MALLOC(_vaddr, _size, _file, _line) {	\
+	if (_vaddr) {							\
+		u32 i;							\
+		for (i = 0; i < g_malloc_cnt; i++) {			\
+			if (g_malloc_arr[i].ptr == NULL)		\
+				break;					\
+		}							\
+		if (i == g_malloc_cnt) {				\
+			g_malloc_cnt++;					\
+			if (g_malloc_cnt >= VXGE_OS_MALLOC_CNT_MAX) {	\
+				vxge_os_bug("g_malloc_cnt exceed %d\n",	\
+				    VXGE_OS_MALLOC_CNT_MAX);		\
+			} else {					\
+				g_malloc_arr[i].ptr = _vaddr;		\
+				g_malloc_arr[i].size = _size;		\
+				g_malloc_arr[i].file = _file;		\
+				g_malloc_arr[i].line = _line;		\
+			}						\
+		}							\
+	}								\
+}
+
+#define	VXGE_OS_MEMORY_CHECK_FREE(_vaddr, _size, _file, _line) {	\
+	u32 i;								\
+	for (i = 0; i < VXGE_OS_MALLOC_CNT_MAX; i++) {			\
+		if (g_malloc_arr[i].ptr == _vaddr) {			\
+			g_malloc_arr[i].ptr = NULL;			\
+			if (_size && g_malloc_arr[i].size !=  _size) {	\
+				vxge_os_printf("freeing wrong size "	\
+				    "%lu allocated %s:%lu:"		\
+				    VXGE_OS_LLXFMT":%lu\n",		\
+				    _size,				\
+				    g_malloc_arr[i].file,		\
+				    g_malloc_arr[i].line,		\
+				    (u64)(u_long) g_malloc_arr[i].ptr,	\
+				    g_malloc_arr[i].size);		\
+			}						\
+			break;						\
+		}							\
+	}								\
+}
+
+#else
+#define	VXGE_OS_MEMORY_CHECK_MALLOC(prt, size, file, line)
+#define	VXGE_OS_MEMORY_CHECK_FREE(vaddr, size, file, line)
+#endif
+
+static inline void *
+vxge_mem_alloc_ex(u_long size, const char *file, int line)
+{
+	void *vaddr = NULL;
+	vaddr = malloc(size, M_DEVBUF, M_ZERO | M_NOWAIT);
+	if (NULL != vaddr) {
+		VXGE_OS_MEMORY_CHECK_MALLOC((void *)vaddr, size, file, line)
+		vxge_os_memzero(vaddr, size);
+	}
+
+	return (vaddr);
+}
+
+static inline void
+vxge_mem_free_ex(const void *vaddr, u_long size, const char *file, int line)
+{
+	if (NULL != vaddr) {
+		VXGE_OS_MEMORY_CHECK_FREE(vaddr, size, file, line)
+		free(__DECONST(void *, vaddr), M_DEVBUF);
+	}
+}
+
+#define	vxge_os_malloc(pdev, size)			\
+	vxge_mem_alloc_ex(size, __FILE__, __LINE__)
+
+#define	vxge_os_free(pdev, vaddr, size)			\
+	vxge_mem_free_ex(vaddr, size, __FILE__, __LINE__)
+
+#define	vxge_mem_alloc(size)				\
+	vxge_mem_alloc_ex(size, __FILE__, __LINE__)
+
+#define	vxge_mem_free(vaddr, size)			\
+	vxge_mem_free_ex(vaddr, size, __FILE__, __LINE__)
+
+#define	vxge_free_packet(x)				\
+	if (NULL != x) { m_freem(x); x = NULL; }
+
+/*
+ * --------------------------- pci primitives ------------------------------
+ */
+#define	vxge_os_pci_read8(pdev, cfgh, where, val)	\
+	(*(val) = pci_read_config(pdev->ndev, where, 1))
+
+#define	vxge_os_pci_write8(pdev, cfgh, where, val)	\
+	pci_write_config(pdev->ndev, where, val, 1)
+
+#define	vxge_os_pci_read16(pdev, cfgh, where, val)	\
+	(*(val) = pci_read_config(pdev->ndev, where, 2))
+
+#define	vxge_os_pci_write16(pdev, cfgh, where, val)	\
+	pci_write_config(pdev->ndev, where, val, 2)
+
+#define	vxge_os_pci_read32(pdev, cfgh, where, val)	\
+	(*(val) = pci_read_config(pdev->ndev, where, 4))
+
+#define	vxge_os_pci_write32(pdev, cfgh, where, val)	\
+	pci_write_config(pdev->ndev, where, val, 4)
+
+static inline u32
+vxge_os_pci_res_len(pci_dev_h pdev, pci_reg_h regh)
+{
+	return (((vxge_bus_res_t *) regh)->bus_res_len);
+}
+
+static inline u8
+vxge_os_pio_mem_read8(pci_dev_h pdev, pci_reg_h regh, void *addr)
+{
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
+
+	return bus_space_read_1(((vxge_bus_res_t *) regh)->bus_space_tag,
+				((vxge_bus_res_t *) regh)->bus_space_handle,
+				(bus_size_t) ((caddr_t) (addr) - vaddr));
+}
+
+static inline u16
+vxge_os_pio_mem_read16(pci_dev_h pdev, pci_reg_h regh, void *addr)
+{
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
+
+	return bus_space_read_2(((vxge_bus_res_t *) regh)->bus_space_tag,
+				((vxge_bus_res_t *) regh)->bus_space_handle,
+				(bus_size_t) ((caddr_t) (addr) - vaddr));
+}
+
+static inline u32
+vxge_os_pio_mem_read32(pci_dev_h pdev, pci_reg_h regh, void *addr)
+{
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
+
+	return bus_space_read_4(((vxge_bus_res_t *) regh)->bus_space_tag,
+				((vxge_bus_res_t *) regh)->bus_space_handle,
+				(bus_size_t) ((caddr_t) (addr) - vaddr));
+}
+
+static inline u64
+vxge_os_pio_mem_read64(pci_dev_h pdev, pci_reg_h regh, void *addr)
+{
+	u64 val, val_l, val_u;
+
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
+
+	val_l = bus_space_read_4(((vxge_bus_res_t *) regh)->bus_space_tag,
+				((vxge_bus_res_t *) regh)->bus_space_handle,
+				(bus_size_t) (((caddr_t) addr) + 4 - vaddr));
+
+	val_u = bus_space_read_4(((vxge_bus_res_t *) regh)->bus_space_tag,
+				((vxge_bus_res_t *) regh)->bus_space_handle,
+				(bus_size_t) ((caddr_t) (addr) - vaddr));
+
+	val = ((val_l << 32) | val_u);
+	return (val);
+}
+
+static inline void
+vxge_os_pio_mem_write8(pci_dev_h pdev, pci_reg_h regh, u8 val, void *addr)
+{
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) regh)->bar_start_addr);
+
+	bus_space_write_1(((vxge_bus_res_t *) regh)->bus_space_tag,
+			((vxge_bus_res_t *) regh)->bus_space_handle,
+			(bus_size_t) ((caddr_t) (addr) - vaddr), val);
+}
+
+static inline void
+vxge_os_pio_mem_write16(pci_dev_h pdev, pci_reg_h regh, u16 val, void *addr)
+{
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
+
+	bus_space_write_2(((vxge_bus_res_t *) regh)->bus_space_tag,
+			((vxge_bus_res_t *) regh)->bus_space_handle,
+			(bus_size_t) ((caddr_t) (addr) - vaddr), val);
+}
+
+static inline void
+vxge_os_pio_mem_write32(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr)
+{
+	caddr_t vaddr =
+	    (caddr_t) (((vxge_bus_res_t *) (regh))->bar_start_addr);
+
+	bus_space_write_4(((vxge_bus_res_t *) regh)->bus_space_tag,
+			((vxge_bus_res_t *) regh)->bus_space_handle,
+			(bus_size_t) ((caddr_t) (addr) - vaddr), val);
+}
+
+static inline void
+vxge_os_pio_mem_write64(pci_dev_h pdev, pci_reg_h regh, u64 val, void *addr)
+{
+	u32 val_l = (u32) (val & 0xffffffff);
+	u32 val_u = (u32) (val >> 32);
+
+	vxge_os_pio_mem_write32(pdev, regh, val_l, addr);
+	vxge_os_pio_mem_write32(pdev, regh, val_u, (caddr_t) addr + 4);
+}
+
+#define	vxge_os_flush_bridge	vxge_os_pio_mem_read64
+
+/*
+ * --------------------------- dma primitives -----------------------------
+ */
+#define	VXGE_OS_DMA_DIR_TODEVICE	0
+#define	VXGE_OS_DMA_DIR_FROMDEVICE	1
+#define	VXGE_OS_DMA_DIR_BIDIRECTIONAL	2
+#define	VXGE_OS_INVALID_DMA_ADDR	((bus_addr_t)0)
+
+static void
+vxge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+	if (error)
+		return;
+
+	*(bus_addr_t *) arg = segs->ds_addr;
+}
+
+static inline void *
+vxge_os_dma_malloc(pci_dev_h pdev, u_long bytes, int dma_flags,
+    pci_dma_h * p_dmah, pci_dma_acc_h * p_dma_acch)
+{
+	int error = 0;
+	bus_addr_t bus_addr = BUS_SPACE_MAXADDR;
+	bus_size_t boundary, max_size, alignment = PAGE_SIZE;
+
+	if (bytes > PAGE_SIZE) {
+		boundary = 0;
+		max_size = bytes;
+	} else {
+		boundary = PAGE_SIZE;
+		max_size = PAGE_SIZE;
+	}
+
+	error = bus_dma_tag_create(
+	    bus_get_dma_tag(pdev->ndev),	/* Parent */
+	    alignment,				/* Alignment */
+	    boundary,				/* Bounds */
+	    bus_addr,				/* Low Address */
+	    bus_addr,				/* High Address */
+	    NULL,				/* Filter Func */
+	    NULL,				/* Filter Func Argument */
+	    bytes,				/* Maximum Size */
+	    1,					/* Number of Segments */
+	    max_size,				/* Maximum Segment Size */
+	    BUS_DMA_ALLOCNOW,			/* Flags */
+	    NULL,				/* Lock Func */
+	    NULL,				/* Lock Func Arguments */
+	    &(p_dmah->dma_tag));		/* DMA Tag */
+
+	if (error != 0) {
+		device_printf(pdev->ndev, "bus_dma_tag_create failed\n");
+		goto _exit0;
+	}
+
+	p_dmah->dma_size = bytes;
+	error = bus_dmamem_alloc(p_dmah->dma_tag, (void **)&p_dmah->dma_vaddr,
+	    (BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT),
+	    &p_dmah->dma_map);
+	if (error != 0) {
+		device_printf(pdev->ndev, "bus_dmamem_alloc failed\n");
+		goto _exit1;
+	}
+
+	VXGE_OS_MEMORY_CHECK_MALLOC(p_dmah->dma_vaddr, p_dmah->dma_size,
+	    __FILE__, __LINE__);
+
+	return (p_dmah->dma_vaddr);
+
+_exit1:
+	bus_dma_tag_destroy(p_dmah->dma_tag);
+_exit0:
+	return (NULL);
+}
+
+static inline void
+vxge_dma_free(pci_dev_h pdev, const void *vaddr, u_long size,
+    pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch,
+    const char *file, int line)
+{
+	VXGE_OS_MEMORY_CHECK_FREE(p_dmah->dma_vaddr, size, file, line)
+
+	bus_dmamem_free(p_dmah->dma_tag, p_dmah->dma_vaddr, p_dmah->dma_map);
+	bus_dma_tag_destroy(p_dmah->dma_tag);
+
+	p_dmah->dma_map = NULL;
+	p_dmah->dma_tag = NULL;
+	p_dmah->dma_vaddr = NULL;
+}
+
+extern void
+vxge_hal_blockpool_block_add(void *, void *, u32, pci_dma_h *, pci_dma_acc_h *);
+
+static inline void
+vxge_os_dma_malloc_async(pci_dev_h pdev, void *devh,
+    u_long size, int dma_flags)
+{
+	pci_dma_h dma_h;
+	pci_dma_acc_h acc_handle;
+
+	void *block_addr = NULL;
+
+	block_addr = vxge_os_dma_malloc(pdev, size, dma_flags,
+	    &dma_h, &acc_handle);
+
+	vxge_hal_blockpool_block_add(devh, block_addr, size,
+	    &dma_h, &acc_handle);
+}
+
+static inline void
+vxge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah, dma_addr_t dma_paddr,
+    u64 dma_offset, size_t length, int dir)
+{
+	bus_dmasync_op_t dmasync_op;
+
+	switch (dir) {
+	case VXGE_OS_DMA_DIR_TODEVICE:
+		dmasync_op = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_POSTWRITE;
+		break;
+
+	case VXGE_OS_DMA_DIR_FROMDEVICE:
+		dmasync_op = BUS_DMASYNC_PREREAD | BUS_DMASYNC_POSTREAD;
+		break;
+
+	default:
+	case VXGE_OS_DMA_DIR_BIDIRECTIONAL:
+		dmasync_op = BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE;
+		break;
+	}
+
+	bus_dmamap_sync(dmah.dma_tag, dmah.dma_map, dmasync_op);
+}
+
+static inline dma_addr_t
+vxge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah, void *vaddr, u_long size,
+		int dir, int dma_flags)
+{
+	int error;
+
+	error = bus_dmamap_load(dmah.dma_tag, dmah.dma_map, dmah.dma_vaddr,
+	    dmah.dma_size, vxge_dmamap_cb, &(dmah.dma_paddr), BUS_DMA_NOWAIT);
+
+	if (error != 0)
+		return (VXGE_OS_INVALID_DMA_ADDR);
+
+	dmah.dma_size = size;
+	return (dmah.dma_paddr);
+}
+
+static inline void
+vxge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah, dma_addr_t dma_paddr,
+    u32 size, int dir)
+{
+	bus_dmamap_unload(dmah.dma_tag, dmah.dma_map);
+}
+
+#define	vxge_os_dma_free(pdev, vaddr, size, dma_flags, p_dma_acch, p_dmah)  \
+	vxge_dma_free(pdev, vaddr, size, p_dma_acch, p_dmah,		    \
+		__FILE__, __LINE__)
+
+static inline int
+vxge_os_is_my_packet(void *pdev, unsigned long addr)
+{
+	return (0);
+}
+
+#endif /* _VXGE_OSDEP_H_ */
diff --git a/sys/dev/vxge/vxge.c b/sys/dev/vxge/vxge.c
new file mode 100644
index 000000000000..05bbbb855a63
--- /dev/null
+++ b/sys/dev/vxge/vxge.c
@@ -0,0 +1,4216 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxge.h>
+
+static int vxge_pci_bd_no = -1;
+static u32 vxge_drv_copyright = 0;
+static u32 vxge_dev_ref_count = 0;
+static u32 vxge_dev_req_reboot = 0;
+
+static int vpath_selector[VXGE_HAL_MAX_VIRTUAL_PATHS] = \
+{0, 1, 3, 3, 7, 7, 7, 7, 15, 15, 15, 15, 15, 15, 15, 15, 31};
+
+/*
+ * vxge_probe
+ * Probes for x3100 devices
+ */
+int
+vxge_probe(device_t ndev)
+{
+	int err = ENXIO;
+
+	u16 pci_bd_no = 0;
+	u16 pci_vendor_id = 0;
+	u16 pci_device_id = 0;
+
+	char adapter_name[64];
+
+	pci_vendor_id = pci_get_vendor(ndev);
+	if (pci_vendor_id != VXGE_PCI_VENDOR_ID)
+		goto _exit0;
+
+	pci_device_id = pci_get_device(ndev);
+
+	if (pci_device_id == VXGE_PCI_DEVICE_ID_TITAN_1) {
+
+		pci_bd_no = (pci_get_bus(ndev) | pci_get_slot(ndev));
+
+		snprintf(adapter_name, sizeof(adapter_name),
+		    VXGE_ADAPTER_NAME, pci_get_revid(ndev));
+		device_set_desc_copy(ndev, adapter_name);
+
+		if (!vxge_drv_copyright) {
+			device_printf(ndev, VXGE_COPYRIGHT);
+			vxge_drv_copyright = 1;
+		}
+
+		if (vxge_dev_req_reboot == 0) {
+			vxge_pci_bd_no = pci_bd_no;
+			err = BUS_PROBE_DEFAULT;
+		} else {
+			if (pci_bd_no != vxge_pci_bd_no) {
+				vxge_pci_bd_no = pci_bd_no;
+				err = BUS_PROBE_DEFAULT;
+			}
+		}
+	}
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_attach
+ * Connects driver to the system if probe was success @ndev handle
+ */
+int
+vxge_attach(device_t ndev)
+{
+	int err = 0;
+	vxge_dev_t *vdev;
+	vxge_hal_device_t *hldev = NULL;
+	vxge_hal_device_attr_t device_attr;
+	vxge_free_resources_e error_level = VXGE_FREE_NONE;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	/* Get per-ndev buffer */
+	vdev = (vxge_dev_t *) device_get_softc(ndev);
+	if (!vdev)
+		goto _exit0;
+
+	bzero(vdev, sizeof(vxge_dev_t));
+
+	vdev->ndev = ndev;
+	strlcpy(vdev->ndev_name, "vxge", sizeof(vdev->ndev_name));
+
+	err = vxge_driver_config(vdev);
+	if (err != 0)
+		goto _exit0;
+
+	/* Initialize HAL driver */
+	status = vxge_driver_init(vdev);
+	if (status != VXGE_HAL_OK) {
+		device_printf(vdev->ndev, "Failed to initialize driver\n");
+		goto _exit0;
+	}
+	/* Enable PCI bus-master */
+	pci_enable_busmaster(ndev);
+
+	/* Allocate resources */
+	err = vxge_alloc_resources(vdev);
+	if (err != 0) {
+		device_printf(vdev->ndev, "resource allocation failed\n");
+		goto _exit0;
+	}
+
+	err = vxge_device_hw_info_get(vdev);
+	if (err != 0) {
+		error_level = VXGE_FREE_BAR2;
+		goto _exit0;
+	}
+
+	/* Get firmware default values for Device Configuration */
+	vxge_hal_device_config_default_get(vdev->device_config);
+
+	/* Customize Device Configuration based on User request */
+	vxge_vpath_config(vdev);
+
+	/* Allocate ISR resources */
+	err = vxge_alloc_isr_resources(vdev);
+	if (err != 0) {
+		error_level = VXGE_FREE_ISR_RESOURCE;
+		device_printf(vdev->ndev, "isr resource allocation failed\n");
+		goto _exit0;
+	}
+
+	/* HAL attributes */
+	device_attr.bar0 = (u8 *) vdev->pdev->bar_info[0];
+	device_attr.bar1 = (u8 *) vdev->pdev->bar_info[1];
+	device_attr.bar2 = (u8 *) vdev->pdev->bar_info[2];
+	device_attr.regh0 = (vxge_bus_res_t *) vdev->pdev->reg_map[0];
+	device_attr.regh1 = (vxge_bus_res_t *) vdev->pdev->reg_map[1];
+	device_attr.regh2 = (vxge_bus_res_t *) vdev->pdev->reg_map[2];
+	device_attr.irqh = (pci_irq_h) vdev->config.isr_info[0].irq_handle;
+	device_attr.cfgh = vdev->pdev;
+	device_attr.pdev = vdev->pdev;
+
+	/* Initialize HAL Device */
+	status = vxge_hal_device_initialize((vxge_hal_device_h *) &hldev,
+	    &device_attr, vdev->device_config);
+	if (status != VXGE_HAL_OK) {
+		error_level = VXGE_FREE_ISR_RESOURCE;
+		device_printf(vdev->ndev, "hal device initialization failed\n");
+		goto _exit0;
+	}
+
+	vdev->devh = hldev;
+	vxge_hal_device_private_set(hldev, vdev);
+
+	if (vdev->is_privilaged) {
+		err = vxge_firmware_verify(vdev);
+		if (err != 0) {
+			vxge_dev_req_reboot = 1;
+			error_level = VXGE_FREE_TERMINATE_DEVICE;
+			goto _exit0;
+		}
+	}
+
+	/* Allocate memory for vpath */
+	vdev->vpaths = (vxge_vpath_t *)
+	    vxge_mem_alloc(vdev->no_of_vpath * sizeof(vxge_vpath_t));
+
+	if (vdev->vpaths == NULL) {
+		error_level = VXGE_FREE_TERMINATE_DEVICE;
+		device_printf(vdev->ndev, "vpath memory allocation failed\n");
+		goto _exit0;
+	}
+
+	vdev->no_of_func = 1;
+	if (vdev->is_privilaged) {
+
+		vxge_hal_func_mode_count(vdev->devh,
+		    vdev->config.hw_info.function_mode, &vdev->no_of_func);
+
+		vxge_bw_priority_config(vdev);
+	}
+
+	/* Initialize mutexes */
+	vxge_mutex_init(vdev);
+
+	/* Initialize Media */
+	vxge_media_init(vdev);
+
+	err = vxge_ifp_setup(ndev);
+	if (err != 0) {
+		error_level = VXGE_FREE_MEDIA;
+		device_printf(vdev->ndev, "setting up interface failed\n");
+		goto _exit0;
+	}
+
+	err = vxge_isr_setup(vdev);
+	if (err != 0) {
+		error_level = VXGE_FREE_INTERFACE;
+		device_printf(vdev->ndev,
+		    "failed to associate interrupt handler with device\n");
+		goto _exit0;
+	}
+	vxge_device_hw_info_print(vdev);
+	vdev->is_active = TRUE;
+
+_exit0:
+	if (error_level) {
+		vxge_free_resources(ndev, error_level);
+		err = ENXIO;
+	}
+
+	return (err);
+}
+
+/*
+ * vxge_detach
+ * Detaches driver from the Kernel subsystem
+ */
+int
+vxge_detach(device_t ndev)
+{
+	vxge_dev_t *vdev;
+
+	vdev = (vxge_dev_t *) device_get_softc(ndev);
+	if (vdev->is_active) {
+		vdev->is_active = FALSE;
+		vxge_stop(vdev);
+		vxge_free_resources(ndev, VXGE_FREE_ALL);
+	}
+
+	return (0);
+}
+
+/*
+ * vxge_shutdown
+ * To shutdown device before system shutdown
+ */
+int
+vxge_shutdown(device_t ndev)
+{
+	vxge_dev_t *vdev = (vxge_dev_t *) device_get_softc(ndev);
+	vxge_stop(vdev);
+	return (0);
+}
+
+/*
+ * vxge_init
+ * Initialize the interface
+ */
+void
+vxge_init(void *vdev_ptr)
+{
+	vxge_dev_t *vdev = (vxge_dev_t *) vdev_ptr;
+
+	VXGE_DRV_LOCK(vdev);
+	vxge_init_locked(vdev);
+	VXGE_DRV_UNLOCK(vdev);
+}
+
+/*
+ * vxge_init_locked
+ * Initialize the interface
+ */
+void
+vxge_init_locked(vxge_dev_t *vdev)
+{
+	int i, err = EINVAL;
+	vxge_hal_device_t *hldev = vdev->devh;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_vpath_h vpath_handle;
+
+	ifnet_t ifp = vdev->ifp;
+
+	/* If device is in running state, initializing is not required */
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+		goto _exit0;
+
+	VXGE_DRV_LOCK_ASSERT(vdev);
+
+	/* Opening vpaths */
+	err = vxge_vpath_open(vdev);
+	if (err != 0)
+		goto _exit1;
+
+	if (vdev->config.rth_enable) {
+		status = vxge_rth_config(vdev);
+		if (status != VXGE_HAL_OK)
+			goto _exit1;
+	}
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath_handle = vxge_vpath_handle_get(vdev, i);
+		if (!vpath_handle)
+			continue;
+
+		/* check initial mtu before enabling the device */
+		status = vxge_hal_device_mtu_check(vpath_handle, ifp->if_mtu);
+		if (status != VXGE_HAL_OK) {
+			device_printf(vdev->ndev,
+			    "invalid mtu size %ld specified\n", ifp->if_mtu);
+			goto _exit1;
+		}
+
+		status = vxge_hal_vpath_mtu_set(vpath_handle, ifp->if_mtu);
+		if (status != VXGE_HAL_OK) {
+			device_printf(vdev->ndev,
+			    "setting mtu in device failed\n");
+			goto _exit1;
+		}
+	}
+
+	/* Enable HAL device */
+	status = vxge_hal_device_enable(hldev);
+	if (status != VXGE_HAL_OK) {
+		device_printf(vdev->ndev, "failed to enable device\n");
+		goto _exit1;
+	}
+
+	if (vdev->config.intr_mode == VXGE_HAL_INTR_MODE_MSIX)
+		vxge_msix_enable(vdev);
+
+	/* Checksum capability */
+	ifp->if_hwassist = 0;
+	if (ifp->if_capenable & IFCAP_TXCSUM)
+		ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP);
+
+	if (ifp->if_capenable & IFCAP_TSO4)
+		ifp->if_hwassist |= CSUM_TSO;
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath_handle = vxge_vpath_handle_get(vdev, i);
+		if (!vpath_handle)
+			continue;
+
+		/* Enabling bcast for all vpath */
+		status = vxge_hal_vpath_bcast_enable(vpath_handle);
+		if (status != VXGE_HAL_OK)
+			device_printf(vdev->ndev,
+			    "can't enable bcast on vpath (%d)\n", i);
+	}
+
+	/* Enable interrupts */
+	vxge_hal_device_intr_enable(vdev->devh);
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath_handle = vxge_vpath_handle_get(vdev, i);
+		if (!vpath_handle)
+			continue;
+
+		bzero(&(vdev->vpaths[i].driver_stats),
+		    sizeof(vxge_drv_stats_t));
+		status = vxge_hal_vpath_enable(vpath_handle);
+		if (status != VXGE_HAL_OK)
+			goto _exit2;
+	}
+
+	vxge_os_mdelay(1000);
+
+	/* Device is initialized */
+	vdev->is_initialized = TRUE;
+
+	/* Now inform the stack we're ready */
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	ifp->if_drv_flags |= IFF_DRV_RUNNING;
+
+	goto _exit0;
+
+_exit2:
+	vxge_hal_device_intr_disable(vdev->devh);
+	vxge_hal_device_disable(hldev);
+
+_exit1:
+	vxge_vpath_close(vdev);
+
+_exit0:
+	return;
+}
+
+/*
+ * vxge_driver_init
+ * Initializes HAL driver
+ */
+vxge_hal_status_e
+vxge_driver_init(vxge_dev_t *vdev)
+{
+	vxge_hal_uld_cbs_t uld_callbacks;
+	vxge_hal_driver_config_t driver_config;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	/* Initialize HAL driver */
+	if (!vxge_dev_ref_count) {
+		bzero(&uld_callbacks, sizeof(vxge_hal_uld_cbs_t));
+		bzero(&driver_config, sizeof(vxge_hal_driver_config_t));
+
+		uld_callbacks.link_up = vxge_link_up;
+		uld_callbacks.link_down = vxge_link_down;
+		uld_callbacks.crit_err = vxge_crit_error;
+		uld_callbacks.sched_timer = NULL;
+		uld_callbacks.xpak_alarm_log = NULL;
+
+		status = vxge_hal_driver_initialize(&driver_config,
+		    &uld_callbacks);
+		if (status != VXGE_HAL_OK) {
+			device_printf(vdev->ndev,
+			    "failed to initialize driver\n");
+			goto _exit0;
+		}
+	}
+	vxge_hal_driver_debug_set(VXGE_TRACE);
+	vxge_dev_ref_count++;
+
+_exit0:
+	return (status);
+}
+
+/*
+ * vxge_driver_config
+ */
+int
+vxge_driver_config(vxge_dev_t *vdev)
+{
+	int i, err = 0;
+	char temp_buffer[30];
+
+	vxge_bw_info_t bw_info;
+
+	VXGE_GET_PARAM("hint.vxge.0.no_of_vpath", vdev->config,
+	    no_of_vpath, VXGE_DEFAULT_USER_HARDCODED);
+
+	if (vdev->config.no_of_vpath == VXGE_DEFAULT_USER_HARDCODED)
+		vdev->config.no_of_vpath = mp_ncpus;
+
+	if (vdev->config.no_of_vpath <= 0) {
+		err = EINVAL;
+		device_printf(vdev->ndev,
+		    "Failed to load driver, \
+		    invalid config : \'no_of_vpath\'\n");
+		goto _exit0;
+	}
+
+	VXGE_GET_PARAM("hint.vxge.0.intr_coalesce", vdev->config,
+	    intr_coalesce, VXGE_DEFAULT_CONFIG_DISABLE);
+
+	VXGE_GET_PARAM("hint.vxge.0.rth_enable", vdev->config,
+	    rth_enable, VXGE_DEFAULT_CONFIG_ENABLE);
+
+	VXGE_GET_PARAM("hint.vxge.0.rth_bkt_sz", vdev->config,
+	    rth_bkt_sz, VXGE_DEFAULT_RTH_BUCKET_SIZE);
+
+	VXGE_GET_PARAM("hint.vxge.0.lro_enable", vdev->config,
+	    lro_enable, VXGE_DEFAULT_CONFIG_ENABLE);
+
+	VXGE_GET_PARAM("hint.vxge.0.tso_enable", vdev->config,
+	    tso_enable, VXGE_DEFAULT_CONFIG_ENABLE);
+
+	VXGE_GET_PARAM("hint.vxge.0.tx_steering", vdev->config,
+	    tx_steering, VXGE_DEFAULT_CONFIG_DISABLE);
+
+	VXGE_GET_PARAM("hint.vxge.0.msix_enable", vdev->config,
+	    intr_mode, VXGE_HAL_INTR_MODE_MSIX);
+
+	VXGE_GET_PARAM("hint.vxge.0.ifqmaxlen", vdev->config,
+	    ifq_maxlen, VXGE_DEFAULT_CONFIG_IFQ_MAXLEN);
+
+	VXGE_GET_PARAM("hint.vxge.0.port_mode", vdev->config,
+	    port_mode, VXGE_DEFAULT_CONFIG_VALUE);
+
+	if (vdev->config.port_mode == VXGE_DEFAULT_USER_HARDCODED)
+		vdev->config.port_mode = VXGE_DEFAULT_CONFIG_VALUE;
+
+	VXGE_GET_PARAM("hint.vxge.0.l2_switch", vdev->config,
+	    l2_switch, VXGE_DEFAULT_CONFIG_VALUE);
+
+	if (vdev->config.l2_switch == VXGE_DEFAULT_USER_HARDCODED)
+		vdev->config.l2_switch = VXGE_DEFAULT_CONFIG_VALUE;
+
+	VXGE_GET_PARAM("hint.vxge.0.fw_upgrade", vdev->config,
+	    fw_option, VXGE_FW_UPGRADE_ALL);
+
+	VXGE_GET_PARAM("hint.vxge.0.low_latency", vdev->config,
+	    low_latency, VXGE_DEFAULT_CONFIG_DISABLE);
+
+	VXGE_GET_PARAM("hint.vxge.0.func_mode", vdev->config,
+	    function_mode, VXGE_DEFAULT_CONFIG_VALUE);
+
+	if (vdev->config.function_mode == VXGE_DEFAULT_USER_HARDCODED)
+		vdev->config.function_mode = VXGE_DEFAULT_CONFIG_VALUE;
+
+	if (!(is_multi_func(vdev->config.function_mode) ||
+	    is_single_func(vdev->config.function_mode)))
+		vdev->config.function_mode = VXGE_DEFAULT_CONFIG_VALUE;
+
+	for (i = 0; i < VXGE_HAL_MAX_FUNCTIONS; i++) {
+
+		bw_info.func_id = i;
+
+		sprintf(temp_buffer, "hint.vxge.0.bandwidth_%d", i);
+		VXGE_GET_PARAM(temp_buffer, bw_info,
+		    bandwidth, VXGE_DEFAULT_USER_HARDCODED);
+
+		if (bw_info.bandwidth == VXGE_DEFAULT_USER_HARDCODED)
+			bw_info.bandwidth = VXGE_HAL_VPATH_BW_LIMIT_DEFAULT;
+
+		sprintf(temp_buffer, "hint.vxge.0.priority_%d", i);
+		VXGE_GET_PARAM(temp_buffer, bw_info,
+		    priority, VXGE_DEFAULT_USER_HARDCODED);
+
+		if (bw_info.priority == VXGE_DEFAULT_USER_HARDCODED)
+			bw_info.priority = VXGE_HAL_VPATH_PRIORITY_DEFAULT;
+
+		vxge_os_memcpy(&vdev->config.bw_info[i], &bw_info,
+		    sizeof(vxge_bw_info_t));
+	}
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_stop
+ */
+void
+vxge_stop(vxge_dev_t *vdev)
+{
+	VXGE_DRV_LOCK(vdev);
+	vxge_stop_locked(vdev);
+	VXGE_DRV_UNLOCK(vdev);
+}
+
+/*
+ * vxge_stop_locked
+ * Common code for both stop and part of reset.
+ * disables device, interrupts and closes vpaths handle
+ */
+void
+vxge_stop_locked(vxge_dev_t *vdev)
+{
+	u64 adapter_status = 0;
+	vxge_hal_status_e status;
+	vxge_hal_device_t *hldev = vdev->devh;
+	ifnet_t ifp = vdev->ifp;
+
+	VXGE_DRV_LOCK_ASSERT(vdev);
+
+	/* If device is not in "Running" state, return */
+	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+		return;
+
+	/* Set appropriate flags */
+	vdev->is_initialized = FALSE;
+	hldev->link_state = VXGE_HAL_LINK_NONE;
+	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	if_link_state_change(ifp, LINK_STATE_DOWN);
+
+	/* Disable interrupts */
+	vxge_hal_device_intr_disable(hldev);
+
+	/* Disable HAL device */
+	status = vxge_hal_device_disable(hldev);
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_device_status(hldev, &adapter_status);
+		device_printf(vdev->ndev,
+		    "adapter status: 0x%llx\n", adapter_status);
+	}
+
+	/* reset vpaths */
+	vxge_vpath_reset(vdev);
+
+	vxge_os_mdelay(1000);
+
+	/* Close Vpaths */
+	vxge_vpath_close(vdev);
+}
+
+void
+vxge_send(ifnet_t ifp)
+{
+	vxge_vpath_t *vpath;
+	vxge_dev_t *vdev = (vxge_dev_t *) ifp->if_softc;
+
+	vpath = &(vdev->vpaths[0]);
+
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+		if (VXGE_TX_TRYLOCK(vpath)) {
+			vxge_send_locked(ifp, vpath);
+			VXGE_TX_UNLOCK(vpath);
+		}
+	}
+}
+
+static inline void
+vxge_send_locked(ifnet_t ifp, vxge_vpath_t *vpath)
+{
+	mbuf_t m_head = NULL;
+	vxge_dev_t *vdev = vpath->vdev;
+
+	VXGE_TX_LOCK_ASSERT(vpath);
+
+	if ((!vdev->is_initialized) ||
+	    ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+	    IFF_DRV_RUNNING))
+		return;
+
+	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		if (vxge_xmit(ifp, vpath, &m_head)) {
+			if (m_head == NULL)
+				break;
+
+			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			VXGE_DRV_STATS(vpath, tx_again);
+			break;
+		}
+		/* Send a copy of the frame to the BPF listener */
+		ETHER_BPF_MTAP(ifp, m_head);
+	}
+}
+
+#if __FreeBSD_version >= 800000
+
+int
+vxge_mq_send(ifnet_t ifp, mbuf_t m_head)
+{
+	int i = 0, err = 0;
+
+	vxge_vpath_t *vpath;
+	vxge_dev_t *vdev = (vxge_dev_t *) ifp->if_softc;
+
+	if (vdev->config.tx_steering) {
+		i = vxge_vpath_get(vdev, m_head);
+	} else if ((m_head->m_flags & M_FLOWID) != 0) {
+		i = m_head->m_pkthdr.flowid % vdev->no_of_vpath;
+	}
+
+	vpath = &(vdev->vpaths[i]);
+	if (VXGE_TX_TRYLOCK(vpath)) {
+		err = vxge_mq_send_locked(ifp, vpath, m_head);
+		VXGE_TX_UNLOCK(vpath);
+	} else
+		err = drbr_enqueue(ifp, vpath->br, m_head);
+
+	return (err);
+}
+
+static inline int
+vxge_mq_send_locked(ifnet_t ifp, vxge_vpath_t *vpath, mbuf_t m_head)
+{
+	int err = 0;
+	mbuf_t next = NULL;
+	vxge_dev_t *vdev = vpath->vdev;
+
+	VXGE_TX_LOCK_ASSERT(vpath);
+
+	if ((!vdev->is_initialized) ||
+	    ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+	    IFF_DRV_RUNNING)) {
+		err = drbr_enqueue(ifp, vpath->br, m_head);
+		goto _exit0;
+	}
+	if (m_head == NULL) {
+		next = drbr_dequeue(ifp, vpath->br);
+	} else if (drbr_needs_enqueue(ifp, vpath->br)) {
+		if ((err = drbr_enqueue(ifp, vpath->br, m_head)) != 0)
+			goto _exit0;
+		next = drbr_dequeue(ifp, vpath->br);
+	} else
+		next = m_head;
+
+	/* Process the queue */
+	while (next != NULL) {
+		if ((err = vxge_xmit(ifp, vpath, &next)) != 0) {
+			if (next == NULL)
+				break;
+
+			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			err = drbr_enqueue(ifp, vpath->br, next);
+			VXGE_DRV_STATS(vpath, tx_again);
+			break;
+		}
+		drbr_stats_update(ifp, next->m_pkthdr.len, next->m_flags);
+
+		/* Send a copy of the frame to the BPF listener */
+		ETHER_BPF_MTAP(ifp, next);
+		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+			break;
+
+		next = drbr_dequeue(ifp, vpath->br);
+	}
+
+_exit0:
+	return (err);
+}
+
+void
+vxge_mq_qflush(ifnet_t ifp)
+{
+	int i;
+	mbuf_t m_head;
+	vxge_vpath_t *vpath;
+
+	vxge_dev_t *vdev = (vxge_dev_t *) ifp->if_softc;
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath = &(vdev->vpaths[i]);
+		if (!vpath->handle)
+			continue;
+
+		VXGE_TX_LOCK(vpath);
+		while ((m_head = buf_ring_dequeue_sc(vpath->br)) != NULL)
+			vxge_free_packet(m_head);
+
+		VXGE_TX_UNLOCK(vpath);
+	}
+	if_qflush(ifp);
+}
+#endif
+
+static inline int
+vxge_xmit(ifnet_t ifp, vxge_vpath_t *vpath, mbuf_t *m_headp)
+{
+	int err, num_segs = 0;
+	u32 txdl_avail, dma_index, tagged = 0;
+
+	dma_addr_t dma_addr;
+	bus_size_t dma_sizes;
+
+	void *dtr_priv;
+	vxge_txdl_priv_t *txdl_priv;
+	vxge_hal_txdl_h txdlh;
+	vxge_hal_status_e status;
+	vxge_dev_t *vdev = vpath->vdev;
+
+	VXGE_DRV_STATS(vpath, tx_xmit);
+
+	txdl_avail = vxge_hal_fifo_free_txdl_count_get(vpath->handle);
+	if (txdl_avail < VXGE_TX_LOW_THRESHOLD) {
+
+		VXGE_DRV_STATS(vpath, tx_low_dtr_cnt);
+		err = ENOBUFS;
+		goto _exit0;
+	}
+
+	/* Reserve descriptors */
+	status = vxge_hal_fifo_txdl_reserve(vpath->handle, &txdlh, &dtr_priv);
+	if (status != VXGE_HAL_OK) {
+		VXGE_DRV_STATS(vpath, tx_reserve_failed);
+		err = ENOBUFS;
+		goto _exit0;
+	}
+
+	/* Update Tx private structure for this descriptor */
+	txdl_priv = (vxge_txdl_priv_t *) dtr_priv;
+
+	/*
+	 * Map the packet for DMA.
+	 * Returns number of segments through num_segs.
+	 */
+	err = vxge_dma_mbuf_coalesce(vpath->dma_tag_tx, txdl_priv->dma_map,
+	    m_headp, txdl_priv->dma_buffers, &num_segs);
+
+	if (vpath->driver_stats.tx_max_frags < num_segs)
+		vpath->driver_stats.tx_max_frags = num_segs;
+
+	if (err == ENOMEM) {
+		VXGE_DRV_STATS(vpath, tx_no_dma_setup);
+		vxge_hal_fifo_txdl_free(vpath->handle, txdlh);
+		goto _exit0;
+	} else if (err != 0) {
+		vxge_free_packet(*m_headp);
+		VXGE_DRV_STATS(vpath, tx_no_dma_setup);
+		vxge_hal_fifo_txdl_free(vpath->handle, txdlh);
+		goto _exit0;
+	}
+
+	txdl_priv->mbuf_pkt = *m_headp;
+
+	/* Set VLAN tag in descriptor only if this packet has it */
+	if ((*m_headp)->m_flags & M_VLANTAG)
+		vxge_hal_fifo_txdl_vlan_set(txdlh,
+		    (*m_headp)->m_pkthdr.ether_vtag);
+
+	/* Set descriptor buffer for header and each fragment/segment */
+	for (dma_index = 0; dma_index < num_segs; dma_index++) {
+
+		dma_sizes = txdl_priv->dma_buffers[dma_index].ds_len;
+		dma_addr = htole64(txdl_priv->dma_buffers[dma_index].ds_addr);
+
+		vxge_hal_fifo_txdl_buffer_set(vpath->handle, txdlh, dma_index,
+		    dma_addr, dma_sizes);
+	}
+
+	/* Pre-write Sync of mapping */
+	bus_dmamap_sync(vpath->dma_tag_tx, txdl_priv->dma_map,
+	    BUS_DMASYNC_PREWRITE);
+
+	if ((*m_headp)->m_pkthdr.csum_flags & CSUM_TSO) {
+		if ((*m_headp)->m_pkthdr.tso_segsz) {
+			VXGE_DRV_STATS(vpath, tx_tso);
+			vxge_hal_fifo_txdl_lso_set(txdlh,
+			    VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO,
+			    (*m_headp)->m_pkthdr.tso_segsz);
+		}
+	}
+
+	/* Checksum */
+	if (ifp->if_hwassist > 0) {
+		vxge_hal_fifo_txdl_cksum_set_bits(txdlh,
+		    VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN |
+		    VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN |
+		    VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN);
+	}
+
+	if ((vxge_hal_device_check_id(vdev->devh) == VXGE_HAL_CARD_TITAN_1A) &&
+	    (vdev->hw_fw_version >= VXGE_FW_VERSION(1, 8, 0)))
+		tagged = 1;
+
+	vxge_hal_fifo_txdl_post(vpath->handle, txdlh, tagged);
+	VXGE_DRV_STATS(vpath, tx_posted);
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_tx_replenish
+ * Allocate buffers and set them into descriptors for later use
+ */
+/* ARGSUSED */
+vxge_hal_status_e
+vxge_tx_replenish(vxge_hal_vpath_h vpath_handle, vxge_hal_txdl_h txdlh,
+    void *dtr_priv, u32 dtr_index, void *userdata, vxge_hal_reopen_e reopen)
+{
+	int err = 0;
+
+	vxge_vpath_t *vpath = (vxge_vpath_t *) userdata;
+	vxge_txdl_priv_t *txdl_priv = (vxge_txdl_priv_t *) dtr_priv;
+
+	err = bus_dmamap_create(vpath->dma_tag_tx, BUS_DMA_NOWAIT,
+	    &txdl_priv->dma_map);
+
+	return ((err == 0) ? VXGE_HAL_OK : VXGE_HAL_FAIL);
+}
+
+/*
+ * vxge_tx_compl
+ * If the interrupt is due to Tx completion, free the sent buffer
+ */
+vxge_hal_status_e
+vxge_tx_compl(vxge_hal_vpath_h vpath_handle, vxge_hal_txdl_h txdlh,
+    void *dtr_priv, vxge_hal_fifo_tcode_e t_code, void *userdata)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_txdl_priv_t *txdl_priv;
+	vxge_vpath_t *vpath = (vxge_vpath_t *) userdata;
+	vxge_dev_t *vdev = vpath->vdev;
+
+	ifnet_t ifp = vdev->ifp;
+
+	VXGE_TX_LOCK(vpath);
+
+	/*
+	 * For each completed descriptor
+	 * Get private structure, free buffer, do unmapping, and free descriptor
+	 */
+
+	do {
+		VXGE_DRV_STATS(vpath, tx_compl);
+		if (t_code != VXGE_HAL_FIFO_T_CODE_OK) {
+			device_printf(vdev->ndev, "tx transfer code %d\n",
+			    t_code);
+
+			ifp->if_oerrors++;
+			VXGE_DRV_STATS(vpath, tx_tcode);
+			vxge_hal_fifo_handle_tcode(vpath_handle, txdlh, t_code);
+		}
+		ifp->if_opackets++;
+		txdl_priv = (vxge_txdl_priv_t *) dtr_priv;
+
+		bus_dmamap_unload(vpath->dma_tag_tx, txdl_priv->dma_map);
+
+		vxge_free_packet(txdl_priv->mbuf_pkt);
+		vxge_hal_fifo_txdl_free(vpath->handle, txdlh);
+
+	} while (vxge_hal_fifo_txdl_next_completed(vpath_handle, &txdlh,
+	    &dtr_priv, &t_code) == VXGE_HAL_OK);
+
+
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	VXGE_TX_UNLOCK(vpath);
+
+	return (status);
+}
+
+/* ARGSUSED */
+void
+vxge_tx_term(vxge_hal_vpath_h vpath_handle, vxge_hal_txdl_h txdlh,
+    void *dtr_priv, vxge_hal_txdl_state_e state,
+    void *userdata, vxge_hal_reopen_e reopen)
+{
+	vxge_vpath_t *vpath = (vxge_vpath_t *) userdata;
+	vxge_txdl_priv_t *txdl_priv = (vxge_txdl_priv_t *) dtr_priv;
+
+	if (state != VXGE_HAL_TXDL_STATE_POSTED)
+		return;
+
+	if (txdl_priv != NULL) {
+		bus_dmamap_sync(vpath->dma_tag_tx, txdl_priv->dma_map,
+		    BUS_DMASYNC_POSTWRITE);
+
+		bus_dmamap_unload(vpath->dma_tag_tx, txdl_priv->dma_map);
+		bus_dmamap_destroy(vpath->dma_tag_tx, txdl_priv->dma_map);
+		vxge_free_packet(txdl_priv->mbuf_pkt);
+	}
+
+	/* Free the descriptor */
+	vxge_hal_fifo_txdl_free(vpath->handle, txdlh);
+}
+
+/*
+ * vxge_rx_replenish
+ * Allocate buffers and set them into descriptors for later use
+ */
+/* ARGSUSED */
+vxge_hal_status_e
+vxge_rx_replenish(vxge_hal_vpath_h vpath_handle, vxge_hal_rxd_h rxdh,
+    void *dtr_priv, u32 dtr_index, void *userdata, vxge_hal_reopen_e reopen)
+{
+	int err = 0;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_vpath_t *vpath = (vxge_vpath_t *) userdata;
+	vxge_rxd_priv_t *rxd_priv = (vxge_rxd_priv_t *) dtr_priv;
+
+	/* Create DMA map for these descriptors */
+	err = bus_dmamap_create(vpath->dma_tag_rx, BUS_DMA_NOWAIT,
+	    &rxd_priv->dma_map);
+	if (err == 0) {
+		if (vxge_rx_rxd_1b_set(vpath, rxdh, dtr_priv)) {
+			bus_dmamap_destroy(vpath->dma_tag_rx,
+			    rxd_priv->dma_map);
+			status = VXGE_HAL_FAIL;
+		}
+	}
+
+	return (status);
+}
+
+/*
+ * vxge_rx_compl
+ */
+vxge_hal_status_e
+vxge_rx_compl(vxge_hal_vpath_h vpath_handle, vxge_hal_rxd_h rxdh,
+    void *dtr_priv, u8 t_code, void *userdata)
+{
+	mbuf_t mbuf_up;
+
+	vxge_rxd_priv_t *rxd_priv;
+	vxge_hal_ring_rxd_info_t ext_info;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_vpath_t *vpath = (vxge_vpath_t *) userdata;
+	vxge_dev_t *vdev = vpath->vdev;
+
+	struct lro_entry *queued = NULL;
+	struct lro_ctrl *lro = &vpath->lro;
+
+	/* get the interface pointer */
+	ifnet_t ifp = vdev->ifp;
+
+	do {
+		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+			vxge_hal_ring_rxd_post(vpath_handle, rxdh);
+			status = VXGE_HAL_FAIL;
+			break;
+		}
+
+		VXGE_DRV_STATS(vpath, rx_compl);
+		rxd_priv = (vxge_rxd_priv_t *) dtr_priv;
+
+		/* Gets details of mbuf i.e., packet length */
+		vxge_rx_rxd_1b_get(vpath, rxdh, dtr_priv);
+
+		/*
+		 * Prepare one buffer to send it to upper layer Since upper
+		 * layer frees the buffer do not use rxd_priv->mbuf_pkt.
+		 * Meanwhile prepare a new buffer, do mapping, use with the
+		 * current descriptor and post descriptor back to ring vpath
+		 */
+		mbuf_up = rxd_priv->mbuf_pkt;
+		if (t_code != VXGE_HAL_RING_RXD_T_CODE_OK) {
+
+			ifp->if_ierrors++;
+			VXGE_DRV_STATS(vpath, rx_tcode);
+			status = vxge_hal_ring_handle_tcode(vpath_handle,
+			    rxdh, t_code);
+
+			/*
+			 * If transfer code is not for unknown protocols and
+			 * vxge_hal_device_handle_tcode is NOT returned
+			 * VXGE_HAL_OK
+			 * drop this packet and increment rx_tcode stats
+			 */
+			if ((status != VXGE_HAL_OK) &&
+			    (t_code != VXGE_HAL_RING_T_CODE_L3_PKT_ERR)) {
+
+				vxge_free_packet(mbuf_up);
+				vxge_hal_ring_rxd_post(vpath_handle, rxdh);
+				continue;
+			}
+		}
+
+		if (vxge_rx_rxd_1b_set(vpath, rxdh, dtr_priv)) {
+			/*
+			 * If unable to allocate buffer, post descriptor back
+			 * to vpath for future processing of same packet.
+			 */
+			vxge_hal_ring_rxd_post(vpath_handle, rxdh);
+			continue;
+		}
+
+		/* Get the extended information */
+		vxge_hal_ring_rxd_1b_info_get(vpath_handle, rxdh, &ext_info);
+
+		/* post descriptor with newly allocated mbuf back to vpath */
+		vxge_hal_ring_rxd_post(vpath_handle, rxdh);
+		vpath->rxd_posted++;
+
+		if (vpath->rxd_posted % VXGE_RXD_REPLENISH_COUNT == 0)
+			vxge_hal_ring_rxd_post_post_db(vpath_handle);
+
+		/*
+		 * Set successfully computed checksums in the mbuf.
+		 * Leave the rest to the stack to be reverified.
+		 */
+		vxge_rx_checksum(ext_info, mbuf_up);
+
+#if __FreeBSD_version >= 800000
+		mbuf_up->m_flags |= M_FLOWID;
+		mbuf_up->m_pkthdr.flowid = vpath->vp_index;
+#endif
+		/* Post-Read sync for buffers */
+		bus_dmamap_sync(vpath->dma_tag_rx, rxd_priv->dma_map,
+		    BUS_DMASYNC_POSTREAD);
+
+		vxge_rx_input(ifp, mbuf_up, vpath);
+
+	} while (vxge_hal_ring_rxd_next_completed(vpath_handle, &rxdh,
+	    &dtr_priv, &t_code) == VXGE_HAL_OK);
+
+	/* Flush any outstanding LRO work */
+	if (vpath->lro_enable && vpath->lro.lro_cnt) {
+		while ((queued = SLIST_FIRST(&lro->lro_active)) != NULL) {
+			SLIST_REMOVE_HEAD(&lro->lro_active, next);
+			tcp_lro_flush(lro, queued);
+		}
+	}
+
+	return (status);
+}
+
+static inline void
+vxge_rx_input(ifnet_t ifp, mbuf_t mbuf_up, vxge_vpath_t *vpath)
+{
+	if (vpath->lro_enable && vpath->lro.lro_cnt) {
+		if (tcp_lro_rx(&vpath->lro, mbuf_up, 0) == 0)
+			return;
+	}
+	(*ifp->if_input) (ifp, mbuf_up);
+}
+
+static inline void
+vxge_rx_checksum(vxge_hal_ring_rxd_info_t ext_info, mbuf_t mbuf_up)
+{
+
+	if (!(ext_info.proto & VXGE_HAL_FRAME_PROTO_IP_FRAG) &&
+	    (ext_info.proto & VXGE_HAL_FRAME_PROTO_TCP_OR_UDP) &&
+	    ext_info.l3_cksum_valid && ext_info.l4_cksum_valid) {
+
+		mbuf_up->m_pkthdr.csum_data = htons(0xffff);
+
+		mbuf_up->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
+		mbuf_up->m_pkthdr.csum_flags |= CSUM_IP_VALID;
+		mbuf_up->m_pkthdr.csum_flags |=
+		    (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
+
+	} else {
+
+		if (ext_info.vlan) {
+			mbuf_up->m_pkthdr.ether_vtag = ext_info.vlan;
+			mbuf_up->m_flags |= M_VLANTAG;
+		}
+	}
+}
+
+/*
+ * vxge_rx_term During unload terminate and free all descriptors
+ * @vpath_handle Rx vpath Handle @rxdh Rx Descriptor Handle @state Descriptor
+ * State @userdata Per-adapter Data @reopen vpath open/reopen option
+ */
+/* ARGSUSED */
+void
+vxge_rx_term(vxge_hal_vpath_h vpath_handle, vxge_hal_rxd_h rxdh,
+    void *dtr_priv, vxge_hal_rxd_state_e state, void *userdata,
+    vxge_hal_reopen_e reopen)
+{
+	vxge_vpath_t *vpath = (vxge_vpath_t *) userdata;
+	vxge_rxd_priv_t *rxd_priv = (vxge_rxd_priv_t *) dtr_priv;
+
+	if (state != VXGE_HAL_RXD_STATE_POSTED)
+		return;
+
+	if (rxd_priv != NULL) {
+		bus_dmamap_sync(vpath->dma_tag_rx, rxd_priv->dma_map,
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(vpath->dma_tag_rx, rxd_priv->dma_map);
+		bus_dmamap_destroy(vpath->dma_tag_rx, rxd_priv->dma_map);
+
+		vxge_free_packet(rxd_priv->mbuf_pkt);
+	}
+	/* Free the descriptor */
+	vxge_hal_ring_rxd_free(vpath_handle, rxdh);
+}
+
+/*
+ * vxge_rx_rxd_1b_get
+ * Get descriptors of packet to send up
+ */
+void
+vxge_rx_rxd_1b_get(vxge_vpath_t *vpath, vxge_hal_rxd_h rxdh, void *dtr_priv)
+{
+	vxge_rxd_priv_t *rxd_priv = (vxge_rxd_priv_t *) dtr_priv;
+	mbuf_t mbuf_up = rxd_priv->mbuf_pkt;
+
+	/* Retrieve data from completed descriptor */
+	vxge_hal_ring_rxd_1b_get(vpath->handle, rxdh, &rxd_priv->dma_addr[0],
+	    (u32 *) &rxd_priv->dma_sizes[0]);
+
+	/* Update newly created buffer to be sent up with packet length */
+	mbuf_up->m_len = rxd_priv->dma_sizes[0];
+	mbuf_up->m_pkthdr.len = rxd_priv->dma_sizes[0];
+	mbuf_up->m_next = NULL;
+}
+
+/*
+ * vxge_rx_rxd_1b_set
+ * Allocates new mbufs to be placed into descriptors
+ */
+int
+vxge_rx_rxd_1b_set(vxge_vpath_t *vpath, vxge_hal_rxd_h rxdh, void *dtr_priv)
+{
+	int num_segs, err = 0;
+
+	mbuf_t mbuf_pkt;
+	bus_dmamap_t dma_map;
+	bus_dma_segment_t dma_buffers[1];
+	vxge_rxd_priv_t *rxd_priv = (vxge_rxd_priv_t *) dtr_priv;
+
+	vxge_dev_t *vdev = vpath->vdev;
+
+	mbuf_pkt = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, vdev->rx_mbuf_sz);
+	if (!mbuf_pkt) {
+		err = ENOBUFS;
+		VXGE_DRV_STATS(vpath, rx_no_buf);
+		device_printf(vdev->ndev, "out of memory to allocate mbuf\n");
+		goto _exit0;
+	}
+
+	/* Update mbuf's length, packet length and receive interface */
+	mbuf_pkt->m_len = vdev->rx_mbuf_sz;
+	mbuf_pkt->m_pkthdr.len = vdev->rx_mbuf_sz;
+	mbuf_pkt->m_pkthdr.rcvif = vdev->ifp;
+
+	/* Load DMA map */
+	err = vxge_dma_mbuf_coalesce(vpath->dma_tag_rx, vpath->extra_dma_map,
+	    &mbuf_pkt, dma_buffers, &num_segs);
+	if (err != 0) {
+		VXGE_DRV_STATS(vpath, rx_map_fail);
+		vxge_free_packet(mbuf_pkt);
+		goto _exit0;
+	}
+
+	/* Unload DMA map of mbuf in current descriptor */
+	bus_dmamap_sync(vpath->dma_tag_rx, rxd_priv->dma_map,
+	    BUS_DMASYNC_POSTREAD);
+	bus_dmamap_unload(vpath->dma_tag_rx, rxd_priv->dma_map);
+
+	/* Update descriptor private data */
+	dma_map = rxd_priv->dma_map;
+	rxd_priv->mbuf_pkt = mbuf_pkt;
+	rxd_priv->dma_addr[0] = htole64(dma_buffers->ds_addr);
+	rxd_priv->dma_map = vpath->extra_dma_map;
+	vpath->extra_dma_map = dma_map;
+
+	/* Pre-Read/Write sync */
+	bus_dmamap_sync(vpath->dma_tag_rx, rxd_priv->dma_map,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	/* Set descriptor buffer */
+	vxge_hal_ring_rxd_1b_set(rxdh, rxd_priv->dma_addr[0], vdev->rx_mbuf_sz);
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_link_up
+ * Callback for Link-up indication from HAL
+ */
+/* ARGSUSED */
+void
+vxge_link_up(vxge_hal_device_h devh, void *userdata)
+{
+	int i;
+	vxge_vpath_t *vpath;
+	vxge_hal_device_hw_info_t *hw_info;
+
+	vxge_dev_t *vdev = (vxge_dev_t *) userdata;
+	hw_info = &vdev->config.hw_info;
+
+	ifnet_t ifp = vdev->ifp;
+
+	if (vdev->config.intr_mode == VXGE_HAL_INTR_MODE_MSIX) {
+		for (i = 0; i < vdev->no_of_vpath; i++) {
+			vpath = &(vdev->vpaths[i]);
+			vxge_hal_vpath_tti_ci_set(vpath->handle);
+			vxge_hal_vpath_rti_ci_set(vpath->handle);
+		}
+	}
+
+	if (vdev->is_privilaged && (hw_info->ports > 1)) {
+		vxge_active_port_update(vdev);
+		device_printf(vdev->ndev,
+		    "Active Port : %lld\n", vdev->active_port);
+	}
+
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	if_link_state_change(ifp, LINK_STATE_UP);
+}
+
+/*
+ * vxge_link_down
+ * Callback for Link-down indication from HAL
+ */
+/* ARGSUSED */
+void
+vxge_link_down(vxge_hal_device_h devh, void *userdata)
+{
+	int i;
+	vxge_vpath_t *vpath;
+	vxge_dev_t *vdev = (vxge_dev_t *) userdata;
+
+	ifnet_t ifp = vdev->ifp;
+
+	if (vdev->config.intr_mode == VXGE_HAL_INTR_MODE_MSIX) {
+		for (i = 0; i < vdev->no_of_vpath; i++) {
+			vpath = &(vdev->vpaths[i]);
+			vxge_hal_vpath_tti_ci_reset(vpath->handle);
+			vxge_hal_vpath_rti_ci_reset(vpath->handle);
+		}
+	}
+
+	ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+	if_link_state_change(ifp, LINK_STATE_DOWN);
+}
+
+/*
+ * vxge_reset
+ */
+void
+vxge_reset(vxge_dev_t *vdev)
+{
+	if (!vdev->is_initialized)
+		return;
+
+	VXGE_DRV_LOCK(vdev);
+	vxge_stop_locked(vdev);
+	vxge_init_locked(vdev);
+	VXGE_DRV_UNLOCK(vdev);
+}
+
+/*
+ * vxge_crit_error
+ * Callback for Critical error indication from HAL
+ */
+/* ARGSUSED */
+void
+vxge_crit_error(vxge_hal_device_h devh, void *userdata,
+    vxge_hal_event_e type, u64 serr_data)
+{
+	vxge_dev_t *vdev = (vxge_dev_t *) userdata;
+	ifnet_t ifp = vdev->ifp;
+
+	switch (type) {
+	case VXGE_HAL_EVENT_SERR:
+	case VXGE_HAL_EVENT_KDFCCTL:
+	case VXGE_HAL_EVENT_CRITICAL:
+		vxge_hal_device_intr_disable(vdev->devh);
+		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+		if_link_state_change(ifp, LINK_STATE_DOWN);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * vxge_ifp_setup
+ */
+int
+vxge_ifp_setup(device_t ndev)
+{
+	ifnet_t ifp;
+	int i, j, err = 0;
+
+	vxge_dev_t *vdev = (vxge_dev_t *) device_get_softc(ndev);
+
+	for (i = 0, j = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		if (!bVAL1(vdev->config.hw_info.vpath_mask, i))
+			continue;
+
+		if (j >= vdev->no_of_vpath)
+			break;
+
+		vdev->vpaths[j].vp_id = i;
+		vdev->vpaths[j].vp_index = j;
+		vdev->vpaths[j].vdev = vdev;
+		vdev->vpaths[j].is_configured = TRUE;
+
+		vxge_os_memcpy((u8 *) vdev->vpaths[j].mac_addr,
+		    (u8 *) (vdev->config.hw_info.mac_addrs[i]),
+		    (size_t) ETHER_ADDR_LEN);
+		j++;
+	}
+
+	/* Get interface ifnet structure for this Ether device */
+	ifp = if_alloc(IFT_ETHER);
+	if (ifp == NULL) {
+		device_printf(vdev->ndev,
+		    "memory allocation for ifnet failed\n");
+		err = ENXIO;
+		goto _exit0;
+	}
+	vdev->ifp = ifp;
+
+	/* Initialize interface ifnet structure */
+	if_initname(ifp, device_get_name(ndev), device_get_unit(ndev));
+
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_baudrate = VXGE_BAUDRATE;
+	ifp->if_init = vxge_init;
+	ifp->if_softc = vdev;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = vxge_ioctl;
+	ifp->if_start = vxge_send;
+
+#if __FreeBSD_version >= 800000
+	ifp->if_transmit = vxge_mq_send;
+	ifp->if_qflush = vxge_mq_qflush;
+#endif
+	ifp->if_snd.ifq_drv_maxlen = max(vdev->config.ifq_maxlen, ifqmaxlen);
+	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
+	/* IFQ_SET_READY(&ifp->if_snd); */
+
+	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
+
+	ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
+	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
+	ifp->if_capabilities |= IFCAP_JUMBO_MTU;
+
+	if (vdev->config.tso_enable)
+		vxge_tso_config(vdev);
+
+	if (vdev->config.lro_enable)
+		ifp->if_capabilities |= IFCAP_LRO;
+
+	ifp->if_capenable = ifp->if_capabilities;
+
+	strlcpy(vdev->ndev_name, device_get_nameunit(ndev),
+	    sizeof(vdev->ndev_name));
+
+	/* Attach the interface */
+	ether_ifattach(ifp, vdev->vpaths[0].mac_addr);
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_isr_setup
+ * Register isr functions
+ */
+int
+vxge_isr_setup(vxge_dev_t *vdev)
+{
+	int i, irq_rid, err = 0;
+	vxge_vpath_t *vpath;
+
+	void *isr_func_arg;
+	void (*isr_func_ptr) (void *);
+
+	switch (vdev->config.intr_mode) {
+	case VXGE_HAL_INTR_MODE_IRQLINE:
+		err = bus_setup_intr(vdev->ndev,
+		    vdev->config.isr_info[0].irq_res,
+		    (INTR_TYPE_NET | INTR_MPSAFE),
+		    vxge_isr_filter, vxge_isr_line, vdev,
+		    &vdev->config.isr_info[0].irq_handle);
+		break;
+
+	case VXGE_HAL_INTR_MODE_MSIX:
+		for (i = 0; i < vdev->intr_count; i++) {
+
+			irq_rid = vdev->config.isr_info[i].irq_rid;
+			vpath = &vdev->vpaths[irq_rid / 4];
+
+			if ((irq_rid % 4) == 2) {
+				isr_func_ptr = vxge_isr_msix;
+				isr_func_arg = (void *) vpath;
+			} else if ((irq_rid % 4) == 3) {
+				isr_func_ptr = vxge_isr_msix_alarm;
+				isr_func_arg = (void *) vpath;
+			} else
+				break;
+
+			err = bus_setup_intr(vdev->ndev,
+			    vdev->config.isr_info[i].irq_res,
+			    (INTR_TYPE_NET | INTR_MPSAFE), NULL,
+			    (void *) isr_func_ptr, (void *) isr_func_arg,
+			    &vdev->config.isr_info[i].irq_handle);
+			if (err != 0)
+				break;
+		}
+
+		if (err != 0) {
+			/* Teardown interrupt handler */
+			while (--i > 0)
+				bus_teardown_intr(vdev->ndev,
+				    vdev->config.isr_info[i].irq_res,
+				    vdev->config.isr_info[i].irq_handle);
+		}
+		break;
+	}
+
+	return (err);
+}
+
+/*
+ * vxge_isr_filter
+ * ISR filter function - filter interrupts from other shared devices
+ */
+int
+vxge_isr_filter(void *handle)
+{
+	u64 val64 = 0;
+	vxge_dev_t *vdev = (vxge_dev_t *) handle;
+	__hal_device_t *hldev = (__hal_device_t *) vdev->devh;
+
+	vxge_hal_common_reg_t *common_reg =
+	(vxge_hal_common_reg_t *) (hldev->common_reg);
+
+	val64 = vxge_os_pio_mem_read64(vdev->pdev, (vdev->devh)->regh0,
+	    &common_reg->titan_general_int_status);
+
+	return ((val64) ? FILTER_SCHEDULE_THREAD : FILTER_STRAY);
+}
+
+/*
+ * vxge_isr_line
+ * Interrupt service routine for Line interrupts
+ */
+void
+vxge_isr_line(void *vdev_ptr)
+{
+	vxge_dev_t *vdev = (vxge_dev_t *) vdev_ptr;
+
+	vxge_hal_device_handle_irq(vdev->devh, 0);
+}
+
+void
+vxge_isr_msix(void *vpath_ptr)
+{
+	u32 got_rx = 0;
+	u32 got_tx = 0;
+
+	__hal_virtualpath_t *hal_vpath;
+	vxge_vpath_t *vpath = (vxge_vpath_t *) vpath_ptr;
+	vxge_dev_t *vdev = vpath->vdev;
+	hal_vpath = ((__hal_vpath_handle_t *) vpath->handle)->vpath;
+
+	VXGE_DRV_STATS(vpath, isr_msix);
+	VXGE_HAL_DEVICE_STATS_SW_INFO_TRAFFIC_INTR(vdev->devh);
+
+	vxge_hal_vpath_mf_msix_mask(vpath->handle, vpath->msix_vec);
+
+	/* processing rx */
+	vxge_hal_vpath_poll_rx(vpath->handle, &got_rx);
+
+	/* processing tx */
+	if (hal_vpath->vp_config->fifo.enable) {
+		vxge_intr_coalesce_tx(vpath);
+		vxge_hal_vpath_poll_tx(vpath->handle, &got_tx);
+	}
+
+	vxge_hal_vpath_mf_msix_unmask(vpath->handle, vpath->msix_vec);
+}
+
+void
+vxge_isr_msix_alarm(void *vpath_ptr)
+{
+	int i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_vpath_t *vpath = (vxge_vpath_t *) vpath_ptr;
+	vxge_dev_t *vdev = vpath->vdev;
+
+	VXGE_HAL_DEVICE_STATS_SW_INFO_NOT_TRAFFIC_INTR(vdev->devh);
+
+	/* Process alarms in each vpath */
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+
+		vpath = &(vdev->vpaths[i]);
+		vxge_hal_vpath_mf_msix_mask(vpath->handle,
+		    vpath->msix_vec_alarm);
+		status = vxge_hal_vpath_alarm_process(vpath->handle, 0);
+		if ((status == VXGE_HAL_ERR_EVENT_SLOT_FREEZE) ||
+		    (status == VXGE_HAL_ERR_EVENT_SERR)) {
+			device_printf(vdev->ndev,
+			    "processing alarms urecoverable error %x\n",
+			    status);
+
+			/* Stop the driver */
+			vdev->is_initialized = FALSE;
+			break;
+		}
+		vxge_hal_vpath_mf_msix_unmask(vpath->handle,
+		    vpath->msix_vec_alarm);
+	}
+}
+
+/*
+ * vxge_msix_enable
+ */
+vxge_hal_status_e
+vxge_msix_enable(vxge_dev_t *vdev)
+{
+	int i, first_vp_id, msix_id;
+
+	vxge_vpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	/*
+	 * Unmasking and Setting MSIX vectors before enabling interrupts
+	 * tim[] : 0 - Tx ## 1 - Rx ## 2 - UMQ-DMQ ## 0 - BITMAP
+	 */
+	int tim[4] = {0, 1, 0, 0};
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+
+		vpath = vdev->vpaths + i;
+		first_vp_id = vdev->vpaths[0].vp_id;
+
+		msix_id = vpath->vp_id * VXGE_HAL_VPATH_MSIX_ACTIVE;
+		tim[1] = vpath->msix_vec = msix_id + 1;
+
+		vpath->msix_vec_alarm = first_vp_id *
+		    VXGE_HAL_VPATH_MSIX_ACTIVE + VXGE_HAL_VPATH_MSIX_ALARM_ID;
+
+		status = vxge_hal_vpath_mf_msix_set(vpath->handle,
+		    tim, VXGE_HAL_VPATH_MSIX_ALARM_ID);
+
+		if (status != VXGE_HAL_OK) {
+			device_printf(vdev->ndev,
+			    "failed to set msix vectors to vpath\n");
+			break;
+		}
+
+		vxge_hal_vpath_mf_msix_unmask(vpath->handle, vpath->msix_vec);
+		vxge_hal_vpath_mf_msix_unmask(vpath->handle,
+		    vpath->msix_vec_alarm);
+	}
+
+	return (status);
+}
+
+/*
+ * vxge_media_init
+ * Initializes, adds and sets media
+ */
+void
+vxge_media_init(vxge_dev_t *vdev)
+{
+	ifmedia_init(&vdev->media,
+	    IFM_IMASK, vxge_media_change, vxge_media_status);
+
+	/* Add supported media */
+	ifmedia_add(&vdev->media,
+	    IFM_ETHER | vdev->ifm_optics | IFM_FDX,
+	    0, NULL);
+
+	/* Set media */
+	ifmedia_add(&vdev->media, IFM_ETHER | IFM_AUTO, 0, NULL);
+	ifmedia_set(&vdev->media, IFM_ETHER | IFM_AUTO);
+}
+
+/*
+ * vxge_media_status
+ * Callback  for interface media settings
+ */
+void
+vxge_media_status(ifnet_t ifp, struct ifmediareq *ifmr)
+{
+	vxge_dev_t *vdev = (vxge_dev_t *) ifp->if_softc;
+	vxge_hal_device_t *hldev = vdev->devh;
+
+	ifmr->ifm_status = IFM_AVALID;
+	ifmr->ifm_active = IFM_ETHER;
+
+	/* set link state */
+	if (vxge_hal_device_link_state_get(hldev) == VXGE_HAL_LINK_UP) {
+		ifmr->ifm_status |= IFM_ACTIVE;
+		ifmr->ifm_active |= vdev->ifm_optics | IFM_FDX;
+		if_link_state_change(ifp, LINK_STATE_UP);
+	}
+}
+
+/*
+ * vxge_media_change
+ * Media change driver callback
+ */
+int
+vxge_media_change(ifnet_t ifp)
+{
+	vxge_dev_t *vdev = (vxge_dev_t *) ifp->if_softc;
+	struct ifmedia *ifmediap = &vdev->media;
+
+	return (IFM_TYPE(ifmediap->ifm_media) != IFM_ETHER ? EINVAL : 0);
+}
+
+/*
+ * Allocate PCI resources
+ */
+int
+vxge_alloc_resources(vxge_dev_t *vdev)
+{
+	int err = 0;
+	vxge_pci_info_t *pci_info = NULL;
+	vxge_free_resources_e error_level = VXGE_FREE_NONE;
+
+	device_t ndev = vdev->ndev;
+
+	/* Allocate Buffer for HAL Device Configuration */
+	vdev->device_config = (vxge_hal_device_config_t *)
+	    vxge_mem_alloc(sizeof(vxge_hal_device_config_t));
+
+	if (!vdev->device_config) {
+		err = ENOMEM;
+		error_level = VXGE_DISABLE_PCI_BUSMASTER;
+		device_printf(vdev->ndev,
+		    "failed to allocate memory for device config\n");
+		goto _exit0;
+	}
+
+
+	pci_info = (vxge_pci_info_t *) vxge_mem_alloc(sizeof(vxge_pci_info_t));
+	if (!pci_info) {
+		error_level = VXGE_FREE_DEVICE_CONFIG;
+		err = ENOMEM;
+		device_printf(vdev->ndev,
+		    "failed to allocate memory for pci info\n");
+		goto _exit0;
+	}
+	pci_info->ndev = ndev;
+	vdev->pdev = pci_info;
+
+	err = vxge_alloc_bar_resources(vdev, 0);
+	if (err != 0) {
+		error_level = VXGE_FREE_BAR0;
+		goto _exit0;
+	}
+
+	err = vxge_alloc_bar_resources(vdev, 1);
+	if (err != 0) {
+		error_level = VXGE_FREE_BAR1;
+		goto _exit0;
+	}
+
+	err = vxge_alloc_bar_resources(vdev, 2);
+	if (err != 0)
+		error_level = VXGE_FREE_BAR2;
+
+_exit0:
+	if (error_level)
+		vxge_free_resources(ndev, error_level);
+
+	return (err);
+}
+
+/*
+ * vxge_alloc_bar_resources
+ * Allocates BAR resources
+ */
+int
+vxge_alloc_bar_resources(vxge_dev_t *vdev, int i)
+{
+	int err = 0;
+	int res_id = 0;
+	vxge_pci_info_t *pci_info = vdev->pdev;
+
+	res_id = PCIR_BAR((i == 0) ? 0 : (i * 2));
+
+	pci_info->bar_info[i] =
+	    bus_alloc_resource_any(vdev->ndev,
+	    SYS_RES_MEMORY, &res_id, RF_ACTIVE);
+
+	if (pci_info->bar_info[i] == NULL) {
+		device_printf(vdev->ndev,
+		    "failed to allocate memory for bus resources\n");
+		err = ENOMEM;
+		goto _exit0;
+	}
+
+	pci_info->reg_map[i] =
+	    (vxge_bus_res_t *) vxge_mem_alloc(sizeof(vxge_bus_res_t));
+
+	if (pci_info->reg_map[i] == NULL) {
+		device_printf(vdev->ndev,
+		    "failed to allocate memory bar resources\n");
+		err = ENOMEM;
+		goto _exit0;
+	}
+
+	((vxge_bus_res_t *) (pci_info->reg_map[i]))->bus_space_tag =
+	    rman_get_bustag(pci_info->bar_info[i]);
+
+	((vxge_bus_res_t *) (pci_info->reg_map[i]))->bus_space_handle =
+	    rman_get_bushandle(pci_info->bar_info[i]);
+
+	((vxge_bus_res_t *) (pci_info->reg_map[i]))->bar_start_addr =
+	    pci_info->bar_info[i];
+
+	((vxge_bus_res_t *) (pci_info->reg_map[i]))->bus_res_len =
+	    rman_get_size(pci_info->bar_info[i]);
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_alloc_isr_resources
+ */
+int
+vxge_alloc_isr_resources(vxge_dev_t *vdev)
+{
+	int i, err = 0, irq_rid;
+	int msix_vec_reqd, intr_count, msix_count;
+
+	int intr_mode = VXGE_HAL_INTR_MODE_IRQLINE;
+
+	if (vdev->config.intr_mode == VXGE_HAL_INTR_MODE_MSIX) {
+		/* MSI-X messages supported by device */
+		intr_count = pci_msix_count(vdev->ndev);
+		if (intr_count) {
+
+			msix_vec_reqd = 4 * vdev->no_of_vpath;
+			if (intr_count >= msix_vec_reqd) {
+				intr_count = msix_vec_reqd;
+
+				err = pci_alloc_msix(vdev->ndev, &intr_count);
+				if (err == 0)
+					intr_mode = VXGE_HAL_INTR_MODE_MSIX;
+			}
+
+			if ((err != 0) || (intr_count < msix_vec_reqd)) {
+				device_printf(vdev->ndev, "Unable to allocate "
+				    "msi/x vectors switching to INTA mode\n");
+			}
+		}
+	}
+
+	err = 0;
+	vdev->intr_count = 0;
+	vdev->config.intr_mode = intr_mode;
+
+	switch (vdev->config.intr_mode) {
+	case VXGE_HAL_INTR_MODE_IRQLINE:
+		vdev->config.isr_info[0].irq_rid = 0;
+		vdev->config.isr_info[0].irq_res =
+		    bus_alloc_resource_any(vdev->ndev, SYS_RES_IRQ,
+		    &vdev->config.isr_info[0].irq_rid,
+		    (RF_SHAREABLE | RF_ACTIVE));
+
+		if (vdev->config.isr_info[0].irq_res == NULL) {
+			device_printf(vdev->ndev,
+			    "failed to allocate line interrupt resource\n");
+			err = ENOMEM;
+			goto _exit0;
+		}
+		vdev->intr_count++;
+		break;
+
+	case VXGE_HAL_INTR_MODE_MSIX:
+		msix_count = 0;
+		for (i = 0; i < vdev->no_of_vpath; i++) {
+			irq_rid = i * 4;
+
+			vdev->config.isr_info[msix_count].irq_rid = irq_rid + 2;
+			vdev->config.isr_info[msix_count].irq_res =
+			    bus_alloc_resource_any(vdev->ndev, SYS_RES_IRQ,
+			    &vdev->config.isr_info[msix_count].irq_rid,
+			    (RF_SHAREABLE | RF_ACTIVE));
+
+			if (vdev->config.isr_info[msix_count].irq_res == NULL) {
+				device_printf(vdev->ndev,
+				    "allocating bus resource (rid %d) failed\n",
+				    vdev->config.isr_info[msix_count].irq_rid);
+				err = ENOMEM;
+				goto _exit0;
+			}
+
+			vdev->intr_count++;
+			err = bus_bind_intr(vdev->ndev,
+			    vdev->config.isr_info[msix_count].irq_res,
+			    (i % mp_ncpus));
+			if (err != 0)
+				break;
+
+			msix_count++;
+		}
+
+		vdev->config.isr_info[msix_count].irq_rid = 3;
+		vdev->config.isr_info[msix_count].irq_res =
+		    bus_alloc_resource_any(vdev->ndev, SYS_RES_IRQ,
+		    &vdev->config.isr_info[msix_count].irq_rid,
+		    (RF_SHAREABLE | RF_ACTIVE));
+
+		if (vdev->config.isr_info[msix_count].irq_res == NULL) {
+			device_printf(vdev->ndev,
+			    "allocating bus resource (rid %d) failed\n",
+			    vdev->config.isr_info[msix_count].irq_rid);
+			err = ENOMEM;
+			goto _exit0;
+		}
+
+		vdev->intr_count++;
+		err = bus_bind_intr(vdev->ndev,
+		    vdev->config.isr_info[msix_count].irq_res, (i % mp_ncpus));
+
+		break;
+	}
+
+	vdev->device_config->intr_mode = vdev->config.intr_mode;
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_free_resources
+ * Undo what-all we did during load/attach
+ */
+void
+vxge_free_resources(device_t ndev, vxge_free_resources_e vxge_free_resource)
+{
+	int i;
+	vxge_dev_t *vdev;
+
+	vdev = (vxge_dev_t *) device_get_softc(ndev);
+
+	switch (vxge_free_resource) {
+	case VXGE_FREE_ALL:
+		for (i = 0; i < vdev->intr_count; i++) {
+			bus_teardown_intr(ndev,
+			    vdev->config.isr_info[i].irq_res,
+			    vdev->config.isr_info[i].irq_handle);
+		}
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_INTERFACE:
+		ether_ifdetach(vdev->ifp);
+		bus_generic_detach(ndev);
+		if_free(vdev->ifp);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_MEDIA:
+		ifmedia_removeall(&vdev->media);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_MUTEX:
+		vxge_mutex_destroy(vdev);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_VPATH:
+		vxge_mem_free(vdev->vpaths,
+		    vdev->no_of_vpath * sizeof(vxge_vpath_t));
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_TERMINATE_DEVICE:
+		if (vdev->devh != NULL) {
+			vxge_hal_device_private_set(vdev->devh, 0);
+			vxge_hal_device_terminate(vdev->devh);
+		}
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_ISR_RESOURCE:
+		vxge_free_isr_resources(vdev);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_BAR2:
+		vxge_free_bar_resources(vdev, 2);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_BAR1:
+		vxge_free_bar_resources(vdev, 1);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_BAR0:
+		vxge_free_bar_resources(vdev, 0);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_PCI_INFO:
+		vxge_mem_free(vdev->pdev, sizeof(vxge_pci_info_t));
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_DEVICE_CONFIG:
+		vxge_mem_free(vdev->device_config,
+		    sizeof(vxge_hal_device_config_t));
+		/* FALLTHROUGH */
+
+	case VXGE_DISABLE_PCI_BUSMASTER:
+		pci_disable_busmaster(ndev);
+		/* FALLTHROUGH */
+
+	case VXGE_FREE_TERMINATE_DRIVER:
+		if (vxge_dev_ref_count) {
+			--vxge_dev_ref_count;
+			if (0 == vxge_dev_ref_count)
+				vxge_hal_driver_terminate();
+		}
+		/* FALLTHROUGH */
+
+	default:
+	case VXGE_FREE_NONE:
+		break;
+		/* NOTREACHED */
+	}
+}
+
+void
+vxge_free_isr_resources(vxge_dev_t *vdev)
+{
+	int i;
+
+	switch (vdev->config.intr_mode) {
+	case VXGE_HAL_INTR_MODE_IRQLINE:
+		if (vdev->config.isr_info[0].irq_res) {
+			bus_release_resource(vdev->ndev, SYS_RES_IRQ,
+			    vdev->config.isr_info[0].irq_rid,
+			    vdev->config.isr_info[0].irq_res);
+
+			vdev->config.isr_info[0].irq_res = NULL;
+		}
+		break;
+
+	case VXGE_HAL_INTR_MODE_MSIX:
+		for (i = 0; i < vdev->intr_count; i++) {
+			if (vdev->config.isr_info[i].irq_res) {
+				bus_release_resource(vdev->ndev, SYS_RES_IRQ,
+				    vdev->config.isr_info[i].irq_rid,
+				    vdev->config.isr_info[i].irq_res);
+
+				vdev->config.isr_info[i].irq_res = NULL;
+			}
+		}
+
+		if (vdev->intr_count)
+			pci_release_msi(vdev->ndev);
+
+		break;
+	}
+}
+
+void
+vxge_free_bar_resources(vxge_dev_t *vdev, int i)
+{
+	int res_id = 0;
+	vxge_pci_info_t *pci_info = vdev->pdev;
+
+	res_id = PCIR_BAR((i == 0) ? 0 : (i * 2));
+
+	if (pci_info->bar_info[i])
+		bus_release_resource(vdev->ndev, SYS_RES_MEMORY,
+		    res_id, pci_info->bar_info[i]);
+
+	vxge_mem_free(pci_info->reg_map[i], sizeof(vxge_bus_res_t));
+}
+
+/*
+ * vxge_init_mutex
+ * Initializes mutexes used in driver
+ */
+void
+vxge_mutex_init(vxge_dev_t *vdev)
+{
+	int i;
+
+	snprintf(vdev->mtx_drv_name, sizeof(vdev->mtx_drv_name),
+	    "%s_drv", vdev->ndev_name);
+
+	mtx_init(&vdev->mtx_drv, vdev->mtx_drv_name,
+	    MTX_NETWORK_LOCK, MTX_DEF);
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		snprintf(vdev->vpaths[i].mtx_tx_name,
+		    sizeof(vdev->vpaths[i].mtx_tx_name), "%s_tx_%d",
+		    vdev->ndev_name, i);
+
+		mtx_init(&vdev->vpaths[i].mtx_tx,
+		    vdev->vpaths[i].mtx_tx_name, NULL, MTX_DEF);
+	}
+}
+
+/*
+ * vxge_mutex_destroy
+ * Destroys mutexes used in driver
+ */
+void
+vxge_mutex_destroy(vxge_dev_t *vdev)
+{
+	int i;
+
+	for (i = 0; i < vdev->no_of_vpath; i++)
+		VXGE_TX_LOCK_DESTROY(&(vdev->vpaths[i]));
+
+	VXGE_DRV_LOCK_DESTROY(vdev);
+}
+
+/*
+ * vxge_rth_config
+ */
+vxge_hal_status_e
+vxge_rth_config(vxge_dev_t *vdev)
+{
+	int i;
+	vxge_hal_vpath_h vpath_handle;
+	vxge_hal_rth_hash_types_t hash_types;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	u8 mtable[256] = {0};
+
+	/* Filling matable with bucket-to-vpath mapping */
+	vdev->config.rth_bkt_sz = VXGE_DEFAULT_RTH_BUCKET_SIZE;
+
+	for (i = 0; i < (1 << vdev->config.rth_bkt_sz); i++)
+		mtable[i] = i % vdev->no_of_vpath;
+
+	/* Fill RTH hash types */
+	hash_types.hash_type_tcpipv4_en = VXGE_HAL_RING_HASH_TYPE_TCP_IPV4;
+	hash_types.hash_type_tcpipv6_en = VXGE_HAL_RING_HASH_TYPE_TCP_IPV6;
+	hash_types.hash_type_tcpipv6ex_en = VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX;
+	hash_types.hash_type_ipv4_en = VXGE_HAL_RING_HASH_TYPE_IPV4;
+	hash_types.hash_type_ipv6_en = VXGE_HAL_RING_HASH_TYPE_IPV6;
+	hash_types.hash_type_ipv6ex_en = VXGE_HAL_RING_HASH_TYPE_IPV6_EX;
+
+	/* set indirection table, bucket-to-vpath mapping */
+	status = vxge_hal_vpath_rts_rth_itable_set(vdev->vpath_handles,
+	    vdev->no_of_vpath, mtable,
+	    ((u32) (1 << vdev->config.rth_bkt_sz)));
+
+	if (status != VXGE_HAL_OK) {
+		device_printf(vdev->ndev, "rth configuration failed\n");
+		goto _exit0;
+	}
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath_handle = vxge_vpath_handle_get(vdev, i);
+		if (!vpath_handle)
+			continue;
+
+		status = vxge_hal_vpath_rts_rth_set(vpath_handle,
+		    RTH_ALG_JENKINS,
+		    &hash_types, vdev->config.rth_bkt_sz, TRUE);
+		if (status != VXGE_HAL_OK) {
+			device_printf(vdev->ndev,
+			    "rth configuration failed for vpath (%d)\n",
+			    vdev->vpaths[i].vp_id);
+			break;
+		}
+	}
+
+_exit0:
+	return (status);
+}
+
+/*
+ * vxge_vpath_config
+ * Sets HAL parameter values from kenv
+ */
+void
+vxge_vpath_config(vxge_dev_t *vdev)
+{
+	int i;
+	u32 no_of_vpath = 0;
+	vxge_hal_vp_config_t *vp_config;
+	vxge_hal_device_config_t *device_config = vdev->device_config;
+
+	device_config->debug_level = VXGE_TRACE;
+	device_config->debug_mask = VXGE_COMPONENT_ALL;
+	device_config->device_poll_millis = VXGE_DEFAULT_DEVICE_POLL_MILLIS;
+
+	vdev->config.no_of_vpath =
+	    min(vdev->config.no_of_vpath, vdev->max_supported_vpath);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		vp_config = &(device_config->vp_config[i]);
+		vp_config->fifo.enable = VXGE_HAL_FIFO_DISABLE;
+		vp_config->ring.enable = VXGE_HAL_RING_DISABLE;
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		if (no_of_vpath >= vdev->config.no_of_vpath)
+			break;
+
+		if (!bVAL1(vdev->config.hw_info.vpath_mask, i))
+			continue;
+
+		no_of_vpath++;
+		vp_config = &(device_config->vp_config[i]);
+		vp_config->mtu = VXGE_HAL_DEFAULT_MTU;
+		vp_config->ring.enable = VXGE_HAL_RING_ENABLE;
+		vp_config->ring.post_mode = VXGE_HAL_RING_POST_MODE_DOORBELL;
+		vp_config->ring.buffer_mode = VXGE_HAL_RING_RXD_BUFFER_MODE_1;
+		vp_config->ring.ring_length =
+		    vxge_ring_length_get(VXGE_HAL_RING_RXD_BUFFER_MODE_1);
+		vp_config->ring.scatter_mode = VXGE_HAL_RING_SCATTER_MODE_A;
+		vp_config->rpa_all_vid_en = VXGE_DEFAULT_ALL_VID_ENABLE;
+		vp_config->rpa_strip_vlan_tag = VXGE_DEFAULT_STRIP_VLAN_TAG;
+		vp_config->rpa_ucast_all_addr_en =
+		    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE;
+
+		vp_config->rti.intr_enable = VXGE_HAL_TIM_INTR_ENABLE;
+		vp_config->rti.txfrm_cnt_en = VXGE_HAL_TXFRM_CNT_EN_ENABLE;
+		vp_config->rti.util_sel =
+		    VXGE_HAL_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL;
+
+		vp_config->rti.uec_a = VXGE_DEFAULT_RTI_RX_UFC_A;
+		vp_config->rti.uec_b = VXGE_DEFAULT_RTI_RX_UFC_B;
+		vp_config->rti.uec_c = VXGE_DEFAULT_RTI_RX_UFC_C;
+		vp_config->rti.uec_d = VXGE_DEFAULT_RTI_RX_UFC_D;
+
+		vp_config->rti.urange_a = VXGE_DEFAULT_RTI_RX_URANGE_A;
+		vp_config->rti.urange_b = VXGE_DEFAULT_RTI_RX_URANGE_B;
+		vp_config->rti.urange_c = VXGE_DEFAULT_RTI_RX_URANGE_C;
+
+		vp_config->rti.timer_ac_en = VXGE_HAL_TIM_TIMER_AC_ENABLE;
+		vp_config->rti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
+
+		vp_config->rti.btimer_val =
+		    (VXGE_DEFAULT_RTI_BTIMER_VAL * 1000) / 272;
+		vp_config->rti.rtimer_val =
+		    (VXGE_DEFAULT_RTI_RTIMER_VAL * 1000) / 272;
+		vp_config->rti.ltimer_val =
+		    (VXGE_DEFAULT_RTI_LTIMER_VAL * 1000) / 272;
+
+		if ((no_of_vpath > 1) && (VXGE_DEFAULT_CONFIG_MQ_ENABLE == 0))
+			continue;
+
+		vp_config->fifo.enable = VXGE_HAL_FIFO_ENABLE;
+		vp_config->fifo.max_aligned_frags =
+		    VXGE_DEFAULT_FIFO_ALIGNED_FRAGS;
+
+		vp_config->tti.intr_enable = VXGE_HAL_TIM_INTR_ENABLE;
+		vp_config->tti.txfrm_cnt_en = VXGE_HAL_TXFRM_CNT_EN_ENABLE;
+		vp_config->tti.util_sel =
+		    VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL;
+
+		vp_config->tti.uec_a = VXGE_DEFAULT_TTI_TX_UFC_A;
+		vp_config->tti.uec_b = VXGE_DEFAULT_TTI_TX_UFC_B;
+		vp_config->tti.uec_c = VXGE_DEFAULT_TTI_TX_UFC_C;
+		vp_config->tti.uec_d = VXGE_DEFAULT_TTI_TX_UFC_D;
+
+		vp_config->tti.urange_a = VXGE_DEFAULT_TTI_TX_URANGE_A;
+		vp_config->tti.urange_b = VXGE_DEFAULT_TTI_TX_URANGE_B;
+		vp_config->tti.urange_c = VXGE_DEFAULT_TTI_TX_URANGE_C;
+
+		vp_config->tti.timer_ac_en = VXGE_HAL_TIM_TIMER_AC_ENABLE;
+		vp_config->tti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
+
+		vp_config->tti.btimer_val =
+		    (VXGE_DEFAULT_TTI_BTIMER_VAL * 1000) / 272;
+		vp_config->tti.rtimer_val =
+		    (VXGE_DEFAULT_TTI_RTIMER_VAL * 1000) / 272;
+		vp_config->tti.ltimer_val =
+		    (VXGE_DEFAULT_TTI_LTIMER_VAL * 1000) / 272;
+	}
+
+	vdev->no_of_vpath = no_of_vpath;
+
+	if (vdev->no_of_vpath == 1)
+		vdev->config.tx_steering = 0;
+
+	if (vdev->config.rth_enable && (vdev->no_of_vpath > 1)) {
+		device_config->rth_en = VXGE_HAL_RTH_ENABLE;
+		device_config->rth_it_type = VXGE_HAL_RTH_IT_TYPE_MULTI_IT;
+	}
+
+	vdev->config.rth_enable = device_config->rth_en;
+}
+
+/*
+ * vxge_vpath_cb_fn
+ * Virtual path Callback function
+ */
+/* ARGSUSED */
+static vxge_hal_status_e
+vxge_vpath_cb_fn(vxge_hal_client_h client_handle, vxge_hal_up_msg_h msgh,
+    vxge_hal_message_type_e msg_type, vxge_hal_obj_id_t obj_id,
+    vxge_hal_result_e result, vxge_hal_opaque_handle_t *opaque_handle)
+{
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_vpath_open
+ */
+int
+vxge_vpath_open(vxge_dev_t *vdev)
+{
+	int i, err = EINVAL;
+	u64 func_id;
+
+	vxge_vpath_t *vpath;
+	vxge_hal_vpath_attr_t vpath_attr;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	struct lro_ctrl *lro = NULL;
+
+	bzero(&vpath_attr, sizeof(vxge_hal_vpath_attr_t));
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+
+		vpath = &(vdev->vpaths[i]);
+		lro = &vpath->lro;
+
+		/* Vpath vpath_attr: FIFO */
+		vpath_attr.vp_id = vpath->vp_id;
+		vpath_attr.fifo_attr.callback = vxge_tx_compl;
+		vpath_attr.fifo_attr.txdl_init = vxge_tx_replenish;
+		vpath_attr.fifo_attr.txdl_term = vxge_tx_term;
+		vpath_attr.fifo_attr.userdata = vpath;
+		vpath_attr.fifo_attr.per_txdl_space = sizeof(vxge_txdl_priv_t);
+
+		/* Vpath vpath_attr: Ring */
+		vpath_attr.ring_attr.callback = vxge_rx_compl;
+		vpath_attr.ring_attr.rxd_init = vxge_rx_replenish;
+		vpath_attr.ring_attr.rxd_term = vxge_rx_term;
+		vpath_attr.ring_attr.userdata = vpath;
+		vpath_attr.ring_attr.per_rxd_space = sizeof(vxge_rxd_priv_t);
+
+		err = vxge_dma_tags_create(vpath);
+		if (err != 0) {
+			device_printf(vdev->ndev,
+			    "failed to create dma tags\n");
+			break;
+		}
+#if __FreeBSD_version >= 800000
+		vpath->br = buf_ring_alloc(VXGE_DEFAULT_BR_SIZE, M_DEVBUF,
+		    M_WAITOK, &vpath->mtx_tx);
+		if (vpath->br == NULL) {
+			err = ENOMEM;
+			break;
+		}
+#endif
+		status = vxge_hal_vpath_open(vdev->devh, &vpath_attr,
+		    (vxge_hal_vpath_callback_f) vxge_vpath_cb_fn,
+		    NULL, &vpath->handle);
+		if (status != VXGE_HAL_OK) {
+			device_printf(vdev->ndev,
+			    "failed to open vpath (%d)\n", vpath->vp_id);
+			err = EPERM;
+			break;
+		}
+		vpath->is_open = TRUE;
+		vdev->vpath_handles[i] = vpath->handle;
+
+		vpath->tx_ticks = ticks;
+		vpath->rx_ticks = ticks;
+
+		vpath->tti_rtimer_val = VXGE_DEFAULT_TTI_RTIMER_VAL;
+		vpath->tti_rtimer_val = VXGE_DEFAULT_TTI_RTIMER_VAL;
+
+		vpath->tx_intr_coalesce = vdev->config.intr_coalesce;
+		vpath->rx_intr_coalesce = vdev->config.intr_coalesce;
+
+		func_id = vdev->config.hw_info.func_id;
+
+		if (vdev->config.low_latency &&
+		    (vdev->config.bw_info[func_id].priority ==
+			VXGE_DEFAULT_VPATH_PRIORITY_HIGH)) {
+			vpath->tx_intr_coalesce = 0;
+		}
+
+		if (vdev->ifp->if_capenable & IFCAP_LRO) {
+			err = tcp_lro_init(lro);
+			if (err != 0) {
+				device_printf(vdev->ndev,
+				    "LRO Initialization failed!\n");
+				break;
+			}
+			vpath->lro_enable = TRUE;
+			lro->ifp = vdev->ifp;
+		}
+	}
+
+	return (err);
+}
+
+void
+vxge_tso_config(vxge_dev_t *vdev)
+{
+	u32 func_id, priority;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vdev->ifp->if_capabilities |= IFCAP_TSO4;
+
+	status = vxge_bw_priority_get(vdev, NULL);
+	if (status == VXGE_HAL_OK) {
+
+		func_id = vdev->config.hw_info.func_id;
+		priority = vdev->config.bw_info[func_id].priority;
+
+		if (priority != VXGE_DEFAULT_VPATH_PRIORITY_HIGH)
+			vdev->ifp->if_capabilities &= ~IFCAP_TSO4;
+	}
+
+#if __FreeBSD_version >= 800000
+	if (vdev->ifp->if_capabilities & IFCAP_TSO4)
+		vdev->ifp->if_capabilities |= IFCAP_VLAN_HWTSO;
+#endif
+
+}
+
+vxge_hal_status_e
+vxge_bw_priority_get(vxge_dev_t *vdev, vxge_bw_info_t *bw_info)
+{
+	u32 priority, bandwidth;
+	u32 vpath_count;
+
+	u64 func_id, func_mode, vpath_list[VXGE_HAL_MAX_VIRTUAL_PATHS];
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	func_id = vdev->config.hw_info.func_id;
+	if (bw_info) {
+		func_id = bw_info->func_id;
+		func_mode = vdev->config.hw_info.function_mode;
+		if ((is_single_func(func_mode)) && (func_id > 0))
+			return (VXGE_HAL_FAIL);
+	}
+
+	if (vdev->hw_fw_version >= VXGE_FW_VERSION(1, 8, 0)) {
+
+		status = vxge_hal_vf_rx_bw_get(vdev->devh,
+		    func_id, &bandwidth, &priority);
+
+	} else {
+
+		status = vxge_hal_get_vpath_list(vdev->devh,
+		    func_id, vpath_list, &vpath_count);
+
+		if (status == VXGE_HAL_OK) {
+			status = vxge_hal_bw_priority_get(vdev->devh,
+			    vpath_list[0], &bandwidth, &priority);
+		}
+	}
+
+	if (status == VXGE_HAL_OK) {
+		if (bw_info) {
+			bw_info->priority = priority;
+			bw_info->bandwidth = bandwidth;
+		} else {
+			vdev->config.bw_info[func_id].priority = priority;
+			vdev->config.bw_info[func_id].bandwidth = bandwidth;
+		}
+	}
+
+	return (status);
+}
+
+/*
+ * close vpaths
+ */
+void
+vxge_vpath_close(vxge_dev_t *vdev)
+{
+	int i;
+	vxge_vpath_t *vpath;
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+
+		vpath = &(vdev->vpaths[i]);
+		if (vpath->handle)
+			vxge_hal_vpath_close(vpath->handle);
+
+#if __FreeBSD_version >= 800000
+		if (vpath->br != NULL)
+			buf_ring_free(vpath->br, M_DEVBUF);
+#endif
+		/* Free LRO memory */
+		if (vpath->lro_enable)
+			tcp_lro_free(&vpath->lro);
+
+		if (vpath->dma_tag_rx) {
+			bus_dmamap_destroy(vpath->dma_tag_rx,
+			    vpath->extra_dma_map);
+			bus_dma_tag_destroy(vpath->dma_tag_rx);
+		}
+
+		if (vpath->dma_tag_tx)
+			bus_dma_tag_destroy(vpath->dma_tag_tx);
+
+		vpath->handle = NULL;
+		vpath->is_open = FALSE;
+	}
+}
+
+/*
+ * reset vpaths
+ */
+void
+vxge_vpath_reset(vxge_dev_t *vdev)
+{
+	int i;
+	vxge_hal_vpath_h vpath_handle;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath_handle = vxge_vpath_handle_get(vdev, i);
+		if (!vpath_handle)
+			continue;
+
+		status = vxge_hal_vpath_reset(vpath_handle);
+		if (status != VXGE_HAL_OK)
+			device_printf(vdev->ndev,
+			    "failed to reset vpath :%d\n", i);
+	}
+}
+
+static inline int
+vxge_vpath_get(vxge_dev_t *vdev, mbuf_t mhead)
+{
+	struct tcphdr *th = NULL;
+	struct udphdr *uh = NULL;
+	struct ip *ip = NULL;
+	struct ip6_hdr *ip6 = NULL;
+	struct ether_vlan_header *eth = NULL;
+	void *ulp = NULL;
+
+	int ehdrlen, iphlen = 0;
+	u8 ipproto = 0;
+	u16 etype, src_port, dst_port;
+	u16 queue_len, counter = 0;
+
+	src_port = dst_port = 0;
+	queue_len = vdev->no_of_vpath;
+
+	eth = mtod(mhead, struct ether_vlan_header *);
+	if (eth->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
+		etype = ntohs(eth->evl_proto);
+		ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
+	} else {
+		etype = ntohs(eth->evl_encap_proto);
+		ehdrlen = ETHER_HDR_LEN;
+	}
+
+	switch (etype) {
+	case ETHERTYPE_IP:
+		ip = (struct ip *) (mhead->m_data + ehdrlen);
+		iphlen = ip->ip_hl << 2;
+		ipproto = ip->ip_p;
+		th = (struct tcphdr *) ((caddr_t)ip + iphlen);
+		uh = (struct udphdr *) ((caddr_t)ip + iphlen);
+		break;
+
+	case ETHERTYPE_IPV6:
+		ip6 = (struct ip6_hdr *) (mhead->m_data + ehdrlen);
+		iphlen = sizeof(struct ip6_hdr);
+		ipproto = ip6->ip6_nxt;
+
+		ulp = mtod(mhead, char *) + iphlen;
+		th = ((struct tcphdr *) (ulp));
+		uh = ((struct udphdr *) (ulp));
+		break;
+
+	default:
+		break;
+	}
+
+	switch (ipproto) {
+	case IPPROTO_TCP:
+		src_port = th->th_sport;
+		dst_port = th->th_dport;
+		break;
+
+	case IPPROTO_UDP:
+		src_port = uh->uh_sport;
+		dst_port = uh->uh_dport;
+		break;
+
+	default:
+		break;
+	}
+
+	counter = (ntohs(src_port) + ntohs(dst_port)) &
+	    vpath_selector[queue_len - 1];
+
+	if (counter >= queue_len)
+		counter = queue_len - 1;
+
+	return (counter);
+}
+
+static inline vxge_hal_vpath_h
+vxge_vpath_handle_get(vxge_dev_t *vdev, int i)
+{
+	return (vdev->vpaths[i].is_open ? vdev->vpaths[i].handle : NULL);
+}
+
+int
+vxge_firmware_verify(vxge_dev_t *vdev)
+{
+	int err = 0;
+	u64 active_config;
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	if (vdev->fw_upgrade) {
+		status = vxge_firmware_upgrade(vdev);
+		if (status == VXGE_HAL_OK) {
+			err = ENXIO;
+			goto _exit0;
+		}
+	}
+
+	if ((vdev->config.function_mode != VXGE_DEFAULT_CONFIG_VALUE) &&
+	    (vdev->config.hw_info.function_mode !=
+	    (u64) vdev->config.function_mode)) {
+
+		status = vxge_func_mode_set(vdev);
+		if (status == VXGE_HAL_OK)
+			err = ENXIO;
+	}
+
+	/* l2_switch configuration */
+	active_config = VXGE_DEFAULT_CONFIG_VALUE;
+	status = vxge_hal_get_active_config(vdev->devh,
+	    VXGE_HAL_XMAC_NWIF_ActConfig_L2SwitchEnabled,
+	    &active_config);
+
+	if (status == VXGE_HAL_OK) {
+		vdev->l2_switch = active_config;
+		if (vdev->config.l2_switch != VXGE_DEFAULT_CONFIG_VALUE) {
+			if (vdev->config.l2_switch != active_config) {
+				status = vxge_l2switch_mode_set(vdev);
+				if (status == VXGE_HAL_OK)
+					err = ENXIO;
+			}
+		}
+	}
+
+	if (vdev->config.hw_info.ports == VXGE_DUAL_PORT_MODE) {
+		if (vxge_port_mode_update(vdev) == ENXIO)
+			err = ENXIO;
+	}
+
+_exit0:
+	if (err == ENXIO)
+		device_printf(vdev->ndev, "PLEASE POWER CYCLE THE SYSTEM\n");
+
+	return (err);
+}
+
+vxge_hal_status_e
+vxge_firmware_upgrade(vxge_dev_t *vdev)
+{
+	u8 *fw_buffer;
+	u32 fw_size;
+	vxge_hal_device_hw_info_t *hw_info;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	hw_info = &vdev->config.hw_info;
+
+	fw_size = sizeof(VXGE_FW_ARRAY_NAME);
+	fw_buffer = (u8 *) VXGE_FW_ARRAY_NAME;
+
+	device_printf(vdev->ndev, "Current firmware version : %s (%s)\n",
+	    hw_info->fw_version.version, hw_info->fw_date.date);
+
+	device_printf(vdev->ndev, "Upgrading firmware to %d.%d.%d\n",
+	    VXGE_MIN_FW_MAJOR_VERSION, VXGE_MIN_FW_MINOR_VERSION,
+	    VXGE_MIN_FW_BUILD_NUMBER);
+
+	/* Call HAL API to upgrade firmware */
+	status = vxge_hal_mrpcim_fw_upgrade(vdev->pdev,
+	    (pci_reg_h) vdev->pdev->reg_map[0],
+	    (u8 *) vdev->pdev->bar_info[0],
+	    fw_buffer, fw_size);
+
+	device_printf(vdev->ndev, "firmware upgrade %s\n",
+	    (status == VXGE_HAL_OK) ? "successful" : "failed");
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_func_mode_set(vxge_dev_t *vdev)
+{
+	u64 active_config;
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	status = vxge_hal_mrpcim_pcie_func_mode_set(vdev->devh,
+	    vdev->config.function_mode);
+	device_printf(vdev->ndev,
+	    "function mode change %s\n",
+	    (status == VXGE_HAL_OK) ? "successful" : "failed");
+
+	if (status == VXGE_HAL_OK) {
+		vxge_hal_set_fw_api(vdev->devh, 0ULL,
+		    VXGE_HAL_API_FUNC_MODE_COMMIT,
+		    0, 0ULL, 0ULL);
+
+		vxge_hal_get_active_config(vdev->devh,
+		    VXGE_HAL_XMAC_NWIF_ActConfig_NWPortMode,
+		    &active_config);
+
+		/*
+		 * If in MF + DP mode
+		 * if user changes to SF, change port_mode to single port mode
+		 */
+		if (((is_multi_func(vdev->config.hw_info.function_mode)) &&
+		    is_single_func(vdev->config.function_mode)) &&
+		    (active_config == VXGE_HAL_DP_NP_MODE_DUAL_PORT)) {
+			vdev->config.port_mode =
+			    VXGE_HAL_DP_NP_MODE_SINGLE_PORT;
+
+			status = vxge_port_mode_set(vdev);
+		}
+	}
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_port_mode_set(vxge_dev_t *vdev)
+{
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	status = vxge_hal_set_port_mode(vdev->devh, vdev->config.port_mode);
+	device_printf(vdev->ndev,
+	    "port mode change %s\n",
+	    (status == VXGE_HAL_OK) ? "successful" : "failed");
+
+	if (status == VXGE_HAL_OK) {
+		vxge_hal_set_fw_api(vdev->devh, 0ULL,
+		    VXGE_HAL_API_FUNC_MODE_COMMIT,
+		    0, 0ULL, 0ULL);
+
+		/* Configure vpath_mapping for active-active mode only */
+		if (vdev->config.port_mode == VXGE_HAL_DP_NP_MODE_DUAL_PORT) {
+
+			status = vxge_hal_config_vpath_map(vdev->devh,
+			    VXGE_DUAL_PORT_MAP);
+
+			device_printf(vdev->ndev, "dual port map change %s\n",
+			    (status == VXGE_HAL_OK) ? "successful" : "failed");
+		}
+	}
+	return (status);
+}
+
+int
+vxge_port_mode_update(vxge_dev_t *vdev)
+{
+	int err = 0;
+	u64 active_config;
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	if ((vdev->config.port_mode == VXGE_HAL_DP_NP_MODE_DUAL_PORT) &&
+	    is_single_func(vdev->config.hw_info.function_mode)) {
+
+		device_printf(vdev->ndev,
+		    "Adapter in SF mode, dual port mode is not allowed\n");
+		err = EPERM;
+		goto _exit0;
+	}
+
+	active_config = VXGE_DEFAULT_CONFIG_VALUE;
+	status = vxge_hal_get_active_config(vdev->devh,
+	    VXGE_HAL_XMAC_NWIF_ActConfig_NWPortMode,
+	    &active_config);
+	if (status != VXGE_HAL_OK) {
+		err = EINVAL;
+		goto _exit0;
+	}
+
+	vdev->port_mode = active_config;
+	if (vdev->config.port_mode != VXGE_DEFAULT_CONFIG_VALUE) {
+		if (vdev->config.port_mode != vdev->port_mode) {
+			status = vxge_port_mode_set(vdev);
+			if (status != VXGE_HAL_OK) {
+				err = EINVAL;
+				goto _exit0;
+			}
+			err = ENXIO;
+			vdev->port_mode  = vdev->config.port_mode;
+		}
+	}
+
+	active_config = VXGE_DEFAULT_CONFIG_VALUE;
+	status = vxge_hal_get_active_config(vdev->devh,
+	    VXGE_HAL_XMAC_NWIF_ActConfig_BehaviourOnFail,
+	    &active_config);
+	if (status != VXGE_HAL_OK) {
+		err = EINVAL;
+		goto _exit0;
+	}
+
+	vdev->port_failure = active_config;
+
+	/*
+	 * active/active mode : set to NoMove
+	 * active/passive mode: set to Failover-Failback
+	 */
+	if (vdev->port_mode == VXGE_HAL_DP_NP_MODE_DUAL_PORT)
+		vdev->config.port_failure =
+		    VXGE_HAL_XMAC_NWIF_OnFailure_NoMove;
+
+	else if (vdev->port_mode == VXGE_HAL_DP_NP_MODE_ACTIVE_PASSIVE)
+		vdev->config.port_failure =
+		    VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore;
+
+	if ((vdev->port_mode != VXGE_HAL_DP_NP_MODE_SINGLE_PORT) &&
+	    (vdev->config.port_failure != vdev->port_failure)) {
+		status = vxge_port_behavior_on_failure_set(vdev);
+		if (status == VXGE_HAL_OK)
+			err = ENXIO;
+	}
+
+_exit0:
+	return (err);
+}
+
+vxge_hal_status_e
+vxge_port_mode_get(vxge_dev_t *vdev, vxge_port_info_t *port_info)
+{
+	int err = 0;
+	u64 active_config;
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	active_config = VXGE_DEFAULT_CONFIG_VALUE;
+	status = vxge_hal_get_active_config(vdev->devh,
+	    VXGE_HAL_XMAC_NWIF_ActConfig_NWPortMode,
+	    &active_config);
+
+	if (status != VXGE_HAL_OK) {
+		err = ENXIO;
+		goto _exit0;
+	}
+
+	port_info->port_mode = active_config;
+
+	active_config = VXGE_DEFAULT_CONFIG_VALUE;
+	status = vxge_hal_get_active_config(vdev->devh,
+	    VXGE_HAL_XMAC_NWIF_ActConfig_BehaviourOnFail,
+	    &active_config);
+	if (status != VXGE_HAL_OK) {
+		err = ENXIO;
+		goto _exit0;
+	}
+
+	port_info->port_failure = active_config;
+
+_exit0:
+	return (err);
+}
+
+vxge_hal_status_e
+vxge_port_behavior_on_failure_set(vxge_dev_t *vdev)
+{
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	status = vxge_hal_set_behavior_on_failure(vdev->devh,
+	    vdev->config.port_failure);
+
+	device_printf(vdev->ndev,
+	    "port behaviour on failure change %s\n",
+	    (status == VXGE_HAL_OK) ? "successful" : "failed");
+
+	if (status == VXGE_HAL_OK)
+		vxge_hal_set_fw_api(vdev->devh, 0ULL,
+		    VXGE_HAL_API_FUNC_MODE_COMMIT,
+		    0, 0ULL, 0ULL);
+
+	return (status);
+}
+
+void
+vxge_active_port_update(vxge_dev_t *vdev)
+{
+	u64 active_config;
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	active_config = VXGE_DEFAULT_CONFIG_VALUE;
+	status = vxge_hal_get_active_config(vdev->devh,
+	    VXGE_HAL_XMAC_NWIF_ActConfig_ActivePort,
+	    &active_config);
+
+	if (status == VXGE_HAL_OK)
+		vdev->active_port = active_config;
+}
+
+vxge_hal_status_e
+vxge_l2switch_mode_set(vxge_dev_t *vdev)
+{
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	status = vxge_hal_set_l2switch_mode(vdev->devh,
+	    vdev->config.l2_switch);
+
+	device_printf(vdev->ndev, "L2 switch %s\n",
+	    (status == VXGE_HAL_OK) ?
+	    (vdev->config.l2_switch) ? "enable" : "disable" :
+	    "change failed");
+
+	if (status == VXGE_HAL_OK)
+		vxge_hal_set_fw_api(vdev->devh, 0ULL,
+		    VXGE_HAL_API_FUNC_MODE_COMMIT,
+		    0, 0ULL, 0ULL);
+
+	return (status);
+}
+
+/*
+ * vxge_promisc_set
+ * Enable Promiscuous Mode
+ */
+void
+vxge_promisc_set(vxge_dev_t *vdev)
+{
+	int i;
+	ifnet_t ifp;
+	vxge_hal_vpath_h vpath_handle;
+
+	if (!vdev->is_initialized)
+		return;
+
+	ifp = vdev->ifp;
+
+	if ((ifp->if_flags & IFF_ALLMULTI) && (!vdev->all_multi_flag)) {
+		for (i = 0; i < vdev->no_of_vpath; i++) {
+			vpath_handle = vxge_vpath_handle_get(vdev, i);
+			if (!vpath_handle)
+				continue;
+
+			vxge_hal_vpath_mcast_enable(vpath_handle);
+			vdev->all_multi_flag = 1;
+		}
+
+	} else if (!(ifp->if_flags & IFF_ALLMULTI) && (vdev->all_multi_flag)) {
+		for (i = 0; i < vdev->no_of_vpath; i++) {
+			vpath_handle = vxge_vpath_handle_get(vdev, i);
+			if (!vpath_handle)
+				continue;
+
+			vxge_hal_vpath_mcast_disable(vpath_handle);
+			vdev->all_multi_flag = 0;
+		}
+	}
+	for (i = 0; i < vdev->no_of_vpath; i++) {
+		vpath_handle = vxge_vpath_handle_get(vdev, i);
+		if (!vpath_handle)
+			continue;
+
+		if (ifp->if_flags & IFF_PROMISC)
+			vxge_hal_vpath_promisc_enable(vpath_handle);
+		else
+			vxge_hal_vpath_promisc_disable(vpath_handle);
+	}
+}
+
+/*
+ * vxge_change_mtu
+ * Change interface MTU to a requested valid size
+ */
+int
+vxge_change_mtu(vxge_dev_t *vdev, unsigned long new_mtu)
+{
+	int err = EINVAL;
+
+	if ((new_mtu < VXGE_HAL_MIN_MTU) || (new_mtu > VXGE_HAL_MAX_MTU))
+		goto _exit0;
+
+	(vdev->ifp)->if_mtu = new_mtu;
+	device_printf(vdev->ndev, "MTU changed to %ld\n", (vdev->ifp)->if_mtu);
+
+	if (vdev->is_initialized) {
+		if_down(vdev->ifp);
+		vxge_reset(vdev);
+		if_up(vdev->ifp);
+	}
+	err = 0;
+
+_exit0:
+	return (err);
+}
+
+/*
+ * Creates DMA tags for both Tx and Rx
+ */
+int
+vxge_dma_tags_create(vxge_vpath_t *vpath)
+{
+	int err = 0;
+	bus_size_t max_size, boundary;
+	vxge_dev_t *vdev = vpath->vdev;
+	ifnet_t ifp = vdev->ifp;
+
+	max_size = ifp->if_mtu +
+	    VXGE_HAL_MAC_HEADER_MAX_SIZE +
+	    VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN;
+
+	VXGE_BUFFER_ALIGN(max_size, 128)
+	if (max_size <= MCLBYTES)
+		vdev->rx_mbuf_sz = MCLBYTES;
+	else
+		vdev->rx_mbuf_sz =
+		    (max_size > MJUMPAGESIZE) ? MJUM9BYTES : MJUMPAGESIZE;
+
+	boundary = (max_size > PAGE_SIZE) ? 0 : PAGE_SIZE;
+
+	/* DMA tag for Tx */
+	err = bus_dma_tag_create(
+	    bus_get_dma_tag(vdev->ndev),
+	    1,
+	    PAGE_SIZE,
+	    BUS_SPACE_MAXADDR,
+	    BUS_SPACE_MAXADDR,
+	    NULL,
+	    NULL,
+	    VXGE_TSO_SIZE,
+	    VXGE_MAX_SEGS,
+	    PAGE_SIZE,
+	    BUS_DMA_ALLOCNOW,
+	    NULL,
+	    NULL,
+	    &(vpath->dma_tag_tx));
+	if (err != 0)
+		goto _exit0;
+
+	/* DMA tag for Rx */
+	err = bus_dma_tag_create(
+	    bus_get_dma_tag(vdev->ndev),
+	    1,
+	    boundary,
+	    BUS_SPACE_MAXADDR,
+	    BUS_SPACE_MAXADDR,
+	    NULL,
+	    NULL,
+	    vdev->rx_mbuf_sz,
+	    1,
+	    vdev->rx_mbuf_sz,
+	    BUS_DMA_ALLOCNOW,
+	    NULL,
+	    NULL,
+	    &(vpath->dma_tag_rx));
+	if (err != 0)
+		goto _exit1;
+
+	/* Create DMA map for this descriptor */
+	err = bus_dmamap_create(vpath->dma_tag_rx, BUS_DMA_NOWAIT,
+	    &vpath->extra_dma_map);
+	if (err == 0)
+		goto _exit0;
+
+	bus_dma_tag_destroy(vpath->dma_tag_rx);
+
+_exit1:
+	bus_dma_tag_destroy(vpath->dma_tag_tx);
+
+_exit0:
+	return (err);
+}
+
+static inline int
+vxge_dma_mbuf_coalesce(bus_dma_tag_t dma_tag_tx, bus_dmamap_t dma_map,
+    mbuf_t * m_headp, bus_dma_segment_t * dma_buffers,
+    int *num_segs)
+{
+	int err = 0;
+	mbuf_t mbuf_pkt = NULL;
+
+retry:
+	err = bus_dmamap_load_mbuf_sg(dma_tag_tx, dma_map, *m_headp,
+	    dma_buffers, num_segs, BUS_DMA_NOWAIT);
+	if (err == EFBIG) {
+		/* try to defrag, too many segments */
+		mbuf_pkt = m_defrag(*m_headp, M_DONTWAIT);
+		if (mbuf_pkt == NULL) {
+			err = ENOBUFS;
+			goto _exit0;
+		}
+		*m_headp = mbuf_pkt;
+		goto retry;
+	}
+
+_exit0:
+	return (err);
+}
+
+int
+vxge_device_hw_info_get(vxge_dev_t *vdev)
+{
+	int i, err = ENXIO;
+	u64 vpath_mask = 0;
+	u32 max_supported_vpath = 0;
+	u32 fw_ver_maj_min;
+	vxge_firmware_upgrade_e fw_option;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_device_hw_info_t *hw_info;
+
+	status = vxge_hal_device_hw_info_get(vdev->pdev,
+	    (pci_reg_h) vdev->pdev->reg_map[0],
+	    (u8 *) vdev->pdev->bar_info[0],
+	    &vdev->config.hw_info);
+
+	if (status != VXGE_HAL_OK)
+		goto _exit0;
+
+	hw_info = &vdev->config.hw_info;
+
+	vpath_mask = hw_info->vpath_mask;
+	if (vpath_mask == 0) {
+		device_printf(vdev->ndev, "No vpaths available in device\n");
+		goto _exit0;
+	}
+
+	fw_option = vdev->config.fw_option;
+
+	/* Check how many vpaths are available */
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		if (!((vpath_mask) & mBIT(i)))
+			continue;
+		max_supported_vpath++;
+	}
+
+	vdev->max_supported_vpath = max_supported_vpath;
+	status = vxge_hal_device_is_privileged(hw_info->host_type,
+	    hw_info->func_id);
+	vdev->is_privilaged = (status == VXGE_HAL_OK) ? TRUE : FALSE;
+
+	vdev->hw_fw_version = VXGE_FW_VERSION(
+	    hw_info->fw_version.major,
+	    hw_info->fw_version.minor,
+	    hw_info->fw_version.build);
+
+	fw_ver_maj_min =
+	    VXGE_FW_MAJ_MIN_VERSION(hw_info->fw_version.major,
+	    hw_info->fw_version.minor);
+
+	if ((fw_option >= VXGE_FW_UPGRADE_FORCE) ||
+	    (vdev->hw_fw_version != VXGE_DRV_FW_VERSION)) {
+
+		/* For fw_ver 1.8.1 and above ignore build number. */
+		if ((fw_option == VXGE_FW_UPGRADE_ALL) &&
+		    ((vdev->hw_fw_version >= VXGE_FW_VERSION(1, 8, 1)) &&
+		    (fw_ver_maj_min == VXGE_DRV_FW_MAJ_MIN_VERSION))) {
+			goto _exit1;
+		}
+
+		if (vdev->hw_fw_version < VXGE_BASE_FW_VERSION) {
+			device_printf(vdev->ndev,
+			    "Upgrade driver through vxge_update, "
+			    "Unable to load the driver.\n");
+			goto _exit0;
+		}
+		vdev->fw_upgrade = TRUE;
+	}
+
+_exit1:
+	err = 0;
+
+_exit0:
+	return (err);
+}
+
+/*
+ * vxge_device_hw_info_print
+ * Print device and driver information
+ */
+void
+vxge_device_hw_info_print(vxge_dev_t *vdev)
+{
+	u32 i;
+	device_t ndev;
+	struct sysctl_ctx_list *ctx;
+	struct sysctl_oid_list *children;
+	char pmd_type[2][VXGE_PMD_INFO_LEN];
+
+	vxge_hal_device_t *hldev;
+	vxge_hal_device_hw_info_t *hw_info;
+	vxge_hal_device_pmd_info_t *pmd_port;
+
+	hldev = vdev->devh;
+	ndev = vdev->ndev;
+
+	ctx = device_get_sysctl_ctx(ndev);
+	children = SYSCTL_CHILDREN(device_get_sysctl_tree(ndev));
+
+	hw_info = &(vdev->config.hw_info);
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_DRV_VERSION],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_DRV_VERSION]),
+	    "%d.%d.%d.%d", XGELL_VERSION_MAJOR, XGELL_VERSION_MINOR,
+	    XGELL_VERSION_FIX, XGELL_VERSION_BUILD);
+
+	/* Print PCI-e bus type/speed/width info */
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_PCIE_INFO],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_PCIE_INFO]),
+	    "x%d", hldev->link_width);
+
+	if (hldev->link_width <= VXGE_HAL_PCI_E_LINK_WIDTH_X4)
+		device_printf(ndev, "For optimal performance a x8 "
+		    "PCI-Express slot is required.\n");
+
+	vxge_null_terminate((char *) hw_info->serial_number,
+	    sizeof(hw_info->serial_number));
+
+	vxge_null_terminate((char *) hw_info->part_number,
+	    sizeof(hw_info->part_number));
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_SERIAL_NO],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_SERIAL_NO]),
+	    "%s", hw_info->serial_number);
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_PART_NO],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_PART_NO]),
+	    "%s", hw_info->part_number);
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_FW_VERSION],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_FW_VERSION]),
+	    "%s", hw_info->fw_version.version);
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_FW_DATE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_FW_DATE]),
+	    "%s", hw_info->fw_date.date);
+
+	pmd_port = &(hw_info->pmd_port0);
+	for (i = 0; i < hw_info->ports; i++) {
+
+		vxge_pmd_port_type_get(vdev, pmd_port->type,
+		    pmd_type[i], sizeof(pmd_type[i]));
+
+		strncpy(vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_0 + i],
+		    "vendor=??, sn=??, pn=??, type=??",
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_0 + i]));
+
+		vxge_null_terminate(pmd_port->vendor, sizeof(pmd_port->vendor));
+		if (strlen(pmd_port->vendor) == 0) {
+			pmd_port = &(hw_info->pmd_port1);
+			continue;
+		}
+
+		vxge_null_terminate(pmd_port->ser_num,
+		    sizeof(pmd_port->ser_num));
+
+		vxge_null_terminate(pmd_port->part_num,
+		    sizeof(pmd_port->part_num));
+
+		snprintf(vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_0 + i],
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_0 + i]),
+		    "vendor=%s, sn=%s, pn=%s, type=%s",
+		    pmd_port->vendor, pmd_port->ser_num,
+		    pmd_port->part_num, pmd_type[i]);
+
+		pmd_port = &(hw_info->pmd_port1);
+	}
+
+	switch (hw_info->function_mode) {
+	case VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17:
+		snprintf(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE],
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE]),
+		    "%s %d %s", "Single Function - 1 function(s)",
+		    vdev->max_supported_vpath, "VPath(s)/function");
+		break;
+
+	case VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8:
+		snprintf(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE],
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE]),
+		    "%s %d %s", "Multi Function - 2 function(s)",
+		    vdev->max_supported_vpath, "VPath(s)/function");
+		break;
+
+	case VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4:
+		snprintf(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE],
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE]),
+		    "%s %d %s", "Multi Function - 4 function(s)",
+		    vdev->max_supported_vpath, "VPath(s)/function");
+		break;
+
+	case VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2:
+		snprintf(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE],
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE]),
+		    "%s %d %s", "Multi Function - 8 function(s)",
+		    vdev->max_supported_vpath, "VPath(s)/function");
+		break;
+
+	case VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2:
+		snprintf(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE],
+		    sizeof(vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE]),
+		    "%s %d %s", "Multi Function (DirectIO) - 8 function(s)",
+		    vdev->max_supported_vpath, "VPath(s)/function");
+		break;
+	}
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_INTR_MODE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_INTR_MODE]),
+	    "%s", ((vdev->config.intr_mode == VXGE_HAL_INTR_MODE_MSIX) ?
+	    "MSI-X" : "INTA"));
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_VPATH_COUNT],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_VPATH_COUNT]),
+	    "%d", vdev->no_of_vpath);
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_MTU_SIZE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_MTU_SIZE]),
+	    "%lu", vdev->ifp->if_mtu);
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_LRO_MODE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_LRO_MODE]),
+	    "%s", ((vdev->config.lro_enable) ? "Enabled" : "Disabled"));
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_RTH_MODE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_RTH_MODE]),
+	    "%s", ((vdev->config.rth_enable) ? "Enabled" : "Disabled"));
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_TSO_MODE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_TSO_MODE]),
+	    "%s", ((vdev->ifp->if_capenable & IFCAP_TSO4) ?
+	    "Enabled" : "Disabled"));
+
+	snprintf(vdev->config.nic_attr[VXGE_PRINT_ADAPTER_TYPE],
+	    sizeof(vdev->config.nic_attr[VXGE_PRINT_ADAPTER_TYPE]),
+	    "%s", ((hw_info->ports == 1) ? "Single Port" : "Dual Port"));
+
+	if (vdev->is_privilaged) {
+
+		if (hw_info->ports > 1) {
+
+			snprintf(vdev->config.nic_attr[VXGE_PRINT_PORT_MODE],
+			    sizeof(vdev->config.nic_attr[VXGE_PRINT_PORT_MODE]),
+			    "%s", vxge_port_mode[vdev->port_mode]);
+
+			if (vdev->port_mode != VXGE_HAL_DP_NP_MODE_SINGLE_PORT)
+				snprintf(vdev->config.nic_attr[VXGE_PRINT_PORT_FAILURE],
+				    sizeof(vdev->config.nic_attr[VXGE_PRINT_PORT_FAILURE]),
+				    "%s", vxge_port_failure[vdev->port_failure]);
+
+			vxge_active_port_update(vdev);
+			snprintf(vdev->config.nic_attr[VXGE_PRINT_ACTIVE_PORT],
+			    sizeof(vdev->config.nic_attr[VXGE_PRINT_ACTIVE_PORT]),
+			    "%lld", vdev->active_port);
+		}
+
+		if (!is_single_func(hw_info->function_mode)) {
+			snprintf(vdev->config.nic_attr[VXGE_PRINT_L2SWITCH_MODE],
+			    sizeof(vdev->config.nic_attr[VXGE_PRINT_L2SWITCH_MODE]),
+			    "%s", ((vdev->l2_switch) ? "Enabled" : "Disabled"));
+		}
+	}
+
+	device_printf(ndev, "Driver version\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_DRV_VERSION]);
+
+	device_printf(ndev, "Serial number\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_SERIAL_NO]);
+
+	device_printf(ndev, "Part number\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_PART_NO]);
+
+	device_printf(ndev, "Firmware version\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_FW_VERSION]);
+
+	device_printf(ndev, "Firmware date\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_FW_DATE]);
+
+	device_printf(ndev, "Link width\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_PCIE_INFO]);
+
+	if (vdev->is_privilaged) {
+		device_printf(ndev, "Function mode\t: %s\n",
+		    vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE]);
+	}
+
+	device_printf(ndev, "Interrupt type\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_INTR_MODE]);
+
+	device_printf(ndev, "VPath(s) opened\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_VPATH_COUNT]);
+
+	device_printf(ndev, "Adapter Type\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_ADAPTER_TYPE]);
+
+	device_printf(ndev, "PMD Port 0\t: %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_0]);
+
+	if (hw_info->ports > 1) {
+		device_printf(ndev, "PMD Port 1\t: %s\n",
+		    vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_1]);
+
+		if (vdev->is_privilaged) {
+			device_printf(ndev, "Port Mode\t: %s\n",
+			    vdev->config.nic_attr[VXGE_PRINT_PORT_MODE]);
+
+			if (vdev->port_mode != VXGE_HAL_DP_NP_MODE_SINGLE_PORT)
+				device_printf(ndev, "Port Failure\t: %s\n",
+				    vdev->config.nic_attr[VXGE_PRINT_PORT_FAILURE]);
+
+			device_printf(vdev->ndev, "Active Port\t: %s\n",
+			    vdev->config.nic_attr[VXGE_PRINT_ACTIVE_PORT]);
+		}
+	}
+
+	if (vdev->is_privilaged && !is_single_func(hw_info->function_mode)) {
+		device_printf(vdev->ndev, "L2 Switch\t: %s\n",
+		    vdev->config.nic_attr[VXGE_PRINT_L2SWITCH_MODE]);
+	}
+
+	device_printf(ndev, "MTU is %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_MTU_SIZE]);
+
+	device_printf(ndev, "LRO %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_LRO_MODE]);
+
+	device_printf(ndev, "RTH %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_RTH_MODE]);
+
+	device_printf(ndev, "TSO %s\n",
+	    vdev->config.nic_attr[VXGE_PRINT_TSO_MODE]);
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Driver version", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_DRV_VERSION],
+	    0, "Driver version");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Serial number", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_SERIAL_NO],
+	    0, "Serial number");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Part number", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_PART_NO],
+	    0, "Part number");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Firmware version", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_FW_VERSION],
+	    0, "Firmware version");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Firmware date", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_FW_DATE],
+	    0, "Firmware date");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Link width", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_PCIE_INFO],
+	    0, "Link width");
+
+	if (vdev->is_privilaged) {
+		SYSCTL_ADD_STRING(ctx, children,
+		    OID_AUTO, "Function mode", CTLFLAG_RD,
+		    &vdev->config.nic_attr[VXGE_PRINT_FUNC_MODE],
+		    0, "Function mode");
+	}
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Interrupt type", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_INTR_MODE],
+	    0, "Interrupt type");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "VPath(s) opened", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_VPATH_COUNT],
+	    0, "VPath(s) opened");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "Adapter Type", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_ADAPTER_TYPE],
+	    0, "Adapter Type");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "pmd port 0", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_0],
+	    0, "pmd port");
+
+	if (hw_info->ports > 1) {
+
+		SYSCTL_ADD_STRING(ctx, children,
+		    OID_AUTO, "pmd port 1", CTLFLAG_RD,
+		    &vdev->config.nic_attr[VXGE_PRINT_PMD_PORTS_1],
+		    0, "pmd port");
+
+		if (vdev->is_privilaged) {
+			SYSCTL_ADD_STRING(ctx, children,
+			    OID_AUTO, "Port Mode", CTLFLAG_RD,
+			    &vdev->config.nic_attr[VXGE_PRINT_PORT_MODE],
+			    0, "Port Mode");
+
+			if (vdev->port_mode != VXGE_HAL_DP_NP_MODE_SINGLE_PORT)
+				SYSCTL_ADD_STRING(ctx, children,
+				    OID_AUTO, "Port Failure", CTLFLAG_RD,
+				    &vdev->config.nic_attr[VXGE_PRINT_PORT_FAILURE],
+				    0, "Port Failure");
+
+			SYSCTL_ADD_STRING(ctx, children,
+			    OID_AUTO, "L2 Switch", CTLFLAG_RD,
+			    &vdev->config.nic_attr[VXGE_PRINT_L2SWITCH_MODE],
+			    0, "L2 Switch");
+		}
+	}
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "LRO mode", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_LRO_MODE],
+	    0, "LRO mode");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "RTH mode", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_RTH_MODE],
+	    0, "RTH mode");
+
+	SYSCTL_ADD_STRING(ctx, children,
+	    OID_AUTO, "TSO mode", CTLFLAG_RD,
+	    &vdev->config.nic_attr[VXGE_PRINT_TSO_MODE],
+	    0, "TSO mode");
+}
+
+void
+vxge_pmd_port_type_get(vxge_dev_t *vdev, u32 port_type,
+    char *ifm_name, u8 ifm_len)
+{
+
+	vdev->ifm_optics = IFM_UNKNOWN;
+
+	switch (port_type) {
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_SR:
+		vdev->ifm_optics = IFM_10G_SR;
+		strlcpy(ifm_name, "10GbE SR", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_LR:
+		vdev->ifm_optics = IFM_10G_LR;
+		strlcpy(ifm_name, "10GbE LR", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_LRM:
+		vdev->ifm_optics = IFM_10G_LRM;
+		strlcpy(ifm_name, "10GbE LRM", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_DIRECT:
+		vdev->ifm_optics = IFM_10G_TWINAX;
+		strlcpy(ifm_name, "10GbE DA (Direct Attached)", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_CX4:
+		vdev->ifm_optics = IFM_10G_CX4;
+		strlcpy(ifm_name, "10GbE CX4", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_BASE_T:
+#if __FreeBSD_version >= 800000
+		vdev->ifm_optics = IFM_10G_T;
+#endif
+		strlcpy(ifm_name, "10GbE baseT", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_10G_OTHER:
+		strlcpy(ifm_name, "10GbE Other", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_SX:
+		vdev->ifm_optics = IFM_1000_SX;
+		strlcpy(ifm_name, "1GbE SX", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_LX:
+		vdev->ifm_optics = IFM_1000_LX;
+		strlcpy(ifm_name, "1GbE LX", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_CX:
+		vdev->ifm_optics = IFM_1000_CX;
+		strlcpy(ifm_name, "1GbE CX", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_BASE_T:
+		vdev->ifm_optics = IFM_1000_T;
+		strlcpy(ifm_name, "1GbE baseT", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_DIRECT:
+		strlcpy(ifm_name, "1GbE DA (Direct Attached)",
+		    ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_CX4:
+		strlcpy(ifm_name, "1GbE CX4", ifm_len);
+		break;
+
+	case VXGE_HAL_DEVICE_PMD_TYPE_1G_OTHER:
+		strlcpy(ifm_name, "1GbE Other", ifm_len);
+		break;
+
+	default:
+	case VXGE_HAL_DEVICE_PMD_TYPE_UNKNOWN:
+		strlcpy(ifm_name, "UNSUP", ifm_len);
+		break;
+	}
+}
+
+u32
+vxge_ring_length_get(u32 buffer_mode)
+{
+	return (VXGE_DEFAULT_RING_BLOCK *
+	    vxge_hal_ring_rxds_per_block_get(buffer_mode));
+}
+
+/*
+ * Removes trailing spaces padded
+ * and NULL terminates strings
+ */
+static inline void
+vxge_null_terminate(char *str, size_t len)
+{
+	len--;
+	while (*str && (*str != ' ') && (len != 0))
+		++str;
+
+	--len;
+	if (*str)
+		*str = '\0';
+}
+
+/*
+ * vxge_ioctl
+ * Callback to control the device
+ */
+int
+vxge_ioctl(ifnet_t ifp, u_long command, caddr_t data)
+{
+	int mask, err = 0;
+	vxge_dev_t *vdev = (vxge_dev_t *) ifp->if_softc;
+	struct ifreq *ifr = (struct ifreq *) data;
+
+	if (!vdev->is_active)
+		return (EBUSY);
+
+	switch (command) {
+		/* Set/Get ifnet address */
+	case SIOCSIFADDR:
+	case SIOCGIFADDR:
+		ether_ioctl(ifp, command, data);
+		break;
+
+		/* Set Interface MTU */
+	case SIOCSIFMTU:
+		err = vxge_change_mtu(vdev, (unsigned long)ifr->ifr_mtu);
+		break;
+
+		/* Set Interface Flags */
+	case SIOCSIFFLAGS:
+		VXGE_DRV_LOCK(vdev);
+		if (ifp->if_flags & IFF_UP) {
+			if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) {
+				if ((ifp->if_flags ^ vdev->if_flags) &
+				    (IFF_PROMISC | IFF_ALLMULTI))
+					vxge_promisc_set(vdev);
+			} else {
+				vxge_init_locked(vdev);
+			}
+		} else {
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+				vxge_stop_locked(vdev);
+		}
+		vdev->if_flags = ifp->if_flags;
+		VXGE_DRV_UNLOCK(vdev);
+		break;
+
+		/* Add/delete multicast address */
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		break;
+
+		/* Get/Set Interface Media */
+	case SIOCSIFMEDIA:
+	case SIOCGIFMEDIA:
+		err = ifmedia_ioctl(ifp, ifr, &vdev->media, command);
+		break;
+
+		/* Set Capabilities */
+	case SIOCSIFCAP:
+		VXGE_DRV_LOCK(vdev);
+		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+
+		if (mask & IFCAP_TXCSUM) {
+			ifp->if_capenable ^= IFCAP_TXCSUM;
+			ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
+
+			if ((ifp->if_capenable & IFCAP_TSO) &&
+			    !(ifp->if_capenable & IFCAP_TXCSUM)) {
+
+				ifp->if_capenable &= ~IFCAP_TSO;
+				ifp->if_hwassist &= ~CSUM_TSO;
+				if_printf(ifp, "TSO Disabled\n");
+			}
+		}
+		if (mask & IFCAP_RXCSUM)
+			ifp->if_capenable ^= IFCAP_RXCSUM;
+
+		if (mask & IFCAP_TSO4) {
+			ifp->if_capenable ^= IFCAP_TSO4;
+
+			if (ifp->if_capenable & IFCAP_TSO) {
+				if (ifp->if_capenable & IFCAP_TXCSUM) {
+					ifp->if_hwassist |= CSUM_TSO;
+					if_printf(ifp, "TSO Enabled\n");
+				} else {
+					ifp->if_capenable &= ~IFCAP_TSO;
+					ifp->if_hwassist &= ~CSUM_TSO;
+					if_printf(ifp,
+					    "Enable tx checksum offload \
+					     first.\n");
+					err = EAGAIN;
+				}
+			} else {
+				ifp->if_hwassist &= ~CSUM_TSO;
+				if_printf(ifp, "TSO Disabled\n");
+			}
+		}
+		if (mask & IFCAP_LRO)
+			ifp->if_capenable ^= IFCAP_LRO;
+
+		if (mask & IFCAP_VLAN_HWTAGGING)
+			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
+
+		if (mask & IFCAP_VLAN_MTU)
+			ifp->if_capenable ^= IFCAP_VLAN_MTU;
+
+		if (mask & IFCAP_VLAN_HWCSUM)
+			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
+
+#if __FreeBSD_version >= 800000
+		if (mask & IFCAP_VLAN_HWTSO)
+			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
+#endif
+
+#if defined(VLAN_CAPABILITIES)
+		VLAN_CAPABILITIES(ifp);
+#endif
+
+		VXGE_DRV_UNLOCK(vdev);
+		break;
+
+	case SIOCGPRIVATE_0:
+		VXGE_DRV_LOCK(vdev);
+		err = vxge_ioctl_stats(vdev, ifr);
+		VXGE_DRV_UNLOCK(vdev);
+		break;
+
+	case SIOCGPRIVATE_1:
+		VXGE_DRV_LOCK(vdev);
+		err = vxge_ioctl_regs(vdev, ifr);
+		VXGE_DRV_UNLOCK(vdev);
+		break;
+
+	default:
+		err = ether_ioctl(ifp, command, data);
+		break;
+	}
+
+	return (err);
+}
+
+/*
+ * vxge_ioctl_regs
+ * IOCTL to get registers
+ */
+int
+vxge_ioctl_regs(vxge_dev_t *vdev, struct ifreq *ifr)
+{
+	u64 value = 0x0;
+	u32 vp_id = 0;
+	u32 offset, reqd_size = 0;
+	int i, err = EINVAL;
+
+	char *command = (char *) ifr->ifr_data;
+	void *reg_info = (void *) ifr->ifr_data;
+
+	vxge_vpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_mgmt_reg_type_e regs_type;
+
+	switch (*command) {
+	case vxge_hal_mgmt_reg_type_pcicfgmgmt:
+		if (vdev->is_privilaged) {
+			reqd_size = sizeof(vxge_hal_pcicfgmgmt_reg_t);
+			regs_type = vxge_hal_mgmt_reg_type_pcicfgmgmt;
+		}
+		break;
+
+	case vxge_hal_mgmt_reg_type_mrpcim:
+		if (vdev->is_privilaged) {
+			reqd_size = sizeof(vxge_hal_mrpcim_reg_t);
+			regs_type = vxge_hal_mgmt_reg_type_mrpcim;
+		}
+		break;
+
+	case vxge_hal_mgmt_reg_type_srpcim:
+		if (vdev->is_privilaged) {
+			reqd_size = sizeof(vxge_hal_srpcim_reg_t);
+			regs_type = vxge_hal_mgmt_reg_type_srpcim;
+		}
+		break;
+
+	case vxge_hal_mgmt_reg_type_memrepair:
+		if (vdev->is_privilaged) {
+			/* reqd_size = sizeof(vxge_hal_memrepair_reg_t); */
+			regs_type = vxge_hal_mgmt_reg_type_memrepair;
+		}
+		break;
+
+	case vxge_hal_mgmt_reg_type_legacy:
+		reqd_size = sizeof(vxge_hal_legacy_reg_t);
+		regs_type = vxge_hal_mgmt_reg_type_legacy;
+		break;
+
+	case vxge_hal_mgmt_reg_type_toc:
+		reqd_size = sizeof(vxge_hal_toc_reg_t);
+		regs_type = vxge_hal_mgmt_reg_type_toc;
+		break;
+
+	case vxge_hal_mgmt_reg_type_common:
+		reqd_size = sizeof(vxge_hal_common_reg_t);
+		regs_type = vxge_hal_mgmt_reg_type_common;
+		break;
+
+	case vxge_hal_mgmt_reg_type_vpmgmt:
+		reqd_size = sizeof(vxge_hal_vpmgmt_reg_t);
+		regs_type = vxge_hal_mgmt_reg_type_vpmgmt;
+		vpath = &(vdev->vpaths[*((u32 *) reg_info + 1)]);
+		vp_id = vpath->vp_id;
+		break;
+
+	case vxge_hal_mgmt_reg_type_vpath:
+		reqd_size = sizeof(vxge_hal_vpath_reg_t);
+		regs_type = vxge_hal_mgmt_reg_type_vpath;
+		vpath = &(vdev->vpaths[*((u32 *) reg_info + 1)]);
+		vp_id = vpath->vp_id;
+		break;
+
+	case VXGE_GET_VPATH_COUNT:
+		*((u32 *) reg_info) = vdev->no_of_vpath;
+		err = 0;
+		break;
+
+	default:
+		reqd_size = 0;
+		break;
+	}
+
+	if (reqd_size) {
+		for (i = 0, offset = 0; offset < reqd_size;
+		    i++, offset += 0x0008) {
+			value = 0x0;
+			status = vxge_hal_mgmt_reg_read(vdev->devh, regs_type,
+			    vp_id, offset, &value);
+
+			err = (status != VXGE_HAL_OK) ? EINVAL : 0;
+			if (err == EINVAL)
+				break;
+
+			*((u64 *) ((u64 *) reg_info + i)) = value;
+		}
+	}
+	return (err);
+}
+
+/*
+ * vxge_ioctl_stats
+ * IOCTL to get statistics
+ */
+int
+vxge_ioctl_stats(vxge_dev_t *vdev, struct ifreq *ifr)
+{
+	int i, retsize, err = EINVAL;
+	u32 bufsize;
+
+	vxge_vpath_t *vpath;
+	vxge_bw_info_t *bw_info;
+	vxge_port_info_t *port_info;
+	vxge_drv_stats_t *drv_stat;
+
+	char *buffer = NULL;
+	char *command = (char *) ifr->ifr_data;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	switch (*command) {
+	case VXGE_GET_PCI_CONF:
+		bufsize = VXGE_STATS_BUFFER_SIZE;
+		buffer = (char *) vxge_mem_alloc(bufsize);
+		if (buffer != NULL) {
+			status = vxge_hal_aux_pci_config_read(vdev->devh,
+			    bufsize, buffer, &retsize);
+			if (status == VXGE_HAL_OK)
+				err = copyout(buffer, ifr->ifr_data, retsize);
+			else
+				device_printf(vdev->ndev,
+				    "failed pciconfig statistics query\n");
+
+			vxge_mem_free(buffer, bufsize);
+		}
+		break;
+
+	case VXGE_GET_MRPCIM_STATS:
+		if (!vdev->is_privilaged)
+			break;
+
+		bufsize = VXGE_STATS_BUFFER_SIZE;
+		buffer = (char *) vxge_mem_alloc(bufsize);
+		if (buffer != NULL) {
+			status = vxge_hal_aux_stats_mrpcim_read(vdev->devh,
+			    bufsize, buffer, &retsize);
+			if (status == VXGE_HAL_OK)
+				err = copyout(buffer, ifr->ifr_data, retsize);
+			else
+				device_printf(vdev->ndev,
+				    "failed mrpcim statistics query\n");
+
+			vxge_mem_free(buffer, bufsize);
+		}
+		break;
+
+	case VXGE_GET_DEVICE_STATS:
+		bufsize = VXGE_STATS_BUFFER_SIZE;
+		buffer = (char *) vxge_mem_alloc(bufsize);
+		if (buffer != NULL) {
+			status = vxge_hal_aux_stats_device_read(vdev->devh,
+			    bufsize, buffer, &retsize);
+			if (status == VXGE_HAL_OK)
+				err = copyout(buffer, ifr->ifr_data, retsize);
+			else
+				device_printf(vdev->ndev,
+				    "failed device statistics query\n");
+
+			vxge_mem_free(buffer, bufsize);
+		}
+		break;
+
+	case VXGE_GET_DEVICE_HWINFO:
+		bufsize = sizeof(vxge_device_hw_info_t);
+		buffer = (char *) vxge_mem_alloc(bufsize);
+		if (buffer != NULL) {
+			vxge_os_memcpy(
+			    &(((vxge_device_hw_info_t *) buffer)->hw_info),
+			    &vdev->config.hw_info,
+			    sizeof(vxge_hal_device_hw_info_t));
+
+			((vxge_device_hw_info_t *) buffer)->port_mode =
+			    vdev->port_mode;
+
+			((vxge_device_hw_info_t *) buffer)->port_failure =
+			    vdev->port_failure;
+
+			err = copyout(buffer, ifr->ifr_data, bufsize);
+			if (err != 0)
+				device_printf(vdev->ndev,
+				    "failed device hardware info query\n");
+
+			vxge_mem_free(buffer, bufsize);
+		}
+		break;
+
+	case VXGE_GET_DRIVER_STATS:
+		bufsize = sizeof(vxge_drv_stats_t) * vdev->no_of_vpath;
+		drv_stat = (vxge_drv_stats_t *) vxge_mem_alloc(bufsize);
+		if (drv_stat != NULL) {
+			for (i = 0; i < vdev->no_of_vpath; i++) {
+				vpath = &(vdev->vpaths[i]);
+
+				vpath->driver_stats.rx_lro_queued +=
+				    vpath->lro.lro_queued;
+
+				vpath->driver_stats.rx_lro_flushed +=
+				    vpath->lro.lro_flushed;
+
+				vxge_os_memcpy(&drv_stat[i],
+				    &(vpath->driver_stats),
+				    sizeof(vxge_drv_stats_t));
+			}
+
+			err = copyout(drv_stat, ifr->ifr_data, bufsize);
+			if (err != 0)
+				device_printf(vdev->ndev,
+				    "failed driver statistics query\n");
+
+			vxge_mem_free(drv_stat, bufsize);
+		}
+		break;
+
+	case VXGE_GET_BANDWIDTH:
+		bw_info = (vxge_bw_info_t *) ifr->ifr_data;
+
+		if ((vdev->config.hw_info.func_id != 0) &&
+		    (vdev->hw_fw_version < VXGE_FW_VERSION(1, 8, 0)))
+			break;
+
+		if (vdev->config.hw_info.func_id != 0)
+			bw_info->func_id = vdev->config.hw_info.func_id;
+
+		status = vxge_bw_priority_get(vdev, bw_info);
+		if (status != VXGE_HAL_OK)
+			break;
+
+		err = copyout(bw_info, ifr->ifr_data, sizeof(vxge_bw_info_t));
+		break;
+
+	case VXGE_SET_BANDWIDTH:
+		if (vdev->is_privilaged)
+			err = vxge_bw_priority_set(vdev, ifr);
+		break;
+
+	case VXGE_SET_PORT_MODE:
+		if (vdev->is_privilaged) {
+			if (vdev->config.hw_info.ports == VXGE_DUAL_PORT_MODE) {
+				port_info = (vxge_port_info_t *) ifr->ifr_data;
+				vdev->config.port_mode = port_info->port_mode;
+				err = vxge_port_mode_update(vdev);
+				if (err != ENXIO)
+					err = VXGE_HAL_FAIL;
+				else {
+					err = VXGE_HAL_OK;
+					device_printf(vdev->ndev,
+					    "PLEASE POWER CYCLE THE SYSTEM\n");
+				}
+			}
+		}
+		break;
+
+	case VXGE_GET_PORT_MODE:
+		if (vdev->is_privilaged) {
+			if (vdev->config.hw_info.ports == VXGE_DUAL_PORT_MODE) {
+				port_info = (vxge_port_info_t *) ifr->ifr_data;
+				err = vxge_port_mode_get(vdev, port_info);
+				if (err == VXGE_HAL_OK) {
+					err = copyout(port_info, ifr->ifr_data,
+					    sizeof(vxge_port_info_t));
+				}
+			}
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	return (err);
+}
+
+int
+vxge_bw_priority_config(vxge_dev_t *vdev)
+{
+	u32 i;
+	int err = EINVAL;
+
+	for (i = 0; i < vdev->no_of_func; i++) {
+		err = vxge_bw_priority_update(vdev, i, TRUE);
+		if (err != 0)
+			break;
+	}
+
+	return (err);
+}
+
+int
+vxge_bw_priority_set(vxge_dev_t *vdev, struct ifreq *ifr)
+{
+	int err;
+	u32 func_id;
+	vxge_bw_info_t *bw_info;
+
+	bw_info = (vxge_bw_info_t *) ifr->ifr_data;
+	func_id = bw_info->func_id;
+
+	vdev->config.bw_info[func_id].priority = bw_info->priority;
+	vdev->config.bw_info[func_id].bandwidth = bw_info->bandwidth;
+
+	err = vxge_bw_priority_update(vdev, func_id, FALSE);
+
+	return (err);
+}
+
+int
+vxge_bw_priority_update(vxge_dev_t *vdev, u32 func_id, bool binit)
+{
+	u32 i, set = 0;
+	u32 bandwidth, priority, vpath_count;
+	u64 vpath_list[VXGE_HAL_MAX_VIRTUAL_PATHS];
+
+	vxge_hal_device_t *hldev;
+	vxge_hal_vp_config_t *vp_config;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	hldev = vdev->devh;
+
+	status = vxge_hal_get_vpath_list(vdev->devh, func_id,
+	    vpath_list, &vpath_count);
+
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	for (i = 0; i < vpath_count; i++) {
+		vp_config = &(hldev->config.vp_config[vpath_list[i]]);
+
+		/* Configure Bandwidth */
+		if (vdev->config.bw_info[func_id].bandwidth !=
+		    VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) {
+
+			set = 1;
+			bandwidth = vdev->config.bw_info[func_id].bandwidth;
+			if (bandwidth < VXGE_HAL_VPATH_BW_LIMIT_MIN ||
+			    bandwidth > VXGE_HAL_VPATH_BW_LIMIT_MAX) {
+
+				bandwidth = VXGE_HAL_VPATH_BW_LIMIT_DEFAULT;
+			}
+			vp_config->bandwidth = bandwidth;
+		}
+
+		/*
+		 * If b/w limiting is enabled on any of the
+		 * VFs, then for remaining VFs set the priority to 3
+		 * and b/w limiting to max i.e 10 Gb)
+		 */
+		if (vp_config->bandwidth == VXGE_HAL_VPATH_BW_LIMIT_DEFAULT)
+			vp_config->bandwidth = VXGE_HAL_VPATH_BW_LIMIT_MAX;
+
+		if (binit && vdev->config.low_latency) {
+			if (func_id == 0)
+				vdev->config.bw_info[func_id].priority =
+				    VXGE_DEFAULT_VPATH_PRIORITY_HIGH;
+		}
+
+		/* Configure Priority */
+		if (vdev->config.bw_info[func_id].priority !=
+		    VXGE_HAL_VPATH_PRIORITY_DEFAULT) {
+
+			set = 1;
+			priority = vdev->config.bw_info[func_id].priority;
+			if (priority < VXGE_HAL_VPATH_PRIORITY_MIN ||
+			    priority > VXGE_HAL_VPATH_PRIORITY_MAX) {
+
+				priority = VXGE_HAL_VPATH_PRIORITY_DEFAULT;
+			}
+			vp_config->priority = priority;
+
+		} else if (vdev->config.low_latency) {
+			set = 1;
+			vp_config->priority = VXGE_DEFAULT_VPATH_PRIORITY_LOW;
+		}
+
+		if (set == 1) {
+			status = vxge_hal_rx_bw_priority_set(vdev->devh,
+			    vpath_list[i]);
+			if (status != VXGE_HAL_OK)
+				break;
+
+			if (vpath_list[i] < VXGE_HAL_TX_BW_VPATH_LIMIT) {
+				status = vxge_hal_tx_bw_priority_set(
+				    vdev->devh, vpath_list[i]);
+				if (status != VXGE_HAL_OK)
+					break;
+			}
+		}
+	}
+
+	return ((status  == VXGE_HAL_OK) ? 0 : EINVAL);
+}
+
+/*
+ * vxge_intr_coalesce_tx
+ * Changes interrupt coalescing if the interrupts are not within a range
+ * Return Value: Nothing
+ */
+void
+vxge_intr_coalesce_tx(vxge_vpath_t *vpath)
+{
+	u32 timer;
+
+	if (!vpath->tx_intr_coalesce)
+		return;
+
+	vpath->tx_interrupts++;
+	if (ticks > vpath->tx_ticks + hz/100) {
+
+		vpath->tx_ticks = ticks;
+		timer = vpath->tti_rtimer_val;
+		if (vpath->tx_interrupts > VXGE_MAX_TX_INTERRUPT_COUNT) {
+			if (timer != VXGE_TTI_RTIMER_ADAPT_VAL) {
+				vpath->tti_rtimer_val =
+				    VXGE_TTI_RTIMER_ADAPT_VAL;
+
+				vxge_hal_vpath_dynamic_tti_rtimer_set(
+				    vpath->handle, vpath->tti_rtimer_val);
+			}
+		} else {
+			if (timer != 0) {
+				vpath->tti_rtimer_val = 0;
+				vxge_hal_vpath_dynamic_tti_rtimer_set(
+				    vpath->handle, vpath->tti_rtimer_val);
+			}
+		}
+		vpath->tx_interrupts = 0;
+	}
+}
+
+/*
+ * vxge_intr_coalesce_rx
+ * Changes interrupt coalescing if the interrupts are not within a range
+ * Return Value: Nothing
+ */
+void
+vxge_intr_coalesce_rx(vxge_vpath_t *vpath)
+{
+	u32 timer;
+
+	if (!vpath->rx_intr_coalesce)
+		return;
+
+	vpath->rx_interrupts++;
+	if (ticks > vpath->rx_ticks + hz/100) {
+
+		vpath->rx_ticks = ticks;
+		timer = vpath->rti_rtimer_val;
+
+		if (vpath->rx_interrupts > VXGE_MAX_RX_INTERRUPT_COUNT) {
+			if (timer != VXGE_RTI_RTIMER_ADAPT_VAL) {
+				vpath->rti_rtimer_val =
+				    VXGE_RTI_RTIMER_ADAPT_VAL;
+
+				vxge_hal_vpath_dynamic_rti_rtimer_set(
+				    vpath->handle, vpath->rti_rtimer_val);
+			}
+		} else {
+			if (timer != 0) {
+				vpath->rti_rtimer_val = 0;
+				vxge_hal_vpath_dynamic_rti_rtimer_set(
+				    vpath->handle, vpath->rti_rtimer_val);
+			}
+		}
+		vpath->rx_interrupts = 0;
+	}
+}
+
+/*
+ * vxge_methods FreeBSD device interface entry points
+ */
+static device_method_t vxge_methods[] = {
+	DEVMETHOD(device_probe, vxge_probe),
+	DEVMETHOD(device_attach, vxge_attach),
+	DEVMETHOD(device_detach, vxge_detach),
+	DEVMETHOD(device_shutdown, vxge_shutdown),
+	{0, 0}
+};
+
+static driver_t vxge_driver = {
+	"vxge", vxge_methods, sizeof(vxge_dev_t),
+};
+
+static devclass_t vxge_devclass;
+
+DRIVER_MODULE(vxge, pci, vxge_driver, vxge_devclass, 0, 0);
diff --git a/sys/dev/vxge/vxge.h b/sys/dev/vxge/vxge.h
new file mode 100644
index 000000000000..630bbefed54d
--- /dev/null
+++ b/sys/dev/vxge/vxge.h
@@ -0,0 +1,620 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	_VXGE_H_
+#define	__VXGE_H_
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+#include <dev/vxge/vxge-osdep.h>
+#include "vxge-firmware.h"
+
+#define	VXGE_GET_PARAM(str_kenv, to, param, hardcode) {	\
+	static int __CONCAT(param, __LINE__);		\
+	if (testenv(str_kenv) == 1)			\
+		TUNABLE_INT_FETCH(str_kenv,		\
+		    &__CONCAT(param, __LINE__));	\
+	else						\
+		__CONCAT(param, __LINE__) = hardcode;	\
+							\
+	to.param = __CONCAT(param, __LINE__);		\
+}
+
+#define	VXGE_BUFFER_ALIGN(buffer_length, to) {		\
+	if (buffer_length % to)				\
+		buffer_length +=			\
+		    (to - (buffer_length % to));	\
+}
+
+#define	VXGE_HAL_VPATH_MSIX_ACTIVE		4
+#define	VXGE_HAL_VPATH_MSIX_ALARM_ID		2
+#define	VXGE_MSIX_ALARM_ID(hldev, i)			\
+	((__hal_device_t *) hldev)->first_vp_id *	\
+	    VXGE_HAL_VPATH_MSIX_ACTIVE + i;
+
+#define	VXGE_DUAL_PORT_MODE			2
+#define	VXGE_DUAL_PORT_MAP			0xAAAAULL
+#define	VXGE_BAUDRATE				1000000000
+#define	VXGE_MAX_SEGS				VXGE_HAL_MAX_FIFO_FRAGS
+#define	VXGE_TSO_SIZE				65600
+#define	VXGE_STATS_BUFFER_SIZE			65536
+#define	VXGE_PRINT_BUF_SIZE			128
+#define	VXGE_PMD_INFO_LEN			24
+#define	VXGE_RXD_REPLENISH_COUNT		4
+#define	VXGE_TX_LOW_THRESHOLD			32
+
+/* Default configuration parameters */
+#define	VXGE_DEFAULT_USER_HARDCODED		-1
+#define	VXGE_DEFAULT_CONFIG_VALUE		0xFF
+#define	VXGE_DEFAULT_CONFIG_ENABLE		1
+#define	VXGE_DEFAULT_CONFIG_DISABLE		0
+
+#if __FreeBSD_version >= 800000
+#define	VXGE_DEFAULT_CONFIG_MQ_ENABLE		1
+#else
+#define	VXGE_DEFAULT_CONFIG_MQ_ENABLE		0
+#endif
+
+#define	VXGE_DEFAULT_CONFIG_IFQ_MAXLEN		1024
+
+#define	VXGE_DEFAULT_BR_SIZE			4096
+#define	VXGE_DEFAULT_RTH_BUCKET_SIZE		8
+#define	VXGE_DEFAULT_RING_BLOCK			2
+#define	VXGE_DEFAULT_SUPPORTED_DEVICES		1
+#define	VXGE_DEFAULT_DEVICE_POLL_MILLIS		2000
+#define	VXGE_DEFAULT_FIFO_ALIGNED_FRAGS		1
+#define	VXGE_DEFAULT_VPATH_PRIORITY_LOW		3
+#define	VXGE_DEFAULT_VPATH_PRIORITY_HIGH	0
+#define	VXGE_DEFAULT_ALL_VID_ENABLE		\
+	VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE
+
+#define	VXGE_DEFAULT_STRIP_VLAN_TAG		\
+	VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE
+
+#define	VXGE_DEFAULT_TTI_BTIMER_VAL		250000
+#define	VXGE_DEFAULT_TTI_LTIMER_VAL		80
+#define	VXGE_DEFAULT_TTI_RTIMER_VAL		0
+
+#define	VXGE_DEFAULT_RTI_BTIMER_VAL		250
+#define	VXGE_DEFAULT_RTI_LTIMER_VAL		100
+#define	VXGE_DEFAULT_RTI_RTIMER_VAL		0
+
+#define	VXGE_TTI_RTIMER_ADAPT_VAL		10
+#define	VXGE_RTI_RTIMER_ADAPT_VAL		15
+
+#define	VXGE_DEFAULT_TTI_TX_URANGE_A		5
+#define	VXGE_DEFAULT_TTI_TX_URANGE_B		15
+#define	VXGE_DEFAULT_TTI_TX_URANGE_C		40
+
+#define	VXGE_DEFAULT_RTI_RX_URANGE_A		5
+#define	VXGE_DEFAULT_RTI_RX_URANGE_B		15
+#define	VXGE_DEFAULT_RTI_RX_URANGE_C		40
+
+#define	VXGE_DEFAULT_TTI_TX_UFC_A		1
+#define	VXGE_DEFAULT_TTI_TX_UFC_B		5
+#define	VXGE_DEFAULT_TTI_TX_UFC_C		15
+#define	VXGE_DEFAULT_TTI_TX_UFC_D		40
+
+#define	VXGE_DEFAULT_RTI_RX_UFC_A		1
+#define	VXGE_DEFAULT_RTI_RX_UFC_B		20
+#define	VXGE_DEFAULT_RTI_RX_UFC_C		40
+#define	VXGE_DEFAULT_RTI_RX_UFC_D		100
+
+#define	VXGE_MAX_RX_INTERRUPT_COUNT		100
+#define	VXGE_MAX_TX_INTERRUPT_COUNT		200
+
+#define	is_multi_func(func_mode) \
+	((func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2) || \
+	(func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8) || \
+	(func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4) || \
+	(func_mode == VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2))
+
+#define	is_single_func(func_mode) \
+	(func_mode == VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17)
+
+#define	VXGE_DRV_STATS(v, x)		v->driver_stats.x++
+#define	VXGE_MAX_MSIX_MESSAGES		(VXGE_HAL_MAX_VIRTUAL_PATHS * 2 + 2)
+
+#define	VXGE_DRV_LOCK(x)		mtx_lock(&(x)->mtx_drv)
+#define	VXGE_DRV_UNLOCK(x)		mtx_unlock(&(x)->mtx_drv)
+#define	VXGE_DRV_LOCK_DESTROY(x)	mtx_destroy(&(x)->mtx_drv)
+#define	VXGE_DRV_LOCK_ASSERT(x)		mtx_assert(&(x)->mtx_drv, MA_OWNED)
+
+#define	VXGE_TX_LOCK(x)			mtx_lock(&(x)->mtx_tx)
+#define	VXGE_TX_TRYLOCK(x)		mtx_trylock(&(x)->mtx_tx)
+#define	VXGE_TX_UNLOCK(x)		mtx_unlock(&(x)->mtx_tx)
+#define	VXGE_TX_LOCK_DESTROY(x)		mtx_destroy(&(x)->mtx_tx)
+#define	VXGE_TX_LOCK_ASSERT(x)		mtx_assert(&(x)->mtx_tx, MA_OWNED)
+
+const char *
+vxge_port_mode[6] =
+{
+	"Default",
+	"Reserved",
+	"Active/Passive",
+	"Single Port",
+	"Dual Port",
+	"Disabled"
+};
+
+const char *
+vxge_port_failure[3] =
+{
+	"No Failover",
+	"Failover only",
+	"Failover & Failback"
+};
+
+/* IOCTLs to identify vxge-manage requests */
+typedef enum _vxge_query_device_info_e {
+
+	VXGE_GET_PCI_CONF = 100,
+	VXGE_GET_MRPCIM_STATS = 101,
+	VXGE_GET_DEVICE_STATS = 102,
+	VXGE_GET_DEVICE_HWINFO = 103,
+	VXGE_GET_DRIVER_STATS = 104,
+	VXGE_GET_INTR_STATS = 105,
+	VXGE_GET_VERSION = 106,
+	VXGE_GET_TCODE = 107,
+	VXGE_GET_VPATH_COUNT = 108,
+	VXGE_GET_BANDWIDTH = 109,
+	VXGE_SET_BANDWIDTH = 110,
+	VXGE_GET_PORT_MODE = 111,
+	VXGE_SET_PORT_MODE = 112
+
+} vxge_query_device_info_e;
+
+typedef enum _vxge_firmware_upgrade_e {
+
+	VXGE_FW_UPGRADE_NONE = 0,
+	VXGE_FW_UPGRADE_ALL = 1,
+	VXGE_FW_UPGRADE_FORCE = 2
+
+} vxge_firmware_upgrade_e;
+
+typedef enum _vxge_free_resources_e {
+
+	VXGE_FREE_NONE = 0,
+	VXGE_FREE_MUTEX = 1,
+	VXGE_FREE_PCI_INFO = 2,
+	VXGE_FREE_BAR0 = 3,
+	VXGE_FREE_BAR1 = 4,
+	VXGE_FREE_BAR2 = 5,
+	VXGE_FREE_ISR_RESOURCE = 6,
+	VXGE_FREE_MEDIA = 7,
+	VXGE_FREE_INTERFACE = 8,
+	VXGE_FREE_DEVICE_CONFIG = 9,
+	VXGE_FREE_TERMINATE_DEVICE = 10,
+	VXGE_FREE_TERMINATE_DRIVER = 11,
+	VXGE_DISABLE_PCI_BUSMASTER = 12,
+	VXGE_FREE_VPATH = 13,
+	VXGE_FREE_ALL = 14
+
+} vxge_free_resources_e;
+
+typedef enum _vxge_device_attributes_e {
+
+	VXGE_PRINT_DRV_VERSION = 0,
+	VXGE_PRINT_PCIE_INFO = 1,
+	VXGE_PRINT_SERIAL_NO = 2,
+	VXGE_PRINT_PART_NO = 3,
+	VXGE_PRINT_FW_VERSION = 4,
+	VXGE_PRINT_FW_DATE = 5,
+	VXGE_PRINT_FUNC_MODE = 6,
+	VXGE_PRINT_INTR_MODE = 7,
+	VXGE_PRINT_VPATH_COUNT = 8,
+	VXGE_PRINT_MTU_SIZE = 9,
+	VXGE_PRINT_LRO_MODE = 10,
+	VXGE_PRINT_RTH_MODE = 11,
+	VXGE_PRINT_TSO_MODE = 12,
+	VXGE_PRINT_PMD_PORTS_0 = 13,
+	VXGE_PRINT_PMD_PORTS_1 = 14,
+	VXGE_PRINT_ADAPTER_TYPE = 15,
+	VXGE_PRINT_PORT_MODE = 16,
+	VXGE_PRINT_PORT_FAILURE = 17,
+	VXGE_PRINT_ACTIVE_PORT = 18,
+	VXGE_PRINT_L2SWITCH_MODE = 19
+
+} vxge_device_attribute_e;
+
+typedef struct _vxge_isr_info_t {
+
+	int	irq_rid;
+	void   *irq_handle;
+	struct resource *irq_res;
+
+} vxge_isr_info_t;
+
+typedef struct _vxge_drv_stats_t {
+
+	u64	isr_msix;
+
+	u64	tx_xmit;
+	u64	tx_posted;
+	u64	tx_compl;
+	u64	tx_tso;
+	u64	tx_tcode;
+	u64	tx_low_dtr_cnt;
+	u64	tx_reserve_failed;
+	u64	tx_no_dma_setup;
+	u64	tx_max_frags;
+	u64	tx_again;
+
+	u64	rx_compl;
+	u64	rx_tcode;
+	u64	rx_no_buf;
+	u64	rx_map_fail;
+	u64	rx_lro_queued;
+	u64	rx_lro_flushed;
+
+} vxge_drv_stats_t;
+
+typedef struct vxge_dev_t vxge_dev_t;
+
+/* Rx descriptor private structure */
+typedef struct _vxge_rxd_priv_t {
+
+	mbuf_t	mbuf_pkt;
+	bus_size_t dma_sizes[1];
+	bus_addr_t dma_addr[1];
+	bus_dmamap_t dma_map;
+
+} vxge_rxd_priv_t;
+
+/* Tx descriptor private structure */
+typedef struct _vxge_txdl_priv_t {
+
+	mbuf_t	mbuf_pkt;
+	bus_dmamap_t dma_map;
+	bus_dma_segment_t dma_buffers[VXGE_MAX_SEGS];
+
+} vxge_txdl_priv_t;
+
+typedef struct _vxge_vpath_t {
+
+	u32		vp_id;
+	u32		vp_index;
+	u32		is_open;
+	u32		lro_enable;
+	int		msix_vec;
+
+	int		msix_vec_alarm;
+	u32		is_configured;
+	u64		rxd_posted;
+	macaddr_t	mac_addr;
+	macaddr_t	mac_mask;
+
+	int		tx_ticks;
+	int		rx_ticks;
+
+	u32		tti_rtimer_val;
+	u32		rti_rtimer_val;
+
+	u64		tx_interrupts;
+	u64		rx_interrupts;
+
+	int		tx_intr_coalesce;
+	int		rx_intr_coalesce;
+
+	vxge_dev_t	*vdev;
+	vxge_hal_vpath_h handle;
+	char		mtx_tx_name[16];
+
+	bus_dma_tag_t	dma_tag_tx;
+	bus_dma_tag_t	dma_tag_rx;
+	bus_dmamap_t	extra_dma_map;
+
+	vxge_drv_stats_t driver_stats;
+	struct		mtx mtx_tx;
+	struct		lro_ctrl lro;
+
+#if __FreeBSD_version >= 800000
+	struct		buf_ring *br;
+#endif
+
+} vxge_vpath_t;
+
+typedef struct _vxge_bw_info_t {
+
+	char	query;
+	u64	func_id;
+	int	priority;
+	int	bandwidth;
+
+} vxge_bw_info_t;
+
+typedef struct _vxge_port_info_t {
+
+	char	query;
+	int	port_mode;
+	int	port_failure;
+
+} vxge_port_info_t;
+
+typedef struct _vxge_device_hw_info_t {
+
+	vxge_hal_device_hw_info_t hw_info;
+	vxge_hal_xmac_nwif_dp_mode port_mode;
+	vxge_hal_xmac_nwif_behavior_on_failure port_failure;
+
+} vxge_device_hw_info_t;
+
+typedef struct _vxge_config_t {
+
+	u32	intr_mode;
+	int	lro_enable;
+	int	rth_enable;
+	int	tso_enable;
+	int	tx_steering;
+	int	rth_bkt_sz;
+	int	ifq_maxlen;
+	int	no_of_vpath;
+	int	ifq_multi;
+	int	intr_coalesce;
+	int	low_latency;
+	int	l2_switch;
+	int	port_mode;
+	int	function_mode;
+	char	nic_attr[20][128];
+
+	vxge_hal_device_hw_info_t	hw_info;
+	vxge_firmware_upgrade_e		fw_option;
+	vxge_hal_xmac_nwif_behavior_on_failure	port_failure;
+
+	vxge_bw_info_t		bw_info[VXGE_HAL_MAX_FUNCTIONS];
+	vxge_isr_info_t		isr_info[VXGE_MAX_MSIX_MESSAGES];
+
+} vxge_config_t;
+
+struct vxge_dev_t {
+
+	device_t ndev;
+
+	bool	is_privilaged;
+	bool	is_initialized;
+	bool	is_active;
+	int	intr_count;
+	bool	fw_upgrade;
+	int	no_of_vpath;
+	u64	active_port;
+	u32	no_of_func;
+	u32	all_multi_flag;
+	u32	hw_fw_version;
+	u32	max_supported_vpath;
+	int	rx_mbuf_sz;
+	int	if_flags;
+	int	ifm_optics;
+	ifnet_t	ifp;
+
+	vxge_hal_xmac_nwif_dp_mode		port_mode;
+	vxge_hal_xmac_nwif_l2_switch_status	l2_switch;
+	vxge_hal_xmac_nwif_behavior_on_failure	port_failure;
+
+	char	ndev_name[16];
+	char	mtx_drv_name[16];
+
+	struct mtx mtx_drv;
+	struct ifmedia media;
+
+	vxge_pci_info_t		*pdev;
+	vxge_hal_device_t	*devh;
+	vxge_vpath_t		*vpaths;
+	vxge_config_t		config;
+	vxge_hal_device_config_t *device_config;
+	vxge_hal_vpath_h	vpath_handles[VXGE_HAL_MAX_VIRTUAL_PATHS];
+};
+
+int	vxge_probe(device_t);
+int	vxge_attach(device_t);
+int	vxge_detach(device_t);
+int	vxge_shutdown(device_t);
+
+int	vxge_alloc_resources(vxge_dev_t *);
+int	vxge_alloc_isr_resources(vxge_dev_t *);
+int	vxge_alloc_bar_resources(vxge_dev_t *, int);
+void	vxge_free_resources(device_t, vxge_free_resources_e);
+void	vxge_free_isr_resources(vxge_dev_t *);
+void	vxge_free_bar_resources(vxge_dev_t *, int);
+
+int	vxge_device_hw_info_get(vxge_dev_t *);
+int	vxge_firmware_verify(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_driver_init(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_firmware_upgrade(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_func_mode_set(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_port_mode_set(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_port_behavior_on_failure_set(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_l2switch_mode_set(vxge_dev_t *);
+
+void	vxge_init(void *);
+void	vxge_init_locked(vxge_dev_t *);
+
+void	vxge_stop(vxge_dev_t *);
+void	vxge_stop_locked(vxge_dev_t *);
+
+void	vxge_reset(vxge_dev_t *);
+int	vxge_ifp_setup(device_t);
+int	vxge_isr_setup(vxge_dev_t *);
+
+void	vxge_media_init(vxge_dev_t *);
+int	vxge_media_change(ifnet_t);
+void	vxge_media_status(ifnet_t, struct ifmediareq *);
+
+void	vxge_mutex_init(vxge_dev_t *);
+void	vxge_mutex_destroy(vxge_dev_t *);
+void	vxge_link_up(vxge_hal_device_h, void *);
+void	vxge_link_down(vxge_hal_device_h, void *);
+void	vxge_crit_error(vxge_hal_device_h, void *, vxge_hal_event_e, u64);
+
+int	vxge_ioctl(ifnet_t, u_long, caddr_t);
+int	vxge_ioctl_regs(vxge_dev_t *, struct ifreq *);
+int	vxge_ioctl_stats(vxge_dev_t *, struct ifreq *);
+void	vxge_promisc_set(vxge_dev_t *);
+
+void	vxge_vpath_config(vxge_dev_t *);
+int	vxge_vpath_open(vxge_dev_t *);
+void	vxge_vpath_close(vxge_dev_t *);
+void	vxge_vpath_reset(vxge_dev_t *);
+
+int	vxge_change_mtu(vxge_dev_t *, unsigned long);
+
+u32	vxge_ring_length_get(u32);
+
+void	vxge_isr_line(void *);
+int	vxge_isr_filter(void *);
+void	vxge_isr_msix(void *);
+void	vxge_isr_msix_alarm(void *);
+
+void
+vxge_intr_coalesce_tx(vxge_vpath_t *);
+
+void
+vxge_intr_coalesce_rx(vxge_vpath_t *);
+
+vxge_hal_status_e
+vxge_msix_enable(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_rth_config(vxge_dev_t *);
+
+int	vxge_dma_tags_create(vxge_vpath_t *);
+void	vxge_device_hw_info_print(vxge_dev_t *);
+int	vxge_driver_config(vxge_dev_t *);
+
+#if __FreeBSD_version >= 800000
+
+int
+vxge_mq_send(ifnet_t, mbuf_t);
+
+static inline int
+vxge_mq_send_locked(ifnet_t, vxge_vpath_t *, mbuf_t);
+
+void
+vxge_mq_qflush(ifnet_t);
+
+#endif
+
+void
+vxge_send(ifnet_t);
+
+static inline void
+vxge_send_locked(ifnet_t, vxge_vpath_t *);
+
+static inline int
+vxge_xmit(ifnet_t, vxge_vpath_t *, mbuf_t *);
+
+static inline int
+vxge_dma_mbuf_coalesce(bus_dma_tag_t, bus_dmamap_t,
+    mbuf_t *, bus_dma_segment_t *, int *);
+
+static inline void
+vxge_rx_checksum(vxge_hal_ring_rxd_info_t, mbuf_t);
+
+static inline void
+vxge_rx_input(ifnet_t, mbuf_t, vxge_vpath_t *);
+
+static inline vxge_hal_vpath_h
+vxge_vpath_handle_get(vxge_dev_t *, int);
+
+static inline int
+vxge_vpath_get(vxge_dev_t *, mbuf_t);
+
+void
+vxge_tso_config(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_tx_replenish(vxge_hal_vpath_h, vxge_hal_txdl_h, void *,
+    u32, void *, vxge_hal_reopen_e);
+
+vxge_hal_status_e
+vxge_tx_compl(vxge_hal_vpath_h, vxge_hal_txdl_h, void *,
+    vxge_hal_fifo_tcode_e, void *);
+
+void
+vxge_tx_term(vxge_hal_vpath_h, vxge_hal_txdl_h, void *,
+    vxge_hal_txdl_state_e, void *, vxge_hal_reopen_e);
+
+vxge_hal_status_e
+vxge_rx_replenish(vxge_hal_vpath_h, vxge_hal_rxd_h, void *,
+    u32, void *, vxge_hal_reopen_e);
+
+vxge_hal_status_e
+vxge_rx_compl(vxge_hal_vpath_h, vxge_hal_rxd_h, void *, u8, void *);
+
+void
+vxge_rx_term(vxge_hal_vpath_h, vxge_hal_rxd_h, void *,
+    vxge_hal_rxd_state_e, void *, vxge_hal_reopen_e);
+
+void
+vxge_rx_rxd_1b_get(vxge_vpath_t *, vxge_hal_rxd_h, void *);
+
+int
+vxge_rx_rxd_1b_set(vxge_vpath_t *, vxge_hal_rxd_h, void *);
+
+int
+vxge_bw_priority_config(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_bw_priority_get(vxge_dev_t *, vxge_bw_info_t *);
+
+int
+vxge_bw_priority_set(vxge_dev_t *, struct ifreq *);
+
+int
+vxge_bw_priority_update(vxge_dev_t *, u32, bool);
+
+int
+vxge_port_mode_update(vxge_dev_t *);
+
+vxge_hal_status_e
+vxge_port_mode_get(vxge_dev_t *, vxge_port_info_t *);
+
+void
+vxge_pmd_port_type_get(vxge_dev_t *, u32, char *, u8);
+
+void
+vxge_active_port_update(vxge_dev_t *);
+
+static inline void
+vxge_null_terminate(char *, size_t);
+
+#endif	/* _VXGE_H_ */
diff --git a/sys/dev/vxge/vxgehal/vxge-queue.c b/sys/dev/vxge/vxgehal/vxge-queue.c
new file mode 100644
index 000000000000..5cf433e53156
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxge-queue.c
@@ -0,0 +1,598 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * vxge_queue_item_data - Get item's data.
+ * @item: Queue item.
+ *
+ * Returns:  item data(variable size). Note that vxge_queue_t
+ * contains items comprized of a fixed vxge_queue_item_t "header"
+ * and a variable size data. This function returns the variable
+ * user-defined portion of the queue item.
+ */
+void *
+vxge_queue_item_data(vxge_queue_item_t *item)
+{
+	return (char *) item + sizeof(vxge_queue_item_t);
+}
+
+/*
+ * __queue_consume - (Lockless) dequeue an item from the specified queue.
+ *
+ * @queue: Event queue.
+ * @data_max_size: Maximum size of the data
+ * @item: Queue item
+ * See vxge_queue_consume().
+ */
+static vxge_queue_status_e
+__queue_consume(vxge_queue_t *queue,
+    u32 data_max_size,
+    vxge_queue_item_t *item)
+{
+	int real_size;
+	vxge_queue_item_t *elem;
+	__hal_device_t *hldev;
+
+	vxge_assert(queue != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue(
+	    "queue = 0x"VXGE_OS_STXFMT", size = %d, item = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) queue, data_max_size, (ptr_t) item);
+
+	if (vxge_list_is_empty(&queue->list_head)) {
+		vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_QUEUE_IS_EMPTY);
+		return (VXGE_QUEUE_IS_EMPTY);
+	}
+
+	elem = (vxge_queue_item_t *) queue->list_head.next;
+	if (elem->data_size > data_max_size) {
+		vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_QUEUE_NOT_ENOUGH_SPACE);
+		return (VXGE_QUEUE_NOT_ENOUGH_SPACE);
+	}
+
+	vxge_list_remove(&elem->item);
+	real_size = elem->data_size + sizeof(vxge_queue_item_t);
+	if (queue->head_ptr == elem) {
+		queue->head_ptr = (char *) queue->head_ptr + real_size;
+		vxge_hal_info_log_queue("event_type: %d \
+		    removing from the head: "
+		    "0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
+		    ":0x0x"VXGE_OS_STXFMT" elem 0x0x"VXGE_OS_STXFMT" length %d",
+		    elem->event_type, (ptr_t) queue->start_ptr,
+		    (ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
+		    (ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
+	} else if ((char *) queue->tail_ptr - real_size == (char *) elem) {
+		queue->tail_ptr = (char *) queue->tail_ptr - real_size;
+		vxge_hal_info_log_queue("event_type: %d \
+		    removing from the tail: "
+		    "0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
+		    ":0x"VXGE_OS_STXFMT" elem 0x"VXGE_OS_STXFMT" length %d",
+		    elem->event_type, (ptr_t) queue->start_ptr,
+		    (ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
+		    (ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
+	} else {
+		vxge_hal_info_log_queue("event_type: %d \
+		    removing from the list: "
+		    "0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
+		    ":0x"VXGE_OS_STXFMT" elem 0x"VXGE_OS_STXFMT" length %d",
+		    elem->event_type, (ptr_t) queue->start_ptr,
+		    (ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
+		    (ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
+	}
+	vxge_assert(queue->tail_ptr >= queue->head_ptr);
+	vxge_assert(queue->tail_ptr >= queue->start_ptr &&
+	    queue->tail_ptr <= queue->end_ptr);
+	vxge_assert(queue->head_ptr >= queue->start_ptr &&
+	    queue->head_ptr < queue->end_ptr);
+	vxge_os_memcpy(item, elem, sizeof(vxge_queue_item_t));
+	vxge_os_memcpy(vxge_queue_item_data(item), vxge_queue_item_data(elem),
+	    elem->data_size);
+
+	if (vxge_list_is_empty(&queue->list_head)) {
+		/* reset buffer pointers just to be clean */
+		queue->head_ptr = queue->tail_ptr = queue->start_ptr;
+	}
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_QUEUE_OK);
+}
+
+/*
+ * vxge_queue_produce - Enqueue an item (see vxge_queue_item_t {})
+ *			 into the specified queue.
+ * @queueh: Queue handle.
+ * @event_type: Event type. One of the enumerated event types
+ *		 that both consumer and producer "understand".
+ *		 For an example, please refer to vxge_hal_event_e.
+ * @context: Opaque (void *) "context", for instance event producer object.
+ * @is_critical: For critical event, e.g. ECC.
+ * @data_size: Size of the @data.
+ * @data: User data of variable @data_size that is _copied_ into
+ *	the new queue item (see vxge_queue_item_t {}). Upon return
+ *	from the call the @data memory can be re-used or released.
+ *
+ * Enqueue a new item.
+ *
+ * Returns: VXGE_QUEUE_OK - success.
+ * VXGE_QUEUE_IS_FULL - Queue is full.
+ * VXGE_QUEUE_OUT_OF_MEMORY - Memory allocation failed.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_consume().
+ */
+vxge_queue_status_e
+vxge_queue_produce(vxge_queue_h queueh,
+    u32 event_type,
+    void *context,
+    u32 is_critical,
+    const u32 data_size,
+    void *data)
+{
+	vxge_queue_t *queue = (vxge_queue_t *) queueh;
+	int real_size = data_size + sizeof(vxge_queue_item_t);
+	__hal_device_t *hldev;
+	vxge_queue_item_t *elem;
+	unsigned long flags = 0;
+
+	vxge_assert(queueh != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue(
+	    "queueh = 0x"VXGE_OS_STXFMT", event_type = %d, "
+	    "context = 0x"VXGE_OS_STXFMT", is_critical = %d, "
+	    "data_size = %d, data = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) queueh, event_type, (ptr_t) context,
+	    is_critical, data_size, (ptr_t) data);
+
+	vxge_assert(real_size <= VXGE_QUEUE_BUF_SIZE);
+
+	vxge_os_spin_lock_irq(&queue->lock, flags);
+
+	if (is_critical && !queue->has_critical_event) {
+		unsigned char item_buf[sizeof(vxge_queue_item_t) +
+		    VXGE_DEFAULT_EVENT_MAX_DATA_SIZE];
+		vxge_queue_item_t *item =
+		    (vxge_queue_item_t *) (void *)item_buf;
+
+		while (__queue_consume(queue, VXGE_DEFAULT_EVENT_MAX_DATA_SIZE,
+		    item) != VXGE_QUEUE_IS_EMPTY) {
+		}		/* do nothing */
+	}
+
+try_again:
+	if ((char *) queue->tail_ptr + real_size <= (char *) queue->end_ptr) {
+		elem = (vxge_queue_item_t *) queue->tail_ptr;
+		queue->tail_ptr = (void *)((char *) queue->tail_ptr + real_size);
+		vxge_hal_info_log_queue("event_type: %d adding to the tail: "
+		    "0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT
+		    ":0x"VXGE_OS_STXFMT" elem 0x"VXGE_OS_STXFMT" length %d",
+		    event_type, (ptr_t) queue->start_ptr,
+		    (ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
+		    (ptr_t) queue->end_ptr, (ptr_t) elem, real_size);
+	} else if ((char *) queue->head_ptr - real_size >=
+	    (char *) queue->start_ptr) {
+		elem = (vxge_queue_item_t *)
+		    ((void *)((char *) queue->head_ptr - real_size));
+		queue->head_ptr = elem;
+		vxge_hal_info_log_queue("event_type: %d adding to the head: "
+		    "0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT":"
+		    "0x"VXGE_OS_STXFMT":0x"VXGE_OS_STXFMT" length %d",
+		    event_type, (ptr_t) queue->start_ptr,
+		    (ptr_t) queue->head_ptr, (ptr_t) queue->tail_ptr,
+		    (ptr_t) queue->end_ptr, real_size);
+	} else {
+		vxge_queue_status_e status;
+
+		if (queue->pages_current >= queue->pages_max) {
+			vxge_os_spin_unlock_irq(&queue->lock, flags);
+			vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, VXGE_QUEUE_IS_FULL);
+			return (VXGE_QUEUE_IS_FULL);
+		}
+
+		if (queue->has_critical_event) {
+			vxge_os_spin_unlock_irq(&queue->lock, flags);
+			vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, VXGE_QUEUE_IS_FULL);
+			return (VXGE_QUEUE_IS_FULL);
+		}
+
+		/* grow */
+		status = vxge_io_queue_grow(queueh);
+		if (status != VXGE_QUEUE_OK) {
+			vxge_os_spin_unlock_irq(&queue->lock, flags);
+			vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		goto try_again;
+	}
+	vxge_assert(queue->tail_ptr >= queue->head_ptr);
+	vxge_assert(queue->tail_ptr >= queue->start_ptr &&
+	    queue->tail_ptr <= queue->end_ptr);
+	vxge_assert(queue->head_ptr >= queue->start_ptr &&
+	    queue->head_ptr < queue->end_ptr);
+	elem->data_size = data_size;
+	elem->event_type = (vxge_hal_event_e) event_type;
+	elem->is_critical = is_critical;
+	if (is_critical)
+		queue->has_critical_event = 1;
+	elem->context = context;
+	vxge_os_memcpy(vxge_queue_item_data(elem), data, data_size);
+	vxge_list_insert_before(&elem->item, &queue->list_head);
+	vxge_os_spin_unlock_irq(&queue->lock, flags);
+
+	/* no lock taken! */
+	queue->queued_func(queue->queued_data, event_type);
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_QUEUE_OK);
+}
+
+
+/*
+ * vxge_queue_create - Create protected first-in-first-out queue.
+ * @devh: HAL device handle.
+ * @pages_initial: Number of pages to be initially allocated at the
+ * time of queue creation.
+ * @pages_max: Max number of pages that can be allocated in the queue.
+ * @queued_func: Optional callback function to be called each time a new item is
+ * added to the queue.
+ * @queued_data: Argument to the callback function.
+ *
+ * Create protected (fifo) queue.
+ *
+ * Returns: Pointer to vxge_queue_t structure,
+ * NULL - on failure.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_destroy().
+ */
+vxge_queue_h
+vxge_queue_create(vxge_hal_device_h devh,
+    u32 pages_initial,
+    u32 pages_max,
+    vxge_queued_f queued_func,
+    void *queued_data)
+{
+	vxge_queue_t *queue;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue(
+	    "devh = 0x"VXGE_OS_STXFMT", pages_initial = %d, "
+	    "pages_max = %d, queued_func = 0x"VXGE_OS_STXFMT", "
+	    "queued_data = 0x"VXGE_OS_STXFMT, (ptr_t) devh, pages_initial,
+	    pages_max, (ptr_t) queued_func, (ptr_t) queued_data);
+
+	if ((queue = (vxge_queue_t *) vxge_os_malloc(hldev->header.pdev,
+	    sizeof(vxge_queue_t))) == NULL) {
+		vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_QUEUE_OUT_OF_MEMORY);
+		return (NULL);
+	}
+
+	queue->queued_func = queued_func;
+	queue->queued_data = queued_data;
+	queue->hldev = devh;
+	queue->pdev = hldev->header.pdev;
+	queue->irqh = hldev->header.irqh;
+	queue->pages_current = pages_initial;
+	queue->start_ptr = vxge_os_malloc(hldev->header.pdev,
+	    queue->pages_current * VXGE_QUEUE_BUF_SIZE);
+	if (queue->start_ptr == NULL) {
+		vxge_os_free(hldev->header.pdev, queue, sizeof(vxge_queue_t));
+		vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_QUEUE_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	queue->head_ptr = queue->tail_ptr = queue->start_ptr;
+	queue->end_ptr = (char *) queue->start_ptr +
+	    queue->pages_current * VXGE_QUEUE_BUF_SIZE;
+	vxge_os_spin_lock_init_irq(&queue->lock, queue->irqh);
+	queue->pages_initial = pages_initial;
+	queue->pages_max = pages_max;
+	vxge_list_init(&queue->list_head);
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (queue);
+}
+
+/*
+ * vxge_queue_destroy - Destroy vxge_queue_t object.
+ * @queueh: Queue handle.
+ *
+ * Destroy the specified vxge_queue_t object.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_create().
+ */
+void
+vxge_queue_destroy(vxge_queue_h queueh)
+{
+	vxge_queue_t *queue = (vxge_queue_t *) queueh;
+	__hal_device_t *hldev;
+
+	vxge_assert(queueh != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) queueh);
+
+	vxge_os_spin_lock_destroy_irq(&queue->lock, queue->irqh);
+	if (!vxge_list_is_empty(&queue->list_head)) {
+		vxge_hal_trace_log_queue("destroying non-empty queue 0x"
+		    VXGE_OS_STXFMT, (ptr_t) queue);
+	}
+	vxge_os_free(queue->pdev, queue->start_ptr, queue->pages_current *
+	    VXGE_QUEUE_BUF_SIZE);
+
+	vxge_os_free(queue->pdev, queue, sizeof(vxge_queue_t));
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_io_queue_grow - Dynamically increases the size of the queue.
+ * @queueh: Queue handle.
+ *
+ * This function is called in the case of no slot avaialble in the queue
+ * to accomodate the newly received event.
+ * Note that queue cannot grow beyond the max size specified for the
+ * queue.
+ *
+ * Returns VXGE_QUEUE_OK: On success.
+ * VXGE_QUEUE_OUT_OF_MEMORY : No memory is available.
+ */
+vxge_queue_status_e
+vxge_io_queue_grow(vxge_queue_h queueh)
+{
+	vxge_queue_t *queue = (vxge_queue_t *) queueh;
+	__hal_device_t *hldev;
+	void *newbuf, *oldbuf;
+	vxge_list_t *item;
+	vxge_queue_item_t *elem;
+
+	vxge_assert(queueh != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) queueh);
+
+	vxge_hal_info_log_queue("queue 0x"VXGE_OS_STXFMT":%d is growing",
+	    (ptr_t) queue, queue->pages_current);
+
+	newbuf = vxge_os_malloc(queue->pdev,
+	    (queue->pages_current + 1) * VXGE_QUEUE_BUF_SIZE);
+	if (newbuf == NULL) {
+		vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_QUEUE_OUT_OF_MEMORY);
+		return (VXGE_QUEUE_OUT_OF_MEMORY);
+	}
+
+	vxge_os_memcpy(newbuf, queue->start_ptr,
+	    queue->pages_current * VXGE_QUEUE_BUF_SIZE);
+	oldbuf = queue->start_ptr;
+
+	/* adjust queue sizes */
+	queue->start_ptr = newbuf;
+	queue->end_ptr = (char *) newbuf +
+	    (queue->pages_current + 1) * VXGE_QUEUE_BUF_SIZE;
+	queue->tail_ptr = (char *) newbuf +
+	/* LINTED */
+	    ((char *) queue->tail_ptr - (char *) oldbuf);
+	queue->head_ptr = (char *) newbuf +
+	/* LINTED */
+	    ((char *) queue->head_ptr - (char *) oldbuf);
+	vxge_assert(!vxge_list_is_empty(&queue->list_head));
+	queue->list_head.next = (vxge_list_t *) (void *)((char *) newbuf +
+	/* LINTED */
+	    ((char *) queue->list_head.next - (char *) oldbuf));
+	queue->list_head.prev = (vxge_list_t *) (void *)((char *) newbuf +
+	/* LINTED */
+	    ((char *) queue->list_head.prev - (char *) oldbuf));
+	/* adjust queue list */
+	vxge_list_for_each(item, &queue->list_head) {
+		elem = vxge_container_of(item, vxge_queue_item_t, item);
+		if (elem->item.next != &queue->list_head) {
+			elem->item.next =
+			    (vxge_list_t *) (void *)((char *) newbuf +
+			/* LINTED */
+			    ((char *) elem->item.next - (char *) oldbuf));
+		}
+		if (elem->item.prev != &queue->list_head) {
+			elem->item.prev =
+			    (vxge_list_t *) (void *)((char *) newbuf +
+			/* LINTED */
+			    ((char *) elem->item.prev - (char *) oldbuf));
+		}
+	}
+	vxge_os_free(queue->pdev, oldbuf,
+	    queue->pages_current * VXGE_QUEUE_BUF_SIZE);
+	queue->pages_current++;
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_QUEUE_OK);
+}
+
+/*
+ * vxge_queue_consume - Dequeue an item from the specified queue.
+ * @queueh: Queue handle.
+ * @data_max_size: Maximum expected size of the item.
+ * @item: Memory area into which the item is _copied_ upon return
+ *	from the function.
+ *
+ * Dequeue an item from the queue. The caller is required to provide
+ * enough space for the item.
+ *
+ * Returns: VXGE_QUEUE_OK - success.
+ * VXGE_QUEUE_IS_EMPTY - Queue is empty.
+ * VXGE_QUEUE_NOT_ENOUGH_SPACE - Requested item size(@data_max_size)
+ * is too small to accomodate an item from the queue.
+ *
+ * See also: vxge_queue_item_t {}, vxge_queue_produce().
+ */
+vxge_queue_status_e
+vxge_queue_consume(vxge_queue_h queueh,
+    u32 data_max_size,
+    vxge_queue_item_t *item)
+{
+	vxge_queue_t *queue = (vxge_queue_t *) queueh;
+	__hal_device_t *hldev;
+	unsigned long flags = 0;
+	vxge_queue_status_e status;
+
+	vxge_assert(queueh != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue(
+	    "queueh = 0x"VXGE_OS_STXFMT", data_max_size = %d, "
+	    "item = 0x"VXGE_OS_STXFMT, (ptr_t) queueh,
+	    data_max_size, (ptr_t) item);
+
+	vxge_os_spin_lock_irq(&queue->lock, flags);
+	status = __queue_consume(queue, data_max_size, item);
+	vxge_os_spin_unlock_irq(&queue->lock, flags);
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+
+/*
+ * vxge_queue_flush - Flush, or empty, the queue.
+ * @queueh: Queue handle.
+ *
+ * Flush the queue, i.e. make it empty by consuming all events
+ * without invoking the event processing logic (callbacks, etc.)
+ */
+void
+vxge_queue_flush(vxge_queue_h queueh)
+{
+	unsigned char item_buf[sizeof(vxge_queue_item_t) +
+	    VXGE_DEFAULT_EVENT_MAX_DATA_SIZE];
+	vxge_queue_item_t *item = (vxge_queue_item_t *) (void *)item_buf;
+	vxge_queue_t *queue = (vxge_queue_t *) queueh;
+	__hal_device_t *hldev;
+
+	vxge_assert(queueh != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) queueh);
+
+	/* flush queue by consuming all enqueued items */
+	while (vxge_queue_consume(queueh, VXGE_DEFAULT_EVENT_MAX_DATA_SIZE,
+	    item) != VXGE_QUEUE_IS_EMPTY) {
+		/* do nothing */
+		vxge_hal_trace_log_queue("item 0x"VXGE_OS_STXFMT"(%d) flushed",
+		    (ptr_t) item, item->event_type);
+	}
+
+	(void) vxge_queue_get_reset_critical(queueh);
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_queue_get_reset_critical - Check for critical events in the queue,
+ * @queueh: Queue handle.
+ *
+ * Check for critical event(s) in the queue, and reset the
+ * "has-critical-event" flag upon return.
+ * Returns: 1 - if the queue contains atleast one critical event.
+ * 0 - If there are no critical events in the queue.
+ */
+u32
+vxge_queue_get_reset_critical(vxge_queue_h queueh)
+{
+	vxge_queue_t *queue = (vxge_queue_t *) queueh;
+	int c = queue->has_critical_event;
+	__hal_device_t *hldev;
+
+	vxge_assert(queueh != NULL);
+
+	hldev = (__hal_device_t *) queue->hldev;
+
+	vxge_hal_trace_log_queue("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_queue("queueh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) queueh);
+
+	queue->has_critical_event = 0;
+
+	vxge_hal_trace_log_queue("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (c);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-blockpool.c b/sys/dev/vxge/vxgehal/vxgehal-blockpool.c
new file mode 100644
index 000000000000..cc5150455220
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-blockpool.c
@@ -0,0 +1,1031 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * __hal_blockpool_create - Create block pool
+ * @devh: Pointer to HAL Device object.
+ * @blockpool: Block pool to be created.
+ * @pool_size: Number of blocks in the pool.
+ * @pool_incr: Number of blocks to be request from OS at a time
+ * @pool_min: Number of blocks below which new blocks to be requested.
+ * @pool_max: Number of blocks above which block to be freed.
+ *
+ * This function creates block pool
+ */
+
+vxge_hal_status_e
+__hal_blockpool_create(vxge_hal_device_h devh,
+    __hal_blockpool_t *blockpool,
+    u32 pool_size,
+    u32 pool_incr,
+    u32 pool_min,
+    u32 pool_max)
+{
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_blockpool_entry_t *entry;
+	void *memblock;
+	dma_addr_t dma_addr;
+	pci_dma_h dma_handle;
+	pci_dma_acc_h acc_handle;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(devh != NULL);
+	vxge_os_memzero(&dma_handle, sizeof(pci_dma_h));
+	vxge_os_memzero(&acc_handle, sizeof(pci_dma_acc_h));
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("devh = 0x"VXGE_OS_STXFMT", "
+	    "blockpool = 0x"VXGE_OS_STXFMT", pool_size = %d, pool_incr = %d, "
+	    "pool_min = %d, pool_max = %d", (ptr_t) devh, (ptr_t) blockpool,
+	    pool_size, pool_incr, pool_min, pool_max);
+
+	if (blockpool == NULL) {
+		vxge_hal_err_log_pool(
+		    "%s:%d null pointer passed. blockpool is null",
+		    __FILE__, __LINE__);
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	blockpool->hldev = devh;
+	blockpool->block_size = VXGE_OS_HOST_PAGE_SIZE;
+	blockpool->pool_size = 0;
+	blockpool->pool_incr = pool_incr;
+	blockpool->pool_min = pool_min;
+	blockpool->pool_max = pool_max;
+	blockpool->req_out = 0;
+
+#if defined(VXGE_HAL_DMA_CONSISTENT)
+	blockpool->dma_flags = VXGE_OS_DMA_CONSISTENT;
+#else
+	blockpool->dma_flags = VXGE_OS_DMA_STREAMING;
+#endif
+
+	vxge_list_init(&blockpool->free_block_list);
+
+	vxge_list_init(&blockpool->free_entry_list);
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock_init(&blockpool->pool_lock, hldev->header.pdev);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_init_irq(&blockpool->pool_lock, hldev->header.irqh);
+#endif
+
+	for (i = 0; i < pool_size + pool_max; i++) {
+
+		entry = (__hal_blockpool_entry_t *) vxge_os_malloc(
+		    hldev->header.pdev,
+		    sizeof(__hal_blockpool_entry_t));
+		if (entry == NULL) {
+			__hal_blockpool_destroy(blockpool);
+
+			vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+			return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+		}
+
+		vxge_list_insert(&entry->item, &blockpool->free_entry_list);
+	}
+
+	for (i = 0; i < pool_size; i++) {
+
+		memblock = vxge_os_dma_malloc(
+		    hldev->header.pdev,
+		    VXGE_OS_HOST_PAGE_SIZE,
+		    blockpool->dma_flags,
+		    &dma_handle,
+		    &acc_handle);
+
+		if (memblock == NULL) {
+			__hal_blockpool_destroy(blockpool);
+			vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+			return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+		}
+
+		dma_addr = vxge_os_dma_map(
+		    hldev->header.pdev,
+		    dma_handle,
+		    memblock,
+		    VXGE_OS_HOST_PAGE_SIZE,
+		    VXGE_OS_DMA_DIR_BIDIRECTIONAL,
+		    blockpool->dma_flags);
+
+		if (dma_addr == VXGE_OS_INVALID_DMA_ADDR) {
+			vxge_os_dma_free(hldev->header.pdev,
+			    memblock,
+			    VXGE_OS_HOST_PAGE_SIZE,
+			    blockpool->dma_flags,
+			    &dma_handle,
+			    &acc_handle);
+			__hal_blockpool_destroy(blockpool);
+
+			vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+			return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+		}
+
+		entry = (__hal_blockpool_entry_t *)
+		    vxge_list_first_get(&blockpool->free_entry_list);
+
+		if (entry == NULL) {
+			entry = (__hal_blockpool_entry_t *) vxge_os_malloc(
+			    hldev->header.pdev,
+			    sizeof(__hal_blockpool_entry_t));
+		}
+
+		if (entry != NULL) {
+			vxge_list_remove(&entry->item);
+			entry->length = VXGE_OS_HOST_PAGE_SIZE;
+			entry->memblock = memblock;
+			entry->dma_addr = dma_addr;
+			entry->acc_handle = acc_handle;
+			entry->dma_handle = dma_handle;
+			vxge_list_insert(&entry->item,
+			    &blockpool->free_block_list);
+			blockpool->pool_size++;
+		} else {
+			__hal_blockpool_destroy(blockpool);
+			vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+			return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+		}
+	}
+
+	vxge_hal_info_log_pool(
+	    "Blockpool  block size:%d block pool size: %d",
+	    blockpool->block_size, blockpool->pool_size);
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_blockpool_destroy - Deallocates the block pool
+ * @blockpool: blockpool to be deallocated
+ *
+ * This function freeup the memory pool and removes the
+ * block pool.
+ */
+
+void
+__hal_blockpool_destroy(
+    __hal_blockpool_t *blockpool)
+{
+	__hal_device_t *hldev;
+	vxge_list_t *p, *n;
+
+	vxge_assert(blockpool != NULL);
+
+	hldev = (__hal_device_t *) blockpool->hldev;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("blockpool = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) blockpool);
+
+	if (blockpool == NULL) {
+		vxge_hal_err_log_pool(
+		    "%s:%d null pointer passed blockpool = null",
+		    __FILE__, __LINE__);
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 1",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+	vxge_list_for_each_safe(p, n, &blockpool->free_block_list) {
+
+		vxge_os_dma_unmap(hldev->header.pdev,
+		    ((__hal_blockpool_entry_t *) p)->dma_handle,
+		    ((__hal_blockpool_entry_t *) p)->dma_addr,
+		    ((__hal_blockpool_entry_t *) p)->length,
+		    VXGE_OS_DMA_DIR_BIDIRECTIONAL);
+
+		vxge_os_dma_free(hldev->header.pdev,
+		    ((__hal_blockpool_entry_t *) p)->memblock,
+		    ((__hal_blockpool_entry_t *) p)->length,
+		    blockpool->dma_flags,
+		    &((__hal_blockpool_entry_t *) p)->dma_handle,
+		    &((__hal_blockpool_entry_t *) p)->acc_handle);
+
+		vxge_list_remove(&((__hal_blockpool_entry_t *) p)->item);
+
+		vxge_os_free(hldev->header.pdev,
+		    (void *)p, sizeof(__hal_blockpool_entry_t));
+
+		blockpool->pool_size--;
+	}
+
+	vxge_list_for_each_safe(p, n, &blockpool->free_entry_list) {
+
+		vxge_list_remove(&((__hal_blockpool_entry_t *) p)->item);
+
+		vxge_os_free(hldev->header.pdev,
+		    (void *)p, sizeof(__hal_blockpool_entry_t));
+
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock_destroy(&blockpool->pool_lock,
+	    hldev->header.pdev);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_destroy_irq(&blockpool->pool_lock,
+	    hldev->header.pdev);
+#endif
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_blockpool_blocks_add - Request additional blocks
+ * @blockpool: Block pool.
+ *
+ * Requests additional blocks to block pool
+ */
+static inline void
+__hal_blockpool_blocks_add(
+    __hal_blockpool_t * blockpool)
+{
+	u32 nreq = 0, i;
+	__hal_device_t *hldev;
+
+	vxge_assert(blockpool != NULL);
+
+	hldev = (__hal_device_t *) blockpool->hldev;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("blockpool = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) blockpool);
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+	if ((blockpool->pool_size + blockpool->req_out) <
+	    blockpool->pool_min) {
+		nreq = blockpool->pool_incr;
+		blockpool->req_out += nreq;
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	for (i = 0; i < nreq; i++) {
+		vxge_os_dma_malloc_async(
+		    ((__hal_device_t *) blockpool->hldev)->header.pdev,
+		    blockpool->hldev,
+		    VXGE_OS_HOST_PAGE_SIZE,
+		    blockpool->dma_flags);
+	}
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_blockpool_blocks_remove - Free additional blocks
+ * @blockpool: Block pool.
+ *
+ * Frees additional blocks over maximum from the block pool
+ */
+static inline void
+__hal_blockpool_blocks_remove(
+    __hal_blockpool_t * blockpool)
+{
+	vxge_list_t *p, *n;
+	__hal_device_t *hldev;
+
+	vxge_assert(blockpool != NULL);
+
+	hldev = (__hal_device_t *) blockpool->hldev;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("blockpool = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) blockpool);
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+	vxge_list_for_each_safe(p, n, &blockpool->free_block_list) {
+
+		if (blockpool->pool_size < blockpool->pool_max)
+			break;
+
+		vxge_os_dma_unmap(
+		    ((__hal_device_t *) blockpool->hldev)->header.pdev,
+		    ((__hal_blockpool_entry_t *) p)->dma_handle,
+		    ((__hal_blockpool_entry_t *) p)->dma_addr,
+		    ((__hal_blockpool_entry_t *) p)->length,
+		    VXGE_OS_DMA_DIR_BIDIRECTIONAL);
+
+		vxge_os_dma_free(
+		    ((__hal_device_t *) blockpool->hldev)->header.pdev,
+		    ((__hal_blockpool_entry_t *) p)->memblock,
+		    ((__hal_blockpool_entry_t *) p)->length,
+		    blockpool->dma_flags,
+		    &((__hal_blockpool_entry_t *) p)->dma_handle,
+		    &((__hal_blockpool_entry_t *) p)->acc_handle);
+
+		vxge_list_remove(&((__hal_blockpool_entry_t *) p)->item);
+
+		vxge_list_insert(p, &blockpool->free_entry_list);
+
+		blockpool->pool_size--;
+
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_blockpool_block_add - callback for vxge_os_dma_malloc_async
+ * @devh: HAL device handle.
+ * @block_addr: Virtual address of the block
+ * @length: Length of the block.
+ * @p_dma_h: Physical address of the block
+ * @acc_handle: DMA acc handle
+ *
+ * Adds a block to block pool
+ */
+void
+vxge_hal_blockpool_block_add(
+    vxge_hal_device_h devh,
+    void *block_addr,
+    u32 length,
+    pci_dma_h * dma_h,
+    pci_dma_acc_h * acc_handle)
+{
+	__hal_blockpool_t *blockpool;
+	__hal_blockpool_entry_t *entry;
+	__hal_device_t *hldev;
+	dma_addr_t dma_addr;
+	vxge_hal_status_e status;
+	u32 req_out;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("devh = 0x"VXGE_OS_STXFMT", length = %d, "
+	    "block_addr = 0x"VXGE_OS_STXFMT",  dma_h = 0x"VXGE_OS_STXFMT", "
+	    "acc_handle = 0x"VXGE_OS_STXFMT, (ptr_t) devh, length,
+	    (ptr_t) block_addr, (ptr_t) dma_h, (ptr_t) acc_handle);
+
+	blockpool = &hldev->block_pool;
+
+	if (block_addr == NULL) {
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+		blockpool->req_out--;
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 1",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+	dma_addr = vxge_os_dma_map(hldev->header.pdev,
+	    *dma_h,
+	    block_addr,
+	    length,
+	    VXGE_OS_DMA_DIR_BIDIRECTIONAL,
+	    blockpool->dma_flags);
+
+	if (dma_addr == VXGE_OS_INVALID_DMA_ADDR) {
+		vxge_os_dma_free(hldev->header.pdev,
+		    block_addr,
+		    length,
+		    blockpool->dma_flags,
+		    dma_h,
+		    acc_handle);
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+		blockpool->req_out--;
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 1",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	entry = (__hal_blockpool_entry_t *)
+	    vxge_list_first_get(&blockpool->free_entry_list);
+
+	if (entry == NULL) {
+		entry = (__hal_blockpool_entry_t *) vxge_os_malloc(
+		    hldev->header.pdev,
+		    sizeof(__hal_blockpool_entry_t));
+	} else {
+		vxge_list_remove(&entry->item);
+	}
+
+	if (entry != NULL) {
+		entry->length = length;
+		entry->memblock = block_addr;
+		entry->dma_addr = dma_addr;
+		entry->acc_handle = *acc_handle;
+		entry->dma_handle = *dma_h;
+		vxge_list_insert(&entry->item, &blockpool->free_block_list);
+		blockpool->pool_size++;
+		status = VXGE_HAL_OK;
+	} else {
+		status = VXGE_HAL_ERR_OUT_OF_MEMORY;
+	}
+
+	blockpool->req_out--;
+
+	req_out = blockpool->req_out;
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	if (req_out == 0)
+		__hal_channel_process_pending_list(devh);
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+}
+
+/*
+ * __hal_blockpool_malloc - Allocate a memory block from pool
+ * @devh: HAL device handle.
+ * @size: Length of the block.
+ * @dma_addr: Buffer to return DMA Address of the block.
+ * @dma_handle: Buffer to return DMA handle of the block.
+ * @acc_handle: Buffer to return DMA acc handle
+ *
+ *
+ * Allocates a block of memory of given size, either from block pool
+ * or by calling vxge_os_dma_malloc()
+ */
+void *
+__hal_blockpool_malloc(vxge_hal_device_h devh,
+    u32 size,
+    dma_addr_t *dma_addr,
+    pci_dma_h *dma_handle,
+    pci_dma_acc_h *acc_handle)
+{
+	__hal_blockpool_entry_t *entry;
+	__hal_blockpool_t *blockpool;
+	__hal_device_t *hldev;
+	void *memblock = NULL;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool(
+	    "devh = 0x"VXGE_OS_STXFMT", size = %d, "
+	    "dma_addr = 0x"VXGE_OS_STXFMT", dma_handle = 0x"VXGE_OS_STXFMT", "
+	    "acc_handle = 0x"VXGE_OS_STXFMT, (ptr_t) devh, size,
+	    (ptr_t) dma_addr, (ptr_t) dma_handle, (ptr_t) acc_handle);
+
+	blockpool = &((__hal_device_t *) devh)->block_pool;
+
+	if (size != blockpool->block_size) {
+
+		memblock = vxge_os_dma_malloc(
+		    ((__hal_device_t *) devh)->header.pdev,
+		    size,
+		    blockpool->dma_flags |
+		    VXGE_OS_DMA_CACHELINE_ALIGNED,
+		    dma_handle,
+		    acc_handle);
+
+		if (memblock == NULL) {
+			vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+			return (NULL);
+		}
+
+		*dma_addr = vxge_os_dma_map(
+		    ((__hal_device_t *) devh)->header.pdev,
+		    *dma_handle,
+		    memblock,
+		    size,
+		    VXGE_OS_DMA_DIR_BIDIRECTIONAL,
+		    blockpool->dma_flags);
+
+		if (*dma_addr == VXGE_OS_INVALID_DMA_ADDR) {
+			vxge_os_dma_free(((__hal_device_t *) devh)->header.pdev,
+			    memblock,
+			    size,
+			    blockpool->dma_flags |
+			    VXGE_OS_DMA_CACHELINE_ALIGNED,
+			    dma_handle,
+			    acc_handle);
+
+			vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+			return (NULL);
+		}
+
+	} else {
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+		entry = (__hal_blockpool_entry_t *)
+		    vxge_list_first_get(&blockpool->free_block_list);
+
+		if (entry != NULL) {
+			vxge_list_remove(&entry->item);
+			*dma_addr = entry->dma_addr;
+			*dma_handle = entry->dma_handle;
+			*acc_handle = entry->acc_handle;
+			memblock = entry->memblock;
+
+			vxge_list_insert(&entry->item,
+			    &blockpool->free_entry_list);
+			blockpool->pool_size--;
+		}
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+
+		if (memblock != NULL)
+			__hal_blockpool_blocks_add(blockpool);
+
+	}
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, !memblock);
+
+	return (memblock);
+
+}
+
+/*
+ * __hal_blockpool_free - Frees the memory allcoated with __hal_blockpool_malloc
+ * @devh: HAL device handle.
+ * @memblock: Virtual address block
+ * @size: Length of the block.
+ * @dma_addr: DMA Address of the block.
+ * @dma_handle: DMA handle of the block.
+ * @acc_handle: DMA acc handle
+ *
+ *
+ * Frees the memory allocated with __hal_blockpool_malloc to blockpool or system
+ */
+void
+__hal_blockpool_free(vxge_hal_device_h devh,
+    void *memblock,
+    u32 size,
+    dma_addr_t *dma_addr,
+    pci_dma_h *dma_handle,
+    pci_dma_acc_h *acc_handle)
+{
+	__hal_blockpool_entry_t *entry;
+	__hal_blockpool_t *blockpool;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("devh = 0x"VXGE_OS_STXFMT", size = %d, "
+	    "dma_addr = 0x"VXGE_OS_STXFMT", dma_handle = 0x"VXGE_OS_STXFMT", "
+	    "acc_handle = 0x"VXGE_OS_STXFMT, (ptr_t) devh, size,
+	    (ptr_t) dma_addr, (ptr_t) dma_handle, (ptr_t) acc_handle);
+
+	blockpool = &((__hal_device_t *) devh)->block_pool;
+
+	if (size != blockpool->block_size) {
+
+		vxge_os_dma_unmap(((__hal_device_t *) devh)->header.pdev,
+		    *dma_handle,
+		    *dma_addr,
+		    size,
+		    VXGE_OS_DMA_DIR_BIDIRECTIONAL);
+
+		vxge_os_dma_free(((__hal_device_t *) devh)->header.pdev,
+		    memblock,
+		    size,
+		    blockpool->dma_flags |
+		    VXGE_OS_DMA_CACHELINE_ALIGNED,
+		    dma_handle,
+		    acc_handle);
+	} else {
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+		entry = (__hal_blockpool_entry_t *)
+		    vxge_list_first_get(&blockpool->free_entry_list);
+
+		if (entry == NULL) {
+			entry = (__hal_blockpool_entry_t *) vxge_os_malloc(
+			    ((__hal_device_t *) devh)->header.pdev,
+			    sizeof(__hal_blockpool_entry_t));
+		} else {
+			vxge_list_remove(&entry->item);
+		}
+
+		if (entry != NULL) {
+			entry->length = size;
+			entry->memblock = memblock;
+			entry->dma_addr = *dma_addr;
+			entry->acc_handle = *acc_handle;
+			entry->dma_handle = *dma_handle;
+			vxge_list_insert(&entry->item,
+			    &blockpool->free_block_list);
+			blockpool->pool_size++;
+			status = VXGE_HAL_OK;
+		} else {
+			status = VXGE_HAL_ERR_OUT_OF_MEMORY;
+		}
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+		if (status == VXGE_HAL_OK)
+			__hal_blockpool_blocks_remove(blockpool);
+
+	}
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+}
+
+/*
+ * __hal_blockpool_block_allocate - Allocates a block from block pool
+ * @hldev: Hal device
+ * @size: Size of the block to be allocated
+ *
+ * This function allocates a block from block pool or from the system
+ */
+__hal_blockpool_entry_t *
+__hal_blockpool_block_allocate(vxge_hal_device_h devh,
+    u32 size)
+{
+	__hal_blockpool_entry_t *entry = NULL;
+	__hal_device_t *hldev;
+	__hal_blockpool_t *blockpool;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("devh = 0x"VXGE_OS_STXFMT", size = %d",
+	    (ptr_t) devh, size);
+
+	blockpool = &((__hal_device_t *) devh)->block_pool;
+
+	if (size == blockpool->block_size) {
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+		entry = (__hal_blockpool_entry_t *)
+		    vxge_list_first_get(&blockpool->free_block_list);
+
+		if (entry != NULL) {
+			vxge_list_remove(&entry->item);
+			blockpool->pool_size--;
+		}
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+	}
+
+	if (entry != NULL)
+		__hal_blockpool_blocks_add(blockpool);
+
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, !entry);
+
+	return (entry);
+}
+
+/*
+ * __hal_blockpool_block_free - Frees a block from block pool
+ * @devh: Hal device
+ * @entry: Entry of block to be freed
+ *
+ * This function frees a block from block pool
+ */
+void
+__hal_blockpool_block_free(vxge_hal_device_h devh,
+    __hal_blockpool_entry_t *entry)
+{
+	__hal_device_t *hldev;
+	__hal_blockpool_t *blockpool;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool(
+	    "devh = 0x"VXGE_OS_STXFMT", entry = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) entry);
+
+	blockpool = &((__hal_device_t *) devh)->block_pool;
+
+	if (entry->length == blockpool->block_size) {
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+		vxge_list_insert(&entry->item, &blockpool->free_block_list);
+		blockpool->pool_size++;
+
+#if defined(VXGE_HAL_BP_POST)
+		vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+		vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+	}
+
+	__hal_blockpool_blocks_remove(blockpool);
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+
+/*
+ * __hal_blockpool_list_allocate - Allocate blocks from block pool
+ * @devh: Hal device
+ * @blocklist: List into which the allocated blocks to be inserted
+ * @count: Number of blocks to be allocated
+ *
+ * This function allocates a register from the register pool
+ */
+vxge_hal_status_e
+__hal_blockpool_list_allocate(
+    vxge_hal_device_h devh,
+    vxge_list_t *blocklist,
+    u32 count)
+{
+	u32 i;
+	__hal_device_t *hldev;
+	__hal_blockpool_t *blockpool;
+	__hal_blockpool_entry_t *block_entry;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool("devh = 0x"VXGE_OS_STXFMT", blocklist = "
+	    "0x"VXGE_OS_STXFMT", count = %d", (ptr_t) devh,
+	    (ptr_t) blocklist, count);
+
+	blockpool = &((__hal_device_t *) devh)->block_pool;
+
+	if (blocklist == NULL) {
+		vxge_hal_err_log_pool(
+		    "null pointer passed blockpool = 0x"VXGE_OS_STXFMT", "
+		    "blocklist = 0x"VXGE_OS_STXFMT, (ptr_t) blockpool,
+		    (ptr_t) blocklist);
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 1",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_FAIL);
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	vxge_list_init(blocklist);
+
+	for (i = 0; i < count; i++) {
+
+		block_entry = (__hal_blockpool_entry_t *)
+		    vxge_list_first_get(&blockpool->free_block_list);
+
+		if (block_entry == NULL)
+			break;
+
+		vxge_list_remove(&block_entry->item);
+
+		vxge_os_memzero(block_entry->memblock, blockpool->block_size);
+
+		vxge_list_insert(&block_entry->item, blocklist);
+
+		blockpool->pool_size++;
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	if (i < count) {
+
+		vxge_hal_err_log_pool("%s:%d Blockpool out of blocks",
+		    __FILE__, __LINE__);
+
+		vxge_assert(FALSE);
+
+		__hal_blockpool_list_free(blockpool, blocklist);
+
+		status = VXGE_HAL_ERR_OUT_OF_MEMORY;
+
+	}
+
+	__hal_blockpool_blocks_add(blockpool);
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_blockpool_list_free - Free a list of blocks from block pool
+ * @devh: Hal device
+ * @blocklist: List of blocks to be freed
+ *
+ * This function frees a list of blocks to the block pool
+ */
+void
+__hal_blockpool_list_free(
+    vxge_hal_device_h devh,
+    vxge_list_t *blocklist)
+{
+	__hal_device_t *hldev;
+	__hal_blockpool_t *blockpool;
+	__hal_blockpool_entry_t *block_entry;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool(
+	    "devh = 0x"VXGE_OS_STXFMT", blocklist = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) blocklist);
+
+	blockpool = &((__hal_device_t *) devh)->block_pool;
+
+	if (blocklist == NULL) {
+		vxge_hal_err_log_pool(
+		    "null pointer passed blockpool = 0x"VXGE_OS_STXFMT", "
+		    "blocklist = 0x"VXGE_OS_STXFMT, (ptr_t) blockpool,
+		    (ptr_t) blocklist);
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 1",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_lock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_lock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	while ((block_entry = (__hal_blockpool_entry_t *)
+	    vxge_list_first_get(blocklist)) != NULL) {
+
+		vxge_list_remove(&block_entry->item);
+
+		vxge_list_insert(&block_entry->item,
+		    &blockpool->free_block_list);
+
+		blockpool->pool_size++;
+	}
+
+#if defined(VXGE_HAL_BP_POST)
+	vxge_os_spin_unlock(&blockpool->pool_lock);
+#elif defined(VXGE_HAL_BP_POST_IRQ)
+	vxge_os_spin_unlock_irq(&blockpool->pool_lock, flags);
+#endif
+
+	__hal_blockpool_blocks_remove(blockpool);
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-blockpool.h b/sys/dev/vxge/vxgehal/vxgehal-blockpool.h
new file mode 100644
index 000000000000..fb3a2aa1dbc3
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-blockpool.h
@@ -0,0 +1,137 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_BLOCKPOOL_H
+#define	VXGE_HAL_BLOCKPOOL_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * struct __hal_blockpool_entry_t - Block private data structure
+ * @item: List header used to link.
+ * @length: Length of the block
+ * @memblock: Virtual address block
+ * @dma_addr: DMA Address of the block.
+ * @dma_handle: DMA handle of the block.
+ * @acc_handle: DMA acc handle
+ *
+ * Block is allocated with a header to put the blocks into list.
+ *
+ */
+typedef struct __hal_blockpool_entry_t {
+	vxge_list_t item;
+	u32	length;
+	void   *memblock;
+	dma_addr_t dma_addr;
+	pci_dma_h dma_handle;
+	pci_dma_acc_h acc_handle;
+} __hal_blockpool_entry_t;
+
+/*
+ * struct __hal_blockpool_t - Block Pool
+ * @hldev: HAL device
+ * @block_size: size of each block.
+ * @Pool_size: Number of blocks in the pool
+ * @pool_incr: Number of blocks to be requested/freed at a time from OS
+ * @pool_min: Minimum number of block below which to request additional blocks
+ * @pool_max: Maximum number of blocks above which to free additional blocks
+ * @req_out: Number of block requests with OS out standing
+ * @dma_flags: DMA flags
+ * @free_block_list: List of free blocks
+ * @pool_lock: Spin lock for the pool
+ *
+ * Block pool contains the DMA blocks preallocated.
+ *
+ */
+typedef struct __hal_blockpool_t {
+	vxge_hal_device_h hldev;
+	u32	block_size;
+	u32	pool_size;
+	u32	pool_incr;
+	u32	pool_min;
+	u32	pool_max;
+	u32	req_out;
+	u32	dma_flags;
+	vxge_list_t free_block_list;
+	vxge_list_t free_entry_list;
+
+#if defined(VXGE_HAL_BP_POST) || defined(VXGE_HAL_BP_POST_IRQ)
+	spinlock_t pool_lock;
+#endif
+
+} __hal_blockpool_t;
+
+vxge_hal_status_e
+__hal_blockpool_create(vxge_hal_device_h hldev,
+    __hal_blockpool_t *blockpool,
+    u32 pool_size,
+    u32 pool_incr,
+    u32 pool_min,
+    u32 pool_max);
+
+void
+__hal_blockpool_destroy(__hal_blockpool_t *blockpool);
+
+__hal_blockpool_entry_t *
+__hal_blockpool_block_allocate(vxge_hal_device_h hldev,
+    u32 size);
+
+void
+__hal_blockpool_block_free(vxge_hal_device_h hldev,
+    __hal_blockpool_entry_t *entry);
+
+void *
+__hal_blockpool_malloc(vxge_hal_device_h hldev,
+    u32 size,
+    dma_addr_t *dma_addr,
+    pci_dma_h *dma_handle,
+    pci_dma_acc_h *acc_handle);
+
+void
+__hal_blockpool_free(vxge_hal_device_h hldev,
+    void *memblock,
+    u32 size,
+    dma_addr_t *dma_addr,
+    pci_dma_h *dma_handle,
+    pci_dma_acc_h *acc_handle);
+
+vxge_hal_status_e
+__hal_blockpool_list_allocate(vxge_hal_device_h hldev,
+    vxge_list_t *blocklist, u32 count);
+
+void
+__hal_blockpool_list_free(vxge_hal_device_h hldev,
+    vxge_list_t *blocklist);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_BLOCKPOOL_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-channel.c b/sys/dev/vxge/vxgehal/vxgehal-channel.c
new file mode 100644
index 000000000000..d497843ee91d
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-channel.c
@@ -0,0 +1,493 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+
+/*
+ * vxge_hal_channel_allocate - Allocate memory for channel
+ * @devh: Handle to the device object
+ * @vph: Handle to Virtual Path
+ * @type: Type of channel
+ * @length: Lengths of arrays
+ * @per_dtr_space: ULD requested per dtr space to be allocated in priv
+ * @userdata: User data to be passed back in the callback
+ *
+ * This function allocates required memory for the channel and various arrays
+ * in the channel
+ */
+__hal_channel_t *
+vxge_hal_channel_allocate(
+    vxge_hal_device_h devh,
+    vxge_hal_vpath_h vph,
+    __hal_channel_type_e type,
+    u32 length,
+    u32 per_dtr_space,
+    void *userdata)
+{
+	vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
+	__hal_channel_t *channel;
+	u32 i, size = 0;
+
+	vxge_assert((devh != NULL) && (vph != NULL));
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT", vph = "
+	    "0x"VXGE_OS_STXFMT", type = %d, length = %d, "
+	    "per_dtr_space = %d, userdata = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) vph, type, length, per_dtr_space,
+	    (ptr_t) userdata);
+
+	switch (type) {
+	case VXGE_HAL_CHANNEL_TYPE_FIFO:
+		size = sizeof(__hal_fifo_t);
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_RING:
+		size = sizeof(__hal_ring_t);
+		break;
+
+
+	default:
+		vxge_assert(size);
+		break;
+
+	}
+
+	channel = (__hal_channel_t *) vxge_os_malloc(hldev->pdev, size);
+	if (channel == NULL) {
+		vxge_hal_trace_log_channel("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+
+	vxge_os_memzero(channel, size);
+	vxge_list_init(&channel->item);
+
+	channel->pdev = hldev->pdev;
+	channel->type = type;
+	channel->devh = devh;
+	channel->vph = vph;
+
+	channel->userdata = userdata;
+	channel->per_dtr_space = per_dtr_space;
+
+	channel->length = length;
+
+	channel->dtr_arr = (__hal_dtr_item_t *) vxge_os_malloc(hldev->pdev,
+	    sizeof(__hal_dtr_item_t)*length);
+	if (channel->dtr_arr == NULL) {
+		vxge_hal_channel_free(channel);
+		vxge_hal_trace_log_channel("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+
+	vxge_os_memzero(channel->dtr_arr, sizeof(__hal_dtr_item_t)*length);
+
+	channel->compl_index = 0;
+	channel->reserve_index = 0;
+
+	for (i = 0; i < length; i++)
+		channel->dtr_arr[i].state = VXGE_HAL_CHANNEL_DTR_FREE;
+
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (channel);
+}
+
+/*
+ * __hal_channel_free - Free memory allocated for channel
+ * @channel: channel to be freed
+ *
+ * This function deallocates memory from the channel and various arrays
+ * in the channel
+ */
+void
+vxge_hal_channel_free(
+    __hal_channel_t *channel)
+{
+	int size = 0;
+	vxge_hal_device_t *hldev;
+
+	vxge_assert(channel != NULL);
+
+	hldev = (vxge_hal_device_t *) channel->devh;
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) channel);
+
+	vxge_assert(channel->pdev);
+
+	if (channel->dtr_arr) {
+		vxge_os_free(channel->pdev, channel->dtr_arr,
+		    sizeof(__hal_dtr_item_t)*channel->length);
+		channel->dtr_arr = NULL;
+	}
+
+	switch (channel->type) {
+	case VXGE_HAL_CHANNEL_TYPE_FIFO:
+		size = sizeof(__hal_fifo_t);
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_RING:
+		size = sizeof(__hal_ring_t);
+		break;
+	default:
+		break;
+	}
+
+	vxge_os_free(channel->pdev, channel, size);
+
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_channel_initialize - Initialize a channel
+ * @channel: channel to be initialized
+ *
+ * This function initializes a channel by properly
+ *		setting the various references
+ */
+vxge_hal_status_e
+vxge_hal_channel_initialize(
+    __hal_channel_t *channel)
+{
+	vxge_hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(channel != NULL);
+
+	hldev = (vxge_hal_device_t *) channel->devh;
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) channel->vph)->vpath;
+
+	vxge_assert(vpath != NULL);
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) channel);
+
+	switch (channel->type) {
+	case VXGE_HAL_CHANNEL_TYPE_FIFO:
+		vpath->fifoh = (vxge_hal_fifo_h) channel;
+		channel->stats =
+		    &((__hal_fifo_t *) channel)->stats->common_stats;
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_RING:
+		vpath->ringh = (vxge_hal_ring_h) channel;
+		channel->stats =
+		    &((__hal_ring_t *) channel)->stats->common_stats;
+		break;
+
+
+	default:
+		break;
+	}
+
+	channel->is_initd = 1;
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_channel_reset - Resets a channel
+ * @channel: channel to be reset
+ *
+ * This function resets a channel by properly setting the various references
+ */
+vxge_hal_status_e
+__hal_channel_reset(
+    __hal_channel_t *channel)
+{
+	u32 i;
+	__hal_device_t *hldev;
+
+	vxge_assert(channel != NULL);
+
+	hldev = (__hal_device_t *) channel->devh;
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) channel);
+
+	vxge_assert(channel->pdev);
+
+	channel->compl_index = 0;
+	channel->reserve_index = 0;
+
+	for (i = 0; i < channel->length; i++) {
+		channel->dtr_arr[i].state =
+		    VXGE_HAL_CHANNEL_DTR_FREE;
+	}
+
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_channel_terminate - Deinitializes a channel
+ * @channel: channel to be deinitialized
+ *
+ * This function deinitializes a channel by properly
+ *		setting the various references
+ */
+void
+vxge_hal_channel_terminate(
+    __hal_channel_t *channel)
+{
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(channel != NULL);
+
+	if (!channel || !channel->is_initd)
+		return;
+
+	hldev = (__hal_device_t *) channel->devh;
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) channel->vph)->vpath;
+
+	vxge_assert(vpath != NULL);
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) channel);
+
+	switch (channel->type) {
+	case VXGE_HAL_CHANNEL_TYPE_FIFO:
+		vpath->fifoh = 0;
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_RING:
+		vpath->ringh = 0;
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_SEND_QUEUE:
+		vxge_list_remove(&channel->item);
+		vpath->sw_stats->obj_counts.no_sqs--;
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE:
+		vxge_list_remove(&channel->item);
+		vpath->sw_stats->obj_counts.no_srqs--;
+		break;
+	case VXGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE:
+		vxge_list_remove(&channel->item);
+		vpath->sw_stats->obj_counts.no_cqrqs--;
+		break;
+	default:
+		break;
+	}
+
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+void
+__hal_channel_init_pending_list(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+	vxge_list_init(&hldev->pending_channel_list);
+
+#if defined(VXGE_HAL_VP_CHANNELS)
+	vxge_os_spin_lock_init(&hldev->pending_channel_lock, hldev->pdev);
+#elif defined(VXGE_HAL_VP_CHANNELS_IRQ)
+	vxge_os_spin_lock_init_irq(&hldev->pending_channel_lock, hldev->irqh);
+#endif
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+void
+__hal_channel_insert_pending_list(
+    __hal_channel_t * channel)
+{
+	__hal_device_t *hldev = (__hal_device_t *) channel->devh;
+
+	vxge_assert(channel != NULL);
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("channel = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) channel);
+
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+	vxge_os_spin_lock(&hldev->pending_channel_lock);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+	vxge_os_spin_lock_irq(&hldev->pending_channel_lock, flags);
+#endif
+
+	vxge_list_insert_before(&channel->item, &hldev->pending_channel_list);
+
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+	vxge_os_spin_unlock(&hldev->pending_channel_lock);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+	vxge_os_spin_unlock_irq(&hldev->pending_channel_lock, flags);
+#endif
+
+	__hal_channel_process_pending_list(channel->devh);
+
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+void
+__hal_channel_process_pending_list(
+    vxge_hal_device_h devh)
+{
+	vxge_hal_status_e status;
+	__hal_channel_t *channel;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (;;) {
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+		vxge_os_spin_lock(&hldev->pending_channel_lock);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+		vxge_os_spin_lock_irq(&hldev->pending_channel_lock, flags);
+#endif
+
+		channel = (__hal_channel_t *)
+		    vxge_list_first_get(&hldev->pending_channel_list);
+
+		if (channel != NULL)
+			vxge_list_remove(&channel->item);
+
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+		vxge_os_spin_unlock(&hldev->pending_channel_lock);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+		vxge_os_spin_unlock_irq(&hldev->pending_channel_lock, flags);
+#endif
+
+		if (channel == NULL) {
+			vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+			    __FILE__, __func__, __LINE__);
+			return;
+		}
+
+		switch (channel->type) {
+		default:
+			status = VXGE_HAL_OK;
+			break;
+		}
+
+		if (status == VXGE_HAL_ERR_OUT_OF_MEMORY) {
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+			vxge_os_spin_lock(&hldev->pending_channel_lock);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+			vxge_os_spin_lock_irq(&hldev->pending_channel_lock,
+			    flags);
+#endif
+
+			vxge_list_insert(&channel->item,
+			    &hldev->pending_channel_list);
+
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+			vxge_os_spin_unlock(&hldev->pending_channel_lock);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+			vxge_os_spin_unlock_irq(&hldev->pending_channel_lock,
+			    flags);
+#endif
+			vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+			    __FILE__, __func__, __LINE__);
+
+			return;
+		}
+
+	}
+}
+
+void
+__hal_channel_destroy_pending_list(
+    vxge_hal_device_h devh)
+{
+	vxge_list_t *p, *n;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_channel("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_channel("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	vxge_list_for_each_safe(p, n, &hldev->pending_channel_list) {
+
+		vxge_list_remove(p);
+
+		switch (((__hal_channel_t *) p)->type) {
+		default:
+			break;
+		}
+
+	}
+
+#if defined(VXGE_HAL_PENDING_CHANNELS)
+	vxge_os_spin_lock_destroy(&hldev->pending_channel_lock,
+	    hldev->header.pdev);
+#elif defined(VXGE_HAL_PENDING_CHANNELS_IRQ)
+	vxge_os_spin_lock_destroy_irq(&hldev->pending_channel_lock,
+	    hldev->header.pdev);
+#endif
+	vxge_hal_trace_log_channel("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-channel.h b/sys/dev/vxge/vxgehal/vxgehal-channel.h
new file mode 100644
index 000000000000..bce3ad2d1f61
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-channel.h
@@ -0,0 +1,386 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_CHANNEL_H
+#define	VXGE_HAL_CHANNEL_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * __hal_dtr_h - Handle to the desriptor object used for nonoffload
+ *		send or receive. Generic handle which can be with txd or rxd
+ */
+typedef void *__hal_dtr_h;
+
+/*
+ * enum __hal_channel_type_e - Enumerated channel types.
+ * @VXGE_HAL_CHANNEL_TYPE_UNKNOWN: Unknown channel.
+ * @VXGE_HAL_CHANNEL_TYPE_FIFO: fifo.
+ * @VXGE_HAL_CHANNEL_TYPE_RING: ring.
+ * @VXGE_HAL_CHANNEL_TYPE_SQ: Send Queue
+ * @VXGE_HAL_CHANNEL_TYPE_SRQ: Receive Queue
+ * @VXGE_HAL_CHANNEL_TYPE_CQRQ: Receive queue completion queue
+ * @VXGE_HAL_CHANNEL_TYPE_UMQ: Up message queue
+ * @VXGE_HAL_CHANNEL_TYPE_DMQ: Down message queue
+ * @VXGE_HAL_CHANNEL_TYPE_MAX: Maximum number of HAL-supported
+ * (and recognized) channel types. Currently: 7.
+ *
+ * Enumerated channel types. Currently there are only two link-layer
+ * channels - X3100 fifo and X3100 ring. In the future the list will grow.
+ */
+typedef enum __hal_channel_type_e {
+	VXGE_HAL_CHANNEL_TYPE_UNKNOWN			= 0,
+	VXGE_HAL_CHANNEL_TYPE_FIFO			= 1,
+	VXGE_HAL_CHANNEL_TYPE_RING			= 2,
+	VXGE_HAL_CHANNEL_TYPE_SEND_QUEUE		= 3,
+	VXGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE		= 4,
+	VXGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE		= 5,
+	VXGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE		= 6,
+	VXGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE	= 7,
+	VXGE_HAL_CHANNEL_TYPE_MAX			= 8
+} __hal_channel_type_e;
+
+/*
+ * __hal_dtr_item_t
+ * @dtr: Pointer to the descriptors that contains the dma data
+ *		to/from the device.
+ * @hal_priv: HAL Private data related to the dtr.
+ * @uld_priv: ULD Private data related to the dtr.
+ */
+typedef struct __hal_dtr_item_t {
+	void   *dtr;
+	void   *hal_priv;
+	void   *uld_priv;
+	u32	state;
+#define	VXGE_HAL_CHANNEL_DTR_FREE	0
+#define	VXGE_HAL_CHANNEL_DTR_RESERVED	1
+#define	VXGE_HAL_CHANNEL_DTR_POSTED	2
+#define	VXGE_HAL_CHANNEL_DTR_COMPLETED	3
+} __hal_dtr_item_t;
+
+/*
+ * __hal_channel_t
+ * @item: List item; used to maintain a list of open channels.
+ * @type: Channel type. See vxge_hal_channel_type_e {}.
+ * @devh: Device handle. HAL device object that contains _this_ channel.
+ * @pdev: PCI Device object
+ * @vph: Virtual path handle. Virtual Path Object that contains _this_ channel.
+ * @length: Channel length. Currently allocated number of descriptors.
+ *	The channel length "grows" when more descriptors get allocated.
+ *	See _hal_mempool_grow.
+ * @dtr_arr: Dtr array. Contains descriptors posted to the channel and their
+ *	private data.
+ *	Note that at any point in time @dtr_arr contains 3 types of
+ *	descriptors:
+ *	1) posted but not yet consumed by X3100 device;
+ *	2) consumed but not yet completed;
+ *	3) completed.
+ * @post_index: Post index. At any point in time points on the
+ *	position in the channel, which'll contain next to-be-posted
+ *	descriptor.
+ * @compl_index: Completion index. At any point in time points on the
+ *	position in the channel, which will contain next
+ *	to-be-completed descriptor.
+ * @reserve_index: Reserve index. At any point in time points on the
+ *	position in the channel, which will contain next
+ *	to-be-reserved descriptor.
+ * @free_dtr_count: Number of dtrs free.
+ * @posted_dtr_count: Number of dtrs posted
+ * @post_lock: Lock to serialize multiple concurrent "posters" of descriptors
+ *		on the given channel.
+ * @poll_bytes: Poll bytes.
+ * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
+ *		to store per-operation control information.
+ * @stats: Pointer to common statistics
+ * @userdata: Per-channel opaque (void *) user-defined context, which may be
+ *	upper-layer driver object, ULP connection, etc.
+ *	Once channel is open, @userdata is passed back to user via
+ *	vxge_hal_channel_callback_f.
+ *
+ * HAL channel object.
+ *
+ * See also: vxge_hal_channel_type_e {}, vxge_hal_channel_flag_e
+ */
+typedef struct __hal_channel_t {
+	vxge_list_t		item;
+	__hal_channel_type_e	type;
+	vxge_hal_device_h	devh;
+	pci_dev_h		pdev;
+	vxge_hal_vpath_h	vph;
+	u32			length;
+	u32			is_initd;
+	__hal_dtr_item_t	*dtr_arr;
+	u32			compl_index __vxge_os_attr_cacheline_aligned;
+	u32			reserve_index __vxge_os_attr_cacheline_aligned;
+	spinlock_t		post_lock;
+	u32			poll_bytes;
+	u32			per_dtr_space;
+	vxge_hal_vpath_stats_sw_common_info_t *stats;
+	void			*userdata;
+} __hal_channel_t __vxge_os_attr_cacheline_aligned;
+
+#define	__hal_channel_is_posted_dtr(channel, index) \
+	    ((channel)->dtr_arr[index].state == VXGE_HAL_CHANNEL_DTR_POSTED)
+
+#define	__hal_channel_for_each_posted_dtr(channel, dtrh, index) \
+	for (index = (channel)->compl_index,\
+	    dtrh = (channel)->dtr_arr[index].dtr; \
+	    (index < (channel)->reserve_index) && \
+	    ((channel)->dtr_arr[index].state == VXGE_HAL_CHANNEL_DTR_POSTED); \
+	    index = (++index == (channel)->length)? 0 : index, \
+	    dtrh = (channel)->dtr_arr[index].dtr)
+
+#define	__hal_channel_for_each_dtr(channel, dtrh, index) \
+	for (index = 0, dtrh = (channel)->dtr_arr[index].dtr; \
+	    index < (channel)->length; \
+	    dtrh = ((++index == (channel)->length)? 0 : \
+	    (channel)->dtr_arr[index].dtr))
+
+#define	__hal_channel_free_dtr_count(channel)			\
+	(((channel)->reserve_index < (channel)->compl_index) ?	\
+	((channel)->compl_index - (channel)->reserve_index) :	\
+	(((channel)->length - (channel)->reserve_index) + \
+	(channel)->reserve_index))
+
+/* ========================== CHANNEL PRIVATE API ========================= */
+
+__hal_channel_t *
+vxge_hal_channel_allocate(
+    vxge_hal_device_h devh,
+    vxge_hal_vpath_h vph,
+    __hal_channel_type_e type,
+    u32 length,
+    u32 per_dtr_space,
+    void *userdata);
+
+void
+vxge_hal_channel_free(
+    __hal_channel_t *channel);
+
+vxge_hal_status_e
+vxge_hal_channel_initialize(
+    __hal_channel_t *channel);
+
+vxge_hal_status_e
+__hal_channel_reset(
+    __hal_channel_t *channel);
+
+void
+vxge_hal_channel_terminate(
+    __hal_channel_t *channel);
+
+void
+__hal_channel_init_pending_list(
+    vxge_hal_device_h devh);
+
+void
+__hal_channel_insert_pending_list(
+    __hal_channel_t * channel);
+
+void
+__hal_channel_process_pending_list(
+    vxge_hal_device_h devhv);
+
+void
+__hal_channel_destroy_pending_list(
+    vxge_hal_device_h devh);
+
+#if defined(VXGE_DEBUG_FP) && (VXGE_DEBUG_FP & VXGE_DEBUG_FP_CHANNEL)
+#define	__HAL_STATIC_CHANNEL
+#define	__HAL_INLINE_CHANNEL
+#else	/* VXGE_FASTPATH_EXTERN */
+#define	__HAL_STATIC_CHANNEL static
+#define	__HAL_INLINE_CHANNEL inline
+#endif	/* VXGE_FASTPATH_INLINE */
+
+/* ========================== CHANNEL Fast Path API ========================= */
+/*
+ * __hal_channel_dtr_reserve- Reserve a dtr from the channel
+ * @channelh: Channel
+ * @dtrh: Buffer to return the DTR pointer
+ *
+ * Reserve a dtr from the reserve array.
+ *
+ */
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL vxge_hal_status_e
+/* LINTED */
+__hal_channel_dtr_reserve(__hal_channel_t *channel, __hal_dtr_h *dtrh)
+{
+	vxge_hal_status_e status = VXGE_HAL_INF_OUT_OF_DESCRIPTORS;
+
+	*dtrh = NULL;
+
+	if (channel->dtr_arr[channel->reserve_index].state ==
+	    VXGE_HAL_CHANNEL_DTR_FREE) {
+
+		*dtrh = channel->dtr_arr[channel->reserve_index].dtr;
+
+		channel->dtr_arr[channel->reserve_index].state =
+		    VXGE_HAL_CHANNEL_DTR_RESERVED;
+
+		if (++channel->reserve_index == channel->length)
+			channel->reserve_index = 0;
+
+		status = VXGE_HAL_OK;
+
+	} else {
+
+#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
+		__hal_device_t *hldev = (__hal_device_t *) channel->devh;
+
+		vxge_hal_info_log_channel("channel %d is full!", channel->type);
+#endif
+
+		channel->stats->full_cnt++;
+	}
+
+	return (status);
+}
+
+/*
+ * __hal_channel_dtr_restore - Restores a dtr to the channel
+ * @channelh: Channel
+ * @dtr: DTR pointer
+ *
+ * Returns a dtr back to reserve array.
+ *
+ */
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+/* LINTED */
+__hal_channel_dtr_restore(__hal_channel_t *channel, __hal_dtr_h dtrh)
+{
+	u32 dtr_index;
+
+	/*
+	 * restore a previously allocated dtrh at current offset and update
+	 * the available reserve length accordingly. If dtrh is null just
+	 * update the reserve length, only
+	 */
+
+	if (channel->reserve_index == 0)
+		dtr_index = channel->length;
+	else
+		dtr_index = channel->reserve_index - 1;
+
+	if ((channel->dtr_arr[dtr_index].dtr == dtrh)) {
+
+		channel->reserve_index = dtr_index;
+		channel->dtr_arr[dtr_index].state = VXGE_HAL_CHANNEL_DTR_FREE;
+
+#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
+
+		__hal_device_t *hldev = (__hal_device_t *) channel->devh;
+		vxge_hal_info_log_channel("dtrh 0x"VXGE_OS_STXFMT" \
+		    restored for " "channel %d at reserve index %d, ",
+		    (ptr_t) dtrh, channel->type,
+		    channel->reserve_index);
+#endif
+	}
+}
+
+/*
+ * __hal_channel_dtr_post - Post a dtr to the channel
+ * @channelh: Channel
+ * @dtr: DTR pointer
+ *
+ * Posts a dtr to work array.
+ *
+ */
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+/* LINTED */
+__hal_channel_dtr_post(__hal_channel_t *channel, u32 dtr_index)
+{
+	channel->dtr_arr[dtr_index].state =
+	    VXGE_HAL_CHANNEL_DTR_POSTED;
+}
+
+/*
+ * __hal_channel_dtr_try_complete - Returns next completed dtr
+ * @channelh: Channel
+ * @dtr: Buffer to return the next completed DTR pointer
+ *
+ * Returns the next completed dtr with out removing it from work array
+ *
+ */
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+/* LINTED */
+__hal_channel_dtr_try_complete(__hal_channel_t *channel, __hal_dtr_h *dtrh)
+{
+	vxge_assert(channel->dtr_arr);
+	vxge_assert(channel->compl_index < channel->length);
+
+	if (channel->dtr_arr[channel->compl_index].state ==
+	    VXGE_HAL_CHANNEL_DTR_POSTED)
+		*dtrh = channel->dtr_arr[channel->compl_index].dtr;
+	else
+		*dtrh = NULL;
+}
+
+/*
+ * __hal_channel_dtr_complete - Removes next completed dtr from the work array
+ * @channelh: Channel
+ *
+ * Removes the next completed dtr from work array
+ *
+ */
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+/* LINTED */
+__hal_channel_dtr_complete(__hal_channel_t *channel)
+{
+	channel->dtr_arr[channel->compl_index].state =
+	VXGE_HAL_CHANNEL_DTR_COMPLETED;
+
+	if (++channel->compl_index == channel->length)
+		channel->compl_index = 0;
+
+	channel->stats->total_compl_cnt++;
+}
+
+/*
+ * __hal_channel_dtr_free - Frees a dtr
+ * @channelh: Channel
+ * @index:  Index of DTR
+ *
+ * Returns the dtr to free array
+ *
+ */
+__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
+/* LINTED */
+__hal_channel_dtr_free(__hal_channel_t *channel, u32 dtr_index)
+{
+	channel->dtr_arr[dtr_index].state =
+	    VXGE_HAL_CHANNEL_DTR_FREE;
+}
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_CHANNEL_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-common-reg.h b/sys/dev/vxge/vxgehal/vxgehal-common-reg.h
new file mode 100644
index 000000000000..19be2595377c
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-common-reg.h
@@ -0,0 +1,256 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_COMMON_REGS_H
+#define	VXGE_HAL_COMMON_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_common_reg_t {
+
+	u8	unused00a00[0x00a00];
+
+/* 0x00a00 */	u64	prc_status1;
+#define	VXGE_HAL_PRC_STATUS1_PRC_VP_QUIESCENT(n)	mBIT(n)
+/* 0x00a08 */	u64	rxdcm_reset_in_progress;
+#define	VXGE_HAL_RXDCM_RESET_IN_PROGRESS_PRC_VP(n)	mBIT(n)
+/* 0x00a10 */	u64	replicq_flush_in_progress;
+#define	VXGE_HAL_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n)	mBIT(n)
+/* 0x00a18 */	u64	rxpe_cmds_reset_in_progress;
+#define	VXGE_HAL_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n)	mBIT(n)
+/* 0x00a20 */	u64	mxp_cmds_reset_in_progress;
+#define	VXGE_HAL_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n)	mBIT(n)
+/* 0x00a28 */	u64	noffload_reset_in_progress;
+#define	VXGE_HAL_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n)	mBIT(n)
+/* 0x00a30 */	u64	rd_req_in_progress;
+#define	VXGE_HAL_RD_REQ_IN_PROGRESS_VP(n)	mBIT(n)
+/* 0x00a38 */	u64	rd_req_outstanding;
+#define	VXGE_HAL_RD_REQ_OUTSTANDING_VP(n)	mBIT(n)
+/* 0x00a40 */	u64	kdfc_reset_in_progress;
+#define	VXGE_HAL_KDFC_RESET_IN_PROGRESS_NOA_VP(n)	mBIT(n)
+	u8	unused00b00[0x00b00 - 0x00a48];
+
+/* 0x00b00 */	u64	one_cfg_vp;
+#define	VXGE_HAL_ONE_CFG_VP_RDY(n)	mBIT(n)
+/* 0x00b08 */	u64	one_common;
+#define	VXGE_HAL_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n)	mBIT(n)
+	u8	unused00b80[0x00b80 - 0x00b10];
+
+/* 0x00b80 */	u64	tim_int_en;
+#define	VXGE_HAL_TIM_INT_EN_TIM_VP(n)	mBIT(n)
+/* 0x00b88 */	u64	tim_set_int_en;
+#define	VXGE_HAL_TIM_SET_INT_EN_VP(n)	mBIT(n)
+/* 0x00b90 */	u64	tim_clr_int_en;
+#define	VXGE_HAL_TIM_CLR_INT_EN_VP(n)	mBIT(n)
+/* 0x00b98 */	u64	tim_mask_int_during_reset;
+#define	VXGE_HAL_TIM_MASK_INT_DURING_RESET_VPATH(n)	mBIT(n)
+/* 0x00ba0 */	u64	tim_reset_in_progress;
+#define	VXGE_HAL_TIM_RESET_IN_PROGRESS_TIM_VPATH(n)	mBIT(n)
+/* 0x00ba8 */	u64	tim_outstanding_bmap;
+#define	VXGE_HAL_TIM_OUTSTANDING_BMAP_TIM_VPATH(n)	mBIT(n)
+	u8	unused00c00[0x00c00 - 0x00bb0];
+
+/* 0x00c00 */	u64	msg_reset_in_progress;
+#define	VXGE_HAL_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val)	vBIT(val, 0, 17)
+/* 0x00c08 */	u64	msg_mxp_mr_ready;
+#define	VXGE_HAL_MSG_MXP_MR_READY_MP_BOOTED(n)	mBIT(n)
+/* 0x00c10 */	u64	msg_uxp_mr_ready;
+#define	VXGE_HAL_MSG_UXP_MR_READY_UP_BOOTED(n)	mBIT(n)
+/* 0x00c18 */	u64	msg_dmq_noni_rtl_prefetch;
+#define	VXGE_HAL_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n)	mBIT(n)
+/* 0x00c20 */	u64	msg_umq_rtl_bwr;
+#define	VXGE_HAL_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n)	mBIT(n)
+	u8	unused00d00[0x00d00 - 0x00c28];
+
+/* 0x00d00 */	u64	cmn_rsthdlr_cfg0;
+#define	VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val)	vBIT(val, 0, 17)
+/* 0x00d08 */	u64	cmn_rsthdlr_cfg1;
+#define	VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val)	vBIT(val, 0, 17)
+/* 0x00d10 */	u64	cmn_rsthdlr_cfg2;
+#define	VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val)	vBIT(val, 0, 17)
+/* 0x00d18 */	u64	cmn_rsthdlr_cfg3;
+#define	VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val)	vBIT(val, 0, 17)
+/* 0x00d20 */	u64	cmn_rsthdlr_cfg4;
+#define	VXGE_HAL_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val)	vBIT(val, 0, 17)
+	u8	unused00d40[0x00d40 - 0x00d28];
+
+/* 0x00d40 */	u64	cmn_rsthdlr_cfg8;
+#define	VXGE_HAL_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val)	vBIT(val, 0, 17)
+/* 0x00d48 */	u64	stats_cfg0;
+#define	VXGE_HAL_STATS_CFG0_STATS_ENABLE(val)	vBIT(val, 0, 17)
+	u8	unused00da8[0x00da8 - 0x00d50];
+
+/* 0x00da8 */	u64	clear_msix_mask_vect[4];
+#define	VXGE_HAL_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val)	vBIT(val, 0, 17)
+/* 0x00dc8 */	u64	set_msix_mask_vect[4];
+#define	VXGE_HAL_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val)	vBIT(val, 0, 17)
+/* 0x00de8 */	u64	clear_msix_mask_all_vect;
+#define	VXGE_HAL_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val)\
+								vBIT(val, 0, 17)
+/* 0x00df0 */	u64	set_msix_mask_all_vect;
+#define	VXGE_HAL_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val)\
+								vBIT(val, 0, 17)
+/* 0x00df8 */	u64	mask_vector[4];
+#define	VXGE_HAL_MASK_VECTOR_MASK_VECTOR(val)	vBIT(val, 0, 17)
+/* 0x00e18 */	u64	msix_pending_vector[4];
+#define	VXGE_HAL_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val)	vBIT(val, 0, 17)
+/* 0x00e38 */	u64	clr_msix_one_shot_vec[4];
+#define	VXGE_HAL_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val)\
+								vBIT(val, 0, 17)
+/* 0x00e58 */	u64	titan_asic_id;
+#define	VXGE_HAL_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val)		vBIT(val, 0, 16)
+#define	VXGE_HAL_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val)	vBIT(val, 48, 8)
+#define	VXGE_HAL_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val)	vBIT(val, 56, 8)
+/* 0x00e60 */	u64	titan_general_int_status;
+#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT	mBIT(0)
+#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT	mBIT(1)
+#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT	mBIT(2)
+#define	VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val)\
+								vBIT(val, 3, 17)
+	u8	unused00e70[0x00e70 - 0x00e68];
+
+/* 0x00e70 */	u64	titan_mask_all_int;
+#define	VXGE_HAL_TITAN_MASK_ALL_INT_ALARM	mBIT(7)
+#define	VXGE_HAL_TITAN_MASK_ALL_INT_TRAFFIC	mBIT(15)
+	u8	unused00e80[0x00e80 - 0x00e78];
+
+/* 0x00e80 */	u64	tim_int_status0;
+#define	VXGE_HAL_TIM_INT_STATUS0_TIM_INT_STATUS0(val)	vBIT(val, 0, 64)
+/* 0x00e88 */	u64	tim_int_mask0;
+#define	VXGE_HAL_TIM_INT_MASK0_TIM_INT_MASK0(val)	vBIT(val, 0, 64)
+/* 0x00e90 */	u64	tim_int_status1;
+#define	VXGE_HAL_TIM_INT_STATUS1_TIM_INT_STATUS1(val)	vBIT(val, 0, 4)
+/* 0x00e98 */	u64	tim_int_mask1;
+#define	VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(val)	vBIT(val, 0, 4)
+/* 0x00ea0 */	u64	rti_int_status;
+#define	VXGE_HAL_RTI_INT_STATUS_RTI_INT_STATUS(val)	vBIT(val, 0, 17)
+/* 0x00ea8 */	u64	rti_int_mask;
+#define	VXGE_HAL_RTI_INT_MASK_RTI_INT_MASK(val)	vBIT(val, 0, 17)
+/* 0x00eb0 */	u64	adapter_status;
+#define	VXGE_HAL_ADAPTER_STATUS_RTDMA_RTDMA_READY	mBIT(0)
+#define	VXGE_HAL_ADAPTER_STATUS_WRDMA_WRDMA_READY	mBIT(1)
+#define	VXGE_HAL_ADAPTER_STATUS_KDFC_KDFC_READY	mBIT(2)
+#define	VXGE_HAL_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY	mBIT(3)
+#define	VXGE_HAL_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT	mBIT(4)
+#define	VXGE_HAL_ADAPTER_STATUS_XGMAC_NETWORK_FAULT	mBIT(5)
+#define	VXGE_HAL_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT	mBIT(6)
+#define	VXGE_HAL_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY	mBIT(7)
+#define	VXGE_HAL_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY	mBIT(8)
+#define	VXGE_HAL_ADAPTER_STATUS_RIC_RIC_RUNNING	mBIT(9)
+#define	VXGE_HAL_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK	mBIT(10)
+#define	VXGE_HAL_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK	mBIT(11)
+#define	VXGE_HAL_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK	mBIT(12)
+#define	VXGE_HAL_ADAPTER_STATUS_PCC_PCC_IDLE(val)	vBIT(val, 24, 8)
+#define	VXGE_HAL_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val)	vBIT(val, 44, 8)
+/* 0x00eb8 */	u64	gen_ctrl;
+#define	VXGE_HAL_GEN_CTRL_SPI_MRPCIM_WR_DIS	mBIT(0)
+#define	VXGE_HAL_GEN_CTRL_SPI_MRPCIM_RD_DIS	mBIT(1)
+#define	VXGE_HAL_GEN_CTRL_SPI_SRPCIM_WR_DIS	mBIT(2)
+#define	VXGE_HAL_GEN_CTRL_SPI_SRPCIM_RD_DIS	mBIT(3)
+#define	VXGE_HAL_GEN_CTRL_SPI_DEBUG_DIS	mBIT(4)
+#define	VXGE_HAL_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS	mBIT(5)
+#define	VXGE_HAL_GEN_CTRL_SPI_NOT_USED(val)	vBIT(val, 6, 4)
+	u8	unused00ed0[0x00ed0 - 0x00ec0];
+
+/* 0x00ed0 */	u64	adapter_ready;
+#define	VXGE_HAL_ADAPTER_READY_ADAPTER_READY	mBIT(63)
+/* 0x00ed8 */	u64	outstanding_read;
+#define	VXGE_HAL_OUTSTANDING_READ_OUTSTANDING_READ(val)	vBIT(val, 0, 17)
+/* 0x00ee0 */	u64	vpath_rst_in_prog;
+#define	VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val)	vBIT(val, 0, 17)
+/* 0x00ee8 */	u64	vpath_reg_modified;
+#define	VXGE_HAL_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val)	vBIT(val, 0, 17)
+	u8	unused00f40[0x00f40 - 0x00ef0];
+
+/* 0x00f40 */	u64	qcc_reset_in_progress;
+#define	VXGE_HAL_QCC_RESET_IN_PROGRESS_QCC_VPATH(n)	mBIT(n)
+	u8	unused00fc0[0x00fc0 - 0x00f48];
+
+/* 0x00fc0 */	u64	cp_reset_in_progress;
+#define	VXGE_HAL_CP_RESET_IN_PROGRESS_CP_VPATH(n)	mBIT(n)
+	u8	unused01000[0x01000 - 0x00fc8];
+
+/* 0x01000 */	u64	h2l_reset_in_progress;
+#define	VXGE_HAL_H2L_RESET_IN_PROGRESS_H2L_VPATH(n)	mBIT(n)
+	u8	unused01080[0x01080 - 0x01008];
+
+/* 0x01080 */	u64	xgmac_ready;
+#define	VXGE_HAL_XGMAC_READY_XMACJ_READY(val)	vBIT(val, 0, 17)
+	u8	unused010c0[0x010c0 - 0x01088];
+
+/* 0x010c0 */	u64	fbif_ready;
+#define	VXGE_HAL_FBIF_READY_FAU_READY(val)	vBIT(val, 0, 17)
+	u8	unused01100[0x01100 - 0x010c8];
+
+/* 0x01100 */	u64	vplane_assignments;
+#define	VXGE_HAL_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val)	vBIT(val, 3, 5)
+/* 0x01108 */	u64	vpath_assignments;
+#define	VXGE_HAL_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val)	vBIT(val, 0, 17)
+/* 0x01110 */	u64	resource_assignments;
+#define	VXGE_HAL_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val)	vBIT(val, 0, 17)
+/* 0x01118 */	u64	host_type_assignments;
+#define	VXGE_HAL_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val)\
+								vBIT(val, 5, 3)
+/* 0x01120 */	u64	debug_assignments;
+#define	VXGE_HAL_DEBUG_ASSIGNMENTS_VHLABEL(val)			vBIT(val, 3, 5)
+#define	VXGE_HAL_DEBUG_ASSIGNMENTS_VPLANE(val)			vBIT(val, 11, 5)
+#define	VXGE_HAL_DEBUG_ASSIGNMENTS_FUNC(val)			vBIT(val, 19, 5)
+
+/* 0x01128 */	u64	max_resource_assignments;
+#define	VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val)	vBIT(val, 3, 5)
+#define	VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val)	vBIT(val, 11, 5)
+/* 0x01130 */	u64	pf_vpath_assignments;
+#define	VXGE_HAL_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val)	vBIT(val, 0, 17)
+	u8	unused01200[0x01200 - 0x01138];
+
+/* 0x01200 */	u64	rts_access_icmp;
+#define	VXGE_HAL_RTS_ACCESS_ICMP_EN(val)	vBIT(val, 0, 17)
+/* 0x01208 */	u64	rts_access_tcpsyn;
+#define	VXGE_HAL_RTS_ACCESS_TCPSYN_EN(val)	vBIT(val, 0, 17)
+/* 0x01210 */	u64	rts_access_zl4pyld;
+#define	VXGE_HAL_RTS_ACCESS_ZL4PYLD_EN(val)	vBIT(val, 0, 17)
+/* 0x01218 */	u64	rts_access_l4prtcl_tcp;
+#define	VXGE_HAL_RTS_ACCESS_L4PRTCL_TCP_EN(val)	vBIT(val, 0, 17)
+/* 0x01220 */	u64	rts_access_l4prtcl_udp;
+#define	VXGE_HAL_RTS_ACCESS_L4PRTCL_UDP_EN(val)	vBIT(val, 0, 17)
+/* 0x01228 */	u64	rts_access_l4prtcl_flex;
+#define	VXGE_HAL_RTS_ACCESS_L4PRTCL_FLEX_EN(val)	vBIT(val, 0, 17)
+/* 0x01230 */	u64	rts_access_ipfrag;
+#define	VXGE_HAL_RTS_ACCESS_IPFRAG_EN(val)	vBIT(val, 0, 17)
+
+	u8	unused01238[0x01248 - 0x01238];
+
+} vxge_hal_common_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_COMMON_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-config-priv.h b/sys/dev/vxge/vxgehal/vxgehal-config-priv.h
new file mode 100644
index 000000000000..f593358654d5
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-config-priv.h
@@ -0,0 +1,96 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	XGEHAL_CONFIG_PRIV_H
+#define	XGEHAL_CONFIG_PRIV_H
+
+__EXTERN_BEGIN_DECLS
+
+vxge_hal_status_e
+vxge_hal_driver_config_check(vxge_hal_driver_config_t *config);
+
+vxge_hal_status_e
+__hal_device_mac_config_check(vxge_hal_mac_config_t *mac_config);
+
+vxge_hal_status_e
+__hal_vpath_qos_config_check(vxge_hal_vpath_qos_config_t *config);
+
+vxge_hal_status_e
+__hal_mrpcim_config_check(vxge_hal_mrpcim_config_t *config);
+
+vxge_hal_status_e
+__hal_device_ring_config_check(vxge_hal_ring_config_t *ring_config);
+
+vxge_hal_status_e
+__hal_device_fifo_config_check(vxge_hal_fifo_config_t *fifo_config);
+
+vxge_hal_status_e
+__hal_device_lag_config_check(vxge_hal_lag_config_t *lag_config);
+
+vxge_hal_status_e
+__hal_device_lag_port_config_check(vxge_hal_lag_port_config_t *port_config);
+
+vxge_hal_status_e
+__hal_device_lag_aggr_config_check(vxge_hal_lag_aggr_config_t *aggr_config);
+
+vxge_hal_status_e
+__hal_device_lag_la_config_check(vxge_hal_lag_la_config_t *la_config);
+
+vxge_hal_status_e
+__hal_device_lag_ap_config_check(vxge_hal_lag_ap_config_t *ap_config);
+
+vxge_hal_status_e
+__hal_device_lag_sl_config_check(vxge_hal_lag_sl_config_t *sl_config);
+
+vxge_hal_status_e
+__hal_device_lag_lacp_config_check(vxge_hal_lag_lacp_config_t *lacp_config);
+
+vxge_hal_status_e
+__hal_device_wire_port_config_check(vxge_hal_wire_port_config_t *port_config);
+
+vxge_hal_status_e
+__hal_device_switch_port_config_check(
+    vxge_hal_switch_port_config_t *port_config);
+
+
+vxge_hal_status_e
+__hal_device_tim_intr_config_check(vxge_hal_tim_intr_config_t *tim_intr_config);
+
+vxge_hal_status_e
+__hal_device_vpath_config_check(vxge_hal_vp_config_t *vp_config);
+
+vxge_hal_status_e
+__hal_device_config_check(vxge_hal_device_config_t *new_config);
+
+__EXTERN_END_DECLS
+
+#endif	/* XGEHAL_CONFIG_PRIV_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-config.c b/sys/dev/vxge/vxgehal/vxgehal-config.c
new file mode 100644
index 000000000000..4c0d6b7c7809
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-config.c
@@ -0,0 +1,2932 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * vxge_hal_driver_config_check - Check driver configuration.
+ * @config: Driver configuration information
+ *
+ * Check the driver configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_driver_config_check(vxge_hal_driver_config_t *config)
+{
+	if (config->level > VXGE_TRACE)
+		return (VXGE_HAL_BADCFG_LOG_LEVEL);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_wire_port_config_check - Check wire port configuration.
+ * @port_config: Port configuration information
+ *
+ * Check wire port configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_wire_port_config_check(vxge_hal_wire_port_config_t *port_config)
+{
+	if (port_config->port_id > VXGE_HAL_WIRE_PORT_MAX_PORTS)
+		return (VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID);
+
+	if ((port_config->media > VXGE_HAL_WIRE_PORT_MAX_MEDIA) &&
+	    (port_config->media != VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA);
+
+	if (((port_config->mtu < VXGE_HAL_WIRE_PORT_MIN_INITIAL_MTU) ||
+	    (port_config->mtu > VXGE_HAL_WIRE_PORT_MAX_INITIAL_MTU)) &&
+	    (port_config->mtu != VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU);
+
+	if ((port_config->autoneg_mode >
+	    VXGE_HAL_WIRE_PORT_AUTONEG_MODE_RESERVED) &&
+	    (port_config->autoneg_mode !=
+	    VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE);
+
+	if ((port_config->autoneg_rate >
+	    VXGE_HAL_WIRE_PORT_AUTONEG_RATE_10G) &&
+	    (port_config->autoneg_rate !=
+	    VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE);
+
+	if ((port_config->fixed_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_PROCESSOR) &&
+	    (port_config->fixed_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_HW) &&
+	    (port_config->fixed_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM);
+
+	if ((port_config->antp_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_PROCESSOR) &&
+	    (port_config->antp_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_HW) &&
+	    (port_config->antp_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM);
+
+	if ((port_config->anbe_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_PROCESSOR) &&
+	    (port_config->anbe_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_HW) &&
+	    (port_config->anbe_use_fsm !=
+	    VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM);
+
+	if ((port_config->link_stability_period >
+	    VXGE_HAL_WIRE_PORT_MAX_LINK_STABILITY_PERIOD) &&
+	    (port_config->link_stability_period !=
+	    VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD);
+
+	if ((port_config->port_stability_period >
+	    VXGE_HAL_WIRE_PORT_MAX_PORT_STABILITY_PERIOD) &&
+	    (port_config->port_stability_period !=
+	    VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD);
+
+	if ((port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_ENABLE) &&
+	    (port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_DISABLE) &&
+	    (port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN);
+
+	if ((port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_ENABLE) &&
+	    (port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_DISABLE) &&
+	    (port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN);
+
+	if ((port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_NO_PAD) &&
+	    (port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_64B_PAD) &&
+	    (port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD);
+
+	if ((port_config->tmac_pad_byte >
+	    VXGE_HAL_WIRE_PORT_MAX_TMAC_PAD_BYTE) &&
+	    (port_config->tmac_pad_byte !=
+	    VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE);
+
+	if ((port_config->tmac_util_period >
+	    VXGE_HAL_WIRE_PORT_MAX_TMAC_UTIL_PERIOD) &&
+	    (port_config->tmac_util_period !=
+	    VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD);
+
+	if ((port_config->rmac_strip_fcs !=
+	    VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS) &&
+	    (port_config->rmac_strip_fcs !=
+	    VXGE_HAL_WIRE_PORT_RMAC_SEND_FCS_TO_HOST) &&
+	    (port_config->rmac_strip_fcs !=
+	    VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS);
+
+	if ((port_config->rmac_prom_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_ENABLE) &&
+	    (port_config->rmac_prom_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DISABLE) &&
+	    (port_config->rmac_prom_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN);
+
+	if ((port_config->rmac_discard_pfrm !=
+	    VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM) &&
+	    (port_config->rmac_discard_pfrm !=
+	    VXGE_HAL_WIRE_PORT_RMAC_SEND_PFRM_TO_HOST) &&
+	    (port_config->rmac_discard_pfrm !=
+	    VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM);
+
+	if ((port_config->rmac_util_period >
+	    VXGE_HAL_WIRE_PORT_MAX_RMAC_UTIL_PERIOD) &&
+	    (port_config->rmac_util_period !=
+	    VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD);
+
+	if ((port_config->rmac_pause_gen_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_ENABLE) &&
+	    (port_config->rmac_pause_gen_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DISABLE) &&
+	    (port_config->rmac_pause_gen_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN);
+
+	if ((port_config->rmac_pause_rcv_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_ENABLE) &&
+	    (port_config->rmac_pause_rcv_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DISABLE) &&
+	    (port_config->rmac_pause_rcv_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN);
+
+	if (((port_config->rmac_pause_time <
+	    VXGE_HAL_WIRE_PORT_MIN_RMAC_HIGH_PTIME) ||
+	    (port_config->rmac_pause_time >
+	    VXGE_HAL_WIRE_PORT_MAX_RMAC_HIGH_PTIME)) &&
+	    (port_config->rmac_pause_time !=
+	    VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME);
+
+	if ((port_config->limiter_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_ENABLE) &&
+	    (port_config->limiter_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DISABLE) &&
+	    (port_config->limiter_en !=
+	    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN);
+
+	if ((port_config->max_limit > VXGE_HAL_WIRE_PORT_MAX_RMAC_MAX_LIMIT) &&
+	    (port_config->max_limit != VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT))
+		return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT);
+
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * __hal_device_switch_port_config_check - Check switch port configuration.
+ * @port_config: Port configuration information
+ *
+ * Check switch port configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_switch_port_config_check(
+    vxge_hal_switch_port_config_t *port_config)
+{
+	if (((port_config->mtu < VXGE_HAL_SWITCH_PORT_MIN_INITIAL_MTU) ||
+	    (port_config->mtu > VXGE_HAL_SWITCH_PORT_MAX_INITIAL_MTU)) &&
+	    (port_config->mtu != VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU);
+
+	if ((port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_ENABLE) &&
+	    (port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_DISABLE) &&
+	    (port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN);
+
+	if ((port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_ENABLE) &&
+	    (port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_DISABLE) &&
+	    (port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN);
+
+	if ((port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_NO_PAD) &&
+	    (port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_64B_PAD) &&
+	    (port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD);
+
+	if ((port_config->tmac_pad_byte >
+	    VXGE_HAL_SWITCH_PORT_MAX_TMAC_PAD_BYTE) &&
+	    (port_config->tmac_pad_byte !=
+	    VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE);
+
+	if ((port_config->tmac_util_period >
+	    VXGE_HAL_SWITCH_PORT_MAX_TMAC_UTIL_PERIOD) &&
+	    (port_config->tmac_util_period !=
+	    VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD);
+
+	if ((port_config->rmac_strip_fcs !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS) &&
+	    (port_config->rmac_strip_fcs !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_SEND_FCS_TO_HOST) &&
+	    (port_config->rmac_strip_fcs !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS);
+
+	if ((port_config->rmac_prom_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_ENABLE) &&
+	    (port_config->rmac_prom_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DISABLE) &&
+	    (port_config->rmac_prom_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN);
+
+	if ((port_config->rmac_discard_pfrm !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM) &&
+	    (port_config->rmac_discard_pfrm !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_SEND_PFRM_TO_HOST) &&
+	    (port_config->rmac_discard_pfrm !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM);
+
+	if ((port_config->rmac_util_period >
+	    VXGE_HAL_SWITCH_PORT_MAX_RMAC_UTIL_PERIOD) &&
+	    (port_config->rmac_util_period !=
+	    VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD);
+
+	if ((port_config->rmac_pause_gen_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_ENABLE) &&
+	    (port_config->rmac_pause_gen_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DISABLE) &&
+	    (port_config->rmac_pause_gen_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN);
+
+	if ((port_config->rmac_pause_rcv_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_ENABLE) &&
+	    (port_config->rmac_pause_rcv_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DISABLE) &&
+	    (port_config->rmac_pause_rcv_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN);
+
+	if (((port_config->rmac_pause_time <
+	    VXGE_HAL_SWITCH_PORT_MIN_RMAC_HIGH_PTIME) ||
+	    (port_config->rmac_pause_time >
+	    VXGE_HAL_SWITCH_PORT_MAX_RMAC_HIGH_PTIME)) &&
+	    (port_config->rmac_pause_time !=
+	    VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME);
+
+	if ((port_config->limiter_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_ENABLE) &&
+	    (port_config->limiter_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DISABLE) &&
+	    (port_config->limiter_en !=
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN);
+
+	if ((port_config->max_limit >
+	    VXGE_HAL_SWITCH_PORT_MAX_RMAC_MAX_LIMIT) &&
+	    (port_config->max_limit !=
+	    VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT))
+		return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_mac_config_check - Check mac port configuration.
+ * @mac_config: MAC configuration information
+ *
+ * Check mac port configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_mac_config_check(vxge_hal_mac_config_t *mac_config)
+{
+	u32 i;
+	vxge_hal_status_e status;
+
+	status = __hal_device_wire_port_config_check(
+	    &mac_config->wire_port_config[0]);
+
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_wire_port_config_check(
+	    &mac_config->wire_port_config[1]);
+
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_switch_port_config_check(
+	    &mac_config->switch_port_config);
+
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	if ((mac_config->network_stability_period >
+	    VXGE_HAL_MAC_MAX_NETWORK_STABILITY_PERIOD) &&
+	    (mac_config->network_stability_period !=
+	    VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD))
+		return (VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD);
+
+	for (i = 0; i < 16; i++) {
+
+		if ((mac_config->mc_pause_threshold[i] >
+		    VXGE_HAL_MAC_MAX_MC_PAUSE_THRESHOLD) &&
+		    (mac_config->mc_pause_threshold[i] !=
+		    VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD))
+			return (VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD);
+
+	}
+
+	if ((mac_config->tmac_perma_stop_en !=
+	    VXGE_HAL_MAC_TMAC_PERMA_STOP_ENABLE) &&
+	    (mac_config->tmac_perma_stop_en !=
+	    VXGE_HAL_MAC_TMAC_PERMA_STOP_DISABLE) &&
+	    (mac_config->tmac_perma_stop_en !=
+	    VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN);
+
+	if ((mac_config->tmac_tx_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_TX_SWITCH_ENABLE) &&
+	    (mac_config->tmac_tx_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_TX_SWITCH_DISABLE) &&
+	    (mac_config->tmac_tx_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS);
+
+	if ((mac_config->tmac_lossy_switch_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_ENABLE) &&
+	    (mac_config->tmac_lossy_switch_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DISABLE) &&
+	    (mac_config->tmac_lossy_switch_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN);
+
+	if ((mac_config->tmac_lossy_wire_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_WIRE_ENABLE) &&
+	    (mac_config->tmac_lossy_wire_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DISABLE) &&
+	    (mac_config->tmac_lossy_wire_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN);
+
+	if ((mac_config->tmac_bcast_to_wire_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DISABLE) &&
+	    (mac_config->tmac_bcast_to_wire_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_ENABLE) &&
+	    (mac_config->tmac_bcast_to_wire_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS);
+
+	if ((mac_config->tmac_bcast_to_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DISABLE) &&
+	    (mac_config->tmac_bcast_to_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_ENABLE) &&
+	    (mac_config->tmac_bcast_to_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS);
+
+	if ((mac_config->tmac_host_append_fcs_en !=
+	    VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_ENABLE) &&
+	    (mac_config->tmac_host_append_fcs_en !=
+	    VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DISABLE) &&
+	    (mac_config->tmac_host_append_fcs_en !=
+	    VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN);
+
+	if ((mac_config->tpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AB) &&
+	    (mac_config->tpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AA) &&
+	    (mac_config->tpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N);
+
+	if ((mac_config->tpa_ecc_enable_n !=
+	    VXGE_HAL_MAC_TPA_ECC_ENABLE_N_ENABLE) &&
+	    (mac_config->tpa_ecc_enable_n !=
+	    VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DISABLE) &&
+	    (mac_config->tpa_ecc_enable_n !=
+	    VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N);
+
+	if ((mac_config->rpa_ignore_frame_err !=
+	    VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_ENABLE) &&
+	    (mac_config->rpa_ignore_frame_err !=
+	    VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DISABLE) &&
+	    (mac_config->rpa_ignore_frame_err !=
+	    VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR);
+
+	if ((mac_config->rpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_ENABLE) &&
+	    (mac_config->rpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DISABLE) &&
+	    (mac_config->rpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N);
+
+	if ((mac_config->rpa_search_for_hao !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_ENABLE) &&
+	    (mac_config->rpa_search_for_hao !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DISABLE) &&
+	    (mac_config->rpa_search_for_hao !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO);
+
+	if ((mac_config->rpa_support_ipv6_mobile_hdrs !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_ENABLE) &&
+	    (mac_config->rpa_support_ipv6_mobile_hdrs !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DISABLE) &&
+	    (mac_config->rpa_support_ipv6_mobile_hdrs !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS);
+
+	if ((mac_config->rpa_ipv6_stop_searching !=
+	    VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING) &&
+	    (mac_config->rpa_ipv6_stop_searching !=
+	    VXGE_HAL_MAC_RPA_IPV6_DONT_STOP_SEARCHING) &&
+	    (mac_config->rpa_ipv6_stop_searching !=
+	    VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING);
+
+	if ((mac_config->rpa_no_ps_if_unknown !=
+	    VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_ENABLE) &&
+	    (mac_config->rpa_no_ps_if_unknown !=
+	    VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DISABLE) &&
+	    (mac_config->rpa_no_ps_if_unknown !=
+	    VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN);
+
+	if ((mac_config->rpa_search_for_etype !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_ENABLE) &&
+	    (mac_config->rpa_search_for_etype !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DISABLE) &&
+	    (mac_config->rpa_search_for_etype !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE);
+
+	if ((mac_config->rpa_repl_l4_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_ENABLE) &&
+	    (mac_config->rpa_repl_l4_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_DISABLE) &&
+	    (mac_config->rpa_repl_l4_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM);
+
+	if ((mac_config->rpa_repl_l3_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_ENABLE) &&
+	    (mac_config->rpa_repl_l3_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DISABLE) &&
+	    (mac_config->rpa_repl_l3_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF);
+
+	if ((mac_config->rpa_repl_l3_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_ENABLE) &&
+	    (mac_config->rpa_repl_l3_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_DISABLE) &&
+	    (mac_config->rpa_repl_l3_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM);
+
+	if ((mac_config->rpa_repl_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_ENABLE) &&
+	    (mac_config->rpa_repl_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DISABLE) &&
+	    (mac_config->rpa_repl_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH);
+
+	if ((mac_config->rpa_repl_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_ENABLE) &&
+	    (mac_config->rpa_repl_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DISABLE) &&
+	    (mac_config->rpa_repl_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH);
+
+	if ((mac_config->rpa_repl_ipv4_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_ENABLE) &&
+	    (mac_config->rpa_repl_ipv4_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DISABLE) &&
+	    (mac_config->rpa_repl_ipv4_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH);
+
+	if ((mac_config->rpa_repl_ipv6_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_ENABLE) &&
+	    (mac_config->rpa_repl_ipv6_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DISABLE) &&
+	    (mac_config->rpa_repl_ipv6_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH);
+
+	if ((mac_config->rpa_repl_l4_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_ENABLE) &&
+	    (mac_config->rpa_repl_l4_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DISABLE) &&
+	    (mac_config->rpa_repl_l4_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF);
+
+	if ((mac_config->rpa_repl_strip_vlan_tag !=
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE) &&
+	    (mac_config->rpa_repl_strip_vlan_tag !=
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE) &&
+	    (mac_config->rpa_repl_strip_vlan_tag !=
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT))
+		return (VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_port_config_check - Check LAG port configuration.
+ * @aggr_config: LAG port configuration information
+ *
+ * Check LAG port configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_port_config_check(vxge_hal_lag_port_config_t *port_config)
+{
+	if ((port_config->port_id != VXGE_HAL_LAG_PORT_PORT_ID_0) &&
+	    (port_config->port_id != VXGE_HAL_LAG_PORT_PORT_ID_1))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PORT_ID);
+
+	if ((port_config->lag_en !=
+	    VXGE_HAL_LAG_PORT_LAG_EN_DISABLE) &&
+	    (port_config->lag_en !=
+	    VXGE_HAL_LAG_PORT_LAG_EN_ENABLE) &&
+	    (port_config->lag_en !=
+	    VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_LAG_EN);
+
+	if ((port_config->discard_slow_proto !=
+	    VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DISABLE) &&
+	    (port_config->discard_slow_proto !=
+	    VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE) &&
+	    (port_config->discard_slow_proto !=
+	    VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO);
+
+	if ((port_config->host_chosen_aggr !=
+	    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_0) &&
+	    (port_config->host_chosen_aggr !=
+	    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1) &&
+	    (port_config->host_chosen_aggr !=
+	    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR);
+
+	if ((port_config->discard_unknown_slow_proto !=
+	    VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DISABLE) &&
+	    (port_config->discard_unknown_slow_proto !=
+	    VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE) &&
+	    (port_config->discard_unknown_slow_proto !=
+	    VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO);
+
+	if ((port_config->actor_port_num >
+	    VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_NUM) &&
+	    (port_config->actor_port_num !=
+	    VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM);
+
+	if ((port_config->actor_port_priority >
+	    VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_PRIORITY) &&
+	    (port_config->actor_port_priority !=
+	    VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY);
+
+	if ((port_config->actor_key_10g >
+	    VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_10G) &&
+	    (port_config->actor_key_10g !=
+	    VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G);
+
+	if ((port_config->actor_key_1g > VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_1G) &&
+	    (port_config->actor_key_1g != VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G);
+
+	if ((port_config->actor_lacp_activity !=
+	    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_PASSIVE) &&
+	    (port_config->actor_lacp_activity !=
+	    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE) &&
+	    (port_config->actor_lacp_activity !=
+	    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY);
+
+	if ((port_config->actor_lacp_timeout !=
+	    VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_LONG) &&
+	    (port_config->actor_lacp_timeout !=
+	    VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT) &&
+	    (port_config->actor_lacp_timeout !=
+	    VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT);
+
+	if ((port_config->actor_aggregation !=
+	    VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_INDIVIDUAL) &&
+	    (port_config->actor_aggregation !=
+	    VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE) &&
+	    (port_config->actor_aggregation !=
+	    VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION);
+
+	if ((port_config->actor_synchronization !=
+	    VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_OUT_OF_SYNC) &&
+	    (port_config->actor_synchronization !=
+	    VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC) &&
+	    (port_config->actor_synchronization !=
+	    VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION);
+
+	if ((port_config->actor_collecting !=
+	    VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DISABLE) &&
+	    (port_config->actor_collecting !=
+	    VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE) &&
+	    (port_config->actor_collecting !=
+	    VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING);
+
+	if ((port_config->actor_distributing !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE) &&
+	    (port_config->actor_distributing !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) &&
+	    (port_config->actor_distributing !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING);
+
+	if ((port_config->actor_distributing !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE) &&
+	    (port_config->actor_distributing !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) &&
+	    (port_config->actor_distributing !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING);
+
+	if ((port_config->actor_defaulted !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED) &&
+	    (port_config->actor_defaulted !=
+	    VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED) &&
+	    (port_config->actor_defaulted !=
+	    VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED);
+
+	if ((port_config->actor_expired !=
+	    VXGE_HAL_LAG_PORT_ACTOR_EXPIRED) &&
+	    (port_config->actor_expired !=
+	    VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED) &&
+	    (port_config->actor_expired !=
+	    VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED);
+
+	if ((port_config->partner_sys_pri >
+	    VXGE_HAL_LAG_PORT_MAX_PARTNER_SYS_PRI) &&
+	    (port_config->partner_sys_pri !=
+	    VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI);
+
+	if ((port_config->partner_key > VXGE_HAL_LAG_PORT_MAX_PARTNER_KEY) &&
+	    (port_config->partner_key != VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY);
+
+	if ((port_config->partner_port_num >
+	    VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_NUM) &&
+	    (port_config->partner_port_num !=
+	    VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM);
+
+	if ((port_config->partner_port_priority >
+	    VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_PRIORITY) &&
+	    (port_config->partner_port_priority !=
+	    VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY);
+
+	if ((port_config->partner_lacp_activity !=
+	    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_PASSIVE) &&
+	    (port_config->partner_lacp_activity !=
+	    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE) &&
+	    (port_config->partner_lacp_activity !=
+	    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY);
+
+	if ((port_config->partner_lacp_timeout !=
+	    VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_LONG) &&
+	    (port_config->partner_lacp_timeout !=
+	    VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT) &&
+	    (port_config->partner_lacp_timeout !=
+	    VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT);
+
+	if ((port_config->partner_aggregation !=
+	    VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_INDIVIDUAL) &&
+	    (port_config->partner_aggregation !=
+	    VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE) &&
+	    (port_config->partner_aggregation !=
+	    VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION);
+
+	if ((port_config->partner_synchronization !=
+	    VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_OUT_OF_SYNC) &&
+	    (port_config->partner_synchronization !=
+	    VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC) &&
+	    (port_config->partner_synchronization !=
+	    VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION);
+
+	if ((port_config->partner_collecting !=
+	    VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DISABLE) &&
+	    (port_config->partner_collecting !=
+	    VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE) &&
+	    (port_config->partner_collecting !=
+	    VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING);
+
+	if ((port_config->partner_distributing !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE) &&
+	    (port_config->partner_distributing !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) &&
+	    (port_config->partner_distributing !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING);
+
+	if ((port_config->partner_distributing !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE) &&
+	    (port_config->partner_distributing !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) &&
+	    (port_config->partner_distributing !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING);
+
+	if ((port_config->partner_defaulted !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED) &&
+	    (port_config->partner_defaulted !=
+	    VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED) &&
+	    (port_config->partner_defaulted !=
+	    VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED);
+
+	if ((port_config->partner_expired !=
+	    VXGE_HAL_LAG_PORT_PARTNER_EXPIRED) &&
+	    (port_config->partner_expired !=
+	    VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED) &&
+	    (port_config->partner_expired !=
+	    VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_aggr_config_check - Check aggregator configuration.
+ * @aggr_config: Aggregator configuration information
+ *
+ * Check aggregator configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_aggr_config_check(vxge_hal_lag_aggr_config_t *aggr_config)
+{
+	if ((aggr_config->aggr_id != VXGE_HAL_LAG_AGGR_AGGR_ID_1) &&
+	    (aggr_config->aggr_id != VXGE_HAL_LAG_AGGR_AGGR_ID_2))
+		return (VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID);
+
+	if ((aggr_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DISBALE) &&
+	    (aggr_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE) &&
+	    (aggr_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR);
+
+	if ((aggr_config->mac_addr_sel !=
+	    VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_0) &&
+	    (aggr_config->mac_addr_sel !=
+	    VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1) &&
+	    (aggr_config->mac_addr_sel !=
+	    VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL);
+
+	if ((aggr_config->admin_key > VXGE_HAL_LAG_AGGR_MAX_ADMIN_KEY) &&
+	    (aggr_config->admin_key != VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY))
+		return (VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_la_config_check
+ * Check LAG link aggregation mode configuration.
+ * @la_config: LAG configuration information
+ *
+ * Check LAG link aggregation mode configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_la_config_check(vxge_hal_lag_la_config_t *la_config)
+{
+	if ((la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_DISBALE) &&
+	    (la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_ENABLE) &&
+	    (la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_TX_DISCARD);
+
+	if ((la_config->distrib_alg_sel !=
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_VPATH) &&
+	    (la_config->distrib_alg_sel !=
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEST_MAC_ADDR) &&
+	    (la_config->distrib_alg_sel !=
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_MAC_ADDR) &&
+	    (la_config->distrib_alg_sel !=
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_BOTH_MAC_ADDR) &&
+	    (la_config->distrib_alg_sel !=
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL);
+
+	if ((la_config->distrib_remap_if_fail !=
+	    VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DISBALE) &&
+	    (la_config->distrib_remap_if_fail !=
+	    VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE) &&
+	    (la_config->distrib_remap_if_fail !=
+	    VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL);
+
+	if ((la_config->coll_max_delay > VXGE_HAL_LAG_MAX_COLL_MAX_DELAY) &&
+	    (la_config->coll_max_delay != VXGE_HAL_LAG_DEF_COLL_MAX_DELAY))
+		return (VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY);
+
+	if ((la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_DISBALE) &&
+	    (la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_ENABLE) &&
+	    (la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_RX_DISCARD);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_ap_config_check - Check LAG a/p mode configuration.
+ * @ap_config: LAG configuration information
+ *
+ * Check LAG a/p mode configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_ap_config_check(vxge_hal_lag_ap_config_t *ap_config)
+{
+	if ((ap_config->hot_standby !=
+	    VXGE_HAL_LAG_HOT_STANDBY_DISBALE_PORT) &&
+	    (ap_config->hot_standby !=
+	    VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT) &&
+	    (ap_config->hot_standby !=
+	    VXGE_HAL_LAG_HOT_STANDBY_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_HOT_STANDBY);
+
+	if ((ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_DISBALE) &&
+	    (ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_ENBALE) &&
+	    (ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LACP_DECIDES);
+
+	if ((ap_config->pref_active_port !=
+	    VXGE_HAL_LAG_PREF_ACTIVE_PORT_0) &&
+	    (ap_config->pref_active_port !=
+	    VXGE_HAL_LAG_PREF_ACTIVE_PORT_1) &&
+	    (ap_config->pref_active_port !=
+	    VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT);
+
+	if ((ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_DISBALE) &&
+	    (ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE) &&
+	    (ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK);
+
+	if ((ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_DISBALE) &&
+	    (ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_ENBALE) &&
+	    (ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_FAILBACK_EN);
+
+	if ((ap_config->cold_failover_timeout !=
+	    VXGE_HAL_LAG_MIN_COLD_FAILOVER_TIMEOUT) &&
+	    (ap_config->cold_failover_timeout !=
+	    VXGE_HAL_LAG_MAX_COLD_FAILOVER_TIMEOUT) &&
+	    (ap_config->cold_failover_timeout !=
+	    VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT))
+		return (VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT);
+
+	if ((ap_config->alt_admin_key !=
+	    VXGE_HAL_LAG_MIN_ALT_ADMIN_KEY) &&
+	    (ap_config->alt_admin_key !=
+	    VXGE_HAL_LAG_MAX_ALT_ADMIN_KEY) &&
+	    (ap_config->alt_admin_key !=
+	    VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY))
+		return (VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY);
+
+	if ((ap_config->alt_aggr !=
+	    VXGE_HAL_LAG_ALT_AGGR_0) &&
+	    (ap_config->alt_aggr !=
+	    VXGE_HAL_LAG_ALT_AGGR_1) &&
+	    (ap_config->alt_aggr !=
+	    VXGE_HAL_LAG_ALT_AGGR_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_ALT_AGGR);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_sl_config_check - Check LAG Single Link mode configuration.
+ * @sl_config: LAG configuration information
+ *
+ * Check LAG Single link mode configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_sl_config_check(vxge_hal_lag_sl_config_t *sl_config)
+{
+	if ((sl_config->pref_indiv_port !=
+	    VXGE_HAL_LAG_PREF_INDIV_PORT_0) &&
+	    (sl_config->pref_indiv_port !=
+	    VXGE_HAL_LAG_PREF_INDIV_PORT_1) &&
+	    (sl_config->pref_indiv_port !=
+	    VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_lacp_config_check - Check LACP configuration.
+ * @lacp_config: LAG configuration information
+ *
+ * Check LACP configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_lacp_config_check(vxge_hal_lag_lacp_config_t *lacp_config)
+{
+	if ((lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_DISBALE) &&
+	    (lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_ENABLE) &&
+	    (lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LACP_EN);
+
+	if ((lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_NORMAL) &&
+	    (lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_RESET) &&
+	    (lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LACP_BEGIN);
+
+	if ((lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_DISBALE) &&
+	    (lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_ENABLE) &&
+	    (lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_DISCARD_LACP);
+
+	if ((lacp_config->liberal_len_chk !=
+	    VXGE_HAL_LAG_LIBERAL_LEN_CHK_DISBALE) &&
+	    (lacp_config->liberal_len_chk !=
+	    VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE) &&
+	    (lacp_config->liberal_len_chk !=
+	    VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK);
+
+	if ((lacp_config->marker_gen_recv_en !=
+	    VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DISBALE) &&
+	    (lacp_config->marker_gen_recv_en !=
+	    VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE) &&
+	    (lacp_config->marker_gen_recv_en !=
+	    VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN);
+
+	if ((lacp_config->marker_resp_en !=
+	    VXGE_HAL_LAG_MARKER_RESP_EN_DISBALE) &&
+	    (lacp_config->marker_resp_en !=
+	    VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE) &&
+	    (lacp_config->marker_resp_en !=
+	    VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN);
+
+	if ((lacp_config->marker_resp_timeout !=
+	    VXGE_HAL_LAG_MIN_MARKER_RESP_TIMEOUT) &&
+	    (lacp_config->marker_resp_timeout !=
+	    VXGE_HAL_LAG_MAX_MARKER_RESP_TIMEOUT) &&
+	    (lacp_config->marker_resp_timeout !=
+	    VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT))
+		return (VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT);
+
+	if ((lacp_config->slow_proto_mrkr_min_interval !=
+	    VXGE_HAL_LAG_MIN_SLOW_PROTO_MRKR_MIN_INTERVAL) &&
+	    (lacp_config->slow_proto_mrkr_min_interval !=
+	    VXGE_HAL_LAG_MAX_SLOW_PROTO_MRKR_MIN_INTERVAL) &&
+	    (lacp_config->slow_proto_mrkr_min_interval !=
+	    VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL))
+		return (VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL);
+
+	if ((lacp_config->throttle_mrkr_resp !=
+	    VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DISBALE) &&
+	    (lacp_config->throttle_mrkr_resp !=
+	    VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE) &&
+	    (lacp_config->throttle_mrkr_resp !=
+	    VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_lag_config_check - Check link aggregation configuration.
+ * @lag_config: LAG configuration information
+ *
+ * Check link aggregation configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_lag_config_check(vxge_hal_lag_config_t *lag_config)
+{
+	u32 i;
+	vxge_hal_status_e status;
+
+	if ((lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_DISABLE) &&
+	    (lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_ENABLE) &&
+	    (lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LAG_EN);
+
+	if ((lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_LAG) &&
+	    (lag_config->lag_mode !=
+	    VXGE_HAL_LAG_LAG_MODE_ACTIVE_PASSIVE_FAILOVER) &&
+	    (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_SINGLE_LINK) &&
+	    (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LAG_MODE);
+
+	status = __hal_device_lag_la_config_check(&lag_config->la_mode_config);
+	if (status == VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_lag_ap_config_check(&lag_config->ap_mode_config);
+	if (status == VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_lag_sl_config_check(&lag_config->sl_mode_config);
+	if (status == VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_lag_lacp_config_check(&lag_config->lacp_config);
+	if (status == VXGE_HAL_OK)
+		return (status);
+
+	if ((lag_config->incr_tx_aggr_stats !=
+	    VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DISBALE) &&
+	    (lag_config->incr_tx_aggr_stats !=
+	    VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE) &&
+	    (lag_config->incr_tx_aggr_stats !=
+	    VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS);
+
+	for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) {
+
+		if ((status = __hal_device_lag_port_config_check(
+		    &lag_config->port_config[i])) != VXGE_HAL_OK)
+			return (status);
+
+	}
+
+	for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) {
+
+		if ((status = __hal_device_lag_aggr_config_check(
+		    &lag_config->aggr_config[i])) != VXGE_HAL_OK)
+			return (status);
+
+	}
+
+	if ((lag_config->sys_pri > VXGE_HAL_LAG_MAX_SYS_PRI) &&
+	    (lag_config->sys_pri != VXGE_HAL_LAG_DEF_SYS_PRI))
+		return (VXGE_HAL_BADCFG_LAG_SYS_PRI);
+
+	if ((lag_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DISBALE) &&
+	    (lag_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE) &&
+	    (lag_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR);
+
+	if ((lag_config->mac_addr_sel !=
+	    VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_0) &&
+	    (lag_config->mac_addr_sel !=
+	    VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1) &&
+	    (lag_config->mac_addr_sel !=
+	    VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL);
+
+	if ((lag_config->fast_per_time > VXGE_HAL_LAG_MAX_FAST_PER_TIME) &&
+	    (lag_config->fast_per_time != VXGE_HAL_LAG_DEF_FAST_PER_TIME))
+		return (VXGE_HAL_BADCFG_LAG_FAST_PER_TIME);
+
+	if ((lag_config->slow_per_time > VXGE_HAL_LAG_MAX_SLOW_PER_TIME) &&
+	    (lag_config->slow_per_time != VXGE_HAL_LAG_DEF_SLOW_PER_TIME))
+		return (VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME);
+
+	if ((lag_config->short_timeout > VXGE_HAL_LAG_MAX_SHORT_TIMEOUT) &&
+	    (lag_config->short_timeout != VXGE_HAL_LAG_DEF_SHORT_TIMEOUT))
+		return (VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT);
+
+	if ((lag_config->long_timeout > VXGE_HAL_LAG_MAX_LONG_TIMEOUT) &&
+	    (lag_config->long_timeout != VXGE_HAL_LAG_DEF_LONG_TIMEOUT))
+		return (VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT);
+
+	if ((lag_config->churn_det_time > VXGE_HAL_LAG_MAX_CHURN_DET_TIME) &&
+	    (lag_config->churn_det_time != VXGE_HAL_LAG_DEF_CHURN_DET_TIME))
+		return (VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME);
+
+	if ((lag_config->aggr_wait_time > VXGE_HAL_LAG_MAX_AGGR_WAIT_TIME) &&
+	    (lag_config->aggr_wait_time != VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME))
+		return (VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME);
+
+	if ((lag_config->short_timer_scale !=
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_1X) &&
+	    (lag_config->short_timer_scale !=
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_10X) &&
+	    (lag_config->short_timer_scale !=
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_100X) &&
+	    (lag_config->short_timer_scale !=
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_1000X) &&
+	    (lag_config->short_timer_scale !=
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE);
+
+	if ((lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_1X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_10X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_100X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_1000X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_10000X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_100000X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_1000000X) &&
+	    (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT))
+		return (VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_qos_config_check - Check vpath QOS configuration.
+ * @config: Vpath QOS configuration information
+ *
+ * Check the vpath QOS configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_qos_config_check(vxge_hal_vpath_qos_config_t *config)
+{
+	if ((config->priority > VXGE_HAL_VPATH_QOS_PRIORITY_MAX) &&
+	    (config->priority != VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT))
+		return (VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY);
+
+	if ((config->min_bandwidth >
+	    VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MAX) &&
+	    (config->min_bandwidth !=
+	    VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT))
+		return (VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH);
+
+	if ((config->max_bandwidth >
+	    VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MAX) &&
+	    (config->max_bandwidth !=
+	    VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT))
+		return (VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_mrpcim_config_check - Check mrpcim configuration.
+ * @config: mrpcim configuration information
+ *
+ * Check the mrpcim configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_mrpcim_config_check(vxge_hal_mrpcim_config_t *config)
+{
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	if ((status = __hal_device_mac_config_check(&config->mac_config)) !=
+	    VXGE_HAL_OK)
+		return (status);
+
+	if ((status = __hal_device_lag_config_check(&config->lag_config)) !=
+	    VXGE_HAL_OK)
+		return (status);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if ((status = __hal_vpath_qos_config_check(
+		    &config->vp_qos[i])) != VXGE_HAL_OK)
+			return (status);
+
+	}
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_ring_config_check - Check ring configuration.
+ * @ring_config: Device configuration information
+ *
+ * Check the ring configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_ring_config_check(vxge_hal_ring_config_t *ring_config)
+{
+	if ((ring_config->enable != VXGE_HAL_RING_ENABLE) &&
+	    (ring_config->enable != VXGE_HAL_RING_DISABLE))
+		return (VXGE_HAL_BADCFG_RING_ENABLE);
+
+	if ((ring_config->ring_length < VXGE_HAL_MIN_RING_LENGTH) ||
+	    (ring_config->ring_length > VXGE_HAL_MAX_RING_LENGTH))
+		return (VXGE_HAL_BADCFG_RING_LENGTH);
+
+	if ((ring_config->buffer_mode < VXGE_HAL_RING_RXD_BUFFER_MODE_1) ||
+	    (ring_config->buffer_mode > VXGE_HAL_RING_RXD_BUFFER_MODE_5))
+		return (VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE);
+
+	if ((ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_A) &&
+	    (ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_B) &&
+	    (ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_C) &&
+	    (ring_config->scatter_mode !=
+	    VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_RING_SCATTER_MODE);
+
+	if ((ring_config->post_mode != VXGE_HAL_RING_POST_MODE_LEGACY) &&
+	    (ring_config->post_mode != VXGE_HAL_RING_POST_MODE_DOORBELL) &&
+	    (ring_config->post_mode !=
+	    VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_RING_POST_MODE);
+
+	if ((ring_config->max_frm_len > VXGE_HAL_MAX_RING_MAX_FRM_LEN) &&
+	    (ring_config->max_frm_len != VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU))
+		return (VXGE_HAL_BADCFG_RING_MAX_FRM_LEN);
+
+	if ((ring_config->no_snoop_bits > VXGE_HAL_RING_NO_SNOOP_ALL) &&
+	    (ring_config->no_snoop_bits !=
+	    VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL);
+
+	if ((ring_config->rx_timer_val > VXGE_HAL_RING_MAX_RX_TIMER_VAL) &&
+	    (ring_config->rx_timer_val !=
+	    VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL))
+		return (VXGE_HAL_BADCFG_RING_TIMER_VAL);
+
+	if ((ring_config->greedy_return !=
+	    VXGE_HAL_RING_GREEDY_RETURN_ENABLE) &&
+	    (ring_config->greedy_return !=
+	    VXGE_HAL_RING_GREEDY_RETURN_DISABLE) &&
+	    (ring_config->greedy_return !=
+	    VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_RING_GREEDY_RETURN);
+
+	if ((ring_config->rx_timer_ci !=
+	    VXGE_HAL_RING_RX_TIMER_CI_ENABLE) &&
+	    (ring_config->rx_timer_ci !=
+	    VXGE_HAL_RING_RX_TIMER_CI_DISABLE) &&
+	    (ring_config->rx_timer_ci !=
+	    VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_RING_TIMER_CI);
+
+	if (((ring_config->backoff_interval_us <
+	    VXGE_HAL_MIN_BACKOFF_INTERVAL_US) ||
+	    (ring_config->backoff_interval_us >
+	    VXGE_HAL_MAX_BACKOFF_INTERVAL_US)) &&
+	    (ring_config->backoff_interval_us !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US))
+		return (VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US);
+
+	if ((ring_config->indicate_max_pkts <
+	    VXGE_HAL_MIN_RING_INDICATE_MAX_PKTS) ||
+	    (ring_config->indicate_max_pkts >
+	    VXGE_HAL_MAX_RING_INDICATE_MAX_PKTS))
+		return (VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_fifo_config_check - Check fifo configuration.
+ * @fifo_config: Fifo configuration information
+ *
+ * Check the fifo configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_fifo_config_check(vxge_hal_fifo_config_t *fifo_config)
+{
+	if ((fifo_config->enable != VXGE_HAL_FIFO_ENABLE) &&
+	    (fifo_config->enable != VXGE_HAL_FIFO_DISABLE))
+		return (VXGE_HAL_BADCFG_FIFO_ENABLE);
+
+	if ((fifo_config->fifo_length < VXGE_HAL_MIN_FIFO_LENGTH) ||
+	    (fifo_config->fifo_length > VXGE_HAL_MAX_FIFO_LENGTH))
+		return (VXGE_HAL_BADCFG_FIFO_LENGTH);
+
+	if ((fifo_config->max_frags < VXGE_HAL_MIN_FIFO_FRAGS) ||
+	    (fifo_config->max_frags > VXGE_HAL_MAX_FIFO_FRAGS))
+		return (VXGE_HAL_BADCFG_FIFO_FRAGS);
+
+	if (fifo_config->alignment_size > VXGE_HAL_MAX_FIFO_ALIGNMENT_SIZE)
+		return (VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE);
+
+	if (fifo_config->max_aligned_frags > fifo_config->max_frags)
+		return (VXGE_HAL_BADCFG_FIFO_MAX_FRAGS);
+
+	if ((fifo_config->intr != VXGE_HAL_FIFO_QUEUE_INTR_ENABLE) &&
+	    (fifo_config->intr != VXGE_HAL_FIFO_QUEUE_INTR_DISABLE))
+		return (VXGE_HAL_BADCFG_FIFO_QUEUE_INTR);
+
+	if (fifo_config->no_snoop_bits > VXGE_HAL_FIFO_NO_SNOOP_ALL)
+		return (VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL);
+
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * __hal_device_tim_intr_config_check - Check tim intr configuration.
+ * @tim_intr_config: tim intr configuration information
+ *
+ * Check the tim intr configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_tim_intr_config_check(vxge_hal_tim_intr_config_t *tim_intr_config)
+{
+	if ((tim_intr_config->intr_enable != VXGE_HAL_TIM_INTR_ENABLE) &&
+	    (tim_intr_config->intr_enable != VXGE_HAL_TIM_INTR_DISABLE))
+		return (VXGE_HAL_BADCFG_TIM_INTR_ENABLE);
+
+	if ((tim_intr_config->btimer_val >
+	    VXGE_HAL_MAX_TIM_BTIMER_VAL) &&
+	    (tim_intr_config->btimer_val !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL))
+		return (VXGE_HAL_BADCFG_TIM_BTIMER_VAL);
+
+	if ((tim_intr_config->timer_ac_en !=
+	    VXGE_HAL_TIM_TIMER_AC_ENABLE) &&
+	    (tim_intr_config->timer_ac_en !=
+	    VXGE_HAL_TIM_TIMER_AC_DISABLE) &&
+	    (tim_intr_config->timer_ac_en !=
+	    VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_TIM_TIMER_AC_EN);
+
+	if ((tim_intr_config->timer_ci_en !=
+	    VXGE_HAL_TIM_TIMER_CI_ENABLE) &&
+	    (tim_intr_config->timer_ci_en !=
+	    VXGE_HAL_TIM_TIMER_CI_DISABLE) &&
+	    (tim_intr_config->timer_ci_en !=
+	    VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_TIM_TIMER_CI_EN);
+
+	if ((tim_intr_config->timer_ri_en !=
+	    VXGE_HAL_TIM_TIMER_RI_ENABLE) &&
+	    (tim_intr_config->timer_ri_en !=
+	    VXGE_HAL_TIM_TIMER_RI_DISABLE) &&
+	    (tim_intr_config->timer_ri_en !=
+	    VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_TIM_TIMER_RI_EN);
+
+	if ((tim_intr_config->rtimer_event_sf >
+	    VXGE_HAL_MAX_TIM_RTIMER_EVENT_SF) &&
+	    (tim_intr_config->rtimer_event_sf !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF))
+		return (VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF);
+
+	if ((tim_intr_config->rtimer_val >
+	    VXGE_HAL_MAX_TIM_RTIMER_VAL) &&
+	    (tim_intr_config->rtimer_val !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL))
+		return (VXGE_HAL_BADCFG_TIM_RTIMER_VAL);
+
+	if ((((tim_intr_config->util_sel > 19) &&
+	    (tim_intr_config->util_sel < 32)) ||
+	    ((tim_intr_config->util_sel > 48) &&
+	    (tim_intr_config->util_sel < 63))) &&
+	    (tim_intr_config->util_sel !=
+	    VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_TIM_UTIL_SEL);
+
+	if ((tim_intr_config->ltimer_val >
+	    VXGE_HAL_MAX_TIM_LTIMER_VAL) &&
+	    (tim_intr_config->ltimer_val !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL))
+		return (VXGE_HAL_BADCFG_TIM_LTIMER_VAL);
+
+	if ((tim_intr_config->txfrm_cnt_en !=
+	    VXGE_HAL_TXFRM_CNT_EN_ENABLE) &&
+	    (tim_intr_config->txfrm_cnt_en !=
+	    VXGE_HAL_TXFRM_CNT_EN_DISABLE) &&
+	    (tim_intr_config->txfrm_cnt_en !=
+	    VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_TXFRM_CNT_EN);
+
+	if ((tim_intr_config->txd_cnt_en !=
+	    VXGE_HAL_TXD_CNT_EN_ENABLE) &&
+	    (tim_intr_config->txd_cnt_en !=
+	    VXGE_HAL_TXD_CNT_EN_DISABLE) &&
+	    (tim_intr_config->txd_cnt_en !=
+	    VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_TXD_CNT_EN);
+
+	if ((tim_intr_config->urange_a >
+	    VXGE_HAL_MAX_TIM_URANGE_A) &&
+	    (tim_intr_config->urange_a !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A))
+		return (VXGE_HAL_BADCFG_TIM_URANGE_A);
+
+	if ((tim_intr_config->uec_a >
+	    VXGE_HAL_MAX_TIM_UEC_A) &&
+	    (tim_intr_config->uec_a !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A))
+		return (VXGE_HAL_BADCFG_TIM_UEC_A);
+
+	if ((tim_intr_config->urange_b >
+	    VXGE_HAL_MAX_TIM_URANGE_B) &&
+	    (tim_intr_config->urange_b !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B))
+		return (VXGE_HAL_BADCFG_TIM_URANGE_B);
+
+	if ((tim_intr_config->uec_b >
+	    VXGE_HAL_MAX_TIM_UEC_B) &&
+	    (tim_intr_config->uec_b !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B))
+		return (VXGE_HAL_BADCFG_TIM_UEC_B);
+
+	if ((tim_intr_config->urange_c >
+	    VXGE_HAL_MAX_TIM_URANGE_C) &&
+	    (tim_intr_config->urange_c !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C))
+		return (VXGE_HAL_BADCFG_TIM_URANGE_C);
+
+	if ((tim_intr_config->uec_c >
+	    VXGE_HAL_MAX_TIM_UEC_C) &&
+	    (tim_intr_config->uec_c !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C))
+		return (VXGE_HAL_BADCFG_TIM_UEC_C);
+
+	if ((tim_intr_config->uec_d >
+	    VXGE_HAL_MAX_TIM_UEC_D) &&
+	    (tim_intr_config->uec_d !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D))
+		return (VXGE_HAL_BADCFG_TIM_UEC_D);
+
+	if (((tim_intr_config->ufca_intr_thres <
+	    VXGE_HAL_MIN_UFCA_INTR_THRES) ||
+	    (tim_intr_config->ufca_intr_thres >
+	    VXGE_HAL_MAX_UFCA_INTR_THRES)) &&
+	    (tim_intr_config->ufca_intr_thres !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES))
+		return (VXGE_HAL_BADCFG_UFCA_INTR_THRES);
+
+	if (((tim_intr_config->ufca_lo_lim <
+	    VXGE_HAL_MIN_UFCA_LO_LIM) ||
+	    (tim_intr_config->ufca_lo_lim >
+	    VXGE_HAL_MAX_UFCA_LO_LIM)) &&
+	    (tim_intr_config->ufca_lo_lim !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM))
+		return (VXGE_HAL_BADCFG_UFCA_LO_LIM);
+
+	if (((tim_intr_config->ufca_hi_lim <
+	    VXGE_HAL_MIN_UFCA_HI_LIM) ||
+	    (tim_intr_config->ufca_hi_lim >
+	    VXGE_HAL_MAX_UFCA_HI_LIM)) &&
+	    (tim_intr_config->ufca_hi_lim !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM))
+		return (VXGE_HAL_BADCFG_UFCA_HI_LIM);
+
+	if (((tim_intr_config->ufca_lbolt_period <
+	    VXGE_HAL_MIN_UFCA_LBOLT_PERIOD) ||
+	    (tim_intr_config->ufca_lbolt_period >
+	    VXGE_HAL_MAX_UFCA_LBOLT_PERIOD)) &&
+	    (tim_intr_config->ufca_lbolt_period !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD))
+		return (VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_vpath_config_check - Check vpath configuration.
+ * @vp_config: Vpath configuration information
+ *
+ * Check the vpath configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_vpath_config_check(vxge_hal_vp_config_t *vp_config)
+{
+	vxge_hal_status_e status;
+
+	if (vp_config->vp_id > VXGE_HAL_MAX_VIRTUAL_PATHS)
+		return (VXGE_HAL_BADCFG_VPATH_ID);
+
+	if ((vp_config->wire_port != VXGE_HAL_VPATH_USE_PORT0) &&
+	    (vp_config->wire_port != VXGE_HAL_VPATH_USE_PORT1) &&
+	    (vp_config->wire_port != VXGE_HAL_VPATH_USE_BOTH) &&
+	    (vp_config->wire_port != VXGE_HAL_VPATH_USE_DEFAULT_PORT))
+		return (VXGE_HAL_BADCFG_VPATH_WIRE_PORT);
+
+	if ((vp_config->priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) &&
+	    (((int)vp_config->priority < VXGE_HAL_VPATH_PRIORITY_MIN) ||
+	    (vp_config->priority > VXGE_HAL_VPATH_PRIORITY_MAX)))
+		return (VXGE_HAL_BADCFG_VPATH_PRIORITY);
+
+	if ((vp_config->bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) &&
+	    ((vp_config->bandwidth < VXGE_HAL_VPATH_BW_LIMIT_MIN) ||
+	    (vp_config->bandwidth > VXGE_HAL_VPATH_BW_LIMIT_MAX)))
+		return (VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT);
+
+	if ((vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_ENABLE) &&
+	    (vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_DISABLE) &&
+	    (vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_VPATH_NO_SNOOP);
+
+	status = __hal_device_ring_config_check(&vp_config->ring);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_fifo_config_check(&vp_config->fifo);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+
+	status = __hal_device_tim_intr_config_check(&vp_config->tti);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	status = __hal_device_tim_intr_config_check(&vp_config->rti);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	if ((vp_config->mtu != VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
+	    ((vp_config->mtu < VXGE_HAL_VPATH_MIN_INITIAL_MTU) ||
+	    (vp_config->mtu > VXGE_HAL_VPATH_MAX_INITIAL_MTU)))
+		return (VXGE_HAL_BADCFG_VPATH_MTU);
+
+	if ((vp_config->tpa_lsov2_en !=
+	    VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT) &&
+	    (vp_config->tpa_lsov2_en !=
+	    VXGE_HAL_VPATH_TPA_LSOV2_EN_ENABLE) &&
+	    (vp_config->tpa_lsov2_en !=
+	    VXGE_HAL_VPATH_TPA_LSOV2_EN_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN);
+
+	if ((vp_config->tpa_ignore_frame_error !=
+	    VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT) &&
+	    (vp_config->tpa_ignore_frame_error !=
+	    VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_ENABLE) &&
+	    (vp_config->tpa_ignore_frame_error !=
+	    VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR);
+
+	if ((vp_config->tpa_ipv6_keep_searching !=
+	    VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) &&
+	    (vp_config->tpa_ipv6_keep_searching !=
+	    VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_ENABLE) &&
+	    (vp_config->tpa_ipv6_keep_searching !=
+	    VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING);
+
+	if ((vp_config->tpa_l4_pshdr_present !=
+	    VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT) &&
+	    (vp_config->tpa_l4_pshdr_present !=
+	    VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_ENABLE) &&
+	    (vp_config->tpa_l4_pshdr_present !=
+	    VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT);
+
+	if ((vp_config->tpa_support_mobile_ipv6_hdrs !=
+	    VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT) &&
+	    (vp_config->tpa_support_mobile_ipv6_hdrs !=
+	    VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_ENABLE) &&
+	    (vp_config->tpa_support_mobile_ipv6_hdrs !=
+	    VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS);
+
+	if ((vp_config->rpa_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_ENABLE) &&
+	    (vp_config->rpa_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH);
+
+	if ((vp_config->rpa_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_ENABLE) &&
+	    (vp_config->rpa_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH);
+
+	if ((vp_config->rpa_ipv4_udp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_ipv4_udp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_ENABLE) &&
+	    (vp_config->rpa_ipv4_udp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH);
+
+	if ((vp_config->rpa_ipv6_udp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_ipv6_udp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_ENABLE) &&
+	    (vp_config->rpa_ipv6_udp_incl_ph !=
+	    VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH);
+
+	if ((vp_config->rpa_l4_incl_cf !=
+	    VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_l4_incl_cf !=
+	    VXGE_HAL_VPATH_RPA_L4_INCL_CF_ENABLE) &&
+	    (vp_config->rpa_l4_incl_cf !=
+	    VXGE_HAL_VPATH_RPA_L4_INCL_CF_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF);
+
+	if ((vp_config->rpa_strip_vlan_tag !=
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_strip_vlan_tag !=
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
+	    (vp_config->rpa_strip_vlan_tag !=
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG);
+
+	if ((vp_config->rpa_l4_comp_csum !=
+	    VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_l4_comp_csum !=
+	    VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_ENABLE) &&
+	    (vp_config->rpa_l4_comp_csum !=
+	    VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM);
+
+	if ((vp_config->rpa_l3_incl_cf !=
+	    VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_l3_incl_cf !=
+	    VXGE_HAL_VPATH_RPA_L3_INCL_CF_ENABLE) &&
+	    (vp_config->rpa_l3_incl_cf !=
+	    VXGE_HAL_VPATH_RPA_L3_INCL_CF_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF);
+
+	if ((vp_config->rpa_l3_comp_csum !=
+	    VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_l3_comp_csum !=
+	    VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_ENABLE) &&
+	    (vp_config->rpa_l3_comp_csum !=
+	    VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM);
+
+	if ((vp_config->rpa_ucast_all_addr_en !=
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_ucast_all_addr_en !=
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE) &&
+	    (vp_config->rpa_ucast_all_addr_en !=
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN);
+
+	if ((vp_config->rpa_mcast_all_addr_en !=
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_mcast_all_addr_en !=
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE) &&
+	    (vp_config->rpa_mcast_all_addr_en !=
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN);
+
+	if ((vp_config->rpa_bcast_en !=
+	    VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_bcast_en !=
+	    VXGE_HAL_VPATH_RPA_BCAST_ENABLE) &&
+	    (vp_config->rpa_bcast_en !=
+	    VXGE_HAL_VPATH_RPA_BCAST_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN);
+
+	if ((vp_config->rpa_all_vid_en !=
+	    VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT) &&
+	    (vp_config->rpa_all_vid_en !=
+	    VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE) &&
+	    (vp_config->rpa_all_vid_en !=
+	    VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE))
+		return (VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN);
+
+	if ((vp_config->vp_queue_l2_flow !=
+	    VXGE_HAL_VPATH_VP_Q_L2_FLOW_ENABLE) &&
+	    (vp_config->vp_queue_l2_flow !=
+	    VXGE_HAL_VPATH_VP_Q_L2_FLOW_DISABLE) &&
+	    (vp_config->vp_queue_l2_flow !=
+	    VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT))
+		return (VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_config_check - Check device configuration.
+ * @new_config: Device configuration information
+ *
+ * Check the device configuration
+ *
+ * Returns: VXGE_HAL_OK - success,
+ * otherwise one of the vxge_hal_status_e {} enumerated error codes.
+ *
+ */
+vxge_hal_status_e
+__hal_device_config_check(vxge_hal_device_config_t *new_config)
+{
+	u32 i;
+	vxge_hal_status_e status;
+
+	if (new_config->dma_blockpool_incr <
+	    VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE)
+		return (VXGE_HAL_BADCFG_BLOCKPOOL_INCR);
+
+	if (new_config->dma_blockpool_max <
+	    VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE)
+		return (VXGE_HAL_BADCFG_BLOCKPOOL_MAX);
+
+	if ((status = __hal_mrpcim_config_check(&new_config->mrpcim_config)) !=
+	    VXGE_HAL_OK)
+		return (status);
+
+	if (new_config->isr_polling_cnt > VXGE_HAL_MAX_ISR_POLLING_CNT)
+		return (VXGE_HAL_BADCFG_ISR_POLLING_CNT);
+
+	if ((new_config->max_payload_size >
+	    VXGE_HAL_MAX_PAYLOAD_SIZE_4096) &&
+	    (new_config->max_payload_size !=
+	    VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE))
+		return (VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE);
+
+	if ((new_config->mmrb_count > VXGE_HAL_MMRB_COUNT_4096) &&
+	    (new_config->mmrb_count != VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT))
+		return (VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE);
+
+	if (((new_config->stats_refresh_time_sec <
+	    VXGE_HAL_MIN_STATS_REFRESH_TIME) ||
+	    (new_config->stats_refresh_time_sec >
+	    VXGE_HAL_MAX_STATS_REFRESH_TIME)) &&
+	    (new_config->stats_refresh_time_sec !=
+	    VXGE_HAL_STATS_REFRESH_DISABLE))
+		return (VXGE_HAL_BADCFG_STATS_REFRESH_TIME);
+
+	if ((new_config->intr_mode != VXGE_HAL_INTR_MODE_IRQLINE) &&
+	    (new_config->intr_mode != VXGE_HAL_INTR_MODE_MSIX) &&
+	    (new_config->intr_mode != VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) &&
+	    (new_config->intr_mode != VXGE_HAL_INTR_MODE_EMULATED_INTA) &&
+	    (new_config->intr_mode != VXGE_HAL_INTR_MODE_DEF))
+		return (VXGE_HAL_BADCFG_INTR_MODE);
+
+	if ((new_config->dump_on_unknown !=
+	    VXGE_HAL_DUMP_ON_UNKNOWN_DISABLE) &&
+	    (new_config->dump_on_unknown !=
+	    VXGE_HAL_DUMP_ON_UNKNOWN_ENABLE))
+		return (VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN);
+
+	if ((new_config->dump_on_serr != VXGE_HAL_DUMP_ON_SERR_DISABLE) &&
+	    (new_config->dump_on_serr != VXGE_HAL_DUMP_ON_SERR_ENABLE))
+		return (VXGE_HAL_BADCFG_DUMP_ON_SERR);
+
+	if ((new_config->dump_on_critical !=
+	    VXGE_HAL_DUMP_ON_CRITICAL_DISABLE) &&
+	    (new_config->dump_on_critical !=
+	    VXGE_HAL_DUMP_ON_CRITICAL_ENABLE))
+		return (VXGE_HAL_BADCFG_DUMP_ON_CRITICAL);
+
+	if ((new_config->dump_on_eccerr != VXGE_HAL_DUMP_ON_ECCERR_DISABLE) &&
+	    (new_config->dump_on_eccerr != VXGE_HAL_DUMP_ON_ECCERR_ENABLE))
+		return (VXGE_HAL_BADCFG_DUMP_ON_ECCERR);
+
+	if ((new_config->rth_en != VXGE_HAL_RTH_DISABLE) &&
+	    (new_config->rth_en != VXGE_HAL_RTH_ENABLE))
+		return (VXGE_HAL_BADCFG_RTH_EN);
+
+	if ((new_config->rth_it_type != VXGE_HAL_RTH_IT_TYPE_SOLO_IT) &&
+	    (new_config->rth_it_type != VXGE_HAL_RTH_IT_TYPE_MULTI_IT))
+		return (VXGE_HAL_BADCFG_RTH_IT_TYPE);
+
+	if ((new_config->rts_mac_en != VXGE_HAL_RTS_MAC_DISABLE) &&
+	    (new_config->rts_mac_en != VXGE_HAL_RTS_MAC_ENABLE))
+		return (VXGE_HAL_BADCFG_RTS_MAC_EN);
+
+	if ((new_config->rts_qos_en != VXGE_HAL_RTS_QOS_DISABLE) &&
+	    (new_config->rts_qos_en != VXGE_HAL_RTS_QOS_ENABLE))
+		return (VXGE_HAL_BADCFG_RTS_QOS_EN);
+
+	if ((new_config->rts_port_en != VXGE_HAL_RTS_PORT_DISABLE) &&
+	    (new_config->rts_port_en != VXGE_HAL_RTS_PORT_ENABLE))
+		return (VXGE_HAL_BADCFG_RTS_PORT_EN);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		if ((status = __hal_device_vpath_config_check(
+		    &new_config->vp_config[i])) != VXGE_HAL_OK)
+			return (status);
+	}
+
+	if ((new_config->max_cqe_groups < VXGE_HAL_MIN_MAX_CQE_GROUPS) ||
+	    (new_config->max_cqe_groups > VXGE_HAL_MAX_MAX_CQE_GROUPS))
+		return (VXGE_HAL_BADCFG_MAX_CQE_GROUPS);
+
+	if ((new_config->max_num_wqe_od_groups <
+	    VXGE_HAL_MIN_MAX_NUM_OD_GROUPS) ||
+	    (new_config->max_num_wqe_od_groups >
+	    VXGE_HAL_MAX_MAX_NUM_OD_GROUPS))
+		return (VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS);
+
+	if ((new_config->no_wqe_threshold < VXGE_HAL_MIN_NO_WQE_THRESHOLD) ||
+	    (new_config->no_wqe_threshold > VXGE_HAL_MAX_NO_WQE_THRESHOLD))
+		return (VXGE_HAL_BADCFG_NO_WQE_THRESHOLD);
+
+	if ((new_config->refill_threshold_high <
+	    VXGE_HAL_MIN_REFILL_THRESHOLD_HIGH) ||
+	    (new_config->refill_threshold_high >
+	    VXGE_HAL_MAX_REFILL_THRESHOLD_HIGH))
+		return (VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH);
+
+	if ((new_config->refill_threshold_low <
+	    VXGE_HAL_MIN_REFILL_THRESHOLD_LOW) ||
+	    (new_config->refill_threshold_low >
+	    VXGE_HAL_MAX_REFILL_THRESHOLD_LOW))
+		return (VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW);
+
+	if ((new_config->ack_blk_limit < VXGE_HAL_MIN_ACK_BLOCK_LIMIT) ||
+	    (new_config->ack_blk_limit > VXGE_HAL_MAX_ACK_BLOCK_LIMIT))
+		return (VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT);
+
+	if ((new_config->stats_read_method !=
+	    VXGE_HAL_STATS_READ_METHOD_DMA) &&
+	    (new_config->stats_read_method !=
+	    VXGE_HAL_STATS_READ_METHOD_PIO))
+		return (VXGE_HAL_BADCFG_STATS_READ_METHOD);
+
+	if ((new_config->poll_or_doorbell !=
+	    VXGE_HAL_POLL_OR_DOORBELL_POLL) &&
+	    (new_config->poll_or_doorbell !=
+	    VXGE_HAL_POLL_OR_DOORBELL_DOORBELL))
+		return (VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL);
+
+	if ((new_config->device_poll_millis <
+	    VXGE_HAL_MIN_DEVICE_POLL_MILLIS) ||
+	    (new_config->device_poll_millis >
+	    VXGE_HAL_MAX_DEVICE_POLL_MILLIS))
+		return (VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS);
+
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_config_default_get - Initialize device config with defaults.
+ * @device_config: Configuration structure to be initialized,
+ *	    For the X3100 configuration "knobs" please
+ *	    refer to vxge_hal_device_config_t and X3100
+ *	    User Guide.
+ *
+ * Initialize X3100 device config with default values.
+ *
+ * See also: vxge_hal_device_initialize(), vxge_hal_device_terminate(),
+ * vxge_hal_status_e {} vxge_hal_device_attr_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_config_default_get(
+    vxge_hal_device_config_t *device_config)
+{
+	u32 i;
+	vxge_hal_mac_config_t *mac_config;
+	vxge_hal_wire_port_config_t *wire_port_config;
+	vxge_hal_switch_port_config_t *switch_port_config;
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver("device_config = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) device_config);
+
+	device_config->dma_blockpool_min = VXGE_HAL_MIN_DMA_BLOCK_POOL_SIZE;
+	device_config->dma_blockpool_initial =
+	    VXGE_HAL_INITIAL_DMA_BLOCK_POOL_SIZE;
+	device_config->dma_blockpool_incr = VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE;
+	device_config->dma_blockpool_max = VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE;
+
+	mac_config = &device_config->mrpcim_config.mac_config;
+
+	for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
+
+		wire_port_config = &mac_config->wire_port_config[i];
+
+		wire_port_config->port_id = i;
+
+		wire_port_config->media = VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT;
+
+		wire_port_config->mtu = VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU;
+
+		wire_port_config->autoneg_mode =
+		    VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT;
+
+		wire_port_config->autoneg_rate =
+		    VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT;
+
+		wire_port_config->fixed_use_fsm =
+		    VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT;
+
+		wire_port_config->antp_use_fsm =
+		    VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT;
+
+		wire_port_config->anbe_use_fsm =
+		    VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT;
+
+		wire_port_config->link_stability_period =
+		    VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD;
+
+		wire_port_config->port_stability_period =
+		    VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD;
+
+		wire_port_config->tmac_en =
+		    VXGE_HAL_WIRE_PORT_TMAC_DEFAULT;
+
+		wire_port_config->rmac_en =
+		    VXGE_HAL_WIRE_PORT_RMAC_DEFAULT;
+
+		wire_port_config->tmac_pad =
+		    VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT;
+
+		wire_port_config->tmac_pad_byte =
+		    VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE;
+
+		wire_port_config->tmac_util_period =
+		    VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD;
+
+		wire_port_config->rmac_strip_fcs =
+		    VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT;
+
+		wire_port_config->rmac_prom_en =
+		    VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT;
+
+		wire_port_config->rmac_discard_pfrm =
+		    VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT;
+
+		wire_port_config->rmac_util_period =
+		    VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD;
+
+		wire_port_config->rmac_pause_gen_en =
+		    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT;
+
+		wire_port_config->rmac_pause_rcv_en =
+		    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT;
+
+		wire_port_config->rmac_pause_time =
+		    VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME;
+
+		wire_port_config->limiter_en =
+		    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT;
+
+		wire_port_config->max_limit =
+		    VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT;
+	}
+
+	switch_port_config = &mac_config->switch_port_config;
+
+	switch_port_config->mtu =
+	    VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU;
+
+	switch_port_config->tmac_en =
+	    VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT;
+
+	switch_port_config->rmac_en =
+	    VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT;
+
+	switch_port_config->tmac_pad =
+	    VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT;
+
+	switch_port_config->tmac_pad_byte =
+	    VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE;
+
+	switch_port_config->tmac_util_period =
+	    VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD;
+
+	switch_port_config->rmac_strip_fcs =
+	    VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT;
+
+	switch_port_config->rmac_prom_en =
+	    VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT;
+
+	switch_port_config->rmac_discard_pfrm =
+	    VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT;
+
+	switch_port_config->rmac_util_period =
+	    VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD;
+
+	switch_port_config->rmac_pause_gen_en =
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT;
+
+	switch_port_config->rmac_pause_rcv_en =
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT;
+
+	switch_port_config->rmac_pause_time =
+	    VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME;
+
+	switch_port_config->limiter_en =
+	    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT;
+
+	switch_port_config->max_limit =
+	    VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT;
+
+	mac_config->network_stability_period =
+	    VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD;
+
+	for (i = 0; i < 16; i++) {
+
+		mac_config->mc_pause_threshold[i] =
+		    VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD;
+
+	}
+
+	mac_config->tmac_perma_stop_en =
+	    VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT;
+
+	mac_config->tmac_tx_switch_dis =
+	    VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT;
+
+	mac_config->tmac_lossy_switch_en =
+	    VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT;
+
+	mac_config->tmac_lossy_wire_en =
+	    VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT;
+
+	mac_config->tmac_bcast_to_wire_dis =
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT;
+
+	mac_config->tmac_bcast_to_switch_dis =
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT;
+
+	mac_config->tmac_host_append_fcs_en =
+	    VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT;
+
+	mac_config->tpa_support_snap_ab_n =
+	    VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT;
+
+	mac_config->tpa_ecc_enable_n =
+	    VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT;
+
+	mac_config->rpa_ignore_frame_err =
+	    VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT;
+
+	mac_config->rpa_support_snap_ab_n =
+	    VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT;
+
+	mac_config->rpa_search_for_hao =
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT;
+
+	mac_config->rpa_support_ipv6_mobile_hdrs =
+	    VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT;
+
+	mac_config->rpa_ipv6_stop_searching =
+	    VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT;
+
+	mac_config->rpa_no_ps_if_unknown =
+	    VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT;
+
+	mac_config->rpa_search_for_etype =
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT;
+
+	mac_config->rpa_repl_l4_comp_csum =
+	    VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT;
+
+	mac_config->rpa_repl_l3_incl_cf =
+	    VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT;
+
+	mac_config->rpa_repl_l3_comp_csum =
+	    VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT;
+
+	mac_config->rpa_repl_ipv4_tcp_incl_ph =
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT;
+
+	mac_config->rpa_repl_ipv6_tcp_incl_ph =
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT;
+
+	mac_config->rpa_repl_ipv4_udp_incl_ph =
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT;
+
+	mac_config->rpa_repl_ipv6_udp_incl_ph =
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT;
+
+	mac_config->rpa_repl_l4_incl_cf =
+	    VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT;
+
+	mac_config->rpa_repl_strip_vlan_tag =
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lag_en =
+	    VXGE_HAL_LAG_LAG_EN_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lag_mode =
+	    VXGE_HAL_LAG_LAG_MODE_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.la_mode_config.tx_discard =
+	    VXGE_HAL_LAG_TX_DISCARD_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.la_mode_config.distrib_alg_sel =
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.la_mode_config.distrib_dest =
+	    VXGE_HAL_LAG_DISTRIB_DEST_DEFAULT;
+
+	device_config->
+	    mrpcim_config.lag_config.la_mode_config.distrib_remap_if_fail =
+	    VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.la_mode_config.coll_max_delay =
+	    VXGE_HAL_LAG_DEF_COLL_MAX_DELAY;
+
+	device_config->mrpcim_config.lag_config.la_mode_config.rx_discard =
+	    VXGE_HAL_LAG_RX_DISCARD_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.ap_mode_config.hot_standby =
+	    VXGE_HAL_LAG_HOT_STANDBY_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.ap_mode_config.lacp_decides =
+	    VXGE_HAL_LAG_LACP_DECIDES_DEFAULT;
+
+	device_config->
+	    mrpcim_config.lag_config.ap_mode_config.pref_active_port =
+	    VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.ap_mode_config.auto_failback =
+	    VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.ap_mode_config.failback_en =
+	    VXGE_HAL_LAG_FAILBACK_EN_DEFAULT;
+
+	device_config->
+	    mrpcim_config.lag_config.ap_mode_config.cold_failover_timeout =
+	    VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT;
+
+	device_config->mrpcim_config.lag_config.ap_mode_config.alt_admin_key =
+	    VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY;
+
+	device_config->mrpcim_config.lag_config.ap_mode_config.alt_aggr =
+	    VXGE_HAL_LAG_ALT_AGGR_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.sl_mode_config.pref_indiv_port =
+	    VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lacp_config.lacp_en =
+	    VXGE_HAL_LAG_LACP_EN_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lacp_config.lacp_begin =
+	    VXGE_HAL_LAG_LACP_BEGIN_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lacp_config.discard_lacp =
+	    VXGE_HAL_LAG_DISCARD_LACP_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lacp_config.liberal_len_chk =
+	    VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lacp_config.marker_gen_recv_en =
+	    VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.lacp_config.marker_resp_en =
+	    VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT;
+
+	device_config->
+	    mrpcim_config.lag_config.lacp_config.marker_resp_timeout =
+	    VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT;
+
+	device_config->
+	    mrpcim_config.lag_config.lacp_config.slow_proto_mrkr_min_interval =
+	    VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL;
+
+	device_config->mrpcim_config.lag_config.lacp_config.throttle_mrkr_resp =
+	    VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.incr_tx_aggr_stats =
+	    VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT;
+
+	for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) {
+
+		vxge_hal_lag_port_config_t *port_config =
+		&device_config->mrpcim_config.lag_config.port_config[i];
+
+		port_config->port_id = i;
+
+		port_config->lag_en = VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT;
+
+		port_config->discard_slow_proto =
+		    VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT;
+
+		port_config->host_chosen_aggr =
+		    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT;
+
+		port_config->host_chosen_aggr =
+		    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT;
+
+		port_config->discard_unknown_slow_proto =
+		    VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT;
+
+		port_config->actor_port_num =
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM;
+
+		port_config->actor_port_priority =
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY;
+
+		port_config->actor_key_10g =
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G;
+
+		port_config->actor_key_1g =
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G;
+
+		port_config->actor_lacp_activity =
+		    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT;
+
+		port_config->actor_lacp_timeout =
+		    VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT;
+
+		port_config->actor_aggregation =
+		    VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT;
+
+		port_config->actor_synchronization =
+		    VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT;
+
+		port_config->actor_collecting =
+		    VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT;
+
+		port_config->actor_distributing =
+		    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT;
+
+		port_config->actor_distributing =
+		    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT;
+
+		port_config->actor_defaulted =
+		    VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT;
+
+		port_config->actor_expired =
+		    VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT;
+
+		port_config->partner_sys_pri =
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI;
+
+		port_config->partner_key =
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY;
+
+		port_config->partner_port_num =
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM;
+
+		port_config->partner_port_priority =
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY;
+
+		port_config->partner_lacp_activity =
+		    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT;
+
+		port_config->partner_lacp_timeout =
+		    VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT;
+
+		port_config->partner_aggregation =
+		    VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT;
+
+		port_config->partner_synchronization =
+		    VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT;
+
+		port_config->partner_collecting =
+		    VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT;
+
+		port_config->partner_distributing =
+		    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT;
+
+		port_config->partner_distributing =
+		    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT;
+
+		port_config->partner_defaulted =
+		    VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT;
+
+		port_config->partner_expired =
+		    VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT;
+
+	}
+
+	for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) {
+
+		device_config->
+		    mrpcim_config.lag_config.aggr_config[i].aggr_id = i + 1;
+
+		device_config->
+		    mrpcim_config.lag_config.aggr_config[i].use_port_mac_addr =
+		    VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT;
+
+		device_config->
+		    mrpcim_config.lag_config.aggr_config[i].mac_addr_sel =
+		    VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT;
+
+		device_config->
+		    mrpcim_config.lag_config.aggr_config[i].admin_key =
+		    VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY;
+
+	}
+
+	device_config->mrpcim_config.lag_config.sys_pri =
+	    VXGE_HAL_LAG_DEF_SYS_PRI;
+
+	device_config->mrpcim_config.lag_config.use_port_mac_addr =
+	    VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.mac_addr_sel =
+	    VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.fast_per_time =
+	    VXGE_HAL_LAG_DEF_FAST_PER_TIME;
+
+	device_config->mrpcim_config.lag_config.slow_per_time =
+	    VXGE_HAL_LAG_DEF_SLOW_PER_TIME;
+
+	device_config->mrpcim_config.lag_config.short_timeout =
+	    VXGE_HAL_LAG_DEF_SHORT_TIMEOUT;
+
+	device_config->mrpcim_config.lag_config.long_timeout =
+	    VXGE_HAL_LAG_DEF_LONG_TIMEOUT;
+
+	device_config->mrpcim_config.lag_config.churn_det_time =
+	    VXGE_HAL_LAG_DEF_CHURN_DET_TIME;
+
+	device_config->mrpcim_config.lag_config.aggr_wait_time =
+	    VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME;
+
+	device_config->mrpcim_config.lag_config.short_timer_scale =
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT;
+
+	device_config->mrpcim_config.lag_config.long_timer_scale =
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT;
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		device_config->mrpcim_config.vp_qos[i].priority =
+		    VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT;
+
+		device_config->mrpcim_config.vp_qos[i].min_bandwidth =
+		    VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT;
+
+		device_config->mrpcim_config.vp_qos[i].max_bandwidth =
+		    VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT;
+
+	}
+
+	device_config->isr_polling_cnt = VXGE_HAL_DEF_ISR_POLLING_CNT;
+
+	device_config->max_payload_size =
+	    VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE;
+
+	device_config->mmrb_count = VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT;
+
+	device_config->stats_refresh_time_sec =
+	    VXGE_HAL_USE_FLASH_DEFAULT_STATS_REFRESH_TIME;
+
+	device_config->intr_mode = VXGE_HAL_INTR_MODE_DEF;
+
+	device_config->dump_on_unknown = VXGE_HAL_DUMP_ON_UNKNOWN_DEFAULT;
+
+	device_config->dump_on_serr = VXGE_HAL_DUMP_ON_SERR_DEFAULT;
+
+	device_config->dump_on_critical = VXGE_HAL_DUMP_ON_CRITICAL_DEFAULT;
+
+	device_config->dump_on_eccerr = VXGE_HAL_DUMP_ON_ECCERR_DEFAULT;
+
+	device_config->rth_en = VXGE_HAL_RTH_DEFAULT;
+
+	device_config->rth_it_type = VXGE_HAL_RTH_IT_TYPE_DEFAULT;
+
+	device_config->device_poll_millis = VXGE_HAL_DEF_DEVICE_POLL_MILLIS;
+
+	device_config->rts_mac_en = VXGE_HAL_RTS_MAC_DEFAULT;
+
+	device_config->rts_qos_en = VXGE_HAL_RTS_QOS_DEFAULT;
+
+	device_config->rts_port_en = VXGE_HAL_RTS_PORT_DEFAULT;
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		device_config->vp_config[i].vp_id = i;
+
+		device_config->vp_config[i].wire_port =
+		    VXGE_HAL_VPATH_USE_DEFAULT_PORT;
+
+		device_config->vp_config[i].priority =
+		    VXGE_HAL_VPATH_PRIORITY_DEFAULT;
+
+		device_config->vp_config[i].bandwidth =
+		    VXGE_HAL_VPATH_BW_LIMIT_DEFAULT;
+
+		device_config->vp_config[i].no_snoop =
+		    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].ring.enable =
+		    VXGE_HAL_RING_DEFAULT;
+
+		device_config->vp_config[i].ring.ring_length =
+		    VXGE_HAL_DEF_RING_LENGTH;
+
+		device_config->vp_config[i].ring.buffer_mode =
+		    VXGE_HAL_RING_RXD_BUFFER_MODE_DEFAULT;
+
+		device_config->vp_config[i].ring.scatter_mode =
+		    VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].ring.post_mode =
+		    VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].ring.max_frm_len =
+		    VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU;
+
+		device_config->vp_config[i].ring.no_snoop_bits =
+		    VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].ring.rx_timer_val =
+		    VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL;
+
+		device_config->vp_config[i].ring.greedy_return =
+		    VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].ring.rx_timer_ci =
+		    VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].ring.backoff_interval_us =
+		    VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US;
+
+		device_config->vp_config[i].ring.indicate_max_pkts =
+		    VXGE_HAL_DEF_RING_INDICATE_MAX_PKTS;
+
+
+		device_config->vp_config[i].fifo.enable =
+		    VXGE_HAL_FIFO_DEFAULT;
+
+		device_config->vp_config[i].fifo.fifo_length =
+		    VXGE_HAL_DEF_FIFO_LENGTH;
+
+		device_config->vp_config[i].fifo.max_frags =
+		    VXGE_HAL_DEF_FIFO_FRAGS;
+
+		device_config->vp_config[i].fifo.alignment_size =
+		    VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE;
+
+		device_config->vp_config[i].fifo.max_aligned_frags = 0;
+
+		device_config->vp_config[i].fifo.intr =
+		    VXGE_HAL_FIFO_QUEUE_INTR_DEFAULT;
+
+		device_config->vp_config[i].fifo.no_snoop_bits =
+		    VXGE_HAL_FIFO_NO_SNOOP_DEFAULT;
+
+
+		device_config->vp_config[i].tti.intr_enable =
+		    VXGE_HAL_TIM_INTR_DEFAULT;
+
+		device_config->vp_config[i].tti.btimer_val =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL;
+
+		device_config->vp_config[i].tti.timer_ac_en =
+		    VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tti.timer_ci_en =
+		    VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tti.timer_ri_en =
+		    VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tti.rtimer_event_sf =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF;
+
+		device_config->vp_config[i].tti.rtimer_val =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL;
+
+		device_config->vp_config[i].tti.util_sel =
+		    VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tti.ltimer_val =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL;
+
+		device_config->vp_config[i].tti.txfrm_cnt_en =
+		    VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tti.txd_cnt_en =
+		    VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tti.urange_a =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A;
+
+		device_config->vp_config[i].tti.uec_a =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A;
+
+		device_config->vp_config[i].tti.urange_b =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B;
+
+		device_config->vp_config[i].tti.uec_b =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B;
+
+		device_config->vp_config[i].tti.urange_c =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C;
+
+		device_config->vp_config[i].tti.uec_c =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C;
+
+		device_config->vp_config[i].tti.uec_d =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D;
+
+		device_config->vp_config[i].tti.ufca_intr_thres =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES;
+
+		device_config->vp_config[i].tti.ufca_lo_lim =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM;
+
+		device_config->vp_config[i].tti.ufca_hi_lim =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM;
+
+		device_config->vp_config[i].tti.ufca_lbolt_period =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD;
+
+		device_config->vp_config[i].rti.intr_enable =
+		    VXGE_HAL_TIM_INTR_DEFAULT;
+
+		device_config->vp_config[i].rti.btimer_val =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL;
+
+		device_config->vp_config[i].rti.timer_ac_en =
+		    VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rti.timer_ci_en =
+		    VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rti.timer_ri_en =
+		    VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rti.rtimer_event_sf =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF;
+
+		device_config->vp_config[i].rti.rtimer_val =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL;
+
+		device_config->vp_config[i].rti.util_sel =
+		    VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rti.ltimer_val =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL;
+
+		device_config->vp_config[i].rti.txfrm_cnt_en =
+		    VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rti.txd_cnt_en =
+		    VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rti.urange_a =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A;
+
+		device_config->vp_config[i].rti.uec_a =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A;
+
+		device_config->vp_config[i].rti.urange_b =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B;
+
+		device_config->vp_config[i].rti.uec_b =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B;
+
+		device_config->vp_config[i].rti.urange_c =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C;
+
+		device_config->vp_config[i].rti.uec_c =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C;
+
+		device_config->vp_config[i].rti.uec_d =
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D;
+
+		device_config->vp_config[i].rti.ufca_intr_thres =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES;
+
+		device_config->vp_config[i].rti.ufca_lo_lim =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM;
+
+		device_config->vp_config[i].rti.ufca_hi_lim =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM;
+
+		device_config->vp_config[i].rti.ufca_lbolt_period =
+		    VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD;
+
+		device_config->vp_config[i].mtu =
+		    VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
+
+		device_config->vp_config[i].tpa_lsov2_en =
+		    VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tpa_ignore_frame_error =
+		    VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tpa_ipv6_keep_searching =
+		    VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tpa_l4_pshdr_present =
+		    VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].tpa_support_mobile_ipv6_hdrs =
+		    VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT;
+
+		device_config->vp_config[i].rpa_ipv4_tcp_incl_ph =
+		    VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_ipv6_tcp_incl_ph =
+		    VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_ipv4_udp_incl_ph =
+		    VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_ipv6_udp_incl_ph =
+		    VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_l4_incl_cf =
+		    VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_strip_vlan_tag =
+		    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_l4_comp_csum =
+		    VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_l3_incl_cf =
+		    VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_l3_comp_csum =
+		    VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_ucast_all_addr_en =
+		    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_mcast_all_addr_en =
+		    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_bcast_en =
+		    VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].rpa_all_vid_en =
+		    VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT;
+
+		device_config->vp_config[i].vp_queue_l2_flow =
+		    VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT;
+
+	}
+
+	device_config->max_cqe_groups = VXGE_HAL_DEF_MAX_CQE_GROUPS;
+
+	device_config->max_num_wqe_od_groups = VXGE_HAL_DEF_MAX_NUM_OD_GROUPS;
+
+	device_config->no_wqe_threshold = VXGE_HAL_DEF_NO_WQE_THRESHOLD;
+
+	device_config->refill_threshold_high =
+	    VXGE_HAL_DEF_REFILL_THRESHOLD_HIGH;
+
+	device_config->refill_threshold_low = VXGE_HAL_DEF_REFILL_THRESHOLD_LOW;
+
+	device_config->ack_blk_limit = VXGE_HAL_DEF_ACK_BLOCK_LIMIT;
+
+	device_config->poll_or_doorbell = VXGE_HAL_POLL_OR_DOORBELL_DEFAULT;
+
+	device_config->stats_read_method = VXGE_HAL_STATS_READ_METHOD_DEFAULT;
+
+	device_config->debug_level = VXGE_DEBUG_LEVEL_DEF;
+
+	device_config->debug_mask = VXGE_DEBUG_MODULE_MASK_DEF;
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+	device_config->tracebuf_size = VXGE_HAL_DEF_CIRCULAR_ARR;
+#endif
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+void
+vxge_hw_vpath_set_zero_rx_frm_len(vxge_hal_device_h devh, u32 vp_id)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(devh != NULL);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	val64 = vxge_os_pio_mem_read64(vpath->hldev->header.pdev,
+	    vpath->hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
+
+	vxge_os_pio_mem_write64(vpath->hldev->header.pdev,
+	    vpath->hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_os_pio_mem_read64(vpath->hldev->header.pdev,
+	    vpath->hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+}
+
+/*
+ * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
+ *
+ * Bug: Receive path stuck during small frames blast test after numerous vpath
+ * reset cycle
+ *
+ * Fix: Driver work-around is to ensure that the vpath queue in the FB(frame
+ * buffer) is empty before reset is asserted. In order to do this driver needs
+ * to stop RxMAC from sending frames to the queue, e.g., by configuring the
+ * max frame length for the vpath to 0 or some small value. Driver then polls
+ * WRDMA registers to check that the ring controller for the vpath is not
+ * processing frames for a period of time(while having enough RxDs to do so).
+ *
+ * Poll 2 registers in the WRDMA, namely the FRM_IN_PROGRESS_CNT_VPn register
+ * and the PRC_RXD_DOORBELL_VPn register. There is no per-vpath register in
+ * the frame buffer that indicates if the vpath queue is empty, so determine
+ * the empty state with 2 conditions:
+ * 1. There are no frames currently being processed in the WRDMA for
+ * the vpath, and
+ * 2. The ring controller for the vpath is not being starved of RxDs
+ * (otherwise it will not be able to process frames even though the FB vpath
+ * queue is not empty).
+ *
+ * For the second condition, compare the read value of PRC_RXD_DOORBELL_VPn
+ * register against the RXD_SPAT value for the vpath.
+ * The ring controller will not attempt to fetch RxDs until it has at least
+ * RXD_SPAT qwords in the doorbell. A factor of 2 is used just to be safe.
+ * Additionally, it is also possible that the ring controller is not
+ * processing frames because of arbitration. The chance of this is very small,
+ * and we try to reduce it even further by checking that the 2 conditions above
+ * hold in 3 successive polls. This bug does not occur when frames from the
+ * reset vpath are not selected back-to-back due to arbitration.
+ * @hldev: HW device handle.
+ * @vp_id: Vpath ID.
+ * Returns: void
+ */
+void
+vxge_hw_vpath_wait_receive_idle(vxge_hal_device_h devh, u32 vp_id,
+    u32 *count, u32 *total_count)
+{
+	u64 val64;
+	u32 new_qw_count, rxd_spat;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+
+	vpath = &hldev->virtual_paths[vp_id];
+
+	vxge_assert(vpath != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (vpath->vp_config->ring.enable == VXGE_HAL_RING_DISABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d ",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+	do {
+		vxge_os_mdelay(10);
+
+		val64 = vxge_os_pio_mem_read64(
+		    hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->prc_rxd_doorbell);
+
+		new_qw_count =
+		    (u32) VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(val64);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->prc_cfg6);
+
+		rxd_spat = (u32) VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->frm_in_progress_cnt);
+
+		/*
+		 * Check if there is enough RxDs with HW AND
+		 * it is not processing any frames.
+		 */
+
+		if ((new_qw_count <= 2 * rxd_spat) || (val64 > 0))
+			*count = 0;
+		else
+			(*count)++;
+		(*total_count)++;
+
+	} while ((*count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
+	    (*total_count < VXGE_HW_MAX_POLLING_COUNT));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_assert(*total_count < VXGE_HW_MAX_POLLING_COUNT);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-debug.h b/sys/dev/vxge/vxgehal/vxgehal-debug.h
new file mode 100644
index 000000000000..57e39f46215d
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-debug.h
@@ -0,0 +1,438 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_DEBUG_H
+#define	VXGE_HAL_DEBUG_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	D_ERR_MASK   ((__hal_device_t *)hldev)->d_err_mask
+#define	D_INFO_MASK  ((__hal_device_t *)hldev)->d_info_mask
+#define	D_TRACE_MASK ((__hal_device_t *)hldev)->d_trace_mask
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+#define	vxge_hal_debug_printf vxge_os_vasprintf
+#else
+#define	vxge_hal_debug_printf vxge_os_vaprintf
+#endif
+
+#ifndef	VXGE_DEBUG_INLINE_FUNCTIONS
+#define	vxge_hal_debug_noop(fmt, ...)
+#else
+static inline void
+vxge_hal_debug_noop(
+    char *fmt, ...)
+{
+
+}
+#endif
+
+#if (VXGE_COMPONENT_HAL_DRIVER & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_driver					\
+	if (g_debug_level & VXGE_ERR) vxge_hal_debug_printf
+#define	vxge_hal_info_log_driver				\
+	if (g_debug_level & VXGE_INFO) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_driver				\
+	if (g_debug_level & VXGE_TRACE) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_driver   vxge_hal_debug_noop
+#define	vxge_hal_info_log_driver  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_driver vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_DEVICE & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_device					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_DEVICE) vxge_hal_debug_printf
+#define	vxge_hal_info_log_device				\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_DEVICE) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_device				\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_DEVICE) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_device   vxge_hal_debug_noop
+#define	vxge_hal_info_log_device  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_device vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_DEVICE_IRQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_device_irq				\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_DEVICE_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_device_irq				\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_DEVICE_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_device_irq				\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_DEVICE_IRQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_device_irq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_device_irq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_device_irq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_VPATH & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_vpath					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_VPATH) vxge_hal_debug_printf
+#define	vxge_hal_info_log_vpath					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_VPATH) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_vpath				\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_VPATH) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_vpath   vxge_hal_debug_noop
+#define	vxge_hal_info_log_vpath  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_vpath vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_VPATH_IRQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_vpath_irq					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_VPATH_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_vpath_irq					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_VPATH_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_vpath_irq					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_VPATH_IRQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_vpath_irq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_vpath_irq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_vpath_irq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_CONFIG & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_config						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_CONFIG) vxge_hal_debug_printf
+#define	vxge_hal_info_log_config					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_CONFIG) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_config					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_CONFIG) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_config   vxge_hal_debug_noop
+#define	vxge_hal_info_log_config  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_config vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_MM & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_mm						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_MM) vxge_hal_debug_printf
+#define	vxge_hal_info_log_mm						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_MM) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_mm						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_MM) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_mm   vxge_hal_debug_noop
+#define	vxge_hal_info_log_mm  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_mm vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_pool						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_POOL) vxge_hal_debug_printf
+#define	vxge_hal_info_log_pool						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_POOL) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_pool						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_POOL) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_pool   vxge_hal_debug_noop
+#define	vxge_hal_info_log_pool  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_pool vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_QUEUE & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_queue						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_QUEUE) vxge_hal_debug_printf
+#define	vxge_hal_info_log_queue						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_QUEUE) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_queue					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_QUEUE) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_queue   vxge_hal_debug_noop
+#define	vxge_hal_info_log_queue  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_queue vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_BITMAP & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_bitmap						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_BITMAP) vxge_hal_debug_printf
+#define	vxge_hal_info_log_bitmap					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_BITMAP) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_bitmap					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_BITMAP) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_bitmap   vxge_hal_debug_noop
+#define	vxge_hal_info_log_bitmap  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_bitmap vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_channel					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_CHANNEL) vxge_hal_debug_printf
+#define	vxge_hal_info_log_channel					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_CHANNEL) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_channel					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_CHANNEL) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_channel   vxge_hal_debug_noop
+#define	vxge_hal_info_log_channel  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_channel vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_FIFO & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_fifo						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_FIFO) vxge_hal_debug_printf
+#define	vxge_hal_info_log_fifo						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_FIFO) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_fifo						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_FIFO) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_fifo   vxge_hal_debug_noop
+#define	vxge_hal_info_log_fifo  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_fifo vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_RING & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_ring						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_RING) vxge_hal_debug_printf
+#define	vxge_hal_info_log_ring						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_RING) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_ring						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_RING) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_ring   vxge_hal_debug_noop
+#define	vxge_hal_info_log_ring  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_ring vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_DMQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_dmq						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_DMQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_dmq						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_DMQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_dmq						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_DMQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_dmq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_dmq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_dmq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_UMQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_umq						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_UMQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_umq						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_UMQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_umq						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_UMQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_umq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_umq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_umq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_SQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_sq						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_SQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_sq						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_SQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_sq						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_sq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_sq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_sq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_SRQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_srq						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_SRQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_srq						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_SRQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_srq						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SRQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_srq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_srq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_srq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_CQRQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_cqrq						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_CQRQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_cqrq						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_CQRQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_cqrq						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_CQRQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_cqrq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_cqrq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_cqrq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_NCE & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_nce						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_NCE) vxge_hal_debug_printf
+#define	vxge_hal_info_log_nce						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_NCE) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_nce						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_NCE) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_nce   vxge_hal_debug_noop
+#define	vxge_hal_info_log_nce  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_nce vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_STAG & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_stag						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_STAG) vxge_hal_debug_printf
+#define	vxge_hal_info_log_stag						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_STAG) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_stag						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_STAG) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_stag   vxge_hal_debug_noop
+#define	vxge_hal_info_log_stag  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_stag vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_TCP & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_tcp						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_TCP) vxge_hal_debug_printf
+#define	vxge_hal_info_log_tcp						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_TCP) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_tcp						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_TCP) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_tcp   vxge_hal_debug_noop
+#define	vxge_hal_info_log_tcp  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_tcp vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_LRO & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_lro						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_LRO) vxge_hal_debug_printf
+#define	vxge_hal_info_log_lro						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_LRO) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_lro						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_LRO) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_lro   vxge_hal_debug_noop
+#define	vxge_hal_info_log_lro  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_lro vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_SPDM & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_spdm						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_SPDM) vxge_hal_debug_printf
+#define	vxge_hal_info_log_spdm						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_SPDM) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_spdm						\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SPDM) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_spdm   vxge_hal_debug_noop
+#define	vxge_hal_info_log_spdm  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_spdm vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_SESSION & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_session					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_SESSION) vxge_hal_debug_printf
+#define	vxge_hal_info_log_session					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_SESSION) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_session					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SESSION) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_session   vxge_hal_debug_noop
+#define	vxge_hal_info_log_session  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_session vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_STATS & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_stats						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_STATS) vxge_hal_debug_printf
+#define	vxge_hal_info_log_stats						\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_STATS) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_stats					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_STATS) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_stats   vxge_hal_debug_noop
+#define	vxge_hal_info_log_stats  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_stats vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_MRPCIM & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_mrpcim						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_MRPCIM) vxge_hal_debug_printf
+#define	vxge_hal_info_log_mrpcim					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_MRPCIM) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_mrpcim					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_MRPCIM) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_mrpcim   vxge_hal_debug_noop
+#define	vxge_hal_info_log_mrpcim  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_mrpcim vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_MRPCIM_IRQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_mrpcim_irq					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_MRPCIM_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_mrpcim_irq					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_MRPCIM_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_mrpcim_irq					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_MRPCIM_IRQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_mrpcim_irq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_mrpcim_irq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_mrpcim_irq vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_SRPCIM & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_srpcim						\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_SRPCIM) vxge_hal_debug_printf
+#define	vxge_hal_info_log_srpcim					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_SRPCIM) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_srpcim					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SRPCIM) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_srpcim   vxge_hal_debug_noop
+#define	vxge_hal_info_log_srpcim  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_srpcim vxge_hal_debug_noop
+#endif
+
+#if (VXGE_COMPONENT_HAL_SRPCIM_IRQ & VXGE_DEBUG_MODULE_MASK)
+#define	vxge_hal_err_log_srpcim_irq					\
+	if (D_ERR_MASK & VXGE_COMPONENT_HAL_SRPCIM_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_info_log_srpcim_irq					\
+	if (D_INFO_MASK & VXGE_COMPONENT_HAL_SRPCIM_IRQ) vxge_hal_debug_printf
+#define	vxge_hal_trace_log_srpcim_irq					\
+	if (D_TRACE_MASK & VXGE_COMPONENT_HAL_SRPCIM_IRQ) vxge_hal_debug_printf
+#else
+#define	vxge_hal_err_log_srpcim_irq   vxge_hal_debug_noop
+#define	vxge_hal_info_log_srpcim_irq  vxge_hal_debug_noop
+#define	vxge_hal_trace_log_srpcim_irq vxge_hal_debug_noop
+#endif
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_DEBUG_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-device.c b/sys/dev/vxge/vxgehal/vxgehal-device.c
new file mode 100644
index 000000000000..2e77f1ec7740
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-device.c
@@ -0,0 +1,3620 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * vxge_hal_pio_mem_write32_upper
+ *
+ * Endiann-aware implementation of vxge_os_pio_mem_write32().
+ * Since X3100 has 64bit registers, we differintiate uppper and lower
+ * parts.
+ */
+void
+vxge_hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr)
+{
+#if defined(VXGE_OS_HOST_BIG_ENDIAN) && !defined(VXGE_OS_PIO_LITTLE_ENDIAN)
+	vxge_os_pio_mem_write32(pdev, regh, val, addr);
+#else
+	vxge_os_pio_mem_write32(pdev, regh, val, (void *) ((char *) addr + 4));
+#endif
+}
+
+/*
+ * vxge_hal_pio_mem_write32_lower
+ *
+ * Endiann-aware implementation of vxge_os_pio_mem_write32().
+ * Since X3100 has 64bit registers, we differintiate uppper and lower
+ * parts.
+ */
+void
+vxge_hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
+    void *addr)
+{
+#if defined(VXGE_OS_HOST_BIG_ENDIAN) && !defined(VXGE_OS_PIO_LITTLE_ENDIAN)
+	vxge_os_pio_mem_write32(pdev, regh, val,
+	    (void *) ((char *) addr + 4));
+#else
+	vxge_os_pio_mem_write32(pdev, regh, val, addr);
+#endif
+}
+
+/*
+ * vxge_hal_device_pciconfig_get - Read the content of given address
+ *			 in pci config space.
+ * @devh: Device handle.
+ * @offset: Configuration address(offset)to read from
+ * @length: Length of the data (1, 2 or 4 bytes)
+ * @val: Pointer to a buffer to return the content of the address
+ *
+ * Read from the pci config space.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_pciconfig_get(
+    vxge_hal_device_h devh,
+    u32 offset,
+    u32 length,
+    void *val)
+{
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (val != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpath_assignments & mBIT(i)))
+			continue;
+
+		status = __hal_vpath_pci_read(hldev, i,
+		    offset, length, val);
+
+		if (status == VXGE_HAL_OK)
+			break;
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+
+}
+
+/*
+ * __hal_device_pci_caps_list_process
+ * @hldev: HAL device handle.
+ *
+ * Process PCI capabilities and initialize the offsets
+ */
+void
+__hal_device_pci_caps_list_process(__hal_device_t *hldev)
+{
+	u8 cap_id;
+	u16 ext_cap_id;
+	u16 next_ptr;
+	u32 *ptr_32;
+	vxge_hal_pci_config_t *pci_config = &hldev->pci_config_space_bios;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	next_ptr = pci_config->capabilities_pointer;
+
+	while (next_ptr != 0) {
+
+		cap_id = VXGE_HAL_PCI_CAP_ID((((u8 *) pci_config) + next_ptr));
+
+		switch (cap_id) {
+
+		case VXGE_HAL_PCI_CAP_ID_PM:
+			hldev->pci_caps.pm_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_VPD:
+			hldev->pci_caps.vpd_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_SLOTID:
+			hldev->pci_caps.sid_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_MSI:
+			hldev->pci_caps.msi_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_VS:
+			hldev->pci_caps.vs_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_SHPC:
+			hldev->pci_caps.shpc_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_PCIE:
+			hldev->pci_e_caps = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_MSIX:
+			hldev->pci_caps.msix_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_CAP_ID_AGP:
+		case VXGE_HAL_PCI_CAP_ID_CHSWP:
+		case VXGE_HAL_PCI_CAP_ID_PCIX:
+		case VXGE_HAL_PCI_CAP_ID_HT:
+		case VXGE_HAL_PCI_CAP_ID_DBGPORT:
+		case VXGE_HAL_PCI_CAP_ID_CPCICSR:
+		case VXGE_HAL_PCI_CAP_ID_PCIBSVID:
+		case VXGE_HAL_PCI_CAP_ID_AGP8X:
+		case VXGE_HAL_PCI_CAP_ID_SECDEV:
+			vxge_hal_info_log_device("Unexpected Capability = %d",
+			    cap_id);
+			break;
+		default:
+			vxge_hal_info_log_device("Unknown capability = %d",
+			    cap_id);
+			break;
+		}
+
+		next_ptr =
+		    VXGE_HAL_PCI_CAP_NEXT((((u8 *) pci_config) + next_ptr));
+
+	}
+
+	/* CONSTCOND */
+	if (VXGE_HAL_PCI_CONFIG_SPACE_SIZE <= 0x100) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+	next_ptr = 0x100;
+	while (next_ptr != 0) {
+
+		ptr_32 = (u32 *) ((void *) (((u8 *) pci_config) + next_ptr));
+		ext_cap_id = (u16) (VXGE_HAL_PCI_EXT_CAP_ID(*ptr_32));
+
+		switch (ext_cap_id) {
+
+		case VXGE_HAL_PCI_EXT_CAP_ID_ERR:
+			hldev->pci_e_ext_caps.err_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_EXT_CAP_ID_VC:
+			hldev->pci_e_ext_caps.vc_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_EXT_CAP_ID_DSN:
+			hldev->pci_e_ext_caps.dsn_cap_offset = next_ptr;
+			break;
+		case VXGE_HAL_PCI_EXT_CAP_ID_PWR:
+			hldev->pci_e_ext_caps.pwr_budget_cap_offset = next_ptr;
+			break;
+
+		default:
+			vxge_hal_info_log_device("Unknown capability = %d",
+			    ext_cap_id);
+			break;
+		}
+
+		next_ptr = (u16) VXGE_HAL_PCI_EXT_CAP_NEXT(*ptr_32);
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_device_pci_e_init
+ * @hldev: HAL device handle.
+ *
+ * Initialize certain PCI/PCI-X configuration registers
+ * with recommended values. Save config space for future hw resets.
+ */
+void
+__hal_device_pci_e_init(__hal_device_t *hldev)
+{
+	int i;
+	u16 cmd;
+	u32 *ptr_32;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	/* save original PCI config space to restore it on device_terminate() */
+	ptr_32 = (u32 *) ((void *) &hldev->pci_config_space_bios);
+	for (i = 0; i < VXGE_HAL_PCI_CONFIG_SPACE_SIZE / 4; i++) {
+		(void) __hal_vpath_pci_read(hldev,
+		    hldev->first_vp_id,
+		    i * 4,
+		    4,
+		    ptr_32 + i);
+	}
+
+	__hal_device_pci_caps_list_process(hldev);
+
+	/* Set the PErr Repconse bit and SERR in PCI command register. */
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, command),
+	    2,
+	    &cmd);
+	cmd |= 0x140;
+	vxge_os_pci_write16(hldev->header.pdev, hldev->header.cfgh,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, command), cmd);
+
+	/* save PCI config space for future resets */
+	ptr_32 = (u32 *) ((void *) &hldev->pci_config_space);
+	for (i = 0; i < VXGE_HAL_PCI_CONFIG_SPACE_SIZE / 4; i++) {
+		(void) __hal_vpath_pci_read(hldev,
+		    hldev->first_vp_id,
+		    i * 4,
+		    4,
+		    ptr_32 + i);
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_device_bus_master_enable
+ * @hldev: HAL device handle.
+ *
+ * Enable bus mastership.
+ */
+static void
+__hal_device_bus_master_enable(__hal_device_t *hldev)
+{
+	u16 cmd;
+	u16 bus_master = 4;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, command),
+	    2,
+	    &cmd);
+	/* already enabled? do nothing */
+	if (cmd & bus_master)
+		return;
+
+	cmd |= bus_master;
+	vxge_os_pci_write16(hldev->header.pdev, hldev->header.cfgh,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, command), cmd);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_register_poll
+ * @pdev: PCI device object.
+ * @regh: BAR mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @reg: register to poll for
+ * @op: 0 - bit reset, 1 - bit set
+ * @mask: mask for logical "and" condition based on %op
+ * @max_millis: maximum time to try to poll in milliseconds
+ *
+ * Will poll certain register for specified amount of time.
+ * Will poll until masked bit is not cleared.
+ */
+vxge_hal_status_e
+vxge_hal_device_register_poll(
+    pci_dev_h pdev,
+    pci_reg_h regh,
+    u64 *reg,
+    u32 op,
+    u64 mask,
+    u32 max_millis)
+{
+	u64 val64;
+	u32 i = 0;
+	vxge_hal_status_e ret = VXGE_HAL_FAIL;
+
+	vxge_os_udelay(10);
+
+	do {
+		val64 = vxge_os_pio_mem_read64(pdev, regh, reg);
+		if (op == 0 && !(val64 & mask)) {
+			return (VXGE_HAL_OK);
+		} else if (op == 1 && (val64 & mask) == mask)
+			return (VXGE_HAL_OK);
+		vxge_os_udelay(100);
+	} while (++i <= 9);
+
+	do {
+		val64 = vxge_os_pio_mem_read64(pdev, regh, reg);
+		if (op == 0 && !(val64 & mask)) {
+			return (VXGE_HAL_OK);
+		} else if (op == 1 && (val64 & mask) == mask) {
+			return (VXGE_HAL_OK);
+		}
+		vxge_os_udelay(1000);
+	} while (++i < max_millis);
+
+	return (ret);
+}
+
+/*
+ * __hal_device_register_stall
+ * @pdev: PCI device object.
+ * @regh: BAR mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @reg: register to poll for
+ * @op: 0 - bit reset, 1 - bit set
+ * @mask: mask for logical "and" condition based on %op
+ * @max_millis: maximum time to try to poll in milliseconds
+ *
+ * Will poll certain register for specified amount of time.
+ * Will poll until masked bit is not cleared.
+ */
+vxge_hal_status_e
+__hal_device_register_stall(
+    pci_dev_h pdev,
+    pci_reg_h regh,
+    u64 *reg,
+    u32 op,
+    u64 mask,
+    u32 max_millis)
+{
+	u64 val64;
+	u32 i = 0;
+	vxge_hal_status_e ret = VXGE_HAL_FAIL;
+
+	vxge_os_stall(10);
+
+	do {
+		val64 = vxge_os_pio_mem_read64(pdev, regh, reg);
+		if (op == 0 && !(val64 & mask)) {
+			return (VXGE_HAL_OK);
+		} else if (op == 1 && (val64 & mask) == mask)
+			return (VXGE_HAL_OK);
+		vxge_os_stall(100);
+	} while (++i <= 9);
+
+	do {
+		val64 = vxge_os_pio_mem_read64(pdev, regh, reg);
+		if (op == 0 && !(val64 & mask)) {
+			return (VXGE_HAL_OK);
+		} else if (op == 1 && (val64 & mask) == mask) {
+			return (VXGE_HAL_OK);
+		}
+		vxge_os_stall(1000);
+	} while (++i < max_millis);
+
+	return (ret);
+}
+
+void*
+vxge_hal_device_get_legacy_reg(pci_dev_h pdev, pci_reg_h regh, u8 *bar0)
+{
+	vxge_hal_legacy_reg_t *legacy_reg = NULL;
+
+	/*
+	 * If length of Bar0 is 16MB, then assume we are configured
+	 * in MF8P_VP2 mode and add 8MB to get legacy_reg offsets
+	 */
+	if (vxge_os_pci_res_len(pdev, regh) == 0x1000000)
+		legacy_reg = (vxge_hal_legacy_reg_t *)
+		    ((void *) (bar0 + 0x800000));
+	else
+		legacy_reg = (vxge_hal_legacy_reg_t *)
+		    ((void *) bar0);
+
+	return (legacy_reg);
+}
+
+/*
+ * __hal_device_reg_addr_get
+ * @hldev: HAL Device object.
+ *
+ * This routine sets the swapper and reads the toc pointer and initializes the
+ * register location pointers in the device object. It waits until the ric is
+ * completed initializing registers.
+ */
+vxge_hal_status_e
+__hal_device_reg_addr_get(__hal_device_t *hldev)
+{
+	u64 val64;
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	hldev->legacy_reg = (vxge_hal_legacy_reg_t *)
+	    vxge_hal_device_get_legacy_reg(hldev->header.pdev,
+		hldev->header.regh0, hldev->header.bar0);
+
+	status = __hal_legacy_swapper_set(hldev->header.pdev,
+	    hldev->header.regh0,
+	    hldev->legacy_reg);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->legacy_reg->toc_first_pointer);
+
+	hldev->toc_reg = (vxge_hal_toc_reg_t *)
+	    ((void *) (hldev->header.bar0 + val64));
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_common_pointer);
+
+	hldev->common_reg = (vxge_hal_common_reg_t *)
+	    ((void *) (hldev->header.bar0 + val64));
+
+	vxge_hal_info_log_device("COMMON = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev->common_reg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_memrepair_pointer);
+
+	hldev->memrepair_reg = (vxge_hal_memrepair_reg_t *)
+	    ((void *) (hldev->header.bar0 + val64));
+
+	vxge_hal_info_log_device("MEM REPAIR = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev->memrepair_reg);
+
+	for (i = 0; i < VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES; i++) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->toc_reg->toc_pcicfgmgmt_pointer[i]);
+
+		hldev->pcicfgmgmt_reg[i] = (vxge_hal_pcicfgmgmt_reg_t *)
+		    ((void *) (hldev->header.bar0 + val64));
+		vxge_hal_info_log_device("PCICFG_MGMT[%d] = "
+		    "0x"VXGE_OS_STXFMT, i, (ptr_t) hldev->pcicfgmgmt_reg[i]);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_mrpcim_pointer);
+
+	hldev->mrpcim_reg = (vxge_hal_mrpcim_reg_t *)
+	    ((void *) (hldev->header.bar0 + val64));
+
+	vxge_hal_info_log_device("MEM REPAIR = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev->mrpcim_reg);
+
+	for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->toc_reg->toc_srpcim_pointer[i]);
+
+		hldev->srpcim_reg[i] = (vxge_hal_srpcim_reg_t *)
+		    ((void *) (hldev->header.bar0 + val64));
+		vxge_hal_info_log_device("SRPCIM[%d] =0x"VXGE_OS_STXFMT, i,
+		    (ptr_t) hldev->srpcim_reg[i]);
+	}
+
+	for (i = 0; i < VXGE_HAL_TITAN_VPMGMT_REG_SPACES; i++) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->toc_reg->toc_vpmgmt_pointer[i]);
+
+		hldev->vpmgmt_reg[i] = (vxge_hal_vpmgmt_reg_t *)
+		    ((void *) (hldev->header.bar0 + val64));
+
+		vxge_hal_info_log_device("VPMGMT[%d] = 0x"VXGE_OS_STXFMT, i,
+		    (ptr_t) hldev->vpmgmt_reg[i]);
+	}
+
+	for (i = 0; i < VXGE_HAL_TITAN_VPATH_REG_SPACES; i++) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->toc_reg->toc_vpath_pointer[i]);
+
+		hldev->vpath_reg[i] = (vxge_hal_vpath_reg_t *)
+		    ((void *) (hldev->header.bar0 + val64));
+
+		vxge_hal_info_log_device("VPATH[%d] = 0x"VXGE_OS_STXFMT, i,
+		    (ptr_t) hldev->vpath_reg[i]);
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_kdfc);
+
+	switch (VXGE_HAL_TOC_GET_KDFC_INITIAL_BIR(val64)) {
+	case 0:
+		hldev->kdfc = hldev->header.bar0 +
+		    VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val64);
+		break;
+	case 2:
+		hldev->kdfc = hldev->header.bar1 +
+		    VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val64);
+		break;
+	case 4:
+		hldev->kdfc = hldev->header.bar2 +
+		    VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val64);
+		break;
+	default:
+		vxge_hal_info_log_device("Invalid BIR = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) VXGE_HAL_TOC_GET_KDFC_INITIAL_BIR(val64));
+		break;
+	}
+
+	vxge_hal_info_log_device("KDFC = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev->kdfc);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_usdc);
+
+	switch (VXGE_HAL_TOC_GET_USDC_INITIAL_BIR(val64)) {
+	case 0:
+		hldev->usdc = hldev->header.bar0 +
+		    VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val64);
+		break;
+	case 2:
+		hldev->usdc = hldev->header.bar1 +
+		    VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val64);
+		break;
+	case 4:
+		hldev->usdc = hldev->header.bar2 +
+		    VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val64);
+		break;
+	default:
+		vxge_hal_info_log_device("Invalid BIR = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) VXGE_HAL_TOC_GET_USDC_INITIAL_BIR(val64));
+		break;
+	}
+
+	vxge_hal_info_log_device("USDC = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev->usdc);
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->vpath_rst_in_prog, 0,
+	    VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
+	    VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_err_log_device("%s:vpath_rst_in_prog is not cleared",
+		    __func__);
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_device_id_get
+ * @hldev: HAL Device object.
+ *
+ * This routine returns sets the device id and revision numbers into the device
+ * structure
+ */
+void
+__hal_device_id_get(__hal_device_t *hldev)
+{
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, device_id),
+	    2,
+	    &hldev->header.device_id);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, revision),
+	    2,
+	    &hldev->header.revision);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_device_access_rights_get: Get Access Rights of the driver
+ * @host_type: Host type.
+ * @func_id: Function Id
+ *
+ * This routine returns the Access Rights of the driver
+ */
+u32
+__hal_device_access_rights_get(u32 host_type, u32 func_id)
+{
+	u32 access_rights = VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH;
+
+	switch (host_type) {
+	case VXGE_HAL_NO_MR_NO_SR_NORMAL_FUNCTION:
+		if (func_id == 0) {
+			access_rights |=
+			    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM |
+			    VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM;
+		}
+		break;
+	case VXGE_HAL_MR_NO_SR_VH0_BASE_FUNCTION:
+		access_rights |= VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM |
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM;
+		break;
+	case VXGE_HAL_NO_MR_SR_VH0_FUNCTION0:
+		access_rights |= VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM |
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM;
+		break;
+	case VXGE_HAL_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
+	case VXGE_HAL_SR_VH_VIRTUAL_FUNCTION:
+		break;
+	case VXGE_HAL_MR_SR_VH0_INVALID_CONFIG:
+		break;
+	case VXGE_HAL_SR_VH_FUNCTION0:
+	case VXGE_HAL_VH_NORMAL_FUNCTION:
+		access_rights |= VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM;
+		break;
+	}
+
+	return (access_rights);
+}
+
+/*
+ * __hal_device_host_info_get
+ * @hldev: HAL Device object.
+ *
+ * This routine returns the host type assignments
+ */
+void
+__hal_device_host_info_get(__hal_device_t *hldev)
+{
+	u64 val64;
+	u32 i;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->host_type_assignments);
+
+	hldev->host_type = (u32)
+	    VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->vplane_assignments);
+
+	hldev->srpcim_id = (u32)
+	    VXGE_HAL_VPLANE_ASSIGNMENTS_GET_VPLANE_ASSIGNMENTS(val64);
+
+	hldev->vpath_assignments = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->vpath_assignments);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpath_assignments & mBIT(i)))
+			continue;
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->debug_assignments);
+		hldev->vh_id =
+		    (u32) VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VHLABEL(val64);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->vpmgmt_reg[i]->vpath_to_func_map_cfg1);
+		hldev->func_id =
+		    (u32) VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(val64);
+
+		hldev->access_rights = __hal_device_access_rights_get(
+		    hldev->host_type, hldev->func_id);
+
+		if (hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+			hldev->manager_up = TRUE;
+		} else {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->vpmgmt_reg[i]->srpcim_to_vpath_wmsg);
+
+			hldev->manager_up = __hal_ifmsg_is_manager_up(val64);
+		}
+
+		hldev->first_vp_id = i;
+
+		break;
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_device_pci_e_info_get - Get PCI_E bus informations such as link_width
+ *				  and signalling rate
+ * @hldev: HAL device.
+ * @signalling_rate:	pointer to a variable of enumerated type
+ *			vxge_hal_pci_e_signalling_rate_e {}.
+ * @link_width:		pointer to a variable of enumerated type
+ *			vxge_hal_pci_e_link_width_e {}.
+ *
+ * Get pci-e signalling rate and link width.
+ *
+ * Returns: one of the vxge_hal_status_e {} enumerated types.
+ * VXGE_HAL_OK			- for success.
+ * VXGE_HAL_ERR_INVALID_PCI_INFO - for invalid PCI information from the card.
+ * VXGE_HAL_ERR_BAD_DEVICE_ID	- for invalid card.
+ *
+ */
+static vxge_hal_status_e
+__hal_device_pci_e_info_get(
+    __hal_device_t *hldev,
+    vxge_hal_pci_e_signalling_rate_e *signalling_rate,
+    vxge_hal_pci_e_link_width_e *link_width)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_pci_e_capability_t *pci_e_caps;
+
+	vxge_assert((hldev != NULL) && (signalling_rate != NULL) &&
+	    (link_width != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT
+	    ", signalling_rate = 0x"VXGE_OS_STXFMT", "
+	    "link_width = 0x"VXGE_OS_STXFMT, (ptr_t) hldev,
+	    (ptr_t) signalling_rate, (ptr_t) link_width);
+
+	pci_e_caps = (vxge_hal_pci_e_capability_t *)
+	    (((u8 *) &hldev->pci_config_space_bios) + hldev->pci_e_caps);
+
+	switch (pci_e_caps->pci_e_lnkcap & VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED) {
+	case VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5:
+		*signalling_rate = VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LS_5:
+		*signalling_rate = VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB;
+		break;
+	default:
+		*signalling_rate =
+		    VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN;
+		break;
+	}
+
+	switch ((pci_e_caps->pci_e_lnksta &
+	    VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4) {
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X1:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X1;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X2:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X2;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X4:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X4;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X8:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X8;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X12:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X12;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X16:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X16;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_X32:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_X32;
+		break;
+	case VXGE_HAL_PCI_EXP_LNKCAP_LW_RES:
+	default:
+		*link_width = VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN;
+		break;
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (status);
+}
+
+/*
+ * __hal_device_hw_initialize
+ * @hldev: HAL device handle.
+ *
+ * Initialize X3100-V hardware.
+ */
+vxge_hal_status_e
+__hal_device_hw_initialize(__hal_device_t *hldev)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	__hal_device_pci_e_init(hldev);
+
+	/* update the pci mode, frequency, and width */
+	if (__hal_device_pci_e_info_get(hldev, &hldev->header.signalling_rate,
+	    &hldev->header.link_width) != VXGE_HAL_OK) {
+		hldev->header.signalling_rate =
+		    VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN;
+		hldev->header.link_width = VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN;
+		/*
+		 * FIXME: this cannot happen.
+		 * But if it happens we cannot continue just like that
+		 */
+		vxge_hal_err_log_device("unable to get pci info == > %s : %d",
+		    __func__, __LINE__);
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM) {
+		status = __hal_srpcim_initialize(hldev);
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+		status = __hal_mrpcim_initialize(hldev);
+	}
+
+	if (status == VXGE_HAL_OK) {
+		hldev->hw_is_initialized = 1;
+		hldev->header.terminating = 0;
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_reset - Reset device.
+ * @devh: HAL device handle.
+ *
+ * Soft-reset the device, reset the device stats except reset_cnt.
+ *
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_reset(vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!hldev->header.is_initialized) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+		return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		status = vxge_hal_vpath_reset(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_err_log_device("vpath %d Reset Failed", i);
+		}
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_reset_poll - Poll the device for reset complete.
+ * @devh: HAL device handle.
+ *
+ * Poll the device for reset complete
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_reset_poll(vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!hldev->header.is_initialized) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+		return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		status = vxge_hal_vpath_reset_poll(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_err_log_device("vpath %d Reset Poll Failed",
+			    i);
+		}
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_device_mrpcim_reset_poll - Poll the device for mrpcim reset complete
+ * @devh: HAL device handle.
+ *
+ * Poll the device for mrpcim reset complete
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ * VXGE_HAL_ERR_MANAGER_NOT_FOUND - MRPCIM/SRPCIM manager not found
+ * VXGE_HAL_ERR_TIME_OUT - Device Reset timed out
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_mrpcim_reset_poll(vxge_hal_device_h devh)
+{
+	u32 i = 0;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!hldev->header.is_initialized) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+		return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+	}
+
+	if (!hldev->manager_up) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_MANAGER_NOT_FOUND);
+		return (VXGE_HAL_ERR_MANAGER_NOT_FOUND);
+	}
+
+	status = __hal_ifmsg_device_reset_end_poll(
+	    hldev, hldev->first_vp_id);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_TIME_OUT);
+		return (VXGE_HAL_ERR_TIME_OUT);
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		status = vxge_hal_vpath_reset_poll(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_err_log_device("vpath %d Reset Poll Failed",
+			    i);
+		}
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_device_status - Check whether X3100 hardware is ready for
+ * operation.
+ * @devh: HAL device handle.
+ * @hw_status: X3100 status register. Returned by HAL.
+ *
+ * Check whether X3100 hardware is ready for operation.
+ * The checking includes TDMA, RDMA, PFC, PIC, MC_DRAM, and the rest
+ * hardware functional blocks.
+ *
+ * Returns: VXGE_HAL_OK if the device is ready for operation. Otherwise
+ * returns VXGE_HAL_FAIL. Also, fills in  adapter status (in @hw_status).
+ *
+ * See also: vxge_hal_status_e {}.
+ * Usage: See ex_open {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_status(vxge_hal_device_h devh, u64 *hw_status)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (hw_status != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	*hw_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->adapter_status);
+
+	vxge_hal_trace_log_device("Adapter_Status = 0x"VXGE_OS_LLXFMT,
+	    *hw_status);
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_RTDMA_RTDMA_READY)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_RTDMA_RTDMA_READY);
+		return (VXGE_HAL_ERR_RTDMA_RTDMA_READY);
+	}
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_WRDMA_WRDMA_READY)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_WRDMA_WRDMA_READY);
+		return (VXGE_HAL_ERR_WRDMA_WRDMA_READY);
+	}
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_KDFC_KDFC_READY)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_KDFC_KDFC_READY);
+		return (VXGE_HAL_ERR_KDFC_KDFC_READY);
+	}
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY);
+		return (VXGE_HAL_ERR_TPA_TMAC_BUF_EMPTY);
+	}
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT);
+		return (VXGE_HAL_ERR_RDCTL_PIC_QUIESCENT);
+	}
+
+	if (*hw_status & VXGE_HAL_ADAPTER_STATUS_XGMAC_NETWORK_FAULT) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_XGMAC_NETWORK_FAULT);
+		return (VXGE_HAL_ERR_XGMAC_NETWORK_FAULT);
+	}
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT);
+		return (VXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT);
+	}
+
+	if (!(*hw_status &
+	    VXGE_HAL_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY);
+		return (VXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READY);
+	}
+
+	if (!(*hw_status &
+	    VXGE_HAL_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY);
+		return (VXGE_HAL_ERR_G3IF_CM_G3IF_CM_GDDR3_READY);
+	}
+
+#ifndef	VXGE_HAL_TITAN_EMULATION
+	if (*hw_status & VXGE_HAL_ADAPTER_STATUS_RIC_RIC_RUNNING) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_RIC_RIC_RUNNING);
+		return (VXGE_HAL_ERR_RIC_RIC_RUNNING);
+	}
+#endif
+
+	if (*hw_status & VXGE_HAL_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK);
+		return (VXGE_HAL_ERR_CMG_C_PLL_IN_LOCK);
+	}
+
+	if (*hw_status & VXGE_HAL_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK);
+		return (VXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCK);
+	}
+
+	if (*hw_status & VXGE_HAL_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK);
+		return (VXGE_HAL_ERR_FBIF_M_PLL_IN_LOCK);
+	}
+
+	if (!(*hw_status & VXGE_HAL_ADAPTER_STATUS_PCC_PCC_IDLE(0xFF))) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PCC_PCC_IDLE);
+		return (VXGE_HAL_ERR_PCC_PCC_IDLE);
+	}
+
+	if (!(*hw_status &
+	    VXGE_HAL_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(0xFF))) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT);
+		return (VXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENT);
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0x"VXGE_OS_STXFMT,
+	    __FILE__, __func__, __LINE__, (ptr_t) *hw_status);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_is_slot_freeze
+ * @devh: the device
+ *
+ * Returns non-zero if the slot is freezed.
+ * The determination is made based on the adapter_status
+ * register which will never give all FFs, unless PCI read
+ * cannot go through.
+ */
+int
+vxge_hal_device_is_slot_freeze(vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	u16 device_id;
+	u64 adapter_status;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	adapter_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->adapter_status);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, device_id),
+	    2,
+	    &device_id);
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__,
+	    (adapter_status == VXGE_HAL_ALL_FOXES) || (device_id == 0xffff));
+
+	return ((adapter_status == VXGE_HAL_ALL_FOXES) ||
+	    (device_id == 0xffff));
+}
+
+/*
+ * vxge_hal_device_intr_enable - Enable interrupts.
+ * @devh: HAL device handle.
+ * @op: One of the vxge_hal_device_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to enable.
+ *
+ * Enable X3100 interrupts. The function is to be executed the last in
+ * X3100 initialization sequence.
+ *
+ * See also: vxge_hal_device_intr_disable()
+ */
+void
+vxge_hal_device_intr_enable(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	u64 val64;
+	u32 val32;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	vxge_hal_device_mask_all(hldev);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		(void) __hal_vpath_intr_enable(&hldev->virtual_paths[i]);
+	}
+
+	if ((hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_IRQLINE) ||
+	    (hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_EMULATED_INTA)) {
+
+		val64 = hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_BMAP];
+
+		if (val64 != 0) {
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &hldev->common_reg->tim_int_status0);
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    ~val64,
+			    &hldev->common_reg->tim_int_mask0);
+		}
+
+		val32 = hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_BMAP];
+
+		if (val32 != 0) {
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val32,
+			    &hldev->common_reg->tim_int_status1);
+
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    ~val32,
+			    &hldev->common_reg->tim_int_mask1);
+		}
+	}
+
+	vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->titan_general_int_status);
+
+	vxge_hal_device_unmask_all(hldev);
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_intr_disable - Disable X3100 interrupts.
+ * @devh: HAL device handle.
+ * @op: One of the vxge_hal_device_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to disable.
+ *
+ * Disable X3100 interrupts.
+ *
+ * See also: vxge_hal_device_intr_enable()
+ */
+void
+vxge_hal_device_intr_disable(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	u64 val64;
+	u32 val32;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	vxge_hal_device_mask_all(hldev);
+
+	if ((hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_IRQLINE) ||
+	    (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA)) {
+
+		val64 = hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_BMAP];
+
+		if (val64 != 0) {
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &hldev->common_reg->tim_int_mask0);
+		}
+
+		val32 = hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_BMAP];
+
+		if (val32 != 0) {
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val32,
+			    &hldev->common_reg->tim_int_mask1);
+		}
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		(void) __hal_vpath_intr_disable(&hldev->virtual_paths[i]);
+	}
+
+	vxge_hal_device_unmask_all(hldev);
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_mask_all - Mask all device interrupts.
+ * @devh: HAL device handle.
+ *
+ * Mask	all	device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_all()
+ */
+void
+vxge_hal_device_mask_all(
+    vxge_hal_device_h devh)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	val64 = VXGE_HAL_TITAN_MASK_ALL_INT_ALARM |
+	    VXGE_HAL_TITAN_MASK_ALL_INT_TRAFFIC;
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->titan_mask_all_int);
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_unmask_all - Unmask all device interrupts.
+ * @devh: HAL device handle.
+ *
+ * Unmask all device interrupts.
+ *
+ * See also: vxge_hal_device_mask_all()
+ */
+void
+vxge_hal_device_unmask_all(
+    vxge_hal_device_h devh)
+{
+	u64 val64 = 0;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_IRQLINE)
+		val64 = VXGE_HAL_TITAN_MASK_ALL_INT_TRAFFIC;
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->titan_mask_all_int);
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_begin_irq - Begin IRQ processing.
+ * @devh: HAL device handle.
+ * @skip_alarms: Do not clear the alarms
+ * @reason: "Reason" for the interrupt,	the value of X3100's
+ *			general_int_status register.
+ *
+ * The function	performs two actions, It first checks whether (shared IRQ) the
+ * interrupt was raised	by the device. Next, it	masks the device interrupts.
+ *
+ * Note:
+ * vxge_hal_device_begin_irq() does not flush MMIO writes through the
+ * bridge. Therefore, two back-to-back interrupts are potentially possible.
+ * It is the responsibility	of the ULD to make sure	that only one
+ * vxge_hal_device_continue_irq() runs at a time.
+ *
+ * Returns: 0, if the interrupt	is not "ours" (note that in this case the
+ * device remain enabled).
+ * Otherwise, vxge_hal_device_begin_irq() returns 64bit general adapter
+ * status.
+ * See also: vxge_hal_device_handle_irq()
+ */
+vxge_hal_status_e
+vxge_hal_device_begin_irq(
+    vxge_hal_device_h devh,
+    u32 skip_alarms,
+    u64 *reason)
+{
+	u32 i;
+	u64 val64;
+	u64 adapter_status;
+	u64 vpath_mask;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vxge_hal_status_e ret = VXGE_HAL_ERR_WRONG_IRQ;
+	vxge_hal_status_e status;
+
+	vxge_assert((hldev != NULL) && (reason != NULL));
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq(
+	    "devh = 0x"VXGE_OS_STXFMT", skip_alarms = %d, "
+	    "reason = 0x"VXGE_OS_STXFMT, (ptr_t) devh,
+	    skip_alarms, (ptr_t) reason);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->titan_general_int_status);
+
+	if (vxge_os_unlikely(!val64)) {
+		/* not Titan interrupt	 */
+		*reason = 0;
+		ret = VXGE_HAL_ERR_WRONG_IRQ;
+		vxge_hal_info_log_device_irq("wrong_isr general_int_status = \
+		    0x%llx", val64);
+		vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, ret);
+		return (ret);
+	}
+
+	if (vxge_os_unlikely(val64 == VXGE_HAL_ALL_FOXES)) {
+
+		adapter_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->adapter_status);
+
+		if (adapter_status == VXGE_HAL_ALL_FOXES) {
+			vxge_hal_info_log_device_irq("%s:Slot is frozen",
+			    __func__);
+			__hal_device_handle_error(hldev,
+			    NULL_VPID, VXGE_HAL_EVENT_SLOT_FREEZE);
+			*reason = 0;
+			ret = VXGE_HAL_ERR_SLOT_FREEZE;
+			goto exit;
+
+		}
+	}
+
+	*reason = val64;
+
+	vpath_mask = hldev->vpaths_deployed >>
+	    (64 - VXGE_HAL_MAX_VIRTUAL_PATHS);
+
+	if (val64 &
+	    VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) {
+		hldev->header.traffic_intr_cnt++;
+		ret = VXGE_HAL_TRAFFIC_INTERRUPT;
+		vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, ret);
+		return (ret);
+	}
+
+	hldev->header.not_traffic_intr_cnt++;
+
+	if (vxge_os_unlikely(val64 &
+	    VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
+
+		for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+			if (!(hldev->vpaths_deployed & mBIT(i)))
+				continue;
+
+			status = __hal_vpath_alarm_process(
+			    &hldev->virtual_paths[i],
+			    skip_alarms);
+
+			if (status != VXGE_HAL_ERR_WRONG_IRQ)
+				ret = status;
+
+		}
+
+	}
+exit:
+	vxge_hal_trace_log_device_irq(
+	    "<==Error in  %s:%s:%d result = 0x%x general_int_status= 0x%llx",
+	    __FILE__, __func__, __LINE__, ret, val64);
+	return (ret);
+}
+
+/*
+ * vxge_hal_device_continue_irq - Continue handling IRQ:	process	all
+ *				completed descriptors.
+ * @devh: HAL device handle.
+ *
+ * Process completed descriptors and unmask the	device interrupts.
+ *
+ * The vxge_hal_device_continue_irq() walks all open virtual paths
+ * and calls upper-layer driver	(ULD) via supplied completion
+ * callback.
+ *
+ * Note	that the vxge_hal_device_continue_irq is	part of	the _fast_ path.
+ * To optimize the processing, the function does _not_ check for
+ * errors and alarms.
+ *
+ * Returns: VXGE_HAL_OK.
+ *
+ * See also: vxge_hal_device_handle_irq()
+ * vxge_hal_ring_rxd_next_completed(),
+ * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {},
+ * vxge_hal_fifo_callback_f {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_continue_irq(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d", __FILE__,
+	    __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		(void) vxge_hal_vpath_continue_irq(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
+
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_handle_irq - Handle device IRQ.
+ * @devh: HAL device handle.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Perform the complete	handling of the	line interrupt.	The function
+ * performs two	calls.
+ * First it uses vxge_hal_device_begin_irq() to check the reason for
+ * the interrupt and mask the device interrupts.
+ * Second, it calls	vxge_hal_device_continue_irq() to process all
+ * completed descriptors and re-enable the interrupts.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device.
+ *
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq().
+ */
+vxge_hal_status_e
+vxge_hal_device_handle_irq(
+    vxge_hal_device_h devh,
+    u32 skip_alarms)
+{
+	u64 reason;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT", \
+	    skip_alarms = %d",
+	    (ptr_t) devh, skip_alarms);
+
+	vxge_hal_device_mask_all(hldev);
+
+	status = vxge_hal_device_begin_irq(hldev, skip_alarms, &reason);
+	if (vxge_os_unlikely(status == VXGE_HAL_ERR_WRONG_IRQ)) {
+		vxge_hal_device_unmask_all(hldev);
+		goto exit;
+	}
+	if (status == VXGE_HAL_TRAFFIC_INTERRUPT) {
+
+		vxge_hal_device_clear_rx(hldev);
+
+		status = vxge_hal_device_continue_irq(hldev);
+
+		vxge_hal_device_clear_tx(hldev);
+
+	}
+
+	if (vxge_os_unlikely((status == VXGE_HAL_ERR_CRITICAL) && skip_alarms))
+		/* ULD needs to unmask explicitely */
+		goto exit;
+
+	vxge_hal_device_unmask_all(hldev);
+
+exit:
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_device_handle_link_up_ind
+ * @hldev: HAL device handle.
+ *
+ * Link up indication handler. The function is invoked by HAL when
+ * X3100 indicates that the link is up for programmable amount of time.
+ */
+vxge_hal_status_e
+__hal_device_handle_link_up_ind(__hal_device_t *hldev)
+{
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	/*
+	 * If the previous link state is not down, return.
+	 */
+	if (hldev->header.link_state == VXGE_HAL_LINK_UP) {
+		vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	hldev->header.link_state = VXGE_HAL_LINK_UP;
+
+	/* notify ULD */
+	if (g_vxge_hal_driver->uld_callbacks.link_up) {
+		g_vxge_hal_driver->uld_callbacks.link_up(
+		    hldev,
+		    hldev->header.upper_layer_data);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_device_handle_link_down_ind
+ * @hldev: HAL device handle.
+ *
+ * Link down indication handler. The function is invoked by HAL when
+ * X3100 indicates that the link is down.
+ */
+vxge_hal_status_e
+__hal_device_handle_link_down_ind(__hal_device_t *hldev)
+{
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	/*
+	 * If the previous link state is not down, return.
+	 */
+	if (hldev->header.link_state == VXGE_HAL_LINK_DOWN) {
+		vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	hldev->header.link_state = VXGE_HAL_LINK_DOWN;
+
+	/* notify ULD */
+	if (g_vxge_hal_driver->uld_callbacks.link_down) {
+		g_vxge_hal_driver->uld_callbacks.link_down(
+		    hldev,
+		    hldev->header.upper_layer_data);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_link_state_test - Test the link state.
+ * @devh: HAL device handle.
+ *
+ * Test link state.
+ * Returns: link state.
+ */
+vxge_hal_device_link_state_e
+vxge_hal_device_link_state_test(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_device_link_state_e status = VXGE_HAL_LINK_NONE;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpath_assignments & mBIT(i)))
+			continue;
+
+		status =
+		    __hal_vpath_link_state_test(&hldev->virtual_paths[i]);
+
+		break;
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_link_state_poll - Poll for the link state.
+ * @devh: HAL device handle.
+ *
+ * Get link state.
+ * Returns: link state.
+ */
+vxge_hal_device_link_state_e
+vxge_hal_device_link_state_poll(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_device_link_state_e link_state = VXGE_HAL_LINK_NONE;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpath_assignments & mBIT(i)))
+			continue;
+
+		hldev->header.link_state = VXGE_HAL_LINK_NONE;
+
+		link_state =
+		    __hal_vpath_link_state_poll(&hldev->virtual_paths[i]);
+
+		break;
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, link_state);
+	return (link_state);
+}
+
+/*
+ * vxge_hal_device_data_rate_poll - Poll for the data rate.
+ * @devh: HAL device handle.
+ *
+ * Get data rate.
+ * Returns: data rate.
+ */
+vxge_hal_device_data_rate_e
+vxge_hal_device_data_rate_poll(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_device_data_rate_e data_rate = VXGE_HAL_DATA_RATE_UNKNOWN;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		data_rate =
+		    __hal_vpath_data_rate_poll(&hldev->virtual_paths[i]);
+
+		break;
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, data_rate);
+	return (data_rate);
+}
+
+/*
+ * vxge_hal_device_lag_mode_get - Get Current LAG Mode
+ * @devh: HAL device handle.
+ *
+ * Get Current LAG Mode
+ */
+vxge_hal_device_lag_mode_e
+vxge_hal_device_lag_mode_get(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_device_lag_mode_e lag_mode = VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		lag_mode =
+		    __hal_vpath_lag_mode_get(&hldev->virtual_paths[i]);
+
+		break;
+
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, lag_mode);
+	return (lag_mode);
+}
+
+
+/*
+ * __hal_device_handle_error - Handle error
+ * @hldev: HAL device
+ * @vp_id: Vpath Id
+ * @type: Error type. Please see vxge_hal_event_e {}
+ *
+ * Handle error.
+ */
+void
+__hal_device_handle_error(
+    __hal_device_t *hldev,
+    u32 vp_id,
+    vxge_hal_event_e type)
+{
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq(
+	    "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, type = %d",
+	    (ptr_t) hldev, vp_id, type);
+
+	switch (type) {
+	default:
+		vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_TYPE);
+		return;
+	case VXGE_HAL_EVENT_UNKNOWN:
+		if (hldev->header.config.dump_on_unknown) {
+			(void) vxge_hal_aux_device_dump(hldev);
+		}
+		break;
+	case VXGE_HAL_EVENT_SERR:
+		if (hldev->header.config.dump_on_serr) {
+			(void) vxge_hal_aux_device_dump(hldev);
+		}
+		break;
+	case VXGE_HAL_EVENT_CRITICAL:
+	case VXGE_HAL_EVENT_SRPCIM_CRITICAL:
+	case VXGE_HAL_EVENT_MRPCIM_CRITICAL:
+		if (hldev->header.config.dump_on_critical) {
+			(void) vxge_hal_aux_device_dump(hldev);
+		}
+		break;
+	case VXGE_HAL_EVENT_ECCERR:
+		if (hldev->header.config.dump_on_eccerr) {
+			(void) vxge_hal_aux_device_dump(hldev);
+		}
+		break;
+	case VXGE_HAL_EVENT_KDFCCTL:
+		break;
+	case VXGE_HAL_EVENT_DEVICE_RESET_START:
+		break;
+	case VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE:
+		break;
+	case VXGE_HAL_EVENT_VPATH_RESET_START:
+		break;
+	case VXGE_HAL_EVENT_VPATH_RESET_COMPLETE:
+		break;
+	case VXGE_HAL_EVENT_SLOT_FREEZE:
+		break;
+	}
+
+
+	/* notify ULD */
+	if (g_vxge_hal_driver->uld_callbacks.crit_err) {
+		g_vxge_hal_driver->uld_callbacks.crit_err(
+		    (vxge_hal_device_h) hldev,
+		    hldev->header.upper_layer_data,
+		    type,
+		    vp_id);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_mask_tx - Mask Tx interrupts.
+ * @devh: HAL device.
+ *
+ * Mask	Tx device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_tx(), vxge_hal_device_mask_rx(),
+ * vxge_hal_device_clear_tx().
+ */
+void
+vxge_hal_device_mask_tx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX],
+		    &hldev->common_reg->tim_int_mask0);
+	}
+
+	if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX],
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_clear_tx - Acknowledge (that is, clear) the
+ * condition that has caused the TX	interrupt.
+ * @devh: HAL device.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Tx interrupt.
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(),
+ * vxge_hal_device_clear_rx(), vxge_hal_device_mask_tx().
+ */
+void
+vxge_hal_device_clear_tx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX],
+		    &hldev->common_reg->tim_int_status0);
+	}
+
+	if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX],
+		    &hldev->common_reg->tim_int_status1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_unmask_tx - Unmask Tx	interrupts.
+ * @devh: HAL device.
+ *
+ * Unmask Tx device interrupts.
+ *
+ * See also: vxge_hal_device_mask_tx(), vxge_hal_device_clear_tx().
+ */
+void
+vxge_hal_device_unmask_tx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    ~(hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX]),
+		    &hldev->common_reg->tim_int_mask0);
+	}
+
+	if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    ~(hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX]),
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_mask_rx - Mask Rx	interrupts.
+ * @devh: HAL device.
+ *
+ * Mask	Rx device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_rx(), vxge_hal_device_mask_tx(),
+ * vxge_hal_device_clear_rx().
+ */
+void
+vxge_hal_device_mask_rx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX],
+		    &hldev->common_reg->tim_int_mask0);
+	}
+
+	if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX],
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_clear_rx - Acknowledge (that is, clear) the
+ * condition that has caused the RX	interrupt.
+ * @devh: HAL device.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Rx interrupt.
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(),
+ * vxge_hal_device_clear_tx(), vxge_hal_device_mask_rx().
+ */
+void
+vxge_hal_device_clear_rx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX],
+		    &hldev->common_reg->tim_int_status0);
+	}
+
+	if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX],
+		    &hldev->common_reg->tim_int_status1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_unmask_rx - Unmask Rx	interrupts.
+ * @devh: HAL device.
+ *
+ * Unmask Rx device interrupts.
+ *
+ * See also: vxge_hal_device_mask_rx(), vxge_hal_device_clear_rx().
+ */
+void
+vxge_hal_device_unmask_rx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    ~(hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_mask0);
+	}
+
+	if (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    ~(hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_mask_tx_rx - Mask Tx and Rx interrupts.
+ * @devh: HAL device.
+ *
+ * Mask Tx and Rx device interrupts.
+ *
+ * See also: vxge_hal_device_unmask_tx_rx(), vxge_hal_device_clear_tx_rx().
+ */
+void
+vxge_hal_device_mask_tx_rx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if ((hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) ||
+	    (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0)) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_mask0);
+	}
+
+	if ((hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) ||
+	    (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0)) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_clear_tx_rx - Acknowledge (that is, clear) the
+ * condition that has caused the Tx and RX interrupt.
+ * @devh: HAL device.
+ *
+ * Acknowledge (that is, clear)	the	condition that has caused
+ * the Tx and Rx interrupt.
+ * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(),
+ * vxge_hal_device_mask_tx_rx(), vxge_hal_device_unmask_tx_rx().
+ */
+void
+vxge_hal_device_clear_tx_rx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if ((hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) ||
+	    (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0)) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_status0);
+	}
+
+	if ((hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) ||
+	    (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0)) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_status1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_unmask_tx_rx - Unmask Tx and Rx interrupts.
+ * @devh: HAL device.
+ *
+ * Unmask Rx device interrupts.
+ *
+ * See also: vxge_hal_device_mask_tx_rx(), vxge_hal_device_clear_tx_rx().
+ */
+void
+vxge_hal_device_unmask_tx_rx(
+    vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_device_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if ((hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] != 0) ||
+	    (hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX] != 0)) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    ~(hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask0[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_mask0);
+	}
+
+	if ((hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] != 0) ||
+	    (hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX] != 0)) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    ~(hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_TX] |
+		    hldev->tim_int_mask1[VXGE_HAL_VPATH_INTR_RX]),
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_device_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_hw_info_get - Get the hw information
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @bar0: Address of BAR0 in PCI config
+ * @hw_info: Buffer to return vxge_hal_device_hw_info_t {} structure
+ *
+ * Returns the vpath mask that has the bits set for each vpath allocated
+ * for the driver, FW version information and the first mac addresse for
+ * each vpath
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_info_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u8 *bar0,
+    vxge_hal_device_hw_info_t *hw_info)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_legacy_reg_t *legacy_reg;
+	vxge_hal_toc_reg_t *toc_reg;
+	vxge_hal_mrpcim_reg_t *mrpcim_reg;
+	vxge_hal_common_reg_t *common_reg;
+	vxge_hal_vpath_reg_t *vpath_reg;
+	vxge_hal_vpmgmt_reg_t *vpmgmt_reg;
+	vxge_hal_status_e status;
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "bar0 = 0x"VXGE_OS_STXFMT", hw_info = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0, (ptr_t) hw_info);
+
+	vxge_assert((bar0 != NULL) && (hw_info != NULL));
+
+	vxge_os_memzero(hw_info, sizeof(vxge_hal_device_hw_info_t));
+
+	legacy_reg = (vxge_hal_legacy_reg_t *)
+	    vxge_hal_device_get_legacy_reg(pdev, regh0, bar0);
+
+	status = __hal_legacy_swapper_set(pdev, regh0, legacy_reg);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &legacy_reg->toc_first_pointer);
+
+	toc_reg = (vxge_hal_toc_reg_t *) ((void *) (bar0 + val64));
+
+	val64 =
+	    vxge_os_pio_mem_read64(pdev, regh0, &toc_reg->toc_common_pointer);
+
+	common_reg = (vxge_hal_common_reg_t *) ((void *) (bar0 + val64));
+
+	status = vxge_hal_device_register_poll(pdev, regh0,
+	    &common_reg->vpath_rst_in_prog, 0,
+	    VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
+	    VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	hw_info->vpath_mask = vxge_os_pio_mem_read64(pdev, regh0,
+	    &common_reg->vpath_assignments);
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &common_reg->host_type_assignments);
+
+	hw_info->host_type = (u32)
+	    VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!((hw_info->vpath_mask) & mBIT(i)))
+			continue;
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &toc_reg->toc_vpmgmt_pointer[i]);
+
+		vpmgmt_reg = (vxge_hal_vpmgmt_reg_t *)
+		    ((void *) (bar0 + val64));
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpmgmt_reg->vpath_to_func_map_cfg1);
+		hw_info->func_id = (u32)
+		    VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(
+		    val64);
+
+		if (__hal_device_access_rights_get(hw_info->host_type,
+		    hw_info->func_id) & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+			val64 = vxge_os_pio_mem_read64(pdev, regh0,
+			    &toc_reg->toc_mrpcim_pointer);
+
+			mrpcim_reg = (vxge_hal_mrpcim_reg_t *)
+			    ((void *) (bar0 + val64));
+
+			vxge_os_pio_mem_write64(pdev, regh0,
+			    0,
+			    &mrpcim_reg->xgmac_gen_fw_memo_mask);
+			vxge_os_wmb();
+		}
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &toc_reg->toc_vpath_pointer[i]);
+
+		vpath_reg = (vxge_hal_vpath_reg_t *) ((void *) (bar0 + val64));
+
+		(void) __hal_vpath_fw_flash_ver_get(pdev, regh0, i, vpath_reg,
+		    &hw_info->fw_version,
+		    &hw_info->fw_date,
+		    &hw_info->flash_version,
+		    &hw_info->flash_date);
+
+		(void) __hal_vpath_card_info_get(pdev, regh0, i, vpath_reg,
+		    hw_info->serial_number,
+		    hw_info->part_number,
+		    hw_info->product_description);
+
+		(void) __hal_vpath_pmd_info_get(pdev, regh0, i, vpath_reg,
+		    &hw_info->ports,
+		    &hw_info->pmd_port0,
+		    &hw_info->pmd_port1);
+
+		hw_info->function_mode =
+		    __hal_vpath_pci_func_mode_get(pdev, regh0, i, vpath_reg);
+
+		break;
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!((hw_info->vpath_mask) & mBIT(i)))
+			continue;
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &toc_reg->toc_vpath_pointer[i]);
+
+		vpath_reg = (vxge_hal_vpath_reg_t *) ((void *) (bar0 + val64));
+
+		status = __hal_vpath_hw_addr_get(pdev, regh0, i, vpath_reg,
+		    hw_info->mac_addrs[i], hw_info->mac_addr_masks[i]);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+
+		}
+
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_initialize - Initialize X3100 device.
+ * @hldev: HAL device handle.
+ * @attr: pointer to vxge_hal_device_attr_t structure
+ * @device_config: Configuration to be _applied_ to the device,
+ *		For the X3100 configuration "knobs" please
+ *		refer to vxge_hal_device_config_t and X3100
+ *		User Guide.
+ *
+ * Initialize X3100 device. Note that all the arguments of this public API
+ * are 'IN', including @hldev. Upper-layer driver (ULD) cooperates with
+ * OS to find new X3100 device, locate its PCI and memory spaces.
+ *
+ * When done, the ULD allocates sizeof(__hal_device_t) bytes for HAL
+ * to enable the latter to perform X3100 hardware initialization.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - Driver is not initialized.
+ * VXGE_HAL_ERR_BAD_DEVICE_CONFIG - Device configuration params are not
+ * valid.
+ * VXGE_HAL_ERR_OUT_OF_MEMORY - Memory allocation failed.
+ * VXGE_HAL_ERR_BAD_SUBSYSTEM_ID - Device subsystem id is invalid.
+ * VXGE_HAL_ERR_INVALID_MAC_ADDRESS - Device mac address in not valid.
+ * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to retrieve the mac
+ * address within the time(timeout) or TTI/RTI initialization failed.
+ * VXGE_HAL_ERR_SWAPPER_CTRL - Failed to configure swapper control.
+ *
+ * See also: __hal_device_terminate(), vxge_hal_status_e {}
+ * vxge_hal_device_attr_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_device_initialize(
+    vxge_hal_device_h *devh,
+    vxge_hal_device_attr_t *attr,
+    vxge_hal_device_config_t *device_config)
+{
+	u32 i;
+	u32 nblocks = 0;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert((devh != NULL) &&
+	    (attr != NULL) && (device_config != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "devh = 0x"VXGE_OS_STXFMT", attr = 0x"VXGE_OS_STXFMT", "
+	    "device_config = 0x"VXGE_OS_STXFMT, (ptr_t) devh, (ptr_t) attr,
+	    (ptr_t) device_config);
+
+	/* sanity check */
+	if (g_vxge_hal_driver == NULL ||
+	    !g_vxge_hal_driver->is_initialized) {
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED);
+		return (VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED);
+	}
+
+	status = __hal_device_config_check(device_config);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	hldev = (__hal_device_t *) vxge_os_malloc(attr->pdev,
+	    sizeof(__hal_device_t));
+
+	if (hldev == NULL) {
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	vxge_os_memzero(hldev, sizeof(__hal_device_t));
+
+	hldev->header.magic = VXGE_HAL_DEVICE_MAGIC;
+
+	__hal_channel_init_pending_list(hldev);
+
+	vxge_hal_device_debug_set(hldev,
+	    device_config->debug_level,
+	    device_config->debug_mask);
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+	hldev->trace_buf.size = device_config->tracebuf_size;
+	hldev->trace_buf.data =
+	    (u8 *) vxge_os_malloc(attr->pdev, hldev->trace_buf.size);
+	if (hldev->trace_buf.data == NULL) {
+		vxge_os_printf("cannot allocate trace buffer!\n");
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+	hldev->trace_buf.offset = 0;
+	hldev->trace_buf.wrapped_count = 0;
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+#endif
+
+	vxge_hal_info_log_device("device 0x"VXGE_OS_STXFMT" is initializing",
+	    (ptr_t) hldev);
+
+	/* apply config */
+	vxge_os_memcpy(&hldev->header.config, device_config,
+	    sizeof(vxge_hal_device_config_t));
+
+	hldev->header.regh0 = attr->regh0;
+	hldev->header.regh1 = attr->regh1;
+	hldev->header.regh2 = attr->regh2;
+	hldev->header.bar0 = attr->bar0;
+	hldev->header.bar1 = attr->bar1;
+	hldev->header.bar2 = attr->bar2;
+	hldev->header.pdev = attr->pdev;
+	hldev->header.irqh = attr->irqh;
+	hldev->header.cfgh = attr->cfgh;
+
+	if ((status = __hal_device_reg_addr_get(hldev)) != VXGE_HAL_OK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		vxge_hal_device_terminate(hldev);
+		return (status);
+	}
+
+	__hal_device_id_get(hldev);
+
+	__hal_device_host_info_get(hldev);
+
+
+	nblocks += 1;		/* For MRPCIM stats */
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpath_assignments & mBIT(i)))
+			continue;
+
+		if (device_config->vp_config[i].ring.enable ==
+		    VXGE_HAL_RING_ENABLE) {
+			nblocks +=
+			    (device_config->vp_config[i].ring.ring_length +
+			    vxge_hal_ring_rxds_per_block_get(
+			    device_config->vp_config[i].ring.buffer_mode) - 1) /
+			    vxge_hal_ring_rxds_per_block_get(
+			    device_config->vp_config[i].ring.buffer_mode);
+		}
+
+		if ((device_config->vp_config[i].fifo.enable ==
+		    VXGE_HAL_FIFO_ENABLE) &&
+		    ((device_config->vp_config[i].fifo.max_frags *
+		    sizeof(vxge_hal_fifo_txd_t)) <=
+		    VXGE_OS_HOST_PAGE_SIZE)) {
+			nblocks +=
+			    ((device_config->vp_config[i].fifo.fifo_length *
+			    sizeof(vxge_hal_fifo_txd_t) *
+			    device_config->vp_config[i].fifo.max_frags) +
+			    VXGE_OS_HOST_PAGE_SIZE - 1) /
+			    VXGE_OS_HOST_PAGE_SIZE;
+		}
+
+
+		nblocks += 1;	/* For vpath stats */
+
+	}
+
+	if (__hal_blockpool_create(hldev,
+	    &hldev->block_pool,
+	    device_config->dma_blockpool_initial + nblocks,
+	    device_config->dma_blockpool_incr,
+	    device_config->dma_blockpool_min,
+	    device_config->dma_blockpool_max + nblocks) != VXGE_HAL_OK) {
+		vxge_hal_info_log_device("%s:__hal_blockpool_create failed",
+		    __func__);
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_MEMORY);
+		vxge_hal_device_terminate(hldev);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+
+	status = __hal_device_hw_initialize(hldev);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		vxge_hal_device_terminate(hldev);
+		return (status);
+	}
+
+	hldev->dump_buf = (char *) vxge_os_malloc(hldev->header.pdev,
+	    VXGE_HAL_DUMP_BUF_SIZE);
+	if (hldev->dump_buf == NULL) {
+		vxge_hal_info_log_device("%s:vxge_os_malloc failed ",
+		    __func__);
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_MEMORY);
+		vxge_hal_device_terminate(hldev);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	hldev->header.is_initialized = 1;
+
+	*devh = hldev;
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_device_terminate - Terminate X3100 device.
+ * @devh: HAL device handle.
+ *
+ * Terminate HAL device.
+ *
+ * See also: vxge_hal_device_initialize().
+ */
+void
+vxge_hal_device_terminate(vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(g_vxge_hal_driver != NULL);
+	vxge_assert(hldev != NULL);
+	vxge_assert(hldev->header.magic == VXGE_HAL_DEVICE_MAGIC);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	hldev->header.terminating = 1;
+	hldev->header.is_initialized = 0;
+	hldev->in_poll = 0;
+	hldev->header.magic = VXGE_HAL_DEVICE_DEAD;
+
+	if (hldev->dump_buf) {
+		vxge_os_free(hldev->header.pdev, hldev->dump_buf,
+		    VXGE_HAL_DUMP_BUF_SIZE);
+		hldev->dump_buf = NULL;
+	}
+
+	if (hldev->srpcim != NULL)
+		(void) __hal_srpcim_terminate(hldev);
+
+	if (hldev->mrpcim != NULL)
+		(void) __hal_mrpcim_terminate(hldev);
+
+	__hal_channel_destroy_pending_list(hldev);
+
+
+	__hal_blockpool_destroy(&hldev->block_pool);
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+	if (hldev->trace_buf.size) {
+		vxge_os_free(NULL,
+		    hldev->trace_buf.data,
+		    hldev->trace_buf.size);
+	}
+#endif
+
+	vxge_os_free(hldev->header.pdev, hldev, sizeof(__hal_device_t));
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_device_enable - Enable device.
+ * @devh: HAL device handle.
+ *
+ * Enable the specified device: bring up the link/interface.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_enable(
+    vxge_hal_device_h devh)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!hldev->hw_is_initialized) {
+
+		status = __hal_device_hw_initialize(hldev);
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	__hal_device_bus_master_enable(hldev);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_disable - Disable X3100 adapter.
+ * @devh: HAL device handle.
+ *
+ * Disable this device. To gracefully reset the adapter, the host should:
+ *
+ *	- call vxge_hal_device_disable();
+ *
+ *	- call vxge_hal_device_intr_disable();
+ *
+ *	- do some work (error recovery, change mtu, reset, etc);
+ *
+ *	- call vxge_hal_device_enable();
+ *
+ *	- call vxge_hal_device_intr_enable().
+ *
+ * Note: Disabling the device does _not_ include disabling of interrupts.
+ * After disabling the device stops receiving new frames but those frames
+ * that were already in the pipe will keep coming for some few milliseconds.
+ *
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_disable(
+    vxge_hal_device_h devh)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(devh != NULL);
+
+#if (VXGE_COMPONENT_HAL_DEVICE & VXGE_DEBUG_MODULE_MASK)
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+#endif
+
+	return (status);
+}
+
+/*
+ * vxge_hal_device_hw_stats_enable - Enable device h/w statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA vpath statistics for the device. The function is to be called
+ * to re-enable the adapter to update stats into the host memory
+ *
+ * See also: vxge_hal_device_hw_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_stats_enable(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->stats_cfg0);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		vxge_os_memcpy(hldev->virtual_paths[i].hw_stats_sav,
+		    hldev->virtual_paths[i].hw_stats,
+		    sizeof(vxge_hal_vpath_stats_hw_info_t));
+		if (hldev->header.config.stats_read_method ==
+		    VXGE_HAL_STATS_READ_METHOD_DMA) {
+			val64 |=
+			    VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - i)));
+		} else {
+			status = __hal_vpath_hw_stats_get(
+			    &hldev->virtual_paths[i],
+			    hldev->virtual_paths[i].hw_stats);
+		}
+
+	}
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->stats_cfg0);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_hw_stats_disable - Disable device h/w statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA vpath statistics for the device. The function is to be called
+ * to disable the adapter to update stats into the host memory. This function
+ * is not needed to be called, normally.
+ *
+ * See also: vxge_hal_device_hw_stats_enable()
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_stats_disable(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->stats_cfg0);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		val64 &= ~VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - i)));
+
+	}
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->stats_cfg0);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_hw_stats_get - Get the device hw statistics.
+ * @devh: HAL Device.
+ * @hw_stats: Hardware stats
+ *
+ * Returns the vpath h/w stats for the device.
+ *
+ * See also: vxge_hal_device_hw_stats_enable(),
+ * vxge_hal_device_hw_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_device_hw_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_device_stats_hw_info_t *hw_stats)
+{
+	u32 i;
+	u64 val64 = 0;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (hw_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "devh = 0x"VXGE_OS_STXFMT", hw_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) hw_stats);
+
+	if (hldev->header.config.stats_read_method ==
+	    VXGE_HAL_STATS_READ_METHOD_DMA) {
+
+		for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+			if (!(hldev->vpaths_deployed & mBIT(i)))
+				continue;
+
+			val64 |=
+			    VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - i)));
+
+		}
+
+		status = vxge_hal_device_register_poll(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->stats_cfg0,
+		    0,
+		    val64,
+		    hldev->header.config.device_poll_millis);
+
+	}
+
+	if (status == VXGE_HAL_OK) {
+		vxge_os_memcpy(hw_stats,
+		    &hldev->stats.hw_dev_info_stats,
+		    sizeof(vxge_hal_device_stats_hw_info_t));
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_sw_stats_get - Get the device sw statistics.
+ * @devh: HAL Device.
+ * @sw_stats: Software stats
+ *
+ * Returns the vpath s/w stats for the device.
+ *
+ * See also: vxge_hal_device_hw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_device_sw_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_device_stats_sw_info_t *sw_stats)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (sw_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "devh = 0x"VXGE_OS_STXFMT", sw_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) sw_stats);
+
+	vxge_os_memcpy(sw_stats,
+	    &hldev->stats.sw_dev_info_stats,
+	    sizeof(vxge_hal_device_stats_sw_info_t));
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_stats_get - Get the device statistics.
+ * @devh: HAL Device.
+ * @stats: Device stats
+ *
+ * Returns the device stats for the device.
+ *
+ * See also: vxge_hal_device_hw_stats_get(), vxge_hal_device_sw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_device_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_device_stats_t *stats)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "devh = 0x"VXGE_OS_STXFMT", stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) stats);
+
+	vxge_os_memcpy(stats,
+	    &hldev->stats,
+	    sizeof(vxge_hal_device_stats_t));
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_device_xmac_stats_get - Get the Device XMAC Statistics
+ * @devh: HAL device handle.
+ * @xmac_stats: Buffer to return XMAC Statistics.
+ *
+ * Get the XMAC Statistics
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_xmac_stats_get(vxge_hal_device_h devh,
+    vxge_hal_device_xmac_stats_t *xmac_stats)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (xmac_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "devh = 0x"VXGE_OS_STXFMT", xmac_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) xmac_stats);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		status = __hal_vpath_xmac_tx_stats_get(&hldev->virtual_paths[i],
+		    &xmac_stats->vpath_tx_stats[i]);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		status = __hal_vpath_xmac_rx_stats_get(&hldev->virtual_paths[i],
+		    &xmac_stats->vpath_rx_stats[i]);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+
+/*
+ * vxge_hal_device_trace_write - Write the trace from the given buffer into
+ *				 circular trace buffer
+ * @devh: HAL device handle.
+ * @trace_buf: Buffer containing the trace.
+ * @trace_len: Length of the trace in the buffer
+ *
+ * Writes the trace from the given buffer into the circular trace buffer
+ *
+ */
+void
+vxge_hal_device_trace_write(vxge_hal_device_h devh,
+    u8 *trace_buf,
+    u32 trace_len)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	u32 offset;
+
+	if (hldev == NULL)
+		return;
+
+	offset = hldev->trace_buf.offset;
+
+	if (trace_len > 1) {
+
+		u32 leftsize = hldev->trace_buf.size - offset;
+
+		if (trace_len > leftsize) {
+			vxge_os_memzero(hldev->trace_buf.data + offset,
+			    leftsize);
+			offset = 0;
+			hldev->trace_buf.wrapped_count++;
+		}
+
+		vxge_os_memcpy(hldev->trace_buf.data + offset,
+		    trace_buf, trace_len);
+		offset += trace_len;
+		hldev->trace_buf.offset = offset;
+
+	}
+}
+
+/*
+ * vxge_hal_device_trace_dump - Dump the trace buffer.
+ * @devh: HAL device handle.
+ *
+ * Dump the trace buffer contents.
+ */
+void
+vxge_hal_device_trace_dump(vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	u32 offset, i = 0;
+
+	if (hldev == NULL)
+		return;
+
+	offset = hldev->trace_buf.offset;
+
+	vxge_os_printf("################ Trace dump Begin ###############\n");
+
+	if (hldev->trace_buf.wrapped_count) {
+		for (i = hldev->trace_buf.offset;
+		    i < hldev->trace_buf.size; i += offset) {
+			if (*(hldev->trace_buf.data + i))
+				vxge_os_printf(hldev->trace_buf.data + i);
+			offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
+		}
+	}
+
+	for (i = 0; i < hldev->trace_buf.offset; i += offset) {
+		if (*(hldev->trace_buf.data + i))
+			vxge_os_printf(hldev->trace_buf.data + i);
+		offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
+	}
+
+	vxge_os_printf("################ Trace dump End ###############\n");
+
+}
+
+/*
+ * vxge_hal_device_trace_read - Read trace buffer contents.
+ * @devh: HAL device handle.
+ * @buffer: Buffer to store the trace buffer contents.
+ * @buf_size: Size of the buffer.
+ * @read_length: Size of the valid data in the buffer.
+ *
+ * Read  HAL trace buffer contents starting from the offset
+ * upto the size of the buffer or till EOF is reached.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_device_trace_read(vxge_hal_device_h devh,
+    char *buffer,
+    unsigned buf_size,
+    unsigned *read_length)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	u32 offset, i = 0, buf_off = 0;
+
+	*read_length = 0;
+	*buffer = 0;
+
+	if (hldev == NULL)
+		return (VXGE_HAL_FAIL);
+
+	offset = hldev->trace_buf.offset;
+
+	if (hldev->trace_buf.wrapped_count) {
+		for (i = hldev->trace_buf.offset;
+		    i < hldev->trace_buf.size; i += offset) {
+			if (*(hldev->trace_buf.data + i)) {
+				vxge_os_sprintf(buffer + buf_off, "%s\n",
+				    hldev->trace_buf.data + i);
+				buf_off += vxge_os_strlen(
+				    hldev->trace_buf.data + i) + 1;
+				if (buf_off > buf_size)
+					return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+			}
+			offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
+		}
+	}
+
+	for (i = 0; i < hldev->trace_buf.offset; i += offset) {
+		if (*(hldev->trace_buf.data + i)) {
+			vxge_os_sprintf(buffer + buf_off, "%s\n",
+			    hldev->trace_buf.data + i);
+			buf_off += vxge_os_strlen(
+			    hldev->trace_buf.data + i) + 1;
+			if (buf_off > buf_size)
+				return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+		}
+		offset = vxge_os_strlen(hldev->trace_buf.data + i) + 1;
+	}
+
+	*read_length = buf_off;
+	*(buffer + buf_off + 1) = 0;
+
+	return (VXGE_HAL_OK);
+}
+
+#endif
+
+/*
+ * vxge_hal_device_debug_set - Set the debug module, level and timestamp
+ * @devh: Hal device object
+ * @level: Debug level as defined in enum vxge_debug_level_e
+ * @module masks: An or value of component masks as defined in vxge_debug.h
+ *
+ * This routine is used to dynamically change the debug output
+ */
+void
+vxge_hal_device_debug_set(
+    vxge_hal_device_h devh,
+    vxge_debug_level_e level,
+    u32 mask)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	hldev->header.debug_module_mask = mask;
+	hldev->header.debug_level = level;
+
+	hldev->d_trace_mask = 0;
+	hldev->d_info_mask = 0;
+	hldev->d_err_mask = 0;
+
+	switch (level) {
+	case VXGE_TRACE:
+		hldev->d_trace_mask = mask;
+		/* FALLTHROUGH */
+
+	case VXGE_INFO:
+		hldev->d_info_mask = mask;
+		/* FALLTHROUGH */
+
+	case VXGE_ERR:
+		hldev->d_err_mask = mask;
+		/* FALLTHROUGH */
+
+	default:
+		break;
+	}
+}
+
+/*
+ * vxge_hal_device_flick_link_led - Flick (blink) link LED.
+ * @devh: HAL device handle.
+ * @port : Port number 0, or 1
+ * @on_off: TRUE if flickering to be on, FALSE to be off
+ *
+ * Flicker the link LED.
+ */
+vxge_hal_status_e
+vxge_hal_device_flick_link_led(vxge_hal_device_h devh, u32 port, u32 on_off)
+{
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT
+	    ", port = %d, on_off = %d", (ptr_t) devh, port, on_off);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	status = __hal_vpath_flick_link_led(hldev,
+	    hldev->first_vp_id, port, on_off);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_device_getpause_data -Pause frame frame generation and reception.
+ * @devh: HAL device handle.
+ * @port : Port number 0, 1, or 2
+ * @tx : A field to return the pause generation capability of the NIC.
+ * @rx : A field to return the pause reception capability of the NIC.
+ *
+ * Returns the Pause frame generation and reception capability of the NIC.
+ * Return value:
+ * status
+ */
+vxge_hal_status_e
+vxge_hal_device_getpause_data(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 *tx,
+    u32 *rx)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_ERR_VPATH_NOT_AVAILABLE;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("devh = 0x"VXGE_OS_STXFMT", "
+	    "port = %d, tx = 0x"VXGE_OS_STXFMT", "
+	    "rx = 0x"VXGE_OS_STXFMT, (ptr_t) devh, port, (ptr_t) tx,
+	    (ptr_t) rx);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (port >= VXGE_HAL_MAC_MAX_PORTS) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT);
+		return (VXGE_HAL_ERR_INVALID_PORT);
+	}
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpath_assignments & mBIT(i)))
+			continue;
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->vpmgmt_reg[i]->
+		    rxmac_pause_cfg_port_vpmgmt_clone[port]);
+
+		if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN)
+			*tx = 1;
+
+		if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN)
+			*rx = 1;
+
+		status = VXGE_HAL_OK;
+
+		break;
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_device_is_privileged(u32 host_type, u32 func_id)
+{
+	u32 access_rights;
+	vxge_hal_status_e status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+
+	access_rights = __hal_device_access_rights_get(host_type, func_id);
+
+	if (access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)
+		status = VXGE_HAL_OK;
+
+	return (status);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-device.h b/sys/dev/vxge/vxgehal/vxgehal-device.h
new file mode 100644
index 000000000000..e44f8f28b27b
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-device.h
@@ -0,0 +1,265 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_DEVICE_H
+#define	VXGE_HAL_DEVICE_H
+
+__EXTERN_BEGIN_DECLS
+
+struct __hal_mrpcim_t;
+struct __hal_srpcim_t;
+
+/*
+ * vxge_hal_vpd_data_t
+ *
+ * Represents vpd capabilty structure
+ */
+typedef struct vxge_hal_vpd_data_t {
+	u8	product_name[VXGE_HAL_VPD_LEN];
+	u8	serial_num[VXGE_HAL_VPD_LEN];
+} vxge_hal_vpd_data_t;
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+/*
+ * __hal_tracebuf_t
+ *
+ * HAL trace buffer object.
+ */
+typedef struct __hal_tracebuf_t {
+	u8		*data;
+	u64		wrapped_count;
+	volatile u32	offset;
+	u32		size;
+} __hal_tracebuf_t;
+#endif
+
+/*
+ * __hal_msix_map_t
+ *
+ * HAL msix to vpath map.
+ */
+typedef struct __hal_msix_map_t {
+	u32	vp_id;
+	u32	int_num;
+} __hal_msix_map_t;
+
+/*
+ * __hal_device_t
+ *
+ * HAL device object. Represents X3100.
+ */
+typedef struct __hal_device_t {
+	vxge_hal_device_t			header;
+	u32					host_type;
+	u32					vh_id;
+	u32					func_id;
+	u32					srpcim_id;
+	u32					access_rights;
+#define	VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH	0x1
+#define	VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM	0x2
+#define	VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM	0x4
+	u32					ifmsg_seqno;
+	u32					manager_up;
+	vxge_hal_pci_config_t			pci_config_space;
+	vxge_hal_pci_config_t			pci_config_space_bios;
+	vxge_hal_pci_caps_offset_t		pci_caps;
+	vxge_hal_pci_e_caps_offset_t		pci_e_caps;
+	vxge_hal_pci_e_ext_caps_offset_t	pci_e_ext_caps;
+	vxge_hal_legacy_reg_t			*legacy_reg;
+	vxge_hal_toc_reg_t			*toc_reg;
+	vxge_hal_common_reg_t			*common_reg;
+	vxge_hal_memrepair_reg_t		*memrepair_reg;
+	vxge_hal_pcicfgmgmt_reg_t
+	    *pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES];
+	vxge_hal_mrpcim_reg_t			*mrpcim_reg;
+	vxge_hal_srpcim_reg_t
+	    *srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES];
+	vxge_hal_vpmgmt_reg_t
+	    *vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES];
+	vxge_hal_vpath_reg_t
+	    *vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES];
+	u8					*kdfc;
+	u8					*usdc;
+	__hal_virtualpath_t
+	    virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS];
+	u64					vpath_assignments;
+	u64					vpaths_deployed;
+	u32					first_vp_id;
+	u64					tim_int_mask0[4];
+	u32					tim_int_mask1[4];
+	__hal_msix_map_t
+	    msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX];
+	struct __hal_srpcim_t			*srpcim;
+	struct __hal_mrpcim_t			*mrpcim;
+	__hal_blockpool_t			block_pool;
+	vxge_list_t				pending_channel_list;
+	spinlock_t				pending_channel_lock;
+	vxge_hal_device_stats_t			stats;
+	volatile u32				msix_enabled;
+	volatile u32				hw_is_initialized;
+	volatile int				device_resetting;
+	volatile int				is_promisc;
+	int					tti_enabled;
+	spinlock_t				titan_post_lock;
+	u32					mtu_first_time_set;
+	char					*dump_buf;
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+	__hal_tracebuf_t			trace_buf;
+#endif
+	volatile u32				in_poll;
+	u32					d_err_mask;
+	u32					d_info_mask;
+	u32					d_trace_mask;
+} __hal_device_t;
+
+/*
+ * I2C device id. Used in I2C control register for accessing EEPROM device
+ * memory.
+ */
+#define	VXGE_DEV_ID				5
+
+#define	VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) {	\
+	((__hal_device_t *)hldev)->manager_up =			\
+		__hal_ifmsg_is_manager_up(wmsg);		\
+}
+
+#define	VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) {	\
+	((vxge_hal_device_t *)hldev)->link_state = ls;	\
+}
+
+#define	VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) {	\
+	((vxge_hal_device_t *)hldev)->data_rate = dr;	\
+}
+
+#define	VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) {			\
+	if (i < 16) {							\
+	    ((__hal_device_t *)hldev)->tim_int_mask0[0] |=		\
+						vBIT(0x8, (i*4), 4);	\
+	    ((__hal_device_t *)hldev)->tim_int_mask0[1] |=		\
+						vBIT(0x4, (i*4), 4);	\
+	    ((__hal_device_t *)hldev)->tim_int_mask0[3] |=		\
+						vBIT(0x1, (i*4), 4);	\
+	} else {							\
+	    ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000;	\
+	    ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000;	\
+	    ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000;	\
+	}								\
+}
+
+#define	VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) {			\
+	if (i < 16) {							\
+	    ((__hal_device_t *)hldev)->tim_int_mask0[0] &=		\
+						~vBIT(0x8, (i*4), 4);	\
+	    ((__hal_device_t *)hldev)->tim_int_mask0[1] &=		\
+						~vBIT(0x4, (i*4), 4);	\
+	    ((__hal_device_t *)hldev)->tim_int_mask0[3] &=		\
+						~vBIT(0x1, (i*4), 4);	\
+	} else {							\
+	    ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0;		\
+	    ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0;		\
+	    ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0;		\
+	}								\
+}
+
+/* ========================== PRIVATE API ================================= */
+
+void
+vxge_hal_pio_mem_write32_upper(pci_dev_h pdev,
+    pci_reg_h regh,
+    u32 val,
+    void *addr);
+
+void
+vxge_hal_pio_mem_write32_lower(pci_dev_h pdev,
+    pci_reg_h regh,
+    u32 val,
+    void *addr);
+
+void
+__hal_device_event_queued(void *data,
+    u32 event_type);
+
+void
+__hal_device_pci_caps_list_process(__hal_device_t *hldev);
+
+void
+__hal_device_pci_e_init(__hal_device_t *hldev);
+
+vxge_hal_status_e
+vxge_hal_device_register_poll(pci_dev_h pdev,
+    pci_reg_h regh,
+    u64 *reg,
+    u32 op,
+    u64 mask,
+    u32 max_millis);
+
+vxge_hal_status_e
+__hal_device_register_stall(pci_dev_h pdev,
+    pci_reg_h regh,
+    u64 *reg,
+    u32 op,
+    u64 mask,
+    u32 max_millis);
+
+vxge_hal_status_e
+__hal_device_reg_addr_get(__hal_device_t *hldev);
+
+void
+__hal_device_id_get(__hal_device_t *hldev);
+
+u32
+__hal_device_access_rights_get(u32 host_type, u32 func_id);
+
+void
+__hal_device_host_info_get(__hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_device_hw_initialize(__hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_device_reset(__hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_device_handle_link_up_ind(__hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_device_handle_link_down_ind(__hal_device_t *hldev);
+
+void
+__hal_device_handle_error(
+    __hal_device_t *hldev,
+    u32 vp_id,
+    vxge_hal_event_e type);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_DEVICE_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-doorbells.c b/sys/dev/vxge/vxgehal/vxgehal-doorbells.c
new file mode 100644
index 000000000000..ab53e028d35c
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-doorbells.c
@@ -0,0 +1,272 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+
+/*
+ * __hal_non_offload_db_post - Post non offload doorbell
+ *
+ * @vpath_handle: vpath handle
+ * @txdl_ptr: The starting location of the TxDL in host memory
+ * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
+ * @no_snoop: No snoop flags
+ *
+ * This function posts a non-offload doorbell to doorbell FIFO
+ *
+ */
+void
+__hal_non_offload_db_post(vxge_hal_vpath_h vpath_handle,
+    u64 txdl_ptr,
+    u32 num_txds,
+    u32 no_snoop)
+{
+	u64 *db_ptr;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (txdl_ptr != 0));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", txdl_ptr = 0x"VXGE_OS_STXFMT
+	    ", num_txds = %d, no_snoop = %d", (ptr_t) vpath_handle,
+	    (ptr_t) txdl_ptr, num_txds, no_snoop);
+
+	db_ptr = &vp->vpath->nofl_db->control_0;
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    VXGE_HAL_NODBW_TYPE(VXGE_HAL_NODBW_TYPE_NODBW) |
+	    VXGE_HAL_NODBW_LAST_TXD_NUMBER(num_txds) |
+	    VXGE_HAL_NODBW_GET_NO_SNOOP(no_snoop),
+	    db_ptr++);
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    txdl_ptr,
+	    db_ptr);
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_non_offload_db_reset - Reset non offload doorbell fifo
+ *
+ * @vpath_handle: vpath handle
+ *
+ * This function resets non-offload doorbell FIFO
+ *
+ */
+vxge_hal_status_e
+__hal_non_offload_db_reset(vxge_hal_vpath_h vpath_handle)
+{
+	vxge_hal_status_e status;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(
+	    1 << (16 - vp->vpath->vp_id)),
+	    &vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg2);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    &vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg2, 0,
+	    (u64) VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(
+	    1 << (16 - vp->vpath->vp_id)),
+	    VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (status);
+}
+
+/*
+ * __hal_rxd_db_post - Post rxd doorbell
+ *
+ * @vpath_handle: vpath handle
+ * @num_bytes: The number of bytes
+ *
+ * This function posts a rxd doorbell
+ *
+ */
+void
+__hal_rxd_db_post(vxge_hal_vpath_h vpath_handle,
+    u32 num_bytes)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", num_bytes = %d",
+	    (ptr_t) vpath_handle, num_bytes);
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    VXGE_HAL_PRC_RXD_DOORBELL_NEW_QW_CNT((num_bytes >> 3)),
+	    &vp->vpath->vp_reg->prc_rxd_doorbell);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+
+/*
+ * __hal_message_db_post - Post message doorbell
+ *
+ * @vpath_handle: VPATH handle
+ * @num_msg_bytes: The number of new message bytes made available
+ *		by this doorbell entry.
+ * @immed_msg: Immediate message to be sent
+ * @immed_msg_len: Immediate message length
+ *
+ * This function posts a message doorbell to doorbell FIFO
+ *
+ */
+void
+__hal_message_db_post(vxge_hal_vpath_h vpath_handle,
+    u32 num_msg_bytes,
+    u8 *immed_msg,
+    u32 immed_msg_len)
+{
+	u32 i;
+	u64 *db_ptr;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (num_msg_bytes != 0));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_dmq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_dmq("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "num_msg_bytes = %d, immed_msg = 0x"VXGE_OS_STXFMT", "
+	    "immed_msg_len = %d", (ptr_t) vpath_handle, num_msg_bytes,
+	    (ptr_t) immed_msg, immed_msg_len);
+
+	db_ptr = &vp->vpath->msg_db->control_0;
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    VXGE_HAL_MDBW_TYPE(VXGE_HAL_MDBW_TYPE_MDBW) |
+	    VXGE_HAL_MDBW_MESSAGE_BYTE_COUNT(num_msg_bytes),
+	    db_ptr++);
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    VXGE_HAL_MDBW_IMMEDIATE_BYTE_COUNT(immed_msg_len),
+	    db_ptr++);
+
+	for (i = 0; i < immed_msg_len / 8; i++) {
+		vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+		    vp->vpath->hldev->header.regh0,
+		    *((u64 *) ((void *)&immed_msg[i * 8])),
+		    db_ptr++);
+	}
+
+	vxge_hal_trace_log_dmq("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_message_db_reset - Reset message doorbell fifo
+ *
+ * @vpath_handle: vpath handle
+ *
+ * This function resets message doorbell FIFO
+ *
+ */
+vxge_hal_status_e
+__hal_message_db_reset(vxge_hal_vpath_h vpath_handle)
+{
+	vxge_hal_status_e status;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_dmq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_dmq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	vxge_os_pio_mem_write64(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(
+	    1 << (16 - vp->vpath->vp_id)),
+	    &vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg3);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    &vp->vpath->hldev->common_reg->cmn_rsthdlr_cfg3, 0,
+	    (u64) VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(
+	    1 << (16 - vp->vpath->vp_id)),
+	    VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	vxge_hal_trace_log_dmq("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (status);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-doorbells.h b/sys/dev/vxge/vxgehal/vxgehal-doorbells.h
new file mode 100644
index 000000000000..fa0006d8f6ec
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-doorbells.h
@@ -0,0 +1,218 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_DOOR_BELLS_H
+#define	VXGE_HAL_DOOR_BELLS_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * struct __hal_non_offload_db_wrapper_t - Non-offload Doorbell Wrapper
+ * @control_0:	Bits 0 to 7 - Doorbell type.
+ *		Bits 8 to 31 - Reserved.
+ *		Bits 32 to 39 - The highest TxD in this TxDL.
+ *		Bits 40 to 47 - Reserved.
+ *		Bits 48 to 55 - Reserved.
+ *		Bits 56 to 63 - No snoop flags.
+ * @txdl_ptr:	The starting location of the TxDL in host memory.
+ *
+ * Created by the host and written to the adapter via PIO to a Kernel Doorbell
+ * FIFO. All non-offload doorbell wrapper fields must be written by the host as
+ * part of a doorbell write. Consumed by the adapter but is not written by the
+ * adapter.
+ */
+typedef __vxge_os_attr_cacheline_aligned struct __hal_non_offload_db_wrapper_t {
+	u64		control_0;
+#define	VXGE_HAL_NODBW_GET_TYPE(ctrl0)				bVAL8(ctrl0, 0)
+#define	VXGE_HAL_NODBW_TYPE(val)				vBIT(val, 0, 8)
+#define	VXGE_HAL_NODBW_TYPE_NODBW				0
+
+#define	VXGE_HAL_NODBW_GET_LAST_TXD_NUMBER(ctrl0)		bVAL8(ctrl0, 32)
+#define	VXGE_HAL_NODBW_LAST_TXD_NUMBER(val)			vBIT(val, 32, 8)
+
+#define	VXGE_HAL_NODBW_GET_NO_SNOOP(ctrl0)			bVAL8(ctrl0, 56)
+#define	VXGE_HAL_NODBW_LIST_NO_SNOOP(val)			vBIT(val, 56, 8)
+#define	VXGE_HAL_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE	0x2
+#define	VXGE_HAL_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ		0x1
+
+	u64		txdl_ptr;
+} __hal_non_offload_db_wrapper_t;
+
+/*
+ * struct __hal_offload_db_wrapper_t - Tx-Offload Doorbell Wrapper
+ * @control_0:	Bits 0 to 7 - Doorbell type.
+ *		Bits 8 to 31 - Identifies the session to which this Tx
+ *		offload doorbell applies.
+ *		Bits 32 to 40 - Identifies the incarnation of this Session
+ *		Number. The adapter assigns a Session Instance
+ *		Number of 0 to a session when that Session Number
+ *		is first used. Each subsequent assignment of that
+ *		Session Number from the free pool causes this
+ *		number to be incremented, with wrap eventually
+ *		occurring from 255 back to 0.
+ *		Bits 40 to 63 - Identifies the end of the TOWI list for
+ *		this session to the adapter.
+ * @control_1:	Bits 0 to 7 - Identifies what is included in this doorbell
+ *		Bits 8 to 15 - The number of Immediate data bytes included in
+ *		this doorbell.
+ *		Bits 16 to 63 - Reserved.
+ *
+ * Created by the host and written to the adapter via PIO to a Kernel Doorbell
+ * FIFO. All Tx Offload doorbell wrapper fields must be written by the host as
+ * part of a doorbell write. Consumed by the adapter but is never written by the
+ * adapter.
+ */
+typedef __vxge_os_attr_cacheline_aligned struct __hal_offload_db_wrapper_t {
+	u64		control_0;
+#define	VXGE_HAL_ODBW_GET_TYPE(ctrl0)			bVAL8(ctrl0, 0)
+#define	VXGE_HAL_ODBW_TYPE(val)				vBIT(val, 0, 8)
+#define	VXGE_HAL_ODBW_TYPE_ODBW				1
+
+#define	VXGE_HAL_ODBW_GET_SESSION_NUMBER(ctrl0)		bVAL24(ctrl0, 8)
+#define	VXGE_HAL_ODBW_SESSION_NUMBER(val)		vBIT(val, 8, 24)
+
+#define	VXGE_HAL_ODBW_GET_SESSION_INST_NUMBER(ctrl0)	bVAL8(ctrl0, 32)
+#define	VXGE_HAL_ODBW_SESSION_INST_NUMBER(val)		vBIT(val, 32, 8)
+
+#define	VXGE_HAL_ODBW_GET_HIGH_TOWI_NUMBER(ctrl0)	bVAL24(ctrl0, 40)
+#define	VXGE_HAL_ODBW_HIGH_TOWI_NUMBER(val)		vBIT(val, 40, 24)
+
+	u64		control_1;
+#define	VXGE_HAL_ODBW_GET_ENTRY_TYPE(ctrl1)		bVAL8(ctrl1, 0)
+#define	VXGE_HAL_ODBW_ENTRY_TYPE(val)			vBIT(val, 0, 8)
+#define	VXGE_HAL_ODBW_ENTRY_TYPE_WRAPPER_ONLY		0x0
+#define	VXGE_HAL_ODBW_ENTRY_TYPE_WRAPPER_TOWI		0x1
+#define	VXGE_HAL_ODBW_ENTRY_TYPE_WRAPPER_TOWI_DATA	0x2
+
+#define	VXGE_HAL_ODBW_GET_IMMEDIATE_BYTE_COUNT(ctrl1)	bVAL8(ctrl1, 8)
+#define	VXGE_HAL_ODBW_IMMEDIATE_BYTE_COUNT(val)		vBIT(val, 8, 8)
+
+} __hal_offload_db_wrapper_t;
+
+/*
+ * struct __hal_offload_atomic_db_wrapper_t - Atomic Tx-Offload Doorbell
+ *						 Wrapper
+ * @control_0:	Bits 0 to 7 - Doorbell type.
+ *		Bits 8 to 31 - Identifies the session to which this Tx
+ *		offload doorbell applies.
+ *		Bits 32 to 40 - Identifies the incarnation of this Session
+ *		Number. The adapter assigns a Session Instance
+ *		Number of 0 to a session when that Session Number
+ *		is first used. Each subsequent assignment of that
+ *		Session Number from the free pool causes this
+ *		number to be incremented, with wrap eventually
+ *		occurring from 255 back to 0.
+ *		Bits 40 to 63 - Identifies the end of the TOWI list for
+ *		this session to the adapter.
+ *
+ * Created by the host and written to the adapter via PIO to a Kernel Doorbell
+ * FIFO.  All Tx Offload doorbell wrapper fields must be written by the host as
+ * part of a doorbell write. Consumed by the adapter but is never written by the
+ * adapter.
+ */
+typedef	__vxge_os_attr_cacheline_aligned
+struct __hal_offload_atomic_db_wrapper_t {
+	u64		control_0;
+#define	VXGE_HAL_ODBW_GET_TYPE(ctrl0)			bVAL8(ctrl0, 0)
+#define	VXGE_HAL_ODBW_TYPE(val)				vBIT(val, 0, 8)
+#define	VXGE_HAL_ODBW_TYPE_ATOMIC			2
+
+#define	VXGE_HAL_ODBW_GET_SESSION_NUMBER(ctrl0)		bVAL24(ctrl0, 8)
+#define	VXGE_HAL_ODBW_SESSION_NUMBER(val)		vBIT(val, 8, 24)
+
+#define	VXGE_HAL_ODBW_GET_SESSION_INST_NUMBER(ctrl0)	bVAL8(ctrl0, 32)
+#define	VXGE_HAL_ODBW_SESSION_INST_NUMBER(val)		vBIT(val, 32, 8)
+
+#define	VXGE_HAL_ODBW_GET_HIGH_TOWI_NUMBER(ctrl0)	bVAL24(ctrl0, 40)
+#define	VXGE_HAL_ODBW_HIGH_TOWI_NUMBER(val)		vBIT(val, 40, 24)
+
+} __hal_offload_atomic_db_wrapper_t;
+
+
+
+/*
+ * struct __hal_messaging_db_wrapper_t - Messaging Doorbell Wrapper
+ * @control_0:	Bits 0 to 7 - Doorbell type.
+ *		Bits 8 to 31 - Reserved.
+ *		Bits 32 to 63 - The number of new message bytes made available
+ *		by this doorbell entry.
+ * @control_1:	Bits 0 to 7 - Reserved.
+ *		Bits 8 to 15 - The number of Immediate messaging bytes included
+ *		in this doorbell.
+ *		Bits 16 to 63 - Reserved.
+ *
+ * Created by the host and written to the adapter via PIO to a Kernel Doorbell
+ * FIFO. All message doorbell wrapper fields must be written by the host as
+ * part of a doorbell write. Consumed by the adapter but not written by adapter.
+ */
+typedef __vxge_os_attr_cacheline_aligned struct __hal_messaging_db_wrapper_t {
+	u64		control_0;
+#define	VXGE_HAL_MDBW_GET_TYPE(ctrl0)			bVAL8(ctrl0, 0)
+#define	VXGE_HAL_MDBW_TYPE(val)				vBIT(val, 0, 8)
+#define	VXGE_HAL_MDBW_TYPE_MDBW				3
+
+#define	VXGE_HAL_MDBW_GET_MESSAGE_BYTE_COUNT(ctrl0)	bVAL32(ctrl0, 32)
+#define	VXGE_HAL_MDBW_MESSAGE_BYTE_COUNT(val)		vBIT(val, 32, 32)
+
+	u64		control_1;
+#define	VXGE_HAL_MDBW_GET_IMMEDIATE_BYTE_COUNT(ctrl1)	bVAL8(ctrl1, 8)
+#define	VXGE_HAL_MDBW_IMMEDIATE_BYTE_COUNT(val)		vBIT(val, 8, 8)
+
+} __hal_messaging_db_wrapper_t;
+
+
+void
+__hal_non_offload_db_post(vxge_hal_vpath_h vpath_handle,
+    u64 txdl_ptr,
+    u32 num_txds,
+    u32 no_snoop);
+
+void
+__hal_rxd_db_post(vxge_hal_vpath_h vpath_handle,
+    u32 num_bytes);
+
+vxge_hal_status_e
+__hal_non_offload_db_reset(vxge_hal_vpath_h vpath_handle);
+
+
+void
+__hal_message_db_post(vxge_hal_vpath_h vpath_handle,
+    u32 num_msg_bytes,
+    u8 *immed_msg,
+    u32 immed_msg_len);
+
+vxge_hal_status_e
+__hal_message_db_reset(vxge_hal_vpath_h vpath_handle);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_DOOR_BELLS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-driver.c b/sys/dev/vxge/vxgehal/vxgehal-driver.c
new file mode 100644
index 000000000000..ce3ae75687c1
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-driver.c
@@ -0,0 +1,173 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+static __hal_driver_t g_driver;
+__hal_driver_t *g_vxge_hal_driver;
+
+#if defined(VXGE_OS_MEMORY_CHECK)
+vxge_os_malloc_t g_malloc_arr[VXGE_OS_MALLOC_CNT_MAX];
+u32 g_malloc_cnt;
+
+#endif
+
+/*
+ * Runtime tracing support
+ */
+u32 g_debug_level;
+
+/*
+ * vxge_hal_driver_initialize - Initialize HAL.
+ * @config: HAL configuration, see vxge_hal_driver_config_t {}.
+ * @uld_callbacks: Upper-layer driver callbacks, e.g. link-up.
+ *
+ * HAL initialization entry point. Not to confuse with device initialization
+ * (note that HAL "contains" zero or more X3100 devices).
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_BAD_DRIVER_CONFIG - Driver configuration params invalid.
+ *
+ * See also: vxge_hal_device_initialize(), vxge_hal_status_e {},
+ * vxge_hal_uld_cbs_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_driver_initialize(
+    vxge_hal_driver_config_t *config,
+    vxge_hal_uld_cbs_t *uld_callbacks)
+{
+	vxge_hal_status_e status;
+	g_vxge_hal_driver = &g_driver;
+
+	if ((status = vxge_hal_driver_config_check(config)) != VXGE_HAL_OK)
+		return (status);
+
+	vxge_os_memzero(g_vxge_hal_driver, sizeof(__hal_driver_t));
+
+	/* apply config */
+	vxge_os_memcpy(&g_vxge_hal_driver->config, config,
+	    sizeof(vxge_hal_driver_config_t));
+
+	/* apply ULD callbacks */
+	vxge_os_memcpy(&g_vxge_hal_driver->uld_callbacks, uld_callbacks,
+	    sizeof(vxge_hal_uld_cbs_t));
+
+	vxge_hal_driver_debug_set(config->level);
+
+	g_vxge_hal_driver->is_initialized = 1;
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_driver_terminate - Terminate HAL.
+ *
+ * HAL termination entry point.
+ *
+ * See also: vxge_hal_device_terminate().
+ */
+void
+vxge_hal_driver_terminate(void)
+{
+	g_vxge_hal_driver->is_initialized = 0;
+
+	g_vxge_hal_driver = NULL;
+
+#if defined(VXGE_OS_MEMORY_CHECK)
+	if (TRUE) {
+		u32 i, leaks = 0;
+
+		vxge_os_printf("OSPAL: max g_malloc_cnt %d\n", g_malloc_cnt);
+		for (i = 0; i < g_malloc_cnt; i++) {
+			if (g_malloc_arr[i].ptr != NULL) {
+				vxge_os_printf("OSPAL: memory leak detected at "
+				    "%s:%lu:"VXGE_OS_LLXFMT":%lu\n",
+				    g_malloc_arr[i].file,
+				    g_malloc_arr[i].line,
+				    (u64) (ptr_t) g_malloc_arr[i].ptr,
+				    g_malloc_arr[i].size);
+				leaks++;
+			}
+		}
+		if (leaks) {
+			vxge_os_printf("OSPAL: %d memory leaks detected\n",
+			    leaks);
+		} else {
+			vxge_os_println("OSPAL: no memory leaks detected\n");
+		}
+	}
+#endif
+}
+
+/*
+ * vxge_hal_driver_debug_set - Set the debug module, level and timestamp
+ * @level: Debug level as defined in enum vxge_debug_level_e
+ *
+ * This routine is used to dynamically change the debug output
+ */
+void
+vxge_hal_driver_debug_set(
+    vxge_debug_level_e level)
+{
+	g_vxge_hal_driver->debug_level = level;
+	g_debug_level = 0;
+
+	switch (level) {
+		/* FALLTHRU */
+
+	case VXGE_TRACE:
+		g_debug_level |= VXGE_TRACE;
+		/* FALLTHRU */
+
+	case VXGE_INFO:
+		g_debug_level |= VXGE_INFO;
+		/* FALLTHRU */
+
+	case VXGE_ERR:
+		g_debug_level |= VXGE_ERR;
+		/* FALLTHRU */
+
+	default:
+		break;
+	}
+}
+
+/*
+ * vxge_hal_driver_debug_get - Get the debug level
+ *
+ * This routine returns the current debug level set
+ */
+u32
+vxge_hal_driver_debug_get(void)
+{
+	return (g_vxge_hal_driver->debug_level);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-driver.h b/sys/dev/vxge/vxgehal/vxgehal-driver.h
new file mode 100644
index 000000000000..6aa6def9d374
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-driver.h
@@ -0,0 +1,68 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_DRIVER_H
+#define	VXGE_HAL_DRIVER_H
+
+__EXTERN_BEGIN_DECLS
+
+/* maximum number of events consumed in a syncle poll() cycle */
+#define	VXGE_HAL_DRIVER_QUEUE_CONSUME_MAX	5
+
+/*
+ * struct __hal_driver_t - Represents HAL object for driver.
+ * @config: HAL configuration.
+ * @devices: List of all PCI-enumerated X3100 devices in the system.
+ * A single vxge_hal_driver_t instance contains zero or more
+ * X3100 devices.
+ * @devices_lock: Lock to protect %devices when inserting/removing.
+ * @is_initialized: True if HAL is initialized; false otherwise.
+ * @uld_callbacks: Upper-layer driver callbacks. See vxge_hal_uld_cbs_t {}.
+ * @debug_module_mask: 32bit mask that defines which components of the
+ * driver are to be traced. The trace-able components are listed in
+ * xgehal_debug.h:
+ * @debug_level: See vxge_debug_level_e {}.
+ *
+ * HAL (driver) object. There is a single instance of this structure per HAL.
+ */
+typedef struct __hal_driver_t {
+	vxge_hal_driver_config_t	config;
+	int				is_initialized;
+	vxge_hal_uld_cbs_t		uld_callbacks;
+	u32				debug_level;
+} __hal_driver_t;
+
+extern __hal_driver_t *g_vxge_hal_driver;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_DRIVER_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-fifo.c b/sys/dev/vxge/vxgehal/vxgehal-fifo.c
new file mode 100644
index 000000000000..e5f6c7815fff
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-fifo.c
@@ -0,0 +1,1896 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * __hal_fifo_mempool_item_alloc - Allocate List blocks for TxD list callback
+ * @mempoolh: Handle to memory pool
+ * @memblock: Address of this memory block
+ * @memblock_index: Index of this memory block
+ * @dma_object: dma object for this block
+ * @item: Pointer to this item
+ * @index: Index of this item in memory block
+ * @is_last: If this is last item in the block
+ * @userdata: Specific data of user
+ *
+ * This function is callback passed to __hal_mempool_create to create memory
+ * pool for TxD list
+ */
+static vxge_hal_status_e
+__hal_fifo_mempool_item_alloc(
+    vxge_hal_mempool_h mempoolh,
+    void *memblock,
+    u32 memblock_index,
+    vxge_hal_mempool_dma_t *dma_object,
+    void *item,
+    u32 item_index,
+    u32 is_last,
+    void *userdata)
+{
+	u32 i;
+	void *block_priv;
+	u32 memblock_item_idx;
+
+	__hal_fifo_t *fifo = (__hal_fifo_t *) userdata;
+
+	vxge_assert(fifo != NULL);
+	vxge_assert(item);
+
+#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
+	{
+		__hal_device_t *hldev = (__hal_device_t *) fifo->channel.devh;
+
+		vxge_hal_trace_log_pool("==> %s:%s:%d",
+		    __FILE__, __func__, __LINE__);
+
+		vxge_hal_trace_log_pool(
+		    "mempoolh = 0x"VXGE_OS_STXFMT", "
+		    "memblock = 0x"VXGE_OS_STXFMT", memblock_index = %d, "
+		    "dma_object = 0x"VXGE_OS_STXFMT", \
+		    item = 0x"VXGE_OS_STXFMT", "
+		    "item_index = %d, is_last = %d, userdata = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) mempoolh, (ptr_t) memblock, memblock_index,
+		    (ptr_t) dma_object, (ptr_t) item, item_index, is_last,
+		    (ptr_t) userdata);
+	}
+#endif
+
+	block_priv = __hal_mempool_item_priv((vxge_hal_mempool_t *) mempoolh,
+	    memblock_index, item, &memblock_item_idx);
+
+	vxge_assert(block_priv != NULL);
+
+	for (i = 0; i < fifo->txdl_per_memblock; i++) {
+
+		__hal_fifo_txdl_priv_t *txdl_priv;
+		vxge_hal_fifo_txd_t *txdp;
+
+		int dtr_index = item_index * fifo->txdl_per_memblock + i;
+
+		txdp = (vxge_hal_fifo_txd_t *) ((void *)
+		    ((char *) item + i * fifo->txdl_size));
+
+		txdp->host_control = dtr_index;
+
+		fifo->channel.dtr_arr[dtr_index].dtr = txdp;
+
+		fifo->channel.dtr_arr[dtr_index].uld_priv = (void *)
+		    ((char *) block_priv + fifo->txdl_priv_size * i);
+
+		fifo->channel.dtr_arr[dtr_index].hal_priv = (void *)
+		    (((char *) fifo->channel.dtr_arr[dtr_index].uld_priv) +
+		    fifo->per_txdl_space);
+
+		txdl_priv = (__hal_fifo_txdl_priv_t *)
+		    fifo->channel.dtr_arr[dtr_index].hal_priv;
+
+		vxge_assert(txdl_priv);
+
+		/* pre-format HAL's TxDL's private */
+		/* LINTED */
+		txdl_priv->dma_offset = (char *) txdp - (char *) memblock;
+		txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
+		txdl_priv->dma_handle = dma_object->handle;
+		txdl_priv->memblock = memblock;
+		txdl_priv->first_txdp = (vxge_hal_fifo_txd_t *) txdp;
+		txdl_priv->next_txdl_priv = NULL;
+		txdl_priv->dang_txdl = NULL;
+		txdl_priv->dang_frags = 0;
+		txdl_priv->alloc_frags = 0;
+
+#if defined(VXGE_DEBUG_ASSERT)
+		txdl_priv->dma_object = dma_object;
+#endif
+
+#if defined(VXGE_HAL_ALIGN_XMIT)
+		txdl_priv->align_vaddr = NULL;
+		txdl_priv->align_dma_addr = (dma_addr_t) 0;
+
+#ifndef	VXGE_HAL_ALIGN_XMIT_ALLOC_RT
+		/* CONSTCOND */
+		if (TRUE) {
+			vxge_hal_status_e status;
+
+			if (fifo->config->alignment_size) {
+				status = __hal_fifo_txdl_align_alloc_map(fifo,
+				    txdp);
+				if (status != VXGE_HAL_OK) {
+
+#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
+					__hal_device_t *hldev;
+					hldev = (__hal_device_t *)
+					    fifo->channel.devh;
+
+					vxge_hal_err_log_pool(
+					    "align buffer[%d] %d bytes, \
+					    status %d",
+					    (item_index * fifo->txdl_per_memblock + i),
+					    fifo->align_size, status);
+
+					vxge_hal_trace_log_pool(
+					    "<== %s:%s:%d  Result: 0",
+					    __FILE__, __func__, __LINE__);
+#endif
+					return (status);
+				}
+			}
+		}
+#endif
+#endif
+		if (fifo->txdl_init) {
+			fifo->txdl_init(fifo->channel.vph,
+			    (vxge_hal_txdl_h) txdp,
+			    VXGE_HAL_FIFO_ULD_PRIV(fifo, txdp),
+			    VXGE_HAL_FIFO_TXDL_INDEX(txdp),
+			    fifo->channel.userdata, VXGE_HAL_OPEN_NORMAL);
+		}
+	}
+
+#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
+	{
+		__hal_device_t *hldev = (__hal_device_t *) fifo->channel.devh;
+
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+		    __FILE__, __func__, __LINE__);
+	}
+#endif
+
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * __hal_fifo_mempool_item_free - Free List blocks for TxD list callback
+ * @mempoolh: Handle to memory pool
+ * @memblock: Address of this memory block
+ * @memblock_index: Index of this memory block
+ * @dma_object: dma object for this block
+ * @item: Pointer to this item
+ * @index: Index of this item in memory block
+ * @is_last: If this is last item in the block
+ * @userdata: Specific data of user
+ *
+ * This function is callback passed to __hal_mempool_free to destroy memory
+ * pool for TxD list
+ */
+static vxge_hal_status_e
+__hal_fifo_mempool_item_free(
+    vxge_hal_mempool_h mempoolh,
+    void *memblock,
+    u32 memblock_index,
+    vxge_hal_mempool_dma_t *dma_object,
+    void *item,
+    u32 item_index,
+    u32 is_last,
+    void *userdata)
+{
+	vxge_assert(item);
+
+#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
+	{
+		__hal_fifo_t *fifo = (__hal_fifo_t *) userdata;
+
+		vxge_assert(fifo != NULL);
+
+		__hal_device_t *hldev = (__hal_device_t *) fifo->channel.devh;
+
+		vxge_hal_trace_log_pool("==> %s:%s:%d",
+		    __FILE__, __func__, __LINE__);
+
+		vxge_hal_trace_log_pool("mempoolh = 0x"VXGE_OS_STXFMT", "
+		    "memblock = 0x"VXGE_OS_STXFMT", memblock_index = %d, "
+		    "dma_object = 0x"VXGE_OS_STXFMT", \
+		    item = 0x"VXGE_OS_STXFMT", "
+		    "item_index = %d, is_last = %d, userdata = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) mempoolh, (ptr_t) memblock, memblock_index,
+		    (ptr_t) dma_object, (ptr_t) item, item_index, is_last,
+		    (ptr_t) userdata);
+	}
+#endif
+
+#if defined(VXGE_HAL_ALIGN_XMIT)
+	{
+		__hal_fifo_t *fifo = (__hal_fifo_t *) userdata;
+
+		vxge_assert(fifo != NULL);
+		if (fifo->config->alignment_size) {
+
+			int i;
+			vxge_hal_fifo_txd_t *txdp;
+
+			for (i = 0; i < fifo->txdl_per_memblock; i++) {
+				txdp = (void *)
+				    ((char *) item + i * fifo->txdl_size);
+				__hal_fifo_txdl_align_free_unmap(fifo, txdp);
+			}
+		}
+	}
+#endif
+
+#if (VXGE_COMPONENT_HAL_POOL & VXGE_DEBUG_MODULE_MASK)
+	{
+		__hal_fifo_t *fifo = (__hal_fifo_t *) userdata;
+
+		vxge_assert(fifo != NULL);
+
+		__hal_device_t *hldev = (__hal_device_t *) fifo->channel.devh;
+
+		vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+		    __FILE__, __func__, __LINE__);
+	}
+#endif
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_fifo_create - Create a FIFO
+ * @vpath_handle: Handle returned by virtual path open
+ * @attr: FIFO configuration parameters structure
+ *
+ * This function creates FIFO and initializes it.
+ *
+ */
+vxge_hal_status_e
+__hal_fifo_create(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_fifo_attr_t *attr)
+{
+	vxge_hal_status_e status;
+	__hal_fifo_t *fifo;
+	vxge_hal_fifo_config_t *config;
+	u32 txdl_size, memblock_size, txdl_per_memblock;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+
+	vxge_assert((vpath_handle != NULL) && (attr != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", attr = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) attr);
+
+	if ((vpath_handle == NULL) || (attr == NULL)) {
+		vxge_hal_err_log_fifo("null pointer passed == > %s : %d",
+		    __func__, __LINE__);
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	config =
+	    &vp->vpath->hldev->header.config.vp_config[vp->vpath->vp_id].fifo;
+
+	txdl_size = config->max_frags * sizeof(vxge_hal_fifo_txd_t);
+
+	if (txdl_size <= VXGE_OS_HOST_PAGE_SIZE)
+		memblock_size = VXGE_OS_HOST_PAGE_SIZE;
+	else
+		memblock_size = txdl_size;
+
+	txdl_per_memblock = memblock_size / txdl_size;
+
+	config->fifo_length = ((config->fifo_length + txdl_per_memblock - 1) /
+	    txdl_per_memblock) * txdl_per_memblock;
+
+	fifo = (__hal_fifo_t *) vxge_hal_channel_allocate(
+	    (vxge_hal_device_h) vp->vpath->hldev,
+	    vpath_handle,
+	    VXGE_HAL_CHANNEL_TYPE_FIFO,
+	    config->fifo_length,
+	    attr->per_txdl_space,
+	    attr->userdata);
+
+	if (fifo == NULL) {
+		vxge_hal_err_log_fifo("Memory allocation failed == > %s : %d",
+		    __func__, __LINE__);
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	vp->vpath->fifoh = fifo;
+
+	fifo->stats = &vp->vpath->sw_stats->fifo_stats;
+
+	fifo->config = config;
+
+	fifo->memblock_size = memblock_size;
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock_init(&fifo->channel.post_lock,
+	    vp->vpath->hldev->header.pdev);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_init_irq(&fifo->channel.post_lock,
+	    vp->vpath->hldev->header.irqh);
+#endif
+
+	fifo->align_size =
+	    fifo->config->alignment_size * fifo->config->max_aligned_frags;
+
+	/* apply "interrupts per txdl" attribute */
+	fifo->interrupt_type = VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ;
+	if (fifo->config->intr) {
+		fifo->interrupt_type = VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST;
+	}
+
+	fifo->no_snoop_bits = config->no_snoop_bits;
+
+	/*
+	 * FIFO memory management strategy:
+	 *
+	 * TxDL splitted into three independent parts:
+	 *	- set of TxD's
+	 *	- TxD HAL private part
+	 *	- upper layer private part
+	 *
+	 * Adaptative memory allocation used. i.e. Memory allocated on
+	 * demand with the size which will fit into one memory block.
+	 * One memory block may contain more than one TxDL. In simple case
+	 * memory block size can be equal to CPU page size. On more
+	 * sophisticated OS's memory block can be contigious across
+	 * several pages.
+	 *
+	 * During "reserve" operations more memory can be allocated on demand
+	 * for example due to FIFO full condition.
+	 *
+	 * Pool of memory memblocks never shrinks except __hal_fifo_close
+	 * routine which will essentially stop channel and free the resources.
+	 */
+
+	/* TxDL common private size == TxDL private + ULD private */
+	fifo->txdl_priv_size =
+	    sizeof(__hal_fifo_txdl_priv_t) + attr->per_txdl_space;
+	fifo->txdl_priv_size =
+	    ((fifo->txdl_priv_size + __vxge_os_cacheline_size - 1) /
+	    __vxge_os_cacheline_size) * __vxge_os_cacheline_size;
+
+	fifo->per_txdl_space = attr->per_txdl_space;
+
+	/* recompute txdl size to be cacheline aligned */
+	fifo->txdl_size = txdl_size;
+	fifo->txdl_per_memblock = txdl_per_memblock;
+
+	/*
+	 * since txdl_init() callback will be called from item_alloc(),
+	 * the same way channels userdata might be used prior to
+	 * channel_initialize()
+	 */
+	fifo->txdl_init = attr->txdl_init;
+	fifo->txdl_term = attr->txdl_term;
+	fifo->callback = attr->callback;
+
+	if (fifo->txdl_per_memblock == 0) {
+		__hal_fifo_delete(vpath_handle);
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_BLOCK_SIZE);
+		return (VXGE_HAL_ERR_INVALID_BLOCK_SIZE);
+	}
+
+	/* calculate actual TxDL block private size */
+	fifo->txdlblock_priv_size =
+	    fifo->txdl_priv_size * fifo->txdl_per_memblock;
+
+	fifo->mempool =
+	    vxge_hal_mempool_create((vxge_hal_device_h) vp->vpath->hldev,
+	    fifo->memblock_size,
+	    fifo->memblock_size,
+	    fifo->txdlblock_priv_size,
+	    fifo->config->fifo_length /
+	    fifo->txdl_per_memblock,
+	    fifo->config->fifo_length /
+	    fifo->txdl_per_memblock,
+	    __hal_fifo_mempool_item_alloc,
+	    __hal_fifo_mempool_item_free,
+	    fifo);
+
+	if (fifo->mempool == NULL) {
+		__hal_fifo_delete(vpath_handle);
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	status = vxge_hal_channel_initialize(&fifo->channel);
+	if (status != VXGE_HAL_OK) {
+		__hal_fifo_delete(vpath_handle);
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_fifo_abort - Returns the TxD
+ * @fifoh: Fifo to be reset
+ * @reopen: See  vxge_hal_reopen_e {}.
+ *
+ * This function terminates the TxDs of fifo
+ */
+void
+__hal_fifo_abort(
+    vxge_hal_fifo_h fifoh,
+    vxge_hal_reopen_e reopen)
+{
+	u32 i = 0;
+	__hal_fifo_t *fifo = (__hal_fifo_t *) fifoh;
+	__hal_device_t *hldev;
+	vxge_hal_txdl_h txdlh;
+
+	vxge_assert(fifoh != NULL);
+
+	hldev = (__hal_device_t *) fifo->channel.devh;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("fifo = 0x"VXGE_OS_STXFMT", reopen = %d",
+	    (ptr_t) fifoh, reopen);
+
+	if (fifo->txdl_term) {
+		__hal_channel_for_each_dtr(&fifo->channel, txdlh, i) {
+			if (!__hal_channel_is_posted_dtr(&fifo->channel,
+			    i)) {
+				fifo->txdl_term(fifo->channel.vph, txdlh,
+				    VXGE_HAL_FIFO_ULD_PRIV(fifo, txdlh),
+				    VXGE_HAL_TXDL_STATE_FREED,
+				    fifo->channel.userdata,
+				    reopen);
+			}
+		}
+	}
+
+	for (;;) {
+		__hal_channel_dtr_try_complete(&fifo->channel, &txdlh);
+
+		if (txdlh == NULL)
+			break;
+
+		__hal_channel_dtr_complete(&fifo->channel);
+
+		if (fifo->txdl_term) {
+			fifo->txdl_term(fifo->channel.vph, txdlh,
+			    VXGE_HAL_FIFO_ULD_PRIV(fifo, txdlh),
+			    VXGE_HAL_TXDL_STATE_POSTED,
+			    fifo->channel.userdata,
+			    reopen);
+		}
+
+		__hal_channel_dtr_free(&fifo->channel,
+		    VXGE_HAL_FIFO_TXDL_INDEX(txdlh));
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_fifo_reset - Resets the fifo
+ * @fifoh: Fifo to be reset
+ *
+ * This function resets the fifo during vpath reset operation
+ */
+vxge_hal_status_e
+__hal_fifo_reset(
+    vxge_hal_fifo_h fifoh)
+{
+	vxge_hal_status_e status;
+	__hal_device_t *hldev;
+	__hal_fifo_t *fifo = (__hal_fifo_t *) fifoh;
+
+	vxge_assert(fifoh != NULL);
+
+	hldev = (__hal_device_t *) fifo->channel.devh;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("fifo = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) fifoh);
+
+	__hal_fifo_abort(fifoh, VXGE_HAL_RESET_ONLY);
+
+	status = __hal_channel_reset(&fifo->channel);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_fifo_doorbell_reset - Resets the doorbell fifo
+ * @vapth_handle: Vpath Handle
+ *
+ * This function resets the doorbell fifo during if fifo error occurs
+ */
+vxge_hal_status_e
+vxge_hal_fifo_doorbell_reset(
+    vxge_hal_vpath_h vpath_handle)
+{
+	u32 i;
+	vxge_hal_txdl_h txdlh;
+	__hal_fifo_t *fifo;
+	__hal_virtualpath_t *vpath;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vpath = ((__hal_vpath_handle_t *) fifo->channel.vph)->vpath;
+
+	status = __hal_non_offload_db_reset(fifo->channel.vph);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+		    __FILE__, __func__, __LINE__);
+		return (status);
+	}
+
+	__hal_channel_for_each_posted_dtr(&fifo->channel, txdlh, i) {
+
+		txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+		__hal_non_offload_db_post(fifo->channel.vph,
+		    ((VXGE_HAL_FIFO_TXD_NO_BW_LIMIT_GET(
+		    ((vxge_hal_fifo_txd_t *) txdlh)->control_1)) ?
+		    (((u64) txdl_priv->dma_addr) | 0x1) :
+		    (u64) txdl_priv->dma_addr),
+		    txdl_priv->frags - 1,
+		    vpath->vp_config->fifo.no_snoop_bits);
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (status);
+}
+
+/*
+ * __hal_fifo_delete - Removes the FIFO
+ * @vpath_handle: Virtual path handle to which this queue belongs
+ *
+ * This function freeup the memory pool and removes the FIFO
+ */
+void
+__hal_fifo_delete(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	if (fifo->mempool) {
+		__hal_fifo_abort(vp->vpath->fifoh, VXGE_HAL_OPEN_NORMAL);
+		vxge_hal_mempool_destroy(fifo->mempool);
+	}
+
+	vxge_hal_channel_terminate(&fifo->channel);
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock_destroy(&fifo->channel.post_lock,
+	    vp->vpath->hldev->header.pdev);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_destroy_irq(&fifo->channel.post_lock,
+	    vp->vpath->hldev->header.pdev);
+#endif
+
+	vxge_hal_channel_free(&fifo->channel);
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+#if defined(VXGE_HAL_ALIGN_XMIT)
+/*
+ * __hal_fifo_txdl_align_free_unmap - Unmap the alignement buffers
+ * @fifo: Fifo
+ * @txdp: txdl
+ *
+ * This function unmaps dma memory for the alignment buffers
+ */
+void
+__hal_fifo_txdl_align_free_unmap(
+    __hal_fifo_t *fifo,
+    vxge_hal_fifo_txd_t *txdp)
+{
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+
+	vxge_assert((fifo != NULL) && (txdp != NULL));
+
+	hldev = (__hal_device_t *) fifo->channel.devh;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "fifo = 0x"VXGE_OS_STXFMT",  txdp = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) fifo, (ptr_t) txdp);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdp);
+
+	if (txdl_priv->align_vaddr != NULL) {
+		__hal_blockpool_free(fifo->channel.devh,
+		    txdl_priv->align_vaddr,
+		    fifo->align_size,
+		    &txdl_priv->align_dma_addr,
+		    &txdl_priv->align_dma_handle,
+		    &txdl_priv->align_dma_acch);
+
+		txdl_priv->align_vaddr = NULL;
+		txdl_priv->align_dma_addr = 0;
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_fifo_txdl_align_alloc_map - Maps the alignement buffers
+ * @fifo: Fifo
+ * @txdp: txdl
+ *
+ * This function maps dma memory for the alignment buffers
+ */
+vxge_hal_status_e
+__hal_fifo_txdl_align_alloc_map(
+    __hal_fifo_t *fifo,
+    vxge_hal_fifo_txd_t *txdp)
+{
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+
+	vxge_assert((fifo != NULL) && (txdp != NULL));
+
+	hldev = (__hal_device_t *) fifo->channel.devh;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "fifo = 0x"VXGE_OS_STXFMT",  txdp = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) fifo, (ptr_t) txdp);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdp);
+
+	/* allocate alignment DMA-buffer */
+	txdl_priv->align_vaddr =
+	    (u8 *) __hal_blockpool_malloc(fifo->channel.devh,
+	    fifo->align_size,
+	    &txdl_priv->align_dma_addr,
+	    &txdl_priv->align_dma_handle,
+	    &txdl_priv->align_dma_acch);
+	if (txdl_priv->align_vaddr == NULL) {
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+#endif
+/*
+ * vxge_hal_fifo_free_txdl_count_get - returns the number of txdls
+ *                               available in the fifo
+ * @vpath_handle: Virtual path handle.
+ */
+u32
+vxge_hal_fifo_free_txdl_count_get(vxge_hal_vpath_h vpath_handle)
+{
+	return __hal_channel_free_dtr_count(&((__hal_fifo_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath->fifoh)->channel);
+}
+
+/*
+ * vxge_hal_fifo_txdl_private_get - Retrieve per-descriptor private data.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ *
+ * Retrieve per-descriptor private data.
+ * Note that ULD requests per-descriptor space via
+ * vxge_hal_fifo_attr_t passed to
+ * vxge_hal_vpath_open().
+ *
+ * Returns: private ULD data associated with the descriptor.
+ */
+void *
+vxge_hal_fifo_txdl_private_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh)
+{
+	return (VXGE_HAL_FIFO_ULD_PRIV(((__hal_fifo_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath->fifoh), txdlh));
+}
+
+/*
+ * vxge_hal_fifo_txdl_reserve - Reserve fifo descriptor.
+ * @vapth_handle: virtual path handle.
+ * @txdlh: Reserved descriptor. On success HAL fills this "out" parameter
+ *	with a valid handle.
+ * @txdl_priv: Buffer to return the pointer to per txdl space
+ *
+ * Reserve a single TxDL (that is, fifo descriptor)
+ * for the subsequent filling-in by upper layerdriver (ULD))
+ * and posting on the corresponding channel (@channelh)
+ * via vxge_hal_fifo_txdl_post().
+ *
+ * Note: it is the responsibility of ULD to reserve multiple descriptors
+ * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
+ * carries up to configured number (fifo.max_frags) of contiguous buffers.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
+ *
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_reserve(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h *txdlh,
+    void **txdl_priv)
+{
+	u32 i;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_fifo_t *fifo;
+	vxge_hal_status_e status;
+
+#if defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	unsigned long flags = 0;
+
+#endif
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT",  txdlh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) txdlh);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	status = __hal_channel_dtr_reserve(&fifo->channel, txdlh);
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_unlock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	if (status == VXGE_HAL_OK) {
+		vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *)*txdlh;
+		__hal_fifo_txdl_priv_t *priv;
+
+		priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdp);
+
+		/* reset the TxDL's private */
+		priv->align_dma_offset = 0;
+		priv->align_vaddr_start = priv->align_vaddr;
+		priv->align_used_frags = 0;
+		priv->frags = 0;
+		priv->alloc_frags = fifo->config->max_frags;
+		priv->dang_txdl = NULL;
+		priv->dang_frags = 0;
+		priv->next_txdl_priv = NULL;
+		priv->bytes_sent = 0;
+
+		*txdl_priv = VXGE_HAL_FIFO_ULD_PRIV(fifo, txdp);
+
+		for (i = 0; i < fifo->config->max_frags; i++) {
+			txdp = ((vxge_hal_fifo_txd_t *)*txdlh) + i;
+			txdp->control_0 = txdp->control_1 = 0;
+		}
+
+#if defined(VXGE_OS_MEMORY_CHECK)
+		priv->allocated = 1;
+#endif
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (status);
+}
+
+/*
+ * vxge_hal_fifo_txdl_buffer_set - Set transmit buffer pointer in the
+ * descriptor.
+ * @vpath_handle: virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @frag_idx: Index of the data buffer in the caller's scatter-gather list
+ *	   (of buffers).
+ * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
+ * @size: Size of the data buffer (in bytes).
+ *
+ * This API is part of the preparation of the transmit descriptor for posting
+ * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include
+ * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits().
+ * All three APIs fill in the fields of the fifo descriptor,
+ * in accordance with the X3100 specification.
+ *
+ */
+void
+vxge_hal_fifo_txdl_buffer_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 frag_idx,
+    dma_addr_t dma_pointer,
+    unsigned long size)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	vxge_hal_fifo_txd_t *txdp;
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL) &&
+	    (dma_pointer != 0) && (size != 0));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", frag_idx = %d, "
+	    "dma_pointer = 0x"VXGE_OS_LLXFMT", size = %lu",
+	    (ptr_t) vpath_handle, (ptr_t) txdlh,
+	    frag_idx, (u64) dma_pointer, size);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+	txdp = (vxge_hal_fifo_txd_t *) txdlh + txdl_priv->frags;
+
+	/*
+	 * Note:
+	 * it is the responsibility of upper layers and not HAL
+	 * detect it and skip zero-size fragment
+	 */
+	vxge_assert(size > 0);
+	vxge_assert(frag_idx < txdl_priv->alloc_frags);
+
+	txdp->buffer_pointer = (u64) dma_pointer;
+	txdp->control_0 |= VXGE_HAL_FIFO_TXD_BUFFER_SIZE(size);
+	txdl_priv->bytes_sent += size;
+	fifo->stats->total_buffers++;
+	txdl_priv->frags++;
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_fifo_txdl_buffer_set_aligned - Align transmit buffer and fill
+ * in fifo descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @frag_idx: Index of the data buffer in the caller's scatter-gather list
+ *	   (of buffers).
+ * @vaddr: Virtual address of the data buffer.
+ * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
+ * @size: Size of the data buffer (in bytes).
+ * @misaligned_size: Size (in bytes) of the misaligned portion of the
+ * data buffer. Calculated by the caller, based on the platform/OS/other
+ * specific criteria, which is outside of HAL's domain. See notes below.
+ *
+ * This API is part of the transmit descriptor preparation for posting
+ * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include
+ * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits().
+ * All three APIs fill in the fields of the fifo descriptor,
+ * in accordance with the X3100 specification.
+ * On the PCI-X based systems aligning transmit data typically provides better
+ * transmit performance. The typical alignment granularity: L2 cacheline size.
+ * However, HAL does not make assumptions in terms of the alignment granularity;
+ * this is specified via additional @misaligned_size parameter described above.
+ * Prior to calling vxge_hal_fifo_txdl_buffer_set_aligned(),
+ * ULD is supposed to check alignment of a given fragment/buffer. For this HAL
+ * provides a separate vxge_hal_check_alignment() API sufficient to cover
+ * most (but not all) possible alignment criteria.
+ * If the buffer appears to be aligned, the ULD calls
+ * vxge_hal_fifo_txdl_buffer_set().
+ * Otherwise, ULD calls vxge_hal_fifo_txdl_buffer_set_aligned().
+ *
+ * Note; This API is a "superset" of vxge_hal_fifo_txdl_buffer_set(). In
+ * addition to filling in the specified descriptor it aligns transmit data on
+ * the specified boundary.
+ * Note: Decision on whether to align or not to align a given contiguous
+ * transmit buffer is outside of HAL's domain. To this end ULD can use any
+ * programmable criteria, which can help to 1) boost transmit performance,
+ * and/or 2) provide a workaround for PCI bridge bugs, if any.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_buffer_set_aligned(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 frag_idx,
+    void *vaddr,
+    dma_addr_t dma_pointer,
+    u32 size,
+    u32 misaligned_size)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	vxge_hal_fifo_txd_t *txdp;
+	int remaining_size;
+	ptrdiff_t prev_boff;
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL) &&
+	    (vaddr != 0) && (dma_pointer != 0) &&
+	    (size != 0) && (misaligned_size != 0));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", txdlh = 0x"VXGE_OS_STXFMT", "
+	    "frag_idx = %d, vaddr = 0x"VXGE_OS_STXFMT", "
+	    "dma_pointer = 0x"VXGE_OS_LLXFMT", size = %d, "
+	    "misaligned_size = %d", (ptr_t) vpath_handle,
+	    (ptr_t) txdlh, frag_idx, (ptr_t) vaddr, (u64) dma_pointer, size,
+	    misaligned_size);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+	txdp = (vxge_hal_fifo_txd_t *) txdlh + txdl_priv->frags;
+
+	/*
+	 * On some systems buffer size could be zero.
+	 * It is the responsibility of ULD and *not HAL* to
+	 * detect it and skip it.
+	 */
+	vxge_assert(size > 0);
+	vxge_assert(frag_idx < txdl_priv->alloc_frags);
+	vxge_assert(misaligned_size != 0 &&
+	    misaligned_size <= fifo->config->alignment_size);
+
+	remaining_size = size - misaligned_size;
+	vxge_assert(remaining_size >= 0);
+
+	vxge_os_memcpy((char *) txdl_priv->align_vaddr_start,
+	    vaddr, misaligned_size);
+
+	if (txdl_priv->align_used_frags >= fifo->config->max_aligned_frags) {
+		return (VXGE_HAL_ERR_OUT_ALIGNED_FRAGS);
+	}
+
+	/* setup new buffer */
+	/* LINTED */
+	prev_boff = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr;
+	txdp->buffer_pointer = (u64) txdl_priv->align_dma_addr + prev_boff;
+	txdp->control_0 |= VXGE_HAL_FIFO_TXD_BUFFER_SIZE(misaligned_size);
+	txdl_priv->bytes_sent += misaligned_size;
+	fifo->stats->total_buffers++;
+	txdl_priv->frags++;
+	txdl_priv->align_used_frags++;
+	txdl_priv->align_vaddr_start += fifo->config->alignment_size;
+	txdl_priv->align_dma_offset = 0;
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC)
+	/* sync new buffer */
+	vxge_os_dma_sync(fifo->channel.pdev,
+	    txdl_priv->align_dma_handle,
+	    txdp->buffer_pointer,
+	    0,
+	    misaligned_size,
+	    VXGE_OS_DMA_DIR_TODEVICE);
+#endif
+
+	if (remaining_size) {
+		vxge_assert(frag_idx < txdl_priv->alloc_frags);
+		txdp++;
+		txdp->buffer_pointer = (u64) dma_pointer + misaligned_size;
+		txdp->control_0 |=
+		    VXGE_HAL_FIFO_TXD_BUFFER_SIZE(remaining_size);
+		txdl_priv->bytes_sent += remaining_size;
+		fifo->stats->total_buffers++;
+		txdl_priv->frags++;
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_fifo_txdl_buffer_append - Append the contents of virtually
+ *		contiguous data buffer to a single physically contiguous buffer.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @vaddr: Virtual address of the data buffer.
+ * @size: Size of the data buffer (in bytes).
+ *
+ * This API is part of the transmit descriptor preparation for posting
+ * (via vxge_hal_fifo_txdl_post()).
+ * The main difference of this API wrt to the APIs
+ * vxge_hal_fifo_txdl_buffer_set_aligned() is that this API appends the
+ * contents of virtually contiguous data buffers received from
+ * upper layer into a single physically contiguous data buffer and the
+ * device will do a DMA from this buffer.
+ *
+ * See Also: vxge_hal_fifo_txdl_buffer_finalize(),
+ * vxge_hal_fifo_txdl_buffer_set(),
+ * vxge_hal_fifo_txdl_buffer_set_aligned().
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_buffer_append(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    void *vaddr,
+    u32 size)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	ptrdiff_t used;
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL) && (vaddr != 0) &&
+	    (size == 0));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", vaddr = 0x"VXGE_OS_STXFMT", "
+	    "size = %d", (ptr_t) vpath_handle, (ptr_t) txdlh,
+	    (ptr_t) vaddr, size);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+	/* LINTED */
+	used = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr;
+	used += txdl_priv->align_dma_offset;
+
+	if (used + (unsigned int)size > (unsigned int)fifo->align_size)
+		return (VXGE_HAL_ERR_OUT_ALIGNED_FRAGS);
+
+	vxge_os_memcpy((char *) txdl_priv->align_vaddr_start +
+	    txdl_priv->align_dma_offset, vaddr, size);
+
+	fifo->stats->copied_frags++;
+
+	txdl_priv->align_dma_offset += size;
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_fifo_txdl_buffer_finalize - Prepares a descriptor that contains the
+ * single physically contiguous buffer.
+ *
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @frag_idx: Index of the data buffer in the Txdl list.
+ *
+ * This API in conjuction with vxge_hal_fifo_txdl_buffer_append() prepares
+ * a descriptor that consists of a single physically contiguous buffer
+ * which inturn contains the contents of one or more virtually contiguous
+ * buffers received from the upper layer.
+ *
+ * See Also: vxge_hal_fifo_txdl_buffer_append().
+ */
+void
+vxge_hal_fifo_txdl_buffer_finalize(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 frag_idx)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	vxge_hal_fifo_txd_t *txdp;
+	ptrdiff_t prev_boff;
+
+	vxge_assert((vpath_handle != NULL) &&
+	    (txdlh != NULL) && (frag_idx != 0));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", frag_idx = %d", (ptr_t) vpath_handle,
+	    (ptr_t) txdlh, frag_idx);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+	txdp = (vxge_hal_fifo_txd_t *) txdlh + txdl_priv->frags;
+
+	/* LINTED */
+	prev_boff = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr;
+	txdp->buffer_pointer = (u64) txdl_priv->align_dma_addr + prev_boff;
+	txdp->control_0 |=
+	    VXGE_HAL_FIFO_TXD_BUFFER_SIZE(txdl_priv->align_dma_offset);
+	txdl_priv->bytes_sent += (unsigned int)txdl_priv->align_dma_offset;
+	fifo->stats->total_buffers++;
+	fifo->stats->copied_buffers++;
+	txdl_priv->frags++;
+	txdl_priv->align_used_frags++;
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC)
+	/* sync pre-mapped buffer */
+	vxge_os_dma_sync(fifo->channel.pdev,
+	    txdl_priv->align_dma_handle,
+	    txdp->buffer_pointer,
+	    0,
+	    txdl_priv->align_dma_offset,
+	    VXGE_OS_DMA_DIR_TODEVICE);
+#endif
+
+	/* increment vaddr_start for the next buffer_append() iteration */
+	txdl_priv->align_vaddr_start += txdl_priv->align_dma_offset;
+	txdl_priv->align_dma_offset = 0;
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_fifo_txdl_new_frame_set - Start the new packet by setting TXDL flags
+ * @vpath_handle: virtual path handle.
+ * @txdlh: Descriptor handle.
+ * @tagged: Is the frame tagged
+ *
+ * This API is part of the preparation of the transmit descriptor for posting
+ * (via vxge_hal_fifo_txdl_post()). This api is used to mark the end of previous
+ * frame and start of a new frame.
+ *
+ */
+void
+vxge_hal_fifo_txdl_new_frame_set(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 tagged)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	vxge_hal_fifo_txd_t *txdp;
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", tagged = %d",
+	    (ptr_t) vpath_handle, (ptr_t) txdlh, tagged);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+	txdp = (vxge_hal_fifo_txd_t *) txdlh + txdl_priv->frags;
+
+	txdp->control_0 |=
+	    VXGE_HAL_FIFO_TXD_HOST_STEER(vp->vpath->vp_config->wire_port);
+	txdp->control_0 |= VXGE_HAL_FIFO_TXD_GATHER_CODE(
+	    VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST);
+	txdp->control_1 |= fifo->interrupt_type;
+	txdp->control_1 |= VXGE_HAL_FIFO_TXD_INT_NUMBER(
+	    vp->vpath->tx_intr_num);
+	if (tagged)
+		txdp->control_1 |= VXGE_HAL_FIFO_TXD_NO_BW_LIMIT;
+	if (txdl_priv->frags) {
+
+		txdp = (vxge_hal_fifo_txd_t *) txdlh + (txdl_priv->frags - 1);
+
+		txdp->control_0 |= VXGE_HAL_FIFO_TXD_GATHER_CODE(
+		    VXGE_HAL_FIFO_TXD_GATHER_CODE_LAST);
+
+	}
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_fifo_txdl_post - Post descriptor on the fifo channel.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor obtained via vxge_hal_fifo_txdl_reserve()
+ * @tagged: Is the frame tagged
+ *
+ * Post descriptor on the 'fifo' type channel for transmission.
+ * Prior to posting the descriptor should be filled in accordance with
+ * Host/X3100 interface specification for a given service (LL, etc.).
+ *
+ */
+void
+vxge_hal_fifo_txdl_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    u32 tagged)
+{
+	u64 list_ptr;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	vxge_hal_fifo_txd_t *txdp_last;
+	vxge_hal_fifo_txd_t *txdp_first;
+
+#if defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	unsigned long flags = 0;
+
+#endif
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", tagged = %d",
+	    (ptr_t) vpath_handle, (ptr_t) txdlh, tagged);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+	txdp_first = (vxge_hal_fifo_txd_t *) txdlh;
+	txdp_first->control_0 |=
+	    VXGE_HAL_FIFO_TXD_HOST_STEER(vp->vpath->vp_config->wire_port);
+	txdp_first->control_0 |=
+	    VXGE_HAL_FIFO_TXD_GATHER_CODE(VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST);
+	txdp_first->control_1 |=
+	    VXGE_HAL_FIFO_TXD_INT_NUMBER(vp->vpath->tx_intr_num);
+	txdp_first->control_1 |= fifo->interrupt_type;
+	list_ptr = (u64) txdl_priv->dma_addr;
+	if (tagged) {
+		txdp_first->control_1 |= VXGE_HAL_FIFO_TXD_NO_BW_LIMIT;
+		list_ptr |= 0x1;
+	}
+
+	txdp_last =
+	    (vxge_hal_fifo_txd_t *) txdlh + (txdl_priv->frags - 1);
+	txdp_last->control_0 |=
+	    VXGE_HAL_FIFO_TXD_GATHER_CODE(VXGE_HAL_FIFO_TXD_GATHER_CODE_LAST);
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	txdp_first->control_0 |= VXGE_HAL_FIFO_TXD_LIST_OWN_ADAPTER;
+
+#if defined(VXGE_DEBUG_ASSERT)
+	/* make sure device overwrites the t_code value on completion */
+	txdp_first->control_0 |=
+	    VXGE_HAL_FIFO_TXD_T_CODE(VXGE_HAL_FIFO_TXD_T_CODE_UNUSED);
+#endif
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_TXDL_STREAMING)
+	/* sync the TxDL to device */
+	vxge_os_dma_sync(fifo->channel.pdev,
+	    txdl_priv->dma_handle,
+	    txdl_priv->dma_addr,
+	    txdl_priv->dma_offset,
+	    txdl_priv->frags << 5, /* sizeof(vxge_hal_fifo_txd_t) */
+	    VXGE_OS_DMA_DIR_TODEVICE);
+#endif
+	/*
+	 * we want touch dtr_arr in order with ownership bit set to HW
+	 */
+	__hal_channel_dtr_post(&fifo->channel, VXGE_HAL_FIFO_TXDL_INDEX(txdlh));
+
+	__hal_non_offload_db_post(vpath_handle,
+	    list_ptr,
+	    txdl_priv->frags - 1,
+	    vp->vpath->vp_config->fifo.no_snoop_bits);
+
+#if defined(VXGE_HAL_FIFO_DUMP_TXD)
+	vxge_hal_info_log_fifo(
+	    ""VXGE_OS_LLXFMT":"VXGE_OS_LLXFMT":"VXGE_OS_LLXFMT":"
+	    VXGE_OS_LLXFMT" dma "VXGE_OS_LLXFMT,
+	    txdp_first->control_0, txdp_first->control_1,
+	    txdp_first->buffer_pointer, VXGE_HAL_FIFO_TXDL_INDEX(txdp_first),
+	    txdl_priv->dma_addr);
+#endif
+
+	fifo->stats->total_posts++;
+	fifo->stats->common_stats.usage_cnt++;
+	if (fifo->stats->common_stats.usage_max <
+	    fifo->stats->common_stats.usage_cnt)
+		fifo->stats->common_stats.usage_max =
+		    fifo->stats->common_stats.usage_cnt;
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_unlock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_fifo_is_next_txdl_completed - Checks if the next txdl is completed
+ * @vpath_handle: Virtual path handle.
+ */
+vxge_hal_status_e
+vxge_hal_fifo_is_next_txdl_completed(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	vxge_hal_fifo_txd_t *txdp;
+	vxge_hal_txdl_h txdlh;
+	vxge_hal_status_e status = VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
+
+#if defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	unsigned long flags = 0;
+
+#endif
+
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	__hal_channel_dtr_try_complete(&fifo->channel, &txdlh);
+
+	txdp = (vxge_hal_fifo_txd_t *) txdlh;
+	if ((txdp != NULL) &&
+	    (!(txdp->control_0 & VXGE_HAL_FIFO_TXD_LIST_OWN_ADAPTER))) {
+		status = VXGE_HAL_OK;
+	}
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_unlock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	/* no more completions */
+	return (status);
+}
+
+/*
+ * vxge_hal_fifo_txdl_next_completed - Retrieve next completed descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle. Returned by HAL.
+ * @txdl_priv: Buffer to return the pointer to per txdl space
+ * @t_code: Transfer code, as per X3100 User Guide,
+ *	 Transmit Descriptor Format.
+ *	 Returned by HAL.
+ *
+ * Retrieve the _next_ completed descriptor.
+ * HAL uses channel callback (*vxge_hal_channel_callback_f) to notifiy
+ * upper-layer driver (ULD) of new completed descriptors. After that
+ * the ULD can use vxge_hal_fifo_txdl_next_completed to retrieve the rest
+ * completions (the very first completion is passed by HAL via
+ * vxge_hal_channel_callback_f).
+ *
+ * Implementation-wise, the upper-layer driver is free to call
+ * vxge_hal_fifo_txdl_next_completed either immediately from inside the
+ * channel callback, or in a deferred fashion and separate (from HAL)
+ * context.
+ *
+ * Non-zero @t_code means failure to process the descriptor.
+ * The failure could happen, for instance, when the link is
+ * down, in which case X3100 completes the descriptor because it
+ * is not able to send the data out.
+ *
+ * For details please refer to X3100 User Guide.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
+ * are currently available for processing.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_fifo_txdl_next_completed(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h * txdlh,
+    void **txdl_priv,
+    vxge_hal_fifo_tcode_e * t_code)
+{
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	vxge_hal_fifo_txd_t *txdp;
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_TXDL_STREAMING)
+	__hal_fifo_txdl_priv_t *priv;
+
+#endif
+#if defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	unsigned long flags = 0;
+
+#endif
+
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	vxge_hal_status_e status = VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
+
+	vxge_assert((vpath_handle != NULL) &&
+	    (txdlh != NULL) && (t_code != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", t_code = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) txdlh, (ptr_t) t_code);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	*txdlh = 0;
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	__hal_channel_dtr_try_complete(&fifo->channel, txdlh);
+
+	txdp = (vxge_hal_fifo_txd_t *) * txdlh;
+	if (txdp != NULL) {
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_TXDL_STREAMING)
+		priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdp);
+
+		/*
+		 * sync TxDL to read the ownership
+		 *
+		 * Note: 16bytes means Control_1 & Control_2
+		 */
+		vxge_os_dma_sync(fifo->channel.pdev,
+		    priv->dma_handle,
+		    priv->dma_addr,
+		    priv->dma_offset,
+		    16,
+		    VXGE_OS_DMA_DIR_FROMDEVICE);
+#endif
+
+		/* check whether host owns it */
+		if (!(txdp->control_0 & VXGE_HAL_FIFO_TXD_LIST_OWN_ADAPTER)) {
+
+			__hal_channel_dtr_complete(&fifo->channel);
+
+			*txdl_priv = VXGE_HAL_FIFO_ULD_PRIV(fifo, txdp);
+
+			*t_code = (vxge_hal_fifo_tcode_e)
+			    VXGE_HAL_FIFO_TXD_T_CODE_GET(txdp->control_0);
+
+			if (fifo->stats->common_stats.usage_cnt > 0)
+				fifo->stats->common_stats.usage_cnt--;
+
+			status = VXGE_HAL_OK;
+		}
+	}
+
+	/* no more completions */
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_unlock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_fifo_handle_tcode - Handle transfer code.
+ * @vpath_handle: Virtual Path handle.
+ * @txdlh: Descriptor handle.
+ * @t_code: One of the enumerated (and documented in the X3100 user guide)
+ *	 "transfer codes".
+ *
+ * Handle descriptor's transfer code. The latter comes with each completed
+ * descriptor.
+ *
+ * Returns: one of the vxge_hal_status_e {} enumerated types.
+ * VXGE_HAL_OK			- for success.
+ * VXGE_HAL_ERR_CRITICAL	- when encounters critical error.
+ */
+vxge_hal_status_e
+vxge_hal_fifo_handle_tcode(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh,
+    vxge_hal_fifo_tcode_e t_code)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT", t_code = 0x%d",
+	    (ptr_t) vpath_handle, (ptr_t) txdlh, t_code);
+
+	switch ((t_code & 0x7)) {
+	case 0:
+		/* 000: Transfer operation completed successfully. */
+		break;
+	case 1:
+		/*
+		 * 001: a PCI read transaction (either TxD or frame data)
+		 *	returned with corrupt data.
+		 */
+		break;
+	case 2:
+		/* 010: a PCI read transaction was returned with no data. */
+		break;
+	case 3:
+		/*
+		 * 011: The host attempted to send either a frame or LSO
+		 *	MSS that was too long (>9800B).
+		 */
+		break;
+	case 4:
+		/*
+		 * 100: Error detected during TCP/UDP Large Send
+		 *	Offload operation, due to improper header template,
+		 *	unsupported protocol, etc.
+		 */
+		break;
+	default:
+		vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_TCODE);
+		return (VXGE_HAL_ERR_INVALID_TCODE);
+	}
+
+	vp->vpath->sw_stats->fifo_stats.txd_t_code_err_cnt[t_code]++;
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, VXGE_HAL_OK);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_fifo_txdl_free_many - Free the fragments
+ * @fifo: FIFO
+ * @txdp: Poniter to a TxD
+ * @list_size: List size
+ * @frags: Number of fragments
+ *
+ * This routinf frees the fragments in a txdl
+ */
+void
+__hal_fifo_txdl_free_many(
+    __hal_fifo_t *fifo,
+    vxge_hal_fifo_txd_t * txdp,
+    u32 list_size,
+    u32 frags)
+{
+	__hal_fifo_txdl_priv_t *current_txdl_priv;
+	__hal_fifo_txdl_priv_t *next_txdl_priv;
+	u32 invalid_frags = frags % list_size;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) fifo->channel.vph;
+	__hal_device_t *hldev;
+
+	vxge_assert((fifo != NULL) && (txdp != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo(
+	    "fifo = 0x"VXGE_OS_STXFMT", txdp = 0x"VXGE_OS_STXFMT", "
+	    "list_size = %d, frags = %d", (ptr_t) fifo, (ptr_t) txdp,
+	    list_size, frags);
+
+	if (invalid_frags) {
+		vxge_hal_trace_log_fifo(
+		    "freeing corrupt txdlh 0x"VXGE_OS_STXFMT", "
+		    "fragments %d list size %d",
+		    (ptr_t) txdp, frags, list_size);
+		vxge_assert(invalid_frags == 0);
+	}
+	while (txdp) {
+		vxge_hal_trace_log_fifo("freeing linked txdlh 0x"VXGE_OS_STXFMT
+		    ", " "fragments %d list size %d",
+		    (ptr_t) txdp, frags, list_size);
+		current_txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdp);
+#if defined(VXGE_DEBUG_ASSERT) && defined(VXGE_OS_MEMORY_CHECK)
+		current_txdl_priv->allocated = 0;
+#endif
+		__hal_channel_dtr_free(&fifo->channel,
+		    VXGE_HAL_FIFO_TXDL_INDEX(txdp));
+		next_txdl_priv = current_txdl_priv->next_txdl_priv;
+		vxge_assert(frags);
+		frags -= list_size;
+		if (next_txdl_priv) {
+			current_txdl_priv->next_txdl_priv = NULL;
+			txdp = next_txdl_priv->first_txdp;
+		} else {
+			vxge_hal_trace_log_fifo(
+			    "freed linked txdlh fragments %d list size %d",
+			    frags, list_size);
+			break;
+		}
+	}
+
+	vxge_assert(frags == 0);
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_fifo_txdl_free - Free descriptor.
+ * @vpath_handle: Virtual path handle.
+ * @txdlh: Descriptor handle.
+ *
+ * Free the reserved descriptor. This operation is "symmetrical" to
+ * vxge_hal_fifo_txdl_reserve. The "free-ing" completes the descriptor's
+ * lifecycle.
+ *
+ * After free-ing (see vxge_hal_fifo_txdl_free()) the descriptor again can
+ * be:
+ *
+ * - reserved (vxge_hal_fifo_txdl_reserve);
+ *
+ * - posted (vxge_hal_fifo_txdl_post);
+ *
+ * - completed (vxge_hal_fifo_txdl_next_completed);
+ *
+ * - and recycled again (vxge_hal_fifo_txdl_free).
+ *
+ * For alternative state transitions and more details please refer to
+ * the design doc.
+ *
+ */
+void
+vxge_hal_fifo_txdl_free(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_txdl_h txdlh)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+	u32 max_frags;
+
+#if defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	u32 flags = 0;
+
+#endif
+	vxge_assert((vpath_handle != NULL) && (txdlh != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_fifo("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_fifo("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "txdlh = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle, (ptr_t) txdlh);
+
+	fifo = (__hal_fifo_t *) vp->vpath->fifoh;
+
+	vxge_assert(fifo != NULL);
+
+	txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+	max_frags = fifo->config->max_frags;
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_lock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	if (txdl_priv->alloc_frags > max_frags) {
+		vxge_hal_fifo_txd_t *dang_txdp = (vxge_hal_fifo_txd_t *)
+		txdl_priv->dang_txdl;
+		u32 dang_frags = txdl_priv->dang_frags;
+		u32 alloc_frags = txdl_priv->alloc_frags;
+		txdl_priv->dang_txdl = NULL;
+		txdl_priv->dang_frags = 0;
+		txdl_priv->alloc_frags = 0;
+		/* txdlh must have a linked list of txdlh */
+		vxge_assert(txdl_priv->next_txdl_priv);
+
+		/* free any dangling txdlh first */
+		if (dang_txdp) {
+			vxge_hal_info_log_fifo(
+			    "freeing dangled txdlh 0x"VXGE_OS_STXFMT" for %d "
+			    "fragments", (ptr_t) dang_txdp, dang_frags);
+			__hal_fifo_txdl_free_many(fifo, dang_txdp,
+			    max_frags, dang_frags);
+		}
+
+		/* now free the reserved txdlh list */
+		vxge_hal_info_log_fifo(
+		    "freeing txdlh 0x"VXGE_OS_STXFMT" list of %d fragments",
+		    (ptr_t) txdlh, alloc_frags);
+		__hal_fifo_txdl_free_many(fifo,
+		    (vxge_hal_fifo_txd_t *) txdlh, max_frags,
+		    alloc_frags);
+	} else {
+		__hal_channel_dtr_free(&fifo->channel,
+		    VXGE_HAL_FIFO_TXDL_INDEX(txdlh));
+	}
+
+	fifo->channel.poll_bytes += txdl_priv->bytes_sent;
+
+#if defined(VXGE_DEBUG_ASSERT) && defined(VXGE_OS_MEMORY_CHECK)
+	txdl_priv->allocated = 0;
+#endif
+
+#if defined(VXGE_HAL_TX_MULTI_POST)
+	vxge_os_spin_unlock(&fifo->channel.post_lock);
+#elif defined(VXGE_HAL_TX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&fifo->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_fifo("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-fifo.h b/sys/dev/vxge/vxgehal/vxgehal-fifo.h
new file mode 100644
index 000000000000..5cb20bc36568
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-fifo.h
@@ -0,0 +1,223 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_FIFO_H
+#define	VXGE_HAL_FIFO_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * struct __hal_fifo_t - Fifo.
+ * @channel: Channel "base" of this fifo, the common part of all HAL
+ *		channels.
+ * @mempool: Memory pool, from which descriptors get allocated.
+ * @config: Fifo configuration, part of device configuration
+ *		(see vxge_hal_device_config_t {}).
+ * @interrupt_type: Interrupt type to be used
+ * @no_snoop_bits: See vxge_hal_fifo_config_t {}.
+ * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
+ *		bytes. Setting @memblock_size to page size ensures
+ *		by-page allocation of descriptors. 128K bytes is the
+ *		maximum supported block size.
+ * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
+ *		on TxDL please refer to X3100 UG.
+ * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
+ *		per-TxDL HAL private space (__hal_fifo_txdl_priv_t).
+ * @txdl_priv_size: Per-TxDL space reserved for HAL and ULD
+ * @per_txdl_space: Per txdl private space for the ULD
+ * @txdlblock_priv_size: Total private space per TXDL memory block
+ * @align_size: Cache alignment size
+ * @callback: Fifo completion callback. HAL invokes the callback when there
+ *		are new completions on that fifo. In many implementations
+ *		the @callback executes in the hw interrupt context.
+ * @txdl_init: Fifo's descriptor-initialize callback.
+ *		See vxge_hal_fifo_txdl_init_f {}.
+ *		If not NULL, HAL invokes the callback when opening
+ *		the fifo via vxge_hal_vpath_open().
+ * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
+ *		HAL invokes the callback when closing the corresponding fifo.
+ *		See also vxge_hal_fifo_txdl_term_f {}.
+ * @stats: Statistics of this fifo
+ *
+ * Fifo channel.
+ * Note: The structure is cache line aligned.
+ */
+typedef struct __hal_fifo_t {
+	__hal_channel_t				channel;
+	vxge_hal_mempool_t			*mempool;
+	vxge_hal_fifo_config_t			*config;
+	u64					interrupt_type;
+	u32					no_snoop_bits;
+	u32					memblock_size;
+	u32					txdl_per_memblock;
+	u32					txdl_size;
+	u32					txdl_priv_size;
+	u32					per_txdl_space;
+	u32					txdlblock_priv_size;
+	u32					align_size;
+	vxge_hal_fifo_callback_f		callback;
+	vxge_hal_fifo_txdl_init_f		txdl_init;
+	vxge_hal_fifo_txdl_term_f		txdl_term;
+	vxge_hal_vpath_stats_sw_fifo_info_t	*stats;
+} __vxge_os_attr_cacheline_aligned __hal_fifo_t;
+
+/*
+ * struct __hal_fifo_txdl_priv_t - Transmit descriptor HAL-private data.
+ * @dma_addr: DMA (mapped) address of _this_ descriptor.
+ * @dma_handle: DMA handle used to map the descriptor onto device.
+ * @dma_offset: Descriptor's offset in the memory block. HAL allocates
+ *		  descriptors in memory blocks (see vxge_hal_fifo_config_t {})
+ *		Each memblock is a contiguous block of DMA-able memory.
+ * @frags: Total number of fragments (that is, contiguous data buffers)
+ * carried by this TxDL.
+ * @align_vaddr_start: Aligned virtual address start
+ * @align_vaddr: Virtual address of the per-TxDL area in memory used for
+ *		alignement. Used to place one or more mis-aligned fragments
+ *		(the maximum defined by configration variable
+ *		@max_aligned_frags).
+ * @align_dma_addr: DMA address translated from the @align_vaddr.
+ * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
+ * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
+ * @align_dma_offset: The current offset into the @align_vaddr area.
+ * Grows while filling the descriptor, gets reset.
+ * @align_used_frags: Number of fragments used.
+ * @alloc_frags: Total number of fragments allocated.
+ * @dang_frags: Number of fragments kept from release until this TxDL is freed.
+ * @bytes_sent:
+ * @unused:
+ * @dang_txdl:
+ * @next_txdl_priv:
+ * @first_txdp:
+ * @dang_txdlh: Pointer to TxDL (list) kept from release until this TxDL
+ *		is freed.
+ * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
+ *		TxDL list.
+ * @txdlh: Corresponding txdlh to this TxDL.
+ * @memblock: Pointer to the TxDL memory block or memory page.
+ *		on the next send operation.
+ * @dma_object: DMA address and handle of the memory block that contains
+ *		the descriptor. This member is used only in the "checked"
+ *		version of the HAL (to enforce certain assertions);
+ *		otherwise it gets compiled out.
+ * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
+ *
+ * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
+ * information associated with the descriptor. Note that ULD can ask HAL
+ * to allocate additional per-descriptor space for its own (ULD-specific)
+ * purposes.
+ *
+ * See also: vxge_hal_ring_rxd_priv_t {}.
+ */
+typedef struct __hal_fifo_txdl_priv_t {
+	dma_addr_t			dma_addr;
+	pci_dma_h			dma_handle;
+	ptrdiff_t			dma_offset;
+	u32				frags;
+	u8				*align_vaddr_start;
+	u8				*align_vaddr;
+	dma_addr_t			align_dma_addr;
+	pci_dma_h			align_dma_handle;
+	pci_dma_acc_h			align_dma_acch;
+	ptrdiff_t			align_dma_offset;
+	u32				align_used_frags;
+	u32				alloc_frags;
+	u32				dang_frags;
+	u32				bytes_sent;
+	u32				unused;
+	vxge_hal_fifo_txd_t		*dang_txdl;
+	struct __hal_fifo_txdl_priv_t	*next_txdl_priv;
+	vxge_hal_fifo_txd_t		*first_txdp;
+	void				*memblock;
+#if defined(VXGE_DEBUG_ASSERT)
+	vxge_hal_mempool_dma_t		*dma_object;
+#endif
+#if defined(VXGE_OS_MEMORY_CHECK)
+	u32				allocated;
+#endif
+} __hal_fifo_txdl_priv_t;
+
+#define	VXGE_HAL_FIFO_ULD_PRIV(fifo, txdh)				\
+	fifo->channel.dtr_arr[						\
+		((vxge_hal_fifo_txd_t *)(txdh))->host_control].uld_priv
+
+#define	VXGE_HAL_FIFO_HAL_PRIV(fifo, txdh)				\
+	((__hal_fifo_txdl_priv_t *)(fifo->channel.dtr_arr[		\
+		((vxge_hal_fifo_txd_t *)(txdh))->host_control].hal_priv))
+
+#define	VXGE_HAL_FIFO_MAX_FRAG_CNT(fifo) fifo->config->max_frags
+
+#define	VXGE_HAL_FIFO_TXDL_INDEX(txdp)	\
+	(u32)((vxge_hal_fifo_txd_t *)txdp)->host_control
+
+/* ========================= FIFO PRIVATE API ============================= */
+
+vxge_hal_status_e
+__hal_fifo_create(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_fifo_attr_t *attr);
+
+void
+__hal_fifo_abort(
+    vxge_hal_fifo_h fifoh,
+    vxge_hal_reopen_e reopen);
+
+vxge_hal_status_e
+__hal_fifo_reset(
+    vxge_hal_fifo_h ringh);
+
+void
+__hal_fifo_delete(
+    vxge_hal_vpath_h vpath_handle);
+
+void
+__hal_fifo_txdl_free_many(
+    __hal_fifo_t *fifo,
+    vxge_hal_fifo_txd_t *txdp,
+    u32 list_size,
+    u32 frags);
+
+#if defined(VXGE_HAL_ALIGN_XMIT)
+void
+__hal_fifo_txdl_align_free_unmap(
+    __hal_fifo_t *fifo,
+    vxge_hal_fifo_txd_t *txdp);
+
+vxge_hal_status_e
+__hal_fifo_txdl_align_alloc_map(
+    __hal_fifo_t *fifo,
+    vxge_hal_fifo_txd_t *txdp);
+
+#endif
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_FIFO_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-ifmsg.c b/sys/dev/vxge/vxgehal/vxgehal-ifmsg.c
new file mode 100644
index 000000000000..1bcdbf2a3d61
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-ifmsg.c
@@ -0,0 +1,258 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * __hal_ifmsg_wmsg_process - Process the srpcim to vpath wmsg
+ * @vpath: vpath
+ * @wmsg: wsmsg
+ *
+ * Processes the wmsg and invokes appropriate action
+ */
+void
+__hal_ifmsg_wmsg_process(
+    __hal_virtualpath_t *vpath,
+    u64 wmsg)
+{
+	u32 msg_type;
+	__hal_device_t *hldev = vpath->hldev;
+
+	vxge_assert(vpath);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT
+	    ",wmsg = 0x"VXGE_OS_LLXFMT"", (ptr_t) vpath, wmsg);
+
+	if ((vpath->vp_id != vpath->hldev->first_vp_id) ||
+	    (vpath->hldev->vpath_assignments &
+	    mBIT((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(wmsg)))) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return;
+	}
+
+	msg_type = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(wmsg);
+
+	switch (msg_type) {
+	default:
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_UNKNOWN:
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN:
+		__hal_device_handle_error(hldev,
+		    vpath->vp_id,
+		    VXGE_HAL_EVENT_DEVICE_RESET_START);
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END:
+		vpath->hldev->manager_up = TRUE;
+		__hal_device_handle_error(hldev,
+		    vpath->vp_id,
+		    VXGE_HAL_EVENT_DEVICE_RESET_COMPLETE);
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN:
+		__hal_device_handle_error(hldev,
+		    vpath->vp_id,
+		    VXGE_HAL_EVENT_VPATH_RESET_START);
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END:
+		vpath->hldev->manager_up = TRUE;
+		__hal_device_handle_error(hldev,
+		    vpath->vp_id,
+		    VXGE_HAL_EVENT_VPATH_RESET_COMPLETE);
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP:
+		vpath->hldev->manager_up = TRUE;
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN:
+		vpath->hldev->manager_up = FALSE;
+		break;
+	case VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_ACK:
+		break;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_ifmsg_device_reset_end_poll - Polls for the
+ *			     srpcim to vpath reset end
+ * @hldev: HAL Device
+ * @vp_id: Vpath id
+ *
+ * Polls for the srpcim to vpath reset end
+ */
+vxge_hal_status_e
+__hal_ifmsg_device_reset_end_poll(
+    __hal_device_t *hldev,
+    u32 vp_id)
+{
+	vxge_hal_status_e status;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) hldev, vp_id);
+
+	status = vxge_hal_device_register_poll(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->vpmgmt_reg[vp_id]->srpcim_to_vpath_wmsg, 0,
+	    ~((u64) VXGE_HAL_IFMSG_DEVICE_RESET_END_MSG),
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (status);
+
+}
+
+/*
+ * __hal_ifmsg_wmsg_post - Posts the srpcim to vpath req
+ * @hldev: Hal device
+ * @src_vp_id: Source vpath id
+ * @dest_vp_id: Vpath id, VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_MRPCIM, or
+ *	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST
+ * @msg_type: wsmsg type
+ * @msg_data: wsmsg data
+ *
+ * Posts the req
+ */
+vxge_hal_status_e
+__hal_ifmsg_wmsg_post(
+    __hal_device_t *hldev,
+    u32 src_vp_id,
+    u32 dest_vp_id,
+    u32 msg_type,
+    u32 msg_data)
+{
+	u64 val64;
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status;
+
+	vxge_assert(hldev);
+
+	vp_reg = hldev->vpath_reg[src_vp_id];
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim(
+	    "hldev = 0x"VXGE_OS_STXFMT", src_vp_id = %d, dest_vp_id = %d, "
+	    "msg_type = %d, msg_data = %d", (ptr_t) hldev, src_vp_id,
+	    dest_vp_id, msg_type, msg_data);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_IGNORE_IN_SVC_CHECK |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(msg_type) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DEST(dest_vp_id) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_SRC(src_vp_id) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEQ_NUM(++hldev->ifmsg_seqno) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DATA(msg_data),
+	    &vp_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+
+		vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vp_reg->rts_access_steer_data0);
+
+		status = VXGE_HAL_OK;
+
+	} else {
+		status = VXGE_HAL_FAIL;
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-ifmsg.h b/sys/dev/vxge/vxgehal/vxgehal-ifmsg.h
new file mode 100644
index 000000000000..b9529fe99dbd
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-ifmsg.h
@@ -0,0 +1,83 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_IFMSG_H
+#define	VXGE_HAL_IFMSG_H
+
+__EXTERN_BEGIN_DECLS
+
+
+#define	VXGE_HAL_IFMSG_PRIV_DRIVER_UP_MSG				\
+	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(VXGE_HAL_IFMSG_MSV_OPCODE_UP)
+
+#define	VXGE_HAL_IFMSG_PRIV_DRIVER_DOWN_MSG				\
+	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(VXGE_HAL_IFMSG_MSV_OPCODE_DOWN)
+
+#define	VXGE_HAL_IFMSG_DEVICE_RESET_BEGIN_MSG				\
+	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(			\
+	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN)
+
+#define	VXGE_HAL_IFMSG_DEVICE_RESET_END_MSG				\
+	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(			\
+	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END)
+
+static inline u32
+/* LINTED */
+__hal_ifmsg_is_manager_up(u64 wmsg)
+{
+	return (((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(wmsg) ==
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP) ||
+	    ((u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(wmsg) ==
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END));
+}
+
+vxge_hal_status_e
+__hal_ifmsg_device_reset_end_poll(
+    __hal_device_t *hldev,
+    u32 vp_id);
+
+void
+__hal_ifmsg_wmsg_process(
+    __hal_virtualpath_t *vpath,
+    u64 wmsg);
+
+vxge_hal_status_e
+__hal_ifmsg_wmsg_post(
+    __hal_device_t *hldev,
+    u32 src_vp_id,
+    u32 dest_vp_id,
+    u32 msg_type,
+    u32 msg_data);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_IFMSG_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-legacy-reg.h b/sys/dev/vxge/vxgehal/vxgehal-legacy-reg.h
new file mode 100644
index 000000000000..6e03af356e47
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-legacy-reg.h
@@ -0,0 +1,61 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_LEGACY_REGS_H
+#define	VXGE_HAL_LEGACY_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_legacy_reg_t {
+
+	u8	unused00010[0x00010];
+
+/* 0x00010 */	u64	toc_swapper_fb;
+#define	VXGE_HAL_TOC_SWAPPER_FB_INITIAL_VAL(val)	vBIT(val, 0, 64)
+/* 0x00018 */	u64	pifm_rd_swap_en;
+#define	VXGE_HAL_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val)	vBIT(val, 0, 64)
+/* 0x00020 */	u64	pifm_rd_flip_en;
+#define	VXGE_HAL_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val)	vBIT(val, 0, 64)
+/* 0x00028 */	u64	pifm_wr_swap_en;
+#define	VXGE_HAL_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val)	vBIT(val, 0, 64)
+/* 0x00030 */	u64	pifm_wr_flip_en;
+#define	VXGE_HAL_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val)	vBIT(val, 0, 64)
+/* 0x00038 */	u64	toc_first_pointer;
+#define	VXGE_HAL_TOC_FIRST_POINTER_INITIAL_VAL(val)	vBIT(val, 0, 64)
+/* 0x00040 */	u64	host_access_en;
+#define	VXGE_HAL_HOST_ACCESS_EN_HOST_ACCESS_EN(val)	vBIT(val, 0, 64)
+
+} vxge_hal_legacy_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_LEGACY_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-memrepair-reg.h b/sys/dev/vxge/vxgehal/vxgehal-memrepair-reg.h
new file mode 100644
index 000000000000..213d196e5884
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-memrepair-reg.h
@@ -0,0 +1,45 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_MEMREPAIR_REGS_H
+#define	VXGE_HAL_MEMREPAIR_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_memrepair_reg_t {
+	u64	unused1;
+	u64	unused2;
+} vxge_hal_memrepair_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_MEMREPAIR_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mgmt.c b/sys/dev/vxge/vxgehal/vxgehal-mgmt.c
new file mode 100644
index 000000000000..3e1a25afb0a2
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mgmt.c
@@ -0,0 +1,2111 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * vxge_hal_mgmt_about - Retrieve about info.
+ * @devh: HAL device handle.
+ * @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}.
+ * @size: Pointer to buffer containing the Size of the @buffer_info.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field
+ *
+ * Retrieve information such as PCI device and vendor IDs, board
+ * revision number, HAL version number, etc.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ * VXGE_HAL_FAIL - Failed to retrieve the information.
+ *
+ * See also: vxge_hal_mgmt_about_info_t {}.
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_about(vxge_hal_device_h devh,
+    vxge_hal_mgmt_about_info_t *about_info,
+    u32 *size)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (about_info != NULL) && (size != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "hldev = 0x"VXGE_OS_STXFMT", about_info = 0x"VXGE_OS_STXFMT", "
+	    "size = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, (ptr_t) about_info, (ptr_t) size);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (*size < sizeof(vxge_hal_mgmt_about_info_t)) {
+		*size = sizeof(vxge_hal_mgmt_about_info_t);
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_SPACE);
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+	}
+
+	about_info->vendor = hldev->pci_config_space_bios.vendor_id;
+	about_info->device = hldev->pci_config_space_bios.device_id;
+	about_info->subsys_vendor =
+	    hldev->pci_config_space_bios.subsystem_vendor_id;
+	about_info->subsys_device = hldev->pci_config_space_bios.subsystem_id;
+	about_info->board_rev = hldev->pci_config_space_bios.revision;
+
+	vxge_os_strlcpy(about_info->vendor_name, VXGE_DRIVER_VENDOR,
+	    sizeof(about_info->vendor_name));
+	vxge_os_strlcpy(about_info->chip_name, VXGE_CHIP_FAMILY,
+	    sizeof(about_info->chip_name));
+	vxge_os_strlcpy(about_info->media, VXGE_SUPPORTED_MEDIA_0,
+	    sizeof(about_info->media));
+
+	(void) vxge_os_snprintf(about_info->hal_major,
+	    sizeof(about_info->hal_major), "%d", VXGE_HAL_VERSION_MAJOR);
+	(void) vxge_os_snprintf(about_info->hal_minor,
+	    sizeof(about_info->hal_minor), "%d", VXGE_HAL_VERSION_MINOR);
+	(void) vxge_os_snprintf(about_info->hal_fix,
+	    sizeof(about_info->hal_fix), "%d", VXGE_HAL_VERSION_FIX);
+	(void) vxge_os_snprintf(about_info->hal_build,
+	    sizeof(about_info->hal_build), "%d", VXGE_HAL_VERSION_BUILD);
+
+	(void) vxge_os_snprintf(about_info->ll_major,
+	    sizeof(about_info->ll_major), "%d", XGELL_VERSION_MAJOR);
+	(void) vxge_os_snprintf(about_info->ll_minor,
+	    sizeof(about_info->ll_minor), "%d", XGELL_VERSION_MINOR);
+	(void) vxge_os_snprintf(about_info->ll_fix,
+	    sizeof(about_info->ll_fix), "%d", XGELL_VERSION_FIX);
+	(void) vxge_os_snprintf(about_info->ll_build,
+	    sizeof(about_info->ll_build), "%d", XGELL_VERSION_BUILD);
+
+	*size = sizeof(vxge_hal_mgmt_about_info_t);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_pci_config - Retrieve PCI configuration.
+ * @devh: HAL device handle.
+ * @buffer: Buffer to return pci config.
+ * @size: Pointer to buffer containing the Size of the @buffer.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_pci_config_t) and returns required size in this field
+ *
+ * Get PCI configuration. Permits to retrieve at run-time configuration
+ * values that were used to configure the device at load-time.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size)
+{
+	int i;
+	vxge_hal_pci_config_t *pci_config = (vxge_hal_pci_config_t *) buffer;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (buffer != NULL) && (size != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT", "
+	    "buffer = 0x"VXGE_OS_STXFMT", "
+	    "size = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, (ptr_t) buffer, (ptr_t) size);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (*size < sizeof(vxge_hal_pci_config_t)) {
+		*size = sizeof(vxge_hal_pci_config_t);
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_SPACE);
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+	}
+
+	/* refresh PCI config space */
+	for (i = 0; i < VXGE_HAL_PCI_CONFIG_SPACE_SIZE / 4; i++) {
+		(void) __hal_vpath_pci_read(hldev,
+		    hldev->first_vp_id,
+		    i * 4,
+		    4,
+		    (u32 *) ((void *)&hldev->pci_config_space) + i);
+	}
+
+	vxge_os_memcpy(pci_config, &hldev->pci_config_space,
+	    sizeof(vxge_hal_pci_config_t));
+
+	*size = sizeof(vxge_hal_pci_config_t);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities
+ * @devh: HAL device handle.
+ * @msi_cap: MSI Capabilities
+ *
+ * Return the msi capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_msi_cap_t *msi_cap)
+{
+	u16 msi_control_reg;
+	u32 addr32;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (msi_cap != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "hldev = 0x"VXGE_OS_STXFMT", msi_cap = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, (ptr_t) msi_cap);
+
+	if (hldev->pci_caps.msi_cap_offset == 0) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_os_memzero(msi_cap, sizeof(vxge_hal_mgmt_msi_cap_t));
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.msi_cap_offset +
+	    vxge_offsetof(vxge_hal_msi_capability_le_t, msi_control),
+	    2,
+	    &msi_control_reg);
+
+	if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_ENABLE)
+		msi_cap->enable = 1;
+
+	if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_PVMASK)
+		msi_cap->is_pvm_capable = 1;
+
+	if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_64BIT)
+		msi_cap->is_64bit_addr_capable = 1;
+
+	msi_cap->vectors_allocated =
+	    (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_QSIZE) >> 4;
+
+	msi_cap->max_vectors_capable =
+	    (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_QMASK) >> 1;
+
+	if (msi_cap->is_64bit_addr_capable) {
+		if (msi_cap->is_pvm_capable) {
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_addr_hi),
+			    4, &addr32);
+
+			msi_cap->address = ((u64) addr32) << 32;
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_addr_lo),
+			    4, &addr32);
+
+			msi_cap->address |= (u64) addr32;
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_data),
+			    2, &msi_cap->data);
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_mask),
+			    4, &msi_cap->mask_bits);
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_pending),
+			    4, &msi_cap->pending_bits);
+		} else {
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_no_pvm.msi_addr_hi),
+			    4, &addr32);
+
+			msi_cap->address = ((u64) addr32) << 32;
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_no_pvm.msi_addr_lo),
+			    4, &addr32);
+
+			msi_cap->address |= (u64) addr32;
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_no_pvm.msi_data),
+			    2, &msi_cap->data);
+
+		}
+	} else {
+		if (msi_cap->is_pvm_capable) {
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_addr),
+			    4, &addr32);
+
+			msi_cap->address = (u64) addr32;
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_data),
+			    2, &msi_cap->data);
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_mask),
+			    4, &msi_cap->mask_bits);
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_pending),
+			    4, &msi_cap->pending_bits);
+
+		} else {
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_no_pvm.msi_addr),
+			    4, &addr32);
+
+			msi_cap->address = (u64) addr32;
+
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_no_pvm.msi_data),
+			    2, &msi_cap->data);
+		}
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities
+ * @devh: HAL device handle.
+ * @msi_cap: MSI Capabilities
+ *
+ * Sets the msi capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
+    vxge_hal_mgmt_msi_cap_t *msi_cap)
+{
+	u16 msi_control_reg;
+	u32 addr32;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (msi_cap != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT","
+	    "msi_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) msi_cap);
+
+	if (hldev->pci_caps.msi_cap_offset == 0) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.msi_cap_offset +
+	    vxge_offsetof(vxge_hal_msi_capability_le_t, msi_control),
+	    2, &msi_control_reg);
+
+	if (msi_cap->enable)
+		msi_control_reg |= VXGE_HAL_PCI_MSI_FLAGS_ENABLE;
+	else
+		msi_control_reg &= ~VXGE_HAL_PCI_MSI_FLAGS_ENABLE;
+
+	if (msi_cap->vectors_allocated >
+	    (u32) ((msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_QMASK) >> 1)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	msi_control_reg &= ~VXGE_HAL_PCI_MSI_FLAGS_QSIZE;
+
+	msi_control_reg |= (msi_cap->vectors_allocated & 0x7) << 4;
+
+	if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_64BIT) {
+		if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_PVMASK) {
+
+			addr32 = (u32) (msi_cap->address >> 32);
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_addr_hi), addr32);
+
+			addr32 = (u32) msi_cap->address;
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_addr_lo), addr32);
+
+			vxge_os_pci_write16(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_data), msi_cap->data);
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_mask), msi_cap->mask_bits);
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_pvm.msi_pending), msi_cap->pending_bits);
+		} else {
+			addr32 = (u32) (msi_cap->address >> 32);
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_no_pvm.msi_addr_hi), addr32);
+
+			addr32 = (u32) msi_cap->address;
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_no_pvm.msi_addr_lo), addr32);
+
+			vxge_os_pci_write16(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma64_no_pvm.msi_data), msi_cap->data);
+
+		}
+	} else {
+		if (msi_control_reg & VXGE_HAL_PCI_MSI_FLAGS_PVMASK) {
+
+			addr32 = (u32) msi_cap->address;
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_addr), addr32);
+
+			vxge_os_pci_write16(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_data), msi_cap->data);
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_mask), msi_cap->mask_bits);
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_pvm.msi_pending), msi_cap->pending_bits);
+
+		} else {
+			addr32 = (u32) msi_cap->address;
+
+			vxge_os_pci_write32(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_no_pvm.msi_addr), addr32);
+
+			vxge_os_pci_write16(hldev->header.pdev,
+			    hldev->header.cfgh,
+			    hldev->pci_caps.msi_cap_offset +
+			    vxge_offsetof(vxge_hal_msi_capability_le_t,
+			    au.ma32_no_pvm.msi_data), msi_cap->data);
+		}
+	}
+
+	vxge_os_pci_write16(hldev->header.pdev, hldev->header.cfgh,
+	    hldev->pci_caps.msi_cap_offset +
+	    vxge_offsetof(vxge_hal_msi_capability_le_t, msi_control),
+	    msi_control_reg);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities
+ * @devh: HAL device handle.
+ * @msix_cap: MSIX Capabilities
+ *
+ * Return the msix capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_msix_cap_t *msix_cap)
+{
+	u16 msix_control_reg;
+	u32 msix_offset;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (msix_cap != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "hldev = 0x"VXGE_OS_STXFMT", msix_cap = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, (ptr_t) msix_cap);
+
+	if (hldev->pci_caps.msix_cap_offset == 0) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_os_memzero(msix_cap, sizeof(vxge_hal_mgmt_msix_cap_t));
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.msix_cap_offset +
+	    vxge_offsetof(vxge_hal_msix_capability_le_t, msix_control),
+	    2, &msix_control_reg);
+
+	if (msix_control_reg & VXGE_HAL_PCI_MSIX_FLAGS_ENABLE)
+		msix_cap->enable = 1;
+
+	if (msix_control_reg & VXGE_HAL_PCI_MSIX_FLAGS_MASK)
+		msix_cap->mask_all_vect = 1;
+
+	msix_cap->table_size =
+	    (msix_control_reg & VXGE_HAL_PCI_MSIX_FLAGS_TSIZE) + 1;
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.msix_cap_offset +
+	    vxge_offsetof(vxge_hal_msix_capability_le_t, table_offset),
+	    4, &msix_offset);
+
+	msix_cap->table_offset =
+	    (msix_offset & VXGE_HAL_PCI_MSIX_TABLE_OFFSET) >> 3;
+
+	msix_cap->table_bir = msix_offset & VXGE_HAL_PCI_MSIX_TABLE_BIR;
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.msix_cap_offset +
+	    vxge_offsetof(vxge_hal_msix_capability_le_t, pba_offset),
+	    4, &msix_offset);
+
+	msix_cap->pba_offset =
+	    (msix_offset & VXGE_HAL_PCI_MSIX_PBA_OFFSET) >> 3;
+
+	msix_cap->pba_bir = msix_offset & VXGE_HAL_PCI_MSIX_PBA_BIR;
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities
+ * @devh: HAL device handle.
+ * @pm_cap: pm Capabilities
+ *
+ * Return the pm capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_pm_cap_t *pm_cap)
+{
+	u16 pm_cap_reg;
+	u16 pm_control_reg;
+	u8 pm_ppb_ext;
+	u8 pm_data_reg;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (pm_cap != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT", "
+	    "pm_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) pm_cap);
+
+	if (hldev->pci_caps.pm_cap_offset == 0) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_os_memzero(pm_cap, sizeof(vxge_hal_mgmt_pm_cap_t));
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.pm_cap_offset +
+	    vxge_offsetof(vxge_hal_pm_capability_le_t, capabilities_reg),
+	    2, &pm_cap_reg);
+
+	pm_cap->pm_cap_ver =
+	    (u32) (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_VER_MASK);
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_CLOCK)
+		pm_cap->pm_cap_pme_clock = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_AUX_POWER)
+		pm_cap->pm_cap_aux_power = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_DSI)
+		pm_cap->pm_cap_dsi = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_AUX_CURRENT)
+		pm_cap->pm_cap_aux_current = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_D1)
+		pm_cap->pm_cap_cap_d0 = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_D2)
+		pm_cap->pm_cap_cap_d1 = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D0)
+		pm_cap->pm_cap_pme_d0 = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D1)
+		pm_cap->pm_cap_pme_d1 = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D2)
+		pm_cap->pm_cap_pme_d2 = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D3_HOT)
+		pm_cap->pm_cap_pme_d3_hot = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CAP_PME_D3_COLD)
+		pm_cap->pm_cap_pme_d3_cold = 1;
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.pm_cap_offset +
+	    vxge_offsetof(vxge_hal_pm_capability_le_t, pm_ctrl),
+	    2, &pm_control_reg);
+
+	pm_cap->pm_ctrl_state =
+	    pm_control_reg & VXGE_HAL_PCI_PM_CTRL_STATE_MASK;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET)
+		pm_cap->pm_ctrl_no_soft_reset = 1;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CTRL_PME_ENABLE)
+		pm_cap->pm_ctrl_pme_enable = 1;
+
+	pm_cap->pm_ctrl_pme_data_sel =
+	    (u32) (pm_control_reg & VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK) >> 10;
+
+	pm_cap->pm_ctrl_pme_data_scale =
+	    (u32) (pm_control_reg & VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK) >> 13;
+
+	if (pm_cap_reg & VXGE_HAL_PCI_PM_CTRL_PME_STATUS)
+		pm_cap->pm_ctrl_pme_status = 1;
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.pm_cap_offset +
+	    vxge_offsetof(vxge_hal_pm_capability_le_t, pm_ctrl),
+	    1, &pm_ppb_ext);
+
+	if (pm_ppb_ext & VXGE_HAL_PCI_PM_PPB_B2_B3)
+		pm_cap->pm_ppb_ext_b2_b3 = 1;
+
+	if (pm_ppb_ext & VXGE_HAL_PCI_PM_BPCC_ENABLE)
+		pm_cap->pm_ppb_ext_ecc_en = 1;
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.pm_cap_offset +
+	    vxge_offsetof(vxge_hal_pm_capability_le_t, pm_data_reg),
+	    1, &pm_data_reg);
+
+	pm_cap->pm_data_reg = (u32) pm_data_reg;
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities
+ * @devh: HAL device handle.
+ * @sid_cap: Slot Id Capabilities
+ *
+ * Return the Slot Id capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_mgmt_sid_cap_t *sid_cap)
+{
+	u8 chasis_num_reg;
+	u8 slot_num_reg;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (sid_cap != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT
+	    ", sid_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) sid_cap);
+
+	if (hldev->pci_caps.sid_cap_offset == 0) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_os_memzero(sid_cap, sizeof(vxge_hal_mgmt_sid_cap_t));
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.sid_cap_offset +
+	    vxge_offsetof(vxge_hal_sid_capability_le_t, sid_esr),
+	    1, &slot_num_reg);
+
+	sid_cap->sid_number_of_slots =
+	    (u32) (slot_num_reg & VXGE_HAL_PCI_SID_ESR_NSLOTS);
+
+	if (slot_num_reg & VXGE_HAL_PCI_SID_ESR_FIC)
+		sid_cap->sid_number_of_slots = 1;
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_caps.sid_cap_offset +
+	    vxge_offsetof(vxge_hal_sid_capability_le_t, sid_chasis_nr),
+	    1, &chasis_num_reg);
+
+	sid_cap->sid_chasis_number = (u32) chasis_num_reg;
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities
+ * @devh: HAL device handle.
+ * @err_cap: PCI-E Extended Error Capabilities
+ *
+ * Return the PCI-E Extended Error capabilities
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
+    vxge_hal_pci_err_cap_t *err_cap)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (err_cap != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device("hldev = 0x"VXGE_OS_STXFMT
+	    ",sid_cap = 0x"VXGE_OS_STXFMT, (ptr_t) hldev, (ptr_t) err_cap);
+
+	if (hldev->pci_e_ext_caps.err_cap_offset == 0) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_os_memzero(err_cap, sizeof(vxge_hal_pci_err_cap_t));
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_header),
+	    4,
+	    &err_cap->pci_err_header);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_uncor_status),
+	    4,
+	    &err_cap->pci_err_uncor_status);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_uncor_mask),
+	    4,
+	    &err_cap->pci_err_uncor_mask);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_uncor_server),
+	    4,
+	    &err_cap->pci_err_uncor_server);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_cor_status),
+	    4,
+	    &err_cap->pci_err_cor_status);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_cap),
+	    4,
+	    &err_cap->pci_err_cap);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, err_header_log),
+	    4,
+	    &err_cap->err_header_log);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_command),
+	    4,
+	    &err_cap->pci_err_root_command);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_status),
+	    4,
+	    &err_cap->pci_err_root_status);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_cor_src),
+	    4,
+	    &err_cap->pci_err_root_cor_src);
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    hldev->pci_e_ext_caps.err_cap_offset +
+	    vxge_offsetof(vxge_hal_err_capability_t, pci_err_root_src),
+	    4,
+	    &err_cap->pci_err_root_src);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_driver_config - Retrieve driver configuration.
+ * @drv_config: Device configuration, see vxge_hal_driver_config_t {}.
+ * @size: Pointer to buffer containing the Size of the @drv_config.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_driver_config_t) and returns required size in this field
+ *
+ * Get driver configuration. Permits to retrieve at run-time configuration
+ * values that were used to configure the device at load-time.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ * See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config().
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size)
+{
+
+	vxge_assert((drv_config != NULL) && (size != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "drv_config = 0x"VXGE_OS_STXFMT", size = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) drv_config, (ptr_t) size);
+
+	if (g_vxge_hal_driver == NULL) {
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED);
+		return (VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED);
+	}
+
+	if (*size < sizeof(vxge_hal_driver_config_t)) {
+		*size = sizeof(vxge_hal_driver_config_t);
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_SPACE);
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+	}
+
+	vxge_os_memcpy(drv_config, &g_vxge_hal_driver->config,
+	    sizeof(vxge_hal_driver_config_t));
+
+	*size = sizeof(vxge_hal_driver_config_t);
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * vxge_hal_mgmt_device_config - Retrieve device configuration.
+ * @devh: HAL device handle.
+ * @dev_config: Device configuration, see vxge_hal_device_config_t {}.
+ * @size: Pointer to buffer containing the Size of the @dev_config.
+ * HAL will return an error if the size is smaller than
+ * sizeof(vxge_hal_device_config_t) and returns required size in this field
+ *
+ * Get device configuration. Permits to retrieve at run-time configuration
+ * values that were used to initialize and configure the device.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ * See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config().
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
+    vxge_hal_device_config_t *dev_config, u32 *size)
+{
+	vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (dev_config != NULL) && (size != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", dev_config = 0x"VXGE_OS_STXFMT", "
+	    "size = 0x"VXGE_OS_STXFMT, (ptr_t) devh, (ptr_t) dev_config,
+	    (ptr_t) size);
+
+	if (hldev->magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (*size < sizeof(vxge_hal_device_config_t)) {
+		*size = sizeof(vxge_hal_device_config_t);
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_SPACE);
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+	}
+
+	vxge_os_memcpy(dev_config, &hldev->config,
+	    sizeof(vxge_hal_device_config_t));
+
+	*size = sizeof(vxge_hal_device_config_t);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified
+ * offset.
+ * @devh: HAL device handle.
+ * @offset: Offset in the 256 byte PCI configuration space.
+ * @value_bits: 8, 16, or 32 (bits) to read.
+ * @value: Value returned by HAL.
+ *
+ * Read PCI configuration, given device and offset in the PCI space.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ * VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid
+ * values(8/16/32).
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
+    int value_bits, u32 *value)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (value != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", offset = %d, value_bits = %d, "
+	    "value = 0x"VXGE_OS_STXFMT, (ptr_t) devh, offset,
+	    value_bits, (ptr_t) value);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (offset > sizeof(vxge_hal_pci_config_t) - value_bits / 8) {
+		vxge_hal_trace_log_device("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_OFFSET);
+	}
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    offset,
+	    value_bits / 8,
+	    value);
+
+	vxge_hal_trace_log_device("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_reg_read - Read X3100 register.
+ * @devh: HAL device handle.
+ * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
+ * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
+ *		ignored for others
+ * @offset: Register offset in the register space qualified by the type and
+ *		index.
+ * @value: Register value. Returned by HAL.
+ * Read X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
+ * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
+    vxge_hal_mgmt_reg_type_e type,
+    u32 vp_id,
+    u32 offset,
+    u64 *value)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (value != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", type = %d, "
+	    "vp_id = %d, offset = %d, value = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, type, vp_id, offset, (ptr_t) value);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	switch (type) {
+	case vxge_hal_mgmt_reg_type_legacy:
+		if (offset > sizeof(vxge_hal_legacy_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->legacy_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_toc:
+		if (offset > sizeof(vxge_hal_toc_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->toc_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_common:
+		if (offset > sizeof(vxge_hal_common_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->common_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_memrepair:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_memrepair_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->memrepair_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_pcicfgmgmt:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (vp_id > VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_pcicfgmgmt_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->pcicfgmgmt_reg[vp_id]) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_mrpcim:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_mrpcim_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->mrpcim_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_srpcim:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (vp_id > VXGE_HAL_TITAN_SRPCIM_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_srpcim_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->srpcim_reg[vp_id]) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_vpmgmt:
+		if ((vp_id > VXGE_HAL_TITAN_VPMGMT_REG_SPACES - 1) ||
+		    (!(hldev->vpath_assignments & mBIT(vp_id)))) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_vpmgmt_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->vpmgmt_reg[vp_id]) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_vpath:
+		if ((vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) ||
+		    (!(hldev->vpath_assignments & mBIT(vp_id)))) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_vpath_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (void *)(((ptr_t) hldev->vpath_reg[vp_id]) + offset));
+		break;
+	default:
+		status = VXGE_HAL_ERR_INVALID_TYPE;
+		break;
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mgmt_reg_Write - Write X3100 register.
+ * @devh: HAL device handle.
+ * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
+ * @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
+ *		ignored for others
+ * @offset: Register offset in the register space qualified by the type and
+ *		index.
+ * @value: Register value to be written.
+ * Write X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
+ * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
+    vxge_hal_mgmt_reg_type_e type,
+    u32 vp_id,
+    u32 offset,
+    u64 value)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+		"devh = 0x"VXGE_OS_STXFMT", type = %d, "
+	    "index = %d, offset = %d, value = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, type, vp_id, offset, (ptr_t) value);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	switch (type) {
+	case vxge_hal_mgmt_reg_type_legacy:
+		if (offset > sizeof(vxge_hal_legacy_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->legacy_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_toc:
+		if (offset > sizeof(vxge_hal_toc_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->toc_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_common:
+		if (offset > sizeof(vxge_hal_common_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->common_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_memrepair:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_memrepair_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->memrepair_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_pcicfgmgmt:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (vp_id > VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_pcicfgmgmt_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->pcicfgmgmt_reg[vp_id]) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_mrpcim:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_mrpcim_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->mrpcim_reg) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_srpcim:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+		if (vp_id > VXGE_HAL_TITAN_SRPCIM_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_srpcim_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->srpcim_reg[vp_id]) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_vpmgmt:
+		if ((vp_id > VXGE_HAL_TITAN_VPMGMT_REG_SPACES - 1) ||
+		    (!(hldev->vpath_assignments & mBIT(vp_id)))) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_vpmgmt_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->vpmgmt_reg[vp_id]) + offset));
+		break;
+	case vxge_hal_mgmt_reg_type_vpath:
+		if ((vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) ||
+		    (!(hldev->vpath_assignments & mBIT(vp_id)))) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+		if (offset > sizeof(vxge_hal_vpath_reg_t) - 8) {
+			status = VXGE_HAL_ERR_INVALID_OFFSET;
+			break;
+		}
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    value,
+		    (void *)(((ptr_t) hldev->vpath_reg[vp_id]) + offset));
+		break;
+	default:
+		status = VXGE_HAL_ERR_INVALID_TYPE;
+		break;
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset
+ *                           from bar0.
+ * @devh: HAL device handle.
+ * @offset: Register offset from bar0
+ * @value: Register value. Returned by HAL.
+ * Read X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
+    u32 offset,
+    u64 *value)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", offset = %d, value = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, offset, (ptr_t) value);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (((ptr_t) hldev->header.bar0 + offset) >
+	    ((ptr_t) hldev->vpath_reg[VXGE_HAL_MAX_VIRTUAL_PATHS - 1] +
+	    sizeof(vxge_hal_vpath_reg_t) - 8)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_OFFSET);
+		return (VXGE_HAL_ERR_INVALID_OFFSET);
+	}
+
+	*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (void *)(((ptr_t) hldev->header.bar0) + offset));
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset
+ *                           from bar1.
+ * @devh: HAL device handle.
+ * @offset: Register offset from bar1
+ * @value: Register value. Returned by HAL.
+ * Read X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
+    u32 offset,
+    u64 *value)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", offset = %d, value = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, offset, (ptr_t) value);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	*value = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (void *)(((ptr_t) hldev->header.bar1) + offset));
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset
+ *			    from bar0.
+ * @devh: HAL device handle.
+ * @offset: Register offset from bar0
+ * @value: Register value to be written.
+ * Write X3100 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
+    u32 offset,
+    u64 value)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", offset = %d, value = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, offset, (ptr_t) value);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+	if (((ptr_t) hldev->header.bar0 + offset) >
+	    ((ptr_t) hldev->vpath_reg[VXGE_HAL_MAX_VIRTUAL_PATHS - 1] +
+	    sizeof(vxge_hal_vpath_reg_t) - 8)) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_OFFSET);
+		return (VXGE_HAL_ERR_INVALID_OFFSET);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    value,
+	    (void *)(((ptr_t) hldev->header.bar0) + offset));
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mgmt_register_config - Retrieve register configuration.
+ * @devh: HAL device handle.
+ * @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
+ * @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
+ *		ignored for others
+ * @config: Device configuration, see vxge_hal_device_config_t {}.
+ * @size: Pointer to buffer containing the Size of the @reg_config.
+ * HAL will return an error if the size is smaller than
+ * requested register space and returns required size in this field
+ *
+ * Get register configuration. Permits to retrieve register values.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
+ * VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
+    vxge_hal_mgmt_reg_type_e type, u32 vp_id, u8 *config, u32 *size)
+{
+	u32 offset;
+	u64 *reg_config = (u64 *) ((void *)config);
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (reg_config != NULL) && (size != NULL));
+
+	vxge_hal_trace_log_device("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_device(
+	    "devh = 0x"VXGE_OS_STXFMT", type = %d, index = %d, "
+	    "reg_config = 0x"VXGE_OS_STXFMT", size = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, type, vp_id, (ptr_t) reg_config, (ptr_t) size);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	switch (type) {
+	case vxge_hal_mgmt_reg_type_legacy:
+		if (*size < sizeof(vxge_hal_legacy_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_legacy_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_legacy_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->legacy_reg) + offset));
+		}
+		*size = sizeof(vxge_hal_legacy_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_toc:
+		if (*size < sizeof(vxge_hal_toc_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_toc_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_toc_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->toc_reg) + offset));
+		}
+		*size = sizeof(vxge_hal_toc_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_common:
+		if (*size < sizeof(vxge_hal_common_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_common_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_common_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->common_reg) + offset));
+		}
+		*size = sizeof(vxge_hal_common_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_memrepair:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+
+		if (*size < sizeof(vxge_hal_memrepair_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_memrepair_reg_t);
+			break;
+		}
+
+		for (offset = 0;
+		    offset < sizeof(vxge_hal_memrepair_reg_t); offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->memrepair_reg) + offset));
+		}
+		*size = sizeof(vxge_hal_memrepair_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_pcicfgmgmt:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+
+		if (vp_id > VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+
+		if (*size < sizeof(vxge_hal_pcicfgmgmt_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_pcicfgmgmt_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_pcicfgmgmt_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->pcicfgmgmt_reg[vp_id]) + offset));
+		}
+		*size = sizeof(vxge_hal_pcicfgmgmt_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_mrpcim:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+
+		if (*size < sizeof(vxge_hal_mrpcim_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_mrpcim_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_mrpcim_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->mrpcim_reg) + offset));
+		}
+		*size = sizeof(vxge_hal_mrpcim_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_srpcim:
+		if (!(hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+			status = VXGE_HAL_ERR_PRIVILAGED_OPEARATION;
+			break;
+		}
+
+		if (vp_id > VXGE_HAL_TITAN_SRPCIM_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+
+		if (*size < sizeof(vxge_hal_srpcim_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_srpcim_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_srpcim_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->srpcim_reg[vp_id]) + offset));
+		}
+		*size = sizeof(vxge_hal_srpcim_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_vpmgmt:
+		if ((vp_id > VXGE_HAL_TITAN_VPMGMT_REG_SPACES - 1) ||
+		    (!(hldev->vpath_assignments & mBIT(vp_id)))) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+
+		if (*size < sizeof(vxge_hal_vpmgmt_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_vpmgmt_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_vpmgmt_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->vpmgmt_reg[vp_id]) + offset));
+		}
+		*size = sizeof(vxge_hal_vpmgmt_reg_t);
+		break;
+
+	case vxge_hal_mgmt_reg_type_vpath:
+		if ((vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) ||
+		    (!(hldev->vpath_assignments & mBIT(vp_id)))) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+
+		if (vp_id > VXGE_HAL_TITAN_VPATH_REG_SPACES - 1) {
+			status = VXGE_HAL_ERR_INVALID_INDEX;
+			break;
+		}
+
+		if (*size < sizeof(vxge_hal_vpath_reg_t)) {
+			status = VXGE_HAL_ERR_OUT_OF_SPACE;
+			*size = sizeof(vxge_hal_vpath_reg_t);
+			break;
+		}
+
+		for (offset = 0; offset < sizeof(vxge_hal_vpath_reg_t);
+		    offset += 8) {
+			*reg_config++ = vxge_os_pio_mem_read64(
+			    hldev->header.pdev,
+			    hldev->header.regh0,
+			    (void *)(((ptr_t) hldev->vpath_reg[vp_id]) + offset));
+		}
+		*size = sizeof(vxge_hal_vpath_reg_t);
+		break;
+
+	default:
+		status = VXGE_HAL_ERR_INVALID_TYPE;
+		break;
+	}
+
+	vxge_hal_trace_log_device("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port
+ * @hldev: HAL device handle.
+ * @port: Port number
+ *
+ * This routine only gets the temperature for XFP modules. Also, updating of the
+ * NVRAM can sometimes fail and so the reading we might get may not be uptodate.
+ */
+u32
+vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port)
+{
+	u16 val1, val2, count = 0;
+	u32 actual;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT", port = %d",
+	    (ptr_t) devh, port);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	val1 = VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_256_BYTES;
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL,
+	    &val1);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	/* Now wait for the transfer to complete */
+	do {
+		vxge_os_mdelay(50);	/* wait 50 milliseonds */
+
+		status = __hal_mrpcim_mdio_access(devh, port,
+		    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+		    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+		    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL,
+		    &val1);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		if (count++ > 10) {
+			/* waited 500 ms which should be plenty of time */
+			break;
+		}
+
+	} while ((val1 &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK)
+	    == VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_PROGRESS);
+
+	if ((val1 &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK) ==
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_FAILED) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (VXGE_HAL_FAIL);
+	}
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_1,
+	    &val1);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_2,
+	    &val2);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	actual = ((val1 << 8) | val2);
+
+	if (actual >= 32768)
+		actual = actual - 65536;
+
+	actual = actual / 256;
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (actual);
+
+}
+
+/*
+ * vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback
+ * @devh: HAL device handle.
+ * @port: Port number
+ * @enable:Boolean set to 1 to enable and 0 to disable.
+ *
+ * Enable or disable PMA loopback.
+ * Return value:
+ * 0 on success.
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable)
+{
+	u16 val;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", port = %d, enable = %d",
+	    (ptr_t) devh, port, enable);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1,
+	    &val);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (enable)
+		val |=
+		    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK;
+	else
+		val &=
+		    ~VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK;
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1,
+	    &val);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback
+ * @devh: HAL device handle.
+ * @port: Port number
+ * @enable:Boolean set to 1 to enable and 0 to disable.
+ *
+ * Enable or disable xgmii loopback.
+ * Return value:
+ * 0 on success.
+ */
+vxge_hal_status_e
+vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", port = %d, enable = %d",
+	    (ptr_t) devh, port, enable);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xmac_cfg_port[port]);
+	if (enable)
+		val64 |= VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK;
+	else
+		val64 &= ~VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->xmac_cfg_port[port]);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mgmtaux.c b/sys/dev/vxge/vxgehal/vxgehal-mgmtaux.c
new file mode 100644
index 000000000000..e294e7eb127d
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mgmtaux.c
@@ -0,0 +1,3184 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+#define	VXGE_HAL_AUX_SEPA		' '
+
+#define	__hal_aux_snprintf(retbuf, bufsize, fmt, key, value, retsize) \
+	if (bufsize <= 0) \
+		return (VXGE_HAL_ERR_OUT_OF_SPACE); \
+	retsize = vxge_os_snprintf(retbuf, bufsize, fmt, key, \
+	    VXGE_HAL_AUX_SEPA, value); \
+	if (retsize < 0 || retsize >= bufsize) \
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+
+#define	__HAL_AUX_ENTRY_DECLARE(size, buf) \
+	int entrysize = 0, leftsize = size; \
+	char *ptr; ptr = buf;
+
+#define	__HAL_AUX_ENTRY(key, value, fmt) \
+	__hal_aux_snprintf(ptr, leftsize, "%s%c"fmt"\n", key, value, entrysize)\
+	ptr += entrysize; leftsize -= entrysize;
+
+#define	__HAL_AUX_CONFIG_ENTRY(key, value, fmt) \
+	if (value == VXGE_HAL_USE_FLASH_DEFAULT) { \
+		__HAL_AUX_ENTRY(key, "FLASH DEFAULT", "%s"); \
+	} else { \
+		__HAL_AUX_ENTRY(key, value, fmt); \
+	}
+
+#define	__HAL_AUX_ENTRY_END(bufsize, retsize) \
+	*retsize = bufsize - leftsize;
+
+#define	__hal_aux_pci_link_info(name, index, var) {	\
+		__HAL_AUX_ENTRY(name,			\
+		    (u64)pcim.link_info[index].var, "%llu") \
+	}
+
+#define	__hal_aux_pci_aggr_info(name, index, var) { \
+		__HAL_AUX_ENTRY(name,				\
+		    (u64)pcim.aggr_info[index].var, "%llu") \
+	}
+
+/*
+ * vxge_hal_aux_about_read - Retrieve and format about info.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Retrieve about info (using vxge_hal_mgmt_about()) and sprintf it
+ * into the provided @retbuf.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ * VXGE_HAL_FAIL - Failed to retrieve the information.
+ *
+ * See also: vxge_hal_mgmt_about(), vxge_hal_aux_device_dump().
+ */
+vxge_hal_status_e
+vxge_hal_aux_about_read(vxge_hal_device_h devh, int bufsize,
+    char *retbuf, int *retsize)
+{
+	u32 size = sizeof(vxge_hal_mgmt_about_info_t);
+	vxge_hal_status_e status;
+	vxge_hal_mgmt_about_info_t about_info;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	status = vxge_hal_mgmt_about(devh, &about_info, &size);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	__HAL_AUX_ENTRY("vendor", about_info.vendor, "0x%x");
+	__HAL_AUX_ENTRY("device", about_info.device, "0x%x");
+	__HAL_AUX_ENTRY("subsys_vendor", about_info.subsys_vendor, "0x%x");
+	__HAL_AUX_ENTRY("subsys_device", about_info.subsys_device, "0x%x");
+	__HAL_AUX_ENTRY("board_rev", about_info.board_rev, "0x%x");
+	__HAL_AUX_ENTRY("vendor_name", about_info.vendor_name, "%s");
+	__HAL_AUX_ENTRY("chip_name", about_info.chip_name, "%s");
+	__HAL_AUX_ENTRY("media", about_info.media, "%s");
+	__HAL_AUX_ENTRY("hal_major", about_info.hal_major, "%s");
+	__HAL_AUX_ENTRY("hal_minor", about_info.hal_minor, "%s");
+	__HAL_AUX_ENTRY("hal_fix", about_info.hal_fix, "%s");
+	__HAL_AUX_ENTRY("hal_build", about_info.hal_build, "%s");
+	__HAL_AUX_ENTRY("ll_major", about_info.ll_major, "%s");
+	__HAL_AUX_ENTRY("ll_minor", about_info.ll_minor, "%s");
+	__HAL_AUX_ENTRY("ll_fix", about_info.ll_fix, "%s");
+	__HAL_AUX_ENTRY("ll_build", about_info.ll_build, "%s");
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_driver_config_read - Read Driver configuration.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read driver configuration,
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ *
+ * See also: vxge_hal_aux_device_config_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_driver_config_read(int bufsize, char *retbuf, int *retsize)
+{
+	u32 size = sizeof(vxge_hal_driver_config_t);
+	vxge_hal_status_e status;
+	vxge_hal_driver_config_t drv_config;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	status = vxge_hal_mgmt_driver_config(&drv_config, &size);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	__HAL_AUX_ENTRY("Debug Level",
+	    g_vxge_hal_driver->debug_level, "%u");
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_pci_config_read - Retrieve and format PCI Configuration
+ * info.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Retrieve about info (using vxge_hal_mgmt_pci_config()) and sprintf it
+ * into the provided @retbuf.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ *
+ * See also: vxge_hal_mgmt_pci_config(), vxge_hal_aux_device_dump().
+ */
+vxge_hal_status_e
+vxge_hal_aux_pci_config_read(
+    vxge_hal_device_h devh,
+    int bufsize,
+    char *retbuf,
+    int *retsize)
+{
+	u8 cap_id;
+	u16 ext_cap_id;
+	u16 next_ptr;
+	u32 size = sizeof(vxge_hal_pci_config_t);
+	vxge_hal_status_e status;
+	vxge_hal_pci_config_t *pci_config =
+	&((__hal_device_t *) devh)->pci_config_space;
+	vxge_hal_mgmt_pm_cap_t pm_cap;
+	vxge_hal_mgmt_sid_cap_t sid_cap;
+	vxge_hal_mgmt_msi_cap_t msi_cap;
+	vxge_hal_mgmt_msix_cap_t msix_cap;
+	vxge_hal_pci_err_cap_t err_cap;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	status = vxge_hal_mgmt_pci_config(devh, (u8 *) pci_config, &size);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	__HAL_AUX_ENTRY("vendor_id", pci_config->vendor_id, "0x%04X");
+	__HAL_AUX_ENTRY("device_id", pci_config->device_id, "0x%04X");
+	__HAL_AUX_ENTRY("command", pci_config->command, "0x%04X");
+	__HAL_AUX_ENTRY("status", pci_config->status, "0x%04X");
+	__HAL_AUX_ENTRY("revision", pci_config->revision, "0x%02X");
+	__HAL_AUX_ENTRY("pciClass1", pci_config->pciClass[0], "0x%02X");
+	__HAL_AUX_ENTRY("pciClass2", pci_config->pciClass[1], "0x%02X");
+	__HAL_AUX_ENTRY("pciClass3", pci_config->pciClass[2], "0x%02X");
+	__HAL_AUX_ENTRY("cache_line_size",
+	    pci_config->cache_line_size, "0x%02X");
+	__HAL_AUX_ENTRY("header_type", pci_config->header_type, "0x%02X");
+	__HAL_AUX_ENTRY("bist", pci_config->bist, "0x%02X");
+	__HAL_AUX_ENTRY("base_addr0_lo", pci_config->base_addr0_lo, "0x%08X");
+	__HAL_AUX_ENTRY("base_addr0_hi", pci_config->base_addr0_hi, "0x%08X");
+	__HAL_AUX_ENTRY("base_addr1_lo", pci_config->base_addr1_lo, "0x%08X");
+	__HAL_AUX_ENTRY("base_addr1_hi", pci_config->base_addr1_hi, "0x%08X");
+	__HAL_AUX_ENTRY("not_Implemented1",
+	    pci_config->not_Implemented1, "0x%08X");
+	__HAL_AUX_ENTRY("not_Implemented2", pci_config->not_Implemented2,
+	    "0x%08X");
+	__HAL_AUX_ENTRY("cardbus_cis_pointer", pci_config->cardbus_cis_pointer,
+	    "0x%08X");
+	__HAL_AUX_ENTRY("subsystem_vendor_id", pci_config->subsystem_vendor_id,
+	    "0x%04X");
+	__HAL_AUX_ENTRY("subsystem_id", pci_config->subsystem_id, "0x%04X");
+	__HAL_AUX_ENTRY("rom_base", pci_config->rom_base, "0x%08X");
+	__HAL_AUX_ENTRY("capabilities_pointer",
+	    pci_config->capabilities_pointer, "0x%02X");
+	__HAL_AUX_ENTRY("interrupt_line", pci_config->interrupt_line, "0x%02X");
+	__HAL_AUX_ENTRY("interrupt_pin", pci_config->interrupt_pin, "0x%02X");
+	__HAL_AUX_ENTRY("min_grant", pci_config->min_grant, "0x%02X");
+	__HAL_AUX_ENTRY("max_latency", pci_config->max_latency, "0x%02X");
+
+	next_ptr = pci_config->capabilities_pointer;
+
+	while (next_ptr != 0) {
+
+		cap_id = VXGE_HAL_PCI_CAP_ID((((u8 *) pci_config) + next_ptr));
+
+		switch (cap_id) {
+
+		case VXGE_HAL_PCI_CAP_ID_PM:
+			status = vxge_hal_mgmt_pm_capabilities_get(devh,
+			    &pm_cap);
+			if (status != VXGE_HAL_OK)
+				return (status);
+
+			__HAL_AUX_ENTRY("PM Capability",
+			    cap_id, "0x%02X");
+			__HAL_AUX_ENTRY("pm_cap_ver",
+			    pm_cap.pm_cap_ver, "%u");
+			__HAL_AUX_ENTRY("pm_cap_pme_clock",
+			    pm_cap.pm_cap_pme_clock, "%u");
+			__HAL_AUX_ENTRY("pm_cap_aux_power",
+			    pm_cap.pm_cap_aux_power, "%u");
+			__HAL_AUX_ENTRY("pm_cap_dsi",
+			    pm_cap.pm_cap_dsi, "%u");
+			__HAL_AUX_ENTRY("pm_cap_aux_current",
+			    pm_cap.pm_cap_aux_current, "%u");
+			__HAL_AUX_ENTRY("pm_cap_cap_d0",
+			    pm_cap.pm_cap_cap_d0, "%u");
+			__HAL_AUX_ENTRY("pm_cap_cap_d1",
+			    pm_cap.pm_cap_cap_d1, "%u");
+			__HAL_AUX_ENTRY("pm_cap_pme_d0",
+			    pm_cap.pm_cap_pme_d0, "%u");
+			__HAL_AUX_ENTRY("pm_cap_pme_d1",
+			    pm_cap.pm_cap_pme_d1, "%u");
+			__HAL_AUX_ENTRY("pm_cap_pme_d2",
+			    pm_cap.pm_cap_pme_d2, "%u");
+			__HAL_AUX_ENTRY("pm_cap_pme_d3_hot",
+			    pm_cap.pm_cap_pme_d3_hot, "%u");
+			__HAL_AUX_ENTRY("pm_cap_pme_d3_cold",
+			    pm_cap.pm_cap_pme_d3_cold, "%u");
+			__HAL_AUX_ENTRY("pm_ctrl_state",
+			    pm_cap.pm_ctrl_state, "%u");
+			__HAL_AUX_ENTRY("pm_ctrl_no_soft_reset",
+			    pm_cap.pm_ctrl_no_soft_reset, "%u");
+			__HAL_AUX_ENTRY("pm_ctrl_pme_enable",
+			    pm_cap.pm_ctrl_pme_enable, "%u");
+			__HAL_AUX_ENTRY("pm_ctrl_pme_data_sel",
+			    pm_cap.pm_ctrl_pme_data_sel, "%u");
+			__HAL_AUX_ENTRY("pm_ctrl_pme_data_scale",
+			    pm_cap.pm_ctrl_pme_data_scale, "%u");
+			__HAL_AUX_ENTRY("pm_ctrl_pme_status",
+			    pm_cap.pm_ctrl_pme_status, "%u");
+			__HAL_AUX_ENTRY("pm_ppb_ext_b2_b3",
+			    pm_cap.pm_ppb_ext_b2_b3, "%u");
+			__HAL_AUX_ENTRY("pm_ppb_ext_ecc_en",
+			    pm_cap.pm_ppb_ext_ecc_en, "%u");
+			__HAL_AUX_ENTRY("pm_data_reg",
+			    pm_cap.pm_data_reg, "%u");
+			break;
+		case VXGE_HAL_PCI_CAP_ID_VPD:
+			break;
+		case VXGE_HAL_PCI_CAP_ID_SLOTID:
+			status = vxge_hal_mgmt_sid_capabilities_get(devh,
+			    &sid_cap);
+			if (status != VXGE_HAL_OK)
+				return (status);
+
+			__HAL_AUX_ENTRY("SID Capability", cap_id, "0x%02X");
+			__HAL_AUX_ENTRY("sid_number_of_slots",
+			    sid_cap.sid_number_of_slots, "%u");
+			__HAL_AUX_ENTRY("sid_first_in_chasis",
+			    sid_cap.sid_first_in_chasis, "%u");
+			__HAL_AUX_ENTRY("sid_chasis_number",
+			    sid_cap.sid_chasis_number, "0x%u");
+			break;
+		case VXGE_HAL_PCI_CAP_ID_MSI:
+			status = vxge_hal_mgmt_msi_capabilities_get(devh,
+			    &msi_cap);
+			if (status != VXGE_HAL_OK)
+				return (status);
+
+			__HAL_AUX_ENTRY("MSI Capability", cap_id, "0x%02X");
+			__HAL_AUX_ENTRY("MSI Enable", msi_cap.enable, "%u");
+			__HAL_AUX_ENTRY("MSI 64bit Address Capable",
+			    msi_cap.is_64bit_addr_capable, "%u");
+			__HAL_AUX_ENTRY("MSI PVM Capable",
+			    msi_cap.is_pvm_capable, "0x%02X");
+			__HAL_AUX_ENTRY("MSI Vectors Allocated",
+			    msi_cap.vectors_allocated, "0x%02X");
+			__HAL_AUX_ENTRY("MSI Max Vectors",
+			    msi_cap.max_vectors_capable, "0x%02X");
+			if (msi_cap.is_64bit_addr_capable) {
+				__HAL_AUX_ENTRY("MSI address",
+				    msi_cap.address, "0x%016llX");
+			} else {
+				__HAL_AUX_ENTRY("MSI address",
+				    msi_cap.address, "0x%08llX");
+			}
+			__HAL_AUX_ENTRY("MSI Data", msi_cap.data, "0x%04X");
+			if (msi_cap.is_pvm_capable) {
+				__HAL_AUX_ENTRY("MSI Mask bits",
+				    msi_cap.mask_bits, "0x%08X");
+				__HAL_AUX_ENTRY("MSI Pending bits",
+				    msi_cap.pending_bits, "0x%08X");
+			}
+			break;
+		case VXGE_HAL_PCI_CAP_ID_VS:
+			break;
+		case VXGE_HAL_PCI_CAP_ID_SHPC:
+			break;
+		case VXGE_HAL_PCI_CAP_ID_PCIE:
+			break;
+		case VXGE_HAL_PCI_CAP_ID_MSIX:
+			status = vxge_hal_mgmt_msix_capabilities_get(devh,
+			    &msix_cap);
+			if (status != VXGE_HAL_OK)
+				return (status);
+
+			__HAL_AUX_ENTRY("MSIX Capability", cap_id, "0x%02X");
+			__HAL_AUX_ENTRY("MSIX Enable", msix_cap.enable, "%u");
+			__HAL_AUX_ENTRY("MSIX Mask All vectors",
+			    msix_cap.mask_all_vect, "%u");
+			__HAL_AUX_ENTRY("MSIX Table Size",
+			    msix_cap.table_size, "%u");
+			__HAL_AUX_ENTRY("MSIX Table Offset",
+			    msix_cap.table_offset, "%u");
+			__HAL_AUX_ENTRY("MSIX Table BIR",
+			    msix_cap.table_bir, "%u");
+			__HAL_AUX_ENTRY("MSIX PBA Offset",
+			    msix_cap.pba_offset, "%u");
+			__HAL_AUX_ENTRY("MSIX PBA BIR", msix_cap.pba_bir, "%u");
+			break;
+		case VXGE_HAL_PCI_CAP_ID_AGP:
+		case VXGE_HAL_PCI_CAP_ID_CHSWP:
+		case VXGE_HAL_PCI_CAP_ID_PCIX:
+		case VXGE_HAL_PCI_CAP_ID_HT:
+		case VXGE_HAL_PCI_CAP_ID_DBGPORT:
+		case VXGE_HAL_PCI_CAP_ID_CPCICSR:
+		case VXGE_HAL_PCI_CAP_ID_PCIBSVID:
+		case VXGE_HAL_PCI_CAP_ID_AGP8X:
+		case VXGE_HAL_PCI_CAP_ID_SECDEV:
+			__HAL_AUX_ENTRY("Unexpected Capability",
+			    cap_id, "0x%02X");
+			break;
+		default:
+			__HAL_AUX_ENTRY("Unknown Capability",
+			    cap_id, "0x%02X");
+			break;
+		}
+
+		next_ptr =
+		    VXGE_HAL_PCI_CAP_NEXT((((u8 *) pci_config) + next_ptr));
+
+	}
+
+	/* CONSTCOND */
+	if (VXGE_HAL_PCI_CONFIG_SPACE_SIZE > 0x100) {
+
+		next_ptr = 0x100;
+
+		while (next_ptr != 0) {
+
+			ext_cap_id = (u16) VXGE_HAL_PCI_EXT_CAP_ID(
+			    *(u32 *)((void *)(((u8 *) pci_config) + next_ptr)));
+
+			switch (ext_cap_id) {
+
+			case VXGE_HAL_PCI_EXT_CAP_ID_ERR:
+				status =
+				    vxge_hal_mgmt_pci_err_capabilities_get(devh,
+				    &err_cap);
+				if (status != VXGE_HAL_OK)
+					return (status);
+
+				__HAL_AUX_ENTRY("pci_err_header",
+				    err_cap.pci_err_header, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_uncor_status",
+				    err_cap.pci_err_uncor_status, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_uncor_mask",
+				    err_cap.pci_err_uncor_mask, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_uncor_server",
+				    err_cap.pci_err_uncor_server, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_cor_status",
+				    err_cap.pci_err_cor_status, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_cap",
+				    err_cap.pci_err_cap, "0x%08X");
+				__HAL_AUX_ENTRY("err_header_log",
+				    err_cap.err_header_log, "%u");
+				__HAL_AUX_ENTRY("pci_err_root_command",
+				    err_cap.pci_err_root_command, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_root_status",
+				    err_cap.pci_err_root_status, "0x%08X");
+				__HAL_AUX_ENTRY("pci_err_root_cor_src",
+				    err_cap.pci_err_root_cor_src, "0x%04X");
+				__HAL_AUX_ENTRY("pci_err_root_src",
+				    err_cap.pci_err_root_src, "0x%04X");
+				break;
+			case VXGE_HAL_PCI_EXT_CAP_ID_VC:
+				break;
+			case VXGE_HAL_PCI_EXT_CAP_ID_DSN:
+				break;
+			case VXGE_HAL_PCI_EXT_CAP_ID_PWR:
+				break;
+			default:
+				__HAL_AUX_ENTRY("Unknown Capability", cap_id,
+				    "0x%02X");
+				break;
+			}
+			next_ptr = (u16) VXGE_HAL_PCI_EXT_CAP_NEXT(
+			    *(u32 *)((void *)(((u8 *) pci_config) + next_ptr)));
+
+		}
+
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_device_config_read - Read device configuration.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device configuration,
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
+ *
+ * See also: vxge_hal_aux_driver_config_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_device_config_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	int i;
+	u32 size = sizeof(vxge_hal_device_config_t);
+	vxge_hal_status_e status;
+	vxge_hal_mac_config_t *mac_config;
+	vxge_hal_device_config_t *dev_config;
+	vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	dev_config = (vxge_hal_device_config_t *) vxge_os_malloc(hldev->pdev,
+	    sizeof(vxge_hal_device_config_t));
+	if (dev_config == NULL) {
+		return (VXGE_HAL_FAIL);
+	}
+
+	status = vxge_hal_mgmt_device_config(devh, dev_config, &size);
+	if (status != VXGE_HAL_OK) {
+		vxge_os_free(hldev->pdev, dev_config,
+		    sizeof(vxge_hal_device_config_t));
+		return (status);
+	}
+
+	__HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Minimum",
+	    dev_config->dma_blockpool_min, "%u");
+	__HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Initial",
+	    dev_config->dma_blockpool_initial, "%u");
+	__HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Increment",
+	    dev_config->dma_blockpool_incr, "%u");
+	__HAL_AUX_CONFIG_ENTRY("DMA Block Pool size-Maximum",
+	    dev_config->dma_blockpool_max, "%u");
+	for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
+		mac_config = &dev_config->mrpcim_config.mac_config;
+		__HAL_AUX_CONFIG_ENTRY("port_id",
+		    mac_config->wire_port_config[i].port_id, "%u");
+		__HAL_AUX_CONFIG_ENTRY("media",
+		    mac_config->wire_port_config[i].media, "%u");
+		__HAL_AUX_CONFIG_ENTRY("mtu",
+		    mac_config->wire_port_config[i].mtu, "%u");
+		__HAL_AUX_CONFIG_ENTRY("autoneg_mode",
+		    mac_config->wire_port_config[i].autoneg_mode, "%u");
+		__HAL_AUX_CONFIG_ENTRY("fixed_use_fsm",
+		    mac_config->wire_port_config[i].fixed_use_fsm, "%u");
+		__HAL_AUX_CONFIG_ENTRY("antp_use_fsm",
+		    mac_config->wire_port_config[i].antp_use_fsm, "%u");
+		__HAL_AUX_CONFIG_ENTRY("anbe_use_fsm",
+		    mac_config->wire_port_config[i].anbe_use_fsm, "%u");
+		__HAL_AUX_CONFIG_ENTRY("link_stability_period",
+		    mac_config->wire_port_config[i].link_stability_period,
+		    "%u");
+		__HAL_AUX_CONFIG_ENTRY("port_stability_period",
+		    mac_config->wire_port_config[i].port_stability_period,
+		    "%u");
+		__HAL_AUX_CONFIG_ENTRY("tmac_en",
+		    mac_config->wire_port_config[i].tmac_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_en",
+		    mac_config->wire_port_config[i].rmac_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("tmac_pad",
+		    mac_config->wire_port_config[i].tmac_pad, "%u");
+		__HAL_AUX_CONFIG_ENTRY("tmac_pad_byte",
+		    mac_config->wire_port_config[i].tmac_pad_byte, "%u");
+		__HAL_AUX_CONFIG_ENTRY("tmac_util_period",
+		    mac_config->wire_port_config[i].tmac_util_period, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_strip_fcs",
+		    mac_config->wire_port_config[i].rmac_strip_fcs, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_prom_en",
+		    mac_config->wire_port_config[i].rmac_prom_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_discard_pfrm",
+		    mac_config->wire_port_config[i].rmac_discard_pfrm, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_util_period",
+		    mac_config->wire_port_config[i].rmac_util_period, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_pause_gen_en",
+		    mac_config->wire_port_config[i].rmac_pause_gen_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_pause_rcv_en",
+		    mac_config->wire_port_config[i].rmac_pause_rcv_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("rmac_pause_time",
+		    mac_config->wire_port_config[i].rmac_pause_time, "%u");
+		__HAL_AUX_CONFIG_ENTRY("limiter_en",
+		    mac_config->wire_port_config[i].limiter_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("max_limit",
+		    mac_config->wire_port_config[i].max_limit, "%u");
+	}
+
+	/* CONSTCOND */
+	__HAL_AUX_CONFIG_ENTRY("port_id",
+	    VXGE_HAL_MAC_SWITCH_PORT, "%u");
+	__HAL_AUX_CONFIG_ENTRY("mtu",
+	    mac_config->switch_port_config.mtu, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_en",
+	    mac_config->switch_port_config.tmac_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_en",
+	    mac_config->switch_port_config.rmac_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_pad",
+	    mac_config->switch_port_config.tmac_pad, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_pad_byte",
+	    mac_config->switch_port_config.tmac_pad_byte, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_util_period",
+	    mac_config->switch_port_config.tmac_util_period, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_strip_fcs",
+	    mac_config->switch_port_config.rmac_strip_fcs, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_prom_en",
+	    mac_config->switch_port_config.rmac_prom_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_discard_pfrm",
+	    mac_config->switch_port_config.rmac_discard_pfrm, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_util_period",
+	    mac_config->switch_port_config.rmac_util_period, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_pause_gen_en",
+	    mac_config->switch_port_config.rmac_pause_gen_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_pause_rcv_en",
+	    mac_config->switch_port_config.rmac_pause_rcv_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rmac_pause_time",
+	    mac_config->switch_port_config.rmac_pause_time, "%u");
+	__HAL_AUX_CONFIG_ENTRY("limiter_en",
+	    mac_config->switch_port_config.limiter_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("max_limit",
+	    mac_config->switch_port_config.max_limit, "%u");
+
+	__HAL_AUX_CONFIG_ENTRY("network_stability_period",
+	    mac_config->network_stability_period, "%u");
+	for (i = 0; i < 16; i++) {
+		__HAL_AUX_CONFIG_ENTRY("mc_pause_threshold[i]",
+		    mac_config->mc_pause_threshold[i], "%u");
+	}
+	__HAL_AUX_CONFIG_ENTRY("tmac_perma_stop_en",
+	    mac_config->tmac_perma_stop_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_tx_switch_dis",
+	    mac_config->tmac_tx_switch_dis, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_lossy_switch_en",
+	    mac_config->tmac_lossy_switch_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_lossy_wire_en",
+	    mac_config->tmac_lossy_wire_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_bcast_to_wire_dis",
+	    mac_config->tmac_bcast_to_wire_dis, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_bcast_to_switch_dis",
+	    mac_config->tmac_bcast_to_switch_dis, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tmac_host_append_fcs_en",
+	    mac_config->tmac_host_append_fcs_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tpa_support_snap_ab_n",
+	    mac_config->tpa_support_snap_ab_n, "%u");
+	__HAL_AUX_CONFIG_ENTRY("tpa_ecc_enable_n",
+	    mac_config->tpa_ecc_enable_n, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_ignore_frame_err",
+	    mac_config->rpa_ignore_frame_err, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_support_snap_ab_n",
+	    mac_config->rpa_support_snap_ab_n, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_search_for_hao",
+	    mac_config->rpa_search_for_hao, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_support_ipv6_mobile_hdrs",
+	    mac_config->rpa_support_ipv6_mobile_hdrs, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_ipv6_stop_searching",
+	    mac_config->rpa_ipv6_stop_searching, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_no_ps_if_unknown",
+	    mac_config->rpa_no_ps_if_unknown, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_search_for_etype",
+	    mac_config->rpa_search_for_etype, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_l4_comp_csum",
+	    mac_config->rpa_repl_l4_comp_csum, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_l3_incl_cf",
+	    mac_config->rpa_repl_l3_incl_cf, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_l3_comp_csum",
+	    mac_config->rpa_repl_l3_comp_csum, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv4_tcp_incl_ph",
+	    mac_config->rpa_repl_ipv4_tcp_incl_ph, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv6_tcp_incl_ph",
+	    mac_config->rpa_repl_ipv6_tcp_incl_ph, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv4_udp_incl_ph",
+	    mac_config->rpa_repl_ipv4_udp_incl_ph, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_ipv6_udp_incl_ph",
+	    mac_config->rpa_repl_ipv6_udp_incl_ph, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_l4_incl_cf",
+	    mac_config->rpa_repl_l4_incl_cf, "%u");
+	__HAL_AUX_CONFIG_ENTRY("rpa_repl_strip_vlan_tag",
+	    mac_config->rpa_repl_strip_vlan_tag, "%u");
+	__HAL_AUX_CONFIG_ENTRY("ISR Polling count",
+	    dev_config->isr_polling_cnt, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Maximum Payload Size",
+	    dev_config->max_payload_size, "%u");
+	__HAL_AUX_CONFIG_ENTRY("MMRB Count",
+	    dev_config->mmrb_count, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Statistics Refresh Time",
+	    dev_config->stats_refresh_time_sec, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Interrupt Mode",
+	    dev_config->intr_mode, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Dump on Unknwon Error",
+	    dev_config->dump_on_unknown, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Dump on Serious Error",
+	    dev_config->dump_on_serr, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Dump on Critical Error",
+	    dev_config->dump_on_critical, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Dump on ECC Error",
+	    dev_config->dump_on_eccerr, "%u");
+	__HAL_AUX_CONFIG_ENTRY("RTH Enable",
+	    dev_config->rth_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("RTS MAC Enable",
+	    dev_config->rts_mac_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("RTS QOS Enable",
+	    dev_config->rts_qos_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("RTS Port Enable",
+	    dev_config->rts_port_en, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Max CQE Groups",
+	    dev_config->max_cqe_groups, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Max Number of OD Groups",
+	    dev_config->max_num_wqe_od_groups, "%u");
+	__HAL_AUX_CONFIG_ENTRY("No WQE Threshold",
+	    dev_config->no_wqe_threshold, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Refill Threshold-High",
+	    dev_config->refill_threshold_high, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Refill Threshold-Low",
+	    dev_config->refill_threshold_low, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Ack Block Limit",
+	    dev_config->ack_blk_limit, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Poll or Doorbell",
+	    dev_config->poll_or_doorbell, "%u");
+	__HAL_AUX_CONFIG_ENTRY("stats_read_method",
+	    dev_config->stats_read_method, "%u");
+	__HAL_AUX_CONFIG_ENTRY("Device Poll Timeout",
+	    dev_config->device_poll_millis, "%u");
+	__HAL_AUX_CONFIG_ENTRY("debug_level",
+	    dev_config->debug_level, "%u");
+	__HAL_AUX_CONFIG_ENTRY("debug_mask",
+	    dev_config->debug_mask, "%u");
+
+#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
+	__HAL_AUX_CONFIG_ENTRY("Trace buffer size",
+	    dev_config->tracebuf_size, "%u");
+#endif
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		if (!(((__hal_device_t *) hldev)->vpath_assignments & mBIT(i)))
+			continue;
+
+		__HAL_AUX_CONFIG_ENTRY("Virtual Path id",
+		    dev_config->vp_config[i].vp_id, "%u");
+		__HAL_AUX_CONFIG_ENTRY("No Snoop",
+		    dev_config->vp_config[i].no_snoop, "%u");
+		__HAL_AUX_CONFIG_ENTRY("mtu",
+		    dev_config->vp_config[i].mtu, "%u");
+		__HAL_AUX_CONFIG_ENTRY("TPA LSOv2 Enable",
+		    dev_config->vp_config[i].tpa_lsov2_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("TPA Ignore Frame Error",
+		    dev_config->vp_config[i].tpa_ignore_frame_error, "%u");
+		__HAL_AUX_CONFIG_ENTRY("TPA IPv6 Keep Searching",
+		    dev_config->vp_config[i].tpa_ipv6_keep_searching, "%u");
+		__HAL_AUX_CONFIG_ENTRY("TPA L4 pseudo header present",
+		    dev_config->vp_config[i].tpa_l4_pshdr_present, "%u");
+		__HAL_AUX_CONFIG_ENTRY("TPA support mobile IPv6 Headers",
+		    dev_config->vp_config[i].tpa_support_mobile_ipv6_hdrs,
+		    "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA IPv4 TCP Include pseudo header",
+		    dev_config->vp_config[i].rpa_ipv4_tcp_incl_ph, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA IPv6 TCP Include pseudo header",
+		    dev_config->vp_config[i].rpa_ipv6_tcp_incl_ph, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA IPv4 UDP Include pseudo header",
+		    dev_config->vp_config[i].rpa_ipv4_udp_incl_ph, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA IPv6 UDP Include pseudo header",
+		    dev_config->vp_config[i].rpa_ipv6_udp_incl_ph, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA L4 Include CF",
+		    dev_config->vp_config[i].rpa_l4_incl_cf, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA Strip VLAN Tag",
+		    dev_config->vp_config[i].rpa_strip_vlan_tag, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA L4 Comp Csum Enable",
+		    dev_config->vp_config[i].rpa_l4_comp_csum, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA L3 Include CF Enable",
+		    dev_config->vp_config[i].rpa_l3_incl_cf, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA L3 Comp Csum",
+		    dev_config->vp_config[i].rpa_l3_comp_csum, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA Unicast All Address Enable",
+		    dev_config->vp_config[i].rpa_ucast_all_addr_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA Unicast All Address Enable",
+		    dev_config->vp_config[i].rpa_ucast_all_addr_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA Multicast All Address Enable",
+		    dev_config->vp_config[i].rpa_mcast_all_addr_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA Broadcast Enable",
+		    dev_config->vp_config[i].rpa_bcast_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RPA All VID Enable",
+		    dev_config->vp_config[i].rpa_all_vid_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("VP Queue L2 Flow",
+		    dev_config->vp_config[i].vp_queue_l2_flow, "%u");
+
+		__HAL_AUX_CONFIG_ENTRY("Ring blocks",
+		    dev_config->vp_config[i].ring.ring_length, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Buffer Mode",
+		    dev_config->vp_config[i].ring.buffer_mode, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Scatter Mode",
+		    dev_config->vp_config[i].ring.scatter_mode, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Post Mode",
+		    dev_config->vp_config[i].ring.post_mode, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Maximum Frame Length",
+		    dev_config->vp_config[i].ring.max_frm_len, "%u");
+		__HAL_AUX_CONFIG_ENTRY("No Snoop Bits",
+		    dev_config->vp_config[i].ring.no_snoop_bits, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Rx Timer Value",
+		    dev_config->vp_config[i].ring.rx_timer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Greedy return",
+		    dev_config->vp_config[i].ring.greedy_return, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Rx Timer CI",
+		    dev_config->vp_config[i].ring.rx_timer_ci, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Backoff Interval",
+		    dev_config->vp_config[i].ring.backoff_interval_us, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Indicate Max Packets",
+		    dev_config->vp_config[i].ring.indicate_max_pkts, "%u");
+
+
+		__HAL_AUX_CONFIG_ENTRY("FIFO Blocks",
+		    dev_config->vp_config[i].fifo.fifo_length, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Max Frags",
+		    dev_config->vp_config[i].fifo.max_frags, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Alignment Size",
+		    dev_config->vp_config[i].fifo.alignment_size, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Maximum Aligned Frags",
+		    dev_config->vp_config[i].fifo.max_aligned_frags, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Interrupt Enable",
+		    dev_config->vp_config[i].fifo.intr, "%u");
+		__HAL_AUX_CONFIG_ENTRY("No Snoop Bits",
+		    dev_config->vp_config[i].fifo.no_snoop_bits, "%u");
+
+
+		__HAL_AUX_CONFIG_ENTRY("Interrupt Enable",
+		    dev_config->vp_config[i].tti.intr_enable, "%u");
+		__HAL_AUX_CONFIG_ENTRY("BTimer Value",
+		    dev_config->vp_config[i].tti.btimer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer AC Enable",
+		    dev_config->vp_config[i].tti.timer_ac_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer CI Enable",
+		    dev_config->vp_config[i].tti.timer_ci_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer RI Enable",
+		    dev_config->vp_config[i].tti.timer_ri_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer Event SF",
+		    dev_config->vp_config[i].tti.rtimer_event_sf, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RTimer Value",
+		    dev_config->vp_config[i].tti.rtimer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Sel",
+		    dev_config->vp_config[i].tti.util_sel, "%u");
+		__HAL_AUX_CONFIG_ENTRY("LTimer Value",
+		    dev_config->vp_config[i].tti.ltimer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Tx Frame Count Enable",
+		    dev_config->vp_config[i].tti.txfrm_cnt_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Txd Count Enable",
+		    dev_config->vp_config[i].tti.txd_cnt_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Range A",
+		    dev_config->vp_config[i].tti.urange_a, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count A",
+		    dev_config->vp_config[i].tti.uec_a, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Range B",
+		    dev_config->vp_config[i].tti.urange_b, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count B",
+		    dev_config->vp_config[i].tti.uec_b, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Range C",
+		    dev_config->vp_config[i].tti.urange_c, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count C",
+		    dev_config->vp_config[i].tti.uec_c, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count D",
+		    dev_config->vp_config[i].tti.uec_d, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca Interrupt Threshold",
+		    dev_config->vp_config[i].tti.ufca_intr_thres, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca Low Limit",
+		    dev_config->vp_config[i].tti.ufca_lo_lim, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca High Limit",
+		    dev_config->vp_config[i].tti.ufca_hi_lim, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca lbolt period",
+		    dev_config->vp_config[i].tti.ufca_lbolt_period, "%u");
+
+		__HAL_AUX_CONFIG_ENTRY("Interrupt Enable",
+		    dev_config->vp_config[i].rti.intr_enable, "%u");
+		__HAL_AUX_CONFIG_ENTRY("BTimer Value",
+		    dev_config->vp_config[i].rti.btimer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer AC Enable",
+		    dev_config->vp_config[i].rti.timer_ac_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer CI Enable",
+		    dev_config->vp_config[i].rti.timer_ci_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer RI Enable",
+		    dev_config->vp_config[i].rti.timer_ri_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Timer Event SF",
+		    dev_config->vp_config[i].rti.rtimer_event_sf, "%u");
+		__HAL_AUX_CONFIG_ENTRY("RTimer Value",
+		    dev_config->vp_config[i].rti.rtimer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Sel",
+		    dev_config->vp_config[i].rti.util_sel, "%u");
+		__HAL_AUX_CONFIG_ENTRY("LTimer Value",
+		    dev_config->vp_config[i].rti.ltimer_val, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Tx Frame Count Enable",
+		    dev_config->vp_config[i].rti.txfrm_cnt_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Txd Count Enable",
+		    dev_config->vp_config[i].rti.txd_cnt_en, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Range A",
+		    dev_config->vp_config[i].rti.urange_a, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count A",
+		    dev_config->vp_config[i].rti.uec_a, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Range B",
+		    dev_config->vp_config[i].rti.urange_b, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count B",
+		    dev_config->vp_config[i].rti.uec_b, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Range C",
+		    dev_config->vp_config[i].rti.urange_c, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count C",
+		    dev_config->vp_config[i].rti.uec_c, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Util Event Count D",
+		    dev_config->vp_config[i].rti.uec_d, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca Interrupt Threshold",
+		    dev_config->vp_config[i].rti.ufca_intr_thres, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca Low Limit",
+		    dev_config->vp_config[i].rti.ufca_lo_lim, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca High Limit",
+		    dev_config->vp_config[i].rti.ufca_hi_lim, "%u");
+		__HAL_AUX_CONFIG_ENTRY("Ufca lbolt period",
+		    dev_config->vp_config[i].rti.ufca_lbolt_period, "%u");
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	vxge_os_free(hldev->pdev, dev_config,
+	    sizeof(vxge_hal_device_config_t));
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_bar0_read - Read and format X3100 BAR0 register.
+ * @devh: HAL device handle.
+ * @offset: Register offset in the BAR0 space.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read X3100 register from BAR0 space.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ *
+ * See also: vxge_hal_mgmt_reg_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_bar0_read(vxge_hal_device_h devh,
+    unsigned int offset, int bufsize, char *retbuf,
+    int *retsize)
+{
+	vxge_hal_status_e status;
+	u64 retval;
+
+	status = vxge_hal_mgmt_bar0_read(devh, offset, &retval);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	if (bufsize < VXGE_OS_SPRINTF_STRLEN)
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+
+	*retsize = vxge_os_snprintf(retbuf, bufsize,
+	    "0x%04X%c0x%08X%08X\n", offset,
+	    VXGE_HAL_AUX_SEPA, (u32) (retval >> 32), (u32) retval);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_bar1_read - Read and format X3100 BAR1 register.
+ * @devh: HAL device handle.
+ * @offset: Register offset in the BAR1 space.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read X3100 register from BAR1 space.
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_OUT_OF_SPACE - Buffer size is very small.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ *
+ * See also: vxge_hal_mgmt_reg_read().
+ */
+vxge_hal_status_e
+vxge_hal_aux_bar1_read(vxge_hal_device_h devh,
+    unsigned int offset, int bufsize, char *retbuf,
+    int *retsize)
+{
+	vxge_hal_status_e status;
+	u64 retval;
+
+	status = vxge_hal_mgmt_bar1_read(devh, offset, &retval);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	if (bufsize < VXGE_OS_SPRINTF_STRLEN)
+		return (VXGE_HAL_ERR_OUT_OF_SPACE);
+
+	*retsize = vxge_os_snprintf(retbuf, bufsize, "0x%04X%c0x%08X%08X\n",
+	    offset, VXGE_HAL_AUX_SEPA, (u32) (retval >> 32), (u32) retval);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_bar0_write - Write BAR0 register.
+ * @devh: HAL device handle.
+ * @offset: Register offset in the BAR0 space.
+ * @value: Regsister value (to write).
+ *
+ * Write BAR0 register.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
+ * VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
+ * valid.
+ *
+ * See also: vxge_hal_mgmt_reg_write().
+ */
+vxge_hal_status_e
+vxge_hal_aux_bar0_write(vxge_hal_device_h devh,
+    unsigned int offset, u64 value)
+{
+	vxge_hal_status_e status;
+
+	status = vxge_hal_mgmt_bar0_write(devh, offset, value);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_vpath_hw_read - Read vpath hardware statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath hardware statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_hw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_hw_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize)
+{
+	vxge_hal_status_e status;
+	vxge_hal_vpath_stats_hw_info_t hw_info;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(vpath_handle != NULL);
+
+	status = vxge_hal_vpath_hw_stats_enable(vpath_handle);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	status = vxge_hal_vpath_hw_stats_get(vpath_handle, &hw_info);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	__HAL_AUX_ENTRY("ini_num_mwr_sent",
+	    hw_info.ini_num_mwr_sent, "%u");
+	__HAL_AUX_ENTRY("ini_num_mrd_sent",
+	    hw_info.ini_num_mrd_sent, "%u");
+	__HAL_AUX_ENTRY("ini_num_cpl_rcvd",
+	    hw_info.ini_num_cpl_rcvd, "%u");
+	__HAL_AUX_ENTRY("ini_num_mwr_byte_sent",
+	    hw_info.ini_num_mwr_byte_sent, "%llu");
+	__HAL_AUX_ENTRY("ini_num_cpl_byte_rcvd",
+	    hw_info.ini_num_cpl_byte_rcvd, "%llu");
+	__HAL_AUX_ENTRY("wrcrdtarb_xoff",
+	    hw_info.wrcrdtarb_xoff, "%u");
+	__HAL_AUX_ENTRY("rdcrdtarb_xoff",
+	    hw_info.rdcrdtarb_xoff, "%u");
+	__HAL_AUX_ENTRY("vpath_genstats_count0",
+	    hw_info.vpath_genstats_count0, "%u");
+	__HAL_AUX_ENTRY("vpath_genstats_count1",
+	    hw_info.vpath_genstats_count1, "%u");
+	__HAL_AUX_ENTRY("vpath_genstats_count2",
+	    hw_info.vpath_genstats_count2, "%u");
+	__HAL_AUX_ENTRY("vpath_genstats_count3",
+	    hw_info.vpath_genstats_count3, "%u");
+	__HAL_AUX_ENTRY("vpath_genstats_count4",
+	    hw_info.vpath_genstats_count4, "%u");
+	__HAL_AUX_ENTRY("vpath_genstats_count5",
+	    hw_info.vpath_genstats_count5, "%u");
+	__HAL_AUX_ENTRY("tx_ttl_eth_frms",
+	    hw_info.tx_stats.tx_ttl_eth_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ttl_eth_octets",
+	    hw_info.tx_stats.tx_ttl_eth_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_data_octets",
+	    hw_info.tx_stats.tx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_mcast_frms",
+	    hw_info.tx_stats.tx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_bcast_frms",
+	    hw_info.tx_stats.tx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ucast_frms",
+	    hw_info.tx_stats.tx_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_tagged_frms",
+	    hw_info.tx_stats.tx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip",
+	    hw_info.tx_stats.tx_vld_ip, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_octets",
+	    hw_info.tx_stats.tx_vld_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_icmp",
+	    hw_info.tx_stats.tx_icmp, "%llu");
+	__HAL_AUX_ENTRY("tx_tcp",
+	    hw_info.tx_stats.tx_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_rst_tcp",
+	    hw_info.tx_stats.tx_rst_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_udp",
+	    hw_info.tx_stats.tx_udp, "%llu");
+	__HAL_AUX_ENTRY("tx_unknown_protocol",
+	    hw_info.tx_stats.tx_unknown_protocol, "%u");
+	__HAL_AUX_ENTRY("tx_lost_ip",
+	    hw_info.tx_stats.tx_lost_ip, "%u");
+	__HAL_AUX_ENTRY("tx_parse_error",
+	    hw_info.tx_stats.tx_parse_error, "%u");
+	__HAL_AUX_ENTRY("tx_tcp_offload",
+	    hw_info.tx_stats.tx_tcp_offload, "%llu");
+	__HAL_AUX_ENTRY("tx_retx_tcp_offload",
+	    hw_info.tx_stats.tx_retx_tcp_offload, "%llu");
+	__HAL_AUX_ENTRY("tx_lost_ip_offload",
+	    hw_info.tx_stats.tx_lost_ip_offload, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_eth_frms",
+	    hw_info.rx_stats.rx_ttl_eth_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_frms",
+	    hw_info.rx_stats.rx_vld_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_frms",
+	    hw_info.rx_stats.rx_offload_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_eth_octets",
+	    hw_info.rx_stats.rx_ttl_eth_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_data_octets",
+	    hw_info.rx_stats.rx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_octets",
+	    hw_info.rx_stats.rx_offload_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_mcast_frms",
+	    hw_info.rx_stats.rx_vld_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_bcast_frms",
+	    hw_info.rx_stats.rx_vld_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ucast_frms",
+	    hw_info.rx_stats.rx_accepted_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_nucast_frms",
+	    hw_info.rx_stats.rx_accepted_nucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_tagged_frms",
+	    hw_info.rx_stats.rx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_long_frms",
+	    hw_info.rx_stats.rx_long_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_usized_frms",
+	    hw_info.rx_stats.rx_usized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_osized_frms",
+	    hw_info.rx_stats.rx_osized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_frag_frms",
+	    hw_info.rx_stats.rx_frag_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_jabber_frms",
+	    hw_info.rx_stats.rx_jabber_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_64_frms",
+	    hw_info.rx_stats.rx_ttl_64_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_65_127_frms",
+	    hw_info.rx_stats.rx_ttl_65_127_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_128_255_frms",
+	    hw_info.rx_stats.rx_ttl_128_255_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_256_511_frms",
+	    hw_info.rx_stats.rx_ttl_256_511_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_512_1023_frms",
+	    hw_info.rx_stats.rx_ttl_512_1023_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1024_1518_frms",
+	    hw_info.rx_stats.rx_ttl_1024_1518_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1519_4095_frms",
+	    hw_info.rx_stats.rx_ttl_1519_4095_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_4096_8191_frms",
+	    hw_info.rx_stats.rx_ttl_4096_8191_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_8192_max_frms",
+	    hw_info.rx_stats.rx_ttl_8192_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_gt_max_frms",
+	    hw_info.rx_stats.rx_ttl_gt_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ip",
+	    hw_info.rx_stats.rx_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ip",
+	    hw_info.rx_stats.rx_accepted_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_octets",
+	    hw_info.rx_stats.rx_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_err_ip",
+	    hw_info.rx_stats.rx_err_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_icmp",
+	    hw_info.rx_stats.rx_icmp, "%llu");
+	__HAL_AUX_ENTRY("rx_tcp",
+	    hw_info.rx_stats.rx_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_udp",
+	    hw_info.rx_stats.rx_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_err_tcp",
+	    hw_info.rx_stats.rx_err_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_lost_frms",
+	    hw_info.rx_stats.rx_lost_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_lost_ip",
+	    hw_info.rx_stats.rx_lost_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_lost_ip_offload",
+	    hw_info.rx_stats.rx_lost_ip_offload, "%llu");
+	__HAL_AUX_ENTRY("rx_various_discard",
+	    hw_info.rx_stats.rx_various_discard, "%u");
+	__HAL_AUX_ENTRY("rx_sleep_discard",
+	    hw_info.rx_stats.rx_sleep_discard, "%u");
+	__HAL_AUX_ENTRY("rx_red_discard",
+	    hw_info.rx_stats.rx_red_discard, "%u");
+	__HAL_AUX_ENTRY("rx_queue_full_discard",
+	    hw_info.rx_stats.rx_queue_full_discard, "%u");
+	__HAL_AUX_ENTRY("rx_mpa_ok_frms",
+	    hw_info.rx_stats.rx_mpa_ok_frms, "%llu");
+	__HAL_AUX_ENTRY("prog_event_vnum1",
+	    hw_info.prog_event_vnum1, "%u");
+	__HAL_AUX_ENTRY("prog_event_vnum0",
+	    hw_info.prog_event_vnum0, "%u");
+	__HAL_AUX_ENTRY("prog_event_vnum3",
+	    hw_info.prog_event_vnum3, "%u");
+	__HAL_AUX_ENTRY("prog_event_vnum2",
+	    hw_info.prog_event_vnum2, "%u");
+	__HAL_AUX_ENTRY("rx_multi_cast_frame_discard",
+	    hw_info.rx_multi_cast_frame_discard, "%u");
+	__HAL_AUX_ENTRY("rx_frm_transferred",
+	    hw_info.rx_frm_transferred, "%u");
+	__HAL_AUX_ENTRY("rxd_returned",
+	    hw_info.rxd_returned, "%u");
+	__HAL_AUX_ENTRY("rx_mpa_len_fail_frms",
+	    hw_info.rx_mpa_len_fail_frms, "%u");
+	__HAL_AUX_ENTRY("rx_mpa_mrk_fail_frms",
+	    hw_info.rx_mpa_mrk_fail_frms, "%u");
+	__HAL_AUX_ENTRY("rx_mpa_crc_fail_frms",
+	    hw_info.rx_mpa_crc_fail_frms, "%u");
+	__HAL_AUX_ENTRY("rx_permitted_frms",
+	    hw_info.rx_permitted_frms, "%u");
+	__HAL_AUX_ENTRY("rx_vp_reset_discarded_frms",
+	    hw_info.rx_vp_reset_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_wol_frms",
+	    hw_info.rx_wol_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_vp_reset_discarded_frms",
+	    hw_info.tx_vp_reset_discarded_frms, "%llu");
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_device_hw_read - Read device hardware statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device hardware statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_hw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_hw_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	u32 i;
+	int rsize = 0;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(devh);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		__HAL_AUX_ENTRY("H/W stats for vpath id", i, "%u");
+
+		status = vxge_hal_aux_stats_vpath_hw_read(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]),
+		    leftsize, ptr, &rsize);
+
+		if (status != VXGE_HAL_OK)
+			return (status);
+
+		ptr += rsize;
+		leftsize -= rsize;
+
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+#define	__HAL_AUX_VPATH_SW_COMMON_INFO(prefix, common) {\
+	__HAL_AUX_ENTRY(prefix"full_cnt", (common)->full_cnt, "%u");\
+	__HAL_AUX_ENTRY(prefix"usage_cnt", (common)->usage_cnt, "%u");\
+	__HAL_AUX_ENTRY(prefix"usage_max", (common)->usage_max, "%u");\
+	__HAL_AUX_ENTRY(prefix"avg_compl_per_intr_cnt",\
+		(common)->avg_compl_per_intr_cnt, "%u");\
+	__HAL_AUX_ENTRY(prefix"total_compl_cnt",\
+		(common)->total_compl_cnt, "%u");\
+}
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_fifo_read - Read vpath fifo software statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath fifo software statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_fifo_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_fifo_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize)
+{
+	u32 i;
+	u8 strbuf[256];
+	vxge_hal_status_e status;
+	vxge_hal_vpath_stats_sw_fifo_info_t *fifo_info;
+	vxge_hal_vpath_stats_sw_info_t sw_stats;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(vpath_handle != NULL);
+
+	status = vxge_hal_vpath_sw_stats_get(vpath_handle, &sw_stats);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	fifo_info = &sw_stats.fifo_stats;
+
+	__HAL_AUX_VPATH_SW_COMMON_INFO("fifo_",
+	    &fifo_info->common_stats);
+
+	__HAL_AUX_ENTRY("total_posts",
+	    fifo_info->total_posts, "%u");
+	__HAL_AUX_ENTRY("total_buffers",
+	    fifo_info->total_buffers, "%u");
+	__HAL_AUX_ENTRY("avg_buffers_per_post",
+	    fifo_info->avg_buffers_per_post, "%u");
+	__HAL_AUX_ENTRY("copied_frags",
+	    fifo_info->copied_frags, "%u");
+	__HAL_AUX_ENTRY("copied_buffers",
+	    fifo_info->copied_buffers, "%u");
+	__HAL_AUX_ENTRY("avg_buffer_size",
+	    fifo_info->avg_buffer_size, "%u");
+	__HAL_AUX_ENTRY("avg_post_size",
+	    fifo_info->avg_post_size, "%u");
+	__HAL_AUX_ENTRY("total_frags",
+	    fifo_info->total_frags, "%u");
+	__HAL_AUX_ENTRY("copied_frags",
+	    fifo_info->copied_frags, "%u");
+	__HAL_AUX_ENTRY("total_posts_dang_dtrs",
+	    fifo_info->total_posts_dang_dtrs, "%u");
+	__HAL_AUX_ENTRY("total_posts_dang_frags",
+	    fifo_info->total_posts_dang_frags, "%u");
+
+	for (i = 0; i < 16; i++) {
+		(void) vxge_os_snprintf((char *) strbuf,
+		    sizeof(strbuf), "txd_t_code_err_cnt[%d]", i);
+		__HAL_AUX_ENTRY(strbuf,
+		    fifo_info->txd_t_code_err_cnt[i], "%u");
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_ring_read - Read vpath ring software statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath ring software statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_ring_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_ring_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize)
+{
+	u32 i;
+	u8 strbuf[256];
+	vxge_hal_status_e status;
+	vxge_hal_vpath_stats_sw_ring_info_t *ring_info;
+	vxge_hal_vpath_stats_sw_info_t sw_stats;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(vpath_handle != NULL);
+
+	status = vxge_hal_vpath_sw_stats_get(vpath_handle, &sw_stats);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	ring_info = &sw_stats.ring_stats;
+
+	__HAL_AUX_VPATH_SW_COMMON_INFO("ring_",
+	    &ring_info->common_stats);
+
+	for (i = 0; i < 16; i++) {
+		(void) vxge_os_snprintf((char *) strbuf,
+		    sizeof(strbuf), "rxd_t_code_err_cnt[%d]", i);
+		__HAL_AUX_ENTRY(strbuf,
+		    ring_info->rxd_t_code_err_cnt[i], "%u");
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_err_read - Read vpath err software statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read vpath err software statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_err_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_err_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize)
+{
+	vxge_hal_vpath_stats_sw_err_t *err_info;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(vpath_handle != NULL);
+
+	err_info = &vp->vpath->sw_stats->error_stats;
+
+	__HAL_AUX_ENTRY("unknown_alarms",
+	    err_info->unknown_alarms, "%u");
+	__HAL_AUX_ENTRY("network_sustained_fault",
+	    err_info->network_sustained_fault, "%u");
+	__HAL_AUX_ENTRY("network_sustained_ok",
+	    err_info->network_sustained_ok, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo0_overwrite",
+	    err_info->kdfcctl_fifo0_overwrite, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo0_poison",
+	    err_info->kdfcctl_fifo0_poison, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo0_dma_error",
+	    err_info->kdfcctl_fifo0_dma_error, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo1_overwrite",
+	    err_info->kdfcctl_fifo1_overwrite, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo1_poison",
+	    err_info->kdfcctl_fifo1_poison, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo1_dma_error",
+	    err_info->kdfcctl_fifo1_dma_error, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo2_overwrite",
+	    err_info->kdfcctl_fifo2_overwrite, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo2_poison",
+	    err_info->kdfcctl_fifo2_poison, "%u");
+	__HAL_AUX_ENTRY("kdfcctl_fifo2_dma_error",
+	    err_info->kdfcctl_fifo2_dma_error, "%u");
+	__HAL_AUX_ENTRY("dblgen_fifo0_overflow",
+	    err_info->dblgen_fifo0_overflow, "%u");
+	__HAL_AUX_ENTRY("dblgen_fifo1_overflow",
+	    err_info->dblgen_fifo1_overflow, "%u");
+	__HAL_AUX_ENTRY("dblgen_fifo2_overflow",
+	    err_info->dblgen_fifo2_overflow, "%u");
+	__HAL_AUX_ENTRY("statsb_pif_chain_error",
+	    err_info->statsb_pif_chain_error, "%u");
+	__HAL_AUX_ENTRY("statsb_drop_timeout",
+	    err_info->statsb_drop_timeout, "%u");
+	__HAL_AUX_ENTRY("target_illegal_access",
+	    err_info->target_illegal_access, "%u");
+	__HAL_AUX_ENTRY("ini_serr_det",
+	    err_info->ini_serr_det, "%u");
+	__HAL_AUX_ENTRY("pci_config_status_err",
+	    err_info->pci_config_status_err, "%u");
+	__HAL_AUX_ENTRY("pci_config_uncor_err",
+	    err_info->pci_config_uncor_err, "%u");
+	__HAL_AUX_ENTRY("pci_config_cor_err",
+	    err_info->pci_config_cor_err, "%u");
+	__HAL_AUX_ENTRY("mrpcim_to_vpath_alarms",
+	    err_info->mrpcim_to_vpath_alarms, "%u");
+	__HAL_AUX_ENTRY("srpcim_to_vpath_alarms",
+	    err_info->srpcim_to_vpath_alarms, "%u");
+	__HAL_AUX_ENTRY("srpcim_msg_to_vpath",
+	    err_info->srpcim_msg_to_vpath, "%u");
+	__HAL_AUX_ENTRY("prc_ring_bumps",
+	    err_info->prc_ring_bumps, "%u");
+	__HAL_AUX_ENTRY("prc_rxdcm_sc_err",
+	    err_info->prc_rxdcm_sc_err, "%u");
+	__HAL_AUX_ENTRY("prc_rxdcm_sc_abort",
+	    err_info->prc_rxdcm_sc_abort, "%u");
+	__HAL_AUX_ENTRY("prc_quanta_size_err",
+	    err_info->prc_quanta_size_err, "%u");
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_vpath_sw_read - Read vpath soft statistics.
+ * @vpath_handle: HAL Vpath handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device hardware statistics. This is a subset of stats counters
+ * from vxge_hal_vpath_stats_sw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_vpath_sw_read(
+    vxge_hal_vpath_h vpath_handle,
+    int bufsize,
+    char *retbuf,
+    int *retsize)
+{
+	int rsize = 0;
+	vxge_hal_status_e status;
+	vxge_hal_vpath_stats_sw_info_t *sw_info;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(vpath_handle != NULL);
+
+	sw_info = vp->vpath->sw_stats;
+
+	__HAL_AUX_ENTRY("soft_reset_cnt", sw_info->soft_reset_cnt, "%u");
+
+
+	status = vxge_hal_aux_stats_vpath_sw_err_read(vpath_handle,
+	    leftsize, ptr, &rsize);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	ptr += rsize;
+	leftsize -= rsize;
+
+	status = vxge_hal_aux_stats_vpath_sw_ring_read(vpath_handle,
+	    leftsize, ptr, &rsize);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	ptr += rsize;
+	leftsize -= rsize;
+
+	status = vxge_hal_aux_stats_vpath_sw_fifo_read(vpath_handle,
+	    leftsize, ptr, &rsize);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+
+	leftsize -= rsize;
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_device_sw_read - Read device software statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device software statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_sw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_sw_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	u32 i;
+	int rsize = 0;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(devh);
+
+	__HAL_AUX_ENTRY("not_traffic_intr_cnt",
+	    hldev->header.not_traffic_intr_cnt, "%u");
+	__HAL_AUX_ENTRY("traffic_intr_cnt",
+	    hldev->header.traffic_intr_cnt, "%u");
+	__HAL_AUX_ENTRY("total_intr_cnt",
+	    hldev->header.not_traffic_intr_cnt +
+	    hldev->header.traffic_intr_cnt, "%u");
+	__HAL_AUX_ENTRY("soft_reset_cnt",
+	    hldev->stats.sw_dev_info_stats.soft_reset_cnt, "%u");
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		__HAL_AUX_ENTRY("S/W stats for vpath id", i, "%u");
+
+		status = vxge_hal_aux_stats_vpath_sw_read(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]),
+		    leftsize, ptr, &rsize);
+
+		if (status != VXGE_HAL_OK)
+			return (status);
+
+		ptr += rsize;
+		leftsize -= rsize;
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_device_sw_err_read - Read device software error statistics
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device software error statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_sw_info_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_sw_err_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	vxge_hal_device_stats_sw_err_t *sw_err;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(devh);
+
+	sw_err = &hldev->stats.sw_dev_err_stats;
+
+	__HAL_AUX_ENTRY("mrpcim_alarms", sw_err->mrpcim_alarms, "%u");
+	__HAL_AUX_ENTRY("srpcim_alarms", sw_err->srpcim_alarms, "%u");
+	__HAL_AUX_ENTRY("vpath_alarms", sw_err->vpath_alarms, "%u");
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_device_read - Read device statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device statistics. This is a subset of stats counters
+ * from vxge_hal_device_stats_t {}.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_device_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	char *ptr = retbuf;
+	int rsize = 0, leftsize = bufsize;
+	vxge_hal_status_e status;
+
+	vxge_assert(devh);
+
+	status = vxge_hal_aux_stats_device_hw_read(devh,
+	    leftsize, ptr, &rsize);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	ptr += rsize;
+	leftsize -= rsize;
+
+	status = vxge_hal_aux_stats_device_sw_err_read(devh,
+	    leftsize, ptr, &rsize);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	ptr += rsize;
+	leftsize -= rsize;
+
+	status = vxge_hal_aux_stats_device_sw_read(devh,
+	    leftsize, ptr, &rsize);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	leftsize -= rsize;
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_stats_xpak_read - Read device xpak statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device xpak statistics. This is valid for function 0 device only
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_xpak_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	u32 i;
+	vxge_hal_mrpcim_xpak_stats_t *xpak_stats;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM))
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
+
+		xpak_stats = &hldev->mrpcim->xpak_stats[i];
+
+		__HAL_AUX_ENTRY("Wire Port Id : ", i, "%u");
+		__HAL_AUX_ENTRY("alarm_transceiver_temp_high",
+		    xpak_stats->excess_bias_current, "%u");
+		__HAL_AUX_ENTRY("alarm_transceiver_temp_high",
+		    xpak_stats->excess_laser_output, "%u");
+		__HAL_AUX_ENTRY("alarm_transceiver_temp_high",
+		    xpak_stats->excess_temp, "%u");
+		__HAL_AUX_ENTRY("alarm_transceiver_temp_high",
+		    xpak_stats->alarm_transceiver_temp_high, "%u");
+		__HAL_AUX_ENTRY("alarm_transceiver_temp_low",
+		    xpak_stats->alarm_transceiver_temp_low, "%u");
+		__HAL_AUX_ENTRY("alarm_laser_bias_current_high",
+		    xpak_stats->alarm_laser_bias_current_high, "%u");
+		__HAL_AUX_ENTRY("alarm_laser_bias_current_low",
+		    xpak_stats->alarm_laser_bias_current_low, "%u");
+		__HAL_AUX_ENTRY("alarm_laser_output_power_high",
+		    xpak_stats->alarm_laser_output_power_high, "%u");
+		__HAL_AUX_ENTRY("alarm_laser_output_power_low",
+		    xpak_stats->alarm_laser_output_power_low, "%u");
+		__HAL_AUX_ENTRY("warn_transceiver_temp_high",
+		    xpak_stats->warn_transceiver_temp_high, "%u");
+		__HAL_AUX_ENTRY("warn_transceiver_temp_low",
+		    xpak_stats->warn_transceiver_temp_low, "%u");
+		__HAL_AUX_ENTRY("warn_laser_bias_current_high",
+		    xpak_stats->warn_laser_bias_current_high, "%u");
+		__HAL_AUX_ENTRY("warn_laser_bias_current_low",
+		    xpak_stats->warn_laser_bias_current_low, "%u");
+		__HAL_AUX_ENTRY("warn_laser_output_power_high",
+		    xpak_stats->warn_laser_output_power_high, "%u");
+		__HAL_AUX_ENTRY("warn_laser_output_power_low",
+		    xpak_stats->warn_laser_output_power_low, "%u");
+
+	}
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+/*
+ * vxge_hal_aux_stats_mrpcim_read - Read device mrpcim statistics.
+ * @devh: HAL device handle.
+ * @bufsize: Buffer size.
+ * @retbuf: Buffer pointer.
+ * @retsize: Size of the result. Cannot be greater than @bufsize.
+ *
+ * Read device mrpcim statistics. This is valid for function 0 device only
+ *
+ */
+vxge_hal_status_e
+vxge_hal_aux_stats_mrpcim_read(vxge_hal_device_h devh,
+    int bufsize, char *retbuf, int *retsize)
+{
+	vxge_hal_status_e status;
+	vxge_hal_mrpcim_stats_hw_info_t mrpcim_info;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	__HAL_AUX_ENTRY_DECLARE(bufsize, retbuf);
+
+	vxge_assert(devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM))
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	status = vxge_hal_mrpcim_stats_enable(devh);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	status = vxge_hal_mrpcim_stats_get(devh, &mrpcim_info);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	__HAL_AUX_ENTRY("pic_ini_rd_drop", mrpcim_info.pic_ini_rd_drop, "%u");
+	__HAL_AUX_ENTRY("pic_ini_wr_drop", mrpcim_info.pic_ini_wr_drop, "%u");
+
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane0",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[0].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane1",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[1].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane2",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[2].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane3",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[3].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane4",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[4].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane5",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[5].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane6",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[6].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane7",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[7].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane8",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[8].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane9",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[9].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane10",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[10].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane11",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[11].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane12",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[12].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane13",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[13].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane14",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[14].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane15",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[15].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_ph_crdt_depleted_vplane16",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[16].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane0",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[0].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane1",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[1].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane2",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[2].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane3",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[3].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane4",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[4].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane5",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[5].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane6",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[6].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane7",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[7].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane8",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[8].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane9",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[9].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane10",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[10].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane11",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[11].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane12",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[12].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane13",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[13].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane14",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[14].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane15",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[15].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_wrcrdtarb_pd_crdt_depleted_vplane16",
+	    mrpcim_info.pic_wrcrdtarb_pd_crdt_depleted_vplane[16].
+	    pic_wrcrdtarb_pd_crdt_depleted, "%u");
+
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane0",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[0].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane1",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[1].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane2",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[2].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane3",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[3].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane4",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[4].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane5",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[5].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane6",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[6].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane7",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[7].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane8",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[8].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane9",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[9].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane10",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[10].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane11",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[11].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane12",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[12].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane13",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[13].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane14",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[14].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane15",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[15].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+	__HAL_AUX_ENTRY("pic_rdcrdtarb_nph_crdt_depleted_vplane16",
+	    mrpcim_info.pic_rdcrdtarb_nph_crdt_depleted_vplane[16].
+	    pic_rdcrdtarb_nph_crdt_depleted, "%u");
+
+	__HAL_AUX_ENTRY("pic_ini_rd_vpin_drop",
+	    mrpcim_info.pic_ini_rd_vpin_drop, "%u");
+	__HAL_AUX_ENTRY("pic_ini_wr_vpin_drop",
+	    mrpcim_info.pic_ini_wr_vpin_drop, "%u");
+	__HAL_AUX_ENTRY("pic_genstats_count0",
+	    mrpcim_info.pic_genstats_count0, "%u");
+	__HAL_AUX_ENTRY("pic_genstats_count1",
+	    mrpcim_info.pic_genstats_count1, "%u");
+	__HAL_AUX_ENTRY("pic_genstats_count2",
+	    mrpcim_info.pic_genstats_count2, "%u");
+	__HAL_AUX_ENTRY("pic_genstats_count3",
+	    mrpcim_info.pic_genstats_count3, "%u");
+	__HAL_AUX_ENTRY("pic_genstats_count4",
+	    mrpcim_info.pic_genstats_count4, "%u");
+	__HAL_AUX_ENTRY("pic_genstats_count5",
+	    mrpcim_info.pic_genstats_count5, "%u");
+	__HAL_AUX_ENTRY("pci_rstdrop_cpl",
+	    mrpcim_info.pci_rstdrop_cpl, "%u");
+	__HAL_AUX_ENTRY("pci_rstdrop_msg",
+	    mrpcim_info.pci_rstdrop_msg, "%u");
+	__HAL_AUX_ENTRY("pci_rstdrop_client1",
+	    mrpcim_info.pci_rstdrop_client1, "%u");
+	__HAL_AUX_ENTRY("pci_rstdrop_client0",
+	    mrpcim_info.pci_rstdrop_client0, "%u");
+	__HAL_AUX_ENTRY("pci_rstdrop_client2",
+	    mrpcim_info.pci_rstdrop_client2, "%u");
+
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane0",
+	    mrpcim_info.pci_depl_h_vplane[0].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane0",
+	    mrpcim_info.pci_depl_h_vplane[0].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane0",
+	    mrpcim_info.pci_depl_h_vplane[0].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane1",
+	    mrpcim_info.pci_depl_h_vplane[1].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane1",
+	    mrpcim_info.pci_depl_h_vplane[1].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane1",
+	    mrpcim_info.pci_depl_h_vplane[1].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane2",
+	    mrpcim_info.pci_depl_h_vplane[2].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane2",
+	    mrpcim_info.pci_depl_h_vplane[2].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane2",
+	    mrpcim_info.pci_depl_h_vplane[2].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane3",
+	    mrpcim_info.pci_depl_h_vplane[3].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane3",
+	    mrpcim_info.pci_depl_h_vplane[3].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane3",
+	    mrpcim_info.pci_depl_h_vplane[3].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane4",
+	    mrpcim_info.pci_depl_h_vplane[4].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane4",
+	    mrpcim_info.pci_depl_h_vplane[4].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane4",
+	    mrpcim_info.pci_depl_h_vplane[4].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane5",
+	    mrpcim_info.pci_depl_h_vplane[5].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane5",
+	    mrpcim_info.pci_depl_h_vplane[5].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane5",
+	    mrpcim_info.pci_depl_h_vplane[5].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane6",
+	    mrpcim_info.pci_depl_h_vplane[6].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane6",
+	    mrpcim_info.pci_depl_h_vplane[6].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane6",
+	    mrpcim_info.pci_depl_h_vplane[6].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane7",
+	    mrpcim_info.pci_depl_h_vplane[7].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane7",
+	    mrpcim_info.pci_depl_h_vplane[7].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane7",
+	    mrpcim_info.pci_depl_h_vplane[7].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane8",
+	    mrpcim_info.pci_depl_h_vplane[8].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane8",
+	    mrpcim_info.pci_depl_h_vplane[8].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane8",
+	    mrpcim_info.pci_depl_h_vplane[8].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane9",
+	    mrpcim_info.pci_depl_h_vplane[9].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane9",
+	    mrpcim_info.pci_depl_h_vplane[9].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane9",
+	    mrpcim_info.pci_depl_h_vplane[9].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane10",
+	    mrpcim_info.pci_depl_h_vplane[10].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane10",
+	    mrpcim_info.pci_depl_h_vplane[10].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane10",
+	    mrpcim_info.pci_depl_h_vplane[10].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane11",
+	    mrpcim_info.pci_depl_h_vplane[11].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane11",
+	    mrpcim_info.pci_depl_h_vplane[11].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane11",
+	    mrpcim_info.pci_depl_h_vplane[11].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane12",
+	    mrpcim_info.pci_depl_h_vplane[12].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane12",
+	    mrpcim_info.pci_depl_h_vplane[12].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane12",
+	    mrpcim_info.pci_depl_h_vplane[12].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane13",
+	    mrpcim_info.pci_depl_h_vplane[13].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane13",
+	    mrpcim_info.pci_depl_h_vplane[13].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane13",
+	    mrpcim_info.pci_depl_h_vplane[13].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane14",
+	    mrpcim_info.pci_depl_h_vplane[14].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane14",
+	    mrpcim_info.pci_depl_h_vplane[14].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane14",
+	    mrpcim_info.pci_depl_h_vplane[14].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane15",
+	    mrpcim_info.pci_depl_h_vplane[15].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane15",
+	    mrpcim_info.pci_depl_h_vplane[15].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane15",
+	    mrpcim_info.pci_depl_h_vplane[15].pci_depl_ph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cplh_vplane16",
+	    mrpcim_info.pci_depl_h_vplane[16].pci_depl_cplh, "%u");
+	__HAL_AUX_ENTRY("pci_depl_nph_vplane16",
+	    mrpcim_info.pci_depl_h_vplane[16].pci_depl_nph, "%u");
+	__HAL_AUX_ENTRY("pci_depl_ph_vplane16",
+	    mrpcim_info.pci_depl_h_vplane[16].pci_depl_ph, "%u");
+
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane0",
+	    mrpcim_info.pci_depl_d_vplane[0].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane0",
+	    mrpcim_info.pci_depl_d_vplane[0].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane0",
+	    mrpcim_info.pci_depl_d_vplane[0].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane1",
+	    mrpcim_info.pci_depl_d_vplane[1].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane1",
+	    mrpcim_info.pci_depl_d_vplane[1].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane1",
+	    mrpcim_info.pci_depl_d_vplane[1].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane2",
+	    mrpcim_info.pci_depl_d_vplane[2].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane2",
+	    mrpcim_info.pci_depl_d_vplane[2].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane2",
+	    mrpcim_info.pci_depl_d_vplane[2].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane3",
+	    mrpcim_info.pci_depl_d_vplane[3].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane3",
+	    mrpcim_info.pci_depl_d_vplane[3].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane3",
+	    mrpcim_info.pci_depl_d_vplane[3].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane4",
+	    mrpcim_info.pci_depl_d_vplane[4].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane4",
+	    mrpcim_info.pci_depl_d_vplane[4].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane4",
+	    mrpcim_info.pci_depl_d_vplane[4].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane5",
+	    mrpcim_info.pci_depl_d_vplane[5].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane5",
+	    mrpcim_info.pci_depl_d_vplane[5].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane5",
+	    mrpcim_info.pci_depl_d_vplane[5].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane6",
+	    mrpcim_info.pci_depl_d_vplane[6].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane6",
+	    mrpcim_info.pci_depl_d_vplane[6].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane6",
+	    mrpcim_info.pci_depl_d_vplane[6].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane7",
+	    mrpcim_info.pci_depl_d_vplane[7].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane7",
+	    mrpcim_info.pci_depl_d_vplane[7].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane7",
+	    mrpcim_info.pci_depl_d_vplane[7].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane8",
+	    mrpcim_info.pci_depl_d_vplane[8].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane8",
+	    mrpcim_info.pci_depl_d_vplane[8].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane8",
+	    mrpcim_info.pci_depl_d_vplane[8].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane9",
+	    mrpcim_info.pci_depl_d_vplane[9].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane9",
+	    mrpcim_info.pci_depl_d_vplane[9].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane9",
+	    mrpcim_info.pci_depl_d_vplane[9].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane10",
+	    mrpcim_info.pci_depl_d_vplane[10].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane10",
+	    mrpcim_info.pci_depl_d_vplane[10].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane10",
+	    mrpcim_info.pci_depl_d_vplane[10].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane11",
+	    mrpcim_info.pci_depl_d_vplane[11].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane11",
+	    mrpcim_info.pci_depl_d_vplane[11].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane11",
+	    mrpcim_info.pci_depl_d_vplane[11].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane12",
+	    mrpcim_info.pci_depl_d_vplane[12].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane12",
+	    mrpcim_info.pci_depl_d_vplane[12].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane12",
+	    mrpcim_info.pci_depl_d_vplane[12].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane13",
+	    mrpcim_info.pci_depl_d_vplane[13].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane13",
+	    mrpcim_info.pci_depl_d_vplane[13].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane13",
+	    mrpcim_info.pci_depl_d_vplane[13].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane14",
+	    mrpcim_info.pci_depl_d_vplane[14].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane14",
+	    mrpcim_info.pci_depl_d_vplane[14].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane14",
+	    mrpcim_info.pci_depl_d_vplane[14].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane15",
+	    mrpcim_info.pci_depl_d_vplane[15].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane15",
+	    mrpcim_info.pci_depl_d_vplane[15].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane15",
+	    mrpcim_info.pci_depl_d_vplane[15].pci_depl_pd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_cpld_vplane16",
+	    mrpcim_info.pci_depl_d_vplane[16].pci_depl_cpld, "%u");
+	__HAL_AUX_ENTRY("pci_depl_npd_vplane16",
+	    mrpcim_info.pci_depl_d_vplane[16].pci_depl_npd, "%u");
+	__HAL_AUX_ENTRY("pci_depl_pd_vplane16",
+	    mrpcim_info.pci_depl_d_vplane[16].pci_depl_pd, "%u");
+
+	__HAL_AUX_ENTRY("tx_ttl_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_ttl_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ttl_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_ttl_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_data_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_mcast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_bcast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ucast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_tagged_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_vld_ip, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_vld_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_icmp_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_icmp, "%llu");
+	__HAL_AUX_ENTRY("tx_tcp_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_rst_tcp_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_rst_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_udp_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_udp, "%llu");
+	__HAL_AUX_ENTRY("tx_parse_error_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_parse_error, "%u");
+	__HAL_AUX_ENTRY("tx_unknown_protocol_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_unknown_protocol, "%u");
+	__HAL_AUX_ENTRY("tx_pause_ctrl_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_pause_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_marker_pdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_marker_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_lacpdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_lacpdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_drop_ip_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_drop_ip, "%u");
+	__HAL_AUX_ENTRY("tx_marker_resp_pdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_marker_resp_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_char2_match_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_xgmii_char2_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_char1_match_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_xgmii_char1_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_column2_match_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_xgmii_column2_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_column1_match_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_xgmii_column1_match, "%u");
+	__HAL_AUX_ENTRY("tx_any_err_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_any_err_frms, "%u");
+	__HAL_AUX_ENTRY("tx_drop_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].tx_drop_frms, "%u");
+	__HAL_AUX_ENTRY("rx_ttl_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_vld_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_offload_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_data_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_offload_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_mcast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_vld_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_bcast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_vld_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ucast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_accepted_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_nucast_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_accepted_nucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_tagged_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_long_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_long_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_usized_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_usized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_osized_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_osized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_frag_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_frag_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_jabber_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_jabber_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_64_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_64_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_65_127_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_65_127_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_128_255_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_128_255_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_256_511_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_256_511_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_512_1023_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_512_1023_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1024_1518_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_1024_1518_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1519_4095_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_1519_4095_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_4096_8191_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_4096_8191_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_8192_max_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_8192_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_gt_max_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ttl_gt_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ip_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_accepted_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_octets_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_err_ip_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_err_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_icmp_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_icmp, "%llu");
+	__HAL_AUX_ENTRY("rx_tcp_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_udp_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_err_tcp_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_err_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_pause_cnt_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_pause_count, "%llu");
+	__HAL_AUX_ENTRY("rx_pause_ctrl_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_pause_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_unsup_ctrl_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_unsup_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_fcs_err_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_fcs_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_in_rng_len_err_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_in_rng_len_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_out_rng_len_err_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_out_rng_len_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_drop_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_discarded_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_ip_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_drop_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_drp_udp_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_drop_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_marker_pdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_marker_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_lacpdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_lacpdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_unknown_pdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_unknown_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_marker_resp_pdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_marker_resp_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_fcs_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_fcs_discard, "%u");
+	__HAL_AUX_ENTRY("rx_illegal_pdu_frms_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_illegal_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_switch_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_switch_discard, "%u");
+	__HAL_AUX_ENTRY("rx_len_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_len_discard, "%u");
+	__HAL_AUX_ENTRY("rx_rpa_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_rpa_discard, "%u");
+	__HAL_AUX_ENTRY("rx_l2_mgmt_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_l2_mgmt_discard, "%u");
+	__HAL_AUX_ENTRY("rx_rts_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_rts_discard, "%u");
+	__HAL_AUX_ENTRY("rx_trash_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_trash_discard, "%u");
+	__HAL_AUX_ENTRY("rx_buff_full_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_buff_full_discard, "%u");
+	__HAL_AUX_ENTRY("rx_red_discard_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_red_discard, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_ctrl_err_cnt_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_ctrl_err_cnt, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_data_err_cnt_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_data_err_cnt, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_char1_match_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_char1_match, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_err_sym_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_err_sym, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_column1_match_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_column1_match, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_char2_match_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_char2_match, "%u");
+	__HAL_AUX_ENTRY("rx_local_fault_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_local_fault, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_column2_match_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_xgmii_column2_match, "%u");
+	__HAL_AUX_ENTRY("rx_jettison_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_jettison, "%u");
+	__HAL_AUX_ENTRY("rx_remote_fault_PORT0",
+	    mrpcim_info.xgmac_port[0].rx_remote_fault, "%u");
+
+	__HAL_AUX_ENTRY("tx_ttl_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_ttl_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ttl_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_ttl_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_data_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_mcast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_bcast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ucast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_tagged_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_vld_ip, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_vld_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_icmp_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_icmp, "%llu");
+	__HAL_AUX_ENTRY("tx_tcp_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_rst_tcp_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_rst_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_udp_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_udp, "%llu");
+	__HAL_AUX_ENTRY("tx_parse_error_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_parse_error, "%u");
+	__HAL_AUX_ENTRY("tx_unknown_protocol_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_unknown_protocol, "%u");
+	__HAL_AUX_ENTRY("tx_pause_ctrl_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_pause_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_marker_pdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_marker_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_lacpdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_lacpdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_drop_ip_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_drop_ip, "%u");
+	__HAL_AUX_ENTRY("tx_marker_resp_pdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_marker_resp_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_char2_match_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_xgmii_char2_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_char1_match_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_xgmii_char1_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_column2_match_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_xgmii_column2_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_column1_match_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_xgmii_column1_match, "%u");
+	__HAL_AUX_ENTRY("tx_any_err_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_any_err_frms, "%u");
+	__HAL_AUX_ENTRY("tx_drop_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].tx_drop_frms, "%u");
+	__HAL_AUX_ENTRY("rx_ttl_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_vld_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_offload_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_data_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_offload_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_mcast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_vld_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_bcast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_vld_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ucast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_accepted_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_nucast_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_accepted_nucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_tagged_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_long_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_long_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_usized_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_usized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_osized_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_osized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_frag_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_frag_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_jabber_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_jabber_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_64_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_64_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_65_127_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_65_127_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_128_255_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_128_255_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_256_511_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_256_511_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_512_1023_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_512_1023_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1024_1518_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_1024_1518_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1519_4095_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_1519_4095_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_4096_8191_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_4096_8191_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_8192_max_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_8192_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_gt_max_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ttl_gt_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ip_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_accepted_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_octets_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_err_ip_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_err_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_icmp_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_icmp, "%llu");
+	__HAL_AUX_ENTRY("rx_tcp_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_udp_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_err_tcp_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_err_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_pause_count_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_pause_count, "%llu");
+	__HAL_AUX_ENTRY("rx_pause_ctrl_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_pause_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_unsup_ctrl_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_unsup_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_fcs_err_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_fcs_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_in_rng_len_err_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_in_rng_len_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_out_rng_len_err_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_out_rng_len_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_drop_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_discarded_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_ip_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_drop_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_udp_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_drop_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_marker_pdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_marker_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_lacpdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_lacpdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_unknown_pdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_unknown_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_marker_resp_pdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_marker_resp_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_fcs_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_fcs_discard, "%u");
+	__HAL_AUX_ENTRY("rx_illegal_pdu_frms_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_illegal_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_switch_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_switch_discard, "%u");
+	__HAL_AUX_ENTRY("rx_len_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_len_discard, "%u");
+	__HAL_AUX_ENTRY("rx_rpa_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_rpa_discard, "%u");
+	__HAL_AUX_ENTRY("rx_l2_mgmt_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_l2_mgmt_discard, "%u");
+	__HAL_AUX_ENTRY("rx_rts_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_rts_discard, "%u");
+	__HAL_AUX_ENTRY("rx_trash_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_trash_discard, "%u");
+	__HAL_AUX_ENTRY("rx_buff_full_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_buff_full_discard, "%u");
+	__HAL_AUX_ENTRY("rx_red_discard_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_red_discard, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_ctrl_err_cnt_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_ctrl_err_cnt, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_data_err_cnt_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_data_err_cnt, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_char1_match_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_char1_match, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_err_sym_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_err_sym, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_column1_match_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_column1_match, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_char2_match_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_char2_match, "%u");
+	__HAL_AUX_ENTRY("rx_local_fault_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_local_fault, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_column2_match_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_xgmii_column2_match, "%u");
+	__HAL_AUX_ENTRY("rx_jettison_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_jettison, "%u");
+	__HAL_AUX_ENTRY("rx_remote_fault_PORT1",
+	    mrpcim_info.xgmac_port[1].rx_remote_fault, "%u");
+
+	__HAL_AUX_ENTRY("tx_ttl_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_ttl_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ttl_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_ttl_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_data_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_mcast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_bcast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_ucast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_tagged_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_vld_ip, "%llu");
+	__HAL_AUX_ENTRY("tx_vld_ip_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_vld_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_icmp_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_icmp, "%llu");
+	__HAL_AUX_ENTRY("tx_tcp_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_rst_tcp_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_rst_tcp, "%llu");
+	__HAL_AUX_ENTRY("tx_udp_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_udp, "%llu");
+	__HAL_AUX_ENTRY("tx_parse_error_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_parse_error, "%u");
+	__HAL_AUX_ENTRY("tx_unknown_protocol_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_unknown_protocol, "%u");
+	__HAL_AUX_ENTRY("tx_pause_ctrl_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_pause_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_marker_pdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_marker_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_lacpdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_lacpdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_drop_ip_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_drop_ip, "%u");
+	__HAL_AUX_ENTRY("tx_marker_resp_pdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_marker_resp_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_char2_match_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_xgmii_char2_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_char1_match_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_xgmii_char1_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_column2_match_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_xgmii_column2_match, "%u");
+	__HAL_AUX_ENTRY("tx_xgmii_column1_match_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_xgmii_column1_match, "%u");
+	__HAL_AUX_ENTRY("tx_any_err_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_any_err_frms, "%u");
+	__HAL_AUX_ENTRY("tx_drop_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].tx_drop_frms, "%u");
+	__HAL_AUX_ENTRY("rx_ttl_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_vld_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_offload_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_data_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_offload_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_offload_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_mcast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_vld_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_vld_bcast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_vld_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ucast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_accepted_ucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_nucast_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_accepted_nucast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_tagged_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_tagged_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_long_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_long_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_usized_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_usized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_osized_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_osized_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_frag_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_frag_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_jabber_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_jabber_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_64_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_64_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_65_127_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_65_127_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_128_255_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_128_255_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_256_511_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_256_511_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_512_1023_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_512_1023_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1024_1518_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_1024_1518_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_1519_4095_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_1519_4095_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_4096_8191_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_4096_8191_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_8192_max_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_8192_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ttl_gt_max_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ttl_gt_max_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_accepted_ip_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_accepted_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_ip_octets_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_ip_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_err_ip_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_err_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_icmp_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_icmp, "%llu");
+	__HAL_AUX_ENTRY("rx_tcp_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_udp_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_err_tcp_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_err_tcp, "%llu");
+	__HAL_AUX_ENTRY("rx_pause_count_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_pause_count, "%llu");
+	__HAL_AUX_ENTRY("rx_pause_ctrl_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_pause_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_unsup_ctrl_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_unsup_ctrl_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_fcs_err_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_fcs_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_in_rng_len_err_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_in_rng_len_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_out_rng_len_err_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_out_rng_len_err_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_drop_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_discarded_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_ip_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_drop_ip, "%llu");
+	__HAL_AUX_ENTRY("rx_drop_udp_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_drop_udp, "%llu");
+	__HAL_AUX_ENTRY("rx_marker_pdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_marker_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_lacpdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_lacpdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_unknown_pdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_unknown_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_marker_resp_pdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_marker_resp_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_fcs_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_fcs_discard, "%u");
+	__HAL_AUX_ENTRY("rx_illegal_pdu_frms_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_illegal_pdu_frms, "%u");
+	__HAL_AUX_ENTRY("rx_switch_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_switch_discard, "%u");
+	__HAL_AUX_ENTRY("rx_len_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_len_discard, "%u");
+	__HAL_AUX_ENTRY("rx_rpa_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_rpa_discard, "%u");
+	__HAL_AUX_ENTRY("rx_l2_mgmt_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_l2_mgmt_discard, "%u");
+	__HAL_AUX_ENTRY("rx_rts_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_rts_discard, "%u");
+	__HAL_AUX_ENTRY("rx_trash_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_trash_discard, "%u");
+	__HAL_AUX_ENTRY("rx_buff_full_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_buff_full_discard, "%u");
+	__HAL_AUX_ENTRY("rx_red_discard_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_red_discard, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_ctrl_err_cnt_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_ctrl_err_cnt, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_data_err_cnt_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_data_err_cnt, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_char1_match_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_char1_match, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_err_sym_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_err_sym, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_column1_match_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_column1_match, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_char2_match_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_char2_match, "%u");
+	__HAL_AUX_ENTRY("rx_local_fault_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_local_fault, "%u");
+	__HAL_AUX_ENTRY("rx_xgmii_column2_match_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_xgmii_column2_match, "%u");
+	__HAL_AUX_ENTRY("rx_jettison_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_jettison, "%u");
+	__HAL_AUX_ENTRY("rx_remote_fault_PORT2",
+	    mrpcim_info.xgmac_port[2].rx_remote_fault, "%u");
+
+	__HAL_AUX_ENTRY("tx_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].tx_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_data_octets_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].tx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_mcast_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].tx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_bcast_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].tx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_discarded_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].tx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_errored_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].tx_errored_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_data_octets_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_mcast_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_bcast_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_discarded_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_errored_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_errored_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_unknown_slow_proto_frms_AGGR0",
+	    mrpcim_info.xgmac_aggr[0].rx_unknown_slow_proto_frms, "%llu");
+
+	__HAL_AUX_ENTRY("tx_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].tx_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_data_octets_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].tx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("tx_mcast_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].tx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_bcast_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].tx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_discarded_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].tx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("tx_errored_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].tx_errored_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_data_octets_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_data_octets, "%llu");
+	__HAL_AUX_ENTRY("rx_mcast_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_mcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_bcast_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_bcast_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_discarded_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_discarded_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_errored_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_errored_frms, "%llu");
+	__HAL_AUX_ENTRY("rx_unknown_slow_proto_frms_AGGR1",
+	    mrpcim_info.xgmac_aggr[1].rx_unknown_slow_proto_frms, "%llu");
+
+	__HAL_AUX_ENTRY("xgmac_global_prog_event_gnum0",
+	    mrpcim_info.xgmac_global_prog_event_gnum0, "%llu");
+	__HAL_AUX_ENTRY("xgmac_global_prog_event_gnum1",
+	    mrpcim_info.xgmac_global_prog_event_gnum1, "%llu");
+
+	__HAL_AUX_ENTRY("xgmac_orp_lro_events",
+	    mrpcim_info.xgmac_orp_lro_events, "%llu");
+
+	__HAL_AUX_ENTRY("xgmac_orp_bs_events",
+	    mrpcim_info.xgmac_orp_bs_events, "%llu");
+
+	__HAL_AUX_ENTRY("xgmac_orp_iwarp_events",
+	    mrpcim_info.xgmac_orp_iwarp_events, "%llu");
+
+	__HAL_AUX_ENTRY("xgmac_tx_permitted_frms",
+	    mrpcim_info.xgmac_tx_permitted_frms, "%u");
+
+	__HAL_AUX_ENTRY("xgmac_port2_tx_any_frms",
+	    mrpcim_info.xgmac_port2_tx_any_frms, "%u");
+	__HAL_AUX_ENTRY("xgmac_port1_tx_any_frms",
+	    mrpcim_info.xgmac_port1_tx_any_frms, "%u");
+	__HAL_AUX_ENTRY("xgmac_port0_tx_any_frms",
+	    mrpcim_info.xgmac_port0_tx_any_frms, "%u");
+
+	__HAL_AUX_ENTRY("xgmac_port2_rx_any_frms",
+	    mrpcim_info.xgmac_port2_rx_any_frms, "%u");
+	__HAL_AUX_ENTRY("xgmac_port1_rx_any_frms",
+	    mrpcim_info.xgmac_port1_rx_any_frms, "%u");
+	__HAL_AUX_ENTRY("xgmac_port0_rx_any_frms",
+	    mrpcim_info.xgmac_port0_rx_any_frms, "%u");
+
+	__HAL_AUX_ENTRY_END(bufsize, retsize);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_vpath_ring_dump - Dump vpath ring.
+ * @vpath_handle: Vpath handle.
+ *
+ * Dump vpath ring.
+ */
+vxge_hal_status_e
+vxge_hal_aux_vpath_ring_dump(vxge_hal_vpath_h vpath_handle)
+{
+	u32 i;
+	char buffer[4096];
+	__hal_ring_t *ring;
+	vxge_hal_rxd_h rxdh;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_ring_rxd_1_t *rxd1;
+	vxge_hal_ring_rxd_3_t *rxd3;
+	vxge_hal_ring_rxd_5_t *rxd5;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	ring = (__hal_ring_t *) vpath->ringh;
+
+	vxge_os_println("********* vxge RING DUMP BEGIN **********");
+
+	vxge_os_println("********* vxge RING RXD LIST **********");
+
+	__hal_channel_for_each_dtr(&ring->channel, rxdh, i) {
+
+		(void) vxge_os_snprintf(buffer, sizeof(buffer),
+		    "%d : 0x"VXGE_OS_STXFMT, i, (ptr_t) rxdh);
+
+		vxge_os_println(buffer);
+
+		switch (ring->buffer_mode) {
+		case 1:
+			rxd1 = (vxge_hal_ring_rxd_1_t *) rxdh;
+			(void) vxge_os_snprintf(buffer, sizeof(buffer),
+			    "\thost_control = 0x"VXGE_OS_LLXFMT", "
+			    "control_0 = 0x"VXGE_OS_LLXFMT", "
+			    "control_1 = 0x"VXGE_OS_LLXFMT", "
+			    "buffer0_ptr = 0x"VXGE_OS_LLXFMT,
+			    rxd1->host_control, rxd1->control_0,
+			    rxd1->control_1, rxd1->buffer0_ptr);
+			break;
+		case 3:
+			rxd3 = (vxge_hal_ring_rxd_3_t *) rxdh;
+			(void) vxge_os_snprintf(buffer, sizeof(buffer),
+			    "\thost_control = 0x"VXGE_OS_LLXFMT", "
+			    "control_0 = 0x"VXGE_OS_LLXFMT", "
+			    "control_1 = 0x"VXGE_OS_LLXFMT", "
+			    "buffer0_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "buffer1_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "buffer2_ptr = 0x"VXGE_OS_LLXFMT,
+			    rxd3->host_control, rxd3->control_0,
+			    rxd3->control_1, rxd3->buffer0_ptr,
+			    rxd3->buffer1_ptr, rxd3->buffer2_ptr);
+			break;
+		case 5:
+			rxd5 = (vxge_hal_ring_rxd_5_t *) rxdh;
+			(void) vxge_os_snprintf(buffer, sizeof(buffer),
+			    "\thost_control = 0x%x, "
+			    "control_0 = 0x"VXGE_OS_LLXFMT", "
+			    "control_1 = 0x"VXGE_OS_LLXFMT", "
+			    "control_2 = 0x%x, "
+			    "buffer0_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "buffer1_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "buffer2_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "buffer3_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "buffer4_ptr = 0x"VXGE_OS_LLXFMT,
+			    rxd5->host_control, rxd5->control_0,
+			    rxd5->control_1, rxd5->control_2,
+			    rxd5->buffer0_ptr, rxd5->buffer1_ptr,
+			    rxd5->buffer2_ptr, rxd5->buffer3_ptr,
+			    rxd5->buffer4_ptr);
+			break;
+		default:
+			continue;
+		}
+
+		vxge_os_println(buffer);
+	}
+
+	vxge_os_println("******* vxge RING RXD LIST END **********");
+
+	vxge_os_println("********* vxge RING DUMP END **********");
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_vpath_fifo_dump - Dump vpath fifo.
+ * @vpath_handle: Vpath handle.
+ *
+ * Dump vpath fifo.
+ */
+vxge_hal_status_e
+vxge_hal_aux_vpath_fifo_dump(vxge_hal_vpath_h vpath_handle)
+{
+	u32 i, j;
+	char buffer[4096];
+	__hal_fifo_t *fifo;
+	vxge_hal_txdl_h txdlh;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_fifo_txd_t *txd;
+	__hal_fifo_txdl_priv_t *txdl_priv;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	fifo = (__hal_fifo_t *) vpath->fifoh;
+
+	vxge_os_println("********* vxge FIFO DUMP BEGIN **********");
+
+	vxge_os_println("********* vxge FIFO TXDL LIST **********");
+
+	__hal_channel_for_each_dtr(&fifo->channel, txdlh, j) {
+
+		(void) vxge_os_snprintf(buffer, sizeof(buffer),
+		    "TXDL %d : 0x"VXGE_OS_STXFMT, j, (ptr_t) txdlh);
+
+		vxge_os_println(buffer);
+
+		txdl_priv = VXGE_HAL_FIFO_HAL_PRIV(fifo, txdlh);
+
+		for (i = 0, txd = (vxge_hal_fifo_txd_t *) txdlh;
+		    i < txdl_priv->frags; i++, txd++) {
+
+			(void) vxge_os_snprintf(buffer, sizeof(buffer),
+			    "\tcontrol_0 = 0x"VXGE_OS_LLXFMT", "
+			    "control_1 = 0x"VXGE_OS_LLXFMT", "
+			    "buffer_ptr = 0x"VXGE_OS_LLXFMT", "
+			    "host_control = 0x"VXGE_OS_LLXFMT,
+			    txd->control_0, txd->control_1,
+			    txd->buffer_pointer, txd->host_control);
+
+			vxge_os_println(buffer);
+		}
+
+	}
+
+	vxge_os_println("******* vxge FIFO TXDL LIST END **********");
+
+	vxge_os_println("********* vxge FIFO DUMP END **********");
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_aux_device_dump - Dump driver "about" info and device state.
+ * @devh: HAL device handle.
+ *
+ * Dump driver & device "about" info and device state,
+ * including all BAR0 registers, hardware and software statistics, PCI
+ * configuration space.
+ */
+vxge_hal_status_e
+vxge_hal_aux_device_dump(vxge_hal_device_h devh)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	int retsize;
+	u32 offset, i;
+	u64 retval;
+
+	vxge_assert(hldev->dump_buf != NULL);
+
+	vxge_os_println("********* vxge DEVICE DUMP BEGIN **********");
+
+	status = vxge_hal_aux_about_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
+	    hldev->dump_buf, &retsize);
+	if (status != VXGE_HAL_OK)
+		goto error;
+
+	vxge_os_println(hldev->dump_buf);
+
+	vxge_os_println("******* PCI Config Reg **********");
+
+	status = vxge_hal_aux_pci_config_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
+	    hldev->dump_buf, &retsize);
+	if (status != VXGE_HAL_OK)
+		goto error;
+
+	vxge_os_println(hldev->dump_buf);
+
+	vxge_os_println("******* Legacy Reg **********");
+
+	for (offset = 0; offset < sizeof(vxge_hal_legacy_reg_t); offset += 8) {
+		status = vxge_hal_mgmt_reg_read(devh,
+		    vxge_hal_mgmt_reg_type_legacy, 0, offset, &retval);
+
+		if (status != VXGE_HAL_OK)
+			goto error;
+
+		if (!retval)
+			continue;
+
+		vxge_os_printf("0x%04x 0x%08x%08x", offset,
+		    (u32) (retval >> 32), (u32) retval);
+	}
+	vxge_os_println("\n");
+
+	vxge_os_println("******* TOC Reg *********");
+
+	for (offset = 0; offset < sizeof(vxge_hal_toc_reg_t); offset += 8) {
+		status = vxge_hal_mgmt_reg_read(devh,
+		    vxge_hal_mgmt_reg_type_toc, 0, offset, &retval);
+		if (status != VXGE_HAL_OK)
+			goto error;
+
+		if (!retval)
+			continue;
+
+		vxge_os_printf("0x%04x 0x%08x%08x", offset,
+		    (u32) (retval >> 32), (u32) retval);
+	}
+	vxge_os_println("\n");
+
+	vxge_os_println("******* Common Reg **********");
+
+	for (offset = 0; offset < sizeof(vxge_hal_common_reg_t); offset += 8) {
+		status = vxge_hal_mgmt_reg_read(devh,
+		    vxge_hal_mgmt_reg_type_common, 0, offset, &retval);
+		if (status != VXGE_HAL_OK)
+			goto error;
+
+		if (!retval)
+			continue;
+
+		vxge_os_printf("0x%04x 0x%08x%08x", offset,
+		    (u32) (retval >> 32), (u32) retval);
+	}
+	vxge_os_println("\n");
+
+	for (i = 0; i < VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES; i++) {
+		vxge_os_printf("****** PCI Config Mgmt Reg : %d ********\n", i);
+
+		for (offset = 0; offset < sizeof(vxge_hal_pcicfgmgmt_reg_t);
+		    offset += 8) {
+			status = vxge_hal_mgmt_reg_read(devh,
+			    vxge_hal_mgmt_reg_type_pcicfgmgmt,
+			    i, offset, &retval);
+			if (status != VXGE_HAL_OK)
+				continue;
+
+			if (!retval)
+				continue;
+
+			vxge_os_printf("0x%04x 0x%08x%08x", offset,
+			    (u32) (retval >> 32), (u32) retval);
+		}
+	}
+	vxge_os_println("\n");
+
+	vxge_os_println("******* MRPCIM Reg **********");
+
+	for (offset = 0; offset < sizeof(vxge_hal_mrpcim_reg_t);
+	    offset += 8) {
+		status = vxge_hal_mgmt_reg_read(devh,
+		    vxge_hal_mgmt_reg_type_mrpcim, 0, offset, &retval);
+		if (status != VXGE_HAL_OK)
+			continue;
+
+		if (!retval)
+			continue;
+
+		vxge_os_printf("0x%04x 0x%08x%08x", offset,
+		    (u32) (retval >> 32), (u32) retval);
+	}
+	vxge_os_println("\n");
+
+	for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+		vxge_os_printf("******* SRPCIM Reg : %d **********\n", i);
+
+		for (offset = 0; offset < sizeof(vxge_hal_srpcim_reg_t);
+		    offset += 8) {
+			status = vxge_hal_mgmt_reg_read(devh,
+			    vxge_hal_mgmt_reg_type_srpcim, i, offset, &retval);
+			if (status != VXGE_HAL_OK)
+				continue;
+
+			if (!retval)
+				continue;
+
+			vxge_os_printf("0x%04x 0x%08x%08x", offset,
+			    (u32) (retval >> 32), (u32) retval);
+		}
+	}
+	vxge_os_println("\n");
+
+	for (i = 0; i < VXGE_HAL_TITAN_VPMGMT_REG_SPACES; i++) {
+		vxge_os_printf("******* VPATH MGMT Reg : %d **********\n", i);
+
+		for (offset = 0; offset < sizeof(vxge_hal_vpmgmt_reg_t);
+		    offset += 8) {
+			status = vxge_hal_mgmt_reg_read(devh,
+			    vxge_hal_mgmt_reg_type_vpmgmt, i, offset, &retval);
+			if (status != VXGE_HAL_OK)
+				continue;
+
+			if (!retval)
+				continue;
+
+			vxge_os_printf("0x%04x 0x%08x%08x", offset,
+			    (u32) (retval >> 32), (u32) retval);
+		}
+	}
+	vxge_os_println("\n");
+
+	for (i = 0; i < VXGE_HAL_TITAN_VPATH_REG_SPACES; i++) {
+		vxge_os_printf("******* VPATH Reg : %d **********\n", i);
+
+		for (offset = 0; offset < sizeof(vxge_hal_vpath_reg_t);
+		    offset += 8) {
+			status = vxge_hal_mgmt_reg_read(devh,
+			    vxge_hal_mgmt_reg_type_vpath, i, offset, &retval);
+			if (status != VXGE_HAL_OK)
+				continue;
+
+			if (!retval)
+				continue;
+
+			vxge_os_printf("0x%04x 0x%08x%08x", offset,
+			    (u32) (retval >> 32), (u32) retval);
+		}
+	}
+
+	vxge_os_println("\n");
+
+	status = vxge_hal_aux_stats_mrpcim_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
+	    hldev->dump_buf,
+	    &retsize);
+	if (status == VXGE_HAL_OK) {
+		vxge_os_println("******* MRPCIM Stats **********");
+		vxge_os_println(hldev->dump_buf);
+	}
+
+	vxge_os_println("******* Device Stats **********");
+
+	status = vxge_hal_aux_stats_device_read(hldev, VXGE_HAL_DUMP_BUF_SIZE,
+	    hldev->dump_buf, &retsize);
+	if (status != VXGE_HAL_OK)
+		goto error;
+
+	vxge_os_println(hldev->dump_buf);
+
+	vxge_os_println("********* DEVICE DUMP END **********");
+
+error:
+	return (status);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mm.c b/sys/dev/vxge/vxgehal/vxgehal-mm.c
new file mode 100644
index 000000000000..4a8eb0869fb3
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mm.c
@@ -0,0 +1,553 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * __hal_mempool_grow
+ *
+ * Will resize mempool up to %num_allocate value.
+ */
+static vxge_hal_status_e
+__hal_mempool_grow(
+    vxge_hal_mempool_t *mempool,
+    u32 num_allocate,
+    u32 *num_allocated)
+{
+	u32 i, j, k, item_index, is_last;
+	u32 first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
+	u32 n_items = mempool->items_per_memblock;
+	u32 start_block_idx = mempool->memblocks_allocated;
+	u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
+	__hal_device_t *hldev;
+
+	vxge_assert(mempool != NULL);
+
+	hldev = (__hal_device_t *) mempool->devh;
+
+	vxge_hal_trace_log_mm("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mm(
+	    "mempool = 0x"VXGE_OS_STXFMT", num_allocate = %d, "
+	    "num_allocated = 0x"VXGE_OS_STXFMT, (ptr_t) mempool,
+	    num_allocate, (ptr_t) num_allocated);
+
+	*num_allocated = 0;
+
+	if (end_block_idx > mempool->memblocks_max) {
+		vxge_hal_err_log_mm("%s",
+		    "__hal_mempool_grow: can grow anymore");
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	for (i = start_block_idx; i < end_block_idx; i++) {
+
+		void *the_memblock;
+		vxge_hal_mempool_dma_t *dma_object;
+
+		is_last = ((end_block_idx - 1) == i);
+		dma_object = mempool->memblocks_dma_arr + i;
+
+		/*
+		 * allocate memblock's private part. Each DMA memblock
+		 * has a space allocated for item's private usage upon
+		 * mempool's user request. Each time mempool grows, it will
+		 * allocate new memblock and its private part at once.
+		 * This helps to minimize memory usage a lot.
+		 */
+		mempool->memblocks_priv_arr[i] = vxge_os_malloc(
+		    ((__hal_device_t *) mempool->devh)->header.pdev,
+		    mempool->items_priv_size * n_items);
+		if (mempool->memblocks_priv_arr[i] == NULL) {
+
+			vxge_hal_err_log_mm("memblock_priv[%d]: \
+			    out of virtual memory, "
+			    "requested %d(%d:%d) bytes", i,
+			    mempool->items_priv_size * n_items,
+			    mempool->items_priv_size, n_items);
+			vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+			return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+		}
+
+		vxge_os_memzero(mempool->memblocks_priv_arr[i],
+		    mempool->items_priv_size * n_items);
+
+		/* allocate DMA-capable memblock */
+		mempool->memblocks_arr[i] =
+		    __hal_blockpool_malloc(mempool->devh,
+		    mempool->memblock_size,
+		    &dma_object->addr,
+		    &dma_object->handle,
+		    &dma_object->acc_handle);
+		if (mempool->memblocks_arr[i] == NULL) {
+			vxge_os_free(
+			    ((__hal_device_t *) mempool->devh)->header.pdev,
+			    mempool->memblocks_priv_arr[i],
+			    mempool->items_priv_size * n_items);
+			vxge_hal_err_log_mm("memblock[%d]: \
+			    out of DMA memory", i);
+			vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_OUT_OF_MEMORY);
+			return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+		}
+
+		(*num_allocated)++;
+		mempool->memblocks_allocated++;
+
+		vxge_os_memzero(mempool->memblocks_arr[i],
+		    mempool->memblock_size);
+
+		the_memblock = mempool->memblocks_arr[i];
+
+		/* fill the items hash array */
+		for (j = 0; j < n_items; j++) {
+			item_index = i * n_items + j;
+
+			if (first_time && (item_index >= mempool->items_initial))
+				break;
+
+			mempool->items_arr[item_index] =
+			    ((char *) the_memblock + j *mempool->item_size);
+
+			/* let caller to do more job on each item */
+			if (mempool->item_func_alloc != NULL) {
+				vxge_hal_status_e status;
+
+				if ((status = mempool->item_func_alloc(
+				    mempool,
+				    the_memblock,
+				    i,
+				    dma_object,
+				    mempool->items_arr[item_index],
+				    item_index,
+				    is_last,
+				    mempool->userdata)) != VXGE_HAL_OK) {
+
+					if (mempool->item_func_free != NULL) {
+
+						for (k = 0; k < j; k++) {
+
+							item_index = i * n_items + k;
+
+							(void) mempool->item_func_free(
+							    mempool,
+							    the_memblock,
+							    i, dma_object,
+							    mempool->items_arr[item_index],
+							    item_index, is_last,
+							    mempool->userdata);
+						}
+					}
+
+					vxge_os_free(((__hal_device_t *)
+					    mempool->devh)->header.pdev,
+					    mempool->memblocks_priv_arr[i],
+					    mempool->items_priv_size *
+					    n_items);
+
+					__hal_blockpool_free(mempool->devh,
+					    the_memblock,
+					    mempool->memblock_size,
+					    &dma_object->addr,
+					    &dma_object->handle,
+					    &dma_object->acc_handle);
+
+					(*num_allocated)--;
+					mempool->memblocks_allocated--;
+					return (status);
+				}
+			}
+
+			mempool->items_current = item_index + 1;
+		}
+
+		vxge_hal_info_log_mm(
+		    "memblock%d: allocated %dk, vaddr 0x"VXGE_OS_STXFMT", "
+		    "dma_addr 0x"VXGE_OS_STXFMT,
+		    i, mempool->memblock_size / 1024,
+		    (ptr_t) mempool->memblocks_arr[i], dma_object->addr);
+
+		if (first_time && mempool->items_current ==
+		    mempool->items_initial) {
+			break;
+		}
+	}
+
+	vxge_hal_trace_log_mm("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mempool_create
+ * @memblock_size:
+ * @items_initial:
+ * @items_max:
+ * @item_size:
+ * @item_func:
+ *
+ * This function will create memory pool object. Pool may grow but will
+ * never shrink. Pool consists of number of dynamically allocated blocks
+ * with size enough to hold %items_initial number of items. Memory is
+ * DMA-able but client must map/unmap before interoperating with the device.
+ * See also: vxge_os_dma_map(), vxge_hal_dma_unmap(), vxge_hal_status_e {}.
+ */
+vxge_hal_mempool_t *
+vxge_hal_mempool_create(
+    vxge_hal_device_h devh,
+    u32 memblock_size,
+    u32 item_size,
+    u32 items_priv_size,
+    u32 items_initial,
+    u32 items_max,
+    vxge_hal_mempool_item_f item_func_alloc,
+    vxge_hal_mempool_item_f item_func_free,
+    void *userdata)
+{
+	vxge_hal_status_e status;
+	u32 memblocks_to_allocate;
+	vxge_hal_mempool_t *mempool;
+	__hal_device_t *hldev;
+	u32 allocated;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_mm("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mm(
+	    "devh = 0x"VXGE_OS_STXFMT", memblock_size = %d, item_size = %d, "
+	    "items_priv_size = %d, items_initial = %d, items_max = %d, "
+	    "item_func_alloc = 0x"VXGE_OS_STXFMT", "
+	    "item_func_free = 0x"VXGE_OS_STXFMT", "
+	    "userdata = 0x"VXGE_OS_STXFMT, (ptr_t) devh,
+	    memblock_size, item_size, items_priv_size,
+	    items_initial, items_max, (ptr_t) item_func_alloc,
+	    (ptr_t) item_func_free, (ptr_t) userdata);
+
+	if (memblock_size < item_size) {
+		vxge_hal_err_log_mm(
+		    "memblock_size %d < item_size %d: misconfiguration",
+		    memblock_size, item_size);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (NULL);
+	}
+
+	mempool = (vxge_hal_mempool_t *) vxge_os_malloc(
+	    ((__hal_device_t *) devh)->header.pdev, sizeof(vxge_hal_mempool_t));
+	if (mempool == NULL) {
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	vxge_os_memzero(mempool, sizeof(vxge_hal_mempool_t));
+
+	mempool->devh = devh;
+	mempool->memblock_size = memblock_size;
+	mempool->items_max = items_max;
+	mempool->items_initial = items_initial;
+	mempool->item_size = item_size;
+	mempool->items_priv_size = items_priv_size;
+	mempool->item_func_alloc = item_func_alloc;
+	mempool->item_func_free = item_func_free;
+	mempool->userdata = userdata;
+
+	mempool->memblocks_allocated = 0;
+
+	if (memblock_size != VXGE_OS_HOST_PAGE_SIZE)
+		mempool->dma_flags = VXGE_OS_DMA_CACHELINE_ALIGNED;
+
+#if defined(VXGE_HAL_DMA_CONSISTENT)
+	mempool->dma_flags |= VXGE_OS_DMA_CONSISTENT;
+#else
+	mempool->dma_flags |= VXGE_OS_DMA_STREAMING;
+#endif
+
+	mempool->items_per_memblock = memblock_size / item_size;
+
+	mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
+	    mempool->items_per_memblock;
+
+	/* allocate array of memblocks */
+	mempool->memblocks_arr = (void **)vxge_os_malloc(
+	    ((__hal_device_t *) mempool->devh)->header.pdev,
+	    sizeof(void *) * mempool->memblocks_max);
+	if (mempool->memblocks_arr == NULL) {
+		vxge_hal_mempool_destroy(mempool);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	vxge_os_memzero(mempool->memblocks_arr,
+	    sizeof(void *) * mempool->memblocks_max);
+
+	/* allocate array of private parts of items per memblocks */
+	mempool->memblocks_priv_arr = (void **)vxge_os_malloc(
+	    ((__hal_device_t *) mempool->devh)->header.pdev,
+	    sizeof(void *) * mempool->memblocks_max);
+	if (mempool->memblocks_priv_arr == NULL) {
+		vxge_hal_mempool_destroy(mempool);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	vxge_os_memzero(mempool->memblocks_priv_arr,
+	    sizeof(void *) * mempool->memblocks_max);
+
+	/* allocate array of memblocks DMA objects */
+	mempool->memblocks_dma_arr =
+	    (vxge_hal_mempool_dma_t *) vxge_os_malloc(
+	    ((__hal_device_t *) mempool->devh)->header.pdev,
+	    sizeof(vxge_hal_mempool_dma_t) * mempool->memblocks_max);
+
+	if (mempool->memblocks_dma_arr == NULL) {
+		vxge_hal_mempool_destroy(mempool);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	vxge_os_memzero(mempool->memblocks_dma_arr,
+	    sizeof(vxge_hal_mempool_dma_t) * mempool->memblocks_max);
+
+	/* allocate hash array of items */
+	mempool->items_arr = (void **)vxge_os_malloc(
+	    ((__hal_device_t *) mempool->devh)->header.pdev,
+	    sizeof(void *) * mempool->items_max);
+	if (mempool->items_arr == NULL) {
+		vxge_hal_mempool_destroy(mempool);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	vxge_os_memzero(mempool->items_arr,
+	    sizeof(void *) * mempool->items_max);
+
+	mempool->shadow_items_arr = (void **)vxge_os_malloc(
+	    ((__hal_device_t *) mempool->devh)->header.pdev,
+	    sizeof(void *) * mempool->items_max);
+	if (mempool->shadow_items_arr == NULL) {
+		vxge_hal_mempool_destroy(mempool);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+	vxge_os_memzero(mempool->shadow_items_arr,
+	    sizeof(void *) * mempool->items_max);
+
+	/* calculate initial number of memblocks */
+	memblocks_to_allocate = (mempool->items_initial +
+	    mempool->items_per_memblock - 1) /
+	    mempool->items_per_memblock;
+
+	vxge_hal_info_log_mm("allocating %d memblocks, "
+	    "%d items per memblock", memblocks_to_allocate,
+	    mempool->items_per_memblock);
+
+	/* pre-allocate the mempool */
+	status = __hal_mempool_grow(mempool, memblocks_to_allocate, &allocated);
+	vxge_os_memcpy(mempool->shadow_items_arr, mempool->items_arr,
+	    sizeof(void *) * mempool->items_max);
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_mempool_destroy(mempool);
+		vxge_hal_trace_log_mm("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (NULL);
+	}
+
+	vxge_hal_info_log_mm(
+	    "total: allocated %dk of DMA-capable memory",
+	    mempool->memblock_size * allocated / 1024);
+
+	vxge_hal_trace_log_mm("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (mempool);
+}
+
+/*
+ * vxge_hal_mempool_destroy
+ */
+void
+vxge_hal_mempool_destroy(
+    vxge_hal_mempool_t *mempool)
+{
+	u32 i, j, item_index;
+	__hal_device_t *hldev;
+
+	vxge_assert(mempool != NULL);
+
+	hldev = (__hal_device_t *) mempool->devh;
+
+	vxge_hal_trace_log_mm("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mm("mempool = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) mempool);
+
+	for (i = 0; i < mempool->memblocks_allocated; i++) {
+		vxge_hal_mempool_dma_t *dma_object;
+
+		vxge_assert(mempool->memblocks_arr[i]);
+		vxge_assert(mempool->memblocks_dma_arr + i);
+
+		dma_object = mempool->memblocks_dma_arr + i;
+
+		for (j = 0; j < mempool->items_per_memblock; j++) {
+			item_index = i * mempool->items_per_memblock + j;
+
+			/* to skip last partially filled(if any) memblock */
+			if (item_index >= mempool->items_current)
+				break;
+
+			/* let caller to do more job on each item */
+			if (mempool->item_func_free != NULL) {
+
+				mempool->item_func_free(mempool,
+				    mempool->memblocks_arr[i],
+				    i, dma_object,
+				    mempool->shadow_items_arr[item_index],
+				    item_index, /* unused */ -1,
+				    mempool->userdata);
+			}
+		}
+
+		vxge_os_free(hldev->header.pdev,
+		    mempool->memblocks_priv_arr[i],
+		    mempool->items_priv_size * mempool->items_per_memblock);
+
+		__hal_blockpool_free(hldev,
+		    mempool->memblocks_arr[i],
+		    mempool->memblock_size,
+		    &dma_object->addr,
+		    &dma_object->handle,
+		    &dma_object->acc_handle);
+	}
+
+	if (mempool->items_arr) {
+		vxge_os_free(hldev->header.pdev,
+		    mempool->items_arr, sizeof(void *) * mempool->items_max);
+	}
+
+	if (mempool->shadow_items_arr) {
+		vxge_os_free(hldev->header.pdev,
+		    mempool->shadow_items_arr,
+		    sizeof(void *) * mempool->items_max);
+	}
+
+	if (mempool->memblocks_dma_arr) {
+		vxge_os_free(hldev->header.pdev,
+		    mempool->memblocks_dma_arr,
+		    sizeof(vxge_hal_mempool_dma_t) *
+		    mempool->memblocks_max);
+	}
+
+	if (mempool->memblocks_priv_arr) {
+		vxge_os_free(hldev->header.pdev,
+		    mempool->memblocks_priv_arr,
+		    sizeof(void *) * mempool->memblocks_max);
+	}
+
+	if (mempool->memblocks_arr) {
+		vxge_os_free(hldev->header.pdev,
+		    mempool->memblocks_arr,
+		    sizeof(void *) * mempool->memblocks_max);
+	}
+
+	vxge_os_free(hldev->header.pdev,
+	    mempool, sizeof(vxge_hal_mempool_t));
+
+	vxge_hal_trace_log_mm("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_check_alignment - Check buffer alignment	and	calculate the
+ * "misaligned"	portion.
+ * @dma_pointer: DMA address of	the	buffer.
+ * @size: Buffer size, in bytes.
+ * @alignment: Alignment "granularity" (see	below),	in bytes.
+ * @copy_size: Maximum number of bytes to "extract"	from the buffer
+ * (in order to	spost it as	a separate scatter-gather entry). See below.
+ *
+ * Check buffer	alignment and calculate	"misaligned" portion, if exists.
+ * The buffer is considered	aligned	if its address is multiple of
+ * the specified @alignment. If	this is	the	case,
+ * vxge_hal_check_alignment() returns zero.
+ * Otherwise, vxge_hal_check_alignment()	uses the last argument,
+ * @copy_size,
+ * to calculate	the	size to	"extract" from the buffer. The @copy_size
+ * may or may not be equal @alignment. The difference between these	two
+ * arguments is	that the @alignment is used to make the decision: aligned
+ * or not aligned. While the @copy_size	is used	to calculate the portion
+ * of the buffer to "extract", i.e.	to post	as a separate entry in the
+ * transmit descriptor.	For example, the combination
+ * @alignment = 8 and @copy_size = 64 will work	okay on	AMD Opteron boxes.
+ *
+ * Note: @copy_size should be a	multiple of @alignment.	In many	practical
+ * cases @copy_size and	@alignment will	probably be equal.
+ *
+ * See also: vxge_hal_fifo_txdl_buffer_set_aligned().
+ */
+u32
+vxge_hal_check_alignment(
+    dma_addr_t dma_pointer,
+    u32 size,
+    u32 alignment,
+    u32 copy_size)
+{
+	u32 misaligned_size;
+
+	misaligned_size = (int)(dma_pointer & (alignment - 1));
+	if (!misaligned_size) {
+		return (0);
+	}
+
+	if (size > copy_size) {
+		misaligned_size = (int)(dma_pointer & (copy_size - 1));
+		misaligned_size = copy_size - misaligned_size;
+	} else {
+		misaligned_size = size;
+	}
+
+	return (misaligned_size);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mm.h b/sys/dev/vxge/vxgehal/vxgehal-mm.h
new file mode 100644
index 000000000000..549b814d11ad
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mm.h
@@ -0,0 +1,206 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_MM_H
+#define	VXGE_HAL_MM_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef void *vxge_hal_mempool_h;
+
+/*
+ * struct vxge_hal_mempool_dma_t - Represents DMA objects passed to the
+ * caller.
+ */
+typedef struct vxge_hal_mempool_dma_t {
+	dma_addr_t			addr;
+	pci_dma_h			handle;
+	pci_dma_acc_h			acc_handle;
+} vxge_hal_mempool_dma_t;
+
+/*
+ * vxge_hal_mempool_item_f  - Mempool item alloc/free callback
+ * @mempoolh: Memory pool handle.
+ * @memblock: Address of memory block
+ * @memblock_index: Index of memory block
+ * @item: Item that gets allocated or freed.
+ * @index: Item's index in the memory pool.
+ * @is_last: True, if this item is the last one in the pool; false - otherwise.
+ * userdata: Per-pool user context.
+ *
+ * Memory pool allocation/deallocation callback.
+ */
+typedef vxge_hal_status_e (*vxge_hal_mempool_item_f) (
+	vxge_hal_mempool_h	mempoolh,
+	void			*memblock,
+	u32			memblock_index,
+	vxge_hal_mempool_dma_t	*dma_object,
+	void			*item,
+	u32			index,
+	u32			is_last,
+	void			*userdata);
+
+/*
+ * struct vxge_hal_mempool_t - Memory pool.
+ */
+typedef struct vxge_hal_mempool_t {
+	vxge_hal_mempool_item_f	item_func_alloc;
+	vxge_hal_mempool_item_f	item_func_free;
+	void			*userdata;
+	void			**memblocks_arr;
+	void			**memblocks_priv_arr;
+	vxge_hal_mempool_dma_t	*memblocks_dma_arr;
+	vxge_hal_device_h	devh;
+	u32			memblock_size;
+	u32			memblocks_max;
+	u32			memblocks_allocated;
+	u32			item_size;
+	u32			items_max;
+	u32			items_initial;
+	u32			items_current;
+	u32			items_per_memblock;
+	u32			dma_flags;
+	void			**items_arr;
+	void			**shadow_items_arr;
+	u32			items_priv_size;
+} vxge_hal_mempool_t;
+
+/*
+ * __hal_mempool_item_count - Returns number of items in the mempool
+ */
+static inline u32
+/* LINTED */
+__hal_mempool_item_count(
+    vxge_hal_mempool_t *mempool)
+{
+	return (mempool->items_current);
+}
+
+/*
+ * __hal_mempool_item - Returns pointer to the item in the mempool
+ * items array.
+ */
+static inline void *
+/* LINTED */
+__hal_mempool_item(
+    vxge_hal_mempool_t *mempool,
+    u32 items_index)
+{
+	return (mempool->items_arr[items_index]);
+}
+
+/*
+ * __hal_mempool_item_priv - will return pointer on per item private space
+ */
+static inline void*
+/* LINTED */
+__hal_mempool_item_priv(
+    vxge_hal_mempool_t *mempool,
+    u32 memblock_idx,
+    void *item,
+    u32 *memblock_item_idx)
+{
+	ptrdiff_t offset;
+	void *memblock = mempool->memblocks_arr[memblock_idx];
+
+	vxge_assert(memblock);
+
+	/* LINTED */
+	offset = (u32) ((u8 *) item - (u8 *) memblock);
+	vxge_assert(offset >= 0 && (u32) offset < mempool->memblock_size);
+
+	(*memblock_item_idx) = (u32) offset / mempool->item_size;
+	vxge_assert((*memblock_item_idx) < mempool->items_per_memblock);
+
+	return ((u8 *) mempool->memblocks_priv_arr[memblock_idx] +
+	    (*memblock_item_idx) * mempool->items_priv_size);
+}
+
+/*
+ * __hal_mempool_items_arr - will return pointer to the items array in the
+ * mempool.
+ */
+static inline void *
+/* LINTED */
+__hal_mempool_items_arr(
+    vxge_hal_mempool_t *mempool)
+{
+	return (mempool->items_arr);
+}
+
+/*
+ * __hal_mempool_memblock - will return pointer to the memblock in the
+ * mempool memblocks array.
+ */
+static inline void *
+/* LINTED */
+__hal_mempool_memblock(
+    vxge_hal_mempool_t *mempool,
+    u32 memblock_idx)
+{
+	vxge_assert(mempool->memblocks_arr[memblock_idx]);
+	return (mempool->memblocks_arr[memblock_idx]);
+}
+
+/*
+ * __hal_mempool_memblock_dma - will return pointer to the dma block
+ * corresponds to the memblock(identified by memblock_idx) in the mempool.
+ */
+static inline vxge_hal_mempool_dma_t *
+/* LINTED */
+__hal_mempool_memblock_dma(
+    vxge_hal_mempool_t *mempool,
+    u32 memblock_idx)
+{
+	return (mempool->memblocks_dma_arr + memblock_idx);
+}
+
+vxge_hal_mempool_t *
+vxge_hal_mempool_create(
+    vxge_hal_device_h devh,
+    u32 memblock_size,
+    u32 item_size,
+    u32 private_size,
+    u32 items_initial,
+    u32 items_max,
+    vxge_hal_mempool_item_f item_func_alloc,
+    vxge_hal_mempool_item_f item_func_free,
+    void *userdata);
+
+void
+vxge_hal_mempool_destroy(
+    vxge_hal_mempool_t *mempool);
+
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_MM_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mrpcim-reg.h b/sys/dev/vxge/vxgehal/vxgehal-mrpcim-reg.h
new file mode 100644
index 000000000000..0c8d68d12246
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mrpcim-reg.h
@@ -0,0 +1,10615 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_MRPCIM_REGS_H
+#define	VXGE_HAL_MRPCIM_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_mrpcim_reg_t {
+
+/* 0x00000 */	u64	g3fbct_int_status;
+#define	VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT		    mBIT(0)
+/* 0x00008 */	u64	g3fbct_int_mask;
+/* 0x00010 */	u64	g3fbct_err_reg;
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR		    mBIT(4)
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC		    mBIT(5)
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC	    mBIT(6)
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC	    mBIT(7)
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_SECC		    mBIT(29)
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC	    mBIT(30)
+#define	VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC	    mBIT(31)
+/* 0x00018 */	u64	g3fbct_err_mask;
+/* 0x00020 */	u64	g3fbct_err_alarm;
+/* 0x00028 */	u64	g3fbct_config0;
+#define	VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY_RPATH(val)   vBIT(val, 5, 3)
+#define	VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_G3FBCT_CONFIG0_REFRESH_PER(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_G3FBCT_CONFIG0_TRC(val)		    vBIT(val, 35, 5)
+#define	VXGE_HAL_G3FBCT_CONFIG0_TRRD(val)		    vBIT(val, 44, 4)
+#define	VXGE_HAL_G3FBCT_CONFIG0_TFAW(val)		    vBIT(val, 50, 6)
+#define	VXGE_HAL_G3FBCT_CONFIG0_RD_FIFO_THR(val)	    vBIT(val, 58, 6)
+/* 0x00030 */	u64	g3fbct_config1;
+#define	VXGE_HAL_G3FBCT_CONFIG1_BIC_THR(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_G3FBCT_CONFIG1_BIC_OFF			    mBIT(15)
+#define	VXGE_HAL_G3FBCT_CONFIG1_IGNORE_BEM		    mBIT(23)
+#define	VXGE_HAL_G3FBCT_CONFIG1_RD_SAMPLING(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_G3FBCT_CONFIG1_CMD_START_PHASE		    mBIT(39)
+#define	VXGE_HAL_G3FBCT_CONFIG1_BIC_HI_THR(val)		    vBIT(val, 43, 5)
+#define	VXGE_HAL_G3FBCT_CONFIG1_BIC_MODE(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_G3FBCT_CONFIG1_ECC_ENABLE(val)		    vBIT(val, 57, 7)
+/* 0x00038 */	u64	g3fbct_config2;
+#define	VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_ENABLE(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_VALUE(val)	    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3FBCT_CONFIG2_ARBITER_CTRL(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_G3FBCT_CONFIG2_DEFINE_CAD		    mBIT(31)
+#define	VXGE_HAL_G3FBCT_CONFIG2_DEFINE_NOP_AD		    mBIT(39)
+#define	VXGE_HAL_G3FBCT_CONFIG2_LAST_CADD(val)		    vBIT(val, 43, 13)
+/* 0x00040 */	u64	g3fbct_init0;
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_BAD(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_WL(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_DLL			    mBIT(23)
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_TM			    mBIT(39)
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_CL(val)		    vBIT(val, 44, 4)
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_BT			    mBIT(55)
+#define	VXGE_HAL_G3FBCT_INIT0_MRS_BL(val)		    vBIT(val, 62, 2)
+/* 0x00048 */	u64	g3fbct_init1;
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_BAD(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_AD_TER		    mBIT(15)
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_ID			    mBIT(23)
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_RON			    mBIT(39)
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_AL			    mBIT(47)
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_TWR(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_G3FBCT_INIT1_EMRS_DQ_TER(val)		    vBIT(val, 62, 2)
+/* 0x00050 */	u64	g3fbct_init2;
+#define	VXGE_HAL_G3FBCT_INIT2_EMRS_DR_STR(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3FBCT_INIT2_START_INI			    mBIT(15)
+#define	VXGE_HAL_G3FBCT_INIT2_POWER_UP_DELAY(val)	    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3FBCT_INIT2_ACTIVE_CMD_DELAY(val)	    vBIT(val, 40, 24)
+/* 0x00058 */	u64	g3fbct_init3;
+#define	VXGE_HAL_G3FBCT_INIT3_TRP_DELAY(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TMRD_DELAY(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TWR2PRE_DELAY(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TRD2PRE_DELAY(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TRCDR_DELAY(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TRCDW_DELAY(val)		    vBIT(val, 40, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TWR2RD_DELAY(val)		    vBIT(val, 48, 8)
+#define	VXGE_HAL_G3FBCT_INIT3_TRD2WR_DELAY(val)		    vBIT(val, 56, 8)
+/* 0x00060 */ u64 g3fbct_init4;
+#define	VXGE_HAL_G3FBCT_INIT4_TRFC_DELAY(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3FBCT_INIT4_REFRESH_BURSTS(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_G3FBCT_INIT4_CKE_INIT_VAL		    mBIT(31)
+#define	VXGE_HAL_G3FBCT_INIT4_VENDOR_ID(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3FBCT_INIT4_OOO_DEPTH(val)		    vBIT(val, 42, 6)
+#define	VXGE_HAL_G3FBCT_INIT4_ICTRL_INIT_DONE		    mBIT(55)
+#define	VXGE_HAL_G3FBCT_INIT4_IOCAL_WAIT_DISABLE	    mBIT(63)
+/* 0x00068 */ u64 g3fbct_init5;
+#define	VXGE_HAL_G3FBCT_INIT5_TRAS_DELAY(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_G3FBCT_INIT5_TVID_DELAY(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD(val)		    vBIT(val, 16, 8)
+#define	VXGE_HAL_G3FBCT_INIT5_TRD_APRE2CMD(val)		    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD_CON(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3FBCT_INIT5_GDDR3_DLL_DELAY(val)	    vBIT(val, 40, 24)
+/* 0x00070 */	u64	g3fbct_dll_training1;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING1_DLL_TRA_DATA00(val)   vBIT(val, 0, 64)
+/* 0x00078 */	u64	g3fbct_dll_training2;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING2_DLL_TRA_DATA01(val)   vBIT(val, 0, 64)
+/* 0x00080 */	u64	g3fbct_dll_training3;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING3_DLL_TRA_DATA10(val)   vBIT(val, 0, 64)
+/* 0x00088 */	u64	g3fbct_dll_training4;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING4_DLL_TRA_DATA11(val)   vBIT(val, 0, 64)
+/* 0x00090 */	u64	g3fbct_dll_training6;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING6_DLL_TRA_DATA20(val)   vBIT(val, 0, 64)
+/* 0x00098 */	u64	g3fbct_dll_training7;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING7_DLL_TRA_DATA21(val)   vBIT(val, 0, 64)
+/* 0x000a0 */	u64	g3fbct_dll_training8;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING8_DLL_TRA_DATA30(val)   vBIT(val, 0, 64)
+/* 0x000a8 */	u64	g3fbct_dll_training9;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING9_DLL_TRA_DATA31(val)   vBIT(val, 0, 64)
+/* 0x000b0 */	u64	g3fbct_dll_training5;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_RADD(val)	    vBIT(val, 2, 14)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD0(val)    vBIT(val, 21, 11)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD1(val)    vBIT(val, 37, 11)
+/* 0x000b8 */	u64	g3fbct_dll_training10;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_TP_READS(val)    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_SAMPLES(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_LOOPS(val)	    vBIT(val, 18, 14)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_PASS_CNT(val)    vBIT(val, 33, 7)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_STEP(val)	    vBIT(val, 41, 7)
+/* 0x000c0 */	u64	g3fbct_dll_training11;
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48)
+#define	VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2)
+/* 0x000c8 */	u64	g3fbct_init6;
+#define	VXGE_HAL_G3FBCT_INIT6_TWR_APRE2RD_DELAY(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TWR_APRE2WR_DELAY(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TWR_APRE2PRE_DELAY(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TWR_APRE2ACT_DELAY(val)	    vBIT(val, 28, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TRD_APRE2RD_DELAY(val)	    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TRD_APRE2WR_DELAY(val)	    vBIT(val, 44, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TRD_APRE2PRE_DELAY(val)	    vBIT(val, 52, 4)
+#define	VXGE_HAL_G3FBCT_INIT6_TRD_APRE2ACT_DELAY(val)	    vBIT(val, 60, 4)
+/* 0x000d0 */	u64	g3fbct_test0;
+#define	VXGE_HAL_G3FBCT_TEST0_TEST_START_RADD(val)	    vBIT(val, 2, 14)
+#define	VXGE_HAL_G3FBCT_TEST0_TEST_END_RADD(val)	    vBIT(val, 18, 14)
+#define	VXGE_HAL_G3FBCT_TEST0_TEST_START_CADD(val)	    vBIT(val, 37, 11)
+#define	VXGE_HAL_G3FBCT_TEST0_TEST_END_CADD(val)	    vBIT(val, 53, 11)
+/* 0x000d8 */	u64	g3fbct_test01;
+#define	VXGE_HAL_G3FBCT_TEST01_TEST_BANK(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3FBCT_TEST01_TEST_CTRL(val)		    vBIT(val, 12, 4)
+#define	VXGE_HAL_G3FBCT_TEST01_TEST_MODE		    mBIT(23)
+#define	VXGE_HAL_G3FBCT_TEST01_TEST_GO			    mBIT(31)
+#define	VXGE_HAL_G3FBCT_TEST01_TEST_DONE		    mBIT(39)
+#define	VXGE_HAL_G3FBCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val)  vBIT(val, 40, 16)
+#define	VXGE_HAL_G3FBCT_TEST01_TEST_DATA_ADDR		    mBIT(63)
+/* 0x000e0 */	u64	g3fbct_test1;
+#define	VXGE_HAL_G3FBCT_TEST1_TX_TEST_DATA(val)		    vBIT(val, 0, 64)
+/* 0x000e8 */	u64	g3fbct_test2;
+#define	VXGE_HAL_G3FBCT_TEST2_TX_TEST_DATA(val)		    vBIT(val, 0, 64)
+/* 0x000f0 */	u64	g3fbct_test11;
+#define	VXGE_HAL_G3FBCT_TEST11_TX_TEST_DATA1(val)	    vBIT(val, 0, 64)
+/* 0x000f8 */	u64	g3fbct_test21;
+#define	VXGE_HAL_G3FBCT_TEST21_TX_TEST_DATA1(val)	    vBIT(val, 0, 64)
+/* 0x00100 */	u64	g3fbct_test3;
+#define	VXGE_HAL_G3FBCT_TEST3_ECC_DEC_RX_TEST_DATA(val)	    vBIT(val, 0, 64)
+/* 0x00108 */	u64	g3fbct_test4;
+#define	VXGE_HAL_G3FBCT_TEST4_ECC_DEC_RX_TEST_DATA(val)	    vBIT(val, 0, 64)
+/* 0x00110 */	u64	g3fbct_test31;
+#define	VXGE_HAL_G3FBCT_TEST31_ECC_DEC_RX_TEST_DATA1(val)   vBIT(val, 0, 64)
+/* 0x00118 */	u64	g3fbct_test41;
+#define	VXGE_HAL_G3FBCT_TEST41_ECC_DEC_RX_TEST_DATA1(val)   vBIT(val, 0, 64)
+/* 0x00120 */	u64	g3fbct_test5;
+#define	VXGE_HAL_G3FBCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
+/* 0x00128 */	u64	g3fbct_test6;
+#define	VXGE_HAL_G3FBCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
+/* 0x00130 */	u64	g3fbct_test51;
+#define	VXGE_HAL_G3FBCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
+							    vBIT(val, 0, 64)
+/* 0x00138 */	u64	g3fbct_test61;
+#define	VXGE_HAL_G3FBCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
+							    vBIT(val, 0, 64)
+/* 0x00140 */	u64	g3fbct_test7;
+#define	VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14)
+#define	VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11)
+#define	VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8)
+/* 0x00148 */	u64	g3fbct_test71;
+#define	VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14)
+#define	VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11)
+#define	VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8)
+	u8	unused001b0[0x001b0 - 0x00150];
+
+/* 0x001b0 */	u64	g3fbct_loop_back;
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_TDATA(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_MODE			    mBIT(39)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_GO			    mBIT(47)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_DONE			    mBIT(55)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_IDLE_VAL(val)	    vBIT(val, 56, 8)
+/* 0x001b8 */	u64	g3fbct_loop_back1;
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_START_VAL(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_END_VAL(val)	    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_IDLE_VAL(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_START_VAL(val)	    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_END_VAL(val)	    vBIT(val, 33, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_STEPS(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MIN_FILTER(val)	    vBIT(val, 49, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MAX_FILTER(val)	    vBIT(val, 57, 7)
+/* 0x001c0 */	u64	g3fbct_loop_back2;
+#define	VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MIN_FILTER(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MAX_FILTER(val)	    vBIT(val, 9, 7)
+/* 0x001c8 */	u64	g3fbct_loop_back3;
+#define	VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_RESULT(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_WDLL_RESULT(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_MON_RESULT(val)\
+							    vBIT(val, 16, 8)
+/* 0x001d0 */	u64	g3fbct_loop_back4;
+#define	VXGE_HAL_G3FBCT_LOOP_BACK4_LBCTRL_IO_PASS_FAILN(val) vBIT(val, 0, 32)
+/* 0x001d8 */	u64	g3fbct_loop_back5;
+#define	VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_START_IO_VAL(val)   vBIT(val, 1, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_END_IO_VAL(val)	    vBIT(val, 9, 7)
+	u8	unused00200[0x00200 - 0x001e0];
+
+/* 0x00200 */	u64	g3fbct_loop_back_rdll[4];
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MIN_VAL(val)  vBIT(val, 1, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MAX_VAL(val)  vBIT(val, 9, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MIN_VAL(val) vBIT(val, 17, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MAX_VAL(val) vBIT(val, 25, 7)
+/* 0x00220 */	u64	g3fbct_loop_back_wdll[4];
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MIN_VAL(val)  vBIT(val, 1, 7)
+#define	VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MAX_VAL(val)  vBIT(val, 9, 7)
+/* 0x00240 */	u64	g3fbct_tran_wrd_cnt;
+#define	VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val)	    vBIT(val, 32, 32)
+/* 0x00248 */	u64	g3fbct_tran_ap_cnt;
+#define	VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_G3FBCT_TRAN_AP_CNT_UPDATE		    mBIT(39)
+/* 0x00250 */	u64	g3fbct_g3bist;
+#define	VXGE_HAL_G3FBCT_G3BIST_DISABLE_MAIN		    mBIT(7)
+#define	VXGE_HAL_G3FBCT_G3BIST_DISABLE_ICTRL		    mBIT(15)
+#define	VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_MAIN(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_ICTRL(val)	    vBIT(val, 29, 3)
+	u8	unused00a00[0x00a00 - 0x00258];
+
+/* 0x00a00 */	u64	wrdma_int_status;
+#define	VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT	    mBIT(0)
+#define	VXGE_HAL_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT    mBIT(1)
+#define	VXGE_HAL_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT mBIT(2)
+#define	VXGE_HAL_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT    mBIT(3)
+#define	VXGE_HAL_WRDMA_INT_STATUS_RDA_ERR_RDA_INT	    mBIT(6)
+#define	VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT mBIT(8)
+#define	VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT mBIT(9)
+#define	VXGE_HAL_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT	    mBIT(12)
+#define	VXGE_HAL_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT	    mBIT(13)
+#define	VXGE_HAL_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT	    mBIT(14)
+#define	VXGE_HAL_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT	    mBIT(15)
+#define	VXGE_HAL_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT	    mBIT(16)
+#define	VXGE_HAL_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT	    mBIT(17)
+/* 0x00a08 */	u64	wrdma_int_mask;
+/* 0x00a10 */	u64	rc_alarm_reg;
+#define	VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR		    mBIT(0)
+#define	VXGE_HAL_RC_ALARM_REG_FTC_SM_PHASE_ERR		    mBIT(1)
+#define	VXGE_HAL_RC_ALARM_REG_BTDWM_SM_ERR		    mBIT(2)
+#define	VXGE_HAL_RC_ALARM_REG_BTC_SM_ERR		    mBIT(3)
+#define	VXGE_HAL_RC_ALARM_REG_BTDCM_SM_ERR		    mBIT(4)
+#define	VXGE_HAL_RC_ALARM_REG_BTDRM_SM_ERR		    mBIT(5)
+#define	VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR	    mBIT(6)
+#define	VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR	    mBIT(8)
+#define	VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR	    mBIT(9)
+#define	VXGE_HAL_RC_ALARM_REG_RMM_SM_ERR		    mBIT(10)
+#define	VXGE_HAL_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR	    mBIT(12)
+/* 0x00a18 */	u64	rc_alarm_mask;
+/* 0x00a20 */	u64	rc_alarm_alarm;
+/* 0x00a28 */	u64	rxdrm_sm_err_reg;
+#define	VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(n)		    mBIT(n)
+/* 0x00a30 */	u64	rxdrm_sm_err_mask;
+/* 0x00a38 */	u64	rxdrm_sm_err_alarm;
+/* 0x00a40 */	u64	rxdcm_sm_err_reg;
+#define	VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(n)		    mBIT(n)
+/* 0x00a48 */	u64	rxdcm_sm_err_mask;
+/* 0x00a50 */	u64	rxdcm_sm_err_alarm;
+/* 0x00a58 */	u64	rxdwm_sm_err_reg;
+#define	VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(n)		    mBIT(n)
+/* 0x00a60 */	u64	rxdwm_sm_err_mask;
+/* 0x00a68 */	u64	rxdwm_sm_err_alarm;
+/* 0x00a70 */	u64	rda_err_reg;
+#define	VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM		    mBIT(0)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_MISC_ERR		    mBIT(1)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_PCIX_ERR		    mBIT(2)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR		    mBIT(3)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR		    mBIT(4)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR		    mBIT(5)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR		    mBIT(6)
+#define	VXGE_HAL_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR		    mBIT(7)
+/* 0x00a78 */	u64	rda_err_mask;
+/* 0x00a80 */	u64	rda_err_alarm;
+/* 0x00a88 */	u64	rda_ecc_db_reg;
+#define	VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(n)		    mBIT(n)
+/* 0x00a90 */	u64	rda_ecc_db_mask;
+/* 0x00a98 */	u64	rda_ecc_db_alarm;
+/* 0x00aa0 */	u64	rda_ecc_sg_reg;
+#define	VXGE_HAL_RDA_ECC_SG_REG_RDA_RXD_ERR(n)		    mBIT(n)
+/* 0x00aa8 */	u64	rda_ecc_sg_mask;
+/* 0x00ab0 */	u64	rda_ecc_sg_alarm;
+/* 0x00ab8 */	u64	rqa_err_reg;
+#define	VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM		    mBIT(0)
+/* 0x00ac0 */	u64	rqa_err_mask;
+/* 0x00ac8 */	u64	rqa_err_alarm;
+/* 0x00ad0 */	u64	frf_alarm_reg;
+#define	VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n)	    mBIT(n)
+/* 0x00ad8 */	u64	frf_alarm_mask;
+/* 0x00ae0 */	u64	frf_alarm_alarm;
+/* 0x00ae8 */	u64	rocrc_alarm_reg;
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB	    mBIT(0)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG	    mBIT(1)
+#define	VXGE_HAL_ROCRC_ALARM_REG_NOA_NMA_SM_ERR		    mBIT(2)
+#define	VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB	    mBIT(3)
+#define	VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG	    mBIT(4)
+#define	VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB	    mBIT(5)
+#define	VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG	    mBIT(6)
+#define	VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB	    mBIT(11)
+#define	VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG	    mBIT(12)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR	    mBIT(13)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR	    mBIT(14)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR	    mBIT(15)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR   mBIT(16)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR	    mBIT(17)
+#define	VXGE_HAL_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR	    mBIT(18)
+#define	VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW	    mBIT(19)
+#define	VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW	    mBIT(20)
+#define	VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW	    mBIT(21)
+#define	VXGE_HAL_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR	    mBIT(22)
+/* 0x00af0 */	u64	rocrc_alarm_mask;
+/* 0x00af8 */	u64	rocrc_alarm_alarm;
+/* 0x00b00 */	u64	wde0_alarm_reg;
+#define	VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR		    mBIT(0)
+#define	VXGE_HAL_WDE0_ALARM_REG_WDE0_PRM_SM_ERR		    mBIT(1)
+#define	VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_SM_ERR		    mBIT(2)
+#define	VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_CMD_ERR		    mBIT(3)
+#define	VXGE_HAL_WDE0_ALARM_REG_WDE0_PCR_SM_ERR		    mBIT(4)
+/* 0x00b08 */	u64	wde0_alarm_mask;
+/* 0x00b10 */	u64	wde0_alarm_alarm;
+/* 0x00b18 */	u64	wde1_alarm_reg;
+#define	VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR		    mBIT(0)
+#define	VXGE_HAL_WDE1_ALARM_REG_WDE1_PRM_SM_ERR		    mBIT(1)
+#define	VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_SM_ERR		    mBIT(2)
+#define	VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_CMD_ERR		    mBIT(3)
+#define	VXGE_HAL_WDE1_ALARM_REG_WDE1_PCR_SM_ERR		    mBIT(4)
+/* 0x00b20 */	u64	wde1_alarm_mask;
+/* 0x00b28 */	u64	wde1_alarm_alarm;
+/* 0x00b30 */	u64	wde2_alarm_reg;
+#define	VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR		    mBIT(0)
+#define	VXGE_HAL_WDE2_ALARM_REG_WDE2_PRM_SM_ERR		    mBIT(1)
+#define	VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_SM_ERR		    mBIT(2)
+#define	VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_CMD_ERR		    mBIT(3)
+#define	VXGE_HAL_WDE2_ALARM_REG_WDE2_PCR_SM_ERR		    mBIT(4)
+/* 0x00b38 */	u64	wde2_alarm_mask;
+/* 0x00b40 */	u64	wde2_alarm_alarm;
+/* 0x00b48 */	u64	wde3_alarm_reg;
+#define	VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR		    mBIT(0)
+#define	VXGE_HAL_WDE3_ALARM_REG_WDE3_PRM_SM_ERR		    mBIT(1)
+#define	VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_SM_ERR		    mBIT(2)
+#define	VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_CMD_ERR		    mBIT(3)
+#define	VXGE_HAL_WDE3_ALARM_REG_WDE3_PCR_SM_ERR		    mBIT(4)
+/* 0x00b50 */	u64	wde3_alarm_mask;
+/* 0x00b58 */	u64	wde3_alarm_alarm;
+/* 0x00b60 */	u64	rc_cfg;
+#define	VXGE_HAL_RC_CFG_RXD_ERR_MASK(val)		    vBIT(val, 0, 4)
+#define	VXGE_HAL_RC_CFG_RXD_RD_RO			    mBIT(12)
+#define	VXGE_HAL_RC_CFG_FIXED_BUFFER_SIZE		    mBIT(13)
+#define	VXGE_HAL_RC_CFG_ENABLE_VP_CFG_CHANGE_WHILE_BUSY	    mBIT(14)
+#define	VXGE_HAL_RC_CFG_PRESERVE_BUFFER_SIZE		    mBIT(15)
+/* 0x00b68 */	u64	ecc_cfg;
+#define	VXGE_HAL_ECC_CFG_RXD_RC_ECC_ENABLE_N		    mBIT(0)
+#define	VXGE_HAL_ECC_CFG_RXD_RHS_ECC_ENABLE_N		    mBIT(1)
+#define	VXGE_HAL_ECC_CFG_NOA_IMMM_ECC_ENABLE_N		    mBIT(4)
+#define	VXGE_HAL_ECC_CFG_UDQ_UMQM_ECC_ENABLE_N		    mBIT(5)
+#define	VXGE_HAL_ECC_CFG_RCBM_CQB_ECC_ENABLE_N		    mBIT(7)
+/* 0x00b70 */	u64	rxd_cfg_1bm;
+#define	VXGE_HAL_RXD_CFG_1BM_QW_SIZE(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG_1BM_QW2WRITE(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_RXD_CFG_1BM_HCW_QWOFF(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG_1BM_RTH_VAL_QWOFF(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W0OFF(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W1OFF(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_BOFF(val)		    vBIT(val, 61, 3)
+/* 0x00b78 */	u64	rxd_cfg1_1bm;
+#define	VXGE_HAL_RXD_CFG1_1BM_BUFF1_SIZE_QWOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_QWOFF(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_BOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG1_1BM_RTH_BUCKET_DATA_QWOF(val)	    vBIT(val, 61, 3)
+/* 0x00b80 */	u64	rxd_cfg2_1bm;
+#define	VXGE_HAL_RXD_CFG2_1BM_RTH_BUCKET_DATA_BOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG2_1BM_BUFF1_SIZE_WOFF(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_BOFF(val)	    vBIT(val, 61, 3)
+/* 0x00b88 */	u64	rxd_cfg3_1bm;
+#define	VXGE_HAL_RXD_CFG3_1BM_BUFF1_PTR_QWOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_QWOFF(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG3_1BM_HEAD_OWN_BIT_IDX(val)	    vBIT(val, 57, 3)
+#define	VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BIT_IDX(val)	    vBIT(val, 61, 3)
+/* 0x00b90 */	u64	rxd_cfg4_1bm;
+#define	VXGE_HAL_RXD_CFG4_1BM_L3C_QWOFF(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG4_1BM_L3C_WOFF(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_RXD_CFG4_1BM_L4C_QWOFF(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG4_1BM_L4C_WOFF(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_RXD_CFG4_1BM_VTAG_QWOFF(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_RXD_CFG4_1BM_VTAG_WOFF(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_BOFF(val)	    vBIT(val, 61, 3)
+/* 0x00b98 */	u64	rxd_cfg_3bm;
+#define	VXGE_HAL_RXD_CFG_3BM_QW_SIZE(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG_3BM_QW2WRITE(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_RXD_CFG_3BM_HCW_QWOFF(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG_3BM_RTH_VAL_QWOFF(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W0OFF(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W1OFF(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_BOFF(val)		    vBIT(val, 61, 3)
+/* 0x00ba0 */	u64	rxd_cfg1_3bm;
+#define	VXGE_HAL_RXD_CFG1_3BM_BUFF1_SIZE_QWOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG1_3BM_BUFF2_SIZE_QWOFF(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_RXD_CFG1_3BM_BUFF3_SIZE_QWOFF(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_QWOFF(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_BOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG1_3BM_RTH_BUCKET_DATA_QWOF(val)	    vBIT(val, 61, 3)
+/* 0x00ba8 */	u64	rxd_cfg2_3bm;
+#define	VXGE_HAL_RXD_CFG2_3BM_RTH_BUCKET_DATA_BOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG2_3BM_BUFF1_SIZE_WOFF(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_RXD_CFG2_3BM_BUFF2_SIZE_WOFF(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_RXD_CFG2_3BM_BUFF3_SIZE_WOFF(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_BOFF(val)	    vBIT(val, 61, 3)
+/* 0x00bb0 */	u64	rxd_cfg3_3bm;
+#define	VXGE_HAL_RXD_CFG3_3BM_BUFF1_PTR_QWOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG3_3BM_BUFF2_PTR_QWOFF(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_RXD_CFG3_3BM_BUFF3_PTR_QWOFF(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_QWOFF(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG3_3BM_HEAD_OWN_BIT_IDX(val)	    vBIT(val, 57, 3)
+#define	VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BIT_IDX(val)	    vBIT(val, 61, 3)
+/* 0x00bb8 */	u64	rxd_cfg4_3bm;
+#define	VXGE_HAL_RXD_CFG4_3BM_L3C_QWOFF(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG4_3BM_L3C_WOFF(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_RXD_CFG4_3BM_L4C_QWOFF(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG4_3BM_L4C_WOFF(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_RXD_CFG4_3BM_VTAG_QWOFF(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_RXD_CFG4_3BM_VTAG_WOFF(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_BOFF(val)	    vBIT(val, 61, 3)
+/* 0x00bc0 */	u64	rxd_cfg_5bm;
+#define	VXGE_HAL_RXD_CFG_5BM_QW_SIZE(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG_5BM_QW2WRITE(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_RXD_CFG_5BM_HCW_QWOFF(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG_5BM_RTH_VAL_QWOFF(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W0OFF(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W1OFF(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_BOFF(val)		    vBIT(val, 61, 3)
+/* 0x00bc8 */	u64	rxd_cfg1_5bm;
+#define	VXGE_HAL_RXD_CFG1_5BM_BUFF1_SIZE_QWOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_BUFF2_SIZE_QWOFF(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_BUFF3_SIZE_QWOFF(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_BUFF4_SIZE_QWOFF(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_BUFF5_SIZE_QWOFF(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_QWOFF(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_BOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG1_5BM_RTH_BUCKET_DATA_QWOF(val)	    vBIT(val, 61, 3)
+/* 0x00bd0 */	u64	rxd_cfg2_5bm;
+#define	VXGE_HAL_RXD_CFG2_5BM_RTH_BUCKET_DATA_BOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG2_5BM_BUFF1_SIZE_WOFF(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_RXD_CFG2_5BM_BUFF2_SIZE_WOFF(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_RXD_CFG2_5BM_BUFF3_SIZE_WOFF(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_RXD_CFG2_5BM_BUFF4_SIZE_WOFF(val)	    vBIT(val, 38, 2)
+#define	VXGE_HAL_RXD_CFG2_5BM_BUFF5_SIZE_WOFF(val)	    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_BOFF(val)	    vBIT(val, 61, 3)
+/* 0x00bd8 */	u64	rxd_cfg3_5bm;
+#define	VXGE_HAL_RXD_CFG3_5BM_BUFF1_PTR_QWOFF(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_BUFF2_PTR_QWOFF(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_BUFF3_PTR_QWOFF(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_BUFF4_PTR_QWOFF(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_BUFF5_PTR_QWOFF(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_QWOFF(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_HEAD_OWN_BIT_IDX(val)	    vBIT(val, 57, 3)
+#define	VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BIT_IDX(val)	    vBIT(val, 61, 3)
+/* 0x00be0 */	u64	rxd_cfg4_5bm;
+#define	VXGE_HAL_RXD_CFG4_5BM_L3C_QWOFF(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_RXD_CFG4_5BM_L3C_WOFF(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_RXD_CFG4_5BM_L4C_QWOFF(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_RXD_CFG4_5BM_L4C_WOFF(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_RXD_CFG4_5BM_VTAG_QWOFF(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_RXD_CFG4_5BM_VTAG_WOFF(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_QWOFF(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_BOFF(val)	    vBIT(val, 61, 3)
+/* 0x00be8 */	u64	rx_w_round_robin_0;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vBIT(val, 59, 5)
+/* 0x00bf0 */	u64	rx_w_round_robin_1;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) vBIT(val, 59, 5)
+/* 0x00bf8 */	u64	rx_w_round_robin_2;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) vBIT(val, 59, 5)
+/* 0x00c00 */	u64	rx_w_round_robin_3;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) vBIT(val, 59, 5)
+/* 0x00c08 */	u64	rx_w_round_robin_4;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) vBIT(val, 59, 5)
+/* 0x00c10 */	u64	rx_w_round_robin_5;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) vBIT(val, 59, 5)
+/* 0x00c18 */	u64	rx_w_round_robin_6;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) vBIT(val, 59, 5)
+/* 0x00c20 */	u64	rx_w_round_robin_7;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) vBIT(val, 59, 5)
+/* 0x00c28 */	u64	rx_w_round_robin_8;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) vBIT(val, 59, 5)
+/* 0x00c30 */	u64	rx_w_round_robin_9;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) vBIT(val, 59, 5)
+/* 0x00c38 */	u64	rx_w_round_robin_10;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) vBIT(val, 59, 5)
+/* 0x00c40 */	u64	rx_w_round_robin_11;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) vBIT(val, 59, 5)
+/* 0x00c48 */	u64	rx_w_round_robin_12;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) vBIT(val, 59, 5)
+/* 0x00c50 */	u64	rx_w_round_robin_13;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) vBIT(val, 59, 5)
+/* 0x00c58 */	u64	rx_w_round_robin_14;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) vBIT(val, 59, 5)
+/* 0x00c60 */	u64	rx_w_round_robin_15;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) vBIT(val, 59, 5)
+/* 0x00c68 */	u64	rx_w_round_robin_16;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) vBIT(val, 59, 5)
+/* 0x00c70 */	u64	rx_w_round_robin_17;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) vBIT(val, 59, 5)
+/* 0x00c78 */	u64	rx_w_round_robin_18;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) vBIT(val, 59, 5)
+/* 0x00c80 */	u64	rx_w_round_robin_19;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) vBIT(val, 59, 5)
+/* 0x00c88 */	u64	rx_w_round_robin_20;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) vBIT(val, 59, 5)
+/* 0x00c90 */	u64	rx_w_round_robin_21;
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) vBIT(val, 19, 5)
+/* 0x00c98 */	u64	rx_queue_priority_0;
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x00ca0 */	u64	rx_queue_priority_1;
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val)    vBIT(val, 59, 5)
+/* 0x00ca8 */	u64	rx_queue_priority_2;
+#define	VXGE_HAL_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val)    vBIT(val, 3, 5)
+	u8	unused00cc8[0x00cc8 - 0x00cb0];
+
+/* 0x00cc8 */	u64	replication_queue_priority;
+#define	VXGE_HAL_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val)\
+							    vBIT(val, 59, 5)
+/* 0x00cd0 */	u64	rx_queue_select;
+#define	VXGE_HAL_RX_QUEUE_SELECT_NUMBER(n)		    mBIT(n)
+#define	VXGE_HAL_RX_QUEUE_SELECT_ENABLE_CODE		    mBIT(15)
+#define	VXGE_HAL_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY   mBIT(23)
+/* 0x00cd8 */	u64	rqa_vpbp_ctrl;
+#define	VXGE_HAL_RQA_VPBP_CTRL_WR_XON_DIS		    mBIT(15)
+#define	VXGE_HAL_RQA_VPBP_CTRL_ROCRC_DIS		    mBIT(23)
+#define	VXGE_HAL_RQA_VPBP_CTRL_TXPE_DIS	mBIT(31)
+/* 0x00ce0 */	u64	rx_multi_cast_ctrl;
+#define	VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_DIS	    mBIT(0)
+#define	VXGE_HAL_RX_MULTI_CAST_CTRL_FRM_DROP_DIS	    mBIT(1)
+#define	VXGE_HAL_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) vBIT(val, 2, 30)
+#define	VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val)	    vBIT(val, 32, 32)
+/* 0x00ce8 */	u64	wde_prm_ctrl;
+#define	VXGE_HAL_WDE_PRM_CTRL_SPAV_THRESHOLD(val)	    vBIT(val, 2, 10)
+#define	VXGE_HAL_WDE_PRM_CTRL_SPLIT_THRESHOLD(val)	    vBIT(val, 18, 14)
+#define	VXGE_HAL_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW		    mBIT(32)
+#define	VXGE_HAL_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY	    mBIT(33)
+#define	VXGE_HAL_WDE_PRM_CTRL_FB_ROW_SIZE(val)		    vBIT(val, 46, 2)
+/* 0x00cf0 */	u64	noa_ctrl;
+#define	VXGE_HAL_NOA_CTRL_FRM_PRTY_QUOTA(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_NOA_CTRL_NON_FRM_PRTY_QUOTA(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_NOA_CTRL_IGNORE_KDFC_IF_STATUS		    mBIT(16)
+#define	VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val)	    vBIT(val, 37, 4)
+#define	VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val)	    vBIT(val, 45, 4)
+#define	VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val)	    vBIT(val, 53, 4)
+#define	VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val)	    vBIT(val, 60, 4)
+/* 0x00cf8 */	u64	phase_cfg;
+#define	VXGE_HAL_PHASE_CFG_QCC_WR_PHASE_EN		    mBIT(0)
+#define	VXGE_HAL_PHASE_CFG_QCC_RD_PHASE_EN		    mBIT(3)
+#define	VXGE_HAL_PHASE_CFG_IMMM_WR_PHASE_EN		    mBIT(7)
+#define	VXGE_HAL_PHASE_CFG_IMMM_RD_PHASE_EN		    mBIT(11)
+#define	VXGE_HAL_PHASE_CFG_UMQM_WR_PHASE_EN		    mBIT(15)
+#define	VXGE_HAL_PHASE_CFG_UMQM_RD_PHASE_EN		    mBIT(19)
+#define	VXGE_HAL_PHASE_CFG_RCBM_WR_PHASE_EN		    mBIT(23)
+#define	VXGE_HAL_PHASE_CFG_RCBM_RD_PHASE_EN		    mBIT(27)
+#define	VXGE_HAL_PHASE_CFG_RXD_RC_WR_PHASE_EN		    mBIT(31)
+#define	VXGE_HAL_PHASE_CFG_RXD_RC_RD_PHASE_EN		    mBIT(35)
+#define	VXGE_HAL_PHASE_CFG_RXD_RHS_WR_PHASE_EN		    mBIT(39)
+#define	VXGE_HAL_PHASE_CFG_RXD_RHS_RD_PHASE_EN		    mBIT(43)
+/* 0x00d00 */	u64	rcq_bypq_cfg;
+#define	VXGE_HAL_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val)	    vBIT(val, 10, 22)
+#define	VXGE_HAL_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val)	    vBIT(val, 39, 9)
+#define	VXGE_HAL_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val)	    vBIT(val, 55, 9)
+	u8	unused00e00[0x00e00 - 0x00d08];
+
+/* 0x00e00 */	u64	doorbell_int_status;
+#define	VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT mBIT(7)
+#define	VXGE_HAL_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT mBIT(15)
+/* 0x00e08 */	u64	doorbell_int_mask;
+/* 0x00e10 */	u64	kdfc_err_reg;
+#define	VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM	    mBIT(23)
+#define	VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1	    mBIT(32)
+#define	VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR	    mBIT(39)
+/* 0x00e18 */	u64	kdfc_err_mask;
+/* 0x00e20 */	u64	kdfc_err_reg_alarm;
+#define	VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR    mBIT(7)
+#define	VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR    mBIT(15)
+#define	VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM  mBIT(23)
+#define	VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1    mBIT(32)
+#define	VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR	    mBIT(39)
+/* 0x00e28 */	u64	usdc_err_reg;
+#define	VXGE_HAL_USDC_ERR_REG_USDC_FIFO_ECC_SG_ERR	    mBIT(4)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_WA_ECC_SG_ERR	    mBIT(5)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_CA_ECC_SG_ERR	    mBIT(6)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_SA_ECC_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_FIFO_ECC_DB_ERR	    mBIT(12)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_WA_ECC_DB_ERR	    mBIT(13)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_CA_ECC_DB_ERR	    mBIT(14)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_SA_ECC_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_USDC_SM_ERR_ALARM	    mBIT(23)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_USDC_MISC_ERR_0	    mBIT(30)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_USDC_MISC_ERR_1	    mBIT(31)
+#define	VXGE_HAL_USDC_ERR_REG_USDC_USDC_PCI_ERR		    mBIT(39)
+/* 0x00e30 */	u64	usdc_err_mask;
+/* 0x00e38 */	u64	usdc_err_reg_alarm;
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_FIFO_ECC_SG_ERR    mBIT(4)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_WA_ECC_SG_ERR	    mBIT(5)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_CA_ECC_SG_ERR	    mBIT(6)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_SA_ECC_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_FIFO_ECC_DB_ERR    mBIT(12)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_WA_ECC_DB_ERR	    mBIT(13)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_CA_ECC_DB_ERR	    mBIT(14)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_SA_ECC_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_SM_ERR_ALARM  mBIT(23)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_MISC_ERR_0    mBIT(30)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_MISC_ERR_1    mBIT(31)
+#define	VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_PCI_ERR	    mBIT(39)
+/* 0x00e40 */	u64	kdfc_vp_partition_0;
+#define	VXGE_HAL_KDFC_VP_PARTITION_0_ENABLE		    mBIT(0)
+#define	VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_0(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_0(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_1(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_1(val)	    vBIT(val, 49, 15)
+/* 0x00e48 */	u64	kdfc_vp_partition_1;
+#define	VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_2(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_2(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_3(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_3(val)	    vBIT(val, 49, 15)
+/* 0x00e50 */	u64	kdfc_vp_partition_2;
+#define	VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_4(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_4(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_5(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_5(val)	    vBIT(val, 49, 15)
+/* 0x00e58 */	u64	kdfc_vp_partition_3;
+#define	VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_6(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_6(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_7(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_7(val)	    vBIT(val, 49, 15)
+/* 0x00e60 */	u64	kdfc_vp_partition_4;
+#define	VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_8(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_9(val)	    vBIT(val, 49, 15)
+/* 0x00e68 */	u64	kdfc_vp_partition_5;
+#define	VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_10(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_11(val)	    vBIT(val, 49, 15)
+/* 0x00e70 */	u64	kdfc_vp_partition_6;
+#define	VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_12(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_13(val)	    vBIT(val, 49, 15)
+/* 0x00e78 */	u64	kdfc_vp_partition_7;
+#define	VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_14(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_15(val)	    vBIT(val, 49, 15)
+/* 0x00e80 */	u64	kdfc_vp_partition_8;
+#define	VXGE_HAL_KDFC_VP_PARTITION_8_LENGTH_16(val)	    vBIT(val, 17, 15)
+/* 0x00e88 */	u64	kdfc_w_round_robin_0;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x00e90 */	u64	kdfc_w_round_robin_1;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_10(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_11(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_12(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_13(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_14(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_15(val)	    vBIT(val, 59, 5)
+/* 0x00e98 */	u64	kdfc_w_round_robin_2;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_16(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_17(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_18(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_19(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_20(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_21(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_22(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_23(val)	    vBIT(val, 59, 5)
+/* 0x00ea0 */	u64	kdfc_w_round_robin_3;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_24(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_25(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_26(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_27(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_28(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_29(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_30(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_31(val)	    vBIT(val, 59, 5)
+/* 0x00ea8 */	u64	kdfc_w_round_robin_4;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_32(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_33(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_34(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_35(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_36(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_37(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_38(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_39(val)	    vBIT(val, 59, 5)
+/* 0x00eb0 */	u64	kdfc_w_round_robin_5;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_40(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_41(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_42(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_43(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_44(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_45(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_46(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_47(val)	    vBIT(val, 59, 5)
+/* 0x00eb8 */	u64	kdfc_w_round_robin_6;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_48(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_49(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_50(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_51(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_52(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_53(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_54(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_55(val)	    vBIT(val, 59, 5)
+/* 0x00ec0 */	u64	kdfc_w_round_robin_7;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_56(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_57(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_58(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_59(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_60(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_61(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_62(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_63(val)	    vBIT(val, 59, 5)
+/* 0x00ec8 */	u64	kdfc_w_round_robin_8;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_64(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_65(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_66(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_67(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_68(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_69(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_70(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_71(val)	    vBIT(val, 59, 5)
+/* 0x00ed0 */	u64	kdfc_w_round_robin_9;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_72(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_73(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_74(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_75(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_76(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_77(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_78(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_79(val)	    vBIT(val, 59, 5)
+/* 0x00ed8 */	u64	kdfc_w_round_robin_10;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_80(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_81(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_82(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_83(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_84(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_85(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_86(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_87(val)	    vBIT(val, 59, 5)
+/* 0x00ee0 */	u64	kdfc_w_round_robin_11;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_88(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_89(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_90(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_91(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_92(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_93(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_94(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_95(val)	    vBIT(val, 59, 5)
+/* 0x00ee8 */	u64	kdfc_w_round_robin_12;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_96(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_97(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_98(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_99(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_100(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_101(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_102(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_103(val)	    vBIT(val, 59, 5)
+/* 0x00ef0 */	u64	kdfc_w_round_robin_13;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_104(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_105(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_106(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_107(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_108(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_109(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_110(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_111(val)	    vBIT(val, 59, 5)
+/* 0x00ef8 */	u64	kdfc_w_round_robin_14;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_112(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_113(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_114(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_115(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_116(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_117(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_118(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_119(val)	    vBIT(val, 59, 5)
+/* 0x00f00 */	u64	kdfc_w_round_robin_15;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_120(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_121(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_122(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_123(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_124(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_125(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_126(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_127(val)	    vBIT(val, 59, 5)
+/* 0x00f08 */	u64	kdfc_w_round_robin_16;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_128(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_129(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_130(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_131(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_132(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_133(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_134(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_135(val)	    vBIT(val, 59, 5)
+/* 0x00f10 */	u64	kdfc_w_round_robin_17;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_136(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_137(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_138(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_139(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_140(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_141(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_142(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_143(val)	    vBIT(val, 59, 5)
+/* 0x00f18 */	u64	kdfc_w_round_robin_18;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_144(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_145(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_146(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_147(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_148(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_149(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_150(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_151(val)	    vBIT(val, 59, 5)
+/* 0x00f20 */	u64	kdfc_w_round_robin_19;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_19_NUMBER_152(val)	    vBIT(val, 3, 5)
+/* 0x00f28 */	u64	kdfc_w_round_robin_20;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x00f30 */	u64	kdfc_w_round_robin_21;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_10(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_11(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_12(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_13(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_14(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_15(val)	    vBIT(val, 59, 5)
+/* 0x00f38 */	u64	kdfc_w_round_robin_22;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_16(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_17(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_18(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_19(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_20(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_21(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_22(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_23(val)	    vBIT(val, 59, 5)
+/* 0x00f40 */	u64	kdfc_w_round_robin_23;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_24(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_25(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_26(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_27(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_28(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_29(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_30(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_31(val)	    vBIT(val, 59, 5)
+/* 0x00f48 */	u64	kdfc_w_round_robin_24;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_32(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_33(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_34(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_35(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_36(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_37(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_38(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_39(val)	    vBIT(val, 59, 5)
+/* 0x00f50 */	u64	kdfc_w_round_robin_25;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_40(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_41(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_42(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_43(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_44(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_45(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_46(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_47(val)	    vBIT(val, 59, 5)
+/* 0x00f58 */	u64	kdfc_w_round_robin_26;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_48(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_49(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_50(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_51(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_52(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_53(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_54(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_55(val)	    vBIT(val, 59, 5)
+/* 0x00f60 */	u64	kdfc_w_round_robin_27;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_56(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_57(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_58(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_59(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_60(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_61(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_62(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_63(val)	    vBIT(val, 59, 5)
+/* 0x00f68 */	u64	kdfc_w_round_robin_28;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_64(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_65(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_66(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_67(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_68(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_69(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_70(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_71(val)	    vBIT(val, 59, 5)
+/* 0x00f70 */	u64	kdfc_w_round_robin_29;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_72(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_73(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_74(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_75(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_76(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_77(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_78(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_79(val)	    vBIT(val, 59, 5)
+/* 0x00f78 */	u64	kdfc_w_round_robin_30;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_80(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_81(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_82(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_83(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_84(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_85(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_86(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_87(val)	    vBIT(val, 59, 5)
+/* 0x00f80 */	u64	kdfc_w_round_robin_31;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_88(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_89(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_90(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_91(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_92(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_93(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_94(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_95(val)	    vBIT(val, 59, 5)
+/* 0x00f88 */	u64	kdfc_w_round_robin_32;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_96(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_97(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_98(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_99(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_100(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_101(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_102(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_103(val)	    vBIT(val, 59, 5)
+/* 0x00f90 */	u64	kdfc_w_round_robin_33;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_104(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_105(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_106(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_107(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_108(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_109(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_110(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_111(val)	    vBIT(val, 59, 5)
+/* 0x00f98 */	u64	kdfc_w_round_robin_34;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_112(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_113(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_114(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_115(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_116(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_117(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_118(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_119(val)	    vBIT(val, 59, 5)
+/* 0x00fa0 */	u64	kdfc_w_round_robin_35;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_120(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_121(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_122(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_123(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_124(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_125(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_126(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_127(val)	    vBIT(val, 59, 5)
+/* 0x00fa8 */	u64	kdfc_w_round_robin_36;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_128(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_129(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_130(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_131(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_132(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_133(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_134(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_135(val)	    vBIT(val, 59, 5)
+/* 0x00fb0 */	u64	kdfc_w_round_robin_37;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_136(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_137(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_138(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_139(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_140(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_141(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_142(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_143(val)	    vBIT(val, 59, 5)
+/* 0x00fb8 */	u64	kdfc_w_round_robin_38;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_144(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_145(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_146(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_147(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_148(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_149(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_150(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_151(val)	    vBIT(val, 59, 5)
+/* 0x00fc0 */	u64	kdfc_w_round_robin_39;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_39_NUMBER_152(val)	    vBIT(val, 3, 5)
+/* 0x00fc8 */	u64	kdfc_w_round_robin_40;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x00fd0 */	u64	kdfc_w_round_robin_41;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_10(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_11(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_12(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_13(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_14(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_15(val)	    vBIT(val, 59, 5)
+/* 0x00fd8 */	u64	kdfc_w_round_robin_42;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_16(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_17(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_18(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_19(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_20(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_21(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_22(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_23(val)	    vBIT(val, 59, 5)
+/* 0x00fe0 */	u64	kdfc_w_round_robin_43;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_24(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_25(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_26(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_27(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_28(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_29(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_30(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_31(val)	    vBIT(val, 59, 5)
+/* 0x00fe8 */	u64	kdfc_w_round_robin_44;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_32(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_33(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_34(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_35(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_36(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_37(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_38(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_39(val)	    vBIT(val, 59, 5)
+/* 0x00ff0 */	u64	kdfc_w_round_robin_45;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_40(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_41(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_42(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_43(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_44(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_45(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_46(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_47(val)	    vBIT(val, 59, 5)
+/* 0x00ff8 */	u64	kdfc_w_round_robin_46;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_48(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_49(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_50(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_51(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_52(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_53(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_54(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_55(val)	    vBIT(val, 59, 5)
+/* 0x01000 */	u64	kdfc_w_round_robin_47;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_56(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_57(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_58(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_59(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_60(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_61(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_62(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_63(val)	    vBIT(val, 59, 5)
+/* 0x01008 */	u64	kdfc_w_round_robin_48;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_64(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_65(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_66(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_67(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_68(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_69(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_70(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_71(val)	    vBIT(val, 59, 5)
+/* 0x01010 */	u64	kdfc_w_round_robin_49;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_72(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_73(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_74(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_75(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_76(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_77(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_78(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_79(val)	    vBIT(val, 59, 5)
+/* 0x01018 */	u64	kdfc_w_round_robin_50;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_80(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_81(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_82(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_83(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_84(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_85(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_86(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_87(val)	    vBIT(val, 59, 5)
+/* 0x01020 */	u64	kdfc_w_round_robin_51;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_88(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_89(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_90(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_91(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_92(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_93(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_94(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_95(val)	    vBIT(val, 59, 5)
+/* 0x01028 */	u64	kdfc_w_round_robin_52;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_96(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_97(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_98(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_99(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_100(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_101(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_102(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_103(val)	    vBIT(val, 59, 5)
+/* 0x01030 */	u64	kdfc_w_round_robin_53;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_104(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_105(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_106(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_107(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_108(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_109(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_110(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_111(val)	    vBIT(val, 59, 5)
+/* 0x01038 */	u64	kdfc_w_round_robin_54;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_112(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_113(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_114(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_115(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_116(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_117(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_118(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_119(val)	    vBIT(val, 59, 5)
+/* 0x01040 */	u64	kdfc_w_round_robin_55;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_120(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_121(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_122(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_123(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_124(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_125(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_126(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_127(val)	    vBIT(val, 59, 5)
+/* 0x01048 */	u64	kdfc_w_round_robin_56;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_128(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_129(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_130(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_131(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_132(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_133(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_134(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_135(val)	    vBIT(val, 59, 5)
+/* 0x01050 */	u64	kdfc_w_round_robin_57;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_136(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_137(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_138(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_139(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_140(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_141(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_142(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_143(val)	    vBIT(val, 59, 5)
+/* 0x01058 */	u64	kdfc_w_round_robin_58;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_144(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_145(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_146(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_147(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_148(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_149(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_150(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_151(val)	    vBIT(val, 59, 5)
+/* 0x01060 */	u64	kdfc_w_round_robin_59;
+#define	VXGE_HAL_KDFC_W_ROUND_ROBIN_59_NUMBER_152(val)	    vBIT(val, 3, 5)
+/* 0x01068 */	u64	kdfc_entry_type_sel_0;
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val)	    vBIT(val, 38, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val)	    vBIT(val, 46, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val)	    vBIT(val, 54, 2)
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val)	    vBIT(val, 62, 2)
+/* 0x01070 */	u64	kdfc_entry_type_sel_1;
+#define	VXGE_HAL_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val)	    vBIT(val, 6, 2)
+/* 0x01078 */	u64	kdfc_fifo_0_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_0_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01080 */	u64	kdfc_fifo_1_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_1_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01088 */	u64	kdfc_fifo_2_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_2_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01090 */	u64	kdfc_fifo_3_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_3_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01098 */	u64	kdfc_fifo_4_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_4_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010a0 */	u64	kdfc_fifo_5_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_5_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010a8 */	u64	kdfc_fifo_6_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_6_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010b0 */	u64	kdfc_fifo_7_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_7_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010b8 */	u64	kdfc_fifo_8_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_8_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010c0 */	u64	kdfc_fifo_9_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_9_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010c8 */	u64	kdfc_fifo_10_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_10_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010d0 */	u64	kdfc_fifo_11_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_11_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010d8 */	u64	kdfc_fifo_12_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_12_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010e0 */	u64	kdfc_fifo_13_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_13_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010e8 */	u64	kdfc_fifo_14_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_14_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010f0 */	u64	kdfc_fifo_15_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_15_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x010f8 */	u64	kdfc_fifo_16_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_16_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01100 */	u64	kdfc_fifo_17_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_17_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01108 */	u64	kdfc_fifo_18_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_18_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01110 */	u64	kdfc_fifo_19_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_19_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01118 */	u64	kdfc_fifo_20_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_20_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01120 */	u64	kdfc_fifo_21_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_21_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01128 */	u64	kdfc_fifo_22_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_22_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01130 */	u64	kdfc_fifo_23_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_23_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01138 */	u64	kdfc_fifo_24_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_24_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01140 */	u64	kdfc_fifo_25_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_25_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01148 */	u64	kdfc_fifo_26_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_26_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01150 */	u64	kdfc_fifo_27_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_27_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01158 */	u64	kdfc_fifo_28_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_28_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01160 */	u64	kdfc_fifo_29_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_29_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01168 */	u64	kdfc_fifo_30_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_30_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01170 */	u64	kdfc_fifo_31_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_31_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01178 */	u64	kdfc_fifo_32_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_32_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01180 */	u64	kdfc_fifo_33_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_33_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01188 */	u64	kdfc_fifo_34_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_34_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01190 */	u64	kdfc_fifo_35_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_35_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01198 */	u64	kdfc_fifo_36_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_36_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011a0 */	u64	kdfc_fifo_37_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_37_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011a8 */	u64	kdfc_fifo_38_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_38_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011b0 */	u64	kdfc_fifo_39_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_39_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011b8 */	u64	kdfc_fifo_40_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_40_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011c0 */	u64	kdfc_fifo_41_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_41_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011c8 */	u64	kdfc_fifo_42_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_42_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011d0 */	u64	kdfc_fifo_43_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_43_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011d8 */	u64	kdfc_fifo_44_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_44_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011e0 */	u64	kdfc_fifo_45_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_45_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011e8 */	u64	kdfc_fifo_46_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_46_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011f0 */	u64	kdfc_fifo_47_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_47_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x011f8 */	u64	kdfc_fifo_48_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_48_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01200 */	u64	kdfc_fifo_49_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_49_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01208 */	u64	kdfc_fifo_50_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_50_CTRL_WRR_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x01210 */	u64	kdfc_krnl_usr_ctrl;
+#define	VXGE_HAL_KDFC_KRNL_USR_CTRL_CODE(val)		    vBIT(val, 4, 4)
+/* 0x01218 */	u64	kdfc_pda_monitor;
+#define	VXGE_HAL_KDFC_PDA_MONITOR_KDFC_ACCEPT		    mBIT(7)
+#define	VXGE_HAL_KDFC_PDA_MONITOR_FIFO_NO(val)		    vBIT(val, 10, 6)
+#define	VXGE_HAL_KDFC_PDA_MONITOR_FIFO_ADD(val)		    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_PDA_MONITOR_TYPE(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFC_PDA_MONITOR_VP(val)		    vBIT(val, 43, 5)
+/* 0x01220 */	u64	kdfc_mp_monitor;
+#define	VXGE_HAL_KDFC_MP_MONITOR_KDFC_ACCEPT		    mBIT(7)
+#define	VXGE_HAL_KDFC_MP_MONITOR_FIFO_NO(val)		    vBIT(val, 10, 6)
+#define	VXGE_HAL_KDFC_MP_MONITOR_FIFO_ADD(val)		    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_MP_MONITOR_TYPE(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFC_MP_MONITOR_VP(val)		    vBIT(val, 43, 5)
+/* 0x01228 */	u64	kdfc_pe_monitor;
+#define	VXGE_HAL_KDFC_PE_MONITOR_KDFC_CREDIT		    mBIT(7)
+#define	VXGE_HAL_KDFC_PE_MONITOR_FIFO_NO(val)		    vBIT(val, 10, 6)
+#define	VXGE_HAL_KDFC_PE_MONITOR_FIFO_ADD(val)		    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_PE_MONITOR_TYPE(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFC_PE_MONITOR_VP(val)		    vBIT(val, 43, 5)
+#define	VXGE_HAL_KDFC_PE_MONITOR_IMM_DATA_CNT(val)	    vBIT(val, 48, 8)
+/* 0x01230 */	u64	kdfc_read_cntrl;
+#define	VXGE_HAL_KDFC_READ_CNTRL_KDFC_FREEZE		    mBIT(7)
+#define	VXGE_HAL_KDFC_READ_CNTRL_KDFC_RDCTRL(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_KDFC_READ_CNTRL_KDFC_WORD_SEL		    mBIT(23)
+#define	VXGE_HAL_KDFC_READ_CNTRL_KDFC_ADDR(val)		    vBIT(val, 49, 15)
+/* 0x01238 */	u64	kdfc_read_data;
+#define	VXGE_HAL_KDFC_READ_DATA_READ_DATA(val)		    vBIT(val, 0, 64)
+/* 0x01240 */	u64	kdfc_force_valid_ctrl;
+#define	VXGE_HAL_KDFC_FORCE_VALID_CTRL_FORCE_VALID	    mBIT(7)
+/* 0x01248 */	u64	kdfc_multi_cycle_ctrl;
+#define	VXGE_HAL_KDFC_MULTI_CYCLE_CTRL_MULTI_CYCLE_SEL(val) vBIT(val, 6, 2)
+/* 0x01250 */	u64	kdfc_ecc_ctrl;
+#define	VXGE_HAL_KDFC_ECC_CTRL_ECC_DISABLE		    mBIT(7)
+/* 0x01258 */	u64	kdfc_vpbp_ctrl;
+#define	VXGE_HAL_KDFC_VPBP_CTRL_RD_XON_DIS		    mBIT(7)
+#define	VXGE_HAL_KDFC_VPBP_CTRL_ROCRC_DIS		    mBIT(23)
+#define	VXGE_HAL_KDFC_VPBP_CTRL_H2L_DIS			    mBIT(31)
+#define	VXGE_HAL_KDFC_VPBP_CTRL_MSG_ONE_DIS		    mBIT(39)
+#define	VXGE_HAL_KDFC_VPBP_CTRL_MSG_DMQ_DIS		    mBIT(47)
+#define	VXGE_HAL_KDFC_VPBP_CTRL_PDA_DIS			    mBIT(55)
+	u8	unused01600[0x01600 - 0x01260];
+
+/* 0x01600 */	u64	rxmac_int_status;
+#define	VXGE_HAL_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT mBIT(3)
+#define	VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT mBIT(7)
+#define	VXGE_HAL_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT mBIT(11)
+/* 0x01608 */	u64	rxmac_int_mask;
+	u8	unused01618[0x01618 - 0x01610];
+
+/* 0x01618 */	u64	rxmac_gen_err_reg;
+/* 0x01620 */	u64	rxmac_gen_err_mask;
+/* 0x01628 */	u64	rxmac_gen_err_alarm;
+/* 0x01630 */	u64	rxmac_ecc_err_reg;
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val)\
+							    vBIT(val, 0, 4)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val)\
+							    vBIT(val, 8, 4)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val)\
+							    vBIT(val, 12, 4)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val)\
+							    vBIT(val, 16, 4)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val)\
+							    vBIT(val, 20, 4)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val)\
+							    vBIT(val, 24, 2)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val)\
+							    vBIT(val, 26, 2)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val)\
+							    vBIT(val, 28, 2)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val)\
+							    vBIT(val, 30, 2)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR	mBIT(32)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR	mBIT(33)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR	mBIT(34)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR	mBIT(35)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR	mBIT(36)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR	mBIT(37)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR	mBIT(38)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR	mBIT(39)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val)\
+							    vBIT(val, 40, 7)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val)\
+							    vBIT(val, 47, 7)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val)\
+							    vBIT(val, 54, 3)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val)\
+							    vBIT(val, 57, 3)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR  mBIT(60)
+#define	VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR  mBIT(61)
+/* 0x01638 */	u64	rxmac_ecc_err_mask;
+/* 0x01640 */	u64	rxmac_ecc_err_alarm;
+/* 0x01648 */	u64	rxmac_various_err_reg;
+#define	VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR mBIT(0)
+#define	VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR mBIT(1)
+#define	VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR mBIT(2)
+#define	VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR  mBIT(3)
+/* 0x01650 */	u64	rxmac_various_err_mask;
+/* 0x01658 */	u64	rxmac_various_err_alarm;
+/* 0x01660 */	u64	rxmac_gen_cfg;
+#define	VXGE_HAL_RXMAC_GEN_CFG_SCALE_RMAC_UTIL		    mBIT(11)
+/* 0x01668 */	u64	rxmac_authorize_all_addr;
+#define	VXGE_HAL_RXMAC_AUTHORIZE_ALL_ADDR_VP(n)		    mBIT(n)
+/* 0x01670 */	u64	rxmac_authorize_all_vid;
+#define	VXGE_HAL_RXMAC_AUTHORIZE_ALL_VID_VP(n)		    mBIT(n)
+	u8	unused016b8[0x016b8 - 0x01678];
+
+/* 0x016b8 */	u64	rxmac_thresh_cross_repl;
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_LOW_UP_CROSSED	mBIT(3)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_LOW_DOWN_CROSSED	mBIT(7)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_HIGH_UP_CROSSED	mBIT(11)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_HIGH_DOWN_CROSSED	mBIT(15)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED0_UP_CROSSED		mBIT(35)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED0_DOWN_CROSSED	mBIT(39)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED1_UP_CROSSED		mBIT(43)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED1_DOWN_CROSSED	mBIT(47)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED2_UP_CROSSED		mBIT(51)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED2_DOWN_CROSSED	mBIT(55)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED3_UP_CROSSED		mBIT(59)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED3_DOWN_CROSSED	mBIT(63)
+/* 0x016c0 */	u64	rxmac_red_rate_repl_queue;
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val)  vBIT(val, 0, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val)  vBIT(val, 4, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val)  vBIT(val, 8, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val)  vBIT(val, 12, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val)  vBIT(val, 16, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val)  vBIT(val, 20, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val)  vBIT(val, 24, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val)  vBIT(val, 28, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN	    mBIT(35)
+	u8	unused016e0[0x016e0 - 0x016c8];
+
+/* 0x016e0 */	u64	rxmac_cfg0_port[3];
+#define	VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN		    mBIT(3)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS		    mBIT(7)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM		    mBIT(11)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_FCS_ERR		    mBIT(15)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_LONG_ERR	    mBIT(19)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR	    mBIT(23)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH	    mBIT(27)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val)	    vBIT(val, 50, 14)
+	u8	unused01710[0x01710 - 0x016f8];
+
+/* 0x01710 */	u64	rxmac_cfg2_port[3];
+#define	VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN		    mBIT(3)
+/* 0x01728 */	u64	rxmac_pause_cfg_port[3];
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN		    mBIT(3)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN		    mBIT(7)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val)	    vBIT(val, 9, 3)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_DUAL_THR		    mBIT(15)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val)	    vBIT(val, 20, 16)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR	    mBIT(39)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR	    mBIT(43)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN	    mBIT(47)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val)	    vBIT(val, 48, 8)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL  mBIT(59)
+	u8	unused01758[0x01758 - 0x01740];
+
+/* 0x01758 */	u64	rxmac_red_cfg0_port[3];
+#define	VXGE_HAL_RXMAC_RED_CFG0_PORT_RED_EN_VP(n)	    mBIT(n)
+/* 0x01770 */	u64	rxmac_red_cfg1_port[3];
+#define	VXGE_HAL_RXMAC_RED_CFG1_PORT_FINE_EN		    mBIT(3)
+#define	VXGE_HAL_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE	    mBIT(11)
+/* 0x01788 */	u64	rxmac_red_cfg2_port[3];
+#define	VXGE_HAL_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n)	    mBIT(n)
+/* 0x017a0 */	u64	rxmac_link_util_port[3];
+#define	VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val)    vBIT(val, 8, 4)
+#define	VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) vBIT(val, 12, 4)
+#define	VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val)  vBIT(val, 16, 4)
+#define	VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR mBIT(23)
+	u8	unused017d0[0x017d0 - 0x017b8];
+
+/* 0x017d0 */	u64	rxmac_status_port[3];
+#define	VXGE_HAL_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD	    mBIT(3)
+	u8	unused01800[0x01800 - 0x017e8];
+
+/* 0x01800 */	u64	rxmac_rx_pa_cfg0;
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR	    mBIT(3)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N	    mBIT(7)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO	    mBIT(18)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS  mBIT(19)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING	    mBIT(23)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN	    mBIT(27)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE	    mBIT(35)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR mBIT(39)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR mBIT(43)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR	mBIT(47)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR	mBIT(51)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR	mBIT(55)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR	mBIT(59)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN		    mBIT(63)
+/* 0x01808 */	u64	rxmac_rx_pa_cfg1;
+#define	VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH	    mBIT(3)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH	    mBIT(7)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH	    mBIT(11)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH	    mBIT(15)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF	    mBIT(19)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG	    mBIT(23)
+	u8	unused01828[0x01828 - 0x01810];
+
+/* 0x01828 */	u64	rts_mgr_cfg0;
+#define	VXGE_HAL_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY	    mBIT(3)
+#define	VXGE_HAL_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_RTS_MGR_CFG0_ICMP_TRASH		    mBIT(35)
+#define	VXGE_HAL_RTS_MGR_CFG0_TCPSYN_TRASH		    mBIT(39)
+#define	VXGE_HAL_RTS_MGR_CFG0_ZL4PYLD_TRASH		    mBIT(43)
+#define	VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH		    mBIT(47)
+#define	VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH		    mBIT(51)
+#define	VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH	    mBIT(55)
+#define	VXGE_HAL_RTS_MGR_CFG0_IPFRAG_TRASH		    mBIT(59)
+/* 0x01830 */	u64	rts_mgr_cfg1;
+#define	VXGE_HAL_RTS_MGR_CFG1_DA_ACTIVE_TABLE		    mBIT(3)
+#define	VXGE_HAL_RTS_MGR_CFG1_PN_ACTIVE_TABLE		    mBIT(7)
+/* 0x01838 */	u64	rts_mgr_criteria_priority;
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vBIT(val, 9, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PN(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val)  vBIT(val, 17, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_DS(val)	    vBIT(val, 25, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_QOS(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val)	    vBIT(val, 33, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val)	    vBIT(val, 37, 3)
+/* 0x01840 */	u64	rts_mgr_da_pause_cfg;
+#define	VXGE_HAL_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val)	    vBIT(val, 0, 17)
+/* 0x01848 */	u64	rts_mgr_da_slow_proto_cfg;
+#define	VXGE_HAL_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17)
+	u8	unused018a8[0x018a8 - 0x01850];
+
+/* 0x018a8 */	u64	rts_mgr_steer_ctrl;
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_WE			    mBIT(7)
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(val)    vBIT(val, 8, 4)
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE		    mBIT(15)
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_BEHAV_TBL_SEL	    mBIT(23)
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL		    mBIT(27)
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(val)		    vBIT(val, 35, 13)
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS	    mBIT(0)
+/* 0x018b0 */	u64	rts_mgr_steer_data0;
+#define	VXGE_HAL_RTS_MGR_STEER_DATA0_DATA(val)		    vBIT(val, 0, 64)
+/* 0x018b8 */	u64	rts_mgr_steer_data1;
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_DATA(val)		    vBIT(val, 0, 64)
+/* 0x018c0 */	u64	rts_mgr_steer_vpath_vector;
+#define	VXGE_HAL_RTS_MGR_STEER_VPATH_VECTOR_VPATH_VECTOR(val) vBIT(val, 0, 17)
+	u8	unused01930[0x01930 - 0x018c8];
+
+/* 0x01930 */	u64	xmac_stats_rx_xgmii_char;
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR1(val)   vBIT(val, 1, 3)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXC_CHAR1	    mBIT(7)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR1(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR2(val)   vBIT(val, 17, 3)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXC_CHAR2	    mBIT(23)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR2(val)    vBIT(val, 24, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NEAR_CHAR1 mBIT(39)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\
+							    vBIT(val, 40, 16)
+/* 0x01938 */	u64	xmac_stats_rx_xgmii_column1;
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE0	    mBIT(7)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE0(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE1	    mBIT(23)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE1(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE2	    mBIT(39)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE2(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE3	    mBIT(55)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE3(val) vBIT(val, 56, 8)
+/* 0x01940 */	u64	xmac_stats_rx_xgmii_column2;
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE0	    mBIT(7)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE0(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE1	    mBIT(23)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE1(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE2	    mBIT(39)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE2(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE3	    mBIT(55)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE3(val) vBIT(val, 56, 8)
+/* 0x01948 */	u64	xmac_stats_rx_xgmii_behav_column2;
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NEAR_COL1 mBIT(7)
+#define	VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NUM_COL(val) vBIT(val, 8, 16)
+/* 0x01950 */	u64	xmac_rx_xgmii_capture_ctrl_port[3];
+#define	VXGE_HAL_XMAC_RX_XGMII_CAPTURE_CTRL_PORT_EN	    mBIT(3)
+#define	VXGE_HAL_XMAC_RX_XGMII_CAPTURE_CTRL_PORT_READBACK   mBIT(7)
+/* 0x01968 */	u64	dbg_stat_rx_any_frms;
+#define	VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) vBIT(val, 16, 8)
+	u8	unused01a00[0x01a00 - 0x01970];
+
+/* 0x01a00 */	u64	rxmac_red_rate_vp[17];
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR0(val)	    vBIT(val, 0, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR1(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR2(val)	    vBIT(val, 8, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR3(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR0(val)	    vBIT(val, 16, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR1(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR2(val)	    vBIT(val, 24, 4)
+#define	VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR3(val)	    vBIT(val, 28, 4)
+	u8	unused01c00[0x01c00 - 0x01a88];
+
+/* 0x01c00 */	u64	rxmac_thresh_cross_vp[17];
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_LOW_UP_CROSSED   mBIT(3)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_LOW_DOWN_CROSSED mBIT(7)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_HIGH_UP_CROSSED  mBIT(11)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_HIGH_DOWN_CROSSED mBIT(15)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR0_UP_CROSSED    mBIT(35)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR0_DOWN_CROSSED  mBIT(39)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR1_UP_CROSSED    mBIT(43)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR1_DOWN_CROSSED  mBIT(47)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR2_UP_CROSSED    mBIT(51)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR2_DOWN_CROSSED  mBIT(55)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR3_UP_CROSSED    mBIT(59)
+#define	VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR3_DOWN_CROSSED  mBIT(63)
+	u8	unused01e00[0x01e00 - 0x01c88];
+
+/* 0x01e00 */	u64	xgmac_int_status;
+#define	VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT mBIT(3)
+#define	VXGE_HAL_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0\
+							    mBIT(7)
+#define	VXGE_HAL_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1\
+							    mBIT(11)
+#define	VXGE_HAL_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT mBIT(15)
+#define	VXGE_HAL_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT mBIT(19)
+#define	VXGE_HAL_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT mBIT(23)
+/* 0x01e08 */	u64	xgmac_int_mask;
+/* 0x01e10 */	u64	xmac_gen_err_reg;
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED mBIT(7)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED	mBIT(11)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU    mBIT(15)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED	mBIT(19)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED	mBIT(23)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU    mBIT(27)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED	mBIT(31)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val)\
+							    vBIT(val, 40, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val)\
+							    vBIT(val, 42, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val)\
+							    vBIT(val, 44, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val)\
+							    vBIT(val, 46, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val)\
+							    vBIT(val, 48, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val)\
+							    vBIT(val, 50, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val)\
+							    vBIT(val, 52, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val)\
+							    vBIT(val, 54, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val)\
+							    vBIT(val, 56, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val)\
+							    vBIT(val, 58, 2)
+#define	VXGE_HAL_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR	    mBIT(63)
+/* 0x01e18 */	u64	xmac_gen_err_mask;
+/* 0x01e20 */	u64	xmac_gen_err_alarm;
+/* 0x01e28 */	u64	xmac_link_err_port0_reg;
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN	    mBIT(3)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP	    mBIT(7)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN mBIT(11)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP  mBIT(15)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT mBIT(19)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK    mBIT(23)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN	    mBIT(27)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP	    mBIT(31)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE mBIT(35)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV   mBIT(39)
+#define	VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE mBIT(47)
+/* 0x01e30 */	u64	xmac_link_err_port0_mask;
+/* 0x01e38 */	u64	xmac_link_err_port0_alarm;
+/* 0x01e40 */	u64	xmac_link_err_port1_reg;
+/* 0x01e48 */	u64	xmac_link_err_port1_mask;
+/* 0x01e50 */	u64	xmac_link_err_port1_alarm;
+/* 0x01e58 */	u64	xgxs_gen_err_reg;
+#define	VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR	    mBIT(63)
+/* 0x01e60 */	u64	xgxs_gen_err_mask;
+/* 0x01e68 */	u64	xgxs_gen_err_alarm;
+/* 0x01e70 */	u64	asic_ntwk_err_reg;
+#define	VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN	    mBIT(3)
+#define	VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP	    mBIT(7)
+#define	VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN	    mBIT(11)
+#define	VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP	    mBIT(15)
+#define	VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT	mBIT(19)
+#define	VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK	mBIT(23)
+/* 0x01e78 */	u64	asic_ntwk_err_mask;
+/* 0x01e80 */	u64	asic_ntwk_err_alarm;
+/* 0x01e88 */	u64	asic_gpio_err_reg;
+#define	VXGE_HAL_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n)	    mBIT(n)
+/* 0x01e90 */	u64	asic_gpio_err_mask;
+/* 0x01e98 */	u64	asic_gpio_err_alarm;
+/* 0x01ea0 */	u64	xgmac_gen_status;
+#define	VXGE_HAL_XGMAC_GEN_STATUS_XMACJ_NTWK_OK		    mBIT(3)
+#define	VXGE_HAL_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE	    mBIT(11)
+/* 0x01ea8 */	u64	xgmac_gen_fw_memo_status;
+#define	VXGE_HAL_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val)\
+							    vBIT(val, 0, 17)
+/* 0x01eb0 */	u64	xgmac_gen_fw_memo_mask;
+#define	VXGE_HAL_XGMAC_GEN_FW_MEMO_MASK_MASK(val)	    vBIT(val, 0, 64)
+/* 0x01eb8 */	u64	xgmac_gen_fw_vpath_to_vsport_status;
+#define	VXGE_HAL_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val)\
+							    vBIT(val, 0, 17)
+/* 0x01ec0 */	u64	xgmac_main_cfg_port[2];
+#define	VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN		    mBIT(3)
+/* 0x01ed0 */	u64	xgmac_debounce_port[2];
+#define	VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(val)    vBIT(val, 0, 4)
+#define	VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(val)  vBIT(val, 4, 4)
+#define	VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(val)    vBIT(val, 8, 4)
+#define	VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(val)  vBIT(val, 12, 4)
+/* 0x01ee0 */	u64	xgmac_status_port[2];
+#define	VXGE_HAL_XGMAC_STATUS_PORT_RMAC_REMOTE_FAULT	    mBIT(3)
+#define	VXGE_HAL_XGMAC_STATUS_PORT_RMAC_LOCAL_FAULT	    mBIT(7)
+#define	VXGE_HAL_XGMAC_STATUS_PORT_XMACJ_MAC_PHY_LAYER_AVAIL mBIT(11)
+#define	VXGE_HAL_XGMAC_STATUS_PORT_XMACJ_PORT_OK	    mBIT(15)
+	u8	unused01f40[0x01f40 - 0x01ef0];
+
+/* 0x01f40 */	u64	xmac_gen_cfg;
+#define	VXGE_HAL_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val)    vBIT(val, 2, 2)
+#define	VXGE_HAL_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT	    mBIT(7)
+#define	VXGE_HAL_XMAC_GEN_CFG_FAULT_BEHAVIOUR		    mBIT(27)
+#define	VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(val)	    vBIT(val, 28, 4)
+#define	VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val)	    vBIT(val, 32, 4)
+/* 0x01f48 */	u64	xmac_timestamp;
+#define	VXGE_HAL_XMAC_TIMESTAMP_EN			    mBIT(3)
+#define	VXGE_HAL_XMAC_TIMESTAMP_USE_LINK_ID(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_XMAC_TIMESTAMP_INTERVAL(val)		    vBIT(val, 12, 4)
+#define	VXGE_HAL_XMAC_TIMESTAMP_TIMER_RESTART		    mBIT(19)
+#define	VXGE_HAL_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val)	    vBIT(val, 32, 16)
+/* 0x01f50 */	u64	xmac_stats_gen_cfg;
+#define	VXGE_HAL_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val)  vBIT(val, 4, 4)
+#define	VXGE_HAL_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val)    vBIT(val, 8, 4)
+#define	VXGE_HAL_XMAC_STATS_GEN_CFG_VLAN_HANDLING	    mBIT(15)
+/* 0x01f58 */	u64	xmac_stats_sys_cmd;
+#define	VXGE_HAL_XMAC_STATS_SYS_CMD_OP(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE		    mBIT(15)
+#define	VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(val)	    vBIT(val, 32, 8)
+/* 0x01f60 */	u64	xmac_stats_sys_data;
+#define	VXGE_HAL_XMAC_STATS_SYS_DATA_XSMGR_DATA(val)	    vBIT(val, 0, 64)
+	u8	unused01f80[0x01f80 - 0x01f68];
+
+/* 0x01f80 */	u64	asic_ntwk_ctrl;
+#define	VXGE_HAL_ASIC_NTWK_CTRL_REQ_TEST_NTWK		    mBIT(3)
+#define	VXGE_HAL_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT	    mBIT(11)
+#define	VXGE_HAL_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT	    mBIT(15)
+/* 0x01f88 */	u64	asic_ntwk_cfg_show_port_info;
+#define	VXGE_HAL_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n)	    mBIT(n)
+/* 0x01f90 */	u64	asic_ntwk_cfg_port_num;
+#define	VXGE_HAL_ASIC_NTWK_CFG_PORT_NUM_VP(n)		    mBIT(n)
+/* 0x01f98 */	u64	xmac_cfg_port[3];
+#define	VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK		    mBIT(3)
+#define	VXGE_HAL_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK	    mBIT(7)
+#define	VXGE_HAL_XMAC_CFG_PORT_XGMII_TX_BEHAV		    mBIT(11)
+#define	VXGE_HAL_XMAC_CFG_PORT_XGMII_RX_BEHAV		    mBIT(15)
+/* 0x01fb0 */	u64	xmac_station_addr_port[2];
+#define	VXGE_HAL_XMAC_STATION_ADDR_PORT_MAC_ADDR(val)	    vBIT(val, 0, 48)
+/* 0x01fc0 */	u64	asic_led_activity_ctrl_port[3];
+#define	VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_TX_ACT_PULSE_EXTEND mBIT(11)
+#define	VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_RX_ACT_PULSE_EXTEND mBIT(15)
+#define	VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_COMBINE_TXRX   mBIT(35)
+	u8	unused02020[0x02020 - 0x01fd8];
+
+/* 0x02020 */	u64	lag_cfg;
+#define	VXGE_HAL_LAG_CFG_EN				    mBIT(3)
+#define	VXGE_HAL_LAG_CFG_MODE(val)			    vBIT(val, 6, 2)
+#define	VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV		    mBIT(11)
+#define	VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV		    mBIT(15)
+#define	VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM		    mBIT(19)
+/* 0x02028 */	u64	lag_status;
+#define	VXGE_HAL_LAG_STATUS_XLCM_WAITING_TO_FAILBACK	    mBIT(3)
+#define	VXGE_HAL_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) vBIT(val, 8, 8)
+/* 0x02030 */	u64	lag_active_passive_cfg;
+#define	VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY	    mBIT(3)
+#define	VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES	    mBIT(7)
+#define	VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM mBIT(11)
+#define	VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK	    mBIT(15)
+#define	VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN	    mBIT(19)
+#define	VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val)\
+							    vBIT(val, 32, 16)
+	u8	unused02040[0x02040 - 0x02038];
+
+/* 0x02040 */	u64	lag_lacp_cfg;
+#define	VXGE_HAL_LAG_LACP_CFG_EN			    mBIT(3)
+#define	VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN		    mBIT(7)
+#define	VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP		    mBIT(11)
+#define	VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK		    mBIT(15)
+/* 0x02048 */	u64	lag_timer_cfg_1;
+#define	VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(val)		    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val)	    vBIT(val, 32, 16)
+#define	VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(val)	    vBIT(val, 48, 16)
+/* 0x02050 */	u64	lag_timer_cfg_2;
+#define	VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(val)		    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val)	    vBIT(val, 32, 16)
+#define	VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val)	    vBIT(val, 48, 16)
+/* 0x02058 */	u64	lag_sys_id;
+#define	VXGE_HAL_LAG_SYS_ID_ADDR(val)			    vBIT(val, 0, 48)
+#define	VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR		    mBIT(51)
+#define	VXGE_HAL_LAG_SYS_ID_ADDR_SEL			    mBIT(55)
+/* 0x02060 */	u64	lag_sys_cfg;
+#define	VXGE_HAL_LAG_SYS_CFG_SYS_PRI(val)		    vBIT(val, 0, 16)
+	u8	unused02070[0x02070 - 0x02068];
+
+/* 0x02070 */	u64	lag_aggr_addr_cfg[2];
+#define	VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(val)		    vBIT(val, 0, 48)
+#define	VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR	    mBIT(51)
+#define	VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL		    mBIT(55)
+/* 0x02080 */	u64	lag_aggr_id_cfg[2];
+#define	VXGE_HAL_LAG_AGGR_ID_CFG_ID(val)		    vBIT(val, 0, 16)
+/* 0x02090 */	u64	lag_aggr_admin_key[2];
+#define	VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(val)		    vBIT(val, 0, 16)
+/* 0x020a0 */	u64	lag_aggr_alt_admin_key;
+#define	VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR	    mBIT(19)
+/* 0x020a8 */	u64	lag_aggr_oper_key[2];
+#define	VXGE_HAL_LAG_AGGR_OPER_KEY_LAGC_KEY(val)	    vBIT(val, 0, 16)
+/* 0x020b8 */	u64	lag_aggr_partner_sys_id[2];
+#define	VXGE_HAL_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val)	    vBIT(val, 0, 48)
+/* 0x020c8 */	u64	lag_aggr_partner_info[2];
+#define	VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val)    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val)   vBIT(val, 16, 16)
+/* 0x020d8 */	u64	lag_aggr_state[2];
+#define	VXGE_HAL_LAG_AGGR_STATE_LAGC_TX			    mBIT(3)
+#define	VXGE_HAL_LAG_AGGR_STATE_LAGC_RX			    mBIT(7)
+#define	VXGE_HAL_LAG_AGGR_STATE_LAGC_READY		    mBIT(11)
+#define	VXGE_HAL_LAG_AGGR_STATE_LAGC_INDIVIDUAL		    mBIT(15)
+	u8	unused020f0[0x020f0 - 0x020e8];
+
+/* 0x020f0 */	u64	lag_port_cfg[2];
+#define	VXGE_HAL_LAG_PORT_CFG_EN			    mBIT(3)
+#define	VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO	    mBIT(7)
+#define	VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR		    mBIT(11)
+#define	VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO    mBIT(15)
+/* 0x02100 */	u64	lag_port_actor_admin_cfg[2];
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val)	    vBIT(val, 32, 16)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val)	    vBIT(val, 48, 16)
+/* 0x02110 */	u64	lag_port_actor_admin_state[2];
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY   mBIT(3)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT    mBIT(7)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION	    mBIT(11)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION mBIT(15)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING	    mBIT(19)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING    mBIT(23)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED	    mBIT(27)
+#define	VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED	    mBIT(31)
+/* 0x02120 */	u64	lag_port_partner_admin_sys_id[2];
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val)    vBIT(val, 0, 48)
+/* 0x02130 */	u64	lag_port_partner_admin_cfg[2];
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val)    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val)   vBIT(val, 32, 16)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val)   vBIT(val, 48, 16)
+/* 0x02140 */	u64	lag_port_partner_admin_state[2];
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY mBIT(3)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT  mBIT(7)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION   mBIT(11)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION mBIT(15)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING    mBIT(19)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING  mBIT(23)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED	    mBIT(27)
+#define	VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED	    mBIT(31)
+/* 0x02150 */	u64	lag_port_to_aggr[2];
+#define	VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID	    mBIT(19)
+/* 0x02160 */	u64	lag_port_actor_oper_key[2];
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val)	    vBIT(val, 0, 16)
+/* 0x02170 */	u64	lag_port_actor_oper_state[2];
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY	mBIT(3)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT	mBIT(7)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION	mBIT(11)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION	mBIT(15)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING	mBIT(19)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING	mBIT(23)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED	mBIT(27)
+#define	VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED		mBIT(31)
+/* 0x02180 */	u64	lag_port_partner_oper_sys_id[2];
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48)
+/* 0x02190 */	u64	lag_port_partner_oper_info[2];
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val)   vBIT(val, 16, 16)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) vBIT(val, 32, 16)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) vBIT(val, 48, 16)
+/* 0x021a0 */	u64	lag_port_partner_oper_state[2];
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY	mBIT(3)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT	mBIT(7)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION	mBIT(11)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION mBIT(15)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING	mBIT(19)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING	mBIT(23)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED	mBIT(27)
+#define	VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED	mBIT(31)
+/* 0x021b0 */	u64	lag_port_state_vars[2];
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_READY		    mBIT(3)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_SELECTED(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM	    mBIT(11)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED	    mBIT(15)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED	    mBIT(18)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED	    mBIT(19)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_NTT		    mBIT(23)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN	    mBIT(27)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN	    mBIT(31)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH mBIT(32)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH mBIT(33)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH mBIT(34)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH mBIT(35)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vBIT(val, 37, 3)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) vBIT(val, 41, 3)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val)   vBIT(val, 44, 4)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE mBIT(54)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE mBIT(55)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val)\
+							    vBIT(val, 56, 4)
+#define	VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val)\
+							    vBIT(val, 60, 4)
+/* 0x021c0 */	u64	lag_port_timer_cntr[2];
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_while (val) vBIT(val, 0, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_while (val) vBIT(val, 8, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_WAIT_while (val)  vBIT(val, 16, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val)\
+							    vBIT(val, 32, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val)\
+							    vBIT(val, 40, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val)\
+							    vBIT(val, 48, 8)
+#define	VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val)\
+							    vBIT(val, 56, 8)
+	u8	unused021e0[0x021e0 - 0x021d0];
+
+/* 0x021e0 */	u64	transceiver_reset_port[2];
+#define	VXGE_HAL_TRANSCEIVER_RESET_PORT_TCVR_RESET(val)	    vBIT(val, 0, 8)
+/* 0x021f0 */	u64	transceiver_ctrl_port[2];
+#define	VXGE_HAL_TRANSCEIVER_CTRL_PORT_TCVR_TX_ON	    mBIT(3)
+/* 0x02200 */	u64	asic_gpio_ctrl;
+#define	VXGE_HAL_ASIC_GPIO_CTRL_XMACJ_GPIO_DATA_IN(n)	    mBIT(n)
+#define	VXGE_HAL_ASIC_GPIO_CTRL_GPIO_DATA_OUT(n)	    mBIT(n)
+#define	VXGE_HAL_ASIC_GPIO_CTRL_GPIO_OUT_EN(n)		    mBIT(n)
+/* 0x02208 */	u64	asic_led_beacon_ctrl;
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_LINK_INVERT	    mBIT(3)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_10G_INVERT	    mBIT(7)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_TX_ACT_INVERT   mBIT(11)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_RX_ACT_INVERT   mBIT(15)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_LINK_INVERT	    mBIT(19)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_10G_INVERT	    mBIT(23)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_TX_ACT_INVERT   mBIT(27)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_RX_ACT_INVERT   mBIT(31)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_AUX_LED1_INVERT	    mBIT(35)
+#define	VXGE_HAL_ASIC_LED_BEACON_CTRL_AUX_LED2_INVERT	    mBIT(39)
+/* 0x02210 */	u64	asic_led_ctrl0;
+#define	VXGE_HAL_ASIC_LED_CTRL0_PORT0_LINK_ON		    mBIT(3)
+#define	VXGE_HAL_ASIC_LED_CTRL0_PORT0_10G_ON		    mBIT(7)
+#define	VXGE_HAL_ASIC_LED_CTRL0_PORT1_LINK_ON		    mBIT(19)
+#define	VXGE_HAL_ASIC_LED_CTRL0_PORT1_10G_ON		    mBIT(23)
+#define	VXGE_HAL_ASIC_LED_CTRL0_AUX_LED1_ON		    mBIT(35)
+#define	VXGE_HAL_ASIC_LED_CTRL0_AUX_LED2_ON		    mBIT(39)
+/* 0x02218 */	u64	asic_led_ctrl1;
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_SOURCE(val)	    vBIT(val, 2, 2)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_SOURCE(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_SOURCE(val)	    vBIT(val, 10, 2)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_SOURCE(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_PULSE_EXTEND	    mBIT(19)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_PULSE_EXTEND	    mBIT(23)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_PULSE_EXTEND	    mBIT(27)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_PULSE_EXTEND	    mBIT(31)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_EXT_SEL(val)	    vBIT(val, 32, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_EXT_SEL(val)	    vBIT(val, 36, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_EXT_SEL(val)	    vBIT(val, 40, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_EXT_SEL(val)	    vBIT(val, 44, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_INT_SEL(val)	    vBIT(val, 48, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_INT_SEL(val)	    vBIT(val, 52, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_INT_SEL(val)	    vBIT(val, 56, 4)
+#define	VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_INT_SEL(val)	    vBIT(val, 60, 4)
+/* 0x02220 */	u64	asic_led_debug_sel;
+#define	VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL0(val)	    vBIT(val, 2, 6)
+#define	VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL1(val)	    vBIT(val, 10, 6)
+#define	VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL2(val)	    vBIT(val, 18, 6)
+#define	VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL3(val)	    vBIT(val, 26, 6)
+	u8	unused02300[0x02300 - 0x02228];
+
+/* 0x02300 */	u64	usdc_sgrp_partition;
+#define	VXGE_HAL_USDC_SGRP_PARTITION_ENABLE		    mBIT(7)
+/* 0x02308 */	u64	usdc_ugrp_priority_0;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_0_NUMBER_0(val)	    vBIT(val, 3, 5)
+/* 0x02310 */	u64	usdc_ugrp_priority_1;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_1_NUMBER_1(val)	    vBIT(val, 3, 5)
+/* 0x02318 */	u64	usdc_ugrp_priority_2;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_2_NUMBER_2(val)	    vBIT(val, 3, 5)
+/* 0x02320 */	u64	usdc_ugrp_priority_3;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_3_NUMBER_3(val)	    vBIT(val, 3, 5)
+/* 0x02328 */	u64	usdc_ugrp_priority_4;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_4_NUMBER_4(val)	    vBIT(val, 3, 5)
+/* 0x02330 */	u64	usdc_ugrp_priority_5;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_5_NUMBER_5(val)	    vBIT(val, 3, 5)
+/* 0x02338 */	u64	usdc_ugrp_priority_6;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_6_NUMBER_6(val)	    vBIT(val, 3, 5)
+/* 0x02340 */	u64	usdc_ugrp_priority_7;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_7_NUMBER_7(val)	    vBIT(val, 3, 5)
+/* 0x02348 */	u64	usdc_ugrp_priority_8;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_8_NUMBER_8(val)	    vBIT(val, 3, 5)
+/* 0x02350 */	u64	usdc_ugrp_priority_9;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_9_NUMBER_9(val)	    vBIT(val, 3, 5)
+/* 0x02358 */	u64	usdc_ugrp_priority_10;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_10_NUMBER_10(val)	    vBIT(val, 3, 5)
+/* 0x02360 */	u64	usdc_ugrp_priority_11;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_11_NUMBER_11(val)	    vBIT(val, 3, 5)
+/* 0x02368 */	u64	usdc_ugrp_priority_12;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_12_NUMBER_12(val)	    vBIT(val, 3, 5)
+/* 0x02370 */	u64	usdc_ugrp_priority_13;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_13_NUMBER_13(val)	    vBIT(val, 3, 5)
+/* 0x02378 */	u64	usdc_ugrp_priority_14;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_14_NUMBER_14(val)	    vBIT(val, 3, 5)
+/* 0x02380 */	u64	usdc_ugrp_priority_15;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_15_NUMBER_15(val)	    vBIT(val, 3, 5)
+/* 0x02388 */	u64	usdc_ugrp_priority_16;
+#define	VXGE_HAL_USDC_UGRP_PRIORITY_16_NUMBER_16(val)	    vBIT(val, 3, 5)
+	u8	unused02398[0x02398 - 0x02390];
+
+/* 0x02398 */	u64	ugrp_htn_wrr_priority_0;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x023a0 */	u64	ugrp_htn_wrr_priority_1;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_10(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_11(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_12(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_13(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_14(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_15(val)	    vBIT(val, 59, 5)
+/* 0x023a8 */	u64	ugrp_htn_wrr_priority_2;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_16(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_17(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_18(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_19(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_20(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_21(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_22(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_23(val)	    vBIT(val, 59, 5)
+/* 0x023b0 */	u64	ugrp_htn_wrr_priority_3;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_24(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_25(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_26(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_27(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_28(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_29(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_30(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_31(val)	    vBIT(val, 59, 5)
+/* 0x023b8 */	u64	ugrp_htn_wrr_priority_4;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_32(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_33(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_34(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_35(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_36(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_37(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_38(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_39(val)	    vBIT(val, 59, 5)
+/* 0x023c0 */	u64	ugrp_htn_wrr_priority_5;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_40(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_41(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_42(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_43(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_44(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_45(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_46(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_47(val)	    vBIT(val, 59, 5)
+/* 0x023c8 */	u64	ugrp_htn_wrr_priority_6;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_48(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_49(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_50(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_51(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_52(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_53(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_54(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_55(val)	    vBIT(val, 59, 5)
+/* 0x023d0 */	u64	ugrp_htn_wrr_priority_7;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_56(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_57(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_58(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_59(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_60(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_61(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_62(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_63(val)	    vBIT(val, 59, 5)
+/* 0x023d8 */	u64	ugrp_htn_wrr_priority_8;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_64(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_65(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_66(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_67(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_68(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_69(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_70(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_71(val)	    vBIT(val, 59, 5)
+/* 0x023e0 */	u64	ugrp_htn_wrr_priority_9;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_72(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_73(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_74(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_75(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_76(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_77(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_78(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_79(val)	    vBIT(val, 59, 5)
+/* 0x023e8 */	u64	ugrp_htn_wrr_priority_10;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_80(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_81(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_82(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_83(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_84(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_85(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_86(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_87(val)    vBIT(val, 59, 5)
+/* 0x023f0 */	u64	ugrp_htn_wrr_priority_11;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_88(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_89(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_90(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_91(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_92(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_93(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_94(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_95(val)    vBIT(val, 59, 5)
+/* 0x023f8 */	u64	ugrp_htn_wrr_priority_12;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_96(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_97(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_98(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_99(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_100(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_101(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_102(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_103(val)   vBIT(val, 59, 5)
+/* 0x02400 */	u64	ugrp_htn_wrr_priority_13;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_104(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_105(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_106(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_107(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_108(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_109(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_110(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_111(val)   vBIT(val, 59, 5)
+/* 0x02408 */	u64	ugrp_htn_wrr_priority_14;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_112(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_113(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_114(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_115(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_116(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_117(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_118(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_119(val)   vBIT(val, 59, 5)
+/* 0x02410 */	u64	ugrp_htn_wrr_priority_15;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_120(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_121(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_122(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_123(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_124(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_125(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_126(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_127(val)   vBIT(val, 59, 5)
+/* 0x02418 */	u64	ugrp_htn_wrr_priority_16;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_128(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_129(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_130(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_131(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_132(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_133(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_134(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_135(val)   vBIT(val, 59, 5)
+/* 0x02420 */	u64	ugrp_htn_wrr_priority_17;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_136(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_137(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_138(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_139(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_140(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_141(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_142(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_143(val)   vBIT(val, 59, 5)
+/* 0x02428 */	u64	ugrp_htn_wrr_priority_18;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_144(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_145(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_146(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_147(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_148(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_149(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_150(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_151(val)   vBIT(val, 59, 5)
+/* 0x02430 */	u64	ugrp_htn_wrr_priority_19;
+#define	VXGE_HAL_UGRP_HTN_WRR_PRIORITY_19_NUMBER_152(val)   vBIT(val, 3, 5)
+/* 0x02438 */	u64	usdc_vplane[17];
+#define	VXGE_HAL_USDC_VPLANE_SGRP_OWN(val)		    vBIT(val, 0, 32)
+	u8	unused024c8[0x024c8 - 0x024c0];
+
+/* 0x024c8 */	u64	usdc_sgrp_assignment;
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_0_ERR	    mBIT(0)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_1_ERR	    mBIT(1)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_2_ERR	    mBIT(2)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_3_ERR	    mBIT(3)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_4_ERR	    mBIT(4)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_5_ERR	    mBIT(5)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_6_ERR	    mBIT(6)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_7_ERR	    mBIT(7)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_8_ERR	    mBIT(8)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_9_ERR	    mBIT(9)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_10_ERR	    mBIT(10)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_11_ERR	    mBIT(11)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_12_ERR	    mBIT(12)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_13_ERR	    mBIT(13)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_14_ERR	    mBIT(14)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_15_ERR	    mBIT(15)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_16_ERR	    mBIT(16)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_17_ERR	    mBIT(17)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_18_ERR	    mBIT(18)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_19_ERR	    mBIT(19)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_20_ERR	    mBIT(20)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_21_ERR	    mBIT(21)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_22_ERR	    mBIT(22)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_23_ERR	    mBIT(23)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_24_ERR	    mBIT(24)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_25_ERR	    mBIT(25)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_26_ERR	    mBIT(26)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_27_ERR	    mBIT(27)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_28_ERR	    mBIT(28)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_29_ERR	    mBIT(29)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_30_ERR	    mBIT(30)
+#define	VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_31_ERR	    mBIT(31)
+/* 0x024d0 */	u64	usdc_cntrl;
+#define	VXGE_HAL_USDC_CNTRL_MIN_VALUE(val)		    vBIT(val, 1, 7)
+/* 0x024d8 */	u64	usdc_read_cntrl;
+#define	VXGE_HAL_USDC_READ_CNTRL_USDC_FREEZE		    mBIT(7)
+#define	VXGE_HAL_USDC_READ_CNTRL_USDC_RDCTRL(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_USDC_READ_CNTRL_USDC_WORD_SEL		    mBIT(23)
+#define	VXGE_HAL_USDC_READ_CNTRL_USDC_ADDR(val)		    vBIT(val, 49, 15)
+/* 0x024e0 */	u64	usdc_read_data;
+#define	VXGE_HAL_USDC_READ_DATA_READ_DATA(val)		    vBIT(val, 0, 64)
+	u8	unused02500[0x02500 - 0x024e8];
+
+/* 0x02500 */	u64	ugrp_srq_wrr_priority_0;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x02508 */	u64	ugrp_srq_wrr_priority_1;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_10(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_11(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_12(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_13(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_14(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_15(val)	    vBIT(val, 59, 5)
+/* 0x02510 */	u64	ugrp_srq_wrr_priority_2;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_16(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_17(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_18(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_19(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_20(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_21(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_22(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_23(val)	    vBIT(val, 59, 5)
+/* 0x02518 */	u64	ugrp_srq_wrr_priority_3;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_24(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_25(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_26(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_27(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_28(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_29(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_30(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_31(val)	    vBIT(val, 59, 5)
+/* 0x02520 */	u64	ugrp_srq_wrr_priority_4;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_32(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_33(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_34(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_35(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_36(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_37(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_38(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_39(val)	    vBIT(val, 59, 5)
+/* 0x02528 */	u64	ugrp_srq_wrr_priority_5;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_40(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_41(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_42(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_43(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_44(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_45(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_46(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_47(val)	    vBIT(val, 59, 5)
+/* 0x02530 */	u64	ugrp_srq_wrr_priority_6;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_48(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_49(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_50(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_51(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_52(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_53(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_54(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_55(val)	    vBIT(val, 59, 5)
+/* 0x02538 */	u64	ugrp_srq_wrr_priority_7;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_56(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_57(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_58(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_59(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_60(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_61(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_62(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_63(val)	    vBIT(val, 59, 5)
+/* 0x02540 */	u64	ugrp_srq_wrr_priority_8;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_64(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_65(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_66(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_67(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_68(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_69(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_70(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_71(val)	    vBIT(val, 59, 5)
+/* 0x02548 */	u64	ugrp_srq_wrr_priority_9;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_72(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_73(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_74(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_75(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_76(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_77(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_78(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_79(val)	    vBIT(val, 59, 5)
+/* 0x02550 */	u64	ugrp_srq_wrr_priority_10;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_80(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_81(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_82(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_83(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_84(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_85(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_86(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_87(val)    vBIT(val, 59, 5)
+/* 0x02558 */	u64	ugrp_srq_wrr_priority_11;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_88(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_89(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_90(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_91(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_92(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_93(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_94(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_95(val)    vBIT(val, 59, 5)
+/* 0x02560 */	u64	ugrp_srq_wrr_priority_12;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_96(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_97(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_98(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_99(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_100(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_101(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_102(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_103(val)   vBIT(val, 59, 5)
+/* 0x02568 */	u64	ugrp_srq_wrr_priority_13;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_104(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_105(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_106(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_107(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_108(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_109(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_110(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_111(val)   vBIT(val, 59, 5)
+/* 0x02570 */	u64	ugrp_srq_wrr_priority_14;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_112(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_113(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_114(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_115(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_116(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_117(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_118(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_119(val)   vBIT(val, 59, 5)
+/* 0x02578 */	u64	ugrp_srq_wrr_priority_15;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_120(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_121(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_122(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_123(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_124(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_125(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_126(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_127(val)   vBIT(val, 59, 5)
+/* 0x02580 */	u64	ugrp_srq_wrr_priority_16;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_128(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_129(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_130(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_131(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_132(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_133(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_134(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_135(val)   vBIT(val, 59, 5)
+/* 0x02588 */	u64	ugrp_srq_wrr_priority_17;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_136(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_137(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_138(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_139(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_140(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_141(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_142(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_143(val)   vBIT(val, 59, 5)
+/* 0x02590 */	u64	ugrp_srq_wrr_priority_18;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_144(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_145(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_146(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_147(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_148(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_149(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_150(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_151(val)   vBIT(val, 59, 5)
+/* 0x02598 */	u64	ugrp_srq_wrr_priority_19;
+#define	VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_19_NUMBER_152(val)   vBIT(val, 3, 5)
+/* 0x025a0 */	u64	ugrp_cqrq_wrr_priority_0;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_0(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_1(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_2(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_3(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_4(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_5(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_6(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_7(val)	    vBIT(val, 59, 5)
+/* 0x025a8 */	u64	ugrp_cqrq_wrr_priority_1;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_8(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_9(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_10(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_11(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_12(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_13(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_14(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_15(val)    vBIT(val, 59, 5)
+/* 0x025b0 */	u64	ugrp_cqrq_wrr_priority_2;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_16(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_17(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_18(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_19(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_20(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_21(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_22(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_23(val)    vBIT(val, 59, 5)
+/* 0x025b8 */	u64	ugrp_cqrq_wrr_priority_3;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_24(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_25(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_26(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_27(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_28(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_29(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_30(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_31(val)    vBIT(val, 59, 5)
+/* 0x025c0 */	u64	ugrp_cqrq_wrr_priority_4;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_32(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_33(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_34(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_35(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_36(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_37(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_38(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_39(val)    vBIT(val, 59, 5)
+/* 0x025c8 */	u64	ugrp_cqrq_wrr_priority_5;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_40(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_41(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_42(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_43(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_44(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_45(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_46(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_47(val)    vBIT(val, 59, 5)
+/* 0x025d0 */	u64	ugrp_cqrq_wrr_priority_6;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_48(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_49(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_50(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_51(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_52(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_53(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_54(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_55(val)    vBIT(val, 59, 5)
+/* 0x025d8 */	u64	ugrp_cqrq_wrr_priority_7;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_56(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_57(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_58(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_59(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_60(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_61(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_62(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_63(val)    vBIT(val, 59, 5)
+/* 0x025e0 */	u64	ugrp_cqrq_wrr_priority_8;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_64(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_65(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_66(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_67(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_68(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_69(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_70(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_71(val)    vBIT(val, 59, 5)
+/* 0x025e8 */	u64	ugrp_cqrq_wrr_priority_9;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_72(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_73(val)    vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_74(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_75(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_76(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_77(val)    vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_78(val)    vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_79(val)    vBIT(val, 59, 5)
+/* 0x025f0 */	u64	ugrp_cqrq_wrr_priority_10;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_80(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_81(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_82(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_83(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_84(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_85(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_86(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_87(val)   vBIT(val, 59, 5)
+/* 0x025f8 */	u64	ugrp_cqrq_wrr_priority_11;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_88(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_89(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_90(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_91(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_92(val)   vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_93(val)   vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_94(val)   vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_95(val)   vBIT(val, 59, 5)
+/* 0x02600 */	u64	ugrp_cqrq_wrr_priority_12;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_96(val)   vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_97(val)   vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_98(val)   vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_99(val)   vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_100(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_101(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_102(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_103(val)  vBIT(val, 59, 5)
+/* 0x02608 */	u64	ugrp_cqrq_wrr_priority_13;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_104(val)  vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_105(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_106(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_107(val)  vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_108(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_109(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_110(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_111(val)  vBIT(val, 59, 5)
+/* 0x02610 */	u64	ugrp_cqrq_wrr_priority_14;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_112(val)  vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_113(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_114(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_115(val)  vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_116(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_117(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_118(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_119(val)  vBIT(val, 59, 5)
+/* 0x02618 */	u64	ugrp_cqrq_wrr_priority_15;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_120(val)  vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_121(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_122(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_123(val)  vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_124(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_125(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_126(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_127(val)  vBIT(val, 59, 5)
+/* 0x02620 */	u64	ugrp_cqrq_wrr_priority_16;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_128(val)  vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_129(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_130(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_131(val)  vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_132(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_133(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_134(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_135(val)  vBIT(val, 59, 5)
+/* 0x02628 */	u64	ugrp_cqrq_wrr_priority_17;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_136(val)  vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_137(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_138(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_139(val)  vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_140(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_141(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_142(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_143(val)  vBIT(val, 59, 5)
+/* 0x02630 */	u64	ugrp_cqrq_wrr_priority_18;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_144(val)  vBIT(val, 3, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_145(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_146(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_147(val)  vBIT(val, 27, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_148(val)  vBIT(val, 35, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_149(val)  vBIT(val, 43, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_150(val)  vBIT(val, 51, 5)
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_151(val)  vBIT(val, 59, 5)
+/* 0x02638 */	u64	ugrp_cqrq_wrr_priority_19;
+#define	VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_19_NUMBER_152(val)  vBIT(val, 3, 5)
+/* 0x02640 */	u64	usdc_ecc_ctrl;
+#define	VXGE_HAL_USDC_ECC_CTRL_ECC_DISABLE		    mBIT(7)
+/* 0x02648 */	u64	usdc_vpbp_ctrl;
+#define	VXGE_HAL_USDC_VPBP_CTRL_MSG_DIS			    mBIT(0)
+#define	VXGE_HAL_USDC_VPBP_CTRL_H2L_DIS			    mBIT(1)
+	u8	unused02700[0x02700 - 0x02650];
+
+/* 0x02700 */	u64	rtdma_int_status;
+#define	VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT	    mBIT(1)
+#define	VXGE_HAL_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT	    mBIT(2)
+#define	VXGE_HAL_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT	    mBIT(4)
+#define	VXGE_HAL_RTDMA_INT_STATUS_SM_ERROR_SM_INT	    mBIT(5)
+/* 0x02708 */	u64	rtdma_int_mask;
+/* 0x02710 */	u64	pda_alarm_reg;
+#define	VXGE_HAL_PDA_ALARM_REG_PDA_HSC_FIFO_ERR		    mBIT(0)
+#define	VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR		    mBIT(1)
+/* 0x02718 */	u64	pda_alarm_mask;
+/* 0x02720 */	u64	pda_alarm_alarm;
+/* 0x02728 */	u64	pcc_error_reg;
+#define	VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n)	    mBIT(n)
+#define	VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n)	    mBIT(n)
+#define	VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n)	    mBIT(n)
+#define	VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n)	    mBIT(n)
+#define	VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n)	    mBIT(n)
+#define	VXGE_HAL_PCC_ERROR_REG_PCC_PCC_SERR(n)		    mBIT(n)
+/* 0x02730 */	u64	pcc_error_mask;
+/* 0x02738 */	u64	pcc_error_alarm;
+/* 0x02740 */	u64	lso_error_reg;
+#define	VXGE_HAL_LSO_ERROR_REG_PCC_LSO_ABORT(n)		    mBIT(n)
+#define	VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n)	    mBIT(n)
+/* 0x02748 */	u64	lso_error_mask;
+/* 0x02750 */	u64	lso_error_alarm;
+/* 0x02758 */	u64	sm_error_reg;
+#define	VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM		    mBIT(15)
+/* 0x02760 */	u64	sm_error_mask;
+/* 0x02768 */	u64	sm_error_alarm;
+/* 0x02770 */	u64	pda_control;
+#define	VXGE_HAL_PDA_CONTROL_PCC_INTERLOCK_EN		    mBIT(7)
+#define	VXGE_HAL_PDA_CONTROL_SPLIT_IDLE			    mBIT(15)
+#define	VXGE_HAL_PDA_CONTROL_PCC_MAX_DISABLE		    mBIT(23)
+#define	VXGE_HAL_PDA_CONTROL_H2L_DO_GATE_EN		    mBIT(31)
+#define	VXGE_HAL_PDA_CONTROL_TXD_INT_NUM_CTLR		    mBIT(39)
+#define	VXGE_HAL_PDA_CONTROL_ISSUE_8B_READ		    mBIT(47)
+/* 0x02778 */	u64	pda_pda_control_0;
+#define	VXGE_HAL_PDA_PDA_CONTROL_0_PCC_MAX(val)		    vBIT(val, 4, 4)
+#define	VXGE_HAL_PDA_PDA_CONTROL_0_FE_MAX(val)		    vBIT(val, 13, 3)
+/* 0x02780 */	u64	pda_pda_service_state_0;
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_0(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_1(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_2(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_3(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_4(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_5(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_6(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_7(val)	    vBIT(val, 61, 3)
+/* 0x02788 */	u64	pda_pda_service_state_1;
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_8(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_9(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_10(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_11(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_12(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_13(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_14(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_15(val)	    vBIT(val, 61, 3)
+/* 0x02790 */	u64	pda_pda_service_state_2;
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_16(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_17(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_18(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_19(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_20(val)	    vBIT(val, 37, 3)
+/* 0x02798 */	u64	pda_pda_task_priority_number;
+#define	VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_CXP(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_H2L(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_KDFC(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_MP(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_PE(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_QCC(val)	    vBIT(val, 45, 3)
+/* 0x027a0 */	u64	pda_vp;
+#define	VXGE_HAL_PDA_VP_RD_XON_ENABLE			    mBIT(0)
+#define	VXGE_HAL_PDA_VP_WR_XON_ENABLE			    mBIT(1)
+#define	VXGE_HAL_PDA_VP_NO_ACTIVITY_DISABLE		    mBIT(2)
+/* 0x027a8 */	u64	txd_ownership_ctrl;
+#define	VXGE_HAL_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP	    mBIT(7)
+/* 0x027b0 */	u64	pcc_cfg;
+#define	VXGE_HAL_PCC_CFG_PCC_ENABLE(n)			    mBIT(n)
+#define	VXGE_HAL_PCC_CFG_PCC_ECC_ENABLE_N(n)		    mBIT(n)
+/* 0x027b8 */	u64	pcc_control;
+#define	VXGE_HAL_PCC_CONTROL_FE_ENABLE(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_PCC_CONTROL_EARLY_ASSIGN_EN		    mBIT(15)
+#define	VXGE_HAL_PCC_CONTROL_UNBLOCK_DB_ERR		    mBIT(31)
+/* 0x027c0 */	u64	pda_status1;
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_0_CTR(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_1_CTR(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_2_CTR(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_3_CTR(val)	    vBIT(val, 28, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_4_CTR(val)	    vBIT(val, 36, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_5_CTR(val)	    vBIT(val, 44, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_6_CTR(val)	    vBIT(val, 52, 4)
+#define	VXGE_HAL_PDA_STATUS1_PDA_WRAP_7_CTR(val)	    vBIT(val, 60, 4)
+/* 0x027c8 */	u64	rtdma_bw_timer;
+#define	VXGE_HAL_RTDMA_BW_TIMER_TIMER_CTRL(val)		    vBIT(val, 12, 4)
+	u8	unused02900[0x02900 - 0x027d0];
+
+/* 0x02900 */	u64	g3cmct_int_status;
+#define	VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT		    mBIT(0)
+/* 0x02908 */	u64	g3cmct_int_mask;
+/* 0x02910 */	u64	g3cmct_err_reg;
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR		    mBIT(4)
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_DECC		    mBIT(5)
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC	    mBIT(6)
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC	    mBIT(7)
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_SECC		    mBIT(29)
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC	    mBIT(30)
+#define	VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC	    mBIT(31)
+/* 0x02918 */	u64	g3cmct_err_mask;
+/* 0x02920 */	u64	g3cmct_err_alarm;
+/* 0x02928 */	u64	g3cmct_config0;
+#define	VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY_RPATH(val)   vBIT(val, 5, 3)
+#define	VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_G3CMCT_CONFIG0_REFRESH_PER(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_G3CMCT_CONFIG0_TRC(val)		    vBIT(val, 35, 5)
+#define	VXGE_HAL_G3CMCT_CONFIG0_TRRD(val)		    vBIT(val, 44, 4)
+#define	VXGE_HAL_G3CMCT_CONFIG0_TFAW(val)		    vBIT(val, 50, 6)
+#define	VXGE_HAL_G3CMCT_CONFIG0_RD_FIFO_THR(val)	    vBIT(val, 58, 6)
+/* 0x02930 */	u64	g3cmct_config1;
+#define	VXGE_HAL_G3CMCT_CONFIG1_BIC_THR(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_G3CMCT_CONFIG1_BIC_OFF			    mBIT(15)
+#define	VXGE_HAL_G3CMCT_CONFIG1_IGNORE_BEM		    mBIT(23)
+#define	VXGE_HAL_G3CMCT_CONFIG1_RD_SAMPLING(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_G3CMCT_CONFIG1_CMD_START_PHASE		    mBIT(39)
+#define	VXGE_HAL_G3CMCT_CONFIG1_BIC_HI_THR(val)		    vBIT(val, 43, 5)
+#define	VXGE_HAL_G3CMCT_CONFIG1_BIC_MODE(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_G3CMCT_CONFIG1_ECC_ENABLE(val)		    vBIT(val, 57, 7)
+/* 0x02938 */	u64	g3cmct_config2;
+#define	VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_ENABLE(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_VALUE(val)	    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3CMCT_CONFIG2_ARBITER_CTRL(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_G3CMCT_CONFIG2_DEFINE_CAD		    mBIT(31)
+#define	VXGE_HAL_G3CMCT_CONFIG2_DEFINE_NOP_AD		    mBIT(39)
+#define	VXGE_HAL_G3CMCT_CONFIG2_LAST_CADD(val)		    vBIT(val, 43, 13)
+/* 0x02940 */	u64	g3cmct_init0;
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_BAD(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_WL(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_DLL			    mBIT(23)
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_TM			    mBIT(39)
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_CL(val)		    vBIT(val, 44, 4)
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_BT			    mBIT(55)
+#define	VXGE_HAL_G3CMCT_INIT0_MRS_BL(val)		    vBIT(val, 62, 2)
+/* 0x02948 */	u64	g3cmct_init1;
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_BAD(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_AD_TER		    mBIT(15)
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_ID			    mBIT(23)
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_RON			    mBIT(39)
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_AL			    mBIT(47)
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_TWR(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_G3CMCT_INIT1_EMRS_DQ_TER(val)		    vBIT(val, 62, 2)
+/* 0x02950 */	u64	g3cmct_init2;
+#define	VXGE_HAL_G3CMCT_INIT2_EMRS_DR_STR(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3CMCT_INIT2_START_INI	mBIT(15)
+#define	VXGE_HAL_G3CMCT_INIT2_POWER_UP_DELAY(val)	    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3CMCT_INIT2_ACTIVE_CMD_DELAY(val)	    vBIT(val, 40, 24)
+/* 0x02958 */	u64	g3cmct_init3;
+#define	VXGE_HAL_G3CMCT_INIT3_TRP_DELAY(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TMRD_DELAY(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TWR2PRE_DELAY(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TRD2PRE_DELAY(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TRCDR_DELAY(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TRCDW_DELAY(val)		    vBIT(val, 40, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TWR2RD_DELAY(val)		    vBIT(val, 48, 8)
+#define	VXGE_HAL_G3CMCT_INIT3_TRD2WR_DELAY(val)		    vBIT(val, 56, 8)
+/* 0x02960 */	u64	g3cmct_init4;
+#define	VXGE_HAL_G3CMCT_INIT4_TRFC_DELAY(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3CMCT_INIT4_REFRESH_BURSTS(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_G3CMCT_INIT4_CKE_INIT_VAL		    mBIT(31)
+#define	VXGE_HAL_G3CMCT_INIT4_VENDOR_ID(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3CMCT_INIT4_OOO_DEPTH(val)		    vBIT(val, 42, 6)
+#define	VXGE_HAL_G3CMCT_INIT4_ICTRL_INIT_DONE		    mBIT(55)
+#define	VXGE_HAL_G3CMCT_INIT4_IOCAL_WAIT_DISABLE	    mBIT(63)
+/* 0x02968 */	u64	g3cmct_init5;
+#define	VXGE_HAL_G3CMCT_INIT5_TRAS_DELAY(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_G3CMCT_INIT5_TVID_DELAY(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD(val)		    vBIT(val, 16, 8)
+#define	VXGE_HAL_G3CMCT_INIT5_TRD_APRE2CMD(val)		    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD_CON(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3CMCT_INIT5_GDDR3_DLL_DELAY(val)	    vBIT(val, 40, 24)
+/* 0x02970 */	u64	g3cmct_dll_training1;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING1_DLL_TRA_DATA00(val)   vBIT(val, 0, 64)
+/* 0x02978 */	u64	g3cmct_dll_training2;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING2_DLL_TRA_DATA01(val)   vBIT(val, 0, 64)
+/* 0x02980 */	u64	g3cmct_dll_training3;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING3_DLL_TRA_DATA10(val)   vBIT(val, 0, 64)
+/* 0x02988 */	u64	g3cmct_dll_training4;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING4_DLL_TRA_DATA11(val)   vBIT(val, 0, 64)
+/* 0x02990 */	u64	g3cmct_dll_training6;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING6_DLL_TRA_DATA20(val)   vBIT(val, 0, 64)
+/* 0x02998 */	u64	g3cmct_dll_training7;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING7_DLL_TRA_DATA21(val)   vBIT(val, 0, 64)
+/* 0x029a0 */	u64	g3cmct_dll_training8;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING8_DLL_TRA_DATA30(val)   vBIT(val, 0, 64)
+/* 0x029a8 */	u64	g3cmct_dll_training9;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING9_DLL_TRA_DATA31(val)   vBIT(val, 0, 64)
+/* 0x029b0 */	u64	g3cmct_dll_training5;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_RADD(val)	    vBIT(val, 2, 14)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD0(val)    vBIT(val, 21, 11)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD1(val)    vBIT(val, 37, 11)
+/* 0x029b8 */	u64	g3cmct_dll_training10;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_TP_READS(val)    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_SAMPLES(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_LOOPS(val)	    vBIT(val, 18, 14)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_PASS_CNT(val)    vBIT(val, 33, 7)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_STEP(val)	    vBIT(val, 41, 7)
+/* 0x029c0 */	u64	g3cmct_dll_training11;
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48)
+#define	VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2)
+/* 0x029c8 */	u64	g3cmct_init6;
+#define	VXGE_HAL_G3CMCT_INIT6_TWR_APRE2RD_DELAY(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TWR_APRE2WR_DELAY(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TWR_APRE2PRE_DELAY(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TWR_APRE2ACT_DELAY(val)	    vBIT(val, 28, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TRD_APRE2RD_DELAY(val)	    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TRD_APRE2WR_DELAY(val)	    vBIT(val, 44, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TRD_APRE2PRE_DELAY(val)	    vBIT(val, 52, 4)
+#define	VXGE_HAL_G3CMCT_INIT6_TRD_APRE2ACT_DELAY(val)	    vBIT(val, 60, 4)
+/* 0x029d0 */	u64	g3cmct_test0;
+#define	VXGE_HAL_G3CMCT_TEST0_TEST_START_RADD(val)	    vBIT(val, 2, 14)
+#define	VXGE_HAL_G3CMCT_TEST0_TEST_END_RADD(val)	    vBIT(val, 18, 14)
+#define	VXGE_HAL_G3CMCT_TEST0_TEST_START_CADD(val)	    vBIT(val, 37, 11)
+#define	VXGE_HAL_G3CMCT_TEST0_TEST_END_CADD(val)	    vBIT(val, 53, 11)
+/* 0x029d8 */	u64	g3cmct_test01;
+#define	VXGE_HAL_G3CMCT_TEST01_TEST_BANK(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3CMCT_TEST01_TEST_CTRL(val)		    vBIT(val, 12, 4)
+#define	VXGE_HAL_G3CMCT_TEST01_TEST_MODE		    mBIT(23)
+#define	VXGE_HAL_G3CMCT_TEST01_TEST_GO			    mBIT(31)
+#define	VXGE_HAL_G3CMCT_TEST01_TEST_DONE		    mBIT(39)
+#define	VXGE_HAL_G3CMCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val)  vBIT(val, 40, 16)
+#define	VXGE_HAL_G3CMCT_TEST01_TEST_DATA_ADDR		    mBIT(63)
+/* 0x029e0 */	u64	g3cmct_test1;
+#define	VXGE_HAL_G3CMCT_TEST1_TX_TEST_DATA(val)		    vBIT(val, 0, 64)
+/* 0x029e8 */	u64	g3cmct_test2;
+#define	VXGE_HAL_G3CMCT_TEST2_TX_TEST_DATA(val)		    vBIT(val, 0, 64)
+/* 0x029f0 */	u64	g3cmct_test11;
+#define	VXGE_HAL_G3CMCT_TEST11_TX_TEST_DATA1(val)	    vBIT(val, 0, 64)
+/* 0x029f8 */	u64	g3cmct_test21;
+#define	VXGE_HAL_G3CMCT_TEST21_TX_TEST_DATA1(val)	    vBIT(val, 0, 64)
+/* 0x02a00 */	u64	g3cmct_test3;
+#define	VXGE_HAL_G3CMCT_TEST3_ECC_DEC_RX_TEST_DATA(val)	    vBIT(val, 0, 64)
+/* 0x02a08 */	u64	g3cmct_test4;
+#define	VXGE_HAL_G3CMCT_TEST4_ECC_DEC_RX_TEST_DATA(val)	    vBIT(val, 0, 64)
+/* 0x02a10 */	u64	g3cmct_test31;
+#define	VXGE_HAL_G3CMCT_TEST31_ECC_DEC_RX_TEST_DATA1(val)   vBIT(val, 0, 64)
+/* 0x02a18 */	u64	g3cmct_test41;
+#define	VXGE_HAL_G3CMCT_TEST41_ECC_DEC_RX_TEST_DATA1(val)   vBIT(val, 0, 64)
+/* 0x02a20 */	u64	g3cmct_test5;
+#define	VXGE_HAL_G3CMCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
+/* 0x02a28 */	u64	g3cmct_test6;
+#define	VXGE_HAL_G3CMCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64)
+/* 0x02a30 */	u64	g3cmct_test51;
+#define	VXGE_HAL_G3CMCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
+							    vBIT(val, 0, 64)
+/* 0x02a38 */	u64	g3cmct_test61;
+#define	VXGE_HAL_G3CMCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\
+							    vBIT(val, 0, 64)
+/* 0x02a40 */	u64	g3cmct_test7;
+#define	VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14)
+#define	VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11)
+#define	VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8)
+/* 0x02a48 */	u64	g3cmct_test71;
+#define	VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14)
+#define	VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11)
+#define	VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8)
+/* 0x02a50 */	u64	g3cmct_init41;
+#define	VXGE_HAL_G3CMCT_INIT41_VENDOR_ID_U(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3CMCT_INIT41_ENABLE_CMU		    mBIT(15)
+/* 0x02a58 */	u64	g3cmct_test8;
+#define	VXGE_HAL_G3CMCT_TEST8_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64)
+/* 0x02a60 */	u64	g3cmct_test9;
+#define	VXGE_HAL_G3CMCT_TEST9_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64)
+/* 0x02a68 */	u64	g3cmct_test10;
+#define	VXGE_HAL_G3CMCT_TEST10_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64)
+/* 0x02a70 */	u64	g3cmct_test101;
+#define	VXGE_HAL_G3CMCT_TEST101_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64)
+/* 0x02a78 */	u64	g3cmct_test12;
+#define	VXGE_HAL_G3CMCT_TEST12_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\
+							    vBIT(val, 0, 64)
+/* 0x02a80 */	u64	g3cmct_test13;
+#define	VXGE_HAL_G3CMCT_TEST13_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\
+							    vBIT(val, 0, 64)
+/* 0x02a88 */	u64	g3cmct_test14;
+#define	VXGE_HAL_G3CMCT_TEST14_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\
+							    vBIT(val, 0, 64)
+/* 0x02a90 */	u64	g3cmct_test15;
+#define	VXGE_HAL_G3CMCT_TEST15_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\
+							    vBIT(val, 0, 64)
+/* 0x02a98 */	u64	g3cmct_test16;
+#define	VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_RADD_U(val)\
+							    vBIT(val, 0, 14)
+#define	VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_CADD_U(val)\
+							    vBIT(val, 19, 11)
+#define	VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_BANK_U(val)\
+							    vBIT(val, 32, 8)
+/* 0x02aa0 */	u64	g3cmct_test17;
+#define	VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_RADD1_U(val)\
+							    vBIT(val, 0, 14)
+#define	VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_CADD1_U(val)\
+							    vBIT(val, 19, 11)
+#define	VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_BANK1_U(val)\
+							    vBIT(val, 32, 8)
+/* 0x02aa8 */	u64	g3cmct_test18;
+#define	VXGE_HAL_G3CMCT_TEST18_ECC_DEC_U_TEST_FAIL_CNTR_U(val)\
+							    vBIT(val, 0, 16)
+/* 0x02ab0 */	u64	g3cmct_loop_back;
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_TDATA(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_MODE			    mBIT(39)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_GO			    mBIT(47)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_DONE			    mBIT(55)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_IDLE_VAL(val)	    vBIT(val, 56, 8)
+/* 0x02ab8 */	u64	g3cmct_loop_back1;
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_START_VAL(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_END_VAL(val)	    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_IDLE_VAL(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_START_VAL(val)	    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_END_VAL(val)	    vBIT(val, 33, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_STEPS(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MIN_FILTER(val)	    vBIT(val, 49, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MAX_FILTER(val)	    vBIT(val, 57, 7)
+/* 0x02ac0 */	u64	g3cmct_loop_back2;
+#define	VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MIN_FILTER(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MAX_FILTER(val)	    vBIT(val, 9, 7)
+/* 0x02ac8 */	u64	g3cmct_loop_back3;
+#define	VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_RESULT(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_WDLL_RESULT(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_RESULT(val) vBIT(val, 16, 8)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_WDLL_RESULT(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_MON_RESULT(val)\
+							    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_MON_RESULT(val)\
+							    vBIT(val, 40, 8)
+/* 0x02ad0 */	u64	g3cmct_loop_back4;
+#define	VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_U_PASS_FAILN(val) vBIT(val, 0, 32)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_L_PASS_FAILN(val) vBIT(val, 32, 32)
+/* 0x02ad8 */	u64	g3cmct_loop_back5;
+#define	VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_START_IO_VAL(val)   vBIT(val, 1, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_END_IO_VAL(val)	    vBIT(val, 9, 7)
+	u8	unused02b00[0x02b00 - 0x02ae0];
+
+/* 0x02b00 */	u64	g3cmct_loop_back_rdll[4];
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MIN_VAL(val)\
+							    vBIT(val, 33, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MAX_VAL(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MIN_VAL(val)\
+							    vBIT(val, 49, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MAX_VAL(val)\
+							    vBIT(val, 57, 7)
+/* 0x02b20 */	u64	g3cmct_loop_back_wdll[4];
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7)
+#define	VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7)
+/* 0x02b40 */	u64	g3cmct_tran_wrd_cnt;
+#define	VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val)	    vBIT(val, 32, 32)
+/* 0x02b48 */	u64	g3cmct_tran_ap_cnt;
+#define	VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_G3CMCT_TRAN_AP_CNT_UPDATE		    mBIT(39)
+/* 0x02b50 */	u64	g3cmct_g3bist;
+#define	VXGE_HAL_G3CMCT_G3BIST_DISABLE_MAIN		    mBIT(7)
+#define	VXGE_HAL_G3CMCT_G3BIST_DISABLE_ICTRL		    mBIT(15)
+#define	VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_MAIN(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_ICTRL(val)	    vBIT(val, 29, 3)
+	u8	unused03000[0x03000 - 0x02b58];
+
+/* 0x03000 */	u64	mc_int_status;
+#define	VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT		    mBIT(3)
+#define	VXGE_HAL_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT	    mBIT(7)
+#define	VXGE_HAL_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT	    mBIT(11)
+#define	VXGE_HAL_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT	    mBIT(15)
+/* 0x03008 */	u64	mc_int_mask;
+/* 0x03010 */	u64	mc_err_reg;
+#define	VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A	    mBIT(3)
+#define	VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B	    mBIT(4)
+#define	VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR	    mBIT(5)
+#define	VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0	    mBIT(6)
+#define	VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1	    mBIT(7)
+#define	VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A	    mBIT(10)
+#define	VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B	    mBIT(11)
+#define	VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR	    mBIT(12)
+#define	VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0	    mBIT(13)
+#define	VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1	    mBIT(14)
+#define	VXGE_HAL_MC_ERR_REG_MC_SM_ERR			    mBIT(15)
+/* 0x03018 */	u64	mc_err_mask;
+/* 0x03020 */	u64	mc_err_alarm;
+/* 0x03028 */	u64	grocrc_alarm_reg;
+#define	VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR	    mBIT(3)
+#define	VXGE_HAL_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR	    mBIT(7)
+/* 0x03030 */	u64	grocrc_alarm_mask;
+/* 0x03038 */	u64	grocrc_alarm_alarm;
+	u8	unused03100[0x03100 - 0x03040];
+
+/* 0x03100 */	u64	rx_thresh_cfg_repl;
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_0(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_1(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_2(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_3(val)	    vBIT(val, 40, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN	    mBIT(62)
+#define	VXGE_HAL_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ	    mBIT(63)
+/* 0x03108 */	u64	dbg_reg1_0;
+#define	VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_0_RP_QUEUE0_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_0_RP_QUEUE0_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03110 */	u64	dbg_reg1_1;
+#define	VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_1_RP_QUEUE1_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_1_RP_QUEUE1_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03118 */	u64	dbg_reg1_2;
+#define	VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_2_RP_QUEUE2_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_2_RP_QUEUE2_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03120 */	u64	dbg_reg1_3;
+#define	VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_3_RP_QUEUE3_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_3_RP_QUEUE3_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03128 */	u64	dbg_reg1_4;
+#define	VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_4_RP_QUEUE4_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_4_RP_QUEUE4_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03130 */	u64	dbg_reg1_5;
+#define	VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_5_RP_QUEUE5_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_5_RP_QUEUE5_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03138 */	u64	dbg_reg1_6;
+#define	VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_6_RP_QUEUE6_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_6_RP_QUEUE6_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03140 */	u64	dbg_reg1_7;
+#define	VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_NON_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_OFFLOAD_FRM_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG1_7_RP_QUEUE7_NON_OFFLOAD_XMFD_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG1_7_RP_QUEUE7_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16)
+/* 0x03148 */	u64	dbg_reg2;
+#define	VXGE_HAL_DBG_REG2_XFMDCNT_XFMD_AVAILABLE(val)	    vBIT(val, 6, 18)
+#define	VXGE_HAL_DBG_REG2_RP_FBMC_PTM_DATA_PHASES(val)	    vBIT(val, 24, 32)
+/* 0x03150 */	u64	dbg_reg3;
+#define	VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_QUEUE_STROBES(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_MC_STROBES(val) vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_QUEUE_SELECT(val) vBIT(val, 32, 16)
+#define	VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_MC_SELECT(val)  vBIT(val, 48, 16)
+/* 0x03158 */	u64	dbg_reg4;
+#define	VXGE_HAL_DBG_REG4_RP_FBMC_ONE_HEADERS(val)	    vBIT(val, 0, 16)
+/* 0x03160 */	u64	dbg_reg5;
+#define	VXGE_HAL_DBG_REG5_INCTRL_TOTAL_ING_FRMS(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_DBG_REG5_RP_TOTAL_EGR_FRMS(val)	    vBIT(val, 32, 32)
+	u8	unused03200[0x03200 - 0x03168];
+
+/* 0x03200 */	u64	rx_queue_cfg;
+#define	VXGE_HAL_RX_QUEUE_CFG_QUEUE_SIZE_ENABLE		    mBIT(39)
+#define	VXGE_HAL_RX_QUEUE_CFG_INGRESS_FIFO_THR(val)	    vBIT(val, 60, 4)
+/* 0x03208 */	u64	rx_queue_size_q[15];
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q_SIZE(val)		    vBIT(val, 0, 24)
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q_LAST_ADD(val)		    vBIT(val, 24, 24)
+/* 0x03280 */	u64	rx_queue_size_q15;
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q15_SIZE(val)		    vBIT(val, 0, 24)
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q15_LAST_ADD(val)	    vBIT(val, 24, 24)
+/* 0x03288 */	u64	rx_queue_size_q16;
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q16_SIZE(val)		    vBIT(val, 0, 24)
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q16_LAST_ADD(val)	    vBIT(val, 24, 24)
+/* 0x03290 */	u64	rx_queue_size_q17;
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q17_SIZE(val)		    vBIT(val, 0, 24)
+#define	VXGE_HAL_RX_QUEUE_SIZE_Q17_LAST_ADD(val)	    vBIT(val, 24, 24)
+	u8	unused032a0[0x032a0 - 0x03298];
+
+/* 0x032a0 */	u64	rx_queue_start_q0;
+#define	VXGE_HAL_RX_QUEUE_START_Q0_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q0_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q0_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q0_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q0_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032a8 */	u64	rx_queue_start_q1;
+#define	VXGE_HAL_RX_QUEUE_START_Q1_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q1_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q1_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q1_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q1_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032b0 */	u64	rx_queue_start_q2;
+#define	VXGE_HAL_RX_QUEUE_START_Q2_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q2_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q2_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q2_FDP_OFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q2_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032b8 */	u64	rx_queue_start_q3;
+#define	VXGE_HAL_RX_QUEUE_START_Q3_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q3_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q3_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q3_FDP_OFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q3_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032c0 */	u64	rx_queue_start_q4;
+#define	VXGE_HAL_RX_QUEUE_START_Q4_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q4_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q4_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q4_FDP_OFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q4_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032c8 */	u64	rx_queue_start_q5;
+#define	VXGE_HAL_RX_QUEUE_START_Q5_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q5_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q5_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q5_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q5_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032d0 */	u64	rx_queue_start_q6;
+#define	VXGE_HAL_RX_QUEUE_START_Q6_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q6_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q6_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q6_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q6_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032d8 */	u64	rx_queue_start_q7;
+#define	VXGE_HAL_RX_QUEUE_START_Q7_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q7_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q7_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q7_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+#define	VXGE_HAL_RX_QUEUE_START_Q7_FDP_NONOFFLOAD_OUTST_FRMS(val)\
+							    vBIT(val, 55, 9)
+/* 0x032e0 */	u64	rx_queue_start_q8;
+#define	VXGE_HAL_RX_QUEUE_START_Q8_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q8_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q8_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q8_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+/* 0x032e8 */	u64	rx_queue_start_q9;
+#define	VXGE_HAL_RX_QUEUE_START_Q9_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q9_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q9_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q9_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+/* 0x032f0 */	u64	rx_queue_start_q10;
+#define	VXGE_HAL_RX_QUEUE_START_Q10_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q10_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q10_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q10_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+/* 0x032f8 */	u64	rx_queue_start_q11;
+#define	VXGE_HAL_RX_QUEUE_START_Q11_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q11_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q11_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q11_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+/* 0x03300 */	u64	rx_queue_start_q12;
+#define	VXGE_HAL_RX_QUEUE_START_Q12_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q12_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q12_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q12_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+/* 0x03308 */	u64	rx_queue_start_q13;
+#define	VXGE_HAL_RX_QUEUE_START_Q13_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q13_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q13_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q13_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9)
+/* 0x03310 */	u64	rx_queue_start_q14;
+#define	VXGE_HAL_RX_QUEUE_START_Q14_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q14_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q14_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q14_FDP_OFFLOAD_OUTST_FRMS(val)	vBIT(val, 39, 9)
+/* 0x03318 */	u64	rx_queue_start_q15;
+#define	VXGE_HAL_RX_QUEUE_START_Q15_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q15_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q15_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q15_FDP_OFFLOAD_OUTST_FRMS(val)	vBIT(val, 39, 9)
+/* 0x03320 */	u64	rx_queue_start_q16;
+#define	VXGE_HAL_RX_QUEUE_START_Q16_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q16_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q16_SROW(val)		    vBIT(val, 18, 14)
+#define	VXGE_HAL_RX_QUEUE_START_Q16_FDP_OFFLOAD_OUTST_FRMS(val)	vBIT(val, 39, 9)
+/* 0x03328 */	u64	rx_queue_start_q17;
+#define	VXGE_HAL_RX_QUEUE_START_Q17_QUEUE_BANKS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_RX_QUEUE_START_Q17_SBANK(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_RX_QUEUE_START_Q17_SROW(val)		    vBIT(val, 18, 14)
+/* 0x03330 */	u64	fm_definition;
+#define	VXGE_HAL_FM_DEFINITION_FM_SIZE(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_FM_DEFINITION_FM_COLUMNS(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_FM_DEFINITION_QUEUE_SPAV_MARGIN(val)	    vBIT(val, 16, 8)
+	u8	unused03380[0x03380 - 0x03338];
+
+/* 0x03380 */	u64	traffic_ctrl;
+#define	VXGE_HAL_TRAFFIC_CTRL_BLOCK_ING_PATH		    mBIT(7)
+#define	VXGE_HAL_TRAFFIC_CTRL_BLOCK_EGR_PATH		    mBIT(15)
+#define	VXGE_HAL_TRAFFIC_CTRL_OFFLOAD_MAX_FRAMES(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_TRAFFIC_CTRL_NOFFLOAD_MAX_FRAMES(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_TRAFFIC_CTRL_MSP_MAX_FRAMES(val)	    vBIT(val, 40, 8)
+/* 0x03388 */	u64	xfmd_arb_ctrl;
+#define	VXGE_HAL_XFMD_ARB_CTRL_ISTAGE_MASK		    mBIT(7)
+#define	VXGE_HAL_XFMD_ARB_CTRL_EN_OFF(val)		    vBIT(val, 15, 17)
+#define	VXGE_HAL_XFMD_ARB_CTRL_EN_NOFF(val)		    vBIT(val, 39, 17)
+/* 0x03390 */	u64	xfmd_arb_ctrl1;
+#define	VXGE_HAL_XFMD_ARB_CTRL1_PROMOTE_NOFF(val)	    vBIT(val, 6, 18)
+/* 0x03398 */	u64	rd_tranc_ctrl;
+#define	VXGE_HAL_RD_TRANC_CTRL_ARB(val)			    vBIT(val, 4, 4)
+/* 0x033a0 */	u64	fm_arb;
+#define	VXGE_HAL_FM_ARB_CTRL(val)			    vBIT(val, 0, 8)
+#define	VXGE_HAL_FM_ARB_TIMER(val)			    vBIT(val, 8, 8)
+#define	VXGE_HAL_FM_ARB_EN_QHIST(val)			    vBIT(val, 16, 8)
+#define	VXGE_HAL_FM_ARB_ACT_ARB_QHIST(val)		    vBIT(val, 28, 4)
+#define	VXGE_HAL_FM_ARB_QHIST_CNT(val)			    vBIT(val, 32, 16)
+#define	VXGE_HAL_FM_ARB_WR_DELAY_CNT(val)		    vBIT(val, 52, 4)
+#define	VXGE_HAL_FM_ARB_WR_WINDOW_CNT(val)		    vBIT(val, 56, 8)
+/* 0x033a8 */	u64	arb;
+#define	VXGE_HAL_ARB_HP_CAL(val)			    vBIT(val, 0, 8)
+#define	VXGE_HAL_ARB_XFMD_LAST_MASK(val)		    vBIT(val, 11, 5)
+#define	VXGE_HAL_ARB_HP_XFMD_PRI(val)			    vBIT(val, 22, 2)
+/* 0x033b0 */	u64	settings0;
+#define	VXGE_HAL_SETTINGS0_CTRL_FIFO_THR(val)		    vBIT(val, 4, 4)
+/* 0x033b8 */	u64	fbmc_ecc_cfg;
+#define	VXGE_HAL_FBMC_ECC_CFG_ENABLE(val)		    vBIT(val, 3, 5)
+	u8	unused03400[0x03400 - 0x033c0];
+
+/* 0x03400 */	u64	pcipif_int_status;
+#define	VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT  mBIT(3)
+#define	VXGE_HAL_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT  mBIT(7)
+#define	VXGE_HAL_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT mBIT(11)
+#define	VXGE_HAL_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT mBIT(15)
+#define	VXGE_HAL_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT mBIT(19)
+/* 0x03408 */	u64	pcipif_int_mask;
+/* 0x03410 */	u64	dbecc_err_reg;
+#define	VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR	    mBIT(3)
+#define	VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR	    mBIT(7)
+#define	VXGE_HAL_DBECC_ERR_REG_PCI_P_HDR_DB_ERR		    mBIT(11)
+#define	VXGE_HAL_DBECC_ERR_REG_PCI_P_DATA_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR	    mBIT(19)
+#define	VXGE_HAL_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR	    mBIT(23)
+/* 0x03418 */	u64	dbecc_err_mask;
+/* 0x03420 */	u64	dbecc_err_alarm;
+/* 0x03428 */	u64	sbecc_err_reg;
+#define	VXGE_HAL_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR	    mBIT(3)
+#define	VXGE_HAL_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_SBECC_ERR_REG_PCI_P_HDR_SG_ERR		    mBIT(11)
+#define	VXGE_HAL_SBECC_ERR_REG_PCI_P_DATA_SG_ERR	    mBIT(15)
+#define	VXGE_HAL_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR	    mBIT(19)
+#define	VXGE_HAL_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR	    mBIT(23)
+/* 0x03430 */	u64	sbecc_err_mask;
+/* 0x03438 */	u64	sbecc_err_alarm;
+/* 0x03440 */	u64	general_err_reg;
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG    mBIT(3)
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG   mBIT(7)
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR	    mBIT(11)
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE  mBIT(15)
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET	    mBIT(19)
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET	    mBIT(23)
+#define	VXGE_HAL_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP	    mBIT(27)
+/* 0x03448 */	u64	general_err_mask;
+/* 0x03450 */	u64	general_err_alarm;
+/* 0x03458 */	u64	srpcim_msg_reg;
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT	mBIT(0)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT	mBIT(1)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT	mBIT(2)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT	mBIT(3)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT	mBIT(4)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT	mBIT(5)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT	mBIT(6)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT	mBIT(7)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT	mBIT(8)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT	mBIT(9)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT	mBIT(10)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT	mBIT(11)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT	mBIT(12)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT	mBIT(13)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT	mBIT(14)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT	mBIT(15)
+#define	VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT	mBIT(16)
+/* 0x03460 */	u64	srpcim_msg_mask;
+/* 0x03468 */	u64	srpcim_msg_alarm;
+	u8	unused03600[0x03600 - 0x03470];
+
+/* 0x03600 */	u64	gcmg1_int_status;
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT	    mBIT(0)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT    mBIT(1)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT    mBIT(2)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT    mBIT(3)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT    mBIT(4)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT    mBIT(5)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT    mBIT(6)
+#define	VXGE_HAL_GCMG1_INT_STATUS_UQM_ERR_UQM_INT	    mBIT(7)
+#define	VXGE_HAL_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT	    mBIT(8)
+/* 0x03608 */	u64	gcmg1_int_mask;
+/* 0x03610 */	u64	gsscc_err_reg;
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_SG_ERR(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_SG_ERR(val)	    vBIT(val, 10, 6)
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_OVERLAPPING_SYNC_ERR    mBIT(23)
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(val)	    vBIT(val, 38, 2)
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(val)	    vBIT(val, 42, 6)
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2STE_UFLOW_ERR	    mBIT(55)
+#define	VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2TTE_UFLOW_ERR	    mBIT(63)
+/* 0x03618 */	u64	gsscc_err_mask;
+/* 0x03620 */	u64	gsscc_err_alarm;
+/* 0x03628 */	u64	gssc_err0_reg[3];
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_SG_ERR(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_SG_ERR(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_SG_ERR(val)    vBIT(val, 22, 2)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_SG_ERR(val)    vBIT(val, 26, 6)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(val)	    vBIT(val, 44, 4)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(val)    vBIT(val, 54, 2)
+#define	VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(val)    vBIT(val, 58, 6)
+/* 0x03630 */	u64	gssc_err0_mask[3];
+/* 0x03638 */	u64	gssc_err0_alarm[3];
+/* 0x03670 */	u64	gssc_err1_reg[3];
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR	    mBIT(0)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SCREQ_ERR		    mBIT(1)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_OFLOW_ERR	    mBIT(2)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_R_WN_ERR	    mBIT(3)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_UFLOW_ERR	    mBIT(4)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_OFLOW_ERR	    mBIT(5)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_UFLOW_ERR	    mBIT(6)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_OFLOW_ERR	    mBIT(7)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_UFLOW_ERR	    mBIT(8)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_OFLOW_ERR	    mBIT(9)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_UFLOW_ERR	    mBIT(10)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_OFLOW_ERR	    mBIT(11)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_R_WN_ERR	    mBIT(12)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_UFLOW_ERR	    mBIT(13)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_OFLOW_ERR	    mBIT(14)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_UFLOW_ERR	    mBIT(15)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_OFLOW_ERR	    mBIT(16)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_R_WN_ERR	    mBIT(17)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_UFLOW_ERR	    mBIT(18)
+#define	VXGE_HAL_GSSC_ERR1_REG_SSCC_SCRESP_ERR		    mBIT(19)
+/* 0x03678 */	u64	gssc_err1_mask[3];
+/* 0x03680 */	u64	gssc_err1_alarm[3];
+/* 0x036b8 */	u64	gqcc_err_reg;
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_SG_ERR(val)  vBIT(val, 0, 4)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_SG_ERR(val)  vBIT(val, 4, 4)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_DB_ERR(val)  vBIT(val, 8, 4)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_DB_ERR(val)  vBIT(val, 12, 4)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCMREQCMD_FIFO_ERR    mBIT(16)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCMREQDAT_FIFO_ERR    mBIT(17)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM_CAM_FIFO_PUSH_ERR mBIT(18)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM_CAM_EIP_FIFO_PUSH_ERR	mBIT(19)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM2CMA_FIFO_POP_ERR  mBIT(20)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM_CAM_FIFO_PUSH_ERR mBIT(24)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM_CAM_EIP_FIFO_PUSH_ERR	mBIT(25)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM2CMA_LP_FIFO_POP_ERR mBIT(26)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM2CMA_HP_FIFO_POP_ERR mBIT(27)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_WSE2CMA_FIFO_POP_ERR  mBIT(28)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_RRP2CMA_LP_FIFO_POP_ERR mBIT(29)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_RRP2CMA_HP_FIFO_POP_ERR mBIT(30)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_IPWOGRRESP_FIFO_POP_ERR mBIT(31)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPRPEDAT_FIFO_ERR	    mBIT(32)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPWRRESP_FIFO_PUSH_ERR mBIT(33)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPCMCREQCMD_ERR	    mBIT(34)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_HPCMCREQCMD_ERR	    mBIT(35)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMCREQDAT_ERR	    mBIT(36)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CMR_SM_ERR	    mBIT(41)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CAR_SM_ERR	    mBIT(42)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_HCMR_SM_ERR	    mBIT(43)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_LCMR_SM_ERR	    mBIT(44)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_CAR_SM_ERR	    mBIT(45)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CMR_INFO_ERR	    mBIT(55)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_WSE_WQE_RD_ERR    mBIT(56)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2WGM_NEXT_WQE_PTR_ERR mBIT(57)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2RLM_RMV_DATA_ERR  mBIT(58)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2DLM_RMV_DATA_ERR  mBIT(59)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2ELM_RMV_DATA_ERR  mBIT(60)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2CGM_CQEGRP_ROW_DATA_ERR mBIT(61)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2RLM_RMV_DATA_ERR  mBIT(62)
+#define	VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2ELM_RMV_DATA_ERR  mBIT(63)
+/* 0x036c0 */	u64	gqcc_err_mask;
+/* 0x036c8 */	u64	gqcc_err_alarm;
+/* 0x036d0 */	u64	uqm_err_reg;
+#define	VXGE_HAL_UQM_ERR_REG_UQM_UQM_CMCREQ_ECC_SG_ERR	    mBIT(0)
+#define	VXGE_HAL_UQM_ERR_REG_UQM_UQM_CMCREQ_ECC_DB_ERR	    mBIT(1)
+#define	VXGE_HAL_UQM_ERR_REG_UQM_UQM_SM_ERR		    mBIT(8)
+/* 0x036d8 */	u64	uqm_err_mask;
+/* 0x036e0 */	u64	uqm_err_alarm;
+/* 0x036e8 */	u64	sscc_config;
+#define	VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_MSB(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_LSB(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_SSCC_CONFIG_TIMEOUT_VALUE(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_SSCC_CONFIG_ALLOW_NOTFOUND_CACHING	    mBIT(39)
+#define	VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_MSB(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_LSB(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_SSCC_CONFIG_NULL_LOOKUP		    mBIT(63)
+/* 0x036f0 */	u64	sscc_mask_0;
+#define	VXGE_HAL_SSCC_MASK_0_IPV6_SA_TOP(val)		    vBIT(val, 0, 64)
+/* 0x036f8 */	u64	sscc_mask_1;
+#define	VXGE_HAL_SSCC_MASK_1_IPV6_SA_BOTTOM(val)	    vBIT(val, 0, 64)
+/* 0x03700 */	u64	sscc_mask_2;
+#define	VXGE_HAL_SSCC_MASK_2_IPV6_DA_TOP(val)		    vBIT(val, 0, 64)
+/* 0x03708 */	u64	sscc_mask_3;
+#define	VXGE_HAL_SSCC_MASK_3_IPV6_DA_BOTTOM(val)	    vBIT(val, 0, 64)
+/* 0x03710 */	u64	sscc_mask_4;
+#define	VXGE_HAL_SSCC_MASK_4_IPV4_SA(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_SSCC_MASK_4_IPV4_DA(val)		    vBIT(val, 32, 32)
+/* 0x03718 */	u64	sscc_mask_5;
+#define	VXGE_HAL_SSCC_MASK_5_TCP_SP(val)		    vBIT(val, 0, 16)
+#define	VXGE_HAL_SSCC_MASK_5_TCP_DP(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_SSCC_MASK_5_VLANID(val)		    vBIT(val, 52, 12)
+/* 0x03720 */	u64	gcmg1_ecc;
+#define	VXGE_HAL_GCMG1_ECC_ENABLE_SSCC_N		    mBIT(7)
+#define	VXGE_HAL_GCMG1_ECC_ENABLE_UQM_N	mBIT(15)
+#define	VXGE_HAL_GCMG1_ECC_ENABLE_QCC_N	mBIT(23)
+	u8	unused03a00[0x03a00 - 0x03728];
+
+/* 0x03a00 */	u64	pcmg1_int_status;
+#define	VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT	    mBIT(0)
+#define	VXGE_HAL_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT	    mBIT(1)
+#define	VXGE_HAL_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT mBIT(2)
+#define	VXGE_HAL_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT mBIT(3)
+/* 0x03a08 */	u64	pcmg1_int_mask;
+/* 0x03a10 */	u64	psscc_err_reg;
+#define	VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR	    mBIT(0)
+#define	VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2TTE_OFLOW_ERR	    mBIT(1)
+/* 0x03a18 */	u64	psscc_err_mask;
+/* 0x03a20 */	u64	psscc_err_alarm;
+/* 0x03a28 */	u64	pqcc_err_reg;
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_SQM_MAX_WQE_GRP_INFO_ERR  mBIT(0)
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_SQM_WQE_FREE_LIST_EMPTY_INFO_ERR  mBIT(1)
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_SQM_FLM_WQE_ID_FIFO_ERR   mBIT(2)
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_SQM_CACHE_FULL_INFO_ERR   mBIT(3)
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_QCC_PDA_ARB_SM_ERR	    mBIT(32)
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_QCC_CP_ARB_SM_ERR	    mBIT(33)
+#define	VXGE_HAL_PQCC_ERR_REG_QCC_QCC_CXP2QCC_FIFO_ERR	    mBIT(63)
+/* 0x03a30 */	u64	pqcc_err_mask;
+/* 0x03a38 */	u64	pqcc_err_alarm;
+/* 0x03a40 */	u64	pqcc_cqm_err_reg;
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_DMACQERSP_SG_ERR  mBIT(4)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_DB_ERR(val) vBIT(val, 8, 4)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_DMACQERSP_DB_ER   mBIT(12)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_RMW_FIFO_ERR  mBIT(16)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_FIFO_ERR  mBIT(17)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_CAM_FIFO_POP_ERR mBIT(18)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_CAM_EIP_FIFO_POP_ERR mBIT(19)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM2CMA_FIFO_PUSH_ERR	mBIT(20)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_HPRPEREQ_FIFO_ERR mBIT(21)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_LPRPEREQ_FIFO_ERR mBIT(22)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_LPRPERSP_FIFO_ERR mBIT(23)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_USDC_DBELL_FIFO_ERR   mBIT(24)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CXP_MSG_IN_FIFO_ERR   mBIT(25)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CXP_MSG_OUT_FIFO_ERR  mBIT(26)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_FIFO_ERR  mBIT(27)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CGM_CCM_REQ_FIFO_ERR mBIT(28)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_EXCESSIVE_RD_RESP_ERR mBIT(29)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CDR_SERR	    mBIT(32)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_FLM_SM_ERR    mBIT(33)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_CRP_SM_ERR    mBIT(34)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_ARB_SM_ERR    mBIT(35)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_RCL_SM_ERR    mBIT(36)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CIN_SM_ERR    mBIT(37)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CSE_SM_ERR	    mBIT(38)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_SM_ERR	    mBIT(39)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_SM_ERR    mBIT(40)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_ADD_SM_ERR mBIT(41)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_SM_ERR    mBIT(42)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_ADD_SM_ERR mBIT(43)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_FULL_INFO_ERR mBIT(58)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_MAX_CQE_GRP_INFO_ERR mBIT(59)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CDR_SM_INFO_ERR   mBIT(60)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_BAD_CIN_INFO_ERR  mBIT(61)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_NO_CQE_GRP_INFO_ERR mBIT(62)
+#define	VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_BAD_VPIN_INFO_ERR mBIT(63)
+/* 0x03a48 */	u64	pqcc_cqm_err_mask;
+/* 0x03a50 */	u64	pqcc_cqm_err_alarm;
+/* 0x03a58 */	u64	pqcc_sqm_err_reg;
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_SG_ERR(val) vBIT(val, 4, 4)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_DMAWQERSP_SG_ERR  mBIT(8)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RPEREQDAT_SG_ERR  mBIT(9)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_BAD_VPIN_INFO_ERR mBIT(10)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WDR_SM_INFO_ERR   mBIT(11)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_BAD_SIN_INFO_ERR  mBIT(12)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_EXCESSIVE_RD_RESP_ERR	mBIT(13)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_DMAWQERSP_DB_ERR  mBIT(14)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RPEREQDAT_DB_ERR  mBIT(15)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_DB_ERR(val) vBIT(val, 16, 4)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_DB_ERR(val) vBIT(val, 20, 4)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_FIFO_ERR  mBIT(24)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_CAM_FIFO_POP_ERR mBIT(25)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_CAM_EIP_FIFO_POP_ERR mBIT(26)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM2CMA_LP_FIFO_PUSH_ERR mBIT(27)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM2CMA_HP_FIFO_PUSH_ERR mBIT(28)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WSE2CMA_FIFO_PUSH_ERR mBIT(29)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP2CMA_LP_FIFO_PUSH_ERR mBIT(30)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP2CMA_HP_FIFO_PUSH_ERR mBIT(31)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_HPRPEREQ_FIFO_ERR mBIT(32)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_IPWOGRREQSB_FIFO_ERR mBIT(33)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_IPWOGRRESP_FIFO_POP_ERR mBIT(34)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_FIFO_ERR	mBIT(35)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEREQ_FIFO_ERR	mBIT(36)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPERESP_FIFO_ERR	mBIT(37)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPERESPSB_FIFO_ERR	mBIT(38)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPWRREQSB_FIFO_ERR	mBIT(39)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPWRRESP_FIFO_POP_ERR	mBIT(40)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_SWRRESP_FIFO_ERR	mBIT(41)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_RPE_REQ_FIFO_ERR	mBIT(42)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_RPE_LASTOD_FIFO_ERR mBIT(43)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_USDC_DBELL_FIFO_ERR mBIT(44)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CXP_MSG_IN_FIFO_ERR mBIT(45)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CXP_MSG_OUT_FIFO_ERR mBIT(46)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_RMW_FIFO_ERR	mBIT(47)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_FIFO_ERR	mBIT(48)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_FIFO_ERR	mBIT(49)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP_RESPDATA_ARB_SM_ERR mBIT(50)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WDR_SERR		mBIT(51)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMA_RLP_SM_ERR	mBIT(52)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_FLM_SM_ERR	mBIT(53)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_RCL_SM_ERR	mBIT(54)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CIN_SM_ERR	mBIT(55)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WSE_SM_ERR		mBIT(56)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_SM_ERR		mBIT(57)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_SM_ERR	mBIT(58)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_ADD_SM_ERR	mBIT(59)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_SM_ERR	mBIT(60)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_ADD_SM_ERR	mBIT(61)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_SM_ERR	mBIT(62)
+#define	VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_ADD_SM_ERR	mBIT(63)
+/* 0x03a60 */	u64	pqcc_sqm_err_mask;
+/* 0x03a68 */	u64	pqcc_sqm_err_alarm;
+/* 0x03a70 */	u64	qcc_srq_cqrq;
+#define	VXGE_HAL_QCC_SRQ_CQRQ_POLL_TIMER(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_QCC_SRQ_CQRQ_MAX_EOL_POLLS(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_QCC_SRQ_CQRQ_CONSERVATIVE_SM_CRD_RTN	    mBIT(47)
+/* 0x03a78 */	u64	qcc_err_policy;
+#define	VXGE_HAL_QCC_ERR_POLICY_CQM_CQE(val)		    vBIT(val, 4, 4)
+#define	VXGE_HAL_QCC_ERR_POLICY_SQM_WQE(val)		    vBIT(val, 12, 4)
+#define	VXGE_HAL_QCC_ERR_POLICY_SQM_SRQIR(val)		    vBIT(val, 22, 2)
+/* 0x03a80 */	u64	qcc_bp_ctrl;
+#define	VXGE_HAL_QCC_BP_CTRL_RD_XON			    mBIT(7)
+/* 0x03a88 */	u64	pcmg1_ecc;
+#define	VXGE_HAL_PCMG1_ECC_ENABLE_QCC_N			    mBIT(23)
+/* 0x03a90 */	u64	qcc_cqm_cqrq_id;
+#define	VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_VPIN_CQRQ_ID(val)  vBIT(val, 0, 16)
+#define	VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_CIN_CQRQ_ID(val)   vBIT(val, 16, 16)
+#define	VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_MAX_CQE_GRP_CQRQ_ID(val) vBIT(val, 32, 16)
+#define	VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_CQM_CDR_CQRQ_ID(val)   vBIT(val, 48, 16)
+/* 0x03a98 */	u64	qcc_sqm_srq_id;
+#define	VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_VPIN_SRQ_ID(val)    vBIT(val, 0, 16)
+#define	VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_SIN_SRQ_ID(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_QCC_SQM_SRQ_ID_SQM_MAX_WQE_GRP_SRQ_ID(val) vBIT(val, 32, 16)
+#define	VXGE_HAL_QCC_SQM_SRQ_ID_SQM_SQM_WDR_SRQ_ID(val)	    vBIT(val, 48, 16)
+/* 0x03aa0 */	u64	qcc_cqm_flm_id;
+#define	VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_CCM_STATE_SERR(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_HEAD_CQEGRP_ID(val) vBIT(val, 8, 24)
+#define	VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_TAIL_CQEGRP_ID(val)\
+							    vBIT(val, 40, 24)
+/* 0x03aa8 */	u64	qcc_sqm_flm_id;
+#define	VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_NO_WQE_OD_GRP_AVAIL mBIT(0)
+#define	VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_CCM_STATE_SERR(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_HEAD_WQEGRP_ID(val) vBIT(val, 8, 24)
+#define	VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_TAIL_WQEGRP_ID(val)\
+							    vBIT(val, 40, 24)
+	u8	unused04000[0x04000 - 0x03ab0];
+
+/* 0x04000 */	u64	one_int_status;
+#define	VXGE_HAL_ONE_INT_STATUS_RXPE_ERR_RXPE_INT	    mBIT(7)
+#define	VXGE_HAL_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT\
+							    mBIT(13)
+#define	VXGE_HAL_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT\
+							    mBIT(14)
+#define	VXGE_HAL_ONE_INT_STATUS_TXPE_ERR_TXPE_INT	    mBIT(15)
+#define	VXGE_HAL_ONE_INT_STATUS_DLM_ERR_DLM_INT		    mBIT(23)
+#define	VXGE_HAL_ONE_INT_STATUS_PE_ERR_PE_INT		    mBIT(31)
+#define	VXGE_HAL_ONE_INT_STATUS_RPE_ERR_RPE_INT		    mBIT(39)
+#define	VXGE_HAL_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT	    mBIT(47)
+#define	VXGE_HAL_ONE_INT_STATUS_OES_ERR_OES_INT		    mBIT(55)
+/* 0x04008 */	u64	one_int_mask;
+/* 0x04010 */	u64	rpe_err_reg;
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_DB_ERR(val)	    vBIT(val, 0, 4)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_DB_ERR(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_DB_ERR	    mBIT(8)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_DB_ERR	    mBIT(9)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCQ_DB_ERR		    mBIT(10)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_DB_ERR	    mBIT(11)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_SG_ERR(val)	    vBIT(val, 16, 4)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_SG_ERR(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_SG_ERR	    mBIT(24)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_SG_ERR	    mBIT(25)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCQ_SG_ERR		    mBIT(26)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_SG_ERR	    mBIT(27)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_CTXTRDRQ_FIFO_ERR	    mBIT(32)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_CTXTWRRQ_FIFO_ERR	    mBIT(33)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQRQLDRQ_FIFO_ERR	    mBIT(34)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_SRQLDRQ_FIFO_ERR	    mBIT(35)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQERDRQ_FIFO_ERR	    mBIT(36)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQEWRRQ_FIFO_ERR	    mBIT(37)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQEAVAILRQ_FIFO_ERR    mBIT(38)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQECOMPL_FIFO_ERR	    mBIT(39)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQEADDRRQ_FIFO_ERR	    mBIT(40)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCC_CTXTLDNT_FIFO_ERR	    mBIT(41)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCC_RCCRESP_FIFO_ERR	    mBIT(42)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_QEM_OESPREINIT_FIFO_ERR    mBIT(43)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_QEM_EVENT_FIFO_ERR	    mBIT(44)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_QEM_WQELDNT_FIFO_ERR	    mBIT(45)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_QEM_QEMRESP_FIFO_ERR	    mBIT(46)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_QEM_PDM_CMD_FIFO_ERR	    mBIT(47)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_CMDRESP_FIFO_ERR	    mBIT(48)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_FIFO_ERR	    mBIT(49)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_EPE_SPQ_FIFO_ERR	    mBIT(50)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_EPE_STCRESP_FIFO_ERR   mBIT(51)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_RIM_RIMIPB_FIFO_ERR    mBIT(52)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCI_MCQLEN_FIFO_ERR	    mBIT(53)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCI_PCQLEN_FIFO_ERR	    mBIT(54)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCI_RDLIM_FIFO_ERR	    mBIT(55)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_MSG_RCMD_FIFO_ERR	    mBIT(56)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_DLM_RCMD_FIFO_ERR	    mBIT(57)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_FIFO_ERR	    mBIT(58)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCQ_FIFO_ERR		    mBIT(59)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCO_CQE_FIFO_ERR	    mBIT(60)
+#define	VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_FIFO_ERR	    mBIT(61)
+/* 0x04018 */	u64	rpe_err_mask;
+/* 0x04020 */	u64	rpe_err_alarm;
+/* 0x04028 */	u64	pe_err_reg;
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PA_SG_ERR	    mBIT(0)
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PB_SG_ERR	    mBIT(1)
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_SG_ERR		    mBIT(2)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_RDFIFO_STATE_SM_ERR mBIT(8)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_STATE_SM_ERR	    mBIT(9)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTWRQ_ADDR_STATE_SM_ERR mBIT(10)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTWRQ_DATA_STATE_SM_ERR mBIT(11)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_DLM_CTXT_STATE_SM_ERR    mBIT(12)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RDMEM_ADDR_STATE_SM_ERR  mBIT(13)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RDMEM_DATA_STATE_SM_ERR  mBIT(14)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RDRESP_STATE_SM_ERR	    mBIT(15)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_RDCTXT_DATA_STATE_SM_ERR mBIT(16)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RXPEIF_STATE_SM_ERR	    mBIT(17)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_TCM_CTXT_STATE_SM_ERR    mBIT(18)
+#define	VXGE_HAL_PE_ERR_REG_PE_SCC_CTXT_CNTRL_SM_ERR	    mBIT(19)
+#define	VXGE_HAL_PE_ERR_REG_PE_SCC_RECALL_SM_ERR	    mBIT(20)
+#define	VXGE_HAL_PE_ERR_REG_PE_SCC_NCE_FETCH_STATE_SM_ERR   mBIT(21)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NCE_CNTRL_SM_ERR	    mBIT(22)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_MEMCNTRL_STATE_SM_ERR	mBIT(23)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NRRQ_RDFIFO_STATE_SM_ERR	mBIT(24)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NRRQ_STATE_SM_ERR    mBIT(25)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NWRQ_RDFIFO_STATE_SM_ERR	mBIT(26)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_RDMEM_DATA_STATE_SM_ERR	mBIT(27)
+#define	VXGE_HAL_PE_ERR_REG_PE_CMGIF_HDREQ_ARB_STATE_SM_ERR	mBIT(28)
+#define	VXGE_HAL_PE_ERR_REG_PE_CMGIF_HNREQ_ARB_STATE_SM_ERR	mBIT(29)
+#define	VXGE_HAL_PE_ERR_REG_PE_CMGIF_LDREQ_ARB_STATE_SM_ERR	mBIT(30)
+#define	VXGE_HAL_PE_ERR_REG_PE_CMGIF_LNREQ_ARB_STATE_SM_ERR	mBIT(31)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_FIFO_ERR	    mBIT(32)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXT_FIFO_ERR	    mBIT(33)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_CTXT_WR_PHASE_ERR   mBIT(34)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_CTXT_RD_PHASE_ERR   mBIT(35)
+#define	VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_RD_RESP_PHASE_ERR mBIT(36)
+#define	VXGE_HAL_PE_ERR_REG_PE_NDP_NRRQ_FIFO_ERR	    mBIT(37)
+#define	VXGE_HAL_PE_ERR_REG_PE_NDP_NWRQ_FIFO_ERR	    mBIT(38)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_WRMEM_PHASE_ERR	    mBIT(39)
+#define	VXGE_HAL_PE_ERR_REG_PE_NCC_PE_RESP_CMD_PHASE_ERR    mBIT(40)
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_SM_ERR		    mBIT(48)
+#define	VXGE_HAL_PE_ERR_REG_PE_PET_MEM_ARB_ERR		    mBIT(49)
+#define	VXGE_HAL_PE_ERR_REG_PE_PET_UPDATE_FSM_ERR	    mBIT(50)
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PA_DB_ERR	    mBIT(61)
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PB_DB_ERR	    mBIT(62)
+#define	VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_DB_ERR		    mBIT(63)
+/* 0x04030 */	u64	pe_err_mask;
+/* 0x04038 */	u64	pe_err_alarm;
+/* 0x04040 */	u64	rxpe_err_reg;
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_FRM_SG_ERR	    mBIT(0)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_FRM_SG_ERR	    mBIT(1)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_FPDU_MEM_SG_ERR	    mBIT(2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_SG_ERR(val)	    vBIT(val, 3, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_SG_ERR(val)	    vBIT(val, 5, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_SG_ERR(val)	    vBIT(val, 7, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_SG_ERR(val)   vBIT(val, 9, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_SG_ERR(val)   vBIT(val, 11, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_TRCE_SG_ERR	    mBIT(13)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_TRCE_SG_ERR	    mBIT(14)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_FRM_DB_ERR	    mBIT(32)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_FRM_DB_ERR	    mBIT(33)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_FPDU_MEM_DB_ERR	    mBIT(34)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_DB_ERR(val)	    vBIT(val, 35, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_DB_ERR(val)	    vBIT(val, 37, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_DB_ERR(val)	    vBIT(val, 39, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_DB_ERR(val)   vBIT(val, 41, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_DB_ERR(val)   vBIT(val, 43, 2)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_TRCE_DB_ERR	    mBIT(45)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_TRCE_DB_ERR	    mBIT(46)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_XLMI_SERR	    mBIT(54)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_XLMI_SERR	    mBIT(55)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_DRAM_WR_ERR		    mBIT(58)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGIN_WR_FSM_ERR	    mBIT(59)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGIN_EVCTRL_FSM_ERR    mBIT(60)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_FIFO_ERR	    mBIT(61)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGOUT_COLLISION_ERR    mBIT(62)
+#define	VXGE_HAL_RXPE_ERR_REG_RXPE_SM_ERR		    mBIT(63)
+/* 0x04048 */	u64	rxpe_err_mask;
+/* 0x04050 */	u64	rxpe_err_alarm;
+/* 0x04058 */	u64	dlm_err_reg;
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PA_SG_ERR	    mBIT(0)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PB_SG_ERR	    mBIT(1)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PA_SG_ERR	    mBIT(2)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PB_SG_ERR	    mBIT(3)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PA_SG_ERR	    mBIT(4)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PB_SG_ERR	    mBIT(5)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_AWRQ_MEM_SG_ERR	    mBIT(6)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_LWRQ_MEM_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PA_DB_ERR	    mBIT(8)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PB_DB_ERR	    mBIT(9)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PA_DB_ERR	    mBIT(10)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PB_DB_ERR	    mBIT(11)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PA_DB_ERR	    mBIT(12)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PB_DB_ERR	    mBIT(13)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_AWRQ_MEM_DB_ERR	    mBIT(14)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_LWRQ_MEM_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ACC_PA_STATE_SM_ERR	    mBIT(16)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ACC_PB_STATE_SM_ERR	    mBIT(17)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ACK_RDMEM_DATA_STATE_SM_ERR mBIT(18)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_AFLM_RDFIFO_STATE_SM_ERR   mBIT(19)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_AFLM_STATE_SM_ERR	    mBIT(20)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_APTR_ALLOC_STATE_SM_ERR    mBIT(21)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_RDFIFO_STATE_SM_ERR   mBIT(22)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_STATE_SM_ERR	    mBIT(23)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_AWRQ_STATE_SM_ERR	    mBIT(24)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_EVENT_CTXT_STATE_SM_ERR    mBIT(25)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LCC_PA_STATE_SM_ERR	    mBIT(26)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LCC_PB_STATE_SM_ERR	    mBIT(27)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LFLM_RDFIFO_STATE_SM_ERR   mBIT(28)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LFLM_STATE_SM_ERR	    mBIT(29)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LPTR_ALLOC_STATE_SM_ERR    mBIT(30)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_RDFIFO_STATE_SM_ERR   mBIT(31)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_STATE_SM_ERR	    mBIT(32)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LWRQ_STATE_SM_ERR	    mBIT(33)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PCIWR_STATE_SM_ERR	    mBIT(34)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PFETCH_STATE_SM_ERR	    mBIT(35)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RCC_PA_STATE_SM_ERR	    mBIT(36)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RCC_PB_STATE_SM_ERR	    mBIT(37)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RFLM_RDFIFO_STATE_SM_ERR   mBIT(38)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RFLM_STATE_SM_ERR	    mBIT(39)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RIRR_RDMEM_DATA_STATE_SM_ERR mBIT(40)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RPTR_ALLOC_STATE_SM_ERR    mBIT(41)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_RDFIFO_STATE_SM_ERR   mBIT(42)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_STATE_SM_ERR	    mBIT(43)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RWRQ_STATE_SM_ERR	    mBIT(44)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RXACK_STATE_SM_ERR	    mBIT(45)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RXLIRR_STATE_SM_ERR	    mBIT(46)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RXRIRR_STATE_SM_ERR	    mBIT(47)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_TXACK_RETX_STATE_SM_ERR    mBIT(48)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_TXACK_STATE_SM_ERR	    mBIT(49)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_TXLIRR_STATE_SM_ERR	    mBIT(50)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_TXRIRR_RETX_STATE_SM_ERR   mBIT(51)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_TXRIRR_STATE_SM_ERR	    mBIT(52)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_PREFETCH_ERR		    mBIT(53)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_AFLM_FIFO_ERR		    mBIT(55)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RFLM_FIFO_ERR		    mBIT(56)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LFLM_FIFO_ERR		    mBIT(57)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_FIFO_ERR		    mBIT(58)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_FIFO_ERR		    mBIT(59)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_FIFO_ERR		    mBIT(60)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_ACK_PTR_FIFO_ERR	    mBIT(61)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_RIRR_PTR_FIFO_ERR	    mBIT(62)
+#define	VXGE_HAL_DLM_ERR_REG_DLM_LIRR_PTR_FIFO_ERR	    mBIT(63)
+/* 0x04060 */	u64	dlm_err_mask;
+/* 0x04068 */	u64	dlm_err_alarm;
+/* 0x04070 */	u64	oes_err_reg;
+#define	VXGE_HAL_OES_ERR_REG_OES_INPUT_ARB_SM_ERR	    mBIT(0)
+#define	VXGE_HAL_OES_ERR_REG_OES_PEND_ARB_SM_ERR	    mBIT(1)
+#define	VXGE_HAL_OES_ERR_REG_OES_RXSEG_FIFO_ERR		    mBIT(2)
+#define	VXGE_HAL_OES_ERR_REG_OES_RXEVT_FIFO_ERR		    mBIT(3)
+#define	VXGE_HAL_OES_ERR_REG_OES_TXTDB_FIFO_ERR		    mBIT(4)
+#define	VXGE_HAL_OES_ERR_REG_OES_RXTX_FIFO_ERR		    mBIT(5)
+#define	VXGE_HAL_OES_ERR_REG_OES_TXIMSG_FIFO_ERR	    mBIT(6)
+#define	VXGE_HAL_OES_ERR_REG_OES_TXCONT_FIFO_ERR	    mBIT(7)
+/* 0x04078 */	u64	oes_err_mask;
+/* 0x04080 */	u64	oes_err_alarm;
+/* 0x04088 */	u64	txpe_err_reg;
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_SG_ERR(val)	    vBIT(val, 0, 2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PA_SG_ERR	    mBIT(2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PB_SG_ERR	    mBIT(3)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SG_ERR(val)	    vBIT(val, 4, 2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_SG_ERR(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_TRACE_SG_ERR	    mBIT(8)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_IMM_SG_ERR	    mBIT(9)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PA_SG_ERR	    mBIT(10)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PB_SG_ERR	    mBIT(11)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PA_SG_ERR	    mBIT(12)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PB_SG_ERR	    mBIT(13)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_STG_SG_ERR	    mBIT(14)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_DB_ERR(val)	    vBIT(val, 16, 2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PA_DB_ERR	    mBIT(18)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PB_DB_ERR	    mBIT(19)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_DB_ERR(val)	    vBIT(val, 20, 2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_DB_ERR(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_TRACE_DB_ERR	    mBIT(24)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_IMM_DB_ERR	    mBIT(25)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PA_DB_ERR	    mBIT(26)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PB_DB_ERR	    mBIT(27)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PA_DB_ERR	    mBIT(28)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PB_DB_ERR	    mBIT(29)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_STG_DB_ERR	    mBIT(30)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_SM_ERR		    mBIT(32)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_IMSGIN_SM_ERR	    mBIT(33)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_SM_ERR		    mBIT(34)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_TCE_CHOICE_SM_ERR   mBIT(35)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_DIV_SM_ERR	    mBIT(36)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_SM_ERR		    mBIT(37)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_RES_SM_ERR	    mBIT(38)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_NACK_SM_ERR	    mBIT(39)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_RDTCE_SM_ERR		    mBIT(40)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_CMGIF_RDRQ_SM_ERR	    mBIT(41)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_CMGIF_READDRES_SM_ERR    mBIT(42)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_CTXT_SM_ERR	    mBIT(43)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_PRI_TCE_UPDATE_SM_ERR    mBIT(44)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_GET_SM_ERR	    mBIT(45)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_DONE_SM_ERR	    mBIT(46)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_INIT_SM_ERR		    mBIT(47)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_FETCH_SM_ERR		    mBIT(48)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_HOG_SM_ERR		    mBIT(49)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_PMON_SM_ERR		    mBIT(50)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SM_ERR	    mBIT(51)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_NCM_CTXT_SM_ERR	    mBIT(52)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_NCM_MEM_SM_ERR	    mBIT(53)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_RQ_SM_ERR	    mBIT(54)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_RDRES_PHASE_ERR	    mBIT(55)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_XT_XLMI_SERR		    mBIT(56)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_WRP_ERR		    mBIT(57)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_FIFO_ERR	    mBIT(58)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_DFIFO_ERR	    mBIT(59)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_HFIFO_ERR	    mBIT(60)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_DIVIDE_ERR	    mBIT(61)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_PDA_NACK_FIFO_ERR	    mBIT(62)
+#define	VXGE_HAL_TXPE_ERR_REG_TXPE_MEM_CONFLICT_ERR	    mBIT(63)
+/* 0x04090 */	u64	txpe_err_mask;
+/* 0x04098 */	u64	txpe_err_alarm;
+/* 0x040a0 */	u64	txpe_bcc_mem_sg_ecc_err_reg;
+#define	VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_TXPE_SG_ERR(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_CDP_SG_ERR(val)\
+							    vBIT(val, 32, 32)
+/* 0x040a8 */	u64	txpe_bcc_mem_sg_ecc_err_mask;
+/* 0x040b0 */	u64	txpe_bcc_mem_sg_ecc_err_alarm;
+/* 0x040b8 */	u64	txpe_bcc_mem_db_ecc_err_reg;
+#define	VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_TXPE_DB_ERR(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_CDP_DB_ERR(val)\
+							    vBIT(val, 32, 32)
+/* 0x040c0 */	u64	txpe_bcc_mem_db_ecc_err_mask;
+/* 0x040c8 */	u64	txpe_bcc_mem_db_ecc_err_alarm;
+/* 0x040d0 */	u64	rpe_fsm_err_reg;
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_SHADOW_ERR	    mBIT(0)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_SHADOW_ERR	    mBIT(1)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCM_SHADOW_ERR	    mBIT(2)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_SHADOW_ERR	    mBIT(3)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_SHADOW_ERR	    mBIT(4)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_SHADOW_ERR	    mBIT(5)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_SHADOW_ERR	    mBIT(6)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_RWM_ERR	    mBIT(7)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_RRM_ERR	    mBIT(8)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_SCC_ERR	    mBIT(9)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_CMM_ERR	    mBIT(10)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_OIF_ERR	    mBIT(11)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_FPG_ERR	    mBIT(12)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_WCC_ERR	    mBIT(13)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_WMM_ERR	    mBIT(14)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_OIF_ERR	    mBIT(15)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_QRI_ERR	    mBIT(16)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_ERR	    mBIT(17)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_UNDEF_EVENT mBIT(18)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_BS_ERR	    mBIT(19)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_IWP_ERR	    mBIT(20)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_LRO_ERR	    mBIT(21)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_HDR_ERR	    mBIT(22)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_MUX_ERR	    mBIT(23)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_RLC_ERR	    mBIT(24)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_IPM_DLM_ERR	    mBIT(25)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_IPM_MSG_ERR	    mBIT(26)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_ARB_ERR	    mBIT(27)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_HBI_ERR	    mBIT(28)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_OPC_ERR	    mBIT(29)
+#define	VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_FW_ERR	    mBIT(32)
+/* 0x040d8 */	u64	rpe_fsm_err_mask;
+/* 0x040e0 */	u64	rpe_fsm_err_alarm;
+	u8	unused04100[0x04100 - 0x040e8];
+
+/* 0x04100 */	u64	one_cfg;
+#define	VXGE_HAL_ONE_CFG_ONE_CFG_RDY			    mBIT(7)
+/* 0x04108 */	u64	sgrp_alloc[17];
+#define	VXGE_HAL_SGRP_ALLOC_SGRP_ALLOC(val)		    vBIT(val, 0, 64)
+/* 0x04190 */	u64	sgrp_iwarp_lro_alloc;
+#define	VXGE_HAL_SGRP_IWARP_LRO_ALLOC_ENABLE_IWARP	    mBIT(7)
+#define	VXGE_HAL_SGRP_IWARP_LRO_ALLOC_LAST_IWARP_SGRP(val)  vBIT(val, 11, 5)
+/* 0x04198 */	u64	rpe_cfg0;
+#define	VXGE_HAL_RPE_CFG0_RCC_NBR_SLOTS(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_RPE_CFG0_RCC_NBR_FREE_SLOTS(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_RPE_CFG0_RCC_MODE			    mBIT(23)
+#define	VXGE_HAL_RPE_CFG0_LL_SEND_MAX_SIZE(val)		    vBIT(val, 24, 8)
+#define	VXGE_HAL_RPE_CFG0_BS_ACK_WQE_PF_ENA		    mBIT(38)
+#define	VXGE_HAL_RPE_CFG0_IWARP_ISL_PF_ENA		    mBIT(39)
+#define	VXGE_HAL_RPE_CFG0_PDM_FRAME_ECC_ENABLE_N	    mBIT(43)
+#define	VXGE_HAL_RPE_CFG0_PDM_RCMD_ECC_ENABLE_N		    mBIT(44)
+#define	VXGE_HAL_RPE_CFG0_RCQ_ECC_ENABLE_N		    mBIT(45)
+#define	VXGE_HAL_RPE_CFG0_RCO_PBLE_ECC_ENABLE_N		    mBIT(46)
+#define	VXGE_HAL_RPE_CFG0_RCM_ECC_ENABLE_N		    mBIT(47)
+#define	VXGE_HAL_RPE_CFG0_PDM_FRAME_PHASE_ENABLE	    mBIT(50)
+#define	VXGE_HAL_RPE_CFG0_DLM_RCMD_PHASE_ENABLE		    mBIT(51)
+#define	VXGE_HAL_RPE_CFG0_MSG_RCMD_PHASE_ENABLE		    mBIT(52)
+#define	VXGE_HAL_RPE_CFG0_PDM_RCMD_PHASE_ENABLE		    mBIT(53)
+#define	VXGE_HAL_RPE_CFG0_RCQ_PHASE_ENABLE		    mBIT(54)
+#define	VXGE_HAL_RPE_CFG0_RCO_PBLE_PHASE_ENABLE		    mBIT(55)
+/* 0x041a0 */	u64	rpe_cfg1;
+#define	VXGE_HAL_RPE_CFG1_WQEOWN_LRO_CTR_ENA		    mBIT(5)
+#define	VXGE_HAL_RPE_CFG1_WQEOWN_BS_CTR_ENA		    mBIT(6)
+#define	VXGE_HAL_RPE_CFG1_WQEOWN_IWARP_CTR_ENA		    mBIT(7)
+#define	VXGE_HAL_RPE_CFG1_DLM_RCMD_MAX_CREDITS(val)	    vBIT(val, 10, 6)
+#define	VXGE_HAL_RPE_CFG1_MSG_RCMD_MAX_CREDITS(val)	    vBIT(val, 18, 6)
+#define	VXGE_HAL_RPE_CFG1_PDM_RCMD_MAX_CREDITS(val)	    vBIT(val, 25, 7)
+#define	VXGE_HAL_RPE_CFG1_RCQ_MAX_CREDITS(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_RPE_CFG1_RCQ_DLM_PRI(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RPE_CFG1_RCQ_MSG_PRI(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_RPE_CFG1_RCQ_PDM_PRI(val)		    vBIT(val, 62, 2)
+/* 0x041a8 */	u64	rpe_cfg2;
+#define	VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL0_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL1_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL2_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL3_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL4_PRI(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL5_PRI(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_RPE_CFG2_RDMA_WRITE_ORDER_ENABLE	    mBIT(49)
+#define	VXGE_HAL_RPE_CFG2_RDMA_RDRESP_ORDER_ENABLE	    mBIT(50)
+#define	VXGE_HAL_RPE_CFG2_RDMA_SEND_ORDER_ENABLE	    mBIT(51)
+#define	VXGE_HAL_RPE_CFG2_RDMA_RDREQ_ORDER_ENABLE	    mBIT(52)
+#define	VXGE_HAL_RPE_CFG2_RDMA_TERMINATE_ORDER_ENABLE	    mBIT(53)
+#define	VXGE_HAL_RPE_CFG2_IWARP_MISALIGNED_ORDER_ENABLE	    mBIT(54)
+#define	VXGE_HAL_RPE_CFG2_IWARP_TIMER_ORDER_ENABLE	    mBIT(55)
+#define	VXGE_HAL_RPE_CFG2_IWARP_IMSG_ORDER_ENABLE	    mBIT(56)
+#define	VXGE_HAL_RPE_CFG2_BS_IWARP_ACK_ORDER_ENABLE	    mBIT(57)
+#define	VXGE_HAL_RPE_CFG2_BS_DATA_ORDER_ENABLE		    mBIT(58)
+#define	VXGE_HAL_RPE_CFG2_BS_TIMER_ORDER_ENABLE		    mBIT(59)
+#define	VXGE_HAL_RPE_CFG2_BS_IMSG_ORDER_ENABLE		    mBIT(60)
+#define	VXGE_HAL_RPE_CFG2_LRO_FRAME_ORDER_ENABLE	    mBIT(61)
+#define	VXGE_HAL_RPE_CFG2_LRO_TIMER_ORDER_ENABLE	    mBIT(62)
+#define	VXGE_HAL_RPE_CFG2_LRO_IMSG_ORDER_ENABLE		    mBIT(63)
+	u8	unused041c0[0x041c0 - 0x041b0];
+
+/* 0x041c0 */	u64	rpe_cfg5;
+#define	VXGE_HAL_RPE_CFG5_LRO_IGNORE_RPA_PARSE_ERRS	    mBIT(4)
+#define	VXGE_HAL_RPE_CFG5_LRO_IGNORE_FRM_INT_ERRS	    mBIT(5)
+#define	VXGE_HAL_RPE_CFG5_LRO_IGNORE_L3_CSUM_ERRS	    mBIT(6)
+#define	VXGE_HAL_RPE_CFG5_LRO_IGNORE_L4_CSUM_ERRS	    mBIT(7)
+#define	VXGE_HAL_RPE_CFG5_LRO_NORM_SCATTER_IPV4_OPTIONS	    mBIT(14)
+#define	VXGE_HAL_RPE_CFG5_LRO_NORM_SCATTER_IPV6_EXTHDRS	    mBIT(15)
+#define	VXGE_HAL_RPE_CFG5_USE_CONCISE_ADAPTIVE_LRO_CQE	    mBIT(22)
+#define	VXGE_HAL_RPE_CFG5_USE_CONCISE_PRECONFIG_LRO_CQE	    mBIT(23)
+/* 0x041c8 */	u64	wqeown0;
+#define	VXGE_HAL_WQEOWN0_RPE_LRO_CTR(val)		    vBIT(val, 13, 19)
+#define	VXGE_HAL_WQEOWN0_RPE_BS_CTR(val)		    vBIT(val, 45, 19)
+/* 0x041d0 */	u64	wqeown1;
+#define	VXGE_HAL_WQEOWN1_RPE_IWARP_CTR(val)		    vBIT(val, 13, 19)
+/* 0x041d8 */	u64	rpe_wqeown2;
+#define	VXGE_HAL_RPE_WQEOWN2_LRO_THRESHOLD(val)		    vBIT(val, 13, 19)
+#define	VXGE_HAL_RPE_WQEOWN2_BS_THRESHOLD(val)		    vBIT(val, 45, 19)
+	u8	unused04200[0x04200 - 0x041e0];
+
+/* 0x04200 */	u64	pe_ctxt;
+#define	VXGE_HAL_PE_CTXT_SCC_TRIGGER_READ		    mBIT(7)
+#define	VXGE_HAL_PE_CTXT_S1_SIZE(val)			    vBIT(val, 10, 6)
+#define	VXGE_HAL_PE_CTXT_S2_SIZE(val)			    vBIT(val, 26, 6)
+#define	VXGE_HAL_PE_CTXT_S3_SIZE(val)			    vBIT(val, 42, 6)
+#define	VXGE_HAL_PE_CTXT_NP_XFER			    mBIT(55)
+#define	VXGE_HAL_PE_CTXT_NP_SPACER			    mBIT(63)
+/* 0x04208 */	u64	pe_cfg;
+#define	VXGE_HAL_PE_CFG_RXPE_ECC_ENABLE_N		    mBIT(7)
+#define	VXGE_HAL_PE_CFG_TXPE_ECC_ENABLE_N		    mBIT(15)
+#define	VXGE_HAL_PE_CFG_DLM_ECC_ENABLE_N		    mBIT(23)
+#define	VXGE_HAL_PE_CFG_CDP_ECC_ENABLE_N		    mBIT(31)
+#define	VXGE_HAL_PE_CFG_PET_ECC_ENABLE_N		    mBIT(39)
+#define	VXGE_HAL_PE_CFG_MAX_RXB2B(val)			    vBIT(val, 56, 8)
+/* 0x04210 */	u64	pe_stats_cmd;
+#define	VXGE_HAL_PE_STATS_CMD_GO			    mBIT(7)
+#define	VXGE_HAL_PE_STATS_CMD_SELECT_TXPE		    mBIT(15)
+#define	VXGE_HAL_PE_STATS_CMD_ADDRESS(val)		    vBIT(val, 21, 11)
+/* 0x04218 */	u64	pe_stats_data;
+#define	VXGE_HAL_PE_STATS_DATA_PE_RETURNED(val)		    vBIT(val, 0, 64)
+/* 0x04220 */	u64	rxpe_fp_mask;
+#define	VXGE_HAL_RXPE_FP_MASK_RXPE_FP_MASK(val)		    vBIT(val, 18, 46)
+/* 0x04228 */	u64	rxpe_cfg;
+#define	VXGE_HAL_RXPE_CFG_FW_EXTEND_FP	mBIT(7)
+#define	VXGE_HAL_RXPE_CFG_RETXK_SP_DONE	mBIT(15)
+/* 0x04230 */	u64	pe_xt_ctrl1;
+#define	VXGE_HAL_PE_XT_CTRL1_IRAM_ADDRESS(val)		    vBIT(val, 4, 12)
+#define	VXGE_HAL_PE_XT_CTRL1_ENABLE_GO_FOR_WR		    mBIT(23)
+#define	VXGE_HAL_PE_XT_CTRL1_IRAM_READ	mBIT(27)
+#define	VXGE_HAL_PE_XT_CTRL1_TXP_IRAM_SEL		    mBIT(29)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP0_IRAM_SEL		    mBIT(30)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP1_IRAM_SEL		    mBIT(31)
+#define	VXGE_HAL_PE_XT_CTRL1_TXP_IRAM_ECC_ENABLE_N	    mBIT(37)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP0_IRAM_ECC_ENABLE_N	    mBIT(38)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP1_IRAM_ECC_ENABLE_N	    mBIT(39)
+#define	VXGE_HAL_PE_XT_CTRL1_TXP_DRAM_ECC_ENABLE_N	    mBIT(46)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP_DRAM_ECC_ENABLE_N	    mBIT(47)
+#define	VXGE_HAL_PE_XT_CTRL1_TXP_RUNSTALL		    mBIT(53)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP0_RUNSTALL		    mBIT(54)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP1_RUNSTALL		    mBIT(55)
+#define	VXGE_HAL_PE_XT_CTRL1_TXP_BRESET			    mBIT(61)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP0_BRESET		    mBIT(62)
+#define	VXGE_HAL_PE_XT_CTRL1_RXP1_BRESET		    mBIT(63)
+/* 0x04238 */	u64	pe_xt_ctrl2;
+#define	VXGE_HAL_PE_XT_CTRL2_IRAM_WRITE_DATA(val)	    vBIT(val, 0, 64)
+/* 0x04240 */	u64	pe_xt_ctrl3;
+#define	VXGE_HAL_PE_XT_CTRL3_GO	mBIT(63)
+/* 0x04248 */	u64	pe_xt_ctrl4;
+#define	VXGE_HAL_PE_XT_CTRL4_PE_IRAM_READ_DATA(val)	    vBIT(val, 0, 64)
+/* 0x04250 */	u64	pet_iwarp_counters;
+#define	VXGE_HAL_PET_IWARP_COUNTERS_MASTER(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_PET_IWARP_COUNTERS_INTERVAL(val)	    vBIT(val, 40, 24)
+/* 0x04258 */	u64	pet_iwarp_slow_counter;
+#define	VXGE_HAL_PET_IWARP_SLOW_COUNTER_MASTER(val)	    vBIT(val, 0, 32)
+/* 0x04260 */	u64	pet_iwarp_timers;
+#define	VXGE_HAL_PET_IWARP_TIMERS_TCP_NOW(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_PET_IWARP_TIMERS_TCP_SLOW_CLK(val)	    vBIT(val, 32, 32)
+/* 0x04268 */	u64	pet_lro_cfg;
+#define	VXGE_HAL_PET_LRO_CFG_START_VALUE(val)		    vBIT(val, 6, 2)
+/* 0x04270 */	u64	pet_lro_counters;
+#define	VXGE_HAL_PET_LRO_COUNTERS_MASTER(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_PET_LRO_COUNTERS_INTERVAL(val)		    vBIT(val, 40, 24)
+/* 0x04278 */	u64	pet_timer_bp_ctrl;
+#define	VXGE_HAL_PET_TIMER_BP_CTRL_RD_XON		    mBIT(7)
+#define	VXGE_HAL_PET_TIMER_BP_CTRL_WR_XON		    mBIT(15)
+#define	VXGE_HAL_PET_TIMER_BP_CTRL_ROCRC_BYP		    mBIT(23)
+#define	VXGE_HAL_PET_TIMER_BP_CTRL_H2L_BYP		    mBIT(31)
+/* 0x04280 */	u64	pe_vp_ack[17];
+#define	VXGE_HAL_PE_VP_ACK_BLK_LIMIT(val)		    vBIT(val, 32, 32)
+/* 0x04308 */	u64	pe_vp[17];
+#define	VXGE_HAL_PE_VP_RIRR_BLK_LIMIT(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_PE_VP_LIRR_BLK_LIMIT(val)		    vBIT(val, 32, 32)
+/* 0x04390 */	u64	dlm_cfg;
+#define	VXGE_HAL_DLM_CFG_AWRQ_PHASE_ENABLE		    mBIT(7)
+#define	VXGE_HAL_DLM_CFG_ACK_PTR_AE_LEVEL(val)		    vBIT(val, 12, 4)
+#define	VXGE_HAL_DLM_CFG_LWRQ_PHASE_ENABLE		    mBIT(23)
+#define	VXGE_HAL_DLM_CFG_LIRR_PTR_AE_LEVEL(val)		    vBIT(val, 28, 4)
+#define	VXGE_HAL_DLM_CFG_RIRR_PTR_AE_LEVEL(val)		    vBIT(val, 44, 4)
+	u8	unused04400[0x04400 - 0x04398];
+
+/* 0x04400 */	u64	txpe_towi_cfg;
+#define	VXGE_HAL_TXPE_TOWI_CFG_TOWI_CACHE_SIZE(val)	    vBIT(val, 48, 8)
+#define	VXGE_HAL_TXPE_TOWI_CFG_TOWI_DMA_THRESHOLD(val)	    vBIT(val, 56, 8)
+	u8	unused04410[0x04410 - 0x04408];
+
+/* 0x04410 */	u64	txpe_pmon;
+#define	VXGE_HAL_TXPE_PMON_GO				    mBIT(15)
+#define	VXGE_HAL_TXPE_PMON_SAMPLE_PERIOD(val)		    vBIT(val, 16, 48)
+/* 0x04418 */	u64	txpe_pmon_downcount;
+#define	VXGE_HAL_TXPE_PMON_DOWNCOUNT_TXPE_REMAINDER(val)    vBIT(val, 16, 48)
+/* 0x04420 */	u64	txpe_pmon_event;
+#define	VXGE_HAL_TXPE_PMON_EVENT_TXPE_STALL_CNT(val)	    vBIT(val, 16, 48)
+/* 0x04428 */	u64	txpe_pmon_other;
+#define	VXGE_HAL_TXPE_PMON_OTHER_TXPE_STALL_CNT(val)	    vBIT(val, 16, 48)
+	u8	unused04500[0x04500 - 0x04430];
+
+/* 0x04500 */	u64	oes_inevt;
+#define	VXGE_HAL_OES_INEVT_PRIORITY_0(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_INEVT_PRIORITY_1(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_INEVT_PRIORITY_2(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_INEVT_PRIORITY_3(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_INEVT_PRIORITY_4(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_OES_INEVT_CFG_SP_WRR			    mBIT(63)
+/* 0x04508 */	u64	oes_inbkbkevt;
+#define	VXGE_HAL_OES_INBKBKEVT_PRIORITY_0(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_INBKBKEVT_PRIORITY_1(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_INBKBKEVT_PRIORITY_2(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_INBKBKEVT_PRIORITY_3(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_INBKBKEVT_PRIORITY_4(val)		    vBIT(val, 37, 3)
+/* 0x04510 */	u64	oes_inevt_wrr0;
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_0(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_1(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_2(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_3(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_4(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_5(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_6(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_OES_INEVT_WRR0_SS_7(val)		    vBIT(val, 61, 3)
+/* 0x04518 */	u64	oes_inevt_wrr1;
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_8(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_9(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_10(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_11(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_12(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_13(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_OES_INEVT_WRR1_SS_14(val)		    vBIT(val, 53, 3)
+/* 0x04520 */	u64	oes_pendevt;
+#define	VXGE_HAL_OES_PENDEVT_PRIORITY_0(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_PENDEVT_PRIORITY_1(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_PENDEVT_PRIORITY_2(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_PENDEVT_PRIORITY_3(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_PENDEVT_PRIORITY_4(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_OES_PENDEVT_CFG_SP_WRR			    mBIT(63)
+/* 0x04528 */	u64	oes_pendbkbkevt;
+#define	VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_0(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_1(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_2(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_3(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_4(val)	    vBIT(val, 37, 3)
+/* 0x04530 */	u64	oes_pendevt_wrr0;
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_0(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_1(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_2(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_3(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_4(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_5(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_6(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR0_SS_7(val)		    vBIT(val, 61, 3)
+/* 0x04538 */	u64	oes_pendevt_wrr1;
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_8(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_9(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_10(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_11(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_12(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_13(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_OES_PENDEVT_WRR1_SS_14(val)		    vBIT(val, 53, 3)
+/* 0x04540 */	u64	oes_pend_queue;
+#define	VXGE_HAL_OES_PEND_QUEUE_RX_PEND_THRESHOLD(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_OES_PEND_QUEUE_TX_PEND_THRESHOLD(val)	    vBIT(val, 57, 7)
+	u8	unused04800[0x04800 - 0x04548];
+
+/* 0x04800 */	u64	rocrc_bypq0_stat_watermark;
+#define	VXGE_HAL_ROCRC_BYPQ0_STAT_WATERMARK_RCQ_ROCRC_BYPQ0_STAT_WATERMARK(val)\
+							    vBIT(val, 11, 22)
+/* 0x04808 */	u64	rocrc_bypq1_stat_watermark;
+#define	VXGE_HAL_ROCRC_BYPQ1_STAT_WATERMARK_RCQ_ROCRC_BYPQ1_STAT_WATERMARK(val)\
+							    vBIT(val, 11, 22)
+/* 0x04810 */	u64	rocrc_bypq2_stat_watermark;
+#define	VXGE_HAL_ROCRC_BYPQ2_STAT_WATERMARK_RCQ_ROCRC_BYPQ2_STAT_WATERMARK(val)\
+							    vBIT(val, 11, 22)
+/* 0x04818 */	u64	noa_wct_ctrl;
+#define	VXGE_HAL_NOA_WCT_CTRL_VP_INT_NUM		    mBIT(0)
+/* 0x04820 */	u64	rc_cfg2;
+#define	VXGE_HAL_RC_CFG2_BUFF1_SIZE(val)		    vBIT(val, 0, 16)
+#define	VXGE_HAL_RC_CFG2_BUFF2_SIZE(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_RC_CFG2_BUFF3_SIZE(val)		    vBIT(val, 32, 16)
+#define	VXGE_HAL_RC_CFG2_BUFF4_SIZE(val)		    vBIT(val, 48, 16)
+/* 0x04828 */	u64	rc_cfg3;
+#define	VXGE_HAL_RC_CFG3_BUFF5_SIZE(val)		    vBIT(val, 0, 16)
+/* 0x04830 */	u64	rx_multi_cast_ctrl1;
+#define	VXGE_HAL_RX_MULTI_CAST_CTRL1_ENABLE		    mBIT(7)
+#define	VXGE_HAL_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val)	    vBIT(val, 11, 5)
+/* 0x04838 */	u64	rxdm_dbg_rd;
+#define	VXGE_HAL_RXDM_DBG_RD_ADDR(val)			    vBIT(val, 0, 12)
+#define	VXGE_HAL_RXDM_DBG_RD_ENABLE			    mBIT(31)
+/* 0x04840 */	u64	rxdm_dbg_rd_data;
+#define	VXGE_HAL_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vBIT(val, 0, 64)
+/* 0x04848 */	u64	rqa_top_prty_for_vh[17];
+#define	VXGE_HAL_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) vBIT(val, 59, 5)
+	u8	unused04900[0x04900 - 0x048d0];
+
+/* 0x04900 */	u64	tim_status;
+#define	VXGE_HAL_TIM_STATUS_TIM_RESET_IN_PROGRESS	    mBIT(0)
+/* 0x04908 */	u64	tim_ecc_enable;
+#define	VXGE_HAL_TIM_ECC_ENABLE_VBLS_N			    mBIT(7)
+#define	VXGE_HAL_TIM_ECC_ENABLE_BMAP_N			    mBIT(15)
+#define	VXGE_HAL_TIM_ECC_ENABLE_BMAP_MSG_N		    mBIT(23)
+/* 0x04910 */	u64	tim_bp_ctrl;
+#define	VXGE_HAL_TIM_BP_CTRL_RD_XON			    mBIT(7)
+#define	VXGE_HAL_TIM_BP_CTRL_WR_XON			    mBIT(15)
+#define	VXGE_HAL_TIM_BP_CTRL_ROCRC_BYP			    mBIT(23)
+/* 0x04918 */	u64	tim_resource_assignment_vh[17];
+#define	VXGE_HAL_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val)  vBIT(val, 0, 32)
+/* 0x049a0 */	u64	tim_bmap_mapping_vp_err[17];
+#define	VXGE_HAL_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vBIT(val, 3, 5)
+	u8	unused04b00[0x04b00 - 0x04a28];
+
+/* 0x04b00 */	u64	gcmg2_int_status;
+#define	VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT	    mBIT(7)
+#define	VXGE_HAL_GCMG2_INT_STATUS_GCP_ERR_GCP_INT	    mBIT(15)
+#define	VXGE_HAL_GCMG2_INT_STATUS_CMC_ERR_CMC_INT	    mBIT(23)
+/* 0x04b08 */	u64	gcmg2_int_mask;
+/* 0x04b10 */	u64	gxtmc_err_reg;
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val)	    vBIT(val, 0, 4)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR	    mBIT(8)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR	    mBIT(9)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR	    mBIT(10)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR	    mBIT(11)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR	    mBIT(12)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR	    mBIT(13)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR		    mBIT(14)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR	    mBIT(15)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR		    mBIT(16)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR	    mBIT(17)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR	    mBIT(18)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR	    mBIT(19)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR	    mBIT(20)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW mBIT(21)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW mBIT(22)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR   mBIT(23)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW mBIT(24)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW mBIT(25)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR    mBIT(26)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR   mBIT(27)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR  mBIT(28)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR	    mBIT(29)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR   mBIT(30)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR    mBIT(31)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR	    mBIT(32)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR  mBIT(33)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR	    mBIT(34)
+#define	VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR	    mBIT(35)
+/* 0x04b18 */	u64	gxtmc_err_mask;
+/* 0x04b20 */	u64	gxtmc_err_alarm;
+/* 0x04b28 */	u64	cmc_err_reg;
+#define	VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR		    mBIT(0)
+/* 0x04b30 */	u64	cmc_err_mask;
+/* 0x04b38 */	u64	cmc_err_alarm;
+/* 0x04b40 */	u64	gcp_err_reg;
+#define	VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR		    mBIT(0)
+#define	VXGE_HAL_GCP_ERR_REG_CP_STC2CP_FIFO_ERR		    mBIT(1)
+#define	VXGE_HAL_GCP_ERR_REG_CP_STE2CP_FIFO_ERR		    mBIT(2)
+#define	VXGE_HAL_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR		    mBIT(3)
+/* 0x04b48 */	u64	gcp_err_mask;
+/* 0x04b50 */	u64	gcp_err_alarm;
+/* 0x04b58 */	u64	cmc_l2_client_uqm_1;
+#define	VXGE_HAL_CMC_L2_CLIENT_UQM_1_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b60 */	u64	cmc_l2_client_ssc_l;
+#define	VXGE_HAL_CMC_L2_CLIENT_SSC_L_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b68 */	u64	cmc_l2_client_qcc_sqm_0;
+#define	VXGE_HAL_CMC_L2_CLIENT_QCC_SQM_0_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b70 */	u64	cmc_l2_client_dam_0;
+#define	VXGE_HAL_CMC_L2_CLIENT_DAM_0_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b78 */	u64	cmc_l2_client_h2l_0;
+#define	VXGE_HAL_CMC_L2_CLIENT_H2L_0_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b80 */	u64	cmc_l2_client_stc_0;
+#define	VXGE_HAL_CMC_L2_CLIENT_STC_0_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b88 */	u64	cmc_l2_client_xtmc_0;
+#define	VXGE_HAL_CMC_L2_CLIENT_XTMC_0_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04b90 */	u64	cmc_wrr_l2_calendar_0;
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_0(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_1(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_2(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_3(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_4(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_5(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_6(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_7(val)	    vBIT(val, 61, 3)
+/* 0x04b98 */	u64	cmc_wrr_l2_calendar_1;
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_8(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_9(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_10(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_11(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_12(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_13(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_14(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_15(val)	    vBIT(val, 61, 3)
+/* 0x04ba0 */	u64	cmc_wrr_l2_calendar_2;
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_16(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_17(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_18(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_19(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_20(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_21(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_22(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_23(val)	    vBIT(val, 61, 3)
+/* 0x04ba8 */	u64	cmc_wrr_l2_calendar_3;
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_24(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_25(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_26(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_27(val)	    vBIT(val, 29, 3)
+/* 0x04bb0 */	u64	cmc_l3_client_qcc_sqm_1;
+#define	VXGE_HAL_CMC_L3_CLIENT_QCC_SQM_1_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04bb8 */	u64	cmc_l3_client_qcc_cqm;
+#define	VXGE_HAL_CMC_L3_CLIENT_QCC_CQM_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04bc0 */	u64	cmc_l3_client_dam_1;
+#define	VXGE_HAL_CMC_L3_CLIENT_DAM_1_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04bc8 */	u64	cmc_l3_client_h2l_1;
+#define	VXGE_HAL_CMC_L3_CLIENT_H2L_1_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04bd0 */	u64	cmc_l3_client_stc_1;
+#define	VXGE_HAL_CMC_L3_CLIENT_STC_1_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04bd8 */	u64	cmc_l3_client_xtmc_1;
+#define	VXGE_HAL_CMC_L3_CLIENT_XTMC_1_NUMBER(val)	    vBIT(val, 5, 3)
+/* 0x04be0 */	u64	cmc_wrr_l3_calendar_0;
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_0(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_1(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_2(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_3(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_4(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_5(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_6(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_7(val)	    vBIT(val, 61, 3)
+/* 0x04be8 */	u64	cmc_wrr_l3_calendar_1;
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_8(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_9(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_10(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_11(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_12(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_13(val)	    vBIT(val, 45, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_14(val)	    vBIT(val, 53, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_15(val)	    vBIT(val, 61, 3)
+/* 0x04bf0 */	u64	cmc_wrr_l3_calendar_2;
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_16(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_17(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_18(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_19(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_20(val)	    vBIT(val, 37, 3)
+/* 0x04bf8 */	u64	cmc_user_doorbell_partition;
+#define	VXGE_HAL_CMC_USER_DOORBELL_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c00 */	u64	cmc_hit_record_partition_0;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_0_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c08 */	u64	cmc_hit_record_partition_1;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_1_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c10 */	u64	cmc_hit_record_partition_2;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_2_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c18 */	u64	cmc_hit_record_partition_3;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_3_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c20 */	u64	cmc_hit_record_partition_4;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_4_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c28 */	u64	cmc_hit_record_partition_5;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_5_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c30 */	u64	cmc_hit_record_partition_6;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_6_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c38 */	u64	cmc_hit_record_partition_7;
+#define	VXGE_HAL_CMC_HIT_RECORD_PARTITION_7_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c40 */	u64	cmc_c_scr_record_partition_0;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_0_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c48 */	u64	cmc_c_scr_record_partition_1;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_1_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c50 */	u64	cmc_c_scr_record_partition_2;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_2_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c58 */	u64	cmc_c_scr_record_partition_3;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_3_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c60 */	u64	cmc_c_scr_record_partition_4;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_4_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c68 */	u64	cmc_c_scr_record_partition_5;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_5_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c70 */	u64	cmc_c_scr_record_partition_6;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_6_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c78 */	u64	cmc_c_scr_record_partition_7;
+#define	VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_7_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c80 */	u64	cmc_wqe_od_group_record_partition;
+#define	VXGE_HAL_CMC_WQE_OD_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
+/* 0x04c88 */	u64	cmc_ack_record_partition;
+#define	VXGE_HAL_CMC_ACK_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c90 */	u64	cmc_lirr_record_partition;
+#define	VXGE_HAL_CMC_LIRR_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04c98 */	u64	cmc_rirr_record_partition;
+#define	VXGE_HAL_CMC_RIRR_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04ca0 */	u64	cmc_tce_record_partition;
+#define	VXGE_HAL_CMC_TCE_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04ca8 */	u64	cmc_hoq_record_partition;
+#define	VXGE_HAL_CMC_HOQ_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04cb0 */	u64	cmc_stag_vp_record_partition[17];
+#define	VXGE_HAL_CMC_STAG_VP_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d38 */	u64	cmc_r_scr_record_partition;
+#define	VXGE_HAL_CMC_R_SCR_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d40 */	u64	cmc_cqrq_context_record_partition;
+#define	VXGE_HAL_CMC_CQRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
+/* 0x04d48 */	u64	cmc_cqe_group_record_partition;
+#define	VXGE_HAL_CMC_CQE_GROUP_RECORD_PARTITION_BASE(val)   vBIT(val, 8, 24)
+/* 0x04d50 */	u64	cmc_p_scr_record_partition;
+#define	VXGE_HAL_CMC_P_SCR_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d58 */	u64	cmc_nce_context_record_partition;
+#define	VXGE_HAL_CMC_NCE_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
+/* 0x04d60 */	u64	cmc_bypass_queue_partition;
+#define	VXGE_HAL_CMC_BYPASS_QUEUE_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d68 */	u64	cmc_h_scr_record_partition;
+#define	VXGE_HAL_CMC_H_SCR_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d70 */	u64	cmc_pbl_record_partition;
+#define	VXGE_HAL_CMC_PBL_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d78 */	u64	cmc_lit_record_partition;
+#define	VXGE_HAL_CMC_LIT_RECORD_PARTITION_BASE(val)	    vBIT(val, 8, 24)
+/* 0x04d80 */	u64	cmc_srq_context_record_partition;
+#define	VXGE_HAL_CMC_SRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24)
+/* 0x04d88 */	u64	cmc_p_scr_record;
+#define	VXGE_HAL_CMC_P_SCR_RECORD_SIZE(val)		    vBIT(val, 2, 6)
+/* 0x04d90 */	u64	cmc_device_select;
+#define	VXGE_HAL_CMC_DEVICE_SELECT_CODE(val)		    vBIT(val, 5, 3)
+/* 0x04d98 */	u64	g3if_fifo_dst_ecc;
+#define	VXGE_HAL_G3IF_FIFO_DST_ECC_ENABLE(val)		    vBIT(val, 3, 5)
+/* 0x04da0 */	u64	gxtmc_cfg;
+#define	VXGE_HAL_GXTMC_CFG_CMC_PRI			    mBIT(7)
+#define	VXGE_HAL_GXTMC_CFG_GPSYNC_WAIT_TOKEN_ENABLE	    mBIT(13)
+#define	VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_TIMER_ENABLE	    mBIT(14)
+#define	VXGE_HAL_GXTMC_CFG_GPSYNC_SRC_NOTIFY_ENABLE	    mBIT(15)
+#define	VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_START_VALUE(val)  vBIT(val, 20, 4)
+#define	VXGE_HAL_GXTMC_CFG_BDT_MEM_ECC_ENABLE_N		    mBIT(31)
+	u8	unused04f00[0x04f00 - 0x04da8];
+
+/* 0x04f00 */	u64	pcmg2_int_status;
+#define	VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT	    mBIT(7)
+#define	VXGE_HAL_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT	    mBIT(15)
+#define	VXGE_HAL_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT	    mBIT(23)
+/* 0x04f08 */	u64	pcmg2_int_mask;
+/* 0x04f10 */	u64	pxtmc_err_reg;
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vBIT(val, 0, 2)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR	    mBIT(2)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR	    mBIT(3)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR	    mBIT(4)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR	    mBIT(5)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR	    mBIT(6)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR	    mBIT(7)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR	    mBIT(8)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR	    mBIT(9)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR	    mBIT(10)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR	    mBIT(11)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR	    mBIT(12)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR	    mBIT(13)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR	    mBIT(14)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR	    mBIT(15)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR	    mBIT(16)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR	    mBIT(17)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR	    mBIT(18)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR	    mBIT(19)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR	    mBIT(20)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR	    mBIT(21)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR	    mBIT(22)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR	    mBIT(23)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR	    mBIT(24)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR	    mBIT(25)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR	    mBIT(26)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR	    mBIT(27)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR	    mBIT(28)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR	    mBIT(29)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR	    mBIT(30)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR	    mBIT(31)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR		    mBIT(32)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR		    mBIT(33)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR		    mBIT(34)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR		    mBIT(35)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR	    mBIT(36)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR	    mBIT(37)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR	    mBIT(38)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR	    mBIT(39)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR	    mBIT(40)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR	    mBIT(41)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR	    mBIT(42)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR	    mBIT(43)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR	    mBIT(44)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR    mBIT(45)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR    mBIT(46)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR    mBIT(47)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR    mBIT(48)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR    mBIT(49)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR    mBIT(50)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR   mBIT(51)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR   mBIT(52)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR   mBIT(53)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vBIT(val, 54, 2)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR   mBIT(56)
+#define	VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR   mBIT(57)
+/* 0x04f18 */	u64	pxtmc_err_mask;
+/* 0x04f20 */	u64	pxtmc_err_alarm;
+/* 0x04f28 */	u64	cp_err_reg;
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val)	    vBIT(val, 8, 2)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_SG_ERR		    mBIT(10)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_SG_ERR		    mBIT(11)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_SG_ERR		    mBIT(12)
+#define	VXGE_HAL_CP_ERR_REG_CP_DMA2CP_SG_ERR		    mBIT(13)
+#define	VXGE_HAL_CP_ERR_REG_CP_MP2CP_SG_ERR		    mBIT(14)
+#define	VXGE_HAL_CP_ERR_REG_CP_QCC2CP_SG_ERR		    mBIT(15)
+#define	VXGE_HAL_CP_ERR_REG_CP_STC2CP_SG_ERR(val)	    vBIT(val, 16, 2)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val)	    vBIT(val, 32, 2)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_DB_ERR		    mBIT(34)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_DB_ERR		    mBIT(35)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_DB_ERR		    mBIT(36)
+#define	VXGE_HAL_CP_ERR_REG_CP_DMA2CP_DB_ERR		    mBIT(37)
+#define	VXGE_HAL_CP_ERR_REG_CP_MP2CP_DB_ERR		    mBIT(38)
+#define	VXGE_HAL_CP_ERR_REG_CP_QCC2CP_DB_ERR		    mBIT(39)
+#define	VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(val)	    vBIT(val, 40, 2)
+#define	VXGE_HAL_CP_ERR_REG_CP_H2L2CP_FIFO_ERR		    mBIT(48)
+#define	VXGE_HAL_CP_ERR_REG_CP_STC2CP_FIFO_ERR		    mBIT(49)
+#define	VXGE_HAL_CP_ERR_REG_CP_STE2CP_FIFO_ERR		    mBIT(50)
+#define	VXGE_HAL_CP_ERR_REG_CP_TTE2CP_FIFO_ERR		    mBIT(51)
+#define	VXGE_HAL_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR		    mBIT(52)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP2DMA_FIFO_ERR		    mBIT(53)
+#define	VXGE_HAL_CP_ERR_REG_CP_DAM2CP_FIFO_ERR		    mBIT(54)
+#define	VXGE_HAL_CP_ERR_REG_CP_MP2CP_FIFO_ERR		    mBIT(55)
+#define	VXGE_HAL_CP_ERR_REG_CP_QCC2CP_FIFO_ERR		    mBIT(56)
+#define	VXGE_HAL_CP_ERR_REG_CP_DMA2CP_FIFO_ERR		    mBIT(57)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR    mBIT(60)
+#define	VXGE_HAL_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR    mBIT(61)
+#define	VXGE_HAL_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR	    mBIT(62)
+#define	VXGE_HAL_CP_ERR_REG_CP_PIFT_CREDIT_ERR		    mBIT(63)
+/* 0x04f30 */	u64	cp_err_mask;
+/* 0x04f38 */	u64	cp_err_alarm;
+/* 0x04f40 */	u64	cp_xt_ctrl1;
+#define	VXGE_HAL_CP_XT_CTRL1_CP_WAKEUP			    mBIT(47)
+#define	VXGE_HAL_CP_XT_CTRL1_CP_RUNSTALL		    mBIT(55)
+#define	VXGE_HAL_CP_XT_CTRL1_CP_BRESET			    mBIT(63)
+/* 0x04f48 */	u64	cp_gen_cfg;
+#define	VXGE_HAL_CP_GEN_CFG_MULT_DMA_RD_REQ_ENA		    mBIT(7)
+#define	VXGE_HAL_CP_GEN_CFG_DMA_RD_PER_VPLANE_CHK_ENA	    mBIT(15)
+#define	VXGE_HAL_CP_GEN_CFG_DMA_RD_XON_CHK_ENA		    mBIT(23)
+#define	VXGE_HAL_CP_GEN_CFG_CAUSE_INT_IS_CRITICAL	    mBIT(31)
+/* 0x04f50 */	u64	cp_exc_reg;
+#define	VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_INFO_INT	    mBIT(47)
+#define	VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT	    mBIT(55)
+#define	VXGE_HAL_CP_EXC_REG_CP_CP_SERR			    mBIT(63)
+/* 0x04f58 */	u64	cp_exc_mask;
+/* 0x04f60 */	u64	cp_exc_alarm;
+/* 0x04f68 */	u64	cp_exc_cause;
+#define	VXGE_HAL_CP_EXC_CAUSE_CP_CP_CAUSE(val)		    vBIT(val, 32, 32)
+	u8	unused04fe8[0x04fe8 - 0x04f70];
+
+/* 0x04fe8 */	u64	xtmc_img_ctrl0;
+#define	VXGE_HAL_XTMC_IMG_CTRL0_LD_BANK_DEPTH(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_XTMC_IMG_CTRL0_ENABLE_GO		    mBIT(15)
+#define	VXGE_HAL_XTMC_IMG_CTRL0_IMG_LD_COMPLETE		    mBIT(23)
+#define	VXGE_HAL_XTMC_IMG_CTRL0_LAST_DATA		    mBIT(31)
+#define	VXGE_HAL_XTMC_IMG_CTRL0_ADDR(val)		    vBIT(val, 40, 24)
+/* 0x04ff0 */	u64	xtmc_img_ctrl1;
+#define	VXGE_HAL_XTMC_IMG_CTRL1_DATA(val)		    vBIT(val, 0, 64)
+/* 0x04ff8 */	u64	xtmc_img_ctrl2;
+#define	VXGE_HAL_XTMC_IMG_CTRL2_XTMC_LD_BANK_AVAIL	    mBIT(63)
+/* 0x05000 */	u64	xtmc_img_ctrl3;
+#define	VXGE_HAL_XTMC_IMG_CTRL3_XTMC_ALL_DATA_WRITTEN	    mBIT(63)
+/* 0x05008 */	u64	xtmc_img_ctrl4;
+#define	VXGE_HAL_XTMC_IMG_CTRL4_GO			    mBIT(63)
+/* 0x05010 */	u64	pxtmc_cfg0;
+#define	VXGE_HAL_PXTMC_CFG0_XT_PIF_SRAM_ECC_ENABLE_N	    mBIT(3)
+#define	VXGE_HAL_PXTMC_CFG0_XT_PIF_SRAM_PHASE_ENA	    mBIT(7)
+#define	VXGE_HAL_PXTMC_CFG0_MXP_RD_PROT_ENA		    mBIT(11)
+#define	VXGE_HAL_PXTMC_CFG0_MXP_WR_PROT_ENA		    mBIT(15)
+#define	VXGE_HAL_PXTMC_CFG0_UXP_RD_PROT_ENA		    mBIT(19)
+#define	VXGE_HAL_PXTMC_CFG0_UXP_WR_PROT_ENA		    mBIT(23)
+#define	VXGE_HAL_PXTMC_CFG0_CXP_RD_PROT_ENA		    mBIT(27)
+#define	VXGE_HAL_PXTMC_CFG0_CXP_WR_PROT_ENA		    mBIT(31)
+#define	VXGE_HAL_PXTMC_CFG0_INVALID_ADDR_CHECK_ENA	    mBIT(39)
+#define	VXGE_HAL_PXTMC_CFG0_SUPPRESS_RD_ON_ADDR_ERR	    mBIT(43)
+#define	VXGE_HAL_PXTMC_CFG0_SUPPRESS_WR_ON_ADDR_ERR	    mBIT(47)
+#define	VXGE_HAL_PXTMC_CFG0_ARB_DURING_4BYTE_WR_ENA	    mBIT(55)
+/* 0x05018 */	u64	pxtmc_cfg1;
+#define	VXGE_HAL_PXTMC_CFG1_MAX_NBR_MXP_EVENTS(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_PXTMC_CFG1_MAX_NBR_UXP_EVENTS(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_PXTMC_CFG1_MAX_NBR_CXP_EVENTS(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_PXTMC_CFG1_PGSYNC_WAIT_TOKEN_ENABLE	    mBIT(29)
+#define	VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_TIMER_ENABLE	    mBIT(30)
+#define	VXGE_HAL_PXTMC_CFG1_PGSYNC_SRC_NOTIFY_ENABLE	    mBIT(31)
+#define	VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4)
+/* 0x05020 */	u64	xtmc_mem_cfg;
+#define	VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SPARSE_BASE(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_PACKED_BASE(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_XTMC_MEM_CFG_SHARED_SRAM_BASE(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SIZE(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_XTMC_MEM_CFG_SRAM_SPARSE_BASE_ADDR(val)    vBIT(val, 32, 16)
+#define	VXGE_HAL_XTMC_MEM_CFG_SRAM_PACKED_BASE_ADDR(val)    vBIT(val, 48, 16)
+/* 0x05028 */	u64	xtmc_mem_bypass_cfg;
+#define	VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3)
+#define	VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3)
+#define	VXGE_HAL_XTMC_MEM_BYPASS_CFG_SHARED_SRAM_BASE(val)  vBIT(val, 21, 3)
+/* 0x05030 */	u64	xtmc_cxp_region0;
+#define	VXGE_HAL_XTMC_CXP_REGION0_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_CXP_REGION0_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05038 */	u64	xtmc_mxp_region0;
+#define	VXGE_HAL_XTMC_MXP_REGION0_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_MXP_REGION0_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05040 */	u64	xtmc_uxp_region0;
+#define	VXGE_HAL_XTMC_UXP_REGION0_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_UXP_REGION0_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05048 */	u64	xtmc_cxp_region1;
+#define	VXGE_HAL_XTMC_CXP_REGION1_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_CXP_REGION1_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05050 */	u64	xtmc_mxp_region1;
+#define	VXGE_HAL_XTMC_MXP_REGION1_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_MXP_REGION1_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05058 */	u64	xtmc_uxp_region1;
+#define	VXGE_HAL_XTMC_UXP_REGION1_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_UXP_REGION1_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05060 */	u64	xtmc_cxp_region2;
+#define	VXGE_HAL_XTMC_CXP_REGION2_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_CXP_REGION2_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05068 */	u64	xtmc_mxp_region2;
+#define	VXGE_HAL_XTMC_MXP_REGION2_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_MXP_REGION2_END_ADDR(val)		    vBIT(val, 32, 32)
+/* 0x05070 */	u64	xtmc_uxp_region2;
+#define	VXGE_HAL_XTMC_UXP_REGION2_START_ADDR(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XTMC_UXP_REGION2_END_ADDR(val)		    vBIT(val, 32, 32)
+	u8	unused05200[0x05200 - 0x05078];
+
+/* 0x05200 */	u64	msg_int_status;
+#define	VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT		    mBIT(7)
+#define	VXGE_HAL_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT	    mBIT(60)
+#define	VXGE_HAL_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT	    mBIT(61)
+#define	VXGE_HAL_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT	    mBIT(62)
+#define	VXGE_HAL_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT	    mBIT(63)
+/* 0x05208 */	u64	msg_int_mask;
+/* 0x05210 */	u64	tim_err_reg;
+#define	VXGE_HAL_TIM_ERR_REG_TIM_VBLS_SG_ERR		    mBIT(4)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR		    mBIT(5)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR		    mBIT(6)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR	    mBIT(7)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR		    mBIT(12)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR		    mBIT(13)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR		    mBIT(14)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR	    mBIT(18)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR mBIT(19)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR		    mBIT(20)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR   mBIT(22)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR    mBIT(23)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH	    mBIT(46)
+#define	VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n)	    mBIT(n)
+/* 0x05218 */	u64	tim_err_mask;
+/* 0x05220 */	u64	tim_err_alarm;
+/* 0x05228 */	u64	msg_err_reg;
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR  mBIT(0)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR  mBIT(1)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR mBIT(2)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR	mBIT(3)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR	mBIT(4)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR	mBIT(5)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR  mBIT(6)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR  mBIT(7)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR		    mBIT(8)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR		    mBIT(10)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR		    mBIT(12)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR		    mBIT(14)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR	    mBIT(16)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR	    mBIT(17)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR	    mBIT(18)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR	    mBIT(19)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR	    mBIT(20)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR	    mBIT(21)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR		    mBIT(26)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR	    mBIT(27)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR	    mBIT(29)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR    mBIT(31)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR  mBIT(33)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR   mBIT(34)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR mBIT(35)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR mBIT(36)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR	    mBIT(38)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR		    mBIT(39)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR		    mBIT(41)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR		    mBIT(43)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR		    mBIT(45)
+#define	VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR	    mBIT(47)
+#define	VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR	    mBIT(48)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR	    mBIT(49)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR	    mBIT(50)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR	    mBIT(51)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR	    mBIT(52)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR	    mBIT(53)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR	    mBIT(54)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR	    mBIT(55)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR	    mBIT(56)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR		    mBIT(57)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR	    mBIT(58)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR	    mBIT(59)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR	    mBIT(60)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR	    mBIT(61)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR    mBIT(62)
+#define	VXGE_HAL_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR	    mBIT(63)
+/* 0x05230 */	u64	msg_err_mask;
+/* 0x05238 */	u64	msg_err_alarm;
+/* 0x05240 */	u64	msg_xt_ctrl;
+#define	VXGE_HAL_MSG_XT_CTRL_MXP_CAUSE_INT_IS_CRITICAL	    mBIT(35)
+#define	VXGE_HAL_MSG_XT_CTRL_UXP_CAUSE_INT_IS_CRITICAL	    mBIT(39)
+#define	VXGE_HAL_MSG_XT_CTRL_MXP_WAKEUP			    mBIT(46)
+#define	VXGE_HAL_MSG_XT_CTRL_UXP_WAKEUP			    mBIT(47)
+#define	VXGE_HAL_MSG_XT_CTRL_MXP_RUNSTALL		    mBIT(54)
+#define	VXGE_HAL_MSG_XT_CTRL_UXP_RUNSTALL		    mBIT(55)
+#define	VXGE_HAL_MSG_XT_CTRL_MXP_BRESET			    mBIT(62)
+#define	VXGE_HAL_MSG_XT_CTRL_UXP_BRESET			    mBIT(63)
+	u8	unused052a8[0x052a8 - 0x05248];
+
+/* 0x052a8 */	u64	msg_dispatch;
+#define	VXGE_HAL_MSG_DISPATCH_MESS_TYPE_ENABLE		    mBIT(55)
+#define	VXGE_HAL_MSG_DISPATCH_VPATH_CUTOFF(val)		    vBIT(val, 59, 5)
+	u8	unused05340[0x05340 - 0x052b0];
+
+/* 0x05340 */	u64	msg_exc_reg;
+#define	VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT	    mBIT(50)
+#define	VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT	    mBIT(51)
+#define	VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT	    mBIT(54)
+#define	VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT	    mBIT(55)
+#define	VXGE_HAL_MSG_EXC_REG_MP_MXP_SERR		    mBIT(62)
+#define	VXGE_HAL_MSG_EXC_REG_UP_UXP_SERR		    mBIT(63)
+/* 0x05348 */	u64	msg_exc_mask;
+/* 0x05350 */	u64	msg_exc_alarm;
+/* 0x05358 */	u64	msg_exc_cause;
+#define	VXGE_HAL_MSG_EXC_CAUSE_MP_MXP(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_MSG_EXC_CAUSE_UP_UXP(val)		    vBIT(val, 32, 32)
+	u8	unused05368[0x05368 - 0x05360];
+
+/* 0x05368 */	u64	msg_direct_pic;
+#define	VXGE_HAL_MSG_DIRECT_PIC_PIPELINE_EN		    mBIT(55)
+#define	VXGE_HAL_MSG_DIRECT_PIC_UMQ_WRITE_ENABLE	    mBIT(56)
+#define	VXGE_HAL_MSG_DIRECT_PIC_UMQ_VPA(val)		    vBIT(val, 59, 5)
+/* 0x05370 */	u64	umq_ir_test_vpa;
+#define	VXGE_HAL_UMQ_IR_TEST_VPA_NUMBER(val)		    vBIT(val, 0, 5)
+/* 0x05378 */	u64	umq_ir_test_byte;
+#define	VXGE_HAL_UMQ_IR_TEST_BYTE_VALUE_START(val)	    vBIT(val, 0, 32)
+/* 0x05380 */	u64	msg_err2_reg;
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR mBIT(0)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR	mBIT(1)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR	mBIT(2)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR	mBIT(3)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR		mBIT(4)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR	mBIT(5)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR	mBIT(6)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR	mBIT(7)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR	mBIT(8)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR	mBIT(9)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR	mBIT(10)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR	mBIT(11)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR\
+							    mBIT(12)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR\
+							    mBIT(13)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR\
+							    mBIT(14)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR\
+							    mBIT(15)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR\
+							    mBIT(16)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR\
+							    mBIT(17)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR\
+							    mBIT(18)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR	mBIT(19)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR	mBIT(20)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR	mBIT(21)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR	mBIT(22)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR	mBIT(23)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR	mBIT(24)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR	mBIT(25)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR	mBIT(26)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR	mBIT(27)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR	mBIT(28)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR	mBIT(29)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR\
+							    mBIT(30)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR\
+							    mBIT(31)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR\
+							    mBIT(32)
+#define	VXGE_HAL_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR  mBIT(33)
+#define	VXGE_HAL_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR  mBIT(34)
+#define	VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR  mBIT(62)
+#define	VXGE_HAL_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR	    mBIT(63)
+/* 0x05388 */	u64	msg_err2_mask;
+/* 0x05390 */	u64	msg_err2_alarm;
+/* 0x05398 */	u64	msg_err3_reg;
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0	    mBIT(0)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1	    mBIT(1)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2	    mBIT(2)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3	    mBIT(3)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4	    mBIT(4)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5	    mBIT(5)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6	    mBIT(6)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7	    mBIT(7)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0	    mBIT(8)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1	    mBIT(9)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0	    mBIT(16)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1	    mBIT(17)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2	    mBIT(18)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3	    mBIT(19)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4	    mBIT(20)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5	    mBIT(21)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6	    mBIT(22)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7	    mBIT(23)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0	    mBIT(24)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1	    mBIT(25)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0	    mBIT(32)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1	    mBIT(33)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2	    mBIT(34)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3	    mBIT(35)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4	    mBIT(36)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5	    mBIT(37)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6	    mBIT(38)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7	    mBIT(39)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0	    mBIT(40)
+#define	VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1	    mBIT(41)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0	    mBIT(48)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1	    mBIT(49)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2	    mBIT(50)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3	    mBIT(51)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4	    mBIT(52)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5	    mBIT(53)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6	    mBIT(54)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7	    mBIT(55)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0	    mBIT(56)
+#define	VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1	    mBIT(57)
+/* 0x053a0 */	u64	msg_err3_mask;
+/* 0x053a8 */	u64	msg_err3_alarm;
+/* 0x053b0 */	u64	umq_ir_test_byte_notify;
+#define	VXGE_HAL_UMQ_IR_TEST_BYTE_NOTIFY_PULSE		    mBIT(3)
+/* 0x053b8 */	u64	msg_bp_ctrl;
+#define	VXGE_HAL_MSG_BP_CTRL_RD_XON_EN			    mBIT(7)
+#define	VXGE_HAL_MSG_BP_CTRL_WR_XON_E			    mBIT(15)
+#define	VXGE_HAL_MSG_BP_CTRL_ROCRC_BYP_EN		    mBIT(23)
+/* 0x053c0 */	u64	umq_bwr_pfch_init[17];
+#define	VXGE_HAL_UMQ_BWR_PFCH_INIT_NUMBER(val)		    vBIT(val, 0, 8)
+/* 0x05448 */	u64	umq_bwr_pfch_init_notify[17];
+#define	VXGE_HAL_UMQ_BWR_PFCH_INIT_NOTIFY_PULSE		    mBIT(3)
+/* 0x054d0 */	u64	umq_bwr_eol;
+#define	VXGE_HAL_UMQ_BWR_EOL_POLL_LATENCY(val)		    vBIT(val, 32, 32)
+/* 0x054d8 */	u64	umq_bwr_eol_latency_notify;
+#define	VXGE_HAL_UMQ_BWR_EOL_LATENCY_NOTIFY_PULSE	    mBIT(3)
+	u8	unused05600[0x05600 - 0x054e0];
+
+/* 0x05600 */	u64	fau_gen_err_reg;
+#define	VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP  mBIT(3)
+#define	VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP  mBIT(7)
+#define	VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP  mBIT(11)
+#define	VXGE_HAL_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIF mBIT(15)
+/* 0x05608 */	u64	fau_gen_err_mask;
+/* 0x05610 */	u64	fau_gen_err_alarm;
+/* 0x05618 */	u64	fau_ecc_err_reg;
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR mBIT(0)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR mBIT(1)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val)\
+							    vBIT(val, 2, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val)\
+							    vBIT(val, 4, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR mBIT(6)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR mBIT(7)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val)\
+							    vBIT(val, 8, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR mBIT(12)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR mBIT(13)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val)\
+							    vBIT(val, 14, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val)\
+							    vBIT(val, 16, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) vBIT(val, 18, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) vBIT(val, 20, 2)
+#define	VXGE_HAL_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR	    mBIT(31)
+/* 0x05620 */	u64	fau_ecc_err_mask;
+/* 0x05628 */	u64	fau_ecc_err_alarm;
+	u8	unused05648[0x05648 - 0x05630];
+
+/* 0x05648 */	u64	fau_global_cfg;
+#define	VXGE_HAL_FAU_GLOBAL_CFG_ARB_ALG(val)		    vBIT(val, 2, 2)
+/* 0x05650 */	u64	rx_datapath_util;
+#define	VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_UTILIZATION(val)   vBIT(val, 7, 9)
+#define	VXGE_HAL_RX_DATAPATH_UTIL_RX_UTIL_CFG(val)	    vBIT(val, 16, 4)
+#define	VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_FRAC_UTIL(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_RX_DATAPATH_UTIL_RX_PKT_WEIGHT(val)	    vBIT(val, 24, 4)
+/* 0x05658 */	u64	fau_pa_cfg;
+#define	VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM		    mBIT(3)
+#define	VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF		    mBIT(7)
+#define	VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM		    mBIT(11)
+	u8	unused05668[0x05668 - 0x05660];
+
+/* 0x05668 */	u64	dbg_stats_fau_rx_path;
+#define	VXGE_HAL_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32)
+/* 0x05670 */	u64	fau_auto_lro_control;
+#define	VXGE_HAL_FAU_AUTO_LRO_CONTROL_OPERATION_TYPE	    mBIT(7)
+#define	VXGE_HAL_FAU_AUTO_LRO_CONTROL_FRAME_COUNT(val)	    vBIT(val, 8, 24)
+#define	VXGE_HAL_FAU_AUTO_LRO_CONTROL_TIMER_VALUE(val)	    vBIT(val, 32, 32)
+/* 0x05678 */	u64	fau_auto_lro_data_0;
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_0_SOURCE_VPATH(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_0_HAS_VLAN		    mBIT(14)
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_0_IS_IPV6		    mBIT(15)
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_0_VLAN_VID(val)	    vBIT(val, 20, 12)
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_DEST_PORT(val)	    vBIT(val, 32, 16)
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_SOURCE_PORT(val)   vBIT(val, 48, 16)
+/* 0x05680 */	u64	fau_auto_lro_data_1;
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_1_IP_SOURCE_ADDR_0(val)  vBIT(val, 0, 64)
+/* 0x05688 */	u64	fau_auto_lro_data_2;
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_2_IP_SOURCE_ADDR_1(val)  vBIT(val, 0, 64)
+/* 0x05690 */	u64	fau_auto_lro_data_3;
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_3_IP_DEST_ADDR_0(val)    vBIT(val, 0, 64)
+/* 0x05698 */	u64	fau_auto_lro_data_4;
+#define	VXGE_HAL_FAU_AUTO_LRO_DATA_4_IP_DEST_ADDR_1(val)    vBIT(val, 0, 64)
+	u8	unused056c0[0x056c0 - 0x056a0];
+
+/* 0x056c0 */	u64	fau_lag_cfg;
+#define	VXGE_HAL_FAU_LAG_CFG_COLL_ALG(val)		    vBIT(val, 2, 2)
+#define	VXGE_HAL_FAU_LAG_CFG_INCR_RX_AGGR_STATS		    mBIT(7)
+	u8	unused05700[0x05700 - 0x056c8];
+
+/* 0x05700 */	u64	fau_mpa_cfg;
+#define	VXGE_HAL_FAU_MPA_CFG_CRC_CHK_EN	mBIT(3)
+#define	VXGE_HAL_FAU_MPA_CFG_MRK_LEN_CHK_EN		    mBIT(7)
+	u8	unused057a0[0x057a0 - 0x05708];
+
+/* 0x057a0 */	u64	xmac_rx_xgmii_capture_data_port[3];
+#define	VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_COL_INDX(val) vBIT(val, 0, 12)
+#define	VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_FLAG(val) vBIT(val, 26, 2)
+#define	VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXC(val) vBIT(val, 28, 4)
+#define	VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXD(val) vBIT(val, 32, 32)
+	u8	unused05800[0x05800 - 0x057b8];
+
+/* 0x05800 */	u64	tpa_int_status;
+#define	VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT		    mBIT(15)
+#define	VXGE_HAL_TPA_INT_STATUS_PTM_ALARM_PTM_INT	    mBIT(23)
+#define	VXGE_HAL_TPA_INT_STATUS_TPA_ERROR_TPA_INT	    mBIT(31)
+/* 0x05808 */	u64	tpa_int_mask;
+/* 0x05810 */	u64	orp_err_reg;
+#define	VXGE_HAL_ORP_ERR_REG_ORP_FIFO_SG_ERR		    mBIT(3)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR		    mBIT(7)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR	    mBIT(11)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR	    mBIT(15)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR	    mBIT(19)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR	    mBIT(23)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR		    mBIT(27)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR	    mBIT(31)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR	    mBIT(35)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR	    mBIT(39)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR	    mBIT(43)
+#define	VXGE_HAL_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR	    mBIT(47)
+/* 0x05818 */	u64	orp_err_mask;
+/* 0x05820 */	u64	orp_err_alarm;
+/* 0x05828 */	u64	ptm_alarm_reg;
+#define	VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR	    mBIT(3)
+#define	VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR	    mBIT(7)
+#define	VXGE_HAL_PTM_ALARM_REG_XFMD_RD_FIFO_ERR		    mBIT(11)
+#define	VXGE_HAL_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR	    mBIT(15)
+#define	VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val)	    vBIT(val, 18, 2)
+#define	VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val)	    vBIT(val, 22, 2)
+/* 0x05830 */	u64	ptm_alarm_mask;
+/* 0x05838 */	u64	ptm_alarm_alarm;
+/* 0x05840 */	u64	tpa_error_reg;
+#define	VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM	    mBIT(3)
+#define	VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR  mBIT(7)
+#define	VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR  mBIT(11)
+/* 0x05848 */	u64	tpa_error_mask;
+/* 0x05850 */	u64	tpa_error_alarm;
+/* 0x05858 */	u64	tpa_global_cfg;
+#define	VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N	    mBIT(7)
+#define	VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N		    mBIT(35)
+/* 0x05860 */	u64	tx_datapath_util;
+#define	VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_UTILIZATION(val)   vBIT(val, 7, 9)
+#define	VXGE_HAL_TX_DATAPATH_UTIL_TX_UTIL_CFG(val)	    vBIT(val, 16, 4)
+#define	VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_FRAC_UTIL(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_TX_DATAPATH_UTIL_TX_PKT_WEIGHT(val)	    vBIT(val, 24, 4)
+/* 0x05868 */	u64	orp_cfg;
+#define	VXGE_HAL_ORP_CFG_FIFO_CREDITS(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_ORP_CFG_ORP_FIFO_ECC_ENABLE_N		    mBIT(15)
+#define	VXGE_HAL_ORP_CFG_FIFO_PHASE_EN			    mBIT(23)
+/* 0x05870 */	u64	ptm_ecc_cfg;
+#define	VXGE_HAL_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N		    mBIT(3)
+/* 0x05878 */	u64	ptm_phase_cfg;
+#define	VXGE_HAL_PTM_PHASE_CFG_FRMM_WR_PHASE_EN		    mBIT(3)
+#define	VXGE_HAL_PTM_PHASE_CFG_FRMM_RD_PHASE_EN		    mBIT(7)
+/* 0x05880 */	u64	orp_lro_events;
+#define	VXGE_HAL_ORP_LRO_EVENTS_ORP_LRO_EVENTS(val)	    vBIT(val, 0, 64)
+/* 0x05888 */	u64	orp_bs_events;
+#define	VXGE_HAL_ORP_BS_EVENTS_ORP_BS_EVENTS(val)	    vBIT(val, 0, 64)
+/* 0x05890 */	u64	orp_iwarp_events;
+#define	VXGE_HAL_ORP_IWARP_EVENTS_ORP_IWARP_EVENTS(val)	    vBIT(val, 0, 64)
+/* 0x05898 */	u64	dbg_stats_tpa_tx_path;
+#define	VXGE_HAL_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) vBIT(val, 32, 32)
+	u8	unused05900[0x05900 - 0x058a0];
+
+/* 0x05900 */	u64	tmac_int_status;
+#define	VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT	mBIT(3)
+#define	VXGE_HAL_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT	mBIT(7)
+/* 0x05908 */	u64	tmac_int_mask;
+/* 0x05910 */	u64	txmac_gen_err_reg;
+#define	VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP	    mBIT(3)
+#define	VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT    mBIT(7)
+/* 0x05918 */	u64	txmac_gen_err_mask;
+/* 0x05920 */	u64	txmac_gen_err_alarm;
+/* 0x05928 */	u64	txmac_ecc_err_reg;
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR	mBIT(3)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR	mBIT(7)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR	mBIT(11)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR	mBIT(15)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR	mBIT(19)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR	mBIT(23)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR  mBIT(27)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR  mBIT(31)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR  mBIT(35)
+#define	VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR	    mBIT(39)
+/* 0x05930 */	u64	txmac_ecc_err_mask;
+/* 0x05938 */	u64	txmac_ecc_err_alarm;
+	u8	unused05948[0x05948-0x05940];
+
+/* 0x05948 */	u64	txmac_gen_cfg1;
+#define	VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE	    mBIT(7)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH		    mBIT(11)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE		    mBIT(15)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_SCALE_TMAC_UTIL		    mBIT(27)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_DISCARD_WHEN_TMAC_DISABLED  mBIT(35)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_IFS_EN			    mBIT(39)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_IFS_STRETCH_RATIO(val)	    vBIT(val, 40, 16)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_IFS_NUM_EXTENSION(val)	    vBIT(val, 59, 5)
+	u8	unused05958[0x05958 - 0x05950];
+
+/* 0x05958 */	u64	txmac_err_inject_cfg;
+#define	VXGE_HAL_TXMAC_ERR_INJECT_CFG_INJECTOR_ERROR_RATE(val) vBIT(val, 0, 32)
+/* 0x05960 */	u64	txmac_frmgen_cfg;
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_EN			    mBIT(3)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_MODE(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_PERIOD(val)		    vBIT(val, 8, 4)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_SEND_TO_WIRE		    mBIT(15)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_VPATH_VECTOR(val)	    vBIT(val, 19, 17)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_SRC_VPATH(val)	    vBIT(val, 39, 5)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_HOST_STEERING(val)	    vBIT(val, 44, 2)
+#define	VXGE_HAL_TXMAC_FRMGEN_CFG_IFS_SEL(val)		    vBIT(val, 47, 3)
+/* 0x05968 */	u64	txmac_frmgen_contents;
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_PATTERN_SEL(val)	    vBIT(val, 2, 2)
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DA_SEL(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LEN_SEL		    mBIT(11)
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MIN_LEN(val)	    vBIT(val, 14, 14)
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MAX_LEN(val)	    vBIT(val, 30, 14)
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LT_FIELD(val)	    vBIT(val, 44, 16)
+#define	VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DATA_SEL(val)	    vBIT(val, 62, 2)
+/* 0x05970 */	u64	txmac_frmgen_data;
+#define	VXGE_HAL_TXMAC_FRMGEN_DATA_FRMDATA(val)		    vBIT(val, 0, 64)
+/* 0x05978 */	u64	dbg_stat_tx_any_frms;
+#define	VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) vBIT(val, 16, 8)
+	u8	unused059a0[0x059a0 - 0x05980];
+
+/* 0x059a0 */	u64	txmac_link_util_port[3];
+#define	VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val)    vBIT(val, 8, 4)
+#define	VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) vBIT(val, 12, 4)
+#define	VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val)  vBIT(val, 16, 4)
+#define	VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR mBIT(23)
+/* 0x059b8 */	u64	txmac_cfg0_port[3];
+#define	VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN		    mBIT(3)
+#define	VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD		    mBIT(7)
+#define	VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(val)		    vBIT(val, 8, 8)
+/* 0x059d0 */	u64	txmac_cfg1_port[3];
+#define	VXGE_HAL_TXMAC_CFG1_PORT_AVG_IPG(val)		    vBIT(val, 40, 8)
+/* 0x059e8 */	u64	txmac_status_port[3];
+#define	VXGE_HAL_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT	    mBIT(3)
+	u8	unused05a20[0x05a20 - 0x05a00];
+
+/* 0x05a20 */	u64	lag_distrib_dest;
+#define	VXGE_HAL_LAG_DISTRIB_DEST_MAP_VPATH(n)		    mBIT(n)
+/* 0x05a28 */	u64	lag_marker_cfg;
+#define	VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN		    mBIT(3)
+#define	VXGE_HAL_LAG_MARKER_CFG_RESP_EN			    mBIT(7)
+#define	VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP	    mBIT(51)
+/* 0x05a30 */	u64	lag_tx_cfg;
+#define	VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS		    mBIT(3)
+#define	VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL	    mBIT(11)
+#define	VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(val)		    vBIT(val, 16, 16)
+/* 0x05a38 */	u64	lag_tx_status;
+#define	VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val)\
+							    vBIT(val, 8, 8)
+#define	VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val)\
+							    vBIT(val, 16, 8)
+	u8	unused05a50[0x05a50 - 0x05a40];
+
+/* 0x05a50 */	u64	txmac_stats_tx_xgmii_char;
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR1(val)  vBIT(val, 1, 3)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXC_CHAR1	    mBIT(7)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR1(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR2(val)  vBIT(val, 17, 3)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXC_CHAR2	    mBIT(23)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR2(val)   vBIT(val, 24, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NEAR_CHAR1 mBIT(39)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\
+							    vBIT(val, 40, 16)
+/* 0x05a58 */	u64	txmac_stats_tx_xgmii_column1;
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE0	    mBIT(7)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE0(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE1	    mBIT(23)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE1(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE2	    mBIT(39)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE2(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE3	    mBIT(55)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE3(val) vBIT(val, 56, 8)
+/* 0x05a60 */	u64	txmac_stats_tx_xgmii_column2;
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE0	    mBIT(7)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE0(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE1	    mBIT(23)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE1(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE2	    mBIT(39)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE2(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE3	    mBIT(55)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE3(val) vBIT(val, 56, 8)
+/* 0x05a68 */	u64	txmac_stats_tx_xgmii_behav_column2;
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NEAR_COL1 mBIT(7)
+#define	VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NUM_COL(val)\
+							    vBIT(val, 8, 16)
+	u8	unused05b00[0x05b00 - 0x05a70];
+
+/* 0x05b00 */	u64	sharedio_status;
+#define	VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_ACTIVE_VPLANE(val)\
+							    vBIT(val, 0, 17)
+#define	VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_VPLANE_COUNT(val)\
+							    vBIT(val, 20, 8)
+#define	VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_SHC	    mBIT(31)
+#define	VXGE_HAL_SHAREDIO_STATUS_PCI_SHARED_IO_MODE	    mBIT(34)
+#define	VXGE_HAL_SHAREDIO_STATUS_PCI_RX_ILLEGAL_TLP_VPLANE_VAL(val)\
+							    vBIT(val, 36, 8)
+/* 0x05b08 */	u64	crdt_status1_vplane[17];
+#define	VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD(val)	    vBIT(val, 4, 12)
+#define	VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD(val)	    vBIT(val, 20, 12)
+#define	VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD(val)	    vBIT(val, 36, 12)
+#define	VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD_INFINITE    mBIT(51)
+#define	VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD_INFINITE   mBIT(55)
+#define	VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD_INFINITE  mBIT(59)
+/* 0x05b90 */	u64	crdt_status2_vplane[17];
+#define	VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH_INFINITE    mBIT(31)
+#define	VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH_INFINITE   mBIT(35)
+#define	VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH_INFINITE  mBIT(39)
+/* 0x05c18 */	u64	crdt_status3_vplane[17];
+#define	VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_PD(val) vBIT(val, 4, 12)
+#define	VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_NPD(val)\
+							    vBIT(val, 20, 12)
+#define	VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_CPLD(val)\
+							    vBIT(val, 36, 12)
+/* 0x05ca0 */	u64	crdt_status4_vplane[17];
+#define	VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_PH(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_NPH(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_CPLH(val)\
+							    vBIT(val, 16, 8)
+/* 0x05d28 */	u64	crdt_status5;
+#define	VXGE_HAL_CRDT_STATUS5_PCI_DEPL_PH(val)		    vBIT(val, 0, 17)
+#define	VXGE_HAL_CRDT_STATUS5_PCI_DEPL_NPH(val)		    vBIT(val, 20, 17)
+#define	VXGE_HAL_CRDT_STATUS5_PCI_DEPL_CPLH(val)	    vBIT(val, 40, 17)
+/* 0x05d30 */	u64	crdt_status6;
+#define	VXGE_HAL_CRDT_STATUS6_PCI_DEPL_PD(val)		    vBIT(val, 0, 17)
+#define	VXGE_HAL_CRDT_STATUS6_PCI_DEPL_NPD(val)		    vBIT(val, 20, 17)
+#define	VXGE_HAL_CRDT_STATUS6_PCI_DEPL_CPLD(val)	    vBIT(val, 40, 17)
+/* 0x05d38 */	u64	crdt_status7;
+#define	VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD(val)		    vBIT(val, 4, 12)
+#define	VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD(val)		    vBIT(val, 20, 12)
+#define	VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD(val)		    vBIT(val, 36, 12)
+#define	VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD_INFINITE	    mBIT(51)
+#define	VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD_INFINITE	    mBIT(55)
+#define	VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD_INFINITE	    mBIT(59)
+/* 0x05d40 */	u64	crdt_status8;
+#define	VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH(val)		    vBIT(val, 0, 8)
+#define	VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH(val)		    vBIT(val, 16, 8)
+#define	VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH_INFINITE	    mBIT(31)
+#define	VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH_INFINITE	    mBIT(35)
+#define	VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH_INFINITE	    mBIT(39)
+/* 0x05d48 */	u64	srpcim_to_mrpcim_vplane_rmsg[17];
+#define	VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_RMSG(val)	    vBIT(val, 0, 64)
+	u8	unused06000[0x06000 - 0x05dd0];
+
+/* 0x06000 */	u64	pcie_lane_cfg1;
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_0_SEL(val)		    vBIT(val, 1, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_1_SEL(val)		    vBIT(val, 5, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_2_SEL(val)		    vBIT(val, 9, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_3_SEL(val)		    vBIT(val, 13, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_4_SEL(val)		    vBIT(val, 17, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_5_SEL(val)		    vBIT(val, 21, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_6_SEL(val)		    vBIT(val, 25, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_RX_7_SEL(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_0_SEL(val)		    vBIT(val, 33, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_1_SEL(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_2_SEL(val)		    vBIT(val, 41, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_3_SEL(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_4_SEL(val)		    vBIT(val, 49, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_5_SEL(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_6_SEL(val)		    vBIT(val, 57, 3)
+#define	VXGE_HAL_PCIE_LANE_CFG1_TX_7_SEL(val)		    vBIT(val, 61, 3)
+/* 0x06008 */	u64	pcie_lane_cfg2;
+#define	VXGE_HAL_PCIE_LANE_CFG2_STROBE			    mBIT(0)
+/* 0x06010 */	u64	pcicfg_no_to_func_cfg[25];
+#define	VXGE_HAL_PCICFG_NO_TO_FUNC_CFG_PCICFG_NO_TO_FUNC_CFG(val)\
+							    vBIT(val, 3, 5)
+/* 0x060d8 */	u64	resource_to_vplane_cfg[17];
+#define	VXGE_HAL_RESOURCE_TO_VPLANE_CFG_RESOURCE_TO_VPLANE_CFG(val)\
+							    vBIT(val, 3, 5)
+/* 0x06160 */	u64	pcicfg_no_to_vplane_cfg[25];
+#define	VXGE_HAL_PCICFG_NO_TO_VPLANE_CFG_PCICFG_NO_TO_VPLANE_CFG(val)\
+							    vBIT(val, 3, 5)
+/* 0x06228 */	u64	general_cfg;
+#define	VXGE_HAL_GENERAL_CFG_ENABLE_FLR_ON_MRIOV_DIS	    mBIT(0)
+#define	VXGE_HAL_GENERAL_CFG_ENABLE_FLR_ON_SRIOV_DIS	    mBIT(1)
+#define	VXGE_HAL_GENERAL_CFG_MULTI_FUNC_8_MODE		    mBIT(2)
+#define	VXGE_HAL_GENERAL_CFG_EN_RST_CPLTO_IN_LUT	    mBIT(3)
+#define	VXGE_HAL_GENERAL_CFG_RST_CPLTO_VAL(val)		    vBIT(val, 4, 4)
+#define	VXGE_HAL_GENERAL_CFG_SHARED_IO_MODE		    mBIT(11)
+#define	VXGE_HAL_GENERAL_CFG_INIT_OSD_COUNT(val)	    vBIT(val, 12, 8)
+#define	VXGE_HAL_GENERAL_CFG_INIT_SHC(val)		    vBIT(val, 20, 8)
+#define	VXGE_HAL_GENERAL_CFG_INITOSD_VERSION(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_GENERAL_CFG_SNOOP_CPLH_CRDT_ON_BUS	    mBIT(35)
+#define	VXGE_HAL_GENERAL_CFG_FC_UPDT_FREQ_VAL(val)	    vBIT(val, 36, 4)
+#define	VXGE_HAL_GENERAL_CFG_RX_MEM_ECC_ENABLE_N	    mBIT(43)
+#define	VXGE_HAL_GENERAL_CFG_TX_MEM_ECC_ENABLE_N	    mBIT(47)
+#define	VXGE_HAL_GENERAL_CFG_MRIOV_CFG_EN		    mBIT(51)
+#define	VXGE_HAL_GENERAL_CFG_HIDE_VPD_CAPABILITY	    mBIT(53)
+#define	VXGE_HAL_GENERAL_CFG_FORCE_RDS_TO_USE_PF_REQID	    mBIT(54)
+#define	VXGE_HAL_GENERAL_CFG_POISON_ADVISORY		    mBIT(55)
+#define	VXGE_HAL_GENERAL_CFG_CPL_TIMEOUT_ADVISORY	    mBIT(56)
+#define	VXGE_HAL_GENERAL_CFG_UNEXP_CPL_ADVISORY		    mBIT(57)
+#define	VXGE_HAL_GENERAL_CFG_UR_ADVISORY		    mBIT(58)
+#define	VXGE_HAL_GENERAL_CFG_CA_ADVISORY		    mBIT(59)
+#define	VXGE_HAL_GENERAL_CFG_WAIT_FOR_CPLH_CRDT_ON_BUS	    mBIT(60)
+#define	VXGE_HAL_GENERAL_CFG_EN_SEND_ERR_MSG_FOR_SERR	    mBIT(61)
+#define	VXGE_HAL_GENERAL_CFG_SEND_NF_MSG_FOR_SERR	    mBIT(62)
+#define	VXGE_HAL_GENERAL_CFG_VF_MUST_USE_CFG_TYPE0	    mBIT(63)
+/* 0x06230 */	u64	start_bist;
+#define	VXGE_HAL_START_BIST_START_BIST			    mBIT(0)
+/* 0x06238 */	u64	bist_cfg;
+#define	VXGE_HAL_BIST_CFG_IGNORE_MEM_RDY		    mBIT(3)
+#define	VXGE_HAL_BIST_CFG_ENABLE			    mBIT(7)
+#define	VXGE_HAL_BIST_CFG_JTAG_BIST_COMPLETION_CODE(val)    vBIT(val, 8, 4)
+/* 0x06240 */	u64	pci_link_control;
+#define	VXGE_HAL_PCI_LINK_CONTROL_APP_REQ_RETRY_EN	    mBIT(3)
+#define	VXGE_HAL_PCI_LINK_CONTROL_APP_LTSSM_EN		    mBIT(7)
+/* 0x06248 */	u64	show_sriov_cap;
+#define	VXGE_HAL_SHOW_SRIOV_CAP_SHOW_SRIOV_CAP(val)	    vBIT(val, 0, 9)
+/* 0x06250 */	u64	link_rst_wait_cnt;
+#define	VXGE_HAL_LINK_RST_WAIT_CNT_LINK_RST_WAIT_CNT(val)   vBIT(val, 0, 16)
+/* 0x06258 */	u64	pcie_based_crdt_cfg1;
+#define	VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_PD(val)	    vBIT(val, 4, 12)
+#define	VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_NPD(val)	    vBIT(val, 20, 12)
+#define	VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_CPLD(val)	    vBIT(val, 36, 12)
+/* 0x06260 */	u64	pcie_based_crdt_cfg2;
+#define	VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_PH(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_NPH(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_CPLH(val)	    vBIT(val, 16, 8)
+/* 0x06268 */	u64	sharedio_abs_based_crdt_cfg1_vplane[17];
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD(val)\
+							    vBIT(val, 4, 12)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD(val)\
+							    vBIT(val, 20, 12)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD(val)\
+							    vBIT(val, 36, 12)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD_INFINITE	mBIT(51)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD_INFINITE	mBIT(55)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD_INFINITE	mBIT(59)
+/* 0x062f0 */	u64	sharedio_abs_based_crdt_cfg2_vplane[17];
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH(val)\
+							    vBIT(val, 0, 8)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH(val)\
+							    vBIT(val, 8, 8)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH(val)\
+							    vBIT(val, 16, 8)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH_INFINITE	mBIT(31)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH_INFINITE	mBIT(35)
+#define	VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH_INFINITE	mBIT(39)
+/* 0x06378 */	u64	arbiter_cfg;
+#define	VXGE_HAL_ARBITER_CFG_CPL_PRIORITY(val)		    vBIT(val, 2, 2)
+#define	VXGE_HAL_ARBITER_CFG_MRD_PRIORITY(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_ARBITER_CFG_MWR_PRIORITY(val)		    vBIT(val, 10, 2)
+#define	VXGE_HAL_ARBITER_CFG_CHK_PRIORITY_MATCH_ONLY	    mBIT(15)
+#define	VXGE_HAL_ARBITER_CFG_CALSTATE0_PRIORITY(val)	    vBIT(val, 18, 2)
+#define	VXGE_HAL_ARBITER_CFG_CALSTATE1_PRIORITY(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_ARBITER_CFG_CALSTATE2_PRIORITY(val)	    vBIT(val, 26, 2)
+#define	VXGE_HAL_ARBITER_CFG_CALSTATE3_PRIORITY(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_ARBITER_CFG_CALSTATE4_PRIORITY(val)	    vBIT(val, 34, 2)
+#define	VXGE_HAL_ARBITER_CFG_CALSTATE5_PRIORITY(val)	    vBIT(val, 38, 2)
+/* 0x06380 */	u64	serdes_cfg1;
+#define	VXGE_HAL_SERDES_CFG1_TX_CLOCK_ALIGN(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_SERDES_CFG1_TX_CALC(val)		    vBIT(val, 8, 8)
+#define	VXGE_HAL_SERDES_CFG1_TX_LVL(val)		    vBIT(val, 19, 5)
+#define	VXGE_HAL_SERDES_CFG1_LOS_LVL(val)		    vBIT(val, 27, 5)
+/* 0x06388 */	u64	serdes_cfg2;
+#define	VXGE_HAL_SERDES_CFG2_TX_0_BOOST(val)		    vBIT(val, 0, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_1_BOOST(val)		    vBIT(val, 4, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_2_BOOST(val)		    vBIT(val, 8, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_3_BOOST(val)		    vBIT(val, 12, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_4_BOOST(val)		    vBIT(val, 16, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_5_BOOST(val)		    vBIT(val, 20, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_6_BOOST(val)		    vBIT(val, 24, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_7_BOOST(val)		    vBIT(val, 28, 4)
+#define	VXGE_HAL_SERDES_CFG2_TX_0_ATTEN(val)		    vBIT(val, 33, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_1_ATTEN(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_2_ATTEN(val)		    vBIT(val, 41, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_3_ATTEN(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_4_ATTEN(val)		    vBIT(val, 49, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_5_ATTEN(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_6_ATTEN(val)		    vBIT(val, 57, 3)
+#define	VXGE_HAL_SERDES_CFG2_TX_7_ATTEN(val)		    vBIT(val, 61, 3)
+/* 0x06390 */	u64	serdes_cfg3;
+#define	VXGE_HAL_SERDES_CFG3_TX_0_EDGERATE(val)		    vBIT(val, 2, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_1_EDGERATE(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_2_EDGERATE(val)		    vBIT(val, 10, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_3_EDGERATE(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_4_EDGERATE(val)		    vBIT(val, 18, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_5_EDGERATE(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_6_EDGERATE(val)		    vBIT(val, 26, 2)
+#define	VXGE_HAL_SERDES_CFG3_TX_7_EDGERATE(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_SERDES_CFG3_RX_0_EQ_VAL(val)		    vBIT(val, 33, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_1_EQ_VAL(val)		    vBIT(val, 37, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_2_EQ_VAL(val)		    vBIT(val, 41, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_3_EQ_VAL(val)		    vBIT(val, 45, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_4_EQ_VAL(val)		    vBIT(val, 49, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_5_EQ_VAL(val)		    vBIT(val, 53, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_6_EQ_VAL(val)		    vBIT(val, 57, 3)
+#define	VXGE_HAL_SERDES_CFG3_RX_7_EQ_VAL(val)		    vBIT(val, 61, 3)
+/* 0x06398 */	u64	vhlabel_to_vplane_cfg[17];
+#define	VXGE_HAL_VHLABEL_TO_VPLANE_CFG_VHLABEL_TO_VPLANE_CFG(val)\
+							    vBIT(val, 3, 5)
+/* 0x06420 */	u64	mrpcim_to_srpcim_vplane_wmsg[17];
+#define	VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_WMSG(val)	    vBIT(val, 0, 64)
+/* 0x064a8 */	u64	mrpcim_to_srpcim_vplane_wmsg_trig[17];
+#define	VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_TRIG_TRIG	    mBIT(0)
+/* 0x06530 */	u64	debug_stats0;
+#define	VXGE_HAL_DEBUG_STATS0_RSTDROP_MSG(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_DEBUG_STATS0_RSTDROP_CPL(val)		    vBIT(val, 32, 32)
+/* 0x06538 */	u64	debug_stats1;
+#define	VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT0(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT1(val)	    vBIT(val, 32, 32)
+/* 0x06540 */	u64	debug_stats2;
+#define	VXGE_HAL_DEBUG_STATS2_RSTDROP_CLIENT2(val)	    vBIT(val, 0, 32)
+/* 0x06548 */	u64	debug_stats3_vplane[17];
+#define	VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_PH(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_NPH(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_CPLH(val)	    vBIT(val, 32, 16)
+/* 0x065d0 */	u64	debug_stats4_vplane[17];
+#define	VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_PD(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_NPD(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_CPLD(val)	    vBIT(val, 32, 16)
+	u8	unused06b00[0x06b00 - 0x06658];
+
+/* 0x06b00 */	u64	rc_rxdmem_end_ofst[16];
+#define	VXGE_HAL_RC_RXDMEM_END_OFST_RC_RXDMEM_END_OFST(val) vBIT(val, 49, 8)
+	u8	unused07000[0x07000 - 0x06b80];
+
+/* 0x07000 */	u64	mrpcim_general_int_status;
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT	    mBIT(0)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCI_INT	    mBIT(1)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT	    mBIT(2)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT	    mBIT(3)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT	    mBIT(4)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT	    mBIT(5)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT	    mBIT(6)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT	    mBIT(7)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT	    mBIT(8)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT	    mBIT(9)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT	    mBIT(10)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT	    mBIT(11)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT	    mBIT(12)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_XMAC_INT	    mBIT(13)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT	    mBIT(14)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TMAC_INT	    mBIT(15)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT	    mBIT(16)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_FBMC_INT	    mBIT(17)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT	    mBIT(18)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TPA_INT	    mBIT(19)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT	    mBIT(20)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_ONE_INT	    mBIT(21)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_MSG_INT	    mBIT(22)
+/* 0x07008 */	u64	mrpcim_general_int_mask;
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PIC_INT	    mBIT(0)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCI_INT	    mBIT(1)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_RTDMA_INT	    mBIT(2)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_WRDMA_INT	    mBIT(3)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT	    mBIT(4)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG1_INT	    mBIT(5)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG2_INT	    mBIT(6)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG3_INT	    mBIT(7)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT	    mBIT(8)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT	    mBIT(9)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG1_INT	    mBIT(10)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG2_INT	    mBIT(11)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG3_INT	    mBIT(12)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_XMAC_INT	    mBIT(13)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_RXMAC_INT	    mBIT(14)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_TMAC_INT	    mBIT(15)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT	    mBIT(16)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_FBMC_INT	    mBIT(17)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT	    mBIT(18)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_TPA_INT	    mBIT(19)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_DRBELL_INT	    mBIT(20)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_ONE_INT	    mBIT(21)
+#define	VXGE_HAL_MRPCIM_GENERAL_INT_MASK_MSG_INT	    mBIT(22)
+/* 0x07010 */	u64	mrpcim_ppif_int_status;
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT  mBIT(3)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT  mBIT(7)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT  mBIT(11)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT mBIT(15)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT mBIT(19)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_MRPCIM_GENERAL_ERRORS_GENERAL_INT\
+							    mBIT(23)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT  mBIT(27)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT\
+							    mBIT(31)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT\
+							    mBIT(32)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT\
+							    mBIT(33)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT\
+							    mBIT(34)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT\
+							    mBIT(35)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT\
+							    mBIT(36)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT\
+							    mBIT(37)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT\
+							    mBIT(38)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT\
+							    mBIT(39)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT\
+							    mBIT(40)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT\
+							    mBIT(41)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT\
+							    mBIT(42)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT\
+							    mBIT(43)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT\
+							    mBIT(44)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT\
+							    mBIT(45)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT\
+							    mBIT(46)
+#define	\
+    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT\
+							    mBIT(47)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_SRPCIM_TO_MRPCIM_ALARM_INT  mBIT(51)
+#define	VXGE_HAL_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_INT   mBIT(55)
+/* 0x07018 */	u64	mrpcim_ppif_int_mask;
+	u8	unused07028[0x07028 - 0x07020];
+
+/* 0x07028 */	u64	ini_errors_reg;
+#define	VXGE_HAL_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG mBIT(3)
+#define	VXGE_HAL_INI_ERRORS_REG_SCPL_CPL_TIMEOUT	    mBIT(7)
+#define	VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR		    mBIT(11)
+#define	VXGE_HAL_INI_ERRORS_REG_DCPL_POISON		    mBIT(12)
+#define	VXGE_HAL_INI_ERRORS_REG_DCPL_UNSUPPORTED	    mBIT(15)
+#define	VXGE_HAL_INI_ERRORS_REG_DCPL_ABORT		    mBIT(19)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_TLP_ABORT		    mBIT(23)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_DLLP_ABORT		    mBIT(27)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_ECRC_ERR		    mBIT(31)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_BUF_DB_ERR		    mBIT(35)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_BUF_SG_ERR		    mBIT(39)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_DATA_OVERFLOW	    mBIT(43)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_HDR_OVERFLOW	    mBIT(47)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_MRD_SYS_DROP	    mBIT(51)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_MWR_SYS_DROP	    mBIT(55)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_MRD_CLIENT_DROP	    mBIT(59)
+#define	VXGE_HAL_INI_ERRORS_REG_INI_MWR_CLIENT_DROP	    mBIT(63)
+/* 0x07030 */	u64	ini_errors_mask;
+/* 0x07038 */	u64	ini_errors_alarm;
+/* 0x07040 */	u64	dma_errors_reg;
+#define	VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR		    mBIT(3)
+#define	VXGE_HAL_DMA_ERRORS_REG_WRARB_FSM_ERR		    mBIT(7)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW   mBIT(8)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW  mBIT(9)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW  mBIT(10)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW mBIT(11)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW	    mBIT(12)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW    mBIT(13)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW    mBIT(14)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW   mBIT(15)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW   mBIT(16)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW  mBIT(17)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW  mBIT(18)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW mBIT(19)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW   mBIT(20)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW  mBIT(21)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW  mBIT(22)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW mBIT(23)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW   mBIT(24)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW  mBIT(25)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW   mBIT(28)
+#define	VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW  mBIT(29)
+#define	VXGE_HAL_DMA_ERRORS_REG_DBLGEN_FSM_ERR		    mBIT(32)
+#define	VXGE_HAL_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR	    mBIT(33)
+#define	VXGE_HAL_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR	    mBIT(34)
+/* 0x07048 */	u64	dma_errors_mask;
+/* 0x07050 */	u64	dma_errors_alarm;
+/* 0x07058 */	u64	tgt_errors_reg;
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_VENDOR_MSG		    mBIT(0)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_MSG_UNLOCK		    mBIT(1)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE	    mBIT(2)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_BOOT_WRITE		    mBIT(3)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE    mBIT(4)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE  mBIT(5)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_KDFC_READ		    mBIT(6)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_USDC_READ		    mBIT(7)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE   mBIT(8)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE	    mBIT(9)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON	    mBIT(10)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON	    mBIT(11)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON	    mBIT(12)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON	    mBIT(13)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON	    mBIT(14)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_NOT_MEM_TLP		    mBIT(15)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP	    mBIT(16)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR		    mBIT(17)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_CPL_FSM_ERR		    mBIT(18)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR	    mBIT(19)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR	    mBIT(20)
+#define	VXGE_HAL_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR   mBIT(21)
+/* 0x07060 */	u64	tgt_errors_mask;
+/* 0x07068 */	u64	tgt_errors_alarm;
+/* 0x07070 */	u64	config_errors_reg;
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND    mBIT(3)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND   mBIT(7)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT	    mBIT(11)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE	    mBIT(15)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR	    mBIT(19)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_REQ_COLLISION	    mBIT(23)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR	    mBIT(27)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT	    mBIT(31)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT	    mBIT(35)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_CFGM_FSM_ERR		    mBIT(39)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_RIC_FSM_ERR		    mBIT(43)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS	    mBIT(47)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TIMEOUT		    mBIT(51)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_PIFM_FSM_ERR		    mBIT(55)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR	    mBIT(59)
+#define	VXGE_HAL_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT	    mBIT(63)
+/* 0x07078 */	u64	config_errors_mask;
+/* 0x07080 */	u64	config_errors_alarm;
+	u8	unused07090[0x07090 - 0x07088];
+
+/* 0x07090 */	u64	crdt_errors_reg;
+#define	VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR	    mBIT(11)
+#define	VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL mBIT(15)
+#define	VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL	mBIT(19)
+#define	VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL mBIT(23)
+#define	VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR	    mBIT(35)
+#define	VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL	mBIT(39)
+#define	VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL	mBIT(43)
+#define	VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL mBIT(47)
+/* 0x07098 */	u64	crdt_errors_mask;
+/* 0x070a0 */	u64	crdt_errors_alarm;
+	u8	unused070b0[0x070b0 - 0x070a8];
+
+/* 0x070b0 */	u64	mrpcim_general_errors_reg;
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR   mBIT(3)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR	    mBIT(7)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR	    mBIT(11)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR  mBIT(15)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR mBIT(19)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR	    mBIT(23)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR  mBIT(27)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR mBIT(31)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET	    mBIT(35)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR mBIT(39)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW mBIT(43)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_SW_RESET\
+							    mBIT(47)
+#define	VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR mBIT(51)
+/* 0x070b8 */	u64	mrpcim_general_errors_mask;
+/* 0x070c0 */	u64	mrpcim_general_errors_alarm;
+	u8	unused070d0[0x070d0 - 0x070c8];
+
+/* 0x070d0 */	u64	pll_errors_reg;
+#define	VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL	    mBIT(3)
+#define	VXGE_HAL_PLL_ERRORS_REG_CORE_FB_PLL_OOL		    mBIT(7)
+#define	VXGE_HAL_PLL_ERRORS_REG_CORE_X_PLL_OOL		    mBIT(11)
+/* 0x070d8 */	u64	pll_errors_mask;
+/* 0x070e0 */	u64	pll_errors_alarm;
+/* 0x070e8 */	u64	srpcim_to_mrpcim_alarm_reg;
+#define	VXGE_HAL_SRPCIM_TO_MRPCIM_ALARM_REG_ALARM(val)	    vBIT(val, 0, 17)
+/* 0x070f0 */	u64	srpcim_to_mrpcim_alarm_mask;
+/* 0x070f8 */	u64	srpcim_to_mrpcim_alarm_alarm;
+/* 0x07100 */	u64	vpath_to_mrpcim_alarm_reg;
+#define	VXGE_HAL_VPATH_TO_MRPCIM_ALARM_REG_ALARM(val)	    vBIT(val, 0, 17)
+/* 0x07108 */	u64	vpath_to_mrpcim_alarm_mask;
+/* 0x07110 */	u64	vpath_to_mrpcim_alarm_alarm;
+	u8	unused07128[0x07128 - 0x07118];
+
+/* 0x07128 */	u64	crdt_errors_vplane_reg[17];
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR	mBIT(3)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR	mBIT(7)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR	mBIT(11)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR	mBIT(15)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR	mBIT(19)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR	mBIT(23)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR	mBIT(27)
+#define	VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR	mBIT(31)
+/* 0x07130 */	u64	crdt_errors_vplane_mask[17];
+/* 0x07138 */	u64	crdt_errors_vplane_alarm[17];
+	u8	unused072f0[0x072f0 - 0x072c0];
+
+/* 0x072f0 */	u64	mrpcim_rst_in_prog;
+#define	VXGE_HAL_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG	    mBIT(7)
+/* 0x072f8 */	u64	mrpcim_reg_modified;
+#define	VXGE_HAL_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED    mBIT(7)
+/* 0x07300 */	u64	split_table_status1;
+#define	VXGE_HAL_SPLIT_TABLE_STATUS1_SCPL_TAG_ENTRY1(val)   vBIT(val, 0, 64)
+/* 0x07308 */	u64	split_table_status2;
+#define	VXGE_HAL_SPLIT_TABLE_STATUS2_SCPL_TAG_ENTRY2(val)   vBIT(val, 0, 64)
+/* 0x07310 */	u64	split_table_status3;
+#define	VXGE_HAL_SPLIT_TABLE_STATUS3_SCPL_TAG_ENTRY3(val)   vBIT(val, 0, 64)
+/* 0x07318 */	u64	mrpcim_general_status1;
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS1_INI_RCPL_ERRSYND(val) vBIT(val, 0, 8)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS1_XGMAC_MISC_INT_ALARM  mBIT(11)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS1_SCPL_NUM_OUTSTANDING_RDS(val)\
+							    vBIT(val, 18, 6)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS1_TGT_VENDOR_MSG_PAYLOAD(val)\
+							    vBIT(val, 32, 32)
+/* 0x07320 */	u64	mrpcim_general_status2;
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS2_CFGM_TIMEOUT_ADDR(val) vBIT(val, 6, 10)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS2_RIC_TIMEOUT_ADDR(val) vBIT(val, 22, 10)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_CLIENT(val)\
+							    vBIT(val, 34, 2)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_RD_WRN mBIT(39)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_ADDR(val) vBIT(val, 44, 20)
+/* 0x07328 */	u64	mrpcim_general_status3;
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_PIFM_TIMEOUT_ADDR(val) vBIT(val, 0, 20)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_FMT(val)\
+							    vBIT(val, 21, 2)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_TYPE(val)\
+							    vBIT(val, 23, 5)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_FMT(val)\
+							    vBIT(val, 29, 2)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_TYPE(val)\
+							    vBIT(val, 31, 5)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE0\
+							    mBIT(40)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE1\
+							    mBIT(41)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE2\
+							    mBIT(42)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE3\
+							    mBIT(43)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE4\
+							    mBIT(44)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE5\
+							    mBIT(45)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE6\
+							    mBIT(46)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE7\
+							    mBIT(47)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE8\
+							    mBIT(48)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE9\
+							    mBIT(49)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE10\
+							    mBIT(50)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE11\
+							    mBIT(51)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE12\
+							    mBIT(52)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE13\
+							    mBIT(53)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE14\
+							    mBIT(54)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE15\
+							    mBIT(55)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE16\
+							    mBIT(56)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_TAGS_DEPLETED mBIT(60)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_RDA_TAGS mBIT(61)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_PDA_TAGS mBIT(62)
+#define	VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_DBLGEN_TAGS\
+							    mBIT(63)
+	u8	unused07338[0x07338 - 0x07330];
+
+/* 0x07338 */	u64	test_status;
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_TX_WR_EP_DONE	    mBIT(3)
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_TX_RD_EP_DONE	    mBIT(7)
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_TX_CPL_EP_DONE	    mBIT(11)
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_TX_ECRCERR_DONE	    mBIT(15)
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_TX_LCRCERR_DONE	    mBIT(19)
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_RX_ECRCERR_DONE	    mBIT(23)
+#define	VXGE_HAL_TEST_STATUS_PERR_INS_RX_LCRCERR_DONE	    mBIT(27)
+	u8	unused07348[0x07348 - 0x07340];
+
+/* 0x07348 */	u64	kdfcctl_dbg_status;
+#define	VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_ADDR_ERR(val)   vBIT(val, 2, 22)
+#define	VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_FIFO_NO_ERR(val) vBIT(val, 26, 6)
+/* 0x07350 */	u64	msix_addr;
+#define	VXGE_HAL_MSIX_ADDR_MSIX_ADDR(val)		    vBIT(val, 0, 64)
+/* 0x07358 */	u64	msix_table;
+#define	VXGE_HAL_MSIX_TABLE_DATA(val)			    vBIT(val, 0, 32)
+#define	VXGE_HAL_MSIX_TABLE_MASK			    mBIT(63)
+/* 0x07360 */	u64	msix_ctl;
+#define	VXGE_HAL_MSIX_CTL_VECTOR_NO(val)		    vBIT(val, 1, 7)
+#define	VXGE_HAL_MSIX_CTL_WRITE_OR_READ			    mBIT(15)
+/* 0x07368 */	u64	msix_access_table;
+#define	VXGE_HAL_MSIX_ACCESS_TABLE_MSIX_ACCESS_TABLE	    mBIT(0)
+	u8	unused07378[0x07378 - 0x07370];
+
+/* 0x07378 */	u64	write_arb_pending;
+#define	VXGE_HAL_WRITE_ARB_PENDING_WRARB_WRDMA		    mBIT(3)
+#define	VXGE_HAL_WRITE_ARB_PENDING_WRARB_RTDMA		    mBIT(7)
+#define	VXGE_HAL_WRITE_ARB_PENDING_WRARB_MSG		    mBIT(11)
+#define	VXGE_HAL_WRITE_ARB_PENDING_WRARB_STATSB		    mBIT(15)
+#define	VXGE_HAL_WRITE_ARB_PENDING_WRARB_INTCTL		    mBIT(19)
+/* 0x07380 */	u64	read_arb_pending;
+#define	VXGE_HAL_READ_ARB_PENDING_RDARB_WRDMA		    mBIT(3)
+#define	VXGE_HAL_READ_ARB_PENDING_RDARB_RTDMA		    mBIT(7)
+#define	VXGE_HAL_READ_ARB_PENDING_RDARB_DBLGEN		    mBIT(11)
+/* 0x07388 */	u64	dmaif_dmadbl_pending;
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR	    mBIT(0)
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD	    mBIT(1)
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR	    mBIT(2)
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD	    mBIT(3)
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR	    mBIT(4)
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR	    mBIT(5)
+#define	VXGE_HAL_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val)   vBIT(val, 13, 51)
+/* 0x07390 */	u64	wrcrdtarb_status0_vplane[17];
+#define	VXGE_HAL_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val)\
+							    vBIT(val, 0, 8)
+/* 0x07418 */	u64	wrcrdtarb_status1_vplane[17];
+#define	VXGE_HAL_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val)\
+							    vBIT(val, 4, 12)
+	u8	unused07500[0x07500 - 0x074a0];
+
+/* 0x07500 */	u64	mrpcim_general_cfg1;
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG1_CLEAR_SERR		    mBIT(7)
+/* 0x07508 */	u64	mrpcim_general_cfg2;
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD	    mBIT(3)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD	    mBIT(7)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD	    mBIT(11)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR	    mBIT(15)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD	    mBIT(19)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX mBIT(23)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB	    mBIT(27)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR   mBIT(31)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE    mBIT(43)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val)\
+							    vBIT(val, 47, 5)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR mBIT(55)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA	    mBIT(59)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS   mBIT(63)
+/* 0x07510 */	u64	mrpcim_general_cfg3;
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN mBIT(0)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN mBIT(3)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN	    mBIT(7)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN	    mBIT(11)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN	    mBIT(15)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN	    mBIT(19)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val)	    vBIT(val, 20, 16)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val)   vBIT(val, 36, 16)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN	    mBIT(55)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val)  vBIT(val, 56, 2)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N	    mBIT(59)
+#define	VXGE_HAL_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN	    mBIT(63)
+/* 0x07518 */	u64	mrpcim_stats_start_host_addr;
+#define	VXGE_HAL_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\
+							    vBIT(val, 0, 57)
+/* 0x07520 */	u64	asic_mode;
+#define	VXGE_HAL_ASIC_MODE_PIC(val)			    vBIT(val, 2, 2)
+/* 0x07528 */	u64	dis_fw_pipeline_wr;
+#define	VXGE_HAL_DIS_FW_PIPELINE_WR_DIS_FW_PIPELINE_WR	    mBIT(0)
+/* 0x07530 */	u64	ini_timeout_val;
+#define	VXGE_HAL_INI_TIMEOUT_VAL_MWR(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_INI_TIMEOUT_VAL_MRD(val)		    vBIT(val, 32, 32)
+/* 0x07538 */	u64	pic_arbiter_cfg;
+#define	VXGE_HAL_PIC_ARBITER_CFG_DMA_READ_EN		    mBIT(3)
+#define	VXGE_HAL_PIC_ARBITER_CFG_DMA_WRITE_EN		    mBIT(7)
+#define	VXGE_HAL_PIC_ARBITER_CFG_DBLGEN_WRR_EN		    mBIT(11)
+#define	VXGE_HAL_PIC_ARBITER_CFG_WRCRDTARB_EN		    mBIT(15)
+#define	VXGE_HAL_PIC_ARBITER_CFG_RDCRDTARB_EN		    mBIT(19)
+/* 0x07540 */	u64	read_arbiter;
+#define	VXGE_HAL_READ_ARBITER_WRDMA_PRIORITY(val)	    vBIT(val, 2, 2)
+#define	VXGE_HAL_READ_ARBITER_RTDMA_PRIORITY(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_READ_ARBITER_DBLGEN_PRIORITY(val)	    vBIT(val, 10, 2)
+#define	VXGE_HAL_READ_ARBITER_CALSTATE0_PRIORITY(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_READ_ARBITER_CALSTATE1_PRIORITY(val)	    vBIT(val, 18, 2)
+#define	VXGE_HAL_READ_ARBITER_CALSTATE2_PRIORITY(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_READ_ARBITER_CALSTATE3_PRIORITY(val)	    vBIT(val, 26, 2)
+#define	VXGE_HAL_READ_ARBITER_CALSTATE4_PRIORITY(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_READ_ARBITER_CALSTATE5_PRIORITY(val)	    vBIT(val, 34, 2)
+#define	VXGE_HAL_READ_ARBITER_CHECK_PRIORITY_MATCH_ONLY	    mBIT(39)
+/* 0x07548 */	u64	write_arbiter;
+#define	VXGE_HAL_WRITE_ARBITER_WRDMA_PRIORITY(val)	    vBIT(val, 2, 2)
+#define	VXGE_HAL_WRITE_ARBITER_RTDMA_PRIORITY(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_WRITE_ARBITER_STATS_PRIORITY(val)	    vBIT(val, 10, 2)
+#define	VXGE_HAL_WRITE_ARBITER_MSG_PRIORITY(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE0_PRIORITY(val)	    vBIT(val, 18, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE1_PRIORITY(val)	    vBIT(val, 22, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE2_PRIORITY(val)	    vBIT(val, 26, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE3_PRIORITY(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE4_PRIORITY(val)	    vBIT(val, 34, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE5_PRIORITY(val)	    vBIT(val, 38, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE6_PRIORITY(val)	    vBIT(val, 42, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE7_PRIORITY(val)	    vBIT(val, 46, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE8_PRIORITY(val)	    vBIT(val, 50, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CALSTATE9_PRIORITY(val)	    vBIT(val, 52, 2)
+#define	VXGE_HAL_WRITE_ARBITER_CHECK_PRIORITY_MATCH_ONLY    mBIT(55)
+/* 0x07550 */	u64	adapter_control;
+#define	VXGE_HAL_ADAPTER_CONTROL_ADAPTER_EN		    mBIT(7)
+#define	VXGE_HAL_ADAPTER_CONTROL_DISABLE_RIC		    mBIT(49)
+#define	VXGE_HAL_ADAPTER_CONTROL_ECC_ENABLE_N		    mBIT(55)
+/* 0x07558 */	u64	program_cfg0;
+#define	VXGE_HAL_PROGRAM_CFG0_I2C_SLAVE_ADDR(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_PROGRAM_CFG0_CFGM_TIMEOUT_EN		    mBIT(11)
+#define	VXGE_HAL_PROGRAM_CFG0_PIFM_TIMEOUT_EN		    mBIT(15)
+/* 0x07560 */	u64	program_cfg1;
+#define	VXGE_HAL_PROGRAM_CFG1_CFGM_TIMEOUT_LOAD_VAL(val)    vBIT(val, 0, 32)
+#define	VXGE_HAL_PROGRAM_CFG1_PIFM_TIMEOUT_LOAD_VAL(val)    vBIT(val, 32, 32)
+/* 0x07568 */	u64	dblgen_wrr_cfg1;
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_0_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_1_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_2_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_3_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_4_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_5_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_6_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_7_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07570 */	u64	dblgen_wrr_cfg2;
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_8_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_9_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_10_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_11_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_12_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_13_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_14_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_15_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07578 */	u64	dblgen_wrr_cfg3;
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_16_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_17_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_18_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_19_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_20_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_21_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_22_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_23_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07580 */	u64	dblgen_wrr_cfg4;
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_24_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_25_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_26_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_27_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_28_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_29_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_30_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_31_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07588 */	u64	dblgen_wrr_cfg5;
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_32_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_33_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_34_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_35_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_36_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_37_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_38_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_39_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07590 */	u64	dblgen_wrr_cfg6;
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_40_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_41_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_42_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_43_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_44_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_45_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_46_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_47_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07598 */	u64	dblgen_wrr_cfg7;
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_48_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_49_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_50_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_51_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_52_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_53_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_54_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_55_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075a0 */	u64	dblgen_wrr_cfg8;
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_56_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_57_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_58_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_59_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_60_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_61_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_62_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_63_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075a8 */	u64	dblgen_wrr_cfg9;
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_64_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_65_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_66_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_67_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_68_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_69_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_70_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_71_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075b0 */	u64	dblgen_wrr_cfg10;
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_72_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_73_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_74_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_75_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_76_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_77_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_78_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_79_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075b8 */	u64	dblgen_wrr_cfg11;
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_80_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_81_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_82_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_83_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_84_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_85_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_86_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_87_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075c0 */	u64	dblgen_wrr_cfg12;
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_88_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_89_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_90_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_91_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_92_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_93_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_94_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_95_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075c8 */	u64	dblgen_wrr_cfg13;
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_96_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_97_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_98_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_99_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_100_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_101_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_102_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_103_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075d0 */	u64	dblgen_wrr_cfg14;
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_104_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_105_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_106_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_107_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_108_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_109_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_110_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_111_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075d8 */	u64	dblgen_wrr_cfg15;
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_112_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_113_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_114_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_115_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_116_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_117_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_118_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_119_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075e0 */	u64	dblgen_wrr_cfg16;
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_120_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_121_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_122_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_123_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_124_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_125_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_126_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_127_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075e8 */	u64	dblgen_wrr_cfg17;
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_128_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_129_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_130_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_131_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_132_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_133_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_134_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_135_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075f0 */	u64	dblgen_wrr_cfg18;
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_136_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_137_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_138_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_139_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_140_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_141_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_142_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_143_NUM(val)	    vBIT(val, 59, 5)
+/* 0x075f8 */	u64	dblgen_wrr_cfg19;
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_144_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_145_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_146_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_147_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_148_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_149_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_150_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_151_NUM(val)	    vBIT(val, 59, 5)
+/* 0x07600 */	u64	dblgen_wrr_cfg20;
+#define	VXGE_HAL_DBLGEN_WRR_CFG20_CTRL_SS_152_NUM(val)	    vBIT(val, 3, 5)
+/* 0x07608 */	u64	debug_cfg1;
+#define	VXGE_HAL_DEBUG_CFG1_TAG_TO_OBSERVE(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_DEBUG_CFG1_DIS_REL_OF_TAG_DUE_TO_ERR	    mBIT(11)
+	u8	unused07900[0x07900 - 0x07610];
+
+/* 0x07900 */	u64	test_cfg1;
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_TX_WR_EP		    mBIT(19)
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_TX_RD_EP		    mBIT(23)
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_TX_CPL_EP		    mBIT(27)
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_TX_ECRCERR		    mBIT(31)
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_TX_LCRCERR		    mBIT(35)
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_RX_ECRCERR		    mBIT(39)
+#define	VXGE_HAL_TEST_CFG1_PERR_INS_RX_LCRCERR		    mBIT(43)
+/* 0x07908 */	u64	test_cfg2;
+#define	VXGE_HAL_TEST_CFG2_PERR_TIMEOUT_VAL(val)	    vBIT(val, 0, 32)
+/* 0x07910 */	u64	test_cfg3;
+#define	VXGE_HAL_TEST_CFG3_PERR_TRIGGER_TIMER		    mBIT(0)
+/* 0x07918 */	u64	wrcrdtarb_cfg0;
+#define	VXGE_HAL_WRCRDTARB_CFG0_WAIT_CNT(val)		    vBIT(val, 48, 4)
+#define	VXGE_HAL_WRCRDTARB_CFG0_STATS_PRTY_TIMEOUT_EN	    mBIT(55)
+#define	VXGE_HAL_WRCRDTARB_CFG0_STATS_DROP_TIMEOUT_EN	    mBIT(59)
+#define	VXGE_HAL_WRCRDTARB_CFG0_EN_XON			    mBIT(63)
+/* 0x07920 */	u64	wrcrdtarb_cfg1;
+#define	VXGE_HAL_WRCRDTARB_CFG1_RST_CREDIT		    mBIT(0)
+/* 0x07928 */	u64	wrcrdtarb_cfg2;
+#define	VXGE_HAL_WRCRDTARB_CFG2_STATS_PRTY_TIMEOUT_VAL(val) vBIT(val, 0, 32)
+#define	VXGE_HAL_WRCRDTARB_CFG2_STATS_DROP_TIMEOUT_VAL(val) vBIT(val, 32, 32)
+/* 0x07930 */	u64	test_wrcrdtarb_cfg1;
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\
+							    vBIT(val, 32, 32)
+/* 0x07938 */	u64	test_wrcrdtarb_cfg2;
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\
+							    vBIT(val, 32, 32)
+/* 0x07940 */	u64	test_wrcrdtarb_cfg3;
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT1_MAP(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT2_MAP(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT3_MAP(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT4_MAP(val)	    vBIT(val, 27, 5)
+/* 0x07948 */	u64	test_wrcrdtarb_cfg4;
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT1_EN mBIT(3)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT2_EN mBIT(7)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT3_EN mBIT(11)
+#define	VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT4_EN mBIT(15)
+/* 0x07950 */	u64	rdcrdtarb_cfg0;
+#define	VXGE_HAL_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 18, 6)
+#define	VXGE_HAL_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 26, 6)
+#define	VXGE_HAL_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) vBIT(val, 34, 6)
+#define	VXGE_HAL_RDCRDTARB_CFG0_WAIT_CNT(val)		    vBIT(val, 48, 4)
+#define	VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val)    vBIT(val, 54, 6)
+#define	VXGE_HAL_RDCRDTARB_CFG0_EN_XON			    mBIT(63)
+/* 0x07958 */	u64	rdcrdtarb_cfg1;
+#define	VXGE_HAL_RDCRDTARB_CFG1_RST_CREDIT		    mBIT(0)
+/* 0x07960 */	u64	rdcrdtarb_cfg2;
+#define	VXGE_HAL_RDCRDTARB_CFG2_SOFTNAK_TIMER_VAL_DIV4(val) vBIT(val, 0, 32)
+/* 0x07968 */	u64	test_rdcrdtarb_cfg1;
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\
+							    vBIT(val, 32, 32)
+/* 0x07970 */	u64	test_rdcrdtarb_cfg2;
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\
+							    vBIT(val, 32, 32)
+/* 0x07978 */	u64	test_rdcrdtarb_cfg3;
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT1_MAP(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT2_MAP(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT3_MAP(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT4_MAP(val)	    vBIT(val, 27, 5)
+/* 0x07980 */	u64	test_rdcrdtarb_cfg4;
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT1_EN mBIT(3)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT2_EN mBIT(7)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT3_EN mBIT(11)
+#define	VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT4_EN mBIT(15)
+/* 0x07988 */	u64	pic_debug_control;
+#define	VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKA_SEL(val)    vBIT(val, 0, 4)
+#define	VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKB_SEL(val)    vBIT(val, 4, 4)
+#define	VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DA_SEL(val)	    vBIT(val, 10, 6)
+#define	VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DB_SEL(val)	    vBIT(val, 18, 6)
+#define	VXGE_HAL_PIC_DEBUG_CONTROL_DBGA_SEL(val)	    vBIT(val, 28, 4)
+#define	VXGE_HAL_PIC_DEBUG_CONTROL_DBGB_SEL(val)	    vBIT(val, 32, 4)
+	u8	unused079d8[0x079d8 - 0x07990];
+
+/* 0x079d8 */	u64	spi_control_3_reg;
+#define	VXGE_HAL_SPI_CONTROL_3_REG_SECTOR_0_WR_EN(val)	    vBIT(val, 0, 32)
+/* 0x079e0 */	u64	clock_cfg0;
+#define	VXGE_HAL_CLOCK_CFG0_ONE_LRO_EN			    mBIT(3)
+#define	VXGE_HAL_CLOCK_CFG0_ONE_IWARP_EN		    mBIT(7)
+/* 0x079e8 */	u64	stats_bp_ctrl;
+#define	VXGE_HAL_STATS_BP_CTRL_WR_XON			    mBIT(7)
+/* 0x079f0 */	u64	kdfcdma_bp_ctrl;
+#define	VXGE_HAL_KDFCDMA_BP_CTRL_RD_XON			    mBIT(3)
+/* 0x079f8 */	u64	intctl_bp_ctrl;
+#define	VXGE_HAL_INTCTL_BP_CTRL_WR_XON			    mBIT(3)
+/* 0x07a00 */	u64	vector_srpcim_alarm_map[9];
+#define	VXGE_HAL_VECTOR_SRPCIM_ALARM_MAP_VECTOR_SRPCIM_ALARM_MAP(val)\
+							    vBIT(val, 17, 7)
+	u8	unused07b10[0x07b10 - 0x07a48];
+
+/* 0x07b10 */	u64	vplane_rdcrdtarb_cfg0[17];
+#define	VXGE_HAL_VPLANE_RDCRDTARB_CFG0_TAGS_THRESHOLD_XOFF(val)\
+							    vBIT(val, 27, 5)
+#define	VXGE_HAL_VPLANE_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val)\
+							    vBIT(val, 34, 6)
+	u8	unused07ba0[0x07ba0 - 0x07b98];
+
+/* 0x07ba0 */	u64	mrpcim_spi_control;
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_KEY(val)		    vBIT(val, 0, 4)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_SEL1		    mBIT(4)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_NACK		    mBIT(5)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_DONE		    mBIT(6)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_REQ			    mBIT(7)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_BYTE_CNT(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_CMD(val)		    vBIT(val, 32, 8)
+#define	VXGE_HAL_MRPCIM_SPI_CONTROL_ADD(val)		    vBIT(val, 40, 24)
+/* 0x07ba8 */	u64	mrpcim_spi_data;
+#define	VXGE_HAL_MRPCIM_SPI_DATA_SPI_RWDATA(val)	    vBIT(val, 0, 64)
+/* 0x07bb0 */	u64	mrpcim_spi_write_protect;
+#define	VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_HWPE		    mBIT(7)
+#define	VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SPI_16ADDR_EN	    mBIT(14)
+#define	VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SPI_2DEV_EN	    mBIT(15)
+#define	VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SLOWCK	    mBIT(63)
+	u8	unused07be0[0x07be0 - 0x07bb8];
+
+/* 0x07be0 */	u64	chip_full_reset;
+#define	VXGE_HAL_CHIP_FULL_RESET_CHIP_FULL_RESET(val)	    vBIT(val, 0, 8)
+/* 0x07be8 */	u64	bf_sw_reset;
+#define	VXGE_HAL_BF_SW_RESET_BF_SW_RESET(val)		    vBIT(val, 0, 8)
+/* 0x07bf0 */	u64	sw_reset_status;
+#define	VXGE_HAL_SW_RESET_STATUS_RESET_CMPLT		    mBIT(7)
+#define	VXGE_HAL_SW_RESET_STATUS_INIT_CMPLT		    mBIT(15)
+	u8	unused07c28[0x07c20 - 0x07bf8];
+
+/* 0x07c20 */	u64	sw_reset_cfg1;
+#define	VXGE_HAL_SW_RESET_CFG1_TYPE			    mBIT(0)
+#define	VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_FOR_FLUSH_PCI(val) vBIT(val, 7, 25)
+#define	VXGE_HAL_SW_RESET_CFG1_SOPR_ASSERT_TIME(val)	    vBIT(val, 32, 4)
+#define	VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_AFTER_RESET(val)   vBIT(val, 38, 25)
+/* 0x07c28 */	u64	ric_timeout;
+#define	VXGE_HAL_RIC_TIMEOUT_EN				    mBIT(3)
+#define	VXGE_HAL_RIC_TIMEOUT_VAL(val)			    vBIT(val, 32, 32)
+/* 0x07c30 */	u64	mrpcim_pci_config_access_cfg1;
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vBIT(val, 4, 10)
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_VPLANE(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_FUNC(val)    vBIT(val, 27, 5)
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_RD_OR_WRN    mBIT(39)
+/* 0x07c38 */	u64	mrpcim_pci_config_access_cfg2;
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG2_REQ	    mBIT(0)
+/* 0x07c40 */	u64	mrpcim_pci_config_access_status;
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR mBIT(0)
+#define	VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_DATA(val)  vBIT(val, 32, 32)
+	u8	unused07ca8[0x07ca8 - 0x07c48];
+
+/* 0x07ca8 */	u64	rdcrdtarb_status0_vplane[17];
+#define	VXGE_HAL_RDCRDTARB_STATUS0_VPLANE_RDCRDTARB_ABS_AVAIL_NP_H(val)\
+							    vBIT(val, 0, 8)
+/* 0x07d30 */	u64	mrpcim_debug_stats0;
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val)	    vBIT(val, 32, 32)
+/* 0x07d38 */	u64	mrpcim_debug_stats1_vplane[17];
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val)\
+							    vBIT(val, 32, 32)
+/* 0x07dc0 */	u64	mrpcim_debug_stats2_vplane[17];
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val)\
+							    vBIT(val, 32, 32)
+/* 0x07e48 */	u64	mrpcim_debug_stats3_vplane[17];
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val)\
+							    vBIT(val, 32, 32)
+/* 0x07ed0 */	u64	mrpcim_debug_stats4;
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val)  vBIT(val, 0, 32)
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val)  vBIT(val, 32, 32)
+/* 0x07ed8 */	u64	genstats_count01;
+#define	VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT1(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT0(val)	    vBIT(val, 32, 32)
+/* 0x07ee0 */	u64	genstats_count23;
+#define	VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT3(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT2(val)	    vBIT(val, 32, 32)
+/* 0x07ee8 */	u64	genstats_count4;
+#define	VXGE_HAL_GENSTATS_COUNT4_GENSTATS_COUNT4(val)	    vBIT(val, 32, 32)
+/* 0x07ef0 */	u64	genstats_count5;
+#define	VXGE_HAL_GENSTATS_COUNT5_GENSTATS_COUNT5(val)	    vBIT(val, 32, 32)
+/* 0x07ef8 */	u64	mrpcim_mmio_cfg1;
+#define	VXGE_HAL_MRPCIM_MMIO_CFG1_WRITE_DATA(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_MRPCIM_MMIO_CFG1_ADDRESS(val)		    vBIT(val, 34, 6)
+#define	VXGE_HAL_MRPCIM_MMIO_CFG1_MRIOVCTL_READ_DATA(val)   vBIT(val, 48, 16)
+/* 0x07f00 */	u64	mrpcim_mmio_cfg2;
+#define	VXGE_HAL_MRPCIM_MMIO_CFG2_WRITE_CS		    mBIT(0)
+/* 0x07f08 */	u64	genstats_cfg[6];
+#define	VXGE_HAL_GENSTATS_CFG_DTYPE_SEL(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_GENSTATS_CFG_CLIENT_NO_SEL(val)	    vBIT(val, 9, 3)
+#define	VXGE_HAL_GENSTATS_CFG_WR_RD_CPL_SEL(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_GENSTATS_CFG_VPATH_SEL(val)		    vBIT(val, 31, 17)
+/* 0x07f38 */	u64	genstat_64bit_cfg;
+#define	VXGE_HAL_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0	    mBIT(3)
+#define	VXGE_HAL_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2	    mBIT(7)
+/* 0x07f40 */	u64	pll_slip_counters;
+#define	VXGE_HAL_PLL_SLIP_COUNTERS_CMG(val)		    vBIT(val, 0, 16)
+#define	VXGE_HAL_PLL_SLIP_COUNTERS_FB(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_PLL_SLIP_COUNTERS_X(val)		    vBIT(val, 32, 16)
+	u8	unused08000[0x08000 - 0x07f48];
+
+/* 0x08000 */	u64	gcmg3_int_status;
+#define	VXGE_HAL_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT	    mBIT(0)
+#define	VXGE_HAL_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT	    mBIT(1)
+#define	VXGE_HAL_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT	    mBIT(2)
+#define	VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT	    mBIT(3)
+#define	VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT	    mBIT(4)
+#define	VXGE_HAL_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT	    mBIT(5)
+#define	VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT	    mBIT(6)
+/* 0x08008 */	u64	gcmg3_int_mask;
+/* 0x08010 */	u64	gstc_err0_reg;
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_DB_ERR(val)    vBIT(val, 0, 3)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_DB_ERR(val)    vBIT(val, 3, 5)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_DB_ERR(val)   vBIT(val, 8, 4)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_DB_ERR(val)   vBIT(val, 12, 4)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_DB_ERR(val)    vBIT(val, 16, 5)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_DB_ERR(val)    vBIT(val, 21, 3)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_DB_ERR(val)	    vBIT(val, 24, 2)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_CMCIF_RD_DATA_DB_ERR	    mBIT(26)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_SG_ERR(val)    vBIT(val, 32, 3)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_SG_ERR(val)    vBIT(val, 35, 5)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_SG_ERR(val)   vBIT(val, 40, 4)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_SG_ERR(val)   vBIT(val, 44, 4)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_SG_ERR(val)    vBIT(val, 48, 5)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_SG_ERR(val)    vBIT(val, 53, 3)
+#define	VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_SG_ERR(val)	    vBIT(val, 56, 2)
+/* 0x08018 */	u64	gstc_err0_mask;
+/* 0x08020 */	u64	gstc_err0_alarm;
+/* 0x08028 */	u64	gstc_err1_reg;
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_REQ_FIFO_ERR	    mBIT(0)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_ECRESP_FIFO_ERR    mBIT(1)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_BUFFRESP_FIFO_ERR  mBIT(2)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_H2L_EVENT_FIFO_ERR	    mBIT(3)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ARB_RPE_FIFO_ERR	    mBIT(4)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ARB_REQ_FIFO_ERR	    mBIT(5)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SSM_EVENT_FIFO_ERR	    mBIT(6)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SSM_CMRSP_FIFO_ERR	    mBIT(7)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ECI_ARB_FIFO_ERR	    mBIT(8)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_EVENT_FIFO_ERR	    mBIT(9)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_FIFO_ERR	    mBIT(10)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_BDM_EVENT_FIFO_ERR	    mBIT(11)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_BDM_CMRSP_FIFO_ERR	    mBIT(12)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_FIFO_ERR	    mBIT(13)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_CP2STC_FIFO_ERR	    mBIT(14)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_CPIF_CREDIT_FIFO_ERR	    mBIT(15)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_SHADOW_ERR	    mBIT(16)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ARB_REQ_SHADOW_ERR	    mBIT(17)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ARB_CTL_SHADOW_ERR	    mBIT(18)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SCC_SHADOW_ERR	    mBIT(19)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SSM_SHADOW_ERR	    mBIT(20)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SSM_SYNC_SHADOW_ERR	    mBIT(21)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ECI_ARB_SHADOW_ERR	    mBIT(22)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ECI_SYNC_SHADOW_ERR	    mBIT(23)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ECI_EPE_SHADOW_ERR	    mBIT(24)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_SHADOW_ERR	    mBIT(25)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PSM_SHADOW_ERR	    mBIT(26)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PRC_SHADOW_ERR	    mBIT(27)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_BDM_SHADOW_ERR	    mBIT(28)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_SHADOW_ERR	    mBIT(29)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_CPIF_SHADOW_ERR	    mBIT(30)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SCC_CLM_ERR		    mBIT(32)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_SCC_RMM_FSM_ERR	    mBIT(33)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_ECI_EPE_FSM_ERR	    mBIT(34)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_PBLESIZE0_ERR    mBIT(35)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_QUOTIENT_ERR	    mBIT(36)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PRC_FSM_ERR	    mBIT(37)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_BDM_FSM_ERR		    mBIT(38)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_BDM_WRAP_ERR		    mBIT(39)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_BUFFER_ERR	    mBIT(40)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_FSM_ERR	    mBIT(41)
+#define	VXGE_HAL_GSTC_ERR1_REG_STC_UNK_CP_MSG_TYPE	    mBIT(42)
+/* 0x08030 */	u64	gstc_err1_mask;
+/* 0x08038 */	u64	gstc_err1_alarm;
+/* 0x08040 */	u64	gh2l_err0_reg;
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_DB_ERR(val)	    vBIT(val, 0, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_DB_ERR(val)	    vBIT(val, 2, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_DB_ERR(val)	    vBIT(val, 4, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_DB_ERR(val)	    vBIT(val, 6, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_RD_RSP_DB_ERR	    mBIT(8)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_DB_ERR(val)	    vBIT(val, 9, 4)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_DB_ERR(val)	    vBIT(val, 13, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PA_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PB_DB_ERR	    mBIT(16)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_SG_ERR(val)	    vBIT(val, 32, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_SG_ERR(val)	    vBIT(val, 34, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_SG_ERR(val)	    vBIT(val, 36, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_SG_ERR(val)	    vBIT(val, 38, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_SG_ERR(val)	    vBIT(val, 41, 4)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_SG_ERR(val)	    vBIT(val, 45, 2)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PA_SG_ERR	    mBIT(47)
+#define	VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PB_SG_ERR	    mBIT(48)
+/* 0x08048 */	u64	gh2l_err0_mask;
+/* 0x08050 */	u64	gh2l_err0_alarm;
+/* 0x08058 */	u64	ghsq_err_reg;
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_WR_COMP_OFLOW_ERR	    mBIT(0)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_WR_COMP_UFLOW_ERR	    mBIT(1)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_CTL_OFLOW_ERR	    mBIT(2)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_CTL_UFLOW_ERR	    mBIT(3)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_OFLOW_ERR		    mBIT(4)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_UFLOW_ERR		    mBIT(5)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_WR_DAT224_BB_OFLOW_ERR    mBIT(6)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_WR_DAT224_BB_UFLOW_ERR    mBIT(7)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_WR_REQ_OFLOW_ERR	    mBIT(8)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_WR_REQ_UFLOW_ERR	    mBIT(9)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_WRDBL_OFLOW_ERR	    mBIT(10)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_WRDBL_UFLOW_ERR	    mBIT(11)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_HOC_XFER_DATX_UFLOW_ERR   mBIT(12)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_HOC_XFER_CTLX_UFLOW_ERR   mBIT(13)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_RSP_OFLOW_ERR	    mBIT(14)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_RSP_UFLOW_ERR	    mBIT(15)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_TRANS_POPCRDCNT_OFLOW_ERR mBIT(16)
+#define	VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_TRANS_POPCRDCNT_UFLOW_ERR mBIT(17)
+/* 0x08060 */	u64	ghsq_err_mask;
+/* 0x08068 */	u64	ghsq_err_alarm;
+/* 0x08070 */	u64	ghsq_err2_reg;
+#define	VXGE_HAL_GHSQ_ERR2_REG_H2L_OFLOW_ERR(n)		    mBIT(n)
+#define	VXGE_HAL_GHSQ_ERR2_REG_H2L_UFLOW_ERR(n)		    mBIT(n)
+/* 0x08078 */	u64	ghsq_err2_mask;
+/* 0x08080 */	u64	ghsq_err2_alarm;
+/* 0x08088 */	u64	ghsq_err3_reg;
+#define	VXGE_HAL_GHSQ_ERR3_REG_H2L_OFLOW_ERR(n)		    mBIT(n)
+#define	VXGE_HAL_GHSQ_ERR3_REG_H2L_UFLOW_ERR(n)		    mBIT(n)
+/* 0x08090 */	u64	ghsq_err3_mask;
+/* 0x08098 */	u64	ghsq_err3_alarm;
+/* 0x080a0 */	u64	gh2l_smerr0_reg;
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_HOPIF_SM_ERR	    mBIT(0)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_NR_SM_ERR	    mBIT(1)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_HOF_SM_ERR	    mBIT(2)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_ROP_SM_ERR	    mBIT(3)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_OADE_SM_ERR	    mBIT(4)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_ODOG_SM_ERR	    mBIT(5)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR0 mBIT(6)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR1 mBIT(7)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR2 mBIT(8)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR3 mBIT(9)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR0    mBIT(10)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR1    mBIT(11)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR2    mBIT(12)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR3    mBIT(13)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR0 mBIT(14)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR1 mBIT(15)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR2 mBIT(16)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR3 mBIT(17)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR0  mBIT(18)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR1  mBIT(19)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR2  mBIT(20)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR3  mBIT(21)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR0	    mBIT(22)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR1	    mBIT(23)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR2	    mBIT(24)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR3	    mBIT(25)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_STAG_KILL_SM_ERROR mBIT(26)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_IMP_SM_ERROR  mBIT(27)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_OMP_SM_ERROR  mBIT(28)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_RECALL_SM_ERROR mBIT(29)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_LOG_CCTL_FIFO_ERR	    mBIT(30)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_RETXK_CCTL_FIFO_ERR    mBIT(31)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HCC_HANDSHAKE_ERR  mBIT(32)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_ARB_HANDSHAKE_ERR  mBIT(33)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_RETXK_HANDSHAKE_ERR mBIT(34)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_OAE_HANDSHAKE_ERR  mBIT(35)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_VPATH_ERR	    mBIT(36)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HO_SIZE_ERR	    mBIT(37)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HO_PARSE_ERR	    mBIT(38)
+#define	VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_ARB_SM_ERR	    mBIT(39)
+/* 0x080a8 */	u64	gh2l_smerr0_mask;
+/* 0x080b0 */	u64	gh2l_smerr0_alarm;
+/* 0x080b8 */	u64	hcc_alarm_reg;
+#define	VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_SG_ERR(val)    vBIT(val, 0, 4)
+#define	VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_DB_ERR(val)    vBIT(val, 4, 4)
+#define	VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_SG_ERR(val)    vBIT(val, 8, 4)
+#define	VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_DB_ERR(val)    vBIT(val, 12, 4)
+#define	VXGE_HAL_HCC_ALARM_REG_H2L_CWBC_FSM_ERR		    mBIT(19)
+#define	VXGE_HAL_HCC_ALARM_REG_H2L_RCC_FSM_ERR		    mBIT(23)
+/* 0x080c0 */	u64	hcc_alarm_mask;
+/* 0x080c8 */	u64	hcc_alarm_alarm;
+/* 0x080d0 */	u64	gstc_cfg0;
+#define	VXGE_HAL_GSTC_CFG0_RPE_PF_ENA			    mBIT(7)
+#define	VXGE_HAL_GSTC_CFG0_SCC_MODE			    mBIT(15)
+#define	VXGE_HAL_GSTC_CFG0_SCC_NBR_FREE_SLOTS(val)	    vBIT(val, 18, 6)
+#define	VXGE_HAL_GSTC_CFG0_STC_LEFT_HASH_INDEX(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_GSTC_CFG0_STC_RIGHT_HASH_INDEX(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_GSTC_CFG0_INCL_ECI_FIFOS_PBL_SYNC	    mBIT(47)
+#define	VXGE_HAL_GSTC_CFG0_MW_LOCAL_ACCESS_ENA		    mBIT(55)
+#define	VXGE_HAL_GSTC_CFG0_LD_FW_CTRL_FIELDS		    mBIT(62)
+#define	VXGE_HAL_GSTC_CFG0_ONLY_ROW0_DUSE1_WRITABLE	    mBIT(63)
+/* 0x080d8 */	u64	gstc_cfg1;
+#define	VXGE_HAL_GSTC_CFG1_INDIRECT_MODE(val)		    vBIT(val, 0, 17)
+#define	VXGE_HAL_GSTC_CFG1_RPE_PF_COUNTDOWN(val)	    vBIT(val, 36, 12)
+#define	VXGE_HAL_GSTC_CFG1_BDM_RATE_CTRL(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_GSTC_CFG1_BDM_EXTRA_RPE_PRM_RD		    mBIT(63)
+/* 0x080e0 */	u64	gstc_cfg2;
+#define	VXGE_HAL_GSTC_CFG2_MAX_FRE_CMREQ_ENTRIES(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_WIRE_INV	    mBIT(12)
+#define	VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_INV		    mBIT(13)
+#define	VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_DEALLOC	    mBIT(14)
+#define	VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_SUSP		    mBIT(15)
+#define	VXGE_HAL_GSTC_CFG2_BDM_CACHE_ECC_ENABLE_N	    mBIT(16)
+#define	VXGE_HAL_GSTC_CFG2_BDM_CMRSP_ECC_ENABLE_N	    mBIT(17)
+#define	VXGE_HAL_GSTC_CFG2_ECI_CACHE0_ECC_ENABLE_N	    mBIT(18)
+#define	VXGE_HAL_GSTC_CFG2_ECI_CACHE1_ECC_ENABLE_N	    mBIT(19)
+#define	VXGE_HAL_GSTC_CFG2_H2L_EVENT_ECC_ENABLE_N	    mBIT(20)
+#define	VXGE_HAL_GSTC_CFG2_PRM_EVENT_ECC_ENABLE_N	    mBIT(21)
+#define	VXGE_HAL_GSTC_CFG2_SRCH_MEM_ECC_ENABLE_N	    mBIT(22)
+#define	VXGE_HAL_GSTC_CFG2_GPSYNC_WAIT_TOKEN_ENABLE	    mBIT(29)
+#define	VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_TIMER_ENABLE	    mBIT(30)
+#define	VXGE_HAL_GSTC_CFG2_GPSYNC_SRC_NOTIFY_ENABLE	    mBIT(31)
+#define	VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_START_VALUE(val)  vBIT(val, 36, 4)
+/* 0x080e8 */	u64	stc_arb_cfg0;
+#define	VXGE_HAL_STC_ARB_CFG0_RPE_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_H2L_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_CP_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_CAL0_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_CAL1_PRI(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_CAL2_PRI(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_CAL3_PRI(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_STC_ARB_CFG0_CAL4_PRI(val)		    vBIT(val, 62, 2)
+/* 0x080f0 */	u64	stc_arb_cfg1;
+#define	VXGE_HAL_STC_ARB_CFG1_CAL5_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_ARB_CFG1_CAL6_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_ARB_CFG1_CAL7_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_ARB_CFG1_CAL8_PRI(val)		    vBIT(val, 30, 2)
+/* 0x080f8 */	u64	stc_arb_cfg2;
+#define	VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L0_EVENTS(val)	    vBIT(val, 4, 4)
+#define	VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L1_EVENTS(val)	    vBIT(val, 12, 4)
+#define	VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L2_EVENTS(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L3_EVENTS(val)	    vBIT(val, 28, 4)
+#define	VXGE_HAL_STC_ARB_CFG2_MAX_NBR_RPE_EVENTS(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_STC_ARB_CFG2_MAX_NBR_MR_EVENTS(val)	    vBIT(val, 45, 3)
+/* 0x08100 */	u64	stc_arb_cfg3;
+#define	VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L0_FETCHES(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L1_FETCHES(val)	    vBIT(val, 13, 3)
+#define	VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L2_FETCHES(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L3_FETCHES(val)	    vBIT(val, 29, 3)
+#define	VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_FETCHES(val)	    vBIT(val, 37, 3)
+#define	VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_PF_FETCHES(val)   vBIT(val, 46, 2)
+/* 0x08108 */	u64	stc_jhash_cfg;
+#define	VXGE_HAL_STC_JHASH_CFG_GOLDEN(val)		    vBIT(val, 0, 32)
+#define	VXGE_HAL_STC_JHASH_CFG_INIT_VAL(val)		    vBIT(val, 32, 32)
+/* 0x08110 */	u64	stc_smi_arb_cfg0;
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_RPE_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_H2L_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_CP_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_CAL0_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_CAL1_PRI(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_CAL2_PRI(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_CAL3_PRI(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG0_CAL4_PRI(val)		    vBIT(val, 62, 2)
+/* 0x08118 */	u64	stc_smi_arb_cfg1;
+#define	VXGE_HAL_STC_SMI_ARB_CFG1_CAL5_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG1_CAL6_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG1_CAL7_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG1_CAL8_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG1_CAL9_PRI(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_STC_SMI_ARB_CFG1_SAME_PRI_B2B_CAL	    mBIT(48)
+/* 0x08120 */	u64	stc_caa_arb_cfg0;
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_RPE_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_H2L_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_CP_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_CAL0_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_CAL1_PRI(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_CAL2_PRI(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_CAL3_PRI(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG0_CAL4_PRI(val)		    vBIT(val, 62, 2)
+/* 0x08128 */	u64	stc_caa_arb_cfg1;
+#define	VXGE_HAL_STC_CAA_ARB_CFG1_CAL5_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG1_CAL6_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG1_CAL7_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG1_CAL8_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_STC_CAA_ARB_CFG1_SAME_PRI_B2B_CAL	    mBIT(39)
+/* 0x08130 */	u64	stc_eci_arb_cfg0;
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_RPE_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_H2L_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_CP_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_CAL0_PRI(val)		    vBIT(val, 30, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_CAL1_PRI(val)		    vBIT(val, 38, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_CAL2_PRI(val)		    vBIT(val, 46, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_CAL3_PRI(val)		    vBIT(val, 54, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG0_CAL4_PRI(val)		    vBIT(val, 62, 2)
+/* 0x08138 */	u64	stc_eci_arb_cfg1;
+#define	VXGE_HAL_STC_ECI_ARB_CFG1_CAL5_PRI(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG1_CAL6_PRI(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG1_CAL7_PRI(val)		    vBIT(val, 22, 2)
+#define	VXGE_HAL_STC_ECI_ARB_CFG1_CAL8_PRI(val)		    vBIT(val, 30, 2)
+/* 0x08140 */	u64	stc_eci_cfg0;
+#define	VXGE_HAL_STC_ECI_CFG0_SUSPEND_DEALLOC_STAGS_ENA	    mBIT(4)
+#define	VXGE_HAL_STC_ECI_CFG0_MULT_SUSPEND_ERR_ENA	    mBIT(5)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSPEND_PDID_CHECK_ENA	    mBIT(6)
+#define	VXGE_HAL_STC_ECI_CFG0_UNSUSPEND_PDID_CHECK_ENA	    mBIT(7)
+#define	VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_KEY_CHECK_ENA   mBIT(14)
+#define	VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_PDID_CHECK_ENA  mBIT(15)
+#define	VXGE_HAL_STC_ECI_CFG0_SET_SHARED_KEY_CHECK_ENA	    mBIT(23)
+#define	VXGE_HAL_STC_ECI_CFG0_STAG_WR_FAIL_IF_DEALLOC	    mBIT(31)
+#define	VXGE_HAL_STC_ECI_CFG0_PLACEMENT_MR_DEFERRAL_ENA	    mBIT(34)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSPEND_MR_DEFERRAL_ENA	    mBIT(35)
+#define	VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_MR_DEFERRAL_ENA mBIT(36)
+#define	VXGE_HAL_STC_ECI_CFG0_BIND_MW_MR_DEFERRAL_ENA	    mBIT(37)
+#define	VXGE_HAL_STC_ECI_CFG0_SET_SHARED_MR_DEFERRAL_ENA    mBIT(38)
+#define	VXGE_HAL_STC_ECI_CFG0_STAG_WR_MR_DEFERRAL_ENA	    mBIT(39)
+#define	VXGE_HAL_STC_ECI_CFG0_RESUBMIT_INTERVAL(val)	    vBIT(val, 40, 8)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_PLACE_STALL_ENA	    mBIT(54)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_WIRE_INV_STALL_ENA  mBIT(55)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_WIRE_INV_ENA	    mBIT(56)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_CP_INV_ENA	    mBIT(57)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_MR_EVENT_ENA	    mBIT(58)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_DEALLOC_ENA	    mBIT(59)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_ALTER_NUM_MWS_ENA   mBIT(60)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_BIND_MW_ENA	    mBIT(61)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_SET_SHARED_ENA	    mBIT(62)
+#define	VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_STAG_WR_ENA	    mBIT(63)
+/* 0x08148 */	u64	stc_prm_cfg0;
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_RPE_PRI		    mBIT(6)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_H2L_PRI		    mBIT(7)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL0_PRI		    mBIT(8)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL1_PRI		    mBIT(9)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL2_PRI		    mBIT(10)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL3_PRI		    mBIT(11)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL4_PRI		    mBIT(12)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL5_PRI		    mBIT(13)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL6_PRI		    mBIT(14)
+#define	VXGE_HAL_STC_PRM_CFG0_PAC_CAL7_PRI		    mBIT(15)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_RPE_PRI		    mBIT(22)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_H2L_PRI		    mBIT(23)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL0_PRI		    mBIT(24)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL1_PRI		    mBIT(25)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL2_PRI		    mBIT(26)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL3_PRI		    mBIT(27)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL4_PRI		    mBIT(28)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL5_PRI		    mBIT(29)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL6_PRI		    mBIT(30)
+#define	VXGE_HAL_STC_PRM_CFG0_PRC_CAL7_PRI		    mBIT(31)
+#define	VXGE_HAL_STC_PRM_CFG0_RDUSE_ENA			    mBIT(39)
+/* 0x08150 */	u64	h2l_misc_cfg;
+#define	VXGE_HAL_H2L_MISC_CFG_HSQ_FORCE_CMP		    mBIT(0)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_IPID_MSB		    mBIT(1)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_ARB_ENABLE		    mBIT(2)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_HSN		    mBIT(3)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_RD_XON	    mBIT(4)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_PDA_VPBP	    mBIT(5)
+#define	VXGE_HAL_H2L_MISC_CFG_OAE_VPBP_CHECK_ENA	    mBIT(6)
+#define	VXGE_HAL_H2L_MISC_CFG_OAE_XON_CHECK_ENA		    mBIT(7)
+#define	VXGE_HAL_H2L_MISC_CFG_HOCHEAD_RD_THRES(val)	    vBIT(val, 10, 6)
+#define	VXGE_HAL_H2L_MISC_CFG_HCC_WB_THRESHOLD(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_MODE(val)	    vBIT(val, 25, 2)
+#define	VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_VPATH(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_H2L_MISC_CFG_HOC_DATX_ECC_ENABLE_N	    mBIT(35)
+#define	VXGE_HAL_H2L_MISC_CFG_WRDBL_ECC_ENABLE_N	    mBIT(36)
+#define	VXGE_HAL_H2L_MISC_CFG_WRBUF_ECC_ENABLE_N	    mBIT(37)
+#define	VXGE_HAL_H2L_MISC_CFG_CMCRSP_ECC_ENABLE_N	    mBIT(38)
+#define	VXGE_HAL_H2L_MISC_CFG_HOC_HEAD_ECC_ENABLE_N	    mBIT(39)
+#define	VXGE_HAL_H2L_MISC_CFG_OD_MEM_ECC_ENABLE_N	    mBIT(40)
+#define	VXGE_HAL_H2L_MISC_CFG_RW_CACHE_ECC_ENABLE_N	    mBIT(41)
+/* 0x08158 */	u64	hsq_cfg[17];
+#define	VXGE_HAL_HSQ_CFG_BASE_ADDR(val)			    vBIT(val, 8, 24)
+#define	VXGE_HAL_HSQ_CFG_SIZE224(val)			    vBIT(val, 40, 24)
+/* 0x081e0 */	u64	usdc_vpbp_cfg;
+#define	VXGE_HAL_USDC_VPBP_CFG_THRES224(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_USDC_VPBP_CFG_HYST224(val)		    vBIT(val, 40, 24)
+/* 0x081e8 */	u64	kdfc_vpbp_cfg;
+#define	VXGE_HAL_KDFC_VPBP_CFG_THRES224(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_KDFC_VPBP_CFG_HYST224(val)		    vBIT(val, 40, 24)
+/* 0x081f0 */	u64	txpe_vpbp_cfg;
+#define	VXGE_HAL_TXPE_VPBP_CFG_THRES224(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_TXPE_VPBP_CFG_HYST224(val)		    vBIT(val, 40, 24)
+/* 0x081f8 */	u64	one_vpbp_cfg;
+#define	VXGE_HAL_ONE_VPBP_CFG_THRES224(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_ONE_VPBP_CFG_HYST224(val)		    vBIT(val, 40, 24)
+/* 0x08200 */	u64	hoparb_wrr_ctrl_0;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_0_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_1_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_2_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_3_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_4_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_5_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_6_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_0_SS_7_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08208 */	u64	hoparb_wrr_ctrl_1;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_8_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_9_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_10_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_11_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_12_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_13_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_14_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_1_SS_15_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08210 */	u64	hoparb_wrr_ctrl_2;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_16_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_17_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_18_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_19_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_20_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_21_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_22_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_2_SS_23_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08218 */	u64	hoparb_wrr_ctrl_3;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_24_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_25_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_26_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_27_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_28_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_29_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_30_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_3_SS_31_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08220 */	u64	hoparb_wrr_ctrl_4;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_32_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_33_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_34_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_35_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_36_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_37_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_38_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_4_SS_39_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08228 */	u64	hoparb_wrr_ctrl_5;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_40_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_41_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_42_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_43_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_44_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_45_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_46_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_5_SS_47_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08230 */	u64	hoparb_wrr_ctrl_6;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_48_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_49_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_50_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_51_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_52_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_53_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_54_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_6_SS_55_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08238 */	u64	hoparb_wrr_ctrl_7;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_56_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_57_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_58_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_59_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_60_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_61_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_62_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_7_SS_63_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08240 */	u64	hoparb_wrr_ctrl_8;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_64_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_65_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_66_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_67_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_68_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_69_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_70_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_8_SS_71_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08248 */	u64	hoparb_wrr_ctrl_9;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_72_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_73_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_74_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_75_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_76_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_77_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_78_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_9_SS_79_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08250 */	u64	hoparb_wrr_ctrl_10;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_80_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_81_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_82_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_83_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_84_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_85_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_86_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_10_SS_87_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08258 */	u64	hoparb_wrr_ctrl_11;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_88_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_89_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_90_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_91_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_92_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_93_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_94_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_11_SS_95_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08260 */	u64	hoparb_wrr_ctrl_12;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_96_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_97_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_98_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_99_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_100_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_101_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_102_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_12_SS_103_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08268 */	u64	hoparb_wrr_ctrl_13;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_104_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_105_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_106_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_107_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_108_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_109_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_110_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_13_SS_111_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08270 */	u64	hoparb_wrr_ctrl_14;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_112_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_113_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_114_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_115_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_116_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_117_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_118_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_14_SS_119_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08278 */	u64	hoparb_wrr_ctrl_15;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_120_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_121_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_122_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_123_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_124_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_125_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_126_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_15_SS_127_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08280 */	u64	hoparb_wrr_ctrl_16;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_128_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_129_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_130_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_131_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_132_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_133_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_134_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_16_SS_135_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08288 */	u64	hoparb_wrr_ctrl_17;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_136_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_137_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_138_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_139_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_140_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_141_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_142_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_17_SS_143_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08290 */	u64	hoparb_wrr_ctrl_18;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_144_NUM(val)	    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_145_NUM(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_146_NUM(val)	    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_147_NUM(val)	    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_148_NUM(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_149_NUM(val)	    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_150_NUM(val)	    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CTRL_18_SS_151_NUM(val)	    vBIT(val, 59, 5)
+/* 0x08298 */	u64	hoparb_wrr_ctrl_19;
+#define	VXGE_HAL_HOPARB_WRR_CTRL_19_SS_152_NUM(val)	    vBIT(val, 3, 5)
+/* 0x082a0 */	u64	hoparb_wrr_cmp_0;
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP0_NUM(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP1_NUM(val)		    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP2_NUM(val)		    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP3_NUM(val)		    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP4_NUM(val)		    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP5_NUM(val)		    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP6_NUM(val)		    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_0_VP7_NUM(val)		    vBIT(val, 59, 5)
+/* 0x082a8 */	u64	hoparb_wrr_cmp_1;
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP8_NUM(val)		    vBIT(val, 3, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP9_NUM(val)		    vBIT(val, 11, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP10_NUM(val)		    vBIT(val, 19, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP11_NUM(val)		    vBIT(val, 27, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP12_NUM(val)		    vBIT(val, 35, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP13_NUM(val)		    vBIT(val, 43, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP14_NUM(val)		    vBIT(val, 51, 5)
+#define	VXGE_HAL_HOPARB_WRR_CMP_1_VP15_NUM(val)		    vBIT(val, 59, 5)
+/* 0x082b0 */	u64	hoparb_wrr_cmp_2;
+#define	VXGE_HAL_HOPARB_WRR_CMP_2_VP16_NUM(val)		    vBIT(val, 3, 5)
+	u8	unused082e8[0x082e8 - 0x082b8];
+
+/* 0x082e8 */	u64	hop_bck_stats0;
+#define	VXGE_HAL_HOP_BCK_STATS0_HO_DISPATCH_CNT(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_HOP_BCK_STATS0_HO_DROP_CNT(val)	    vBIT(val, 32, 32)
+	u8	unused08400[0x08400 - 0x082f0];
+
+/* 0x08400 */	u64	pcmg3_int_status;
+#define	VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT	    mBIT(0)
+#define	VXGE_HAL_PCMG3_INT_STATUS_PSTC_ERR_PSTC_INT	    mBIT(1)
+#define	VXGE_HAL_PCMG3_INT_STATUS_PH2L_ERR0_PH2L_INT	    mBIT(2)
+/* 0x08408 */	u64	pcmg3_int_mask;
+/* 0x08410 */	u64	dam_err_reg;
+#define	VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_SG_ERR	    mBIT(0)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_SG_ERR	    mBIT(1)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_SG_ERR	    mBIT(3)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_SG_ERR	    mBIT(4)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_SG_ERR	    mBIT(5)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR	    mBIT(32)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_DB_ERR	    mBIT(33)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_DB_ERR	    mBIT(34)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_DB_ERR	    mBIT(35)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_DB_ERR	    mBIT(36)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_HPRD_ERR		    mBIT(40)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_LPRD_0_ERR		    mBIT(41)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_LPRD_1_ERR		    mBIT(42)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_OVERFLOW_ERR	    mBIT(48)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_OVERFLOW_ERR	    mBIT(49)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_OVERFLOW_ERR	    mBIT(50)
+#define	VXGE_HAL_DAM_ERR_REG_DAM_SM_ERR			    mBIT(56)
+/* 0x08418 */	u64	dam_err_mask;
+/* 0x08420 */	u64	dam_err_alarm;
+/* 0x08428 */	u64	pstc_err_reg;
+#define	VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_REQ_FIFO_ERR	    mBIT(0)
+#define	VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_ECRESP_FIFO_ERR	    mBIT(1)
+#define	VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_BUFFRESP_FIFO_ERR   mBIT(2)
+#define	VXGE_HAL_PSTC_ERR_REG_STC_ARB_RPE_FIFO_ERR	    mBIT(3)
+#define	VXGE_HAL_PSTC_ERR_REG_STC_CP2STC_FIFO_ERR	    mBIT(4)
+/* 0x08430 */	u64	pstc_err_mask;
+/* 0x08438 */	u64	pstc_err_alarm;
+/* 0x08440 */	u64	ph2l_err0_reg;
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_DATX_OFLOW_ERR  mBIT(0)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_CTLX_OFLOW_ERR  mBIT(1)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_PARSE_ERR	    mBIT(2)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_TCPOP_BYTES_ERR mBIT(3)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_IDATA_BYTES_ERR mBIT(4)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_PLDTYPE_ERR	    mBIT(5)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_OD_ODLIST_LEN_ERR mBIT(6)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_VPATH_ERR	    mBIT(7)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_DB_ERR(val)	    vBIT(val, 8, 2)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_DB_ERR(val)    vBIT(val, 10, 2)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_DB_ERR(val)	    vBIT(val, 12, 3)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TBL_DB_ERR	    mBIT(15)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_FIFO_ERR	    mBIT(16)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_CCTL_FIFO_ERR	    mBIT(17)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_FIFO_ERR	    mBIT(18)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_CRED_CNT_ERR	    mBIT(19)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PDI_CRED_CNT_ERR	    mBIT(20)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PCTL_SHADOW_ERR	    mBIT(21)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_OPC_SHADOW_ERR	    mBIT(22)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_SHADOW_ERR	    mBIT(23)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PDI_SHADOW_ERR	    mBIT(24)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_LCTL_SHADOW_ERR    mBIT(26)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TXI_SHADOW_ERR	    mBIT(27)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_RXI_SHADOW_ERR	    mBIT(28)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_HPI_SHADOW_ERR	    mBIT(29)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_SHADOW_ERR    mBIT(30)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PCTL_FSM_ERR	    mBIT(31)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_FSM_ERR	    mBIT(32)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_LO_COMPL_ERR	    mBIT(33)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_LCTL_FSM_ERR	    mBIT(34)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TXI_FSM_ERR	    mBIT(35)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_SLOT_MGMT_ERR	    mBIT(36)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_HPI_FSM_ERR	    mBIT(37)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_FSM_ERR	    mBIT(38)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_ROCRC_HOP_OFLOW_ERR	    mBIT(39)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_PDA_H2L_DONE_FIFO_OVERFLOW mBIT(40)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_SG_ERR(val)	    vBIT(val, 48, 2)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_SG_ERR(val)    vBIT(val, 50, 2)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_SG_ERR(val)	    vBIT(val, 52, 3)
+#define	VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TBL_SG_ERR	    mBIT(55)
+/* 0x08448 */	u64	ph2l_err0_mask;
+/* 0x08450 */	u64	ph2l_err0_alarm;
+/* 0x08458 */	u64	dam_bypass_queue_0;
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_0_ENABLE		    mBIT(0)
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_0_BASE(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_0_LENGTH(val)		    vBIT(val, 40, 24)
+/* 0x08460 */	u64	dam_bypass_queue_1;
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_1_BASE(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_1_LENGTH(val)		    vBIT(val, 40, 24)
+/* 0x08468 */	u64	dam_bypass_queue_2;
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_2_BASE(val)		    vBIT(val, 8, 24)
+#define	VXGE_HAL_DAM_BYPASS_QUEUE_2_LENGTH(val)		    vBIT(val, 40, 24)
+/* 0x08470 */	u64	dam_ecc_ctrl;
+#define	VXGE_HAL_DAM_ECC_CTRL_DISABLE			    mBIT(0)
+/* 0x08478 */	u64	ph2l_cfg0;
+#define	VXGE_HAL_PH2L_CFG0_PHDR_MEM_ECC_ENABLE_N	    mBIT(15)
+#define	VXGE_HAL_PH2L_CFG0_IDATA_MEM_ECC_ENABLE_N	    mBIT(23)
+#define	VXGE_HAL_PH2L_CFG0_RO_CACHE_ECC_ENABLE_N	    mBIT(31)
+#define	VXGE_HAL_PH2L_CFG0_RETXK_TBL_ECC_ENABLE_N	    mBIT(39)
+#define	VXGE_HAL_PH2L_CFG0_LOG_XON_CHECK_ENA		    mBIT(47)
+#define	VXGE_HAL_PH2L_CFG0_LOG_VPBP_CHECK_ENA		    mBIT(55)
+#define	VXGE_HAL_PH2L_CFG0_NBR_RETX_SLOTS_PER_VP(val)	    vBIT(val, 62, 2)
+/* 0x08480 */	u64	pstc_cfg0;
+#define	VXGE_HAL_PSTC_CFG0_PGSYNC_WAIT_TOKEN_ENABLE	    mBIT(5)
+#define	VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_TIMER_ENABLE	    mBIT(6)
+#define	VXGE_HAL_PSTC_CFG0_PGSYNC_SRC_NOTIFY_ENABLE	    mBIT(7)
+#define	VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_START_VALUE(val)  vBIT(val, 12, 4)
+	u8	unused08510[0x08510 - 0x08488];
+
+/* 0x08510 */	u64	neterion_membist_control;
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG1	    mBIT(0)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG2	    mBIT(1)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG3	    mBIT(2)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_DRBELL	    mBIT(3)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_FBIF	    mBIT(4)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_MSG	    mBIT(5)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_ONE	    mBIT(6)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_PCI	    mBIT(7)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_RTDMA	    mBIT(8)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_WRDMA	    mBIT(9)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_XGMAC	    mBIT(10)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_FB	    mBIT(11)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CM	    mBIT(12)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_OVERRIDE_FB_DONE  mBIT(16)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_OVERRIDE_CM_DONE  mBIT(17)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_INCLUDE_PCIE_MEMS mBIT(24)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_LAUNCH	    mBIT(31)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_DONE	    mBIT(48)
+#define	VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_ERROR(val)   vBIT(val, 56, 4)
+/* 0x08518 */	u64	neterion_membist_errors;
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG1(val)	    vBIT(val, 0, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG2(val)	    vBIT(val, 3, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG3(val)	    vBIT(val, 6, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_DRBELL(val)   vBIT(val, 9, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_FBif (val)    vBIT(val, 12, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_MSG(val)	    vBIT(val, 15, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_ONE(val)	    vBIT(val, 18, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_PCI(val)	    vBIT(val, 21, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_RTDMA(val)    vBIT(val, 24, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_WRDMA(val)    vBIT(val, 27, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_XGMAC(val)    vBIT(val, 30, 3)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_FB	    mBIT(33)
+#define	VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CM	    mBIT(34)
+/* 0x08520 */	u64	rr_cqm_cache_rtl_top_0;
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08528 */	u64	rr_cqm_cache_rtl_top_1;
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08530 */	u64	rr_sqm_cache_rtl_top_0;
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08538 */	u64	rr_sqm_cache_rtl_top_1;
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08540 */	u64	rf_sqm_lprpedat_rtl_top_0;
+#define	VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08548 */	u64	rf_sqm_lprpedat_rtl_top_1;
+#define	VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08550 */	u64	rr_sqm_dmawqersp_rtl_top_0;
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x08558 */	u64	rr_sqm_dmawqersp_rtl_top_1;
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x08560 */	u64	rf_cqm_dmacqersp_rtl_top;
+#define	VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08568 */	u64	rf_sqm_rpereqdat_rtl_top_0;
+#define	VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08570 */	u64	rf_sqm_rpereqdat_rtl_top_1;
+#define	VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08578 */	u64	rf_sscc_ssr_rtl_top_0_0;
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08580 */	u64	rf_sscc_ssr_rtl_top_1_0;
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08588 */	u64	rf_sscc_ssr_rtl_top_0_1;
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08590 */	u64	rf_sscc_ssr_rtl_top_1_1;
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08598 */	u64	rf_ssc_cm_resp_rtl_top_1_ssc0;
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085a0 */	u64	rf_ssc_cm_resp_rtl_top_0_ssc1;
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085a8 */	u64	rf_ssc_cm_resp_rtl_top_1_sscl;
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085b0 */	u64	rf_ssc_cm_resp_rtl_top_0_ssc0;
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085b8 */	u64	rf_ssc_cm_resp_rtl_top_1_ssc1;
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085c0 */	u64	rf_ssc_cm_resp_rtl_top_0_sscl;
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085c8 */	u64	rf_ssc_ssr_resp_rtl_top_ssc0;
+#define	VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085d0 */	u64	rf_ssc_ssr_resp_rtl_top_ssc1;
+#define	VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085d8 */	u64	rf_ssc_ssr_resp_rtl_top_sscl;
+#define	VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085e0 */	u64	rf_ssc_tsr_resp_rtl_top_1_ssc0;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085e8 */	u64	rf_ssc_tsr_resp_rtl_top_2_ssc0;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085f0 */	u64	rf_ssc_tsr_resp_rtl_top_2_ssc1;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x085f8 */	u64	rf_ssc_tsr_resp_rtl_top_0_sscl;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08600 */	u64	rf_ssc_tsr_resp_rtl_top_0_ssc0;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08608 */	u64	rf_ssc_tsr_resp_rtl_top_0_ssc1;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08610 */	u64	rf_ssc_tsr_resp_rtl_top_1_ssc1;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08618 */	u64	rf_ssc_tsr_resp_rtl_top_1_sscl;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08620 */	u64	rf_ssc_tsr_resp_rtl_top_2_sscl;
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08628 */	u64	rf_ssc_state_rtl_top_1_ssc0;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08630 */	u64	rf_ssc_state_rtl_top_2_ssc0;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08638 */	u64	rf_ssc_state_rtl_top_1_ssc1;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08640 */	u64	rf_ssc_state_rtl_top_2_ssc1;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08648 */	u64	rf_ssc_state_rtl_top_1_sscl;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08650 */	u64	rf_ssc_state_rtl_top_2_sscl;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08658 */	u64	rf_ssc_state_rtl_top_0_ssc0;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08660 */	u64	rf_ssc_state_rtl_top_3_ssc0;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08668 */	u64	rf_ssc_state_rtl_top_0_ssc1;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08670 */	u64	rf_ssc_state_rtl_top_3_ssc1;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08678 */	u64	rf_ssc_state_rtl_top_0_sscl;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08680 */	u64	rf_ssc_state_rtl_top_3_sscl;
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08688 */	u64	rf_sscc_tsr_rtl_top_0;
+#define	VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08690 */	u64	rf_sscc_tsr_rtl_top_1;
+#define	VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08698 */	u64	rf_sscc_tsr_rtl_top_2;
+#define	VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086a0 */	u64	rf_uqm_cmcreq_rtl_top;
+#define	VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086a8 */	u64	rr0_g3if_cm_ctrl_rtl_top;
+#define	VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086b0 */	u64	rr1_g3if_cm_ctrl_rtl_top;
+#define	VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086b8 */	u64	rr2_g3if_cm_ctrl_rtl_top;
+#define	VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086c0 */	u64	rf_g3if_cm_rd_rtl_top0;
+#define	VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086c8 */	u64	rf_g3if_cm_rd_rtl_top1;
+#define	VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086d0 */	u64	rf_g3if_cm_rd_rtl_top2;
+#define	VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x086d8 */	u64	rf_cmg_msg2cmg_rtl_top_0_0;
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x086e0 */	u64	rf_cmg_msg2cmg_rtl_top_1_0;
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x086e8 */	u64	rf_cmg_msg2cmg_rtl_top_0_1;
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x086f0 */	u64	rf_cmg_msg2cmg_rtl_top_1_1;
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x086f8 */	u64	rf_cp_dma_resp_rtl_top_0;
+#define	VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08700 */	u64	rf_cp_dma_resp_rtl_top_1;
+#define	VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08708 */	u64	rf_cp_dma_resp_rtl_top_2;
+#define	VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08710 */	u64	rf_cp_qcc2cxp_rtl_top;
+#define	VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08718 */	u64	rf_cp_stc2cp_rtl_top;
+#define	VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08720 */	u64	rf_cp_xt_trace_rtl_top;
+#define	VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08728 */	u64	rf_cp_xt_dtag_rtl_top;
+#define	VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08730 */	u64	rf_cp_xt_icache_rtl_top_0_0;
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08738 */	u64	rf_cp_xt_icache_rtl_top_1_0;
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08740 */	u64	rf_cp_xt_icache_rtl_top_0_1;
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08748 */	u64	rf_cp_xt_icache_rtl_top_1_1;
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08750 */	u64	rf_cp_xt_itag_rtl_top;
+#define	VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08758 */	u64	rf_cp_xt_dcache_rtl_top_0_0;
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08760 */	u64	rf_cp_xt_dcache_rtl_top_1_0;
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08768 */	u64	rf_cp_xt_dcache_rtl_top_0_1;
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08770 */	u64	rf_cp_xt_dcache_rtl_top_1_1;
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08778 */	u64	rf_xtmc_bdt_mem_rtl_top_0;
+#define	VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08780 */	u64	rf_xtmc_bdt_mem_rtl_top_1;
+#define	VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08788 */	u64	rf_xt_pif_sram_rtl_top_sram0;
+#define	VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08790 */	u64	rf_xt_pif_sram_rtl_top_sram1;
+#define	VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08798 */	u64	rf_stc_srch_mem_rtl_top_0_0;
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x087a0 */	u64	rf_stc_srch_mem_rtl_top_1_0;
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x087a8 */	u64	rf_stc_srch_mem_rtl_top_0_1;
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x087b0 */	u64	rf_stc_srch_mem_rtl_top_1_1;
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x087b8 */	u64	rf_dam_wrresp_rtl_top;
+#define	VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x087c0 */	u64	rf_dam_rdsb_fifo_rtl_top;
+#define	VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x087c8 */	u64	rf_dam_wrsb_fifo_rtl_top;
+#define	VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x087d0 */	u64	rr_dbf_ladd_0_dbl_rtl_top;
+#define	VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 5)
+#define	VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 6)
+#define	VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 5)
+/* 0x087d8 */	u64	rr_dbf_ladd_1_dbl_rtl_top;
+#define	VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 5)
+#define	VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 6)
+#define	VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 5)
+/* 0x087e0 */	u64	rr_dbf_ladd_2_dbl_rtl_top;
+#define	VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 5)
+#define	VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 6)
+#define	VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 5)
+/* 0x087e8 */	u64	rr_dbf_hadd_0_dbl_rtl_top;
+#define	VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 5)
+#define	VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 6)
+#define	VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 5)
+/* 0x087f0 */	u64	rr_dbf_hadd_1_dbl_rtl_top;
+#define	VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 5)
+#define	VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 6)
+#define	VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 5)
+/* 0x087f8 */	u64	rr_dbf_hadd_2_dbl_rtl_top;
+#define	VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 5)
+#define	VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 6)
+#define	VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 5)
+/* 0x08800 */	u64	rf_usdc_0_fifo_rtl_top;
+#define	VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08808 */	u64	rf_usdc_1_fifo_rtl_top;
+#define	VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08810 */	u64	rf_usdc_0_wa_rtl_top;
+#define	VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08818 */	u64	rf_usdc_1_wa_rtl_top;
+#define	VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08820 */	u64	rf_usdc_0_sa_rtl_top;
+#define	VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08828 */	u64	rf_usdc_1_sa_rtl_top;
+#define	VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08830 */	u64	rf_usdc_0_ca_rtl_top;
+#define	VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08838 */	u64	rf_usdc_1_ca_rtl_top;
+#define	VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08840 */	u64	rf_g3if_fb_rd1;
+#define	VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_ALL_FUSE(val)   vBIT(val, 2, 8)
+/* 0x08848 */	u64	rf_g3if_fb_rd2;
+#define	VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_REPAIR_STATUS(val) vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_ALL_FUSE(val)   vBIT(val, 2, 8)
+/* 0x08850 */	u64	rf_g3if_fb_ctrl_rtl_top1;
+#define	VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08858 */	u64	rf_g3if_fb_ctrl_rtl_top;
+#define	VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08860 */	u64	rr_rocrc_frmbuf_rtl_top_0;
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08868 */	u64	rr_rocrc_frmbuf_rtl_top_1;
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08870 */	u64	rr_fau_xfmd_ins_rtl_top;
+#define	VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08878 */	u64	rf_fbmc_xfmd_rtl_top_a1;
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08880 */	u64	rf_fbmc_xfmd_rtl_top_a2;
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08888 */	u64	rf_fbmc_xfmd_rtl_top_a3;
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08890 */	u64	rf_fbmc_xfmd_rtl_top_b1;
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08898 */	u64	rf_fbmc_xfmd_rtl_top_b2;
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x088a0 */	u64	rf_fbmc_xfmd_rtl_top_b3;
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x088a8 */	u64	rr_fau_mac2f_w_h_rtl_top_port0;
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x088b0 */	u64	rr_fau_mac2f_w_h_rtl_top_port1;
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x088b8 */	u64	rr_fau_mac2f_n_h_rtl_top_port0;
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x088c0 */	u64	rr_fau_mac2f_n_h_rtl_top_port1;
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x088c8 */	u64	rr_fau_mac2f_w_l_rtl_top_port2;
+#define	VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x088d0 */	u64	rr_fau_mac2f_n_l_rtl_top_port2;
+#define	VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x088d8 */	u64	rf_orp_frm_fifo_rtl_top_0;
+#define	VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x088e0 */	u64	rf_orp_frm_fifo_rtl_top_1;
+#define	VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x088e8 */	u64	rf_tpa_da_lkp_rtl_top_0_0;
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x088f0 */	u64	rf_tpa_da_lkp_rtl_top_1_0;
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x088f8 */	u64	rf_tpa_da_lkp_rtl_top_0_1;
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08900 */	u64	rf_tpa_da_lkp_rtl_top_1_1;
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08908 */	u64	rf_tmac_tpa2mac_rtl_top_0_0;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08910 */	u64	rf_tmac_tpa2mac_rtl_top_1_0;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08918 */	u64	rf_tmac_tpa2mac_rtl_top_2_0;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08920 */	u64	rf_tmac_tpa2mac_rtl_top_0_1;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08928 */	u64	rf_tmac_tpa2mac_rtl_top_1_1;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08930 */	u64	rf_tmac_tpa2mac_rtl_top_2_1;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08938 */	u64	rf_tmac_tpa2mac_rtl_top_0_2;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08940 */	u64	rf_tmac_tpa2mac_rtl_top_1_2;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08948 */	u64	rf_tmac_tpa2mac_rtl_top_2_2;
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08950 */	u64	rf_tmac_tpa2m_da_rtl_top;
+#define	VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08958 */	u64	rf_tmac_tpa2m_sb_rtl_top;
+#define	VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08960 */	u64	rf_xt_trace_rtl_top_mp;
+#define	VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08968 */	u64	rf_mp_xt_dtag_rtl_top;
+#define	VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x08970 */	u64	rf_mp_xt_icache_rtl_top_0_0;
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08978 */	u64	rf_mp_xt_icache_rtl_top_1_0;
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08980 */	u64	rf_mp_xt_icache_rtl_top_0_1;
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08988 */	u64	rf_mp_xt_icache_rtl_top_1_1;
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08990 */	u64	rf_mp_xt_itag_rtl_top;
+#define	VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x08998 */	u64	rf_mp_xt_dcache_rtl_top_0_0;
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x089a0 */	u64	rf_mp_xt_dcache_rtl_top_1_0;
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x089a8 */	u64	rf_mp_xt_dcache_rtl_top_0_1;
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x089b0 */	u64	rf_mp_xt_dcache_rtl_top_1_1;
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x089b8 */	u64	rf_msg_bwr_pf_rtl_top_0;
+#define	VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x089c0 */	u64	rf_msg_bwr_pf_rtl_top_1;
+#define	VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x089c8 */	u64	rf_msg_umq_rtl_top_0;
+#define	VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7)
+/* 0x089d0 */	u64	rf_msg_umq_rtl_top_1;
+#define	VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7)
+/* 0x089d8 */	u64	rf_msg_dmq_rtl_top_0;
+#define	VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x089e0 */	u64	rf_msg_dmq_rtl_top_1;
+#define	VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x089e8 */	u64	rf_msg_dmq_rtl_top_2;
+#define	VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x089f0 */	u64	rf_msg_dma_resp_rtl_top_0;
+#define	VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x089f8 */	u64	rf_msg_dma_resp_rtl_top_1;
+#define	VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a00 */	u64	rf_msg_dma_resp_rtl_top_2;
+#define	VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a08 */	u64	rf_msg_cmg2msg_rtl_top_0_0;
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a10 */	u64	rf_msg_cmg2msg_rtl_top_1_0;
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a18 */	u64	rf_msg_cmg2msg_rtl_top_0_1;
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a20 */	u64	rf_msg_cmg2msg_rtl_top_1_1;
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a28 */	u64	rf_msg_txpe2msg_rtl_top;
+#define	VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08a30 */	u64	rf_msg_rxpe2msg_rtl_top;
+#define	VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08a38 */	u64	rf_msg_rpe2msg_rtl_top;
+#define	VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08a40 */	u64	rr_tim_bmap_rtl_top;
+#define	VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_FUSE(val) vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_FUSE(val) vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08a48 */	u64	rf_tim_vbls_rtl_top;
+#define	VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
+/* 0x08a50 */	u64	rf_tim_bmap_msg_rtl_top_0_0;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a58 */	u64	rf_tim_bmap_msg_rtl_top_1_0;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a60 */	u64	rf_tim_bmap_msg_rtl_top_2_0;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a68 */	u64	rf_tim_bmap_msg_rtl_top_0_1;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a70 */	u64	rf_tim_bmap_msg_rtl_top_1_1;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a78 */	u64	rf_tim_bmap_msg_rtl_top_2_1;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a80 */	u64	rf_tim_bmap_msg_rtl_top_0_2;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a88 */	u64	rf_tim_bmap_msg_rtl_top_1_2;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a90 */	u64	rf_tim_bmap_msg_rtl_top_2_2;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08a98 */	u64	rf_tim_bmap_msg_rtl_top_0_3;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08aa0 */	u64	rf_tim_bmap_msg_rtl_top_1_3;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08aa8 */	u64	rf_tim_bmap_msg_rtl_top_2_3;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ab0 */	u64	rf_tim_bmap_msg_rtl_top_0_4;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ab8 */	u64	rf_tim_bmap_msg_rtl_top_1_4;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ac0 */	u64	rf_tim_bmap_msg_rtl_top_2_4;
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ac8 */	u64	rf_xt_trace_rtl_top_up;
+#define	VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08ad0 */	u64	rf_up_xt_dtag_rtl_top;
+#define	VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x08ad8 */	u64	rf_up_xt_icache_rtl_top_0_0;
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ae0 */	u64	rf_up_xt_icache_rtl_top_1_0;
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ae8 */	u64	rf_up_xt_icache_rtl_top_0_1;
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08af0 */	u64	rf_up_xt_icache_rtl_top_1_1;
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08af8 */	u64	rf_up_xt_itag_rtl_top;
+#define	VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6)
+/* 0x08b00 */	u64	rf_up_xt_dcache_rtl_top_0_0;
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08b08 */	u64	rf_up_xt_dcache_rtl_top_1_0;
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08b10 */	u64	rf_up_xt_dcache_rtl_top_0_1;
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08b18 */	u64	rf_up_xt_dcache_rtl_top_1_1;
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08b20 */	u64	rr_rxpe_xt0_iram_rtl_top_0;
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 4)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 7)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 4)
+/* 0x08b28 */	u64	rr_rxpe_xt0_iram_rtl_top_1;
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 4)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 7)
+#define	VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 4)
+/* 0x08b30 */	u64	rr_rxpe_xt_dram_rtl_top_0;
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x08b38 */	u64	rr_rxpe_xt_dram_rtl_top_1;
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x08b40 */	u64	rf_rxpe_msg2rxpe_rtl_top_0;
+#define	VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08b48 */	u64	rf_rxpe_msg2rxpe_rtl_top_1;
+#define	VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08b50 */	u64	rf_rxpe_xt0_frm_rtl_top;
+#define	VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08b58 */	u64	rf_rpe_pdm_rcmd_rtl_top;
+#define	VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08b60 */	u64	rf_rpe_rcq_rtl_top;
+#define	VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
+/* 0x08b68 */	u64	rf_rpe_rco_pble_rtl_top;
+#define	VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08b70 */	u64	rr_rxpe_xt1_iram_rtl_top_0;
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 4)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 7)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 4)
+/* 0x08b78 */	u64	rr_rxpe_xt1_iram_rtl_top_1;
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 4)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 13, 7)
+#define	VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 4)
+/* 0x08b80 */	u64	rr_rpe_sccm_rtl_top_0;
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08b88 */	u64	rr_rpe_sccm_rtl_top_1;
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08b90 */	u64	rr_pe_pet_timer_rtl_top_0;
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x08b98 */	u64	rr_pe_pet_timer_rtl_top_1;
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 7)
+#define	VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 19, 3)
+/* 0x08ba0 */	u64	rf_pe_dlm_lwrq_rtl_top_0;
+#define	VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08ba8 */	u64	rf_pe_dlm_lwrq_rtl_top_1;
+#define	VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bb0 */	u64	rf_txpe_msg2txpe_rtl_top_0;
+#define	VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bb8 */	u64	rf_txpe_msg2txpe_rtl_top_1;
+#define	VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bc0 */	u64	rf_pci_retry_buf_rtl_top_0;
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bc8 */	u64	rf_pci_retry_buf_rtl_top_1;
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bd0 */	u64	rf_pci_retry_buf_rtl_top_2;
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bd8 */	u64	rf_pci_retry_buf_rtl_top_3;
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08be0 */	u64	rf_pci_retry_buf_rtl_top_4;
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08be8 */	u64	rf_pci_retry_buf_rtl_top_5;
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08bf0 */	u64	rf_pci_sot_buf_rtl_top;
+#define	VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08bf8 */	u64	rf_pci_rx_ph_rtl_top;
+#define	VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
+/* 0x08c00 */	u64	rf_pci_rx_nph_rtl_top;
+#define	VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8)
+/* 0x08c08 */	u64	rf_pci_rx_pd_rtl_top_0;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c10 */	u64	rf_pci_rx_pd_rtl_top_1;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c18 */	u64	rf_pci_rx_pd_rtl_top_2;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c20 */	u64	rf_pci_rx_pd_rtl_top_3;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c28 */	u64	rf_pci_rx_pd_rtl_top_4;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c30 */	u64	rf_pci_rx_pd_rtl_top_5;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c38 */	u64	rf_pci_rx_pd_rtl_top_6;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c40 */	u64	rf_pci_rx_pd_rtl_top_7;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c48 */	u64	rf_pci_rx_pd_rtl_top_8;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c50 */	u64	rf_pci_rx_pd_rtl_top_9;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c58 */	u64	rf_pci_rx_pd_rtl_top_10;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c60 */	u64	rf_pci_rx_pd_rtl_top_11;
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c68 */	u64	rf_pci_rx_npd_rtl_top_0;
+#define	VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c70 */	u64	rf_pci_rx_npd_rtl_top_1;
+#define	VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08c78 */	u64	rf_pic_kdfc_dbl_rtl_top_0;
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08c80 */	u64	rf_pic_kdfc_dbl_rtl_top_1;
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08c88 */	u64	rf_pic_kdfc_dbl_rtl_top_2;
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08c90 */	u64	rf_pic_kdfc_dbl_rtl_top_3;
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08c98 */	u64	rf_pic_kdfc_dbl_rtl_top_4;
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08ca0 */	u64	rf_pcc_txdo_rtl_top_pcc0;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08ca8 */	u64	rf_pcc_txdo_rtl_top_pcc1;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08cb0 */	u64	rf_pcc_txdo_rtl_top_pcc2;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08cb8 */	u64	rf_pcc_txdo_rtl_top_pcc3;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08cc0 */	u64	rf_pcc_txdo_rtl_top_pcc4;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08cc8 */	u64	rf_pcc_txdo_rtl_top_pcc5;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08cd0 */	u64	rf_pcc_txdo_rtl_top_pcc6;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08cd8 */	u64	rf_pcc_txdo_rtl_top_pcc7;
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08ce0 */	u64	rr_pcc_ass_buf_rtl_top_pcc1;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08ce8 */	u64	rr_pcc_ass_buf_rtl_top_pcc3;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08cf0 */	u64	rr_pcc_ass_buf_rtl_top_pcc5;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08cf8 */	u64	rr_pcc_ass_buf_rtl_top_pcc7;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d00 */	u64	rr_pcc_ass_buf_rtl_top_pcc0;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d08 */	u64	rr_pcc_ass_buf_rtl_top_pcc2;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d10 */	u64	rr_pcc_ass_buf_rtl_top_pcc6;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d18 */	u64	rr_pcc_ass_buf_rtl_top_pcc4;
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d20 */	u64	rf_rocrc_cmdq_bp_rtl_top_0_wrapper0;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d28 */	u64	rf_rocrc_cmdq_bp_rtl_top_1_wrapper0;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d30 */	u64	rf_rocrc_cmdq_bp_rtl_top_2_wrapper0;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_WRAPPER0_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d38 */	u64	rf_rocrc_cmdq_bp_rtl_top_0_wrapper1;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d40 */	u64	rf_rocrc_cmdq_bp_rtl_top_1_wrapper1;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d48 */	u64	rf_rocrc_cmdq_bp_rtl_top_2_wrapper1;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d50 */	u64	rf_rocrc_cmdq_bp_rtl_top_0_wrapper2;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_WRAPPER2_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d58 */	u64	rf_rocrc_cmdq_bp_rtl_top_1_wrapper2;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d60 */	u64	rf_rocrc_cmdq_bp_rtl_top_2_wrapper2;
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d68 */	u64	rr_rocrc_rxd_rtl_top_rxd0;
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d70 */	u64	rr_rocrc_rxd_rtl_top_rxd1;
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 8)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 10, 2)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 12, 8)
+#define	VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 20, 2)
+/* 0x08d78 */	u64	rf_rocrc_umq_mdq_rtl_top_0;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d80 */	u64	rf_rocrc_umq_mdq_rtl_top_1;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d88 */	u64	rf_rocrc_umq_mdq_rtl_top_2;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d90 */	u64	rf_rocrc_umq_mdq_rtl_top_3;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08d98 */	u64	rf_rocrc_umq_mdq_rtl_top_4;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08da0 */	u64	rf_rocrc_umq_mdq_rtl_top_5;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08da8 */	u64	rf_rocrc_umq_mdq_rtl_top_6;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08db0 */	u64	rf_rocrc_umq_mdq_rtl_top_7;
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08db8 */	u64	rf_rocrc_immdbuf_rtl_top;
+#define	VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08dc0 */	u64	rf_rocrc_qcc_byp_rtl_top_0;
+#define	VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08dc8 */	u64	rf_rocrc_qcc_byp_rtl_top_1;
+#define	VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08dd0 */	u64	rr_rmac_da_lkp_rtl_top_0;
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 10, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 16, 2)
+/* 0x08dd8 */	u64	rr_rmac_da_lkp_rtl_top_1;
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 10, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 16, 2)
+/* 0x08de0 */	u64	rr_rmac_da_lkp_rtl_top_2;
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 10, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 16, 2)
+/* 0x08de8 */	u64	rr_rmac_da_lkp_rtl_top_3;
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 8, 2)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 10, 6)
+#define	VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 16, 2)
+/* 0x08df0 */	u64	rr_rmac_pn_lkp_d_rtl_top;
+#define	VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_FUSE(val)\
+							    vBIT(val, 2, 7)
+#define	VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\
+							    vBIT(val, 9, 2)
+#define	VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_FUSE(val)\
+							    vBIT(val, 11, 7)
+#define	VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\
+							    vBIT(val, 18, 2)
+/* 0x08df8 */	u64	rf_rmac_pn_lkp_s_rtl_top_0;
+#define	VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08e00 */	u64	rf_rmac_pn_lkp_s_rtl_top_1;
+#define	VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08e08 */	u64	rf_rmac_rth_lkp_rtl_top_0_0;
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e10 */	u64	rf_rmac_rth_lkp_rtl_top_1_0;
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e18 */	u64	rf_rmac_rth_lkp_rtl_top_0_1;
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e20 */	u64	rf_rmac_rth_lkp_rtl_top_1_1;
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e28 */	u64	rf_rmac_ds_lkp_rtl_top;
+#define	VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08e30 */	u64	rf_rmac_rts_part_rtl_top_0_rmac0;
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e38 */	u64	rf_rmac_rts_part_rtl_top_1_rmac0;
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e40 */	u64	rf_rmac_rts_part_rtl_top_0_rmac1;
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e48 */	u64	rf_rmac_rts_part_rtl_top_1_rmac1;
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e50 */	u64	rf_rmac_rts_part_rtl_top_0_rmac2;
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e58 */	u64	rf_rmac_rts_part_rtl_top_1_rmac2;
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e60 */	u64	rf_rmac_rth_mask_rtl_top_0;
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e68 */	u64	rf_rmac_rth_mask_rtl_top_1;
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e70 */	u64	rf_rmac_rth_mask_rtl_top_2;
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e78 */	u64	rf_rmac_rth_mask_rtl_top_3;
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 8)
+/* 0x08e80 */	u64	rf_rmac_vid_lkp_rtl_top_0;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08e88 */	u64	rf_rmac_vid_lkp_rtl_top_1;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08e90 */	u64	rf_rmac_vid_lkp_rtl_top_2;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08e98 */	u64	rf_rmac_vid_lkp_rtl_top_3;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ea0 */	u64	rf_rmac_vid_lkp_rtl_top_4;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ea8 */	u64	rf_rmac_vid_lkp_rtl_top_5;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08eb0 */	u64	rf_rmac_vid_lkp_rtl_top_6;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08eb8 */	u64	rf_rmac_vid_lkp_rtl_top_7;
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_REPAIR_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 6)
+/* 0x08ec0 */	u64	rf_rmac_stats_rtl_top_0_stats_0;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ec8 */	u64	rf_rmac_stats_rtl_top_1_stats_0;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ed0 */	u64	rf_rmac_stats_rtl_top_0_stats_1;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ed8 */	u64	rf_rmac_stats_rtl_top_1_stats_1;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ee0 */	u64	rf_rmac_stats_rtl_top_0_stats_2;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ee8 */	u64	rf_rmac_stats_rtl_top_1_stats_2;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ef0 */	u64	rf_rmac_stats_rtl_top_0_stats_3;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08ef8 */	u64	rf_rmac_stats_rtl_top_1_stats_3;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08f00 */	u64	rf_rmac_stats_rtl_top_0_stats_4;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+/* 0x08f08 */	u64	rf_rmac_stats_rtl_top_1_stats_4;
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\
+							    vBIT(val, 2, 7)
+	u8	unused09000[0x09000 - 0x08f10];
+
+/* 0x09000 */	u64	g3ifcmd_fb_int_status;
+#define	VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT	    mBIT(0)
+/* 0x09008 */	u64	g3ifcmd_fb_int_mask;
+/* 0x09010 */	u64	g3ifcmd_fb_err_reg;
+#define	VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK	    mBIT(6)
+#define	VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR		    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT	    mBIT(55)
+/* 0x09018 */	u64	g3ifcmd_fb_err_mask;
+/* 0x09020 */	u64	g3ifcmd_fb_err_alarm;
+/* 0x09028 */	u64	g3ifcmd_fb_dll_ck0;
+#define	VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SA_CAL(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SB_CAL(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_CK0_ROLL		    mBIT(23)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_CK0_CMD_ADD_DLL_0_S(val)    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_ENABLE		    mBIT(39)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_UPD(val)	    vBIT(val, 44, 4)
+/* 0x09030 */	u64	g3ifcmd_fb_io_ctrl;
+#define	VXGE_HAL_G3IFCMD_FB_IO_CTRL_DRIVE		    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_FB_IO_CTRL_TERM(val)		    vBIT(val, 13, 3)
+/* 0x09038 */	u64	g3ifcmd_fb_iocal;
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_RST_CYCLES(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_RST_VALUE(val)	    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_CORR_VALUE(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7)
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7)
+#define	VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7)
+/* 0x09040 */	u64	g3ifcmd_fb_master_dll_ck;
+#define	VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_DDR_GR_RAW(val)   vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_SAMPLE(val)	    vBIT(val, 8, 8)
+/* 0x09048 */	u64	g3ifcmd_fb_dll_training;
+#define	VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_TRA_START	    mBIT(6)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_TRA_DISABLE	    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_START_CODE(val)    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_END_CODE(val)	    vBIT(val, 17, 7)
+	u8	unused09110[0x09110 - 0x09050];
+
+/* 0x09110 */	u64	g3ifgr01_fb_group0_dll_rdqs;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09118 */	u64	g3ifgr01_fb_group0_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_ENABLE    mBIT(14)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+/* 0x09120 */	u64	g3ifgr01_fb_group0_dll_wdqs;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09128 */	u64	g3ifgr01_fb_group0_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_ENABLE    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x09130 */	u64	g3ifgr01_fb_group0_dll_training1;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09138 */	u64	g3ifgr01_fb_group0_dll_training2;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09140 */	u64	g3ifgr01_fb_group0_dll_training3;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09148 */	u64	g3ifgr01_fb_group0_dll_act_training5;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x09150 */	u64	g3ifgr01_fb_group0_dll_training6;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x09158 */	u64	g3ifgr01_fb_group0_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09160 */	u64	g3ifgr01_fb_group0_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09168 */	u64	g3ifgr01_fb_group0_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09170 */	u64	g3ifgr01_fb_group0_dll_master_codes;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09178 */	u64	g3ifgr01_fb_group0_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_VALUE(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_ENABLED  mBIT(23)
+/* 0x09180 */	u64	g3ifgr01_fb_group1_dll_rdqs;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SA_CAL(val)\
+							    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SB_CAL(val)\
+							    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SA_CAL(val)\
+							    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SB_CAL(val)\
+							    vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_DDR_DLL_S(val)\
+							    vBIT(val, 57, 7)
+/* 0x09188 */	u64	g3ifgr01_fb_group1_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_ENABLE    mBIT(14)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+/* 0x09190 */	u64	g3ifgr01_fb_group1_dll_wdqs;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09198 */	u64	g3ifgr01_fb_group1_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_ENABLE    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x091a0 */	u64	g3ifgr01_fb_group1_dll_training1;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x091a8 */	u64	g3ifgr01_fb_group1_dll_training2;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x091b0 */	u64	g3ifgr01_fb_group1_dll_training3;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x091b8 */	u64	g3ifgr01_fb_group1_dll_act_training5;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_DISABLE	mBIT(23)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_TCNT(val)	vBIT(val, 28, 4)
+/* 0x091c0 */	u64	g3ifgr01_fb_group1_dll_training6;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+								mBIT(7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+								mBIT(15)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORRECTION\
+								mBIT(23)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORRECTION\
+								mBIT(31)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x091c8 */	u64	g3ifgr01_fb_group1_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x091d0 */	u64	g3ifgr01_fb_group1_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x091d8 */	u64	g3ifgr01_fb_group1_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x091e0 */	u64	g3ifgr01_fb_group1_dll_master_codes;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x091e8 */	u64	g3ifgr01_fb_group1_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_ENABLED  mBIT(23)
+	u8	unused09210[0x09210 - 0x091f0];
+
+/* 0x09210 */	u64	g3ifgr23_fb_group2_dll_rdqs;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09218 */	u64	g3ifgr23_fb_group2_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_ENABLE    mBIT(14)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+/* 0x09220 */	u64	g3ifgr23_fb_group2_dll_wdqs;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09228 */	u64	g3ifgr23_fb_group2_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_ENABLE    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x09230 */	u64	g3ifgr23_fb_group2_dll_training1;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09238 */	u64	g3ifgr23_fb_group2_dll_training2;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09240 */	u64	g3ifgr23_fb_group2_dll_training3;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09248 */	u64	g3ifgr23_fb_group2_dll_act_training5;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x09250 */	u64	g3ifgr23_fb_group2_dll_training6;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORRECTION\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORRECTION\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x09258 */	u64	g3ifgr23_fb_group2_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09260 */	u64	g3ifgr23_fb_group2_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09268 */	u64	g3ifgr23_fb_group2_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09270 */	u64	g3ifgr23_fb_group2_dll_master_codes;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09278 */	u64	g3ifgr23_fb_group2_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_ENABLED  mBIT(23)
+/* 0x09280 */	u64	g3ifgr23_fb_group3_dll_rdqs;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09288 */	u64	g3ifgr23_fb_group3_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_ENABLE    mBIT(14)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+/* 0x09290 */	u64	g3ifgr23_fb_group3_dll_wdqs;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SA_CAL(val)    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SB_CAL(val)    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09298 */	u64	g3ifgr23_fb_group3_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_ENABLE    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_UPD(val)  vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x092a0 */	u64	g3ifgr23_fb_group3_dll_training1;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x092a8 */	u64	g3ifgr23_fb_group3_dll_training2;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x092b0 */	u64	g3ifgr23_fb_group3_dll_training3;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x092b8 */	u64	g3ifgr23_fb_group3_dll_act_training5;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_TCNT(val)	vBIT(val, 28, 4)
+/* 0x092c0 */	u64	g3ifgr23_fb_group3_dll_training6;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORRECTION\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORRECTION\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x092c8 */	u64	g3ifgr23_fb_group3_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x092d0 */	u64	g3ifgr23_fb_group3_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x092d8 */	u64	g3ifgr23_fb_group3_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x092e0 */	u64	g3ifgr23_fb_group3_dll_master_codes;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x092e8 */	u64	g3ifgr23_fb_group3_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_ENABLED  mBIT(23)
+	u8	unused09400[0x09400 - 0x092f0];
+
+/* 0x09400 */	u64	g3ifcmd_cmu_int_status;
+#define	VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT	    mBIT(0)
+/* 0x09408 */	u64	g3ifcmd_cmu_int_mask;
+/* 0x09410 */	u64	g3ifcmd_cmu_err_reg;
+#define	VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK	    mBIT(6)
+#define	VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR	    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8)
+#define	VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT	    mBIT(55)
+/* 0x09418 */	u64	g3ifcmd_cmu_err_mask;
+/* 0x09420 */	u64	g3ifcmd_cmu_err_alarm;
+/* 0x09428 */	u64	g3ifcmd_cmu_dll_ck0;
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SA_CAL(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SB_CAL(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_CK0_ROLL		    mBIT(23)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_CK0_CMD_ADD_DLL_0_S(val)   vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_ENABLE		    mBIT(39)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_UPD(val)	    vBIT(val, 44, 4)
+/* 0x09430 */	u64	g3ifcmd_cmu_io_ctrl;
+#define	VXGE_HAL_G3IFCMD_CMU_IO_CTRL_DRIVE		    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_CMU_IO_CTRL_TERM(val)		    vBIT(val, 13, 3)
+/* 0x09438 */	u64	g3ifcmd_cmu_iocal;
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_CYCLES(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_VALUE(val)	    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_CORR_VALUE(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7)
+/* 0x09440 */	u64	g3ifcmd_cmu_master_dll_ck;
+#define	VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_DDR_GR_RAW(val)  vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_SAMPLE(val)	    vBIT(val, 8, 8)
+/* 0x09448 */	u64	g3ifcmd_cmu_dll_training;
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_TRA_START	    mBIT(6)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_TRA_DISABLE	    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_START_CODE(val)   vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_END_CODE(val)	    vBIT(val, 17, 7)
+	u8	unused09510[0x09510 - 0x09450];
+
+/* 0x09510 */	u64	g3ifgr01_cmu_group0_dll_rdqs;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09518 */	u64	g3ifgr01_cmu_group0_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09520 */	u64	g3ifgr01_cmu_group0_dll_wdqs;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09528 */	u64	g3ifgr01_cmu_group0_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN\
+							    mBIT(31)
+/* 0x09530 */	u64	g3ifgr01_cmu_group0_dll_training1;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09538 */	u64	g3ifgr01_cmu_group0_dll_training2;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09540 */	u64	g3ifgr01_cmu_group0_dll_training3;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09548 */	u64	g3ifgr01_cmu_group0_dll_act_training5;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x09550 */	u64	g3ifgr01_cmu_group0_dll_training6;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x09558 */	u64	g3ifgr01_cmu_group0_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09560 */	u64	g3ifgr01_cmu_group0_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09568 */	u64	g3ifgr01_cmu_group0_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09570 */	u64	g3ifgr01_cmu_group0_dll_master_codes;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09578 */	u64	g3ifgr01_cmu_group0_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23)
+/* 0x09580 */	u64	g3ifgr01_cmu_group1_dll_rdqs;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09588 */	u64	g3ifgr01_cmu_group1_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09590 */	u64	g3ifgr01_cmu_group1_dll_wdqs;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09598 */	u64	g3ifgr01_cmu_group1_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x095a0 */	u64	g3ifgr01_cmu_group1_dll_training1;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x095a8 */	u64	g3ifgr01_cmu_group1_dll_training2;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x095b0 */	u64	g3ifgr01_cmu_group1_dll_training3;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x095b8 */	u64	g3ifgr01_cmu_group1_dll_act_training5;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x095c0 */	u64	g3ifgr01_cmu_group1_dll_training6;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x095c8 */	u64	g3ifgr01_cmu_group1_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x095d0 */	u64	g3ifgr01_cmu_group1_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x095d8 */	u64	g3ifgr01_cmu_group1_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x095e0 */	u64	g3ifgr01_cmu_group1_dll_master_codes;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x095e8 */	u64	g3ifgr01_cmu_group1_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23)
+	u8	unused09610[0x09610 - 0x095f0];
+
+/* 0x09610 */	u64	g3ifgr23_cmu_group2_dll_rdqs;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09618 */	u64	g3ifgr23_cmu_group2_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09620 */	u64	g3ifgr23_cmu_group2_dll_wdqs;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09628 */	u64	g3ifgr23_cmu_group2_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_DLL_ENABLE\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_DLL_UPD(val)\
+							    vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN\
+							    mBIT(31)
+/* 0x09630 */	u64	g3ifgr23_cmu_group2_dll_training1;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09638 */	u64	g3ifgr23_cmu_group2_dll_training2;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09640 */	u64	g3ifgr23_cmu_group2_dll_training3;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09648 */	u64	g3ifgr23_cmu_group2_dll_act_training5;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_DISABLE	mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x09650 */	u64	g3ifgr23_cmu_group2_dll_training6;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x09658 */	u64	g3ifgr23_cmu_group2_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09660 */	u64	g3ifgr23_cmu_group2_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09668 */	u64	g3ifgr23_cmu_group2_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09670 */	u64	g3ifgr23_cmu_group2_dll_master_codes;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09678 */	u64	g3ifgr23_cmu_group2_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23)
+/* 0x09680 */	u64	g3ifgr23_cmu_group3_dll_rdqs;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09688 */	u64	g3ifgr23_cmu_group3_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09690 */	u64	g3ifgr23_cmu_group3_dll_wdqs;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09698 */	u64	g3ifgr23_cmu_group3_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x096a0 */	u64	g3ifgr23_cmu_group3_dll_training1;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x096a8 */	u64	g3ifgr23_cmu_group3_dll_training2;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x096b0 */	u64	g3ifgr23_cmu_group3_dll_training3;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x096b8 */	u64	g3ifgr23_cmu_group3_dll_act_training5;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_DISABLE\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x096c0 */	u64	g3ifgr23_cmu_group3_dll_training6;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x096c8 */	u64	g3ifgr23_cmu_group3_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x096d0 */	u64	g3ifgr23_cmu_group3_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x096d8 */	u64	g3ifgr23_cmu_group3_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x096e0 */	u64	g3ifgr23_cmu_group3_dll_master_codes;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x096e8 */	u64	g3ifgr23_cmu_group3_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23)
+	u8	unused09800[0x09800 - 0x096f0];
+
+/* 0x09800 */	u64	g3ifcmd_cml_int_status;
+#define	VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT	    mBIT(0)
+/* 0x09808 */	u64	g3ifcmd_cml_int_mask;
+/* 0x09810 */	u64	g3ifcmd_cml_err_reg;
+#define	VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK	    mBIT(6)
+#define	VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR	    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val)\
+							    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT	    mBIT(55)
+/* 0x09818 */	u64	g3ifcmd_cml_err_mask;
+/* 0x09820 */	u64	g3ifcmd_cml_err_alarm;
+/* 0x09828 */	u64	g3ifcmd_cml_dll_ck0;
+#define	VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SA_CAL(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SB_CAL(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_CK0_ROLL		    mBIT(23)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_CK0_CMD_ADD_DLL_0_S(val)   vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_ENABLE	mBIT(39)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_UPD(val)	    vBIT(val, 44, 4)
+/* 0x09830 */	u64	g3ifcmd_cml_io_ctrl;
+#define	VXGE_HAL_G3IFCMD_CML_IO_CTRL_DRIVE		    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_CML_IO_CTRL_TERM(val)		    vBIT(val, 13, 3)
+/* 0x09838 */	u64	g3ifcmd_cml_iocal;
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_RST_CYCLES(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_RST_VALUE(val)	    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_CORR_VALUE(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE0(val)\
+							    vBIT(val, 33, 7)
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE1(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE2(val)\
+							    vBIT(val, 49, 7)
+#define	VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE3(val)\
+							    vBIT(val, 57, 7)
+/* 0x09840 */	u64	g3ifcmd_cml_master_dll_ck;
+#define	VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_DDR_GR_RAW(val)  vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_SAMPLE(val)	    vBIT(val, 8, 8)
+/* 0x09848 */	u64	g3ifcmd_cml_dll_training;
+#define	VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_TRA_START	    mBIT(6)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_TRA_DISABLE	    mBIT(7)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_START_CODE(val)   vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_END_CODE(val)	    vBIT(val, 17, 7)
+	u8	unused09910[0x09910 - 0x09850];
+
+/* 0x09910 */	u64	g3ifgr01_cml_group0_dll_rdqs;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SA_CAL(val)\
+							    vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SB_CAL(val)\
+							    vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09918 */	u64	g3ifgr01_cml_group0_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09920 */	u64	g3ifgr01_cml_group0_dll_wdqs;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09928 */	u64	g3ifgr01_cml_group0_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN\
+							    mBIT(31)
+/* 0x09930 */	u64	g3ifgr01_cml_group0_dll_training1;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09938 */	u64	g3ifgr01_cml_group0_dll_training2;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09940 */	u64	g3ifgr01_cml_group0_dll_training3;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09948 */	u64	g3ifgr01_cml_group0_dll_act_training5;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x09950 */	u64	g3ifgr01_cml_group0_dll_training6;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x09958 */	u64	g3ifgr01_cml_group0_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09960 */	u64	g3ifgr01_cml_group0_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09968 */	u64	g3ifgr01_cml_group0_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09970 */	u64	g3ifgr01_cml_group0_dll_master_codes;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09978 */	u64	g3ifgr01_cml_group0_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23)
+/* 0x09980 */	u64	g3ifgr01_cml_group1_dll_rdqs;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09988 */	u64	g3ifgr01_cml_group1_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA	mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09990 */	u64	g3ifgr01_cml_group1_dll_wdqs;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09998 */	u64	g3ifgr01_cml_group1_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x099a0 */	u64	g3ifgr01_cml_group1_dll_training1;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x099a8 */	u64	g3ifgr01_cml_group1_dll_training2;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x099b0 */	u64	g3ifgr01_cml_group1_dll_training3;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x099b8 */	u64	g3ifgr01_cml_group1_dll_act_training5;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_DISABLE	mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x099c0 */	u64	g3ifgr01_cml_group1_dll_training6;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x099c8 */	u64	g3ifgr01_cml_group1_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x099d0 */	u64	g3ifgr01_cml_group1_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x099d8 */	u64	g3ifgr01_cml_group1_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x099e0 */	u64	g3ifgr01_cml_group1_dll_master_codes;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x099e8 */	u64	g3ifgr01_cml_group1_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_VALUE(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23)
+	u8	unused09a10[0x09a10 - 0x099f0];
+
+/* 0x09a10 */	u64	g3ifgr23_cml_group2_dll_rdqs;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09a18 */	u64	g3ifgr23_cml_group2_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA	mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09a20 */	u64	g3ifgr23_cml_group2_dll_wdqs;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09a28 */	u64	g3ifgr23_cml_group2_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN\
+							    mBIT(31)
+/* 0x09a30 */	u64	g3ifgr23_cml_group2_dll_training1;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09a38 */	u64	g3ifgr23_cml_group2_dll_training2;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09a40 */	u64	g3ifgr23_cml_group2_dll_training3;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09a48 */	u64	g3ifgr23_cml_group2_dll_act_training5;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_TCNT(val) \
+							    vBIT(val, 28, 4)
+/* 0x09a50 */	u64	g3ifgr23_cml_group2_dll_training6;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY	mBIT(39)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR	mBIT(47)
+/* 0x09a58 */	u64	g3ifgr23_cml_group2_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09a60 */	u64	g3ifgr23_cml_group2_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09a68 */	u64	g3ifgr23_cml_group2_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09a70 */	u64	g3ifgr23_cml_group2_dll_master_codes;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09a78 */	u64	g3ifgr23_cml_group2_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23)
+/* 0x09a80 */	u64	g3ifgr23_cml_group3_dll_rdqs;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09a88 */	u64	g3ifgr23_cml_group3_dll_rdqs1;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_ENABLE   mBIT(14)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+/* 0x09a90 */	u64	g3ifgr23_cml_group3_dll_wdqs;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SA_CAL(val)   vBIT(val, 0, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SB_CAL(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7)
+/* 0x09a98 */	u64	g3ifgr23_cml_group3_dll_wdqs1;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_ROLL	    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_ENABLE   mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31)
+/* 0x09aa0 */	u64	g3ifgr23_cml_group3_dll_training1;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\
+							    vBIT(val, 17, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\
+							    vBIT(val, 49, 7)
+/* 0x09aa8 */	u64	g3ifgr23_cml_group3_dll_training2;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09ab0 */	u64	g3ifgr23_cml_group3_dll_training3;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\
+							    vBIT(val, 16, 16)
+/* 0x09ab8 */	u64	g3ifgr23_cml_group3_dll_act_training5;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_DISABLE mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\
+							    vBIT(val, 28, 4)
+/* 0x09ac0 */	u64	g3ifgr23_cml_group3_dll_training6;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\
+							    mBIT(7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\
+							    mBIT(15)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\
+							    mBIT(23)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\
+							    mBIT(31)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47)
+/* 0x09ac8 */	u64	g3ifgr23_cml_group3_dll_atra_offset;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\
+							    vBIT(val, 8, 8)
+/* 0x09ad0 */	u64	g3ifgr23_cml_group3_dll_tra_hold;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09ad8 */	u64	g3ifgr23_cml_group3_dll_atra_hold;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\
+							    vBIT(val, 16, 24)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\
+							    vBIT(val, 40, 24)
+/* 0x09ae0 */	u64	g3ifgr23_cml_group3_dll_master_codes;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\
+							    vBIT(val, 57, 7)
+/* 0x09ae8 */	u64	g3ifgr23_cml_group3_dll_atra_timer;
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16)
+#define	VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23)
+	u8	unused09b00[0x09b00 - 0x09af0];
+
+/* 0x09b00 */	u64	vpath_to_vplane_map[17];
+#define	VXGE_HAL_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) vBIT(val, 3, 5)
+	u8	unused09c30[0x09c30 - 0x09b88];
+
+/* 0x09c30 */	u64	xgxs_cfg_port[2];
+#define	VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val)    vBIT(val, 16, 4)
+#define	VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val)  vBIT(val, 20, 4)
+#define	VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_0		    mBIT(27)
+#define	VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_1(val)		    vBIT(val, 29, 3)
+#define	VXGE_HAL_XGXS_CFG_PORT_TX_LANE0_SKEW(val)	    vBIT(val, 32, 4)
+#define	VXGE_HAL_XGXS_CFG_PORT_TX_LANE1_SKEW(val)	    vBIT(val, 36, 4)
+#define	VXGE_HAL_XGXS_CFG_PORT_TX_LANE2_SKEW(val)	    vBIT(val, 40, 4)
+#define	VXGE_HAL_XGXS_CFG_PORT_TX_LANE3_SKEW(val)	    vBIT(val, 44, 4)
+/* 0x09c40 */	u64	xgxs_rxber_cfg_port[2];
+#define	VXGE_HAL_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val)	    vBIT(val, 0, 4)
+#define	VXGE_HAL_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) vBIT(val, 16, 48)
+/* 0x09c50 */	u64	xgxs_rxber_status_port[2];
+#define	VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val)\
+							    vBIT(val, 32, 16)
+#define	VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val)\
+							    vBIT(val, 48, 16)
+/* 0x09c60 */	u64	xgxs_status_port[2];
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vBIT(val, 0, 4)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vBIT(val, 4, 4)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR    BIT(11)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) vBIT(val, 12, 4)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val)    vBIT(val, 16, 4)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR   mBIT(23)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val)    vBIT(val, 24, 8)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) vBIT(val, 32, 4)
+#define	VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) vBIT(val, 36, 4)
+/* 0x09c70 */	u64	xgxs_pma_reset_port[2];
+#define	VXGE_HAL_XGXS_PMA_RESET_PORT_SERDES_RESET(val)	    vBIT(val, 0, 8)
+	u8	unused09c90[0x09c90 - 0x09c80];
+
+/* 0x09c90 */	u64	xgxs_static_cfg_port[2];
+#define	VXGE_HAL_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES	    mBIT(3)
+	u8	unused09cc0[0x09cc0 - 0x09ca0];
+
+/* 0x09cc0 */	u64	xgxs_serdes_fw_cfg_port[2];
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE0(val)   vBIT(val, 1, 3)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE1(val)   vBIT(val, 5, 3)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE2(val)   vBIT(val, 9, 3)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE3(val)   vBIT(val, 13, 3)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE0	    mBIT(16)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE1	    mBIT(17)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE2	    mBIT(18)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE3	    mBIT(19)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE0 mBIT(20)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE1 mBIT(21)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE2 mBIT(22)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE3 mBIT(23)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE0   mBIT(24)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE1   mBIT(25)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE2   mBIT(26)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE3   mBIT(27)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_MPLL_CK_OFF	    mBIT(31)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_MPLL_PWRON	    mBIT(35)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_CON(val)  vBIT(val, 37, 3)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RESET_N	    mBIT(43)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_READY	    mBIT(47)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE0  mBIT(48)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE1  mBIT(49)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE2  mBIT(50)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE3  mBIT(51)
+#define	VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TRUST_HW_RX_CK_READY mBIT(55)
+/* 0x09cd0 */	u64	xgxs_serdes_tx_cfg_port[2];
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE0(val) vBIT(val, 0, 4)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE1(val) vBIT(val, 4, 4)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE2(val) vBIT(val, 8, 4)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE3(val) vBIT(val, 12, 4)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE0(val) vBIT(val, 17, 3)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE1(val) vBIT(val, 21, 3)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE2(val) vBIT(val, 25, 3)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE3(val) vBIT(val, 29, 3)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE0	    mBIT(32)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE1	    mBIT(33)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE2	    mBIT(34)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE3	    mBIT(35)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE0 mBIT(36)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE1 mBIT(37)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE2 mBIT(38)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE3 mBIT(39)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE0    mBIT(40)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE1    mBIT(41)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE2    mBIT(42)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE3    mBIT(43)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE0(val)	vBIT(val, 44, 2)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE1(val)	vBIT(val, 46, 2)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE2(val)	vBIT(val, 48, 2)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE3(val)	vBIT(val, 50, 2)
+#define	VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_LVL(val)	    vBIT(val, 55, 5)
+/* 0x09ce0 */	u64	xgxs_serdes_rx_cfg_port[2];
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE0  mBIT(0)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE1  mBIT(1)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE2  mBIT(2)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE3  mBIT(3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE0(val) vBIT(val, 5, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE1(val) vBIT(val, 9, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE2(val) vBIT(val, 13, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE3(val) vBIT(val, 17, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE0(val)\
+							    vBIT(val, 21, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE1(val)\
+							    vBIT(val, 25, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE2(val)\
+							    vBIT(val, 29, 3)
+#define	VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE3(val)\
+							    vBIT(val, 33, 3)
+/* 0x09cf0 */	u64	xgxs_serdes_extra_cfg_port[2];
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE0 mBIT(0)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE1 mBIT(1)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE2 mBIT(2)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE3 mBIT(3)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE0(val) vBIT(val, 4, 2)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE1(val) vBIT(val, 6, 2)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE2(val) vBIT(val, 8, 2)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE3(val) vBIT(val, 10, 2)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_WIDE_XFACE	    mBIT(14)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_RTUNE_DO_TUNE   mBIT(15)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_LVL(val)    vBIT(val, 19, 5)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_CKO_ALIVE_CON(val) vBIT(val, 28, 2)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_SS_EN	    mBIT(32)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_INT_CTL(val) vBIT(val, 33, 3)
+#define	VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_PROP_CTL(val) vBIT(val, 37, 3)
+/* 0x09d00 */	u64	xgxs_serdes_status_port[2];
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE0(val)\
+							    vBIT(val, 0, 2)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE1(val)\
+							    vBIT(val, 2, 2)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE2(val)\
+							    vBIT(val, 4, 2)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE3(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE0 mBIT(8)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE1 mBIT(9)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE2 mBIT(10)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE3 mBIT(11)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE0 mBIT(12)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE1 mBIT(13)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE2 mBIT(14)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE3 mBIT(15)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE0 mBIT(16)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE1 mBIT(17)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE2 mBIT(18)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE3 mBIT(19)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE0 mBIT(20)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE1 mBIT(21)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE2 mBIT(22)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE3 mBIT(23)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE0	    mBIT(24)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE1	    mBIT(25)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE2	    mBIT(26)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE3	    mBIT(27)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_OP_DONE_ASSERTED	mBIT(30)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_OP_DONE_DEASSERTED mBIT(31)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_POWER_GOOD    mBIT(35)
+#define	VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_SERDES_INIT_COMPLETE mBIT(39)
+/* 0x09d10 */	u64	xgxs_serdes_cr_access_port[2];
+#define	VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_WE		    mBIT(3)
+#define	VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_STROBE	    mBIT(7)
+#define	VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_ADDR(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_DATA(val)	    vBIT(val, 48, 16)
+	u8	unused09d40[0x09d40 - 0x09d20];
+
+/* 0x09d40 */	u64	xgxs_info_port[2];
+#define	VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_0(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_1(val)	    vBIT(val, 32, 32)
+/* 0x09d50 */	u64	ratemgmt_cfg_port[2];
+#define	VXGE_HAL_RATEMGMT_CFG_PORT_MODE(val)		    vBIT(val, 2, 2)
+#define	VXGE_HAL_RATEMGMT_CFG_PORT_RATE			    mBIT(7)
+#define	VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM	    mBIT(11)
+#define	VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM		    mBIT(15)
+#define	VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM		    mBIT(19)
+/* 0x09d60 */	u64	ratemgmt_status_port[2];
+#define	VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE	    mBIT(3)
+#define	VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_RATE	    mBIT(7)
+#define	VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY mBIT(11)
+	u8	unused09d80[0x09d80 - 0x09d70];
+
+/* 0x09d80 */	u64	ratemgmt_fixed_cfg_port[2];
+#define	VXGE_HAL_RATEMGMT_FIXED_CFG_PORT_RESTART	    mBIT(7)
+/* 0x09d90 */	u64	ratemgmt_antp_cfg_port[2];
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_RESTART		    mBIT(7)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY mBIT(11)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL	    mBIT(15)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val)\
+							    vBIT(val, 16, 4)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESP(val)\
+							    vBIT(val, 20, 4)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESP(val)\
+							    vBIT(val, 24, 4)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G	    mBIT(31)
+#define	VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G	    mBIT(35)
+/* 0x09da0 */	u64	ratemgmt_anbe_cfg_port[2];
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_RESTART	mBIT(7)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE mBIT(11)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE mBIT(15)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vBIT(val, 16, 4)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val)   vBIT(val, 20, 4)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vBIT(val, 24, 4)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4   mBIT(31)
+#define	VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX	    mBIT(35)
+/* 0x09db0 */	u64	anbe_cfg_port[2];
+#define	VXGE_HAL_ANBE_CFG_PORT_RESET_CFG_REGS(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val)  vBIT(val, 10, 2)
+#define	VXGE_HAL_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val)	    vBIT(val, 14, 2)
+/* 0x09dc0 */	u64	anbe_mgr_ctrl_port[2];
+#define	VXGE_HAL_ANBE_MGR_CTRL_PORT_WE	mBIT(3)
+#define	VXGE_HAL_ANBE_MGR_CTRL_PORT_STROBE		    mBIT(7)
+#define	VXGE_HAL_ANBE_MGR_CTRL_PORT_ADDR(val)		    vBIT(val, 15, 9)
+#define	VXGE_HAL_ANBE_MGR_CTRL_PORT_DATA(val)		    vBIT(val, 32, 32)
+	u8	unused09de0[0x09de0 - 0x09dd0];
+
+/* 0x09de0 */	u64	anbe_fw_mstr_port[2];
+#define	VXGE_HAL_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES   mBIT(3)
+#define	VXGE_HAL_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES	    mBIT(7)
+/* 0x09df0 */	u64	anbe_hwfsm_gen_status_port[2];
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD\
+							    mBIT(3)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME\
+							    mBIT(7)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD\
+							    mBIT(11)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME\
+							    mBIT(15)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val)\
+							    vBIT(val, 18, 6)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED\
+							    mBIT(27)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_PARALLEL_DETECT_FAULT\
+							    mBIT(31)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED\
+							    mBIT(35)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE\
+							    mBIT(39)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_NP_BEFORE_BP\
+							    mBIT(43)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_AN_COMPL_BEFORE_BP\
+							    mBIT(47)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_AN_COMPL_BEFORE_NP\
+							    mBIT(51)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_MODE_WHEN_AN_COMPL\
+							    mBIT(55)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val)\
+							    vBIT(val, 56, 4)
+#define	VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val)\
+							    vBIT(val, 60, 4)
+/* 0x09e00 */	u64	anbe_hwfsm_bp_status_port[2];
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE	mBIT(32)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY	mBIT(33)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE	mBIT(40)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE	mBIT(41)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE	mBIT(42)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val)\
+							    vBIT(val, 43, 5)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP   mBIT(48)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK  mBIT(49)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT mBIT(50)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR mBIT(51)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE mBIT(53)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val)\
+							    vBIT(val, 54, 5)
+#define	VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\
+							    vBIT(val, 59, 5)
+/* 0x09e10 */	u64	anbe_hwfsm_np_status_port[2];
+#define	VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val)\
+							    vBIT(val, 32, 32)
+	u8	unused09e30[0x09e30 - 0x09e20];
+
+/* 0x09e30 */	u64	antp_gen_cfg_port[2];
+/* 0x09e40 */	u64	antp_hwfsm_gen_status_port[2];
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G	mBIT(3)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G	mBIT(7)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val)\
+							    vBIT(val, 10, 6)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_TIMEOUT	mBIT(19)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE	mBIT(23)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP\
+							    mBIT(27)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP	mBIT(31)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE\
+							    mBIT(35)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_MESSAGE_CODE_10G_1K\
+							    mBIT(39)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD	mBIT(43)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD	mBIT(47)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE\
+							    mBIT(51)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE	mBIT(55)
+#define	VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN mBIT(59)
+/* 0x09e50 */	u64	antp_hwfsm_bp_status_port[2];
+#define	VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP	mBIT(0)
+#define	VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK	mBIT(1)
+#define	VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF	mBIT(2)
+#define	VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP	mBIT(3)
+#define	VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val)\
+								vBIT(val, 4, 7)
+#define	VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\
+								vBIT(val, 11, 5)
+/* 0x09e60 */	u64	antp_hwfsm_xnp_status_port[2];
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP	mBIT(0)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK	mBIT(1)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP	mBIT(2)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2	mBIT(3)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE	mBIT(4)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val)\
+							    vBIT(val, 5, 11)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val)\
+							    vBIT(val, 32, 16)
+/* 0x09e70 */	u64	mdio_mgr_access_port[2];
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE	    mBIT(3)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(val)	    vBIT(val, 5, 3)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(val)	    vBIT(val, 11, 5)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(val)		    vBIT(val, 32, 16)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val)	    vBIT(val, 49, 2)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_PREAMBLE		    mBIT(51)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(val)	    vBIT(val, 55, 5)
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO	    mBIT(63)
+	u8	unused09ea0[0x09ea0 - 0x09e80];
+
+/* 0x09ea0 */	u64	mdio_gen_cfg_port[2];
+
+	u8	unused0a200[0x0a200 - 0x09eb0];
+
+/* 0x0a200 */	u64	xmac_vsport_choices_vh[17];
+#define	VXGE_HAL_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val)  vBIT(val, 0, 17)
+	u8	unused0a400[0x0a400 - 0x0a288];
+
+/* 0x0a400 */	u64	rx_thresh_cfg_vp[17];
+#define	VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_0(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_1(val)	    vBIT(val, 24, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_2(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_3(val)	    vBIT(val, 40, 8)
+	u8	unused0ac00[0x0ac00 - 0x0a488];
+
+/* 0x0ac00 */	u64	fau_adaptive_lro_vpath_enable;
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_VPATH_ENABLE_EN(val)	    vBIT(val, 0, 17)
+/* 0x0ac08 */	u64	fau_adaptive_lro_base_sid_vp[17];
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_VALUE(val)    vBIT(val, 2, 6)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_USE_HASH_WIDTH(val)\
+							    vBIT(val, 11, 5)
+
+} vxge_hal_mrpcim_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_MRPCIM_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mrpcim.c b/sys/dev/vxge/vxgehal/vxgehal-mrpcim.c
new file mode 100644
index 000000000000..94337c012479
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mrpcim.c
@@ -0,0 +1,6638 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * vxge_hal_mrpcim_serial_number_get - Returns the serial number
+ * @devh: HAL device handle.
+ *
+ * Return the serial number
+ */
+const u8 *
+vxge_hal_mrpcim_serial_number_get(vxge_hal_device_h devh)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (NULL);
+	}
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (hldev->mrpcim->vpd_data.serial_num);
+}
+
+/*
+ * vxge_hal_mrpcim_vpath_map_get - Returns the assigned vpaths map
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @bar0: Address of BAR0 in PCI config
+ * @func: Function Number
+ *
+ * Returns the assigned vpaths map
+ */
+u64
+vxge_hal_mrpcim_vpath_map_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u8 *bar0,
+    u32 func)
+{
+	u64 val64;
+	vxge_hal_legacy_reg_t *legacy_reg;
+	vxge_hal_toc_reg_t *toc_reg;
+	vxge_hal_vpath_reg_t *vpath_reg;
+
+	vxge_assert(bar0 != NULL);
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "bar0 = 0x"VXGE_OS_STXFMT", func = %d",
+	    (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0, func);
+
+	legacy_reg = (vxge_hal_legacy_reg_t *)
+	    vxge_hal_device_get_legacy_reg(pdev, regh0, bar0);
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &legacy_reg->toc_first_pointer);
+
+	toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64));
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &toc_reg->toc_vpath_pointer[0]);
+
+	vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64));
+
+	val64 = __hal_vpath_vpath_map_get(pdev, regh0, 0, 0, func, vpath_reg);
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (val64);
+}
+
+/*
+ * vxge_hal_mrpcim_pcie_func_mode_set - Set PCI-E function mode
+ * @devh: Device Handle.
+ * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{}
+ *
+ * Set PCI-E function mode.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_pcie_func_mode_set(
+    vxge_hal_device_h devh,
+    vxge_hal_pcie_function_mode_e func_mode)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	u32 fmode;
+	vxge_hal_status_e status;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver("devh = 0x"VXGE_OS_STXFMT
+	    ",func_mode = %d", (ptr_t) devh, func_mode);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	switch (func_mode) {
+	case VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SF1_VP17;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8_VP2;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR17_VP1;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR17_VP1;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR8_VP2;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF17_VP1;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR8_VP2;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR4_VP4;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF2_VP8;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF4_VP4;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MR4_VP4:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR4_VP4;
+		break;
+	case VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2:
+		fmode =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8P_VP2;
+		break;
+	default:
+		vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_TYPE);
+
+		return (VXGE_HAL_ERR_INVALID_TYPE);
+	}
+
+	status = __hal_vpath_pcie_func_mode_set(hldev, hldev->first_vp_id, fmode);
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (status);
+
+}
+
+/*
+ * vxge_hal_mrpcim_fw_upgrade - Upgrade firmware
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @bar0: Address of BAR0 in PCI config
+ * @buffer: Buffer containing F/W image
+ * @length: F/W image length
+ *
+ * Upgrade firmware
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_fw_upgrade(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u8 *bar0,
+    u8 *buffer,
+    u32 length)
+{
+	u64 val64, vpath_mask;
+	u32 host_type, func_id, i;
+	vxge_hal_legacy_reg_t *legacy_reg;
+	vxge_hal_toc_reg_t *toc_reg;
+	vxge_hal_mrpcim_reg_t *mrpcim_reg;
+	vxge_hal_common_reg_t *common_reg;
+	vxge_hal_vpmgmt_reg_t *vpmgmt_reg;
+	vxge_hal_vpath_reg_t *vpath_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((bar0 != NULL) && (buffer != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "bar0 = 0x"VXGE_OS_STXFMT", buffer = 0x"VXGE_OS_STXFMT", "
+	    "length = %d", (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0,
+	    (ptr_t) buffer, length);
+
+	legacy_reg = (vxge_hal_legacy_reg_t *)
+	    vxge_hal_device_get_legacy_reg(pdev, regh0, bar0);
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &legacy_reg->toc_first_pointer);
+
+	toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64));
+
+	val64 =
+	    vxge_os_pio_mem_read64(pdev, regh0, &toc_reg->toc_common_pointer);
+
+	common_reg = (vxge_hal_common_reg_t *) ((void *)(bar0 + val64));
+
+	vpath_mask = vxge_os_pio_mem_read64(pdev, regh0,
+	    &common_reg->vpath_assignments);
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &common_reg->host_type_assignments);
+
+	host_type = (u32)
+	    VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!((vpath_mask) & mBIT(i)))
+			continue;
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &toc_reg->toc_vpmgmt_pointer[i]);
+
+		vpmgmt_reg = (vxge_hal_vpmgmt_reg_t *) ((void *)(bar0 + val64));
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpmgmt_reg->vpath_to_func_map_cfg1);
+
+		func_id = (u32) VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(val64);
+
+		if (!(__hal_device_access_rights_get(host_type, func_id) &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+			return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		}
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &toc_reg->toc_vpath_pointer[i]);
+
+		vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64));
+
+		status = __hal_vpath_fw_upgrade(pdev, regh0,
+		    i, vpath_reg, buffer, length);
+
+		break;
+	}
+
+	if (status == VXGE_HAL_OK) {
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &toc_reg->toc_mrpcim_pointer);
+
+		mrpcim_reg = (vxge_hal_mrpcim_reg_t *) ((void *)(bar0 + val64));
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &mrpcim_reg->sw_reset_cfg1);
+
+		val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE;
+
+		vxge_os_pio_mem_write64(pdev, regh0,
+		    val64,
+		    &mrpcim_reg->sw_reset_cfg1);
+
+		vxge_os_pio_mem_write64(pdev, regh0,
+		    VXGE_HAL_PF_SW_RESET_PF_SW_RESET(
+		    VXGE_HAL_PF_SW_RESET_COMMAND),
+		    &mrpcim_reg->bf_sw_reset);
+
+		vxge_os_mdelay(100);
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_vpath_qos_set - Set the priority, Guaranteed and maximum
+ *				 bandwidth for a vpath.
+ * @devh: HAL device handle.
+ * @vp_id: Vpath Id.
+ * @priority: Priority
+ * @min_bandwidth: Minimum Bandwidth
+ * @max_bandwidth: Maximum Bandwidth
+ *
+ * Set the Guaranteed and maximum bandwidth for a given vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_vpath_qos_set(
+    vxge_hal_device_h devh,
+    u32 vp_id,
+    u32 priority,
+    u32 min_bandwidth,
+    u32 max_bandwidth)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_vpath_qos_config_t config;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT", vp_id = %d, "
+	    "priority = %d, min_bandwidth = %d, max_bandwidth = %d",
+	    (ptr_t) devh, vp_id, priority, min_bandwidth, max_bandwidth);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	if (vp_id >= VXGE_HAL_MAX_VIRTUAL_PATHS) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+
+		return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+	}
+
+	config.priority = priority;
+	config.min_bandwidth = min_bandwidth;
+	config.max_bandwidth = max_bandwidth;
+
+	if ((status = __hal_vpath_qos_config_check(&config)) != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (status == VXGE_HAL_OK) {
+		hldev->header.config.mrpcim_config.vp_qos[vp_id].priority =
+		    priority;
+		hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth =
+		    min_bandwidth;
+		hldev->header.config.mrpcim_config.vp_qos[vp_id].max_bandwidth =
+		    max_bandwidth;
+	}
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_vpath_qos_get - Get the priority, Guaranteed and maximum
+ *				 bandwidth for a vpath.
+ * @devh: HAL device handle.
+ * @vp_id: Vpath Id.
+ * @priority: Buffer to return Priority
+ * @min_bandwidth: Buffer to return Minimum Bandwidth
+ * @max_bandwidth: Buffer to return Maximum Bandwidth
+ *
+ * Get the Guaranteed and maximum bandwidth for a given vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_vpath_qos_get(
+    vxge_hal_device_h devh,
+    u32 vp_id,
+    u32 *priority,
+    u32 *min_bandwidth,
+    u32 *max_bandwidth)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", vp_id = %d, "
+	    "priority = 0x"VXGE_OS_STXFMT", "
+	    "min_bandwidth = 0x"VXGE_OS_STXFMT", "
+	    "max_bandwidth = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, vp_id, (ptr_t) priority,
+	    (ptr_t) min_bandwidth, (ptr_t) max_bandwidth);
+
+	if (vp_id >= VXGE_HAL_MAX_VIRTUAL_PATHS) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+
+		return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+	}
+
+	*priority =
+	    hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth;
+
+	*min_bandwidth =
+	    hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth;
+
+	*max_bandwidth =
+	    hldev->header.config.mrpcim_config.vp_qos[vp_id].max_bandwidth;
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_mrpcim_mdio_access - Access the MDIO device
+ * @devh: HAL Device handle.
+ * @port: Port id
+ * @operation: Type of operation
+ * @device: MMD device address
+ * @addr: MMD address
+ * @data: MMD data
+ *
+ * Access the data from a MDIO Device.
+ *
+ */
+vxge_hal_status_e
+__hal_mrpcim_mdio_access(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 operation,
+    u32 device,
+    u16 addr,
+    u16 *data)
+{
+	u64 val64;
+	u32 prtad;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (data != NULL));
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", operation = %d, "
+	    "device = %d, addr = %d, data = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, operation, device, addr, (ptr_t) data);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	if (device == VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_DTE_XS) {
+		if (port == 0)
+			prtad = hldev->mrpcim->mdio_dte_prtad0;
+		else
+			prtad = hldev->mrpcim->mdio_dte_prtad1;
+	} else {
+		if (port == 0)
+			prtad = hldev->mrpcim->mdio_phy_prtad0;
+		else
+			prtad = hldev->mrpcim->mdio_phy_prtad1;
+	}
+
+	val64 = VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(operation) |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(device) |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(addr) |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(*data) |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(0) |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_PREAMBLE |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(prtad) |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->mdio_mgr_access_port[port]);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mdio_mgr_access_port[port],
+	    0,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE |
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO,
+	    hldev->header.config.device_poll_millis);
+
+	if ((status == VXGE_HAL_OK) &&
+	    ((operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ_INCR) ||
+	    (operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ) ||
+	    (operation ==
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ_INCR) ||
+	    (operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ))) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->mdio_mgr_access_port[port]);
+
+		*data = (u16) VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(val64);
+
+	} else {
+		*data = 0;
+	}
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_intr_enable - Enable the interrupts on mrpcim.
+ * @devh: HAL device handle.
+ *
+ * Enable mrpcim interrupts
+ *
+ * See also: vxge_hal_mrpcim_intr_disable().
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_intr_enable(vxge_hal_device_h devh)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_mrpcim_reg_t *mrpcim_reg;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	mrpcim_reg = hldev->mrpcim_reg;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->ini_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dma_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tgt_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->config_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->crdt_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mrpcim_general_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pll_errors_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mrpcim_ppif_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dbecc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->general_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcipif_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pda_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcc_error_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->lso_error_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->sm_error_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rtdma_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rc_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdrm_sm_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdcm_sm_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdwm_sm_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rda_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rda_ecc_db_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rqa_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->frf_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rocrc_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde0_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde1_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde2_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde3_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wrdma_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3cmct_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3cmct_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gsscc_err_reg);
+
+	for (i = 0; i < 3; i++) {
+
+		VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gssc_err0_reg[i]);
+
+		VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gssc_err1_reg[i]);
+
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcmg1_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gxtmc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcp_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cmc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcmg2_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cml_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cml_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cmu_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cmu_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->psscc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg1_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pxtmc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cp_exc_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cp_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg2_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dam_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg3_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xmac_gen_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xgxs_gen_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->asic_ntwk_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xgmac_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_ecc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_various_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->txmac_gen_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->txmac_ecc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tmac_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_fb_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_fb_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->grocrc_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->fau_ecc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mc_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3fbct_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3fbct_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->orp_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->ptm_alarm_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tpa_error_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tpa_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->kdfc_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->doorbell_int_status);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tim_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_exc_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err2_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err3_reg);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_int_status);
+
+	vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &mrpcim_reg->mrpcim_general_int_status);
+
+	/* unmask interrupts */
+	val64 = VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR |
+	    VXGE_HAL_INI_ERRORS_REG_INI_BUF_DB_ERR |
+	    VXGE_HAL_INI_ERRORS_REG_INI_DATA_OVERFLOW |
+	    VXGE_HAL_INI_ERRORS_REG_INI_HDR_OVERFLOW;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ini_errors_mask);
+
+	val64 = VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR |
+	    VXGE_HAL_DMA_ERRORS_REG_WRARB_FSM_ERR |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW |
+	    VXGE_HAL_DMA_ERRORS_REG_DBLGEN_FSM_ERR |
+	    VXGE_HAL_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR |
+	    VXGE_HAL_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dma_errors_mask);
+
+	val64 = VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR |
+	    VXGE_HAL_TGT_ERRORS_REG_TGT_CPL_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tgt_errors_mask);
+
+	val64 = VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR |
+	    VXGE_HAL_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR |
+	    VXGE_HAL_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT |
+	    VXGE_HAL_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT |
+	    VXGE_HAL_CONFIG_ERRORS_REG_CFGM_FSM_ERR |
+	    VXGE_HAL_CONFIG_ERRORS_REG_RIC_FSM_ERR |
+	    VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TIMEOUT |
+	    VXGE_HAL_CONFIG_ERRORS_REG_PIFM_FSM_ERR |
+	    VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR |
+	    VXGE_HAL_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->config_errors_mask);
+
+	val64 = VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR |
+	    VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL |
+	    VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL |
+	    VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL |
+	    VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR |
+	    VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL |
+	    VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL |
+	    VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->crdt_errors_mask);
+
+	val64 = VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_SW_RESET |
+	    VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->mrpcim_general_errors_mask);
+
+	val64 = VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL |
+	    VXGE_HAL_PLL_ERRORS_REG_CORE_FB_PLL_OOL |
+	    VXGE_HAL_PLL_ERRORS_REG_CORE_X_PLL_OOL;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pll_errors_mask);
+
+	val64 = VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT |
+	    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT |
+	    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT |
+	    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT |
+	    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT |
+	    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_MRPCIM_GENERAL_ERRORS_GENERAL_INT |
+	    VXGE_HAL_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->mrpcim_ppif_int_mask);
+
+	val64 = VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR |
+	    VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR |
+	    VXGE_HAL_DBECC_ERR_REG_PCI_P_HDR_DB_ERR |
+	    VXGE_HAL_DBECC_ERR_REG_PCI_P_DATA_DB_ERR |
+	    VXGE_HAL_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR |
+	    VXGE_HAL_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dbecc_err_mask);
+
+	val64 = VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->general_err_mask);
+
+	val64 = VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT |
+	    VXGE_HAL_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcipif_int_mask);
+
+	val64 = VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pda_alarm_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 8; i++) {
+		val64 |= VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(i) |
+		    VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(i) |
+		    VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(i) |
+		    VXGE_HAL_PCC_ERROR_REG_PCC_PCC_SERR(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcc_error_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 8; i++) {
+		val64 |= VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->lso_error_mask);
+
+	val64 = VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->sm_error_mask);
+
+	val64 = VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT |
+	    VXGE_HAL_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT |
+	    VXGE_HAL_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT |
+	    VXGE_HAL_RTDMA_INT_STATUS_SM_ERROR_SM_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rtdma_int_mask);
+
+	val64 = VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR |
+	    VXGE_HAL_RC_ALARM_REG_FTC_SM_PHASE_ERR |
+	    VXGE_HAL_RC_ALARM_REG_BTDWM_SM_ERR |
+	    VXGE_HAL_RC_ALARM_REG_BTC_SM_ERR |
+	    VXGE_HAL_RC_ALARM_REG_BTDCM_SM_ERR |
+	    VXGE_HAL_RC_ALARM_REG_BTDRM_SM_ERR |
+	    VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR |
+	    VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR |
+	    VXGE_HAL_RC_ALARM_REG_RMM_SM_ERR |
+	    VXGE_HAL_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rc_alarm_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 17; i++) {
+		val64 |= VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdrm_sm_err_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 17; i++) {
+		val64 |= VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdcm_sm_err_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 17; i++) {
+		val64 |= VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdwm_sm_err_mask);
+
+	val64 = VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM |
+	    VXGE_HAL_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR |
+	    VXGE_HAL_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR |
+	    VXGE_HAL_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR |
+	    VXGE_HAL_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR |
+	    VXGE_HAL_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_err_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 17; i++) {
+		val64 |= VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_ecc_db_mask);
+
+	val64 = VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rqa_err_mask);
+
+	val64 = 0;
+
+	for (i = 0; i < 17; i++) {
+		val64 |= VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(i);
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->frf_alarm_mask);
+
+	val64 = VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB |
+	    VXGE_HAL_ROCRC_ALARM_REG_NOA_NMA_SM_ERR |
+	    VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB |
+	    VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB |
+	    VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB |
+	    VXGE_HAL_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rocrc_alarm_mask);
+
+	val64 = VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR |
+	    VXGE_HAL_WDE0_ALARM_REG_WDE0_PRM_SM_ERR |
+	    VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_SM_ERR |
+	    VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_CMD_ERR |
+	    VXGE_HAL_WDE0_ALARM_REG_WDE0_PCR_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde0_alarm_mask);
+
+	val64 = VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR |
+	    VXGE_HAL_WDE1_ALARM_REG_WDE1_PRM_SM_ERR |
+	    VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_SM_ERR |
+	    VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_CMD_ERR |
+	    VXGE_HAL_WDE1_ALARM_REG_WDE1_PCR_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde1_alarm_mask);
+
+	val64 = VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR |
+	    VXGE_HAL_WDE2_ALARM_REG_WDE2_PRM_SM_ERR |
+	    VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_SM_ERR |
+	    VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_CMD_ERR |
+	    VXGE_HAL_WDE2_ALARM_REG_WDE2_PCR_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde2_alarm_mask);
+
+	val64 = VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR |
+	    VXGE_HAL_WDE3_ALARM_REG_WDE3_PRM_SM_ERR |
+	    VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_SM_ERR |
+	    VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_CMD_ERR |
+	    VXGE_HAL_WDE3_ALARM_REG_WDE3_PCR_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde3_alarm_mask);
+
+	val64 = VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_RDA_ERR_RDA_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT |
+	    VXGE_HAL_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wrdma_int_mask);
+
+	val64 = VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR |
+	    VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_DECC |
+	    VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC |
+	    VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_err_mask);
+
+	val64 = VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_int_mask);
+
+	val64 = VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(0x3) |
+	    VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(0x3f) |
+	    VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2STE_UFLOW_ERR |
+	    VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2TTE_UFLOW_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gsscc_err_mask);
+
+	for (i = 0; i < 3; i++) {
+
+		val64 = VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(0xff) |
+		    VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(0xf) |
+		    VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(0x3) |
+		    VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(0x3f);
+
+		VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+		    &mrpcim_reg->gssc_err0_mask[i]);
+
+		val64 = VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SCREQ_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_R_WN_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_R_WN_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_OFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_R_WN_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_UFLOW_ERR |
+		    VXGE_HAL_GSSC_ERR1_REG_SSCC_SCRESP_ERR;
+
+		VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+		    &mrpcim_reg->gssc_err1_mask[i]);
+
+	}
+
+	val64 = VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT |
+	    VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT |
+	    VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT |
+	    VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT |
+	    VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT |
+	    VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT |
+	    VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg1_int_mask);
+
+	val64 = VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(0xf) |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR |
+	    VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gxtmc_err_mask);
+
+	val64 = VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR |
+	    VXGE_HAL_GCP_ERR_REG_CP_STC2CP_FIFO_ERR |
+	    VXGE_HAL_GCP_ERR_REG_CP_STE2CP_FIFO_ERR |
+	    VXGE_HAL_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcp_err_mask);
+
+	val64 = VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cmc_err_mask);
+
+	val64 = VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT |
+	    VXGE_HAL_GCMG2_INT_STATUS_GCP_ERR_GCP_INT |
+	    VXGE_HAL_GCMG2_INT_STATUS_CMC_ERR_CMC_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg2_int_mask);
+
+	val64 = VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->g3ifcmd_cml_err_mask);
+
+	val64 = VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->g3ifcmd_cml_int_mask);
+
+	val64 = VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->g3ifcmd_cmu_err_mask);
+
+	val64 = VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->g3ifcmd_cmu_int_mask);
+
+	val64 = VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR |
+	    VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2TTE_OFLOW_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->psscc_err_mask);
+
+	val64 = VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->pcmg1_int_mask);
+
+	val64 = VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(0x3) |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR |
+	    VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pxtmc_err_mask);
+
+	val64 = VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT |
+	    VXGE_HAL_CP_EXC_REG_CP_CP_SERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_exc_mask);
+
+	val64 = VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(0xff) |
+	    VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(0x3) |
+	    VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_DB_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_DB_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_DB_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_DMA2CP_DB_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_MP2CP_DB_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_QCC2CP_DB_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(0x3) |
+	    VXGE_HAL_CP_ERR_REG_CP_H2L2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_STC2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_STE2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_TTE2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_CP2DMA_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_DAM2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_MP2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_QCC2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_DMA2CP_FIFO_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR |
+	    VXGE_HAL_CP_ERR_REG_CP_PIFT_CREDIT_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_err_mask);
+
+	val64 = VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT |
+	    VXGE_HAL_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT |
+	    VXGE_HAL_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg2_int_mask);
+
+	val64 = VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_DB_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_DB_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_DB_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_DB_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_HPRD_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_LPRD_0_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_LPRD_1_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_OVERFLOW_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_OVERFLOW_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_OVERFLOW_ERR |
+	    VXGE_HAL_DAM_ERR_REG_DAM_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dam_err_mask);
+
+	val64 = VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg3_int_mask);
+
+	val64 = VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(0x3) |
+	    VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(0x3) |
+	    VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(0x3) |
+	    VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(0x3) |
+	    VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(0x3) |
+	    VXGE_HAL_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xmac_gen_err_mask);
+
+	val64 = VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgxs_gen_err_mask);
+
+	val64 = VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN |
+	    VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP |
+	    VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN |
+	    VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP |
+	    VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT |
+	    VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->asic_ntwk_err_mask);
+
+	val64 = VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT |
+	    VXGE_HAL_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT |
+	    VXGE_HAL_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgmac_int_mask);
+
+	val64 =
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(0xf) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(0xf) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(0xf) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(0x3) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(0x3) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(0x3f) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(0x7) |
+	    VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->rxmac_ecc_err_mask);
+
+	val64 = VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR |
+	    VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR |
+	    VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR |
+	    VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->rxmac_various_err_mask);
+
+	val64 = VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT |
+	    VXGE_HAL_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxmac_int_mask);
+
+	val64 = VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->txmac_gen_err_mask);
+
+	val64 = VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR |
+	    VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR |
+	    VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR |
+	    VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR |
+	    VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR |
+	    VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR |
+	    VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->txmac_ecc_err_mask);
+
+	val64 = VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT |
+	    VXGE_HAL_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tmac_int_mask);
+
+	val64 = VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->g3ifcmd_fb_err_mask);
+
+	val64 = VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
+	    &mrpcim_reg->g3ifcmd_fb_int_mask);
+
+	val64 = VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A |
+	    VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B |
+	    VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR |
+	    VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 |
+	    VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 |
+	    VXGE_HAL_MC_ERR_REG_MC_SM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_err_mask);
+
+	val64 = VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR |
+	    VXGE_HAL_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->grocrc_alarm_mask);
+
+	val64 = VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(0x3) |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(0x3) |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(0x3) |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(0x3) |
+	    VXGE_HAL_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->fau_ecc_err_mask);
+
+	val64 = VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT |
+	    VXGE_HAL_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT |
+	    VXGE_HAL_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_int_mask);
+
+	val64 = VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR |
+	    VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC |
+	    VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC |
+	    VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_err_mask);
+
+	val64 = VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_int_mask);
+
+	val64 = VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR |
+	    VXGE_HAL_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->orp_err_mask);
+
+	val64 = VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR |
+	    VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR |
+	    VXGE_HAL_PTM_ALARM_REG_XFMD_RD_FIFO_ERR |
+	    VXGE_HAL_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR |
+	    VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(0x3);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ptm_alarm_mask);
+
+	val64 = VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM |
+	    VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_error_mask);
+
+	val64 = VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT |
+	    VXGE_HAL_TPA_INT_STATUS_PTM_ALARM_PTM_INT |
+	    VXGE_HAL_TPA_INT_STATUS_TPA_ERROR_TPA_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_int_mask);
+
+	val64 = VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR |
+	    VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->kdfc_err_mask);
+
+	val64 = VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->doorbell_int_mask);
+
+	val64 = VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR |
+	    VXGE_HAL_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tim_err_mask);
+
+	val64 = VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT |
+	    VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT |
+	    VXGE_HAL_MSG_EXC_REG_MP_MXP_SERR |
+	    VXGE_HAL_MSG_EXC_REG_UP_UXP_SERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_exc_mask);
+
+	val64 = VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR |
+	    VXGE_HAL_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err_mask);
+
+	val64 =
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR |
+	    VXGE_HAL_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err2_mask);
+
+	val64 = VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 |
+	    VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 |
+	    VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err3_mask);
+
+	val64 = VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT |
+	    VXGE_HAL_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT |
+	    VXGE_HAL_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT |
+	    VXGE_HAL_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT |
+	    VXGE_HAL_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_int_mask);
+
+	val64 = VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCI_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_XMAC_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TMAC_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_FBMC_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TPA_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT |
+	    VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_MSG_INT;
+
+	vxge_hal_pio_mem_write32_upper(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(~val64, 0),
+	    &mrpcim_reg->mrpcim_general_int_mask);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_intr_disable - Disable the interrupts on mrpcim.
+ * @devh: HAL device handle.
+ *
+ * Disable mrpcim interrupts
+ *
+ * See also: vxge_hal_mrpcim_intr_enable().
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_intr_disable(vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_mrpcim_reg_t *mrpcim_reg;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	mrpcim_reg = hldev->mrpcim_reg;
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->ini_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dma_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tgt_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->config_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->crdt_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mrpcim_general_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pll_errors_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mrpcim_ppif_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dbecc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->general_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcipif_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pda_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcc_error_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->lso_error_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->sm_error_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rtdma_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rc_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdrm_sm_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdcm_sm_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdwm_sm_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rda_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rda_ecc_db_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rqa_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->frf_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rocrc_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde0_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde1_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde2_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde3_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wrdma_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3cmct_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3cmct_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gsscc_err_mask);
+
+	for (i = 0; i < 3; i++) {
+
+		VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gssc_err0_mask[i]);
+
+		VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gssc_err1_mask[i]);
+
+	}
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcmg1_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gxtmc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcp_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cmc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcmg2_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cml_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cml_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cmu_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cmu_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->psscc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg1_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pxtmc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cp_exc_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cp_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg2_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dam_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg3_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xmac_gen_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xgxs_gen_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->asic_ntwk_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xgmac_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_ecc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_various_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->txmac_gen_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->txmac_ecc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tmac_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_fb_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_fb_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->grocrc_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->fau_ecc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mc_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3fbct_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3fbct_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->orp_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->ptm_alarm_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tpa_error_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tpa_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->kdfc_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->doorbell_int_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tim_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_exc_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err2_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err3_mask);
+
+	VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &mrpcim_reg->mrpcim_general_int_mask);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_reset - Reset the entire device.
+ * @devh: HAL device handle.
+ *
+ * Soft-reset the device, reset the device stats except reset_cnt.
+ *
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_reset(vxge_hal_device_h devh)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (!hldev->header.is_initialized)
+		return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+
+	if (hldev->device_resetting == 1) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_RESET_IN_PROGRESS);
+
+		return (VXGE_HAL_ERR_RESET_IN_PROGRESS);
+	}
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    hldev->first_vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN,
+	    0);
+
+	vxge_os_mdelay(100);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->sw_reset_cfg1);
+
+	val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->sw_reset_cfg1);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_PF_SW_RESET_PF_SW_RESET(
+	    VXGE_HAL_PF_SW_RESET_COMMAND),
+	    &hldev->mrpcim_reg->bf_sw_reset);
+
+	hldev->stats.sw_dev_info_stats.soft_reset_cnt++;
+
+	hldev->device_resetting = 1;
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, VXGE_HAL_PENDING);
+
+	return (VXGE_HAL_PENDING);
+}
+
+/*
+ * vxge_hal_mrpcim_reset_poll - Poll the device for reset complete.
+ * @devh: HAL device handle.
+ *
+ * Soft-reset the device, reset the device stats except reset_cnt.
+ *
+ * After reset is done, will try to re-initialize HW.
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized.
+ * VXGE_HAL_ERR_RESET_FAILED - Reset failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_reset_poll(vxge_hal_device_h devh)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d", __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (!hldev->header.is_initialized) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+		return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED);
+	}
+
+	if ((status = __hal_device_reg_addr_get(hldev)) != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		hldev->device_resetting = 0;
+		return (status);
+	}
+
+	__hal_device_id_get(hldev);
+
+	__hal_device_host_info_get(hldev);
+
+	hldev->hw_is_initialized = 0;
+
+	hldev->device_resetting = 0;
+
+	vxge_os_memzero(hldev->mrpcim->mrpcim_stats,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	vxge_os_memzero(&hldev->mrpcim->mrpcim_stats_sav,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	status = __hal_mrpcim_mac_configure(hldev);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_mrpcim_lag_configure(hldev);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mdio_gen_cfg_port[0]);
+
+	hldev->mrpcim->mdio_phy_prtad0 =
+	    (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mdio_gen_cfg_port[1]);
+
+	hldev->mrpcim->mdio_phy_prtad1 =
+	    (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xgxs_static_cfg_port[0]);
+
+	hldev->mrpcim->mdio_dte_prtad0 =
+	    (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xgxs_static_cfg_port[1]);
+
+	hldev->mrpcim->mdio_dte_prtad1 =
+	    (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    hldev->mrpcim->mrpcim_stats_block->dma_addr,
+	    &hldev->mrpcim_reg->mrpcim_stats_start_host_addr);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    hldev->vpath_assignments,
+	    &hldev->mrpcim_reg->rxmac_authorize_all_addr);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    hldev->vpath_assignments,
+	    &hldev->mrpcim_reg->rxmac_authorize_all_vid);
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    hldev->first_vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END,
+	    0);
+
+	(void) vxge_hal_device_reset_poll(devh);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_mrpcim_xpak_counter_check -  check the Xpak error count and log the msg
+ * @hldev: pointer to __hal_device_t structure
+ * @port: Port number
+ * @type:  xpak stats error type
+ * @value: xpak stats value
+ *
+ * It is used to log the error message based on the xpak stats value
+ * Return value:
+ * None
+ */
+void
+__hal_mrpcim_xpak_counter_check(__hal_device_t *hldev,
+    u32 port, u32 type, u32 value)
+{
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "hldev = 0x"VXGE_OS_STXFMT", port = %d, type = %d, value = %d",
+	    (ptr_t) hldev, port, type, value);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return;
+
+	}
+
+	/*
+	 * If the value is high for three consecutive cylce,
+	 * log a error message
+	 */
+	if (value == 3) {
+		switch (type) {
+		case VXGE_HAL_XPAK_ALARM_EXCESS_TEMP:
+			hldev->mrpcim->xpak_stats[port].excess_temp = 0;
+
+			/*
+			 * Notify the ULD on Excess Xpak temperature alarm msg
+			 */
+			if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) {
+				g_vxge_hal_driver->uld_callbacks.xpak_alarm_log(
+				    hldev->header.upper_layer_data,
+				    port,
+				    VXGE_HAL_XPAK_ALARM_EXCESS_TEMP);
+			}
+			break;
+		case VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT:
+			hldev->mrpcim->xpak_stats[port].excess_bias_current = 0;
+
+			/*
+			 * Notify the ULD on Excess  xpak bias current alarm msg
+			 */
+			if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) {
+				g_vxge_hal_driver->uld_callbacks.xpak_alarm_log(
+				    hldev->header.upper_layer_data,
+				    port,
+				    VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT);
+			}
+			break;
+		case VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT:
+			hldev->mrpcim->xpak_stats[port].excess_laser_output = 0;
+
+			/*
+			 * Notify the ULD on Excess Xpak Laser o/p power
+			 * alarm msg
+			 */
+			if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) {
+				g_vxge_hal_driver->uld_callbacks.xpak_alarm_log(
+				    hldev->header.upper_layer_data,
+				    port,
+				    VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT);
+			}
+			break;
+		default:
+			vxge_hal_info_log_stats("%s",
+			    "Incorrect XPAK Alarm type");
+		}
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_mrpcim_xpak_stats_poll -  Poll and update the Xpak error count.
+ * @devh: HAL device handle
+ * @port: Port number
+ *
+ * It is used to update the xpak stats value
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xpak_stats_poll(
+    vxge_hal_device_h devh, u32 port)
+{
+	u16 val;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("hldev = 0x"VXGE_OS_STXFMT", port = %d",
+	    (ptr_t) hldev, port);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	/* Loading the DOM register to MDIO register */
+
+	val = 0;
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT,
+	    &val);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT,
+	    &val);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	/*
+	 * Reading the Alarm flags
+	 */
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG,
+	    &val);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (val &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_HIGH) {
+		hldev->mrpcim->xpak_stats[port].alarm_transceiver_temp_high++;
+		hldev->mrpcim->xpak_stats[port].excess_temp++;
+		__hal_mrpcim_xpak_counter_check(hldev, port,
+		    VXGE_HAL_XPAK_ALARM_EXCESS_TEMP,
+		    hldev->mrpcim->xpak_stats[port].excess_temp);
+	} else {
+		hldev->mrpcim->xpak_stats[port].excess_temp = 0;
+	}
+
+	if (val &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_LOW) {
+		hldev->mrpcim->xpak_stats[port].alarm_transceiver_temp_low++;
+	}
+
+	if (val &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_HIGH) {
+		hldev->mrpcim->xpak_stats[port].alarm_laser_bias_current_high++;
+		hldev->mrpcim->xpak_stats[port].excess_bias_current++;
+		__hal_mrpcim_xpak_counter_check(hldev, port,
+		    VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT,
+		    hldev->mrpcim->xpak_stats[port].excess_bias_current);
+	} else {
+		hldev->mrpcim->xpak_stats[port].excess_bias_current = 0;
+	}
+
+	if (val &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_LOW) {
+		hldev->mrpcim->xpak_stats[port].alarm_laser_bias_current_low++;
+	}
+
+	if (val &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_HIGH) {
+		hldev->mrpcim->xpak_stats[port].alarm_laser_output_power_high++;
+		hldev->mrpcim->xpak_stats[port].excess_laser_output++;
+		__hal_mrpcim_xpak_counter_check(hldev, port,
+		    VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT,
+		    hldev->mrpcim->xpak_stats[port].excess_laser_output);
+	} else {
+		hldev->mrpcim->xpak_stats[port].excess_laser_output = 0;
+	}
+
+	if (val &
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_LOW) {
+		hldev->mrpcim->xpak_stats[port].alarm_laser_output_power_low++;
+	}
+
+	/*
+	 * Reading the warning flags
+	 */
+	status = __hal_mrpcim_mdio_access(devh, port,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD,
+	    VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG,
+	    &val);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_HIGH)
+		hldev->mrpcim->xpak_stats[port].warn_transceiver_temp_high++;
+	if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_LOW)
+		hldev->mrpcim->xpak_stats[port].warn_transceiver_temp_low++;
+	if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_HIGH)
+		hldev->mrpcim->xpak_stats[port].warn_laser_bias_current_high++;
+	if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_LOW)
+		hldev->mrpcim->xpak_stats[port].warn_laser_bias_current_low++;
+	if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_HIGH)
+		hldev->mrpcim->xpak_stats[port].warn_laser_output_power_high++;
+	if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_LOW)
+		hldev->mrpcim->xpak_stats[port].warn_laser_output_power_low++;
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_stats_enable - Enable mrpcim statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA mrpcim statistics for the device. The function is to be called
+ * to re-enable the adapter to update stats into the host memory
+ *
+ * See also: vxge_hal_mrpcim_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_enable(vxge_hal_device_h devh)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	vxge_os_memcpy(&hldev->mrpcim->mrpcim_stats_sav,
+	    hldev->mrpcim->mrpcim_stats,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	if (hldev->header.config.stats_read_method ==
+	    VXGE_HAL_STATS_READ_METHOD_DMA) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+		val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE;
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->stats_cfg0);
+
+		val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE(
+		    (1 << (16 - hldev->first_vp_id)));
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->stats_cfg0);
+	} else {
+		status = __hal_mrpcim_stats_get(
+		    hldev,
+		    hldev->mrpcim->mrpcim_stats);
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_stats_disable - Disable mrpcim statistics.
+ * @devh: HAL Device.
+ *
+ * Enable the DMA mrpcim statistics for the device. The function is to be called
+ * to disable the adapter to update stats into the host memory. This function
+ * is not needed to be called, normally.
+ *
+ * See also: vxge_hal_mrpcim_stats_enable()
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_disable(vxge_hal_device_h devh)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+	val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_stats_get - Get the device mrpcim statistics.
+ * @devh: HAL Device.
+ * @stats: mrpcim stats
+ *
+ * Returns the device mrpcim stats for the device.
+ *
+ * See also: vxge_hal_device_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_get(
+    vxge_hal_device_h devh,
+    vxge_hal_mrpcim_stats_hw_info_t *stats)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((hldev != NULL) && (stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "devh = 0x"VXGE_OS_STXFMT", stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) stats);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (hldev->header.config.stats_read_method ==
+	    VXGE_HAL_STATS_READ_METHOD_DMA) {
+
+		status = vxge_hal_device_register_poll(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->stats_cfg0,
+		    0,
+		    VXGE_HAL_STATS_CFG0_STATS_ENABLE(
+		    (1 << (16 - hldev->first_vp_id))),
+		    hldev->header.config.device_poll_millis);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+		val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE;
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+	}
+
+	if (status == VXGE_HAL_OK) {
+		vxge_os_memcpy(stats,
+		    hldev->mrpcim->mrpcim_stats,
+		    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_stats_access - Access the statistics from the given location
+ *			  and offset and perform an operation
+ * @devh: HAL Device handle.
+ * @operation: Operation to be performed
+ * @location: Location (one of vpath id, aggregate or port)
+ * @offset: Offset with in the location
+ * @stat: Pointer to a buffer to return the value
+ *
+ * Get the statistics from the given location and offset.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_access(
+    vxge_hal_device_h devh,
+    u32 operation,
+    u32 location,
+    u32 offset,
+    u64 *stat)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (stat != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", operation = %d, "
+	    "location = %d, offset = %d, stat = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, operation, location, offset, (ptr_t) stat);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	val64 = VXGE_HAL_XMAC_STATS_SYS_CMD_OP(operation) |
+	    VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE |
+	    VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
+	    VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
+
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &hldev->mrpcim_reg->xmac_stats_sys_cmd);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->mrpcim_reg->xmac_stats_sys_cmd);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xmac_stats_sys_cmd,
+	    0,
+	    VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE,
+	    hldev->header.config.device_poll_millis);
+
+	if ((status == VXGE_HAL_OK) && (operation == VXGE_HAL_STATS_OP_READ)) {
+
+		*stat = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->xmac_stats_sys_data);
+
+	} else {
+		*stat = 0;
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_xmac_aggr_stats_get - Get the Statistics on aggregate port
+ * @devh: HAL device handle.
+ * @port: Number of the port (0 or 1)
+ * @aggr_stats: Buffer to return Statistics on aggregate port.
+ *
+ * Get the Statistics on aggregate port
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xmac_aggr_stats_get(vxge_hal_device_h devh,
+    u32 port,
+    vxge_hal_xmac_aggr_stats_t *aggr_stats)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (aggr_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", port = %d, "
+	    "aggr_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, port, (ptr_t) aggr_stats);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_TX_FRMS_OFFSET(port));
+
+	aggr_stats->tx_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_TX_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_TX_DATA_OCTETS_OFFSET(port));
+
+	aggr_stats->tx_data_octets =
+	    VXGE_HAL_STATS_GET_AGGRn_TX_DATA_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_TX_MCAST_FRMS_OFFSET(port));
+
+	aggr_stats->tx_mcast_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_TX_MCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_TX_BCAST_FRMS_OFFSET(port));
+
+	aggr_stats->tx_bcast_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_TX_BCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_TX_DISCARDED_FRMS_OFFSET(port));
+
+	aggr_stats->tx_discarded_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_TX_DISCARDED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_TX_ERRORED_FRMS_OFFSET(port));
+
+	aggr_stats->tx_errored_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_TX_ERRORED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_FRMS_OFFSET(port));
+
+	aggr_stats->rx_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_DATA_OCTETS_OFFSET(port));
+
+	aggr_stats->rx_data_octets =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_DATA_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_MCAST_FRMS_OFFSET(port));
+
+	aggr_stats->rx_mcast_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_MCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_BCAST_FRMS_OFFSET(port));
+
+	aggr_stats->rx_bcast_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_BCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_DISCARDED_FRMS_OFFSET(port));
+
+	aggr_stats->rx_discarded_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_DISCARDED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_ERRORED_FRMS_OFFSET(port));
+
+	aggr_stats->rx_errored_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_ERRORED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_AGGRn_RX_U_SLOW_PROTO_FRMS_OFFSET(port));
+
+	aggr_stats->rx_unknown_slow_proto_frms =
+	    VXGE_HAL_STATS_GET_AGGRn_RX_U_SLOW_PROTO_FRMS(val64);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * vxge_hal_mrpcim_xmac_port_stats_get - Get the Statistics on a port
+ * @devh: HAL device handle.
+ * @port: Number of the port (wire 0, wire 1 or LAG)
+ * @port_stats: Buffer to return Statistics on a port.
+ *
+ * Get the Statistics on port
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xmac_port_stats_get(vxge_hal_device_h devh,
+    u32 port,
+    vxge_hal_xmac_port_stats_t *port_stats)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert((devh != NULL) && (port_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", port = %d, "
+	    "port_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, port, (ptr_t) port_stats);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(port));
+
+	port_stats->tx_ttl_frms =
+	    VXGE_HAL_STATS_GET_PORTn_TX_TTL_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(port));
+
+	port_stats->tx_ttl_octets =
+	    VXGE_HAL_STATS_GET_PORTn_TX_TTL_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_DATA_OCTETS_OFFSET(port));
+
+	port_stats->tx_data_octets =
+	    VXGE_HAL_STATS_GET_PORTn_TX_DATA_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_MCAST_FRMS_OFFSET(port));
+
+	port_stats->tx_mcast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_TX_MCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_BCAST_FRMS_OFFSET(port));
+
+	port_stats->tx_bcast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_TX_BCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_UCAST_FRMS_OFFSET(port));
+
+	port_stats->tx_ucast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_TX_UCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_TAGGED_FRMS_OFFSET(port));
+
+	port_stats->tx_tagged_frms =
+	    VXGE_HAL_STATS_GET_PORTn_TX_TAGGED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_VLD_IP_OFFSET(port));
+
+	port_stats->tx_vld_ip =
+	    VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_VLD_IP_OCTETS_OFFSET(port));
+
+	port_stats->tx_vld_ip_octets =
+	    VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_ICMP_OFFSET(port));
+
+	port_stats->tx_icmp =
+	    VXGE_HAL_STATS_GET_PORTn_TX_ICMP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_TCP_OFFSET(port));
+
+	port_stats->tx_tcp =
+	    VXGE_HAL_STATS_GET_PORTn_TX_TCP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_RST_TCP_OFFSET(port));
+
+	port_stats->tx_rst_tcp =
+	    VXGE_HAL_STATS_GET_PORTn_TX_RST_TCP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_UDP_OFFSET(port));
+
+	port_stats->tx_udp =
+	    VXGE_HAL_STATS_GET_PORTn_TX_UDP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_UNKNOWN_PROTOCOL_OFFSET(port));
+
+	port_stats->tx_unknown_protocol =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_UNKNOWN_PROTOCOL(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_PARSE_ERROR_OFFSET(port));
+
+	port_stats->tx_parse_error =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_PARSE_ERROR(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_PAUSE_CTRL_FRMS_OFFSET(port));
+
+	port_stats->tx_pause_ctrl_frms =
+	    VXGE_HAL_STATS_GET_PORTn_TX_PAUSE_CTRL_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_LACPDU_FRMS_OFFSET(port));
+
+	port_stats->tx_lacpdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_LACPDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_MRKR_PDU_FRMS_OFFSET(port));
+
+	port_stats->tx_marker_pdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_PDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_MRKR_RESP_PDU_FRMS_OFFSET(port));
+
+	port_stats->tx_marker_resp_pdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_RESP_PDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_DROP_IP_OFFSET(port));
+
+	port_stats->tx_drop_ip =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_DROP_IP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR1_MATCH_OFFSET(port));
+
+	port_stats->tx_xgmii_char1_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR1_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR2_MATCH_OFFSET(port));
+
+	port_stats->tx_xgmii_char2_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR2_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_XGMII_COL1_MATCH_OFFSET(port));
+
+	port_stats->tx_xgmii_column1_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL1_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_XGMII_COL2_MATCH_OFFSET(port));
+
+	port_stats->tx_xgmii_column2_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL2_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_DROP_FRMS_OFFSET(port));
+
+	port_stats->tx_drop_frms =
+	    (u16) VXGE_HAL_STATS_GET_PORTn_TX_DROP_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_TX_ANY_ERR_FRMS_OFFSET(port));
+
+	port_stats->tx_any_err_frms =
+	    (u16) VXGE_HAL_STATS_GET_PORTn_TX_ANY_ERR_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_VLD_FRMS_OFFSET(port));
+
+	port_stats->rx_vld_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_VLD_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_OFFLOAD_FRMS_OFFSET(port));
+
+	port_stats->rx_offload_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_OCTETS_OFFSET(port));
+
+	port_stats->rx_ttl_octets =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_DATA_OCTETS_OFFSET(port));
+
+	port_stats->rx_data_octets =
+	    VXGE_HAL_STATS_GET_PORTn_RX_DATA_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_OFFLOAD_OCTETS_OFFSET(port));
+
+	port_stats->rx_offload_octets =
+	    VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_VLD_MCAST_FRMS_OFFSET(port));
+
+	port_stats->rx_vld_mcast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_VLD_MCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_VLD_BCAST_FRMS_OFFSET(port));
+
+	port_stats->rx_vld_bcast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_VLD_BCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ACC_UCAST_FRMS_OFFSET(port));
+
+	port_stats->rx_accepted_ucast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_ACC_UCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ACC_NUCAST_FRMS_OFFSET(port));
+
+	port_stats->rx_accepted_nucast_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_ACC_NUCAST_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TAGGED_FRMS_OFFSET(port));
+
+	port_stats->rx_tagged_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TAGGED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_LONG_FRMS_OFFSET(port));
+
+	port_stats->rx_long_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_LONG_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_USIZED_FRMS_OFFSET(port));
+
+	port_stats->rx_usized_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_USIZED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_OSIZED_FRMS_OFFSET(port));
+
+	port_stats->rx_osized_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_OSIZED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_FRAG_FRMS_OFFSET(port));
+
+	port_stats->rx_frag_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_FRAG_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_JABBER_FRMS_OFFSET(port));
+
+	port_stats->rx_jabber_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_JABBER_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_64_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_64_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_64_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_65_127_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_65_127_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_65_127_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_128_255_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_128_255_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_128_255_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_256_511_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_256_511_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_256_511_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_512_1023_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_512_1023_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_512_1023_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_1024_1518_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_1024_1518_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_1024_1518_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_1519_4095_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_1519_4095_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_1519_4095_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_4096_81915_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_4096_8191_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_4096_8191_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_8192_MAX_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_8192_max_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_8192_MAX_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TTL_GT_MAX_FRMS_OFFSET(port));
+
+	port_stats->rx_ttl_gt_max_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_TTL_GT_MAX_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_IP_OFFSET(port));
+
+	port_stats->rx_ip = VXGE_HAL_STATS_GET_PORTn_RX_IP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ACC_IP_OFFSET(port));
+
+	port_stats->rx_accepted_ip =
+	    VXGE_HAL_STATS_GET_PORTn_RX_ACC_IP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_IP_OCTETS_OFFSET(port));
+
+	port_stats->rx_ip_octets =
+	    VXGE_HAL_STATS_GET_PORTn_RX_IP_OCTETS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ERR_IP_OFFSET(port));
+
+	port_stats->rx_err_ip =
+	    VXGE_HAL_STATS_GET_PORTn_RX_ERR_IP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ICMP_OFFSET(port));
+
+	port_stats->rx_icmp = VXGE_HAL_STATS_GET_PORTn_RX_ICMP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TCP_OFFSET(port));
+
+	port_stats->rx_tcp = VXGE_HAL_STATS_GET_PORTn_RX_TCP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_UDP_OFFSET(port));
+
+	port_stats->rx_udp = VXGE_HAL_STATS_GET_PORTn_RX_UDP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ERR_TCP_OFFSET(port));
+
+	port_stats->rx_err_tcp = VXGE_HAL_STATS_GET_PORTn_RX_ERR_TCP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_PAUSE_CNT_OFFSET(port));
+
+	port_stats->rx_pause_count =
+	    VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CNT(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_PAUSE_CTRL_FRMS_OFFSET(port));
+
+	port_stats->rx_pause_ctrl_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CTRL_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_UNSUP_CTRL_FRMS_OFFSET(port));
+
+	port_stats->rx_unsup_ctrl_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_UNSUP_CTRL_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_FCS_ERR_FRMS_OFFSET(port));
+
+	port_stats->rx_fcs_err_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_FCS_ERR_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_IN_RNG_LEN_ERR_FRMS_OFFSET(port));
+
+	port_stats->rx_in_rng_len_err_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_IN_RNG_LEN_ERR_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_OUT_RNG_LEN_ERR_FRMS_OFFSET(port));
+
+	port_stats->rx_out_rng_len_err_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_OUT_RNG_LEN_ERR_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_DROP_FRMS_OFFSET(port));
+
+	port_stats->rx_drop_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_DROP_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_DISCARDED_FRMS_OFFSET(port));
+
+	port_stats->rx_discarded_frms =
+	    VXGE_HAL_STATS_GET_PORTn_RX_DISCARDED_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_DROP_IP_OFFSET(port));
+
+	port_stats->rx_drop_ip =
+	    VXGE_HAL_STATS_GET_PORTn_RX_DROP_IP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_DRP_UDP_OFFSET(port));
+
+	port_stats->rx_drop_udp =
+	    VXGE_HAL_STATS_GET_PORTn_RX_DRP_UDP(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_LACPDU_FRMS_OFFSET(port));
+
+	port_stats->rx_lacpdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_LACPDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_MRKR_PDU_FRMS_OFFSET(port));
+
+	port_stats->rx_marker_pdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_PDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_MRKR_RESP_PDU_FRMS_OFFSET(port));
+
+	port_stats->rx_marker_resp_pdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_RESP_PDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_UNKNOWN_PDU_FRMS_OFFSET(port));
+
+	port_stats->rx_unknown_pdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_UNKNOWN_PDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_ILLEGAL_PDU_FRMS_OFFSET(port));
+
+	port_stats->rx_illegal_pdu_frms =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_ILLEGAL_PDU_FRMS(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_FCS_DISCARD_OFFSET(port));
+
+	port_stats->rx_fcs_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_FCS_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_LEN_DISCARD_OFFSET(port));
+
+	port_stats->rx_len_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_LEN_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_SWITCH_DISCARD_OFFSET(port));
+
+	port_stats->rx_switch_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_SWITCH_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_L2_MGMT_DISCARD_OFFSET(port));
+
+	port_stats->rx_l2_mgmt_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_L2_MGMT_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_RPA_DISCARD_OFFSET(port));
+
+	port_stats->rx_rpa_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_RPA_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_TRASH_DISCARD_OFFSET(port));
+
+	port_stats->rx_trash_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_TRASH_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_RTS_DISCARD_OFFSET(port));
+
+	port_stats->rx_rts_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_RTS_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_RED_DISCARD_OFFSET(port));
+
+	port_stats->rx_red_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_RED_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_BUFF_FULL_DISCARD_OFFSET(port));
+
+	port_stats->rx_buff_full_discard =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_BUFF_FULL_DISCARD(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_DATA_ERR_CNT_OFFSET(port));
+
+	port_stats->rx_xgmii_data_err_cnt =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_DATA_ERR_CNT(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_CTRL_ERR_CNT_OFFSET(port));
+
+	port_stats->rx_xgmii_ctrl_err_cnt =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CTRL_ERR_CNT(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_ERR_SYM_OFFSET(port));
+
+	port_stats->rx_xgmii_err_sym =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_ERR_SYM(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR1_MATCH_OFFSET(port));
+
+	port_stats->rx_xgmii_char1_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR1_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR2_MATCH_OFFSET(port));
+
+	port_stats->rx_xgmii_char2_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR2_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_COL1_MATCH_OFFSET(port));
+
+	port_stats->rx_xgmii_column1_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL1_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_XGMII_COL2_MATCH_OFFSET(port));
+
+	port_stats->rx_xgmii_column2_match =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL2_MATCH(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_LOCAL_FAULT_OFFSET(port));
+
+	port_stats->rx_local_fault =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_LOCAL_FAULT(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_REMOTE_FAULT_OFFSET(port));
+
+	port_stats->rx_remote_fault =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_REMOTE_FAULT(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT,
+	    VXGE_HAL_STATS_PORTn_RX_JETTISON_OFFSET(port));
+
+	port_stats->rx_jettison =
+	    (u32) VXGE_HAL_STATS_GET_PORTn_RX_JETTISON(val64);
+
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * vxge_hal_mrpcim_xmac_stats_get - Get the XMAC Statistics
+ * @devh: HAL device handle.
+ * @xmac_stats: Buffer to return XMAC Statistics.
+ *
+ * Get the XMAC Statistics
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_xmac_stats_get(vxge_hal_device_h devh,
+    vxge_hal_mrpcim_xmac_stats_t *xmac_stats)
+{
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((devh != NULL) && (xmac_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "hldev = 0x"VXGE_OS_STXFMT", mrpcim_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) xmac_stats);
+
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	status = vxge_hal_mrpcim_xmac_aggr_stats_get(devh,
+	    0,
+	    &xmac_stats->aggr_stats[0]);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = vxge_hal_mrpcim_xmac_aggr_stats_get(devh,
+	    1,
+	    &xmac_stats->aggr_stats[1]);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	for (i = 0; i < VXGE_HAL_MAC_MAX_PORTS; i++) {
+
+		status = vxge_hal_mrpcim_xmac_port_stats_get(devh,
+		    i,
+		    &xmac_stats->port_stats[i]);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * _hal_mrpcim_stats_get - Get the mrpcim statistics using PIO
+ * @hldev: hal device.
+ * @mrpcim_stats: MRPCIM stats
+ *
+ * Returns the mrpcim stats.
+ *
+ * See also: vxge_hal_mrpcim_stats_enable(), vxge_hal_mrpcim_stats_disable()
+ */
+vxge_hal_status_e
+__hal_mrpcim_stats_get(
+    __hal_device_t *hldev,
+    vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_device_h devh = (vxge_hal_device_h) hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((hldev != NULL) && (mrpcim_stats != NULL));
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "hldev = 0x"VXGE_OS_STXFMT", mrpcim_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, (ptr_t) mrpcim_stats);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mrpcim_debug_stats0);
+
+	mrpcim_stats->pic_ini_rd_drop =
+	    (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(val64);
+
+	mrpcim_stats->pic_ini_wr_drop =
+	    (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(val64);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->mrpcim_debug_stats1_vplane[i]);
+
+		mrpcim_stats->pic_wrcrdtarb_ph_crdt_depleted_vplane[i].
+		    pic_wrcrdtarb_ph_crdt_depleted = (u32)
+		    VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(
+		    val64);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->mrpcim_debug_stats2_vplane[i]);
+
+		mrpcim_stats->pic_wrcrdtarb_pd_crdt_depleted_vplane[i].
+		    pic_wrcrdtarb_pd_crdt_depleted = (u32)
+		    VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(
+		    val64);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->mrpcim_debug_stats3_vplane[i]);
+
+		mrpcim_stats->pic_rdcrdtarb_nph_crdt_depleted_vplane[i].
+		    pic_rdcrdtarb_nph_crdt_depleted = (u32)
+		    VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(
+		    val64);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mrpcim_debug_stats4);
+
+	mrpcim_stats->pic_ini_rd_vpin_drop =
+	    (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(val64);
+
+	mrpcim_stats->pic_ini_wr_vpin_drop =
+	    (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->genstats_count01);
+
+	mrpcim_stats->pic_genstats_count0 =
+	    (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(val64);
+
+	mrpcim_stats->pic_genstats_count1 =
+	    (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->genstats_count23);
+
+	mrpcim_stats->pic_genstats_count2 =
+	    (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(val64);
+
+	mrpcim_stats->pic_genstats_count3 =
+	    (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->genstats_count4);
+
+	mrpcim_stats->pic_genstats_count4 =
+	    (u32) VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->genstats_count5);
+
+	mrpcim_stats->pic_genstats_count5 =
+	    (u32) VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->debug_stats0);
+
+	mrpcim_stats->pci_rstdrop_cpl =
+	    (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(val64);
+
+	mrpcim_stats->pci_rstdrop_msg =
+	    (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->debug_stats1);
+
+	mrpcim_stats->pci_rstdrop_client0 =
+	    (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(val64);
+
+	mrpcim_stats->pci_rstdrop_client1 =
+	    (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->debug_stats2);
+
+	mrpcim_stats->pci_rstdrop_client2 =
+	    (u32) VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(val64);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->debug_stats3_vplane);
+
+		mrpcim_stats->pci_depl_h_vplane[i].pci_depl_cplh =
+		    (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(val64);
+
+		mrpcim_stats->pci_depl_h_vplane[i].pci_depl_nph =
+		    (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(val64);
+
+		mrpcim_stats->pci_depl_h_vplane[i].pci_depl_ph =
+		    (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(val64);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->debug_stats4_vplane);
+
+		mrpcim_stats->pci_depl_d_vplane[i].pci_depl_cpld =
+		    (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(val64);
+
+		mrpcim_stats->pci_depl_d_vplane[i].pci_depl_npd =
+		    (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(val64);
+
+		mrpcim_stats->pci_depl_d_vplane[i].pci_depl_pd =
+		    (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(val64);
+	}
+
+	status = vxge_hal_mrpcim_xmac_aggr_stats_get(hldev,
+	    0,
+	    &mrpcim_stats->xgmac_aggr[0]);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = vxge_hal_mrpcim_xmac_aggr_stats_get(hldev,
+	    1,
+	    &mrpcim_stats->xgmac_aggr[1]);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	for (i = 0; i < VXGE_HAL_MAC_MAX_PORTS; i++) {
+
+		status = vxge_hal_mrpcim_xmac_port_stats_get(hldev,
+		    i,
+		    &mrpcim_stats->xgmac_port[i]);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+	}
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM0_OFFSET);
+
+	mrpcim_stats->xgmac_global_prog_event_gnum0 =
+	    VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM0(val64);
+
+	VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR,
+	    VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM1_OFFSET);
+
+	mrpcim_stats->xgmac_global_prog_event_gnum1 =
+	    VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM1(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->orp_lro_events);
+
+	mrpcim_stats->xgmac_orp_lro_events =
+	    VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->orp_bs_events);
+
+	mrpcim_stats->xgmac_orp_bs_events =
+	    VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->orp_iwarp_events);
+
+	mrpcim_stats->xgmac_orp_iwarp_events =
+	    VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->dbg_stats_tpa_tx_path);
+
+	mrpcim_stats->xgmac_tx_permitted_frms =
+	    (u32) VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->dbg_stat_tx_any_frms);
+
+	mrpcim_stats->xgmac_port0_tx_any_frms =
+	    (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(val64);
+
+	mrpcim_stats->xgmac_port1_tx_any_frms =
+	    (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(val64);
+
+	mrpcim_stats->xgmac_port2_tx_any_frms =
+	    (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->dbg_stat_rx_any_frms);
+
+	mrpcim_stats->xgmac_port0_rx_any_frms =
+	    (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(val64);
+
+	mrpcim_stats->xgmac_port1_rx_any_frms =
+	    (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(val64);
+
+	mrpcim_stats->xgmac_port2_rx_any_frms =
+	    (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(val64);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_stats_clear - Clear the statistics of the device
+ * @devh: HAL Device handle.
+ *
+ * Clear the statistics of the given Device.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_stats_clear(vxge_hal_device_h devh)
+{
+	u32 i;
+	u64 stat;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	vxge_os_memcpy(&hldev->mrpcim->mrpcim_stats_sav,
+	    hldev->mrpcim->mrpcim_stats,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	vxge_os_memzero(hldev->mrpcim->mrpcim_stats,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	vxge_os_memzero(&hldev->stats.sw_dev_err_stats,
+	    sizeof(vxge_hal_device_stats_sw_err_t));
+
+	hldev->stats.sw_dev_info_stats.soft_reset_cnt = 0;
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (!(hldev->vpaths_deployed & mBIT(i)))
+			continue;
+
+		(void) vxge_hal_vpath_stats_clear(
+		    VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
+
+	}
+
+	status = vxge_hal_mrpcim_stats_access(
+	    devh,
+	    VXGE_HAL_STATS_OP_CLEAR_ALL_STATS,
+	    0,
+	    0,
+	    &stat);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_udp_rth_enable - Enable UDP/RTH.
+ * @devh: HAL device handle.
+ *
+ * enable udp rth
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_udp_rth_enable(
+    vxge_hal_device_h devh)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	status = __hal_vpath_udp_rth_set(hldev,
+	    hldev->first_vp_id,
+	    TRUE);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_mrpcim_mac_configure - Initialize mac
+ * @hldev: hal device.
+ *
+ * Initializes mac
+ *
+ */
+vxge_hal_status_e
+__hal_mrpcim_mac_configure(__hal_device_t *hldev)
+{
+	u64 val64;
+	u32 i, port_id;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_mac_config_t *mac_config =
+	&hldev->header.config.mrpcim_config.mac_config;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
+
+		port_id = mac_config->wire_port_config[i].port_id;
+
+		if (mac_config->wire_port_config[i].tmac_en ==
+		    VXGE_HAL_WIRE_PORT_TMAC_DEFAULT) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->mrpcim_reg->txmac_cfg0_port[port_id]);
+
+			if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) {
+				mac_config->wire_port_config[i].tmac_en =
+				    VXGE_HAL_WIRE_PORT_TMAC_ENABLE;
+			} else {
+				mac_config->wire_port_config[i].tmac_en =
+				    VXGE_HAL_WIRE_PORT_TMAC_DISABLE;
+			}
+
+		}
+
+		if (mac_config->wire_port_config[i].rmac_en ==
+		    VXGE_HAL_WIRE_PORT_RMAC_DEFAULT) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]);
+
+			if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) {
+				mac_config->wire_port_config[i].rmac_en =
+				    VXGE_HAL_WIRE_PORT_RMAC_ENABLE;
+			} else {
+				mac_config->wire_port_config[i].rmac_en =
+				    VXGE_HAL_WIRE_PORT_RMAC_DISABLE;
+			}
+
+		}
+
+		if ((!(mac_config->wire_port_config[i].rmac_en)) &&
+		    (!(mac_config->wire_port_config[i].tmac_en)))
+			val64 = 0;
+		else
+			val64 = VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN;
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->xgmac_main_cfg_port[port_id]);
+
+		if (!val64)
+			continue;
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]);
+
+		if (mac_config->wire_port_config[i].rmac_en)
+			val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
+
+		if (mac_config->wire_port_config[i].rmac_strip_fcs !=
+		    VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT) {
+			if (mac_config->wire_port_config[i].rmac_strip_fcs)
+				val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
+		}
+
+		if (mac_config->wire_port_config[i].rmac_discard_pfrm !=
+		    VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT) {
+			if (mac_config->wire_port_config[i].rmac_discard_pfrm)
+				val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
+		}
+
+		if (mac_config->wire_port_config[i].mtu !=
+		    VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU) {
+
+			val64 &=
+			    ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff);
+
+			val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(
+			    mac_config->wire_port_config[i].mtu);
+
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_cfg2_port[port_id]);
+
+		if (mac_config->wire_port_config[i].rmac_prom_en !=
+		    VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT) {
+			if (mac_config->wire_port_config[i].rmac_prom_en)
+				val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_cfg2_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_pause_cfg_port[port_id]);
+
+		if (mac_config->wire_port_config[i].rmac_pause_gen_en !=
+		    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT) {
+			if (mac_config->wire_port_config[i].rmac_pause_gen_en)
+				val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
+
+		}
+
+		if (mac_config->wire_port_config[i].rmac_pause_rcv_en !=
+		    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT) {
+			if (mac_config->wire_port_config[i].rmac_pause_rcv_en)
+				val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
+
+		}
+
+		if (mac_config->wire_port_config[i].rmac_pause_time !=
+		    VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME) {
+			val64 &=
+			    ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(0xffff);
+
+			val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(
+			    mac_config->wire_port_config[i].rmac_pause_time);
+
+		}
+
+		if (mac_config->wire_port_config[i].rmac_pause_time !=
+		    VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT) {
+			if (mac_config->wire_port_config[i].limiter_en)
+				val64 |=
+				    VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN;
+
+		}
+
+		if (mac_config->wire_port_config[i].max_limit !=
+		    VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT) {
+			val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff);
+
+			val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(
+			    mac_config->wire_port_config[i].max_limit);
+
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_pause_cfg_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_link_util_port[port_id]);
+
+		if (mac_config->wire_port_config[i].rmac_util_period !=
+		    VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD) {
+			val64 &=
+			    ~VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(0xf);
+
+			val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(
+			    mac_config->wire_port_config[i].rmac_util_period);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_link_util_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->xgmac_debounce_port[port_id]);
+
+		if (mac_config->wire_port_config[i].link_stability_period !=
+		    VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD) {
+			val64 &=
+			    ~(VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(0xf) |
+			    VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(0xf));
+
+			val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(
+			    mac_config->wire_port_config[i].link_stability_period) |
+			    VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(
+			    mac_config->wire_port_config[i].link_stability_period);
+		}
+
+		if (mac_config->wire_port_config[i].port_stability_period !=
+		    VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD) {
+			val64 &=
+			    ~(VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(0xf) |
+			    VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(0xf));
+
+			val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(
+			    mac_config->wire_port_config[i].port_stability_period) |
+			    VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(
+			    mac_config->wire_port_config[i].port_stability_period);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->xgmac_debounce_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->txmac_cfg0_port[port_id]);
+
+		if (mac_config->wire_port_config[i].tmac_en)
+			val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
+
+		if (mac_config->wire_port_config[i].tmac_pad !=
+		    VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT) {
+			if (mac_config->wire_port_config[i].tmac_pad)
+				val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
+			else
+				val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
+		}
+
+		if (mac_config->wire_port_config[i].tmac_pad_byte !=
+		    VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT) {
+			val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff);
+
+			val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(
+			    mac_config->wire_port_config[i].tmac_pad_byte);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->txmac_cfg0_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->txmac_link_util_port);
+
+		if (mac_config->wire_port_config[i].tmac_util_period !=
+		    VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD) {
+			val64 &=
+			    ~VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(0xf);
+
+			val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(
+			    mac_config->wire_port_config[i].tmac_util_period);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->txmac_link_util_port[port_id]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->ratemgmt_cfg_port);
+
+		if (mac_config->wire_port_config[i].autoneg_mode !=
+		    VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT) {
+
+			val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_MODE(0x3);
+
+			val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_MODE(
+			    mac_config->wire_port_config[i].autoneg_mode);
+		}
+
+		if (mac_config->wire_port_config[i].autoneg_rate !=
+		    VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT) {
+
+			if (mac_config->wire_port_config[i].autoneg_rate)
+				val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_RATE;
+			else
+				val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_RATE;
+
+		}
+
+		if (mac_config->wire_port_config[i].fixed_use_fsm !=
+		    VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT) {
+
+			if (mac_config->wire_port_config[i].fixed_use_fsm)
+				val64 |=
+				    VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM;
+			else
+				val64 &=
+				    ~VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM;
+
+		}
+
+		if (mac_config->wire_port_config[i].antp_use_fsm !=
+		    VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT) {
+
+			if (mac_config->wire_port_config[i].antp_use_fsm)
+				val64 |=
+				    VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM;
+			else
+				val64 &=
+				    ~VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM;
+
+		}
+
+		if (mac_config->wire_port_config[i].anbe_use_fsm !=
+		    VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT) {
+
+			if (mac_config->wire_port_config[i].anbe_use_fsm)
+				val64 |=
+				    VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM;
+			else
+				val64 &=
+				    ~VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM;
+
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->ratemgmt_cfg_port[port_id]);
+
+	}
+
+	if (mac_config->switch_port_config.tmac_en ==
+	    VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->txmac_cfg0_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) {
+			mac_config->switch_port_config.tmac_en =
+			    VXGE_HAL_SWITCH_PORT_TMAC_ENABLE;
+		} else {
+			mac_config->switch_port_config.tmac_en =
+			    VXGE_HAL_SWITCH_PORT_TMAC_DISABLE;
+		}
+
+	}
+
+	if (mac_config->switch_port_config.rmac_en ==
+	    VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_cfg0_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) {
+			mac_config->switch_port_config.rmac_en =
+			    VXGE_HAL_SWITCH_PORT_RMAC_ENABLE;
+		} else {
+			mac_config->switch_port_config.rmac_en =
+			    VXGE_HAL_SWITCH_PORT_RMAC_DISABLE;
+		}
+
+	}
+
+	if (mac_config->switch_port_config.rmac_en ||
+	    mac_config->switch_port_config.tmac_en) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_cfg0_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (mac_config->switch_port_config.rmac_en)
+			val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
+
+		if (mac_config->switch_port_config.rmac_strip_fcs !=
+		    VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT) {
+			if (mac_config->switch_port_config.rmac_strip_fcs)
+				val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
+		}
+
+		if (mac_config->switch_port_config.rmac_discard_pfrm !=
+		    VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT) {
+			if (mac_config->switch_port_config.rmac_discard_pfrm)
+				val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
+		}
+
+		if (mac_config->switch_port_config.mtu !=
+		    VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU) {
+
+			val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff);
+
+			val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(
+			    mac_config->switch_port_config.mtu);
+
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_cfg0_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_cfg2_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (mac_config->switch_port_config.rmac_prom_en !=
+		    VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT) {
+			if (mac_config->switch_port_config.rmac_prom_en)
+				val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_cfg2_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_pause_cfg_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (mac_config->switch_port_config.rmac_pause_gen_en !=
+		    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT) {
+			if (mac_config->switch_port_config.rmac_pause_gen_en)
+				val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
+
+		}
+
+		if (mac_config->switch_port_config.rmac_pause_rcv_en !=
+		    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT) {
+			if (mac_config->switch_port_config.rmac_pause_rcv_en)
+				val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
+
+		}
+
+		if (mac_config->switch_port_config.rmac_pause_time !=
+		    VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME) {
+			val64 &=
+			    ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(0xffff);
+
+			val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(
+			    mac_config->switch_port_config.rmac_pause_time);
+
+		}
+
+		if (mac_config->switch_port_config.rmac_pause_time !=
+		    VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT) {
+			if (mac_config->switch_port_config.limiter_en)
+				val64 |=
+				    VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN;
+
+		}
+
+		if (mac_config->switch_port_config.max_limit !=
+		    VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT) {
+			val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff);
+
+			val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(
+			    mac_config->switch_port_config.max_limit);
+
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_pause_cfg_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rxmac_link_util_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (mac_config->switch_port_config.rmac_util_period !=
+		    VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD) {
+			val64 &=
+			    ~VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(0xf);
+
+			val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(
+			    mac_config->switch_port_config.rmac_util_period);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rxmac_link_util_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->txmac_cfg0_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		if (mac_config->switch_port_config.tmac_en)
+			val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
+
+		if (mac_config->switch_port_config.tmac_pad !=
+		    VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT) {
+			if (mac_config->switch_port_config.tmac_pad)
+				val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
+			else
+				val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
+		}
+
+		if (mac_config->switch_port_config.tmac_pad_byte !=
+		    VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT) {
+			val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff);
+
+			val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(
+			    mac_config->switch_port_config.tmac_pad_byte);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->txmac_cfg0_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->txmac_link_util_port);
+
+		if (mac_config->switch_port_config.tmac_util_period !=
+		    VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD) {
+			val64 &=
+			    ~VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(0xf);
+
+			val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(
+			    mac_config->switch_port_config.tmac_util_period);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->txmac_link_util_port[
+		    VXGE_HAL_MAC_SWITCH_PORT]);
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->txmac_gen_cfg1);
+
+	if (mac_config->tmac_perma_stop_en !=
+	    VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT) {
+
+		if (mac_config->tmac_perma_stop_en)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN;
+
+	}
+
+	if (mac_config->tmac_tx_switch_dis !=
+	    VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT) {
+
+		if (mac_config->tmac_tx_switch_dis)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE;
+
+	}
+
+	if (mac_config->tmac_lossy_switch_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT) {
+
+		if (mac_config->tmac_lossy_switch_en)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH;
+
+	}
+
+	if (mac_config->tmac_lossy_switch_en !=
+	    VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT) {
+
+		if (mac_config->tmac_lossy_wire_en)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE;
+
+	}
+
+	if (mac_config->tmac_bcast_to_wire_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT) {
+
+		if (mac_config->tmac_bcast_to_wire_dis)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE;
+
+	}
+
+	if (mac_config->tmac_bcast_to_wire_dis !=
+	    VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT) {
+
+		if (mac_config->tmac_bcast_to_switch_dis)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH;
+
+	}
+
+	if (mac_config->tmac_host_append_fcs_en !=
+	    VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT) {
+
+		if (mac_config->tmac_host_append_fcs_en)
+			val64 |= VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS;
+		else
+			val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS;
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->txmac_gen_cfg1);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg0);
+
+	if (mac_config->rpa_ignore_frame_err !=
+	    VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT) {
+
+		if (mac_config->rpa_ignore_frame_err)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR;
+
+	}
+
+	if (mac_config->rpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT) {
+
+		if (mac_config->rpa_support_snap_ab_n)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N;
+
+	}
+
+	if (mac_config->rpa_search_for_hao !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT) {
+
+		if (mac_config->rpa_search_for_hao)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO;
+
+	}
+
+	if (mac_config->rpa_support_ipv6_mobile_hdrs !=
+	    VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT) {
+
+		if (mac_config->rpa_support_ipv6_mobile_hdrs)
+			val64 |=
+			    VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS;
+		else
+			val64 &=
+			    ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS;
+
+	}
+
+	if (mac_config->rpa_ipv6_stop_searching !=
+	    VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT) {
+
+		if (mac_config->rpa_ipv6_stop_searching)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING;
+
+	}
+
+	if (mac_config->rpa_no_ps_if_unknown !=
+	    VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT) {
+
+		if (mac_config->rpa_no_ps_if_unknown)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN;
+
+	}
+
+	if (mac_config->rpa_search_for_etype !=
+	    VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT) {
+
+		if (mac_config->rpa_search_for_etype)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE;
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg0);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->fau_pa_cfg);
+
+	if (mac_config->rpa_repl_l4_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT) {
+
+		if (mac_config->rpa_repl_l4_comp_csum)
+			val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM;
+		else
+			val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM;
+
+	}
+
+	if (mac_config->rpa_repl_l3_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT) {
+
+		if (mac_config->rpa_repl_l3_incl_cf)
+			val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF;
+		else
+			val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF;
+
+	}
+
+	if (mac_config->rpa_repl_l3_comp_csum !=
+	    VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT) {
+
+		if (mac_config->rpa_repl_l3_comp_csum)
+			val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM;
+		else
+			val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM;
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->fau_pa_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg1);
+
+	if (mac_config->rpa_repl_ipv4_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT) {
+
+		if (mac_config->rpa_repl_ipv4_tcp_incl_ph)
+			val64 |=
+			    VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH;
+		else
+			val64 &=
+			    ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH;
+
+	}
+
+	if (mac_config->rpa_repl_ipv6_tcp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT) {
+
+		if (mac_config->rpa_repl_ipv6_tcp_incl_ph)
+			val64 |=
+			    VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH;
+		else
+			val64 &=
+			    ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH;
+
+	}
+
+	if (mac_config->rpa_repl_ipv4_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT) {
+
+		if (mac_config->rpa_repl_ipv4_udp_incl_ph)
+			val64 |=
+			    VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH;
+		else
+			val64 &=
+			    ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH;
+
+	}
+
+	if (mac_config->rpa_repl_ipv6_udp_incl_ph !=
+	    VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT) {
+
+		if (mac_config->rpa_repl_ipv6_udp_incl_ph)
+			val64 |=
+			    VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH;
+		else
+			val64 &=
+			    ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH;
+
+	}
+
+	if (mac_config->rpa_repl_l4_incl_cf !=
+	    VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT) {
+
+		if (mac_config->rpa_repl_l4_incl_cf)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF;
+
+	}
+
+	if (mac_config->rpa_repl_strip_vlan_tag !=
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT) {
+
+		if (mac_config->rpa_repl_strip_vlan_tag)
+			val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
+
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg1);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xmac_gen_cfg);
+
+	if (mac_config->network_stability_period !=
+	    VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD) {
+
+		val64 &= ~(VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(0xf) |
+		    VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(0xf));
+
+		val64 |= VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(
+		    mac_config->network_stability_period) |
+		    VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(
+		    mac_config->network_stability_period);
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->xmac_gen_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->tpa_global_cfg);
+
+	if (mac_config->tpa_support_snap_ab_n !=
+	    VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT) {
+
+		if (mac_config->tpa_support_snap_ab_n)
+			val64 |= VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N;
+		else
+			val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N;
+
+	}
+
+	if (mac_config->tpa_ecc_enable_n !=
+	    VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT) {
+
+		if (mac_config->tpa_ecc_enable_n)
+			val64 |= VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N;
+		else
+			val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N;
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->tpa_global_cfg);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+
+}
+
+/*
+ * __hal_mrpcim_lag_configure - Initialize LAG registers
+ * @hldev: hal device.
+ *
+ * Initializes LAG registers
+ *
+ */
+vxge_hal_status_e
+__hal_mrpcim_lag_configure(__hal_device_t *hldev)
+{
+	u64 val64;
+	u64 mac_addr;
+	u32 i, j;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_lag_config_t *lag_config =
+	&hldev->header.config.mrpcim_config.lag_config;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_cfg);
+
+	if (lag_config->lag_en == VXGE_HAL_LAG_LAG_EN_DEFAULT) {
+
+		if (val64 & VXGE_HAL_LAG_CFG_EN)
+			lag_config->lag_en = VXGE_HAL_LAG_LAG_EN_ENABLE;
+		else
+			lag_config->lag_en = VXGE_HAL_LAG_LAG_EN_DISABLE;
+
+	}
+
+	if (lag_config->lag_en == VXGE_HAL_LAG_LAG_EN_DISABLE) {
+
+		if (val64 & VXGE_HAL_LAG_CFG_EN) {
+			val64 &= ~VXGE_HAL_LAG_CFG_EN;
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &hldev->mrpcim_reg->lag_cfg);
+		}
+
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+
+		return (VXGE_HAL_OK);
+
+	}
+
+	if (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_DEFAULT) {
+		val64 &= ~VXGE_HAL_LAG_CFG_MODE(0x3);
+		val64 |= VXGE_HAL_LAG_CFG_MODE(lag_config->lag_mode);
+	} else {
+		lag_config->lag_mode = (u32) VXGE_HAL_LAG_CFG_GET_MODE(val64);
+	}
+
+	if (lag_config->la_mode_config.tx_discard !=
+	    VXGE_HAL_LAG_TX_DISCARD_DEFAULT) {
+		if (lag_config->la_mode_config.tx_discard ==
+		    VXGE_HAL_LAG_TX_DISCARD_ENABLE)
+			val64 |= VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV;
+		else
+			val64 &= ~VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV;
+	}
+
+	if (lag_config->la_mode_config.rx_discard !=
+	    VXGE_HAL_LAG_RX_DISCARD_DEFAULT) {
+		if (lag_config->la_mode_config.rx_discard ==
+		    VXGE_HAL_LAG_RX_DISCARD_ENABLE)
+			val64 |= VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV;
+		else
+			val64 &= ~VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV;
+	}
+
+	if (lag_config->sl_mode_config.pref_indiv_port !=
+	    VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT) {
+		if (lag_config->sl_mode_config.pref_indiv_port ==
+		    VXGE_HAL_LAG_RX_DISCARD_ENABLE)
+			val64 |= VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM;
+		else
+			val64 &= ~VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_tx_cfg);
+
+	if (lag_config->incr_tx_aggr_stats !=
+	    VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT) {
+		if (lag_config->incr_tx_aggr_stats ==
+		    VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE)
+			val64 |= VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS;
+		else
+			val64 &= ~VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS;
+	}
+
+	if (lag_config->la_mode_config.distrib_alg_sel !=
+	    VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT) {
+		val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(0x3);
+		val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(
+		    lag_config->la_mode_config.distrib_alg_sel);
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    lag_config->la_mode_config.distrib_dest,
+		    &hldev->mrpcim_reg->lag_distrib_dest);
+	} else {
+		lag_config->la_mode_config.distrib_alg_sel =
+		    (u32) VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(val64);
+		lag_config->la_mode_config.distrib_dest =
+		    vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_distrib_dest);
+	}
+
+	if (lag_config->la_mode_config.distrib_remap_if_fail !=
+	    VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT) {
+		if (lag_config->la_mode_config.distrib_remap_if_fail ==
+		    VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE)
+			val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL;
+		else
+			val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL;
+	}
+
+	if (lag_config->la_mode_config.coll_max_delay !=
+	    VXGE_HAL_LAG_DEF_COLL_MAX_DELAY) {
+		val64 &= ~VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(0xffff);
+		val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(
+		    lag_config->la_mode_config.coll_max_delay);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_tx_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_active_passive_cfg);
+
+	if (lag_config->ap_mode_config.hot_standby !=
+	    VXGE_HAL_LAG_HOT_STANDBY_DEFAULT) {
+		if (lag_config->ap_mode_config.hot_standby ==
+		    VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT)
+			val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY;
+		else
+			val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY;
+	}
+
+	if (lag_config->ap_mode_config.lacp_decides !=
+	    VXGE_HAL_LAG_LACP_DECIDES_DEFAULT) {
+		if (lag_config->ap_mode_config.lacp_decides ==
+		    VXGE_HAL_LAG_LACP_DECIDES_ENBALE)
+			val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES;
+		else
+			val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES;
+	}
+
+	if (lag_config->ap_mode_config.pref_active_port !=
+	    VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT) {
+		if (lag_config->ap_mode_config.pref_active_port ==
+		    VXGE_HAL_LAG_PREF_ACTIVE_PORT_1)
+			val64 |=
+			    VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM;
+		else
+			val64 &=
+			    ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM;
+	}
+
+	if (lag_config->ap_mode_config.auto_failback !=
+	    VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT) {
+		if (lag_config->ap_mode_config.auto_failback ==
+		    VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE)
+			val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK;
+		else
+			val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK;
+	}
+
+	if (lag_config->ap_mode_config.failback_en !=
+	    VXGE_HAL_LAG_FAILBACK_EN_DEFAULT) {
+		if (lag_config->ap_mode_config.failback_en ==
+		    VXGE_HAL_LAG_FAILBACK_EN_ENBALE)
+			val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN;
+		else
+			val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN;
+	}
+
+	if (lag_config->ap_mode_config.cold_failover_timeout !=
+	    VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT) {
+		val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(
+		    0xffff);
+		val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(
+		    lag_config->ap_mode_config.cold_failover_timeout);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_active_passive_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_lacp_cfg);
+
+	if (lag_config->lacp_config.lacp_en !=
+	    VXGE_HAL_LAG_LACP_EN_DEFAULT) {
+		if (lag_config->lacp_config.lacp_en ==
+		    VXGE_HAL_LAG_LACP_EN_ENABLE)
+			val64 |= VXGE_HAL_LAG_LACP_CFG_EN;
+		else
+			val64 &= ~VXGE_HAL_LAG_LACP_CFG_EN;
+	}
+
+	if (lag_config->lacp_config.lacp_begin !=
+	    VXGE_HAL_LAG_LACP_BEGIN_DEFAULT) {
+		if (lag_config->lacp_config.lacp_begin ==
+		    VXGE_HAL_LAG_LACP_BEGIN_RESET)
+			val64 |= VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN;
+		else
+			val64 &= ~VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN;
+	}
+
+	if (lag_config->lacp_config.discard_lacp !=
+	    VXGE_HAL_LAG_DISCARD_LACP_DEFAULT) {
+		if (lag_config->lacp_config.discard_lacp ==
+		    VXGE_HAL_LAG_DISCARD_LACP_ENABLE)
+			val64 |= VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP;
+		else
+			val64 &= ~VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP;
+	}
+
+	if (lag_config->lacp_config.liberal_len_chk !=
+	    VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT) {
+		if (lag_config->lacp_config.liberal_len_chk ==
+		    VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE)
+			val64 |= VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK;
+		else
+			val64 &= ~VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_lacp_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_marker_cfg);
+
+	if (lag_config->lacp_config.marker_gen_recv_en !=
+	    VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT) {
+		if (lag_config->lacp_config.marker_gen_recv_en ==
+		    VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE)
+			val64 |= VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN;
+		else
+			val64 &= ~VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN;
+	}
+
+	if (lag_config->lacp_config.marker_resp_en !=
+	    VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT) {
+		if (lag_config->lacp_config.marker_resp_en ==
+		    VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE)
+			val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_EN;
+		else
+			val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_EN;
+	}
+
+	if (lag_config->lacp_config.marker_resp_timeout !=
+	    VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT) {
+		val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(0xffff);
+		val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(
+		    lag_config->lacp_config.marker_resp_timeout);
+	}
+
+	if (lag_config->lacp_config.slow_proto_mrkr_min_interval !=
+	    VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL) {
+		val64 &= ~VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(
+		    0xffff);
+		val64 |= VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(
+		    lag_config->lacp_config.slow_proto_mrkr_min_interval);
+	}
+
+	if (lag_config->lacp_config.throttle_mrkr_resp !=
+	    VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT) {
+		if (lag_config->lacp_config.throttle_mrkr_resp ==
+		    VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE)
+			val64 |= VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP;
+		else
+			val64 &= ~VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_marker_cfg);
+
+	for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_port_cfg[i]);
+
+		if (lag_config->port_config[i].lag_en !=
+		    VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT) {
+			if (lag_config->port_config[i].lag_en ==
+			    VXGE_HAL_LAG_PORT_LAG_EN_ENABLE)
+				val64 |= VXGE_HAL_LAG_PORT_CFG_EN;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_CFG_EN;
+		}
+
+		if (lag_config->port_config[i].discard_slow_proto !=
+		    VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT) {
+			if (lag_config->port_config[i].discard_slow_proto ==
+			    VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO;
+		}
+
+		if (lag_config->port_config[i].host_chosen_aggr !=
+		    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT) {
+			if (lag_config->port_config[i].host_chosen_aggr ==
+			    VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR;
+		}
+
+		if (lag_config->port_config[i].discard_unknown_slow_proto !=
+		    VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT) {
+			if (lag_config->port_config[i].discard_unknown_slow_proto ==
+			    VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_port_cfg[i]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_port_actor_admin_cfg[i]);
+
+		if (lag_config->port_config[i].actor_port_num !=
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM) {
+			val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(
+			    lag_config->port_config[i].actor_port_num);
+		}
+
+		if (lag_config->port_config[i].actor_port_priority !=
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY) {
+			val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(
+			    lag_config->port_config[i].actor_port_priority);
+		}
+
+		if (lag_config->port_config[i].actor_key_10g !=
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G) {
+			val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(
+			    lag_config->port_config[i].actor_key_10g);
+		}
+
+		if (lag_config->port_config[i].actor_key_1g !=
+		    VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G) {
+			val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(
+			    lag_config->port_config[i].actor_key_1g);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_port_actor_admin_cfg[i]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_port_actor_admin_state[i]);
+
+		if (lag_config->port_config[i].actor_lacp_activity !=
+		    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT) {
+			if (lag_config->port_config[i].actor_lacp_activity ==
+			    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY;
+		}
+
+		if (lag_config->port_config[i].actor_lacp_timeout !=
+		    VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT) {
+			if (lag_config->port_config[i].actor_lacp_timeout ==
+			    VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT;
+		}
+
+		if (lag_config->port_config[i].actor_aggregation !=
+		    VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT) {
+			if (lag_config->port_config[i].actor_aggregation ==
+			    VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION;
+		}
+
+		if (lag_config->port_config[i].actor_synchronization !=
+		    VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT) {
+			if (lag_config->port_config[i].actor_aggregation ==
+			    VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC)
+				val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION;
+		}
+
+		if (lag_config->port_config[i].actor_collecting !=
+		    VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT) {
+			if (lag_config->port_config[i].actor_collecting ==
+			    VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING;
+		}
+
+		if (lag_config->port_config[i].actor_distributing !=
+		    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT) {
+			if (lag_config->port_config[i].actor_distributing ==
+			    VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING;
+		}
+
+		if (lag_config->port_config[i].actor_defaulted !=
+		    VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT) {
+			if (lag_config->port_config[i].actor_defaulted ==
+			    VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED)
+				val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED;
+		}
+
+		if (lag_config->port_config[i].actor_expired !=
+		    VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT) {
+			if (lag_config->port_config[i].actor_expired ==
+			    VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED)
+				val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_port_actor_admin_state[i]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_port_partner_admin_cfg[i]);
+
+		if (lag_config->port_config[i].partner_sys_pri !=
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI) {
+			val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(
+			    lag_config->port_config[i].partner_sys_pri);
+		}
+
+		if (lag_config->port_config[i].partner_key !=
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY) {
+			val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(
+			    lag_config->port_config[i].partner_key);
+		}
+
+		if (lag_config->port_config[i].partner_port_num !=
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM) {
+			val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(
+			    lag_config->port_config[i].partner_port_num);
+		}
+
+		if (lag_config->port_config[i].partner_port_priority !=
+		    VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY) {
+			val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(
+			    0xffff);
+			val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(
+			    lag_config->port_config[i].actor_port_priority);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_port_partner_admin_cfg[i]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_port_partner_admin_state[i]);
+
+		if (lag_config->port_config[i].partner_lacp_activity !=
+		    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT) {
+			if (lag_config->port_config[i].partner_lacp_activity ==
+			    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE)
+				val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY;
+		}
+
+		if (lag_config->port_config[i].partner_lacp_timeout !=
+		    VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT) {
+			if (lag_config->port_config[i].partner_lacp_timeout ==
+			    VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT;
+		}
+
+		if (lag_config->port_config[i].partner_aggregation !=
+		    VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT) {
+			if (lag_config->port_config[i].partner_aggregation ==
+			    VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION;
+		}
+
+		if (lag_config->port_config[i].partner_synchronization !=
+		    VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT) {
+			if (lag_config->port_config[i].partner_aggregation ==
+			    VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC)
+				val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION;
+		}
+
+		if (lag_config->port_config[i].partner_collecting !=
+		    VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT) {
+			if (lag_config->port_config[i].partner_collecting ==
+			    VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING;
+		}
+
+		if (lag_config->port_config[i].partner_distributing !=
+		    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT) {
+			if (lag_config->port_config[i].partner_distributing ==
+			    VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING;
+		}
+
+		if (lag_config->port_config[i].partner_defaulted !=
+		    VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT) {
+			if (lag_config->port_config[i].partner_defaulted ==
+			    VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED)
+				val64 |=
+				    VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED;
+		}
+
+		if (lag_config->port_config[i].partner_expired !=
+		    VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT) {
+			if (lag_config->port_config[i].partner_expired ==
+			    VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED)
+				val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED;
+			else
+				val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_port_partner_admin_state[i]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_port_partner_admin_sys_id[i]);
+
+		mac_addr = 0;
+
+		for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) {
+			mac_addr <<= 8;
+			mac_addr |=
+			    (u8) lag_config->port_config[i].partner_mac_addr[j];
+		}
+
+		if (mac_addr != 0xffffffffffffULL) {
+			val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(
+			    0xffffffffffffULL);
+			val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(
+			    mac_addr);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_port_partner_admin_sys_id[i]);
+
+	}
+
+	for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_aggr_id_cfg[i]);
+
+		val64 &= ~VXGE_HAL_LAG_AGGR_ID_CFG_ID(0xffff);
+		val64 |= VXGE_HAL_LAG_AGGR_ID_CFG_ID(
+		    lag_config->aggr_config[i].aggr_id);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_aggr_id_cfg[i]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_aggr_addr_cfg[i]);
+
+		mac_addr = 0;
+
+		for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) {
+			mac_addr <<= 8;
+			mac_addr |= (u8) lag_config->aggr_config[i].mac_addr[j];
+		}
+
+		if (mac_addr != 0xffffffffffffULL) {
+			val64 &=
+			    ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(0xffffffffffffULL);
+			val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(mac_addr);
+		}
+
+		if (lag_config->aggr_config[i].use_port_mac_addr !=
+		    VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT) {
+			if (lag_config->aggr_config[i].use_port_mac_addr ==
+			    VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE)
+				val64 |=
+				    VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR;
+			else
+				val64 &=
+				    ~VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR;
+		}
+
+		if (lag_config->aggr_config[i].mac_addr_sel !=
+		    VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT) {
+			if (lag_config->aggr_config[i].mac_addr_sel ==
+			    VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1)
+				val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL;
+			else
+				val64 &= ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_aggr_addr_cfg[i]);
+
+		if (lag_config->aggr_config[i].admin_key ==
+		    VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->mrpcim_reg->lag_aggr_admin_key[i]);
+
+			val64 &= ~VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(0xffff);
+			val64 |= VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(
+			    lag_config->aggr_config[i].admin_key);
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &hldev->mrpcim_reg->lag_aggr_admin_key[i]);
+		}
+	}
+
+	if (lag_config->sys_pri != VXGE_HAL_LAG_DEF_SYS_PRI) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->lag_sys_cfg);
+
+		val64 &= ~VXGE_HAL_LAG_SYS_CFG_SYS_PRI(0xffff);
+		val64 |= VXGE_HAL_LAG_SYS_CFG_SYS_PRI(
+		    lag_config->sys_pri);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->lag_sys_cfg);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_sys_id);
+
+	mac_addr = 0;
+
+	for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) {
+		mac_addr <<= 8;
+		mac_addr |= (u8) lag_config->mac_addr[j];
+	}
+
+	if (mac_addr != 0xffffffffffffULL) {
+		val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR(0xffffffffffffULL);
+		val64 |= VXGE_HAL_LAG_SYS_ID_ADDR(mac_addr);
+	}
+
+	if (lag_config->use_port_mac_addr !=
+	    VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT) {
+		if (lag_config->use_port_mac_addr ==
+		    VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE)
+			val64 |= VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR;
+		else
+			val64 &= ~VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR;
+	}
+
+	if (lag_config->mac_addr_sel != VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT) {
+		if (lag_config->mac_addr_sel ==
+		    VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1)
+			val64 |= VXGE_HAL_LAG_SYS_ID_ADDR_SEL;
+		else
+			val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR_SEL;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_sys_id);
+
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_aggr_alt_admin_key);
+
+	if (lag_config->ap_mode_config.alt_admin_key !=
+	    VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY) {
+		val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(0xffff);
+		val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(
+		    lag_config->ap_mode_config.alt_admin_key);
+	}
+
+	if (lag_config->ap_mode_config.alt_aggr !=
+	    VXGE_HAL_LAG_ALT_AGGR_DEFAULT) {
+		if (lag_config->ap_mode_config.alt_aggr ==
+		    VXGE_HAL_LAG_ALT_AGGR_1)
+			val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR;
+		else
+			val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_aggr_alt_admin_key);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_timer_cfg_1);
+
+	if (lag_config->fast_per_time != VXGE_HAL_LAG_DEF_FAST_PER_TIME) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(
+		    lag_config->fast_per_time);
+	}
+
+	if (lag_config->slow_per_time != VXGE_HAL_LAG_DEF_SLOW_PER_TIME) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(
+		    lag_config->slow_per_time);
+	}
+
+	if (lag_config->short_timeout != VXGE_HAL_LAG_DEF_SHORT_TIMEOUT) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(
+		    lag_config->short_timeout);
+	}
+
+	if (lag_config->long_timeout != VXGE_HAL_LAG_DEF_LONG_TIMEOUT) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(
+		    lag_config->short_timeout);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_timer_cfg_1);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->lag_timer_cfg_2);
+
+	if (lag_config->churn_det_time != VXGE_HAL_LAG_DEF_CHURN_DET_TIME) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(
+		    lag_config->churn_det_time);
+	}
+
+	if (lag_config->aggr_wait_time != VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(
+		    lag_config->slow_per_time);
+	}
+
+	if (lag_config->short_timer_scale !=
+	    VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(
+		    lag_config->short_timer_scale);
+	}
+
+	if (lag_config->long_timer_scale !=
+	    VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT) {
+		val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(0xffff);
+		val64 |= VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(
+		    lag_config->long_timer_scale);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->lag_timer_cfg_2);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+
+}
+
+/*
+ * __hal_mrpcim_get_vpd_data - Getting vpd_data.
+ *
+ * @hldev: HAL device handle.
+ *
+ * Getting  product name and serial number from vpd capabilites structure
+ *
+ */
+void
+__hal_mrpcim_get_vpd_data(__hal_device_t *hldev)
+{
+	u8 *vpd_data;
+	u16 data;
+	u32 data32;
+	u32 i, j, count, fail = 0;
+	u32 addr_offset, data_offset;
+	u32 max_count = hldev->header.config.device_poll_millis * 10;
+
+	vxge_assert(hldev);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	addr_offset = hldev->pci_caps.vpd_cap_offset +
+	    vxge_offsetof(vxge_hal_vpid_capability_le_t, vpd_address);
+
+	data_offset = hldev->pci_caps.vpd_cap_offset +
+	    vxge_offsetof(vxge_hal_vpid_capability_le_t, vpd_data);
+
+	vxge_os_strlcpy((char *) hldev->mrpcim->vpd_data.product_name,
+	    "10 Gigabit Ethernet Adapter",
+	    sizeof(hldev->mrpcim->vpd_data.product_name));
+	vxge_os_strlcpy((char *) hldev->mrpcim->vpd_data.serial_num,
+	    "not available",
+	    sizeof(hldev->mrpcim->vpd_data.serial_num));
+
+	if (hldev->func_id != 0) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return;
+	}
+	vpd_data = (u8 *) vxge_os_malloc(hldev->header.pdev,
+	    VXGE_HAL_VPD_BUFFER_SIZE + 16);
+	if (vpd_data == 0)
+		return;
+
+	for (i = 0; i < VXGE_HAL_VPD_BUFFER_SIZE; i += 4) {
+		vxge_os_pci_write16(hldev->header.pdev,
+		    hldev->header.cfgh,
+		    addr_offset, (u16) i);
+		for (count = 0; count < max_count; count++) {
+			vxge_os_udelay(100);
+			(void) __hal_vpath_pci_read(hldev,
+			    hldev->first_vp_id,
+			    addr_offset, 2, &data);
+			if (data & VXGE_HAL_PCI_VPID_COMPL_FALG)
+				break;
+		}
+
+		if (count >= max_count) {
+			vxge_hal_info_log_device("%s:ERR, \
+			    Reading VPD data failed", __func__);
+			fail = 1;
+			break;
+		}
+		(void) __hal_vpath_pci_read(hldev,
+		    hldev->first_vp_id,
+		    data_offset,
+		    4,
+		    &data32);
+
+		for (j = 0; j < 4; j++) {
+			vpd_data[i + j] = (u8) (data32 & 0xff);
+			data32 >>= 8;
+		}
+	}
+
+	if (!fail) {
+
+		/* read serial number of adapter */
+		for (count = 0; count < VXGE_HAL_VPD_BUFFER_SIZE; count++) {
+			if ((vpd_data[count] == 'S') &&
+			    (vpd_data[count + 1] == 'N') &&
+			    (vpd_data[count + 2] < VXGE_HAL_VPD_LENGTH)) {
+				(void) vxge_os_memzero(
+				    hldev->mrpcim->vpd_data.serial_num,
+				    VXGE_HAL_VPD_LENGTH);
+				(void) vxge_os_memcpy(
+				    hldev->mrpcim->vpd_data.serial_num,
+				    &vpd_data[count + 3],
+				    vpd_data[count + 2]);
+				break;
+			}
+		}
+
+		if (vpd_data[1] < VXGE_HAL_VPD_LENGTH) {
+			(void) vxge_os_memzero(
+			    hldev->mrpcim->vpd_data.product_name, vpd_data[1]);
+			(void) vxge_os_memcpy(hldev->mrpcim->vpd_data.product_name,
+			    &vpd_data[3], vpd_data[1]);
+		}
+	}
+
+	vxge_os_free(hldev->header.pdev,
+	    vpd_data,
+	    VXGE_HAL_VPD_BUFFER_SIZE + 16);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, fail);
+}
+
+/*
+ * __hal_mrpcim_rts_table_access - Get/Set the entries from RTS access tables
+ * @devh: Device handle.
+ * @action: Write Enable. 0 - Read Operation; 1 - Write Operation
+ * @rts_table: Data structure select. Identifies the RTS data structure
+ *		(i.e. lookup table) to access.
+ *		0; DA; Destination Address
+ *		1; VID; VLAN ID
+ *		2; ETYPE; Ethertype
+ *		3; PN; Layer 4 Port Number
+ *		4; RANGE_PN; Range of Layer 4 Port Numbers
+ *		5; RTH_GEN_CFG; Receive-Traffic Hashing General Configuration
+ *		6; RTH_SOLO_IT; Receive-Traffic Hashing Indirection Table
+ *		(Single Bucket Programming)
+ *		7; RTH_JHASH_CFG; Receive-Traffic Hashing Jenkins Hash Config
+ *		8; RTH_MASK; Receive-Traffic Hashing Mask
+ *		9; RTH_KEY; Receive-Traffic Hashing Key
+ *		10; QOS; VLAN Quality of Service
+ *		11; DS; IP Differentiated Services
+ * @offset: Offset (into the data structure) to execute the command on.
+ * @data1: Pointer to the data 1 to be read from the table
+ * @data2: Pointer to the data 2 to be read from the table
+ * @vpath_vector: Identifies the candidate VPATH(s) for the given entry.
+ *		These VPATH(s) determine the set of target destinations for
+ *		a frame that matches this steering entry. Any or all bits
+ *		can be set, which handles 16+1 virtual paths in an 'n-hot'
+ *		basis. VPATH 0 is the MSbit.
+ *
+ * Read from the RTS table
+ *
+ */
+vxge_hal_status_e
+__hal_mrpcim_rts_table_access(
+    vxge_hal_device_h devh,
+    u32 action,
+    u32 rts_table,
+    u32 offset,
+    u64 *data1,
+    u64 *data2,
+    u64 *vpath_vector)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((devh != NULL) && (data1 != NULL) &&
+	    (data2 != NULL) && (vpath_vector != NULL));
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, "
+	    "offset = %d, data1 = 0x"VXGE_OS_STXFMT", "
+	    "data2 = 0x"VXGE_OS_STXFMT", vpath_vector = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, action, rts_table, offset, (ptr_t) data1,
+	    (ptr_t) data2, (ptr_t) vpath_vector);
+
+	val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(offset);
+
+	if (action == VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE)
+		val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_WE;
+
+	if ((rts_table ==
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
+		val64 |= VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL;
+	}
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &hldev->mrpcim_reg->rts_mgr_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->mrpcim_reg->rts_mgr_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->rts_mgr_steer_ctrl, 0,
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->rts_mgr_steer_ctrl);
+
+	if ((val64 & VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS) &&
+	    (action == VXGE_HAL_RTS_MGR_STEER_CTRL_WE_READ)) {
+
+		*data1 = vxge_os_pio_mem_read64(
+		    hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rts_mgr_steer_data0);
+
+		*data2 = vxge_os_pio_mem_read64(
+		    hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rts_mgr_steer_data1);
+
+		*vpath_vector = vxge_os_pio_mem_read64(
+		    hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rts_mgr_steer_vpath_vector);
+
+		status = VXGE_HAL_OK;
+
+	} else {
+		status = VXGE_HAL_FAIL;
+	}
+
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_mac_addr_add - Add the mac address entry
+ *				into MAC address table.
+ * @devh: Device handle.
+ * @offset: Index into the DA table to add the mac address.
+ * @macaddr: MAC address to be added for this vpath into the list
+ * @macaddr_mask: MAC address mask for macaddr
+ * @vpath_vector: Bit mask specifying the vpaths to which
+ *		the mac address applies
+ * @duplicate_mode: Duplicate MAC address add mode. Please see
+ *		vxge_hal_vpath_mac_addr_add_mode_e {}
+ *
+ * Adds the given mac address, mac address mask and vpath vector into the list
+ *
+ * see also: vxge_hal_mrpcim_mac_addr_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_mac_addr_add(
+    vxge_hal_device_h devh,
+    u32 offset,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask,
+    u64 vpath_vector,
+    u32 duplicate_mode)
+{
+	u32 i;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", offset = %d, "
+	    "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, "
+	    "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x, "
+	    "vpath_vector = 0x"VXGE_OS_LLXFMT,
+	    (ptr_t) devh, offset, macaddr[0], macaddr[1], macaddr[2],
+	    macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0],
+	    macaddr_mask[1], macaddr_mask[2], macaddr_mask[3],
+	    macaddr_mask[4], macaddr_mask[5], vpath_vector);
+
+	for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
+		data1 <<= 8;
+		data1 |= (u8) macaddr[i];
+	}
+
+	data1 = VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(data1);
+
+	for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
+		data2 <<= 8;
+		data2 |= (u8) macaddr_mask[i];
+	}
+
+	switch (duplicate_mode) {
+	case VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE:
+		i = 0;
+		break;
+	case VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
+		i = 1;
+		break;
+	case VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
+		i = 2;
+		break;
+	default:
+		i = 0;
+		break;
+	}
+
+	data2 = VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(data2) |
+	    VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(i);
+
+	status = __hal_mrpcim_rts_table_access(devh,
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE,
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA,
+	    offset,
+	    &data1,
+	    &data2,
+	    &vpath_vector);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_mac_addr_get - Read the mac address entry into
+ *				MAC address table.
+ * @devh: Device handle.
+ * @offset: Index into the DA table to execute the command on.
+ * @macaddr: Buffer to return MAC address to be added for this vpath
+ *		into the list
+ * @macaddr_mask: Buffer to return MAC address mask for macaddr
+ * @vpath_vector: Buffer to return Bit mask specifying the vpaths
+ *		to which the mac address applies
+ *
+ * Reads the mac address, mac address mask and vpath vector from
+ *		the given offset
+ *
+ * see also: vxge_hal_mrpcim_mac_addr_add
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_mac_addr_get(
+    vxge_hal_device_h devh,
+    u32 offset,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask,
+    u64 *vpath_vector)
+{
+	u32 i;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	status = __hal_mrpcim_rts_table_access(devh,
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE,
+	    VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA,
+	    offset,
+	    &data1,
+	    &data2,
+	    vpath_vector);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	data1 = VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(data1);
+
+	data2 = VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
+
+	for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+		macaddr[i - 1] = (u8) (data1 & 0xFF);
+		data1 >>= 8;
+	}
+
+	for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+		macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
+		data2 >>= 8;
+	}
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_mrpcim_strip_repl_vlan_tag_enable - Enable strip Repl vlan tag.
+ * @devh: Device handle.
+ *
+ * Enable X3100 strip Repl vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_strip_repl_vlan_tag_enable(
+    vxge_hal_device_h devh)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	if (hldev->header.config.mrpcim_config.mac_config.
+	    rpa_repl_strip_vlan_tag ==
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg1);
+
+	val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg1);
+
+	hldev->header.config.mrpcim_config.mac_config.rpa_repl_strip_vlan_tag =
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE;
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_strip_repl_vlan_tag_disable - Disable strip Repl vlan tag.
+ * @devh: Device handle.
+ *
+ * Disable X3100 strip Repl vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_strip_repl_vlan_tag_disable(
+    vxge_hal_device_h devh)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	if (hldev->header.config.mrpcim_config.mac_config.
+	    rpa_repl_strip_vlan_tag ==
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg1);
+
+	val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->rxmac_rx_pa_cfg1);
+
+	hldev->header.config.mrpcim_config.mac_config.rpa_repl_strip_vlan_tag =
+	    VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE;
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_lag_config_get - Get the LAG config.
+ * @devh: Device handle.
+ * @lconfig: LAG Configuration
+ *
+ * Returns the current LAG configuration.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_lag_config_get(
+    vxge_hal_device_h devh,
+    vxge_hal_lag_config_t *lconfig)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", lconfig = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) lconfig);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	vxge_os_memcpy(lconfig,
+	    &hldev->header.config.mrpcim_config.lag_config,
+	    sizeof(vxge_hal_lag_config_t));
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_lag_config_set - Set the LAG config.
+ * @devh: Device handle.
+ * @lconfig: LAG Configuration
+ *
+ * Sets the LAG configuration.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_lag_config_set(
+    vxge_hal_device_h devh,
+    vxge_hal_lag_config_t *lconfig)
+{
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", lconfig = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) lconfig);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	status = __hal_device_lag_config_check(lconfig);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_os_memcpy(&hldev->header.config.mrpcim_config.lag_config,
+	    lconfig,
+	    sizeof(vxge_hal_lag_config_t));
+
+	status = __hal_mrpcim_lag_configure(hldev);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_getpause_data -Pause frame frame generation and reception.
+ * @devh: HAL device handle.
+ * @port : Port number 0, 1, or 2
+ * @tx : A field to return the pause generation capability of the NIC.
+ * @rx : A field to return the pause reception capability of the NIC.
+ *
+ * Returns the Pause frame generation and reception capability of the NIC.
+ * Return value:
+ * status
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_getpause_data(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 *tx,
+    u32 *rx)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", port = %d, tx = 0x"VXGE_OS_STXFMT", "
+	    "rx = 0x"VXGE_OS_STXFMT, (ptr_t) devh, port, (ptr_t) tx,
+	    (ptr_t) rx);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (port >= VXGE_HAL_MAC_MAX_PORTS) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT);
+		return (VXGE_HAL_ERR_INVALID_PORT);
+	}
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0,
+	    &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
+
+	if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN)
+		*tx = 1;
+
+	if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN)
+		*rx = 1;
+
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_setpause_data -  set/reset pause frame generation.
+ * @devh: HAL device handle.
+ * @port : Port number 0, 1, or 2
+ * @tx: A field that indicates the pause generation capability to be
+ * set on the NIC.
+ * @rx: A field that indicates the pause reception capability to be
+ * set on the NIC.
+ *
+ * It can be used to set or reset Pause frame generation or reception
+ * support of the NIC.
+ * Return value:
+ * int, returns 0 on Success
+ */
+
+vxge_hal_status_e
+vxge_hal_mrpcim_setpause_data(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 tx,
+    u32 rx)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim(
+	    "devh = 0x"VXGE_OS_STXFMT", port = %d, tx = %d, rx = %d",
+	    (ptr_t) devh, port, tx, rx);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (port >= VXGE_HAL_MAC_MAX_PORTS) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT);
+		return (VXGE_HAL_ERR_INVALID_PORT);
+	}
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0,
+	    &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
+	if (tx)
+		val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
+	else
+		val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
+	if (rx)
+		val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
+	else
+		val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_mrpcim_bist_test - invokes the MemBist test of the card .
+ * @devh: HAL device handle.
+ * vxge_nic structure.
+ * @data:variable that returns the result of each of the test conducted by
+ * the driver.
+ *
+ * This invokes the MemBist test of the card. We give around
+ * 2 secs time for the Test to complete. If it's still not complete
+ * within this peiod, we consider that the test failed.
+ * Return value:
+ * 0 on success and -1 on failure.
+ */
+vxge_hal_status_e
+vxge_hal_mrpcim_bist_test(vxge_hal_device_h devh, u64 *data)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	u8 bist = 0;
+	int retry = 0;
+	vxge_hal_status_e status = VXGE_HAL_FAIL;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT,
+			(ptr_t)devh);
+
+	if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE);
+		return (VXGE_HAL_ERR_INVALID_DEVICE);
+	}
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	(void) __hal_vpath_pci_read(hldev,
+	    hldev->first_vp_id,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, bist),
+	    1,
+	    &bist);
+	bist |= 0x40;
+	vxge_os_pci_write8(hldev->header.pdev, hldev->header.cfgh,
+	    vxge_offsetof(vxge_hal_pci_config_le_t, bist), bist);
+
+	while (retry < 20) {
+		(void) __hal_vpath_pci_read(hldev,
+		    hldev->first_vp_id,
+		    vxge_offsetof(vxge_hal_pci_config_le_t, bist),
+		    1,
+		    &bist);
+		if (!(bist & 0x40)) {
+			*data = (bist & 0x0f);
+			status = VXGE_HAL_OK;
+			break;
+		}
+		vxge_os_mdelay(100);
+		retry++;
+	}
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_mrpcim_initialize - Initialize mrpcim
+ * @hldev: hal device.
+ *
+ * Initializes mrpcim
+ *
+ * See also: __hal_mrpcim_terminate()
+ */
+vxge_hal_status_e
+__hal_mrpcim_initialize(__hal_device_t *hldev)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT,
+			(ptr_t)hldev);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	hldev->mrpcim = (__hal_mrpcim_t *)
+	    vxge_os_malloc(hldev->header.pdev, sizeof(__hal_mrpcim_t));
+
+	if (hldev->mrpcim == NULL) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	vxge_os_memzero(hldev->mrpcim, sizeof(__hal_mrpcim_t));
+
+	__hal_mrpcim_get_vpd_data(hldev);
+
+	hldev->mrpcim->mrpcim_stats_block =
+	    __hal_blockpool_block_allocate(hldev, VXGE_OS_HOST_PAGE_SIZE);
+
+	if (hldev->mrpcim->mrpcim_stats_block == NULL) {
+
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+
+	}
+
+	hldev->mrpcim->mrpcim_stats = (vxge_hal_mrpcim_stats_hw_info_t *)
+	    hldev->mrpcim->mrpcim_stats_block->memblock;
+
+	vxge_os_memzero(hldev->mrpcim->mrpcim_stats,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	vxge_os_memzero(&hldev->mrpcim->mrpcim_stats_sav,
+	    sizeof(vxge_hal_mrpcim_stats_hw_info_t));
+
+	status = __hal_mrpcim_mac_configure(hldev);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_mrpcim_lag_configure(hldev);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mdio_gen_cfg_port[0]);
+
+	hldev->mrpcim->mdio_phy_prtad0 =
+	    (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mdio_gen_cfg_port[1]);
+
+	hldev->mrpcim->mdio_phy_prtad1 =
+	    (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xgxs_static_cfg_port[0]);
+
+	hldev->mrpcim->mdio_dte_prtad0 =
+	    (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->xgxs_static_cfg_port[1]);
+
+	hldev->mrpcim->mdio_dte_prtad1 =
+	    (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    hldev->mrpcim->mrpcim_stats_block->dma_addr,
+	    &hldev->mrpcim_reg->mrpcim_stats_start_host_addr);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+	val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(0x1f);
+	val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(
+	    hldev->first_vp_id);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &hldev->mrpcim_reg->mrpcim_general_cfg2);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS),
+	    &hldev->mrpcim_reg->rxmac_authorize_all_addr);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS),
+	    &hldev->mrpcim_reg->rxmac_authorize_all_vid);
+
+	if (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->rdcrdtarb_cfg0);
+
+		/* Set MOST to 8 for HP-ISS platform */
+		val64 &= ~VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(0x3f);
+
+		val64 |= VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(8);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->mrpcim_reg->rdcrdtarb_cfg0);
+	}
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    hldev->first_vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP,
+	    0);
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+
+}
+
+/*
+ * __hal_mrpcim_terminate - Terminates mrpcim
+ * @hldev: hal device.
+ *
+ * Terminates mrpcim.
+ *
+ * See also: __hal_mrpcim_initialize()
+ */
+vxge_hal_status_e
+__hal_mrpcim_terminate(__hal_device_t *hldev)
+{
+	vxge_hal_device_h devh = (vxge_hal_device_h) hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((hldev != NULL) && (hldev->mrpcim != NULL));
+
+	vxge_hal_trace_log_mrpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	if (hldev->mrpcim == NULL) {
+		vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    hldev->first_vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN,
+	    0);
+
+	if (hldev->mrpcim->mrpcim_stats_block != NULL) {
+		__hal_blockpool_block_free(devh,
+		    hldev->mrpcim->mrpcim_stats_block);
+		hldev->mrpcim->mrpcim_stats_block = NULL;
+	}
+
+	vxge_os_free(hldev->header.pdev,
+	    hldev->mrpcim, sizeof(__hal_mrpcim_t));
+
+	hldev->mrpcim = NULL;
+
+	vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-mrpcim.h b/sys/dev/vxge/vxgehal/vxgehal-mrpcim.h
new file mode 100644
index 000000000000..324130e8f34e
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-mrpcim.h
@@ -0,0 +1,135 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_MRPCIM_H
+#define	VXGE_HAL_MRPCIM_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * __hal_mrpcim_t
+ *
+ * HAL mrpcim object. Represents privileged mode device.
+ */
+typedef struct __hal_mrpcim_t {
+	u32	mdio_phy_prtad0;
+	u32	mdio_phy_prtad1;
+	u32	mdio_dte_prtad0;
+	u32	mdio_dte_prtad1;
+	vxge_hal_vpd_data_t vpd_data;
+	__hal_blockpool_entry_t *mrpcim_stats_block;
+	vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats;
+	vxge_hal_mrpcim_stats_hw_info_t mrpcim_stats_sav;
+	vxge_hal_mrpcim_xpak_stats_t xpak_stats[VXGE_HAL_MAC_MAX_WIRE_PORTS];
+} __hal_mrpcim_t;
+
+#define	VXGE_HAL_MRPCIM_STATS_PIO_READ(loc, offset) {			\
+	status = vxge_hal_mrpcim_stats_access(devh,			\
+				VXGE_HAL_STATS_OP_READ,			\
+				loc,					\
+				offset,					\
+				&val64);				\
+									\
+	if (status != VXGE_HAL_OK) {					\
+		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",	\
+				__FILE__, __func__, __LINE__, status);	\
+		return (status);					\
+	}								\
+}
+
+#define	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(reg)				\
+	vxge_os_pio_mem_write64(					\
+		hldev->header.pdev,					\
+		hldev->header.regh0,					\
+		VXGE_HAL_INTR_MASK_ALL,					\
+		(reg));
+
+#define	VXGE_HAL_MRPCIM_ERROR_REG_MASK(reg)				\
+	vxge_os_pio_mem_write64(					\
+		hldev->header.pdev,					\
+		hldev->header.regh0,					\
+		VXGE_HAL_INTR_MASK_ALL,					\
+		(reg));
+
+#define	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(mask, reg)			\
+	vxge_os_pio_mem_write64(					\
+		hldev->header.pdev,					\
+		hldev->header.regh0,					\
+		~mask,							\
+		(reg));
+
+vxge_hal_status_e
+__hal_mrpcim_mdio_access(
+    vxge_hal_device_h devh,
+    u32 port,
+    u32 operation,
+    u32 device,
+    u16 addr,
+    u16 *data);
+
+vxge_hal_status_e
+__hal_mrpcim_rts_table_access(
+    vxge_hal_device_h devh,
+    u32 action,
+    u32 rts_table,
+    u32 offset,
+    u64 *data1,
+    u64 *data2,
+    u64 *vpath_vector);
+
+vxge_hal_status_e
+__hal_mrpcim_initialize(__hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_mrpcim_terminate(__hal_device_t *hldev);
+
+void
+__hal_mrpcim_get_vpd_data(__hal_device_t *hldev);
+
+void
+__hal_mrpcim_xpak_counter_check(__hal_device_t *hldev,
+    u32 port, u32 type, u32 value);
+
+vxge_hal_status_e
+__hal_mrpcim_stats_get(
+    __hal_device_t *hldev,
+    vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats);
+
+vxge_hal_status_e
+__hal_mrpcim_mac_configure(__hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_mrpcim_lag_configure(__hal_device_t *hldev);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_MRPCIM_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h b/sys/dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h
new file mode 100644
index 000000000000..62ac39e4f98c
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h
@@ -0,0 +1,58 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_PCICFGMGMT_REGS_H
+#define	VXGE_HAL_PCICFGMGMT_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_pcicfgmgmt_reg_t {
+
+/* 0x00000 */	u64	resource_no;
+#define	VXGE_HAL_RESOURCE_NO_PFN_OR_VF	BIT(3)
+/* 0x00008 */	u64	bargrp_pf_or_vf_bar0_mask;
+#define	VXGE_HAL_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val)\
+							    vBIT(val, 2, 6)
+/* 0x00010 */	u64	bargrp_pf_or_vf_bar1_mask;
+#define	VXGE_HAL_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val)\
+							    vBIT(val, 2, 6)
+/* 0x00018 */	u64	bargrp_pf_or_vf_bar2_mask;
+#define	VXGE_HAL_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val)\
+							    vBIT(val, 2, 6)
+/* 0x00020 */	u64	msixgrp_no;
+#define	VXGE_HAL_MSIXGRP_NO_TABLE_SIZE(val)		    vBIT(val, 5, 11)
+
+} vxge_hal_pcicfgmgmt_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_PCICFGMGMT_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-regdefs.h b/sys/dev/vxge/vxgehal/vxgehal-regdefs.h
new file mode 100644
index 000000000000..9ba8e5751427
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-regdefs.h
@@ -0,0 +1,780 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_REGDEFS_H
+#define	VXGE_HAL_REGDEFS_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits)	bVAL16(bits, 0)
+#define	VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits)	bVAL8(bits, 48)
+#define	VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits)	bVAL8(bits, 56)
+
+#define	VXGE_HAL_VPD_LEN						80
+#define	VXGE_HAL_CARD_TITAN_VPD_ADDR					0x80
+#define	VPD_READ_COMPLETE						0x80
+
+#define	VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(bits)		bVAL5(bits, 3)
+
+#define	VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VHLABEL(bits)		bVAL5(bits, 3)
+#define	VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VPLANE(bits)		bVAL5(bits, 11)
+#define	VXGE_HAL_DEBUG_ASSIGNMENTS_GET_FUNC(bits)		bVAL5(bits, 19)
+
+#define	VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits)\
+							    bVAL3(bits, 5)
+#define	VXGE_HAL_VPLANE_ASSIGNMENTS_GET_VPLANE_ASSIGNMENTS(bits)    \
+							    bVAL5(bits, 3)
+
+#define	VXGE_HAL_PF_SW_RESET_COMMAND					0xA5
+
+#define	VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES				17
+#define	VXGE_HAL_TITAN_SRPCIM_REG_SPACES				17
+#define	VXGE_HAL_TITAN_VPMGMT_REG_SPACES				17
+#define	VXGE_HAL_TITAN_VPATH_REG_SPACES					17
+
+#define	VXGE_HAL_PRIV_VPATH_ACTION					5
+#define	VXGE_HAL_BW_CONTROL						12
+#define	VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_NON_PRIV_BANDWIDTH_CTRL	32
+#define	VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF			17
+#define	VXGE_HAL_API_FUNC_MODE_COMMIT					21
+
+#define	VXGE_HAL_ASIC_MODE_RESERVED					0
+#define	VXGE_HAL_ASIC_MODE_NO_IOV					1
+#define	VXGE_HAL_ASIC_MODE_SR_IOV					2
+#define	VXGE_HAL_ASIC_MODE_MR_IOV					3
+
+#define	VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN		mBIT(3)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE		mBIT(19)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH		mBIT(23)
+#define	VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS			mBIT(31)
+
+#define	VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits)	bVAL1(bits, 3)
+
+#define	VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits)	bVAL32(bits, 0)
+
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits)\
+							bVAL14(bits, 50)
+
+#define	VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits)	bVAL17(bits, 0)
+
+#define	VXGE_HAL_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits)\
+							bVAL5(bits, 3)
+
+#define	VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits)\
+							bVAL15(bits, 17)
+
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE			0
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY		1
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE		2
+
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY		0
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE		1
+
+#define	VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val)\
+					(val&~VXGE_HAL_TOC_KDFC_INITIAL_BIR(7))
+#define	VXGE_HAL_TOC_GET_KDFC_INITIAL_BIR(val)		    bVAL3(val, 61)
+#define	VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val)\
+					(val&~VXGE_HAL_TOC_USDC_INITIAL_BIR(7))
+#define	VXGE_HAL_TOC_GET_USDC_INITIAL_BIR(val)		    bVAL3(val, 61)
+
+#define	VXGE_HAL_LAG_CFG_GET_MODE(bits)			    bVAL2(bits, 6)
+#define	VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(bits)	    bVAL2(bits, 6)
+
+#define	VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits)	bits
+#define	VXGE_HAL_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits)	bits
+
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) bVAL15(bits, 1)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) bVAL15(bits, 17)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) bVAL15(bits, 33)
+
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val)  vBIT(val, 42, 5)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val)   vBIT(val, 47, 2)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) vBIT(val, 49, 15)
+
+#define	VXGE_HAL_PRC_CFG4_RING_MODE_ONE_BUFFER				0
+#define	VXGE_HAL_PRC_CFG4_RING_MODE_THREE_BUFFER			1
+#define	VXGE_HAL_PRC_CFG4_RING_MODE_FIVE_BUFFER				2
+
+#define	VXGE_HAL_PRC_CFG7_SCATTER_MODE_A				0
+#define	VXGE_HAL_PRC_CFG7_SCATTER_MODE_B				2
+#define	VXGE_HAL_PRC_CFG7_SCATTER_MODE_C				1
+
+#define	VXGE_HAL_RTDMA_BW_CTRL_GET_DESIRED_BW(bits)	    bVAL18(bits, 46)
+
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_WE_READ				0
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE				1
+
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA			0
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID			1
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE		2
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN			3
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN		4
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG		5
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT		6
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG	7
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK		8
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY		9
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS			10
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS			11
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT	12
+#define	VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO		13
+
+#define	VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits)  bVAL48(bits, 0)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val)	    vBIT(val, 0, 48)
+
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) bVAL48(bits, 0)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val)  vBIT(val, 0, 48)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE mBIT(54)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
+							    bVAL5(bits, 55)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)	vBIT(val, 55, 5)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
+							    bVAL2(bits, 62)
+#define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val)  vBIT(val, 62, 2)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY			0
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY		1
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY		2
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY		3
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY		0
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY		1
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_CLEAR_TABLE		2
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_VERSION		0
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO		3
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL		4
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_VPATH_MAP			5
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PCI_CONFIG		6
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_UDP_RTH			10
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FUNC_MODE			11
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG			15
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE		16
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL			17
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_INFO			18
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_COMMIT			21
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_COUNT		24
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE		29
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR			172
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA		0
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID		1
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE		2
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN		3
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG	5
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT	6
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG	7
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK		8
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY		9
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS		10
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS		11
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT	12
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO		13
+#define	VXGE_HAL_MSG_SEND_TO_VPATH_MASK				0xFFFFFFFFUL
+#define	VXGE_HAL_MSG_SEND_RETRY						100
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_MODE		2
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_DATA		3
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_COMMIT		4
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_STREAM_SKIP	    mBIT(63)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(bits) \
+							    bVAL8(bits, 56)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_OK	0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_DONE	1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_ERROR	2
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_SKIP	3
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_CODE(bits) \
+							    bVAL8(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SUB_SUB_CODE(bits) \
+							    bVAL8(bits, 40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(bits) \
+							    bVAL32(bits, 24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_TOTAL_STEPS(bits) \
+							    bVAL32(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_FW_UPGRADE_GET_COMPL_STEPS(bits) \
+							    bVAL32(bits, 32)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) bVAL48(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val)    vBIT(val, 0, 48)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits)   bVAL11(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(val)	    vBIT(val, 0, 12)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits)	    bVAL11(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(val)	    vBIT(val, 0, 16)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_TYPE(val)	vBIT(val, 0, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DEST(val)	vBIT(val, 8, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_SRC(val)    vBIT(val, 16, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DATA(val)    vBIT(val, 32, 32)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) bVAL1(bits, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL	    mBIT(3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) bVAL1(bits, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL	    mBIT(7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) bVAL16(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val)    vBIT(val, 8, 16)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) bVAL1(bits, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN	    mBIT(3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits)\
+							    bVAL4(bits, 4)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) vBIT(val, 4, 4)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits)\
+							    bVAL2(bits, 10)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) vBIT(val, 10, 2)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS	0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS	1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C	2
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits)\
+							    bVAL1(bits, 15)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN	mBIT(15)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits)\
+							    bVAL1(bits, 19)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN mBIT(19)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits)\
+							    bVAL1(bits, 23)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN	mBIT(23)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits)\
+							    bVAL1(bits, 27)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN mBIT(27)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits)\
+							    bVAL1(bits, 31)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN mBIT(31)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits)\
+							    bVAL1(bits, 35)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN	mBIT(35)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits)\
+							    bVAL1(bits, 39)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE mBIT(39)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits)\
+							    bVAL1(bits, 43)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN mBIT(43)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits)\
+							    bVAL1(bits, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN mBIT(3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits)\
+							    bVAL7(bits, 9)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val)\
+							    vBIT(val, 9, 7)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val)\
+							    vBIT(val, 0, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits)\
+							    bVAL1(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN  mBIT(8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits)\
+							    bVAL7(bits, 9)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits)\
+							    bVAL8(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val)\
+							    vBIT(val, 16, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits)\
+							    bVAL1(bits, 24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN  mBIT(24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits)\
+							    bVAL7(bits, 25)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val)\
+							    vBIT(val, 0, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits)\
+							    bVAL1(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN  mBIT(8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits)\
+							    bVAL7(bits, 9)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits)\
+							    bVAL8(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val)\
+							    vBIT(val, 16, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits)\
+							    bVAL1(bits, 24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN  mBIT(24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits)\
+							    bVAL7(bits, 25)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val)\
+							    vBIT(val, 25, 7)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits)\
+							    bVAL32(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits)\
+							    bVAL32(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val)\
+							    vBIT(val, 32, 32)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits)\
+							    bVAL16(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val)\
+							    vBIT(val, 0, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits)\
+							    bVAL16(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits)\
+							    bVAL4(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val)\
+							    vBIT(val, 32, 4)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits)\
+							    bVAL4(bits, 36)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val)\
+							    vBIT(val, 36, 4)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits)\
+							    bVAL2(bits, 40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val)	vBIT(val, 40, 2)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits)\
+							    bVAL2(bits, 42)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val)	vBIT(val, 42, 2)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits)	bVAL64(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY		vBIT(val, 0, 64)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits)	bVAL1(bits, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN		mBIT(3)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits)	bVAL1(bits, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN		mBIT(3)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)\
+								bVAL48(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val)	vBIT(val, 0, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE	mBIT(54)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)\
+							    bVAL5(bits, 55)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)\
+							    vBIT(val, 55, 5)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)\
+							    bVAL2(bits, 62)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val)	vBIT(val, 62, 2)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val)\
+							    vBIT(val, 0, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits)\
+							    bVAL1(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN  mBIT(8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits)\
+							    bVAL7(bits, 9)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val)\
+							    vBIT(val, 9, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits)\
+							    bVAL8(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val)\
+							    vBIT(val, 16, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits)\
+							    bVAL1(bits, 24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN  mBIT(24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits)\
+							    bVAL7(bits, 25)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val)\
+							    vBIT(val, 25, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits)\
+							    bVAL8(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val)\
+							    vBIT(val, 32, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits)\
+							    bVAL1(bits, 40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN  mBIT(40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits)\
+							    bVAL7(bits, 41)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val)\
+							    vBIT(val, 41, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits)\
+							    bVAL8(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val)\
+							    vBIT(val, 48, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits)\
+							    bVAL1(bits, 56)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN  mBIT(56)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits)\
+							    bVAL7(bits, 57)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val)\
+							    vBIT(val, 57, 7)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FW_VERSION		0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER		0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER		1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FLASH_VERSION		2
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE		3
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0		4
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1		5
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2		6
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3		7
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS			8
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE	10
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR	11
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO	13
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO	14
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE	20
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR	21
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO	23
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO	24
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_LAG_MODE		1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_ACTIVE_PORT		2
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(bits)	\
+							    bVAL8(bits, 56)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS(val)		\
+							    vBIT(val, 56, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_SUCCESS	1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_FAIL		0
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_GET_LAG_MODE(bits)	\
+							    bVAL3(bits, 61)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_LAG_MODE(val)		\
+							    vBIT(val, 61, 3)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_PREFFERRED_PORT   mBIT(62)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_ACTIVE_PORT	    mBIT(63)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON			1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF			0
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_ADDR(bits)  bVAL16(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_ADDR(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_CONFIG_READ			0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_CONFIG_WRITE	    mBIT(39)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_BYTE_COUNT(bits) bVAL8(bits, 40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_BYTE_COUNT(val)	    vBIT(val, 40, 8)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VH(bits)	    bVAL8(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VH(val)		    vBIT(val, 48, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNCTION(bits)  bVAL8(bits, 56)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNCTION(val)	    vBIT(val, 56, 8)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PCI_DATA(bits)  bVAL32(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_DATA(val)	    vBIT(val, 32, 32)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_PCI_DATA(bits)  bVAL32(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_PCI_DATA(val)	    vBIT(val, 32, 32)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_IS_VPATH_ASSIGNED(vpid) mBIT((63-vpid))
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_IGNORE_IN_SVC_CHECK mBIT(0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_TYPE(bits)  bVAL7(bits, 1)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_UNKNOWN		0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN	1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END	2
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN	3
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END	4
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP		5
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN	6
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_ACK			127
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DEST(bits)  bVAL8(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DEST(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_MRPCIM	    0xfe
+#define	VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST	    0xff
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_SRC(bits)   bVAL8(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_SRC(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_SEQ_NUM(bits)   bVAL32(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEQ_NUM(val)	    vBIT(val, 32, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MSG_DATA(bits)  bVAL16(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DATA(val)	    vBIT(val, 48, 16)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_ERROR_PENDING	0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_ERROR_NOT_IN_SVC	1
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_UDP_RTH_ENABLE		mBIT(63)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VHN(val)		vBIT(val, 48, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VFID(val)		vBIT(val, 56, 8)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(bits)	bVAL3(bits, 45)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MIN_BW(bits)	bVAL8(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(bits)	bVAL8(bits, 56)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(val)	vBIT(val, 45, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MIN_BW(val)	vBIT(val, 48, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(val)	vBIT(val, 56, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(val)	vBIT(val, 0, 8)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_PRIORITY(bits)	bVAL3(bits, 21)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MIN_BW(bits)	bVAL8(bits, 24)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_TX_MAX_BW(bits)	bVAL8(bits, 32)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(val)	vBIT(val, 21, 3)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MIN_BW(val)	vBIT(val, 24, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(val)	vBIT(val, 32, 8)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(bits)	bVAL8(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(bits)	bVAL8(bits, 56)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE(val)		vBIT(val, 56, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SF1_VP17	0
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8_VP2	1
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR17_VP1	2
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR17_VP1	3
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR8_VP2	4
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF17_VP1	5
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR8_VP2	6
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR4_VP4	7
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF2_VP8	8
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF4_VP4	9
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR4_VP4	10
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8P_VP2	11
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val)	vBIT(val, 0, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits)\
+							    bVAL8(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val)   vBIT(val, 8, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) bVAL16(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val)    vBIT(val, 16, 16)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits)\
+							    bVAL8(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR	vBIT(val, 32, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits)\
+							    bVAL8(bits, 40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR	vBIT(val, 40, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits)\
+							    bVAL16(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD	vBIT(val, 48, 16)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_DAY(val)  vBIT(val, 0, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(bits)\
+							    bVAL8(bits, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MONTH(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(bits)\
+							    bVAL16(bits, 16)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_YEAR(val) vBIT(val, 16, 16)
+
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(bits)\
+							    bVAL8(bits, 32)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MAJOR	    vBIT(val, 32, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(bits)\
+							    bVAL8(bits, 40)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MINOR	    vBIT(val, 40, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(bits)\
+							    bVAL16(bits, 48)
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_BUILD	    vBIT(val, 48, 16)
+
+/* Netork port control API related */
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(val)	vBIT(val, 0, 8)
+
+/* Bandwidth & priority related MACROS */
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_API_VER(bits) \
+							vxge_bVALn(bits, 0, 8)
+
+#define	VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_SHOW_PORT_INFO(bits)\
+							    bVAL1(bits, 55)
+#define	VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_PORT_NUM(bits) bVAL1(bits, 63)
+
+#define	VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_GET_ALARM(bits)  bVAL17(bits, 0)
+
+#define	VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) bVAL16(bits, 48)
+#define	VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits)\
+							    bVAL32(bits, 32)
+#define	VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(bits)	    bVAL16(bits, 48)
+#define	VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(bits)	    bVAL16(bits, 48)
+#define	VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(bits)		    bVAL9(bits, 36)
+#define	VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) bVAL32(bits, 0)
+#define	VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) bVAL32(bits, 0)
+#define	VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) bVAL32(bits, 0)
+#define	VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits)
+#define	VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits)
+#define	VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) bVAL32(bits, 32)
+#define	VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) bVAL32(bits, 32)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits)\
+							    bVAL32(bits, 0)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits)\
+							    bVAL32(bits, 32)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits)\
+							    bVAL32(bits, 0)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits)\
+							    bVAL32(bits, 32)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits)\
+							    bVAL32(bits, 0)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits)\
+							    bVAL32(bits, 32)
+#define	\
+    VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits)\
+							    bVAL16(bits, 48)
+#define	VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits)   bVAL16(bits, 0)
+#define	VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits)   bVAL16(bits, 16)
+#define	VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits)   bVAL16(bits, 32)
+#define	VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits)	    bVAL16(bits, 0)
+#define	VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits)\
+							    bVAL16(bits, 16)
+#define	VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) bVAL16(bits, 32)
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR			0x0
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_WRITE			0x1
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ_INCR			0x2
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ			0x3
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_RESERVED			0x4
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE		0x5
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ_INCR		0x6
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ			0x7
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1		0x0000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_PMA_CONTROL_1_LOOPBACK	0x01
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL		0x8000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_1_BYTE	0x02
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_256_BYTES	0x03
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_COMPLETE	0x04
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_PROGRESS	0x08
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_FAILED	0x0C
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_STAT_MASK	0x0C
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_READ	0x00
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_WRITE	0x20
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_ADDR(val)	(val<<8)
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_1	0x8067
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_XFP_TEMP_2	0x8068
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_DATA(val)\
+							    (val&0xff)
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG		0xA070
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_LOW	0x01
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_HIGH	0x02
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_LOW	0x04
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_HIGH	0x08
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_LOW	0x40
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_HIGH	0x80
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG		0xA074
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_LOW	0x01
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_HIGH	0x02
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_LOW	0x04
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_HIGH	0x08
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_LOW	0x40
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_HIGH	0x80
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT			0xA100
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_SINGLE_UPDATE	0x0000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_SLOW_PER_UPDATE	0x0001
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_INT_PER_UPDATE	0x0002
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_FAST_PER_UPDATE	0x0003
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_IDLE	0x0000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_COMPLETE	0x0004
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_PROGRESS	0x0008
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_READ_FAILED	0x000C
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_UPLOAD_EN	0x0010
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_256_BYTES	0x0000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_1_BYTES		0x0100
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_IDLE	0x0000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_COMPLETE	0x1000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_PROGRESS	0x2000
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT_WRITE_FAILED	0x3000
+
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_TX_LED			0xD006
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_RX_LED			0xD007
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_LINK_LED			0xD008
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD			1
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PCS				3
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PHY_XS			4
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_DTE_XS			5
+#define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_AN				7
+
+#define	VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(bits) bVAL5(bits, 19)
+#define	VXGE_HAL_MDIO_GEN_CFG_PORT_MDIO_PHY_PRTAD(val)	    vBIT(val, 19, 5)
+
+#define	VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(bits) bVAL5(bits, 7)
+#define	VXGE_HAL_XGXS_STATIC_CFG_PORT_MDIO_DTE_PRTAD(val)   vBIT(val, 7, 5)
+
+#define	VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(bits)	    bVAL16(bits, 32)
+
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits)  bVAL32(bits, 0)
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits)  bVAL32(bits, 32)
+#define	\
+    VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits)\
+							    bVAL32(bits, 32)
+#define	\
+    VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits)\
+							    bVAL32(bits, 32)
+#define	\
+    VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits)\
+							    bVAL32(bits, 32)
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) bVAL32(bits, 0)
+#define	VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) bVAL32(bits, 32)
+#define	VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) bVAL32(bits, 0)
+#define	VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) bVAL32(bits, 32)
+#define	VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) bVAL32(bits, 0)
+#define	VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) bVAL32(bits, 32)
+#define	VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits)  bVAL32(bits, 32)
+#define	VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits)  bVAL32(bits, 32)
+
+#define	VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(bits)	    bVAL32(bits, 0)
+#define	VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(bits)	    bVAL32(bits, 32)
+#define	VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits)	    bVAL32(bits, 0)
+#define	VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits)	    bVAL32(bits, 32)
+#define	VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits)	    bVAL32(bits, 0)
+#define	VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits)	    bVAL16(bits, 0)
+#define	VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits)	    bVAL16(bits, 16)
+#define	VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits)    bVAL16(bits, 32)
+#define	VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits)	    bVAL16(bits, 0)
+#define	VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits)	    bVAL16(bits, 16)
+#define	VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits)    bVAL16(bits, 32)
+
+#define	VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(bits)    (bits)
+#define	VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(bits)	    (bits)
+#define	VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(bits) (bits)
+#define	VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits)\
+							    bVAL32(bits, 32)
+
+#define	VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits)\
+							    bVAL8(bits, 8)
+#define	VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits)\
+							    bVAL8(bits, 16)
+
+#define	VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits)\
+							    bVAL8(bits, 0)
+#define	VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits)\
+							    bVAL8(bits, 8)
+#define	VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits)\
+							    bVAL8(bits, 16)
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_REGDEFS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-regs.h b/sys/dev/vxge/vxgehal/vxgehal-regs.h
new file mode 100644
index 000000000000..52cef7420706
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-regs.h
@@ -0,0 +1,1231 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_REGS_H
+#define	VXGE_HAL_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+#pragma pack(1)
+/* Using this strcture to calculate offsets */
+typedef struct vxge_hal_pci_config_le_t {
+	u16	vendor_id;		/* 0x00 */
+	u16	device_id;		/* 0x02 */
+
+	u16	command;		/* 0x04 */
+	u16	status;			/* 0x06 */
+
+	u8	revision;		/* 0x08 */
+	u8	pciClass[3];		/* 0x09 */
+
+	u8	cache_line_size;	/* 0x0c */
+	u8	latency_timer;		/* 0x0d */
+	u8	header_type;		/* 0x0e */
+	u8	bist;			/* 0x0f */
+
+	u32	base_addr0_lo;		/* 0x10 */
+	u32	base_addr0_hi;		/* 0x14 */
+
+	u32	base_addr1_lo;		/* 0x18 */
+	u32	base_addr1_hi;		/* 0x1C */
+
+	u32	base_addr2_lo;		/* 0x20 */
+	u32	base_addr2_hi;		/* 0x24 */
+
+	u32	cardbus_cis_pointer;	/* 0x28 */
+
+	u16	subsystem_vendor_id;	/* 0x2c */
+	u16	subsystem_id;		/* 0x2e */
+
+	u32	rom_base;		/* 0x30 */
+	u8	capabilities_pointer;	/* 0x34 */
+	u8	rsvd_35[3];		/* 0x35 */
+	u32	rsvd_38;		/* 0x38 */
+
+	u8	interrupt_line;		/* 0x3c */
+	u8	interrupt_pin;		/* 0x3d */
+	u8	min_grant;		/* 0x3e */
+	u8	max_latency;		/* 0x3f */
+
+	u8	rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40];
+} vxge_hal_pci_config_le_t;	/* 0x100 */
+
+typedef struct vxge_hal_pci_config_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u16	device_id;		/* 0x02 */
+	u16	vendor_id;		/* 0x00 */
+
+	u16	status;			/* 0x06 */
+	u16	command;		/* 0x04 */
+
+	u8	pciClass[3];		/* 0x09 */
+	u8	revision;		/* 0x08 */
+
+	u8	bist;			/* 0x0f */
+	u8	header_type;		/* 0x0e */
+	u8	latency_timer;		/* 0x0d */
+	u8	cache_line_size;	/* 0x0c */
+
+	u32	base_addr0_lo;		/* 0x10 */
+	u32	base_addr0_hi;		/* 0x14 */
+
+	u32	base_addr1_lo;		/* 0x18 */
+	u32	base_addr1_hi;		/* 0x1C */
+
+	u32	not_Implemented1;	/* 0x20 */
+	u32	not_Implemented2;	/* 0x24 */
+
+	u32	cardbus_cis_pointer;	/* 0x28 */
+
+	u16	subsystem_id;		/* 0x2e */
+	u16	subsystem_vendor_id;	/* 0x2c */
+
+	u32	rom_base;		/* 0x30 */
+	u8	rsvd_35[3];		/* 0x35 */
+	u8	capabilities_pointer;	/* 0x34 */
+	u32	rsvd_38;		/* 0x38 */
+
+	u8	max_latency;		/* 0x3f */
+	u8	min_grant;		/* 0x3e */
+	u8	interrupt_pin;		/* 0x3d */
+	u8	interrupt_line;		/* 0x3c */
+#else
+	u16	vendor_id;		/* 0x00 */
+	u16	device_id;		/* 0x02 */
+
+	u16	command;		/* 0x04 */
+	u16	status;			/* 0x06 */
+
+	u8	revision;		/* 0x08 */
+	u8	pciClass[3];		/* 0x09 */
+
+	u8	cache_line_size;	/* 0x0c */
+	u8	latency_timer;		/* 0x0d */
+	u8	header_type;		/* 0x0e */
+	u8	bist;			/* 0x0f */
+
+	u32	base_addr0_lo;		/* 0x10 */
+	u32	base_addr0_hi;		/* 0x14 */
+
+	u32	base_addr1_lo;		/* 0x18 */
+	u32	base_addr1_hi;		/* 0x1C */
+
+	u32	not_Implemented1;	/* 0x20 */
+	u32	not_Implemented2;	/* 0x24 */
+
+	u32	cardbus_cis_pointer;	/* 0x28 */
+
+	u16	subsystem_vendor_id;	/* 0x2c */
+	u16	subsystem_id;		/* 0x2e */
+
+	u32	rom_base;		/* 0x30 */
+	u8	capabilities_pointer;	/* 0x34 */
+	u8	rsvd_35[3];		/* 0x35 */
+	u32	rsvd_38;		/* 0x38 */
+
+	u8	interrupt_line;		/* 0x3c */
+	u8	interrupt_pin;		/* 0x3d */
+	u8	min_grant;		/* 0x3e */
+	u8	max_latency;		/* 0x3f */
+
+#endif
+	u8	rsvd_b1[VXGE_HAL_PCI_CONFIG_SPACE_SIZE - 0x40];
+} vxge_hal_pci_config_t;	/* 0x100 */
+
+#define	VXGE_HAL_EEPROM_SIZE	(0x01 << 11)
+
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+#define	VXGE_HAL_PCI_CAP_ID(ptr)	*((ptr) + 3)
+#define	VXGE_HAL_PCI_CAP_NEXT(ptr)	*((ptr) + 2)
+#else
+#define	VXGE_HAL_PCI_CAP_ID(ptr)	*(ptr)
+#define	VXGE_HAL_PCI_CAP_NEXT(ptr)	*((ptr) + 1)
+#endif
+
+/* Capability lists */
+
+#define	VXGE_HAL_PCI_CAP_LIST_ID	0	/* Capability ID */
+#define	VXGE_HAL_PCI_CAP_ID_PM		0x01	/* Power Management */
+#define	VXGE_HAL_PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
+#define	VXGE_HAL_PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
+#define	VXGE_HAL_PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
+#define	VXGE_HAL_PCI_CAP_ID_MSI		0x05	/* Message Signalled Intr */
+#define	VXGE_HAL_PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
+#define	VXGE_HAL_PCI_CAP_ID_PCIX	0x07	/* PCIX */
+#define	VXGE_HAL_PCI_CAP_ID_HT		0x08	/* Hypertransport */
+#define	VXGE_HAL_PCI_CAP_ID_VS		0x09	/* Vendor Specific */
+#define	VXGE_HAL_PCI_CAP_ID_DBGPORT	0x0A	/* Debug Port */
+#define	VXGE_HAL_PCI_CAP_ID_CPCICSR	0x0B	/* CompPCI central res ctrl */
+#define	VXGE_HAL_PCI_CAP_ID_SHPC	0x0C	/* PCI Standard Hot-Plug Ctrl */
+#define	VXGE_HAL_PCI_CAP_ID_PCIBSVID	0x0D	/* PCI Bridge Subsys Vendr Id */
+#define	VXGE_HAL_PCI_CAP_ID_AGP8X	0x0E	/* AGP 8x */
+#define	VXGE_HAL_PCI_CAP_ID_SECDEV	0x0F	/* Secure Device */
+#define	VXGE_HAL_PCI_CAP_ID_PCIE	0x10	/* PCI Express */
+#define	VXGE_HAL_PCI_CAP_ID_MSIX	0x11	/* MSI-X */
+#define	VXGE_HAL_PCI_CAP_LIST_NEXT	1	/* Next cap in the list */
+#define	VXGE_HAL_PCI_CAP_FLAGS		2	/* Cap defined flags(16 bits) */
+
+typedef struct vxge_hal_pm_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	capabilities_reg;
+#define	VXGE_HAL_PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define	VXGE_HAL_PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
+#define	VXGE_HAL_PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
+#define	VXGE_HAL_PCI_PM_CAP_DSI		0x0020	/* Device specific init */
+#define	VXGE_HAL_PCI_PM_AUX_CURRENT	0x01C0	/* Auxiliary current reqs */
+#define	VXGE_HAL_PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define	VXGE_HAL_PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D0	0x0800	/* PME# assertable from D0 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D1	0x1000	/* PME# assertable from D1 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D2	0x2000	/* PME# assertable from D2 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D3_HOT	0x4000	/* PME# assertable from D3hot */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D3_COLD	0x8000	/* PME# assertable from D3cold */
+	u16	pm_ctrl;
+#define	VXGE_HAL_PCI_PM_CTRL_STATE_MASK	0x0003	/* Curr power state(D0 to D3) */
+#define	VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008	/* trans from D3hot to D0 */
+#define	VXGE_HAL_PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
+#define	VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00	/* Data select (??) */
+#define	VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000	/* Data scale (??) */
+#define	VXGE_HAL_PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
+	u8	pm_ppb_ext;
+#define	VXGE_HAL_PCI_PM_PPB_B2_B3	0x40	/* Stop clk when in D3hot(??) */
+#define	VXGE_HAL_PCI_PM_BPCC_ENABLE	0x80	/* Bus pwr/clk ctrl enable(??) */
+	u8	pm_data_reg;
+} vxge_hal_pm_capability_le_t;
+
+typedef struct vxge_hal_pm_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u16	capabilities_reg;
+#define	VXGE_HAL_PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define	VXGE_HAL_PCI_PM_CAP_PME_CLOCK   0x0008	/* PME clock required */
+#define	VXGE_HAL_PCI_PM_CAP_AUX_POWER   0x0010	/* Auxilliary power support */
+#define	VXGE_HAL_PCI_PM_CAP_DSI		0x0020	/* Dev specific init */
+#define	VXGE_HAL_PCI_PM_AUX_CURRENT	0x01C0	/* Auxiliary current reqs */
+#define	VXGE_HAL_PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define	VXGE_HAL_PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D0	0x0800	/* PME# assertable from D0 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D1	0x1000	/* PME# assertable from D1 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D2	0x2000	/* PME# assertable from D2 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D3_HOT  0x4000	/* PME# assertable from D3hot */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000	/* PME# assertable from D3cold */
+	u8	next_capability_ptr;
+	u8	capability_id;
+	u8	pm_data_reg;
+	u8	pm_ppb_ext;
+#define	VXGE_HAL_PCI_PM_PPB_B2_B3	0x40	/* Stop clk when in D3hot(??) */
+#define	VXGE_HAL_PCI_PM_BPCC_ENABLE	0x80	/* Bus pwr/clk ctrl enable(??) */
+	u16	pm_ctrl;
+#define	VXGE_HAL_PCI_PM_CTRL_STATE_MASK	0x0003	/* Curr pwr state (D0 to D3) */
+#define	VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008	/* dev trans D3hot to D0 */
+#define	VXGE_HAL_PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
+#define	VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK  0x1e00	/* Data select (??) */
+#define	VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000	/* Data scale (??) */
+#define	VXGE_HAL_PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	capabilities_reg;
+#define	VXGE_HAL_PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define	VXGE_HAL_PCI_PM_CAP_PME_CLOCK   0x0008	/* PME clock required */
+#define	VXGE_HAL_PCI_PM_CAP_AUX_POWER   0x0010	/* Auxilliary power support */
+#define	VXGE_HAL_PCI_PM_CAP_DSI		0x0020	/* Dev specific init */
+#define	VXGE_HAL_PCI_PM_AUX_CURRENT	0x01C0	/* Auxiliary curr reqs */
+#define	VXGE_HAL_PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define	VXGE_HAL_PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D0	0x0800	/* PME# assertable from D0 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D1	0x1000	/* PME# assertable from D1 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D2	0x2000	/* PME# assertable from D2 */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D3_HOT  0x4000	/* PME# assertable from D3hot */
+#define	VXGE_HAL_PCI_PM_CAP_PME_D3_COLD 0x8000	/* PME# assertable from D3cold */
+	u16	pm_ctrl;
+#define	VXGE_HAL_PCI_PM_CTRL_STATE_MASK	0x0003	/* Curr pwr state (D0 to D3) */
+#define	VXGE_HAL_PCI_PM_CTRL_NO_SOFT_RESET 0x0008	/* dev trans D3hot to D0 */
+#define	VXGE_HAL_PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
+#define	VXGE_HAL_PCI_PM_CTRL_DATA_SEL_MASK 0x1e00	/* Data select (??) */
+#define	VXGE_HAL_PCI_PM_CTRL_DATA_SCALE_MASK 0x6000	/* Data scale (??) */
+#define	VXGE_HAL_PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
+	u8	pm_ppb_ext;
+#define	VXGE_HAL_PCI_PM_PPB_B2_B3	0x40	/* Stop clk when in D3hot(??) */
+#define	VXGE_HAL_PCI_PM_BPCC_ENABLE	0x80	/* Bus pwr/clk ctrl enable(??) */
+	u8	pm_data_reg;
+#endif
+} vxge_hal_pm_capability_t;
+
+typedef struct vxge_hal_vpid_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	vpd_address;
+#define	VXGE_HAL_PCI_VPID_COMPL_FALG	0x8000	/* Read Completion Flag */
+	u32	vpd_data;
+} vxge_hal_vpid_capability_le_t;
+
+typedef struct vxge_hal_vpid_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u16	vpd_address;
+#define	VXGE_HAL_PCI_VPID_COMPL_FALG	0x8000	/* Read Completion Flag */
+	u8	next_capability_ptr;
+	u8	capability_id;
+	u32	vpd_data;
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	vpd_address;
+#define	VXGE_HAL_PCI_VPID_COMPL_FALG	0x8000	/* Read Completion Flag */
+	u32	vpd_data;
+#endif
+} vxge_hal_vpid_capability_t;
+
+typedef struct vxge_hal_sid_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u8	sid_esr;
+#define	VXGE_HAL_PCI_SID_ESR_NSLOTS	0x1f	/* Num of exp slots avail */
+#define	VXGE_HAL_PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+	u8	sid_chasis_nr;
+} vxge_hal_sid_capability_le_t;
+
+typedef struct vxge_hal_sid_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u8	sid_chasis_nr;
+	u8	sid_esr;
+#define	VXGE_HAL_PCI_SID_ESR_NSLOTS	0x1f	/* Num of exp slots avail */
+#define	VXGE_HAL_PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+	u8	next_capability_ptr;
+	u8	capability_id;
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u8	sid_esr;
+#define	VXGE_HAL_PCI_SID_ESR_NSLOTS	0x1f	/* Num of exp slots avail */
+#define	VXGE_HAL_PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+	u8	sid_chasis_nr;
+#endif
+} vxge_hal_sid_capability_t;
+
+typedef struct vxge_hal_msi_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	msi_control;
+#define	VXGE_HAL_PCI_MSI_FLAGS_PVMASK	0x0100	/* Per Vector Masking Capable */
+#define	VXGE_HAL_PCI_MSI_FLAGS_64BIT	0x0080	/* 64-bit addresses allowed */
+#define	VXGE_HAL_PCI_MSI_FLAGS_QSIZE	0x0070	/* Msg queue size configured */
+#define	VXGE_HAL_PCI_MSI_FLAGS_QMASK	0x000e	/* Max queue size available */
+#define	VXGE_HAL_PCI_MSI_FLAGS_ENABLE   0x0001	/* MSI feature enabled */
+	union {
+		struct {
+			u32	msi_addr;
+			u16	msi_data;
+			u16	msi_unused;
+		} ma32_no_pvm;
+		struct {
+			u32	msi_addr;
+			u16	msi_data;
+			u16	msi_unused;
+			u32	msi_mask;
+			u32	msi_pending;
+		} ma32_pvm;
+		struct {
+			u32	msi_addr_lo;
+			u32	msi_addr_hi;
+			u16	msi_data;
+			u16	msi_unused;
+		} ma64_no_pvm;
+		struct {
+			u32	msi_addr_lo;
+			u32	msi_addr_hi;
+			u16	msi_data;
+			u16	msi_unused;
+			u32	msi_mask;
+			u32	msi_pending;
+		} ma64_pvm;
+	} au;
+} vxge_hal_msi_capability_le_t;
+
+typedef struct vxge_hal_msi_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u16	msi_control;
+#define	VXGE_HAL_PCI_MSI_FLAGS_PVMASK	0x0100	/* Per Vector Masking Capable */
+#define	VXGE_HAL_PCI_MSI_FLAGS_64BIT	0x0080	/* 64-bit addresses allowed */
+#define	VXGE_HAL_PCI_MSI_FLAGS_QSIZE	0x0070	/* Msg queue size configured */
+#define	VXGE_HAL_PCI_MSI_FLAGS_QMASK	0x000e	/* Max queue size available */
+#define	VXGE_HAL_PCI_MSI_FLAGS_ENABLE   0x0001	/* MSI feature enabled */
+	u8	next_capability_ptr;
+	u8	capability_id;
+	union {
+		struct {
+			u32	msi_addr;
+			u16	msi_unused;
+			u16	msi_data;
+		} ma32_no_pvm;
+		struct {
+			u32	msi_addr;
+			u16	msi_unused;
+			u16	msi_data;
+			u32	msi_mask;
+			u32	msi_pending;
+		} ma32_pvm;
+		struct {
+			u32	msi_addr_lo;
+			u32	msi_addr_hi;
+			u16	msi_unused;
+			u16	msi_data;
+		} ma64_no_pvm;
+		struct {
+			u32	msi_addr_lo;
+			u32	msi_addr_hi;
+			u16	msi_unused;
+			u16	msi_data;
+			u32	msi_mask;
+			u32	msi_pending;
+		} ma64_pvm;
+	} au;
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	msi_control;
+#define	VXGE_HAL_PCI_MSI_FLAGS_PVMASK	0x0100	/* Per Vector Masking Capable */
+#define	VXGE_HAL_PCI_MSI_FLAGS_64BIT	0x0080	/* 64-bit addresses allowed */
+#define	VXGE_HAL_PCI_MSI_FLAGS_QSIZE	0x0070	/* Msg queue size configured */
+#define	VXGE_HAL_PCI_MSI_FLAGS_QMASK	0x000e	/* Max queue size available */
+#define	VXGE_HAL_PCI_MSI_FLAGS_ENABLE   0x0001	/* MSI feature enabled */
+	union {
+		struct {
+			u32	msi_addr;
+			u16	msi_data;
+			u16	msi_unused;
+		} ma32_no_pvm;
+		struct {
+			u32	msi_addr;
+			u16	msi_data;
+			u16	msi_unused;
+			u32	msi_mask;
+			u32	msi_pending;
+		} ma32_pvm;
+		struct {
+			u32	msi_addr_lo;
+			u32	msi_addr_hi;
+			u16	msi_data;
+			u16	msi_unused;
+		} ma64_no_pvm;
+		struct {
+			u32	msi_addr_lo;
+			u32	msi_addr_hi;
+			u16	msi_data;
+			u16	msi_unused;
+			u32	msi_mask;
+			u32	msi_pending;
+		} ma64_pvm;
+	} au;
+#endif
+} vxge_hal_msi_capability_t;
+
+typedef struct vxge_hal_chswp_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u8	chswp_csr;
+#define	VXGE_HAL_PCI_CHSWP_DHA	 0x01	/* Device Hiding Arm */
+#define	VXGE_HAL_PCI_CHSWP_EIM	 0x02	/* ENUM# Signal Mask */
+#define	VXGE_HAL_PCI_CHSWP_PIE	 0x04	/* Pending Insert or Extract */
+#define	VXGE_HAL_PCI_CHSWP_LOO	 0x08	/* LED On / Off */
+#define	VXGE_HAL_PCI_CHSWP_PI	  0x30	/* Programming Interface */
+#define	VXGE_HAL_PCI_CHSWP_EXT	 0x40	/* ENUM# status - extraction */
+#define	VXGE_HAL_PCI_CHSWP_INS	 0x80	/* ENUM# status - insertion */
+} vxge_hal_chswp_capability_le_t;
+
+typedef struct vxge_hal_chswp_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u8	chswp_csr;
+#define	VXGE_HAL_PCI_CHSWP_DHA	 0x01	/* Device Hiding Arm */
+#define	VXGE_HAL_PCI_CHSWP_EIM	 0x02	/* ENUM# Signal Mask */
+#define	VXGE_HAL_PCI_CHSWP_PIE	 0x04	/* Pending Insert or Extract */
+#define	VXGE_HAL_PCI_CHSWP_LOO	 0x08	/* LED On / Off */
+#define	VXGE_HAL_PCI_CHSWP_PI	  0x30	/* Programming Interface */
+#define	VXGE_HAL_PCI_CHSWP_EXT	 0x40	/* ENUM# status - extraction */
+#define	VXGE_HAL_PCI_CHSWP_INS	 0x80	/* ENUM# status - insertion */
+	u8	next_capability_ptr;
+	u8	capability_id;
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u8	chswp_csr;
+#define	VXGE_HAL_PCI_CHSWP_DHA	 0x01	/* Device Hiding Arm */
+#define	VXGE_HAL_PCI_CHSWP_EIM	 0x02	/* ENUM# Signal Mask */
+#define	VXGE_HAL_PCI_CHSWP_PIE	 0x04	/* Pending Insert or Extract */
+#define	VXGE_HAL_PCI_CHSWP_LOO	 0x08	/* LED On / Off */
+#define	VXGE_HAL_PCI_CHSWP_PI	  0x30	/* Programming Interface */
+#define	VXGE_HAL_PCI_CHSWP_EXT	 0x40	/* ENUM# status - extraction */
+#define	VXGE_HAL_PCI_CHSWP_INS	 0x80	/* ENUM# status - insertion */
+#endif
+} vxge_hal_chswp_capability_t;
+
+typedef struct vxge_hal_shpc_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+} vxge_hal_shpc_capability_le_t;
+
+typedef struct vxge_hal_shpc_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u8	next_capability_ptr;
+	u8	capability_id;
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+#endif
+} vxge_hal_shpc_capability_t;
+
+typedef struct vxge_hal_msix_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	msix_control;
+#define	VXGE_HAL_PCI_MSIX_FLAGS_ENABLE	0x8000	/* MSIX Enable */
+#define	VXGE_HAL_PCI_MSIX_FLAGS_MASK	0x4000	/* Mask all vectors */
+#define	VXGE_HAL_PCI_MSIX_FLAGS_TSIZE	0x001f	/* Table Size */
+	u32	table_offset;
+#define	VXGE_HAL_PCI_MSIX_TABLE_OFFSET	0xFFFFFFF8	/* Table offset mask */
+#define	VXGE_HAL_PCI_MSIX_TABLE_BIR	0x00000007	/* Table BIR mask */
+	u32	pba_offset;
+#define	VXGE_HAL_PCI_MSIX_PBA_OFFSET	0xFFFFFFF8	/* Table offset mask */
+#define	VXGE_HAL_PCI_MSIX_PBA_BIR	0x00000007	/* Table BIR mask */
+} vxge_hal_msix_capability_le_t;
+
+typedef struct vxge_hal_msix_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u16	msix_control;
+#define	VXGE_HAL_PCI_MSIX_FLAGS_ENABLE	0x8000	/* MSIX Enable */
+#define	VXGE_HAL_PCI_MSIX_FLAGS_MASK	0x4000	/* Mask all vectors */
+#define	VXGE_HAL_PCI_MSIX_FLAGS_TSIZE	0x001f	/* Table Size */
+	u8	next_capability_ptr;
+	u8	capability_id;
+	u32	table_offset;
+#define	VXGE_HAL_PCI_MSIX_TABLE_OFFSET	0xFFFFFFF8	/* Table offset mask */
+#define	VXGE_HAL_PCI_MSIX_TABLE_BIR	0x00000007	/* Table BIR mask */
+	u32	pba_offset;
+#define	VXGE_HAL_PCI_MSIX_PBA_OFFSET	0xFFFFFFF8	/* Table offset mask */
+#define	VXGE_HAL_PCI_MSIX_PBA_BIR	0x00000007	/* Table BIR mask */
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	msix_control;
+#define	VXGE_HAL_PCI_MSIX_FLAGS_ENABLE	0x8000	/* MSIX Enable */
+#define	VXGE_HAL_PCI_MSIX_FLAGS_MASK	0x4000	/* Mask all vectors */
+#define	VXGE_HAL_PCI_MSIX_FLAGS_TSIZE	0x001f	/* Table Size */
+	u32	table_offset;
+#define	VXGE_HAL_PCI_MSIX_TABLE_OFFSET	0xFFFFFFF8	/* Table offset mask */
+#define	VXGE_HAL_PCI_MSIX_TABLE_BIR	0x00000007	/* Table BIR mask */
+	u32	pba_offset;
+#define	VXGE_HAL_PCI_MSIX_PBA_OFFSET	0xFFFFFFF8	/* Table offset mask */
+#define	VXGE_HAL_PCI_MSIX_PBA_BIR	0x00000007	/* Table BIR mask */
+#endif
+} vxge_hal_msix_capability_t;
+
+typedef struct vxge_hal_pci_caps_offset_t {
+	u32	pm_cap_offset;
+	u32	vpd_cap_offset;
+	u32	sid_cap_offset;
+	u32	msi_cap_offset;
+	u32	vs_cap_offset;
+	u32	shpc_cap_offset;
+	u32	msix_cap_offset;
+} vxge_hal_pci_caps_offset_t;
+
+typedef struct vxge_hal_pci_e_capability_le_t {
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	pci_e_flags;
+#define	VXGE_HAL_PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
+#define	VXGE_HAL_PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
+#define	VXGE_HAL_PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
+#define	VXGE_HAL_PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
+#define	VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT	0x4	/* Root Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
+#define	VXGE_HAL_PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
+#define	VXGE_HAL_PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt msg number */
+	u32	pci_e_devcap;
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07	/* Max_Payload_Size */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18	/* Phantom functions */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20	/* Extended tags */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Ind Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000	/* Slot Power Limit Value */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000	/* Slot Power Limit Scale */
+	u16	pci_e_devctl;
+#define	VXGE_HAL_PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Err Report En. */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_NFERE   0x0002	/* Non-Fatal Err Report En */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Report En */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Req Report En. */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010	/* Enable relaxed ordering */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800	/* Enable No Snoop */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+	u16	pci_e_devsta;
+#define	VXGE_HAL_PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Req Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
+	u32	pci_e_lnkcap;
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5	0x1	/* 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LS_5	0x2	/* 5 and 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_RES	0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X1	0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X2	0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X4	0x4	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X8	0x8	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X12	0xa	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X16	0x10	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X32	0x20	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM  0xc00	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1  0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO	0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2  0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT	0x7000	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64	0x0	/* Less than 64ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128   0x1	/* 64ns to less than 128ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256  0x2	/* 128ns to less than 256ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512  0x3	/* 256ns to less than 512ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us  0x4	/* 512ns to less than 1s. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us  0x5	/* 1s to less than 2s. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us  0x6	/* 2s-4s. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us   0x7	/* More than 4s. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT	    0x38000	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us   0x0	/* Less than 1us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us  0x1	/* 1us to less than 2us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us  0x2	/* 2us to less than 4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us  0x3	/* 4us to less than 8us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4	/* 8us to less than 16us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5	/* 16us to less than 32us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6	/* 32us-64us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us   0x7	/* More than 64us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000	/* Clk power management. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000	/* Down error capable. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP  0x100000	/* DL active rep cap. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP   0x200000	/* DL bw reporting cap. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000	/* Port number. */
+	u16	pci_e_lnkctl;
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM	    0x3	/* ASPM Control. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0	/* Disabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN  0x1	/* L0 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN  0x2	/* L1 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3	/* L0 & L1 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB	    0x8	/* Read Completion Boundary. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB_64	    0x0	/* RCB 64 bytes. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB_128	    0x1	/* RCB 128 bytes. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_DISABLED    0x10	/* Disables the link. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN	    0x20	/* Retrain the link. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_CCCFG	    0x40	/* Common clock config. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC    0x80	/* Extended Sync. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100	/* Enable clk pwr mgmt. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200	/* Hw autonomous with dis */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400	/* Bw mgt interrupt enable */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800	/* Autonomous BW intr en */
+	u16	pci_e_lnksta;
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED   0xf	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5	    0x1	/* 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LS_5	    0x2	/* 5 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH   0x3f0	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_RES	    0x0		/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X1	    0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X2	    0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X4	    0x4	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X8	    0x8	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X12	    0xa	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X16	    0x10	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X32	    0x20	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN   0x800	/* Link training. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG    0x1000	/* Slot Clock Config. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE  0x2000	/* Data LL Active. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA	    0x4000	/* Bw mgmt intr enable */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA	    0x8000	/* Autonomous BW intr en */
+	u32	pci_e_stlcap;
+#define	VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN   0x1	/* Attention Button Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL    0x2	/* Power Control Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS    0x4	/* MRL Sesor Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND    0x8	/* Attention Ind Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PWR_IND	    0x10	/* Power Indicator Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_HP_SURP	    0x20	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_HP_CAP	    0x40	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL  0x7F80	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250  0xF0	/* 250 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275  0xF1	/* 275 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300  0xF2	/* 300 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM  0x18000	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X   0x0	/* 1.0x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1	/* 0.1x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2	/* 0.01x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3	/* 0.001x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000	/* Ele-mec Intrlock Pres */
+#define	VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL  0x40000	/* No Cmd Compl Support */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO   0xFFF80000	/* Phys Slot Number */
+	u16	pci_e_stlctl;
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN  0x1	/* Atten Btn pressed enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN    0x2	/* Power Fault Detected En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN  0x4	/* MRL Sensor Changed Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN   0x8	/* Presence Detect Change En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN   0x10	/* Cmd Compl Intr Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN   0x20	/* Hot-Plug Intr Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0	/* Attention Ind Control */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES  0x0	/* Reserved */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON   0x1	/* On */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2	/* Blink */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF  0x3	/* Off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300	/* POwer Indicator Control */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES  0x0	/* Reserved */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON   0x1	/* On */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2	/* Blink */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF  0x3	/* Off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400	/* Power Controller Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on   0x0	/* Power on */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off  0x1	/* Power off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL   0x800	/* Ele-mec Interlock Crl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000	/* DL Layer State Ch En */
+	u16	pci_e_stlsta;
+#define	VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN    0x1	/* Attention Button Pressed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PF_DET	    0x2	/* Power Fault Detected */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4	/* MRL Sensor Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_CH	    0x8	/* Presence Detect Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL   0x10	/* Command Completed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20	/* MRL Sensor State */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0	/* MRL Sensor State - closed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1	/* MRL Sensor State - open */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_STA    0x400	/* Presence Detect State */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY  0x0	/* Clost Empty */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1	/* Card Present */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA   0x80	/* Ele-mec Intrlock Control */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS   0x0	/* Disengaged */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN    0x1	/* Engaged */
+#define	VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH   0x100	/* DL Layer State Changed */
+	u16	pci_e_rtctl;
+#define	VXGE_HAL_PCI_EXP_RTCTL_SECEE	0x01	/* Sys Err on Correctable Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_SENFEE	0x02	/* Sys Err on Non-Fatal Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_SEFEE	0x04	/* Sys Err on Fatal Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_PMEIE	0x08	/* PME Interrupt Enable */
+#define	VXGE_HAL_PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS SW Visibility Enable */
+	u16	pci_e_rtcap;
+#define	VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS   0x01	/* CRS SW Visibility */
+	u32	pci_e_rtsta;
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID   0xFFFF	/* PME Requestor ID */
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS   0x10000	/* PME status */
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING  0x20000	/* PME Pending */
+} vxge_hal_pci_e_capability_le_t;
+
+typedef struct vxge_hal_pci_e_capability_t {
+#if defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u16	pci_e_flags;
+#define	VXGE_HAL_PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
+#define	VXGE_HAL_PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
+#define	VXGE_HAL_PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
+#define	VXGE_HAL_PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
+#define	VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT	0x4	/* Root Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
+#define	VXGE_HAL_PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
+#define	VXGE_HAL_PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
+	u8	next_capability_ptr;
+	u8	capability_id;
+	u32	pci_e_devcap;
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Ind Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000	/* Slot Power Limit Value */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL	0xc000000	/* Slot Power Limit Scale */
+	u16	pci_e_devsta;
+#define	VXGE_HAL_PCI_EXP_DEVSTA_CED	0x01	/* Correctable Err Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Req Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
+	u16	pci_e_devctl;
+#define	VXGE_HAL_PCI_EXP_DEVCTL_CERE	0x0001	/* Corr'ble Err Reporting En. */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Err Reporting En */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting En */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupp Req Reporting En. */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010	/* Enable relaxed ordering */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800	/* Enable No Snoop */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+	u32	pci_e_lnkcap;
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5	  0x1	/* 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LS_5	  0x2	/* 5 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_RES	  0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X1	  0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X2	  0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X4	  0x4	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X8	  0x8	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X12	  0xa	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X16	  0x10	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X32	  0x20	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM  0xc00	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1 0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO  0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT	  0x7000	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64  0x0	/* Less than 64 ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128 0x1	/* 64 ns to less than 128 ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2	/* 128 ns to less than 256 ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512 0x3	/* 256 ns to less than 512 ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us 0x4	/* 512 ns to less than 1us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us 0x5	/* 1us to less than 2us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us 0x6	/* 2us-4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us  0x7	/* More than 4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT	   0x38000	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us  0x0	/* Less than 1us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us   0x1	/* 1us to less than 2us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us   0x2	/* 2us to less than 4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us   0x3	/* 4us to less than 8us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us  0x4	/* 8us to less than 16us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5	/* 16us to less than 32us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6	/* 32us-64s. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us   0x7	/* More than 64us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000	/* Clk power management. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000	/* Down error capable. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP  0x100000	/* DL active rep cap. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP   0x200000	/* DL bw rep cap. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000	/* Port number. */
+	u16	pci_e_lnksta;
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED  0xf	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5	   0x1	/* 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LS_5	   0x2	/* 5 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH  0x3f0	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_RES	   0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X1	   0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X2	   0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X4	   0x4	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X8	   0x8	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X12	   0xa	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X16	   0x10	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X32	   0x20	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN  0x800	/* Link training. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG   0x1000	/* Slot Clock Config. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE 0x2000	/* Data LL Active. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA	   0x4000	/* Bw mgmt interrupt enable */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA	   0x8000	/* Autonomous BW intr en */
+	u16	pci_e_lnkctl;
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM		0x3	/* ASPM Control. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED	0x0	/* Disabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN	0x1	/* L0 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN	0x2	/* L1 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN	0x3	/* L0 & L1 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB		0x8	/* Read Compl Boundary. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB_64		0x0	/* RCB 64 bytes. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB_128		0x1	/* RCB 128 bytes. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_DISABLED	0x10	/* Disables the link. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN		0x20	/* Retrain the link. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_CCCFG		0x40	/* Common clock config. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC	0x80	/* Extended Sync. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT	0x100	/* Enable clk pwr mgmt. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS	0x200	/* Hw autonomous w/dis */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN	0x400	/* Bw mgmt intr enable */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN	0x800	/* Autonomous BW int en */
+	u32	pci_e_stlcap;
+#define	VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN   0x1	/* Attention Button Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL    0x2	/* Power Control Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS    0x4	/* MRL Sesor Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND    0x8	/* Attention Ind Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PWR_IND	    0x10	/* Power Indicator Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_HP_SURP	    0x20	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_HP_CAP	    0x40	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL  0x7F80	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250  0xF0	/* 250 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275  0xF1	/* 275 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300  0xF2	/* 300 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM  0x18000	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X   0x0	/* 1.0x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1	/* 0.1x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2	/* 0.01x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3	/* 0.001x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000	/* Ele-mec Intrlock Pres */
+#define	VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000	/* No Command Compl Supp */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO   0xFFF80000	/* Phy Slot Number */
+	u16	pci_e_stlsta;
+#define	VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN    0x1	/* Attention Button Pressed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PF_DET	    0x2	/* Power Fault Detected */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4	/* MRL Sensor Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_CH	    0x8	/* Presence Detect Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL   0x10	/* Command Completed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20	/* MRL Sensor State */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0	/* MRL Sensor State - closed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1	/* MRL Sensor State - open */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_STA    0x400	/* Presence Detect State */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY  0x0	/* Clost Empty */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1	/* Card Present */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA   0x80	/* Ele-mec Intrlock Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS   0x0	/* Disengaged */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN    0x1	/* Engaged */
+#define	VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH   0x100	/* DL State Changed */
+	u16	pci_e_stlctl;
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1	/* Atten Btn pressed en */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN   0x2	/* Pwr Fault Detected En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4	/* MRL Sensor Changed En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN  0x8	/* Presence Detect Changed En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN  0x10	/* Cmmd Completed Intr En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN  0x20	/* Hot-Plug Intr Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0	/* Attention Ind Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0	/* Reserved */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON  0x1	/* On */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2	/* Blink */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3	/* Off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300	/* POwer Ind Control */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0	/* Reserved */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON  0x1	/* On */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2	/* Blink */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3	/* Off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400	/* Power Controller Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on  0x0	/* Power on */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1	/* Power off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL  0x800	/* Ele-mec Intrlock Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000	/* DL State Changed En */
+	u16	pci_e_rtcap;
+#define	VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS 0x01	/* CRS Software Visibility */
+	u16	pci_e_rtctl;
+#define	VXGE_HAL_PCI_EXP_RTCTL_SECEE	0x01	/* Sys Err on Correctable Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_SENFEE	0x02	/* Sys Err on Non-Fatal Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_SEFEE	0x04	/* Sys Err on Fatal Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_PMEIE	0x08	/* PME Intr Enable */
+#define	VXGE_HAL_PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS SW Visibility Enable */
+	u32	pci_e_rtsta;
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID   0xFFFF	/* PME Requestor ID */
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS   0x10000	/* PME status */
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING  0x20000	/* PME Pending */
+#else
+	u8	capability_id;
+	u8	next_capability_ptr;
+	u16	pci_e_flags;
+#define	VXGE_HAL_PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
+#define	VXGE_HAL_PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
+#define	VXGE_HAL_PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
+#define	VXGE_HAL_PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
+#define	VXGE_HAL_PCI_EXP_TYPE_ROOT_PORT	0x4	/* Root Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
+#define	VXGE_HAL_PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
+#define	VXGE_HAL_PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
+#define	VXGE_HAL_PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
+	u32	pci_e_devcap;
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PAYLOAD 0x07	/* Max_Payload_Size */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PHANTOM 0x18	/* Phantom functions */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_EXT_TAG 0x20	/* Extended tags */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_ATN_BUT 0x1000	/* Attention Button Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_ATN_IND 0x2000	/* Attention Ind Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_IND 0x4000	/* Power Indicator Present */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000	/* Slot Power Limit Value */
+#define	VXGE_HAL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000	/* Slot Power Limit Scale */
+	u16	pci_e_devctl;
+#define	VXGE_HAL_PCI_EXP_DEVCTL_CERE	0x0001	/* Corr'ble Err Reporting En. */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Err Reporting En */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Err Reporting En */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupp Req Reporting En. */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_RELAX_EN 0x0010	/* Enable relaxed ordering */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0	/* Max_Payload_Size */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_EXT_TAG 0x0100	/* Extended Tag Field Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_PHANTOM 0x0200	/* Phantom Functions Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_AUX_PME 0x0400	/* Auxiliary Power PM Enable */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800	/* Enable No Snoop */
+#define	VXGE_HAL_PCI_EXP_DEVCTL_READRQ  0x7000	/* Max_Read_Request_Size */
+	u16	pci_e_devsta;
+#define	VXGE_HAL_PCI_EXP_DEVSTA_CED	 0x01	/* Correctable Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_FED	 0x04	/* Fatal Error Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_URD	 0x08	/* Unsupp Request Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_AUXPD   0x10	/* AUX Power Detected */
+#define	VXGE_HAL_PCI_EXP_DEVSTA_TRPND   0x20	/* Transactions Pending */
+	u32	pci_e_lnkcap;
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_SPEED 0xf	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LS_2_5	0x1	/* 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LS_5	0x2	/* 5 and 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_RES  0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X1   0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X2   0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X4   0x4	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X8   0x8	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X12  0xa	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X16  0x10	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LW_X32  0x20	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_ASPM  0xc00	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES1  0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_LO    0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2  0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LASPM_L0_L1 0x3	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_LAT	    0x7000	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_LT_64    0x0	/* Less than 64 ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_64_128   0x1	/* 64ns to less than 128ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256  0x2	/* 128ns to less than 256ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_256_512  0x3	/* 256ns to less than 512ns. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_512_1us  0x4	/* 512ns to less than 1us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_1us_2us  0x5	/* 1us to less than 2us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_2us_4us  0x6	/* 2us-4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L0_GT_4us   0x7	/* More than 4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_LAT	    0x38000	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_LT_1us   0x0	/* Less than 1us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_1us_2us  0x1	/* 1us to less than 2us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us  0x2	/* 2us to less than 4us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_4us_8us  0x3	/* 4us to less than 8us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_8us_16us 0x4	/* 8us to less than 16us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_16us_32us 0x5	/* 16us to less than 32us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_32us_64us 0x6	/* 32us-64us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_L1_GT_64us   0x7	/* More than 64us. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_CLK_PWR_MGMT 0x40000	/* Clock power mgmt */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_DOWN_ERR_CAP 0x80000	/* Down error capable. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_ACT_CAP  0x100000	/* DL active rep cap. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_BW_CAP   0x200000	/* DL bw rep cap. */
+#define	VXGE_HAL_PCI_EXP_LNKCAP_LNK_PORT_NUM 0xff000000	/* Port number. */
+	u16	pci_e_lnkctl;
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM	    0x3	/* ASPM Control. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_DISABLED 0x0	/* Disabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_EN  0x1	/* L0 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN  0x2	/* L1 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L0_L1_EN 0x3	/* L0 & L1 entry enabled. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB	    0x8	/* Read Completion Boundary. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB_64	    0x0	/* RCB 64 bytes. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RCB_128	    0x1	/* RCB 128 bytes. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_DISABLED    0x10	/* Disables the link. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_RETRAIN	    0x20	/* Retrain the link. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_CCCFG	    0x40	/* Common clock config. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_EXT_SYNC    0x80	/* Extended Sync. */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_CLK_PWRMGMT 0x100	/* Enable clock power mgmt */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_HW_AUTO_DIS 0x200	/* HW autonomous with dis */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_BWM_INTR_EN 0x400	/* Bw mgmt interrupt enable */
+#define	VXGE_HAL_PCI_EXP_LNKCTL_ABW_INTR_EN 0x800	/* Autonomous BW int enable */
+	u16	pci_e_lnksta;
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_SPEED   0xf	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LS_2_5	    0x1	/* 2.5 Gb/s supported. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LS_5	    0x2	/* 5 and 2.5 Gb/s supported */
+	/* Supported Link speeds. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_WIDTH   0x3f0
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_RES	    0x0	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X1	    0x1	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X2	    0x2	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X4	    0x4	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X8	    0x8	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X12	    0xa	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X16	    0x10	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LW_X32	    0x20	/* Reserved. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_LNK_TRAIN   0x800	/* Link training. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_SCLK_CFG    0x1000	/* Slot Clock Config. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_DLL_ACTIVE  0x2000	/* Data LL Active. */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_BWM_STA	    0x4000	/* Bw mgmt intr enable */
+#define	VXGE_HAL_PCI_EXP_LNKSTA_ABW_STA	    0x8000	/* Autonomous BW intr en */
+	u32	pci_e_stlcap;
+#define	VXGE_HAL_PCI_EXP_STLCAP_ATTN_BTTN   0x1	/* Attention Button Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL    0x2	/* Power Control Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_MRL_SENS    0x4	/* MRL Sesor Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_ATTN_IND    0x8	/* Attention Ind Present */
+	/* Power Indicator Present */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PWR_IND	    0x10
+#define	VXGE_HAL_PCI_EXP_STLCAP_HP_SURP	    0x20	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_HP_CAP	    0x40	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_VAL  0x7F80	/* Hot-Plug Surprise */
+	/* 250 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_250  0xF0
+	/* 275 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_275  0xF1
+	/* 300 W Slot Power Limit */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_300  0xF2
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_LIM  0x18000	/* Hot-Plug Surprise */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_1X   0x0	/* 1.0x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY10 0x1	/* 0.1x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2	/* 0.01x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY1000 0x3	/* 0.001x */
+#define	VXGE_HAL_PCI_EXP_STLCAP_EM_INTR_LOCK 0x20000	/* Ele-mec Intrlock Pres */
+#define	VXGE_HAL_PCI_EXP_STLCAP_NO_CMD_CMPL 0x40000	/* No Cmd Completed Supp */
+#define	VXGE_HAL_PCI_EXP_STLCAP_PHY_SL_NO   0xFFF80000	/* Phys Slot Number */
+	u16	pci_e_stlctl;
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATTN_BTN_EN 0x1	/* Atten Bttn pressed en */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PF_DET_EN   0x2	/* Power Fault Detected En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_MRL_SENS_EN 0x4	/* MRL Sensor Changed Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PDET_CH_EN  0x8	/* Presence Detect Changed En */
+#define	VXGE_HAL_PCI_EXP_STLCTL_CC_INTR_EN  0x10	/* Cmd Compl Intr Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_HP_INTR_EN  0x20	/* Hot-Plug Intr Enable */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_CTRL 0xC0	/* Atten Ind Control */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_RES 0x0	/* Reserved */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_ON  0x1	/* On */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_BLNK 0x2	/* Blink */
+#define	VXGE_HAL_PCI_EXP_STLCTL_ATN_IND_OFF 0x3	/* Off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_CTRL 0x300	/* Power Ind Control */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_RES 0x0	/* Reserved */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_ON  0x1	/* On */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_BLNK 0x2	/* Blink */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWR_IND_OFF 0x3	/* Off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_CTRL 0x400	/* Power Controller Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_on  0x0	/* Power on */
+#define	VXGE_HAL_PCI_EXP_STLCTL_PWRCTRL_off 0x1	/* Power off */
+#define	VXGE_HAL_PCI_EXP_STLCTL_EM_IL_CTRL  0x800	/* Ele-mec Intrlock Ctrl */
+#define	VXGE_HAL_PCI_EXP_STLCTL_DLL_ST_CH_EN 0x1000	/* DL State Changed En */
+	u16	pci_e_stlsta;
+#define	VXGE_HAL_PCI_EXP_STLSTA_ATTN_BTN    0x1	/* Attention Button Pressed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PF_DET	    0x2	/* Power Fault Detected */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CH 0x4	/* MRL Sensor Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_CH	    0x8	/* Presence Detect Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_CMD_COMPL   0x10	/* Command Completed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_STA 0x20	/* MRL Sensor State */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_CL 0x0	/* MRL Sensor State - closed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_MRL_SENS_OP 0x1	/* MRL Sensor State - open */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_STA    0x400	/* Presence Detect State */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_EMPTY  0x0	/* Clost Empty */
+#define	VXGE_HAL_PCI_EXP_STLSTA_PDET_PRESENT 0x1	/* Card Present */
+	/* Ele-mec Interlock Control */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_STA   0x80
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_DIS   0x0	/* Disengaged */
+#define	VXGE_HAL_PCI_EXP_STLSTA_EM_IL_EN    0x1	/* Engaged */
+	/* DL Layer State Changed */
+#define	VXGE_HAL_PCI_EXP_STLSTA_DLL_ST_CH   0x100
+	u16	pci_e_rtctl;
+#define	VXGE_HAL_PCI_EXP_RTCTL_SECEE	0x01	/* Sys Err on Correctable Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_SENFEE	0x02	/* Sys Err on Non-Fatal Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_SEFEE	0x04	/* Sys Err on Fatal Error */
+#define	VXGE_HAL_PCI_EXP_RTCTL_PMEIE	0x08	/* PME Interrupt Enable */
+#define	VXGE_HAL_PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS SW Visibility Enable */
+	u16	pci_e_rtcap;
+#define	VXGE_HAL_PCI_EXP_RTCAP_CRS_SW_VIS   0x01	/* CRS SW Visibility */
+	u32	pci_e_rtsta;
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_REQ_ID   0xFFFF	/* PME Requestor ID */
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_STATUS   0x10000	/* PME status */
+#define	VXGE_HAL_PCI_EXP_RTSTA_PME_PENDING  0x20000	/* PME Pending */
+#endif
+} vxge_hal_pci_e_capability_t;
+
+typedef u32 vxge_hal_pci_e_caps_offset_t;
+
+#define	VXGE_HAL_PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
+#define	VXGE_HAL_PCI_EXT_CAP_VER(header)	((header >> 16) & 0xf)
+#define	VXGE_HAL_PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
+
+#define	VXGE_HAL_PCI_EXT_CAP_ID_ERR	    1
+#define	VXGE_HAL_PCI_EXT_CAP_ID_VC	    2
+#define	VXGE_HAL_PCI_EXT_CAP_ID_DSN	    3
+#define	VXGE_HAL_PCI_EXT_CAP_ID_PWR	    4
+
+typedef struct vxge_hal_err_capability_t {
+	u32	pci_err_header;
+	u32	pci_err_uncor_status;
+#define	VXGE_HAL_PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
+#define	VXGE_HAL_PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
+#define	VXGE_HAL_PCI_ERR_UNC_POISON_TLP 0x00001000	/* Poisoned TLP */
+#define	VXGE_HAL_PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
+#define	VXGE_HAL_PCI_ERR_UNC_COMP_TIME  0x00004000	/* Completion Timeout */
+#define	VXGE_HAL_PCI_ERR_UNC_COMP_ABORT 0x00008000	/* Completer Abort */
+#define	VXGE_HAL_PCI_ERR_UNC_UNX_COMP   0x00010000	/* Unexpected Completion */
+#define	VXGE_HAL_PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
+#define	VXGE_HAL_PCI_ERR_UNC_MALF_TLP   0x00040000	/* Malformed TLP */
+#define	VXGE_HAL_PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
+#define	VXGE_HAL_PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
+	u32	pci_err_uncor_mask;
+	u32	pci_err_uncor_server;
+	u32	pci_err_cor_status;
+#define	VXGE_HAL_PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
+#define	VXGE_HAL_PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
+#define	VXGE_HAL_PCI_ERR_COR_BAD_DLLP   0x00000080	/* Bad DLLP Status */
+#define	VXGE_HAL_PCI_ERR_COR_REP_ROLL   0x00000100	/* REPLAY_NUM Rollover */
+#define	VXGE_HAL_PCI_ERR_COR_REP_TIMER  0x00001000	/* Replay Timer Timeout */
+#define	VXGE_HAL_PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
+	u32	pci_err_cap;
+#define	VXGE_HAL_PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
+	/* ECRC Generation Capable */
+#define	VXGE_HAL_PCI_ERR_CAP_ECRC_GENC  0x00000020
+
+#define	VXGE_HAL_PCI_ERR_CAP_ECRC_GENE  0x00000040	/* ECRC Generation Enable */
+#define	VXGE_HAL_PCI_ERR_CAP_ECRC_CHKC  0x00000080	/* ECRC Check Capable */
+#define	VXGE_HAL_PCI_ERR_CAP_ECRC_CHKE  0x00000100	/* ECRC Check Enable */
+	u32	err_header_log;
+#define	VXGE_HAL_PCI_ERR_HEADER_LOG(x)  ((x) >> 31)	/* Error Header Log */
+	u32	unused2[3];
+	u32	pci_err_root_command;
+	u32	pci_err_root_status;
+	u32	pci_err_root_cor_src;
+	u32	pci_err_root_src;
+} vxge_hal_err_capability_t;
+
+typedef struct vxge_hal_vc_capability_t {
+	u32	pci_vc_header;
+	u32	pci_vc_port_reg1;
+	u32	pci_vc_port_reg2;
+	u32	pci_vc_port_ctrl;
+	u32	pci_vc_port_status;
+	u32	pci_vc_res_cap;
+	u32	pci_vc_res_ctrl;
+	u32	pci_vc_res_status;
+} vxge_hal_vc_capability_t;
+
+typedef struct vxge_hal_pwr_budget_capability_t {
+	u32	pci_pwr_header;
+	u32	pci_pwr_dsr;
+	u32	pci_pwr_data;
+#define	VXGE_HAL_PCI_PWR_DATA_BASE(x)   ((x) & 0xff)	/* Base Power */
+#define	VXGE_HAL_PCI_PWR_DATA_SCALE(x)  (((x) >> 8) & 3)	/* Data Scale */
+#define	VXGE_HAL_PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7)	/* PM Sub State */
+#define	VXGE_HAL_PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3)	/* PM State */
+#define	VXGE_HAL_PCI_PWR_DATA_TYPE(x)   (((x) >> 15) & 7)	/* Type */
+#define	VXGE_HAL_PCI_PWR_DATA_RAIL(x)   (((x) >> 18) & 7)	/* Power Rail */
+	u32	pci_pwr_cap;
+#define	VXGE_HAL_PCI_PWR_CAP_BUDGET(x)  ((x) & 1)	/* Include in sys budget */
+} vxge_hal_pwr_budget_capability_t;
+
+typedef struct vxge_hal_pci_e_ext_caps_offset_t {
+	u32	err_cap_offset;
+	u32	vc_cap_offset;
+	u32	dsn_cap_offset;
+	u32	pwr_budget_cap_offset;
+} vxge_hal_pci_e_ext_caps_offset_t;
+
+#pragma pack()
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-ring.c b/sys/dev/vxge/vxgehal/vxgehal-ring.c
new file mode 100644
index 000000000000..bcfa078e778a
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-ring.c
@@ -0,0 +1,1813 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * __hal_ring_block_memblock_idx - Return the memblock index
+ * @block: Virtual address of memory block
+ *
+ * This function returns the index of memory block
+ */
+static inline u32
+__hal_ring_block_memblock_idx(
+    vxge_hal_ring_block_t block)
+{
+	return (u32)*((u64 *) ((void *)((u8 *) block +
+	    VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET)));
+}
+
+/*
+ * __hal_ring_block_memblock_idx_set - Sets the memblock index
+ * @block: Virtual address of memory block
+ * @memblock_idx: Index of memory block
+ *
+ * This function sets index to a memory block
+ */
+static inline void
+__hal_ring_block_memblock_idx_set(
+    vxge_hal_ring_block_t block,
+    u32 memblock_idx)
+{
+	*((u64 *) ((void *)((u8 *) block +
+	    VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET))) = memblock_idx;
+}
+
+/*
+ * __hal_ring_block_next_pointer - Returns the dma address of next block
+ * @block: RxD block
+ *
+ * Returns the dma address of next block stored in the RxD block
+ */
+static inline dma_addr_t
+/* LINTED */
+__hal_ring_block_next_pointer(
+    vxge_hal_ring_block_t *block)
+{
+	return (dma_addr_t)*((u64 *) ((void *)((u8 *) block +
+	    VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET)));
+}
+
+/*
+ * __hal_ring_block_next_pointer_set - Sets the next block pointer in RxD block
+ * @block: RxD block
+ * @dma_next: dma address of next block
+ *
+ * Sets the next block pointer in RxD block
+ */
+static inline void
+__hal_ring_block_next_pointer_set(
+    vxge_hal_ring_block_t *block,
+    dma_addr_t dma_next)
+{
+	*((u64 *) ((void *)((u8 *) block +
+	    VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET))) = dma_next;
+}
+
+/*
+ * __hal_ring_first_block_address_get - Returns the dma address of the
+ *		first block
+ * @ringh: Handle to the ring
+ *
+ * Returns the dma address of the first RxD block
+ */
+u64
+__hal_ring_first_block_address_get(
+    vxge_hal_ring_h ringh)
+{
+	__hal_ring_t *ring = (__hal_ring_t *) ringh;
+	vxge_hal_mempool_dma_t *dma_object;
+
+	dma_object = __hal_mempool_memblock_dma(ring->mempool, 0);
+
+	vxge_assert(dma_object != NULL);
+
+	return (dma_object->addr);
+}
+
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+/*
+ * __hal_ring_item_dma_offset - Return the dma offset of an item
+ * @mempoolh: Handle to the memory pool of the ring
+ * @item: Item for which to get the dma offset
+ *
+ * This function returns the dma offset of a given item
+ */
+static ptrdiff_t
+__hal_ring_item_dma_offset(
+    vxge_hal_mempool_h mempoolh,
+    void *item)
+{
+	u32 memblock_idx;
+	void *memblock;
+	vxge_hal_mempool_t *mempool = (vxge_hal_mempool_t *) mempoolh;
+	__hal_device_t *hldev;
+
+	vxge_assert((mempoolh != NULL) && (item != NULL) &&
+	    (dma_handle != NULL));
+
+	hldev = (__hal_device_t *) mempool->devh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "mempoolh = 0x"VXGE_OS_STXFMT", item = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) mempoolh, (ptr_t) item);
+
+	/* get owner memblock index */
+	memblock_idx = __hal_ring_block_memblock_idx(item);
+
+	/* get owner memblock by memblock index */
+	memblock = __hal_mempool_memblock(mempoolh, memblock_idx);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return ((u8 *) item - (u8 *) memblock);
+}
+#endif
+
+/*
+ * __hal_ring_item_dma_addr - Return the dma address of an item
+ * @mempoolh: Handle to the memory pool of the ring
+ * @item: Item for which to get the dma offset
+ * @dma_handle: dma handle
+ *
+ * This function returns the dma address of a given item
+ */
+static dma_addr_t
+__hal_ring_item_dma_addr(
+    vxge_hal_mempool_h mempoolh,
+    void *item,
+    pci_dma_h *dma_handle)
+{
+	u32 memblock_idx;
+	void *memblock;
+	vxge_hal_mempool_dma_t *memblock_dma_object;
+	vxge_hal_mempool_t *mempool = (vxge_hal_mempool_t *) mempoolh;
+	__hal_device_t *hldev;
+	ptrdiff_t dma_item_offset;
+
+	vxge_assert((mempoolh != NULL) && (item != NULL) &&
+	    (dma_handle != NULL));
+
+	hldev = (__hal_device_t *) mempool->devh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "mempoolh = 0x"VXGE_OS_STXFMT", item = 0x"VXGE_OS_STXFMT", "
+	    "dma_handle = 0x"VXGE_OS_STXFMT, (ptr_t) mempoolh,
+	    (ptr_t) item, (ptr_t) dma_handle);
+
+	/* get owner memblock index */
+	memblock_idx = __hal_ring_block_memblock_idx((u8 *) item);
+
+	/* get owner memblock by memblock index */
+	memblock = __hal_mempool_memblock(
+	    (vxge_hal_mempool_t *) mempoolh, memblock_idx);
+
+	/* get memblock DMA object by memblock index */
+	memblock_dma_object = __hal_mempool_memblock_dma(
+	    (vxge_hal_mempool_t *) mempoolh, memblock_idx);
+
+	/* calculate offset in the memblock of this item */
+	/* LINTED */
+	dma_item_offset = (u8 *) item - (u8 *) memblock;
+
+	*dma_handle = memblock_dma_object->handle;
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (memblock_dma_object->addr + dma_item_offset);
+}
+
+/*
+ * __hal_ring_rxdblock_link - Link the RxD blocks
+ * @mempoolh: Handle to the memory pool of the ring
+ * @ring: ring
+ * @from: RxD block from which to link
+ * @to: RxD block to which to link to
+ *
+ * This function returns the dma address of a given item
+ */
+static void
+__hal_ring_rxdblock_link(
+    vxge_hal_mempool_h mempoolh,
+    __hal_ring_t *ring,
+    u32 from,
+    u32 to)
+{
+	vxge_hal_ring_block_t *to_item, *from_item;
+	dma_addr_t to_dma, from_dma;
+	pci_dma_h to_dma_handle, from_dma_handle;
+	__hal_device_t *hldev;
+
+	vxge_assert((mempoolh != NULL) && (ring != NULL));
+
+	hldev = (__hal_device_t *) ring->channel.devh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "mempoolh = 0x"VXGE_OS_STXFMT", ring = 0x"VXGE_OS_STXFMT", "
+	    "from = %d, to = %d", (ptr_t) mempoolh, (ptr_t) ring, from, to);
+
+	/* get "from" RxD block */
+	from_item = (vxge_hal_ring_block_t *) __hal_mempool_item(
+	    (vxge_hal_mempool_t *) mempoolh, from);
+	vxge_assert(from_item);
+
+	/* get "to" RxD block */
+	to_item = (vxge_hal_ring_block_t *) __hal_mempool_item(
+	    (vxge_hal_mempool_t *) mempoolh, to);
+	vxge_assert(to_item);
+
+	/* return address of the beginning of previous RxD block */
+	to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle);
+
+	/*
+	 * set next pointer for this RxD block to point on
+	 * previous item's DMA start address
+	 */
+	__hal_ring_block_next_pointer_set(from_item, to_dma);
+
+	/* return "from" RxD block's DMA start address */
+	from_dma = __hal_ring_item_dma_addr(
+	    mempoolh, from_item, &from_dma_handle);
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+	/* we must sync "from" RxD block, so hardware will see it */
+	vxge_os_dma_sync(ring->channel.pdev,
+	    from_dma_handle,
+	    from_dma + VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
+	    __hal_ring_item_dma_offset(mempoolh, from_item) +
+	    VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET,
+	    sizeof(u64),
+	    VXGE_OS_DMA_DIR_TODEVICE);
+#endif
+
+	vxge_hal_info_log_ring(
+	    "block%d:0x"VXGE_OS_STXFMT" => block%d:0x"VXGE_OS_STXFMT,
+	    from, (ptr_t) from_dma, to, (ptr_t) to_dma);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+}
+
+/*
+ * __hal_ring_mempool_item_alloc - Allocate List blocks for RxD block callback
+ * @mempoolh: Handle to memory pool
+ * @memblock: Address of this memory block
+ * @memblock_index: Index of this memory block
+ * @dma_object: dma object for this block
+ * @item: Pointer to this item
+ * @index: Index of this item in memory block
+ * @is_last: If this is last item in the block
+ * @userdata: Specific data of user
+ *
+ * This function is callback passed to __hal_mempool_create to create memory
+ * pool for RxD block
+ */
+static vxge_hal_status_e
+__hal_ring_mempool_item_alloc(
+    vxge_hal_mempool_h mempoolh,
+    void *memblock,
+    u32 memblock_index,
+    vxge_hal_mempool_dma_t *dma_object,
+    void *item,
+    u32 item_index,
+    u32 is_last,
+    void *userdata)
+{
+	u32 i;
+	__hal_ring_t *ring = (__hal_ring_t *) userdata;
+	__hal_device_t *hldev;
+
+	vxge_assert((item != NULL) && (ring != NULL));
+
+	hldev = (__hal_device_t *) ring->channel.devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool(
+	    "mempoolh = 0x"VXGE_OS_STXFMT", memblock = 0x"VXGE_OS_STXFMT", "
+	    "memblock_index = %d, dma_object = 0x"VXGE_OS_STXFMT", "
+	    "item = 0x"VXGE_OS_STXFMT", item_index = %d, is_last = %d, "
+	    "userdata = 0x"VXGE_OS_STXFMT, (ptr_t) mempoolh, (ptr_t) memblock,
+	    memblock_index, (ptr_t) dma_object, (ptr_t) item, item_index, is_last,
+	    (ptr_t) userdata);
+
+	/* format rxds array */
+	for (i = 0; i < ring->rxds_per_block; i++) {
+
+		void *uld_priv;
+		void *rxdblock_priv;
+		__hal_ring_rxd_priv_t *rxd_priv;
+		vxge_hal_ring_rxd_1_t *rxdp;
+		u32 memblock_item_idx;
+		u32 dtr_index = item_index * ring->rxds_per_block + i;
+
+		ring->channel.dtr_arr[dtr_index].dtr =
+		    ((u8 *) item) + i * ring->rxd_size;
+
+		/*
+		 * Note: memblock_item_idx is index of the item within
+		 * the memblock. For instance, in case of three RxD-blocks
+		 * per memblock this value can be 0, 1 or 2.
+		 */
+		rxdblock_priv = __hal_mempool_item_priv(
+		    (vxge_hal_mempool_t *) mempoolh,
+		    memblock_index,
+		    item,
+		    &memblock_item_idx);
+
+		rxdp = (vxge_hal_ring_rxd_1_t *)
+		    ring->channel.dtr_arr[dtr_index].dtr;
+
+		uld_priv = ((u8 *) rxdblock_priv + ring->rxd_priv_size * i);
+		rxd_priv =
+		    (__hal_ring_rxd_priv_t *) ((void *)(((char *) uld_priv) +
+		    ring->per_rxd_space));
+
+		((vxge_hal_ring_rxd_5_t *) rxdp)->host_control = dtr_index;
+
+		ring->channel.dtr_arr[dtr_index].uld_priv = (void *)uld_priv;
+		ring->channel.dtr_arr[dtr_index].hal_priv = (void *)rxd_priv;
+
+		/* pre-format per-RxD Ring's private */
+		/* LINTED */
+		rxd_priv->dma_offset = (u8 *) rxdp - (u8 *) memblock;
+		rxd_priv->dma_addr = dma_object->addr + rxd_priv->dma_offset;
+		rxd_priv->dma_handle = dma_object->handle;
+#if defined(VXGE_DEBUG_ASSERT)
+		rxd_priv->dma_object = dma_object;
+#endif
+		rxd_priv->db_bytes = ring->rxd_size;
+
+		if (i == (ring->rxds_per_block - 1)) {
+			rxd_priv->db_bytes +=
+			    (((vxge_hal_mempool_t *) mempoolh)->memblock_size -
+			    (ring->rxds_per_block * ring->rxd_size));
+		}
+	}
+
+	__hal_ring_block_memblock_idx_set((u8 *) item, memblock_index);
+	if (is_last) {
+		/* link last one with first one */
+		__hal_ring_rxdblock_link(mempoolh, ring, item_index, 0);
+	}
+
+	if (item_index > 0) {
+		/* link this RxD block with previous one */
+		__hal_ring_rxdblock_link(mempoolh, ring, item_index - 1, item_index);
+	}
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_ring_mempool_item_free - Free RxD blockt callback
+ * @mempoolh: Handle to memory pool
+ * @memblock: Address of this memory block
+ * @memblock_index: Index of this memory block
+ * @dma_object: dma object for this block
+ * @item: Pointer to this item
+ * @index: Index of this item in memory block
+ * @is_last: If this is last item in the block
+ * @userdata: Specific data of user
+ *
+ * This function is callback passed to __hal_mempool_free to destroy memory
+ * pool for RxD block
+ */
+static vxge_hal_status_e
+__hal_ring_mempool_item_free(
+    vxge_hal_mempool_h mempoolh,
+    void *memblock,
+    u32 memblock_index,
+    vxge_hal_mempool_dma_t *dma_object,
+    void *item,
+    u32 item_index,
+    u32 is_last,
+    void *userdata)
+{
+	__hal_ring_t *ring = (__hal_ring_t *) userdata;
+	__hal_device_t *hldev;
+
+	vxge_assert((item != NULL) && (ring != NULL));
+
+	hldev = (__hal_device_t *) ring->channel.devh;
+
+	vxge_hal_trace_log_pool("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_pool(
+	    "mempoolh = 0x"VXGE_OS_STXFMT", memblock = 0x"VXGE_OS_STXFMT", "
+	    "memblock_index = %d, dma_object = 0x"VXGE_OS_STXFMT", "
+	    "item = 0x"VXGE_OS_STXFMT", item_index = %d, is_last = %d, "
+	    "userdata = 0x"VXGE_OS_STXFMT, (ptr_t) mempoolh, (ptr_t) memblock,
+	    memblock_index, (ptr_t) dma_object, (ptr_t) item, item_index, is_last,
+	    (ptr_t) userdata);
+
+	vxge_hal_trace_log_pool("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_ring_initial_replenish - Initial replenish of RxDs
+ * @ring: ring
+ * @reopen: Flag to denote if it is open or repopen
+ *
+ * This function replenishes the RxDs from reserve array to work array
+ */
+static vxge_hal_status_e
+__hal_ring_initial_replenish(
+    __hal_ring_t *ring,
+    vxge_hal_reopen_e reopen)
+{
+	vxge_hal_rxd_h rxd;
+	void *uld_priv;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(ring != NULL);
+
+	hldev = (__hal_device_t *) ring->channel.devh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring("ring = 0x"VXGE_OS_STXFMT", reopen = %d",
+	    (ptr_t) ring, reopen);
+
+	while (vxge_hal_ring_rxd_reserve(ring->channel.vph, &rxd, &uld_priv) ==
+	    VXGE_HAL_OK) {
+
+		if (ring->rxd_init) {
+			status = ring->rxd_init(ring->channel.vph,
+			    rxd,
+			    uld_priv,
+			    VXGE_HAL_RING_RXD_INDEX(rxd),
+			    ring->channel.userdata,
+			    reopen);
+			if (status != VXGE_HAL_OK) {
+				vxge_hal_ring_rxd_free(ring->channel.vph, rxd);
+				vxge_hal_trace_log_ring("<== %s:%s:%d \
+				    Result: %d",
+				    __FILE__, __func__, __LINE__, status);
+				return (status);
+			}
+		}
+
+		vxge_hal_ring_rxd_post(ring->channel.vph, rxd);
+	}
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_ring_create - Create a Ring
+ * @vpath_handle: Handle returned by virtual path open
+ * @attr: Ring configuration parameters structure
+ *
+ * This function creates Ring and initializes it.
+ *
+ */
+vxge_hal_status_e
+__hal_ring_create(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_ring_attr_t *attr)
+{
+	vxge_hal_status_e status;
+	__hal_ring_t *ring;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	vxge_hal_ring_config_t *config;
+	__hal_device_t *hldev;
+
+	vxge_assert((vpath_handle != NULL) && (attr != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", attr = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) attr);
+
+	if ((vpath_handle == NULL) || (attr == NULL)) {
+		vxge_hal_err_log_ring("null pointer passed == > %s : %d",
+		    __func__, __LINE__);
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result:1",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_FAIL);
+	}
+
+	config =
+	    &vp->vpath->hldev->header.config.vp_config[vp->vpath->vp_id].ring;
+
+	config->ring_length = ((config->ring_length +
+	    vxge_hal_ring_rxds_per_block_get(config->buffer_mode) - 1) /
+	    vxge_hal_ring_rxds_per_block_get(config->buffer_mode)) *
+	    vxge_hal_ring_rxds_per_block_get(config->buffer_mode);
+
+	ring = (__hal_ring_t *) vxge_hal_channel_allocate(
+	    (vxge_hal_device_h) vp->vpath->hldev,
+	    vpath_handle,
+	    VXGE_HAL_CHANNEL_TYPE_RING,
+	    config->ring_length,
+	    attr->per_rxd_space,
+	    attr->userdata);
+
+	if (ring == NULL) {
+		vxge_hal_err_log_ring("Memory allocation failed == > %s : %d",
+		    __func__, __LINE__);
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	vp->vpath->ringh = (vxge_hal_ring_h) ring;
+
+	ring->stats = &vp->vpath->sw_stats->ring_stats;
+
+	ring->config = config;
+	ring->callback = attr->callback;
+	ring->rxd_init = attr->rxd_init;
+	ring->rxd_term = attr->rxd_term;
+
+	ring->indicate_max_pkts = config->indicate_max_pkts;
+	ring->buffer_mode = config->buffer_mode;
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock_init(&ring->channel.post_lock, hldev->pdev);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_init_irq(&ring->channel.post_lock, hldev->irqh);
+#endif
+
+	ring->rxd_size = vxge_hal_ring_rxd_size_get(config->buffer_mode);
+	ring->rxd_priv_size =
+	    sizeof(__hal_ring_rxd_priv_t) + attr->per_rxd_space;
+	ring->per_rxd_space = attr->per_rxd_space;
+
+	ring->rxd_priv_size =
+	    ((ring->rxd_priv_size + __vxge_os_cacheline_size - 1) /
+	    __vxge_os_cacheline_size) * __vxge_os_cacheline_size;
+
+	/*
+	 * how many RxDs can fit into one block. Depends on configured
+	 * buffer_mode.
+	 */
+	ring->rxds_per_block =
+	    vxge_hal_ring_rxds_per_block_get(config->buffer_mode);
+
+	/* calculate actual RxD block private size */
+	ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
+
+	ring->rxd_mem_avail =
+	    ((__hal_vpath_handle_t *) ring->channel.vph)->vpath->rxd_mem_size;
+
+	ring->db_byte_count = 0;
+
+	ring->mempool = vxge_hal_mempool_create(
+	    (vxge_hal_device_h) vp->vpath->hldev,
+	    VXGE_OS_HOST_PAGE_SIZE,
+	    VXGE_OS_HOST_PAGE_SIZE,
+	    ring->rxdblock_priv_size,
+	    ring->config->ring_length / ring->rxds_per_block,
+	    ring->config->ring_length / ring->rxds_per_block,
+	    __hal_ring_mempool_item_alloc,
+	    __hal_ring_mempool_item_free,
+	    ring);
+
+	if (ring->mempool == NULL) {
+		__hal_ring_delete(vpath_handle);
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	status = vxge_hal_channel_initialize(&ring->channel);
+	if (status != VXGE_HAL_OK) {
+		__hal_ring_delete(vpath_handle);
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+
+	/*
+	 * Note:
+	 * Specifying rxd_init callback means two things:
+	 * 1) rxds need to be initialized by ULD at channel-open time;
+	 * 2) rxds need to be posted at channel-open time
+	 *	(that's what the initial_replenish() below does)
+	 * Currently we don't have a case when the 1) is done without the 2).
+	 */
+	if (ring->rxd_init) {
+		if ((status = __hal_ring_initial_replenish(
+		    ring,
+		    VXGE_HAL_OPEN_NORMAL))
+		    != VXGE_HAL_OK) {
+			__hal_ring_delete(vpath_handle);
+			vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	/*
+	 * initial replenish will increment the counter in its post() routine,
+	 * we have to reset it
+	 */
+	ring->stats->common_stats.usage_cnt = 0;
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_ring_abort - Returns the RxD
+ * @ringh: Ring to be reset
+ * @reopen: See  vxge_hal_reopen_e {}.
+ *
+ * This function terminates the RxDs of ring
+ */
+void
+__hal_ring_abort(
+    vxge_hal_ring_h ringh,
+    vxge_hal_reopen_e reopen)
+{
+	u32 i = 0;
+	vxge_hal_rxd_h rxdh;
+
+	__hal_device_t *hldev;
+	__hal_ring_t *ring = (__hal_ring_t *) ringh;
+
+	vxge_assert(ringh != NULL);
+
+	hldev = (__hal_device_t *) ring->channel.devh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring("ring = 0x"VXGE_OS_STXFMT", reopen = %d",
+	    (ptr_t) ringh, reopen);
+
+	if (ring->rxd_term) {
+		__hal_channel_for_each_dtr(&ring->channel, rxdh, i) {
+			if (!__hal_channel_is_posted_dtr(&ring->channel, i)) {
+				ring->rxd_term(ring->channel.vph, rxdh,
+				    VXGE_HAL_RING_ULD_PRIV(ring, rxdh),
+				    VXGE_HAL_RXD_STATE_FREED,
+				    ring->channel.userdata,
+				    reopen);
+			}
+		}
+	}
+
+	for (;;) {
+		__hal_channel_dtr_try_complete(&ring->channel, &rxdh);
+		if (rxdh == NULL)
+			break;
+
+		__hal_channel_dtr_complete(&ring->channel);
+		if (ring->rxd_term) {
+			ring->rxd_term(ring->channel.vph, rxdh,
+			    VXGE_HAL_RING_ULD_PRIV(ring, rxdh),
+			    VXGE_HAL_RXD_STATE_POSTED,
+			    ring->channel.userdata,
+			    reopen);
+		}
+		__hal_channel_dtr_free(&ring->channel,
+		    VXGE_HAL_RING_RXD_INDEX(rxdh));
+	}
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_ring_reset - Resets the ring
+ * @ringh: Ring to be reset
+ *
+ * This function resets the ring during vpath reset operation
+ */
+vxge_hal_status_e
+__hal_ring_reset(
+    vxge_hal_ring_h ringh)
+{
+	__hal_ring_t *ring = (__hal_ring_t *) ringh;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+	__hal_vpath_handle_t *vph = (__hal_vpath_handle_t *) ring->channel.vph;
+
+	vxge_assert(ringh != NULL);
+
+	hldev = (__hal_device_t *) ring->channel.devh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring("ring = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) ringh);
+
+	__hal_ring_abort(ringh, VXGE_HAL_RESET_ONLY);
+
+	status = __hal_channel_reset(&ring->channel);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+
+	}
+	ring->rxd_mem_avail = vph->vpath->rxd_mem_size;
+	ring->db_byte_count = 0;
+
+
+	if (ring->rxd_init) {
+		if ((status = __hal_ring_initial_replenish(
+		    ring,
+		    VXGE_HAL_RESET_ONLY))
+		    != VXGE_HAL_OK) {
+			vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_ring_delete - Removes the ring
+ * @vpath_handle: Virtual path handle to which this queue belongs
+ *
+ * This function freeup the memory pool and removes the ring
+ */
+void
+__hal_ring_delete(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_ring_t *ring;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+	vxge_assert(ring->channel.pdev);
+
+	__hal_ring_abort(vp->vpath->ringh, VXGE_HAL_OPEN_NORMAL);
+
+
+	if (ring->mempool) {
+		vxge_hal_mempool_destroy(ring->mempool);
+	}
+
+	vxge_hal_channel_terminate(&ring->channel);
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock_destroy(&ring->channel.post_lock, hldev->pdev);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_destroy_irq(&ring->channel.post_lock, hldev->pdev);
+#endif
+
+	vxge_hal_channel_free(&ring->channel);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+}
+
+/*
+ * __hal_ring_frame_length_set	- Set the maximum frame length of recv frames.
+ * @vpath: virtual Path
+ * @new_frmlen: New frame length
+ *
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
+ *
+ */
+vxge_hal_status_e
+__hal_ring_frame_length_set(
+    __hal_virtualpath_t *vpath,
+    u32 new_frmlen)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = (__hal_device_t *) vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath = 0x"VXGE_OS_STXFMT", new_frmlen = %d",
+	    (ptr_t) vpath, new_frmlen);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    vpath->hldev->header.pdev,
+	    vpath->hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
+
+	if (vpath->vp_config->ring.max_frm_len !=
+	    VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU) {
+
+		val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
+		    vpath->vp_config->ring.max_frm_len +
+		    VXGE_HAL_MAC_HEADER_MAX_SIZE);
+
+	} else {
+
+		val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_frmlen +
+		    VXGE_HAL_MAC_HEADER_MAX_SIZE);
+	}
+
+	vxge_os_pio_mem_write64(
+	    vpath->hldev->header.pdev,
+	    vpath->hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_ring_rxd_reserve - Reserve ring descriptor.
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Reserved descriptor. On success HAL fills this "out" parameter
+ *		with a valid handle.
+ * @rxd_priv: Buffer to return pointer to per rxd private space
+ *
+ * Reserve Rx descriptor for the subsequent filling-in (by upper layer
+ * driver (ULD)) and posting on the corresponding channel (@channelh)
+ * via vxge_hal_ring_rxd_post().
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_ring_rxd_reserve(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h * rxdh,
+    void **rxd_priv)
+{
+	vxge_hal_status_e status;
+#if defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	unsigned long flags;
+#endif
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_ring_t *ring;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL) &&
+	    (rxd_priv != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT", "
+	    "rxd_priv = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
+	    (ptr_t) rxdh, (ptr_t) rxd_priv);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	status = __hal_channel_dtr_reserve(&ring->channel, rxdh);
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	if (status == VXGE_HAL_OK) {
+		vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *)*rxdh;
+
+		/* instead of memset: reset	this RxD */
+		rxdp->control_0 = rxdp->control_1 = 0;
+
+		*rxd_priv = VXGE_HAL_RING_ULD_PRIV(ring, rxdp);
+
+#if defined(VXGE_OS_MEMORY_CHECK)
+		VXGE_HAL_RING_HAL_PRIV(ring, rxdp)->allocated = 1;
+#endif
+	}
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (status);
+}
+
+/*
+ * vxge_hal_ring_rxd_pre_post - Prepare rxd and post
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * This routine prepares a rxd and posts
+ */
+void
+vxge_hal_ring_rxd_pre_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh)
+{
+
+#if defined(VXGE_DEBUG_ASSERT)
+	vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+
+#endif
+
+#if defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	unsigned long flags;
+
+#endif
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_ring_t *ring;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) rxdh);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+#if defined(VXGE_DEBUG_ASSERT)
+	/* make	sure device overwrites the (illegal) t_code on completion */
+	rxdp->control_0 |=
+	    VXGE_HAL_RING_RXD_T_CODE(VXGE_HAL_RING_RXD_T_CODE_UNUSED);
+#endif
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+#if defined(VXGE_DEBUG_ASSERT) && defined(VXGE_HAL_RING_ENFORCE_ORDER)
+	if (TRUE) {
+		if (VXGE_HAL_RING_RXD_INDEX(rxdp) != 0) {
+			vxge_hal_rxd_h prev_rxdh;
+			__hal_ring_rxd_priv_t *rxdp_priv;
+			u32 index;
+
+			rxdp_priv = VXGE_HAL_RING_HAL_PRIV(ring, rxdp);
+
+			if (VXGE_HAL_RING_RXD_INDEX(rxdp) == 0)
+				index = ring->channel.length;
+			else
+				index = VXGE_HAL_RING_RXD_INDEX(rxdp) - 1;
+
+			prev_rxdh = ring->channel.dtr_arr[index].dtr;
+
+			if (prev_rxdh != NULL &&
+			    (rxdp_priv->dma_offset & (~0xFFF)) !=
+			    rxdp_priv->dma_offset) {
+				vxge_assert((char *) prev_rxdh +
+				    ring->rxd_size == rxdh);
+			}
+		}
+	}
+#endif
+
+	__hal_channel_dtr_post(&ring->channel, VXGE_HAL_RING_RXD_INDEX(rxdh));
+
+	ring->db_byte_count +=
+	    VXGE_HAL_RING_HAL_PRIV(ring, rxdh)->db_bytes;
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_ring_rxd_post_post - Process rxd after post.
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Processes rxd after post
+ */
+void
+vxge_hal_ring_rxd_post_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh)
+{
+	vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+	__hal_ring_rxd_priv_t *priv;
+
+#endif
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_ring_t *ring;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) rxdh);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+	/* do POST */
+	rxdp->control_0 |= VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER;
+
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER;
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+	priv = __hal_ring_rxd_priv(ring, rxdp);
+	vxge_os_dma_sync(ring->channel.pdev,
+	    priv->dma_handle,
+	    priv->dma_addr,
+	    priv->dma_offset,
+	    ring->rxd_size,
+	    VXGE_OS_DMA_DIR_TODEVICE);
+#endif
+	if (ring->stats->common_stats.usage_cnt > 0)
+		ring->stats->common_stats.usage_cnt--;
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_ring_rxd_post - Post descriptor on the ring.
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor obtained via vxge_hal_ring_rxd_reserve().
+ *
+ * Post	descriptor on the ring.
+ * Prior to posting the	descriptor should be filled in accordance with
+ * Host/X3100 interface specification for a given service (LL, etc.).
+ *
+ */
+void
+vxge_hal_ring_rxd_post(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh)
+{
+	vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+
+#if defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	unsigned long flags;
+#endif
+
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_ring_t *ring;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) rxdh);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+	/* Based on Titan HW bugzilla # 3039, we need to reset the tcode */
+	rxdp->control_0 = 0;
+
+#if defined(VXGE_DEBUG_ASSERT)
+	/* make	sure device overwrites the (illegal) t_code on completion */
+	rxdp->control_0 |=
+	    VXGE_HAL_RING_RXD_T_CODE(VXGE_HAL_RING_RXD_T_CODE_UNUSED);
+#endif
+
+	rxdp->control_1 |= VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER;
+	rxdp->control_0 |= VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER;
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+	{
+		__hal_ring_rxd_priv_t *rxdp_temp1;
+		rxdp_temp1 = VXGE_HAL_RING_HAL_PRIV(ring, rxdp);
+		vxge_os_dma_sync(ring->channel.pdev,
+		    rxdp_temp1->dma_handle,
+		    rxdp_temp1->dma_addr,
+		    rxdp_temp1->dma_offset,
+		    ring->rxd_size,
+		    VXGE_OS_DMA_DIR_TODEVICE);
+	}
+#endif
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+#if defined(VXGE_DEBUG_ASSERT) && defined(VXGE_HAL_RING_ENFORCE_ORDER)
+	if (TRUE) {
+		if (VXGE_HAL_RING_RXD_INDEX(rxdp) != 0) {
+
+			vxge_hal_rxd_h prev_rxdh;
+			__hal_ring_rxd_priv_t *rxdp_temp2;
+
+			rxdp_temp2 = VXGE_HAL_RING_HAL_PRIV(ring, rxdp);
+			prev_rxdh =
+			    ring->channel.dtr_arr[VXGE_HAL_RING_RXD_INDEX(rxdp) - 1].dtr;
+
+			if (prev_rxdh != NULL &&
+			    (rxdp_temp2->dma_offset & (~0xFFF)) != rxdp_temp2->dma_offset)
+				vxge_assert((char *) prev_rxdh + ring->rxd_size == rxdh);
+		}
+	}
+#endif
+
+	__hal_channel_dtr_post(&ring->channel, VXGE_HAL_RING_RXD_INDEX(rxdh));
+
+	ring->db_byte_count +=
+	    VXGE_HAL_RING_HAL_PRIV(ring, rxdp)->db_bytes;
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	if (ring->stats->common_stats.usage_cnt > 0)
+		ring->stats->common_stats.usage_cnt--;
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_ring_rxd_post_post_wmb - Process rxd after post with memory barrier
+ * @vpath_handle: virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Processes rxd after post with memory barrier.
+ */
+void
+vxge_hal_ring_rxd_post_post_wmb(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) rxdh);
+
+	/* Do memory barrier before changing the ownership */
+	vxge_os_wmb();
+
+	vxge_hal_ring_rxd_post_post(vpath_handle, rxdh);
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_ring_rxd_post_post_db - Post Doorbell after posting the rxd(s).
+ * @vpath_handle: virtual Path handle.
+ *
+ * Post Doorbell after posting the rxd(s).
+ */
+void
+vxge_hal_ring_rxd_post_post_db(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	__hal_ring_t *ring;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	if (ring->db_byte_count <= ring->rxd_mem_avail) {
+		__hal_rxd_db_post(vpath_handle, ring->db_byte_count);
+		ring->rxd_mem_avail -= ring->db_byte_count;
+		ring->db_byte_count = 0;
+	} else {
+		__hal_rxd_db_post(vpath_handle, ring->rxd_mem_avail);
+		ring->db_byte_count -= ring->rxd_mem_avail;
+		ring->rxd_mem_avail = 0;
+	}
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_ring_is_next_rxd_completed - Check if the next rxd is completed
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Checks if the the _next_	completed descriptor is	in host	memory
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed	descriptors
+ * are currently available for processing.
+ */
+vxge_hal_status_e
+vxge_hal_ring_is_next_rxd_completed(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_ring_t *ring;
+	vxge_hal_rxd_h rxdh;
+	vxge_hal_ring_rxd_1_t *rxdp;	/* doesn't matter 1, 3 or 5... */
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	__hal_channel_dtr_try_complete(&ring->channel, &rxdh);
+
+	rxdp = (vxge_hal_ring_rxd_1_t *) rxdh;
+
+	if (rxdp != NULL) {
+
+		/* check whether it is not the end */
+		if ((!(rxdp->control_0 & VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER)) &&
+		    (!(rxdp->control_1 &
+		    VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER))) {
+
+			status = VXGE_HAL_OK;
+		}
+	}
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_ring_rxd_next_completed - Get the _next_ completed descriptor.
+ * @channelh: Channel handle.
+ * @rxdh: Descriptor handle. Returned by HAL.
+ * @rxd_priv: Buffer to return a pointer to the per rxd space allocated
+ * @t_code:	Transfer code, as per X3100 User Guide,
+ *			Receive	Descriptor Format. Returned	by HAL.
+ *
+ * Retrieve the	_next_ completed descriptor.
+ * HAL uses ring callback (*vxge_hal_ring_callback_f) to notifiy
+ * upper-layer driver (ULD) of new completed descriptors. After that
+ * the ULD can use vxge_hal_ring_rxd_next_completed to retrieve the rest
+ * completions (the very first completion is passed by HAL via
+ * vxge_hal_ring_callback_f).
+ *
+ * Implementation-wise,	the upper-layer	driver is free to call
+ * vxge_hal_ring_rxd_next_completed either immediately from inside the
+ * ring callback, or in a deferred fashion and separate (from HAL)
+ * context.
+ *
+ * Non-zero @t_code means failure to fill-in receive buffer(s)
+ * of the descriptor.
+ * For instance, parity	error detected during the data transfer.
+ * In this case	X3100 will	complete the descriptor	and	indicate
+ * for the host	that the received data is not to be	used.
+ * For details please refer	to X3100 User Guide.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed	descriptors
+ * are currently available for processing.
+ *
+ * See also: vxge_hal_ring_callback_f {},
+ * vxge_hal_fifo_rxd_next_completed(), vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+vxge_hal_ring_rxd_next_completed(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h *rxdh,
+    void **rxd_priv,
+    u8 *t_code)
+{
+	__hal_ring_t *ring;
+	vxge_hal_ring_rxd_5_t *rxdp;	/* doesn't matter 1, 3 or 5... */
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+	__hal_ring_rxd_priv_t *priv;
+#endif
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	u64 own, control_0, control_1;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL) &&
+	    (rxd_priv != NULL) && (t_code != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT", "
+	    "rxd_priv = 0x"VXGE_OS_STXFMT", t_code = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) rxdh, (ptr_t) rxd_priv,
+	    (ptr_t) t_code);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+	*rxdh = 0;
+	*rxd_priv = NULL;
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	__hal_channel_dtr_try_complete(&ring->channel, rxdh);
+
+	rxdp = (vxge_hal_ring_rxd_5_t *)*rxdh;
+	if (rxdp != NULL) {
+
+#if defined(VXGE_OS_DMA_REQUIRES_SYNC) && defined(VXGE_HAL_DMA_RXD_STREAMING)
+		/*
+		 * Note: 24 bytes at most means:
+		 *	- Control_3 in case of 5-buffer	mode
+		 *	- Control_1 and	Control_2
+		 *
+		 * This is the only length needs to be invalidated
+		 * type of channels.
+		 */
+		priv = __hal_ring_rxd_priv(ring, rxdp);
+		vxge_os_dma_sync(ring->channel.pdev,
+		    priv->dma_handle,
+		    priv->dma_addr,
+		    priv->dma_offset,
+		    24,
+		    VXGE_OS_DMA_DIR_FROMDEVICE);
+#endif
+		*t_code = (u8) VXGE_HAL_RING_RXD_T_CODE_GET(rxdp->control_0);
+
+		control_0 = rxdp->control_0;
+		control_1 = rxdp->control_1;
+		own = control_0 & VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER;
+
+		/* check whether it is not the end */
+		if ((!own && !(control_1 & VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER)) ||
+		    (*t_code == VXGE_HAL_RING_RXD_T_CODE_FRM_DROP)) {
+
+#ifndef	VXGE_HAL_IRQ_POLLING
+			if (++ring->cmpl_cnt > ring->indicate_max_pkts) {
+				/*
+				 * reset it. since we don't want to return
+				 * garbage to the ULD
+				 */
+				*rxdh = 0;
+				status = VXGE_HAL_COMPLETIONS_REMAIN;
+			} else {
+#endif
+				__hal_channel_dtr_complete(&ring->channel);
+
+				*rxd_priv = VXGE_HAL_RING_ULD_PRIV(ring, rxdp);
+
+				ring->rxd_mem_avail +=
+				    (VXGE_HAL_RING_HAL_PRIV(ring, rxdp))->db_bytes;
+
+				ring->stats->common_stats.usage_cnt++;
+				if (ring->stats->common_stats.usage_max <
+				    ring->stats->common_stats.usage_cnt)
+					ring->stats->common_stats.usage_max =
+					    ring->stats->common_stats.usage_cnt;
+
+				switch (ring->buffer_mode) {
+				case VXGE_HAL_RING_RXD_BUFFER_MODE_1:
+					ring->channel.poll_bytes +=
+					    (u32) VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(
+					    rxdp->control_1);
+					break;
+				case VXGE_HAL_RING_RXD_BUFFER_MODE_3:
+					ring->channel.poll_bytes +=
+					    (u32) VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(
+					    rxdp->control_1) +
+					    (u32) VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(
+					    rxdp->control_1) +
+					    (u32) VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(
+					    rxdp->control_1);
+					break;
+				case VXGE_HAL_RING_RXD_BUFFER_MODE_5:
+					ring->channel.poll_bytes +=
+					    (u32) VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(
+					    rxdp->control_1) +
+					    (u32) VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(
+					    rxdp->control_1) +
+					    (u32) VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(
+					    rxdp->control_1) +
+					    (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(
+					    rxdp->control_2) +
+					    (u32) VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_GET(
+					    rxdp->control_2);
+					break;
+				}
+
+				status = VXGE_HAL_OK;
+#ifndef	VXGE_HAL_IRQ_POLLING
+			}
+#endif
+		}
+	}
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+
+/*
+ * vxge_hal_ring_handle_tcode - Handle transfer code.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ * @t_code: One of the enumerated (and documented in the X3100 user guide)
+ *	 "transfer codes".
+ *
+ * Handle descriptor's transfer code. The latter comes with each completed
+ * descriptor.
+ *
+ * Returns: one of the vxge_hal_status_e {} enumerated types.
+ * VXGE_HAL_OK			- for success.
+ * VXGE_HAL_ERR_CRITICAL	- when encounters critical error.
+ */
+vxge_hal_status_e
+vxge_hal_ring_handle_tcode(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh,
+    u8 t_code)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "rxdh = 0x"VXGE_OS_STXFMT", t_code = 0x%d",
+	    (ptr_t) vpath_handle, (ptr_t) rxdh, t_code);
+
+	switch (t_code) {
+	case 0x0:
+		/* 0x0: Transfer ok. */
+		break;
+	case 0x1:
+		/*
+		 * 0x1: Layer 3 checksum presentation
+		 *	configuration mismatch.
+		 */
+		break;
+	case 0x2:
+		/*
+		 * 0x2: Layer 4 checksum presentation
+		 *	configuration mismatch.
+		 */
+		break;
+	case 0x3:
+		/*
+		 * 0x3: Layer 3 and Layer 4 checksum
+		 *	presentation configuration mismatch.
+		 */
+		break;
+	case 0x4:
+		/* 0x4: Reserved. */
+		break;
+	case 0x5:
+		/*
+		 * 0x5: Layer 3 error unparseable packet,
+		 *	such as unknown IPv6 header.
+		 */
+		break;
+	case 0x6:
+		/*
+		 * 0x6: Layer 2 error frame integrity
+		 *	error, such as FCS or ECC).
+		 */
+		break;
+	case 0x7:
+		/*
+		 * 0x7: Buffer size error the RxD buffer(s)
+		 *	were not appropriately sized and
+		 *	data loss occurred.
+		 */
+		break;
+	case 0x8:
+		/* 0x8: Internal ECC error RxD corrupted. */
+		__hal_device_handle_error(vp->vpath->hldev,
+		    vp->vpath->vp_id, VXGE_HAL_EVENT_ECCERR);
+		break;
+	case 0x9:
+		/*
+		 * 0x9: Benign overflow the contents of
+		 *	Segment1 exceeded the capacity of
+		 *	Buffer1 and the remainder was placed
+		 *	in Buffer2. Segment2 now starts in
+		 *	Buffer3. No data loss or errors occurred.
+		 */
+		break;
+	case 0xA:
+		/*
+		 * 0xA: Buffer size 0 one of the RxDs
+		 *	assigned buffers has a size of 0 bytes.
+		 */
+		break;
+	case 0xB:
+		/* 0xB: Reserved. */
+		break;
+	case 0xC:
+		/*
+		 * 0xC: Frame dropped either due to
+		 *	VPath Reset or because of a VPIN mismatch.
+		 */
+		break;
+	case 0xD:
+		/* 0xD: Reserved. */
+		break;
+	case 0xE:
+		/* 0xE: Reserved. */
+		break;
+	case 0xF:
+		/*
+		 * 0xF: Multiple errors more than one
+		 *	transfer code condition occurred.
+		 */
+		break;
+	default:
+		vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_TCODE);
+		return (VXGE_HAL_ERR_INVALID_TCODE);
+	}
+
+	vp->vpath->sw_stats->ring_stats.rxd_t_code_err_cnt[t_code]++;
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, VXGE_HAL_OK);
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * vxge_hal_ring_rxd_private_get - Get ULD private per-descriptor data.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Returns: private ULD	info associated	with the descriptor.
+ * ULD requests	per-descriptor space via vxge_hal_ring_attr.
+ *
+ */
+void *
+vxge_hal_ring_rxd_private_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	return (VXGE_HAL_RING_ULD_PRIV(
+	    ((__hal_ring_t *) vp->vpath->ringh), rxdh));
+
+}
+
+/*
+ * vxge_hal_ring_rxd_free - Free descriptor.
+ * @vpath_handle: Virtual Path handle.
+ * @rxdh: Descriptor handle.
+ *
+ * Free	the reserved descriptor. This operation is "symmetrical" to
+ * vxge_hal_ring_rxd_reserve. The "free-ing" completes the descriptor's
+ * lifecycle.
+ *
+ * After free-ing (see vxge_hal_ring_rxd_free()) the descriptor again can
+ * be:
+ *
+ * - reserved (vxge_hal_ring_rxd_reserve);
+ *
+ * - posted	(vxge_hal_ring_rxd_post);
+ *
+ * - completed (vxge_hal_ring_rxd_next_completed);
+ *
+ * - and recycled again	(vxge_hal_ring_rxd_free).
+ *
+ * For alternative state transitions and more details please refer to
+ * the design doc.
+ *
+ */
+void
+vxge_hal_ring_rxd_free(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rxd_h rxdh)
+{
+#if defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	unsigned long flags;
+
+#endif
+	__hal_ring_t *ring;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (rxdh != NULL));
+
+	hldev = (__hal_device_t *) vp->vpath->hldev;
+
+	vxge_hal_trace_log_ring("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_ring(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", rxdh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) rxdh);
+
+	ring = (__hal_ring_t *) vp->vpath->ringh;
+
+	vxge_assert(ring != NULL);
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_lock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_lock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	__hal_channel_dtr_free(&ring->channel, VXGE_HAL_RING_RXD_INDEX(rxdh));
+#if defined(VXGE_OS_MEMORY_CHECK)
+	VXGE_HAL_RING_HAL_PRIV(ring, rxdh)->allocated = 0;
+#endif
+
+#if defined(VXGE_HAL_RX_MULTI_POST)
+	vxge_os_spin_unlock(&ring->channel.post_lock);
+#elif defined(VXGE_HAL_RX_MULTI_POST_IRQ)
+	vxge_os_spin_unlock_irq(&ring->channel.post_lock, flags);
+#endif
+
+	vxge_hal_trace_log_ring("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-ring.h b/sys/dev/vxge/vxgehal/vxgehal-ring.h
new file mode 100644
index 000000000000..223116728b27
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-ring.h
@@ -0,0 +1,201 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_RING_H
+#define	VXGE_HAL_RING_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef u8 vxge_hal_ring_block_t[VXGE_OS_HOST_PAGE_SIZE];
+
+#define	VXGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_OS_HOST_PAGE_SIZE-8)
+#define	VXGE_HAL_RING_MEMBLOCK_IDX_OFFSET	(VXGE_OS_HOST_PAGE_SIZE-16)
+
+/*
+ * struct __hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
+ * @dma_addr: DMA (mapped) address of _this_ descriptor.
+ * @dma_handle: DMA handle used to map the descriptor onto device.
+ * @dma_offset: Descriptor's offset in the memory block. HAL allocates
+ *		descriptors in memory blocks of %VXGE_OS_HOST_PAGE_SIZE
+ *		bytes. Each memblock is contiguous DMA-able memory. Each
+ *		memblock contains 1 or more 4KB RxD blocks visible to the
+ *		X3100 hardware.
+ * @dma_object: DMA address and handle of the memory block that contains
+ *		the descriptor. This member is used only in the "checked"
+ *		version of the HAL (to enforce certain assertions);
+ *		otherwise it gets compiled out.
+ * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
+ * @db_bytes: Number of doorbell bytes to be posted for this Rxd. This includes
+ *		next RxD block pointers
+ *
+ * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
+ * information associated with the descriptor. Note that ULD can ask HAL
+ * to allocate additional per-descriptor space for its own (ULD-specific)
+ * purposes.
+ */
+typedef struct __hal_ring_rxd_priv_t {
+	dma_addr_t		dma_addr;
+	pci_dma_h		dma_handle;
+	ptrdiff_t		dma_offset;
+#if defined(VXGE_DEBUG_ASSERT)
+	vxge_hal_mempool_dma_t	*dma_object;
+#endif
+#if defined(VXGE_OS_MEMORY_CHECK)
+	u32			allocated;
+#endif
+	u32			db_bytes;
+} __hal_ring_rxd_priv_t;
+
+
+/*
+ * struct __hal_ring_t - Ring channel.
+ * @channel: Channel "base" of this ring, the common part of all HAL
+ *	channels.
+ * @mempool: Memory pool, the pool from which descriptors get allocated.
+ *	(See vxge_hal_mm.h).
+ * @config: Ring configuration, part of device configuration
+ *	(see vxge_hal_device_config_t {}).
+ * @ring_length: Length of the ring
+ * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
+ *	as per X3100 User Guide.
+ * @indicate_max_pkts: Maximum number of packets processed within a single
+ *	interrupt. Can be used to limit the time spent inside hw interrupt.
+ * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per X3100 spec,
+ *	1-buffer mode descriptor is 32 byte long, etc.
+ * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
+ *		data (e.g., DMA handle for Solaris)
+ * @per_rxd_space: Per rxd space requested by ULD
+ * @rxds_per_block: Number of descriptors per hardware-defined RxD
+ *		block. Depends on the (1-, 3-, 5-) buffer mode.
+ * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
+ *			usage. Not to confuse with @rxd_priv_size.
+ * @rxd_mem_avail: Available RxD memory
+ * @db_byte_count: Number of doorbell bytes to be posted
+ * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
+ *	Used in conjunction with @indicate_max_pkts.
+ * @active_sw_lros: List of Software LRO sessions in progess
+ * @active_sw_lro_count: Number of Software LRO sessions in progess
+ * @free_sw_lros: List of Software LRO sessions free
+ * @free_sw_lro_count: Number of Software LRO sessions free
+ * @sw_lro_lock: LRO session lists' lock
+ * @callback: Channel completion callback. HAL invokes the callback when there
+ *	    are new completions on that channel. In many implementations
+ *	    the @callback executes in the hw interrupt context.
+ * @rxd_init: Channel's descriptor-initialize callback.
+ *	    See vxge_hal_ring_rxd_init_f {}.
+ *	    If not NULL, HAL invokes the callback when opening the ring.
+ * @rxd_term: Channel's descriptor-terminate callback. If not NULL,
+ *	HAL invokes the callback when closing the corresponding channel.
+ *	See also vxge_hal_channel_rxd_term_f {}.
+ * @stats: Statistics for ring
+ * Ring channel.
+ *
+ * Note: The structure is cache line aligned to better utilize
+ *	   CPU cache performance.
+ */
+typedef struct __hal_ring_t {
+	__hal_channel_t				channel;
+	vxge_hal_mempool_t			*mempool;
+	vxge_hal_ring_config_t			*config;
+	u32					ring_length;
+	u32					buffer_mode;
+	u32					indicate_max_pkts;
+	u32					rxd_size;
+	u32					rxd_priv_size;
+	u32					per_rxd_space;
+	u32					rxds_per_block;
+	u32					rxdblock_priv_size;
+	u32					rxd_mem_avail;
+	u32					db_byte_count;
+	u32					cmpl_cnt;
+	vxge_hal_ring_callback_f		callback;
+	vxge_hal_ring_rxd_init_f		rxd_init;
+	vxge_hal_ring_rxd_term_f		rxd_term;
+	vxge_hal_vpath_stats_sw_ring_info_t *stats;
+} __vxge_os_attr_cacheline_aligned __hal_ring_t;
+
+#define	VXGE_HAL_RING_ULD_PRIV(ring, rxdh)				\
+	ring->channel.dtr_arr[						\
+	    ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].uld_priv
+
+#define	VXGE_HAL_RING_HAL_PRIV(ring, rxdh)				\
+	((__hal_ring_rxd_priv_t *)(ring->channel.dtr_arr[		\
+	    ((vxge_hal_ring_rxd_5_t *)(rxdh))->host_control].hal_priv))
+
+#define	VXGE_HAL_RING_POST_DOORBELL(vph, ringh)				\
+{									\
+	if (((__hal_ring_t *)(ringh))->config->post_mode ==		\
+	    VXGE_HAL_RING_POST_MODE_DOORBELL) {				\
+		vxge_hal_ring_rxd_post_post_db(vph);			\
+	}								\
+}
+
+#define	VXGE_HAL_RING_RXD_INDEX(rxdp)	\
+	(u32)((vxge_hal_ring_rxd_5_t *)rxdp)->host_control
+
+/* ========================== RING PRIVATE API ============================ */
+
+u64
+__hal_ring_first_block_address_get(
+    vxge_hal_ring_h ringh);
+
+vxge_hal_status_e
+__hal_ring_create(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_ring_attr_t *attr);
+
+void
+__hal_ring_abort(
+    vxge_hal_ring_h ringh,
+    vxge_hal_reopen_e reopen);
+
+vxge_hal_status_e
+__hal_ring_reset(
+    vxge_hal_ring_h ringh);
+
+void
+__hal_ring_delete(
+    vxge_hal_vpath_h vpath_handle);
+
+vxge_hal_status_e
+vxge_hal_ring_initial_replenish(
+    __hal_ring_t *ring,
+    vxge_hal_reopen_e reopen);
+
+vxge_hal_status_e
+__hal_ring_frame_length_set(
+    __hal_virtualpath_t *vpath,
+    u32 new_frmlen);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_RING_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-srpcim-reg.h b/sys/dev/vxge/vxgehal/vxgehal-srpcim-reg.h
new file mode 100644
index 000000000000..18414e26c555
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-srpcim-reg.h
@@ -0,0 +1,236 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_SRPCIM_REGS_H
+#define	VXGE_HAL_SRPCIM_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_srpcim_reg_t {
+
+/* 0x00000 */	u64	tim_mr2sr_resource_assignment_vh;
+#define	VXGE_HAL_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val)\
+							    vBIT(val, 0, 32)
+	u8	unused00100[0x00100 - 0x00008];
+
+/* 0x00100 */	u64	srpcim_pcipif_int_status;
+#define	VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_INT mBIT(3)
+#define	VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT mBIT(7)
+#define	VXGE_HAL_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT\
+							    mBIT(11)
+/* 0x00108 */	u64	srpcim_pcipif_int_mask;
+/* 0x00110 */	u64	mrpcim_msg_reg;
+#define	VXGE_HAL_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT	mBIT(3)
+/* 0x00118 */	u64	mrpcim_msg_mask;
+/* 0x00120 */	u64	mrpcim_msg_alarm;
+/* 0x00128 */	u64	vpath_msg_reg;
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT	mBIT(0)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT	mBIT(1)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT	mBIT(2)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT	mBIT(3)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT	mBIT(4)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT	mBIT(5)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT	mBIT(6)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT	mBIT(7)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT	mBIT(8)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT	mBIT(9)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT	mBIT(10)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT	mBIT(11)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT	mBIT(12)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT	mBIT(13)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT	mBIT(14)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT	mBIT(15)
+#define	VXGE_HAL_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT	mBIT(16)
+/* 0x00130 */	u64	vpath_msg_mask;
+/* 0x00138 */	u64	vpath_msg_alarm;
+	u8	unused00158[0x00158 - 0x00140];
+
+/* 0x00158 */	u64	vf_bargrp_no;
+#define	VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR0(val)  vBIT(val, 11, 5)
+#define	VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR1(val)  vBIT(val, 19, 5)
+#define	VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR2(val)  vBIT(val, 26, 6)
+#define	VXGE_HAL_VF_BARGRP_NO_FIRST_VF_OFFSET(val)	    vBIT(val, 32, 4)
+#define	VXGE_HAL_VF_BARGRP_NO_MASK(val)			    vBIT(val, 36, 4)
+/* 0x00160 */	u64	srpcim_to_mrpcim_wmsg;
+#define	VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val)\
+							    vBIT(val, 0, 64)
+/* 0x00168 */	u64	srpcim_to_mrpcim_wmsg_trig;
+#define	VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG mBIT(0)
+/* 0x00170 */	u64	mrpcim_to_srpcim_rmsg;
+#define	VXGE_HAL_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val)\
+							    vBIT(val, 0, 64)
+/* 0x00178 */	u64	vpath_to_srpcim_rmsg_sel;
+#define	VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SEL_SEL(val)	    vBIT(val, 0, 5)
+/* 0x00180 */	u64	vpath_to_srpcim_rmsg;
+#define	VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val)\
+							    vBIT(val, 0, 64)
+	u8	unused00200[0x00200 - 0x00188];
+
+/* 0x00200 */	u64	srpcim_general_int_status;
+#define	VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT	    mBIT(0)
+#define	VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PCI_INT	    mBIT(3)
+#define	VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT	    mBIT(7)
+	u8	unused00210[0x00210 - 0x00208];
+
+/* 0x00210 */	u64	srpcim_general_int_mask;
+#define	VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PIC_INT	    mBIT(0)
+#define	VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT	    mBIT(3)
+#define	VXGE_HAL_SRPCIM_GENERAL_INT_MASK_XMAC_INT	    mBIT(7)
+	u8	unused00220[0x00220 - 0x00218];
+
+/* 0x00220 */	u64	srpcim_ppif_int_status;
+#define	VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT\
+							    mBIT(3)
+#define	VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM mBIT(7)
+#define	VXGE_HAL_SRPCIM_PPIF_INT_STATUS_VPATH_TO_SRPCIM_ALARM_INT mBIT(11)
+/* 0x00228 */	u64	srpcim_ppif_int_mask;
+/* 0x00230 */	u64	srpcim_gen_errors_reg;
+#define	VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR	mBIT(3)
+#define	VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR	mBIT(7)
+#define	VXGE_HAL_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR	mBIT(11)
+#define	VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT	mBIT(15)
+#define	VXGE_HAL_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET	    mBIT(19)
+#define	VXGE_HAL_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS	mBIT(23)
+/* 0x00238 */	u64	srpcim_gen_errors_mask;
+/* 0x00240 */	u64	srpcim_gen_errors_alarm;
+/* 0x00248 */	u64	mrpcim_to_srpcim_alarm_reg;
+#define	VXGE_HAL_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM	mBIT(3)
+/* 0x00250 */	u64	mrpcim_to_srpcim_alarm_mask;
+/* 0x00258 */	u64	mrpcim_to_srpcim_alarm_alarm;
+/* 0x00260 */	u64	vpath_to_srpcim_alarm_reg;
+#define	VXGE_HAL_VPATH_TO_SRPCIM_ALARM_REG_PPIF_VPATH_TO_SRPCIM_ALARM(val)\
+							    vBIT(val, 0, 17)
+/* 0x00268 */	u64	vpath_to_srpcim_alarm_mask;
+/* 0x00270 */	u64	vpath_to_srpcim_alarm_alarm;
+	u8	unused00280[0x00280 - 0x00278];
+
+/* 0x00280 */	u64	pf_sw_reset;
+#define	VXGE_HAL_PF_SW_RESET_PF_SW_RESET(val)		    vBIT(val, 0, 8)
+/* 0x00288 */	u64	srpcim_general_cfg1;
+#define	VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN	    mBIT(19)
+#define	VXGE_HAL_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN	    mBIT(23)
+#define	VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN	    mBIT(27)
+#define	VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN	    mBIT(31)
+#define	VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN	    mBIT(35)
+#define	VXGE_HAL_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN	    mBIT(39)
+/* 0x00290 */	u64	srpcim_interrupt_cfg1;
+#define	VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vBIT(val, 1, 7)
+#define	VXGE_HAL_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val)   vBIT(val, 9, 3)
+/* 0x00298 */	u64	srpcim_interrupt_cfg2;
+#define	VXGE_HAL_SRPCIM_INTERRUPT_CFG2_MSIX_FOR_SCHED_INT(val)\
+							    vBIT(val, 1, 7)
+#define	VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_ONE_SHOT	    mBIT(11)
+#define	VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_TIMER_EN	    mBIT(15)
+#define	VXGE_HAL_SRPCIM_INTERRUPT_CFG2_SCHED_INT_PERIOD(val) vBIT(val, 32, 32)
+	u8	unused002a8[0x002a8 - 0x002a0];
+
+/* 0x002a8 */	u64	srpcim_clear_msix_mask;
+#define	VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK mBIT(0)
+/* 0x002b0 */	u64	srpcim_set_msix_mask;
+#define	VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK  mBIT(0)
+/* 0x002b8 */	u64	srpcim_clr_msix_one_shot;
+#define	VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT mBIT(0)
+/* 0x002c0 */	u64	srpcim_rst_in_prog;
+#define	VXGE_HAL_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG	    mBIT(7)
+/* 0x002c8 */	u64	srpcim_reg_modified;
+#define	VXGE_HAL_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED    mBIT(7)
+/* 0x002d0 */	u64	tgt_pf_illegal_access;
+#define	VXGE_HAL_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val)	    vBIT(val, 1, 7)
+/* 0x002d8 */	u64	srpcim_msix_status;
+#define	VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK mBIT(3)
+#define	VXGE_HAL_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR mBIT(7)
+	u8	unused00318[0x00318 - 0x002e0];
+
+/* 0x00318 */	u64	usdc_vpl;
+#define	VXGE_HAL_USDC_VPL_SGRP_OWN(val)			    vBIT(val, 0, 32)
+	u8	unused00600[0x00600 - 0x00320];
+
+/* 0x00600 */	u64	one_cfg_sr_copy;
+#define	VXGE_HAL_ONE_CFG_SR_COPY_ONE_CFG_RDY		    mBIT(7)
+/* 0x00608 */	u64	sgrp_allocated;
+#define	VXGE_HAL_SGRP_ALLOCATED_SGRP_ALLOC(val)		    vBIT(val, 0, 64)
+/* 0x00610 */	u64	sgrp_iwarp_lro_allocated;
+#define	VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_ENABLE_IWARP	    mBIT(7)
+#define	VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_LAST_IWARP_SGRP(val) vBIT(val, 11, 5)
+	u8	unused00880[0x00880 - 0x00618];
+
+/* 0x00880 */	u64	xgmac_sr_int_status;
+#define	VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT   mBIT(3)
+/* 0x00888 */	u64	xgmac_sr_int_mask;
+/* 0x00890 */	u64	asic_ntwk_sr_err_reg;
+#define	VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT mBIT(3)
+#define	VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK mBIT(7)
+#define	VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED\
+							    mBIT(11)
+#define	VXGE_HAL_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED mBIT(15)
+/* 0x00898 */	u64	asic_ntwk_sr_err_mask;
+/* 0x008a0 */	u64	asic_ntwk_sr_err_alarm;
+	u8	unused008c0[0x008c0 - 0x008a8];
+
+/* 0x008c0 */	u64	xmac_vsport_choices_sr_clone;
+#define	VXGE_HAL_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val)\
+							    vBIT(val, 0, 17)
+	u8	unused00900[0x00900 - 0x008c8];
+
+/* 0x00900 */	u64	mr_rqa_top_prty_for_vh;
+#define	VXGE_HAL_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val)\
+							    vBIT(val, 59, 5)
+/* 0x00908 */	u64	umq_vh_data_list_empty;
+#define	VXGE_HAL_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY mBIT(0)
+/* 0x00910 */	u64	wde_cfg;
+#define	VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_START		    mBIT(0)
+#define	VXGE_HAL_WDE_CFG_NS0_FORCE_MWB_END		    mBIT(1)
+#define	VXGE_HAL_WDE_CFG_NS0_FORCE_QB_START		    mBIT(2)
+#define	VXGE_HAL_WDE_CFG_NS0_FORCE_QB_END		    mBIT(3)
+#define	VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_START		    mBIT(4)
+#define	VXGE_HAL_WDE_CFG_NS0_FORCE_MPSB_END		    mBIT(5)
+#define	VXGE_HAL_WDE_CFG_NS0_MWB_OPT_EN			    mBIT(6)
+#define	VXGE_HAL_WDE_CFG_NS0_QB_OPT_EN			    mBIT(7)
+#define	VXGE_HAL_WDE_CFG_NS0_MPSB_OPT_EN		    mBIT(8)
+#define	VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_START		    mBIT(9)
+#define	VXGE_HAL_WDE_CFG_NS1_FORCE_MWB_END		    mBIT(10)
+#define	VXGE_HAL_WDE_CFG_NS1_FORCE_QB_START		    mBIT(11)
+#define	VXGE_HAL_WDE_CFG_NS1_FORCE_QB_END		    mBIT(12)
+#define	VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_START		    mBIT(13)
+#define	VXGE_HAL_WDE_CFG_NS1_FORCE_MPSB_END		    mBIT(14)
+#define	VXGE_HAL_WDE_CFG_NS1_MWB_OPT_EN			    mBIT(15)
+#define	VXGE_HAL_WDE_CFG_NS1_QB_OPT_EN			    mBIT(16)
+#define	VXGE_HAL_WDE_CFG_NS1_MPSB_OPT_EN		    mBIT(17)
+#define	VXGE_HAL_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR    mBIT(19)
+#define	VXGE_HAL_WDE_CFG_ALIGNMENT_PREFERENCE(val)	    vBIT(val, 30, 2)
+#define	VXGE_HAL_WDE_CFG_MEM_WORD_SIZE(val)		    vBIT(val, 46, 2)
+
+} vxge_hal_srpcim_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_SRPCIM_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-srpcim.c b/sys/dev/vxge/vxgehal/vxgehal-srpcim.c
new file mode 100644
index 000000000000..64c5288d46d5
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-srpcim.c
@@ -0,0 +1,787 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * __hal_srpcim_alarm_process - Process Alarms.
+ * @hldev: HAL Device
+ * @srpcim_id: srpcim index
+ * @skip_alarms: Flag to indicate if not to clear the alarms
+ *
+ * Process srpcim alarms.
+ *
+ */
+vxge_hal_status_e
+__hal_srpcim_alarm_process(
+    __hal_device_t * hldev,
+    u32 srpcim_id,
+    u32 skip_alarms)
+{
+	u64 val64;
+	u64 alarm_status;
+	u64 pic_status;
+	u64 xgmac_status;
+	vxge_hal_srpcim_reg_t *srpcim_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim_irq("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	srpcim_reg = hldev->srpcim_reg[srpcim_id];
+
+	alarm_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &srpcim_reg->srpcim_general_int_status);
+
+	vxge_hal_info_log_srpcim_irq("alarm_status = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) alarm_status);
+
+	if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT) {
+
+		xgmac_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &srpcim_reg->xgmac_sr_int_status);
+
+		vxge_hal_info_log_srpcim_irq("xgmac_status = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) xgmac_status);
+
+		if (xgmac_status &
+		    VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &srpcim_reg->asic_ntwk_sr_err_reg);
+
+			vxge_hal_info_log_srpcim_irq("asic_ntwk_sr_err_reg = \
+			    0x"VXGE_OS_STXFMT, (ptr_t) val64);
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &srpcim_reg->asic_ntwk_sr_err_reg);
+
+		}
+	}
+
+	if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT) {
+
+		pic_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &srpcim_reg->srpcim_ppif_int_status);
+
+		vxge_hal_info_log_srpcim_irq("pic_status = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) pic_status);
+
+		if (pic_status &
+		    VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &srpcim_reg->srpcim_gen_errors_reg);
+
+			vxge_hal_info_log_srpcim_irq("srpcim_gen_errors_reg = \
+			    0x"VXGE_OS_STXFMT, (ptr_t) val64);
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &srpcim_reg->srpcim_gen_errors_reg);
+		}
+
+		if (pic_status &
+		    VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &srpcim_reg->mrpcim_to_srpcim_alarm_reg);
+
+			vxge_hal_info_log_srpcim_irq("mrpcim_to_srpcim_alarm_reg = \
+			    0x"VXGE_OS_STXFMT, (ptr_t) val64);
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &srpcim_reg->mrpcim_to_srpcim_alarm_reg);
+
+		}
+	}
+
+	if (alarm_status & ~(
+	    VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT |
+	    VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT)) {
+		vxge_hal_trace_log_srpcim_irq("%s:%s:%d Unknown Alarm",
+		    __FILE__, __func__, __LINE__);
+	}
+
+	vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_srpcim_alarm_process - Process srpcim Alarms.
+ * @devh: Device Handle.
+ * @skip_alarms: Flag to indicate if not to clear the alarms
+ *
+ * Process srpcim alarms.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_alarm_process(
+    vxge_hal_device_h devh,
+    u32 skip_alarms)
+{
+	u32 i;
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim_irq("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg);
+
+		vxge_hal_trace_log_srpcim_irq("srpcim_to_mrpcim_alarm_reg = \
+		    0x"VXGE_OS_STXFMT, (ptr_t) val64);
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			if (val64 & mBIT(i)) {
+				status = __hal_srpcim_alarm_process(hldev,
+				    i, skip_alarms);
+			}
+		}
+
+		if (!skip_alarms)
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    VXGE_HAL_INTR_MASK_ALL,
+			    &hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg);
+	} else {
+		status = __hal_srpcim_alarm_process(hldev,
+		    hldev->srpcim_id, skip_alarms);
+	}
+
+	vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_srpcim_intr_enable - Enable srpcim interrupts.
+ * @hldev: Hal Device.
+ * @srpcim_id: SRPCIM Id
+ *
+ * Enable srpcim interrupts.
+ *
+ * See also: __hal_srpcim_intr_disable()
+ */
+vxge_hal_status_e
+__hal_srpcim_intr_enable(
+    __hal_device_t * hldev,
+    u32 srpcim_id)
+{
+	vxge_hal_srpcim_reg_t *srpcim_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	srpcim_reg = hldev->srpcim_reg[srpcim_id];
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->srpcim_gen_errors_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->mrpcim_to_srpcim_alarm_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->vpath_to_srpcim_alarm_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->srpcim_ppif_int_status);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->mrpcim_msg_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->vpath_msg_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->srpcim_pcipif_int_status);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->asic_ntwk_sr_err_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->xgmac_sr_int_status);
+
+	vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &srpcim_reg->srpcim_general_int_status);
+
+	/* Unmask the individual interrupts. */
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &srpcim_reg->vpath_msg_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &srpcim_reg->srpcim_pcipif_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(~VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT, 0),
+	    &srpcim_reg->srpcim_general_int_mask);
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_srpcim_intr_enable - Enable srpcim interrupts.
+ * @devh: Hal Device.
+ *
+ * Enable srpcim interrupts.
+ *
+ * See also: vxge_hal_srpcim_intr_disable()
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_intr_enable(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			status = __hal_srpcim_intr_enable(hldev, i);
+
+		}
+
+	} else {
+		status = __hal_srpcim_intr_enable(hldev, hldev->srpcim_id);
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_srpcim_intr_disable - Disable srpcim interrupts.
+ * @hldev: Hal Device.
+ * @srpcim_id: SRPCIM Id
+ *
+ * Disable srpcim interrupts.
+ *
+ * See also: __hal_srpcim_intr_enable()
+ */
+vxge_hal_status_e
+__hal_srpcim_intr_disable(
+    __hal_device_t * hldev,
+    u32 srpcim_id)
+{
+	vxge_hal_srpcim_reg_t *srpcim_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	srpcim_reg = hldev->srpcim_reg[srpcim_id];
+
+	/* Mask the individual interrupts. */
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->vpath_msg_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->srpcim_pcipif_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &srpcim_reg->srpcim_general_int_mask);
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+
+}
+
+/*
+ * vxge_hal_srpcim_intr_disable - Disable srpcim interrupts.
+ * @devh: Hal Device.
+ *
+ * Disable srpcim interrupts.
+ *
+ * See also: vxge_hal_srpcim_intr_enable()
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_intr_disable(
+    vxge_hal_device_h devh)
+{
+	u32 i;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			status = __hal_srpcim_intr_disable(hldev, i);
+
+		}
+
+	} else {
+		status = __hal_srpcim_intr_disable(hldev, hldev->srpcim_id);
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm
+ * @hldev: HAL device.
+ * @alarm_msix_id: MSIX vector for alarm.
+ *
+ * This API will associate a given MSIX vector numbers with srpcim alarm
+ */
+vxge_hal_status_e
+vxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id)
+{
+	u32 i;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    (u32) bVAL32(
+			    VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(
+			    alarm_msix_id),
+			    0),
+			    &hldev->srpcim_reg[i]->srpcim_interrupt_cfg1);
+
+		}
+
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(
+		    VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(
+		    alarm_msix_id),
+		    0),
+		    &hldev->srpcim_reg[hldev->srpcim_id]->
+		    srpcim_interrupt_cfg1);
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_srpcim_msix_mask - Mask MSIX Vector.
+ * @hldev: HAL device.
+ *
+ * The function masks the srpcim msix interrupt
+ *
+ */
+void
+vxge_hal_srpcim_msix_mask(vxge_hal_device_h devh)
+{
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return;
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    (u32) bVAL32(
+			    VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK,
+			    0),
+			    &hldev->srpcim_reg[i]->srpcim_set_msix_mask);
+
+		}
+
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(
+		    VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK,
+		    0),
+		    &hldev->srpcim_reg[hldev->srpcim_id]->srpcim_set_msix_mask);
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_srpcim_msix_clear - Clear MSIX Vector.
+ * @hldev: HAL device.
+ *
+ * The function clears the srpcim msix interrupt
+ *
+ */
+void
+vxge_hal_srpcim_msix_clear(vxge_hal_device_h devh)
+{
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return;
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    (u32) bVAL32(
+			    VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK,
+			    0),
+			    &hldev->srpcim_reg[i]->srpcim_clear_msix_mask);
+
+		}
+
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(
+		    VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK,
+		    0),
+		    &hldev->srpcim_reg[hldev->srpcim_id]->
+		    srpcim_clear_msix_mask);
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector.
+ * @hldev: HAL device.
+ *
+ * The function unmasks the srpcim msix interrupt
+ *
+ */
+void
+vxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh)
+{
+	u32 i;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+
+		return;
+
+	}
+
+	if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
+
+		for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
+
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    (u32) bVAL32(
+			    VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT,
+			    0),
+			    &hldev->srpcim_reg[i]->srpcim_clr_msix_one_shot);
+
+		}
+
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(
+		    VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT,
+		    0),
+		    &hldev->srpcim_reg[hldev->srpcim_id]->
+		    srpcim_clr_msix_one_shot);
+	}
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_srpcim_initialize - Initialize srpcim.
+ * @hldev: HAL Device
+ *
+ * Initialize srpcim.
+ *
+ */
+vxge_hal_status_e
+__hal_srpcim_initialize(
+    __hal_device_t * hldev)
+{
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+		return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
+	}
+
+	hldev->srpcim = (__hal_srpcim_t *)
+	    vxge_os_malloc(hldev->header.pdev, sizeof(__hal_srpcim_t));
+
+	if (hldev->srpcim == NULL) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
+		return (VXGE_HAL_ERR_OUT_OF_MEMORY);
+	}
+
+	vxge_os_memzero(hldev->srpcim, sizeof(__hal_srpcim_t));
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_srpcim_terminate - Terminate srpcim.
+ * @hldev: HAL Device
+ *
+ * Terminate srpcim.
+ *
+ */
+vxge_hal_status_e
+__hal_srpcim_terminate(
+    __hal_device_t * hldev)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_srpcim("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev);
+
+	if (hldev->srpcim == NULL) {
+		vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_os_free(hldev->header.pdev,
+	    hldev->srpcim, sizeof(__hal_srpcim_t));
+
+	hldev->srpcim = NULL;
+
+	vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-srpcim.h b/sys/dev/vxge/vxgehal/vxgehal-srpcim.h
new file mode 100644
index 000000000000..a0973209e85a
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-srpcim.h
@@ -0,0 +1,84 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_SRPCIM_H
+#define	VXGE_HAL_SRPCIM_H
+
+__EXTERN_BEGIN_DECLS
+
+/*
+ * __hal_srpcim_vpath_t
+ *
+ * HAL srpcim vpath messaging state.
+ */
+typedef struct __hal_srpcim_vpath_t {
+	u32	registered;
+	u32	srpcim_id;
+} __hal_srpcim_vpath_t;
+
+/*
+ * __hal_srpcim_t
+ *
+ * HAL srpcim object. Represents privileged mode srpcim device.
+ */
+typedef struct __hal_srpcim_t {
+	__hal_srpcim_vpath_t vpath_state[VXGE_HAL_MAX_VIRTUAL_PATHS];
+} __hal_srpcim_t;
+
+
+vxge_hal_status_e
+__hal_srpcim_alarm_process(
+    __hal_device_t *hldev,
+    u32 srpcim_id,
+    u32 skip_alarms);
+
+vxge_hal_status_e
+__hal_srpcim_intr_enable(
+    __hal_device_t *hldev,
+    u32 srpcim_id);
+
+vxge_hal_status_e
+__hal_srpcim_intr_disable(
+    __hal_device_t *hldev,
+    u32 srpcim_id);
+
+vxge_hal_status_e
+__hal_srpcim_initialize(
+    __hal_device_t *hldev);
+
+vxge_hal_status_e
+__hal_srpcim_terminate(
+    __hal_device_t *hldev);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_SRPCIM_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-swapper.c b/sys/dev/vxge/vxgehal/vxgehal-swapper.c
new file mode 100644
index 000000000000..475317d93fba
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-swapper.c
@@ -0,0 +1,243 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+/*
+ * _hal_legacy_swapper_set - Set the swapper bits for the legacy secion.
+ * @pdev: PCI device object.
+ * @regh: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
+ *	(Linux and the rest.)
+ * @legacy_reg: Address of the legacy register space.
+ *
+ * Set the swapper bits appropriately for the lagacy section.
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_SWAPPER_CTRL - failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+__hal_legacy_swapper_set(
+    pci_dev_h pdev,
+    pci_reg_h regh,
+    vxge_hal_legacy_reg_t *legacy_reg)
+{
+	u64 val64;
+	vxge_hal_status_e status;
+
+	vxge_assert(legacy_reg != NULL);
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh = 0x"VXGE_OS_STXFMT", "
+	    "legacy_reg = 0x"VXGE_OS_STXFMT, (ptr_t) pdev, (ptr_t) regh,
+	    (ptr_t) legacy_reg);
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh, &legacy_reg->toc_swapper_fb);
+
+	vxge_hal_info_log_driver("TOC Swapper Fb: 0x"VXGE_OS_LLXFMT, val64);
+
+	vxge_os_wmb();
+
+	switch (val64) {
+
+	case VXGE_HAL_SWAPPER_INITIAL_VALUE:
+		return (VXGE_HAL_OK);
+
+	case VXGE_HAL_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_READ_BYTE_SWAP_ENABLE,
+		    &legacy_reg->pifm_rd_swap_en);
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_READ_BIT_FLAP_ENABLE,
+		    &legacy_reg->pifm_rd_flip_en);
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
+		    &legacy_reg->pifm_wr_swap_en);
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_ENABLE,
+		    &legacy_reg->pifm_wr_flip_en);
+		break;
+
+	case VXGE_HAL_SWAPPER_BYTE_SWAPPED:
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_READ_BYTE_SWAP_ENABLE,
+		    &legacy_reg->pifm_rd_swap_en);
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
+		    &legacy_reg->pifm_wr_swap_en);
+		break;
+
+	case VXGE_HAL_SWAPPER_BIT_FLIPPED:
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_READ_BIT_FLAP_ENABLE,
+		    &legacy_reg->pifm_rd_flip_en);
+		vxge_os_pio_mem_write64(pdev, regh,
+		    VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_ENABLE,
+		    &legacy_reg->pifm_wr_flip_en);
+		break;
+
+	}
+
+	vxge_os_wmb();
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh, &legacy_reg->toc_swapper_fb);
+
+	if (val64 == VXGE_HAL_SWAPPER_INITIAL_VALUE) {
+		status = VXGE_HAL_OK;
+	} else {
+		vxge_hal_err_log_driver("%s:TOC Swapper setting failed",
+		    __func__);
+		status = VXGE_HAL_ERR_SWAPPER_CTRL;
+	}
+
+	vxge_hal_info_log_driver("TOC Swapper Fb: 0x"VXGE_OS_LLXFMT, val64);
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_swapper_set - Set the swapper bits for the vpath.
+ * @hldev: HAL device object.
+ * @vp_id: Vpath Id
+ *
+ * Set the swapper bits appropriately for the vpath.
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_SWAPPER_CTRL - failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+__hal_vpath_swapper_set(
+    vxge_hal_device_t *hldev,
+    u32 vp_id)
+{
+#if !defined(VXGE_OS_HOST_BIG_ENDIAN)
+	u64 val64;
+	vxge_hal_vpath_reg_t *vpath_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) hldev, vp_id);
+
+	vpath_reg = ((__hal_device_t *) hldev)->vpath_reg[vp_id];
+
+	val64 = vxge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
+	    &vpath_reg->vpath_general_cfg1);
+
+	vxge_os_wmb();
+
+	val64 |= VXGE_HAL_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
+
+	vxge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
+	    val64,
+	    &vpath_reg->vpath_general_cfg1);
+	vxge_os_wmb();
+
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+#endif
+	return (VXGE_HAL_OK);
+}
+
+
+/*
+ * __hal_kdfc_swapper_set - Set the swapper bits for the kdfc.
+ * @hldev: HAL device object.
+ * @vp_id: Vpath Id
+ *
+ * Set the swapper bits appropriately for the vpath.
+ *
+ * Returns:  VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_SWAPPER_CTRL - failed.
+ *
+ * See also: vxge_hal_status_e {}.
+ */
+vxge_hal_status_e
+__hal_kdfc_swapper_set(
+    vxge_hal_device_t *hldev,
+    u32 vp_id)
+{
+	u64 val64;
+	vxge_hal_vpath_reg_t *vpath_reg;
+	vxge_hal_legacy_reg_t *legacy_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("hldev = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) hldev, vp_id);
+
+	vpath_reg = ((__hal_device_t *) hldev)->vpath_reg[vp_id];
+	legacy_reg = ((__hal_device_t *) hldev)->legacy_reg;
+
+	val64 = vxge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
+	    &legacy_reg->pifm_wr_swap_en);
+
+	if (val64 == VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
+		    &vpath_reg->kdfcctl_cfg0);
+
+		vxge_os_wmb();
+
+		val64 |= VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
+		    VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
+		    VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
+
+		vxge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
+		    val64,
+		    &vpath_reg->kdfcctl_cfg0);
+		vxge_os_wmb();
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-swapper.h b/sys/dev/vxge/vxgehal/vxgehal-swapper.h
new file mode 100644
index 000000000000..97a5d56dbd50
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-swapper.h
@@ -0,0 +1,72 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_SWAPPER_H
+#define	VXGE_HAL_SWAPPER_H
+
+__EXTERN_BEGIN_DECLS
+
+#define	VXGE_HAL_SWAPPER_INITIAL_VALUE			0x0123456789abcdefULL
+#define	VXGE_HAL_SWAPPER_BYTE_SWAPPED			0xefcdab8967452301ULL
+#define	VXGE_HAL_SWAPPER_BIT_FLIPPED			0x80c4a2e691d5b3f7ULL
+#define	VXGE_HAL_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED	0xf7b3d591e6a2c480ULL
+
+#define	VXGE_HAL_SWAPPER_READ_BYTE_SWAP_ENABLE		0xFFFFFFFFFFFFFFFFULL
+#define	VXGE_HAL_SWAPPER_READ_BYTE_SWAP_DISABLE		0x0000000000000000ULL
+
+#define	VXGE_HAL_SWAPPER_READ_BIT_FLAP_ENABLE		0xFFFFFFFFFFFFFFFFULL
+#define	VXGE_HAL_SWAPPER_READ_BIT_FLAP_DISABLE		0x0000000000000000ULL
+
+#define	VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_ENABLE		0xFFFFFFFFFFFFFFFFULL
+#define	VXGE_HAL_SWAPPER_WRITE_BYTE_SWAP_DISABLE	0x0000000000000000ULL
+
+#define	VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_ENABLE		0xFFFFFFFFFFFFFFFFULL
+#define	VXGE_HAL_SWAPPER_WRITE_BIT_FLAP_DISABLE		0x0000000000000000ULL
+
+vxge_hal_status_e
+__hal_legacy_swapper_set(
+    pci_dev_h pdev,
+    pci_reg_h regh,
+    vxge_hal_legacy_reg_t *legacy_reg);
+vxge_hal_status_e
+__hal_vpath_swapper_set(
+    vxge_hal_device_t *hldev,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_kdfc_swapper_set(
+    vxge_hal_device_t *hldev,
+    u32 vp_id);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_SWAPPER_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-toc-reg.h b/sys/dev/vxge/vxgehal/vxgehal-toc-reg.h
new file mode 100644
index 000000000000..748f4b057499
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-toc-reg.h
@@ -0,0 +1,81 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_TOC_REGS_H
+#define	VXGE_HAL_TOC_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_toc_reg_t {
+
+	u8	unused00050[0x00050];
+
+/* 0x00050 */	u64	toc_common_pointer;
+#define	VXGE_HAL_TOC_COMMON_POINTER_INITIAL_VAL(val)	    vBIT(val, 0, 64)
+/* 0x00058 */	u64	toc_memrepair_pointer;
+#define	VXGE_HAL_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val)	    vBIT(val, 0, 64)
+/* 0x00060 */	u64	toc_pcicfgmgmt_pointer[17];
+#define	VXGE_HAL_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val)    vBIT(val, 0, 64)
+	u8	unused001e0[0x001e0 - 0x000e8];
+
+/* 0x001e0 */	u64	toc_mrpcim_pointer;
+#define	VXGE_HAL_TOC_MRPCIM_POINTER_INITIAL_VAL(val)	    vBIT(val, 0, 64)
+/* 0x001e8 */	u64	toc_srpcim_pointer[17];
+#define	VXGE_HAL_TOC_SRPCIM_POINTER_INITIAL_VAL(val)	    vBIT(val, 0, 64)
+	u8	unused00278[0x00278 - 0x00270];
+
+/* 0x00278 */	u64	toc_vpmgmt_pointer[17];
+#define	VXGE_HAL_TOC_VPMGMT_POINTER_INITIAL_VAL(val)	    vBIT(val, 0, 64)
+	u8	unused00390[0x00390 - 0x00300];
+
+/* 0x00390 */	u64	toc_vpath_pointer[17];
+#define	VXGE_HAL_TOC_VPATH_POINTER_INITIAL_VAL(val)	    vBIT(val, 0, 64)
+	u8	unused004a0[0x004a0 - 0x00418];
+
+/* 0x004a0 */	u64	toc_kdfc;
+#define	VXGE_HAL_TOC_KDFC_INITIAL_OFFSET(val)		    vBIT(val, 0, 61)
+#define	VXGE_HAL_TOC_KDFC_INITIAL_BIR(val)		    vBIT(val, 61, 3)
+/* 0x004a8 */	u64	toc_usdc;
+#define	VXGE_HAL_TOC_USDC_INITIAL_OFFSET(val)		    vBIT(val, 0, 61)
+#define	VXGE_HAL_TOC_USDC_INITIAL_BIR(val)		    vBIT(val, 61, 3)
+/* 0x004b0 */	u64	toc_kdfc_vpath_stride;
+#define	VXGE_HAL_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val)\
+							    vBIT(val, 0, 64)
+/* 0x004b8 */	u64	toc_kdfc_fifo_stride;
+#define	VXGE_HAL_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val)\
+							    vBIT(val, 0, 64)
+
+} vxge_hal_toc_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_TOC_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-virtualpath.c b/sys/dev/vxge/vxgehal/vxgehal-virtualpath.c
new file mode 100644
index 000000000000..ac51b9763195
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-virtualpath.c
@@ -0,0 +1,12143 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+#include <dev/vxge/vxgehal/vxgehal.h>
+
+
+/*
+ * __hal_vpath_fw_memo_get - Get the fw memo interface parameters
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ * @action: Action for FW Interface
+ * @param_index: Index of the parameter
+ * @data0: Buffer to return data 0 register contents
+ * @data1: Buffer to return data 1 register contents
+ *
+ * Returns FW memo interface parameters
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_fw_memo_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u32 action,
+    u64 param_index,
+    u64 *data0,
+    u64 *data1)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_reg != NULL) && (data0 != NULL) && (data1 != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", action = %d, "
+	    "param_index = %lld, data0 = 0x"VXGE_OS_STXFMT", "
+	    "data1 = 0x"VXGE_OS_STXFMT, (ptr_t) pdev, (ptr_t) regh0,
+	    vp_id, (ptr_t) vpath_reg, action, param_index,
+	    (ptr_t) data0, (ptr_t) data1);
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    0,
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    param_index,
+	    &vpath_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    0,
+	    &vpath_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+	vxge_hal_pio_mem_write32_lower(pdev,
+	    regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(pdev,
+	    regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(pdev, regh0,
+	    &vpath_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+
+		*data0 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpath_reg->rts_access_steer_data0);
+
+		*data1 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpath_reg->rts_access_steer_data1);
+
+		status = VXGE_HAL_OK;
+
+	} else {
+		status = VXGE_HAL_FAIL;
+	}
+
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_fw_flash_ver_get - Get the fw version
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ * @fw_version: Buffer to return FW Version (Major)
+ * @fw_date: Buffer to return FW Version (date)
+ * @flash_version: Buffer to return FW Version (Major)
+ * @flash_date: Buffer to return FW Version (date)
+ *
+ * Returns FW Version
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_fw_flash_ver_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    vxge_hal_device_version_t *fw_version,
+    vxge_hal_device_date_t *fw_date,
+    vxge_hal_device_version_t *flash_version,
+    vxge_hal_device_date_t *flash_date)
+{
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_reg != NULL) && (fw_version != NULL) &&
+	    (fw_date != NULL) && (flash_version != NULL) &&
+	    (flash_date != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
+	    "fw_version = 0x"VXGE_OS_STXFMT", "
+	    "fw_date = 0x"VXGE_OS_STXFMT", "
+	    "flash_version = 0x"VXGE_OS_STXFMT", "
+	    "flash_date = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
+	    (ptr_t) fw_version, (ptr_t) fw_date,
+	    (ptr_t) flash_version, (ptr_t) flash_date);
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_VERSION,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FW_VERSION,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	fw_date->day =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data1);
+	fw_date->month =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data1);
+	fw_date->year =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data1);
+
+	(void) vxge_os_snprintf(fw_date->date, sizeof(fw_date->date),
+	    "%2.2d/%2.2d/%4.4d",
+	    fw_date->month, fw_date->day, fw_date->year);
+
+	fw_version->major =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1);
+	fw_version->minor =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1);
+	fw_version->build =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1);
+
+	(void) vxge_os_snprintf(fw_version->version,
+	    sizeof(fw_version->version),
+	    "%d.%d.%d", fw_version->major,
+	    fw_version->minor, fw_version->build);
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_FLASH_VERSION,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	flash_date->day =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_DAY(data1);
+	flash_date->month =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MONTH(data1);
+	flash_date->year =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_YEAR(data1);
+
+	(void) vxge_os_snprintf(flash_date->date, sizeof(flash_date->date),
+	    "%2.2d/%2.2d/%4.4d", flash_date->month, flash_date->day,
+	    flash_date->year);
+
+	flash_version->major =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MAJOR(data1);
+	flash_version->minor =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_MINOR(data1);
+	flash_version->build =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FLASH_VER_BUILD(data1);
+
+	(void) vxge_os_snprintf(flash_version->version,
+	    sizeof(flash_version->version),
+	    "%d.%d.%d", flash_version->major,
+	    flash_version->minor, flash_version->build);
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_card_info_get - Get the card infor
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ * @serial_number: Buffer to return card serial number
+ * @part_number: Buffer to return card part number
+ * @product_description: Buffer to return card description
+ *
+ * Returns Card Info
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_card_info_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u8 *serial_number,
+    u8 *part_number,
+    u8 *product_description)
+{
+	u32 i, j;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_reg != NULL) && (serial_number != NULL) &&
+	    (part_number != NULL) && (product_description != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
+	    "serial_number = 0x"VXGE_OS_STXFMT", "
+	    "part_number = 0x"VXGE_OS_STXFMT", "
+	    "product_description = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
+	    (ptr_t) serial_number, (ptr_t) part_number,
+	    (ptr_t) product_description);
+
+	*serial_number = 0;
+	*part_number = 0;
+	*product_description = 0;
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	/* LINTED */
+	((u64 *) serial_number)[0] = vxge_os_ntohll(data1);
+
+	/* LINTED */
+	((u64 *) serial_number)[1] = vxge_os_ntohll(data2);
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	/* LINTED */
+	((u64 *) part_number)[0] = vxge_os_ntohll(data1);
+
+	/* LINTED */
+	((u64 *) part_number)[1] = vxge_os_ntohll(data2);
+
+	j = 0;
+
+	for (i = VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
+	    i <= VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3;
+	    i++) {
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    i,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) product_description)[j++] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) product_description)[j++] = vxge_os_ntohll(data2);
+
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_pmd_info_get - Get the PMD info
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ * @ports: Number of ports supported
+ * @pmd_port0: Buffer to return PMD info for port 0
+ * @pmd_port1: Buffer to return PMD info for port 1
+ *
+ * Returns PMD Info
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_pmd_info_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u32 *ports,
+    vxge_hal_device_pmd_info_t *pmd_port0,
+    vxge_hal_device_pmd_info_t *pmd_port1)
+{
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_reg != NULL) &&
+	    (pmd_port0 != NULL) && (pmd_port1 != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
+	    "ports = 0x"VXGE_OS_STXFMT", "
+	    "pmd_port0 = 0x"VXGE_OS_STXFMT", "
+	    "pmd_port1 = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
+	    (ptr_t) ports, (ptr_t) pmd_port0, (ptr_t) pmd_port1);
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	*ports = (u32) data1;
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (data1) {
+
+		pmd_port0->type = (u32) data1;
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) pmd_port0->vendor)[0] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) pmd_port0->vendor)[1] = vxge_os_ntohll(data2);
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) pmd_port0->part_num)[0] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) pmd_port0->part_num)[1] = vxge_os_ntohll(data2);
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) pmd_port0->ser_num)[0] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) pmd_port0->ser_num)[1] = vxge_os_ntohll(data2);
+	} else {
+		vxge_os_memzero(pmd_port0, sizeof(vxge_hal_device_pmd_info_t));
+	}
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE,
+	    &data1, &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (data1) {
+
+		pmd_port1->type = (u32) data1;
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) pmd_port1->vendor)[0] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) pmd_port1->vendor)[1] = vxge_os_ntohll(data2);
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) pmd_port1->part_num)[0] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) pmd_port1->part_num)[1] = vxge_os_ntohll(data2);
+
+		status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_MEMO_CARD_INFO,
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO,
+		    &data1, &data2);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		/* LINTED */
+		((u64 *) pmd_port1->ser_num)[0] = vxge_os_ntohll(data1);
+
+		/* LINTED */
+		((u64 *) pmd_port1->ser_num)[1] = vxge_os_ntohll(data2);
+
+	} else {
+		vxge_os_memzero(pmd_port1, sizeof(vxge_hal_device_pmd_info_t));
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_pci_func_mode_get - Get the pci mode
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ *
+ * Returns pci function mode
+ *
+ */
+u64
+__hal_vpath_pci_func_mode_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg)
+{
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_reg != NULL);
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg);
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE,
+	    &data1, &data2);
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (data1);
+}
+
+/*
+ * __hal_vpath_lag_mode_get - Get the LAG mode
+ * @vpath: VIrtual Path
+ *
+ * Returns the LAG mode in use
+ */
+vxge_hal_device_lag_mode_e
+__hal_vpath_lag_mode_get(__hal_virtualpath_t *vpath)
+{
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	u32 lag_mode = VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	(void) __hal_vpath_fw_memo_get(hldev->header.pdev, hldev->header.regh0,
+	    vpath->vp_id, vpath->vp_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_INFO,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_LAG_MODE,
+	    &data1, &data2);
+
+	if (VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_MEMO_ITEM_STATUS(data1) ==
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS_SUCCESS) {
+		lag_mode = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_GET_LAG_MODE(data2);
+		status = VXGE_HAL_OK;
+	} else {
+		status = VXGE_HAL_FAIL;
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return ((vxge_hal_device_lag_mode_e) lag_mode);
+}
+
+/*
+ * __hal_vpath_vpath_map_get - Get the vpath map
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vh: Virtual Hierrachy
+ * @func: Function number
+ * @vpath_reg: Pointer to vpath registers
+ *
+ * Returns vpath map for a give hierarchy and function
+ *
+ */
+u64
+__hal_vpath_vpath_map_get(pci_dev_h pdev, pci_reg_h regh0,
+    u32 vp_id, u32 vh, u32 func,
+    vxge_hal_vpath_reg_t *vpath_reg)
+{
+	u64 i;
+	u64 val64 = 0ULL;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_reg != NULL);
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vh = %d, func = %d, vpath_reg = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, vh, func, (ptr_t) vpath_reg);
+
+	status = __hal_vpath_fw_memo_get(pdev, regh0, vp_id, vpath_reg,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_VPATH_MAP,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_VH(vh) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNCTION(func),
+	    &data1, &data2);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+		if (data2 & VXGE_HAL_RTS_ACCESS_STEER_DATA1_IS_VPATH_ASSIGNED(i))
+			val64 |= mBIT(i);
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (val64);
+}
+
+/*
+ * __hal_vpath_pci_read - Read the content of given address
+ *			 in pci config space.
+ * @vpath: Virtual Path object.
+ * @offset: Configuration address(offset)to read from
+ * @length: Length of the data (1, 2 or 4 bytes)
+ * @val: Pointer to a buffer to return the content of the address
+ *
+ * Read from the vpath pci config space.
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_pci_read(struct __hal_device_t *hldev,
+    u32 vp_id, u32 offset,
+    u32 length, void *val)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((hldev != NULL) && (val != NULL));
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, "
+	    "offset = %d, val = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, vp_id, offset, (ptr_t) val);
+
+	switch (length) {
+	case 1:
+		vxge_os_pci_read8(hldev->header.pdev,
+		    hldev->header.cfgh,
+		    offset,
+		    ((u8 *) val));
+		break;
+	case 2:
+		vxge_os_pci_read16(hldev->header.pdev,
+		    hldev->header.cfgh,
+		    offset,
+		    ((u16 *) val));
+		break;
+	case 4:
+		vxge_os_pci_read32(hldev->header.pdev,
+		    hldev->header.cfgh,
+		    offset,
+		    ((u32 *) val));
+		break;
+	default:
+		status = VXGE_HAL_FAIL;
+		vxge_os_memzero(val, length);
+		break;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_fw_upgrade - Upgrade the firmware
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ * @buffer: Buffer containing F/W image
+ * @length: Length of F/W image
+ *
+ * Upgrade the firmware
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_fw_upgrade(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u8 *buffer,
+    u32 length)
+{
+	u32 i = 0;
+	u64 val64;
+	u32 not_done = TRUE;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_reg != NULL) && (buffer != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
+	    "buffer = 0x"VXGE_OS_STXFMT", length = %d\n",
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
+	    (ptr_t) buffer, length);
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    0,
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_STREAM_SKIP,
+	    &vpath_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    0,
+	    &vpath_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_MODE);
+
+	vxge_hal_pio_mem_write32_lower(pdev, regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(pdev, regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = __hal_device_register_stall(pdev, regh0,
+	    &vpath_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	while (not_done) {
+		if ((i + 16) > length) {
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+			return (VXGE_HAL_FAIL);
+		}
+		vxge_os_pio_mem_write64(pdev, regh0, ((u64) (buffer[i])) |
+		    ((u64) (buffer[i + 1]) << 8) |
+		    ((u64) (buffer[i + 2]) << 16) |
+		    ((u64) (buffer[i + 3]) << 24) |
+		    ((u64) (buffer[i + 4]) << 32) |
+		    ((u64) (buffer[i + 5]) << 40) |
+		    ((u64) (buffer[i + 6]) << 48) |
+		    ((u64) (buffer[i + 7]) << 56),
+		    &vpath_reg->rts_access_steer_data0);
+
+		vxge_os_pio_mem_write64(pdev, regh0,
+		    ((u64) (buffer[i + 8])) |
+		    ((u64) (buffer[i + 9]) << 8) |
+		    ((u64) (buffer[i + 10]) << 16) |
+		    ((u64) (buffer[i + 11]) << 24) |
+		    ((u64) (buffer[i + 12]) << 32) |
+		    ((u64) (buffer[i + 13]) << 40) |
+		    ((u64) (buffer[i + 14]) << 48) |
+		    ((u64) (buffer[i + 15]) << 56),
+		    &vpath_reg->rts_access_steer_data1);
+		vxge_os_wmb();
+
+		val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE) |
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_DATA);
+		vxge_hal_pio_mem_write32_lower(pdev, regh0,
+		    (u32) bVAL32(val64, 32),
+		    &vpath_reg->rts_access_steer_ctrl);
+
+		vxge_os_wmb();
+
+		vxge_hal_pio_mem_write32_upper(pdev, regh0,
+		    (u32) bVAL32(val64, 0), &vpath_reg->rts_access_steer_ctrl);
+		vxge_os_wmb();
+
+		status = __hal_device_register_stall(pdev, regh0,
+		    &vpath_reg->rts_access_steer_ctrl, 0,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+		    WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpath_reg->rts_access_steer_ctrl);
+		if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+			return (VXGE_HAL_FAIL);
+		}
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpath_reg->rts_access_steer_data0);
+		switch (VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(val64)) {
+		case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_OK:
+			i += 16;
+			break;
+		case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_DONE:
+			not_done = FALSE;
+			break;
+		case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_SKIP:
+			i += 16;
+			i += (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(val64);
+			break;
+		case VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE_ERROR:
+		default:
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+			return (VXGE_HAL_FAIL);
+		}
+	}
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    0,
+	    &vpath_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(pdev,
+	    regh0,
+	    0,
+	    &vpath_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FW_UPGRADE) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET_FW_UPGRADE_COMMIT);
+
+	vxge_hal_pio_mem_write32_lower(pdev,
+	    regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(pdev,
+	    regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = __hal_device_register_stall(pdev, regh0,
+	    &vpath_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    100 * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(pdev, regh0,
+	    &vpath_reg->rts_access_steer_ctrl);
+
+	if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
+
+		vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, VXGE_HAL_OK);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_flick_link_led - Flick (blink) link LED.
+ * @hldev: HAL device.
+ * @vp_id: Vpath Id
+ * @port : Port number 0, or 1
+ * @on_off: TRUE if flickering to be on, FALSE to be off
+ *
+ * Flicker the link LED.
+ */
+vxge_hal_status_e
+__hal_vpath_flick_link_led(struct __hal_device_t *hldev,
+    u32 vp_id, u32 port, u32 on_off)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_vpath_reg_t *vp_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, port = %d, on_off = %d",
+	    (ptr_t) hldev, vp_id, port, on_off);
+
+	vp_reg = hldev->vpath_reg[vp_id];
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) on_off,
+	    &vp_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_udp_rth_set - Enable or Disable UDP/RTH.
+ * @hldev: HAL device.
+ * @vp_id: Vpath Id
+ * @on_off: TRUE if UDP/RTH to be enabled, FALSE to be disabled
+ *
+ * Enable or Disable UDP/RTH.
+ */
+vxge_hal_status_e
+__hal_vpath_udp_rth_set(
+    struct __hal_device_t *hldev,
+    u32 vp_id,
+    u32 on_off)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_vpath_reg_t *vp_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, on_off = %d",
+	    (ptr_t) hldev, vp_id, on_off);
+
+	vp_reg = hldev->vpath_reg[vp_id];
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    ((on_off) ? VXGE_HAL_RTS_ACCESS_STEER_DATA0_UDP_RTH_ENABLE : 0),
+	    &vp_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_UDP_RTH) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_pcie_func_mode_set - Set PCI-E function mode.
+ * @hldev: HAL device.
+ * @vp_id: Vpath Id
+ * @func_mode: func_mode to be set
+ *
+ * Set PCI-E function mode.
+ */
+vxge_hal_status_e
+__hal_vpath_pcie_func_mode_set(struct __hal_device_t *hldev,
+    u32 vp_id, u32 func_mode)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_vpath_reg_t *vp_reg;
+
+	vxge_assert(hldev != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "hldev = 0x"VXGE_OS_STXFMT", vp_id = %d, func_mode = %d",
+	    (ptr_t) hldev, vp_id, func_mode);
+
+	vp_reg = hldev->vpath_reg[vp_id];
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE(func_mode),
+	    &vp_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_FUNC_MODE) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_COMMIT) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+		status = VXGE_HAL_OK;
+	} else {
+		status = VXGE_HAL_FAIL;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_udp_rth_disable - Enable UDP/RTH.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable udp rth
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_udp_rth_disable(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_udp_rth_set(hldev,
+	    vpath->vp_id,
+	    FALSE);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_rts_table_get - Get the entries from RTS access tables
+ * @vpath_handle: Vpath handle.
+ * @action: Identifies the action to take on the specified entry. The
+ *	    interpretation of this field depends on the DATA_STRUCT_SEL field
+ *	    DA, VID, ETYPE, PN, RANGE_PN:
+ *		8'd0 - ADD_ENTRY (Add an entry to the table. This command may be
+ *		rejected by management/administration).
+ *		8'd1 - DELETE_ENTRY (Add an entry to the table. This command may
+ *		be rejected by management/administration)
+ *		8'd2 - LIST_FIRST_ENTRY
+ *		8'd3 - LIST_NEXT_ENTRY
+ *		RTH_GEN_CFG, RTH_IT, RTH_JHASH_CFG, RTH_MASK, RTH_KEY, QOS, DS:
+ *		8'd0 - READ_ENTRY
+ *		  8'd1 - WRITE_ENTRY
+ *		Note: This field is updated by the H/W during an operation and
+ *		is used to report additional TBD status information back to the
+ *		host.
+ * @rts_table: Identifies the RTS data structure (i.e. lookup table) to access.
+ *		0; DA; Destination Address 1; VID; VLAN ID 2; ETYPE; Ethertype
+ *		3; PN; Layer 4 Port Number 4; Reserved 5; RTH_GEN_CFG; Receive
+ *		Traffic Hashing General Configuration 6; RTH_IT; Receive Traffic
+ *		Hashing Indirection Table 7; RTH_JHASH_CFG; Receive-Traffic
+ *		Hashing Jenkins Hash Configuration 8; RTH_MASK; Receive Traffic
+ *		Hashing Mask 9; RTH_KEY; Receive-Traffic Hashing Key 10; QOS;
+ *		VLAN Quality of Service 11; DS; IP Differentiated Services
+ * @offset: Applies to RTH_IT, RTH_MASK, RTH_KEY, QOS, DS structures only.
+ *		The interpretation of this field depends on the DATA_STRUCT_SEL
+ *		field:
+ *		RTH_IT - {BUCKET_NUM[0:7]} (Bucket Number)
+ *		RTH_MASK - {5'b0,
+ *		INDEX_8BYTE} (8-byte Index)
+ *		RTH_KEY - {5'b0, INDEX_8BYTE} (8-byte Index)
+ *		QOS - {5'b0, PRI} (Priority)
+ *		DS - {5'b0, CP} (Codepoint)
+ * @data1: Pointer to the data 1 to be read from the table
+ * @data2: Pointer to the data 2 to be read from the table
+ *
+ * Read from the RTS table
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_rts_table_get(
+    vxge_hal_vpath_h vpath_handle,
+    u32 action,
+    u32 rts_table,
+    u32 offset,
+    u64 *data1,
+    u64 *data2)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_handle != NULL) &&
+	    (data1 != NULL) && (data2 != NULL));
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, "
+	    "offset = %d, data1 = 0x"VXGE_OS_STXFMT", data2 = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, action, rts_table, offset, (ptr_t) data1,
+	    (ptr_t) data2);
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
+
+
+	if ((rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
+		val64 |= VXGE_HAL_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
+	}
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vpath->vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vpath->vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rts_access_steer_ctrl);
+
+	if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_FAIL);
+		return (VXGE_HAL_FAIL);
+	}
+
+	*data1 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rts_access_steer_data0);
+
+	if ((rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
+		*data2 = vxge_os_pio_mem_read64(
+		    hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->rts_access_steer_data1);
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_rts_table_set - Set the entries of RTS access tables
+ * @vpath_handle: Vpath handle.
+ * @action: Identifies the action to take on the specified entry. The
+ *		interpretation of this field depends on DATA_STRUCT_SEL field
+ *		DA, VID, ETYPE, PN, RANGE_PN:
+ *		8'd0 - ADD_ENTRY (Add an entry to the table. This command may be
+ *		   rejected by management/administration).
+ *		8'd1 - DELETE_ENTRY (Add an entry to the table. This command may
+ *		   be rejected by management/administration)
+ *		8'd2 - LIST_FIRST_ENTRY
+ *		8'd3 - LIST_NEXT_ENTRY
+ *		RTH_GEN_CFG, RTH_IT, RTH_JHASH_CFG, RTH_MASK, RTH_KEY, QOS, DS:
+ *		8'd0 - READ_ENTRY
+ *		  8'd1 - WRITE_ENTRY
+ *		Note: This field is updated by the H/W during an operation and
+ *		is used to report additional TBD status information back to the
+ *		host.
+ * @rts_table: Identifies the RTS data structure (i.e. lookup table) to access.
+ *		0; DA; Destination Address 1; VID; VLAN ID 2; ETYPE; Ethertype
+ *		3; PN; Layer 4 Port Number 4; Reserved 5; RTH_GEN_CFG; Receive
+ *		Traffic Hashing General Configuration 6; RTH_IT; Receive Traffic
+ *		Hashing Indirection Table 7; RTH_JHASH_CFG; Receive-Traffic
+ *		Hashing Jenkins Hash Configuration 8; RTH_MASK; Receive Traffic
+ *		Hashing Mask 9; RTH_KEY; Receive-Traffic Hashing Key 10; QOS;
+ *		VLAN Quality of Service 11; DS; IP Differentiated Services
+ * @offset: Applies to RTH_IT, RTH_MASK, RTH_KEY, QOS, DS structures only.
+ *		The interpretation of this field depends on the DATA_STRUCT_SEL
+ *		field:
+ *		RTH_IT - {BUCKET_NUM[0:7]} (Bucket Number)
+ *		RTH_MASK - {5'b0,
+ *		INDEX_8BYTE} (8-byte Index)
+ *		RTH_KEY - {5'b0, INDEX_8BYTE} (8-byte Index)
+ *		QOS - {5'b0, PRI} (Priority)
+ *		DS - {5'b0, CP} (Codepoint)
+ * @data1: data 1 to be written to the table
+ * @data2: data 2 to be written to the table
+ *
+ * Read from the RTS table
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_rts_table_set(
+    vxge_hal_vpath_h vpath_handle,
+    u32 action,
+    u32 rts_table,
+    u32 offset,
+    u64 data1,
+    u64 data2)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, "
+	    "offset = %d, data1 = 0x"VXGE_OS_LLXFMT", data2 = 0x"VXGE_OS_LLXFMT,
+	    (ptr_t) vpath_handle, action, rts_table, offset, data1, data2);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    data1,
+	    &vpath->vp_reg->rts_access_steer_data0);
+	vxge_os_wmb();
+
+	if ((rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
+	    (rts_table ==
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    data2,
+		    &vpath->vp_reg->rts_access_steer_data1);
+		vxge_os_wmb();
+
+	}
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vpath->vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vpath->vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rts_access_steer_ctrl);
+
+	if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+
+		status = VXGE_HAL_OK;
+
+	} else {
+		status = VXGE_HAL_FAIL;
+	}
+
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+
+/*
+ * vxge_hal_vpath_mac_addr_add - Add the mac address entry for this vpath
+ *		  to MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: MAC address to be added for this vpath into the list
+ * @macaddr_mask: MAC address mask for macaddr
+ * @duplicate_mode: Duplicate MAC address add mode. Please see
+ *		vxge_hal_vpath_mac_addr_add_mode_e {}
+ *
+ * Adds the given mac address and mac address mask into the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and
+ * vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_add(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask,
+    vxge_hal_vpath_mac_addr_add_mode_e duplicate_mode)
+{
+	u32 i;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, "
+	    "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x",
+	    (ptr_t) vpath_handle, macaddr[0], macaddr[1], macaddr[2],
+	    macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0],
+	    macaddr_mask[1], macaddr_mask[2], macaddr_mask[3],
+	    macaddr_mask[4], macaddr_mask[5]);
+
+	for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
+		data1 <<= 8;
+		data1 |= (u8) macaddr[i];
+	}
+
+	for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
+		data2 <<= 8;
+		data2 |= (u8) macaddr_mask[i];
+	}
+
+	switch (duplicate_mode) {
+	case VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE:
+		i = 0;
+		break;
+
+	case VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
+		i = 1;
+		break;
+
+	case VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
+		i = 2;
+		break;
+
+	default:
+		i = 0;
+		break;
+	}
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_hw_addr_get - Get the hw address entry for this vpath
+ *		  from MAC address table.
+ * @pdev: PCI device object.
+ * @regh0: BAR0 mapped memory handle, or simply PCI device @pdev
+ * (Linux and the rest.)
+ * @vp_id: Vpath id
+ * @vpath_reg: Pointer to vpath registers
+ * @macaddr: First MAC address entry for this vpath in the list
+ * @macaddr_mask: MAC address mask for macaddr
+ *
+ * Returns the first mac address and mac address mask in the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_hw_addr_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask)
+{
+	u32 i;
+	u64 val64;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	u64 action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_reg != NULL) && (macaddr != NULL) &&
+	    (macaddr_mask != NULL));
+
+	vxge_hal_trace_log_driver("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_driver(
+	    "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", "
+	    "vp_id = %d, vpath_reg = 0x"VXGE_OS_STXFMT", "
+	    "macaddr = 0x"VXGE_OS_STXFMT", macaddr_mask = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) pdev, (ptr_t) regh0, vp_id, (ptr_t) vpath_reg,
+	    (ptr_t) macaddr, (ptr_t) macaddr_mask);
+
+	/* CONSTCOND */
+	while (TRUE) {
+
+		val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) |
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE |
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(0);
+
+		vxge_hal_pio_mem_write32_lower(pdev,
+		    regh0,
+		    (u32) bVAL32(val64, 32),
+		    &vpath_reg->rts_access_steer_ctrl);
+
+		vxge_os_wmb();
+
+		vxge_hal_pio_mem_write32_upper(pdev,
+		    regh0,
+		    (u32) bVAL32(val64, 0),
+		    &vpath_reg->rts_access_steer_ctrl);
+
+		vxge_os_wmb();
+
+		status = vxge_hal_device_register_poll(pdev, regh0,
+		    &vpath_reg->rts_access_steer_ctrl, 0,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+		    WAIT_FACTOR * VXGE_HAL_DEF_DEVICE_POLL_MILLIS);
+
+		if (status != VXGE_HAL_OK) {
+
+			vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+
+		val64 = vxge_os_pio_mem_read64(pdev, regh0,
+		    &vpath_reg->rts_access_steer_ctrl);
+
+		if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+			data1 = vxge_os_pio_mem_read64(pdev, regh0,
+			    &vpath_reg->rts_access_steer_data0);
+			data2 = vxge_os_pio_mem_read64(pdev, regh0,
+			    &vpath_reg->rts_access_steer_data1);
+			data1 =
+			    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
+			data2 =
+			    VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
+
+			if (VXGE_HAL_IS_UNICAST(data1)) {
+
+				for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+					macaddr[i - 1] = (u8) (data1 & 0xFF);
+					data1 >>= 8;
+				}
+				for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+				    macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
+				    data2 >>= 8;
+				}
+				status = VXGE_HAL_OK;
+				break;
+			}
+			action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
+		} else {
+			status = VXGE_HAL_FAIL;
+			break;
+		}
+	}
+
+	vxge_hal_trace_log_driver("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_mac_addr_get - Get the first mac address entry for this vpath
+ *		  from MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: First MAC address entry for this vpath in the list
+ * @macaddr_mask: MAC address mask for macaddr
+ *
+ * Returns the first mac address and mac address mask in the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_get(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask)
+{
+	u32 i;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
+	    0,
+	    &data1,
+	    &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
+
+	data2 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
+
+	for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+		macaddr[i - 1] = (u8) (data1 & 0xFF);
+		data1 >>= 8;
+	}
+
+	for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+		macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
+		data2 >>= 8;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_mac_addr_get_next - Get the next mac address entry for vpath
+ *		  from MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: Next MAC address entry for this vpath in the list
+ * @macaddr_mask: MAC address mask for macaddr
+ *
+ * Returns the next mac address and mac address mask in the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask)
+{
+	u32 i;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
+	    0,
+	    &data1,
+	    &data2);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
+
+	data2 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
+
+	for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+		macaddr[i - 1] = (u8) (data1 & 0xFF);
+		data1 >>= 8;
+	}
+
+	for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) {
+		macaddr_mask[i - 1] = (u8) (data2 & 0xFF);
+		data2 >>= 8;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+
+/*
+ * vxge_hal_vpath_mac_addr_delete - Delete the mac address entry for this vpath
+ *		  to MAC address table.
+ * @vpath_handle: Vpath handle.
+ * @macaddr: MAC address to be added for this vpath into the list
+ * @macaddr_mask: MAC address mask for macaddr
+ *
+ * Delete the given mac address and mac address mask into the list for this
+ * vpath.
+ * see also: vxge_hal_vpath_mac_addr_add, vxge_hal_vpath_mac_addr_get and
+ * vxge_hal_vpath_mac_addr_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mac_addr_delete(
+    vxge_hal_vpath_h vpath_handle,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask)
+{
+	u32 i;
+	u64 data1 = 0ULL;
+	u64 data2 = 0ULL;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, "
+	    "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x",
+	    (ptr_t) vpath_handle, macaddr[0], macaddr[1], macaddr[2],
+	    macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0],
+	    macaddr_mask[1], macaddr_mask[2], macaddr_mask[3],
+	    macaddr_mask[4], macaddr_mask[5]);
+
+	for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
+		data1 <<= 8;
+		data1 |= (u8) macaddr[i];
+	}
+
+	for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) {
+		data2 <<= 8;
+		data2 |= (u8) macaddr_mask[i];
+	}
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_vid_add - Add the vlan id entry for this vpath
+ *		  to vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: vlan id to be added for this vpath into the list
+ *
+ * Adds the given vlan id into the list for this  vpath.
+ * see also: vxge_hal_vpath_vid_delete, vxge_hal_vpath_vid_get and
+ * vxge_hal_vpath_vid_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_add(
+    vxge_hal_vpath_h vpath_handle,
+    u64 vid)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", vid = %d",
+	    (ptr_t) vpath_handle, (u32) vid);
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid),
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_vid_get - Get the first vid entry for this vpath
+ *		  from vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: Buffer to return vlan id
+ *
+ * Returns the first vlan id in the list for this vpath.
+ * see also: vxge_hal_vpath_vid_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_get(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *vid)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (vid != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", vid = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) vid);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
+	    0,
+	    vid,
+	    NULL);
+
+	*vid = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_vid_get_next - Get the next vid entry for this vpath
+ *		  from vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: Buffer to return vlan id
+ *
+ * Returns the next vlan id in the list for this vpath.
+ * see also: vxge_hal_vpath_vid_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *vid)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (vid != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", vid = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) vid);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
+	    0,
+	    vid,
+	    NULL);
+
+	*vid = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_vid_delete - Delete the vlan id entry for this vpath
+ *		  to vlan id table.
+ * @vpath_handle: Vpath handle.
+ * @vid: vlan id to be added for this vpath into the list
+ *
+ * Adds the given vlan id into the list for this  vpath.
+ * see also: vxge_hal_vpath_vid_add, vxge_hal_vpath_vid_get and
+ * vxge_hal_vpath_vid_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_vid_delete(
+    vxge_hal_vpath_h vpath_handle,
+    u64 vid)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", vid = %d",
+	    (ptr_t) vpath_handle, (u32) vid);
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid),
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_etype_add - Add the Ethertype entry for this vpath
+ *		  to Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: ethertype to be added for this vpath into the list
+ *
+ * Adds the given Ethertype into the list for this  vpath.
+ * see also: vxge_hal_vpath_etype_delete, vxge_hal_vpath_etype_get and
+ * vxge_hal_vpath_etype_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_add(
+    vxge_hal_vpath_h vpath_handle,
+    u64 etype)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"
+	    VXGE_OS_STXFMT", etype = %d",
+	    (ptr_t) vpath_handle, (u32) etype);
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(etype),
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_etype_get - Get the first ethertype entry for this vpath
+ *		  from Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: Buffer to return Ethertype
+ *
+ * Returns the first ethype entry in the list for this vpath.
+ * see also: vxge_hal_vpath_etype_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_get(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *etype)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (etype != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", etype = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) etype);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
+	    0,
+	    etype,
+	    NULL);
+
+	*etype = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(*etype);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_etype_get_next - Get the next Ethertype entry for this vpath
+ *		  from Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: Buffer to return Ethwrtype
+ *
+ * Returns the next Ethwrtype in the list for this vpath.
+ * see also: vxge_hal_vpath_etype_get
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    u64 *etype)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (etype != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", etype = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) etype);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
+	    0,
+	    etype,
+	    NULL);
+
+	*etype = VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_ETYPE(*etype);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_etype_delete - Delete the Ethertype entry for this vpath
+ *		  to Ethertype table.
+ * @vpath_handle: Vpath handle.
+ * @etype: ethertype to be added for this vpath into the list
+ *
+ * Adds the given Ethertype into the list for this  vpath.
+ * see also: vxge_hal_vpath_etype_add, vxge_hal_vpath_etype_get and
+ * vxge_hal_vpath_etype_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_etype_delete(vxge_hal_vpath_h vpath_handle, u64 etype)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"
+	    VXGE_OS_STXFMT", etype = %d",
+	    (ptr_t) vpath_handle, (u32) etype);
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(etype),
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_port_add - Add the port entry for this vpath
+ *		  to port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: if 0 - Src port or 1 - Dest port
+ * @protocol: if 0 - TCP or 1 - UDP
+ * @port: port to be added for this vpath into the list
+ *
+ * Adds the given port into the list for this  vpath.
+ * see also: vxge_hal_vpath_port_delete, vxge_hal_vpath_port_get and
+ * vxge_hal_vpath_port_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_add(
+    vxge_hal_vpath_h vpath_handle,
+    u32 port_type,
+    u32 protocol,
+    u32 port)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = %d, "
+	    "protocol = %d, port = %d", (ptr_t) vpath_handle, port_type,
+	    protocol, port);
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(port);
+
+	if (port_type)
+		val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL;
+
+	if (protocol)
+		val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL;
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
+	    0,
+	    val64,
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_port_get
+ * Get the first port number entry for this vpath from port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: Buffer to return if 0 - Src port or 1 - Dest port
+ * @protocol: Buffer to return if 0 - TCP or 1 - UDP
+ * @port: Buffer to return port number
+ *
+ * Returns the first port number entry in the list for this vpath.
+ * see also: vxge_hal_vpath_port_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_get(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *port_type,
+    u32 *protocol,
+    u32 *port)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (port_type != NULL) &&
+	    (protocol != NULL) && (port != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = 0x"VXGE_OS_STXFMT
+	    ", protocol = 0x"VXGE_OS_STXFMT", port = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) port_type, (ptr_t) protocol,
+	    (ptr_t) port);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
+	    0,
+	    &val64,
+	    NULL);
+
+	*port_type =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(val64);
+	*protocol =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(val64);
+	*port = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(val64);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_port_get_next
+ * Get the next port number entry for this vpath from port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: Buffer to return if 0 - Src port or 1 - Dest port
+ * @protocol: Buffer to return if 0 - TCP or 1 - UDP
+ * @port: Buffer to return port number
+ *
+ * Returns the next port number entry in the list for this vpath.
+ * see also: vxge_hal_vpath_port_get
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_get_next(
+    vxge_hal_vpath_h vpath_handle,
+    u32 *port_type,
+    u32 *protocol,
+    u32 *port)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (port_type != NULL) &&
+	    (protocol != NULL) && (port != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = 0x"VXGE_OS_STXFMT
+	    ", protocol = 0x"VXGE_OS_STXFMT", port = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) port_type, (ptr_t) protocol,
+	    (ptr_t) port);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
+	    0,
+	    &val64,
+	    NULL);
+
+	*port_type =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(val64);
+
+	*protocol =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(val64);
+
+	*port = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(val64);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__,
+	    status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_port_delete
+ * Delete the port entry for this vpath to port number table.
+ * @vpath_handle: Vpath handle.
+ * @port_type: if 0 - Src port or 1 - Dest port
+ * @protocol: if 0 - TCP or 1 - UDP
+ * @port: port to be added for this vpath into the list
+ *
+ * Adds the given port into the list for this  vpath.
+ * see also: vxge_hal_vpath_port_add, vxge_hal_vpath_port_get and
+ * vxge_hal_vpath_port_get_next
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_port_delete(
+    vxge_hal_vpath_h vpath_handle,
+    u32 port_type,
+    u32 protocol,
+    u32 port)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", port_type = %d, "
+	    "protocol = %d, port = %d", (ptr_t) vpath_handle, port_type,
+	    protocol, port);
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(port);
+
+	if (port_type)
+		val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL;
+
+	if (protocol)
+		val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL;
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN,
+	    0,
+	    val64,
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_set - Set/configure RTS hashing.
+ * @vpath_handle: Virtual Path handle.
+ * @algorithm: Algorithm Select
+ * @hash_type: Hash Type
+ * @bucket_size: no of least significant bits to be used for hashing.
+ * @it_switch: Itable switch required
+ *
+ * Used to set/configure all RTS hashing related stuff.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_set(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rth_algoritms_t algorithm,
+    vxge_hal_rth_hash_types_t *hash_type,
+    u16 bucket_size,
+    u16 it_switch)
+{
+	u64 data0, data1;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vp = (__hal_vpath_handle_t *) vpath_handle;
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", algorithm = %d, "
+	    "hash_type = 0x"VXGE_OS_STXFMT", bucket_size = %d",
+	    (ptr_t) vpath_handle, algorithm, (ptr_t) hash_type,
+	    bucket_size);
+
+	(void) __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
+	    0,
+	    &data0,
+	    &data1);
+
+	if (algorithm == RTH_ALG_NONE) {
+
+		data0 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN;
+
+	} else {
+
+		if (it_switch) {
+
+			if (VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(
+			    data0))
+				data0 = 0;
+			else
+				data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
+
+		} else {
+			data0 &= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
+
+		}
+
+		data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
+
+		if (hash_type->hash_type_tcpipv4_en)
+			data0 |=
+			    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
+
+		if (hash_type->hash_type_ipv4_en)
+			data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
+
+		if (hash_type->hash_type_tcpipv6_en)
+			data0 |=
+			    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
+
+		if (hash_type->hash_type_ipv6_en)
+			data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
+
+		if (hash_type->hash_type_tcpipv6ex_en)
+			data0 |=
+			    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
+
+		if (hash_type->hash_type_ipv6ex_en)
+			data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
+
+	}
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
+	    0,
+	    data0,
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_get - Read RTS hashing.
+ * @vpath_handle: Virtual Path handle.
+ * @algorithm: Buffer to return Algorithm Select
+ * @hash_type: Buffer to return Hash Type
+ * @table_select: Buffer to return active Table
+ * @bucket_size: Buffer to return no of least significant bits used for hashing.
+ *
+ * Used to read all RTS hashing related stuff.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(),
+ *		vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_get(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_rth_algoritms_t *algorithm,
+    vxge_hal_rth_hash_types_t *hash_type,
+    u8 *table_select,
+    u16 *bucket_size)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", algorithm = 0x"VXGE_OS_STXFMT
+	    ", hash_type = 0x"VXGE_OS_STXFMT", "
+	    "table_select = 0x"VXGE_OS_STXFMT", "
+	    "bucket_size = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
+	    (ptr_t) algorithm, (ptr_t) hash_type,
+	    (ptr_t) table_select, (ptr_t) bucket_size);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
+	    0,
+	    &val64,
+	    NULL);
+
+	*algorithm = (vxge_hal_rth_algoritms_t)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(val64);
+
+	hash_type->hash_type_tcpipv4_en = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(val64))
+	    ? 1 : 0;
+
+	hash_type->hash_type_ipv4_en = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(val64))
+	    ? 1 : 0;
+
+	hash_type->hash_type_tcpipv6_en = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(val64))
+	    ? 1 : 0;
+
+	hash_type->hash_type_ipv6_en = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(val64))
+	    ? 1 : 0;
+
+	hash_type->hash_type_tcpipv6ex_en = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(
+	    val64)) ? 1 : 0;
+
+	hash_type->hash_type_ipv6ex_en = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(val64))
+	    ? 1 : 0;
+
+	*table_select = ((u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(val64))
+	    ? 1 : 0;
+
+	*bucket_size = (u16)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(val64);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_key_set - Configure 40byte secret for hash calc.
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @KeySize: Number of 64-bit words
+ * @Key: upto 40-byte array of 64-bit values
+ * This function configures the 40-byte secret which is used for hash
+ * calculation.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_key_set(vxge_hal_vpath_h vpath_handle,
+    u8 KeySize, u64 *Key)
+{
+	u32 i;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (Key != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", KeySize = %d"
+	    ", Key = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle, KeySize,
+	    (ptr_t) Key);
+
+	for (i = 0; i < KeySize; i++) {
+
+		status = __hal_vpath_rts_table_set(vpath_handle,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY,
+		    i,
+		    vxge_os_htonll(*Key++),
+		    0);
+
+		if (status != VXGE_HAL_OK)
+			break;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_key_get - Read 40byte secret for hash calc.
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @KeySize: Number of 64-bit words
+ * @Key: Buffer to return the key
+ * This function reads the 40-byte secret which is used for hash
+ * calculation.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *		vxge_hal_vpath_rts_rth_key_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_key_get(vxge_hal_vpath_h vpath_handle,
+    u8 KeySize, u64 *Key)
+{
+	u32 i;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (Key != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", KeySize = %d"
+	    ", Key = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle, KeySize,
+	    (ptr_t) Key);
+
+	for (i = 0; i < KeySize; i++) {
+
+		status = __hal_vpath_rts_table_get(vpath_handle,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY,
+		    i,
+		    Key++,
+		    NULL);
+
+		if (status != VXGE_HAL_OK)
+			break;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_jhash_cfg_set - Configure JHASH algorithm
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @golden_ratio: Golden ratio
+ * @init_value: Initial value
+ * This function configures JENKIN's HASH algorithm
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_jhash_cfg_set(vxge_hal_vpath_h vpath_handle,
+    u32 golden_ratio, u32 init_value)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", golden_ratio = %d"
+	    ", init_value = %d", (ptr_t) vpath_handle, golden_ratio,
+	    init_value);
+
+	status = __hal_vpath_rts_table_set(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG,
+	    0,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(
+	    golden_ratio) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(
+	    init_value),
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_jhash_cfg_get - Read JHASH algorithm
+ *
+ * @vpath_handle: Virtual Path ahandle.
+ * @golden_ratio: Buffer to return Golden ratio
+ * @init_value: Buffer to return Initial value
+ * This function reads JENKIN's HASH algorithm
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *		vxge_hal_vpath_rts_rth_jhash_cfg_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_jhash_cfg_get(vxge_hal_vpath_h vpath_handle,
+    u32 * golden_ratio, u32 *init_value)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "golden_ratio = 0x"VXGE_OS_STXFMT", init_value = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) golden_ratio, (ptr_t) init_value);
+
+	status = __hal_vpath_rts_table_get(vpath_handle,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG,
+	    0,
+	    &val64,
+	    NULL);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	*golden_ratio = (u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(
+	    val64);
+
+	*init_value = (u32)
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(
+	    val64);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_mask_set - Set/configure JHASH mask.
+ * @vpath_handle: Virtual Path ahandle.
+ * @table_size: Size of the mask table
+ * @hash_mask_ipv6sa: IPv6SA Hash Mask
+ * @hash_mask_ipv6da: IPv6DA Hash Mask
+ * @hash_mask_ipv4sa: IPv4SA Hash Mask
+ * @hash_mask_ipv4da: IPv4DA Hash Mask
+ * @hash_mask_l4sp: L4SP Hash Mask
+ * @hash_mask_l4dp: L4DP Hash Mask
+ *
+ * Used to set/configure indirection table.
+ * It enables the required no of entries in the IT.
+ * It adds entries to the IT.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_mask_set(vxge_hal_vpath_h vpath_handle,
+    u32 table_size,
+    u32 *hash_mask_ipv6sa,
+    u32 *hash_mask_ipv6da,
+    u32 *hash_mask_ipv4sa,
+    u32 *hash_mask_ipv4da,
+    u32 *hash_mask_l4sp,
+    u32 *hash_mask_l4dp)
+{
+	u32 i;
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (hash_mask_ipv6sa != NULL) &&
+	    (hash_mask_ipv6da != NULL) && (hash_mask_ipv4sa != NULL) &&
+	    (hash_mask_ipv4da != NULL) && (hash_mask_l4sp != NULL) &&
+	    (hash_mask_l4dp != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "table_size = %d, hash_mask_ipv6sa = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_ipv6da = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_ipv4sa = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_ipv4da = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_l4sp = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_l4dp = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, table_size, (ptr_t) hash_mask_ipv6sa,
+	    (ptr_t) hash_mask_ipv6da, (ptr_t) hash_mask_ipv4sa,
+	    (ptr_t) hash_mask_ipv4da, (ptr_t) hash_mask_l4sp,
+	    (ptr_t) hash_mask_l4dp);
+
+	for (i = 0; i < table_size; i++) {
+
+		val64 =
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(
+		    *hash_mask_ipv6sa++) |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(
+		    *hash_mask_ipv6da++) |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(
+		    *hash_mask_ipv4sa++) |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(
+		    *hash_mask_ipv4da++) |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(
+		    *hash_mask_l4sp++) |
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(
+		    *hash_mask_l4dp++);
+
+		status = __hal_vpath_rts_table_set(vpath_handle,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK,
+		    i,
+		    val64,
+		    0);
+
+		if (status != VXGE_HAL_OK)
+			break;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_mask_get - Read JHASH mask.
+ * @vpath_handle: Virtual Path ahandle.
+ * @table_size: Size of the mask table
+ * @hash_mask_ipv6sa: Buffer to return IPv6SA Hash Mask
+ * @hash_mask_ipv6da: Buffer to return IPv6DA Hash Mask
+ * @hash_mask_ipv4sa: Buffer to return IPv4SA Hash Mask
+ * @hash_mask_ipv4da: Buffer to return IPv4DA Hash Mask
+ * @hash_mask_l4sp: Buffer to return L4SP Hash Mask
+ * @hash_mask_l4dp: Buffer to return L4DP Hash Mask
+ *
+ * Used to read rth mask.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *	  vxge_hal_vpath_rts_rth_mask_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_mask_get(vxge_hal_vpath_h vpath_handle,
+    u32 table_size,
+    u32 *hash_mask_ipv6sa,
+    u32 *hash_mask_ipv6da,
+    u32 *hash_mask_ipv4sa,
+    u32 *hash_mask_ipv4da,
+    u32 *hash_mask_l4sp,
+    u32 *hash_mask_l4dp)
+{
+	u32 i;
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (hash_mask_ipv6sa != NULL) &&
+	    (hash_mask_ipv6da != NULL) && (hash_mask_ipv4sa != NULL) &&
+	    (hash_mask_ipv4da != NULL) && (hash_mask_l4sp != NULL) &&
+	    (hash_mask_l4dp != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "table_size = %d, hash_mask_ipv6sa = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_ipv6da = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_ipv4sa = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_ipv4da = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_l4sp = 0x"VXGE_OS_STXFMT
+	    ", hash_mask_l4dp = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, table_size, (ptr_t) hash_mask_ipv6sa,
+	    (ptr_t) hash_mask_ipv6da, (ptr_t) hash_mask_ipv4sa,
+	    (ptr_t) hash_mask_ipv4da, (ptr_t) hash_mask_l4sp,
+	    (ptr_t) hash_mask_l4dp);
+
+	for (i = 0; i < table_size; i++) {
+
+		status = __hal_vpath_rts_table_get(vpath_handle,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+		    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK,
+		    i,
+		    &val64,
+		    NULL);
+
+		if (status != VXGE_HAL_OK)
+			break;
+
+		*hash_mask_ipv6sa++ = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(
+		    val64);
+
+		*hash_mask_ipv6da++ = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(
+		    val64);
+
+		*hash_mask_ipv4sa++ = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(
+		    val64);
+
+		*hash_mask_ipv4da++ = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(
+		    val64);
+
+		*hash_mask_l4sp++ = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val64);
+
+		*hash_mask_l4dp++ = (u32)
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val64);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
+ * @vpath_handles: Virtual Path handles.
+ * @vpath_count: Number of vpath handles passed in vpath_handles
+ * @itable: Pointer to indirection table
+ * @itable_size: Number of entries in itable
+ *
+ * Used to set/configure indirection table.
+ * It enables the required no of entries in the IT.
+ * It adds entries to the IT.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_itable_set(vxge_hal_vpath_h *vpath_handles,
+    u32 vpath_count,
+    u8 *itable,
+    u32 itable_size)
+{
+	u32 i, j, k, l, items[4];
+	u64 data0;
+	u64 data1;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handles[0];
+
+	vxge_assert((vpath_handles != NULL) && (itable != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", vpath_count = %d, "
+	    "itable = 0x"VXGE_OS_STXFMT", itable_size = %d",
+	    (ptr_t) vpath_handles, vpath_count, (ptr_t) itable, itable_size);
+
+	if (hldev->header.config.rth_it_type == VXGE_HAL_RTH_IT_TYPE_SOLO_IT) {
+
+		for (j = 0; j < itable_size; j++) {
+
+			data1 = 0;
+
+			data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
+			    itable[j]);
+
+			status = __hal_vpath_rts_table_set(vpath_handles[0],
+			    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+			    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
+			    j,
+			    data0,
+			    data1);
+
+			if (status != VXGE_HAL_OK) {
+				vxge_hal_trace_log_vpath(
+				    "<== %s:%s:%d Result: %d",
+				    __FILE__, __func__, __LINE__,
+				    status);
+
+				return (status);
+			}
+		}
+
+		for (j = 0; j < itable_size; j++) {
+
+			data1 = 0;
+
+			data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
+			    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(itable[j]);
+
+			status = __hal_vpath_rts_table_set(vpath_handles[itable[j]],
+			    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+			    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
+			    j, data0, data1);
+
+			if (status != VXGE_HAL_OK) {
+				vxge_hal_trace_log_vpath(
+				    "<== %s:%s:%d Result: %d",
+				    __FILE__, __func__, __LINE__,
+				    status);
+				return (status);
+			}
+		}
+
+	} else {
+		for (i = 0; i < vpath_count; i++) {
+
+			for (k = 0, j = 0; k < itable_size; k++) {
+
+				if (itable[k] != i)
+					continue;
+
+				for (l = j; l < 4; l++)
+					items[l] = k;
+
+				if ((j++ == 3) || (k == (itable_size - 1))) {
+
+					data0 =
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(
+					    items[0]) |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
+					    itable[items[0]]) |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(
+					    items[1]) |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
+					    itable[items[1]]);
+
+					data1 =
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(
+					    items[2]) |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
+					    itable[items[2]]) |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(
+					    items[3]) |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
+					    itable[items[3]]);
+
+					status =
+					    __hal_vpath_rts_table_set(vpath_handles[i],
+					    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+					    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT,
+					    0,
+					    data0,
+					    data1);
+
+					if (status != VXGE_HAL_OK) {
+						vxge_hal_trace_log_vpath(
+						    "<== %s:%s:%d  Result: %d",
+						    __FILE__, __func__,
+						    __LINE__, status);
+
+						return (status);
+					}
+
+					j = 0;
+				}
+			}
+		}
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_itable_get - Read indirection table(IT).
+ * @vpath_handles: Virtual Path handles.
+ * @vpath_count: Number of vpath handles passed in vpath_handles
+ * @itable: Pointer to the buffer to return indirection table
+ * @itable_size: pointer to buffer to return Number of entries in itable
+ *
+ * Used to read indirection table.
+ *
+ * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(),
+ *		vxge_hal_vpath_rts_rth_itable_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_itable_get(vxge_hal_vpath_h *vpath_handles,
+    u32 vpath_count,
+    u8 *itable,
+    u32 itable_size)
+{
+	u32 i, j;
+	u64 data0;
+	u64 data1;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handles[0];
+
+	vxge_assert((vpath_handles != NULL) && (itable != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", vpath_count = %d, "
+	    "itable = 0x"VXGE_OS_STXFMT", itable_size = %d",
+	    (ptr_t) vpath_handles, vpath_count, (ptr_t) itable, itable_size);
+
+	if (hldev->header.config.rth_it_type == VXGE_HAL_RTH_IT_TYPE_SOLO_IT) {
+
+		for (i = 0; i < vpath_count; i++) {
+
+			for (j = 0; j < itable_size; j++) {
+
+				status = __hal_vpath_rts_table_get(vpath_handles[i],
+				    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+				    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
+				    j,
+				    &data0,
+				    &data1);
+
+				if (status != VXGE_HAL_OK) {
+					vxge_hal_trace_log_vpath(
+					    "<== %s:%s:%d Result: %d",
+					    __FILE__, __func__, __LINE__,
+					    status);
+
+					return (status);
+				}
+
+				if ((u8) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(data0)) {
+					itable[j] = (u8) i;
+				}
+			}
+		}
+	} else {
+
+		for (i = 0; i < vpath_count; i++) {
+
+			for (j = 0; j < itable_size; ) {
+
+				data0 = 0;
+				data1 = 0;
+
+				if (j < itable_size)
+					data0 =
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j);
+
+				if (j + 1 < itable_size)
+					data0 |= VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j + 1);
+
+				if (j + 2 < itable_size)
+					data1 = VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j + 2);
+
+				if (j + 3 < itable_size)
+					data1 |= VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j + 3);
+
+				status = __hal_vpath_rts_table_get(
+				    vpath_handles[i],
+				    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+				    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT,
+				    0, &data0, &data1);
+
+				if (status != VXGE_HAL_OK) {
+					vxge_hal_trace_log_vpath(
+					    "<== %s:%s:%d Result: %d",
+					    __FILE__, __func__, __LINE__,
+					    status);
+
+					return (status);
+				}
+
+				if (j < itable_size) {
+					if ((u8)
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(data0)) {
+						itable[j] = (u8) i;
+					}
+
+					j++;
+				}
+
+				if (j < itable_size) {
+					if ((u8)
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(data0)) {
+						itable[j] = (u8) i;
+					}
+					j++;
+				}
+
+				if (j < itable_size) {
+					if ((u8)
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(data1)) {
+						itable[j] = (u8) i;
+					}
+					j++;
+				}
+
+				if (j < itable_size) {
+					if ((u8)
+					    VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(data1)) {
+						itable[j] = (u8) i;
+					}
+					j++;
+				}
+			}
+		}
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_rts_rth_clr - Clear RTS hashing.
+ * @vpath_handles: Virtual Path handles.
+ * @vpath_count: Number of vpath handles passed in vpath_handles
+ *
+ * This function is used to clear all RTS hashing related stuff.
+ *
+ * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_itable_set().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rts_rth_clr(
+    vxge_hal_vpath_h *vpath_handles,
+    u32 vpath_count)
+{
+	u64 data0, data1;
+	u32 i, j;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath_handles != NULL);
+
+	vp = (__hal_vpath_handle_t *) vpath_handles[0];
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handles = 0x"VXGE_OS_STXFMT", vpath_count = %d",
+	    (ptr_t) vpath_handles, vpath_count);
+
+	if (hldev->header.config.rth_it_type == VXGE_HAL_RTH_IT_TYPE_SOLO_IT) {
+
+		for (j = 0; j < VXGE_HAL_MAX_ITABLE_ENTRIES; j++) {
+
+			data0 = 0;
+			data1 = 0;
+
+			status = __hal_vpath_rts_table_set(vpath_handles[0],
+			    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+			    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT,
+			    j,
+			    data0,
+			    data1);
+
+			if (status != VXGE_HAL_OK) {
+				vxge_hal_trace_log_vpath(
+				    "<== %s:%s:%d Result: %d",
+				    __FILE__, __func__, __LINE__,
+				    status);
+
+				return (status);
+			}
+		}
+	} else {
+		for (i = 0; i < vpath_count; i++) {
+
+			for (j = 0; j < VXGE_HAL_MAX_ITABLE_ENTRIES; j += 4) {
+
+				data0 =
+				    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j) |
+				    VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j + 1);
+
+				data1 =
+				    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j + 2) |
+				    VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j + 3);
+
+				status = __hal_vpath_rts_table_set(vpath_handles[i],
+				    VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
+				    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT,
+				    0,
+				    data0,
+				    data1);
+
+				if (status != VXGE_HAL_OK) {
+					vxge_hal_trace_log_vpath(
+					    "<== %s:%s:%d Result: %d",
+					    __FILE__, __func__, __LINE__,
+					    status);
+					return (status);
+				}
+			}
+		}
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_promisc_enable - Enable promiscuous mode.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable promiscuous mode of X3100 operation.
+ *
+ * See also: vxge_hal_vpath_promisc_disable().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_promisc_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->promisc_en == VXGE_HAL_VP_PROMISC_ENABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
+	    VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
+	    VXGE_HAL_RXMAC_VCFG0_BCAST_EN |
+	    VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->promisc_en = VXGE_HAL_VP_PROMISC_ENABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_promisc_disable - Disable promiscuous mode.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable promiscuous mode of X3100 operation.
+ *
+ * See also: vxge_hal_vpath_promisc_enable().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_promisc_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->promisc_en == VXGE_HAL_VP_PROMISC_DISABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	if (vpath->vp_config->rpa_ucast_all_addr_en ==
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE) {
+		val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+	}
+
+	if (vpath->vp_config->rpa_mcast_all_addr_en ==
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE) {
+		val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+	}
+
+	if (vpath->vp_config->rpa_bcast_en ==
+	    VXGE_HAL_VPATH_RPA_BCAST_DISABLE) {
+		val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+	}
+
+	if (vpath->vp_config->rpa_all_vid_en ==
+	    VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE) {
+		val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+	}
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->promisc_en = VXGE_HAL_VP_PROMISC_DISABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_bcast_enable - Enable broadcast
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable receiving broadcasts.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_bcast_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_HANDLE);
+
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_bcast_en ==
+	    VXGE_HAL_VPATH_RPA_BCAST_ENABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_bcast_en = VXGE_HAL_VPATH_RPA_BCAST_ENABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_bcast_disable - Disable broadcast
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable receiving broadcasts.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_bcast_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_bcast_en ==
+	    VXGE_HAL_VPATH_RPA_BCAST_DISABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_bcast_en = VXGE_HAL_VPATH_RPA_BCAST_DISABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_mcast_enable - Enable multicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100 multicast addresses.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mcast_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_mcast_all_addr_en ==
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_mcast_all_addr_en =
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_mcast_disable - Disable  multicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100 multicast addresses.
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to disable mcast
+ * feature within the time(timeout).
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mcast_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_mcast_all_addr_en ==
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_mcast_all_addr_en =
+	    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_ucast_enable - Enable unicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100 unicast addresses.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_ucast_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_ucast_all_addr_en ==
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_ucast_all_addr_en =
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_ucast_disable - Disable  unicast addresses.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100 unicast addresses.
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to disable mcast
+ * feature within the time(timeout).
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_ucast_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_ucast_all_addr_en ==
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_ucast_all_addr_en =
+	    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_all_vid_enable - Enable all Vlan Ids.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100 vlan ids.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_all_vid_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_all_vid_en ==
+	    VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_all_vid_en = VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_all_vid_disable - Disable all Vlan Ids.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100  vlan ids.
+ * Returns: VXGE_HAL_OK - success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_all_vid_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_all_vid_en ==
+	    VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+
+	vxge_os_pio_mem_write64(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_all_vid_en = VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_strip_vlan_tag_enable - Enable strip vlan tag.
+ * @vpath_handle: Vpath handle.
+ *
+ * Enable X3100  strip vlan tag.
+ * Returns: VXGE_HAL_OK on success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_strip_vlan_tag_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_strip_vlan_tag ==
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->xmac_rpa_vcfg);
+
+	val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->xmac_rpa_vcfg);
+
+	vpath->vp_config->rpa_strip_vlan_tag =
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_strip_vlan_tag_disable - Disable strip vlan tag.
+ * @vpath_handle: Vpath handle.
+ *
+ * Disable X3100  strip vlan tag.
+ * Returns: VXGE_HAL_OK - success.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_strip_vlan_tag_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	if (vpath->vp_config->rpa_strip_vlan_tag ==
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_OK);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->xmac_rpa_vcfg);
+
+	val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->xmac_rpa_vcfg);
+
+	vpath->vp_config->rpa_strip_vlan_tag =
+	    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_tpa_set - Set tpa parameters.
+ * @vpath_handle: Virtual Path ahandle.
+ * @params: vxge_hal_vpath_tpa_params {} structure with parameters
+ *
+ * The function	sets the tpa parametrs for the vpath.
+ *
+ * See also: vxge_hal_vpath_tpa_params {}
+ */
+vxge_hal_status_e
+vxge_hal_vpath_tpa_set(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_tpa_params *params)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert((vpath_handle != NULL) && (params != NULL));
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", params = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) params);
+
+	if (vpath->fifoh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->tpa_cfg);
+
+	if (params->tpa_ignore_frame_error != VXGE_HAL_DEFAULT_32) {
+		if (params->tpa_ignore_frame_error)
+			val64 |= VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
+		else
+			val64 &= ~VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
+	}
+
+	if (params->tpa_ipv6_keep_searching != VXGE_HAL_DEFAULT_32) {
+		if (params->tpa_ipv6_keep_searching)
+			val64 &= ~VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
+		else
+			val64 |= VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
+	}
+
+	if (params->tpa_l4_pshdr_present != VXGE_HAL_DEFAULT_32) {
+		if (params->tpa_l4_pshdr_present)
+			val64 |= VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
+		else
+			val64 &= ~VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
+	}
+
+	if (params->tpa_support_mobile_ipv6_hdrs != VXGE_HAL_DEFAULT_32) {
+		if (params->tpa_support_mobile_ipv6_hdrs)
+			val64 |= VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
+		else
+			val64 &= ~VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tpa_cfg);
+
+	vpath->vp_config->tpa_ignore_frame_error =
+	    params->tpa_ignore_frame_error;
+	vpath->vp_config->tpa_l4_pshdr_present =
+	    params->tpa_l4_pshdr_present;
+	vpath->vp_config->tpa_support_mobile_ipv6_hdrs =
+	    params->tpa_support_mobile_ipv6_hdrs;
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->tx_protocol_assist_cfg);
+
+	if (params->tpa_lsov2_en != VXGE_HAL_DEFAULT_32) {
+		if (params->tpa_lsov2_en)
+			val64 |= VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
+		else
+			val64 &= ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
+	}
+
+	if (params->tpa_ipv6_keep_searching != VXGE_HAL_DEFAULT_32) {
+		if (params->tpa_ipv6_keep_searching)
+			val64 |=
+			    VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
+		else
+			val64 &=
+			    ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tx_protocol_assist_cfg);
+
+	vpath->vp_config->tpa_lsov2_en = params->tpa_lsov2_en;
+	vpath->vp_config->tpa_ipv6_keep_searching =
+	    params->tpa_ipv6_keep_searching;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_rpa_set - Set rpa parameters.
+ * @vpath_handle: Virtual Path ahandle.
+ * @params: vxge_hal_vpath_rpa_params {} structure with parameters
+ *
+ * The function	sets the rpa parametrs for the vpath.
+ *
+ * See also: vxge_hal_vpath_rpa_params {}
+ */
+vxge_hal_status_e
+vxge_hal_vpath_rpa_set(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_rpa_params *params)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert((vpath_handle != NULL) && (params != NULL));
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", params = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) params);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->xmac_rpa_vcfg);
+
+	if (params->rpa_ipv4_tcp_incl_ph != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_ipv4_tcp_incl_ph)
+			val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
+		else
+			val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
+	}
+
+	if (params->rpa_ipv6_tcp_incl_ph != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_ipv6_tcp_incl_ph)
+			val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
+		else
+			val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
+	}
+
+	if (params->rpa_ipv4_udp_incl_ph != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_ipv4_udp_incl_ph)
+			val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
+		else
+			val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
+	}
+
+	if (params->rpa_ipv6_udp_incl_ph != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_ipv6_udp_incl_ph)
+			val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
+		else
+			val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
+	}
+
+	if (params->rpa_l4_incl_cf != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_l4_incl_cf)
+			val64 |= VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
+		else
+			val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
+	}
+
+	if (params->rpa_strip_vlan_tag != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_strip_vlan_tag)
+			val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
+		else
+			val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->xmac_rpa_vcfg);
+
+	vpath->vp_config->rpa_ipv4_tcp_incl_ph = params->rpa_ipv4_tcp_incl_ph;
+	vpath->vp_config->rpa_ipv6_tcp_incl_ph = params->rpa_ipv6_tcp_incl_ph;
+	vpath->vp_config->rpa_ipv4_udp_incl_ph = params->rpa_ipv4_udp_incl_ph;
+	vpath->vp_config->rpa_ipv6_udp_incl_ph = params->rpa_ipv6_udp_incl_ph;
+	vpath->vp_config->rpa_l4_incl_cf = params->rpa_l4_incl_cf;
+	vpath->vp_config->rpa_strip_vlan_tag = params->rpa_strip_vlan_tag;
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	if (params->rpa_ucast_all_addr_en != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_ucast_all_addr_en)
+			val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+	}
+
+	if (params->rpa_mcast_all_addr_en != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_mcast_all_addr_en)
+			val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+	}
+
+	if (params->rpa_bcast_en != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_bcast_en)
+			val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+	}
+
+	if (params->rpa_all_vid_en != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_all_vid_en)
+			val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+		else
+			val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rxmac_vcfg0);
+
+	vpath->vp_config->rpa_ucast_all_addr_en = params->rpa_ucast_all_addr_en;
+	vpath->vp_config->rpa_mcast_all_addr_en = params->rpa_mcast_all_addr_en;
+	vpath->vp_config->rpa_bcast_en = params->rpa_bcast_en;
+	vpath->vp_config->rpa_all_vid_en = params->rpa_all_vid_en;
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->fau_rpa_vcfg);
+
+	if (params->rpa_l4_comp_csum != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_l4_comp_csum)
+			val64 |= VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
+		else
+			val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
+	}
+
+	if (params->rpa_l3_incl_cf != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_l3_incl_cf)
+			val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
+		else
+			val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
+	}
+
+	if (params->rpa_l3_comp_csum != VXGE_HAL_DEFAULT_32) {
+		if (params->rpa_l3_comp_csum)
+			val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
+		else
+			val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->fau_rpa_vcfg);
+
+	vpath->vp_config->rpa_l4_comp_csum = params->rpa_l4_comp_csum;
+	vpath->vp_config->rpa_l3_incl_cf = params->rpa_l3_incl_cf;
+	vpath->vp_config->rpa_l3_comp_csum = params->rpa_l3_comp_csum;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_intr_enable - Enable vpath interrupts.
+ * @vpath: Virtual Path.
+ * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to enable.
+ *
+ * Enable vpath interrupts. The function is to be executed the last in
+ * vpath initialization sequence.
+ *
+ * See also: __hal_vpath_intr_disable()
+ */
+vxge_hal_status_e
+__hal_vpath_intr_enable(__hal_virtualpath_t *vpath)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->kdfcctl_errors_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->general_errors_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->pci_config_errors_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->srpcim_to_vpath_alarm_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->vpath_ppif_int_status);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->srpcim_msg_to_vpath_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->vpath_pcipif_int_status);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->prc_alarm_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->wrdma_alarm_status);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->asic_ntwk_vp_err_reg);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->xgmac_vp_int_status);
+
+	vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_general_int_status);
+
+	/* Unmask the individual interrupts. */
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->kdfcctl_errors_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->general_errors_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->pci_config_errors_mask);
+
+	if (hldev->first_vp_id != vpath->vp_id) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) VXGE_HAL_INTR_MASK_ALL,
+		    &vpath->vp_reg->mrpcim_to_vpath_alarm_mask);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) VXGE_HAL_INTR_MASK_ALL,
+		    &vpath->vp_reg->srpcim_to_vpath_alarm_mask);
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    0,
+		    &vpath->vp_reg->mrpcim_to_vpath_alarm_mask);
+
+		if (hldev->access_rights &
+		    VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM) {
+			vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+			    hldev->header.regh0,
+			    0,
+			    &vpath->vp_reg->srpcim_to_vpath_alarm_mask);
+		}
+	}
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->vpath_ppif_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->srpcim_msg_to_vpath_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->vpath_pcipif_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP, 0),
+	    &vpath->vp_reg->prc_alarm_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->wrdma_alarm_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->xgmac_vp_int_mask);
+
+	if (hldev->first_vp_id != vpath->vp_id) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) VXGE_HAL_INTR_MASK_ALL,
+		    &vpath->vp_reg->asic_ntwk_vp_err_mask);
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32((
+		    VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_FAULT |
+		    VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_OK), 0),
+		    &vpath->vp_reg->asic_ntwk_vp_err_mask);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->tim_int_en);
+
+	/* val64 |= VXGE_HAL_TIM_SET_INT_EN_VP(1 << (16 - vpath->vp_id)); */
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->tim_set_int_en);
+
+	vxge_hal_pio_mem_write32_upper(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->vpath_general_int_mask);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+
+}
+
+/*
+ * vxge_hal_vpath_intr_enable - Enable vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to enable.
+ *
+ * Enable vpath interrupts. The function is to be executed the last in
+ * vpath initialization sequence.
+ *
+ * See also: vxge_hal_vpath_intr_disable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_intr_enable(vxge_hal_vpath_h vpath_handle)
+{
+	vxge_hal_status_e status;
+
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vp = (__hal_vpath_handle_t *) vpath_handle;
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_intr_enable((__hal_virtualpath_t *) vp->vpath);
+
+	vxge_hal_vpath_unmask_all(vpath_handle);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+
+}
+
+/*
+ * __hal_vpath_intr_disable - Disable vpath interrupts.
+ * @vpath: Virtual Path.
+ * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to enable.
+ *
+ * Disable vpath interrupts. The function is to be executed the last in
+ * vpath initialization sequence.
+ *
+ * See also: __hal_vpath_intr_enable()
+ */
+vxge_hal_status_e
+__hal_vpath_intr_disable(__hal_virtualpath_t *vpath)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->vpath_general_int_mask);
+
+	val64 = VXGE_HAL_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id));
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->tim_clr_int_en);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->kdfcctl_errors_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->general_errors_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->pci_config_errors_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->mrpcim_to_vpath_alarm_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->srpcim_to_vpath_alarm_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->vpath_ppif_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->srpcim_msg_to_vpath_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->vpath_pcipif_int_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->prc_alarm_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->wrdma_alarm_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->asic_ntwk_vp_err_mask);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) VXGE_HAL_INTR_MASK_ALL,
+	    &vpath->vp_reg->xgmac_vp_int_mask);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+
+}
+/*
+ * vxge_hal_vpath_intr_disable - Disable vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying
+ *	  the type(s) of interrupts to disable.
+ *
+ * Disable vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_intr_enable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_intr_disable(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	vxge_hal_vpath_mask_all(vpath_handle);
+
+	(void) __hal_vpath_intr_disable(vpath);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_mask_all - Mask all vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	all vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_all()
+ */
+void
+vxge_hal_vpath_mask_all(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vp = (__hal_vpath_handle_t *) vpath_handle;
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	val64 = VXGE_HAL_VPATH_GENERAL_INT_MASK_PIC_INT |
+	    VXGE_HAL_VPATH_GENERAL_INT_MASK_PCI_INT |
+	    VXGE_HAL_VPATH_GENERAL_INT_MASK_WRDMA_INT |
+	    VXGE_HAL_VPATH_GENERAL_INT_MASK_XMAC_INT;
+
+	vxge_hal_pio_mem_write32_upper(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vp->vpath->vp_reg->vpath_general_int_mask);
+
+	if (vp->vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 |= vBIT(0xf, (vp->vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(0xf), 0),
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_unmask_all - Unmask all vpath interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask all vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_all()
+ */
+void
+vxge_hal_vpath_unmask_all(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vp == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	vxge_hal_pio_mem_write32_upper(
+	    hldev->header.pdev,
+	    hldev->header.regh0,
+	    0,
+	    &vp->vpath->vp_reg->vpath_general_int_mask);
+
+	if (vp->vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 &= ~(vBIT(0xf, (vp->vpath->vp_id * 4), 4));
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    0,
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * __hal_vpath_link_state_test - Test for the link state.
+ * @vpath: Virtual Path.
+ *
+ * Test link state.
+ * Returns: link state.
+ */
+vxge_hal_device_link_state_e
+__hal_vpath_link_state_test(__hal_virtualpath_t *vpath)
+{
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath != NULL);
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK,
+	    &vpath->vp_reg->asic_ntwk_vp_ctrl);
+
+	(void) vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->asic_ntwk_vp_ctrl,
+	    0,
+	    VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK,
+	    hldev->header.config.device_poll_millis);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (hldev->header.link_state);
+}
+
+/*
+ * __hal_vpath_link_state_poll - Poll for the link state.
+ * @vpath: Virtual Path.
+ *
+ * Get link state.
+ * Returns: link state.
+ */
+vxge_hal_device_link_state_e
+__hal_vpath_link_state_poll(__hal_virtualpath_t *vpath)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_LINK_NONE);
+		return (VXGE_HAL_LINK_NONE);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
+
+	if (val64 & VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) {
+
+		(void) __hal_device_handle_link_up_ind(vpath->hldev);
+
+		if (val64 &
+		    VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE) {
+			VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
+			    VXGE_HAL_DATA_RATE_10G);
+
+		} else {
+			VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
+			    VXGE_HAL_DATA_RATE_1G);
+
+		}
+	} else {
+		(void) __hal_device_handle_link_down_ind(vpath->hldev);
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (vpath->hldev->header.link_state);
+}
+
+/*
+ * __hal_vpath_data_rate_poll - Poll for the data rate.
+ * @vpath: Virtual Path.
+ *
+ * Get data rate.
+ * Returns: data rate.
+ */
+vxge_hal_device_data_rate_e
+__hal_vpath_data_rate_poll(
+    __hal_virtualpath_t *vpath)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath == NULL) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_DATA_RATE_UNKNOWN);
+		return (VXGE_HAL_DATA_RATE_UNKNOWN);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
+
+	if (val64 &
+	    VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+
+		return (VXGE_HAL_DATA_RATE_10G);
+
+	} else {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+		    __FILE__, __func__, __LINE__);
+
+		return (VXGE_HAL_DATA_RATE_1G);
+
+	}
+}
+
+/*
+ * __hal_vpath_alarm_process - Process Alarms.
+ * @vpath: Virtual Path.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Process vpath alarms.
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_alarm_process(__hal_virtualpath_t *vpath, u32 skip_alarms)
+{
+	u64 val64;
+	u64 alarm_status;
+	u64 pic_status = 0;
+	u64 pif_status;
+	u64 wrdma_status;
+	u64 xgmac_status;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	alarm_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_general_int_status);
+
+	vxge_hal_info_log_vpath_irq(
+	    "alarm_status = 0x"VXGE_OS_STXFMT, (ptr_t) alarm_status);
+
+	if (vxge_os_unlikely(!alarm_status)) {
+		status = VXGE_HAL_ERR_WRONG_IRQ;
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT) {
+
+		pic_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->vpath_ppif_int_status);
+
+		vxge_hal_info_log_vpath_irq(
+		    "pic_status = 0x"VXGE_OS_STXFMT, (ptr_t) pic_status);
+
+		if (pic_status &
+		    VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->general_errors_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "general_errors_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+			if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET) {
+
+				vpath->sw_stats->error_stats.ini_serr_det++;
+				vxge_hal_info_log_vpath_irq("%s:"
+				    "VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET",
+				    __func__);
+
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_SERR);
+
+				if (!skip_alarms) {
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET,
+					    &vpath->vp_reg->general_errors_reg);
+				}
+
+				vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
+				    Result = 0", __FILE__, __func__, __LINE__);
+
+				return (VXGE_HAL_ERR_EVENT_SERR);
+			}
+		}
+
+		if (pic_status & VXGE_HAL_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_INT) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->pci_config_errors_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "pci_config_errors_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			if (val64 &
+			    VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR) {
+				vpath->sw_stats->error_stats.pci_config_status_err++;
+				vxge_hal_info_log_vpath_irq("%s: \
+				    VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR",
+				    __func__);
+			}
+
+			if (val64 & VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR) {
+				vpath->sw_stats->error_stats.pci_config_uncor_err++;
+				vxge_hal_info_log_vpath_irq("%s: \
+				    VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR",
+				    __func__);
+			}
+
+			if (val64 & VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR) {
+				vpath->sw_stats->error_stats.pci_config_cor_err++;
+				vxge_hal_info_log_vpath_irq("%s: \
+				    VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR",
+				    __func__);
+			}
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0, VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->pci_config_errors_reg);
+		}
+
+		if (pic_status &
+		    VXGE_HAL_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "mrpcim_to_vpath_alarm_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			if (val64 &
+			    VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM) {
+
+				vpath->sw_stats->error_stats.mrpcim_to_vpath_alarms++;
+				hldev->stats.sw_dev_err_stats.mrpcim_alarms++;
+				vxge_hal_info_log_vpath_irq(
+				    "%s:VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM",
+				    __func__);
+
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_MRPCIM_CRITICAL);
+
+				if (!skip_alarms)
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM,
+					    &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
+					return (VXGE_HAL_ERR_EVENT_MRPCIM_CRITICAL);
+			}
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->mrpcim_to_vpath_alarm_reg);
+		}
+
+		if (pic_status &
+		    VXGE_HAL_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->srpcim_to_vpath_alarm_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "srpcim_to_vpath_alarm_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			vpath->sw_stats->error_stats.srpcim_to_vpath_alarms++;
+			hldev->stats.sw_dev_err_stats.srpcim_alarms++;
+
+			vxge_hal_info_log_vpath_irq(
+			    "%s:VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_GET_ALARM",
+			    __func__);
+
+			status = vxge_hal_srpcim_alarm_process(
+			    (vxge_hal_device_h) hldev, skip_alarms);
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->srpcim_to_vpath_alarm_reg);
+
+			if (status == VXGE_HAL_ERR_EVENT_SRPCIM_CRITICAL)
+				return (status);
+		}
+	}
+
+	if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
+
+		wrdma_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->wrdma_alarm_status);
+
+		vxge_hal_info_log_vpath_irq(
+		    "wrdma_alarm_status = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) wrdma_status);
+
+		if (wrdma_status &
+		    VXGE_HAL_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->prc_alarm_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "prc_alarm_reg = 0x"VXGE_OS_STXFMT, (ptr_t) val64);
+
+			if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP) {
+				vpath->sw_stats->error_stats.prc_ring_bumps++;
+				vxge_hal_info_log_vpath_irq(
+				    "%s:VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP",
+				    __func__);
+			}
+
+			if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) {
+				vpath->sw_stats->error_stats.prc_rxdcm_sc_err++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR",
+				    __func__);
+				__hal_device_handle_error(hldev,
+				    vpath->vp_id,
+				    VXGE_HAL_EVENT_CRITICAL);
+
+				if (!skip_alarms) {
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR,
+					    &vpath->vp_reg->prc_alarm_reg);
+				}
+
+				vxge_hal_trace_log_vpath_irq(
+				    "<== %s:%s:%d Result = %d",
+				    __FILE__, __func__, __LINE__,
+				    VXGE_HAL_ERR_EVENT_CRITICAL);
+
+				return (VXGE_HAL_ERR_EVENT_CRITICAL);
+			}
+
+			if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT) {
+				vpath->sw_stats->error_stats.prc_rxdcm_sc_abort++;
+				vxge_hal_info_log_vpath_irq("%s: \
+				    VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT",
+				    __func__);
+
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_CRITICAL);
+
+				if (!skip_alarms)
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT,
+					    &vpath->vp_reg->prc_alarm_reg);
+
+				vxge_hal_trace_log_vpath_irq(
+				    "<== %s:%s:%d Result = %d",
+				    __FILE__, __func__, __LINE__,
+				    VXGE_HAL_ERR_EVENT_CRITICAL);
+
+				return (VXGE_HAL_ERR_EVENT_CRITICAL);
+			}
+
+			if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR) {
+				vpath->sw_stats->error_stats.prc_quanta_size_err++;
+				vxge_hal_info_log_vpath_irq("%s: \
+				    VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR",
+				    __func__);
+			}
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0, VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->prc_alarm_reg);
+			}
+	}
+
+	if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT) {
+
+		if (pic_status &
+		    VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->general_errors_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "general_errors_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			if (val64 &
+			    VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) {
+
+				vpath->sw_stats->error_stats.dblgen_fifo0_overflow++;
+				vxge_hal_info_log_vpath_irq(
+				    "%s:"
+				    "VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW",
+				    __func__);
+
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_KDFCCTL);
+
+				if (!skip_alarms) {
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW,
+					    &vpath->vp_reg->general_errors_reg);
+				}
+
+				vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
+				    Result = %d",
+				    __FILE__, __func__, __LINE__,
+				    VXGE_HAL_ERR_EVENT_KDFCCTL);
+				return (VXGE_HAL_ERR_EVENT_KDFCCTL);
+			}
+
+			if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW) {
+				vpath->sw_stats->error_stats.dblgen_fifo1_overflow++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW",
+				    __func__);
+
+			}
+
+			if (val64 &
+			    VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW) {
+				vpath->sw_stats->error_stats.dblgen_fifo2_overflow++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW",
+				    __func__);
+			}
+
+			if (val64 &
+			    VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) {
+				vpath->sw_stats->error_stats.statsb_pif_chain_error++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR",
+				    __func__);
+			}
+
+			if (val64 &
+			    VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT) {
+				vpath->sw_stats->error_stats.statsb_drop_timeout++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT",
+				    __func__);
+			}
+
+			if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) {
+				vpath->sw_stats->error_stats.target_illegal_access++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS",
+				    __func__);
+			}
+
+			if (!skip_alarms)
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->general_errors_reg);
+		}
+
+		if (pic_status &
+		    VXGE_HAL_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_INT) {
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->kdfcctl_errors_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "kdfcctl_errors_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR",
+				    __func__);
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_KDFCCTL);
+
+				if (!skip_alarms) {
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR,
+					    &vpath->vp_reg->kdfcctl_errors_reg);
+				}
+
+				vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
+				    Result = %d", __FILE__, __func__, __LINE__,
+				    VXGE_HAL_ERR_EVENT_KDFCCTL);
+				return (VXGE_HAL_ERR_EVENT_KDFCCTL);
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo1_overwrite++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR",
+				    __func__);
+
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo2_overwrite++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR",
+				    __func__);
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo0_poison++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON",
+				    __func__);
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_KDFCCTL);
+
+				if (!skip_alarms) {
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON,
+					    &vpath->vp_reg->kdfcctl_errors_reg);
+				}
+
+				vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
+				    Result = %d", __FILE__, __func__, __LINE__,
+				    VXGE_HAL_ERR_EVENT_KDFCCTL);
+				return (VXGE_HAL_ERR_EVENT_KDFCCTL);
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo1_poison++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON",
+				    __func__);
+
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo2_poison++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON",
+				    __func__);
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR",
+				    __func__);
+
+				__hal_device_handle_error(hldev, vpath->vp_id,
+				    VXGE_HAL_EVENT_KDFCCTL);
+
+				if (!skip_alarms) {
+					vxge_os_pio_mem_write64(hldev->header.pdev,
+					    hldev->header.regh0,
+					    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR,
+					    &vpath->vp_reg->kdfcctl_errors_reg);
+				}
+
+				vxge_hal_trace_log_vpath_irq("<== %s:%s:%d \
+				    Result = %d", __FILE__, __func__, __LINE__,
+				    VXGE_HAL_ERR_EVENT_KDFCCTL);
+				return (VXGE_HAL_ERR_EVENT_KDFCCTL);
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo1_dma_error++;
+				vxge_hal_info_log_vpath_irq("%s:"
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR",
+				    __func__);
+			}
+
+			if (val64 &
+			    VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR) {
+				vpath->sw_stats->error_stats.kdfcctl_fifo2_dma_error++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR",
+				    __func__);
+			}
+
+			if (!skip_alarms) {
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->kdfcctl_errors_reg);
+			}
+		}
+	}
+
+	if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT) {
+
+		pif_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->vpath_pcipif_int_status);
+
+		vxge_hal_info_log_vpath_irq(
+		    "vpath_pcipif_int_status = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) pif_status);
+
+		if (pif_status &
+		    VXGE_HAL_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->srpcim_msg_to_vpath_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "srpcim_msg_to_vpath_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			if (val64 &
+			    VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT) {
+
+				val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    &vpath->vpmgmt_reg->srpcim_to_vpath_wmsg);
+
+				__hal_ifmsg_wmsg_process(vpath, val64);
+
+				vpath->sw_stats->error_stats.srpcim_msg_to_vpath++;
+
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    0,
+				    &vpath->vpmgmt_reg->srpcim_to_vpath_wmsg);
+
+				vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+				    hldev->header.regh0,
+				    (u32) VXGE_HAL_INTR_MASK_ALL,
+				    &vpath->vp_reg->srpcim_msg_to_vpath_mask);
+
+				vxge_hal_info_log_vpath_irq("%s:"
+				    "VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT",
+				    __func__);
+			}
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    VXGE_HAL_INTR_MASK_ALL,
+			    &vpath->vp_reg->srpcim_msg_to_vpath_reg);
+		}
+	}
+
+	if (alarm_status & VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
+
+		xgmac_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->xgmac_vp_int_status);
+
+		vxge_hal_info_log_vpath_irq("xgmac_status = 0x"VXGE_OS_STXFMT,
+		    (ptr_t) xgmac_status);
+
+		if (xgmac_status &
+		    VXGE_HAL_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_INT) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->asic_ntwk_vp_err_reg);
+
+			vxge_hal_info_log_vpath_irq(
+			    "asic_ntwk_vp_err_reg = 0x"VXGE_OS_STXFMT,
+			    (ptr_t) val64);
+
+			if (((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT) &&
+			    (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK))) ||
+			    ((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED) &&
+			    (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED)))) {
+				vpath->sw_stats->error_stats.network_sustained_fault++;
+				vxge_hal_info_log_vpath_irq("%s:" \
+				    "VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT",
+				    __func__);
+				vxge_os_pio_mem_write64(vpath->hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT,
+				    &vpath->vp_reg->asic_ntwk_vp_err_mask);
+
+				(void) __hal_device_handle_link_down_ind(hldev);
+			}
+
+			if (((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK) &&
+			    (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT))) ||
+			    ((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED) &&
+			    (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED)))) {
+				vpath->sw_stats->error_stats.network_sustained_ok++;
+				vxge_hal_info_log_vpath_irq(
+				    "%s:VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK",
+				    __func__);
+
+				vxge_os_pio_mem_write64(hldev->header.pdev,
+				    hldev->header.regh0,
+				    VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK,
+				    &vpath->vp_reg->asic_ntwk_vp_err_mask);
+
+				(void) __hal_device_handle_link_up_ind(hldev);
+			}
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    VXGE_HAL_INTR_MASK_ALL,
+			    &vpath->vp_reg->asic_ntwk_vp_err_reg);
+			return (VXGE_HAL_INF_LINK_UP_DOWN);
+		}
+	}
+
+	if (alarm_status & ~(
+	    VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT |
+	    VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT |
+	    VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
+	    VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
+
+		vpath->sw_stats->error_stats.unknown_alarms++;
+		vxge_hal_info_log_vpath_irq(
+		    "%s:%s:%d Unknown Alarm", __FILE__, __func__, __LINE__);
+
+		__hal_device_handle_error(hldev, vpath->vp_id,
+		    VXGE_HAL_EVENT_UNKNOWN);
+		status = VXGE_HAL_ERR_EVENT_UNKNOWN;
+
+	} else {
+		hldev->stats.sw_dev_err_stats.vpath_alarms++;
+		status = VXGE_HAL_OK;
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_begin_irq - Begin IRQ processing.
+ * @vpath_handle: Virtual Path handle.
+ * @skip_alarms: Do not clear the alarms
+ * @reason: "Reason" for the interrupt,	the value of vpath's
+ *			general_int_status register.
+ *
+ * The function	performs two actions, It first checks whether (shared IRQ) the
+ * interrupt was raised	by the device. Next, it	masks the device interrupts.
+ *
+ * Note:
+ * vxge_hal_vpath_begin_irq() does not flush MMIO writes through the
+ * bridge. Therefore, two back-to-back interrupts are potentially possible.
+ * It is the responsibility	of the ULD to make sure	that only one
+ * vxge_hal_vpath_continue_irq() runs at a time.
+ *
+ * Returns: 0, if the interrupt	is not "ours" (note that in this case the
+ * vpath remain enabled).
+ * Otherwise, vxge_hal_vpath_begin_irq() returns 64bit general adapter
+ * status.
+ * See also: vxge_hal_vpath_handle_irq()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_begin_irq(vxge_hal_vpath_h vpath_handle,
+    u32 skip_alarms, u64 *reason)
+{
+	u64 val64;
+	u64 adapter_status;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_status_e ret_val = VXGE_HAL_OK;
+
+	vxge_assert((vpath_handle != NULL) && (reason != NULL));
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", skip_alarms = %d, "
+	    "reason = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
+	    skip_alarms, (ptr_t) reason);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->titan_general_int_status);
+
+	if (vxge_os_unlikely(!val64)) {
+		/* not Titan interrupt	 */
+		*reason = 0;
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_WRONG_IRQ);
+		return (VXGE_HAL_ERR_WRONG_IRQ);
+	}
+
+	if (vxge_os_unlikely(val64 == VXGE_HAL_ALL_FOXES)) {
+
+		adapter_status = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->adapter_status);
+
+		if (adapter_status == VXGE_HAL_ALL_FOXES) {
+			__hal_device_handle_error(hldev,
+			    vpath->vp_id,
+			    VXGE_HAL_EVENT_SLOT_FREEZE);
+
+			*reason = 0;
+			ret_val = VXGE_HAL_ERR_SLOT_FREEZE;
+			goto exit;
+		}
+	}
+
+	if (val64 &
+	    VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(
+	    1 << (16 - vpath->vp_id))) {
+
+		if (vpath->vp_id < 16) {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->common_reg->tim_int_mask0);
+
+			*reason = bVAL4(val64, (vpath->vp_id * 4));
+		} else {
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->common_reg->tim_int_mask1);
+
+			*reason = bVAL4(val64, 0);
+		}
+
+		return (VXGE_HAL_OK);
+	}
+
+	*reason = VXGE_HAL_INTR_ALARM;
+
+	if (vxge_os_unlikely(val64 &
+	    VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT)) {
+		vxge_hal_info_log_vpath_irq(
+		    "%s:VXGE_HAL_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT",
+		    __func__);
+		ret_val = VXGE_HAL_ERR_CRITICAL;
+		goto exit;
+	}
+
+	if (vxge_os_unlikely(val64 &
+	    VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT)) {
+		vxge_hal_info_log_vpath_irq(
+		    "%s:VXGE_HAL_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT",
+		    __func__);
+		ret_val = VXGE_HAL_ERR_CRITICAL;
+		goto exit;
+	}
+
+	if (vxge_os_unlikely(val64 &
+	    VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
+		vxge_hal_info_log_vpath_irq(
+		    "%s:VXGE_HAL_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT",
+		    __func__);
+		ret_val = __hal_vpath_alarm_process(vpath, skip_alarms);
+	}
+
+exit:
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (ret_val);
+
+}
+
+/*
+ * vxge_hal_vpath_continue_irq - Continue handling IRQ:	process	all
+ *				completed descriptors.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Process completed descriptors and unmask the	vpath interrupts.
+ *
+ * The vxge_hal_vpath_continue_irq() calls upper-layer driver (ULD)
+ * via supplied completion callback.
+ *
+ * Note	that the vxge_hal_vpath_continue_irq is	part of	the _fast_ path.
+ * To optimize the processing, the function does _not_ check for
+ * errors and alarms.
+ *
+ * Returns: VXGE_HAL_OK.
+ *
+ * See also: vxge_hal_vpath_handle_irq()
+ * vxge_hal_ring_rxd_next_completed(),
+ * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {},
+ * vxge_hal_fifo_callback_f {}.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_continue_irq(vxge_hal_vpath_h vpath_handle)
+{
+	u32 got_rx = 1, got_tx = 1;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	u32 isr_polling_cnt;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	isr_polling_cnt = hldev->header.config.isr_polling_cnt;
+
+	do {
+		if (got_rx && (vp->vpath->ringh != NULL))
+			(void) vxge_hal_vpath_poll_rx(vpath_handle, &got_rx);
+
+		if (got_tx && (vp->vpath->fifoh != NULL))
+			(void) vxge_hal_vpath_poll_tx(vpath_handle, &got_tx);
+
+		if (!got_rx && !got_tx)
+			break;
+
+	} while (isr_polling_cnt--);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_handle_irq - Handle vpath IRQ.
+ * @vpath_handle: Virtual Path handle.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Perform the complete	handling of the	line interrupt.	The function
+ * performs two	calls.
+ * First it uses vxge_hal_vpath_begin_irq() to check the reason for
+ * the interrupt and mask the vpath interrupts.
+ * Second, it calls vxge_hal_vpath_continue_irq() to process all
+ * completed descriptors and re-enable the interrupts.
+ *
+ * Returns: VXGE_HAL_OK - success;
+ * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device.
+ *
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_handle_irq(vxge_hal_vpath_h vpath_handle, u32 skip_alarms)
+{
+	u64 reason;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	vxge_hal_vpath_mask_all(vpath_handle);
+
+	status = vxge_hal_vpath_begin_irq(vpath_handle,
+	    skip_alarms, &reason);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_vpath_unmask_all(vpath_handle);
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (reason & VXGE_HAL_INTR_ALARM) {
+		if (skip_alarms) {
+			/* ULD needs to unmask explicitely */
+			vxge_hal_trace_log_vpath_irq(
+			    "<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_ERR_CRITICAL);
+			return (VXGE_HAL_ERR_CRITICAL);
+		} else {
+			vxge_hal_vpath_unmask_all(vpath_handle);
+			vxge_hal_trace_log_vpath_irq(
+			    "<== %s:%s:%d Result = %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	if (reason & VXGE_HAL_INTR_RX)
+		vxge_hal_vpath_clear_rx(vpath_handle);
+
+	status = vxge_hal_vpath_continue_irq(vpath_handle);
+
+	vxge_hal_vpath_clear_tx(vpath_handle);
+
+	vxge_hal_vpath_unmask_all(vpath_handle);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_mask_tx - Mask Tx interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	Tx device interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_tx(), vxge_hal_vpath_mask_rx(),
+ * vxge_hal_vpath_clear_tx().
+ */
+void
+vxge_hal_vpath_mask_tx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->fifoh == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask1);
+
+		val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_mask1);
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_clear_tx - Acknowledge (that is, clear) the
+ * condition that has caused the TX interrupt.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Acknowledge (that is, clear)	the condition that has caused
+ * the Tx interrupt.
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
+ * vxge_hal_vpath_clear_rx(), vxge_hal_vpath_mask_tx().
+ */
+void
+vxge_hal_vpath_clear_tx(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->fifoh == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4),
+		    &hldev->common_reg->tim_int_status0);
+
+	} else {
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    vBIT(VXGE_HAL_INTR_TX, 0, 4),
+		    0),
+		    &hldev->common_reg->tim_int_status1);
+
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_unmask_tx - Unmask Tx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask Tx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_tx(), vxge_hal_vpath_clear_tx().
+ */
+void
+vxge_hal_vpath_unmask_tx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->fifoh == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask1);
+
+		val64 &=
+		    ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_mask_rx - Mask Rx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_rx(), vxge_hal_vpath_mask_tx(),
+ * vxge_hal_vpath_clear_rx().
+ */
+void
+vxge_hal_vpath_mask_rx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask1);
+
+		val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+
+/*
+ * vxge_hal_vpath_clear_rx - Acknowledge (that is, clear) the
+ * condition that has caused the RX	interrupt.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Acknowledge (that is, clear)	the condition that has caused
+ * the Rx interrupt.
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
+ * vxge_hal_vpath_clear_tx(), vxge_hal_vpath_mask_rx().
+ */
+void
+vxge_hal_vpath_clear_rx(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4),
+		    &hldev->common_reg->tim_int_status0);
+
+	} else {
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(vBIT(VXGE_HAL_INTR_RX, 0, 4), 0),
+		    &hldev->common_reg->tim_int_status1);
+
+	}
+
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_unmask_rx - Unmask Rx	interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_rx(), vxge_hal_vpath_clear_rx().
+ */
+void
+vxge_hal_vpath_unmask_rx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->ringh == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return;
+	}
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask1);
+
+		val64 &=
+		    ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_mask_tx_rx - Mask Tx and Rx interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Mask	Tx and Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_unmask_tx_rx(), vxge_hal_vpath_clear_tx_rx().
+ */
+void
+vxge_hal_vpath_mask_tx_rx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4) |
+		    vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask1);
+
+		val64 |=
+		    VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX) |
+		    VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+
+/*
+ * vxge_hal_vpath_clear_tx_rx - Acknowledge (that is, clear) the
+ * condition that has caused the Tx and RX interrupt.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Acknowledge (that is, clear)	the condition that has caused
+ * the Tx and Rx interrupt.
+ * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(),
+ * vxge_hal_vpath_clear_tx_rx(), vxge_hal_vpath_mask_tx_rx().
+ */
+void
+vxge_hal_vpath_clear_tx_rx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	val64 = 0;
+
+	if (vpath->vp_id < 16) {
+
+		if (vpath->fifoh != NULL)
+			val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
+		else
+			val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
+
+		if (vpath->ringh != NULL)
+			val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+		else
+			val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_status0);
+
+	} else {
+
+		if (vpath->fifoh != NULL)
+			val64 |= vBIT(VXGE_HAL_INTR_TX, 0, 4);
+
+		if (vpath->ringh != NULL)
+			val64 |= vBIT(VXGE_HAL_INTR_RX, 0, 4);
+		else
+			val64 &= ~vBIT(VXGE_HAL_INTR_RX, 0, 4);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_status1);
+
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_unmask_tx_rx - Unmask Tx and Rx interrupts.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Unmask Tx and Rx vpath interrupts.
+ *
+ * See also: vxge_hal_vpath_mask_tx_rx(), vxge_hal_vpath_clear_tx_rx().
+ */
+void
+vxge_hal_vpath_unmask_tx_rx(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+	}
+
+	if (vpath->vp_id < 16) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask0);
+
+		if (vpath->fifoh != NULL)
+			val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
+		else
+			val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
+
+		if (vpath->ringh != NULL)
+			val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+		else
+			val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &hldev->common_reg->tim_int_mask0);
+
+	} else {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->tim_int_mask1);
+
+		if (vpath->fifoh != NULL)
+			val64 &= ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
+			    VXGE_HAL_INTR_TX);
+		else
+			val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
+			    VXGE_HAL_INTR_TX);
+
+		if (vpath->ringh != NULL)
+			val64 &= ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
+			    VXGE_HAL_INTR_RX);
+		else
+			val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
+			    VXGE_HAL_INTR_RX);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->tim_int_mask1);
+
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_alarm_process - Process Alarms.
+ * @vpath: Virtual Path.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Process vpath alarms.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_alarm_process(vxge_hal_vpath_h vpath_handle, u32 skip_alarms)
+{
+	vxge_hal_status_e status;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_alarm_process(
+	    vp->vpath,
+	    skip_alarms);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_msix_mode - Is MSIX enabled?
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Returns 0 if MSI is enabled for the specified device,
+ * non-zero otherwise.
+ */
+u32
+vxge_hal_vpath_msix_mode(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (hldev->header.msix_enabled);
+}
+
+/*
+ * vxge_hal_vpath_msix_set
+ * Associate MSIX vectors with TIM interrupts and alrms
+ * @vpath_handle: Virtual Path handle.
+ * @tim_msix_id: MSIX vectors associated with VXGE_HAL_VPATH_MSIX_MAX number of
+ *		interrupts(Can be repeated). If fifo or ring are not enabled
+ *		the MSIX vector for that should be set to 0
+ * @alarm_msix_id: MSIX vector for alarm.
+ *
+ * This API will associate a given MSIX vector numbers with the four TIM
+ * interrupts and alarm interrupt.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_msix_set(vxge_hal_vpath_h vpath_handle,
+    int *tim_msix_id,
+    int alarm_msix_id)
+{
+	u32 i;
+	u32 j;
+	u32 rvp_id;
+	u32 msix_id;
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vp != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "tim_msix_id0 = %d, tim_msix_id1 = %d, tim_msix_id2 = %d, "
+	    "tim_msix_id3 = %d, alarm_msix_id = %d", (ptr_t) vpath_handle,
+	    tim_msix_id[0], tim_msix_id[1], tim_msix_id[2], tim_msix_id[3],
+	    alarm_msix_id);
+
+	for (i = 0; i < VXGE_HAL_VPATH_MSIX_MAX + 1; i++) {
+
+		if (i == VXGE_HAL_VPATH_MSIX_MAX)
+			msix_id = alarm_msix_id;
+		else
+			msix_id = tim_msix_id[i];
+
+		rvp_id = msix_id / VXGE_HAL_VPATH_MSIX_MAX;
+
+		for (j = 0; j < VXGE_HAL_MAX_VIRTUAL_PATHS; j++) {
+
+			if (!(hldev->vpath_assignments & mBIT(j)))
+				continue;
+
+			if (rvp_id-- == 0) {
+				hldev->msix_map[msix_id].vp_id = j;
+				hldev->msix_map[msix_id].int_num =
+				    msix_id % VXGE_HAL_VPATH_MSIX_MAX;
+				break;
+			}
+		}
+	}
+
+	val64 = VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
+	    hldev->msix_map[tim_msix_id[0]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
+	    hldev->msix_map[tim_msix_id[0]].int_num) |
+	    VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
+	    hldev->msix_map[tim_msix_id[1]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
+	    hldev->msix_map[tim_msix_id[1]].int_num) |
+	    VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
+	    hldev->msix_map[tim_msix_id[2]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
+	    hldev->msix_map[tim_msix_id[2]].int_num) |
+	    VXGE_HAL_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(
+	    hldev->msix_map[tim_msix_id[3]].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
+	    hldev->msix_map[tim_msix_id[3]].int_num);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vp->vpath->vp_reg->interrupt_cfg0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
+	    hldev->msix_map[alarm_msix_id].vp_id * VXGE_HAL_VPATH_MSIX_MAX +
+	    hldev->msix_map[alarm_msix_id].int_num),
+	    &vp->vpath->vp_reg->interrupt_cfg2);
+
+	if (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) {
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect0_en);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect1_en);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect2_en);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect3_en);
+
+	} else if (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA) {
+		/* For emulated-INTA we are only using MSI-X 1 to be one shot */
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect1_en);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_msix_mask - Mask MSIX Vector.
+ * @vpath_handle: Virtual Path handle.
+ * @msix_id:  MSIX ID
+ *
+ * The function masks the msix interrupt for the given msix_id
+ *
+ * Note:
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", msix_id = %d",
+	    (ptr_t) vpath_handle, msix_id);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
+	    &hldev->common_reg->set_msix_mask_vect[
+	    hldev->msix_map[msix_id].int_num]);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_msix_clear - Clear MSIX Vector.
+ * @vpath_handle: Virtual Path handle.
+ * @msix_id:  MSI ID
+ *
+ * The function clears the msix interrupt for the given msix_id
+ *
+ * Note:
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vp = (__hal_vpath_handle_t *) vpath_handle;
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", msix_id = %d",
+	    (ptr_t) vpath_handle, msix_id);
+
+	if ((hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) ||
+	    (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA)) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
+		    &hldev->common_reg->clr_msix_one_shot_vec[
+		    hldev->msix_map[msix_id].int_num]);
+
+		if (hldev->header.config.intr_mode ==
+		    VXGE_HAL_INTR_MODE_EMULATED_INTA) {
+			/* Adding read to flush the write,
+			 * for HP-ISS platform
+			 */
+			vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &hldev->common_reg->titan_general_int_status);
+		}
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
+		    &hldev->common_reg->clear_msix_mask_vect[
+		    hldev->msix_map[msix_id].int_num]);
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/* NEW CODE BEGIN */
+
+vxge_hal_status_e
+vxge_hal_vpath_mf_msix_set(vxge_hal_vpath_h vpath_handle,
+    int *tim_msix_id,
+    int alarm_msix_id)
+{
+
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vp = (__hal_vpath_handle_t *) vpath_handle;
+	hldev = vp->vpath->hldev;
+
+	/* Write the internal msi-x vectors numbers */
+	val64 = VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(tim_msix_id[0]) |
+	    VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(tim_msix_id[1]);
+
+#if defined(VXGE_EMULATED_INTA)
+	if (hldev->config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA)
+		val64 |= VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
+		    (vp->vpath->vp_id * 4) + tim_msix_id[2]);
+#endif
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vp->vpath->vp_reg->interrupt_cfg0);
+
+	vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp->vpath->vp_reg->interrupt_cfg0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
+	    (hldev->first_vp_id * 4) + alarm_msix_id),
+	    &vp->vpath->vp_reg->interrupt_cfg2);
+
+	if (
+#if defined(VXGE_EMULATED_INTA)
+	    (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA) ||
+#endif
+	    (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT)) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect1_en);
+	}
+
+	if (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect2_en);
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0, (u32) bVAL32(
+		    VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN, 0),
+		    &vp->vpath->vp_reg->one_shot_vect3_en);
+	}
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_mf_msix_mask - Mask MSIX Vector.
+ * @vp: Virtual Path handle.
+ * @msix_id:  MSIX ID
+ *
+ * The function masks the msix interrupt for the given msix_id
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_mf_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_hal_pio_mem_write32_upper(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0, (u32) bVAL32(mBIT(msix_id >> 2), 0),
+	    &vp->vpath->hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
+}
+
+/*
+ * vxge_hal_vpath_mf_msix_clear - Clear MSIX Vector.
+ * @vp: Virtual Path handle.
+ * @msix_id:  MSI ID
+ *
+ * The function clears the msix interrupt for the given msix_id
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_mf_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	if (
+#if defined(VXGE_EMULATED_INTA)
+	    (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA) ||
+#endif
+	    (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT)) {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(mBIT((msix_id >> 2)), 0),
+		    &hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
+	} else {
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(mBIT((msix_id >> 2)), 0),
+		    &hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
+	}
+}
+
+/*
+ * vxge_hal_vpath_mf_msix_unmask - Unmask the MSIX Vector.
+ * @vp: Virtual Path handle.
+ * @msix_id:  MSI ID
+ *
+ * The function unmasks the msix interrupt for the given msix_id
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_mf_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	vxge_hal_pio_mem_write32_upper(vp->vpath->hldev->header.pdev,
+	    vp->vpath->hldev->header.regh0,
+	    (u32) bVAL32(mBIT(msix_id >> 2), 0),
+	    &vp->vpath->hldev->common_reg->
+	    clear_msix_mask_vect[msix_id % 4]);
+}
+
+/* NEW CODE ENDS */
+
+/*
+ * vxge_hal_vpath_msix_unmask - Unmask the MSIX Vector.
+ * @vpath_handle: Virtual Path handle.
+ * @msix_id:  MSI ID
+ *
+ * The function unmasks the msix interrupt for the given msix_id
+ *
+ * Note:
+ *
+ * Returns: 0,
+ * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range
+ * status.
+ * See also:
+ */
+void
+vxge_hal_vpath_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT", msix_id = %d",
+	    (ptr_t) vpath_handle, msix_id);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(mBIT(hldev->msix_map[msix_id].vp_id), 0),
+	    &hldev->common_reg->clear_msix_mask_vect[
+	    hldev->msix_map[msix_id].int_num]);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_msix_mask_all - Mask all MSIX vectors for the vpath.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * The function masks all msix interrupt for the given vpath
+ *
+ */
+void
+vxge_hal_vpath_msix_mask_all(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(mBIT(vp->vpath->vp_id), 0),
+	    &hldev->common_reg->set_msix_mask_all_vect);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+
+}
+
+/*
+ * vxge_hal_vpath_msix_unmask_all - Unmask all MSIX vectors for the vpath.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * The function unmasks the msix interrupt for the given vpath
+ *
+ */
+void
+vxge_hal_vpath_msix_unmask_all(vxge_hal_vpath_h vpath_handle)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(mBIT(vp->vpath->vp_id), 0),
+	    &hldev->common_reg->clear_msix_mask_all_vect);
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d Result = 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+/*
+ * vxge_hal_vpath_poll_rx - Poll Rx Virtual Path for completed
+ *			descriptors and process the same.
+ * @vpath_handle: Virtual Path ahandle.
+ * @got_rx: Buffer to return the flag set if receive interrupt is occured
+ *
+ * The function	polls the Rx for the completed	descriptors and	calls
+ * the upper-layer driver (ULD)	via supplied completion	callback.
+ *
+ * Returns: VXGE_HAL_OK, if the polling is completed successful.
+ * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed
+ * descriptors available which are yet to be processed.
+ *
+ * See also: vxge_hal_vpath_poll_tx()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_poll_rx(vxge_hal_vpath_h vpath_handle, u32 *got_rx)
+{
+	u8 t_code;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_rxd_h first_rxdh;
+	void *rxd_priv;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	__hal_ring_t *ring;
+
+	vxge_assert((vpath_handle != NULL) && (got_rx != NULL));
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpathh = 0x"VXGE_OS_STXFMT", got_rx = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) got_rx);
+
+	ring = (__hal_ring_t *) vpath->ringh;
+	if (ring == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	ring->cmpl_cnt = 0;
+	ring->channel.poll_bytes = 0;
+	*got_rx = 0;
+
+	if ((status = vxge_hal_ring_rxd_next_completed(vpath_handle,
+	    &first_rxdh, &rxd_priv, &t_code)) == VXGE_HAL_OK) {
+		if (ring->callback(vpath_handle, first_rxdh, rxd_priv,
+		    t_code, ring->channel.userdata) != VXGE_HAL_OK) {
+			status = VXGE_HAL_COMPLETIONS_REMAIN;
+		}
+
+		(*got_rx)++;
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_poll_tx - Poll Tx for completed descriptors and process
+ *			the same.
+ * @vpath_handle: Virtual Path ahandle.
+ * @got_tx: Buffer to return the flag set if transmit interrupt is occured
+ *
+ * The function	polls the Tx for the completed	descriptors and	calls
+ * the upper-layer driver (ULD)	via supplied completion callback.
+ *
+ * Returns: VXGE_HAL_OK, if the polling is completed successful.
+ * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed
+ * descriptors available which are yet to be processed.
+ *
+ * See also: vxge_hal_vpath_poll_rx().
+ */
+vxge_hal_status_e
+vxge_hal_vpath_poll_tx(vxge_hal_vpath_h vpath_handle, u32 *got_tx)
+{
+	vxge_hal_fifo_tcode_e t_code;
+	vxge_hal_txdl_h first_txdlh;
+	void *txdl_priv;
+	__hal_virtualpath_t *vpath;
+	__hal_fifo_t *fifo;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((vpath_handle != NULL) && (got_tx != NULL));
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath_irq("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath_irq(
+	    "vpathh = 0x"VXGE_OS_STXFMT", got_tx = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) got_tx);
+
+	fifo = (__hal_fifo_t *) vpath->fifoh;
+	if (fifo == NULL) {
+		vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	fifo->channel.poll_bytes = 0;
+	*got_tx = 0;
+
+	if ((status = vxge_hal_fifo_txdl_next_completed(vpath_handle,
+	    &first_txdlh, &txdl_priv, &t_code)) == VXGE_HAL_OK) {
+		if (fifo->callback(vpath_handle, first_txdlh, txdl_priv,
+		    t_code, fifo->channel.userdata) != VXGE_HAL_OK) {
+			status = VXGE_HAL_COMPLETIONS_REMAIN;
+		}
+
+		(*got_tx)++;
+	}
+
+	vxge_hal_trace_log_vpath_irq("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+
+/*
+ * __hal_vpath_mgmt_read
+ * @hldev: HAL device
+ * @vpath: Virtual path structure
+ *
+ * This routine reads the vpath_mgmt registers
+ */
+vxge_hal_status_e
+__hal_vpath_mgmt_read(
+    __hal_device_t *hldev,
+    __hal_virtualpath_t *vpath)
+{
+	u32 i, mtu;
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((hldev != NULL) && (vpath != NULL));
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "hldev = 0x"VXGE_OS_STXFMT", vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) hldev, (ptr_t) vpath);
+
+	vpath->sess_grps_available = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->sgrp_own);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->vpath_is_first);
+
+	vpath->is_first_vpath =
+	    (u32) VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->tim_vpath_assignment);
+
+	vpath->bmap_root_assigned =
+	    (u32) VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(val64);
+
+	mtu = 0;
+
+	for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[i]);
+
+		if (mtu < (u32)
+		    VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(
+		    val64)) {
+			mtu = (u32)
+			    VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(
+			    val64);
+		}
+	}
+
+	vpath->max_mtu = mtu + VXGE_HAL_MAC_HEADER_MAX_SIZE;
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->xmac_vsport_choices_vp);
+
+	vpath->vsport_choices =
+	    (u32) VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(val64);
+
+	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
+
+		if (val64 & mBIT(i))
+			vpath->vsport_number = i;
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
+
+	if (val64 & VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) {
+
+		VXGE_HAL_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HAL_LINK_UP);
+
+	} else {
+
+		VXGE_HAL_DEVICE_LINK_STATE_SET(vpath->hldev,
+		    VXGE_HAL_LINK_DOWN);
+
+	}
+
+	if (val64 &
+	    VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE) {
+
+		VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
+		    VXGE_HAL_DATA_RATE_10G);
+
+	} else {
+
+		VXGE_HAL_DEVICE_DATA_RATE_SET(vpath->hldev,
+		    VXGE_HAL_DATA_RATE_1G);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_reset_check - Check if resetting the vpath completed
+ *
+ * @vpath: Virtual Path
+ *
+ * This routine checks the vpath_rst_in_prog register to see if adapter
+ * completed the reset process for the vpath
+ */
+vxge_hal_status_e
+__hal_vpath_reset_check(
+    __hal_virtualpath_t *vpath)
+{
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->vpath_rst_in_prog,
+	    0,
+	    VXGE_HAL_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
+	    1 << (16 - vpath->vp_id)),
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_hw_reset
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine resets the vpath on the device
+ */
+vxge_hal_status_e
+__hal_vpath_hw_reset(vxge_hal_device_h devh, u32 vp_id)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	__hal_device_t *hldev;
+
+	vxge_assert(devh != NULL);
+
+	hldev = (__hal_device_t *) devh;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	val64 = VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->cmn_rsthdlr_cfg0);
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_BEGIN,
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_sw_reset
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine resets the vpath structures
+ */
+vxge_hal_status_e
+__hal_vpath_sw_reset(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(devh != NULL);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	if (vpath->ringh) {
+
+		status = __hal_ring_reset(vpath->ringh);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	if (vpath->fifoh) {
+
+		status = __hal_fifo_reset(vpath->fifoh);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_enable
+ * @vpath_handle: Handle to the vpath object
+ *
+ * This routine clears the vpath reset and puts vpath in service
+ */
+vxge_hal_status_e
+vxge_hal_vpath_enable(
+    vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	val64 = VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
+	    1 << (16 - vpath->vp_id));
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->cmn_rsthdlr_cfg1);
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    vpath->vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END,
+	    0);
+
+	VXGE_HAL_RING_POST_DOORBELL(vpath_handle, vpath->ringh);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+
+/*
+ * __hal_vpath_prc_configure
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine configures the prc registers of virtual path
+ * using the config passed
+ */
+vxge_hal_status_e
+__hal_vpath_prc_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_vp_config_t *vp_config;
+
+	vxge_assert(devh != NULL);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	vp_config = vpath->vp_config;
+
+	if (vp_config->ring.enable == VXGE_HAL_RING_DISABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->prc_cfg1);
+
+	if (vp_config->ring.rx_timer_val !=
+	    VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL) {
+		val64 &= ~VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(0x1fffffff);
+		val64 |= VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(
+		    vp_config->ring.rx_timer_val);
+	}
+
+	val64 |= VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE;
+
+	if (vp_config->ring.greedy_return !=
+	    VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT) {
+		if (vp_config->ring.greedy_return)
+			val64 |= VXGE_HAL_PRC_CFG1_GREEDY_RETURN;
+		else
+			val64 &= ~VXGE_HAL_PRC_CFG1_GREEDY_RETURN;
+	}
+
+	if (vp_config->ring.rx_timer_ci !=
+	    VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT) {
+		if (vp_config->ring.rx_timer_ci)
+			val64 |= VXGE_HAL_PRC_CFG1_RX_TIMER_CI;
+		else
+			val64 &= ~VXGE_HAL_PRC_CFG1_RX_TIMER_CI;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->prc_cfg1);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->prc_cfg7);
+
+	if (vpath->vp_config->ring.scatter_mode !=
+	    VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
+
+		val64 &= ~VXGE_HAL_PRC_CFG7_SCATTER_MODE(0x3);
+
+		switch (vpath->vp_config->ring.scatter_mode) {
+		case VXGE_HAL_RING_SCATTER_MODE_A:
+			val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
+			    VXGE_HAL_PRC_CFG7_SCATTER_MODE_A);
+			break;
+		case VXGE_HAL_RING_SCATTER_MODE_B:
+			val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
+			    VXGE_HAL_PRC_CFG7_SCATTER_MODE_B);
+			break;
+		case VXGE_HAL_RING_SCATTER_MODE_C:
+			val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
+			    VXGE_HAL_PRC_CFG7_SCATTER_MODE_C);
+			break;
+		}
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->prc_cfg7);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->prc_cfg6);
+
+	if (vpath->vp_config->ring.post_mode !=
+	    VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT) {
+
+		if (vpath->vp_config->ring.post_mode ==
+		    VXGE_HAL_RING_POST_MODE_DOORBELL)
+			val64 |= VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN;
+		else
+			val64 &= ~VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN;
+
+	} else {
+
+		vpath->vp_config->ring.post_mode =
+		    ((val64 & VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN) ?
+		    VXGE_HAL_RING_POST_MODE_DOORBELL :
+		    VXGE_HAL_RING_POST_MODE_LEGACY);
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->prc_cfg6);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_PRC_CFG5_RXD0_ADD(
+	    __hal_ring_first_block_address_get(vpath->ringh) >> 3),
+	    &vpath->vp_reg->prc_cfg5);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->prc_cfg4);
+
+	val64 |= VXGE_HAL_PRC_CFG4_IN_SVC;
+
+	val64 &= ~VXGE_HAL_PRC_CFG4_RING_MODE(0x3);
+
+	if (vp_config->ring.buffer_mode == VXGE_HAL_RING_RXD_BUFFER_MODE_1) {
+		val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
+		    VXGE_HAL_PRC_CFG4_RING_MODE_ONE_BUFFER);
+	} else {
+		if (vp_config->ring.buffer_mode ==
+		    VXGE_HAL_RING_RXD_BUFFER_MODE_3) {
+			val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
+			    VXGE_HAL_PRC_CFG4_RING_MODE_THREE_BUFFER);
+		} else {
+			val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
+			    VXGE_HAL_PRC_CFG4_RING_MODE_FIVE_BUFFER);
+		}
+	}
+
+	if (vp_config->ring.no_snoop_bits !=
+	    VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT) {
+
+		val64 &= ~(VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP |
+		    VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP);
+
+		if (vp_config->ring.no_snoop_bits ==
+		    VXGE_HAL_RING_NO_SNOOP_RXD) {
+			val64 |= VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP;
+		} else {
+			if (vp_config->ring.no_snoop_bits ==
+			    VXGE_HAL_RING_NO_SNOOP_FRM) {
+				val64 |= VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP;
+			} else {
+				if (vp_config->ring.no_snoop_bits ==
+				    VXGE_HAL_RING_NO_SNOOP_ALL) {
+					val64 |= VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP;
+					val64 |= VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP;
+				}
+			}
+		}
+
+	}
+
+	if (hldev->header.config.rth_en == VXGE_HAL_RTH_DISABLE)
+		val64 |= VXGE_HAL_PRC_CFG4_RTH_DISABLE;
+	else
+		val64 &= ~VXGE_HAL_PRC_CFG4_RTH_DISABLE;
+
+	val64 |= VXGE_HAL_PRC_CFG4_SIGNAL_BENIGN_OVFLW;
+
+	val64 |= VXGE_HAL_PRC_CFG4_BIMODAL_INTERRUPT;
+
+	if (vp_config->ring.backoff_interval_us !=
+	    VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US) {
+
+		val64 &= ~VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(0xffffff);
+
+		val64 |= VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(
+		    vp_config->ring.backoff_interval_us * 1000 / 4);
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->prc_cfg4);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_vpath_kdfc_configure
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine configures the kdfc registers of virtual path
+ * using the config passed
+ */
+vxge_hal_status_e
+__hal_vpath_kdfc_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	u64 val64;
+	u64 vpath_stride;
+	u64 fifo_stride;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(devh != NULL);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	status = __hal_kdfc_swapper_set((vxge_hal_device_t *) hldev, vp_id);
+
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+
+	}
+
+	if ((vpath->vp_config->ring.post_mode ==
+	    VXGE_HAL_RING_POST_MODE_DOORBELL) &&
+	    (vxge_hal_device_check_id(devh) == VXGE_HAL_CARD_TITAN_1)) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->rxdmem_size);
+
+		vpath->rxd_mem_size =
+		    (u32) VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val64) * 8;
+
+	} else {
+
+		vpath->rxd_mem_size = (VXGE_HAL_MAX_RING_LENGTH /
+		    vxge_hal_ring_rxds_per_block_get(
+		    vpath->vp_config->ring.buffer_mode)) *
+		    VXGE_OS_HOST_PAGE_SIZE;
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->kdfc_drbl_triplet_total);
+
+	vpath->max_kdfc_db =
+	    (u32) VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(val64 + 1) / 2;
+
+	vpath->max_ofl_db = 0;
+
+	if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
+
+		vpath->max_nofl_db = vpath->max_kdfc_db - 1;
+		vpath->max_msg_db = 0;
+
+		if (vpath->max_nofl_db < vpath->vp_config->fifo.fifo_length) {
+
+			vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__,
+			    VXGE_HAL_BADCFG_FIFO_LENGTH);
+			return (VXGE_HAL_BADCFG_FIFO_LENGTH);
+		}
+
+	} else {
+
+		vpath->max_nofl_db = 0;
+		vpath->max_msg_db = vpath->max_kdfc_db;
+	}
+
+	val64 = 0;
+
+	if (vpath->max_nofl_db)
+		val64 |= VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
+		    (vpath->max_nofl_db * 2) - 1);
+
+	if (vpath->max_msg_db)
+		val64 |= VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(
+		    (vpath->max_msg_db * 2) - 1);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->kdfc_fifo_trpl_partition);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
+	    &vpath->vp_reg->kdfc_fifo_trpl_ctrl);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->kdfc_trpl_fifo_0_ctrl);
+
+	if (vpath->max_nofl_db) {
+
+		val64 &= ~(VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
+		    VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
+
+		val64 |= VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(
+		    VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
+#if !defined(VXGE_OS_HOST_BIG_ENDIAN)
+		    VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
+#endif
+		    VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
+
+		if (vpath->vp_config->no_snoop !=
+		    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->no_snoop)
+				val64 |=
+				    VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP;
+			else
+				val64 &=
+				    ~VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP;
+		}
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->kdfc_trpl_fifo_0_ctrl);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->kdfc_trpl_fifo_1_ctrl);
+
+	if (vpath->max_msg_db) {
+
+		val64 &= ~(VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(0x3) |
+		    VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(0xFF));
+
+		val64 |= VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(
+		    VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY) |
+#if !defined(VXGE_OS_HOST_BIG_ENDIAN)
+		    VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN |
+#endif
+		    VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(0);
+
+		if (vpath->vp_config->no_snoop !=
+		    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->no_snoop)
+				val64 |=
+				    VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP;
+			else
+				val64 &=
+				    ~VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP;
+		}
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->kdfc_trpl_fifo_1_ctrl);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->kdfc_trpl_fifo_2_ctrl);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->kdfc_trpl_fifo_0_wb_address);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->kdfc_trpl_fifo_1_wb_address);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->kdfc_trpl_fifo_2_wb_address);
+
+
+	vxge_os_wmb();
+
+	vpath_stride = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_kdfc_vpath_stride);
+
+	fifo_stride = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->toc_reg->toc_kdfc_fifo_stride);
+
+	vpath->nofl_db = (__hal_non_offload_db_wrapper_t *) ((void *)(hldev->kdfc +
+	    (vp_id * VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
+	    vpath_stride))));
+
+	vpath->msg_db = (__hal_messaging_db_wrapper_t *) ((void *)(hldev->kdfc +
+	    (vp_id * VXGE_HAL_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
+	    vpath_stride)) +
+	    VXGE_HAL_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(
+	    fifo_stride)));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_vpath_mac_configure
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine configures the mac of virtual path using the config passed
+ */
+vxge_hal_status_e
+__hal_vpath_mac_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_vp_config_t *vp_config;
+
+	vxge_assert(devh != NULL);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	vp_config = vpath->vp_config;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    VXGE_HAL_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(vpath->vsport_number),
+	    &vpath->vp_reg->xmac_vsport_choice);
+
+	if (vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->xmac_rpa_vcfg);
+
+		if (vp_config->rpa_ipv4_tcp_incl_ph !=
+		    VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_ipv4_tcp_incl_ph)
+				val64 |=
+				    VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
+			else
+				val64 &=
+				    ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
+		}
+
+		if (vp_config->rpa_ipv6_tcp_incl_ph !=
+		    VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_ipv6_tcp_incl_ph)
+				val64 |=
+				    VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
+			else
+				val64 &=
+				    ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
+		}
+
+		if (vp_config->rpa_ipv4_udp_incl_ph !=
+		    VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_ipv4_udp_incl_ph)
+				val64 |=
+				    VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
+			else
+				val64 &=
+				    ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
+		}
+
+		if (vp_config->rpa_ipv6_udp_incl_ph !=
+		    VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_ipv6_udp_incl_ph)
+				val64 |=
+				    VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
+			else
+				val64 &=
+				    ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
+		}
+
+		if (vp_config->rpa_l4_incl_cf !=
+		    VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_l4_incl_cf)
+				val64 |= VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
+			else
+				val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
+		}
+
+		if (vp_config->rpa_strip_vlan_tag !=
+		    VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_strip_vlan_tag)
+				val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
+			else
+				val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->xmac_rpa_vcfg);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->rxmac_vcfg0);
+
+		if (vp_config->mtu !=
+		    VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
+			val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
+			if ((vp_config->mtu + VXGE_HAL_MAC_HEADER_MAX_SIZE) <
+			    vpath->max_mtu)
+				val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
+				    vp_config->mtu +
+				    VXGE_HAL_MAC_HEADER_MAX_SIZE);
+			else
+				val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
+				    vpath->max_mtu);
+		}
+
+		if (vp_config->rpa_ucast_all_addr_en !=
+		    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_ucast_all_addr_en)
+				val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
+		} else {
+			if (val64 & VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
+				vp_config->rpa_ucast_all_addr_en =
+				    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE;
+			} else {
+				vp_config->rpa_ucast_all_addr_en =
+				    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE;
+			}
+		}
+
+		if (vp_config->rpa_mcast_all_addr_en !=
+		    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_mcast_all_addr_en)
+				val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
+		} else {
+			if (val64 & VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
+				vp_config->rpa_mcast_all_addr_en =
+				    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE;
+			} else {
+				vp_config->rpa_mcast_all_addr_en =
+				    VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE;
+			}
+		}
+
+		if (vp_config->rpa_bcast_en !=
+		    VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_bcast_en)
+				val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
+		} else {
+			if (val64 & VXGE_HAL_RXMAC_VCFG0_BCAST_EN) {
+				vp_config->rpa_bcast_en =
+				    VXGE_HAL_VPATH_RPA_BCAST_ENABLE;
+			} else {
+				vp_config->rpa_bcast_en =
+				    VXGE_HAL_VPATH_RPA_BCAST_DISABLE;
+			}
+		}
+
+		if (vp_config->rpa_all_vid_en !=
+		    VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_all_vid_en)
+				val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+		} else {
+			if (val64 & VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN) {
+				vp_config->rpa_all_vid_en =
+				    VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE;
+			} else {
+				vp_config->rpa_all_vid_en =
+				    VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE;
+			}
+		}
+
+		if (vpath->promisc_en == VXGE_HAL_VP_PROMISC_ENABLE) {
+			val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
+			    VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
+			    VXGE_HAL_RXMAC_VCFG0_BCAST_EN |
+			    VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->rxmac_vcfg0);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->rxmac_vcfg1);
+
+		val64 &= ~(VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
+		    VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
+
+		if (hldev->header.config.rth_it_type ==
+		    VXGE_HAL_RTH_IT_TYPE_MULTI_IT) {
+			val64 |=
+			    VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x2) |
+			    VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
+		}
+
+		if (vp_config->vp_queue_l2_flow !=
+		    VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT) {
+			if (vp_config->vp_queue_l2_flow)
+				val64 |= VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW;
+			else
+				val64 &= ~VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->rxmac_vcfg1);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->fau_rpa_vcfg);
+
+		if (vp_config->rpa_l4_comp_csum !=
+		    VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_l4_comp_csum)
+				val64 |= VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
+			else
+				val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
+		}
+
+		if (vp_config->rpa_l3_incl_cf !=
+		    VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_l3_incl_cf)
+				val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
+			else
+				val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
+		}
+
+		if (vp_config->rpa_l3_comp_csum !=
+		    VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT) {
+			if (vp_config->rpa_l3_comp_csum)
+				val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
+			else
+				val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->fau_rpa_vcfg);
+	}
+
+	if (vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tpa_cfg);
+
+		if (vp_config->tpa_ignore_frame_error !=
+		    VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT) {
+			if (vp_config->tpa_ignore_frame_error)
+				val64 |= VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
+			else
+				val64 &= ~VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
+		}
+
+		if (vp_config->tpa_ipv6_keep_searching !=
+		    VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) {
+			if (vp_config->tpa_ipv6_keep_searching)
+				val64 |= VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
+			else
+				val64 &= ~VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
+		}
+
+		if (vp_config->tpa_l4_pshdr_present !=
+		    VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT) {
+			if (vp_config->tpa_l4_pshdr_present)
+				val64 |= VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
+			else
+				val64 &= ~VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
+		}
+
+		if (vp_config->tpa_support_mobile_ipv6_hdrs !=
+		    VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT) {
+			if (vp_config->tpa_support_mobile_ipv6_hdrs)
+				val64 |=
+				    VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
+			else
+				val64 &=
+				    ~VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tpa_cfg);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tx_protocol_assist_cfg);
+
+		if (vp_config->tpa_lsov2_en !=
+		    VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT) {
+			if (vp_config->tpa_lsov2_en)
+				val64 |=
+				    VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
+		}
+
+		if (vp_config->tpa_ipv6_keep_searching !=
+		    VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) {
+			if (vp_config->tpa_ipv6_keep_searching)
+				val64 |= VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
+			else
+				val64 &= ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tx_protocol_assist_cfg);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_vpath_tim_configure
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine configures the tim registers of virtual path
+ * using the config passed
+ */
+vxge_hal_status_e
+__hal_vpath_tim_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_dest_addr);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_vpath_map);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_bitmap);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_remap);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rtdma_rd_optimization_ctrl);
+
+	val64 |= VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
+
+	if (hldev->header.config.intr_mode == VXGE_HAL_INTR_MODE_EMULATED_INTA)
+		val64 = 0x1000150012000100ULL;	/* override for HPISS */
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rtdma_rd_optimization_ctrl);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->tim_wrkld_clc);
+
+	val64 |= VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(0x5BE9) |
+	    VXGE_HAL_TIM_WRKLD_CLC_CNT_FRM_BYTE |
+	    VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0x15) |
+	    VXGE_HAL_TIM_WRKLD_CLC_CNT_RX_TX(3);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tim_wrkld_clc);
+
+	if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    VXGE_HAL_TIM_RING_ASSN_INT_NUM(vpath->rx_intr_num),
+		    &vpath->vp_reg->tim_ring_assn);
+
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->tim_pci_cfg);
+
+	val64 |= VXGE_HAL_TIM_PCI_CFG_ADD_PAD;
+
+	if (vpath->vp_config->no_snoop !=
+	    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
+		if (vpath->vp_config->no_snoop)
+			val64 |= VXGE_HAL_TIM_PCI_CFG_NO_SNOOP;
+		else
+			val64 &= ~VXGE_HAL_TIM_PCI_CFG_NO_SNOOP;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tim_pci_cfg);
+
+	if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+		if (vpath->vp_config->tti.btimer_val !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(0x3ffffff);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(
+			    vpath->vp_config->tti.btimer_val);
+		}
+
+		val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN;
+
+		if (vpath->vp_config->tti.txfrm_cnt_en !=
+		    VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->tti.txfrm_cnt_en)
+				val64 |=
+				    VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
+		}
+
+		if (vpath->vp_config->tti.txd_cnt_en !=
+		    VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->tti.txd_cnt_en)
+				val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
+		}
+
+		if (vpath->vp_config->tti.timer_ac_en !=
+		    VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->tti.timer_ac_en)
+				val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
+		}
+
+		if (vpath->vp_config->tti.timer_ci_en !=
+		    VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->tti.timer_ci_en)
+				val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+		}
+
+		if (vpath->vp_config->tti.urange_a !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A) {
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(
+			    vpath->vp_config->tti.urange_a);
+		}
+
+		if (vpath->vp_config->tti.urange_b !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B) {
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(
+			    vpath->vp_config->tti.urange_b);
+		}
+
+		if (vpath->vp_config->tti.urange_c !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C) {
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(
+			    vpath->vp_config->tti.urange_c);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+		vpath->tim_tti_cfg1_saved = val64;
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+		if (vpath->vp_config->tti.uec_a !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(
+			    vpath->vp_config->tti.uec_a);
+		}
+
+		if (vpath->vp_config->tti.uec_b !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(
+			    vpath->vp_config->tti.uec_b);
+		}
+
+		if (vpath->vp_config->tti.uec_c !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(
+			    vpath->vp_config->tti.uec_c);
+		}
+
+		if (vpath->vp_config->tti.uec_d !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(
+			    vpath->vp_config->tti.uec_d);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+		if (vpath->vp_config->tti.timer_ri_en !=
+		    VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->tti.timer_ri_en)
+				val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
+		}
+
+		if (vpath->vp_config->tti.rtimer_event_sf !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(0xf);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(
+			    vpath->vp_config->tti.rtimer_event_sf);
+		}
+
+		if (vpath->vp_config->tti.rtimer_val !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL) {
+			val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
+			    0x3ffffff);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
+			    vpath->vp_config->tti.rtimer_val);
+		}
+
+		if (vpath->vp_config->tti.util_sel !=
+		    VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT) {
+			val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(
+			    vpath->vp_config->tti.util_sel);
+		}
+
+		if (vpath->vp_config->tti.ltimer_val !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(0x3ffffff);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(
+			    vpath->vp_config->tti.ltimer_val);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+		vpath->tim_tti_cfg3_saved = val64;
+	}
+
+	if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+		if (vpath->vp_config->rti.btimer_val !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(0x3ffffff);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(
+			    vpath->vp_config->rti.btimer_val);
+		}
+
+		val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN;
+
+		if (vpath->vp_config->rti.txfrm_cnt_en !=
+		    VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->rti.txfrm_cnt_en)
+				val64 |=
+				    VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
+			else
+				val64 &=
+				    ~VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN;
+		}
+
+		if (vpath->vp_config->rti.txd_cnt_en !=
+		    VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->rti.txd_cnt_en)
+				val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
+		}
+
+		if (vpath->vp_config->rti.timer_ac_en !=
+		    VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->rti.timer_ac_en)
+				val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
+		}
+
+		if (vpath->vp_config->rti.timer_ci_en !=
+		    VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->rti.timer_ci_en)
+				val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+		}
+
+		if (vpath->vp_config->rti.urange_a !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A) {
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(
+			    vpath->vp_config->rti.urange_a);
+		}
+
+		if (vpath->vp_config->rti.urange_b !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B) {
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(
+			    vpath->vp_config->rti.urange_b);
+		}
+
+		if (vpath->vp_config->rti.urange_c !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C) {
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(
+			    vpath->vp_config->rti.urange_c);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+		vpath->tim_rti_cfg1_saved = val64;
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+		if (vpath->vp_config->rti.uec_a !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(
+			    vpath->vp_config->rti.uec_a);
+		}
+
+		if (vpath->vp_config->rti.uec_b !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(
+			    vpath->vp_config->rti.uec_b);
+		}
+
+		if (vpath->vp_config->rti.uec_c !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(
+			    vpath->vp_config->rti.uec_c);
+		}
+
+		if (vpath->vp_config->rti.uec_d !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D) {
+			val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(0xffff);
+			val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(
+			    vpath->vp_config->rti.uec_d);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+		if (vpath->vp_config->rti.timer_ri_en !=
+		    VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT) {
+			if (vpath->vp_config->rti.timer_ri_en)
+				val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
+			else
+				val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
+		}
+
+		if (vpath->vp_config->rti.rtimer_event_sf !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(0xf);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(
+			    vpath->vp_config->rti.rtimer_event_sf);
+		}
+
+		if (vpath->vp_config->rti.rtimer_val !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
+			    vpath->vp_config->rti.rtimer_val);
+		}
+
+		if (vpath->vp_config->rti.util_sel !=
+		    VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT) {
+			val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(
+			    vpath->vp_config->rti.util_sel);
+		}
+
+		if (vpath->vp_config->rti.ltimer_val !=
+		    VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL) {
+			val64 &=
+			    ~VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(0x3ffffff);
+			val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(
+			    vpath->vp_config->rti.ltimer_val);
+		}
+
+		vxge_os_pio_mem_write64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    val64,
+		    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+		vpath->tim_rti_cfg3_saved = val64;
+	}
+
+	val64 = 0;
+
+	if (hldev->header.config.intr_mode ==
+	    VXGE_HAL_INTR_MODE_EMULATED_INTA) {
+
+		val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(1) |
+		    VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_EINTA]);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_EINTA]);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_EINTA]);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_BMAP]);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_cfg2_int_num[VXGE_HAL_VPATH_INTR_BMAP]);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u64) 0,
+	    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_BMAP]);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_is_rxdmem_leak - Check for the rxd memory leak.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * The function checks for the rxd memory leak.
+ *
+ */
+u32
+vxge_hal_vpath_is_rxdmem_leak(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	u32 new_qw_count, rxd_spat, bRet = 0;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vp != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vp->vpath->vp_config->ring.enable == VXGE_HAL_RING_DISABLE) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, bRet);
+		return (bRet);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp->vpath->vp_reg->prc_rxd_doorbell);
+
+	new_qw_count = (u32) VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp->vpath->vp_reg->prc_cfg6);
+
+	rxd_spat = (u32) VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(val64);
+
+	bRet = (new_qw_count > (rxd_spat * 3 / 2));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, bRet);
+
+	return (bRet);
+}
+
+/*
+ * vxge_hal_vpath_mtu_check - check MTU value for ranges
+ * @vpath_handle: Virtal path handle
+ * @new_mtu: new MTU value to check
+ *
+ * Will do sanity check for new MTU value.
+ *
+ * Returns: VXGE_HAL_OK - success.
+ * VXGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
+ *
+ * See also: vxge_hal_vpath_mtu_set()
+ */
+vxge_hal_status_e
+vxge_hal_device_mtu_check(vxge_hal_vpath_h vpath_handle,
+    unsigned long new_mtu)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vp == NULL) {
+		vxge_hal_trace_log_vpath(
+		    "<== %s:%s:%d  Result: %d", __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	new_mtu += VXGE_HAL_MAC_HEADER_MAX_SIZE;
+
+	if ((new_mtu < VXGE_HAL_MIN_MTU) || (new_mtu > vp->vpath->max_mtu)) {
+		status = VXGE_HAL_ERR_INVALID_MTU_SIZE;
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_mtu_set - Set MTU.
+ * @vpath_handle: Virtal path handle
+ * @new_mtu: New MTU size to configure.
+ *
+ * Set new MTU value. Example, to use jumbo frames:
+ * vxge_hal_vpath_mtu_set(my_device, 9600);
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_mtu_set(vxge_hal_vpath_h vpath_handle,
+    unsigned long new_mtu)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vp == NULL) {
+		vxge_hal_trace_log_vpath(
+		    "<== %s:%s:%d  Result: %d", __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_INVALID_HANDLE);
+		return (VXGE_HAL_ERR_INVALID_HANDLE);
+	}
+
+	new_mtu += VXGE_HAL_MAC_HEADER_MAX_SIZE;
+
+	if ((new_mtu < VXGE_HAL_MIN_MTU) || (new_mtu > vp->vpath->max_mtu)) {
+		status = VXGE_HAL_ERR_INVALID_MTU_SIZE;
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp->vpath->vp_reg->rxmac_vcfg0);
+
+	val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
+	val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vp->vpath->vp_reg->rxmac_vcfg0);
+
+	vp->vpath->vp_config->mtu = new_mtu - VXGE_HAL_MAC_HEADER_MAX_SIZE;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+
+/*
+ * __hal_vpath_size_quantum_set
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine configures the size quantum of virtual path
+ * using the config passed
+ */
+vxge_hal_status_e
+__hal_vpath_size_quantum_set(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	u64 val64;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	switch (__vxge_os_cacheline_size) {
+	case 8:
+		val64 = 0;
+		break;
+	case 16:
+		val64 = 1;
+		break;
+	case 32:
+		val64 = 2;
+		break;
+	case 64:
+		val64 = 3;
+		break;
+	default:
+	case 128:
+		val64 = 4;
+		break;
+	case 256:
+		val64 = 5;
+		break;
+	case 512:
+		val64 = 6;
+		break;
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->vpath_general_cfg2);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_hw_initialize
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine initializes the registers of virtual path
+ * using the config passed
+ */
+vxge_hal_status_e
+__hal_vpath_hw_initialize(
+    vxge_hal_device_h devh,
+    u32 vp_id)
+{
+	u64 val64;
+	u32 mrrs;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_virtualpath_t *vpath;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vxge_hal_pci_e_capability_t *pci_e_cap;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
+	    (ptr_t) devh, vp_id);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	if (!(hldev->vpath_assignments & mBIT(vp_id))) {
+
+		vxge_hal_trace_log_vpath(
+		    "<== %s:%s:%d  Result: %d", __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+		return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+	}
+
+	status = __hal_vpath_swapper_set((vxge_hal_device_t *) hldev, vp_id);
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_vpath_size_quantum_set(hldev, vp_id);
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_vpath_mac_configure(hldev, vp_id);
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_vpath_kdfc_configure(hldev, vp_id);
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+
+	status = __hal_vpath_tim_configure(hldev, vp_id);
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(
+	    vpath->sess_grps_available),
+	    &vpath->vp_reg->usdc_vpath);
+
+	vxge_os_wmb();
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->qcc_pci_cfg);
+
+	val64 |= VXGE_HAL_QCC_PCI_CFG_ADD_PAD_CQE_SPACE |
+	    VXGE_HAL_QCC_PCI_CFG_ADD_PAD_WQE |
+	    VXGE_HAL_QCC_PCI_CFG_ADD_PAD_SRQIR |
+	    VXGE_HAL_QCC_PCI_CFG_CTL_STR_CQE_SPACE |
+	    VXGE_HAL_QCC_PCI_CFG_CTL_STR_WQE |
+	    VXGE_HAL_QCC_PCI_CFG_CTL_STR_SRQIR;
+
+	if (vpath->vp_config->no_snoop !=
+	    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
+		if (vpath->vp_config->no_snoop) {
+			val64 |= VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE |
+			    VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE |
+			    VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR;
+		} else {
+			val64 &= ~(VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE |
+			    VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE |
+			    VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR);
+		}
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->qcc_pci_cfg);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->h2l_vpath_config);
+
+	if (vpath->vp_config->no_snoop !=
+	    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
+		if (vpath->vp_config->no_snoop) {
+			val64 |= VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP;
+		} else {
+			val64 &= ~VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP;
+		}
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->h2l_vpath_config);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->ph2l_vp_cfg0);
+
+	if (vpath->vp_config->no_snoop !=
+	    VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT) {
+		if (vpath->vp_config->no_snoop) {
+			val64 |= VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA;
+		} else {
+			val64 &= ~VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA;
+		}
+	}
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->ph2l_vp_cfg0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    0,
+	    &vpath->vp_reg->gendma_int);
+
+	pci_e_cap = (vxge_hal_pci_e_capability_t *)
+	    (((char *)&hldev->pci_config_space_bios) + hldev->pci_e_caps);
+
+	mrrs = pci_e_cap->pci_e_devctl >> 12;
+
+	val64 = VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT |
+	    VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(mrrs) |
+	    VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN |
+	    VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(1);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->rtdma_rd_optimization_ctrl);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_vp_initialize - Initialize Virtual Path structure
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ * @config: Configuration for the virtual path
+ *
+ * This routine initializes virtual path using the config passed
+ */
+vxge_hal_status_e
+__hal_vp_initialize(vxge_hal_device_h devh,
+    u32 vp_id,
+    vxge_hal_vp_config_t *config)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert((hldev != NULL) && (config != NULL));
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "devh = 0x"VXGE_OS_STXFMT", vp_id = %d, config = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, vp_id, (ptr_t) config);
+
+	if (!(hldev->vpath_assignments & mBIT(vp_id))) {
+
+		vxge_hal_trace_log_vpath(
+		    "<== %s:%s:%d  Result: %d", __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+		return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE);
+	}
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+	vpath->vp_id = vp_id;
+
+	vpath->vp_open = VXGE_HAL_VP_OPEN;
+
+	vpath->hldev = (__hal_device_t *) devh;
+
+	vpath->vp_config = config;
+
+	vpath->vp_reg = hldev->vpath_reg[vp_id];
+
+	vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
+
+	status = __hal_vpath_hw_reset(devh, vp_id);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_vpath(
+		    "vpath is already in reset  %s:%s:%d",
+		    __FILE__, __func__, __LINE__);
+	}
+
+	status = __hal_vpath_reset_check(vpath);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_os_memzero(vpath, sizeof(__hal_virtualpath_t));
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+
+		return (status);
+	}
+
+	status = __hal_vpath_mgmt_read(hldev, vpath);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_os_memzero(vpath, sizeof(__hal_virtualpath_t));
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vpath->tx_intr_num =
+	    (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_TX;
+
+	vpath->rx_intr_num =
+	    (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_RX;
+
+	vpath->einta_intr_num =
+	    (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_EINTA;
+
+	vpath->bmap_intr_num =
+	    (vp_id * VXGE_HAL_MAX_INTR_PER_VP) + VXGE_HAL_VPATH_INTR_BMAP;
+
+
+#if defined(VXGE_HAL_VP_CBS)
+	vxge_os_spin_lock_init(&vpath->vpath_handles_lock, hldev->pdev);
+#elif defined(VXGE_HAL_VP_CBS_IRQ)
+	vxge_os_spin_lock_init_irq(&vpath->vpath_handles_lock, hldev->irqh);
+#endif
+
+	vxge_list_init(&vpath->vpath_handles);
+
+	vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
+
+	vxge_os_memzero(&vpath->sw_stats->obj_counts,
+	    sizeof(vxge_hal_vpath_sw_obj_count_t));
+
+	VXGE_HAL_DEVICE_TIM_INT_MASK_SET(vpath->hldev, vpath->vp_id);
+
+	status = __hal_vpath_hw_initialize(vpath->hldev, vpath->vp_id);
+
+	if (status != VXGE_HAL_OK) {
+		__hal_vp_terminate(devh, vp_id);
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * __hal_vp_terminate - Terminate Virtual Path structure
+ * @hldev: Handle to the device object
+ * @vp_id: Virtual Path Id
+ *
+ * This routine closes all channels it opened and freeup memory
+ */
+void
+__hal_vp_terminate(vxge_hal_device_h devh, u32 vp_id)
+{
+	__hal_virtualpath_t *vpath;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(devh != NULL);
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "devh = 0x"VXGE_OS_STXFMT", vp_id = %d", (ptr_t) devh, vp_id);
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+
+		vxge_hal_trace_log_vpath(
+		    "<== %s:%s:%d  Result: %d", __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return;
+
+	}
+
+	VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(vpath->hldev, vpath->vp_id);
+
+
+#if defined(VXGE_HAL_VP_CBS)
+	vxge_os_spin_lock_destroy(
+	    &vpath->vpath_handles_lock, hldev->header.pdev);
+#elif defined(VXGE_HAL_VP_CBS_IRQ)
+	vxge_os_spin_lock_destroy_irq(
+	    &vpath->vpath_handles_lock, hldev->header.pdev);
+#endif
+
+	vxge_os_memzero(vpath, sizeof(__hal_virtualpath_t));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+}
+
+
+/*
+ * vxge_hal_vpath_obj_count_get - Get the Object usage count for a given
+ *		 virtual path
+ * @vpath_handle: Virtal path handle
+ * @obj_counts: Buffer to return object counts
+ *
+ * This function returns the object counts for virtual path.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_obj_count_get(
+    vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_sw_obj_count_t *obj_count)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	if ((vpath_handle == NULL) || (obj_count == NULL))
+		return (VXGE_HAL_FAIL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT", "
+	    "obj_count = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle,
+	    (ptr_t) obj_count);
+
+	vxge_os_memcpy(obj_count, &vp->vpath->sw_stats->obj_counts,
+	    sizeof(vxge_hal_vpath_sw_obj_count_t));
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_open - Open a virtual path on a given adapter
+ * @devh: handle to device object
+ * @attr: Virtual path attributes
+ * @cb_fn: Call back to be called to complete an asynchronous function call
+ * @client_handle: handle to be returned in the callback
+ * @vpath_handle: Buffer to return a handle to the vpath
+ *
+ * This function is used to open access to virtual path of an
+ * adapter for offload, LRO and SPDM operations. This function returns
+ * synchronously.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_open(vxge_hal_device_h devh,
+    vxge_hal_vpath_attr_t *attr,
+    vxge_hal_vpath_callback_f cb_fn,
+    vxge_hal_client_h client_handle,
+    vxge_hal_vpath_h *vpath_handle)
+{
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	__hal_virtualpath_t *vpath;
+	__hal_vpath_handle_t *vp;
+	vxge_hal_status_e status;
+
+	vxge_assert((devh != NULL) && (attr != NULL) && (cb_fn != NULL) &&
+	    (vpath_handle != NULL));
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", "
+	    "attr = 0x"VXGE_OS_STXFMT", cb_fn = 0x"VXGE_OS_STXFMT", "
+	    "client_handle = 0x"VXGE_OS_STXFMT", "
+	    "vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) devh, (ptr_t) attr, (ptr_t) cb_fn,
+	    (ptr_t) client_handle, (ptr_t) vpath_handle);
+
+
+	vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[attr->vp_id];
+
+	if (vpath->vp_open == VXGE_HAL_VP_OPEN) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_STATE);
+		return (VXGE_HAL_ERR_INVALID_STATE);
+	}
+
+	status = __hal_vp_initialize(hldev, attr->vp_id,
+	    &hldev->header.config.vp_config[attr->vp_id]);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_err_log_vpath(
+		    "virtual Paths: __hal_vp_initialize failed == > %s : %d",
+		    __func__, __LINE__);
+
+		goto vpath_open_exit1;
+
+	}
+
+	vp = (__hal_vpath_handle_t *) vxge_os_malloc(hldev->header.pdev,
+	    sizeof(__hal_vpath_handle_t));
+
+	if (vp == NULL) {
+
+		status = VXGE_HAL_ERR_OUT_OF_MEMORY;
+
+		goto vpath_open_exit2;
+
+	}
+
+	vxge_os_memzero(vp, sizeof(__hal_vpath_handle_t));
+
+	vp->vpath = vpath;
+	vp->cb_fn = cb_fn;
+	vp->client_handle = client_handle;
+
+
+	if (vp->vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
+
+		status = __hal_fifo_create(vp, &attr->fifo_attr);
+		if (status != VXGE_HAL_OK) {
+			goto vpath_open_exit6;
+		}
+	}
+
+	if (vp->vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
+
+		status = __hal_ring_create(vp, &attr->ring_attr);
+		if (status != VXGE_HAL_OK) {
+			goto vpath_open_exit7;
+		}
+
+		status = __hal_vpath_prc_configure(devh, attr->vp_id);
+		if (status != VXGE_HAL_OK) {
+			goto vpath_open_exit8;
+		}
+	}
+
+
+
+	vp->vpath->stats_block = __hal_blockpool_block_allocate(devh,
+	    VXGE_OS_HOST_PAGE_SIZE);
+
+	if (vp->vpath->stats_block == NULL) {
+
+		status = VXGE_HAL_ERR_OUT_OF_MEMORY;
+
+		goto vpath_open_exit8;
+
+	}
+
+	vp->vpath->hw_stats =
+	    (vxge_hal_vpath_stats_hw_info_t *) vp->vpath->stats_block->memblock;
+
+	vxge_os_memzero(vp->vpath->hw_stats,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
+	    vp->vpath->hw_stats;
+
+	vp->vpath->hw_stats_sav =
+	    &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
+
+	vxge_os_memzero(vp->vpath->hw_stats_sav,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    vp->vpath->stats_block->dma_addr,
+	    &vpath->vp_reg->stats_cfg);
+
+	status = vxge_hal_vpath_hw_stats_enable(vp);
+
+	if (status != VXGE_HAL_OK) {
+
+		goto vpath_open_exit8;
+
+	}
+
+	vxge_list_insert(&vp->item, &vpath->vpath_handles);
+
+	hldev->vpaths_deployed |= mBIT(vpath->vp_id);
+	*vpath_handle = vp;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+
+vpath_open_exit8:
+	if (vpath->ringh != NULL)
+		__hal_ring_delete(vp);
+vpath_open_exit7:
+	if (vpath->fifoh != NULL)
+		__hal_fifo_delete(vp);
+vpath_open_exit6:
+
+	vxge_os_free(hldev->header.pdev, vp,
+	    sizeof(__hal_vpath_handle_t));
+vpath_open_exit2:
+	__hal_vp_terminate(devh, attr->vp_id);
+vpath_open_exit1:
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_id - Get virtual path ID
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function returns virtual path id
+ */
+u32
+vxge_hal_vpath_id(
+    vxge_hal_vpath_h vpath_handle)
+{
+	u32 id;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	id = ((__hal_vpath_handle_t *) vpath_handle)->vpath->vp_id;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (id);
+}
+
+/*
+ * vxge_hal_vpath_close - Close the handle got from previous vpath (vpath) open
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function is used to close access to virtual path opened
+ * earlier.
+ */
+vxge_hal_status_e
+vxge_hal_vpath_close(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_virtualpath_t *vpath;
+	__hal_device_t *hldev;
+	u32 vp_id;
+	u32 is_empty = TRUE;
+
+	vxge_assert(vpath_handle != NULL);
+
+	vpath = (__hal_virtualpath_t *) vp->vpath;
+
+	hldev = (__hal_device_t *) vpath->hldev;
+
+	vp_id = vpath->vp_id;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+#if defined(VXGE_HAL_VP_CBS)
+	vxge_os_spin_lock(&vpath->vpath_handles_lock);
+#elif defined(VXGE_HAL_VP_CBS_IRQ)
+	vxge_os_spin_lock_irq(&vpath->vpath_handles_lock, flags);
+#endif
+
+	vxge_list_remove(&vp->item);
+
+	if (!vxge_list_is_empty(&vpath->vpath_handles)) {
+		vxge_list_insert(&vp->item, &vpath->vpath_handles);
+		is_empty = FALSE;
+	}
+
+#if defined(VXGE_HAL_VP_CBS)
+	vxge_os_spin_unlock(&vpath->vpath_handles_lock);
+#elif defined(VXGE_HAL_VP_CBS_IRQ)
+	vxge_os_spin_unlock_irq(&vpath->vpath_handles_lock, flags);
+#endif
+
+	if (!is_empty) {
+		vxge_hal_err_log_vpath("clients are still attached == > %s : %d",
+		    __func__, __LINE__);
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 1",
+		    __FILE__, __func__, __LINE__);
+		return (VXGE_HAL_FAIL);
+	}
+
+	vpath->hldev->vpaths_deployed &= ~mBIT(vp_id);
+
+	if (vpath->ringh != NULL)
+		__hal_ring_delete(vpath_handle);
+
+	if (vpath->fifoh != NULL)
+		__hal_fifo_delete(vpath_handle);
+
+
+	if (vpath->stats_block != NULL) {
+		__hal_blockpool_block_free(hldev, vpath->stats_block);
+	}
+
+	vxge_os_free(hldev->header.pdev,
+	    vpath_handle, sizeof(__hal_vpath_handle_t));
+
+	__hal_vp_terminate(hldev, vp_id);
+
+	vpath->vp_open = VXGE_HAL_VP_NOT_OPEN;
+
+	(void) __hal_ifmsg_wmsg_post(hldev,
+	    vp_id,
+	    VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST,
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_VPATH_RESET_END,
+	    0);
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_reset - Resets vpath
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function is used to request a reset of vpath
+ */
+vxge_hal_status_e
+vxge_hal_vpath_reset(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+	u32 count = 0, total_count = 0;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vp->vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	vxge_hw_vpath_set_zero_rx_frm_len(hldev, vp->vpath->vp_id);
+
+	vxge_hw_vpath_wait_receive_idle(hldev, vp->vpath->vp_id,
+	    &count, &total_count);
+
+	status = __hal_vpath_hw_reset((vxge_hal_device_h) hldev,
+	    vp->vpath->vp_id);
+
+	if (status == VXGE_HAL_OK)
+		vp->vpath->sw_stats->soft_reset_cnt++;
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_reset_poll - Poll for reset complete
+ * @vpath_handle: Handle got from previous vpath open
+ *
+ * This function is used to poll for the vpath reset completion
+ */
+vxge_hal_status_e
+vxge_hal_vpath_reset_poll(
+    vxge_hal_vpath_h vpath_handle)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_vpath("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	if (vp->vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	status = __hal_vpath_reset_check(vp->vpath);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d Result = %d",
+		    __FILE__, __func__, __LINE__, status);
+
+		return (status);
+	}
+
+	status = __hal_vpath_sw_reset((vxge_hal_device_h) hldev,
+	    vp->vpath->vp_id);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	vxge_os_memzero(vp->vpath->sw_stats,
+	    sizeof(vxge_hal_vpath_stats_sw_info_t));
+
+	status = __hal_vpath_hw_initialize((vxge_hal_device_h) hldev,
+	    vp->vpath->vp_id);
+
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	if (vp->vpath->ringh != NULL) {
+
+		status = __hal_vpath_prc_configure(
+		    (vxge_hal_device_h) hldev,
+		    vp->vpath->vp_id);
+
+		if (status != VXGE_HAL_OK) {
+			vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+			    __FILE__, __func__, __LINE__, status);
+			return (status);
+		}
+	}
+
+	vxge_os_memzero(vp->vpath->hw_stats,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	vxge_os_memzero(vp->vpath->hw_stats_sav,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    vp->vpath->stats_block->dma_addr,
+	    &vp->vpath->vp_reg->stats_cfg);
+
+
+	status = vxge_hal_vpath_hw_stats_enable(vp);
+
+	if (status != VXGE_HAL_OK) {
+
+		vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+
+	}
+
+	vxge_hal_trace_log_vpath("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_hw_stats_enable - Enable vpath h/wstatistics.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Enable the DMA vpath statistics. The function is to be called to re-enable
+ * the adapter to update stats into the host memory
+ *
+ * See also: vxge_hal_vpath_hw_stats_disable(), vxge_hal_vpath_hw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_hw_stats_enable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	vpath = vp->vpath;
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	vxge_os_memcpy(vpath->hw_stats_sav,
+	    vpath->hw_stats,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	if (hldev->header.config.stats_read_method ==
+	    VXGE_HAL_STATS_READ_METHOD_DMA) {
+		val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &hldev->common_reg->stats_cfg0);
+
+		val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE(
+		    (1 << (16 - vpath->vp_id)));
+
+		vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+		    hldev->header.regh0,
+		    (u32) bVAL32(val64, 0),
+		    &hldev->common_reg->stats_cfg0);
+	} else {
+		status = __hal_vpath_hw_stats_get(
+		    vpath,
+		    vpath->hw_stats);
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_hw_stats_disable - Disable vpath h/w statistics.
+ * @vpath_handle: Virtual Path handle.
+ *
+ * Enable the DMA vpath statistics. The function is to be called to disable
+ * the adapter to update stats into the host memory. This function is not
+ * needed to be called, normally.
+ *
+ * See also: vxge_hal_vpath_hw_stats_enable(), vxge_hal_vpath_hw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_hw_stats_disable(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "vpath = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
+
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->stats_cfg0);
+
+	val64 &= ~VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - vpath->vp_id)));
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &hldev->common_reg->stats_cfg0);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_hw_stats_get - Get the vpath hw statistics.
+ * @vpath_handle: Virtual Path handle.
+ * @hw_stats: Hardware stats
+ *
+ * Returns the vpath h/w stats.
+ *
+ * See also: vxge_hal_vpath_hw_stats_enable(),
+ * vxge_hal_vpath_hw_stats_disable()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_hw_stats_get(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_stats_hw_info_t *hw_stats)
+{
+	__hal_virtualpath_t *vpath;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (hw_stats != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "vpath = 0x"VXGE_OS_STXFMT", hw_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) hw_stats);
+
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &hldev->common_reg->stats_cfg0,
+	    0,
+	    VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - vpath->vp_id))),
+	    hldev->header.config.device_poll_millis);
+
+	if (status == VXGE_HAL_OK) {
+		vxge_os_memcpy(hw_stats,
+		    vpath->hw_stats,
+		    sizeof(vxge_hal_vpath_stats_hw_info_t));
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_sw_stats_get - Get the vpath sw statistics.
+ * @vpath_handle: Virtual Path handle.
+ * @sw_stats: Software stats
+ *
+ * Returns the vpath s/w stats.
+ *
+ * See also: vxge_hal_vpath_hw_stats_get()
+ */
+vxge_hal_status_e
+vxge_hal_vpath_sw_stats_get(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_vpath_stats_sw_info_t *sw_stats)
+{
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert((vpath_handle != NULL) && (sw_stats != NULL));
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "vpath = 0x"VXGE_OS_STXFMT", sw_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle, (ptr_t) sw_stats);
+
+	vpath = (__hal_virtualpath_t *)
+	    ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	if (hldev->header.traffic_intr_cnt) {
+		int intrcnt = hldev->header.traffic_intr_cnt;
+
+		if (!intrcnt)
+			intrcnt = 1;
+
+		vpath->sw_stats->fifo_stats.common_stats.avg_compl_per_intr_cnt =
+		    vpath->sw_stats->fifo_stats.common_stats.total_compl_cnt / intrcnt;
+
+		if (vpath->sw_stats->fifo_stats.common_stats.avg_compl_per_intr_cnt ==
+		    0) {
+			/* to not confuse user */
+			vpath->sw_stats->fifo_stats.common_stats.avg_compl_per_intr_cnt = 1;
+		}
+
+		vpath->sw_stats->ring_stats.common_stats.avg_compl_per_intr_cnt =
+		    vpath->sw_stats->ring_stats.common_stats.total_compl_cnt / intrcnt;
+
+		if (vpath->sw_stats->ring_stats.common_stats.avg_compl_per_intr_cnt ==
+		    0) {
+			/* to not confuse user */
+			vpath->sw_stats->ring_stats.common_stats.avg_compl_per_intr_cnt = 1;
+		}
+	}
+
+	if (vpath->sw_stats->fifo_stats.total_posts) {
+		vpath->sw_stats->fifo_stats.avg_buffers_per_post =
+		    vpath->sw_stats->fifo_stats.total_buffers /
+		    vpath->sw_stats->fifo_stats.total_posts;
+
+		vpath->sw_stats->fifo_stats.avg_post_size =
+		    (u32) (vpath->hw_stats->tx_stats.tx_ttl_eth_octets /
+		    vpath->sw_stats->fifo_stats.total_posts);
+	}
+
+	if (vpath->sw_stats->fifo_stats.total_buffers) {
+		vpath->sw_stats->fifo_stats.avg_buffer_size =
+		    (u32) (vpath->hw_stats->tx_stats.tx_ttl_eth_octets /
+		    vpath->sw_stats->fifo_stats.total_buffers);
+	}
+
+	vxge_os_memcpy(sw_stats,
+	    vpath->sw_stats,
+	    sizeof(vxge_hal_vpath_stats_sw_info_t));
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_stats_access - Get the statistics from the given location
+ *			  and offset and perform an operation
+ * @vpath: Virtual path.
+ * @operation: Operation to be performed
+ * @location: Location (one of vpath id, aggregate or port)
+ * @offset: Offset with in the location
+ * @stat: Pointer to a buffer to return the value
+ *
+ * Get the statistics from the given location and offset.
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_stats_access(
+    __hal_virtualpath_t *vpath,
+    u32 operation,
+    u32 offset,
+    u64 *stat)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	val64 = VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(operation) |
+	    VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE |
+	    VXGE_HAL_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
+
+	vxge_hal_pio_mem_write32_lower(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 32),
+	    &vpath->vp_reg->xmac_stats_access_cmd);
+	vxge_os_wmb();
+
+	vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
+	    hldev->header.regh0,
+	    (u32) bVAL32(val64, 0),
+	    &vpath->vp_reg->xmac_stats_access_cmd);
+	vxge_os_wmb();
+
+	status = vxge_hal_device_register_poll(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->xmac_stats_access_cmd,
+	    0,
+	    VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE,
+	    hldev->header.config.device_poll_millis);
+
+	if ((status == VXGE_HAL_OK) && (operation == VXGE_HAL_STATS_OP_READ)) {
+
+		*stat = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vpath->vp_reg->xmac_stats_access_data);
+
+	} else {
+		*stat = 0;
+	}
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_stats_access
+ * Get statistics from given location and offset to perform an operation
+ * @vpath_handle: Virtual path handle.
+ * @operation: Operation to be performed
+ * @offset: Offset with in the location
+ * @stat: Pointer to a buffer to return the value
+ *
+ * Get the statistics from the given location and offset.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_stats_access(
+    vxge_hal_vpath_h vpath_handle,
+    u32 operation,
+    u32 offset,
+    u64 *stat)
+{
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "vpath_handle = 0x"VXGE_OS_STXFMT, (ptr_t) vpath_handle);
+
+	status = __hal_vpath_stats_access(vp->vpath,
+	    operation,
+	    offset,
+	    stat);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
+ * @vpath: vpath
+ * @vpath_tx_stats: Buffer to return TX Statistics of vpath.
+ *
+ * Get the TX Statistics of a vpath
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_xmac_tx_stats_get(__hal_virtualpath_t *vpath,
+    vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__,
+		    __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_TTL_ETH_FRMS_OFFSET);
+
+	vpath_tx_stats->tx_ttl_eth_frms =
+	    VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_TTL_ETH_OCTETS_OFFSET);
+
+	vpath_tx_stats->tx_ttl_eth_octets =
+	    VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_DATA_OCTETS_OFFSET);
+
+	vpath_tx_stats->tx_data_octets =
+	    VXGE_HAL_STATS_GET_VPATH_TX_DATA_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_MCAST_FRMS_OFFSET);
+
+	vpath_tx_stats->tx_mcast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_TX_MCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_BCAST_FRMS_OFFSET);
+
+	vpath_tx_stats->tx_bcast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_TX_BCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_UCAST_FRMS_OFFSET);
+
+	vpath_tx_stats->tx_ucast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_TX_UCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_TAGGED_FRMS_OFFSET);
+
+	vpath_tx_stats->tx_tagged_frms =
+	    VXGE_HAL_STATS_GET_VPATH_TX_TAGGED_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_TX_VLD_IP_OFFSET);
+
+	vpath_tx_stats->tx_vld_ip =
+	    VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_VLD_IP_OCTETS_OFFSET);
+
+	vpath_tx_stats->tx_vld_ip_octets =
+	    VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_TX_ICMP_OFFSET);
+
+	vpath_tx_stats->tx_icmp =
+	    VXGE_HAL_STATS_GET_VPATH_TX_ICMP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_TX_TCP_OFFSET);
+
+	vpath_tx_stats->tx_tcp =
+	    VXGE_HAL_STATS_GET_VPATH_TX_TCP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_RST_TCP_OFFSET);
+
+	vpath_tx_stats->tx_rst_tcp =
+	    VXGE_HAL_STATS_GET_VPATH_TX_RST_TCP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_UDP_OFFSET);
+
+	vpath_tx_stats->tx_udp =
+	    VXGE_HAL_STATS_GET_VPATH_TX_UDP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_LOST_IP_OFFSET);
+
+	vpath_tx_stats->tx_lost_ip =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_UNKNOWN_PROTOCOL_OFFSET);
+
+	vpath_tx_stats->tx_unknown_protocol =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_TX_UNKNOWN_PROTOCOL(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_PARSE_ERROR_OFFSET);
+
+	vpath_tx_stats->tx_parse_error =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_TX_PARSE_ERROR(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_TCP_OFFLOAD_OFFSET);
+
+	vpath_tx_stats->tx_tcp_offload =
+	    VXGE_HAL_STATS_GET_VPATH_TX_TCP_OFFLOAD(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_RETX_TCP_OFFLOAD_OFFSET);
+
+	vpath_tx_stats->tx_retx_tcp_offload =
+	    VXGE_HAL_STATS_GET_VPATH_TX_RETX_TCP_OFFLOAD(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_TX_LOST_IP_OFFLOAD_OFFSET);
+
+	vpath_tx_stats->tx_lost_ip_offload =
+	    VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP_OFFLOAD(val64);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * __hal_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
+ * @vpath: vpath
+ * @vpath_rx_stats: Buffer to return RX Statistics of vpath.
+ *
+ * Get the RX Statistics of a vpath
+ *
+ */
+vxge_hal_status_e
+__hal_vpath_xmac_rx_stats_get(__hal_virtualpath_t *vpath,
+    vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath != NULL);
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__,
+		    VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_ETH_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_eth_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_VLD_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_vld_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_VLD_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_OFFLOAD_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_offload_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_ETH_OCTETS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_eth_octets =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_DATA_OCTETS_OFFSET);
+
+	vpath_rx_stats->rx_data_octets =
+	    VXGE_HAL_STATS_GET_VPATH_RX_DATA_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_OFFLOAD_OCTETS_OFFSET);
+
+	vpath_rx_stats->rx_offload_octets =
+	    VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_VLD_MCAST_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_vld_mcast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_VLD_MCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_VLD_BCAST_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_vld_bcast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_VLD_BCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_ACC_UCAST_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_accepted_ucast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_ACC_UCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_ACC_NUCAST_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_accepted_nucast_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_ACC_NUCAST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TAGGED_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_tagged_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TAGGED_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_LONG_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_long_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_LONG_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_USIZED_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_usized_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_USIZED_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_OSIZED_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_osized_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_OSIZED_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_FRAG_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_frag_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_FRAG_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_JABBER_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_jabber_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_JABBER_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_64_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_64_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_64_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_65_127_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_65_127_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_65_127_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_128_255_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_128_255_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_128_255_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_256_511_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_256_511_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_256_511_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_512_1023_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_512_1023_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_512_1023_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_1024_1518_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_1024_1518_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_1024_1518_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_1519_4095_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_1519_4095_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_1519_4095_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_4096_8191_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_4096_8191_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_4096_8191_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_8192_MAX_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_8192_max_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_8192_MAX_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_TTL_GT_MAX_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_ttl_gt_max_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TTL_GT_MAX_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_IP_OFFSET);
+
+	vpath_rx_stats->rx_ip =
+	    VXGE_HAL_STATS_GET_VPATH_RX_IP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ACC_IP_OFFSET);
+
+	vpath_rx_stats->rx_accepted_ip =
+	    VXGE_HAL_STATS_GET_VPATH_RX_ACC_IP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_IP_OCTETS_OFFSET);
+
+	vpath_rx_stats->rx_ip_octets =
+	    VXGE_HAL_STATS_GET_VPATH_RX_IP_OCTETS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ERR_IP_OFFSET);
+
+	vpath_rx_stats->rx_err_ip =
+	    VXGE_HAL_STATS_GET_VPATH_RX_ERR_IP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ICMP_OFFSET);
+
+	vpath_rx_stats->rx_icmp =
+	    VXGE_HAL_STATS_GET_VPATH_RX_ICMP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_TCP_OFFSET);
+
+	vpath_rx_stats->rx_tcp =
+	    VXGE_HAL_STATS_GET_VPATH_RX_TCP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_UDP_OFFSET);
+
+	vpath_rx_stats->rx_udp =
+	    VXGE_HAL_STATS_GET_VPATH_RX_UDP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_ERR_TCP_OFFSET);
+
+	vpath_rx_stats->rx_err_tcp =
+	    VXGE_HAL_STATS_GET_VPATH_RX_ERR_TCP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_LOST_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_lost_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_LOST_FRMS(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(VXGE_HAL_STATS_VPATH_RX_LOST_IP_OFFSET);
+
+	vpath_rx_stats->rx_lost_ip =
+	    VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_LOST_IP_OFFLOAD_OFFSET);
+
+	vpath_rx_stats->rx_lost_ip_offload =
+	    VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP_OFFLOAD(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_QUEUE_FULL_DISCARD_OFFSET);
+
+	vpath_rx_stats->rx_queue_full_discard =
+	    (u16) VXGE_HAL_STATS_GET_VPATH_RX_QUEUE_FULL_DISCARD(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_RED_DISCARD_OFFSET);
+
+	vpath_rx_stats->rx_red_discard =
+	    (u16) VXGE_HAL_STATS_GET_VPATH_RX_RED_DISCARD(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_SLEEP_DISCARD_OFFSET);
+
+	vpath_rx_stats->rx_sleep_discard =
+	    (u16) VXGE_HAL_STATS_GET_VPATH_RX_SLEEP_DISCARD(val64);
+
+	vpath_rx_stats->rx_various_discard =
+	    vpath_rx_stats->rx_queue_full_discard;
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_RX_MPA_OK_FRMS_OFFSET);
+
+	vpath_rx_stats->rx_mpa_ok_frms =
+	    VXGE_HAL_STATS_GET_VPATH_RX_MPA_OK_FRMS(val64);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: 0",
+	    __FILE__, __func__, __LINE__);
+	return (VXGE_HAL_OK);
+}
+
+/*
+ * vxge_hal_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
+ * @vpath_handle: vpath handle.
+ * @vpath_tx_stats: Buffer to return TX Statistics of vpath.
+ *
+ * Get the TX Statistics of a vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_xmac_tx_stats_get(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_xmac_tx_stats_get(vp->vpath, vpath_tx_stats);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
+ * @vpath_handle: vpath handle.
+ * @vpath_rx_stats: Buffer to return RX Statistics of vpath.
+ *
+ * Get the RX Statistics of a vpath
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_xmac_rx_stats_get(vxge_hal_vpath_h vpath_handle,
+    vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats)
+{
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert(vpath_handle != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath_handle = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	status = __hal_vpath_xmac_rx_stats_get(vp->vpath, vpath_rx_stats);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * __hal_vpath_hw_stats_get - Get the vpath hw statistics.
+ * @vpath: Virtual Path.
+ * @hw_stats: Hardware stats
+ *
+ * Returns the vpath h/w stats.
+ *
+ * See also: vxge_hal_vpath_hw_stats_enable(),
+ * vxge_hal_vpath_hw_stats_disable()
+ */
+vxge_hal_status_e
+__hal_vpath_hw_stats_get(__hal_virtualpath_t *vpath,
+    vxge_hal_vpath_stats_hw_info_t *hw_stats)
+{
+	u64 val64;
+	__hal_device_t *hldev;
+	vxge_hal_status_e status;
+
+	vxge_assert((vpath != NULL) && (hw_stats != NULL));
+
+	hldev = vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats(
+	    "vpath = 0x"VXGE_OS_STXFMT", hw_stats = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath, (ptr_t) hw_stats);
+
+	if (vpath->vp_open == VXGE_HAL_VP_NOT_OPEN) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, VXGE_HAL_ERR_VPATH_NOT_OPEN);
+		return (VXGE_HAL_ERR_VPATH_NOT_OPEN);
+	}
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats0);
+
+	hw_stats->ini_num_mwr_sent =
+	    (u32) VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats1);
+
+	hw_stats->ini_num_mrd_sent =
+	    (u32) VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats2);
+
+	hw_stats->ini_num_cpl_rcvd =
+	    (u32) VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats3);
+
+	hw_stats->ini_num_mwr_byte_sent =
+	    VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats4);
+
+	hw_stats->ini_num_cpl_byte_rcvd =
+	    VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats5);
+
+	hw_stats->wrcrdtarb_xoff =
+	    (u32) VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_debug_stats6);
+
+	hw_stats->rdcrdtarb_xoff =
+	    (u32) VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_genstats_count01);
+
+	hw_stats->vpath_genstats_count0 =
+	    (u32) VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
+	    val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_genstats_count01);
+
+	hw_stats->vpath_genstats_count1 =
+	    (u32) VXGE_HAL_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
+	    val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_genstats_count23);
+
+	hw_stats->vpath_genstats_count2 =
+	    (u32) VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
+	    val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_genstats_count01);
+
+	hw_stats->vpath_genstats_count3 =
+	    (u32) VXGE_HAL_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
+	    val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_genstats_count4);
+
+	hw_stats->vpath_genstats_count4 =
+	    (u32) VXGE_HAL_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
+	    val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->vpath_genstats_count5);
+
+	hw_stats->vpath_genstats_count5 = (u32)
+	    VXGE_HAL_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
+	    val64);
+
+	status = __hal_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	status = __hal_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
+	if (status != VXGE_HAL_OK) {
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+		    __FILE__, __func__, __LINE__, status);
+		return (status);
+	}
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
+
+	hw_stats->prog_event_vnum0 =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
+
+	hw_stats->prog_event_vnum1 =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
+
+	VXGE_HAL_VPATH_STATS_PIO_READ(
+	    VXGE_HAL_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
+
+	hw_stats->prog_event_vnum2 =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
+
+	hw_stats->prog_event_vnum3 =
+	    (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rx_multi_cast_stats);
+
+	hw_stats->rx_multi_cast_frame_discard =
+	    (u16) VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rx_frm_transferred);
+
+	hw_stats->rx_frm_transferred =
+	    (u32) VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->rxd_returned);
+
+	hw_stats->rxd_returned =
+	    (u16) VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(val64);
+
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->dbg_stats_rx_mpa);
+
+	hw_stats->rx_mpa_len_fail_frms =
+	    (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
+	hw_stats->rx_mpa_mrk_fail_frms =
+	    (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
+	hw_stats->rx_mpa_crc_fail_frms =
+	    (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->dbg_stats_rx_fau);
+
+	hw_stats->rx_permitted_frms =
+	    (u16) VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
+	hw_stats->rx_vp_reset_discarded_frms = (u16)
+	    VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
+	hw_stats->rx_wol_frms =
+	    (u16) VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vpath->vp_reg->tx_vp_reset_discarded_frms);
+
+	hw_stats->tx_vp_reset_discarded_frms = (u16)
+	    VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
+	    val64);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_vpath_stats_clear - Clear all the statistics of vpath
+ * @vpath_handle: Virtual path handle.
+ *
+ * Clear the statistics of the given vpath.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_vpath_stats_clear(vxge_hal_vpath_h vpath_handle)
+{
+	u64 stat;
+	vxge_hal_status_e status;
+	__hal_device_t *hldev;
+	__hal_vpath_handle_t *vp = (__hal_vpath_handle_t *) vpath_handle;
+
+	vxge_assert(vp != NULL);
+
+	hldev = vp->vpath->hldev;
+
+	vxge_hal_trace_log_stats("==> %s:%s:%d",
+	    __FILE__, __func__, __LINE__);
+
+	vxge_hal_trace_log_stats("vpath = 0x"VXGE_OS_STXFMT,
+	    (ptr_t) vpath_handle);
+
+	vxge_os_memcpy(vp->vpath->hw_stats_sav,
+	    vp->vpath->hw_stats,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	vxge_os_memzero(vp->vpath->hw_stats,
+	    sizeof(vxge_hal_vpath_stats_hw_info_t));
+
+	vxge_os_memzero(vp->vpath->sw_stats,
+	    sizeof(vxge_hal_vpath_stats_sw_info_t));
+
+	status = vxge_hal_vpath_stats_access(
+	    vpath_handle,
+	    VXGE_HAL_STATS_OP_CLEAR_ALL_VPATH_STATS,
+	    0,
+	    &stat);
+
+	vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",
+	    __FILE__, __func__, __LINE__, status);
+
+	return (status);
+}
+
+
+/*
+ * vxge_hal_set_fw_api - Setup FW api
+ * @devh: Device Handle.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_set_fw_api(vxge_hal_device_h devh,
+    u64 vp_id, u32 action, u32 offset,
+    u64 data0, u64 data1)
+{
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	u64 val64;
+	u32 fw_memo = VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vxge_assert(hldev != NULL);
+
+	/* Assumption: Privileged vpath is zero */
+	vp_reg = hldev->vpath_reg[vp_id];
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0, data0,
+	    &vp_reg->rts_access_steer_data0);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0, data1,
+	    &vp_reg->rts_access_steer_data1);
+
+	vxge_os_wmb();
+
+	val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE;
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0, val64,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	vxge_os_wmb();
+
+	status =
+	    vxge_hal_device_register_poll(
+	    hldev->header.pdev, hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl, 0,
+	    VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE,
+	    WAIT_FACTOR * hldev->header.config.device_poll_millis);
+
+	if (status != VXGE_HAL_OK)
+		return (VXGE_HAL_FAIL);
+
+	val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_ctrl);
+
+	if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)
+		status = VXGE_HAL_OK;
+	else
+		status = VXGE_HAL_FAIL;
+
+	return (status);
+}
+
+/*
+ * vxge_hal_get_active_config - Get active configuration
+ * @devh: Device Handle.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_get_active_config(vxge_hal_device_h devh,
+    vxge_hal_xmac_nwif_actconfig req_config,
+    u64 *cur_config)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_Get_Active_Config;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_assert(hldev != NULL);
+
+	/* Assumption: Privileged vpath is zero */
+	vp_reg = hldev->vpath_reg[0];
+
+	/* get port mode */
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd) | req_config;
+	action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+	if (status == VXGE_HAL_OK) {
+		*cur_config = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vp_reg->rts_access_steer_data1);
+	}
+
+	return (status);
+}
+
+/*
+ * vxge_hal_set_port_mode - Set dual port mode
+ * override the default dual port mode
+ * @devh: Device Handle.
+ *
+ */
+vxge_hal_status_e
+vxge_hal_set_port_mode(vxge_hal_device_h devh,
+    vxge_hal_xmac_nwif_dp_mode port_mode)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_SetMode;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	if ((port_mode < VXGE_HAL_DP_NP_MODE_DEFAULT) ||
+	    (port_mode > VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT)) {
+
+		vxge_os_printf("Invalid port mode : %d\n", port_mode);
+		return (VXGE_HAL_ERR_INVALID_DP_MODE);
+	}
+
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
+	data1 = port_mode;
+	action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+
+	return (status);
+}
+
+/*
+ * vxge_hal_set_port_mode - Set dual port mode
+ * change behavior on failure *
+ * @devh: Device Handle.
+ */
+vxge_hal_status_e
+vxge_hal_set_behavior_on_failure(vxge_hal_device_h devh,
+    vxge_hal_xmac_nwif_behavior_on_failure behave_on_failure)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_CfgSetBehaviourOnFailure;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	if ((behave_on_failure < VXGE_HAL_XMAC_NWIF_OnFailure_NoMove) ||
+	    (behave_on_failure >
+	    VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore)) {
+		vxge_os_printf("Invalid setting for failure behavior : %d\n",
+		    behave_on_failure);
+
+		return (VXGE_HAL_FAIL);
+	}
+
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
+	data1 = behave_on_failure;
+	action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_PORT_CTRL;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_set_l2switch_mode(vxge_hal_device_h devh,
+    enum vxge_hal_xmac_nwif_l2_switch_status l2_switch)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_L2SwitchEnable;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	if ((l2_switch < VXGE_HAL_XMAC_NWIF_L2_SWITCH_DISABLE) ||
+	    (l2_switch > VXGE_HAL_XMAC_NWIF_L2_SWITCH_ENABLE)) {
+		vxge_os_printf("Invalid setting for failure behavior : %d\n",
+		    l2_switch);
+
+		return (VXGE_HAL_ERR_INVALID_L2_SWITCH_STATE);
+	}
+
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
+	data1 = l2_switch;
+	action = VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+
+	return (status);
+}
+
+/* Get function mode */
+vxge_hal_status_e
+vxge_hal_func_mode_get(vxge_hal_device_h devh, u32 *func_mode)
+{
+	int vp_id;
+	u32 action;
+	u64 val64;
+
+	vxge_hal_status_e status = VXGE_HAL_OK;
+	vxge_hal_vpath_reg_t *vp_reg;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_assert(hldev != NULL);
+	/* get the first vpath number assigned to this function */
+	vp_id = hldev->first_vp_id;
+
+	vp_reg = hldev->vpath_reg[vp_id];
+	action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_MODE;
+
+	status = vxge_hal_set_fw_api(devh, vp_id, action, 0x0, 0x0, 0x0);
+	if (status == VXGE_HAL_OK) {
+		val64 = vxge_os_pio_mem_read64(
+		    hldev->header.pdev, hldev->header.regh0,
+		    &vp_reg->rts_access_steer_data0);
+
+		*func_mode =
+		    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(val64);
+	}
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_func_mode_count(vxge_hal_device_h devh, u32 func_mode, u32 *num_funcs)
+{
+	int vp_id;
+	u32 action;
+	u64 val64, data0;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vp_id = hldev->first_vp_id;
+	vp_reg = hldev->vpath_reg[0];
+
+	data0 = func_mode;
+	action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_GET_FUNC_COUNT;
+
+	status = vxge_hal_set_fw_api(devh, vp_id, action, 0x0, data0, 0x0);
+	if (status == VXGE_HAL_OK) {
+
+		val64 = vxge_os_pio_mem_read64(
+		    hldev->header.pdev, hldev->header.regh0,
+		    &vp_reg->rts_access_steer_data0);
+
+		*num_funcs = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(val64);
+	}
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_config_vpath_map(vxge_hal_device_h devh, u64 port_map)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 cmd = VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_VPathVector;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	action = VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF;
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(cmd);
+	data1 = port_map;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_get_vpath_mask(vxge_hal_device_h devh,
+    u32 vf_id, u32 * num_vp, u64 * data1)
+{
+	u32 action, vhn = 0;
+	u64 data0 = 0x0;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vp_reg = hldev->vpath_reg[0];
+
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_VFID(vf_id) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_VHN(vhn);
+
+	action = VXGE_HAL_PRIV_VPATH_ACTION;
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, 0x0);
+	if (status == VXGE_HAL_OK) {
+
+		data0 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vp_reg->rts_access_steer_data0);
+
+		*num_vp = (u32) ((data0 >> 16) & 0xFF);
+		*data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
+		    hldev->header.regh0,
+		    &vp_reg->rts_access_steer_data1);
+	}
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_get_vpath_list(vxge_hal_device_h devh, u32 vf_id,
+    u64 *vpath_list, u32 *vpath_count)
+{
+	u32 i, j = 0;
+	u64 pos, vpath_mask;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	*vpath_count = 0;
+
+	status = vxge_hal_get_vpath_mask(devh, vf_id, vpath_count, &vpath_mask);
+	if (status == VXGE_HAL_OK) {
+		for (i = VXGE_HAL_VPATH_BMAP_END;
+		    i >= VXGE_HAL_VPATH_BMAP_START; i--) {
+			if (bVAL1(vpath_mask, i)) {
+				pos = VXGE_HAL_VPATH_BMAP_END - i;
+				vpath_list[j] = pos;
+				j++;
+			}
+		}
+	}
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_rx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id)
+{
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 action, bandwidth, priority, set = 0;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vp_reg = hldev->vpath_reg[0];
+	action = VXGE_HAL_BW_CONTROL;
+
+	bandwidth =
+	    ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].bandwidth;
+
+	priority =
+	    ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].priority;
+
+	/*
+	 * Get bandwidth and priority settings
+	 * and perform read-modify-write operation
+	 */
+	data0 = 1;
+	data0 |= vp_id << 32;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+	if (status != VXGE_HAL_OK)
+		goto _exit;
+
+	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_data1);
+
+	/* Set */
+	data0 = 0;
+	data0 |= vp_id << 32;
+
+	/* Rx Bandwidth */
+	if (bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) {
+		set = 1;
+		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(0xff);
+		bandwidth = (bandwidth * 256) / 10000;
+		data1 |=
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(bandwidth);
+		data1 |= VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(1);
+	}
+
+	/* Priority */
+	if (priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) {
+		set = 1;
+		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(0x7);
+		data1 |=
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(priority);
+	}
+
+	if (set == 1)
+		status = vxge_hal_set_fw_api(devh, 0, action,
+		    0x0, data0, data1);
+
+_exit:
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_tx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id)
+{
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 action, bandwidth, priority, set = 0;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vp_reg = hldev->vpath_reg[0];
+	action = VXGE_HAL_BW_CONTROL;
+
+	bandwidth =
+	    ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].bandwidth;
+
+	priority =
+	    ((vxge_hal_device_t *) (devh))->config.vp_config[vp_id].priority;
+
+	/*
+	 * Get bandwidth and priority settings and
+	 * perform a read-modify-write operation
+	 */
+	data0 = 1;
+	data0 |= vp_id << 32;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+	if (status != VXGE_HAL_OK)
+		goto _exit;
+
+	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_data1);
+
+	/* Set */
+	data0 = 0;
+	data0 |= vp_id << 32;
+
+	/* Tx Bandwidth */
+	if (bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) {
+		set = 1;
+		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(0xff);
+		bandwidth = (bandwidth * 256) / 10000;
+		data1 |=
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(bandwidth);
+	}
+
+	/* Priority */
+	if (priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) {
+		set = 1;
+		data1 &= ~VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(0x7);
+		data1 |=
+		    VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(priority);
+	}
+
+	if (set == 1)
+		status = vxge_hal_set_fw_api(devh, 0, action,
+		    0x0, data0, data1);
+
+_exit:
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_bw_priority_get(vxge_hal_device_h devh, u64 vp_id,
+    u32 *bandwidth, u32 *priority)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+	vp_reg = hldev->vpath_reg[0];
+	action = VXGE_HAL_BW_CONTROL;
+
+	/* Get rx bandwidth and rx priority settings */
+	data0 = 1;
+	data0 |= vp_id << 32;
+
+	status = vxge_hal_set_fw_api(devh, 0, action, 0x0, data0, data1);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_data1);
+
+	*priority = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(data1);
+
+	/*
+	 * Bandwidth setting is stored in increments of approx. 39 Mb/s
+	 * so revert it back to get the b/w value
+	 */
+	*bandwidth = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(data1);
+	*bandwidth = ((*bandwidth) * 10000) / 256;
+
+	return (status);
+}
+
+vxge_hal_status_e
+vxge_hal_vf_rx_bw_get(vxge_hal_device_h devh, u64 func_id,
+    u32 *bandwidth, u32 *priority)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	__hal_device_t *hldev = (__hal_device_t *) devh;
+
+	vxge_hal_vpath_reg_t *vp_reg;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	vp_reg = hldev->vpath_reg[func_id];
+	action = VXGE_HAL_RTS_ACCESS_FW_MEMO_ACTION_NON_PRIV_BANDWIDTH_CTRL;
+
+	/* Get rx bandwidth and rx priority settings */
+	data0 = 3;
+	data0 |= func_id << 32;
+
+	status = vxge_hal_set_fw_api(devh, func_id, action, 0x0, data0, data1);
+	if (status != VXGE_HAL_OK)
+		return (status);
+
+	data1 = vxge_os_pio_mem_read64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    &vp_reg->rts_access_steer_data1);
+
+	*priority =
+	    (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(data1);
+
+	/*
+	 * Bandwidth setting is stored in increments of approx. 39 Mb/s
+	 * so revert it back to get the b/w value
+	 */
+	*bandwidth = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(data1);
+	*bandwidth = ((*bandwidth) * 10000) / 256;
+
+	return (status);
+}
+
+void
+vxge_hal_vpath_dynamic_tti_rtimer_set(vxge_hal_vpath_h vpath_handle,
+    u32 timer_val)
+{
+	u64 val64, timer;
+
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	val64 = vpath->tim_tti_cfg3_saved;
+	timer = (timer_val * 1000) / 272;
+
+	val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
+	if (timer)
+		val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
+		    VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+	/*
+	 * tti_cfg3_saved is not updated again because it is
+	 * initialized at one place only - init time.
+	 */
+}
+
+void
+vxge_hal_vpath_dynamic_rti_rtimer_set(vxge_hal_vpath_h vpath_handle,
+    u32 timer_val)
+{
+	u64 val64, timer;
+
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	val64 = vpath->tim_rti_cfg3_saved;
+	timer = (timer_val * 1000) / 272;
+
+	val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
+	if (timer)
+		val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
+		    VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
+
+	vxge_os_pio_mem_write64(hldev->header.pdev,
+	    hldev->header.regh0,
+	    val64,
+	    &vpath->vp_reg->tim_cfg3_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+	/*
+	 * rti_cfg3_saved is not updated again because it is
+	 * initialized at one place only - init time.
+	 */
+}
+
+void
+vxge_hal_vpath_tti_ci_set(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
+		if (vpath->vp_config->tti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_ENABLE) {
+			vpath->vp_config->tti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+			vpath->tim_rti_cfg1_saved = val64;
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
+		}
+	}
+}
+
+void
+vxge_hal_vpath_tti_ci_reset(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	if (vpath->vp_config->fifo.enable == VXGE_HAL_FIFO_ENABLE) {
+		if (vpath->vp_config->tti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_DISABLE) {
+			vpath->vp_config->tti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_DISABLE;
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
+
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+			vpath->tim_rti_cfg1_saved = val64;
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_TX]);
+		}
+	}
+}
+
+void
+vxge_hal_vpath_rti_ci_set(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
+		if (vpath->vp_config->rti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_ENABLE) {
+			vpath->vp_config->rti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+			val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+			vpath->tim_rti_cfg1_saved = val64;
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
+		}
+	}
+}
+
+void
+vxge_hal_vpath_rti_ci_reset(vxge_hal_vpath_h vpath_handle)
+{
+	u64 val64;
+
+	__hal_device_t *hldev;
+	__hal_virtualpath_t *vpath;
+
+	vpath = ((__hal_vpath_handle_t *) vpath_handle)->vpath;
+	hldev = vpath->hldev;
+
+	if (vpath->vp_config->ring.enable == VXGE_HAL_RING_ENABLE) {
+		if (vpath->vp_config->rti.timer_ci_en != VXGE_HAL_TIM_TIMER_CI_DISABLE) {
+			vpath->vp_config->rti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_DISABLE;
+
+			val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
+
+			val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
+			vpath->tim_rti_cfg1_saved = val64;
+
+			vxge_os_pio_mem_write64(hldev->header.pdev,
+			    hldev->header.regh0,
+			    val64,
+			    &vpath->vp_reg->tim_cfg1_int_num[VXGE_HAL_VPATH_INTR_RX]);
+		}
+	}
+}
+
+vxge_hal_status_e
+vxge_hal_send_message(vxge_hal_device_h devh, u64 vp_id, u8 msg_type,
+    u8 msg_dst, u32 msg_data, u64 *msg_sent_to_vpaths)
+{
+	u32 action;
+	u64 data0 = 0x0, data1 = 0x0;
+	u32 attempts = VXGE_HAL_MSG_SEND_RETRY;
+	vxge_hal_status_e status = VXGE_HAL_OK;
+
+	data0 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_TYPE(msg_type) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DEST(msg_dst) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_SRC(vp_id) |
+	    VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DATA(msg_data);
+
+	action = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION_SEND_MSG;
+
+	do {
+		status = vxge_hal_set_fw_api(devh, vp_id, action, 0x0,
+		    data0, data1);
+		if (status != VXGE_HAL_OK) {
+			attempts--;
+			if (attempts == 0)
+			return (status);
+		}
+	} while (status != VXGE_HAL_OK);
+
+	if (msg_sent_to_vpaths != NULL) {
+		/* The API returns a vector of VPATHs the message
+		* was sent to in the event the destination is a
+		* broadcast message or being sent to the privileged VPATH
+		*/
+		*msg_sent_to_vpaths = data0 & VXGE_HAL_MSG_SEND_TO_VPATH_MASK;
+	}
+
+	return (status);
+}
diff --git a/sys/dev/vxge/vxgehal/vxgehal-virtualpath.h b/sys/dev/vxge/vxgehal/vxgehal-virtualpath.h
new file mode 100644
index 000000000000..09afc65fefe5
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-virtualpath.h
@@ -0,0 +1,425 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_VIRTUALPATH_H
+#define	VXGE_HAL_VIRTUALPATH_H
+
+__EXTERN_BEGIN_DECLS
+
+struct __hal_device_t;
+
+
+/*
+ * struct __hal_virtualpath_t - Virtual Path
+ *
+ * @vp_id: Virtual path id
+ * @vp_open: This flag specifies if vxge_hal_vp_open is called from LL Driver
+ * @hldev: Hal device
+ * @vp_config: Virtual Path Config
+ * @vp_reg: VPATH Register map address in BAR0
+ * @vpmgmt_reg: VPATH_MGMT register map address
+ * @is_first_vpath: 1 if this first vpath in this vfunc, 0 otherwise
+ * @promisc_en: Promisc mode state flag.
+ * @min_bandwidth: Guaranteed Band Width in Mbps
+ * @max_bandwidth: Maximum Band Width in Mbps
+ * @max_mtu: Max mtu that can be supported
+ * @sess_grps_available: The mask of available session groups for this vpath
+ * @bmap_root_assigned: The bitmap root for this vpath
+ * @vsport_choices: The mask of vsports that are available for this vpath
+ * @vsport_number: vsport attached to this vpath
+ * @sess_grp_start: Session oid start
+ * @sess_grp_end: session oid end
+ * @max_kdfc_db: Maximum kernel mode doorbells
+ * @max_nofl_db: Maximum non offload doorbells
+ * @max_ofl_db: Maximum offload doorbells
+ * @max_msg_db: Maximum message doorbells
+ * @rxd_mem_size: Maximum RxD memory size
+ * @tx_intr_num: Interrupt Number associated with the TX
+ * @rx_intr_num: Interrupt Number associated with the RX
+ * @einta_intr_num: Interrupt Number associated with Emulated MSIX DeAssert IntA
+ * @bmap_intr_num: Interrupt Number associated with the bitmap
+ * @nce_oid_db: NCE ID database
+ * @session_oid_db: Session Object Id database
+ * @active_lros: Active LRO session list
+ * @active_lro_count: Active LRO count
+ * @free_lros: Free LRO session list
+ * @free_lro_count: Free LRO count
+ * @lro_lock: LRO session lists' lock
+ * @sqs: List of send queues
+ * @sq_lock: Lock for operations on sqs
+ * @srqs: List of SRQs
+ * @srq_lock: Lock for operations on srqs
+ * @srq_oid_db: DRQ object id database
+ * @cqrqs: CQRQs
+ * @cqrq_lock: Lock for operations on cqrqs
+ * @cqrq_oid_db: CQRQ object id database
+ * @umqh: UP Message Queue
+ * @dmqh: Down Message Queue
+ * @umq_dmq_ir: The adapter will overwrite and update this location as Messages
+ *		are read from DMQ and written into UMQ.
+ * @umq_dmq_ir_reg_entry: Reg entry of umq_dmq_ir_t
+ * @ringh: Ring Queue
+ * @fifoh: FIFO Queue
+ * @vpath_handles: Virtual Path handles list
+ * @vpath_handles_lock: Lock for operations on Virtual Path handles list
+ * @stats_block: Memory for DMAing stats
+ * @stats: Vpath statistics
+ *
+ * Virtual path structure to encapsulate the data related to a virtual path.
+ * Virtual paths are allocated by the HAL upon getting configuration from the
+ * driver and inserted into the list of virtual paths.
+ */
+typedef struct __hal_virtualpath_t {
+	u32				vp_id;
+
+	u32				vp_open;
+#define	VXGE_HAL_VP_NOT_OPEN		0
+#define	VXGE_HAL_VP_OPEN		1
+
+	struct __hal_device_t		*hldev;
+	vxge_hal_vp_config_t		*vp_config;
+	vxge_hal_vpath_reg_t		*vp_reg;
+	vxge_hal_vpmgmt_reg_t		*vpmgmt_reg;
+	__hal_non_offload_db_wrapper_t	*nofl_db;
+	__hal_messaging_db_wrapper_t	*msg_db;
+	u32				is_first_vpath;
+
+	u32				promisc_en;
+#define	VXGE_HAL_VP_PROMISC_ENABLE	1
+#define	VXGE_HAL_VP_PROMISC_DISABLE	0
+
+	u32				min_bandwidth;
+	u32				max_bandwidth;
+
+	u32				max_mtu;
+	u64				sess_grps_available;
+	u32				bmap_root_assigned;
+	u32				vsport_choices;
+	u32				vsport_number;
+	u32				sess_grp_start;
+	u32				sess_grp_end;
+	u32				max_kdfc_db;
+	u32				max_nofl_db;
+	u32				max_ofl_db;
+	u32				max_msg_db;
+	u32				rxd_mem_size;
+	u32				tx_intr_num;
+	u32				rx_intr_num;
+	u32				einta_intr_num;
+	u32				bmap_intr_num;
+
+	u64				tim_tti_cfg1_saved;
+	u64				tim_tti_cfg3_saved;
+	u64				tim_rti_cfg1_saved;
+	u64				tim_rti_cfg3_saved;
+
+
+	vxge_hal_ring_h			ringh;
+	vxge_hal_fifo_h			fifoh;
+	vxge_list_t			vpath_handles;
+	spinlock_t			vpath_handles_lock;
+	__hal_blockpool_entry_t		*stats_block;
+	vxge_hal_vpath_stats_hw_info_t	*hw_stats;
+	vxge_hal_vpath_stats_hw_info_t	*hw_stats_sav;
+	vxge_hal_vpath_stats_sw_info_t	*sw_stats;
+} __hal_virtualpath_t;
+
+/*
+ * struct __hal_vpath_handle_t - List item to store callback information
+ * @item: List head to keep the item in linked list
+ * @vpath: Virtual path to which this item belongs
+ * @cb_fn: Callback function to be called
+ * @client_handle: Client handle to be returned with the callback
+ *
+ * This structure is used to store the callback information.
+ */
+typedef struct __hal_vpath_handle_t {
+	vxge_list_t			item;
+	__hal_virtualpath_t		*vpath;
+	vxge_hal_vpath_callback_f	cb_fn;
+	vxge_hal_client_h		client_handle;
+} __hal_vpath_handle_t;
+
+
+#define	VXGE_HAL_VIRTUAL_PATH_HANDLE(vpath)				\
+		((vxge_hal_vpath_h)(vpath)->vpath_handles.next)
+
+#define	VXGE_HAL_VPATH_STATS_PIO_READ(offset) {				\
+	status = __hal_vpath_stats_access(vpath,			\
+			VXGE_HAL_STATS_OP_READ,				\
+			offset,						\
+			&val64);					\
+	if (status != VXGE_HAL_OK) {					\
+		vxge_hal_trace_log_stats("<== %s:%s:%d  Result: %d",	\
+		    __FILE__, __func__, __LINE__, status);		\
+		return (status);					\
+	}								\
+}
+
+vxge_hal_status_e
+__hal_vpath_size_quantum_set(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_mgmt_read(
+    struct __hal_device_t *hldev,
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_status_e
+__hal_vpath_pci_read(
+    struct __hal_device_t *hldev,
+    u32 vp_id,
+    u32 offset,
+    u32 length,
+    void *val);
+
+vxge_hal_status_e
+__hal_vpath_reset_check(
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_status_e
+__hal_vpath_fw_memo_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u32 action,
+    u64 param_index,
+    u64 *data0,
+    u64 *data1);
+
+vxge_hal_status_e
+__hal_vpath_fw_flash_ver_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    vxge_hal_device_version_t *fw_version,
+    vxge_hal_device_date_t *fw_date,
+    vxge_hal_device_version_t *flash_version,
+    vxge_hal_device_date_t *flash_date);
+
+vxge_hal_status_e
+__hal_vpath_card_info_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u8 *serial_number,
+    u8 *part_number,
+    u8 *product_description);
+
+vxge_hal_status_e
+__hal_vpath_pmd_info_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u32 *ports,
+    vxge_hal_device_pmd_info_t *pmd_port0,
+    vxge_hal_device_pmd_info_t *pmd_port1);
+
+u64
+__hal_vpath_pci_func_mode_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg);
+
+vxge_hal_device_lag_mode_e
+__hal_vpath_lag_mode_get(
+    __hal_virtualpath_t *vpath);
+
+u64
+__hal_vpath_vpath_map_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    u32 vh,
+    u32 func,
+    vxge_hal_vpath_reg_t *vpath_reg);
+
+vxge_hal_status_e
+__hal_vpath_fw_upgrade(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    u8 *buffer,
+    u32 length);
+
+vxge_hal_status_e
+__hal_vpath_pcie_func_mode_set(
+    struct __hal_device_t *hldev,
+    u32 vp_id,
+    u32 func_mode);
+
+vxge_hal_status_e
+__hal_vpath_flick_link_led(
+    struct __hal_device_t *hldev,
+    u32 vp_id,
+    u32 port,
+    u32 on_off);
+
+vxge_hal_status_e
+__hal_vpath_udp_rth_set(
+    struct __hal_device_t *hldev,
+    u32 vp_id,
+    u32 on_off);
+
+vxge_hal_status_e
+__hal_vpath_rts_table_get(
+    vxge_hal_vpath_h vpath_handle,
+    u32 action,
+    u32 rts_table,
+    u32 offset,
+    u64 *data1,
+    u64 *data2);
+
+vxge_hal_status_e
+__hal_vpath_rts_table_set(
+    vxge_hal_vpath_h vpath_handle,
+    u32 action,
+    u32 rts_table,
+    u32 offset,
+    u64 data1,
+    u64 data2);
+
+
+vxge_hal_status_e
+__hal_vpath_hw_reset(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_sw_reset(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_prc_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_kdfc_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_mac_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_tim_configure(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_hw_initialize(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vp_initialize(
+    vxge_hal_device_h devh,
+    u32 vp_id,
+    vxge_hal_vp_config_t *config);
+
+void
+__hal_vp_terminate(
+    vxge_hal_device_h devh,
+    u32 vp_id);
+
+vxge_hal_status_e
+__hal_vpath_hw_addr_get(
+    pci_dev_h pdev,
+    pci_reg_h regh0,
+    u32 vp_id,
+    vxge_hal_vpath_reg_t *vpath_reg,
+    macaddr_t macaddr,
+    macaddr_t macaddr_mask);
+
+
+vxge_hal_status_e
+__hal_vpath_intr_enable(
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_status_e
+__hal_vpath_intr_disable(
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_device_link_state_e
+__hal_vpath_link_state_test(
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_device_link_state_e
+__hal_vpath_link_state_poll(
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_device_data_rate_e
+__hal_vpath_data_rate_poll(
+    __hal_virtualpath_t *vpath);
+
+vxge_hal_status_e
+__hal_vpath_alarm_process(
+    __hal_virtualpath_t *vpath,
+    u32 skip_alarms);
+
+vxge_hal_status_e
+__hal_vpath_stats_access(
+    __hal_virtualpath_t *vpath,
+    u32 operation,
+    u32 offset,
+    u64 *stat);
+
+vxge_hal_status_e
+__hal_vpath_xmac_tx_stats_get(
+    __hal_virtualpath_t *vpath,
+    vxge_hal_xmac_vpath_tx_stats_t *vpath_tx_stats);
+
+vxge_hal_status_e
+__hal_vpath_xmac_rx_stats_get(
+    __hal_virtualpath_t *vpath,
+    vxge_hal_xmac_vpath_rx_stats_t *vpath_rx_stats);
+
+
+vxge_hal_status_e
+__hal_vpath_hw_stats_get(
+    __hal_virtualpath_t *vpath,
+    vxge_hal_vpath_stats_hw_info_t *hw_stats);
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_VIRTUALPATH_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-vpath-reg.h b/sys/dev/vxge/vxgehal/vxgehal-vpath-reg.h
new file mode 100644
index 000000000000..20eeedd7a8a2
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-vpath-reg.h
@@ -0,0 +1,725 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_VPATH_REGS_H
+#define	VXGE_HAL_VPATH_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_vpath_reg_t {
+
+	u8	unused00300[0x00300];
+
+/* 0x00300 */	u64	usdc_vpath;
+#define	VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(val)		    vBIT(val, 0, 32)
+	u8	unused00a00[0x00a00 - 0x00308];
+
+/* 0x00a00 */	u64	wrdma_alarm_status;
+#define	VXGE_HAL_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT	    mBIT(1)
+/* 0x00a08 */	u64	wrdma_alarm_mask;
+	u8	unused00a30[0x00a30 - 0x00a10];
+
+/* 0x00a30 */	u64	prc_alarm_reg;
+#define	VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP		    mBIT(0)
+#define	VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR		    mBIT(1)
+#define	VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT	    mBIT(2)
+#define	VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR	    mBIT(3)
+/* 0x00a38 */	u64	prc_alarm_mask;
+/* 0x00a40 */	u64	prc_alarm_alarm;
+/* 0x00a48 */	u64	prc_cfg1;
+#define	VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(val)		    vBIT(val, 3, 29)
+#define	VXGE_HAL_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE	    mBIT(34)
+#define	VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE		    mBIT(35)
+#define	VXGE_HAL_PRC_CFG1_GREEDY_RETURN			    mBIT(36)
+#define	VXGE_HAL_PRC_CFG1_QUICK_SHOT			    mBIT(37)
+#define	VXGE_HAL_PRC_CFG1_RX_TIMER_CI			    mBIT(39)
+#define	VXGE_HAL_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val)	    vBIT(val, 40, 2)
+	u8	unused00a60[0x00a60 - 0x00a50];
+
+/* 0x00a60 */	u64	prc_cfg4;
+#define	VXGE_HAL_PRC_CFG4_IN_SVC			    mBIT(7)
+#define	VXGE_HAL_PRC_CFG4_RING_MODE(val)		    vBIT(val, 14, 2)
+#define	VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP			    mBIT(22)
+#define	VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP			    mBIT(23)
+#define	VXGE_HAL_PRC_CFG4_RTH_DISABLE			    mBIT(31)
+#define	VXGE_HAL_PRC_CFG4_IGNORE_OWNERSHIP		    mBIT(32)
+#define	VXGE_HAL_PRC_CFG4_SIGNAL_BENIGN_OVFLW		    mBIT(36)
+#define	VXGE_HAL_PRC_CFG4_BIMODAL_INTERRUPT		    mBIT(37)
+#define	VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(val)		    vBIT(val, 40, 24)
+/* 0x00a68 */	u64	prc_cfg5;
+#define	VXGE_HAL_PRC_CFG5_RXD0_ADD(val)			    vBIT(val, 0, 61)
+/* 0x00a70 */	u64	prc_cfg6;
+#define	VXGE_HAL_PRC_CFG6_FRM_PAD_EN			    mBIT(0)
+#define	VXGE_HAL_PRC_CFG6_QSIZE_ALIGNED_RXD		    mBIT(2)
+#define	VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN		    mBIT(5)
+#define	VXGE_HAL_PRC_CFG6_L3_CPC_TRSFR_CODE_EN		    mBIT(8)
+#define	VXGE_HAL_PRC_CFG6_L4_CPC_TRSFR_CODE_EN		    mBIT(9)
+#define	VXGE_HAL_PRC_CFG6_RXD_CRXDT(val)		    vBIT(val, 23, 9)
+#define	VXGE_HAL_PRC_CFG6_RXD_SPAT(val)			    vBIT(val, 36, 9)
+/* 0x00a78 */	u64	prc_cfg7;
+#define	VXGE_HAL_PRC_CFG7_SCATTER_MODE(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_PRC_CFG7_SMART_SCAT_EN			    mBIT(11)
+#define	VXGE_HAL_PRC_CFG7_RXD_NS_CHG_EN			    mBIT(12)
+#define	VXGE_HAL_PRC_CFG7_NO_HDR_SEPARATION		    mBIT(14)
+#define	VXGE_HAL_PRC_CFG7_RXD_BUFF_SIZE_MASK(val)	    vBIT(val, 20, 4)
+#define	VXGE_HAL_PRC_CFG7_BUFF_SIZE0_MASK(val)		    vBIT(val, 27, 5)
+/* 0x00a80 */	u64	tim_dest_addr;
+#define	VXGE_HAL_TIM_DEST_ADDR_TIM_DEST_ADDR(val)	    vBIT(val, 0, 64)
+/* 0x00a88 */	u64	prc_rxd_doorbell;
+#define	VXGE_HAL_PRC_RXD_DOORBELL_NEW_QW_CNT(val)	    vBIT(val, 48, 16)
+/* 0x00a90 */	u64	rqa_prty_for_vp;
+#define	VXGE_HAL_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val)	    vBIT(val, 59, 5)
+/* 0x00a98 */	u64	rxdmem_size;
+#define	VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val)	    vBIT(val, 51, 13)
+/* 0x00aa0 */	u64	frm_in_progress_cnt;
+#define	VXGE_HAL_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val)\
+							    vBIT(val, 59, 5)
+/* 0x00aa8 */	u64	rx_multi_cast_stats;
+#define	VXGE_HAL_RX_MULTI_CAST_STATS_FRAME_DISCARD(val)	    vBIT(val, 48, 16)
+/* 0x00ab0 */	u64	rx_frm_transferred;
+#define	VXGE_HAL_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) vBIT(val, 32, 32)
+/* 0x00ab8 */	u64	rxd_returned;
+#define	VXGE_HAL_RXD_RETURNED_RXD_RETURNED(val)		    vBIT(val, 48, 16)
+	u8	unused00c00[0x00c00 - 0x00ac0];
+
+/* 0x00c00 */	u64	kdfc_fifo_trpl_partition;
+#define	VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val)	    vBIT(val, 33, 15)
+#define	VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val)	    vBIT(val, 49, 15)
+/* 0x00c08 */	u64	kdfc_fifo_trpl_ctrl;
+#define	VXGE_HAL_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE	    mBIT(7)
+/* 0x00c10 */	u64	kdfc_trpl_fifo_0_ctrl;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN		    mBIT(22)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN		    mBIT(23)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val)	    vBIT(val, 26, 2)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC	    mBIT(28)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD		    mBIT(29)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP		    mBIT(30)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD		    mBIT(31)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val)	    vBIT(val, 41, 7)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val)	    vBIT(val, 48, 16)
+/* 0x00c18 */	u64	kdfc_trpl_fifo_1_ctrl;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(val)	    vBIT(val, 14, 2)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN		    mBIT(22)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN		    mBIT(23)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val)	    vBIT(val, 26, 2)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC	    mBIT(28)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD		    mBIT(29)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP		    mBIT(30)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD		    mBIT(31)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val)	    vBIT(val, 41, 7)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val)	    vBIT(val, 48, 16)
+/* 0x00c20 */	u64	kdfc_trpl_fifo_2_ctrl;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN		    mBIT(22)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN		    mBIT(23)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val)	    vBIT(val, 26, 2)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC	    mBIT(28)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD		    mBIT(29)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP		    mBIT(30)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD		    mBIT(31)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SELECT(val)	    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val)	    vBIT(val, 41, 7)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val)	    vBIT(val, 48, 16)
+/* 0x00c28 */	u64	kdfc_trpl_fifo_0_wb_address;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val)	    vBIT(val, 0, 64)
+/* 0x00c30 */	u64	kdfc_trpl_fifo_1_wb_address;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val)	    vBIT(val, 0, 64)
+/* 0x00c38 */	u64	kdfc_trpl_fifo_2_wb_address;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val)	    vBIT(val, 0, 64)
+/* 0x00c40 */	u64	kdfc_trpl_fifo_offset;
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val)	    vBIT(val, 1, 15)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val)	    vBIT(val, 17, 15)
+#define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val)	    vBIT(val, 33, 15)
+/* 0x00c48 */	u64	kdfc_drbl_triplet_total;
+#define	VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) vBIT(val, 17, 15)
+	u8	unused00c60[0x00c60 - 0x00c50];
+
+/* 0x00c60 */	u64	usdc_drbl_ctrl;
+#define	VXGE_HAL_USDC_DRBL_CTRL_FLIP_EN			    mBIT(22)
+#define	VXGE_HAL_USDC_DRBL_CTRL_SWAP_EN			    mBIT(23)
+/* 0x00c68 */	u64	usdc_vp_ready;
+#define	VXGE_HAL_USDC_VP_READY_USDC_HTN_READY		    mBIT(7)
+#define	VXGE_HAL_USDC_VP_READY_USDC_SRQ_READY		    mBIT(15)
+#define	VXGE_HAL_USDC_VP_READY_USDC_CQRQ_READY		    mBIT(23)
+/* 0x00c70 */	u64	kdfc_status;
+#define	VXGE_HAL_KDFC_STATUS_KDFC_WRR_0_READY		    mBIT(0)
+#define	VXGE_HAL_KDFC_STATUS_KDFC_WRR_1_READY		    mBIT(1)
+#define	VXGE_HAL_KDFC_STATUS_KDFC_WRR_2_READY		    mBIT(2)
+	u8	unused00c80[0x00c80 - 0x00c78];
+
+/* 0x00c80 */	u64	xmac_rpa_vcfg;
+#define	VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH		    mBIT(3)
+#define	VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH		    mBIT(7)
+#define	VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH		    mBIT(11)
+#define	VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH		    mBIT(15)
+#define	VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF		    mBIT(19)
+#define	VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG		    mBIT(23)
+/* 0x00c88 */	u64	rxmac_vcfg0;
+#define	VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val)	    vBIT(val, 2, 14)
+#define	VXGE_HAL_RXMAC_VCFG0_RTS_USE_MIN_LEN		    mBIT(19)
+#define	VXGE_HAL_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val)	    vBIT(val, 26, 14)
+#define	VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN		    mBIT(43)
+#define	VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN		    mBIT(47)
+#define	VXGE_HAL_RXMAC_VCFG0_BCAST_EN			    mBIT(51)
+#define	VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN			    mBIT(55)
+/* 0x00c90 */	u64	rxmac_vcfg1;
+#define	VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val)  vBIT(val, 42, 2)
+#define	VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE	    mBIT(47)
+#define	VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW		    mBIT(51)
+/* 0x00c98 */	u64	rts_access_steer_ctrl;
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4)
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_STROBE		    mBIT(15)
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL	    mBIT(23)
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_TABLE_SEL	    mBIT(27)
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(val)	    vBIT(val, 40, 8)
+#define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS	    mBIT(0)
+/* 0x00ca0 */	u64	rts_access_steer_data0;
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_DATA(val)	    vBIT(val, 0, 64)
+/* 0x00ca8 */	u64	rts_access_steer_data1;
+#define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DATA(val)	    vBIT(val, 0, 64)
+	u8	unused00d00[0x00d00 - 0x00cb0];
+
+/* 0x00d00 */	u64	xmac_vsport_choice;
+#define	VXGE_HAL_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val)	    vBIT(val, 3, 5)
+/* 0x00d08 */	u64	xmac_stats_cfg;
+/* 0x00d10 */	u64	xmac_stats_access_cmd;
+#define	VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(val)		    vBIT(val, 6, 2)
+#define	VXGE_HAL_XMAC_STATS_ACCESS_CMD_STROBE		    mBIT(15)
+#define	VXGE_HAL_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val)	    vBIT(val, 32, 8)
+/* 0x00d18 */	u64	xmac_stats_access_data;
+#define	VXGE_HAL_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val)	    vBIT(val, 0, 64)
+/* 0x00d20 */	u64	asic_ntwk_vp_ctrl;
+#define	VXGE_HAL_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK	    mBIT(3)
+#define	VXGE_HAL_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO	    mBIT(55)
+#define	VXGE_HAL_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM	    mBIT(63)
+	u8	unused00d30[0x00d30 - 0x00d28];
+
+/* 0x00d30 */	u64	xgmac_vp_int_status;
+#define	VXGE_HAL_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_INT   mBIT(3)
+/* 0x00d38 */	u64	xgmac_vp_int_mask;
+/* 0x00d40 */	u64	asic_ntwk_vp_err_reg;
+#define	VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT		    mBIT(3)
+#define	VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK		    mBIT(7)
+#define	VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED    mBIT(11)
+#define	VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED	    mBIT(15)
+#define	VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_FAULT	    mBIT(19)
+#define	VXGE_HAL_ASIC_NTWK_VP_ERR_REG_REAF_OK		    mBIT(23)
+/* 0x00d48 */	u64	asic_ntwk_vp_err_mask;
+/* 0x00d50 */	u64	asic_ntwk_vp_err_alarm;
+	u8	unused00d80[0x00d80 - 0x00d58];
+
+/* 0x00d80 */	u64	rtdma_bw_ctrl;
+#define	VXGE_HAL_RTDMA_BW_CTRL_BW_CTRL_EN		    mBIT(39)
+#define	VXGE_HAL_RTDMA_BW_CTRL_DESIRED_BW(val)		    vBIT(val, 46, 18)
+/* 0x00d88 */	u64	rtdma_rd_optimization_ctrl;
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT	mBIT(3)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val)   vBIT(val, 6, 2)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vBIT(val, 8, 8)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE mBIT(19)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val)\
+							    vBIT(val, 21, 3)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN mBIT(28)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val)\
+							    vBIT(val, 29, 3)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN mBIT(35)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) vBIT(val, 37, 3)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE mBIT(43)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val)\
+							    vBIT(val, 51, 5)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN mBIT(59)
+#define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) vBIT(val, 61, 3)
+/* 0x00d90 */	u64	pda_pcc_job_monitor;
+#define	VXGE_HAL_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS	    mBIT(7)
+/* 0x00d98 */	u64	tx_protocol_assist_cfg;
+#define	VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN	    mBIT(6)
+#define	VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING mBIT(7)
+	u8	unused01000[0x01000 - 0x00da0];
+
+/* 0x01000 */	u64	tim_cfg1_int_num[4];
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(val)	    vBIT(val, 6, 26)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN		    mBIT(35)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_TXFRM_CNT_EN		    mBIT(36)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN		    mBIT(37)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC		    mBIT(38)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI		    mBIT(39)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(val)		    vBIT(val, 41, 7)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(val)		    vBIT(val, 49, 7)
+#define	VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(val)		    vBIT(val, 57, 7)
+/* 0x01020 */	u64	tim_cfg2_int_num[4];
+#define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(val)		    vBIT(val, 0, 16)
+#define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(val)		    vBIT(val, 16, 16)
+#define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(val)		    vBIT(val, 32, 16)
+#define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(val)		    vBIT(val, 48, 16)
+/* 0x01040 */	u64	tim_cfg3_int_num[4];
+#define	VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI		    mBIT(0)
+#define	VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val)	    vBIT(val, 1, 4)
+#define	VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(val)	    vBIT(val, 6, 26)
+#define	VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(val)		    vBIT(val, 32, 6)
+#define	VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(val)	    vBIT(val, 38, 26)
+/* 0x01060 */	u64	tim_wrkld_clc;
+#define	VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val)	    vBIT(val, 35, 5)
+#define	VXGE_HAL_TIM_WRKLD_CLC_CNT_FRM_BYTE		    mBIT(40)
+#define	VXGE_HAL_TIM_WRKLD_CLC_CNT_RX_TX(val)		    vBIT(val, 41, 2)
+#define	VXGE_HAL_TIM_WRKLD_CLC_CNT_LNK_EN		    mBIT(43)
+#define	VXGE_HAL_TIM_WRKLD_CLC_HOST_UTIL(val)		    vBIT(val, 57, 7)
+/* 0x01068 */	u64	tim_bitmap;
+#define	VXGE_HAL_TIM_BITMAP_MASK(val)			    vBIT(val, 0, 32)
+#define	VXGE_HAL_TIM_BITMAP_LLROOT_RXD_EN		    mBIT(32)
+#define	VXGE_HAL_TIM_BITMAP_LLROOT_TXD_EN		    mBIT(33)
+/* 0x01070 */	u64	tim_ring_assn;
+#define	VXGE_HAL_TIM_RING_ASSN_INT_NUM(val)		    vBIT(val, 6, 2)
+/* 0x01078 */	u64	tim_remap;
+#define	VXGE_HAL_TIM_REMAP_TX_EN			    mBIT(5)
+#define	VXGE_HAL_TIM_REMAP_RX_EN			    mBIT(6)
+#define	VXGE_HAL_TIM_REMAP_OFFLOAD_EN			    mBIT(7)
+#define	VXGE_HAL_TIM_REMAP_TO_VPATH_NUM(val)		    vBIT(val, 11, 5)
+/* 0x01080 */	u64	tim_vpath_map;
+#define	VXGE_HAL_TIM_VPATH_MAP_BMAP_ROOT(val)		    vBIT(val, 0, 32)
+/* 0x01088 */	u64	tim_pci_cfg;
+#define	VXGE_HAL_TIM_PCI_CFG_ADD_PAD			    mBIT(7)
+#define	VXGE_HAL_TIM_PCI_CFG_NO_SNOOP			    mBIT(15)
+#define	VXGE_HAL_TIM_PCI_CFG_RELAXED			    mBIT(23)
+#define	VXGE_HAL_TIM_PCI_CFG_CTL_STR			    mBIT(31)
+	u8	unused01100[0x01100 - 0x01090];
+
+/* 0x01100 */	u64	sgrp_assign;
+#define	VXGE_HAL_SGRP_ASSIGN_SGRP_ASSIGN(val)		    vBIT(val, 0, 64)
+/* 0x01108 */	u64	sgrp_aoa_and_result;
+#define	VXGE_HAL_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val)\
+							    vBIT(val, 0, 64)
+/* 0x01110 */	u64	rpe_pci_cfg;
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE	    mBIT(7)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE		    mBIT(8)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE		    mBIT(9)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE	    mBIT(10)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE	    mBIT(11)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE	    mBIT(12)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE		    mBIT(13)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE		    mBIT(14)
+#define	VXGE_HAL_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE		    mBIT(15)
+#define	VXGE_HAL_RPE_PCI_CFG_NOSNOOP_DATA		    mBIT(18)
+#define	VXGE_HAL_RPE_PCI_CFG_NOSNOOP_NONLL_CQE		    mBIT(19)
+#define	VXGE_HAL_RPE_PCI_CFG_NOSNOOP_LL_CQE		    mBIT(20)
+#define	VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQRQ_IR		    mBIT(21)
+#define	VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQSQ_IR		    mBIT(22)
+#define	VXGE_HAL_RPE_PCI_CFG_NOSNOOP_CQRR_IR		    mBIT(23)
+#define	VXGE_HAL_RPE_PCI_CFG_RELAXED_DATA		    mBIT(26)
+#define	VXGE_HAL_RPE_PCI_CFG_RELAXED_NONLL_CQE		    mBIT(27)
+#define	VXGE_HAL_RPE_PCI_CFG_RELAXED_LL_CQE		    mBIT(28)
+#define	VXGE_HAL_RPE_PCI_CFG_RELAXED_CQRQ_IR		    mBIT(29)
+#define	VXGE_HAL_RPE_PCI_CFG_RELAXED_CQSQ_IR		    mBIT(30)
+#define	VXGE_HAL_RPE_PCI_CFG_RELAXED_CQRR_IR		    mBIT(31)
+/* 0x01118 */	u64	rpe_lro_cfg;
+#define	VXGE_HAL_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR	    mBIT(7)
+#define	VXGE_HAL_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG   mBIT(11)
+#define	VXGE_HAL_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG	    mBIT(15)
+#define	VXGE_HAL_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE	    mBIT(23)
+/* 0x01120 */	u64	pe_mr2vp_ack_blk_limit;
+#define	VXGE_HAL_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val)	    vBIT(val, 32, 32)
+/* 0x01128 */	u64	pe_mr2vp_rirr_lirr_blk_limit;
+#define	VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val)\
+							    vBIT(val, 32, 32)
+/* 0x01130 */	u64	txpe_pci_nce_cfg;
+#define	VXGE_HAL_TXPE_PCI_NCE_CFG_NCE_THRESH(val)	    vBIT(val, 0, 32)
+#define	VXGE_HAL_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE	    mBIT(55)
+#define	VXGE_HAL_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI		    mBIT(63)
+	u8	unused01180[0x01180 - 0x01138];
+
+/* 0x01180 */	u64	msg_qpad_en_cfg;
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_UMQ_BWR_READ		    mBIT(3)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_DMQ_BWR_READ		    mBIT(7)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_MXP_GENDMA_READ	    mBIT(11)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_UXP_GENDMA_READ	    mBIT(15)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE		    mBIT(19)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE	    mBIT(23)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE	    mBIT(27)
+#define	VXGE_HAL_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE	    mBIT(31)
+/* 0x01188 */	u64	msg_pci_cfg;
+#define	VXGE_HAL_MSG_PCI_CFG_GENDMA_NO_SNOOP		    mBIT(3)
+#define	VXGE_HAL_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP		    mBIT(7)
+#define	VXGE_HAL_MSG_PCI_CFG_UMQ_NO_SNOOP		    mBIT(11)
+#define	VXGE_HAL_MSG_PCI_CFG_DMQ_NO_SNOOP		    mBIT(15)
+/* 0x01190 */	u64	umqdmq_ir_init;
+#define	VXGE_HAL_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val)	    vBIT(val, 0, 64)
+/* 0x01198 */	u64	dmq_ir_int;
+#define	VXGE_HAL_DMQ_IR_INT_IMMED_ENABLE		    mBIT(6)
+#define	VXGE_HAL_DMQ_IR_INT_EVENT_ENABLE		    mBIT(7)
+#define	VXGE_HAL_DMQ_IR_INT_NUMBER(val)			    vBIT(val, 9, 7)
+#define	VXGE_HAL_DMQ_IR_INT_BITMAP(val)			    vBIT(val, 16, 16)
+/* 0x011a0 */	u64	dmq_bwr_init_add;
+#define	VXGE_HAL_DMQ_BWR_INIT_ADD_HOST(val)		    vBIT(val, 0, 64)
+/* 0x011a8 */	u64	dmq_bwr_init_byte;
+#define	VXGE_HAL_DMQ_BWR_INIT_BYTE_COUNT(val)		    vBIT(val, 0, 32)
+/* 0x011b0 */	u64	dmq_ir;
+#define	VXGE_HAL_DMQ_IR_POLICY(val)			    vBIT(val, 0, 8)
+/* 0x011b8 */	u64	umq_int;
+#define	VXGE_HAL_UMQ_INT_IMMED_ENABLE			    mBIT(6)
+#define	VXGE_HAL_UMQ_INT_EVENT_ENABLE			    mBIT(7)
+#define	VXGE_HAL_UMQ_INT_NUMBER(val)			    vBIT(val, 9, 7)
+#define	VXGE_HAL_UMQ_INT_BITMAP(val)			    vBIT(val, 16, 16)
+/* 0x011c0 */	u64	umq_mr2vp_bwr_pfch_init;
+#define	VXGE_HAL_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val)	    vBIT(val, 0, 8)
+/* 0x011c8 */	u64	umq_bwr_pfch_ctrl;
+#define	VXGE_HAL_UMQ_BWR_PFCH_CTRL_POLL_EN		    mBIT(3)
+/* 0x011d0 */	u64	umq_mr2vp_bwr_eol;
+#define	VXGE_HAL_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val)	    vBIT(val, 32, 32)
+/* 0x011d8 */	u64	umq_bwr_init_add;
+#define	VXGE_HAL_UMQ_BWR_INIT_ADD_HOST(val)		    vBIT(val, 0, 64)
+/* 0x011e0 */	u64	umq_bwr_init_byte;
+#define	VXGE_HAL_UMQ_BWR_INIT_BYTE_COUNT(val)		    vBIT(val, 0, 32)
+/* 0x011e8 */	u64	gendma_int;
+#define	VXGE_HAL_GENDMA_INT_IMMED_ENABLE		    mBIT(6)
+#define	VXGE_HAL_GENDMA_INT_EVENT_ENABLE		    mBIT(7)
+#define	VXGE_HAL_GENDMA_INT_NUMBER(val)			    vBIT(val, 9, 7)
+#define	VXGE_HAL_GENDMA_INT_BITMAP(val)			    vBIT(val, 16, 16)
+/* 0x011f0 */	u64	umqdmq_ir_init_notify;
+#define	VXGE_HAL_UMQDMQ_IR_INIT_NOTIFY_PULSE		    mBIT(3)
+/* 0x011f8 */	u64	dmq_init_notify;
+#define	VXGE_HAL_DMQ_INIT_NOTIFY_PULSE			    mBIT(3)
+/* 0x01200 */	u64	umq_init_notify;
+#define	VXGE_HAL_UMQ_INIT_NOTIFY_PULSE			    mBIT(3)
+	u8	unused01380[0x01380 - 0x01208];
+
+/* 0x01380 */	u64	tpa_cfg;
+#define	VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR		    mBIT(3)
+#define	VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING		    mBIT(7)
+#define	VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT		    mBIT(11)
+#define	VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS	    mBIT(15)
+	u8	unused01400[0x01400 - 0x01388];
+
+/* 0x01400 */	u64	tx_vp_reset_discarded_frms;
+#define	VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val)\
+							    vBIT(val, 48, 16)
+	u8	unused01480[0x01480 - 0x01408];
+
+/* 0x01480 */	u64	fau_rpa_vcfg;
+#define	VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM		    mBIT(7)
+#define	VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF		    mBIT(11)
+#define	VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM		    mBIT(15)
+	u8	unused014a8[0x014a8 - 0x01488];
+
+/* 0x014a8 */	u64	fau_adaptive_lro_filter_ctrl;
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IP_FILTER_EN  mBIT(0)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IP_MODE	    mBIT(1)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_VLAN_FILTER_EN mBIT(2)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_A_EN	mBIT(3)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_B_EN	mBIT(4)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_C_EN	mBIT(5)
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_CTRL_IPV4_ADDRESS_D_EN	mBIT(6)
+/* 0x014b0 */	u64	fau_adaptive_lro_filter_ip_data0;
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA0_DATA(val) vBIT(val, 0, 64)
+/* 0x014b8 */	u64	fau_adaptive_lro_filter_ip_data1;
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA1_DATA(val) vBIT(val, 0, 64)
+/* 0x014c0 */	u64	fau_adaptive_lro_filter_vlan_data;
+#define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_VLAN_DATA_VLAN_VID(val)\
+							    vBIT(val, 0, 12)
+	u8	unused014d0[0x014d0 - 0x014c8];
+
+/* 0x014d0 */	u64	dbg_stats_rx_mpa;
+#define	VXGE_HAL_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val)	    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val)	    vBIT(val, 32, 16)
+/* 0x014d8 */	u64	dbg_stats_rx_fau;
+#define	VXGE_HAL_DBG_STATS_RX_FAU_RX_WOL_FRMS(val)	    vBIT(val, 0, 16)
+#define	VXGE_HAL_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val)\
+							    vBIT(val, 16, 16)
+#define	VXGE_HAL_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val)    vBIT(val, 32, 32)
+	u8	unused014f0[0x014f0 - 0x014e0];
+
+/* 0x014f0 */	u64	fbmc_vp_rdy;
+#define	VXGE_HAL_FBMC_VP_RDY_QUEUE_SPAV_FM		    mBIT(0)
+	u8	unused01e00[0x01e00 - 0x014f8];
+
+/* 0x01e00 */	u64	vpath_pcipif_int_status;
+#define	VXGE_HAL_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_INT mBIT(3)
+#define	VXGE_HAL_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_INT mBIT(7)
+/* 0x01e08 */	u64	vpath_pcipif_int_mask;
+	u8	unused01e20[0x01e20 - 0x01e10];
+
+/* 0x01e20 */	u64	srpcim_msg_to_vpath_reg;
+#define	VXGE_HAL_SRPCIM_MSG_TO_VPATH_REG_INT		mBIT(3)
+/* 0x01e28 */	u64	srpcim_msg_to_vpath_mask;
+/* 0x01e30 */	u64	srpcim_msg_to_vpath_alarm;
+	u8	unused01ea0[0x01ea0 - 0x01e38];
+
+/* 0x01ea0 */	u64	vpath_to_srpcim_wmsg;
+#define	VXGE_HAL_VPATH_TO_SRPCIM_WMSG_WMSG(val)		vBIT(val, 0, 64)
+/* 0x01ea8 */	u64	vpath_to_srpcim_wmsg_trig;
+#define	VXGE_HAL_VPATH_TO_SRPCIM_WMSG_TRIG		mBIT(0)
+	u8	unused02000[0x02000 - 0x01eb0];
+
+/* 0x02000 */	u64	vpath_general_int_status;
+#define	VXGE_HAL_VPATH_GENERAL_INT_STATUS_PIC_INT	mBIT(3)
+#define	VXGE_HAL_VPATH_GENERAL_INT_STATUS_PCI_INT	mBIT(7)
+#define	VXGE_HAL_VPATH_GENERAL_INT_STATUS_WRDMA_INT	mBIT(15)
+#define	VXGE_HAL_VPATH_GENERAL_INT_STATUS_XMAC_INT	mBIT(19)
+/* 0x02008 */	u64	vpath_general_int_mask;
+#define	VXGE_HAL_VPATH_GENERAL_INT_MASK_PIC_INT		mBIT(3)
+#define	VXGE_HAL_VPATH_GENERAL_INT_MASK_PCI_INT		mBIT(7)
+#define	VXGE_HAL_VPATH_GENERAL_INT_MASK_WRDMA_INT	mBIT(15)
+#define	VXGE_HAL_VPATH_GENERAL_INT_MASK_XMAC_INT	mBIT(19)
+/* 0x02010 */	u64	vpath_ppif_int_status;
+#define	VXGE_HAL_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_INT   mBIT(3)
+#define	VXGE_HAL_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_INT   mBIT(7)
+#define	VXGE_HAL_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_INT mBIT(11)
+#define	VXGE_HAL_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_INT mBIT(15)
+#define	VXGE_HAL_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_INT mBIT(19)
+/* 0x02018 */	u64	vpath_ppif_int_mask;
+/* 0x02020 */	u64	kdfcctl_errors_reg;
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR	    mBIT(3)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR	    mBIT(7)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR	    mBIT(11)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON    mBIT(15)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON    mBIT(19)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON    mBIT(23)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR   mBIT(31)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR   mBIT(35)
+#define	VXGE_HAL_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR   mBIT(39)
+/* 0x02028 */	u64	kdfcctl_errors_mask;
+/* 0x02030 */	u64	kdfcctl_errors_alarm;
+	u8	unused02040[0x02040 - 0x02038];
+
+/* 0x02040 */	u64	general_errors_reg;
+#define	VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW    mBIT(3)
+#define	VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW    mBIT(7)
+#define	VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW    mBIT(11)
+#define	VXGE_HAL_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR    mBIT(15)
+#define	VXGE_HAL_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT	    mBIT(19)
+#define	VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS	    mBIT(27)
+#define	VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET	    mBIT(31)
+/* 0x02048 */	u64	general_errors_mask;
+/* 0x02050 */	u64	general_errors_alarm;
+/* 0x02058 */	u64	pci_config_errors_reg;
+#define	VXGE_HAL_PCI_CONFIG_ERRORS_REG_STATUS_ERR	    mBIT(3)
+#define	VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR	    mBIT(7)
+#define	VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR		    mBIT(11)
+/* 0x02060 */	u64	pci_config_errors_mask;
+/* 0x02068 */	u64	pci_config_errors_alarm;
+/* 0x02070 */	u64	mrpcim_to_vpath_alarm_reg;
+#define	VXGE_HAL_MRPCIM_TO_VPATH_ALARM_REG_ALARM	    mBIT(3)
+/* 0x02078 */	u64	mrpcim_to_vpath_alarm_mask;
+/* 0x02080 */	u64	mrpcim_to_vpath_alarm_alarm;
+/* 0x02088 */	u64	srpcim_to_vpath_alarm_reg;
+#define	VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_PPIF_ALARM(val)  vBIT(val, 0, 17)
+/* 0x02090 */	u64	srpcim_to_vpath_alarm_mask;
+/* 0x02098 */	u64	srpcim_to_vpath_alarm_alarm;
+	u8	unused02108[0x02108 - 0x020a0];
+
+/* 0x02108 */	u64	kdfcctl_status;
+#define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val)	    vBIT(val, 0, 8)
+#define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val)	    vBIT(val, 8, 8)
+#define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val)	    vBIT(val, 16, 8)
+#define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val)    vBIT(val, 24, 8)
+#define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val)    vBIT(val, 32, 8)
+#define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val)    vBIT(val, 40, 8)
+/* 0x02110 */	u64	rsthdlr_status;
+#define	VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET	    mBIT(3)
+#define	VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val)   vBIT(val, 6, 2)
+/* 0x02118 */	u64	fifo0_status;
+#define	VXGE_HAL_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val)	    vBIT(val, 0, 12)
+/* 0x02120 */	u64	fifo1_status;
+#define	VXGE_HAL_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val)	    vBIT(val, 0, 12)
+/* 0x02128 */	u64	fifo2_status;
+#define	VXGE_HAL_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val)	    vBIT(val, 0, 12)
+	u8	unused02158[0x02158 - 0x02130];
+
+/* 0x02158 */	u64	tgt_illegal_access;
+#define	VXGE_HAL_TGT_ILLEGAL_ACCESS_SWIF_REGION(val)	    vBIT(val, 1, 7)
+	u8	unused02200[0x02200 - 0x02160];
+
+/* 0x02200 */	u64	vpath_general_cfg1;
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_TC_VALUE(val)	    vBIT(val, 1, 3)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN	    mBIT(7)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_DATA_FLIPEN		    mBIT(11)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN	    mBIT(15)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_CTL_FLIPEN		    mBIT(23)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN	    mBIT(51)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN	    mBIT(55)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN	    mBIT(59)
+#define	VXGE_HAL_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN	    mBIT(63)
+/* 0x02208 */	u64	vpath_general_cfg2;
+#define	VXGE_HAL_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val)	    vBIT(val, 1, 3)
+/* 0x02210 */	u64	vpath_general_cfg3;
+#define	VXGE_HAL_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA mBIT(3)
+	u8	unused02220[0x02220 - 0x02218];
+
+/* 0x02220 */	u64	kdfcctl_cfg0;
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0		    mBIT(1)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1		    mBIT(2)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2		    mBIT(3)
+#define	VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0		    mBIT(5)
+#define	VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1		    mBIT(6)
+#define	VXGE_HAL_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2		    mBIT(7)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0	    mBIT(9)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1	    mBIT(10)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2	    mBIT(11)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0	    mBIT(13)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1	    mBIT(14)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2	    mBIT(15)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0	    mBIT(17)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1	    mBIT(18)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2	    mBIT(19)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0	    mBIT(21)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1	    mBIT(22)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2	    mBIT(23)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0	    mBIT(25)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1	    mBIT(26)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2	    mBIT(27)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0	    mBIT(29)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1	    mBIT(30)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2	    mBIT(31)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0	    mBIT(33)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1	    mBIT(34)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2	    mBIT(35)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0	    mBIT(37)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1	    mBIT(38)
+#define	VXGE_HAL_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2	    mBIT(39)
+/* 0x02228 */	u64	dblgen_cfg0;
+#define	VXGE_HAL_DBLGEN_CFG0_NO_OF_QWORDS(val)		    vBIT(val, 0, 12)
+#define	VXGE_HAL_DBLGEN_CFG0_EN_DMA			    mBIT(15)
+#define	VXGE_HAL_DBLGEN_CFG0_NO_SNOOP			    mBIT(19)
+#define	VXGE_HAL_DBLGEN_CFG0_RELAX_ORD			    mBIT(23)
+#define	VXGE_HAL_DBLGEN_CFG0_RD_SPLIT_ON_ADDR		    mBIT(27)
+/* 0x02230 */	u64	dblgen_cfg1;
+#define	VXGE_HAL_DBLGEN_CFG1_FIFO0_BUFFER_START_ADDR(val)   vBIT(val, 0, 64)
+/* 0x02238 */	u64	dblgen_cfg2;
+#define	VXGE_HAL_DBLGEN_CFG2_FIFO1_BUFFER_START_ADDR(val)   vBIT(val, 0, 64)
+/* 0x02240 */	u64	dblgen_cfg3;
+#define	VXGE_HAL_DBLGEN_CFG3_FIFO2_BUFFER_START_ADDR(val)   vBIT(val, 0, 64)
+/* 0x02248 */	u64	dblgen_cfg4;
+#define	VXGE_HAL_DBLGEN_CFG4_TRIPLET_PRIORITY_VP_NUMBER(val) vBIT(val, 3, 5)
+/* 0x02250 */	u64	dblgen_cfg5;
+#define	VXGE_HAL_DBLGEN_CFG5_FIFO0_WRIDX(val)		    vBIT(val, 0, 12)
+/* 0x02258 */	u64	dblgen_cfg6;
+#define	VXGE_HAL_DBLGEN_CFG6_FIFO1_WRIDX(val)		    vBIT(val, 0, 12)
+/* 0x02260 */	u64	dblgen_cfg7;
+#define	VXGE_HAL_DBLGEN_CFG7_FIFO2_WRIDX(val)		    vBIT(val, 0, 12)
+/* 0x02268 */	u64	stats_cfg;
+#define	VXGE_HAL_STATS_CFG_START_HOST_ADDR(val)		    vBIT(val, 0, 57)
+/* 0x02270 */	u64	interrupt_cfg0;
+#define	VXGE_HAL_INTERRUPT_CFG0_MSIX_FOR_RXTI(val)	    vBIT(val, 1, 7)
+#define	VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val)   vBIT(val, 9, 7)
+#define	VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val)   vBIT(val, 17, 7)
+#define	VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val)   vBIT(val, 25, 7)
+#define	VXGE_HAL_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val)   vBIT(val, 33, 7)
+	u8	unused02280[0x02280 - 0x02278];
+
+/* 0x02280 */	u64	interrupt_cfg2;
+#define	VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val)	    vBIT(val, 1, 7)
+/* 0x02288 */	u64	one_shot_vect0_en;
+#define	VXGE_HAL_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN	    mBIT(3)
+/* 0x02290 */	u64	one_shot_vect1_en;
+#define	VXGE_HAL_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN	    mBIT(3)
+/* 0x02298 */	u64	one_shot_vect2_en;
+#define	VXGE_HAL_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN	    mBIT(3)
+/* 0x022a0 */	u64	one_shot_vect3_en;
+#define	VXGE_HAL_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN	    mBIT(3)
+	u8	unused022b0[0x022b0 - 0x022a8];
+
+/* 0x022b0 */	u64	pci_config_access_cfg1;
+#define	VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val)	    vBIT(val, 0, 12)
+#define	VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0	    mBIT(15)
+/* 0x022b8 */	u64	pci_config_access_cfg2;
+#define	VXGE_HAL_PCI_CONFIG_ACCESS_CFG2_REQ		    mBIT(0)
+/* 0x022c0 */	u64	pci_config_access_status;
+#define	VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR	    mBIT(0)
+#define	VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_DATA(val)	    vBIT(val, 32, 32)
+	u8	unused02300[0x02300 - 0x022c8];
+
+/* 0x02300 */	u64	vpath_debug_stats0;
+#define	VXGE_HAL_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val)   vBIT(val, 0, 32)
+/* 0x02308 */	u64	vpath_debug_stats1;
+#define	VXGE_HAL_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val)   vBIT(val, 0, 32)
+/* 0x02310 */	u64	vpath_debug_stats2;
+#define	VXGE_HAL_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val)   vBIT(val, 0, 32)
+/* 0x02318 */	u64	vpath_debug_stats3;
+#define	VXGE_HAL_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) vBIT(val, 0, 64)
+/* 0x02320 */	u64	vpath_debug_stats4;
+#define	VXGE_HAL_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) vBIT(val, 0, 64)
+/* 0x02328 */	u64	vpath_debug_stats5;
+#define	VXGE_HAL_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val)	    vBIT(val, 32, 32)
+/* 0x02330 */	u64	vpath_debug_stats6;
+#define	VXGE_HAL_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val)	    vBIT(val, 32, 32)
+/* 0x02338 */	u64	vpath_genstats_count01;
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val)\
+							    vBIT(val, 32, 32)
+/* 0x02340 */	u64	vpath_genstats_count23;
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val)\
+							    vBIT(val, 0, 32)
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val)\
+							    vBIT(val, 32, 32)
+/* 0x02348 */	u64	vpath_genstats_count4;
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val)\
+							    vBIT(val, 32, 32)
+/* 0x02350 */	u64	vpath_genstats_count5;
+#define	VXGE_HAL_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val)\
+							    vBIT(val, 32, 32)
+	u8	unused02540[0x02540 - 0x02358];
+
+/* 0x02540 */	u64	qcc_pci_cfg;
+#define	VXGE_HAL_QCC_PCI_CFG_ADD_PAD_CQE_SPACE		    mBIT(5)
+#define	VXGE_HAL_QCC_PCI_CFG_ADD_PAD_WQE		    mBIT(6)
+#define	VXGE_HAL_QCC_PCI_CFG_ADD_PAD_SRQIR		    mBIT(7)
+#define	VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE		    mBIT(13)
+#define	VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_WQE		    mBIT(14)
+#define	VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_SRQIR		    mBIT(15)
+#define	VXGE_HAL_QCC_PCI_CFG_RELAXED_SRQIR		    mBIT(23)
+#define	VXGE_HAL_QCC_PCI_CFG_CTL_STR_CQE_SPACE		    mBIT(29)
+#define	VXGE_HAL_QCC_PCI_CFG_CTL_STR_WQE		    mBIT(30)
+#define	VXGE_HAL_QCC_PCI_CFG_CTL_STR_SRQIR		    mBIT(31)
+	u8	unused02600[0x02600 - 0x02548];
+
+/* 0x02600 */	u64	h2l_vpath_config;
+#define	VXGE_HAL_H2L_VPATH_CONFIG_OD_PAD_ENABLE		    mBIT(7)
+#define	VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP		    mBIT(15)
+/* 0x02608 */	u64	h2l_zero_byte_read_address;
+#define	VXGE_HAL_H2L_ZERO_BYTE_READ_ADDRESS_H2L_ZERO_BYTE_READ_ADDRESS(val)\
+							    vBIT(val, 0, 64)
+	u8	unused02640[0x02640 - 0x02610];
+
+/* 0x02640 */	u64	ph2l_vp_cfg0;
+#define	VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA		    mBIT(7)
+
+} vxge_hal_vpath_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_VPATH_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h b/sys/dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h
new file mode 100644
index 000000000000..2b958ae61f4a
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h
@@ -0,0 +1,246 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_VPMGMT_REGS_H
+#define	VXGE_HAL_VPMGMT_REGS_H
+
+__EXTERN_BEGIN_DECLS
+
+typedef struct vxge_hal_vpmgmt_reg_t {
+
+/* 0x00000 */	u64	one_cfg_sr_rdy;
+#define	VXGE_HAL_ONE_CFG_SR_RDY_ONE_CFG_SR_RDY		    mBIT(7)
+/* 0x00008 */	u64	sgrp_own;
+#define	VXGE_HAL_SGRP_OWN_SGRP_OWN(val)			    vBIT(val, 0, 64)
+	u8	unused00040[0x00040 - 0x00010];
+
+/* 0x00040 */	u64	vpath_to_func_map_cfg1;
+#define	VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val)\
+							    vBIT(val, 3, 5)
+/* 0x00048 */	u64	vpath_is_first;
+#define	VXGE_HAL_VPATH_IS_FIRST_VPATH_IS_FIRST		    mBIT(3)
+/* 0x00050 */	u64	srpcim_to_vpath_wmsg;
+#define	VXGE_HAL_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val)\
+							    vBIT(val, 0, 64)
+/* 0x00058 */	u64	srpcim_to_vpath_wmsg_trig;
+#define	VXGE_HAL_SRPCIM_TO_VPATH_WMSG_TRIG_TRIG		    mBIT(0)
+	u8	unused00100[0x00100 - 0x00060];
+
+/* 0x00100 */	u64	tim_vpath_assignment;
+#define	VXGE_HAL_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val)	    vBIT(val, 0, 32)
+	u8	unused00140[0x00140 - 0x00108];
+
+/* 0x00140 */	u64	rqa_top_prty_for_vp;
+#define	VXGE_HAL_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) vBIT(val, 59, 5)
+	u8	unused00180[0x00180 - 0x00148];
+
+/* 0x00180 */	u64	usdc_vpath_own;
+#define	VXGE_HAL_USDC_VPATH_OWN_SGRP_OWN(val)		    vBIT(val, 0, 32)
+	u8	unused001c0[0x001c0 - 0x00188];
+
+/* 0x001c0 */	u64	rxmac_rx_pa_cfg0_vpmgmt_clone;
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR	mBIT(3)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N mBIT(7)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO mBIT(18)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS\
+							    mBIT(19)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING mBIT(23)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN	mBIT(27)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE	mBIT(35)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR\
+							    mBIT(39)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR\
+							    mBIT(43)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR\
+							    mBIT(47)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR\
+							    mBIT(51)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR\
+							    mBIT(55)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR\
+							    mBIT(59)
+#define	VXGE_HAL_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN mBIT(63)
+/* 0x001c8 */	u64	rts_mgr_cfg0_vpmgmt_clone;
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY mBIT(3)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val)\
+							    vBIT(val, 24, 8)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH	    mBIT(35)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH	    mBIT(39)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH    mBIT(43)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH mBIT(47)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH mBIT(51)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH mBIT(55)
+#define	VXGE_HAL_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH	    mBIT(59)
+/* 0x001d0 */	u64	rts_mgr_criteria_priority_vpmgmt_clone;
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val)\
+							    vBIT(val, 5, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val)\
+							    vBIT(val, 13, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val)\
+							    vBIT(val, 17, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val)\
+							    vBIT(val, 21, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val)\
+							    vBIT(val, 25, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val)\
+							    vBIT(val, 29, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val)\
+							    vBIT(val, 33, 3)
+#define	VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val)\
+							    vBIT(val, 37, 3)
+/* 0x001d8 */	u64	rxmac_cfg0_port_vpmgmt_clone[3];
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN	    mBIT(3)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS	    mBIT(7)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM  mBIT(11)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR mBIT(15)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR mBIT(19)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR	mBIT(23)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH mBIT(27)
+#define	VXGE_HAL_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val)\
+							    vBIT(val, 50, 14)
+/* 0x001f0 */	u64	rxmac_pause_cfg_port_vpmgmt_clone[3];
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN   mBIT(3)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN   mBIT(7)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val)\
+							    vBIT(val, 9, 3)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR mBIT(15)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val)\
+							    vBIT(val, 20, 16)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR mBIT(39)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR mBIT(43)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN mBIT(47)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val)\
+							    vBIT(val, 48, 8)
+#define	VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL	mBIT(59)
+	u8	unused00240[0x00240 - 0x00208];
+
+/* 0x00240 */	u64	xmac_vsport_choices_vp;
+#define	VXGE_HAL_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val)  vBIT(val, 0, 17)
+	u8	unused00260[0x00260 - 0x00248];
+
+/* 0x00260 */	u64	xgmac_gen_status_vpmgmt_clone;
+#define	VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK mBIT(3)
+#define	VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE mBIT(11)
+/* 0x00268 */	u64	xgmac_status_port_vpmgmt_clone[2];
+#define	VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT mBIT(3)
+#define	VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT mBIT(7)
+#define	VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL\
+							    mBIT(11)
+#define	VXGE_HAL_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK mBIT(15)
+/* 0x00278 */	u64	xmac_gen_cfg_vpmgmt_clone;
+#define	VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val)\
+							    vBIT(val, 2, 2)
+#define	VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT\
+							    mBIT(7)
+#define	VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR\
+							    mBIT(27)
+#define	VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val)\
+							    vBIT(val, 28, 4)
+#define	VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val)\
+							    vBIT(val, 32, 4)
+/* 0x00280 */	u64	xmac_timestamp_vpmgmt_clone;
+#define	VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_EN	mBIT(3)
+#define	VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val)\
+							    vBIT(val, 6, 2)
+#define	VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val)\
+							    vBIT(val, 12, 4)
+#define	VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART\
+							    mBIT(19)
+#define	VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val)\
+							    vBIT(val, 32, 16)
+/* 0x00288 */	u64	xmac_stats_gen_cfg_vpmgmt_clone;
+#define	VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val)\
+							    vBIT(val, 4, 4)
+#define	VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val)\
+							    vBIT(val, 8, 4)
+#define	VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING\
+							    mBIT(15)
+/* 0x00290 */	u64	xmac_cfg_port_vpmgmt_clone[3];
+#define	VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK\
+							    mBIT(3)
+#define	VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK\
+							    mBIT(7)
+#define	VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV\
+							    mBIT(11)
+#define	VXGE_HAL_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV\
+							    mBIT(15)
+	u8	unused002c0[0x002c0 - 0x002a8];
+
+/* 0x002c0 */	u64	txmac_gen_cfg0_vpmgmt_clone;
+#define	VXGE_HAL_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT\
+							    mBIT(7)
+/* 0x002c8 */	u64	txmac_cfg0_port_vpmgmt_clone[3];
+#define	VXGE_HAL_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN\
+							    mBIT(3)
+#define	VXGE_HAL_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD\
+							    mBIT(7)
+#define	VXGE_HAL_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vBIT(val, 8, 8)
+	u8	unused00300[0x00300 - 0x002e0];
+
+/* 0x00300 */	u64	wol_mp_crc;
+#define	VXGE_HAL_WOL_MP_CRC_CRC(val)			    vBIT(val, 0, 32)
+#define	VXGE_HAL_WOL_MP_CRC_RC_EN			    mBIT(63)
+/* 0x00308 */	u64	wol_mp_mask_a;
+#define	VXGE_HAL_WOL_MP_MASK_A_MASK(val)		    vBIT(val, 0, 64)
+/* 0x00310 */	u64	wol_mp_mask_b;
+#define	VXGE_HAL_WOL_MP_MASK_B_MASK(val)		    vBIT(val, 0, 64)
+	u8	unused00360[0x00360 - 0x00318];
+
+/* 0x00360 */	u64	fau_pa_cfg_vpmgmt_clone;
+#define	VXGE_HAL_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM  mBIT(3)
+#define	VXGE_HAL_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF    mBIT(7)
+#define	VXGE_HAL_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM  mBIT(11)
+/* 0x00368 */	u64	rx_datapath_util_vp_clone;
+#define	VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val)\
+							    vBIT(val, 7, 9)
+#define	VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) vBIT(val, 16, 4)
+#define	VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val)\
+							    vBIT(val, 20, 4)
+#define	VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val)\
+							    vBIT(val, 24, 4)
+	u8	unused00380[0x00380 - 0x00370];
+
+/* 0x00380 */	u64	tx_datapath_util_vp_clone;
+#define	VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val)\
+							    vBIT(val, 7, 9)
+#define	VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) vBIT(val, 16, 4)
+#define	VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val)\
+							    vBIT(val, 20, 4)
+#define	VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) vBIT(val, 24, 4)
+
+} vxge_hal_vpmgmt_reg_t;
+
+__EXTERN_END_DECLS
+
+#endif	/* VXGE_HAL_VPMGMT_REGS_H */
diff --git a/sys/dev/vxge/vxgehal/vxgehal.h b/sys/dev/vxge/vxgehal/vxgehal.h
new file mode 100644
index 000000000000..3a7b4e39edf1
--- /dev/null
+++ b/sys/dev/vxge/vxgehal/vxgehal.h
@@ -0,0 +1,67 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	VXGE_HAL_H
+#define	VXGE_HAL_H
+
+#include <dev/vxge/include/vxgehal-ll.h>
+#include <dev/vxge/vxgehal/vxgehal-debug.h>
+#include <dev/vxge/vxgehal/vxgehal-regdefs.h>
+#include <dev/vxge/vxgehal/vxgehal-legacy-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-toc-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-common-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-memrepair-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-mrpcim-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-srpcim-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-vpath-reg.h>
+#include <dev/vxge/vxgehal/vxgehal-regs.h>
+#include <dev/vxge/vxgehal/vxgehal-config-priv.h>
+#include <dev/vxge/vxgehal/vxgehal-swapper.h>
+#include <dev/vxge/vxgehal/vxgehal-mm.h>
+
+#include <dev/vxge/vxgehal/vxgehal-blockpool.h>
+#include <dev/vxge/vxgehal/vxgehal-doorbells.h>
+#include <dev/vxge/vxgehal/vxgehal-virtualpath.h>
+#include <dev/vxge/vxgehal/vxgehal-device.h>
+#include <dev/vxge/vxgehal/vxgehal-channel.h>
+#include <dev/vxge/vxgehal/vxgehal-srpcim.h>
+#include <dev/vxge/vxgehal/vxgehal-mrpcim.h>
+#include <dev/vxge/vxgehal/vxgehal-driver.h>
+#include <dev/vxge/vxgehal/vxgehal-ring.h>
+#include <dev/vxge/vxgehal/vxgehal-fifo.h>
+#include <dev/vxge/vxgehal/vxgehal-ifmsg.h>
+
+
+
+#endif	/* VXGE_HAL_H */
diff --git a/sys/dev/vxge/vxgell-version.h b/sys/dev/vxge/vxgell-version.h
new file mode 100644
index 000000000000..d229d5f5cc81
--- /dev/null
+++ b/sys/dev/vxge/vxgell-version.h
@@ -0,0 +1,71 @@
+/*-
+ * Copyright(c) 2002-2011 Exar Corp.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification are permitted provided the following conditions are met:
+ *
+ *    1. Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimer.
+ *
+ *    2. Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *    3. Neither the name of the Exar Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived from
+ *       this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*$FreeBSD$*/
+
+#ifndef	_VXGELL_VERSION_H_
+#define	_VXGELL_VERSION_H_
+
+#define	XGELL_VERSION_MAJOR     2
+#define	XGELL_VERSION_MINOR     5
+#define	XGELL_VERSION_FIX       1
+#define	XGELL_VERSION_BUILD	GENERATED_BUILD_VERSION
+
+#define	VXGE_FW_VERSION(major, minor, build)	\
+	((major << 16) + (minor << 8) + build)
+
+#define	VXGE_FW_MAJ_MIN_VERSION(major, minor)	\
+	((major << 16) + (minor << 8))
+
+/* Adapter should be running with this fw version for using FW_UPGRADE API's */
+#define	VXGE_BASE_FW_MAJOR_VERSION	1
+#define	VXGE_BASE_FW_MINOR_VERSION	4
+#define	VXGE_BASE_FW_BUILD_VERSION	4
+
+#define	VXGE_BASE_FW_VERSION					\
+	VXGE_FW_VERSION(VXGE_BASE_FW_MAJOR_VERSION,		\
+			VXGE_BASE_FW_MINOR_VERSION,		\
+			VXGE_BASE_FW_BUILD_VERSION)
+
+#define	VXGE_DRV_FW_VERSION					\
+	VXGE_FW_VERSION(VXGE_MIN_FW_MAJOR_VERSION,		\
+			VXGE_MIN_FW_MINOR_VERSION,		\
+			VXGE_MIN_FW_BUILD_NUMBER)
+
+#define	VXGE_DRV_FW_MAJ_MIN_VERSION				\
+	VXGE_FW_MAJ_MIN_VERSION(VXGE_MIN_FW_MAJOR_VERSION,	\
+				VXGE_MIN_FW_MINOR_VERSION)
+
+#define	VXGE_FW_ARRAY_NAME	X3fw_ncf
+#define	VXGE_COPYRIGHT		"Copyright(c) 2002-2011 Exar Corp.\n"
+#define	VXGE_ADAPTER_NAME	"Neterion x3100 10GbE PCIe Server Adapter " \
+				"(Rev %d)"
+
+#endif				/* _VXGELL_VERSION_H_ */
diff --git a/sys/modules/vxge/Makefile b/sys/modules/vxge/Makefile
new file mode 100644
index 000000000000..d86440076692
--- /dev/null
+++ b/sys/modules/vxge/Makefile
@@ -0,0 +1,64 @@
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../../dev/vxge
+VPATH =	${.CURDIR}/../../dev/vxge/vxgehal
+
+CFLAGS_VXGE = 
+
+# Debugging/Tracing:
+#VXGE_COMPONENT_HAL_DEVICE		0x00000001
+#VXGE_COMPONENT_HAL_DEVICE_IRQ		0x00000002
+#VXGE_COMPONENT_HAL_VPATH		0x00000004
+#VXGE_COMPONENT_HAL_VPATH_IRQ		0x00000008
+#VXGE_COMPONENT_HAL_CONFIG		0x00000010
+#VXGE_COMPONENT_HAL_MM			0x00000020
+#VXGE_COMPONENT_HAL_POOL		0x00000040
+#VXGE_COMPONENT_HAL_QUEUE		0x00000080
+#VXGE_COMPONENT_HAL_CHANNEL		0x00000200
+#VXGE_COMPONENT_HAL_FIFO		0x00000400
+#VXGE_COMPONENT_HAL_RING		0x00000800
+#VXGE_COMPONENT_HAL_LRO			0x00100000
+#VXGE_COMPONENT_HAL_STATS		0x00800000
+#VXGE_COMPONENT_HAL_MRPCIM		0x01000000
+#VXGE_COMPONENT_HAL_MRPCIM_IRQ		0x02000000
+#VXGE_COMPONENT_HAL_SRPCIM		0x04000000
+#VXGE_COMPONENT_HAL_SRPCIM_IRQ		0x08000000
+#VXGE_COMPONENT_HAL_DRIVER		0x10000000
+#VXGE_COMPONENT_OSDEP			0x20000000
+#VXGE_COMPONENT_LL			0x40000000
+#VXGE_COMPONENT_ULD			0x80000000
+#VXGE_COMPONENT_ALL			0xffffffff
+
+#CFLAGS_VXGE += -DVXGE_DEBUG_MODULE_MASK=VXGE_COMPONENT_ALL
+#CFLAGS_VXGE += -DVXGE_DEBUG_ERR_MASK=VXGE_COMPONENT_ALL
+#CFLAGS_VXGE += -DVXGE_DEBUG_TRACE_MASK=VXGE_COMPONENT_ALL
+#CFLAGS_VXGE += -DVXGE_OS_MEMORY_CHECK
+
+CFLAGS_VXGE += -DVXGE_HAL_RX_MULTI_POST
+CFLAGS_VXGE += -DVXGE_HAL_TX_MULTI_POST
+
+CFLAGS += $(CFLAGS_VXGE)
+
+KMOD =	vxge
+SRCS =	vxge.c
+SRCS +=	vxgehal-driver.c
+SRCS +=	vxgehal-swapper.c
+SRCS +=	vxgehal-config.c
+SRCS +=	vxgehal-device.c
+SRCS +=	vxge-queue.c
+SRCS +=	vxgehal-mm.c
+SRCS +=	vxgehal-blockpool.c
+SRCS +=	vxgehal-channel.c
+SRCS +=	vxgehal-fifo.c
+SRCS +=	vxgehal-ring.c
+SRCS +=	vxgehal-virtualpath.c
+SRCS +=	vxgehal-doorbells.c
+SRCS +=	vxgehal-mgmt.c
+SRCS +=	vxgehal-mgmtaux.c
+SRCS +=	vxgehal-mrpcim.c
+SRCS +=	vxgehal-srpcim.c
+SRCS +=	vxgehal-ifmsg.c
+
+SRCS+=	bus_if.h device_if.h pci_if.h
+
+.include <bsd.kmod.mk>