Balance parentheses in sysctl descriptions

3 files changed, 8 insertions, 8 deletions

diff --git a/sys/amd64/amd64/trap.c b/sys/amd64/amd64/trap.c
index 01519d9a7c16..4ce31ce47a45 100644
--- a/sys/amd64/amd64/trap.c
+++ b/sys/amd64/amd64/trap.c
@@ -1135,7 +1135,7 @@ SYSCTL_PROC(_machdep, OID_AUTO, syscall_ret_flush_l1d, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     machdep_syscall_ret_flush_l1d, "I",
     "Flush L1D on syscall return with error (0 - off, 1 - on, "
-    "2 - use hw only, 3 - use sw only");
+    "2 - use hw only, 3 - use sw only)");
 
 /*
  * System call handler for native binaries.  The trap frame is already
diff --git a/sys/kern/kern_timeout.c b/sys/kern/kern_timeout.c
index 5bb948610da1..cc1521adf151 100644
--- a/sys/kern/kern_timeout.c
+++ b/sys/kern/kern_timeout.c
@@ -119,7 +119,7 @@ static int pin_pcpu_swi = 0;
 SYSCTL_INT(_kern, OID_AUTO, pin_default_swi, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &pin_default_swi,
     0, "Pin the default (non-per-cpu) swi (shared with PCPU 0 swi)");
 SYSCTL_INT(_kern, OID_AUTO, pin_pcpu_swi, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &pin_pcpu_swi,
-    0, "Pin the per-CPU swis (except PCPU 0, which is also default");
+    0, "Pin the per-CPU swis (except PCPU 0, which is also default)");
 
 /*
  * TODO:
diff --git a/sys/x86/x86/cpu_machdep.c b/sys/x86/x86/cpu_machdep.c
index 5bac8eb91eac..eb94285ad606 100644
--- a/sys/x86/x86/cpu_machdep.c
+++ b/sys/x86/x86/cpu_machdep.c
@@ -970,12 +970,12 @@ hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS)
 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     hw_ssb_disable_handler, "I",
-    "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto");
+    "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)");
 
 SYSCTL_PROC(_machdep_mitigations_ssb, OID_AUTO, disable, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     hw_ssb_disable_handler, "I",
-    "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto");
+    "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)");
 
 int hw_mds_disable;
 
@@ -1189,13 +1189,13 @@ SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     sysctl_mds_disable_handler, "I",
     "Microarchitectural Data Sampling Mitigation "
-    "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO");
+    "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)");
 
 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, disable, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     sysctl_mds_disable_handler, "I",
     "Microarchitectural Data Sampling Mitigation "
-    "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO");
+    "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)");
 
 /*
  * Intel Transactional Memory Asynchronous Abort Mitigation
@@ -1334,7 +1334,7 @@ SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, enable, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     sysctl_taa_handler, "I",
     "TAA Mitigation enablement control "
-    "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO");
+    "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO)");
 
 static int
 sysctl_taa_state_handler(SYSCTL_HANDLER_ARGS)
@@ -1407,7 +1407,7 @@ SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, enable, CTLTYPE_INT |
     CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
     sysctl_rngds_mitg_enable_handler, "I",
     "MCU Optimization, disabling RDSEED mitigation control "
-    "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled");
+    "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled)");
 
 static int
 sysctl_rngds_state_handler(SYSCTL_HANDLER_ARGS)