bwn(4): migrate bwn(4) to the native bhnd(9) interface, and drop siba_bwn.

- Remove the shim interface that allowed bwn(4) to use either siba_bwn or
  bhnd(4), replacing all siba_bwn calls with their bhnd(4) bus equivalents.
- Drop the legay, now-unused siba_bwn bus driver.
- Clean up bhnd(4) board flag defines referenced by bwn(4).

Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D13518

34 files changed, 1843 insertions, 9336 deletions

diff --git a/sys/conf/files b/sys/conf/files
index bd6dc1dc972f..1125e879b005 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1250,9 +1250,9 @@ dev/bhnd/bhndb/bhndb.c			optional bhndb bhnd
 dev/bhnd/bhndb/bhndb_bus_if.m		optional bhndb bhnd
 dev/bhnd/bhndb/bhndb_hwdata.c		optional bhndb bhnd
 dev/bhnd/bhndb/bhndb_if.m		optional bhndb bhnd
-dev/bhnd/bhndb/bhndb_pci.c		optional bhndb bhnd pci
-dev/bhnd/bhndb/bhndb_pci_hwdata.c 	optional bhndb bhnd pci
-dev/bhnd/bhndb/bhndb_pci_sprom.c	optional bhndb bhnd pci
+dev/bhnd/bhndb/bhndb_pci.c		optional bhndb_pci bhndb bhnd pci
+dev/bhnd/bhndb/bhndb_pci_hwdata.c 	optional bhndb_pci bhndb bhnd pci
+dev/bhnd/bhndb/bhndb_pci_sprom.c	optional bhndb_pci bhndb bhnd pci
 dev/bhnd/bhndb/bhndb_subr.c		optional bhndb bhnd
 dev/bhnd/bcma/bcma.c			optional bcma bhnd
 dev/bhnd/bcma/bcma_bhndb.c		optional bcma bhnd bhndb
@@ -1327,19 +1327,16 @@ dev/bwi/bwirf.c			optional bwi
 dev/bwi/if_bwi.c		optional bwi
 dev/bwi/if_bwi_pci.c		optional bwi pci
 # XXX Work around clang warnings, until maintainer approves fix.
-dev/bwn/if_bwn.c		optional bwn siba_bwn \
+dev/bwn/if_bwn.c		optional bwn bhnd \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
-dev/bwn/if_bwn_bhnd.c		optional bwn bhnd
-dev/bwn/if_bwn_pci.c		optional bwn pci bhnd bhndb
-dev/bwn/if_bwn_phy_common.c	optional bwn siba_bwn
-dev/bwn/if_bwn_phy_g.c		optional bwn siba_bwn \
+dev/bwn/if_bwn_pci.c		optional bwn pci bhnd bhndb bhndb_pci
+dev/bwn/if_bwn_phy_common.c	optional bwn bhnd
+dev/bwn/if_bwn_phy_g.c		optional bwn bhnd \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED} ${NO_WCONSTANT_CONVERSION}"
-dev/bwn/if_bwn_phy_lp.c		optional bwn siba_bwn \
+dev/bwn/if_bwn_phy_lp.c		optional bwn bhnd \
 	compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}"
-dev/bwn/if_bwn_phy_n.c		optional bwn siba_bwn
-dev/bwn/if_bwn_siba.c		optional bwn siba_bwn
-dev/bwn/if_bwn_siba_compat.c	optional bwn bhnd !bwn_use_siba
-dev/bwn/if_bwn_util.c		optional bwn siba_bwn
+dev/bwn/if_bwn_phy_n.c		optional bwn bhnd
+dev/bwn/if_bwn_util.c		optional bwn bhnd
 dev/cardbus/cardbus.c		optional cardbus
 dev/cardbus/cardbus_cis.c	optional cardbus
 dev/cardbus/cardbus_device.c	optional cardbus
@@ -3020,8 +3017,6 @@ dev/sdhci/sdhci_acpi.c		optional sdhci acpi
 dev/sdhci/sdhci_pci.c		optional sdhci pci
 dev/sf/if_sf.c			optional sf pci
 dev/sge/if_sge.c		optional sge pci
-dev/siba/siba_bwn.c		optional siba_bwn pci
-dev/siba/siba_core.c		optional siba_bwn pci
 dev/siis/siis.c			optional siis pci
 dev/sis/if_sis.c		optional sis pci
 dev/sk/if_sk.c			optional sk pci
diff --git a/sys/dev/bhnd/bhnd_ids.h b/sys/dev/bhnd/bhnd_ids.h
index 7f0ec27afba8..6c7e71f7f832 100644
--- a/sys/dev/bhnd/bhnd_ids.h
+++ b/sys/dev/bhnd/bhnd_ids.h
@@ -69,6 +69,7 @@
 
 
 /* PCI vendor IDs */
+#define	PCI_VENDOR_ASUSTEK	0x1043
 #define	PCI_VENDOR_EPIGRAM	0xfeda
 #define	PCI_VENDOR_BROADCOM	0x14e4
 #define	PCI_VENDOR_3COM		0x10b7
@@ -78,6 +79,8 @@
 #define	PCI_VENDOR_DELL		0x1028
 #define	PCI_VENDOR_HP		0x103c
 #define	PCI_VENDOR_HP_COMPAQ	0x0e11
+#define	PCI_VENDOR_LINKSYS	0x1737
+#define	PCI_VENDOR_MOTOROLA	0x1057
 #define	PCI_VENDOR_APPLE	0x106b
 #define	PCI_VENDOR_SI_IMAGE	0x1095		/* Silicon Image, used by Arasan SDIO Host */
 #define	PCI_VENDOR_BUFFALO	0x1154		/* Buffalo vendor id */
@@ -581,10 +584,10 @@
 #define	BHND_BFL_LNLDO2_2P5		0x04000000	/* Select 2.5V as LNLDO2 output voltage */
 #define	BHND_BFL_FASTPWR		0x08000000
 #define	BHND_BFL_UCPWRCTL_MININDX	0x08000000	/* Enforce min power index to avoid FEM damage */
-#define	BHND_BFL_EXTLNA_5GHz		0x10000000	/* Board has an external LNA in 5GHz band */
-#define	BHND_BFL_TRSW_1by2		0x20000000	/* Board has 2 TRSW's in 1by2 designs */
+#define	BHND_BFL_EXTLNA_5GHZ		0x10000000	/* Board has an external LNA in 5GHz band */
+#define	BHND_BFL_TRSW_1BY2		0x20000000	/* Board has 2 TRSW's in 1by2 designs */
 #define	BHND_BFL_GAINBOOSTA01	        0x20000000	/* 5g Gainboost for core0 and core1 */
-#define	BHND_BFL_LO_TRSW_R_5GHz		0x40000000	/* In 5G do not throw TRSW to T for clipLO gain */
+#define	BHND_BFL_LO_TRSW_R_5GHZ		0x40000000	/* In 5G do not throw TRSW to T for clipLO gain */
 #define	BHND_BFL_ELNA_GAINDEF		0x80000000	/* Backoff InitGain based on elna_2g/5g field
 							 * when this flag is set
 							 */
@@ -644,7 +647,7 @@
 #define	BHND_BFL_SROM11_BTCOEX		0x00000001	/* Board supports BTCOEX */
 #define	BHND_BFL_SROM11_WLAN_BT_SH_XTL	0x00000002	/* bluetooth and wlan share same crystal */
 #define	BHND_BFL_SROM11_EXTLNA		0x00001000	/* Board has an external LNA in 2.4GHz band */
-#define	BHND_BFL_SROM11_EXTLNA_5GHz	0x10000000	/* Board has an external LNA in 5GHz band */
+#define	BHND_BFL_SROM11_EXTLNA_5GHZ	0x10000000	/* Board has an external LNA in 5GHz band */
 #define	BHND_BFL_SROM11_GAINBOOSTA01	0x20000000	/* 5g Gainboost for core0 and core1 */
 #define	BHND_BFL2_SROM11_APLL_WAR	0x00000002	/* Flag to implement alternative A-band PLL settings */
 #define	BHND_BFL2_SROM11_ANAPACTRL_2G	0x00100000	/* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
diff --git a/sys/dev/bwn/if_bwn.c b/sys/dev/bwn/if_bwn.c
index 5fb008a07eba..5f48cf3dc377 100644
--- a/sys/dev/bwn/if_bwn.c
+++ b/sys/dev/bwn/if_bwn.c
@@ -2,7 +2,12 @@
  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  *
  * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * Copyright (c) 2017 The FreeBSD Foundation
  * All rights reserved.
+ * 
+ * Portions of this software were developed by Landon Fuller
+ * under sponsorship from the FreeBSD Foundation.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -42,6 +47,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
+#include <sys/gpio.h>
 #include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/endian.h>
@@ -65,16 +71,17 @@ __FBSDID("$FreeBSD$");
 #include <net/if_media.h>
 #include <net/if_types.h>
 
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-
 #include <net80211/ieee80211_var.h>
 #include <net80211/ieee80211_radiotap.h>
 #include <net80211/ieee80211_regdomain.h>
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/chipc/chipc.h>
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
@@ -87,6 +94,10 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_phy_lp.h>
 #include <dev/bwn/if_bwn_phy_n.h>
 
+#include "bhnd_nvram_map.h"
+
+#include "gpio_if.h"
+
 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0,
     "Broadcom driver parameters");
 
@@ -109,8 +120,6 @@ SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0,
 static int	bwn_hwpctl = 0;
 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0,
     "uses H/W power control");
-static int	bwn_msi_disable = 0;		/* MSI disabled  */
-TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable);
 static int	bwn_usedma = 1;
 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0,
     "uses DMA");
@@ -121,6 +130,8 @@ SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
 
 static void	bwn_attach_pre(struct bwn_softc *);
 static int	bwn_attach_post(struct bwn_softc *);
+static int	bwn_retain_bus_providers(struct bwn_softc *sc);
+static void	bwn_release_bus_providers(struct bwn_softc *sc);
 static void	bwn_sprom_bugfixes(device_t);
 static int	bwn_init(struct bwn_softc *);
 static void	bwn_parent(struct ieee80211com *);
@@ -153,6 +164,7 @@ static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
 		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	bwn_vap_delete(struct ieee80211vap *);
 static void	bwn_stop(struct bwn_softc *);
+static int	bwn_core_forceclk(struct bwn_mac *, bool);
 static int	bwn_core_init(struct bwn_mac *);
 static void	bwn_core_start(struct bwn_mac *);
 static void	bwn_core_exit(struct bwn_mac *);
@@ -211,8 +223,6 @@ static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *,
 		    uint16_t, struct bwn_pio_txpkt **);
 static void	bwn_dma_init(struct bwn_mac *);
 static void	bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t);
-static int	bwn_dma_mask2type(uint64_t);
-static uint64_t	bwn_dma_mask(struct bwn_mac *);
 static uint16_t	bwn_dma_base(int, int);
 static void	bwn_dma_ringfree(struct bwn_dma_ring **);
 static void	bwn_dma_32_getdesc(struct bwn_dma_ring *,
@@ -248,7 +258,6 @@ static int	bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int);
 static void	bwn_dma_free_descbuf(struct bwn_dma_ring *,
 		    struct bwn_dmadesc_meta *);
 static void	bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *);
-static int	bwn_dma_gettype(struct bwn_mac *);
 static void	bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
 static int	bwn_dma_freeslot(struct bwn_dma_ring *);
 static int	bwn_dma_nextslot(struct bwn_dma_ring *, int);
@@ -270,7 +279,7 @@ static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *,
 		    uint8_t);
 static int	bwn_dma_attach(struct bwn_mac *);
 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *,
-		    int, int, int);
+		    int, int);
 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *,
 		    const struct bwn_txstatus *, uint16_t, int *);
 static void	bwn_dma_free(struct bwn_mac *);
@@ -296,7 +305,7 @@ static void	bwn_phy_exit(struct bwn_mac *);
 static void	bwn_core_stop(struct bwn_mac *);
 static int	bwn_switch_band(struct bwn_softc *,
 		    struct ieee80211_channel *);
-static void	bwn_phy_reset(struct bwn_mac *);
+static int	bwn_phy_reset(struct bwn_mac *);
 static int	bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
 static void	bwn_set_pretbtt(struct bwn_mac *);
 static int	bwn_intr(void *);
@@ -346,7 +355,7 @@ static void	bwn_watchdog(void *);
 static void	bwn_dma_stop(struct bwn_mac *);
 static void	bwn_pio_stop(struct bwn_mac *);
 static void	bwn_dma_ringstop(struct bwn_dma_ring **);
-static void	bwn_led_attach(struct bwn_mac *);
+static int	bwn_led_attach(struct bwn_mac *);
 static void	bwn_led_newstate(struct bwn_mac *, enum ieee80211_state);
 static void	bwn_led_event(struct bwn_mac *, int);
 static void	bwn_led_blink_start(struct bwn_mac *, int, int);
@@ -357,16 +366,6 @@ static void	bwn_rf_turnon(struct bwn_mac *);
 static void	bwn_rf_turnoff(struct bwn_mac *);
 static void	bwn_sysctl_node(struct bwn_softc *);
 
-static struct resource_spec bwn_res_spec_legacy[] = {
-	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
-	{ -1,			0,		0 }
-};
-
-static struct resource_spec bwn_res_spec_msi[] = {
-	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
-	{ -1,			0,		0 }
-};
-
 static const struct bwn_channelinfo bwn_chantable_bg = {
 	.channels = {
 		{ 2412,  1, 30 }, { 2417,  2, 30 }, { 2422,  3, 30 },
@@ -449,7 +448,7 @@ static const struct {
 	uint16_t	vid;
 	uint8_t		led_act[BWN_LED_MAX];
 } bwn_vendor_led_act[] = {
-	VENDOR_LED_ACT(COMPAQ),
+	VENDOR_LED_ACT(HP_COMPAQ),
 	VENDOR_LED_ACT(ASUSTEK)
 };
 
@@ -458,6 +457,13 @@ static const uint8_t bwn_default_led_act[BWN_LED_MAX] =
 
 #undef VENDOR_LED_ACT
 
+static const char *bwn_led_vars[] = {
+	BHND_NVAR_LEDBH0,
+	BHND_NVAR_LEDBH1,
+	BHND_NVAR_LEDBH2,
+	BHND_NVAR_LEDBH3
+};
+
 static const struct {
 	int		on_dur;
 	int		off_dur;
@@ -484,89 +490,130 @@ static const uint16_t bwn_wme_shm_offsets[] = {
 	[3] = BWN_WME_VIDEO,
 };
 
-static const struct siba_devid bwn_devs[] = {
-	SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"),
-	SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"),
-	SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"),
-	SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"),
-	SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"),
-	SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"),
-	SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"),
-	SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"),
-	SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"),
-	SIBA_DEV(BROADCOM, 80211, 16, "Revision 16")
+/* Supported D11 core revisions */
+#define	BWN_DEV(_hwrev)	{{					\
+	BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11),	\
+	BHND_MATCH_CORE_REV(_hwrev),				\
+}}
+static const struct bhnd_device bwn_devices[] = {
+	BWN_DEV(HWREV_RANGE(5, 16)),
+	BWN_DEV(HWREV_EQ(23)),
+	BHND_DEVICE_END
 };
 
-static const struct bwn_bus_ops *
-bwn_get_bus_ops(device_t dev)
-{
-#if BWN_USE_SIBA
-	return (NULL);
-#else
-	devclass_t	bus_cls;
+/* D11 quirks when bridged via a PCI host bridge core */
+static const struct bhnd_device_quirk pci_bridge_quirks[] = {
+	BHND_CORE_QUIRK	(HWREV_LTE(10),	BWN_QUIRK_UCODE_SLOWCLOCK_WAR),
+	BHND_DEVICE_QUIRK_END
+};
 
-	bus_cls = device_get_devclass(device_get_parent(dev));
-	if (bus_cls == devclass_find("bhnd"))
-		return (&bwn_bhnd_bus_ops);
-	else
-		return (&bwn_siba_bus_ops);
-#endif
-}
+/* D11 quirks when bridged via a PCMCIA host bridge core */
+static const struct bhnd_device_quirk pcmcia_bridge_quirks[] = {
+	BHND_CORE_QUIRK	(HWREV_ANY,	BWN_QUIRK_NODMA),
+	BHND_DEVICE_QUIRK_END
+};
+
+/* Host bridge cores for which D11 quirk flags should be applied */
+static const struct bhnd_device bridge_devices[] = {
+	BHND_DEVICE(BCM, PCI,		NULL, pci_bridge_quirks),
+	BHND_DEVICE(BCM, PCMCIA,	NULL, pcmcia_bridge_quirks),
+	BHND_DEVICE_END
+};
 
 static int
 bwn_probe(device_t dev)
 {
-	struct bwn_softc	*sc;
-	int			 i;
+	const struct bhnd_device *id;
 
-	sc = device_get_softc(dev);
-	sc->sc_bus_ops = bwn_get_bus_ops(dev);
-
-	for (i = 0; i < nitems(bwn_devs); i++) {
-		if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor &&
-		    siba_get_device(dev) == bwn_devs[i].sd_device &&
-		    siba_get_revid(dev) == bwn_devs[i].sd_rev)
-			return (BUS_PROBE_DEFAULT);
-	}
+	id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0]));
+	if (id == NULL)
+		return (ENXIO);
 
-	return (ENXIO);
+	bhnd_set_default_core_desc(dev);
+	return (BUS_PROBE_DEFAULT);
 }
 
-int
+static int
 bwn_attach(device_t dev)
 {
-	struct bwn_mac *mac;
-	struct bwn_softc *sc = device_get_softc(dev);
-	int error, i, msic, reg;
+	struct bwn_mac		*mac;
+	struct bwn_softc	*sc;
+	device_t		 parent, hostb;
+	char			 chip_name[BHND_CHIPID_MAX_NAMELEN];
+	int			 error;
 
+	sc = device_get_softc(dev);
 	sc->sc_dev = dev;
 #ifdef BWN_DEBUG
 	sc->sc_debug = bwn_debug;
 #endif
 
-	sc->sc_bus_ops = bwn_get_bus_ops(dev);
-	if ((error = BWN_BUS_OPS_ATTACH(dev))) {
-		device_printf(sc->sc_dev,
-		    "bus-specific initialization failed (%d)\n", error);
+	mac = NULL;
+
+	/* Determine the driver quirks applicable to this device, including any
+	 * quirks specific to the bus host bridge core (if any) */
+	sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices,
+	    sizeof(bwn_devices[0]));
+
+	parent = device_get_parent(dev);
+	if ((hostb = bhnd_bus_find_hostb_device(parent)) != NULL) {
+		sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices,
+		    sizeof(bridge_devices[0]));
+	}
+
+	/* DMA explicitly disabled? */
+	if (!bwn_usedma)
+		sc->sc_quirks |= BWN_QUIRK_NODMA;
+
+	/* Fetch our chip identification and board info */
+	sc->sc_cid = *bhnd_get_chipid(dev);
+	if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) {
+		device_printf(sc->sc_dev, "couldn't read board info\n");
 		return (error);
 	}
 
+	/* Allocate our D11 register block and PMU state */
+	sc->sc_mem_rid = 0;
+	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+	    &sc->sc_mem_rid, RF_ACTIVE);
+	if (sc->sc_mem_res == NULL) {
+		device_printf(sc->sc_dev, "couldn't allocate registers\n");
+		return (error);
+	}
+	
+	if ((error = bhnd_alloc_pmu(sc->sc_dev))) {
+		bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
+		    sc->sc_mem_rid, sc->sc_mem_res);
+		return (error);
+	}
+
+	/* Retain references to all required bus service providers */
+	if ((error = bwn_retain_bus_providers(sc)))
+		goto fail;
+
+	/* Fetch mask of available antennas */
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA2G,
+	    &sc->sc_ant2g);
+	if (error) {
+		device_printf(sc->sc_dev, "error determining 2GHz antenna "
+		    "availability from NVRAM: %d\n", error);
+		goto fail;
+	}
+
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA5G,
+	    &sc->sc_ant5g);
+	if (error) {
+		device_printf(sc->sc_dev, "error determining 5GHz antenna "
+		    "availability from NVRAM: %d\n", error);
+		goto fail;
+	}
+
 	if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
 		bwn_attach_pre(sc);
 		bwn_sprom_bugfixes(dev);
 		sc->sc_flags |= BWN_FLAG_ATTACHED;
 	}
 
-	if (!TAILQ_EMPTY(&sc->sc_maclist)) {
-		if (siba_get_pci_device(dev) != 0x4313 &&
-		    siba_get_pci_device(dev) != 0x431a &&
-		    siba_get_pci_device(dev) != 0x4321) {
-			device_printf(sc->sc_dev,
-			    "skip 802.11 cores\n");
-			return (ENODEV);
-		}
-	}
-
 	mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO);
 	mac->mac_sc = sc;
 	mac->mac_status = BWN_MAC_STATUS_UNINIT;
@@ -579,18 +626,19 @@ bwn_attach(device_t dev)
 
 	error = bwn_attach_core(mac);
 	if (error)
-		goto fail0;
-	bwn_led_attach(mac);
+		goto fail;
+	error = bwn_led_attach(mac);
+	if (error)
+		goto fail;
 
-	device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) "
+	bhnd_format_chip_id(chip_name, sizeof(chip_name), sc->sc_cid.chip_id);
+	device_printf(sc->sc_dev, "WLAN (%s rev %u) "
 	    "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
-	    siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev),
-	    mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev,
-	    mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver,
-	    mac->mac_phy.rf_rev);
+	    chip_name, bhnd_get_hwrev(sc->sc_dev), mac->mac_phy.analog,
+	    mac->mac_phy.type, mac->mac_phy.rev, mac->mac_phy.rf_manuf,
+	    mac->mac_phy.rf_ver, mac->mac_phy.rf_rev);
 	if (mac->mac_flags & BWN_MAC_FLAG_DMA)
-		device_printf(sc->sc_dev, "DMA (%d bits)\n",
-		    mac->mac_method.dma.dmatype);
+		device_printf(sc->sc_dev, "DMA (%d bits)\n", mac->mac_dmatype);
 	else
 		device_printf(sc->sc_dev, "PIO\n");
 
@@ -599,49 +647,23 @@ bwn_attach(device_t dev)
 	    "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n");
 #endif
 
-	/*
-	 * setup PCI resources and interrupt.
-	 */
-	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
-		msic = pci_msi_count(dev);
-		if (bootverbose)
-			device_printf(sc->sc_dev, "MSI count : %d\n", msic);
-	} else
-		msic = 0;
-
-	mac->mac_intr_spec = bwn_res_spec_legacy;
-	if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) {
-		if (pci_alloc_msi(dev, &msic) == 0) {
-			device_printf(sc->sc_dev,
-			    "Using %d MSI messages\n", msic);
-			mac->mac_intr_spec = bwn_res_spec_msi;
-			mac->mac_msi = 1;
-		}
-	}
+	mac->mac_rid_irq = 0;
+	mac->mac_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+	    &mac->mac_rid_irq, RF_ACTIVE | RF_SHAREABLE);
 
-	error = bus_alloc_resources(dev, mac->mac_intr_spec,
-	    mac->mac_res_irq);
-	if (error) {
-		device_printf(sc->sc_dev,
-		    "couldn't allocate IRQ resources (%d)\n", error);
-		goto fail1;
+	if (mac->mac_res_irq == NULL) {
+		device_printf(sc->sc_dev, "couldn't allocate IRQ resource\n");
+		error = ENXIO;
+		goto fail;
 	}
 
-	if (mac->mac_msi == 0)
-		error = bus_setup_intr(dev, mac->mac_res_irq[0],
-		    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
-		    &mac->mac_intrhand[0]);
-	else {
-		for (i = 0; i < BWN_MSI_MESSAGES; i++) {
-			error = bus_setup_intr(dev, mac->mac_res_irq[i],
-			    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
-			    &mac->mac_intrhand[i]);
-			if (error != 0) {
-				device_printf(sc->sc_dev,
-				    "couldn't setup interrupt (%d)\n", error);
-				break;
-			}
-		}
+	error = bus_setup_intr(dev, mac->mac_res_irq,
+	    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
+	    &mac->mac_intrhand);
+	if (error != 0) {
+		device_printf(sc->sc_dev, "couldn't setup interrupt (%d)\n",
+		    error);
+		goto fail;
 	}
 
 	TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list);
@@ -653,30 +675,85 @@ bwn_attach(device_t dev)
 		bwn_attach_post(sc);
 
 	return (0);
-fail1:
-	if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0)
-		pci_release_msi(dev);
-fail0:
-	BWN_BUS_OPS_DETACH(dev);
+fail:
+	if (mac != NULL && mac->mac_res_irq != NULL) {
+		bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
+		    mac->mac_res_irq);
+	}
+
 	free(mac, M_DEVBUF);
+	bhnd_release_pmu(dev);
+	bwn_release_bus_providers(sc);
+	
+	if (sc->sc_mem_res != NULL) {
+		bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
+		    sc->sc_mem_rid, sc->sc_mem_res);
+	}
+
 	return (error);
 }
 
 static int
-bwn_is_valid_ether_addr(uint8_t *addr)
+bwn_retain_bus_providers(struct bwn_softc *sc)
+{
+	struct chipc_caps *ccaps;
+
+	sc->sc_chipc = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_CHIPC);
+	if (sc->sc_chipc == NULL) {
+		device_printf(sc->sc_dev, "ChipCommon device not found\n");
+		goto failed;
+	}
+
+	ccaps = BHND_CHIPC_GET_CAPS(sc->sc_chipc);
+
+	sc->sc_gpio = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_GPIO);
+	if (sc->sc_gpio == NULL) {
+		device_printf(sc->sc_dev, "GPIO device not found\n");
+		goto failed;
+	}
+
+	if (ccaps->pmu) {
+		sc->sc_pmu = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_PMU);
+		if (sc->sc_pmu == NULL) {
+			device_printf(sc->sc_dev, "PMU device not found\n");
+			goto failed;
+		}
+	}
+
+	return (0);
+
+failed:
+	bwn_release_bus_providers(sc);
+	return (ENXIO);
+}
+
+static void
+bwn_release_bus_providers(struct bwn_softc *sc)
 {
-	char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
+#define	BWN_RELEASE_PROV(_sc, _prov, _service)	do {			\
+	if ((_sc)-> _prov != NULL) {					\
+		bhnd_release_provider((_sc)->sc_dev, (_sc)-> _prov,	\
+		    (_service));					\
+		(_sc)-> _prov = NULL;					\
+	}								\
+} while (0)
 
-	if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN)))
-		return (FALSE);
+	BWN_RELEASE_PROV(sc, sc_chipc, BHND_SERVICE_CHIPC);
+	BWN_RELEASE_PROV(sc, sc_gpio, BHND_SERVICE_GPIO);
+	BWN_RELEASE_PROV(sc, sc_pmu, BHND_SERVICE_PMU);
 
-	return (TRUE);
+#undef	BWN_RELEASE_PROV
 }
 
 static int
 bwn_attach_post(struct bwn_softc *sc)
 {
-	struct ieee80211com *ic = &sc->sc_ic;
+	struct ieee80211com	*ic;
+	const char		*mac_varname;
+	u_int			 core_unit;
+	int			 error;
+
+	ic = &sc->sc_ic;
 
 	ic->ic_softc = sc;
 	ic->ic_name = device_get_nameunit(sc->sc_dev);
@@ -699,10 +776,35 @@ bwn_attach_post(struct bwn_softc *sc)
 
 	ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;	/* s/w bmiss */
 
-	IEEE80211_ADDR_COPY(ic->ic_macaddr,
-	    bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ?
-	    siba_sprom_get_mac_80211a(sc->sc_dev) :
-	    siba_sprom_get_mac_80211bg(sc->sc_dev));
+	/* Determine the NVRAM variable containing our MAC address */
+	core_unit = bhnd_get_core_unit(sc->sc_dev);
+	mac_varname = NULL;
+	if (sc->sc_board_info.board_srom_rev <= 2) {
+		if (core_unit == 0) {
+			mac_varname = BHND_NVAR_IL0MACADDR;
+		} else if (core_unit == 1) {
+			mac_varname = BHND_NVAR_ET1MACADDR;
+		}
+	} else {
+		if (core_unit == 0) {
+			mac_varname = BHND_NVAR_MACADDR;
+		}
+	}
+
+	if (mac_varname == NULL) {
+		device_printf(sc->sc_dev, "missing MAC address variable for "
+		    "D11 core %u", core_unit);
+		return (ENXIO);
+	}
+
+	/* Read the MAC address from NVRAM */
+	error = bhnd_nvram_getvar_array(sc->sc_dev, mac_varname, ic->ic_macaddr,
+	    sizeof(ic->ic_macaddr), BHND_NVRAM_TYPE_UINT8_ARRAY);
+	if (error) {
+		device_printf(sc->sc_dev, "error reading %s: %d\n", mac_varname,
+		    error);
+		return (error);
+	}
 
 	/* call MI attach routine. */
 	ieee80211_ifattach(ic);
@@ -743,13 +845,12 @@ bwn_phy_detach(struct bwn_mac *mac)
 		mac->mac_phy.detach(mac);
 }
 
-int
+static int
 bwn_detach(device_t dev)
 {
 	struct bwn_softc *sc = device_get_softc(dev);
 	struct bwn_mac *mac = sc->sc_curmac;
 	struct ieee80211com *ic = &sc->sc_ic;
-	int i;
 
 	sc->sc_flags |= BWN_FLAG_INVALID;
 
@@ -770,20 +871,22 @@ bwn_detach(device_t dev)
 	taskqueue_drain(sc->sc_tq, &mac->mac_intrtask);
 	taskqueue_free(sc->sc_tq);
 
-	for (i = 0; i < BWN_MSI_MESSAGES; i++) {
-		if (mac->mac_intrhand[i] != NULL) {
-			bus_teardown_intr(dev, mac->mac_res_irq[i],
-			    mac->mac_intrhand[i]);
-			mac->mac_intrhand[i] = NULL;
-		}
+	if (mac->mac_intrhand != NULL) {
+		bus_teardown_intr(dev, mac->mac_res_irq, mac->mac_intrhand);
+		mac->mac_intrhand = NULL;
 	}
-	bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq);
-	if (mac->mac_msi != 0)
-		pci_release_msi(dev);
+
+	bhnd_release_pmu(dev);
+	bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
+	    sc->sc_mem_res);
+	bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
+	    mac->mac_res_irq);
 	mbufq_drain(&sc->sc_snd);
 	bwn_release_firmware(mac);
 	BWN_LOCK_DESTROY(sc);
-	BWN_BUS_OPS_DETACH(dev);
+
+	bwn_release_bus_providers(sc);
+
 	return (0);
 }
 
@@ -806,32 +909,28 @@ bwn_attach_pre(struct bwn_softc *sc)
 static void
 bwn_sprom_bugfixes(device_t dev)
 {
-#define	BWN_ISDEV(_vendor, _device, _subvendor, _subdevice)		\
-	((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) &&		\
-	 (siba_get_pci_device(dev) == _device) &&			\
-	 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) &&	\
-	 (siba_get_pci_subdevice(dev) == _subdevice))
-
-	if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE &&
-	    siba_get_pci_subdevice(dev) == 0x4e &&
-	    siba_get_pci_revid(dev) > 0x40)
-		siba_sprom_set_bf_lo(dev,
-		    siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL);
-	if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL &&
-	    siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74)
-		siba_sprom_set_bf_lo(dev,
-		    siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST);
-	if (siba_get_type(dev) == SIBA_TYPE_PCI) {
-		if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010))
-			siba_sprom_set_bf_lo(dev,
-			    siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST);
-	}
+	struct bwn_softc *sc = device_get_softc(dev);
+
+#define	BWN_ISDEV(_device, _subvendor, _subdevice)		\
+	((sc->sc_board_info.board_devid == PCI_DEVID_##_device) &&	\
+	 (sc->sc_board_info.board_vendor == PCI_VENDOR_##_subvendor) &&	\
+	 (sc->sc_board_info.board_type == _subdevice))
+
+	 /* A subset of Apple Airport Extreme (BCM4306 rev 2) devices
+	  * were programmed with a missing PACTRL boardflag */
+	 if (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE &&
+	     sc->sc_board_info.board_type == 0x4e &&
+	     sc->sc_board_info.board_rev > 0x40)
+		 sc->sc_board_info.board_flags |= BHND_BFL_PACTRL;
+
+	if (BWN_ISDEV(BCM4318_D11G, ASUSTEK, 0x100f) ||
+	    BWN_ISDEV(BCM4306_D11G, DELL, 0x0003) ||
+	    BWN_ISDEV(BCM4306_D11G, HP, 0x12f8) ||
+	    BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0013) ||
+	    BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0014) ||
+	    BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0015) ||
+	    BWN_ISDEV(BCM4306_D11G, MOTOROLA, 0x7010))
+		sc->sc_board_info.board_flags &= ~BHND_BFL_BTCOEX;
 #undef	BWN_ISDEV
 }
 
@@ -1008,7 +1107,7 @@ bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m)
 	tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
 	tq->tq_free--;
 
-	if (siba_get_revid(sc->sc_dev) >= 8) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 8) {
 		/*
 		 * XXX please removes m_defrag(9)
 		 */
@@ -1181,29 +1280,37 @@ bwn_attach_core(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	int error, have_bg = 0, have_a = 0;
-	uint32_t high;
+	uint16_t iost;
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 5,
-	    ("unsupported revision %d", siba_get_revid(sc->sc_dev)));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5,
+	    ("unsupported revision %d", bhnd_get_hwrev(sc->sc_dev)));
 
-	siba_powerup(sc->sc_dev, 0);
-	high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
-	have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0;
-	have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
-	if (high & BWN_TGSHIGH_DUALPHY) {
+	if ((error = bwn_core_forceclk(mac, true)))
+		return (error);
+
+	if ((error = bhnd_read_iost(sc->sc_dev, &iost))) {
+		device_printf(sc->sc_dev, "error reading I/O status flags: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	have_a = (iost & BWN_IOST_HAVE_5GHZ) ? 1 : 0;
+	have_bg = (iost & BWN_IOST_HAVE_2GHZ) ? 1 : 0;
+	if (iost & BWN_IOST_DUALPHY) {
 		have_bg = 1;
 		have_a = 1;
 	}
+	
 
 #if 0
-	device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d,"
+	device_printf(sc->sc_dev, "%s: iost=0x%04hx, have_a=%d, have_bg=%d,"
 	    " deviceid=0x%04x, siba_deviceid=0x%04x\n",
 	    __func__,
-	    high,
+	    iost,
 	    have_a,
 	    have_bg,
-	    siba_get_pci_device(sc->sc_dev),
-	    siba_get_chipid(sc->sc_dev));
+	    sc->sc_board_info.board_devid,
+	    sc->sc_cid.chip_id);
 #endif
 
 	/*
@@ -1211,7 +1318,29 @@ bwn_attach_core(struct bwn_mac *mac)
 	 * This is just used for resetting the core to probe things;
 	 * we will re-guess once it's all up and working.
 	 */
-	bwn_reset_core(mac, have_bg);
+	error = bwn_reset_core(mac, have_bg);
+	if (error)
+		goto fail;
+
+	/*
+	 * Determine the DMA engine type
+	 */
+	if (iost & BHND_IOST_DMA64) {
+		mac->mac_dmatype = BHND_DMA_ADDR_64BIT;
+	} else {
+		uint32_t tmp;
+		uint16_t base;
+
+		base = bwn_dma_base(0, 0);
+		BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL,
+		    BWN_DMA32_TXADDREXT_MASK);
+		tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
+		if (tmp & BWN_DMA32_TXADDREXT_MASK) {
+			mac->mac_dmatype = BHND_DMA_ADDR_32BIT;
+		} else {
+			mac->mac_dmatype = BHND_DMA_ADDR_30BIT;
+		}
+	}
 
 	/*
 	 * Get the PHY version.
@@ -1224,12 +1353,12 @@ bwn_attach_core(struct bwn_mac *mac)
 	 * This is the whitelist of devices which we "believe"
 	 * the SPROM PHY config from.  The rest are "guessed".
 	 */
-	if (siba_get_pci_device(sc->sc_dev) != 0x4312 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4315 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4319 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4324 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4328 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x432b) {
+	if (sc->sc_board_info.board_devid != PCI_DEVID_BCM4311_D11DUAL &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4328_D11G &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4318_D11DUAL &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4306_D11DUAL &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4321_D11N &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4322_D11N) {
 		have_a = have_bg = 0;
 		if (mac->mac_phy.type == BWN_PHYTYPE_A)
 			have_a = 1;
@@ -1330,7 +1459,9 @@ bwn_attach_core(struct bwn_mac *mac)
 		}
 	}
 
-	bwn_reset_core(mac, have_bg);
+	error = bwn_reset_core(mac, have_bg);
+	if (error)
+		goto fail;
 
 	error = bwn_chiptest(mac);
 	if (error)
@@ -1352,46 +1483,64 @@ bwn_attach_core(struct bwn_mac *mac)
 
 	mac->mac_phy.switch_analog(mac, 0);
 
-	siba_dev_down(sc->sc_dev, 0);
 fail:
-	siba_powerdown(sc->sc_dev);
+	bhnd_suspend_hw(sc->sc_dev, 0);
 	bwn_release_firmware(mac);
 	return (error);
 }
 
 /*
- * Reset - SIBA.
+ * Reset
  */
-void
+int
 bwn_reset_core(struct bwn_mac *mac, int g_mode)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t low, ctl;
-	uint32_t flags = 0;
+	struct bwn_softc	*sc;
+	uint32_t		 ctl;
+	uint16_t		 ioctl, ioctl_mask;
+	int			 error;
+
+	sc = mac->mac_sc;
 
 	DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode);
 
-	flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET);
+	/* Reset core */
+	ioctl = (BWN_IOCTL_PHYCLOCK_ENABLE | BWN_IOCTL_PHYRESET);
 	if (g_mode)
-		flags |= BWN_TGSLOW_SUPPORT_G;
+		ioctl |= BWN_IOCTL_SUPPORT_G;
 
 	/* XXX N-PHY only; and hard-code to 20MHz for now */
 	if (mac->mac_phy.type == BWN_PHYTYPE_N)
-		flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ;
+		ioctl |= BWN_IOCTL_PHY_BANDWIDTH_20MHZ;
+
+	if ((error = bhnd_reset_hw(sc->sc_dev, ioctl, ioctl))) {
+		device_printf(sc->sc_dev, "core reset failed: %d", error);
+		return (error);
+	}
 
-	siba_dev_up(sc->sc_dev, flags);
 	DELAY(2000);
 
 	/* Take PHY out of reset */
-	low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) &
-	    ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE);
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
-	siba_read_4(sc->sc_dev, SIBA_TGSLOW);
+	ioctl = BHND_IOCTL_CLK_FORCE;
+	ioctl_mask = BHND_IOCTL_CLK_FORCE |
+		     BWN_IOCTL_PHYRESET |
+		     BWN_IOCTL_PHYCLOCK_ENABLE;
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
+		device_printf(sc->sc_dev, "failed to set core ioctl flags: "
+		    "%d\n", error);
+		return (error);
+	}
+
 	DELAY(2000);
-	low &= ~SIBA_TGSLOW_FGC;
-	low |= BWN_TGSLOW_PHYCLOCK_ENABLE;
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
-	siba_read_4(sc->sc_dev, SIBA_TGSLOW);
+
+	ioctl = BWN_IOCTL_PHYCLOCK_ENABLE;
+	if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
+		device_printf(sc->sc_dev, "failed to set core ioctl flags: "
+		    "%d\n", error);
+		return (error);
+	}
+
 	DELAY(2000);
 
 	if (mac->mac_phy.switch_analog != NULL)
@@ -1401,6 +1550,8 @@ bwn_reset_core(struct bwn_mac *mac, int g_mode)
 	if (g_mode)
 		ctl |= BWN_MACCTL_GMODE;
 	BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
+
+	return (0);
 }
 
 static int
@@ -1426,19 +1577,11 @@ bwn_phy_getinfo(struct bwn_mac *mac, int gmode)
 		goto unsupphy;
 
 	/* RADIO */
-	if (siba_get_chipid(sc->sc_dev) == 0x4317) {
-		if (siba_get_chiprev(sc->sc_dev) == 0)
-			tmp = 0x3205017f;
-		else if (siba_get_chiprev(sc->sc_dev) == 1)
-			tmp = 0x4205017f;
-		else
-			tmp = 0x5205017f;
-	} else {
-		BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
-		tmp = BWN_READ_2(mac, BWN_RFDATALO);
-		BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
-		tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
-	}
+	BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
+	tmp = BWN_READ_2(mac, BWN_RFDATALO);
+	BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
+	tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
+
 	phy->rf_rev = (tmp & 0xf0000000) >> 28;
 	phy->rf_ver = (tmp & 0x0ffff000) >> 12;
 	phy->rf_manuf = (tmp & 0x00000fff);
@@ -1495,8 +1638,8 @@ bwn_chiptest(struct bwn_mac *mac)
 
 	bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
 
-	if ((siba_get_revid(sc->sc_dev) >= 3) &&
-	    (siba_get_revid(sc->sc_dev) <= 10)) {
+	if ((bhnd_get_hwrev(sc->sc_dev) >= 3) &&
+	    (bhnd_get_hwrev(sc->sc_dev) <= 10)) {
 		BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
 		BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
 		if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
@@ -2027,6 +2170,34 @@ bwn_wme_clear(struct bwn_softc *sc)
 }
 
 static int
+bwn_core_forceclk(struct bwn_mac *mac, bool force)
+{
+	struct bwn_softc	*sc;
+	bhnd_clock		 clock;
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	/* On PMU equipped devices, we do not need to force the HT clock */
+	if (sc->sc_pmu != NULL)
+		return (0);
+
+	/* Issue a PMU clock request */
+	if (force)
+		clock = BHND_CLOCK_HT;
+	else
+		clock = BHND_CLOCK_DYN;
+
+	if ((error = bhnd_request_clock(sc->sc_dev, clock))) {
+		device_printf(sc->sc_dev, "%d clock request failed: %d\n",
+		    clock, error);
+		return (error);
+	}
+
+	return (0);
+}
+
+static int
 bwn_core_init(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
@@ -2038,9 +2209,13 @@ bwn_core_init(struct bwn_mac *mac)
 
 	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
 
-	siba_powerup(sc->sc_dev, 0);
-	if (!siba_dev_isup(sc->sc_dev))
-		bwn_reset_core(mac, mac->mac_phy.gmode);
+	if ((error = bwn_core_forceclk(mac, true)))
+		return (error);
+
+	if (bhnd_is_hw_suspended(sc->sc_dev)) {
+		if ((error = bwn_reset_core(mac, mac->mac_phy.gmode)))
+			goto fail0;
+	}
 
 	mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
 	mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
@@ -2062,9 +2237,6 @@ bwn_core_init(struct bwn_mac *mac)
 
 	mac->mac_phy.init_pre(mac);
 
-	siba_pcicore_intr(sc->sc_dev);
-
-	siba_fix_imcfglobug(sc->sc_dev);
 	bwn_bt_disable(mac);
 	if (mac->mac_phy.prepare_hw) {
 		error = mac->mac_phy.prepare_hw(mac);
@@ -2076,11 +2248,11 @@ bwn_core_init(struct bwn_mac *mac)
 	if (error)
 		goto fail0;
 	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
-	    siba_get_revid(sc->sc_dev));
+	    bhnd_get_hwrev(sc->sc_dev));
 	hf = bwn_hf_read(mac);
 	if (mac->mac_phy.type == BWN_PHYTYPE_G) {
 		hf |= BWN_HF_GPHY_SYM_WORKAROUND;
-		if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
+		if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
 			hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
 		if (mac->mac_phy.rev == 1)
 			hf |= BWN_HF_GPHY_DC_CANCELFILTER;
@@ -2091,16 +2263,15 @@ bwn_core_init(struct bwn_mac *mac)
 		if (mac->mac_phy.rf_rev == 6)
 			hf |= BWN_HF_4318_TSSI;
 	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)
+	if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
 		hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
-	if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) &&
-	    (siba_get_pcicore_revid(sc->sc_dev) <= 10))
+	if (sc->sc_quirks & BWN_QUIRK_UCODE_SLOWCLOCK_WAR)
 		hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
 	hf &= ~BWN_HF_SKIP_CFP_UPDATE;
 	bwn_hf_write(mac, hf);
 
 	/* Tell the firmware about the MAC capabilities */
-	if (siba_get_revid(sc->sc_dev) >= 13) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 13) {
 		uint32_t cap;
 		cap = BWN_READ_4(mac, BWN_MAC_HW_CAP);
 		DPRINTF(sc, BWN_DEBUG_RESET,
@@ -2124,7 +2295,7 @@ bwn_core_init(struct bwn_mac *mac)
 	    (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
 	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
 
-	if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
+	if (sc->sc_quirks & BWN_QUIRK_NODMA)
 		bwn_pio_init(mac);
 	else
 		bwn_dma_init(mac);
@@ -2133,8 +2304,11 @@ bwn_core_init(struct bwn_mac *mac)
 	bwn_bt_enable(mac);
 
 	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__);
-	siba_powerup(sc->sc_dev,
-	    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW));
+	if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
+		bwn_core_forceclk(mac, true);
+	else
+		bwn_core_forceclk(mac, false);
+
 	bwn_set_macaddr(mac);
 	bwn_crypt_init(mac);
 
@@ -2146,7 +2320,7 @@ bwn_core_init(struct bwn_mac *mac)
 	return (error);
 
 fail0:
-	siba_powerdown(sc->sc_dev);
+	bhnd_suspend_hw(sc->sc_dev, 0);
 	KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
 	    ("%s:%d: fail", __func__, __LINE__));
 	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__);
@@ -2162,7 +2336,7 @@ bwn_core_start(struct bwn_mac *mac)
 	KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	if (siba_get_revid(sc->sc_dev) < 5)
+	if (bhnd_get_hwrev(sc->sc_dev) < 5)
 		return;
 
 	while (1) {
@@ -2203,8 +2377,7 @@ bwn_core_exit(struct bwn_mac *mac)
 	bwn_pio_stop(mac);
 	bwn_chip_exit(mac);
 	mac->mac_phy.switch_analog(mac, 0);
-	siba_dev_down(sc->sc_dev, 0);
-	siba_powerdown(sc->sc_dev);
+	bhnd_suspend_hw(sc->sc_dev, 0);
 }
 
 static void
@@ -2222,6 +2395,7 @@ bwn_chip_init(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
 	uint32_t macctl;
+	u_int delay;
 	int error;
 
 	macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
@@ -2241,16 +2415,14 @@ bwn_chip_init(struct bwn_mac *mac)
 		return (error);
 
 	error = bwn_fw_loadinitvals(mac);
-	if (error) {
-		siba_gpio_set(sc->sc_dev, 0);
+	if (error)
 		return (error);
-	}
+
 	phy->switch_analog(mac, 1);
 	error = bwn_phy_init(mac);
-	if (error) {
-		siba_gpio_set(sc->sc_dev, 0);
+	if (error)
 		return (error);
-	}
+
 	if (phy->set_im)
 		phy->set_im(mac, BWN_IMMODE_NONE);
 	if (phy->set_antenna)
@@ -2260,7 +2432,7 @@ bwn_chip_init(struct bwn_mac *mac)
 	if (phy->type == BWN_PHYTYPE_B)
 		BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
 	BWN_WRITE_4(mac, 0x0100, 0x01000000);
-	if (siba_get_revid(sc->sc_dev) < 5)
+	if (bhnd_get_hwrev(sc->sc_dev) < 5)
 		BWN_WRITE_4(mac, 0x010c, 0x01000000);
 
 	BWN_WRITE_4(mac, BWN_MACCTL,
@@ -2270,7 +2442,7 @@ bwn_chip_init(struct bwn_mac *mac)
 	bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
 
 	bwn_set_opmode(mac);
-	if (siba_get_revid(sc->sc_dev) < 3) {
+	if (bhnd_get_hwrev(sc->sc_dev) < 3) {
 		BWN_WRITE_2(mac, 0x060e, 0x0000);
 		BWN_WRITE_2(mac, 0x0610, 0x8000);
 		BWN_WRITE_2(mac, 0x0604, 0x0000);
@@ -2289,9 +2461,22 @@ bwn_chip_init(struct bwn_mac *mac)
 
 	bwn_mac_phy_clock_set(mac, true);
 
-	/* SIBA powerup */
-	BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev));
-	return (error);
+	/* Provide the HT clock transition latency to the MAC core */
+	error = bhnd_get_clock_latency(sc->sc_dev, BHND_CLOCK_HT, &delay);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch HT clock latency: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	if (delay > UINT16_MAX) {
+		device_printf(sc->sc_dev, "invalid HT clock latency: %u\n",
+		    delay);
+		return (ENXIO);
+	}
+
+	BWN_WRITE_2(mac, BWN_POWERUP_DELAY, delay);
+	return (0);
 }
 
 /* read hostflags */
@@ -2459,7 +2644,7 @@ bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
 	tq->tq_index = index;
 
 	tq->tq_free = BWN_PIO_MAX_TXPACKETS;
-	if (siba_get_revid(sc->sc_dev) >= 8)
+	if (bhnd_get_hwrev(sc->sc_dev) >= 8)
 		tq->tq_size = 1920;
 	else {
 		tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
@@ -2498,7 +2683,7 @@ bwn_pio_idx2base(struct bwn_mac *mac, int index)
 		BWN_PIO11_BASE5,
 	};
 
-	if (siba_get_revid(sc->sc_dev) >= 11) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 11) {
 		if (index >= N(bases_rev11))
 			device_printf(sc->sc_dev, "%s: warning\n", __func__);
 		return (bases_rev11[index]);
@@ -2515,7 +2700,7 @@ bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
 	struct bwn_softc *sc = mac->mac_sc;
 
 	prq->prq_mac = mac;
-	prq->prq_rev = siba_get_revid(sc->sc_dev);
+	prq->prq_rev = bhnd_get_hwrev(sc->sc_dev);
 	prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
 	bwn_dma_rxdirectfifo(mac, index, 1);
 }
@@ -2547,12 +2732,10 @@ static void
 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
 {
 	uint32_t ctl;
-	int type;
 	uint16_t base;
 
-	type = bwn_dma_mask2type(bwn_dma_mask(mac));
-	base = bwn_dma_base(type, idx);
-	if (type == BWN_DMA_64BIT) {
+	base = bwn_dma_base(mac->mac_dmatype, idx);
+	if (mac->mac_dmatype == BHND_DMA_ADDR_64BIT) {
 		ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL);
 		ctl &= ~BWN_DMA64_RXDIRECTFIFO;
 		if (enable)
@@ -2567,38 +2750,6 @@ bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
 	}
 }
 
-static uint64_t
-bwn_dma_mask(struct bwn_mac *mac)
-{
-	uint32_t tmp;
-	uint16_t base;
-
-	tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
-	if (tmp & SIBA_TGSHIGH_DMA64)
-		return (BWN_DMA_BIT_MASK(64));
-	base = bwn_dma_base(0, 0);
-	BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
-	tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
-	if (tmp & BWN_DMA32_TXADDREXT_MASK)
-		return (BWN_DMA_BIT_MASK(32));
-
-	return (BWN_DMA_BIT_MASK(30));
-}
-
-static int
-bwn_dma_mask2type(uint64_t dmamask)
-{
-
-	if (dmamask == BWN_DMA_BIT_MASK(30))
-		return (BWN_DMA_30BIT);
-	if (dmamask == BWN_DMA_BIT_MASK(32))
-		return (BWN_DMA_32BIT);
-	if (dmamask == BWN_DMA_BIT_MASK(64))
-		return (BWN_DMA_64BIT);
-	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
-	return (BWN_DMA_30BIT);
-}
-
 static void
 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq)
 {
@@ -2634,7 +2785,7 @@ bwn_dma_base(int type, int controller_idx)
 		BWN_DMA32_BASE5,
 	};
 
-	if (type == BWN_DMA_64BIT) {
+	if (type == BHND_DMA_ADDR_64BIT) {
 		KASSERT(controller_idx >= 0 && controller_idx < N(map64),
 		    ("%s:%d: fail", __func__, __LINE__));
 		return (map64[controller_idx]);
@@ -2661,7 +2812,7 @@ bwn_dma_init(struct bwn_mac *mac)
 
 static struct bwn_dma_ring *
 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
-    int for_tx, int type)
+    int for_tx)
 {
 	struct bwn_dma *dma = &mac->mac_method.dma;
 	struct bwn_dma_ring *dr;
@@ -2682,11 +2833,11 @@ bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
 	if (dr->dr_meta == NULL)
 		goto fail0;
 
-	dr->dr_type = type;
+	dr->dr_type = mac->mac_dmatype;
 	dr->dr_mac = mac;
-	dr->dr_base = bwn_dma_base(type, controller_index);
+	dr->dr_base = bwn_dma_base(dr->dr_type, controller_index);
 	dr->dr_index = controller_index;
-	if (type == BWN_DMA_64BIT) {
+	if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 		dr->getdesc = bwn_dma_64_getdesc;
 		dr->setdesc = bwn_dma_64_setdesc;
 		dr->start_transfer = bwn_dma_64_start_transfer;
@@ -2886,18 +3037,22 @@ bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
     struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
     int start, int end, int irq)
 {
-	struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase;
-	struct bwn_softc *sc = dr->dr_mac->mac_sc;
-	uint32_t addr, addrext, ctl;
-	int slot;
+	struct bwn_dmadesc32		*descbase;
+	struct bwn_dma			*dma;
+	struct bhnd_dma_translation	*dt;
+	uint32_t			 addr, addrext, ctl;
+	int				 slot;
+	
+	descbase = dr->dr_ring_descbase;
+	dma = &dr->dr_mac->mac_method.dma;
+	dt = &dma->translation;
 
 	slot = (int)(&(desc->dma.dma32) - descbase);
 	KASSERT(slot >= 0 && slot < dr->dr_numslots,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK);
-	addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30;
-	addr |= siba_dma_translation(sc->sc_dev);
+	addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
+	addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
 	ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
 	if (slot == dr->dr_numslots - 1)
 		ctl |= BWN_DMA32_DCTL_DTABLEEND;
@@ -2975,22 +3130,30 @@ bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
     struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
     int start, int end, int irq)
 {
-	struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase;
-	struct bwn_softc *sc = dr->dr_mac->mac_sc;
-	int slot;
-	uint32_t ctl0 = 0, ctl1 = 0;
-	uint32_t addrlo, addrhi;
-	uint32_t addrext;
+	struct bwn_dmadesc64		*descbase;
+	struct bwn_dma			*dma;
+	struct bhnd_dma_translation	*dt;
+	bhnd_addr_t			 addr;
+	uint32_t			 addrhi, addrlo;
+	uint32_t			 addrext;
+	uint32_t			 ctl0, ctl1;
+	int				 slot;
+	
+	
+	descbase = dr->dr_ring_descbase;
+	dma = &dr->dr_mac->mac_method.dma;
+	dt = &dma->translation;
 
 	slot = (int)(&(desc->dma.dma64) - descbase);
 	KASSERT(slot >= 0 && slot < dr->dr_numslots,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	addrlo = (uint32_t) (dmaaddr & 0xffffffff);
-	addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK);
-	addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >>
-	    30;
-	addrhi |= (siba_dma_translation(sc->sc_dev) << 1);
+	addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
+	addrhi = (addr >> 32);
+	addrlo = (addr & UINT32_MAX);
+	addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
+
+	ctl0 = 0;
 	if (slot == dr->dr_numslots - 1)
 		ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
 	if (start)
@@ -2999,6 +3162,8 @@ bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
 		ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
 	if (irq)
 		ctl0 |= BWN_DMA64_DCTL0_IRQ;
+
+	ctl1 = 0;
 	ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT;
 	ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT)
 	    & BWN_DMA64_DCTL1_ADDREXT_MASK;
@@ -3100,38 +3265,40 @@ bwn_dma_allocringmemory(struct bwn_dma_ring *dr)
 static void
 bwn_dma_setup(struct bwn_dma_ring *dr)
 {
-	struct bwn_softc *sc = dr->dr_mac->mac_sc;
-	uint64_t ring64;
-	uint32_t addrext, ring32, value;
-	uint32_t trans = siba_dma_translation(sc->sc_dev);
+	struct bwn_mac			*mac;
+	struct bwn_dma			*dma;
+	struct bhnd_dma_translation	*dt;
+	bhnd_addr_t			 addr, paddr;
+	uint32_t			 addrhi, addrlo, addrext, value;
+
+	mac = dr->dr_mac;
+	dma = &mac->mac_method.dma;
+	dt = &dma->translation;
+
+	paddr = dr->dr_ring_dmabase;
+	addr = (paddr & dt->addr_mask) | dt->base_addr;
+	addrhi = (addr >> 32);
+	addrlo = (addr & UINT32_MAX);
+	addrext = ((paddr & dt->addrext_mask) >> dma->addrext_shift);
 
 	if (dr->dr_tx) {
 		dr->dr_curslot = -1;
 
-		if (dr->dr_type == BWN_DMA_64BIT) {
-			ring64 = (uint64_t)(dr->dr_ring_dmabase);
-			addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK)
-			    >> 30;
+		if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 			value = BWN_DMA64_TXENABLE;
 			value |= BWN_DMA64_TXPARITY_DISABLE;
 			value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT)
 			    & BWN_DMA64_TXADDREXT_MASK;
 			BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value);
-			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO,
-			    (ring64 & 0xffffffff));
-			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI,
-			    ((ring64 >> 32) &
-			    ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1));
+			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, addrlo);
+			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, addrhi);
 		} else {
-			ring32 = (uint32_t)(dr->dr_ring_dmabase);
-			addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
 			value = BWN_DMA32_TXENABLE;
 			value |= BWN_DMA32_TXPARITY_DISABLE;
 			value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT)
 			    & BWN_DMA32_TXADDREXT_MASK;
 			BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value);
-			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING,
-			    (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
+			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, addrlo);
 		}
 		return;
 	}
@@ -3141,32 +3308,25 @@ bwn_dma_setup(struct bwn_dma_ring *dr)
 	 */
 	dr->dr_usedslot = dr->dr_numslots;
 
-	if (dr->dr_type == BWN_DMA_64BIT) {
-		ring64 = (uint64_t)(dr->dr_ring_dmabase);
-		addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30;
+	if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 		value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT);
 		value |= BWN_DMA64_RXENABLE;
 		value |= BWN_DMA64_RXPARITY_DISABLE;
 		value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT)
 		    & BWN_DMA64_RXADDREXT_MASK;
 		BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value);
-		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff));
-		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI,
-		    ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK)
-		    | (trans << 1));
+		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, addrlo);
+		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, addrhi);
 		BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots *
 		    sizeof(struct bwn_dmadesc64));
 	} else {
-		ring32 = (uint32_t)(dr->dr_ring_dmabase);
-		addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
 		value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT);
 		value |= BWN_DMA32_RXENABLE;
 		value |= BWN_DMA32_RXPARITY_DISABLE;
 		value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT)
 		    & BWN_DMA32_RXADDREXT_MASK;
 		BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value);
-		BWN_DMA_WRITE(dr, BWN_DMA32_RXRING,
-		    (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
+		BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, addrlo);
 		BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots *
 		    sizeof(struct bwn_dmadesc32));
 	}
@@ -3187,14 +3347,14 @@ bwn_dma_cleanup(struct bwn_dma_ring *dr)
 
 	if (dr->dr_tx) {
 		bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
-		if (dr->dr_type == BWN_DMA_64BIT) {
+		if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0);
 			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0);
 		} else
 			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0);
 	} else {
 		bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
-		if (dr->dr_type == BWN_DMA_64BIT) {
+		if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 			BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0);
 			BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0);
 		} else
@@ -3246,10 +3406,10 @@ bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
 	uint16_t offset;
 
 	for (i = 0; i < 10; i++) {
-		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
+		offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
 		    BWN_DMA32_TXSTATUS;
 		value = BWN_READ_4(mac, base + offset);
-		if (type == BWN_DMA_64BIT) {
+		if (type == BHND_DMA_ADDR_64BIT) {
 			value &= BWN_DMA64_TXSTAT;
 			if (value == BWN_DMA64_TXSTAT_DISABLED ||
 			    value == BWN_DMA64_TXSTAT_IDLEWAIT ||
@@ -3264,13 +3424,14 @@ bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
 		}
 		DELAY(1000);
 	}
-	offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL;
+	offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXCTL :
+	    BWN_DMA32_TXCTL;
 	BWN_WRITE_4(mac, base + offset, 0);
 	for (i = 0; i < 10; i++) {
-		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
-						   BWN_DMA32_TXSTATUS;
+		offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
+		    BWN_DMA32_TXSTATUS;
 		value = BWN_READ_4(mac, base + offset);
-		if (type == BWN_DMA_64BIT) {
+		if (type == BHND_DMA_ADDR_64BIT) {
 			value &= BWN_DMA64_TXSTAT;
 			if (value == BWN_DMA64_TXSTAT_DISABLED) {
 				i = -1;
@@ -3303,13 +3464,14 @@ bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base,
 	int i;
 	uint16_t offset;
 
-	offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL;
+	offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXCTL :
+	    BWN_DMA32_RXCTL;
 	BWN_WRITE_4(mac, base + offset, 0);
 	for (i = 0; i < 10; i++) {
-		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS :
+		offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXSTATUS :
 		    BWN_DMA32_RXSTATUS;
 		value = BWN_READ_4(mac, base + offset);
-		if (type == BWN_DMA_64BIT) {
+		if (type == BHND_DMA_ADDR_64BIT) {
 			value &= BWN_DMA64_RXSTAT;
 			if (value == BWN_DMA64_RXSTAT_DISABLED) {
 				i = -1;
@@ -3408,13 +3570,13 @@ bwn_bt_enable(struct bwn_mac *mac)
 
 	if (bwn_bluetooth == 0)
 		return;
-	if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0)
+	if ((sc->sc_board_info.board_flags & BHND_BFL_BTCOEX) == 0)
 		return;
 	if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
 		return;
 
 	hf = bwn_hf_read(mac);
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD)
+	if (sc->sc_board_info.board_flags & BHND_BFL_BTC2WIRE_ALTGPIO)
 		hf |= BWN_HF_BT_COEXISTALT;
 	else
 		hf |= BWN_HF_BT_COEXIST;
@@ -3454,12 +3616,12 @@ bwn_crypt_init(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 
-	mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20;
+	mac->mac_max_nr_keys = (bhnd_get_hwrev(sc->sc_dev) >= 5) ? 58 : 20;
 	KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
 	    ("%s:%d: fail", __func__, __LINE__));
 	mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
 	mac->mac_ktp *= 2;
-	if (siba_get_revid(sc->sc_dev) >= 5)
+	if (bhnd_get_hwrev(sc->sc_dev) >= 5)
 		BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
 	bwn_clear_keys(mac);
 }
@@ -3467,10 +3629,7 @@ bwn_crypt_init(struct bwn_mac *mac)
 static void
 bwn_chip_exit(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-
 	bwn_phy_exit(mac);
-	siba_gpio_set(sc->sc_dev, 0);
 }
 
 static int
@@ -3487,36 +3646,72 @@ bwn_fw_fillinfo(struct bwn_mac *mac)
 	return (error);
 }
 
+/**
+ * Request that the GPIO controller tristate all pins set in @p mask, granting
+ * the MAC core control over the pins.
+ * 
+ * @param mac	bwn MAC state.
+ * @param pins	If the bit position for a pin number is set to one, tristate the
+ *		pin.
+ */
+int
+bwn_gpio_control(struct bwn_mac *mac, uint32_t pins)
+{
+	struct bwn_softc	*sc;
+	uint32_t		 flags[32];
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	/* Determine desired pin flags */
+	for (size_t pin = 0; pin < nitems(flags); pin++) {
+		uint32_t pinbit = (1 << pin);
+
+		if (pins & pinbit) {
+			/* Tristate output */
+			flags[pin] = GPIO_PIN_OUTPUT|GPIO_PIN_TRISTATE;
+		} else {
+			/* Leave unmodified */
+			flags[pin] = 0;
+		}
+	}
+
+	/* Configure all pins */
+	error = GPIO_PIN_CONFIG_32(sc->sc_gpio, 0, nitems(flags), flags);
+	if (error) {
+		device_printf(sc->sc_dev, "error configuring %s pin flags: "
+		    "%d\n", device_get_nameunit(sc->sc_gpio), error);
+		return (error);
+	}
+
+	return (0);
+}
+
+
 static int
 bwn_gpio_init(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t mask = 0x1f, set = 0xf, value;
+	struct bwn_softc	*sc;
+	uint32_t		 pins;
+
+	sc = mac->mac_sc;
+
+	pins = 0xF;
 
 	BWN_WRITE_4(mac, BWN_MACCTL,
 	    BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
 	BWN_WRITE_2(mac, BWN_GPIO_MASK,
-	    BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f);
+	    BWN_READ_2(mac, BWN_GPIO_MASK) | pins);
 
-	if (siba_get_chipid(sc->sc_dev) == 0x4301) {
-		mask |= 0x0060;
-		set |= 0x0060;
-	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) {
+	if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) {
+		/* MAC core is responsible for toggling PAREF via gpio9 */
 		BWN_WRITE_2(mac, BWN_GPIO_MASK,
-		    BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200);
-		mask |= 0x0200;
-		set |= 0x0200;
-	}
-	if (siba_get_revid(sc->sc_dev) >= 2)
-		mask |= 0x0010;
+		    BWN_READ_2(mac, BWN_GPIO_MASK) | BHND_GPIO_BOARD_PACTRL);
 
-	value = siba_gpio_get(sc->sc_dev);
-	if (value == -1)
-		return (0);
-	siba_gpio_set(sc->sc_dev, (value & mask) | set);
+		pins |= BHND_GPIO_BOARD_PACTRL;
+	}
 
-	return (0);
+	return (bwn_gpio_control(mac, pins));
 }
 
 static int
@@ -3614,15 +3809,15 @@ bwn_set_opmode(struct bwn_mac *mac)
 		ctl &= ~BWN_MACCTL_STA;
 	ctl |= sc->sc_filters;
 
-	if (siba_get_revid(sc->sc_dev) <= 4)
+	if (bhnd_get_hwrev(sc->sc_dev) <= 4)
 		ctl |= BWN_MACCTL_PROMISC;
 
 	BWN_WRITE_4(mac, BWN_MACCTL, ctl);
 
 	cfp_pretbtt = 2;
 	if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
-		if (siba_get_chipid(sc->sc_dev) == 0x4306 &&
-		    siba_get_chiprev(sc->sc_dev) == 3)
+		if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 &&
+		    sc->sc_cid.chip_rev == 3)
 			cfp_pretbtt = 100;
 		else
 			cfp_pretbtt = 50;
@@ -3630,24 +3825,6 @@ bwn_set_opmode(struct bwn_mac *mac)
 	BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
 }
 
-static int
-bwn_dma_gettype(struct bwn_mac *mac)
-{
-	uint32_t tmp;
-	uint16_t base;
-
-	tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
-	if (tmp & SIBA_TGSHIGH_DMA64)
-		return (BWN_DMA_64BIT);
-	base = bwn_dma_base(0, 0);
-	BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
-	tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
-	if (tmp & BWN_DMA32_TXADDREXT_MASK)
-		return (BWN_DMA_32BIT);
-
-	return (BWN_DMA_30BIT);
-}
-
 static void
 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
 {
@@ -3683,7 +3860,7 @@ bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
 
 	BWN_WRITE_2(mac, 0x0568, 0x0000);
 	BWN_WRITE_2(mac, 0x07c0,
-	    (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
+	    (bhnd_get_hwrev(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
 
 	value = (ofdm ? 0x41 : 0x40);
 	BWN_WRITE_2(mac, 0x050c, value);
@@ -3752,7 +3929,7 @@ bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val)
 		printf("TODO: need swap\n");
 
 	BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset);
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
+	BWN_BARRIER(mac, BWN_RAM_CONTROL, 4, BUS_SPACE_BARRIER_WRITE);
 	BWN_WRITE_4(mac, BWN_RAM_DATA, val);
 }
 
@@ -3842,7 +4019,7 @@ bwn_psctl(struct bwn_mac *mac, uint32_t flags)
 	    (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
 	    ~BWN_MACCTL_HWPS);
 	BWN_READ_4(mac, BWN_MACCTL);
-	if (siba_get_revid(sc->sc_dev) >= 5) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
 		for (i = 0; i < 100; i++) {
 			ucstat = bwn_shm_read_2(mac, BWN_SHARED,
 			    BWN_SHARED_UCODESTAT);
@@ -3860,9 +4037,9 @@ bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_fw *fw = &mac->mac_fw;
-	const uint8_t rev = siba_get_revid(sc->sc_dev);
+	const uint8_t rev = bhnd_get_hwrev(sc->sc_dev);
 	const char *filename;
-	uint32_t high;
+	uint16_t iost;
 	int error;
 
 	/* microcode */
@@ -3967,12 +4144,15 @@ bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
 	}
 
 	/* initvals */
-	high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
+	error = bhnd_read_iost(sc->sc_dev, &iost);
+	if (error)
+		goto fail1;
+
 	switch (mac->mac_phy.type) {
 	case BWN_PHYTYPE_A:
 		if (rev < 5 || rev > 10)
 			goto fail1;
-		if (high & BWN_TGSHIGH_HAVE_2GHZ)
+		if (iost & BWN_IOST_HAVE_2GHZ)
 			filename = "a0g1initvals5";
 		else
 			filename = "a0g0initvals5";
@@ -4024,7 +4204,7 @@ bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
 	switch (mac->mac_phy.type) {
 	case BWN_PHYTYPE_A:
 		if (rev >= 5 && rev <= 10) {
-			if (high & BWN_TGSHIGH_HAVE_2GHZ)
+			if (iost & BWN_IOST_HAVE_2GHZ)
 				filename = "a0g1bsinitvals5";
 			else
 				filename = "a0g0bsinitvals5";
@@ -4569,7 +4749,7 @@ bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
 		addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
 	}
 
-	if (siba_get_revid(sc->sc_dev) >= 5) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
 		bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
 		bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
 	} else {
@@ -4694,8 +4874,11 @@ bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan)
 	if (status >= BWN_MAC_STATUS_INITED)
 		bwn_core_exit(down_dev);
 
-	if (down_dev != up_dev)
-		bwn_phy_reset(down_dev);
+	if (down_dev != up_dev) {
+		err = bwn_phy_reset(down_dev);
+		if (err)
+			goto fail;
+	}
 
 	up_dev->mac_phy.gmode = gmode;
 	if (status >= BWN_MAC_STATUS_INITED) {
@@ -4745,18 +4928,31 @@ bwn_rf_turnoff(struct bwn_mac *mac)
 /*
  * PHY reset.
  */
-static void
+static int
 bwn_phy_reset(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	struct bwn_softc	*sc;
+	uint16_t		 iost, mask;
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	iost = BWN_IOCTL_PHYRESET | BHND_IOCTL_CLK_FORCE;
+	mask = iost | BWN_IOCTL_SUPPORT_G;
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
+		return (error);
 
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW,
-	    ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) |
-	     BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC);
 	DELAY(1000);
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW,
-	    (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC));
+
+	iost &= ~BHND_IOCTL_CLK_FORCE;
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
+		return (error);
+
 	DELAY(1000);
+
+	return (0);
 }
 
 static int
@@ -4868,8 +5064,7 @@ bwn_intr(void *arg)
 
 	mac->mac_reason_intr = reason;
 
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
+	BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
 
 	taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask);
 	return (FILTER_HANDLED);
@@ -4982,8 +5177,7 @@ bwn_intrtask(void *arg, int npending)
 	if (mbufq_first(&sc->sc_snd) != NULL)
 		bwn_start(sc);
 
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
+	BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
 
 	BWN_UNLOCK(sc);
 }
@@ -5512,12 +5706,15 @@ bwn_pio_rxeof(struct bwn_pio_rxqueue *prq)
 	device_printf(sc->sc_dev, "%s: timed out\n", __func__);
 	return (1);
 ready:
-	if (prq->prq_rev >= 8)
-		siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr),
-		    prq->prq_base + BWN_PIO8_RXDATA);
-	else
-		siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr),
-		    prq->prq_base + BWN_PIO_RXDATA);
+	if (prq->prq_rev >= 8) {
+		bus_read_multi_4(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO8_RXDATA, (void *)&rxhdr,
+		    sizeof(rxhdr));
+	} else {
+		bus_read_multi_2(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO_RXDATA, (void *)&rxhdr,
+		    sizeof(rxhdr));
+	}
 	len = le16toh(rxhdr.frame_len);
 	if (len > 0x700) {
 		device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
@@ -5555,8 +5752,8 @@ ready:
 	}
 	mp = mtod(m, unsigned char *);
 	if (prq->prq_rev >= 8) {
-		siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3),
-		    prq->prq_base + BWN_PIO8_RXDATA);
+		bus_read_multi_4(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO8_RXDATA, (void *)mp, (totlen & ~3));
 		if (totlen & 3) {
 			v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
 			data = &(mp[totlen - 1]);
@@ -5572,8 +5769,8 @@ ready:
 			}
 		}
 	} else {
-		siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1),
-		    prq->prq_base + BWN_PIO_RXDATA);
+		bus_read_multi_2(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO_RXDATA, (void *)mp, (totlen & ~1));
 		if (totlen & 1) {
 			v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
 			mp[totlen - 1] = v16;
@@ -5741,8 +5938,8 @@ bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi,
 			else
 				tmp -= 3;
 		} else {
-			if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev)
-			    & BWN_BFL_RSSI) {
+			if (mac->mac_sc->sc_board_info.board_flags
+			    & BHND_BFL_ADCDIV) {
 				if (in_rssi > 63)
 					in_rssi = 63;
 				tmp = gphy->pg_nrssi_lt[in_rssi];
@@ -6043,8 +6240,8 @@ bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
 		return;
 	phy->nexttime = now + 2 * 1000;
 
-	if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
-	    siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306)
+	if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM &&
+	    sc->sc_board_info.board_type == BHND_BOARD_BU4306)
 		return;
 
 	if (phy->recalc_txpwr != NULL) {
@@ -6527,9 +6724,9 @@ bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
 	if (n == 0)
 		return (0);
 	if (mac->mac_phy.gmode)
-		mask = siba_sprom_get_ant_bg(sc->sc_dev);
+		mask = sc->sc_ant2g;
 	else
-		mask = siba_sprom_get_ant_a(sc->sc_dev);
+		mask = sc->sc_ant5g;
 	if (!(mask & (1 << (n - 1))))
 		return (0);
 	return (n);
@@ -6588,8 +6785,8 @@ bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
 	    BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
 	bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
 
-	siba_write_multi_4(sc->sc_dev, data, (len & ~3),
-	    tq->tq_base + BWN_PIO8_TXDATA);
+	bus_write_multi_4(sc->sc_mem_res, tq->tq_base + BWN_PIO8_TXDATA,
+	    __DECONST(void *, data), (len & ~3));
 	if (len & 3) {
 		ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
 		    BWN_PIO8_TXCTL_24_31);
@@ -6631,8 +6828,8 @@ bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
 	ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
 	BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
 
-	siba_write_multi_2(sc->sc_dev, data, (len & ~1),
-	    tq->tq_base + BWN_PIO_TXDATA);
+	bus_write_multi_2(sc->sc_mem_res, tq->tq_base + BWN_PIO_TXDATA,
+	    __DECONST(void *, data), (len & ~1));
 	if (len & 1) {
 		ctl &= ~BWN_PIO_TXCTL_WRITEHI;
 		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
@@ -6941,7 +7138,7 @@ bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
 {
 	uint32_t low, high;
 
-	KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3,
+	KASSERT(bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 3,
 	    ("%s:%d: fail", __func__, __LINE__));
 
 	low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
@@ -6954,30 +7151,98 @@ bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
 static int
 bwn_dma_attach(struct bwn_mac *mac)
 {
-	struct bwn_dma *dma = &mac->mac_method.dma;
-	struct bwn_softc *sc = mac->mac_sc;
-	bus_addr_t lowaddr = 0;
-	int error;
+	struct bwn_dma			*dma;
+	struct bwn_softc		*sc;
+	struct bhnd_dma_translation	*dt, dma_translation;
+	bhnd_addr_t			 addrext_req;
+	bus_dma_tag_t			 dmat;
+	bus_addr_t			 lowaddr;
+	u_int				 addrext_shift, addr_width;
+	int				 error;
 
-	if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
+	dma = &mac->mac_method.dma;
+	sc = mac->mac_sc;
+	dt = NULL;
+
+	if (sc->sc_quirks & BWN_QUIRK_NODMA)
 		return (0);
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, ("%s: fail", __func__));
+
+	/* Use the DMA engine's maximum host address width to determine the
+	 * addrext constraints, and supported device address width. */
+	switch (mac->mac_dmatype) {
+	case BHND_DMA_ADDR_30BIT:
+		/* 32-bit engine without addrext support */
+		addrext_req = 0x0;
+		addrext_shift = 0;
+
+		/* We can address the full 32-bit device address space */
+		addr_width = BHND_DMA_ADDR_32BIT;
+		break;
 
+	case BHND_DMA_ADDR_32BIT:
+		/* 32-bit engine with addrext support */
+		addrext_req = BWN_DMA32_ADDREXT_MASK;
+		addrext_shift = BWN_DMA32_ADDREXT_SHIFT;
+		addr_width = BHND_DMA_ADDR_32BIT;
+		break;
+
+	case BHND_DMA_ADDR_64BIT:
+		/* 64-bit engine with addrext support */
+		addrext_req = BWN_DMA64_ADDREXT_MASK;
+		addrext_shift = BWN_DMA64_ADDREXT_SHIFT;
+		addr_width = BHND_DMA_ADDR_64BIT;
+		break;
+
+	default:
+		device_printf(sc->sc_dev, "unsupported DMA address width: %d\n",
+		    mac->mac_dmatype);
+		return (ENXIO);
+	}
+
+
+	/* Fetch our device->host DMA translation and tag */
+	error = bhnd_get_dma_translation(sc->sc_dev, addr_width, 0, &dmat,
+	    &dma_translation);
+	if (error) {
+		device_printf(sc->sc_dev, "error fetching DMA translation: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	/* Verify that our DMA engine's addrext constraints are compatible with
+	 * our DMA translation */
+	if (addrext_req != 0x0 &&
+	    (dma_translation.addrext_mask & addrext_req) != addrext_req)
+	{
+		device_printf(sc->sc_dev, "bus addrext mask %#jx incompatible "
+		    "with device addrext mask %#jx, disabling extended address "
+		    "support\n", (uintmax_t)dma_translation.addrext_mask,
+		    (uintmax_t)addrext_req);
+
+		addrext_req = 0x0;
+		addrext_shift = 0;
+	}
+
+	/* Apply our addrext translation constraint */
+	dma_translation.addrext_mask = addrext_req;
+
+	/* Initialize our DMA engine configuration */
 	mac->mac_flags |= BWN_MAC_FLAG_DMA;
 
-	dma->dmatype = bwn_dma_gettype(mac);
-	if (dma->dmatype == BWN_DMA_30BIT)
-		lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT;
-	else if (dma->dmatype == BWN_DMA_32BIT)
-		lowaddr = BUS_SPACE_MAXADDR_32BIT;
-	else
-		lowaddr = BUS_SPACE_MAXADDR;
+	dma->addrext_shift = addrext_shift;
+	dma->translation = dma_translation;
+
+	dt = &dma->translation;
+
+	/* Dermine our translation's maximum supported address */
+	lowaddr = MIN((dt->addr_mask | dt->addrext_mask), BUS_SPACE_MAXADDR);
 
 	/*
 	 * Create top level DMA tag
 	 */
-	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),	/* parent */
+	error = bus_dma_tag_create(dmat,		/* parent */
 			       BWN_ALIGN, 0,		/* alignment, bounds */
 			       lowaddr,			/* lowaddr */
 			       BUS_SPACE_MAXADDR,	/* highaddr */
@@ -7029,26 +7294,26 @@ bwn_dma_attach(struct bwn_mac *mac)
 		goto fail1;
 	}
 
-	dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype);
+	dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1);
 	if (!dma->wme[WME_AC_BK])
 		goto fail2;
 
-	dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype);
+	dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1);
 	if (!dma->wme[WME_AC_BE])
 		goto fail3;
 
-	dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype);
+	dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1);
 	if (!dma->wme[WME_AC_VI])
 		goto fail4;
 
-	dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype);
+	dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1);
 	if (!dma->wme[WME_AC_VO])
 		goto fail5;
 
-	dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype);
+	dma->mcast = bwn_dma_ringsetup(mac, 4, 1);
 	if (!dma->mcast)
 		goto fail6;
-	dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype);
+	dma->rx = bwn_dma_ringsetup(mac, 0, 0);
 	if (!dma->rx)
 		goto fail7;
 
@@ -7157,19 +7422,19 @@ bwn_pio_stop(struct bwn_mac *mac)
 	bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
 }
 
-static void
+static int
 bwn_led_attach(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	const uint8_t *led_act = NULL;
-	uint16_t val[BWN_LED_MAX];
+	int error;
 	int i;
 
 	sc->sc_led_idle = (2350 * hz) / 1000;
 	sc->sc_led_blink = 1;
 
 	for (i = 0; i < N(bwn_vendor_led_act); ++i) {
-		if (siba_get_pci_subvendor(sc->sc_dev) ==
+		if (sc->sc_board_info.board_vendor ==
 		    bwn_vendor_led_act[i].vid) {
 			led_act = bwn_vendor_led_act[i].led_act;
 			break;
@@ -7178,20 +7443,31 @@ bwn_led_attach(struct bwn_mac *mac)
 	if (led_act == NULL)
 		led_act = bwn_default_led_act;
 
-	val[0] = siba_sprom_get_gpio0(sc->sc_dev);
-	val[1] = siba_sprom_get_gpio1(sc->sc_dev);
-	val[2] = siba_sprom_get_gpio2(sc->sc_dev);
-	val[3] = siba_sprom_get_gpio3(sc->sc_dev);
+	_Static_assert(nitems(bwn_led_vars) == BWN_LED_MAX,
+	    "invalid NVRAM variable name array");
 
 	for (i = 0; i < BWN_LED_MAX; ++i) {
-		struct bwn_led *led = &sc->sc_leds[i];
+		struct bwn_led	*led;
+		uint8_t		 val;
+
+		led = &sc->sc_leds[i];
 
-		if (val[i] == 0xff) {
+		KASSERT(i < nitems(bwn_led_vars), ("unknown LED index"));
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev, bwn_led_vars[i],
+		    &val);
+		if (error) {
+			if (error != ENOENT) {
+				device_printf(sc->sc_dev, "NVRAM variable %s "
+				    "unreadable: %d", bwn_led_vars[i], error);
+				return (error);
+			}
+
+			/* Not found; use default */
 			led->led_act = led_act[i];
 		} else {
-			if (val[i] & BWN_LED_ACT_LOW)
+			if (val & BWN_LED_ACT_LOW)
 				led->led_flags |= BWN_LED_F_ACTLOW;
-			led->led_act = val[i] & BWN_LED_ACT_MASK;
+			led->led_act = val & BWN_LED_ACT_MASK;
 		}
 		led->led_mask = (1 << i);
 
@@ -7216,6 +7492,8 @@ bwn_led_attach(struct bwn_mac *mac)
 		    led->led_act, led->led_flags & BWN_LED_F_ACTLOW);
 	}
 	callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
+
+	return (0);
 }
 
 static __inline uint16_t
@@ -7486,15 +7764,14 @@ static device_method_t bwn_methods[] = {
 	DEVMETHOD(device_resume,	bwn_resume),
 	DEVMETHOD_END
 };
-driver_t bwn_driver = {
+static driver_t bwn_driver = {
 	"bwn",
 	bwn_methods,
 	sizeof(struct bwn_softc)
 };
 static devclass_t bwn_devclass;
-DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0);
-MODULE_DEPEND(bwn, bwn_pci, 1, 1, 1);
-MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1);
+DRIVER_MODULE(bwn, bhnd, bwn_driver, bwn_devclass, 0, 0);
+MODULE_DEPEND(bwn, bhnd, 1, 1, 1);
 MODULE_DEPEND(bwn, gpiobus, 1, 1, 1);
 MODULE_DEPEND(bwn, wlan, 1, 1, 1);		/* 802.11 media layer */
 MODULE_DEPEND(bwn, firmware, 1, 1, 1);		/* firmware support */
diff --git a/sys/dev/bwn/if_bwn_bhnd.c b/sys/dev/bwn/if_bwn_bhnd.c
deleted file mode 100644
index 305fee0243c9..000000000000
--- a/sys/dev/bwn/if_bwn_bhnd.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
- * Copyright (c) 2017 The FreeBSD Foundation
- * All rights reserved.
- * 
- * Portions of this software were developed by Landon Fuller
- * under sponsorship from the FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_bwn.h"
-#include "opt_wlan.h"
-
-#include <sys/param.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/systm.h>
-#include <sys/socket.h>
-#include <sys/sockio.h>
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <net/ethernet.h>
-#include <net/if.h>
-#include <net/if_var.h>
-#include <net/if_arp.h>
-#include <net/if_dl.h>
-#include <net/if_llc.h>
-#include <net/if_media.h>
-#include <net/if_types.h>
-
-#include <net80211/ieee80211_var.h>
-#include <net80211/ieee80211_radiotap.h>
-#include <net80211/ieee80211_regdomain.h>
-#include <net80211/ieee80211_phy.h>
-#include <net80211/ieee80211_ratectl.h>
-
-#include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/bhnd_ids.h>
-
-#include "if_bwnvar.h"
-
-/* Supported device identifiers */
-#define	BWN_DEV(_hwrev)	{{					\
-	BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11),	\
-	BHND_MATCH_CORE_REV(_hwrev),				\
-}}
-
-static const struct bhnd_device bwn_devices[] = {
-	BWN_DEV(HWREV_RANGE(5, 16)),
-	BWN_DEV(HWREV_EQ(23)),
-
-	BHND_DEVICE_END
-};
-
-static int
-bwn_bhnd_probe(device_t dev)
-{
-	const struct bhnd_device *id;
-
-	id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0]));
-	if (id == NULL)
-		return (ENXIO);
-
-	bhnd_set_default_core_desc(dev);
-	return (BUS_PROBE_DEFAULT);
-}
-
-static device_method_t bwn_bhnd_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		bwn_bhnd_probe),
-
-	DEVMETHOD_END
-};
-
-static devclass_t bwn_devclass;
-
-DEFINE_CLASS_1(bwn, bwn_bhnd_driver, bwn_bhnd_methods, sizeof(struct bwn_softc),
-    bwn_driver);
-
-DRIVER_MODULE(bwn_bhnd, bhnd, bwn_bhnd_driver, bwn_devclass, 0, 0);
-MODULE_DEPEND(bwn_bhnd, bhnd, 1, 1, 1);
-MODULE_VERSION(bwn_bhnd, 1);
diff --git a/sys/dev/bwn/if_bwn_chipid.h b/sys/dev/bwn/if_bwn_chipid.h
deleted file mode 100644
index 333c980e2d6b..000000000000
--- a/sys/dev/bwn/if_bwn_chipid.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*-
- * Copyright (c) 2016 Adrian Chadd <adrian@FreeBSD.org>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification.
- * 2. Redistributions in binary form must reproduce at minimum a disclaimer
- *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
- *    redistribution must be conditioned upon including a substantially
- *    similar Disclaimer requirement for further binary redistribution.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
- * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGES.
- *
- * $FreeBSD$
- */
-#ifndef	__IF_BWN_CHIPID_H__
-#define	__IF_BWN_CHIPID_H__
-
-/*
- * BCMA chip identifiers.
- */
-#define	BCMA_CHIP_ID_BCM4313		0x4313
-#define	BCMA_CHIP_ID_BCM43142		43142
-#define	BCMA_CHIP_ID_BCM43131		43131
-#define	BCMA_CHIP_ID_BCM43217		43217
-#define	BCMA_CHIP_ID_BCM43222		43222
-#define	BCMA_CHIP_ID_BCM43224		43224
-#define	 BCMA_PKG_ID_BCM43224_FAB_CSM	0x8
-#define	 BCMA_PKG_ID_BCM43224_FAB_SMIC	0xa
-#define	BCMA_CHIP_ID_BCM43225		43225
-#define	BCMA_CHIP_ID_BCM43227		43227
-#define	BCMA_CHIP_ID_BCM43228		43228
-#define	BCMA_CHIP_ID_BCM43421		43421
-#define	BCMA_CHIP_ID_BCM43428		43428
-#define	BCMA_CHIP_ID_BCM43431		43431
-#define	BCMA_CHIP_ID_BCM43460		43460
-#define	BCMA_CHIP_ID_BCM4331		0x4331
-#define	BCMA_CHIP_ID_BCM6362		0x6362
-#define	BCMA_CHIP_ID_BCM4360		0x4360
-#define	BCMA_CHIP_ID_BCM4352		0x4352
-#define	BCMA_CHIP_ID_BCM4706		0x5300
-#define	BCMA_CHIP_ID_BCM4716		0x4716
-#define	BCMA_CHIP_ID_BCM47162		47162
-#define	BCMA_CHIP_ID_BCM4748		0x4748
-#define	BCMA_CHIP_ID_BCM4749		0x4749
-#define	BCMA_CHIP_ID_BCM5356		0x5356
-#define	BCMA_CHIP_ID_BCM5357		0x5357
-#define	BCMA_CHIP_ID_BCM53572		53572
-#define	BCMA_CHIP_ID_BCM4707		53010
-#define	BCMA_CHIP_ID_BCM47094		53030
-#define	BCMA_CHIP_ID_BCM53018		53018
-
-#define	BCMA_BOARD_TYPE_BCM943224M93		0x008B
-#define	BCMA_BOARD_TYPE_BCM943224M93A		0x0090
-
-#endif	/* __IF_BWN_CHIPID_H__ */
diff --git a/sys/dev/bwn/if_bwn_misc.h b/sys/dev/bwn/if_bwn_misc.h
index 37df75f21414..76d6b8445524 100644
--- a/sys/dev/bwn/if_bwn_misc.h
+++ b/sys/dev/bwn/if_bwn_misc.h
@@ -40,6 +40,8 @@
 
 struct bwn_mac;
 
+extern int	bwn_gpio_control(struct bwn_mac *, uint32_t);
+
 extern uint64_t	bwn_hf_read(struct bwn_mac *);
 extern void	bwn_hf_write(struct bwn_mac *, uint64_t);
 
@@ -59,8 +61,7 @@ extern uint32_t	bwn_shm_read_4(struct bwn_mac *, uint16_t, uint16_t);
 extern void	bwn_shm_write_4(struct bwn_mac *, uint16_t, uint16_t,
 		    uint32_t);
 
-/* This is only for SIBA core */
-extern	void bwn_reset_core(struct bwn_mac *, int g_mode);
+extern int	bwn_reset_core(struct bwn_mac *, int g_mode);
 
 extern void	bwn_psctl(struct bwn_mac *, uint32_t);
 
diff --git a/sys/dev/bwn/if_bwn_pci.c b/sys/dev/bwn/if_bwn_pci.c
index 41489603bf74..6aa8dd734443 100644
--- a/sys/dev/bwn/if_bwn_pci.c
+++ b/sys/dev/bwn/if_bwn_pci.c
@@ -54,10 +54,6 @@ __FBSDID("$FreeBSD$");
 static int attach_untested = 0; 
 TUNABLE_INT("hw.bwn_pci.attach_untested", &attach_untested);
 
-/* If non-zero, probe at a higher priority than the stable if_bwn driver. */
-static int prefer_new_driver = 1;
-TUNABLE_INT("hw.bwn_pci.preferred", &prefer_new_driver);
-
 /* SIBA Devices */
 static const struct bwn_pci_device siba_devices[] = {
 	BWN_BCM_DEV(BCM4306_D11A,	"BCM4306 802.11a",
@@ -169,15 +165,7 @@ bwn_pci_probe(device_t dev)
 		return (ENXIO);
 
 	device_set_desc(dev, ident->desc);
-
-	/* Until this driver is complete, require explicit opt-in before
-	 * superceding if_bwn/siba_bwn. */
-	if (prefer_new_driver)
-		return (BUS_PROBE_DEFAULT+1);
-	else
-		return (BUS_PROBE_LOW_PRIORITY);
-
-	// return (BUS_PROBE_DEFAULT);
+	return (BUS_PROBE_DEFAULT);
 }
 
 static int
@@ -309,6 +297,7 @@ DRIVER_MODULE_ORDERED(bwn_pci, pci, bwn_pci_driver, bwn_pci_devclass, NULL,
     NULL, SI_ORDER_ANY);
 DRIVER_MODULE(bhndb, bwn_pci, bhndb_pci_driver, bhndb_devclass, NULL, NULL);
 
+MODULE_DEPEND(bwn_pci, bwn, 1, 1, 1);
 MODULE_DEPEND(bwn_pci, bhnd, 1, 1, 1);
 MODULE_DEPEND(bwn_pci, bhndb, 1, 1, 1);
 MODULE_DEPEND(bwn_pci, bhndb_pci, 1, 1, 1);
diff --git a/sys/dev/bwn/if_bwn_phy_common.c b/sys/dev/bwn/if_bwn_phy_common.c
index 22dde9f95d24..704348f19294 100644
--- a/sys/dev/bwn/if_bwn_phy_common.c
+++ b/sys/dev/bwn/if_bwn_phy_common.c
@@ -73,65 +73,72 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/chipc/chipc.h>
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
-#include <dev/bwn/if_bwn_chipid.h>
 #include <dev/bwn/if_bwn_debug.h>
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_phy_common.h>
 
 void
-bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode)
+bwn_mac_switch_freq(struct bwn_mac *mac, bhnd_pmu_spuravoid spurmode)
 {
 	struct bwn_softc *sc = mac->mac_sc;
-	uint16_t chip_id = siba_get_chipid(sc->sc_dev);
+	uint16_t chip_id = sc->sc_cid.chip_id;
 
-	if (chip_id == BCMA_CHIP_ID_BCM4331) {
+	if (chip_id == BHND_CHIPID_BCM4331) {
 		switch (spurmode) {
-		case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
+		case BHND_PMU_SPURAVOID_M2: /* 168 Mhz: 2^26/168 = 0x61862 */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x1862);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6);
 			break;
-		case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
+		case BHND_PMU_SPURAVOID_M1: /* 164 Mhz: 2^26/164 = 0x63e70 */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x3e70);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6);
 			break;
-		default: /* 160 Mhz: 2^26/160 = 0x66666 */
+		case BHND_PMU_SPURAVOID_NONE: /* 160 Mhz: 2^26/160 = 0x66666 */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x6666);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6);
 			break;
 		}
-	} else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
-	    chip_id == BCMA_CHIP_ID_BCM43217 ||
-	    chip_id == BCMA_CHIP_ID_BCM43222 ||
-	    chip_id == BCMA_CHIP_ID_BCM43224 ||
-	    chip_id == BCMA_CHIP_ID_BCM43225 ||
-	    chip_id == BCMA_CHIP_ID_BCM43227 ||
-	    chip_id == BCMA_CHIP_ID_BCM43228) {
+	} else if (chip_id == BHND_CHIPID_BCM43131 ||
+	    chip_id == BHND_CHIPID_BCM43217 ||
+	    chip_id == BHND_CHIPID_BCM43222 ||
+	    chip_id == BHND_CHIPID_BCM43224 ||
+	    chip_id == BHND_CHIPID_BCM43225 ||
+	    chip_id == BHND_CHIPID_BCM43227 ||
+	    chip_id == BHND_CHIPID_BCM43228) {
 		switch (spurmode) {
-		case 2: /* 126 Mhz */
+		case BHND_PMU_SPURAVOID_M2: /* 126 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x2082);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8);
 			break;
-		case 1: /* 123 Mhz */
+		case BHND_PMU_SPURAVOID_M1: /* 123 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x5341);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8);
 			break;
-		default: /* 120 Mhz */
+		case BHND_PMU_SPURAVOID_NONE: /* 120 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x8889);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8);
 			break;
 		}
 	} else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) {
 		switch (spurmode) {
-		case 1: /* 82 Mhz */
+		case BHND_PMU_SPURAVOID_M2:
+			device_printf(sc->sc_dev, "invalid spuravoid mode: "
+			    "%d\n", spurmode);
+			break;
+		case BHND_PMU_SPURAVOID_M1: /* 82 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x7CE0);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC);
 			break;
-		default: /* 80 Mhz */
+		case BHND_PMU_SPURAVOID_NONE: /* 80 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0xCCCD);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC);
 			break;
@@ -140,20 +147,30 @@ bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode)
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
-void
+int
 bwn_phy_force_clock(struct bwn_mac *mac, int force)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t tmp;
+	struct bwn_softc	*sc;
+	uint32_t		 val, mask;
+	int			 error;
+
+	sc = mac->mac_sc;
 
 	/* XXX Only for N, HT and AC PHYs */
+	mask = BHND_IOCTL_CLK_FORCE;
+	if (force) {
+		val = BHND_IOCTL_CLK_FORCE;
+	} else {
+		val = 0;
+	}
 
-	tmp = siba_read_4(sc->sc_dev, SIBA_TGSLOW);
-	if (force)
-		tmp |= SIBA_TGSLOW_FGC;
-	else
-		tmp &= ~SIBA_TGSLOW_FGC;
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, tmp);
+	if ((error = bhnd_write_ioctl(sc->sc_dev, val, mask))) {
+		device_printf(sc->sc_dev, "failed to set CLK_FORCE ioctl flag: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	return (0);
 }
 
 int
@@ -172,28 +189,49 @@ bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset, uint16_t mask,
 	return (0);
 }
 
-void
+int
 bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t val;
-
-	val = siba_read_4(sc->sc_dev, SIBA_TGSLOW);
-	if (enabled)
-		    val |= BWN_TGSLOW_MACPHYCLKEN;
-	else
-		    val &= ~BWN_TGSLOW_MACPHYCLKEN;
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, val);
+	struct bwn_softc	*sc;
+	uint32_t		 val, mask;
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	mask = BWN_IOCTL_MACPHYCLKEN;
+	if (enabled) {
+		val = BWN_IOCTL_MACPHYCLKEN;
+	} else {
+		val = 0;
+	}
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, val, mask))) {
+		device_printf(sc->sc_dev, "failed to set MACPHYCLKEN ioctl "
+		    "flag: %d\n", error);
+		return (error);
+	}
+
+	return (0);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
-void
+int
 bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	struct bwn_softc	*sc;
+	uint32_t		 pll_flag;
 
-	siba_cc_write32(sc->sc_dev, SIBA_CC_CHIPCTL_ADDR, 0);
-	siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4);
-	siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, 0x4);
-	siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4);
+	sc = mac->mac_sc;
+
+	if (sc->sc_pmu == NULL) {
+		device_printf(sc->sc_dev, "PMU device not found\n");
+		return (ENXIO);
+	}
+
+	pll_flag = 0x4;
+	bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, 0x0, pll_flag);
+	bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, pll_flag, pll_flag);	
+	bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, 0x0, pll_flag);
+
+	return (0);
 }
diff --git a/sys/dev/bwn/if_bwn_phy_common.h b/sys/dev/bwn/if_bwn_phy_common.h
index 687fc78388bb..a10976b2b62c 100644
--- a/sys/dev/bwn/if_bwn_phy_common.h
+++ b/sys/dev/bwn/if_bwn_phy_common.h
@@ -31,11 +31,12 @@
 #ifndef	__PHY_COMMON_H__
 #define	__PHY_COMMON_H__
 
-extern	void bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode);
-extern	void bwn_phy_force_clock(struct bwn_mac *mac, int force);
+extern	void bwn_mac_switch_freq(struct bwn_mac *mac,
+	    bhnd_pmu_spuravoid spurmode);
+extern	int bwn_phy_force_clock(struct bwn_mac *mac, int force);
 extern	int bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset,
 	    uint16_t mask, uint16_t value, int delay, int timeout);
-extern	void bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled);
-extern	void bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac);
+extern	int bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled);
+extern	int bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac);
 
 #endif	/* __PHY_COMMON_H__ */
diff --git a/sys/dev/bwn/if_bwn_phy_g.c b/sys/dev/bwn/if_bwn_phy_g.c
index f0e76f6ec82d..280e52156974 100644
--- a/sys/dev/bwn/if_bwn_phy_g.c
+++ b/sys/dev/bwn/if_bwn_phy_g.c
@@ -72,8 +72,6 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
-
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
@@ -81,6 +79,8 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_phy_g.h>
 
+#include "bhnd_nvram_map.h"
+
 static void	bwn_phy_g_init_sub(struct bwn_mac *);
 static uint8_t	bwn_has_hwpctl(struct bwn_mac *);
 static void	bwn_phy_init_b5(struct bwn_mac *);
@@ -157,14 +157,27 @@ bwn_phy_g_attach(struct bwn_mac *mac)
 	int16_t pab0, pab1, pab2;
 	static int8_t bwn_phy_g_tssi2dbm_table[] = BWN_PHY_G_TSSI2DBM_TABLE;
 	int8_t bg;
-
-	bg = (int8_t)siba_sprom_get_tssi_bg(sc->sc_dev);
-	pab0 = (int16_t)siba_sprom_get_pa0b0(sc->sc_dev);
-	pab1 = (int16_t)siba_sprom_get_pa0b1(sc->sc_dev);
-	pab2 = (int16_t)siba_sprom_get_pa0b2(sc->sc_dev);
-
-	if ((siba_get_chipid(sc->sc_dev) == 0x4301) && (phy->rf_ver != 0x2050))
-		device_printf(sc->sc_dev, "not supported anymore\n");
+	int error;
+
+	/* Fetch SPROM configuration */
+#define	BWN_PHY_G_READVAR(_dev, _type, _name, _result)		\
+do {									\
+	error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result));	\
+	if (error) {							\
+		device_printf((_dev), "NVRAM variable %s unreadable: "	\
+		    "%d\n", (_name), error);				\
+		return (error);						\
+	}								\
+} while(0)
+
+	BWN_PHY_G_READVAR(sc->sc_dev, int8, BHND_NVAR_PA0ITSSIT, &bg);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B0, &pab0);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B1, &pab1);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B2, &pab2);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0MAXPWR,
+	    &pg->pg_pa0maxpwr);
+
+#undef	BWN_PHY_G_READVAR
 
 	pg->pg_flags = 0;
 	if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 ||
@@ -289,12 +302,12 @@ bwn_phy_g_prepare_hw(struct bwn_mac *mac)
 	/* prepare Radio Attenuation */
 	pg->pg_rfatt.padmix = 0;
 
-	if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
-	    siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4309G) {
-		if (siba_get_pci_revid(sc->sc_dev) < 0x43) {
+	if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM &&
+	    sc->sc_board_info.board_type == BHND_BOARD_BCM94309G) {
+		if (sc->sc_board_info.board_rev < 0x43) {
 			pg->pg_rfatt.att = 2;
 			goto done;
-		} else if (siba_get_pci_revid(sc->sc_dev) < 0x51) {
+		} else if (sc->sc_board_info.board_rev < 0x51) {
 			pg->pg_rfatt.att = 3;
 			goto done;
 		}
@@ -313,25 +326,25 @@ bwn_phy_g_prepare_hw(struct bwn_mac *mac)
 			goto done;
 		case 1:
 			if (phy->type == BWN_PHYTYPE_G) {
-				if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BCM4309G &&
-				    siba_get_pci_revid(sc->sc_dev) >= 30)
+				if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BCM94309G &&
+				    sc->sc_board_info.board_rev >= 30)
 					pg->pg_rfatt.att = 3;
-				else if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BU4306)
+				else if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BU4306)
 					pg->pg_rfatt.att = 3;
 				else
 					pg->pg_rfatt.att = 1;
 			} else {
-				if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BCM4309G &&
-				    siba_get_pci_revid(sc->sc_dev) >= 30)
+				if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BCM94309G &&
+				    sc->sc_board_info.board_rev >= 30)
 					pg->pg_rfatt.att = 7;
 				else
 					pg->pg_rfatt.att = 6;
@@ -339,18 +352,19 @@ bwn_phy_g_prepare_hw(struct bwn_mac *mac)
 			goto done;
 		case 2:
 			if (phy->type == BWN_PHYTYPE_G) {
-				if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BCM4309G &&
-				    siba_get_pci_revid(sc->sc_dev) >= 30)
+				if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BCM94309G &&
+				    sc->sc_board_info.board_rev >= 30)
 					pg->pg_rfatt.att = 3;
-				else if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BU4306)
+				else if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BU4306)
 					pg->pg_rfatt.att = 5;
-				else if (siba_get_chipid(sc->sc_dev) == 0x4320)
+				else if (sc->sc_cid.chip_id ==
+				    BHND_CHIPID_BCM4320)
 					pg->pg_rfatt.att = 4;
 				else
 					pg->pg_rfatt.att = 3;
@@ -656,13 +670,13 @@ bwn_phy_g_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi)
 	pg->pg_avgtssi = tssi;
 	KASSERT(tssi < BWN_TSSI_MAX, ("%s:%d: fail", __func__, __LINE__));
 
-	max = siba_sprom_get_maxpwr_bg(sc->sc_dev);
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
+	max = pg->pg_pa0maxpwr;
+	if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
 		max -= 3;
 	if (max >= 120) {
 		device_printf(sc->sc_dev, "invalid max TX-power value\n");
 		max = 80;
-		siba_sprom_set_maxpwr_bg(sc->sc_dev, max);
+		pg->pg_pa0maxpwr = max;
 	}
 
 	power = MIN(MAX((phy->txpower < 0) ? 0 : (phy->txpower << 2), 0), max) -
@@ -706,8 +720,8 @@ bwn_phy_g_set_txpwr(struct bwn_mac *mac)
 				txctl = BWN_TXCTL_PA2DB | BWN_TXCTL_TXMIX;
 				rfatt += 2;
 				bbatt += 2;
-			} else if (siba_sprom_get_bf_lo(sc->sc_dev) &
-			    BWN_BFL_PACTRL) {
+			} else if (sc->sc_board_info.board_flags &
+			    BHND_BFL_PACTRL) {
 				bbatt += 4 * (rfatt - 2);
 				rfatt = 2;
 			}
@@ -805,7 +819,7 @@ bwn_phy_g_task_60s(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	uint8_t old = phy->chan;
 
-	if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI))
+	if (!(sc->sc_board_info.board_flags & BHND_BFL_ADCDIV))
 		return;
 
 	bwn_mac_suspend(mac);
@@ -892,7 +906,7 @@ bwn_phy_g_init_sub(struct bwn_mac *mac)
 		BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x36), 0x0fff,
 		    (pg->pg_loctl.tx_bias << 12));
 	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
+	if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
 		BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8075);
 	else
 		BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x807f);
@@ -905,7 +919,7 @@ bwn_phy_g_init_sub(struct bwn_mac *mac)
 		BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8078);
 	}
 
-	if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) {
+	if (!(sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) {
 		for (i = 0; i < 64; i++) {
 			BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_CTRL, i);
 			BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_DATA,
@@ -924,8 +938,8 @@ bwn_phy_g_init_sub(struct bwn_mac *mac)
 	if (phy->rf_rev == 8)
 		BWN_PHY_WRITE(mac, BWN_PHY_EXTG(0x05), 0x3230);
 	bwn_phy_hwpctl_init(mac);
-	if ((siba_get_chipid(sc->sc_dev) == 0x4306
-	     && siba_get_chippkg(sc->sc_dev) == 2) || 0) {
+	if ((sc->sc_cid.chip_id == BHND_CHIPID_BCM4306
+	     && sc->sc_cid.chip_pkg == 2) || 0) {
 		BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0xbfff);
 		BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xc3), 0x7fff);
 	}
@@ -942,8 +956,8 @@ bwn_phy_init_b5(struct bwn_mac *mac)
 
 	if (phy->analog == 1)
 		BWN_RF_SET(mac, 0x007a, 0x0050);
-	if ((siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM) &&
-	    (siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306)) {
+	if ((sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM) &&
+	    (sc->sc_board_info.board_type != BHND_BOARD_BU4306)) {
 		value = 0x2120;
 		for (offset = 0x00a8; offset < 0x00c7; offset++) {
 			BWN_PHY_WRITE(mac, offset, value);
@@ -1111,7 +1125,7 @@ bwn_loopback_calcgain(struct bwn_mac *mac)
 	BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0100);
 	BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xcfff);
 
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) {
+	if (sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) {
 		if (phy->rev >= 7) {
 			BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0800);
 			BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x8000);
@@ -1441,7 +1455,7 @@ bwn_phy_init_b6(struct bwn_mac *mac)
 		BWN_RF_WRITE(mac, 0x5a, 0x88);
 		BWN_RF_WRITE(mac, 0x5b, 0x6b);
 		BWN_RF_WRITE(mac, 0x5c, 0x0f);
-		if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_ALTIQ) {
+		if (sc->sc_board_info.board_flags & BHND_BFL_ALTIQ) {
 			BWN_RF_WRITE(mac, 0x5d, 0xfa);
 			BWN_RF_WRITE(mac, 0x5e, 0xd8);
 		} else {
@@ -1539,7 +1553,7 @@ bwn_phy_init_a(struct bwn_mac *mac)
 	bwn_wa_init(mac);
 
 	if (phy->type == BWN_PHYTYPE_G &&
-	    (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL))
+	    (sc->sc_board_info.board_flags & BHND_BFL_PACTRL))
 		BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x6e), 0xe000, 0x3cf);
 }
 
@@ -1809,9 +1823,9 @@ bwn_wa_init(struct bwn_mac *mac)
 		KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
 	}
 
-	if (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM ||
-	    siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306 ||
-	    siba_get_pci_revid(sc->sc_dev) != 0x17) {
+	if (sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM ||
+	    sc->sc_board_info.board_type != BHND_BOARD_BU4306 ||
+	    sc->sc_board_info.board_rev != 0x17) {
 		if (phy->rev < 2) {
 			bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 1,
 			    0x0002);
@@ -1820,8 +1834,8 @@ bwn_wa_init(struct bwn_mac *mac)
 		} else {
 			bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 1, 0x0002);
 			bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 2, 0x0001);
-			if ((siba_sprom_get_bf_lo(sc->sc_dev) &
-			     BWN_BFL_EXTLNA) &&
+			if ((sc->sc_board_info.board_flags &
+			     BHND_BFL_EXTLNA) &&
 			    (phy->rev >= 7)) {
 				BWN_PHY_MASK(mac, BWN_PHY_EXTG(0x11), 0xf7ff);
 				bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
@@ -1839,7 +1853,7 @@ bwn_wa_init(struct bwn_mac *mac)
 			}
 		}
 	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) {
+	if (sc->sc_board_info.board_flags & BHND_BFL_FEM) {
 		BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, 0x3120);
 		BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, 0xc480);
 	}
@@ -1927,7 +1941,7 @@ bwn_lo_calcfeed(struct bwn_mac *mac,
 		trsw_rx &= (BWN_PHY_RFOVERVAL_TRSWRX | BWN_PHY_RFOVERVAL_BW);
 
 		rfover = BWN_PHY_RFOVERVAL_UNK | pga | lna | trsw_rx;
-		if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) &&
+		if ((sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) &&
 		    phy->rev > 6)
 			rfover |= BWN_PHY_RFOVERVAL_EXTLNA;
 
@@ -2216,8 +2230,8 @@ bwn_lo_save(struct bwn_mac *mac, struct bwn_lo_g_value *sav)
 		BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffc);
 		if (phy->type == BWN_PHYTYPE_G) {
 			if ((phy->rev >= 7) &&
-			    (siba_sprom_get_bf_lo(sc->sc_dev) &
-			     BWN_BFL_EXTLNA)) {
+			    (sc->sc_board_info.board_flags &
+			     BHND_BFL_EXTLNA)) {
 				BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x933);
 			} else {
 				BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x133);
@@ -2675,7 +2689,7 @@ bwn_nrssi_threshold(struct bwn_mac *mac)
 
 	KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));
 
-	if (phy->gmode && (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) {
+	if (phy->gmode && (sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) {
 		if (!pg->pg_aci_wlan_automatic && pg->pg_aci_enable) {
 			a = 0x13;
 			b = 0x12;
@@ -3118,8 +3132,8 @@ bwn_phy_hwpctl_init(struct bwn_mac *mac)
 	KASSERT(phy->type == BWN_PHYTYPE_G,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	if ((siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM) &&
-	    (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306))
+	if ((sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM) &&
+	    (sc->sc_board_info.board_type == BHND_BOARD_BU4306))
 		return;
 
 	BWN_PHY_WRITE(mac, 0x0028, 0x8018);
@@ -3256,7 +3270,8 @@ bwn_hwpctl_init_gphy(struct bwn_mac *mac)
 static void
 bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	struct bwn_softc	*sc = mac->mac_sc;
+	int			 error;
 
 	if (spu != 0)
 		bwn_spu_workaround(mac, channel);
@@ -3264,7 +3279,17 @@ bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu)
 	BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel));
 
 	if (channel == 14) {
-		if (siba_sprom_get_ccode(sc->sc_dev) == SIBA_CCODE_JAPAN)
+		uint8_t cc;
+
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_CC, &cc);
+		if (error) {
+			device_printf(sc->sc_dev, "error reading country code "
+			    "from NVRAM, assuming channel 14 unavailable: %d\n",
+			    error);
+			cc = BWN_SPROM1_CC_WORLDWIDE;
+		}
+
+		if (cc == BWN_SPROM1_CC_JP)
 			bwn_hf_write(mac,
 			    bwn_hf_read(mac) & ~BWN_HF_JAPAN_CHAN14_OFF);
 		else
@@ -3381,7 +3406,7 @@ bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)
 		}
 
 		if ((phy->rev < 7) ||
-		    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) {
+		    !(sc->sc_board_info.board_flags & BHND_BFL_EXTLNA)) {
 			if (reg == BWN_PHY_RFOVER) {
 				return (0x1b3);
 			} else if (reg == BWN_PHY_RFOVERVAL) {
@@ -3425,7 +3450,7 @@ bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)
 	}
 
 	if ((phy->rev < 7) ||
-	    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) {
+	    !(sc->sc_board_info.board_flags & BHND_BFL_EXTLNA)) {
 		if (reg == BWN_PHY_RFOVER) {
 			return (0x1b3);
 		} else if (reg == BWN_PHY_RFOVERVAL) {
@@ -3562,8 +3587,8 @@ bwn_phy_lock(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct ieee80211com *ic = &sc->sc_ic;
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 3,
-	    ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev)));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 3,
+	    ("%s: unsupported rev %d", __func__, bhnd_get_hwrev(sc->sc_dev)));
 
 	if (ic->ic_opmode != IEEE80211_M_HOSTAP)
 		bwn_psctl(mac, BWN_PS_AWAKE);
@@ -3575,8 +3600,8 @@ bwn_phy_unlock(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct ieee80211com *ic = &sc->sc_ic;
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 3,
-	    ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev)));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 3,
+	    ("%s: unsupported rev %d", __func__, bhnd_get_hwrev(sc->sc_dev)));
 
 	if (ic->ic_opmode != IEEE80211_M_HOSTAP)
 		bwn_psctl(mac, 0);
diff --git a/sys/dev/bwn/if_bwn_phy_lp.c b/sys/dev/bwn/if_bwn_phy_lp.c
index 0faee2d8625d..bec003ee9fda 100644
--- a/sys/dev/bwn/if_bwn_phy_lp.c
+++ b/sys/dev/bwn/if_bwn_phy_lp.c
@@ -72,7 +72,10 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
@@ -83,7 +86,9 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_phy_common.h>
 #include <dev/bwn/if_bwn_phy_lp.h>
 
-static void	bwn_phy_lp_readsprom(struct bwn_mac *);
+#include "bhnd_nvram_map.h"
+
+static int	bwn_phy_lp_readsprom(struct bwn_mac *);
 static void	bwn_phy_lp_bbinit(struct bwn_mac *);
 static void	bwn_phy_lp_txpctl_init(struct bwn_mac *);
 static void	bwn_phy_lp_calib(struct bwn_mac *);
@@ -99,10 +104,10 @@ static void	bwn_phy_lp_digflt_restore(struct bwn_mac *);
 static void	bwn_phy_lp_tblinit(struct bwn_mac *);
 static void	bwn_phy_lp_bbinit_r2(struct bwn_mac *);
 static void	bwn_phy_lp_bbinit_r01(struct bwn_mac *);
-static void	bwn_phy_lp_b2062_init(struct bwn_mac *);
-static void	bwn_phy_lp_b2063_init(struct bwn_mac *);
-static void	bwn_phy_lp_rxcal_r2(struct bwn_mac *);
-static void	bwn_phy_lp_rccal_r12(struct bwn_mac *);
+static int	bwn_phy_lp_b2062_init(struct bwn_mac *);
+static int	bwn_phy_lp_b2063_init(struct bwn_mac *);
+static int	bwn_phy_lp_rxcal_r2(struct bwn_mac *);
+static int	bwn_phy_lp_rccal_r12(struct bwn_mac *);
 static void	bwn_phy_lp_set_rccap(struct bwn_mac *);
 static uint32_t	bwn_phy_lp_roundup(uint32_t, uint32_t, uint8_t);
 static void	bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *);
@@ -409,7 +414,16 @@ bwn_phy_lp_init(struct bwn_mac *mac)
 	int i, error;
 	uint16_t tmp;
 
-	bwn_phy_lp_readsprom(mac);	/* XXX bad place */
+	/* All LP-PHY devices have a PMU */
+	if (sc->sc_pmu == NULL) {
+		device_printf(sc->sc_dev, "no PMU; cannot configure PAREF "
+		    "LDO\n");
+		return (ENXIO);
+	}
+
+	if ((error = bwn_phy_lp_readsprom(mac)))
+		return (error);
+
 	bwn_phy_lp_bbinit(mac);
 
 	/* initialize RF */
@@ -418,10 +432,12 @@ bwn_phy_lp_init(struct bwn_mac *mac)
 	BWN_PHY_MASK(mac, BWN_PHY_4WIRECTL, 0xfffd);
 	DELAY(1);
 
-	if (mac->mac_phy.rf_ver == 0x2062)
-		bwn_phy_lp_b2062_init(mac);
-	else {
-		bwn_phy_lp_b2063_init(mac);
+	if (mac->mac_phy.rf_ver == 0x2062) {
+		if ((error = bwn_phy_lp_b2062_init(mac)))
+			return (error);
+	} else {
+		if ((error = bwn_phy_lp_b2063_init(mac)))
+			return (error);
 
 		/* synchronize stx table. */
 		for (i = 0; i < N(tables); i++) {
@@ -439,11 +455,14 @@ bwn_phy_lp_init(struct bwn_mac *mac)
 	}
 
 	/* calibrate RC */
-	if (mac->mac_phy.rev >= 2)
-		bwn_phy_lp_rxcal_r2(mac);
-	else if (!plp->plp_rccap) {
-		if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
-			bwn_phy_lp_rccal_r12(mac);
+	if (mac->mac_phy.rev >= 2) {
+		if ((error = bwn_phy_lp_rxcal_r2(mac)))
+			return (error);
+	} else if (!plp->plp_rccap) {
+		if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
+			if ((error = bwn_phy_lp_rccal_r12(mac)))
+				return (error);
+		}
 	} else
 		bwn_phy_lp_set_rccap(mac);
 
@@ -586,31 +605,62 @@ bwn_phy_lp_task_60s(struct bwn_mac *mac)
 	bwn_phy_lp_calib(mac);
 }
 
-static void
+static int
 bwn_phy_lp_readsprom(struct bwn_mac *mac)
 {
 	struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
 	struct bwn_softc *sc = mac->mac_sc;
 	struct ieee80211com *ic = &sc->sc_ic;
 
+#define	BWN_PHY_LP_READVAR(_dev, _type, _name, _result)		\
+do {									\
+	int error;							\
+									\
+	error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result));	\
+	if (error) {							\
+		device_printf((_dev), "NVRAM variable %s unreadable: "	\
+		    "%d\n", (_name), error);				\
+		return (error);						\
+	}								\
+} while(0)
+
 	if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
-		plp->plp_txisoband_m = siba_sprom_get_tri2g(sc->sc_dev);
-		plp->plp_bxarch = siba_sprom_get_bxa2g(sc->sc_dev);
-		plp->plp_rxpwroffset = siba_sprom_get_rxpo2g(sc->sc_dev);
-		plp->plp_rssivf = siba_sprom_get_rssismf2g(sc->sc_dev);
-		plp->plp_rssivc = siba_sprom_get_rssismc2g(sc->sc_dev);
-		plp->plp_rssigs = siba_sprom_get_rssisav2g(sc->sc_dev);
-		return;
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI2G,
+		    &plp->plp_txisoband_m);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA2G,
+		    &plp->plp_bxarch);
+		BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO2G,
+		    &plp->plp_rxpwroffset);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF2G,
+		    &plp->plp_rssivf);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC2G,
+		    &plp->plp_rssivc);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV2G,
+		    &plp->plp_rssigs);
+
+		return (0);
 	}
 
-	plp->plp_txisoband_l = siba_sprom_get_tri5gl(sc->sc_dev);
-	plp->plp_txisoband_m = siba_sprom_get_tri5g(sc->sc_dev);
-	plp->plp_txisoband_h = siba_sprom_get_tri5gh(sc->sc_dev);
-	plp->plp_bxarch = siba_sprom_get_bxa5g(sc->sc_dev);
-	plp->plp_rxpwroffset = siba_sprom_get_rxpo5g(sc->sc_dev);
-	plp->plp_rssivf = siba_sprom_get_rssismf5g(sc->sc_dev);
-	plp->plp_rssivc = siba_sprom_get_rssismc5g(sc->sc_dev);
-	plp->plp_rssigs = siba_sprom_get_rssisav5g(sc->sc_dev);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GL,
+	    &plp->plp_txisoband_l);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5G,
+	    &plp->plp_txisoband_m);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GH,
+	    &plp->plp_txisoband_h);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA5G,
+	    &plp->plp_bxarch);
+	BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO5G,
+	    &plp->plp_rxpwroffset);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF5G,
+	    &plp->plp_rssivf);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC5G,
+	    &plp->plp_rssivc);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV5G,
+	    &plp->plp_rssigs);
+
+#undef	BWN_PHY_LP_READVAR
+
+	return (0);
 }
 
 static void
@@ -686,7 +736,7 @@ bwn_phy_lp_calib(struct bwn_mac *mac)
 		bwn_phy_lp_digflt_restore(mac);
 
 	/* do RX IQ Calculation; assumes that noise is true. */
-	if (siba_get_chipid(sc->sc_dev) == 0x5354) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) {
 		for (i = 0; i < N(bwn_rxcompco_5354); i++) {
 			if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan)
 				rc = &bwn_rxcompco_5354[i];
@@ -766,10 +816,11 @@ bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
 {
 	static const struct bwn_b206x_chan *bc = NULL;
 	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t count, freqref, freqvco, freqxtal, val[3], timeout, timeoutref,
+	uint32_t count, freqref, freqvco, val[3], timeout, timeoutref,
 	    tmp[6];
 	uint16_t old, scale, tmp16;
-	int i, div;
+	u_int freqxtal;
+	int error, i, div;
 
 	for (i = 0; i < N(bwn_b2063_chantable); i++) {
 		if (bwn_b2063_chantable[i].bc_chan == chan) {
@@ -780,6 +831,13 @@ bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	if (bc == NULL)
 		return (EINVAL);
 
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
+
 	BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]);
 	BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]);
 	BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]);
@@ -796,7 +854,6 @@ bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	old = BWN_RF_READ(mac, BWN_B2063_COM15);
 	BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e);
 
-	freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
 	freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2);
 	freqref = freqxtal * 3;
 	div = (freqxtal <= 26000000 ? 1 : 2);
@@ -897,9 +954,9 @@ bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
 	const struct bwn_b206x_chan *bc = NULL;
-	uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
 	uint32_t tmp[9];
-	int i;
+	u_int freqxtal;
+	int error, i;
 
 	for (i = 0; i < N(bwn_b2062_chantable); i++) {
 		if (bwn_b2062_chantable[i].bc_chan == chan) {
@@ -911,6 +968,13 @@ bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	if (bc == NULL)
 		return (EINVAL);
 
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
+
 	BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL14, 0x04);
 	BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]);
 	BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]);
@@ -1301,7 +1365,7 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000);
 	BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000);
 	BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1);
-	if (siba_get_pci_revid(sc->sc_dev) >= 0x18) {
+	if (sc->sc_board_info.board_rev >= 0x18) {
 		bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec);
 		BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14);
 	} else {
@@ -1318,8 +1382,8 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0);
 	BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300);
 	BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00);
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
 		BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa);
 	} else {
@@ -1328,8 +1392,8 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	}
 	for (i = 0; i < N(v3); i++)
 		BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set);
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0);
 		bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40);
 	}
@@ -1354,8 +1418,8 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	    0x2000 | ((uint16_t)plp->plp_rssigs << 10) |
 	    ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf);
 
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c);
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800);
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400);
@@ -1427,7 +1491,7 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 		{ BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0006 },
 		{ BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0700 }
 	};
-	int i;
+	int error, i;
 	uint16_t tmp, tmp2;
 
 	BWN_PHY_MASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf7ff);
@@ -1449,23 +1513,38 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 		BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set);
 	BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB,
 	    0xff00, plp->plp_rxpwroffset);
-	if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) &&
+	if ((sc->sc_board_info.board_flags & BHND_BFL_FEM) &&
 	    ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ||
-	   (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF))) {
-		siba_cc_pmu_set_ldovolt(sc->sc_dev, SIBA_LDO_PAREF, 0x28);
-		siba_cc_pmu_set_ldoparef(sc->sc_dev, 1);
+	   (sc->sc_board_info.board_flags & BHND_BFL_PAREF))) {
+		error = bhnd_pmu_set_voltage_raw(sc->sc_pmu,
+		    BHND_REGULATOR_PAREF_LDO, 0x28);
+		if (error)
+			device_printf(sc->sc_dev, "failed to set PAREF LDO "
+			    "voltage: %d\n", error);
+
+		error = bhnd_pmu_enable_regulator(sc->sc_pmu,
+		    BHND_REGULATOR_PAREF_LDO);
+		if (error)
+			device_printf(sc->sc_dev, "failed to enable PAREF LDO "
+			    "regulator: %d\n", error);
+
 		if (mac->mac_phy.rev == 0)
 			BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT,
 			    0xffcf, 0x0010);
 		bwn_tab_write(mac, BWN_TAB_2(11, 7), 60);
 	} else {
-		siba_cc_pmu_set_ldoparef(sc->sc_dev, 0);
+		error = bhnd_pmu_disable_regulator(sc->sc_pmu,
+		    BHND_REGULATOR_PAREF_LDO);
+		if (error)
+			device_printf(sc->sc_dev, "failed to disable PAREF LDO "
+			    "regulator: %d\n", error);
+
 		BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020);
 		bwn_tab_write(mac, BWN_TAB_2(11, 7), 100);
 	}
 	tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000;
 	BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp);
-	if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_RSSIINV)
+	if (sc->sc_board_info.board_flags & BHND_BFL_RSSIINV)
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa);
 	else
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa);
@@ -1473,19 +1552,19 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 	BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL,
 	    0xfff9, (plp->plp_bxarch << 1));
 	if (mac->mac_phy.rev == 1 &&
-	    (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT)) {
+	    (sc->sc_board_info.board_flags & BHND_BFL_FEM_BT)) {
 		for (i = 0; i < N(v2); i++)
 			BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask,
 			    v2[i].set);
 	} else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ||
-	    (siba_get_pci_subdevice(sc->sc_dev) == 0x048a) ||
+	    (sc->sc_board_info.board_type == 0x048a) ||
 	    ((mac->mac_phy.rev == 0) &&
-	     (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM))) {
+	     (sc->sc_board_info.board_flags & BHND_BFL_FEM))) {
 		for (i = 0; i < N(v3); i++)
 			BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask,
 			    v3[i].set);
 	} else if (mac->mac_phy.rev == 1 ||
-		  (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM)) {
+		  (sc->sc_board_info.board_flags & BHND_BFL_FEM)) {
 		for (i = 0; i < N(v4); i++)
 			BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask,
 			    v4[i].set);
@@ -1495,15 +1574,15 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 			    v5[i].set);
 	}
 	if (mac->mac_phy.rev == 1 &&
-	    (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF)) {
+	    (sc->sc_board_info.board_flags & BHND_BFL_PAREF)) {
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1);
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2);
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3);
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4);
 	}
-	if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT) &&
-	    (siba_get_chipid(sc->sc_dev) == 0x5354) &&
-	    (siba_get_chippkg(sc->sc_dev) == SIBA_CHIPPACK_BCM4712S)) {
+	if ((sc->sc_board_info.board_flags & BHND_BFL_FEM_BT) &&
+	    (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) &&
+	    (sc->sc_cid.chip_pkg == BHND_PKGID_BCM4712SMALL)) {
 		BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006);
 		BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005);
 		BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff);
@@ -1543,7 +1622,7 @@ struct bwn_b2062_freq {
 	uint8_t			value[6];
 };
 
-static void
+static int
 bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 {
 #define	CALC_CTL7(freq, div)						\
@@ -1574,8 +1653,17 @@ bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 		{ BWN_B2062_N_CALIB_TS, 0 }
 	};
 	const struct bwn_b2062_freq *f = NULL;
-	uint32_t xtalfreq, ref;
+	uint32_t ref;
+	u_int xtalfreq;
 	unsigned int i;
+	int error;
+
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &xtalfreq);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
 
 	bwn_phy_lp_b2062_tblinit(mac);
 
@@ -1589,11 +1677,6 @@ bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 	else
 		BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1);
 
-	KASSERT(siba_get_cc_caps(sc->sc_dev) & SIBA_CC_CAPS_PMU,
-	    ("%s:%d: fail", __func__, __LINE__));
-	xtalfreq = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
-	KASSERT(xtalfreq != 0, ("%s:%d: fail", __func__, __LINE__));
-
 	if (xtalfreq <= 30000000) {
 		plp->plp_div = 1;
 		BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb);
@@ -1625,12 +1708,14 @@ bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 	    ((uint16_t)(f->value[3]) << 4) | f->value[2]);
 	BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]);
 	BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]);
+
+	return (0);
 #undef CALC_CTL7
 #undef CALC_CTL18
 #undef CALC_CTL19
 }
 
-static void
+static int
 bwn_phy_lp_b2063_init(struct bwn_mac *mac)
 {
 
@@ -1650,9 +1735,11 @@ bwn_phy_lp_b2063_init(struct bwn_mac *mac)
 		BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20);
 		BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20);
 	}
+
+	return (0);
 }
 
-static void
+static int
 bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
@@ -1673,10 +1760,17 @@ bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
 		{ BWN_B2063_RC_CALIB_CTL2, 0x55 },
 		{ BWN_B2063_RC_CALIB_CTL3, 0x76 }
 	};
-	uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
-	int i;
+	u_int freqxtal;
+	int error, i;
 	uint8_t tmp;
 
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
+
 	tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff;
 
 	for (i = 0; i < 2; i++)
@@ -1713,9 +1807,11 @@ bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
 	if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2))
 		BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp);
 	BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL1, 0x7e);
+
+	return (0);
 }
 
-static void
+static int
 bwn_phy_lp_rccal_r12(struct bwn_mac *mac)
 {
 	struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
@@ -1831,6 +1927,8 @@ done:
 	bwn_phy_lp_set_txpctlmode(mac, txpctlmode);
 	if (plp->plp_rccap)
 		bwn_phy_lp_set_rccap(mac);
+
+	return (0);
 }
 
 static void
@@ -1876,7 +1974,7 @@ bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac)
 
 	BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff);
 	DELAY(20);
-	if (siba_get_chipid(sc->sc_dev) == 0x5354) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) {
 		BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4);
 		BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4);
 	} else {
@@ -2735,8 +2833,8 @@ bwn_phy_lp_tblinit_r2(struct bwn_mac *mac)
 	bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps);
 	bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult);
 
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0),
 		    gainidx_a0);
 		bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0),
@@ -3353,7 +3451,7 @@ bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
 	};
 
 	if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) {
-		if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA)
+		if (sc->sc_board_info.board_flags & BHND_BFL_NOPA)
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2);
 		else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
@@ -3365,8 +3463,8 @@ bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
 	}
 
 	if (mac->mac_phy.rev == 0) {
-		if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) ||
-		    (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA))
+		if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) ||
+		    (sc->sc_board_info.board_flags & BHND_BFL_HGPA))
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0);
 		else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
@@ -3377,8 +3475,8 @@ bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
 		return;
 	}
 
-	if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) ||
-	    (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA))
+	if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) ||
+	    (sc->sc_board_info.board_flags & BHND_BFL_HGPA))
 		bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1);
 	else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
 		bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1);
diff --git a/sys/dev/bwn/if_bwn_phy_n.c b/sys/dev/bwn/if_bwn_phy_n.c
index 1a01c2c12d44..937bd9352da5 100644
--- a/sys/dev/bwn/if_bwn_phy_n.c
+++ b/sys/dev/bwn/if_bwn_phy_n.c
@@ -72,8 +72,6 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
-
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
@@ -121,8 +119,7 @@ bwn_phy_n_prepare_hw(struct bwn_mac *mac)
 {
 
 #ifdef	BWN_GPL_PHY
-	bwn_nphy_op_prepare_structs(mac);
-	return (0);
+	return (bwn_nphy_op_prepare_structs(mac));
 #else
 	return (ENXIO);
 #endif
diff --git a/sys/dev/bwn/if_bwn_siba.c b/sys/dev/bwn/if_bwn_siba.c
deleted file mode 100644
index f01381636a8a..000000000000
--- a/sys/dev/bwn/if_bwn_siba.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#define	BWN_USE_SIBA	1
-#include "if_bwn_siba.h"
-
-/** Legacy siba(4) bus operations */
-
-static int
-bwn_siba_bus_ops_init(device_t dev)
-{
-	return (0);
-}
-
-static void
-bwn_siba_bus_ops_fini(device_t dev)
-{
-}
-
-const struct bwn_bus_ops bwn_siba_bus_ops = {
-	.init				= bwn_siba_bus_ops_init,
-	.fini				= bwn_siba_bus_ops_fini,
-	.pci_find_cap			= pci_find_cap,
-	.pci_alloc_msi			= pci_alloc_msi,
-	.pci_release_msi		= pci_release_msi,
-	.pci_msi_count			= pci_msi_count,
-	.get_vendor			= siba_get_vendor,
-	.get_device			= siba_get_device,
-	.get_revid			= siba_get_revid,
-	.get_pci_vendor			= siba_get_pci_vendor,
-	.get_pci_device			= siba_get_pci_device,
-	.get_pci_subvendor		= siba_get_pci_subvendor,
-	.get_pci_subdevice		= siba_get_pci_subdevice,
-	.get_pci_revid			= siba_get_pci_revid,
-	.get_chipid			= siba_get_chipid,
-	.get_chiprev			= siba_get_chiprev,
-	.get_chippkg			= siba_get_chippkg,
-	.get_type			= siba_get_type,
-	.get_cc_pmufreq			= siba_get_cc_pmufreq,
-	.get_cc_caps			= siba_get_cc_caps,
-	.get_cc_powerdelay		= siba_get_cc_powerdelay,
-	.get_pcicore_revid		= siba_get_pcicore_revid,
-	.sprom_get_rev			= siba_sprom_get_rev,
-	.sprom_get_mac_80211bg		= siba_sprom_get_mac_80211bg,
-	.sprom_get_mac_80211a		= siba_sprom_get_mac_80211a,
-	.sprom_get_brev			= siba_sprom_get_brev,
-	.sprom_get_ccode		= siba_sprom_get_ccode,
-	.sprom_get_ant_a		= siba_sprom_get_ant_a,
-	.sprom_get_ant_bg		= siba_sprom_get_ant_bg,
-	.sprom_get_pa0b0		= siba_sprom_get_pa0b0,
-	.sprom_get_pa0b1		= siba_sprom_get_pa0b1,
-	.sprom_get_pa0b2		= siba_sprom_get_pa0b2,
-	.sprom_get_gpio0		= siba_sprom_get_gpio0,
-	.sprom_get_gpio1		= siba_sprom_get_gpio1,
-	.sprom_get_gpio2		= siba_sprom_get_gpio2,
-	.sprom_get_gpio3		= siba_sprom_get_gpio3,
-	.sprom_get_maxpwr_bg		= siba_sprom_get_maxpwr_bg,
-	.sprom_set_maxpwr_bg		= siba_sprom_set_maxpwr_bg,
-	.sprom_get_rxpo2g		= siba_sprom_get_rxpo2g,
-	.sprom_get_rxpo5g		= siba_sprom_get_rxpo5g,
-	.sprom_get_tssi_bg		= siba_sprom_get_tssi_bg,
-	.sprom_get_tri2g		= siba_sprom_get_tri2g,
-	.sprom_get_tri5gl		= siba_sprom_get_tri5gl,
-	.sprom_get_tri5g		= siba_sprom_get_tri5g,
-	.sprom_get_tri5gh		= siba_sprom_get_tri5gh,
-	.sprom_get_rssisav2g		= siba_sprom_get_rssisav2g,
-	.sprom_get_rssismc2g		= siba_sprom_get_rssismc2g,
-	.sprom_get_rssismf2g		= siba_sprom_get_rssismf2g,
-	.sprom_get_bxa2g		= siba_sprom_get_bxa2g,
-	.sprom_get_rssisav5g		= siba_sprom_get_rssisav5g,
-	.sprom_get_rssismc5g		= siba_sprom_get_rssismc5g,
-	.sprom_get_rssismf5g		= siba_sprom_get_rssismf5g,
-	.sprom_get_bxa5g		= siba_sprom_get_bxa5g,
-	.sprom_get_cck2gpo		= siba_sprom_get_cck2gpo,
-	.sprom_get_ofdm2gpo		= siba_sprom_get_ofdm2gpo,
-	.sprom_get_ofdm5glpo		= siba_sprom_get_ofdm5glpo,
-	.sprom_get_ofdm5gpo		= siba_sprom_get_ofdm5gpo,
-	.sprom_get_ofdm5ghpo		= siba_sprom_get_ofdm5ghpo,
-	.sprom_get_bf_lo		= siba_sprom_get_bf_lo,
-	.sprom_set_bf_lo		= siba_sprom_set_bf_lo,
-	.sprom_get_bf_hi		= siba_sprom_get_bf_hi,
-	.sprom_get_bf2_lo		= siba_sprom_get_bf2_lo,
-	.sprom_get_bf2_hi		= siba_sprom_get_bf2_hi,
-	.sprom_get_fem_2ghz_tssipos	= siba_sprom_get_fem_2ghz_tssipos,
-	.sprom_get_fem_2ghz_extpa_gain	= siba_sprom_get_fem_2ghz_extpa_gain,
-	.sprom_get_fem_2ghz_pdet_range	= siba_sprom_get_fem_2ghz_pdet_range,
-	.sprom_get_fem_2ghz_tr_iso	= siba_sprom_get_fem_2ghz_tr_iso,
-	.sprom_get_fem_2ghz_antswlut	= siba_sprom_get_fem_2ghz_antswlut,
-	.sprom_get_fem_5ghz_extpa_gain	= siba_sprom_get_fem_5ghz_extpa_gain,
-	.sprom_get_fem_5ghz_pdet_range	= siba_sprom_get_fem_5ghz_pdet_range,
-	.sprom_get_fem_5ghz_antswlut	= siba_sprom_get_fem_5ghz_antswlut,
-	.sprom_get_txpid_2g_0		= siba_sprom_get_txpid_2g_0,
-	.sprom_get_txpid_2g_1		= siba_sprom_get_txpid_2g_1,
-	.sprom_get_txpid_5gl_0		= siba_sprom_get_txpid_5gl_0,
-	.sprom_get_txpid_5gl_1		= siba_sprom_get_txpid_5gl_1,
-	.sprom_get_txpid_5g_0		= siba_sprom_get_txpid_5g_0,
-	.sprom_get_txpid_5g_1		= siba_sprom_get_txpid_5g_1,
-	.sprom_get_txpid_5gh_0		= siba_sprom_get_txpid_5gh_0,
-	.sprom_get_txpid_5gh_1		= siba_sprom_get_txpid_5gh_1,
-	.sprom_get_stbcpo		= siba_sprom_get_stbcpo,
-	.sprom_get_cddpo		= siba_sprom_get_cddpo,
-	.powerup			= siba_powerup,
-	.powerdown			= siba_powerdown,
-	.read_2				= siba_read_2,
-	.write_2			= siba_write_2,
-	.read_4				= siba_read_4,
-	.write_4			= siba_write_4,
-	.dev_up				= siba_dev_up,
-	.dev_down			= siba_dev_down,
-	.dev_isup			= siba_dev_isup,
-	.pcicore_intr			= siba_pcicore_intr,
-	.dma_translation		= siba_dma_translation,
-	.read_multi_2			= siba_read_multi_2,
-	.read_multi_4			= siba_read_multi_4,
-	.write_multi_2			= siba_write_multi_2,
-	.write_multi_4			= siba_write_multi_4,
-	.barrier			= siba_barrier,
-	.cc_pmu_set_ldovolt		= siba_cc_pmu_set_ldovolt,
-	.cc_pmu_set_ldoparef		= siba_cc_pmu_set_ldoparef,
-	.gpio_set			= siba_gpio_set,
-	.gpio_get			= siba_gpio_get,
-	.fix_imcfglobug			= siba_fix_imcfglobug,
-	.sprom_get_core_power_info	= siba_sprom_get_core_power_info,
-	.sprom_get_mcs2gpo		= siba_sprom_get_mcs2gpo,
-	.sprom_get_mcs5glpo		= siba_sprom_get_mcs5glpo,
-	.sprom_get_mcs5gpo		= siba_sprom_get_mcs5gpo,
-	.sprom_get_mcs5ghpo		= siba_sprom_get_mcs5ghpo,
-	.pmu_spuravoid_pllupdate	= siba_pmu_spuravoid_pllupdate,
-	.cc_set32			= siba_cc_set32,
-	.cc_mask32			= siba_cc_mask32,
-	.cc_write32			= siba_cc_write32,
-};
diff --git a/sys/dev/bwn/if_bwn_siba.h b/sys/dev/bwn/if_bwn_siba.h
deleted file mode 100644
index db97516c0d33..000000000000
--- a/sys/dev/bwn/if_bwn_siba.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon J. Fuller <landonf@FreeBSD.org>.
- * Copyright (c) 2007 Bruce M. Simpson.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _IF_BWN_SIBA_H_
-#define _IF_BWN_SIBA_H_
-
-/** If true, expose legacy siba_pci headers directly. Otherwise,
-  * we expose our siba/bhnd compatibility shims. */
-#ifndef	BWN_USE_SIBA
-#define	BWN_USE_SIBA	0
-#endif
-
-struct bwn_softc;
-struct siba_sprom_core_pwr_info;
-
-/*
- * Legacy siba(4) bus API compatibility shims.
- */
-struct bwn_bus_ops {
-	/* bus-specific initialization/finalization */
-	int		(*init)(device_t);
-	void		(*fini)(device_t);
-
-	/* compatibility shims */
-	int		(*pci_find_cap)(device_t, int, int *);
-	int		(*pci_alloc_msi)(device_t, int *);
-	int		(*pci_release_msi)(device_t);
-	int		(*pci_msi_count)(device_t);
-	uint16_t	(*get_vendor)(device_t);
-	uint16_t	(*get_device)(device_t);
-	uint8_t		(*get_revid)(device_t);
-	uint16_t	(*get_pci_vendor)(device_t);
-	uint16_t	(*get_pci_device)(device_t);
-	uint16_t	(*get_pci_subvendor)(device_t);
-	uint16_t	(*get_pci_subdevice)(device_t);
-	uint8_t		(*get_pci_revid)(device_t);
-	uint16_t	(*get_chipid)(device_t);
-	uint16_t	(*get_chiprev)(device_t);
-	uint8_t		(*get_chippkg)(device_t);
-	enum siba_type	(*get_type)(device_t);
-	uint32_t	(*get_cc_pmufreq)(device_t);
-	uint32_t	(*get_cc_caps)(device_t);
-	uint16_t	(*get_cc_powerdelay)(device_t);
-	uint8_t		(*get_pcicore_revid)(device_t);
-	uint8_t		(*sprom_get_rev)(device_t);
-	uint8_t		*(*sprom_get_mac_80211bg)(device_t);
-	uint8_t		*(*sprom_get_mac_80211a)(device_t);
-	uint8_t		(*sprom_get_brev)(device_t);
-	uint8_t		(*sprom_get_ccode)(device_t);
-	uint8_t		(*sprom_get_ant_a)(device_t);
-	uint8_t		(*sprom_get_ant_bg)(device_t);
-	uint16_t	(*sprom_get_pa0b0)(device_t);
-	uint16_t	(*sprom_get_pa0b1)(device_t);
-	uint16_t	(*sprom_get_pa0b2)(device_t);
-	uint8_t		(*sprom_get_gpio0)(device_t);
-	uint8_t		(*sprom_get_gpio1)(device_t);
-	uint8_t		(*sprom_get_gpio2)(device_t);
-	uint8_t		(*sprom_get_gpio3)(device_t);
-	uint16_t	(*sprom_get_maxpwr_bg)(device_t);
-	void		(*sprom_set_maxpwr_bg)(device_t, uint16_t);
-	uint8_t		(*sprom_get_rxpo2g)(device_t);
-	uint8_t		(*sprom_get_rxpo5g)(device_t);
-	uint8_t		(*sprom_get_tssi_bg)(device_t);
-	uint8_t		(*sprom_get_tri2g)(device_t);
-	uint8_t		(*sprom_get_tri5gl)(device_t);
-	uint8_t		(*sprom_get_tri5g)(device_t);
-	uint8_t		(*sprom_get_tri5gh)(device_t);
-	uint8_t		(*sprom_get_rssisav2g)(device_t);
-	uint8_t		(*sprom_get_rssismc2g)(device_t);
-	uint8_t		(*sprom_get_rssismf2g)(device_t);
-	uint8_t		(*sprom_get_bxa2g)(device_t);
-	uint8_t		(*sprom_get_rssisav5g)(device_t);
-	uint8_t		(*sprom_get_rssismc5g)(device_t);
-	uint8_t		(*sprom_get_rssismf5g)(device_t);
-	uint8_t		(*sprom_get_bxa5g)(device_t);
-	uint16_t	(*sprom_get_cck2gpo)(device_t);
-	uint32_t	(*sprom_get_ofdm2gpo)(device_t);
-	uint32_t	(*sprom_get_ofdm5glpo)(device_t);
-	uint32_t	(*sprom_get_ofdm5gpo)(device_t);
-	uint32_t	(*sprom_get_ofdm5ghpo)(device_t);
-	uint16_t	(*sprom_get_bf_lo)(device_t);
-	void		(*sprom_set_bf_lo)(device_t, uint16_t);
-	uint16_t	(*sprom_get_bf_hi)(device_t);
-	uint16_t	(*sprom_get_bf2_lo)(device_t);
-	uint16_t	(*sprom_get_bf2_hi)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_tssipos)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_extpa_gain)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_pdet_range)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_tr_iso)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_antswlut)(device_t);
-	uint8_t		(*sprom_get_fem_5ghz_extpa_gain)(device_t);
-	uint8_t		(*sprom_get_fem_5ghz_pdet_range)(device_t);
-	uint8_t		(*sprom_get_fem_5ghz_antswlut)(device_t);
-	uint8_t		(*sprom_get_txpid_2g_0)(device_t);
-	uint8_t		(*sprom_get_txpid_2g_1)(device_t);
-	uint8_t		(*sprom_get_txpid_5gl_0)(device_t);
-	uint8_t		(*sprom_get_txpid_5gl_1)(device_t);
-	uint8_t		(*sprom_get_txpid_5g_0)(device_t);
-	uint8_t		(*sprom_get_txpid_5g_1)(device_t);
-	uint8_t		(*sprom_get_txpid_5gh_0)(device_t);
-	uint8_t		(*sprom_get_txpid_5gh_1)(device_t);
-	uint16_t	(*sprom_get_stbcpo)(device_t);
-	uint16_t	(*sprom_get_cddpo)(device_t);
-	void		(*powerup)(device_t, int);
-	int		(*powerdown)(device_t);
-	uint16_t	(*read_2)(device_t, uint16_t);
-	void		(*write_2)(device_t, uint16_t, uint16_t);
-	uint32_t	(*read_4)(device_t, uint16_t);
-	void		(*write_4)(device_t, uint16_t, uint32_t);
-	void		(*dev_up)(device_t, uint32_t);
-	void		(*dev_down)(device_t, uint32_t);
-	int		(*dev_isup)(device_t);
-	void		(*pcicore_intr)(device_t);
-	uint32_t	(*dma_translation)(device_t);
-	void		(*read_multi_2)(device_t, void *, size_t, uint16_t);
-	void		(*read_multi_4)(device_t, void *, size_t, uint16_t);
-	void		(*write_multi_2)(device_t, const void *, size_t, uint16_t);
-	void		(*write_multi_4)(device_t, const void *, size_t, uint16_t);
-	void		(*barrier)(device_t, int);
-	void		(*cc_pmu_set_ldovolt)(device_t, int, uint32_t);
-	void		(*cc_pmu_set_ldoparef)(device_t, uint8_t);
-	void		(*gpio_set)(device_t, uint32_t);
-	uint32_t	(*gpio_get)(device_t);
-	void		(*fix_imcfglobug)(device_t);
-	int		(*sprom_get_core_power_info)(device_t, int, struct siba_sprom_core_pwr_info *);
-	int		(*sprom_get_mcs2gpo)(device_t, uint16_t *);
-	int		(*sprom_get_mcs5glpo)(device_t, uint16_t *);
-	int		(*sprom_get_mcs5gpo)(device_t, uint16_t *);
-	int		(*sprom_get_mcs5ghpo)(device_t, uint16_t *);
-	void		(*pmu_spuravoid_pllupdate)(device_t, int);
-	void		(*cc_set32)(device_t, uint32_t, uint32_t);
-	void		(*cc_mask32)(device_t, uint32_t, uint32_t);
-	void		(*cc_write32)(device_t, uint32_t, uint32_t);
-};
-
-#if BWN_USE_SIBA
-
-#include <dev/siba/siba_ids.h>
-#include <dev/siba/sibareg.h>
-#include <dev/siba/sibavar.h>
-
-#define	BWN_BUS_OPS_ATTACH(_dev)	(0)
-#define	BWN_BUS_OPS_DETACH(_dev)
-
-#else /* !BWN_USE_SIBA */
-
-struct bwn_bus_ops;
-
-extern const struct bwn_bus_ops bwn_siba_bus_ops;
-extern const struct bwn_bus_ops bwn_bhnd_bus_ops;
-
-/*
- * Declared in:
- *    /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/siba_ids.h
- */
-
-struct siba_devid {
-    uint16_t sd_vendor;
-    uint16_t sd_device;
-    uint8_t sd_rev;
-    char *sd_desc;
-};
-
-#define	SIBA_DEV(_vendor, _cid, _rev, _msg)	\
-	{ SIBA_VID_##_vendor, SIBA_DEVID_##_cid, _rev, _msg }
-
-#define	SIBA_DEVID_80211		0x812
-#define	SIBA_VID_BROADCOM		0x4243
-
-/*
- * Declared in:
- *    /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/sibareg.h
- */
-
-#define	SIBA_CC_CAPS_PMU		0x10000000
-#define	SIBA_CC_CHIPCTL			0x0028
-#define	SIBA_CC_CHIPCTL_ADDR		0x0650
-#define	SIBA_CC_CHIPCTL_DATA		0x0654
-
-#define	SIBA_DMA_TRANSLATION_MASK	0xc0000000
-
-#define	SIBA_TGSLOW			0x0f98
-#define	SIBA_TGSLOW_FGC			0x00020000
-
-#define	SIBA_TGSHIGH			0x0f9c
-#define	SIBA_TGSHIGH_DMA64		0x10000000
-
-#define	SIBA_BOARDVENDOR_DELL		0x1028
-#define	SIBA_BOARDVENDOR_BCM		0x14e4
-
-#define	SIBA_BOARD_BCM4309G		0x0421
-#define	SIBA_BOARD_BU4306		0x0416
-#define	SIBA_BOARD_BCM4321		0x046d
-
-#define	SIBA_CHIPPACK_BCM4712S		1
-
-
-/*
- * Declared in:
- *    /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/sibavar.h
- */
-
-enum siba_type {
-	SIBA_TYPE_SSB			/* unused */,
-	SIBA_TYPE_PCI,
-	SIBA_TYPE_PCMCIA
-};
-
-/* TODO: need a real country code table */
-enum {
-	SIBA_CCODE_JAPAN,
-	SIBA_CCODE_UNKNOWN
-};
-
-struct siba_sprom_core_pwr_info {
-    uint8_t itssi_2g;
-    uint8_t itssi_5g;
-    uint8_t maxpwr_2g;
-    uint8_t maxpwr_5gl;
-    uint8_t maxpwr_5g;
-    uint8_t maxpwr_5gh;
-    int16_t pa_2g[3];
-    int16_t pa_5gl[4];
-    int16_t pa_5g[4];
-    int16_t pa_5gh[4];
-};
-
-#define	SIBA_LDO_PAREF	0
-
-#define	BWN_BUS_OPS_SC(_sc)	\
-	((_sc)->sc_bus_ops)
-
-#define	BWN_BUS_OPS(_dev)	\
-	BWN_BUS_OPS_SC((struct bwn_softc *)device_get_softc(_dev))
-
-#define	BWN_BUS_OPS_ATTACH(_dev)	\
-	BWN_BUS_OPS(_dev)->init(_dev)
-#define	BWN_BUS_OPS_DETACH(_dev)	\
-	BWN_BUS_OPS(_dev)->fini(_dev)
-
-#define	pci_find_cap(_dev, capability, capreg)	\
-	BWN_BUS_OPS(_dev)->pci_find_cap(_dev, capability, capreg)
-#define	pci_alloc_msi(_dev, count)	\
-	BWN_BUS_OPS(_dev)->pci_alloc_msi(_dev, count)
-#define	pci_release_msi(_dev)	\
-	BWN_BUS_OPS(_dev)->pci_release_msi(_dev)
-#define	pci_msi_count(_dev)	\
-	BWN_BUS_OPS(_dev)->pci_msi_count(_dev)
-
-#define	siba_get_vendor(_dev)	\
-	BWN_BUS_OPS(_dev)->get_vendor(_dev)
-#define	siba_get_device(_dev)	\
-	BWN_BUS_OPS(_dev)->get_device(_dev)
-#define	siba_get_revid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_revid(_dev)
-#define	siba_get_pci_vendor(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_vendor(_dev)
-#define	siba_get_pci_device(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_device(_dev)
-#define	siba_get_pci_subvendor(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_subvendor(_dev)
-#define	siba_get_pci_subdevice(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_subdevice(_dev)
-#define	siba_get_pci_revid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_revid(_dev)
-#define	siba_get_chipid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_chipid(_dev)
-#define	siba_get_chiprev(_dev)	\
-	BWN_BUS_OPS(_dev)->get_chiprev(_dev)
-#define	siba_get_chippkg(_dev)	\
-	BWN_BUS_OPS(_dev)->get_chippkg(_dev)
-#define	siba_get_type(_dev)	\
-	BWN_BUS_OPS(_dev)->get_type(_dev)
-#define	siba_get_cc_pmufreq(_dev)	\
-	BWN_BUS_OPS(_dev)->get_cc_pmufreq(_dev)
-#define	siba_get_cc_caps(_dev)	\
-	BWN_BUS_OPS(_dev)->get_cc_caps(_dev)
-#define	siba_get_cc_powerdelay(_dev)	\
-	BWN_BUS_OPS(_dev)->get_cc_powerdelay(_dev)
-#define	siba_get_pcicore_revid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pcicore_revid(_dev)
-#define	siba_sprom_get_rev(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rev(_dev)
-#define	siba_sprom_get_mac_80211bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mac_80211bg(_dev)
-#define	siba_sprom_get_mac_80211a(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mac_80211a(_dev)
-#define	siba_sprom_get_brev(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_brev(_dev)
-#define	siba_sprom_get_ccode(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ccode(_dev)
-#define	siba_sprom_get_ant_a(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ant_a(_dev)
-#define	siba_sprom_get_ant_bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ant_bg(_dev)
-#define	siba_sprom_get_pa0b0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_pa0b0(_dev)
-#define	siba_sprom_get_pa0b1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_pa0b1(_dev)
-#define	siba_sprom_get_pa0b2(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_pa0b2(_dev)
-#define	siba_sprom_get_gpio0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio0(_dev)
-#define	siba_sprom_get_gpio1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio1(_dev)
-#define	siba_sprom_get_gpio2(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio2(_dev)
-#define	siba_sprom_get_gpio3(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio3(_dev)
-#define	siba_sprom_get_maxpwr_bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_maxpwr_bg(_dev)
-#define	siba_sprom_set_maxpwr_bg(_dev, t)	\
-	BWN_BUS_OPS(_dev)->sprom_set_maxpwr_bg(_dev, t)
-#define	siba_sprom_get_rxpo2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rxpo2g(_dev)
-#define	siba_sprom_get_rxpo5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rxpo5g(_dev)
-#define	siba_sprom_get_tssi_bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tssi_bg(_dev)
-#define	siba_sprom_get_tri2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri2g(_dev)
-#define	siba_sprom_get_tri5gl(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri5gl(_dev)
-#define	siba_sprom_get_tri5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri5g(_dev)
-#define	siba_sprom_get_tri5gh(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri5gh(_dev)
-#define	siba_sprom_get_rssisav2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssisav2g(_dev)
-#define	siba_sprom_get_rssismc2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismc2g(_dev)
-#define	siba_sprom_get_rssismf2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismf2g(_dev)
-#define	siba_sprom_get_bxa2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bxa2g(_dev)
-#define	siba_sprom_get_rssisav5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssisav5g(_dev)
-#define	siba_sprom_get_rssismc5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismc5g(_dev)
-#define	siba_sprom_get_rssismf5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismf5g(_dev)
-#define	siba_sprom_get_bxa5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bxa5g(_dev)
-#define	siba_sprom_get_cck2gpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_cck2gpo(_dev)
-#define	siba_sprom_get_ofdm2gpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm2gpo(_dev)
-#define	siba_sprom_get_ofdm5glpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm5glpo(_dev)
-#define	siba_sprom_get_ofdm5gpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm5gpo(_dev)
-#define	siba_sprom_get_ofdm5ghpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm5ghpo(_dev)
-#define	siba_sprom_get_bf_lo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf_lo(_dev)
-#define	siba_sprom_set_bf_lo(_dev, t)	\
-	BWN_BUS_OPS(_dev)->sprom_set_bf_lo(_dev, t)
-#define	siba_sprom_get_bf_hi(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf_hi(_dev)
-#define	siba_sprom_get_bf2_lo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf2_lo(_dev)
-#define	siba_sprom_get_bf2_hi(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf2_hi(_dev)
-#define	siba_sprom_get_fem_2ghz_tssipos(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_tssipos(_dev)
-#define	siba_sprom_get_fem_2ghz_extpa_gain(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_extpa_gain(_dev)
-#define	siba_sprom_get_fem_2ghz_pdet_range(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_pdet_range(_dev)
-#define	siba_sprom_get_fem_2ghz_tr_iso(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_tr_iso(_dev)
-#define	siba_sprom_get_fem_2ghz_antswlut(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_antswlut(_dev)
-#define	siba_sprom_get_fem_5ghz_extpa_gain(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_extpa_gain(_dev)
-#define	siba_sprom_get_fem_5ghz_pdet_range(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_pdet_range(_dev)
-#define	siba_sprom_get_fem_5ghz_antswlut(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_antswlut(_dev)
-#define	siba_sprom_get_txpid_2g_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_2g_0(_dev)
-#define	siba_sprom_get_txpid_2g_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_2g_1(_dev)
-#define	siba_sprom_get_txpid_5gl_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gl_0(_dev)
-#define	siba_sprom_get_txpid_5gl_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gl_1(_dev)
-#define	siba_sprom_get_txpid_5g_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5g_0(_dev)
-#define	siba_sprom_get_txpid_5g_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5g_1(_dev)
-#define	siba_sprom_get_txpid_5gh_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gh_0(_dev)
-#define	siba_sprom_get_txpid_5gh_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gh_1(_dev)
-#define	siba_sprom_get_stbcpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_stbcpo(_dev)
-#define	siba_sprom_get_cddpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_cddpo(_dev)
-#define	siba_powerup(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->powerup(_dev, _arg1)
-#define	siba_powerdown(_dev)	\
-	BWN_BUS_OPS(_dev)->powerdown(_dev)
-#define	siba_read_2(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->read_2(_dev, _arg1)
-#define	siba_write_2(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->write_2(_dev, _arg1, _arg2)
-#define	siba_read_4(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->read_4(_dev, _arg1)
-#define	siba_write_4(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->write_4(_dev, _arg1, _arg2)
-#define	siba_dev_up(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->dev_up(_dev, _arg1)
-#define	siba_dev_down(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->dev_down(_dev, _arg1)
-#define	siba_dev_isup(_dev)	\
-	BWN_BUS_OPS(_dev)->dev_isup(_dev)
-#define	siba_pcicore_intr(_dev)	\
-	BWN_BUS_OPS(_dev)->pcicore_intr(_dev)
-#define	siba_dma_translation(_dev)	\
-	BWN_BUS_OPS(_dev)->dma_translation(_dev)
-#define	siba_read_multi_2(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->read_multi_2(_dev, _arg1, _arg2, _arg3)
-#define	siba_read_multi_4(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->read_multi_4(_dev, _arg1, _arg2, _arg3)
-#define	siba_write_multi_2(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->write_multi_2(_dev, _arg1, _arg2, _arg3)
-#define	siba_write_multi_4(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->write_multi_4(_dev, _arg1, _arg2, _arg3)
-#define	siba_barrier(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->barrier(_dev, _arg1)
-#define	siba_cc_pmu_set_ldovolt(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_pmu_set_ldovolt(_dev, _arg1, _arg2)
-#define	siba_cc_pmu_set_ldoparef(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->cc_pmu_set_ldoparef(_dev, _arg1)
-#define	siba_gpio_set(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->gpio_set(_dev, _arg1)
-#define	siba_gpio_get(_dev)	\
-	BWN_BUS_OPS(_dev)->gpio_get(_dev)
-#define	siba_fix_imcfglobug(_dev)	\
-	BWN_BUS_OPS(_dev)->fix_imcfglobug(_dev)
-#define	siba_sprom_get_core_power_info(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->sprom_get_core_power_info(_dev, _arg1, _arg2)
-#define	siba_sprom_get_mcs2gpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs2gpo(_dev, _arg1)
-#define	siba_sprom_get_mcs5glpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs5glpo(_dev, _arg1)
-#define	siba_sprom_get_mcs5gpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs5gpo(_dev, _arg1)
-#define	siba_sprom_get_mcs5ghpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs5ghpo(_dev, _arg1)
-#define	siba_pmu_spuravoid_pllupdate(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->pmu_spuravoid_pllupdate(_dev, _arg1)
-#define	siba_cc_set32(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_set32(_dev, _arg1, _arg2)
-#define	siba_cc_mask32(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_mask32(_dev, _arg1, _arg2)
-#define	siba_cc_write32(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_write32(_dev, _arg1, _arg2)
-
-#endif /* BWN_USE_SIBA */
-
-#endif /* _IF_BWN_SIBA_H_ */
diff --git a/sys/dev/bwn/if_bwn_siba_compat.c b/sys/dev/bwn/if_bwn_siba_compat.c
deleted file mode 100644
index bd59c0097256..000000000000
--- a/sys/dev/bwn/if_bwn_siba_compat.c
+++ /dev/null
@@ -1,2577 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
- * Copyright (c) 2017 The FreeBSD Foundation
- * All rights reserved.
- * 
- * Portions of this software were developed by Landon Fuller
- * under sponsorship from the FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/gpio.h>
-#include <sys/kernel.h>
-#include <sys/systm.h>
-#include <sys/socket.h>
-#include <sys/sockio.h>
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <net/ethernet.h>
-#include <net/if.h>
-#include <net/if_var.h>
-#include <net/if_arp.h>
-#include <net/if_dl.h>
-#include <net/if_llc.h>
-#include <net/if_media.h>
-#include <net/if_types.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include <net80211/ieee80211_var.h>
-#include <net80211/ieee80211_radiotap.h>
-#include <net80211/ieee80211_regdomain.h>
-#include <net80211/ieee80211_phy.h>
-#include <net80211/ieee80211_ratectl.h>
-
-#include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/siba/sibareg.h>
-
-#include <dev/bhnd/cores/chipc/chipc.h>
-#include <dev/bhnd/cores/pci/bhnd_pcireg.h>
-#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
-
-#include "gpio_if.h"
-
-#include "bhnd_nvram_map.h"
-
-#include "if_bwn_siba_compat.h"
-
-static int		bwn_bhnd_populate_nvram_data(device_t dev,
-			    struct bwn_bhnd_ctx *ctx);
-static inline bool	bwn_bhnd_is_siba_reg(device_t dev, uint16_t offset);
-
-#define	BWN_ASSERT_VALID_REG(_dev, _offset)				\
-	KASSERT(!bwn_bhnd_is_siba_reg(_dev, _offset),			\
-	    ("%s: accessing siba-specific register %#jx", __FUNCTION__,	\
-		(uintmax_t)(_offset)));
-
-static int
-bwn_bhnd_bus_ops_init(device_t dev)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	struct bwn_softc	*sc;
-	const struct chipc_caps	*ccaps;
-	int			 error;
-
-	sc = device_get_softc(dev);
-	ctx = NULL;
-
-	sc->sc_mem_rid = 0;
-	sc->sc_mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY,
-	    &sc->sc_mem_rid, RF_ACTIVE);
-	if (sc->sc_mem_res == NULL) {
-		return (ENXIO);
-	}
-
-	/* Allocate PMU state */
-	if ((error = bhnd_alloc_pmu(dev))) {
-		device_printf(dev, "PMU allocation failed: %d\n", error);
-		goto failed;
-	}
-
-	/* Allocate our context */
-	ctx = malloc(sizeof(struct bwn_bhnd_ctx), M_DEVBUF, M_WAITOK|M_ZERO);
-
-	/* Locate the ChipCommon device */
-	ctx->chipc_dev = bhnd_retain_provider(dev, BHND_SERVICE_CHIPC);
-	if (ctx->chipc_dev == NULL) {
-		device_printf(dev, "ChipCommon not found\n");
-		error = ENXIO;
-		goto failed;
-	}
-
-	/* Locate the GPIO device */
-	ctx->gpio_dev = bhnd_retain_provider(dev, BHND_SERVICE_GPIO);
-	if (ctx->gpio_dev == NULL) {
-		device_printf(dev, "GPIO not found\n");
-		error = ENXIO;
-		goto failed;
-	}
-
-	/* Locate the PMU device (if any) */
-	ccaps = BHND_CHIPC_GET_CAPS(ctx->chipc_dev);
-	if (ccaps->pmu) {
-		ctx->pmu_dev = bhnd_retain_provider(dev, BHND_SERVICE_PMU);
-		if (ctx->pmu_dev == NULL) {
-			device_printf(dev, "PMU not found\n");
-			error = ENXIO;
-			goto failed;
-		}
-	}
-
-	/* Populate NVRAM data */
-	if ((error = bwn_bhnd_populate_nvram_data(dev, ctx)))
-		goto failed;
-
-	/* Initialize bwn_softc */
-	sc->sc_bus_ctx = ctx;
-	return (0);
-
-failed:
-	bhnd_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
-	    sc->sc_mem_res);
-
-	if (ctx != NULL) {
-		if (ctx->chipc_dev != NULL) {
-			bhnd_release_provider(dev, ctx->chipc_dev,
-			    BHND_SERVICE_CHIPC);
-		}
-
-		if (ctx->gpio_dev != NULL) {
-			bhnd_release_provider(dev, ctx->gpio_dev,
-			    BHND_SERVICE_GPIO);
-		}
-
-		if (ctx->pmu_dev != NULL) {
-			bhnd_release_provider(dev, ctx->pmu_dev,
-			    BHND_SERVICE_PMU);
-		}
-
-		free(ctx, M_DEVBUF);
-	}
-
-	return (error);
-}
-
-static void
-bwn_bhnd_bus_ops_fini(device_t dev)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	struct bwn_softc	*sc;
-
-	sc = device_get_softc(dev);
-	ctx = sc->sc_bus_ctx;
-
-	bhnd_release_pmu(dev);
-	bhnd_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
-	    sc->sc_mem_res);
-
-	bhnd_release_provider(dev, ctx->chipc_dev, BHND_SERVICE_CHIPC);
-	bhnd_release_provider(dev, ctx->gpio_dev, BHND_SERVICE_GPIO);
-
-	if (ctx->pmu_dev != NULL)
-		bhnd_release_provider(dev, ctx->pmu_dev, BHND_SERVICE_PMU);
-
-	free(ctx, M_DEVBUF);
-	sc->sc_bus_ctx = NULL;
-}
-
-
-/**
- * Return true if @p offset is within a siba-specific configuration register
- * block.
- */
-static inline bool
-bwn_bhnd_is_siba_reg(device_t dev, uint16_t offset)
-{
-	if (offset >= SIBA_CFG0_OFFSET &&
-	    offset <= SIBA_CFG0_OFFSET + SIBA_CFG_SIZE)
-		return (true);
-
-	if (offset >= SIBA_CFG1_OFFSET &&
-	    offset <= SIBA_CFG1_OFFSET + SIBA_CFG_SIZE)
-		return (true);
-	
-	return (false);
-}
-
-/* Populate SPROM values from NVRAM */
-static int
-bwn_bhnd_populate_nvram_data(device_t dev, struct bwn_bhnd_ctx *ctx)
-{
-	const char	*mac_80211bg_var, *mac_80211a_var;
-	int	error;
-
-	/* Fetch SROM revision */
-	error = bhnd_nvram_getvar_uint8(dev, BHND_NVAR_SROMREV, &ctx->sromrev);
-	if (error) {
-		device_printf(dev, "error reading %s: %d\n", BHND_NVAR_SROMREV,
-		    error);
-		return (error);
-	}
-
-	/* Fetch board flags */
-	error = bhnd_nvram_getvar_uint32(dev, BHND_NVAR_BOARDFLAGS,
-	    &ctx->boardflags);
-	if (error) {
-		device_printf(dev, "error reading %s: %d\n",
-		    BHND_NVAR_BOARDFLAGS, error);
-		return (error);
-	}
-
-	/* Fetch macaddrs if available; bwn(4) expects any missing macaddr
-	 * values to be initialized with 0xFF octets */
-	memset(ctx->mac_80211bg, 0xFF, sizeof(ctx->mac_80211bg));
-	memset(ctx->mac_80211a, 0xFF, sizeof(ctx->mac_80211a));
-
-	if (ctx->sromrev <= 2) {
-		mac_80211bg_var = BHND_NVAR_IL0MACADDR;
-		mac_80211a_var = BHND_NVAR_ET1MACADDR;
-	} else {
-		mac_80211bg_var = BHND_NVAR_MACADDR;
-		mac_80211a_var = NULL;
-	}
-
-	/* Fetch required D11 core 0 macaddr */
-	error = bhnd_nvram_getvar_array(dev, mac_80211bg_var, ctx->mac_80211bg,
-	    sizeof(ctx->mac_80211bg), BHND_NVRAM_TYPE_UINT8_ARRAY);
-	if (error) {
-		device_printf(dev, "error reading %s: %d\n", mac_80211bg_var,
-		    error);
-		return (error);
-	}
-
-	/* Fetch optional D11 core 1 macaddr */
-	if (mac_80211a_var != NULL) {
-		error = bhnd_nvram_getvar_array(dev, mac_80211a_var,
-		    ctx->mac_80211a, sizeof(ctx->mac_80211a),
-		    BHND_NVRAM_TYPE_UINT8_ARRAY);
-
-		if (error && error != ENOENT) {
-			device_printf(dev, "error reading %s: %d\n",
-			    mac_80211a_var, error);
-			return (error);
-		}
-	};
-
-	/* Fetch pa0maxpwr; bwn(4) expects to be able to modify it */
-	if ((ctx->sromrev >= 1 && ctx->sromrev <= 3) ||
-	    (ctx->sromrev >= 8 && ctx->sromrev <= 10))
-	{
-		error = bhnd_nvram_getvar_uint8(dev, BHND_NVAR_PA0MAXPWR,
-		     &ctx->pa0maxpwr);
-		if (error) {
-			device_printf(dev, "error reading %s: %d\n",
-			    BHND_NVAR_PA0MAXPWR, error);
-			return (error);
-		}
-	}
-
-	return (0);
-}
-
-/*
- * Disable PCI-specific MSI interrupt allocation handling
- */
-
-/*
- * pci_find_cap()
- *
- * Referenced by:
- *   bwn_attach()
- */
-static int
-bhnd_compat_pci_find_cap(device_t dev, int capability, int *capreg)
-{
-	return (ENODEV);
-}
-
-/*
- * pci_alloc_msi()
- *
- * Referenced by:
- *   bwn_attach()
- */
-static int
-bhnd_compat_pci_alloc_msi(device_t dev, int *count)
-{
-	return (ENODEV);
-}
-
-/*
- * pci_release_msi()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_detach()
- */
-static int
-bhnd_compat_pci_release_msi(device_t dev)
-{
-	return (ENODEV);
-}
-
-/*
- * pci_msi_count()
- *
- * Referenced by:
- *   bwn_attach()
- */
-static int
-bhnd_compat_pci_msi_count(device_t dev)
-{
-	return (0);
-}
-
-/*
- * siba_get_vendor()
- *
- * Referenced by:
- *   bwn_probe()
- */
-static uint16_t
-bhnd_compat_get_vendor(device_t dev)
-{
-	uint16_t vendor = bhnd_get_vendor(dev);
-
-	switch (vendor) {
-	case BHND_MFGID_BCM:
-		return (SIBA_VID_BROADCOM);
-	default:
-		return (0x0000);
-	}
-}
-
-/*
- * siba_get_device()
- *
- * Referenced by:
- *   bwn_probe()
- */
-static uint16_t
-bhnd_compat_get_device(device_t dev)
-{
-	return (bhnd_get_device(dev));
-}
-
-/*
- * siba_get_revid()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_attach_core()
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_core_init()
- *   bwn_core_start()
- *   bwn_pio_idx2base()
- *   bwn_pio_set_txqueue()
- *   bwn_pio_tx_start()
- *   bwn_probe()
- * ... and 19 others
- * 
- */
-static uint8_t
-bhnd_compat_get_revid(device_t dev)
-{
-	return (bhnd_get_hwrev(dev));
-}
-
-/**
- * Return the PCI bridge root device.
- * 
- * Will panic if a PCI bridge root device is not found.
- */
-static device_t
-bwn_bhnd_get_pci_dev(device_t dev)
-{	device_t bridge_root;
-
-	bridge_root = bhnd_find_bridge_root(dev, devclass_find("pci"));
-	if (bridge_root == NULL)
-		panic("not a PCI device");
-
-	return (bridge_root);
-}
-
-/*
- * siba_get_pci_vendor()
- *
- * Referenced by:
- *   bwn_sprom_bugfixes()
- */
-static uint16_t
-bhnd_compat_get_pci_vendor(device_t dev)
-{
-	return (pci_get_vendor(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_device()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_attach_core()
- *   bwn_nphy_op_prepare_structs()
- *   bwn_sprom_bugfixes()
- */
-static uint16_t
-bhnd_compat_get_pci_device(device_t dev)
-{
-	return (pci_get_device(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_subvendor()
- *
- * Referenced by:
- *   bwn_led_attach()
- *   bwn_nphy_op_prepare_structs()
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_hwpctl_init()
- *   bwn_phy_init_b5()
- *   bwn_phy_initn()
- *   bwn_phy_txpower_check()
- *   bwn_radio_init2055_post()
- *   bwn_sprom_bugfixes()
- *   bwn_wa_init()
- */
-static uint16_t
-bhnd_compat_get_pci_subvendor(device_t dev)
-{
-	return (pci_get_subvendor(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_subdevice()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev1_2()
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_hwpctl_init()
- *   bwn_phy_init_b5()
- *   bwn_phy_initn()
- *   bwn_phy_lp_bbinit_r01()
- *   bwn_phy_txpower_check()
- *   bwn_radio_init2055_post()
- *   bwn_sprom_bugfixes()
- *   bwn_wa_init()
- */
-static uint16_t
-bhnd_compat_get_pci_subdevice(device_t dev)
-{
-	return (pci_get_subdevice(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_revid()
- *
- * Referenced by:
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_lp_bbinit_r2()
- *   bwn_sprom_bugfixes()
- *   bwn_wa_init()
- */
-static uint8_t
-bhnd_compat_get_pci_revid(device_t dev)
-{
-	return (pci_get_revid(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_chipid()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_gpio_init()
- *   bwn_mac_switch_freq()
- *   bwn_phy_g_attach()
- *   bwn_phy_g_init_sub()
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_getinfo()
- *   bwn_phy_lp_calib()
- *   bwn_set_opmode()
- *   bwn_sprom_bugfixes()
- * ... and 9 others
- * 
- */
-static uint16_t
-bhnd_compat_get_chipid(device_t dev)
-{
-	return (bhnd_get_chipid(dev)->chip_id);
-}
-
-/*
- * siba_get_chiprev()
- *
- * Referenced by:
- *   bwn_phy_getinfo()
- *   bwn_phy_lp_bbinit_r2()
- *   bwn_phy_lp_tblinit_r2()
- *   bwn_set_opmode()
- */
-static uint16_t
-bhnd_compat_get_chiprev(device_t dev)
-{
-	return (bhnd_get_chipid(dev)->chip_rev);
-}
-
-/*
- * siba_get_chippkg()
- *
- * Referenced by:
- *   bwn_phy_g_init_sub()
- *   bwn_phy_lp_bbinit_r01()
- *   bwn_radio_2056_setup()
- */
-static uint8_t
-bhnd_compat_get_chippkg(device_t dev)
-{
-	return (bhnd_get_chipid(dev)->chip_pkg);
-}
-
-/*
- * siba_get_type()
- *
- * Referenced by:
- *   bwn_core_init()
- *   bwn_dma_attach()
- *   bwn_nphy_op_prepare_structs()
- *   bwn_sprom_bugfixes()
- */
-static enum siba_type
-bhnd_compat_get_type(device_t dev)
-{
-	device_t		bus, hostb;
-	bhnd_devclass_t		hostb_devclass;
-
-	bus = device_get_parent(dev);
-	hostb = bhnd_bus_find_hostb_device(bus);
-
-	if (hostb == NULL)
-		return (SIBA_TYPE_SSB);
-
-	hostb_devclass = bhnd_get_class(hostb);
-	switch (hostb_devclass) {
-	case BHND_DEVCLASS_PCCARD:
-		return (SIBA_TYPE_PCMCIA);
-	case BHND_DEVCLASS_PCI:
-	case BHND_DEVCLASS_PCIE:
-		return (SIBA_TYPE_PCI);
-	default:
-		panic("unsupported hostb devclass: %d\n", hostb_devclass);
-	}
-}
-
-/*
- * siba_get_cc_pmufreq()
- *
- * Referenced by:
- *   bwn_phy_lp_b2062_init()
- *   bwn_phy_lp_b2062_switch_channel()
- *   bwn_phy_lp_b2063_switch_channel()
- *   bwn_phy_lp_rxcal_r2()
- */
-static uint32_t
-bhnd_compat_get_cc_pmufreq(device_t dev)
-{
-	u_int	freq;
-	int	error;
-
-	if ((error = bhnd_get_clock_freq(dev, BHND_CLOCK_ALP, &freq)))
-		panic("failed to fetch clock frequency: %d", error);
-
-	/* TODO: bwn(4) immediately multiplies the result by 1000 (MHz -> Hz) */
-	return (freq / 1000);
-}
-
-/*
- * siba_get_cc_caps()
- *
- * Referenced by:
- *   bwn_phy_lp_b2062_init()
- */
-static uint32_t
-bhnd_compat_get_cc_caps(device_t dev)
-{
-	device_t		 chipc;
-	const struct chipc_caps	*ccaps;
-	uint32_t		 result;
-
-	/* Fetch our ChipCommon device */
-	chipc = bhnd_retain_provider(dev, BHND_SERVICE_CHIPC);
-	if (chipc == NULL)
-		panic("missing ChipCommon device");
-
-	/*
-	 * The ChipCommon capability flags are only used in one LP-PHY function,
-	 * to assert that a PMU is in fact available.
-	 *
-	 * We can support this by producing a value containing just that flag. 
-	 */
-	result = 0;
-	ccaps = BHND_CHIPC_GET_CAPS(chipc);
-	if (ccaps->pmu)
-		result |= SIBA_CC_CAPS_PMU;
-
-	bhnd_release_provider(dev, chipc, BHND_SERVICE_CHIPC);
-
-	return (result);
-}
-
-/*
- * siba_get_cc_powerdelay()
- *
- * Referenced by:
- *   bwn_chip_init()
- */
-static uint16_t
-bhnd_compat_get_cc_powerdelay(device_t dev)
-{
-	u_int	 delay;
-	int	 error;
-
-	if ((error = bhnd_get_clock_latency(dev, BHND_CLOCK_HT, &delay)))
-		panic("failed to fetch clock latency: %d", error);
-
-	if (delay > UINT16_MAX)
-		panic("%#x would overflow", delay);
-
-	return (delay);
-}
-
-/*
- * siba_get_pcicore_revid()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static uint8_t
-bhnd_compat_get_pcicore_revid(device_t dev)
-{
-	device_t	hostb;
-	uint8_t		nomatch_revid;
-
-	/* 
-	 * This is used by bwn(4) in only bwn_core_init(), where a revid <= 10
-	 * results in the BWN_HF_PCI_SLOWCLOCK_WORKAROUND workaround being
-	 * enabled.
-	 * 
-	 * The quirk should only be applied on siba(4) devices using a PCI
-	 * core; we handle around this by returning a bogus value >= 10 here.
-	 * 
-	 * TODO: bwn(4) should match this quirk on:
-	 *	- BHND_CHIPTYPE_SIBA
-	 *	- BHND_COREID_PCI
-	 *	- HWREV_LTE(10)
-	 */
-	nomatch_revid = 0xFF;
-
-	hostb = bhnd_bus_find_hostb_device(device_get_parent(dev));
-	if (hostb == NULL) {
-		/* Not a bridged device */
-		return (nomatch_revid);
-	}
-
-	if (bhnd_get_device(hostb) != BHND_COREID_PCI) {
-		/* Not a PCI core */
-		return (nomatch_revid);
-	}
-
-	/* This is a PCI core; we can return the real core revision */
-	return (bhnd_get_hwrev(hostb));
-}
-
-/*
- * siba_sprom_get_rev()
- *
- * Referenced by:
- *   bwn_nphy_op_prepare_structs()
- *   bwn_nphy_tx_power_ctl_setup()
- *   bwn_nphy_tx_power_fix()
- *   bwn_nphy_workarounds_rev7plus()
- */
-static uint8_t
-bhnd_compat_sprom_get_rev(device_t dev)
-{
-	return (bwn_bhnd_get_ctx(dev)->sromrev);
-}
-
-/*
- * siba_sprom_get_mac_80211bg()
- *
- * Referenced by:
- *   bwn_attach_post()
- */
-static uint8_t *
-bhnd_compat_sprom_get_mac_80211bg(device_t dev)
-{
-	/* 'MAC_80211BG' is il0macaddr or macaddr*/
-	return (bwn_bhnd_get_ctx(dev)->mac_80211bg);
-}
-
-/*
- * siba_sprom_get_mac_80211a()
- *
- * Referenced by:
- *   bwn_attach_post()
- */
-static uint8_t *
-bhnd_compat_sprom_get_mac_80211a(device_t dev)
-{
-	/* 'MAC_80211A' is et1macaddr */
-	return (bwn_bhnd_get_ctx(dev)->mac_80211a);
-}
-
-/*
- * siba_sprom_get_brev()
- *
- * Referenced by:
- *   bwn_radio_init2055_post()
- */
-static uint8_t
-bhnd_compat_sprom_get_brev(device_t dev)
-{
-	/* TODO: bwn(4) needs to switch to uint16_t */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BOARDREV);
-}
-
-/*
- * siba_sprom_get_ccode()
- *
- * Referenced by:
- *   bwn_phy_g_switch_chan()
- */
-static uint8_t
-bhnd_compat_sprom_get_ccode(device_t dev)
-{
-	/* This has been replaced with 'ccode' in later SPROM
-	 * revisions, but this API is only called on devices with
-	 * spromrev 1. */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_CC);
-}
-
-/*
- * siba_sprom_get_ant_a()
- *
- * Referenced by:
- *   bwn_antenna_sanitize()
- */
-static uint8_t
-bhnd_compat_sprom_get_ant_a(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_AA5G);
-}
-
-/*
- * siba_sprom_get_ant_bg()
- *
- * Referenced by:
- *   bwn_antenna_sanitize()
- */
-static uint8_t
-bhnd_compat_sprom_get_ant_bg(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_AA2G);
-}
-
-/*
- * siba_sprom_get_pa0b0()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint16_t
-bhnd_compat_sprom_get_pa0b0(device_t dev)
-{
-	int16_t value;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B0, &value);
-
-	/* TODO: bwn(4) immediately casts this back to int16_t */
-	return ((uint16_t)value);
-}
-
-/*
- * siba_sprom_get_pa0b1()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint16_t
-bhnd_compat_sprom_get_pa0b1(device_t dev)
-{
-	int16_t value;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B1, &value);
-
-	/* TODO: bwn(4) immediately casts this back to int16_t */
-	return ((uint16_t)value);
-}
-
-/*
- * siba_sprom_get_pa0b2()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint16_t
-bhnd_compat_sprom_get_pa0b2(device_t dev)
-{
-	int16_t value;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B2, &value);
-
-	/* TODO: bwn(4) immediately casts this back to int16_t */
-	return ((uint16_t)value);
-}
-
-/**
- * Fetch an led behavior (ledbhX) NVRAM variable value, for use by
- * siba_sprom_get_gpioX().
- * 
- * ('gpioX' are actually the ledbhX NVRAM variables).
- */
-static uint8_t
-bhnd_compat_sprom_get_ledbh(device_t dev, const char *name)
-{
-	uint8_t	value;
-	int	error;
-
-	error = bhnd_nvram_getvar_uint8(dev, name, &value);
-	if (error && error != ENOENT)
-		panic("NVRAM variable %s unreadable: %d", name, error);
-
-	/* For some variables (including ledbhX), a value with all bits set is
-	 * treated as uninitialized in the SPROM format; our SPROM parser
-	 * detects this case and returns ENOENT, but bwn(4) actually expects
-	 * to read the raw value 0xFF value. */
-	if (error == ENOENT)
-		value = 0xFF;
-
-	return (value);
-}
-
-/*
- * siba_sprom_get_gpio0()
- *
- * 'gpioX' are actually the led behavior (ledbh) NVRAM variables.
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio0(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH0));
-}
-
-/*
- * siba_sprom_get_gpio1()
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio1(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH1));
-}
-
-/*
- * siba_sprom_get_gpio2()
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio2(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH2));
-}
-
-/*
- * siba_sprom_get_gpio3()
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio3(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH3));
-}
-
-/*
- * siba_sprom_get_maxpwr_bg()
- *
- * Referenced by:
- *   bwn_phy_g_recalc_txpwr()
- */
-static uint16_t
-bhnd_compat_sprom_get_maxpwr_bg(device_t dev)
-{
-	return (bwn_bhnd_get_ctx(dev)->pa0maxpwr);
-}
-
-/*
- * siba_sprom_set_maxpwr_bg()
- *
- * Referenced by:
- *   bwn_phy_g_recalc_txpwr()
- */
-static void
-bhnd_compat_sprom_set_maxpwr_bg(device_t dev, uint16_t t)
-{
-	KASSERT(t <= UINT8_MAX, ("invalid maxpwr value %hu", t));
-	bwn_bhnd_get_ctx(dev)->pa0maxpwr = t;
-}
-
-/*
- * siba_sprom_get_rxpo2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rxpo2g(device_t dev)
-{
-	/* Should be signed, but bwn(4) expects an unsigned value */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, int8, BHND_NVAR_RXPO2G);
-}
-
-/*
- * siba_sprom_get_rxpo5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rxpo5g(device_t dev)
-{
-	/* Should be signed, but bwn(4) expects an unsigned value */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, int8, BHND_NVAR_RXPO5G);
-}
-
-/*
- * siba_sprom_get_tssi_bg()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_tssi_bg(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PA0ITSSIT);
-}
-
-/*
- * siba_sprom_get_tri2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI2G);
-}
-
-/*
- * siba_sprom_get_tri5gl()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri5gl(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5GL);
-}
-
-/*
- * siba_sprom_get_tri5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5G);
-}
-
-/*
- * siba_sprom_get_tri5gh()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri5gh(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5GH);
-}
-
-/*
- * siba_sprom_get_rssisav2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssisav2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISAV2G);
-}
-
-/*
- * siba_sprom_get_rssismc2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismc2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMC2G);
-}
-
-/*
- * siba_sprom_get_rssismf2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismf2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMF2G);
-}
-
-/*
- * siba_sprom_get_bxa2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_bxa2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BXA2G);
-}
-
-/*
- * siba_sprom_get_rssisav5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssisav5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISAV5G);
-}
-
-/*
- * siba_sprom_get_rssismc5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismc5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMC5G);
-}
-
-/*
- * siba_sprom_get_rssismf5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismf5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMF5G);
-}
-
-/*
- * siba_sprom_get_bxa5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_bxa5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BXA5G);
-}
-
-/*
- * siba_sprom_get_cck2gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint16_t
-bhnd_compat_sprom_get_cck2gpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_CCK2GPO);
-}
-
-/*
- * siba_sprom_get_ofdm2gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm2gpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM2GPO);
-}
-
-/*
- * siba_sprom_get_ofdm5glpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm5glpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GLPO);
-}
-
-/*
- * siba_sprom_get_ofdm5gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm5gpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GPO);
-}
-
-/*
- * siba_sprom_get_ofdm5ghpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm5ghpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GHPO);
-}
-
-/*
- * siba_sprom_set_bf_lo()
- *
- * Referenced by:
- *   bwn_sprom_bugfixes()
- */
-static void
-bhnd_compat_sprom_set_bf_lo(device_t dev, uint16_t t)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	ctx->boardflags &= ~0xFFFF;
-	ctx->boardflags |= t;
-}
-
-/*
- * siba_sprom_get_bf_lo()
- *
- * Referenced by:
- *   bwn_bt_enable()
- *   bwn_core_init()
- *   bwn_gpio_init()
- *   bwn_loopback_calcgain()
- *   bwn_phy_g_init_sub()
- *   bwn_phy_g_recalc_txpwr()
- *   bwn_phy_g_set_txpwr()
- *   bwn_phy_g_task_60s()
- *   bwn_rx_rssi_calc()
- *   bwn_sprom_bugfixes()
- * ... and 11 others
- * 
- */
-static uint16_t
-bhnd_compat_sprom_get_bf_lo(device_t dev)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	return (ctx->boardflags & UINT16_MAX);
-}
-
-/*
- * siba_sprom_get_bf_hi()
- *
- * Referenced by:
- *   bwn_nphy_gain_ctl_workarounds_rev3()
- *   bwn_phy_lp_bbinit_r01()
- *   bwn_phy_lp_tblinit_txgain()
- */
-static uint16_t
-bhnd_compat_sprom_get_bf_hi(device_t dev)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	return (ctx->boardflags >> 16);
-}
-
-/*
- * siba_sprom_get_bf2_lo()
- *
- * Referenced by:
- *   bwn_nphy_op_prepare_structs()
- *   bwn_nphy_workarounds_rev1_2()
- *   bwn_nphy_workarounds_rev3plus()
- *   bwn_phy_initn()
- *   bwn_radio_2056_setup()
- *   bwn_radio_init2055_post()
- */
-static uint16_t
-bhnd_compat_sprom_get_bf2_lo(device_t dev)
-{
-	uint32_t bf2;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, uint32, BHND_NVAR_BOARDFLAGS2, &bf2);
-	return (bf2 & UINT16_MAX);
-}
-
-/*
- * siba_sprom_get_bf2_hi()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev7plus()
- *   bwn_phy_initn()
- *   bwn_radio_2056_setup()
- */
-static uint16_t
-bhnd_compat_sprom_get_bf2_hi(device_t dev)
-{
-	uint32_t bf2;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, uint32, BHND_NVAR_BOARDFLAGS2, &bf2);
-	return (bf2 >> 16);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_tssipos()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_ctl_setup()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_tssipos(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TSSIPOS2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_extpa_gain()
- *
- * Referenced by:
- *   bwn_nphy_op_prepare_structs()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_extpa_gain(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_EXTPAGAIN2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_pdet_range()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev3plus()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_pdet_range(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PDETRANGE2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_tr_iso()
- *
- * Referenced by:
- *   bwn_nphy_get_gain_ctl_workaround_ent()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_tr_iso(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRISO2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_antswlut()
- *
- * Referenced by:
- *   bwn_nphy_tables_init_rev3()
- *   bwn_nphy_tables_init_rev7_volatile()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_antswlut(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_ANTSWCTL2G);
-}
-
-/*
- * siba_sprom_get_fem_5ghz_extpa_gain()
- *
- * Referenced by:
- *   bwn_nphy_get_tx_gain_table()
- *   bwn_nphy_op_prepare_structs()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_5ghz_extpa_gain(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_EXTPAGAIN5G);
-}
-
-/*
- * siba_sprom_get_fem_5ghz_pdet_range()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev3plus()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_5ghz_pdet_range(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PDETRANGE5G);
-}
-
-/*
- * siba_sprom_get_fem_5ghz_antswlut()
- *
- * Referenced by:
- *   bwn_nphy_tables_init_rev3()
- *   bwn_nphy_tables_init_rev7_volatile()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_5ghz_antswlut(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_ANTSWCTL5G);
-}
-
-/*
- * siba_sprom_get_txpid_2g_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_2g_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID2GA0);
-}
-
-/*
- * siba_sprom_get_txpid_2g_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_2g_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID2GA1);
-}
-
-/*
- * siba_sprom_get_txpid_5gl_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gl_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GLA0);
-}
-
-/*
- * siba_sprom_get_txpid_5gl_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gl_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GLA1);
-}
-
-/*
- * siba_sprom_get_txpid_5g_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5g_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GA0);
-}
-
-/*
- * siba_sprom_get_txpid_5g_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5g_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GA1);
-}
-
-/*
- * siba_sprom_get_txpid_5gh_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gh_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GHA0);
-}
-
-/*
- * siba_sprom_get_txpid_5gh_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gh_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GHA1);
-}
-
-/*
- * siba_sprom_get_stbcpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint16_t
-bhnd_compat_sprom_get_stbcpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_STBCPO);
-}
-
-/*
- * siba_sprom_get_cddpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint16_t
-bhnd_compat_sprom_get_cddpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_CDDPO);
-}
-
-/*
- * siba_powerup()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_core_init()
- */
-static void
-bhnd_compat_powerup(device_t dev, int dynamic)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	bhnd_clock		 clock;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	/* On PMU equipped devices, we do not need to issue a clock request
-	 * at powerup */
-	if (ctx->pmu_dev != NULL)
-		return;
-
-	/* Issue a PMU clock request */
-	if (dynamic)
-		clock = BHND_CLOCK_DYN;
-	else
-		clock = BHND_CLOCK_HT;
-
-	if ((error = bhnd_request_clock(dev, clock))) {
-		device_printf(dev, "%d clock request failed: %d\n",
-		    clock, error);
-	}
-
-}
-
-/*
- * siba_powerdown()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_core_exit()
- *   bwn_core_init()
- */
-static int
-bhnd_compat_powerdown(device_t dev)
-{
-	int	error;
-
-	/* Suspend the core */
-	if ((error = bhnd_suspend_hw(dev, 0)))
-		return (error);
-
-	return (0);
-}
-
-/*
- * siba_read_2()
- *
- * Referenced by:
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_dummy_transmission()
- *   bwn_gpio_init()
- *   bwn_phy_getinfo()
- *   bwn_pio_read_2()
- *   bwn_shm_read_2()
- *   bwn_shm_read_4()
- *   bwn_wme_init()
- *   bwn_wme_loadparams()
- * ... and 23 others
- * 
- */
-static uint16_t
-bhnd_compat_read_2(device_t dev, uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	return (bhnd_bus_read_2(sc->sc_mem_res, offset));
-}
-
-/*
- * siba_write_2()
- *
- * Referenced by:
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_crypt_init()
- *   bwn_gpio_init()
- *   bwn_phy_getinfo()
- *   bwn_pio_tx_start()
- *   bwn_set_opmode()
- *   bwn_shm_write_2()
- *   bwn_shm_write_4()
- *   bwn_wme_init()
- * ... and 43 others
- * 
- */
-static void
-bhnd_compat_write_2(device_t dev, uint16_t offset, uint16_t value)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	return (bhnd_bus_write_2(sc->sc_mem_res, offset, value));
-}
-
-/*
- * siba_read_4()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_core_exit()
- *   bwn_core_init()
- *   bwn_core_start()
- *   bwn_pio_init()
- *   bwn_pio_tx_start()
- *   bwn_reset_core()
- *   bwn_shm_read_4()
- * ... and 42 others
- * 
- */
-static uint32_t
-bhnd_compat_read_4(device_t dev, uint16_t offset)
-{
-	struct bwn_softc	*sc = device_get_softc(dev);
-	uint16_t		 ioreg;
-	int			 error;
-
-	/* bwn(4) fetches IOCTL/IOST values directly from siba-specific target
-	 * state registers; we map these directly to bhnd_read_(ioctl|iost) */
-	switch (offset) {
-	case SB0_REG_ABS(SIBA_CFG0_TMSTATELOW):
-		if ((error = bhnd_read_ioctl(dev, &ioreg)))
-			panic("error reading IOCTL: %d\n", error);
-
-		return (((uint32_t)ioreg) << SIBA_TML_SICF_SHIFT);
-
-	case SB0_REG_ABS(SIBA_CFG0_TMSTATEHIGH):
-		if ((error = bhnd_read_iost(dev, &ioreg)))
-			panic("error reading IOST: %d\n", error);
-
-		return (((uint32_t)ioreg) << SIBA_TMH_SISF_SHIFT);
-	}
-
-	/* Otherwise, perform a standard bus read */
-	BWN_ASSERT_VALID_REG(dev, offset);
-	return (bhnd_bus_read_4(sc->sc_mem_res, offset));
-}
-
-/*
- * siba_write_4()
- *
- * Referenced by:
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_core_exit()
- *   bwn_core_start()
- *   bwn_dma_mask()
- *   bwn_dma_rxdirectfifo()
- *   bwn_pio_init()
- *   bwn_reset_core()
- *   bwn_shm_ctlword()
- *   bwn_shm_write_4()
- * ... and 37 others
- * 
- */
-static void
-bhnd_compat_write_4(device_t dev, uint16_t offset, uint32_t value)
-{
-	struct bwn_softc	*sc = device_get_softc(dev);
-	uint16_t		 ioctl;
-	int			 error;
-
-	/* bwn(4) writes IOCTL values directly to siba-specific target state
-	 * registers; we map these directly to bhnd_write_ioctl() */
-	if (offset == SB0_REG_ABS(SIBA_CFG0_TMSTATELOW)) {
-		/* shift IOCTL flags back down to their original values */
-		if (value & ~SIBA_TML_SICF_MASK)
-			panic("%s: non-IOCTL flags provided", __FUNCTION__);
-
-		ioctl = (value & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT;
-
-		if ((error = bhnd_write_ioctl(dev, ioctl, UINT16_MAX)))
-			panic("error writing IOCTL: %d\n", error);
-	} else {
-		/* Otherwise, perform a standard bus write */
-		BWN_ASSERT_VALID_REG(dev, offset);
-
-		bhnd_bus_write_4(sc->sc_mem_res, offset, value);
-	}
-
-	return;
-}
-
-/*
- * siba_dev_up()
- *
- * Referenced by:
- *   bwn_reset_core()
- */
-static void
-bhnd_compat_dev_up(device_t dev, uint32_t flags)
-{
-	uint16_t	ioctl;
-	int		error;
-
-	/* shift IOCTL flags back down to their original values */
-	if (flags & ~SIBA_TML_SICF_MASK)
-		panic("%s: non-IOCTL flags provided", __FUNCTION__);
-
-	ioctl = (flags & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT;
-
-	/* Perform core reset; note that bwn(4) incorrectly assumes that both
-	 * RESET and post-RESET ioctl flags should be identical */
-	if ((error = bhnd_reset_hw(dev, ioctl, ioctl)))
-		panic("%s: core reset failed: %d", __FUNCTION__, error);
-}
-
-/*
- * siba_dev_down()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_core_exit()
- */
-static void
-bhnd_compat_dev_down(device_t dev, uint32_t flags)
-{
-	uint16_t	ioctl;
-	int		error;
-
-	/* shift IOCTL flags back down to their original values */
-	if (flags & ~SIBA_TML_SICF_MASK)
-		panic("%s: non-IOCTL flags provided", __FUNCTION__);
-
-	ioctl = (flags & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT;
-
-	/* Put core into RESET state */
-	if ((error = bhnd_suspend_hw(dev, ioctl)))
-		panic("%s: core suspend failed: %d", __FUNCTION__, error);
-}
-
-/*
- * siba_dev_isup()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static int
-bhnd_compat_dev_isup(device_t dev)
-{
-	return (!bhnd_is_hw_suspended(dev));
-}
-
-/*
- * siba_pcicore_intr()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static void
-bhnd_compat_pcicore_intr(device_t dev)
-{
-	/* This is handled by bhnd_bhndb on the first call to
-	 * bus_setup_intr() */
-}
-
-/*
- * siba_dma_translation()
- *
- * Referenced by:
- *   bwn_dma_32_setdesc()
- *   bwn_dma_64_setdesc()
- *   bwn_dma_setup()
- */
-static uint32_t
-bhnd_compat_dma_translation(device_t dev)
-{
-	struct bhnd_dma_translation	 dt;
-	struct bwn_softc		*sc;
-	struct bwn_mac			*mac;
-	u_int				 width;
-	int				 error;
-
-	sc = device_get_softc(dev);
-	mac = sc->sc_curmac;
-	KASSERT(mac != NULL, ("no MAC"));
-
-	/*
-	 * Use the DMA engine's maximum host address width to determine the
-	 * supported device address width.
-	 */
-	switch (mac->mac_method.dma.dmatype) {
-		case BWN_DMA_32BIT:
-		case BWN_DMA_30BIT:
-			/* The 32-bit engine is always capable of addressing
-			 * a full 32-bit device address */
-			width = BHND_DMA_ADDR_32BIT;
-			break;
-
-		case BWN_DMA_64BIT:
-			width = BHND_DMA_ADDR_64BIT;
-			break;
-
-		default:
-			panic("unknown dma type %d",
-			    mac->mac_method.dma.dmatype);
-	}
-
-
-	/* Fetch our DMA translation */
-	if ((error = bhnd_get_dma_translation(dev, width, 0, NULL, &dt)))
-		panic("error requesting DMA translation: %d\n", error);
-
-	/*
-	 * TODO: bwn(4) needs to switch to bhnd_get_dma_translation().
-	 *
-	 * Currently, bwn(4) incorrectly assumes that:
-	 *  - The 32-bit translation mask is always SIBA_DMA_TRANSLATION_MASK.
-	 *  - The 32-bit mask can simply be applied to the top 32-bits of a
-	 *    64-bit DMA address.
-	 *  - The 64-bit address translation is always derived by shifting the
-	 *    32-bit siba_dma_translation() left by 1 bit.
-	 *
-	 * In practice, these assumptions won't result in any bugs on known
-	 * PCI/PCIe Wi-Fi hardware:
-	 *  - The 32-bit mask _is_ always SIBA_DMA_TRANSLATION_MASK on
-	 *    the subset of devices supported by bwn(4).
-	 *  - The 64-bit mask used by bwn(4) is a superset of the real
-	 *    mask, and thus:
-	 *	- Our DMA tag will still have valid constraints.
-	 *	- Our address translation will not be corrupted by
-	 *	  applying the mask.
-	 *  - The mask falls within the top 16 address bits, and our
-	 *    supported 64-bit architectures are all still limited
-	 *    to 48-bit addresses anyway; we don't need to worry about
-	 *    addressing >= 48-bit host memory.
-	 *
-	 * However, we will need to resolve these issues in bwn(4) if DMA is to
-	 * work on new hardware (e.g. WiSoCs).
-	 */
-	switch (width) {
-	case BHND_DMA_ADDR_32BIT:
-		KASSERT((~dt.addr_mask & BHND_DMA_ADDR_BITMASK(32)) ==
-		    SIBA_DMA_TRANSLATION_MASK, ("unexpected DMA mask: %#jx",
-		    (uintmax_t)dt.addr_mask));
-
-		return (dt.base_addr);
-
-	case BHND_DMA_ADDR_64BIT:
-		/* bwn(4) will shift this left by 32+1 bits before applying it
-		 * to the top 32-bits of the DMA address */
-		KASSERT((~dt.addr_mask & BHND_DMA_ADDR_BITMASK(33)) == 0,
-		    ("DMA64 translation %#jx masks low 33-bits",
-		     (uintmax_t)dt.addr_mask));
-
-		return (dt.base_addr >> 33);
-
-	default:
-		panic("unsupported address width: %u", width);
-	}
-}
-
-/*
- * siba_read_multi_2()
- *
- * Referenced by:
- *   bwn_pio_rxeof()
- */
-static void
-bhnd_compat_read_multi_2(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-	return (bhnd_bus_read_multi_2(sc->sc_mem_res, offset, buffer, count));
-}
-
-/*
- * siba_read_multi_4()
- *
- * Referenced by:
- *   bwn_pio_rxeof()
- */
-static void
-bhnd_compat_read_multi_4(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-	return (bhnd_bus_read_multi_4(sc->sc_mem_res, offset, buffer, count));
-}
-
-/*
- * siba_write_multi_2()
- *
- * Referenced by:
- *   bwn_pio_write_multi_2()
- */
-static void
-bhnd_compat_write_multi_2(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	/* XXX discarding const to maintain API compatibility with
-	 * siba_write_multi_2() */
-	bhnd_bus_write_multi_2(sc->sc_mem_res, offset,
-	    __DECONST(void *, buffer), count);
-}
-
-/*
- * siba_write_multi_4()
- *
- * Referenced by:
- *   bwn_pio_write_multi_4()
- */
-static void
-bhnd_compat_write_multi_4(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	/* XXX discarding const to maintain API compatibility with
-	 * siba_write_multi_4() */
-	bhnd_bus_write_multi_4(sc->sc_mem_res, offset,
-	    __DECONST(void *, buffer), count);
-}
-
-/*
- * siba_barrier()
- *
- * Referenced by:
- *   bwn_intr()
- *   bwn_intrtask()
- *   bwn_ram_write()
- */
-static void
-bhnd_compat_barrier(device_t dev, int flags)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	/* XXX is siba_barrier()'s use of an offset and length of 0
-	 * correct? */
-	BWN_ASSERT_VALID_REG(dev, 0);
-	bhnd_bus_barrier(sc->sc_mem_res, 0, 0, flags);
-}
-
-/*
- * siba_cc_pmu_set_ldovolt()
- *
- * Referenced by:
- *   bwn_phy_lp_bbinit_r01()
- */
-static void
-bhnd_compat_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	/* Only ever used to set the PAREF LDO voltage */
-	if (id != SIBA_LDO_PAREF)
-		panic("invalid LDO id: %d", id);
-
-	/* Configuring regulator voltage requires a PMU */
-	if (ctx->pmu_dev == NULL)
-		panic("no PMU; cannot set LDO voltage");
-
-	error = bhnd_pmu_set_voltage_raw(ctx->pmu_dev, BHND_REGULATOR_PAREF_LDO,
-	    volt);
-	if (error)
-		panic("failed to set LDO voltage: %d", error);
-}
-
-/*
- * siba_cc_pmu_set_ldoparef()
- *
- * Referenced by:
- *   bwn_phy_lp_bbinit_r01()
- */
-static void
-bhnd_compat_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	/* Enabling/disabling regulators requires a PMU */
-	if (ctx->pmu_dev == NULL)
-		panic("no PMU; cannot set LDO voltage");
-
-	if (on) {
-		error = bhnd_pmu_enable_regulator(ctx->pmu_dev,
-		    BHND_REGULATOR_PAREF_LDO);
-	} else {
-		error = bhnd_pmu_disable_regulator(ctx->pmu_dev,
-		    BHND_REGULATOR_PAREF_LDO);
-	}
-
-	if (error) {
-		panic("failed to %s PAREF_LDO: %d", on ? "enable" : "disable",
-		    error);
-	}
-}
-
-/*
- * siba_gpio_set()
- *
- * Referenced by:
- *   bwn_chip_exit()
- *   bwn_chip_init()
- *   bwn_gpio_init()
- *   bwn_nphy_superswitch_init()
- */
-static void
-bhnd_compat_gpio_set(device_t dev, uint32_t value)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	uint32_t		 flags[32];
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	for (size_t i = 0; i < nitems(flags); i++) {
-		if (value & (1 << i)) {
-			/* Tristate pin */
-			flags[i] = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
-		} else {
-			/* Leave unmodified */
-			flags[i] = 0;
-		}
-	}
-
-	error = GPIO_PIN_CONFIG_32(ctx->gpio_dev, 0, nitems(flags), flags);
-	if (error)
-		panic("error configuring pin flags: %d", error);
-}
-
-/*
- * siba_gpio_get()
- *
- * Referenced by:
- *   bwn_gpio_init()
- */
-static uint32_t
-bhnd_compat_gpio_get(device_t dev)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	uint32_t		 ctrl;
-	int			 npin;
-	int			 error;
-
-	/*
-	 * We recreate the expected GPIOCTRL register value for bwn_gpio_init()
-	 * by querying pins individually for GPIO_PIN_TRISTATE.
-	 * 
-	 * Once we drop these compatibility shims, the GPIO_PIN_CONFIG_32 method
-	 * can be used to set pin configuration without bwn(4) externally
-	 * implementing RMW.
-	 */
-
-	/* Fetch the total pin count */
-	ctx = bwn_bhnd_get_ctx(dev);
-	if ((error = GPIO_PIN_MAX(ctx->gpio_dev, &npin)))
-		panic("failed to fetch max pin: %d", error);
-
-	/* Must be representable within a 32-bit GPIOCTRL register value */
-	KASSERT(npin <= 32, ("unsupported pin count: %u", npin));
-
-	ctrl = 0;
-	for (uint32_t pin = 0; pin < npin; pin++) {
-		uint32_t flags;
-
-		if ((error = GPIO_PIN_GETFLAGS(ctx->gpio_dev, pin, &flags)))
-			panic("error fetching pin%u flags: %d", pin, error);
-
-		if (flags & GPIO_PIN_TRISTATE)
-			ctrl |= (1 << pin);
-	}
-
-	return (ctrl);
-}
-
-/*
- * siba_fix_imcfglobug()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static void
-bhnd_compat_fix_imcfglobug(device_t dev)
-{
-	/* This is handled by siba_bhndb during attach/resume */
-}
-
-
-/* Core power NVRAM variables, indexed by D11 core unit number */
-static const struct bwn_power_vars {
-	const char *itt2ga;
-	const char *itt5ga;
-	const char *maxp2ga;
-	const char *pa2ga;
-	const char *pa5ga;
-} bwn_power_vars[BWN_BHND_NUM_CORE_PWR] = {
-#define	BHND_POWER_NVAR(_idx)					\
-	{ BHND_NVAR_ITT2GA ## _idx, BHND_NVAR_ITT5GA ## _idx,	\
-	  BHND_NVAR_MAXP2GA ## _idx, BHND_NVAR_PA2GA ## _idx,	\
-	  BHND_NVAR_PA5GA ## _idx }
-	BHND_POWER_NVAR(0),
-	BHND_POWER_NVAR(1),
-	BHND_POWER_NVAR(2),
-	BHND_POWER_NVAR(3)
-#undef BHND_POWER_NVAR
-};
-
-static int
-bwn_get_core_power_info_r11(device_t dev, const struct bwn_power_vars *v,
-    struct siba_sprom_core_pwr_info *c)
-{
-	int16_t	pa5ga[12];
-	int	error;
-
-	/* BHND_NVAR_PA2GA[core] */
-	error = bhnd_nvram_getvar_array(dev, v->pa2ga, c->pa_2g,
-	    sizeof(c->pa_2g), BHND_NVRAM_TYPE_INT16);
-	if (error)
-		return (error);
-
-	/* 
-	 * BHND_NVAR_PA5GA
-	 * 
-	 * The NVRAM variable is defined as a single pa5ga[12] array; we have
-	 * to split this into pa_5gl[4], pa_5g[4], and pa_5gh[4] for use
-	 * by bwn(4);
-	 */
-	_Static_assert(nitems(pa5ga) == nitems(c->pa_5g) + nitems(c->pa_5gh) +
-	    nitems(c->pa_5gl), "cannot split pa5ga into pa_5gl/pa_5g/pa_5gh");
-
-	error = bhnd_nvram_getvar_array(dev, v->pa5ga, pa5ga, sizeof(pa5ga),
-	    BHND_NVRAM_TYPE_INT16);
-	if (error)
-		return (error);
-
-	memcpy(c->pa_5gl, &pa5ga[0], sizeof(c->pa_5gl));
-	memcpy(c->pa_5g, &pa5ga[4], sizeof(c->pa_5g));
-	memcpy(c->pa_5gh, &pa5ga[8], sizeof(c->pa_5gh));
-	return (0);
-}
-
-static int
-bwn_get_core_power_info_r4_r10(device_t dev,
-    const struct bwn_power_vars *v, struct siba_sprom_core_pwr_info *c)
-{
-	int error;
-
-	/* BHND_NVAR_ITT2GA[core] */
-	if ((error = bhnd_nvram_getvar_uint8(dev, v->itt2ga, &c->itssi_2g)))
-		return (error);
-
-	/* BHND_NVAR_ITT5GA[core] */
-	if ((error = bhnd_nvram_getvar_uint8(dev, v->itt5ga, &c->itssi_5g)))
-		return (error);
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_core_power_info()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_ctl_setup()
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_core_power_info(device_t dev, int core,
-    struct siba_sprom_core_pwr_info *c)
-{
-	struct bwn_bhnd_ctx		*ctx;
-	const struct bwn_power_vars	*v;
-	int				 error;
-
-	if (core < 0 || core >= nitems(bwn_power_vars))
-		return (EINVAL);
-
-	ctx = bwn_bhnd_get_ctx(dev);
-	if (ctx->sromrev < 4)
-		return (ENXIO);
-
-	v = &bwn_power_vars[core];
-
-	/* Any power variables not found in NVRAM (or returning a
-	 * shorter array for a particular NVRAM revision) should be zero
-	 * initialized */
-	memset(c, 0x0, sizeof(*c));
-
-	/* Populate SPROM revision-independent values */
-	if ((error = bhnd_nvram_getvar_uint8(dev, v->maxp2ga, &c->maxpwr_2g)))
-		return (error);
-
-	/* Populate SPROM revision-specific values */
-	if (ctx->sromrev >= 4 && ctx->sromrev <= 10)
-		return (bwn_get_core_power_info_r4_r10(dev, v, c));
-	else
-		return (bwn_get_core_power_info_r11(dev, v, c));
-}
-
-/*
- * siba_sprom_get_mcs2gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs2gpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS2GPO0,
-		BHND_NVAR_MCS2GPO1,
-		BHND_NVAR_MCS2GPO2,
-		BHND_NVAR_MCS2GPO3,
-		BHND_NVAR_MCS2GPO4,
-		BHND_NVAR_MCS2GPO5,
-		BHND_NVAR_MCS2GPO6,
-		BHND_NVAR_MCS2GPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_mcs5glpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs5glpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS5GLPO0,
-		BHND_NVAR_MCS5GLPO1,
-		BHND_NVAR_MCS5GLPO2,
-		BHND_NVAR_MCS5GLPO3,
-		BHND_NVAR_MCS5GLPO4,
-		BHND_NVAR_MCS5GLPO5,
-		BHND_NVAR_MCS5GLPO6,
-		BHND_NVAR_MCS5GLPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_mcs5gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs5gpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS5GPO0,
-		BHND_NVAR_MCS5GPO1,
-		BHND_NVAR_MCS5GPO2,
-		BHND_NVAR_MCS5GPO3,
-		BHND_NVAR_MCS5GPO4,
-		BHND_NVAR_MCS5GPO5,
-		BHND_NVAR_MCS5GPO6,
-		BHND_NVAR_MCS5GPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_mcs5ghpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs5ghpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS5GHPO0,
-		BHND_NVAR_MCS5GHPO1,
-		BHND_NVAR_MCS5GHPO2,
-		BHND_NVAR_MCS5GHPO3,
-		BHND_NVAR_MCS5GHPO4,
-		BHND_NVAR_MCS5GHPO5,
-		BHND_NVAR_MCS5GHPO6,
-		BHND_NVAR_MCS5GHPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_pmu_spuravoid_pllupdate()
- *
- * Referenced by:
- *   bwn_nphy_pmu_spur_avoid()
- */
-static void
-bhnd_compat_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	bhnd_pmu_spuravoid	 mode;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	if (ctx->pmu_dev == NULL)
-		panic("requested spuravoid on non-PMU device");
-
-	switch (spur_avoid) {
-	case 0:
-		mode = BHND_PMU_SPURAVOID_NONE;
-		break;
-	case 1:
-		mode = BHND_PMU_SPURAVOID_M1;
-		break;
-	default:
-		panic("unknown spur_avoid: %d", spur_avoid);
-	}
-
-	if ((error = bhnd_pmu_request_spuravoid(ctx->pmu_dev, mode)))
-		panic("spuravoid request failed: %d", error);
-}
-
-/*
- * siba_cc_set32()
- *
- * Referenced by:
- *   bwn_phy_initn()
- *   bwn_wireless_core_phy_pll_reset()
- */
-static void
-bhnd_compat_cc_set32(device_t dev, uint32_t reg, uint32_t val)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	
-	/*
-	 * OR with the current value.
-	 *
-	 * This function is only ever used to write to either ChipCommon's
-	 * chipctrl register or chipctl_data register. Note that chipctl_data
-	 * is actually a PMU register; it is not actually mapped by ChipCommon
-	 * on Always-on-Bus (AOB) devices with a standalone PMU core.
-	 */
-	if (dev != ctx->chipc_dev)
-		panic("unsupported device: %s", device_get_nameunit(dev));
-
-	switch (reg) {
-	case SIBA_CC_CHIPCTL:
-		BHND_CHIPC_WRITE_CHIPCTRL(ctx->chipc_dev, val, val);
-		break;
-	case SIBA_CC_CHIPCTL_DATA:
-		bhnd_pmu_write_chipctrl(ctx->pmu_dev, ctx->pmu_cctl_addr, val,
-		    val);
-		break;
-	default:
-		panic("unsupported register: %#x", reg);
-	}
-}
-
-/*
- * siba_cc_mask32()
- *
- * Referenced by:
- *   bwn_wireless_core_phy_pll_reset()
- */
-static void
-bhnd_compat_cc_mask32(device_t dev, uint32_t reg, uint32_t mask)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-
-	/*
-	 * AND with the current value.
-	 *
-	 * This function is only ever used to write to ChipCommon's chipctl_data
-	 * register. Note that chipctl_data is actually a PMU register; it is
-	 * not actually mapped by ChipCommon on Always-on-Bus (AOB) devices with
-	 * a standalone PMU core.
-	 */
-	if (dev != ctx->chipc_dev)
-		panic("unsupported device: %s", device_get_nameunit(dev));
-
-	switch (reg) {
-	case SIBA_CC_CHIPCTL_DATA:
-		bhnd_pmu_write_chipctrl(ctx->pmu_dev, ctx->pmu_cctl_addr, 0,
-		    ~mask);
-		break;
-	default:
-		panic("unsupported register: %#x", reg);
-	}
-}
-
-/*
- * siba_cc_write32()
- *
- * Referenced by:
- *   bwn_wireless_core_phy_pll_reset()
- */
-static void
-bhnd_compat_cc_write32(device_t dev, uint32_t reg, uint32_t val)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-
-	/*
-	 * This function is only ever used to write to ChipCommon's chipctl_addr
-	 * register; setting chipctl_addr is handled atomically by
-	 * bhnd_pmu_write_chipctrl(), so we merely cache the intended address
-	 * for later use when chipctl_data is written.
-	 *
-	 * Also, note that chipctl_addr is actually a PMU register; it is
-	 * not actually mapped by ChipCommon on Always-on-Bus (AOB) devices with
-	 * a standalone PMU core.
-	 */
-	if (dev != ctx->chipc_dev)
-		panic("unsupported device: %s", device_get_nameunit(dev));
-
-	switch (reg) {
-	case SIBA_CC_CHIPCTL_ADDR:
-		ctx->pmu_cctl_addr = val;
-		break;
-	default:
-		panic("unsupported register: %#x", reg);
-	}
-}
-
-const struct bwn_bus_ops bwn_bhnd_bus_ops = {
-	.init				= bwn_bhnd_bus_ops_init,
-	.fini				= bwn_bhnd_bus_ops_fini,
-	.pci_find_cap			= bhnd_compat_pci_find_cap,
-	.pci_alloc_msi			= bhnd_compat_pci_alloc_msi,
-	.pci_release_msi		= bhnd_compat_pci_release_msi,
-	.pci_msi_count			= bhnd_compat_pci_msi_count,
-	.get_vendor			= bhnd_compat_get_vendor,
-	.get_device			= bhnd_compat_get_device,
-	.get_revid			= bhnd_compat_get_revid,
-	.get_pci_vendor			= bhnd_compat_get_pci_vendor,
-	.get_pci_device			= bhnd_compat_get_pci_device,
-	.get_pci_subvendor		= bhnd_compat_get_pci_subvendor,
-	.get_pci_subdevice		= bhnd_compat_get_pci_subdevice,
-	.get_pci_revid			= bhnd_compat_get_pci_revid,
-	.get_chipid			= bhnd_compat_get_chipid,
-	.get_chiprev			= bhnd_compat_get_chiprev,
-	.get_chippkg			= bhnd_compat_get_chippkg,
-	.get_type			= bhnd_compat_get_type,
-	.get_cc_pmufreq			= bhnd_compat_get_cc_pmufreq,
-	.get_cc_caps			= bhnd_compat_get_cc_caps,
-	.get_cc_powerdelay		= bhnd_compat_get_cc_powerdelay,
-	.get_pcicore_revid		= bhnd_compat_get_pcicore_revid,
-	.sprom_get_rev			= bhnd_compat_sprom_get_rev,
-	.sprom_get_mac_80211bg		= bhnd_compat_sprom_get_mac_80211bg,
-	.sprom_get_mac_80211a		= bhnd_compat_sprom_get_mac_80211a,
-	.sprom_get_brev			= bhnd_compat_sprom_get_brev,
-	.sprom_get_ccode		= bhnd_compat_sprom_get_ccode,
-	.sprom_get_ant_a		= bhnd_compat_sprom_get_ant_a,
-	.sprom_get_ant_bg		= bhnd_compat_sprom_get_ant_bg,
-	.sprom_get_pa0b0		= bhnd_compat_sprom_get_pa0b0,
-	.sprom_get_pa0b1		= bhnd_compat_sprom_get_pa0b1,
-	.sprom_get_pa0b2		= bhnd_compat_sprom_get_pa0b2,
-	.sprom_get_gpio0		= bhnd_compat_sprom_get_gpio0,
-	.sprom_get_gpio1		= bhnd_compat_sprom_get_gpio1,
-	.sprom_get_gpio2		= bhnd_compat_sprom_get_gpio2,
-	.sprom_get_gpio3		= bhnd_compat_sprom_get_gpio3,
-	.sprom_get_maxpwr_bg		= bhnd_compat_sprom_get_maxpwr_bg,
-	.sprom_set_maxpwr_bg		= bhnd_compat_sprom_set_maxpwr_bg,
-	.sprom_get_rxpo2g		= bhnd_compat_sprom_get_rxpo2g,
-	.sprom_get_rxpo5g		= bhnd_compat_sprom_get_rxpo5g,
-	.sprom_get_tssi_bg		= bhnd_compat_sprom_get_tssi_bg,
-	.sprom_get_tri2g		= bhnd_compat_sprom_get_tri2g,
-	.sprom_get_tri5gl		= bhnd_compat_sprom_get_tri5gl,
-	.sprom_get_tri5g		= bhnd_compat_sprom_get_tri5g,
-	.sprom_get_tri5gh		= bhnd_compat_sprom_get_tri5gh,
-	.sprom_get_rssisav2g		= bhnd_compat_sprom_get_rssisav2g,
-	.sprom_get_rssismc2g		= bhnd_compat_sprom_get_rssismc2g,
-	.sprom_get_rssismf2g		= bhnd_compat_sprom_get_rssismf2g,
-	.sprom_get_bxa2g		= bhnd_compat_sprom_get_bxa2g,
-	.sprom_get_rssisav5g		= bhnd_compat_sprom_get_rssisav5g,
-	.sprom_get_rssismc5g		= bhnd_compat_sprom_get_rssismc5g,
-	.sprom_get_rssismf5g		= bhnd_compat_sprom_get_rssismf5g,
-	.sprom_get_bxa5g		= bhnd_compat_sprom_get_bxa5g,
-	.sprom_get_cck2gpo		= bhnd_compat_sprom_get_cck2gpo,
-	.sprom_get_ofdm2gpo		= bhnd_compat_sprom_get_ofdm2gpo,
-	.sprom_get_ofdm5glpo		= bhnd_compat_sprom_get_ofdm5glpo,
-	.sprom_get_ofdm5gpo		= bhnd_compat_sprom_get_ofdm5gpo,
-	.sprom_get_ofdm5ghpo		= bhnd_compat_sprom_get_ofdm5ghpo,
-	.sprom_get_bf_lo		= bhnd_compat_sprom_get_bf_lo,
-	.sprom_set_bf_lo		= bhnd_compat_sprom_set_bf_lo,
-	.sprom_get_bf_hi		= bhnd_compat_sprom_get_bf_hi,
-	.sprom_get_bf2_lo		= bhnd_compat_sprom_get_bf2_lo,
-	.sprom_get_bf2_hi		= bhnd_compat_sprom_get_bf2_hi,
-	.sprom_get_fem_2ghz_tssipos	= bhnd_compat_sprom_get_fem_2ghz_tssipos,
-	.sprom_get_fem_2ghz_extpa_gain	= bhnd_compat_sprom_get_fem_2ghz_extpa_gain,
-	.sprom_get_fem_2ghz_pdet_range	= bhnd_compat_sprom_get_fem_2ghz_pdet_range,
-	.sprom_get_fem_2ghz_tr_iso	= bhnd_compat_sprom_get_fem_2ghz_tr_iso,
-	.sprom_get_fem_2ghz_antswlut	= bhnd_compat_sprom_get_fem_2ghz_antswlut,
-	.sprom_get_fem_5ghz_extpa_gain	= bhnd_compat_sprom_get_fem_5ghz_extpa_gain,
-	.sprom_get_fem_5ghz_pdet_range	= bhnd_compat_sprom_get_fem_5ghz_pdet_range,
-	.sprom_get_fem_5ghz_antswlut	= bhnd_compat_sprom_get_fem_5ghz_antswlut,
-	.sprom_get_txpid_2g_0		= bhnd_compat_sprom_get_txpid_2g_0,
-	.sprom_get_txpid_2g_1		= bhnd_compat_sprom_get_txpid_2g_1,
-	.sprom_get_txpid_5gl_0		= bhnd_compat_sprom_get_txpid_5gl_0,
-	.sprom_get_txpid_5gl_1		= bhnd_compat_sprom_get_txpid_5gl_1,
-	.sprom_get_txpid_5g_0		= bhnd_compat_sprom_get_txpid_5g_0,
-	.sprom_get_txpid_5g_1		= bhnd_compat_sprom_get_txpid_5g_1,
-	.sprom_get_txpid_5gh_0		= bhnd_compat_sprom_get_txpid_5gh_0,
-	.sprom_get_txpid_5gh_1		= bhnd_compat_sprom_get_txpid_5gh_1,
-	.sprom_get_stbcpo		= bhnd_compat_sprom_get_stbcpo,
-	.sprom_get_cddpo		= bhnd_compat_sprom_get_cddpo,
-	.powerup			= bhnd_compat_powerup,
-	.powerdown			= bhnd_compat_powerdown,
-	.read_2				= bhnd_compat_read_2,
-	.write_2			= bhnd_compat_write_2,
-	.read_4				= bhnd_compat_read_4,
-	.write_4			= bhnd_compat_write_4,
-	.dev_up				= bhnd_compat_dev_up,
-	.dev_down			= bhnd_compat_dev_down,
-	.dev_isup			= bhnd_compat_dev_isup,
-	.pcicore_intr			= bhnd_compat_pcicore_intr,
-	.dma_translation		= bhnd_compat_dma_translation,
-	.read_multi_2			= bhnd_compat_read_multi_2,
-	.read_multi_4			= bhnd_compat_read_multi_4,
-	.write_multi_2			= bhnd_compat_write_multi_2,
-	.write_multi_4			= bhnd_compat_write_multi_4,
-	.barrier			= bhnd_compat_barrier,
-	.cc_pmu_set_ldovolt		= bhnd_compat_cc_pmu_set_ldovolt,
-	.cc_pmu_set_ldoparef		= bhnd_compat_cc_pmu_set_ldoparef,
-	.gpio_set			= bhnd_compat_gpio_set,
-	.gpio_get			= bhnd_compat_gpio_get,
-	.fix_imcfglobug			= bhnd_compat_fix_imcfglobug,
-	.sprom_get_core_power_info	= bhnd_compat_sprom_get_core_power_info,
-	.sprom_get_mcs2gpo		= bhnd_compat_sprom_get_mcs2gpo,
-	.sprom_get_mcs5glpo		= bhnd_compat_sprom_get_mcs5glpo,
-	.sprom_get_mcs5gpo		= bhnd_compat_sprom_get_mcs5gpo,
-	.sprom_get_mcs5ghpo		= bhnd_compat_sprom_get_mcs5ghpo,
-	.pmu_spuravoid_pllupdate	= bhnd_compat_pmu_spuravoid_pllupdate,
-	.cc_set32			= bhnd_compat_cc_set32,
-	.cc_mask32			= bhnd_compat_cc_mask32,
-	.cc_write32			= bhnd_compat_cc_write32,
-};
diff --git a/sys/dev/bwn/if_bwn_siba_compat.h b/sys/dev/bwn/if_bwn_siba_compat.h
deleted file mode 100644
index 36bd9783e52d..000000000000
--- a/sys/dev/bwn/if_bwn_siba_compat.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon J. Fuller <landonf@FreeBSD.org>.
- * Copyright (c) 2017 The FreeBSD Foundation
- * All rights reserved.
- *
- * Portions of this software were developed by Landon Fuller
- * under sponsorship from the FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _IF_BWN_SIBA_COMPAT_H_
-#define _IF_BWN_SIBA_COMPAT_H_
-
-#define	BWN_USE_SIBA	0
-#include "if_bwn_siba.h"
-
-#include "if_bwnvar.h"
-
-#define	BWN_BHND_NUM_CORE_PWR	4
-
-/**
- * Compatiblity shim state.
- */
-struct bwn_bhnd_ctx {
-	device_t	chipc_dev;	/**< ChipCommon device */
-	device_t	gpio_dev;	/**< GPIO device */
-
-	device_t	pmu_dev;	/**< PMU device, or NULL if no PMU */
-	uint32_t	pmu_cctl_addr;	/**< chipctrl_addr target of
-					     reads/writes to/from the
-					     chipctrl_data register */
-
-	uint8_t		sromrev;	/**< SROM format revision */
-
-	/* NVRAM variables for which bwn(4) expects the bus to manage storage
-	 * for (and in some cases, allow writes). */	
-	uint8_t		mac_80211bg[6];	/**< D11 unit 0 */
-	uint8_t		mac_80211a[6];	/**< D11 unit 1 */
-
-	uint32_t	boardflags;	/**< boardflags (bwn-writable) */
-	uint8_t		pa0maxpwr;	/**< 2GHz max power (bwn-writable) */
-};
-
-/**
- * Return the bwn(4) device's bhnd compatiblity context.
- */
-static inline struct bwn_bhnd_ctx *
-bwn_bhnd_get_ctx(device_t dev)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-	return (sc->sc_bus_ctx);
-}
-
-/**
- * Fetch an NVRAM variable via bhnd_nvram_getvar_*().
- */
-#define	BWN_BHND_NVRAM_FETCH_VAR(_dev, _type, _name, _result)		\
-do {									\
-	int error;							\
-									\
-	error = bhnd_nvram_getvar_ ## _type(_dev, _name, _result);	\
-	if (error) {							\
-		panic("NVRAM variable %s unreadable: %d", _name,	\
-		    error);						\
-	}								\
-} while(0)
-
-/**
- * Fetch and return an NVRAM variable via bhnd_nvram_getvar_*().
- */
-#define	BWN_BHND_NVRAM_RETURN_VAR(_dev, _type, _name)			\
-do {									\
-	_type ## _t	value;						\
-	BWN_BHND_NVRAM_FETCH_VAR(_dev, _type, _name, &value);		\
-	return (value);							\
-} while(0)
-
-#endif /* _IF_BWN_SIBA_COMPAT_H_ */
diff --git a/sys/dev/bwn/if_bwn_util.c b/sys/dev/bwn/if_bwn_util.c
index c1799d09172a..41aa94f1aaec 100644
--- a/sys/dev/bwn/if_bwn_util.c
+++ b/sys/dev/bwn/if_bwn_util.c
@@ -72,12 +72,9 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
-
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
-#include <dev/bwn/if_bwn_chipid.h>
 #include <dev/bwn/if_bwn_debug.h>
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_util.h>
diff --git a/sys/dev/bwn/if_bwnreg.h b/sys/dev/bwn/if_bwnreg.h
index 2437a68e0513..87bc4cb021c8 100644
--- a/sys/dev/bwn/if_bwnreg.h
+++ b/sys/dev/bwn/if_bwnreg.h
@@ -34,83 +34,22 @@
 #ifndef _IF_BWNREG_H
 #define	_IF_BWNREG_H
 
-#define	PCI_VENDOR_COMPAQ		0x0e11
-#define	PCI_VENDOR_DELL			0x1028
-#define	PCI_VENDOR_HP			0x103c
-#define	PCI_VENDOR_ASUSTEK		0x1043
-#define	PCI_VENDOR_MOTOROLA		0x1057
-#define	PCI_VENDOR_APPLE		0x106b
-#define	PCI_VENDOR_BROADCOM		0x14e4
-#define	PCI_VENDOR_LINKSYS		0x1737
-
-/* SPROM flags */
-#define	BWN_BFL_BTCOEXIST		0x0001  /* implements Bluetooth coexistance */
-#define	BWN_BFL_PACTRL			0x0002  /* GPIO 9 controlling the PA */
-#define	BWN_BFL_AIRLINEMODE		0x0004  /* implements GPIO 13 radio disable indication */
-#define	BWN_BFL_RSSI			0x0008  /* software calculates nrssi slope. */
-#define	BWN_BFL_ENETSPI			0x0010  /* has ephy roboswitch spi */
-#define	BWN_BFL_CRYSTAL_NOSLOW		0x0020  /* no slow clock available */
-#define	BWN_BFL_CCKHIPWR		0x0040  /* can do high power CCK transmission */
-#define	BWN_BFL_ENETADM			0x0080  /* has ADMtek switch */
-#define	BWN_BFL_ENETVLAN		0x0100  /* can do vlan */
-#define	BWN_BFL_AFTERBURNER		0x0200  /* supports Afterburner mode */
-#define	BWN_BFL_NOPCI			0x0400  /* leaves PCI floating */
-#define	BWN_BFL_FEM			0x0800  /* supports the Front End Module */
-#define	BWN_BFL_EXTLNA			0x1000  /* has an external LNA */
-#define	BWN_BFL_HGPA			0x2000  /* had high gain PA */
-#define	BWN_BFL_BTCMOD			0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
-#define	BWN_BFL_ALTIQ			0x8000  /* alternate I/Q settings */
-
-/* SPROM boardflags_hi values */
-#define	BWN_BFH_NOPA			0x0001  /* has no PA */
-#define	BWN_BFH_RSSIINV			0x0002  /* RSSI uses positive slope (not TSSI) */
-#define	BWN_BFH_LDO_PAREF		0x0004  /* uses the PARef LDO */
-#define	BWN_BFH_3TSWITCH		0x0008  /* uses a triple throw switch shared
-						 * with bluetooth */
-#define	BWN_BFH_PHASESHIFT		0x0010  /* can support phase shifter */
-#define	BWN_BFH_BUCKBOOST		0x0020  /* has buck/booster */
-#define	BWN_BFH_FEM_BT			0x0040  /* has FEM and switch to share antenna
-						 * with bluetooth */
-#define	BWN_BFH_NOCBUCK			0x0080
-#define	BWN_BFH_PALDO			0x0200
-#define	BWN_BFH_EXTLNA_5GHZ		0x1000  /* has an external LNA (5GHz mode) */
-
-/* SPROM boardflags2_lo values */
-#define	BWN_BFL2_RXBB_INT_REG_DIS	0x0001  /* external RX BB regulator present */
-#define	BWN_BFL2_APLL_WAR		0x0002  /* alternative A-band PLL settings implemented */
-#define	BWN_BFL2_TXPWRCTRL_EN		0x0004  /* permits enabling TX Power Control */
-#define	BWN_BFL2_2X4_DIV		0x0008  /* 2x4 diversity switch */
-#define	BWN_BFL2_5G_PWRGAIN		0x0010  /* supports 5G band power gain */
-#define	BWN_BFL2_PCIEWAR_OVR		0x0020  /* overrides ASPM and Clkreq settings */
-#define	BWN_BFL2_CAESERS_BRD		0x0040  /* is Caesers board (unused) */
-#define	BWN_BFL2_BTC3WIRE		0x0080  /* used 3-wire bluetooth coexist */
-#define	BWN_BFL2_SKWRKFEM_BRD		0x0100  /* 4321mcm93 uses Skyworks FEM */
-#define	BWN_BFL2_SPUR_WAR		0x0200  /* has a workaround for clock-harmonic spurs */
-#define	BWN_BFL2_GPLL_WAR		0x0400  /* altenative G-band PLL settings implemented */
-#define	BWN_BFL2_SINGLEANT_CCK		0x1000
-#define	BWN_BFL2_2G_SPUR_WAR		0x2000
-
-/* SPROM boardflags2_hi values */
-#define	BWN_BFH2_GPLL_WAR2		0x0001
-#define	BWN_BFH2_IPALVLSHIFT_3P3	0x0002
-#define	BWN_BFH2_INTERNDET_TXIQCAL	0x0004
-#define	BWN_BFH2_XTALBUFOUTEN		0x0008
-
-/* SIBA control registers */
-#define	BWN_TGSLOW_PHYCLOCK_ENABLE	0x00040000
-#define	BWN_TGSLOW_PHYRESET		0x00080000
-#define	BWN_TGSLOW_MACPHYCLKEN		0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
-#define	BWN_TGSLOW_PLLREFSEL		0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
+/* D11-specific I/O control flags */
+#define	BWN_IOCTL_PHYCLOCK_ENABLE	0x0004
+#define	BWN_IOCTL_PHYRESET		0x0008
+#define	BWN_IOCTL_MACPHYCLKEN		0x0010	/* MAC PHY Clock Control Enable (rev >= 5) */
+#define	BWN_IOCTL_PLLREFSEL		0x0020	/* PLL Frequency Reference Select (rev >= 5) */
 /* PHY_BANDWIDTH: N-PHY only */
-#define	BWN_TGSLOW_PHY_BANDWIDTH	0x00C00000
-#define	BWN_TGSLOW_PHY_BANDWIDTH_10MHZ	0x00000000
-#define	BWN_TGSLOW_PHY_BANDWIDTH_20MHZ	0x00400000
-#define	BWN_TGSLOW_PHY_BANDWIDTH_40MHZ	0x00800000
-#define	BWN_TGSLOW_SUPPORT_G		0x20000000
+#define	BWN_IOCTL_PHY_BANDWIDTH		0x00C0
+#define	BWN_IOCTL_PHY_BANDWIDTH_10MHZ	0x0000
+#define	BWN_IOCTL_PHY_BANDWIDTH_20MHZ	0x0040
+#define	BWN_IOCTL_PHY_BANDWIDTH_40MHZ	0x0080
+#define	BWN_IOCTL_SUPPORT_G		0x2000
 
-#define	BWN_TGSHIGH_HAVE_2GHZ		0x00010000
-#define	BWN_TGSHIGH_HAVE_5GHZ		0x00020000
-#define	BWN_TGSHIGH_DUALPHY		0x00080000
+/* D11-specific I/O status flags */
+#define	BWN_IOST_HAVE_2GHZ		0x0001
+#define	BWN_IOST_HAVE_5GHZ		0x0002
+#define	BWN_IOST_DUALPHY		0x0008
 
 #define	BWN_PHYTYPE_A			0x00
 #define	BWN_PHYTYPE_B			0x01
@@ -433,6 +372,8 @@
 #define	BWN_DMA32_RXDPTR		0x00000fff
 #define	BWN_DMA32_RXSTATE		0x0000f000
 #define	BWN_DMA32_RXSTAT_DISABLED	0x00000000
+#define	BWN_DMA32_ADDREXT_MASK		0xC0000000
+#define	BWN_DMA32_ADDREXT_SHIFT		30
 #define	BWN_DMA64_TXCTL			0x00
 #define	BWN_DMA64_TXENABLE		0x00000001
 #define	BWN_DMA64_TXSUSPEND		0x00000002
@@ -461,6 +402,8 @@
 #define	BWN_DMA64_RXSTATDPTR		0x00001fff
 #define	BWN_DMA64_RXSTAT		0xf0000000
 #define	BWN_DMA64_RXSTAT_DISABLED	0x00000000
+#define	BWN_DMA64_ADDREXT_MASK		0xC000000000000000ULL
+#define	BWN_DMA64_ADDREXT_SHIFT		62
 #define	BWN_DMA_RINGMEMSIZE		PAGE_SIZE
 #define	BWN_DMA0_RX_FRAMEOFFSET_FW351	30
 #define	BWN_DMA0_RX_FRAMEOFFSET_FW598	38
@@ -724,6 +667,23 @@
 #define	BWN_TAB_NOISESCALE_SIZE		27
 
 /*
+ * SPROM rev 1 locale codes. Later SPROM revisions use a two-character
+ * country code.
+ */
+enum {
+	BWN_SPROM1_CC_WORLDWIDE	= 0,
+	BWN_SPROM1_CC_THAILAND	= 1,
+	BWN_SPROM1_CC_ISRAEL	= 2,
+	BWN_SPROM1_CC_JORDAN	= 3,
+	BWN_SPROM1_CC_CHINA	= 4,
+	BWN_SPROM1_CC_JP	= 5,
+	BWN_SPROM1_CC_USA	= 6,
+	BWN_SPROM1_CC_EUROPE	= 7,
+	BWN_SPROM1_CC_US_LOW	= 8,
+	BWN_SPROM1_CC_JP_HIGH	= 9,
+};
+
+/*
  * SPROM GPIO
  */
 #define	BWN_LED_ACT_LOW			0x80
@@ -741,7 +701,7 @@
 #define	BWN_LED_ACT_ASSOC		10
 #define	BWN_LED_ACT_NULL		11
 
-#define	BWN_VENDOR_LED_ACT_COMPAQ	\
+#define	BWN_VENDOR_LED_ACT_HP_COMPAQ	\
 	BWN_LED_ACT_RF_ENABLED,		\
 	BWN_LED_ACT_2GHZ,		\
 	BWN_LED_ACT_5GHZ,		\
diff --git a/sys/dev/bwn/if_bwnvar.h b/sys/dev/bwn/if_bwnvar.h
index 686b671df290..2d77f8c4db46 100644
--- a/sys/dev/bwn/if_bwnvar.h
+++ b/sys/dev/bwn/if_bwnvar.h
@@ -34,19 +34,13 @@
 #ifndef _IF_BWNVAR_H
 #define	_IF_BWNVAR_H
 
-#include "if_bwn_siba.h"
+#include <dev/bhnd/bhnd.h>
 
 struct bwn_softc;
 struct bwn_mac;
 
-extern driver_t bwn_driver;
-
-int	bwn_attach(device_t dev);
-int	bwn_detach(device_t dev);
-
 #define	N(a)			(sizeof(a) / sizeof(a[0]))
 #define	BWN_ALIGN			0x1000
-#define	BWN_BUS_SPACE_MAXADDR_30BIT	0x3fffffff
 #define	BWN_RETRY_SHORT			7
 #define	BWN_RETRY_LONG			4
 #define	BWN_STAID_MAX			64
@@ -73,10 +67,12 @@ int	bwn_detach(device_t dev);
 	((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index))
 #define	BWN_DMA_COOKIE(dr, slot)					\
 	((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot)
-#define	BWN_READ_2(mac, o)		(siba_read_2(mac->mac_sc->sc_dev, o))
-#define	BWN_READ_4(mac, o)		(siba_read_4(mac->mac_sc->sc_dev, o))
+#define	BWN_READ_2(mac, o)						\
+	(bus_read_2((mac)->mac_sc->sc_mem_res, (o)))
+#define	BWN_READ_4(mac, o)						\
+	(bus_read_4((mac)->mac_sc->sc_mem_res, (o)))
 #define	BWN_WRITE_2(mac, o, v)						\
-	(siba_write_2(mac->mac_sc->sc_dev, o, v))
+	(bus_write_2((mac)->mac_sc->sc_mem_res, (o), (v)))
 #define	BWN_WRITE_2_F(mac, o, v) do { \
 	(BWN_WRITE_2(mac, o, v)); \
 	BWN_READ_2(mac, o); \
@@ -84,13 +80,13 @@ int	bwn_detach(device_t dev);
 #define	BWN_WRITE_SETMASK2(mac, offset, mask, set)			\
 	BWN_WRITE_2(mac, offset, (BWN_READ_2(mac, offset) & mask) | set)
 #define	BWN_WRITE_4(mac, o, v)						\
-	(siba_write_4(mac->mac_sc->sc_dev, o, v))
+	(bus_write_4((mac)->mac_sc->sc_mem_res, (o), (v)))
 #define	BWN_WRITE_SETMASK4(mac, offset, mask, set)			\
 	BWN_WRITE_4(mac, offset, (BWN_READ_4(mac, offset) & mask) | set)
 #define	BWN_PIO_TXQOFFSET(mac)						\
-	((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0)
+	((bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0)
 #define	BWN_PIO_RXQOFFSET(mac)						\
-	((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8)
+	((bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8)
 #define	BWN_SEC_NEWAPI(mac)		(mac->mac_fw.rev >= 351)
 #define	BWN_SEC_KEY2FW(mac, idx)					\
 	(BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx))
@@ -144,7 +140,6 @@ int	bwn_detach(device_t dev);
 #define BWN_LO_CALIB_EXPIRE		(1000 * (30 - 2))
 #define BWN_LO_PWRVEC_EXPIRE		(1000 * (30 - 2))
 #define BWN_LO_TXCTL_EXPIRE		(1000 * (180 - 4))
-#define	BWN_DMA_BIT_MASK(n)		(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
 #define BWN_LPD(L, P, D)		(((L) << 2) | ((P) << 1) | ((D) << 0))
 #define BWN_BITREV4(tmp)		(BWN_BITREV8(tmp) >> 4)
 #define	BWN_BITREV8(byte)		(bwn_bitrev_table[byte])
@@ -159,7 +154,8 @@ int	bwn_detach(device_t dev);
 	(rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB ||	\
 	 rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB)
 #define	BWN_ISOFDMRATE(rate)		(!BWN_ISCCKRATE(rate))
-#define	BWN_BARRIER(mac, flags)		siba_barrier(mac->mac_sc->sc_dev, flags)
+#define	BWN_BARRIER(mac, offset, length, flags)			\
+	bus_barrier((mac)->mac_sc->sc_mem_res, (offset), (length), (flags))
 #define	BWN_DMA_READ(dr, offset)				\
 	(BWN_READ_4(dr->dr_mac, dr->dr_base + offset))
 #define	BWN_DMA_WRITE(dr, offset, value)			\
@@ -349,6 +345,7 @@ struct bwn_phy_g {
 	uint16_t			pg_radioctx_overval;
 	uint16_t			pg_minlowsig[2];
 	uint16_t			pg_minlowsigpos[2];
+	uint16_t			pg_pa0maxpwr;
 	int8_t				*pg_tssi2dbm;
 	int				pg_idletssi;
 	int				pg_curtssi;
@@ -606,10 +603,6 @@ struct bwn_noise {
 	int8_t				noi_samples[8][4];
 };
 
-#define	BWN_DMA_30BIT			30
-#define	BWN_DMA_32BIT			32
-#define	BWN_DMA_64BIT			64
-
 struct bwn_dmadesc_meta {
 	bus_dmamap_t			mt_dmap;
 	bus_addr_t			mt_paddr;
@@ -701,10 +694,11 @@ struct bwn_dma_ring {
 };
 
 struct bwn_dma {
-	int				dmatype;
 	bus_dma_tag_t			parent_dtag;
 	bus_dma_tag_t			rxbuf_dtag;
 	bus_dma_tag_t			txbuf_dtag;
+	struct bhnd_dma_translation	translation;
+	u_int				addrext_shift;
 
 	struct bwn_dma_ring		*wme[5];
 	struct bwn_dma_ring		*mcast;
@@ -948,11 +942,9 @@ struct bwn_mac {
 #define	BWN_MAC_FLAG_WME		(1 << 4)
 #define	BWN_MAC_FLAG_HWCRYPTO		(1 << 5)
 
-	struct resource_spec		*mac_intr_spec;
-#define	BWN_MSI_MESSAGES		1
-	struct resource			*mac_res_irq[BWN_MSI_MESSAGES];
-	void				*mac_intrhand[BWN_MSI_MESSAGES];
-	int				mac_msi;
+	struct resource			*mac_res_irq;
+	int				 mac_rid_irq;
+	void				*mac_intrhand;
 
 	struct bwn_noise		mac_noise;
 	struct bwn_phy			mac_phy;
@@ -964,6 +956,7 @@ struct bwn_mac {
 
 	struct bwn_fw			mac_fw;
 
+	int				mac_dmatype;
 	union {
 		struct bwn_dma		dma;
 		struct bwn_pio		pio;
@@ -1009,14 +1002,31 @@ struct bwn_vap {
 #define	BWN_VAP(vap)			((struct bwn_vap *)(vap))
 #define	BWN_VAP_CONST(vap)		((const struct mwl_vap *)(vap))
 
+enum bwn_quirk {
+	/**
+	 * The ucode PCI slowclock workaround is required on this device.
+	 * @see BWN_HF_PCI_SLOWCLOCK_WORKAROUND.
+	 */
+	BWN_QUIRK_UCODE_SLOWCLOCK_WAR	= (1<<0),
+
+	/**
+	 * DMA is unsupported on this device; PIO should be used instead.
+	 */
+	BWN_QUIRK_NODMA			= (1<<1),
+};
+
 struct bwn_softc {
 	device_t			sc_dev;
-	const struct bwn_bus_ops	*sc_bus_ops;
-#if !BWN_USE_SIBA
-	void				*sc_bus_ctx;
-	struct bhnd_resource		*sc_mem_res;
-	int				 sc_mem_rid;
-#endif /* !BWN_USE_SIBA */
+	struct bhnd_board_info		sc_board_info;
+	struct bhnd_chipid		sc_cid;
+	uint32_t			sc_quirks;	/**< @see bwn_quirk */
+	struct resource			*sc_mem_res;
+	int				sc_mem_rid;
+
+	device_t			sc_chipc;	/**< ChipCommon device */
+	device_t			sc_gpio;	/**< GPIO device */
+	device_t			sc_pmu;		/**< PMU device, or NULL if unsupported */
+
 	struct mtx			sc_mtx;
 	struct ieee80211com		sc_ic;
 	struct mbufq			sc_snd;
@@ -1059,6 +1069,9 @@ struct bwn_softc {
 	int				sc_led_idle;
 	int				sc_led_blink;
 
+	uint8_t				sc_ant2g;	/**< available 2GHz antennas */
+	uint8_t				sc_ant5g;	/**< available 5GHz antennas */
+
 	struct bwn_tx_radiotap_header	sc_tx_th;
 	struct bwn_rx_radiotap_header	sc_rx_th;
 };
diff --git a/sys/dev/siba/siba_bwn.c b/sys/dev/siba/siba_bwn.c
deleted file mode 100644
index cb70283d8e02..000000000000
--- a/sys/dev/siba/siba_bwn.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification.
- * 2. Redistributions in binary form must reproduce at minimum a disclaimer
- *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
- *    redistribution must be conditioned upon including a substantially
- *    similar Disclaimer requirement for further binary redistribution.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
- * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGES.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * Sonics Silicon Backplane front-end for bwn(4).
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/errno.h>
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <sys/bus.h>
-#include <sys/rman.h>
-#include <sys/socket.h>
-
-#include <net/if.h>
-#include <net/if_media.h>
-#include <net/if_arp.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-
-#include <dev/siba/siba_ids.h>
-#include <dev/siba/sibareg.h>
-#include <dev/siba/sibavar.h>
-
-/*
- * PCI glue.
- */
-
-struct siba_bwn_softc {
-	/* Child driver using MSI. */
-	device_t			ssc_msi_child;
-	struct siba_softc		ssc_siba;
-};
-
-#define	BS_BAR				0x10
-#define	PCI_VENDOR_BROADCOM		0x14e4
-#define	N(a)				(sizeof(a) / sizeof(a[0]))
-
-static const struct siba_dev {
-	uint16_t	vid;
-	uint16_t	did;
-	const char	*desc;
-} siba_devices[] = {
-	{ PCI_VENDOR_BROADCOM, 0x4301, "Broadcom BCM4301 802.11b Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4306, "Unknown" },
-	{ PCI_VENDOR_BROADCOM, 0x4307, "Broadcom BCM4307 802.11b Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4311, "Broadcom BCM4311 802.11b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4312,
-	  "Broadcom BCM4312 802.11a/b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4315, "Broadcom BCM4312 802.11b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4318, "Broadcom BCM4318 802.11b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4319,
-	  "Broadcom BCM4318 802.11a/b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4320, "Broadcom BCM4306 802.11b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4321, "Broadcom BCM4306 802.11a Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4324,
-	  "Broadcom BCM4309 802.11a/b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4325, "Broadcom BCM4306 802.11b/g Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4328, "Broadcom BCM4321 802.11a/b/g/n Wireless" },
-	{ PCI_VENDOR_BROADCOM, 0x4329, "Unknown" },
-	{ PCI_VENDOR_BROADCOM, 0x432b, "Broadcom BCM4322 802.11a/b/g/n Wireless" }
-};
-
-int		siba_core_attach(struct siba_softc *);
-int		siba_core_detach(struct siba_softc *);
-int		siba_core_suspend(struct siba_softc *);
-int		siba_core_resume(struct siba_softc *);
-
-static int
-siba_bwn_probe(device_t dev)
-{
-	int i;
-	uint16_t did, vid;
-
-	did = pci_get_device(dev);
-	vid = pci_get_vendor(dev);
-
-	for (i = 0; i < N(siba_devices); i++) {
-		if (siba_devices[i].did == did && siba_devices[i].vid == vid) {
-			device_set_desc(dev, siba_devices[i].desc);
-			return (BUS_PROBE_DEFAULT);
-		}
-	}
-	return (ENXIO);
-}
-
-static int
-siba_bwn_attach(device_t dev)
-{
-	struct siba_bwn_softc *ssc = device_get_softc(dev);
-	struct siba_softc *siba = &ssc->ssc_siba;
-
-	siba->siba_dev = dev;
-	siba->siba_type = SIBA_TYPE_PCI;
-
-	/*
-	 * Enable bus mastering.
-	 */
-	pci_enable_busmaster(dev);
-
-	/* 
-	 * Setup memory-mapping of PCI registers.
-	 */
-	siba->siba_mem_rid = SIBA_PCIR_BAR;
-	siba->siba_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
-		&siba->siba_mem_rid, RF_ACTIVE);
-	if (siba->siba_mem_res == NULL) {
-		device_printf(dev, "cannot map register space\n");
-		return (ENXIO);
-	}
-	siba->siba_mem_bt = rman_get_bustag(siba->siba_mem_res);
-	siba->siba_mem_bh = rman_get_bushandle(siba->siba_mem_res);
-
-	/* Get more PCI information */
-	siba->siba_pci_did = pci_get_device(dev);
-	siba->siba_pci_vid = pci_get_vendor(dev);
-	siba->siba_pci_subvid = pci_get_subvendor(dev);
-	siba->siba_pci_subdid = pci_get_subdevice(dev);
-	siba->siba_pci_revid = pci_get_revid(dev);
-
-	return (siba_core_attach(siba));
-}
-
-static int
-siba_bwn_detach(device_t dev)
-{
-	struct siba_bwn_softc *ssc = device_get_softc(dev);
-	struct siba_softc *siba = &ssc->ssc_siba;
-
-	/* check if device was removed */
-	siba->siba_invalid = !bus_child_present(dev);
-
-	pci_disable_busmaster(dev);
-	bus_generic_detach(dev);
-	siba_core_detach(siba);
-
-	bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, siba->siba_mem_res);
-
-	return (0);
-}
-
-static int
-siba_bwn_suspend(device_t dev)
-{
-	struct siba_bwn_softc *ssc = device_get_softc(dev);
-	struct siba_softc *siba = &ssc->ssc_siba;
-	int error;
-
-	error = bus_generic_suspend(dev);
-
-	if (error != 0)
-		return (error);
-
-	return (siba_core_suspend(siba));
-}
-
-static int
-siba_bwn_resume(device_t dev)
-{
-	struct siba_bwn_softc *ssc = device_get_softc(dev);
-	struct siba_softc *siba = &ssc->ssc_siba;
-	int error;
-
-	error = siba_core_resume(siba);
-	if (error != 0)
-		return (error);
-
-	bus_generic_resume(dev);
-
-	return (0);
-}
-
-/* proxying to the parent */
-static struct resource *
-siba_bwn_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
-{
-
-	return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
-	    type, rid, start, end, count, flags));
-}
-
-/* proxying to the parent */
-static int
-siba_bwn_release_resource(device_t dev, device_t child, int type,
-    int rid, struct resource *r)
-{
-
-	return (BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, type,
-	    rid, r));
-}
-
-/* proxying to the parent */
-static int
-siba_bwn_setup_intr(device_t dev, device_t child, struct resource *irq,
-    int flags, driver_filter_t *filter, driver_intr_t *intr, void *arg,
-    void **cookiep)
-{
-
-	return (BUS_SETUP_INTR(device_get_parent(dev), dev, irq, flags,
-	    filter, intr, arg, cookiep));
-}
-
-/* proxying to the parent */
-static int
-siba_bwn_teardown_intr(device_t dev, device_t child, struct resource *irq,
-    void *cookie)
-{
-
-	return (BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie));
-}
-
-static int
-siba_bwn_find_cap(device_t dev, device_t child, int capability,
-    int *capreg)
-{
-
-	return (pci_find_cap(dev, capability, capreg));
-}
-
-static int
-siba_bwn_find_extcap(device_t dev, device_t child, int capability,
-    int *capreg)
-{
-
-	return (pci_find_extcap(dev, capability, capreg));
-}
-
-static int
-siba_bwn_find_htcap(device_t dev, device_t child, int capability,
-    int *capreg)
-{
-
-	return (pci_find_htcap(dev, capability, capreg));
-}
-
-static int
-siba_bwn_alloc_msi(device_t dev, device_t child, int *count)
-{
-	struct siba_bwn_softc *ssc;
-	int error;
-
-	ssc = device_get_softc(dev);
-	if (ssc->ssc_msi_child != NULL)
-		return (EBUSY);
-	error = pci_alloc_msi(dev, count);
-	if (error == 0)
-		ssc->ssc_msi_child = child;
-	return (error);
-}
-
-static int
-siba_bwn_release_msi(device_t dev, device_t child)
-{
-	struct siba_bwn_softc *ssc;
-	int error;
-
-	ssc = device_get_softc(dev);
-	if (ssc->ssc_msi_child != child)
-		return (ENXIO);
-	error = pci_release_msi(dev);
-	if (error == 0)
-		ssc->ssc_msi_child = NULL;
-	return (error);
-}
-
-static int
-siba_bwn_msi_count(device_t dev, device_t child)
-{
-
-	return (pci_msi_count(dev));
-}
-
-static int
-siba_bwn_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
-{
-	struct siba_dev_softc *sd;
-	struct siba_softc *siba;
-
-	sd = device_get_ivars(child);
-	siba = sd->sd_bus;
-
-	switch (which) {
-	case SIBA_IVAR_VENDOR:
-		*result = sd->sd_id.sd_vendor;
-		break;
-	case SIBA_IVAR_DEVICE:
-		*result = sd->sd_id.sd_device;
-		break;
-	case SIBA_IVAR_REVID:
-		*result = sd->sd_id.sd_rev;
-		break;
-	case SIBA_IVAR_PCI_VENDOR:
-		*result = siba->siba_pci_vid;
-		break;
-	case SIBA_IVAR_PCI_DEVICE:
-		*result = siba->siba_pci_did;
-		break;
-	case SIBA_IVAR_PCI_SUBVENDOR:
-		*result = siba->siba_pci_subvid;
-		break;
-	case SIBA_IVAR_PCI_SUBDEVICE:
-		*result = siba->siba_pci_subdid;
-		break;
-	case SIBA_IVAR_PCI_REVID:
-		*result = siba->siba_pci_revid;
-		break;
-	case SIBA_IVAR_CHIPID:
-		*result = siba->siba_chipid;
-		break;
-	case SIBA_IVAR_CHIPREV:
-		*result = siba->siba_chiprev;
-		break;
-	case SIBA_IVAR_CHIPPKG:
-		*result = siba->siba_chippkg;
-		break;
-	case SIBA_IVAR_TYPE:
-		*result = siba->siba_type;
-		break;
-	case SIBA_IVAR_CC_PMUFREQ:
-		*result = siba->siba_cc.scc_pmu.freq;
-		break;
-	case SIBA_IVAR_CC_CAPS:
-		*result = siba->siba_cc.scc_caps;
-		break;
-	case SIBA_IVAR_CC_POWERDELAY:
-		*result = siba->siba_cc.scc_powerup_delay;
-		break;
-	case SIBA_IVAR_PCICORE_REVID:
-		*result = siba->siba_pci.spc_dev->sd_id.sd_rev;
-		break;
-	default:
-		return (ENOENT);
-	}
-
-	return (0);
-}
-
-static device_method_t siba_bwn_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		siba_bwn_probe),
-	DEVMETHOD(device_attach,	siba_bwn_attach),
-	DEVMETHOD(device_detach,	siba_bwn_detach),
-	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	DEVMETHOD(device_suspend,	siba_bwn_suspend),
-	DEVMETHOD(device_resume,	siba_bwn_resume),
-
-	/* Bus interface */
-	DEVMETHOD(bus_alloc_resource,   siba_bwn_alloc_resource),
-	DEVMETHOD(bus_release_resource, siba_bwn_release_resource),
-	DEVMETHOD(bus_read_ivar,	siba_bwn_read_ivar),
-	DEVMETHOD(bus_setup_intr,       siba_bwn_setup_intr),
-	DEVMETHOD(bus_teardown_intr,    siba_bwn_teardown_intr),
-
-	/* PCI interface */
-	DEVMETHOD(pci_find_cap,		siba_bwn_find_cap),
-	DEVMETHOD(pci_find_extcap,	siba_bwn_find_extcap),
-	DEVMETHOD(pci_find_htcap,	siba_bwn_find_htcap),
-	DEVMETHOD(pci_alloc_msi,	siba_bwn_alloc_msi),
-	DEVMETHOD(pci_release_msi,	siba_bwn_release_msi),
-	DEVMETHOD(pci_msi_count,	siba_bwn_msi_count),
-
-	DEVMETHOD_END
-};
-static driver_t siba_bwn_driver = {
-	"siba_bwn",
-	siba_bwn_methods,
-	sizeof(struct siba_bwn_softc)
-};
-static devclass_t siba_bwn_devclass;
-DRIVER_MODULE(siba_bwn, pci, siba_bwn_driver, siba_bwn_devclass, 0, 0);
-MODULE_VERSION(siba_bwn, 1);
diff --git a/sys/dev/siba/siba_core.c b/sys/dev/siba/siba_core.c
deleted file mode 100644
index 6bfc4f315894..000000000000
--- a/sys/dev/siba/siba_core.c
+++ /dev/null
@@ -1,3036 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification.
- * 2. Redistributions in binary form must reproduce at minimum a disclaimer
- *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
- *    redistribution must be conditioned upon including a substantially
- *    similar Disclaimer requirement for further binary redistribution.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
- * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGES.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * the Sonics Silicon Backplane driver.
- */
-
-#include "opt_siba.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/kernel.h>
-#include <sys/endian.h>
-#include <sys/errno.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <sys/bus.h>
-#include <sys/rman.h>
-#include <sys/socket.h>
-
-#include <net/if.h>
-#include <net/if_media.h>
-#include <net/if_arp.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-
-#include <dev/siba/siba_ids.h>
-#include <dev/siba/sibareg.h>
-#include <dev/siba/sibavar.h>
-
-enum {
-	SIBA_DEBUG_SCAN		= 0x00000001,	/* scan */
-	SIBA_DEBUG_PMU		= 0x00000002,	/* PMU */
-	SIBA_DEBUG_PLL		= 0x00000004,	/* PLL */
-	SIBA_DEBUG_SWITCHCORE	= 0x00000008,	/* switching core */
-	SIBA_DEBUG_SPROM	= 0x00000010,	/* SPROM */
-	SIBA_DEBUG_CORE		= 0x00000020,	/* handling cores */
-	SIBA_DEBUG_DMA		= 0x00000040,	/* DMA bits */
-	SIBA_DEBUG_ANY		= 0xffffffff
-};
-
-#ifdef SIBA_DEBUG
-#define DPRINTF(siba, m, ...) do {				\
-	if (siba->siba_debug & (m))				\
-		device_printf(siba->siba_dev, __VA_ARGS__);	\
-} while (0)
-#else
-#define DPRINTF(siba, m, ...) do { (void) siba; } while (0)
-#endif
-
-#define	N(a)			(sizeof(a) / sizeof(a[0]))
-
-static void	siba_pci_gpio(struct siba_softc *, uint32_t, int);
-static void	siba_scan(struct siba_softc *);
-static int	siba_switchcore(struct siba_softc *, uint8_t);
-static int	siba_pci_switchcore_sub(struct siba_softc *, uint8_t);
-static uint32_t	siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t);
-static uint16_t	siba_dev2chipid(struct siba_softc *);
-static uint16_t	siba_pci_read_2(struct siba_dev_softc *, uint16_t);
-static uint32_t	siba_pci_read_4(struct siba_dev_softc *, uint16_t);
-static void	siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
-static void	siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
-static void	siba_cc_clock(struct siba_cc *,
-		    enum siba_clock);
-static void	siba_cc_pmu_init(struct siba_cc *);
-static void	siba_cc_power_init(struct siba_cc *);
-static void	siba_cc_powerup_delay(struct siba_cc *);
-static int	siba_cc_clockfreq(struct siba_cc *, int);
-static void	siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t);
-static void	siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t);
-static enum siba_clksrc siba_cc_clksrc(struct siba_cc *);
-static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t);
-static uint32_t	siba_cc_pll_read(struct siba_cc *, uint32_t);
-static void	siba_cc_pll_write(struct siba_cc *, uint32_t,
-		    uint32_t);
-static const struct siba_cc_pmu0_plltab *
-		siba_cc_pmu0_plltab_findentry(uint32_t);
-static int	siba_pci_sprom(struct siba_softc *, struct siba_sprom *);
-static int	siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t);
-static int	sprom_check_crc(const uint16_t *, size_t);
-static uint8_t	siba_crc8(uint8_t, uint8_t);
-static void	siba_sprom_r123(struct siba_sprom *, const uint16_t *);
-static void	siba_sprom_r45(struct siba_sprom *, const uint16_t *);
-static void	siba_sprom_r8(struct siba_sprom *, const uint16_t *);
-static int8_t	siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t,
-		    uint16_t);
-static uint32_t	siba_tmslow_reject_bitmask(struct siba_dev_softc *);
-static uint32_t	siba_pcicore_read_4(struct siba_pci *, uint16_t);
-static void	siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t);
-static uint32_t	siba_pcie_read(struct siba_pci *, uint32_t);
-static void	siba_pcie_write(struct siba_pci *, uint32_t, uint32_t);
-static void	siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t,
-		    uint16_t);
-static void	siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t,
-		    uint16_t);
-static void	siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t,
-		    uint16_t);
-static void	siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t,
-		    uint16_t);
-static void	siba_pci_write_multi_1(struct siba_dev_softc *, const void *,
-		    size_t, uint16_t);
-static void	siba_pci_write_multi_2(struct siba_dev_softc *, const void *,
-		    size_t, uint16_t);
-static void	siba_pci_write_multi_4(struct siba_dev_softc *, const void *,
-		    size_t, uint16_t);
-static const char *siba_core_name(uint16_t);
-static void	siba_pcicore_init(struct siba_pci *);
-static uint32_t	siba_read_4_sub(struct siba_dev_softc *, uint16_t);
-static void	siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t);
-static void	siba_powerup_sub(struct siba_softc *, int);
-static int	siba_powerdown_sub(struct siba_softc *);
-static int	siba_dev_isup_sub(struct siba_dev_softc *);
-static void	siba_dev_up_sub(struct siba_dev_softc *, uint32_t);
-static void	siba_dev_down_sub(struct siba_dev_softc *, uint32_t);
-int		siba_core_attach(struct siba_softc *);
-int		siba_core_detach(struct siba_softc *);
-int		siba_core_suspend(struct siba_softc *);
-int		siba_core_resume(struct siba_softc *);
-uint8_t		siba_getncores(device_t, uint16_t);
-
-static const struct siba_bus_ops siba_pci_ops = {
-	.read_2		= siba_pci_read_2,
-	.read_4		= siba_pci_read_4,
-	.write_2	= siba_pci_write_2,
-	.write_4	= siba_pci_write_4,
-	.read_multi_1	= siba_pci_read_multi_1,
-	.read_multi_2	= siba_pci_read_multi_2,
-	.read_multi_4	= siba_pci_read_multi_4,
-	.write_multi_1	= siba_pci_write_multi_1,
-	.write_multi_2	= siba_pci_write_multi_2,
-	.write_multi_4	= siba_pci_write_multi_4,
-};
-
-static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] =
-    SIBA_CC_PMU_4325_RES_UPDOWN;
-static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] =
-    SIBA_CC_PMU_4325_RES_DEPEND;
-static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] =
-    SIBA_CC_PMU_4328_RES_UPDOWN;
-static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] =
-    SIBA_CC_PMU_4328_RES_DEPEND;
-static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] =
-    SIBA_CC_PMU0_PLLTAB_ENTRY;
-static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] =
-    SIBA_CC_PMU1_PLLTAB_ENTRY;
-
-int
-siba_core_attach(struct siba_softc *siba)
-{
-	struct siba_cc *scc;
-	int error;
-
-	KASSERT(siba->siba_type == SIBA_TYPE_PCI,
-	    ("unsupported BUS type (%#x)", siba->siba_type));
-
-	siba->siba_ops = &siba_pci_ops;
-
-	siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
-	siba_scan(siba);
-
-	/* XXX init PCI or PCMCIA host devices */
-
-	siba_powerup_sub(siba, 0);
-
-	/* init ChipCommon */
-	scc = &siba->siba_cc;
-	if (scc->scc_dev != NULL) {
-		siba_cc_pmu_init(scc);
-		siba_cc_power_init(scc);
-		siba_cc_clock(scc, SIBA_CLOCK_FAST);
-		siba_cc_powerup_delay(scc);
-	}
-
-	error = siba_pci_sprom(siba, &siba->siba_sprom);
-	if (error) {
-		siba_powerdown_sub(siba);
-		return (error);
-	}
-
-	siba_pcicore_init(&siba->siba_pci);
-	siba_powerdown_sub(siba);
-
-	return (bus_generic_attach(siba->siba_dev));
-}
-
-int
-siba_core_detach(struct siba_softc *siba)
-{
-	/* detach & delete all children */
-	device_delete_children(siba->siba_dev);
-	return (0);
-}
-
-static void
-siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on)
-{
-	uint32_t in, out;
-	uint16_t status;
-
-	if (siba->siba_type != SIBA_TYPE_PCI)
-		return;
-
-	out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4);
-	if (on == 0) {
-		if (what & SIBA_GPIO_PLL)
-			out |= SIBA_GPIO_PLL;
-		if (what & SIBA_GPIO_CRYSTAL)
-			out &= ~SIBA_GPIO_CRYSTAL;
-		pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
-		pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN,
-		    pci_read_config(siba->siba_dev,
-			SIBA_GPIO_OUT_EN, 4) | what, 4);
-		return;
-	}
-
-	in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4);
-	if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) {
-		if (what & SIBA_GPIO_CRYSTAL) {
-			out |= SIBA_GPIO_CRYSTAL;
-			if (what & SIBA_GPIO_PLL)
-				out |= SIBA_GPIO_PLL;
-			pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
-			pci_write_config(siba->siba_dev,
-			    SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev,
-				SIBA_GPIO_OUT_EN, 4) | what, 4);
-			DELAY(1000);
-		}
-		if (what & SIBA_GPIO_PLL) {
-			out &= ~SIBA_GPIO_PLL;
-			pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
-			DELAY(5000);
-		}
-	}
-
-	status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2);
-	status &= ~PCIM_STATUS_STABORT;
-	pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2);
-}
-
-static void
-siba_scan(struct siba_softc *siba)
-{
-	struct siba_dev_softc *sd;
-	uint32_t idhi, tmp;
-	device_t child;
-	int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0,
-	    n_pci = 0;
-
-	KASSERT(siba->siba_type == SIBA_TYPE_PCI,
-	    ("unsupported BUS type (%#x)", siba->siba_type));
-
-	siba->siba_ndevs = 0;
-	error = siba_switchcore(siba, 0); /* need the first core */
-	if (error)
-		return;
-
-	idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH);
-	if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) {
-		tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID);
-		siba->siba_chipid = SIBA_CC_ID(tmp);
-		siba->siba_chiprev = SIBA_CC_REV(tmp);
-		siba->siba_chippkg = SIBA_CC_PKG(tmp);
-		if (SIBA_IDHIGH_REV(idhi) >= 4)
-			siba->siba_ndevs = SIBA_CC_NCORES(tmp);
-		siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0,
-		    SIBA_CC_CAPS);
-	} else {
-		if (siba->siba_type == SIBA_TYPE_PCI) {
-			siba->siba_chipid = siba_dev2chipid(siba);
-			siba->siba_chiprev = pci_read_config(siba->siba_dev,
-			    PCIR_REVID, 2);
-			siba->siba_chippkg = 0;
-		} else {
-			siba->siba_chipid = 0x4710;
-			siba->siba_chiprev = 0;
-			siba->siba_chippkg = 0;
-		}
-	}
-	if (siba->siba_ndevs == 0)
-		siba->siba_ndevs = siba_getncores(siba->siba_dev,
-		    siba->siba_chipid);
-	if (siba->siba_ndevs > SIBA_MAX_CORES) {
-		device_printf(siba->siba_dev,
-		    "too many siba cores (max %d %d)\n",
-		    SIBA_MAX_CORES, siba->siba_ndevs);
-		return;
-	}
-
-	/* looking basic information about each cores/devices */
-	for (i = 0; i < siba->siba_ndevs; i++) {
-		error = siba_switchcore(siba, i);
-		if (error)
-			return;
-		sd = &(siba->siba_devs[dev_i]);
-		idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH);
-		sd->sd_bus = siba;
-		sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi);
-		sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi);
-		sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi);
-		sd->sd_ops = siba->siba_ops;
-		sd->sd_coreidx = i;
-
-		DPRINTF(siba, SIBA_DEBUG_SCAN,
-		    "core %d (%s) found (cc %#x rev %#x vendor %#x)\n",
-		    i, siba_core_name(sd->sd_id.sd_device),
-		    sd->sd_id.sd_device, sd->sd_id.sd_rev,
-		    sd->sd_id.sd_vendor);
-
-		switch (sd->sd_id.sd_device) {
-		case SIBA_DEVID_CHIPCOMMON:
-			n_cc++;
-			if (n_cc > 1) {
-				device_printf(siba->siba_dev,
-				    "warn: multiple ChipCommon\n");
-				break;
-			}
-			siba->siba_cc.scc_dev = sd;
-			break;
-		case SIBA_DEVID_80211:
-			n_80211++;
-			if (n_80211 > 1) {
-				device_printf(siba->siba_dev,
-				    "warn: multiple 802.11 core\n");
-				continue;
-			}
-			break;
-		case SIBA_DEVID_PCI:
-		case SIBA_DEVID_PCIE:
-			n_pci++;
-			error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS,
-			    &base);
-			is_pcie = (error == 0) ? 1 : 0;
-
-			if (n_pci > 1) {
-				device_printf(siba->siba_dev,
-				    "warn: multiple PCI(E) cores\n");
-				break;
-			}
-			if (sd->sd_id.sd_device == SIBA_DEVID_PCI &&
-			    is_pcie == 1)
-				continue;
-			if (sd->sd_id.sd_device == SIBA_DEVID_PCIE &&
-			    is_pcie == 0)
-				continue;
-			siba->siba_pci.spc_dev = sd;
-			break;
-		case SIBA_DEVID_MODEM:
-		case SIBA_DEVID_PCMCIA:
-			break;
-		default:
-			device_printf(siba->siba_dev,
-			    "unsupported coreid (%s)\n",
-			    siba_core_name(sd->sd_id.sd_device));
-			break;
-		}
-		dev_i++;
-
-		child = device_add_child(siba->siba_dev, NULL, -1);
-		if (child == NULL) {
-			device_printf(siba->siba_dev, "child attach failed\n");
-			continue;
-		}
-
-		device_set_ivars(child, sd);
-	}
-	siba->siba_ndevs = dev_i;
-}
-
-static int
-siba_switchcore(struct siba_softc *siba, uint8_t idx)
-{
-
-	switch (siba->siba_type) {
-	case SIBA_TYPE_PCI:
-		return (siba_pci_switchcore_sub(siba, idx));
-	default:
-		KASSERT(0 == 1,
-		    ("%s: unsupported bustype %#x", __func__,
-		    siba->siba_type));
-	}
-	return (0);
-}
-
-static int
-siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx)
-{
-#define RETRY_MAX	50
-	int i;
-	uint32_t dir;
-
-	dir = SIBA_REGWIN(idx);
-
-	for (i = 0; i < RETRY_MAX; i++) {
-		pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4);
-		if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir)
-			return (0);
-		DELAY(10);
-	}
-	DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "%s: idx %d, failed\n", __func__, idx);
-	return (ENODEV);
-#undef RETRY_MAX
-}
-
-static int
-siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd)
-{
-	int error;
-
-	DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n",
-	    siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx);
-
-	error = siba_pci_switchcore_sub(siba, sd->sd_coreidx);
-	if (error == 0)
-		siba->siba_curdev = sd;
-
-	return (error);
-}
-
-static uint32_t
-siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx,
-    uint16_t offset)
-{
-
-	(void)coreidx;
-	KASSERT(siba->siba_type == SIBA_TYPE_PCI,
-	    ("unsupported BUS type (%#x)", siba->siba_type));
-
-	return (SIBA_READ_4(siba, offset));
-}
-
-static uint16_t
-siba_dev2chipid(struct siba_softc *siba)
-{
-	uint16_t chipid = 0;
-
-	switch (siba->siba_pci_did) {
-	case 0x4301:
-		chipid = 0x4301;
-		break;
-	case 0x4305:
-	case 0x4306:
-	case 0x4307:
-		chipid = 0x4307;
-		break;
-	case 0x4403:
-		chipid = 0x4402;
-		break;
-	case 0x4610:
-	case 0x4611:
-	case 0x4612:
-	case 0x4613:
-	case 0x4614:
-	case 0x4615:
-		chipid = 0x4610;
-		break;
-	case 0x4710:
-	case 0x4711:
-	case 0x4712:
-	case 0x4713:
-	case 0x4714:
-	case 0x4715:
-		chipid = 0x4710;
-		break;
-	case 0x4320:
-	case 0x4321:
-	case 0x4322:
-	case 0x4323:
-	case 0x4324:
-	case 0x4325:
-		chipid = 0x4309;
-		break;
-	case PCI_DEVICE_ID_BCM4401:
-	case PCI_DEVICE_ID_BCM4401B0:
-	case PCI_DEVICE_ID_BCM4401B1:
-		chipid = 0x4401;
-		break;
-	default:
-		device_printf(siba->siba_dev, "unknown PCI did (%d)\n",
-		    siba->siba_pci_did);
-	}
-
-	return (chipid);
-}
-
-/*
- * Earlier ChipCommon revisions have hardcoded number of cores
- * present dependent on the ChipCommon ID.
- */
-uint8_t
-siba_getncores(device_t dev, uint16_t chipid)
-{
-	switch (chipid) {
-	case 0x4401:
-	case 0x4402:
-		return (3);
-	case 0x4301:
-	case 0x4307:
-		return (5);
-	case 0x4306:
-		return (6);
-	case SIBA_CCID_SENTRY5:
-		return (7);
-	case 0x4310:
-		return (8);
-	case SIBA_CCID_BCM4710:
-	case 0x4610:
-	case SIBA_CCID_BCM4704:
-		return (9);
-	default:
-		device_printf(dev, "unknown the chipset ID %#x\n", chipid);
-	}
-
-	return (1);
-}
-
-static const char *
-siba_core_name(uint16_t coreid)
-{
-
-	switch (coreid) {
-	case SIBA_DEVID_CHIPCOMMON:
-		return ("ChipCommon");
-	case SIBA_DEVID_ILINE20:
-		return ("ILine 20");
-	case SIBA_DEVID_SDRAM:
-		return ("SDRAM");
-	case SIBA_DEVID_PCI:
-		return ("PCI");
-	case SIBA_DEVID_MIPS:
-		return ("MIPS");
-	case SIBA_DEVID_ETHERNET:
-		return ("Fast Ethernet");
-	case SIBA_DEVID_MODEM:
-		return ("Modem");
-	case SIBA_DEVID_USB11_HOSTDEV:
-		return ("USB 1.1 Hostdev");
-	case SIBA_DEVID_ADSL:
-		return ("ADSL");
-	case SIBA_DEVID_ILINE100:
-		return ("ILine 100");
-	case SIBA_DEVID_IPSEC:
-		return ("IPSEC");
-	case SIBA_DEVID_PCMCIA:
-		return ("PCMCIA");
-	case SIBA_DEVID_INTERNAL_MEM:
-		return ("Internal Memory");
-	case SIBA_DEVID_SDRAMDDR:
-		return ("MEMC SDRAM");
-	case SIBA_DEVID_EXTIF:
-		return ("EXTIF");
-	case SIBA_DEVID_80211:
-		return ("IEEE 802.11");
-	case SIBA_DEVID_MIPS_3302:
-		return ("MIPS 3302");
-	case SIBA_DEVID_USB11_HOST:
-		return ("USB 1.1 Host");
-	case SIBA_DEVID_USB11_DEV:
-		return ("USB 1.1 Device");
-	case SIBA_DEVID_USB20_HOST:
-		return ("USB 2.0 Host");
-	case SIBA_DEVID_USB20_DEV:
-		return ("USB 2.0 Device");
-	case SIBA_DEVID_SDIO_HOST:
-		return ("SDIO Host");
-	case SIBA_DEVID_ROBOSWITCH:
-		return ("Roboswitch");
-	case SIBA_DEVID_PARA_ATA:
-		return ("PATA");
-	case SIBA_DEVID_SATA_XORDMA:
-		return ("SATA XOR-DMA");
-	case SIBA_DEVID_ETHERNET_GBIT:
-		return ("GBit Ethernet");
-	case SIBA_DEVID_PCIE:
-		return ("PCI-Express");
-	case SIBA_DEVID_MIMO_PHY:
-		return ("MIMO PHY");
-	case SIBA_DEVID_SRAM_CTRLR:
-		return ("SRAM Controller");
-	case SIBA_DEVID_MINI_MACPHY:
-		return ("Mini MACPHY");
-	case SIBA_DEVID_ARM_1176:
-		return ("ARM 1176");
-	case SIBA_DEVID_ARM_7TDMI:
-		return ("ARM 7TDMI");
-	}
-	return ("unknown");
-}
-
-static uint16_t
-siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return (0xffff);
-
-	return (SIBA_READ_2(siba, offset));
-}
-
-static uint32_t
-siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return (0xffff);
-
-	return (SIBA_READ_4(siba, offset));
-}
-
-static void
-siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return;
-
-	SIBA_WRITE_2(siba, offset, value);
-}
-
-static void
-siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return;
-
-	SIBA_WRITE_4(siba, offset, value);
-}
-
-static void
-siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
-		memset(buffer, 0xff, count);
-		return;
-	}
-
-	SIBA_READ_MULTI_1(siba, offset, buffer, count);
-}
-
-static void
-siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
-		memset(buffer, 0xff, count);
-		return;
-	}
-
-	KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
-	SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1);
-}
-
-static void
-siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
-		memset(buffer, 0xff, count);
-		return;
-	}
-
-	KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
-	SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2);
-}
-
-static void
-siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer,
-    size_t count, uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return;
-
-	SIBA_WRITE_MULTI_1(siba, offset, buffer, count);
-}
-
-static void
-siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer,
-    size_t count, uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return;
-
-	KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
-	SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1);
-}
-
-static void
-siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
-    size_t count, uint16_t offset)
-{
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
-		return;
-
-	KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
-	SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2);
-}
-
-void
-siba_powerup(device_t dev, int dynamic)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	siba_powerup_sub(siba, dynamic);
-}
-
-static void
-siba_powerup_sub(struct siba_softc *siba, int dynamic)
-{
-
-	siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
-	siba_cc_clock(&siba->siba_cc,
-	    (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST);
-}
-
-static void
-siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
-{
-	struct siba_dev_softc *sd = scc->scc_dev;
-	struct siba_softc *siba;
-	uint32_t tmp;
-
-	if (sd == NULL)
-		return;
-	siba = sd->sd_bus;
-
-	/*
-	 * PMU controls clockmode; separate function is needed
-	 */
-	if (scc->scc_caps & SIBA_CC_CAPS_PMU)
-		return;
-
-	/*
-	 * chipcommon < r6 (no dynamic clock control)
-	 * chipcommon >= r10 (unknown)
-	 */
-	if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 ||
-	    (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
-		return;
-
-	switch (clock) {
-	case SIBA_CLOCK_DYNAMIC:
-		tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
-		    ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW |
-		    SIBA_CC_CLKSLOW_IPLL);
-		if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL)
-			tmp |= SIBA_CC_CLKSLOW_ENXTAL;
-		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
-		if (tmp & SIBA_CC_CLKSLOW_ENXTAL)
-			siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0);
-		break;
-	case SIBA_CLOCK_SLOW:
-		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
-		    SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
-		    SIBA_CC_CLKSLOW_FSLOW);
-		break;
-	case SIBA_CLOCK_FAST:
-		/* crystal on */
-		siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1);
-		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
-		    (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
-			SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW);
-		break;
-	default:
-		KASSERT(0 == 1,
-		    ("%s: unsupported clock %#x", __func__, clock));
-	}
-}
-
-uint16_t
-siba_read_2(device_t dev, uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	return (sd->sd_ops->read_2(sd, offset));
-}
-
-uint32_t
-siba_read_4(device_t dev, uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	return (siba_read_4_sub(sd, offset));
-}
-
-static uint32_t
-siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset)
-{
-
-	return (sd->sd_ops->read_4(sd, offset));
-}
-
-void
-siba_write_2(device_t dev, uint16_t offset, uint16_t value)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->write_2(sd, offset, value);
-}
-
-void
-siba_write_4(device_t dev, uint16_t offset, uint32_t value)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	return (siba_write_4_sub(sd, offset, value));
-}
-
-static void
-siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
-{
-
-	sd->sd_ops->write_4(sd, offset, value);
-}
-
-void
-siba_read_multi_1(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->read_multi_1(sd, buffer, count, offset);
-}
-
-void
-siba_read_multi_2(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->read_multi_2(sd, buffer, count, offset);
-}
-
-void
-siba_read_multi_4(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->read_multi_4(sd, buffer, count, offset);
-}
-
-void
-siba_write_multi_1(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->write_multi_1(sd, buffer, count, offset);
-}
-
-void
-siba_write_multi_2(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->write_multi_2(sd, buffer, count, offset);
-}
-
-void
-siba_write_multi_4(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	sd->sd_ops->write_multi_4(sd, buffer, count, offset);
-}
-
-static void
-siba_cc_pmu_init(struct siba_cc *scc)
-{
-	const struct siba_cc_pmu_res_updown *updown = NULL;
-	const struct siba_cc_pmu_res_depend *depend = NULL;
-	struct siba_dev_softc *sd = scc->scc_dev;
-	struct siba_softc *siba = sd->sd_bus;
-	uint32_t min = 0, max = 0, pmucap;
-	unsigned int i, updown_size, depend_size;
-
-	if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0)
-		return;
-
-	pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS);
-	scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV);
-
-	DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n",
-	    scc->scc_pmu.rev, pmucap);
-
-#if 0
-	if (scc->scc_pmu.rev >= 1) {
-		if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325)
-			SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL,
-			    ~SIBA_CC_PMUCTL_NOILP);
-		else
-			SIBA_CC_SET32(scc, SIBA_CC_PMUCTL,
-			    SIBA_CC_PMUCTL_NOILP);
-	}
-#endif
-	if (scc->scc_pmu.rev == 1) {
-		SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, ~SIBA_CC_PMUCTL_NOILP);
-	} else {
-		SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_NOILP);
-	}
-
-	/* initialize PLL & PMU resources */
-	switch (siba->siba_chipid) {
-	case 0x4312:
-		siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
-		/* use the default: min = 0xcbb max = 0x7ffff */
-		break;
-	case 0x4322:
-		if (scc->scc_pmu.rev == 2) {
-			DPRINTF(siba, SIBA_DEBUG_PMU, "%s: chipid 0x4322; PLLing\n",
-			    __func__);
-			SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, 0x0000000a);
-			SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, 0x380005c0);
-		}
-		/* use the default: min = 0xcbb max = 0x7ffff */
-		break;
-	case 43222:
-		break;
-	case 0x4325:
-		siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
-
-		updown = siba_cc_pmu_4325_updown;
-		updown_size = N(siba_cc_pmu_4325_updown);
-		depend = siba_cc_pmu_4325_depend;
-		depend_size = N(siba_cc_pmu_4325_depend);
-
-		min = (1 << SIBA_CC_PMU_4325_BURST) |
-		    (1 << SIBA_CC_PMU_4325_LN);
-		if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) &
-		    SIBA_CC_CHST_4325_PMUTOP_2B)
-			min |= (1 << SIBA_CC_PMU_4325_CLBURST);
-		max = 0xfffff;
-		break;
-	case 0x4328:
-		siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
-
-		updown = siba_cc_pmu_4328_updown;
-		updown_size = N(siba_cc_pmu_4328_updown);
-		depend = siba_cc_pmu_4328_depend;
-		depend_size = N(siba_cc_pmu_4328_depend);
-
-		min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) |
-			  (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) |
-			  (1 << SIBA_CC_PMU_4328_CRYSTAL_EN);
-
-		max = 0xfffff;
-		break;
-	case 0x5354:
-		siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
-
-		max = 0xfffff;
-		break;
-	default:
-		device_printf(siba->siba_dev,
-		    "unknown chipid %#x for PLL & PMU init\n",
-		    siba->siba_chipid);
-	}
-
-	if (updown) {
-		for (i = 0; i < updown_size; i++) {
-			SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
-			    updown[i].res);
-			SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM,
-			    updown[i].updown);
-		}
-	}
-	if (depend) {
-		for (i = 0; i < depend_size; i++) {
-			SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
-			    depend[i].res);
-			switch (depend[i].task) {
-			case SIBA_CC_PMU_DEP_SET:
-				SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK,
-				    depend[i].depend);
-				break;
-			case SIBA_CC_PMU_DEP_ADD:
-				SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK,
-				    depend[i].depend);
-				break;
-			case SIBA_CC_PMU_DEP_REMOVE:
-				SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK,
-				    ~(depend[i].depend));
-				break;
-			default:
-				KASSERT(0 == 1,
-				    ("%s:%d: assertion failed",
-					__func__, __LINE__));
-			}
-		}
-	}
-
-	if (min)
-		SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min);
-	if (max)
-		SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max);
-}
-
-static void
-siba_cc_power_init(struct siba_cc *scc)
-{
-	struct siba_softc *siba = scc->scc_dev->sd_bus;
-	int maxfreq;
-
-	if (siba->siba_chipid == 0x4321) {
-		if (siba->siba_chiprev == 0)
-			SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4);
-		else if (siba->siba_chiprev == 1)
-			SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4);
-	}
-
-	if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
-		return;
-
-	if (scc->scc_dev->sd_id.sd_rev >= 10)
-		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL,
-		    (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) &
-		    0xffff) | 0x40000);
-	else {
-		maxfreq = siba_cc_clockfreq(scc, 1);
-		SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY,
-		    (maxfreq * 150 + 999999) / 1000000);
-		SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY,
-		    (maxfreq * 15 + 999999) / 1000000);
-	}
-}
-
-static void
-siba_cc_powerup_delay(struct siba_cc *scc)
-{
-	struct siba_softc *siba = scc->scc_dev->sd_bus;
-	int min;
-
-	if (siba->siba_type != SIBA_TYPE_PCI)
-		return;
-
-	if (scc->scc_caps & SIBA_CC_CAPS_PMU) {
-		if ((siba->siba_chipid == 0x4312) ||
-		    (siba->siba_chipid == 0x4322) ||
-		    (siba->siba_chipid == 0x4328)) {
-			scc->scc_powerup_delay = 7000;
-		} else {
-			/* 0x4325 is marked as TODO */
-			scc->scc_powerup_delay = 15000;
-		}
-		return;
-	}
-
-	if (!(scc->scc_caps & SIBA_CC_CAPS_PWCTL))
-		return;
-
-	min = siba_cc_clockfreq(scc, 0);
-	scc->scc_powerup_delay =
-	    howmany((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000,
-	    min);
-}
-
-static int
-siba_cc_clockfreq(struct siba_cc *scc, int max)
-{
-	enum siba_clksrc src;
-	int div = 1, limit = 0;
-
-	src = siba_cc_clksrc(scc);
-	if (scc->scc_dev->sd_id.sd_rev < 6) {
-		div = (src == SIBA_CC_CLKSRC_PCI) ? 64 :
-		    (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1;
-		KASSERT(div != 1,
-		    ("%s: unknown clock %d", __func__, src));
-	} else if (scc->scc_dev->sd_id.sd_rev < 10) {
-		switch (src) {
-		case SIBA_CC_CLKSRC_CRYSTAL:
-		case SIBA_CC_CLKSRC_PCI:
-			div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) +
-			    1) * 4;
-			break;
-		case SIBA_CC_CLKSRC_LOWPW:
-			break;
-		}
-	} else
-		div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4;
-
-	switch (src) {
-	case SIBA_CC_CLKSRC_CRYSTAL:
-		limit = (max) ? 20200000 : 19800000;
-		break;
-	case SIBA_CC_CLKSRC_LOWPW:
-		limit = (max) ? 43000 : 25000;
-		break;
-	case SIBA_CC_CLKSRC_PCI:
-		limit = (max) ? 34000000 : 25000000;
-		break;
-	}
-
-	return (limit / div);
-}
-
-static void
-siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq)
-{
-	struct siba_dev_softc *sd = scc->scc_dev;
-	struct siba_softc *siba = sd->sd_bus;
-	const struct siba_cc_pmu1_plltab *e = NULL;
-	uint32_t bufsth = 0, pll, pmu;
-	unsigned int i;
-
-	KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__));
-	if (siba->siba_chipid == 0x4312) {
-		scc->scc_pmu.freq = 20000;
-		return;
-	}
-
-	e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ);
-	KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__));
-	scc->scc_pmu.freq = e->freq;
-
-	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
-	if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf)
-		return;
-
-	DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
-	    (e->freq / 1000), (e->freq % 1000));
-
-	/* turn PLL off */
-	switch (siba->siba_chipid) {
-	case 0x4325:
-		bufsth = 0x222222;
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
-		    ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
-		      (1 << SIBA_CC_PMU_4325_HT)));
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
-		    ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
-		      (1 << SIBA_CC_PMU_4325_HT)));
-		break;
-	default:
-		KASSERT(0 == 1,
-		    ("%s:%d: assertion failed", __func__, __LINE__));
-	}
-	for (i = 0; i < 1500; i++) {
-		if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) &
-		      SIBA_CC_CLKCTLSTATUS_HT))
-			break;
-		DELAY(10);
-	}
-	if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT)
-		device_printf(siba->siba_dev, "failed to turn PLL off!\n");
-
-	pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
-	pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV);
-	pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV;
-	pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV;
-	siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
-
-	pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
-	pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE);
-	pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT;
-	pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE;
-	siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll);
-
-	pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3);
-	pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC;
-	pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC;
-	siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll);
-
-	if (bufsth) {
-		pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5);
-		pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV;
-		pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV;
-		siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll);
-	}
-
-	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
-	pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF);
-	pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) &
-	    SIBA_CC_PMUCTL_ILP;
-	pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
-	SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
-}
-
-static void
-siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
-{
-	struct siba_dev_softc *sd = scc->scc_dev;
-	struct siba_softc *siba = sd->sd_bus;
-	const struct siba_cc_pmu0_plltab *e = NULL;
-	uint32_t pmu, tmp, pll;
-	unsigned int i;
-
-	if ((siba->siba_chipid == 0x5354) && !xtalfreq)
-		xtalfreq = 25000;
-	if (xtalfreq)
-		e = siba_cc_pmu0_plltab_findentry(xtalfreq);
-	if (!e)
-		e = siba_cc_pmu0_plltab_findentry(
-		    SIBA_CC_PMU0_DEFAULT_XTALFREQ);
-	KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__));
-	xtalfreq = e->freq;
-	scc->scc_pmu.freq = e->freq;
-
-	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
-	if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
-		return;
-
-	DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
-	    (xtalfreq / 1000), (xtalfreq % 1000));
-
-	KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354,
-	    ("%s:%d: fail", __func__, __LINE__));
-
-	switch (siba->siba_chipid) {
-	case 0x4328:
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
-		    ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
-		    ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
-		break;
-	case 0x5354:
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
-		    ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
-		    ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
-		break;
-	}
-	for (i = 1500; i; i--) {
-		tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
-		if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT))
-			break;
-		DELAY(10);
-	}
-	tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
-	if (tmp & SIBA_CC_CLKCTLSTATUS_HT)
-		device_printf(siba->siba_dev, "failed to turn PLL off!\n");
-
-	/* set PDIV */
-	pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0);
-	if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ)
-		pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK;
-	else
-		pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK;
-	siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll);
-
-	/* set WILD */
-	pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1);
-	pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK |
-	    SIBA_CC_PMU0_PLL1_FMSK);
-	pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK;
-	pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK;
-	if (e->wb_frac == 0)
-		pll |= SIBA_CC_PMU0_PLL1_STOPMOD;
-	siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll);
-
-	/* set WILD */
-	pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2);
-	pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI;
-	pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI;
-	siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll);
-
-	/* set freq and divisor. */
-	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
-	pmu &= ~SIBA_CC_PMUCTL_ILP;
-	pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP;
-	pmu &= ~SIBA_CC_PMUCTL_XF;
-	pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
-	SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
-}
-
-static enum siba_clksrc
-siba_cc_clksrc(struct siba_cc *scc)
-{
-	struct siba_dev_softc *sd = scc->scc_dev;
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (sd->sd_id.sd_rev < 6) {
-		if (siba->siba_type == SIBA_TYPE_PCI) {
-			if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) &
-			    0x10)
-				return (SIBA_CC_CLKSRC_PCI);
-			return (SIBA_CC_CLKSRC_CRYSTAL);
-		}
-		if (siba->siba_type == SIBA_TYPE_SSB ||
-		    siba->siba_type == SIBA_TYPE_PCMCIA)
-			return (SIBA_CC_CLKSRC_CRYSTAL);
-	}
-	if (sd->sd_id.sd_rev < 10) {
-		switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) {
-		case 0:
-			return (SIBA_CC_CLKSRC_LOWPW);
-		case 1:
-			return (SIBA_CC_CLKSRC_CRYSTAL);
-		case 2:
-			return (SIBA_CC_CLKSRC_PCI);
-		default:
-			break;
-		}
-	}
-
-	return (SIBA_CC_CLKSRC_CRYSTAL);
-}
-
-static const struct siba_cc_pmu1_plltab *
-siba_cc_pmu1_plltab_find(uint32_t crystalfreq)
-{
-	const struct siba_cc_pmu1_plltab *e;
-	unsigned int i;
-
-	for (i = 0; i < N(siba_cc_pmu1_plltab); i++) {
-		e = &siba_cc_pmu1_plltab[i];
-		if (crystalfreq == e->freq)
-			return (e);
-	}
-
-	return (NULL);
-}
-
-static uint32_t
-siba_cc_pll_read(struct siba_cc *scc, uint32_t offset)
-{
-
-	SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
-	return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA));
-}
-
-static void
-siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value)
-{
-
-	SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
-	SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value);
-}
-
-static const struct siba_cc_pmu0_plltab *
-siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq)
-{
-	const struct siba_cc_pmu0_plltab *e;
-	unsigned int i;
-
-	for (i = 0; i < N(siba_cc_pmu0_plltab); i++) {
-		e = &siba_cc_pmu0_plltab[i];
-		if (e->freq == crystalfreq)
-			return (e);
-	}
-
-	return (NULL);
-}
-
-static int
-siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom)
-{
-	int error = ENOMEM;
-	uint16_t *buf;
-
-	buf = malloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t),
-	    M_DEVBUF, M_NOWAIT | M_ZERO);
-	if (buf == NULL)
-		return (ENOMEM);
-	siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123);
-	error = sprom_check_crc(buf, siba->siba_spromsize);
-	if (error) {
-		free(buf, M_DEVBUF);
-		buf = malloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t),
-		    M_DEVBUF, M_NOWAIT | M_ZERO);
-		if (buf == NULL)
-			return (ENOMEM);
-		siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4);
-		error = sprom_check_crc(buf, siba->siba_spromsize);
-		if (error)
-			device_printf(siba->siba_dev, "warn: bad SPROM CRC\n");
-	}
-
-	bzero(sprom, sizeof(*sprom));
-
-	sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF;
-	DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n",
-	    sprom->rev);
-	memset(sprom->mac_eth, 0xff, 6);
-	memset(sprom->mac_80211a, 0xff, 6);
-	if ((siba->siba_chipid & 0xff00) == 0x4400) {
-		sprom->rev = 1;
-		siba_sprom_r123(sprom, buf);
-	} else if (siba->siba_chipid == 0x4321) {
-		sprom->rev = 4;
-		siba_sprom_r45(sprom, buf);
-	} else {
-		switch (sprom->rev) {
-		case 1:
-		case 2:
-		case 3:
-			siba_sprom_r123(sprom, buf);
-			break;
-		case 4:
-		case 5:
-			siba_sprom_r45(sprom, buf);
-			break;
-		case 8:
-			siba_sprom_r8(sprom, buf);
-			break;
-		default:
-			device_printf(siba->siba_dev,
-			    "unknown SPROM revision %d.\n", sprom->rev);
-			siba_sprom_r123(sprom, buf);
-		}
-	}
-
-	if (sprom->bf_lo == 0xffff)
-		sprom->bf_lo = 0;
-	if (sprom->bf_hi == 0xffff)
-		sprom->bf_hi = 0;
-
-	free(buf, M_DEVBUF);
-	return (error);
-}
-
-static int
-siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2));
-
-	siba->siba_spromsize = len;
-	return (0);
-}
-
-static int
-sprom_check_crc(const uint16_t *sprom, size_t size)
-{
-	int word;
-	uint8_t crc0, crc1 = 0xff;
-
-	crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8;
-	for (word = 0; word < size - 1; word++) {
-		crc1 = siba_crc8(crc1, sprom[word] & 0x00ff);
-		crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8);
-	}
-	crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff);
-	crc1 ^= 0xff;
-
-	return ((crc0 != crc1) ? EPROTO : 0);
-}
-
-static uint8_t
-siba_crc8(uint8_t crc, uint8_t data)
-{
-	static const uint8_t ct[] = {
-		0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b,
-		0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21,
-		0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff,
-		0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5,
-		0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14,
-		0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e,
-		0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80,
-		0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca,
-		0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95,
-		0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf,
-		0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01,
-		0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b,
-		0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea,
-		0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0,
-		0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e,
-		0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34,
-		0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0,
-		0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a,
-		0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54,
-		0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e,
-		0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf,
-		0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5,
-		0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b,
-		0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61,
-		0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e,
-		0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74,
-		0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa,
-		0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0,
-		0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41,
-		0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b,
-		0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5,
-		0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f,
-	};
-	return (ct[crc ^ data]);
-}
-
-#define	SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
-#define SIBA_OFFSET(offset)	\
-	(((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t))
-#define	SIBA_SHIFTOUT_SUB(__x, __mask)					\
-	(((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask))
-#define	SIBA_SHIFTOUT(_var, _offset, _mask)				\
-	out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask))
-#define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift)			\
-	out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 |	\
-	    in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift))
-
-static void
-siba_sprom_r123(struct siba_sprom *out, const uint16_t *in)
-{
-	int i;
-	uint16_t v;
-	int8_t gain;
-	uint16_t loc[3];
-
-	if (out->rev == 3)
-		loc[0] = SIBA_SPROM3_MAC_80211BG;
-	else {
-		loc[0] = SIBA_SPROM1_MAC_80211BG;
-		loc[1] = SIBA_SPROM1_MAC_ETH;
-		loc[2] = SIBA_SPROM1_MAC_80211A;
-	}
-	for (i = 0; i < 3; i++) {
-		v = in[SIBA_OFFSET(loc[0]) + i];
-		*(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
-	}
-	if (out->rev < 3) {
-		for (i = 0; i < 3; i++) {
-			v = in[SIBA_OFFSET(loc[1]) + i];
-			*(((uint16_t *)out->mac_eth) + i) = htobe16(v);
-		}
-		for (i = 0; i < 3; i++) {
-			v = in[SIBA_OFFSET(loc[2]) + i];
-			*(((uint16_t *)out->mac_80211a) + i) = htobe16(v);
-		}
-	}
-	SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY,
-	    SIBA_SPROM1_ETHPHY_MII_ETH0);
-	SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY,
-	    SIBA_SPROM1_ETHPHY_MII_ETH1);
-	SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY,
-	    SIBA_SPROM1_ETHPHY_MDIO_ETH0);
-	SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY,
-	    SIBA_SPROM1_ETHPHY_MDIO_ETH1);
-	SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV);
-	SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO,
-	    SIBA_SPROM1_BOARDINFO_CCODE);
-	SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA);
-	SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO,
-	    SIBA_SPROM1_BOARDINFO_ANTBG);
-	SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff);
-	SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff);
-	SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff);
-	SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff);
-	SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff);
-	SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff);
-	SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0);
-	SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1);
-	SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2);
-	SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3);
-
-	SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A);
-	SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG);
-	SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A);
-	SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG);
-	SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff);
-	if (out->rev >= 2)
-		SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff);
-
-	/* antenna gain */
-	gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0);
-	out->again.ghz24.a0 = out->again.ghz24.a1 = gain;
-	out->again.ghz24.a2 = out->again.ghz24.a3 = gain;
-	gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8);
-	out->again.ghz5.a0 = out->again.ghz5.a1 = gain;
-	out->again.ghz5.a2 = out->again.ghz5.a3 = gain;
-}
-
-static void
-siba_sprom_r458(struct siba_sprom *out, const uint16_t *in)
-{
-
-	SIBA_SHIFTOUT(txpid2g[0], SIBA_SPROM4_TXPID2G01,
-	    SIBA_SPROM4_TXPID2G0);
-	SIBA_SHIFTOUT(txpid2g[1], SIBA_SPROM4_TXPID2G01,
-	    SIBA_SPROM4_TXPID2G1);
-	SIBA_SHIFTOUT(txpid2g[2], SIBA_SPROM4_TXPID2G23,
-	    SIBA_SPROM4_TXPID2G2);
-	SIBA_SHIFTOUT(txpid2g[3], SIBA_SPROM4_TXPID2G23,
-	    SIBA_SPROM4_TXPID2G3);
-
-	SIBA_SHIFTOUT(txpid5gl[0], SIBA_SPROM4_TXPID5GL01,
-	    SIBA_SPROM4_TXPID5GL0);
-	SIBA_SHIFTOUT(txpid5gl[1], SIBA_SPROM4_TXPID5GL01,
-	    SIBA_SPROM4_TXPID5GL1);
-	SIBA_SHIFTOUT(txpid5gl[2], SIBA_SPROM4_TXPID5GL23,
-	    SIBA_SPROM4_TXPID5GL2);
-	SIBA_SHIFTOUT(txpid5gl[3], SIBA_SPROM4_TXPID5GL23,
-	    SIBA_SPROM4_TXPID5GL3);
-
-	SIBA_SHIFTOUT(txpid5g[0], SIBA_SPROM4_TXPID5G01,
-	    SIBA_SPROM4_TXPID5G0);
-	SIBA_SHIFTOUT(txpid5g[1], SIBA_SPROM4_TXPID5G01,
-	    SIBA_SPROM4_TXPID5G1);
-	SIBA_SHIFTOUT(txpid5g[2], SIBA_SPROM4_TXPID5G23,
-	    SIBA_SPROM4_TXPID5G2);
-	SIBA_SHIFTOUT(txpid5g[3], SIBA_SPROM4_TXPID5G23,
-	    SIBA_SPROM4_TXPID5G3);
-
-	SIBA_SHIFTOUT(txpid5gh[0], SIBA_SPROM4_TXPID5GH01,
-	    SIBA_SPROM4_TXPID5GH0);
-	SIBA_SHIFTOUT(txpid5gh[1], SIBA_SPROM4_TXPID5GH01,
-	    SIBA_SPROM4_TXPID5GH1);
-	SIBA_SHIFTOUT(txpid5gh[2], SIBA_SPROM4_TXPID5GH23,
-	    SIBA_SPROM4_TXPID5GH2);
-	SIBA_SHIFTOUT(txpid5gh[3], SIBA_SPROM4_TXPID5GH23,
-	    SIBA_SPROM4_TXPID5GH3);
-}
-
-static void
-siba_sprom_r45(struct siba_sprom *out, const uint16_t *in)
-{
-	int i;
-	uint16_t v;
-	uint16_t mac_80211bg_offset;
-	const uint16_t pwr_info_offset[] = {
-	    SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1,
-	    SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3
-	};
-
-	if (out->rev == 4)
-		mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG;
-	else
-		mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG;
-	for (i = 0; i < 3; i++) {
-		v = in[SIBA_OFFSET(mac_80211bg_offset) + i];
-		*(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
-	}
-	SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A);
-	SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A);
-	if (out->rev == 4) {
-		SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff);
-		SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff);
-		SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff);
-	} else {
-		SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff);
-		SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff);
-		SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff);
-	}
-	SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A);
-	SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG);
-	SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK);
-	SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG);
-	SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK);
-	SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A);
-	if (out->rev == 4) {
-		SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0);
-		SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1);
-		SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2);
-		SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3);
-	} else {
-		SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0);
-		SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1);
-		SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2);
-		SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3);
-	}
-
-	/* antenna gain */
-	SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0);
-	SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1);
-	SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2);
-	SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3);
-	bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
-
-	/* Extract core power info */
-	for (i = 0; i < nitems(pwr_info_offset); i++) {
-		uint16_t o = pwr_info_offset[i];
-
-		SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI,
-			SIBA_SPROM4_2G_ITSSI);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI,
-			SIBA_SPROM4_2G_MAXP);
-
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0);
-
-		SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI,
-			SIBA_SPROM4_5G_ITSSI);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI,
-			SIBA_SPROM4_5G_MAXP);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP,
-			SIBA_SPROM4_5GH_MAXP);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP,
-			SIBA_SPROM4_5GL_MAXP);
-
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0);
-	}
-
-	siba_sprom_r458(out, in);
-}
-
-static void
-siba_sprom_r8(struct siba_sprom *out, const uint16_t *in)
-{
-	int i;
-	uint16_t v;
-	uint16_t pwr_info_offset[] = {
-		SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1,
-		SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3
-	};
-
-	for (i = 0; i < 3; i++) {
-		v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i];
-		*(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
-	}
-	SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff);
-	SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff);
-	SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff);
-	SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff);
-	SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff);
-	SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A);
-	SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG);
-	SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK);
-	SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG);
-	SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK);
-	SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A);
-	SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL,
-	    SIBA_SPROM8_MAXP_AH_MASK);
-	SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL,
-	    SIBA_SPROM8_MAXP_AL_MASK);
-	SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0);
-	SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1);
-	SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2);
-	SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3);
-	SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G);
-	SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G);
-	SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL);
-	SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH);
-	SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G);
-	SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G);
-
-	SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G);
-	SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G);
-	SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G);
-	SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G);
-	SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G);
-	SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G);
-	SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G);
-	SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G);
-
-	SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff);
-	SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff);
-	SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff);
-	SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff);
-	SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff);
-	SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff);
-	SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff);
-	SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff);
-	SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff);
-	SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff);
-	SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff);
-	SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff);
-	SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff);
-
-	SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0);
-	SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0);
-	SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0);
-	SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0);
-
-	/* antenna gain */
-	SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0);
-	SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1);
-	SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2);
-	SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3);
-	bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
-
-	/* FEM */
-	SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G,
-	    SIBA_SROM8_FEM_TSSIPOS);
-	SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G,
-	    SIBA_SROM8_FEM_EXTPA_GAIN);
-	SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G,
-	    SIBA_SROM8_FEM_PDET_RANGE);
-	SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G,
-	    SIBA_SROM8_FEM_TR_ISO);
-	SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G,
-	    SIBA_SROM8_FEM_ANTSWLUT);
-
-	SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G,
-	    SIBA_SROM8_FEM_TSSIPOS);
-	SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G,
-	    SIBA_SROM8_FEM_EXTPA_GAIN);
-	SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G,
-	    SIBA_SROM8_FEM_PDET_RANGE);
-	SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G,
-	    SIBA_SROM8_FEM_TR_ISO);
-	SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G,
-	    SIBA_SROM8_FEM_ANTSWLUT);
-
-	/* Extract cores power info info */
-	for (i = 0; i < nitems(pwr_info_offset); i++) {
-		uint16_t o = pwr_info_offset[i];
-		SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI,
-			SIBA_SPROM8_2G_ITSSI);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI,
-			SIBA_SPROM8_2G_MAXP);
-
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0);
-
-		SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI,
-			SIBA_SPROM8_5G_ITSSI);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI,
-			SIBA_SPROM8_5G_MAXP);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP,
-			SIBA_SPROM8_5GH_MAXP);
-		SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP,
-			SIBA_SPROM8_5GL_MAXP);
-
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0);
-		SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0);
-	}
-
-	SIBA_SHIFTOUT(cddpo, SIBA_SPROM8_CDDPO, ~0);
-	SIBA_SHIFTOUT(stbcpo, SIBA_SPROM8_STBCPO, ~0);
-
-	siba_sprom_r458(out, in);
-}
-
-static int8_t
-siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in,
-    uint16_t mask, uint16_t shift)
-{
-	uint16_t v;
-	uint8_t gain;
-
-	v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)];
-	gain = (v & mask) >> shift;
-	gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 :
-	    ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2);
-
-	return ((int8_t)gain);
-}
-
-#undef SIBA_LOWEST_SET_BIT
-#undef SIBA_OFFSET
-#undef SIBA_SHIFTOUT_SUB
-#undef SIBA_SHIFTOUT
-
-int
-siba_powerdown(device_t dev)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	return (siba_powerdown_sub(siba));
-}
-
-static int
-siba_powerdown_sub(struct siba_softc *siba)
-{
-	struct siba_cc *scc;
-
-	if (siba->siba_type == SIBA_TYPE_SSB)
-		return (0);
-
-	scc = &siba->siba_cc;
-	if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5)
-		return (0);
-	siba_cc_clock(scc, SIBA_CLOCK_SLOW);
-	siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
-	return (0);
-}
-
-static void
-siba_pcicore_init(struct siba_pci *spc)
-{
-	struct siba_dev_softc *sd = spc->spc_dev;
-
-	if (sd == NULL)
-		return;
-
-	if (!siba_dev_isup_sub(sd))
-		siba_dev_up_sub(sd, 0);
-
-	KASSERT(spc->spc_hostmode == 0,
-	    ("%s:%d: hostmode", __func__, __LINE__));
-	/* disable PCI interrupt */
-	siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
-}
-
-int
-siba_dev_isup(device_t dev)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	return (siba_dev_isup_sub(sd));
-}
-
-static int
-siba_dev_isup_sub(struct siba_dev_softc *sd)
-{
-	uint32_t reject, val;
-
-	reject = siba_tmslow_reject_bitmask(sd);
-	val = siba_read_4_sub(sd, SIBA_TGSLOW);
-	val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject;
-
-	return (val == SIBA_TGSLOW_CLOCK);
-}
-
-void
-siba_dev_up(device_t dev, uint32_t flags)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	siba_dev_up_sub(sd, flags);
-}
-
-static void
-siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags)
-{
-	uint32_t val;
-
-	siba_dev_down_sub(sd, flags);
-	siba_write_4_sub(sd, SIBA_TGSLOW,
-	    SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
-	siba_read_4_sub(sd, SIBA_TGSLOW);
-	DELAY(1);
-
-	if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
-		siba_write_4_sub(sd, SIBA_TGSHIGH, 0);
-
-	val = siba_read_4_sub(sd, SIBA_IAS);
-	if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) {
-		val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT);
-		siba_write_4_sub(sd, SIBA_IAS, val);
-	}
-
-	siba_write_4_sub(sd, SIBA_TGSLOW,
-	    SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
-	siba_read_4_sub(sd, SIBA_TGSLOW);
-	DELAY(1);
-
-	siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
-	siba_read_4_sub(sd, SIBA_TGSLOW);
-	DELAY(1);
-}
-
-static uint32_t
-siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
-{
-	uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
-
-	switch (rev) {
-	case SIBA_IDLOW_SSBREV_22:
-		return (SIBA_TGSLOW_REJECT_22);
-	case SIBA_IDLOW_SSBREV_23:
-		return (SIBA_TGSLOW_REJECT_23);
-	case SIBA_IDLOW_SSBREV_24:
-	case SIBA_IDLOW_SSBREV_25:
-	case SIBA_IDLOW_SSBREV_26:
-	case SIBA_IDLOW_SSBREV_27:
-		return (SIBA_TGSLOW_REJECT_23);
-	default:
-		KASSERT(0 == 1,
-		    ("%s:%d: unknown backplane rev %#x\n",
-			__func__, __LINE__, rev));
-	}
-	return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23);
-}
-
-void
-siba_dev_down(device_t dev, uint32_t flags)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-
-	siba_dev_down_sub(sd, flags);
-}
-
-static void
-siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags)
-{
-	struct siba_softc *siba = sd->sd_bus;
-	uint32_t reject, val;
-	int i;
-
-	if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
-		return;
-
-	reject = siba_tmslow_reject_bitmask(sd);
-	siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
-
-	for (i = 0; i < 1000; i++) {
-		val = siba_read_4_sub(sd, SIBA_TGSLOW);
-		if (val & reject)
-			break;
-		DELAY(10);
-	}
-	if ((val & reject) == 0) {
-		device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
-		    reject, SIBA_TGSLOW);
-	}
-	for (i = 0; i < 1000; i++) {
-		val = siba_read_4_sub(sd, SIBA_TGSHIGH);
-		if (!(val & SIBA_TGSHIGH_BUSY))
-			break;
-		DELAY(10);
-	}
-	if ((val & SIBA_TGSHIGH_BUSY) != 0) {
-		device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
-		    SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH);
-	}
-
-	siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
-	    reject | SIBA_TGSLOW_RESET | flags);
-	siba_read_4_sub(sd, SIBA_TGSLOW);
-	DELAY(1);
-	siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
-	siba_read_4_sub(sd, SIBA_TGSLOW);
-	DELAY(1);
-}
-
-static void
-siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
-{
-	struct siba_dev_softc *psd = spc->spc_dev;
-	struct siba_softc *siba = psd->sd_bus;
-	uint32_t tmp;
-
-	if (psd->sd_id.sd_device == SIBA_DEVID_PCI) {
-		siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2,
-		    siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) |
-		    SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST);
-
-		if (psd->sd_id.sd_rev < 5) {
-			tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
-			tmp &= ~SIBA_IMCFGLO_SERTO;
-			tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
-			tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
-			siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
-
-			/* broadcast value */
-			sd = (siba->siba_cc.scc_dev != NULL) ?
-			    siba->siba_cc.scc_dev : siba->siba_pci.spc_dev;
-			if (sd != NULL) {
-				siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR,
-				    0xfd8);
-				siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR);
-				siba_write_4_sub(sd,
-				    SIBA_PCICORE_BCAST_DATA, 0);
-				siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA);
-			}
-		} else if (psd->sd_id.sd_rev >= 11) {
-			tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
-			tmp |= SIBA_PCICORE_SBTOPCI_MRM;
-			siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
-		}
-	} else {
-		KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE"));
-		if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1))
-			siba_pcie_write(spc, 0x4,
-			    siba_pcie_read(spc, 0x4) | 0x8);
-		if (psd->sd_id.sd_rev == 0) {
-			siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */
-			siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */
-			siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */
-		} else if (psd->sd_id.sd_rev == 1)
-			siba_pcie_write(spc, 0x100,
-			    siba_pcie_read(spc, 0x100) | 0x40);
-	}
-	spc->spc_inited = 1;
-}
-
-void
-siba_pcicore_intr(device_t dev)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_pci *spc = &siba->siba_pci;
-	struct siba_dev_softc *psd = spc->spc_dev;
-	uint32_t tmp;
-
-	if (siba->siba_type != SIBA_TYPE_PCI || !psd)
-		return;
-
-	KASSERT(siba == psd->sd_bus, ("different pointers"));
-
-	/* enable interrupts */
-	if (siba->siba_dev != NULL &&
-	    (psd->sd_id.sd_rev >= 6 ||
-	     psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
-		tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
-		tmp |= (1 << sd->sd_coreidx) << 8;
-		pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
-	} else {
-		tmp = siba_read_4_sub(sd, SIBA_TPS);
-		tmp &= SIBA_TPS_BPFLAG;
-		siba_write_4_sub(psd, SIBA_INTR_MASK,
-		    siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
-	}
-
-	/* setup PCIcore */
-	if (spc->spc_inited == 0)
-		siba_pcicore_setup(spc, sd);
-}
-
-static uint32_t
-siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
-{
-
-	return (siba_read_4_sub(spc->spc_dev, offset));
-}
-
-static void
-siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
-{
-
-	siba_write_4_sub(spc->spc_dev, offset, value);
-}
-
-static uint32_t
-siba_pcie_read(struct siba_pci *spc, uint32_t address)
-{
-
-	siba_pcicore_write_4(spc, 0x130, address);
-	return (siba_pcicore_read_4(spc, 0x134));
-}
-
-static void
-siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data)
-{
-
-	siba_pcicore_write_4(spc, 0x130, address);
-	siba_pcicore_write_4(spc, 0x134, data);
-}
-
-static void
-siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
-    uint16_t data)
-{
-	int i;
-
-	siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2);
-	siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA,
-	    (1 << 30) | (1 << 28) |
-	    ((uint32_t)device << 22) | ((uint32_t)address << 18) |
-	    (1 << 17) | data);
-	DELAY(10);
-	for (i = 0; i < 10; i++) {
-		if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100)
-			break;
-		DELAY(1000);
-	}
-	siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0);
-}
-
-uint32_t
-siba_dma_translation(device_t dev)
-{
-#ifdef INVARIANTS
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	KASSERT(siba->siba_type == SIBA_TYPE_PCI,
-	    ("unsupported bustype %d\n", siba->siba_type));
-#endif
-
-	/* Default */
-	return (SIBA_PCI_DMA);
-}
-
-void
-siba_barrier(device_t dev, int flags)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	SIBA_BARRIER(siba, flags);
-}
-
-static void
-siba_cc_suspend(struct siba_cc *scc)
-{
-
-	siba_cc_clock(scc, SIBA_CLOCK_SLOW);
-}
-
-static void
-siba_cc_resume(struct siba_cc *scc)
-{
-
-	siba_cc_power_init(scc);
-	siba_cc_clock(scc, SIBA_CLOCK_FAST);
-}
-
-int
-siba_core_suspend(struct siba_softc *siba)
-{
-
-	siba_cc_suspend(&siba->siba_cc);
-	siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
-	return (0);
-}
-
-int
-siba_core_resume(struct siba_softc *siba)
-{
-
-	siba->siba_pci.spc_inited = 0;
-	siba->siba_curdev = NULL;
-
-	siba_powerup_sub(siba, 0);
-	/* XXX setup H/W for PCMCIA??? */
-	siba_cc_resume(&siba->siba_cc);
-	siba_powerdown_sub(siba);
-
-	return (0);
-}
-
-static void
-siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask,
-    uint32_t set)
-{
-
-	SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
-	SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset);
-	SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
-	SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA,
-	    (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set);
-	SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA);
-}
-
-void
-siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc = &siba->siba_cc;
-	uint32_t *p = NULL, info[5][3] = {
-		{ 2, 25,  0xf },
-		{ 3,  1,  0xf },
-		{ 3,  9,  0xf },
-		{ 3, 17, 0x3f },
-		{ 0, 21, 0x3f }
-	};
-
-	if (siba->siba_chipid == 0x4312) {
-		if (id != SIBA_LDO_PAREF)
-			return;
-		p = info[4];
-		siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
-		    (volt & p[2]) << p[1]);
-		return;
-	}
-	if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) {
-		switch (id) {
-		case SIBA_LDO_PAREF:
-			p = info[3];
-			break;
-		case SIBA_LDO_VOLT1:
-			p = info[0];
-			break;
-		case SIBA_LDO_VOLT2:
-			p = info[1];
-			break;
-		case SIBA_LDO_VOLT3:
-			p = info[2];
-			break;
-		default:
-			KASSERT(0 == 1,
-			    ("%s: unsupported voltage ID %#x", __func__, id));
-			return;
-		}
-		siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
-		    (volt & p[2]) << p[1]);
-	}
-}
-
-void
-siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc = &siba->siba_cc;
-	int ldo;
-
-	ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF :
-	    ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF :
-	    ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1)));
-	if (ldo == -1)
-		return;
-
-	if (on)
-		SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo);
-	else
-		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
-	SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);
-}
-
-int
-siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result)
-{
-	struct siba_dev_softc *sd = device_get_ivars(child);
-	struct siba_softc *siba = sd->sd_bus;
-
-	switch (which) {
-	case SIBA_SPROMVAR_REV:
-		*result = siba->siba_sprom.rev;
-		break;
-	case SIBA_SPROMVAR_MAC_80211BG:
-		*((uint8_t **) result) = siba->siba_sprom.mac_80211bg;
-		break;
-	case SIBA_SPROMVAR_MAC_ETH:
-		*((uint8_t **) result) = siba->siba_sprom.mac_eth;
-		break;
-	case SIBA_SPROMVAR_MAC_80211A:
-		*((uint8_t **) result) = siba->siba_sprom.mac_80211a;
-		break;
-	case SIBA_SPROMVAR_MII_ETH0:
-		*result = siba->siba_sprom.mii_eth0;
-		break;
-	case SIBA_SPROMVAR_MII_ETH1:
-		*result = siba->siba_sprom.mii_eth1;
-		break;
-	case SIBA_SPROMVAR_MDIO_ETH0:
-		*result = siba->siba_sprom.mdio_eth0;
-		break;
-	case SIBA_SPROMVAR_MDIO_ETH1:
-		*result = siba->siba_sprom.mdio_eth1;
-		break;
-	case SIBA_SPROMVAR_BREV:
-		*result = siba->siba_sprom.brev;
-		break;
-	case SIBA_SPROMVAR_CCODE:
-		*result = siba->siba_sprom.ccode;
-		break;
-	case SIBA_SPROMVAR_ANT_A:
-		*result = siba->siba_sprom.ant_a;
-		break;
-	case SIBA_SPROMVAR_ANT_BG:
-		*result = siba->siba_sprom.ant_bg;
-		break;
-	case SIBA_SPROMVAR_PA0B0:
-		*result = siba->siba_sprom.pa0b0;
-		break;
-	case SIBA_SPROMVAR_PA0B1:
-		*result = siba->siba_sprom.pa0b1;
-		break;
-	case SIBA_SPROMVAR_PA0B2:
-		*result = siba->siba_sprom.pa0b2;
-		break;
-	case SIBA_SPROMVAR_PA1B0:
-		*result = siba->siba_sprom.pa1b0;
-		break;
-	case SIBA_SPROMVAR_PA1B1:
-		*result = siba->siba_sprom.pa1b1;
-		break;
-	case SIBA_SPROMVAR_PA1B2:
-		*result = siba->siba_sprom.pa1b2;
-		break;
-	case SIBA_SPROMVAR_PA1LOB0:
-		*result = siba->siba_sprom.pa1lob0;
-		break;
-	case SIBA_SPROMVAR_PA1LOB1:
-		*result = siba->siba_sprom.pa1lob1;
-		break;
-	case SIBA_SPROMVAR_PA1LOB2:
-		*result = siba->siba_sprom.pa1lob2;
-		break;
-	case SIBA_SPROMVAR_PA1HIB0:
-		*result = siba->siba_sprom.pa1hib0;
-		break;
-	case SIBA_SPROMVAR_PA1HIB1:
-		*result = siba->siba_sprom.pa1hib1;
-		break;
-	case SIBA_SPROMVAR_PA1HIB2:
-		*result = siba->siba_sprom.pa1hib2;
-		break;
-	case SIBA_SPROMVAR_GPIO0:
-		*result = siba->siba_sprom.gpio0;
-		break;
-	case SIBA_SPROMVAR_GPIO1:
-		*result = siba->siba_sprom.gpio1;
-		break;
-	case SIBA_SPROMVAR_GPIO2:
-		*result = siba->siba_sprom.gpio2;
-		break;
-	case SIBA_SPROMVAR_GPIO3:
-		*result = siba->siba_sprom.gpio3;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_AL:
-		*result = siba->siba_sprom.maxpwr_al;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_A:
-		*result = siba->siba_sprom.maxpwr_a;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_AH:
-		*result = siba->siba_sprom.maxpwr_ah;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_BG:
-		*result = siba->siba_sprom.maxpwr_bg;
-		break;
-	case SIBA_SPROMVAR_RXPO2G:
-		*result = siba->siba_sprom.rxpo2g;
-		break;
-	case SIBA_SPROMVAR_RXPO5G:
-		*result = siba->siba_sprom.rxpo5g;
-		break;
-	case SIBA_SPROMVAR_TSSI_A:
-		*result = siba->siba_sprom.tssi_a;
-		break;
-	case SIBA_SPROMVAR_TSSI_BG:
-		*result = siba->siba_sprom.tssi_bg;
-		break;
-	case SIBA_SPROMVAR_TRI2G:
-		*result = siba->siba_sprom.tri2g;
-		break;
-	case SIBA_SPROMVAR_TRI5GL:
-		*result = siba->siba_sprom.tri5gl;
-		break;
-	case SIBA_SPROMVAR_TRI5G:
-		*result = siba->siba_sprom.tri5g;
-		break;
-	case SIBA_SPROMVAR_TRI5GH:
-		*result = siba->siba_sprom.tri5gh;
-		break;
-	case SIBA_SPROMVAR_RSSISAV2G:
-		*result = siba->siba_sprom.rssisav2g;
-		break;
-	case SIBA_SPROMVAR_RSSISMC2G:
-		*result = siba->siba_sprom.rssismc2g;
-		break;
-	case SIBA_SPROMVAR_RSSISMF2G:
-		*result = siba->siba_sprom.rssismf2g;
-		break;
-	case SIBA_SPROMVAR_BXA2G:
-		*result = siba->siba_sprom.bxa2g;
-		break;
-	case SIBA_SPROMVAR_RSSISAV5G:
-		*result = siba->siba_sprom.rssisav5g;
-		break;
-	case SIBA_SPROMVAR_RSSISMC5G:
-		*result = siba->siba_sprom.rssismc5g;
-		break;
-	case SIBA_SPROMVAR_RSSISMF5G:
-		*result = siba->siba_sprom.rssismf5g;
-		break;
-	case SIBA_SPROMVAR_BXA5G:
-		*result = siba->siba_sprom.bxa5g;
-		break;
-	case SIBA_SPROMVAR_CCK2GPO:
-		*result = siba->siba_sprom.cck2gpo;
-		break;
-	case SIBA_SPROMVAR_OFDM2GPO:
-		*result = siba->siba_sprom.ofdm2gpo;
-		break;
-	case SIBA_SPROMVAR_OFDM5GLPO:
-		*result = siba->siba_sprom.ofdm5glpo;
-		break;
-	case SIBA_SPROMVAR_OFDM5GPO:
-		*result = siba->siba_sprom.ofdm5gpo;
-		break;
-	case SIBA_SPROMVAR_OFDM5GHPO:
-		*result = siba->siba_sprom.ofdm5ghpo;
-		break;
-	case SIBA_SPROMVAR_BF_LO:
-		*result = siba->siba_sprom.bf_lo;
-		break;
-	case SIBA_SPROMVAR_BF_HI:
-		*result = siba->siba_sprom.bf_hi;
-		break;
-	case SIBA_SPROMVAR_BF2_LO:
-		*result = siba->siba_sprom.bf2_lo;
-		break;
-	case SIBA_SPROMVAR_BF2_HI:
-		*result = siba->siba_sprom.bf2_hi;
-		break;
-	case SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS:
-		*result = siba->siba_sprom.fem.ghz2.tssipos;
-		break;
-	case SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN:
-		*result = siba->siba_sprom.fem.ghz2.extpa_gain;
-		break;
-	case SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE:
-		*result = siba->siba_sprom.fem.ghz2.pdet_range;
-		break;
-	case SIBA_SPROMVAR_FEM_2GHZ_TR_ISO:
-		*result = siba->siba_sprom.fem.ghz2.tr_iso;
-		break;
-	case SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT:
-		*result = siba->siba_sprom.fem.ghz2.antswlut;
-		break;
-	case SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS:
-		*result = siba->siba_sprom.fem.ghz5.tssipos;
-		break;
-	case SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN:
-		*result = siba->siba_sprom.fem.ghz5.extpa_gain;
-		break;
-	case SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE:
-		*result = siba->siba_sprom.fem.ghz5.pdet_range;
-		break;
-	case SIBA_SPROMVAR_FEM_5GHZ_TR_ISO:
-		*result = siba->siba_sprom.fem.ghz5.tr_iso;
-		break;
-	case SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT:
-		*result = siba->siba_sprom.fem.ghz5.antswlut;
-		break;
-	case SIBA_SPROMVAR_TXPID_2G_0:
-		*result = siba->siba_sprom.txpid2g[0];
-		break;
-	case SIBA_SPROMVAR_TXPID_2G_1:
-		*result = siba->siba_sprom.txpid2g[1];
-		break;
-	case SIBA_SPROMVAR_TXPID_2G_2:
-		*result = siba->siba_sprom.txpid2g[2];
-		break;
-	case SIBA_SPROMVAR_TXPID_2G_3:
-		*result = siba->siba_sprom.txpid2g[3];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GL_0:
-		*result = siba->siba_sprom.txpid5gl[0];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GL_1:
-		*result = siba->siba_sprom.txpid5gl[1];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GL_2:
-		*result = siba->siba_sprom.txpid5gl[2];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GL_3:
-		*result = siba->siba_sprom.txpid5gl[3];
-		break;
-	case SIBA_SPROMVAR_TXPID_5G_0:
-		*result = siba->siba_sprom.txpid5g[0];
-		break;
-	case SIBA_SPROMVAR_TXPID_5G_1:
-		*result = siba->siba_sprom.txpid5g[1];
-		break;
-	case SIBA_SPROMVAR_TXPID_5G_2:
-		*result = siba->siba_sprom.txpid5g[2];
-		break;
-	case SIBA_SPROMVAR_TXPID_5G_3:
-		*result = siba->siba_sprom.txpid5g[3];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GH_0:
-		*result = siba->siba_sprom.txpid5gh[0];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GH_1:
-		*result = siba->siba_sprom.txpid5gh[1];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GH_2:
-		*result = siba->siba_sprom.txpid5gh[2];
-		break;
-	case SIBA_SPROMVAR_TXPID_5GH_3:
-		*result = siba->siba_sprom.txpid5gh[3];
-		break;
-	case SIBA_SPROMVAR_STBCPO:
-		*result = siba->siba_sprom.stbcpo;
-		break;
-	case SIBA_SPROMVAR_CDDPO:
-		*result = siba->siba_sprom.cddpo;
-		break;
-	default:
-		return (ENOENT);
-	}
-	return (0);
-}
-
-int
-siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value)
-{
-	struct siba_dev_softc *sd = device_get_ivars(child);
-	struct siba_softc *siba = sd->sd_bus;
-
-	switch (which) {
-	case SIBA_SPROMVAR_REV:
-		siba->siba_sprom.rev = value;
-		break;
-	case SIBA_SPROMVAR_MII_ETH0:
-		siba->siba_sprom.mii_eth0 = value;
-		break;
-	case SIBA_SPROMVAR_MII_ETH1:
-		siba->siba_sprom.mii_eth1 = value;
-		break;
-	case SIBA_SPROMVAR_MDIO_ETH0:
-		siba->siba_sprom.mdio_eth0 = value;
-		break;
-	case SIBA_SPROMVAR_MDIO_ETH1:
-		siba->siba_sprom.mdio_eth1 = value;
-		break;
-	case SIBA_SPROMVAR_BREV:
-		siba->siba_sprom.brev = value;
-		break;
-	case SIBA_SPROMVAR_CCODE:
-		siba->siba_sprom.ccode = value;
-		break;
-	case SIBA_SPROMVAR_ANT_A:
-		siba->siba_sprom.ant_a = value;
-		break;
-	case SIBA_SPROMVAR_ANT_BG:
-		siba->siba_sprom.ant_bg = value;
-		break;
-	case SIBA_SPROMVAR_PA0B0:
-		siba->siba_sprom.pa0b0 = value;
-		break;
-	case SIBA_SPROMVAR_PA0B1:
-		siba->siba_sprom.pa0b1 = value;
-		break;
-	case SIBA_SPROMVAR_PA0B2:
-		siba->siba_sprom.pa0b2 = value;
-		break;
-	case SIBA_SPROMVAR_PA1B0:
-		siba->siba_sprom.pa1b0 = value;
-		break;
-	case SIBA_SPROMVAR_PA1B1:
-		siba->siba_sprom.pa1b1 = value;
-		break;
-	case SIBA_SPROMVAR_PA1B2:
-		siba->siba_sprom.pa1b2 = value;
-		break;
-	case SIBA_SPROMVAR_PA1LOB0:
-		siba->siba_sprom.pa1lob0 = value;
-		break;
-	case SIBA_SPROMVAR_PA1LOB1:
-		siba->siba_sprom.pa1lob1 = value;
-		break;
-	case SIBA_SPROMVAR_PA1LOB2:
-		siba->siba_sprom.pa1lob2 = value;
-		break;
-	case SIBA_SPROMVAR_PA1HIB0:
-		siba->siba_sprom.pa1hib0 = value;
-		break;
-	case SIBA_SPROMVAR_PA1HIB1:
-		siba->siba_sprom.pa1hib1 = value;
-		break;
-	case SIBA_SPROMVAR_PA1HIB2:
-		siba->siba_sprom.pa1hib2 = value;
-		break;
-	case SIBA_SPROMVAR_GPIO0:
-		siba->siba_sprom.gpio0 = value;
-		break;
-	case SIBA_SPROMVAR_GPIO1:
-		siba->siba_sprom.gpio1 = value;
-		break;
-	case SIBA_SPROMVAR_GPIO2:
-		siba->siba_sprom.gpio2 = value;
-		break;
-	case SIBA_SPROMVAR_GPIO3:
-		siba->siba_sprom.gpio3 = value;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_AL:
-		siba->siba_sprom.maxpwr_al = value;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_A:
-		siba->siba_sprom.maxpwr_a = value;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_AH:
-		siba->siba_sprom.maxpwr_ah = value;
-		break;
-	case SIBA_SPROMVAR_MAXPWR_BG:
-		siba->siba_sprom.maxpwr_bg = value;
-		break;
-	case SIBA_SPROMVAR_RXPO2G:
-		siba->siba_sprom.rxpo2g = value;
-		break;
-	case SIBA_SPROMVAR_RXPO5G:
-		siba->siba_sprom.rxpo5g = value;
-		break;
-	case SIBA_SPROMVAR_TSSI_A:
-		siba->siba_sprom.tssi_a = value;
-		break;
-	case SIBA_SPROMVAR_TSSI_BG:
-		siba->siba_sprom.tssi_bg = value;
-		break;
-	case SIBA_SPROMVAR_TRI2G:
-		siba->siba_sprom.tri2g = value;
-		break;
-	case SIBA_SPROMVAR_TRI5GL:
-		siba->siba_sprom.tri5gl = value;
-		break;
-	case SIBA_SPROMVAR_TRI5G:
-		siba->siba_sprom.tri5g = value;
-		break;
-	case SIBA_SPROMVAR_TRI5GH:
-		siba->siba_sprom.tri5gh = value;
-		break;
-	case SIBA_SPROMVAR_RSSISAV2G:
-		siba->siba_sprom.rssisav2g = value;
-		break;
-	case SIBA_SPROMVAR_RSSISMC2G:
-		siba->siba_sprom.rssismc2g = value;
-		break;
-	case SIBA_SPROMVAR_RSSISMF2G:
-		siba->siba_sprom.rssismf2g = value;
-		break;
-	case SIBA_SPROMVAR_BXA2G:
-		siba->siba_sprom.bxa2g = value;
-		break;
-	case SIBA_SPROMVAR_RSSISAV5G:
-		siba->siba_sprom.rssisav5g = value;
-		break;
-	case SIBA_SPROMVAR_RSSISMC5G:
-		siba->siba_sprom.rssismc5g = value;
-		break;
-	case SIBA_SPROMVAR_RSSISMF5G:
-		siba->siba_sprom.rssismf5g = value;
-		break;
-	case SIBA_SPROMVAR_BXA5G:
-		siba->siba_sprom.bxa5g = value;
-		break;
-	case SIBA_SPROMVAR_CCK2GPO:
-		siba->siba_sprom.cck2gpo = value;
-		break;
-	case SIBA_SPROMVAR_OFDM2GPO:
-		siba->siba_sprom.ofdm2gpo = value;
-		break;
-	case SIBA_SPROMVAR_OFDM5GLPO:
-		siba->siba_sprom.ofdm5glpo = value;
-		break;
-	case SIBA_SPROMVAR_OFDM5GPO:
-		siba->siba_sprom.ofdm5gpo = value;
-		break;
-	case SIBA_SPROMVAR_OFDM5GHPO:
-		siba->siba_sprom.ofdm5ghpo = value;
-		break;
-	case SIBA_SPROMVAR_BF_LO:
-		siba->siba_sprom.bf_lo = value;
-		break;
-	case SIBA_SPROMVAR_BF_HI:
-		siba->siba_sprom.bf_hi = value;
-		break;
-	case SIBA_SPROMVAR_BF2_LO:
-		siba->siba_sprom.bf2_lo = value;
-		break;
-	case SIBA_SPROMVAR_BF2_HI:
-		siba->siba_sprom.bf2_hi = value;
-		break;
-	default:
-		return (ENOENT);
-	}
-	return (0);
-}
-
-#define	SIBA_GPIOCTL			0x06c
-
-uint32_t
-siba_gpio_get(device_t dev)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_dev_softc *gpiodev, *pcidev = NULL;
-
-	pcidev = siba->siba_pci.spc_dev;
-	gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
-	if (!gpiodev)
-		return (-1);
-	return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL));
-}
-
-void
-siba_gpio_set(device_t dev, uint32_t value)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_dev_softc *gpiodev, *pcidev = NULL;
-
-	pcidev = siba->siba_pci.spc_dev;
-	gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
-	if (!gpiodev)
-		return;
-	siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value);
-}
-
-void
-siba_fix_imcfglobug(device_t dev)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	uint32_t tmp;
-
-	if (siba->siba_pci.spc_dev == NULL)
-		return;
-	if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
-	    siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
-		return;
-
-	tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
-	    ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
-	switch (siba->siba_type) {
-	case SIBA_TYPE_PCI:
-	case SIBA_TYPE_PCMCIA:
-		tmp |= 0x32;
-		break;
-	case SIBA_TYPE_SSB:
-		tmp |= 0x53;
-		break;
-	}
-	siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);
-}
-
-int
-siba_sprom_get_core_power_info(device_t dev, int core,
-    struct siba_sprom_core_pwr_info *c)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	if (core < 0 || core > 3) {
-		return (EINVAL);
-	}
-	memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c));
-	return (0);
-}
-
-int
-siba_sprom_get_mcs2gpo(device_t dev, uint16_t *c)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	memcpy(c, &siba->siba_sprom.mcs2gpo, sizeof(uint16_t) * 8);
-	return (0);
-}
-
-int
-siba_sprom_get_mcs5glpo(device_t dev, uint16_t *c)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	memcpy(c, &siba->siba_sprom.mcs5glpo, sizeof(uint16_t) * 8);
-	return (0);
-}
-
-int
-siba_sprom_get_mcs5gpo(device_t dev, uint16_t *c)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	memcpy(c, &siba->siba_sprom.mcs5gpo, sizeof(uint16_t) * 8);
-	return (0);
-}
-
-int
-siba_sprom_get_mcs5ghpo(device_t dev, uint16_t *c)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-
-	memcpy(c, &siba->siba_sprom.mcs5ghpo, sizeof(uint16_t) * 8);
-	return (0);
-}
-
-void
-siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc;
-
-	scc = &siba->siba_cc;
-
-	if (scc->scc_dev == NULL) {
-		device_printf(dev, "%s: called; no pmu\n", __func__);
-		return;
-	}
-
-	switch (siba_get_chipid(dev)) {
-	case 0x4322:
-		siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070);
-		siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a);
-		siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854);
-		if (spur_avoid == 1)
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828);
-		else
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828);
-		break;
-	case 43222:
-		if (spur_avoid == 1) {
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815);
-		} else {
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0);
-			siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855);
-		}
-		break;
-	default:
-		device_printf(dev,
-		    "%s: unknown spur avoidance settings for chip 0x%04x\n",
-		    __func__,
-		    siba_get_chipid(dev));
-		return;
-	}
-
-	/* Both chips above use the same update */
-	SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD);
-}
-
-void
-siba_cc_set32(device_t dev, uint32_t reg, uint32_t val)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc;
-
-	scc = &siba->siba_cc;
-
-	if (scc->scc_dev == NULL) {
-		device_printf(dev, "%s: called; no pmu\n", __func__);
-		return;
-	}
-
-	SIBA_CC_SET32(scc, reg, val);
-}
-
-void
-siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc;
-
-	scc = &siba->siba_cc;
-
-	if (scc->scc_dev == NULL) {
-		device_printf(dev, "%s: called; no pmu\n", __func__);
-		return;
-	}
-
-	SIBA_CC_MASK32(scc, reg, mask);
-}
-
-uint32_t
-siba_cc_read32(device_t dev, uint32_t reg)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc;
-
-	scc = &siba->siba_cc;
-
-	if (scc->scc_dev == NULL) {
-		device_printf(dev, "%s: called; no pmu\n", __func__);
-		return 0xffffffff;
-	}
-
-	return SIBA_CC_READ32(scc, reg);
-}
-
-void
-siba_cc_write32(device_t dev, uint32_t reg, uint32_t val)
-{
-	struct siba_dev_softc *sd = device_get_ivars(dev);
-	struct siba_softc *siba = sd->sd_bus;
-	struct siba_cc *scc;
-
-	scc = &siba->siba_cc;
-
-	if (scc->scc_dev == NULL) {
-		device_printf(dev, "%s: called; no pmu\n", __func__);
-		return;
-	}
-
-	SIBA_CC_WRITE32(scc, reg, val);
-}
-
diff --git a/sys/dev/siba/siba_ids.h b/sys/dev/siba/siba_ids.h
deleted file mode 100644
index d90206292ac7..000000000000
--- a/sys/dev/siba/siba_ids.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2007 Bruce M. Simpson.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _SIBA_SIBA_IDS_H_
-#define	_SIBA_SIBA_IDS_H_
-
-/*
- * Constants and structures for SiBa bus enumeration.
- */
-
-struct siba_devid {
-	uint16_t	 sd_vendor;
-	uint16_t	 sd_device;
-	uint8_t		 sd_rev;
-	char		*sd_desc;
-};
-#define	SIBA_DEV(_vendor, _cid, _rev, _msg)			\
-	{ SIBA_VID_##_vendor, SIBA_DEVID_##_cid, _rev, _msg }
-
-/*
- * Device IDs
- */
-#define SIBA_DEVID_ANY			0xffff
-#define	SIBA_DEVID_CHIPCOMMON		0x800
-#define	SIBA_DEVID_ILINE20		0x801
-#define	SIBA_DEVID_SDRAM		0x803
-#define	SIBA_DEVID_PCI			0x804
-#define	SIBA_DEVID_MIPS			0x805
-#define	SIBA_DEVID_ETHERNET		0x806
-#define	SIBA_DEVID_MODEM		0x807
-#define	SIBA_DEVID_USB11_HOSTDEV	0x808
-#define	SIBA_DEVID_ADSL			0x809
-#define	SIBA_DEVID_ILINE100		0x80a
-#define	SIBA_DEVID_IPSEC		0x80b
-#define	SIBA_DEVID_PCMCIA		0x80d
-#define	SIBA_DEVID_INTERNAL_MEM		0x80e
-#define	SIBA_DEVID_SDRAMDDR		0x80f
-#define	SIBA_DEVID_EXTIF		0x811
-#define	SIBA_DEVID_80211		0x812
-#define	SIBA_DEVID_MIPS_3302		0x816
-#define	SIBA_DEVID_USB11_HOST		0x817
-#define	SIBA_DEVID_USB11_DEV		0x818
-#define	SIBA_DEVID_USB20_HOST		0x819
-#define	SIBA_DEVID_USB20_DEV		0x81a
-#define	SIBA_DEVID_SDIO_HOST		0x81b
-#define	SIBA_DEVID_ROBOSWITCH		0x81c
-#define	SIBA_DEVID_PARA_ATA		0x81d
-#define	SIBA_DEVID_SATA_XORDMA		0x81e
-#define	SIBA_DEVID_ETHERNET_GBIT	0x81f
-#define	SIBA_DEVID_PCIE			0x820
-#define	SIBA_DEVID_MIMO_PHY		0x821
-#define	SIBA_DEVID_SRAM_CTRLR		0x822
-#define	SIBA_DEVID_MINI_MACPHY		0x823
-#define	SIBA_DEVID_ARM_1176		0x824
-#define	SIBA_DEVID_ARM_7TDMI		0x825
-
-/*
- * Vendor IDs
- */
-#define SIBA_VID_ANY		0xffff
-#define SIBA_VID_BROADCOM	0x4243
-
-/*
- * Revision IDs
- */
-#define SIBA_REV_ANY		0xff
-
-#endif /*_SIBA_SIBA_IDS_H_ */
diff --git a/sys/dev/siba/sibareg.h b/sys/dev/siba/sibareg.h
deleted file mode 100644
index bc6d0f149c02..000000000000
--- a/sys/dev/siba/sibareg.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2007 Bruce M. Simpson.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * TODO: sprom
- * TODO: implement dma translation bits (if needed for system bus)
- */
-
-#ifndef _SIBA_SIBAREG_H_
-#define	_SIBA_SIBAREG_H_
-
-#define	PCI_DEVICE_ID_BCM4401		0x4401
-#define	PCI_DEVICE_ID_BCM4401B0		0x4402
-#define	PCI_DEVICE_ID_BCM4401B1		0x170c
-#define	SIBA_PCIR_BAR			PCIR_BAR(0)
-#define	SIBA_CCID_BCM4710		0x4710
-#define	SIBA_CCID_BCM4704		0x4704
-#define	SIBA_CCID_SENTRY5		0x5365
-
-/*
- * ChipCommon registers.
- */
-#define	SIBA_CC_CHIPID			0x0000
-#define	SIBA_CC_IDMASK			0x0000ffff
-#define	SIBA_CC_ID(id)			(id & SIBA_CC_IDMASK)
-#define	SIBA_CC_REVMASK			0x000f0000
-#define	SIBA_CC_REVSHIFT		16
-#define	SIBA_CC_REV(id)							\
-	((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT)
-#define	SIBA_CC_PKGMASK			0x00F00000
-#define	SIBA_CC_PKGSHIFT		20
-#define	SIBA_CC_PKG(id)							\
-	((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT)
-#define	SIBA_CC_NCORESMASK		0x0F000000
-#define	SIBA_CC_NCORESSHIFT		24
-#define	SIBA_CC_NCORES(id)						\
-	((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT)
-#define	SIBA_CC_CAPS			0x0004
-#define	SIBA_CC_CAPS_PWCTL		0x00040000
-#define	SIBA_CC_CAPS_PMU		0x10000000	/* PMU (rev >= 20) */
-#define	SIBA_CC_CHIPCTL			0x0028		/* rev >= 11 */
-#define	SIBA_CC_CHIPSTAT		0x002C		/* rev >= 11 */
-#define	SIBA_CC_BCAST_ADDR		0x0050		/* Broadcast Address */
-#define	SIBA_CC_BCAST_DATA		0x0054		/* Broadcast Data */
-#define	SIBA_CC_PLLONDELAY		0x00B0		/* Rev >= 4 only */
-#define	SIBA_CC_FREFSELDELAY		0x00B4		/* Rev >= 4 only */
-#define	SIBA_CC_CLKSLOW			0x00b8		/* 6 <= Rev <= 9 only */
-#define	SIBA_CC_CLKSLOW_SRC		0x00000007
-#define	SIBA_CC_CLKSLOW_SRC_CRYSTAL	0x00000001
-#define	SIBA_CC_CLKSLOW_FSLOW		0x00000800
-#define	SIBA_CC_CLKSLOW_IPLL		0x00001000
-#define	SIBA_CC_CLKSLOW_ENXTAL		0x00002000
-#define	SIBA_CC_CLKSYSCTL		0x00C0		/* Rev >= 3 only */
-#define	SIBA_CC_CLKCTLSTATUS		0x01e0
-#define	SIBA_CC_CLKCTLSTATUS_HT		0x00010000
-#define	SIBA_CC_UART0			0x0300		/* offset of UART0 */
-#define	SIBA_CC_UART1			0x0400		/* offset of UART1 */
-#define	SIBA_CC_PMUCTL			0x0600		/* PMU control */
-#define	SIBA_CC_PMUCTL_PLL_UPD		0x00000400
-#define	SIBA_CC_PMUCTL_ILP		0xffff0000	/* mask */
-#define	SIBA_CC_PMUCTL_NOILP		0x00000200
-#define	SIBA_CC_PMUCTL_XF		0x0000007c	/* crystal freq */
-#define	SIBA_CC_PMUCTL_XF_VAL(id)	((id & 0x0000007c) >> 2)
-#define	SIBA_CC_PMUCAPS			0x0604
-#define	SIBA_CC_PMUCAPS_REV		0x000000ff
-#define	SIBA_CC_PMU_MINRES		0x0618
-#define	SIBA_CC_PMU_MAXRES		0x061c
-#define	SIBA_CC_PMU_TABSEL		0x0620
-#define	SIBA_CC_PMU_DEPMSK		0x0624
-#define	SIBA_CC_PMU_UPDNTM		0x0628
-#define	SIBA_CC_CHIPCTL_ADDR		0x0650
-#define	SIBA_CC_CHIPCTL_DATA		0x0654
-#define	SIBA_CC_REGCTL_ADDR		0x0658
-#define	SIBA_CC_REGCTL_DATA		0x065c
-#define	SIBA_CC_PLLCTL_ADDR		0x0660
-#define	SIBA_CC_PLLCTL_DATA		0x0664
-
-#define	SIBA_CC_PMU0_PLL0		0
-#define	SIBA_CC_PMU0_PLL0_PDIV_MSK	0x00000001
-#define	SIBA_CC_PMU0_PLL0_PDIV_FREQ	25000
-#define	SIBA_CC_PMU0_PLL1		1
-#define	SIBA_CC_PMU0_PLL1_IMSK		0xf0000000
-#define	SIBA_CC_PMU0_PLL1_FMSK		0x0fffff00
-#define	SIBA_CC_PMU0_PLL1_STOPMOD	0x00000040
-#define	SIBA_CC_PMU0_PLL2		2
-#define	SIBA_CC_PMU0_PLL2_IMSKHI	0x0000000f
-#define	SIBA_CC_PMU1_PLL0		0
-#define	SIBA_CC_PMU1_PLL0_P1DIV		0x00f00000
-#define	SIBA_CC_PMU1_PLL0_P2DIV		0x0f000000
-#define	SIBA_CC_PMU1_PLL1		1
-#define	SIBA_CC_PMU1_PLL2		2
-#define	SIBA_CC_PMU1_PLL2_NDIVMODE	0x000e0000
-#define	SIBA_CC_PMU1_PLL2_NDIVINT	0x1ff00000
-#define	SIBA_CC_PMU1_PLL3		3
-#define	SIBA_CC_PMU1_PLL3_NDIVFRAC	0x00ffffff
-#define	SIBA_CC_PMU1_PLL4		4
-#define	SIBA_CC_PMU1_PLL5		5
-#define	SIBA_CC_PMU1_PLL5_CLKDRV	0xffffff00
-
-#define	SIBA_CC_PMU0_DEFAULT_XTALFREQ	20000
-#define	SIBA_CC_PMU1_DEFAULT_FREQ	15360
-
-#define	SIBA_CC_PMU1_PLLTAB_ENTRY					\
-{									\
-	{ 12000,  1, 3, 22,  0x9, 0xffffef },				\
-	{ 13000,  2, 1,  6,  0xb, 0x483483 },				\
-	{ 14400,  3, 1, 10,  0xa, 0x1c71c7 },				\
-	{ 15360,  4, 1,  5,  0xb, 0x755555 },				\
-	{ 16200,  5, 1, 10,  0x5, 0x6e9e06 },				\
-	{ 16800,  6, 1, 10,  0x5, 0x3cf3cf },				\
-	{ 19200,  7, 1,  9,  0x5, 0x17b425 },				\
-	{ 19800,  8, 1, 11,  0x4, 0xa57eb },				\
-	{ 20000,  9, 1, 11,  0x4, 0 },					\
-	{ 24000, 10, 3, 11,  0xa, 0 },					\
-	{ 25000, 11, 5, 16,  0xb, 0 },					\
-	{ 26000, 12, 1,  2, 0x10, 0xec4ec4 },				\
-	{ 30000, 13, 3,  8,  0xb, 0 },					\
-	{ 38400, 14, 1,  5,  0x4, 0x955555 },				\
-	{ 40000, 15, 1,  2,  0xb, 0 }					\
-}
-
-#define	SIBA_CC_PMU0_PLLTAB_ENTRY					\
-{									\
-	{ 12000,  1, 73, 349525, }, { 13000,  2, 67, 725937, },		\
-	{ 14400,  3, 61, 116508, }, { 15360,  4, 57, 305834, },		\
-	{ 16200,  5, 54, 336579, }, { 16800,  6, 52, 399457, },		\
-	{ 19200,  7, 45, 873813, }, { 19800,  8, 44, 466033, },		\
-	{ 20000,  9, 44, 0,      }, { 25000, 10, 70, 419430, },		\
-	{ 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, },		\
-	{ 38400, 13, 45, 873813, }, { 40000, 14, 45, 0,      },		\
-}
-
-#define	SIBA_CC_PMU_4312_PA_REF		2
-#define	SIBA_CC_PMU_4325_BURST		1
-#define	SIBA_CC_PMU_4325_CLBURST	3
-#define	SIBA_CC_PMU_4325_LN		10
-#define	SIBA_CC_PMU_4325_CRYSTAL	13
-#define	SIBA_CC_PMU_4325_RX_PWR		15
-#define	SIBA_CC_PMU_4325_TX_PWR		16
-#define	SIBA_CC_PMU_4325_LOGEN_PWR	18
-#define	SIBA_CC_PMU_4325_AFE_PWR	19
-#define	SIBA_CC_PMU_4325_BBPLL_PWR	20
-#define	SIBA_CC_PMU_4325_HT		21
-#define	SIBA_CC_PMU_4328_EXT_SWITCH_PWM	0
-#define	SIBA_CC_PMU_4328_BB_SWITCH_PWM	1
-#define	SIBA_CC_PMU_4328_BB_SWITCH_BURST	2
-#define	SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST	3
-#define	SIBA_CC_PMU_4328_ILP_REQUEST	4
-#define	SIBA_CC_PMU_4328_RADSWITCH_PWM	5	/* radio switch */
-#define	SIBA_CC_PMU_4328_RADSWITCH_BURST	6
-#define	SIBA_CC_PMU_4328_ROM_SWITCH	7
-#define	SIBA_CC_PMU_4328_PA_REF		8
-#define	SIBA_CC_PMU_4328_RADIO		9
-#define	SIBA_CC_PMU_4328_AFE		10
-#define	SIBA_CC_PMU_4328_PLL		11
-#define	SIBA_CC_PMU_4328_BG_FILTBYP	12
-#define	SIBA_CC_PMU_4328_TX_FILTBYP	13
-#define	SIBA_CC_PMU_4328_RX_FILTBYP	14
-#define	SIBA_CC_PMU_4328_CRYSTAL_PU	15
-#define	SIBA_CC_PMU_4328_CRYSTAL_EN	16
-#define	SIBA_CC_PMU_4328_BB_PLL_FILTBYP	17
-#define	SIBA_CC_PMU_4328_RF_PLL_FILTBYP	18
-#define	SIBA_CC_PMU_4328_BB_PLL_PU	19
-#define	SIBA_CC_PMU_5354_PA_REF		8
-#define	SIBA_CC_PMU_5354_BB_PLL_PU	19
-
-#define	SIBA_CC_PMU_4325_RES_UPDOWN					\
-{									\
-	{ SIBA_CC_PMU_4325_CRYSTAL, 0x1501 }				\
-}
-
-#define	SIBA_CC_PMU_4325_RES_DEPEND					\
-{									\
-	{ SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD,			\
-	  ((1 << SIBA_CC_PMU_4325_RX_PWR) |				\
-	   (1 << SIBA_CC_PMU_4325_TX_PWR) |				\
-	   (1 << SIBA_CC_PMU_4325_LOGEN_PWR) |				\
-	   (1 << SIBA_CC_PMU_4325_AFE_PWR)) }				\
-}
-
-#define	SIBA_CC_PMU_4328_RES_UPDOWN					\
-{									\
-	{ SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 },			\
-	{ SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f },			\
-	{ SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 },		\
-	{ SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 },			\
-	{ SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 },			\
-	{ SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 },			\
-	{ SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_PA_REF, 0x0f01 },				\
-	{ SIBA_CC_PMU_4328_RADIO, 0x0f01 },				\
-	{ SIBA_CC_PMU_4328_AFE, 0x0f01 },				\
-	{ SIBA_CC_PMU_4328_PLL, 0x0f01 },				\
-	{ SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 },			\
-	{ SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 },			\
-	{ SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 },				\
-}
-
-#define	SIBA_CC_PMU_4328_RES_DEPEND					\
-{									\
-	{ SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET,		\
-	  ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) |			\
-	   (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) },			\
-}
-
-#define	SIBA_CC_CHST_4325_PMUTOP_2B	0x00000200
-
-#define	SIBA_BAR0			0x80
-#define	SIBA_IRQMASK			0x94
-#define	SIBA_GPIO_IN			0xb0
-#define	SIBA_GPIO_OUT			0xb4
-#define	SIBA_GPIO_OUT_EN		0xb8
-#define	SIBA_GPIO_CRYSTAL		0x40
-#define	SIBA_GPIO_PLL			0x80
-
-#define	SIBA_REGWIN(x)							\
-	(SIBA_ENUM_START + ((x) * SIBA_CORE_LEN))
-#define	SIBA_CORE_LEN		0x00001000	/* Size of cfg per core */
-#define	SIBA_CFG_END		0x00010000	/* Upper bound of cfg space */
-#define	SIBA_MAX_CORES		(SIBA_CFG_END/SIBA_CORE_LEN)	/* #max cores */
-#define	SIBA_ENUM_START			0x18000000U
-#define	SIBA_ENUM_END			0x18010000U
-
-#define	SIBA_DMA_TRANSLATION_MASK	0xc0000000
-
-#define	SIBA_PCI_DMA			0x40000000U
-#define	SIBA_TPS			0x0f18
-#define	SIBA_TPS_BPFLAG			0x0000003f
-#define	SIBA_IAS			0x0f90     /* Initiator Agent State */
-#define	SIBA_IAS_INBAND_ERR		0x00020000
-#define	SIBA_IAS_TIMEOUT		0x00040000
-#define	SIBA_INTR_MASK			0x0f94
-#define	SIBA_TGSLOW			0x0f98
-#define	SIBA_TGSLOW_RESET		0x00000001	/* target state low */
-#define	SIBA_TGSLOW_REJECT_22		0x00000002
-#define	SIBA_TGSLOW_REJECT_23		0x00000004
-#define	SIBA_TGSLOW_CLOCK		0x00010000
-#define	SIBA_TGSLOW_FGC			0x00020000
-#define	SIBA_TGSHIGH			0x0f9c
-#define	SIBA_TGSHIGH_SERR		0x00000001
-#define	SIBA_TGSHIGH_BUSY		0x00000004
-#define	SIBA_TGSHIGH_DMA64		0x10000000
-#define	SIBA_IMCFGLO			0x0fa8
-#define	SIBA_IMCFGLO_SERTO		0x00000007
-#define	SIBA_IMCFGLO_REQTO		0x00000070
-#define	SIBA_IDLOW			0x0ff8
-#define	SIBA_IDLOW_SSBREV		0xf0000000
-#define	SIBA_IDLOW_SSBREV_22		0x00000000
-#define	SIBA_IDLOW_SSBREV_23		0x10000000
-#define	SIBA_IDLOW_SSBREV_24		0x40000000
-#define	SIBA_IDLOW_SSBREV_25		0x50000000
-#define	SIBA_IDLOW_SSBREV_26		0x60000000
-#define	SIBA_IDLOW_SSBREV_27		0x70000000
-#define	SIBA_IDHIGH			0x0ffc
-#define	SIBA_IDHIGH_CORECODEMASK	0x00008FF0 /* Core Code */
-#define	SIBA_IDHIGH_CORECODE_SHIFT	4
-#define	SIBA_IDHIGH_CORECODE(id)					\
-	((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT)
-/* Revision Code (low part) */
-#define	SIBA_IDHIGH_REVLO		0x0000000f
-/* Revision Code (high part) */
-#define	SIBA_IDHIGH_REVHI		0x00007000
-#define	SIBA_IDHIGH_REVHI_SHIFT	8
-#define	SIBA_IDHIGH_REV(id)						\
-	((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >>	\
-	  	 SIBA_IDHIGH_REVHI_SHIFT))
-#define	SIBA_IDHIGH_VENDORMASK		0xFFFF0000 /* Vendor Code */
-#define	SIBA_IDHIGH_VENDOR_SHIFT	16
-#define	SIBA_IDHIGH_VENDOR(id)						\
-	((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT)
-
-#define	SIBA_SPROMSIZE_R123		64
-#define	SIBA_SPROMSIZE_R4		220
-#define	SIBA_SPROM_BASE			0x1000
-#define	SIBA_SPROM_REV_CRC		0xff00
-
-#define	SIBA_SPROM1_MAC_80211BG		0x1048
-#define	SIBA_SPROM1_MAC_ETH		0x104e
-#define	SIBA_SPROM1_MAC_80211A		0x1054
-#define	SIBA_SPROM1_ETHPHY		0x105a
-#define	SIBA_SPROM1_ETHPHY_MII_ETH0	0x001f
-#define	SIBA_SPROM1_ETHPHY_MII_ETH1	0x03e0
-#define	SIBA_SPROM1_ETHPHY_MDIO_ETH0	(1 << 14)
-#define	SIBA_SPROM1_ETHPHY_MDIO_ETH1	(1 << 15)
-#define	SIBA_SPROM1_BOARDINFO		0x105c
-#define	SIBA_SPROM1_BOARDINFO_BREV	0x00ff
-#define	SIBA_SPROM1_BOARDINFO_CCODE	0x0f00
-#define	SIBA_SPROM1_BOARDINFO_ANTBG	0x3000
-#define	SIBA_SPROM1_BOARDINFO_ANTA	0xc000
-#define	SIBA_SPROM1_PA0B0		0x105e
-#define	SIBA_SPROM1_PA0B1		0x1060
-#define	SIBA_SPROM1_PA0B2		0x1062
-#define	SIBA_SPROM1_GPIOA		0x1064
-#define	SIBA_SPROM1_GPIOA_P0		0x00ff
-#define	SIBA_SPROM1_GPIOA_P1		0xff00
-#define	SIBA_SPROM1_GPIOB		0x1066
-#define	SIBA_SPROM1_GPIOB_P2		0x00ff
-#define	SIBA_SPROM1_GPIOB_P3		0xff00
-#define	SIBA_SPROM1_MAXPWR		0x1068
-#define	SIBA_SPROM1_MAXPWR_BG		0x00ff
-#define	SIBA_SPROM1_MAXPWR_A		0xff00
-#define	SIBA_SPROM1_PA1B0		0x106a
-#define	SIBA_SPROM1_PA1B1		0x106c
-#define	SIBA_SPROM1_PA1B2		0x106e
-#define	SIBA_SPROM1_TSSI		0x1070
-#define	SIBA_SPROM1_TSSI_BG		0x00ff
-#define	SIBA_SPROM1_TSSI_A		0xff00
-#define	SIBA_SPROM1_BFLOW		0x1072
-#define	SIBA_SPROM1_AGAIN		0x1074
-#define	SIBA_SPROM1_AGAIN_BG		0x00ff
-#define	SIBA_SPROM1_AGAIN_A		0xff00
-
-#define	SIBA_SPROM2_BFHIGH		0x1038
-
-#define	SIBA_SPROM3_MAC_80211BG		0x104a
-
-#define	SIBA_SPROM4_MAC_80211BG		0x104c
-#define	SIBA_SPROM4_ETHPHY		0x105a
-#define	SIBA_SPROM4_ETHPHY_ET0A		0x001f
-#define	SIBA_SPROM4_ETHPHY_ET1A		0x03e0
-#define	SIBA_SPROM4_CCODE		0x1052
-#define	SIBA_SPROM4_ANTAVAIL		0x105d
-#define	SIBA_SPROM4_ANTAVAIL_A		0x00ff
-#define	SIBA_SPROM4_ANTAVAIL_BG		0xff00
-#define	SIBA_SPROM4_BFLOW		0x1044
-#define	SIBA_SPROM4_AGAIN01		0x105e
-#define	SIBA_SPROM4_AGAIN0		0x00ff
-#define	SIBA_SPROM4_AGAIN1		0xff00
-#define	SIBA_SPROM4_AGAIN23		0x1060
-#define	SIBA_SPROM4_AGAIN2		0x00ff
-#define	SIBA_SPROM4_AGAIN3		0xff00
-#define	SIBA_SPROM4_TXPID2G01		0x0062
-#define	 SIBA_SPROM4_TXPID2G0		0x00ff
-#define	 SIBA_SPROM4_TXPID2G1		0xff00
-#define	SIBA_SPROM4_TXPID2G23		0x0064
-#define	 SIBA_SPROM4_TXPID2G2		0x00ff
-#define	 SIBA_SPROM4_TXPID2G3		0xff00
-#define	SIBA_SPROM4_TXPID5G01		0x0066
-#define	 SIBA_SPROM4_TXPID5G0		0x00ff
-#define	 SIBA_SPROM4_TXPID5G1		0xff00
-#define	SIBA_SPROM4_TXPID5G23		0x0068
-#define	 SIBA_SPROM4_TXPID5G2		0x00ff
-#define	 SIBA_SPROM4_TXPID5G3		0xff00
-#define	SIBA_SPROM4_TXPID5GL01		0x006a
-#define	 SIBA_SPROM4_TXPID5GL0		0x00ff
-#define	 SIBA_SPROM4_TXPID5GL1		0xff00
-#define	SIBA_SPROM4_TXPID5GL23		0x006c
-#define	 SIBA_SPROM4_TXPID5GL2		0x00ff
-#define	 SIBA_SPROM4_TXPID5GL3		0xff00
-#define	SIBA_SPROM4_TXPID5GH01		0x006e
-#define	 SIBA_SPROM4_TXPID5GH0		0x00ff
-#define	 SIBA_SPROM4_TXPID5GH1		0xff00
-#define	SIBA_SPROM4_TXPID5GH23		0x0070
-#define	 SIBA_SPROM4_TXPID5GH2		0x00ff
-#define	 SIBA_SPROM4_TXPID5GH3		0xff00
-#define	SIBA_SPROM4_BFHIGH		0x1046
-#define	SIBA_SPROM4_MAXP_BG		0x1080
-#define	SIBA_SPROM4_MAXP_BG_MASK	0x00ff
-#define	SIBA_SPROM4_TSSI_BG		0xff00
-#define	SIBA_SPROM4_MAXP_A		0x108a
-#define	SIBA_SPROM4_MAXP_A_MASK		0x00ff
-#define	SIBA_SPROM4_TSSI_A		0xff00
-#define	SIBA_SPROM4_GPIOA		0x1056
-#define	SIBA_SPROM4_GPIOA_P0		0x00ff
-#define	SIBA_SPROM4_GPIOA_P1		0xff00
-#define	SIBA_SPROM4_GPIOB		0x1058
-#define	SIBA_SPROM4_GPIOB_P2		0x00ff
-#define	SIBA_SPROM4_GPIOB_P3		0xff00
-
-/* The following four blocks share the same structure */
-#define	SIBA_SPROM4_PWR_INFO_CORE0	0x1080
-#define	SIBA_SPROM4_PWR_INFO_CORE1	0x10AE
-#define	SIBA_SPROM4_PWR_INFO_CORE2	0x10DC
-#define	SIBA_SPROM4_PWR_INFO_CORE3	0x110A
-
-#define	SIBA_SPROM4_2G_MAXP_ITSSI	0x00    /* 2 GHz ITSSI and 2 GHz Max Power */
-#define	 SIBA_SPROM4_2G_MAXP		0x00FF
-#define	 SIBA_SPROM4_2G_ITSSI		0xFF00
-#define	 SIBA_SPROM4_2G_ITSSI_SHIFT	8
-#define	SIBA_SPROM4_2G_PA_0		0x02    /* 2 GHz power amp */
-#define	SIBA_SPROM4_2G_PA_1		0x04
-#define	SIBA_SPROM4_2G_PA_2		0x06
-#define	SIBA_SPROM4_2G_PA_3		0x08
-#define	SIBA_SPROM4_5G_MAXP_ITSSI	0x0A    /* 5 GHz ITSSI and 5.3 GHz Max Power */
-#define	 SIBA_SPROM4_5G_MAXP		0x00FF
-#define	 SIBA_SPROM4_5G_ITSSI		0xFF00
-#define	 SIBA_SPROM4_5G_ITSSI_SHIFT	8
-#define	SIBA_SPROM4_5GHL_MAXP		0x0C    /* 5.2 GHz and 5.8 GHz Max Power */
-#define	 SIBA_SPROM4_5GH_MAXP		0x00FF
-#define	 SIBA_SPROM4_5GL_MAXP		0xFF00
-#define	 SIBA_SPROM4_5GL_MAXP_SHIFT	8
-#define	SIBA_SPROM4_5G_PA_0		0x0E    /* 5.3 GHz power amp */
-#define	SIBA_SPROM4_5G_PA_1		0x10
-#define	SIBA_SPROM4_5G_PA_2		0x12
-#define	SIBA_SPROM4_5G_PA_3		0x14
-#define	SIBA_SPROM4_5GL_PA_0		0x16    /* 5.2 GHz power amp */
-#define	SIBA_SPROM4_5GL_PA_1		0x18
-#define	SIBA_SPROM4_5GL_PA_2		0x1A
-#define	SIBA_SPROM4_5GL_PA_3		0x1C
-#define	SIBA_SPROM4_5GH_PA_0		0x1E    /* 5.8 GHz power amp */
-#define	SIBA_SPROM4_5GH_PA_1		0x20
-#define	SIBA_SPROM4_5GH_PA_2		0x22
-#define	SIBA_SPROM4_5GH_PA_3		0x24
-
-#define	SIBA_SPROM5_BFLOW		0x104a
-#define	SIBA_SPROM5_BFHIGH		0x104c
-#define	SIBA_SPROM5_MAC_80211BG		0x1052
-#define	SIBA_SPROM5_CCODE		0x1044
-#define	SIBA_SPROM5_GPIOA		0x1076
-#define	SIBA_SPROM5_GPIOA_P0		0x00ff
-#define	SIBA_SPROM5_GPIOA_P1		0xff00
-#define	SIBA_SPROM5_GPIOB		0x1078
-#define	SIBA_SPROM5_GPIOB_P2		0x00ff
-#define	SIBA_SPROM5_GPIOB_P3		0xff00
-
-#define	SIBA_SPROM8_BFLOW		0x1084
-#define	SIBA_SPROM8_BFHIGH		0x1086
-#define	SIBA_SPROM8_BFL2LO		0x1088
-#define	SIBA_SPROM8_BFL2HI		0x108a
-#define	SIBA_SPROM8_MAC_80211BG		0x108c
-#define	SIBA_SPROM8_CCODE		0x1092
-#define	SIBA_SPROM8_ANTAVAIL		0x109c
-#define	SIBA_SPROM8_ANTAVAIL_A		0xff00
-#define	SIBA_SPROM8_ANTAVAIL_BG		0x00ff
-#define	SIBA_SPROM8_AGAIN01		0x109e
-#define	SIBA_SPROM8_AGAIN0		0x00ff
-#define	SIBA_SPROM8_AGAIN1		0xff00
-#define	SIBA_SPROM8_GPIOA		0x1096
-#define	SIBA_SPROM8_GPIOA_P0		0x00ff
-#define	SIBA_SPROM8_GPIOA_P1		0xff00
-#define	SIBA_SPROM8_GPIOB		0x1098
-#define	SIBA_SPROM8_GPIOB_P2		0x00ff
-#define	SIBA_SPROM8_GPIOB_P3		0xff00
-#define	SIBA_SPROM8_AGAIN23		0x10a0
-#define	SIBA_SPROM8_AGAIN2		0x00ff
-#define	SIBA_SPROM8_AGAIN3		0xff00
-#define	SIBA_SPROM8_RSSIPARM2G		0x10a4
-#define	SIBA_SPROM8_RSSISMF2G		0x000f
-#define	SIBA_SPROM8_RSSISMC2G		0x00f0
-#define	SIBA_SPROM8_RSSISAV2G		0x0700	/* BITMASK */
-#define	SIBA_SPROM8_BXA2G		0x1800	/* BITMASK */
-#define	SIBA_SPROM8_RSSIPARM5G		0x10a6
-#define	SIBA_SPROM8_RSSISMF5G		0x000f
-#define	SIBA_SPROM8_RSSISMC5G		0x00f0
-#define	SIBA_SPROM8_RSSISAV5G		0x0700	/* BITMASK */
-#define	SIBA_SPROM8_BXA5G		0x1800	/* BITMASK */
-#define	SIBA_SPROM8_TRI25G		0x10a8
-#define	SIBA_SPROM8_TRI2G		0x00ff
-#define	SIBA_SPROM8_TRI5G		0xff00
-#define	SIBA_SPROM8_TRI5GHL		0x10aa
-#define	SIBA_SPROM8_TRI5GL		0x00ff
-#define	SIBA_SPROM8_TRI5GH		0xff00
-#define	SIBA_SPROM8_RXPO		0x10ac
-#define	SIBA_SPROM8_RXPO2G		0x00ff
-#define	SIBA_SPROM8_RXPO5G		0xff00
-
-/* The FEM blocks share the same structure */
-#define	SIBA_SPROM8_FEM2G		0x10ae
-#define	SIBA_SPROM8_FEM5G		0x10b0
-#define	 SIBA_SROM8_FEM_TSSIPOS		0x0001
-#define	 SIBA_SROM8_FEM_EXTPA_GAIN	0x0006
-#define	 SIBA_SROM8_FEM_PDET_RANGE	0x00F8
-#define	 SIBA_SROM8_FEM_TR_ISO		0x0700
-#define	 SIBA_SROM8_FEM_ANTSWLUT	0xF800
-
-#define	SIBA_SPROM8_MAXP_BG		0x10c0
-#define	SIBA_SPROM8_MAXP_BG_MASK	0x00ff
-#define	SIBA_SPROM8_TSSI_BG		0xff00
-#define	SIBA_SPROM8_PA0B0		0x10c2
-#define	SIBA_SPROM8_PA0B1		0x10c4
-#define	SIBA_SPROM8_PA0B2		0x10c6
-#define	SIBA_SPROM8_MAXP_A		0x10c8
-#define	SIBA_SPROM8_MAXP_A_MASK		0x00ff
-#define	SIBA_SPROM8_TSSI_A		0xff00
-#define	SIBA_SPROM8_MAXP_AHL		0x10ca
-#define	SIBA_SPROM8_MAXP_AH_MASK	0x00ff
-#define	SIBA_SPROM8_MAXP_AL_MASK	0xff00
-#define	SIBA_SPROM8_PA1B0		0x10cc
-#define	SIBA_SPROM8_PA1B1		0x10ce
-#define	SIBA_SPROM8_PA1B2		0x10d0
-#define	SIBA_SPROM8_PA1LOB0		0x10d2
-#define	SIBA_SPROM8_PA1LOB1		0x10d4
-#define	SIBA_SPROM8_PA1LOB2		0x10d6
-#define	SIBA_SPROM8_PA1HIB0		0x10d8
-#define	SIBA_SPROM8_PA1HIB1		0x10da
-#define	SIBA_SPROM8_PA1HIB2		0x10dc
-#define	SIBA_SPROM8_CCK2GPO		0x1140
-#define	SIBA_SPROM8_OFDM2GPO		0x1142
-#define	SIBA_SPROM8_OFDM5GPO		0x1146
-#define	SIBA_SPROM8_OFDM5GLPO		0x114a
-#define	SIBA_SPROM8_OFDM5GHPO		0x114e
-#define	SIBA_SPROM8_CDDPO		0x0192
-#define	SIBA_SPROM8_STBCPO		0x0194
-#define	SIBA_SPROM8_BW40PO		0x0196
-#define	SIBA_SPROM8_BWDUPPO		0x0198
-
-/* There are 4 blocks with power info sharing the same layout */
-#define	SIBA_SROM8_PWR_INFO_CORE0	0x10C0
-#define	SIBA_SROM8_PWR_INFO_CORE1	0x10E0
-#define	SIBA_SROM8_PWR_INFO_CORE2	0x1100
-#define	SIBA_SROM8_PWR_INFO_CORE3	0x1120
-
-#define	SIBA_SROM8_2G_MAXP_ITSSI	0x00
-#define	 SIBA_SPROM8_2G_MAXP		0x00FF
-#define	 SIBA_SPROM8_2G_ITSSI		0xFF00
-#define	 SIBA_SPROM8_2G_ITSSI_SHIFT	8
-#define	SIBA_SROM8_2G_PA_0		0x02    /* 2GHz power amp settings */
-#define	SIBA_SROM8_2G_PA_1		0x04
-#define	SIBA_SROM8_2G_PA_2		0x06
-#define	SIBA_SROM8_5G_MAXP_ITSSI	0x08    /* 5GHz ITSSI and 5.3GHz Max Power */
-#define	 SIBA_SPROM8_5G_MAXP		0x00FF
-#define	 SIBA_SPROM8_5G_ITSSI		0xFF00
-#define	 SIBA_SPROM8_5G_ITSSI_SHIFT	8
-#define	SIBA_SPROM8_5GHL_MAXP		0x0A    /* 5.2GHz and 5.8GHz Max Power */
-#define	 SIBA_SPROM8_5GH_MAXP		0x00FF
-#define	 SIBA_SPROM8_5GL_MAXP		0xFF00
-#define	 SIBA_SPROM8_5GL_MAXP_SHIFT	8
-#define	SIBA_SROM8_5G_PA_0		0x0C    /* 5.3GHz power amp settings */
-#define	SIBA_SROM8_5G_PA_1		0x0E
-#define	SIBA_SROM8_5G_PA_2		0x10
-#define	SIBA_SROM8_5GL_PA_0		0x12    /* 5.2GHz power amp settings */
-#define	SIBA_SROM8_5GL_PA_1		0x14
-#define	SIBA_SROM8_5GL_PA_2		0x16
-#define	SIBA_SROM8_5GH_PA_0		0x18    /* 5.8GHz power amp settings */
-#define	SIBA_SROM8_5GH_PA_1		0x1A
-#define	SIBA_SROM8_5GH_PA_2		0x1C
-
-#define	SIBA_BOARDVENDOR_DELL		0x1028
-#define	SIBA_BOARDVENDOR_BCM		0x14e4
-#define	SIBA_BOARD_BCM4309G		0x0421
-#define	SIBA_BOARD_MP4318		0x044a
-#define	SIBA_BOARD_BU4306		0x0416
-#define	SIBA_BOARD_BU4309		0x040a
-#define	SIBA_BOARD_BCM4321		0x046d
-
-#define	SIBA_PCICORE_BCAST_ADDR		SIBA_CC_BCAST_ADDR
-#define	SIBA_PCICORE_BCAST_DATA		SIBA_CC_BCAST_DATA
-#define	SIBA_PCICORE_SBTOPCI0		0x0100
-#define	SIBA_PCICORE_SBTOPCI1		0x0104
-#define	SIBA_PCICORE_SBTOPCI2		0x0108
-#define	SIBA_PCICORE_MDIO_CTL		0x0128
-#define	SIBA_PCICORE_MDIO_DATA		0x012c
-#define	SIBA_PCICORE_SBTOPCI_PREF	0x00000004
-#define	SIBA_PCICORE_SBTOPCI_BURST	0x00000008
-#define	SIBA_PCICORE_SBTOPCI_MRM	0x00000020
-
-#define	SIBA_CHIPPACK_BCM4712S     1       /* Small 200pin 4712 */
-
-#endif /* _SIBA_SIBAREG_H_ */
diff --git a/sys/dev/siba/sibavar.h b/sys/dev/siba/sibavar.h
deleted file mode 100644
index b3bda80683f3..000000000000
--- a/sys/dev/siba/sibavar.h
+++ /dev/null
@@ -1,676 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2007 Bruce M. Simpson.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _SIBA_SIBAVAR_H_
-#define _SIBA_SIBAVAR_H_
-
-#include <sys/rman.h>
-
-struct siba_softc;
-struct siba_dev_softc;
-
-enum siba_type {
-	SIBA_TYPE_SSB,
-	SIBA_TYPE_PCI,
-	SIBA_TYPE_PCMCIA,
-};
-
-enum siba_device_ivars {
-	SIBA_IVAR_VENDOR,
-	SIBA_IVAR_DEVICE,
-	SIBA_IVAR_REVID,
-	SIBA_IVAR_CORE_INDEX,
-	SIBA_IVAR_PCI_VENDOR,
-	SIBA_IVAR_PCI_DEVICE,
-	SIBA_IVAR_PCI_SUBVENDOR,
-	SIBA_IVAR_PCI_SUBDEVICE,
-	SIBA_IVAR_PCI_REVID,
-	SIBA_IVAR_CHIPID,
-	SIBA_IVAR_CHIPREV,
-	SIBA_IVAR_CHIPPKG,
-	SIBA_IVAR_TYPE,
-	SIBA_IVAR_CC_PMUFREQ,
-	SIBA_IVAR_CC_CAPS,
-	SIBA_IVAR_CC_POWERDELAY,
-	SIBA_IVAR_PCICORE_REVID
-};
-
-#define	SIBA_ACCESSOR(var, ivar, type)				\
-	__BUS_ACCESSOR(siba, var, SIBA, ivar, type)
-
-SIBA_ACCESSOR(vendor,		VENDOR,		uint16_t)
-SIBA_ACCESSOR(device,		DEVICE,		uint16_t)
-SIBA_ACCESSOR(revid,		REVID,		uint8_t)
-SIBA_ACCESSOR(core_index,	CORE_INDEX,	uint8_t)
-SIBA_ACCESSOR(pci_vendor,	PCI_VENDOR,	uint16_t)
-SIBA_ACCESSOR(pci_device,	PCI_DEVICE,	uint16_t)
-SIBA_ACCESSOR(pci_subvendor,	PCI_SUBVENDOR,	uint16_t)
-SIBA_ACCESSOR(pci_subdevice,	PCI_SUBDEVICE,	uint16_t)
-SIBA_ACCESSOR(pci_revid,	PCI_REVID,	uint8_t)
-SIBA_ACCESSOR(chipid,		CHIPID,		uint16_t)
-SIBA_ACCESSOR(chiprev,		CHIPREV,	uint16_t)
-SIBA_ACCESSOR(chippkg,		CHIPPKG,	uint8_t)
-SIBA_ACCESSOR(type,		TYPE,		enum siba_type)
-SIBA_ACCESSOR(cc_pmufreq,	CC_PMUFREQ,	uint32_t)
-SIBA_ACCESSOR(cc_caps,		CC_CAPS,	uint32_t)
-SIBA_ACCESSOR(cc_powerdelay,	CC_POWERDELAY,	uint16_t)
-SIBA_ACCESSOR(pcicore_revid,	PCICORE_REVID,	uint8_t)
-
-#undef SIBA_ACCESSOR
-
-/* XXX just for SPROM1? */
-enum {
-	SIBA_CCODE_WORLD,
-	SIBA_CCODE_THAILAND,
-	SIBA_CCODE_ISRAEL,
-	SIBA_CCODE_JORDAN,
-	SIBA_CCODE_CHINA,
-	SIBA_CCODE_JAPAN,
-	SIBA_CCODE_USA_CANADA_ANZ,
-	SIBA_CCODE_EUROPE,
-	SIBA_CCODE_USA_LOW,
-	SIBA_CCODE_JAPAN_HIGH,
-	SIBA_CCODE_ALL,
-	SIBA_CCODE_NONE,
-};
-
-#define siba_mips_read_2(sc, core, reg)				\
-	bus_space_read_2((sc)->siba_mem_bt, (sc)->siba_mem_bh,	\
-			 (core * SIBA_CORE_LEN) + (reg))
-
-#define siba_mips_read_4(sc, core, reg)				\
-	bus_space_read_4((sc)->siba_mem_bt, (sc)->siba_mem_bh,	\
-			 (core * SIBA_CORE_LEN) + (reg))
-
-#define siba_mips_write_2(sc, core, reg, val)			\
-	bus_space_write_2((sc)->siba_mem_bt, (sc)->siba_mem_bh,	\
-			 (core * SIBA_CORE_LEN) + (reg), (val))
-
-#define siba_mips_write_4(sc, core, reg, val)			\
-	bus_space_write_4((sc)->siba_mem_bt, (sc)->siba_mem_bh,	\
-			 (core * SIBA_CORE_LEN) + (reg), (val))
-
-#define	SIBA_READ_4(siba, reg)		\
-	bus_space_read_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
-#define	SIBA_READ_2(siba, reg)		\
-	bus_space_read_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
-#define	SIBA_READ_MULTI_1(siba, reg, addr, count)			\
-	bus_space_read_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
-	    (reg), (addr), (count))
-#define	SIBA_READ_MULTI_2(siba, reg, addr, count)			\
-	bus_space_read_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
-	    (reg), (addr), (count))
-#define	SIBA_READ_MULTI_4(siba, reg, addr, count)			\
-	bus_space_read_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
-	    (reg), (addr), (count))
-
-#define	SIBA_WRITE_4(siba, reg, val)	\
-	bus_space_write_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,	\
-	    (reg), (val))
-#define	SIBA_WRITE_2(siba, reg, val)	\
-	bus_space_write_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,	\
-	    (reg), (val))
-#define	SIBA_WRITE_MULTI_1(siba, reg, addr, count)			\
-	bus_space_write_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
-	    (reg), (addr), (count))
-#define	SIBA_WRITE_MULTI_2(siba, reg, addr, count)			\
-	bus_space_write_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
-	    (reg), (addr), (count))
-#define	SIBA_WRITE_MULTI_4(siba, reg, addr, count)			\
-	bus_space_write_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
-	    (reg), (addr), (count))
-
-#define	SIBA_BARRIER(siba, flags)					\
-	bus_space_barrier((siba)->siba_mem_bt, (siba)->siba_mem_bh, (0),\
-	    (0), (flags))
-
-#define	SIBA_SETBITS_4(siba, reg, bits)	\
-	SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) | (bits))
-#define	SIBA_SETBITS_2(siba, reg, bits)	\
-	SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) | (bits))
-
-#define	SIBA_FILT_SETBITS_4(siba, reg, filt, bits) \
-	SIBA_WRITE_4((siba), (reg), (SIBA_READ_4((siba),	\
-	    (reg)) & (filt)) | (bits))
-#define	SIBA_FILT_SETBITS_2(siba, reg, filt, bits)	\
-	SIBA_WRITE_2((siba), (reg), (SIBA_READ_2((siba),	\
-	    (reg)) & (filt)) | (bits))
-
-#define	SIBA_CLRBITS_4(siba, reg, bits)	\
-	SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) & ~(bits))
-#define	SIBA_CLRBITS_2(siba, reg, bits)	\
-	SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits))
-
-#define	SIBA_CC_READ32(scc, offset) \
-	siba_read_4_sub((scc)->scc_dev, offset)
-#define	SIBA_CC_WRITE32(scc, offset, val) \
-	siba_write_4_sub((scc)->scc_dev, offset, val)
-#define	SIBA_CC_MASK32(scc, offset, mask) \
-	SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) & (mask))
-#define	SIBA_CC_SET32(scc, offset, set) \
-	SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) | (set))
-#define	SIBA_CC_MASKSET32(scc, offset, mask, set)	\
-	SIBA_CC_WRITE32(scc, offset,			\
-	    (SIBA_CC_READ32(scc, offset) & (mask)) | (set))
-
-enum siba_clock {
-	SIBA_CLOCK_DYNAMIC,
-	SIBA_CLOCK_SLOW,
-	SIBA_CLOCK_FAST,
-};
-
-enum siba_clksrc {
-	SIBA_CC_CLKSRC_PCI,
-	SIBA_CC_CLKSRC_CRYSTAL,
-	SIBA_CC_CLKSRC_LOWPW,
-};
-
-struct siba_cc_pmu0_plltab {
-	uint16_t		freq;	/* in kHz.*/
-	uint8_t			xf;	/* crystal frequency */
-	uint8_t			wb_int;
-	uint32_t		wb_frac;
-};
-
-struct siba_cc_pmu1_plltab {
-	uint16_t		freq;
-	uint8_t			xf;
-	uint8_t			p1div;
-	uint8_t			p2div;
-	uint8_t			ndiv_int;
-	uint32_t		ndiv_frac;
-};
-
-struct siba_cc_pmu_res_updown {
-	uint8_t			res;
-	uint16_t		updown;
-};
-
-#define	SIBA_CC_PMU_DEP_SET	1
-#define	SIBA_CC_PMU_DEP_ADD	2
-#define	SIBA_CC_PMU_DEP_REMOVE	3
-
-struct siba_cc_pmu_res_depend {
-	uint8_t			res;
-	uint8_t			task;
-	uint32_t		depend;
-};
-
-enum siba_sprom_vars {
-	SIBA_SPROMVAR_REV,
-	SIBA_SPROMVAR_MAC_80211BG,
-	SIBA_SPROMVAR_MAC_ETH,
-	SIBA_SPROMVAR_MAC_80211A,
-	SIBA_SPROMVAR_MII_ETH0,
-	SIBA_SPROMVAR_MII_ETH1,
-	SIBA_SPROMVAR_MDIO_ETH0,
-	SIBA_SPROMVAR_MDIO_ETH1,
-	SIBA_SPROMVAR_BREV,
-	SIBA_SPROMVAR_CCODE,
-	SIBA_SPROMVAR_ANT_A,
-	SIBA_SPROMVAR_ANT_BG,
-	SIBA_SPROMVAR_PA0B0,
-	SIBA_SPROMVAR_PA0B1,
-	SIBA_SPROMVAR_PA0B2,
-	SIBA_SPROMVAR_PA1B0,
-	SIBA_SPROMVAR_PA1B1,
-	SIBA_SPROMVAR_PA1B2,
-	SIBA_SPROMVAR_PA1LOB0,
-	SIBA_SPROMVAR_PA1LOB1,
-	SIBA_SPROMVAR_PA1LOB2,
-	SIBA_SPROMVAR_PA1HIB0,
-	SIBA_SPROMVAR_PA1HIB1,
-	SIBA_SPROMVAR_PA1HIB2,
-	SIBA_SPROMVAR_GPIO0,
-	SIBA_SPROMVAR_GPIO1,
-	SIBA_SPROMVAR_GPIO2,
-	SIBA_SPROMVAR_GPIO3,
-	SIBA_SPROMVAR_MAXPWR_AL,
-	SIBA_SPROMVAR_MAXPWR_A,
-	SIBA_SPROMVAR_MAXPWR_AH,
-	SIBA_SPROMVAR_MAXPWR_BG,
-	SIBA_SPROMVAR_RXPO2G,
-	SIBA_SPROMVAR_RXPO5G,
-	SIBA_SPROMVAR_TSSI_A,
-	SIBA_SPROMVAR_TSSI_BG,
-	SIBA_SPROMVAR_TRI2G,
-	SIBA_SPROMVAR_TRI5GL,
-	SIBA_SPROMVAR_TRI5G,
-	SIBA_SPROMVAR_TRI5GH,
-	SIBA_SPROMVAR_RSSISAV2G,
-	SIBA_SPROMVAR_RSSISMC2G,
-	SIBA_SPROMVAR_RSSISMF2G,
-	SIBA_SPROMVAR_BXA2G,
-	SIBA_SPROMVAR_RSSISAV5G,
-	SIBA_SPROMVAR_RSSISMC5G,
-	SIBA_SPROMVAR_RSSISMF5G,
-	SIBA_SPROMVAR_BXA5G,
-	SIBA_SPROMVAR_CCK2GPO,
-	SIBA_SPROMVAR_OFDM2GPO,
-	SIBA_SPROMVAR_OFDM5GLPO,
-	SIBA_SPROMVAR_OFDM5GPO,
-	SIBA_SPROMVAR_OFDM5GHPO,
-	SIBA_SPROMVAR_BF_LO,
-	SIBA_SPROMVAR_BF_HI,
-	SIBA_SPROMVAR_BF2_LO,
-	SIBA_SPROMVAR_BF2_HI,
-	SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS,
-	SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN,
-	SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE,
-	SIBA_SPROMVAR_FEM_2GHZ_TR_ISO,
-	SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT,
-	SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS,
-	SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN,
-	SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE,
-	SIBA_SPROMVAR_FEM_5GHZ_TR_ISO,
-	SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT,
-	SIBA_SPROMVAR_TXPID_2G_0,
-	SIBA_SPROMVAR_TXPID_2G_1,
-	SIBA_SPROMVAR_TXPID_2G_2,
-	SIBA_SPROMVAR_TXPID_2G_3,
-	SIBA_SPROMVAR_TXPID_5GL_0,
-	SIBA_SPROMVAR_TXPID_5GL_1,
-	SIBA_SPROMVAR_TXPID_5GL_2,
-	SIBA_SPROMVAR_TXPID_5GL_3,
-	SIBA_SPROMVAR_TXPID_5G_0,
-	SIBA_SPROMVAR_TXPID_5G_1,
-	SIBA_SPROMVAR_TXPID_5G_2,
-	SIBA_SPROMVAR_TXPID_5G_3,
-	SIBA_SPROMVAR_TXPID_5GH_0,
-	SIBA_SPROMVAR_TXPID_5GH_1,
-	SIBA_SPROMVAR_TXPID_5GH_2,
-	SIBA_SPROMVAR_TXPID_5GH_3,
-	SIBA_SPROMVAR_STBCPO,
-	SIBA_SPROMVAR_CDDPO,
-};
-
-int		siba_read_sprom(device_t, device_t, int, uintptr_t *);
-int		siba_write_sprom(device_t, device_t, int, uintptr_t);
-
-/**
- * Generic sprom accessor generation macros for siba(4) drivers
- */
-#define __SPROM_ACCESSOR(varp, var, ivarp, ivar, type)			\
-									\
-static __inline type varp ## _get_ ## var(device_t dev)			\
-{									\
-	uintptr_t v;							\
-	siba_read_sprom(device_get_parent(dev), dev,			\
-	    ivarp ## _SPROMVAR_ ## ivar, &v);				\
-	return ((type) v);						\
-}									\
-									\
-static __inline void varp ## _set_ ## var(device_t dev, type t)		\
-{									\
-	uintptr_t v = (uintptr_t) t;					\
-	siba_write_sprom(device_get_parent(dev), dev,			\
-	    ivarp ## _SPROMVAR_ ## ivar, v);				\
-}
-
-#define	SIBA_SPROM_ACCESSOR(var, ivar, type)				\
-	__SPROM_ACCESSOR(siba_sprom, var, SIBA, ivar, type)
-
-SIBA_SPROM_ACCESSOR(rev,	REV,		uint8_t);
-SIBA_SPROM_ACCESSOR(mac_80211bg,	MAC_80211BG,	uint8_t *);
-SIBA_SPROM_ACCESSOR(mac_eth,	MAC_ETH,	uint8_t *);
-SIBA_SPROM_ACCESSOR(mac_80211a,	MAC_80211A,	uint8_t *);
-SIBA_SPROM_ACCESSOR(mii_eth0,	MII_ETH0,	uint8_t);
-SIBA_SPROM_ACCESSOR(mii_eth1,	MII_ETH1,	uint8_t);
-SIBA_SPROM_ACCESSOR(mdio_eth0,	MDIO_ETH0,	uint8_t);
-SIBA_SPROM_ACCESSOR(mdio_eth1,	MDIO_ETH1,	uint8_t);
-SIBA_SPROM_ACCESSOR(brev,	BREV,		uint8_t);
-SIBA_SPROM_ACCESSOR(ccode,	CCODE,		uint8_t);
-SIBA_SPROM_ACCESSOR(ant_a,	ANT_A,		uint8_t);
-SIBA_SPROM_ACCESSOR(ant_bg,	ANT_BG,		uint8_t);
-SIBA_SPROM_ACCESSOR(pa0b0,	PA0B0,		uint16_t);
-SIBA_SPROM_ACCESSOR(pa0b1,	PA0B1,		uint16_t);
-SIBA_SPROM_ACCESSOR(pa0b2,	PA0B2,		uint16_t);
-SIBA_SPROM_ACCESSOR(pa1b0,	PA1B0,		uint16_t);
-SIBA_SPROM_ACCESSOR(pa1b1,	PA1B1,		uint16_t);
-SIBA_SPROM_ACCESSOR(pa1b2,	PA1B2,		uint16_t);
-SIBA_SPROM_ACCESSOR(pa1lob0,	PA1LOB0,	uint16_t);
-SIBA_SPROM_ACCESSOR(pa1lob1,	PA1LOB1,	uint16_t);
-SIBA_SPROM_ACCESSOR(pa1lob2,	PA1LOB2,	uint16_t);
-SIBA_SPROM_ACCESSOR(pa1hib0,	PA1HIB0,	uint16_t);
-SIBA_SPROM_ACCESSOR(pa1hib1,	PA1HIB1,	uint16_t);
-SIBA_SPROM_ACCESSOR(pa1hib2,	PA1HIB2,	uint16_t);
-SIBA_SPROM_ACCESSOR(gpio0,	GPIO0,		uint8_t);
-SIBA_SPROM_ACCESSOR(gpio1,	GPIO1,		uint8_t);
-SIBA_SPROM_ACCESSOR(gpio2,	GPIO2,		uint8_t);
-SIBA_SPROM_ACCESSOR(gpio3,	GPIO3,		uint8_t);
-SIBA_SPROM_ACCESSOR(maxpwr_al,	MAXPWR_AL,	uint16_t);
-SIBA_SPROM_ACCESSOR(maxpwr_a,	MAXPWR_A,	uint16_t);
-SIBA_SPROM_ACCESSOR(maxpwr_ah,	MAXPWR_AH,	uint16_t);
-SIBA_SPROM_ACCESSOR(maxpwr_bg,	MAXPWR_BG,	uint16_t);
-SIBA_SPROM_ACCESSOR(rxpo2g,	RXPO2G,		uint8_t);
-SIBA_SPROM_ACCESSOR(rxpo5g,	RXPO5G,		uint8_t);
-SIBA_SPROM_ACCESSOR(tssi_a,	TSSI_A,		uint8_t);
-SIBA_SPROM_ACCESSOR(tssi_bg,	TSSI_BG,	uint8_t);
-SIBA_SPROM_ACCESSOR(tri2g,	TRI2G,		uint8_t);
-SIBA_SPROM_ACCESSOR(tri5gl,	TRI5GL,		uint8_t);
-SIBA_SPROM_ACCESSOR(tri5g,	TRI5G,		uint8_t);
-SIBA_SPROM_ACCESSOR(tri5gh,	TRI5GH,		uint8_t);
-SIBA_SPROM_ACCESSOR(rssisav2g,	RSSISAV2G,	uint8_t);
-SIBA_SPROM_ACCESSOR(rssismc2g,	RSSISMC2G,	uint8_t);
-SIBA_SPROM_ACCESSOR(rssismf2g,	RSSISMF2G,	uint8_t);
-SIBA_SPROM_ACCESSOR(bxa2g,	BXA2G,		uint8_t);
-SIBA_SPROM_ACCESSOR(rssisav5g,	RSSISAV5G,	uint8_t);
-SIBA_SPROM_ACCESSOR(rssismc5g,	RSSISMC5G,	uint8_t);
-SIBA_SPROM_ACCESSOR(rssismf5g,	RSSISMF5G,	uint8_t);
-SIBA_SPROM_ACCESSOR(bxa5g,	BXA5G,		uint8_t);
-SIBA_SPROM_ACCESSOR(cck2gpo,	CCK2GPO,	uint16_t);
-SIBA_SPROM_ACCESSOR(ofdm2gpo,	OFDM2GPO,	uint32_t);
-SIBA_SPROM_ACCESSOR(ofdm5glpo,	OFDM5GLPO,	uint32_t);
-SIBA_SPROM_ACCESSOR(ofdm5gpo,	OFDM5GPO,	uint32_t);
-SIBA_SPROM_ACCESSOR(ofdm5ghpo,	OFDM5GHPO,	uint32_t);
-SIBA_SPROM_ACCESSOR(bf_lo,	BF_LO,		uint16_t);
-SIBA_SPROM_ACCESSOR(bf_hi,	BF_HI,		uint16_t);
-SIBA_SPROM_ACCESSOR(bf2_lo,	BF2_LO,		uint16_t);
-SIBA_SPROM_ACCESSOR(bf2_hi,	BF2_HI,		uint16_t);
-/* 2GHz FEM */
-SIBA_SPROM_ACCESSOR(fem_2ghz_tssipos, FEM_2GHZ_TSSIPOS, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_2ghz_extpa_gain, FEM_2GHZ_EXTPAGAIN, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_2ghz_pdet_range, FEM_2GHZ_PDET_RANGE, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_2ghz_tr_iso, FEM_2GHZ_TR_ISO, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_2ghz_antswlut, FEM_2GHZ_ANTSWLUT, uint8_t);
-/* 5GHz FEM */
-SIBA_SPROM_ACCESSOR(fem_5ghz_tssipos, FEM_5GHZ_TSSIPOS, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_5ghz_extpa_gain, FEM_5GHZ_EXTPAGAIN, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_5ghz_pdet_range, FEM_5GHZ_PDET_RANGE, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_5ghz_tr_iso, FEM_5GHZ_TR_ISO, uint8_t);
-SIBA_SPROM_ACCESSOR(fem_5ghz_antswlut, FEM_5GHZ_ANTSWLUT, uint8_t);
-/* TX power index */
-SIBA_SPROM_ACCESSOR(txpid_2g_0, TXPID_2G_0, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_2g_1, TXPID_2G_1, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_2g_2, TXPID_2G_2, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_2g_3, TXPID_2G_3, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gl_0, TXPID_5GL_0, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gl_1, TXPID_5GL_1, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gl_2, TXPID_5GL_2, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gl_3, TXPID_5GL_3, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5g_0, TXPID_5G_0, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5g_1, TXPID_5G_1, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5g_2, TXPID_5G_2, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5g_3, TXPID_5G_3, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gh_0, TXPID_5GH_0, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gh_1, TXPID_5GH_1, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gh_2, TXPID_5GH_2, uint8_t);
-SIBA_SPROM_ACCESSOR(txpid_5gh_3, TXPID_5GH_3, uint8_t);
-SIBA_SPROM_ACCESSOR(stbcpo, STBCPO, uint16_t);
-SIBA_SPROM_ACCESSOR(cddpo, CDDPO, uint16_t);
-
-#undef SIBA_SPROM_ACCESSOR
-
-struct siba_sprom_core_pwr_info {
-	uint8_t itssi_2g, itssi_5g;
-	uint8_t maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
-	uint8_t pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
-};
-
-struct siba_sprom {
-	uint8_t			rev;		/* revision */
-	uint8_t			mac_80211bg[6];	/* address for 802.11b/g */
-	uint8_t			mac_eth[6];	/* address for Ethernet */
-	uint8_t			mac_80211a[6];	/* address for 802.11a */
-	uint8_t			mii_eth0;	/* MII address for eth0 */
-	uint8_t			mii_eth1;	/* MII address for eth1 */
-	uint8_t			mdio_eth0;	/* MDIO for eth0 */
-	uint8_t			mdio_eth1;	/* MDIO for eth1 */
-	uint8_t			brev;		/* board revision */
-	uint8_t			ccode;		/* Country Code */
-	uint8_t			ant_a;		/* A-PHY antenna */
-	uint8_t			ant_bg;		/* B/G-PHY antenna */
-	uint16_t		pa0b0;
-	uint16_t		pa0b1;
-	uint16_t		pa0b2;
-	uint16_t		pa1b0;
-	uint16_t		pa1b1;
-	uint16_t		pa1b2;
-	uint16_t		pa1lob0;
-	uint16_t		pa1lob1;
-	uint16_t		pa1lob2;
-	uint16_t		pa1hib0;
-	uint16_t		pa1hib1;
-	uint16_t		pa1hib2;
-	uint8_t			gpio0;
-	uint8_t			gpio1;
-	uint8_t			gpio2;
-	uint8_t			gpio3;
-	uint16_t		maxpwr_al;
-	uint16_t		maxpwr_a;	/* A-PHY Max Power */
-	uint16_t		maxpwr_ah;
-	uint16_t		maxpwr_bg;	/* BG-PHY Max Power */
-	uint8_t			rxpo2g;
-	uint8_t			rxpo5g;
-	uint8_t			tssi_a;		/* Idle TSSI */
-	uint8_t			tssi_bg;	/* Idle TSSI */
-	uint8_t			tri2g;
-	uint8_t			tri5gl;
-	uint8_t			tri5g;
-	uint8_t			tri5gh;
-	uint8_t			txpid2g[4];	/* 2GHz TX power index */
-	uint8_t			txpid5gl[4];	/* 4.9 - 5.1GHz TX power index */
-	uint8_t			txpid5g[4];	/* 5.1 - 5.5GHz TX power index */
-	uint8_t			txpid5gh[4];	/* 5.5 - 5.9GHz TX power index */
-	uint8_t			rssisav2g;
-	uint8_t			rssismc2g;
-	uint8_t			rssismf2g;
-	uint8_t			bxa2g;
-	uint8_t			rssisav5g;
-	uint8_t			rssismc5g;
-	uint8_t			rssismf5g;
-	uint8_t			bxa5g;
-	uint16_t		cck2gpo;
-	uint32_t		ofdm2gpo;
-	uint32_t		ofdm5glpo;
-	uint32_t		ofdm5gpo;
-	uint32_t		ofdm5ghpo;
-	uint16_t		bf_lo;		/* boardflags */
-	uint16_t		bf_hi;		/* boardflags */
-	uint16_t		bf2_lo;
-	uint16_t		bf2_hi;
-
-	struct siba_sprom_core_pwr_info core_pwr_info[4];
-
-	struct {
-		struct {
-			int8_t a0, a1, a2, a3;
-		} ghz24;
-		struct {
-			int8_t a0, a1, a2, a3;
-		} ghz5;
-	} again;	/* antenna gain */
-
-	struct {
-		struct {
-			uint8_t tssipos, extpa_gain, pdet_range, tr_iso;
-			uint8_t antswlut;
-		} ghz2;
-		struct {
-			uint8_t tssipos, extpa_gain, pdet_range, tr_iso;
-			uint8_t antswlut;
-		} ghz5;
-	} fem;
-
-	uint16_t mcs2gpo[8];
-	uint16_t mcs5gpo[8];
-	uint16_t mcs5glpo[8];
-	uint16_t mcs5ghpo[8];
-
-	uint16_t cddpo;
-	uint16_t stbcpo;
-};
-
-#define	SIBA_LDO_PAREF			0
-#define	SIBA_LDO_VOLT1			1
-#define	SIBA_LDO_VOLT2			2
-#define	SIBA_LDO_VOLT3			3
-
-struct siba_cc_pmu {
-	uint8_t				rev;	/* PMU rev */
-	uint32_t			freq;	/* crystal freq in kHz */
-};
-
-struct siba_cc {
-	struct siba_dev_softc		*scc_dev;
-	uint32_t			scc_caps;
-	struct siba_cc_pmu		scc_pmu;
-	uint16_t			scc_powerup_delay;
-};
-
-struct siba_pci {
-	struct siba_dev_softc		*spc_dev;
-	uint8_t				spc_inited;
-	uint8_t				spc_hostmode;
-};
-
-struct siba_bus_ops {
-	uint16_t		(*read_2)(struct siba_dev_softc *,
-				    uint16_t);
-	uint32_t		(*read_4)(struct siba_dev_softc *,
-				    uint16_t);
-	void			(*write_2)(struct siba_dev_softc *,
-				    uint16_t, uint16_t);
-	void			(*write_4)(struct siba_dev_softc *,
-				    uint16_t, uint32_t);
-	void			(*read_multi_1)(struct siba_dev_softc *,
-				    void *, size_t, uint16_t);
-	void			(*read_multi_2)(struct siba_dev_softc *,
-				    void *, size_t, uint16_t);
-	void			(*read_multi_4)(struct siba_dev_softc *,
-				    void *, size_t, uint16_t);
-	void			(*write_multi_1)(struct siba_dev_softc *,
-				    const void *, size_t, uint16_t);
-	void			(*write_multi_2)(struct siba_dev_softc *,
-				    const void *, size_t, uint16_t);
-	void			(*write_multi_4)(struct siba_dev_softc *,
-				    const void *, size_t, uint16_t);
-};
-
-struct siba_dev_softc {
-	struct siba_softc		*sd_bus;
-	struct siba_devid		sd_id;
-	const struct siba_bus_ops	*sd_ops;
-
-	uint8_t				sd_coreidx;
-};
-
-struct siba_devinfo {
-	struct resource_list		 sdi_rl;
-	/*devhandle_t			 sdi_devhandle; XXX*/
-	/*struct rman sdi_intr_rman;*/
-
-	/* Accessors are needed for ivars below. */
-	uint16_t			 sdi_vid;
-	uint16_t			 sdi_devid;
-	uint8_t				 sdi_rev;
-	uint8_t				 sdi_idx;	/* core index on bus */
-	uint8_t				 sdi_irq;	/* TODO */
-};
-
-struct siba_softc {
-	/*
-	 * common variables which used for siba(4) bus and siba_bwn bridge.
-	 */
-	device_t			siba_dev;	/* Device ID */
-	struct resource			*siba_mem_res;
-	bus_space_tag_t			siba_mem_bt;
-	bus_space_handle_t		siba_mem_bh;
-	bus_addr_t			siba_maddr;
-	bus_size_t			siba_msize;
-	uint8_t				siba_ncores;
-	uint32_t			siba_debug;
-
-	/*
-	 * the following variables are only used for siba_bwn bridge.
-	 */
-
-	enum siba_type			siba_type;
-	int				siba_invalid;
-
-	struct siba_dev_softc		*siba_curdev;	/* only for PCI */
-	struct siba_dev_softc		siba_devs[SIBA_MAX_CORES];
-	int				siba_ndevs;
-
-	uint16_t			siba_pci_vid;
-	uint16_t			siba_pci_did;
-	uint16_t			siba_pci_subvid;
-	uint16_t			siba_pci_subdid;
-	uint8_t				siba_pci_revid;
-	int				siba_mem_rid;
-
-	uint16_t			siba_chipid;	/* for CORE 0 */
-	uint16_t			siba_chiprev;
-	uint8_t				siba_chippkg;
-
-	struct siba_cc			siba_cc;		/* ChipCommon */
-	struct siba_pci			siba_pci;	/* PCI-core */
-	const struct siba_bus_ops	*siba_ops;
-
-	struct siba_sprom		siba_sprom;	/* SPROM */
-	uint16_t			siba_spromsize;	/* in word size */
-};
-
-void		siba_powerup(device_t, int);
-int		siba_powerdown(device_t);
-uint16_t	siba_read_2(device_t, uint16_t);
-void		siba_write_2(device_t, uint16_t, uint16_t);
-uint32_t	siba_read_4(device_t, uint16_t);
-void		siba_write_4(device_t, uint16_t, uint32_t);
-void		siba_dev_up(device_t, uint32_t);
-void		siba_dev_down(device_t, uint32_t);
-int		siba_dev_isup(device_t);
-void		siba_pcicore_intr(device_t);
-uint32_t	siba_dma_translation(device_t);
-void		siba_read_multi_1(device_t, void *, size_t, uint16_t);
-void		siba_read_multi_2(device_t, void *, size_t, uint16_t);
-void		siba_read_multi_4(device_t, void *, size_t, uint16_t);
-void		siba_write_multi_1(device_t, const void *, size_t, uint16_t);
-void		siba_write_multi_2(device_t, const void *, size_t, uint16_t);
-void		siba_write_multi_4(device_t, const void *, size_t, uint16_t);
-void		siba_barrier(device_t, int);
-void		siba_cc_pmu_set_ldovolt(device_t, int, uint32_t);
-void		siba_cc_pmu_set_ldoparef(device_t, uint8_t);
-void		siba_gpio_set(device_t, uint32_t);
-uint32_t	siba_gpio_get(device_t);
-void		siba_fix_imcfglobug(device_t);
-int		siba_sprom_get_core_power_info(device_t, int,
-		    struct siba_sprom_core_pwr_info *);
-int		siba_sprom_get_mcs2gpo(device_t, uint16_t *);
-int		siba_sprom_get_mcs5glpo(device_t, uint16_t *);
-int		siba_sprom_get_mcs5gpo(device_t, uint16_t *);
-int		siba_sprom_get_mcs5ghpo(device_t, uint16_t *);
-void		siba_pmu_spuravoid_pllupdate(device_t, int);
-void		siba_cc_set32(device_t dev, uint32_t, uint32_t);
-void		siba_cc_mask32(device_t dev, uint32_t, uint32_t);
-uint32_t	siba_cc_read32(device_t dev, uint32_t);
-void		siba_cc_write32(device_t dev, uint32_t, uint32_t);
-
-#endif /* _SIBA_SIBAVAR_H_ */
diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c
index 0e1291ea39b3..c7ecb9747e7a 100644
--- a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c
+++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c
@@ -69,23 +69,31 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
+#include <dev/bhnd/cores/chipc/chipc.h>
+
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_util.h>
 #include <dev/bwn/if_bwn_debug.h>
 #include <dev/bwn/if_bwn_phy_common.h>
-#include <dev/bwn/if_bwn_chipid.h>
 #include <dev/bwn/if_bwn_cordic.h>
 
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h>
+#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_radio_2055.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_radio_2056.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_radio_2057.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h>
 
+#include "bhnd_nvram_map.h"
+
 struct bwn_nphy_txgains {
 	uint16_t tx_lpf[2];
 	uint16_t txgm[2];
@@ -590,7 +598,7 @@ static uint16_t bwn_nphy_classifier(struct bwn_mac *mac, uint16_t mask, uint16_t
 	struct bwn_softc *sc = mac->mac_sc;
 	uint16_t tmp;
 
-	if (siba_get_revid(sc->sc_dev) == 16)
+	if (bhnd_get_hwrev(sc->sc_dev) == 16)
 		bwn_mac_suspend(mac);
 
 	tmp = BWN_PHY_READ(mac, BWN_NPHY_CLASSCTL);
@@ -600,7 +608,7 @@ static uint16_t bwn_nphy_classifier(struct bwn_mac *mac, uint16_t mask, uint16_t
 	tmp |= (val & mask);
 	BWN_PHY_SETMASK(mac, BWN_NPHY_CLASSCTL, 0xFFF8, tmp);
 
-	if (siba_get_revid(sc->sc_dev) == 16)
+	if (bhnd_get_hwrev(sc->sc_dev) == 16)
 		bwn_mac_enable(mac);
 
 	return tmp;
@@ -1232,20 +1240,20 @@ static void bwn_radio_2056_setup(struct bwn_mac *mac,
 	}
 
 	is_pkg_fab_smic =
-		((siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43224 ||
-		  siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43225 ||
-		  siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43421) &&
-		 siba_get_chippkg(sc->sc_dev) == BCMA_PKG_ID_BCM43224_FAB_SMIC);
+		((sc->sc_cid.chip_id == BHND_CHIPID_BCM43224 ||
+		  sc->sc_cid.chip_id == BHND_CHIPID_BCM43225 ||
+		  sc->sc_cid.chip_id == BHND_CHIPID_BCM43421) &&
+		 sc->sc_cid.chip_pkg == BHND_PKGID_BCM43224_FAB_SMIC);
 
 	bwn_chantab_radio_2056_upload(mac, e);
 	b2056_upload_syn_pll_cp2(mac, band == BWN_BAND_5G);
 
-	if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_GPLL_WAR &&
+	if (sc->sc_board_info.board_flags2 & BHND_BFL2_GPLL_WAR &&
 	    bwn_current_band(mac) == BWN_BAND_2G) {
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
-		if (siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM4716 ||
-		    siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM47162) {
+		if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4716 ||
+		    sc->sc_cid.chip_id == BHND_CHIPID_BCM47162) {
 			BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 			BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0);
 		} else {
@@ -1253,14 +1261,14 @@ static void bwn_radio_2056_setup(struct bwn_mac *mac,
 			BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x14);
 		}
 	}
-	if (siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_GPLL_WAR2 &&
+	if (sc->sc_board_info.board_flags2 & BHND_BFL2_GPLL_WAR &&
 	    bwn_current_band(mac) == BWN_BAND_2G) {
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x20);
 	}
-	if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_APLL_WAR &&
+	if (sc->sc_board_info.board_flags2 & BHND_BFL2_APLL_WAR &&
 	    bwn_current_band(mac) == BWN_BAND_5G) {
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 		BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
@@ -1275,8 +1283,8 @@ static void bwn_radio_2056_setup(struct bwn_mac *mac,
 				BWN_RF_WRITE(mac,
 					offset | B2056_TX_PADG_IDAC, 0xcc);
 
-				if (siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM4716 ||
-				    siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM47162) {
+				if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4716 ||
+				    sc->sc_cid.chip_id == BHND_CHIPID_BCM47162) {
 					bias = 0x40;
 					cbias = 0x45;
 					pag_boost = 0x5;
@@ -1551,14 +1559,14 @@ static void bwn_radio_init2055_post(struct bwn_mac *mac)
 	struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
 	bool workaround = false;
 
-	if (siba_get_revid(sc->sc_dev) < 4)
+	if (bhnd_get_hwrev(sc->sc_dev) < 4)
 		workaround =
-		    (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM)
-		    && (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4321)
-		      && (siba_sprom_get_brev(sc->sc_dev) >= 0x41);
+		    (sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM)
+		    && (sc->sc_board_info.board_type == BHND_BOARD_BCM4321CB2)
+		      && (sc->sc_board_info.board_rev >= 0x41);
 	else
 		workaround =
-			!(siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_RXBB_INT_REG_DIS);
+			!(sc->sc_board_info.board_flags2 & BHND_BFL2_RXBB_INT_REG_DIS);
 
 	BWN_RF_MASK(mac, B2055_MASTER1, 0xFFF3);
 	if (workaround) {
@@ -2618,8 +2626,8 @@ static void bwn_nphy_gain_ctl_workarounds_rev3(struct bwn_mac *mac)
 	/* Prepare values */
 	ghz5 = BWN_PHY_READ(mac, BWN_NPHY_BANDCTL)
 		& BWN_NPHY_BANDCTL_5GHZ;
-	ext_lna = ghz5 ? siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_EXTLNA_5GHZ :
-		siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA;
+	ext_lna = ghz5 ? sc->sc_board_info.board_flags & BHND_BFL_EXTLNA_5GHZ :
+		sc->sc_board_info.board_flags & BHND_BFL_EXTLNA;
 	e = bwn_nphy_get_gain_ctl_workaround_ent(mac, ghz5, ext_lna);
 	if (ghz5 && mac->mac_phy.rev >= 5)
 		rssi_gain = 0x90;
@@ -2811,7 +2819,7 @@ static void bwn_nphy_gain_ctl_workarounds(struct bwn_mac *mac)
 		bwn_nphy_gain_ctl_workarounds_rev1_2(mac);
 }
 
-static void bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac)
+static int bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
@@ -3073,8 +3081,8 @@ static void bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac)
 		bwn_nphy_rf_ctl_override_rev7(mac, 4, 1, 3, false, 0);
 
 	if (phy->rf_rev == 3 || phy->rf_rev == 4 || phy->rf_rev == 6) {
-		if (siba_sprom_get_rev(sc->sc_dev) &&
-		    siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_IPALVLSHIFT_3P3) {
+		if (sc->sc_board_info.board_srom_rev &&
+		    sc->sc_board_info.board_flags2 & BHND_BFL2_IPALVLSHIFT_3P3) {
 			BWN_RF_WRITE(mac, 0x5, 0x05);
 			BWN_RF_WRITE(mac, 0x6, 0x30);
 			BWN_RF_WRITE(mac, 0x7, 0x00);
@@ -3254,9 +3262,11 @@ static void bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac)
 	bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1C), 4,
 			    aux_adc_gain_rev7);
 	*/
+
+	return (0);
 }
 
-static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
+static int bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
@@ -3287,9 +3297,11 @@ static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
 	};
 	uint16_t *vmid, *gain;
 
+	const char *pdet_range_var;
 	uint8_t pdet_range;
 	uint16_t tmp16;
 	uint32_t tmp32;
+	int error;
 
 	BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1f8);
 	BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1f8);
@@ -3347,9 +3359,18 @@ static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
 	bwn_ntab_write(mac, BWN_NTAB16(8, 16), 2);
 
 	if (bwn_current_band(mac) == BWN_BAND_2G)
-		pdet_range = siba_sprom_get_fem_2ghz_pdet_range(sc->sc_dev);
+		pdet_range_var = BHND_NVAR_PDETRANGE2G;
 	else
-		pdet_range = siba_sprom_get_fem_5ghz_pdet_range(sc->sc_dev);
+		pdet_range_var = BHND_NVAR_PDETRANGE5G;
+
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, pdet_range_var,
+	    &pdet_range);
+	if (error) {
+		BWN_ERRPRINTF(mac->mac_sc, "Error reading PDet range %s from "
+		    "NVRAM: %d\n", pdet_range_var, error);
+		return (error);
+	}
+
 	/* uint16_t min() */
 	vmid = vmids[min(pdet_range, 4)];
 	gain = gains[min(pdet_range, 4)];
@@ -3428,9 +3449,9 @@ static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
 
 	/* N PHY WAR TX Chain Update with hw_phytxchain as argument */
 
-	if ((siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_APLL_WAR &&
+	if ((sc->sc_board_info.board_flags2 & BHND_BFL2_APLL_WAR &&
 	     bwn_current_band(mac) == BWN_BAND_5G) ||
-	    (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_GPLL_WAR &&
+	    (sc->sc_board_info.board_flags2 & BHND_BFL2_GPLL_WAR2 &&
 	     bwn_current_band(mac) == BWN_BAND_2G))
 		tmp32 = 0x00088888;
 	else
@@ -3461,11 +3482,13 @@ static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
 	BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
 	BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
 
-	if (mac->mac_phy.rev >= 6 && siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SINGLEANT_CCK)
+	if (mac->mac_phy.rev >= 6 && sc->sc_board_info.board_flags2 & BHND_BFL2_SINGLEANT_CCK)
 		; /* TODO: 0x0080000000000000 HF */
+
+	return (0);
 }
 
-static void bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac)
+static int bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
@@ -3477,8 +3500,8 @@ static void bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac)
 	uint8_t events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 	uint8_t delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 
-	if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SKWRKFEM_BRD ||
-	    siba_get_pci_subdevice(sc->sc_dev)== BCMA_BOARD_TYPE_BCM943224M93) {
+	if (sc->sc_board_info.board_flags2 & BHND_BFL2_SKWRKFEM_BRD ||
+	    sc->sc_board_info.board_type == BHND_BOARD_BCM943224M93) {
 		delays1[0] = 0x1;
 		delays1[5] = 0x14;
 	}
@@ -3550,13 +3573,16 @@ static void bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac)
 	if (mac->mac_phy.rev == 2)
 		BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC,
 				BWN_NPHY_FINERX2_CGC_DECGC);
+
+	return (0);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
-static void bwn_nphy_workarounds(struct bwn_mac *mac)
+static int bwn_nphy_workarounds(struct bwn_mac *mac)
 {
 	struct bwn_phy *phy = &mac->mac_phy;
 	struct bwn_phy_n *nphy = phy->phy_n;
+	int error;
 
 	if (bwn_current_band(mac) == BWN_BAND_5G)
 		bwn_nphy_classifier(mac, 1, 0);
@@ -3571,14 +3597,19 @@ static void bwn_nphy_workarounds(struct bwn_mac *mac)
 
 	/* TODO: rev19+ */
 	if (mac->mac_phy.rev >= 7)
-		bwn_nphy_workarounds_rev7plus(mac);
+		error = bwn_nphy_workarounds_rev7plus(mac);
 	else if (mac->mac_phy.rev >= 3)
-		bwn_nphy_workarounds_rev3plus(mac);
+		error = bwn_nphy_workarounds_rev3plus(mac);
 	else
-		bwn_nphy_workarounds_rev1_2(mac);
+		error = bwn_nphy_workarounds_rev1_2(mac);
+
+	if (error)
+		return (error);
 
 	if (nphy->hang_avoid)
 		bwn_nphy_stay_in_carrier_search(mac, 0);
+
+	return (0);
 }
 
 /**************************************************
@@ -3852,7 +3883,7 @@ static void bwn_nphy_tx_power_ctrl(struct bwn_mac *mac, bool enable)
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
-static void bwn_nphy_tx_power_fix(struct bwn_mac *mac)
+static int bwn_nphy_tx_power_fix(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
@@ -3872,26 +3903,40 @@ static void bwn_nphy_tx_power_fix(struct bwn_mac *mac)
 	} else if (mac->mac_phy.rev >= 3) {
 		txpi[0] = 40;
 		txpi[1] = 40;
-	} else if (siba_sprom_get_rev(sc->sc_dev) < 4) {
+	} else if (sc->sc_board_info.board_srom_rev < 4) {
 		txpi[0] = 72;
 		txpi[1] = 72;
 	} else {
+#define	BWN_NPHY_GET_TXPI(_name, _result)				\
+do {									\
+	int error;							\
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, (_name),		\
+	    (_result));							\
+	if (error) {							\
+		device_printf(sc->sc_dev, "NVRAM variable %s "		\
+		     "unreadable: %d\n", (_name), error);		\
+		return (error);						\
+	}								\
+} while(0)
+
 		if (bwn_current_band(mac) == BWN_BAND_2G) {
-			txpi[0] = siba_sprom_get_txpid_2g_0(sc->sc_dev);
-			txpi[1] = siba_sprom_get_txpid_2g_1(sc->sc_dev);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID2GA0, &txpi[0]);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID2GA1, &txpi[1]);
 		} else if (freq >= 4900 && freq < 5100) {
-			txpi[0] = siba_sprom_get_txpid_5gl_0(sc->sc_dev);
-			txpi[1] = siba_sprom_get_txpid_5gl_1(sc->sc_dev);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GLA0, &txpi[0]);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GLA1, &txpi[1]);
 		} else if (freq >= 5100 && freq < 5500) {
-			txpi[0] = siba_sprom_get_txpid_5g_0(sc->sc_dev);
-			txpi[1] = siba_sprom_get_txpid_5g_1(sc->sc_dev);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GA0, &txpi[0]);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GA1, &txpi[1]);
 		} else if (freq >= 5500) {
-			txpi[0] = siba_sprom_get_txpid_5gh_0(sc->sc_dev);
-			txpi[1] = siba_sprom_get_txpid_5gh_1(sc->sc_dev);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GHA0, &txpi[0]);
+			BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GHA1, &txpi[1]);
 		} else {
 			txpi[0] = 91;
 			txpi[1] = 91;
 		}
+
+#undef	BWN_NPHY_GET_TXPI
 	}
 	if (mac->mac_phy.rev < 7 &&
 	    (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
@@ -3960,6 +4005,8 @@ static void bwn_nphy_tx_power_fix(struct bwn_mac *mac)
 
 	if (nphy->hang_avoid)
 		bwn_nphy_stay_in_carrier_search(mac, 0);
+
+	return (0);
 }
 
 static void bwn_nphy_ipa_internal_tssi_setup(struct bwn_mac *mac)
@@ -4163,7 +4210,7 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
 	struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
-	struct siba_sprom_core_pwr_info core_pwr_info[4];
+	struct bwn_phy_n_core_pwr_info core_pwr_info[4];
 	int n;
 
 	int16_t a1[2], b0[2], b1[2];
@@ -4180,7 +4227,7 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 
 	for (n = 0; n < 4; n++) {
 		bzero(&core_pwr_info[n], sizeof(core_pwr_info[n]));
-		if (siba_sprom_get_core_power_info(sc->sc_dev, n,
+		if (bwn_nphy_get_core_power_info(mac, n,
 		    &core_pwr_info[n]) != 0) {
 			BWN_ERRPRINTF(mac->mac_sc,
 			    "%s: failed to get core_pwr_info for core %d\n",
@@ -4189,7 +4236,7 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 		}
 	}
 
-	if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) {
+	if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) {
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000);
 		BWN_READ_4(mac, BWN_MACCTL);
 		DELAY(1);
@@ -4206,14 +4253,14 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 		BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_CMD,
 			    BWN_NPHY_TXPCTL_CMD_PCTLEN);
 
-	if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12)
+	if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12)
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0);
 
 	/*
 	 * XXX TODO: see if those bandsbelow map to 5g-lo, 5g-mid, 5g-hi in
 	 * any way.
 	 */
-	if (siba_sprom_get_rev(sc->sc_dev) < 4) {
+	if (sc->sc_board_info.board_srom_rev < 4) {
 		idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
 		idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
 		target[0] = target[1] = 52;
@@ -4270,7 +4317,7 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 	}
 
 	if (mac->mac_phy.rev >= 3) {
-		if (siba_sprom_get_fem_2ghz_tssipos(sc->sc_dev))
+		if (nphy->tsspos_2g)
 			BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_ITSSI, 0x4000);
 		if (mac->mac_phy.rev >= 7) {
 			for (c = 0; c < 2; c++) {
@@ -4294,7 +4341,7 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 		}
 	}
 
-	if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) {
+	if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) {
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000);
 		BWN_READ_4(mac, BWN_MACCTL);
 		DELAY(1);
@@ -4315,7 +4362,7 @@ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
 				~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
 	}
 
-	if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12)
+	if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12)
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0);
 
 	BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_N,
@@ -6061,13 +6108,13 @@ bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi)
 	tx_pwr_state = nphy->txpwrctrl;
 	bwn_mac_suspend(mac);
 	bwn_nphy_tx_power_ctl_setup(mac);
-	if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) {
+	if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) {
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, BWN_MACCTL_PHY_LOCK);
 		BWN_READ_4(mac, BWN_MACCTL);
 		DELAY(1);
 	}
 	bwn_nphy_tx_power_ctrl(mac, nphy->txpwrctrl);
-	if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12)
+	if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12)
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_PHY_LOCK, 0);
 	bwn_mac_enable(mac);
 
@@ -6115,16 +6162,16 @@ static void bwn_nphy_bphy_init(struct bwn_mac *mac)
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
-static void bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init)
+static int bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	int error;
 
 	if (mac->mac_phy.rev >= 7)
-		return;
+		return (0);
 
 	if (mac->mac_phy.rev >= 3) {
 		if (!init)
-			return;
+			return (0);
 		if (0 /* FIXME */) {
 			bwn_ntab_write(mac, BWN_NTAB16(9, 2), 0x211);
 			bwn_ntab_write(mac, BWN_NTAB16(9, 3), 0x222);
@@ -6135,7 +6182,8 @@ static void bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init)
 		BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_LOOEN, 0);
 		BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_HIOEN, 0);
 
-		siba_gpio_set(sc->sc_dev, 0xfc00);
+		if ((error = bwn_gpio_control(mac, 0xfc00)))
+			return (error);
 
 		BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_GPOUT_MASK, 0);
 		BWN_WRITE_SETMASK2(mac, BWN_GPIO_MASK, ~0, 0xFC00);
@@ -6149,6 +6197,8 @@ static void bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init)
 			BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 		}
 	}
+
+	return (0);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
@@ -6159,6 +6209,7 @@ static int bwn_phy_initn(struct bwn_mac *mac)
 	struct bwn_phy_n *nphy = phy->phy_n;
 	uint8_t tx_pwr_state;
 	struct bwn_nphy_txgains target;
+	int error;
 	uint16_t tmp;
 	bwn_band_t tmp2;
 	bool do_rssi_cal;
@@ -6166,15 +6217,28 @@ static int bwn_phy_initn(struct bwn_mac *mac)
 	uint16_t clip[2];
 	bool do_cal = false;
 
+	if (mac->mac_phy.rev >= 3) {
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_TSSIPOS2G,
+		    &nphy->tsspos_2g);
+		if (error) {
+			BWN_ERRPRINTF(mac->mac_sc, "Error reading %s from "
+			    "NVRAM: %d\n", BHND_NVAR_TSSIPOS2G, error);
+			return (error);
+		}
+	} else {
+		nphy->tsspos_2g = 0;
+	}
+
 	if ((mac->mac_phy.rev >= 3) &&
-	   (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) &&
-	   (bwn_current_band(mac) == BWN_BAND_2G)) {
-		siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL, 0x40);
+	   (sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) &&
+	   (bwn_current_band(mac) == BWN_BAND_2G))
+	{
+		BHND_CHIPC_WRITE_CHIPCTRL(sc->sc_chipc, 0x40, 0x40);
 	}
 	nphy->use_int_tx_iq_lo_cal = bwn_nphy_ipa(mac) ||
 		phy->rev >= 7 ||
 		(phy->rev >= 5 &&
-		 siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_INTERNDET_TXIQCAL);
+		 sc->sc_board_info.board_flags2 & BHND_BFL2_INTERNDET_TXIQCAL);
 	nphy->deaf_count = 0;
 	bwn_nphy_tables_init(mac);
 	nphy->crsminpwr_adjusted = false;
@@ -6221,9 +6285,9 @@ static int bwn_phy_initn(struct bwn_mac *mac)
 	BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
 	BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
 
-	if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SKWRKFEM_BRD ||
-	    (siba_get_pci_subvendor(sc->sc_dev) == PCI_VENDOR_APPLE &&
-	     siba_get_pci_subdevice(sc->sc_dev) == BCMA_BOARD_TYPE_BCM943224M93))
+	if (sc->sc_board_info.board_flags2 & BHND_BFL2_SKWRKFEM_BRD ||
+	    (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE &&
+	     sc->sc_board_info.board_type == BHND_BOARD_BCM943224M93))
 		BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xA0);
 	else
 		BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xB8);
@@ -6254,7 +6318,8 @@ static int bwn_phy_initn(struct bwn_mac *mac)
 		bwn_nphy_ext_pa_set_tx_dig_filters(mac);
 	}
 
-	bwn_nphy_workarounds(mac);
+	if ((error = bwn_nphy_workarounds(mac)))
+		return (error);
 
 	/* Reset CCA, in init code it differs a little from standard way */
 	bwn_phy_force_clock(mac, 1);
@@ -6279,7 +6344,8 @@ static int bwn_phy_initn(struct bwn_mac *mac)
 
 	tx_pwr_state = nphy->txpwrctrl;
 	bwn_nphy_tx_power_ctrl(mac, false);
-	bwn_nphy_tx_power_fix(mac);
+	if ((error = bwn_nphy_tx_power_fix(mac)))
+		return (error);
 	bwn_nphy_tx_power_ctl_idle_tssi(mac);
 	bwn_nphy_tx_power_ctl_setup(mac);
 	bwn_nphy_tx_gain_table_upload(mac);
@@ -6316,8 +6382,11 @@ static int bwn_phy_initn(struct bwn_mac *mac)
 		if (do_cal) {
 			target = bwn_nphy_get_tx_gains(mac);
 
-			if (nphy->antsel_type == 2)
-				bwn_nphy_superswitch_init(mac, true);
+			if (nphy->antsel_type == 2) {
+				error = bwn_nphy_superswitch_init(mac, true);
+				if (error)
+					return (error);
+			}
 			if (nphy->perical != 2) {
 				bwn_nphy_rssi_cal(mac);
 				if (phy->rev >= 3) {
@@ -6367,16 +6436,28 @@ static void bwn_chantab_phy_upload(struct bwn_mac *mac,
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
-static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac, bool avoid)
+static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac,
+				    bhnd_pmu_spuravoid mode)
 {
 	struct bwn_softc *sc = mac->mac_sc;
+	int error;
+
+	DPRINTF(sc, BWN_DEBUG_RESET, "%s: spuravoid %d\n", __func__, mode);
 
-	DPRINTF(sc, BWN_DEBUG_RESET, "%s: spuravoid %d\n", __func__, avoid);
-	siba_pmu_spuravoid_pllupdate(sc->sc_dev, avoid);
+	if (sc->sc_pmu == NULL) {
+		BWN_ERRPRINTF(mac->mac_sc, "no PMU; cannot configure spurious "
+		    "signal avoidance\n");
+		return;
+	}
+
+	if ((error = bhnd_pmu_request_spuravoid(sc->sc_pmu, mode))) {
+		device_printf(sc->sc_dev, "spuravoid request failed: %d",
+		    error);
+	}
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
-static void bwn_nphy_channel_setup(struct bwn_mac *mac,
+static int bwn_nphy_channel_setup(struct bwn_mac *mac,
 				const struct bwn_phy_n_sfo_cfg *e,
 				struct ieee80211_channel *new_channel)
 {
@@ -6384,6 +6465,7 @@ static void bwn_nphy_channel_setup(struct bwn_mac *mac,
 	struct bwn_phy *phy = &mac->mac_phy;
 	struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
 	int ch = new_channel->ic_ieee;
+	int error;
 	uint16_t tmp16;
 
 	if (bwn_channel_band(mac, new_channel) == BWN_BAND_5G) {
@@ -6422,8 +6504,10 @@ static void bwn_nphy_channel_setup(struct bwn_mac *mac,
 			BWN_PHY_MASK(mac, BWN_PHY_B_TEST, ~0x840);
 	}
 
-	if (!nphy->txpwrctrl)
-		bwn_nphy_tx_power_fix(mac);
+	if (!nphy->txpwrctrl) {
+		if ((error = bwn_nphy_tx_power_fix(mac)))
+			return (error);
+	}
 
 	if (mac->mac_phy.rev < 3)
 		bwn_nphy_adjust_lna_gain_table(mac);
@@ -6432,10 +6516,10 @@ static void bwn_nphy_channel_setup(struct bwn_mac *mac,
 
 	if (mac->mac_phy.rev >= 3 &&
 	    mac->mac_phy.phy_n->spur_avoid != BWN_SPUR_AVOID_DISABLE) {
-		uint8_t spuravoid = 0;
+		bhnd_pmu_spuravoid spuravoid = BHND_PMU_SPURAVOID_NONE;
 
 		if (mac->mac_phy.phy_n->spur_avoid == BWN_SPUR_AVOID_FORCE) {
-			spuravoid = 1;
+			spuravoid = BHND_PMU_SPURAVOID_M1;
 		} else if (phy->rev >= 19) {
 			/* TODO */
 		} else if (phy->rev >= 18) {
@@ -6447,19 +6531,20 @@ static void bwn_nphy_channel_setup(struct bwn_mac *mac,
 		} else if (phy->rev >= 7) {
 			if (!bwn_is_40mhz(mac)) { /* 20MHz */
 				if (ch == 13 || ch == 14 || ch == 153)
-					spuravoid = 1;
+					spuravoid = BHND_PMU_SPURAVOID_M1;
 			} else { /* 40 MHz */
 				if (ch == 54)
-					spuravoid = 1;
+					spuravoid = BHND_PMU_SPURAVOID_M1;
 			}
 		} else {
 			if (!bwn_is_40mhz(mac)) { /* 20MHz */
 				if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
-					spuravoid = 1;
+					spuravoid = BHND_PMU_SPURAVOID_M1;
 			} else { /* 40MHz */
 				if (nphy->aband_spurwar_en &&
-				    (ch == 38 || ch == 102 || ch == 118))
-					spuravoid = siba_get_chipid(sc->sc_dev) == 0x4716;
+				    (ch == 38 || ch == 102 || ch == 118) &&
+				    sc->sc_cid.chip_id == BHND_CHIPID_BCM4716)
+					spuravoid = BHND_PMU_SPURAVOID_M1;
 			}
 		}
 
@@ -6470,7 +6555,7 @@ static void bwn_nphy_channel_setup(struct bwn_mac *mac,
 		if (mac->mac_phy.rev == 3 || mac->mac_phy.rev == 4)
 			bwn_wireless_core_phy_pll_reset(mac);
 
-		if (spuravoid)
+		if (spuravoid != BHND_PMU_SPURAVOID_NONE)
 			BWN_PHY_SET(mac, BWN_NPHY_BBCFG, BWN_NPHY_BBCFG_RSTRX);
 		else
 			BWN_PHY_MASK(mac, BWN_NPHY_BBCFG,
@@ -6485,6 +6570,8 @@ static void bwn_nphy_channel_setup(struct bwn_mac *mac,
 
 	if (phy->rev >= 3)
 		bwn_nphy_spur_workaround(mac);
+
+	return (0);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
@@ -6499,6 +6586,7 @@ static int bwn_nphy_set_channel(struct bwn_mac *mac,
 	const struct bwn_nphy_chantabent_rev7 *tabent_r7 = NULL;
 	const struct bwn_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL;
 
+	int error;
 	uint8_t tmp;
 
 	if (phy->rev >= 19) {
@@ -6545,6 +6633,7 @@ static int bwn_nphy_set_channel(struct bwn_mac *mac,
 
 	if (phy->rev >= 19) {
 		/* TODO */
+		error = ENODEV;
 	} else if (phy->rev >= 7) {
 		const struct bwn_phy_n_sfo_cfg *phy_regs = tabent_r7 ?
 			&(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs);
@@ -6556,20 +6645,22 @@ static int bwn_nphy_set_channel(struct bwn_mac *mac,
 		}
 
 		bwn_radio_2057_setup(mac, tabent_r7, tabent_r7_2g);
-		bwn_nphy_channel_setup(mac, phy_regs, channel);
+		error = bwn_nphy_channel_setup(mac, phy_regs, channel);
 	} else if (phy->rev >= 3) {
 		tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 4 : 0;
 		BWN_RF_SETMASK(mac, 0x08, 0xFFFB, tmp);
 		bwn_radio_2056_setup(mac, tabent_r3);
-		bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs), channel);
+		error = bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs),
+		    channel);
 	} else {
 		tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 0x0020 : 0x0050;
 		BWN_RF_SETMASK(mac, B2055_MASTER1, 0xFF8F, tmp);
 		bwn_radio_2055_setup(mac, tabent_r2);
-		bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs), channel);
+		error = bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs),
+		    channel);
 	}
 
-	return 0;
+	return (error);
 }
 
 /**************************************************
@@ -6590,12 +6681,13 @@ bwn_nphy_op_allocate(struct bwn_mac *mac)
 	return 0;
 }
 
-void
+int
 bwn_nphy_op_prepare_structs(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
 	struct bwn_phy_n *nphy = phy->phy_n;
+	int error;
 
 	memset(nphy, 0, sizeof(*nphy));
 
@@ -6615,28 +6707,46 @@ bwn_nphy_op_prepare_structs(struct bwn_mac *mac)
 	nphy->txpwrctrl = false;
 	nphy->pwg_gain_5ghz = false;
 	if (mac->mac_phy.rev >= 3 ||
-	    (siba_get_pci_subvendor(sc->sc_dev) == PCI_VENDOR_APPLE &&
-	     (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12))) {
+	    (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE &&
+	     (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12))) {
 		nphy->txpwrctrl = true;
 		nphy->pwg_gain_5ghz = true;
-	} else if (siba_sprom_get_rev(sc->sc_dev) >= 4) {
+	} else if (sc->sc_board_info.board_srom_rev >= 4) {
 		if (mac->mac_phy.rev >= 2 &&
-		    (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_TXPWRCTRL_EN)) {
+		    (sc->sc_board_info.board_flags2 & BHND_BFL2_TXPWRCTRL_EN)) {
 			nphy->txpwrctrl = true;
-			if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) {
-				if ((siba_get_pci_device(sc->sc_dev) == 0x4328) ||
-				    (siba_get_pci_device(sc->sc_dev) == 0x432a))
-					nphy->pwg_gain_5ghz = true;
-			}
-		} else if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_5G_PWRGAIN) {
+			if ((sc->sc_board_info.board_devid == PCI_DEVID_BCM4321_D11N) ||
+			    (sc->sc_board_info.board_devid == PCI_DEVID_BCM4321_D11N5G))
+				nphy->pwg_gain_5ghz = true;
+		} else if (sc->sc_board_info.board_flags2 & BHND_BFL2_5G_PWRGAIN) {
 			nphy->pwg_gain_5ghz = true;
 		}
 	}
 
 	if (mac->mac_phy.rev >= 3) {
-		nphy->ipa2g_on = siba_sprom_get_fem_2ghz_extpa_gain(sc->sc_dev) == 2;
-		nphy->ipa5g_on = siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 2;
+		uint8_t extpa_gain2g, extpa_gain5g;
+
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev,
+		    BHND_NVAR_EXTPAGAIN2G, &extpa_gain2g);
+		if (error) {
+			BWN_ERRPRINTF(mac->mac_sc, "Error reading 2GHz EPA "
+			    "gain configuration from NVRAM: %d\n", error);
+			return (error);
+		}
+
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev,
+		    BHND_NVAR_EXTPAGAIN5G, &extpa_gain5g);
+		if (error) {
+			BWN_ERRPRINTF(mac->mac_sc, "Error reading 5GHz EPA "
+			    "gain configuration from NVRAM: %d\n", error);
+			return (error);
+		}
+
+		nphy->ipa2g_on = (extpa_gain2g == 2);
+		nphy->ipa5g_on = (extpa_gain5g == 2);
 	}
+
+	return (0);
 }
 
 void
diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h
index 3876a3e0db78..72a9fb920789 100644
--- a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h
+++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h
@@ -136,6 +136,7 @@ struct bwn_phy_n {
 	struct bwn_ppr tx_pwr_max_ppr;
 	uint16_t tx_pwr_last_recalc_freq;
 	int tx_pwr_last_recalc_limit;
+	uint8_t tsspos_2g;
 
 	uint8_t txrx_chain;
 	uint16_t tx_rx_cal_phy_saveregs[11];
@@ -167,7 +168,7 @@ struct bwn_phy_n {
 
 extern	bwn_txpwr_result_t bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi);
 extern	int bwn_nphy_op_allocate(struct bwn_mac *mac);
-extern	void bwn_nphy_op_prepare_structs(struct bwn_mac *mac);
+extern	int bwn_nphy_op_prepare_structs(struct bwn_mac *mac);
 extern	void bwn_nphy_op_free(struct bwn_mac *mac);
 extern	int bwn_nphy_op_init(struct bwn_mac *mac);
 extern	void bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, uint16_t set);
diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c
index d62911b51511..080a57ef9435 100644
--- a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c
+++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c
@@ -67,6 +67,9 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
+
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 #include <dev/bwn/if_bwn_debug.h>
@@ -74,8 +77,11 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_phy_common.h>
 
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h>
+#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h>
 
+#include "bhnd_nvram_map.h"
+
 #define ppr_for_each_entry(ppr, i, entry)				\
 	for (i = 0, entry = &(ppr)->__all_rates[i];			\
 	     i < BWN_PPR_RATES_NUM;					\
@@ -136,18 +142,21 @@ bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, struct bwn_ppr *ppr,
 				 bwn_phy_band_t band)
 {
 	struct bwn_softc *sc = mac->mac_sc;
-	struct siba_sprom_core_pwr_info core_pwr_info[4];
+	struct bwn_phy_n_core_pwr_info core_pwr_info[4];
 	struct bwn_ppr_rates *rates = &ppr->rates;
 	struct bwn_phy *phy = &mac->mac_phy;
+	const char *var_ofdmgpo, *var_mcsgpo_prefix;
 	uint8_t maxpwr, off;
 	uint32_t sprom_ofdm_po;
 	uint16_t sprom_mcs_po[8];
+	uint16_t cddpo, stbcpo;
 	uint8_t extra_cdd_po, extra_stbc_po;
+	int error;
 	int i;
 
 	for (i = 0; i < 4; i++) {
 		bzero(&core_pwr_info[i], sizeof(core_pwr_info[i]));
-		if (siba_sprom_get_core_power_info(sc->sc_dev, i,
+		if (bwn_nphy_get_core_power_info(mac, i,
 		    &core_pwr_info[i]) != 0) {
 			BWN_ERRPRINTF(mac->mac_sc,
 			    "%s: failed to get core_pwr_info for core %d\n",
@@ -156,38 +165,53 @@ bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, struct bwn_ppr *ppr,
 		}
 	}
 
+	error = bhnd_nvram_getvar_uint16(sc->sc_dev, BHND_NVAR_CDDPO, &cddpo);
+	if (error) {
+		BWN_ERRPRINTF(mac->mac_sc, "NVRAM variable %s unreadable: %d\n",
+		     BHND_NVAR_CDDPO, error);
+		return (false);
+	}
+
+	error = bhnd_nvram_getvar_uint16(sc->sc_dev, BHND_NVAR_STBCPO, &stbcpo);
+	if (error) {
+		BWN_ERRPRINTF(mac->mac_sc, "NVRAM variable %s unreadable: %d\n",
+		     BHND_NVAR_STBCPO, error);
+		return (false);
+	}
+
 	switch (band) {
 	case BWN_PHY_BAND_2G:
 		maxpwr = min(core_pwr_info[0].maxpwr_2g,
 			     core_pwr_info[1].maxpwr_2g);
-		sprom_ofdm_po = siba_sprom_get_ofdm2gpo(sc->sc_dev);
-		siba_sprom_get_mcs2gpo(sc->sc_dev, sprom_mcs_po);
-		extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 0) & 0xf;
-		extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 0) & 0xf;
+
+		var_ofdmgpo = BHND_NVAR_OFDM2GPO;
+		var_mcsgpo_prefix = "mcs2gpo";
+		extra_cdd_po = (cddpo >> 0) & 0xf;
+		extra_stbc_po = (stbcpo >> 0) & 0xf;
 		break;
 	case BWN_PHY_BAND_5G_LO:
 		maxpwr = min(core_pwr_info[0].maxpwr_5gl,
 			     core_pwr_info[1].maxpwr_5gl);
-		sprom_ofdm_po = siba_sprom_get_ofdm5glpo(sc->sc_dev);
-		siba_sprom_get_mcs5glpo(sc->sc_dev, sprom_mcs_po);
-		extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 8) & 0xf;
-		extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 8) & 0xf;
+		var_ofdmgpo = BHND_NVAR_OFDM5GLPO;
+		var_mcsgpo_prefix = "mcs5glpo";
+		extra_cdd_po = (cddpo >> 8) & 0xf;
+		extra_stbc_po = (stbcpo >> 8) & 0xf;
 		break;
 	case BWN_PHY_BAND_5G_MI:
 		maxpwr = min(core_pwr_info[0].maxpwr_5g,
 			     core_pwr_info[1].maxpwr_5g);
-		sprom_ofdm_po = siba_sprom_get_ofdm5gpo(sc->sc_dev);
-		siba_sprom_get_mcs5gpo(sc->sc_dev, sprom_mcs_po);
-		extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 4) & 0xf;
-		extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 4) & 0xf;
+		var_ofdmgpo = BHND_NVAR_OFDM5GPO;
+		var_mcsgpo_prefix = "mcs5gpo";
+		extra_cdd_po = (cddpo >> 4) & 0xf;
+		extra_stbc_po = (stbcpo >> 4) & 0xf;
 		break;
 	case BWN_PHY_BAND_5G_HI:
 		maxpwr = min(core_pwr_info[0].maxpwr_5gh,
 			     core_pwr_info[1].maxpwr_5gh);
-		sprom_ofdm_po = siba_sprom_get_ofdm5ghpo(sc->sc_dev);
-		siba_sprom_get_mcs5ghpo(sc->sc_dev, sprom_mcs_po);
-		extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 12) & 0xf;
-		extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 12) & 0xf;
+		var_ofdmgpo = BHND_NVAR_OFDM5GHPO;
+		var_mcsgpo_prefix = "mcs5ghpo";
+		extra_cdd_po = (cddpo >> 12) & 0xf;
+		extra_stbc_po = (stbcpo >> 12) & 0xf;
 		break;
 	default:
 		device_printf(mac->mac_sc->sc_dev, "%s: invalid band (%d)\n",
@@ -196,9 +220,48 @@ bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, struct bwn_ppr *ppr,
 		return false;
 	}
 
+	error = bhnd_nvram_getvar_uint32(sc->sc_dev, var_ofdmgpo,
+	    &sprom_ofdm_po);
+	if (error) {
+		device_printf(sc->sc_dev, "NVRAM variable %s unreadable: %d\n",
+		     var_ofdmgpo, error);
+		return (false);
+	}
+
+	for (size_t i = 0; i < nitems(sprom_mcs_po); i++) {
+		char	var[strlen(var_mcsgpo_prefix) + sizeof("XX")];
+		int	ret;
+
+		/* mcs[25]g[lh]?po[0-9] */
+		ret = snprintf(var, sizeof(var), "%s%zu", var_mcsgpo_prefix, i);
+		if (ret >= sizeof(var)) {
+			device_printf(sc->sc_dev, "buffer too small for "
+			    "%s%zu\n", var_mcsgpo_prefix, i);
+			return (false);
+		}
+
+		error = bhnd_nvram_getvar_uint16(sc->sc_dev, var,
+		    &sprom_mcs_po[i]);
+		if (error) {
+			device_printf(sc->sc_dev, "NVRAM variable %s "
+			    "unreadable: %d\n", var, error);
+			return (false);
+		}
+	}
+
 	if (band == BWN_BAND_2G) {
+		uint16_t ck2gpo;
+
+		error = bhnd_nvram_getvar_uint16(sc->sc_dev, BHND_NVAR_CCK2GPO,
+		    &ck2gpo);
+		if (error) {
+			device_printf(sc->sc_dev, "NVRAM variable %s "
+			    "unreadable: %d\n", BHND_NVAR_CCK2GPO, error);
+			return (false);
+		}
+
 		for (i = 0; i < 4; i++) {
-			off = ((siba_sprom_get_cck2gpo(sc->sc_dev) >> (i * 4)) & 0xf) * 2;
+			off = ((ck2gpo >> (i * 4)) & 0xf) * 2;
 			rates->cck[i] = maxpwr - off;
 		}
 	}
diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c
new file mode 100644
index 000000000000..25c1c82dca5b
--- /dev/null
+++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c
@@ -0,0 +1,181 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * Copyright (c) 2017 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <net/ethernet.h>
+#include <net/if.h>
+#include <net/if_var.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_llc.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_radiotap.h>
+#include <net80211/ieee80211_regdomain.h>
+#include <net80211/ieee80211_phy.h>
+#include <net80211/ieee80211_ratectl.h>
+
+#include <dev/bhnd/bhnd.h>
+
+#include <dev/bwn/if_bwnvar.h>
+
+#include "if_bwn_phy_n_sprom.h"
+
+#include "bhnd_nvram_map.h"
+
+
+/* Core power NVRAM variables, indexed by D11 core unit number */
+static const struct bwn_nphy_power_vars {
+	const char *itt2ga;
+	const char *itt5ga;
+	const char *maxp2ga;
+	const char *pa2ga;
+	const char *pa5ga;
+} bwn_nphy_power_vars[BWN_NPHY_NUM_CORE_PWR] = {
+#define	BHND_POWER_NVAR(_idx)					\
+	{ BHND_NVAR_ITT2GA ## _idx, BHND_NVAR_ITT5GA ## _idx,	\
+	  BHND_NVAR_MAXP2GA ## _idx, BHND_NVAR_PA2GA ## _idx,	\
+	  BHND_NVAR_PA5GA ## _idx }
+	BHND_POWER_NVAR(0),
+	BHND_POWER_NVAR(1),
+	BHND_POWER_NVAR(2),
+	BHND_POWER_NVAR(3)
+#undef BHND_POWER_NVAR
+};
+
+static int
+bwn_nphy_get_core_power_info_r11(struct bwn_softc *sc,
+    const struct bwn_nphy_power_vars *v, struct bwn_phy_n_core_pwr_info *c)
+{
+	int16_t	pa5ga[12];
+	int	error;
+
+	/* BHND_NVAR_PA2GA[core] */
+	error = bhnd_nvram_getvar_array(sc->sc_dev, v->pa2ga, c->pa_2g,
+	    sizeof(c->pa_2g), BHND_NVRAM_TYPE_INT16);
+	if (error)
+		return (error);
+
+	/* 
+	 * BHND_NVAR_PA5GA
+	 * 
+	 * The NVRAM variable is defined as a single pa5ga[12] array; we have
+	 * to split this into pa_5gl[4], pa_5g[4], and pa_5gh[4] for use
+	 * by bwn(4);
+	 */
+	_Static_assert(nitems(pa5ga) == nitems(c->pa_5g) + nitems(c->pa_5gh) +
+	    nitems(c->pa_5gl), "cannot split pa5ga into pa_5gl/pa_5g/pa_5gh");
+
+	error = bhnd_nvram_getvar_array(sc->sc_dev, v->pa5ga, pa5ga,
+	    sizeof(pa5ga), BHND_NVRAM_TYPE_INT16);
+	if (error)
+		return (error);
+
+	memcpy(c->pa_5gl, &pa5ga[0], sizeof(c->pa_5gl));
+	memcpy(c->pa_5g, &pa5ga[4], sizeof(c->pa_5g));
+	memcpy(c->pa_5gh, &pa5ga[8], sizeof(c->pa_5gh));
+	return (0);
+}
+
+static int
+bwn_nphy_get_core_power_info_r4_r10(struct bwn_softc *sc,
+    const struct bwn_nphy_power_vars *v, struct bwn_phy_n_core_pwr_info *c)
+{
+	int error;
+
+	/* BHND_NVAR_ITT2GA[core] */
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, v->itt2ga, &c->itssi_2g);
+	if (error)
+		return (error);
+
+	/* BHND_NVAR_ITT5GA[core] */
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, v->itt5ga, &c->itssi_5g);
+	if (error)
+		return (error);
+
+	return (0);
+}
+
+/*
+ * siba_sprom_get_core_power_info()
+ *
+ * Referenced by:
+ *   bwn_nphy_tx_power_ctl_setup()
+ *   bwn_ppr_load_max_from_sprom()
+ */
+int
+bwn_nphy_get_core_power_info(struct bwn_mac *mac, int core,
+    struct bwn_phy_n_core_pwr_info *c)
+{
+	struct bwn_softc			*sc;
+	const struct bwn_nphy_power_vars	*v;
+	uint8_t					 sromrev;
+	int					 error;
+
+	sc = mac->mac_sc;
+
+	if (core < 0 || core >= nitems(bwn_nphy_power_vars))
+		return (EINVAL);
+
+	sromrev = sc->sc_board_info.board_srom_rev;
+	if (sromrev < 4)
+		return (ENXIO);
+
+	v = &bwn_nphy_power_vars[core];
+
+	/* Any power variables not found in NVRAM (or returning a
+	 * shorter array for a particular NVRAM revision) should be zero
+	 * initialized */
+	memset(c, 0x0, sizeof(*c));
+
+	/* Populate SPROM revision-independent values */
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, v->maxp2ga, &c->maxpwr_2g);
+	if (error)
+		return (error);
+
+	/* Populate SPROM revision-specific values */
+	if (sromrev >= 4 && sromrev <= 10)
+		return (bwn_nphy_get_core_power_info_r4_r10(sc, v, c));
+	else
+		return (bwn_nphy_get_core_power_info_r11(sc, v, c));
+}
diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h
new file mode 100644
index 000000000000..0dd038c069d1
--- /dev/null
+++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h
@@ -0,0 +1,56 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2017 The FreeBSD Foundation
+ * Copyright (c) 2016 Landon J. Fuller <landonf@FreeBSD.org>
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _IF_BWN_PHY_N_SPROM_H_
+#define _IF_BWN_PHY_N_SPROM_H_
+
+struct bwn_mac;
+
+#define	BWN_NPHY_NUM_CORE_PWR	4
+
+struct bwn_phy_n_core_pwr_info {
+    uint8_t itssi_2g;
+    uint8_t itssi_5g;
+    uint8_t maxpwr_2g;
+    uint8_t maxpwr_5gl;
+    uint8_t maxpwr_5g;
+    uint8_t maxpwr_5gh;
+    int16_t pa_2g[3];
+    int16_t pa_5gl[4];
+    int16_t pa_5g[4];
+    int16_t pa_5gh[4];
+};
+
+int	bwn_nphy_get_core_power_info(struct bwn_mac *mac, int core,
+	    struct bwn_phy_n_core_pwr_info *c);
+
+#endif /* _IF_BWN_PHY_N_SPROM_H_ */
diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c
index 2a3725caa632..b59271f65933 100644
--- a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c
+++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c
@@ -68,6 +68,9 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 #include <dev/bwn/if_bwn_debug.h>
@@ -77,6 +80,8 @@ __FBSDID("$FreeBSD$");
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h>
 #include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h>
 
+#include "bhnd_nvram_map.h"
+
 static const uint8_t bwn_ntab_adjustpower0[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -3418,8 +3423,8 @@ void bwn_ntab_read_bulk(struct bwn_mac *mac, uint32_t offset,
 
 	for (i = 0; i < nr_elements; i++) {
 		/* Auto increment broken + caching issue on BCM43224? */
-		if (siba_get_chipid(sc->sc_dev) == 43224 &&
-		    siba_get_revid(sc->sc_dev) == 1) {
+		if (sc->sc_cid.chip_id == BHND_CHIPID_BCM43224 &&
+		    bhnd_get_hwrev(sc->sc_dev) == 1) {
 			BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO);
 			BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset + i);
 		}
@@ -3504,8 +3509,8 @@ void bwn_ntab_write_bulk(struct bwn_mac *mac, uint32_t offset,
 	for (i = 0; i < nr_elements; i++) {
 		/* Auto increment broken + caching issue on BCM43224? */
 		if ((offset >> 10) == 9 &&
-		    siba_get_chipid(sc->sc_dev) == 43224 &&
-		    siba_get_revid(sc->sc_dev) == 1) {
+		    sc->sc_cid.chip_id == BHND_CHIPID_BCM43224 &&
+		    bhnd_get_hwrev(sc->sc_dev) == 1) {
 			BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO);
 			BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset + i);
 		}
@@ -3557,12 +3562,30 @@ static void bwn_nphy_tables_init_shared_lut(struct bwn_mac *mac)
 	ntab_upload(mac, BWN_NTAB_C1_LOFEEDTH_R3, bwn_ntab_loftlt1_r3);
 }
 
+static int bwn_nphy_tables_get_antswlut(struct bwn_mac *mac, uint8_t *antswlut)
+{
+	struct ieee80211com	*ic = &mac->mac_sc->sc_ic;
+	struct bwn_softc	*sc = mac->mac_sc;
+	const char		*antswlut_var;
+	int			 error;
+
+	if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
+		antswlut_var = BHND_NVAR_ANTSWCTL5G;
+	else
+		antswlut_var = BHND_NVAR_ANTSWCTL2G;
+
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, antswlut_var, antswlut);
+	if (error)
+		BWN_ERRPRINTF(mac->mac_sc, "NVRAM variable %s unreadable: %d",
+		    antswlut_var, error);
+
+	return (error);
+}
+
 static void bwn_nphy_tables_init_rev7_volatile(struct bwn_mac *mac)
 {
-	struct ieee80211com *ic = &mac->mac_sc->sc_ic;
-	struct bwn_softc *sc = mac->mac_sc;
-	uint8_t antswlut;
-	int core, offset, i;
+	int	core, error, offset, i;
+	uint8_t	antswlut;
 
 	const int antswlut0_offsets[] = { 0, 4, 8, }; /* Offsets for values */
 	const uint8_t antswlut0_values[][3] = {
@@ -3570,10 +3593,8 @@ static void bwn_nphy_tables_init_rev7_volatile(struct bwn_mac *mac)
 		{ 0x2, 0x18, 0x2 }, /* Core 1 */
 	};
 
-	if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
-		antswlut = siba_sprom_get_fem_5ghz_antswlut(sc->sc_dev);
-	else
-		antswlut = siba_sprom_get_fem_2ghz_antswlut(sc->sc_dev);
+	if ((error = bwn_nphy_tables_get_antswlut(mac, &antswlut)))
+		return;
 
 	switch (antswlut) {
 	case 0:
@@ -3631,14 +3652,11 @@ static void bwn_nphy_tables_init_rev7(struct bwn_mac *mac)
 
 static void bwn_nphy_tables_init_rev3(struct bwn_mac *mac)
 {
-	struct ieee80211com *ic = &mac->mac_sc->sc_ic;
-	struct bwn_softc *sc = mac->mac_sc;
-	uint8_t antswlut;
+	int	error;
+	uint8_t	antswlut;
 
-	if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
-		antswlut = siba_sprom_get_fem_5ghz_antswlut(sc->sc_dev);
-	else
-		antswlut = siba_sprom_get_fem_2ghz_antswlut(sc->sc_dev);
+	if ((error = bwn_nphy_tables_get_antswlut(mac, &antswlut)))
+		return;
 
 	/* Static tables */
 	if (mac->mac_phy.phy_do_full_init) {
@@ -3738,7 +3756,7 @@ static const uint32_t *bwn_nphy_get_ipa_gain_table(struct bwn_mac *mac)
 				return bwn_ntab_tx_gain_ipa_2057_rev5_2g;
 			break;
 		case 6:
-			if (siba_get_chipid(sc->sc_dev) == 47162) /* BCM47612 */
+			if (sc->sc_cid.chip_id == BHND_CHIPID_BCM47162)
 				return bwn_ntab_tx_gain_ipa_rev5_2g;
 			return bwn_ntab_tx_gain_ipa_rev6_2g;
 		case 5:
@@ -3772,7 +3790,8 @@ const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac)
 	struct ieee80211com *ic = &mac->mac_sc->sc_ic;
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
-	int is_5ghz;
+	int error, is_5ghz;
+	uint8_t extpa_gain;
 
 	/* XXX ideally we'd have is2, is5, etc */
 	is_5ghz = !! IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan);
@@ -3790,7 +3809,16 @@ const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac)
 		case 5:
 			return bwn_ntab_tx_gain_epa_rev5_5g;
 		case 4:
-			return siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 3 ?
+			error = bhnd_nvram_getvar_uint8(sc->sc_dev,
+			    BHND_NVAR_EXTPAGAIN5G, &extpa_gain);
+			if (error) {
+				BWN_ERRPRINTF(mac->mac_sc, "Error reading EPA "
+				    "gain configuration (%s) from NVRAM: %d\n",
+				    BHND_NVAR_EXTPAGAIN5G, error);
+				return (NULL);
+			}
+
+			return (extpa_gain == 3) ?
 				bwn_ntab_tx_gain_epa_rev4_5g :
 				bwn_ntab_tx_gain_epa_rev4_hi_pwr_5g;
 		case 3:
@@ -3804,7 +3832,16 @@ const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac)
 		switch (phy->rev) {
 		case 6:
 		case 5:
-			if (siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 3)
+			error = bhnd_nvram_getvar_uint8(sc->sc_dev,
+			    BHND_NVAR_EXTPAGAIN2G, &extpa_gain);
+			if (error) {
+				BWN_ERRPRINTF(mac->mac_sc, "Error reading EPA "
+				    "gain configuration (%s) from NVRAM: %d\n",
+				    BHND_NVAR_EXTPAGAIN2G, error);
+				return (NULL);
+			}
+
+			if (extpa_gain == 3)
 				return bwn_ntab_tx_gain_epa_rev3_hi_pwr_2g;
 			/* fall through */
 		case 4:
@@ -3879,7 +3916,13 @@ struct bwn_nphy_gain_ctl_workaround_entry *bwn_nphy_get_gain_ctl_workaround_ent(
 
 	/* Some workarounds to the workarounds... */
 	if (!ghz5) {
-		uint8_t tr_iso = siba_sprom_get_fem_2ghz_tr_iso(sc->sc_dev);
+		uint8_t	tr_iso;
+		int	error;
+
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_TRISO2G,
+		    &tr_iso);
+		BWN_ERRPRINTF(mac->mac_sc, "Error reading %s from NVRAM: %d\n",
+		    BHND_NVAR_TRISO2G, error);
 
 		if (tr_iso > 7)
 			tr_iso = 3;
diff --git a/sys/modules/Makefile b/sys/modules/Makefile
index 1dabb3deef95..afdacfeb55d2 100644
--- a/sys/modules/Makefile
+++ b/sys/modules/Makefile
@@ -73,7 +73,6 @@ SUBDIR=	\
 	bridgestp \
 	bwi \
 	bwn \
-	bwn_pci \
 	${_bytgpio} \
 	cam \
 	${_cardbus} \
@@ -351,7 +350,6 @@ SUBDIR=	\
 	sge \
 	${_sgx} \
 	${_sgx_linux} \
-	siba_bwn \
 	siftr \
 	siis \
 	sis \
diff --git a/sys/modules/bwn/Makefile b/sys/modules/bwn/Makefile
index 2ba00a2ce517..2ce6493046b6 100644
--- a/sys/modules/bwn/Makefile
+++ b/sys/modules/bwn/Makefile
@@ -4,7 +4,7 @@
 
 KMOD=	if_bwn
 SRCS=	if_bwn.c if_bwnreg.h if_bwnvar.h
-SRCS+=	if_bwn_siba.c if_bwn_bhnd.c if_bwn_siba_compat.c
+SRCS+=	if_bwn_pci.c
 SRCS+=	if_bwn_util.c
 
 # PHY
@@ -19,6 +19,10 @@ SRCS+=	bhnd_bus_if.h \
 	bhnd_pwrctl_if.h
 SRCS+=	bhnd_nvram_map.h
 
+# BHNDB
+SRCS+=	bhndb_bus_if.h \
+	bhndb_if.h
+
 # Other
 SRCS+=	device_if.h bus_if.h gpio_if.h pci_if.h opt_bwn.h opt_wlan.h
 
@@ -28,6 +32,7 @@ SRCS+=	device_if.h bus_if.h gpio_if.h pci_if.h opt_bwn.h opt_wlan.h
 SRCS.BWN_GPL_PHY+=  if_bwn_radio_2055.c
 SRCS.BWN_GPL_PHY+=  if_bwn_radio_2056.c
 SRCS.BWN_GPL_PHY+=  if_bwn_radio_2057.c
+SRCS.BWN_GPL_PHY+=  if_bwn_phy_n_sprom.c
 SRCS.BWN_GPL_PHY+=  if_bwn_phy_n_tables.c
 SRCS.BWN_GPL_PHY+=  if_bwn_phy_n_ppr.c
 SRCS.BWN_GPL_PHY+=  if_bwn_phy_n_core.c
diff --git a/sys/modules/bwn_pci/Makefile b/sys/modules/bwn_pci/Makefile
deleted file mode 100644
index 3c760413b788..000000000000
--- a/sys/modules/bwn_pci/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${SRCTOP}/sys/dev/bwn
-
-KMOD=	if_bwn_pci
-SRCS=	if_bwn_pci.c
-
-SRCS+=	bhnd_bus_if.h bhndb_bus_if.h \
-	bhndb_if.h
-SRCS+=	device_if.h bus_if.h pci_if.h \
-	opt_bwn.h opt_wlan.h opt_global.h
-
-.include <bsd.kmod.mk>
diff --git a/sys/modules/siba_bwn/Makefile b/sys/modules/siba_bwn/Makefile
deleted file mode 100644
index 9091f2338757..000000000000
--- a/sys/modules/siba_bwn/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${SRCTOP}/sys/dev/siba
-
-KMOD=	siba_bwn
-SRCS=	siba_core.c siba_bwn.c sibareg.h sibavar.h
-SRCS+=	device_if.h bus_if.h pci_if.h opt_siba.h
-
-.include <bsd.kmod.mk>