igb: Report 82580 memory ECC errorsHEADmain

82580 exposes clear-on-read, saturating corrected error counters for
the receive and transmit packet buffers.  Its two PCIe command memories
expose RW1C indications for uncorrectable ECC errors.

Sample the packet buffer counters and PCIe indications from the regular
hardware statistics update.  Fatal recovery samples the PCIe indications
from the serialized admin path rather than the interrupt filter.  Thus,
either the regular statistics pass or recovery reads and clears each
indication, but they cannot both account it.  Also preserve indications
observed while initialization is completing.

Expose the exact packet buffer error total and observed PCIe command
memory indications under the memory_errors sysctl node.  Multiple PCIe
errors between samples can collapse into one indication per memory.

Validated on an Intel I340-T2 (82580, revision 1).  A clean boot and
three down/up cycles left the packet-buffer, PCIe, and region-specific
counters at zero.  Synthetic ICS.FER events advanced fatal_unknown and
fatal_resets exactly once on the targeted function without changing the
sibling or ECC counters.

The 82580 datasheet exposes no ECC or parity error injection register,
so corrected packet buffer and PCIe ECC accounting could not be forced
independently.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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