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| author | Osvaldo Janeri Filho <ojanerif@amd.com> | 2026-09-09 15:13:52 +0000 |
|---|---|---|
| committer | Mitchell Horne <mhorne@FreeBSD.org> | 2026-09-21 22:49:42 +0000 |
| commit | 8a0cab240f2146a000396c411df471df4b75bb9d (patch) | |
| tree | 5a7f9b3a6e3d7eafc77826f8001e2434f7801cf1 /tests/atf_python/sys/netpfil/(public-mirror) | |
| parent | c745fccd9b2647c1f84f8e38b3992640ea34c50d (diff) | |
AMD_NPMCS_MAX = 342 (16 core + 6 L3 + 64 DF + 256 UMC). On a Zen 4
EPYC 9654 with 6 core, 6 L3, 16 DF, and 4 UMC counters, only 32
descriptors are needed; the static arrays over-allocate by ~10x.
Replace both amd_pmcdesc[AMD_NPMCS_MAX] and per-CPU pc_amdpmcs[AMD_NPMCS_MAX]
with mallocarray() sized to the actual registered PMC count:
- amd_pmcdesc: allocated in pmc_amd_initialize()
- pc_amdpmcs: allocated per-CPU in amd_pcpu_init(), freed in fini()
Normalize amd_l3_npmcs and amd_df_npmcs against the AMDID2_PTSCEL2I
and AMDID2_PNXC feature bits before computing npmcs_total, so that
allocation, registration, and amd_get_msr() row offsets are all derived
from the same values. Previously the ternary in npmcs_total excluded
L3/DF from the allocation while the globals retained their defaults,
causing amd_get_msr() to miscompute DF row offsets when L3 is absent.
amd_umc_npmcs comes from CPUID Fn8000_0022h EBX[23:16] (NumUMCCounters)
and is zero when the leaf is absent, so no additional feature flag is
needed. See AMD64 APM Vol.3 Appendix E.
Fix three error-path memory leaks: amd_hwcheck() failure, goto error,
and finalize. Reset amd_npmcs = 0 on the error path.
Tested on AMD EPYC 9654 (Zen 4, Family 19h Model 11h, 192 threads).
Full PMC test suite (IBS/UMCDF/PMC/L3/DF/TSC): 0 failures.
Signed-off-by: Osvaldo Janeri Filho <ojanerif@amd.com>
Reviewed by: mhorne
MFC after: 1 week
Sponsored by: AMD
Pull Request: https://github.com/freebsd/freebsd-src/pull/2415
Diffstat (limited to 'tests/atf_python/sys/netpfil/(public-mirror)')
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