aboutsummaryrefslogtreecommitdiff
path: root/usr.sbin/pim6sd/(developers-only)
diff options
context:
space:
mode:
authorAlan Cox <alc@FreeBSD.org>2025-06-28 19:49:26 +0000
committerAlan Cox <alc@FreeBSD.org>2025-07-03 21:30:02 +0000
commit1c1acaf6858be301384fd20b402cf2df831507a7 (patch)
tree9a2594bb95ea16cb3c1e2e7acdca7de55eb95187 /usr.sbin/pim6sd/(developers-only)
parent906d7a4b521c19b2b1ae3ec844b5d4626f2fd529 (diff)
amd64: enable EFER.TCEHEADmain
Setting this option tells AMD processors that targeted TLB invalidation instructions, such as invlpg, only have to invalidate cached entries from the upper levels of the page table that lie along the path to the targeted virtual address. Otherwise, by default, all cached entries from the upper levels of the page table are invalidated. After unmapping a page table page we always perform a TLB invalidation that will invalidate any cached references to that page table page, so this option is safe to enable. Reviewed by: kib, markj Tested by: dougm Differential Revision: https://reviews.freebsd.org/D51093
Diffstat (limited to 'usr.sbin/pim6sd/(developers-only)')
0 files changed, 0 insertions, 0 deletions