e1000: Report corrected I210 and I211 ECC errorsHEADmain

I210 and I211 do not interrupt for corrected internal ECC errors.
Instead, the DMA packet-buffer and PCIe memories expose sticky status
bits in PBECCSTS and PCIEECCSTS.

Sample these bits with the regular hardware statistics update, preserve
the I210/I211 PBECCSTS enable state while clearing its RW1C indication,
and expose separate counters for the DMA packet buffer, PCIe transmit
data, and PCIe retry buffer.

The counters represent observed indications rather than exact error
counts because multiple corrections between samples collapse into one
sticky status bit.

Hardware validation used an I210 revision 3.  Unlike I225 and I226, the
published I210/I211 register definitions do not expose self-clearing
injectors for these corrected ECC memories.  The three counter sysctls
were present and remained zero under line-rate traffic and three fatal
LAN parity recoveries.  PBECCSTS.ECC_ENABLE remained set after every
reset.  Actual corrected-error accounting was therefore not injected.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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