693 files changed, 81669 insertions, 14079 deletions

diff --git a/.cirrus.yml b/.cirrus.yml
index 84efa04f1ccb..b5c96820c192 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -4,13 +4,13 @@ compute_engine_instance:
   # gcloud compute images list --project freebsd-org-cloud-dev --no-standard-images
   platform: freebsd
   image_project: freebsd-org-cloud-dev
-  image: freebsd-14-2-release-amd64-ufs
+  image: freebsd-14-3-release-amd64-ufs
   cpu: 8
   memory: 8G
   disk: 40
 
 env:
-  PKG_FORMAT: tar
+  PKG_LEVEL: 1
 
 task:
   matrix:
@@ -154,13 +154,13 @@ task:
   - su user -c "git config --global --add safe.directory $(pwd -P)"
 
   build_world_script:
-  - su user -c "make -j$(sysctl -n hw.ncpu) ${EXTRA_MAKE_FLAGS} CROSS_TOOLCHAIN=${TOOLCHAIN} WITHOUT_TOOLCHAIN=yes buildworld"
+  - su user -c "make -j$(nproc) ${EXTRA_MAKE_FLAGS} CROSS_TOOLCHAIN=${TOOLCHAIN} WITHOUT_TOOLCHAIN=yes buildworld"
 
   build_kernel_script:
-  - su user -c "make -j$(sysctl -n hw.ncpu) CROSS_TOOLCHAIN=${TOOLCHAIN} WITHOUT_TOOLCHAIN=yes buildkernel"
+  - su user -c "make -j$(nproc) CROSS_TOOLCHAIN=${TOOLCHAIN} WITHOUT_TOOLCHAIN=yes buildkernel"
 
   package_script:
-  - su user -c "make CROSS_TOOLCHAIN=${TOOLCHAIN} WITHOUT_TOOLCHAIN=yes packages"
+  - su user -c "make -j$(nproc) CROSS_TOOLCHAIN=${TOOLCHAIN} WITHOUT_TOOLCHAIN=yes packages"
 
   package_check_script:
   - su user -c "/usr/libexec/flua tools/pkgbase/metalog_reader.lua -c /usr/obj/$(pwd -P)/${TARGET}.${TARGET_ARCH}/worldstage/METALOG"
diff --git a/.github/workflows/cross-bootstrap-tools.yml b/.github/workflows/cross-bootstrap-tools.yml
index 8f0dd933ef09..a99c3d31f2f1 100644
--- a/.github/workflows/cross-bootstrap-tools.yml
+++ b/.github/workflows/cross-bootstrap-tools.yml
@@ -22,9 +22,9 @@ jobs:
         include:
           # TODO: both Ubuntu and macOS have bmake packages, we should try them instead of bootstrapping our own copy.
           - os: ubuntu-22.04
-            compiler: clang-14
-            cross-bindir: /usr/lib/llvm-14/bin
-            pkgs: bmake libarchive-dev clang-14 lld-14
+            compiler: clang-15
+            cross-bindir: /usr/lib/llvm-15/bin
+            pkgs: bmake libarchive-dev clang-15 lld-15
           - os: ubuntu-24.04
             compiler: clang-18
             cross-bindir: /usr/lib/llvm-18/bin
diff --git a/Makefile b/Makefile
index 383430307495..664f31a48abf 100644
--- a/Makefile
+++ b/Makefile
@@ -219,6 +219,8 @@ META_TGT_WHITELIST+=	build${libcompat}
 .ORDER: buildworld distribute
 .ORDER: buildworld distributeworld
 .ORDER: buildworld buildkernel
+.ORDER: buildworld packages
+.ORDER: buildworld update-packages
 .ORDER: distrib-dirs distribute
 .ORDER: distrib-dirs distributeworld
 .ORDER: distrib-dirs installworld
@@ -232,6 +234,8 @@ META_TGT_WHITELIST+=	build${libcompat}
 .ORDER: buildkernel installkernel.debug
 .ORDER: buildkernel reinstallkernel
 .ORDER: buildkernel reinstallkernel.debug
+.ORDER: buildkernel packages
+.ORDER: buildkernel update-packages
 .ORDER: kernel-toolchain buildkernel
 
 # Only sanitize PATH on FreeBSD.
diff --git a/Makefile.inc1 b/Makefile.inc1
index 92570d1d2fb9..9dc4f2db4a6c 100644
--- a/Makefile.inc1
+++ b/Makefile.inc1
@@ -198,13 +198,18 @@ _GCC_BROKEN=boot code linker script issues.
 .endif
 
 .if ${.MAKE.OS} != "FreeBSD"
-CROSSBUILD_HOST=${.MAKE.OS}
+CROSSBUILD_HOST=${.MAKE.OS} # Unset for native FreeBSD builds
 .if ${.MAKE.OS} != "Linux" && ${.MAKE.OS} != "Darwin"
 .warning Unsupported crossbuild system: ${.MAKE.OS}. Build will probably fail!
 .endif
+.endif
 # We need to force NO_ROOT/DB_FROM_SRC builds when building on other operating
 # systems since the BSD.foo.dist specs contain users and groups that do not
-# exist by default on a Linux/MacOS system.
+# exist by default on a Linux/MacOS system.  The distribute* and package*
+# targets used for install media legacy distribution sets also always use and
+# require NO_ROOT mode.
+.if defined(CROSSBUILD_HOST) || make(distributeworld) || make(packageworld) || \
+    make(distributekernel) || make(packagekernel)
 NO_ROOT:=	1
 DB_FROM_SRC:=	1
 .export NO_ROOT
@@ -518,25 +523,6 @@ BUILDENV_SHELL?=/bin/sh
 .endif
 
 .if !defined(_MKSHOWCONFIG)
-.if !defined(VCS_REVISION) || empty(VCS_REVISION)
-.if !defined(SVNVERSION_CMD) || empty(SVNVERSION_CMD)
-. for _D in ${PATH:S,:, ,g}
-.  if exists(${_D}/svnversion)
-SVNVERSION_CMD?=${_D}/svnversion
-.  endif
-.  if exists(${_D}/svnliteversion)
-SVNVERSION_CMD?=${_D}/svnliteversion
-.  endif
-. endfor
-.endif
-.if defined(SVNVERSION_CMD) && !empty(SVNVERSION_CMD)
-_VCS_REVISION?=	$$(eval ${SVNVERSION_CMD} ${SRCDIR})
-. if !empty(_VCS_REVISION)
-VCS_REVISION=	$$(echo r${_VCS_REVISION})
-.export VCS_REVISION
-. endif
-.endif
-.endif
 
 .if !defined(GIT_CMD) || empty(GIT_CMD)
 . for _P in /usr/bin /usr/local/bin
@@ -598,6 +584,7 @@ EXTRA_REVISION=	p${_BRANCH:C/.*-p([0-9]+$)/\1/}
 .if !defined(PKG_VERSION)
 PKG_VERSION:=	${_PKG_REVISION}${EXTRA_REVISION:C/[[:space:]]//g}
 .endif
+
 .endif	# !defined(_MKSHOWCONFIG)
 
 .if make(*package*)
@@ -2220,9 +2207,6 @@ create-world-package-${pkgname}: .PHONY
 		/^name/ { printf("===> Creating %s-", $$2); next } \
 		/^version/ { print $$2; next } \
 		' ${WSTAGEDIR}/${pkgname}.ucl
-	@if [ "${pkgname}" == "runtime" ]; then \
-		sed -i '' -e "s/%VCS_REVISION%/${VCS_REVISION}/" ${WSTAGEDIR}/${pkgname}.ucl ; \
-	fi
 	${PKG_CMD} -o ABI=${PKG_ABI} -o ALLOW_BASE_SHLIBS=yes \
 		-o OSVERSION="${SRCRELDATE}" \
 		create -f ${PKG_FORMAT} ${PKG_CLEVEL} \
@@ -2543,6 +2527,10 @@ ${_bt}-usr.sbin/kldxref: ${_bt_libelf_depend} ${_bt_libkldelf_depend}
 .if ${BOOTSTRAPPING} < 1300059
 ${_bt}-libexec/flua: ${_bt}-lib/liblua
 _flua= lib/liblua libexec/flua
+.if ${BOOTSTRAPPING} == 0
+_flua+= lib/libmd lib/libucl lib/libyaml
+${_bt}-libexec/flua: ${_bt}-lib/libmd ${_bt}-lib/libucl ${_bt}-lib/libyaml
+.endif # BOOTSTRAPPING == 0
 .endif
 
 # r245440 mtree -N support added
@@ -2854,6 +2842,15 @@ bootstrap-tools: ${_bt}-links .PHONY
     ${_mkesdb} \
     ${_zic} \
     ${LOCAL_BSTOOL_DIRS}
+# We don't enforce any particular uniqueness of targets in the above list; it
+# may be the case that different bootstrap tools may have shared dependencies
+# at different BOOTSTRAPPING points, so we don't object to them using their own
+# conditionals and duplicating them into their ${_foo} variable to ease future
+# maintenance if we purge some entries.  These target names are purposefully
+# unique and this is the only place that should be generating commands for them,
+# but the target may have been defined earlier to express dependencies -- thus,
+# we specifically want commands() here.
+.if !commands(${_bt}-${_tool})
 ${_bt}-${_tool}: ${_bt}-links .PHONY .MAKE
 	${_+_}@${ECHODIR} "===> ${_tool} (obj,all,install)"; \
 		cd ${.CURDIR}/${_tool}; \
@@ -2863,8 +2860,8 @@ ${_bt}-${_tool}: ${_bt}-links .PHONY .MAKE
 		fi; \
 		${MAKE} DIRPRFX=${_tool}/ all; \
 		${MAKE} DIRPRFX=${_tool}/ DESTDIR=${WORLDTMP}/legacy install
-
 bootstrap-tools: ${_bt}-${_tool}
+.endif
 .endfor
 .if target(${_bt}-lib/libmd)
 # If we are bootstrapping libmd (e.g. when building on macOS/Linux) add the
diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc
index 785ab4913f8d..3645cff43458 100644
--- a/ObsoleteFiles.inc
+++ b/ObsoleteFiles.inc
@@ -51,6 +51,26 @@
 #   xargs -n1 | sort | uniq -d;
 # done
 
+# 20251006: Remove libnss_tacplus.a (it never should have been installed)
+OLD_FILES+=usr/lib/libnss_tacplus.a
+
+# 20251003: kgdb python scripts moved
+OLD_FILES+=usr/libexec/kgdb/acttrace.py
+OLD_DIRS+=usr/libexec/kgdb
+
+# 20251001: test helper sendto-IP_MULTICAST_IF renamed
+OLD_FILES+=usr/tests/sys/netinet/sendto-IP_MULTICAST_IF
+
+# 20250930: Rename wlanstats to wlanstat
+OLD_FILES+=usr/sbin/wlanstats
+OLD_FILES+=usr/share/man/man8/wlanstats.8.gz
+
+# 20250929: Remove ftpd(8)
+OLD_FILES+=etc/rc.d/ftpd
+OLD_FILES+=usr/libexec/ftpd
+OLD_FILES+=usr/share/man/man5/ftpchroot.5.gz
+OLD_FILES+=usr/share/man/man8/ftpd.8.gz
+
 # 20250917: VREF macro removed
 OLD_FILES+=usr/share/man/man9/VREF.9.gz
 
diff --git a/UPDATING b/UPDATING
index 73d3eddc2941..4460898fca2d 100644
--- a/UPDATING
+++ b/UPDATING
@@ -27,6 +27,24 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 16.x IS SLOW:
 	world, or to merely disable the most expensive debugging functionality
 	at runtime, run "ln -s 'abort:false,junk:false' /etc/malloc.conf".)
 
+20251002:
+	Audio-related utilities including mixer(8) and virtual_oss(8) have
+	moved to the new FreeBSD-sound package.  If you have set-optional or
+	set-base installed this package will be installed automatically,
+	otherwise you should install it manually if you need these utilities.
+
+20250929:
+	Both drm-kmod and nividia-drm ports had to be updated to either no
+	longer conflict on LinuxKPI vs. native PCI changes and/or to keep
+	working after some LinuxKPI PCI adjustments which were previously
+	hidden behind native PCI.
+	Bump __FreeBSD_version 1600001 so users will pick up updated packages.
+
+20250929:
+	The deprecated ftpd(8) has been removed.  Users who still need ftpd
+	can install the ftp/freebsd-ftpd port.  pkgbase users should remove
+	the orphaned FreeBSD-ftpd package.
+
 20250923:
 	Several changes which affect pkgbase users (only):
 
diff --git a/bin/sh/Makefile b/bin/sh/Makefile
index 916bb88b57fa..2b1eca8e4b31 100644
--- a/bin/sh/Makefile
+++ b/bin/sh/Makefile
@@ -69,11 +69,4 @@ token.h: mktokens
 HAS_TESTS=
 SUBDIR.${MK_TESTS}+= tests
 
-beforeinstallconfig:
-	rm -f ${DESTDIR}/.profile
-
-LINKMODE=${CONFMODE}
-afterinstallconfig:
-	${INSTALL_LINK} ${TAG_ARGS:D${TAG_ARGS},config} ${DESTDIR}/root/.profile ${DESTDIR}/.profile
-
 .include <bsd.prog.mk>
diff --git a/cddl/lib/libctf/Makefile b/cddl/lib/libctf/Makefile
index 10854482cd21..1c605182bc1d 100644
--- a/cddl/lib/libctf/Makefile
+++ b/cddl/lib/libctf/Makefile
@@ -2,6 +2,8 @@
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/lib/libctf/common
 .PATH: ${SRCTOP}/sys/cddl/contrib/opensolaris/common/ctf
 
+PACKAGE=	ctf
+LIB_PACKAGE=
 LIB=		ctf
 SRCS=		ctf_create.c \
 		ctf_decl.c \
diff --git a/cddl/share/zfs/compatibility.d/Makefile b/cddl/share/zfs/compatibility.d/Makefile
index 6cdb64b0fccb..6d3663081ae6 100644
--- a/cddl/share/zfs/compatibility.d/Makefile
+++ b/cddl/share/zfs/compatibility.d/Makefile
@@ -24,6 +24,7 @@ FILES= \
 	openzfs-2.1-linux \
 	openzfs-2.2 \
 	openzfs-2.3 \
+	openzfs-2.4 \
 	zol-0.6.1 \
 	zol-0.6.4 \
 	zol-0.6.5 \
@@ -60,7 +61,9 @@ LINKS= \
 	${FILESDIR}/openzfs-2.2		${FILESDIR}/openzfs-2.2-linux \
 	${FILESDIR}/openzfs-2.2		${FILESDIR}/openzfs-2.2-freebsd \
 	${FILESDIR}/openzfs-2.3		${FILESDIR}/openzfs-2.3-linux \
-	${FILESDIR}/openzfs-2.3		${FILESDIR}/openzfs-2.3-freebsd
+	${FILESDIR}/openzfs-2.3		${FILESDIR}/openzfs-2.3-freebsd \
+	${FILESDIR}/openzfs-2.4		${FILESDIR}/openzfs-2.4-linux \
+	${FILESDIR}/openzfs-2.4		${FILESDIR}/openzfs-2.4-freebsd
 
 LINKMODE= ${NOBINMODE}
 
diff --git a/cddl/usr.bin/ctfconvert/Makefile b/cddl/usr.bin/ctfconvert/Makefile
index cd9f850f480c..df53c46b7246 100644
--- a/cddl/usr.bin/ctfconvert/Makefile
+++ b/cddl/usr.bin/ctfconvert/Makefile
@@ -3,7 +3,7 @@
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/tools/ctf/common
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/tools/ctf/cvt
 
-PACKAGE=	ctf-tools
+PACKAGE=	ctf
 PROG=		ctfconvert
 SRCS=		alist.c \
 		ctf.c \
diff --git a/cddl/usr.bin/ctfdump/Makefile b/cddl/usr.bin/ctfdump/Makefile
index 23ded7458bed..357598583ae7 100644
--- a/cddl/usr.bin/ctfdump/Makefile
+++ b/cddl/usr.bin/ctfdump/Makefile
@@ -1,7 +1,7 @@
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/tools/ctf/common
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/tools/ctf/dump
 
-PACKAGE=	ctf-tools
+PACKAGE=	ctf
 PROG=		ctfdump
 SRCS=		dump.c \
 		symbol.c \
diff --git a/cddl/usr.bin/ctfmerge/Makefile b/cddl/usr.bin/ctfmerge/Makefile
index 4cd9511f911c..81bccc047a25 100644
--- a/cddl/usr.bin/ctfmerge/Makefile
+++ b/cddl/usr.bin/ctfmerge/Makefile
@@ -1,7 +1,7 @@
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/tools/ctf/common
 .PATH: ${SRCTOP}/cddl/contrib/opensolaris/tools/ctf/cvt
 
-PACKAGE=	ctf-tools
+PACKAGE=	ctf
 PROG=		ctfmerge
 SRCS=		alist.c \
 		barrier.c \
diff --git a/contrib/expat/Changes b/contrib/expat/Changes
index 092252ed1fa3..01e54b676416 100644
--- a/contrib/expat/Changes
+++ b/contrib/expat/Changes
@@ -41,6 +41,59 @@
 !! THANK YOU!                        Sebastian Pipping -- Berlin, 2024-03-09 !!
 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
 
+Release 2.7.3 Wed September 24 2025
+        Security fixes:
+     #1046 #1048  Fix alignment of internal allocations for some non-amd64
+                    architectures (e.g. sparc32); fixes up on the fix to
+                    CVE-2025-59375 from #1034 (of Expat 2.7.2 and related
+                    backports)
+           #1059  Fix a class of false positives where input should have been
+                    rejected with error XML_ERROR_ASYNC_ENTITY; regression from
+                    CVE-2024-8176 fix pull request #973 (of Expat 2.7.0 and
+                    related backports). Please check the added unit tests for
+                    example documents.
+
+        Other changes:
+           #1043  Prove and regression-proof absence of integer overflow
+                    from function expat_realloc
+           #1062  Remove "harmless" cast that truncated a size_t to unsigned
+           #1049  Autotools: Remove "ln -s" discovery
+           #1054  docs: Be consistent with use of floating point around
+                    XML_SetAllocTrackerMaximumAmplification
+           #1056  docs: Make it explicit that XML_GetCurrentColumnNumber
+                    starts at 0
+           #1057  docs: Better integrate the effect of the activation
+                    thresholds
+           #1058  docs: Fix an in-comment typo in expat.h
+           #1045  docs: Fix a typo in README.md
+           #1041  docs: Improve change log of release 2.7.2
+           #1053  xmlwf: Resolve use of functions XML_GetErrorLineNumber
+                    and XML_GetErrorColumnNumber
+           #1032  Windows: Normalize .bat files to CRLF line endings
+     #1060 #1061  Version info bumped from 12:0:11 (libexpat*.so.1.11.0)
+                    to 12:1:11 (libexpat*.so.1.11.1); see https://verbump.de/
+                    for what these numbers do
+
+        Infrastructure:
+     #1047 #1050  CI: Cleanup UndefinedBehaviorSanitizer fatality
+           #1044  CI|Linux: Stop aborting at first job failure
+           #1052  CI|FreeBSD: Upgrade to FreeBSD 15.0
+           #1039  CI|FreeBSD: Do not install CMake meta-package
+
+        Special thanks to:
+            Bénédikt Tran
+            Berkay Eren Ürün
+            Daniel Engberg
+            Hanno Böck
+            Matthew Fernandez
+            Rolf Eike Beer
+            Sam James
+            Tim Bray
+                 and
+            Clang/GCC UndefinedBehaviorSanitizer
+            OSS-Fuzz / ClusterFuzz
+            Z3 Theorem Prover
+
 Release 2.7.2 Tue September 16 2025
         Security fixes:
      #1018 #1034  CVE-2025-59375 -- Disallow use of disproportional amounts of
@@ -73,7 +126,7 @@ Release 2.7.2 Tue September 16 2025
                     to the pull request URL could be of help.
 
         Other changes:
-     #1008 #1017  Autotools: Sync CMake templates with CMake 3.31 for macOS
+     #1008 #1017  Autotools|macOS: Sync CMake templates with CMake 3.31
            #1007  CMake: Drop support for CMake <3.15
            #1004  CMake: Fix off_t detection for -Werror
            #1007  CMake|Windows: Fix -DEXPAT_MSVC_STATIC_CRT=ON
@@ -89,7 +142,7 @@ Release 2.7.2 Tue September 16 2025
             #994  docs: Drop AppVeyor badge
            #1000  tests: Fix portable_strndup
            #1036  Drop casts around malloc/free/realloc that C99 does not need
-           #1010  Replace empty for-loops with while loops
+           #1010  Replace empty for loops with while loops
            #1011  Add const with internal XmlInitUnknownEncodingNS
        #14 #1037  Drop an OpenVMS support leftover
       #999 #1001  Address more clang-tidy warnings
@@ -111,6 +164,7 @@ Release 2.7.2 Tue September 16 2025
             Neil Pang
             Theo Buehler
                  and
+            GNU Time
             OSS-Fuzz / ClusterFuzz
             Perl XML::Parser
 
diff --git a/contrib/expat/README.md b/contrib/expat/README.md
index fdaaf459e204..c2f288ca1242 100644
--- a/contrib/expat/README.md
+++ b/contrib/expat/README.md
@@ -11,7 +11,7 @@
 > at the top of the `Changes` file.
 
 
-# Expat, Release 2.7.2
+# Expat, Release 2.7.3
 
 This is Expat, a C99 library for parsing
 [XML 1.0 Fourth Edition](https://www.w3.org/TR/2006/REC-xml-20060816/), started by
@@ -120,7 +120,7 @@ project(hello VERSION 1.0.0)
 FetchContent_Declare(
     expat
     GIT_REPOSITORY https://github.com/libexpat/libexpat/
-    GIT_TAG        000000000_GIT_COMMIT_SHA1_HERE_000000000  # i.e. Git tag R_0_Y_Z
+    GIT_TAG        000000000_GIT_COMMIT_SHA1_HERE_000000000  # i.e. Git tag R_X_Y_Z
     SOURCE_SUBDIR  expat/
 )
 
diff --git a/contrib/expat/configure.ac b/contrib/expat/configure.ac
index b9966eabcd60..072fea41ee8c 100644
--- a/contrib/expat/configure.ac
+++ b/contrib/expat/configure.ac
@@ -24,6 +24,7 @@ dnl   Copyright (c) 2019      Kishore Kunche <kishore.kunche@intel.com>
 dnl   Copyright (c) 2020      Jeffrey Walton <noloader@gmail.com>
 dnl   Copyright (c) 2024      Ferenc Géczi <ferenc.gm@gmail.com>
 dnl   Copyright (c) 2024      Dag-Erling Smørgrav <des@des.dev>
+dnl   Copyright (c) 2025      Matthew Fernandez <matthew.fernandez@gmail.com>
 dnl   Licensed under the MIT license:
 dnl
 dnl   Permission is  hereby granted,  free of charge,  to any  person obtaining
@@ -85,7 +86,7 @@ dnl If the API changes incompatibly set LIBAGE back to 0
 dnl
 
 LIBCURRENT=12  # sync
-LIBREVISION=0  # with
+LIBREVISION=1  # with
 LIBAGE=11      # CMakeLists.txt!
 
 AC_CONFIG_HEADERS([expat_config.h])
@@ -95,7 +96,6 @@ AH_BOTTOM([#endif // ndef EXPAT_CONFIG_H])
 
 AM_PROG_AR
 AC_PROG_INSTALL
-AC_PROG_LN_S
 AC_PROG_MAKE_SET
 
 LT_PREREQ([2.4])
diff --git a/contrib/expat/doc/reference.html b/contrib/expat/doc/reference.html
index 12b12b92ff6d..d2dded499435 100644
--- a/contrib/expat/doc/reference.html
+++ b/contrib/expat/doc/reference.html
@@ -52,7 +52,7 @@
   <div>
     <h1>
       The Expat XML Parser
-      <small>Release 2.7.2</small>
+      <small>Release 2.7.3</small>
     </h1>
   </div>
 <div class="content">
@@ -2137,8 +2137,8 @@ XML_Size XMLCALL
 XML_GetCurrentColumnNumber(XML_Parser p);
 </pre>
 <div class="fcndef">
-Return the offset, from the beginning of the current line, of
-the position.
+Return the <em>offset</em>, from the beginning of the current line, of
+the position.  The first column is reported as <code>0</code>.
 </div>
 
 <h4 id="XML_GetCurrentByteCount">XML_GetCurrentByteCount</h4>
@@ -2200,7 +2200,10 @@ XML_SetBillionLaughsAttackProtectionMaximumAmplification(XML_Parser p,
     returns <code>XML_TRUE</code> upon success and <code>XML_FALSE</code> upon error.
   </p>
 
-  <p>The amplification factor is calculated as ..</p>
+  <p>
+    Once the <a href="#XML_SetBillionLaughsAttackProtectionActivationThreshold">threshold for activation</a> is reached,
+    the amplification factor is calculated as ..
+  </p>
   <pre>amplification := (direct + indirect) / direct</pre>
   <p>
     .. while parsing, whereas
@@ -2317,7 +2320,10 @@ XML_SetAllocTrackerMaximumAmplification(XML_Parser p,
     </li>
   </ul>
 
-  <p>The amplification factor is calculated as ..</p>
+  <p>
+    Once the <a href="#XML_SetAllocTrackerActivationThreshold">threshold for activation</a> is reached,
+    the amplification factor is calculated as ..
+  </p>
   <pre>amplification := allocated / direct</pre>
   <p>
     .. while parsing, whereas
@@ -2339,7 +2345,7 @@ XML_SetAllocTrackerMaximumAmplification(XML_Parser p,
 
   <p>
     <strong>Note:</strong>
-    Amplifications factors greater than 100 can been observed near the start of parsing
+    Amplifications factors greater than <code>100.0</code> can been observed near the start of parsing
     even with benign files in practice.
 
     So if you do reduce the maximum allowed amplification,
diff --git a/contrib/expat/doc/xmlwf.1 b/contrib/expat/doc/xmlwf.1
index 5f50ba9e4d00..aa2e9c218007 100644
--- a/contrib/expat/doc/xmlwf.1
+++ b/contrib/expat/doc/xmlwf.1
@@ -5,7 +5,7 @@
 \\$2 \(la\\$1\(ra\\$3
 ..
 .if \n(.g .mso www.tmac
-.TH XMLWF 1 "September 16, 2025" "" ""
+.TH XMLWF 1 "September 24, 2025" "" ""
 .SH NAME
 xmlwf \- Determines if an XML document is well-formed
 .SH SYNOPSIS
diff --git a/contrib/expat/doc/xmlwf.xml b/contrib/expat/doc/xmlwf.xml
index defe9df8e46a..01316bb16627 100644
--- a/contrib/expat/doc/xmlwf.xml
+++ b/contrib/expat/doc/xmlwf.xml
@@ -21,7 +21,7 @@
           "http://www.oasis-open.org/docbook/xml/4.2/docbookx.dtd" [
   <!ENTITY dhfirstname "<firstname>Scott</firstname>">
   <!ENTITY dhsurname   "<surname>Bronson</surname>">
-  <!ENTITY dhdate      "<date>September 16, 2025</date>">
+  <!ENTITY dhdate      "<date>September 24, 2025</date>">
   <!-- Please adjust this^^ date whenever cutting a new release. -->
   <!ENTITY dhsection   "<manvolnum>1</manvolnum>">
   <!ENTITY dhemail     "<email>bronson@rinspin.com</email>">
diff --git a/contrib/expat/lib/expat.h b/contrib/expat/lib/expat.h
index bb9cdedbac7d..290dfeb0f6dd 100644
--- a/contrib/expat/lib/expat.h
+++ b/contrib/expat/lib/expat.h
@@ -19,6 +19,7 @@
    Copyright (c) 2023      Hanno Böck <hanno@gentoo.org>
    Copyright (c) 2023      Sony Corporation / Snild Dolkow <snild@sony.com>
    Copyright (c) 2024      Taichi Haradaguchi <20001722@ymail.ne.jp>
+   Copyright (c) 2025      Matthew Fernandez <matthew.fernandez@gmail.com>
    Licensed under the MIT license:
 
    Permission is  hereby granted,  free of charge,  to any  person obtaining
@@ -276,7 +277,7 @@ XML_ParserCreate_MM(const XML_Char *encoding,
 
 /* Prepare a parser object to be reused.  This is particularly
    valuable when memory allocation overhead is disproportionately high,
-   such as when a large number of small documnents need to be parsed.
+   such as when a large number of small documents need to be parsed.
    All handlers are cleared from the parser, except for the
    unknownEncodingHandler. The parser's external state is re-initialized
    except for the values of ns and ns_triplets.
@@ -1081,7 +1082,7 @@ XML_SetReparseDeferralEnabled(XML_Parser parser, XML_Bool enabled);
 */
 #  define XML_MAJOR_VERSION 2
 #  define XML_MINOR_VERSION 7
-#  define XML_MICRO_VERSION 2
+#  define XML_MICRO_VERSION 3
 
 #  ifdef __cplusplus
 }
diff --git a/contrib/expat/lib/internal.h b/contrib/expat/lib/internal.h
index 6e087858ebbe..8f5edf48ef7c 100644
--- a/contrib/expat/lib/internal.h
+++ b/contrib/expat/lib/internal.h
@@ -108,6 +108,7 @@
 #endif
 
 #include <limits.h> // ULONG_MAX
+#include <stddef.h> // size_t
 
 #if defined(_WIN32)                                                            \
     && (! defined(__USE_MINGW_ANSI_STDIO)                                      \
@@ -153,6 +154,11 @@
 #define EXPAT_ALLOC_TRACKER_ACTIVATION_THRESHOLD_DEFAULT                       \
   67108864 // 64 MiB, 2^26
 
+// NOTE: If function expat_alloc was user facing, EXPAT_MALLOC_ALIGNMENT would
+//       have to take sizeof(long double) into account
+#define EXPAT_MALLOC_ALIGNMENT sizeof(long long) // largest parser (sub)member
+#define EXPAT_MALLOC_PADDING ((EXPAT_MALLOC_ALIGNMENT) - sizeof(size_t))
+
 /* NOTE END */
 
 #include "expat.h" // so we can use type XML_Parser below
diff --git a/contrib/expat/lib/xmlparse.c b/contrib/expat/lib/xmlparse.c
index de1594934900..a187a3a18f19 100644
--- a/contrib/expat/lib/xmlparse.c
+++ b/contrib/expat/lib/xmlparse.c
@@ -1,4 +1,4 @@
-/* 60e137abb91af642d6c3988f8f133d23329b32638659c74d47125fc0faf6ddd5 (2.7.2+)
+/* 28bcd8b1ba7eb595d82822908257fd9c3589b4243e3c922d0369f35bfcd7b506 (2.7.3+)
                             __  __            _
                          ___\ \/ /_ __   __ _| |_
                         / _ \\  /| '_ \ / _` | __|
@@ -41,6 +41,7 @@
    Copyright (c) 2023-2024 Sony Corporation / Snild Dolkow <snild@sony.com>
    Copyright (c) 2024-2025 Berkay Eren Ürün <berkay.ueruen@siemens.com>
    Copyright (c) 2024      Hanno Böck <hanno@gentoo.org>
+   Copyright (c) 2025      Matthew Fernandez <matthew.fernandez@gmail.com>
    Licensed under the MIT license:
 
    Permission is  hereby granted,  free of charge,  to any  person obtaining
@@ -850,14 +851,14 @@ static void *
 #  endif
 expat_malloc(XML_Parser parser, size_t size, int sourceLine) {
   // Detect integer overflow
-  if (SIZE_MAX - size < sizeof(size_t)) {
+  if (SIZE_MAX - size < sizeof(size_t) + EXPAT_MALLOC_PADDING) {
     return NULL;
   }
 
   const XML_Parser rootParser = getRootParserOf(parser, NULL);
   assert(rootParser->m_parentParser == NULL);
 
-  const size_t bytesToAllocate = sizeof(size_t) + size;
+  const size_t bytesToAllocate = sizeof(size_t) + EXPAT_MALLOC_PADDING + size;
 
   if ((XmlBigCount)-1 - rootParser->m_alloc_tracker.bytesAllocated
       < bytesToAllocate) {
@@ -894,7 +895,7 @@ expat_malloc(XML_Parser parser, size_t size, int sourceLine) {
                     rootParser->m_alloc_tracker.peakBytesAllocated, sourceLine);
   }
 
-  return (char *)mallocedPtr + sizeof(size_t);
+  return (char *)mallocedPtr + sizeof(size_t) + EXPAT_MALLOC_PADDING;
 }
 
 #  if defined(XML_TESTING)
@@ -914,8 +915,9 @@ expat_free(XML_Parser parser, void *ptr, int sourceLine) {
 
   // Extract size (to the eyes of malloc_fcn/realloc_fcn) and
   // the original pointer returned by malloc/realloc
-  void *const mallocedPtr = (char *)ptr - sizeof(size_t);
-  const size_t bytesAllocated = sizeof(size_t) + *(size_t *)mallocedPtr;
+  void *const mallocedPtr = (char *)ptr - EXPAT_MALLOC_PADDING - sizeof(size_t);
+  const size_t bytesAllocated
+      = sizeof(size_t) + EXPAT_MALLOC_PADDING + *(size_t *)mallocedPtr;
 
   // Update accounting
   assert(rootParser->m_alloc_tracker.bytesAllocated >= bytesAllocated);
@@ -954,7 +956,7 @@ expat_realloc(XML_Parser parser, void *ptr, size_t size, int sourceLine) {
 
   // Extract original size (to the eyes of the caller) and the original
   // pointer returned by malloc/realloc
-  void *mallocedPtr = (char *)ptr - sizeof(size_t);
+  void *mallocedPtr = (char *)ptr - EXPAT_MALLOC_PADDING - sizeof(size_t);
   const size_t prevSize = *(size_t *)mallocedPtr;
 
   // Classify upcoming change
@@ -969,8 +971,13 @@ expat_realloc(XML_Parser parser, void *ptr, size_t size, int sourceLine) {
     }
   }
 
+  // NOTE: Integer overflow detection has already been done for us
+  //       by expat_heap_increase_tolerable(..) above
+  assert(SIZE_MAX - sizeof(size_t) - EXPAT_MALLOC_PADDING >= size);
+
   // Actually allocate
-  mallocedPtr = parser->m_mem.realloc_fcn(mallocedPtr, sizeof(size_t) + size);
+  mallocedPtr = parser->m_mem.realloc_fcn(
+      mallocedPtr, sizeof(size_t) + EXPAT_MALLOC_PADDING + size);
 
   if (mallocedPtr == NULL) {
     return NULL;
@@ -1001,7 +1008,7 @@ expat_realloc(XML_Parser parser, void *ptr, size_t size, int sourceLine) {
   // Update in-block recorded size
   *(size_t *)mallocedPtr = size;
 
-  return (char *)mallocedPtr + sizeof(size_t);
+  return (char *)mallocedPtr + sizeof(size_t) + EXPAT_MALLOC_PADDING;
 }
 #endif // XML_GE == 1
 
@@ -1337,7 +1344,8 @@ parserCreate(const XML_Char *encodingName,
   XML_Parser parser = NULL;
 
 #if XML_GE == 1
-  const size_t increase = sizeof(size_t) + sizeof(struct XML_ParserStruct);
+  const size_t increase
+      = sizeof(size_t) + EXPAT_MALLOC_PADDING + sizeof(struct XML_ParserStruct);
 
   if (parentParser != NULL) {
     const XML_Parser rootParser = getRootParserOf(parentParser, NULL);
@@ -1352,11 +1360,13 @@ parserCreate(const XML_Char *encodingName,
   if (memsuite) {
     XML_Memory_Handling_Suite *mtemp;
 #if XML_GE == 1
-    void *const sizeAndParser = memsuite->malloc_fcn(
-        sizeof(size_t) + sizeof(struct XML_ParserStruct));
+    void *const sizeAndParser
+        = memsuite->malloc_fcn(sizeof(size_t) + EXPAT_MALLOC_PADDING
+                               + sizeof(struct XML_ParserStruct));
     if (sizeAndParser != NULL) {
       *(size_t *)sizeAndParser = sizeof(struct XML_ParserStruct);
-      parser = (XML_Parser)((char *)sizeAndParser + sizeof(size_t));
+      parser = (XML_Parser)((char *)sizeAndParser + sizeof(size_t)
+                            + EXPAT_MALLOC_PADDING);
 #else
     parser = memsuite->malloc_fcn(sizeof(struct XML_ParserStruct));
     if (parser != NULL) {
@@ -1369,11 +1379,12 @@ parserCreate(const XML_Char *encodingName,
   } else {
     XML_Memory_Handling_Suite *mtemp;
 #if XML_GE == 1
-    void *const sizeAndParser
-        = malloc(sizeof(size_t) + sizeof(struct XML_ParserStruct));
+    void *const sizeAndParser = malloc(sizeof(size_t) + EXPAT_MALLOC_PADDING
+                                       + sizeof(struct XML_ParserStruct));
     if (sizeAndParser != NULL) {
       *(size_t *)sizeAndParser = sizeof(struct XML_ParserStruct);
-      parser = (XML_Parser)((char *)sizeAndParser + sizeof(size_t));
+      parser = (XML_Parser)((char *)sizeAndParser + sizeof(size_t)
+                            + EXPAT_MALLOC_PADDING);
 #else
     parser = malloc(sizeof(struct XML_ParserStruct));
     if (parser != NULL) {
@@ -6437,6 +6448,10 @@ internalEntityProcessor(XML_Parser parser, const char *s, const char *end,
     // process its possible inner entities (which are added to the
     // m_openInternalEntities during doProlog or doContent calls above)
     entity->hasMore = XML_FALSE;
+    if (! entity->is_param
+        && (openEntity->startTagLevel != parser->m_tagLevel)) {
+      return XML_ERROR_ASYNC_ENTITY;
+    }
     triggerReenter(parser);
     return result;
   } // End of entity processing, "if" block will return here
@@ -8135,7 +8150,7 @@ poolGrow(STRING_POOL *pool) {
     if (bytesToAllocate == 0)
       return XML_FALSE;
 
-    temp = REALLOC(pool->parser, pool->blocks, (unsigned)bytesToAllocate);
+    temp = REALLOC(pool->parser, pool->blocks, bytesToAllocate);
     if (temp == NULL)
       return XML_FALSE;
     pool->blocks = temp;
diff --git a/contrib/expat/lib/xmlrole.h b/contrib/expat/lib/xmlrole.h
index 67bdd3dd5160..9d0d4ff11b7f 100644
--- a/contrib/expat/lib/xmlrole.h
+++ b/contrib/expat/lib/xmlrole.h
@@ -10,7 +10,7 @@
    Copyright (c) 2000      Clark Cooper <coopercc@users.sourceforge.net>
    Copyright (c) 2002      Karl Waclawek <karl@waclawek.net>
    Copyright (c) 2002      Fred L. Drake, Jr. <fdrake@users.sourceforge.net>
-   Copyright (c) 2017-2024 Sebastian Pipping <sebastian@pipping.org>
+   Copyright (c) 2017-2025 Sebastian Pipping <sebastian@pipping.org>
    Licensed under the MIT license:
 
    Permission is  hereby granted,  free of charge,  to any  person obtaining
diff --git a/contrib/expat/tests/alloc_tests.c b/contrib/expat/tests/alloc_tests.c
index 644a49523c6e..5ae6c6a72025 100644
--- a/contrib/expat/tests/alloc_tests.c
+++ b/contrib/expat/tests/alloc_tests.c
@@ -2091,6 +2091,13 @@ START_TEST(test_alloc_reset_after_external_entity_parser_create_fail) {
 }
 END_TEST
 
+#if XML_GE == 1
+static size_t
+sizeRecordedFor(void *ptr) {
+  return *(size_t *)((char *)ptr - EXPAT_MALLOC_PADDING - sizeof(size_t));
+}
+#endif // XML_GE == 1
+
 START_TEST(test_alloc_tracker_size_recorded) {
   XML_Memory_Handling_Suite memsuite = {malloc, realloc, free};
 
@@ -2106,16 +2113,16 @@ START_TEST(test_alloc_tracker_size_recorded) {
     void *ptr = expat_malloc(parser, 10, -1);
 
     assert_true(ptr != NULL);
-    assert_true(*((size_t *)ptr - 1) == 10);
+    assert_true(sizeRecordedFor(ptr) == 10);
 
     assert_true(expat_realloc(parser, ptr, SIZE_MAX / 2, -1) == NULL);
 
-    assert_true(*((size_t *)ptr - 1) == 10); // i.e. unchanged
+    assert_true(sizeRecordedFor(ptr) == 10); // i.e. unchanged
 
     ptr = expat_realloc(parser, ptr, 20, -1);
 
     assert_true(ptr != NULL);
-    assert_true(*((size_t *)ptr - 1) == 20);
+    assert_true(sizeRecordedFor(ptr) == 20);
 
     expat_free(parser, ptr, -1);
 #endif
@@ -2125,6 +2132,22 @@ START_TEST(test_alloc_tracker_size_recorded) {
 }
 END_TEST
 
+START_TEST(test_alloc_tracker_pointer_alignment) {
+  XML_Parser parser = XML_ParserCreate(NULL);
+#if XML_GE == 1
+  assert_true(sizeof(long long) >= sizeof(size_t)); // self-test
+  long long *const ptr
+      = (long long *)expat_malloc(parser, 4 * sizeof(long long), -1);
+  ptr[0] = 0LL;
+  ptr[1] = 1LL;
+  ptr[2] = 2LL;
+  ptr[3] = 3LL;
+  expat_free(parser, ptr, -1);
+#endif
+  XML_ParserFree(parser);
+}
+END_TEST
+
 START_TEST(test_alloc_tracker_maximum_amplification) {
   if (g_reparseDeferralEnabledDefault == XML_TRUE) {
     return;
@@ -2355,14 +2378,13 @@ make_alloc_test_case(Suite *s) {
   tcase_add_test__ifdef_xml_dtd(
       tc_alloc, test_alloc_reset_after_external_entity_parser_create_fail);
 
-  tcase_add_test__ifdef_xml_dtd(tc_alloc, test_alloc_tracker_size_recorded);
-  tcase_add_test__ifdef_xml_dtd(tc_alloc,
-                                test_alloc_tracker_maximum_amplification);
-  tcase_add_test__ifdef_xml_dtd(tc_alloc, test_alloc_tracker_threshold);
-  tcase_add_test__ifdef_xml_dtd(tc_alloc,
-                                test_alloc_tracker_getbuffer_unlimited);
-  tcase_add_test__ifdef_xml_dtd(tc_alloc, test_alloc_tracker_api);
+  tcase_add_test__if_xml_ge(tc_alloc, test_alloc_tracker_size_recorded);
+  tcase_add_test__if_xml_ge(tc_alloc, test_alloc_tracker_pointer_alignment);
+  tcase_add_test__if_xml_ge(tc_alloc, test_alloc_tracker_maximum_amplification);
+  tcase_add_test__if_xml_ge(tc_alloc, test_alloc_tracker_threshold);
+  tcase_add_test__if_xml_ge(tc_alloc, test_alloc_tracker_getbuffer_unlimited);
+  tcase_add_test__if_xml_ge(tc_alloc, test_alloc_tracker_api);
 
   tcase_add_test(tc_alloc, test_mem_api_cycle);
-  tcase_add_test__ifdef_xml_dtd(tc_alloc, test_mem_api_unlimited);
+  tcase_add_test__if_xml_ge(tc_alloc, test_mem_api_unlimited);
 }
diff --git a/contrib/expat/tests/misc_tests.c b/contrib/expat/tests/misc_tests.c
index 3346bce6074b..2a8054546a12 100644
--- a/contrib/expat/tests/misc_tests.c
+++ b/contrib/expat/tests/misc_tests.c
@@ -211,7 +211,7 @@ START_TEST(test_misc_version) {
   if (! versions_equal(&read_version, &parsed_version))
     fail("Version mismatch");
 
-  if (xcstrcmp(version_text, XCS("expat_2.7.2"))
+  if (xcstrcmp(version_text, XCS("expat_2.7.3"))
       != 0) /* needs bump on releases */
     fail("XML_*_VERSION in expat.h out of sync?\n");
 }
@@ -679,6 +679,98 @@ START_TEST(test_misc_expected_event_ptr_issue_980) {
 }
 END_TEST
 
+START_TEST(test_misc_sync_entity_tolerated) {
+  const char *const doc = "<!DOCTYPE t0 [\n"
+                          "   <!ENTITY a '<t1></t1>'>\n"
+                          "   <!ENTITY b '<t2>two</t2>'>\n"
+                          "   <!ENTITY c '<t3>three<t4>four</t4>three</t3>'>\n"
+                          "   <!ENTITY d '<t5>&b;</t5>'>\n"
+                          "]>\n"
+                          "<t0>&a;&b;&c;&d;</t0>\n";
+  XML_Parser parser = XML_ParserCreate(NULL);
+
+  assert_true(_XML_Parse_SINGLE_BYTES(parser, doc, (int)strlen(doc),
+                                      /*isFinal=*/XML_TRUE)
+              == XML_STATUS_OK);
+
+  XML_ParserFree(parser);
+}
+END_TEST
+
+START_TEST(test_misc_async_entity_rejected) {
+  struct test_case {
+    const char *doc;
+    enum XML_Status expectedStatusNoGE;
+    enum XML_Error expectedErrorNoGE;
+    XML_Size expectedErrorLine;
+    XML_Size expectedErrorColumn;
+  };
+  const struct test_case cases[] = {
+      // Opened by one entity, closed by another
+      {"<!DOCTYPE t0 [\n"
+       "   <!ENTITY open '<t1>'>\n"
+       "   <!ENTITY close '</t1>'>\n"
+       "]>\n"
+       "<t0>&open;&close;</t0>\n",
+       XML_STATUS_OK, XML_ERROR_NONE, 5, 4},
+      // Opened by tag, closed by entity (non-root case)
+      {"<!DOCTYPE t0 [\n"
+       "  <!ENTITY g0 ''>\n"
+       "  <!ENTITY g1 '&g0;</t1>'>\n"
+       "]>\n"
+       "<t0><t1>&g1;</t0>\n",
+       XML_STATUS_ERROR, XML_ERROR_TAG_MISMATCH, 5, 8},
+      // Opened by tag, closed by entity (root case)
+      {"<!DOCTYPE t0 [\n"
+       "  <!ENTITY g0 ''>\n"
+       "  <!ENTITY g1 '&g0;</t0>'>\n"
+       "]>\n"
+       "<t0>&g1;\n",
+       XML_STATUS_ERROR, XML_ERROR_NO_ELEMENTS, 5, 4},
+      // Opened by entity, closed by tag <-- regression from 2.7.0
+      {"<!DOCTYPE t0 [\n"
+       "  <!ENTITY g0 ''>\n"
+       "  <!ENTITY g1 '<t1>&g0;'>\n"
+       "]>\n"
+       "<t0>&g1;</t1></t0>\n",
+       XML_STATUS_ERROR, XML_ERROR_TAG_MISMATCH, 5, 4},
+      // Opened by tag, closed by entity; then the other way around
+      {"<!DOCTYPE t0 [\n"
+       "  <!ENTITY open '<t1>'>\n"
+       "  <!ENTITY close '</t1>'>\n"
+       "]>\n"
+       "<t0><t1>&close;&open;</t1></t0>\n",
+       XML_STATUS_OK, XML_ERROR_NONE, 5, 8},
+  };
+
+  for (size_t i = 0; i < sizeof(cases) / sizeof(cases[0]); i++) {
+    const struct test_case testCase = cases[i];
+    set_subtest("cases[%d]", (int)i);
+
+    const char *const doc = testCase.doc;
+#if XML_GE == 1
+    const enum XML_Status expectedStatus = XML_STATUS_ERROR;
+    const enum XML_Error expectedError = XML_ERROR_ASYNC_ENTITY;
+#else
+    const enum XML_Status expectedStatus = testCase.expectedStatusNoGE;
+    const enum XML_Error expectedError = testCase.expectedErrorNoGE;
+#endif
+
+    XML_Parser parser = XML_ParserCreate(NULL);
+    assert_true(_XML_Parse_SINGLE_BYTES(parser, doc, (int)strlen(doc),
+                                        /*isFinal=*/XML_TRUE)
+                == expectedStatus);
+    assert_true(XML_GetErrorCode(parser) == expectedError);
+#if XML_GE == 1
+    assert_true(XML_GetCurrentLineNumber(parser) == testCase.expectedErrorLine);
+    assert_true(XML_GetCurrentColumnNumber(parser)
+                == testCase.expectedErrorColumn);
+#endif
+    XML_ParserFree(parser);
+  }
+}
+END_TEST
+
 void
 make_miscellaneous_test_case(Suite *s) {
   TCase *tc_misc = tcase_create("miscellaneous tests");
@@ -707,4 +799,6 @@ make_miscellaneous_test_case(Suite *s) {
   tcase_add_test(tc_misc, test_misc_stopparser_rejects_unstarted_parser);
   tcase_add_test__if_xml_ge(tc_misc, test_renter_loop_finite_content);
   tcase_add_test(tc_misc, test_misc_expected_event_ptr_issue_980);
+  tcase_add_test(tc_misc, test_misc_sync_entity_tolerated);
+  tcase_add_test(tc_misc, test_misc_async_entity_rejected);
 }
diff --git a/contrib/expat/xmlwf/xmlfile.c b/contrib/expat/xmlwf/xmlfile.c
index 54617fcc5a1a..ce0b61217ed7 100644
--- a/contrib/expat/xmlwf/xmlfile.c
+++ b/contrib/expat/xmlwf/xmlfile.c
@@ -96,8 +96,8 @@ reportError(XML_Parser parser, const XML_Char *filename) {
     ftprintf(stdout,
              T("%s") T(":%") T(XML_FMT_INT_MOD) T("u") T(":%")
                  T(XML_FMT_INT_MOD) T("u") T(": %s\n"),
-             filename, XML_GetErrorLineNumber(parser),
-             XML_GetErrorColumnNumber(parser), message);
+             filename, XML_GetCurrentLineNumber(parser),
+             XML_GetCurrentColumnNumber(parser), message);
   else
     ftprintf(stderr, T("%s: (unknown message %u)\n"), filename,
              (unsigned int)code);
diff --git a/contrib/libucl/lua/lua_ucl.c b/contrib/libucl/lua/lua_ucl.c
index d6be69e42a71..1b3f9dfd111c 100644
--- a/contrib/libucl/lua/lua_ucl.c
+++ b/contrib/libucl/lua/lua_ucl.c
@@ -30,6 +30,8 @@
 #include "lua_ucl.h"
 #include <strings.h>
 
+#include "bootstrap.h"
+
 /***
  * @module ucl
  * This lua module allows to parse objects from strings and to store data into
@@ -1571,3 +1573,5 @@ ucl_object_toclosure (const ucl_object_t *obj)
 
 	return (struct ucl_lua_funcdata*)obj->value.ud;
 }
+
+FLUA_MODULE(ucl);
diff --git a/contrib/libucl/src/ucl_parser.c b/contrib/libucl/src/ucl_parser.c
index 6be16d12169c..728cd6381056 100644
--- a/contrib/libucl/src/ucl_parser.c
+++ b/contrib/libucl/src/ucl_parser.c
@@ -164,51 +164,50 @@ start:
 			}
 		}
 	}
-	else if (chunk->remain >= 2 && *p == '/') {
-		if (p[1] == '*') {
-			beg = p;
-			ucl_chunk_skipc (chunk, p);
-			comments_nested ++;
-			ucl_chunk_skipc (chunk, p);
-
-			while (p < chunk->end) {
-				if (*p == '"' && *(p - 1) != '\\') {
-					quoted = !quoted;
-				}
-
-				if (!quoted) {
-					if (*p == '*') {
-						ucl_chunk_skipc (chunk, p);
-						if (chunk->remain > 0 && *p == '/') {
-							comments_nested --;
-							if (comments_nested == 0) {
-								if (parser->flags & UCL_PARSER_SAVE_COMMENTS) {
-									ucl_save_comment (parser, beg, p - beg + 1);
-									beg = NULL;
-								}
-
-								ucl_chunk_skipc (chunk, p);
-								goto start;
-							}
-						}
-						ucl_chunk_skipc (chunk, p);
-					}
-					else if (p[0] == '/' && chunk->remain >= 2 && p[1] == '*') {
-						comments_nested ++;
-						ucl_chunk_skipc (chunk, p);
-						ucl_chunk_skipc (chunk, p);
-						continue;
+	else if (chunk->remain >= 2 && *p == '/' && p[1] == '*') {
+		beg = p;
+		comments_nested ++;
+		ucl_chunk_skipc (chunk, p);
+		ucl_chunk_skipc (chunk, p);
+		while (p < chunk->end) {
+			if (*p == '"' && *(p - 1) != '\\') {
+				/* begin or end double-quoted string */
+				quoted = !quoted;
+				ucl_chunk_skipc (chunk, p);
+			}
+			else if (quoted) {
+				/* quoted character */
+				ucl_chunk_skipc (chunk, p);
+			}
+			else if (chunk->remain >= 2 && *p == '*' && p[1] == '/') {
+				/* end of comment */
+				ucl_chunk_skipc (chunk, p);
+				ucl_chunk_skipc (chunk, p);
+				comments_nested --;
+				if (comments_nested == 0) {
+					if (parser->flags & UCL_PARSER_SAVE_COMMENTS) {
+						ucl_save_comment (parser, beg, p - beg + 1);
+						beg = NULL;
 					}
+					goto start;
 				}
-
+			}
+			else if (chunk->remain >= 2 && *p == '/' && p[1] == '*') {
+				/* start of nested comment */
+				comments_nested ++;
+				ucl_chunk_skipc (chunk, p);
 				ucl_chunk_skipc (chunk, p);
 			}
-			if (comments_nested != 0) {
-				ucl_set_err (parser, UCL_ENESTED,
-						"unfinished multiline comment", &parser->err);
-				return false;
+			else {
+				/* anything else */
+				ucl_chunk_skipc (chunk, p);
 			}
 		}
+		if (comments_nested != 0) {
+			ucl_set_err (parser, UCL_ENESTED,
+			    "unfinished multiline comment", &parser->err);
+			return false;
+		}
 	}
 
 	if (beg && p > beg && (parser->flags & UCL_PARSER_SAVE_COMMENTS)) {
diff --git a/contrib/lyaml/ext/yaml/yaml.c b/contrib/lyaml/ext/yaml/yaml.c
index 54478610134f..6a5ddc605e0f 100644
--- a/contrib/lyaml/ext/yaml/yaml.c
+++ b/contrib/lyaml/ext/yaml/yaml.c
@@ -35,6 +35,8 @@
 
 #include "lyaml.h"
 
+#include "bootstrap.h"
+
 #define MYNAME		"yaml"
 #define MYVERSION	MYNAME " library for " LUA_VERSION " / " VERSION
 
@@ -64,3 +66,5 @@ luaopen_yaml (lua_State *L)
 
    return 1;
 }
+
+FLUA_MODULE(yaml);
diff --git a/contrib/mandoc/Makefile b/contrib/mandoc/Makefile
index 0830c9f289a3..d4a2c794b437 100644
--- a/contrib/mandoc/Makefile
+++ b/contrib/mandoc/Makefile
@@ -15,7 +15,7 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-VERSION = 1.14.6s20250727
+VERSION = 1.14.6s20250926
 
 # === LIST OF FILES ====================================================
 
diff --git a/contrib/mandoc/dba.c b/contrib/mandoc/dba.c
index ee43933de3bf..ab40798e8eed 100644
--- a/contrib/mandoc/dba.c
+++ b/contrib/mandoc/dba.c
@@ -1,6 +1,6 @@
-/*	$Id: dba.c,v 1.10 2017/02/17 14:43:54 schwarze Exp $ */
+/* $Id: dba.c,v 1.11 2025/09/24 13:13:30 schwarze Exp $ */
 /*
- * Copyright (c) 2016, 2017 Ingo Schwarze <schwarze@openbsd.org>
+ * Copyright (c) 2016, 2017, 2025 Ingo Schwarze <schwarze@openbsd.org>
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -318,7 +318,8 @@ compare_names(const void *vp1, const void *vp2)
 	cp1 = *(const char * const *)vp1;
 	cp2 = *(const char * const *)vp2;
 	return (diff = *cp2 - *cp1) ? diff :
-	    strcasecmp(cp1 + 1, cp2 + 1);
+	    (diff = strcasecmp(cp1 + 1, cp2 + 1)) ? diff :
+	    strcmp(cp1 + 1, cp2 + 1);
 }
 
 static int
diff --git a/contrib/mandoc/main.c b/contrib/mandoc/main.c
index 57b06c9b9e66..d70ff1ce77b4 100644
--- a/contrib/mandoc/main.c
+++ b/contrib/mandoc/main.c
@@ -1,6 +1,6 @@
-/* $Id: main.c,v 1.361 2022/04/14 16:43:43 schwarze Exp $ */
+/* $Id: main.c,v 1.364 2025/09/24 21:30:20 schwarze Exp $ */
 /*
- * Copyright (c) 2010-2012, 2014-2021 Ingo Schwarze <schwarze@openbsd.org>
+ * Copyright (c) 2010-2012,2014-2021,2025 Ingo Schwarze <schwarze@openbsd.org>
  * Copyright (c) 2008-2012 Kristaps Dzonsons <kristaps@bsd.lv>
  * Copyright (c) 2010 Joerg Sonnenberger <joerg@netbsd.org>
  *
@@ -109,7 +109,7 @@ static	void		  parse(struct mparse *, int, const char *,
 				struct outstate *, struct manconf *);
 static	void		  passthrough(int, int);
 static	void		  process_onefile(struct mparse *, struct manpage *,
-				int, struct outstate *, struct manconf *);
+				struct outstate *, struct manconf *);
 static	void		  run_pager(struct outstate *, char *);
 static	pid_t		  spawn_pager(struct outstate *, char *);
 static	void		  usage(enum argmode) __attribute__((__noreturn__));
@@ -144,7 +144,6 @@ main(int argc, char *argv[])
 	int		 options;	/* Parser options. */
 	int		 show_usage;	/* Invalid argument: give up. */
 	int		 prio, best_prio;
-	int		 startdir;
 	int		 c;
 	enum mandoc_os	 os_e;		/* Check base system conventions. */
 	enum outmode	 outmode;	/* According to command line. */
@@ -514,7 +513,7 @@ main(int argc, char *argv[])
 			if (resnsz == 0)
 				(void)fs_search(&search, &conf.manpath,
 				    *argv, &resn, &resnsz);
-			if (resnsz == 0 && strchr(*argv, '/') == NULL) {
+			if (resnsz == 0) {
 				if (search.arch != NULL &&
 				    arch_valid(search.arch, OSENUM) == 0)
 					warnx("Unknown architecture \"%s\".",
@@ -529,20 +528,6 @@ main(int argc, char *argv[])
 				mandoc_msg_setrc(MANDOCLEVEL_BADARG);
 				continue;
 			}
-			if (resnsz == 0) {
-				if (access(*argv, R_OK) == -1) {
-					mandoc_msg_setinfilename(*argv);
-					mandoc_msg(MANDOCERR_BADARG_BAD,
-					    0, 0, "%s", strerror(errno));
-					mandoc_msg_setinfilename(NULL);
-					continue;
-				}
-				resnsz = 1;
-				resn = mandoc_calloc(resnsz, sizeof(*res));
-				resn->file = mandoc_strdup(*argv);
-				resn->ipath = SIZE_MAX;
-				resn->form = FORM_SRC;
-			}
 			if (outmode != OUTMODE_ONE || resnsz == 1) {
 				res = mandoc_reallocarray(res,
 				    ressz + resnsz, sizeof(*res));
@@ -559,7 +544,8 @@ main(int argc, char *argv[])
 
 			best_prio = 40;
 			for (ib = i = 0; i < resnsz; i++) {
-				sec = resn[i].file;
+				sec = resn[i].file +
+				    strlen(conf.manpath.paths[resn[i].ipath]);
 				sec += strcspn(sec, "123456789");
 				if (sec[0] == '\0')
 					continue; /* No section at all. */
@@ -647,23 +633,13 @@ main(int argc, char *argv[])
 	mchars_alloc();
 	mp = mparse_alloc(options, os_e, os_s);
 
-	/*
-	 * Remember the original working directory, if possible.
-	 * This will be needed if some names on the command line
-	 * are page names and some are relative file names.
-	 * Do not error out if the current directory is not
-	 * readable: Maybe it won't be needed after all.
-	 */
-	startdir = open(".", O_RDONLY | O_DIRECTORY);
 	for (i = 0; i < ressz; i++) {
-		process_onefile(mp, res + i, startdir, &outst, &conf);
+		if (i > 0)
+			mparse_reset(mp);
+		process_onefile(mp, res + i, &outst, &conf);
 		if (outst.wstop && mandoc_msg_getrc() != MANDOCLEVEL_OK)
 			break;
 	}
-	if (startdir != -1) {
-		(void)fchdir(startdir);
-		close(startdir);
-	}
 	if (conf.output.tag != NULL && conf.output.tag_found == 0) {
 		mandoc_msg(MANDOCERR_TAG, 0, 0, "%s", conf.output.tag);
 		conf.output.tag = NULL;
@@ -909,7 +885,7 @@ fs_search(const struct mansearch *cfg, const struct manpaths *paths,
 }
 
 static void
-process_onefile(struct mparse *mp, struct manpage *resp, int startdir,
+process_onefile(struct mparse *mp, struct manpage *resp,
     struct outstate *outst, struct manconf *conf)
 {
 	int	 fd;
@@ -921,8 +897,6 @@ process_onefile(struct mparse *mp, struct manpage *resp, int startdir,
 	 */
 	if (resp->ipath != SIZE_MAX)
 		(void)chdir(conf->manpath.paths[resp->ipath]);
-	else if (startdir != -1)
-		(void)fchdir(startdir);
 
 	mandoc_msg_setinfilename(resp->file);
 	if (resp->file != NULL) {
@@ -982,18 +956,12 @@ parse(struct mparse *mp, int fd, const char *file,
     struct outstate *outst, struct manconf *conf)
 {
 	static struct manpaths	 basepaths;
-	static int		 previous;
 	struct roff_meta	*meta;
 
 	assert(fd >= 0);
 	if (file == NULL)
 		file = "<stdin>";
 
-	if (previous)
-		mparse_reset(mp);
-	else
-		previous = 1;
-
 	mparse_readfd(mp, fd, file);
 	if (fd != STDIN_FILENO)
 		close(fd);
diff --git a/contrib/mandoc/man.c b/contrib/mandoc/man.c
index f651efe3de8b..26846f1cf243 100644
--- a/contrib/mandoc/man.c
+++ b/contrib/mandoc/man.c
@@ -1,4 +1,4 @@
-/* $Id: man.c,v 1.189 2022/08/16 23:01:09 schwarze Exp $ */
+/* $Id: man.c,v 1.190 2025/08/22 13:17:06 schwarze Exp $ */
 /*
  * Copyright (c) 2013-2015,2017-2019,2022 Ingo Schwarze <schwarze@openbsd.org>
  * Copyright (c) 2008, 2009, 2010, 2011 Kristaps Dzonsons <kristaps@bsd.lv>
@@ -134,6 +134,7 @@ man_ptext(struct roff_man *man, int line, char *buf, int offs)
 			*ep = '\0';
 			return 1;
 		}
+		mandoc_msg(MANDOCERR_FI_BLANK, line, i, NULL);
 		roff_elem_alloc(man, line, offs, ROFF_sp);
 		man->next = ROFF_NEXT_SIBLING;
 		return 1;
diff --git a/contrib/mandoc/man.options.1 b/contrib/mandoc/man.options.1
index be65ad98fddc..be101d4b5b62 100644
--- a/contrib/mandoc/man.options.1
+++ b/contrib/mandoc/man.options.1
@@ -1,4 +1,4 @@
-.\" $Id: man.options.1,v 1.8 2025/06/30 00:11:06 schwarze Exp $
+.\" $Id: man.options.1,v 1.9 2025/08/28 13:46:57 schwarze Exp $
 .\"
 .\" Copyright (c) 2017, 2025 Ingo Schwarze <schwarze@openbsd.org>
 .\"
@@ -14,7 +14,7 @@
 .\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 .\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 .\"
-.Dd $Mdocdate: June 30 2025 $
+.Dd $Mdocdate: August 28 2025 $
 .Dt MAN.OPTIONS 1
 .Os
 .Sh NAME
@@ -39,9 +39,18 @@
 .de At5
 .At V Pq January 1983 \\$1
 ..
+.de At8
+.No Version 8 At Pq February 1985 \\$1
+..
 .de Bx43
 .Bx 4.3 Pq June 1986 \\$1
 ..
+.de At9
+.No Version 9 At Pq September 1986 \\$1
+..
+.de At10
+.No Version 10 At Pq October 1989 \\$1
+..
 .\" option was present in groff-1.01 as contained in 4.3BSD-Net/2
 .\" and no mention of it could be found in the ChangeLog,
 .\" so it's probably older than groff-0.4, where the log started
@@ -49,7 +58,7 @@
 .No probably before groff-0.4 Pq before July 14, 1990 \\$1
 ..
 .de Eaton
-.No Eaton Pq before July 7, 1993; 1990/91? \\$1
+.No Eaton Pq before July 7, 1993; 1990/91?\& \\$1
 ..
 .\" man-1.5e was released on July 11, 1998.
 .de man15e
@@ -399,6 +408,12 @@ do not feed out paper nor stop phototypesetter
 .br
 .Nm troff :
 .At7
+.Pp
+.Bq superseded by Fl l
+interpret arguments as file names
+.br
+.Nm man :
+.At10
 .It Fl G
 preprocess with
 .Xr grap 1
@@ -549,6 +564,7 @@ mode
 .br
 .Nm man :
 .Bx4 ,
+.At10 ,
 .Eaton ;
 .No POSIX , Ox , Fx , Nx , No man-db , man-1.6 , illumos , Solaris 9-11
 .br
@@ -720,7 +736,9 @@ specify a page number for the first page
 output mode
 .br
 .Nm man :
-.At7
+.At7 ,
+.At8 ,
+.At10
 .Pp
 do not create the
 .Xr whatis 1
@@ -852,6 +870,12 @@ invoke the simultaneous input-output mode of the .rd request
 .Nm nroff , troff :
 .At7
 .Pp
+quick mode: prefer preformatted page if available
+.br
+.Nm man :
+.At8 ,
+.At10
+.Pp
 issue no warnings
 .br
 .Nm manpath :
@@ -1046,6 +1070,8 @@ output mode
 .Bx 2 Pq May 10, 1979 ,
 .At3 ,
 .At5 ,
+.At8 ,
+.At10 ,
 .Eaton ;
 .Fx , No man-db , man-1.6 , illumos , Solaris 9-11
 .br
@@ -1162,6 +1188,7 @@ list pathnames
 .At7 ,
 .At3 ,
 .At5 ,
+.At8 ,
 .Eaton ;
 .Ox , Fx , Nx , No man-db , man-1.6
 .br
diff --git a/contrib/mandoc/mandoc.1 b/contrib/mandoc/mandoc.1
index 8b6fe7d19b1e..0f83bcd53f1b 100644
--- a/contrib/mandoc/mandoc.1
+++ b/contrib/mandoc/mandoc.1
@@ -1,4 +1,4 @@
-.\" $Id: mandoc.1,v 1.272 2025/07/09 13:46:05 schwarze Exp $
+.\" $Id: mandoc.1,v 1.273 2025/08/22 13:17:06 schwarze Exp $
 .\"
 .\" Copyright (c) 2012, 2014-2023, 2025 Ingo Schwarze <schwarze@openbsd.org>
 .\" Copyright (c) 2009, 2010, 2011 Kristaps Dzonsons <kristaps@bsd.lv>
@@ -15,7 +15,7 @@
 .\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 .\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 .\"
-.Dd $Mdocdate: July 9 2025 $
+.Dd $Mdocdate: August 22 2025 $
 .Dt MANDOC 1
 .Os
 .Sh NAME
@@ -1002,14 +1002,14 @@ macro that could be represented using
 or
 .Ic \&Dx .
 .It Sy "errnos out of order"
-.Pq mdoc, Nx
+.Pq mdoc , Nx
 The
 .Ic \&Er
 items in a
 .Ic \&Bl
 list are not in alphabetical order.
 .It Sy "duplicate errno"
-.Pq mdoc, Nx
+.Pq mdoc , Nx
 A
 .Ic \&Bl
 list contains two consecutive
@@ -1150,7 +1150,7 @@ The
 argument is used as provided anyway.
 Consider checking whether the file name or the argument need a correction.
 .It Sy "missing date, using \(dq\(dq"
-.Pq mdoc, man
+.Pq mdoc , man
 The document was parsed as
 .Xr mdoc 7
 and it has no
@@ -1732,7 +1732,7 @@ or
 macro contains an opening or closing parenthesis; that's probably wrong,
 parentheses are added automatically.
 .It Sy "unknown library name"
-.Pq mdoc, not on Ox
+.Pq mdoc , not on Ox
 An
 .Ic \&Lb
 macro has an unknown name argument and will be rendered as
@@ -1790,7 +1790,7 @@ The last character is mapped to the blank character.
 .Ss "Warnings related to plain text"
 .Bl -ohang
 .It Sy "blank line in fill mode, using .sp"
-.Pq mdoc
+.Pq mdoc , man
 The meaning of blank input lines is only well-defined in non-fill mode:
 In fill mode, line breaks of text input lines are not supposed to be
 significant.
@@ -1800,6 +1800,8 @@ are formatted like
 requests.
 To request a paragraph break, use
 .Ic \&Pp
+or
+.Ic \&PP
 instead of a blank line.
 .It Sy "tab in filled text"
 .Pq mdoc , man
diff --git a/contrib/mandoc/mdoc.7 b/contrib/mandoc/mdoc.7
index 55cc7fae688d..6c2d3568baa6 100644
--- a/contrib/mandoc/mdoc.7
+++ b/contrib/mandoc/mdoc.7
@@ -1,4 +1,4 @@
-.\" $Id: mdoc.7,v 1.299 2025/06/13 16:18:28 schwarze Exp $
+.\" $Id: mdoc.7,v 1.300 2025/08/19 14:08:59 schwarze Exp $
 .\"
 .\" Copyright (c) 2010-2021, 2024, 2025 Ingo Schwarze <schwarze@openbsd.org>
 .\" Copyright (c) 2009, 2010, 2011 Kristaps Dzonsons <kristaps@bsd.lv>
@@ -15,7 +15,7 @@
 .\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 .\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 .\"
-.Dd $Mdocdate: June 13 2025 $
+.Dd $Mdocdate: August 19 2025 $
 .Dt MDOC 7
 .Os
 .Sh NAME
@@ -979,7 +979,7 @@ Unless the
 .Fl compact
 argument is specified, list entries are separated by vertical space.
 .Pp
-A list must specify one of the following list types:
+The following list types are commonly used:
 .Bl -tag -width 12n -offset indent
 .It Fl bullet
 No item heads can be specified, but a bullet will be printed at the head
@@ -994,7 +994,14 @@ The
 .Fl width
 argument has no effect; instead, the string length of each argument
 specifies the width of one column.
-If the first line of the body of a
+The width specification for the last column does not affect formatting.
+.Pp
+For two-column lists, using
+.Fl tag
+often results in simpler code, identical terminal output, and better HTML
+output, especially when the first column contains short identifiers.
+.Pp
+For compatibility with legacy documents, if the first line of the body of a
 .Fl column
 list is not an
 .Ic \&It
@@ -1016,7 +1023,7 @@ Like
 except that item heads are not parsed for macro invocations.
 Most often used in the
 .Em DIAGNOSTICS
-section with error constants in the item heads.
+section with error messages in the item heads.
 .It Fl enum
 A numbered list.
 No item heads can be specified.
@@ -1024,6 +1031,17 @@ Formatted like
 .Fl bullet ,
 except that ordinal numbers are used in place of bullets,
 starting at 1.
+.It Fl tag
+Item bodies are indented according to the
+.Fl width
+argument.
+When an item head fits inside the indentation, the item body follows
+this head on the same output line.
+Otherwise, the body starts on the output line following the head.
+.El
+.Pp
+The following list types are rarely useful:
+.Bl -tag -width 12n -offset indent
 .It Fl hang
 Like
 .Fl tag ,
@@ -1050,13 +1068,6 @@ Item bodies start on the line following item heads and are not indented.
 The
 .Fl width
 argument is ignored.
-.It Fl tag
-Item bodies are indented according to the
-.Fl width
-argument.
-When an item head fits inside the indentation, the item body follows
-this head on the same output line.
-Otherwise, the body starts on the output line following the head.
 .El
 .Pp
 Lists may be nested within lists and displays.
diff --git a/contrib/mandoc/roff_term.c b/contrib/mandoc/roff_term.c
index 85d2caeb2749..38321c830013 100644
--- a/contrib/mandoc/roff_term.c
+++ b/contrib/mandoc/roff_term.c
@@ -1,4 +1,4 @@
-/* $Id: roff_term.c,v 1.26 2025/07/16 14:33:08 schwarze Exp $ */
+/* $Id: roff_term.c,v 1.27 2025/08/21 15:38:51 schwarze Exp $ */
 /*
  * Copyright (c) 2010, 2014, 2015, 2017-2021, 2025
  *               Ingo Schwarze <schwarze@openbsd.org>
diff --git a/contrib/mandoc/term_ps.c b/contrib/mandoc/term_ps.c
index 4c6368ca1d1f..91124152d55a 100644
--- a/contrib/mandoc/term_ps.c
+++ b/contrib/mandoc/term_ps.c
@@ -1,4 +1,4 @@
-/* $Id: term_ps.c,v 1.94 2025/07/18 15:47:18 schwarze Exp $ */
+/* $Id: term_ps.c,v 1.95 2025/09/26 12:17:12 schwarze Exp $ */
 /*
  * Copyright (c) 2014-2017, 2020, 2025 Ingo Schwarze <schwarze@openbsd.org>
  * Copyright (c) 2010, 2011 Kristaps Dzonsons <kristaps@bsd.lv>
@@ -1222,6 +1222,8 @@ ps_endline(struct termp *p)
 
 	ps_plast(p);
 	ps_pclose(p);
+	p->viscol = 0;
+	p->minbl = 0;
 
 	/*
 	 * If we're in the margin, don't try to recalculate our current
@@ -1235,8 +1237,6 @@ ps_endline(struct termp *p)
 	/* Left-justify. */
 
 	p->ps->pscol = p->ps->left;
-	p->viscol = 0;
-	p->minbl = 0;
 
 	/* If we haven't printed anything, return. */
 
diff --git a/contrib/ofed/libcxgb4/dev.c b/contrib/ofed/libcxgb4/dev.c
index d3c289dad9f2..db728f5627da 100644
--- a/contrib/ofed/libcxgb4/dev.c
+++ b/contrib/ofed/libcxgb4/dev.c
@@ -144,6 +144,8 @@ static struct ibv_context *c4iw_alloc_context(struct ibv_device *ibdev,
 	context->ibv_ctx.ops = c4iw_ctx_ops;
 
 	switch (rhp->chip_version) {
+	case CHELSIO_T7:
+		PDBG("%s T7/T6/T5/T4 device\n", __FUNCTION__);
 	case CHELSIO_T6:
 		PDBG("%s T6/T5/T4 device\n", __FUNCTION__);
 	case CHELSIO_T5:
@@ -429,6 +431,8 @@ static struct verbs_device *cxgb4_driver_init(const char *uverbs_sys_path,
 	    strstr(&ibdev[2], "nex") && devnum >= 0) {
 		snprintf(dev_str, sizeof(dev_str), "/dev/t%cnex/%d", ibdev[1],
 		    devnum);
+	} else if (strstr(&ibdev[0], "chnex") && devnum >= 0) {
+		snprintf(dev_str, sizeof(dev_str), "/dev/chnex/%d", devnum);
 	} else
 		return NULL;
 
@@ -523,7 +527,10 @@ found:
 		goto err;
 
 	dev->ibv_dev.ops = &c4iw_dev_ops;
-	dev->chip_version = CHELSIO_CHIP_VERSION(hca_table[i].device >> 8);
+	if (hca_table[i].device == 0xd000)
+		dev->chip_version = CHELSIO_T7;
+	else
+		dev->chip_version = CHELSIO_CHIP_VERSION(hca_table[i].device >> 8);
 	dev->abi_version = abi_version;
 
 	PDBG("%s device claimed\n", __FUNCTION__);
diff --git a/contrib/ofed/libcxgb4/libcxgb4.h b/contrib/ofed/libcxgb4/libcxgb4.h
index b891e8b1df97..216eee05a9d8 100644
--- a/contrib/ofed/libcxgb4/libcxgb4.h
+++ b/contrib/ofed/libcxgb4/libcxgb4.h
@@ -64,6 +64,11 @@ struct c4iw_dev {
 	int abi_version;
 };
 
+static inline int dev_is_t7(struct c4iw_dev *dev)
+{
+	return dev->chip_version == CHELSIO_T7;
+}
+
 static inline int dev_is_t6(struct c4iw_dev *dev)
 {
 	return dev->chip_version == CHELSIO_T6;
diff --git a/contrib/ofed/libcxgb4/t4_chip_type.h b/contrib/ofed/libcxgb4/t4_chip_type.h
index 54b718111e3f..ae3b760c51a1 100644
--- a/contrib/ofed/libcxgb4/t4_chip_type.h
+++ b/contrib/ofed/libcxgb4/t4_chip_type.h
@@ -37,6 +37,7 @@
 #define CHELSIO_T4		0x4
 #define CHELSIO_T5		0x5
 #define CHELSIO_T6		0x6
+#define CHELSIO_T7		0x7
 
 /* We code the Chelsio T4 Family "Chip Code" as a tuple:
  *
@@ -65,6 +66,10 @@ enum chip_type {
 	T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
 	T6_FIRST_REV	= T6_A0,
 	T6_LAST_REV	= T6_A0,
+
+	T7_A1 = CHELSIO_CHIP_CODE(CHELSIO_T7, 1),
+	T7_FIRST_REV	= T7_A1,
+	T7_LAST_REV	= T7_A1,
 };
 
 static inline int is_t4(enum chip_type chip)
@@ -82,4 +87,9 @@ static inline int is_t6(enum chip_type chip)
 	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
 }
 
+static inline int is_t7(enum chip_type chip)
+{
+	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T7);
+}
+
 #endif /* __T4_CHIP_TYPE_H__ */
diff --git a/contrib/ofed/libcxgb4/t4_pci_id_tbl.h b/contrib/ofed/libcxgb4/t4_pci_id_tbl.h
index 50812a1d67bd..0ff7e689dc84 100644
--- a/contrib/ofed/libcxgb4/t4_pci_id_tbl.h
+++ b/contrib/ofed/libcxgb4/t4_pci_id_tbl.h
@@ -92,8 +92,7 @@
 #endif
 
 CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
-	/* T4 adapters:
-	 */
+	/* T4 adapters */
 	CH_PCI_ID_TABLE_FENTRY(0x4000),	/* T440-dbg */
 	CH_PCI_ID_TABLE_FENTRY(0x4001),	/* T420-cr */
 	CH_PCI_ID_TABLE_FENTRY(0x4002),	/* T422-cr */
@@ -119,8 +118,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 	CH_PCI_ID_TABLE_FENTRY(0x4087),	/* Custom T440-cr */
 	CH_PCI_ID_TABLE_FENTRY(0x4088),	/* Custom T440 2-xaui, 2-xfi */
 
-	/* T5 adapters:
-	 */
+	/* T5 adapters */
 	CH_PCI_ID_TABLE_FENTRY(0x5000),	/* T580-dbg */
 	CH_PCI_ID_TABLE_FENTRY(0x5001),	/* T520-cr */
 	CH_PCI_ID_TABLE_FENTRY(0x5002),	/* T522-cr */
@@ -169,8 +167,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 	CH_PCI_ID_TABLE_FENTRY(0x509b),	/* Custom T540-CR LOM */
 	CH_PCI_ID_TABLE_FENTRY(0x509c),	/* Custom T520-CR*/
 
-	/* T6 adapters:
-	 */
+	/* T6 adapters */
 	CH_PCI_ID_TABLE_FENTRY(0x6001),
 	CH_PCI_ID_TABLE_FENTRY(0x6002),
 	CH_PCI_ID_TABLE_FENTRY(0x6003),
@@ -184,6 +181,24 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 	CH_PCI_ID_TABLE_FENTRY(0x6011),
 	CH_PCI_ID_TABLE_FENTRY(0x6014),
 	CH_PCI_ID_TABLE_FENTRY(0x6015),
+	CH_PCI_ID_TABLE_FENTRY(0x6081),
+
+	/* T7 adapters */
+	{ .vendor = 0x1425, .device = 0xd000 }, /* T7 FPGA */
+	CH_PCI_ID_TABLE_FENTRY(0x7000),	/* T7-DBG */
+	CH_PCI_ID_TABLE_FENTRY(0x7001),	/* T7250 */
+	CH_PCI_ID_TABLE_FENTRY(0x7002),	/* S7250 */
+	CH_PCI_ID_TABLE_FENTRY(0x7003),	/* T7450 */
+	CH_PCI_ID_TABLE_FENTRY(0x7004),	/* S7450 */
+	CH_PCI_ID_TABLE_FENTRY(0x7005),	/* T72200 */
+	CH_PCI_ID_TABLE_FENTRY(0x7006),	/* S72200 */
+	CH_PCI_ID_TABLE_FENTRY(0x7007),	/* T72200-FH */
+	CH_PCI_ID_TABLE_FENTRY(0x7008),	/* T71400 */
+	CH_PCI_ID_TABLE_FENTRY(0x7009),	/* S7210-BT */
+	CH_PCI_ID_TABLE_FENTRY(0x700a),	/* T7450-RC */
+	CH_PCI_ID_TABLE_FENTRY(0x700b),	/* T72200-RC */
+	CH_PCI_ID_TABLE_FENTRY(0x700c),	/* T72200-FH-RC */
+	CH_PCI_ID_TABLE_FENTRY(0x7080), /* Custom */
 CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
 
 #endif /* __T4_PCI_ID_TBL_H__ */
diff --git a/contrib/tnftp/src/ftp.1 b/contrib/tnftp/src/ftp.1
index 34a88c23520b..e9f09ddca8cc 100644
--- a/contrib/tnftp/src/ftp.1
+++ b/contrib/tnftp/src/ftp.1
@@ -58,7 +58,7 @@
 .\"
 .\"	@(#)ftp.1	8.3 (Berkeley) 10/9/94
 .\"
-.Dd May 10, 2008
+.Dd September 25, 2025
 .Dt FTP 1
 .Os
 .Sh NAME
@@ -2325,8 +2325,7 @@ for an example of how to make this automatic.
 .Sh SEE ALSO
 .Xr getservbyname 3 ,
 .Xr editrc 5 ,
-.Xr services 5 ,
-.Xr ftpd 8
+.Xr services 5
 .Sh STANDARDS
 .Nm
 attempts to be compliant with:
diff --git a/contrib/tzcode/localtime.c b/contrib/tzcode/localtime.c
index 8638ac9ba2cd..1668475ea646 100644
--- a/contrib/tzcode/localtime.c
+++ b/contrib/tzcode/localtime.c
@@ -677,7 +677,7 @@ tzloadbody(char const *name, struct state *sp, char tzloadflags,
 	  while (*relname == '/')
 	    relname++;
 	}
-	dd = open(TZDIR, O_DIRECTORY | O_RDONLY);
+	dd = open(TZDIR, O_DIRECTORY | O_SEARCH | O_CLOEXEC);
 	if ((tzloadflags & TZLOAD_FROMENV) && issetugid()) {
 	  if (dd < 0)
 	    return errno;
@@ -687,14 +687,14 @@ tzloadbody(char const *name, struct state *sp, char tzloadflags,
 	    fid = -1;
 	    errno = EINVAL;
 	  } else {
-	    fid = openat(dd, relname, O_RDONLY | O_BINARY, AT_RESOLVE_BENEATH);
+	    fid = openat(dd, relname, O_RDONLY | O_CLOEXEC | O_RESOLVE_BENEATH);
 	  }
 	} else {
 	  if (dd < 0) {
 	    relname = name;
 	    dd = AT_FDCWD;
 	  }
-	  fid = openat(dd, relname, O_RDONLY | O_BINARY, 0);
+	  fid = openat(dd, relname, O_RDONLY | O_CLOEXEC);
 	}
 	if (dd != AT_FDCWD && dd >= 0) {
 	  serrno = errno;
diff --git a/crypto/heimdal/kadmin/dump.c b/crypto/heimdal/kadmin/dump.c
index 91a5ada86607..2c302eced210 100644
--- a/crypto/heimdal/kadmin/dump.c
+++ b/crypto/heimdal/kadmin/dump.c
@@ -42,32 +42,51 @@ dump(struct dump_options *opt, int argc, char **argv)
 {
     krb5_error_code ret;
     FILE *f;
+    struct hdb_print_entry_arg parg;
     HDB *db = NULL;
 
-    if(!local_flag) {
+    if (!local_flag) {
 	krb5_warnx(context, "dump is only available in local (-l) mode");
 	return 0;
     }
 
     db = _kadm5_s_get_db(kadm_handle);
 
-    if(argc == 0)
+    if (argc == 0)
 	f = stdout;
     else
 	f = fopen(argv[0], "w");
 
-    if(f == NULL) {
+    if (f == NULL) {
 	krb5_warn(context, errno, "open: %s", argv[0]);
 	goto out;
     }
     ret = db->hdb_open(context, db, O_RDONLY, 0600);
-    if(ret) {
+    if (ret) {
 	krb5_warn(context, ret, "hdb_open");
 	goto out;
     }
 
+    if (!opt->format_string || strcmp(opt->format_string, "Heimdal") == 0) {
+        parg.fmt = HDB_DUMP_HEIMDAL;
+    } else if (opt->format_string && strcmp(opt->format_string, "MIT") == 0) {
+        parg.fmt = HDB_DUMP_MIT;
+        fprintf(f, "kdb5_util load_dump version 5\n"); /* 5||6, either way */
+    } else if (opt->format_string) {
+	/* Open the format string as a MIT mkey file. */
+	ret = hdb_read_master_key(context, opt->format_string, &db->hdb_mit_key);
+	if (ret)
+	    krb5_errx(context, 1, "Cannot open MIT mkey file");
+	db->hdb_mit_key_set = 1;
+        parg.fmt = HDB_DUMP_MIT;
+	opt->decrypt_flag = 1;
+        fprintf(f, "kdb5_util load_dump version 5\n"); /* 5||6, either way */
+    } else {
+        krb5_errx(context, 1, "Supported dump formats: Heimdal and MIT");
+    }
+    parg.out = f;
     hdb_foreach(context, db, opt->decrypt_flag ? HDB_F_DECRYPT : 0,
-		hdb_print_entry, f);
+		hdb_print_entry, &parg);
 
     db->hdb_close(context, db);
 out:
diff --git a/crypto/heimdal/kadmin/kadmin-commands.in b/crypto/heimdal/kadmin/kadmin-commands.in
index 4396ff800441..dc36db4e0a00 100644
--- a/crypto/heimdal/kadmin/kadmin-commands.in
+++ b/crypto/heimdal/kadmin/kadmin-commands.in
@@ -76,6 +76,12 @@ command = {
 		type = "flag"
 		help = "decrypt keys"
 	}
+	option = {
+		long = "format"
+		short = "f"
+		type = "string"
+		help = "dump format, mit or heimdal (default: heimdal)"
+	}
 	argument = "[dump-file]"
 	min_args = "0"
 	max_args = "1"
diff --git a/crypto/heimdal/kadmin/kadmin.8 b/crypto/heimdal/kadmin/kadmin.8
index bd2fd4e7363f..e4555cd529f4 100644
--- a/crypto/heimdal/kadmin/kadmin.8
+++ b/crypto/heimdal/kadmin/kadmin.8
@@ -31,7 +31,7 @@
 .\"
 .\" $Id$
 .\"
-.Dd Feb  22, 2007
+.Dd October 5, 2025
 .Dt KADMIN 8
 .Os HEIMDAL
 .Sh NAME
@@ -286,14 +286,39 @@ When running in local mode, the following commands can also be used:
 .Pp
 .Nm dump
 .Op Fl d | Fl Fl decrypt
+.Op Fl f Ns Ar format | Fl Fl format= Ns Ar format
 .Op Ar dump-file
 .Bd -ragged -offset indent
 Writes the database in
-.Dq human readable
+.Dq machine readable text
 form to the specified file, or standard out. If the database is
 encrypted, the dump will also have encrypted keys, unless
 .Fl Fl decrypt
 is used.
+.Pp
+If
+.Fl Fl format=MIT
+is used then the dump will be in MIT format.
+This option may be used if you require that all principal
+passwords be changed after loading the dump into an MIT KDC database.
+.Pp
+If
+.Fl Fl format=<keytab-file>
+is used, the
+.Dq <keytab-file>
+should hold the master key for the
+MIT KDC (usually a file called /var/db/krb5kdc/.k5.YOUR.REALM).
+This will cause the keys to be re-encrypted in the MIT master
+key as well as doing the dump in MIT format.
+When this dump is loaded into the MIT KDC's database,
+the principals that had at least one strong encryption type
+key should work and any keytabs for those principals should still work.
+The principcals with only weak encryption keys will require a
+.Dq change_password
+be done on the MIT KDC to get them working.
+The
+.Fl Fl decrypt
+flag is meaningless for this case.
 .Ed
 .Pp
 .Nm init
diff --git a/crypto/heimdal/kdc/hpropd.c b/crypto/heimdal/kdc/hpropd.c
index 1cfc688b2a6c..c76be0446705 100644
--- a/crypto/heimdal/kdc/hpropd.c
+++ b/crypto/heimdal/kdc/hpropd.c
@@ -85,23 +85,23 @@ main(int argc, char **argv)
     setprogname(argv[0]);
 
     ret = krb5_init_context(&context);
-    if(ret)
+    if (ret)
 	exit(1);
 
     ret = krb5_openlog(context, "hpropd", &fac);
-    if(ret)
+    if (ret)
 	errx(1, "krb5_openlog");
     krb5_set_warn_dest(context, fac);
 
-    if(getarg(args, num_args, argc, argv, &optidx))
+    if (getarg(args, num_args, argc, argv, &optidx))
 	usage(1);
 
-    if(local_realm != NULL)
+    if (local_realm != NULL)
 	krb5_set_default_realm(context, local_realm);
 
-    if(help_flag)
+    if (help_flag)
 	usage(0);
-    if(version_flag) {
+    if (version_flag) {
 	print_version(NULL);
 	exit(0);
     }
@@ -117,7 +117,7 @@ main(int argc, char **argv)
     if (database == NULL)
 	database = hdb_default_db(context);
 
-    if(from_stdin) {
+    if (from_stdin) {
 	sock = STDIN_FILENO;
     } else {
 	struct sockaddr_storage ss;
@@ -145,7 +145,7 @@ main(int argc, char **argv)
 					    HPROP_PORT), &sock);
 	}
 	sin_len = sizeof(ss);
-	if(getpeername(sock, sa, &sin_len) < 0)
+	if (getpeername(sock, sa, &sin_len) < 0)
 	    krb5_err(context, 1, errno, "getpeername");
 
 	if (inet_ntop(sa->sa_family,
@@ -158,7 +158,7 @@ main(int argc, char **argv)
 	krb5_log(context, fac, 0, "Connection from %s", addr_name);
 
 	ret = krb5_kt_register(context, &hdb_kt_ops);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "krb5_kt_register");
 
 	if (ktname != NULL) {
@@ -173,7 +173,7 @@ main(int argc, char **argv)
 
 	ret = krb5_recvauth(context, &ac, &sock, HPROP_VERSION, NULL,
 			    0, keytab, &ticket);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "krb5_recvauth");
 
 	ret = krb5_unparse_name(context, ticket->server, &server);
@@ -186,15 +186,15 @@ main(int argc, char **argv)
 	krb5_free_ticket (context, ticket);
 
 	ret = krb5_auth_con_getauthenticator(context, ac, &authent);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "krb5_auth_con_getauthenticator");
 
 	ret = krb5_make_principal(context, &c1, NULL, "kadmin", "hprop", NULL);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "krb5_make_principal");
 	_krb5_principalname2krb5_principal(context, &c2,
 					   authent->cname, authent->crealm);
-	if(!krb5_principal_compare(context, c1, c2)) {
+	if (!krb5_principal_compare(context, c1, c2)) {
 	    char *s;
 	    ret = krb5_unparse_name(context, c2, &s);
 	    if (ret)
@@ -205,48 +205,48 @@ main(int argc, char **argv)
 	krb5_free_principal(context, c2);
 
 	ret = krb5_kt_close(context, keytab);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "krb5_kt_close");
     }
 
-    if(!print_dump) {
+    if (!print_dump) {
 	asprintf(&tmp_db, "%s~", database);
 
 	ret = hdb_create(context, &db, tmp_db);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "hdb_create(%s)", tmp_db);
 	ret = db->hdb_open(context, db, O_RDWR | O_CREAT | O_TRUNC, 0600);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "hdb_open(%s)", tmp_db);
     }
 
     nprincs = 0;
-    while(1){
+    while (1){
 	krb5_data data;
 	hdb_entry_ex entry;
 
-	if(from_stdin) {
+	if (from_stdin) {
 	    ret = krb5_read_message(context, &sock, &data);
-	    if(ret != 0 && ret != HEIM_ERR_EOF)
+	    if (ret != 0 && ret != HEIM_ERR_EOF)
 		krb5_err(context, 1, ret, "krb5_read_message");
 	} else {
 	    ret = krb5_read_priv_message(context, ac, &sock, &data);
-	    if(ret)
+	    if (ret)
 		krb5_err(context, 1, ret, "krb5_read_priv_message");
 	}
 
-	if(ret == HEIM_ERR_EOF || data.length == 0) {
-	    if(!from_stdin) {
+	if (ret == HEIM_ERR_EOF || data.length == 0) {
+	    if (!from_stdin) {
 		data.data = NULL;
 		data.length = 0;
 		krb5_write_priv_message(context, ac, &sock, &data);
 	    }
-	    if(!print_dump) {
+	    if (!print_dump) {
 		ret = db->hdb_close(context, db);
-		if(ret)
+		if (ret)
 		    krb5_err(context, 1, ret, "db_close");
 		ret = db->hdb_rename(context, db, database);
-		if(ret)
+		if (ret)
 		    krb5_err(context, 1, ret, "db_rename");
 	    }
 	    break;
@@ -254,20 +254,24 @@ main(int argc, char **argv)
 	memset(&entry, 0, sizeof(entry));
 	ret = hdb_value2entry(context, &data, &entry.entry);
 	krb5_data_free(&data);
-	if(ret)
+	if (ret)
 	    krb5_err(context, 1, ret, "hdb_value2entry");
-	if(print_dump)
-	    hdb_print_entry(context, db, &entry, stdout);
-	else {
+	if (print_dump) {
+            struct hdb_print_entry_arg parg;
+
+            parg.out = stdout;
+            parg.fmt = HDB_DUMP_HEIMDAL;
+	    hdb_print_entry(context, db, &entry, &parg);
+        } else {
 	    ret = db->hdb_store(context, db, 0, &entry);
-	    if(ret == HDB_ERR_EXISTS) {
+	    if (ret == HDB_ERR_EXISTS) {
 		char *s;
 		ret = krb5_unparse_name(context, entry.entry.principal, &s);
 		if (ret)
 		    s = strdup(unparseable_name);
 		krb5_warnx(context, "Entry exists: %s", s);
 		free(s);
-	    } else if(ret)
+	    } else if (ret)
 		krb5_err(context, 1, ret, "db_store");
 	    else
 		nprincs++;
diff --git a/crypto/heimdal/kdc/mit_dump.c b/crypto/heimdal/kdc/mit_dump.c
index f28e932b15b4..4397d1ad897d 100644
--- a/crypto/heimdal/kdc/mit_dump.c
+++ b/crypto/heimdal/kdc/mit_dump.c
@@ -33,6 +33,17 @@
 
 #include "hprop.h"
 
+extern krb5_error_code _hdb_mdb_value2entry(krb5_context context,
+                                            krb5_data *data,
+                                            krb5_kvno target_kvno,
+                                            hdb_entry *entry);
+
+extern int _hdb_mit_dump2mitdb_entry(krb5_context context,
+                                     char *line,
+                                     krb5_storage *sp);
+
+
+
 /*
 can have any number of princ stanzas.
 format is as follows (only \n indicates newlines)
@@ -74,19 +85,6 @@ unless no extra data
 
 */
 
-static int
-hex_to_octet_string(const char *ptr, krb5_data *data)
-{
-    size_t i;
-    unsigned int v;
-    for(i = 0; i < data->length; i++) {
-	if(sscanf(ptr + 2 * i, "%02x", &v) != 1)
-	    return -1;
-	((unsigned char*)data->data)[i] = v;
-    }
-    return 2 * i;
-}
-
 static char *
 nexttoken(char **p)
 {
@@ -97,321 +95,116 @@ nexttoken(char **p)
     return q;
 }
 
-static size_t
-getdata(char **p, unsigned char *buf, size_t len)
-{
-    size_t i;
-    int v;
-    char *q = nexttoken(p);
-    i = 0;
-    while(*q && i < len) {
-	if(sscanf(q, "%02x", &v) != 1)
-	    break;
-	buf[i++] = v;
-	q += 2;
-    }
-    return i;
-}
-
-static int
-getint(char **p)
-{
-    int val;
-    char *q = nexttoken(p);
-    sscanf(q, "%d", &val);
-    return val;
-}
-
 #include <kadm5/admin.h>
 
-static void
-attr_to_flags(unsigned attr, HDBFlags *flags)
-{
-    flags->postdate =		!(attr & KRB5_KDB_DISALLOW_POSTDATED);
-    flags->forwardable =	!(attr & KRB5_KDB_DISALLOW_FORWARDABLE);
-    flags->initial =	       !!(attr & KRB5_KDB_DISALLOW_TGT_BASED);
-    flags->renewable =		!(attr & KRB5_KDB_DISALLOW_RENEWABLE);
-    flags->proxiable =		!(attr & KRB5_KDB_DISALLOW_PROXIABLE);
-    /* DUP_SKEY */
-    flags->invalid =	       !!(attr & KRB5_KDB_DISALLOW_ALL_TIX);
-    flags->require_preauth =   !!(attr & KRB5_KDB_REQUIRES_PRE_AUTH);
-    flags->require_hwauth =    !!(attr & KRB5_KDB_REQUIRES_HW_AUTH);
-    flags->server =		!(attr & KRB5_KDB_DISALLOW_SVR);
-    flags->change_pw = 	       !!(attr & KRB5_KDB_PWCHANGE_SERVICE);
-    flags->client =	        1; /* XXX */
-}
-
-#define KRB5_KDB_SALTTYPE_NORMAL	0
-#define KRB5_KDB_SALTTYPE_V4		1
-#define KRB5_KDB_SALTTYPE_NOREALM	2
-#define KRB5_KDB_SALTTYPE_ONLYREALM	3
-#define KRB5_KDB_SALTTYPE_SPECIAL	4
-#define KRB5_KDB_SALTTYPE_AFS3		5
-
-static krb5_error_code
-fix_salt(krb5_context context, hdb_entry *ent, int key_num)
+static int
+my_fgetln(FILE *f, char **buf, size_t *sz, size_t *len)
 {
-    krb5_error_code ret;
-    Salt *salt = ent->keys.val[key_num].salt;
-    /* fix salt type */
-    switch((int)salt->type) {
-    case KRB5_KDB_SALTTYPE_NORMAL:
-	salt->type = KRB5_PADATA_PW_SALT;
-	break;
-    case KRB5_KDB_SALTTYPE_V4:
-	krb5_data_free(&salt->salt);
-	salt->type = KRB5_PADATA_PW_SALT;
-	break;
-    case KRB5_KDB_SALTTYPE_NOREALM:
-    {
-	size_t len;
-	size_t i;
-	char *p;
-
-	len = 0;
-	for (i = 0; i < ent->principal->name.name_string.len; ++i)
-	    len += strlen(ent->principal->name.name_string.val[i]);
-	ret = krb5_data_alloc (&salt->salt, len);
-	if (ret)
-	    return ret;
-	p = salt->salt.data;
-	for (i = 0; i < ent->principal->name.name_string.len; ++i) {
-	    memcpy (p,
-		    ent->principal->name.name_string.val[i],
-		    strlen(ent->principal->name.name_string.val[i]));
-	    p += strlen(ent->principal->name.name_string.val[i]);
-	}
-
-	salt->type = KRB5_PADATA_PW_SALT;
-	break;
+    char *p, *n;
+
+    if (!*buf) {
+        *buf = malloc(*sz ? *sz : 2048);
+        if (!*buf)
+            return ENOMEM;
+        if (!*sz)
+            *sz = 2048;
     }
-    case KRB5_KDB_SALTTYPE_ONLYREALM:
-	krb5_data_free(&salt->salt);
-	ret = krb5_data_copy(&salt->salt,
-			     ent->principal->realm,
-			     strlen(ent->principal->realm));
-	if(ret)
-	    return ret;
-	salt->type = KRB5_PADATA_PW_SALT;
-	break;
-    case KRB5_KDB_SALTTYPE_SPECIAL:
-	salt->type = KRB5_PADATA_PW_SALT;
-	break;
-    case KRB5_KDB_SALTTYPE_AFS3:
-	krb5_data_free(&salt->salt);
-	ret = krb5_data_copy(&salt->salt,
-		       ent->principal->realm,
-		       strlen(ent->principal->realm));
-	if(ret)
-	    return ret;
-	salt->type = KRB5_PADATA_AFS3_SALT;
-	break;
-    default:
-	abort();
+    *len = 0;
+    while ((p = fgets(&(*buf)[*len], *sz, f))) {
+        if (strcspn(*buf, "\r\n") || feof(f)) {
+            *len = strlen(*buf);
+            return 0;
+        }
+        *len += strlen(&(*buf)[*len]); /* *len should be == *sz */
+        n = realloc(buf, *sz + (*sz >> 1));
+        if (!n) {
+            free(*buf);
+            *buf = NULL;
+            *sz = 0;
+            *len = 0;
+            return ENOMEM;
+        }
+        *buf = n;
+        *sz += *sz >> 1;
     }
-    return 0;
+    return 0; /* *len == 0 || no EOL -> EOF */
 }
 
 int
 mit_prop_dump(void *arg, const char *file)
 {
     krb5_error_code ret;
-    char line [2048];
-    FILE *f;
+    size_t line_bufsz = 0;
+    size_t line_len = 0;
+    char *line = NULL;
     int lineno = 0;
+    FILE *f;
     struct hdb_entry_ex ent;
-
     struct prop_data *pd = arg;
+    krb5_storage *sp = NULL;
+    krb5_data kdb_ent;
 
+    memset(&ent, 0, sizeof (ent));
     f = fopen(file, "r");
-    if(f == NULL)
+    if (f == NULL)
 	return errno;
 
-    while(fgets(line, sizeof(line), f)) {
-	char *p = line, *q;
-
-	int i;
-
-	int num_tl_data;
-	int num_key_data;
-	int high_kvno;
-	int attributes;
+    ret = ENOMEM;
+    sp = krb5_storage_emem();
+    if (!sp)
+        goto out;
+    while ((ret = my_fgetln(f, &line, &line_bufsz, &line_len)) == 0) {
+        char *p = line;
+        char *q;
+        lineno++;
 
-	int tmp;
-
-	lineno++;
-
-	memset(&ent, 0, sizeof(ent));
-
-	q = nexttoken(&p);
-	if(strcmp(q, "kdb5_util") == 0) {
+	if(strncmp(line, "kdb5_util", strlen("kdb5_util")) == 0) {
 	    int major;
+            q = nexttoken(&p);
+            if (strcmp(q, "kdb5_util"))
+                errx(1, "line %d: unknown version", lineno);
 	    q = nexttoken(&p); /* load_dump */
-	    if(strcmp(q, "load_dump"))
+	    if (strcmp(q, "load_dump"))
 		errx(1, "line %d: unknown version", lineno);
 	    q = nexttoken(&p); /* load_dump */
-	    if(strcmp(q, "version"))
+	    if (strcmp(q, "version"))
 		errx(1, "line %d: unknown version", lineno);
 	    q = nexttoken(&p); /* x.0 */
-	    if(sscanf(q, "%d", &major) != 1)
+	    if (sscanf(q, "%d", &major) != 1)
 		errx(1, "line %d: unknown version", lineno);
-	    if(major != 4 && major != 5 && major != 6)
+	    if (major != 4 && major != 5 && major != 6)
 		errx(1, "unknown dump file format, got %d, expected 4-6",
 		     major);
 	    continue;
-	} else if(strcmp(q, "policy") == 0) {
+	} else if(strncmp(p, "policy", strlen("policy")) == 0) {
+            warnx("line: %d: ignoring policy (not supported)", lineno);
 	    continue;
-	} else if(strcmp(q, "princ") != 0) {
+	} else if(strncmp(p, "princ", strlen("princ")) != 0) {
 	    warnx("line %d: not a principal", lineno);
 	    continue;
 	}
-	tmp = getint(&p);
-	if(tmp != 38) {
-	    warnx("line %d: bad base length %d != 38", lineno, tmp);
-	    continue;
-	}
-	nexttoken(&p); /* length of principal */
-	num_tl_data = getint(&p); /* number of tl-data */
-	num_key_data = getint(&p); /* number of key-data */
-	getint(&p);  /* length of extra data */
-	q = nexttoken(&p); /* principal name */
-	krb5_parse_name(pd->context, q, &ent.entry.principal);
-	attributes = getint(&p); /* attributes */
-	attr_to_flags(attributes, &ent.entry.flags);
-	tmp = getint(&p); /* max life */
-	if(tmp != 0) {
-	    ALLOC(ent.entry.max_life);
-	    *ent.entry.max_life = tmp;
-	}
-	tmp = getint(&p); /* max renewable life */
-	if(tmp != 0) {
-	    ALLOC(ent.entry.max_renew);
-	    *ent.entry.max_renew = tmp;
-	}
-	tmp = getint(&p); /* expiration */
-	if(tmp != 0 && tmp != 2145830400) {
-	    ALLOC(ent.entry.valid_end);
-	    *ent.entry.valid_end = tmp;
-	}
-	tmp = getint(&p); /* pw expiration */
-	if(tmp != 0) {
-	    ALLOC(ent.entry.pw_end);
-	    *ent.entry.pw_end = tmp;
-	}
-	nexttoken(&p); /* last auth */
-	nexttoken(&p); /* last failed auth */
-	nexttoken(&p); /* fail auth count */
-	for(i = 0; i < num_tl_data; i++) {
-	    unsigned long val;
-	    int tl_type, tl_length;
-	    unsigned char *buf;
-	    krb5_principal princ;
-
-	    tl_type = getint(&p); /* data type */
-	    tl_length = getint(&p); /* data length */
-
-#define mit_KRB5_TL_LAST_PWD_CHANGE	1
-#define mit_KRB5_TL_MOD_PRINC		2
-	    switch(tl_type) {
-	    case mit_KRB5_TL_LAST_PWD_CHANGE:
-		buf = malloc(tl_length);
-		if (buf == NULL)
-		    errx(ENOMEM, "malloc");
-		getdata(&p, buf, tl_length); /* data itself */
-		val = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
-		free(buf);
-		ALLOC(ent.entry.extensions);
-		ALLOC_SEQ(ent.entry.extensions, 1);
-		ent.entry.extensions->val[0].mandatory = 0;
-		ent.entry.extensions->val[0].data.element
-		    = choice_HDB_extension_data_last_pw_change;
-		ent.entry.extensions->val[0].data.u.last_pw_change = val;
-		break;
-	    case mit_KRB5_TL_MOD_PRINC:
-		buf = malloc(tl_length);
-		if (buf == NULL)
-		    errx(ENOMEM, "malloc");
-		getdata(&p, buf, tl_length); /* data itself */
-		val = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
-		ret = krb5_parse_name(pd->context, (char *)buf + 4, &princ);
-		if (ret)
-		    krb5_err(pd->context, 1, ret,
-			     "parse_name: %s", (char *)buf + 4);
-		free(buf);
-		ALLOC(ent.entry.modified_by);
-		ent.entry.modified_by->time = val;
-		ent.entry.modified_by->principal = princ;
-		break;
-	    default:
-		nexttoken(&p);
-		break;
-	    }
-	}
-	ALLOC_SEQ(&ent.entry.keys, num_key_data);
-	high_kvno = -1;
-	for(i = 0; i < num_key_data; i++) {
-	    int key_versions;
-	    int kvno;
-	    key_versions = getint(&p); /* key data version */
-	    kvno = getint(&p);
-
-	    /*
-	     * An MIT dump file may contain multiple sets of keys with
-	     * different kvnos.  Since the Heimdal database can only represent
-	     * one kvno per principal, we only want the highest set.  Assume
-	     * that set will be given first, and discard all keys with lower
-	     * kvnos.
-	     */
-	    if (kvno > high_kvno && high_kvno != -1)
-		errx(1, "line %d: high kvno keys given after low kvno keys",
-		     lineno);
-	    else if (kvno < high_kvno) {
-		nexttoken(&p); /* key type */
-		nexttoken(&p); /* key length */
-		nexttoken(&p); /* key */
-		if (key_versions > 1) {
-		    nexttoken(&p); /* salt type */
-		    nexttoken(&p); /* salt length */
-		    nexttoken(&p); /* salt */
-		}
-		ent.entry.keys.len--;
-		continue;
-	    }
-	    ent.entry.kvno = kvno;
-	    high_kvno = kvno;
-	    ALLOC(ent.entry.keys.val[i].mkvno);
-	    *ent.entry.keys.val[i].mkvno = 1;
-
-	    /* key version 0 -- actual key */
-	    ent.entry.keys.val[i].key.keytype = getint(&p); /* key type */
-	    tmp = getint(&p); /* key length */
-	    /* the first two bytes of the key is the key length --
-	       skip it */
-	    krb5_data_alloc(&ent.entry.keys.val[i].key.keyvalue, tmp - 2);
-	    q = nexttoken(&p); /* key itself */
-	    hex_to_octet_string(q + 4, &ent.entry.keys.val[i].key.keyvalue);
-
-	    if(key_versions > 1) {
-		/* key version 1 -- optional salt */
-		ALLOC(ent.entry.keys.val[i].salt);
-		ent.entry.keys.val[i].salt->type = getint(&p); /* salt type */
-		tmp = getint(&p); /* salt length */
-		if(tmp > 0) {
-		    krb5_data_alloc(&ent.entry.keys.val[i].salt->salt, tmp - 2);
-		    q = nexttoken(&p); /* salt itself */
-		    hex_to_octet_string(q + 4,
-					&ent.entry.keys.val[i].salt->salt);
-		} else {
-		    ent.entry.keys.val[i].salt->salt.length = 0;
-		    ent.entry.keys.val[i].salt->salt.data = NULL;
-		    getint(&p);	/* -1, if no data. */
-		}
-		fix_salt(pd->context, &ent.entry, i);
-	    }
-	}
-	nexttoken(&p); /* extra data */
-	v5_prop(pd->context, NULL, &ent, arg);
+        krb5_storage_truncate(sp, 0);
+        ret = _hdb_mit_dump2mitdb_entry(pd->context, line, sp);
+        if (ret) break;
+        ret = krb5_storage_to_data(sp, &kdb_ent);
+        if (ret) break;
+        ret = _hdb_mdb_value2entry(pd->context, &kdb_ent, 0, &ent.entry);
+        krb5_data_free(&kdb_ent);
+        if (ret) break;
+	ret = v5_prop(pd->context, NULL, &ent, arg);
+        hdb_free_entry(pd->context, &ent);
+        if (ret) break;
     }
+
+out:
     fclose(f);
-    return 0;
+    free(line);
+    if (sp)
+        krb5_storage_free(sp);
+    if (ret && ret == ENOMEM)
+        errx(1, "out of memory");
+    if (ret)
+        errx(1, "line %d: problem parsing dump line", lineno);
+    return ret;
 }
+
diff --git a/crypto/heimdal/lib/hdb/Makefile.am b/crypto/heimdal/lib/hdb/Makefile.am
index b629f56258d2..fd009bd26867 100644
--- a/crypto/heimdal/lib/hdb/Makefile.am
+++ b/crypto/heimdal/lib/hdb/Makefile.am
@@ -29,6 +29,7 @@ gen_files_hdb = \
 	asn1_HDB_Ext_Lan_Manager_OWF.x \
 	asn1_HDB_Ext_Password.x \
 	asn1_HDB_Ext_Aliases.x \
+	asn1_HDB_Ext_KeySet.x \
 	asn1_HDB_extension.x \
 	asn1_HDB_extensions.x \
 	asn1_hdb_entry.x \
diff --git a/crypto/heimdal/lib/hdb/common.c b/crypto/heimdal/lib/hdb/common.c
index 2715adf63dca..80482e7a4c1c 100644
--- a/crypto/heimdal/lib/hdb/common.c
+++ b/crypto/heimdal/lib/hdb/common.c
@@ -105,7 +105,6 @@ _hdb_fetch_kvno(krb5_context context, HDB *db, krb5_const_principal principal,
     krb5_principal enterprise_principal = NULL;
     krb5_data key, value;
     krb5_error_code ret;
-    int code;
 
     if (principal->name.name_type == KRB5_NT_ENTERPRISE_PRINCIPAL) {
 	if (principal->name.name_string.len != 1) {
@@ -125,43 +124,74 @@ _hdb_fetch_kvno(krb5_context context, HDB *db, krb5_const_principal principal,
     hdb_principal2key(context, principal, &key);
     if (enterprise_principal)
 	krb5_free_principal(context, enterprise_principal);
-    code = db->hdb__get(context, db, key, &value);
+    ret = db->hdb__get(context, db, key, &value);
     krb5_data_free(&key);
-    if(code)
-	return code;
-    code = hdb_value2entry(context, &value, &entry->entry);
-    if (code == ASN1_BAD_ID && (flags & HDB_F_CANON) == 0) {
+    if(ret)
+	return ret;
+    ret = hdb_value2entry(context, &value, &entry->entry);
+    if (ret == ASN1_BAD_ID && (flags & HDB_F_CANON) == 0) {
 	krb5_data_free(&value);
 	return HDB_ERR_NOENTRY;
-    } else if (code == ASN1_BAD_ID) {
+    } else if (ret == ASN1_BAD_ID) {
 	hdb_entry_alias alias;
 
-	code = hdb_value2entry_alias(context, &value, &alias);
-	if (code) {
+	ret = hdb_value2entry_alias(context, &value, &alias);
+	if (ret) {
 	    krb5_data_free(&value);
-	    return code;
+	    return ret;
 	}
 	hdb_principal2key(context, alias.principal, &key);
 	krb5_data_free(&value);
 	free_hdb_entry_alias(&alias);
 
-	code = db->hdb__get(context, db, key, &value);
+	ret = db->hdb__get(context, db, key, &value);
 	krb5_data_free(&key);
-	if (code)
-	    return code;
-	code = hdb_value2entry(context, &value, &entry->entry);
-	if (code) {
+	if (ret)
+	    return ret;
+	ret = hdb_value2entry(context, &value, &entry->entry);
+	if (ret) {
 	    krb5_data_free(&value);
-	    return code;
+	    return ret;
 	}
     }
     krb5_data_free(&value);
     if (db->hdb_master_key_set && (flags & HDB_F_DECRYPT)) {
-	code = hdb_unseal_keys (context, db, &entry->entry);
-	if (code)
+#ifdef notnow
+	if ((flags & HDB_F_KVNO_SPECIFIED) == 0 &&
+	    (flags & HDB_F_CURRENT_KVNO) == 0) {
+
+	    /*
+	     * Decrypt all the old keys too, since we don't know which
+	     * the caller will need.
+	     */
+	    ret = hdb_unseal_keys_kvno(context, db, 0, &entry->entry);
+	    if (ret) {
+		hdb_free_entry(context, entry);
+		return ret;
+	    }
+	} else if ((flags & HDB_F_KVNO_SPECIFIED) != 0 &&
+	    kvno != entry->entry.kvno &&
+	    kvno < entry->entry.kvno &&
+	    kvno > 0) {
+
+	    /* Decrypt the keys we were asked for, if not the current ones */
+	    ret = hdb_unseal_keys_kvno(context, db, kvno, &entry->entry);
+	    if (ret) {
+		hdb_free_entry(context, entry);
+		return ret;
+	    }
+	}
+#endif
+
+	/* Always decrypt the current keys too */
+	ret = hdb_unseal_keys(context, db, &entry->entry);
+	if (ret) {
 	    hdb_free_entry(context, entry);
+	    return ret;
+	}
     }
-    return code;
+
+    return ret;
 }
 
 static krb5_error_code
diff --git a/crypto/heimdal/lib/hdb/ext.c b/crypto/heimdal/lib/hdb/ext.c
index d2a4373b9b38..5f7a19a55e04 100644
--- a/crypto/heimdal/lib/hdb/ext.c
+++ b/crypto/heimdal/lib/hdb/ext.c
@@ -432,3 +432,34 @@ hdb_entry_get_aliases(const hdb_entry *entry, const HDB_Ext_Aliases **a)
 
     return 0;
 }
+
+krb5_error_code
+hdb_set_last_modified_by(krb5_context context, hdb_entry *entry,
+                         krb5_principal modby, time_t modtime)
+{
+    krb5_error_code ret;
+    Event *old_ev;
+    Event *ev;
+
+    old_ev = entry->modified_by;
+
+    ev = calloc(1, sizeof (*ev));
+    if (!ev)
+        return ENOMEM;
+    if (modby)
+        ret = krb5_copy_principal(context, modby, &ev->principal);
+    else
+        ret = krb5_parse_name(context, "root/admin", &ev->principal);
+    if (ret) {
+        free(ev);
+        return ret;
+    }
+    ev->time = modtime;
+    if (!ev->time)
+        time(&ev->time);
+
+    entry->modified_by = ev;
+    if (old_ev)
+        free_Event(old_ev);
+    return 0;
+}
diff --git a/crypto/heimdal/lib/hdb/hdb-mitdb.c b/crypto/heimdal/lib/hdb/hdb-mitdb.c
index 02c575050fe2..1dfe7835cb4d 100644
--- a/crypto/heimdal/lib/hdb/hdb-mitdb.c
+++ b/crypto/heimdal/lib/hdb/hdb-mitdb.c
@@ -91,18 +91,28 @@ salt:
 
 #include "hdb_locl.h"
 
-#define KDB_V1_BASE_LENGTH 38
-
-#if HAVE_DB1
+static void
+attr_to_flags(unsigned attr, HDBFlags *flags)
+{
+    flags->postdate =		!(attr & KRB5_KDB_DISALLOW_POSTDATED);
+    flags->forwardable =	!(attr & KRB5_KDB_DISALLOW_FORWARDABLE);
+    flags->initial =	       !!(attr & KRB5_KDB_DISALLOW_TGT_BASED);
+    flags->renewable =		!(attr & KRB5_KDB_DISALLOW_RENEWABLE);
+    flags->proxiable =		!(attr & KRB5_KDB_DISALLOW_PROXIABLE);
+    /* DUP_SKEY */
+    flags->invalid =	       !!(attr & KRB5_KDB_DISALLOW_ALL_TIX);
+    flags->require_preauth =   !!(attr & KRB5_KDB_REQUIRES_PRE_AUTH);
+    flags->require_hwauth =    !!(attr & KRB5_KDB_REQUIRES_HW_AUTH);
+    flags->server =		!(attr & KRB5_KDB_DISALLOW_SVR);
+    flags->change_pw = 	       !!(attr & KRB5_KDB_PWCHANGE_SERVICE);
+    flags->client =	        1; /* XXX */
+}
 
-#if defined(HAVE_DB_185_H)
-#include <db_185.h>
-#elif defined(HAVE_DB_H)
-#include <db.h>
-#endif
+#define KDB_V1_BASE_LENGTH 38
 
 #define CHECK(x) do { if ((x)) goto out; } while(0)
 
+#ifdef HAVE_DB1
 static krb5_error_code
 mdb_principal2key(krb5_context context,
 		  krb5_const_principal principal,
@@ -118,6 +128,7 @@ mdb_principal2key(krb5_context context,
     key->length = strlen(str) + 1;
     return 0;
 }
+#endif /* HAVE_DB1 */
 
 #define KRB5_KDB_SALTTYPE_NORMAL	0
 #define KRB5_KDB_SALTTYPE_V4		1
@@ -197,13 +208,15 @@ fix_salt(krb5_context context, hdb_entry *ent, int key_num)
 }
 
 
-static krb5_error_code
-mdb_value2entry(krb5_context context, krb5_data *data, krb5_kvno kvno, hdb_entry *entry)
+krb5_error_code
+_hdb_mdb_value2entry(krb5_context context, krb5_data *data,
+                     krb5_kvno kvno, hdb_entry *entry)
 {
     krb5_error_code ret;
     krb5_storage *sp;
     uint32_t u32;
     uint16_t u16, num_keys, num_tl;
+    ssize_t sz;
     size_t i, j;
     char *p;
 
@@ -234,18 +247,7 @@ mdb_value2entry(krb5_context context, krb5_data *data, krb5_kvno kvno, hdb_entry
     if (u16 != KDB_V1_BASE_LENGTH) { ret = EINVAL; goto out; }
     /* 32: attributes */
     CHECK(ret = krb5_ret_uint32(sp, &u32));
-    entry->flags.postdate =	 !(u32 & KRB5_KDB_DISALLOW_POSTDATED);
-    entry->flags.forwardable =	 !(u32 & KRB5_KDB_DISALLOW_FORWARDABLE);
-    entry->flags.initial =	!!(u32 & KRB5_KDB_DISALLOW_TGT_BASED);
-    entry->flags.renewable =	 !(u32 & KRB5_KDB_DISALLOW_RENEWABLE);
-    entry->flags.proxiable =	 !(u32 & KRB5_KDB_DISALLOW_PROXIABLE);
-    /* DUP_SKEY */
-    entry->flags.invalid =	!!(u32 & KRB5_KDB_DISALLOW_ALL_TIX);
-    entry->flags.require_preauth =!!(u32 & KRB5_KDB_REQUIRES_PRE_AUTH);
-    entry->flags.require_hwauth =!!(u32 & KRB5_KDB_REQUIRES_HW_AUTH);
-    entry->flags.server =	 !(u32 & KRB5_KDB_DISALLOW_SVR);
-    entry->flags.change_pw = 	!!(u32 & KRB5_KDB_PWCHANGE_SERVICE);
-    entry->flags.client =	   1; /* XXX */
+    attr_to_flags(u32, &entry->flags);
 
     /* 32: max time */
     CHECK(ret = krb5_ret_uint32(sp, &u32));
@@ -296,7 +298,11 @@ mdb_value2entry(krb5_context context, krb5_data *data, krb5_kvno kvno, hdb_entry
 	    ret = ENOMEM;
 	    goto out;
 	}
-	krb5_storage_read(sp, p, u16);
+	sz = krb5_storage_read(sp, p, u16);
+        if (sz != u16) {
+            ret = EINVAL; /* XXX */
+            goto out;
+        }
 	p[u16] = '\0';
 	CHECK(ret = krb5_parse_name(context, p, &entry->principal));
 	free(p);
@@ -305,12 +311,53 @@ mdb_value2entry(krb5_context context, krb5_data *data, krb5_kvno kvno, hdb_entry
            16: tl data type
            16: tl data length
            length: length */
+#define mit_KRB5_TL_LAST_PWD_CHANGE     1
+#define mit_KRB5_TL_MOD_PRINC           2
     for (i = 0; i < num_tl; i++) {
+        int tl_type;
+        krb5_principal modby;
 	/* 16: TL data type */
 	CHECK(ret = krb5_ret_uint16(sp, &u16));
+        tl_type = u16;
 	/* 16: TL data length */
 	CHECK(ret = krb5_ret_uint16(sp, &u16));
-	krb5_storage_seek(sp, u16, SEEK_CUR);
+        /*
+         * For rollback to MIT purposes we really must understand some
+         * TL data!
+         *
+         * XXX Move all this to separate functions, one per-TL type.
+         */
+        switch (tl_type) {
+        case mit_KRB5_TL_LAST_PWD_CHANGE:
+            CHECK(ret = krb5_ret_uint32(sp, &u32));
+            CHECK(ret = hdb_entry_set_pw_change_time(context, entry, u32));
+            break;
+        case mit_KRB5_TL_MOD_PRINC:
+            if (u16 < 5) {
+                ret = EINVAL; /* XXX */
+                goto out;
+            }
+            CHECK(ret = krb5_ret_uint32(sp, &u32)); /* mod time */
+            p = malloc(u16 - 4 + 1);
+            if (!p) {
+                ret = ENOMEM;
+                goto out;
+            }
+            p[u16 - 4] = '\0';
+            sz = krb5_storage_read(sp, p, u16 - 4);
+            if (sz != u16 - 4) { 
+                ret = EINVAL; /* XXX */
+                goto out;
+            }
+            CHECK(ret = krb5_parse_name(context, p, &modby));
+            ret = hdb_set_last_modified_by(context, entry, modby, u32);
+            krb5_free_principal(context, modby);
+            free(p);
+            break;
+        default:
+            krb5_storage_seek(sp, u16, SEEK_CUR);
+            break;
+        }
     }
     /*
      * for num key data times
@@ -471,6 +518,14 @@ mdb_entry2value(krb5_context context, hdb_entry *entry, krb5_data *data)
 }
 #endif
 
+#if HAVE_DB1
+
+#if defined(HAVE_DB_185_H)
+#include <db_185.h>
+#elif defined(HAVE_DB_H)
+#include <db.h>
+#endif
+
 
 static krb5_error_code
 mdb_close(krb5_context context, HDB *db)
@@ -551,7 +606,7 @@ mdb_seq(krb5_context context, HDB *db,
     data.length = value.size;
     memset(entry, 0, sizeof(*entry));
 
-    if (mdb_value2entry(context, &data, 0, &entry->entry))
+    if (_hdb_mdb_value2entry(context, &data, 0, &entry->entry))
 	return mdb_seq(context, db, flags, entry, R_NEXT);
 
     if (db->hdb_master_key_set && (flags & HDB_F_DECRYPT)) {
@@ -684,24 +739,26 @@ mdb_fetch_kvno(krb5_context context, HDB *db, krb5_const_principal principal,
 	       unsigned flags, krb5_kvno kvno, hdb_entry_ex *entry)
 {
     krb5_data key, value;
-    krb5_error_code code;
+    krb5_error_code ret;
 
-    code = mdb_principal2key(context, principal, &key);
-    if (code)
-	return code;
-    code = db->hdb__get(context, db, key, &value);
+    ret = mdb_principal2key(context, principal, &key);
+    if (ret)
+	return ret;
+    ret = db->hdb__get(context, db, key, &value);
     krb5_data_free(&key);
-    if(code)
-	return code;
-    code = mdb_value2entry(context, &value, kvno, &entry->entry);
+    if(ret)
+	return ret;
+    ret = _hdb_mdb_value2entry(context, &value, kvno, &entry->entry);
     krb5_data_free(&value);
-    if (code)
-	return code;
+    if (ret)
+	return ret;
 
     if (db->hdb_master_key_set && (flags & HDB_F_DECRYPT)) {
-	code = hdb_unseal_keys (context, db, &entry->entry);
-	if (code)
+	ret = hdb_unseal_keys (context, db, &entry->entry);
+	if (ret) {
 	    hdb_free_entry(context, entry);
+            return ret;
+        }
     }
 
     return 0;
@@ -710,8 +767,48 @@ mdb_fetch_kvno(krb5_context context, HDB *db, krb5_const_principal principal,
 static krb5_error_code
 mdb_store(krb5_context context, HDB *db, unsigned flags, hdb_entry_ex *entry)
 {
-    krb5_set_error_message(context, EINVAL, "can't set principal in mdb");
-    return EINVAL;
+    krb5_error_code ret;
+    krb5_storage *sp = NULL;
+    krb5_storage *spent = NULL;
+    krb5_data line = { 0, 0 };
+    krb5_data kdb_ent = { 0, 0 };
+    krb5_data key = { 0, 0 };
+    ssize_t sz;
+
+    sp = krb5_storage_emem();
+    if (!sp) return ENOMEM;
+    ret = _hdb_set_master_key_usage(context, db, 0); /* MIT KDB uses KU 0 */
+    ret = hdb_seal_keys(context, db, &entry->entry);
+    if (ret) return ret;
+    ret = entry2mit_string_int(context, sp, &entry->entry);
+    if (ret) goto out;
+    sz = krb5_storage_write(sp, "\n", 2); /* NUL-terminate */
+    ret = ENOMEM;
+    if (sz == -1) goto out;
+    ret = krb5_storage_to_data(sp, &line);
+    if (ret) goto out;
+
+    ret = ENOMEM;
+    spent = krb5_storage_emem();
+    if (!spent) goto out;
+    ret = _hdb_mit_dump2mitdb_entry(context, line.data, spent);
+    if (ret) goto out;
+    ret = krb5_storage_to_data(spent, &kdb_ent);
+    if (ret) goto out;
+    ret = mdb_principal2key(context, entry->entry.principal, &key);
+    if (ret) goto out;
+    ret = mdb__put(context, db, 1, key, kdb_ent);
+
+out:
+    if (sp)
+        krb5_storage_free(sp);
+    if (spent)
+        krb5_storage_free(spent);
+    krb5_data_free(&line);
+    krb5_data_free(&kdb_ent);
+    krb5_data_free(&key);
+
+    return ret;
 }
 
 static krb5_error_code
@@ -729,25 +826,31 @@ static krb5_error_code
 mdb_open(krb5_context context, HDB *db, int flags, mode_t mode)
 {
     char *fn;
+    char *actual_fn;
     krb5_error_code ret;
+    struct stat st;
 
     asprintf(&fn, "%s.db", db->hdb_name);
     if (fn == NULL) {
 	krb5_set_error_message(context, ENOMEM, "malloc: out of memory");
 	return ENOMEM;
     }
-    db->hdb_db = dbopen(fn, flags, mode, DB_BTREE, NULL);
-    free(fn);
 
+     if (stat(fn, &st) == 0)
+         actual_fn = fn;
+     else
+         actual_fn = db->hdb_name;
+     db->hdb_db = dbopen(actual_fn, flags, mode, DB_BTREE, NULL);
     if (db->hdb_db == NULL) {
 	switch (errno) {
 #ifdef EFTYPE
 	case EFTYPE:
 #endif
 	case EINVAL:
-	    db->hdb_db = dbopen(fn, flags, mode, DB_BTREE, NULL);
+	    db->hdb_db = dbopen(actual_fn, flags, mode, DB_BTREE, NULL);
 	}
     }
+    free(fn);
 
     /* try to open without .db extension */
     if(db->hdb_db == NULL && errno == ENOENT)
@@ -758,11 +861,16 @@ mdb_open(krb5_context context, HDB *db, int flags, mode_t mode)
 			      db->hdb_name, strerror(ret));
 	return ret;
     }
-    if((flags & O_ACCMODE) == O_RDONLY)
-	ret = hdb_check_db_format(context, db);
-    else
+#if 0
+    /*
+     * Don't do this -- MIT won't be able to handle the
+     * HDB_DB_FORMAT_ENTRY key.
+     */
+    if ((flags & O_ACCMODE) != O_RDONLY)
 	ret = hdb_init_db(context, db);
-    if(ret == HDB_ERR_NOENTRY) {
+#endif
+    ret = hdb_check_db_format(context, db);
+    if (ret == HDB_ERR_NOENTRY) {
 	krb5_clear_error_message(context);
 	return 0;
     }
@@ -815,3 +923,280 @@ hdb_mdb_create(krb5_context context, HDB **db,
 }
 
 #endif /* HAVE_DB1 */
+
+/*
+can have any number of princ stanzas.
+format is as follows (only \n indicates newlines)
+princ\t%d\t (%d is KRB5_KDB_V1_BASE_LENGTH, always 38)
+%d\t (strlen of principal e.g. shadow/foo@ANDREW.CMU.EDU)
+%d\t (number of tl_data)
+%d\t (number of key data, e.g. how many keys for this user)
+%d\t (extra data length)
+%s\t (principal name)
+%d\t (attributes)
+%d\t (max lifetime, seconds)
+%d\t (max renewable life, seconds)
+%d\t (expiration, seconds since epoch or 2145830400 for never)
+%d\t (password expiration, seconds, 0 for never)
+%d\t (last successful auth, seconds since epoch)
+%d\t (last failed auth, per above)
+%d\t (failed auth count)
+foreach tl_data 0 to number of tl_data - 1 as above
+  %d\t%d\t (data type, data length)
+  foreach tl_data 0 to length-1
+    %02x (tl data contents[element n])
+  except if tl_data length is 0
+    %d (always -1)
+  \t
+foreach key 0 to number of keys - 1 as above
+  %d\t%d\t (key data version, kvno)
+  foreach version 0 to key data version - 1 (a key or a salt)
+    %d\t%d\t(data type for this key, data length for this key)
+    foreach key data length 0 to length-1
+      %02x (key data contents[element n])
+    except if key_data length is 0
+      %d (always -1)
+    \t
+foreach extra data length 0 to length - 1
+  %02x (extra data part)
+unless no extra data
+  %d (always -1)
+;\n
+
+*/
+
+static char *
+nexttoken(char **p)
+{
+    char *q;
+    do {
+	q = strsep(p, " \t");
+    } while(q && *q == '\0');
+    return q;
+}
+
+static size_t
+getdata(char **p, unsigned char *buf, size_t len)
+{
+    size_t i;
+    int v;
+    char *q = nexttoken(p);
+    i = 0;
+    while(*q && i < len) {
+	if(sscanf(q, "%02x", &v) != 1)
+	    break;
+	buf[i++] = v;
+	q += 2;
+    }
+    return i;
+}
+
+static int
+getint(char **p)
+{
+    int val;
+    char *q = nexttoken(p);
+    sscanf(q, "%d", &val);
+    return val;
+}
+
+static unsigned int
+getuint(char **p)
+{
+    int val;
+    char *q = nexttoken(p);
+    sscanf(q, "%u", &val);
+    return val;
+}
+
+#define KRB5_KDB_SALTTYPE_NORMAL	0
+#define KRB5_KDB_SALTTYPE_V4		1
+#define KRB5_KDB_SALTTYPE_NOREALM	2
+#define KRB5_KDB_SALTTYPE_ONLYREALM	3
+#define KRB5_KDB_SALTTYPE_SPECIAL	4
+#define KRB5_KDB_SALTTYPE_AFS3		5
+
+#define CHECK_UINT(num)                            \
+        if ((num) < 0 || (num) > INT_MAX) return EINVAL
+#define CHECK_UINT16(num)                          \
+        if ((num) < 0 || (num) > 1<<15) return EINVAL
+#define CHECK_NUM(num, maxv)                     \
+        if ((num) > (maxv)) return EINVAL
+
+/*
+ * This utility function converts an MIT dump entry to an MIT on-disk
+ * encoded entry, which can then be decoded with _hdb_mdb_value2entry().
+ * This allows us to have a single decoding function (_hdb_mdb_value2entry),
+ * which makes the code cleaner (less code duplication), if a bit less
+ * efficient.  It also will allow us to have a function to dump an HDB
+ * entry in MIT format so we can dump HDB into MIT format for rollback
+ * purposes.  And that will allow us to write to MIT KDBs, again
+ * somewhat inefficiently, also for migration/rollback purposes.
+ */
+int
+_hdb_mit_dump2mitdb_entry(krb5_context context, char *line, krb5_storage *sp)
+{
+    krb5_error_code ret = EINVAL;
+    char *p = line, *q;
+    char *princ;
+    ssize_t sz;
+    size_t i;
+    size_t princ_len;
+    unsigned int num_tl_data;
+    size_t num_key_data;
+    unsigned int attributes;
+    int tmp;
+
+    krb5_storage_set_byteorder(sp, KRB5_STORAGE_BYTEORDER_LE);
+
+    q = nexttoken(&p);
+    if (strcmp(q, "kdb5_util") == 0 || strcmp(q, "policy") == 0 ||
+        strcmp(q, "princ") != 0) {
+        return -1;
+    }
+    if (getint(&p) != 38)
+        return EINVAL;
+#define KDB_V1_BASE_LENGTH 38
+    ret = krb5_store_int16(sp, KDB_V1_BASE_LENGTH);
+    if (ret) return ret;
+
+    nexttoken(&p); /* length of principal */
+    num_tl_data = getuint(&p); /* number of tl-data */
+    num_key_data = getuint(&p); /* number of key-data */
+    getint(&p);  /* length of extra data */
+    princ = nexttoken(&p); /* principal name */
+
+    attributes = getuint(&p); /* attributes */
+    ret = krb5_store_uint32(sp, attributes);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* max life */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* max renewable life */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* expiration */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* pw expiration */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* last auth */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* last failed auth */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    tmp = getint(&p); /* fail auth count */
+    CHECK_UINT(tmp);
+    ret = krb5_store_uint32(sp, tmp);
+    if (ret) return ret;
+
+    /* add TL data count */
+    CHECK_NUM(num_tl_data, 1023);
+    ret = krb5_store_uint16(sp, num_tl_data);
+    if (ret) return ret;
+
+    /* add key count */
+    CHECK_NUM(num_key_data, 1023);
+    ret = krb5_store_uint16(sp, num_key_data);
+    if (ret) return ret;
+
+    /* add principal unparsed name length and unparsed name */
+    princ_len = strlen(princ);
+    if (princ_len > (1<<15) - 1) return EINVAL;
+    princ_len++; /* must count and write the NUL in the on-disk encoding */
+    ret = krb5_store_uint16(sp, princ_len);
+    if (ret) return ret;
+    sz = krb5_storage_write(sp, princ, princ_len);
+    if (sz == -1) return ENOMEM;
+
+    /* scan and write TL data */
+    for (i = 0; i < num_tl_data; i++) {
+        int tl_type, tl_length;
+        unsigned char *buf;
+
+        tl_type = getint(&p); /* data type */
+        tl_length = getint(&p); /* data length */
+
+        CHECK_UINT16(tl_type);
+        ret = krb5_store_uint16(sp, tl_type);
+        if (ret) return ret;
+        CHECK_UINT16(tl_length);
+        ret = krb5_store_uint16(sp, tl_length);
+        if (ret) return ret;
+
+        if (tl_length) {
+            buf = malloc(tl_length);
+            if (!buf) return ENOMEM;
+            if (getdata(&p, buf, tl_length) != tl_length) return EINVAL;
+            sz = krb5_storage_write(sp, buf, tl_length);
+            free(buf);
+            if (sz == -1) return ENOMEM;
+        } else {
+            if (strcmp(nexttoken(&p), "-1") != 0) return EINVAL;
+        }
+    }
+
+    for (i = 0; i < num_key_data; i++) {
+        unsigned char *buf;
+        int key_versions;
+        int kvno;
+        int keytype;
+        int keylen;
+        size_t k;
+
+        key_versions = getint(&p); /* key data version */
+        CHECK_UINT16(key_versions);
+        ret = krb5_store_int16(sp, key_versions);
+        if (ret) return ret;
+
+        kvno = getint(&p);
+        CHECK_UINT16(kvno);
+        ret = krb5_store_int16(sp, kvno);
+        if (ret) return ret;
+
+        for (k = 0; k < key_versions; k++) {
+            keytype = getint(&p);
+            CHECK_UINT16(keytype);
+            ret = krb5_store_int16(sp, keytype);
+            if (ret) return ret;
+
+            keylen = getint(&p);
+            CHECK_UINT16(keylen);
+            ret = krb5_store_int16(sp, keylen);
+            if (ret) return ret;
+
+            if (keylen) {
+                buf = malloc(keylen);
+                if (!buf) return ENOMEM;
+                if (getdata(&p, buf, keylen) != keylen) return EINVAL;
+                sz = krb5_storage_write(sp, buf, keylen);
+                free(buf);
+                if (sz == -1) return ENOMEM;
+            } else {
+                if (strcmp(nexttoken(&p), "-1") != 0) return EINVAL;
+            }
+        }
+    }
+    /*
+     * The rest is "extra data", but there's never any and we wouldn't
+     * know what to do with it.
+     */
+    /* nexttoken(&p); */
+    return 0;
+}
+
diff --git a/crypto/heimdal/lib/hdb/hdb-protos.h b/crypto/heimdal/lib/hdb/hdb-protos.h
index 44a1bddc7625..2b692855c405 100644
--- a/crypto/heimdal/lib/hdb/hdb-protos.h
+++ b/crypto/heimdal/lib/hdb/hdb-protos.h
@@ -9,6 +9,17 @@ extern "C" {
 #endif
 
 krb5_error_code
+entry2mit_string_int (
+	krb5_context /*context*/,
+	krb5_storage */*sp*/,
+	hdb_entry */*ent*/);
+
+krb5_error_code
+hdb_add_current_keys_to_history (
+	krb5_context /*context*/,
+	hdb_entry */*entry*/);
+
+krb5_error_code
 hdb_add_master_key (
 	krb5_context /*context*/,
 	krb5_keyblock */*key*/,
@@ -347,6 +358,13 @@ hdb_seal_keys_mkey (
 	hdb_master_key /*mkey*/);
 
 krb5_error_code
+hdb_set_last_modified_by (
+	krb5_context /*context*/,
+	hdb_entry */*entry*/,
+	krb5_principal /*modby*/,
+	time_t /*modtime*/);
+
+krb5_error_code
 hdb_set_master_key (
 	krb5_context /*context*/,
 	HDB */*db*/,
@@ -386,6 +404,13 @@ hdb_unseal_keys (
 	hdb_entry */*ent*/);
 
 krb5_error_code
+hdb_unseal_keys_kvno (
+	krb5_context /*context*/,
+	HDB */*db*/,
+	krb5_kvno /*kvno*/,
+	hdb_entry */*ent*/);
+
+krb5_error_code
 hdb_unseal_keys_mkey (
 	krb5_context /*context*/,
 	hdb_entry */*ent*/,
diff --git a/crypto/heimdal/lib/hdb/hdb.asn1 b/crypto/heimdal/lib/hdb/hdb.asn1
index a72851c9f201..d24737fbf6e8 100644
--- a/crypto/heimdal/lib/hdb/hdb.asn1
+++ b/crypto/heimdal/lib/hdb/hdb.asn1
@@ -87,6 +87,14 @@ HDB-Ext-Aliases ::= SEQUENCE {
 	aliases[1]		SEQUENCE OF Principal -- all names, inc primary
 }
 
+hdb_keyset ::= SEQUENCE {
+	kvno[0]		INTEGER (0..4294967295),
+	replace-time[1]	KerberosTime,	-- time this key was replaced
+	keys[2]		SEQUENCE OF Key
+}
+
+HDB-Ext-KeySet ::= SEQUENCE OF hdb_keyset
+
 
 HDB-extension ::= SEQUENCE {
         mandatory[0]    BOOLEAN,        -- kdc MUST understand this extension,
@@ -102,6 +110,7 @@ HDB-extension ::= SEQUENCE {
 		aliases[6]			HDB-Ext-Aliases,
 		last-pw-change[7]		KerberosTime,
 	        pkinit-cert[8]  		HDB-Ext-PKINIT-cert,
+	        hist-keys[9]			HDB-Ext-KeySet,
 		...
 	},
 	...
@@ -109,11 +118,6 @@ HDB-extension ::= SEQUENCE {
 
 HDB-extensions ::= SEQUENCE OF HDB-extension
 
-hdb_keyset ::= SEQUENCE {
-	kvno[1]		INTEGER (0..4294967295),
-	keys[0]		SEQUENCE OF Key
-}
-
 hdb_entry ::= SEQUENCE {
 	principal[0]	Principal  OPTIONAL, -- this is optional only 
 					     -- for compatibility with libkrb5
diff --git a/crypto/heimdal/lib/hdb/hdb.c b/crypto/heimdal/lib/hdb/hdb.c
index ca05cc4a1785..aff576a30d37 100644
--- a/crypto/heimdal/lib/hdb/hdb.c
+++ b/crypto/heimdal/lib/hdb/hdb.c
@@ -168,13 +168,14 @@ hdb_unlock(int fd)
 void
 hdb_free_entry(krb5_context context, hdb_entry_ex *ent)
 {
-    size_t i;
+    Key *k;
+    int i;
 
     if (ent->free_entry)
 	(*ent->free_entry)(context, ent);
 
-    for(i = 0; i < ent->entry.keys.len; ++i) {
-	Key *k = &ent->entry.keys.val[i];
+    for(i = 0; i < ent->entry.keys.len; i++) {
+	k = &ent->entry.keys.val[i];
 
 	memset (k->key.keyvalue.data, 0, k->key.keyvalue.length);
     }
diff --git a/crypto/heimdal/lib/hdb/hdb.h b/crypto/heimdal/lib/hdb/hdb.h
index a1692ce82ca2..4c4c2c2b1a5c 100644
--- a/crypto/heimdal/lib/hdb/hdb.h
+++ b/crypto/heimdal/lib/hdb/hdb.h
@@ -99,7 +99,7 @@ typedef struct hdb_entry_ex {
  * query the backend database when talking about principals.
  */
 
-typedef struct HDB{
+typedef struct HDB {
     void *hdb_db;
     void *hdb_dbc; /** don't use, only for DB3 */
     char *hdb_name;
@@ -256,6 +256,8 @@ typedef struct HDB{
      * Check if s4u2self is allowed from this client to this server
      */
     krb5_error_code (*hdb_check_s4u2self)(krb5_context, struct HDB *, hdb_entry_ex *, krb5_const_principal);
+    int hdb_mit_key_set;
+    hdb_master_key hdb_mit_key;
 }HDB;
 
 #define HDB_INTERFACE_VERSION	7
@@ -266,6 +268,17 @@ struct hdb_so_method {
     krb5_error_code (*create)(krb5_context, HDB **, const char *filename);
 };
 
+/* dump entry format, for hdb_print_entry() */
+typedef enum hdb_dump_format {
+    HDB_DUMP_HEIMDAL = 0,
+    HDB_DUMP_MIT = 1,
+} hdb_dump_format_t;
+
+struct hdb_print_entry_arg {
+    FILE *out;
+    hdb_dump_format_t fmt;
+};
+
 typedef krb5_error_code (*hdb_foreach_func_t)(krb5_context, HDB*,
 					      hdb_entry_ex*, void*);
 extern krb5_kt_ops hdb_kt_ops;
diff --git a/crypto/heimdal/lib/hdb/hdb_locl.h b/crypto/heimdal/lib/hdb/hdb_locl.h
index e896b5802575..5aad504589df 100644
--- a/crypto/heimdal/lib/hdb/hdb_locl.h
+++ b/crypto/heimdal/lib/hdb/hdb_locl.h
@@ -38,6 +38,8 @@
 
 #include <config.h>
 
+#include <heimbase.h>
+
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
@@ -67,4 +69,9 @@
 #define HDB_DEFAULT_DB HDB_DB_DIR "/heimdal"
 #define HDB_DB_FORMAT_ENTRY "hdb/db-format"
 
+/* Test for strong key etypes accepted by MIT's KDC. */
+#define	mit_strong_etype(t)				\
+	    ((t) == ETYPE_AES128_CTS_HMAC_SHA1_96 ||	\
+	    (t) == ETYPE_AES256_CTS_HMAC_SHA1_96)
+
 #endif /* __HDB_LOCL_H__ */
diff --git a/crypto/heimdal/lib/hdb/keys.c b/crypto/heimdal/lib/hdb/keys.c
index 3d0b9d7c1b31..9c0af5c47f23 100644
--- a/crypto/heimdal/lib/hdb/keys.c
+++ b/crypto/heimdal/lib/hdb/keys.c
@@ -39,7 +39,7 @@
  */
 
 void
-hdb_free_keys (krb5_context context, int len, Key *keys)
+hdb_free_keys(krb5_context context, int len, Key *keys)
 {
     int i;
 
@@ -56,6 +56,19 @@ hdb_free_keys (krb5_context context, int len, Key *keys)
     free (keys);
 }
 
+void
+hdb_free_keysets(krb5_context context, int len, hdb_keyset *keysets)
+{
+    int i;
+
+    for (i = 0; i < len; i++) {
+	hdb_free_keys(context, keysets[i].keys.len, keysets[i].keys.val);
+	keysets[i].keys.val = NULL;
+	keysets[i].keys.len = 0;
+    }
+    free (keysets);
+}
+
 /*
  * for each entry in `default_keys' try to parse it as a sequence
  * of etype:salttype:salt, syntax of this if something like:
@@ -196,6 +209,60 @@ parse_key_set(krb5_context context, const char *key,
     return 0;
 }
 
+
+krb5_error_code
+hdb_add_current_keys_to_history(krb5_context context, hdb_entry *entry)
+{
+    krb5_error_code ret;
+    HDB_extension *ext;
+    HDB_Ext_KeySet *hist_keys;
+    hdb_keyset *tmp_keysets;
+    int add = 0;
+
+    ext = hdb_find_extension(entry, choice_HDB_extension_data_hist_keys);
+    if (ext != NULL) {
+	hist_keys = &ext->data.u.hist_keys;
+	tmp_keysets = realloc(hist_keys->val,
+			      sizeof (*hist_keys->val) * (hist_keys->len + 1));
+	if (tmp_keysets == NULL)
+	    return ENOMEM;
+	hist_keys->val = tmp_keysets;
+	memmove(&hist_keys->val[1], hist_keys->val,
+		sizeof (*hist_keys->val) * hist_keys->len++);
+    } else {
+	add = 1;
+	ext = calloc(1, sizeof (*ext));
+	if (ext == NULL)
+	    return ENOMEM;
+	ext->data.element = choice_HDB_extension_data_hist_keys;
+	hist_keys = &ext->data.u.hist_keys;
+	hist_keys->val = calloc(1, sizeof (*hist_keys->val));
+	if (hist_keys->val == NULL) {
+	    free(hist_keys);
+	    return ENOMEM;
+	}
+	hist_keys->len = 1;
+    }
+
+    hist_keys->val[0].keys.val = entry->keys.val;
+    hist_keys->val[0].keys.len = entry->keys.len;
+    hist_keys->val[0].kvno = entry->kvno;
+    hist_keys->val[0].replace_time = time(NULL);
+
+    if (add) {
+	ret = hdb_replace_extension(context, entry, ext);
+	if (ret) {
+	    free_HDB_extension(ext);
+	    return ret;
+	}
+    }
+
+    /* hdb_replace_extension() copies ext, so we have to free it */
+    free_HDB_extension(ext);
+    return 0;
+}
+
+
 static krb5_error_code
 add_enctype_to_key_set(Key **key_set, size_t *nkeyset,
 		       krb5_enctype enctype, krb5_salt *salt)
diff --git a/crypto/heimdal/lib/hdb/mkey.c b/crypto/heimdal/lib/hdb/mkey.c
index 9eb98fca32c0..78a9e51a132c 100644
--- a/crypto/heimdal/lib/hdb/mkey.c
+++ b/crypto/heimdal/lib/hdb/mkey.c
@@ -32,6 +32,7 @@
  */
 
 #include "hdb_locl.h"
+#include <assert.h>
 #ifndef O_BINARY
 #define O_BINARY 0
 #endif
@@ -40,6 +41,7 @@ struct hdb_master_key_data {
     krb5_keytab_entry keytab;
     krb5_crypto crypto;
     struct hdb_master_key_data *next;
+    unsigned int key_usage;
 };
 
 void
@@ -68,6 +70,7 @@ hdb_process_master_key(krb5_context context,
 	krb5_set_error_message(context, ENOMEM, "malloc: out of memory");
 	return ENOMEM;
     }
+    (*mkey)->key_usage = HDB_KU_MKEY;
     (*mkey)->keytab.vno = kvno;
     ret = krb5_parse_name(context, "K/M", &(*mkey)->keytab.principal);
     if(ret)
@@ -362,6 +365,15 @@ hdb_write_master_key(krb5_context context, const char *filename,
     return ret;
 }
 
+krb5_error_code
+_hdb_set_master_key_usage(krb5_context context, HDB *db, unsigned int key_usage)
+{
+    if (db->hdb_master_key_set == 0)
+	return HDB_ERR_NO_MKEY;
+    db->hdb_master_key->key_usage = key_usage;
+    return 0;
+}
+
 hdb_master_key
 _hdb_find_master_key(uint32_t *mkvno, hdb_master_key mkey)
 {
@@ -403,15 +415,20 @@ _hdb_mkey_encrypt(krb5_context context, hdb_master_key key,
 			ptr, size, res);
 }
 
-krb5_error_code
-hdb_unseal_key_mkey(krb5_context context, Key *k, hdb_master_key mkey)
+/*
+ * Unseal and optionally reseal the key in the MIT KDC master key.
+ * If mit_key != NULL, the key is sealed using this key.
+ */
+static krb5_error_code
+_hdb_reseal_key_mkey(krb5_context context, Key *k, hdb_master_key mkey,
+    hdb_master_key mit_key)
 {
 
     krb5_error_code ret;
-    krb5_data res;
+    krb5_data mitres, res;
     size_t keysize;
 
-    hdb_master_key key;
+    hdb_master_key key, mitkey;
 
     if(k->mkvno == NULL)
 	return 0;
@@ -428,9 +445,9 @@ hdb_unseal_key_mkey(krb5_context context, Key *k, hdb_master_key mkey)
     if(ret == KRB5KRB_AP_ERR_BAD_INTEGRITY) {
 	/* try to decrypt with MIT key usage */
 	ret = _hdb_mkey_decrypt(context, key, 0,
-				k->key.keyvalue.data,
-				k->key.keyvalue.length,
-				&res);
+			    k->key.keyvalue.data,
+			    k->key.keyvalue.length,
+			    &res);
     }
     if (ret)
 	return ret;
@@ -446,25 +463,81 @@ hdb_unseal_key_mkey(krb5_context context, Key *k, hdb_master_key mkey)
 	return KRB5_BAD_KEYSIZE;
     }
 
-    memset(k->key.keyvalue.data, 0, k->key.keyvalue.length);
-    free(k->key.keyvalue.data);
-    k->key.keyvalue = res;
-    k->key.keyvalue.length = keysize;
-    free(k->mkvno);
-    k->mkvno = NULL;
+    /* For mit_key != NULL, re-encrypt the key using the mitkey. */
+    if (mit_key != NULL) {
+	mitkey = _hdb_find_master_key(NULL, mit_key);
+	if (mitkey == NULL) {
+	    krb5_data_free(&res);
+	    return HDB_ERR_NO_MKEY;
+	}
+
+	ret = _hdb_mkey_encrypt(context, mitkey, 0,
+			    res.data,
+			    keysize,
+			    &mitres);
+	krb5_data_free(&res);
+	if (ret)
+	    return ret;
+    }
+
+    krb5_data_free(&k->key.keyvalue);
+    if (mit_key == NULL) {
+	k->key.keyvalue = res;
+	k->key.keyvalue.length = keysize;
+	free(k->mkvno);
+	k->mkvno = NULL;
+    } else {
+	k->key.keyvalue = mitres;
+	*k->mkvno = mitkey->keytab.vno;
+    }
 
     return 0;
 }
 
 krb5_error_code
-hdb_unseal_keys_mkey(krb5_context context, hdb_entry *ent, hdb_master_key mkey)
+hdb_unseal_key_mkey(krb5_context context, Key *k, hdb_master_key mkey)
+{
+
+    krb5_error_code ret;
+
+    ret = _hdb_reseal_key_mkey(context, k, mkey, NULL);
+    return ret;
+}
+
+static krb5_error_code
+_hdb_unseal_keys_mkey(krb5_context context, hdb_entry *ent, hdb_master_key mkey,
+    hdb_master_key mitkey)
 {
+    krb5_error_code ret;
     size_t i;
+    int got_one = 0;
 
     for(i = 0; i < ent->keys.len; i++){
-	krb5_error_code ret;
+	if (mitkey == NULL || mit_strong_etype(ent->keys.val[i].key.keytype)) {
+	    ret = _hdb_reseal_key_mkey(context, &ent->keys.val[i], mkey,
+		mitkey);
+	    if (ret)
+		return ret;
+	    got_one = 1;
+	}
+    }
 
-	ret = hdb_unseal_key_mkey(context, &ent->keys.val[i], mkey);
+    /*
+     * If none of the keys were string enough, create a strong key,
+     * but one that is not encrypted in the MIT master key.  As such,
+     * it will require a "change_password" once in the MIT KDC to
+     * make it work.
+     */
+    if (got_one == 0 && mitkey != NULL && ent->keys.len > 0) {
+	krb5_keyblock key;
+	krb5_salt salt;
+
+	krb5_free_keyblock_contents(context, &ent->keys.val[0].key);
+	salt.salttype = KRB5_PW_SALT;
+	salt.saltvalue.data = NULL;
+	salt.saltvalue.length = 0;
+	ret = krb5_string_to_key_salt(context, ETYPE_AES256_CTS_HMAC_SHA1_96,
+	    "XXXX", salt, &ent->keys.val[0].key);
 	if (ret)
 	    return ret;
     }
@@ -472,19 +545,114 @@ hdb_unseal_keys_mkey(krb5_context context, hdb_entry *ent, hdb_master_key mkey)
 }
 
 krb5_error_code
+hdb_unseal_keys_mkey(krb5_context context, hdb_entry *ent, hdb_master_key mkey)
+{
+    krb5_error_code ret;
+
+    ret = _hdb_unseal_keys_mkey(context, ent, mkey, NULL);
+    return ret;
+}
+
+krb5_error_code
 hdb_unseal_keys(krb5_context context, HDB *db, hdb_entry *ent)
 {
     if (db->hdb_master_key_set == 0)
 	return 0;
-    return hdb_unseal_keys_mkey(context, ent, db->hdb_master_key);
+    if (db->hdb_mit_key_set != 0)
+	return _hdb_unseal_keys_mkey(context, ent, db->hdb_master_key,
+	    db->hdb_mit_key);
+    else
+	return _hdb_unseal_keys_mkey(context, ent, db->hdb_master_key,
+	    NULL);
+}
+
+#ifdef notnow
+krb5_error_code
+hdb_unseal_keys_kvno(krb5_context context, HDB *db, krb5_kvno kvno,
+		     hdb_entry *ent)
+{
+    krb5_error_code ret = KRB5KRB_AP_ERR_NOKEY;	/* XXX need a better code? */
+    HDB_extension *tmp;
+    HDB_Ext_KeySet *hist_keys;
+    hdb_keyset *tmp_keys;
+    Key *tmp_val;
+    unsigned int tmp_len;
+    krb5_kvno tmp_kvno;
+    int i, k;
+
+    assert(kvno == 0 || kvno < ent->kvno);
+
+    tmp = hdb_find_extension(ent, choice_HDB_extension_data_hist_keys);
+    if (tmp == NULL)
+	return ret;
+
+    tmp_len = ent->keys.len;
+    tmp_val = ent->keys.val;
+    tmp_kvno = ent->kvno;
+
+    hist_keys = &tmp->data.u.hist_keys;
+
+    for (i = hist_keys->len - 1; i >= 0; i++) {
+	if (kvno != 0 && hist_keys->val[i].kvno != kvno)
+	    continue;
+	for (k = 0; k < hist_keys->val[i].keys.len; k++) {
+	    ret = _hdb_reseal_key_mkey(context,
+				      &hist_keys->val[i].keys.val[k],
+				      db->hdb_master_key, NULL);
+	    if (ret)
+		return (ret);
+	}
+
+	if (kvno == 0)
+	    continue;
+
+	/*
+	 * NOTE: What follows is a bit of an ugly hack.
+	 *
+	 * This is the keyset we're being asked for, so we add the
+	 * current keyset to the history, leave the one we were asked
+	 * for in the history, and pretend the one we were asked for is
+	 * also the current keyset.
+	 *
+	 * This is a bit of a defensive hack in case an entry fetched
+	 * this way ever gets modified then stored: if the keyset is not
+	 * changed we can detect this and put things back, else we won't
+	 * drop any keysets from history by accident.
+	 *
+	 * Note too that we only ever get called with a non-zero kvno
+	 * either in the KDC or in cases where we aren't changing the
+	 * HDB entry anyways, which is why this is just a defensive
+	 * hack.  We also don't fetch specific kvnos in the dump case,
+	 * so there's no danger that we'll dump this entry and load it
+	 * again, repeatedly causing the history to grow boundelessly.
+	 */
+	tmp_keys = realloc(hist_keys->val,
+		      sizeof (*hist_keys->val) * (hist_keys->len + 1));
+	if (tmp_keys == NULL)
+	    return ENOMEM;
+
+	memmove(&tmp_keys[1], tmp_keys,
+		sizeof (*hist_keys->val) * hist_keys->len++);
+	tmp_keys[0].keys.len = ent->keys.len;
+	tmp_keys[0].keys.val = ent->keys.val;
+	tmp_keys[0].kvno = ent->kvno;
+	tmp_keys[0].replace_time = time(NULL);
+	i++;
+	ent->keys.len = hist_keys->val[i].keys.len;
+	ent->keys.val = hist_keys->val[i].keys.val;
+	ent->kvno = kvno;
+    }
+
+    return (ret);
 }
+#endif
 
 krb5_error_code
 hdb_unseal_key(krb5_context context, HDB *db, Key *k)
 {
     if (db->hdb_master_key_set == 0)
 	return 0;
-    return hdb_unseal_key_mkey(context, k, db->hdb_master_key);
+    return _hdb_reseal_key_mkey(context, k, db->hdb_master_key, NULL);
 }
 
 krb5_error_code
@@ -556,9 +724,9 @@ hdb_seal_key(krb5_context context, HDB *db, Key *k)
 }
 
 krb5_error_code
-hdb_set_master_key (krb5_context context,
-		    HDB *db,
-		    krb5_keyblock *key)
+hdb_set_master_key(krb5_context context,
+		   HDB *db,
+		   krb5_keyblock *key)
 {
     krb5_error_code ret;
     hdb_master_key mkey;
@@ -571,6 +739,7 @@ hdb_set_master_key (krb5_context context,
     des_set_random_generator_seed(key.keyvalue.data);
 #endif
     db->hdb_master_key_set = 1;
+    db->hdb_master_key->key_usage = HDB_KU_MKEY;
     return 0;
 }
 
diff --git a/crypto/heimdal/lib/hdb/print.c b/crypto/heimdal/lib/hdb/print.c
index 697d32d2909c..d5359f538056 100644
--- a/crypto/heimdal/lib/hdb/print.c
+++ b/crypto/heimdal/lib/hdb/print.c
@@ -57,44 +57,57 @@
   generation number
   */
 
-static krb5_error_code
+/*
+ * These utility functions return the number of bytes written or -1, and
+ * they set an error in the context.
+ */
+static ssize_t
 append_string(krb5_context context, krb5_storage *sp, const char *fmt, ...)
 {
-    krb5_error_code ret;
+    ssize_t sz;
     char *s;
+    int rc;
     va_list ap;
     va_start(ap, fmt);
-    vasprintf(&s, fmt, ap);
+    rc = vasprintf(&s, fmt, ap);
     va_end(ap);
-    if(s == NULL) {
+    if(rc < 0) {
 	krb5_set_error_message(context, ENOMEM, "malloc: out of memory");
-	return ENOMEM;
+	return -1;
     }
-    ret = krb5_storage_write(sp, s, strlen(s));
+    sz = krb5_storage_write(sp, s, strlen(s));
     free(s);
-    return ret;
+    return sz;
 }
 
 static krb5_error_code
-append_hex(krb5_context context, krb5_storage *sp, krb5_data *data)
+append_hex(krb5_context context, krb5_storage *sp,
+           int always_encode, int lower, krb5_data *data)
 {
+    ssize_t sz;
     int printable = 1;
     size_t i;
     char *p;
 
     p = data->data;
-    for(i = 0; i < data->length; i++)
-	if(!isalnum((unsigned char)p[i]) && p[i] != '.'){
-	    printable = 0;
-	    break;
-	}
-    if(printable)
+    if (!always_encode) {
+        for (i = 0; i < data->length; i++) {
+            if (!isalnum((unsigned char)p[i]) && p[i] != '.'){
+                printable = 0;
+                break;
+            }
+        }
+    }
+    if (printable && !always_encode)
 	return append_string(context, sp, "\"%.*s\"",
 			     data->length, data->data);
-    hex_encode(data->data, data->length, &p);
-    append_string(context, sp, "%s", p);
+    sz = hex_encode(data->data, data->length, &p);
+    if (sz == -1) return sz;
+    if (lower)
+        strlwr(p);
+    sz = append_string(context, sp, "%s", p);
     free(p);
-    return 0;
+    return sz;
 }
 
 static char *
@@ -105,29 +118,97 @@ time2str(time_t t)
     return buf;
 }
 
-static krb5_error_code
+static ssize_t
 append_event(krb5_context context, krb5_storage *sp, Event *ev)
 {
-    char *pr = NULL;
     krb5_error_code ret;
+    ssize_t sz;
+    char *pr = NULL;
     if(ev == NULL)
 	return append_string(context, sp, "- ");
     if (ev->principal != NULL) {
        ret = krb5_unparse_name(context, ev->principal, &pr);
-       if(ret)
-           return ret;
+       if (ret) return -1; /* krb5_unparse_name() sets error info */
     }
-    ret = append_string(context, sp, "%s:%s ",
-			time2str(ev->time), pr ? pr : "UNKNOWN");
+    sz = append_string(context, sp, "%s:%s ", time2str(ev->time),
+                       pr ? pr : "UNKNOWN");
     free(pr);
-    return ret;
+    return sz;
+}
+
+#define KRB5_KDB_SALTTYPE_NORMAL        0
+#define KRB5_KDB_SALTTYPE_V4            1
+#define KRB5_KDB_SALTTYPE_NOREALM       2
+#define KRB5_KDB_SALTTYPE_ONLYREALM     3
+#define KRB5_KDB_SALTTYPE_SPECIAL       4
+#define KRB5_KDB_SALTTYPE_AFS3          5
+
+static ssize_t
+append_mit_key(krb5_context context, krb5_storage *sp,
+               krb5_const_principal princ,
+               unsigned int kvno, Key *key)
+{
+    krb5_error_code ret;
+    ssize_t sz;
+    size_t key_versions = key->salt ? 2 : 1;
+    size_t decrypted_key_length;
+    char buf[2];
+    krb5_data keylenbytes;
+    unsigned int salttype;
+
+    sz = append_string(context, sp, "\t%u\t%u\t%d\t%d\t", key_versions, kvno,
+                        key->key.keytype, key->key.keyvalue.length + 2);
+    if (sz == -1) return sz;
+    ret = krb5_enctype_keysize(context, key->key.keytype, &decrypted_key_length);
+    if (ret) return -1; /* XXX we lose the error code */
+    buf[0] = decrypted_key_length & 0xff;
+    buf[1] = (decrypted_key_length & 0xff00) >> 8;
+    keylenbytes.data = buf;
+    keylenbytes.length = sizeof (buf);
+    sz = append_hex(context, sp, 1, 1, &keylenbytes);
+    if (sz == -1) return sz;
+    sz = append_hex(context, sp, 1, 1, &key->key.keyvalue);
+    if (!key->salt)
+        return sz;
+    
+    /* Map salt to MIT KDB style */
+    if (key->salt->type == KRB5_PADATA_PW_SALT) {
+        krb5_salt k5salt;
+
+        /*
+         * Compute normal salt and then see whether it matches the stored one
+         */
+        ret = krb5_get_pw_salt(context, princ, &k5salt);
+        if (ret) return -1;
+        if (k5salt.saltvalue.length == key->salt->salt.length &&
+            memcmp(k5salt.saltvalue.data, key->salt->salt.data,
+                   k5salt.saltvalue.length) == 0)
+            salttype = KRB5_KDB_SALTTYPE_NORMAL; /* matches */
+        else if (key->salt->salt.length == strlen(princ->realm) &&
+                 memcmp(key->salt->salt.data, princ->realm,
+                        key->salt->salt.length) == 0)
+            salttype = KRB5_KDB_SALTTYPE_ONLYREALM; /* matches realm */
+        else if (key->salt->salt.length == k5salt.saltvalue.length - strlen(princ->realm) &&
+                 memcmp((char *)k5salt.saltvalue.data + strlen(princ->realm),
+                        key->salt->salt.data, key->salt->salt.length) == 0)
+            salttype = KRB5_KDB_SALTTYPE_NOREALM; /* matches w/o realm */
+        else
+            salttype = KRB5_KDB_SALTTYPE_NORMAL;  /* hope for best */
+
+    } else if (key->salt->type == KRB5_PADATA_AFS3_SALT) {
+        salttype = KRB5_KDB_SALTTYPE_AFS3;
+    }
+    sz = append_string(context, sp, "\t%u\t%u\t", salttype,
+                       key->salt->salt.length);
+    if (sz == -1) return sz;
+    return append_hex(context, sp, 1, 1, &key->salt->salt);
 }
 
 static krb5_error_code
 entry2string_int (krb5_context context, krb5_storage *sp, hdb_entry *ent)
 {
     char *p;
-    size_t i;
+    int i;
     krb5_error_code ret;
 
     /* --- principal */
@@ -149,12 +230,12 @@ entry2string_int (krb5_context context, krb5_storage *sp, hdb_entry *ent)
 	    append_string(context, sp, "::%d:",
 			  ent->keys.val[i].key.keytype);
 	/* --- keydata */
-	append_hex(context, sp, &ent->keys.val[i].key.keyvalue);
+	append_hex(context, sp, 0, 0, &ent->keys.val[i].key.keyvalue);
 	append_string(context, sp, ":");
 	/* --- salt */
 	if(ent->keys.val[i].salt){
 	    append_string(context, sp, "%u/", ent->keys.val[i].salt->type);
-	    append_hex(context, sp, &ent->keys.val[i].salt->salt);
+	    append_hex(context, sp, 0, 0, &ent->keys.val[i].salt->salt);
 	}else
 	    append_string(context, sp, "-");
     }
@@ -234,25 +315,266 @@ entry2string_int (krb5_context context, krb5_storage *sp, hdb_entry *ent)
     } else
 	append_string(context, sp, "-");
 
+    return 0;
+}
+
+#define KRB5_KDB_DISALLOW_POSTDATED     0x00000001
+#define KRB5_KDB_DISALLOW_FORWARDABLE   0x00000002
+#define KRB5_KDB_DISALLOW_TGT_BASED     0x00000004
+#define KRB5_KDB_DISALLOW_RENEWABLE     0x00000008
+#define KRB5_KDB_DISALLOW_PROXIABLE     0x00000010
+#define KRB5_KDB_DISALLOW_DUP_SKEY      0x00000020
+#define KRB5_KDB_DISALLOW_ALL_TIX       0x00000040
+#define KRB5_KDB_REQUIRES_PRE_AUTH      0x00000080
+#define KRB5_KDB_REQUIRES_HW_AUTH       0x00000100
+#define KRB5_KDB_REQUIRES_PWCHANGE      0x00000200
+#define KRB5_KDB_DISALLOW_SVR           0x00001000
+#define KRB5_KDB_PWCHANGE_SERVICE       0x00002000
+#define KRB5_KDB_SUPPORT_DESMD5         0x00004000
+#define KRB5_KDB_NEW_PRINC              0x00008000
+
+static int
+flags_to_attr(HDBFlags flags)
+{
+    int a = 0;
+
+    if (!flags.postdate)
+        a |= KRB5_KDB_DISALLOW_POSTDATED;
+    if (!flags.forwardable)
+        a |= KRB5_KDB_DISALLOW_FORWARDABLE;
+    if (flags.initial)
+        a |= KRB5_KDB_DISALLOW_TGT_BASED;
+    if (!flags.renewable)
+        a |= KRB5_KDB_DISALLOW_RENEWABLE;
+    if (!flags.proxiable)
+        a |= KRB5_KDB_DISALLOW_PROXIABLE;
+    if (flags.invalid)
+        a |= KRB5_KDB_DISALLOW_ALL_TIX;
+    if (flags.require_preauth)
+        a |= KRB5_KDB_REQUIRES_PRE_AUTH;
+    if (flags.require_hwauth)
+        a |= KRB5_KDB_REQUIRES_HW_AUTH;
+    if (!flags.server)
+        a |= KRB5_KDB_DISALLOW_SVR;
+    if (flags.change_pw)
+        a |= KRB5_KDB_PWCHANGE_SERVICE;
+    return a;
+}
 
+krb5_error_code
+entry2mit_string_int(krb5_context context, krb5_storage *sp, hdb_entry *ent)
+{
+    krb5_error_code ret;
+    ssize_t sz;
+    size_t i, k;
+    size_t num_tl_data = 0;
+    size_t num_key_data = 0;
+    char *p;
+    HDB_Ext_KeySet *hist_keys = NULL;
+    HDB_extension *extp;
+    time_t last_pw_chg = 0;
+    time_t exp = 0;
+    time_t pwexp = 0;
+    unsigned int max_life = 0;
+    unsigned int max_renew = 0;
+
+    /* Always create a modified_by entry. */
+    num_tl_data++;
+
+    ret = hdb_entry_get_pw_change_time(ent, &last_pw_chg);
+    if (ret) return ret;
+    if (last_pw_chg)
+        num_tl_data++;
+
+    extp = hdb_find_extension(ent, choice_HDB_extension_data_hist_keys);
+    if (extp)
+        hist_keys = &extp->data.u.hist_keys;
+
+    for (i = 0; i < ent->keys.len;i++) {
+	if (!mit_strong_etype(ent->keys.val[i].key.keytype))
+            continue;
+        num_key_data++;
+    }
+    if (hist_keys) {
+        for (i = 0; i < hist_keys->len; i++) {
+            /*
+             * MIT uses the highest kvno as the current kvno instead of
+             * tracking kvno separately, so we can't dump keysets with kvno
+             * higher than the entry's kvno.
+             */
+            if (hist_keys->val[i].kvno >= ent->kvno)
+                continue;
+            for (k = 0; k < hist_keys->val[i].keys.len; k++) {
+                if (ent->keys.val[k].key.keytype == ETYPE_DES_CBC_MD4 ||
+                    ent->keys.val[k].key.keytype == ETYPE_DES_CBC_MD5)
+                    continue;
+                num_key_data++;
+            }
+        }
+    }
+
+    ret = krb5_unparse_name(context, ent->principal, &p);
+    if (ret) return ret;
+    sz = append_string(context, sp, "princ\t38\t%u\t%u\t%u\t0\t%s\t%d",
+                       strlen(p), num_tl_data, num_key_data, p,
+                       flags_to_attr(ent->flags));
+    if (sz == -1) {
+	free(p);
+	return ENOMEM;
+    }
+
+    if (ent->max_life)
+        max_life = *ent->max_life;
+    if (ent->max_renew)
+        max_renew = *ent->max_renew;
+    if (ent->valid_end)
+        exp = *ent->valid_end;
+    if (ent->pw_end)
+        pwexp = *ent->pw_end;
+
+    sz = append_string(context, sp, "\t%u\t%u\t%u\t%u\t0\t0\t0",
+                       max_life, max_renew, exp, pwexp);
+    if (sz == -1) {
+	free(p);
+	return ENOMEM;
+    }
+
+    /* Dump TL data we know: last pw chg and modified_by */
+#define mit_KRB5_TL_LAST_PWD_CHANGE     1
+#define mit_KRB5_TL_MOD_PRINC           2
+    if (last_pw_chg) {
+        krb5_data d;
+        time_t val;
+        unsigned char *ptr;
+        
+        ptr = (unsigned char *)&last_pw_chg;
+        val = ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
+        d.data = &val;
+        d.length = sizeof (last_pw_chg);
+        sz = append_string(context, sp, "\t%u\t%u\t",
+                           mit_KRB5_TL_LAST_PWD_CHANGE, d.length);
+	if (sz == -1) {
+	    free(p);
+	    return ENOMEM;
+	}
+        sz = append_hex(context, sp, 1, 1, &d);
+	if (sz == -1) {
+	    free(p);
+	    return ENOMEM;
+	}
+    }
+    if (ent->modified_by) {
+        krb5_data d;
+        unsigned int val;
+        size_t plen;
+        unsigned char *ptr;
+        char *modby_p;
+
+	free(p);
+        ptr = (unsigned char *)&ent->modified_by->time;
+        val = ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
+        d.data = &val;
+        d.length = sizeof (ent->modified_by->time);
+        ret = krb5_unparse_name(context, ent->modified_by->principal, &modby_p);
+        if (ret) return ret;
+        plen = strlen(modby_p);
+        sz = append_string(context, sp, "\t%u\t%u\t",
+                           mit_KRB5_TL_MOD_PRINC,
+                           d.length + plen + 1 /* NULL counted */);
+        if (sz == -1) {
+            free(modby_p);
+            return ENOMEM;
+        }
+        sz = append_hex(context, sp, 1, 1, &d);
+        if (sz == -1) {
+            free(modby_p);
+            return ENOMEM;
+        }
+        d.data = modby_p;
+        d.length = plen + 1;
+        sz = append_hex(context, sp, 1, 1, &d);
+        free(modby_p);
+        if (sz == -1) return ENOMEM;
+    } else {
+        krb5_data d;
+        unsigned int val;
+        size_t plen;
+        unsigned char *ptr;
+
+	/* Fake the entry to make MIT happy. */
+        ptr = (unsigned char *)&last_pw_chg;
+        val = ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
+        d.data = &val;
+        d.length = sizeof (last_pw_chg);
+        plen = strlen(p);
+        sz = append_string(context, sp, "\t%u\t%u\t",
+                           mit_KRB5_TL_MOD_PRINC,
+                           d.length + plen + 1 /* NULL counted */);
+	if (sz == -1) {
+	    free(p);
+	    return ENOMEM;
+	}
+        sz = append_hex(context, sp, 1, 1, &d);
+	if (sz == -1) {
+	    free(p);
+	    return ENOMEM;
+	}
+        d.data = p;
+        d.length = plen + 1;
+        sz = append_hex(context, sp, 1, 1, &d);
+	free(p);
+        if (sz == -1) return ENOMEM;
+    }
+    /*
+     * Dump keys (remembering to not include any with kvno higher than
+     * the entry's because MIT doesn't track entry kvno separately from
+     * the entry's keys -- max kvno is it)
+     */
+    for (i = 0; i < ent->keys.len; i++) {
+	if (!mit_strong_etype(ent->keys.val[i].key.keytype))
+            continue;
+        sz = append_mit_key(context, sp, ent->principal, ent->kvno,
+                            &ent->keys.val[i]);
+        if (sz == -1) return ENOMEM;
+    }
+    for (i = 0; hist_keys && i < ent->kvno; i++) {
+        size_t m;
+
+        /* dump historical keys */
+        for (k = 0; k < hist_keys->len; k++) {
+            if (hist_keys->val[k].kvno != ent->kvno - i)
+                continue;
+            for (m = 0; m < hist_keys->val[k].keys.len; m++) {
+                if (ent->keys.val[k].key.keytype == ETYPE_DES_CBC_MD4 ||
+                    ent->keys.val[k].key.keytype == ETYPE_DES_CBC_MD5)
+                    continue;
+                sz = append_mit_key(context, sp, ent->principal,
+                                    hist_keys->val[k].kvno,
+                                    &hist_keys->val[k].keys.val[m]);
+                if (sz == -1) return ENOMEM;
+            }
+        }
+    }
+    sz = append_string(context, sp, "\t-1;"); /* "extra data" */
+    if (sz == -1) return ENOMEM;
     return 0;
 }
 
 krb5_error_code
-hdb_entry2string (krb5_context context, hdb_entry *ent, char **str)
+hdb_entry2string(krb5_context context, hdb_entry *ent, char **str)
 {
     krb5_error_code ret;
     krb5_data data;
     krb5_storage *sp;
 
     sp = krb5_storage_emem();
-    if(sp == NULL) {
+    if (sp == NULL) {
 	krb5_set_error_message(context, ENOMEM, "malloc: out of memory");
 	return ENOMEM;
     }
 
     ret = entry2string_int(context, sp, ent);
-    if(ret) {
+    if (ret) {
 	krb5_storage_free(sp);
 	return ret;
     }
@@ -267,22 +589,31 @@ hdb_entry2string (krb5_context context, hdb_entry *ent, char **str)
 /* print a hdb_entry to (FILE*)data; suitable for hdb_foreach */
 
 krb5_error_code
-hdb_print_entry(krb5_context context, HDB *db, hdb_entry_ex *entry, void *data)
+hdb_print_entry(krb5_context context, HDB *db, hdb_entry_ex *entry,
+                void *data)
 {
+    struct hdb_print_entry_arg *parg = data;
     krb5_error_code ret;
     krb5_storage *sp;
 
-    FILE *f = data;
-
-    fflush(f);
-    sp = krb5_storage_from_fd(fileno(f));
-    if(sp == NULL) {
+    fflush(parg->out);
+    sp = krb5_storage_from_fd(fileno(parg->out));
+    if (sp == NULL) {
 	krb5_set_error_message(context, ENOMEM, "malloc: out of memory");
 	return ENOMEM;
     }
 
-    ret = entry2string_int(context, sp, &entry->entry);
-    if(ret) {
+    switch (parg->fmt) {
+    case HDB_DUMP_HEIMDAL:
+        ret = entry2string_int(context, sp, &entry->entry);
+        break;
+    case HDB_DUMP_MIT:
+        ret = entry2mit_string_int(context, sp, &entry->entry);
+        break;
+    default:
+        heim_abort("Only two dump formats supported: Heimdal and MIT");
+    }
+    if (ret) {
 	krb5_storage_free(sp);
 	return ret;
     }
diff --git a/crypto/heimdal/lib/hdb/version-script.map b/crypto/heimdal/lib/hdb/version-script.map
index 50a36cec0aa9..42e2043b4b47 100644
--- a/crypto/heimdal/lib/hdb/version-script.map
+++ b/crypto/heimdal/lib/hdb/version-script.map
@@ -4,6 +4,7 @@ HEIMDAL_HDB_1.0 {
 	global:
 		encode_hdb_keyset;
 		hdb_add_master_key;
+		hdb_add_current_keys_to_history;
 		hdb_check_db_format;
 		hdb_clear_extension;
 		hdb_clear_master_key;
@@ -57,6 +58,7 @@ HEIMDAL_HDB_1.0 {
 		hdb_seal_key_mkey;
 		hdb_seal_keys;
 		hdb_seal_keys_mkey;
+                hdb_set_last_modified_by;
 		hdb_set_master_key;
 		hdb_set_master_keyfile;
 		hdb_unlock;
@@ -71,6 +73,10 @@ HEIMDAL_HDB_1.0 {
 		hdb_interface_version;
 		initialize_hdb_error_table_r;
 
+                # MIT KDB related entries
+                _hdb_mdb_value2entry;
+                _hdb_mit_dump2mitdb_entry;
+
 		hdb_kt_ops;
 
 		# some random bits needed for libkadm
diff --git a/crypto/heimdal/lib/kadm5/chpass_s.c b/crypto/heimdal/lib/kadm5/chpass_s.c
index 624293e5c3a3..22f65517fcc5 100644
--- a/crypto/heimdal/lib/kadm5/chpass_s.c
+++ b/crypto/heimdal/lib/kadm5/chpass_s.c
@@ -58,6 +58,10 @@ change(void *server_handle,
     if(ret)
 	goto out;
 
+    ret = hdb_add_current_keys_to_history(context->context, &ent.entry);
+    if (ret)
+	goto out;
+
     if (context->db->hdb_capability_flags & HDB_CAP_F_HANDLE_PASSWORDS) {
 	ret = context->db->hdb_password(context->context, context->db,
 					&ent, password, cond);
@@ -170,6 +174,9 @@ kadm5_s_chpass_principal_with_key(void *server_handle,
 				      HDB_F_GET_ANY|HDB_F_ADMIN_DATA, &ent);
     if(ret)
 	goto out;
+    ret = hdb_add_current_keys_to_history(context->context, &ent.entry);
+    if (ret)
+        goto out2;
     ret = _kadm5_set_keys2(context, &ent.entry, n_key_data, key_data);
     if(ret)
 	goto out2;
diff --git a/crypto/heimdal/lib/kadm5/randkey_s.c b/crypto/heimdal/lib/kadm5/randkey_s.c
index dcb179aac40f..adb3564be719 100644
--- a/crypto/heimdal/lib/kadm5/randkey_s.c
+++ b/crypto/heimdal/lib/kadm5/randkey_s.c
@@ -59,6 +59,10 @@ kadm5_s_randkey_principal(void *server_handle,
     if(ret)
 	goto out;
 
+    ret = hdb_add_current_keys_to_history(context->context, &ent.entry);
+    if (ret)
+        goto out2;
+
     ret = _kadm5_set_keys_randomly (context,
 				    &ent.entry,
 				    new_keys,
diff --git a/crypto/openssh/auth-pam.c b/crypto/openssh/auth-pam.c
index f95f6abbcbe0..df08dbd99a9d 100644
--- a/crypto/openssh/auth-pam.c
+++ b/crypto/openssh/auth-pam.c
@@ -937,8 +937,8 @@ sshpam_query(void *ctx, char **name, char **info,
 				sshbuf_free(buffer);
 				return (0);
 			}
-			BLACKLIST_NOTIFY(NULL, BLACKLIST_BAD_USER,
-			    sshpam_authctxt->user);
+			BLACKLIST_NOTIFY(NULL, BLACKLIST_AUTH_FAIL,
+			    "PAM illegal user");
 			error("PAM: %s for %s%.100s from %.100s", msg,
 			    sshpam_authctxt->valid ? "" : "illegal user ",
 			    sshpam_authctxt->user, sshpam_rhost);
diff --git a/crypto/openssh/auth.c b/crypto/openssh/auth.c
index 961082b76667..0a1c8f71b390 100644
--- a/crypto/openssh/auth.c
+++ b/crypto/openssh/auth.c
@@ -289,7 +289,8 @@ auth_log(struct ssh *ssh, int authenticated, int partial,
 	else {
 		authmsg = authenticated ? "Accepted" : "Failed";
 		if (authenticated)
-			BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_OK, "ssh");
+			BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_OK,
+			    "Authenticated");
 	}
 
 	if ((extra = format_method_key(authctxt)) == NULL) {
@@ -338,6 +339,7 @@ auth_maxtries_exceeded(struct ssh *ssh)
 {
 	Authctxt *authctxt = (Authctxt *)ssh->authctxt;
 
+	BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL, "Maximum attempts exceeded");
 	error("maximum authentication attempts exceeded for "
 	    "%s%.100s from %.200s port %d ssh2",
 	    authctxt->valid ? "" : "invalid user ",
@@ -498,7 +500,7 @@ getpwnamallow(struct ssh *ssh, const char *user)
 	aix_restoreauthdb();
 #endif
 	if (pw == NULL) {
-		BLACKLIST_NOTIFY(ssh, BLACKLIST_BAD_USER, user);
+		BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL, "Invalid user");
 		logit("Invalid user %.100s from %.100s port %d",
 		    user, ssh_remote_ipaddr(ssh), ssh_remote_port(ssh));
 #ifdef CUSTOM_FAILED_LOGIN
diff --git a/crypto/openssh/auth2.c b/crypto/openssh/auth2.c
index eac1d26a4aaf..82f6e6211259 100644
--- a/crypto/openssh/auth2.c
+++ b/crypto/openssh/auth2.c
@@ -52,7 +52,6 @@
 #include "dispatch.h"
 #include "pathnames.h"
 #include "ssherr.h"
-#include "blacklist_client.h"
 #ifdef GSSAPI
 #include "ssh-gss.h"
 #endif
@@ -443,10 +442,8 @@ userauth_finish(struct ssh *ssh, int authenticated, const char *packet_method,
 	} else {
 		/* Allow initial try of "none" auth without failure penalty */
 		if (!partial && !authctxt->server_caused_failure &&
-		    (authctxt->attempt > 1 || strcmp(method, "none") != 0)) {
+		    (authctxt->attempt > 1 || strcmp(method, "none") != 0))
 			authctxt->failures++;
-			BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL, "ssh");
-		}
 		if (authctxt->failures >= options.max_authtries) {
 #ifdef SSH_AUDIT_EVENTS
 			mm_audit_event(ssh, SSH_LOGIN_EXCEED_MAXTRIES);
diff --git a/crypto/openssh/monitor.c b/crypto/openssh/monitor.c
index 2179553d3401..b826ecdb9065 100644
--- a/crypto/openssh/monitor.c
+++ b/crypto/openssh/monitor.c
@@ -85,6 +85,8 @@
 #include "misc.h"
 #include "servconf.h"
 #include "monitor.h"
+#include "blacklist_client.h"
+
 #ifdef GSSAPI
 #include "ssh-gss.h"
 #endif
@@ -353,16 +355,24 @@ monitor_child_preauth(struct ssh *ssh, struct monitor *pmonitor)
 			}
 		}
 		if (authctxt->failures > options.max_authtries) {
+			BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL,
+			    "Too many authentication attempts");
 			/* Shouldn't happen */
 			fatal_f("privsep child made too many authentication "
 			    "attempts");
 		}
 	}
 
-	if (!authctxt->valid)
+	if (!authctxt->valid) {
+		BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL,
+		    "Authenticated invalid user");
 		fatal_f("authenticated invalid user");
-	if (strcmp(auth_method, "unknown") == 0)
+	}
+	if (strcmp(auth_method, "unknown") == 0) {
+		BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL,
+		    "Authentication method name unknown");
 		fatal_f("authentication method name unknown");
+	}
 
 	debug_f("user %s authenticated by privileged process", authctxt->user);
 	auth_attempted = 0;
diff --git a/crypto/openssh/packet.c b/crypto/openssh/packet.c
index cc114c837e31..9dea2cfc5188 100644
--- a/crypto/openssh/packet.c
+++ b/crypto/openssh/packet.c
@@ -96,7 +96,6 @@
 #include "packet.h"
 #include "ssherr.h"
 #include "sshbuf.h"
-#include "blacklist_client.h"
 
 #ifdef PACKET_DEBUG
 #define DBG(x) x
@@ -2022,7 +2021,6 @@ sshpkt_vfatal(struct ssh *ssh, int r, const char *fmt, va_list ap)
 	case SSH_ERR_NO_KEX_ALG_MATCH:
 	case SSH_ERR_NO_HOSTKEY_ALG_MATCH:
 		if (ssh->kex && ssh->kex->failed_choice) {
-			BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL, "ssh");
 			ssh_packet_clear_keys(ssh);
 			errno = oerrno;
 			logdie("Unable to negotiate with %s: %s. "
diff --git a/crypto/openssh/sshd-session.c b/crypto/openssh/sshd-session.c
index 902718524279..62c76cc1c8aa 100644
--- a/crypto/openssh/sshd-session.c
+++ b/crypto/openssh/sshd-session.c
@@ -217,6 +217,8 @@ mm_is_monitor(void)
 static void
 grace_alarm_handler(int sig)
 {
+	BLACKLIST_NOTIFY(the_active_state, BLACKLIST_AUTH_FAIL,
+	    "Grace period expired");
 	/*
 	 * Try to kill any processes that we have spawned, E.g. authorized
 	 * keys command helpers or privsep children.
@@ -1201,6 +1203,8 @@ main(int ac, char **av)
 	ssh_signal(SIGCHLD, SIG_DFL);
 	ssh_signal(SIGINT, SIG_DFL);
 
+	BLACKLIST_INIT();
+
 	/*
 	 * Register our connection.  This turns encryption off because we do
 	 * not have a key.
@@ -1277,8 +1281,10 @@ main(int ac, char **av)
 	}
 
 	if ((r = kex_exchange_identification(ssh, -1,
-	    options.version_addendum)) != 0)
+	    options.version_addendum)) != 0) {
+		BLACKLIST_NOTIFY(ssh, BLACKLIST_AUTH_FAIL, "Banner exchange");
 		sshpkt_fatal(ssh, r, "banner exchange");
+	}
 
 	ssh_packet_set_nonblocking(ssh);
 
@@ -1298,8 +1304,6 @@ main(int ac, char **av)
 		fatal("sshbuf_new loginmsg failed");
 	auth_debug_reset();
 
-	BLACKLIST_INIT();
-
 	if (privsep_preauth(ssh) != 1)
 		fatal("privsep_preauth failed");
 
@@ -1425,7 +1429,10 @@ cleanup_exit(int i)
 		audit_event(the_active_state, SSH_CONNECTION_ABANDON);
 #endif
 	/* Override default fatal exit value when auth was attempted */
-	if (i == 255 && auth_attempted)
+	if (i == 255 && auth_attempted) {
+		BLACKLIST_NOTIFY(the_active_state, BLACKLIST_AUTH_FAIL,
+		    "Fatal exit");
 		_exit(EXIT_AUTH_ATTEMPTED);
+	}
 	_exit(i);
 }
diff --git a/crypto/openssl/CHANGES.md b/crypto/openssl/CHANGES.md
index 5f5ba3ef1751..b991285aedb2 100644
--- a/crypto/openssl/CHANGES.md
+++ b/crypto/openssl/CHANGES.md
@@ -28,6 +28,72 @@ OpenSSL Releases
 OpenSSL 3.5
 -----------
 
+### Changes between 3.5.3 and 3.5.4 [30 Sep 2025]
+
+ * Fix Out-of-bounds read & write in RFC 3211 KEK Unwrap
+
+   Issue summary: An application trying to decrypt CMS messages encrypted using
+   password based encryption can trigger an out-of-bounds read and write.
+
+   Impact summary: This out-of-bounds read may trigger a crash which leads to
+   Denial of Service for an application. The out-of-bounds write can cause
+   a memory corruption which can have various consequences including
+   a Denial of Service or Execution of attacker-supplied code.
+
+   The issue was reported by Stanislav Fort (Aisle Research).
+
+   ([CVE-2025-9230])
+
+   *Viktor Dukhovni*
+
+ * Fix Timing side-channel in SM2 algorithm on 64 bit ARM
+
+   Issue summary: A timing side-channel which could potentially allow remote
+   recovery of the private key exists in the SM2 algorithm implementation on
+   64 bit ARM platforms.
+
+   Impact summary: A timing side-channel in SM2 signature computations on
+   64 bit ARM platforms could allow recovering the private key by an attacker.
+
+   The issue was reported by Stanislav Fort (Aisle Research).
+
+   ([CVE-2025-9231])
+
+   *Stanislav Fort and Tomáš Mráz*
+
+ * Fix Out-of-bounds read in HTTP client no_proxy handling
+
+   Issue summary: An application using the OpenSSL HTTP client API functions
+   may trigger an out-of-bounds read if the "no_proxy" environment variable is
+   set and the host portion of the authority component of the HTTP URL is an
+   IPv6 address.
+
+   Impact summary: An out-of-bounds read can trigger a crash which leads to
+   Denial of Service for an application.
+
+   The issue was reported by Stanislav Fort (Aisle Research).
+
+   ([CVE-2025-9232])
+
+   *Stanislav Fort*
+
+ * The FIPS provider no longer performs a PCT on key import for ECX keys
+   (that was introduced in 3.5.2), following the latest update
+   on that requirement in FIPS 140-3 IG 10.3.A additional comment 1.
+
+   *Eugene Syromiatnikov*
+
+ * Fixed the length of the ASN.1 sequence for the SM3 digests of RSA-encrypted
+   signatures.
+
+   *Xiao Lou Dong Feng*
+
+ * Reverted the synthesised `OPENSSL_VERSION_NUMBER` change for the release
+   builds, as it broke some exiting applications that relied on the previous
+   3.x semantics, as documented in `OpenSSL_version(3)`.
+
+   *Richard Levitte*
+
 ### Changes between 3.5.2 and 3.5.3 [16 Sep 2025]
 
  * Avoided a potential race condition introduced in 3.5.1, where
@@ -21284,6 +21350,9 @@ ndif
 
 <!-- Links -->
 
+[CVE-2025-9232]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-9232
+[CVE-2025-9231]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-9231
+[CVE-2025-9230]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-9230
 [CVE-2025-4575]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-4575
 [CVE-2024-13176]: https://www.openssl.org/news/vulnerabilities.html#CVE-2024-13176
 [CVE-2024-9143]: https://www.openssl.org/news/vulnerabilities.html#CVE-2024-9143
diff --git a/crypto/openssl/NEWS.md b/crypto/openssl/NEWS.md
index 5d8a83f43068..b194dfb7cb06 100644
--- a/crypto/openssl/NEWS.md
+++ b/crypto/openssl/NEWS.md
@@ -23,19 +23,46 @@ OpenSSL Releases
 OpenSSL 3.5
 -----------
 
+### Major changes between OpenSSL 3.5.3 and OpenSSL 3.5.4 [30 Sep 2025]
+
+OpenSSL 3.5.4 is a security patch release. The most severe CVE fixed in this
+release is Moderate.
+
+This release incorporates the following bug fixes and mitigations:
+
+  * Fix Out-of-bounds read & write in RFC 3211 KEK Unwrap.
+    ([CVE-2025-9230])
+
+  * Fix Timing side-channel in SM2 algorithm on 64 bit ARM.
+    ([CVE-2025-9231])
+
+  * Fix Out-of-bounds read in HTTP client no_proxy handling.
+    ([CVE-2025-9232])
+
+  * Reverted the synthesised `OPENSSL_VERSION_NUMBER` change for the release
+    builds, as it broke some exiting applications that relied on the previous
+    3.x semantics, as documented in `OpenSSL_version(3)`.
+
 ### Major changes between OpenSSL 3.5.2 and OpenSSL 3.5.3 [16 Sep 2025]
 
-  * Added FIPS 140-3 PCT on DH key generation.
+OpenSSL 3.5.3 is a bug fix release.
+
+This release incorporates the following bug fixes and mitigations:
 
-    *Nikola Pajkovsky*
+  * Added FIPS 140-3 PCT on DH key generation.
 
   * Fixed the synthesised `OPENSSL_VERSION_NUMBER`.
 
-    *Richard Levitte*
+  * Removed PCT on key import in the FIPS provider as it is not required by
+    the standard.
 
 ### Major changes between OpenSSL 3.5.1 and OpenSSL 3.5.2 [5 Aug 2025]
 
-  * none
+OpenSSL 3.5.2 is a bug fix release.
+
+This release incorporates the following bug fixes and mitigations:
+
+  * The FIPS provider now performs a PCT on key import for RSA, EC and ECX.
 
 ### Major changes between OpenSSL 3.5.0 and OpenSSL 3.5.1 [1 Jul 2025]
 
@@ -45,7 +72,7 @@ release is Low.
 This release incorporates the following bug fixes and mitigations:
 
   * Fix x509 application adds trusted use instead of rejected use.
-   ([CVE-2025-4575])
+    ([CVE-2025-4575])
 
 ### Major changes between OpenSSL 3.4 and OpenSSL 3.5.0 [8 Apr 2025]
 
@@ -1913,6 +1940,9 @@ OpenSSL 0.9.x
   * Support for various new platforms
 
 <!-- Links -->
+[CVE-2025-9232]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-9232
+[CVE-2025-9231]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-9231
+[CVE-2025-9230]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-9230
 [CVE-2025-4575]: https://www.openssl.org/news/vulnerabilities.html#CVE-2025-4575
 [CVE-2024-13176]: https://www.openssl.org/news/vulnerabilities.html#CVE-2024-13176
 [CVE-2024-9143]: https://www.openssl.org/news/vulnerabilities.html#CVE-2024-9143
diff --git a/crypto/openssl/VERSION.dat b/crypto/openssl/VERSION.dat
index 8a2893b68006..a8eb3ac9c421 100644
--- a/crypto/openssl/VERSION.dat
+++ b/crypto/openssl/VERSION.dat
@@ -1,7 +1,7 @@
 MAJOR=3
 MINOR=5
-PATCH=3
+PATCH=4
 PRE_RELEASE_TAG=
 BUILD_METADATA=
-RELEASE_DATE="16 Sep 2025"
+RELEASE_DATE="30 Sep 2025"
 SHLIB_VERSION=3
diff --git a/crypto/openssl/apps/storeutl.c b/crypto/openssl/apps/storeutl.c
index 62f0e6135640..f8ebde44481c 100644
--- a/crypto/openssl/apps/storeutl.c
+++ b/crypto/openssl/apps/storeutl.c
@@ -331,14 +331,22 @@ int storeutl_main(int argc, char *argv[])
 static int indent_printf(int indent, BIO *bio, const char *format, ...)
 {
     va_list args;
-    int ret;
+    int ret, vret;
+
+    ret = BIO_printf(bio, "%*s", indent, "");
+    if (ret < 0)
+        return ret;
 
     va_start(args, format);
+    vret = BIO_vprintf(bio, format, args);
+    va_end(args);
 
-    ret = BIO_printf(bio, "%*s", indent, "") + BIO_vprintf(bio, format, args);
+    if (vret < 0)
+        return vret;
+    if (vret > INT_MAX - ret)
+        return INT_MAX;
 
-    va_end(args);
-    return ret;
+    return ret + vret;
 }
 
 static int process(const char *uri, const UI_METHOD *uimeth, PW_CB_DATA *uidata,
diff --git a/crypto/openssl/crypto/bio/bss_file.c b/crypto/openssl/crypto/bio/bss_file.c
index 2743a14417cf..ddcb4feb6a58 100644
--- a/crypto/openssl/crypto/bio/bss_file.c
+++ b/crypto/openssl/crypto/bio/bss_file.c
@@ -287,7 +287,7 @@ static long file_ctrl(BIO *b, int cmd, long num, void *ptr)
         if (fp == NULL) {
             ERR_raise_data(ERR_LIB_SYS, get_last_sys_error(),
                            "calling fopen(%s, %s)",
-                           ptr, p);
+                           (const char *)ptr, p);
             ERR_raise(ERR_LIB_BIO, ERR_R_SYS_LIB);
             ret = 0;
             break;
diff --git a/crypto/openssl/crypto/cms/cms_pwri.c b/crypto/openssl/crypto/cms/cms_pwri.c
index a7d609f83791..ee1b8aa6ed61 100644
--- a/crypto/openssl/crypto/cms/cms_pwri.c
+++ b/crypto/openssl/crypto/cms/cms_pwri.c
@@ -242,7 +242,7 @@ static int kek_unwrap_key(unsigned char *out, size_t *outlen,
         /* Check byte failure */
         goto err;
     }
-    if (inlen < (size_t)(tmp[0] - 4)) {
+    if (inlen < 4 + (size_t)tmp[0]) {
         /* Invalid length value */
         goto err;
     }
diff --git a/crypto/openssl/crypto/ec/ecp_sm2p256.c b/crypto/openssl/crypto/ec/ecp_sm2p256.c
index 7668b61378b6..4c39be2186fb 100644
--- a/crypto/openssl/crypto/ec/ecp_sm2p256.c
+++ b/crypto/openssl/crypto/ec/ecp_sm2p256.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 2023-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -56,10 +56,6 @@ ALIGN32 static const BN_ULONG def_p[P256_LIMBS] = {
     0xffffffffffffffff, 0xffffffff00000000,
     0xffffffffffffffff, 0xfffffffeffffffff
 };
-ALIGN32 static const BN_ULONG def_ord[P256_LIMBS] = {
-    0x53bbf40939d54123, 0x7203df6b21c6052b,
-    0xffffffffffffffff, 0xfffffffeffffffff
-};
 
 ALIGN32 static const BN_ULONG ONE[P256_LIMBS] = {1, 0, 0, 0};
 
@@ -177,13 +173,6 @@ static ossl_inline void ecp_sm2p256_mod_inverse(BN_ULONG* out,
     BN_MOD_INV(out, in, ecp_sm2p256_div_by_2, ecp_sm2p256_sub, def_p);
 }
 
-/* Modular inverse mod order |out| = |in|^(-1) % |ord|. */
-static ossl_inline void ecp_sm2p256_mod_ord_inverse(BN_ULONG* out,
-                                                    const BN_ULONG* in) {
-    BN_MOD_INV(out, in, ecp_sm2p256_div_by_2_mod_ord, ecp_sm2p256_sub_mod_ord,
-               def_ord);
-}
-
 /* Point double: R <- P + P */
 static void ecp_sm2p256_point_double(P256_POINT *R, const P256_POINT *P)
 {
@@ -454,52 +443,6 @@ static int ecp_sm2p256_is_affine_G(const EC_POINT *generator)
 }
 #endif
 
-/*
- * Convert Jacobian coordinate point into affine coordinate (x,y)
- */
-static int ecp_sm2p256_get_affine(const EC_GROUP *group,
-                                  const EC_POINT *point,
-                                  BIGNUM *x, BIGNUM *y, BN_CTX *ctx)
-{
-    ALIGN32 BN_ULONG z_inv2[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG z_inv3[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG x_aff[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG y_aff[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG point_x[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG point_y[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG point_z[P256_LIMBS] = {0};
-
-    if (EC_POINT_is_at_infinity(group, point)) {
-        ECerr(ERR_LIB_EC, EC_R_POINT_AT_INFINITY);
-        return 0;
-    }
-
-    if (ecp_sm2p256_bignum_field_elem(point_x, point->X) <= 0
-        || ecp_sm2p256_bignum_field_elem(point_y, point->Y) <= 0
-        || ecp_sm2p256_bignum_field_elem(point_z, point->Z) <= 0) {
-        ECerr(ERR_LIB_EC, EC_R_COORDINATES_OUT_OF_RANGE);
-        return 0;
-    }
-
-    ecp_sm2p256_mod_inverse(z_inv3, point_z);
-    ecp_sm2p256_sqr(z_inv2, z_inv3);
-
-    if (x != NULL) {
-        ecp_sm2p256_mul(x_aff, point_x, z_inv2);
-        if (!bn_set_words(x, x_aff, P256_LIMBS))
-            return 0;
-    }
-
-    if (y != NULL) {
-        ecp_sm2p256_mul(z_inv3, z_inv3, z_inv2);
-        ecp_sm2p256_mul(y_aff, point_y, z_inv3);
-        if (!bn_set_words(y, y_aff, P256_LIMBS))
-            return 0;
-    }
-
-    return 1;
-}
-
 /* r = sum(scalar[i]*point[i]) */
 static int ecp_sm2p256_windowed_mul(const EC_GROUP *group,
                                     P256_POINT *r,
@@ -689,44 +632,6 @@ static int ecp_sm2p256_field_sqr(const EC_GROUP *group, BIGNUM *r,
     return 1;
 }
 
-static int ecp_sm2p256_inv_mod_ord(const EC_GROUP *group, BIGNUM *r,
-                                             const BIGNUM *x, BN_CTX *ctx)
-{
-    int ret = 0;
-    ALIGN32 BN_ULONG t[P256_LIMBS] = {0};
-    ALIGN32 BN_ULONG out[P256_LIMBS] = {0};
-
-    if (bn_wexpand(r, P256_LIMBS) == NULL) {
-        ECerr(ERR_LIB_EC, ERR_R_BN_LIB);
-        goto err;
-    }
-
-    if ((BN_num_bits(x) > 256) || BN_is_negative(x)) {
-        BIGNUM *tmp;
-
-        if ((tmp = BN_CTX_get(ctx)) == NULL
-            || !BN_nnmod(tmp, x, group->order, ctx)) {
-            ECerr(ERR_LIB_EC, ERR_R_BN_LIB);
-            goto err;
-        }
-        x = tmp;
-    }
-
-    if (!ecp_sm2p256_bignum_field_elem(t, x)) {
-        ECerr(ERR_LIB_EC, EC_R_COORDINATES_OUT_OF_RANGE);
-        goto err;
-    }
-
-    ecp_sm2p256_mod_ord_inverse(out, t);
-
-    if (!bn_set_words(r, out, P256_LIMBS))
-        goto err;
-
-    ret = 1;
-err:
-    return ret;
-}
-
 const EC_METHOD *EC_GFp_sm2p256_method(void)
 {
     static const EC_METHOD ret = {
@@ -747,7 +652,7 @@ const EC_METHOD *EC_GFp_sm2p256_method(void)
         ossl_ec_GFp_simple_point_copy,
         ossl_ec_GFp_simple_point_set_to_infinity,
         ossl_ec_GFp_simple_point_set_affine_coordinates,
-        ecp_sm2p256_get_affine,
+        ossl_ec_GFp_simple_point_get_affine_coordinates,
         0, 0, 0,
         ossl_ec_GFp_simple_add,
         ossl_ec_GFp_simple_dbl,
@@ -763,7 +668,7 @@ const EC_METHOD *EC_GFp_sm2p256_method(void)
         ecp_sm2p256_field_mul,
         ecp_sm2p256_field_sqr,
         0 /* field_div */,
-        0 /* field_inv */,
+        ossl_ec_GFp_simple_field_inv,
         0 /* field_encode */,
         0 /* field_decode */,
         0 /* field_set_to_one */,
@@ -779,7 +684,7 @@ const EC_METHOD *EC_GFp_sm2p256_method(void)
         ossl_ecdsa_simple_sign_setup,
         ossl_ecdsa_simple_sign_sig,
         ossl_ecdsa_simple_verify_sig,
-        ecp_sm2p256_inv_mod_ord,
+        0, /* use constant‑time fallback for inverse mod order */
         0, /* blind_coordinates */
         0, /* ladder_pre */
         0, /* ladder_step */
diff --git a/crypto/openssl/crypto/evp/bio_ok.c b/crypto/openssl/crypto/evp/bio_ok.c
index 20811ffded6f..d7f6c71ee1ad 100644
--- a/crypto/openssl/crypto/evp/bio_ok.c
+++ b/crypto/openssl/crypto/evp/bio_ok.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 1995-2024 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 1995-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -560,7 +560,7 @@ static int block_in(BIO *b)
 {
     BIO_OK_CTX *ctx;
     EVP_MD_CTX *md;
-    unsigned long tl = 0;
+    size_t tl = 0;
     unsigned char tmp[EVP_MAX_MD_SIZE];
     int md_size;
 
@@ -571,15 +571,18 @@ static int block_in(BIO *b)
         goto berr;
 
     assert(sizeof(tl) >= OK_BLOCK_BLOCK); /* always true */
-    tl = ctx->buf[0];
-    tl <<= 8;
-    tl |= ctx->buf[1];
-    tl <<= 8;
-    tl |= ctx->buf[2];
-    tl <<= 8;
-    tl |= ctx->buf[3];
-
-    if (ctx->buf_len < tl + OK_BLOCK_BLOCK + md_size)
+    tl = ((size_t)ctx->buf[0] << 24)
+           | ((size_t)ctx->buf[1] << 16)
+           | ((size_t)ctx->buf[2] << 8)
+           | ((size_t)ctx->buf[3]);
+
+    if (tl > OK_BLOCK_SIZE)
+        goto berr;
+
+    if (tl > SIZE_MAX - OK_BLOCK_BLOCK - (size_t)md_size)
+        goto berr;
+
+    if (ctx->buf_len < tl + OK_BLOCK_BLOCK + (size_t)md_size)
         return 1;
 
     if (!EVP_DigestUpdate(md,
@@ -587,7 +590,7 @@ static int block_in(BIO *b)
         goto berr;
     if (!EVP_DigestFinal_ex(md, tmp, NULL))
         goto berr;
-    if (memcmp(&(ctx->buf[tl + OK_BLOCK_BLOCK]), tmp, md_size) == 0) {
+    if (memcmp(&(ctx->buf[tl + OK_BLOCK_BLOCK]), tmp, (size_t)md_size) == 0) {
         /* there might be parts from next block lurking around ! */
         ctx->buf_off_save = tl + OK_BLOCK_BLOCK + md_size;
         ctx->buf_len_save = ctx->buf_len;
diff --git a/crypto/openssl/crypto/evp/ctrl_params_translate.c b/crypto/openssl/crypto/evp/ctrl_params_translate.c
index ed73fc0fbb8d..c846353200b2 100644
--- a/crypto/openssl/crypto/evp/ctrl_params_translate.c
+++ b/crypto/openssl/crypto/evp/ctrl_params_translate.c
@@ -1356,7 +1356,7 @@ static int fix_rsa_padding_mode(enum state state,
         if (i == OSSL_NELEM(str_value_map)) {
             ERR_raise_data(ERR_LIB_RSA, RSA_R_UNKNOWN_PADDING_TYPE,
                            "[action:%d, state:%d] padding name %s",
-                           ctx->action_type, state, ctx->p1);
+                           ctx->action_type, state, (const char *)ctx->p2);
             ctx->p1 = ret = -2;
         } else if (state == POST_CTRL_TO_PARAMS) {
             /* EVP_PKEY_CTRL_GET_RSA_PADDING weirdness explained further up */
diff --git a/crypto/openssl/crypto/evp/p_lib.c b/crypto/openssl/crypto/evp/p_lib.c
index 7f4508169dfa..63953a84e1f5 100644
--- a/crypto/openssl/crypto/evp/p_lib.c
+++ b/crypto/openssl/crypto/evp/p_lib.c
@@ -1146,15 +1146,14 @@ int EVP_PKEY_can_sign(const EVP_PKEY *pkey)
     } else {
         const OSSL_PROVIDER *prov = EVP_KEYMGMT_get0_provider(pkey->keymgmt);
         OSSL_LIB_CTX *libctx = ossl_provider_libctx(prov);
-        const char *supported_sig =
-            pkey->keymgmt->query_operation_name != NULL
-            ? pkey->keymgmt->query_operation_name(OSSL_OP_SIGNATURE)
-            : EVP_KEYMGMT_get0_name(pkey->keymgmt);
-        EVP_SIGNATURE *signature = NULL;
-
-        signature = EVP_SIGNATURE_fetch(libctx, supported_sig, NULL);
-        if (signature != NULL) {
-            EVP_SIGNATURE_free(signature);
+        EVP_SIGNATURE *sig;
+        const char *name;
+
+        name = evp_keymgmt_util_query_operation_name(pkey->keymgmt,
+                                                     OSSL_OP_SIGNATURE);
+        sig = EVP_SIGNATURE_fetch(libctx, name, NULL);
+        if (sig != NULL) {
+            EVP_SIGNATURE_free(sig);
             return 1;
         }
     }
diff --git a/crypto/openssl/crypto/http/http_lib.c b/crypto/openssl/crypto/http/http_lib.c
index fcf8a69e07a8..022b8c194cbe 100644
--- a/crypto/openssl/crypto/http/http_lib.c
+++ b/crypto/openssl/crypto/http/http_lib.c
@@ -263,6 +263,7 @@ static int use_proxy(const char *no_proxy, const char *server)
         /* strip leading '[' and trailing ']' from escaped IPv6 address */
         sl -= 2;
         strncpy(host, server + 1, sl);
+        host[sl] = '\0';
         server = host;
     }
 
diff --git a/crypto/openssl/crypto/info.c b/crypto/openssl/crypto/info.c
index 4d70471be255..e760ec094027 100644
--- a/crypto/openssl/crypto/info.c
+++ b/crypto/openssl/crypto/info.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019-2024 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 2019-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -23,6 +23,9 @@
 #if defined(__arm__) || defined(__arm) || defined(__aarch64__)
 # include "arm_arch.h"
 # define CPU_INFO_STR_LEN 128
+#elif defined(__powerpc__) || defined(__POWERPC__) || defined(_ARCH_PPC)
+# include "crypto/ppc_arch.h"
+# define CPU_INFO_STR_LEN 128
 #elif defined(__s390__) || defined(__s390x__)
 # include "s390x_arch.h"
 # define CPU_INFO_STR_LEN 2048
@@ -77,6 +80,15 @@ DEFINE_RUN_ONCE_STATIC(init_info_strings)
         BIO_snprintf(ossl_cpu_info_str + strlen(ossl_cpu_info_str),
                      sizeof(ossl_cpu_info_str) - strlen(ossl_cpu_info_str),
                      " env:%s", env);
+# elif defined(__powerpc__) || defined(__POWERPC__) || defined(_ARCH_PPC)
+    const char *env;
+
+    BIO_snprintf(ossl_cpu_info_str, sizeof(ossl_cpu_info_str),
+                 CPUINFO_PREFIX "OPENSSL_ppccap=0x%x", OPENSSL_ppccap_P);
+    if ((env = getenv("OPENSSL_ppccap")) != NULL)
+        BIO_snprintf(ossl_cpu_info_str + strlen(ossl_cpu_info_str),
+                     sizeof(ossl_cpu_info_str) - strlen(ossl_cpu_info_str),
+                     " env:%s", env);
 # elif defined(__s390__) || defined(__s390x__)
     const char *env;
 
diff --git a/crypto/openssl/crypto/ml_dsa/ml_dsa_key.c b/crypto/openssl/crypto/ml_dsa/ml_dsa_key.c
index 41df1a956fb8..50e3b5433085 100644
--- a/crypto/openssl/crypto/ml_dsa/ml_dsa_key.c
+++ b/crypto/openssl/crypto/ml_dsa/ml_dsa_key.c
@@ -311,6 +311,7 @@ int ossl_ml_dsa_key_has(const ML_DSA_KEY *key, int selection)
 static int public_from_private(const ML_DSA_KEY *key, EVP_MD_CTX *md_ctx,
                                VECTOR *t1, VECTOR *t0)
 {
+    int ret = 0;
     const ML_DSA_PARAMS *params = key->params;
     uint32_t k = params->k, l = params->l;
     POLY *polys;
@@ -343,9 +344,10 @@ static int public_from_private(const ML_DSA_KEY *key, EVP_MD_CTX *md_ctx,
 
     /* Zeroize secret */
     vector_zero(&s1_ntt);
+    ret = 1;
 err:
     OPENSSL_free(polys);
-    return 1;
+    return ret;
 }
 
 int ossl_ml_dsa_key_public_from_private(ML_DSA_KEY *key)
diff --git a/crypto/openssl/crypto/ml_kem/ml_kem.c b/crypto/openssl/crypto/ml_kem/ml_kem.c
index 4474af0f87cb..716c3bf4275e 100644
--- a/crypto/openssl/crypto/ml_kem/ml_kem.c
+++ b/crypto/openssl/crypto/ml_kem/ml_kem.c
@@ -2046,5 +2046,5 @@ int ossl_ml_kem_pubkey_cmp(const ML_KEM_KEY *key1, const ML_KEM_KEY *key2)
      * No match if just one of the public keys is not available, otherwise both
      * are unavailable, and for now such keys are considered equal.
      */
-    return (ossl_ml_kem_have_pubkey(key1) ^ ossl_ml_kem_have_pubkey(key2));
+    return (!(ossl_ml_kem_have_pubkey(key1) ^ ossl_ml_kem_have_pubkey(key2)));
 }
diff --git a/crypto/openssl/crypto/modes/siv128.c b/crypto/openssl/crypto/modes/siv128.c
index 72526b849eaf..4e52d8eb8782 100644
--- a/crypto/openssl/crypto/modes/siv128.c
+++ b/crypto/openssl/crypto/modes/siv128.c
@@ -202,9 +202,12 @@ int ossl_siv128_init(SIV128_CONTEXT *ctx, const unsigned char *key, int klen,
             || !EVP_MAC_final(mac_ctx, ctx->d.byte, &out_len,
                               sizeof(ctx->d.byte))) {
         EVP_CIPHER_CTX_free(ctx->cipher_ctx);
+        ctx->cipher_ctx = NULL;
         EVP_MAC_CTX_free(ctx->mac_ctx_init);
+        ctx->mac_ctx_init = NULL;
         EVP_MAC_CTX_free(mac_ctx);
         EVP_MAC_free(ctx->mac);
+        ctx->mac = NULL;
         return 0;
     }
     EVP_MAC_CTX_free(mac_ctx);
diff --git a/crypto/openssl/crypto/property/property_parse.c b/crypto/openssl/crypto/property/property_parse.c
index 3a67754224f0..23963c89bc46 100644
--- a/crypto/openssl/crypto/property/property_parse.c
+++ b/crypto/openssl/crypto/property/property_parse.c
@@ -641,7 +641,7 @@ static void put_str(const char *str, char **buf, size_t *remain, size_t *needed)
         }
 
     quotes = quote != '\0';
-    if (*remain == 0) {
+    if (*remain <= (size_t)quotes) {
         *needed += 2 * quotes;
         return;
     }
diff --git a/crypto/openssl/crypto/rsa/rsa_gen.c b/crypto/openssl/crypto/rsa/rsa_gen.c
index 033f66714add..f76bb7748369 100644
--- a/crypto/openssl/crypto/rsa/rsa_gen.c
+++ b/crypto/openssl/crypto/rsa/rsa_gen.c
@@ -734,18 +734,3 @@ err:
 
     return ret;
 }
-
-#ifdef FIPS_MODULE
-int ossl_rsa_key_pairwise_test(RSA *rsa)
-{
-    OSSL_CALLBACK *stcb;
-    void *stcbarg;
-    int res;
-
-    OSSL_SELF_TEST_get_callback(rsa->libctx, &stcb, &stcbarg);
-    res = rsa_keygen_pairwise_test(rsa, stcb, stcbarg);
-    if (res <= 0)
-        ossl_set_error_state(OSSL_SELF_TEST_TYPE_PCT_IMPORT);
-    return res;
-}
-#endif  /* FIPS_MODULE */
diff --git a/crypto/openssl/crypto/rsa/rsa_sign.c b/crypto/openssl/crypto/rsa/rsa_sign.c
index 78e4bad69e49..bb6e99acf9d3 100644
--- a/crypto/openssl/crypto/rsa/rsa_sign.c
+++ b/crypto/openssl/crypto/rsa/rsa_sign.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 1995-2024 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 1995-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -129,7 +129,7 @@ static const unsigned char digestinfo_ripemd160_der[] = {
 # ifndef OPENSSL_NO_SM3
 /* SM3 (1 2 156 10197 1 401) */
 static const unsigned char digestinfo_sm3_der[] = {
-    ASN1_SEQUENCE, 0x0f + SM3_DIGEST_LENGTH,
+    ASN1_SEQUENCE, 0x10 + SM3_DIGEST_LENGTH,
       ASN1_SEQUENCE, 0x0c,
         ASN1_OID, 0x08, 1 * 40 + 2, 0x81, 0x1c, 0xcf, 0x55, 1, 0x83, 0x78,
         ASN1_NULL, 0x00,
diff --git a/crypto/openssl/crypto/threads_pthread.c b/crypto/openssl/crypto/threads_pthread.c
index 44d6ebe09231..ace2dc499061 100644
--- a/crypto/openssl/crypto/threads_pthread.c
+++ b/crypto/openssl/crypto/threads_pthread.c
@@ -62,8 +62,10 @@ __tsan_mutex_post_lock((x), 0, 0)
 /*
  * The Non-Stop KLT thread model currently seems broken in its rwlock
  * implementation
+ * Likewise is there a problem with the glibc implementation on riscv.
  */
-# if defined(PTHREAD_RWLOCK_INITIALIZER) && !defined(_KLT_MODEL_)
+# if defined(PTHREAD_RWLOCK_INITIALIZER) && !defined(_KLT_MODEL_) \
+                                         && !defined(__riscv)
 #  define USE_RWLOCK
 # endif
 
@@ -279,7 +281,7 @@ static struct rcu_qp *get_hold_current_qp(struct rcu_lock_st *lock)
 
         /* if the idx hasn't changed, we're good, else try again */
         if (qp_idx == ATOMIC_LOAD_N(uint32_t, &lock->reader_idx,
-                                    __ATOMIC_RELAXED))
+                                    __ATOMIC_ACQUIRE))
             break;
 
         ATOMIC_SUB_FETCH(&lock->qp_group[qp_idx].users, (uint64_t)1,
@@ -403,8 +405,12 @@ static struct rcu_qp *update_qp(CRYPTO_RCU_LOCK *lock, uint32_t *curr_id)
     *curr_id = lock->id_ctr;
     lock->id_ctr++;
 
+    /*
+     * make the current state of everything visible by this release
+     * when get_hold_current_qp acquires the next qp
+     */
     ATOMIC_STORE_N(uint32_t, &lock->reader_idx, lock->current_alloc_idx,
-                   __ATOMIC_RELAXED);
+                   __ATOMIC_RELEASE);
 
     /*
      * this should make sure that the new value of reader_idx is visible in
diff --git a/crypto/openssl/crypto/x509/t_x509.c b/crypto/openssl/crypto/x509/t_x509.c
index 7d693669cd36..d849e642ce8b 100644
--- a/crypto/openssl/crypto/x509/t_x509.c
+++ b/crypto/openssl/crypto/x509/t_x509.c
@@ -219,7 +219,8 @@ int X509_ocspid_print(BIO *bp, X509 *x)
         goto err;
     if ((der = dertmp = OPENSSL_malloc(derlen)) == NULL)
         goto err;
-    i2d_X509_NAME(subj, &dertmp);
+    if (i2d_X509_NAME(subj, &dertmp) < 0)
+        goto err;
 
     md = EVP_MD_fetch(x->libctx, SN_sha1, x->propq);
     if (md == NULL)
diff --git a/crypto/openssl/crypto/x509/x509_lu.c b/crypto/openssl/crypto/x509/x509_lu.c
index 05ee7c8c6b51..eb2d47955b2e 100644
--- a/crypto/openssl/crypto/x509/x509_lu.c
+++ b/crypto/openssl/crypto/x509/x509_lu.c
@@ -408,7 +408,6 @@ static int x509_store_add(X509_STORE *store, void *x, int crl)
     }
 
     if (!X509_STORE_lock(store)) {
-        obj->type = X509_LU_NONE;
         X509_OBJECT_free(obj);
         return 0;
     }
diff --git a/crypto/openssl/doc/man3/DEFINE_STACK_OF.pod b/crypto/openssl/doc/man3/DEFINE_STACK_OF.pod
index ff2074820f68..eeb882f291e4 100644
--- a/crypto/openssl/doc/man3/DEFINE_STACK_OF.pod
+++ b/crypto/openssl/doc/man3/DEFINE_STACK_OF.pod
@@ -170,15 +170,14 @@ B<sk_I<TYPE>_set>() sets element I<idx> of I<sk> to I<ptr> replacing the current
 element. The new element value is returned or NULL if an error occurred:
 this will only happen if I<sk> is NULL or I<idx> is out of range.
 
-B<sk_I<TYPE>_find>() searches I<sk> for the element I<ptr>.  In the case
-where no comparison function has been specified, the function performs
-a linear search for a pointer equal to I<ptr>. The index of the first
-matching element is returned or B<-1> if there is no match. In the case
-where a comparison function has been specified, I<sk> is sorted and
-B<sk_I<TYPE>_find>() returns the index of a matching element or B<-1> if there
-is no match. Note that, in this case the comparison function will usually
-compare the values pointed to rather than the pointers themselves and
-the order of elements in I<sk> can change.
+B<sk_I<TYPE>_find>() searches I<sk> for the element I<ptr>. In the
+case where no comparison function has been specified, the function
+performs a linear search for a pointer equal to I<ptr>. In the case
+where a comparison function has been specified, the function performs
+a search for a element that the comparison function indicates is a
+match. If the stack is sorted, a binary search is used, otherwise, a
+linear search is used. B<sk_I<TYPE>_find>() returns the index of a
+matching element or B<-1> if there is no match.
 
 B<sk_I<TYPE>_find_ex>() operates like B<sk_I<TYPE>_find>() except when a
 comparison function has been specified and no matching element is found.
@@ -301,7 +300,7 @@ was changed to return 0 in this condition as for other errors.
 
 =head1 COPYRIGHT
 
-Copyright 2000-2024 The OpenSSL Project Authors. All Rights Reserved.
+Copyright 2000-2025 The OpenSSL Project Authors. All Rights Reserved.
 
 Licensed under the Apache License 2.0 (the "License").  You may not use
 this file except in compliance with the License.  You can obtain a copy
diff --git a/crypto/openssl/doc/man3/OpenSSL_version.pod b/crypto/openssl/doc/man3/OpenSSL_version.pod
index e5dff33dcdda..6b899cbe5438 100644
--- a/crypto/openssl/doc/man3/OpenSSL_version.pod
+++ b/crypto/openssl/doc/man3/OpenSSL_version.pod
@@ -256,9 +256,16 @@ L<crypto(7)>
 The macros and functions described here were added in OpenSSL 3.0,
 except for OPENSSL_VERSION_NUMBER and OpenSSL_version_num().
 
+=head1 BUGS
+
+There was a discrepancy between this manual and commentary + code
+in F<< <openssl/opensslv.h> >>, where the latter suggested that the
+four least significant bits of B<OPENSSL_VERSION_NUMBER> could be
+C<0x0f> in released OpenSSL versions.
+
 =head1 COPYRIGHT
 
-Copyright 2018-2022 The OpenSSL Project Authors. All Rights Reserved.
+Copyright 2018-2025 The OpenSSL Project Authors. All Rights Reserved.
 
 Licensed under the Apache License 2.0 (the "License").  You may not use
 this file except in compliance with the License.  You can obtain a copy
diff --git a/crypto/openssl/doc/man3/SSL_CIPHER_get_name.pod b/crypto/openssl/doc/man3/SSL_CIPHER_get_name.pod
index 09b7280bdd58..a10942433aa7 100644
--- a/crypto/openssl/doc/man3/SSL_CIPHER_get_name.pod
+++ b/crypto/openssl/doc/man3/SSL_CIPHER_get_name.pod
@@ -37,7 +37,7 @@ SSL_CIPHER_get_protocol_id
  int SSL_CIPHER_is_aead(const SSL_CIPHER *c);
  const SSL_CIPHER *SSL_CIPHER_find(SSL *ssl, const unsigned char *ptr);
  uint32_t SSL_CIPHER_get_id(const SSL_CIPHER *c);
- uint32_t SSL_CIPHER_get_protocol_id(const SSL_CIPHER *c);
+ uint16_t SSL_CIPHER_get_protocol_id(const SSL_CIPHER *c);
 
 =head1 DESCRIPTION
 
@@ -203,7 +203,7 @@ The OPENSSL_cipher_name() function was added in OpenSSL 1.1.1.
 
 =head1 COPYRIGHT
 
-Copyright 2000-2024 The OpenSSL Project Authors. All Rights Reserved.
+Copyright 2000-2025 The OpenSSL Project Authors. All Rights Reserved.
 
 Licensed under the Apache License 2.0 (the "License").  You may not use
 this file except in compliance with the License.  You can obtain a copy
diff --git a/crypto/openssl/doc/man3/SSL_SESSION_get0_hostname.pod b/crypto/openssl/doc/man3/SSL_SESSION_get0_hostname.pod
index f7add16d7bdd..0140deee9a5e 100644
--- a/crypto/openssl/doc/man3/SSL_SESSION_get0_hostname.pod
+++ b/crypto/openssl/doc/man3/SSL_SESSION_get0_hostname.pod
@@ -23,9 +23,10 @@ SSL_SESSION_set1_alpn_selected
 
 =head1 DESCRIPTION
 
-SSL_SESSION_get0_hostname() retrieves the SNI value that was sent by the
-client when the session was created if it was accepted by the server. Otherwise
-NULL is returned.
+SSL_SESSION_get0_hostname() retrieves the Server Name Indication (SNI) value
+that was sent by the client when the session was created if the server
+acknowledged the client's SNI extension by including an empty SNI extension
+in response. Otherwise NULL is returned.
 
 The value returned is a pointer to memory maintained within B<s> and
 should not be free'd.
@@ -44,8 +45,7 @@ B<alpn>.
 
 =head1 RETURN VALUES
 
-SSL_SESSION_get0_hostname() returns either a string or NULL based on if there
-is the SNI value sent by client.
+SSL_SESSION_get0_hostname() returns the SNI string if available, or NULL if not.
 
 SSL_SESSION_set1_hostname() returns 1 on success or 0 on error.
 
diff --git a/crypto/openssl/include/crypto/rsa.h b/crypto/openssl/include/crypto/rsa.h
index ffbc95a77888..55cc814ce913 100644
--- a/crypto/openssl/include/crypto/rsa.h
+++ b/crypto/openssl/include/crypto/rsa.h
@@ -124,10 +124,6 @@ ASN1_STRING *ossl_rsa_ctx_to_pss_string(EVP_PKEY_CTX *pkctx);
 int ossl_rsa_pss_to_ctx(EVP_MD_CTX *ctx, EVP_PKEY_CTX *pkctx,
                         const X509_ALGOR *sigalg, EVP_PKEY *pkey);
 
-# ifdef FIPS_MODULE
-int ossl_rsa_key_pairwise_test(RSA *rsa);
-# endif /* FIPS_MODULE */
-
 # if defined(FIPS_MODULE) && !defined(OPENSSL_NO_ACVP_TESTS)
 int ossl_rsa_acvp_test_gen_params_new(OSSL_PARAM **dst, const OSSL_PARAM src[]);
 void ossl_rsa_acvp_test_gen_params_free(OSSL_PARAM *dst);
diff --git a/crypto/openssl/include/openssl/opensslv.h.in b/crypto/openssl/include/openssl/opensslv.h.in
index e547281ff527..69b9caacf4dc 100644
--- a/crypto/openssl/include/openssl/opensslv.h.in
+++ b/crypto/openssl/include/openssl/opensslv.h.in
@@ -89,12 +89,12 @@ extern "C" {
 
 # define OPENSSL_VERSION_TEXT "OpenSSL {- "$config{full_version} $config{release_date}" -}"
 
-/* Synthesize OPENSSL_VERSION_NUMBER with the layout 0xMNN00PPSL */
+/* Synthesize OPENSSL_VERSION_NUMBER with the layout 0xMNN00PP0L */
 # define OPENSSL_VERSION_NUMBER          \
     ( (OPENSSL_VERSION_MAJOR<<28)        \
       |(OPENSSL_VERSION_MINOR<<20)       \
       |(OPENSSL_VERSION_PATCH<<4)        \
-      |{- @config{prerelease} ? "0x0L" : "0xfL" -} )
+      |0x0L )
 
 # ifdef  __cplusplus
 }
diff --git a/crypto/openssl/providers/fips-sources.checksums b/crypto/openssl/providers/fips-sources.checksums
index d48a9c85f57b..334b4ad6b7f2 100644
--- a/crypto/openssl/providers/fips-sources.checksums
+++ b/crypto/openssl/providers/fips-sources.checksums
@@ -250,7 +250,7 @@ c685813be6ad35b0861ba888670ef54aa2b399d003472698e39426de6e52db59  crypto/initthr
 f866aafae928db1b439ac950dc90744a2397dfe222672fe68b3798396190c8b0  crypto/mem_clr.c
 18127868d868ca5705444c24f7dc385391ba31154fc04ff54949739e8fa7fdfc  crypto/ml_dsa/ml_dsa_encoders.c
 825105b0a2c4844b2b4229001650ff7e61e1348e52f1072210f70b97cd4adb71  crypto/ml_dsa/ml_dsa_hash.h
-c82201cf1a17ff2d4b169dcd4402d3d56f4685e460a1447e021db4abd67f7f0e  crypto/ml_dsa/ml_dsa_key.c
+c467f4400d399aad6b51746ef2575d1e04d260a1bf901b35ca55624fe62e650e  crypto/ml_dsa/ml_dsa_key.c
 579c1a12a5c5f014476a6bf695dc271f63074fb187e23ffc3f9ccb5b7ea044f1  crypto/ml_dsa/ml_dsa_key.h
 3f98eb0467033d0a40867ef1c1036dcfea5d231eeac2321196f7d7c7243edace  crypto/ml_dsa/ml_dsa_key_compress.c
 983d164bfa3dbe8d85ad1fdc24d897e79d9246d96d9c1862855c6c538b387ad9  crypto/ml_dsa/ml_dsa_local.h
@@ -263,7 +263,7 @@ ff65c82c56e341f47df03d0c74de7fb537de0e68a4fa23fa07a9fdb51c511f1c  crypto/ml_dsa/
 1d7f57a41034988a4e7d4c9a998760d2ef802c5e90275d09a3ca31c5f3403d94  crypto/ml_dsa/ml_dsa_sign.c
 5217ef237e21872205703b95577290c34898423466a465c7bd609b2eb4627964  crypto/ml_dsa/ml_dsa_sign.h
 abd934284bcd8061027a69f437fa4410c6b72cd950be1ebe048244d036371208  crypto/ml_dsa/ml_dsa_vector.h
-defc2e4e81ff1b78056c795bc0565f4241a259c2957abe84a51bcbc1e4ace3f1  crypto/ml_kem/ml_kem.c
+8c4f7238f68f959f2ad1e2529c567364c5a8818898355c82818521e03239ea76  crypto/ml_kem/ml_kem.c
 36e24eae5d38cc9666ae40e4e8a2dc12328e1159fea68447cb19dab174d25adf  crypto/modes/asm/aes-gcm-armv8-unroll8_64.pl
 33357356cd739d4ae89d52f0804b6900e4b94d8829323819c6f64c8908e978df  crypto/modes/asm/aes-gcm-armv8_64.pl
 bcc09bdb474f045d04c983fa09c31a010c5a25513f53a5d3653ade91304f0f96  crypto/modes/asm/aes-gcm-avx512.pl
@@ -306,7 +306,7 @@ f50450f7e5f6896fb8e3cde2fdc11cc543124c854ef9d88252a166606ca80081  crypto/params_
 467c416422ecf61e3b713c5eb259fdbcb4aa73ae8dee61804d0b85cfd3fff4f7  crypto/property/defn_cache.c
 91c1f1f8eb5588ed9da17386c244ae68a6a81717b1c7ab6c9f1a6a57973a039f  crypto/property/property.c
 66da4f28d408133fb544b14aeb9ad4913e7c5c67e2826e53f0dc5bf4d8fada26  crypto/property/property_local.h
-d32105cb087d708d0504a787f74bc163cc398c299faf2e98d6bb5ae02f5ce9b7  crypto/property/property_parse.c
+1e99a3934812f99dad79cbfbb6727ad61b6093711c1a6c74d4b50f9318152611  crypto/property/property_parse.c
 a7cefda6a117550e2c76e0f307565ce1e11640b11ba10c80e469a837fd1212a3  crypto/property/property_query.c
 20e69b9d594dfc443075eddbb0e6bcc0ed36ca51993cd50cc5a4f86eb31127f8  crypto/property/property_string.c
 10644e9d20214660706de58d34edf635c110d4e4f2628cd5284a08c60ed9aff8  crypto/provider_core.c
@@ -322,7 +322,7 @@ f0c8792a99132e0b9c027cfa7370f45594a115934cdc9e8f23bdd64abecaf7fd  crypto/rsa/rsa
 1b828f428f0e78b591378f7b780164c4574620c68f9097de041cbd576f811bf6  crypto/rsa/rsa_backend.c
 38a102cd1da1f6ca5a46e6a22f018237964336274385f5c70cbedcaa6997647e  crypto/rsa/rsa_chk.c
 e762c599b17d5c89f4b1c9eb7d0ca1f04a95d815c86a3e72c30b231ce57fb199  crypto/rsa/rsa_crpt.c
-0fa3e4687510e2d91c8f4b1c460b1d51375d9855ed825b3d6697620b146b52d1  crypto/rsa/rsa_gen.c
+a3d20f27ae3cb41af5b62febd0bb19025e59d401b136306d570cdba103b15542  crypto/rsa/rsa_gen.c
 f22bc4e2c3acab83e67820c906c1caf048ec1f0d4fcb7472c1bec753c75f8e93  crypto/rsa/rsa_lib.c
 5ae8edaf654645996385fbd420ef73030762fc146bf41deb5294d6d83e257a16  crypto/rsa/rsa_local.h
 cf0b75cd54b61b9b9a290ef18d0ddce9fb26a029a54eb3f720d9b25188440f00  crypto/rsa/rsa_mp_names.c
@@ -416,7 +416,7 @@ a00e16963e1e2a0126c6a8e62da8a14f98de9736027654c925925dadd0ca3cc1  crypto/thread/
 27ec0090f4243c96e4fbe1babfd4320c2a16615ffa368275433217d50a1ef76c  crypto/thread/internal.c
 67ba8d87fbbb7c9a9e438018e7ecfd1cedd4d00224be05755580d044f5f1317a  crypto/threads_lib.c
 b1a828491d9ce305802662561788facac92dff70cca9ead807f3e28741ff21e0  crypto/threads_none.c
-c659f7ce5c4b59d2a1cff78485fa8e89c8d20d5798df4afc1b94ff635ffc0262  crypto/threads_pthread.c
+491e9c29d4a7b4dd627ea25c20ce4a33103565b3108b618c41c6816dfc675569  crypto/threads_pthread.c
 9c3bf7b4baa302a4017150fbcaa114ee9df935b18d5a3a8c8015003780d4e7de  crypto/threads_win.c
 7edd638df588b14711a50c98d458c4fc83f223ed03bc6c39c7c8edf7915b7cfa  crypto/time.c
 88c5f9f4d2611223d283ebd2ae10ae5ecbb9972d00f747d93fcb74b62641e3f9  crypto/x86_64cpuid.pl
@@ -445,7 +445,7 @@ bbe5e52d84e65449a13e42cd2d6adce59b8ed6e73d6950917aa77dc1f3f5dff6  include/crypto
 6e7762e7fb63f56d25b24f70209f4dc834c59a87f74467531ec81646f565dbe3  include/crypto/modes.h
 920bc48a4dad3712bdcef188c0ce8e8a8304e0ce332b54843bab366fc5eab472  include/crypto/rand.h
 71f23915ea74e93971fb0205901031be3abea7ffef2c52e4cc4848515079f68d  include/crypto/rand_pool.h
-b1df067691f9741ef9c42b2e5f12461bcd87b745514fc5701b9c9402fb10b224  include/crypto/rsa.h
+6f16685ffbc97dc2ac1240bfddf4bbac2dd1ad83fff6da91aee6f3f64c6ee8ff  include/crypto/rsa.h
 32f0149ab1d82fddbdfbbc44e3078b4a4cc6936d35187e0f8d02cc0bc19f2401  include/crypto/security_bits.h
 80338f3865b7c74aab343879432a6399507b834e2f55dd0e9ee7a5eeba11242a  include/crypto/sha.h
 dc7808729c3231a08bbe470b3e1b562420030f59f7bc05b14d7b516fa77b4f3a  include/crypto/slh_dsa.h
@@ -546,7 +546,7 @@ a8a45996fd21411cb7ed610bc202dbd06570cdfa0a2d14f7dfc8bfadc820e636  include/openss
 cb6bca3913c60a57bac39583eee0f789d49c3d29be3ecde9aecc7f3287117aa5  include/openssl/objects.h
 d25537af264684dff033dd8ae62b0348f868fcfec4aa51fa8f07bcfa4bd807ad  include/openssl/objectserr.h
 fe6acd42c3e90db31aaafc2236a7d30ebfa53c4c07ea4d8265064c7fcb951970  include/openssl/opensslconf.h
-fc914a750d798ac9fc9287e6359cfa1da214b91651deaaaa7e1a46b595cd0425  include/openssl/opensslv.h.in
+6c1a8837bbba633db2a8951ff29ccfe09e7d2a24a37ee2af90f2d897c190da9a  include/openssl/opensslv.h.in
 767d9d7d5051c937a3ce8a268c702902fda93eeaa210a94dfde1f45c23277d20  include/openssl/param_build.h
 1c442aaaa4dda7fbf727a451bc676fb4d855ef617c14dc77ff2a5e958ae33c3e  include/openssl/params.h
 44f178176293c6ce8142890ff9dc2d466364c734e4e811f56bd62010c5403183  include/openssl/pkcs7.h.in
@@ -618,8 +618,8 @@ f2581d7b4e105f2bb6d30908f3c2d9959313be08cec6dbeb49030c125a7676d3  providers/fips
 669f76f742bcaaf28846b057bfab97da7c162d69da244de71b7c743bf16e430f  providers/fips/include/fipscommon.h
 f111fd7e016af8cc6f96cd8059c28227b328dd466ed137ae0c0bc0c3c3eec3ba  providers/fips/self_test.c
 5c2c6c2f69e2eb01b88fa35630f27948e00dd2c2fd351735c74f34ccb2005cbe  providers/fips/self_test.h
-663441de9aba1d1b81ce02b3acded520b88cc460330d4d98adb7450d9664c474  providers/fips/self_test_data.inc
-2e568e2b161131240e97bd77a730c2299f961c2f1409ea8466422fc07f9be23f  providers/fips/self_test_kats.c
+df83c901ad13675fbbb4708b6087feba6099870ad3dd0e8d09cfdb6798419770  providers/fips/self_test_data.inc
+6779d5afb3f48d82868b247ffb0a6a572f6e3964738296ad47e7ccafdb263c88  providers/fips/self_test_kats.c
 dde79dfdedfe0e73006a0cf912fdde1ff109dfbc5ba6ecab319c938bc4275950  providers/implementations/asymciphers/rsa_enc.c
 c2f1b12c64fc369dfc3b9bc9e76a76de7280e6429adaee55d332eb1971ad1879  providers/implementations/ciphers/cipher_aes.c
 6ba7d817081cf0d87ba7bfb38cd9d70e41505480bb8bc796ef896f68d4514ea6  providers/implementations/ciphers/cipher_aes.h
@@ -699,7 +699,7 @@ c764555b9dc9b273c280514a5d2d44156f82f3e99155a77c627f2c773209bcd7  providers/impl
 24cc3cc8e8681c77b7f96c83293bd66045fd8ad69f756e673ca7f8ca9e82b0af  providers/implementations/keymgmt/dsa_kmgmt.c
 36a9c1c8658ce7918453827cb58ed52787e590e3f148c5510deeb2c16c25a29d  providers/implementations/keymgmt/ec_kmgmt.c
 258ae17bb2dd87ed1511a8eb3fe99eed9b77f5c2f757215ff6b3d0e8791fc251  providers/implementations/keymgmt/ec_kmgmt_imexport.inc
-9728d696d249b2d224724c9872138a60e1998e5cfa5c49f3f48ad0666f7eed34  providers/implementations/keymgmt/ecx_kmgmt.c
+11c27cc3c9f38885c484f25d11987e93f197aa90bef2fc1d6e8f508c2d014d4d  providers/implementations/keymgmt/ecx_kmgmt.c
 daf35a7ab961ef70aefca981d80407935904c5da39dca6692432d6e6bc98759d  providers/implementations/keymgmt/kdf_legacy_kmgmt.c
 d97d7c8d3410b3e560ef2becaea2a47948e22205be5162f964c5e51a7eef08cb  providers/implementations/keymgmt/mac_legacy_kmgmt.c
 a428de71082fd01e5dcfa030a6fc34f6700b86d037b4e22f015c917862a158ce  providers/implementations/keymgmt/ml_dsa_kmgmt.c
diff --git a/crypto/openssl/providers/fips.checksum b/crypto/openssl/providers/fips.checksum
index 7fa4ea19bba3..5d1117361d27 100644
--- a/crypto/openssl/providers/fips.checksum
+++ b/crypto/openssl/providers/fips.checksum
@@ -1 +1 @@
-8d0c2c2b986f4c98f511c9aa020e98aa984dce5976d8e1966a7721f8b559cda8  providers/fips-sources.checksums
+c342f9dc7075a6ecd0e4b3c9db06e180765278a7bbae233ec1a65095a0e524ec  providers/fips-sources.checksums
diff --git a/crypto/openssl/providers/fips/self_test_data.inc b/crypto/openssl/providers/fips/self_test_data.inc
index b6aa433ca93c..6abab0a7a173 100644
--- a/crypto/openssl/providers/fips/self_test_data.inc
+++ b/crypto/openssl/providers/fips/self_test_data.inc
@@ -1308,6 +1308,18 @@ static const ST_KAT_PARAM rsa_priv_key[] = {
     ST_KAT_PARAM_END()
 };
 
+/*-
+ * Using OSSL_PKEY_RSA_PAD_MODE_NONE directly in the expansion of the
+ * ST_KAT_PARAM_UTF8STRING macro below causes a failure on ancient
+ * HP/UX PA-RISC compilers.
+ */
+static const char pad_mode_none[] = OSSL_PKEY_RSA_PAD_MODE_NONE;
+
+static const ST_KAT_PARAM rsa_enc_params[] = {
+    ST_KAT_PARAM_UTF8STRING(OSSL_ASYM_CIPHER_PARAM_PAD_MODE, pad_mode_none),
+    ST_KAT_PARAM_END()
+};
+
 static const unsigned char rsa_sig_msg[] = "Hello World!";
 
 static const unsigned char rsa_expected_sig[256] = {
@@ -3497,3 +3509,33 @@ static const ST_KAT_ASYM_KEYGEN st_kat_asym_keygen_tests[] = {
 # endif
 };
 #endif /* !OPENSSL_NO_ML_DSA || !OPENSSL_NO_SLH_DSA */
+
+static const ST_KAT_ASYM_CIPHER st_kat_asym_cipher_tests[] = {
+    {
+        OSSL_SELF_TEST_DESC_ASYM_RSA_ENC,
+        "RSA",
+        1,
+        rsa_pub_key,
+        rsa_enc_params,
+        ITM(rsa_asym_plaintext_encrypt),
+        ITM(rsa_asym_expected_encrypt),
+    },
+    {
+        OSSL_SELF_TEST_DESC_ASYM_RSA_DEC,
+        "RSA",
+        0,
+        rsa_priv_key,
+        rsa_enc_params,
+        ITM(rsa_asym_expected_encrypt),
+        ITM(rsa_asym_plaintext_encrypt),
+    },
+    {
+        OSSL_SELF_TEST_DESC_ASYM_RSA_DEC,
+        "RSA",
+        0,
+        rsa_crt_key,
+        rsa_enc_params,
+        ITM(rsa_asym_expected_encrypt),
+        ITM(rsa_asym_plaintext_encrypt),
+    },
+};
diff --git a/crypto/openssl/providers/fips/self_test_kats.c b/crypto/openssl/providers/fips/self_test_kats.c
index 35ecb43598ee..acb0b85f7343 100644
--- a/crypto/openssl/providers/fips/self_test_kats.c
+++ b/crypto/openssl/providers/fips/self_test_kats.c
@@ -813,6 +813,93 @@ err:
 #endif
 
 /*
+ * Test an encrypt or decrypt KAT..
+ *
+ * FIPS 140-2 IG D.9 states that separate KAT tests are needed for encrypt
+ * and decrypt..
+ */
+static int self_test_asym_cipher(const ST_KAT_ASYM_CIPHER *t, OSSL_SELF_TEST *st,
+                                 OSSL_LIB_CTX *libctx)
+{
+    int ret = 0;
+    OSSL_PARAM *keyparams = NULL, *initparams = NULL;
+    OSSL_PARAM_BLD *keybld = NULL, *initbld = NULL;
+    EVP_PKEY_CTX *encctx = NULL, *keyctx = NULL;
+    EVP_PKEY *key = NULL;
+    BN_CTX *bnctx = NULL;
+    unsigned char out[256];
+    size_t outlen = sizeof(out);
+
+    OSSL_SELF_TEST_onbegin(st, OSSL_SELF_TEST_TYPE_KAT_ASYM_CIPHER, t->desc);
+
+    bnctx = BN_CTX_new_ex(libctx);
+    if (bnctx == NULL)
+        goto err;
+
+    /* Load a public or private key from data */
+    keybld = OSSL_PARAM_BLD_new();
+    if (keybld == NULL
+        || !add_params(keybld, t->key, bnctx))
+        goto err;
+    keyparams = OSSL_PARAM_BLD_to_param(keybld);
+    keyctx = EVP_PKEY_CTX_new_from_name(libctx, t->algorithm, NULL);
+    if (keyctx == NULL || keyparams == NULL)
+        goto err;
+    if (EVP_PKEY_fromdata_init(keyctx) <= 0
+        || EVP_PKEY_fromdata(keyctx, &key, EVP_PKEY_KEYPAIR, keyparams) <= 0)
+        goto err;
+
+    /* Create a EVP_PKEY_CTX to use for the encrypt or decrypt operation */
+    encctx = EVP_PKEY_CTX_new_from_pkey(libctx, key, NULL);
+    if (encctx == NULL
+        || (t->encrypt && EVP_PKEY_encrypt_init(encctx) <= 0)
+        || (!t->encrypt && EVP_PKEY_decrypt_init(encctx) <= 0))
+        goto err;
+
+    /* Add any additional parameters such as padding */
+    if (t->postinit != NULL) {
+        initbld = OSSL_PARAM_BLD_new();
+        if (initbld == NULL)
+            goto err;
+        if (!add_params(initbld, t->postinit, bnctx))
+            goto err;
+        initparams = OSSL_PARAM_BLD_to_param(initbld);
+        if (initparams == NULL)
+            goto err;
+        if (EVP_PKEY_CTX_set_params(encctx, initparams) <= 0)
+            goto err;
+    }
+
+    if (t->encrypt) {
+        if (EVP_PKEY_encrypt(encctx, out, &outlen,
+                             t->in, t->in_len) <= 0)
+            goto err;
+    } else {
+        if (EVP_PKEY_decrypt(encctx, out, &outlen,
+                             t->in, t->in_len) <= 0)
+            goto err;
+    }
+    /* Check the KAT */
+    OSSL_SELF_TEST_oncorrupt_byte(st, out);
+    if (outlen != t->expected_len
+        || memcmp(out, t->expected, t->expected_len) != 0)
+        goto err;
+
+    ret = 1;
+err:
+    BN_CTX_free(bnctx);
+    EVP_PKEY_free(key);
+    EVP_PKEY_CTX_free(encctx);
+    EVP_PKEY_CTX_free(keyctx);
+    OSSL_PARAM_free(keyparams);
+    OSSL_PARAM_BLD_free(keybld);
+    OSSL_PARAM_free(initparams);
+    OSSL_PARAM_BLD_free(initbld);
+    OSSL_SELF_TEST_onend(st, ret);
+    return ret;
+}
+
+/*
  * Test a data driven list of KAT's for digest algorithms.
  * All tests are run regardless of if they fail or not.
  * Return 0 if any test fails.
@@ -853,6 +940,17 @@ static int self_test_kems(OSSL_SELF_TEST *st, OSSL_LIB_CTX *libctx)
     return ret;
 }
 
+static int self_test_asym_ciphers(OSSL_SELF_TEST *st, OSSL_LIB_CTX *libctx)
+{
+    int i, ret = 1;
+
+    for (i = 0; i < (int)OSSL_NELEM(st_kat_asym_cipher_tests); ++i) {
+        if (!self_test_asym_cipher(&st_kat_asym_cipher_tests[i], st, libctx))
+            ret = 0;
+    }
+    return ret;
+}
+
 static int self_test_kdfs(OSSL_SELF_TEST *st, OSSL_LIB_CTX *libctx)
 {
     int i, ret = 1;
@@ -1092,6 +1190,8 @@ int SELF_TEST_kats(OSSL_SELF_TEST *st, OSSL_LIB_CTX *libctx)
         ret = 0;
     if (!self_test_kems(st, libctx))
         ret = 0;
+    if (!self_test_asym_ciphers(st, libctx))
+        ret = 0;
 
     RAND_set0_private(libctx, saved_rand);
     return ret;
diff --git a/crypto/openssl/providers/implementations/kdfs/krb5kdf.c b/crypto/openssl/providers/implementations/kdfs/krb5kdf.c
index 566afa74fece..13623ec7302e 100644
--- a/crypto/openssl/providers/implementations/kdfs/krb5kdf.c
+++ b/crypto/openssl/providers/implementations/kdfs/krb5kdf.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2024 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 2018-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -350,7 +350,7 @@ static int cipher_init(EVP_CIPHER_CTX *ctx,
 {
     int klen, ret;
 
-    ret = EVP_EncryptInit_ex(ctx, cipher, engine, key, NULL);
+    ret = EVP_EncryptInit_ex(ctx, cipher, engine, NULL, NULL);
     if (!ret)
         goto out;
     /* set the key len for the odd variable key len cipher */
@@ -362,6 +362,9 @@ static int cipher_init(EVP_CIPHER_CTX *ctx,
             goto out;
         }
     }
+    ret = EVP_EncryptInit_ex(ctx, NULL, NULL, key, NULL);
+    if (!ret)
+        goto out;
     /* we never want padding, either the length requested is a multiple of
      * the cipher block size or we are passed a cipher that can cope with
      * partial blocks via techniques like cipher text stealing */
diff --git a/crypto/openssl/providers/implementations/keymgmt/ecx_kmgmt.c b/crypto/openssl/providers/implementations/keymgmt/ecx_kmgmt.c
index e6d326a90705..0ebe8b4d59b1 100644
--- a/crypto/openssl/providers/implementations/keymgmt/ecx_kmgmt.c
+++ b/crypto/openssl/providers/implementations/keymgmt/ecx_kmgmt.c
@@ -218,14 +218,6 @@ static int ecx_import(void *keydata, int selection, const OSSL_PARAM params[])
     include_private = selection & OSSL_KEYMGMT_SELECT_PRIVATE_KEY ? 1 : 0;
     ok = ok && ossl_ecx_key_fromdata(key, params, include_private);
 
-#ifdef FIPS_MODULE
-    if (ok > 0 && ecx_key_type_is_ed(key->type) && !ossl_fips_self_testing())
-        if (key->haspubkey && key->privkey != NULL) {
-            ok = ecd_fips140_pairwise_test(key, key->type, 1);
-            if (ok <= 0)
-                ossl_set_error_state(OSSL_SELF_TEST_TYPE_PCT_IMPORT);
-        }
-#endif  /* FIPS_MODULE */
     return ok;
 }
 
diff --git a/crypto/openssl/ssl/quic/quic_impl.c b/crypto/openssl/ssl/quic/quic_impl.c
index c44e6b33c2a8..cec05d5bd37b 100644
--- a/crypto/openssl/ssl/quic/quic_impl.c
+++ b/crypto/openssl/ssl/quic/quic_impl.c
@@ -3197,6 +3197,7 @@ int ossl_quic_conn_stream_conclude(SSL *s)
     QCTX ctx;
     QUIC_STREAM *qs;
     int err;
+    int ret;
 
     if (!expect_quic_with_stream_lock(s, /*remote_init=*/0, /*io=*/0, &ctx))
         return 0;
@@ -3204,13 +3205,15 @@ int ossl_quic_conn_stream_conclude(SSL *s)
     qs = ctx.xso->stream;
 
     if (!quic_mutation_allowed(ctx.qc, /*req_active=*/1)) {
+        ret = QUIC_RAISE_NON_NORMAL_ERROR(&ctx, SSL_R_PROTOCOL_IS_SHUTDOWN, NULL);
         qctx_unlock(&ctx);
-        return QUIC_RAISE_NON_NORMAL_ERROR(&ctx, SSL_R_PROTOCOL_IS_SHUTDOWN, NULL);
+        return ret;
     }
 
     if (!quic_validate_for_write(ctx.xso, &err)) {
+        ret = QUIC_RAISE_NON_NORMAL_ERROR(&ctx, err, NULL);
         qctx_unlock(&ctx);
-        return QUIC_RAISE_NON_NORMAL_ERROR(&ctx, err, NULL);
+        return ret;
     }
 
     if (ossl_quic_sstream_get_final_size(qs->sstream, NULL)) {
diff --git a/crypto/openssl/ssl/record/methods/tls_common.c b/crypto/openssl/ssl/record/methods/tls_common.c
index 80d4477bd0c0..b9c79099462d 100644
--- a/crypto/openssl/ssl/record/methods/tls_common.c
+++ b/crypto/openssl/ssl/record/methods/tls_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 2022-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -1093,9 +1093,12 @@ int tls13_common_post_process_record(OSSL_RECORD_LAYER *rl, TLS_RL_RECORD *rec)
         return 0;
     }
 
-    if (rl->msg_callback != NULL)
-        rl->msg_callback(0, rl->version, SSL3_RT_INNER_CONTENT_TYPE, &rec->type,
-                        1, rl->cbarg);
+    if (rl->msg_callback != NULL) {
+        unsigned char ctype = (unsigned char)rec->type;
+
+        rl->msg_callback(0, rl->version, SSL3_RT_INNER_CONTENT_TYPE, &ctype,
+                         1, rl->cbarg);
+    }
 
     /*
      * TLSv1.3 alert and handshake records are required to be non-zero in
diff --git a/crypto/openssl/ssl/ssl_rsa.c b/crypto/openssl/ssl/ssl_rsa.c
index e833bcdbc377..f4731a87af90 100644
--- a/crypto/openssl/ssl/ssl_rsa.c
+++ b/crypto/openssl/ssl/ssl_rsa.c
@@ -1056,10 +1056,13 @@ static int ssl_set_cert_and_key(SSL *ssl, SSL_CTX *ctx, X509 *x509, EVP_PKEY *pr
         }
     }
 
-    if (!X509_up_ref(x509))
+    if (!X509_up_ref(x509)) {
+        OSSL_STACK_OF_X509_free(dup_chain);
         goto out;
+    }
 
     if (!EVP_PKEY_up_ref(privatekey)) {
+        OSSL_STACK_OF_X509_free(dup_chain);
         X509_free(x509);
         goto out;
     }
diff --git a/crypto/openssl/ssl/t1_trce.c b/crypto/openssl/ssl/t1_trce.c
index 35c60feb4371..73fd4ebaa4b0 100644
--- a/crypto/openssl/ssl/t1_trce.c
+++ b/crypto/openssl/ssl/t1_trce.c
@@ -549,8 +549,12 @@ static const ssl_trace_tbl ssl_groups_tbl[] = {
     {258, "ffdhe4096"},
     {259, "ffdhe6144"},
     {260, "ffdhe8192"},
+    {512, "MLKEM512"},
+    {513, "MLKEM768"},
+    {514, "MLKEM1024"},
     {4587, "SecP256r1MLKEM768"},
     {4588, "X25519MLKEM768"},
+    {4589, "SecP384r1MLKEM1024"},
     {25497, "X25519Kyber768Draft00"},
     {25498, "SecP256r1Kyber768Draft00"},
     {0xFF01, "arbitrary_explicit_prime_curves"},
diff --git a/crypto/openssl/test/build.info b/crypto/openssl/test/build.info
index 9d9be6b642e9..3dca6117796b 100644
--- a/crypto/openssl/test/build.info
+++ b/crypto/openssl/test/build.info
@@ -31,7 +31,8 @@ IF[{- !$disabled{tests} -}]
           testutil/format_output.c testutil/load.c testutil/fake_random.c \
           testutil/test_cleanup.c testutil/main.c testutil/testutil_init.c \
           testutil/options.c testutil/test_options.c testutil/provider.c \
-          testutil/apps_shims.c testutil/random.c testutil/helper.c $LIBAPPSSRC
+          testutil/apps_shims.c testutil/random.c testutil/helper.c \
+          testutil/compare.c $LIBAPPSSRC
   INCLUDE[libtestutil.a]=../include ../apps/include ..
   DEPEND[libtestutil.a]=../libcrypto
 
diff --git a/crypto/openssl/test/fake_rsaprov.c b/crypto/openssl/test/fake_rsaprov.c
index 46fc9104ef95..6ed121554336 100644
--- a/crypto/openssl/test/fake_rsaprov.c
+++ b/crypto/openssl/test/fake_rsaprov.c
@@ -35,6 +35,8 @@ static int exptypes_selection;
 static int query_id;
 static int key_deleted;
 
+unsigned fake_rsa_query_operation_name = 0;
+
 typedef struct {
     OSSL_LIB_CTX *libctx;
 } PROV_FAKE_RSA_CTX;
@@ -90,7 +92,7 @@ static const char *fake_rsa_keymgmt_query(int id)
     /* record global for checking */
     query_id = id;
 
-    return "RSA";
+    return fake_rsa_query_operation_name ? NULL: "RSA";
 }
 
 static int fake_rsa_keymgmt_import(void *keydata, int selection,
diff --git a/crypto/openssl/test/fake_rsaprov.h b/crypto/openssl/test/fake_rsaprov.h
index cb2e66eb68ef..00e7dccb4872 100644
--- a/crypto/openssl/test/fake_rsaprov.h
+++ b/crypto/openssl/test/fake_rsaprov.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 2021-2025 The OpenSSL Project Authors. All Rights Reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
  * this file except in compliance with the License.  You can obtain a copy
@@ -14,5 +14,14 @@
 /* Fake RSA provider implementation */
 OSSL_PROVIDER *fake_rsa_start(OSSL_LIB_CTX *libctx);
 void fake_rsa_finish(OSSL_PROVIDER *p);
+
 OSSL_PARAM *fake_rsa_key_params(int priv);
 void fake_rsa_restore_store_state(void);
+
+/*
+ * When fake_rsa_query_operation_name is set to a non-zero value,
+ * query_operation_name() will return NULL.
+ *
+ * By default, it is 0, in which case query_operation_name() will return "RSA".
+ */
+extern unsigned fake_rsa_query_operation_name;
diff --git a/crypto/openssl/test/ml_kem_evp_extra_test.c b/crypto/openssl/test/ml_kem_evp_extra_test.c
index bfa52c9af2e6..b867b14ad1d4 100644
--- a/crypto/openssl/test/ml_kem_evp_extra_test.c
+++ b/crypto/openssl/test/ml_kem_evp_extra_test.c
@@ -140,9 +140,19 @@ static int test_ml_kem(void)
     if (!TEST_int_gt(EVP_PKEY_copy_parameters(bkey, akey), 0))
         goto err;
 
+    /* Bob's empty key is not equal to Alice's */
+    if (!TEST_false(EVP_PKEY_eq(akey, bkey))
+        || !TEST_false(EVP_PKEY_eq(bkey, akey)))
+        goto err;
+
     if (!TEST_true(EVP_PKEY_set1_encoded_public_key(bkey, rawpub, publen)))
         goto err;
 
+    /* Bob's copy of Alice's public key makes the two equal */
+    if (!TEST_true(EVP_PKEY_eq(akey, bkey))
+        || !TEST_true(EVP_PKEY_eq(bkey, akey)))
+        goto err;
+
     /* Encapsulate Bob's key */
     ctx = EVP_PKEY_CTX_new_from_pkey(testctx, bkey, NULL);
     if (!TEST_ptr(ctx))
diff --git a/crypto/openssl/test/property_test.c b/crypto/openssl/test/property_test.c
index 18f8cc8740e0..e62ff247c42c 100644
--- a/crypto/openssl/test/property_test.c
+++ b/crypto/openssl/test/property_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019-2023 The OpenSSL Project Authors. All Rights Reserved.
+ * Copyright 2019-2025 The OpenSSL Project Authors. All Rights Reserved.
  * Copyright (c) 2019, Oracle and/or its affiliates.  All rights reserved.
  *
  * Licensed under the Apache License 2.0 (the "License").  You may not use
@@ -687,6 +687,22 @@ static int test_property_list_to_string(int i)
     return ret;
 }
 
+static int test_property_list_to_string_bounds(void)
+{
+    OSSL_PROPERTY_LIST *pl = NULL;
+    char buf[16];
+    int ret = 0;
+
+    if (!TEST_ptr(pl = ossl_parse_query(NULL, "provider='$1'", 1)))
+        goto err;
+    if (!TEST_size_t_eq(ossl_property_list_to_string(NULL, pl, buf, 10), 14))
+        goto err;
+    ret = 1;
+ err:
+    ossl_property_free(pl);
+    return ret;
+}
+
 int setup_tests(void)
 {
     ADD_TEST(test_property_string);
@@ -701,5 +717,6 @@ int setup_tests(void)
     ADD_TEST(test_query_cache_stochastic);
     ADD_TEST(test_fips_mode);
     ADD_ALL_TESTS(test_property_list_to_string, OSSL_NELEM(to_string_tests));
+    ADD_TEST(test_property_list_to_string_bounds);
     return 1;
 }
diff --git a/crypto/openssl/test/provider_pkey_test.c b/crypto/openssl/test/provider_pkey_test.c
index cb656a62a650..9ffe3581d62a 100644
--- a/crypto/openssl/test/provider_pkey_test.c
+++ b/crypto/openssl/test/provider_pkey_test.c
@@ -239,6 +239,77 @@ end:
     return ret;
 }
 
+static int test_pkey_can_sign(void)
+{
+    OSSL_PROVIDER *fake_rsa = NULL;
+    EVP_PKEY *pkey_fake = NULL;
+    EVP_PKEY_CTX *ctx = NULL;
+    OSSL_PARAM *params = NULL;
+    int ret = 0;
+
+    if (!TEST_ptr(fake_rsa = fake_rsa_start(libctx)))
+        return 0;
+
+    /*
+     * Ensure other tests did not forget to reset fake_rsa_query_operation_name
+     * to its default value: 0
+     */
+    if (!TEST_int_eq(fake_rsa_query_operation_name, 0))
+        goto end;
+
+    if (!TEST_ptr(params = fake_rsa_key_params(0))
+        || !TEST_ptr(ctx = EVP_PKEY_CTX_new_from_name(libctx, "RSA",
+                                                      "provider=fake-rsa"))
+        || !TEST_true(EVP_PKEY_fromdata_init(ctx))
+        || !TEST_true(EVP_PKEY_fromdata(ctx, &pkey_fake, EVP_PKEY_PUBLIC_KEY,
+                                        params))
+        || !TEST_true(EVP_PKEY_can_sign(pkey_fake))
+        || !TEST_ptr(pkey_fake))
+        goto end;
+
+    EVP_PKEY_CTX_free(ctx);
+    ctx = NULL;
+    EVP_PKEY_free(pkey_fake);
+    pkey_fake = NULL;
+    OSSL_PARAM_free(params);
+    params = NULL;
+
+    /*
+     * Documented behavior for OSSL_FUNC_keymgmt_query_operation_name()
+     * allows it to return NULL, in which case the fallback should be to use
+     * EVP_KEYMGMT_get0_name(). That is exactly the thing we are testing here.
+     */
+    fake_rsa_query_operation_name = 1;
+
+    if (!TEST_ptr(params = fake_rsa_key_params(0))
+        || !TEST_ptr(ctx = EVP_PKEY_CTX_new_from_name(libctx, "RSA",
+                                                      "provider=fake-rsa"))
+        || !TEST_true(EVP_PKEY_fromdata_init(ctx))
+        || !TEST_true(EVP_PKEY_fromdata(ctx, &pkey_fake, EVP_PKEY_PUBLIC_KEY,
+                                        params))
+        || !TEST_true(EVP_PKEY_can_sign(pkey_fake))
+        || !TEST_ptr(pkey_fake))
+        goto end;
+
+    EVP_PKEY_CTX_free(ctx);
+    ctx = NULL;
+    EVP_PKEY_free(pkey_fake);
+    pkey_fake = NULL;
+    OSSL_PARAM_free(params);
+    params = NULL;
+
+    ret = 1;
+end:
+
+    EVP_PKEY_CTX_free(ctx);
+    EVP_PKEY_free(pkey_fake);
+    OSSL_PARAM_free(params);
+    fake_rsa_query_operation_name = 0;
+
+    fake_rsa_finish(fake_rsa);
+    return ret;
+}
+
 static int test_pkey_store(int idx)
 {
     OSSL_PROVIDER *deflt = NULL;
@@ -719,6 +790,7 @@ int setup_tests(void)
     ADD_TEST(test_pkey_sig);
     ADD_TEST(test_alternative_keygen_init);
     ADD_TEST(test_pkey_eq);
+    ADD_TEST(test_pkey_can_sign);
     ADD_ALL_TESTS(test_pkey_store, 2);
     ADD_TEST(test_pkey_delete);
     ADD_TEST(test_pkey_store_open_ex);
diff --git a/crypto/openssl/test/quicapitest.c b/crypto/openssl/test/quicapitest.c
index f665c511bb72..4e887c13d14c 100644
--- a/crypto/openssl/test/quicapitest.c
+++ b/crypto/openssl/test/quicapitest.c
@@ -428,91 +428,6 @@ static int test_version(void)
 }
 
 #if defined(DO_SSL_TRACE_TEST)
-static void strip_line_ends(char *str)
-{
-    size_t i;
-
-    for (i = strlen(str);
-         i > 0 && (str[i - 1] == '\n' || str[i - 1] == '\r');
-         i--);
-
-    str[i] = '\0';
-}
-
-static int compare_with_file(BIO *membio)
-{
-    BIO *file = NULL, *newfile = NULL;
-    char buf1[8192], buf2[8192];
-    char *reffile;
-    int ret = 0;
-    size_t i;
-
-#ifdef OPENSSL_NO_ZLIB
-    reffile = test_mk_file_path(datadir, "ssltraceref.txt");
-#else
-    reffile = test_mk_file_path(datadir, "ssltraceref-zlib.txt");
-#endif
-    if (!TEST_ptr(reffile))
-        goto err;
-
-    file = BIO_new_file(reffile, "rb");
-    if (!TEST_ptr(file))
-        goto err;
-
-    newfile = BIO_new_file("ssltraceref-new.txt", "wb");
-    if (!TEST_ptr(newfile))
-        goto err;
-
-    while (BIO_gets(membio, buf2, sizeof(buf2)) > 0)
-        if (BIO_puts(newfile, buf2) <= 0) {
-            TEST_error("Failed writing new file data");
-            goto err;
-        }
-
-    if (!TEST_int_ge(BIO_seek(membio, 0), 0))
-        goto err;
-
-    while (BIO_gets(file, buf1, sizeof(buf1)) > 0) {
-        size_t line_len;
-
-        if (BIO_gets(membio, buf2, sizeof(buf2)) <= 0) {
-            TEST_error("Failed reading mem data");
-            goto err;
-        }
-        strip_line_ends(buf1);
-        strip_line_ends(buf2);
-        line_len = strlen(buf1);
-        if (line_len > 0 && buf1[line_len - 1] == '?') {
-            /* Wildcard at the EOL means ignore anything after it */
-            if (strlen(buf2) > line_len)
-                buf2[line_len] = '\0';
-        }
-        if (line_len != strlen(buf2)) {
-            TEST_error("Actual and ref line data length mismatch");
-            TEST_info("%s", buf1);
-            TEST_info("%s", buf2);
-           goto err;
-        }
-        for (i = 0; i < line_len; i++) {
-            /* '?' is a wild card character in the reference text */
-            if (buf1[i] == '?')
-                buf2[i] = '?';
-        }
-        if (!TEST_str_eq(buf1, buf2))
-            goto err;
-    }
-    if (!TEST_true(BIO_eof(file))
-            || !TEST_true(BIO_eof(membio)))
-        goto err;
-
-    ret = 1;
- err:
-    OPENSSL_free(reffile);
-    BIO_free(file);
-    BIO_free(newfile);
-    return ret;
-}
-
 /*
  * Tests that the SSL_trace() msg_callback works as expected with a QUIC
  * connection. This also provides testing of the msg_callback at the same time.
@@ -524,6 +439,7 @@ static int test_ssl_trace(void)
     QUIC_TSERVER *qtserv = NULL;
     int testresult = 0;
     BIO *bio = NULL;
+    char *reffile = NULL;
 
     if (!TEST_ptr(cctx = SSL_CTX_new_ex(libctx, NULL, OSSL_QUIC_client_method()))
             || !TEST_ptr(bio = BIO_new(BIO_s_mem()))
@@ -547,7 +463,13 @@ static int test_ssl_trace(void)
         if (!TEST_int_gt(BIO_pending(bio), 0))
             goto err;
     } else {
-        if (!TEST_true(compare_with_file(bio)))
+
+# ifdef OPENSSL_NO_ZLIB
+        reffile = test_mk_file_path(datadir, "ssltraceref.txt");
+# else
+        reffile = test_mk_file_path(datadir, "ssltraceref-zlib.txt");
+# endif
+        if (!TEST_true(compare_with_reference_file(bio, reffile)))
             goto err;
     }
 
@@ -557,6 +479,7 @@ static int test_ssl_trace(void)
     SSL_free(clientquic);
     SSL_CTX_free(cctx);
     BIO_free(bio);
+    OPENSSL_free(reffile);
 
     return testresult;
 }
diff --git a/crypto/openssl/test/radix/terp.c b/crypto/openssl/test/radix/terp.c
index 3c83fd9b18b0..41d3bdeb9fd4 100644
--- a/crypto/openssl/test/radix/terp.c
+++ b/crypto/openssl/test/radix/terp.c
@@ -871,8 +871,10 @@ err:
     }
 
     GEN_SCRIPT_cleanup(&gen_script);
-    BIO_printf(debug_bio, "Stats:\n  Ops executed: %16llu\n\n",
-               (unsigned long long)terp.ops_executed);
+    if (have_terp) {
+        BIO_printf(debug_bio, "Stats:\n  Ops executed: %16llu\n\n",
+                   (unsigned long long)terp.ops_executed);
+    }
     SCRIPT_INFO_print(script_info, debug_bio, /*error=*/!ok,
                       ok ? "completed" : "failed, exiting");
     return ok;
diff --git a/crypto/openssl/test/recipes/03-test_fipsinstall.t b/crypto/openssl/test/recipes/03-test_fipsinstall.t
index 1f9110ef600a..3dcbe67c6d55 100644
--- a/crypto/openssl/test/recipes/03-test_fipsinstall.t
+++ b/crypto/openssl/test/recipes/03-test_fipsinstall.t
@@ -63,7 +63,7 @@ my @commandline =
         ( 'x942kdf_key_check',              'x942kdf-key-check' )
     );
 
-plan tests => 40 + (scalar @pedantic_okay) + (scalar @pedantic_fail)
+plan tests => 41 + (scalar @pedantic_okay) + (scalar @pedantic_fail)
               + 4 * (scalar @commandline);
 
 my $infile = bldtop_file('providers', platform->dso('fips'));
@@ -392,6 +392,16 @@ SKIP: {
        "fipsinstall fails when the ML-KEM decapsulate implicit failure result is corrupted");
 }
 
+# corrupt an Asymmetric cipher test
+SKIP: {
+    skip "Skipping Asymmetric RSA corruption test because of no rsa in this build", 1
+        if disabled("rsa") || disabled("fips-post");
+    ok(!run(app(['openssl', 'fipsinstall', '-out', 'fips.cnf', '-module', $infile,
+                '-corrupt_desc', 'RSA_Encrypt',
+                '-corrupt_type', 'KAT_AsymmetricCipher'])),
+       "fipsinstall fails when the asymmetric cipher result is corrupted");
+}
+
 # 'local' ensures that this change is only done in this file.
 local $ENV{OPENSSL_CONF_INCLUDE} = abs2rel(curdir());
 
diff --git a/crypto/openssl/test/recipes/25-test_verify.t b/crypto/openssl/test/recipes/25-test_verify.t
index 271f499690bf..673c3d5f1772 100644
--- a/crypto/openssl/test/recipes/25-test_verify.t
+++ b/crypto/openssl/test/recipes/25-test_verify.t
@@ -602,9 +602,10 @@ ok(vfy_root("-CAfile", $rootcert), "CAfile");
 ok(vfy_root("-CAstore", $rootcert), "CAstore");
 ok(vfy_root("-CAstore", $rootcert, "-CAfile", $rootcert), "CAfile and existing CAstore");
 ok(!vfy_root("-CAstore", "non-existing", "-CAfile", $rootcert), "CAfile and non-existing CAstore");
+
 SKIP: {
-    skip "file names with colons aren't supported on Windows and VMS", 2
-        if $^O =~ /^(MsWin32|VMS)$/;
+    skip "file names with colons aren't supported on Windows and VMS", 1
+        if $^O =~ /^(MSWin32|VMS)$/;
     my $foo_file = "foo:cert.pem";
     copy($rootcert, $foo_file);
     ok(vfy_root("-CAstore", $foo_file), "CAstore foo:file");
diff --git a/crypto/openssl/test/recipes/30-test_evp_data/evpkdf_krb5.txt b/crypto/openssl/test/recipes/30-test_evp_data/evpkdf_krb5.txt
index d8f6aa72a175..e2de4754fa74 100644
--- a/crypto/openssl/test/recipes/30-test_evp_data/evpkdf_krb5.txt
+++ b/crypto/openssl/test/recipes/30-test_evp_data/evpkdf_krb5.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2001-2020 The OpenSSL Project Authors. All Rights Reserved.
+# Copyright 2001-2025 The OpenSSL Project Authors. All Rights Reserved.
 #
 # Licensed under the Apache License 2.0 (the "License").  You may not use
 # this file except in compliance with the License.  You can obtain a copy
@@ -129,3 +129,11 @@ Ctrl.cipher = cipher:DES-EDE3-CBC
 Ctrl.hexkey = hexkey:dce06b1f64c857a11c3db57c51899b2cc1791008ce973b92
 Ctrl.hexconstant = hexconstant:0000000155
 Output = 935079d14490a75c3093c4a6e8c3b049c71e6ee705
+
+#Erroneous key size for the cipher as XTS has double key size
+KDF = KRB5KDF
+Ctrl.cipher = cipher:AES-256-XTS
+Ctrl.hexkey = hexkey:FE697B52BC0D3CE14432BA036A92E65BBB52280990A2FA27883998D72AF30161
+Ctrl.hexconstant = hexconstant:0000000255
+Output = 97151B4C76945063E2EB0529DC067D97D7BBA90776D8126D91F34F3101AEA8BA
+Result = KDF_DERIVE_ERROR
diff --git a/crypto/openssl/test/recipes/30-test_evp_data/evppkey_rsa_sigalg.txt b/crypto/openssl/test/recipes/30-test_evp_data/evppkey_rsa_sigalg.txt
index 5083cc2bde24..f258700670ab 100644
--- a/crypto/openssl/test/recipes/30-test_evp_data/evppkey_rsa_sigalg.txt
+++ b/crypto/openssl/test/recipes/30-test_evp_data/evppkey_rsa_sigalg.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2001-2024 The OpenSSL Project Authors. All Rights Reserved.
+# Copyright 2001-2025 The OpenSSL Project Authors. All Rights Reserved.
 #
 # Licensed under the Apache License 2.0 (the "License").  You may not use
 # this file except in compliance with the License.  You can obtain a copy
@@ -186,4 +186,4 @@ Output = 6a7fc08e9999fc9d50cda476e973a01a06efeb52eece1c78cb1422950476cbff67408c6
 Availablein = default
 Sign-Message = RSA-SM3:RSA-2048
 Input = "Hello World"
-Output = 92657e22036214c343d8e95d129c0c47430d5a1ae452371a7847a963f533f96e018aa6658958e6a584cf0d380aa9435175cf2de3dfa60100aca893b76aa6d8f0cc9154ee982cb5ea8f19153fe8a9c801aa2da8bb4451c7ec6fd836e81ecdacf022b68294db068efa47decf3a7c548ea7088a16433029b8733b9573053b7e7122ea10b662726fc97bd149c663617434a9707b672b024f95865d91077edfb79c8ed4c8528032204c46c984a6c82b17794cbf9c4dfe4c1af1d59535f7755540ff36d6a2b55accbf046896c4aae9287a33f38c2a269a02abdac46c17b1b55ee89cc9eb3011a84916596f982c5375dd2110633be6dc43532919466d83bd0f3e406978
+Output = b74e03c18050807541bde949aa0ac91d43fb9730f0b529d5100d5776f4f446d0ca0f0992359dc5f89386ed45bc3bf52cac1f75fbcc088fc2ea77624fd962569d2d317e90886dec424fb6757c4eba1e881ddf4f7942e8003b54e05cc974558dea171ce23a2fc158f71a5621c9a2c3ce45c9af4c706d3f60efe0c0f087a6ec504f771b08e2a1d78e0316c74706c678869bf121d5da00e2e8c8dc1cd273315b4ad8ab9962c62f81cebc5fb393b7f8860ee68545578413feada82b1c2bbfabfa157e298f0354bffc1cc6aa68f058a5d34b6b70ffacd3532c6b2c6a0de059bf605edf392ac8adbf1769555a0a50b2b13c63cae98a461498fae7f0d1729b710f05f39e
diff --git a/crypto/openssl/test/recipes/90-test_sslapi.t b/crypto/openssl/test/recipes/90-test_sslapi.t
index 650e0d1ffb16..70c2c24d8661 100644
--- a/crypto/openssl/test/recipes/90-test_sslapi.t
+++ b/crypto/openssl/test/recipes/90-test_sslapi.t
@@ -1,5 +1,5 @@
 #! /usr/bin/env perl
-# Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
+# Copyright 2016-2025 The OpenSSL Project Authors. All Rights Reserved.
 #
 # Licensed under the Apache License 2.0 (the "License").  You may not use
 # this file except in compliance with the License.  You can obtain a copy
@@ -45,7 +45,10 @@ ok(run(test(["sslapitest", srctop_dir("test", "certs"),
              srctop_file("test",
                          "recipes",
                          "90-test_sslapi_data",
-                         "dhparams.pem")])),
+                         "dhparams.pem"),
+             srctop_dir("test",
+                        "recipes",
+                        "90-test_sslapi_data")])),
              "running sslapitest");
 
 SKIP: {
@@ -62,7 +65,10 @@ SKIP: {
                  srctop_file("test",
                              "recipes",
                              "90-test_sslapi_data",
-                             "dhparams.pem")])),
+                             "dhparams.pem"),
+                 srctop_dir("test",
+                            "recipes",
+                            "90-test_sslapi_data")])),
                  "running sslapitest with default fips config");
 
     run(test(["fips_version_test", "-config", $provconf, ">=3.1.0"]),
@@ -140,7 +146,10 @@ SKIP: {
                     srctop_file("test",
                                 "recipes",
                                 "90-test_sslapi_data",
-                                "dhparams.pem")])),
+                                "dhparams.pem"),
+                    srctop_dir("test",
+                               "recipes",
+                               "90-test_sslapi_data")])),
        "running sslapitest with modified fips config");
 }
 
diff --git a/crypto/openssl/test/recipes/90-test_sslapi_data/ssltraceref-zlib.txt b/crypto/openssl/test/recipes/90-test_sslapi_data/ssltraceref-zlib.txt
new file mode 100644
index 000000000000..05aed8299b0e
--- /dev/null
+++ b/crypto/openssl/test/recipes/90-test_sslapi_data/ssltraceref-zlib.txt
@@ -0,0 +1,255 @@
+Sent TLS Record
+Header:
+  Version = TLS 1.0 (0x301)
+  Content Type = Handshake (22)
+  Length = ?
+    ClientHello, Length=?
+      client_version=0x303 (TLS 1.2)
+      Random:
+        gmt_unix_time=0x?
+        random_bytes (len=28): ?
+      session_id (len=?
+      cipher_suites (len=2)
+        {0x13, 0x01} TLS_AES_128_GCM_SHA256
+      compression_methods (len=1)
+        No Compression (0x00)
+      extensions, length = ?
+        extension_type=ec_point_formats(11), length=4
+          uncompressed (0)
+          ansiX962_compressed_prime (1)
+          ansiX962_compressed_char2 (2)
+        extension_type=supported_groups(10), length=20
+          MLKEM512 (512)
+          MLKEM768 (513)
+          MLKEM1024 (514)
+          X25519MLKEM768 (4588)
+          SecP256r1MLKEM768 (4587)
+          SecP384r1MLKEM1024 (4589)
+          secp521r1 (P-521) (25)
+          secp384r1 (P-384) (24)
+          secp256r1 (P-256) (23)
+        extension_type=session_ticket(35), length=0
+        extension_type=encrypt_then_mac(22), length=0
+        extension_type=extended_master_secret(23), length=0
+        extension_type=signature_algorithms(13), length=?
+          mldsa65 (0x0905)
+          mldsa87 (0x0906)
+          mldsa44 (0x0904)
+          ecdsa_secp256r1_sha256 (0x0403)
+          ecdsa_secp384r1_sha384 (0x0503)
+          ecdsa_secp521r1_sha512 (0x0603)
+          ed25519 (0x0807)
+          ed448 (0x0808)
+          ecdsa_brainpoolP256r1tls13_sha256 (0x081a)
+          ecdsa_brainpoolP384r1tls13_sha384 (0x081b)
+          ecdsa_brainpoolP512r1tls13_sha512 (0x081c)
+          rsa_pss_pss_sha256 (0x0809)
+          rsa_pss_pss_sha384 (0x080a)
+          rsa_pss_pss_sha512 (0x080b)
+          rsa_pss_rsae_sha256 (0x0804)
+          rsa_pss_rsae_sha384 (0x0805)
+          rsa_pss_rsae_sha512 (0x0806)
+          rsa_pkcs1_sha256 (0x0401)
+          rsa_pkcs1_sha384 (0x0501)
+          rsa_pkcs1_sha512 (0x0601)
+        extension_type=supported_versions(43), length=3
+          TLS 1.3 (772)
+        extension_type=psk_key_exchange_modes(45), length=2
+          psk_dhe_ke (1)
+        extension_type=key_share(51), length=806
+            NamedGroup: MLKEM512 (512)
+            key_exchange:  (len=800): ?
+        extension_type=compress_certificate(27), length=3
+          zlib (1)
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = Handshake (22)
+  Length = 858
+    ServerHello, Length=854
+      server_version=0x303 (TLS 1.2)
+      Random:
+        gmt_unix_time=0x?
+        random_bytes (len=28): ?
+      session_id (len=?
+      cipher_suite {0x13, 0x01} TLS_AES_128_GCM_SHA256
+      compression_method: No Compression (0x00)
+      extensions, length = ?
+        extension_type=supported_versions(43), length=2
+            TLS 1.3 (772)
+        extension_type=key_share(51), length=772
+            NamedGroup: MLKEM512 (512)
+            key_exchange:  (len=768): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ChangeCipherSpec (20)
+  Length = 1
+    change_cipher_spec (1)
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 23
+  Inner Content Type = Handshake (22)
+    EncryptedExtensions, Length=2
+      No extensions
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 839
+  Inner Content Type = Handshake (22)
+    Certificate, Length=818
+      context (len=0): 
+      certificate_list, length=814
+        ASN.1Cert, length=809
+------details-----
+Certificate:
+    Data:
+        Version: 3 (0x2)
+        Serial Number: 2 (0x2)
+        Signature Algorithm: sha256WithRSAEncryption
+        Issuer: CN = Root CA
+        Validity
+            Not Before: Jan 14 22:29:46 2016 GMT
+            Not After : Jan 15 22:29:46 2116 GMT
+        Subject: CN = server.example
+        Subject Public Key Info:
+            Public Key Algorithm: rsaEncryption
+                Public-Key: (2048 bit)
+                Modulus:
+                    00:d5:5d:60:6a:df:fc:61:ee:48:aa:8c:11:48:43:
+                    a5:6d:b6:52:5d:aa:98:49:b1:61:92:35:b1:fc:3a:
+                    04:25:0c:6d:79:ff:b4:d5:c9:e9:5c:1c:3b:e0:ab:
+                    b3:b8:7d:a3:de:6d:bd:e0:dd:d7:5a:bf:14:47:11:
+                    42:5e:a6:82:d0:61:c1:7f:dd:13:46:e6:09:85:07:
+                    0e:f2:d4:fc:1a:64:d2:0a:ad:20:ab:20:6b:96:f0:
+                    ad:cc:c4:19:53:55:dc:01:1d:a4:b3:ef:8a:b4:49:
+                    53:5d:8a:05:1c:f1:dc:e1:44:bf:c5:d7:e2:77:19:
+                    57:5c:97:0b:75:ee:88:43:71:0f:ca:6c:c1:b4:b2:
+                    50:a7:77:46:6c:58:0f:11:bf:f1:76:24:5a:ae:39:
+                    42:b7:51:67:29:e1:d0:55:30:6f:17:e4:91:ea:ad:
+                    f8:28:c2:43:6f:a2:64:a9:fb:9d:98:92:62:48:3e:
+                    eb:0d:4f:82:4a:8a:ff:3f:72:ee:96:b5:ae:a1:c1:
+                    98:ba:ef:7d:90:75:6d:ff:5a:52:9e:ab:f5:c0:7e:
+                    d0:87:43:db:85:07:07:0f:7d:38:7a:fd:d1:d3:ee:
+                    65:1d:d3:ea:39:6a:87:37:ee:4a:d3:e0:0d:6e:f5:
+                    70:ac:c2:bd:f1:6e:f3:92:95:5e:a9:f0:a1:65:95:
+                    93:8d
+                Exponent: 65537 (0x10001)
+        X509v3 extensions:
+            X509v3 Subject Key Identifier: 
+                C0:E7:84:BF:E8:59:27:33:10:B0:52:4F:51:52:2F:06:D6:C0:7A:CD
+            X509v3 Authority Key Identifier: 
+                70:7F:2E:AE:83:68:59:98:04:23:2A:CD:EB:3E:17:CD:24:DD:01:49
+            X509v3 Basic Constraints: 
+                CA:FALSE
+            X509v3 Extended Key Usage: 
+                TLS Web Server Authentication
+            X509v3 Subject Alternative Name: 
+                DNS:server.example
+    Signature Algorithm: sha256WithRSAEncryption
+    Signature Value:
+        7b:d3:04:43:75:8a:0f:11:ae:c4:fb:d7:a1:a2:9e:fe:20:18:
+        d5:f4:2f:31:88:46:b6:75:8c:ee:e5:9b:97:a6:b9:a3:cd:60:
+        9a:46:c3:48:97:e5:97:68:f7:5a:86:35:73:d9:69:9e:f9:5f:
+        74:b9:e6:94:13:01:cb:6a:dc:e3:c4:04:e9:65:da:9c:a4:8b:
+        28:f3:f9:9a:7f:bf:97:1f:45:92:e5:05:b1:56:e6:0b:f6:47:
+        de:1e:89:b6:2b:e1:4d:df:4a:7e:01:d3:23:dc:97:8c:47:fe:
+        5f:c7:cc:98:46:0e:c4:83:5b:ca:8a:f1:52:09:be:6b:ec:3f:
+        09:8b:d0:93:02:bf:e1:51:e7:d1:7e:34:56:19:74:d0:ff:28:
+        25:de:b7:9f:56:52:91:7d:20:29:85:0a:80:44:5f:71:32:25:
+        71:0f:c2:16:e2:5f:6b:1d:3f:32:5b:0a:3c:74:1c:b9:62:f1:
+        ed:07:50:a3:6d:b4:b4:31:0a:c0:53:44:6a:3a:88:84:8b:2d:
+        a9:b0:37:8e:e6:18:36:bd:9a:20:40:0f:01:92:8b:3d:aa:61:
+        e7:ae:2c:ed:36:cd:3a:07:86:74:3a:29:b3:d7:3a:b4:00:a9:
+        c2:f5:92:78:0e:e2:0f:a3:fe:bb:be:e0:06:53:84:59:1d:90:
+        69:e5:b6:f9
+-----BEGIN CERTIFICATE-----
+MIIDJTCCAg2gAwIBAgIBAjANBgkqhkiG9w0BAQsFADASMRAwDgYDVQQDDAdSb290
+IENBMCAXDTE2MDExNDIyMjk0NloYDzIxMTYwMTE1MjIyOTQ2WjAZMRcwFQYDVQQD
+DA5zZXJ2ZXIuZXhhbXBsZTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEB
+ANVdYGrf/GHuSKqMEUhDpW22Ul2qmEmxYZI1sfw6BCUMbXn/tNXJ6VwcO+Crs7h9
+o95tveDd11q/FEcRQl6mgtBhwX/dE0bmCYUHDvLU/Bpk0gqtIKsga5bwrczEGVNV
+3AEdpLPvirRJU12KBRzx3OFEv8XX4ncZV1yXC3XuiENxD8pswbSyUKd3RmxYDxG/
+8XYkWq45QrdRZynh0FUwbxfkkeqt+CjCQ2+iZKn7nZiSYkg+6w1PgkqK/z9y7pa1
+rqHBmLrvfZB1bf9aUp6r9cB+0IdD24UHBw99OHr90dPuZR3T6jlqhzfuStPgDW71
+cKzCvfFu85KVXqnwoWWVk40CAwEAAaN9MHswHQYDVR0OBBYEFMDnhL/oWSczELBS
+T1FSLwbWwHrNMB8GA1UdIwQYMBaAFHB/Lq6DaFmYBCMqzes+F80k3QFJMAkGA1Ud
+EwQCMAAwEwYDVR0lBAwwCgYIKwYBBQUHAwEwGQYDVR0RBBIwEIIOc2VydmVyLmV4
+YW1wbGUwDQYJKoZIhvcNAQELBQADggEBAHvTBEN1ig8RrsT716Ginv4gGNX0LzGI
+RrZ1jO7lm5emuaPNYJpGw0iX5Zdo91qGNXPZaZ75X3S55pQTActq3OPEBOll2pyk
+iyjz+Zp/v5cfRZLlBbFW5gv2R94eibYr4U3fSn4B0yPcl4xH/l/HzJhGDsSDW8qK
+8VIJvmvsPwmL0JMCv+FR59F+NFYZdND/KCXet59WUpF9ICmFCoBEX3EyJXEPwhbi
+X2sdPzJbCjx0HLli8e0HUKNttLQxCsBTRGo6iISLLamwN47mGDa9miBADwGSiz2q
+YeeuLO02zToHhnQ6KbPXOrQAqcL1kngO4g+j/ru+4AZThFkdkGnltvk=
+-----END CERTIFICATE-----
+------------------
+        No extensions
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 281
+  Inner Content Type = Handshake (22)
+    CertificateVerify, Length=260
+      Signature Algorithm: rsa_pss_rsae_sha256 (0x0804)
+      Signature (len=256): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 53
+  Inner Content Type = Handshake (22)
+    Finished, Length=32
+      verify_data (len=32): ?
+
+Sent TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ChangeCipherSpec (20)
+  Length = 1
+    change_cipher_spec (1)
+
+Sent TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 53
+  Inner Content Type = Handshake (22)
+    Finished, Length=32
+      verify_data (len=32): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 234
+  Inner Content Type = Handshake (22)
+    NewSessionTicket, Length=213
+        ticket_lifetime_hint=7200
+        ticket_age_add=?
+        ticket_nonce (len=8): ?
+        ticket (len=192): ?
+        No extensions
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 234
+  Inner Content Type = Handshake (22)
+    NewSessionTicket, Length=213
+        ticket_lifetime_hint=7200
+        ticket_age_add=?
+        ticket_nonce (len=8): ?
+        ticket (len=192): ?
+        No extensions
+
diff --git a/crypto/openssl/test/recipes/90-test_sslapi_data/ssltraceref.txt b/crypto/openssl/test/recipes/90-test_sslapi_data/ssltraceref.txt
new file mode 100644
index 000000000000..5d332da235fb
--- /dev/null
+++ b/crypto/openssl/test/recipes/90-test_sslapi_data/ssltraceref.txt
@@ -0,0 +1,253 @@
+Sent TLS Record
+Header:
+  Version = TLS 1.0 (0x301)
+  Content Type = Handshake (22)
+  Length = ?
+    ClientHello, Length=?
+      client_version=0x303 (TLS 1.2)
+      Random:
+        gmt_unix_time=0x?
+        random_bytes (len=28): ?
+      session_id (len=?
+      cipher_suites (len=2)
+        {0x13, 0x01} TLS_AES_128_GCM_SHA256
+      compression_methods (len=1)
+        No Compression (0x00)
+      extensions, length = ?
+        extension_type=ec_point_formats(11), length=4
+          uncompressed (0)
+          ansiX962_compressed_prime (1)
+          ansiX962_compressed_char2 (2)
+        extension_type=supported_groups(10), length=20
+          MLKEM512 (512)
+          MLKEM768 (513)
+          MLKEM1024 (514)
+          X25519MLKEM768 (4588)
+          SecP256r1MLKEM768 (4587)
+          SecP384r1MLKEM1024 (4589)
+          secp521r1 (P-521) (25)
+          secp384r1 (P-384) (24)
+          secp256r1 (P-256) (23)
+        extension_type=session_ticket(35), length=0
+        extension_type=encrypt_then_mac(22), length=0
+        extension_type=extended_master_secret(23), length=0
+        extension_type=signature_algorithms(13), length=?
+          mldsa65 (0x0905)
+          mldsa87 (0x0906)
+          mldsa44 (0x0904)
+          ecdsa_secp256r1_sha256 (0x0403)
+          ecdsa_secp384r1_sha384 (0x0503)
+          ecdsa_secp521r1_sha512 (0x0603)
+          ed25519 (0x0807)
+          ed448 (0x0808)
+          ecdsa_brainpoolP256r1tls13_sha256 (0x081a)
+          ecdsa_brainpoolP384r1tls13_sha384 (0x081b)
+          ecdsa_brainpoolP512r1tls13_sha512 (0x081c)
+          rsa_pss_pss_sha256 (0x0809)
+          rsa_pss_pss_sha384 (0x080a)
+          rsa_pss_pss_sha512 (0x080b)
+          rsa_pss_rsae_sha256 (0x0804)
+          rsa_pss_rsae_sha384 (0x0805)
+          rsa_pss_rsae_sha512 (0x0806)
+          rsa_pkcs1_sha256 (0x0401)
+          rsa_pkcs1_sha384 (0x0501)
+          rsa_pkcs1_sha512 (0x0601)
+        extension_type=supported_versions(43), length=3
+          TLS 1.3 (772)
+        extension_type=psk_key_exchange_modes(45), length=2
+          psk_dhe_ke (1)
+        extension_type=key_share(51), length=806
+            NamedGroup: MLKEM512 (512)
+            key_exchange:  (len=800): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = Handshake (22)
+  Length = 858
+    ServerHello, Length=854
+      server_version=0x303 (TLS 1.2)
+      Random:
+        gmt_unix_time=0x?
+        random_bytes (len=28): ?
+      session_id (len=?
+      cipher_suite {0x13, 0x01} TLS_AES_128_GCM_SHA256
+      compression_method: No Compression (0x00)
+      extensions, length = ?
+        extension_type=supported_versions(43), length=2
+            TLS 1.3 (772)
+        extension_type=key_share(51), length=772
+            NamedGroup: MLKEM512 (512)
+            key_exchange:  (len=768): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ChangeCipherSpec (20)
+  Length = 1
+    change_cipher_spec (1)
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 23
+  Inner Content Type = Handshake (22)
+    EncryptedExtensions, Length=2
+      No extensions
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 839
+  Inner Content Type = Handshake (22)
+    Certificate, Length=818
+      context (len=0): 
+      certificate_list, length=814
+        ASN.1Cert, length=809
+------details-----
+Certificate:
+    Data:
+        Version: 3 (0x2)
+        Serial Number: 2 (0x2)
+        Signature Algorithm: sha256WithRSAEncryption
+        Issuer: CN = Root CA
+        Validity
+            Not Before: Jan 14 22:29:46 2016 GMT
+            Not After : Jan 15 22:29:46 2116 GMT
+        Subject: CN = server.example
+        Subject Public Key Info:
+            Public Key Algorithm: rsaEncryption
+                Public-Key: (2048 bit)
+                Modulus:
+                    00:d5:5d:60:6a:df:fc:61:ee:48:aa:8c:11:48:43:
+                    a5:6d:b6:52:5d:aa:98:49:b1:61:92:35:b1:fc:3a:
+                    04:25:0c:6d:79:ff:b4:d5:c9:e9:5c:1c:3b:e0:ab:
+                    b3:b8:7d:a3:de:6d:bd:e0:dd:d7:5a:bf:14:47:11:
+                    42:5e:a6:82:d0:61:c1:7f:dd:13:46:e6:09:85:07:
+                    0e:f2:d4:fc:1a:64:d2:0a:ad:20:ab:20:6b:96:f0:
+                    ad:cc:c4:19:53:55:dc:01:1d:a4:b3:ef:8a:b4:49:
+                    53:5d:8a:05:1c:f1:dc:e1:44:bf:c5:d7:e2:77:19:
+                    57:5c:97:0b:75:ee:88:43:71:0f:ca:6c:c1:b4:b2:
+                    50:a7:77:46:6c:58:0f:11:bf:f1:76:24:5a:ae:39:
+                    42:b7:51:67:29:e1:d0:55:30:6f:17:e4:91:ea:ad:
+                    f8:28:c2:43:6f:a2:64:a9:fb:9d:98:92:62:48:3e:
+                    eb:0d:4f:82:4a:8a:ff:3f:72:ee:96:b5:ae:a1:c1:
+                    98:ba:ef:7d:90:75:6d:ff:5a:52:9e:ab:f5:c0:7e:
+                    d0:87:43:db:85:07:07:0f:7d:38:7a:fd:d1:d3:ee:
+                    65:1d:d3:ea:39:6a:87:37:ee:4a:d3:e0:0d:6e:f5:
+                    70:ac:c2:bd:f1:6e:f3:92:95:5e:a9:f0:a1:65:95:
+                    93:8d
+                Exponent: 65537 (0x10001)
+        X509v3 extensions:
+            X509v3 Subject Key Identifier: 
+                C0:E7:84:BF:E8:59:27:33:10:B0:52:4F:51:52:2F:06:D6:C0:7A:CD
+            X509v3 Authority Key Identifier: 
+                70:7F:2E:AE:83:68:59:98:04:23:2A:CD:EB:3E:17:CD:24:DD:01:49
+            X509v3 Basic Constraints: 
+                CA:FALSE
+            X509v3 Extended Key Usage: 
+                TLS Web Server Authentication
+            X509v3 Subject Alternative Name: 
+                DNS:server.example
+    Signature Algorithm: sha256WithRSAEncryption
+    Signature Value:
+        7b:d3:04:43:75:8a:0f:11:ae:c4:fb:d7:a1:a2:9e:fe:20:18:
+        d5:f4:2f:31:88:46:b6:75:8c:ee:e5:9b:97:a6:b9:a3:cd:60:
+        9a:46:c3:48:97:e5:97:68:f7:5a:86:35:73:d9:69:9e:f9:5f:
+        74:b9:e6:94:13:01:cb:6a:dc:e3:c4:04:e9:65:da:9c:a4:8b:
+        28:f3:f9:9a:7f:bf:97:1f:45:92:e5:05:b1:56:e6:0b:f6:47:
+        de:1e:89:b6:2b:e1:4d:df:4a:7e:01:d3:23:dc:97:8c:47:fe:
+        5f:c7:cc:98:46:0e:c4:83:5b:ca:8a:f1:52:09:be:6b:ec:3f:
+        09:8b:d0:93:02:bf:e1:51:e7:d1:7e:34:56:19:74:d0:ff:28:
+        25:de:b7:9f:56:52:91:7d:20:29:85:0a:80:44:5f:71:32:25:
+        71:0f:c2:16:e2:5f:6b:1d:3f:32:5b:0a:3c:74:1c:b9:62:f1:
+        ed:07:50:a3:6d:b4:b4:31:0a:c0:53:44:6a:3a:88:84:8b:2d:
+        a9:b0:37:8e:e6:18:36:bd:9a:20:40:0f:01:92:8b:3d:aa:61:
+        e7:ae:2c:ed:36:cd:3a:07:86:74:3a:29:b3:d7:3a:b4:00:a9:
+        c2:f5:92:78:0e:e2:0f:a3:fe:bb:be:e0:06:53:84:59:1d:90:
+        69:e5:b6:f9
+-----BEGIN CERTIFICATE-----
+MIIDJTCCAg2gAwIBAgIBAjANBgkqhkiG9w0BAQsFADASMRAwDgYDVQQDDAdSb290
+IENBMCAXDTE2MDExNDIyMjk0NloYDzIxMTYwMTE1MjIyOTQ2WjAZMRcwFQYDVQQD
+DA5zZXJ2ZXIuZXhhbXBsZTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEB
+ANVdYGrf/GHuSKqMEUhDpW22Ul2qmEmxYZI1sfw6BCUMbXn/tNXJ6VwcO+Crs7h9
+o95tveDd11q/FEcRQl6mgtBhwX/dE0bmCYUHDvLU/Bpk0gqtIKsga5bwrczEGVNV
+3AEdpLPvirRJU12KBRzx3OFEv8XX4ncZV1yXC3XuiENxD8pswbSyUKd3RmxYDxG/
+8XYkWq45QrdRZynh0FUwbxfkkeqt+CjCQ2+iZKn7nZiSYkg+6w1PgkqK/z9y7pa1
+rqHBmLrvfZB1bf9aUp6r9cB+0IdD24UHBw99OHr90dPuZR3T6jlqhzfuStPgDW71
+cKzCvfFu85KVXqnwoWWVk40CAwEAAaN9MHswHQYDVR0OBBYEFMDnhL/oWSczELBS
+T1FSLwbWwHrNMB8GA1UdIwQYMBaAFHB/Lq6DaFmYBCMqzes+F80k3QFJMAkGA1Ud
+EwQCMAAwEwYDVR0lBAwwCgYIKwYBBQUHAwEwGQYDVR0RBBIwEIIOc2VydmVyLmV4
+YW1wbGUwDQYJKoZIhvcNAQELBQADggEBAHvTBEN1ig8RrsT716Ginv4gGNX0LzGI
+RrZ1jO7lm5emuaPNYJpGw0iX5Zdo91qGNXPZaZ75X3S55pQTActq3OPEBOll2pyk
+iyjz+Zp/v5cfRZLlBbFW5gv2R94eibYr4U3fSn4B0yPcl4xH/l/HzJhGDsSDW8qK
+8VIJvmvsPwmL0JMCv+FR59F+NFYZdND/KCXet59WUpF9ICmFCoBEX3EyJXEPwhbi
+X2sdPzJbCjx0HLli8e0HUKNttLQxCsBTRGo6iISLLamwN47mGDa9miBADwGSiz2q
+YeeuLO02zToHhnQ6KbPXOrQAqcL1kngO4g+j/ru+4AZThFkdkGnltvk=
+-----END CERTIFICATE-----
+------------------
+        No extensions
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 281
+  Inner Content Type = Handshake (22)
+    CertificateVerify, Length=260
+      Signature Algorithm: rsa_pss_rsae_sha256 (0x0804)
+      Signature (len=256): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 53
+  Inner Content Type = Handshake (22)
+    Finished, Length=32
+      verify_data (len=32): ?
+
+Sent TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ChangeCipherSpec (20)
+  Length = 1
+    change_cipher_spec (1)
+
+Sent TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 53
+  Inner Content Type = Handshake (22)
+    Finished, Length=32
+      verify_data (len=32): ?
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 234
+  Inner Content Type = Handshake (22)
+    NewSessionTicket, Length=213
+        ticket_lifetime_hint=7200
+        ticket_age_add=?
+        ticket_nonce (len=8): ?
+        ticket (len=192): ?
+        No extensions
+
+Received TLS Record
+Header:
+  Version = TLS 1.2 (0x303)
+  Content Type = ApplicationData (23)
+  Length = 234
+  Inner Content Type = Handshake (22)
+    NewSessionTicket, Length=213
+        ticket_lifetime_hint=7200
+        ticket_age_add=?
+        ticket_nonce (len=8): ?
+        ticket (len=192): ?
+        No extensions
+
diff --git a/crypto/openssl/test/sslapitest.c b/crypto/openssl/test/sslapitest.c
index b83dd6c552de..fbe284b9ff1e 100644
--- a/crypto/openssl/test/sslapitest.c
+++ b/crypto/openssl/test/sslapitest.c
@@ -98,6 +98,7 @@ static char *privkey8192 = NULL;
 static char *srpvfile = NULL;
 static char *tmpfilename = NULL;
 static char *dhfile = NULL;
+static char *datadir = NULL;
 
 static int is_fips = 0;
 static int fips_ems_check = 0;
@@ -120,6 +121,15 @@ static X509 *ocspcert = NULL;
 
 #define CLIENT_VERSION_LEN      2
 
+/* The ssltrace test assumes some options are switched on/off */
+#if !defined(OPENSSL_NO_SSL_TRACE) \
+        && defined(OPENSSL_NO_BROTLI) && defined(OPENSSL_NO_ZSTD) \
+        && !defined(OPENSSL_NO_ECX) && !defined(OPENSSL_NO_DH) \
+        && !defined(OPENSSL_NO_ML_DSA) && !defined(OPENSSL_NO_ML_KEM) \
+        && !defined(OPENSSL_NO_TLS1_3)
+# define DO_SSL_TRACE_TEST
+#endif
+
 /*
  * This structure is used to validate that the correct number of log messages
  * of various types are emitted when emitting secret logs.
@@ -13269,6 +13279,77 @@ static int test_no_renegotiation(int idx)
     return testresult;
 }
 
+#if defined(DO_SSL_TRACE_TEST)
+/*
+ * Tests that the SSL_trace() msg_callback works as expected with a PQ Groups.
+ */
+static int test_ssl_trace(void)
+{
+    SSL_CTX *sctx = NULL, *cctx = NULL;
+    SSL *serverssl = NULL, *clientssl = NULL;
+    int testresult = 0;
+    BIO *bio = NULL;
+    char *reffile = NULL;
+    char *grouplist = "MLKEM512:MLKEM768:MLKEM1024:X25519MLKEM768:SecP256r1MLKEM768"
+        ":SecP384r1MLKEM1024:secp521r1:secp384r1:secp256r1";
+
+    if (!fips_provider_version_ge(libctx, 3, 5, 0))
+        return TEST_skip("FIPS provider does not support MLKEM algorithms");
+
+    if (!TEST_true(create_ssl_ctx_pair(libctx, TLS_server_method(),
+                                       TLS_client_method(),
+                                       TLS1_3_VERSION, TLS1_3_VERSION,
+                                       &sctx, &cctx, cert, privkey))
+            || !TEST_ptr(bio = BIO_new(BIO_s_mem()))
+            || !TEST_true(SSL_CTX_set1_groups_list(sctx, grouplist))
+            || !TEST_true(SSL_CTX_set1_groups_list(cctx, grouplist))
+            || !TEST_true(SSL_CTX_set_ciphersuites(cctx,
+                                                   "TLS_AES_128_GCM_SHA256"))
+            || !TEST_true(SSL_CTX_set_ciphersuites(sctx,
+                                                   "TLS_AES_128_GCM_SHA256"))
+# ifdef SSL_OP_LEGACY_EC_POINT_FORMATS
+            || !TEST_true(SSL_CTX_set_options(cctx, SSL_OP_LEGACY_EC_POINT_FORMATS))
+            || !TEST_true(SSL_CTX_set_options(sctx, SSL_OP_LEGACY_EC_POINT_FORMATS))
+# endif
+            || !TEST_true(create_ssl_objects(sctx, cctx, &serverssl, &clientssl,
+                                             NULL, NULL)))
+        goto err;
+
+    SSL_set_msg_callback(clientssl, SSL_trace);
+    SSL_set_msg_callback_arg(clientssl, bio);
+
+    if (!TEST_true(create_ssl_connection(serverssl, clientssl, SSL_ERROR_NONE)))
+        goto err;
+
+    /* Skip the comparison of the trace when the fips provider is used. */
+    if (is_fips) {
+        /* Check whether there was something written. */
+        if (!TEST_int_gt(BIO_pending(bio), 0))
+            goto err;
+    } else {
+
+# ifdef OPENSSL_NO_ZLIB
+        reffile = test_mk_file_path(datadir, "ssltraceref.txt");
+# else
+        reffile = test_mk_file_path(datadir, "ssltraceref-zlib.txt");
+# endif
+        if (!TEST_true(compare_with_reference_file(bio, reffile)))
+            goto err;
+    }
+
+    testresult = 1;
+ err:
+    BIO_free(bio);
+    SSL_free(serverssl);
+    SSL_free(clientssl);
+    SSL_CTX_free(sctx);
+    SSL_CTX_free(cctx);
+    OPENSSL_free(reffile);
+
+    return testresult;
+}
+#endif
+
 OPT_TEST_DECLARE_USAGE("certfile privkeyfile srpvfile tmpfile provider config dhfile\n")
 
 int setup_tests(void)
@@ -13303,6 +13384,8 @@ int setup_tests(void)
             || !TEST_ptr(dhfile = test_get_argument(5)))
         return 0;
 
+    datadir = test_get_argument(6);
+
     if (!TEST_true(OSSL_LIB_CTX_load_config(libctx, configfile)))
         return 0;
 
@@ -13598,6 +13681,10 @@ int setup_tests(void)
     ADD_TEST(test_quic_tls_early_data);
 #endif
     ADD_ALL_TESTS(test_no_renegotiation, 2);
+#if defined(DO_SSL_TRACE_TEST)
+    if (datadir != NULL)
+        ADD_TEST(test_ssl_trace);
+#endif
     return 1;
 
  err:
diff --git a/crypto/openssl/test/testutil.h b/crypto/openssl/test/testutil.h
index f02dcdfba6f9..a262d9371955 100644
--- a/crypto/openssl/test/testutil.h
+++ b/crypto/openssl/test/testutil.h
@@ -652,4 +652,6 @@ X509 *load_cert_der(const unsigned char *bytes, int len);
 STACK_OF(X509) *load_certs_pem(const char *file);
 X509_REQ *load_csr_der(const char *file, OSSL_LIB_CTX *libctx);
 time_t test_asn1_string_to_time_t(const char *asn1_string);
+
+int compare_with_reference_file(BIO *membio, const char *reffile);
 #endif                          /* OSSL_TESTUTIL_H */
diff --git a/crypto/openssl/test/testutil/compare.c b/crypto/openssl/test/testutil/compare.c
new file mode 100644
index 000000000000..067fb878b58e
--- /dev/null
+++ b/crypto/openssl/test/testutil/compare.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2017-2025 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the Apache License 2.0 (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+
+#include "../testutil.h"
+
+static void strip_line_ends(char *str)
+{
+    size_t i;
+
+    for (i = strlen(str);
+         i > 0 && (str[i - 1] == '\n' || str[i - 1] == '\r');
+         i--);
+
+    str[i] = '\0';
+}
+
+int compare_with_reference_file(BIO *membio, const char *reffile)
+{
+    BIO *file = NULL, *newfile = NULL;
+    char buf1[8192], buf2[8192];
+    int ret = 0;
+    size_t i;
+
+    if (!TEST_ptr(reffile))
+        goto err;
+
+    file = BIO_new_file(reffile, "rb");
+    if (!TEST_ptr(file))
+        goto err;
+
+    newfile = BIO_new_file("ssltraceref-new.txt", "wb");
+    if (!TEST_ptr(newfile))
+        goto err;
+
+    while (BIO_gets(membio, buf2, sizeof(buf2)) > 0)
+        if (BIO_puts(newfile, buf2) <= 0) {
+            TEST_error("Failed writing new file data");
+            goto err;
+        }
+
+    if (!TEST_int_ge(BIO_seek(membio, 0), 0))
+        goto err;
+
+    while (BIO_gets(file, buf1, sizeof(buf1)) > 0) {
+        size_t line_len;
+
+        if (BIO_gets(membio, buf2, sizeof(buf2)) <= 0) {
+            TEST_error("Failed reading mem data");
+            goto err;
+        }
+        strip_line_ends(buf1);
+        strip_line_ends(buf2);
+        line_len = strlen(buf1);
+        if (line_len > 0 && buf1[line_len - 1] == '?') {
+            /* Wildcard at the EOL means ignore anything after it */
+            if (strlen(buf2) > line_len)
+                buf2[line_len] = '\0';
+        }
+        if (line_len != strlen(buf2)) {
+            TEST_error("Actual and ref line data length mismatch");
+            TEST_info("%s", buf1);
+            TEST_info("%s", buf2);
+            goto err;
+        }
+        for (i = 0; i < line_len; i++) {
+            /* '?' is a wild card character in the reference text */
+            if (buf1[i] == '?')
+                buf2[i] = '?';
+        }
+        if (!TEST_str_eq(buf1, buf2))
+            goto err;
+    }
+    if (!TEST_true(BIO_eof(file))
+            || !TEST_true(BIO_eof(membio)))
+        goto err;
+
+    ret = 1;
+ err:
+    BIO_free(file);
+    BIO_free(newfile);
+    return ret;
+}
diff --git a/crypto/openssl/test/threadstest.c b/crypto/openssl/test/threadstest.c
index 38401911d87f..d33ad46999c6 100644
--- a/crypto/openssl/test/threadstest.c
+++ b/crypto/openssl/test/threadstest.c
@@ -183,13 +183,16 @@ static void rwreader_fn(int *iterations)
         CRYPTO_atomic_add(&rwwriter2_done, 0, &lw2, atomiclock);
 
         count++;
-        if (rwwriter_ptr != NULL && old > *rwwriter_ptr) {
-            TEST_info("rwwriter pointer went backwards\n");
-            rw_torture_result = 0;
+        if (rwwriter_ptr != NULL) {
+            if (old > *rwwriter_ptr) {
+                TEST_info("rwwriter pointer went backwards! %d : %d\n",
+                          old, *rwwriter_ptr);
+                rw_torture_result = 0;
+            }
+            old = *rwwriter_ptr;
         }
         if (CRYPTO_THREAD_unlock(rwtorturelock) == 0)
             abort();
-        *iterations = count;
         if (rw_torture_result == 0) {
             *iterations = count;
             return;
diff --git a/crypto/openssl/test/wpackettest.c b/crypto/openssl/test/wpackettest.c
index bd696e007407..c6d6faf5c485 100644
--- a/crypto/openssl/test/wpackettest.c
+++ b/crypto/openssl/test/wpackettest.c
@@ -588,7 +588,7 @@ static int test_WPACKET_quic_vlint_random(void)
 
     for (i = 0; i < 10000; ++i) {
         if (!TEST_int_gt(RAND_bytes(rand_data, sizeof(rand_data)), 0))
-            return cleanup(&pkt);
+            return 0;
 
         memcpy(&expected, rand_data, sizeof(expected));
 
diff --git a/etc/Makefile b/etc/Makefile
index ab799b2f6c80..93d4b489ec7d 100644
--- a/etc/Makefile
+++ b/etc/Makefile
@@ -64,9 +64,12 @@ distribution:
 	${INSTALL_SYMLINK} -T "package=runtime" ../var/run/os-release \
 		${DESTDIR}/etc/os-release
 .if ${MK_UNBOUND} != "no"
-	if [ ! -e ${DESTDIR}/etc/unbound ]; then \
-		${INSTALL_SYMLINK} -T "package=unbound" \
-		../var/unbound ${DESTDIR}/etc/unbound; \
+# If NO_ROOT is defined, we are doing a stage install and always need to
+# install the /etc/unbound symlink, otherwise, don't overwrite the user's
+# existing symlink.
+	if [ "${NO_ROOT:Dtrue}" = true -o ! -e ${DESTDIR}/etc/unbound ]; then \
+		${INSTALL_SYMLINK} -Tpackage=unbound ../var/unbound \
+			${DESTDIR}/etc/unbound; \
 	fi
 .endif
 .if ${MK_SENDMAIL} != "no"
@@ -82,12 +85,16 @@ distribution:
 .if ${MK_MAIL} != "no"
 	cd ${.CURDIR}/mail; ${INSTALL} -o ${BINOWN} -g ${BINGRP} -m 644 \
 	    -T "package=runtime,config" ${ETCMAIL} ${DESTDIR}/etc/mail
-	if [ -d ${DESTDIR}/etc/mail -a -f ${DESTDIR}/etc/mail/aliases -a \
-	      ! -f ${DESTDIR}/etc/aliases ]; then \
-		${INSTALL_SYMLINK} -T "package=runtime" \
-		mail/aliases ${DESTDIR}/etc/aliases; \
+# If NO_ROOT is defined, we are doing a stage install and always need to
+# install the /etc/aliases symlink, otherwise, don't overwrite the user's
+# existing symlink.
+	if [ "${NO_ROOT:Dtrue}" = true -o \( -f ${DESTDIR}/etc/mail/aliases -a \
+	   ! -f ${DESTDIR}/etc/aliases \) ]; then \
+		${INSTALL_SYMLINK} -Tpackage=runtime mail/aliases \
+			${DESTDIR}/etc/aliases; \
 	fi
-.endif
+.endif	# ${MK_MAIL} != "no"
+
 .if ${MK_SENDMAIL} != "no"
 	cd ${.CURDIR}/mail; ${INSTALL} -o ${BINOWN} -g ${BINGRP} -m 644 \
 		-T "package=sendmail" ${ETCMAIL_SENDMAIL} ${DESTDIR}/etc/mail
diff --git a/etc/mtree/BSD.usr.dist b/etc/mtree/BSD.usr.dist
index 1945c26ebc5f..d7d839b94b96 100644
--- a/etc/mtree/BSD.usr.dist
+++ b/etc/mtree/BSD.usr.dist
@@ -181,8 +181,6 @@
         ..
         hyperv
         ..
-        kgdb
-        ..
         lpr
             ru
             ..
diff --git a/gnu/usr.bin/diff3/Makefile b/gnu/usr.bin/diff3/Makefile
index 4d7bb8a82e1c..568733801a6b 100644
--- a/gnu/usr.bin/diff3/Makefile
+++ b/gnu/usr.bin/diff3/Makefile
@@ -1,8 +1,9 @@
+PACKAGE= diff3
+
 DIFFSRC=${SRCTOP}/contrib/diff/src
 .PATH:  ${DIFFSRC} \
 	${SRCTOP}/contrib/diff/lib \
 	${SRCTOP}/contrib/diff/man
-
 PROG=		diff3
 SRCS=           diff3.c version-etc.c \
 		xmalloc.c error.c c-stack.c exitfail.c cmpbuf.c
diff --git a/include/Makefile b/include/Makefile
index 07890362d7a6..661b2ee131ca 100644
--- a/include/Makefile
+++ b/include/Makefile
@@ -94,14 +94,14 @@ BSM=		audit.h \
 		audit_fcntl.h \
 		audit_kevents.h \
 		audit_socket_type.h
-BSMPACKAGE=	libbsm
+BSMPACKAGE=	audit
 BSMDIR=		${INCLUDEDIR}/bsm
 
 .PATH: ${SRCTOP}/sys/security
 SECAUDIT=	audit/audit.h \
 		audit/audit_ioctl.h \
 		audit/audit_private.h
-SECAUDITPACKAGE=	libbsm
+SECAUDITPACKAGE=	audit
 SECAUDITDIR=	${INCLUDEDIR}/security/audit
 
 .PATH:	${SRCTOP}/sys/cam
diff --git a/include/resolv.h b/include/resolv.h
index f32f52bab431..6ef79601b5f8 100644
--- a/include/resolv.h
+++ b/include/resolv.h
@@ -188,7 +188,7 @@ struct __res_state {
 			struct __res_state_ext *ext;	/*%< extension for IPv6 */
 		} _ext;
 	} _u;
-	u_char	*_rnd;			/*%< PRIVATE: random state */
+	u_char	*_rnd;			/*%< PRIVATE: random state (unused) */
 };
 
 typedef struct __res_state *res_state;
@@ -380,7 +380,6 @@ extern const struct res_sym __p_rcode_syms[];
 #define res_nisourserver	__res_nisourserver
 #define res_ownok		__res_ownok
 #define res_queriesmatch	__res_queriesmatch
-#define res_rndinit		__res_rndinit
 #define res_randomid		__res_randomid
 #define res_nrandomid		__res_nrandomid
 #define sym_ntop		__sym_ntop
@@ -445,7 +444,6 @@ int		dn_count_labels(const char *);
 int		dn_comp(const char *, u_char *, int, u_char **, u_char **);
 int		dn_expand(const u_char *, const u_char *, const u_char *,
 			  char *, int);
-void		res_rndinit(res_state);
 u_int		res_randomid(void);
 u_int		res_nrandomid(res_state);
 int		res_nameinquery(const char *, int, int, const u_char *,
diff --git a/include/stdlib.h b/include/stdlib.h
index ba0cf4b5e88e..784cb63bfc5b 100644
--- a/include/stdlib.h
+++ b/include/stdlib.h
@@ -314,6 +314,8 @@ int	 radixsort(const unsigned char **, int, const unsigned char *,
 	    unsigned);
 void	*reallocarray(void *, size_t, size_t) __result_use_check
 	    __alloc_size2(2, 3);
+void	*recallocarray(void *, size_t, size_t, size_t) __result_use_check
+	    __alloc_size2(3, 4);
 void	*reallocf(void *, size_t) __result_use_check __alloc_size(2);
 int	 rpmatch(const char *);
 char	*secure_getenv(const char *);
diff --git a/kerberos5/lib/libhdb/Makefile b/kerberos5/lib/libhdb/Makefile
index bcc3f75206bc..14fa242bc9e5 100644
--- a/kerberos5/lib/libhdb/Makefile
+++ b/kerberos5/lib/libhdb/Makefile
@@ -1,7 +1,9 @@
+PACKAGE=	kerberos-lib
+
 LIB=	hdb
 LDFLAGS+=	-Wl,--no-undefined ${LDAPLDFLAGS}
 VERSION_MAP=	${KRB5DIR}/lib/hdb/version-script.map
-LIBADD=	asn1 com_err krb5 roken sqlite3
+LIBADD=	asn1 com_err krb5 roken sqlite3 heimbase
 LDADD=	${LDAPLDADD}
 DPADD=	${LDAPDPADD}
 
@@ -74,6 +76,7 @@ GEN=	asn1_Salt.x \
 	asn1_HDB_Ext_Lan_Manager_OWF.x \
 	asn1_HDB_Ext_Password.x \
 	asn1_HDB_Ext_Aliases.x \
+	asn1_HDB_Ext_KeySet.x \
 	asn1_HDB_extension.x \
 	asn1_HDB_extensions.x \
 	asn1_hdb_entry.x \
diff --git a/lib/Makefile b/lib/Makefile
index bf38a489911d..d43e4d395f56 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -115,8 +115,7 @@ SUBDIR=	${SUBDIR_BOOTSTRAP} \
 	libz \
 	libzstd \
 	ncurses \
-	nss_tacplus \
-	virtual_oss
+	nss_tacplus
 
 # Inter-library dependencies.  When the makefile for a library contains LDADD
 # libraries, those libraries should be listed as build order dependencies here.
@@ -175,6 +174,7 @@ SUBDIR+=	clang
 .endif
 
 SUBDIR.${MK_CUSE}+= 	libcuse
+SUBDIR.${MK_CUSE}+=	virtual_oss
 SUBDIR.${MK_TOOLCHAIN}+=libpe
 SUBDIR.${MK_DIALOG}+=	libdpv libfigpar
 SUBDIR.${MK_FDT}+=	libfdt
diff --git a/lib/libbsdstat/bsdstat.h b/lib/libbsdstat/bsdstat.h
index 1b0d1f24e93f..b293cd652a72 100644
--- a/lib/libbsdstat/bsdstat.h
+++ b/lib/libbsdstat/bsdstat.h
@@ -76,7 +76,7 @@ struct fmt {
  * classes derived from it are useful.
  */
 struct bsdstat {
-	const char *name;		/* statistics name, e.g. wlanstats */
+	const char *name;		/* statistics name, e.g. wlanstat */
 	const struct fmt *stats;	/* statistics in class */
 	int nstats;			/* number of stats */
 #define	FMTS_IS_STAT	0x80	/* the following two bytes are the stat id */
diff --git a/lib/libbsm/Makefile b/lib/libbsm/Makefile
index 67802eef62ac..4413a5dd79f7 100644
--- a/lib/libbsm/Makefile
+++ b/lib/libbsm/Makefile
@@ -1,9 +1,8 @@
-#
-#
+PACKAGE=	audit
+LIB_PACKAGE=
 
-PACKAGE=	lib${LIB}
-OPENBSMDIR=		${SRCTOP}/contrib/openbsm
-_LIBBSMDIR=		${OPENBSMDIR}/libbsm
+OPENBSMDIR=	${SRCTOP}/contrib/openbsm
+_LIBBSMDIR=	${OPENBSMDIR}/libbsm
 
 LIB=		bsm
 SHLIB_MAJOR=	3
diff --git a/lib/libc/Makefile b/lib/libc/Makefile
index d0c254e33396..8705568f6d34 100644
--- a/lib/libc/Makefile
+++ b/lib/libc/Makefile
@@ -109,7 +109,6 @@ NOASM=
 .include "${LIBC_SRCTOP}/inet/Makefile.inc"
 .include "${LIBC_SRCTOP}/isc/Makefile.inc"
 .include "${LIBC_SRCTOP}/locale/Makefile.inc"
-.include "${LIBC_SRCTOP}/md/Makefile.inc"
 .include "${LIBC_SRCTOP}/nameser/Makefile.inc"
 .include "${LIBC_SRCTOP}/net/Makefile.inc"
 .include "${LIBC_SRCTOP}/nls/Makefile.inc"
diff --git a/lib/libc/Versions.def b/lib/libc/Versions.def
index 184e107d225a..1c7b34bef35b 100644
--- a/lib/libc/Versions.def
+++ b/lib/libc/Versions.def
@@ -42,6 +42,10 @@ FBSD_1.7 {
 FBSD_1.8 {
 } FBSD_1.7;
 
+# This version was first added to 16.0-current.
+FBSD_1.9 {
+} FBSD_1.8;
+
 # This is our private namespace.  Any global interfaces that are
 # strictly for use only by other FreeBSD applications and libraries
 # are listed here.  We use a separate namespace so we can write
@@ -49,4 +53,4 @@ FBSD_1.8 {
 #
 # Please do NOT increment the version of this namespace.
 FBSDprivate_1.0 {
-} FBSD_1.8;
+} FBSD_1.9;
diff --git a/lib/libc/gen/_rand48.c b/lib/libc/gen/_rand48.c
index 990e2c86949b..114c1595b33d 100644
--- a/lib/libc/gen/_rand48.c
+++ b/lib/libc/gen/_rand48.c
@@ -13,34 +13,6 @@
 
 #include "rand48.h"
 
-unsigned short _rand48_seed[3] = {
-	RAND48_SEED_0,
-	RAND48_SEED_1,
-	RAND48_SEED_2
-};
-unsigned short _rand48_mult[3] = {
-	RAND48_MULT_0,
-	RAND48_MULT_1,
-	RAND48_MULT_2
-};
-unsigned short _rand48_add = RAND48_ADD;
-
-void
-_dorand48(unsigned short xseed[3])
-{
-	unsigned long accu;
-	unsigned short temp[2];
-
-	accu = (unsigned long) _rand48_mult[0] * (unsigned long) xseed[0] +
-	 (unsigned long) _rand48_add;
-	temp[0] = (unsigned short) accu;	/* lower 16 bits */
-	accu >>= sizeof(unsigned short) * 8;
-	accu += (unsigned long) _rand48_mult[0] * (unsigned long) xseed[1] +
-	 (unsigned long) _rand48_mult[1] * (unsigned long) xseed[0];
-	temp[1] = (unsigned short) accu;	/* middle 16 bits */
-	accu >>= sizeof(unsigned short) * 8;
-	accu += _rand48_mult[0] * xseed[2] + _rand48_mult[1] * xseed[1] + _rand48_mult[2] * xseed[0];
-	xseed[0] = temp[0];
-	xseed[1] = temp[1];
-	xseed[2] = (unsigned short) accu;
-}
+uint48 _rand48_seed = RAND48_SEED;
+uint48 _rand48_mult = RAND48_MULT;
+uint48 _rand48_add = RAND48_ADD;
diff --git a/lib/libc/gen/drand48.c b/lib/libc/gen/drand48.c
index cec04a6a2425..f7f43ff20468 100644
--- a/lib/libc/gen/drand48.c
+++ b/lib/libc/gen/drand48.c
@@ -13,10 +13,10 @@
 
 #include "rand48.h"
 
-extern unsigned short _rand48_seed[3];
-
 double
 drand48(void)
 {
-	return erand48(_rand48_seed);
+	ERAND48_BEGIN;
+	_DORAND48(_rand48_seed);
+	ERAND48_END(_rand48_seed);
 }
diff --git a/lib/libc/gen/erand48.c b/lib/libc/gen/erand48.c
index 286904c27839..38d4774a9fe6 100644
--- a/lib/libc/gen/erand48.c
+++ b/lib/libc/gen/erand48.c
@@ -16,8 +16,9 @@
 double
 erand48(unsigned short xseed[3])
 {
-	_dorand48(xseed);
-	return ldexp((double) xseed[0], -48) +
-	       ldexp((double) xseed[1], -32) +
-	       ldexp((double) xseed[2], -16);
+	uint48 tmp;
+
+	ERAND48_BEGIN;
+	DORAND48(tmp, xseed);
+	ERAND48_END(tmp);
 }
diff --git a/lib/libc/gen/fts.3 b/lib/libc/gen/fts.3
index ee558b892c8c..b937607b48e0 100644
--- a/lib/libc/gen/fts.3
+++ b/lib/libc/gen/fts.3
@@ -25,7 +25,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd June 30, 2025
+.Dd October 1, 2025
 .Dt FTS 3
 .Os
 .Sh NAME
@@ -376,7 +376,44 @@ The
 .Fa fts_name
 field is always
 .Dv NUL Ns -terminated .
-.Sh FTS_OPEN
+.Ss Thread Safety
+The
+.Nm
+functions can safely be used in multi-threaded programs provided no
+two threads access the same
+.Vt FTS
+or
+.Vt FTSENT
+structure simultaneously.
+However, unless the
+.Dv FTS_NOCHDIR
+flag was passed to
+.Fn fts_open
+or
+.Fn fts_open_b ,
+calls to
+.Fn fts_read
+and
+.Fn fts_children
+may change the current working directory, which will affect all
+threads.
+Conversely, changing the current working directory either during or
+between calls to
+.Fn fts_read
+or
+.Fn fts_children
+(even in a single-thread program) may cause
+.Nm
+to malfunction unless the
+.Dv FTS_NOCHDIR
+flag was passed to
+.Fn fts_open
+or
+.Fn fts_open_b
+and all paths in
+.Va path_argv
+were absolute.
+.Ss Fn fts_open
 The
 .Fn fts_open
 function takes a pointer to an array of character pointers naming one
@@ -545,7 +582,7 @@ the directory traversal order is in the order listed in
 .Fa path_argv
 for the root paths, and in the order listed in the directory for
 everything else.
-.Sh FTS_OPEN_B
+.Ss Fn fts_open_b
 The
 .Fn fts_open_b
 function is identical to
@@ -554,7 +591,7 @@ except that it takes a block pointer instead of a function pointer.
 The block is copied before
 .Fn fts_open_b
 returns, so the original can safely go out of scope or be released.
-.Sh FTS_READ
+.Ss Fn fts_read
 The
 .Fn fts_read
 function returns a pointer to an
@@ -605,7 +642,7 @@ after the
 structure has been returned by the function
 .Fn fts_read
 in post-order.
-.Sh FTS_CHILDREN
+.Ss Fn fts_children
 The
 .Fn fts_children
 function returns a pointer to an
@@ -679,7 +716,7 @@ and
 .Fa fts_namelen
 fields.
 .El
-.Sh FTS_SET
+.Ss Fn fts_set
 The function
 .Fn fts_set
 allows the user application to determine further processing for the
@@ -749,7 +786,7 @@ The file may be one of those most recently returned by either
 or
 .Fn fts_read .
 .El
-.Sh FTS_CLOSE
+.Ss Fn fts_close
 The
 .Fn fts_close
 function closes a file hierarchy stream
diff --git a/lib/libc/gen/jrand48.c b/lib/libc/gen/jrand48.c
index 0a9f780a9e5c..93442439d49e 100644
--- a/lib/libc/gen/jrand48.c
+++ b/lib/libc/gen/jrand48.c
@@ -11,14 +11,13 @@
  * to anyone/anything when using this software.
  */
 
-#include <stdint.h>
-
 #include "rand48.h"
 
 long
 jrand48(unsigned short xseed[3])
 {
+	uint48 tmp;
 
-	_dorand48(xseed);
-	return ((int32_t)(((uint32_t)xseed[2] << 16) | (uint32_t)xseed[1]));
+	DORAND48(tmp, xseed);
+	return ((int)((tmp >> 16) & 0xffffffff));
 }
diff --git a/lib/libc/gen/lcong48.c b/lib/libc/gen/lcong48.c
index f13826b3d3f3..871b2110ed94 100644
--- a/lib/libc/gen/lcong48.c
+++ b/lib/libc/gen/lcong48.c
@@ -13,18 +13,10 @@
 
 #include "rand48.h"
 
-extern unsigned short _rand48_seed[3];
-extern unsigned short _rand48_mult[3];
-extern unsigned short _rand48_add;
-
 void
 lcong48(unsigned short p[7])
 {
-	_rand48_seed[0] = p[0];
-	_rand48_seed[1] = p[1];
-	_rand48_seed[2] = p[2];
-	_rand48_mult[0] = p[3];
-	_rand48_mult[1] = p[4];
-	_rand48_mult[2] = p[5];
+	LOADRAND48(_rand48_seed, &p[0]);
+	LOADRAND48(_rand48_mult, &p[3]);
 	_rand48_add = p[6];
 }
diff --git a/lib/libc/gen/lrand48.c b/lib/libc/gen/lrand48.c
index a3d0111cf4d5..cc07044b8af9 100644
--- a/lib/libc/gen/lrand48.c
+++ b/lib/libc/gen/lrand48.c
@@ -13,11 +13,9 @@
 
 #include "rand48.h"
 
-extern unsigned short _rand48_seed[3];
-
 long
 lrand48(void)
 {
-	_dorand48(_rand48_seed);
-	return ((long) _rand48_seed[2] << 15) + ((long) _rand48_seed[1] >> 1);
+	_DORAND48(_rand48_seed);
+	return (_rand48_seed >> 17) & 0x7fffffff;
 }
diff --git a/lib/libc/gen/mrand48.c b/lib/libc/gen/mrand48.c
index 15b0bfb1bd6e..f9128a6d4188 100644
--- a/lib/libc/gen/mrand48.c
+++ b/lib/libc/gen/mrand48.c
@@ -15,13 +15,9 @@
 
 #include "rand48.h"
 
-extern unsigned short _rand48_seed[3];
-
 long
 mrand48(void)
 {
-
-	_dorand48(_rand48_seed);
-	return ((int32_t)(((uint32_t)_rand48_seed[2] << 16) |
-	    (uint32_t)_rand48_seed[1]));
+	_DORAND48(_rand48_seed);
+	return ((int)((_rand48_seed >> 16) & 0xffffffff));
 }
diff --git a/lib/libc/gen/nrand48.c b/lib/libc/gen/nrand48.c
index 6c54065e7e0f..f6f4e231105c 100644
--- a/lib/libc/gen/nrand48.c
+++ b/lib/libc/gen/nrand48.c
@@ -16,6 +16,8 @@
 long
 nrand48(unsigned short xseed[3])
 {
-	_dorand48(xseed);
-	return ((long) xseed[2] << 15) + ((long) xseed[1] >> 1);
+	uint48 tmp;
+
+	DORAND48(tmp, xseed);
+	return ((tmp >> 17) & 0x7fffffff);
 }
diff --git a/lib/libc/gen/rand48.3 b/lib/libc/gen/rand48.3
index 1e47c843058e..3ea649354270 100644
--- a/lib/libc/gen/rand48.3
+++ b/lib/libc/gen/rand48.3
@@ -9,7 +9,7 @@
 .\" of any kind. I shall in no event be liable for anything that happens
 .\" to anyone/anything when using this software.
 .\"
-.Dd September 4, 2012
+.Dd September 11, 2025
 .Dt RAND48 3
 .Os
 .Sh NAME
@@ -183,5 +183,8 @@ generator calls.
 .Xr arc4random 3 ,
 .Xr rand 3 ,
 .Xr random 3
+.Sh STANDARDS
+The functions described in this page are expected to conform to
+.St -p1003.1-2008 .
 .Sh AUTHORS
 .An Martin Birgmeier
diff --git a/lib/libc/gen/rand48.h b/lib/libc/gen/rand48.h
index 9861e99683cb..d3326e851491 100644
--- a/lib/libc/gen/rand48.h
+++ b/lib/libc/gen/rand48.h
@@ -14,10 +14,11 @@
 #ifndef _RAND48_H_
 #define _RAND48_H_
 
+#include <sys/types.h>
 #include <math.h>
 #include <stdlib.h>
 
-void		_dorand48(unsigned short[3]);
+#include "fpmath.h"
 
 #define	RAND48_SEED_0	(0x330e)
 #define	RAND48_SEED_1	(0xabcd)
@@ -27,4 +28,62 @@ void		_dorand48(unsigned short[3]);
 #define	RAND48_MULT_2	(0x0005)
 #define	RAND48_ADD	(0x000b)
 
+typedef uint64_t uint48;
+
+extern uint48 _rand48_seed;
+extern uint48 _rand48_mult;
+extern uint48 _rand48_add;
+
+#define	TOUINT48(x, y, z)						\
+	((uint48)(x) + (((uint48)(y)) << 16) + (((uint48)(z)) << 32))
+
+#define	RAND48_SEED	TOUINT48(RAND48_SEED_0, RAND48_SEED_1, RAND48_SEED_2)
+#define	RAND48_MULT	TOUINT48(RAND48_MULT_0, RAND48_MULT_1, RAND48_MULT_2)
+
+#define	LOADRAND48(l, x) do {						\
+	(l) = TOUINT48((x)[0], (x)[1], (x)[2]);				\
+} while (0)
+
+#define	STORERAND48(l, x) do {						\
+	(x)[0] = (unsigned short)(l);					\
+	(x)[1] = (unsigned short)((l) >> 16);				\
+	(x)[2] = (unsigned short)((l) >> 32);				\
+} while (0)
+
+#define	_DORAND48(l) do {						\
+	(l) = (l) * _rand48_mult + _rand48_add;				\
+} while (0)
+
+#define	DORAND48(l, x) do {						\
+	LOADRAND48(l, x);						\
+	_DORAND48(l);							\
+	STORERAND48(l, x);						\
+} while (0)
+
+#define	ERAND48_BEGIN							\
+	union {								\
+		union IEEEd2bits ieee;					\
+		uint64_t u64;						\
+	} u;								\
+	int s
+
+/*
+ * Optimization for speed: assume doubles are IEEE 754 and use bit fiddling
+ * rather than converting to double.  Specifically, clamp the result to 48 bits
+ * and convert to a double in [0.0, 1.0) via division by 2^48.  Normalize by
+ * shifting the most significant bit into the implicit one position and
+ * adjusting the exponent accordingly.  The store to the exponent field
+ * overwrites the implicit one.
+ */
+#define	ERAND48_END(x) do {						\
+	u.u64 = ((x) & 0xffffffffffffULL);				\
+	if (u.u64 == 0)							\
+		return (0.0);						\
+	u.u64 <<= 5;							\
+	for (s = 0; !(u.u64 & (1LL << 52)); s++, u.u64 <<= 1)		\
+		;							\
+	u.ieee.bits.exp = 1022 - s;					\
+	return (u.ieee.d);						\
+} while (0)
+
 #endif /* _RAND48_H_ */
diff --git a/lib/libc/gen/seed48.c b/lib/libc/gen/seed48.c
index 258c4bac3c9f..f57656ce1121 100644
--- a/lib/libc/gen/seed48.c
+++ b/lib/libc/gen/seed48.c
@@ -13,24 +13,14 @@
 
 #include "rand48.h"
 
-extern unsigned short _rand48_seed[3];
-extern unsigned short _rand48_mult[3];
-extern unsigned short _rand48_add;
-
 unsigned short *
 seed48(unsigned short xseed[3])
 {
 	static unsigned short sseed[3];
 
-	sseed[0] = _rand48_seed[0];
-	sseed[1] = _rand48_seed[1];
-	sseed[2] = _rand48_seed[2];
-	_rand48_seed[0] = xseed[0];
-	_rand48_seed[1] = xseed[1];
-	_rand48_seed[2] = xseed[2];
-	_rand48_mult[0] = RAND48_MULT_0;
-	_rand48_mult[1] = RAND48_MULT_1;
-	_rand48_mult[2] = RAND48_MULT_2;
+	STORERAND48(_rand48_seed, sseed);
+	LOADRAND48(_rand48_seed, xseed);
+	_rand48_mult = RAND48_MULT;
 	_rand48_add = RAND48_ADD;
-	return sseed;
+	return (sseed);
 }
diff --git a/lib/libc/gen/srand48.c b/lib/libc/gen/srand48.c
index fd369a094c51..4b82ece72db8 100644
--- a/lib/libc/gen/srand48.c
+++ b/lib/libc/gen/srand48.c
@@ -13,18 +13,11 @@
 
 #include "rand48.h"
 
-extern unsigned short _rand48_seed[3];
-extern unsigned short _rand48_mult[3];
-extern unsigned short _rand48_add;
-
 void
 srand48(long seed)
 {
-	_rand48_seed[0] = RAND48_SEED_0;
-	_rand48_seed[1] = (unsigned short) seed;
-	_rand48_seed[2] = (unsigned short) (seed >> 16);
-	_rand48_mult[0] = RAND48_MULT_0;
-	_rand48_mult[1] = RAND48_MULT_1;
-	_rand48_mult[2] = RAND48_MULT_2;
+	_rand48_seed = TOUINT48(RAND48_SEED_0, (unsigned short)seed,
+	    (unsigned short)(seed >> 16));
+	_rand48_mult = RAND48_MULT;
 	_rand48_add = RAND48_ADD;
 }
diff --git a/lib/libc/include/port_before.h b/lib/libc/include/port_before.h
index cfc43c53f157..aa2cd394104a 100644
--- a/lib/libc/include/port_before.h
+++ b/lib/libc/include/port_before.h
@@ -5,7 +5,6 @@
 #define _LIBC		1
 #define DO_PTHREADS	1
 #define USE_POLL	1
-#define HAVE_MD5	1
 
 #define ISC_SOCKLEN_T	socklen_t
 #define ISC_FORMAT_PRINTF(fmt, args) \
diff --git a/lib/libc/md/Makefile.inc b/lib/libc/md/Makefile.inc
deleted file mode 100644
index 82c5f0670485..000000000000
--- a/lib/libc/md/Makefile.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-.PATH: ${SRCTOP}/sys/kern
-
-SRCS+=	md5c.c
diff --git a/lib/libc/nls/Makefile.inc b/lib/libc/nls/Makefile.inc
index f26e04c187a5..c211026aba72 100644
--- a/lib/libc/nls/Makefile.inc
+++ b/lib/libc/nls/Makefile.inc
@@ -12,6 +12,11 @@ MAN+=	catclose.3 catgets.3 catopen.3
 #       for translators.
 
 NLSNAME=	libc
+# We don't want libc's NLS catalogues to be installed in the clibs package.
+# Put them in locales instead, since anyone interested in NLS will have
+# that installed.
+NLSPACKAGE=	locales
+
 NLS+=	be_BY.UTF-8
 NLS+=	ca_ES.ISO8859-1
 NLS+=	de_DE.ISO8859-1
diff --git a/lib/libc/resolv/Symbol.map b/lib/libc/resolv/Symbol.map
index 6b9c43298fb5..26daecbe2eff 100644
--- a/lib/libc/resolv/Symbol.map
+++ b/lib/libc/resolv/Symbol.map
@@ -103,6 +103,5 @@ FBSD_1.0 {
 };
 
 FBSD_1.4 {
-	__res_rndinit;
 	__res_nrandomid;
 };
diff --git a/lib/libc/resolv/res_init.c b/lib/libc/resolv/res_init.c
index 71ab2dcb7038..5a2fce013c8c 100644
--- a/lib/libc/resolv/res_init.c
+++ b/lib/libc/resolv/res_init.c
@@ -86,19 +86,6 @@
 #include <unistd.h>
 #include <netdb.h>
 
-#ifndef HAVE_MD5
-# include "../dst/md5.h"
-#else
-# ifdef SOLARIS2
-#  include <sys/md5.h>
-# elif _LIBC
-# include <md5.h>
-# endif
-#endif
-#ifndef _MD5_H_
-# define _MD5_H_ 1	/*%< make sure we do not include rsaref md5.h file */
-#endif
-
 #include "un-namespace.h"
 
 #include "port_after.h"
@@ -184,8 +171,6 @@ __res_vinit(res_state statp, int preinit) {
 		statp->options = RES_DEFAULT;
 	}
 
-	statp->_rnd = malloc(16);
-	res_rndinit(statp);
 	statp->id = res_nrandomid(statp);
 
 	memset(u, 0, sizeof(u));
@@ -733,48 +718,18 @@ net_mask(struct in_addr in)		/*!< XXX - should really use system's version of th
 }
 #endif
 
-static u_char srnd[16];
-
 void
-res_rndinit(res_state statp)
+freebsd15_res_rndinit(res_state statp)
 {
-	struct timeval now;
-	u_int32_t u32;
-	u_int16_t u16;
-	u_char *rnd = statp->_rnd == NULL ? srnd : statp->_rnd;
-
-	gettimeofday(&now, NULL);
-	u32 = now.tv_sec;
-	memcpy(rnd, &u32, 4);
-	u32 = now.tv_usec;
-	memcpy(rnd + 4, &u32, 4);
-	u32 += now.tv_sec;
-	memcpy(rnd + 8, &u32, 4);
-	u16 = getpid();
-	memcpy(rnd + 12, &u16, 2);
+	(void)statp;
 }
+__sym_compat(__res_rndinit, freebsd15_res_rndinit, FBSD_1.4);
 
 u_int
 res_nrandomid(res_state statp) {
-	struct timeval now;
-	u_int16_t u16;
-	MD5_CTX ctx;
-	u_char *rnd = statp->_rnd == NULL ? srnd : statp->_rnd;
-
-	gettimeofday(&now, NULL);
-	u16 = (u_int16_t) (now.tv_sec ^ now.tv_usec);
-	memcpy(rnd + 14, &u16, 2);
-#ifndef HAVE_MD5
-	MD5_Init(&ctx);
-	MD5_Update(&ctx, rnd, 16);
-	MD5_Final(rnd, &ctx);
-#else
-	MD5Init(&ctx);
-	MD5Update(&ctx, rnd, 16);
-	MD5Final(rnd, &ctx);
-#endif
-	memcpy(&u16, rnd + 14, 2);
-	return ((u_int) u16);
+	(void) statp;
+
+	return ((u_int)(arc4random() & 0xffff));
 }
 
 /*%
@@ -808,10 +763,6 @@ res_ndestroy(res_state statp) {
 		free(statp->_u._ext.ext);
 		statp->_u._ext.ext = NULL;
 	}
-	if (statp->_rnd != NULL) {
-		free(statp->_rnd);
-		statp->_rnd = NULL;
-	}
 	statp->options &= ~RES_INIT;
 }
 
diff --git a/lib/libc/stdlib/Makefile.inc b/lib/libc/stdlib/Makefile.inc
index ca199a669be1..e7b9955b9646 100644
--- a/lib/libc/stdlib/Makefile.inc
+++ b/lib/libc/stdlib/Makefile.inc
@@ -10,7 +10,7 @@ MISRCS+=C99_Exit.c a64l.c abort.c abs.c atexit.c atof.c atoi.c atol.c atoll.c \
 	insque.c l64a.c labs.c ldiv.c llabs.c lldiv.c lsearch.c \
 	merge.c mergesort_b.c ptsname.c qsort.c qsort_r.c qsort_r_compat.c \
 	qsort_s.c quick_exit.c radixsort.c rand.c \
-	random.c reallocarray.c reallocf.c realpath.c remque.c \
+	random.c reallocarray.c reallocf.c realpath.c recallocarray.c remque.c \
 	set_constraint_handler_s.c strfmon.c strtoimax.c \
 	strtol.c strtold.c strtoll.c strtoq.c strtoul.c strtonum.c strtoull.c \
 	strtoumax.c strtouq.c system.c tdelete.c tfind.c tsearch.c twalk.c
@@ -76,6 +76,7 @@ MLINKS+=random.3 initstate.3 \
 	random.3 srandom.3 \
 	random.3 srandomdev.3
 MLINKS+=radixsort.3 sradixsort.3
+MLINKS+=reallocarray.3 recallocarray.3
 MLINKS+=set_constraint_handler_s.3 abort_handler_s.3
 MLINKS+=set_constraint_handler_s.3 ignore_handler_s.3
 MLINKS+=strfmon.3 strfmon_l.3
diff --git a/lib/libc/stdlib/Symbol.map b/lib/libc/stdlib/Symbol.map
index 2b79ca2ece8b..53d71bcafb7d 100644
--- a/lib/libc/stdlib/Symbol.map
+++ b/lib/libc/stdlib/Symbol.map
@@ -131,6 +131,10 @@ FBSD_1.8 {
 	getenv_r;
 };
 
+FBSD_1.9 {
+	recallocarray;
+};
+
 FBSDprivate_1.0 {
 	__system;
 	_system;
diff --git a/lib/libc/stdlib/reallocarray.3 b/lib/libc/stdlib/reallocarray.3
index 80035c67a497..9a2ab5c7a840 100644
--- a/lib/libc/stdlib/reallocarray.3
+++ b/lib/libc/stdlib/reallocarray.3
@@ -26,7 +26,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd May 1, 2015
+.Dd October 2, 2025
 .Dt REALLOCARRAY 3
 .Os
 .Sh NAME
@@ -38,6 +38,8 @@
 .In stdlib.h
 .Ft void *
 .Fn reallocarray "void *ptr" "size_t nmemb" "size_t size"
+.Ft void *
+.Fn recallocarray "void *ptr" "size_t oldnmeb" "size_t nmemb" size_t size"
 .Sh DESCRIPTION
 The
 .Fn reallocarray
@@ -52,6 +54,33 @@ and checks for integer overflow in the calculation
 .Fa nmemb
 *
 .Fa size .
+.Pp
+The
+.Fn recallocarray
+function is similar to the
+.Fn reallocarray
+function
+except it ensures newly allocated memory is cleared similar to
+.Fn calloc .
+If
+.Fa ptr
+is
+.Dv NULL ,
+.Fa oldnmemb
+is ignored and the call	is equivalent to
+.Fn calloc .
+If
+.Fa ptr
+is not
+.Dv NULL ,
+.Fa oldnmemb
+must be a value such that
+.Fa oldnmemb
+*
+.Fa size
+is the size of the earlier allocation that returned
+.Fa ptr ,
+otherwise the behaviour is undefined.
 .Sh RETURN VALUES
 The
 .Fn reallocarray
@@ -142,3 +171,9 @@ function first appeared in
 .Ox 5.6
 and
 .Fx 11.0 .
+The
+.Fn recallocarray
+function first appeared in
+.Ox 6.1
+and
+.Fx 16.0 .
diff --git a/lib/libc/stdlib/reallocarray.c b/lib/libc/stdlib/reallocarray.c
index 0868804486cc..3632734c84de 100644
--- a/lib/libc/stdlib/reallocarray.c
+++ b/lib/libc/stdlib/reallocarray.c
@@ -17,23 +17,19 @@
 
 #include <sys/types.h>
 #include <errno.h>
+#include <stdckdint.h>
 #include <stdint.h>
 #include <stdlib.h>
 
-/*
- * This is sqrt(SIZE_MAX+1), as s1*s2 <= SIZE_MAX
- * if both s1 < MUL_NO_OVERFLOW and s2 < MUL_NO_OVERFLOW
- */
-#define MUL_NO_OVERFLOW	((size_t)1 << (sizeof(size_t) * 4))
-
 void *
 reallocarray(void *optr, size_t nmemb, size_t size)
 {
+	size_t nbytes;
 
-	if ((nmemb >= MUL_NO_OVERFLOW || size >= MUL_NO_OVERFLOW) &&
-	    nmemb > 0 && SIZE_MAX / nmemb < size) {
+	if (ckd_mul(&nbytes, nmemb, size)) {
 		errno = ENOMEM;
 		return (NULL);
 	}
-	return (realloc(optr, size * nmemb));
+
+	return (realloc(optr, nbytes));
 }
diff --git a/lib/libopenbsd/recallocarray.c b/lib/libc/stdlib/recallocarray.c
index 11e1fda744c7..cbf1fb2470cf 100644
--- a/lib/libopenbsd/recallocarray.c
+++ b/lib/libc/stdlib/recallocarray.c
@@ -16,17 +16,12 @@
  */
 
 #include <errno.h>
+#include <stdckdint.h>
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
 #include <unistd.h>
 
-/*
- * This is sqrt(SIZE_MAX+1), as s1*s2 <= SIZE_MAX
- * if both s1 < MUL_NO_OVERFLOW and s2 < MUL_NO_OVERFLOW
- */
-#define MUL_NO_OVERFLOW ((size_t)1 << (sizeof(size_t) * 4))
-
 void *recallocarray(void *, size_t, size_t, size_t);
 
 void *
@@ -38,19 +33,15 @@ recallocarray(void *ptr, size_t oldnmemb, size_t newnmemb, size_t size)
 	if (ptr == NULL)
 		return calloc(newnmemb, size);
 
-	if ((newnmemb >= MUL_NO_OVERFLOW || size >= MUL_NO_OVERFLOW) &&
-	    newnmemb > 0 && SIZE_MAX / newnmemb < size) {
+	if (ckd_mul(&newsize, newnmemb, size)) {
 		errno = ENOMEM;
 		return NULL;
 	}
-	newsize = newnmemb * size;
 
-	if ((oldnmemb >= MUL_NO_OVERFLOW || size >= MUL_NO_OVERFLOW) &&
-	    oldnmemb > 0 && SIZE_MAX / oldnmemb < size) {
+	if (ckd_mul(&oldsize, oldnmemb, size)) {
 		errno = EINVAL;
 		return NULL;
 	}
-	oldsize = oldnmemb * size;
 	
 	/*
 	 * Don't bother too much if we're shrinking just a bit,
diff --git a/lib/libc/stdtime/Makefile.inc b/lib/libc/stdtime/Makefile.inc
index 647cbe6f40ba..1baa39a6c0a6 100644
--- a/lib/libc/stdtime/Makefile.inc
+++ b/lib/libc/stdtime/Makefile.inc
@@ -32,4 +32,5 @@ MLINKS+=strftime.3 strftime_l.3
 MLINKS+=strptime.3 strptime_l.3
 MLINKS+=time2posix.3 posix2time.3
 MLINKS+=tzset.3 daylight.3 \
-	tzset.3 timezone.3
+	tzset.3 timezone.3 \
+	tzset.3 tzname.3
diff --git a/lib/libc/stdtime/tzset.3 b/lib/libc/stdtime/tzset.3
index 94ccbec9aba7..33e6a556306d 100644
--- a/lib/libc/stdtime/tzset.3
+++ b/lib/libc/stdtime/tzset.3
@@ -28,7 +28,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd December 25, 2023
+.Dd September 30, 2025
 .Dt TZSET 3
 .Os
 .Sh NAME
@@ -58,8 +58,8 @@ specifies how this is done.
 .Pp
 If
 .Ev TZ
-does not appear in the environment, the best available approximation to
-local wall clock time, as specified by the
+does not appear in the environment, the best available approximation
+to local wall clock time, as specified by the
 .Xr tzfile 5 Ns -format
 file
 .Pa /etc/localtime
@@ -68,9 +68,7 @@ is used.
 If
 .Ev TZ
 appears in the environment but its value is a null string, Coordinated
-Universal Time
-.Pq Tn UTC
-is used (without leap second correction).
+Universal Time (UTC) is used (without leap second correction).
 .Pp
 If
 .Ev TZ
@@ -81,13 +79,12 @@ the rest of its value is used as a pathname of a
 file from which to read the time conversion information.
 If the first character of the pathname is a slash
 .Pq Ql /
-it is used as
-an absolute pathname; otherwise, it is used as a pathname relative to
-the system time conversion information directory.
+it is used as an absolute pathname; otherwise, it is used as a
+pathname relative to the system time conversion information directory.
 .Pp
-If its value does not begin with a colon, it is first used as the pathname
-of a file (as described above) from which to read the time conversion
-information.
+If its value does not begin with a colon, it is first used as the
+pathname of a file (as described above) from which to read the time
+conversion information.
 If that file cannot be read, the value is then interpreted as a direct
 specification (the format is described below) of the time conversion
 information.
@@ -96,24 +93,23 @@ If the
 .Ev TZ
 environment variable does not specify a
 .Xr tzfile 5 Ns -format
-file and cannot be interpreted as a direct specification,
-.Tn UTC
-is used.
+file and cannot be interpreted as a direct specification, UTC is used.
 .Pp
 After the first call to
 .Nm tzset ,
 the
 .Vt timezone
-variable is set to the difference, in seconds, between Coordinated Universal
-Time (UTC) and the local time.
+variable is set to the difference, in seconds, between Coordinated
+Universal Time (UTC) and the local time.
 The
 .Vt daylight
 variable is set to 0 if the local timezone is observing standard time.
-It is set to 1 if the local timezone ever observes an alternate time, such as summer time.
+It is set to 1 if the local timezone ever observes an alternate time,
+such as summer time.
 The first element of the
 .Vt tzname
-array is the timezone name of standard time, while the second element is the
-name of the altnerative time zone.
+array is the timezone name of standard time, while the second element
+is the name of the altnerative time zone.
 .Sh SPECIFICATION FORMAT
 When
 .Ev TZ
@@ -151,8 +147,7 @@ minus
 .Pq Ql \- ,
 plus
 .Pq Ql + ,
-and
-.Tn ASCII
+and ASCII
 .Dv NUL
 are allowed.
 .It Em offset
@@ -294,10 +289,8 @@ by the
 file
 .Em posixrules
 in the system time conversion information directory are used, with the
-standard and summer time offsets from
-.Tn UTC
-replaced by those specified by
-the
+standard and summer time offsets from UTC replaced by those specified
+by the
 .Em offset
 values in
 .Ev TZ .
@@ -315,20 +308,14 @@ local time zone file
 .It Pa /usr/share/zoneinfo
 time zone directory
 .It Pa /usr/share/zoneinfo/posixrules
-rules for
-.Tn POSIX Ns -style
-.Tn TZ Ns 's
+rules for POSIX-style TZs
 .It Pa /usr/share/zoneinfo/Etc/GMT
-for
-.Tn UTC
-leap seconds
+for UTC leap seconds
 .El
 .Pp
 If the file
 .Pa /usr/share/zoneinfo/UTC
-does not exist,
-.Tn UTC
-leap seconds are loaded from
+does not exist, UTC leap seconds are loaded from
 .Pa /usr/share/zoneinfo/posixrules .
 .Sh SEE ALSO
 .Xr date 1 ,
diff --git a/lib/libc/tests/stdtime/detect_tz_changes_test.c b/lib/libc/tests/stdtime/detect_tz_changes_test.c
index fe6b04357331..06c31c9fbc3d 100644
--- a/lib/libc/tests/stdtime/detect_tz_changes_test.c
+++ b/lib/libc/tests/stdtime/detect_tz_changes_test.c
@@ -24,10 +24,12 @@
 
 #include <atf-c.h>
 
-static const struct tzcase {
+struct tzcase {
 	const char *tzfn;
 	const char *expect;
-} tzcases[] = {
+};
+
+static const struct tzcase tzcases[] = {
 	/*
 	 * A handful of time zones and the expected result of
 	 * strftime("%z (%Z)", tm) when that time zone is active
@@ -43,7 +45,8 @@ static const struct tzcase {
 	{ "UTC",		"+0000 (UTC)"	},
 	{ 0 },
 };
-
+static const struct tzcase utc = { "UTC", "+0000 (UTC)" };
+static const struct tzcase invalid = { "invalid", "+0000 (-00)" };
 static const time_t then = 1751328000; /* 2025-07-01 00:00:00 UTC */
 
 static bool debugging;
@@ -139,7 +142,7 @@ ATF_TC_BODY(tz_invalid_file, tc)
 	ATF_REQUIRE_EQ(0, chdir("/"));
 	/* check timezone */
 	unsetenv("TZ");
-	test_tz("+0000 (-00)");
+	test_tz(invalid.expect);
 }
 
 ATF_TC(thin_jail);
@@ -366,12 +369,8 @@ test_tz_env(const char *tzval, const char *expect)
 	test_tz(expect);
 }
 
-ATF_TC(tz_env);
-ATF_TC_HEAD(tz_env, tc)
-{
-	atf_tc_set_md_var(tc, "descr", "Test TZ environment variable");
-}
-ATF_TC_BODY(tz_env, tc)
+static void
+tz_env_common(void)
 {
 	char path[MAXPATHLEN];
 	const struct tzcase *tzcase = tzcases;
@@ -394,6 +393,18 @@ ATF_TC_BODY(tz_env, tc)
 	}
 }
 
+ATF_TC(tz_env);
+ATF_TC_HEAD(tz_env, tc)
+{
+	atf_tc_set_md_var(tc, "descr", "Test TZ environment variable");
+}
+ATF_TC_BODY(tz_env, tc)
+{
+	tz_env_common();
+	/* escape from TZDIR is permitted when not setugid */
+	test_tz_env("../zoneinfo/UTC", utc.expect);
+}
+
 
 ATF_TC(tz_invalid_env);
 ATF_TC_HEAD(tz_invalid_env, tc)
@@ -403,8 +414,8 @@ ATF_TC_HEAD(tz_invalid_env, tc)
 }
 ATF_TC_BODY(tz_invalid_env, tc)
 {
-	test_tz_env("invalid", "+0000 (-00)");
-	test_tz_env(":invalid", "+0000 (-00)");
+	test_tz_env("invalid", invalid.expect);
+	test_tz_env(":invalid", invalid.expect);
 }
 
 ATF_TC(setugid);
@@ -443,7 +454,9 @@ ATF_TC_BODY(tz_env_setugid, tc)
 {
 	ATF_REQUIRE_EQ(0, seteuid(UID_NOBODY));
 	ATF_REQUIRE(issetugid());
-	ATF_TC_BODY_NAME(tz_env)(tc);
+	tz_env_common();
+	/* escape from TZDIR is not permitted when setugid */
+	test_tz_env("../zoneinfo/UTC", invalid.expect);
 }
 
 ATF_TP_ADD_TCS(tp)
diff --git a/lib/libdiff/Makefile b/lib/libdiff/Makefile
index 8541ff424de2..25f849a69e05 100644
--- a/lib/libdiff/Makefile
+++ b/lib/libdiff/Makefile
@@ -8,7 +8,7 @@ INTERNALLIB=	# API not published or supported.
 
 SRCS=	diff_atomize_text.c diff_main.c diff_myers.c \
 	diff_patience.c diff_output.c diff_output_plain.c \
-	diff_output_unidiff.c diff_output_edscript.c recallocarray.c
+	diff_output_unidiff.c diff_output_edscript.c
 
 WARNS=
 CFLAGS+= -I${SRCTOP}/contrib/libdiff/compat/include
diff --git a/lib/libedit/Makefile b/lib/libedit/Makefile
index f0254c1f42bc..c7a54253dae9 100644
--- a/lib/libedit/Makefile
+++ b/lib/libedit/Makefile
@@ -1,7 +1,5 @@
 #	$NetBSD: Makefile,v 1.56 2016/03/02 19:24:20 christos Exp $
 
-PACKAGE=clibs
-
 EDITDIR=	${SRCTOP}/contrib/libedit
 .PATH: ${EDITDIR}
 
@@ -93,6 +91,7 @@ tc1.o: ${EDITDIR}/TEST/tc1.c
 test: tc1.o libedit.a ${DPADD} ${LIBTERMCAP}
 	${CC} ${CFLAGS} ${.ALLSRC} -o ${.TARGET} libedit.a ${LDADD}
 
+.include "Makefile.inc"
 .include <bsd.lib.mk>
 
 CWARNFLAGS.chartype.c=	${NO_WUSE_AFTER_FREE}
diff --git a/lib/libedit/Makefile.inc b/lib/libedit/Makefile.inc
new file mode 100644
index 000000000000..9ec65b0d266f
--- /dev/null
+++ b/lib/libedit/Makefile.inc
@@ -0,0 +1 @@
+PACKAGE?=runtime
diff --git a/lib/libexpat/expat_config.h b/lib/libexpat/expat_config.h
index 64da66e1cf6f..565404f1577b 100644
--- a/lib/libexpat/expat_config.h
+++ b/lib/libexpat/expat_config.h
@@ -89,7 +89,7 @@
 #define PACKAGE_NAME "expat"
 
 /* Define to the full name and version of this package. */
-#define PACKAGE_STRING "expat 2.7.2"
+#define PACKAGE_STRING "expat 2.7.3"
 
 /* Define to the one symbol short name of this package. */
 #define PACKAGE_TARNAME "expat"
@@ -98,7 +98,7 @@
 #define PACKAGE_URL ""
 
 /* Define to the version of this package. */
-#define PACKAGE_VERSION "2.7.2"
+#define PACKAGE_VERSION "2.7.3"
 
 /* Define to 1 if all of the C89 standard headers exist (not just the ones
    required in a freestanding environment). This macro is provided for
@@ -106,7 +106,7 @@
 #define STDC_HEADERS 1
 
 /* Version number of package */
-#define VERSION "2.7.2"
+#define VERSION "2.7.3"
 
 /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
    significant byte first (like Motorola and SPARC, unlike Intel). */
diff --git a/lib/libexpat/libbsdxml.3 b/lib/libexpat/libbsdxml.3
index 60aa64fba20d..d25249bbc155 100644
--- a/lib/libexpat/libbsdxml.3
+++ b/lib/libexpat/libbsdxml.3
@@ -23,7 +23,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"/
-.Dd April 7, 2025
+.Dd September 28, 2025
 .Dt LIBBSDXML 3
 .Os
 .Sh NAME
@@ -34,7 +34,7 @@
 .Sh DESCRIPTION
 The
 .Nm
-library is a verbatim copy of the eXpat XML library version 2.7.2.
+library is a verbatim copy of the eXpat XML library version 2.7.3.
 .Pp
 The
 .Nm
diff --git a/lib/libfido2/Makefile b/lib/libfido2/Makefile
index 10c008967e3d..021a32dd514b 100644
--- a/lib/libfido2/Makefile
+++ b/lib/libfido2/Makefile
@@ -43,7 +43,6 @@ SRCS+=	u2f.c
 SRCS+=	util.c
 
 SRCS+=	openbsd-compat/freezero.c
-SRCS+=	openbsd-compat/recallocarray.c
 
 CFLAGS+= -I ${DIST}/src -I${SRCTOP}/contrib/libcbor/src -I${.CURDIR}/../libcbor
 CFLAGS+= -D_FIDO_INTERNAL
diff --git a/lib/liblzma/Makefile b/lib/liblzma/Makefile
index 27e0521f5884..9c6ece74ffd0 100644
--- a/lib/liblzma/Makefile
+++ b/lib/liblzma/Makefile
@@ -1,4 +1,6 @@
-PACKAGE=lib${LIB}
+PACKAGE=	xz
+LIB_PACKAGE=
+
 LIB=		lzma
 LZMADIR=	${SRCTOP}/contrib/xz/src/liblzma
 
diff --git a/lib/libmixer/Makefile b/lib/libmixer/Makefile
index a0bb37a85fb8..49621ad1f188 100644
--- a/lib/libmixer/Makefile
+++ b/lib/libmixer/Makefile
@@ -1,3 +1,5 @@
+PACKAGE=	sound
+
 LIB=		mixer
 SRCS=		${LIB}.c
 INCS=		${LIB}.h
diff --git a/lib/libopenbsd/Makefile b/lib/libopenbsd/Makefile
index 53bd0200934f..80ae0f90621a 100644
--- a/lib/libopenbsd/Makefile
+++ b/lib/libopenbsd/Makefile
@@ -1,8 +1,12 @@
 LIB=	openbsd
 SRCS=	imsg-buffer.c \
 	imsg.c \
-	ohash.c \
-	recallocarray.c
+	ohash.c
+.if defined(BOOTSTRAPPING)
+.PATH:	${SRCTOP}/lib/libc/stdlib
+SRCS+=	recallocarray.c
+.endif
+
 .if !defined(BOOTSTRAPPING)
 # Skip getdtablecount.c when bootstrapping since it doesn't compile for Linux
 # and is not used by any of the bootstrap tools
diff --git a/lib/libpfctl/libpfctl.c b/lib/libpfctl/libpfctl.c
index 4b579de38ad0..8c4b26b98054 100644
--- a/lib/libpfctl/libpfctl.c
+++ b/lib/libpfctl/libpfctl.c
@@ -561,6 +561,10 @@ pfctl_free_status(struct pfctl_status *status)
 		free(c->name);
 		free(c);
 	}
+	TAILQ_FOREACH_SAFE(c, &status->ncounters, entry, tmp) {
+		free(c->name);
+		free(c);
+	}
 
 	free(status);
 }
diff --git a/lib/libsamplerate/Makefile b/lib/libsamplerate/Makefile
index 6ca87d8b20ca..4c55d5c2cb82 100644
--- a/lib/libsamplerate/Makefile
+++ b/lib/libsamplerate/Makefile
@@ -1,5 +1,7 @@
 .PATH:		${SRCTOP}/contrib/libsamplerate
 
+PACKAGE=	sound
+
 LIB=		samplerate
 PRIVATELIB=
 
diff --git a/lib/libsdp/Makefile b/lib/libsdp/Makefile
index f0153e756dfd..8177c9bdbd1a 100644
--- a/lib/libsdp/Makefile
+++ b/lib/libsdp/Makefile
@@ -1,6 +1,7 @@
 # $Id: Makefile,v 1.2 2003/09/07 20:34:19 max Exp $
 
-PACKAGE=lib${LIB}
+PACKAGE=	bluetooth
+LIB_PACKAGE=
 LIB=		sdp
 MAN=		sdp.3
 
diff --git a/lib/libstdbuf/Makefile b/lib/libstdbuf/Makefile
index 102c6745c593..9e289e0018fc 100644
--- a/lib/libstdbuf/Makefile
+++ b/lib/libstdbuf/Makefile
@@ -1,6 +1,5 @@
 .include <bsd.own.mk>
 
-PACKAGE=lib${LIB}
 LIB=		stdbuf
 SRCS=		stdbuf.c
 SHLIB_MAJOR=	1
diff --git a/lib/libstdthreads/Makefile b/lib/libstdthreads/Makefile
index 49d024052420..dcdac58efc12 100644
--- a/lib/libstdthreads/Makefile
+++ b/lib/libstdthreads/Makefile
@@ -1,4 +1,4 @@
-PACKAGE=lib${LIB}
+PACKAGE=runtime
 LIB=	stdthreads
 SHLIB_MAJOR= 0
 
diff --git a/lib/libutil/login.conf.5 b/lib/libutil/login.conf.5
index 27f37fb5fc30..942f3ecd2661 100644
--- a/lib/libutil/login.conf.5
+++ b/lib/libutil/login.conf.5
@@ -17,7 +17,7 @@
 .\" 5. Modifications may be freely made to this file providing the above
 .\"    conditions are met.
 .\"
-.Dd June 28, 2023
+.Dd September 25, 2025
 .Dt LOGIN.CONF 5
 .Os
 .Sh NAME
@@ -496,7 +496,7 @@ lists.
 .Xr pam 3 ,
 .Xr passwd 5 ,
 .Xr ttys 5 ,
-.Xr ftpd 8 ,
+.Xr ftpd 8 Pq Pa ports/ftp/freebsd-ftpd ,
 .Xr pam_passwdqc 8
 .Sh HISTORY
 The file
diff --git a/lib/liby/Makefile b/lib/liby/Makefile
index 93f72ee440f8..ace8f8457d22 100644
--- a/lib/liby/Makefile
+++ b/lib/liby/Makefile
@@ -1,4 +1,4 @@
-PACKAGE=lib${LIB}
+PACKAGE=toolchain
 LIB=	y
 SRCS=	main.c yyerror.c
 NO_PIC=
diff --git a/lib/ncurses/Makefile.inc b/lib/ncurses/Makefile.inc
index f2ed84e2e38f..eea49908474c 100644
--- a/lib/ncurses/Makefile.inc
+++ b/lib/ncurses/Makefile.inc
@@ -1,5 +1,6 @@
 # This is to include src/lib/Makefile.inc
 
+PACKAGE?=	ncurses
 WARNS?=	3
 
 .include "../Makefile.inc"
diff --git a/lib/ncurses/form/Makefile b/lib/ncurses/form/Makefile
index d4774a5f51a8..7d8963b05ae8 100644
--- a/lib/ncurses/form/Makefile
+++ b/lib/ncurses/form/Makefile
@@ -3,7 +3,6 @@
 
 SRCDIR=	${NCURSES_DIR}/form
 
-PACKAGE=	clibs
 LIB=	formw
 SHLIB_MAJOR=	6
 
diff --git a/lib/ncurses/ncurses/Makefile b/lib/ncurses/ncurses/Makefile
index 512a452ad6d0..b60760281b39 100644
--- a/lib/ncurses/ncurses/Makefile
+++ b/lib/ncurses/ncurses/Makefile
@@ -1,4 +1,3 @@
-PACKAGE=	clibs
 SHLIBDIR?=	/lib
 
 .include <src.opts.mk>
diff --git a/lib/ncurses/panel/Makefile b/lib/ncurses/panel/Makefile
index a51129df42e3..dfb478aa5f5b 100644
--- a/lib/ncurses/panel/Makefile
+++ b/lib/ncurses/panel/Makefile
@@ -3,7 +3,6 @@
 
 SRCDIR=	${NCURSES_DIR}/panel
 
-PACKAGE=	clibs
 LIB=	panelw
 SHLIB_MAJOR=	6
 
diff --git a/lib/ncurses/tinfo/Makefile b/lib/ncurses/tinfo/Makefile
index 476df54bb72a..8f01557edaee 100644
--- a/lib/ncurses/tinfo/Makefile
+++ b/lib/ncurses/tinfo/Makefile
@@ -1,4 +1,3 @@
-PACKAGE=	clibs
 SHLIBDIR?=	/lib
 
 .include <src.opts.mk>
diff --git a/lib/nss_tacplus/Makefile b/lib/nss_tacplus/Makefile
index f39788cfbdea..c85297a7dbaa 100644
--- a/lib/nss_tacplus/Makefile
+++ b/lib/nss_tacplus/Makefile
@@ -1,9 +1,9 @@
 LIB=		nss_tacplus
-SRCS=		${LIB}.8
+SRCS=		${LIB}.c
 SHLIB_MAJOR=	1
 SHLIB_NAME=	${LIB}.so.${SHLIB_MAJOR}
 LIBADD=		tacplus
-MK_INSTALLIB=	no
+MK_INSTALLLIB=	no
 MAN=		${LIB}.8
 
 .include <bsd.lib.mk>
diff --git a/libexec/Makefile b/libexec/Makefile
index 55e586434087..e87b48b153a8 100644
--- a/libexec/Makefile
+++ b/libexec/Makefile
@@ -10,7 +10,6 @@ SUBDIR=	${_atf} \
 	flua \
 	getty \
 	${_hyperv} \
-	kgdb \
 	${_mail.local} \
 	${_makewhatis.local} \
 	${_mknetid} \
@@ -54,10 +53,6 @@ SUBDIR+=	fingerd
 _phttpget=	phttpget
 .endif
 
-.if ${MK_FTP} != "no"
-SUBDIR+=	ftpd
-.endif
-
 .if ${MK_MAIL} != "no"
 _comsat=	comsat
 .endif
diff --git a/libexec/blacklistd-helper/Makefile b/libexec/blacklistd-helper/Makefile
index 50fd3b5c982b..d32b69c278a8 100644
--- a/libexec/blacklistd-helper/Makefile
+++ b/libexec/blacklistd-helper/Makefile
@@ -1,5 +1,7 @@
 BLOCKLIST_DIR=${SRCTOP}/contrib/blocklist
 
+PACKAGE=	blocklist
+
 SCRIPTS=	${BLOCKLIST_DIR}/libexec/blacklistd-helper
 
 .include <bsd.prog.mk>
diff --git a/libexec/flua/Makefile b/libexec/flua/Makefile
index 86d27c0653d4..23de404710d0 100644
--- a/libexec/flua/Makefile
+++ b/libexec/flua/Makefile
@@ -1,10 +1,42 @@
 .include <src.lua.mk>
 
-SUBDIR+=	libfreebsd
-SUBDIR+=	libhash
-SUBDIR+=	libjail
-SUBDIR+=	libucl
-SUBDIR+=	liblyaml
+# New flua modules should be added here rather than to SUBDIR so that we can do
+# the right thing for both bootstrap flua and target flua.  The former does not
+# do any shared libs, so we just build them all straight into flua itself rather
+# than mucking about with the infrastructure to make them linkable -- thus, why
+# these are all structured to have a Makefile that describes what we want
+# *installed*, and a Makefile.inc that describes what we need to *build*.
+FLUA_MODULES+=	lfbsd
+FLUA_MODULES+=	lfs
+FLUA_MODULES+=	libhash
+.ifndef BOOTSTRAPPING
+# Bootstrap flua can't usefully do anything with libjail anyways, because it
+# can't assume it's being run on a system that even supports jails.
+FLUA_MODULES+=	libjail
+.endif
+FLUA_MODULES+=	libucl
+FLUA_MODULES+=	liblyaml
+
+.ifdef BOOTSTRAPPING
+# libfreebsd is generally omitted from the bootstrap flua because its
+# functionality largely assumes a FreeBSD kernel/system headers, so it doesn't
+# really offer functionality that we can use in bootstrap.
+CFLAGS+=	-I${.CURDIR} -DBOOTSTRAPPING
+
+SHAREDIR=	${WORLDTMP}/legacy/usr/share/flua
+FLUA_PATH=	${SHAREDIR}/?.lua;${SHAREDIR}/?/init.lua
+CFLAGS+=	-DBOOTSTRAP_FLUA_PATH=\"${FLUA_PATH:Q}\"
+
+.for mod in ${FLUA_MODULES}
+.include "${mod}/Makefile.inc"
+.endfor
+
+.else
+
+FLUA_MODULES+=	libfreebsd
+SUBDIR+=	${FLUA_MODULES}
+
+.endif
 
 LUASRC?=	${SRCTOP}/contrib/lua/src
 .PATH: ${LUASRC}
@@ -14,7 +46,7 @@ WARNS?=	3
 
 CWARNFLAGS.gcc+=	-Wno-format-nonliteral
 
-LIBADD=	lua
+LIBADD+=	lua
 
 # Entry point
 SRCS+=	lua.c
@@ -22,7 +54,7 @@ SRCS+=	lua.c
 # FreeBSD Extensions
 .PATH: ${.CURDIR}/modules
 SRCS+=	linit_flua.c
-SRCS+=	lfs.c lposix.c lfbsd.c
+SRCS+=	lposix.c
 
 CFLAGS+=	-I${SRCTOP}/lib/liblua -I${.CURDIR}/modules -I${LUASRC}
 CFLAGS+=	-DLUA_PROGNAME="\"${PROG}\""
diff --git a/libexec/flua/Makefile.inc b/libexec/flua/Makefile.inc
index 34505d54d7df..37a49e258ecb 100644
--- a/libexec/flua/Makefile.inc
+++ b/libexec/flua/Makefile.inc
@@ -2,4 +2,9 @@ SHLIBDIR?=	${LIBDIR}/flua
 
 CFLAGS+=	\
 		-I${SRCTOP}/contrib/lua/src \
-		-I${SRCTOP}/lib/liblua
+		-I${SRCTOP}/lib/liblua \
+		-I${SRCTOP}/libexec/flua
+
+.ifdef BOOTSTRAPPING
+CFLAGS+=	-DBOOTSTRAPPING
+.endif
diff --git a/libexec/flua/bootstrap.h b/libexec/flua/bootstrap.h
new file mode 100644
index 000000000000..caf00518c1e0
--- /dev/null
+++ b/libexec/flua/bootstrap.h
@@ -0,0 +1,32 @@
+/*-
+ * Copyright (c) 2025 Kyle Evans <kevans@FreeBSD.org>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef FLUA_BOOTSTRAP_H
+#define	FLUA_BOOTSTRAP_H
+
+#ifdef BOOTSTRAPPING
+#include <sys/linker_set.h>
+
+#include <lauxlib.h>
+
+#define	FLUA_MODULE_SETNAME	flua_modules
+
+SET_DECLARE(FLUA_MODULE_SETNAME, const luaL_Reg);
+#define	FLUA_MODULE_DEF(ident, modname, openfn)			\
+	static const luaL_Reg ident = {	modname, openfn };	\
+	DATA_SET(FLUA_MODULE_SETNAME, ident)
+
+#define	FLUA_MODULE_NAMED(mod, name)	\
+	FLUA_MODULE_DEF(module_ ## mod, name, luaopen_ ## mod)
+#define	FLUA_MODULE(mod)		\
+	FLUA_MODULE_DEF(module_ ## mod, #mod, luaopen_ ## mod)
+#else	/* !BOOTSTRAPPING */
+#define	FLUA_MODULE_DEF(ident, modname, openfn)
+#define	FLUA_MODULE_NAMED(mod, name)
+#define	FLUA_MODULE(modname)
+#endif	/* BOOTSTRAPPING */
+
+#endif	/* FLUA_BOOTSTRAP_H */
diff --git a/libexec/flua/lfbsd/Makefile b/libexec/flua/lfbsd/Makefile
new file mode 100644
index 000000000000..e2a4aae14bcd
--- /dev/null
+++ b/libexec/flua/lfbsd/Makefile
@@ -0,0 +1,5 @@
+SHLIB_NAME=	fbsd.so
+WARNS?=	3
+
+.include "Makefile.inc"
+.include <bsd.lib.mk>
diff --git a/libexec/flua/lfbsd/Makefile.inc b/libexec/flua/lfbsd/Makefile.inc
new file mode 100644
index 000000000000..7a78ef82e0fc
--- /dev/null
+++ b/libexec/flua/lfbsd/Makefile.inc
@@ -0,0 +1,2 @@
+.PATH:	${.PARSEDIR}
+SRCS+=	lfbsd.c
diff --git a/libexec/flua/modules/lfbsd.c b/libexec/flua/lfbsd/lfbsd.c
index ef660ba9fd77..541b6c9611df 100644
--- a/libexec/flua/modules/lfbsd.c
+++ b/libexec/flua/lfbsd/lfbsd.c
@@ -40,6 +40,8 @@
 #include "lauxlib.h"
 #include "lfbsd.h"
 
+#include "bootstrap.h"
+
 #define	FBSD_PROCESSHANDLE	"fbsd_process_t*"
 
 struct fbsd_process {
@@ -283,3 +285,5 @@ luaopen_fbsd(lua_State *L)
 
 	return (1);
 }
+
+FLUA_MODULE(fbsd);
diff --git a/libexec/flua/modules/lfbsd.h b/libexec/flua/lfbsd/lfbsd.h
index 01034a3ad7cd..01034a3ad7cd 100644
--- a/libexec/flua/modules/lfbsd.h
+++ b/libexec/flua/lfbsd/lfbsd.h
diff --git a/libexec/flua/lfs/Makefile b/libexec/flua/lfs/Makefile
new file mode 100644
index 000000000000..3df83d6d2fc1
--- /dev/null
+++ b/libexec/flua/lfs/Makefile
@@ -0,0 +1,5 @@
+SHLIB_NAME=	lfs.so
+WARNS?=	3
+
+.include "Makefile.inc"
+.include <bsd.lib.mk>
diff --git a/libexec/flua/lfs/Makefile.inc b/libexec/flua/lfs/Makefile.inc
new file mode 100644
index 000000000000..9d40c42dc0e6
--- /dev/null
+++ b/libexec/flua/lfs/Makefile.inc
@@ -0,0 +1,2 @@
+.PATH:	${.PARSEDIR}
+SRCS+=	lfs.c
diff --git a/libexec/flua/modules/lfs.c b/libexec/flua/lfs/lfs.c
index 8cb8d6fc9fed..517e16ae65c8 100644
--- a/libexec/flua/modules/lfs.c
+++ b/libexec/flua/lfs/lfs.c
@@ -66,9 +66,10 @@
 #ifdef _STANDALONE
 #include "lstd.h"
 #include "lutils.h"
-#include "bootstrap.h"
 #endif
 
+#include "bootstrap.h"
+
 #ifndef nitems
 #define	nitems(x)	(sizeof((x)) / sizeof((x)[0]))
 #endif
@@ -446,3 +447,7 @@ luaopen_lfs(lua_State *L)
 #endif
 	return 1;
 }
+
+#ifndef _STANDALONE
+FLUA_MODULE(lfs);
+#endif
diff --git a/libexec/flua/modules/lfs.h b/libexec/flua/lfs/lfs.h
index a99e66d7f601..a99e66d7f601 100644
--- a/libexec/flua/modules/lfs.h
+++ b/libexec/flua/lfs/lfs.h
diff --git a/libexec/flua/libfreebsd/kenv/Makefile b/libexec/flua/libfreebsd/kenv/Makefile
index 1726c892c515..a1b388bb3612 100644
--- a/libexec/flua/libfreebsd/kenv/Makefile
+++ b/libexec/flua/libfreebsd/kenv/Makefile
@@ -1,5 +1,5 @@
 SHLIB_NAME=	kenv.so
-SRCS+=		kenv.c
 MAN=		freebsd.kenv.3lua
 
+.include "Makefile.inc"
 .include <bsd.lib.mk>
diff --git a/libexec/flua/libfreebsd/kenv/Makefile.inc b/libexec/flua/libfreebsd/kenv/Makefile.inc
new file mode 100644
index 000000000000..05819c5280d9
--- /dev/null
+++ b/libexec/flua/libfreebsd/kenv/Makefile.inc
@@ -0,0 +1,2 @@
+.PATH:		${.PARSEDIR}
+SRCS+=		kenv.c
diff --git a/libexec/flua/libfreebsd/kenv/kenv.c b/libexec/flua/libfreebsd/kenv/kenv.c
index 954baa00facb..56b24c72904a 100644
--- a/libexec/flua/libfreebsd/kenv/kenv.c
+++ b/libexec/flua/libfreebsd/kenv/kenv.c
@@ -14,6 +14,8 @@
 #include <lualib.h>
 #include <lauxlib.h>
 
+#include "bootstrap.h"
+
 int luaopen_freebsd_kenv(lua_State *L);
 
 static int
@@ -94,3 +96,5 @@ luaopen_freebsd_kenv(lua_State *L)
 
 	return (1);
 }
+
+FLUA_MODULE_NAMED(freebsd_kenv, "freebsd.kenv");
diff --git a/libexec/flua/libfreebsd/sys/linker/Makefile b/libexec/flua/libfreebsd/sys/linker/Makefile
index 1adf547b503c..f1f65ad5f6c1 100644
--- a/libexec/flua/libfreebsd/sys/linker/Makefile
+++ b/libexec/flua/libfreebsd/sys/linker/Makefile
@@ -1,7 +1,6 @@
 SHLIB_NAME=	linker.so
 
-SRCS+=		linker.c
-
 MAN=	freebsd.sys.linker.3lua
 
+.include "Makefile.inc"
 .include <bsd.lib.mk>
diff --git a/libexec/flua/libfreebsd/sys/linker/Makefile.inc b/libexec/flua/libfreebsd/sys/linker/Makefile.inc
new file mode 100644
index 000000000000..da65c0070170
--- /dev/null
+++ b/libexec/flua/libfreebsd/sys/linker/Makefile.inc
@@ -0,0 +1,2 @@
+.PATH:		${.PARSEDIR}
+SRCS+=		linker.c
diff --git a/libexec/flua/libfreebsd/sys/linker/linker.c b/libexec/flua/libfreebsd/sys/linker/linker.c
index 87eccfb651f0..c78fbb2b39d2 100644
--- a/libexec/flua/libfreebsd/sys/linker/linker.c
+++ b/libexec/flua/libfreebsd/sys/linker/linker.c
@@ -15,6 +15,8 @@
 #include <lualib.h>
 #include <lauxlib.h>
 
+#include "bootstrap.h"
+
 int luaopen_freebsd_sys_linker(lua_State *L);
 
 static int
@@ -80,3 +82,5 @@ luaopen_freebsd_sys_linker(lua_State *L)
 
 	return (1);
 }
+
+FLUA_MODULE_NAMED(freebsd_sys_linker, "freebsd.sys.linker");
diff --git a/libexec/flua/libhash/Makefile b/libexec/flua/libhash/Makefile
index b7c8d7ee9948..9cbd6f15acae 100644
--- a/libexec/flua/libhash/Makefile
+++ b/libexec/flua/libhash/Makefile
@@ -1,9 +1,6 @@
 SHLIB_NAME=	hash.so
 
-SRCS+=		lhash.c
-
-LIBADD+=	md
-
 MAN=	hash.3lua
 
+.include "Makefile.inc"
 .include <bsd.lib.mk>
diff --git a/libexec/flua/libhash/Makefile.inc b/libexec/flua/libhash/Makefile.inc
new file mode 100644
index 000000000000..d112dfe7df33
--- /dev/null
+++ b/libexec/flua/libhash/Makefile.inc
@@ -0,0 +1,3 @@
+.PATH:		${.PARSEDIR}
+SRCS+=		lhash.c
+LIBADD+=	md
diff --git a/libexec/flua/libhash/lhash.c b/libexec/flua/libhash/lhash.c
index 4587961fe8a0..f455f006bf27 100644
--- a/libexec/flua/libhash/lhash.c
+++ b/libexec/flua/libhash/lhash.c
@@ -11,6 +11,8 @@
 #include <sha256.h>
 #include <string.h>
 
+#include "bootstrap.h"
+
 #define SHA256_META "SHA256 meta table"
 #define SHA256_DIGEST_LEN 32
 
@@ -175,3 +177,7 @@ luaopen_hash(lua_State *L)
 
 	return 1;
 }
+
+#ifndef _STANDALONE
+FLUA_MODULE(hash);
+#endif
diff --git a/libexec/flua/libjail/Makefile b/libexec/flua/libjail/Makefile
index 20cd9f5f1429..b9c8bdc39095 100644
--- a/libexec/flua/libjail/Makefile
+++ b/libexec/flua/libjail/Makefile
@@ -1,9 +1,6 @@
 SHLIB_NAME=	jail.so
 
-SRCS+=		lua_jail.c
-
-LIBADD+=	jail
-
 MAN=	jail.3lua
 
+.include "Makefile.inc"
 .include <bsd.lib.mk>
diff --git a/libexec/flua/libjail/Makefile.inc b/libexec/flua/libjail/Makefile.inc
new file mode 100644
index 000000000000..a896bf38c65b
--- /dev/null
+++ b/libexec/flua/libjail/Makefile.inc
@@ -0,0 +1,3 @@
+.PATH:		${.PARSEDIR}
+SRCS+=		lua_jail.c
+LIBADD+=	jail
diff --git a/libexec/flua/libjail/lua_jail.c b/libexec/flua/libjail/lua_jail.c
index 9632db795775..8c3ec6c1d500 100644
--- a/libexec/flua/libjail/lua_jail.c
+++ b/libexec/flua/libjail/lua_jail.c
@@ -38,6 +38,8 @@
 #include <lauxlib.h>
 #include <lualib.h>
 
+#include "bootstrap.h"
+
 #define	JAIL_METATABLE "jail iterator metatable"
 
 /*
@@ -716,3 +718,5 @@ luaopen_jail(lua_State *L)
 
 	return (1);
 }
+
+FLUA_MODULE(jail);
diff --git a/libexec/flua/liblyaml/Makefile b/libexec/flua/liblyaml/Makefile
index e7a89d09bb9e..8d1432acd325 100644
--- a/libexec/flua/liblyaml/Makefile
+++ b/libexec/flua/liblyaml/Makefile
@@ -1,22 +1,4 @@
 SHLIB_NAME=	yaml.so
 
-WARNS=	1
-LYAMLSRC?=	${SRCTOP}/contrib/lyaml
-.PATH:		${LYAMLSRC}/ext/yaml ${LYAMLSRC}/lib/lyaml
-SRCS=		emitter.c \
-		parser.c \
-		scanner.c \
-		yaml.c
-CFLAGS+=	\
-		-I${LYAMLSRC}/ext/yaml \
-		-I${SRCTOP}/contrib/libyaml/include \
-		-DVERSION=\"6.2.8\"
-LIBADD+=	yaml
-
-FILES=		explicit.lua \
-		functional.lua \
-		implicit.lua \
-		init.lua
-FILESDIR=	${SHAREDIR}/flua/lyaml
-
+.include "Makefile.inc"
 .include <bsd.lib.mk>
diff --git a/libexec/flua/liblyaml/Makefile.inc b/libexec/flua/liblyaml/Makefile.inc
new file mode 100644
index 000000000000..caa1f37b57eb
--- /dev/null
+++ b/libexec/flua/liblyaml/Makefile.inc
@@ -0,0 +1,20 @@
+WARNS=	1
+
+LYAMLSRC?=	${SRCTOP}/contrib/lyaml
+.PATH:		${LYAMLSRC}/ext/yaml ${LYAMLSRC}/lib/lyaml
+SRCS+=		emitter.c \
+		parser.c \
+		scanner.c \
+		yaml.c
+CFLAGS+=	\
+		-I${LYAMLSRC}/ext/yaml \
+		-I${SRCTOP}/contrib/libyaml/include \
+		-DVERSION=\"6.2.8\"
+LIBADD+=	yaml
+
+FILESGROUPS+=	YAML
+YAML=		explicit.lua \
+		functional.lua \
+		implicit.lua \
+		init.lua
+YAMLDIR=	${SHAREDIR}/flua/lyaml
diff --git a/libexec/flua/libucl/Makefile b/libexec/flua/libucl/Makefile
index a88c8bda6bfc..32d76d1ea1ad 100644
--- a/libexec/flua/libucl/Makefile
+++ b/libexec/flua/libucl/Makefile
@@ -1,14 +1,4 @@
 SHLIB_NAME=	ucl.so
 
-WARNS=		2
-
-UCLSRC?= 	${SRCTOP}/contrib/libucl
-.PATH: ${UCLSRC}/lua
-SRCS+=		lua_ucl.c
-CFLAGS+=	\
-		-I${UCLSRC}/include \
-		-I${UCLSRC}/src \
-		-I${UCLSRC}/uthash
-LIBADD+=	ucl
-
+.include "Makefile.inc"
 .include <bsd.lib.mk>
diff --git a/libexec/flua/libucl/Makefile.inc b/libexec/flua/libucl/Makefile.inc
new file mode 100644
index 000000000000..70fb0f265635
--- /dev/null
+++ b/libexec/flua/libucl/Makefile.inc
@@ -0,0 +1,12 @@
+.if ${WARNS:U6} > 2
+WARNS=		2
+.endif
+
+UCLSRC?=	${SRCTOP}/contrib/libucl
+.PATH: ${UCLSRC}/lua
+SRCS+=		lua_ucl.c
+CFLAGS+=	\
+		-I${UCLSRC}/include \
+		-I${UCLSRC}/src \
+		-I${UCLSRC}/uthash
+LIBADD+=	ucl
diff --git a/libexec/flua/linit_flua.c b/libexec/flua/linit_flua.c
index b466b7872158..65356c938671 100644
--- a/libexec/flua/linit_flua.c
+++ b/libexec/flua/linit_flua.c
@@ -26,16 +26,16 @@
 
 #include "lprefix.h"
 
-
 #include <stddef.h>
+#include <stdlib.h>
 
 #include "lua.h"
 
 #include "lualib.h"
 #include "lauxlib.h"
-#include "lfs.h"
 #include "lposix.h"
-#include "lfbsd.h"
+
+#include "bootstrap.h"
 
 /*
 ** these libs are loaded by lua.c and are readily available to any Lua
@@ -56,12 +56,32 @@ static const luaL_Reg loadedlibs[] = {
   {LUA_BITLIBNAME, luaopen_bit32},
 #endif
   /* FreeBSD Extensions */
-  {"lfs", luaopen_lfs},
   {"posix", luaopen_posix},
-  {"fbsd", luaopen_fbsd},
   {NULL, NULL}
 };
 
+#ifdef BOOTSTRAPPING
+static void __attribute__((constructor)) flua_init_env(void) {
+  /*
+   * This happens in the middle of luaopen_package().  We could move it into
+   * flua_setup_mods(), but it seems better to avoid its timing being so
+   * important that it would break some of our bootstrap modules if someone
+   * were to reorder things.
+   */
+  if (getenv("LUA_PATH") == NULL)
+    setenv("LUA_PATH", BOOTSTRAP_FLUA_PATH, 1);
+}
+
+static void flua_setup_mods (lua_State *L) {
+  const luaL_Reg **flib;
+
+  SET_FOREACH(flib, FLUA_MODULE_SETNAME) {
+    luaL_requiref(L, (*flib)->name, (*flib)->func, 1);
+    lua_pop(L, 1);  /* remove lib */
+  }
+};
+#endif
+
 LUALIB_API void luaL_openlibs (lua_State *L) {
   const luaL_Reg *lib;
   /* "require" functions from 'loadedlibs' and set results to global table */
@@ -69,4 +89,7 @@ LUALIB_API void luaL_openlibs (lua_State *L) {
     luaL_requiref(L, lib->name, lib->func, 1);
     lua_pop(L, 1);  /* remove lib */
   }
+#ifdef BOOTSTRAPPING
+  flua_setup_mods(L);
+#endif
 }
diff --git a/libexec/ftpd/Makefile b/libexec/ftpd/Makefile
deleted file mode 100644
index a040fa57f7d7..000000000000
--- a/libexec/ftpd/Makefile
+++ /dev/null
@@ -1,39 +0,0 @@
-.include <src.opts.mk>
-
-PACKAGE=	ftpd
-
-CONFS=	ftpusers
-PROG=	ftpd
-MAN=	ftpd.8 ftpchroot.5
-SRCS=	ftpd.c ftpcmd.y logwtmp.c popen.c
-
-CFLAGS+=-DSETPROCTITLE -DLOGIN_CAP -DVIRTUAL_HOSTING
-CFLAGS+=-I${.CURDIR}
-YFLAGS=
-WARNS?=	2
-WFORMAT=0
-
-LIBADD=	crypt md util
-
-.PATH:	${SRCTOP}/bin/ls
-SRCS+=	ls.c cmp.c print.c util.c
-CFLAGS+=-Dmain=ls_main -I${SRCTOP}/bin/ls
-LIBADD+=	m
-
-.if ${MK_BLACKLIST_SUPPORT} != "no"
-CFLAGS+= -DUSE_BLACKLIST -I${SRCTOP}/contrib/blocklist/include
-SRCS+= blacklist.c
-LIBADD+= blacklist
-LDFLAGS+=-L${LIBBLACKLISTDIR}
-.endif
-
-.if ${MK_INET6_SUPPORT} != "no"
-CFLAGS+=-DINET6
-.endif
-
-.if ${MK_PAM_SUPPORT} != "no"
-CFLAGS+=-DUSE_PAM
-LIBADD+=	pam
-.endif
-
-.include <bsd.prog.mk>
diff --git a/libexec/ftpd/Makefile.depend b/libexec/ftpd/Makefile.depend
deleted file mode 100644
index b6e94a3cf93c..000000000000
--- a/libexec/ftpd/Makefile.depend
+++ /dev/null
@@ -1,21 +0,0 @@
-# Autogenerated - do NOT edit!
-
-DIRDEPS = \
-	include \
-	include/arpa \
-	include/xlocale \
-	lib/${CSU_DIR} \
-	lib/libc \
-	lib/libcompiler_rt \
-	lib/libcrypt \
-	lib/libmd \
-	lib/libutil \
-	lib/msun \
-	usr.bin/yacc.host \
-
-
-.include <dirdeps.mk>
-
-.if ${DEP_RELDIR} == ${_DEP_RELDIR}
-# local dependencies - needed for -jN in clean tree
-.endif
diff --git a/libexec/ftpd/Makefile.depend.options b/libexec/ftpd/Makefile.depend.options
deleted file mode 100644
index 5f186bb031f2..000000000000
--- a/libexec/ftpd/Makefile.depend.options
+++ /dev/null
@@ -1,5 +0,0 @@
-# This file is not autogenerated - take care!
-
-DIRDEPS_OPTIONS= BLACKLIST_SUPPORT PAM_SUPPORT
-
-.include <dirdeps-options.mk>
diff --git a/libexec/ftpd/blacklist.c b/libexec/ftpd/blacklist.c
deleted file mode 100644
index 0a45f9369074..000000000000
--- a/libexec/ftpd/blacklist.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*-
- * Copyright (c) 2016 The FreeBSD Foundation
- *
- * This software was developed by Kurt Lidl under sponsorship from the
- * FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE. */
-
-
-#include <ctype.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <unistd.h>
-
-#include <blacklist.h>
-#include "blacklist_client.h"
-
-static struct blacklist *blstate;
-extern int use_blacklist;
-
-void
-blacklist_init(void)
-{
-
-	if (use_blacklist)
-		blstate = blacklist_open();
-}
-
-void
-blacklist_notify(int action, int fd, const char *msg)
-{
-
-	if (blstate == NULL)
-		return;
-	(void)blacklist_r(blstate, action, fd, msg);
-}
diff --git a/libexec/ftpd/blacklist_client.h b/libexec/ftpd/blacklist_client.h
deleted file mode 100644
index 0b6805dc218e..000000000000
--- a/libexec/ftpd/blacklist_client.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*-
- * Copyright (c) 2016 The FreeBSD Foundation
- *
- * This software was developed by Kurt Lidl under sponsorship from the
- * FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE. */
-
-
-#ifndef BLACKLIST_CLIENT_H
-#define BLACKLIST_CLIENT_H
-
-#ifndef BLACKLIST_API_ENUM
-enum {
-	BLACKLIST_AUTH_OK = 0,
-	BLACKLIST_AUTH_FAIL
-};
-#endif
-
-#ifdef USE_BLACKLIST
-void blacklist_init(void);
-void blacklist_notify(int, int, const char *);
-
-#define BLACKLIST_INIT() blacklist_init()
-#define BLACKLIST_NOTIFY(x, y, z) blacklist_notify(x, y, z)
-
-#else
-
-#define BLACKLIST_INIT()
-#define BLACKLIST_NOTIFY(x, y, z)
-
-#endif
-
-#endif /* BLACKLIST_CLIENT_H */
diff --git a/libexec/ftpd/config.h b/libexec/ftpd/config.h
deleted file mode 100644
index c5ca1f01e10e..000000000000
--- a/libexec/ftpd/config.h
+++ /dev/null
@@ -1,280 +0,0 @@
-
-
-/* config.h.  Generated automatically by configure.  */
-/* config.h.in.  Generated automatically from configure.in by autoheader.  */
-/* $Id: config.h.in,v 1.15 2001/04/28 07:11:46 lukem Exp $ */
-
-
-/* Define if the closedir function returns void instead of int.  */
-/* #undef CLOSEDIR_VOID */
-
-/* Define to empty if the keyword does not work.  */
-/* #undef const */
-
-/* Define if your C compiler doesn't accept -c and -o together.  */
-/* #undef NO_MINUS_C_MINUS_O */
-
-/* Define if your Fortran 77 compiler doesn't accept -c and -o together. */
-/* #undef F77_NO_MINUS_C_MINUS_O */
-
-/* Define to `long' if <sys/types.h> doesn't define.  */
-/* #undef off_t */
-
-/* Define to the type of arg1 for select(). */
-/* #undef SELECT_TYPE_ARG1 */
-
-/* Define to the type of args 2, 3 and 4 for select(). */
-/* #undef SELECT_TYPE_ARG234 */
-
-/* Define to the type of arg5 for select(). */
-/* #undef SELECT_TYPE_ARG5 */
-
-/* Define if you have the ANSI C header files.  */
-#define STDC_HEADERS 1
-
-/* Define if you can safely include both <sys/time.h> and <time.h>.  */
-#define TIME_WITH_SYS_TIME 1
-
-/* Define if the closedir function returns void instead of int.  */
-/* #undef VOID_CLOSEDIR */
-
-/* The number of bytes in a off_t.  */
-#define SIZEOF_OFF_T 0
-
-/* Define if you have the err function.  */
-#define HAVE_ERR 1
-
-/* Define if you have the fgetln function.  */
-#define HAVE_FGETLN 1
-
-/* Define if you have the flock function.  */
-#define HAVE_FLOCK 1
-
-/* Define if you have the fparseln function.  */
-#define HAVE_FPARSELN 1
-
-/* Define if you have the fts_open function.  */
-#define HAVE_FTS_OPEN 1
-
-/* Define if you have the getaddrinfo function.  */
-#define HAVE_GETADDRINFO 1
-
-/* Define if you have the getgrouplist function.  */
-#define HAVE_GETGROUPLIST 1
-
-/* Define if you have the getnameinfo function.  */
-#define HAVE_GETNAMEINFO 1
-
-/* Define if you have the getspnam function.  */
-/* #undef HAVE_GETSPNAM */
-
-/* Define if you have the getusershell function.  */
-#define HAVE_GETUSERSHELL 1
-
-/* Define if you have the inet_net_pton function.  */
-#define HAVE_INET_NET_PTON 1
-
-/* Define if you have the inet_ntop function.  */
-#define HAVE_INET_NTOP 1
-
-/* Define if you have the inet_pton function.  */
-#define HAVE_INET_PTON 1
-
-/* Define if you have the lockf function.  */
-#define HAVE_LOCKF 1
-
-/* Define if you have the mkstemp function.  */
-#define HAVE_MKSTEMP 1
-
-/* Define if you have the setlogin function.  */
-#define HAVE_SETLOGIN 1
-
-/* Define if you have the setproctitle function.  */
-#define HAVE_SETPROCTITLE 1
-
-/* Define if you have the sl_init function.  */
-#define HAVE_SL_INIT 1
-
-/* Define if you have the snprintf function.  */
-#define HAVE_SNPRINTF 1
-
-/* Define if you have the strdup function.  */
-#define HAVE_STRDUP 1
-
-/* Define if you have the strerror function.  */
-#define HAVE_STRERROR 1
-
-/* Define if you have the strlcat function.  */
-#define HAVE_STRLCAT 1
-
-/* Define if you have the strlcpy function.  */
-#define HAVE_STRLCPY 1
-
-/* Define if you have the strmode function.  */
-#define HAVE_STRMODE 1
-
-/* Define if you have the strsep function.  */
-#define HAVE_STRSEP 1
-
-/* Define if you have the strtoll function.  */
-#define HAVE_STRTOLL 1
-
-/* Define if you have the user_from_uid function.  */
-#define HAVE_USER_FROM_UID 1
-
-/* Define if you have the usleep function.  */
-#define HAVE_USLEEP 1
-
-/* Define if you have the vfork function.  */
-#define HAVE_VFORK 1
-
-/* Define if you have the vsyslog function.  */
-#define HAVE_VSYSLOG 1
-
-/* Define if you have the <arpa/nameser.h> header file.  */
-#define HAVE_ARPA_NAMESER_H 1
-
-/* Define if you have the <dirent.h> header file.  */
-#define HAVE_DIRENT_H 1
-
-/* Define if you have the <err.h> header file.  */
-#define HAVE_ERR_H 1
-
-/* Define if you have the <fts.h> header file.  */
-#define HAVE_FTS_H 1
-
-/* Define if you have the <libutil.h> header file.  */
-#define HAVE_LIBUTIL_H 1
-
-/* Define if you have the <ndir.h> header file.  */
-/* #undef HAVE_NDIR_H */
-
-/* Define if you have the <paths.h> header file.  */
-#define HAVE_PATHS_H 1
-
-/* Define if you have the <sys/dir.h> header file.  */
-#define HAVE_SYS_DIR_H 1
-
-/* Define if you have the <sys/ndir.h> header file.  */
-/* #undef HAVE_SYS_NDIR_H */
-
-/* Define if you have the <sys/sysmacros.h> header file.  */
-/* #undef HAVE_SYS_SYSMACROS_H */
-
-/* Define if you have the <util.h> header file.  */
-/* #undef HAVE_UTIL_H */
-
-/* Define if you have the crypt library (-lcrypt).  */
-#define HAVE_LIBCRYPT 1
-
-/* Define if you have the nsl library (-lnsl).  */
-/* #undef HAVE_LIBNSL */
-
-/* Define if you have the skey library (-lskey).  */
-/* #undef HAVE_LIBSKEY */
-
-/* Define if you have the socket library (-lsocket).  */
-/* #undef HAVE_LIBSOCKET */
-
-/* Define if you have the util library (-lutil).  */
-#define HAVE_LIBUTIL 1
-
-/* Define if your compiler supports `long long' */
-#define HAVE_LONG_LONG 1
-
-/* Define if *printf() uses %qd to print `long long' (otherwise uses %lld) */
-#define HAVE_PRINTF_QD 1
-
-/* Define if in_port_t exists */
-#define HAVE_IN_PORT_T 1
-
-/* Define if struct sockaddr.sa_len exists (implies sockaddr_in.sin_len, etc) */
-#define HAVE_SOCKADDR_SA_LEN 1
-
-/* Define if socklen_t exists */
-#define HAVE_SOCKLEN_T 1
-
-/* Define if AF_INET6 exists in <sys/socket.h> */
-#define HAVE_AF_INET6 1
-
-/* Define if `struct sockaddr_in6' exists in <netinet/in.h> */
-#define HAVE_SOCKADDR_IN6 1
-
-/* Define if `struct addrinfo' exists in <netdb.h> */
-#define HAVE_ADDRINFO 1
-
-/*
- * Define if <netdb.h> contains AI_NUMERICHOST et al.
- * Systems which only implement RFC2133 will need this.
- */
-#define HAVE_RFC2553_NETDB 1
-
-/* Define if `struct direct' has a d_namlen element */
-#define HAVE_D_NAMLEN 1
-
-/* Define if struct passwd.pw_expire exists. */
-#define HAVE_PW_EXPIRE 1
-
-/* Define if GLOB_BRACE, gl_path and gl_match exist in <glob.h> */
-#define HAVE_WORKING_GLOB 1
-
-/* Define if crypt() is declared in <unistd.h> */
-#define HAVE_CRYPT_D 1
-
-/* Define if fclose() is declared in <stdio.h> */
-#define HAVE_FCLOSE_D 1
-
-/* Define if optarg is declared in <stdlib.h> or <unistd.h> */
-#define HAVE_OPTARG_D 1
-
-/* Define if optind is declared in <stdlib.h> or <unistd.h> */
-#define HAVE_OPTIND_D 1
-
-/* Define if optreset exists */
-#define HAVE_OPTRESET 1
-
-/* Define if pclose() is declared in <stdio.h> */
-#define HAVE_PCLOSE_D 1
-
-/* Define if getusershell() is declared in <unistd.h> */
-#define HAVE_GETUSERSHELL_D 1
-
-/* Define if `long long' is supported and sizeof(off_t) >= 8 */
-#define HAVE_QUAD_SUPPORT 1
-
-/* Define if not using in-built /bin/ls code */
-/* #undef NO_INTERNAL_LS */
-
-/* Define if using S/Key */
-/* #undef SKEY */
-
-/*
- * Define this if compiling with SOCKS (the firewall traversal library).
- * Also, you must define connect, getsockname, bind, accept, listen, and
- * select to their R-versions.
- */
-/* #undef	SOCKS */
-/* #undef	SOCKS4 */
-/* #undef	SOCKS5 */
-/* #undef	connect */
-/* #undef	getsockname */
-/* #undef	bind */
-/* #undef	accept */
-/* #undef	listen */
-/* #undef	select */
-/* #undef	dup */
-/* #undef	dup2 */
-/* #undef	fclose */
-/* #undef	gethostbyname */
-/* #undef	getpeername */
-/* #undef	read */
-/* #undef	recv */
-/* #undef	recvfrom */
-/* #undef	rresvport */
-/* #undef	send */
-/* #undef	sendto */
-/* #undef	shutdown */
-/* #undef	write */
-
-/* Define if you have the <arpa/ftp.h> header file.  */
-#define HAVE_FTP_NAMES 1
diff --git a/libexec/ftpd/extern.h b/libexec/ftpd/extern.h
deleted file mode 100644
index 047e8573dd09..000000000000
--- a/libexec/ftpd/extern.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/types.h>
-#include <sys/socket.h>
-
-void	blkfree(char **);
-char  **copyblk(char **);
-void	cwd(char *);
-void	delete(char *);
-void	dologout(int);
-void	fatalerror(char *);
-void    ftpd_logwtmp(char *, char *, struct sockaddr *addr);
-int	ftpd_pclose(FILE *);
-FILE   *ftpd_popen(char *, char *);
-int	get_line(char *, int, FILE *);
-void	lreply(int, const char *, ...) __printflike(2, 3);
-void	makedir(char *);
-void	nack(char *);
-void	pass(char *);
-void	passive(void);
-void	long_passive(char *, int);
-void	perror_reply(int, char *);
-void	pwd(void);
-void	removedir(char *);
-void	renamecmd(char *, char *);
-char   *renamefrom(char *);
-void	reply(int, const char *, ...) __printflike(2, 3);
-void	retrieve(char *, char *);
-void	send_file_list(char *);
-void	statcmd(void);
-void	statfilecmd(char *);
-void	store(char *, char *, int);
-void	upper(char *);
-void	user(char *);
-void	yyerror(char *);
-int	yyparse(void);
-int	ls_main(int, char **);
-
-extern	int assumeutf8;
-extern	char cbuf[];
-extern	union sockunion data_dest;
-extern	int epsvall;
-extern	int form;
-extern	int ftpdebug;
-extern	int guest;
-extern	union sockunion his_addr;
-extern	char *homedir;
-extern	int hostinfo;
-extern	char *hostname;
-extern	int maxtimeout;
-extern	int logged_in;
-extern	int logging;
-extern	int noepsv;
-extern	int noguestretr;
-extern	int noretr;
-extern	int paranoid;
-extern	struct passwd *pw;
-extern	int pdata;
-extern	char proctitle[];
-extern	int readonly;
-extern	off_t restart_point;
-extern	int timeout;
-extern  char tmpline[];
-extern	int type;
-extern	char *typenames[]; /* defined in <arpa/ftp.h> included from ftpd.c */
-extern	int usedefault;
-
-struct sockaddr_in;
-struct sockaddr_in6;
-union sockunion {
-	struct sockinet {
-		u_char	si_len;
-		u_char	si_family;
-		u_short	si_port;
-	} su_si;
-	struct	sockaddr_in  su_sin;
-	struct	sockaddr_in6 su_sin6;
-};
-#define	su_len		su_si.si_len
-#define	su_family	su_si.si_family
-#define	su_port		su_si.si_port
diff --git a/libexec/ftpd/ftpchroot.5 b/libexec/ftpd/ftpchroot.5
deleted file mode 100644
index cb2f15f719ad..000000000000
--- a/libexec/ftpd/ftpchroot.5
+++ /dev/null
@@ -1,118 +0,0 @@
-.\" Copyright (c) 2003 FreeBSD Project
-.\" All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.Dd January 26, 2003
-.Dt FTPCHROOT 5
-.Os
-.Sh NAME
-.Nm ftpchroot
-.Nd "list users and groups subject to FTP access restrictions"
-.Sh DESCRIPTION
-The file
-.Nm
-is read by
-.Xr ftpd 8
-at the beginning of an FTP session, after having authenticated the user.
-Each line in
-.Nm
-corresponds to a user or group.
-If a line in
-.Nm
-matches the current user or a group he is a member of,
-access restrictions will be applied to this
-session by changing its root directory with
-.Xr chroot 2
-to that specified on the line or to the user's login directory.
-.Pp
-The order of records in
-.Nm
-is important because the first match will be used.
-Fields on each line are separated by tabs or spaces.
-.Pp
-The first field specifies a user or group name.
-If it is prefixed by an
-.Dq at
-sign,
-.Ql @ ,
-it specifies a group name;
-the line will match each user who is a member of this group.
-As a special case, a single
-.Ql @
-in this field will match any user.
-A username is specified otherwise.
-.Pp
-The optional second field describes the directory for the user
-or each member of the group to be locked up in using
-.Xr chroot 2 .
-Be it omitted, the user's login directory will be used.
-If it is not an absolute pathname, then it will be relative
-to the user's login directory.
-If it contains the
-.Pa /./
-separator,
-.Xr ftpd 8
-will treat its left-hand side as the name of the directory to do
-.Xr chroot 2
-to, and its right-hand side to change the current directory to afterwards.
-.Sh FILES
-.Bl -tag -width ".Pa /etc/ftpchroot" -compact
-.It Pa /etc/ftpchroot
-.El
-.Sh EXAMPLES
-These lines in
-.Nm
-will lock up the user
-.Dq Li webuser
-and each member of the group
-.Dq Li hostee
-in their respective login directories:
-.Bd -literal -offset indent
-webuser
-@hostee
-.Ed
-.Pp
-And this line will tell
-.Xr ftpd 8
-to lock up the user
-.Dq Li joe
-in
-.Pa /var/spool/ftp
-and then to change the current directory to
-.Pa /joe ,
-which is relative to the session's new root:
-.Pp
-.Dl "joe	/var/spool/ftp/./joe"
-.Pp
-And finally the following line will lock up every user connecting
-through FTP in his respective
-.Pa ~/public_html ,
-thus lowering possible impact on the system
-from intrinsic insecurity of FTP:
-.Pp
-.Dl "@	public_html"
-.Sh SEE ALSO
-.Xr chroot 2 ,
-.Xr group 5 ,
-.Xr passwd 5 ,
-.Xr ftpd 8
diff --git a/libexec/ftpd/ftpcmd.y b/libexec/ftpd/ftpcmd.y
deleted file mode 100644
index c090130d8137..000000000000
--- a/libexec/ftpd/ftpcmd.y
+++ /dev/null
@@ -1,1806 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1985, 1988, 1993, 1994
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Grammar for FTP commands.
- * See RFC 959.
- */
-
-%{
-
-#include <sys/param.h>
-#include <sys/socket.h>
-#include <sys/stat.h>
-
-#include <netinet/in.h>
-#include <arpa/ftp.h>
-
-#include <ctype.h>
-#include <errno.h>
-#include <glob.h>
-#include <libutil.h>
-#include <limits.h>
-#include <md5.h>
-#include <netdb.h>
-#include <pwd.h>
-#include <signal.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <syslog.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "extern.h"
-#include "pathnames.h"
-
-#define	yylex	ftpcmd_yylex
-
-off_t	restart_point;
-
-static	int cmd_type;
-static	int cmd_form;
-static	int cmd_bytesz;
-static	int state;
-char	cbuf[512];
-char	*fromname = NULL;
-
-%}
-
-%union {
-	struct {
-		off_t	o;
-		int	i;
-	} u;
-	char   *s;
-}
-
-%token
-	A	B	C	E	F	I
-	L	N	P	R	S	T
-	ALL
-
-	SP	CRLF	COMMA
-
-	USER	PASS	ACCT	REIN	QUIT	PORT
-	PASV	TYPE	STRU	MODE	RETR	STOR
-	APPE	MLFL	MAIL	MSND	MSOM	MSAM
-	MRSQ	MRCP	ALLO	REST	RNFR	RNTO
-	ABOR	DELE	CWD	LIST	NLST	SITE
-	STAT	HELP	NOOP	MKD	RMD	PWD
-	CDUP	STOU	SMNT	SYST	SIZE	MDTM
-	LPRT	LPSV	EPRT	EPSV	FEAT
-
-	UMASK	IDLE	CHMOD	MDFIVE
-
-	LEXERR	NOTIMPL
-
-%token	<s> STRING
-%token	<u> NUMBER
-
-%type	<u.i> check_login octal_number byte_size
-%type	<u.i> check_login_ro check_login_epsv
-%type	<u.i> struct_code mode_code type_code form_code
-%type	<s> pathstring pathname password username
-%type	<s> ALL NOTIMPL
-
-%start	cmd_list
-
-%%
-
-cmd_list
-	: /* empty */
-	| cmd_list cmd
-		{
-			if (fromname)
-				free(fromname);
-			fromname = NULL;
-			restart_point = 0;
-		}
-	| cmd_list rcmd
-	;
-
-cmd
-	: USER SP username CRLF
-		{
-			user($3);
-			free($3);
-		}
-	| PASS SP password CRLF
-		{
-			pass($3);
-			free($3);
-		}
-	| PASS CRLF
-		{
-			pass("");
-		}
-	| PORT check_login SP host_port CRLF
-		{
-			if (epsvall) {
-				reply(501, "No PORT allowed after EPSV ALL.");
-				goto port_done;
-			}
-			if (!$2)
-				goto port_done;
-			if (port_check("PORT") == 1)
-				goto port_done;
-#ifdef INET6
-			if ((his_addr.su_family != AF_INET6 ||
-			     !IN6_IS_ADDR_V4MAPPED(&his_addr.su_sin6.sin6_addr))) {
-				/* shoud never happen */
-				usedefault = 1;
-				reply(500, "Invalid address rejected.");
-				goto port_done;
-			}
-			port_check_v6("pcmd");
-#endif
-		port_done:
-			;
-		}
-	| LPRT check_login SP host_long_port CRLF
-		{
-			if (epsvall) {
-				reply(501, "No LPRT allowed after EPSV ALL.");
-				goto lprt_done;
-			}
-			if (!$2)
-				goto lprt_done;
-			if (port_check("LPRT") == 1)
-				goto lprt_done;
-#ifdef INET6
-			if (his_addr.su_family != AF_INET6) {
-				usedefault = 1;
-				reply(500, "Invalid address rejected.");
-				goto lprt_done;
-			}
-			if (port_check_v6("LPRT") == 1)
-				goto lprt_done;
-#endif
-		lprt_done:
-			;
-		}
-	| EPRT check_login SP STRING CRLF
-		{
-			char delim;
-			char *tmp = NULL;
-			char *p, *q;
-			char *result[3];
-			struct addrinfo hints;
-			struct addrinfo *res;
-			int i;
-
-			if (epsvall) {
-				reply(501, "No EPRT allowed after EPSV ALL.");
-				goto eprt_done;
-			}
-			if (!$2)
-				goto eprt_done;
-
-			memset(&data_dest, 0, sizeof(data_dest));
-			tmp = strdup($4);
-			if (ftpdebug)
-				syslog(LOG_DEBUG, "%s", tmp);
-			if (!tmp) {
-				fatalerror("not enough core");
-				/*NOTREACHED*/
-			}
-			p = tmp;
-			delim = p[0];
-			p++;
-			memset(result, 0, sizeof(result));
-			for (i = 0; i < 3; i++) {
-				q = strchr(p, delim);
-				if (!q || *q != delim) {
-		parsefail:
-					reply(500,
-						"Invalid argument, rejected.");
-					if (tmp)
-						free(tmp);
-					usedefault = 1;
-					goto eprt_done;
-				}
-				*q++ = '\0';
-				result[i] = p;
-				if (ftpdebug)
-					syslog(LOG_DEBUG, "%d: %s", i, p);
-				p = q;
-			}
-
-			/* some more sanity check */
-			p = result[0];
-			while (*p) {
-				if (!isdigit(*p))
-					goto parsefail;
-				p++;
-			}
-			p = result[2];
-			while (*p) {
-				if (!isdigit(*p))
-					goto parsefail;
-				p++;
-			}
-
-			/* grab address */
-			memset(&hints, 0, sizeof(hints));
-			if (atoi(result[0]) == 1)
-				hints.ai_family = PF_INET;
-#ifdef INET6
-			else if (atoi(result[0]) == 2)
-				hints.ai_family = PF_INET6;
-#endif
-			else
-				hints.ai_family = PF_UNSPEC;	/*XXX*/
-			hints.ai_socktype = SOCK_STREAM;
-			i = getaddrinfo(result[1], result[2], &hints, &res);
-			if (i)
-				goto parsefail;
-			memcpy(&data_dest, res->ai_addr, res->ai_addrlen);
-#ifdef INET6
-			if (his_addr.su_family == AF_INET6
-			    && data_dest.su_family == AF_INET6) {
-				/* XXX more sanity checks! */
-				data_dest.su_sin6.sin6_scope_id =
-					his_addr.su_sin6.sin6_scope_id;
-			}
-#endif
-			free(tmp);
-			tmp = NULL;
-
-			if (port_check("EPRT") == 1)
-				goto eprt_done;
-#ifdef INET6
-			if (his_addr.su_family != AF_INET6) {
-				usedefault = 1;
-				reply(500, "Invalid address rejected.");
-				goto eprt_done;
-			}
-			if (port_check_v6("EPRT") == 1)
-				goto eprt_done;
-#endif
-		eprt_done:
-			free($4);
-		}
-	| PASV check_login CRLF
-		{
-			if (epsvall)
-				reply(501, "No PASV allowed after EPSV ALL.");
-			else if ($2)
-				passive();
-		}
-	| LPSV check_login CRLF
-		{
-			if (epsvall)
-				reply(501, "No LPSV allowed after EPSV ALL.");
-			else if ($2)
-				long_passive("LPSV", PF_UNSPEC);
-		}
-	| EPSV check_login_epsv SP NUMBER CRLF
-		{
-			if ($2) {
-				int pf;
-				switch ($4.i) {
-				case 1:
-					pf = PF_INET;
-					break;
-#ifdef INET6
-				case 2:
-					pf = PF_INET6;
-					break;
-#endif
-				default:
-					pf = -1;	/*junk value*/
-					break;
-				}
-				long_passive("EPSV", pf);
-			}
-		}
-	| EPSV check_login_epsv SP ALL CRLF
-		{
-			if ($2) {
-				reply(200, "EPSV ALL command successful.");
-				epsvall++;
-			}
-		}
-	| EPSV check_login_epsv CRLF
-		{
-			if ($2)
-				long_passive("EPSV", PF_UNSPEC);
-		}
-	| TYPE check_login SP type_code CRLF
-		{
-			if ($2) {
-				switch (cmd_type) {
-
-				case TYPE_A:
-					if (cmd_form == FORM_N) {
-						reply(200, "Type set to A.");
-						type = cmd_type;
-						form = cmd_form;
-					} else
-						reply(504, "Form must be N.");
-					break;
-
-				case TYPE_E:
-					reply(504, "Type E not implemented.");
-					break;
-
-				case TYPE_I:
-					reply(200, "Type set to I.");
-					type = cmd_type;
-					break;
-
-				case TYPE_L:
-#if CHAR_BIT == 8
-					if (cmd_bytesz == 8) {
-						reply(200,
-						    "Type set to L (byte size 8).");
-						type = cmd_type;
-					} else
-						reply(504, "Byte size must be 8.");
-#else /* CHAR_BIT == 8 */
-					UNIMPLEMENTED for CHAR_BIT != 8
-#endif /* CHAR_BIT == 8 */
-				}
-			}
-		}
-	| STRU check_login SP struct_code CRLF
-		{
-			if ($2) {
-				switch ($4) {
-
-				case STRU_F:
-					reply(200, "STRU F accepted.");
-					break;
-
-				default:
-					reply(504, "Unimplemented STRU type.");
-				}
-			}
-		}
-	| MODE check_login SP mode_code CRLF
-		{
-			if ($2) {
-				switch ($4) {
-
-				case MODE_S:
-					reply(200, "MODE S accepted.");
-					break;
-	
-				default:
-					reply(502, "Unimplemented MODE type.");
-				}
-			}
-		}
-	| ALLO check_login SP NUMBER CRLF
-		{
-			if ($2) {
-				reply(202, "ALLO command ignored.");
-			}
-		}
-	| ALLO check_login SP NUMBER SP R SP NUMBER CRLF
-		{
-			if ($2) {
-				reply(202, "ALLO command ignored.");
-			}
-		}
-	| RETR check_login SP pathname CRLF
-		{
-			if (noretr || (guest && noguestretr))
-				reply(500, "RETR command disabled.");
-			else if ($2 && $4 != NULL)
-				retrieve(NULL, $4);
-
-			if ($4 != NULL)
-				free($4);
-		}
-	| STOR check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				store($4, "w", 0);
-			if ($4 != NULL)
-				free($4);
-		}
-	| APPE check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				store($4, "a", 0);
-			if ($4 != NULL)
-				free($4);
-		}
-	| NLST check_login CRLF
-		{
-			if ($2)
-				send_file_list(".");
-		}
-	| NLST check_login SP pathstring CRLF
-		{
-			if ($2)
-				send_file_list($4);
-			free($4);
-		}
-	| LIST check_login CRLF
-		{
-			if ($2)
-				retrieve(_PATH_LS " -lA", "");
-		}
-	| LIST check_login SP pathstring CRLF
-		{
-			if ($2)
-				retrieve(_PATH_LS " -lA %s", $4);
-			free($4);
-		}
-	| STAT check_login SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				statfilecmd($4);
-			if ($4 != NULL)
-				free($4);
-		}
-	| STAT check_login CRLF
-		{
-			if ($2) {
-				statcmd();
-			}
-		}
-	| DELE check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				delete($4);
-			if ($4 != NULL)
-				free($4);
-		}
-	| RNTO check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL) {
-				if (fromname) {
-					renamecmd(fromname, $4);
-					free(fromname);
-					fromname = NULL;
-				} else {
-					reply(503, "Bad sequence of commands.");
-				}
-			}
-			if ($4 != NULL)
-				free($4);
-		}
-	| ABOR check_login CRLF
-		{
-			if ($2)
-				reply(225, "ABOR command successful.");
-		}
-	| CWD check_login CRLF
-		{
-			if ($2) {
-				cwd(homedir);
-			}
-		}
-	| CWD check_login SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				cwd($4);
-			if ($4 != NULL)
-				free($4);
-		}
-	| HELP CRLF
-		{
-			help(cmdtab, NULL);
-		}
-	| HELP SP STRING CRLF
-		{
-			char *cp = $3;
-
-			if (strncasecmp(cp, "SITE", 4) == 0) {
-				cp = $3 + 4;
-				if (*cp == ' ')
-					cp++;
-				if (*cp)
-					help(sitetab, cp);
-				else
-					help(sitetab, NULL);
-			} else
-				help(cmdtab, $3);
-			free($3);
-		}
-	| NOOP CRLF
-		{
-			reply(200, "NOOP command successful.");
-		}
-	| MKD check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				makedir($4);
-			if ($4 != NULL)
-				free($4);
-		}
-	| RMD check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				removedir($4);
-			if ($4 != NULL)
-				free($4);
-		}
-	| PWD check_login CRLF
-		{
-			if ($2)
-				pwd();
-		}
-	| CDUP check_login CRLF
-		{
-			if ($2)
-				cwd("..");
-		}
-	| SITE SP HELP CRLF
-		{
-			help(sitetab, NULL);
-		}
-	| SITE SP HELP SP STRING CRLF
-		{
-			help(sitetab, $5);
-			free($5);
-		}
-	| SITE SP MDFIVE check_login SP pathname CRLF
-		{
-			char p[64], *q;
-
-			if ($4 && $6) {
-				q = MD5File($6, p);
-				if (q != NULL)
-					reply(200, "MD5(%s) = %s", $6, p);
-				else
-					perror_reply(550, $6);
-			}
-			if ($6)
-				free($6);
-		}
-	| SITE SP UMASK check_login CRLF
-		{
-			int oldmask;
-
-			if ($4) {
-				oldmask = umask(0);
-				(void) umask(oldmask);
-				reply(200, "Current UMASK is %03o.", oldmask);
-			}
-		}
-	| SITE SP UMASK check_login SP octal_number CRLF
-		{
-			int oldmask;
-
-			if ($4) {
-				if (($6 == -1) || ($6 > 0777)) {
-					reply(501, "Bad UMASK value.");
-				} else {
-					oldmask = umask($6);
-					reply(200,
-					    "UMASK set to %03o (was %03o).",
-					    $6, oldmask);
-				}
-			}
-		}
-	| SITE SP CHMOD check_login_ro SP octal_number SP pathname CRLF
-		{
-			if ($4 && ($8 != NULL)) {
-				if (($6 == -1 ) || ($6 > 0777))
-					reply(501, "Bad mode value.");
-				else if (chmod($8, $6) < 0)
-					perror_reply(550, $8);
-				else
-					reply(200, "CHMOD command successful.");
-			}
-			if ($8 != NULL)
-				free($8);
-		}
-	| SITE SP check_login IDLE CRLF
-		{
-			if ($3)
-				reply(200,
-			    	    "Current IDLE time limit is %d seconds; max %d.",
-				    timeout, maxtimeout);
-		}
-	| SITE SP check_login IDLE SP NUMBER CRLF
-		{
-			if ($3) {
-				if ($6.i < 30 || $6.i > maxtimeout) {
-					reply(501,
-					    "Maximum IDLE time must be between 30 and %d seconds.",
-					    maxtimeout);
-				} else {
-					timeout = $6.i;
-					(void) alarm(timeout);
-					reply(200,
-					    "Maximum IDLE time set to %d seconds.",
-					    timeout);
-				}
-			}
-		}
-	| STOU check_login_ro SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				store($4, "w", 1);
-			if ($4 != NULL)
-				free($4);
-		}
-	| FEAT CRLF
-		{
-			lreply(211, "Extensions supported:");
-#if 0
-			/* XXX these two keywords are non-standard */
-			printf(" EPRT\r\n");
-			if (!noepsv)
-				printf(" EPSV\r\n");
-#endif
-			printf(" MDTM\r\n");
-			printf(" REST STREAM\r\n");
-			printf(" SIZE\r\n");
-			if (assumeutf8) {
-				/* TVFS requires UTF8, see RFC 3659 */
-				printf(" TVFS\r\n");
-				printf(" UTF8\r\n");
-			}
-			reply(211, "End.");
-		}
-	| SYST check_login CRLF
-		{
-			if ($2) {
-				if (hostinfo)
-#ifdef BSD
-					reply(215, "UNIX Type: L%d Version: BSD-%d",
-					      CHAR_BIT, BSD);
-#else /* BSD */
-					reply(215, "UNIX Type: L%d", CHAR_BIT);
-#endif /* BSD */
-				else
-					reply(215, "UNKNOWN Type: L%d", CHAR_BIT);
-			}
-		}
-
-		/*
-		 * SIZE is not in RFC959, but Postel has blessed it and
-		 * it will be in the updated RFC.
-		 *
-		 * Return size of file in a format suitable for
-		 * using with RESTART (we just count bytes).
-		 */
-	| SIZE check_login SP pathname CRLF
-		{
-			if ($2 && $4 != NULL)
-				sizecmd($4);
-			if ($4 != NULL)
-				free($4);
-		}
-
-		/*
-		 * MDTM is not in RFC959, but Postel has blessed it and
-		 * it will be in the updated RFC.
-		 *
-		 * Return modification time of file as an ISO 3307
-		 * style time. E.g. YYYYMMDDHHMMSS or YYYYMMDDHHMMSS.xxx
-		 * where xxx is the fractional second (of any precision,
-		 * not necessarily 3 digits)
-		 */
-	| MDTM check_login SP pathname CRLF
-		{
-			if ($2 && $4 != NULL) {
-				struct stat stbuf;
-				if (stat($4, &stbuf) < 0)
-					perror_reply(550, $4);
-				else if (!S_ISREG(stbuf.st_mode)) {
-					reply(550, "%s: not a plain file.", $4);
-				} else {
-					struct tm *t;
-					t = gmtime(&stbuf.st_mtime);
-					reply(213,
-					    "%04d%02d%02d%02d%02d%02d",
-					    1900 + t->tm_year,
-					    t->tm_mon+1, t->tm_mday,
-					    t->tm_hour, t->tm_min, t->tm_sec);
-				}
-			}
-			if ($4 != NULL)
-				free($4);
-		}
-	| QUIT CRLF
-		{
-			reply(221, "Goodbye.");
-			dologout(0);
-		}
-	| NOTIMPL
-		{
-			nack($1);
-		}
-	| error
-		{
-			yyclearin;		/* discard lookahead data */
-			yyerrok;		/* clear error condition */
-			state = CMD;		/* reset lexer state */
-		}
-	;
-rcmd
-	: RNFR check_login_ro SP pathname CRLF
-		{
-			restart_point = 0;
-			if ($2 && $4) {
-				if (fromname)
-					free(fromname);
-				fromname = NULL;
-				if (renamefrom($4))
-					fromname = $4;
-				else
-					free($4);
-			} else if ($4) {
-				free($4);
-			}
-		}
-	| REST check_login SP NUMBER CRLF
-		{
-			if ($2) {
-				if (fromname)
-					free(fromname);
-				fromname = NULL;
-				restart_point = $4.o;
-				reply(350, "Restarting at %jd. %s",
-				    (intmax_t)restart_point,
-				    "Send STORE or RETRIEVE to initiate transfer.");
-			}
-		}
-	;
-
-username
-	: STRING
-	;
-
-password
-	: /* empty */
-		{
-			$$ = (char *)calloc(1, sizeof(char));
-		}
-	| STRING
-	;
-
-byte_size
-	: NUMBER
-		{
-			$$ = $1.i;
-		}
-	;
-
-host_port
-	: NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER COMMA NUMBER
-		{
-			char *a, *p;
-
-			data_dest.su_len = sizeof(struct sockaddr_in);
-			data_dest.su_family = AF_INET;
-			p = (char *)&data_dest.su_sin.sin_port;
-			p[0] = $9.i; p[1] = $11.i;
-			a = (char *)&data_dest.su_sin.sin_addr;
-			a[0] = $1.i; a[1] = $3.i; a[2] = $5.i; a[3] = $7.i;
-		}
-	;
-
-host_long_port
-	: NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER
-		{
-			char *a, *p;
-
-			memset(&data_dest, 0, sizeof(data_dest));
-			data_dest.su_len = sizeof(struct sockaddr_in6);
-			data_dest.su_family = AF_INET6;
-			p = (char *)&data_dest.su_port;
-			p[0] = $39.i; p[1] = $41.i;
-			a = (char *)&data_dest.su_sin6.sin6_addr;
-			a[0] = $5.i; a[1] = $7.i; a[2] = $9.i; a[3] = $11.i;
-			a[4] = $13.i; a[5] = $15.i; a[6] = $17.i; a[7] = $19.i;
-			a[8] = $21.i; a[9] = $23.i; a[10] = $25.i; a[11] = $27.i;
-			a[12] = $29.i; a[13] = $31.i; a[14] = $33.i; a[15] = $35.i;
-			if (his_addr.su_family == AF_INET6) {
-				/* XXX more sanity checks! */
-				data_dest.su_sin6.sin6_scope_id =
-					his_addr.su_sin6.sin6_scope_id;
-			}
-			if ($1.i != 6 || $3.i != 16 || $37.i != 2)
-				memset(&data_dest, 0, sizeof(data_dest));
-		}
-	| NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER COMMA NUMBER COMMA NUMBER COMMA NUMBER COMMA
-		NUMBER
-		{
-			char *a, *p;
-
-			memset(&data_dest, 0, sizeof(data_dest));
-			data_dest.su_sin.sin_len = sizeof(struct sockaddr_in);
-			data_dest.su_family = AF_INET;
-			p = (char *)&data_dest.su_port;
-			p[0] = $15.i; p[1] = $17.i;
-			a = (char *)&data_dest.su_sin.sin_addr;
-			a[0] =  $5.i; a[1] = $7.i; a[2] = $9.i; a[3] = $11.i;
-			if ($1.i != 4 || $3.i != 4 || $13.i != 2)
-				memset(&data_dest, 0, sizeof(data_dest));
-		}
-	;
-
-form_code
-	: N
-		{
-			$$ = FORM_N;
-		}
-	| T
-		{
-			$$ = FORM_T;
-		}
-	| C
-		{
-			$$ = FORM_C;
-		}
-	;
-
-type_code
-	: A
-		{
-			cmd_type = TYPE_A;
-			cmd_form = FORM_N;
-		}
-	| A SP form_code
-		{
-			cmd_type = TYPE_A;
-			cmd_form = $3;
-		}
-	| E
-		{
-			cmd_type = TYPE_E;
-			cmd_form = FORM_N;
-		}
-	| E SP form_code
-		{
-			cmd_type = TYPE_E;
-			cmd_form = $3;
-		}
-	| I
-		{
-			cmd_type = TYPE_I;
-		}
-	| L
-		{
-			cmd_type = TYPE_L;
-			cmd_bytesz = CHAR_BIT;
-		}
-	| L SP byte_size
-		{
-			cmd_type = TYPE_L;
-			cmd_bytesz = $3;
-		}
-		/* this is for a bug in the BBN ftp */
-	| L byte_size
-		{
-			cmd_type = TYPE_L;
-			cmd_bytesz = $2;
-		}
-	;
-
-struct_code
-	: F
-		{
-			$$ = STRU_F;
-		}
-	| R
-		{
-			$$ = STRU_R;
-		}
-	| P
-		{
-			$$ = STRU_P;
-		}
-	;
-
-mode_code
-	: S
-		{
-			$$ = MODE_S;
-		}
-	| B
-		{
-			$$ = MODE_B;
-		}
-	| C
-		{
-			$$ = MODE_C;
-		}
-	;
-
-pathname
-	: pathstring
-		{
-			if (logged_in && $1) {
-				char *p;
-
-				/*
-				 * Expand ~user manually since glob(3)
-				 * will return the unexpanded pathname
-				 * if the corresponding file/directory
-				 * doesn't exist yet.  Using sole glob(3)
-				 * would break natural commands like
-				 * MKD ~user/newdir
-				 * or
-				 * RNTO ~/newfile
-				 */
-				if ((p = exptilde($1)) != NULL) {
-					$$ = expglob(p);
-					free(p);
-				} else
-					$$ = NULL;
-				free($1);
-			} else
-				$$ = $1;
-		}
-	;
-
-pathstring
-	: STRING
-	;
-
-octal_number
-	: NUMBER
-		{
-			int ret, dec, multby, digit;
-
-			/*
-			 * Convert a number that was read as decimal number
-			 * to what it would be if it had been read as octal.
-			 */
-			dec = $1.i;
-			multby = 1;
-			ret = 0;
-			while (dec) {
-				digit = dec%10;
-				if (digit > 7) {
-					ret = -1;
-					break;
-				}
-				ret += digit * multby;
-				multby *= 8;
-				dec /= 10;
-			}
-			$$ = ret;
-		}
-	;
-
-
-check_login
-	: /* empty */
-		{
-		$$ = check_login1();
-		}
-	;
-
-check_login_epsv
-	: /* empty */
-		{
-		if (noepsv) {
-			reply(500, "EPSV command disabled.");
-			$$ = 0;
-		}
-		else
-			$$ = check_login1();
-		}
-	;
-
-check_login_ro
-	: /* empty */
-		{
-		if (readonly) {
-			reply(550, "Permission denied.");
-			$$ = 0;
-		}
-		else
-			$$ = check_login1();
-		}
-	;
-
-%%
-
-#define	CMD	0	/* beginning of command */
-#define	ARGS	1	/* expect miscellaneous arguments */
-#define	STR1	2	/* expect SP followed by STRING */
-#define	STR2	3	/* expect STRING */
-#define	OSTR	4	/* optional SP then STRING */
-#define	ZSTR1	5	/* optional SP then optional STRING */
-#define	ZSTR2	6	/* optional STRING after SP */
-#define	SITECMD	7	/* SITE command */
-#define	NSTR	8	/* Number followed by a string */
-
-#define	MAXGLOBARGS	1000
-
-#define	MAXASIZE	10240	/* Deny ASCII SIZE on files larger than that */
-
-struct tab {
-	char	*name;
-	short	token;
-	short	state;
-	short	implemented;	/* 1 if command is implemented */
-	char	*help;
-};
-
-struct tab cmdtab[] = {		/* In order defined in RFC 765 */
-	{ "USER", USER, STR1, 1,	"<sp> username" },
-	{ "PASS", PASS, ZSTR1, 1,	"[<sp> [password]]" },
-	{ "ACCT", ACCT, STR1, 0,	"(specify account)" },
-	{ "SMNT", SMNT, ARGS, 0,	"(structure mount)" },
-	{ "REIN", REIN, ARGS, 0,	"(reinitialize server state)" },
-	{ "QUIT", QUIT, ARGS, 1,	"(terminate service)", },
-	{ "PORT", PORT, ARGS, 1,	"<sp> b0, b1, b2, b3, b4, b5" },
-	{ "LPRT", LPRT, ARGS, 1,	"<sp> af, hal, h1, h2, h3,..., pal, p1, p2..." },
-	{ "EPRT", EPRT, STR1, 1,	"<sp> |af|addr|port|" },
-	{ "PASV", PASV, ARGS, 1,	"(set server in passive mode)" },
-	{ "LPSV", LPSV, ARGS, 1,	"(set server in passive mode)" },
-	{ "EPSV", EPSV, ARGS, 1,	"[<sp> af|ALL]" },
-	{ "TYPE", TYPE, ARGS, 1,	"<sp> { A | E | I | L }" },
-	{ "STRU", STRU, ARGS, 1,	"(specify file structure)" },
-	{ "MODE", MODE, ARGS, 1,	"(specify transfer mode)" },
-	{ "RETR", RETR, STR1, 1,	"<sp> file-name" },
-	{ "STOR", STOR, STR1, 1,	"<sp> file-name" },
-	{ "APPE", APPE, STR1, 1,	"<sp> file-name" },
-	{ "MLFL", MLFL, OSTR, 0,	"(mail file)" },
-	{ "MAIL", MAIL, OSTR, 0,	"(mail to user)" },
-	{ "MSND", MSND, OSTR, 0,	"(mail send to terminal)" },
-	{ "MSOM", MSOM, OSTR, 0,	"(mail send to terminal or mailbox)" },
-	{ "MSAM", MSAM, OSTR, 0,	"(mail send to terminal and mailbox)" },
-	{ "MRSQ", MRSQ, OSTR, 0,	"(mail recipient scheme question)" },
-	{ "MRCP", MRCP, STR1, 0,	"(mail recipient)" },
-	{ "ALLO", ALLO, ARGS, 1,	"allocate storage (vacuously)" },
-	{ "REST", REST, ARGS, 1,	"<sp> offset (restart command)" },
-	{ "RNFR", RNFR, STR1, 1,	"<sp> file-name" },
-	{ "RNTO", RNTO, STR1, 1,	"<sp> file-name" },
-	{ "ABOR", ABOR, ARGS, 1,	"(abort operation)" },
-	{ "DELE", DELE, STR1, 1,	"<sp> file-name" },
-	{ "CWD",  CWD,  OSTR, 1,	"[ <sp> directory-name ]" },
-	{ "XCWD", CWD,	OSTR, 1,	"[ <sp> directory-name ]" },
-	{ "LIST", LIST, OSTR, 1,	"[ <sp> path-name ]" },
-	{ "NLST", NLST, OSTR, 1,	"[ <sp> path-name ]" },
-	{ "SITE", SITE, SITECMD, 1,	"site-cmd [ <sp> arguments ]" },
-	{ "SYST", SYST, ARGS, 1,	"(get type of operating system)" },
-	{ "FEAT", FEAT, ARGS, 1,	"(get extended features)" },
-	{ "STAT", STAT, OSTR, 1,	"[ <sp> path-name ]" },
-	{ "HELP", HELP, OSTR, 1,	"[ <sp> <string> ]" },
-	{ "NOOP", NOOP, ARGS, 1,	"" },
-	{ "MKD",  MKD,  STR1, 1,	"<sp> path-name" },
-	{ "XMKD", MKD,  STR1, 1,	"<sp> path-name" },
-	{ "RMD",  RMD,  STR1, 1,	"<sp> path-name" },
-	{ "XRMD", RMD,  STR1, 1,	"<sp> path-name" },
-	{ "PWD",  PWD,  ARGS, 1,	"(return current directory)" },
-	{ "XPWD", PWD,  ARGS, 1,	"(return current directory)" },
-	{ "CDUP", CDUP, ARGS, 1,	"(change to parent directory)" },
-	{ "XCUP", CDUP, ARGS, 1,	"(change to parent directory)" },
-	{ "STOU", STOU, STR1, 1,	"<sp> file-name" },
-	{ "SIZE", SIZE, OSTR, 1,	"<sp> path-name" },
-	{ "MDTM", MDTM, OSTR, 1,	"<sp> path-name" },
-	{ NULL,   0,    0,    0,	0 }
-};
-
-struct tab sitetab[] = {
-	{ "MD5", MDFIVE, STR1, 1,	"[ <sp> file-name ]" },
-	{ "UMASK", UMASK, ARGS, 1,	"[ <sp> umask ]" },
-	{ "IDLE", IDLE, ARGS, 1,	"[ <sp> maximum-idle-time ]" },
-	{ "CHMOD", CHMOD, NSTR, 1,	"<sp> mode <sp> file-name" },
-	{ "HELP", HELP, OSTR, 1,	"[ <sp> <string> ]" },
-	{ NULL,   0,    0,    0,	0 }
-};
-
-static char	*copy(char *);
-static char	*expglob(char *);
-static char	*exptilde(char *);
-static void	 help(struct tab *, char *);
-static struct tab *
-		 lookup(struct tab *, char *);
-static int	 port_check(const char *);
-#ifdef INET6
-static int	 port_check_v6(const char *);
-#endif
-static void	 sizecmd(char *);
-static void	 toolong(int);
-#ifdef INET6
-static void	 v4map_data_dest(void);
-#endif
-static int	 yylex(void);
-
-static struct tab *
-lookup(struct tab *p, char *cmd)
-{
-
-	for (; p->name != NULL; p++)
-		if (strcmp(cmd, p->name) == 0)
-			return (p);
-	return (0);
-}
-
-#include <arpa/telnet.h>
-
-/*
- * get_line - a hacked up version of fgets to ignore TELNET escape codes.
- */
-int
-get_line(char *s, int n, FILE *iop)
-{
-	int c;
-	register char *cs;
-	sigset_t sset, osset;
-
-	cs = s;
-/* tmpline may contain saved command from urgent mode interruption */
-	for (c = 0; tmpline[c] != '\0' && --n > 0; ++c) {
-		*cs++ = tmpline[c];
-		if (tmpline[c] == '\n') {
-			*cs++ = '\0';
-			if (ftpdebug)
-				syslog(LOG_DEBUG, "command: %s", s);
-			tmpline[0] = '\0';
-			return(0);
-		}
-		if (c == 0)
-			tmpline[0] = '\0';
-	}
-	/* SIGURG would interrupt stdio if not blocked during the read loop */
-	sigemptyset(&sset);
-	sigaddset(&sset, SIGURG);
-	sigprocmask(SIG_BLOCK, &sset, &osset);
-	while ((c = getc(iop)) != EOF) {
-		c &= 0377;
-		if (c == IAC) {
-			if ((c = getc(iop)) == EOF)
-				goto got_eof;
-			c &= 0377;
-			switch (c) {
-			case WILL:
-			case WONT:
-				if ((c = getc(iop)) == EOF)
-					goto got_eof;
-				printf("%c%c%c", IAC, DONT, 0377&c);
-				(void) fflush(stdout);
-				continue;
-			case DO:
-			case DONT:
-				if ((c = getc(iop)) == EOF)
-					goto got_eof;
-				printf("%c%c%c", IAC, WONT, 0377&c);
-				(void) fflush(stdout);
-				continue;
-			case IAC:
-				break;
-			default:
-				continue;	/* ignore command */
-			}
-		}
-		*cs++ = c;
-		if (--n <= 0) {
-			/*
-			 * If command doesn't fit into buffer, discard the
-			 * rest of the command and indicate truncation.
-			 * This prevents the command to be split up into
-			 * multiple commands.
-			 */
-			while (c != '\n' && (c = getc(iop)) != EOF)
-				;
-			return (-2);
-		}
-		if (c == '\n')
-			break;
-	}
-got_eof:
-	sigprocmask(SIG_SETMASK, &osset, NULL);
-	if (c == EOF && cs == s)
-		return (-1);
-	*cs++ = '\0';
-	if (ftpdebug) {
-		if (!guest && strncasecmp("pass ", s, 5) == 0) {
-			/* Don't syslog passwords */
-			syslog(LOG_DEBUG, "command: %.5s ???", s);
-		} else {
-			register char *cp;
-			register int len;
-
-			/* Don't syslog trailing CR-LF */
-			len = strlen(s);
-			cp = s + len - 1;
-			while (cp >= s && (*cp == '\n' || *cp == '\r')) {
-				--cp;
-				--len;
-			}
-			syslog(LOG_DEBUG, "command: %.*s", len, s);
-		}
-	}
-	return (0);
-}
-
-static void
-toolong(int signo)
-{
-
-	reply(421,
-	    "Timeout (%d seconds): closing control connection.", timeout);
-	if (logging)
-		syslog(LOG_INFO, "User %s timed out after %d seconds",
-		    (pw ? pw -> pw_name : "unknown"), timeout);
-	dologout(1);
-}
-
-static int
-yylex(void)
-{
-	static int cpos;
-	char *cp, *cp2;
-	struct tab *p;
-	int n;
-	char c;
-
-	for (;;) {
-		switch (state) {
-
-		case CMD:
-			(void) signal(SIGALRM, toolong);
-			(void) alarm(timeout);
-			n = get_line(cbuf, sizeof(cbuf)-1, stdin);
-			if (n == -1) {
-				reply(221, "You could at least say goodbye.");
-				dologout(0);
-			} else if (n == -2) {
-				reply(500, "Command too long.");
-				(void) alarm(0);
-				continue;
-			}
-			(void) alarm(0);
-#ifdef SETPROCTITLE
-			if (strncasecmp(cbuf, "PASS", 4) != 0)
-				setproctitle("%s: %s", proctitle, cbuf);
-#endif /* SETPROCTITLE */
-			if ((cp = strchr(cbuf, '\r'))) {
-				*cp++ = '\n';
-				*cp = '\0';
-			}
-			if ((cp = strpbrk(cbuf, " \n")))
-				cpos = cp - cbuf;
-			if (cpos == 0)
-				cpos = 4;
-			c = cbuf[cpos];
-			cbuf[cpos] = '\0';
-			upper(cbuf);
-			p = lookup(cmdtab, cbuf);
-			cbuf[cpos] = c;
-			if (p != 0) {
-				yylval.s = p->name;
-				if (!p->implemented)
-					return (NOTIMPL); /* state remains CMD */
-				state = p->state;
-				return (p->token);
-			}
-			break;
-
-		case SITECMD:
-			if (cbuf[cpos] == ' ') {
-				cpos++;
-				return (SP);
-			}
-			cp = &cbuf[cpos];
-			if ((cp2 = strpbrk(cp, " \n")))
-				cpos = cp2 - cbuf;
-			c = cbuf[cpos];
-			cbuf[cpos] = '\0';
-			upper(cp);
-			p = lookup(sitetab, cp);
-			cbuf[cpos] = c;
-			if (guest == 0 && p != 0) {
-				yylval.s = p->name;
-				if (!p->implemented) {
-					state = CMD;
-					return (NOTIMPL);
-				}
-				state = p->state;
-				return (p->token);
-			}
-			state = CMD;
-			break;
-
-		case ZSTR1:
-		case OSTR:
-			if (cbuf[cpos] == '\n') {
-				state = CMD;
-				return (CRLF);
-			}
-			/* FALLTHROUGH */
-
-		case STR1:
-		dostr1:
-			if (cbuf[cpos] == ' ') {
-				cpos++;
-				state = state == OSTR ? STR2 : state+1;
-				return (SP);
-			}
-			break;
-
-		case ZSTR2:
-			if (cbuf[cpos] == '\n') {
-				state = CMD;
-				return (CRLF);
-			}
-			/* FALLTHROUGH */
-
-		case STR2:
-			cp = &cbuf[cpos];
-			n = strlen(cp);
-			cpos += n - 1;
-			/*
-			 * Make sure the string is nonempty and \n terminated.
-			 */
-			if (n > 1 && cbuf[cpos] == '\n') {
-				cbuf[cpos] = '\0';
-				yylval.s = copy(cp);
-				cbuf[cpos] = '\n';
-				state = ARGS;
-				return (STRING);
-			}
-			break;
-
-		case NSTR:
-			if (cbuf[cpos] == ' ') {
-				cpos++;
-				return (SP);
-			}
-			if (isdigit(cbuf[cpos])) {
-				cp = &cbuf[cpos];
-				while (isdigit(cbuf[++cpos]))
-					;
-				c = cbuf[cpos];
-				cbuf[cpos] = '\0';
-				yylval.u.i = atoi(cp);
-				cbuf[cpos] = c;
-				state = STR1;
-				return (NUMBER);
-			}
-			state = STR1;
-			goto dostr1;
-
-		case ARGS:
-			if (isdigit(cbuf[cpos])) {
-				cp = &cbuf[cpos];
-				while (isdigit(cbuf[++cpos]))
-					;
-				c = cbuf[cpos];
-				cbuf[cpos] = '\0';
-				yylval.u.i = atoi(cp);
-				yylval.u.o = strtoull(cp, NULL, 10);
-				cbuf[cpos] = c;
-				return (NUMBER);
-			}
-			if (strncasecmp(&cbuf[cpos], "ALL", 3) == 0
-			 && !isalnum(cbuf[cpos + 3])) {
-				cpos += 3;
-				return ALL;
-			}
-			switch (cbuf[cpos++]) {
-
-			case '\n':
-				state = CMD;
-				return (CRLF);
-
-			case ' ':
-				return (SP);
-
-			case ',':
-				return (COMMA);
-
-			case 'A':
-			case 'a':
-				return (A);
-
-			case 'B':
-			case 'b':
-				return (B);
-
-			case 'C':
-			case 'c':
-				return (C);
-
-			case 'E':
-			case 'e':
-				return (E);
-
-			case 'F':
-			case 'f':
-				return (F);
-
-			case 'I':
-			case 'i':
-				return (I);
-
-			case 'L':
-			case 'l':
-				return (L);
-
-			case 'N':
-			case 'n':
-				return (N);
-
-			case 'P':
-			case 'p':
-				return (P);
-
-			case 'R':
-			case 'r':
-				return (R);
-
-			case 'S':
-			case 's':
-				return (S);
-
-			case 'T':
-			case 't':
-				return (T);
-
-			}
-			break;
-
-		default:
-			fatalerror("Unknown state in scanner.");
-		}
-		state = CMD;
-		return (LEXERR);
-	}
-}
-
-void
-upper(char *s)
-{
-	while (*s != '\0') {
-		if (islower(*s))
-			*s = toupper(*s);
-		s++;
-	}
-}
-
-static char *
-copy(char *s)
-{
-	char *p;
-
-	p = malloc(strlen(s) + 1);
-	if (p == NULL)
-		fatalerror("Ran out of memory.");
-	(void) strcpy(p, s);
-	return (p);
-}
-
-static void
-help(struct tab *ctab, char *s)
-{
-	struct tab *c;
-	int width, NCMDS;
-	char *type;
-
-	if (ctab == sitetab)
-		type = "SITE ";
-	else
-		type = "";
-	width = 0, NCMDS = 0;
-	for (c = ctab; c->name != NULL; c++) {
-		int len = strlen(c->name);
-
-		if (len > width)
-			width = len;
-		NCMDS++;
-	}
-	width = (width + 8) &~ 7;
-	if (s == 0) {
-		int i, j, w;
-		int columns, lines;
-
-		lreply(214, "The following %scommands are recognized %s.",
-		    type, "(* =>'s unimplemented)");
-		columns = 76 / width;
-		if (columns == 0)
-			columns = 1;
-		lines = (NCMDS + columns - 1) / columns;
-		for (i = 0; i < lines; i++) {
-			printf("   ");
-			for (j = 0; j < columns; j++) {
-				c = ctab + j * lines + i;
-				printf("%s%c", c->name,
-					c->implemented ? ' ' : '*');
-				if (c + lines >= &ctab[NCMDS])
-					break;
-				w = strlen(c->name) + 1;
-				while (w < width) {
-					putchar(' ');
-					w++;
-				}
-			}
-			printf("\r\n");
-		}
-		(void) fflush(stdout);
-		if (hostinfo)
-			reply(214, "Direct comments to ftp-bugs@%s.", hostname);
-		else
-			reply(214, "End.");
-		return;
-	}
-	upper(s);
-	c = lookup(ctab, s);
-	if (c == NULL) {
-		reply(502, "Unknown command %s.", s);
-		return;
-	}
-	if (c->implemented)
-		reply(214, "Syntax: %s%s %s", type, c->name, c->help);
-	else
-		reply(214, "%s%-*s\t%s; unimplemented.", type, width,
-		    c->name, c->help);
-}
-
-static void
-sizecmd(char *filename)
-{
-	switch (type) {
-	case TYPE_L:
-	case TYPE_I: {
-		struct stat stbuf;
-		if (stat(filename, &stbuf) < 0)
-			perror_reply(550, filename);
-		else if (!S_ISREG(stbuf.st_mode))
-			reply(550, "%s: not a plain file.", filename);
-		else
-			reply(213, "%jd", (intmax_t)stbuf.st_size);
-		break; }
-	case TYPE_A: {
-		FILE *fin;
-		int c;
-		off_t count;
-		struct stat stbuf;
-		fin = fopen(filename, "r");
-		if (fin == NULL) {
-			perror_reply(550, filename);
-			return;
-		}
-		if (fstat(fileno(fin), &stbuf) < 0) {
-			perror_reply(550, filename);
-			(void) fclose(fin);
-			return;
-		} else if (!S_ISREG(stbuf.st_mode)) {
-			reply(550, "%s: not a plain file.", filename);
-			(void) fclose(fin);
-			return;
-		} else if (stbuf.st_size > MAXASIZE) {
-			reply(550, "%s: too large for type A SIZE.", filename);
-			(void) fclose(fin);
-			return;
-		}
-
-		count = 0;
-		while((c=getc(fin)) != EOF) {
-			if (c == '\n')	/* will get expanded to \r\n */
-				count++;
-			count++;
-		}
-		(void) fclose(fin);
-
-		reply(213, "%jd", (intmax_t)count);
-		break; }
-	default:
-		reply(504, "SIZE not implemented for type %s.",
-		           typenames[type]);
-	}
-}
-
-/* Return 1, if port check is done. Return 0, if not yet. */
-static int
-port_check(const char *pcmd)
-{
-	if (his_addr.su_family == AF_INET) {
-		if (data_dest.su_family != AF_INET) {
-			usedefault = 1;
-			reply(500, "Invalid address rejected.");
-			return 1;
-		}
-		if (paranoid &&
-		    ((ntohs(data_dest.su_port) < IPPORT_RESERVED) ||
-		     memcmp(&data_dest.su_sin.sin_addr,
-			    &his_addr.su_sin.sin_addr,
-			    sizeof(data_dest.su_sin.sin_addr)))) {
-			usedefault = 1;
-			reply(500, "Illegal PORT range rejected.");
-		} else {
-			usedefault = 0;
-			if (pdata >= 0) {
-				(void) close(pdata);
-				pdata = -1;
-			}
-			reply(200, "%s command successful.", pcmd);
-		}
-		return 1;
-	}
-	return 0;
-}
-
-static int
-check_login1(void)
-{
-	if (logged_in)
-		return 1;
-	else {
-		reply(530, "Please login with USER and PASS.");
-		return 0;
-	}
-}
-
-/*
- * Replace leading "~user" in a pathname by the user's login directory.
- * Returned string will be in a freshly malloced buffer unless it's NULL.
- */
-static char *
-exptilde(char *s)
-{
-	char *p, *q;
-	char *path, *user;
-	struct passwd *ppw;
-
-	if ((p = strdup(s)) == NULL)
-		return (NULL);
-	if (*p != '~')
-		return (p);
-
-	user = p + 1;	/* skip tilde */
-	if ((path = strchr(p, '/')) != NULL)
-		*(path++) = '\0'; /* separate ~user from the rest of path */
-	if (*user == '\0') /* no user specified, use the current user */
-		user = pw->pw_name;
-	/* read passwd even for the current user since we may be chrooted */
-	if ((ppw = getpwnam(user)) != NULL) {
-		/* user found, substitute login directory for ~user */
-		if (path)
-			asprintf(&q, "%s/%s", ppw->pw_dir, path);
-		else
-			q = strdup(ppw->pw_dir);
-		free(p);
-		p = q;
-	} else {
-		/* user not found, undo the damage */
-		if (path)
-			path[-1] = '/';
-	}
-	return (p);
-}
-
-/*
- * Expand glob(3) patterns possibly present in a pathname.
- * Avoid expanding to a pathname including '\r' or '\n' in order to
- * not disrupt the FTP protocol.
- * The expansion found must be unique.
- * Return the result as a malloced string, or NULL if an error occurred.
- *
- * Problem: this production is used for all pathname
- * processing, but only gives a 550 error reply.
- * This is a valid reply in some cases but not in others.
- */
-static char *
-expglob(char *s)
-{
-	char *p, **pp, *rval;
-	int flags = GLOB_BRACE | GLOB_NOCHECK;
-	int n;
-	glob_t gl;
-
-	memset(&gl, 0, sizeof(gl));
-	flags |= GLOB_LIMIT;
-	gl.gl_matchc = MAXGLOBARGS;
-	if (glob(s, flags, NULL, &gl) == 0 && gl.gl_pathc != 0) {
-		for (pp = gl.gl_pathv, p = NULL, n = 0; *pp; pp++)
-			if (*(*pp + strcspn(*pp, "\r\n")) == '\0') {
-				p = *pp;
-				n++;
-			}
-		if (n == 0)
-			rval = strdup(s);
-		else if (n == 1)
-			rval = strdup(p);
-		else {
-			reply(550, "Wildcard is ambiguous.");
-			rval = NULL;
-		}
-	} else {
-		reply(550, "Wildcard expansion error.");
-		rval = NULL;
-	}
-	globfree(&gl);
-	return (rval);
-}
-
-#ifdef INET6
-/* Return 1, if port check is done. Return 0, if not yet. */
-static int
-port_check_v6(const char *pcmd)
-{
-	if (his_addr.su_family == AF_INET6) {
-		if (IN6_IS_ADDR_V4MAPPED(&his_addr.su_sin6.sin6_addr))
-			/* Convert data_dest into v4 mapped sockaddr.*/
-			v4map_data_dest();
-		if (data_dest.su_family != AF_INET6) {
-			usedefault = 1;
-			reply(500, "Invalid address rejected.");
-			return 1;
-		}
-		if (paranoid &&
-		    ((ntohs(data_dest.su_port) < IPPORT_RESERVED) ||
-		     memcmp(&data_dest.su_sin6.sin6_addr,
-			    &his_addr.su_sin6.sin6_addr,
-			    sizeof(data_dest.su_sin6.sin6_addr)))) {
-			usedefault = 1;
-			reply(500, "Illegal PORT range rejected.");
-		} else {
-			usedefault = 0;
-			if (pdata >= 0) {
-				(void) close(pdata);
-				pdata = -1;
-			}
-			reply(200, "%s command successful.", pcmd);
-		}
-		return 1;
-	}
-	return 0;
-}
-
-static void
-v4map_data_dest(void)
-{
-	struct in_addr savedaddr;
-	int savedport;
-
-	if (data_dest.su_family != AF_INET) {
-		usedefault = 1;
-		reply(500, "Invalid address rejected.");
-		return;
-	}
-
-	savedaddr = data_dest.su_sin.sin_addr;
-	savedport = data_dest.su_port;
-
-	memset(&data_dest, 0, sizeof(data_dest));
-	data_dest.su_sin6.sin6_len = sizeof(struct sockaddr_in6);
-	data_dest.su_sin6.sin6_family = AF_INET6;
-	data_dest.su_sin6.sin6_port = savedport;
-	memset((caddr_t)&data_dest.su_sin6.sin6_addr.s6_addr[10], 0xff, 2);
-	memcpy((caddr_t)&data_dest.su_sin6.sin6_addr.s6_addr[12],
-	       (caddr_t)&savedaddr, sizeof(savedaddr));
-}
-#endif
diff --git a/libexec/ftpd/ftpd.8 b/libexec/ftpd/ftpd.8
deleted file mode 100644
index 96db4753209e..000000000000
--- a/libexec/ftpd/ftpd.8
+++ /dev/null
@@ -1,589 +0,0 @@
-.\" Copyright (c) 1985, 1988, 1991, 1993
-.\"	The Regents of the University of California.  All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
-.\" 3. Neither the name of the University nor the names of its contributors
-.\"    may be used to endorse or promote products derived from this software
-.\"    without specific prior written permission.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.Dd June 26, 2025
-.Dt FTPD 8
-.Os
-.Sh NAME
-.Nm ftpd
-.Nd Internet File Transfer Protocol server
-.Sh SYNOPSIS
-.Nm
-.Op Fl 468BDdEhMmOoRrSUvW
-.Bq Fl A | Fl n
-.Op Fl l Op Fl l
-.Op Fl a Ar address
-.Op Fl P Ar port
-.Op Fl p Ar file
-.Op Fl T Ar maxtimeout
-.Op Fl t Ar timeout
-.Op Fl u Ar umask
-.Sh DEPRECATION NOTICE
-The
-.Fx
-base system
-.Nm
-is deprecated, and will be removed in
-.Fx 15.0 .
-Users are advised to install the
-.Pa ftp/freebsd-ftpd
-port or package instead.
-.Sh DESCRIPTION
-The
-.Nm
-utility is the
-Internet File Transfer Protocol
-server process.
-The server uses the TCP protocol
-and listens at the port specified with the
-.Fl P
-option or in the
-.Dq ftp
-service specification; see
-.Xr services 5 .
-.Pp
-Available options:
-.Bl -tag -width indent
-.It Fl 4
-When
-.Fl D
-is specified, accept connections via
-.Dv AF_INET
-socket.
-.It Fl 6
-When
-.Fl D
-is specified, accept connections via
-.Dv AF_INET6
-socket.
-.It Fl 8
-Enable transparent UTF-8 mode.
-RFC\ 2640 compliant clients will be told that the character encoding
-used by the server is UTF-8, which is the only effect of the option.
-.Pp
-This option does not enable any encoding conversion for server file names;
-it implies instead that the names of files on the server are encoded
-in UTF-8.
-As for files uploaded via FTP, it is the duty of the RFC\ 2640 compliant
-client to convert their names from the client's local encoding to UTF-8.
-FTP command names and own
-.Nm
-messages are always encoded in ASCII, which is a subset of UTF-8.
-Hence no need for server-side conversion at all.
-.It Fl A
-Allow only anonymous ftp access.
-.It Fl a
-When
-.Fl D
-is specified, accept connections only on the specified
-.Ar address .
-.It Fl B
-With this option set,
-.Nm
-sends authentication success and failure messages to the
-.Xr blacklistd 8
-daemon.
-If this option is not specified, no communcation with the
-.Xr blacklistd 8
-daemon is attempted.
-.It Fl D
-With this option set,
-.Nm
-will detach and become a daemon, accepting connections on the FTP port and
-forking children processes to handle them.
-This is lower overhead than starting
-.Nm
-from
-.Xr inetd 8
-and is thus useful on busy servers to reduce load.
-.It Fl d
-Debugging information is written to the syslog using
-.Dv LOG_FTP .
-.It Fl E
-Disable the EPSV command.
-This is useful for servers behind older firewalls.
-.It Fl h
-Disable printing host-specific information, such as the
-server software version or hostname, in server messages.
-.It Fl l
-Each successful and failed
-.Xr ftp 1
-session is logged using syslog with a facility of
-.Dv LOG_FTP .
-If this option is specified twice, the retrieve (get), store (put), append,
-delete, make directory, remove directory and rename operations and
-their filename arguments are also logged.
-By default,
-.Xr syslogd 8
-logs these to
-.Pa /var/log/xferlog .
-.It Fl M
-Prevent anonymous users from creating directories.
-.It Fl m
-Permit anonymous users to overwrite or modify
-existing files if allowed by file system permissions.
-By default, anonymous users cannot modify existing files;
-in particular, files to upload will be created under a unique name.
-.It Fl n
-Disable anonymous FTP access.
-The
-.Fl n
-option is mutually exclusive with the
-.Fl A
-option.
-.It Fl O
-Put server in write-only mode for anonymous users only.
-RETR is disabled for anonymous users, preventing anonymous downloads.
-This has no effect if
-.Fl o
-is also specified.
-.It Fl o
-Put server in write-only mode.
-RETR is disabled, preventing downloads.
-.It Fl P
-When
-.Fl D
-is specified, accept connections at
-.Ar port ,
-specified as a numeric value or service name, instead of at the default
-.Dq ftp
-port.
-.It Fl p
-When
-.Fl D
-is specified, write the daemon's process ID to
-.Ar file
-instead of the default pid file,
-.Pa /var/run/ftpd.pid .
-.It Fl R
-With this option set,
-.Nm
-will revert to historical behavior with regard to security checks on
-user operations and restrictions on PORT requests.
-Currently,
-.Nm
-will only honor PORT commands directed to unprivileged ports on the
-remote user's host (which violates the FTP protocol specification but
-closes some security holes).
-.It Fl r
-Put server in read-only mode.
-All commands which may modify the local file system are disabled.
-.It Fl S
-With this option set,
-.Nm
-logs all anonymous file downloads to the file
-.Pa /var/log/ftpd
-when this file exists.
-.It Fl T
-A client may also request a different timeout period;
-the maximum period allowed may be set to
-.Ar timeout
-seconds with the
-.Fl T
-option.
-The default limit is 2 hours.
-.It Fl t
-The inactivity timeout period is set to
-.Ar timeout
-seconds (the default is 15 minutes).
-.It Fl U
-This option instructs ftpd to use data ports in the range of
-.Dv IP_PORTRANGE_DEFAULT
-instead of in the range of
-.Dv IP_PORTRANGE_HIGH .
-Such a change may be useful for some specific firewall configurations;
-see
-.Xr ip 4
-for more information.
-.Pp
-Note that option is a virtual no-op in
-.Fx 5.0
-and above; both port
-ranges are identical by default.
-.It Fl u
-The default file creation mode mask is set to
-.Ar umask ,
-which is expected to be an octal numeric value.
-Refer to
-.Xr umask 2
-for details.
-This option may be overridden by
-.Xr login.conf 5 .
-.It Fl v
-A synonym for
-.Fl d .
-.It Fl W
-Do not log FTP sessions to the user accounting database.
-.El
-.Pp
-The file
-.Pa /var/run/nologin
-can be used to disable ftp access.
-If the file exists,
-.Nm
-displays it and exits.
-If the file
-.Pa /etc/ftpwelcome
-exists,
-.Nm
-prints it before issuing the
-.Dq ready
-message.
-If the file
-.Pa /etc/ftpmotd
-exists,
-.Nm
-prints it after a successful login.
-Note the motd file used is the one
-relative to the login environment.
-This means the one in
-.Pa ~ftp/etc
-in the anonymous user's case.
-.Pp
-The ftp server currently supports the following ftp requests.
-The case of the requests is ignored.
-Requests marked [RW] are
-disabled if
-.Fl r
-is specified.
-.Bl -column "Request" -offset indent
-.It Sy Request Ta Sy "Description"
-.It ABOR Ta "abort previous command"
-.It ACCT Ta "specify account (ignored)"
-.It ALLO Ta "allocate storage (vacuously)"
-.It APPE Ta "append to a file [RW]"
-.It CDUP Ta "change to parent of current working directory"
-.It CWD Ta "change working directory"
-.It DELE Ta "delete a file [RW]"
-.It EPRT Ta "specify data connection port, multiprotocol"
-.It EPSV Ta "prepare for server-to-server transfer, multiprotocol"
-.It FEAT Ta "give information on extended features of server"
-.It HELP Ta "give help information"
-.It LIST Ta "give list files in a directory" Pq Dq Li "ls -lA"
-.It LPRT Ta "specify data connection port, multiprotocol"
-.It LPSV Ta "prepare for server-to-server transfer, multiprotocol"
-.It MDTM Ta "show last modification time of file"
-.It MKD Ta "make a directory [RW]"
-.It MODE Ta "specify data transfer" Em mode
-.It NLST Ta "give name list of files in directory"
-.It NOOP Ta "do nothing"
-.It PASS Ta "specify password"
-.It PASV Ta "prepare for server-to-server transfer"
-.It PORT Ta "specify data connection port"
-.It PWD Ta "print the current working directory"
-.It QUIT Ta "terminate session"
-.It REST Ta "restart incomplete transfer"
-.It RETR Ta "retrieve a file"
-.It RMD Ta "remove a directory [RW]"
-.It RNFR Ta "specify rename-from file name [RW]"
-.It RNTO Ta "specify rename-to file name [RW]"
-.It SITE Ta "non-standard commands (see next section)"
-.It SIZE Ta "return size of file"
-.It STAT Ta "return status of server"
-.It STOR Ta "store a file [RW]"
-.It STOU Ta "store a file with a unique name [RW]"
-.It STRU Ta "specify data transfer" Em structure
-.It SYST Ta "show operating system type of server system"
-.It TYPE Ta "specify data transfer" Em type
-.It USER Ta "specify user name"
-.It XCUP Ta "change to parent of current working directory (deprecated)"
-.It XCWD Ta "change working directory (deprecated)"
-.It XMKD Ta "make a directory (deprecated) [RW]"
-.It XPWD Ta "print the current working directory (deprecated)"
-.It XRMD Ta "remove a directory (deprecated) [RW]"
-.El
-.Pp
-The following non-standard or
-.Ux
-specific commands are supported
-by the
-SITE request.
-.Bl -column Request -offset indent
-.It Sy Request Ta Sy Description
-.It UMASK Ta change umask, e.g. ``SITE UMASK 002''
-.It IDLE Ta set idle-timer, e.g. ``SITE IDLE 60''
-.It CHMOD Ta "change mode of a file [RW], e.g. ``SITE CHMOD 755 filename''"
-.It MD5 Ta "report the files MD5 checksum, e.g. ``SITE MD5 filename''"
-.It HELP Ta give help information
-.El
-.Pp
-Note: SITE requests are disabled in case of anonymous logins.
-.Pp
-The remaining ftp requests specified in Internet RFC 959
-are
-recognized, but not implemented.
-MDTM and SIZE are not specified in RFC 959, but will appear in the
-next updated FTP RFC.
-To avoid possible denial-of-service attacks, SIZE requests against
-files larger than 10240 bytes will be denied if the current transfer
-type is ASCII.
-.Pp
-The ftp server will abort an active file transfer only when the
-ABOR
-command is preceded by a Telnet "Interrupt Process" (IP)
-signal and a Telnet "Synch" signal in the command Telnet stream,
-as described in Internet RFC 959.
-If a
-STAT
-command is received during a data transfer, preceded by a Telnet IP
-and Synch, transfer status will be returned.
-.Pp
-The
-.Nm
-utility interprets file names according to the
-.Dq globbing
-conventions used by
-.Xr csh 1 .
-This allows users to utilize the metacharacters
-.Dq Li \&*?[]{}~ .
-.Pp
-The
-.Nm
-utility authenticates users according to six rules.
-.Bl -enum -offset indent
-.It
-The login name must be in the password data base
-and not have a null password.
-In this case a password must be provided by the client before any
-file operations may be performed.
-.It
-The login name must not appear in the file
-.Pa /etc/ftpusers .
-.It
-The login name must not be a member of a group specified in the file
-.Pa /etc/ftpusers .
-Entries in this file interpreted as group names are prefixed by an "at"
-.Ql \&@
-sign.
-.It
-The user must have a standard shell returned by
-.Xr getusershell 3 .
-.It
-If the user name appears in the file
-.Pa /etc/ftpchroot ,
-or the user is a member of a group with a group entry in this file,
-i.e., one prefixed with
-.Ql \&@ ,
-the session's root will be changed to the directory specified
-in this file or to the user's login directory by
-.Xr chroot 2
-as for an
-.Dq anonymous
-or
-.Dq ftp
-account (see next item).
-See
-.Xr ftpchroot 5
-for a detailed description of the format of this file.
-This facility may also be triggered by enabling the boolean "ftp-chroot"
-capability in
-.Xr login.conf 5 .
-However, the user must still supply a password.
-This feature is intended as a compromise between a fully anonymous
-account and a fully privileged account.
-The account should also be set up as for an anonymous account.
-.It
-If the user name is
-.Dq anonymous
-or
-.Dq ftp ,
-an
-anonymous ftp account must be present in the password
-file (user
-.Dq ftp ) .
-In this case the user is allowed
-to log in by specifying any password (by convention an email address for
-the user should be used as the password).
-When the
-.Fl S
-option is set, all transfers are logged as well.
-.El
-.Pp
-In the last case,
-.Nm
-takes special measures to restrict the client's access privileges.
-The server performs a
-.Xr chroot 2
-to the home directory of the
-.Dq ftp
-user.
-As a special case if the
-.Dq ftp
-user's home directory pathname contains the
-.Pa /./
-separator,
-.Nm
-uses its left-hand side as the name of the directory to do
-.Xr chroot 2
-to, and its right-hand side to change the current directory to afterwards.
-A typical example for this case would be
-.Pa /var/spool/ftp/./pub .
-In order that system security is not breached, it is recommended
-that the
-.Dq ftp
-subtree be constructed with care, following these rules:
-.Bl -tag -width "~ftp/pub" -offset indent
-.It Pa ~ftp
-Make the home directory owned by
-.Dq root
-and unwritable by anyone.
-.It Pa ~ftp/etc
-Make this directory owned by
-.Dq root
-and unwritable by anyone (mode 555).
-The files pwd.db (see
-.Xr passwd 5 )
-and
-.Xr group 5
-must be present for the
-.Xr ls 1
-command to be able to produce owner names rather than numbers.
-The password field in
-.Xr passwd 5
-is not used, and should not contain real passwords.
-The file
-.Pa ftpmotd ,
-if present, will be printed after a successful login.
-These files should be mode 444.
-.It Pa ~ftp/pub
-This directory and the subdirectories beneath it should be owned
-by the users and groups responsible for placing files in them,
-and be writable only by them (mode 755 or 775).
-They should
-.Em not
-be owned or writable by
-.Dq ftp
-or its group, otherwise guest users
-can fill the drive with unwanted files.
-.El
-.Pp
-If the system has multiple IP addresses,
-.Nm
-supports the idea of virtual hosts, which provides the ability to
-define multiple anonymous ftp areas, each one allocated to a different
-internet address.
-The file
-.Pa /etc/ftphosts
-contains information pertaining to each of the virtual hosts.
-Each host is defined on its own line which contains a number of
-fields separated by whitespace:
-.Bl -tag -offset indent -width hostname
-.It hostname
-Contains the hostname or IP address of the virtual host.
-.It user
-Contains a user record in the system password file.
-As with normal anonymous ftp, this user's access uid, gid and group
-memberships determine file access to the anonymous ftp area.
-The anonymous ftp area (to which any user is chrooted on login)
-is determined by the home directory defined for the account.
-User id and group for any ftp account may be the same as for the
-standard ftp user.
-.It statfile
-File to which all file transfers are logged, which
-defaults to
-.Pa /var/log/ftpd .
-.It welcome
-This file is the welcome message displayed before the server ready
-prompt.
-It defaults to
-.Pa /etc/ftpwelcome .
-.It motd
-This file is displayed after the user logs in.
-It defaults to
-.Pa /etc/ftpmotd .
-.El
-.Pp
-Lines beginning with a '#' are ignored and can be used to include
-comments.
-.Pp
-Defining a virtual host for the primary IP address or hostname
-changes the default for ftp logins to that address.
-The 'user', 'statfile', 'welcome' and 'motd' fields may be left
-blank, or a single hyphen '-' used to indicate that the default
-value is to be used.
-.Pp
-As with any anonymous login configuration, due care must be given
-to setup and maintenance to guard against security related problems.
-.Pp
-The
-.Nm
-utility has internal support for handling remote requests to list
-files, and will not execute
-.Pa /bin/ls
-in either a chrooted or non-chrooted environment.
-The
-.Pa ~/bin/ls
-executable need not be placed into the chrooted tree, nor need the
-.Pa ~/bin
-directory exist.
-.Sh FILES
-.Bl -tag -width ".Pa /var/run/ftpd.pid" -compact
-.It Pa /etc/ftpusers
-List of unwelcome/restricted users.
-.It Pa /etc/ftpchroot
-List of normal users who should be chroot'd.
-.It Pa /etc/ftphosts
-Virtual hosting configuration file.
-.It Pa /etc/ftpwelcome
-Welcome notice.
-.It Pa /etc/ftpmotd
-Welcome notice after login.
-.It Pa /var/run/ftpd.pid
-Default pid file for daemon mode.
-.It Pa /var/run/nologin
-Displayed and access refused.
-.It Pa /var/log/ftpd
-Log file for anonymous transfers.
-.It Pa /var/log/xferlog
-Default place for session logs.
-.It Pa /var/spool/ftp
-Recommended directory for the FTP root directory
-(the home directory of the ftp user).
-.El
-.Sh SEE ALSO
-.Xr ftp 1 ,
-.Xr umask 2 ,
-.Xr getusershell 3 ,
-.Xr ftpchroot 5 ,
-.Xr login.conf 5 ,
-.Xr inetd 8 ,
-.Xr syslogd 8
-.Sh HISTORY
-The
-.Nm
-utility appeared in
-.Bx 4.2 .
-IPv6 support was added in WIDE Hydrangea IPv6 stack kit.
-.Sh BUGS
-The server must run as the super-user
-to create sockets with privileged port numbers.
-It maintains
-an effective user id of the logged in user, reverting to
-the super-user only when binding addresses to sockets.
-The
-possible security holes have been extensively
-scrutinized, but are possibly incomplete.
diff --git a/libexec/ftpd/ftpd.c b/libexec/ftpd/ftpd.c
deleted file mode 100644
index 751d77b218b7..000000000000
--- a/libexec/ftpd/ftpd.c
+++ /dev/null
@@ -1,3446 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1985, 1988, 1990, 1992, 1993, 1994
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * FTP server.
- */
-#include <sys/param.h>
-#include <sys/ioctl.h>
-#include <sys/mman.h>
-#include <sys/socket.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include <sys/wait.h>
-
-#include <netinet/in.h>
-#include <netinet/in_systm.h>
-#include <netinet/ip.h>
-#include <netinet/tcp.h>
-
-#define	FTP_NAMES
-#include <arpa/ftp.h>
-#include <arpa/inet.h>
-#include <arpa/telnet.h>
-
-#include <ctype.h>
-#include <dirent.h>
-#include <err.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <glob.h>
-#include <limits.h>
-#include <netdb.h>
-#include <pwd.h>
-#include <grp.h>
-#include <signal.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <syslog.h>
-#include <time.h>
-#include <unistd.h>
-#include <libutil.h>
-#ifdef	LOGIN_CAP
-#include <login_cap.h>
-#endif
-
-#ifdef USE_PAM
-#include <security/pam_appl.h>
-#endif
-
-#include "blacklist_client.h"
-#include "pathnames.h"
-#include "extern.h"
-
-#include <stdarg.h>
-
-static char version[] = "Version 6.00LS";
-#undef main
-
-union sockunion ctrl_addr;
-union sockunion data_source;
-union sockunion data_dest;
-union sockunion his_addr;
-union sockunion pasv_addr;
-
-int	daemon_mode;
-int	data;
-int	dataport;
-int	hostinfo = 1;	/* print host-specific info in messages */
-int	logged_in;
-struct	passwd *pw;
-char	*homedir;
-int	ftpdebug;
-int	timeout = 900;    /* timeout after 15 minutes of inactivity */
-int	maxtimeout = 7200;/* don't allow idle time to be set beyond 2 hours */
-int	logging;
-int	restricted_data_ports = 1;
-int	paranoid = 1;	  /* be extra careful about security */
-int	anon_only = 0;    /* Only anonymous ftp allowed */
-int	noanon = 0;       /* disable anonymous ftp */
-int	assumeutf8 = 0;   /* Assume that server file names are in UTF-8 */
-int	guest;
-int	dochroot;
-char	*chrootdir;
-int	dowtmp = 1;
-int	stats;
-int	statfd = -1;
-int	type;
-int	form;
-int	stru;			/* avoid C keyword */
-int	mode;
-int	usedefault = 1;		/* for data transfers */
-int	pdata = -1;		/* for passive mode */
-int	readonly = 0;		/* Server is in readonly mode.	*/
-int	noepsv = 0;		/* EPSV command is disabled.	*/
-int	noretr = 0;		/* RETR command is disabled.	*/
-int	noguestretr = 0;	/* RETR command is disabled for anon users. */
-int	noguestmkd = 0;		/* MKD command is disabled for anon users. */
-int	noguestmod = 1;		/* anon users may not modify existing files. */
-int	use_blacklist = 0;
-
-off_t	file_size;
-off_t	byte_count;
-#if !defined(CMASK) || CMASK == 0
-#undef CMASK
-#define CMASK 027
-#endif
-int	defumask = CMASK;		/* default umask value */
-char	tmpline[7];
-char	*hostname;
-int	epsvall = 0;
-
-#ifdef VIRTUAL_HOSTING
-char	*ftpuser;
-
-static struct ftphost {
-	struct ftphost	*next;
-	struct addrinfo *hostinfo;
-	char		*hostname;
-	char		*anonuser;
-	char		*statfile;
-	char		*welcome;
-	char		*loginmsg;
-} *thishost, *firsthost;
-
-#endif
-char	remotehost[NI_MAXHOST];
-char	*ident = NULL;
-
-static char	wtmpid[20];
-
-#ifdef USE_PAM
-static int	auth_pam(struct passwd**, const char*);
-pam_handle_t	*pamh = NULL;
-#endif
-
-char	*pid_file = NULL; /* means default location to pidfile(3) */
-
-/*
- * Limit number of pathnames that glob can return.
- * A limit of 0 indicates the number of pathnames is unlimited.
- */
-#define MAXGLOBARGS	16384
-#
-
-/*
- * Timeout intervals for retrying connections
- * to hosts that don't accept PORT cmds.  This
- * is a kludge, but given the problems with TCP...
- */
-#define	SWAITMAX	90	/* wait at most 90 seconds */
-#define	SWAITINT	5	/* interval between retries */
-
-int	swaitmax = SWAITMAX;
-int	swaitint = SWAITINT;
-
-#ifdef SETPROCTITLE
-char	proctitle[LINE_MAX];	/* initial part of title */
-#endif /* SETPROCTITLE */
-
-#define LOGCMD(cmd, file)		logcmd((cmd), (file), NULL, -1)
-#define LOGCMD2(cmd, file1, file2)	logcmd((cmd), (file1), (file2), -1)
-#define LOGBYTES(cmd, file, cnt)	logcmd((cmd), (file), NULL, (cnt))
-
-static	volatile sig_atomic_t recvurg;
-static	int transflag;		/* NB: for debugging only */
-
-#define STARTXFER	flagxfer(1)
-#define ENDXFER		flagxfer(0)
-
-#define START_UNSAFE	maskurg(1)
-#define END_UNSAFE	maskurg(0)
-
-/* It's OK to put an `else' clause after this macro. */
-#define CHECKOOB(action)						\
-	if (recvurg) {							\
-		recvurg = 0;						\
-		if (myoob()) {						\
-			ENDXFER;					\
-			action;						\
-		}							\
-	}
-
-#ifdef VIRTUAL_HOSTING
-static void	 inithosts(int);
-static void	 selecthost(union sockunion *);
-#endif
-static void	 ack(char *);
-static void	 sigurg(int);
-static void	 maskurg(int);
-static void	 flagxfer(int);
-static int	 myoob(void);
-static int	 checkuser(char *, char *, int, char **, int *);
-static FILE	*dataconn(char *, off_t, char *);
-static void	 dolog(struct sockaddr *);
-static void	 end_login(void);
-static FILE	*getdatasock(char *);
-static int	 guniquefd(char *, char **);
-static void	 lostconn(int);
-static void	 sigquit(int);
-static int	 receive_data(FILE *, FILE *);
-static int	 send_data(FILE *, FILE *, size_t, off_t, int);
-static struct passwd *
-		 sgetpwnam(char *);
-static char	*sgetsave(char *);
-static void	 reapchild(int);
-static void	 appendf(char **, char *, ...) __printflike(2, 3);
-static void	 logcmd(char *, char *, char *, off_t);
-static void      logxfer(char *, off_t, time_t);
-static char	*doublequote(char *);
-static int	*socksetup(int, char *, const char *);
-
-int
-main(int argc, char *argv[], char **envp)
-{
-	socklen_t addrlen;
-	int ch, on = 1, tos, s = STDIN_FILENO;
-	char *cp, line[LINE_MAX];
-	FILE *fd;
-	char	*bindname = NULL;
-	const char *bindport = "ftp";
-	int	family = AF_UNSPEC;
-	struct sigaction sa;
-
-	tzset();		/* in case no timezone database in ~ftp */
-	sigemptyset(&sa.sa_mask);
-	sa.sa_flags = SA_RESTART;
-
-	/*
-	 * Prevent diagnostic messages from appearing on stderr.
-	 * We run as a daemon or from inetd; in both cases, there's
-	 * more reason in logging to syslog.
-	 */
-	(void) freopen(_PATH_DEVNULL, "w", stderr);
-	opterr = 0;
-
-	/*
-	 * LOG_NDELAY sets up the logging connection immediately,
-	 * necessary for anonymous ftp's that chroot and can't do it later.
-	 */
-	openlog("ftpd", LOG_PID | LOG_NDELAY, LOG_FTP);
-
-	while ((ch = getopt(argc, argv,
-	                    "468a:ABdDEhlmMnoOp:P:rRSt:T:u:UvW")) != -1) {
-		switch (ch) {
-		case '4':
-			family = (family == AF_INET6) ? AF_UNSPEC : AF_INET;
-			break;
-
-		case '6':
-			family = (family == AF_INET) ? AF_UNSPEC : AF_INET6;
-			break;
-
-		case '8':
-			assumeutf8 = 1;
-			break;
-
-		case 'a':
-			bindname = optarg;
-			break;
-
-		case 'A':
-			anon_only = 1;
-			break;
-
-		case 'B':
-#ifdef USE_BLACKLIST
-			use_blacklist = 1;
-#else
-			syslog(LOG_WARNING, "not compiled with USE_BLACKLIST support");
-#endif
-			break;
-
-		case 'd':
-			ftpdebug++;
-			break;
-
-		case 'D':
-			daemon_mode++;
-			break;
-
-		case 'E':
-			noepsv = 1;
-			break;
-
-		case 'h':
-			hostinfo = 0;
-			break;
-
-		case 'l':
-			logging++;	/* > 1 == extra logging */
-			break;
-
-		case 'm':
-			noguestmod = 0;
-			break;
-
-		case 'M':
-			noguestmkd = 1;
-			break;
-
-		case 'n':
-			noanon = 1;
-			break;
-
-		case 'o':
-			noretr = 1;
-			break;
-
-		case 'O':
-			noguestretr = 1;
-			break;
-
-		case 'p':
-			pid_file = optarg;
-			break;
-
-		case 'P':
-			bindport = optarg;
-			break;
-
-		case 'r':
-			readonly = 1;
-			break;
-
-		case 'R':
-			paranoid = 0;
-			break;
-
-		case 'S':
-			stats++;
-			break;
-
-		case 't':
-			timeout = atoi(optarg);
-			if (maxtimeout < timeout)
-				maxtimeout = timeout;
-			break;
-
-		case 'T':
-			maxtimeout = atoi(optarg);
-			if (timeout > maxtimeout)
-				timeout = maxtimeout;
-			break;
-
-		case 'u':
-		    {
-			long val = 0;
-
-			val = strtol(optarg, &optarg, 8);
-			if (*optarg != '\0' || val < 0)
-				syslog(LOG_WARNING, "bad value for -u");
-			else
-				defumask = val;
-			break;
-		    }
-		case 'U':
-			restricted_data_ports = 0;
-			break;
-
-		case 'v':
-			ftpdebug++;
-			break;
-
-		case 'W':
-			dowtmp = 0;
-			break;
-
-		default:
-			syslog(LOG_WARNING, "unknown flag -%c ignored", optopt);
-			break;
-		}
-	}
-
-	if (noanon && anon_only) {
-		syslog(LOG_ERR, "-n and -A are mutually exclusive");
-		exit(1);
-	}
-
-	/* handle filesize limit gracefully */
-	sa.sa_handler = SIG_IGN;
-	(void)sigaction(SIGXFSZ, &sa, NULL);
-
-	if (daemon_mode) {
-		int *ctl_sock, fd, maxfd = -1, nfds, i;
-		fd_set defreadfds, readfds;
-		pid_t pid;
-		struct pidfh *pfh;
-
-		if ((pfh = pidfile_open(pid_file, 0600, &pid)) == NULL) {
-			if (errno == EEXIST) {
-				syslog(LOG_ERR, "%s already running, pid %d",
-				       getprogname(), (int)pid);
-				exit(1);
-			}
-			syslog(LOG_WARNING, "pidfile_open: %m");
-		}
-
-		/*
-		 * Detach from parent.
-		 */
-		if (daemon(1, 1) < 0) {
-			syslog(LOG_ERR, "failed to become a daemon");
-			exit(1);
-		}
-
-		if (pfh != NULL && pidfile_write(pfh) == -1)
-			syslog(LOG_WARNING, "pidfile_write: %m");
-
-		sa.sa_handler = reapchild;
-		(void)sigaction(SIGCHLD, &sa, NULL);
-
-#ifdef VIRTUAL_HOSTING
-		inithosts(family);
-#endif
-
-		/*
-		 * Open a socket, bind it to the FTP port, and start
-		 * listening.
-		 */
-		ctl_sock = socksetup(family, bindname, bindport);
-		if (ctl_sock == NULL)
-			exit(1);
-
-		FD_ZERO(&defreadfds);
-		for (i = 1; i <= *ctl_sock; i++) {
-			FD_SET(ctl_sock[i], &defreadfds);
-			if (listen(ctl_sock[i], 32) < 0) {
-				syslog(LOG_ERR, "control listen: %m");
-				exit(1);
-			}
-			if (maxfd < ctl_sock[i])
-				maxfd = ctl_sock[i];
-		}
-
-		/*
-		 * Loop forever accepting connection requests and forking off
-		 * children to handle them.
-		 */
-		while (1) {
-			FD_COPY(&defreadfds, &readfds);
-			nfds = select(maxfd + 1, &readfds, NULL, NULL, 0);
-			if (nfds <= 0) {
-				if (nfds < 0 && errno != EINTR)
-					syslog(LOG_WARNING, "select: %m");
-				continue;
-			}
-
-			pid = -1;
-                        for (i = 1; i <= *ctl_sock; i++)
-				if (FD_ISSET(ctl_sock[i], &readfds)) {
-					addrlen = sizeof(his_addr);
-					fd = accept(ctl_sock[i],
-					    (struct sockaddr *)&his_addr,
-					    &addrlen);
-					if (fd == -1) {
-						syslog(LOG_WARNING,
-						       "accept: %m");
-						continue;
-					}
-					switch (pid = fork()) {
-					case 0:
-						/* child */
-						(void) dup2(fd, s);
-						(void) dup2(fd, STDOUT_FILENO);
-						(void) close(fd);
-						for (i = 1; i <= *ctl_sock; i++)
-							close(ctl_sock[i]);
-						if (pfh != NULL)
-							pidfile_close(pfh);
-						goto gotchild;
-					case -1:
-						syslog(LOG_WARNING, "fork: %m");
-						/* FALLTHROUGH */
-					default:
-						close(fd);
-					}
-				}
-		}
-	} else {
-		addrlen = sizeof(his_addr);
-		if (getpeername(s, (struct sockaddr *)&his_addr, &addrlen) < 0) {
-			syslog(LOG_ERR, "getpeername (%s): %m",argv[0]);
-			exit(1);
-		}
-
-#ifdef VIRTUAL_HOSTING
-		if (his_addr.su_family == AF_INET6 &&
-		    IN6_IS_ADDR_V4MAPPED(&his_addr.su_sin6.sin6_addr))
-			family = AF_INET;
-		else
-			family = his_addr.su_family;
-		inithosts(family);
-#endif
-	}
-
-gotchild:
-	sa.sa_handler = SIG_DFL;
-	(void)sigaction(SIGCHLD, &sa, NULL);
-
-	sa.sa_handler = sigurg;
-	sa.sa_flags = 0;		/* don't restart syscalls for SIGURG */
-	(void)sigaction(SIGURG, &sa, NULL);
-
-	sigfillset(&sa.sa_mask);	/* block all signals in handler */
-	sa.sa_flags = SA_RESTART;
-	sa.sa_handler = sigquit;
-	(void)sigaction(SIGHUP, &sa, NULL);
-	(void)sigaction(SIGINT, &sa, NULL);
-	(void)sigaction(SIGQUIT, &sa, NULL);
-	(void)sigaction(SIGTERM, &sa, NULL);
-
-	sa.sa_handler = lostconn;
-	(void)sigaction(SIGPIPE, &sa, NULL);
-
-	addrlen = sizeof(ctrl_addr);
-	if (getsockname(s, (struct sockaddr *)&ctrl_addr, &addrlen) < 0) {
-		syslog(LOG_ERR, "getsockname (%s): %m",argv[0]);
-		exit(1);
-	}
-	dataport = ntohs(ctrl_addr.su_port) - 1; /* as per RFC 959 */
-#ifdef VIRTUAL_HOSTING
-	/* select our identity from virtual host table */
-	selecthost(&ctrl_addr);
-#endif
-#ifdef IP_TOS
-	if (ctrl_addr.su_family == AF_INET)
-      {
-	tos = IPTOS_LOWDELAY;
-	if (setsockopt(s, IPPROTO_IP, IP_TOS, &tos, sizeof(int)) < 0)
-		syslog(LOG_WARNING, "control setsockopt (IP_TOS): %m");
-      }
-#endif
-	/*
-	 * Disable Nagle on the control channel so that we don't have to wait
-	 * for peer's ACK before issuing our next reply.
-	 */
-	if (setsockopt(s, IPPROTO_TCP, TCP_NODELAY, &on, sizeof(on)) < 0)
-		syslog(LOG_WARNING, "control setsockopt (TCP_NODELAY): %m");
-
-	data_source.su_port = htons(ntohs(ctrl_addr.su_port) - 1);
-
-	(void)snprintf(wtmpid, sizeof(wtmpid), "%xftpd", getpid());
-
-	/* Try to handle urgent data inline */
-#ifdef SO_OOBINLINE
-	if (setsockopt(s, SOL_SOCKET, SO_OOBINLINE, &on, sizeof(on)) < 0)
-		syslog(LOG_WARNING, "control setsockopt (SO_OOBINLINE): %m");
-#endif
-
-#ifdef	F_SETOWN
-	if (fcntl(s, F_SETOWN, getpid()) == -1)
-		syslog(LOG_ERR, "fcntl F_SETOWN: %m");
-#endif
-	dolog((struct sockaddr *)&his_addr);
-	/*
-	 * Set up default state
-	 */
-	data = -1;
-	type = TYPE_A;
-	form = FORM_N;
-	stru = STRU_F;
-	mode = MODE_S;
-	tmpline[0] = '\0';
-
-	/* If logins are disabled, print out the message. */
-	if ((fd = fopen(_PATH_NOLOGIN,"r")) != NULL) {
-		while (fgets(line, sizeof(line), fd) != NULL) {
-			if ((cp = strchr(line, '\n')) != NULL)
-				*cp = '\0';
-			lreply(530, "%s", line);
-		}
-		(void) fflush(stdout);
-		(void) fclose(fd);
-		reply(530, "System not available.");
-		exit(0);
-	}
-#ifdef VIRTUAL_HOSTING
-	fd = fopen(thishost->welcome, "r");
-#else
-	fd = fopen(_PATH_FTPWELCOME, "r");
-#endif
-	if (fd != NULL) {
-		while (fgets(line, sizeof(line), fd) != NULL) {
-			if ((cp = strchr(line, '\n')) != NULL)
-				*cp = '\0';
-			lreply(220, "%s", line);
-		}
-		(void) fflush(stdout);
-		(void) fclose(fd);
-		/* reply(220,) must follow */
-	}
-#ifndef VIRTUAL_HOSTING
-	if ((hostname = malloc(MAXHOSTNAMELEN)) == NULL)
-		fatalerror("Ran out of memory.");
-	if (gethostname(hostname, MAXHOSTNAMELEN - 1) < 0)
-		hostname[0] = '\0';
-	hostname[MAXHOSTNAMELEN - 1] = '\0';
-#endif
-	if (hostinfo)
-		reply(220, "%s FTP server (%s) ready.", hostname, version);
-	else
-		reply(220, "FTP server ready.");
-	BLACKLIST_INIT();
-	for (;;)
-		(void) yyparse();
-	/* NOTREACHED */
-}
-
-static void
-lostconn(int signo)
-{
-
-	if (ftpdebug)
-		syslog(LOG_DEBUG, "lost connection");
-	dologout(1);
-}
-
-static void
-sigquit(int signo)
-{
-
-	syslog(LOG_ERR, "got signal %d", signo);
-	dologout(1);
-}
-
-#ifdef VIRTUAL_HOSTING
-/*
- * read in virtual host tables (if they exist)
- */
-
-static void
-inithosts(int family)
-{
-	int insert;
-	size_t len;
-	FILE *fp;
-	char *cp, *mp, *line;
-	char *hostname;
-	char *vhost, *anonuser, *statfile, *welcome, *loginmsg;
-	struct ftphost *hrp, *lhrp;
-	struct addrinfo hints, *res, *ai;
-
-	/*
-	 * Fill in the default host information
-	 */
-	if ((hostname = malloc(MAXHOSTNAMELEN)) == NULL)
-		fatalerror("Ran out of memory.");
-	if (gethostname(hostname, MAXHOSTNAMELEN - 1) < 0)
-		hostname[0] = '\0';
-	hostname[MAXHOSTNAMELEN - 1] = '\0';
-	if ((hrp = malloc(sizeof(struct ftphost))) == NULL)
-		fatalerror("Ran out of memory.");
-	hrp->hostname = hostname;
-	hrp->hostinfo = NULL;
-
-	memset(&hints, 0, sizeof(hints));
-	hints.ai_flags = AI_PASSIVE;
-	hints.ai_family = family;
-	hints.ai_socktype = SOCK_STREAM;
-	if (getaddrinfo(hrp->hostname, NULL, &hints, &res) == 0)
-		hrp->hostinfo = res;
-	hrp->statfile = _PATH_FTPDSTATFILE;
-	hrp->welcome  = _PATH_FTPWELCOME;
-	hrp->loginmsg = _PATH_FTPLOGINMESG;
-	hrp->anonuser = "ftp";
-	hrp->next = NULL;
-	thishost = firsthost = lhrp = hrp;
-	if ((fp = fopen(_PATH_FTPHOSTS, "r")) != NULL) {
-		int addrsize, gothost;
-		void *addr;
-		struct hostent *hp;
-
-		while ((line = fgetln(fp, &len)) != NULL) {
-			int	i, hp_error;
-
-			/* skip comments */
-			if (line[0] == '#')
-				continue;
-			if (line[len - 1] == '\n') {
-				line[len - 1] = '\0';
-				mp = NULL;
-			} else {
-				if ((mp = malloc(len + 1)) == NULL)
-					fatalerror("Ran out of memory.");
-				memcpy(mp, line, len);
-				mp[len] = '\0';
-				line = mp;
-			}
-			cp = strtok(line, " \t");
-			/* skip empty lines */
-			if (cp == NULL)
-				goto nextline;
-			vhost = cp;
-
-			/* set defaults */
-			anonuser = "ftp";
-			statfile = _PATH_FTPDSTATFILE;
-			welcome  = _PATH_FTPWELCOME;
-			loginmsg = _PATH_FTPLOGINMESG;
-
-			/*
-			 * Preparse the line so we can use its info
-			 * for all the addresses associated with
-			 * the virtual host name.
-			 * Field 0, the virtual host name, is special:
-			 * it's already parsed off and will be strdup'ed
-			 * later, after we know its canonical form.
-			 */
-			for (i = 1; i < 5 && (cp = strtok(NULL, " \t")); i++)
-				if (*cp != '-' && (cp = strdup(cp)))
-					switch (i) {
-					case 1:	/* anon user permissions */
-						anonuser = cp;
-						break;
-					case 2: /* statistics file */
-						statfile = cp;
-						break;
-					case 3: /* welcome message */
-						welcome  = cp;
-						break;
-					case 4: /* login message */
-						loginmsg = cp;
-						break;
-					default: /* programming error */
-						abort();
-						/* NOTREACHED */
-					}
-
-			hints.ai_flags = AI_PASSIVE;
-			hints.ai_family = family;
-			hints.ai_socktype = SOCK_STREAM;
-			if (getaddrinfo(vhost, NULL, &hints, &res) != 0)
-				goto nextline;
-			for (ai = res; ai != NULL && ai->ai_addr != NULL;
-			     ai = ai->ai_next) {
-
-			gothost = 0;
-			for (hrp = firsthost; hrp != NULL; hrp = hrp->next) {
-				struct addrinfo *hi;
-
-				for (hi = hrp->hostinfo; hi != NULL;
-				     hi = hi->ai_next)
-					if (hi->ai_addrlen == ai->ai_addrlen &&
-					    memcmp(hi->ai_addr,
-						   ai->ai_addr,
-						   ai->ai_addr->sa_len) == 0) {
-						gothost++;
-						break;
-					}
-				if (gothost)
-					break;
-			}
-			if (hrp == NULL) {
-				if ((hrp = malloc(sizeof(struct ftphost))) == NULL)
-					goto nextline;
-				hrp->hostname = NULL;
-				insert = 1;
-			} else {
-				if (hrp->hostinfo && hrp->hostinfo != res)
-					freeaddrinfo(hrp->hostinfo);
-				insert = 0; /* host already in the chain */
-			}
-			hrp->hostinfo = res;
-
-			/*
-			 * determine hostname to use.
-			 * force defined name if there is a valid alias
-			 * otherwise fallback to primary hostname
-			 */
-			/* XXX: getaddrinfo() can't do alias check */
-			switch(hrp->hostinfo->ai_family) {
-			case AF_INET:
-				addr = &((struct sockaddr_in *)hrp->hostinfo->ai_addr)->sin_addr;
-				addrsize = sizeof(struct in_addr);
-				break;
-			case AF_INET6:
-				addr = &((struct sockaddr_in6 *)hrp->hostinfo->ai_addr)->sin6_addr;
-				addrsize = sizeof(struct in6_addr);
-				break;
-			default:
-				/* should not reach here */
-				freeaddrinfo(hrp->hostinfo);
-				if (insert)
-					free(hrp); /*not in chain, can free*/
-				else
-					hrp->hostinfo = NULL; /*mark as blank*/
-				goto nextline;
-				/* NOTREACHED */
-			}
-			if ((hp = getipnodebyaddr(addr, addrsize,
-						  hrp->hostinfo->ai_family,
-						  &hp_error)) != NULL) {
-				if (strcmp(vhost, hp->h_name) != 0) {
-					if (hp->h_aliases == NULL)
-						vhost = hp->h_name;
-					else {
-						i = 0;
-						while (hp->h_aliases[i] &&
-						       strcmp(vhost, hp->h_aliases[i]) != 0)
-							++i;
-						if (hp->h_aliases[i] == NULL)
-							vhost = hp->h_name;
-					}
-				}
-			}
-			if (hrp->hostname &&
-			    strcmp(hrp->hostname, vhost) != 0) {
-				free(hrp->hostname);
-				hrp->hostname = NULL;
-			}
-			if (hrp->hostname == NULL &&
-			    (hrp->hostname = strdup(vhost)) == NULL) {
-				freeaddrinfo(hrp->hostinfo);
-				hrp->hostinfo = NULL; /* mark as blank */
-				if (hp)
-					freehostent(hp);
-				goto nextline;
-			}
-			hrp->anonuser = anonuser;
-			hrp->statfile = statfile;
-			hrp->welcome  = welcome;
-			hrp->loginmsg = loginmsg;
-			if (insert) {
-				hrp->next  = NULL;
-				lhrp->next = hrp;
-				lhrp = hrp;
-			}
-			if (hp)
-				freehostent(hp);
-		      }
-nextline:
-			if (mp)
-				free(mp);
-		}
-		(void) fclose(fp);
-	}
-}
-
-static void
-selecthost(union sockunion *su)
-{
-	struct ftphost	*hrp;
-	u_int16_t port;
-#ifdef INET6
-	struct in6_addr *mapped_in6 = NULL;
-#endif
-	struct addrinfo *hi;
-
-#ifdef INET6
-	/*
-	 * XXX IPv4 mapped IPv6 addr consideraton,
-	 * specified in rfc2373.
-	 */
-	if (su->su_family == AF_INET6 &&
-	    IN6_IS_ADDR_V4MAPPED(&su->su_sin6.sin6_addr))
-		mapped_in6 = &su->su_sin6.sin6_addr;
-#endif
-
-	hrp = thishost = firsthost;	/* default */
-	port = su->su_port;
-	su->su_port = 0;
-	while (hrp != NULL) {
-	    for (hi = hrp->hostinfo; hi != NULL; hi = hi->ai_next) {
-		if (memcmp(su, hi->ai_addr, hi->ai_addrlen) == 0) {
-			thishost = hrp;
-			goto found;
-		}
-#ifdef INET6
-		/* XXX IPv4 mapped IPv6 addr consideraton */
-		if (hi->ai_addr->sa_family == AF_INET && mapped_in6 != NULL &&
-		    (memcmp(&mapped_in6->s6_addr[12],
-			    &((struct sockaddr_in *)hi->ai_addr)->sin_addr,
-			    sizeof(struct in_addr)) == 0)) {
-			thishost = hrp;
-			goto found;
-		}
-#endif
-	    }
-	    hrp = hrp->next;
-	}
-found:
-	su->su_port = port;
-	/* setup static variables as appropriate */
-	hostname = thishost->hostname;
-	ftpuser = thishost->anonuser;
-}
-#endif
-
-/*
- * Helper function for sgetpwnam().
- */
-static char *
-sgetsave(char *s)
-{
-	char *new = malloc(strlen(s) + 1);
-
-	if (new == NULL) {
-		reply(421, "Ran out of memory.");
-		dologout(1);
-		/* NOTREACHED */
-	}
-	(void) strcpy(new, s);
-	return (new);
-}
-
-/*
- * Save the result of a getpwnam.  Used for USER command, since
- * the data returned must not be clobbered by any other command
- * (e.g., globbing).
- * NB: The data returned by sgetpwnam() will remain valid until
- * the next call to this function.  Its difference from getpwnam()
- * is that sgetpwnam() is known to be called from ftpd code only.
- */
-static struct passwd *
-sgetpwnam(char *name)
-{
-	static struct passwd save;
-	struct passwd *p;
-
-	if ((p = getpwnam(name)) == NULL)
-		return (p);
-	if (save.pw_name) {
-		free(save.pw_name);
-		free(save.pw_passwd);
-		free(save.pw_class);
-		free(save.pw_gecos);
-		free(save.pw_dir);
-		free(save.pw_shell);
-	}
-	save = *p;
-	save.pw_name = sgetsave(p->pw_name);
-	save.pw_passwd = sgetsave(p->pw_passwd);
-	save.pw_class = sgetsave(p->pw_class);
-	save.pw_gecos = sgetsave(p->pw_gecos);
-	save.pw_dir = sgetsave(p->pw_dir);
-	save.pw_shell = sgetsave(p->pw_shell);
-	return (&save);
-}
-
-static int login_attempts;	/* number of failed login attempts */
-static int askpasswd;		/* had user command, ask for passwd */
-static char curname[MAXLOGNAME];	/* current USER name */
-
-/*
- * USER command.
- * Sets global passwd pointer pw if named account exists and is acceptable;
- * sets askpasswd if a PASS command is expected.  If logged in previously,
- * need to reset state.  If name is "ftp" or "anonymous", the name is not in
- * _PATH_FTPUSERS, and ftp account exists, set guest and pw, then just return.
- * If account doesn't exist, ask for passwd anyway.  Otherwise, check user
- * requesting login privileges.  Disallow anyone who does not have a standard
- * shell as returned by getusershell().  Disallow anyone mentioned in the file
- * _PATH_FTPUSERS to allow people such as root and uucp to be avoided.
- */
-void
-user(char *name)
-{
-	int ecode;
-	char *cp, *shell;
-
-	if (logged_in) {
-		if (guest) {
-			reply(530, "Can't change user from guest login.");
-			return;
-		} else if (dochroot) {
-			reply(530, "Can't change user from chroot user.");
-			return;
-		}
-		end_login();
-	}
-
-	guest = 0;
-#ifdef VIRTUAL_HOSTING
-	pw = sgetpwnam(thishost->anonuser);
-#else
-	pw = sgetpwnam("ftp");
-#endif
-	if (!noanon &&
-	    (strcmp(name, "ftp") == 0 || strcmp(name, "anonymous") == 0)) {
-		if (checkuser(_PATH_FTPUSERS, "ftp", 0, NULL, &ecode) ||
-		    (ecode != 0 && ecode != ENOENT))
-			reply(530, "User %s access denied.", name);
-		else if (checkuser(_PATH_FTPUSERS, "anonymous", 0, NULL, &ecode) ||
-		    (ecode != 0 && ecode != ENOENT))
-			reply(530, "User %s access denied.", name);
-		else if (pw != NULL) {
-			guest = 1;
-			askpasswd = 1;
-			reply(331,
-			"Guest login ok, send your email address as password.");
-		} else
-			reply(530, "User %s unknown.", name);
-		if (!askpasswd && logging)
-			syslog(LOG_NOTICE,
-			    "ANONYMOUS FTP LOGIN REFUSED FROM %s", remotehost);
-		return;
-	}
-	if (anon_only != 0) {
-		reply(530, "Sorry, only anonymous ftp allowed.");
-		return;
-	}
-		
-	if ((pw = sgetpwnam(name))) {
-		if ((shell = pw->pw_shell) == NULL || *shell == 0)
-			shell = _PATH_BSHELL;
-		setusershell();
-		while ((cp = getusershell()) != NULL)
-			if (strcmp(cp, shell) == 0)
-				break;
-		endusershell();
-
-		if (cp == NULL || 
-		    (checkuser(_PATH_FTPUSERS, name, 1, NULL, &ecode) ||
-		    (ecode != 0 && ecode != ENOENT))) {
-			reply(530, "User %s access denied.", name);
-			if (logging)
-				syslog(LOG_NOTICE,
-				    "FTP LOGIN REFUSED FROM %s, %s",
-				    remotehost, name);
-			pw = NULL;
-			return;
-		}
-	}
-	if (logging)
-		strlcpy(curname, name, sizeof(curname));
-
-	reply(331, "Password required for %s.", name);
-	askpasswd = 1;
-	/*
-	 * Delay before reading passwd after first failed
-	 * attempt to slow down passwd-guessing programs.
-	 */
-	if (login_attempts)
-		sleep(login_attempts);
-}
-
-/*
- * Check if a user is in the file "fname",
- * return a pointer to a malloc'd string with the rest
- * of the matching line in "residue" if not NULL.
- */
-static int
-checkuser(char *fname, char *name, int pwset, char **residue, int *ecode)
-{
-	FILE *fd;
-	int found = 0;
-	size_t len;
-	char *line, *mp, *p;
-
-	if (ecode != NULL)
-		*ecode = 0;
-	if ((fd = fopen(fname, "r")) != NULL) {
-		while (!found && (line = fgetln(fd, &len)) != NULL) {
-			/* skip comments */
-			if (line[0] == '#')
-				continue;
-			if (line[len - 1] == '\n') {
-				line[len - 1] = '\0';
-				mp = NULL;
-			} else {
-				if ((mp = malloc(len + 1)) == NULL)
-					fatalerror("Ran out of memory.");
-				memcpy(mp, line, len);
-				mp[len] = '\0';
-				line = mp;
-			}
-			/* avoid possible leading and trailing whitespace */
-			p = strtok(line, " \t");
-			/* skip empty lines */
-			if (p == NULL)
-				goto nextline;
-			/*
-			 * if first chr is '@', check group membership
-			 */
-			if (p[0] == '@') {
-				int i = 0;
-				struct group *grp;
-
-				if (p[1] == '\0') /* single @ matches anyone */
-					found = 1;
-				else {
-					if ((grp = getgrnam(p+1)) == NULL)
-						goto nextline;
-					/*
-					 * Check user's default group
-					 */
-					if (pwset && grp->gr_gid == pw->pw_gid)
-						found = 1;
-					/*
-					 * Check supplementary groups
-					 */
-					while (!found && grp->gr_mem[i])
-						found = strcmp(name,
-							grp->gr_mem[i++])
-							== 0;
-				}
-			}
-			/*
-			 * Otherwise, just check for username match
-			 */
-			else
-				found = strcmp(p, name) == 0;
-			/*
-			 * Save the rest of line to "residue" if matched
-			 */
-			if (found && residue) {
-				if ((p = strtok(NULL, "")) != NULL)
-					p += strspn(p, " \t");
-				if (p && *p) {
-				 	if ((*residue = strdup(p)) == NULL)
-						fatalerror("Ran out of memory.");
-				} else
-					*residue = NULL;
-			}
-nextline:
-			if (mp)
-				free(mp);
-		}
-		(void) fclose(fd);
-	} else if (ecode != NULL)
-		*ecode = errno;
-	return (found);
-}
-
-/*
- * Terminate login as previous user, if any, resetting state;
- * used when USER command is given or login fails.
- */
-static void
-end_login(void)
-{
-#ifdef USE_PAM
-	int e;
-#endif
-
-	(void) seteuid(0);
-#ifdef	LOGIN_CAP
-	setusercontext(NULL, getpwuid(0), 0, LOGIN_SETALL & ~(LOGIN_SETLOGIN |
-		       LOGIN_SETUSER | LOGIN_SETGROUP | LOGIN_SETPATH |
-		       LOGIN_SETENV));
-#endif
-	if (logged_in && dowtmp)
-		ftpd_logwtmp(wtmpid, NULL, NULL);
-	pw = NULL;
-#ifdef USE_PAM
-	if (pamh) {
-		if ((e = pam_setcred(pamh, PAM_DELETE_CRED)) != PAM_SUCCESS)
-			syslog(LOG_ERR, "pam_setcred: %s", pam_strerror(pamh, e));
-		if ((e = pam_close_session(pamh,0)) != PAM_SUCCESS)
-			syslog(LOG_ERR, "pam_close_session: %s", pam_strerror(pamh, e));
-		if ((e = pam_end(pamh, e)) != PAM_SUCCESS)
-			syslog(LOG_ERR, "pam_end: %s", pam_strerror(pamh, e));
-		pamh = NULL;
-	}
-#endif
-	logged_in = 0;
-	guest = 0;
-	dochroot = 0;
-}
-
-#ifdef USE_PAM
-
-/*
- * the following code is stolen from imap-uw PAM authentication module and
- * login.c
- */
-#define COPY_STRING(s) (s ? strdup(s) : NULL)
-
-struct cred_t {
-	const char *uname;		/* user name */
-	const char *pass;		/* password */
-};
-typedef struct cred_t cred_t;
-
-static int
-auth_conv(int num_msg, const struct pam_message **msg,
-	  struct pam_response **resp, void *appdata)
-{
-	int i;
-	cred_t *cred = (cred_t *) appdata;
-	struct pam_response *reply;
-
-	reply = calloc(num_msg, sizeof *reply);
-	if (reply == NULL)
-		return PAM_BUF_ERR;
-
-	for (i = 0; i < num_msg; i++) {
-		switch (msg[i]->msg_style) {
-		case PAM_PROMPT_ECHO_ON:	/* assume want user name */
-			reply[i].resp_retcode = PAM_SUCCESS;
-			reply[i].resp = COPY_STRING(cred->uname);
-			/* PAM frees resp. */
-			break;
-		case PAM_PROMPT_ECHO_OFF:	/* assume want password */
-			reply[i].resp_retcode = PAM_SUCCESS;
-			reply[i].resp = COPY_STRING(cred->pass);
-			/* PAM frees resp. */
-			break;
-		case PAM_TEXT_INFO:
-		case PAM_ERROR_MSG:
-			reply[i].resp_retcode = PAM_SUCCESS;
-			reply[i].resp = NULL;
-			break;
-		default:			/* unknown message style */
-			free(reply);
-			return PAM_CONV_ERR;
-		}
-	}
-
-	*resp = reply;
-	return PAM_SUCCESS;
-}
-
-/*
- * Attempt to authenticate the user using PAM.  Returns 0 if the user is
- * authenticated, or 1 if not authenticated.  If some sort of PAM system
- * error occurs (e.g., the "/etc/pam.conf" file is missing) then this
- * function returns -1.  This can be used as an indication that we should
- * fall back to a different authentication mechanism.
- */
-static int
-auth_pam(struct passwd **ppw, const char *pass)
-{
-	const char *tmpl_user;
-	const void *item;
-	int rval;
-	int e;
-	cred_t auth_cred = { (*ppw)->pw_name, pass };
-	struct pam_conv conv = { &auth_conv, &auth_cred };
-
-	e = pam_start("ftpd", (*ppw)->pw_name, &conv, &pamh);
-	if (e != PAM_SUCCESS) {
-		/*
-		 * In OpenPAM, it's OK to pass NULL to pam_strerror()
-		 * if context creation has failed in the first place.
-		 */
-		syslog(LOG_ERR, "pam_start: %s", pam_strerror(NULL, e));
-		return -1;
-	}
-
-	e = pam_set_item(pamh, PAM_RHOST, remotehost);
-	if (e != PAM_SUCCESS) {
-		syslog(LOG_ERR, "pam_set_item(PAM_RHOST): %s",
-			pam_strerror(pamh, e));
-		if ((e = pam_end(pamh, e)) != PAM_SUCCESS) {
-			syslog(LOG_ERR, "pam_end: %s", pam_strerror(pamh, e));
-		}
-		pamh = NULL;
-		return -1;
-	}
-
-	e = pam_authenticate(pamh, 0);
-	switch (e) {
-	case PAM_SUCCESS:
-		/*
-		 * With PAM we support the concept of a "template"
-		 * user.  The user enters a login name which is
-		 * authenticated by PAM, usually via a remote service
-		 * such as RADIUS or TACACS+.  If authentication
-		 * succeeds, a different but related "template" name
-		 * is used for setting the credentials, shell, and
-		 * home directory.  The name the user enters need only
-		 * exist on the remote authentication server, but the
-		 * template name must be present in the local password
-		 * database.
-		 *
-		 * This is supported by two various mechanisms in the
-		 * individual modules.  However, from the application's
-		 * point of view, the template user is always passed
-		 * back as a changed value of the PAM_USER item.
-		 */
-		if ((e = pam_get_item(pamh, PAM_USER, &item)) ==
-		    PAM_SUCCESS) {
-			tmpl_user = (const char *) item;
-			if (strcmp((*ppw)->pw_name, tmpl_user) != 0)
-				*ppw = getpwnam(tmpl_user);
-		} else
-			syslog(LOG_ERR, "Couldn't get PAM_USER: %s",
-			    pam_strerror(pamh, e));
-		rval = 0;
-		break;
-
-	case PAM_AUTH_ERR:
-	case PAM_USER_UNKNOWN:
-	case PAM_MAXTRIES:
-		rval = 1;
-		break;
-
-	default:
-		syslog(LOG_ERR, "pam_authenticate: %s", pam_strerror(pamh, e));
-		rval = -1;
-		break;
-	}
-
-	if (rval == 0) {
-		e = pam_acct_mgmt(pamh, 0);
-		if (e != PAM_SUCCESS) {
-			syslog(LOG_ERR, "pam_acct_mgmt: %s",
-						pam_strerror(pamh, e));
-			rval = 1;
-		}
-	}
-
-	if (rval != 0) {
-		if ((e = pam_end(pamh, e)) != PAM_SUCCESS) {
-			syslog(LOG_ERR, "pam_end: %s", pam_strerror(pamh, e));
-		}
-		pamh = NULL;
-	}
-	return rval;
-}
-
-#endif /* USE_PAM */
-
-void
-pass(char *passwd)
-{
-	int rval, ecode;
-	FILE *fd;
-#ifdef	LOGIN_CAP
-	login_cap_t *lc = NULL;
-#endif
-#ifdef USE_PAM
-	int e;
-#endif
-	char *residue = NULL;
-	char *xpasswd;
-
-	if (logged_in || askpasswd == 0) {
-		reply(503, "Login with USER first.");
-		return;
-	}
-	askpasswd = 0;
-	if (!guest) {		/* "ftp" is only account allowed no password */
-		if (pw == NULL) {
-			rval = 1;	/* failure below */
-			goto skip;
-		}
-#ifdef USE_PAM
-		rval = auth_pam(&pw, passwd);
-		if (rval >= 0) {
-			goto skip;
-		}
-#endif
-		xpasswd = crypt(passwd, pw->pw_passwd);
-		if (passwd[0] == '\0' && pw->pw_passwd[0] != '\0')
-			xpasswd = ":";
-		rval = strcmp(pw->pw_passwd, xpasswd);
-		if (pw->pw_expire && time(NULL) >= pw->pw_expire)
-			rval = 1;	/* failure */
-skip:
-		/*
-		 * If rval == 1, the user failed the authentication check
-		 * above.  If rval == 0, either PAM or local authentication
-		 * succeeded.
-		 */
-		if (rval) {
-			reply(530, "Login incorrect.");
-			BLACKLIST_NOTIFY(BLACKLIST_AUTH_FAIL, STDIN_FILENO, "Login incorrect");
-			if (logging) {
-				syslog(LOG_NOTICE,
-				    "FTP LOGIN FAILED FROM %s",
-				    remotehost);
-				syslog(LOG_AUTHPRIV | LOG_NOTICE,
-				    "FTP LOGIN FAILED FROM %s, %s",
-				    remotehost, curname);
-			}
-			pw = NULL;
-			if (login_attempts++ >= 5) {
-				syslog(LOG_NOTICE,
-				    "repeated login failures from %s",
-				    remotehost);
-				exit(0);
-			}
-			return;
-		} else {
-			BLACKLIST_NOTIFY(BLACKLIST_AUTH_OK, STDIN_FILENO, "Login successful");
-		}
-	}
-	login_attempts = 0;		/* this time successful */
-	if (setegid(pw->pw_gid) < 0) {
-		reply(550, "Can't set gid.");
-		return;
-	}
-	/* May be overridden by login.conf */
-	(void) umask(defumask);
-#ifdef	LOGIN_CAP
-	if ((lc = login_getpwclass(pw)) != NULL) {
-		char	remote_ip[NI_MAXHOST];
-
-		if (getnameinfo((struct sockaddr *)&his_addr, his_addr.su_len,
-			remote_ip, sizeof(remote_ip) - 1, NULL, 0,
-			NI_NUMERICHOST))
-				*remote_ip = 0;
-		remote_ip[sizeof(remote_ip) - 1] = 0;
-		if (!auth_hostok(lc, remotehost, remote_ip)) {
-			syslog(LOG_INFO|LOG_AUTH,
-			    "FTP LOGIN FAILED (HOST) as %s: permission denied.",
-			    pw->pw_name);
-			reply(530, "Permission denied.");
-			pw = NULL;
-			return;
-		}
-		if (!auth_timeok(lc, time(NULL))) {
-			reply(530, "Login not available right now.");
-			pw = NULL;
-			return;
-		}
-	}
-	setusercontext(lc, pw, 0, LOGIN_SETALL &
-		       ~(LOGIN_SETRESOURCES | LOGIN_SETUSER | LOGIN_SETPATH | LOGIN_SETENV));
-#else
-	setlogin(pw->pw_name);
-	(void) initgroups(pw->pw_name, pw->pw_gid);
-#endif
-
-#ifdef USE_PAM
-	if (pamh) {
-		if ((e = pam_open_session(pamh, 0)) != PAM_SUCCESS) {
-			syslog(LOG_ERR, "pam_open_session: %s", pam_strerror(pamh, e));
-		} else if ((e = pam_setcred(pamh, PAM_ESTABLISH_CRED)) != PAM_SUCCESS) {
-			syslog(LOG_ERR, "pam_setcred: %s", pam_strerror(pamh, e));
-		}
-	}
-#endif
-
-	dochroot =
-		checkuser(_PATH_FTPCHROOT, pw->pw_name, 1, &residue, &ecode)
-#ifdef	LOGIN_CAP	/* Allow login.conf configuration as well */
-		|| login_getcapbool(lc, "ftp-chroot", 0)
-#endif
-	;
-	/*
-	 * It is possible that checkuser() failed to open the chroot file.
-	 * If this is the case, report that logins are un-available, since we
-	 * have no way of checking whether or not the user should be chrooted.
-	 * We ignore ENOENT since it is not required that this file be present.
-	 */
-	if (ecode != 0 && ecode != ENOENT) {
-		reply(530, "Login not available right now.");
-		return;
-	}
-	chrootdir = NULL;
-
-	/* Disable wtmp logging when chrooting. */
-	if (dochroot || guest)
-		dowtmp = 0;
-	if (dowtmp)
-		ftpd_logwtmp(wtmpid, pw->pw_name,
-		    (struct sockaddr *)&his_addr);
-	logged_in = 1;
-
-#ifdef	LOGIN_CAP
-	setusercontext(lc, pw, 0, LOGIN_SETRESOURCES);
-#endif
-
-	if (guest && stats && statfd < 0) {
-#ifdef VIRTUAL_HOSTING
-		statfd = open(thishost->statfile, O_WRONLY|O_APPEND);
-#else
-		statfd = open(_PATH_FTPDSTATFILE, O_WRONLY|O_APPEND);
-#endif
-		if (statfd < 0)
-			stats = 0;
-	}
-
-	/*
-	 * For a chrooted local user,
-	 * a) see whether ftpchroot(5) specifies a chroot directory,
-	 * b) extract the directory pathname from the line,
-	 * c) expand it to the absolute pathname if necessary.
-	 */
-	if (dochroot && residue &&
-	    (chrootdir = strtok(residue, " \t")) != NULL) {
-		if (chrootdir[0] != '/')
-			asprintf(&chrootdir, "%s/%s", pw->pw_dir, chrootdir);
-		else
-			chrootdir = strdup(chrootdir); /* make it permanent */
-		if (chrootdir == NULL)
-			fatalerror("Ran out of memory.");
-	}
-	if (guest || dochroot) {
-		/*
-		 * If no chroot directory set yet, use the login directory.
-		 * Copy it so it can be modified while pw->pw_dir stays intact.
-		 */
-		if (chrootdir == NULL &&
-		    (chrootdir = strdup(pw->pw_dir)) == NULL)
-			fatalerror("Ran out of memory.");
-		/*
-		 * Check for the "/chroot/./home" syntax,
-		 * separate the chroot and home directory pathnames.
-		 */
-		if ((homedir = strstr(chrootdir, "/./")) != NULL) {
-			*(homedir++) = '\0';	/* wipe '/' */
-			homedir++;		/* skip '.' */
-		} else {
-			/*
-			 * We MUST do a chdir() after the chroot. Otherwise
-			 * the old current directory will be accessible as "."
-			 * outside the new root!
-			 */
-			homedir = "/";
-		}
-		/*
-		 * Finally, do chroot()
-		 */
-		if (chroot(chrootdir) < 0) {
-			reply(550, "Can't change root.");
-			goto bad;
-		}
-		__FreeBSD_libc_enter_restricted_mode();
-	} else	/* real user w/o chroot */
-		homedir = pw->pw_dir;
-	/*
-	 * Set euid *before* doing chdir() so
-	 * a) the user won't be carried to a directory that he couldn't reach
-	 *    on his own due to no permission to upper path components,
-	 * b) NFS mounted homedirs w/restrictive permissions will be accessible
-	 *    (uid 0 has no root power over NFS if not mapped explicitly.)
-	 */
-	if (seteuid(pw->pw_uid) < 0) {
-		if (guest || dochroot) {
-			fatalerror("Can't set uid.");
-		} else {
-			reply(550, "Can't set uid.");
-			goto bad;
-		}
-	}
-	/*
-	 * Do not allow the session to live if we're chroot()'ed and chdir()
-	 * fails. Otherwise the chroot jail can be escaped.
-	 */
-	if (chdir(homedir) < 0) {
-		if (guest || dochroot) {
-			fatalerror("Can't change to base directory.");
-		} else {
-			if (chdir("/") < 0) {
-				reply(550, "Root is inaccessible.");
-				goto bad;
-			}
-			lreply(230, "No directory! Logging in with home=/.");
-		}
-	}
-
-	/*
-	 * Display a login message, if it exists.
-	 * N.B. reply(230,) must follow the message.
-	 */
-#ifdef VIRTUAL_HOSTING
-	fd = fopen(thishost->loginmsg, "r");
-#else
-	fd = fopen(_PATH_FTPLOGINMESG, "r");
-#endif
-	if (fd != NULL) {
-		char *cp, line[LINE_MAX];
-
-		while (fgets(line, sizeof(line), fd) != NULL) {
-			if ((cp = strchr(line, '\n')) != NULL)
-				*cp = '\0';
-			lreply(230, "%s", line);
-		}
-		(void) fflush(stdout);
-		(void) fclose(fd);
-	}
-	if (guest) {
-		if (ident != NULL)
-			free(ident);
-		ident = strdup(passwd);
-		if (ident == NULL)
-			fatalerror("Ran out of memory.");
-
-		reply(230, "Guest login ok, access restrictions apply.");
-#ifdef SETPROCTITLE
-#ifdef VIRTUAL_HOSTING
-		if (thishost != firsthost)
-			snprintf(proctitle, sizeof(proctitle),
-				 "%s: anonymous(%s)/%s", remotehost, hostname,
-				 passwd);
-		else
-#endif
-			snprintf(proctitle, sizeof(proctitle),
-				 "%s: anonymous/%s", remotehost, passwd);
-		setproctitle("%s", proctitle);
-#endif /* SETPROCTITLE */
-		if (logging)
-			syslog(LOG_INFO, "ANONYMOUS FTP LOGIN FROM %s, %s",
-			    remotehost, passwd);
-	} else {
-		if (dochroot)
-			reply(230, "User %s logged in, "
-				   "access restrictions apply.", pw->pw_name);
-		else
-			reply(230, "User %s logged in.", pw->pw_name);
-
-#ifdef SETPROCTITLE
-		snprintf(proctitle, sizeof(proctitle),
-			 "%s: user/%s", remotehost, pw->pw_name);
-		setproctitle("%s", proctitle);
-#endif /* SETPROCTITLE */
-		if (logging)
-			syslog(LOG_INFO, "FTP LOGIN FROM %s as %s",
-			    remotehost, pw->pw_name);
-	}
-	if (logging && (guest || dochroot))
-		syslog(LOG_INFO, "session root changed to %s", chrootdir);
-#ifdef	LOGIN_CAP
-	login_close(lc);
-#endif
-	if (residue)
-		free(residue);
-	return;
-bad:
-	/* Forget all about it... */
-#ifdef	LOGIN_CAP
-	login_close(lc);
-#endif
-	if (residue)
-		free(residue);
-	end_login();
-}
-
-void
-retrieve(char *cmd, char *name)
-{
-	FILE *fin, *dout;
-	struct stat st;
-	int (*closefunc)(FILE *);
-	time_t start;
-	char line[BUFSIZ];
-
-	if (cmd == 0) {
-		fin = fopen(name, "r"), closefunc = fclose;
-		st.st_size = 0;
-	} else {
-		(void) snprintf(line, sizeof(line), cmd, name);
-		name = line;
-		fin = ftpd_popen(line, "r"), closefunc = ftpd_pclose;
-		st.st_size = -1;
-		st.st_blksize = BUFSIZ;
-	}
-	if (fin == NULL) {
-		if (errno != 0) {
-			perror_reply(550, name);
-			if (cmd == 0) {
-				LOGCMD("get", name);
-			}
-		}
-		return;
-	}
-	byte_count = -1;
-	if (cmd == 0) {
-		if (fstat(fileno(fin), &st) < 0) {
-			perror_reply(550, name);
-			goto done;
-		}
-		if (!S_ISREG(st.st_mode)) {
-			/*
-			 * Never sending a raw directory is a workaround
-			 * for buggy clients that will attempt to RETR
-			 * a directory before listing it, e.g., Mozilla.
-			 * Preventing a guest from getting irregular files
-			 * is a simple security measure.
-			 */
-			if (S_ISDIR(st.st_mode) || guest) {
-				reply(550, "%s: not a plain file.", name);
-				goto done;
-			}
-			st.st_size = -1;
-			/* st.st_blksize is set for all descriptor types */
-		}
-	}
-	if (restart_point) {
-		if (type == TYPE_A) {
-			off_t i, n;
-			int c;
-
-			n = restart_point;
-			i = 0;
-			while (i++ < n) {
-				if ((c=getc(fin)) == EOF) {
-					perror_reply(550, name);
-					goto done;
-				}
-				if (c == '\n')
-					i++;
-			}
-		} else if (lseek(fileno(fin), restart_point, L_SET) < 0) {
-			perror_reply(550, name);
-			goto done;
-		}
-	}
-	dout = dataconn(name, st.st_size, "w");
-	if (dout == NULL)
-		goto done;
-	time(&start);
-	send_data(fin, dout, st.st_blksize, st.st_size,
-		  restart_point == 0 && cmd == 0 && S_ISREG(st.st_mode));
-	if (cmd == 0 && guest && stats && byte_count > 0)
-		logxfer(name, byte_count, start);
-	(void) fclose(dout);
-	data = -1;
-	pdata = -1;
-done:
-	if (cmd == 0)
-		LOGBYTES("get", name, byte_count);
-	(*closefunc)(fin);
-}
-
-void
-store(char *name, char *mode, int unique)
-{
-	int fd;
-	FILE *fout, *din;
-	int (*closefunc)(FILE *);
-
-	if (*mode == 'a') {		/* APPE */
-		if (unique) {
-			/* Programming error */
-			syslog(LOG_ERR, "Internal: unique flag to APPE");
-			unique = 0;
-		}
-		if (guest && noguestmod) {
-			reply(550, "Appending to existing file denied.");
-			goto err;
-		}
-		restart_point = 0;	/* not affected by preceding REST */
-	}
-	if (unique)			/* STOU overrides REST */
-		restart_point = 0;
-	if (guest && noguestmod) {
-		if (restart_point) {	/* guest STOR w/REST */
-			reply(550, "Modifying existing file denied.");
-			goto err;
-		} else			/* treat guest STOR as STOU */
-			unique = 1;
-	}
-
-	if (restart_point)
-		mode = "r+";	/* so ASCII manual seek can work */
-	if (unique) {
-		if ((fd = guniquefd(name, &name)) < 0)
-			goto err;
-		fout = fdopen(fd, mode);
-	} else
-		fout = fopen(name, mode);
-	closefunc = fclose;
-	if (fout == NULL) {
-		perror_reply(553, name);
-		goto err;
-	}
-	byte_count = -1;
-	if (restart_point) {
-		if (type == TYPE_A) {
-			off_t i, n;
-			int c;
-
-			n = restart_point;
-			i = 0;
-			while (i++ < n) {
-				if ((c=getc(fout)) == EOF) {
-					perror_reply(550, name);
-					goto done;
-				}
-				if (c == '\n')
-					i++;
-			}
-			/*
-			 * We must do this seek to "current" position
-			 * because we are changing from reading to
-			 * writing.
-			 */
-			if (fseeko(fout, 0, SEEK_CUR) < 0) {
-				perror_reply(550, name);
-				goto done;
-			}
-		} else if (lseek(fileno(fout), restart_point, L_SET) < 0) {
-			perror_reply(550, name);
-			goto done;
-		}
-	}
-	din = dataconn(name, -1, "r");
-	if (din == NULL)
-		goto done;
-	if (receive_data(din, fout) == 0) {
-		if (unique)
-			reply(226, "Transfer complete (unique file name:%s).",
-			    name);
-		else
-			reply(226, "Transfer complete.");
-	}
-	(void) fclose(din);
-	data = -1;
-	pdata = -1;
-done:
-	LOGBYTES(*mode == 'a' ? "append" : "put", name, byte_count);
-	(*closefunc)(fout);
-	return;
-err:
-	LOGCMD(*mode == 'a' ? "append" : "put" , name);
-	return;
-}
-
-static FILE *
-getdatasock(char *mode)
-{
-	int on = 1, s, t, tries;
-
-	if (data >= 0)
-		return (fdopen(data, mode));
-
-	s = socket(data_dest.su_family, SOCK_STREAM, 0);
-	if (s < 0)
-		goto bad;
-	if (setsockopt(s, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on)) < 0)
-		syslog(LOG_WARNING, "data setsockopt (SO_REUSEADDR): %m");
-	/* anchor socket to avoid multi-homing problems */
-	data_source = ctrl_addr;
-	data_source.su_port = htons(dataport);
-	(void) seteuid(0);
-	for (tries = 1; ; tries++) {
-		/*
-		 * We should loop here since it's possible that
-		 * another ftpd instance has passed this point and is
-		 * trying to open a data connection in active mode now.
-		 * Until the other connection is opened, we'll be getting
-		 * EADDRINUSE because no SOCK_STREAM sockets in the system
-		 * can share both local and remote addresses, localIP:20
-		 * and *:* in this case.
-		 */
-		if (bind(s, (struct sockaddr *)&data_source,
-		    data_source.su_len) >= 0)
-			break;
-		if (errno != EADDRINUSE || tries > 10)
-			goto bad;
-		sleep(tries);
-	}
-	(void) seteuid(pw->pw_uid);
-#ifdef IP_TOS
-	if (data_source.su_family == AF_INET)
-      {
-	on = IPTOS_THROUGHPUT;
-	if (setsockopt(s, IPPROTO_IP, IP_TOS, &on, sizeof(int)) < 0)
-		syslog(LOG_WARNING, "data setsockopt (IP_TOS): %m");
-      }
-#endif
-#ifdef TCP_NOPUSH
-	/*
-	 * Turn off push flag to keep sender TCP from sending short packets
-	 * at the boundaries of each write().
-	 */
-	on = 1;
-	if (setsockopt(s, IPPROTO_TCP, TCP_NOPUSH, &on, sizeof on) < 0)
-		syslog(LOG_WARNING, "data setsockopt (TCP_NOPUSH): %m");
-#endif
-	return (fdopen(s, mode));
-bad:
-	/* Return the real value of errno (close may change it) */
-	t = errno;
-	(void) seteuid(pw->pw_uid);
-	(void) close(s);
-	errno = t;
-	return (NULL);
-}
-
-static FILE *
-dataconn(char *name, off_t size, char *mode)
-{
-	char sizebuf[32];
-	FILE *file;
-	int retry = 0, tos, conerrno;
-
-	file_size = size;
-	byte_count = 0;
-	if (size != -1)
-		(void) snprintf(sizebuf, sizeof(sizebuf),
-				" (%jd bytes)", (intmax_t)size);
-	else
-		*sizebuf = '\0';
-	if (pdata >= 0) {
-		union sockunion from;
-		socklen_t fromlen = ctrl_addr.su_len;
-		int flags, s;
-		struct timeval timeout;
-		fd_set set;
-
-		FD_ZERO(&set);
-		FD_SET(pdata, &set);
-
-		timeout.tv_usec = 0;
-		timeout.tv_sec = 120;
-
-		/*
-		 * Granted a socket is in the blocking I/O mode,
-		 * accept() will block after a successful select()
-		 * if the selected connection dies in between.
-		 * Therefore set the non-blocking I/O flag here.
-		 */
-		if ((flags = fcntl(pdata, F_GETFL, 0)) == -1 ||
-		    fcntl(pdata, F_SETFL, flags | O_NONBLOCK) == -1)
-			goto pdata_err;
-		if (select(pdata+1, &set, NULL, NULL, &timeout) <= 0 ||
-		    (s = accept(pdata, (struct sockaddr *) &from, &fromlen)) < 0)
-			goto pdata_err;
-		(void) close(pdata);
-		pdata = s;
-		/*
-		 * Unset the inherited non-blocking I/O flag
-		 * on the child socket so stdio can work on it.
-		 */
-		if ((flags = fcntl(pdata, F_GETFL, 0)) == -1 ||
-		    fcntl(pdata, F_SETFL, flags & ~O_NONBLOCK) == -1)
-			goto pdata_err;
-#ifdef IP_TOS
-		if (from.su_family == AF_INET)
-	      {
-		tos = IPTOS_THROUGHPUT;
-		if (setsockopt(s, IPPROTO_IP, IP_TOS, &tos, sizeof(int)) < 0)
-			syslog(LOG_WARNING, "pdata setsockopt (IP_TOS): %m");
-	      }
-#endif
-		reply(150, "Opening %s mode data connection for '%s'%s.",
-		     type == TYPE_A ? "ASCII" : "BINARY", name, sizebuf);
-		return (fdopen(pdata, mode));
-pdata_err:
-		reply(425, "Can't open data connection.");
-		(void) close(pdata);
-		pdata = -1;
-		return (NULL);
-	}
-	if (data >= 0) {
-		reply(125, "Using existing data connection for '%s'%s.",
-		    name, sizebuf);
-		usedefault = 1;
-		return (fdopen(data, mode));
-	}
-	if (usedefault)
-		data_dest = his_addr;
-	usedefault = 1;
-	do {
-		file = getdatasock(mode);
-		if (file == NULL) {
-			char hostbuf[NI_MAXHOST], portbuf[NI_MAXSERV];
-
-			if (getnameinfo((struct sockaddr *)&data_source,
-				data_source.su_len,
-				hostbuf, sizeof(hostbuf) - 1,
-				portbuf, sizeof(portbuf) - 1,
-				NI_NUMERICHOST|NI_NUMERICSERV))
-					*hostbuf = *portbuf = 0;
-			hostbuf[sizeof(hostbuf) - 1] = 0;
-			portbuf[sizeof(portbuf) - 1] = 0;
-			reply(425, "Can't create data socket (%s,%s): %s.",
-				hostbuf, portbuf, strerror(errno));
-			return (NULL);
-		}
-		data = fileno(file);
-		conerrno = 0;
-		if (connect(data, (struct sockaddr *)&data_dest,
-		    data_dest.su_len) == 0)
-			break;
-		conerrno = errno;
-		(void) fclose(file);
-		data = -1;
-		if (conerrno == EADDRINUSE) {
-			sleep(swaitint);
-			retry += swaitint;
-		} else {
-			break;
-		}
-	} while (retry <= swaitmax);
-	if (conerrno != 0) {
-		reply(425, "Can't build data connection: %s.",
-			   strerror(conerrno));
-		return (NULL);
-	}
-	reply(150, "Opening %s mode data connection for '%s'%s.",
-	     type == TYPE_A ? "ASCII" : "BINARY", name, sizebuf);
-	return (file);
-}
-
-/*
- * A helper macro to avoid code duplication
- * in send_data() and receive_data().
- *
- * XXX We have to block SIGURG during putc() because BSD stdio
- * is unable to restart interrupted write operations and hence
- * the entire buffer contents will be lost as soon as a write()
- * call indicates EINTR to stdio.
- */
-#define FTPD_PUTC(ch, file, label)					\
-	do {								\
-		int ret;						\
-									\
-		do {							\
-			START_UNSAFE;					\
-			ret = putc((ch), (file));			\
-			END_UNSAFE;					\
-			CHECKOOB(return (-1))				\
-			else if (ferror(file))				\
-				goto label;				\
-			clearerr(file);					\
-		} while (ret == EOF);					\
-	} while (0)
-
-/*
- * Transfer the contents of "instr" to "outstr" peer using the appropriate
- * encapsulation of the data subject to Mode, Structure, and Type.
- *
- * NB: Form isn't handled.
- */
-static int
-send_data(FILE *instr, FILE *outstr, size_t blksize, off_t filesize, int isreg)
-{
-	int c, cp, filefd, netfd;
-	char *buf;
-
-	STARTXFER;
-
-	switch (type) {
-
-	case TYPE_A:
-		cp = EOF;
-		for (;;) {
-			c = getc(instr);
-			CHECKOOB(return (-1))
-			else if (c == EOF && ferror(instr))
-				goto file_err;
-			if (c == EOF) {
-				if (ferror(instr)) {	/* resume after OOB */
-					clearerr(instr);
-					continue;
-				}
-				if (feof(instr))	/* EOF */
-					break;
-				syslog(LOG_ERR, "Internal: impossible condition"
-						" on file after getc()");
-				goto file_err;
-			}
-			if (c == '\n' && cp != '\r') {
-				FTPD_PUTC('\r', outstr, data_err);
-				byte_count++;
-			}
-			FTPD_PUTC(c, outstr, data_err);
-			byte_count++;
-			cp = c;
-		}
-#ifdef notyet	/* BSD stdio isn't ready for that */
-		while (fflush(outstr) == EOF) {
-			CHECKOOB(return (-1))
-			else
-				goto data_err;
-			clearerr(outstr);
-		}
-		ENDXFER;
-#else
-		ENDXFER;
-		if (fflush(outstr) == EOF)
-			goto data_err;
-#endif
-		reply(226, "Transfer complete.");
-		return (0);
-
-	case TYPE_I:
-	case TYPE_L:
-		/*
-		 * isreg is only set if we are not doing restart and we
-		 * are sending a regular file
-		 */
-		netfd = fileno(outstr);
-		filefd = fileno(instr);
-
-		if (isreg) {
-			char *msg = "Transfer complete.";
-			off_t cnt, offset;
-			int err;
-
-			cnt = offset = 0;
-
-			while (filesize > 0) {
-				err = sendfile(filefd, netfd, offset, 0,
-					       NULL, &cnt, 0);
-				/*
-				 * Calculate byte_count before OOB processing.
-				 * It can be used in myoob() later.
-				 */
-				byte_count += cnt;
-				offset += cnt;
-				filesize -= cnt;
-				CHECKOOB(return (-1))
-				else if (err == -1) {
-					if (errno != EINTR &&
-					    cnt == 0 && offset == 0)
-						goto oldway;
-					goto data_err;
-				}
-				if (err == -1)	/* resume after OOB */
-					continue;
-				/*
-				 * We hit the EOF prematurely.
-				 * Perhaps the file was externally truncated.
-				 */
-				if (cnt == 0) {
-					msg = "Transfer finished due to "
-					      "premature end of file.";
-					break;
-				}
-			}
-			ENDXFER;
-			reply(226, "%s", msg);
-			return (0);
-		}
-
-oldway:
-		if ((buf = malloc(blksize)) == NULL) {
-			ENDXFER;
-			reply(451, "Ran out of memory.");
-			return (-1);
-		}
-
-		for (;;) {
-			int cnt, len;
-			char *bp;
-
-			cnt = read(filefd, buf, blksize);
-			CHECKOOB(free(buf); return (-1))
-			else if (cnt < 0) {
-				free(buf);
-				goto file_err;
-			}
-			if (cnt < 0)	/* resume after OOB */
-				continue;
-			if (cnt == 0)	/* EOF */
-				break;
-			for (len = cnt, bp = buf; len > 0;) {
-				cnt = write(netfd, bp, len);
-				CHECKOOB(free(buf); return (-1))
-				else if (cnt < 0) {
-					free(buf);
-					goto data_err;
-				}
-				if (cnt <= 0)
-					continue;
-				len -= cnt;
-				bp += cnt;
-				byte_count += cnt;
-			}
-		}
-		ENDXFER;
-		free(buf);
-		reply(226, "Transfer complete.");
-		return (0);
-	default:
-		ENDXFER;
-		reply(550, "Unimplemented TYPE %d in send_data.", type);
-		return (-1);
-	}
-
-data_err:
-	ENDXFER;
-	perror_reply(426, "Data connection");
-	return (-1);
-
-file_err:
-	ENDXFER;
-	perror_reply(551, "Error on input file");
-	return (-1);
-}
-
-/*
- * Transfer data from peer to "outstr" using the appropriate encapulation of
- * the data subject to Mode, Structure, and Type.
- *
- * N.B.: Form isn't handled.
- */
-static int
-receive_data(FILE *instr, FILE *outstr)
-{
-	int c, cp;
-	int bare_lfs = 0;
-
-	STARTXFER;
-
-	switch (type) {
-
-	case TYPE_I:
-	case TYPE_L:
-		for (;;) {
-			int cnt, len;
-			char *bp;
-			char buf[BUFSIZ];
-
-			cnt = read(fileno(instr), buf, sizeof(buf));
-			CHECKOOB(return (-1))
-			else if (cnt < 0)
-				goto data_err;
-			if (cnt < 0)	/* resume after OOB */
-				continue;
-			if (cnt == 0)	/* EOF */
-				break;
-			for (len = cnt, bp = buf; len > 0;) {
-				cnt = write(fileno(outstr), bp, len);
-				CHECKOOB(return (-1))
-				else if (cnt < 0)
-					goto file_err;
-				if (cnt <= 0)
-					continue;
-				len -= cnt;
-				bp += cnt;
-				byte_count += cnt;
-			}
-		}
-		ENDXFER;
-		return (0);
-
-	case TYPE_E:
-		ENDXFER;
-		reply(553, "TYPE E not implemented.");
-		return (-1);
-
-	case TYPE_A:
-		cp = EOF;
-		for (;;) {
-			c = getc(instr);
-			CHECKOOB(return (-1))
-			else if (c == EOF && ferror(instr))
-				goto data_err;
-			if (c == EOF && ferror(instr)) { /* resume after OOB */
-				clearerr(instr);
-				continue;
-			}
-
-			if (cp == '\r') {
-				if (c != '\n')
-					FTPD_PUTC('\r', outstr, file_err);
-			} else
-				if (c == '\n')
-					bare_lfs++;
-			if (c == '\r') {
-				byte_count++;
-				cp = c;
-				continue;
-			}
-
-			/* Check for EOF here in order not to lose last \r. */
-			if (c == EOF) {
-				if (feof(instr))	/* EOF */
-					break;
-				syslog(LOG_ERR, "Internal: impossible condition"
-						" on data stream after getc()");
-				goto data_err;
-			}
-
-			byte_count++;
-			FTPD_PUTC(c, outstr, file_err);
-			cp = c;
-		}
-#ifdef notyet	/* BSD stdio isn't ready for that */
-		while (fflush(outstr) == EOF) {
-			CHECKOOB(return (-1))
-			else
-				goto file_err;
-			clearerr(outstr);
-		}
-		ENDXFER;
-#else
-		ENDXFER;
-		if (fflush(outstr) == EOF)
-			goto file_err;
-#endif
-		if (bare_lfs) {
-			lreply(226,
-		"WARNING! %d bare linefeeds received in ASCII mode.",
-			    bare_lfs);
-		(void)printf("   File may not have transferred correctly.\r\n");
-		}
-		return (0);
-	default:
-		ENDXFER;
-		reply(550, "Unimplemented TYPE %d in receive_data.", type);
-		return (-1);
-	}
-
-data_err:
-	ENDXFER;
-	perror_reply(426, "Data connection");
-	return (-1);
-
-file_err:
-	ENDXFER;
-	perror_reply(452, "Error writing to file");
-	return (-1);
-}
-
-void
-statfilecmd(char *filename)
-{
-	FILE *fin;
-	int atstart;
-	int c, code;
-	char line[LINE_MAX];
-	struct stat st;
-
-	code = lstat(filename, &st) == 0 && S_ISDIR(st.st_mode) ? 212 : 213;
-	(void)snprintf(line, sizeof(line), _PATH_LS " -lA %s", filename);
-	fin = ftpd_popen(line, "r");
-	if (fin == NULL) {
-		perror_reply(551, filename);
-		return;
-	}
-	lreply(code, "Status of %s:", filename);
-	atstart = 1;
-	while ((c = getc(fin)) != EOF) {
-		if (c == '\n') {
-			if (ferror(stdout)){
-				perror_reply(421, "Control connection");
-				(void) ftpd_pclose(fin);
-				dologout(1);
-				/* NOTREACHED */
-			}
-			if (ferror(fin)) {
-				perror_reply(551, filename);
-				(void) ftpd_pclose(fin);
-				return;
-			}
-			(void) putc('\r', stdout);
-		}
-		/*
-		 * RFC 959 says neutral text should be prepended before
-		 * a leading 3-digit number followed by whitespace, but
-		 * many ftp clients can be confused by any leading digits,
-		 * as a matter of fact.
-		 */
-		if (atstart && isdigit(c))
-			(void) putc(' ', stdout);
-		(void) putc(c, stdout);
-		atstart = (c == '\n');
-	}
-	(void) ftpd_pclose(fin);
-	reply(code, "End of status.");
-}
-
-void
-statcmd(void)
-{
-	union sockunion *su;
-	u_char *a, *p;
-	char hname[NI_MAXHOST];
-	int ispassive;
-
-	if (hostinfo) {
-		lreply(211, "%s FTP server status:", hostname);
-		printf("     %s\r\n", version);
-	} else
-		lreply(211, "FTP server status:");
-	printf("     Connected to %s", remotehost);
-	if (!getnameinfo((struct sockaddr *)&his_addr, his_addr.su_len,
-			 hname, sizeof(hname) - 1, NULL, 0, NI_NUMERICHOST)) {
-		hname[sizeof(hname) - 1] = 0;
-		if (strcmp(hname, remotehost) != 0)
-			printf(" (%s)", hname);
-	}
-	printf("\r\n");
-	if (logged_in) {
-		if (guest)
-			printf("     Logged in anonymously\r\n");
-		else
-			printf("     Logged in as %s\r\n", pw->pw_name);
-	} else if (askpasswd)
-		printf("     Waiting for password\r\n");
-	else
-		printf("     Waiting for user name\r\n");
-	printf("     TYPE: %s", typenames[type]);
-	if (type == TYPE_A || type == TYPE_E)
-		printf(", FORM: %s", formnames[form]);
-	if (type == TYPE_L)
-#if CHAR_BIT == 8
-		printf(" %d", CHAR_BIT);
-#else
-		printf(" %d", bytesize);	/* need definition! */
-#endif
-	printf("; STRUcture: %s; transfer MODE: %s\r\n",
-	    strunames[stru], modenames[mode]);
-	if (data != -1)
-		printf("     Data connection open\r\n");
-	else if (pdata != -1) {
-		ispassive = 1;
-		su = &pasv_addr;
-		goto printaddr;
-	} else if (usedefault == 0) {
-		ispassive = 0;
-		su = &data_dest;
-printaddr:
-#define UC(b) (((int) b) & 0xff)
-		if (epsvall) {
-			printf("     EPSV only mode (EPSV ALL)\r\n");
-			goto epsvonly;
-		}
-
-		/* PORT/PASV */
-		if (su->su_family == AF_INET) {
-			a = (u_char *) &su->su_sin.sin_addr;
-			p = (u_char *) &su->su_sin.sin_port;
-			printf("     %s (%d,%d,%d,%d,%d,%d)\r\n",
-				ispassive ? "PASV" : "PORT",
-				UC(a[0]), UC(a[1]), UC(a[2]), UC(a[3]),
-				UC(p[0]), UC(p[1]));
-		}
-
-		/* LPRT/LPSV */
-	    {
-		int alen, af, i;
-
-		switch (su->su_family) {
-		case AF_INET:
-			a = (u_char *) &su->su_sin.sin_addr;
-			p = (u_char *) &su->su_sin.sin_port;
-			alen = sizeof(su->su_sin.sin_addr);
-			af = 4;
-			break;
-		case AF_INET6:
-			a = (u_char *) &su->su_sin6.sin6_addr;
-			p = (u_char *) &su->su_sin6.sin6_port;
-			alen = sizeof(su->su_sin6.sin6_addr);
-			af = 6;
-			break;
-		default:
-			af = 0;
-			break;
-		}
-		if (af) {
-			printf("     %s (%d,%d,", ispassive ? "LPSV" : "LPRT",
-				af, alen);
-			for (i = 0; i < alen; i++)
-				printf("%d,", UC(a[i]));
-			printf("%d,%d,%d)\r\n", 2, UC(p[0]), UC(p[1]));
-		}
-	    }
-
-epsvonly:;
-		/* EPRT/EPSV */
-	    {
-		int af;
-
-		switch (su->su_family) {
-		case AF_INET:
-			af = 1;
-			break;
-		case AF_INET6:
-			af = 2;
-			break;
-		default:
-			af = 0;
-			break;
-		}
-		if (af) {
-			union sockunion tmp;
-
-			tmp = *su;
-			if (tmp.su_family == AF_INET6)
-				tmp.su_sin6.sin6_scope_id = 0;
-			if (!getnameinfo((struct sockaddr *)&tmp, tmp.su_len,
-					hname, sizeof(hname) - 1, NULL, 0,
-					NI_NUMERICHOST)) {
-				hname[sizeof(hname) - 1] = 0;
-				printf("     %s |%d|%s|%d|\r\n",
-					ispassive ? "EPSV" : "EPRT",
-					af, hname, htons(tmp.su_port));
-			}
-		}
-	    }
-#undef UC
-	} else
-		printf("     No data connection\r\n");
-	reply(211, "End of status.");
-}
-
-void
-fatalerror(char *s)
-{
-
-	reply(451, "Error in server: %s", s);
-	reply(221, "Closing connection due to server error.");
-	dologout(0);
-	/* NOTREACHED */
-}
-
-void
-reply(int n, const char *fmt, ...)
-{
-	va_list ap;
-
-	(void)printf("%d ", n);
-	va_start(ap, fmt);
-	(void)vprintf(fmt, ap);
-	va_end(ap);
-	(void)printf("\r\n");
-	(void)fflush(stdout);
-	if (ftpdebug) {
-		syslog(LOG_DEBUG, "<--- %d ", n);
-		va_start(ap, fmt);
-		vsyslog(LOG_DEBUG, fmt, ap);
-		va_end(ap);
-	}
-}
-
-void
-lreply(int n, const char *fmt, ...)
-{
-	va_list ap;
-
-	(void)printf("%d- ", n);
-	va_start(ap, fmt);
-	(void)vprintf(fmt, ap);
-	va_end(ap);
-	(void)printf("\r\n");
-	(void)fflush(stdout);
-	if (ftpdebug) {
-		syslog(LOG_DEBUG, "<--- %d- ", n);
-		va_start(ap, fmt);
-		vsyslog(LOG_DEBUG, fmt, ap);
-		va_end(ap);
-	}
-}
-
-static void
-ack(char *s)
-{
-
-	reply(250, "%s command successful.", s);
-}
-
-void
-nack(char *s)
-{
-
-	reply(502, "%s command not implemented.", s);
-}
-
-/* ARGSUSED */
-void
-yyerror(char *s)
-{
-	char *cp;
-
-	if ((cp = strchr(cbuf,'\n')))
-		*cp = '\0';
-	reply(500, "%s: command not understood.", cbuf);
-}
-
-void
-delete(char *name)
-{
-	struct stat st;
-
-	LOGCMD("delete", name);
-	if (lstat(name, &st) < 0) {
-		perror_reply(550, name);
-		return;
-	}
-	if (S_ISDIR(st.st_mode)) {
-		if (rmdir(name) < 0) {
-			perror_reply(550, name);
-			return;
-		}
-		goto done;
-	}
-	if (guest && noguestmod) {
-		reply(550, "Operation not permitted.");
-		return;
-	}
-	if (unlink(name) < 0) {
-		perror_reply(550, name);
-		return;
-	}
-done:
-	ack("DELE");
-}
-
-void
-cwd(char *path)
-{
-
-	if (chdir(path) < 0)
-		perror_reply(550, path);
-	else
-		ack("CWD");
-}
-
-void
-makedir(char *name)
-{
-	char *s;
-
-	LOGCMD("mkdir", name);
-	if (guest && noguestmkd)
-		reply(550, "Operation not permitted.");
-	else if (mkdir(name, 0777) < 0)
-		perror_reply(550, name);
-	else {
-		if ((s = doublequote(name)) == NULL)
-			fatalerror("Ran out of memory.");
-		reply(257, "\"%s\" directory created.", s);
-		free(s);
-	}
-}
-
-void
-removedir(char *name)
-{
-
-	LOGCMD("rmdir", name);
-	if (rmdir(name) < 0)
-		perror_reply(550, name);
-	else
-		ack("RMD");
-}
-
-void
-pwd(void)
-{
-	char *s, path[MAXPATHLEN + 1];
-
-	if (getcwd(path, sizeof(path)) == NULL)
-		perror_reply(550, "Get current directory");
-	else {
-		if ((s = doublequote(path)) == NULL)
-			fatalerror("Ran out of memory.");
-		reply(257, "\"%s\" is current directory.", s);
-		free(s);
-	}
-}
-
-char *
-renamefrom(char *name)
-{
-	struct stat st;
-
-	if (guest && noguestmod) {
-		reply(550, "Operation not permitted.");
-		return (NULL);
-	}
-	if (lstat(name, &st) < 0) {
-		perror_reply(550, name);
-		return (NULL);
-	}
-	reply(350, "File exists, ready for destination name.");
-	return (name);
-}
-
-void
-renamecmd(char *from, char *to)
-{
-	struct stat st;
-
-	LOGCMD2("rename", from, to);
-
-	if (guest && (stat(to, &st) == 0)) {
-		reply(550, "%s: permission denied.", to);
-		return;
-	}
-
-	if (rename(from, to) < 0)
-		perror_reply(550, "rename");
-	else
-		ack("RNTO");
-}
-
-static void
-dolog(struct sockaddr *who)
-{
-	char who_name[NI_MAXHOST];
-
-	realhostname_sa(remotehost, sizeof(remotehost) - 1, who, who->sa_len);
-	remotehost[sizeof(remotehost) - 1] = 0;
-	if (getnameinfo(who, who->sa_len,
-		who_name, sizeof(who_name) - 1, NULL, 0, NI_NUMERICHOST))
-			*who_name = 0;
-	who_name[sizeof(who_name) - 1] = 0;
-
-#ifdef SETPROCTITLE
-#ifdef VIRTUAL_HOSTING
-	if (thishost != firsthost)
-		snprintf(proctitle, sizeof(proctitle), "%s: connected (to %s)",
-			 remotehost, hostname);
-	else
-#endif
-		snprintf(proctitle, sizeof(proctitle), "%s: connected",
-			 remotehost);
-	setproctitle("%s", proctitle);
-#endif /* SETPROCTITLE */
-
-	if (logging) {
-#ifdef VIRTUAL_HOSTING
-		if (thishost != firsthost)
-			syslog(LOG_INFO, "connection from %s (%s) to %s",
-			       remotehost, who_name, hostname);
-		else
-#endif
-			syslog(LOG_INFO, "connection from %s (%s)",
-			       remotehost, who_name);
-	}
-}
-
-/*
- * Record logout in wtmp file
- * and exit with supplied status.
- */
-void
-dologout(int status)
-{
-
-	if (logged_in && dowtmp) {
-		(void) seteuid(0);
-#ifdef		LOGIN_CAP
- 	        setusercontext(NULL, getpwuid(0), 0, LOGIN_SETALL & ~(LOGIN_SETLOGIN |
-		       LOGIN_SETUSER | LOGIN_SETGROUP | LOGIN_SETPATH |
-		       LOGIN_SETENV));
-#endif
-		ftpd_logwtmp(wtmpid, NULL, NULL);
-	}
-	/* beware of flushing buffers after a SIGPIPE */
-	_exit(status);
-}
-
-static void
-sigurg(int signo)
-{
-
-	recvurg = 1;
-}
-
-static void
-maskurg(int flag)
-{
-	int oerrno;
-	sigset_t sset;
-
-	if (!transflag) {
-		syslog(LOG_ERR, "Internal: maskurg() while no transfer");
-		return;
-	}
-	oerrno = errno;
-	sigemptyset(&sset);
-	sigaddset(&sset, SIGURG);
-	sigprocmask(flag ? SIG_BLOCK : SIG_UNBLOCK, &sset, NULL);
-	errno = oerrno;
-}
-
-static void
-flagxfer(int flag)
-{
-
-	if (flag) {
-		if (transflag)
-			syslog(LOG_ERR, "Internal: flagxfer(1): "
-					"transfer already under way");
-		transflag = 1;
-		maskurg(0);
-		recvurg = 0;
-	} else {
-		if (!transflag)
-			syslog(LOG_ERR, "Internal: flagxfer(0): "
-					"no active transfer");
-		maskurg(1);
-		transflag = 0;
-	}
-}
-
-/*
- * Returns 0 if OK to resume or -1 if abort requested.
- */
-static int
-myoob(void)
-{
-	char *cp;
-	int ret;
-
-	if (!transflag) {
-		syslog(LOG_ERR, "Internal: myoob() while no transfer");
-		return (0);
-	}
-	cp = tmpline;
-	ret = get_line(cp, 7, stdin);
-	if (ret == -1) {
-		reply(221, "You could at least say goodbye.");
-		dologout(0);
-	} else if (ret == -2) {
-		/* Ignore truncated command. */
-		return (0);
-	}
-	upper(cp);
-	if (strcmp(cp, "ABOR\r\n") == 0) {
-		tmpline[0] = '\0';
-		reply(426, "Transfer aborted. Data connection closed.");
-		reply(226, "Abort successful.");
-		return (-1);
-	}
-	if (strcmp(cp, "STAT\r\n") == 0) {
-		tmpline[0] = '\0';
-		if (file_size != -1)
-			reply(213, "Status: %jd of %jd bytes transferred.",
-				   (intmax_t)byte_count, (intmax_t)file_size);
-		else
-			reply(213, "Status: %jd bytes transferred.",
-				   (intmax_t)byte_count);
-	}
-	return (0);
-}
-
-/*
- * Note: a response of 425 is not mentioned as a possible response to
- *	the PASV command in RFC959. However, it has been blessed as
- *	a legitimate response by Jon Postel in a telephone conversation
- *	with Rick Adams on 25 Jan 89.
- */
-void
-passive(void)
-{
-	socklen_t len;
-	int on;
-	char *p, *a;
-
-	if (pdata >= 0)		/* close old port if one set */
-		close(pdata);
-
-	pdata = socket(ctrl_addr.su_family, SOCK_STREAM, 0);
-	if (pdata < 0) {
-		perror_reply(425, "Can't open passive connection");
-		return;
-	}
-	on = 1;
-	if (setsockopt(pdata, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on)) < 0)
-		syslog(LOG_WARNING, "pdata setsockopt (SO_REUSEADDR): %m");
-
-	(void) seteuid(0);
-
-#ifdef IP_PORTRANGE
-	if (ctrl_addr.su_family == AF_INET) {
-	    on = restricted_data_ports ? IP_PORTRANGE_HIGH
-				       : IP_PORTRANGE_DEFAULT;
-
-	    if (setsockopt(pdata, IPPROTO_IP, IP_PORTRANGE,
-			    &on, sizeof(on)) < 0)
-		    goto pasv_error;
-	}
-#endif
-#ifdef IPV6_PORTRANGE
-	if (ctrl_addr.su_family == AF_INET6) {
-	    on = restricted_data_ports ? IPV6_PORTRANGE_HIGH
-				       : IPV6_PORTRANGE_DEFAULT;
-
-	    if (setsockopt(pdata, IPPROTO_IPV6, IPV6_PORTRANGE,
-			    &on, sizeof(on)) < 0)
-		    goto pasv_error;
-	}
-#endif
-
-	pasv_addr = ctrl_addr;
-	pasv_addr.su_port = 0;
-	if (bind(pdata, (struct sockaddr *)&pasv_addr, pasv_addr.su_len) < 0)
-		goto pasv_error;
-
-	(void) seteuid(pw->pw_uid);
-
-	len = sizeof(pasv_addr);
-	if (getsockname(pdata, (struct sockaddr *) &pasv_addr, &len) < 0)
-		goto pasv_error;
-	if (listen(pdata, 1) < 0)
-		goto pasv_error;
-	if (pasv_addr.su_family == AF_INET)
-		a = (char *) &pasv_addr.su_sin.sin_addr;
-	else if (pasv_addr.su_family == AF_INET6 &&
-		 IN6_IS_ADDR_V4MAPPED(&pasv_addr.su_sin6.sin6_addr))
-		a = (char *) &pasv_addr.su_sin6.sin6_addr.s6_addr[12];
-	else
-		goto pasv_error;
-		
-	p = (char *) &pasv_addr.su_port;
-
-#define UC(b) (((int) b) & 0xff)
-
-	reply(227, "Entering Passive Mode (%d,%d,%d,%d,%d,%d)", UC(a[0]),
-		UC(a[1]), UC(a[2]), UC(a[3]), UC(p[0]), UC(p[1]));
-	return;
-
-pasv_error:
-	(void) seteuid(pw->pw_uid);
-	(void) close(pdata);
-	pdata = -1;
-	perror_reply(425, "Can't open passive connection");
-	return;
-}
-
-/*
- * Long Passive defined in RFC 1639.
- *     228 Entering Long Passive Mode
- *         (af, hal, h1, h2, h3,..., pal, p1, p2...)
- */
-
-void
-long_passive(char *cmd, int pf)
-{
-	socklen_t len;
-	int on;
-	char *p, *a;
-
-	if (pdata >= 0)		/* close old port if one set */
-		close(pdata);
-
-	if (pf != PF_UNSPEC) {
-		if (ctrl_addr.su_family != pf) {
-			switch (ctrl_addr.su_family) {
-			case AF_INET:
-				pf = 1;
-				break;
-			case AF_INET6:
-				pf = 2;
-				break;
-			default:
-				pf = 0;
-				break;
-			}
-			/*
-			 * XXX
-			 * only EPRT/EPSV ready clients will understand this
-			 */
-			if (strcmp(cmd, "EPSV") == 0 && pf) {
-				reply(522, "Network protocol mismatch, "
-					"use (%d)", pf);
-			} else
-				reply(501, "Network protocol mismatch."); /*XXX*/
-
-			return;
-		}
-	}
-		
-	pdata = socket(ctrl_addr.su_family, SOCK_STREAM, 0);
-	if (pdata < 0) {
-		perror_reply(425, "Can't open passive connection");
-		return;
-	}
-	on = 1;
-	if (setsockopt(pdata, SOL_SOCKET, SO_REUSEADDR, &on, sizeof(on)) < 0)
-		syslog(LOG_WARNING, "pdata setsockopt (SO_REUSEADDR): %m");
-
-	(void) seteuid(0);
-
-	pasv_addr = ctrl_addr;
-	pasv_addr.su_port = 0;
-	len = pasv_addr.su_len;
-
-#ifdef IP_PORTRANGE
-	if (ctrl_addr.su_family == AF_INET) {
-	    on = restricted_data_ports ? IP_PORTRANGE_HIGH
-				       : IP_PORTRANGE_DEFAULT;
-
-	    if (setsockopt(pdata, IPPROTO_IP, IP_PORTRANGE,
-			    &on, sizeof(on)) < 0)
-		    goto pasv_error;
-	}
-#endif
-#ifdef IPV6_PORTRANGE
-	if (ctrl_addr.su_family == AF_INET6) {
-	    on = restricted_data_ports ? IPV6_PORTRANGE_HIGH
-				       : IPV6_PORTRANGE_DEFAULT;
-
-	    if (setsockopt(pdata, IPPROTO_IPV6, IPV6_PORTRANGE,
-			    &on, sizeof(on)) < 0)
-		    goto pasv_error;
-	}
-#endif
-
-	if (bind(pdata, (struct sockaddr *)&pasv_addr, len) < 0)
-		goto pasv_error;
-
-	(void) seteuid(pw->pw_uid);
-
-	if (getsockname(pdata, (struct sockaddr *) &pasv_addr, &len) < 0)
-		goto pasv_error;
-	if (listen(pdata, 1) < 0)
-		goto pasv_error;
-
-#define UC(b) (((int) b) & 0xff)
-
-	if (strcmp(cmd, "LPSV") == 0) {
-		p = (char *)&pasv_addr.su_port;
-		switch (pasv_addr.su_family) {
-		case AF_INET:
-			a = (char *) &pasv_addr.su_sin.sin_addr;
-		v4_reply:
-			reply(228,
-"Entering Long Passive Mode (%d,%d,%d,%d,%d,%d,%d,%d,%d)",
-			      4, 4, UC(a[0]), UC(a[1]), UC(a[2]), UC(a[3]),
-			      2, UC(p[0]), UC(p[1]));
-			return;
-		case AF_INET6:
-			if (IN6_IS_ADDR_V4MAPPED(&pasv_addr.su_sin6.sin6_addr)) {
-				a = (char *) &pasv_addr.su_sin6.sin6_addr.s6_addr[12];
-				goto v4_reply;
-			}
-			a = (char *) &pasv_addr.su_sin6.sin6_addr;
-			reply(228,
-"Entering Long Passive Mode "
-"(%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",
-			      6, 16, UC(a[0]), UC(a[1]), UC(a[2]), UC(a[3]),
-			      UC(a[4]), UC(a[5]), UC(a[6]), UC(a[7]),
-			      UC(a[8]), UC(a[9]), UC(a[10]), UC(a[11]),
-			      UC(a[12]), UC(a[13]), UC(a[14]), UC(a[15]),
-			      2, UC(p[0]), UC(p[1]));
-			return;
-		}
-	} else if (strcmp(cmd, "EPSV") == 0) {
-		switch (pasv_addr.su_family) {
-		case AF_INET:
-		case AF_INET6:
-			reply(229, "Entering Extended Passive Mode (|||%d|)",
-				ntohs(pasv_addr.su_port));
-			return;
-		}
-	} else {
-		/* more proper error code? */
-	}
-
-pasv_error:
-	(void) seteuid(pw->pw_uid);
-	(void) close(pdata);
-	pdata = -1;
-	perror_reply(425, "Can't open passive connection");
-	return;
-}
-
-/*
- * Generate unique name for file with basename "local"
- * and open the file in order to avoid possible races.
- * Try "local" first, then "local.1", "local.2" etc, up to "local.99".
- * Return descriptor to the file, set "name" to its name.
- *
- * Generates failure reply on error.
- */
-static int
-guniquefd(char *local, char **name)
-{
-	static char new[MAXPATHLEN];
-	struct stat st;
-	char *cp;
-	int count;
-	int fd;
-
-	cp = strrchr(local, '/');
-	if (cp)
-		*cp = '\0';
-	if (stat(cp ? local : ".", &st) < 0) {
-		perror_reply(553, cp ? local : ".");
-		return (-1);
-	}
-	if (cp) {
-		/*
-		 * Let not overwrite dirname with counter suffix.
-		 * -4 is for /nn\0
-		 * In this extreme case dot won't be put in front of suffix.
-		 */
-		if (strlen(local) > sizeof(new) - 4) {
-			reply(553, "Pathname too long.");
-			return (-1);
-		}
-		*cp = '/';
-	}
-	/* -4 is for the .nn<null> we put on the end below */
-	(void) snprintf(new, sizeof(new) - 4, "%s", local);
-	cp = new + strlen(new);
-	/* 
-	 * Don't generate dotfile unless requested explicitly.
-	 * This covers the case when basename gets truncated off
-	 * by buffer size.
-	 */
-	if (cp > new && cp[-1] != '/')
-		*cp++ = '.';
-	for (count = 0; count < 100; count++) {
-		/* At count 0 try unmodified name */
-		if (count)
-			(void)sprintf(cp, "%d", count);
-		if ((fd = open(count ? new : local,
-		    O_RDWR | O_CREAT | O_EXCL, 0666)) >= 0) {
-			*name = count ? new : local;
-			return (fd);
-		}
-		if (errno != EEXIST) {
-			perror_reply(553, count ? new : local);
-			return (-1);
-		}
-	}
-	reply(452, "Unique file name cannot be created.");
-	return (-1);
-}
-
-/*
- * Format and send reply containing system error number.
- */
-void
-perror_reply(int code, char *string)
-{
-
-	reply(code, "%s: %s.", string, strerror(errno));
-}
-
-static char *onefile[] = {
-	"",
-	0
-};
-
-void
-send_file_list(char *whichf)
-{
-	struct stat st;
-	DIR *dirp = NULL;
-	struct dirent *dir;
-	FILE *dout = NULL;
-	char **dirlist, *dirname;
-	int simple = 0;
-	int freeglob = 0;
-	glob_t gl;
-
-	if (strpbrk(whichf, "~{[*?") != NULL) {
-		int flags = GLOB_BRACE|GLOB_NOCHECK|GLOB_TILDE;
-
-		memset(&gl, 0, sizeof(gl));
-		gl.gl_matchc = MAXGLOBARGS;
-		flags |= GLOB_LIMIT;
-		freeglob = 1;
-		if (glob(whichf, flags, 0, &gl)) {
-			reply(550, "No matching files found.");
-			goto out;
-		} else if (gl.gl_pathc == 0) {
-			errno = ENOENT;
-			perror_reply(550, whichf);
-			goto out;
-		}
-		dirlist = gl.gl_pathv;
-	} else {
-		onefile[0] = whichf;
-		dirlist = onefile;
-		simple = 1;
-	}
-
-	while ((dirname = *dirlist++)) {
-		if (stat(dirname, &st) < 0) {
-			/*
-			 * If user typed "ls -l", etc, and the client
-			 * used NLST, do what the user meant.
-			 */
-			if (dirname[0] == '-' && *dirlist == NULL &&
-			    dout == NULL)
-				retrieve(_PATH_LS " %s", dirname);
-			else
-				perror_reply(550, whichf);
-			goto out;
-		}
-
-		if (S_ISREG(st.st_mode)) {
-			if (dout == NULL) {
-				dout = dataconn("file list", -1, "w");
-				if (dout == NULL)
-					goto out;
-				STARTXFER;
-			}
-			START_UNSAFE;
-			fprintf(dout, "%s%s\n", dirname,
-				type == TYPE_A ? "\r" : "");
-			END_UNSAFE;
-			if (ferror(dout))
-				goto data_err;
-			byte_count += strlen(dirname) +
-				      (type == TYPE_A ? 2 : 1);
-			CHECKOOB(goto abrt);
-			continue;
-		} else if (!S_ISDIR(st.st_mode))
-			continue;
-
-		if ((dirp = opendir(dirname)) == NULL)
-			continue;
-
-		while ((dir = readdir(dirp)) != NULL) {
-			char nbuf[MAXPATHLEN];
-
-			CHECKOOB(goto abrt);
-
-			if (dir->d_name[0] == '.' && dir->d_namlen == 1)
-				continue;
-			if (dir->d_name[0] == '.' && dir->d_name[1] == '.' &&
-			    dir->d_namlen == 2)
-				continue;
-
-			snprintf(nbuf, sizeof(nbuf),
-				"%s/%s", dirname, dir->d_name);
-
-			/*
-			 * We have to do a stat to insure it's
-			 * not a directory or special file.
-			 */
-			if (simple || (stat(nbuf, &st) == 0 &&
-			    S_ISREG(st.st_mode))) {
-				if (dout == NULL) {
-					dout = dataconn("file list", -1, "w");
-					if (dout == NULL)
-						goto out;
-					STARTXFER;
-				}
-				START_UNSAFE;
-				if (nbuf[0] == '.' && nbuf[1] == '/')
-					fprintf(dout, "%s%s\n", &nbuf[2],
-						type == TYPE_A ? "\r" : "");
-				else
-					fprintf(dout, "%s%s\n", nbuf,
-						type == TYPE_A ? "\r" : "");
-				END_UNSAFE;
-				if (ferror(dout))
-					goto data_err;
-				byte_count += strlen(nbuf) +
-					      (type == TYPE_A ? 2 : 1);
-				CHECKOOB(goto abrt);
-			}
-		}
-		(void) closedir(dirp);
-		dirp = NULL;
-	}
-
-	if (dout == NULL)
-		reply(550, "No files found.");
-	else if (ferror(dout))
-data_err:	perror_reply(550, "Data connection");
-	else
-		reply(226, "Transfer complete.");
-out:
-	if (dout) {
-		ENDXFER;
-abrt:
-		(void) fclose(dout);
-		data = -1;
-		pdata = -1;
-	}
-	if (dirp)
-		(void) closedir(dirp);
-	if (freeglob) {
-		freeglob = 0;
-		globfree(&gl);
-	}
-}
-
-void
-reapchild(int signo)
-{
-	while (waitpid(-1, NULL, WNOHANG) > 0);
-}
-
-static void
-appendf(char **strp, char *fmt, ...)
-{
-	va_list ap;
-	char *ostr, *p;
-
-	va_start(ap, fmt);
-	vasprintf(&p, fmt, ap);
-	va_end(ap);
-	if (p == NULL)
-		fatalerror("Ran out of memory.");
-	if (*strp == NULL)
-		*strp = p;
-	else {
-		ostr = *strp;
-		asprintf(strp, "%s%s", ostr, p);
-		if (*strp == NULL)
-			fatalerror("Ran out of memory.");
-		free(ostr);
-	}
-}
-
-static void
-logcmd(char *cmd, char *file1, char *file2, off_t cnt)
-{
-	char *msg = NULL;
-	char wd[MAXPATHLEN + 1];
-
-	if (logging <= 1)
-		return;
-
-	if (getcwd(wd, sizeof(wd) - 1) == NULL)
-		strcpy(wd, strerror(errno));
-
-	appendf(&msg, "%s", cmd);
-	if (file1)
-		appendf(&msg, " %s", file1);
-	if (file2)
-		appendf(&msg, " %s", file2);
-	if (cnt >= 0)
-		appendf(&msg, " = %jd bytes", (intmax_t)cnt);
-	appendf(&msg, " (wd: %s", wd);
-	if (guest || dochroot)
-		appendf(&msg, "; chrooted");
-	appendf(&msg, ")");
-	syslog(LOG_INFO, "%s", msg);
-	free(msg);
-}
-
-static void
-logxfer(char *name, off_t size, time_t start)
-{
-	char buf[MAXPATHLEN + 1024];
-	char path[MAXPATHLEN + 1];
-	time_t now;
-
-	if (statfd >= 0) {
-		time(&now);
-		if (realpath(name, path) == NULL) {
-			syslog(LOG_NOTICE, "realpath failed on %s: %m", path);
-			return;
-		}
-		snprintf(buf, sizeof(buf), "%.20s!%s!%s!%s!%jd!%ld\n",
-			ctime(&now)+4, ident, remotehost,
-			path, (intmax_t)size,
-			(long)(now - start + (now == start)));
-		write(statfd, buf, strlen(buf));
-	}
-}
-
-static char *
-doublequote(char *s)
-{
-	int n;
-	char *p, *s2;
-
-	for (p = s, n = 0; *p; p++)
-		if (*p == '"')
-			n++;
-
-	if ((s2 = malloc(p - s + n + 1)) == NULL)
-		return (NULL);
-
-	for (p = s2; *s; s++, p++) {
-		if ((*p = *s) == '"')
-			*(++p) = '"';
-	}
-	*p = '\0';
-
-	return (s2);
-}
-
-/* setup server socket for specified address family */
-/* if af is PF_UNSPEC more than one socket may be returned */
-/* the returned list is dynamically allocated, so caller needs to free it */
-static int *
-socksetup(int af, char *bindname, const char *bindport)
-{
-	struct addrinfo hints, *res, *r;
-	int error, maxs, *s, *socks;
-	const int on = 1;
-
-	memset(&hints, 0, sizeof(hints));
-	hints.ai_flags = AI_PASSIVE;
-	hints.ai_family = af;
-	hints.ai_socktype = SOCK_STREAM;
-	error = getaddrinfo(bindname, bindport, &hints, &res);
-	if (error) {
-		syslog(LOG_ERR, "%s", gai_strerror(error));
-		if (error == EAI_SYSTEM)
-			syslog(LOG_ERR, "%s", strerror(errno));
-		return NULL;
-	}
-
-	/* Count max number of sockets we may open */
-	for (maxs = 0, r = res; r; r = r->ai_next, maxs++)
-		;
-	socks = malloc((maxs + 1) * sizeof(int));
-	if (!socks) {
-		freeaddrinfo(res);
-		syslog(LOG_ERR, "couldn't allocate memory for sockets");
-		return NULL;
-	}
-
-	*socks = 0;   /* num of sockets counter at start of array */
-	s = socks + 1;
-	for (r = res; r; r = r->ai_next) {
-		*s = socket(r->ai_family, r->ai_socktype, r->ai_protocol);
-		if (*s < 0) {
-			syslog(LOG_DEBUG, "control socket: %m");
-			continue;
-		}
-		if (setsockopt(*s, SOL_SOCKET, SO_REUSEADDR,
-		    &on, sizeof(on)) < 0)
-			syslog(LOG_WARNING,
-			    "control setsockopt (SO_REUSEADDR): %m");
-		if (r->ai_family == AF_INET6) {
-			if (setsockopt(*s, IPPROTO_IPV6, IPV6_V6ONLY,
-			    &on, sizeof(on)) < 0)
-				syslog(LOG_WARNING,
-				    "control setsockopt (IPV6_V6ONLY): %m");
-		}
-		if (bind(*s, r->ai_addr, r->ai_addrlen) < 0) {
-			syslog(LOG_DEBUG, "control bind: %m");
-			close(*s);
-			continue;
-		}
-		(*socks)++;
-		s++;
-	}
-
-	if (res)
-		freeaddrinfo(res);
-
-	if (*socks == 0) {
-		syslog(LOG_ERR, "control socket: Couldn't bind to any socket");
-		free(socks);
-		return NULL;
-	}
-	return(socks);
-}
diff --git a/libexec/ftpd/ftpusers b/libexec/ftpd/ftpusers
deleted file mode 100644
index 2e6f80a5968c..000000000000
--- a/libexec/ftpd/ftpusers
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# list of users disallowed any ftp access.
-# read by ftpd(8).
-root
-toor
-daemon
-operator
-bin
-tty
-kmem
-games
-news
-ntpd
-man
-sshd
-smmsp
-mailnull
-bind
-unbound
-proxy
-_pflogd
-_dhcp
-uucp
-pop
-auditdistd
-www
-hast
-nobody
diff --git a/libexec/ftpd/logwtmp.c b/libexec/ftpd/logwtmp.c
deleted file mode 100644
index 85db1f13419d..000000000000
--- a/libexec/ftpd/logwtmp.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1988, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <netinet/in.h>
-#include <arpa/inet.h>
-#include <sys/socket.h>
-
-#include <libutil.h>
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-#include <utmpx.h>
-#include "extern.h"
-
-void
-ftpd_logwtmp(char *id, char *user, struct sockaddr *addr)
-{
-	struct utmpx ut;
-
-	memset(&ut, 0, sizeof(ut));
-
-	if (user != NULL) {
-		/* Log in. */
-		ut.ut_type = USER_PROCESS;
-		(void)strncpy(ut.ut_user, user, sizeof(ut.ut_user));
-		if (addr != NULL)
-			realhostname_sa(ut.ut_host, sizeof(ut.ut_host),
-			    addr, addr->sa_len);
-	} else {
-		/* Log out. */
-		ut.ut_type = DEAD_PROCESS;
-	}
-
-	ut.ut_pid = getpid();
-	gettimeofday(&ut.ut_tv, NULL);
-	(void)strncpy(ut.ut_id, id, sizeof(ut.ut_id));
-	(void)strncpy(ut.ut_line, "ftpd", sizeof(ut.ut_line));
-
-	pututxline(&ut);
-}
diff --git a/libexec/ftpd/pathnames.h b/libexec/ftpd/pathnames.h
deleted file mode 100644
index 1ff753123b1c..000000000000
--- a/libexec/ftpd/pathnames.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1989, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <paths.h>
-
-#define	_PATH_FTPCHROOT		"/etc/ftpchroot"
-#define	_PATH_FTPWELCOME	"/etc/ftpwelcome"
-#define	_PATH_FTPLOGINMESG	"/etc/ftpmotd"
-#define	_PATH_FTPHOSTS		"/etc/ftphosts"
-#define	_PATH_FTPDSTATFILE	"/var/log/ftpd"
-#define	_PATH_LS		"/bin/ls"
diff --git a/libexec/ftpd/popen.c b/libexec/ftpd/popen.c
deleted file mode 100644
index 5f48356a376f..000000000000
--- a/libexec/ftpd/popen.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Copyright (c) 1988, 1993, 1994
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software written by Ken Arnold and
- * published in UNIX Review, Vol. 6, No. 8.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/types.h>
-#include <sys/wait.h>
-#include <netinet/in.h>
-
-#include <errno.h>
-#include <glob.h>
-#include <signal.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "extern.h"
-#include "pathnames.h"
-#include <syslog.h>
-#include <time.h>
-
-#define	MAXUSRARGS	100
-#define	MAXGLOBARGS	1000
-
-/*
- * Special version of popen which avoids call to shell.  This ensures no one
- * may create a pipe to a hidden program as a side effect of a list or dir
- * command.
- */
-static int *pids;
-static int fds;
-
-FILE *
-ftpd_popen(char *program, char *type)
-{
-	char *cp;
-	FILE *iop;
-	int argc, gargc, pdes[2], pid;
-	char **pop, *argv[MAXUSRARGS], *gargv[MAXGLOBARGS];
-
-	if (((*type != 'r') && (*type != 'w')) || type[1])
-		return (NULL);
-
-	if (!pids) {
-		if ((fds = getdtablesize()) <= 0)
-			return (NULL);
-		if ((pids = calloc(fds, sizeof(int))) == NULL)
-			return (NULL);
-	}
-	if (pipe(pdes) < 0)
-		return (NULL);
-
-	/* break up string into pieces */
-	for (argc = 0, cp = program; argc < MAXUSRARGS; cp = NULL) {
-		if (!(argv[argc++] = strtok(cp, " \t\n")))
-			break;
-	}
-	argv[argc - 1] = NULL;
-
-	/* glob each piece */
-	gargv[0] = argv[0];
-	for (gargc = argc = 1; argv[argc] && gargc < (MAXGLOBARGS-1); argc++) {
-		glob_t gl;
-		int flags = GLOB_BRACE|GLOB_NOCHECK|GLOB_TILDE;
-
-		memset(&gl, 0, sizeof(gl));
-		gl.gl_matchc = MAXGLOBARGS;
-		flags |= GLOB_LIMIT;
-		if (glob(argv[argc], flags, NULL, &gl))
-			gargv[gargc++] = strdup(argv[argc]);
-		else if (gl.gl_pathc > 0) {
-			for (pop = gl.gl_pathv; *pop && gargc < (MAXGLOBARGS-1);
-			     pop++)
-				gargv[gargc++] = strdup(*pop);
-		}
-		globfree(&gl);
-	}
-	gargv[gargc] = NULL;
-
-	iop = NULL;
-	fflush(NULL);
-	pid = (strcmp(gargv[0], _PATH_LS) == 0) ? fork() : vfork();
-	switch(pid) {
-	case -1:			/* error */
-		(void)close(pdes[0]);
-		(void)close(pdes[1]);
-		goto pfree;
-		/* NOTREACHED */
-	case 0:				/* child */
-		if (*type == 'r') {
-			if (pdes[1] != STDOUT_FILENO) {
-				dup2(pdes[1], STDOUT_FILENO);
-				(void)close(pdes[1]);
-			}
-			dup2(STDOUT_FILENO, STDERR_FILENO); /* stderr too! */
-			(void)close(pdes[0]);
-		} else {
-			if (pdes[0] != STDIN_FILENO) {
-				dup2(pdes[0], STDIN_FILENO);
-				(void)close(pdes[0]);
-			}
-			(void)close(pdes[1]);
-		}
-		/* Drop privileges before proceeding */
-		if (getuid() != geteuid() && setuid(geteuid()) < 0)
-			_exit(1);
-		if (strcmp(gargv[0], _PATH_LS) == 0) {
-			/* Reset getopt for ls_main() */
-			optreset = optind = optopt = 1;
-			/* Close syslogging to remove pwd.db missing msgs */
-			closelog();
-			/* Trigger to sense new /etc/localtime after chroot */
-			if (getenv("TZ") == NULL) {
-				setenv("TZ", "", 0);
-				tzset();
-				unsetenv("TZ");
-				tzset();
-			}
-			exit(ls_main(gargc, gargv));
-		}
-		execv(gargv[0], gargv);
-		_exit(1);
-	}
-	/* parent; assume fdopen can't fail...  */
-	if (*type == 'r') {
-		iop = fdopen(pdes[0], type);
-		(void)close(pdes[1]);
-	} else {
-		iop = fdopen(pdes[1], type);
-		(void)close(pdes[0]);
-	}
-	pids[fileno(iop)] = pid;
-
-pfree:	for (argc = 1; gargv[argc] != NULL; argc++)
-		free(gargv[argc]);
-
-	return (iop);
-}
-
-int
-ftpd_pclose(FILE *iop)
-{
-	int fdes, omask, status;
-	pid_t pid;
-
-	/*
-	 * pclose returns -1 if stream is not associated with a
-	 * `popened' command, or, if already `pclosed'.
-	 */
-	if (pids == NULL || pids[fdes = fileno(iop)] == 0)
-		return (-1);
-	(void)fclose(iop);
-	omask = sigblock(sigmask(SIGINT)|sigmask(SIGQUIT)|sigmask(SIGHUP));
-	while ((pid = waitpid(pids[fdes], &status, 0)) < 0 && errno == EINTR)
-		continue;
-	(void)sigsetmask(omask);
-	pids[fdes] = 0;
-	if (pid < 0)
-		return (pid);
-	if (WIFEXITED(status))
-		return (WEXITSTATUS(status));
-	return (1);
-}
diff --git a/libexec/kgdb/Makefile b/libexec/kgdb/Makefile
deleted file mode 100644
index f6b255ab4f60..000000000000
--- a/libexec/kgdb/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-FILESDIR?= /usr/libexec/kgdb
-
-FILES= acttrace.py
-
-.include <bsd.prog.mk>
diff --git a/libexec/nuageinit/nuageinit b/libexec/nuageinit/nuageinit
index 29340a3d91ea..f29fa8ba1bac 100755
--- a/libexec/nuageinit/nuageinit
+++ b/libexec/nuageinit/nuageinit
@@ -6,6 +6,7 @@
 -- Copyright(c) 2025 Jesús Daniel Colmenares Oviedo <dtxdf@FreeBSD.org>
 
 local nuage = require("nuage")
+local lfs = require("lfs")
 local ucl = require("ucl")
 local yaml = require("lyaml")
 
diff --git a/libexec/rc/rc.conf b/libexec/rc/rc.conf
index 1220d060232d..c776a815003c 100644
--- a/libexec/rc/rc.conf
+++ b/libexec/rc/rc.conf
@@ -369,9 +369,6 @@ sshd_enable="NO"		# Enable sshd
 sshd_oomprotect="YES"		# Don't kill sshd when swap space is exhausted.
 sshd_program="/usr/sbin/sshd"	# path to sshd, if you want a different one.
 sshd_flags=""			# Additional flags for sshd.
-ftpd_enable="NO"		# Enable stand-alone ftpd.
-ftpd_program="/usr/libexec/ftpd" # Path to ftpd, if you want a different one.
-ftpd_flags=""			# Additional flags to stand-alone ftpd.
 
 ### Network daemon (NFS): All need rpcbind_enable="YES" ###
 autofs_enable="NO"		# Run autofs daemons.
@@ -503,6 +500,9 @@ netwait_enable="NO"		# Enable rc.d/netwait (or NO)
 netwait_timeout="60"		# Total number of seconds to perform pings.
 #netwait_if=""			# Wait for active link on each intf in this list.
 netwait_if_timeout="30"		# Total number of seconds to monitor link state.
+netwait_dad="NO"		# Wait for DAD to complete
+netwait_dad_timeout=""		# Total number of seconds to wait for DAD, zero
+				# or unset to autodetect
 
 ### Miscellaneous network options: ###
 icmp_bmcastecho="NO"	# respond to broadcast ping packets
diff --git a/libexec/rc/rc.d/Makefile b/libexec/rc/rc.d/Makefile
index 370254285efb..03f0933533ca 100644
--- a/libexec/rc/rc.d/Makefile
+++ b/libexec/rc/rc.d/Makefile
@@ -75,7 +75,6 @@ CONFS=	DAEMON \
 	ugidfw \
 	var \
 	var_run \
-	virtual_oss \
 	watchdogd
 
 CONFGROUPS+=		DEVD
@@ -216,10 +215,10 @@ CCD=		ccd
 CCDPACKAGE=	ccdconfig
 .endif
 
-.if ${MK_FTP} != "no"
-CONFGROUPS+=	FTPD
-FTPD=		ftpd
-FTPDPACKAGE=	ftpd
+.if ${MK_CUSE} != "no"
+CONFGROUPS+=	VOSS
+VOSS=		virtual_oss
+VOSSPACKAGE=	sound
 .endif
 
 .if ${MK_KERBEROS_SUPPORT} != "no"
diff --git a/libexec/rc/rc.d/ftpd b/libexec/rc/rc.d/ftpd
deleted file mode 100755
index 5a4fd49e36f1..000000000000
--- a/libexec/rc/rc.d/ftpd
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-#
-#
-
-# PROVIDE: ftpd
-# REQUIRE: LOGIN FILESYSTEMS
-# KEYWORD: shutdown
-
-. /etc/rc.subr
-
-name="ftpd"
-desc="Internet File Transfer Protocol daemon"
-rcvar="ftpd_enable"
-command="/usr/libexec/${name}"
-command_args="-D"
-pidfile="/var/run/${name}.pid"
-
-: ${ftpd_svcj_options:="net_basic"}
-
-load_rc_config $name
-
-run_rc_command "$1"
diff --git a/libexec/rc/rc.d/netwait b/libexec/rc/rc.d/netwait
index 3f374806d97c..05874552cf1c 100755
--- a/libexec/rc/rc.d/netwait
+++ b/libexec/rc/rc.d/netwait
@@ -2,12 +2,14 @@
 #
 # PROVIDE: netwait
 # REQUIRE: devd ipfw pf routing
-# KEYWORD: nojail
 #
-# The netwait script helps handle two situations:
+# The netwait script helps handle three situations:
 #  - Systems with USB or other late-attaching network hardware which
 #    is initialized by devd events.  The script waits for all the
 #    interfaces named in the netwait_if list to appear.
+#  - Systems with IPv6 addresses, especially jails, where we need to
+#    wait for DAD to complete before starting daemons, as they will
+#    otherwise fail to bind to IN6ADDR_ANY.
 #  - Systems with statically-configured IP addresses in rc.conf(5).
 #    The IP addresses in the netwait_ip list are pinged.  The script
 #    waits for any single IP in the list to respond to the ping.  If your
@@ -29,28 +31,38 @@ netwait_start()
 {
 	local ip rc count output link wait_if got_if any_error
 
-	if [ -z "${netwait_if}" ] && [ -z "${netwait_ip}" ]; then
-		err 1 "No interface or IP addresses listed, nothing to wait for"
+	if [ -z "${netwait_if}" ] && [ -z "${netwait_ip}" ] &&
+	   ! checkyesno netwait_dad ; then
+		err 1 "Nothing to wait for"
 	fi
 
-	if [ ${netwait_timeout} -lt 1 ]; then
+	if ! [ "${netwait_if_timeout:=0}" -ge 1 ]; then
+		err 1 "netwait_if_timeout must be >= 1"
+	fi
+	if ! check_kern_features inet6; then
+		netwait_dad="NO"
+	elif ! [ "${netwait_dad_timeout:=0}" -ge 1 ]; then
+		netwait_dad_timeout=$(($(sysctl -n net.inet6.ip6.dad_count)+1))
+	fi
+	if ! [ "${netwait_timeout:=0}" -ge 1 ]; then
 		err 1 "netwait_timeout must be >= 1"
 	fi
 
+	any_error=false
+
 	if [ -n "${netwait_if}" ]; then
-		any_error=0
 		for wait_if in ${netwait_if}; do
 			echo -n "Waiting for ${wait_if}"
 			link=""
-			got_if=0
+			got_if=false
 			count=1
-			# Handle SIGINT (Ctrl-C); force abort of while() loop
+			# Handle SIGINT (Ctrl-C); force abort of while loop
 			trap break SIGINT
 			while [ ${count} -le ${netwait_if_timeout} ]; do
 				if output=`/sbin/ifconfig ${wait_if} 2>/dev/null`; then
-					if [ ${got_if} -eq 0 ]; then
+					if ! ${got_if}; then
 						echo -n ", interface present"
-						got_if=1
+						got_if=true
 					fi
 					link=`expr "${output}" : '.*[[:blank:]]status: \(no carrier\)'`
 					if [ -z "${link}" ]; then
@@ -63,22 +75,45 @@ netwait_start()
 			done
 			# Restore default SIGINT handler
 			trap - SIGINT
-			if [ ${got_if} -eq 0 ]; then
+			if ! ${got_if}; then
 				echo ", wait failed: interface never appeared."
-				any_error=1
+				any_error=true
 			elif [ -n "${link}" ]; then
 				echo ", wait failed: interface still has no link."
-				any_error=1
+				any_error=true
 			fi
 		done
-		if [ ${any_error} -eq 1 ]; then
-		    warn "Continuing with startup, but be aware you may not have "
-		    warn "a fully functional networking layer at this point."
-		fi
 	fi
 	
+	if checkyesno netwait_dad; then
+		got_dad=false
+		# Handle SIGINT (Ctrl-C); force abort of while loop
+		trap break SIGINT
+
+		echo -n "Waiting for DAD to complete"
+		count=1
+		while [ ${count} -le ${netwait_dad_timeout} ]; do
+			if ! ifconfig | grep -q 'inet6.*tentative'; then
+				echo ', done.'
+				got_dad=true
+				break
+			fi
+			sleep 1
+			count=$((count+1))
+		done
+
+		# Restore default SIGINT handler
+		trap - SIGINT
+
+		if ! ${got_dad}; then
+			echo ', timed out.'
+			any_error=true
+		fi
+	fi
+
 	if [ -n "${netwait_ip}" ]; then
-		# Handle SIGINT (Ctrl-C); force abort of for() loop
+		got_ip=false
+		# Handle SIGINT (Ctrl-C); force abort of for loop
 		trap break SIGINT
 
 		for ip in ${netwait_ip}; do
@@ -90,11 +125,9 @@ netwait_start()
 				rc=$?
 
 				if [ $rc -eq 0 ]; then
-					# Restore default SIGINT handler
-					trap - SIGINT
-
 					echo ', got response.'
-					return
+					got_ip=false
+					break 2
 				fi
 				count=$((count+1))
 			done
@@ -104,10 +137,15 @@ netwait_start()
 		# Restore default SIGINT handler
 		trap - SIGINT
 
-		warn "Exhausted IP list.  Continuing with startup, but be aware you may"
-		warn "not have a fully functional networking layer at this point."
+		if ! ${got_ip}; then
+			any_error=true
+		fi
 	fi
 
+	if ${any_error}; then
+		warn "Continuing with startup, but be aware you may not have "
+		warn "a fully functional networking layer at this point."
+	fi
 }
 
 load_rc_config $name
diff --git a/release/Makefile b/release/Makefile
index 82617c1f4dd7..12f5114f8b22 100644
--- a/release/Makefile
+++ b/release/Makefile
@@ -75,14 +75,22 @@ VOLUME_LABEL=	${REVISION:C/[.-]/_/g}_${BRANCH:C/[.-]/_/g}_${TARGET_ARCH}
 .endfor
 .endif
 
+.if !defined(NOPKGBASE) || empty(NOPKGBASE)
+PKGBASE_REPO_DIR= pkgbase-repo-dir
+WSTAGEDIR!=	${IMAKE} -f Makefile.inc1 -C ${WORLDDIR} -V WSTAGEDIR
+PKG_ABI_FILE=	${WSTAGEDIR}/usr/bin/uname
+PKG_ABI=	$$(${PKG_CMD} -o ABI_FILE=${PKG_ABI_FILE} config ABI)
+.endif
+
 .if ${.MAKE.OS} == "FreeBSD"
 # For installing packages into the release media.
 PKG_ENV+=	INSTALL_AS_USER=yes
 PKG_ENV+=	ASSUME_ALWAYS_YES=yes
 PKG_ARGS+=	-o METALOG=METALOG
+PKG_ARGS+=	-o ABI=${PKG_ABI}
 PKG_ARGS+=	-r ${.TARGET}
 PKG_REPO_ARGS=	-o REPOS_DIR=${.CURDIR}/pkg_repos
-PKGBASE_REPO_ARGS=-o REPOS_DIR=${.OBJDIR}/pkgbase-repo-conf
+PKGBASE_REPO_ARGS=-o REPOS_DIR=${.OBJDIR}/pkgbase-repo-dir
 # Pass -f to make sure pkg writes to the METALOG even if the package
 # is already installed from a previous build
 PKG_INSTALL=	env ${PKG_ENV} ${PKG_CMD} ${PKG_ARGS} ${PKG_REPO_ARGS} install -f
@@ -108,7 +116,10 @@ DISTRIBUTIONS+= ports.txz
 DISTRIBUTIONS+= src.txz
 .endif
 
-RELEASE_TARGETS= ftp
+RELEASE_TARGETS=
+.if !defined(NODISTSETS) || empty(NODISTSETS)
+RELEASE_TARGETS+= ftp
+.endif
 IMAGES=
 .if exists(${.CURDIR}/${TARGET}/mkisoimages.sh)
 RELEASE_TARGETS+= cdrom
@@ -124,6 +135,9 @@ RELEASE_TARGETS+= mini-memstick.img
 IMAGES+=	memstick.img
 IMAGES+=	mini-memstick.img
 .endif
+.if !defined(NOPKGBASE) || empty(NOPKGBASE)
+RELEASE_TARGETS+= pkgbase-repo.tar
+.endif
 
 CLEANFILES=	packagesystem *.txz MANIFEST release ${IMAGES}
 .if defined(WITH_COMPRESSED_IMAGES) && !empty(WITH_COMPRESSED_IMAGES)
@@ -134,7 +148,7 @@ CLEANFILES+=	${I}.xz
 .if defined(WITH_DVD) && !empty(WITH_DVD)
 CLEANFILES+=	pkg-stage
 .endif
-CLEANDIRS=	dist pkgdb-dvd pkgdb-disc1 pkgbase-repo pkgbase-repo-dir ftp disc1 disc1-disc1 disc1-memstick bootonly bootonly-bootonly bootonly-memstick dvd
+CLEANDIRS=	dist pkgdb-dvd pkgdb-disc1 pkgbase-repo pkgbase-repo-dir ftp disc1 disc1-disc1 disc1-memstick bootonly bootonly-bootonly bootonly-memstick dvd pkgbase-repo.tar
 beforeclean:
 	chflags -R noschg .
 .include <bsd.obj.mk>
@@ -188,17 +202,15 @@ packagesystem: ${DISTRIBUTIONS}
 	sh ${.CURDIR}/scripts/make-manifest.sh $$(ls *.txz | grep -v container) > MANIFEST
 	touch ${.TARGET}
 
-.if !defined(NODISTSETS)
+.if !defined(NODISTSETS) || empty(NODISTSETS)
 disc1: packagesystem
 bootonly: packagesystem
 dvd: packagesystem
 .endif
-
 .if !defined(NOPKGBASE) || empty(NOPKGBASE)
-PKGBASE_REPO_DIR= pkgbase-repo-dir
-WSTAGEDIR!=	${IMAKE} -f Makefile.inc1 -C ${WORLDDIR} -V WSTAGEDIR
-PKG_ABI_FILE=	${WSTAGEDIR}/usr/bin/uname
-PKG_ABI=	$$(${PKG_CMD} -o ABI_FILE=${PKG_ABI_FILE} config ABI)
+disc1: pkgbase-repo-dir
+bootonly: pkgbase-repo-dir
+dvd: pkgbase-repo-dir
 .endif
 
 pkgbase-repo:
@@ -207,13 +219,16 @@ pkgbase-repo:
 	( ${IMAKE} -C ${WORLDDIR} packages REPODIR=${.OBJDIR}/pkgbase-repo \
 	    INCLUDE_PKG_IN_PKGBASE_REPO=YES BOOTSTRAP_PKG_FROM_PORTS=YES )
 
+pkgbase-repo.tar: pkgbase-repo
+	tar -cf pkgbase-repo.tar -C pkgbase-repo .
+
 pkgbase-repo-dir: pkgbase-repo
 	mkdir -p pkgbase-repo-dir
 	printf "FreeBSD-base: { url: "file://%s", enabled: yes }" \
 	    ${.OBJDIR}/pkgbase-repo/${PKG_ABI}/latest \
 	    > pkgbase-repo-dir/FreeBSD-base.conf
 
-disc1: ${PKGBASE_REPO_DIR}
+disc1:
 # Install system
 	mkdir -p ${.TARGET}
 	( cd ${WORLDDIR} && ${IMAKE} installworld installkernel distribution \
@@ -236,7 +251,7 @@ disc1: ${PKGBASE_REPO_DIR}
 	    mtree -C -k type,mode,link,size | \
 	    sed 's|^\.|./usr/freebsd-packages|g' >> ${.TARGET}/METALOG
 .endif
-.if !defined(NODISTSETS)
+.if !defined(NODISTSETS) || empty(NODISTSETS)
 	# Copy MANIFEST to provide legacy dist checksums in both modes
 	mkdir -p ${.TARGET}/usr/freebsd-dist
 	echo "./usr/freebsd-dist type=dir uname=root gname=wheel mode=0755" >> ${.TARGET}/METALOG
@@ -289,7 +304,7 @@ bootonly:
 	    MK_TOOLCHAIN=no \
 	    MK_RESCUE=no MK_DICT=no \
 	    MK_KERNEL_SYMBOLS=no MK_TESTS=no MK_DEBUG_FILES=no)
-.if !defined(NODISTSETS)
+.if !defined(NODISTSETS) || empty(NODISTSETS)
 # Copy manifest only (no distfiles) to get checksums
 	mkdir -p ${.TARGET}/usr/freebsd-dist
 	cp MANIFEST ${.TARGET}/usr/freebsd-dist
@@ -297,7 +312,12 @@ bootonly:
 	echo "./usr/freebsd-dist/MANIFEST type=file uname=root gname=wheel mode=0644" >> ${.TARGET}/METALOG
 .endif
 .if ${.MAKE.OS} == "FreeBSD" && (!defined(NOPKG) || empty(NOPKG))
-	${PKG_INSTALL} pkg || true
+.if !defined(NOPKGBASE) || empty(NOPKGBASE)
+	${PKGBASE_INSTALL} pkg
+	${PKGBASE_CLEAN}
+.else
+	${PKG_INSTALL} pkg
+.endif
 	${PKG_INSTALL} wifi-firmware-iwlwifi-kmod wifi-firmware-rtw88-kmod || true
 	${PKG_CLEAN} || true
 .endif
@@ -317,7 +337,7 @@ bootonly:
 	echo "./boot/loader.conf type=file uname=root gname=wheel mode=0644" >> ${.TARGET}/METALOG
 	echo "./etc/rc.local type=file uname=root gname=wheel mode=0644" >> ${.TARGET}/METALOG
 
-dvd: ${PKGBASE_REPO_DIR}
+dvd:
 # Install system
 	mkdir -p ${.TARGET}
 	( cd ${WORLDDIR} && ${IMAKE} installworld installkernel distribution \
@@ -336,7 +356,7 @@ dvd: ${PKGBASE_REPO_DIR}
 	    mtree -C -k type,mode,link,size | \
 	    sed 's|^\.|./usr/freebsd-packages|g' >> ${.TARGET}/METALOG
 .endif
-.if !defined(NODISTSETS)
+.if !defined(NODISTSETS) || empty(NODISTSETS)
 	# Copy MANIFEST to provide legacy dist checksums in both modes
 	mkdir -p ${.TARGET}/usr/freebsd-dist
 	echo "./usr/freebsd-dist type=dir uname=root gname=wheel mode=0755" >> ${.TARGET}/METALOG
@@ -438,7 +458,9 @@ release-install:
 .if defined(DESTDIR) && !empty(DESTDIR)
 	mkdir -p ${DESTDIR}
 .endif
+.if !defined(NODISTSETS) || empty(NODISTSETS)
 	cp -a ftp ${DESTDIR}/
+.endif
 .if !empty(IMAGES)
 .for I in ${IMAGES}
 	cp -p ${I} ${DESTDIR}/${OSRELEASE}-${I}
@@ -449,6 +471,12 @@ release-install:
 	( cd ${DESTDIR} && sha512 ${OSRELEASE}* > ${DESTDIR}/CHECKSUM.SHA512 )
 	( cd ${DESTDIR} && sha256 ${OSRELEASE}* > ${DESTDIR}/CHECKSUM.SHA256 )
 .endif
+.if !defined (NOPKGBASE) || empty(NOPKGBASE)
+	mkdir -p ${DESTDIR}/pkgbase
+	cp -p pkgbase-repo.tar ${DESTDIR}/pkgbase/
+	( cd ${DESTDIR}/pkgbase && sha256 pkgbase-repo.tar > CHECKSUM.SHA256 )
+	( cd ${DESTDIR}/pkgbase && sha512 pkgbase-repo.tar > CHECKSUM.SHA512 )
+.endif
 
 .include "${.CURDIR}/Makefile.inc1"
 .include "${.CURDIR}/Makefile.vm"
diff --git a/release/Makefile.azure b/release/Makefile.azure
index 577221ee3899..09dcde6af636 100644
--- a/release/Makefile.azure
+++ b/release/Makefile.azure
@@ -39,7 +39,7 @@ azure-check-depends:
 .endif
 
 .for _FS in ${AZURE_FSLIST}
-AZURE_IMG_${_FS}=	${.OBJDIR}/azure.${_FS}.vhdf
+AZURE_IMG_${_FS}=	${.OBJDIR}/azure.${_FS}.vhd
 AZURE_TARGET_${_FS}=	${OSRELEASE}-${_FS}${SNAPSHOT_DATE}
 
 azure-do-upload-${_FS}:
diff --git a/release/Makefile.mirrors b/release/Makefile.mirrors
index 5e65bfbe8b3f..ed9420e926ce 100644
--- a/release/Makefile.mirrors
+++ b/release/Makefile.mirrors
@@ -63,6 +63,13 @@ STAGE_TARGETS+=		oci-images-stage
 OCI_DIR=		${TLD}/OCI-IMAGES/${REVISION}-${BRANCH}/${TARGET_ARCH}
 .endif
 
+.if !defined(EMBEDDED) || empty(EMBEDDED)
+.if !defined(NOPKGBASE) || empty(NOPKGBASE)
+STAGE_TARGETS+=		pkgbase-repo-stage
+PKGBASE_DIR=		${TLD}/PKGBASE-REPOS/${REVISION}-${BRANCH}/${TARGET_ARCH}
+.endif
+.endif
+
 CLEANFILES+=		${STAGE_TARGETS}
 CHECKSUM_FILES?=	SHA512 SHA256
 SNAP_SUFFIX!=		echo ${_SNAP_SUFFIX:S,^-,,1} | tr -d ' '
@@ -366,5 +373,48 @@ oci-images-stage:
 . endfor
 .endif
 
+pkgbase-repo-stage:
+	mkdir -p ${PKGBASE_DIR}
+.if defined(SNAPSHOT) && !empty(SNAPSHOT)
+. if exists(${PKGBASE_DIR}/Latest)
+	rm -rf ${PKGBASE_DIR}/Latest
+. endif
+	mkdir -p ${PKGBASE_DIR}/Latest
+	mkdir -p ${PKGBASE_DIR}/${BUILDDATE}
+	cd ${RELEASEDIR}/pkgbase && \
+		mv pkgbase-repo.tar ${OSRELEASE}-pkgbase-repo-${SNAP_SUFFIX}.tar
+	cp -p ${RELEASEDIR}/pkgbase/${OSRELEASE}-pkgbase-repo-${SNAP_SUFFIX}.tar \
+		${PKGBASE_DIR}/${BUILDDATE}/${OSRELEASE}-pkgbase-repo-${SNAP_SUFFIX}.tar
+	cd ${PKGBASE_DIR}/Latest && \
+		ln -s ../${BUILDDATE}/${OSRELEASE}-pkgbase-repo-${SNAP_SUFFIX}.tar \
+		${OSRELEASE}-pkgbase-repo.tar
+	cd ${RELEASEDIR}/pkgbase && rm -f CHECKSUM.*
+. for CHECKSUM in ${CHECKSUM_FILES}
+	cd ${RELEASEDIR}/pkgbase && \
+		${CHECKSUM:tl} ${OSRELEASE}-pkgbase-repo-*.tar > CHECKSUM.${CHECKSUM}-${SNAP_SUFFIX}
+	cp -p ${RELEASEDIR}/pkgbase/CHECKSUM.${CHECKSUM}-${SNAP_SUFFIX} \
+		${PKGBASE_DIR}/${BUILDDATE}/CHECKSUM.${CHECKSUM}-${SNAP_SUFFIX}
+	cd ${PKGBASE_DIR}/Latest && \
+		ln -s ../${BUILDDATE}/CHECKSUM.${CHECKSUM}-${SNAP_SUFFIX} \
+		CHECKSUM.${CHECKSUM}
+. endfor
+.else # not snapshot
+. if exists(${PKGBASE_DIR}/Latest)
+	rm -rf ${PKGBASE_DIR}/Latest
+. endif
+	mkdir -p ${PKGBASE_DIR}/Latest
+	cd ${RELEASEDIR}/pkgbase && \
+		mv pkgbase-repo.tar ${OSRELEASE}-pkgbase-repo.tar
+	cp -p ${RELEASEDIR}/pkgbase/${OSRELEASE}-pkgbase-repo.tar \
+		${PKGBASE_DIR}/Latest/${OSRELEASE}-pkgbase-repo.tar
+. endfor
+. for CHECKSUM in ${CHECKSUM_FILES}
+	cd ${RELEASEDIR}/pkgbase && \
+		${CHECKSUM:tl} ${OSRELEASE}-pkgbase-repo.tar > CHECKSUM.${CHECKSUM}
+	cp -p ${RELEASEDIR}/pkgbase/CHECKSUM.${CHECKSUM} \
+		${PKGBASE_DIR}/Latest/CHECKSUM.${CHECKSUM}
+. endfor
+.endif
+
 ftp-stage:	remove-old-bits ${STAGE_TARGETS}
 
diff --git a/release/Makefile.vm b/release/Makefile.vm
index eafd1d6abf71..336e8fc82299 100644
--- a/release/Makefile.vm
+++ b/release/Makefile.vm
@@ -134,6 +134,7 @@ cw-${_CW:tl}-${_FS}-${_FMT}: ${QEMUTGT} ${PKGBASE_REPO_DIR}
 		${WITHOUT_QEMU:DWITHOUT_QEMU=true} \
 		${NO_ROOT:DNO_ROOT=true} \
 		PKG_CMD=${PKG_CMD:Upkg} \
+		PKG_ABI=${PKG_ABI} \
 		PKG_REPOS_DIR=${PKG_REPOS_DIR:U${.OBJDIR}/${.TARGET}/etc/pkg} \
 		PKG_REPO_NAME=${PKG_REPO_NAME:UFreeBSD-ports} \
 		PKG_INSTALL_EPOCH=${PKG_INSTALL_EPOCH:U${GITEPOCH}} \
@@ -192,6 +193,7 @@ vm-image:	${QEMUTGT} ${PKGBASE_REPO_DIR}
 		${WITHOUT_QEMU:DWITHOUT_QEMU=true} \
 		${NO_ROOT:DNO_ROOT=true} \
 		PKG_CMD=${PKG_CMD:Upkg} \
+		PKG_ABI=${PKG_ABI} \
 		PKG_REPOS_DIR=${PKG_REPOS_DIR:U${.OBJDIR}/${.TARGET}-${FORMAT}-${FS}/etc/pkg} \
 		PKG_REPO_NAME=${PKG_REPO_NAME:UFreeBSD-ports} \
 		PKG_INSTALL_EPOCH=${PKG_INSTALL_EPOCH:U${GITEPOCH}} \
diff --git a/release/packages/create-sets.sh b/release/packages/create-sets.sh
index 8c564ecfeb92..3780e8ee46c6 100755
--- a/release/packages/create-sets.sh
+++ b/release/packages/create-sets.sh
@@ -1,4 +1,20 @@
 #! /bin/sh
+#
+# SPDX-License-Identifier: ISC
+#
+# Copyright (c) 2025 Lexi Winter <ivy@FreeBSD.org>
+#
+# Permission to use, copy, modify, and distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
 # Generate metapackage sets.  We do this by examining the annotations field
 # of the packages we previously built.
@@ -17,6 +33,10 @@ repodir="$1"; shift
 # generate-set-ucl.lua.
 UCL_VARS="$@"
 
+# Nothing is explicitly added to set-base, so it wouldn't get built unless
+# we list it here.
+SETS="base base-dbg base-jail base-jail-dbg"
+
 for pkg in "$repodir"/*.pkg; do
 	# If the package name doesn't containing a '-', then it's
 	# probably data.pkg or packagesite.pkg, which are not real
diff --git a/release/packages/generate-set-ucl.lua b/release/packages/generate-set-ucl.lua
index b1b70053b02a..3c8474bf8e68 100755
--- a/release/packages/generate-set-ucl.lua
+++ b/release/packages/generate-set-ucl.lua
@@ -1,7 +1,7 @@
 #!/usr/libexec/flua
 
 --[[ usage:
-generare-set-ucl.lua <template> [<variablename> <variablevalue>]
+generate-set-ucl.lua <template> [<variablename> <variablevalue>]
 
 Generate the UCL for a set metapackage.  The variables provided will be
 substituted as UCL variables.
diff --git a/release/packages/generate-ucl.lua b/release/packages/generate-ucl.lua
index ea3743894740..c61cbb251d8b 100755
--- a/release/packages/generate-ucl.lua
+++ b/release/packages/generate-ucl.lua
@@ -1,7 +1,7 @@
 #!/usr/libexec/flua
 
 --[[ usage:
-generare-ucl.lua [<variablename> <variablevalue>]... <sourceucl> <destucl>
+generate-ucl.lua [<variablename> <variablevalue>]... <sourceucl> <destucl>
 
 Build a package's UCL configuration by loading the template UCL file
 <sourceucl>, replacing any $VARIABLES in the UCL based on the provided
diff --git a/release/packages/sets/base-jail.ucl b/release/packages/sets/base-jail.ucl
index e6c52349d3cb..d1dc17bc9860 100644
--- a/release/packages/sets/base-jail.ucl
+++ b/release/packages/sets/base-jail.ucl
@@ -16,7 +16,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-comment = "Base jail system (metapackage)"
+comment = "Base system for jails (metapackage)"
 
 vital = true
 
@@ -30,6 +30,10 @@ deps {
 		version = "${VERSION}"
 		origin = "base"
 	},
+	"set-optional-jail" {
+		version = "${VERSION}"
+		origin = "base"
+	},
 	"set-devel" {
 		version = "${VERSION}"
 		origin = "base"
diff --git a/release/packages/sets/base.ucl b/release/packages/sets/base.ucl
index 7b86450ae5b2..823e2342fab8 100644
--- a/release/packages/sets/base.ucl
+++ b/release/packages/sets/base.ucl
@@ -21,7 +21,11 @@ comment = "Base system (metapackage)"
 vital = true
 
 desc = <<EOD
-This metapackage installs all packages which are part of the base system.
+This metapackage installs all packages which are part of the base system,
+excluding 32-bit compatibility libraries, tests, debugging symbols, and
+source code.
+
+This is equivalent to installing the legacy "base.txz" distribution set.
 EOD
 
 deps {
@@ -29,6 +33,10 @@ deps {
 		version = "${VERSION}"
 		origin = "base"
 	},
+	"set-optional" {
+		version = "${VERSION}"
+		origin = "base"
+	},
 	"set-devel" {
 		version = "${VERSION}"
 		origin = "base"
diff --git a/release/packages/ucl/liblzma-all.ucl b/release/packages/sets/optional-dbg.ucl
index 61424c86febb..a221327518f9 100644
--- a/release/packages/ucl/liblzma-all.ucl
+++ b/release/packages/sets/optional-dbg.ucl
@@ -16,13 +16,16 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-comment = "XZ LZMA library"
+comment = "Optional software debug symbols (metapackage)"
 
 desc = <<EOD
-liblzma allows applications to compress and decompress data using the XZ
-compression algorithm.
+This metapackage installs debugging symbols for optional software
+which is not part of the minimal set.
 EOD
 
-annotations {
-	set = "base,base-jail"
+deps {
+	"set-minimal-dbg" {
+		version = "${VERSION}"
+		origin = "base"
+	},
 }
diff --git a/release/packages/ucl/libstdthreads-all.ucl b/release/packages/sets/optional-jail-dbg.ucl
index 0ac43e7576a2..84c76fa407fe 100644
--- a/release/packages/ucl/libstdthreads-all.ucl
+++ b/release/packages/sets/optional-jail-dbg.ucl
@@ -16,13 +16,16 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-comment = "C11 threading library"
+comment = "Optional software debug symbols for jails (metapackage)"
 
 desc = <<EOD
-libstdthreads provides the thread-control interface defined in the
-ISO/IEC 9899:2011 (C11) standard.
+This metapackage installs debugging symbols for optional software
+which is not part of the minimal set.
 EOD
 
-annotations {
-	set = "base,base-jail"
+deps {
+	"set-minimal-jail-dbg" {
+		version = "${VERSION}"
+		origin = "base"
+	},
 }
diff --git a/release/packages/sets/optional-jail.ucl b/release/packages/sets/optional-jail.ucl
new file mode 100644
index 000000000000..da6d5fb00825
--- /dev/null
+++ b/release/packages/sets/optional-jail.ucl
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: ISC
+ *
+ * Copyright (c) 2025 Lexi Winter <ivy@FreeBSD.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+comment = "Optional base system software for jails (metapackage)"
+
+vital = true
+
+desc = <<EOD
+This metapackage installs all optional software which is part of the
+base system but not installed by the minimal set, other than compilers
+and software which is not generally useful in a jail(8) environment.
+EOD
+
+deps {
+	"set-minimal-jail" {
+		version = "${VERSION}"
+		origin = "base"
+	},
+}
diff --git a/release/packages/sets/optional.ucl b/release/packages/sets/optional.ucl
new file mode 100644
index 000000000000..f50fa17e4297
--- /dev/null
+++ b/release/packages/sets/optional.ucl
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: ISC
+ *
+ * Copyright (c) 2025 Lexi Winter <ivy@FreeBSD.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+comment = "Optional base system software (metapackage)"
+
+vital = true
+
+desc = <<EOD
+This metapackage installs all optional software, other than compilers,
+which is part of the base system but not installed by the minimal set.
+EOD
+
+deps {
+	"set-minimal" {
+		version = "${VERSION}"
+		origin = "base"
+	},
+}
diff --git a/release/packages/ucl/acct-all.ucl b/release/packages/ucl/acct-all.ucl
index f4c7119af798..e6c98c3180ce 100644
--- a/release/packages/ucl/acct-all.ucl
+++ b/release/packages/ucl/acct-all.ucl
@@ -31,5 +31,5 @@ system provided in the $PKG_NAME_PREFIX-audit package for that.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/acpi-all.ucl b/release/packages/ucl/acpi-all.ucl
index c459f0004f5d..9e75822a8a04 100644
--- a/release/packages/ucl/acpi-all.ucl
+++ b/release/packages/ucl/acpi-all.ucl
@@ -34,3 +34,7 @@ ACPI implementation in the kernel:
 * acpidump(8) dumps the system's raw ACPI data.
 * iasl(8) is the Intel ACPI compiler/decompiler
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/apm-all.ucl b/release/packages/ucl/apm-all.ucl
index 1318befc4273..a0ade7fb8a5f 100644
--- a/release/packages/ucl/apm-all.ucl
+++ b/release/packages/ucl/apm-all.ucl
@@ -27,3 +27,7 @@ This package provides apm(8), a utility which can be used to monitor the APM
 state and change the system power mode, and the /etc/rc.d/apm service which
 can enable and disable APM at system startup and shutdown.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/atf-all.ucl b/release/packages/ucl/atf-all.ucl
index 3014163c95bd..6e86955fb539 100644
--- a/release/packages/ucl/atf-all.ucl
+++ b/release/packages/ucl/atf-all.ucl
@@ -35,5 +35,5 @@ interface.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/audit-all.ucl b/release/packages/ucl/audit-all.ucl
index 43074b3bf299..3324795d8d9c 100644
--- a/release/packages/ucl/audit-all.ucl
+++ b/release/packages/ucl/audit-all.ucl
@@ -44,5 +44,5 @@ used to manage the auditing system and work with audit data.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/autofs-all.ucl b/release/packages/ucl/autofs-all.ucl
index 63261b9ce8d1..d45949847ce1 100644
--- a/release/packages/ucl/autofs-all.ucl
+++ b/release/packages/ucl/autofs-all.ucl
@@ -29,5 +29,5 @@ managing this, as well as the management utility automount(8).
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/bhyve-all.ucl b/release/packages/ucl/bhyve-all.ucl
index c4e450a47934..c01a826a123f 100644
--- a/release/packages/ucl/bhyve-all.ucl
+++ b/release/packages/ucl/bhyve-all.ucl
@@ -42,5 +42,5 @@ which can be used to run simple virtual machines.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/blocklist-all.ucl b/release/packages/ucl/blocklist-all.ucl
index 6e94b3822cf0..92f304ac9151 100644
--- a/release/packages/ucl/blocklist-all.ucl
+++ b/release/packages/ucl/blocklist-all.ucl
@@ -28,5 +28,5 @@ only daemons which have had blacklist support added will work.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/bluetooth-all.ucl b/release/packages/ucl/bluetooth-all.ucl
index a2376996ec60..55ce4f37f475 100644
--- a/release/packages/ucl/bluetooth-all.ucl
+++ b/release/packages/ucl/bluetooth-all.ucl
@@ -24,3 +24,7 @@ network devices, including the /etc/rc.d/bluetooth service which manages
 the Bluetooth stack when Bluetooth devices are attached or removed, and
 the rfcomm_pppd(8) daemon which manages PPP connections over Bluetooth.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/bsdconfig-all.ucl b/release/packages/ucl/bsdconfig-all.ucl
index 944dc0a259da..42e4114ba20d 100644
--- a/release/packages/ucl/bsdconfig-all.ucl
+++ b/release/packages/ucl/bsdconfig-all.ucl
@@ -27,5 +27,5 @@ the rc.conf(5) configuration.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/bsdinstall-all.ucl b/release/packages/ucl/bsdinstall-all.ucl
index 2e01cbcb51ca..a3fa820e1383 100644
--- a/release/packages/ucl/bsdinstall-all.ucl
+++ b/release/packages/ucl/bsdinstall-all.ucl
@@ -37,5 +37,5 @@ images and jails.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/bsnmp-all.ucl b/release/packages/ucl/bsnmp-all.ucl
index 88a777b3181d..9d02968b0ebf 100644
--- a/release/packages/ucl/bsnmp-all.ucl
+++ b/release/packages/ucl/bsnmp-all.ucl
@@ -42,5 +42,5 @@ bsnmpd can be used in unexpected ways.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ccdconfig-all.ucl b/release/packages/ucl/ccdconfig-all.ucl
index 8f7d1e4300a5..7c23c56d9a29 100644
--- a/release/packages/ucl/ccdconfig-all.ucl
+++ b/release/packages/ucl/ccdconfig-all.ucl
@@ -22,3 +22,7 @@ desc = <<EOD
 ccdconfig(8) is used to configure the concatenated disk driver, ccd(4).
 ccdconfig(8) may also be started on boot using the "ccd" rc(8) service.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/clang-all.ucl b/release/packages/ucl/clang-all.ucl
index e0372940ed42..86cac409fa9e 100644
--- a/release/packages/ucl/clang-all.ucl
+++ b/release/packages/ucl/clang-all.ucl
@@ -25,7 +25,7 @@ This package provides the clang(1) frontend as well as related utilities for
 working with object files.
 EOD
 
-licenses = [ NCSA ]
+licenses = [ "Apache-2.0 WITH LLVM-exception" ]
 
 annotations {
 	set = devel
diff --git a/release/packages/ucl/console-tools-all.ucl b/release/packages/ucl/console-tools-all.ucl
index fee09a1ea3f5..1eef02d8370d 100644
--- a/release/packages/ucl/console-tools-all.ucl
+++ b/release/packages/ucl/console-tools-all.ucl
@@ -29,3 +29,7 @@ to the system:
 * moused(8) can be used to interface with a mouse and provide a graphical
   mouse cursor on the video console.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/csh-all.ucl b/release/packages/ucl/csh-all.ucl
index 787c43bdb82b..1df758ed29ec 100644
--- a/release/packages/ucl/csh-all.ucl
+++ b/release/packages/ucl/csh-all.ucl
@@ -40,5 +40,5 @@ a history mechanism, job control, and a C-like syntax.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ctf-tools-all.ucl b/release/packages/ucl/ctf-all.ucl
index df2955dafab5..970ac3ffb4fa 100644
--- a/release/packages/ucl/ctf-tools-all.ucl
+++ b/release/packages/ucl/ctf-all.ucl
@@ -21,7 +21,7 @@
  * text is licensed under the CDDL.
  */
 
-comment = "Compact C Type Format (CTF) utilities"
+comment = "Compact C Type Format (CTF)"
 
 desc = <<EOD
 The Compact C Type Format (CTF) is a method of encoding type information for C
@@ -29,7 +29,8 @@ programs inside ELF objects.  Compared to the common DWARF debug symbol format,
 CTF is intended specifically for runtime program analyzers such as DTrace.
 
 This package provides the ctfconvert(1), ctfdump(1) and ctfmerge(1) utilities
-which are used to work with CTF data.
+which are used to work with CTF data, and the libctf library which allows
+applications to access CTF debugging information programmatically.
 EOD
 
 licenses = [ "CDDL-1.0" ]
diff --git a/release/packages/ucl/ctl-all.ucl b/release/packages/ucl/ctl-all.ucl
index 22eebb7a2eee..9aa4de455df7 100644
--- a/release/packages/ucl/ctl-all.ucl
+++ b/release/packages/ucl/ctl-all.ucl
@@ -39,3 +39,7 @@ the CAM Target Layer configuration, accepting incoming iSCSI connections,
 performing authentication and passing connections to the kernel part of the
 native iSCSI target.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/cxgbe-tools-all.ucl b/release/packages/ucl/cxgbe-tools-all.ucl
index 33701ae96951..34e1718bb83e 100644
--- a/release/packages/ucl/cxgbe-tools-all.ucl
+++ b/release/packages/ucl/cxgbe-tools-all.ucl
@@ -25,3 +25,7 @@ state of the interface, loading firmware, and configuring features such
 as the hardware packet filter, Quality-of-Service (QoS) scheduler, and
 TCP offload engine.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/diff3-all.ucl b/release/packages/ucl/diff3-all.ucl
new file mode 100644
index 000000000000..b4e53e63c67f
--- /dev/null
+++ b/release/packages/ucl/diff3-all.ucl
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: ISC
+ */
+
+comment = "GNU 3-way file comparison and merge utility"
+
+desc = <<EOD
+Compares three files line by line, optionally merging them.
+EOD
+
+licenses = [ "GPL-2.0-or-later" ]
+
+annotations {
+	set = "optional,optional-jail"
+}
diff --git a/release/packages/ucl/dma-all.ucl b/release/packages/ucl/dma-all.ucl
index 7b52c48a6def..1465fa44f5f1 100644
--- a/release/packages/ucl/dma-all.ucl
+++ b/release/packages/ucl/dma-all.ucl
@@ -48,5 +48,5 @@ the $PKG_NAME_PREFIX-sendmail package instead.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/dtrace-all.ucl b/release/packages/ucl/dtrace-all.ucl
index 7969ed59c144..c41ca59621de 100644
--- a/release/packages/ucl/dtrace-all.ucl
+++ b/release/packages/ucl/dtrace-all.ucl
@@ -27,3 +27,7 @@ This package provides the dtrace(1) utility for executing DTrace scripts written
 in the D language, the utilities lockstat(1) and plockstat(1), and several
 example D scripts installed in /usr/share/dtrace.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/dwatch-all.ucl b/release/packages/ucl/dwatch-all.ucl
index d4646c78101e..c4a6527677f7 100644
--- a/release/packages/ucl/dwatch-all.ucl
+++ b/release/packages/ucl/dwatch-all.ucl
@@ -35,3 +35,7 @@ DTrace scripts to coalesce trace output by date/time, process info, and
 [optionally] probe-specific data.  dwatch also includes a set of pre-defined
 profiles for tracing common system operations.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/ee-all.ucl b/release/packages/ucl/ee-all.ucl
index fbad921e7ef8..93f9d5e056af 100644
--- a/release/packages/ucl/ee-all.ucl
+++ b/release/packages/ucl/ee-all.ucl
@@ -25,5 +25,5 @@ new users.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/examples-all.ucl b/release/packages/ucl/examples-all.ucl
index 027c65427924..15b0b8aadd0f 100644
--- a/release/packages/ucl/examples-all.ucl
+++ b/release/packages/ucl/examples-all.ucl
@@ -26,5 +26,5 @@ Some useful graphics data related to the "Beastie" mascot are also provided.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/fd-all.ucl b/release/packages/ucl/fd-all.ucl
index 768dac3c1a0c..ff87148049ef 100644
--- a/release/packages/ucl/fd-all.ucl
+++ b/release/packages/ucl/fd-all.ucl
@@ -26,3 +26,7 @@ by the fdc(4) driver:
 * fdformat(8) is used to format disks.
 * fdread(1) and fdwrite(1) read and write data to or from floppy disks.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/fetch-all.ucl b/release/packages/ucl/fetch-all.ucl
index d14f22cb74a5..5a3c0be826fa 100644
--- a/release/packages/ucl/fetch-all.ucl
+++ b/release/packages/ucl/fetch-all.ucl
@@ -19,13 +19,13 @@
 comment = "Retrieve a file from a remote URL"
 
 desc = <<EOD
-The fetch(1) utility retieves one or more files from a remote URL via
+The fetch(1) utility retrieves one or more files from a remote URL via
 HTTP or FTP.  fetch(1) includes support for TLS, HTTP proxies, .netrc
 files, and includes a "mirror" mode which only downloads files which
 are newer on the remote site.
 
 Also provided is fetch(3), a library which allows applications to use
-this functionality programatically.
+this functionality programmatically.
 EOD
 
 annotations {
diff --git a/release/packages/ucl/ftp-all.ucl b/release/packages/ucl/ftp-all.ucl
index 285bf72529b5..626feabc69af 100644
--- a/release/packages/ucl/ftp-all.ucl
+++ b/release/packages/ucl/ftp-all.ucl
@@ -24,5 +24,5 @@ protocol (RFC 959) to upload and download files.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/games-all.ucl b/release/packages/ucl/games-all.ucl
index 80339ef6cdea..0716b0c79c19 100644
--- a/release/packages/ucl/games-all.ucl
+++ b/release/packages/ucl/games-all.ucl
@@ -28,5 +28,5 @@ Games distributed with the system:
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ggate-all.ucl b/release/packages/ucl/ggate-all.ucl
index 9b968e1b1239..9a8ba37f0f66 100644
--- a/release/packages/ucl/ggate-all.ucl
+++ b/release/packages/ucl/ggate-all.ucl
@@ -30,3 +30,7 @@ such as iSCSI.
 This package provides the ggated(8) server used to export devices, and
 the ggatec(8) client used to access them.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/gssd-all.ucl b/release/packages/ucl/gssd-all.ucl
index dfd2958d143e..c3e76e365ac4 100644
--- a/release/packages/ucl/gssd-all.ucl
+++ b/release/packages/ucl/gssd-all.ucl
@@ -30,5 +30,5 @@ This daemon is required when using Kerberos authentication with NFS.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/hast-all.ucl b/release/packages/ucl/hast-all.ucl
index f4eed4eb81bd..9fb4ed1a350d 100644
--- a/release/packages/ucl/hast-all.ucl
+++ b/release/packages/ucl/hast-all.ucl
@@ -23,3 +23,7 @@ The Highly Available Storage daemon, hastd(8), provides replication of block
 storage devices between two machines on a network.  HAST can be used by itself
 or as part of an HA cluster to provide redundant cluster storage.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/hostapd-all.ucl b/release/packages/ucl/hostapd-all.ucl
index a2639c464935..cb25beab4f58 100644
--- a/release/packages/ucl/hostapd-all.ucl
+++ b/release/packages/ucl/hostapd-all.ucl
@@ -24,3 +24,7 @@ IEEE Std 802.11 wireless network interface configured in Access Point (AP)
 mode.  hostapd can authenticate clients itself via 802.11i (WPA), or via
 802.1X (EAP) using an external RADIUS server.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/inetd-all.ucl b/release/packages/ucl/inetd-all.ucl
index be1e44fbaa3d..bff3393e5f73 100644
--- a/release/packages/ucl/inetd-all.ucl
+++ b/release/packages/ucl/inetd-all.ucl
@@ -25,5 +25,5 @@ built-in servers for basic services are also provided.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ipf-all.ucl b/release/packages/ucl/ipf-all.ucl
index 04a0a8ef7469..d9ca0424a442 100644
--- a/release/packages/ucl/ipf-all.ucl
+++ b/release/packages/ucl/ipf-all.ucl
@@ -27,5 +27,5 @@ of configuring IP Filter are also provided in /usr/share/examples/ipfilter.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ipfw-all.ucl b/release/packages/ucl/ipfw-all.ucl
index 4eec24194633..1a76aca68987 100644
--- a/release/packages/ucl/ipfw-all.ucl
+++ b/release/packages/ucl/ipfw-all.ucl
@@ -30,5 +30,5 @@ at system startup.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/iscsi-all.ucl b/release/packages/ucl/iscsi-all.ucl
index 928dfe2d0176..c59345a0e147 100644
--- a/release/packages/ucl/iscsi-all.ucl
+++ b/release/packages/ucl/iscsi-all.ucl
@@ -24,3 +24,7 @@ network.  This package provides iscsid(8), the userland component of the iSCSI
 initiator, the iscsictl(8) utility used to monitor and configure the initiator,
 and rc(8) services to configure the initiator during system startup.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/jail-all.ucl b/release/packages/ucl/jail-all.ucl
index 6cd085581240..d2f069f2eb52 100644
--- a/release/packages/ucl/jail-all.ucl
+++ b/release/packages/ucl/jail-all.ucl
@@ -32,5 +32,5 @@ the /etc/jail.conf configuration file.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/kerberos-all.ucl b/release/packages/ucl/kerberos-all.ucl
index a62be895e96d..c888ff5be6e0 100644
--- a/release/packages/ucl/kerberos-all.ucl
+++ b/release/packages/ucl/kerberos-all.ucl
@@ -34,5 +34,5 @@ sometimes called Kerberos V.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/kerberos-kdc-all.ucl b/release/packages/ucl/kerberos-kdc-all.ucl
index 7c2d412460ec..21b0d2121be7 100644
--- a/release/packages/ucl/kerberos-kdc-all.ucl
+++ b/release/packages/ucl/kerberos-kdc-all.ucl
@@ -29,5 +29,5 @@ manages the Kerberos database and issues tickets to Kerberos users.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/kyua-all.ucl b/release/packages/ucl/kyua-all.ucl
index e7a26de7ea6d..2b38efc30d96 100644
--- a/release/packages/ucl/kyua-all.ucl
+++ b/release/packages/ucl/kyua-all.ucl
@@ -54,5 +54,5 @@ TAP-compliant test programs can also be executed through kyua.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "devel"
 }
diff --git a/release/packages/ucl/lib9p-all.ucl b/release/packages/ucl/lib9p-all.ucl
index 9eb030bd7a0c..2cc31d4a3889 100644
--- a/release/packages/ucl/lib9p-all.ucl
+++ b/release/packages/ucl/lib9p-all.ucl
@@ -24,5 +24,5 @@ of the 9P protocol.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libarchive-all.ucl b/release/packages/ucl/libarchive-all.ucl
index 79a80b6a4c54..742734bf8b62 100644
--- a/release/packages/ucl/libarchive-all.ucl
+++ b/release/packages/ucl/libarchive-all.ucl
@@ -34,5 +34,5 @@ such as gzip and bzip2.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libbegemot-all.ucl b/release/packages/ucl/libbegemot-all.ucl
index c1080de8f253..812e94f72eaf 100644
--- a/release/packages/ucl/libbegemot-all.ucl
+++ b/release/packages/ucl/libbegemot-all.ucl
@@ -46,5 +46,5 @@ and, in addition to select(2) and poll(2) also support timers.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libblocksruntime-all.ucl b/release/packages/ucl/libblocksruntime-all.ucl
index 4b4085d9d0da..72f1fca68a99 100644
--- a/release/packages/ucl/libblocksruntime-all.ucl
+++ b/release/packages/ucl/libblocksruntime-all.ucl
@@ -25,5 +25,5 @@ support for lambda expressions and closures.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libbsdstat-all.ucl b/release/packages/ucl/libbsdstat-all.ucl
index acfb77fd6242..144d4200fed9 100644
--- a/release/packages/ucl/libbsdstat-all.ucl
+++ b/release/packages/ucl/libbsdstat-all.ucl
@@ -24,5 +24,5 @@ statistics.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libbsm-all.ucl b/release/packages/ucl/libbsm-all.ucl
deleted file mode 100644
index 76852b310e8f..000000000000
--- a/release/packages/ucl/libbsm-all.ucl
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2005-2007 Robert N. M. Watson
- * Copyright (c) 2008-2009 Apple Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-comment = "Basic Security Module (BSM) audit library"
-
-desc = <<EOD
-The libbsm library routines provide an interface to BSM audit record streams,
-allowing both the parsing of existing audit streams, as well as the creation
-of new audit records and streams.
-EOD
-
-annotations {
-	set = "base,base-jail"
-}
diff --git a/release/packages/ucl/libcasper-all.ucl b/release/packages/ucl/libcasper-all.ucl
index 4f839ef6fc46..387200b6d1bf 100644
--- a/release/packages/ucl/libcasper-all.ucl
+++ b/release/packages/ucl/libcasper-all.ucl
@@ -26,5 +26,5 @@ helper process to allow restricted access to system and network resources.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libcompat-all.ucl b/release/packages/ucl/libcompat-all.ucl
index 1fb209f4cafc..f78c54d93216 100644
--- a/release/packages/ucl/libcompat-all.ucl
+++ b/release/packages/ucl/libcompat-all.ucl
@@ -24,5 +24,5 @@ cuserid(3), re_comp(3), re_exec(3) and rexec(3).
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libcompiler_rt-all.ucl b/release/packages/ucl/libcompiler_rt-all.ucl
index 02be19aa0b7d..af7890c61639 100644
--- a/release/packages/ucl/libcompiler_rt-all.ucl
+++ b/release/packages/ucl/libcompiler_rt-all.ucl
@@ -4,5 +4,5 @@ The libcompiler_rt library from LLVM.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libcuse-all.ucl b/release/packages/ucl/libcuse-all.ucl
index 4be6e8d32a16..422fcb6d3d90 100644
--- a/release/packages/ucl/libcuse-all.ucl
+++ b/release/packages/ucl/libcuse-all.ucl
@@ -35,5 +35,5 @@ userspace.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libdwarf-all.ucl b/release/packages/ucl/libdwarf-all.ucl
index 84905e103dc3..00ec7fcdc452 100644
--- a/release/packages/ucl/libdwarf-all.ucl
+++ b/release/packages/ucl/libdwarf-all.ucl
@@ -34,5 +34,5 @@ information accessible through this API is defined by the DWARF standard.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libevent1-all.ucl b/release/packages/ucl/libevent1-all.ucl
index 4c4f2957d829..31fdf055d8dc 100644
--- a/release/packages/ucl/libevent1-all.ucl
+++ b/release/packages/ucl/libevent1-all.ucl
@@ -23,5 +23,5 @@ A private library used by applications in the base system.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libexecinfo-all.ucl b/release/packages/ucl/libexecinfo-all.ucl
index ce826cb647d9..5cdbea8153d1 100644
--- a/release/packages/ucl/libexecinfo-all.ucl
+++ b/release/packages/ucl/libexecinfo-all.ucl
@@ -24,5 +24,5 @@ examine its current call stack.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libipt-all.ucl b/release/packages/ucl/libipt-all.ucl
index 4bea833f0557..21f8cf29d437 100644
--- a/release/packages/ucl/libipt-all.ucl
+++ b/release/packages/ucl/libipt-all.ucl
@@ -6,5 +6,5 @@ or it can be partially or fully integrated into your tool.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libldns-all.ucl b/release/packages/ucl/libldns-all.ucl
index e4b39caff868..98aa86f9bc53 100644
--- a/release/packages/ucl/libldns-all.ucl
+++ b/release/packages/ucl/libldns-all.ucl
@@ -24,5 +24,5 @@ use by applications in the base system.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libmagic-all.ucl b/release/packages/ucl/libmagic-all.ucl
index c3741ba935df..dc623a14b57e 100644
--- a/release/packages/ucl/libmagic-all.ucl
+++ b/release/packages/ucl/libmagic-all.ucl
@@ -24,5 +24,5 @@ using the magic(5) magic number database.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libmilter-all.ucl b/release/packages/ucl/libmilter-all.ucl
index fea39408e58c..336e9f8c2c78 100644
--- a/release/packages/ucl/libmilter-all.ucl
+++ b/release/packages/ucl/libmilter-all.ucl
@@ -7,5 +7,5 @@ applications implementing the milter interface.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libpathconv-all.ucl b/release/packages/ucl/libpathconv-all.ucl
index a88bf3d017c2..985774986514 100644
--- a/release/packages/ucl/libpathconv-all.ucl
+++ b/release/packages/ucl/libpathconv-all.ucl
@@ -24,5 +24,5 @@ absolute and relative pathnames.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/librpcsec_gss-all.ucl b/release/packages/ucl/librpcsec_gss-all.ucl
index 37ee057b6fd7..a520b75be179 100644
--- a/release/packages/ucl/librpcsec_gss-all.ucl
+++ b/release/packages/ucl/librpcsec_gss-all.ucl
@@ -43,5 +43,5 @@ RPCSEC_GSS security mechanism.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/librss-all.ucl b/release/packages/ucl/librss-all.ucl
index fac6d9ff5c42..68b1ae5fbb11 100644
--- a/release/packages/ucl/librss-all.ucl
+++ b/release/packages/ucl/librss-all.ucl
@@ -6,5 +6,5 @@ system RSS configuration and interacting with RSS aware sockets.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libsdp-all.ucl b/release/packages/ucl/libsdp-all.ucl
index ec9d3319b063..e4f848c3281c 100644
--- a/release/packages/ucl/libsdp-all.ucl
+++ b/release/packages/ucl/libsdp-all.ucl
@@ -24,5 +24,5 @@ Protocol.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libsqlite3-all.ucl b/release/packages/ucl/libsqlite3-all.ucl
index 39364d6804f3..8b770e1ce5ee 100644
--- a/release/packages/ucl/libsqlite3-all.ucl
+++ b/release/packages/ucl/libsqlite3-all.ucl
@@ -23,5 +23,5 @@ A private version of SQLite for use by applications in the base system.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libstdbuf-all.ucl b/release/packages/ucl/libstdbuf-all.ucl
deleted file mode 100644
index c9b1e807fe2b..000000000000
--- a/release/packages/ucl/libstdbuf-all.ucl
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012 Jeremie Le Hen <jlh@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code and documentation must retain the above
- *    copyright notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-comment = "Preloaded library to change standard streams initial buffering"
-
-desc = <<EOD
-The libstdbuf library can be preloaded with the LD_PRELOAD environment variable
-to change the initial buffering of standard input, standard output and standard
-error streams.
-EOD
-
-annotations {
-	set = "base,base-jail"
-}
diff --git a/release/packages/ucl/libthread_db-all.ucl b/release/packages/ucl/libthread_db-all.ucl
index fdae1e70ba41..540e155ccd99 100644
--- a/release/packages/ucl/libthread_db-all.ucl
+++ b/release/packages/ucl/libthread_db-all.ucl
@@ -24,5 +24,5 @@ multithreaded process being debugged.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libucl-all.ucl b/release/packages/ucl/libucl-all.ucl
index aacfe67343f2..4763038a8668 100644
--- a/release/packages/ucl/libucl-all.ucl
+++ b/release/packages/ucl/libucl-all.ucl
@@ -24,5 +24,5 @@ in the base system.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libvgl-all.ucl b/release/packages/ucl/libvgl-all.ucl
index c45ef13a9433..88fd51fffffd 100644
--- a/release/packages/ucl/libvgl-all.ucl
+++ b/release/packages/ucl/libvgl-all.ucl
@@ -47,5 +47,5 @@ on different virtual consoles.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libvmmapi-all.ucl b/release/packages/ucl/libvmmapi-all.ucl
index 2e748501246e..1246a488d4be 100644
--- a/release/packages/ucl/libvmmapi-all.ucl
+++ b/release/packages/ucl/libvmmapi-all.ucl
@@ -23,5 +23,5 @@ libvmmapi provides an interface for applications to access the vmm(4) driver.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/libyaml-all.ucl b/release/packages/ucl/libyaml-all.ucl
index 1446e226cc09..abfded908a87 100644
--- a/release/packages/ucl/libyaml-all.ucl
+++ b/release/packages/ucl/libyaml-all.ucl
@@ -24,5 +24,5 @@ files.  This library is not intended for use outside of the base system.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/lp-all.ucl b/release/packages/ucl/lp-all.ucl
index 00afb70ba61f..6c4e55dbdfef 100644
--- a/release/packages/ucl/lp-all.ucl
+++ b/release/packages/ucl/lp-all.ucl
@@ -29,5 +29,5 @@ Some sample lp filters for common printers are also provided in
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/mlx-tools-all.ucl b/release/packages/ucl/mlx-tools-all.ucl
index ef02c60ae8b2..3b254bf51577 100644
--- a/release/packages/ucl/mlx-tools-all.ucl
+++ b/release/packages/ucl/mlx-tools-all.ucl
@@ -33,3 +33,7 @@ The mlx5tool utility is provided for management of the Connect-X4, 5 and
 6 network adapters in the aspects not covered by the generic ifconfig(8)
 command, mostly related to the PCIe attachment and internal card working.
 EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/natd-all.ucl b/release/packages/ucl/natd-all.ucl
index 4fd0a3d30c40..95f8e8cff031 100644
--- a/release/packages/ucl/natd-all.ucl
+++ b/release/packages/ucl/natd-all.ucl
@@ -28,5 +28,5 @@ or IRC protocols.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ncurses-all.ucl b/release/packages/ucl/ncurses-all.ucl
new file mode 100644
index 000000000000..c0d52e046e78
--- /dev/null
+++ b/release/packages/ucl/ncurses-all.ucl
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2018-2023,2024 Thomas E. Dickey
+ * Copyright 1998-2017,2018 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: X11
+ *
+ * See contrib/ncurses/COPYING for the full license text.
+ */
+
+comment = "ncurses terminal control library"
+desc = <<EOD
+The ncurses package is a subroutine library for terminal-independent
+screen-painting and input-event handling which presents a high level screen
+model to the programmer.  ncurses implements the System V Release 4.0 (SVR4)
+curses interface, and is also backward compatible with traditional BSD curses.
+
+This package ships with a limited termcap database, but it is designed to use
+a terminfo database provided by ports, such as in misc/terminfo-db.
+EOD
diff --git a/release/packages/ucl/netmap-all.ucl b/release/packages/ucl/netmap-all.ucl
index 69a7df614d09..e0770c14c0f2 100644
--- a/release/packages/ucl/netmap-all.ucl
+++ b/release/packages/ucl/netmap-all.ucl
@@ -29,5 +29,5 @@ with netmap, and valectl(8), a utility to manage vale(4) network switches.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/nfs-all.ucl b/release/packages/ucl/nfs-all.ucl
index d48a4ef2efe2..0c9141f2076c 100644
--- a/release/packages/ucl/nfs-all.ucl
+++ b/release/packages/ucl/nfs-all.ucl
@@ -34,5 +34,5 @@ be necessary depending on the NFS configuration.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ntp-all.ucl b/release/packages/ucl/ntp-all.ucl
index 60a5d57ecc26..c0a3fb688d97 100644
--- a/release/packages/ucl/ntp-all.ucl
+++ b/release/packages/ucl/ntp-all.ucl
@@ -39,5 +39,5 @@ A periodic(8) script to monitor the status of the NTP daemon is also provided.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/nvme-tools-all.ucl b/release/packages/ucl/nvme-tools-all.ucl
index 910936f6e70c..ca4d8daff0d2 100644
--- a/release/packages/ucl/nvme-tools-all.ucl
+++ b/release/packages/ucl/nvme-tools-all.ucl
@@ -23,3 +23,7 @@ This package provides the nvmecontrol(8) utility, which is used to monitor
 and configure NVMe devices connected to the local system, and to discover
 and connect to remote NVMe over Fabrics (NVMe-oF) targets.
 EOD
+
+annotations {
+	set = optional
+}
diff --git a/release/packages/ucl/openssl-all.ucl b/release/packages/ucl/openssl-all.ucl
index 398b5165330e..4c393efe3b89 100644
--- a/release/packages/ucl/openssl-all.ucl
+++ b/release/packages/ucl/openssl-all.ucl
@@ -26,7 +26,7 @@ protocols such as HTTP, SMTP and DNS.
 
 OpenSSL provides openssl(1), a command-line utility used for testing TLS
 clients and servers, managing certificate used in TLS authentication, and
-performing various miscallenous cryptographic operations.
+performing various miscellaneous cryptographic operations.
 
 Also provided are two libraries, libcrypto and libssl, which can be used by
 applications to provide generic cryptographic functionality, and to implement
@@ -37,5 +37,5 @@ protocol, which was commonly used prior to the standardisation of TLS.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/pf-all.ucl b/release/packages/ucl/pf-all.ucl
index f8898dd490f1..b1d0ca915d72 100644
--- a/release/packages/ucl/pf-all.ucl
+++ b/release/packages/ucl/pf-all.ucl
@@ -34,5 +34,5 @@ Several example pf rulesets are also provided in /usr/share/examples/pf.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/pmc-all.ucl b/release/packages/ucl/pmc-all.ucl
index b4474b8a0e49..1562bde741a0 100644
--- a/release/packages/ucl/pmc-all.ucl
+++ b/release/packages/ucl/pmc-all.ucl
@@ -12,5 +12,5 @@ command-line access to the facilities provided by libpmc.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/quotacheck-all.ucl b/release/packages/ucl/quotacheck-all.ucl
index d9577624668c..de29ff373f0c 100644
--- a/release/packages/ucl/quotacheck-all.ucl
+++ b/release/packages/ucl/quotacheck-all.ucl
@@ -43,5 +43,5 @@ latter only occurs if an active file system is checked).
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/rcmds-all.ucl b/release/packages/ucl/rcmds-all.ucl
index 9514c8d752e6..c2295af91f9e 100644
--- a/release/packages/ucl/rcmds-all.ucl
+++ b/release/packages/ucl/rcmds-all.ucl
@@ -26,5 +26,5 @@ rpc.rusersd, and rpc.rwalld.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/rdma-all.ucl b/release/packages/ucl/rdma-all.ucl
index be6854780b48..c12104170731 100644
--- a/release/packages/ucl/rdma-all.ucl
+++ b/release/packages/ucl/rdma-all.ucl
@@ -25,5 +25,5 @@ network functionality.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/rip-all.ucl b/release/packages/ucl/rip-all.ucl
index ca9d2ec80d8e..f3cfc2c80211 100644
--- a/release/packages/ucl/rip-all.ucl
+++ b/release/packages/ucl/rip-all.ucl
@@ -27,5 +27,5 @@ RIP and RIPng support is deprecated and will be removed in FreeBSD 16.0.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/sendmail-all.ucl b/release/packages/ucl/sendmail-all.ucl
index 2879431446bf..2b26f982db7d 100644
--- a/release/packages/ucl/sendmail-all.ucl
+++ b/release/packages/ucl/sendmail-all.ucl
@@ -34,5 +34,5 @@ not receive) mail over SMTP.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/smbutils-all.ucl b/release/packages/ucl/smbutils-all.ucl
index 746441d83f73..719afd295d89 100644
--- a/release/packages/ucl/smbutils-all.ucl
+++ b/release/packages/ucl/smbutils-all.ucl
@@ -26,3 +26,7 @@ Message Block (SMB) protocol, sometimes called CIFS.
 This facility only supports SMB version 1, which is strongly deprecated
 and not supported by most SMB servers.
 EOD
+
+annotations {
+	set = optional
+}
diff --git a/release/packages/ucl/sound-all.ucl b/release/packages/ucl/sound-all.ucl
new file mode 100644
index 000000000000..6a8ad098c6b1
--- /dev/null
+++ b/release/packages/ucl/sound-all.ucl
@@ -0,0 +1,42 @@
+/*
+ * SPDX-License-Identifier: ISC
+ *
+ * Copyright (c) 2025 Lexi Winter <ivy@FreeBSD.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+comment = "Audio utilities"
+
+desc = <<EOD
+The sound(4) facility provides an API based on the Open Sound System (OSS)
+to allow applications to play and record audio through physical or virtual
+audio devices.
+
+This package provides several sound-related userland utilities:
+
+* mixer(8) can adjust the playback and recording levels of audio devices.
+
+* sndctl(8) can display and modify audio device configuration.
+
+* The virtual_oss(8) daemon can be used to configure flexible virtual audio
+  devices which can be used by any application.
+
+* beep(1) can play a beep sound.
+
+* mididump(1) can monitor the incoming MIDI events on a MIDI port.
+EOD
+
+annotations {
+	set = "optional"
+}
diff --git a/release/packages/ucl/ssh-all.ucl b/release/packages/ucl/ssh-all.ucl
index 274f9db3ffc5..1bf93f85dbbf 100644
--- a/release/packages/ucl/ssh-all.ucl
+++ b/release/packages/ucl/ssh-all.ucl
@@ -37,5 +37,5 @@ EOD
 licenses = [ ISCL ]
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/syscons-data-all.ucl b/release/packages/ucl/syscons-data-all.ucl
index 5284b8f6dc10..140eebc42a73 100644
--- a/release/packages/ucl/syscons-data-all.ucl
+++ b/release/packages/ucl/syscons-data-all.ucl
@@ -21,3 +21,7 @@ comment = "syscons(4) fonts and keymaps"
 desc = <<EOD
 Fonts and keymaps for use with the legacy syscons(4) video console driver.
 EOD
+
+annotations {
+	set = optional
+}
diff --git a/release/packages/ucl/tcpd-all.ucl b/release/packages/ucl/tcpd-all.ucl
index fd659507a44e..c9cdcab9dde1 100644
--- a/release/packages/ucl/tcpd-all.ucl
+++ b/release/packages/ucl/tcpd-all.ucl
@@ -33,5 +33,5 @@ activity.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/telnet-all.ucl b/release/packages/ucl/telnet-all.ucl
index 426985642560..af4c9001be0f 100644
--- a/release/packages/ucl/telnet-all.ucl
+++ b/release/packages/ucl/telnet-all.ucl
@@ -29,5 +29,5 @@ In most situations, the Secure Shell protocol is preferred over TELNET.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/ufs-all.ucl b/release/packages/ucl/ufs-all.ucl
index d9302bd0e3f9..b35e0f3d1dc7 100644
--- a/release/packages/ucl/ufs-all.ucl
+++ b/release/packages/ucl/ufs-all.ucl
@@ -32,7 +32,7 @@ utilities used to check the consistency of an existing filesystem after
 an unclean shutdown or panic.
 
 The libufs library is also provided, which allows applications to access
-UFS filesystems programatically.
+UFS filesystems programmatically.
 EOD
 
 annotations {
diff --git a/release/packages/ucl/unbound-all.ucl b/release/packages/ucl/unbound-all.ucl
index 40a292bc9685..e66f00be16a7 100644
--- a/release/packages/ucl/unbound-all.ucl
+++ b/release/packages/ucl/unbound-all.ucl
@@ -31,5 +31,5 @@ EOD
 licenses = [ BSD4CLAUSE ]
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/liby-all.ucl b/release/packages/ucl/xz-all.ucl
index a2698faec0b0..8a7c33bcce46 100644
--- a/release/packages/ucl/liby-all.ucl
+++ b/release/packages/ucl/xz-all.ucl
@@ -16,13 +16,14 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-comment = "YACC runtime library"
+comment = "LZMA2 data compression"
 
 desc = <<EOD
-liby provides default implementations of main() and yyerror() for applications
-which use the yacc(1) parser generator.
+xz compresses data using the LZMA2 data compression algorithm.  This package
+provides the front-end xz(1) utility, and the liblzma library which allows
+applications to use this functionality programmatically.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/yp-all.ucl b/release/packages/ucl/yp-all.ucl
index 0cdea7e130c4..f361f319b730 100644
--- a/release/packages/ucl/yp-all.ucl
+++ b/release/packages/ucl/yp-all.ucl
@@ -26,5 +26,5 @@ utilities and a sample Makefile for building the YP database.
 EOD
 
 annotations {
-	set = "base,base-jail"
+	set = "optional,optional-jail"
 }
diff --git a/release/packages/ucl/zfs-all.ucl b/release/packages/ucl/zfs-all.ucl
index 70ebcdacdb57..9d166452188d 100644
--- a/release/packages/ucl/zfs-all.ucl
+++ b/release/packages/ucl/zfs-all.ucl
@@ -39,7 +39,7 @@ This package provides the zfs(8) and zpool(8) utilities used to manage
 ZFS filesystems, the zfsd(8) self-healing daemon, and several other
 utilities, as well as the runtime libraries used internally by ZFS
 itself, and the libzfs_core library providing a stable interface for
-managing ZFS programatically.
+managing ZFS programmatically.
 EOD
 
 licenses = [ "CDDL-1.0" ]
diff --git a/release/scripts/make-pkg-package.sh b/release/scripts/make-pkg-package.sh
index a1e006bd6964..3a1b163bd591 100755
--- a/release/scripts/make-pkg-package.sh
+++ b/release/scripts/make-pkg-package.sh
@@ -8,6 +8,13 @@ PKG_ABI=$(${PKG_CMD} -o ABI_FILE=${WSTAGEDIR}/bin/sh config ABI)
 unset PKG_VERSION
 unset MAKEFLAGS
 unset PKGBASE
+# Ports interprets CROSS_TOOLCHAIN differently from src, and having this set
+# breaks the package-pkg build.  For now, forcibly unset this and hope ports
+# can find a working compiler.
+if [ -n "$CROSS_TOOLCHAIN" ]; then
+	printf >&2 '%s: WARNING: CROSS_TOOLCHAIN will be ignored for the pkg build.\n' "$0"
+	unset CROSS_TOOLCHAIN
+fi
 export WRKDIRPREFIX=/tmp/ports.${TARGET}
 export DISTDIR=/tmp/distfiles
 export WRKDIR=$(make -C ${PORTSDIR}/ports-mgmt/pkg I_DONT_CARE_IF_MY_BUILDS_TARGET_THE_WRONG_RELEASE=YES -V WRKDIR)
diff --git a/release/tools/ec2-builder.conf b/release/tools/ec2-builder.conf
index cf4276fc80ec..a55485fec0cd 100644
--- a/release/tools/ec2-builder.conf
+++ b/release/tools/ec2-builder.conf
@@ -7,17 +7,16 @@
 export VMSIZE=8000m
 
 # Flags to installworld/kernel: We don't want debug symbols (kernel or
-# userland), 32-bit libraries, tests, or the debugger.
+# userland), 32-bit libraries, or tests.
 export INSTALLOPTS="WITHOUT_DEBUG_FILES=YES WITHOUT_KERNEL_SYMBOLS=YES \
-    WITHOUT_LIB32=YES WITHOUT_TESTS=YES WITHOUT_LLDB=YES"
+    WITHOUT_LIB32=YES WITHOUT_TESTS=YES"
 
 # Equivalent to INSTALLOPTS for pkgbase
 vm_extra_filter_base_packages() {
 	grep -v \
 		-e '.*-dbg$' \
 		-e '.*-lib32$' \
-		-e '^FreeBSD-tests.*' \
-		-e '^FreeBSD-lldb.*'
+		-e '^FreeBSD-set-tests'
 }
 
 # Packages to install into the image we're creating.  In addition to packages
diff --git a/release/tools/ec2-small.conf b/release/tools/ec2-small.conf
index 32d02cbb79e4..acaffbbc0c42 100644
--- a/release/tools/ec2-small.conf
+++ b/release/tools/ec2-small.conf
@@ -10,17 +10,16 @@
 export VMSIZE=5000m
 
 # Flags to installworld/kernel: We don't want debug symbols (kernel or
-# userland), 32-bit libraries, tests, or the debugger.
+# userland), 32-bit libraries, or tests.
 export INSTALLOPTS="WITHOUT_DEBUG_FILES=YES WITHOUT_KERNEL_SYMBOLS=YES \
-    WITHOUT_LIB32=YES WITHOUT_TESTS=YES WITHOUT_LLDB=YES"
+    WITHOUT_LIB32=YES WITHOUT_TESTS=YES"
 
 # Equivalent to INSTALLOPTS for pkgbase
 vm_extra_filter_base_packages() {
 	grep -v \
 		-e '.*-dbg$' \
 		-e '.*-lib32$' \
-		-e '^FreeBSD-tests.*' \
-		-e '^FreeBSD-lldb.*'
+		-e '^FreeBSD-set-tests'
 }
 
 # Packages to install into the image we're creating.  In addition to packages
diff --git a/release/tools/oci-image-notoolchain.conf b/release/tools/oci-image-notoolchain.conf
index e251281a7357..a769b53f9ff6 100644
--- a/release/tools/oci-image-notoolchain.conf
+++ b/release/tools/oci-image-notoolchain.conf
@@ -24,7 +24,6 @@ oci_image_build() {
 		FreeBSD-fd \
 		FreeBSD-fetch \
 		FreeBSD-ftp \
-		FreeBSD-ftpd \
 		FreeBSD-inetd \
 		FreeBSD-ipf \
 		FreeBSD-ipfw \
diff --git a/release/tools/vagrant.conf b/release/tools/vagrant.conf
index 7ab0e1238693..5b0f38b740a6 100644
--- a/release/tools/vagrant.conf
+++ b/release/tools/vagrant.conf
@@ -14,14 +14,16 @@ export VM_EXTRA_PACKAGES="${VM_EXTRA_PACKAGES} shells/bash \
 export VM_RC_LIST="firstboot_freebsd_update firstboot_pkgs growfs"
 
 vagrant_common () {
-	# The firstboot_pkgs rc.d script will download the repository
-	# catalogue and install or update pkg when the instance first
-	# launches, so these files would just be replaced anyway; removing
-	# them from the image allows it to boot faster.
-	env ASSUME_ALWAYS_YES=yes pkg -c ${DESTDIR} clean -y -a
-	env ASSUME_ALWAYS_YES=yes pkg -c ${DESTDIR} delete -f -y pkg
-	rm -r ${DESTDIR}/var/db/pkg/repos/FreeBSD-ports
-	rm -r ${DESTDIR}/var/db/pkg/repos/FreeBSD-ports-kmods
+	if [ -z "${NO_ROOT}" ]; then
+		# The firstboot_pkgs rc.d script will download the repository
+		# catalogue and install or update pkg when the instance first
+		# launches, so these files would just be replaced anyway;
+		# removing them from the image allows it to boot faster.
+		pkg -c ${DESTDIR} clean -y -a
+		pkg -c ${DESTDIR} delete -f -y pkg
+		rm -r ${DESTDIR}/var/db/pkg/repos/FreeBSD-ports
+		rm -r ${DESTDIR}/var/db/pkg/repos/FreeBSD-ports-kmods
+	fi
 
 	# Vagrant instances use DHCP to get their network configuration.
 	echo 'ifconfig_DEFAULT="SYNCDHCP"' >> ${DESTDIR}/etc/rc.conf
@@ -40,8 +42,7 @@ vagrant_common () {
 	# Create the vagrant user with a password of vagrant
 	/usr/sbin/pw -R ${DESTDIR} \
 		groupadd vagrant -g 1001
-	chroot ${DESTDIR} mkdir -p /home/vagrant
-	/usr/sbin/pw -R ${DESTDIR} \
+	/usr/sbin/pw -R ${DESTDIR} -M ${DESTDIR}/METALOG \
 		useradd vagrant \
 		-m -M 0755 -w yes -n vagrant -u 1001 -g 1001 -G 0 \
 		-c 'Vagrant User' -d '/home/vagrant' -s '/bin/csh'
@@ -58,11 +59,11 @@ vagrant_common () {
 	echo "ssh-rsa AAAAB3NzaC1yc2EAAAABIwAAAQEA6NF8iallvQVp22WDkTkyrtvp9eWW6A8YVr+kz4TjGYe7gHzIw+niNltGEFHzD8+v1I2YJ6oXevct1YeS0o9HZyN1Q9qgCgzUFtdOKLv6IedplqoPkcmF0aYet2PkEDo3MlTBckFXPITAMzF8dJSIFo9D8HfdOV0IAdx4O7PtixWKn5y2hMNG0zQPyUecp4pzC6kivAIhyfHilFR61RGL+GPXQ2MWZWFYbAGjyiYJnAmCP3NOTd0jMZEnDkbUvxhMmBYSdETk1rRgm+R4LOzFUGaHqHDLKLX+FIPKcF96hrucXzcWyLbIbEgE98OHlnVYCzRdK8jlqm8tehUc9c9WhQ== vagrant insecure public key" > ${DESTDIR}/home/vagrant/.ssh/authorized_keys
 	echo "ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAIN1YdxBpNlzxDqfJyw/QKow1F+wvG9hXGoqiysfJOn5Y vagrant insecure public key" >> ${DESTDIR}/home/vagrant/.ssh/authorized_keys
 	chmod 600 ${DESTDIR}/home/vagrant/.ssh/authorized_keys
-	metalog_add_data ./home/vagrant/.ssh/authorized_keys 0600
 
 	chmod 700 ${DESTDIR}/home/vagrant/.ssh
 	chown -R 1001 ${DESTDIR}/home/vagrant/.ssh
-	echo "./home/vagrant/.ssh type=dir uid=1001 gid=1001 mode=0700" >> METALOG
+	echo "./home/vagrant/.ssh type=dir uid=1001 gid=1001 mode=0700" >> ${DESTDIR}/METALOG
+	echo "./home/vagrant/.ssh/authorized_keys type=file uid=1001 gid=1001 mode=0600" >> ${DESTDIR}/METALOG
 
 	# Reboot quickly, Don't wait at the panic screen
 	echo 'debug.trace_on_panic=1' >> ${DESTDIR}/etc/sysctl.conf
diff --git a/release/tools/vmimage.subr b/release/tools/vmimage.subr
index 577abaac73cf..131ebe37db6c 100644
--- a/release/tools/vmimage.subr
+++ b/release/tools/vmimage.subr
@@ -70,15 +70,15 @@ vm_copy_base() {
 	return 0
 }
 
-vm_filter_base_packages() {
-	# Reads a list of all base system packages from stdin.
-	# Writes a list of base system packages to install to stdout.
-	grep -v -e '^FreeBSD-src.*' -e '^FreeBSD-kernel.*'
-	# There are several kernel variants available in separate packages.
-	# For VMs it is sufficient to install only the generic kernel.
-	echo "FreeBSD-kernel-man"
-	echo "FreeBSD-kernel-generic"
-	echo "FreeBSD-kernel-generic-dbg"
+vm_base_packages_list() {
+	# Output a list of package sets equivalent to what we get from
+	# "installworld installkernel distribution", aka. the full base
+	# system.
+	for S in base lib32 kernels; do
+		echo FreeBSD-set-$S
+		echo FreeBSD-set-$S-dbg
+	done
+	echo FreeBSD-set-tests
 }
 
 vm_extra_filter_base_packages() {
@@ -94,10 +94,12 @@ vm_install_base() {
 		local pkg_cmd
 		pkg_cmd="pkg --rootdir ${DESTDIR} --repo-conf-dir ${PKGBASE_REPO_DIR}
 			-o ASSUME_ALWAYS_YES=yes -o IGNORE_OSVERSION=yes
-			-o INSTALL_AS_USER=yes "
+			-o ABI=${PKG_ABI} -o INSTALL_AS_USER=yes "
+		if [ -n "${NO_ROOT}" ]; then
+			pkg_cmd="$pkg_cmd -o METALOG=METALOG"
+		fi
 		$pkg_cmd update
-		selected=$($pkg_cmd rquery -U -r FreeBSD-base %n | \
-			vm_filter_base_packages | vm_extra_filter_base_packages)
+		selected=$(vm_base_packages_list | vm_extra_filter_base_packages)
 		$pkg_cmd install -U -r FreeBSD-base $selected
 	else
 		cd ${WORLDDIR} && \
@@ -198,6 +200,7 @@ vm_extra_install_packages() {
 		for pkg in ${VM_EXTRA_PACKAGES}; do
 			INSTALL_AS_USER=yes \
 			${PKG_CMD} \
+			    -o ABI=${PKG_ABI} \
 			    -o METALOG=${DESTDIR}/METALOG.pkg \
 			    -o REPOS_DIR=${PKG_REPOS_DIR} \
 			    -o PKG_DBDIR=${DESTDIR}/var/db/pkg \
@@ -249,9 +252,17 @@ vm_emulation_cleanup() {
 }
 
 vm_extra_pkg_rmcache() {
-	if [ -e ${DESTDIR}/usr/local/sbin/pkg ]; then
-		chroot ${DESTDIR} ${EMULATOR} env ASSUME_ALWAYS_YES=yes \
-			/usr/local/sbin/pkg clean -y -a
+	if [ -n "${NO_ROOT}" ]; then
+		${PKG_CMD} \
+		    -o ASSUME_ALWAYS_YES=yes \
+		    -o INSTALL_AS_USER=yes \
+		    -r ${DESTDIR} \
+		    clean -y -a
+	else
+		if [ -e ${DESTDIR}/usr/local/sbin/pkg ]; then
+			chroot ${DESTDIR} ${EMULATOR} env ASSUME_ALWAYS_YES=yes \
+			    /usr/local/sbin/pkg clean -y -a
+		fi
 	fi
 
 	return 0
diff --git a/sbin/devd/Makefile b/sbin/devd/Makefile
index 5d5721d16884..553aecf4ee88 100644
--- a/sbin/devd/Makefile
+++ b/sbin/devd/Makefile
@@ -32,6 +32,11 @@ CONSOLEDIR=		${DEVDDIR}
 CONSOLE+=		moused.conf syscons.conf
 CONSOLEPACKAGE=		console-tools
 
+CONFGROUPS+=		SND
+SNDDIR=			${DEVDDIR}
+SND=			snd.conf
+SNDPACKAGE=		sound
+
 .if ${MK_BLUETOOTH} != "no"
 CONFGROUPS+=		BLUETOOTH
 BLUETOOTHDIR=		${DEVDDIR}
diff --git a/sbin/devd/devd.conf.5 b/sbin/devd/devd.conf.5
index baf4b9d3a183..8df3e910e076 100644
--- a/sbin/devd/devd.conf.5
+++ b/sbin/devd/devd.conf.5
@@ -652,6 +652,22 @@ and
 for details.
 .El
 .Pp
+.Bl -column "System" "Subsystem" "1234567" -compact
+.Sy "System" Ta Sy "Subsystem" Ta Sy "Type" Ta Sy "Description"
+.It Li SND Ta Ta Ta
+Events related to the
+.Xr sound 4
+driver.
+.It Li SND Ta Li CONN Ta Li IN Ta
+Connected input device specified in
+.Pa cdev
+variable.
+.It Li SND Ta Li CONN Ta Li OUT Ta
+Connected output device specified in
+.Pa cdev
+variable.
+.El
+.Pp
 .\"
 .\" End of tables
 .\"
diff --git a/sbin/devd/snd.conf b/sbin/devd/snd.conf
new file mode 100644
index 000000000000..cf9cd9e94191
--- /dev/null
+++ b/sbin/devd/snd.conf
@@ -0,0 +1,23 @@
+# Audio redirection
+notify 0 {
+	match "system"		"SND";
+	match "subsystem"	"CONN";
+	match "type"		"IN";
+	match "cdev"		"dsp[0-9]+";
+
+	# FIXME: We are hardcoding /dev/vdsp.ctl here, simply because it is a
+	# common virtual_oss control device name. Until we find a proper way to
+	# define control devices here, /dev/vdsp.ctl can be changed to the
+	# control device of choice.
+	action			"/usr/sbin/virtual_oss_cmd /dev/vdsp.ctl -R /dev/$cdev";
+};
+
+notify 0 {
+	match "system"		"SND";
+	match "subsystem"	"CONN";
+	match "type"		"OUT";
+	match "cdev"		"dsp[0-9]+";
+
+	# FIXME: See comment above.
+	action			"/usr/sbin/virtual_oss_cmd /dev/vdsp.ctl -P /dev/$cdev";
+};
diff --git a/sbin/ipf/libipf/printdstl_live.c b/sbin/ipf/libipf/printdstl_live.c
index 088448e6656d..72cb75a832c9 100644
--- a/sbin/ipf/libipf/printdstl_live.c
+++ b/sbin/ipf/libipf/printdstl_live.c
@@ -40,6 +40,9 @@ printdstl_live( ippool_dst_t *d, int fd, char *name, int opts,
 	if ((d->ipld_flags & IPHASH_DELETE) != 0)
 		PRINTF("# ");
 
+	if (opts & OPT_SAVEOUT)
+		PRINTF("{\n");
+
 	if ((opts & OPT_DEBUG) == 0)
 		PRINTF("\t{");
 
diff --git a/sbin/ipf/libipf/printdstlist.c b/sbin/ipf/libipf/printdstlist.c
index 2cf41ffe414c..497d7004c94c 100644
--- a/sbin/ipf/libipf/printdstlist.c
+++ b/sbin/ipf/libipf/printdstlist.c
@@ -42,6 +42,8 @@ printdstlist( ippool_dst_t *pp, copyfunc_t copyfunc, char *name, int opts,
 				return (NULL);
 			}
 
+			if (opts & OPT_SAVEOUT)
+				PRINTF("\t");
 			node = printdstlistnode(n, bcopywrap, opts, fields);
 
 			free(n);
diff --git a/sbin/ipf/libipf/printdstlistdata.c b/sbin/ipf/libipf/printdstlistdata.c
index 7940d2ae021b..546bf35cabf6 100644
--- a/sbin/ipf/libipf/printdstlistdata.c
+++ b/sbin/ipf/libipf/printdstlistdata.c
@@ -11,8 +11,7 @@
 void
 printdstlistdata( ippool_dst_t *pool, int opts)
 {
-
-	if ((opts & OPT_DEBUG) == 0) {
+	if ((opts & OPT_DEBUG) == 0 || opts & OPT_SAVEOUT) {
 		if ((pool->ipld_flags & IPDST_DELETE) != 0)
 			PRINTF("# ");
 		PRINTF("pool ");
@@ -24,7 +23,7 @@ printdstlistdata( ippool_dst_t *pool, int opts)
 
 	printunit(pool->ipld_unit);
 
-	if ((opts & OPT_DEBUG) == 0) {
+	if ((opts & OPT_DEBUG) == 0 || opts & OPT_SAVEOUT) {
 		PRINTF("/dstlist (name %s;", pool->ipld_name);
 		if (pool->ipld_policy != IPLDP_NONE) {
 			PRINTF(" policy ");
diff --git a/sbin/ipf/libipf/printhash_live.c b/sbin/ipf/libipf/printhash_live.c
index b8ee31b27597..427daa18316b 100644
--- a/sbin/ipf/libipf/printhash_live.c
+++ b/sbin/ipf/libipf/printhash_live.c
@@ -26,7 +26,9 @@ printhash_live(iphtable_t *hp, int fd, char *name, int opts, wordtab_t *fields)
 	if ((hp->iph_flags & IPHASH_DELETE) != 0)
 		PRINTF("# ");
 
-	if ((opts & OPT_DEBUG) == 0)
+	if (opts & OPT_SAVEOUT)
+		PRINTF("{\n");
+	else if ((opts & OPT_DEBUG) == 0)
 		PRINTF("\t{");
 
 	obj.ipfo_rev = IPFILTER_VERSION;
@@ -50,6 +52,8 @@ printhash_live(iphtable_t *hp, int fd, char *name, int opts, wordtab_t *fields)
 			last = 1;
 		if (bcmp(&zero, &entry, sizeof(zero)) == 0)
 			break;
+		if (opts & OPT_SAVEOUT)
+			PRINTF("\t");
 		(void) printhashnode(hp, &entry, bcopywrap, opts, fields);
 		printed++;
 	}
@@ -59,7 +63,7 @@ printhash_live(iphtable_t *hp, int fd, char *name, int opts, wordtab_t *fields)
 	if (printed == 0)
 		putchar(';');
 
-	if ((opts & OPT_DEBUG) == 0)
+	if ((opts & OPT_DEBUG) == 0 || (opts & OPT_SAVEOUT))
 		PRINTF(" };\n");
 
 	(void) ioctl(fd,SIOCIPFDELTOK, &iter.ili_key);
diff --git a/sbin/ipf/libipf/printhashdata.c b/sbin/ipf/libipf/printhashdata.c
index 690243d63f1e..6fa62e67556d 100644
--- a/sbin/ipf/libipf/printhashdata.c
+++ b/sbin/ipf/libipf/printhashdata.c
@@ -12,7 +12,11 @@ void
 printhashdata(iphtable_t *hp, int opts)
 {
 
-	if ((opts & OPT_DEBUG) == 0) {
+	if (opts & OPT_SAVEOUT) {
+		if ((hp->iph_flags & IPHASH_DELETE) == IPHASH_DELETE)
+			PRINTF("# ");
+		PRINTF("pool ");
+	} else if ((opts & OPT_DEBUG) == 0) {
 		if ((hp->iph_type & IPHASH_ANON) == IPHASH_ANON)
 			PRINTF("# 'anonymous' table refs %d\n", hp->iph_ref);
 		if ((hp->iph_flags & IPHASH_DELETE) == IPHASH_DELETE)
@@ -37,6 +41,8 @@ printhashdata(iphtable_t *hp, int opts)
 		}
 		PRINTF(" role=");
 	} else {
+		if ((hp->iph_flags & IPHASH_DELETE) == IPHASH_DELETE)
+			PRINTF("# ");
 		PRINTF("Hash Table %s: %s",
 			ISDIGIT(*hp->iph_name) ? "Number" : "Name",
 			hp->iph_name);
@@ -48,7 +54,16 @@ printhashdata(iphtable_t *hp, int opts)
 
 	printunit(hp->iph_unit);
 
-	if ((opts & OPT_DEBUG) == 0) {
+	if ((opts & OPT_SAVEOUT)) {
+		if ((hp->iph_type & ~IPHASH_ANON) == IPHASH_LOOKUP)
+			PRINTF("/hash");
+		PRINTF("(%s \"%s\"; size %lu;",
+			ISDIGIT(*hp->iph_name) ? "number" : "name",
+			hp->iph_name, (u_long)hp->iph_size);
+		if (hp->iph_seed != 0)
+			PRINTF(" seed %lu;", hp->iph_seed);
+		PRINTF(")\n", hp->iph_seed);
+	} else if ((opts & OPT_DEBUG) == 0) {
 		if ((hp->iph_type & ~IPHASH_ANON) == IPHASH_LOOKUP)
 			PRINTF(" type=hash");
 		PRINTF(" %s=%s size=%lu",
diff --git a/sbin/ipf/libipf/printpooldata.c b/sbin/ipf/libipf/printpooldata.c
index bd5af316eb19..b203522734be 100644
--- a/sbin/ipf/libipf/printpooldata.c
+++ b/sbin/ipf/libipf/printpooldata.c
@@ -13,6 +13,8 @@ printpooldata(ip_pool_t *pool, int opts)
 {
 
 	if (opts & OPT_SAVEOUT) {
+		if ((pool->ipo_flags & IPOOL_DELETE) != 0)
+			PRINTF("# ");
 		PRINTF("pool ");
 	} else if ((opts & OPT_DEBUG) == 0) {
 		if ((pool->ipo_flags & IPOOL_ANON) != 0)
diff --git a/sbin/ipfw/tests/test_add_rule.py b/sbin/ipfw/tests/test_add_rule.py
index 60c8cebaceaa..c2c4bf0b360c 100755
--- a/sbin/ipfw/tests/test_add_rule.py
+++ b/sbin/ipfw/tests/test_add_rule.py
@@ -36,6 +36,7 @@ from atf_python.sys.netpfil.ipfw.insns import InsnProb
 from atf_python.sys.netpfil.ipfw.insns import InsnProto
 from atf_python.sys.netpfil.ipfw.insns import InsnReject
 from atf_python.sys.netpfil.ipfw.insns import InsnTable
+from atf_python.sys.netpfil.ipfw.insns import InsnU32
 from atf_python.sys.netpfil.ipfw.insns import IpFwOpcode
 from atf_python.sys.netpfil.ipfw.ioctl import CTlv
 from atf_python.sys.netpfil.ipfw.ioctl import CTlvRule
@@ -152,8 +153,8 @@ class TestAddRule(BaseTest):
                             NTlv(IpFwTlvType.IPFW_TLV_TBL_NAME, idx=2, name="BBB"),
                         ],
                         "insns": [
-                            InsnTable(IpFwOpcode.O_IP_SRC_LOOKUP, arg1=1),
-                            InsnTable(IpFwOpcode.O_IP_DST_LOOKUP, arg1=2),
+                            InsnU32(IpFwOpcode.O_IP_SRC_LOOKUP, u32=1),
+                            InsnU32(IpFwOpcode.O_IP_DST_LOOKUP, u32=2),
                             InsnEmpty(IpFwOpcode.O_ACCEPT),
                         ],
                     },
@@ -182,7 +183,7 @@ class TestAddRule(BaseTest):
                         ],
                         "insns": [
                             InsnIp(IpFwOpcode.O_IP_DST, ip="1.2.3.4"),
-                            Insn(IpFwOpcode.O_EXTERNAL_ACTION, arg1=1),
+                            InsnU32(IpFwOpcode.O_EXTERNAL_ACTION, u32=1),
                             Insn(IpFwOpcode.O_EXTERNAL_DATA, arg1=123),
                         ],
                     },
@@ -199,8 +200,8 @@ class TestAddRule(BaseTest):
                         ],
                         "insns": [
                             InsnIp(IpFwOpcode.O_IP_DST, ip="1.2.3.4"),
-                            Insn(IpFwOpcode.O_EXTERNAL_ACTION, arg1=1),
-                            Insn(IpFwOpcode.O_EXTERNAL_INSTANCE, arg1=2),
+                            InsnU32(IpFwOpcode.O_EXTERNAL_ACTION, u32=1),
+                            InsnU32(IpFwOpcode.O_EXTERNAL_INSTANCE, u32=2),
                         ],
                     },
                 },
@@ -227,7 +228,7 @@ class TestAddRule(BaseTest):
                         ],
                         "insns": [
                             InsnComment(comment="test comment"),
-                            Insn(IpFwOpcode.O_CHECK_STATE, arg1=1),
+                            InsnU32(IpFwOpcode.O_CHECK_STATE, u32=1),
                         ],
                     },
                 },
@@ -241,9 +242,9 @@ class TestAddRule(BaseTest):
                             NTlv(IpFwTlvType.IPFW_TLV_STATE_NAME, idx=1, name="OUT"),
                         ],
                         "insns": [
-                            Insn(IpFwOpcode.O_PROBE_STATE, arg1=1),
+                            InsnU32(IpFwOpcode.O_PROBE_STATE, u32=1),
                             Insn(IpFwOpcode.O_PROTO, arg1=6),
-                            Insn(IpFwOpcode.O_KEEP_STATE, arg1=1),
+                            InsnU32(IpFwOpcode.O_KEEP_STATE, u32=1),
                             InsnEmpty(IpFwOpcode.O_ACCEPT),
                         ],
                     },
@@ -259,7 +260,7 @@ class TestAddRule(BaseTest):
                         ],
                         "insns": [
                             Insn(IpFwOpcode.O_PROTO, arg1=6),
-                            Insn(IpFwOpcode.O_KEEP_STATE, arg1=1),
+                            InsnU32(IpFwOpcode.O_KEEP_STATE, u32=1),
                             InsnEmpty(IpFwOpcode.O_ACCEPT),
                         ],
                     },
@@ -370,7 +371,7 @@ class TestAddRule(BaseTest):
             ),
             pytest.param(("pipe 42", Insn(IpFwOpcode.O_PIPE, arg1=42)), id="pipe_42"),
             pytest.param(
-                ("skipto 42", Insn(IpFwOpcode.O_SKIPTO, arg1=42)), id="skipto_42"
+                ("skipto 42", InsnU32(IpFwOpcode.O_SKIPTO, u32=42)), id="skipto_42"
             ),
             pytest.param(
                 ("netgraph 42", Insn(IpFwOpcode.O_NETGRAPH, arg1=42)), id="netgraph_42"
@@ -386,7 +387,7 @@ class TestAddRule(BaseTest):
             ),
             pytest.param(("tee 42", Insn(IpFwOpcode.O_TEE, arg1=42)), id="tee_42"),
             pytest.param(
-                ("call 420", Insn(IpFwOpcode.O_CALLRETURN, arg1=420)), id="call_420"
+                ("call 420", InsnU32(IpFwOpcode.O_CALLRETURN, u32=420)), id="call_420"
             ),
             # TOK_FORWARD
             pytest.param(
@@ -400,7 +401,7 @@ class TestAddRule(BaseTest):
             ),
             pytest.param(("reass", InsnEmpty(IpFwOpcode.O_REASS)), id="reass"),
             pytest.param(
-                ("return", InsnEmpty(IpFwOpcode.O_CALLRETURN, is_not=True)), id="return"
+                ("return", InsnU32(IpFwOpcode.O_CALLRETURN, is_not=True)), id="return"
             ),
         ],
     )
diff --git a/sbin/pfctl/pfctl.c b/sbin/pfctl/pfctl.c
index 21562fa03e0d..ed317495c2e0 100644
--- a/sbin/pfctl/pfctl.c
+++ b/sbin/pfctl/pfctl.c
@@ -2183,6 +2183,7 @@ pfctl_load_rule(struct pfctl *pf, char *path, struct pfctl_rule *r, int depth)
 {
 	u_int8_t		rs_num = pf_get_ruleset_number(r->action);
 	char			*name;
+	uint32_t		ticket;
 	char			anchor[PF_ANCHOR_NAME_SIZE];
 	int			len = strlen(path);
 	int			error;
@@ -2192,7 +2193,9 @@ pfctl_load_rule(struct pfctl *pf, char *path, struct pfctl_rule *r, int depth)
 	if ((pf->opts & PF_OPT_NOACTION) == 0) {
 		if (pf->trans == NULL)
 			errx(1, "pfctl_load_rule: no transaction");
-		pf->anchor->ruleset.tticket = pfctl_get_ticket(pf->trans, rs_num, path);
+		ticket = pfctl_get_ticket(pf->trans, rs_num, path);
+		if (rs_num == PF_RULESET_FILTER)
+			 pf->anchor->ruleset.tticket = ticket;
 	}
 	if (strlcpy(anchor, path, sizeof(anchor)) >= sizeof(anchor))
 		errx(1, "pfctl_load_rule: strlcpy");
@@ -2225,7 +2228,7 @@ pfctl_load_rule(struct pfctl *pf, char *path, struct pfctl_rule *r, int depth)
 			return (1);
 		if (pfctl_add_pool(pf, &r->route, PF_RT))
 			return (1);
-		error = pfctl_add_rule_h(pf->h, r, anchor, name, pf->anchor->ruleset.tticket,
+		error = pfctl_add_rule_h(pf->h, r, anchor, name, ticket,
 		    pf->paddr.ticket);
 		switch (error) {
 		case 0:
@@ -3582,6 +3585,12 @@ main(int argc, char *argv[])
 	}
 
 	if (clearopt != NULL) {
+		int	 mnr;
+
+		/* Check if anchor exists. */
+		if ((pfctl_get_rulesets(pfh, anchorname, &mnr)) == ENOENT)
+			errx(1, "No such anchor %s", anchorname);
+
 		switch (*clearopt) {
 		case 'e':
 			pfctl_flush_eth_rules(dev, opts, anchorname);
diff --git a/share/examples/etc/README.examples b/share/examples/etc/README.examples
index b0dc2b83ad66..810e5e28cb5c 100644
--- a/share/examples/etc/README.examples
+++ b/share/examples/etc/README.examples
@@ -19,7 +19,6 @@ devfs.conf	- configuration file for devfs(8)
 dhclient.conf	- configuration file for dhclient(8)
 disktab		- disk description file (see disktab(5))
 fbtab		- configuration file for login(1)
-ftpusers	- user restriction file for ftpd(8)
 gettytab	- defines port configuration for getty(8)
 group		- group permissions file (see group(5))
 hosts		- see hosts(5)
diff --git a/share/man/man3/snl.3 b/share/man/man3/snl.3
index 9a6eceb66a32..04bae46691bf 100644
--- a/share/man/man3/snl.3
+++ b/share/man/man3/snl.3
@@ -288,7 +288,7 @@ main(int ac, char *argv[])
 		struct nl_parsed_link link = {};
 		if (!snl_parse_nlmsg(&ss, hdr, &link_parser, &link))
 			continue;
-		printf("Link#%u %s mtu %u\n", link.ifi_index, link.ifla_ifname, link.ifla_mtu);
+		printf("Link#%u %s mtu %u\en", link.ifi_index, link.ifla_ifname, link.ifla_mtu);
 	}
 
 	return (0);
diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile
index f5d7a0e081fc..6e076722c786 100644
--- a/share/man/man4/Makefile
+++ b/share/man/man4/Makefile
@@ -589,6 +589,7 @@ MAN=	aac.4 \
 	tdfx.4 \
 	termios.4 \
 	textdump.4 \
+	thunderbolt.4 \
 	ti.4 \
 	timecounters.4 \
 	tmpfs.4 \
diff --git a/share/man/man4/aac.4 b/share/man/man4/aac.4
index 7a7d0350dcdb..f4b431cc6b4f 100644
--- a/share/man/man4/aac.4
+++ b/share/man/man4/aac.4
@@ -1,3 +1,6 @@
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
 .\" Copyright (c) 2000 Scott Long
 .\" All rights reserved.
 .\"
@@ -21,7 +24,7 @@
 .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
-.Dd July 10, 2009
+.Dd September 29, 2025
 .Dt AAC 4
 .Os
 .Sh NAME
@@ -83,9 +86,10 @@ Linux-compatible
 interface for the management device will be enabled and will allow
 Linux-based management applications to control the card.
 .Sh HARDWARE
-Controllers supported by the
+The
 .Nm
-driver include:
+driver supports the following Parallel SCSI, SATA, and 3G SAS
+RAID controllers from the Adaptec AAC family:
 .Pp
 .Bl -bullet -compact
 .It
diff --git a/share/man/man4/ahc.4 b/share/man/man4/ahc.4
index 38712c1f08b6..72a1e092f1bc 100644
--- a/share/man/man4/ahc.4
+++ b/share/man/man4/ahc.4
@@ -1,4 +1,6 @@
 .\"
+.\" SPDX-License-Identifier: BSD-3-Clause
+.\"
 .\" Copyright (c) 1995, 1996, 1997, 1998, 2000
 .\" 	Justin T. Gibbs.  All rights reserved.
 .\"
@@ -24,7 +26,7 @@
 .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd February 15, 2017
+.Dd September 29, 2025
 .Dt AHC 4
 .Os
 .Sh NAME
@@ -172,11 +174,7 @@ adapter, defaults to enabled (0 -- disabled, 1 -- enabled).
 .Sh HARDWARE
 The
 .Nm
-driver supports the following
-.Tn SCSI
-host adapter chips and
-.Tn SCSI
-controller cards:
+driver supports the following VL/ISA/PCI parallel SCSI controllers and cards:
 .Pp
 .Bl -bullet -compact
 .It
diff --git a/share/man/man4/ahd.4 b/share/man/man4/ahd.4
index c173a8cef619..7fa08c12b5b5 100644
--- a/share/man/man4/ahd.4
+++ b/share/man/man4/ahd.4
@@ -1,4 +1,6 @@
 .\"
+.\" SPDX-License-Identifer: BSD-3-Clause
+.\"
 .\" Copyright (c) 1995, 1996, 1997, 1998, 2000
 .\" 	Justin T. Gibbs.  All rights reserved.
 .\" Copyright (c) 2002
@@ -26,7 +28,7 @@
 .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd July 4, 2004
+.Dd September 29, 2025
 .Dt AHD 4
 .Os
 .Sh NAME
@@ -132,7 +134,7 @@ A hint to define whether the SCSI target mode is enabled (0 -- disabled, 1 -- en
 .Sh HARDWARE
 The
 .Nm
-driver supports the following:
+driver supports the following PCI/PCI-X parallel SCSI controllers:
 .Pp
 .Bl -bullet -compact
 .It
diff --git a/share/man/man4/cxgbe.4 b/share/man/man4/cxgbe.4
index bfba202d1fec..77465a3ae590 100644
--- a/share/man/man4/cxgbe.4
+++ b/share/man/man4/cxgbe.4
@@ -29,7 +29,7 @@
 .\"
 .\" * Other names and brands may be claimed as the property of others.
 .\"
-.Dd November 10, 2022
+.Dd September 29, 2025
 .Dt CXGBE 4
 .Os
 .Sh NAME
@@ -73,6 +73,7 @@ driver uses different names for devices based on the associated ASIC:
 .It T4 Ta cxgbe Ta t4nex Ta vcxgbe
 .It T5 Ta cxl Ta t5nex Ta vcxl
 .It T6 Ta cc Ta t6nex Ta vcc
+.It T7 Ta che Ta chnex Ta vche
 .El
 .Pp
 Loader tunables with the hw.cxgbe prefix apply to all cards.
@@ -416,6 +417,8 @@ Support for T6 cards first appeared in
 .Fx 11.1
 and
 .Fx 12.0 .
+Support for T7 cards first appeared in
+.Fx 15.0 .
 .Sh AUTHORS
 .An -nosplit
 The
diff --git a/share/man/man4/ice.4 b/share/man/man4/ice.4
index 3f7a9017756d..c7675e627726 100644
--- a/share/man/man4/ice.4
+++ b/share/man/man4/ice.4
@@ -1,4 +1,4 @@
-.\"-
+.\"
 .\" SPDX-License-Identifier: BSD-3-Clause
 .\"
 .\" Copyright (c) 2019-2020, Intel Corporation
@@ -32,25 +32,35 @@
 .\"
 .\" * Other names and brands may be claimed as the property of others.
 .\"
-.Dd March 28, 2025
+.Dd October 3, 2025
 .Dt ICE 4
 .Os
 .Sh NAME
 .Nm ice
-.Nd "Intel\(rg Ethernet 800 Series Driver"
+.Nd Intel Ethernet 800 Series Driver
 .Sh SYNOPSIS
-To compile this driver into the kernel, place the following lines in your
-kernel configuration file:
-.Bd -literal -offset indent
 .Cd device iflib
 .Cd device ice
-.Ed
 .Pp
-To load the driver as a module at boot time, place the following lines in
+In
 .Xr loader.conf 5 :
-.Bd -literal -offset indent
-if_ice_load="YES"
-.Ed
+.Cd if_ice_load
+.Cd hw.ice.enable_health_events
+.Cd hw.ice.irdma
+.Cd hw.ice.irdma_max_msix
+.Cd hw.ice.debug.enable_tx_fc_filter
+.Cd hw.ice.debug.enable_tx_lldp_filter
+.Cd hw.ice.debug.ice_tx_balance_en
+.Pp
+In
+.Xr sysctl.conf 5
+or
+.Xr loader.conf 5 :
+.Cd dev.ice.#.current_speed
+.Cd dev.ice.#.fw_version
+.Cd dev.ice.#.ddp_version
+.Cd dev.ice.#.pba_number
+.Cd dev.ice.#.hw.mac.*
 .Sh DESCRIPTION
 .Ss Features
 The
@@ -86,7 +96,7 @@ Intel\(rg Ethernet Connection E830\-XXV
 .El
 .Pp
 For questions related to hardware requirements, refer to the documentation
-supplied with your adapter.
+supplied with the adapter.
 .Pp
 Support for Jumbo Frames is provided via the interface MTU setting.
 Selecting an MTU larger than 1500 bytes with the
@@ -134,17 +144,16 @@ See the
 .Dq Intel\(rg Ethernet Adapters and Devices User Guide
 for more details on DDP and Safe Mode.
 .Pp
-If you encounter issues with the DDP package file, you may need to download
-an updated driver or
+If issues are encountered with the DDP package file, an updated driver or
 .Sy ice_ddp
-module.
+module may need to be downloaded.
 See the log messages for more information.
 .Pp
-You cannot update the DDP package if any PF drivers are already loaded.
+The DDP package cannot be updated if any PF drivers are already loaded.
 To overwrite a package, unload all PFs and then reload the driver with the
 new package.
 .Pp
-You can only use one DDP package per driver, even if you have more than one
+Only one DDP package can be used per driver, even if more than one
 device installed that uses the driver.
 .Pp
 Only the first loaded PF per device can download a package for that device.
@@ -164,9 +173,9 @@ each jumbo packet.
 This should help to avoid buffer starvation issues when allocating receive
 packets.
 .Pp
-Packet loss may have a greater impact on throughput when you use jumbo
-frames.
-If you observe a drop in performance after enabling jumbo frames, enabling
+Packet loss may have a greater impact on throughput when jumbo frames are in
+use.
+If a drop in performance is observed after enabling jumbo frames, enabling
 flow control may mitigate the issue.
 .Ss Remote Direct Memory Access
 Remote Direct Memory Access, or RDMA, allows a network device to transfer data
@@ -184,14 +193,14 @@ operating in multiport mode with more than 4 ports.
 For detailed installation and configuration information for RDMA, see
 .Xr irdma 4 .
 .Ss RDMA Monitoring
-For debugging/testing purposes, you can use sysctl to set up a mirroring
+For debugging/testing purposes, a sysctl can be used to set up a mirroring
 interface on a port.
 The interface can receive mirrored RDMA traffic for packet
 analysis tools like
 .Xr tcpdump 1 .
 This mirroring may impact performance.
 .Pp
-To use RDMA monitoring, you may need to reserve more MSI\-X interrupts.
+To use RDMA monitoring, more MSI\-X interrupts may need to be reserved.
 Before the
 .Nm
 driver loads, configure the following tunable provided by
@@ -200,7 +209,7 @@ driver loads, configure the following tunable provided by
 dev.ice.<interface #>.iflib.use_extra_msix_vectors=4
 .Ed
 .Pp
-You may need to adjust the number of extra MSI\-X interrupt vectors.
+The number of extra MSI\-X interrupt vectors may need to be adjusted.
 .Pp
 To create/delete the interface:
 .Bd -literal -offset indent
@@ -276,7 +285,7 @@ To enable/disable priority flow control in software\-based DCBX mode:
 sysctl dev.ice.<interface #>.pfc=1 (or 0 to disable)
 .Ed
 .Pp
-Enhanced Transmission Selection (ETS) allows you to assign bandwidth to certain
+Enhanced Transmission Selection (ETS) allows bandwidth to be assigned to certain
 TCs, to help ensure traffic reliability.
 To view the assigned ETS configuration, use the following:
 .Bd -literal -offset indent
@@ -310,7 +319,7 @@ Use the following sysctl to enable or disable L3 QoS:
 sysctl dev.ice.<interface #>.pfc_mode=1 (or 0 to disable)
 .Ed
 .Pp
-If you disable L3 QoS mode, it returns to L2 QoS mode.
+If the L3 QoS mode is disabled, it returns to L2 QoS mode.
 .Pp
 To map a DSCP value to a traffic class, separate the values by commas.
 For example, to map DSCPs 0\-3 and DSCP 8 to DCB TCs 0\-3 and 4, respectively:
@@ -329,7 +338,7 @@ sysctl dev.ice.<interface #>.dscp2tc_map
 .Pp
 L3 QoS mode is not available when FW\-LLDP is enabled.
 .Pp
-You also cannot enable FW\-LLDP if L3 QoS mode is active.
+FW\-LLDP cannot be enabled if L3 QoS mode is active.
 .Pp
 Disable FW\-LLDP before switching to L3 QoS mode.
 .Pp
@@ -355,11 +364,11 @@ To check the current LLDP setting:
 sysctl dev.ice.<interface #>.fw_lldp_agent
 .Ed
 .Pp
-You must enable the UEFI HII LLDP Agent attribute for this setting
+The UEFI HII LLDP Agent attribute must be enabled for this setting
 to take effect.
 If the
 .Dq LLDP AGENT
-attribute is set to disabled, you cannot enable the FW\-LLDP Agent from the
+attribute is set to disabled, the FW\-LLDP Agent cannot be enabled from the
 driver.
 .Ss Link\-Level Flow Control (LFC)
 Ethernet Flow Control (IEEE 802.3x) can be configured with sysctl to enable
@@ -416,11 +425,11 @@ provide a stable link without FEC.
 .Pp
 For devices to benefit from this feature, link partners must have FEC enabled.
 .Pp
-If you enable the sysctl
-.Em allow_no_fec_modules_in_auto
-Auto FEC negotiation will include
+If the
+.Va allow_no_fec_modules_in_auto
+sysctl is enabled Auto FEC negotiation will include
 .Dq No FEC
-in case your link partner does not have FEC enabled or is not FEC capable:
+in case the link partner does not have FEC enabled or is not FEC capable:
 .Bd -literal -offset indent
 sysctl dev.ice.<interface #>.allow_no_fec_modules_in_auto=1
 .Ed
@@ -443,16 +452,16 @@ To see the valid FEC modes for the link:
 sysctl \-d dev.ice.<interface #>.requested_fec
 .Ed
 .Ss Speed and Duplex Configuration
-You cannot set duplex or autonegotiation settings.
+The speed and duplex settings cannot be hard set.
 .Pp
-To have your device change the speeds it will use in auto-negotiation or
+To have the device change the speeds it will use in auto-negotiation or
 force link with:
 .Bd -literal -offset indent
 sysctl dev.ice.<interface #>.advertise_speed=<mask>
 .Ed
 .Pp
 Supported speeds will vary by device.
-Depending on the speeds your device supports, valid bits used in a speed mask
+Depending on the speeds the device supports, valid bits used in a speed mask
 could include:
 .Bd -literal -offset indent
 0x0 \- Auto
@@ -493,13 +502,13 @@ At a high level, to capture a firmware log:
 .It
 Set the configuration for the firmware log.
 .It
-Perform the necessary steps to generate the issue you are trying to debug.
+Perform the necessary steps to reproduce the issue.
 .It
 Capture the firmware log.
 .It
 Stop capturing the firmware log.
 .It
-Reset your firmware log settings as needed.
+Reset the firmware log settings as needed.
 .It
 Work with Customer Support to debug the issue.
 .El
@@ -583,8 +592,8 @@ PF Registration (Bit 30)
 Module Version (Bit 31)
 .El
 .Pp
-You can change the verbosity level of the firmware logs.
-You can set only one log level per module, and each level includes the
+The verbosity level of the firmware logs can be modified.
+It is possible to set only one log level per module, and each level includes the
 verbosity levels lower than it.
 For instance, setting the level to
 .Dq normal
@@ -640,8 +649,8 @@ dmesg > log_output
 NOTE: Logging a large number of modules or too high of a verbosity level will
 add extraneous messages to dmesg and could hinder debug efforts.
 .Ss Debug Dump
-Intel\(rg Ethernet 800 Series devices support debug dump, which allows you to
-obtain runtime register values from the firmware for
+Intel\(rg Ethernet 800 Series devices support debug dump, which allows
+gathering of runtime register values from the firmware for
 .Dq clusters
 of events and then write the results to a single dump file, for debugging
 complicated issues in the field.
@@ -654,7 +663,7 @@ stateless snapshot of the whole device.
 .Pp
 NOTE: Like with firmware logs, the contents of the debug dump are not
 human\-readable.
-You must work with Customer Support to decode the file.
+Work with Customer Support to decode the file.
 .Pp
 Debug dump is per device, not per PF.
 .Pp
@@ -717,20 +726,19 @@ sysctl dev.ice.0.debug.dump.clusters=0
 .Pp
 NOTE: Using 0 will skip Manageability Transactions data.
 .Pp
-If you don't specify a cluster, the driver will dump all clusters to a
+If a single cluster is not specified, the driver will dump all clusters to a
 single file.
 Issue the debug dump command, using the following:
 .Bd -literal -offset indent
 sysctl \-b dev.ice.<interface #>.debug.dump.dump=1 > dump.bin
 .Ed
 .Pp
-NOTE: The driver will not receive the command if you do not write
-.Dq 1
-to the sysctl.
+NOTE: The driver will not receive the command if the sysctl is not set to
+.Dq 1 .
 .Pp
 Replace
 .Dq dump.bin
-above with the file name you want to use.
+above with the preferred file name.
 .Pp
 To clear the
 .Va clusters
@@ -744,7 +752,7 @@ The ice driver supports the ability to obtain the values of the PHY registers
 from Intel(R) Ethernet 810 Series devices in order to debug link and
 connection issues during runtime.
 .Pp
-The driver allows you to obtain information about:
+The driver provides information about:
 .Bl -bullet
 .It
 Rx and Tx Equalization parameters
@@ -758,12 +766,12 @@ sysctl dev.ice.<interface #>.debug.phy_statistics
 .Ed
 .Pp
 NOTE: The contents of the registers are not human\-readable.
-Like with firmware logs and debug dump, you must work with Customer Support
+Like with firmware logs and debug dump, work with Customer Support
 to decode the file.
 .Ss Transmit Balancing
-Some Intel(R) Ethernet 800 Series devices allow you to enable a transmit
+Some Intel(R) Ethernet 800 Series devices allow for enabling a transmit
 balancing feature to improve transmit performance under certain conditions.
-When the feature is enabled, you should experience more consistent transmit
+When enabled, the feature should provide more consistent transmit
 performance across queues and/or PFs and VFs.
 .Pp
 By default, transmit balancing is disabled in the NVM.
@@ -784,7 +792,7 @@ configures the device accordingly.
 .Pp
 NOTE: The user selection for transmit balancing in EPCT or HII is persistent
 across reboots.
-You must reboot the system for the selected setting to take effect.
+The system must be rebooted for the selected setting to take effect.
 .Pp
 This setting is device wide.
 .Pp
@@ -801,7 +809,7 @@ sysctl dev.ice.<interface #>.temp
 may have a low number of network memory buffers (mbufs) by default.
 If the number of mbufs available is too low, it may cause the driver to fail
 to initialize and/or cause the system to become unresponsive.
-You can check to see if the system is mbuf\-starved by running
+Check to see if the system is mbuf\-starved by running
 .Ic netstat Fl m .
 Increase the number of mbufs by editing the lines below in
 .Pa /etc/sysctl.conf :
@@ -813,7 +821,7 @@ kern.ipc.nmbjumbo16
 kern.ipc.nmbufs
 .Ed
 .Pp
-The amount of memory that you allocate is system specific, and may require some
+The amount of memory that should be allocated is system specific, and may require some
 trial and error.
 Also, increasing the following in
 .Pa /etc/sysctl.conf
@@ -908,8 +916,8 @@ link partner's switch ports.
 Some PCIe x8 slots are actually configured as x4 slots.
 These slots have insufficient bandwidth for full line rate with dual port and
 quad port devices.
-In addition, if you put a PCIe v4.0 or v3.0\-capable adapter into a PCIe v2.x
-slot, you cannot get full bandwidth.
+In addition, if a PCIe v4.0 or v3.0\-capable adapter is placed into a PCIe v2.x
+slot, full bandwidth will not be possible.
 .Pp
 The driver detects this situation and writes the following message in the
 system log:
@@ -920,7 +928,7 @@ Please move the device to a different PCI\-e link with more lanes and/or
 higher transfer rate.
 .Ed
 .Pp
-If this error occurs, moving your adapter to a true PCIe x8 or x16 slot will
+If this error occurs, moving the adapter to a true PCIe x8 or x16 slot will
 resolve the issue.
 For best performance, install devices in the following PCI slots:
 .Bl -bullet
diff --git a/share/man/man4/ip.4 b/share/man/man4/ip.4
index c52715a43380..fb5ea398c840 100644
--- a/share/man/man4/ip.4
+++ b/share/man/man4/ip.4
@@ -575,7 +575,7 @@ is the following structure:
 .Bd -literal
 struct ip_mreqn {
     struct in_addr imr_multiaddr; /* IP multicast address of group */
-    struct in_addr imr_interface; /* local IP address of interface */
+    struct in_addr imr_address;   /* local IP address of interface */
     int            imr_ifindex;   /* interface index */
 }
 .Ed
diff --git a/share/man/man4/mmcsd.4 b/share/man/man4/mmcsd.4
index 7466bc546b91..07d7e963b596 100644
--- a/share/man/man4/mmcsd.4
+++ b/share/man/man4/mmcsd.4
@@ -1,4 +1,6 @@
 .\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
 .\" Copyright (c) 2007 M. Warner Losh <imp@FreeBSD.org>
 .\"
 .\" Redistribution and use in source and binary forms, with or without
@@ -21,7 +23,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd June 10, 2021
+.Dd October 2, 2025
 .Dt MMCSD 4
 .Os
 .Sh NAME
@@ -29,7 +31,7 @@
 .Nd MMC and SD memory card driver
 .Sh SYNOPSIS
 .Cd device mmcsd
-.Sh DESCRIPTION
+.Sh HARDWARE
 The
 .Nm
 driver implements direct access block device for MMC and SD memory cards.
@@ -42,3 +44,8 @@ driver implements direct access block device for MMC and SD memory cards.
 .Rs
 .%T "The MultiMediaCard System Specification"
 .Re
+.Sh HISTORY
+The
+.Nm
+driver appeared in
+.Fx 7.0 .
diff --git a/share/man/man4/mpr.4 b/share/man/man4/mpr.4
index e114ecfd077b..cce21113e5c2 100644
--- a/share/man/man4/mpr.4
+++ b/share/man/man4/mpr.4
@@ -65,9 +65,9 @@ Fusion-MPT 3/3.5 IT/IR
 .Tn SAS/PCIe
 controllers.
 .Sh HARDWARE
-These controllers are supported by the
+The
 .Nm
-driver:
+driver supports the following SATA/SAS/NVMe RAID controllers:
 .Pp
 .Bl -bullet -compact
 .It
diff --git a/share/man/man4/nda.4 b/share/man/man4/nda.4
index c4fa157af851..e45b2905462e 100644
--- a/share/man/man4/nda.4
+++ b/share/man/man4/nda.4
@@ -1,4 +1,6 @@
 .\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
 .\" Copyright (c) 2017 Netflix, Inc.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
@@ -23,7 +25,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd June 6, 2020
+.Dd October 2, 2025
 .Dt NDA 4
 .Os
 .Sh NAME
@@ -39,6 +41,14 @@ driver provides support for direct access devices, implementing the
 .Tn NVMe
 command protocol, that are attached to the system through a host adapter
 supported by the CAM subsystem.
+.Sh HARDWARE
+The
+.Nm
+driver supports NVMe
+.Pq Non-Volatile Memory Express
+storage devices connected via PCIe or over NVMF
+.Pq NVMe over Fabric
+via the CAM subsystem.
 .Sh SYSCTL VARIABLES
 The following variables are available as both
 .Xr sysctl 8
diff --git a/share/man/man4/sdhci.4 b/share/man/man4/sdhci.4
index 4a4e02539acd..1608d9c2fe1a 100644
--- a/share/man/man4/sdhci.4
+++ b/share/man/man4/sdhci.4
@@ -1,4 +1,6 @@
 .\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
 .\" Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
 .\" All rights reserved.
 .\"
@@ -22,7 +24,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd August 25, 2020
+.Dd October 3, 2025
 .Dt SDHCI 4
 .Os
 .Sh NAME
@@ -56,21 +58,28 @@ detaches it on card removing.
 .Sh HARDWARE
 The
 .Nm
-driver supports different specification compatible chips.
-The following chips have been verified to work:
+driver supports the SD Host Controller Specification.
+When attaching via the PCI bus,
+the controller is automatically configured.
+Many SoC chips provide a SDHCI controller directly mapped to I/O memory.
+For those, the controller may be configured using
+.Xr fdt 4
+or
+.Xr acpi 4
+methods, supplied by your board's vendor.
 .Pp
-.Bl -bullet -compact
-.It
-ENE CB712
-.It
-ENE CB714
-.It
-RICOH R5C822
-.It
-RICOH R5CE823
-.It
-TI PCIXX21/XX11/XX12
-.El
+Unlike most other drivers that support a generic standard,
+.Nm
+requires a large number of quirks to cope with hardware bugs,
+proprietary registers and poorly specified power management.
+While many chipsets from
+Intel, Xilinx, Rockchip, Frescale, Ricoh, and TI have these entries,
+suboptimal performance may result when using some controllers.
+Quirks and custom configuration are most often required
+when the device is configured via
+.Xr fdt 4
+or
+.Xr acpi 4 .
 .Sh SEE ALSO
 .Xr mmc 4 ,
 .Xr mmcsd 4
@@ -79,8 +88,3 @@ TI PCIXX21/XX11/XX12
 .Re
 .Sh AUTHORS
 .An Alexander Motin Aq Mt mav@FreeBSD.org
-.Sh BUGS
-Many of existing SD controller chips have some nonstandard requirements,
-proprietary registers and hardware bugs, requiring additional handling.
-ENE chips are handled to work fine, while some revisions of RICOH and TI
-controllers still do not see cards without some additional initialization.
diff --git a/share/man/man4/thunderbolt.4 b/share/man/man4/thunderbolt.4
new file mode 100644
index 000000000000..fd7cb1f3f338
--- /dev/null
+++ b/share/man/man4/thunderbolt.4
@@ -0,0 +1,22 @@
+.\"
+.\" Copyright (c) 2025 Alexander Ziaee
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
+.Dd October 2, 2025
+.Dt THUNDERBOLT 4
+.Os
+.Sh NAME
+.Nm thunderbolt
+.Nd USB4 controller driver
+.Sh SYNOPSIS
+.Cd device thunderbolt
+.Sh HARDWARE
+The
+.Nm
+driver supports Thunderbolt 3 and USB4 controllers.
+.Sh HISTORY
+The
+.Nm
+driver appeared in
+.Fx 15.0 .
diff --git a/share/man/man4/umass.4 b/share/man/man4/umass.4
index 03e8b6ff6ef1..db4e6f0890f2 100644
--- a/share/man/man4/umass.4
+++ b/share/man/man4/umass.4
@@ -1,3 +1,6 @@
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
 .\" Copyright (c) 1999
 .\"	Nick Hibma <n_hibma@FreeBSD.org>. All rights reserved.
 .\"
@@ -22,7 +25,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd January 27, 2020
+.Dd October 2, 2025
 .Dt UMASS 4
 .Os
 .Sh NAME
@@ -71,6 +74,19 @@ requires
 and
 .Xr scbus 4
 to be included in the kernel.
+.Sh HARDWARE
+The
+.Nm
+driver supports USB Mass Storage devices such as:
+.Pp
+.Bl -bullet -compact
+.It
+USB thumb drives
+.It
+USB hard disk drives
+.It
+USB floppy drives
+.El
 .Sh EXAMPLES
 .Bd -literal -offset indent
 device umass
@@ -92,7 +108,8 @@ camcontrol rescan 0:0:3
 Rescan all slots on a multi-slot flash reader, where the slots map to separate
 LUNs on a single SCSI ID.
 Typically only the first slot will be enabled at boot time.
-This assumes that the flash reader is the first SCSI bus in the system and has 4 slots.
+This assumes that
+the flash reader is the first SCSI bus in the system and has 4 slots.
 .Sh SEE ALSO
 .Xr cfumass 4 ,
 .Xr ehci 4 ,
@@ -101,7 +118,11 @@ This assumes that the flash reader is the first SCSI bus in the system and has 4
 .Xr usb 4 ,
 .Xr xhci 4 ,
 .Xr camcontrol 8
-.\".Sh HISTORY
+.Sh HISTORY
+The
+.Nm
+driver appeared in
+.Fx 4.3 .
 .Sh AUTHORS
 .An -nosplit
 The
diff --git a/share/man/man4/usbhid.4 b/share/man/man4/usbhid.4
index e5ba370cd025..0b2e7230e3f4 100644
--- a/share/man/man4/usbhid.4
+++ b/share/man/man4/usbhid.4
@@ -21,7 +21,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd July 30, 2025
+.Dd October 2, 2025
 .Dt USBHID 4
 .Os
 .Sh NAME
@@ -67,9 +67,13 @@ Default is 1.
 Debug output level, where 0 is debugging disabled and larger values increase
 debug message verbosity.
 Default is 0.
+Debug messages are printed on the system console and can be viewed using
+.Xr dmesg 8 .
 .El
 .Sh SEE ALSO
 .Xr ehci 4 ,
+.Xr hkbd 4 ,
+.Xr hms 4 ,
 .Xr ohci 4 ,
 .Xr uhci 4 ,
 .Xr usb 4 ,
@@ -80,6 +84,8 @@ The
 .Nm
 driver first appeared in
 .Fx 13.0 .
+It was enabled by default in
+.Fx 15.0 .
 .Sh AUTHORS
 .An -nosplit
 The
diff --git a/share/man/man4/vtnet.4 b/share/man/man4/vtnet.4
index 636ce4cc9b60..fd41b36882a6 100644
--- a/share/man/man4/vtnet.4
+++ b/share/man/man4/vtnet.4
@@ -22,7 +22,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd September 26, 2025
+.Dd September 30, 2025
 .Dt VTNET 4
 .Os
 .Sh NAME
@@ -54,6 +54,18 @@ TCP segmentation offload (TSO), TCP large receive offload (LRO),
 hardware VLAN tag stripping/insertion features, a multicast hash filter,
 as well as Jumbo Frames (up to 9216 bytes), which can be
 configured via the interface MTU setting.
+.Pp
+Two flavors of TCP LRO are supported:
+Hardware TCP LRO, which is performed by the host providing TCP segments larger
+than the MTU to the guest, and Software TCP LRO, which is performed by the
+network stack of the guest processing TCP segments in an optimized way.
+Only one flavour of TCP LRO should be used.
+Since hardware TCP LRO can have bad interactions with IP forwarding and
+software TCP LRO mitigates several drawbacks of hardware TCP LRO, the default
+setting is to disable hardware TCP LRO.
+See the loader tunable
+.Va hw.vtnet. Ns Ar X Ns Va .lro_disable .
+.Pp
 TCP/UDP receive checksum offload cannot be configured independently for IPv4
 and IPv6.
 Selecting an MTU larger than 1500 bytes with the
@@ -94,8 +106,8 @@ This tunable disables TCP segmentation offloading.
 The default value is 0.
 .It Va hw.vtnet.lro_disable
 .It Va hw.vtnet. Ns Ar X Ns Va .lro_disable
-This tunable disables large receive offload.
-The default value is 0.
+This tunable disables hardware TCP LRO.
+The default value is 1.
 .It Va hw.vtnet.mq_disable
 .It Va hw.vtnet. Ns Ar X Ns Va .mq_disable
 This tunable disables multiqueue.
@@ -119,11 +131,11 @@ This tunable sets the number of RX segments processed in one pass.
 The default value is 1024.
 .It Va hw.vtnet.lro_entry_count
 .It Va hw.vtnet. Ns Ar X Ns Va .lro_entry_count
-This tunable sets the software LRO entry count.
+This tunable sets the software TCP LRO entry count.
 The default value is 128, the minimum value is 8.
 .It Va hw.vtnet.lro_mbufq_depth
 .It Va hw.vtnet. Ns Ar X Ns Va .lro_mbufq_depth
-This tunable sets the depth of the software LRO mbuf queue.
+This tunable sets the depth of the software TCP LRO mbuf queue.
 The default value is 0.
 .It Va hw.vtnet.altq_disable
 This tunable disables ALTQ support, allowing the use of multiqueue instead.
diff --git a/share/man/man5/Makefile b/share/man/man5/Makefile
index 0f6559b236c6..c13a8b7afde2 100644
--- a/share/man/man5/Makefile
+++ b/share/man/man5/Makefile
@@ -73,9 +73,11 @@ MANGROUPS+=	BOOTLOADER
 BOOTLOADER=	device.hints.5
 BOOTLOADERPACKAGE=bootloader
 
-MANGROUPS+=	CLANG
-CLANG=		ar.5
-CLANGPACKAGE=	clang
+.if ${MK_TOOLCHAIN} != "no"
+MANGROUPS+=	TOOLCHAIN
+TOOLCHAIN=	ar.5
+TOOLCHAINPACKAGE=toolchain
+.endif
 
 MANGROUPS+=	LP
 LP=		hosts.lpd.5
diff --git a/share/man/man5/pf.conf.5 b/share/man/man5/pf.conf.5
index da02f10aac01..41410d6bc0fa 100644
--- a/share/man/man5/pf.conf.5
+++ b/share/man/man5/pf.conf.5
@@ -27,7 +27,7 @@
 .\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 .\" POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd August 28, 2025
+.Dd October 7, 2025
 .Dt PF.CONF 5
 .Os
 .Sh NAME
@@ -2377,7 +2377,7 @@ packets matching the same connection.
 .It Ar route-to
 The
 .Ar route-to
-option routes the packet to the specified interface with an optional address
+option routes the packet to the specified interface with an address
 for the next hop.
 When a
 .Ar route-to
@@ -3552,7 +3552,7 @@ hosts          = "all" |
 ipspec         = "any" | host | "{" host-list "}"
 host           = [ "!" ] ( address [ "/" mask-bits ] | "<" string ">" )
 redirhost      = address [ "/" mask-bits ]
-routehost      = "(" interface-name [ address [ "/" mask-bits ] ] ")"
+routehost      = "(" interface-name address [ "/" mask-bits ] ")"
 address        = ( interface-name | interface-group |
                  "(" ( interface-name | interface-group ) ")" |
                  hostname | ipv4-dotted-quad | ipv6-coloned-hex )
diff --git a/share/man/man5/rc.conf.5 b/share/man/man5/rc.conf.5
index de2181d638d1..edbfa937f8df 100644
--- a/share/man/man5/rc.conf.5
+++ b/share/man/man5/rc.conf.5
@@ -22,7 +22,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd July 15, 2025
+.Dd October 5, 2025
 .Dt RC.CONF 5
 .Os
 .Sh NAME
@@ -3867,27 +3867,6 @@ is set to
 these are the flags to pass to the
 .Xr sshd 8
 daemon.
-.It Va ftpd_program
-.Pq Vt str
-Path to the FTP server program
-.Pa ( /usr/libexec/ftpd
-is the default).
-.It Va ftpd_enable
-.Pq Vt bool
-Set to
-.Dq Li YES
-to start
-.Xr ftpd 8
-as a stand-alone daemon at system boot time.
-.It Va ftpd_flags
-.Pq Vt str
-If
-.Va ftpd_enable
-is set to
-.Dq Li YES ,
-these are the additional flags to pass to the
-.Xr ftpd 8
-daemon.
 .It Va watchdogd_enable
 .Pq Vt bool
 If set to
@@ -4584,20 +4563,16 @@ If set to
 .Dq Li YES ,
 delays the start of network-reliant services until
 .Va netwait_if
-is up and ICMP packets to a destination defined in
+is up, duplicate address discovery (DAD) has completed, and ICMP
+packets to a destination defined in
 .Va netwait_ip
 are flowing.
-Link state is examined first, followed by
+Link state is examined first, followed by DAD, then
 .Dq Li pinging
 an IP address to verify network usability.
 If no destination can be reached or timeouts are exceeded,
 network services are started anyway with no guarantee that
 the network is usable.
-Use of this variable requires both
-.Va netwait_ip
-and
-.Va netwait_if
-to be set.
 .It Va netwait_ip
 .Pq Vt str
 Empty by default.
@@ -4633,6 +4608,21 @@ interface if desired.
 Defines the total number of seconds to wait for link to become usable,
 polled at a 1-second interval.
 The default is 30.
+.It Va netwait_dad
+.Pq Vt str
+Set to
+.Dq Li NO
+by default.
+Set to
+.Dq Li YES
+to enable waiting for DAD to complete.
+.It Va netwait_dad_timeout
+.Pq Vt int
+Unset by default.
+Indicates the maximum number of seconds to wait for DAD to complete.
+If zero or unset, the timeout will be one more than the value of the
+.Va net.inet6.ip6.dad_count
+sysctl variable.
 .It Va rctl_enable
 .Pq Vt bool
 If set to
@@ -5116,7 +5106,6 @@ to
 .Xr cron 8 ,
 .Xr devfs 8 ,
 .Xr dhclient 8 ,
-.Xr ftpd 8 ,
 .Xr geli 8 ,
 .Xr hcsecd 8 ,
 .Xr ifconfig 8 ,
diff --git a/share/man/man5/src.conf.5 b/share/man/man5/src.conf.5
index ded16c9cf436..5c8ae5b83e5f 100644
--- a/share/man/man5/src.conf.5
+++ b/share/man/man5/src.conf.5
@@ -1,5 +1,5 @@
 .\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman.
-.Dd September 10, 2025
+.Dd September 25, 2025
 .Dt SRC.CONF 5
 .Os
 .Sh NAME
@@ -242,8 +242,7 @@ is set explicitly)
 Build some programs without
 .Xr libblacklist 3
 support, like
-.Xr fingerd 8 ,
-.Xr ftpd 8 ,
+.Xr fingerd 8
 and
 .Xr sshd 8 .
 .It Va WITHOUT_BLUETOOTH
@@ -720,9 +719,7 @@ Do not build
 .Xr freebsd-update 8 .
 .It Va WITHOUT_FTP
 Do not build or install
-.Xr ftp 1
-and
-.Xr ftpd 8 .
+.Xr ftp 1 .
 .It Va WITHOUT_GAMES
 Do not build games.
 .It Va WITHOUT_GNU_DIFF
@@ -1481,10 +1478,9 @@ When set, these options are also in effect:
 is set explicitly)
 .El
 .It Va WITHOUT_PAM_SUPPORT
-Build some programs without PAM support, particularly
-.Xr ftpd 8
-and
-.Xr ppp 8 .
+Build
+.Xr ppp 8
+without PAM support.
 .It Va WITHOUT_PF
 Do not build PF firewall package.
 When set, it enforces these options:
diff --git a/share/man/man7/arch.7 b/share/man/man7/arch.7
index b29fedbfd4ec..5de441aed699 100644
--- a/share/man/man7/arch.7
+++ b/share/man/man7/arch.7
@@ -24,7 +24,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd July 14, 2025
+.Dd October 1, 2025
 .Dt ARCH 7
 .Os
 .Sh NAME
@@ -183,9 +183,9 @@ On all supported architectures:
 Integers are represented in two's complement.
 Alignment of integer and pointer types is natural, that is,
 the address of the variable must be congruent to zero modulo the type size.
-Most ILP32 ABIs, except
-.Dv arm ,
-require only 4-byte alignment for 64-bit integers.
+The sole exception is that
+.Dv i386
+requires only 4-byte alignment for 64-bit integers.
 .Pp
 Machine-dependent type sizes:
 .Bl -column -offset indent "Architecture" "void *" "long double" "time_t"
@@ -345,9 +345,6 @@ Common type size and endianness macros:
 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
 .It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
-.Dv PDP11_ENDIAN
-is not used on
-.Fx .
 .El
 .Pp
 Architecture-specific macros:
diff --git a/share/man/man7/hier.7 b/share/man/man7/hier.7
index 814f5b769be8..c438511678d4 100644
--- a/share/man/man7/hier.7
+++ b/share/man/man7/hier.7
@@ -28,7 +28,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd August 18, 2025
+.Dd September 25, 2025
 .Dt HIER 7
 .Os
 .Sh NAME
@@ -892,9 +892,6 @@ last login log; see
 .It Pa utx.log
 login/logout log; see
 .Xr getutxent 3
-.It Pa xferlog
-default log for
-.Xr ftpd 8
 .El
 .Pp
 .It Pa mail/
@@ -952,9 +949,6 @@ serial device locks; see
 .Xr uucplock 3
 .It Pa lpd/
 line printer spooler daemon spool
-.It Pa ftp/
-ftp root directory; see
-.Xr ftpd 8
 .It Pa mqueue/
 undelivered mail queue for
 .Xr sendmail 8
diff --git a/share/man/man7/security.7 b/share/man/man7/security.7
index cdb4d066d3e6..f1035fd093d5 100644
--- a/share/man/man7/security.7
+++ b/share/man/man7/security.7
@@ -364,7 +364,6 @@ There are a number of other servers that typically do not run in sandboxes:
 .Xr sendmail 8 ,
 .Xr popper 8 ,
 .Xr imapd 8 ,
-.Xr ftpd 8 ,
 and others.
 There are alternatives to
 some of these, but installing them may require more work than you are willing
diff --git a/share/man/man8/intro.8 b/share/man/man8/intro.8
index 39b72af5f741..bfa7d026afbb 100644
--- a/share/man/man8/intro.8
+++ b/share/man/man8/intro.8
@@ -52,8 +52,6 @@ and recover files when disks die an untimely death
 .\" consulted when formatting disks and tapes.
 Network related services like
 .Xr inetd 8
-and
-.Xr ftpd 8
 are also described.
 .Pp
 All commands set an exit status.
diff --git a/share/man/man9/Makefile b/share/man/man9/Makefile
index d2282b3e5a80..3bccc92572d6 100644
--- a/share/man/man9/Makefile
+++ b/share/man/man9/Makefile
@@ -2455,6 +2455,9 @@ MLINKS+=vm_page_insert.9 vm_page_remove.9
 MLINKS+=vm_page_wire.9 vm_page_unwire.9 \
 	vm_page_wire.9 vm_page_unwire_noq.9 \
 	vm_page_wire.9 vm_page_wire_mapped.9
+MLINKS+=vn_fullpath.9 vn_fullpath_jail.9 \
+	vn_fullpath.9 vn_fullpath_global.9 \
+	vn_fullpath.9 vn_fullpath_hardlink.9
 MLINKS+=VOP_ACCESS.9 VOP_ACCESSX.9
 MLINKS+=VOP_ATTRIB.9 VOP_GETATTR.9 \
 	VOP_ATTRIB.9 VOP_SETATTR.9 \
diff --git a/share/man/man9/namei.9 b/share/man/man9/namei.9
index 5bdffce8c360..a42043587432 100644
--- a/share/man/man9/namei.9
+++ b/share/man/man9/namei.9
@@ -31,7 +31,7 @@
 .\" If you integrate this manpage in another OS, I'd appreciate a note
 .\"	- eivind@FreeBSD.org
 .\"
-.Dd May 16, 2025
+.Dd September 30, 2025
 .Dt NAMEI 9
 .Os
 .Sh NAME
@@ -206,12 +206,6 @@ This flag allows the
 function to return the parent (directory) vnode in an unlocked state.
 The parent vnode must be released separately by using
 .Xr vrele 9 .
-.It Dv WANTPARENT
-This flag allows the
-.Fn namei
-function to return the parent (directory) vnode in an unlocked state.
-The parent vnode must be released separately by using
-.Xr vrele 9 .
 .It Dv FAILIFEXISTS
 Makes the
 .Nm
diff --git a/share/man/man9/vn_fullpath.9 b/share/man/man9/vn_fullpath.9
index 116f519ec8aa..9815abc3c86c 100644
--- a/share/man/man9/vn_fullpath.9
+++ b/share/man/man9/vn_fullpath.9
@@ -1,6 +1,13 @@
+.\"-
+.\" SPDX-License-Identifier: BSD-2-Clause
 .\"
 .\" Copyright (c) 2003 Robert N. M. Watson.
 .\" All rights reserved.
+.\" Copyright (c) 2025 The FreeBSD Foundation
+.\"
+.\" Portions of this documentation were written by Olivier Certner
+.\" <olce@FreeBSD.org> at Kumacom SARL under sponsorship from the FreeBSD
+.\" Foundation.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
 .\" modification, are permitted provided that the following conditions
@@ -25,7 +32,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 .\" DAMAGE.
 .\"
-.Dd June 15, 2021
+.Dd September 29, 2025
 .Dt VN_FULLPATH 9
 .Os
 .Sh NAME
@@ -35,23 +42,64 @@
 .In sys/param.h
 .In sys/vnode.h
 .Ft int
-.Fo vn_fullpath
-.Fa "struct vnode *vp" "char **retbuf" "char **freebuf"
+.Fn vn_fullpath "struct vnode *vp" "char **retbuf" "char **freebuf"
+.Ft int
+.Fn vn_fullpath_jail "struct vnode *vp" "char **retbuf" "char **freebuf"
+.Ft int
+.Fn vn_fullpath_global "struct vnode *vp" "char **retbuf" "char **freebuf"
+.Ft int
+.Fo vn_fullpath_hardlink
+.Fa "struct vnode *vp" "struct vnode *dvp"
+.Fa "const char *hrdl_name" "size_t hrdl_name_length"
+.Fa "char **retbuf" "char **freebuf" "size_t *buflen"
 .Fc
 .Sh DESCRIPTION
 The
+.Fn vn_fullpath ,
+.Fn vn_fullpath_jail ,
+.Fn vn_fullpath_global
+and
+.Fn vn_fullpath_hardlink
+functions make a
+.Dq best effort
+attempt at generating a string pathname for the passed vnode.
+They differ in which directory the returned path is relative to, except for
+.Fn vn_fullpath_hardlink
+which behaves like
 .Fn vn_fullpath
-function makes a
-.Dq "best effort"
-attempt to generate a string pathname for
-the passed vnode; the resulting path, if any, will be relative to
-the root directory of the process associated with the passed thread pointer.
+in this respect and is described at the end.
+.Pp
 The
 .Fn vn_fullpath
-function
-is implemented by inspecting the VFS name cache, and attempting to
-reconstruct a path from the process root to the object.
+function returns a path relative to the root directory of the process associated
+with the passed thread pointer.
+That root directory is either the system's or the thread's process' containing
+jail's root directory, or some descendant directory of such established by some
+.Xr chroot 2
+call.
+The
+.Fn vn_fullpath_jail
+function returns a path relative to the passed thread's process' current jail's
+root, ignoring intervening
+.Xr chroot 2
+calls possibly made inside that jail.
+The
+.Fn vn_fullpath_global
+function returns the full path from the system root, ignoring all jail roots and
+.Xr chroot 2
+calls.
+.Pp
+Paths that the kernel intends to communicate to the passed user thread should
+exclusively be obtained via
+.Fn vn_fullpath .
+Paths obtained via
+.Fn vn_fullpath_jail
+or
+.Fn vn_fullpath_global
+are only useful for specific kernel checks or auditing purposes.
 .Pp
+All these functions are implemented by inspecting the VFS name cache, and
+attempting to reconstruct a path from the process root to the object.
 This process is necessarily unreliable for several reasons: intermediate
 entries in the path may not be found in the cache; files may have more
 than one name (hard links), not all file systems use the name cache
@@ -64,7 +112,7 @@ a vnode pointer value, or a device number and inode number.
 Code consuming the results of this function should anticipate (and
 properly handle) failure.
 .Pp
-Its arguments are:
+These functions take the following arguments:
 .Bl -tag -width ".Fa freebuf"
 .It Fa vp
 The vnode to search for.
@@ -72,17 +120,13 @@ No need to be locked by the caller.
 .It Fa retbuf
 Pointer to a
 .Vt "char *"
-that
-.Fn vn_fullpath
-may (on success) point at a newly
-allocated buffer containing the resulting pathname.
+that may be set (on success) to point at a newly allocated buffer containing the
+resulting pathname.
 .It Fa freebuf
 Pointer to a
 .Vt "char *"
-that
-.Fn vn_fullpath
-may (on success) point at a buffer
-to be freed, when the caller is done with
+that may be set (on success) to point at a buffer to be freed, when the caller
+is done with
 .Fa retbuf .
 .El
 .Pp
@@ -110,11 +154,43 @@ and if so, invoke
 .Xr free 9
 with a pool type of
 .Dv M_TEMP .
+.Pp
+The
+.Fn vn_fullpath_hardlink
+function is a convenience wrapper which automatically appends the hardlink name
+passed via arguments
+.Fa hrdl_name
+and
+.Fa hrdl_name_length
+to the result of calling
+.Fn vn_fullpath
+on the vnode's parent directory.
+It requires the results of a prior call to
+.Xr namei 9
+with flag
+.Dv WANTPARENT
+to be passed in the
+.Fa vp
+and
+.Fa dvp
+arguments.
+Argument
+.Fa buflen
+must point to a valid storage containing the size of the desired buffer, which
+will be reduced to
+.Dv MAXPATHLEN
+if in excess of it.
 .Sh RETURN VALUES
 If the vnode is successfully converted to a pathname, 0 is returned;
 otherwise, an error number is returned.
 .Sh SEE ALSO
 .Xr free 9
 .Sh AUTHORS
-This manual page was written by
-.An Robert Watson Aq Mt rwatson@FreeBSD.org .
+.An -nosplit
+This manual page was initally written by
+.An Robert Watson Aq Mt rwatson@FreeBSD.org
+to describe the
+.Fn vn_fullpath
+function.
+The descriptions of the other related functions were added by
+.An Olivier Certner Aq Mt olce@FreeBSD.org .
diff --git a/share/misc/committers-doc.dot b/share/misc/committers-doc.dot
index ba4c229bc658..8c9fe4cf9991 100644
--- a/share/misc/committers-doc.dot
+++ b/share/misc/committers-doc.dot
@@ -106,6 +106,7 @@ rene [label="Rene Ladan\nrene@FreeBSD.org\n2008/11/03"]
 ryusuke [label="Ryusuke Suzuki\nryusuke@FreeBSD.org\n2009/12/21"]
 salvadore [label="Lorenzo Salvadore\nsalvadore@FreeBSD.org\n2023/03/20"]
 trhodes [label="Tom Rhodes\ntrhodes@FreeBSD.org\n2002/03/25"]
+vladlen [label="Vladlen Popolitov\nvladlen@FreeBSD.org\n2025/09/09"]
 ygy [label="Guangyuan Yang\nygy@FreeBSD.org\n2017/09/18"]
 ziaee [label="Alexander Ziaee\nziaee@FreeBSD.org\n2024/12/30"]
 
@@ -208,6 +209,7 @@ marck -> pluknet
 marck -> taras
 
 maxim -> taras
+maxim -> vladlen
 
 mheinen -> jkois
 
diff --git a/share/misc/committers-ports.dot b/share/misc/committers-ports.dot
index fb6c168f1425..81870cf98af5 100644
--- a/share/misc/committers-ports.dot
+++ b/share/misc/committers-ports.dot
@@ -292,6 +292,7 @@ tagattie [label="Hiroki Tagato\ntagattie@FreeBSD.org\n2020/04/01"]
 tcberner [label="Tobias C. Berner\ntcberner@FreeBSD.org\n2016/07/06"]
 tdb [label="Tim Bishop\ntdb@FreeBSD.org\n2005/11/30"]
 thierry [label="Thierry Thomas\nthierry@FreeBSD.org\n2004/03/15"]
+tiga [label="Tiago Gasiba\ntiga@FreeBSD.org\n2025/09/28"]
 tijl [label="Tijl Coosemans\ntijl@FreeBSD.org\n2013/03/27"]
 timur [label="Timur Bakeyev\ntimur@FreeBSD.org\n2007/06/07"]
 tobik [label="Tobias Kortkamp\ntobik@FreeBSD.org\n2017/02/08"]
@@ -448,6 +449,7 @@ eadler -> tj
 eadler -> vg
 
 eduardo -> fuz
+eduardo -> tiga
 
 edwin -> cperciva
 edwin -> erwin
@@ -487,6 +489,7 @@ flo -> fuz
 flo -> jase
 flo -> jbeich
 flo -> grembo
+flo -> tiga
 
 fluffy -> vishwin
 
diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk
index 1225d690e908..d11b8994dcd7 100644
--- a/share/mk/bsd.cpu.mk
+++ b/share/mk/bsd.cpu.mk
@@ -396,19 +396,19 @@ MACHINE_ABI+=	hard-float
 # (which uses arm64/arm).
 .if ${MACHINE_ARCH:M*64*} || \
     (defined(BOOTSTRAPPING) && ${.MAKE.OS} == "Darwin" && ${MACHINE} == "arm64")
-MACHINE_ABI+=  long64
+MACHINE_ABI+=	long64
 .else
-MACHINE_ABI+=  long32
+MACHINE_ABI+=	long32
 .endif
 .if ${MACHINE_ABI:Mlong64}
-MACHINE_ABI+=  ptr64
+MACHINE_ABI+=	ptr64
 .else
-MACHINE_ABI+=  ptr32
+MACHINE_ABI+=	ptr32
 .endif
 .if ${MACHINE_ARCH} == "i386"
-MACHINE_ABI+=  time32
+MACHINE_ABI+=	time32
 .else
-MACHINE_ABI+=  time64
+MACHINE_ABI+=	time64
 .endif
 .if ${MACHINE_ARCH:Mpowerpc*} && !${MACHINE_ARCH:M*le}
 MACHINE_ABI+=	big-endian
diff --git a/share/mk/bsd.nls.mk b/share/mk/bsd.nls.mk
index bd13fe56679d..5a28e1cdd026 100644
--- a/share/mk/bsd.nls.mk
+++ b/share/mk/bsd.nls.mk
@@ -1,6 +1,8 @@
 #
-# This include file <bsd.nls.mk> handles building and installing Native
-# Language Support (NLS) catalogs
+# Handle building and installing Native Language Support (NLS) catalogs.
+# This is implemented using a <bsd.files.mk> files group called "NLS",
+# so any per-group options that bsd.files.mk supports can be used here
+# with the prefix "NLS".
 #
 # +++ variables +++
 #
@@ -17,6 +19,9 @@
 # NLSMODE	National Language Support files mode. [${NOBINMODE}]
 #
 # NLSOWN	National Language Support files owner. [${SHAREOWN}]
+#
+# NLSPACKAGE	Package to install the NLS files in.
+#		[${PACKAGE}, or "utilities" if not set]
 
 .if !target(__<bsd.init.mk>__)
 .error bsd.nls.mk cannot be included directly.
diff --git a/share/mk/src.libnames.mk b/share/mk/src.libnames.mk
index 95cd3b02d8e4..3e108591251a 100644
--- a/share/mk/src.libnames.mk
+++ b/share/mk/src.libnames.mk
@@ -425,7 +425,7 @@ _DP_kadm5clnt=	com_err krb5 roken
 _DP_kadm5srv=	com_err hdb krb5 roken
 _DP_heimntlm=	crypto com_err krb5 roken
 _DP_hx509=	asn1 com_err crypto roken wind
-_DP_hdb=	asn1 com_err krb5 roken sqlite3
+_DP_hdb=	asn1 com_err krb5 roken sqlite3 heimbase
 _DP_asn1=	com_err roken
 _DP_kdc=	roken hdb hx509 krb5 heimntlm asn1 crypto
 _DP_wind=	com_err roken
diff --git a/stand/liblua/Makefile b/stand/liblua/Makefile
index ce7eb89fe494..b1c34ec0a466 100644
--- a/stand/liblua/Makefile
+++ b/stand/liblua/Makefile
@@ -24,7 +24,7 @@ SRCS+=	lauxlib.c lbaselib.c lstrlib.c loadlib.c
 SRCS+=	lerrno.c lpager.c lstd.c lutils.c
 SRCS+=	gfx_utils.c
 
-.PATH:	${FLUASRC}/modules
+.PATH:	${FLUASRC}/lfs
 SRCS+=	lfs.c
 .PATH:	${FLUALIB}/libhash
 SRCS+=	lhash.c
diff --git a/stand/libsa/smbios.c b/stand/libsa/smbios.c
index 32cd198a9537..73b49a111f89 100644
--- a/stand/libsa/smbios.c
+++ b/stand/libsa/smbios.c
@@ -186,14 +186,17 @@ smbios_sigsearch(const caddr_t addr, const uint32_t len)
 		     */
 		    SMBIOS_GET8(cp, 0x0a) != 0 &&
 		    smbios_checksum(cp, SMBIOS_GET8(cp, 0x06)) == 0) {
-#ifdef __ILP32__
+#if __SIZEOF_SIZE_T__ < 8
 			uint64_t end_addr;
 
 			end_addr = SMBIOS_GET64(cp, 0x10) + /* Start address. */
 			    SMBIOS_GET32(cp, 0x0c); /* Maximum size. */
-			/* Is the table (or part of it) located above 4G? */
-			if (end_addr >= (uint64_t)1 << 32)
-				/* Can't access it with 32-bit addressing. */
+			/*
+			 * Is the table (or part of it) located above what we
+			 * can address?
+			 */
+			if ((size_t)end_addr != end_addr)
+				/* Yes, give it up. */
 				continue;
 #endif
 			smbios.is_64bit_ep = 1;
diff --git a/stand/loader.mk b/stand/loader.mk
index 4073e523e552..e26ba1401912 100644
--- a/stand/loader.mk
+++ b/stand/loader.mk
@@ -89,7 +89,7 @@ SRCS+=	interp_lua.c
 .include "${BOOTSRC}/lua.mk"
 LDR_INTERP=	${LIBLUA}
 LDR_INTERP32=	${LIBLUA32}
-CFLAGS.interp_lua.c= -DLUA_PATH=\"${LUAPATH}\" -I${FLUASRC}/modules
+CFLAGS.interp_lua.c= -DLUA_PATH=\"${LUAPATH}\" -I${FLUASRC}/lfs
 .elif ${LOADER_INTERP} == "4th"
 SRCS+=	interp_forth.c
 .include "${BOOTSRC}/ficl.mk"
diff --git a/stand/lua/cli.lua b/stand/lua/cli.lua
index 6832da0a31a5..dda8c3da4c89 100644
--- a/stand/lua/cli.lua
+++ b/stand/lua/cli.lua
@@ -30,18 +30,6 @@ local core = require("core")
 
 local cli = {}
 
-if not pager then
-	-- shim for the pager module that just doesn't do it.
-	-- XXX Remove after 12.2 goes EoL.
-	pager = {
-		open = function() end,
-		close = function() end,
-		output = function(str)
-			printc(str)
-		end,
-	}
-end
-
 -- Internal function
 -- Parses arguments to boot and returns two values: kernel_name, argstr
 -- Defaults to nil and "" respectively.
@@ -247,9 +235,17 @@ cli["disable-device"] = function(...)
 		return
 	end
 
+	if #argv > 1 then
+		print("Too many arguments")
+		print("usage error: disable-device device")
+		return
+	end
+
 	d, u = string.match(argv[1], "(%w*%a)(%d+)")
-	if d ~= nil then
+	if d ~= nil and u ~= nil then
 		loader.setenv("hint." .. d .. "." .. u .. ".disabled", "1")
+	else
+		print("Cannot parse " .. argv[1] .." into driver and unit number.")
 	end
 end
 
diff --git a/stand/lua/core.lua b/stand/lua/core.lua
index f42be6fbebb7..ad417e5f97e5 100644
--- a/stand/lua/core.lua
+++ b/stand/lua/core.lua
@@ -413,7 +413,7 @@ end
 
 function core.isSingleUserBoot()
 	local single_user = loader.getenv("boot_single")
-	return single_user ~= nil and single_user:lower() == "yes"
+	return single_user ~= nil and single_user:lower() ~= "no"
 end
 
 function core.isUEFIBoot()
diff --git a/sys/amd64/acpica/acpi_wakeup.c b/sys/amd64/acpica/acpi_wakeup.c
index 99565fbb69ca..8cada2f4f911 100644
--- a/sys/amd64/acpica/acpi_wakeup.c
+++ b/sys/amd64/acpica/acpi_wakeup.c
@@ -74,7 +74,7 @@ extern int		acpi_susp_bounce;
 extern struct susppcb	**susppcbs;
 static cpuset_t		suspcpus;
 
-static void		acpi_stop_beep(void *);
+static void		acpi_stop_beep(void *, enum power_stype);
 
 static int		acpi_wakeup_ap(struct acpi_softc *, int);
 static void		acpi_wakeup_cpus(struct acpi_softc *);
@@ -88,7 +88,7 @@ static void		acpi_wakeup_cpus(struct acpi_softc *);
 } while (0)
 
 static void
-acpi_stop_beep(void *arg)
+acpi_stop_beep(void *arg, enum power_stype stype)
 {
 
 	if (acpi_resume_beep != 0)
diff --git a/sys/amd64/include/param.h b/sys/amd64/include/param.h
index 5a9c3162e14c..0654bb9de790 100644
--- a/sys/amd64/include/param.h
+++ b/sys/amd64/include/param.h
@@ -150,6 +150,15 @@
     (((va) >= kva_layout.dmap_low && (va) < kva_layout.dmap_high) || \
     ((va) >= kva_layout.km_low && (va) < kva_layout.km_high))
 
-#define SC_TABLESIZE    1024                     /* Must be power of 2. */
+/*
+ * Must be power of 2.
+ *
+ * Perhaps should be autosized on boot based on found ncpus.
+ */
+#if MAXCPU > 256
+#define SC_TABLESIZE    2048
+#else
+#define SC_TABLESIZE    1024
+#endif
 
 #endif /* !_AMD64_INCLUDE_PARAM_H_ */
diff --git a/sys/arm/allwinner/aw_gpio.c b/sys/arm/allwinner/aw_gpio.c
index f1b6f0bc9193..c90d61f7b45e 100644
--- a/sys/arm/allwinner/aw_gpio.c
+++ b/sys/arm/allwinner/aw_gpio.c
@@ -1531,6 +1531,10 @@ static device_method_t aw_gpio_methods[] = {
 	DEVMETHOD(device_attach,	aw_gpio_attach),
 	DEVMETHOD(device_detach,	aw_gpio_detach),
 
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* Interrupt controller interface */
 	DEVMETHOD(pic_disable_intr,	aw_gpio_pic_disable_intr),
 	DEVMETHOD(pic_enable_intr,	aw_gpio_pic_enable_intr),
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_gpio.c b/sys/arm/broadcom/bcm2835/bcm2835_gpio.c
index 93ee5d7c8bd3..ff5c4043dd86 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_gpio.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_gpio.c
@@ -1321,6 +1321,10 @@ static device_method_t bcm_gpio_methods[] = {
 	DEVMETHOD(device_attach,	bcm_gpio_attach),
 	DEVMETHOD(device_detach,	bcm_gpio_detach),
 
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* GPIO protocol */
 	DEVMETHOD(gpio_get_bus,		bcm_gpio_get_bus),
 	DEVMETHOD(gpio_pin_max,		bcm_gpio_pin_max),
diff --git a/sys/arm/freescale/imx/imx_gpio.c b/sys/arm/freescale/imx/imx_gpio.c
index 3b19ef1b5e67..60b8d79ab27e 100644
--- a/sys/arm/freescale/imx/imx_gpio.c
+++ b/sys/arm/freescale/imx/imx_gpio.c
@@ -918,6 +918,10 @@ static device_method_t imx51_gpio_methods[] = {
 	DEVMETHOD(device_detach,	imx51_gpio_detach),
 
 #ifdef INTRNG
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* Interrupt controller interface */
 	DEVMETHOD(pic_disable_intr,	gpio_pic_disable_intr),
 	DEVMETHOD(pic_enable_intr,	gpio_pic_enable_intr),
diff --git a/sys/arm/mv/mvebu_gpio.c b/sys/arm/mv/mvebu_gpio.c
index 4cc9b7030a65..c27d5a204052 100644
--- a/sys/arm/mv/mvebu_gpio.c
+++ b/sys/arm/mv/mvebu_gpio.c
@@ -839,6 +839,10 @@ static device_method_t mvebu_gpio_methods[] = {
 	DEVMETHOD(device_attach,	mvebu_gpio_attach),
 	DEVMETHOD(device_detach,	mvebu_gpio_detach),
 
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* Interrupt controller interface */
 	DEVMETHOD(pic_disable_intr,	mvebu_gpio_pic_disable_intr),
 	DEVMETHOD(pic_enable_intr,	mvebu_gpio_pic_enable_intr),
diff --git a/sys/arm/nvidia/tegra_gpio.c b/sys/arm/nvidia/tegra_gpio.c
index aa34537352be..ce24fccd3a40 100644
--- a/sys/arm/nvidia/tegra_gpio.c
+++ b/sys/arm/nvidia/tegra_gpio.c
@@ -853,6 +853,10 @@ static device_method_t tegra_gpio_methods[] = {
 	DEVMETHOD(device_attach,	tegra_gpio_attach),
 	DEVMETHOD(device_detach,	tegra_gpio_detach),
 
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* Interrupt controller interface */
 	DEVMETHOD(pic_disable_intr,	tegra_gpio_pic_disable_intr),
 	DEVMETHOD(pic_enable_intr,	tegra_gpio_pic_enable_intr),
diff --git a/sys/arm/ti/ti_gpio.c b/sys/arm/ti/ti_gpio.c
index 01b9597a4418..b7e9909b8548 100644
--- a/sys/arm/ti/ti_gpio.c
+++ b/sys/arm/ti/ti_gpio.c
@@ -1048,6 +1048,10 @@ static device_method_t ti_gpio_methods[] = {
 	DEVMETHOD(device_attach, ti_gpio_attach),
 	DEVMETHOD(device_detach, ti_gpio_detach),
 
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* GPIO protocol */
 	DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
 	DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index da051e8f7c8a..393d6d89da0c 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2180,6 +2180,7 @@
 #define	OSLAR_EL1_CRn			1
 #define	OSLAR_EL1_CRm			0
 #define	OSLAR_EL1_op2			4
+#define	OSLAR_OSLK			(0x1ul << 0)
 
 /* OSLSR_EL1 */
 #define	OSLSR_EL1_op0			2
@@ -2187,6 +2188,10 @@
 #define	OSLSR_EL1_CRn			1
 #define	OSLSR_EL1_CRm			1
 #define	OSLSR_EL1_op2			4
+#define	OSLSR_OSLM_1			(0x1ul << 3)
+#define	OSLSR_nTT			(0x1ul << 2)
+#define	OSLSR_OSLK			(0x1ul << 1)
+#define	OSLSR_OSLM_0			(0x1ul << 0)
 
 /* PAR_EL1 - Physical Address Register */
 #define	PAR_F_SHIFT		0
diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 04e15b55b218..8feabd2b981b 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -247,6 +247,54 @@
 #define	ICC_SRE_EL2_SRE		(1UL << 0)
 #define	ICC_SRE_EL2_EN		(1UL << 3)
 
+/* MDCR_EL2 - Hyp Debug Control Register */
+#define	MDCR_EL2_HPMN_MASK	0x1f
+#define	MDCR_EL2_HPMN_SHIFT	0
+#define	MDCR_EL2_TPMCR_SHIFT	5
+#define	MDCR_EL2_TPMCR		(0x1UL << MDCR_EL2_TPMCR_SHIFT)
+#define	MDCR_EL2_TPM_SHIFT	6
+#define	MDCR_EL2_TPM		(0x1UL << MDCR_EL2_TPM_SHIFT)
+#define	MDCR_EL2_HPME_SHIFT	7
+#define	MDCR_EL2_HPME		(0x1UL << MDCR_EL2_HPME_SHIFT)
+#define	MDCR_EL2_TDE_SHIFT	8
+#define	MDCR_EL2_TDE		(0x1UL << MDCR_EL2_TDE_SHIFT)
+#define	MDCR_EL2_TDA_SHIFT	9
+#define	MDCR_EL2_TDA		(0x1UL << MDCR_EL2_TDA_SHIFT)
+#define	MDCR_EL2_TDOSA_SHIFT	10
+#define	MDCR_EL2_TDOSA		(0x1UL << MDCR_EL2_TDOSA_SHIFT)
+#define	MDCR_EL2_TDRA_SHIFT	11
+#define	MDCR_EL2_TDRA		(0x1UL << MDCR_EL2_TDRA_SHIFT)
+#define	MDCR_EL2_E2PB_SHIFT	12
+#define	MDCR_EL2_E2PB_MASK	(0x3UL << MDCR_EL2_E2PB_SHIFT)
+#define	MDCR_EL2_TPMS_SHIFT	14
+#define	MDCR_EL2_TPMS		(0x1UL << MDCR_EL2_TPMS_SHIFT)
+#define	MDCR_EL2_EnSPM_SHIFT	15
+#define	MDCR_EL2_EnSPM		(0x1UL << MDCR_EL2_EnSPM_SHIFT)
+#define	MDCR_EL2_HPMD_SHIFT	17
+#define	MDCR_EL2_HPMD		(0x1UL << MDCR_EL2_HPMD_SHIFT)
+#define	MDCR_EL2_TTRF_SHIFT	19
+#define	MDCR_EL2_TTRF		(0x1UL << MDCR_EL2_TTRF_SHIFT)
+#define	MDCR_EL2_HCCD_SHIFT	23
+#define	MDCR_EL2_HCCD		(0x1UL << MDCR_EL2_HCCD_SHIFT)
+#define	MDCR_EL2_E2TB_SHIFT	24
+#define	MDCR_EL2_E2TB_MASK	(0x3UL << MDCR_EL2_E2TB_SHIFT)
+#define	MDCR_EL2_HLP_SHIFT	26
+#define	MDCR_EL2_HLP		(0x1UL << MDCR_EL2_HLP_SHIFT)
+#define	MDCR_EL2_TDCC_SHIFT	27
+#define	MDCR_EL2_TDCC		(0x1UL << MDCR_EL2_TDCC_SHIFT)
+#define	MDCR_EL2_MTPME_SHIFT	28
+#define	MDCR_EL2_MTPME		(0x1UL << MDCR_EL2_MTPME_SHIFT)
+#define	MDCR_EL2_HPMFZO_SHIFT	29
+#define	MDCR_EL2_HPMFZO		(0x1UL << MDCR_EL2_HPMFZO_SHIFT)
+#define	MDCR_EL2_PMSSE_SHIFT	30
+#define	MDCR_EL2_PMSSE_MASK	(0x3UL << MDCR_EL2_PMSSE_SHIFT)
+#define	MDCR_EL2_HPMFZS_SHIFT	36
+#define	MDCR_EL2_HPMFZS		(0x1UL << MDCR_EL2_HPMFZS_SHIFT)
+#define	MDCR_EL2_PMEE_SHIFT	40
+#define	MDCR_EL2_PMEE_MASK	(0x3UL << MDCR_EL2_PMEE_SHIFT)
+#define	MDCR_EL2_EBWE_SHIFT	43
+#define	MDCR_EL2_EBWE		(0x1UL << MDCR_EL2_EBWE_SHIFT)
+
 /* SCTLR_EL2 - System Control Register */
 #define	SCTLR_EL2_RES1		0x30c50830
 #define	SCTLR_EL2_M_SHIFT	0
@@ -356,52 +404,4 @@
 /* Assumed to be 0 by locore.S */
 #define	VTTBR_HOST		0x0000000000000000
 
-/* MDCR_EL2 - Hyp Debug Control Register */
-#define	MDCR_EL2_HPMN_MASK	0x1f
-#define	MDCR_EL2_HPMN_SHIFT	0
-#define	MDCR_EL2_TPMCR_SHIFT	5
-#define	MDCR_EL2_TPMCR		(0x1UL << MDCR_EL2_TPMCR_SHIFT)
-#define	MDCR_EL2_TPM_SHIFT	6
-#define	MDCR_EL2_TPM		(0x1UL << MDCR_EL2_TPM_SHIFT)
-#define	MDCR_EL2_HPME_SHIFT	7
-#define	MDCR_EL2_HPME		(0x1UL << MDCR_EL2_HPME_SHIFT)
-#define	MDCR_EL2_TDE_SHIFT	8
-#define	MDCR_EL2_TDE		(0x1UL << MDCR_EL2_TDE_SHIFT)
-#define	MDCR_EL2_TDA_SHIFT	9
-#define	MDCR_EL2_TDA		(0x1UL << MDCR_EL2_TDA_SHIFT)
-#define	MDCR_EL2_TDOSA_SHIFT	10
-#define	MDCR_EL2_TDOSA		(0x1UL << MDCR_EL2_TDOSA_SHIFT)
-#define	MDCR_EL2_TDRA_SHIFT	11
-#define	MDCR_EL2_TDRA		(0x1UL << MDCR_EL2_TDRA_SHIFT)
-#define	MDCR_E2PB_SHIFT		12
-#define	MDCR_E2PB_MASK		(0x3UL << MDCR_E2PB_SHIFT)
-#define	MDCR_TPMS_SHIFT		14
-#define	MDCR_TPMS		(0x1UL << MDCR_TPMS_SHIFT)
-#define	MDCR_EnSPM_SHIFT	15
-#define	MDCR_EnSPM		(0x1UL << MDCR_EnSPM_SHIFT)
-#define	MDCR_HPMD_SHIFT		17
-#define	MDCR_HPMD		(0x1UL << MDCR_HPMD_SHIFT)
-#define	MDCR_TTRF_SHIFT		19
-#define	MDCR_TTRF		(0x1UL << MDCR_TTRF_SHIFT)
-#define	MDCR_HCCD_SHIFT		23
-#define	MDCR_HCCD		(0x1UL << MDCR_HCCD_SHIFT)
-#define	MDCR_E2TB_SHIFT		24
-#define	MDCR_E2TB_MASK		(0x3UL << MDCR_E2TB_SHIFT)
-#define	MDCR_HLP_SHIFT		26
-#define	MDCR_HLP		(0x1UL << MDCR_HLP_SHIFT)
-#define	MDCR_TDCC_SHIFT		27
-#define	MDCR_TDCC		(0x1UL << MDCR_TDCC_SHIFT)
-#define	MDCR_MTPME_SHIFT	28
-#define	MDCR_MTPME		(0x1UL << MDCR_MTPME_SHIFT)
-#define	MDCR_HPMFZO_SHIFT	29
-#define	MDCR_HPMFZO		(0x1UL << MDCR_HPMFZO_SHIFT)
-#define	MDCR_PMSSE_SHIFT	30
-#define	MDCR_PMSSE_MASK		(0x3UL << MDCR_PMSSE_SHIFT)
-#define	MDCR_HPMFZS_SHIFT	36
-#define	MDCR_HPMFZS		(0x1UL << MDCR_HPMFZS_SHIFT)
-#define	MDCR_PMEE_SHIFT		40
-#define	MDCR_PMEE_MASK		(0x3UL << MDCR_PMEE_SHIFT)
-#define	MDCR_EBWE_SHIFT		43
-#define	MDCR_EBWE		(0x1UL << MDCR_EBWE_SHIFT)
-
 #endif /* !_MACHINE_HYPERVISOR_H_ */
diff --git a/sys/arm64/rockchip/rk_gpio.c b/sys/arm64/rockchip/rk_gpio.c
index 145d9769f35f..8da37d516802 100644
--- a/sys/arm64/rockchip/rk_gpio.c
+++ b/sys/arm64/rockchip/rk_gpio.c
@@ -851,6 +851,10 @@ static device_method_t rk_gpio_methods[] = {
 	DEVMETHOD(device_attach,	rk_gpio_attach),
 	DEVMETHOD(device_detach,	rk_gpio_detach),
 
+	/* Bus interface */
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
 	/* GPIO protocol */
 	DEVMETHOD(gpio_get_bus,		rk_gpio_get_bus),
 	DEVMETHOD(gpio_pin_max,		rk_gpio_pin_max),
diff --git a/sys/arm64/vmm/arm64.h b/sys/arm64/vmm/arm64.h
index 82c4481b8692..f9b74aef7188 100644
--- a/sys/arm64/vmm/arm64.h
+++ b/sys/arm64/vmm/arm64.h
@@ -78,14 +78,16 @@ struct hypctx {
 	uint64_t	pmcr_el0;	/* Performance Monitors Control Register */
 	uint64_t	pmccntr_el0;
 	uint64_t	pmccfiltr_el0;
+	uint64_t	pmuserenr_el0;
+	uint64_t	pmselr_el0;
+	uint64_t	pmxevcntr_el0;
 	uint64_t	pmcntenset_el0;
 	uint64_t	pmintenset_el1;
 	uint64_t	pmovsset_el0;
-	uint64_t	pmselr_el0;
-	uint64_t	pmuserenr_el0;
 	uint64_t	pmevcntr_el0[31];
 	uint64_t	pmevtyper_el0[31];
 
+	uint64_t	dbgclaimset_el1;
 	uint64_t	dbgbcr_el1[16];	/* Debug Breakpoint Control Registers */
 	uint64_t	dbgbvr_el1[16];	/* Debug Breakpoint Value Registers */
 	uint64_t	dbgwcr_el1[16];	/* Debug Watchpoint Control Registers */
@@ -117,6 +119,7 @@ struct hypctx {
 	struct vgic_v3_regs	vgic_v3_regs;
 	struct vgic_v3_cpu	*vgic_cpu;
 	bool			has_exception;
+	bool			dbg_oslock;
 };
 
 struct hyp {
diff --git a/sys/arm64/vmm/vmm.c b/sys/arm64/vmm/vmm.c
index 1dcefa1489e9..a551a2807183 100644
--- a/sys/arm64/vmm/vmm.c
+++ b/sys/arm64/vmm/vmm.c
@@ -651,6 +651,33 @@ vmm_reg_wi(struct vcpu *vcpu, uint64_t wval, void *arg)
 	return (0);
 }
 
+static int
+vmm_write_oslar_el1(struct vcpu *vcpu, uint64_t wval, void *arg)
+{
+	struct hypctx *hypctx;
+
+	hypctx = vcpu_get_cookie(vcpu);
+	/* All other fields are RES0 & we don't do anything with this */
+	/* TODO: Disable access to other debug state when locked */
+	hypctx->dbg_oslock = (wval & OSLAR_OSLK) == OSLAR_OSLK;
+	return (0);
+}
+
+static int
+vmm_read_oslsr_el1(struct vcpu *vcpu, uint64_t *rval, void *arg)
+{
+	struct hypctx *hypctx;
+	uint64_t val;
+
+	hypctx = vcpu_get_cookie(vcpu);
+	val = OSLSR_OSLM_1;
+	if (hypctx->dbg_oslock)
+		val |= OSLSR_OSLK;
+	*rval = val;
+
+	return (0);
+}
+
 static const struct vmm_special_reg vmm_special_regs[] = {
 #define	SPECIAL_REG(_reg, _read, _write)				\
 	{								\
@@ -707,6 +734,13 @@ static const struct vmm_special_reg vmm_special_regs[] = {
 	SPECIAL_REG(CNTP_TVAL_EL0, vtimer_phys_tval_read,
 	    vtimer_phys_tval_write),
 	SPECIAL_REG(CNTPCT_EL0, vtimer_phys_cnt_read, vtimer_phys_cnt_write),
+
+	/* Debug registers */
+	SPECIAL_REG(DBGPRCR_EL1, vmm_reg_raz, vmm_reg_wi),
+	SPECIAL_REG(OSDLR_EL1, vmm_reg_raz, vmm_reg_wi),
+	/* TODO: Exceptions on invalid access */
+	SPECIAL_REG(OSLAR_EL1, vmm_reg_raz, vmm_write_oslar_el1),
+	SPECIAL_REG(OSLSR_EL1, vmm_read_oslsr_el1, vmm_reg_wi),
 #undef SPECIAL_REG
 };
 
diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index 345535318f6e..b8c6d2ab7a9a 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -121,6 +121,8 @@ vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, bool guest,
 		}
 	}
 
+	hypctx->dbgclaimset_el1 = READ_SPECIALREG(dbgclaimset_el1);
+
 	dfr0 = READ_SPECIALREG(id_aa64dfr0_el1);
 	switch (ID_AA64DFR0_BRPs_VAL(dfr0) - 1) {
 #define	STORE_DBG_BRP(x)						\
@@ -180,10 +182,13 @@ vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, bool guest,
 	hypctx->pmcr_el0 = READ_SPECIALREG(pmcr_el0);
 	hypctx->pmccntr_el0 = READ_SPECIALREG(pmccntr_el0);
 	hypctx->pmccfiltr_el0 = READ_SPECIALREG(pmccfiltr_el0);
+	hypctx->pmuserenr_el0 = READ_SPECIALREG(pmuserenr_el0);
+	hypctx->pmselr_el0 = READ_SPECIALREG(pmselr_el0);
+	hypctx->pmxevcntr_el0 = READ_SPECIALREG(pmxevcntr_el0);
 	hypctx->pmcntenset_el0 = READ_SPECIALREG(pmcntenset_el0);
 	hypctx->pmintenset_el1 = READ_SPECIALREG(pmintenset_el1);
 	hypctx->pmovsset_el0 = READ_SPECIALREG(pmovsset_el0);
-	hypctx->pmuserenr_el0 = READ_SPECIALREG(pmuserenr_el0);
+
 	switch ((hypctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT) {
 #define	STORE_PMU(x)							\
 	case (x + 1):							\
@@ -337,12 +342,15 @@ vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, bool guest,
 	WRITE_SPECIALREG(pmcr_el0, hypctx->pmcr_el0);
 	WRITE_SPECIALREG(pmccntr_el0, hypctx->pmccntr_el0);
 	WRITE_SPECIALREG(pmccfiltr_el0, hypctx->pmccfiltr_el0);
+	WRITE_SPECIALREG(pmuserenr_el0, hypctx->pmuserenr_el0);
+	WRITE_SPECIALREG(pmselr_el0, hypctx->pmselr_el0);
+	WRITE_SPECIALREG(pmxevcntr_el0, hypctx->pmxevcntr_el0);
 	/* Clear all events/interrupts then enable them */
-	WRITE_SPECIALREG(pmcntenclr_el0, 0xfffffffful);
+	WRITE_SPECIALREG(pmcntenclr_el0, ~0ul);
 	WRITE_SPECIALREG(pmcntenset_el0, hypctx->pmcntenset_el0);
-	WRITE_SPECIALREG(pmintenclr_el1, 0xfffffffful);
+	WRITE_SPECIALREG(pmintenclr_el1, ~0ul);
 	WRITE_SPECIALREG(pmintenset_el1, hypctx->pmintenset_el1);
-	WRITE_SPECIALREG(pmovsclr_el0, 0xfffffffful);
+	WRITE_SPECIALREG(pmovsclr_el0, ~0ul);
 	WRITE_SPECIALREG(pmovsset_el0, hypctx->pmovsset_el0);
 
 	switch ((hypctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT) {
@@ -388,6 +396,9 @@ vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, bool guest,
 #undef LOAD_PMU
 	}
 
+	WRITE_SPECIALREG(dbgclaimclr_el1, ~0ul);
+	WRITE_SPECIALREG(dbgclaimclr_el1, hypctx->dbgclaimset_el1);
+
 	dfr0 = READ_SPECIALREG(id_aa64dfr0_el1);
 	switch (ID_AA64DFR0_BRPs_VAL(dfr0) - 1) {
 #define	LOAD_DBG_BRP(x)							\
diff --git a/sys/arm64/vmm/vmm_reset.c b/sys/arm64/vmm/vmm_reset.c
index 79d022cf33e8..1240c3ed16ec 100644
--- a/sys/arm64/vmm/vmm_reset.c
+++ b/sys/arm64/vmm/vmm_reset.c
@@ -100,10 +100,12 @@ reset_vm_el01_regs(void *vcpu)
 	el2ctx->pmcr_el0 |= PMCR_LC;
 	set_arch_unknown(el2ctx->pmccntr_el0);
 	set_arch_unknown(el2ctx->pmccfiltr_el0);
+	set_arch_unknown(el2ctx->pmuserenr_el0);
+	set_arch_unknown(el2ctx->pmselr_el0);
+	set_arch_unknown(el2ctx->pmxevcntr_el0);
 	set_arch_unknown(el2ctx->pmcntenset_el0);
 	set_arch_unknown(el2ctx->pmintenset_el1);
 	set_arch_unknown(el2ctx->pmovsset_el0);
-	set_arch_unknown(el2ctx->pmuserenr_el0);
 	memset(el2ctx->pmevcntr_el0, 0, sizeof(el2ctx->pmevcntr_el0));
 	memset(el2ctx->pmevtyper_el0, 0, sizeof(el2ctx->pmevtyper_el0));
 }
@@ -143,7 +145,8 @@ reset_vm_el2_regs(void *vcpu)
 	/* Set the Extended Hypervisor Configuration Register */
 	el2ctx->hcrx_el2 = 0;
 	/* TODO: Trap all extensions we don't support */
-	el2ctx->mdcr_el2 = 0;
+	el2ctx->mdcr_el2 = MDCR_EL2_TDOSA | MDCR_EL2_TDRA | MDCR_EL2_TPMS |
+	    MDCR_EL2_TTRF;
 	/* PMCR_EL0.N is read from MDCR_EL2.HPMN */
 	el2ctx->mdcr_el2 |= (el2ctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT;
 
diff --git a/sys/cam/ata/ata_da.c b/sys/cam/ata/ata_da.c
index 1facab47473c..0d844a6fbf9e 100644
--- a/sys/cam/ata/ata_da.c
+++ b/sys/cam/ata/ata_da.c
@@ -44,6 +44,7 @@
 #include <sys/malloc.h>
 #include <sys/endian.h>
 #include <sys/cons.h>
+#include <sys/power.h>
 #include <sys/proc.h>
 #include <sys/reboot.h>
 #include <sys/sbuf.h>
@@ -878,8 +879,8 @@ static  int		adaerror(union ccb *ccb, uint32_t cam_flags,
 				uint32_t sense_flags);
 static callout_func_t	adasendorderedtag;
 static void		adashutdown(void *arg, int howto);
-static void		adasuspend(void *arg);
-static void		adaresume(void *arg);
+static void		adasuspend(void *arg, enum power_stype stype);
+static void		adaresume(void *arg, enum power_stype stype);
 
 #ifndef ADA_DEFAULT_TIMEOUT
 #define ADA_DEFAULT_TIMEOUT 30	/* Timeout in seconds */
@@ -3747,7 +3748,7 @@ adashutdown(void *arg, int howto)
 }
 
 static void
-adasuspend(void *arg)
+adasuspend(void *arg, enum power_stype stype)
 {
 
 	adaflush();
@@ -3760,7 +3761,7 @@ adasuspend(void *arg)
 }
 
 static void
-adaresume(void *arg)
+adaresume(void *arg, enum power_stype stype)
 {
 	struct cam_periph *periph;
 	struct ada_softc *softc;
diff --git a/sys/cam/nvme/nvme_da.c b/sys/cam/nvme/nvme_da.c
index 1c0d5e8381d8..9c4707da482c 100644
--- a/sys/cam/nvme/nvme_da.c
+++ b/sys/cam/nvme/nvme_da.c
@@ -43,6 +43,7 @@
 #include <sys/eventhandler.h>
 #include <sys/malloc.h>
 #include <sys/cons.h>
+#include <sys/power.h>
 #include <sys/proc.h>
 #include <sys/reboot.h>
 #include <sys/sbuf.h>
@@ -159,7 +160,7 @@ static	void		ndadone(struct cam_periph *periph,
 static  int		ndaerror(union ccb *ccb, uint32_t cam_flags,
 				uint32_t sense_flags);
 static void		ndashutdown(void *arg, int howto);
-static void		ndasuspend(void *arg);
+static void		ndasuspend(void *arg, enum power_stype stype);
 
 #ifndef	NDA_DEFAULT_SEND_ORDERED
 #define	NDA_DEFAULT_SEND_ORDERED	1
@@ -1365,7 +1366,7 @@ ndashutdown(void *arg, int howto)
 }
 
 static void
-ndasuspend(void *arg)
+ndasuspend(void *arg, enum power_stype stype)
 {
 
 	ndaflush();
diff --git a/sys/compat/linuxkpi/common/include/linux/pci.h b/sys/compat/linuxkpi/common/include/linux/pci.h
index d891d0df3546..ffc2be600c22 100644
--- a/sys/compat/linuxkpi/common/include/linux/pci.h
+++ b/sys/compat/linuxkpi/common/include/linux/pci.h
@@ -1332,6 +1332,12 @@ struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
 #define	pci_get_domain_bus_and_slot(domain, bus, devfn)	\
 	lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
 
+struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int);
+#ifndef	WANT_NATIVE_PCI_GET_SLOT
+#define	pci_get_slot(_pbus, _devfn)				\
+    lkpi_pci_get_slot(_pbus, _devfn)
+#endif
+
 static inline int
 pci_domain_nr(struct pci_bus *pbus)
 {
diff --git a/sys/compat/linuxkpi/common/src/linux_acpi.c b/sys/compat/linuxkpi/common/src/linux_acpi.c
index 43783bb8727b..c7d62c745c7e 100644
--- a/sys/compat/linuxkpi/common/src/linux_acpi.c
+++ b/sys/compat/linuxkpi/common/src/linux_acpi.c
@@ -33,6 +33,7 @@
 #include <sys/bus.h>
 #include <sys/eventhandler.h>
 #include <sys/kernel.h>
+#include <sys/power.h>
 
 #include <contrib/dev/acpica/include/acpi.h>
 #include <dev/acpica/acpivar.h>
@@ -118,20 +119,32 @@ acpi_evaluate_dsm(ACPI_HANDLE ObjHandle, const guid_t *guid,
 }
 
 static void
-linux_handle_power_suspend_event(void *arg __unused)
+linux_handle_power_suspend_event(void *arg __unused, enum power_stype stype)
 {
-	/*
-	 * Only support S3 for now.
-	 * acpi_sleep_event isn't always called so we use power_suspend_early
-	 * instead which means we don't know what state we're switching to.
-	 * TODO: Make acpi_sleep_event consistent
-	 */
-	linux_acpi_target_sleep_state = ACPI_STATE_S3;
-	pm_suspend_target_state = PM_SUSPEND_MEM;
+	switch (stype) {
+	case POWER_STYPE_SUSPEND_TO_IDLE:
+		/*
+		 * XXX: obiwac Not 100% sure this is correct, but
+		 * acpi_target_sleep_state does seem to be set to
+		 * ACPI_STATE_S3 during s2idle on Linux.
+		 */
+		linux_acpi_target_sleep_state = ACPI_STATE_S3;
+		pm_suspend_target_state = PM_SUSPEND_TO_IDLE;
+		break;
+	case POWER_STYPE_SUSPEND_TO_MEM:
+		linux_acpi_target_sleep_state = ACPI_STATE_S3;
+		pm_suspend_target_state = PM_SUSPEND_MEM;
+		break;
+	default:
+		printf("%s: sleep type %d not yet supported\n",
+		    __func__, stype);
+		break;
+	}
 }
 
 static void
-linux_handle_power_resume_event(void *arg __unused)
+linux_handle_power_resume_event(void *arg __unused,
+    enum power_stype stype __unused)
 {
 	linux_acpi_target_sleep_state = ACPI_STATE_S0;
 	pm_suspend_target_state = PM_SUSPEND_ON;
diff --git a/sys/compat/linuxkpi/common/src/linux_pci.c b/sys/compat/linuxkpi/common/src/linux_pci.c
index 43fd6ad28ac4..8507a59a8df3 100644
--- a/sys/compat/linuxkpi/common/src/linux_pci.c
+++ b/sys/compat/linuxkpi/common/src/linux_pci.c
@@ -67,6 +67,7 @@
 #include <linux/mm.h>
 #include <linux/io.h>
 #include <linux/vmalloc.h>
+#define	WANT_NATIVE_PCI_GET_SLOT
 #include <linux/pci.h>
 #include <linux/compat.h>
 
@@ -342,6 +343,7 @@ lkpi_pci_dev_release(struct device *dev)
 static int
 lkpifill_pci_dev(device_t dev, struct pci_dev *pdev)
 {
+	struct pci_devinfo *dinfo;
 	int error;
 
 	error = kobject_init_and_add(&pdev->dev.kobj, &linux_dev_ktype,
@@ -362,15 +364,24 @@ lkpifill_pci_dev(device_t dev, struct pci_dev *pdev)
 	pdev->path_name = kasprintf(GFP_KERNEL, "%04d:%02d:%02d.%d",
 	    pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
 	    pci_get_function(dev));
+
 	pdev->bus = malloc(sizeof(*pdev->bus), M_DEVBUF, M_WAITOK | M_ZERO);
-	/*
-	 * This should be the upstream bridge; pci_upstream_bridge()
-	 * handles that case on demand as otherwise we'll shadow the
-	 * entire PCI hierarchy.
-	 */
-	pdev->bus->self = pdev;
 	pdev->bus->number = pci_get_bus(dev);
 	pdev->bus->domain = pci_get_domain(dev);
+
+	/* Check if we have reached the root to satisfy pci_is_root_bus() */
+	dinfo = device_get_ivars(dev);
+	if (dinfo->cfg.pcie.pcie_location != 0 &&
+	    dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
+		pdev->bus->self = NULL;
+	} else {
+		/*
+		 * This should be the upstream bridge; pci_upstream_bridge()
+		 * handles that case on demand as otherwise we'll shadow the
+		 * entire PCI hierarchy.
+		 */
+		pdev->bus->self = pdev;
+	}
 	pdev->dev.bsddev = dev;
 	pdev->dev.parent = &linux_root_device;
 	pdev->dev.release = lkpi_pci_dev_release;
@@ -395,7 +406,7 @@ lkpinew_pci_dev_release(struct device *dev)
 	pdev = to_pci_dev(dev);
 	if (pdev->root != NULL)
 		pci_dev_put(pdev->root);
-	if (pdev->bus->self != pdev)
+	if (pdev->bus->self != pdev && pdev->bus->self != NULL)
 		pci_dev_put(pdev->bus->self);
 	free(pdev->bus, M_DEVBUF);
 	if (pdev->msi_desc != NULL) {
@@ -475,6 +486,20 @@ lkpi_pci_get_domain_bus_and_slot(int domain, unsigned int bus,
 	return (pdev);
 }
 
+struct pci_dev *
+lkpi_pci_get_slot(struct pci_bus *pbus, unsigned int devfn)
+{
+	device_t dev;
+	struct pci_dev *pdev;
+
+	dev = pci_find_bsf(pbus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+	if (dev == NULL)
+		return (NULL);
+
+	pdev = lkpinew_pci_dev(dev);
+	return (pdev);
+}
+
 static int
 linux_pci_probe(device_t dev)
 {
@@ -551,6 +576,7 @@ linux_pci_attach_device(device_t dev, struct pci_driver *pdrv,
 {
 	struct resource_list_entry *rle;
 	device_t parent;
+	struct pci_dev *pbus, *ppbus;
 	uintptr_t rid;
 	int error;
 	bool isdrm;
@@ -594,6 +620,27 @@ linux_pci_attach_device(device_t dev, struct pci_driver *pdrv,
 	list_add(&pdev->links, &pci_devices);
 	spin_unlock(&pci_lock);
 
+	/*
+	 * Create the hierarchy now as we cannot on demand later.
+	 * Take special care of DRM as there is a non-PCI device in the chain.
+	 */
+	pbus = pdev;
+	if (isdrm) {
+		pbus = lkpinew_pci_dev(parent);
+		if (pbus == NULL) {
+			error = ENXIO;
+			goto out_dma_init;
+		}
+	}
+	pcie_find_root_port(pbus);
+	if (isdrm)
+		pdev->root = pbus->root;
+	ppbus = pci_upstream_bridge(pbus);
+	while (ppbus != NULL && ppbus != pbus) {
+		pbus = ppbus;
+		ppbus = pci_upstream_bridge(pbus);
+	}
+
 	if (pdrv != NULL) {
 		error = pdrv->probe(pdev, id);
 		if (error)
@@ -601,6 +648,7 @@ linux_pci_attach_device(device_t dev, struct pci_driver *pdrv,
 	}
 	return (0);
 
+/* XXX the cleanup does not match the allocation up there. */
 out_probe:
 	free(pdev->bus, M_DEVBUF);
 	spin_lock_destroy(&pdev->pcie_cap_lock);
diff --git a/sys/conf/files b/sys/conf/files
index db05a1424f00..d9730e6bf55b 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1393,6 +1393,8 @@ dev/cxgbe/t4_smt.c		optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/t4_l2t.c		optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
+dev/cxgbe/t4_tpt.c		optional cxgbe pci \
+	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/t4_tracer.c		optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/t4_vf.c		optional cxgbev pci \
@@ -1403,6 +1405,8 @@ dev/cxgbe/common/t4vf_hw.c	optional cxgbev pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/crypto/t6_kern_tls.c	optional cxgbe pci kern_tls \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
+dev/cxgbe/crypto/t7_kern_tls.c	optional cxgbe pci kern_tls \
+	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/crypto/t4_keyctx.c	optional cxgbe pci \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cxgbe/cudbg/cudbg_common.c	optional cxgbe \
@@ -1519,6 +1523,30 @@ t6fw.fw			optional cxgbe					\
 	compile-with	"${CP} ${.ALLSRC} ${.TARGET}"			\
 	no-obj no-implicit-rule						\
 	clean		"t6fw.fw"
+t7fw_cfg.c		optional cxgbe					\
+	compile-with	"${AWK} -f $S/tools/fw_stub.awk t7fw_cfg.fw:t7fw_cfg t7fw_cfg_uwire.fw:t7fw_cfg_uwire -mt7fw_cfg -c${.TARGET}" \
+	no-ctfconvert no-implicit-rule before-depend local		\
+	clean		"t7fw_cfg.c"
+t7fw_cfg.fwo		optional cxgbe					\
+	dependency	"t7fw_cfg.fw"					\
+	compile-with	"${NORMAL_FWO}"					\
+	no-implicit-rule						\
+	clean		"t7fw_cfg.fwo"
+t7fw_cfg.fw		optional cxgbe					\
+	dependency	"$S/dev/cxgbe/firmware/t7fw_cfg.txt"		\
+	compile-with	"${CP} ${.ALLSRC} ${.TARGET}"			\
+	no-obj no-implicit-rule						\
+	clean		"t7fw_cfg.fw"
+t7fw_cfg_uwire.fwo	optional cxgbe					\
+	dependency	"t7fw_cfg_uwire.fw"				\
+	compile-with	"${NORMAL_FWO}"					\
+	no-implicit-rule						\
+	clean		"t7fw_cfg_uwire.fwo"
+t7fw_cfg_uwire.fw	optional cxgbe					\
+	dependency	"$S/dev/cxgbe/firmware/t7fw_cfg_uwire.txt"	\
+	compile-with	"${CP} ${.ALLSRC} ${.TARGET}"			\
+	no-obj no-implicit-rule						\
+	clean		"t7fw_cfg_uwire.fw"
 dev/cxgbe/crypto/t4_crypto.c	optional ccr \
 	compile-with "${NORMAL_C} -I$S/dev/cxgbe"
 dev/cyapa/cyapa.c		optional cyapa iicbus
diff --git a/sys/conf/kern.post.mk b/sys/conf/kern.post.mk
index bb3c7af82a4d..7cdfd17778db 100644
--- a/sys/conf/kern.post.mk
+++ b/sys/conf/kern.post.mk
@@ -398,6 +398,14 @@ CFLAGS+= -fdebug-prefix-map=./${_link}=${PREFIX_SYSDIR}/${_link}/include
 .endif
 .endfor
 
+# Install GDB plugins that are useful for kernel debugging.  See the
+# README in sys/tools/gdb for more information.
+GDB_FILES= acttrace.py \
+	   freebsd.py \
+	   pcpu.py \
+	   selftest.py \
+	   vnet.py
+
 ${_ILINKS}:
 	@case ${.TARGET} in \
 	machine) \
@@ -447,6 +455,13 @@ kernel-install: .PHONY
 .if defined(DEBUG) && !defined(INSTALL_NODEBUG) && ${MK_KERNEL_SYMBOLS} != "no"
 	mkdir -p ${DESTDIR}${KERN_DEBUGDIR}${KODIR}
 	${INSTALL} -p -m ${KMODMODE} -o ${KMODOWN} -g ${KMODGRP} ${KERNEL_KO}.debug ${DESTDIR}${KERN_DEBUGDIR}${KODIR}/
+	${INSTALL} -m ${KMODMODE} -o ${KMODOWN} -g ${KMODGRP} \
+	    $S/tools/kernel-gdb.py ${DESTDIR}${KERN_DEBUGDIR}${KODIR}/${KERNEL_KO}-gdb.py
+	mkdir -p ${DESTDIR}${KERN_DEBUGDIR}${KODIR}/gdb
+.for file in ${GDB_FILES}
+	${INSTALL} -m ${KMODMODE} -o ${KMODOWN} -g ${KMODGRP} \
+	    $S/tools/gdb/${file} ${DESTDIR}${KERN_DEBUGDIR}${KODIR}/gdb/${file}
+.endfor
 .endif
 .if defined(KERNEL_EXTRA_INSTALL)
 	${INSTALL} -p -m ${KMODMODE} -o ${KMODOWN} -g ${KMODGRP} ${KERNEL_EXTRA_INSTALL} ${DESTDIR}${KODIR}/
diff --git a/sys/contrib/openzfs/.github/ISSUE_TEMPLATE/feature_request.md b/sys/contrib/openzfs/.github/ISSUE_TEMPLATE/feature_request.md
index 9b50a4a3d96e..f3d4316f6f67 100644
--- a/sys/contrib/openzfs/.github/ISSUE_TEMPLATE/feature_request.md
+++ b/sys/contrib/openzfs/.github/ISSUE_TEMPLATE/feature_request.md
@@ -14,7 +14,7 @@ Please check our issue tracker before opening a new feature request.
 Filling out the following template will help other contributors better understand your proposed feature.
 -->
 
-### Describe the feature would like to see added to OpenZFS
+### Describe the feature you would like to see added to OpenZFS
 
 <!--
 Provide a clear and concise description of the feature.
diff --git a/sys/contrib/openzfs/.github/PULL_REQUEST_TEMPLATE.md b/sys/contrib/openzfs/.github/PULL_REQUEST_TEMPLATE.md
index 79809179cf13..47edc8174603 100644
--- a/sys/contrib/openzfs/.github/PULL_REQUEST_TEMPLATE.md
+++ b/sys/contrib/openzfs/.github/PULL_REQUEST_TEMPLATE.md
@@ -2,11 +2,6 @@
 
 <!--- Provide a general summary of your changes in the Title above -->
 
-<!---
-Documentation on ZFS Buildbot options can be found at
-https://openzfs.github.io/openzfs-docs/Developer%20Resources/Buildbot%20Options.html
--->
-
 ### Motivation and Context
 <!--- Why is this change required? What problem does it solve? -->
 <!--- If it fixes an open issue, please link to the issue here. -->
diff --git a/sys/contrib/openzfs/.github/workflows/scripts/qemu-2-start.sh b/sys/contrib/openzfs/.github/workflows/scripts/qemu-2-start.sh
index 8439942c5a41..1c608348ffcd 100755
--- a/sys/contrib/openzfs/.github/workflows/scripts/qemu-2-start.sh
+++ b/sys/contrib/openzfs/.github/workflows/scripts/qemu-2-start.sh
@@ -121,7 +121,7 @@ case "$OS" in
     KSRC="$FREEBSD_SNAP/../amd64/$FreeBSD/src.txz"
     ;;
   freebsd15-0c)
-    FreeBSD="15.0-ALPHA2"
+    FreeBSD="15.0-ALPHA3"
     OSNAME="FreeBSD $FreeBSD"
     OSv="freebsd14.0"
     URLxz="$FREEBSD_SNAP/$FreeBSD/amd64/Latest/FreeBSD-$FreeBSD-amd64-BASIC-CI-ufs.raw.xz"
diff --git a/sys/contrib/openzfs/.github/workflows/scripts/qemu-3-deps-vm.sh b/sys/contrib/openzfs/.github/workflows/scripts/qemu-3-deps-vm.sh
index ee058b488088..f67bb2f68e94 100755
--- a/sys/contrib/openzfs/.github/workflows/scripts/qemu-3-deps-vm.sh
+++ b/sys/contrib/openzfs/.github/workflows/scripts/qemu-3-deps-vm.sh
@@ -20,7 +20,7 @@ function archlinux() {
   sudo pacman -Sy --noconfirm base-devel bc cpio cryptsetup dhclient dkms \
     fakeroot fio gdb inetutils jq less linux linux-headers lsscsi nfs-utils \
     parted pax perf python-packaging python-setuptools qemu-guest-agent ksh \
-    samba sysstat rng-tools rsync wget xxhash
+    samba strace sysstat rng-tools rsync wget xxhash
   echo "##[endgroup]"
 }
 
@@ -43,7 +43,8 @@ function debian() {
     lsscsi nfs-kernel-server pamtester parted python3 python3-all-dev \
     python3-cffi python3-dev python3-distlib python3-packaging libtirpc-dev \
     python3-setuptools python3-sphinx qemu-guest-agent rng-tools rpm2cpio \
-    rsync samba sysstat uuid-dev watchdog wget xfslibs-dev  xxhash zlib1g-dev
+    rsync samba strace sysstat uuid-dev watchdog wget xfslibs-dev xxhash \
+    zlib1g-dev
   echo "##[endgroup]"
 }
 
@@ -87,8 +88,8 @@ function rhel() {
     libuuid-devel lsscsi mdadm nfs-utils openssl-devel pam-devel pamtester \
     parted perf python3 python3-cffi python3-devel python3-packaging \
     kernel-devel python3-setuptools qemu-guest-agent rng-tools rpcgen \
-    rpm-build rsync samba sysstat systemd watchdog wget xfsprogs-devel xxhash \
-    zlib-devel
+    rpm-build rsync samba strace sysstat systemd watchdog wget xfsprogs-devel \
+    xxhash zlib-devel
   echo "##[endgroup]"
 }
 
@@ -104,7 +105,7 @@ function install_fedora_experimental_kernel {
   our_version="$1"
   sudo dnf -y copr enable @kernel-vanilla/stable
   sudo dnf -y copr enable @kernel-vanilla/mainline
-  all="$(sudo dnf list --showduplicates kernel-*)"
+  all="$(sudo dnf list --showduplicates kernel-* python3-perf* perf* bpftool*)"
   echo "Available versions:"
   echo "$all"
 
diff --git a/sys/contrib/openzfs/.github/workflows/scripts/qemu-5-setup.sh b/sys/contrib/openzfs/.github/workflows/scripts/qemu-5-setup.sh
index 0adcad2a99bc..4869c1003e48 100755
--- a/sys/contrib/openzfs/.github/workflows/scripts/qemu-5-setup.sh
+++ b/sys/contrib/openzfs/.github/workflows/scripts/qemu-5-setup.sh
@@ -108,19 +108,30 @@ echo '*/5 * * * *  /root/cronjob.sh' > crontab.txt
 sudo crontab crontab.txt
 rm crontab.txt
 
-# check if the machines are okay
-echo "Waiting for vm's to come up...  (${VMs}x CPU=$CPU RAM=$RAM)"
-for ((i=1; i<=VMs; i++)); do
-  .github/workflows/scripts/qemu-wait-for-vm.sh vm$i
-done
-echo "All $VMs VMs are up now."
-
 # Save the VM's serial output (ttyS0) to /var/tmp/console.txt
 # - ttyS0 on the VM corresponds to a local /dev/pty/N entry
 # - use 'virsh ttyconsole' to lookup the /dev/pty/N entry
 for ((i=1; i<=VMs; i++)); do
   mkdir -p $RESPATH/vm$i
   read "pty" <<< $(sudo virsh ttyconsole vm$i)
+
+  # Create the file so we can tail it, even if there's no output.
+  touch $RESPATH/vm$i/console.txt
+
   sudo nohup bash -c "cat $pty > $RESPATH/vm$i/console.txt" &
+
+  # Write all VM boot lines to the console to aid in debugging failed boots.
+  # The boot lines from all the VMs will be munged together, so prepend each
+  # line with the vm hostname (like 'vm1:').
+  (while IFS=$'\n' read -r line; do echo "vm$i: $line" ; done < <(sudo tail -f $RESPATH/vm$i/console.txt)) &
+
 done
 echo "Console logging for ${VMs}x $OS started."
+
+
+# check if the machines are okay
+echo "Waiting for vm's to come up...  (${VMs}x CPU=$CPU RAM=$RAM)"
+for ((i=1; i<=VMs; i++)); do
+  .github/workflows/scripts/qemu-wait-for-vm.sh vm$i
+done
+echo "All $VMs VMs are up now."
diff --git a/sys/contrib/openzfs/.github/workflows/scripts/qemu-6-tests.sh b/sys/contrib/openzfs/.github/workflows/scripts/qemu-6-tests.sh
index 5ab822f4f076..ca6ac77f146d 100755
--- a/sys/contrib/openzfs/.github/workflows/scripts/qemu-6-tests.sh
+++ b/sys/contrib/openzfs/.github/workflows/scripts/qemu-6-tests.sh
@@ -111,7 +111,7 @@ fi
 sudo dmesg -c > dmesg-prerun.txt
 mount > mount.txt
 df -h > df-prerun.txt
-$TDIR/zfs-tests.sh -vK -s 3GB -T $TAGS
+$TDIR/zfs-tests.sh -vKO -s 3GB -T $TAGS
 RV=$?
 df -h > df-postrun.txt
 echo $RV > tests-exitcode.txt
diff --git a/sys/contrib/openzfs/META b/sys/contrib/openzfs/META
index 5704b5c6de8a..bdb7aee48041 100644
--- a/sys/contrib/openzfs/META
+++ b/sys/contrib/openzfs/META
@@ -6,5 +6,5 @@ Release:       1
 Release-Tags:  relext
 License:       CDDL
 Author:        OpenZFS
-Linux-Maximum: 6.16
+Linux-Maximum: 6.17
 Linux-Minimum: 4.18
diff --git a/sys/contrib/openzfs/cmd/zdb/zdb.c b/sys/contrib/openzfs/cmd/zdb/zdb.c
index d655fa715e15..70a4ed46f263 100644
--- a/sys/contrib/openzfs/cmd/zdb/zdb.c
+++ b/sys/contrib/openzfs/cmd/zdb/zdb.c
@@ -3301,6 +3301,7 @@ zdb_derive_key(dsl_dir_t *dd, uint8_t *key_out)
 	uint64_t keyformat, salt, iters;
 	int i;
 	unsigned char c;
+	FILE *f;
 
 	VERIFY0(zap_lookup(dd->dd_pool->dp_meta_objset, dd->dd_crypto_obj,
 	    zfs_prop_to_name(ZFS_PROP_KEYFORMAT), sizeof (uint64_t),
@@ -3333,6 +3334,25 @@ zdb_derive_key(dsl_dir_t *dd, uint8_t *key_out)
 
 		break;
 
+	case ZFS_KEYFORMAT_RAW:
+		if ((f = fopen(key_material, "r")) == NULL)
+			return (B_FALSE);
+
+		if (fread(key_out, 1, WRAPPING_KEY_LEN, f) !=
+		    WRAPPING_KEY_LEN) {
+			(void) fclose(f);
+			return (B_FALSE);
+		}
+
+		/* Check the key length */
+		if (fgetc(f) != EOF) {
+			(void) fclose(f);
+			return (B_FALSE);
+		}
+
+		(void) fclose(f);
+		break;
+
 	default:
 		fatal("no support for key format %u\n",
 		    (unsigned int) keyformat);
diff --git a/sys/contrib/openzfs/cmd/zfs/zfs_main.c b/sys/contrib/openzfs/cmd/zfs/zfs_main.c
index 484986bde719..ccdd5ffef8e6 100644
--- a/sys/contrib/openzfs/cmd/zfs/zfs_main.c
+++ b/sys/contrib/openzfs/cmd/zfs/zfs_main.c
@@ -914,7 +914,11 @@ zfs_do_clone(int argc, char **argv)
 			log_history = B_FALSE;
 		}
 
-		ret = zfs_mount_and_share(g_zfs, argv[1], ZFS_TYPE_DATASET);
+		/*
+		 * Dataset cloned successfully, mount/share failures are
+		 * non-fatal.
+		 */
+		(void) zfs_mount_and_share(g_zfs, argv[1], ZFS_TYPE_DATASET);
 	}
 
 	zfs_close(zhp);
@@ -930,19 +934,15 @@ usage:
 }
 
 /*
- * Return a default volblocksize for the pool which always uses more than
- * half of the data sectors.  This primarily applies to dRAID which always
- * writes full stripe widths.
+ * Calculate the minimum allocation size based on the top-level vdevs.
  */
 static uint64_t
-default_volblocksize(zpool_handle_t *zhp, nvlist_t *props)
+calculate_volblocksize(nvlist_t *config)
 {
-	uint64_t volblocksize, asize = SPA_MINBLOCKSIZE;
+	uint64_t asize = SPA_MINBLOCKSIZE;
 	nvlist_t *tree, **vdevs;
 	uint_t nvdevs;
 
-	nvlist_t *config = zpool_get_config(zhp, NULL);
-
 	if (nvlist_lookup_nvlist(config, ZPOOL_CONFIG_VDEV_TREE, &tree) != 0 ||
 	    nvlist_lookup_nvlist_array(tree, ZPOOL_CONFIG_CHILDREN,
 	    &vdevs, &nvdevs) != 0) {
@@ -973,6 +973,24 @@ default_volblocksize(zpool_handle_t *zhp, nvlist_t *props)
 		}
 	}
 
+	return (asize);
+}
+
+/*
+ * Return a default volblocksize for the pool which always uses more than
+ * half of the data sectors.  This primarily applies to dRAID which always
+ * writes full stripe widths.
+ */
+static uint64_t
+default_volblocksize(zpool_handle_t *zhp, nvlist_t *props)
+{
+	uint64_t volblocksize, asize = SPA_MINBLOCKSIZE;
+
+	nvlist_t *config = zpool_get_config(zhp, NULL);
+
+	if (nvlist_lookup_uint64(config, ZPOOL_CONFIG_MAX_ALLOC, &asize) != 0)
+		asize = calculate_volblocksize(config);
+
 	/*
 	 * Calculate the target volblocksize such that more than half
 	 * of the asize is used. The following table is for 4k sectors.
@@ -1319,7 +1337,9 @@ zfs_do_create(int argc, char **argv)
 		goto error;
 	}
 
-	ret = zfs_mount_and_share(g_zfs, argv[0], ZFS_TYPE_DATASET);
+	/* Dataset created successfully, mount/share failures are non-fatal */
+	ret = 0;
+	(void) zfs_mount_and_share(g_zfs, argv[0], ZFS_TYPE_DATASET);
 error:
 	nvlist_free(props);
 	return (ret);
diff --git a/sys/contrib/openzfs/cmd/zinject/zinject.c b/sys/contrib/openzfs/cmd/zinject/zinject.c
index 113797c878b9..c2f646f2567d 100644
--- a/sys/contrib/openzfs/cmd/zinject/zinject.c
+++ b/sys/contrib/openzfs/cmd/zinject/zinject.c
@@ -107,6 +107,8 @@
  * 	zinject
  * 	zinject <-a | -u pool>
  * 	zinject -c <id|all>
+ * 	zinject -E <delay> [-a] [-m] [-f freq] [-l level] [-r range]
+ *	    [-T iotype] [-t type object | -b bookmark pool]
  * 	zinject [-q] <-t type> [-f freq] [-u] [-a] [-m] [-e errno] [-l level]
  *	    [-r range] <object>
  * 	zinject [-f freq] [-a] [-m] [-u] -b objset:object:level:start:end pool
@@ -132,14 +134,18 @@
  * The '-f' flag controls the frequency of errors injected, expressed as a
  * real number percentage between 0.0001 and 100.  The default is 100.
  *
- * The this form is responsible for actually injecting the handler into the
+ * The <object> form is responsible for actually injecting the handler into the
  * framework.  It takes the arguments described above, translates them to the
  * internal tuple using libzpool, and then issues an ioctl() to register the
  * handler.
  *
- * The final form can target a specific bookmark, regardless of whether a
+ * The '-b' option can target a specific bookmark, regardless of whether a
  * human-readable interface has been designed.  It allows developers to specify
  * a particular block by number.
+ *
+ * The '-E' option injects pipeline ready stage delays for the given object or
+ * bookmark. The delay is specified in milliseconds, and it supports I/O type
+ * and range filters.
  */
 
 #include <errno.h>
@@ -346,6 +352,13 @@ usage(void)
 	    "\t\tsuch that the operation takes a minimum of supplied seconds\n"
 	    "\t\tto complete.\n"
 	    "\n"
+	    "\tzinject -E <delay> [-a] [-m] [-f freq] [-l level] [-r range]\n"
+	    "\t\t[-T iotype] [-t type object | -b bookmark pool]\n"
+	    "\n"
+	    "\t\tInject pipeline ready stage delays for the given object path\n"
+	    "\t\t(data or dnode) or raw bookmark. The delay is specified in\n"
+	    "\t\tmilliseconds.\n"
+	    "\n"
 	    "\tzinject -I [-s <seconds> | -g <txgs>] pool\n"
 	    "\t\tCause the pool to stop writing blocks yet not\n"
 	    "\t\treport errors for a duration.  Simulates buggy hardware\n"
@@ -724,12 +737,15 @@ register_handler(const char *pool, int flags, zinject_record_t *record,
 	if (quiet) {
 		(void) printf("%llu\n", (u_longlong_t)zc.zc_guid);
 	} else {
+		boolean_t show_object = B_FALSE;
+		boolean_t show_iotype = B_FALSE;
 		(void) printf("Added handler %llu with the following "
 		    "properties:\n", (u_longlong_t)zc.zc_guid);
 		(void) printf("  pool: %s\n", pool);
 		if (record->zi_guid) {
 			(void) printf("  vdev: %llx\n",
 			    (u_longlong_t)record->zi_guid);
+			show_iotype = B_TRUE;
 		} else if (record->zi_func[0] != '\0') {
 			(void) printf("  panic function: %s\n",
 			    record->zi_func);
@@ -742,7 +758,18 @@ register_handler(const char *pool, int flags, zinject_record_t *record,
 		} else if (record->zi_timer > 0) {
 			(void) printf(" timer: %lld ms\n",
 			    (u_longlong_t)NSEC2MSEC(record->zi_timer));
+			if (record->zi_cmd == ZINJECT_DELAY_READY) {
+				show_object = B_TRUE;
+				show_iotype = B_TRUE;
+			}
 		} else {
+			show_object = B_TRUE;
+		}
+		if (show_iotype) {
+			(void) printf("iotype: %s\n",
+			    iotype_to_str(record->zi_iotype));
+		}
+		if (show_object) {
 			(void) printf("objset: %llu\n",
 			    (u_longlong_t)record->zi_objset);
 			(void) printf("object: %llu\n",
@@ -910,6 +937,7 @@ main(int argc, char **argv)
 	int ret;
 	int flags = 0;
 	uint32_t dvas = 0;
+	hrtime_t ready_delay = -1;
 
 	if ((g_zfs = libzfs_init()) == NULL) {
 		(void) fprintf(stderr, "%s\n", libzfs_error_init(errno));
@@ -940,7 +968,7 @@ main(int argc, char **argv)
 	}
 
 	while ((c = getopt(argc, argv,
-	    ":aA:b:C:d:D:f:Fg:qhIc:t:T:l:mr:s:e:uL:p:P:")) != -1) {
+	    ":aA:b:C:d:D:E:f:Fg:qhIc:t:T:l:mr:s:e:uL:p:P:")) != -1) {
 		switch (c) {
 		case 'a':
 			flags |= ZINJECT_FLUSH_ARC;
@@ -1113,6 +1141,18 @@ main(int argc, char **argv)
 		case 'u':
 			flags |= ZINJECT_UNLOAD_SPA;
 			break;
+		case 'E':
+			ready_delay = MSEC2NSEC(strtol(optarg, &end, 10));
+			if (ready_delay <= 0 || *end != '\0') {
+				(void) fprintf(stderr, "invalid delay '%s': "
+				    "must be a positive duration\n", optarg);
+				usage();
+				libzfs_fini(g_zfs);
+				return (1);
+			}
+			record.zi_cmd = ZINJECT_DELAY_READY;
+			record.zi_timer = ready_delay;
+			break;
 		case 'L':
 			if ((label = name_to_type(optarg)) == TYPE_INVAL &&
 			    !LABEL_TYPE(type)) {
@@ -1150,7 +1190,7 @@ main(int argc, char **argv)
 		 */
 		if (raw != NULL || range != NULL || type != TYPE_INVAL ||
 		    level != 0 || record.zi_cmd != ZINJECT_UNINITIALIZED ||
-		    record.zi_freq > 0 || dvas != 0) {
+		    record.zi_freq > 0 || dvas != 0 || ready_delay >= 0) {
 			(void) fprintf(stderr, "cancel (-c) incompatible with "
 			    "any other options\n");
 			usage();
@@ -1186,7 +1226,7 @@ main(int argc, char **argv)
 		 */
 		if (raw != NULL || range != NULL || type != TYPE_INVAL ||
 		    level != 0 || record.zi_cmd != ZINJECT_UNINITIALIZED ||
-		    dvas != 0) {
+		    dvas != 0 || ready_delay >= 0) {
 			(void) fprintf(stderr, "device (-d) incompatible with "
 			    "data error injection\n");
 			usage();
@@ -1276,13 +1316,23 @@ main(int argc, char **argv)
 			return (1);
 		}
 
-		record.zi_cmd = ZINJECT_DATA_FAULT;
+		if (record.zi_cmd == ZINJECT_UNINITIALIZED) {
+			record.zi_cmd = ZINJECT_DATA_FAULT;
+			if (!error)
+				error = EIO;
+		} else if (error != 0) {
+			(void) fprintf(stderr, "error type -e incompatible "
+			    "with delay injection\n");
+			libzfs_fini(g_zfs);
+			return (1);
+		} else {
+			record.zi_iotype = io_type;
+		}
+
 		if (translate_raw(raw, &record) != 0) {
 			libzfs_fini(g_zfs);
 			return (1);
 		}
-		if (!error)
-			error = EIO;
 	} else if (record.zi_cmd == ZINJECT_PANIC) {
 		if (raw != NULL || range != NULL || type != TYPE_INVAL ||
 		    level != 0 || device != NULL || record.zi_freq > 0 ||
@@ -1410,6 +1460,13 @@ main(int argc, char **argv)
 			record.zi_dvas = dvas;
 		}
 
+		if (record.zi_cmd != ZINJECT_UNINITIALIZED && error != 0) {
+			(void) fprintf(stderr, "error type -e incompatible "
+			    "with delay injection\n");
+			libzfs_fini(g_zfs);
+			return (1);
+		}
+
 		if (error == EACCES) {
 			if (type != TYPE_DATA) {
 				(void) fprintf(stderr, "decryption errors "
@@ -1425,8 +1482,12 @@ main(int argc, char **argv)
 			 * not found.
 			 */
 			error = ECKSUM;
-		} else {
+		} else if (record.zi_cmd == ZINJECT_UNINITIALIZED) {
 			record.zi_cmd = ZINJECT_DATA_FAULT;
+			if (!error)
+				error = EIO;
+		} else {
+			record.zi_iotype = io_type;
 		}
 
 		if (translate_record(type, argv[0], range, level, &record, pool,
@@ -1434,8 +1495,6 @@ main(int argc, char **argv)
 			libzfs_fini(g_zfs);
 			return (1);
 		}
-		if (!error)
-			error = EIO;
 	}
 
 	/*
diff --git a/sys/contrib/openzfs/cmd/zpool/zpool_iter.c b/sys/contrib/openzfs/cmd/zpool/zpool_iter.c
index 2eec9a95e24c..fef602736705 100644
--- a/sys/contrib/openzfs/cmd/zpool/zpool_iter.c
+++ b/sys/contrib/openzfs/cmd/zpool/zpool_iter.c
@@ -26,6 +26,7 @@
 
 /*
  * Copyright 2016 Igor Kozhukhov <ikozhukhov@gmail.com>.
+ * Copyright (c) 2025, Klara, Inc.
  */
 
 #include <libintl.h>
@@ -52,7 +53,7 @@
 typedef struct zpool_node {
 	zpool_handle_t	*zn_handle;
 	uu_avl_node_t	zn_avlnode;
-	int		zn_mark;
+	hrtime_t	zn_last_refresh;
 } zpool_node_t;
 
 struct zpool_list {
@@ -62,6 +63,7 @@ struct zpool_list {
 	uu_avl_pool_t	*zl_pool;
 	zprop_list_t	**zl_proplist;
 	zfs_type_t	zl_type;
+	hrtime_t	zl_last_refresh;
 };
 
 static int
@@ -81,26 +83,30 @@ zpool_compare(const void *larg, const void *rarg, void *unused)
  * of known pools.
  */
 static int
-add_pool(zpool_handle_t *zhp, void *data)
+add_pool(zpool_handle_t *zhp, zpool_list_t *zlp)
 {
-	zpool_list_t *zlp = data;
-	zpool_node_t *node = safe_malloc(sizeof (zpool_node_t));
+	zpool_node_t *node, *new = safe_malloc(sizeof (zpool_node_t));
 	uu_avl_index_t idx;
 
-	node->zn_handle = zhp;
-	uu_avl_node_init(node, &node->zn_avlnode, zlp->zl_pool);
-	if (uu_avl_find(zlp->zl_avl, node, NULL, &idx) == NULL) {
+	new->zn_handle = zhp;
+	uu_avl_node_init(new, &new->zn_avlnode, zlp->zl_pool);
+
+	node = uu_avl_find(zlp->zl_avl, new, NULL, &idx);
+	if (node == NULL) {
 		if (zlp->zl_proplist &&
 		    zpool_expand_proplist(zhp, zlp->zl_proplist,
 		    zlp->zl_type, zlp->zl_literal) != 0) {
 			zpool_close(zhp);
-			free(node);
+			free(new);
 			return (-1);
 		}
-		uu_avl_insert(zlp->zl_avl, node, idx);
+		new->zn_last_refresh = zlp->zl_last_refresh;
+		uu_avl_insert(zlp->zl_avl, new, idx);
 	} else {
+		zpool_refresh_stats_from_handle(node->zn_handle, zhp);
+		node->zn_last_refresh = zlp->zl_last_refresh;
 		zpool_close(zhp);
-		free(node);
+		free(new);
 		return (-1);
 	}
 
@@ -108,6 +114,18 @@ add_pool(zpool_handle_t *zhp, void *data)
 }
 
 /*
+ * add_pool(), but always returns 0. This allows zpool_iter() to continue
+ * even if a pool exists in the tree, or we fail to get the properties for
+ * a new one.
+ */
+static int
+add_pool_cb(zpool_handle_t *zhp, void *data)
+{
+	(void) add_pool(zhp, data);
+	return (0);
+}
+
+/*
  * Create a list of pools based on the given arguments.  If we're given no
  * arguments, then iterate over all pools in the system and add them to the AVL
  * tree.  Otherwise, add only those pool explicitly specified on the command
@@ -135,9 +153,10 @@ pool_list_get(int argc, char **argv, zprop_list_t **proplist, zfs_type_t type,
 	zlp->zl_type = type;
 
 	zlp->zl_literal = literal;
+	zlp->zl_last_refresh = gethrtime();
 
 	if (argc == 0) {
-		(void) zpool_iter(g_zfs, add_pool, zlp);
+		(void) zpool_iter(g_zfs, add_pool_cb, zlp);
 		zlp->zl_findall = B_TRUE;
 	} else {
 		int i;
@@ -159,15 +178,61 @@ pool_list_get(int argc, char **argv, zprop_list_t **proplist, zfs_type_t type,
 }
 
 /*
- * Search for any new pools, adding them to the list.  We only add pools when no
- * options were given on the command line.  Otherwise, we keep the list fixed as
- * those that were explicitly specified.
+ * Refresh the state of all pools on the list. Additionally, if no options were
+ * given on the command line, add any new pools and remove any that are no
+ * longer available.
  */
-void
-pool_list_update(zpool_list_t *zlp)
+int
+pool_list_refresh(zpool_list_t *zlp)
 {
-	if (zlp->zl_findall)
-		(void) zpool_iter(g_zfs, add_pool, zlp);
+	zlp->zl_last_refresh = gethrtime();
+
+	if (!zlp->zl_findall) {
+		/*
+		 * This list is a fixed list of pools, so we must not add
+		 * or remove any. Just walk over them and refresh their
+		 * state.
+		 */
+		int navail = 0;
+		for (zpool_node_t *node = uu_avl_first(zlp->zl_avl);
+		    node != NULL; node = uu_avl_next(zlp->zl_avl, node)) {
+			boolean_t missing;
+			zpool_refresh_stats(node->zn_handle, &missing);
+			navail += !missing;
+			node->zn_last_refresh = zlp->zl_last_refresh;
+		}
+		return (navail);
+	}
+
+	/* Search for any new pools and add them to the list. */
+	(void) zpool_iter(g_zfs, add_pool_cb, zlp);
+
+	/* Walk the list of existing pools, and update or remove them. */
+	zpool_node_t *node, *next;
+	for (node = uu_avl_first(zlp->zl_avl); node != NULL; node = next) {
+		next = uu_avl_next(zlp->zl_avl, node);
+
+		/*
+		 * Skip any that were refreshed and are online; they were added
+		 * by zpool_iter() and are already up to date.
+		 */
+		if (node->zn_last_refresh == zlp->zl_last_refresh &&
+		    zpool_get_state(node->zn_handle) != POOL_STATE_UNAVAIL)
+			continue;
+
+		/* Refresh and remove if necessary. */
+		boolean_t missing;
+		zpool_refresh_stats(node->zn_handle, &missing);
+		if (missing) {
+			uu_avl_remove(zlp->zl_avl, node);
+			zpool_close(node->zn_handle);
+			free(node);
+		} else {
+			node->zn_last_refresh = zlp->zl_last_refresh;
+		}
+	}
+
+	return (uu_avl_numnodes(zlp->zl_avl));
 }
 
 /*
@@ -191,23 +256,6 @@ pool_list_iter(zpool_list_t *zlp, int unavail, zpool_iter_f func,
 }
 
 /*
- * Remove the given pool from the list.  When running iostat, we want to remove
- * those pools that no longer exist.
- */
-void
-pool_list_remove(zpool_list_t *zlp, zpool_handle_t *zhp)
-{
-	zpool_node_t search, *node;
-
-	search.zn_handle = zhp;
-	if ((node = uu_avl_find(zlp->zl_avl, &search, NULL, NULL)) != NULL) {
-		uu_avl_remove(zlp->zl_avl, node);
-		zpool_close(node->zn_handle);
-		free(node);
-	}
-}
-
-/*
  * Free all the handles associated with this list.
  */
 void
diff --git a/sys/contrib/openzfs/cmd/zpool/zpool_main.c b/sys/contrib/openzfs/cmd/zpool/zpool_main.c
index 2c46ad0df895..1feec55c0e8b 100644
--- a/sys/contrib/openzfs/cmd/zpool/zpool_main.c
+++ b/sys/contrib/openzfs/cmd/zpool/zpool_main.c
@@ -33,7 +33,7 @@
  * Copyright (c) 2017, Intel Corporation.
  * Copyright (c) 2019, loli10K <ezomori.nozomu@gmail.com>
  * Copyright (c) 2021, Colm Buckley <colm@tuatha.org>
- * Copyright (c) 2021, 2023, Klara Inc.
+ * Copyright (c) 2021, 2023, 2025, Klara, Inc.
  * Copyright (c) 2021, 2025 Hewlett Packard Enterprise Development LP.
  */
 
@@ -5761,24 +5761,6 @@ children:
 	return (ret);
 }
 
-static int
-refresh_iostat(zpool_handle_t *zhp, void *data)
-{
-	iostat_cbdata_t *cb = data;
-	boolean_t missing;
-
-	/*
-	 * If the pool has disappeared, remove it from the list and continue.
-	 */
-	if (zpool_refresh_stats(zhp, &missing) != 0)
-		return (-1);
-
-	if (missing)
-		pool_list_remove(cb->cb_list, zhp);
-
-	return (0);
-}
-
 /*
  * Callback to print out the iostats for the given pool.
  */
@@ -6359,15 +6341,14 @@ get_namewidth_iostat(zpool_handle_t *zhp, void *data)
  * This command can be tricky because we want to be able to deal with pool
  * creation/destruction as well as vdev configuration changes.  The bulk of this
  * processing is handled by the pool_list_* routines in zpool_iter.c.  We rely
- * on pool_list_update() to detect the addition of new pools.  Configuration
- * changes are all handled within libzfs.
+ * on pool_list_refresh() to detect the addition and removal of pools.
+ * Configuration changes are all handled within libzfs.
  */
 int
 zpool_do_iostat(int argc, char **argv)
 {
 	int c;
 	int ret;
-	int npools;
 	float interval = 0;
 	unsigned long count = 0;
 	zpool_list_t *list;
@@ -6618,10 +6599,24 @@ zpool_do_iostat(int argc, char **argv)
 		return (1);
 	}
 
+	int last_npools = 0;
 	for (;;) {
-		if ((npools = pool_list_count(list)) == 0)
+		/*
+		 * Refresh all pools in list, adding or removing pools as
+		 * necessary.
+		 */
+		int npools = pool_list_refresh(list);
+		if (npools == 0) {
 			(void) fprintf(stderr, gettext("no pools available\n"));
-		else {
+		} else {
+			/*
+			 * If the list of pools has changed since last time
+			 * around, reset the iteration count to force the
+			 * header to be redisplayed.
+			 */
+			if (last_npools != npools)
+				cb.cb_iteration = 0;
+
 			/*
 			 * If this is the first iteration and -y was supplied
 			 * we skip any printing.
@@ -6630,15 +6625,6 @@ zpool_do_iostat(int argc, char **argv)
 			    cb.cb_iteration == 0);
 
 			/*
-			 * Refresh all statistics.  This is done as an
-			 * explicit step before calculating the maximum name
-			 * width, so that any * configuration changes are
-			 * properly accounted for.
-			 */
-			(void) pool_list_iter(list, B_FALSE, refresh_iostat,
-			    &cb);
-
-			/*
 			 * Iterate over all pools to determine the maximum width
 			 * for the pool / device name column across all pools.
 			 */
@@ -6691,6 +6677,7 @@ zpool_do_iostat(int argc, char **argv)
 			if (skip) {
 				(void) fflush(stdout);
 				(void) fsleep(interval);
+				last_npools = npools;
 				continue;
 			}
 
@@ -6728,6 +6715,8 @@ zpool_do_iostat(int argc, char **argv)
 
 		(void) fflush(stdout);
 		(void) fsleep(interval);
+
+		last_npools = npools;
 	}
 
 	pool_list_free(list);
diff --git a/sys/contrib/openzfs/cmd/zpool/zpool_util.h b/sys/contrib/openzfs/cmd/zpool/zpool_util.h
index 5ab7cb9750f1..3af23c52bd45 100644
--- a/sys/contrib/openzfs/cmd/zpool/zpool_util.h
+++ b/sys/contrib/openzfs/cmd/zpool/zpool_util.h
@@ -76,11 +76,10 @@ typedef struct zpool_list zpool_list_t;
 
 zpool_list_t *pool_list_get(int, char **, zprop_list_t **, zfs_type_t,
     boolean_t, int *);
-void pool_list_update(zpool_list_t *);
+int pool_list_refresh(zpool_list_t *);
 int pool_list_iter(zpool_list_t *, int unavail, zpool_iter_f, void *);
 void pool_list_free(zpool_list_t *);
 int pool_list_count(zpool_list_t *);
-void pool_list_remove(zpool_list_t *, zpool_handle_t *);
 
 extern libzfs_handle_t *g_zfs;
 
diff --git a/sys/contrib/openzfs/cmd/zpool/zpool_vdev.c b/sys/contrib/openzfs/cmd/zpool/zpool_vdev.c
index 684b46a2d673..088c0108e911 100644
--- a/sys/contrib/openzfs/cmd/zpool/zpool_vdev.c
+++ b/sys/contrib/openzfs/cmd/zpool/zpool_vdev.c
@@ -609,22 +609,28 @@ get_replication(nvlist_t *nvroot, boolean_t fatal)
 				    ZPOOL_CONFIG_PATH, &path) == 0);
 
 				/*
+				 * Skip active spares they should never cause
+				 * the pool to be evaluated as inconsistent.
+				 */
+				if (is_spare(NULL, path))
+					continue;
+
+				/*
 				 * If we have a raidz/mirror that combines disks
-				 * with files, report it as an error.
+				 * with files, only report it as an error when
+				 * fatal is set to ensure all the replication
+				 * checks aren't skipped in check_replication().
 				 */
-				if (!dontreport && type != NULL &&
+				if (fatal && !dontreport && type != NULL &&
 				    strcmp(type, childtype) != 0) {
 					if (ret != NULL)
 						free(ret);
 					ret = NULL;
-					if (fatal)
-						vdev_error(gettext(
-						    "mismatched replication "
-						    "level: %s contains both "
-						    "files and devices\n"),
-						    rep.zprl_type);
-					else
-						return (NULL);
+					vdev_error(gettext(
+					    "mismatched replication "
+					    "level: %s contains both "
+					    "files and devices\n"),
+					    rep.zprl_type);
 					dontreport = B_TRUE;
 				}
 
diff --git a/sys/contrib/openzfs/contrib/intel_qat/readme.md b/sys/contrib/openzfs/contrib/intel_qat/readme.md
index 7e45d395bb80..04c299b6404c 100644
--- a/sys/contrib/openzfs/contrib/intel_qat/readme.md
+++ b/sys/contrib/openzfs/contrib/intel_qat/readme.md
@@ -8,7 +8,7 @@ This contrib contains community compatibility patches to get Intel QAT working o
 These patches are based on the following Intel QAT version:
 [1.7.l.4.10.0-00014](https://01.org/sites/default/files/downloads/qat1.7.l.4.10.0-00014.tar.gz)
 
-When using QAT with above kernels versions, the following patches needs to be applied using:
+When using QAT with the above kernel versions, the following patches need to be applied using:
 patch -p1 < _$PATCH_
 _Where $PATCH refers to the path of the patch in question_
 
diff --git a/sys/contrib/openzfs/contrib/pyzfs/libzfs_core/test/test_libzfs_core.py b/sys/contrib/openzfs/contrib/pyzfs/libzfs_core/test/test_libzfs_core.py
index 971aa1d0d493..bad1af2d1671 100644
--- a/sys/contrib/openzfs/contrib/pyzfs/libzfs_core/test/test_libzfs_core.py
+++ b/sys/contrib/openzfs/contrib/pyzfs/libzfs_core/test/test_libzfs_core.py
@@ -4223,7 +4223,7 @@ class _TempPool(object):
             self.getRoot().reset()
             return
 
-        # On the Buildbot builders this may fail with "pool is busy"
+        # On the CI builders this may fail with "pool is busy"
         # Retry 5 times before raising an error
         retry = 0
         while True:
diff --git a/sys/contrib/openzfs/etc/init.d/README.md b/sys/contrib/openzfs/etc/init.d/README.md
index da780fdc1222..3852dd9a6b2e 100644
--- a/sys/contrib/openzfs/etc/init.d/README.md
+++ b/sys/contrib/openzfs/etc/init.d/README.md
@@ -1,5 +1,5 @@
 DESCRIPTION
-  These script were written with the primary intention of being portable and
+  These scripts were written with the primary intention of being portable and
   usable on as many systems as possible.
 
   This is, in practice, usually not possible. But the intention is there.
diff --git a/sys/contrib/openzfs/include/libzfs.h b/sys/contrib/openzfs/include/libzfs.h
index 3fcdc176a621..14930fb90622 100644
--- a/sys/contrib/openzfs/include/libzfs.h
+++ b/sys/contrib/openzfs/include/libzfs.h
@@ -479,6 +479,8 @@ _LIBZFS_H zpool_status_t zpool_import_status(nvlist_t *, const char **,
 _LIBZFS_H nvlist_t *zpool_get_config(zpool_handle_t *, nvlist_t **);
 _LIBZFS_H nvlist_t *zpool_get_features(zpool_handle_t *);
 _LIBZFS_H int zpool_refresh_stats(zpool_handle_t *, boolean_t *);
+_LIBZFS_H void zpool_refresh_stats_from_handle(zpool_handle_t *,
+    zpool_handle_t *);
 _LIBZFS_H int zpool_get_errlog(zpool_handle_t *, nvlist_t **);
 _LIBZFS_H void zpool_add_propname(zpool_handle_t *, const char *);
 
diff --git a/sys/contrib/openzfs/include/os/linux/kernel/linux/blkdev_compat.h b/sys/contrib/openzfs/include/os/linux/kernel/linux/blkdev_compat.h
index 076dab8ba6dc..214f3ea0e787 100644
--- a/sys/contrib/openzfs/include/os/linux/kernel/linux/blkdev_compat.h
+++ b/sys/contrib/openzfs/include/os/linux/kernel/linux/blkdev_compat.h
@@ -542,24 +542,6 @@ blk_generic_alloc_queue(make_request_fn make_request, int node_id)
 }
 #endif /* !HAVE_SUBMIT_BIO_IN_BLOCK_DEVICE_OPERATIONS */
 
-/*
- * All the io_*() helper functions below can operate on a bio, or a rq, but
- * not both.  The older submit_bio() codepath will pass a bio, and the
- * newer blk-mq codepath will pass a rq.
- */
-static inline int
-io_data_dir(struct bio *bio, struct request *rq)
-{
-	if (rq != NULL) {
-		if (op_is_write(req_op(rq))) {
-			return (WRITE);
-		} else {
-			return (READ);
-		}
-	}
-	return (bio_data_dir(bio));
-}
-
 static inline int
 io_is_flush(struct bio *bio, struct request *rq)
 {
diff --git a/sys/contrib/openzfs/include/sys/fs/zfs.h b/sys/contrib/openzfs/include/sys/fs/zfs.h
index 49ab9d3db795..662fd81c5ee1 100644
--- a/sys/contrib/openzfs/include/sys/fs/zfs.h
+++ b/sys/contrib/openzfs/include/sys/fs/zfs.h
@@ -748,6 +748,8 @@ typedef struct zpool_load_policy {
 #define	ZPOOL_CONFIG_METASLAB_SHIFT	"metaslab_shift"
 #define	ZPOOL_CONFIG_ASHIFT		"ashift"
 #define	ZPOOL_CONFIG_ASIZE		"asize"
+#define	ZPOOL_CONFIG_MIN_ALLOC		"min_alloc"
+#define	ZPOOL_CONFIG_MAX_ALLOC		"max_alloc"
 #define	ZPOOL_CONFIG_DTL		"DTL"
 #define	ZPOOL_CONFIG_SCAN_STATS		"scan_stats"	/* not stored on disk */
 #define	ZPOOL_CONFIG_REMOVAL_STATS	"removal_stats"	/* not stored on disk */
diff --git a/sys/contrib/openzfs/include/sys/range_tree.h b/sys/contrib/openzfs/include/sys/range_tree.h
index 0f6884682459..0f6def36f9f6 100644
--- a/sys/contrib/openzfs/include/sys/range_tree.h
+++ b/sys/contrib/openzfs/include/sys/range_tree.h
@@ -238,8 +238,7 @@ zfs_rs_set_end_raw(zfs_range_seg_t *rs, zfs_range_tree_t *rt, uint64_t end)
 }
 
 static inline void
-zfs_zfs_rs_set_fill_raw(zfs_range_seg_t *rs, zfs_range_tree_t *rt,
-    uint64_t fill)
+zfs_rs_set_fill_raw(zfs_range_seg_t *rs, zfs_range_tree_t *rt, uint64_t fill)
 {
 	ASSERT3U(rt->rt_type, <=, ZFS_RANGE_SEG_NUM_TYPES);
 	switch (rt->rt_type) {
@@ -277,7 +276,7 @@ static inline void
 zfs_rs_set_fill(zfs_range_seg_t *rs, zfs_range_tree_t *rt, uint64_t fill)
 {
 	ASSERT(IS_P2ALIGNED(fill, 1ULL << rt->rt_shift));
-	zfs_zfs_rs_set_fill_raw(rs, rt, fill >> rt->rt_shift);
+	zfs_rs_set_fill_raw(rs, rt, fill >> rt->rt_shift);
 }
 
 typedef void zfs_range_tree_func_t(void *arg, uint64_t start, uint64_t size);
diff --git a/sys/contrib/openzfs/include/sys/spa.h b/sys/contrib/openzfs/include/sys/spa.h
index 66db16b33c51..f172f2af6f07 100644
--- a/sys/contrib/openzfs/include/sys/spa.h
+++ b/sys/contrib/openzfs/include/sys/spa.h
@@ -1030,7 +1030,7 @@ extern void spa_import_progress_set_notes_nolog(spa_t *spa,
 extern int spa_config_tryenter(spa_t *spa, int locks, const void *tag,
     krw_t rw);
 extern void spa_config_enter(spa_t *spa, int locks, const void *tag, krw_t rw);
-extern void spa_config_enter_mmp(spa_t *spa, int locks, const void *tag,
+extern void spa_config_enter_priority(spa_t *spa, int locks, const void *tag,
     krw_t rw);
 extern void spa_config_exit(spa_t *spa, int locks, const void *tag);
 extern int spa_config_held(spa_t *spa, int locks, krw_t rw);
@@ -1084,6 +1084,7 @@ extern pool_state_t spa_state(spa_t *spa);
 extern spa_load_state_t spa_load_state(spa_t *spa);
 extern uint64_t spa_freeze_txg(spa_t *spa);
 extern uint64_t spa_get_worst_case_asize(spa_t *spa, uint64_t lsize);
+extern void spa_get_min_alloc_range(spa_t *spa, uint64_t *min, uint64_t *max);
 extern uint64_t spa_get_dspace(spa_t *spa);
 extern uint64_t spa_get_checkpoint_space(spa_t *spa);
 extern uint64_t spa_get_slop_space(spa_t *spa);
diff --git a/sys/contrib/openzfs/include/sys/spa_impl.h b/sys/contrib/openzfs/include/sys/spa_impl.h
index 07a959db3447..62b062984d36 100644
--- a/sys/contrib/openzfs/include/sys/spa_impl.h
+++ b/sys/contrib/openzfs/include/sys/spa_impl.h
@@ -265,6 +265,7 @@ struct spa {
 	uint64_t	spa_min_ashift;		/* of vdevs in normal class */
 	uint64_t	spa_max_ashift;		/* of vdevs in normal class */
 	uint64_t	spa_min_alloc;		/* of vdevs in normal class */
+	uint64_t	spa_max_alloc;		/* of vdevs in normal class */
 	uint64_t	spa_gcd_alloc;		/* of vdevs in normal class */
 	uint64_t	spa_config_guid;	/* config pool guid */
 	uint64_t	spa_load_guid;		/* spa_load initialized guid */
diff --git a/sys/contrib/openzfs/include/sys/zfs_ioctl.h b/sys/contrib/openzfs/include/sys/zfs_ioctl.h
index 8174242abdac..cfe11f43bb8e 100644
--- a/sys/contrib/openzfs/include/sys/zfs_ioctl.h
+++ b/sys/contrib/openzfs/include/sys/zfs_ioctl.h
@@ -455,6 +455,7 @@ typedef enum zinject_type {
 	ZINJECT_DECRYPT_FAULT,
 	ZINJECT_DELAY_IMPORT,
 	ZINJECT_DELAY_EXPORT,
+	ZINJECT_DELAY_READY,
 } zinject_type_t;
 
 typedef enum zinject_iotype {
diff --git a/sys/contrib/openzfs/include/sys/zio.h b/sys/contrib/openzfs/include/sys/zio.h
index a8acb83b4c2f..acb0a03a36b2 100644
--- a/sys/contrib/openzfs/include/sys/zio.h
+++ b/sys/contrib/openzfs/include/sys/zio.h
@@ -718,6 +718,7 @@ extern void zio_handle_ignored_writes(zio_t *zio);
 extern hrtime_t zio_handle_io_delay(zio_t *zio);
 extern void zio_handle_import_delay(spa_t *spa, hrtime_t elapsed);
 extern void zio_handle_export_delay(spa_t *spa, hrtime_t elapsed);
+extern hrtime_t zio_handle_ready_delay(zio_t *zio);
 
 /*
  * Checksum ereport functions
diff --git a/sys/contrib/openzfs/lib/libuutil/libuutil.abi b/sys/contrib/openzfs/lib/libuutil/libuutil.abi
index 6c736c61e4a5..2a740afa07ca 100644
--- a/sys/contrib/openzfs/lib/libuutil/libuutil.abi
+++ b/sys/contrib/openzfs/lib/libuutil/libuutil.abi
@@ -616,6 +616,7 @@
     <array-type-def dimensions='1' type-id='de572c22' size-in-bits='1472' id='6d3c2f42'>
       <subrange length='23' type-id='7359adad' id='fdd0f594'/>
     </array-type-def>
+    <type-decl name='long long int' size-in-bits='64' id='1eb56b1e'/>
     <array-type-def dimensions='1' type-id='3a47d82b' size-in-bits='256' id='a133ec23'>
       <subrange length='4' type-id='7359adad' id='16fe7105'/>
     </array-type-def>
@@ -1020,13 +1021,6 @@
     <array-type-def dimensions='1' type-id='03085adc' size-in-bits='192' id='083f8d58'>
       <subrange length='3' type-id='7359adad' id='56f209d2'/>
     </array-type-def>
-    <array-type-def dimensions='1' type-id='d315442e' size-in-bits='16' id='811205dc'>
-      <subrange length='1' type-id='7359adad' id='52f813b4'/>
-    </array-type-def>
-    <array-type-def dimensions='1' type-id='d3130597' size-in-bits='768' id='f63f23b9'>
-      <subrange length='12' type-id='7359adad' id='84827bdc'/>
-    </array-type-def>
-    <type-decl name='long long int' size-in-bits='64' id='1eb56b1e'/>
     <class-decl name='mnttab' size-in-bits='256' is-struct='yes' visibility='default' id='1b055409'>
       <data-member access='public' layout-offset-in-bits='0'>
         <var-decl name='mnt_special' type-id='26a90f95' visibility='default'/>
@@ -1061,93 +1055,6 @@
         <var-decl name='mnt_minor' type-id='3502e3ff' visibility='default'/>
       </data-member>
     </class-decl>
-    <typedef-decl name='__u16' type-id='8efea9e5' id='d315442e'/>
-    <typedef-decl name='__s32' type-id='95e97e5e' id='3158a266'/>
-    <typedef-decl name='__u32' type-id='f0981eeb' id='3f1a6b60'/>
-    <typedef-decl name='__s64' type-id='1eb56b1e' id='49659421'/>
-    <typedef-decl name='__u64' type-id='3a47d82b' id='d3130597'/>
-    <class-decl name='statx_timestamp' size-in-bits='128' is-struct='yes' visibility='default' id='94101016'>
-      <data-member access='public' layout-offset-in-bits='0'>
-        <var-decl name='tv_sec' type-id='49659421' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='64'>
-        <var-decl name='tv_nsec' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='96'>
-        <var-decl name='__reserved' type-id='3158a266' visibility='default'/>
-      </data-member>
-    </class-decl>
-    <class-decl name='statx' size-in-bits='2048' is-struct='yes' visibility='default' id='720b04c5'>
-      <data-member access='public' layout-offset-in-bits='0'>
-        <var-decl name='stx_mask' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='32'>
-        <var-decl name='stx_blksize' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='64'>
-        <var-decl name='stx_attributes' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='128'>
-        <var-decl name='stx_nlink' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='160'>
-        <var-decl name='stx_uid' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='192'>
-        <var-decl name='stx_gid' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='224'>
-        <var-decl name='stx_mode' type-id='d315442e' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='240'>
-        <var-decl name='__spare0' type-id='811205dc' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='256'>
-        <var-decl name='stx_ino' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='320'>
-        <var-decl name='stx_size' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='384'>
-        <var-decl name='stx_blocks' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='448'>
-        <var-decl name='stx_attributes_mask' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='512'>
-        <var-decl name='stx_atime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='640'>
-        <var-decl name='stx_btime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='768'>
-        <var-decl name='stx_ctime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='896'>
-        <var-decl name='stx_mtime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1024'>
-        <var-decl name='stx_rdev_major' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1056'>
-        <var-decl name='stx_rdev_minor' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1088'>
-        <var-decl name='stx_dev_major' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1120'>
-        <var-decl name='stx_dev_minor' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1152'>
-        <var-decl name='stx_mnt_id' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1216'>
-        <var-decl name='__spare2' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1280'>
-        <var-decl name='__spare3' type-id='f63f23b9' visibility='default'/>
-      </data-member>
-    </class-decl>
     <class-decl name='mntent' size-in-bits='320' is-struct='yes' visibility='default' id='56fe4a37'>
       <data-member access='public' layout-offset-in-bits='0'>
         <var-decl name='mnt_fsname' type-id='26a90f95' visibility='default'/>
@@ -1237,8 +1144,6 @@
     <pointer-type-def type-id='1b055409' size-in-bits='64' id='9d424d31'/>
     <pointer-type-def type-id='0bbec9cd' size-in-bits='64' id='62f7a03d'/>
     <qualified-type-def type-id='62f7a03d' restrict='yes' id='f1cadedf'/>
-    <pointer-type-def type-id='720b04c5' size-in-bits='64' id='936b8e35'/>
-    <qualified-type-def type-id='936b8e35' restrict='yes' id='31d265b7'/>
     <function-decl name='getmntent_r' visibility='default' binding='global' size-in-bits='64'>
       <parameter type-id='e75a27e9'/>
       <parameter type-id='3cad23cd'/>
@@ -1254,14 +1159,6 @@
       <parameter type-id='95e97e5e'/>
       <return type-id='26a90f95'/>
     </function-decl>
-    <function-decl name='statx' visibility='default' binding='global' size-in-bits='64'>
-      <parameter type-id='95e97e5e'/>
-      <parameter type-id='9d26089a'/>
-      <parameter type-id='95e97e5e'/>
-      <parameter type-id='f0981eeb'/>
-      <parameter type-id='31d265b7'/>
-      <return type-id='95e97e5e'/>
-    </function-decl>
     <function-decl name='__fprintf_chk' visibility='default' binding='global' size-in-bits='64'>
       <parameter type-id='e75a27e9'/>
       <parameter type-id='95e97e5e'/>
diff --git a/sys/contrib/openzfs/lib/libzfs/libzfs.abi b/sys/contrib/openzfs/lib/libzfs/libzfs.abi
index 184ea4a55b43..f988d27a286a 100644
--- a/sys/contrib/openzfs/lib/libzfs/libzfs.abi
+++ b/sys/contrib/openzfs/lib/libzfs/libzfs.abi
@@ -571,6 +571,7 @@
     <elf-symbol name='zpool_props_refresh' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zpool_read_label' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zpool_refresh_stats' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
+    <elf-symbol name='zpool_refresh_stats_from_handle' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zpool_reguid' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zpool_reopen_one' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zpool_scan' type='func-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
@@ -641,7 +642,7 @@
     <elf-symbol name='sa_protocol_names' size='16' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='spa_feature_table' size='2632' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zfeature_checks_disable' size='4' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
-    <elf-symbol name='zfs_deleg_perm_tab' size='528' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
+    <elf-symbol name='zfs_deleg_perm_tab' size='544' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zfs_history_event_names' size='328' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zfs_max_dataset_nesting' size='4' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
     <elf-symbol name='zfs_userquota_prop_prefixes' size='96' type='object-type' binding='global-binding' visibility='default-visibility' is-defined='yes'/>
@@ -1458,103 +1459,8 @@
     </function-decl>
   </abi-instr>
   <abi-instr address-size='64' path='lib/libspl/os/linux/getmntany.c' language='LANG_C99'>
-    <array-type-def dimensions='1' type-id='d315442e' size-in-bits='16' id='811205dc'>
-      <subrange length='1' type-id='7359adad' id='52f813b4'/>
-    </array-type-def>
-    <array-type-def dimensions='1' type-id='d3130597' size-in-bits='768' id='f63f23b9'>
-      <subrange length='12' type-id='7359adad' id='84827bdc'/>
-    </array-type-def>
-    <typedef-decl name='__u16' type-id='8efea9e5' id='d315442e'/>
-    <typedef-decl name='__s32' type-id='95e97e5e' id='3158a266'/>
-    <typedef-decl name='__u32' type-id='f0981eeb' id='3f1a6b60'/>
-    <typedef-decl name='__s64' type-id='1eb56b1e' id='49659421'/>
-    <typedef-decl name='__u64' type-id='3a47d82b' id='d3130597'/>
-    <class-decl name='statx_timestamp' size-in-bits='128' is-struct='yes' visibility='default' id='94101016'>
-      <data-member access='public' layout-offset-in-bits='0'>
-        <var-decl name='tv_sec' type-id='49659421' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='64'>
-        <var-decl name='tv_nsec' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='96'>
-        <var-decl name='__reserved' type-id='3158a266' visibility='default'/>
-      </data-member>
-    </class-decl>
-    <class-decl name='statx' size-in-bits='2048' is-struct='yes' visibility='default' id='720b04c5'>
-      <data-member access='public' layout-offset-in-bits='0'>
-        <var-decl name='stx_mask' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='32'>
-        <var-decl name='stx_blksize' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='64'>
-        <var-decl name='stx_attributes' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='128'>
-        <var-decl name='stx_nlink' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='160'>
-        <var-decl name='stx_uid' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='192'>
-        <var-decl name='stx_gid' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='224'>
-        <var-decl name='stx_mode' type-id='d315442e' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='240'>
-        <var-decl name='__spare0' type-id='811205dc' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='256'>
-        <var-decl name='stx_ino' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='320'>
-        <var-decl name='stx_size' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='384'>
-        <var-decl name='stx_blocks' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='448'>
-        <var-decl name='stx_attributes_mask' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='512'>
-        <var-decl name='stx_atime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='640'>
-        <var-decl name='stx_btime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='768'>
-        <var-decl name='stx_ctime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='896'>
-        <var-decl name='stx_mtime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1024'>
-        <var-decl name='stx_rdev_major' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1056'>
-        <var-decl name='stx_rdev_minor' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1088'>
-        <var-decl name='stx_dev_major' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1120'>
-        <var-decl name='stx_dev_minor' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1152'>
-        <var-decl name='stx_mnt_id' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1216'>
-        <var-decl name='__spare2' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1280'>
-        <var-decl name='__spare3' type-id='f63f23b9' visibility='default'/>
-      </data-member>
-    </class-decl>
     <pointer-type-def type-id='56fe4a37' size-in-bits='64' id='b6b61d2f'/>
     <qualified-type-def type-id='b6b61d2f' restrict='yes' id='3cad23cd'/>
-    <pointer-type-def type-id='720b04c5' size-in-bits='64' id='936b8e35'/>
-    <qualified-type-def type-id='936b8e35' restrict='yes' id='31d265b7'/>
     <function-decl name='getmntent_r' visibility='default' binding='global' size-in-bits='64'>
       <parameter type-id='e75a27e9'/>
       <parameter type-id='3cad23cd'/>
@@ -1566,14 +1472,6 @@
       <parameter type-id='822cd80b'/>
       <return type-id='95e97e5e'/>
     </function-decl>
-    <function-decl name='statx' visibility='default' binding='global' size-in-bits='64'>
-      <parameter type-id='95e97e5e'/>
-      <parameter type-id='9d26089a'/>
-      <parameter type-id='95e97e5e'/>
-      <parameter type-id='f0981eeb'/>
-      <parameter type-id='31d265b7'/>
-      <return type-id='95e97e5e'/>
-    </function-decl>
   </abi-instr>
   <abi-instr address-size='64' path='lib/libspl/timestamp.c' language='LANG_C99'>
     <typedef-decl name='nl_item' type-id='95e97e5e' id='03b79a94'/>
@@ -3194,6 +3092,10 @@
       <parameter type-id='dace003f'/>
       <return type-id='80f4b756'/>
     </function-decl>
+    <function-decl name='fnvlist_dup' visibility='default' binding='global' size-in-bits='64'>
+      <parameter type-id='22cce67b'/>
+      <return type-id='5ce45b60'/>
+    </function-decl>
     <function-decl name='fnvpair_value_nvlist' visibility='default' binding='global' size-in-bits='64'>
       <parameter type-id='3fa542f0'/>
       <return type-id='5ce45b60'/>
@@ -3238,6 +3140,11 @@
       <parameter type-id='37e3bd22' name='missing'/>
       <return type-id='95e97e5e'/>
     </function-decl>
+    <function-decl name='zpool_refresh_stats_from_handle' mangled-name='zpool_refresh_stats_from_handle' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='zpool_refresh_stats_from_handle'>
+      <parameter type-id='4c81de99' name='dzhp'/>
+      <parameter type-id='4c81de99' name='szhp'/>
+      <return type-id='48b5725f'/>
+    </function-decl>
     <function-decl name='zpool_skip_pool' mangled-name='zpool_skip_pool' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='zpool_skip_pool'>
       <parameter type-id='80f4b756' name='poolname'/>
       <return type-id='c19b74c3'/>
@@ -9398,10 +9305,6 @@
       <parameter type-id='5ce45b60'/>
       <return type-id='48b5725f'/>
     </function-decl>
-    <function-decl name='fnvlist_dup' visibility='default' binding='global' size-in-bits='64'>
-      <parameter type-id='22cce67b'/>
-      <return type-id='5ce45b60'/>
-    </function-decl>
     <function-decl name='spl_pagesize' mangled-name='spl_pagesize' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='spl_pagesize'>
       <return type-id='b59d7dce'/>
     </function-decl>
@@ -9774,8 +9677,8 @@
     </function-decl>
   </abi-instr>
   <abi-instr address-size='64' path='module/zcommon/zfs_deleg.c' language='LANG_C99'>
-    <array-type-def dimensions='1' type-id='fa1870fd' size-in-bits='4224' id='55e705e7'>
-      <subrange length='33' type-id='7359adad' id='6a5934df'/>
+    <array-type-def dimensions='1' type-id='fa1870fd' size-in-bits='4352' id='55f84f08'>
+      <subrange length='34' type-id='7359adad' id='6a6a7e00'/>
     </array-type-def>
     <array-type-def dimensions='1' type-id='fa1870fd' size-in-bits='infinite' id='7c00e69d'>
       <subrange length='infinite' id='031f2035'/>
@@ -9805,30 +9708,31 @@
       <enumerator name='ZFS_DELEG_NOTE_PROMOTE' value='5'/>
       <enumerator name='ZFS_DELEG_NOTE_RENAME' value='6'/>
       <enumerator name='ZFS_DELEG_NOTE_SEND' value='7'/>
-      <enumerator name='ZFS_DELEG_NOTE_RECEIVE' value='8'/>
-      <enumerator name='ZFS_DELEG_NOTE_ALLOW' value='9'/>
-      <enumerator name='ZFS_DELEG_NOTE_USERPROP' value='10'/>
-      <enumerator name='ZFS_DELEG_NOTE_MOUNT' value='11'/>
-      <enumerator name='ZFS_DELEG_NOTE_SHARE' value='12'/>
-      <enumerator name='ZFS_DELEG_NOTE_USERQUOTA' value='13'/>
-      <enumerator name='ZFS_DELEG_NOTE_GROUPQUOTA' value='14'/>
-      <enumerator name='ZFS_DELEG_NOTE_USERUSED' value='15'/>
-      <enumerator name='ZFS_DELEG_NOTE_GROUPUSED' value='16'/>
-      <enumerator name='ZFS_DELEG_NOTE_USEROBJQUOTA' value='17'/>
-      <enumerator name='ZFS_DELEG_NOTE_GROUPOBJQUOTA' value='18'/>
-      <enumerator name='ZFS_DELEG_NOTE_USEROBJUSED' value='19'/>
-      <enumerator name='ZFS_DELEG_NOTE_GROUPOBJUSED' value='20'/>
-      <enumerator name='ZFS_DELEG_NOTE_HOLD' value='21'/>
-      <enumerator name='ZFS_DELEG_NOTE_RELEASE' value='22'/>
-      <enumerator name='ZFS_DELEG_NOTE_DIFF' value='23'/>
-      <enumerator name='ZFS_DELEG_NOTE_BOOKMARK' value='24'/>
-      <enumerator name='ZFS_DELEG_NOTE_LOAD_KEY' value='25'/>
-      <enumerator name='ZFS_DELEG_NOTE_CHANGE_KEY' value='26'/>
-      <enumerator name='ZFS_DELEG_NOTE_PROJECTUSED' value='27'/>
-      <enumerator name='ZFS_DELEG_NOTE_PROJECTQUOTA' value='28'/>
-      <enumerator name='ZFS_DELEG_NOTE_PROJECTOBJUSED' value='29'/>
-      <enumerator name='ZFS_DELEG_NOTE_PROJECTOBJQUOTA' value='30'/>
-      <enumerator name='ZFS_DELEG_NOTE_NONE' value='31'/>
+      <enumerator name='ZFS_DELEG_NOTE_SEND_RAW' value='8'/>
+      <enumerator name='ZFS_DELEG_NOTE_RECEIVE' value='9'/>
+      <enumerator name='ZFS_DELEG_NOTE_ALLOW' value='10'/>
+      <enumerator name='ZFS_DELEG_NOTE_USERPROP' value='11'/>
+      <enumerator name='ZFS_DELEG_NOTE_MOUNT' value='12'/>
+      <enumerator name='ZFS_DELEG_NOTE_SHARE' value='13'/>
+      <enumerator name='ZFS_DELEG_NOTE_USERQUOTA' value='14'/>
+      <enumerator name='ZFS_DELEG_NOTE_GROUPQUOTA' value='15'/>
+      <enumerator name='ZFS_DELEG_NOTE_USERUSED' value='16'/>
+      <enumerator name='ZFS_DELEG_NOTE_GROUPUSED' value='17'/>
+      <enumerator name='ZFS_DELEG_NOTE_USEROBJQUOTA' value='18'/>
+      <enumerator name='ZFS_DELEG_NOTE_GROUPOBJQUOTA' value='19'/>
+      <enumerator name='ZFS_DELEG_NOTE_USEROBJUSED' value='20'/>
+      <enumerator name='ZFS_DELEG_NOTE_GROUPOBJUSED' value='21'/>
+      <enumerator name='ZFS_DELEG_NOTE_HOLD' value='22'/>
+      <enumerator name='ZFS_DELEG_NOTE_RELEASE' value='23'/>
+      <enumerator name='ZFS_DELEG_NOTE_DIFF' value='24'/>
+      <enumerator name='ZFS_DELEG_NOTE_BOOKMARK' value='25'/>
+      <enumerator name='ZFS_DELEG_NOTE_LOAD_KEY' value='26'/>
+      <enumerator name='ZFS_DELEG_NOTE_CHANGE_KEY' value='27'/>
+      <enumerator name='ZFS_DELEG_NOTE_PROJECTUSED' value='28'/>
+      <enumerator name='ZFS_DELEG_NOTE_PROJECTQUOTA' value='29'/>
+      <enumerator name='ZFS_DELEG_NOTE_PROJECTOBJUSED' value='30'/>
+      <enumerator name='ZFS_DELEG_NOTE_PROJECTOBJQUOTA' value='31'/>
+      <enumerator name='ZFS_DELEG_NOTE_NONE' value='32'/>
     </enum-decl>
     <typedef-decl name='zfs_deleg_note_t' type-id='729d4547' id='4613c173'/>
     <class-decl name='zfs_deleg_perm_tab' size-in-bits='128' is-struct='yes' visibility='default' id='5aa05c1f'>
diff --git a/sys/contrib/openzfs/lib/libzfs/libzfs_config.c b/sys/contrib/openzfs/lib/libzfs/libzfs_config.c
index 0d2102191389..9d704e4303ff 100644
--- a/sys/contrib/openzfs/lib/libzfs/libzfs_config.c
+++ b/sys/contrib/openzfs/lib/libzfs/libzfs_config.c
@@ -308,6 +308,23 @@ zpool_refresh_stats(zpool_handle_t *zhp, boolean_t *missing)
 }
 
 /*
+ * Copies the pool config and state from szhp to dzhp. szhp and dzhp must
+ * represent the same pool. Used by pool_list_refresh() to avoid another
+ * round-trip into the kernel to get stats already collected earlier in the
+ * function.
+ */
+void
+zpool_refresh_stats_from_handle(zpool_handle_t *dzhp, zpool_handle_t *szhp)
+{
+	VERIFY0(strcmp(dzhp->zpool_name, szhp->zpool_name));
+	nvlist_free(dzhp->zpool_old_config);
+	dzhp->zpool_old_config = dzhp->zpool_config;
+	dzhp->zpool_config = fnvlist_dup(szhp->zpool_config);
+	dzhp->zpool_config_size = szhp->zpool_config_size;
+	dzhp->zpool_state = szhp->zpool_state;
+}
+
+/*
  * The following environment variables are undocumented
  * and should be used for testing purposes only:
  *
diff --git a/sys/contrib/openzfs/lib/libzfs_core/libzfs_core.abi b/sys/contrib/openzfs/lib/libzfs_core/libzfs_core.abi
index 7464b3adb254..263cad045f7a 100644
--- a/sys/contrib/openzfs/lib/libzfs_core/libzfs_core.abi
+++ b/sys/contrib/openzfs/lib/libzfs_core/libzfs_core.abi
@@ -617,6 +617,7 @@
     <array-type-def dimensions='1' type-id='de572c22' size-in-bits='1472' id='6d3c2f42'>
       <subrange length='23' type-id='7359adad' id='fdd0f594'/>
     </array-type-def>
+    <type-decl name='long long int' size-in-bits='64' id='1eb56b1e'/>
     <array-type-def dimensions='1' type-id='3a47d82b' size-in-bits='256' id='a133ec23'>
       <subrange length='4' type-id='7359adad' id='16fe7105'/>
     </array-type-def>
@@ -988,13 +989,6 @@
     </function-decl>
   </abi-instr>
   <abi-instr address-size='64' path='lib/libspl/os/linux/getmntany.c' language='LANG_C99'>
-    <array-type-def dimensions='1' type-id='d315442e' size-in-bits='16' id='811205dc'>
-      <subrange length='1' type-id='7359adad' id='52f813b4'/>
-    </array-type-def>
-    <array-type-def dimensions='1' type-id='d3130597' size-in-bits='768' id='f63f23b9'>
-      <subrange length='12' type-id='7359adad' id='84827bdc'/>
-    </array-type-def>
-    <type-decl name='long long int' size-in-bits='64' id='1eb56b1e'/>
     <class-decl name='mnttab' size-in-bits='256' is-struct='yes' visibility='default' id='1b055409'>
       <data-member access='public' layout-offset-in-bits='0'>
         <var-decl name='mnt_special' type-id='26a90f95' visibility='default'/>
@@ -1029,93 +1023,6 @@
         <var-decl name='mnt_minor' type-id='3502e3ff' visibility='default'/>
       </data-member>
     </class-decl>
-    <typedef-decl name='__u16' type-id='8efea9e5' id='d315442e'/>
-    <typedef-decl name='__s32' type-id='95e97e5e' id='3158a266'/>
-    <typedef-decl name='__u32' type-id='f0981eeb' id='3f1a6b60'/>
-    <typedef-decl name='__s64' type-id='1eb56b1e' id='49659421'/>
-    <typedef-decl name='__u64' type-id='3a47d82b' id='d3130597'/>
-    <class-decl name='statx_timestamp' size-in-bits='128' is-struct='yes' visibility='default' id='94101016'>
-      <data-member access='public' layout-offset-in-bits='0'>
-        <var-decl name='tv_sec' type-id='49659421' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='64'>
-        <var-decl name='tv_nsec' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='96'>
-        <var-decl name='__reserved' type-id='3158a266' visibility='default'/>
-      </data-member>
-    </class-decl>
-    <class-decl name='statx' size-in-bits='2048' is-struct='yes' visibility='default' id='720b04c5'>
-      <data-member access='public' layout-offset-in-bits='0'>
-        <var-decl name='stx_mask' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='32'>
-        <var-decl name='stx_blksize' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='64'>
-        <var-decl name='stx_attributes' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='128'>
-        <var-decl name='stx_nlink' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='160'>
-        <var-decl name='stx_uid' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='192'>
-        <var-decl name='stx_gid' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='224'>
-        <var-decl name='stx_mode' type-id='d315442e' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='240'>
-        <var-decl name='__spare0' type-id='811205dc' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='256'>
-        <var-decl name='stx_ino' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='320'>
-        <var-decl name='stx_size' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='384'>
-        <var-decl name='stx_blocks' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='448'>
-        <var-decl name='stx_attributes_mask' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='512'>
-        <var-decl name='stx_atime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='640'>
-        <var-decl name='stx_btime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='768'>
-        <var-decl name='stx_ctime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='896'>
-        <var-decl name='stx_mtime' type-id='94101016' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1024'>
-        <var-decl name='stx_rdev_major' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1056'>
-        <var-decl name='stx_rdev_minor' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1088'>
-        <var-decl name='stx_dev_major' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1120'>
-        <var-decl name='stx_dev_minor' type-id='3f1a6b60' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1152'>
-        <var-decl name='stx_mnt_id' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1216'>
-        <var-decl name='__spare2' type-id='d3130597' visibility='default'/>
-      </data-member>
-      <data-member access='public' layout-offset-in-bits='1280'>
-        <var-decl name='__spare3' type-id='f63f23b9' visibility='default'/>
-      </data-member>
-    </class-decl>
     <class-decl name='mntent' size-in-bits='320' is-struct='yes' visibility='default' id='56fe4a37'>
       <data-member access='public' layout-offset-in-bits='0'>
         <var-decl name='mnt_fsname' type-id='26a90f95' visibility='default'/>
@@ -1191,8 +1098,6 @@
     <pointer-type-def type-id='1b055409' size-in-bits='64' id='9d424d31'/>
     <pointer-type-def type-id='0bbec9cd' size-in-bits='64' id='62f7a03d'/>
     <qualified-type-def type-id='62f7a03d' restrict='yes' id='f1cadedf'/>
-    <pointer-type-def type-id='720b04c5' size-in-bits='64' id='936b8e35'/>
-    <qualified-type-def type-id='936b8e35' restrict='yes' id='31d265b7'/>
     <function-decl name='getmntent_r' visibility='default' binding='global' size-in-bits='64'>
       <parameter type-id='e75a27e9'/>
       <parameter type-id='3cad23cd'/>
@@ -1208,14 +1113,6 @@
       <parameter type-id='95e97e5e'/>
       <return type-id='26a90f95'/>
     </function-decl>
-    <function-decl name='statx' visibility='default' binding='global' size-in-bits='64'>
-      <parameter type-id='95e97e5e'/>
-      <parameter type-id='9d26089a'/>
-      <parameter type-id='95e97e5e'/>
-      <parameter type-id='f0981eeb'/>
-      <parameter type-id='31d265b7'/>
-      <return type-id='95e97e5e'/>
-    </function-decl>
     <function-decl name='stat64' visibility='default' binding='global' size-in-bits='64'>
       <parameter type-id='9d26089a'/>
       <parameter type-id='f1cadedf'/>
diff --git a/sys/contrib/openzfs/man/man8/zinject.8 b/sys/contrib/openzfs/man/man8/zinject.8
index 1d9e43aed5ec..704f6a7accd8 100644
--- a/sys/contrib/openzfs/man/man8/zinject.8
+++ b/sys/contrib/openzfs/man/man8/zinject.8
@@ -138,6 +138,20 @@ This injector is automatically cleared after the import is finished.
 .
 .It Xo
 .Nm zinject
+.Fl E Ar delay
+.Op Fl a
+.Op Fl m
+.Op Fl f Ar freq
+.Op Fl l Ar level
+.Op Fl r Ar range
+.Op Fl T Ar iotype
+.Op Fl t Ar type Ns | Ns Fl b Ar bookmark
+.Xc
+Inject pipeline ready stage delays for the given object or bookmark.
+The delay is specified in milliseconds.
+.
+.It Xo
+.Nm zinject
 .Fl I
 .Op Fl s Ar seconds Ns | Ns Fl g Ar txgs
 .Ar pool
diff --git a/sys/contrib/openzfs/man/man8/zpool-upgrade.8 b/sys/contrib/openzfs/man/man8/zpool-upgrade.8
index cf69060da5ce..adae47f82eb1 100644
--- a/sys/contrib/openzfs/man/man8/zpool-upgrade.8
+++ b/sys/contrib/openzfs/man/man8/zpool-upgrade.8
@@ -65,10 +65,10 @@ property).
 .Cm upgrade
 .Fl v
 .Xc
-Displays legacy ZFS versions supported by the this version of ZFS.
+Displays legacy ZFS versions supported by this version of ZFS.
 See
 .Xr zpool-features 7
-for a description of feature flags features supported by this version of ZFS.
+for a description of features supported by this version of ZFS.
 .It Xo
 .Nm zpool
 .Cm upgrade
diff --git a/sys/contrib/openzfs/module/os/linux/zfs/zvol_os.c b/sys/contrib/openzfs/module/os/linux/zfs/zvol_os.c
index bac166fcd89e..967a018640e1 100644
--- a/sys/contrib/openzfs/module/os/linux/zfs/zvol_os.c
+++ b/sys/contrib/openzfs/module/os/linux/zfs/zvol_os.c
@@ -484,7 +484,28 @@ zvol_request_impl(zvol_state_t *zv, struct bio *bio, struct request *rq,
 	fstrans_cookie_t cookie = spl_fstrans_mark();
 	uint64_t offset = io_offset(bio, rq);
 	uint64_t size = io_size(bio, rq);
-	int rw = io_data_dir(bio, rq);
+	int rw;
+
+	if (rq != NULL) {
+		/*
+		 * Flush & trim requests go down the zvol_write codepath.  Or
+		 * more specifically:
+		 *
+		 * If request is a write, or if it's op_is_sync() and not a
+		 * read, or if it's a flush, or if it's a discard, then send the
+		 * request down the write path.
+		 */
+		if (op_is_write(rq->cmd_flags) ||
+		    (op_is_sync(rq->cmd_flags) && req_op(rq) != REQ_OP_READ) ||
+		    req_op(rq) == REQ_OP_FLUSH ||
+		    op_is_discard(rq->cmd_flags)) {
+			rw = WRITE;
+		} else {
+			rw = READ;
+		}
+	} else {
+		rw = bio_data_dir(bio);
+	}
 
 	if (unlikely(zv->zv_flags & ZVOL_REMOVING)) {
 		zvol_end_io(bio, rq, SET_ERROR(ENXIO));
diff --git a/sys/contrib/openzfs/module/zcommon/zfs_prop.c b/sys/contrib/openzfs/module/zcommon/zfs_prop.c
index 864e3898b365..9190ae0362ea 100644
--- a/sys/contrib/openzfs/module/zcommon/zfs_prop.c
+++ b/sys/contrib/openzfs/module/zcommon/zfs_prop.c
@@ -364,8 +364,8 @@ zfs_prop_init(void)
 
 	static const zprop_index_t xattr_table[] = {
 		{ "off",	ZFS_XATTR_OFF },
-		{ "on",		ZFS_XATTR_SA },
 		{ "sa",		ZFS_XATTR_SA },
+		{ "on",		ZFS_XATTR_SA },
 		{ "dir",	ZFS_XATTR_DIR },
 		{ NULL }
 	};
diff --git a/sys/contrib/openzfs/module/zfs/arc.c b/sys/contrib/openzfs/module/zfs/arc.c
index bd6dc8edd8ca..591e2dade59e 100644
--- a/sys/contrib/openzfs/module/zfs/arc.c
+++ b/sys/contrib/openzfs/module/zfs/arc.c
@@ -1392,6 +1392,7 @@ arc_get_complevel(arc_buf_t *buf)
 	return (buf->b_hdr->b_complevel);
 }
 
+__maybe_unused
 static inline boolean_t
 arc_buf_is_shared(arc_buf_t *buf)
 {
diff --git a/sys/contrib/openzfs/module/zfs/dnode.c b/sys/contrib/openzfs/module/zfs/dnode.c
index 6c150d31c669..e88d394b5229 100644
--- a/sys/contrib/openzfs/module/zfs/dnode.c
+++ b/sys/contrib/openzfs/module/zfs/dnode.c
@@ -2656,6 +2656,32 @@ dnode_next_offset_level(dnode_t *dn, int flags, uint64_t *offset,
 }
 
 /*
+ * Adjust *offset to the next (or previous) block byte offset at lvl.
+ * Returns FALSE if *offset would overflow or underflow.
+ */
+static boolean_t
+dnode_next_block(dnode_t *dn, int flags, uint64_t *offset, int lvl)
+{
+	int epbs = dn->dn_indblkshift - SPA_BLKPTRSHIFT;
+	int span = lvl * epbs + dn->dn_datablkshift;
+	uint64_t blkid, maxblkid;
+
+	if (span >= 8 * sizeof (uint64_t))
+		return (B_FALSE);
+
+	blkid = *offset >> span;
+	maxblkid = 1ULL << (8 * sizeof (*offset) - span);
+	if (!(flags & DNODE_FIND_BACKWARDS) && blkid + 1 < maxblkid)
+		*offset = (blkid + 1) << span;
+	else if ((flags & DNODE_FIND_BACKWARDS) && blkid > 0)
+		*offset = (blkid << span) - 1;
+	else
+		return (B_FALSE);
+
+	return (B_TRUE);
+}
+
+/*
  * Find the next hole, data, or sparse region at or after *offset.
  * The value 'blkfill' tells us how many items we expect to find
  * in an L0 data block; this value is 1 for normal objects,
@@ -2682,7 +2708,7 @@ int
 dnode_next_offset(dnode_t *dn, int flags, uint64_t *offset,
     int minlvl, uint64_t blkfill, uint64_t txg)
 {
-	uint64_t initial_offset = *offset;
+	uint64_t matched = *offset;
 	int lvl, maxlvl;
 	int error = 0;
 
@@ -2706,16 +2732,36 @@ dnode_next_offset(dnode_t *dn, int flags, uint64_t *offset,
 
 	maxlvl = dn->dn_phys->dn_nlevels;
 
-	for (lvl = minlvl; lvl <= maxlvl; lvl++) {
+	for (lvl = minlvl; lvl <= maxlvl; ) {
 		error = dnode_next_offset_level(dn,
 		    flags, offset, lvl, blkfill, txg);
-		if (error != ESRCH)
+		if (error == 0 && lvl > minlvl) {
+			--lvl;
+			matched = *offset;
+		} else if (error == ESRCH && lvl < maxlvl &&
+		    dnode_next_block(dn, flags, &matched, lvl)) {
+			/*
+			 * Continue search at next/prev offset in lvl+1 block.
+			 *
+			 * Usually we only search upwards at the start of the
+			 * search as higher level blocks point at a matching
+			 * minlvl block in most cases, but we backtrack if not.
+			 *
+			 * This can happen for txg > 0 searches if the block
+			 * contains only BPs/dnodes freed at that txg. It also
+			 * happens if we are still syncing out the tree, and
+			 * some BP's at higher levels are not updated yet.
+			 *
+			 * We must adjust offset to avoid coming back to the
+			 * same offset and getting stuck looping forever. This
+			 * also deals with the case where offset is already at
+			 * the beginning or end of the object.
+			 */
+			++lvl;
+			*offset = matched;
+		} else {
 			break;
-	}
-
-	while (error == 0 && --lvl >= minlvl) {
-		error = dnode_next_offset_level(dn,
-		    flags, offset, lvl, blkfill, txg);
+		}
 	}
 
 	/*
@@ -2727,9 +2773,6 @@ dnode_next_offset(dnode_t *dn, int flags, uint64_t *offset,
 		error = 0;
 	}
 
-	if (error == 0 && (flags & DNODE_FIND_BACKWARDS ?
-	    initial_offset < *offset : initial_offset > *offset))
-		error = SET_ERROR(ESRCH);
 out:
 	if (!(flags & DNODE_FIND_HAVELOCK))
 		rw_exit(&dn->dn_struct_rwlock);
diff --git a/sys/contrib/openzfs/module/zfs/mmp.c b/sys/contrib/openzfs/module/zfs/mmp.c
index 7db72b9b04b0..fd46127b6068 100644
--- a/sys/contrib/openzfs/module/zfs/mmp.c
+++ b/sys/contrib/openzfs/module/zfs/mmp.c
@@ -446,7 +446,7 @@ mmp_write_uberblock(spa_t *spa)
 	uint64_t offset;
 
 	hrtime_t lock_acquire_time = gethrtime();
-	spa_config_enter_mmp(spa, SCL_STATE, mmp_tag, RW_READER);
+	spa_config_enter_priority(spa, SCL_STATE, mmp_tag, RW_READER);
 	lock_acquire_time = gethrtime() - lock_acquire_time;
 	if (lock_acquire_time > (MSEC2NSEC(MMP_MIN_INTERVAL) / 10))
 		zfs_dbgmsg("MMP SCL_STATE acquisition pool '%s' took %llu ns "
diff --git a/sys/contrib/openzfs/module/zfs/range_tree.c b/sys/contrib/openzfs/module/zfs/range_tree.c
index ea2d2c7227c8..d73195f1a21f 100644
--- a/sys/contrib/openzfs/module/zfs/range_tree.c
+++ b/sys/contrib/openzfs/module/zfs/range_tree.c
@@ -585,7 +585,7 @@ zfs_range_tree_remove_impl(zfs_range_tree_t *rt, uint64_t start, uint64_t size,
 		 * the size, since we do not support removing partial segments
 		 * of range trees with gaps.
 		 */
-		zfs_zfs_rs_set_fill_raw(rs, rt, zfs_rs_get_end_raw(rs, rt) -
+		zfs_rs_set_fill_raw(rs, rt, zfs_rs_get_end_raw(rs, rt) -
 		    zfs_rs_get_start_raw(rs, rt));
 		zfs_range_tree_stat_incr(rt, &rs_tmp);
 
diff --git a/sys/contrib/openzfs/module/zfs/spa_config.c b/sys/contrib/openzfs/module/zfs/spa_config.c
index cf28955b0c50..f615591e826b 100644
--- a/sys/contrib/openzfs/module/zfs/spa_config.c
+++ b/sys/contrib/openzfs/module/zfs/spa_config.c
@@ -372,6 +372,8 @@ spa_config_generate(spa_t *spa, vdev_t *vd, uint64_t txg, int getstats)
 	fnvlist_add_uint64(config, ZPOOL_CONFIG_POOL_TXG, txg);
 	fnvlist_add_uint64(config, ZPOOL_CONFIG_POOL_GUID, spa_guid(spa));
 	fnvlist_add_uint64(config, ZPOOL_CONFIG_ERRATA, spa->spa_errata);
+	fnvlist_add_uint64(config, ZPOOL_CONFIG_MIN_ALLOC, spa->spa_min_alloc);
+	fnvlist_add_uint64(config, ZPOOL_CONFIG_MAX_ALLOC, spa->spa_max_alloc);
 	if (spa->spa_comment != NULL)
 		fnvlist_add_string(config, ZPOOL_CONFIG_COMMENT,
 		    spa->spa_comment);
diff --git a/sys/contrib/openzfs/module/zfs/spa_misc.c b/sys/contrib/openzfs/module/zfs/spa_misc.c
index 6f7c060f97f8..0bead6d49666 100644
--- a/sys/contrib/openzfs/module/zfs/spa_misc.c
+++ b/sys/contrib/openzfs/module/zfs/spa_misc.c
@@ -510,7 +510,7 @@ spa_config_tryenter(spa_t *spa, int locks, const void *tag, krw_t rw)
 
 static void
 spa_config_enter_impl(spa_t *spa, int locks, const void *tag, krw_t rw,
-    int mmp_flag)
+    int priority_flag)
 {
 	(void) tag;
 	int wlocks_held = 0;
@@ -526,7 +526,7 @@ spa_config_enter_impl(spa_t *spa, int locks, const void *tag, krw_t rw,
 		mutex_enter(&scl->scl_lock);
 		if (rw == RW_READER) {
 			while (scl->scl_writer ||
-			    (!mmp_flag && scl->scl_write_wanted)) {
+			    (!priority_flag && scl->scl_write_wanted)) {
 				cv_wait(&scl->scl_cv, &scl->scl_lock);
 			}
 		} else {
@@ -551,7 +551,7 @@ spa_config_enter(spa_t *spa, int locks, const void *tag, krw_t rw)
 }
 
 /*
- * The spa_config_enter_mmp() allows the mmp thread to cut in front of
+ * The spa_config_enter_priority() allows the mmp thread to cut in front of
  * outstanding write lock requests. This is needed since the mmp updates are
  * time sensitive and failure to service them promptly will result in a
  * suspended pool. This pool suspension has been seen in practice when there is
@@ -560,7 +560,7 @@ spa_config_enter(spa_t *spa, int locks, const void *tag, krw_t rw)
  */
 
 void
-spa_config_enter_mmp(spa_t *spa, int locks, const void *tag, krw_t rw)
+spa_config_enter_priority(spa_t *spa, int locks, const void *tag, krw_t rw)
 {
 	spa_config_enter_impl(spa, locks, tag, rw, 1);
 }
@@ -806,6 +806,7 @@ spa_add(const char *name, nvlist_t *config, const char *altroot)
 	spa->spa_min_ashift = INT_MAX;
 	spa->spa_max_ashift = 0;
 	spa->spa_min_alloc = INT_MAX;
+	spa->spa_max_alloc = 0;
 	spa->spa_gcd_alloc = INT_MAX;
 
 	/* Reset cached value */
@@ -1865,6 +1866,19 @@ spa_get_worst_case_asize(spa_t *spa, uint64_t lsize)
 }
 
 /*
+ * Return the range of minimum allocation sizes for the normal allocation
+ * class. This can be used by external consumers of the DMU to estimate
+ * potential wasted capacity when setting the recordsize for an object.
+ * This is mainly for dRAID pools which always pad to a full stripe width.
+ */
+void
+spa_get_min_alloc_range(spa_t *spa, uint64_t *min_alloc, uint64_t *max_alloc)
+{
+	*min_alloc = spa->spa_min_alloc;
+	*max_alloc = spa->spa_max_alloc;
+}
+
+/*
  * Return the amount of slop space in bytes.  It is typically 1/32 of the pool
  * (3.2%), minus the embedded log space.  On very small pools, it may be
  * slightly larger than this.  On very large pools, it will be capped to
@@ -3085,6 +3099,7 @@ EXPORT_SYMBOL(spa_version);
 EXPORT_SYMBOL(spa_state);
 EXPORT_SYMBOL(spa_load_state);
 EXPORT_SYMBOL(spa_freeze_txg);
+EXPORT_SYMBOL(spa_get_min_alloc_range); /* for Lustre */
 EXPORT_SYMBOL(spa_get_dspace);
 EXPORT_SYMBOL(spa_update_dspace);
 EXPORT_SYMBOL(spa_deflate);
diff --git a/sys/contrib/openzfs/module/zfs/vdev.c b/sys/contrib/openzfs/module/zfs/vdev.c
index fc6d445f9785..654e034de9e1 100644
--- a/sys/contrib/openzfs/module/zfs/vdev.c
+++ b/sys/contrib/openzfs/module/zfs/vdev.c
@@ -1497,12 +1497,14 @@ vdev_spa_set_alloc(spa_t *spa, uint64_t min_alloc)
 {
 	if (min_alloc < spa->spa_min_alloc)
 		spa->spa_min_alloc = min_alloc;
-	if (spa->spa_gcd_alloc == INT_MAX) {
+
+	if (min_alloc > spa->spa_max_alloc)
+		spa->spa_max_alloc = min_alloc;
+
+	if (spa->spa_gcd_alloc == INT_MAX)
 		spa->spa_gcd_alloc = min_alloc;
-	} else {
-		spa->spa_gcd_alloc = vdev_gcd(min_alloc,
-		    spa->spa_gcd_alloc);
-	}
+	else
+		spa->spa_gcd_alloc = vdev_gcd(min_alloc, spa->spa_gcd_alloc);
 }
 
 void
@@ -1560,8 +1562,7 @@ vdev_metaslab_group_create(vdev_t *vd)
 			if (vd->vdev_ashift < spa->spa_min_ashift)
 				spa->spa_min_ashift = vd->vdev_ashift;
 
-			uint64_t min_alloc = vdev_get_min_alloc(vd);
-			vdev_spa_set_alloc(spa, min_alloc);
+			vdev_spa_set_alloc(spa, vdev_get_min_alloc(vd));
 		}
 	}
 }
diff --git a/sys/contrib/openzfs/module/zfs/vdev_label.c b/sys/contrib/openzfs/module/zfs/vdev_label.c
index c44f654b0261..0d4fdaa77ba0 100644
--- a/sys/contrib/openzfs/module/zfs/vdev_label.c
+++ b/sys/contrib/openzfs/module/zfs/vdev_label.c
@@ -511,6 +511,8 @@ vdev_config_generate(spa_t *spa, vdev_t *vd, boolean_t getstats,
 		fnvlist_add_uint64(nv, ZPOOL_CONFIG_ASHIFT, vd->vdev_ashift);
 		fnvlist_add_uint64(nv, ZPOOL_CONFIG_ASIZE,
 		    vd->vdev_asize);
+		fnvlist_add_uint64(nv, ZPOOL_CONFIG_MIN_ALLOC,
+		    vdev_get_min_alloc(vd));
 		fnvlist_add_uint64(nv, ZPOOL_CONFIG_IS_LOG, vd->vdev_islog);
 		if (vd->vdev_noalloc) {
 			fnvlist_add_uint64(nv, ZPOOL_CONFIG_NONALLOCATING,
diff --git a/sys/contrib/openzfs/module/zfs/zio.c b/sys/contrib/openzfs/module/zfs/zio.c
index 4cf8912d4269..aeea58bedfe4 100644
--- a/sys/contrib/openzfs/module/zfs/zio.c
+++ b/sys/contrib/openzfs/module/zfs/zio.c
@@ -4574,8 +4574,29 @@ zio_vdev_io_start(zio_t *zio)
 	ASSERT0(zio->io_child_error[ZIO_CHILD_VDEV]);
 
 	if (vd == NULL) {
-		if (!(zio->io_flags & ZIO_FLAG_CONFIG_WRITER))
-			spa_config_enter(spa, SCL_ZIO, zio, RW_READER);
+		if (!(zio->io_flags & ZIO_FLAG_CONFIG_WRITER)) {
+			/*
+			 * A deadlock workaround. The ddt_prune_unique_entries()
+			 * -> prune_candidates_sync() code path takes the
+			 * SCL_ZIO reader lock and may request it again here.
+			 * If there is another thread who wants the SCL_ZIO
+			 * writer lock, then scl_write_wanted will be set.
+			 * Thus, the spa_config_enter_priority() is used to
+			 * ignore pending writer requests.
+			 *
+			 * The locking should be revised to remove the need
+			 * for this workaround.  If that's not workable then
+			 * it should only be applied to the zios involved in
+			 * the pruning process.  This impacts the read/write
+			 * I/O balance while pruning.
+			 */
+			if (spa->spa_active_ddt_prune)
+				spa_config_enter_priority(spa, SCL_ZIO, zio,
+				    RW_READER);
+			else
+				spa_config_enter(spa, SCL_ZIO, zio,
+				    RW_READER);
+		}
 
 		/*
 		 * The mirror_ops handle multiple DVAs in a single BP.
@@ -5305,6 +5326,16 @@ zio_ready(zio_t *zio)
 		return (NULL);
 	}
 
+	if (zio_injection_enabled) {
+		hrtime_t target = zio_handle_ready_delay(zio);
+		if (target != 0 && zio->io_target_timestamp == 0) {
+			zio->io_stage >>= 1;
+			zio->io_target_timestamp = target;
+			zio_delay_interrupt(zio);
+			return (NULL);
+		}
+	}
+
 	if (zio->io_ready) {
 		ASSERT(IO_IS_ALLOCATING(zio));
 		ASSERT(BP_GET_BIRTH(bp) == zio->io_txg ||
diff --git a/sys/contrib/openzfs/module/zfs/zio_inject.c b/sys/contrib/openzfs/module/zfs/zio_inject.c
index 981a1be4847c..287577018ed1 100644
--- a/sys/contrib/openzfs/module/zfs/zio_inject.c
+++ b/sys/contrib/openzfs/module/zfs/zio_inject.c
@@ -827,6 +827,44 @@ zio_handle_export_delay(spa_t *spa, hrtime_t elapsed)
 	zio_handle_pool_delay(spa, elapsed, ZINJECT_DELAY_EXPORT);
 }
 
+/*
+ * For testing, inject a delay before ready state.
+ */
+hrtime_t
+zio_handle_ready_delay(zio_t *zio)
+{
+	inject_handler_t *handler;
+	hrtime_t now = gethrtime();
+	hrtime_t target = 0;
+
+	/*
+	 * Ignore I/O not associated with any logical data.
+	 */
+	if (zio->io_logical == NULL)
+		return (0);
+
+	rw_enter(&inject_lock, RW_READER);
+
+	for (handler = list_head(&inject_handlers); handler != NULL;
+	    handler = list_next(&inject_handlers, handler)) {
+		if (zio->io_spa != handler->zi_spa ||
+		    handler->zi_record.zi_cmd != ZINJECT_DELAY_READY)
+			continue;
+
+		/* If this handler matches, inject the delay */
+		if (zio_match_iotype(zio, handler->zi_record.zi_iotype) &&
+		    zio_match_handler(&zio->io_logical->io_bookmark,
+		    zio->io_bp ? BP_GET_TYPE(zio->io_bp) : DMU_OT_NONE,
+		    zio_match_dva(zio), &handler->zi_record, zio->io_error)) {
+			target = now + (hrtime_t)handler->zi_record.zi_timer;
+			break;
+		}
+	}
+
+	rw_exit(&inject_lock);
+	return (target);
+}
+
 static int
 zio_calculate_range(const char *pool, zinject_record_t *record)
 {
diff --git a/sys/contrib/openzfs/module/zstd/zfs_zstd.c b/sys/contrib/openzfs/module/zstd/zfs_zstd.c
index 3db196953f74..c403c001086a 100644
--- a/sys/contrib/openzfs/module/zstd/zfs_zstd.c
+++ b/sys/contrib/openzfs/module/zstd/zfs_zstd.c
@@ -441,64 +441,6 @@ zstd_enum_to_level(enum zio_zstd_levels level, int16_t *zstd_level)
 }
 
 #ifndef IN_LIBSA
-static size_t
-zfs_zstd_compress_wrap(void *s_start, void *d_start, size_t s_len, size_t d_len,
-    int level)
-{
-	int16_t zstd_level;
-	if (zstd_enum_to_level(level, &zstd_level)) {
-		ZSTDSTAT_BUMP(zstd_stat_com_inval);
-		return (s_len);
-	}
-	/*
-	 * A zstd early abort heuristic.
-	 *
-	 * - Zeroth, if this is <= zstd-3, or < zstd_abort_size (currently
-	 *   128k), don't try any of this, just go.
-	 *   (because experimentally that was a reasonable cutoff for a perf win
-	 *   with tiny ratio change)
-	 * - First, we try LZ4 compression, and if it doesn't early abort, we
-	 *   jump directly to whatever compression level we intended to try.
-	 * - Second, we try zstd-1 - if that errors out (usually, but not
-	 *   exclusively, if it would overflow), we give up early.
-	 *
-	 *   If it works, instead we go on and compress anyway.
-	 *
-	 * Why two passes? LZ4 alone gets you a lot of the way, but on highly
-	 * compressible data, it was losing up to 8.5% of the compressed
-	 * savings versus no early abort, and all the zstd-fast levels are
-	 * worse indications on their own than LZ4, and don't improve the LZ4
-	 * pass noticably if stacked like this.
-	 */
-	size_t actual_abort_size = zstd_abort_size;
-	if (zstd_earlyabort_pass > 0 && zstd_level >= zstd_cutoff_level &&
-	    s_len >= actual_abort_size) {
-		int pass_len = 1;
-		pass_len = zfs_lz4_compress(s_start, d_start, s_len, d_len, 0);
-		if (pass_len < d_len) {
-			ZSTDSTAT_BUMP(zstd_stat_lz4pass_allowed);
-			goto keep_trying;
-		}
-		ZSTDSTAT_BUMP(zstd_stat_lz4pass_rejected);
-
-		pass_len = zfs_zstd_compress(s_start, d_start, s_len, d_len,
-		    ZIO_ZSTD_LEVEL_1);
-		if (pass_len == s_len || pass_len <= 0 || pass_len > d_len) {
-			ZSTDSTAT_BUMP(zstd_stat_zstdpass_rejected);
-			return (s_len);
-		}
-		ZSTDSTAT_BUMP(zstd_stat_zstdpass_allowed);
-	} else {
-		ZSTDSTAT_BUMP(zstd_stat_passignored);
-		if (s_len < actual_abort_size) {
-			ZSTDSTAT_BUMP(zstd_stat_passignored_size);
-		}
-	}
-keep_trying:
-	return (zfs_zstd_compress(s_start, d_start, s_len, d_len, level));
-
-}
-
 /* Compress block using zstd */
 static size_t
 zfs_zstd_compress_impl(void *s_start, void *d_start, size_t s_len, size_t d_len,
diff --git a/sys/contrib/openzfs/scripts/zfs-tests.sh b/sys/contrib/openzfs/scripts/zfs-tests.sh
index 04f3b6f32cb8..5a0a1a609448 100755
--- a/sys/contrib/openzfs/scripts/zfs-tests.sh
+++ b/sys/contrib/openzfs/scripts/zfs-tests.sh
@@ -38,6 +38,7 @@ DEBUG=""
 CLEANUP="yes"
 CLEANUPALL="no"
 KMSG=""
+TIMEOUT_DEBUG=""
 LOOPBACK="yes"
 STACK_TRACER="no"
 FILESIZE="4G"
@@ -364,6 +365,7 @@ OPTIONS:
 	-k          Disable cleanup after test failure
 	-K          Log test names to /dev/kmsg
 	-f          Use files only, disables block device tests
+	-O          Dump debugging info to /dev/kmsg on test timeout
 	-S          Enable stack tracer (negative performance impact)
 	-c          Only create and populate constrained path
 	-R          Automatically rerun failing tests
@@ -402,7 +404,7 @@ $0 -x
 EOF
 }
 
-while getopts 'hvqxkKfScRmn:d:Ds:r:?t:T:u:I:' OPTION; do
+while getopts 'hvqxkKfScRmOn:d:Ds:r:?t:T:u:I:' OPTION; do
 	case $OPTION in
 	h)
 		usage
@@ -445,6 +447,9 @@ while getopts 'hvqxkKfScRmn:d:Ds:r:?t:T:u:I:' OPTION; do
 		export NFS=1
 		. "$nfsfile"
 		;;
+	O)
+		TIMEOUT_DEBUG="yes"
+		;;
 	d)
 		FILEDIR="$OPTARG"
 		;;
@@ -773,6 +778,7 @@ msg "${TEST_RUNNER}" \
     "${DEBUG:+-D}" \
     "${KMEMLEAK:+-m}" \
     "${KMSG:+-K}" \
+    "${TIMEOUT_DEBUG:+-O}" \
     "-c \"${RUNFILES}\"" \
     "-T \"${TAGS}\"" \
     "-i \"${STF_SUITE}\"" \
@@ -783,6 +789,7 @@ msg "${TEST_RUNNER}" \
     ${DEBUG:+-D} \
     ${KMEMLEAK:+-m} \
     ${KMSG:+-K} \
+    ${TIMEOUT_DEBUG:+-O} \
     -c "${RUNFILES}" \
     -T "${TAGS}" \
     -i "${STF_SUITE}" \
diff --git a/sys/contrib/openzfs/tests/runfiles/common.run b/sys/contrib/openzfs/tests/runfiles/common.run
index 2b002830c82f..9f531411fbe1 100644
--- a/sys/contrib/openzfs/tests/runfiles/common.run
+++ b/sys/contrib/openzfs/tests/runfiles/common.run
@@ -168,10 +168,10 @@ tags = ['functional', 'cli_root', 'zinject']
 tests = ['zdb_002_pos', 'zdb_003_pos', 'zdb_004_pos', 'zdb_005_pos',
     'zdb_006_pos', 'zdb_args_neg', 'zdb_args_pos',
     'zdb_block_size_histogram', 'zdb_checksum', 'zdb_decompress',
-    'zdb_display_block', 'zdb_encrypted', 'zdb_label_checksum',
-    'zdb_object_range_neg', 'zdb_object_range_pos', 'zdb_objset_id',
-    'zdb_decompress_zstd', 'zdb_recover', 'zdb_recover_2', 'zdb_backup',
-    'zdb_tunables']
+    'zdb_display_block', 'zdb_encrypted', 'zdb_encrypted_raw',
+    'zdb_label_checksum', 'zdb_object_range_neg', 'zdb_object_range_pos',
+    'zdb_objset_id', 'zdb_decompress_zstd', 'zdb_recover', 'zdb_recover_2',
+    'zdb_backup', 'zdb_tunables']
 pre =
 post =
 tags = ['functional', 'cli_root', 'zdb']
@@ -395,8 +395,9 @@ tags = ['functional', 'cli_root', 'zpool']
 [tests/functional/cli_root/zpool_add]
 tests = ['zpool_add_001_pos', 'zpool_add_002_pos', 'zpool_add_003_pos',
     'zpool_add_004_pos', 'zpool_add_006_pos', 'zpool_add_007_neg',
-    'zpool_add_008_neg', 'zpool_add_009_neg', 'zpool_add_010_pos',
-    'add-o_ashift', 'add_prop_ashift', 'zpool_add_dryrun_output']
+    'zpool_add_008_neg', 'zpool_add_009_neg', 'zpool_add_warn_create',
+    'zpool_add_warn_degraded', 'zpool_add_warn_removal', 'add-o_ashift',
+    'add_prop_ashift', 'zpool_add_dryrun_output']
 tags = ['functional', 'cli_root', 'zpool_add']
 
 [tests/functional/cli_root/zpool_attach]
@@ -490,6 +491,10 @@ tests = ['zpool_import_001_pos', 'zpool_import_002_pos',
 tags = ['functional', 'cli_root', 'zpool_import']
 timeout = 1200
 
+[tests/functional/cli_root/zpool_iostat]
+tests = ['zpool_iostat_interval_all', 'zpool_iostat_interval_some']
+tags = ['functional', 'cli_root', 'zpool_iostat']
+
 [tests/functional/cli_root/zpool_labelclear]
 tests = ['zpool_labelclear_active', 'zpool_labelclear_exported',
     'zpool_labelclear_removed', 'zpool_labelclear_valid']
@@ -1085,7 +1090,8 @@ tags = ['functional', 'write_dirs']
 [tests/functional/xattr]
 tests = ['xattr_001_pos', 'xattr_002_neg', 'xattr_003_neg', 'xattr_004_pos',
     'xattr_005_pos', 'xattr_006_pos', 'xattr_007_neg',
-    'xattr_011_pos', 'xattr_012_pos', 'xattr_013_pos', 'xattr_compat']
+    'xattr_011_pos', 'xattr_012_pos', 'xattr_013_pos', 'xattr_014_pos',
+    'xattr_compat']
 tags = ['functional', 'xattr']
 
 [tests/functional/zvol/zvol_ENOSPC]
diff --git a/sys/contrib/openzfs/tests/runfiles/sanity.run b/sys/contrib/openzfs/tests/runfiles/sanity.run
index b56ffc3a4a2d..249b415029c4 100644
--- a/sys/contrib/openzfs/tests/runfiles/sanity.run
+++ b/sys/contrib/openzfs/tests/runfiles/sanity.run
@@ -622,7 +622,7 @@ tags = ['functional', 'vdev_zaps']
 [tests/functional/xattr]
 tests = ['xattr_001_pos', 'xattr_002_neg', 'xattr_003_neg', 'xattr_004_pos',
     'xattr_005_pos', 'xattr_006_pos', 'xattr_007_neg',
-    'xattr_011_pos', 'xattr_013_pos', 'xattr_compat']
+    'xattr_011_pos', 'xattr_013_pos', 'xattr_014_pos', 'xattr_compat']
 tags = ['functional', 'xattr']
 
 [tests/functional/zvol/zvol_ENOSPC]
diff --git a/sys/contrib/openzfs/tests/test-runner/bin/test-runner.py.in b/sys/contrib/openzfs/tests/test-runner/bin/test-runner.py.in
index 2158208be6e5..d2c1185e4a94 100755
--- a/sys/contrib/openzfs/tests/test-runner/bin/test-runner.py.in
+++ b/sys/contrib/openzfs/tests/test-runner/bin/test-runner.py.in
@@ -34,6 +34,7 @@ from select import select
 from subprocess import PIPE
 from subprocess import Popen
 from subprocess import check_output
+from subprocess import run
 from threading import Timer
 from time import time, CLOCK_MONOTONIC
 from os.path import exists
@@ -187,6 +188,63 @@ User: %s
 ''' % (self.pathname, self.identifier, self.outputdir, self.timeout, self.user)
 
     def kill_cmd(self, proc, options, kmemleak, keyboard_interrupt=False):
+
+        """
+        We're about to kill a command due to a timeout.
+        If we're running with the -O option, then dump debug info about the
+        process with the highest CPU usage to /dev/kmsg (Linux only).  This can
+        help debug the timeout.
+
+        Debug info includes:
+        - 30 lines from 'top'
+        - /proc/<PID>/stack output of process with highest CPU usage
+        - Last lines strace-ing process with highest CPU usage
+        """
+        if exists("/dev/kmsg"):
+            c = """
+TOP_OUT="$(COLUMNS=160 top -b -n 1 | head -n 30)"
+read -r PID CMD <<< $(echo "$TOP_OUT" | /usr/bin/awk \
+"/COMMAND/{
+    print_next=1
+    next
+}
+{
+    if (print_next == 1) {
+        print \\$1\\" \\"\\$12
+        exit
+    }
+}")
+echo "##### ZTS timeout debug #####"
+echo "----- top -----"
+echo "$TOP_OUT"
+echo "----- /proc/$PID/stack ($CMD)) -----"
+cat /proc/$PID/stack
+echo "----- strace ($CMD) -----"
+TMPFILE="$(mktemp --suffix=ZTS)"
+/usr/bin/strace -k --stack-traces -p $PID &> "$TMPFILE" &
+sleep 0.1
+killall strace
+tail -n 30 $TMPFILE
+rm "$TMPFILE"
+echo "##### /proc/sysrq-trigger stack #####"
+"""
+            c = "sudo bash -c '" + c + "'"
+            data = run(c, capture_output=True, shell=True, text=True)
+            out = data.stdout
+            try:
+                kp = Popen([SUDO, "sh", "-c",
+                            "echo '" + out + "' > /dev/kmsg"])
+                kp.wait()
+
+                """
+                Trigger kernel stack traces
+                """
+                kp = Popen([SUDO, "sh", "-c",
+                            "echo l > /proc/sysrq-trigger"])
+                kp.wait()
+            except Exception:
+                pass
+
         """
         Kill a running command due to timeout, or ^C from the keyboard. If
         sudo is required, this user was verified previously.
@@ -1129,6 +1187,9 @@ def parse_args():
     parser.add_option('-o', action='callback', callback=options_cb,
                       default=BASEDIR, dest='outputdir', type='string',
                       metavar='outputdir', help='Specify an output directory.')
+    parser.add_option('-O', action='store_true', default=False,
+                      dest='timeout_debug',
+                      help='Dump debugging info to /dev/kmsg on test timeout')
     parser.add_option('-i', action='callback', callback=options_cb,
                       default=TESTDIR, dest='testdir', type='string',
                       metavar='testdir', help='Specify a test directory.')
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/Makefile.am b/sys/contrib/openzfs/tests/zfs-tests/tests/Makefile.am
index 1517f90e99a5..678c01b58f94 100644
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/Makefile.am
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/Makefile.am
@@ -197,6 +197,7 @@ nobase_dist_datadir_zfs_tests_tests_DATA += \
 	functional/cli_root/zpool_import/blockfiles/unclean_export.dat.bz2 \
 	functional/cli_root/zpool_import/zpool_import.cfg \
 	functional/cli_root/zpool_import/zpool_import.kshlib \
+	functional/cli_root/zpool_iostat/zpool_iostat.kshlib \
 	functional/cli_root/zpool_initialize/zpool_initialize.kshlib \
 	functional/cli_root/zpool_labelclear/labelclear.cfg \
 	functional/cli_root/zpool_remove/zpool_remove.cfg \
@@ -640,6 +641,7 @@ nobase_dist_datadir_zfs_tests_tests_SCRIPTS += \
 	functional/cli_root/zdb/zdb_decompress_zstd.ksh \
 	functional/cli_root/zdb/zdb_display_block.ksh \
 	functional/cli_root/zdb/zdb_encrypted.ksh \
+	functional/cli_root/zdb/zdb_encrypted_raw.ksh \
 	functional/cli_root/zdb/zdb_label_checksum.ksh \
 	functional/cli_root/zdb/zdb_object_range_neg.ksh \
 	functional/cli_root/zdb/zdb_object_range_pos.ksh \
@@ -1027,7 +1029,9 @@ nobase_dist_datadir_zfs_tests_tests_SCRIPTS += \
 	functional/cli_root/zpool_add/zpool_add_007_neg.ksh \
 	functional/cli_root/zpool_add/zpool_add_008_neg.ksh \
 	functional/cli_root/zpool_add/zpool_add_009_neg.ksh \
-	functional/cli_root/zpool_add/zpool_add_010_pos.ksh \
+	functional/cli_root/zpool_add/zpool_add_warn_create.ksh \
+	functional/cli_root/zpool_add/zpool_add_warn_degraded.ksh \
+	functional/cli_root/zpool_add/zpool_add_warn_removal.ksh \
 	functional/cli_root/zpool_add/zpool_add_dryrun_output.ksh \
 	functional/cli_root/zpool_attach/attach-o_ashift.ksh \
 	functional/cli_root/zpool_attach/cleanup.ksh \
@@ -1178,6 +1182,10 @@ nobase_dist_datadir_zfs_tests_tests_SCRIPTS += \
 	functional/cli_root/zpool_import/zpool_import_parallel_admin.ksh \
 	functional/cli_root/zpool_import/zpool_import_parallel_neg.ksh \
 	functional/cli_root/zpool_import/zpool_import_parallel_pos.ksh \
+	functional/cli_root/zpool_iostat/setup.ksh \
+	functional/cli_root/zpool_iostat/cleanup.ksh \
+	functional/cli_root/zpool_iostat/zpool_iostat_interval_all.ksh \
+	functional/cli_root/zpool_iostat/zpool_iostat_interval_some.ksh \
 	functional/cli_root/zpool_initialize/cleanup.ksh \
 	functional/cli_root/zpool_initialize/zpool_initialize_attach_detach_add_remove.ksh \
 	functional/cli_root/zpool_initialize/zpool_initialize_fault_export_import_online.ksh \
@@ -2226,6 +2234,7 @@ nobase_dist_datadir_zfs_tests_tests_SCRIPTS += \
 	functional/xattr/xattr_011_pos.ksh \
 	functional/xattr/xattr_012_pos.ksh \
 	functional/xattr/xattr_013_pos.ksh \
+	functional/xattr/xattr_014_pos.ksh \
 	functional/xattr/xattr_compat.ksh \
 	functional/zap_shrink/cleanup.ksh \
 	functional/zap_shrink/zap_shrink_001_pos.ksh \
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zdb/zdb_encrypted_raw.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zdb/zdb_encrypted_raw.ksh
new file mode 100755
index 000000000000..85d267d5402f
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zdb/zdb_encrypted_raw.ksh
@@ -0,0 +1,75 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# This file and its contents are supplied under the terms of the
+# Common Development and Distribution License ("CDDL"), version 1.0.
+# You may only use this file in accordance with the terms of version
+# 1.0 of the CDDL.
+#
+# A full copy of the text of the CDDL should have accompanied this
+# source.  A copy of the CDDL is also available via the Internet at
+# http://www.illumos.org/license/CDDL.
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2023, Klara Inc.
+#
+
+. $STF_SUITE/include/libtest.shlib
+. $STF_SUITE/tests/functional/cli_root/zfs_load-key/zfs_load-key_common.kshlib
+
+#
+# DESCRIPTION:
+# 'zdb -K ...' should enable reading from a raw-encrypted dataset
+#
+# STRATEGY:
+# 1. Create an encrypted dataset
+# 2. Write some data to a file
+# 3. Run zdb -dddd on the file, confirm it can't be read
+# 4. Run zdb -K ... -ddddd on the file, confirm it can be read
+#
+
+verify_runnable "both"
+
+dataset="$TESTPOOL/$TESTFS2"
+file="$TESTDIR2/somefile"
+keyfile="$TEST_BASE_DIR/keyfile"
+
+function cleanup
+{
+	datasetexists "$dataset" && destroy_dataset "$dataset" -f
+	rm -f "$keyfile"
+	default_cleanup_noexit
+}
+
+log_onexit cleanup
+
+log_must default_setup_noexit $DISKS
+
+log_assert "'zdb -K' should enable reading from a raw-encrypted dataset"
+
+# The key must be 32 bytes long.
+echo -n "$RAWKEY" > "$keyfile"
+
+log_must zfs create -o mountpoint="$TESTDIR2" \
+    -o encryption=on -o keyformat=raw -o keylocation="file://$keyfile" \
+    "$dataset"
+
+echo 'my great encrypted text' > "$file"
+
+typeset -i obj=$(ls -i "$file" | cut -d' ' -f1)
+typeset -i size=$(wc -c < "$file")
+
+log_note "test file $file is objid $obj, size $size"
+
+sync_pool "$TESTPOOL" true
+
+log_must eval "zdb -dddd $dataset $obj | grep -q 'object encrypted'"
+
+log_must eval "zdb -K $keyfile -dddd $dataset $obj | grep -q 'size\s$size$'"
+
+log_pass "'zdb -K' enables reading from a raw-encrypted dataset"
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add.kshlib b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add.kshlib
index 091d65bb4f33..74780bb02141 100644
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add.kshlib
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add.kshlib
@@ -27,6 +27,7 @@
 
 #
 # Copyright (c) 2012, 2016 by Delphix. All rights reserved.
+# Copyright 2025 by Lawrence Livermore National Security, LLC.
 #
 
 . $STF_SUITE/include/libtest.shlib
@@ -89,3 +90,44 @@ function save_dump_dev
 	fi
 	echo $dumpdev
 }
+
+function zpool_create_add_setup
+{
+	typeset -i i=0
+
+	while ((i < 10)); do
+		log_must truncate -s $MINVDEVSIZE $TEST_BASE_DIR/vdev$i
+
+		eval vdev$i=$TEST_BASE_DIR/vdev$i
+		((i += 1))
+	done
+
+	if is_linux; then
+	        vdev_lo="$(losetup -f "$vdev4" --show)"
+	elif is_freebsd; then
+	        vdev_lo=/dev/"$(mdconfig -a -t vnode -f "$vdev4")"
+	else
+	        vdev_lo="$(lofiadm -a "$vdev4")"
+	fi
+}
+
+function zpool_create_add_cleanup
+{
+	datasetexists $TESTPOOL1 && destroy_pool $TESTPOOL1
+
+	if [[ -e $vdev_lo ]]; then
+		if is_linux; then
+			log_must losetup -d "$vdev_lo"
+		elif is_freebsd; then
+			log_must mdconfig -d -u "$vdev_lo"
+		else
+			log_must lofiadm -d "$vdev_lo"
+		fi
+	fi
+
+	typeset -i i=0
+	while ((i < 10)); do
+		rm -f $TEST_BASE_DIR/vdev$i
+		((i += 1))
+	done
+}
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_010_pos.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_create.ksh
index df085a2ec746..661e55998d8d 100755
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_010_pos.ksh
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_create.ksh
@@ -23,67 +23,51 @@
 
 #
 # Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
-# Use is subject to license terms.
-#
-
-#
-# Copyright (c) 2012, 2016 by Delphix. All rights reserved.
+# Copyright 2012, 2016 by Delphix. All rights reserved.
+# Copyright 2025 by Lawrence Livermore National Security, LLC.
 #
 
 . $STF_SUITE/include/libtest.shlib
-. $STF_SUITE/tests/functional/cli_root/zpool_create/zpool_create.shlib
+. $STF_SUITE/tests/functional/cli_root/zpool_add/zpool_add.kshlib
 
 #
 # DESCRIPTION:
-#	Verify zpool add succeed when adding vdevs with matching redundancy.
+#	Verify zpool add succeeds when adding vdevs with matching redundancy
+#	and warns with differing redundancy for a healthy pool.
 #
 # STRATEGY:
 #	1. Create several files == $MINVDEVSIZE.
 #	2. Verify 'zpool add' succeeds with matching redundancy.
 #	3. Verify 'zpool add' warns with differing redundancy.
-#	4. Verify 'zpool add' warns with differing redundancy after removal.
 #
 
 verify_runnable "global"
 
-function cleanup
-{
-	datasetexists $TESTPOOL1 && destroy_pool $TESTPOOL1
-
-	typeset -i i=0
-	while ((i < 10)); do
-		rm -f $TEST_BASE_DIR/vdev$i
-		((i += 1))
-	done
-}
-
+log_assert "Verify 'zpool add' warns for differing redundancy."
+log_onexit zpool_create_add_cleanup
 
-log_assert "Verify 'zpool add' succeed with keywords combination."
-log_onexit cleanup
+zpool_create_add_setup
 
-# 1. Create several files == $MINVDEVSIZE.
 typeset -i i=0
-while ((i < 10)); do
-	log_must truncate -s $MINVDEVSIZE $TEST_BASE_DIR/vdev$i
-
-	eval vdev$i=$TEST_BASE_DIR/vdev$i
-	((i += 1))
-done
+typeset -i j=0
 
 set -A redundancy0_create_args \
 	"$vdev0"
 
 set -A redundancy1_create_args \
 	"mirror $vdev0 $vdev1" \
-	"raidz1 $vdev0 $vdev1"
+	"raidz1 $vdev0 $vdev1" \
+	"draid1:1s $vdev0 $vdev1 $vdev9"
 
 set -A redundancy2_create_args \
 	"mirror $vdev0 $vdev1 $vdev2" \
-	"raidz2 $vdev0 $vdev1 $vdev2"
+	"raidz2 $vdev0 $vdev1 $vdev2" \
+	"draid2:1s $vdev0 $vdev1 $vdev2 $vdev9"
 
 set -A redundancy3_create_args \
 	"mirror $vdev0 $vdev1 $vdev2 $vdev3" \
-	"raidz3 $vdev0 $vdev1 $vdev2 $vdev3"
+	"raidz3 $vdev0 $vdev1 $vdev2 $vdev3" \
+	"draid3:1s $vdev0 $vdev1 $vdev2 $vdev3 $vdev9"
 
 set -A redundancy0_add_args \
 	"$vdev5" \
@@ -93,21 +77,19 @@ set -A redundancy1_add_args \
 	"mirror $vdev5 $vdev6" \
 	"raidz1 $vdev5 $vdev6" \
 	"raidz1 $vdev5 $vdev6 mirror $vdev7 $vdev8" \
-	"mirror $vdev5 $vdev6 raidz1 $vdev7 $vdev8"
+	"mirror $vdev5 $vdev6 raidz1 $vdev7 $vdev8" \
+	"draid1 $vdev5 $vdev6 mirror $vdev7 $vdev8" \
+	"mirror $vdev5 $vdev6 draid1 $vdev7 $vdev8"
 
 set -A redundancy2_add_args \
 	"mirror $vdev5 $vdev6 $vdev7" \
-	"raidz2 $vdev5 $vdev6 $vdev7"
+	"raidz2 $vdev5 $vdev6 $vdev7" \
+	"draid2 $vdev5 $vdev6 $vdev7"
 
 set -A redundancy3_add_args \
 	"mirror $vdev5 $vdev6 $vdev7 $vdev8" \
-	"raidz3 $vdev5 $vdev6 $vdev7 $vdev8"
-
-set -A log_args "log" "$vdev4"
-set -A cache_args "cache" "$vdev4"
-set -A spare_args "spare" "$vdev4"
-
-typeset -i j=0
+	"raidz3 $vdev5 $vdev6 $vdev7 $vdev8" \
+	"draid3 $vdev5 $vdev6 $vdev7 $vdev8"
 
 function zpool_create_add
 {
@@ -148,30 +130,6 @@ function zpool_create_forced_add
 	done
 }
 
-function zpool_create_rm_add
-{
-	typeset -n create_args=$1
-	typeset -n add_args=$2
-	typeset -n rm_args=$3
-
-	i=0
-	while ((i < ${#create_args[@]})); do
-		j=0
-		while ((j < ${#add_args[@]})); do
-			log_must zpool create $TESTPOOL1 ${create_args[$i]}
-			log_must zpool add $TESTPOOL1 ${rm_args[0]} ${rm_args[1]}
-			log_must zpool add $TESTPOOL1 ${add_args[$j]}
-			log_must zpool remove $TESTPOOL1 ${rm_args[1]}
-			log_mustnot zpool add $TESTPOOL1 ${rm_args[1]}
-			log_must zpool add $TESTPOOL1 ${rm_args[0]} ${rm_args[1]}
-			log_must zpool destroy -f $TESTPOOL1
-
-			((j += 1))
-		done
-		((i += 1))
-	done
-}
-
 # 2. Verify 'zpool add' succeeds with matching redundancy.
 zpool_create_add redundancy0_create_args redundancy0_add_args
 zpool_create_add redundancy1_create_args redundancy1_add_args
@@ -195,17 +153,4 @@ zpool_create_forced_add redundancy3_create_args redundancy0_add_args
 zpool_create_forced_add redundancy3_create_args redundancy1_add_args
 zpool_create_forced_add redundancy3_create_args redundancy2_add_args
 
-# 4. Verify 'zpool add' warns with differing redundancy after removal.
-zpool_create_rm_add redundancy1_create_args redundancy1_add_args log_args
-zpool_create_rm_add redundancy2_create_args redundancy2_add_args log_args
-zpool_create_rm_add redundancy3_create_args redundancy3_add_args log_args
-
-zpool_create_rm_add redundancy1_create_args redundancy1_add_args cache_args
-zpool_create_rm_add redundancy2_create_args redundancy2_add_args cache_args
-zpool_create_rm_add redundancy3_create_args redundancy3_add_args cache_args
-
-zpool_create_rm_add redundancy1_create_args redundancy1_add_args spare_args
-zpool_create_rm_add redundancy2_create_args redundancy2_add_args spare_args
-zpool_create_rm_add redundancy3_create_args redundancy3_add_args spare_args
-
-log_pass "'zpool add' succeed with keywords combination."
+log_pass "Verify 'zpool add' warns for differing redundancy."
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_degraded.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_degraded.ksh
new file mode 100755
index 000000000000..313eb3666f27
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_degraded.ksh
@@ -0,0 +1,204 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
+# Copyright 2012, 2016 by Delphix. All rights reserved.
+# Copyright 2025 by Lawrence Livermore National Security, LLC.
+#
+
+. $STF_SUITE/include/libtest.shlib
+. $STF_SUITE/tests/functional/cli_root/zpool_add/zpool_add.kshlib
+
+#
+# DESCRIPTION:
+#	Verify zpool add succeeds when adding vdevs with matching redundancy
+#	and warns with differing redundancy for a degraded pool.
+#
+# STRATEGY:
+#	1. Create several files == $MINVDEVSIZE.
+#	2. Verify 'zpool add' succeeds with matching redundancy
+#	3. Verify 'zpool add' warns with differing redundancy when
+#	  a. Degraded pool with replaced mismatch vdev (file vs disk)
+#	  b. Degraded pool dRAID distributed spare active
+#	  c. Degraded pool hot spare active
+#
+
+verify_runnable "global"
+
+log_assert "Verify 'zpool add' warns for differing redundancy."
+log_onexit zpool_create_add_cleanup
+
+zpool_create_add_setup
+
+set -A redundancy1_create_args \
+	"mirror $vdev0 $vdev1" \
+	"raidz1 $vdev0 $vdev1" \
+	"draid1:1s $vdev0 $vdev1 $vdev9"
+
+set -A redundancy2_create_args \
+	"mirror $vdev0 $vdev1 $vdev2" \
+	"raidz2 $vdev0 $vdev1 $vdev2" \
+	"draid2:1s $vdev0 $vdev1 $vdev2 $vdev9"
+
+set -A redundancy3_create_args \
+	"mirror $vdev0 $vdev1 $vdev2 $vdev3" \
+	"raidz3 $vdev0 $vdev1 $vdev2 $vdev3" \
+	"draid3:1s $vdev0 $vdev1 $vdev2 $vdev3 $vdev9"
+
+set -A redundancy1_add_args \
+	"mirror $vdev5 $vdev6" \
+	"raidz1 $vdev5 $vdev6" \
+	"raidz1 $vdev5 $vdev6 mirror $vdev7 $vdev8" \
+	"mirror $vdev5 $vdev6 raidz1 $vdev7 $vdev8" \
+	"draid1 $vdev5 $vdev6 mirror $vdev7 $vdev8" \
+	"mirror $vdev5 $vdev6 draid1 $vdev7 $vdev8"
+
+set -A redundancy2_add_args \
+	"mirror $vdev5 $vdev6 $vdev7" \
+	"raidz2 $vdev5 $vdev6 $vdev7" \
+	"draid2 $vdev5 $vdev6 $vdev7"
+
+set -A redundancy3_add_args \
+	"mirror $vdev5 $vdev6 $vdev7 $vdev8" \
+	"raidz3 $vdev5 $vdev6 $vdev7 $vdev8" \
+	"draid3 $vdev5 $vdev6 $vdev7 $vdev8"
+
+set -A redundancy1_create_draid_args \
+	"draid1:1s $vdev0 $vdev1 $vdev2"
+
+set -A redundancy2_create_draid_args \
+	"draid2:1s $vdev0 $vdev1 $vdev2 $vdev3"
+
+set -A redundancy3_create_draid_args \
+	"draid3:1s $vdev0 $vdev1 $vdev2 $vdev3 $vdev9"
+
+set -A redundancy1_create_spare_args \
+	"mirror $vdev0 $vdev1 spare $vdev_lo" \
+	"raidz1 $vdev0 $vdev1 spare $vdev_lo" \
+	"draid1 $vdev0 $vdev1 spare $vdev_lo"
+
+set -A redundancy2_create_spare_args \
+	"mirror $vdev0 $vdev1 $vdev2 spare $vdev_lo" \
+	"raidz2 $vdev0 $vdev1 $vdev2 spare $vdev_lo" \
+	"draid2 $vdev0 $vdev1 $vdev2 spare $vdev_lo"
+
+set -A redundancy3_create_spare_args \
+	"mirror $vdev0 $vdev1 $vdev2 $vdev3 spare $vdev_lo" \
+	"raidz3 $vdev0 $vdev1 $vdev2 $vdev3 spare $vdev_lo" \
+	"draid3 $vdev0 $vdev1 $vdev2 $vdev3 spare $vdev_lo"
+
+set -A replace_args "$vdev1" "$vdev_lo"
+set -A draid1_args "$vdev1" "draid1-0-0"
+set -A draid2_args "$vdev1" "draid2-0-0"
+set -A draid3_args "$vdev1" "draid3-0-0"
+
+typeset -i i=0
+typeset -i j=0
+
+function zpool_create_degraded_add
+{
+	typeset -n create_args=$1
+	typeset -n add_args=$2
+	typeset -n rm_args=$3
+
+	i=0
+	while ((i < ${#create_args[@]})); do
+		j=0
+		while ((j < ${#add_args[@]})); do
+			log_must zpool create $TESTPOOL1 ${create_args[$i]}
+			log_must zpool offline -f $TESTPOOL1 ${rm_args[0]}
+			log_must zpool replace -w $TESTPOOL1 ${rm_args[0]} ${rm_args[1]}
+			log_must zpool add $TESTPOOL1 ${add_args[$j]}
+			log_must zpool destroy -f $TESTPOOL1
+			log_must zpool labelclear -f ${rm_args[0]}
+
+			((j += 1))
+		done
+		((i += 1))
+	done
+}
+
+function zpool_create_forced_degraded_add
+{
+	typeset -n create_args=$1
+	typeset -n add_args=$2
+	typeset -n rm_args=$3
+
+	i=0
+	while ((i < ${#create_args[@]})); do
+		j=0
+		while ((j < ${#add_args[@]})); do
+			log_must zpool create $TESTPOOL1 ${create_args[$i]}
+			log_must zpool offline -f $TESTPOOL1 ${rm_args[0]}
+			log_must zpool replace -w $TESTPOOL1 ${rm_args[0]} ${rm_args[1]}
+			log_mustnot zpool add $TESTPOOL1 ${add_args[$j]}
+			log_must zpool add --allow-replication-mismatch $TESTPOOL1 ${add_args[$j]}
+			log_must zpool destroy -f $TESTPOOL1
+			log_must zpool labelclear -f ${rm_args[0]}
+
+			((j += 1))
+		done
+		((i += 1))
+	done
+}
+
+# 2. Verify 'zpool add' succeeds with matching redundancy and a degraded pool.
+zpool_create_degraded_add redundancy1_create_args redundancy1_add_args replace_args
+zpool_create_degraded_add redundancy2_create_args redundancy2_add_args replace_args
+zpool_create_degraded_add redundancy3_create_args redundancy3_add_args replace_args
+
+# 3. Verify 'zpool add' warns with differing redundancy and a degraded pool.
+#
+# a. Degraded pool with replaced mismatch vdev (file vs disk)
+zpool_create_forced_degraded_add redundancy1_create_args redundancy2_add_args replace_args
+zpool_create_forced_degraded_add redundancy1_create_args redundancy3_add_args replace_args
+
+zpool_create_forced_degraded_add redundancy2_create_args redundancy1_add_args replace_args
+zpool_create_forced_degraded_add redundancy2_create_args redundancy3_add_args replace_args
+
+zpool_create_forced_degraded_add redundancy3_create_args redundancy1_add_args replace_args
+zpool_create_forced_degraded_add redundancy3_create_args redundancy2_add_args replace_args
+
+# b. Degraded pool dRAID distributed spare active
+
+zpool_create_forced_degraded_add redundancy1_create_draid_args redundancy2_add_args draid1_args
+zpool_create_forced_degraded_add redundancy1_create_draid_args redundancy3_add_args draid1_args
+
+zpool_create_forced_degraded_add redundancy2_create_draid_args redundancy1_add_args draid2_args
+zpool_create_forced_degraded_add redundancy2_create_draid_args redundancy3_add_args draid2_args
+
+zpool_create_forced_degraded_add redundancy3_create_draid_args redundancy1_add_args draid3_args
+zpool_create_forced_degraded_add redundancy3_create_draid_args redundancy2_add_args draid3_args
+
+# c. Degraded pool hot spare active
+zpool_create_forced_degraded_add redundancy1_create_spare_args redundancy2_add_args replace_args
+zpool_create_forced_degraded_add redundancy1_create_spare_args redundancy3_add_args replace_args
+
+zpool_create_forced_degraded_add redundancy2_create_spare_args redundancy1_add_args replace_args
+zpool_create_forced_degraded_add redundancy2_create_spare_args redundancy3_add_args replace_args
+
+zpool_create_forced_degraded_add redundancy3_create_spare_args redundancy1_add_args replace_args
+zpool_create_forced_degraded_add redundancy3_create_spare_args redundancy2_add_args replace_args
+
+log_pass "Verify 'zpool add' warns for differing redundancy."
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_removal.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_removal.ksh
new file mode 100755
index 000000000000..782858e301ac
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_add/zpool_add_warn_removal.ksh
@@ -0,0 +1,126 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
+# Copyright 2012, 2016 by Delphix. All rights reserved.
+# Copyright 2025 by Lawrence Livermore National Security, LLC.
+#
+
+. $STF_SUITE/include/libtest.shlib
+. $STF_SUITE/tests/functional/cli_root/zpool_add/zpool_add.kshlib
+
+#
+# DESCRIPTION:
+#	Verify zpool add succeeds when adding vdevs with matching redundancy
+#	and warns with differing redundancy after removal.
+#
+# STRATEGY:
+#	1. Create several files == $MINVDEVSIZE.
+#	2. Verify 'zpool add' warns with differing redundancy after removal.
+#
+
+verify_runnable "global"
+
+log_assert "Verify 'zpool add' warns for differing redundancy."
+log_onexit zpool_create_add_cleanup
+
+zpool_create_add_setup
+
+typeset -i i=0
+typeset -i j=0
+
+set -A redundancy1_create_args \
+	"mirror $vdev0 $vdev1" \
+	"raidz1 $vdev0 $vdev1" \
+	"draid1:1s $vdev0 $vdev1 $vdev9"
+
+set -A redundancy2_create_args \
+	"mirror $vdev0 $vdev1 $vdev2" \
+	"raidz2 $vdev0 $vdev1 $vdev2" \
+	"draid2:1s $vdev0 $vdev1 $vdev2 $vdev9"
+
+set -A redundancy3_create_args \
+	"mirror $vdev0 $vdev1 $vdev2 $vdev3" \
+	"raidz3 $vdev0 $vdev1 $vdev2 $vdev3" \
+	"draid3:1s $vdev0 $vdev1 $vdev2 $vdev3 $vdev9"
+
+set -A redundancy1_add_args \
+	"mirror $vdev5 $vdev6" \
+	"raidz1 $vdev5 $vdev6" \
+	"raidz1 $vdev5 $vdev6 mirror $vdev7 $vdev8" \
+	"mirror $vdev5 $vdev6 raidz1 $vdev7 $vdev8" \
+	"draid1 $vdev5 $vdev6 mirror $vdev7 $vdev8" \
+	"mirror $vdev5 $vdev6 draid1 $vdev7 $vdev8"
+
+set -A redundancy2_add_args \
+	"mirror $vdev5 $vdev6 $vdev7" \
+	"raidz2 $vdev5 $vdev6 $vdev7" \
+	"draid2 $vdev5 $vdev6 $vdev7"
+
+set -A redundancy3_add_args \
+	"mirror $vdev5 $vdev6 $vdev7 $vdev8" \
+	"raidz3 $vdev5 $vdev6 $vdev7 $vdev8" \
+	"draid3 $vdev5 $vdev6 $vdev7 $vdev8"
+
+set -A log_args "log" "$vdev_lo"
+set -A cache_args "cache" "$vdev_lo"
+set -A spare_args "spare" "$vdev_lo"
+
+
+function zpool_create_rm_add
+{
+	typeset -n create_args=$1
+	typeset -n add_args=$2
+	typeset -n rm_args=$3
+
+	i=0
+	while ((i < ${#create_args[@]})); do
+		j=0
+		while ((j < ${#add_args[@]})); do
+			log_must zpool create $TESTPOOL1 ${create_args[$i]}
+			log_must zpool add $TESTPOOL1 ${rm_args[0]} ${rm_args[1]}
+			log_must zpool add $TESTPOOL1 ${add_args[$j]}
+			log_must zpool remove $TESTPOOL1 ${rm_args[1]}
+			log_mustnot zpool add $TESTPOOL1 ${rm_args[1]}
+			log_must zpool add $TESTPOOL1 ${rm_args[0]} ${rm_args[1]}
+			log_must zpool destroy -f $TESTPOOL1
+
+			((j += 1))
+		done
+		((i += 1))
+	done
+}
+
+# 2. Verify 'zpool add' warns with differing redundancy after removal.
+zpool_create_rm_add redundancy1_create_args redundancy1_add_args log_args
+zpool_create_rm_add redundancy2_create_args redundancy2_add_args log_args
+zpool_create_rm_add redundancy3_create_args redundancy3_add_args log_args
+
+zpool_create_rm_add redundancy1_create_args redundancy1_add_args cache_args
+zpool_create_rm_add redundancy2_create_args redundancy2_add_args cache_args
+zpool_create_rm_add redundancy3_create_args redundancy3_add_args cache_args
+
+zpool_create_rm_add redundancy1_create_args redundancy1_add_args spare_args
+zpool_create_rm_add redundancy2_create_args redundancy2_add_args spare_args
+zpool_create_rm_add redundancy3_create_args redundancy3_add_args spare_args
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/cleanup.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/cleanup.ksh
new file mode 100755
index 000000000000..099b5426031d
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/cleanup.ksh
@@ -0,0 +1,30 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2025, Klara, Inc.
+#
+#
+. $STF_SUITE/include/libtest.shlib
+
+log_pass
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/setup.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/setup.ksh
new file mode 100755
index 000000000000..3529a0ccc015
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/setup.ksh
@@ -0,0 +1,32 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2025, Klara, Inc.
+#
+#
+. $STF_SUITE/include/libtest.shlib
+
+verify_runnable "global"
+
+log_pass
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat.kshlib b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat.kshlib
new file mode 100644
index 000000000000..ea4b0bd2756d
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat.kshlib
@@ -0,0 +1,235 @@
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2025, Klara, Inc.
+#
+
+# Since we want to make sure that iostat responds correctly as pools appear and
+# disappear, we run it in the background and capture its output to a file.
+# Once we're done, we parse the output and ensure it matches what we'd expect
+# from the operations we performed.
+#
+# Because iostat is producing output every interval, it may produce the "same"
+# output for each step of the change; in fact, we want that to make sure we
+# don't miss anything. So, we describe what we expect as a series of "chunks".
+# Each chunk is a particular kind of output, which may repeat. Current known
+# chunk types are:
+#
+# NOPOOL: the text "no pools available"
+# HEADER: three lines, starting with "capacity", "pool" and "----" respectively.
+#         (the rough shape of the normal iostat header).
+# POOL1: a line starting with "pool1" (stats line for a pool of that name)
+# POOL2: a line starting with "pool2"
+# POOLBOTH: three lines, starting with "pool1", "pool2" (either order) and
+#           "-----" respectively. (the pool stat output for multiple pools)
+#
+# (the parser may produce other chunks in a failed parse to assist with
+#  debugging, but they should never be part of the "wanted" output See the
+#  parser commentary below).
+#
+# To help recognise the start of a new interval output, we run iostat with the
+# -T u option, which will output a numeric timestamp before each header or
+# second-or-later pool stat after the header.
+#
+# To keep the test run shorter, we use a subsecond interval, but to make sure
+# nothing is missed, we sleep for three intervals after each change.
+
+typeset _iostat_out=$(mktemp)
+typeset _iostat_pid=""
+
+function cleanup_iostat {
+	if [[ -n $_iostat_pid ]] ; then
+		kill -KILL $_iostat_pid || true
+	fi
+	rm -f $_iostat_out
+}
+
+function start_iostat {
+	zpool iostat -T u $@ 0.1 > $_iostat_out 2>&1 &
+	_iostat_pid=$!
+}
+
+function stop_iostat {
+	kill -TERM $_iostat_pid
+	wait $_iostat_pid
+	_iostat_pid=""
+}
+
+function delay_iostat {
+	sleep 0.3
+}
+
+typeset -a _iostat_expect
+function expect_iostat {
+	typeset chunk=$1
+	_iostat_expect+=($chunk)
+}
+
+# Parse the output The `state` var is used to track state across
+# multiple lines. The `last` var and the `_got_iostat` function are used
+# to record the completed chunks, and to collapse repetitions.
+typeset -a _iostat_got
+typeset _iostat_last=""
+typeset _iostat_state=""
+
+function _got_iostat {
+	typeset chunk=$1
+	if [[ -n $chunk && $_iostat_last != $chunk ]] ; then
+		_iostat_last=$chunk
+		_iostat_got+=($chunk)
+	fi
+	_iostat_state=""
+}
+
+function verify_iostat {
+
+	cat $_iostat_out | while read line ; do
+
+		# The "no pools available" text has no timestamp or other
+		# header, and should never appear in the middle of multiline
+		# chunk, so we can close any in-flight state.
+		if [[ $line = "no pools available" ]] ; then
+			_got_iostat $_iostat_state
+			_got_iostat "NOPOOL"
+			continue
+		fi
+
+		# A run of digits alone on the line is a timestamp (the `-T u`
+		# switch to `iostat`). It closes any in-flight state as a
+		# complete chunk, and indicates the start of a new chunk.
+		if [[ -z ${line/#+([0-9])/} ]] ; then
+			_got_iostat $_iostat_state
+			_iostat_state="TIMESTAMP"
+			continue
+		fi
+
+		# For this test, the first word of each line should be unique,
+		# so we extract it and use it for simplicity.
+		typeset first=${line%% *}
+
+		# Header is emitted whenever the pool list changes. It has
+		# three lines:
+		#
+		#                   capacity     operations     bandwidth
+		#     pool        alloc   free   read  write   read  write
+		#     ----------  -----  -----  -----  -----  -----  -----
+		#
+		# Each line moves the state; when we get to a run of dashes, we
+		# commit.  Note that we check for one-or-more dashes, because
+		# the width can vary depending on the length of pool name.
+		#
+		if [[ $_iostat_state = "TIMESTAMP" &&
+		    $first = "capacity" ]] ; then
+			_iostat_state="INHEADER1"
+			continue
+		fi
+		if [[ $_iostat_state = "INHEADER1" &&
+		    $first = "pool" ]] ; then
+			_iostat_state="INHEADER2"
+			continue
+		fi
+		if [[ $_iostat_state = "INHEADER2" &&
+		    -z ${first/#+(-)/} ]] ; then
+			# Headers never repeat, so if the last committed chunk
+			# was a header, we commit this one as EXTRAHEADER so we
+			# can see it in the error output.
+			if [[ $_iostat_last = "HEADER" ]] ; then
+				_got_iostat "EXTRAHEADER"
+			elif [[ $_iostat_last != "EXTRAHEADER" ]] ; then
+				_got_iostat "HEADER"
+			fi
+			_iostat_state="HEADER"
+			continue
+		fi
+
+		# A pool stat line looks like:
+		#
+		#     pool1        147K   240M      0      0      0      0
+		#
+		# If there are multiple pools, iostat follows them with a
+		# separator of dashed lines:
+		#
+		#     pool1        147K   240M      0      0      0      0
+		#     pool2        147K   240M      0      0      0      0
+		#     ----------  -----  -----  -----  -----  -----  -----
+		#
+		# Stats rows always start after a timestamp or a header. If the
+		# header was emitted, we won't see a timestamp here (it goes
+		# before the header).
+		#
+		# Because our test exercises both pools on their own and
+		# together, we allow pools in either order. In practice they
+		# are sorted, but that's a side-effect of the implementation
+		# (see zpool_compare()), so we're not going to rely on it here.
+		if [[ $first = "pool1" ]] || [[ $first = "pool2" ]] ; then
+
+			# First line, track which one we saw. If it's a
+			# standalone line, it will be committed by the next
+			# NOPOOL or TIMESTAMP above (or the `_got_iostat` after
+			# the loop if this is the last line).
+			if [[ $_iostat_state == "TIMESTAMP" ||
+			    $_iostat_state == "HEADER" ]] ; then
+				if [[ $first = "pool1" ]] ; then
+					_iostat_state="POOL1"
+				elif [[ $first = "pool2" ]] ; then
+					_iostat_state="POOL2"
+				fi
+				continue
+			fi
+
+			# If this is the second pool, we're in a multi-pool
+			# block, and need to look for the separator to close it
+			# out.
+			if [[ $_iostat_state = "POOL1" && $first = "pool2" ]] ||
+			    [[ $_iostat_state = "POOL2" && $first = "pool1" ]] ;
+			    then
+				_iostat_state="INPOOLBOTH"
+				continue
+			fi
+		fi
+
+		# Separator after the stats block.
+		if [[ $_iostat_state = "INPOOLBOTH" &&
+		    -z ${first/#+(-)/} ]] ; then
+			_got_iostat "POOLBOTH"
+			continue
+		fi
+
+		# Anything else will fall through to here. We commit any
+		# in-flight state, then "UNKNOWN", all to help with debugging..
+		if [[ $_iostat_state != "UNKNOWN" ]] ; then
+			_got_iostat $_iostat_state
+			_got_iostat "UNKNOWN"
+		fi
+	done
+
+	# Close out any remaining state.
+	_got_iostat $_iostat_state
+
+	# Compare what we wanted with what we got, and pass/fail the test!
+	if [[ "${_iostat_expect[*]}" != "${_iostat_got[*]}" ]] ; then
+		log_note "expected: ${_iostat_expect[*]}"
+		log_note "     got: ${_iostat_got[*]}"
+		log_fail "zpool iostat did not produce expected output"
+	fi
+}
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat_interval_all.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat_interval_all.ksh
new file mode 100755
index 000000000000..8e040058ec3e
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat_interval_all.ksh
@@ -0,0 +1,90 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2025, Klara, Inc.
+#
+
+# `zpool iostat <N>` should keep running and update the pools it displays as
+# pools are created/destroyed/imported/export.
+
+. $STF_SUITE/include/libtest.shlib
+. $STF_SUITE/tests/functional/cli_root/zpool_iostat/zpool_iostat.kshlib
+
+typeset vdev1=$(mktemp)
+typeset vdev2=$(mktemp)
+
+function cleanup {
+	cleanup_iostat
+
+	poolexists pool1 && destroy_pool pool1
+	poolexists pool2 && destroy_pool pool2
+	rm -f $vdev1 $vdev2
+}
+
+log_must mkfile $MINVDEVSIZE $vdev1 $vdev2
+
+expect_iostat "NOPOOL"
+
+start_iostat
+
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOL1"
+log_must zpool create pool1 $vdev1
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOLBOTH"
+log_must zpool create pool2 $vdev2
+delay_iostat
+
+expect_iostat "NOPOOL"
+log_must zpool export -a
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOL2"
+log_must zpool import -d $vdev2 pool2
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOLBOTH"
+log_must zpool import -d $vdev1 pool1
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOL2"
+log_must zpool destroy pool1
+delay_iostat
+
+expect_iostat "NOPOOL"
+log_must zpool destroy pool2
+delay_iostat
+
+stop_iostat
+
+verify_iostat
+
+log_pass "zpool iostat in interval mode follows pool updates"
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat_interval_some.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat_interval_some.ksh
new file mode 100755
index 000000000000..ab1f258aa1cd
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_iostat/zpool_iostat_interval_some.ksh
@@ -0,0 +1,80 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2025, Klara, Inc.
+#
+
+# `zpool iostat <pools> <N>` should keep running and only show the listed pools.
+
+. $STF_SUITE/include/libtest.shlib
+. $STF_SUITE/tests/functional/cli_root/zpool_iostat/zpool_iostat.kshlib
+
+typeset vdev1=$(mktemp)
+typeset vdev2=$(mktemp)
+
+function cleanup {
+	cleanup_iostat
+
+	poolexists pool1 && destroy_pool pool1
+	poolexists pool2 && destroy_pool pool2
+	rm -f $vdev1 $vdev2
+}
+
+log_must mkfile $MINVDEVSIZE $vdev1 $vdev2
+
+log_must zpool create pool1 $vdev1
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOL1"
+start_iostat pool1
+delay_iostat
+
+log_must zpool create pool2 $vdev2
+delay_iostat
+
+expect_iostat "NOPOOL"
+log_must zpool export -a
+delay_iostat
+
+log_must zpool import -d $vdev2 pool2
+delay_iostat
+
+expect_iostat "HEADER"
+expect_iostat "POOL1"
+log_must zpool import -d $vdev1 pool1
+delay_iostat
+
+expect_iostat "NOPOOL"
+log_must zpool destroy pool1
+delay_iostat
+
+log_must zpool destroy pool2
+delay_iostat
+
+stop_iostat
+
+verify_iostat
+
+log_pass "zpool iostat in interval mode with pools follows listed pool updates"
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/delegate/delegate_common.kshlib b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/delegate/delegate_common.kshlib
index 0a402e71ee68..345239b88680 100644
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/delegate/delegate_common.kshlib
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/delegate/delegate_common.kshlib
@@ -1234,10 +1234,10 @@ function verify_fs_aedsx
 	typeset oldval
 	set -A modes "on" "off"
 	oldval=$(get_prop $perm $fs)
-	if [[ $oldval == "on" ]]; then
-		n=1
-	elif [[ $oldval == "off" ]]; then
+	if [[ $oldval == "off" ]]; then
 		n=0
+	else
+		n=1
 	fi
 	log_note "$user zfs set $perm=${modes[$n]} $fs"
 	user_run $user zfs set $perm=${modes[$n]} $fs
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/setup.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/setup.ksh
index 26153aafbc02..0e79e9b8b70c 100755
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/setup.ksh
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/setup.ksh
@@ -39,6 +39,6 @@
 verify_runnable "global"
 
 # create a pool without any features
-log_must mkfile 128m $TMPDEV
+log_must truncate -s $MINVDEVSIZE $TMPDEV
 
 log_pass
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/upgrade_readonly_pool.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/upgrade_readonly_pool.ksh
index d6bd69b7e134..e81d07794689 100755
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/upgrade_readonly_pool.ksh
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/upgrade/upgrade_readonly_pool.ksh
@@ -35,17 +35,19 @@
 
 verify_runnable "global"
 
-TESTFILE="$TESTDIR/file.bin"
-
 log_assert "User accounting upgrade should not be executed on readonly pool"
 log_onexit cleanup_upgrade
 
 # 1. Create a pool with the feature@userobj_accounting disabled to simulate
 #    a legacy pool from a previous ZFS version.
-log_must zpool create -d -m $TESTDIR $TESTPOOL $TMPDEV
+log_must zpool create -d $TESTPOOL $TMPDEV
+log_must zfs create $TESTPOOL/$TESTFS
+
+MNTPNT=$(get_prop mountpoint $TESTPOOL/$TESTFS)
+TESTFILE="$MNTPNT/file.bin"
 
 # 2. Create a file on the "legecy" dataset
-log_must touch $TESTDIR/file.bin
+log_must touch $TESTFILE
 
 # 3. Enable feature@userobj_accounting on the pool and verify it is only
 #    "enabled" and not "active": upgrading starts when the filesystem is mounted
@@ -54,12 +56,12 @@ log_must test "enabled" == "$(get_pool_prop 'feature@userobj_accounting' $TESTPO
 
 # 4. Export the pool and re-import is readonly, without mounting any filesystem
 log_must zpool export $TESTPOOL
-log_must zpool import -o readonly=on -N -d "$(dirname $TMPDEV)" $TESTPOOL
+log_must zpool import -o readonly=on -N -d $TEST_BASE_DIR $TESTPOOL
 
 # 5. Try to mount the root dataset manually without the "ro" option, then verify
 #    filesystem status and the pool feature status (not "active") to ensure the
 #    pool "readonly" status is enforced.
-log_must mount -t zfs -o zfsutil $TESTPOOL $TESTDIR
+log_must zfs mount -R $TESTPOOL
 log_must stat "$TESTFILE"
 log_mustnot touch "$TESTFILE"
 log_must test "enabled" == "$(get_pool_prop 'feature@userobj_accounting' $TESTPOOL)"
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/xattr/xattr_014_pos.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/xattr/xattr_014_pos.ksh
new file mode 100755
index 000000000000..d4c9a0a41816
--- /dev/null
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/xattr/xattr_014_pos.ksh
@@ -0,0 +1,53 @@
+#!/bin/ksh -p
+# SPDX-License-Identifier: CDDL-1.0
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or https://opensource.org/licenses/CDDL-1.0.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright (c) 2025 by Klara, Inc.
+#
+
+. $STF_SUITE/include/libtest.shlib
+. $STF_SUITE/tests/functional/xattr/xattr_common.kshlib
+
+#
+# DESCRIPTION:
+# The default xattr should be shown as 'sa', not 'on', for clarity.
+#
+# STRATEGY:
+#	1. Create a filesystem.
+#	2. Verify that the xattra is shown as 'sa'.
+#	3. Manually set the value to 'dir', 'sa', 'on', and 'off'.
+#	4. Verify that it is shown as 'dir', 'sa', 'sa', and 'off.
+#
+
+log_assert "The default and specific xattr values are displayed correctly."
+
+set -A args "dir" "sa" "on" "off"
+set -A display "dir" "sa" "sa" "off"
+
+log_must eval "[[ 'sa' == '$(zfs get -Hpo value xattr $TESTPOOL)' ]]"
+
+for i in `seq 0 3`; do
+	log_must zfs set xattr="${args[$i]}" $TESTPOOL
+	log_must eval "[[ '${display[$i]}' == '$(zfs get -Hpo value xattr $TESTPOOL)' ]]"
+done
+log_pass "The default and specific xattr values are displayed correctly."
diff --git a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/zvol/zvol_misc/zvol_misc_fua.ksh b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/zvol/zvol_misc/zvol_misc_fua.ksh
index 571a698eb63a..502ebada22dc 100755
--- a/sys/contrib/openzfs/tests/zfs-tests/tests/functional/zvol/zvol_misc/zvol_misc_fua.ksh
+++ b/sys/contrib/openzfs/tests/zfs-tests/tests/functional/zvol/zvol_misc/zvol_misc_fua.ksh
@@ -50,17 +50,53 @@ fi
 
 typeset datafile1="$(mktemp -t zvol_misc_fua1.XXXXXX)"
 typeset datafile2="$(mktemp -t zvol_misc_fua2.XXXXXX)"
+typeset datafile3="$(mktemp -t zvol_misc_fua3_log.XXXXXX)"
 typeset zvolpath=${ZVOL_DEVDIR}/$TESTPOOL/$TESTVOL
 
+typeset DISK1=${DISKS%% *}
 function cleanup
 {
-       rm "$datafile1" "$datafile2"
+	log_must zpool remove $TESTPOOL $datafile3
+	rm "$datafile1" "$datafile2" "$datafile2"
+}
+
+# Prints the total number of sync writes for a vdev
+# $1: vdev
+function get_sync
+{
+	zpool iostat -p -H -v -r $TESTPOOL $1 | \
+	    awk '/[0-9]+$/{s+=$4+$5} END{print s}'
 }
 
 function do_test {
 	# Wait for udev to create symlinks to our zvol
 	block_device_wait $zvolpath
 
+	# Write using sync (creates FLUSH calls after writes, but not FUA)
+	old_vdev_writes=$(get_sync $DISK1)
+	old_log_writes=$(get_sync $datafile3)
+
+	log_must fio --name=write_iops --size=5M \
+		--ioengine=libaio --verify=0 --bs=4K \
+		--iodepth=1 --rw=randwrite --group_reporting=1 \
+		--filename=$zvolpath --sync=1
+
+	vdev_writes=$(( $(get_sync $DISK1) - $old_vdev_writes))
+	log_writes=$(( $(get_sync $datafile3) - $old_log_writes))
+
+	# When we're doing sync writes, we should see many more writes go to
+	# the log vs the first vdev.  Experiments show anywhere from a 160-320x
+	# ratio of writes to the log vs the first vdev (due to some straggler
+	# writes to the first vdev).
+	#
+	# Check that we have a large ratio (100x) of sync writes going to the
+	# log device
+	ratio=$(($log_writes / $vdev_writes))
+	log_note "Got $log_writes log writes, $vdev_writes vdev writes."
+	if [ $ratio -lt 100 ] ; then
+		log_fail "Expected > 100x more log writes than vdev writes. "
+	fi
+
 	# Create a data file
 	log_must dd if=/dev/urandom of="$datafile1" bs=1M count=5
 
@@ -81,6 +117,8 @@ log_assert "Verify that a ZFS volume can do Force Unit Access (FUA)"
 log_onexit cleanup
 
 log_must zfs set compression=off $TESTPOOL/$TESTVOL
+log_must truncate -s 100M $datafile3
+log_must zpool add $TESTPOOL log $datafile3
 
 log_note "Testing without blk-mq"
 
diff --git a/sys/dev/acpica/acpi.c b/sys/dev/acpica/acpi.c
index 7f9ca6e39df8..3f0a7b40245d 100644
--- a/sys/dev/acpica/acpi.c
+++ b/sys/dev/acpica/acpi.c
@@ -3468,10 +3468,10 @@ acpi_EnterSleepState(struct acpi_softc *sc, enum power_stype stype)
 	return_ACPI_STATUS (AE_OK);
     }
 
-    EVENTHANDLER_INVOKE(power_suspend_early);
+    EVENTHANDLER_INVOKE(power_suspend_early, stype);
     stop_all_proc();
     suspend_all_fs();
-    EVENTHANDLER_INVOKE(power_suspend);
+    EVENTHANDLER_INVOKE(power_suspend, stype);
 
 #ifdef EARLY_AP_STARTUP
     MPASS(mp_ncpus == 1 || smp_started);
@@ -3632,7 +3632,7 @@ backout:
     resume_all_fs();
     resume_all_proc();
 
-    EVENTHANDLER_INVOKE(power_resume);
+    EVENTHANDLER_INVOKE(power_resume, stype);
 
     /* Allow another sleep request after a while. */
     callout_schedule(&acpi_sleep_timer, hz * ACPI_MINIMUM_AWAKETIME);
diff --git a/sys/dev/acpica/acpi_apei.c b/sys/dev/acpica/acpi_apei.c
index 9cfd46c97430..624c81ad1b4f 100644
--- a/sys/dev/acpica/acpi_apei.c
+++ b/sys/dev/acpica/acpi_apei.c
@@ -754,7 +754,7 @@ apei_detach(device_t dev)
 	apei_nmi = NULL;
 	apei_nmi_nges = NULL;
 	if (sc->nges.swi_ih != NULL) {
-		swi_remove(&sc->nges.swi_ih);
+		swi_remove(sc->nges.swi_ih);
 		sc->nges.swi_ih = NULL;
 	}
 	if (acpi_get_handle(dev) != NULL) {
diff --git a/sys/dev/acpica/acpi_powerres.c b/sys/dev/acpica/acpi_powerres.c
index 0a8b67a5fa84..29d1690f1bdd 100644
--- a/sys/dev/acpica/acpi_powerres.c
+++ b/sys/dev/acpica/acpi_powerres.c
@@ -76,13 +76,6 @@ struct acpi_powerconsumer {
     /* Device which is powered */
     ACPI_HANDLE				ac_consumer;
     int					ac_state;
-
-    struct {
-	bool				prx_has;
-	size_t				prx_count;
-	ACPI_HANDLE			*prx_deps;
-    } ac_prx[ACPI_D_STATE_COUNT];
-
     TAILQ_ENTRY(acpi_powerconsumer)	ac_link;
     TAILQ_HEAD(,acpi_powerreference)	ac_references;
 };
@@ -103,7 +96,9 @@ static TAILQ_HEAD(acpi_powerconsumer_list, acpi_powerconsumer)
 ACPI_SERIAL_DECL(powerres, "ACPI power resources");
 
 static ACPI_STATUS	acpi_pwr_register_consumer(ACPI_HANDLE consumer);
+#ifdef notyet
 static ACPI_STATUS	acpi_pwr_deregister_consumer(ACPI_HANDLE consumer);
+#endif /* notyet */
 static ACPI_STATUS	acpi_pwr_register_resource(ACPI_HANDLE res);
 #ifdef notyet
 static ACPI_STATUS	acpi_pwr_deregister_resource(ACPI_HANDLE res);
@@ -117,8 +112,6 @@ static struct acpi_powerresource
 			*acpi_pwr_find_resource(ACPI_HANDLE res);
 static struct acpi_powerconsumer
 			*acpi_pwr_find_consumer(ACPI_HANDLE consumer);
-static ACPI_STATUS	acpi_pwr_infer_state(struct acpi_powerconsumer *pc);
-static ACPI_STATUS	acpi_pwr_get_state_locked(ACPI_HANDLE consumer, int *state);
 
 /*
  * Register a power resource.
@@ -229,84 +222,6 @@ acpi_pwr_deregister_resource(ACPI_HANDLE res)
 #endif /* notyet */
 
 /*
- * Evaluate the _PRx (power resources each D-state depends on).  This also
- * populates the acpi_powerresources queue with the power resources discovered
- * during this step.
- *
- * ACPI 7.3.8 - 7.3.11 guarantee that _PRx will return the same data each
- * time they are evaluated.
- *
- * If this function fails, acpi_pwr_deregister_consumer() must be called on the
- * power consumer to free already allocated memory.
- */
-static ACPI_STATUS
-acpi_pwr_get_power_resources(ACPI_HANDLE consumer, struct acpi_powerconsumer *pc)
-{
-    ACPI_INTEGER	status;
-    ACPI_STRING		reslist_name;
-    ACPI_HANDLE		reslist_handle;
-    ACPI_STRING		reslist_names[] = {"_PR0", "_PR1", "_PR2", "_PR3"};
-    ACPI_BUFFER		reslist;
-    ACPI_OBJECT		*reslist_object;
-    ACPI_OBJECT		*dep;
-    ACPI_HANDLE		*res;
-
-    ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
-    ACPI_SERIAL_ASSERT(powerres);
-
-    MPASS(consumer != NULL);
-
-    for (int state = ACPI_STATE_D0; state <= ACPI_STATE_D3_HOT; state++) {
-	pc->ac_prx[state].prx_has = false;
-	pc->ac_prx[state].prx_count = 0;
-	pc->ac_prx[state].prx_deps = NULL;
-
-	reslist_name = reslist_names[state - ACPI_STATE_D0];
-	if (ACPI_FAILURE(AcpiGetHandle(consumer, reslist_name, &reslist_handle)))
-	    continue;
-
-	reslist.Pointer = NULL;
-	reslist.Length = ACPI_ALLOCATE_BUFFER;
-	status = AcpiEvaluateObjectTyped(reslist_handle, NULL, NULL, &reslist,
-					 ACPI_TYPE_PACKAGE);
-	if (ACPI_FAILURE(status) || reslist.Pointer == NULL)
-	    /*
-	     * ACPI_ALLOCATE_BUFFER entails everything will be freed on error
-	     * by AcpiEvaluateObjectTyped.
-	     */
-	    continue;
-
-	reslist_object = (ACPI_OBJECT *)reslist.Pointer;
-	pc->ac_prx[state].prx_has = true;
-	pc->ac_prx[state].prx_count = reslist_object->Package.Count;
-
-	if (reslist_object->Package.Count == 0) {
-	    AcpiOsFree(reslist_object);
-	    continue;
-	}
-
-	pc->ac_prx[state].prx_deps = mallocarray(pc->ac_prx[state].prx_count,
-	    sizeof(*pc->ac_prx[state].prx_deps), M_ACPIPWR, M_NOWAIT);
-	if (pc->ac_prx[state].prx_deps == NULL) {
-	    AcpiOsFree(reslist_object);
-	    return_ACPI_STATUS (AE_NO_MEMORY);
-	}
-
-	for (size_t i = 0; i < reslist_object->Package.Count; i++) {
-	    dep = &reslist_object->Package.Elements[i];
-	    res = dep->Reference.Handle;
-	    pc->ac_prx[state].prx_deps[i] = res;
-
-	    /* It's fine to attempt to register the same resource twice. */
-	    acpi_pwr_register_resource(res);
-	}
-	AcpiOsFree(reslist_object);
-    }
-
-    return_ACPI_STATUS (AE_OK);
-}
-
-/*
  * Register a power consumer.  
  *
  * It's OK to call this if we already know about the consumer.
@@ -314,7 +229,6 @@ acpi_pwr_get_power_resources(ACPI_HANDLE consumer, struct acpi_powerconsumer *pc
 static ACPI_STATUS
 acpi_pwr_register_consumer(ACPI_HANDLE consumer)
 {
-    ACPI_INTEGER		status;
     struct acpi_powerconsumer	*pc;
     
     ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
@@ -325,30 +239,14 @@ acpi_pwr_register_consumer(ACPI_HANDLE consumer)
 	return_ACPI_STATUS (AE_OK);
     
     /* Allocate a new power consumer */
-    if ((pc = malloc(sizeof(*pc), M_ACPIPWR, M_NOWAIT | M_ZERO)) == NULL)
+    if ((pc = malloc(sizeof(*pc), M_ACPIPWR, M_NOWAIT)) == NULL)
 	return_ACPI_STATUS (AE_NO_MEMORY);
     TAILQ_INSERT_HEAD(&acpi_powerconsumers, pc, ac_link);
     TAILQ_INIT(&pc->ac_references);
     pc->ac_consumer = consumer;
 
-    /*
-     * Get all its power resource dependencies, if it has _PRx.  We do this now
-     * as an opportunity to populate the acpi_powerresources queue.
-     *
-     * If this fails, immediately deregister it.
-     */
-    status = acpi_pwr_get_power_resources(consumer, pc);
-    if (ACPI_FAILURE(status)) {
-	ACPI_DEBUG_PRINT((ACPI_DB_OBJECTS,
-			 "failed to get power resources for %s\n",
-			 acpi_name(consumer)));
-	acpi_pwr_deregister_consumer(consumer);
-	return_ACPI_STATUS (status);
-    }
-
-    /* Find its initial state. */
-    if (ACPI_FAILURE(acpi_pwr_get_state_locked(consumer, &pc->ac_state)))
-	pc->ac_state = ACPI_STATE_UNKNOWN;
+    /* XXX we should try to find its current state */
+    pc->ac_state = ACPI_STATE_UNKNOWN;
 
     ACPI_DEBUG_PRINT((ACPI_DB_OBJECTS, "registered power consumer %s\n",
 		     acpi_name(consumer)));
@@ -356,6 +254,7 @@ acpi_pwr_register_consumer(ACPI_HANDLE consumer)
     return_ACPI_STATUS (AE_OK);
 }
 
+#ifdef notyet
 /*
  * Deregister a power consumer.
  *
@@ -380,9 +279,6 @@ acpi_pwr_deregister_consumer(ACPI_HANDLE consumer)
 
     /* Pull the consumer off the list and free it */
     TAILQ_REMOVE(&acpi_powerconsumers, pc, ac_link);
-    for (size_t i = 0; i < sizeof(pc->ac_prx) / sizeof(*pc->ac_prx); i++)
-	if (pc->ac_prx[i].prx_deps != NULL)
-	    free(pc->ac_prx[i].prx_deps, M_ACPIPWR);
     free(pc, M_ACPIPWR);
 
     ACPI_DEBUG_PRINT((ACPI_DB_OBJECTS, "deregistered power consumer %s\n",
@@ -390,139 +286,10 @@ acpi_pwr_deregister_consumer(ACPI_HANDLE consumer)
 
     return_ACPI_STATUS (AE_OK);
 }
+#endif /* notyet */
 
 /*
- * The _PSC control method isn't required if it's possible to infer the D-state
- * from the _PRx control methods.  (See 7.3.6.)
- * We can infer that a given D-state has been achieved when all the dependencies
- * are in the ON state.
- */
-static ACPI_STATUS
-acpi_pwr_infer_state(struct acpi_powerconsumer *pc)
-{
-    ACPI_HANDLE		*res;
-    uint32_t		on;
-    bool		all_on = false;
-
-    ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
-    ACPI_SERIAL_ASSERT(powerres);
-
-    /* It is important we go from the hottest to the coldest state. */
-    for (
-	pc->ac_state = ACPI_STATE_D0;
-	pc->ac_state <= ACPI_STATE_D3_HOT && !all_on;
-	pc->ac_state++
-    ) {
-	MPASS(pc->ac_state <= sizeof(pc->ac_prx) / sizeof(*pc->ac_prx));
-
-	if (!pc->ac_prx[pc->ac_state].prx_has)
-	    continue;
-
-	all_on = true;
-
-	for (size_t i = 0; i < pc->ac_prx[pc->ac_state].prx_count; i++) {
-	    res = pc->ac_prx[pc->ac_state].prx_deps[i];
-	    /* If failure, better to assume D-state is hotter than colder. */
-	    if (ACPI_FAILURE(acpi_GetInteger(res, "_STA", &on)))
-		continue;
-	    if (on == 0) {
-		all_on = false;
-		break;
-	    }
-	}
-    }
-
-    MPASS(pc->ac_state != ACPI_STATE_D0);
-
-    /*
-     * If none of the power resources required for the shallower D-states are
-     * on, then we can assume it is unpowered (i.e. D3cold).  A device is not
-     * required to support D3cold however; in that case, _PR3 is not explicitly
-     * provided.  Those devices should default to D3hot instead.
-     *
-     * See comments of first row of table 7.1 in ACPI spec.
-     */
-    if (!all_on)
-	pc->ac_state = pc->ac_prx[ACPI_STATE_D3_HOT].prx_has ?
-	    ACPI_STATE_D3_COLD : ACPI_STATE_D3_HOT;
-    else
-	pc->ac_state--;
-
-    return_ACPI_STATUS (AE_OK);
-}
-
-static ACPI_STATUS
-acpi_pwr_get_state_locked(ACPI_HANDLE consumer, int *state)
-{
-    struct acpi_powerconsumer	*pc;
-    ACPI_HANDLE			method_handle;
-    ACPI_STATUS			status;
-    ACPI_BUFFER			result;
-    ACPI_OBJECT			*object = NULL;
-
-    ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
-    ACPI_SERIAL_ASSERT(powerres);
-
-    if (consumer == NULL)
-	return_ACPI_STATUS (AE_NOT_FOUND);
-
-    if ((pc = acpi_pwr_find_consumer(consumer)) == NULL) {
-	if (ACPI_FAILURE(status = acpi_pwr_register_consumer(consumer)))
-	    goto out;
-	if ((pc = acpi_pwr_find_consumer(consumer)) == NULL)
-	    panic("acpi added power consumer but can't find it");
-    }
-
-    status = AcpiGetHandle(consumer, "_PSC", &method_handle);
-    if (ACPI_FAILURE(status)) {
-	ACPI_DEBUG_PRINT((ACPI_DB_OBJECTS, "no _PSC object - %s\n",
-			 AcpiFormatException(status)));
-	status = acpi_pwr_infer_state(pc);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_OBJECTS, "couldn't infer D-state - %s\n",
-				 AcpiFormatException(status)));
-		pc->ac_state = ACPI_STATE_UNKNOWN;
-	}
-	goto out;
-    }
-
-    result.Pointer = NULL;
-    result.Length = ACPI_ALLOCATE_BUFFER;
-    status = AcpiEvaluateObjectTyped(method_handle, NULL, NULL, &result, ACPI_TYPE_INTEGER);
-    if (ACPI_FAILURE(status) || result.Pointer == NULL) {
-	ACPI_DEBUG_PRINT((ACPI_DB_OBJECTS, "failed to get state with _PSC - %s\n",
-			 AcpiFormatException(status)));
-	pc->ac_state = ACPI_STATE_UNKNOWN;
-	goto out;
-    }
-
-    object = (ACPI_OBJECT *)result.Pointer;
-    pc->ac_state = ACPI_STATE_D0 + object->Integer.Value;
-    status = AE_OK;
-
-out:
-    if (object != NULL)
-	AcpiOsFree(object);
-    *state = pc->ac_state;
-    return_ACPI_STATUS (status);
-}
-
-/*
- * Get a power consumer's D-state.
- */
-ACPI_STATUS
-acpi_pwr_get_state(ACPI_HANDLE consumer, int *state)
-{
-	ACPI_STATUS	res;
-
-	ACPI_SERIAL_BEGIN(powerres);
-	res = acpi_pwr_get_state_locked(consumer, state);
-	ACPI_SERIAL_END(powerres);
-	return (res);
-}
-
-/*
- * Set a power consumer to a particular D-state.
+ * Set a power consumer to a particular power state.
  */
 ACPI_STATUS
 acpi_pwr_switch_consumer(ACPI_HANDLE consumer, int state)
@@ -533,7 +300,6 @@ acpi_pwr_switch_consumer(ACPI_HANDLE consumer, int state)
     ACPI_OBJECT			*reslist_object;
     ACPI_STATUS			status;
     char			*method_name, *reslist_name = NULL;
-    int				new_state;
 
     ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
 
@@ -735,28 +501,8 @@ acpi_pwr_switch_consumer(ACPI_HANDLE consumer, int state)
 	}
     }
 
-    /*
-     * Make sure the transition succeeded.  If getting new state failed,
-     * just assume the new state is what we wanted.  This was the behaviour
-     * before we were checking D-states.
-     */
-    if (ACPI_FAILURE(acpi_pwr_get_state_locked(consumer, &new_state))) {
-	printf("%s: failed to get new D-state\n", __func__);
-	pc->ac_state = state;
-    } else {
-	if (new_state != state)
-	    printf("%s: new power state %s is not the one requested %s\n",
-		   __func__, acpi_d_state_to_str(new_state),
-		   acpi_d_state_to_str(state));
-	pc->ac_state = new_state;
-    }
-
-    /*
-     * We consider the transition successful even if the state we got doesn't
-     * reflect what we set it to.  This is because we weren't previously
-     * checking the new state at all, so there might exist buggy platforms on
-     * which suspend would otherwise succeed if we failed here.
-     */
+    /* Transition was successful */
+    pc->ac_state = state;
     status = AE_OK;
 
 out:
diff --git a/sys/dev/acpica/acpi_timer.c b/sys/dev/acpica/acpi_timer.c
index 3d51a4211b80..b20912e2f5fb 100644
--- a/sys/dev/acpica/acpi_timer.c
+++ b/sys/dev/acpica/acpi_timer.c
@@ -34,6 +34,7 @@
 #include <sys/module.h>
 #include <sys/sysctl.h>
 #include <sys/timetc.h>
+#include <sys/power.h>
 
 #include <machine/bus.h>
 #include <machine/resource.h>
@@ -69,8 +70,10 @@ bool acpi_timer_disabled = false;
 static void	acpi_timer_identify(driver_t *driver, device_t parent);
 static int	acpi_timer_probe(device_t dev);
 static int	acpi_timer_attach(device_t dev);
-static void	acpi_timer_resume_handler(struct timecounter *);
-static void	acpi_timer_suspend_handler(struct timecounter *);
+static void	acpi_timer_resume_handler(struct timecounter *,
+		    enum power_stype);
+static void	acpi_timer_suspend_handler(struct timecounter *,
+		    enum power_stype);
 static u_int	acpi_timer_get_timecount(struct timecounter *tc);
 static u_int	acpi_timer_get_timecount_safe(struct timecounter *tc);
 static int	acpi_timer_sysctl_freq(SYSCTL_HANDLER_ARGS);
@@ -235,7 +238,7 @@ acpi_timer_attach(device_t dev)
 }
 
 static void
-acpi_timer_resume_handler(struct timecounter *newtc)
+acpi_timer_resume_handler(struct timecounter *newtc, enum power_stype stype)
 {
 	struct timecounter *tc;
 
@@ -251,7 +254,7 @@ acpi_timer_resume_handler(struct timecounter *newtc)
 }
 
 static void
-acpi_timer_suspend_handler(struct timecounter *newtc)
+acpi_timer_suspend_handler(struct timecounter *newtc, enum power_stype stype)
 {
 	struct timecounter *tc;
 
diff --git a/sys/dev/acpica/acpivar.h b/sys/dev/acpica/acpivar.h
index 4c789dd3e9f2..71d8e46ab310 100644
--- a/sys/dev/acpica/acpivar.h
+++ b/sys/dev/acpica/acpivar.h
@@ -490,7 +490,6 @@ EVENTHANDLER_DECLARE(acpi_video_event, acpi_event_handler_t);
 
 /* Device power control. */
 ACPI_STATUS	acpi_pwr_wake_enable(ACPI_HANDLE consumer, int enable);
-ACPI_STATUS	acpi_pwr_get_state(ACPI_HANDLE consumer, int *state);
 ACPI_STATUS	acpi_pwr_switch_consumer(ACPI_HANDLE consumer, int state);
 acpi_pwr_for_sleep_t	acpi_device_pwr_for_sleep;
 int		acpi_set_powerstate(device_t child, int state);
diff --git a/sys/dev/ahci/ahci_pci.c b/sys/dev/ahci/ahci_pci.c
index 82f56fc0d19e..2b4cb37275a6 100644
--- a/sys/dev/ahci/ahci_pci.c
+++ b/sys/dev/ahci/ahci_pci.c
@@ -467,28 +467,6 @@ ahci_ata_probe(device_t dev)
 }
 
 static int
-ahci_pci_read_msix_bars(device_t dev, uint8_t *table_bar, uint8_t *pba_bar)
-{
-	int cap_offset = 0, ret;
-	uint32_t val;
-
-	if ((table_bar == NULL) || (pba_bar == NULL))
-		return (EINVAL);
-
-	ret = pci_find_cap(dev, PCIY_MSIX, &cap_offset);
-	if (ret != 0)
-		return (EINVAL);
-
-	val = pci_read_config(dev, cap_offset + PCIR_MSIX_TABLE, 4);
-	*table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
-
-	val = pci_read_config(dev, cap_offset + PCIR_MSIX_PBA, 4);
-	*pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
-
-	return (0);
-}
-
-static int
 ahci_pci_attach(device_t dev)
 {
 	struct ahci_controller *ctlr = device_get_softc(dev);
@@ -496,7 +474,6 @@ ahci_pci_attach(device_t dev)
 	uint32_t devid = pci_get_devid(dev);
 	uint8_t revid = pci_get_revid(dev);
 	int msi_count, msix_count;
-	uint8_t table_bar = 0, pba_bar = 0;
 	uint32_t caps, pi;
 
 	msi_count = pci_msi_count(dev);
@@ -584,20 +561,11 @@ ahci_pci_attach(device_t dev)
 	if (ctlr->quirks & AHCI_Q_NOMSIX)
 		msix_count = 0;
 
-	/* Read MSI-x BAR IDs if supported */
-	if (msix_count > 0) {
-		error = ahci_pci_read_msix_bars(dev, &table_bar, &pba_bar);
-		if (error == 0) {
-			ctlr->r_msix_tab_rid = table_bar;
-			ctlr->r_msix_pba_rid = pba_bar;
-		} else {
-			/* Failed to read BARs, disable MSI-x */
-			msix_count = 0;
-		}
-	}
-
 	/* Allocate resources for MSI-x table and PBA */
 	if (msix_count > 0) {
+		ctlr->r_msix_tab_rid = pci_msix_table_bar(dev);
+		ctlr->r_msix_pba_rid = pci_msix_pba_bar(dev);
+
 		/*
 		 * Allocate new MSI-x table only if not
 		 * allocated before.
@@ -608,8 +576,8 @@ ahci_pci_attach(device_t dev)
 			ctlr->r_msix_table = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 			    &ctlr->r_msix_tab_rid, RF_ACTIVE);
 			if (ctlr->r_msix_table == NULL) {
-				ahci_free_mem(dev);
-				return (ENXIO);
+				msix_count = 0;
+				goto no_msix;
 			}
 		}
 
@@ -624,12 +592,12 @@ ahci_pci_attach(device_t dev)
 			ctlr->r_msix_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 			    &ctlr->r_msix_pba_rid, RF_ACTIVE);
 			if (ctlr->r_msix_pba == NULL) {
-				ahci_free_mem(dev);
-				return (ENXIO);
+				msix_count = 0;
 			}
 		}
 	}
 
+no_msix:
 	pci_enable_busmaster(dev);
 	/* Reset controller */
 	if ((error = ahci_pci_ctlr_reset(dev)) != 0) {
diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c
index deadd63c3d18..9ac591c14943 100644
--- a/sys/dev/ath/if_ath_tx.c
+++ b/sys/dev/ath/if_ath_tx.c
@@ -971,6 +971,12 @@ ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
 		ath_tx_handoff_hw(sc, txq, bf);
 }
 
+/*
+ * Setup a frame for encryption.
+ *
+ * If this fails, then an non-zero error is returned.  The mbuf
+ * must be freed by the caller.
+ */
 static int
 ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni,
     struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen,
@@ -1547,6 +1553,10 @@ ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq,
  *
  * Note that this may cause the mbuf to be reallocated, so
  * m0 may not be valid.
+ *
+ * If there's a problem then the mbuf is freed and an error
+ * is returned.  The ath_buf then needs to be freed by the
+ * caller.
  */
 static int
 ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
@@ -2073,9 +2083,8 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
 
 	/* This also sets up the DMA map; crypto; frame parameters, etc */
 	r = ath_tx_normal_setup(sc, ni, bf, m0, txq);
-
 	if (r != 0)
-		goto done;
+		return (r);
 
 	/* At this point m0 could have changed! */
 	m0 = bf->bf_m;
@@ -2132,7 +2141,6 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
 	ath_tx_leak_count_update(sc, tid, bf);
 	ath_tx_xmit_normal(sc, txq, bf);
 #endif
-done:
 	return 0;
 }
 
diff --git a/sys/dev/bnxt/bnxt_en/if_bnxt.c b/sys/dev/bnxt/bnxt_en/if_bnxt.c
index feac3ce54a29..471e26a4b252 100644
--- a/sys/dev/bnxt/bnxt_en/if_bnxt.c
+++ b/sys/dev/bnxt/bnxt_en/if_bnxt.c
@@ -48,6 +48,7 @@
 #include <net/ethernet.h>
 #include <net/iflib.h>
 
+#define	WANT_NATIVE_PCI_GET_SLOT
 #include <linux/pci.h>
 #include <linux/kmod.h>
 #include <linux/module.h>
diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h
index d3820245837a..55f09fefb7e3 100644
--- a/sys/dev/cxgbe/adapter.h
+++ b/sys/dev/cxgbe/adapter.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2025 Chelsio Communications.
  * Written by: Navdeep Parhar <np@FreeBSD.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -319,7 +318,7 @@ struct port_info {
 	char lockname[16];
 	unsigned long flags;
 
-	uint8_t  lport;		/* associated offload logical port */
+	uint8_t  hw_port;	/* associated hardware port idx */
 	int8_t   mdio_addr;
 	uint8_t  port_type;
 	uint8_t  mod_type;
@@ -413,6 +412,24 @@ enum {
 	NUM_CPL_COOKIES = 8	/* Limited by M_COOKIE.  Do not increase. */
 };
 
+/*
+ * Crypto replies use the low bit in the 64-bit cookie of CPL_FW6_PLD as a
+ * CPL cookie to identify the sender/receiver.
+ */
+enum {
+	CPL_FW6_COOKIE_CCR = 0,
+	CPL_FW6_COOKIE_KTLS,
+
+	NUM_CPL_FW6_COOKIES = 2	/* Low bits of cookie value. */
+};
+
+_Static_assert(powerof2(NUM_CPL_FW6_COOKIES),
+    "NUM_CPL_FW6_COOKIES must be a power of 2");
+
+#define	CPL_FW6_COOKIE_MASK	(NUM_CPL_FW6_COOKIES - 1)
+
+#define	CPL_FW6_PLD_COOKIE(cpl)	(be64toh((cpl)->data[1]) & ~CPL_FW6_COOKIE_MASK)
+
 struct sge_iq;
 struct rss_header;
 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
@@ -477,6 +494,7 @@ struct sge_eq {
 	uint8_t doorbells;
 	uint8_t port_id;	/* port_id of the port associated with the eq */
 	uint8_t tx_chan;	/* tx channel used by the eq */
+	uint8_t hw_port;	/* hw port used by the eq */
 	struct mtx eq_lock;
 
 	struct tx_desc *desc;	/* KVA of descriptor ring */
@@ -640,12 +658,26 @@ struct sge_txq {
 	uint64_t kern_tls_full;
 	uint64_t kern_tls_octets;
 	uint64_t kern_tls_waste;
-	uint64_t kern_tls_options;
 	uint64_t kern_tls_header;
-	uint64_t kern_tls_fin;
 	uint64_t kern_tls_fin_short;
 	uint64_t kern_tls_cbc;
 	uint64_t kern_tls_gcm;
+	union {
+		struct {
+			/* T6 only. */
+			uint64_t kern_tls_options;
+			uint64_t kern_tls_fin;
+		};
+		struct {
+			/* T7 only. */
+			uint64_t kern_tls_ghash_received;
+			uint64_t kern_tls_ghash_requested;
+			uint64_t kern_tls_lso;
+			uint64_t kern_tls_partial_ghash;
+			uint64_t kern_tls_splitmode;
+			uint64_t kern_tls_trailer;
+		};
+	};
 
 	/* stats for not-that-common events */
 
@@ -769,6 +801,16 @@ struct sge_ofld_txq {
 	counter_u64_t tx_toe_tls_octets;
 } __aligned(CACHE_LINE_SIZE);
 
+static inline int
+ofld_txq_group(int val, int mask)
+{
+	const uint32_t ngroup = 1 << bitcount32(mask);
+	const int mshift = ffs(mask) - 1;
+	const uint32_t gmask = ngroup - 1;
+
+	return (val >> mshift & gmask);
+}
+
 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
 struct sge_nm_rxq {
 	/* Items used by the driver rx ithread are in this cacheline. */
@@ -836,6 +878,7 @@ struct sge_nm_txq {
 } __aligned(CACHE_LINE_SIZE);
 
 struct sge {
+	int nctrlq;	/* total # of control queues */
 	int nrxq;	/* total # of Ethernet rx queues */
 	int ntxq;	/* total # of Ethernet tx queues */
 	int nofldrxq;	/* total # of TOE rx queues */
@@ -937,7 +980,8 @@ struct adapter {
 
 	struct taskqueue *tq[MAX_NPORTS];	/* General purpose taskqueues */
 	struct port_info *port[MAX_NPORTS];
-	uint8_t chan_map[MAX_NCHAN];		/* channel -> port */
+	uint8_t chan_map[MAX_NCHAN];		/* tx_chan -> port_id */
+	uint8_t port_map[MAX_NPORTS];		/* hw_port -> port_id */
 
 	CXGBE_LIST_HEAD(, clip_entry) *clip_table;
 	TAILQ_HEAD(, clip_entry) clip_pending;	/* these need hw update. */
@@ -959,9 +1003,12 @@ struct adapter {
 	vmem_t *key_map;
 	struct tls_tunables tlst;
 
+	vmem_t *pbl_arena;
+	vmem_t *stag_arena;
+
 	uint8_t doorbells;
 	int offload_map;	/* port_id's with IFCAP_TOE enabled */
-	int bt_map;		/* tx_chan's with BASE-T */
+	int bt_map;		/* hw_port's that are BASE-T */
 	int active_ulds;	/* ULDs activated on this adapter */
 	int flags;
 	int debug_flags;
@@ -988,6 +1035,7 @@ struct adapter {
 	uint16_t nbmcaps;
 	uint16_t linkcaps;
 	uint16_t switchcaps;
+	uint16_t nvmecaps;
 	uint16_t niccaps;
 	uint16_t toecaps;
 	uint16_t rdmacaps;
@@ -1409,6 +1457,14 @@ void t6_ktls_modunload(void);
 int t6_ktls_try(if_t, struct socket *, struct ktls_session *);
 int t6_ktls_parse_pkt(struct mbuf *);
 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int);
+
+/* t7_kern_tls.c */
+int t7_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
+    struct m_snd_tag **);
+void t7_ktls_modload(void);
+void t7_ktls_modunload(void);
+int t7_ktls_parse_pkt(struct mbuf *);
+int t7_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int);
 #endif
 
 /* t4_keyctx.c */
@@ -1536,6 +1592,27 @@ int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbu
 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
 void free_hftid_hash(struct tid_info *);
 
+/* t4_tpt.c */
+#define T4_STAG_UNSET 0xffffffff
+#define	T4_WRITE_MEM_DMA_LEN						\
+	roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_sgl), 16)
+#define T4_ULPTX_MIN_IO 32
+#define T4_MAX_INLINE_SIZE 96
+#define	T4_WRITE_MEM_INLINE_LEN(len)					\
+	roundup2(sizeof(struct ulp_mem_io) + sizeof(struct ulptx_idata) + \
+	    roundup((len), T4_ULPTX_MIN_IO), 16)
+
+uint32_t t4_pblpool_alloc(struct adapter *, int);
+void t4_pblpool_free(struct adapter *, uint32_t, int);
+uint32_t t4_stag_alloc(struct adapter *, int);
+void t4_stag_free(struct adapter *, uint32_t, int);
+void t4_init_tpt(struct adapter *);
+void t4_free_tpt(struct adapter *);
+void t4_write_mem_dma_wr(struct adapter *, void *, int, int, uint32_t,
+    uint32_t, vm_paddr_t, uint64_t);
+void t4_write_mem_inline_wr(struct adapter *, void *, int, int, uint32_t,
+    uint32_t, void *, uint64_t);
+
 static inline struct wrqe *
 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
 {
diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index 6e80ce40648b..6b36832a7464 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -32,6 +31,15 @@
 
 #include "t4_hw.h"
 
+#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
+		F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
+		F_CPL_SWITCH | F_SGE | F_ULP_TX | F_SF)
+
+#define GLBL_T7_INTR_MASK (F_CIM | F_MPS | F_PL | F_T7_PCIE | F_T7_MC0 | \
+			   F_T7_EDC0 | F_T7_EDC1 | F_T7_LE | F_T7_TP | \
+			   F_T7_MA | F_T7_PM_TX | F_T7_PM_RX | F_T7_ULP_RX | \
+			   F_T7_CPL_SWITCH | F_T7_SGE | F_T7_ULP_TX | F_SF)
+
 enum {
 	MAX_NPORTS     = 4,     /* max # of ports */
 	SERNUM_LEN     = 24,    /* Serial # length */
@@ -77,6 +85,18 @@ enum {
 	FEC_MODULE    = 1 << 6,	/* FEC suggested by the cable/transceiver. */
 };
 
+enum {
+	ULP_T10DIF_ISCSI = 1 << 0,
+	ULP_T10DIF_FCOE = 1 << 1
+};
+
+enum {
+	ULP_CRYPTO_LOOKASIDE  = 1 << 0,
+	ULP_CRYPTO_INLINE_TLS = 1 << 1,
+	ULP_CRYPTO_INLINE_IPSEC = 1 << 2,
+	ULP_CRYPTO_OFLD_OVER_IPSEC_INLINE = 1 << 4
+};
+
 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
 
 struct port_stats {
@@ -230,6 +250,15 @@ struct tp_cpl_stats {
 struct tp_rdma_stats {
 	u32 rqe_dfr_pkt;
 	u32 rqe_dfr_mod;
+	u32 pkts_in[MAX_NCHAN];
+	u64 bytes_in[MAX_NCHAN];
+	/*
+	 * When reading rdma stats, the address difference b/w RDMA_IN and
+	 * RDMA_OUT is 4*u32, to read both at once, added padding
+	 */
+	u32 padding[4];
+	u32 pkts_out[MAX_NCHAN];
+	u64 bytes_out[MAX_NCHAN];
 };
 
 struct sge_params {
@@ -259,7 +288,10 @@ struct tp_params {
 	uint32_t max_rx_pdu;
 	uint32_t max_tx_pdu;
 	bool rx_pkt_encap;
+	uint8_t lb_mode;
+	uint8_t lb_nchan;
 
+	int8_t ipsecidx_shift;
 	int8_t fcoe_shift;
 	int8_t port_shift;
 	int8_t vnic_shift;
@@ -270,6 +302,9 @@ struct tp_params {
 	int8_t macmatch_shift;
 	int8_t matchtype_shift;
 	int8_t frag_shift;
+	int8_t roce_shift;
+	int8_t synonly_shift;
+	int8_t tcpflags_shift;
 };
 
 /* Use same modulation queue as the tx channel. */
@@ -285,6 +320,22 @@ struct vpd_params {
 	u8 md[MD_LEN + 1];
 };
 
+/*
+ * Maximum resources provisioned for a PCI PF.
+ */
+struct pf_resources {
+	unsigned int nvi;		/* N virtual interfaces */
+	unsigned int neq;		/* N egress Qs */
+	unsigned int nethctrl;		/* N egress ETH or CTRL Qs */
+	unsigned int niqflint;		/* N ingress Qs/w free list(s) & intr */
+	unsigned int niq;		/* N ingress Qs */
+	unsigned int tc;		/* PCI-E traffic class */
+	unsigned int pmask;		/* port access rights mask */
+	unsigned int nexactf;		/* N exact MPS filters */
+	unsigned int r_caps;		/* read capabilities */
+	unsigned int wx_caps;		/* write/execute capabilities */
+};
+
 struct pci_params {
 	unsigned int vpd_cap_addr;
 	unsigned int mps;
@@ -308,8 +359,11 @@ struct chip_params {
 	u8 pm_stats_cnt;
 	u8 cng_ch_bits_log;		/* congestion channel map bits width */
 	u8 nsched_cls;
+	u8 cim_num_ibq;
 	u8 cim_num_obq;
-	u8 filter_opt_len;
+	u8 filter_opt_len;		/* number of bits for optional fields */
+	u8 filter_num_opt;		/* number of optional fields */
+	u8 sge_ctxt_size;
 	u16 mps_rplc_size;
 	u16 vfcount;
 	u32 sge_fl_db;
@@ -360,6 +414,7 @@ struct adapter_params {
 	struct sge_params sge;
 	struct tp_params  tp;		/* PF-only */
 	struct vpd_params vpd;
+	struct pf_resources pfres;	/* PF-only */
 	struct pci_params pci;
 	struct devlog_params devlog;	/* PF-only */
 	struct rss_params rss;		/* VF-only */
@@ -399,12 +454,13 @@ struct adapter_params {
 	unsigned int ofldq_wr_cred;
 	unsigned int eo_wr_cred;
 
-	unsigned int max_ordird_qp;
-	unsigned int max_ird_adapter;
+	unsigned int max_ordird_qp;	  /* Max read depth per RDMA QP */
+	unsigned int max_ird_adapter;	  /* Max read depth per adapter */
 
 	/* These values are for all ports (8b/port, upto 4 ports) */
 	uint32_t mps_bg_map;	/* MPS rx buffer group map */
 	uint32_t tp_ch_map;	/* TPCHMAP from firmware */
+	uint32_t tx_tp_ch_map;	/* TX_TPCHMAP from firmware */
 
 	bool ulptx_memwrite_dsgl;	/* use of T5 DSGL allowed */
 	bool fr_nsmr_tpte_wr_support;	/* FW support for FR_NSMR_TPTE_WR */
@@ -412,11 +468,15 @@ struct adapter_params {
 	bool viid_smt_extn_support;	/* FW returns vin, vfvld & smt index? */
 	unsigned int max_pkts_per_eth_tx_pkts_wr;
 	uint8_t nsched_cls;		/* # of usable sched classes per port */
+
+	uint8_t ncores;
+	uint32_t tid_qid_sel_mask;	/* TID based QID selection mask */
 };
 
 #define CHELSIO_T4		0x4
 #define CHELSIO_T5		0x5
 #define CHELSIO_T6		0x6
+#define CHELSIO_T7		0x7
 
 /*
  * State needed to monitor the forward progress of SGE Ingress DMA activities
@@ -509,10 +569,11 @@ static inline int is_hashfilter(const struct adapter *adap)
 
 static inline int is_ktls(const struct adapter *adap)
 {
-	return adap->cryptocaps & FW_CAPS_CONFIG_TLS_HW;
+	return adap->cryptocaps & FW_CAPS_CONFIG_TLS_HW ||
+	    adap->params.chipid == CHELSIO_T7;
 }
 
-static inline int chip_id(struct adapter *adap)
+static inline int chip_id(const struct adapter *adap)
 {
 	return adap->params.chipid;
 }
@@ -537,6 +598,11 @@ static inline int is_t6(struct adapter *adap)
 	return adap->params.chipid == CHELSIO_T6;
 }
 
+static inline int is_t7(struct adapter *adap)
+{
+	return adap->params.chipid == CHELSIO_T7;
+}
+
 static inline int is_fpga(struct adapter *adap)
 {
 	 return adap->params.fpga;
@@ -641,7 +707,7 @@ int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int si
 int t4_load_boot(struct adapter *adap, u8 *boot_data,
                  unsigned int boot_addr, unsigned int size);
 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
-int t4_flash_cfg_addr(struct adapter *adapter);
+int t4_flash_cfg_addr(struct adapter *adapter, unsigned int *lenp);
 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr);
@@ -655,9 +721,10 @@ int t4_init_hw(struct adapter *adapter, u32 fw_params);
 const struct chip_params *t4_get_chip_params(int chipid);
 int t4_prep_adapter(struct adapter *adapter, u32 *buf);
 int t4_shutdown_adapter(struct adapter *adapter);
-int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
+int t4_init_devlog_ncores_params(struct adapter *adapter, int fw_attach);
 int t4_init_sge_params(struct adapter *adapter);
 int t4_init_tp_params(struct adapter *adap);
+int t4_filter_field_width(const struct adapter *adap, int filter_field);
 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
 void t4_fatal_err(struct adapter *adapter, bool fw_error);
@@ -665,6 +732,7 @@ int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
 			int filter_index, int enable);
 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
 			 int filter_index, int *enabled);
+void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid);
 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
 			int start, int n, const u16 *rspq, unsigned int nrspq);
 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
@@ -691,19 +759,60 @@ void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok);
 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
-void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
-int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
-int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
-int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
-		unsigned int *valp);
-int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
-		 const unsigned int *valp);
-int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
-		    unsigned int *valp);
-int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
+void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[]);
+void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
+			   u16 *size, u16 *thres);
+int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+			 size_t n);
+int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+			 size_t n);
+int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
+		     unsigned int addr, unsigned int n,
+		     unsigned int *valp);
+int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
+		      unsigned int addr, unsigned int n,
+		      const unsigned int *valp);
+int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
+			u32 *wrptr);
 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
 		unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
+
+static inline void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size,
+    				    u16 *thres)
+{
+	t4_read_cimq_cfg_core(adap, 0, base, size, thres);
+}
+
+static inline int t4_read_cim_ibq(struct adapter *adap, u32 qid, u32 *data,
+			          size_t n)
+{
+	return t4_read_cim_ibq_core(adap, 0, qid, data, n);
+}
+
+static inline int t4_read_cim_obq(struct adapter *adap, u32 qid, u32 *data,
+			          size_t n)
+{
+	return t4_read_cim_obq_core(adap, 0, qid, data, n);
+}
+
+static inline int t4_cim_read(struct adapter *adap, unsigned int addr,
+			      unsigned int n, unsigned int *valp)
+{
+	return t4_cim_read_core(adap, 0, 0, addr, n, valp);
+}
+
+static inline int t4_cim_write(struct adapter *adap, unsigned int addr,
+			       unsigned int n, unsigned int *valp)
+{
+	return t4_cim_write_core(adap, 0, 0, addr, n, valp);
+}
+
+static inline int t4_cim_read_la(struct adapter *adap, u32 *la_buf, u32 *wrptr)
+{
+	return t4_cim_read_la_core(adap, 0, la_buf, wrptr);
+}
+
 int t4_get_flash_params(struct adapter *adapter);
 
 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
@@ -919,6 +1028,8 @@ int t4_configure_ringbb(struct adapter *adap);
 int t4_configure_add_smac(struct adapter *adap);
 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
 		    u16 vlan);
+int t4_flash_loc_start(struct adapter *adap, enum t4_flash_loc loc,
+    unsigned int *lenp);
 
 static inline int t4vf_query_params(struct adapter *adapter,
 				    unsigned int nparams, const u32 *params,
@@ -969,8 +1080,8 @@ port_top_speed(const struct port_info *pi)
     sizeof(struct ulptx_idata) + sizeof(struct cpl_set_tcb_field_core))
 
 static inline void *
-mk_set_tcb_field_ulp(struct adapter *sc, void *cur, int tid, uint16_t word,
-    uint64_t mask, uint64_t val)
+mk_set_tcb_field_ulp_with_rpl(struct adapter *sc, void *cur, int tid,
+    uint16_t word, uint64_t mask, uint64_t val, const int qid)
 {
 	struct ulp_txpkt *ulpmc;
 	struct ulptx_idata *ulpsc;
@@ -989,8 +1100,21 @@ mk_set_tcb_field_ulp(struct adapter *sc, void *cur, int tid, uint16_t word,
 
 	req = (struct cpl_set_tcb_field_core *)(ulpsc + 1);
 	OPCODE_TID(req) = htobe32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
-	req->reply_ctrl = htobe16(F_NO_REPLY);
-	req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(0));
+
+	if (qid == -1) {
+		req->reply_ctrl = htobe16(F_NO_REPLY);
+		req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(0));
+	} else {
+		if (chip_id(sc) >= CHELSIO_T7) {
+			req->reply_ctrl = htobe16(V_T7_QUEUENO(qid) |
+			    V_T7_REPLY_CHAN(0) | V_NO_REPLY(0));
+		} else {
+			req->reply_ctrl = htobe16(V_QUEUENO(qid) |
+			    V_REPLY_CHAN(0) | V_NO_REPLY(0));
+		}
+		req->word_cookie = htobe16(V_WORD(word) |
+		    V_COOKIE(CPL_COOKIE_TOM));
+	}
 	req->mask = htobe64(mask);
 	req->val = htobe64(val);
 
@@ -1006,4 +1130,11 @@ mk_set_tcb_field_ulp(struct adapter *sc, void *cur, int tid, uint16_t word,
 
 	return (ulpsc + 1);
 }
+
+static inline void *
+mk_set_tcb_field_ulp(struct adapter *sc, void *cur, int tid, uint16_t word,
+    uint64_t mask, uint64_t val)
+{
+	return (mk_set_tcb_field_ulp_with_rpl(sc, cur, tid, word, mask, val, -1));
+}
 #endif /* __CHELSIO_COMMON_H */
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 07940a44f66e..eb7ea9acc108 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2012, 2016, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -246,6 +245,8 @@ struct port_tx_state {
 u32
 t4_port_reg(struct adapter *adap, u8 port, u32 reg)
 {
+	if (chip_id(adap) > CHELSIO_T6)
+		return T7_PORT_REG(port, reg);
 	if (chip_id(adap) > CHELSIO_T4)
 		return T5_PORT_REG(port, reg);
 	return PORT_REG(port, reg);
@@ -268,8 +269,10 @@ read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
 {
 	int i;
 
-	for_each_port(sc, i)
-		read_tx_state_one(sc, i, &tx_state[i]);
+	for (i = 0; i < MAX_NCHAN; i++) {
+		if (sc->chan_map[i] != 0xff)
+			read_tx_state_one(sc, i, &tx_state[i]);
+	}
 }
 
 static void
@@ -279,7 +282,9 @@ check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
 	uint64_t tx_frames, rx_pause;
 	int i;
 
-	for_each_port(sc, i) {
+	for (i = 0; i < MAX_NCHAN; i++) {
+		if (sc->chan_map[i] == 0xff)
+			continue;
 		rx_pause = tx_state[i].rx_pause;
 		tx_frames = tx_state[i].tx_frames;
 		read_tx_state_one(sc, i, &tx_state[i]);	/* update */
@@ -351,7 +356,7 @@ int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 		return -EINVAL;
 
 	if (adap->flags & IS_VF) {
-		if (is_t6(adap))
+		if (chip_id(adap) >= CHELSIO_T6)
 			data_reg = FW_T6VF_MBDATA_BASE_ADDR;
 		else
 			data_reg = FW_T4VF_MBDATA_BASE_ADDR;
@@ -508,9 +513,8 @@ failed:
 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 		    void *rpl, bool sleep_ok)
 {
-		return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
-					       sleep_ok, FW_CMD_MAX_TIMEOUT);
-
+	return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
+				       sleep_ok, FW_CMD_MAX_TIMEOUT);
 }
 
 static int t4_edc_err_read(struct adapter *adap, int idx)
@@ -799,6 +803,7 @@ unsigned int t4_get_regs_len(struct adapter *adapter)
 
 	case CHELSIO_T5:
 	case CHELSIO_T6:
+	case CHELSIO_T7:
 		if (adapter->flags & IS_VF)
 			return FW_T4VF_REGMAP_SIZE;
 		return T5_REGMAP_SIZE;
@@ -2639,6 +2644,638 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
 	};
 
+	static const unsigned int t7_reg_ranges[] = {
+		0x1008, 0x101c,
+		0x1024, 0x10a8,
+		0x10b4, 0x10f8,
+		0x1100, 0x1114,
+		0x111c, 0x112c,
+		0x1138, 0x113c,
+		0x1144, 0x115c,
+		0x1180, 0x1184,
+		0x1190, 0x1194,
+		0x11a0, 0x11a4,
+		0x11b0, 0x11d0,
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+		0x39a1c, 0x39aa8,
+		0x39b00, 0x39ecc,
+		0x3a000, 0x3a004,
+		0x3a050, 0x3a084,
+		0x3a090, 0x3a09c,
+		0x3e000, 0x3e020,
+		0x3e03c, 0x3e05c,
+		0x3e100, 0x3e120,
+		0x3e13c, 0x3e15c,
+		0x3e200, 0x3e220,
+		0x3e23c, 0x3e25c,
+		0x3e300, 0x3e320,
+		0x3e33c, 0x3e35c,
+		0x3f000, 0x3f034,
+		0x3f100, 0x3f130,
+		0x3f200, 0x3f218,
+		0x44000, 0x44014,
+		0x44020, 0x44028,
+		0x44030, 0x44030,
+		0x44100, 0x44114,
+		0x44120, 0x44128,
+		0x44130, 0x44130,
+		0x44200, 0x44214,
+		0x44220, 0x44228,
+		0x44230, 0x44230,
+		0x44300, 0x44314,
+		0x44320, 0x44328,
+		0x44330, 0x44330,
+		0x44400, 0x44414,
+		0x44420, 0x44428,
+		0x44430, 0x44430,
+		0x44500, 0x44514,
+		0x44520, 0x44528,
+		0x44530, 0x44530,
+		0x44714, 0x44718,
+		0x44730, 0x44730,
+		0x447c0, 0x447c0,
+		0x447f0, 0x447f0,
+		0x447f8, 0x447fc,
+		0x45000, 0x45014,
+		0x45020, 0x45028,
+		0x45030, 0x45030,
+		0x45100, 0x45114,
+		0x45120, 0x45128,
+		0x45130, 0x45130,
+		0x45200, 0x45214,
+		0x45220, 0x45228,
+		0x45230, 0x45230,
+		0x45300, 0x45314,
+		0x45320, 0x45328,
+		0x45330, 0x45330,
+		0x45400, 0x45414,
+		0x45420, 0x45428,
+		0x45430, 0x45430,
+		0x45500, 0x45514,
+		0x45520, 0x45528,
+		0x45530, 0x45530,
+		0x45714, 0x45718,
+		0x45730, 0x45730,
+		0x457c0, 0x457c0,
+		0x457f0, 0x457f0,
+		0x457f8, 0x457fc,
+		0x46000, 0x46010,
+		0x46020, 0x46034,
+		0x46040, 0x46050,
+		0x46060, 0x46088,
+		0x47000, 0x4709c,
+		0x470c0, 0x470d4,
+		0x47100, 0x471a8,
+		0x471b0, 0x471e8,
+		0x47200, 0x47210,
+		0x4721c, 0x47230,
+		0x47238, 0x47238,
+		0x47240, 0x472ac,
+		0x472d0, 0x472f4,
+		0x47300, 0x47310,
+		0x47318, 0x47348,
+		0x47350, 0x47354,
+		0x47380, 0x47388,
+		0x47390, 0x47394,
+		0x47400, 0x47448,
+		0x47450, 0x47458,
+		0x47500, 0x4751c,
+		0x47530, 0x4754c,
+		0x47560, 0x4757c,
+		0x47590, 0x475ac,
+		0x47600, 0x47630,
+		0x47640, 0x47644,
+		0x47660, 0x4769c,
+		0x47700, 0x47710,
+		0x47740, 0x47750,
+		0x4775c, 0x4779c,
+		0x477b0, 0x477bc,
+		0x477c4, 0x477c8,
+		0x477d4, 0x477fc,
+		0x48000, 0x48004,
+		0x48018, 0x4801c,
+		0x49304, 0x493f0,
+		0x49400, 0x49410,
+		0x49460, 0x494f4,
+		0x50000, 0x50084,
+		0x50090, 0x500cc,
+		0x50300, 0x50384,
+		0x50400, 0x50404,
+		0x50800, 0x50884,
+		0x50890, 0x508cc,
+		0x50b00, 0x50b84,
+		0x50c00, 0x50c04,
+		0x51000, 0x51020,
+		0x51028, 0x510c4,
+		0x51104, 0x51108,
+		0x51200, 0x51274,
+		0x51300, 0x51324,
+		0x51400, 0x51548,
+		0x51550, 0x51554,
+		0x5155c, 0x51584,
+		0x5158c, 0x515c8,
+		0x515f0, 0x515f4,
+		0x58000, 0x58004,
+		0x58018, 0x5801c,
+		0x59304, 0x593f0,
+		0x59400, 0x59410,
+		0x59460, 0x594f4,
+	};
+
 	u32 *buf_end = (u32 *)(buf + buf_size);
 	const unsigned int *reg_ranges;
 	int reg_ranges_size, range;
@@ -2679,6 +3316,16 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
 		}
 		break;
 
+	case CHELSIO_T7:
+		if (adap->flags & IS_VF) {
+			reg_ranges = t6vf_reg_ranges;
+			reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
+		} else {
+			reg_ranges = t7_reg_ranges;
+			reg_ranges_size = ARRAY_SIZE(t7_reg_ranges);
+		}
+		break;
+
 	default:
 		CH_ERR(adap,
 			"Unsupported chip version %d\n", chip_version);
@@ -3086,6 +3733,56 @@ static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
 	return 0;
 }
 
+/* Flash Layout {start sector, # of sectors} for T4/T5/T6 adapters */
+static const struct t4_flash_loc_entry t4_flash_loc_arr[] = {
+	[FLASH_LOC_EXP_ROM] = { 0, 6 },
+	[FLASH_LOC_IBFT] = { 6, 1 },
+	[FLASH_LOC_BOOTCFG] = { 7, 1 },
+	[FLASH_LOC_FW] = { 8, 16 },
+	[FLASH_LOC_FWBOOTSTRAP] = { 27, 1 },
+	[FLASH_LOC_ISCSI_CRASH] = { 29, 1 },
+	[FLASH_LOC_FCOE_CRASH] = { 30, 1 },
+	[FLASH_LOC_CFG] = { 31, 1 },
+	[FLASH_LOC_CUDBG] = { 32, 32 },
+	[FLASH_LOC_BOOT_AREA] = { 0, 8 }, /* Spans complete Boot Area */
+	[FLASH_LOC_END] = { 64, 0 },
+};
+
+/* Flash Layout {start sector, # of sectors} for T7 adapters */
+static const struct t4_flash_loc_entry t7_flash_loc_arr[] = {
+	[FLASH_LOC_VPD] = { 0, 1 },
+	[FLASH_LOC_FWBOOTSTRAP] = { 1, 1 },
+	[FLASH_LOC_FW] = { 2, 29 },
+	[FLASH_LOC_CFG] = { 31, 1 },
+	[FLASH_LOC_EXP_ROM] = { 32, 15 },
+	[FLASH_LOC_IBFT] = { 47, 1 },
+	[FLASH_LOC_BOOTCFG] = { 48, 1 },
+	[FLASH_LOC_DPU_BOOT] = { 49, 13 },
+	[FLASH_LOC_ISCSI_CRASH] = { 62, 1 },
+	[FLASH_LOC_FCOE_CRASH] = { 63, 1 },
+	[FLASH_LOC_VPD_BACKUP] = { 64, 1 },
+	[FLASH_LOC_FWBOOTSTRAP_BACKUP] = { 65, 1 },
+	[FLASH_LOC_FW_BACKUP] = { 66, 29 },
+	[FLASH_LOC_CFG_BACK] = { 95, 1 },
+	[FLASH_LOC_CUDBG] = { 96, 48 },
+	[FLASH_LOC_CHIP_DUMP] = { 144, 48 },
+	[FLASH_LOC_DPU_AREA] = { 192, 64 },
+	[FLASH_LOC_BOOT_AREA] = { 32, 17 }, /* Spans complete UEFI/PXE Boot Area */
+	[FLASH_LOC_END] = { 256, 0 },
+};
+
+int
+t4_flash_loc_start(struct adapter *adap, enum t4_flash_loc loc,
+    unsigned int *lenp)
+{
+	const struct t4_flash_loc_entry *l = chip_id(adap) >= CHELSIO_T7 ?
+	    &t7_flash_loc_arr[loc] : &t4_flash_loc_arr[loc];
+
+	if (lenp != NULL)
+		*lenp = FLASH_MAX_SIZE(l->nsecs);
+	return (FLASH_START(l->start_sec));
+}
+
 /* serial flash and firmware constants and flash config file constants */
 enum {
 	SF_ATTEMPTS = 10,	/* max retries for SF operations */
@@ -3116,13 +3813,16 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
 		    int lock, u32 *valp)
 {
 	int ret;
+	uint32_t op;
 
 	if (!byte_cnt || byte_cnt > 4)
 		return -EINVAL;
 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
 		return -EBUSY;
-	t4_write_reg(adapter, A_SF_OP,
-		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
+	op = V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1);
+	if (chip_id(adapter) >= CHELSIO_T7)
+		op |= F_QUADREADDISABLE;
+	t4_write_reg(adapter, A_SF_OP, op);
 	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
 	if (!ret)
 		*valp = t4_read_reg(adapter, A_SF_DATA);
@@ -3294,9 +3994,10 @@ unlock:
  */
 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
 {
-	return t4_read_flash(adapter, FLASH_FW_START +
-			     offsetof(struct fw_hdr, fw_ver), 1,
-			     vers, 0);
+	const int start = t4_flash_loc_start(adapter, FLASH_LOC_FW, NULL);
+
+	return t4_read_flash(adapter, start + offsetof(struct fw_hdr, fw_ver),
+	    1, vers, 0);
 }
 
 /**
@@ -3308,8 +4009,10 @@ int t4_get_fw_version(struct adapter *adapter, u32 *vers)
  */
 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
 {
-	return t4_read_flash(adapter, FLASH_FW_START,
-	    sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
+	const int start = t4_flash_loc_start(adapter, FLASH_LOC_FW, NULL);
+
+	return t4_read_flash(adapter, start, sizeof (*hdr) / sizeof (uint32_t),
+	    (uint32_t *)hdr, 1);
 }
 
 /**
@@ -3321,9 +4024,11 @@ int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
  */
 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
 {
-	return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
-			     offsetof(struct fw_hdr, fw_ver), 1,
-			     vers, 0);
+	const int start = t4_flash_loc_start(adapter, FLASH_LOC_FWBOOTSTRAP,
+	    NULL);
+
+	return t4_read_flash(adapter, start + offsetof(struct fw_hdr, fw_ver),
+	    1, vers, 0);
 }
 
 /**
@@ -3335,9 +4040,10 @@ int t4_get_bs_version(struct adapter *adapter, u32 *vers)
  */
 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
 {
-	return t4_read_flash(adapter, FLASH_FW_START +
-			     offsetof(struct fw_hdr, tp_microcode_ver),
-			     1, vers, 0);
+	const int start = t4_flash_loc_start(adapter, FLASH_LOC_FW, NULL);
+
+	return t4_read_flash(adapter, start +
+	    offsetof(struct fw_hdr, tp_microcode_ver), 1, vers, 0);
 }
 
 /**
@@ -3359,10 +4065,10 @@ int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
 	u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
 					   sizeof(u32))];
 	int ret;
+	const int start = t4_flash_loc_start(adapter, FLASH_LOC_EXP_ROM, NULL);
 
-	ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
-			    ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
-			    0);
+	ret = t4_read_flash(adapter, start, ARRAY_SIZE(exprom_header_buf),
+	    exprom_header_buf, 0);
 	if (ret)
 		return ret;
 
@@ -3520,16 +4226,20 @@ int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
  *	File is stored, or an error if the device FLASH is too small to contain
  *	a Firmware Configuration File.
  */
-int t4_flash_cfg_addr(struct adapter *adapter)
+int t4_flash_cfg_addr(struct adapter *adapter, unsigned int *lenp)
 {
+	unsigned int len = 0;
+	const int cfg_start = t4_flash_loc_start(adapter, FLASH_LOC_CFG, &len);
+
 	/*
 	 * If the device FLASH isn't large enough to hold a Firmware
 	 * Configuration File, return an error.
 	 */
-	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
+	if (adapter->params.sf_size < cfg_start + len)
 		return -ENOSPC;
-
-	return FLASH_CFG_START;
+	if (lenp != NULL)
+		*lenp = len;
+	return (cfg_start);
 }
 
 /*
@@ -3547,7 +4257,8 @@ static int t4_fw_matches_chip(struct adapter *adap,
 	 */
 	if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
 	    (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
-	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
+	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6) ||
+	    (is_t7(adap) && hdr->chip == FW_HDR_CHIP_T7))
 		return 1;
 
 	CH_ERR(adap,
@@ -3572,20 +4283,15 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
 	u8 first_page[SF_PAGE_SIZE];
 	const u32 *p = (const u32 *)fw_data;
 	const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
-	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
 	unsigned int fw_start_sec;
 	unsigned int fw_start;
 	unsigned int fw_size;
+	enum t4_flash_loc loc;
 
-	if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
-		fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
-		fw_start = FLASH_FWBOOTSTRAP_START;
-		fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
-	} else {
-		fw_start_sec = FLASH_FW_START_SEC;
- 		fw_start = FLASH_FW_START;
-		fw_size = FLASH_FW_MAX_SIZE;
-	}
+	loc = ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP ?
+	    FLASH_LOC_FWBOOTSTRAP : FLASH_LOC_FW;
+	fw_start = t4_flash_loc_start(adap, loc, &fw_size);
+	fw_start_sec = fw_start / SF_SEC_SIZE;
 
 	if (!size) {
 		CH_ERR(adap, "FW image has no data\n");
@@ -3618,7 +4324,7 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
 		return -EINVAL;
 	}
 
-	i = DIV_ROUND_UP(size, sf_sec_size);	/* # of sectors spanned */
+	i = DIV_ROUND_UP(size, SF_SEC_SIZE);	/* # of sectors spanned */
 	ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
 	if (ret)
 		goto out;
@@ -3672,7 +4378,7 @@ int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
 	c.param[0].mnem =
 	    cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
-	c.param[0].val = (__force __be32)op;
+	c.param[0].val = cpu_to_be32(op);
 
 	return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
 }
@@ -3922,15 +4628,12 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
 				 * speed and let the firmware pick one.
 				 */
 				fec |= FW_PORT_CAP32_FORCE_FEC;
-				if (speed & FW_PORT_CAP32_SPEED_100G) {
+				if (speed & FW_PORT_CAP32_SPEED_25G) {
 					fec |= FW_PORT_CAP32_FEC_RS;
-					fec |= FW_PORT_CAP32_FEC_NO_FEC;
-				} else if (speed & FW_PORT_CAP32_SPEED_50G) {
 					fec |= FW_PORT_CAP32_FEC_BASER_RS;
 					fec |= FW_PORT_CAP32_FEC_NO_FEC;
 				} else {
 					fec |= FW_PORT_CAP32_FEC_RS;
-					fec |= FW_PORT_CAP32_FEC_BASER_RS;
 					fec |= FW_PORT_CAP32_FEC_NO_FEC;
 				}
 			} else {
@@ -3948,12 +4651,9 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
 				 * the potential top speed.  Request the best
 				 * FEC at that speed instead.
 				 */
-				if (speed & FW_PORT_CAP32_SPEED_100G) {
-					if (fec == FW_PORT_CAP32_FEC_BASER_RS)
-						fec = FW_PORT_CAP32_FEC_RS;
-				} else if (speed & FW_PORT_CAP32_SPEED_50G) {
-					if (fec == FW_PORT_CAP32_FEC_RS)
-						fec = FW_PORT_CAP32_FEC_BASER_RS;
+				if ((speed & FW_PORT_CAP32_SPEED_25G) == 0 &&
+				    fec == FW_PORT_CAP32_FEC_BASER_RS) {
+					fec = FW_PORT_CAP32_FEC_RS;
 				}
 			}
 		} else {
@@ -4925,6 +5625,15 @@ static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
 		.details = mps_trc_intr_details,
 		.actions = NULL,
 	};
+	static const struct intr_info t7_mps_trc_intr_info = {
+		.name = "T7_MPS_TRC_INT_CAUSE",
+		.cause_reg = A_T7_MPS_TRC_INT_CAUSE,
+		.enable_reg = A_T7_MPS_TRC_INT_ENABLE,
+		.fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
+		.flags = 0,
+		.details = mps_trc_intr_details,
+		.actions = NULL,
+	};
 	static const struct intr_details mps_stat_sram_intr_details[] = {
 		{ 0xffffffff, "MPS statistics SRAM parity error" },
 		{ 0 }
@@ -4998,7 +5707,10 @@ static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
 	fatal = false;
 	fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
 	fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
-	fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
+	if (chip_id(adap) > CHELSIO_T6)
+		fatal |= t4_handle_intr(adap, &t7_mps_trc_intr_info, 0, verbose);
+	else
+		fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
 	fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
 	fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
 	fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
@@ -5225,7 +5937,7 @@ static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
 		ii.flags = 0;
 		ii.details = mac_intr_details;
 		ii.actions = NULL;
-	} else {
+	} else if (chip_id(adap) < CHELSIO_T7) {
 		snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
 		ii.name = &name[0];
 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
@@ -5234,10 +5946,29 @@ static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
 		ii.flags = 0;
 		ii.details = mac_intr_details;
 		ii.actions = NULL;
+	} else {
+		snprintf(name, sizeof(name), "T7_MAC_PORT%u_INT_CAUSE", port);
+		ii.name = &name[0];
+		ii.cause_reg = T7_PORT_REG(port, A_T7_MAC_PORT_INT_CAUSE);
+		ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_INT_EN);
+		ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
+		ii.flags = 0;
+		ii.details = mac_intr_details;
+		ii.actions = NULL;
 	}
 	fatal |= t4_handle_intr(adap, &ii, 0, verbose);
 
-	if (chip_id(adap) >= CHELSIO_T5) {
+	if (chip_id(adap) > CHELSIO_T6) {
+		snprintf(name, sizeof(name), "T7_MAC_PORT%u_PERR_INT_CAUSE", port);
+		ii.name = &name[0];
+		ii.cause_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_CAUSE);
+		ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_EN);
+		ii.fatal = 0;
+		ii.flags = 0;
+		ii.details = NULL;
+		ii.actions = NULL;
+		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+	} else if (chip_id(adap) >= CHELSIO_T5) {
 		snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
 		ii.name = &name[0];
 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
@@ -5249,7 +5980,17 @@ static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
 		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
 	}
 
-	if (chip_id(adap) >= CHELSIO_T6) {
+	if (chip_id(adap) > CHELSIO_T6) {
+		snprintf(name, sizeof(name), "T7_MAC_PORT%u_PERR_INT_CAUSE_100G", port);
+		ii.name = &name[0];
+		ii.cause_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_CAUSE_100G);
+		ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_EN_100G);
+		ii.fatal = 0;
+		ii.flags = 0;
+		ii.details = NULL;
+		ii.actions = NULL;
+		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
+	} else if (is_t6(adap)) {
 		snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
 		ii.name = &name[0];
 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
@@ -5346,13 +6087,42 @@ bool t4_slow_intr_handler(struct adapter *adap, bool verbose)
 		{ F_CIM, "CIM" },
 		{ 0 }
 	};
-	static const struct intr_info pl_perr_cause = {
+	static const struct intr_details t7_pl_intr_details[] = {
+		{ F_T7_MC1, "MC1" },
+		{ F_T7_ULP_TX, "ULP TX" },
+		{ F_T7_SGE, "SGE" },
+		{ F_T7_CPL_SWITCH, "CPL Switch" },
+		{ F_T7_ULP_RX, "ULP RX" },
+		{ F_T7_PM_RX, "PM RX" },
+		{ F_T7_PM_TX, "PM TX" },
+		{ F_T7_MA, "MA" },
+		{ F_T7_TP, "TP" },
+		{ F_T7_LE, "LE" },
+		{ F_T7_EDC1, "EDC1" },
+		{ F_T7_EDC0, "EDC0" },
+		{ F_T7_MC0, "MC0" },
+		{ F_T7_PCIE, "PCIE" },
+		{ F_MAC3, "MAC3" },
+		{ F_MAC2, "MAC2" },
+		{ F_MAC1, "MAC1" },
+		{ F_MAC0, "MAC0" },
+		{ F_SMB, "SMB" },
+		{ F_PL, "PL" },
+		{ F_NCSI, "NC-SI" },
+		{ F_MPS, "MPS" },
+		{ F_DBG, "DBG" },
+		{ F_I2CM, "I2CM" },
+		{ F_MI, "MI" },
+		{ F_CIM, "CIM" },
+		{ 0 }
+	};
+	struct intr_info pl_perr_cause = {
 		.name = "PL_PERR_CAUSE",
 		.cause_reg = A_PL_PERR_CAUSE,
 		.enable_reg = A_PL_PERR_ENABLE,
 		.fatal = 0xffffffff,
-		.flags = 0,
-		.details = pl_intr_details,
+		.flags = NONFATAL_IF_DISABLED,
+		.details = NULL,
 		.actions = NULL,
 	};
 	static const struct intr_action pl_intr_action[] = {
@@ -5381,17 +6151,53 @@ bool t4_slow_intr_handler(struct adapter *adap, bool verbose)
 		{ F_CIM, -1, cim_intr_handler },
 		{ 0 }
 	};
-	static const struct intr_info pl_intr_info = {
+	static const struct intr_action t7_pl_intr_action[] = {
+		{ F_T7_ULP_TX, -1, ulptx_intr_handler },
+		{ F_T7_SGE, -1, sge_intr_handler },
+		{ F_T7_CPL_SWITCH, -1, cplsw_intr_handler },
+		{ F_T7_ULP_RX, -1, ulprx_intr_handler },
+		{ F_T7_PM_RX, -1, pmrx_intr_handler},
+		{ F_T7_PM_TX, -1, pmtx_intr_handler},
+		{ F_T7_MA, -1, ma_intr_handler },
+		{ F_T7_TP, -1, tp_intr_handler },
+		{ F_T7_LE, -1, le_intr_handler },
+		{ F_T7_EDC1, MEM_EDC1, mem_intr_handler },
+		{ F_T7_EDC0, MEM_EDC0, mem_intr_handler },
+		{ F_T7_MC1, MEM_MC1, mem_intr_handler },
+		{ F_T7_MC0, MEM_MC0, mem_intr_handler },
+		{ F_T7_PCIE, -1, pcie_intr_handler },
+		{ F_MAC3, 3, mac_intr_handler},
+		{ F_MAC2, 2, mac_intr_handler},
+		{ F_MAC1, 1, mac_intr_handler},
+		{ F_MAC0, 0, mac_intr_handler},
+		{ F_SMB, -1, smb_intr_handler},
+		{ F_PL, -1, plpl_intr_handler },
+		{ F_NCSI, -1, ncsi_intr_handler},
+		{ F_MPS, -1, mps_intr_handler },
+		{ F_CIM, -1, cim_intr_handler },
+		{ 0 }
+	};
+	struct intr_info pl_intr_info = {
 		.name = "PL_INT_CAUSE",
 		.cause_reg = A_PL_INT_CAUSE,
 		.enable_reg = A_PL_INT_ENABLE,
 		.fatal = 0,
 		.flags = 0,
-		.details = pl_intr_details,
-		.actions = pl_intr_action,
+		.details = NULL,
+		.actions = NULL,
 	};
 	u32 perr;
 
+	if (chip_id(adap) >= CHELSIO_T7) {
+		pl_perr_cause.details = t7_pl_intr_details;
+		pl_intr_info.details = t7_pl_intr_details;
+		pl_intr_info.actions = t7_pl_intr_action;
+	} else {
+		pl_perr_cause.details = pl_intr_details;
+		pl_intr_info.details = pl_intr_details;
+		pl_intr_info.actions = pl_intr_action;
+	}
+
 	perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
 	if (verbose || perr != 0) {
 		t4_show_intr_info(adap, &pl_perr_cause, perr);
@@ -5421,19 +6227,20 @@ bool t4_slow_intr_handler(struct adapter *adap, bool verbose)
  */
 void t4_intr_enable(struct adapter *adap)
 {
-	u32 val = 0;
+	u32 mask, val;
 
 	if (chip_id(adap) <= CHELSIO_T5)
-		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
+		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT |
+		    F_DBFIFO_LP_INT;
 	else
 		val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
 	val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
 	    F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
 	    F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
 	    F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
-	    F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
-	    F_EGRESS_SIZE_ERR;
-	t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
+	    F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_EGRESS_SIZE_ERR;
+	mask = val;
+	t4_set_reg_field(adap, A_SGE_INT_ENABLE3, mask, val);
 	t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
 	t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
 	t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
@@ -6184,6 +6991,11 @@ void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
 {
 	t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
 		       sleep_ok);
+
+	if (chip_id(adap) >= CHELSIO_T7)
+		/* read RDMA stats IN and OUT for all ports at once */
+		t4_tp_mib_read(adap, &st->pkts_in[0], 28, A_TP_MIB_RDMA_IN_PKT_0,
+			       sleep_ok);
 }
 
 /**
@@ -6564,16 +7376,24 @@ void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
     int idx, int enable)
 {
-	int i, ofst = idx * 4;
+	int i, ofst;
+	u32 match_ctl_a, match_ctl_b;
 	u32 data_reg, mask_reg, cfg;
 	u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
 
 	if (idx < 0 || idx >= NTRACE)
 		return -EINVAL;
 
+	if (chip_id(adap) >= CHELSIO_T7) {
+		match_ctl_a = T7_MPS_TRC_FILTER_MATCH_CTL_A(idx);
+		match_ctl_b = T7_MPS_TRC_FILTER_MATCH_CTL_B(idx);
+	} else {
+		match_ctl_a = MPS_TRC_FILTER_MATCH_CTL_A(idx);
+		match_ctl_b = MPS_TRC_FILTER_MATCH_CTL_B(idx);
+	}
+
 	if (tp == NULL || !enable) {
-		t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
-		    enable ? en : 0);
+		t4_set_reg_field(adap, match_ctl_a, en, enable ? en : 0);
 		return 0;
 	}
 
@@ -6610,22 +7430,20 @@ int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
 		return -EINVAL;
 
 	/* stop the tracer we'll be changing */
-	t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
+	t4_set_reg_field(adap, match_ctl_a, en, 0);
 
-	idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
-	data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
-	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
+	ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
+	data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
+	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
 
 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
 		t4_write_reg(adap, data_reg, tp->data[i]);
 		t4_write_reg(adap, mask_reg, ~tp->mask[i]);
 	}
-	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
-		     V_TFCAPTUREMAX(tp->snap_len) |
+	t4_write_reg(adap, match_ctl_b, V_TFCAPTUREMAX(tp->snap_len) |
 		     V_TFMINPKTSIZE(tp->min_len));
-	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
-		     V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
-		     (is_t4(adap) ?
+	t4_write_reg(adap, match_ctl_a, V_TFOFFSET(tp->skip_ofst) |
+		     V_TFLENGTH(tp->skip_len) | en | (is_t4(adap) ?
 		     V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
 		     V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
 
@@ -6645,11 +7463,16 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
 			 int *enabled)
 {
 	u32 ctla, ctlb;
-	int i, ofst = idx * 4;
+	int i, ofst;
 	u32 data_reg, mask_reg;
 
-	ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
-	ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
+	if (chip_id(adap) >= CHELSIO_T7) {
+		ctla = t4_read_reg(adap, T7_MPS_TRC_FILTER_MATCH_CTL_A(idx));
+		ctlb = t4_read_reg(adap, T7_MPS_TRC_FILTER_MATCH_CTL_B(idx));
+	} else {
+		ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A(idx));
+		ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B(idx));
+	}
 
 	if (is_t4(adap)) {
 		*enabled = !!(ctla & F_TFEN);
@@ -6676,6 +7499,37 @@ void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
 }
 
 /**
+ *	t4_set_trace_rss_control - configure the trace rss control register
+ *	@adap: the adapter
+ *	@chan: the channel number for RSS control
+ *	@qid: queue number
+ *
+ *	Configures the MPS tracing RSS control parameter for specified
+ *	@chan channel and @qid queue number.
+ */
+void t4_set_trace_rss_control(struct adapter *adap, u8 chan, u16 qid)
+{
+	u32 mps_trc_rss_control;
+
+	switch (chip_id(adap)) {
+	case CHELSIO_T4:
+		mps_trc_rss_control = A_MPS_TRC_RSS_CONTROL;
+		break;
+	case CHELSIO_T5:
+	case CHELSIO_T6:
+		mps_trc_rss_control = A_MPS_T5_TRC_RSS_CONTROL;
+		break;
+	case CHELSIO_T7:
+	default:
+		mps_trc_rss_control = A_T7_MPS_T5_TRC_RSS_CONTROL;
+		break;
+	}
+
+	t4_write_reg(adap, mps_trc_rss_control,
+		     V_RSSCONTROL(chan) | V_QUEUENUMBER(qid));
+}
+
+/**
  *	t4_pmtx_get_stats - returns the HW stats from PMTX
  *	@adap: the adapter
  *	@cnt: where to store the count statistics
@@ -6696,6 +7550,8 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
 		else {
 			t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
 					 A_PM_TX_DBG_DATA, data, 2,
+					 chip_id(adap) >= CHELSIO_T7 ?
+					 A_T7_PM_TX_DBG_STAT_MSB :
 					 A_PM_TX_DBG_STAT_MSB);
 			cycles[i] = (((u64)data[0] << 32) | data[1]);
 		}
@@ -6730,6 +7586,25 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
 }
 
 /**
+ * t4_pmrx_cache_get_stats - returns the HW PMRX cache stats
+ * @adap: the adapter
+ * @stats: where to store the statistics
+ *
+ * Returns performance statistics of PMRX cache.
+ */
+void t4_pmrx_cache_get_stats(struct adapter *adap, u32 stats[])
+{
+	u8 i, j;
+
+	for (i = 0, j = 0; i < T7_PM_RX_CACHE_NSTATS / 3; i++, j += 3) {
+		t4_write_reg(adap, A_PM_RX_STAT_CONFIG, 0x100 + i);
+		stats[j] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
+		t4_read_indirect(adap, A_PM_RX_DBG_CTRL, A_PM_RX_DBG_DATA,
+				 &stats[j + 1], 2, A_PM_RX_DBG_STAT_MSB);
+	}
+}
+
+/**
  *	t4_get_mps_bg_map - return the buffer groups associated with a port
  *	@adap: the adapter
  *	@idx: the port index
@@ -6762,11 +7637,24 @@ static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
 	const u32 n = adap->params.nports;
 	const u32 all_chan = (1 << adap->chip_params->nchan) - 1;
 
-	if (n == 1)
-		return idx == 0 ? all_chan : 0;
-	if (n == 2 && chip_id(adap) <= CHELSIO_T5)
-		return idx < 2 ? (3 << (2 * idx)) : 0;
-	return 1 << idx;
+	switch (adap->params.tp.lb_mode) {
+	case 0:
+		if (n == 1)
+			return (all_chan);
+		if (n == 2 && chip_id(adap) <= CHELSIO_T5)
+			return (3 << (2 * idx));
+		return (1 << idx);
+	case 1:
+		MPASS(n == 1);
+		return (all_chan);
+	case 2:
+		MPASS(n <= 2);
+		return (3 << (2 * idx));
+	default:
+		CH_ERR(adap, "Unsupported LB mode %d\n",
+		    adap->params.tp.lb_mode);
+		return (0);
+	}
 }
 
 /*
@@ -6784,6 +7672,8 @@ static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx)
  */
 static unsigned int t4_get_tx_c_chan(struct adapter *adap, int idx)
 {
+	if (adap->params.tx_tp_ch_map != UINT32_MAX)
+		return (adap->params.tx_tp_ch_map >> (8 * idx)) & 0xff;
 	return idx;
 }
 
@@ -6856,79 +7746,89 @@ void t4_get_port_stats_offset(struct adapter *adap, int idx,
  */
 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 {
-	struct port_info *pi = adap->port[idx];
-	u32 bgmap = pi->mps_bg_map;
-	u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
+	struct port_info *pi;
+	int port_id, tx_chan;
+	u32 bgmap, stat_ctl;
+
+	port_id  = adap->port_map[idx];
+	MPASS(port_id >= 0 && port_id <= adap->params.nports);
+	pi = adap->port[port_id];
 
 #define GET_STAT(name) \
 	t4_read_reg64(adap, \
-	    t4_port_reg(adap, pi->tx_chan, A_MPS_PORT_STAT_##name##_L));
-#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
+	    t4_port_reg(adap, tx_chan, A_MPS_PORT_STAT_##name##_L));
+	memset(p, 0, sizeof(*p));
+	for (tx_chan = pi->tx_chan;
+	    tx_chan < pi->tx_chan + adap->params.tp.lb_nchan; tx_chan++) {
+		p->tx_pause		+= GET_STAT(TX_PORT_PAUSE);
+		p->tx_octets		+= GET_STAT(TX_PORT_BYTES);
+		p->tx_frames		+= GET_STAT(TX_PORT_FRAMES);
+		p->tx_bcast_frames	+= GET_STAT(TX_PORT_BCAST);
+		p->tx_mcast_frames	+= GET_STAT(TX_PORT_MCAST);
+		p->tx_ucast_frames	+= GET_STAT(TX_PORT_UCAST);
+		p->tx_error_frames	+= GET_STAT(TX_PORT_ERROR);
+		p->tx_frames_64		+= GET_STAT(TX_PORT_64B);
+		p->tx_frames_65_127	+= GET_STAT(TX_PORT_65B_127B);
+		p->tx_frames_128_255	+= GET_STAT(TX_PORT_128B_255B);
+		p->tx_frames_256_511	+= GET_STAT(TX_PORT_256B_511B);
+		p->tx_frames_512_1023	+= GET_STAT(TX_PORT_512B_1023B);
+		p->tx_frames_1024_1518	+= GET_STAT(TX_PORT_1024B_1518B);
+		p->tx_frames_1519_max	+= GET_STAT(TX_PORT_1519B_MAX);
+		p->tx_drop		+= GET_STAT(TX_PORT_DROP);
+		p->tx_ppp0		+= GET_STAT(TX_PORT_PPP0);
+		p->tx_ppp1		+= GET_STAT(TX_PORT_PPP1);
+		p->tx_ppp2		+= GET_STAT(TX_PORT_PPP2);
+		p->tx_ppp3		+= GET_STAT(TX_PORT_PPP3);
+		p->tx_ppp4		+= GET_STAT(TX_PORT_PPP4);
+		p->tx_ppp5		+= GET_STAT(TX_PORT_PPP5);
+		p->tx_ppp6		+= GET_STAT(TX_PORT_PPP6);
+		p->tx_ppp7		+= GET_STAT(TX_PORT_PPP7);
+
+		p->rx_pause		+= GET_STAT(RX_PORT_PAUSE);
+		p->rx_octets		+= GET_STAT(RX_PORT_BYTES);
+		p->rx_frames		+= GET_STAT(RX_PORT_FRAMES);
+		p->rx_bcast_frames	+= GET_STAT(RX_PORT_BCAST);
+		p->rx_mcast_frames	+= GET_STAT(RX_PORT_MCAST);
+		p->rx_ucast_frames	+= GET_STAT(RX_PORT_UCAST);
+		p->rx_too_long		+= GET_STAT(RX_PORT_MTU_ERROR);
+		p->rx_jabber		+= GET_STAT(RX_PORT_MTU_CRC_ERROR);
+		p->rx_len_err		+= GET_STAT(RX_PORT_LEN_ERROR);
+		p->rx_symbol_err	+= GET_STAT(RX_PORT_SYM_ERROR);
+		p->rx_runt		+= GET_STAT(RX_PORT_LESS_64B);
+		p->rx_frames_64		+= GET_STAT(RX_PORT_64B);
+		p->rx_frames_65_127	+= GET_STAT(RX_PORT_65B_127B);
+		p->rx_frames_128_255	+= GET_STAT(RX_PORT_128B_255B);
+		p->rx_frames_256_511	+= GET_STAT(RX_PORT_256B_511B);
+		p->rx_frames_512_1023	+= GET_STAT(RX_PORT_512B_1023B);
+		p->rx_frames_1024_1518	+= GET_STAT(RX_PORT_1024B_1518B);
+		p->rx_frames_1519_max	+= GET_STAT(RX_PORT_1519B_MAX);
+		p->rx_ppp0		+= GET_STAT(RX_PORT_PPP0);
+		p->rx_ppp1		+= GET_STAT(RX_PORT_PPP1);
+		p->rx_ppp2		+= GET_STAT(RX_PORT_PPP2);
+		p->rx_ppp3		+= GET_STAT(RX_PORT_PPP3);
+		p->rx_ppp4		+= GET_STAT(RX_PORT_PPP4);
+		p->rx_ppp5		+= GET_STAT(RX_PORT_PPP5);
+		p->rx_ppp6		+= GET_STAT(RX_PORT_PPP6);
+		p->rx_ppp7		+= GET_STAT(RX_PORT_PPP7);
+		if (!is_t6(adap)) {
+			MPASS(pi->fcs_reg == A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L);
+			p->rx_fcs_err	+= GET_STAT(RX_PORT_CRC_ERROR);
+		}
+	}
+#undef GET_STAT
 
-	p->tx_pause		= GET_STAT(TX_PORT_PAUSE);
-	p->tx_octets		= GET_STAT(TX_PORT_BYTES);
-	p->tx_frames		= GET_STAT(TX_PORT_FRAMES);
-	p->tx_bcast_frames	= GET_STAT(TX_PORT_BCAST);
-	p->tx_mcast_frames	= GET_STAT(TX_PORT_MCAST);
-	p->tx_ucast_frames	= GET_STAT(TX_PORT_UCAST);
-	p->tx_error_frames	= GET_STAT(TX_PORT_ERROR);
-	p->tx_frames_64		= GET_STAT(TX_PORT_64B);
-	p->tx_frames_65_127	= GET_STAT(TX_PORT_65B_127B);
-	p->tx_frames_128_255	= GET_STAT(TX_PORT_128B_255B);
-	p->tx_frames_256_511	= GET_STAT(TX_PORT_256B_511B);
-	p->tx_frames_512_1023	= GET_STAT(TX_PORT_512B_1023B);
-	p->tx_frames_1024_1518	= GET_STAT(TX_PORT_1024B_1518B);
-	p->tx_frames_1519_max	= GET_STAT(TX_PORT_1519B_MAX);
-	p->tx_drop		= GET_STAT(TX_PORT_DROP);
-	p->tx_ppp0		= GET_STAT(TX_PORT_PPP0);
-	p->tx_ppp1		= GET_STAT(TX_PORT_PPP1);
-	p->tx_ppp2		= GET_STAT(TX_PORT_PPP2);
-	p->tx_ppp3		= GET_STAT(TX_PORT_PPP3);
-	p->tx_ppp4		= GET_STAT(TX_PORT_PPP4);
-	p->tx_ppp5		= GET_STAT(TX_PORT_PPP5);
-	p->tx_ppp6		= GET_STAT(TX_PORT_PPP6);
-	p->tx_ppp7		= GET_STAT(TX_PORT_PPP7);
+	if (is_t6(adap) && pi->fcs_reg != -1)
+		p->rx_fcs_err = t4_read_reg64(adap,
+		    t4_port_reg(adap, pi->tx_chan, pi->fcs_reg)) - pi->fcs_base;
 
 	if (chip_id(adap) >= CHELSIO_T5) {
+		stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
 		if (stat_ctl & F_COUNTPAUSESTATTX) {
 			p->tx_frames -= p->tx_pause;
 			p->tx_octets -= p->tx_pause * 64;
 		}
 		if (stat_ctl & F_COUNTPAUSEMCTX)
 			p->tx_mcast_frames -= p->tx_pause;
-	}
-
-	p->rx_pause		= GET_STAT(RX_PORT_PAUSE);
-	p->rx_octets		= GET_STAT(RX_PORT_BYTES);
-	p->rx_frames		= GET_STAT(RX_PORT_FRAMES);
-	p->rx_bcast_frames	= GET_STAT(RX_PORT_BCAST);
-	p->rx_mcast_frames	= GET_STAT(RX_PORT_MCAST);
-	p->rx_ucast_frames	= GET_STAT(RX_PORT_UCAST);
-	p->rx_too_long		= GET_STAT(RX_PORT_MTU_ERROR);
-	p->rx_jabber		= GET_STAT(RX_PORT_MTU_CRC_ERROR);
-	p->rx_len_err		= GET_STAT(RX_PORT_LEN_ERROR);
-	p->rx_symbol_err	= GET_STAT(RX_PORT_SYM_ERROR);
-	p->rx_runt		= GET_STAT(RX_PORT_LESS_64B);
-	p->rx_frames_64		= GET_STAT(RX_PORT_64B);
-	p->rx_frames_65_127	= GET_STAT(RX_PORT_65B_127B);
-	p->rx_frames_128_255	= GET_STAT(RX_PORT_128B_255B);
-	p->rx_frames_256_511	= GET_STAT(RX_PORT_256B_511B);
-	p->rx_frames_512_1023	= GET_STAT(RX_PORT_512B_1023B);
-	p->rx_frames_1024_1518	= GET_STAT(RX_PORT_1024B_1518B);
-	p->rx_frames_1519_max	= GET_STAT(RX_PORT_1519B_MAX);
-	p->rx_ppp0		= GET_STAT(RX_PORT_PPP0);
-	p->rx_ppp1		= GET_STAT(RX_PORT_PPP1);
-	p->rx_ppp2		= GET_STAT(RX_PORT_PPP2);
-	p->rx_ppp3		= GET_STAT(RX_PORT_PPP3);
-	p->rx_ppp4		= GET_STAT(RX_PORT_PPP4);
-	p->rx_ppp5		= GET_STAT(RX_PORT_PPP5);
-	p->rx_ppp6		= GET_STAT(RX_PORT_PPP6);
-	p->rx_ppp7		= GET_STAT(RX_PORT_PPP7);
-
-	if (pi->fcs_reg != -1)
-		p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base;
-
-	if (chip_id(adap) >= CHELSIO_T5) {
 		if (stat_ctl & F_COUNTPAUSESTATRX) {
 			p->rx_frames -= p->rx_pause;
 			p->rx_octets -= p->rx_pause * 64;
@@ -6937,6 +7837,8 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 			p->rx_mcast_frames -= p->rx_pause;
 	}
 
+#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
+	bgmap = pi->mps_bg_map;
 	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
 	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
 	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
@@ -6945,8 +7847,6 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
 	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
 	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
 	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
-
-#undef GET_STAT
 #undef GET_STAT_COM
 }
 
@@ -7016,10 +7916,14 @@ void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
 		mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
 		mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
-	} else {
+	} else if (chip_id(adap) < CHELSIO_T7) {
 		mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
 		mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
+	} else {
+		mag_id_reg_l = T7_PORT_REG(port, A_T7_MAC_PORT_MAGIC_MACID_LO);
+		mag_id_reg_h = T7_PORT_REG(port, A_T7_MAC_PORT_MAGIC_MACID_HI);
+		port_cfg_reg = T7_PORT_REG(port, A_MAC_PORT_CFG2);
 	}
 
 	if (addr) {
@@ -7056,8 +7960,10 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
 
 	if (is_t4(adap))
 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
-	else
+	else if (chip_id(adap) < CHELSIO_T7)
 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
+	else
+		port_cfg_reg = T7_PORT_REG(port, A_MAC_PORT_CFG2);
 
 	if (!enable) {
 		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
@@ -7348,6 +8254,7 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
 		break;
 
 	case CHELSIO_T6:
+	case CHELSIO_T7:
 		sge_idma_decode = (const char * const *)t6_decode;
 		sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
 		break;
@@ -8964,7 +9871,7 @@ static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
 	    F_FW_CMD_REQUEST | F_FW_CMD_READ |
-	    V_FW_PORT_CMD_PORTID(pi->tx_chan));
+	    V_FW_PORT_CMD_PORTID(pi->hw_port));
 	action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
 	    FW_PORT_ACTION_GET_PORT_INFO;
 	cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
@@ -8996,16 +9903,12 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
 	    (action == FW_PORT_ACTION_GET_PORT_INFO ||
 	    action == FW_PORT_ACTION_GET_PORT_INFO32)) {
 		/* link/module state change message */
-		int i;
-		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
-		struct port_info *pi = NULL;
-
-		for_each_port(adap, i) {
-			pi = adap2pinfo(adap, i);
-			if (pi->tx_chan == chan)
-				break;
-		}
+		int hw_port = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
+		int port_id = adap->port_map[hw_port];
+		struct port_info *pi;
 
+		MPASS(port_id >= 0 && port_id < adap->params.nports);
+		pi = adap->port[port_id];
 		PORT_LOCK(pi);
 		handle_port_info(pi, p, action, &mod_changed, &link_changed);
 		PORT_UNLOCK(pi);
@@ -9159,14 +10062,15 @@ int t4_get_flash_params(struct adapter *adapter)
 	}
 
 	/* If we didn't recognize the FLASH part, that's no real issue: the
-	 * Hardware/Software contract says that Hardware will _*ALWAYS*_
-	 * use a FLASH part which is at least 4MB in size and has 64KB
-	 * sectors.  The unrecognized FLASH part is likely to be much larger
-	 * than 4MB, but that's all we really need.
+	 * Hardware/Software contract says that Hardware will _*ALWAYS*_ use a
+	 * FLASH part which has 64KB sectors and is at least 4MB or 16MB in
+	 * size, depending on the board.
 	 */
 	if (size == 0) {
-		CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
-		size = 1 << 22;
+		size = chip_id(adapter) >= CHELSIO_T7 ? 16 : 4;
+		CH_WARN(adapter, "Unknown Flash Part %#x, assuming %uMB\n",
+		    flashid, size);
+		size <<= 20;
 	}
 
 	/*
@@ -9212,11 +10116,14 @@ const struct chip_params *t4_get_chip_params(int chipid)
 			.pm_stats_cnt = PM_NSTATS,
 			.cng_ch_bits_log = 2,
 			.nsched_cls = 15,
+			.cim_num_ibq = CIM_NUM_IBQ,
 			.cim_num_obq = CIM_NUM_OBQ,
 			.filter_opt_len = FILTER_OPT_LEN,
+			.filter_num_opt = S_FT_LAST + 1,
 			.mps_rplc_size = 128,
 			.vfcount = 128,
 			.sge_fl_db = F_DBPRIO,
+			.sge_ctxt_size = SGE_CTXT_SIZE,
 			.mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
 			.rss_nentries = RSS_NENTRIES,
 			.cim_la_size = CIMLA_SIZE,
@@ -9227,11 +10134,14 @@ const struct chip_params *t4_get_chip_params(int chipid)
 			.pm_stats_cnt = PM_NSTATS,
 			.cng_ch_bits_log = 2,
 			.nsched_cls = 16,
+			.cim_num_ibq = CIM_NUM_IBQ,
 			.cim_num_obq = CIM_NUM_OBQ_T5,
 			.filter_opt_len = T5_FILTER_OPT_LEN,
+			.filter_num_opt = S_FT_LAST + 1,
 			.mps_rplc_size = 128,
 			.vfcount = 128,
 			.sge_fl_db = F_DBPRIO | F_DBTYPE,
+			.sge_ctxt_size = SGE_CTXT_SIZE,
 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
 			.rss_nentries = RSS_NENTRIES,
 			.cim_la_size = CIMLA_SIZE,
@@ -9242,15 +10152,36 @@ const struct chip_params *t4_get_chip_params(int chipid)
 			.pm_stats_cnt = T6_PM_NSTATS,
 			.cng_ch_bits_log = 3,
 			.nsched_cls = 16,
+			.cim_num_ibq = CIM_NUM_IBQ,
 			.cim_num_obq = CIM_NUM_OBQ_T5,
 			.filter_opt_len = T5_FILTER_OPT_LEN,
+			.filter_num_opt = S_FT_LAST + 1,
 			.mps_rplc_size = 256,
 			.vfcount = 256,
 			.sge_fl_db = 0,
+			.sge_ctxt_size = SGE_CTXT_SIZE,
 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
 			.rss_nentries = T6_RSS_NENTRIES,
 			.cim_la_size = CIMLA_SIZE_T6,
 		},
+		{
+			/* T7 */
+			.nchan = NCHAN,
+			.pm_stats_cnt = T6_PM_NSTATS,
+			.cng_ch_bits_log = 2,
+			.nsched_cls = 16,
+			.cim_num_ibq = CIM_NUM_IBQ_T7,
+			.cim_num_obq = CIM_NUM_OBQ_T7,
+			.filter_opt_len = T7_FILTER_OPT_LEN,
+			.filter_num_opt = S_T7_FT_LAST + 1,
+			.mps_rplc_size = 256,
+			.vfcount = 256,
+			.sge_fl_db = 0,
+			.sge_ctxt_size = SGE_CTXT_SIZE_T7,
+			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
+			.rss_nentries = T7_RSS_NENTRIES,
+			.cim_la_size = CIMLA_SIZE_T6,
+		},
 	};
 
 	chipid -= CHELSIO_T4;
@@ -9466,14 +10397,11 @@ int t4_bar2_sge_qregs(struct adapter *adapter,
 }
 
 /**
- *	t4_init_devlog_params - initialize adapter->params.devlog
+ *	t4_init_devlog_ncores_params - initialize adap->params.devlog and ncores
  *	@adap: the adapter
  *	@fw_attach: whether we can talk to the firmware
- *
- *	Initialize various fields of the adapter's Firmware Device Log
- *	Parameters structure.
  */
-int t4_init_devlog_params(struct adapter *adap, int fw_attach)
+int t4_init_devlog_ncores_params(struct adapter *adap, int fw_attach)
 {
 	struct devlog_params *dparams = &adap->params.devlog;
 	u32 pf_dparams;
@@ -9487,12 +10415,15 @@ int t4_init_devlog_params(struct adapter *adap, int fw_attach)
 	 */
 	pf_dparams =
 		t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
-	if (pf_dparams) {
-		unsigned int nentries, nentries128;
+	if (pf_dparams && pf_dparams != UINT32_MAX) {
+		unsigned int nentries, nentries128, ncore_shift;
+
+		ncore_shift = (G_PCIE_FW_PF_DEVLOG_COUNT_MSB(pf_dparams) << 1) |
+		    G_PCIE_FW_PF_DEVLOG_COUNT_LSB(pf_dparams);
+		adap->params.ncores = 1 << ncore_shift;
 
 		dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
 		dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
-
 		nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
 		nentries = (nentries128 + 1) * 128;
 		dparams->size = nentries * sizeof(struct fw_devlog_e);
@@ -9503,6 +10434,7 @@ int t4_init_devlog_params(struct adapter *adap, int fw_attach)
 	/*
 	 * For any failing returns ...
 	 */
+	adap->params.ncores = 1;
 	memset(dparams, 0, sizeof *dparams);
 
 	/*
@@ -9624,21 +10556,28 @@ int t4_init_sge_params(struct adapter *adapter)
 
 /* Convert the LE's hardware hash mask to a shorter filter mask. */
 static inline uint16_t
-hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode)
+hashmask_to_filtermask(struct adapter *adap, uint64_t hashmask, uint16_t filter_mode)
 {
-	static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1};
-	int i;
+	int first, last, i;
 	uint16_t filter_mask;
-	uint64_t mask;		/* field mask */
+	uint64_t mask;          /* field mask */
+
+
+	if (chip_id(adap) >= CHELSIO_T7) {
+		first = S_T7_FT_FIRST;
+		last = S_T7_FT_LAST;
+	} else {
+		first = S_FT_FIRST;
+		last = S_FT_LAST;
+	}
 
-	filter_mask = 0;
-	for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
+	for (filter_mask = 0, i = first; i <= last; i++) {
 		if ((filter_mode & (1 << i)) == 0)
 			continue;
-		mask = (1 << width[i]) - 1;
+		mask = (1 << t4_filter_field_width(adap, i)) - 1;
 		if ((hashmask & mask) == mask)
 			filter_mask |= 1 << i;
-		hashmask >>= width[i];
+		hashmask >>= t4_filter_field_width(adap, i);
 	}
 
 	return (filter_mask);
@@ -9681,7 +10620,15 @@ read_filter_mode_and_ingress_config(struct adapter *adap)
 			v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
 			hash_mask |= (u64)v << 32;
 		}
-		tpp->filter_mask = hashmask_to_filtermask(hash_mask,
+		if (chip_id(adap) >= CHELSIO_T7) {
+			/*
+			 * This param came before T7 so T7+ firmwares should
+			 * always support this query.
+			 */
+			CH_WARN(adap, "query for filter mode/mask failed: %d\n",
+			    rc);
+		}
+		tpp->filter_mask = hashmask_to_filtermask(adap, hash_mask,
 		    tpp->filter_mode);
 
 		t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true);
@@ -9696,16 +10643,37 @@ read_filter_mode_and_ingress_config(struct adapter *adap)
 	 * shift positions of several elements of the Compressed Filter Tuple
 	 * for this adapter which we need frequently ...
 	 */
-	tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
-	tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
-	tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
-	tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
-	tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
-	tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
-	tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
-	tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
-	tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
-	tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
+	if (chip_id(adap) >= CHELSIO_T7) {
+		tpp->ipsecidx_shift = t4_filter_field_shift(adap, F_IPSECIDX);
+		tpp->fcoe_shift = t4_filter_field_shift(adap, F_T7_FCOE);
+		tpp->port_shift = t4_filter_field_shift(adap, F_T7_PORT);
+		tpp->vnic_shift = t4_filter_field_shift(adap, F_T7_VNIC_ID);
+		tpp->vlan_shift = t4_filter_field_shift(adap, F_T7_VLAN);
+		tpp->tos_shift = t4_filter_field_shift(adap, F_T7_TOS);
+		tpp->protocol_shift = t4_filter_field_shift(adap, F_T7_PROTOCOL);
+		tpp->ethertype_shift = t4_filter_field_shift(adap, F_T7_ETHERTYPE);
+		tpp->macmatch_shift = t4_filter_field_shift(adap, F_T7_MACMATCH);
+		tpp->matchtype_shift = t4_filter_field_shift(adap, F_T7_MPSHITTYPE);
+		tpp->frag_shift = t4_filter_field_shift(adap, F_T7_FRAGMENTATION);
+		tpp->roce_shift = t4_filter_field_shift(adap, F_ROCE);
+		tpp->synonly_shift = t4_filter_field_shift(adap, F_SYNONLY);
+		tpp->tcpflags_shift = t4_filter_field_shift(adap, F_TCPFLAGS);
+	} else {
+		tpp->ipsecidx_shift = -1;
+		tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
+		tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
+		tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
+		tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
+		tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
+		tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
+		tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
+		tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
+		tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
+		tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
+		tpp->roce_shift = -1;
+		tpp->synonly_shift = -1;
+		tpp->tcpflags_shift = -1;
+	}
 }
 
 /**
@@ -9725,11 +10693,21 @@ int t4_init_tp_params(struct adapter *adap)
 
 	read_filter_mode_and_ingress_config(adap);
 
+	tpp->rx_pkt_encap = false;
+	tpp->lb_mode = 0;
+	tpp->lb_nchan = 1;
 	if (chip_id(adap) > CHELSIO_T5) {
 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
 		tpp->rx_pkt_encap = v & F_CRXPKTENC;
-	} else
-		tpp->rx_pkt_encap = false;
+		if (chip_id(adap) >= CHELSIO_T7) {
+			t4_tp_pio_read(adap, &v, 1, A_TP_CHANNEL_MAP, true);
+			tpp->lb_mode = G_T7_LB_MODE(v);
+			if (tpp->lb_mode == 1)
+				tpp->lb_nchan = 4;
+			else if (tpp->lb_mode == 2)
+				tpp->lb_nchan = 2;
+		}
+	}
 
 	rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE);
 	tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE);
@@ -9750,6 +10728,53 @@ int t4_init_tp_params(struct adapter *adap)
 }
 
 /**
+ *      t4_filter_field_width - returns the width of a filter field
+ *      @adap: the adapter
+ *      @filter_field: the filter field whose width is being requested
+ *
+ *      Return the shift position of a filter field within the Compressed
+ *      Filter Tuple.  The filter field is specified via its selection bit
+ *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
+ */
+int t4_filter_field_width(const struct adapter *adap, int filter_field)
+{
+	const int nopt = adap->chip_params->filter_num_opt;
+	static const uint8_t width_t7[] = {
+		W_FT_IPSECIDX,
+		W_FT_FCOE,
+		W_FT_PORT,
+		W_FT_VNIC_ID,
+		W_FT_VLAN,
+		W_FT_TOS,
+		W_FT_PROTOCOL,
+		W_FT_ETHERTYPE,
+		W_FT_MACMATCH,
+		W_FT_MPSHITTYPE,
+		W_FT_FRAGMENTATION,
+		W_FT_ROCE,
+		W_FT_SYNONLY,
+		W_FT_TCPFLAGS
+	};
+	static const uint8_t width_t4[] = {
+		W_FT_FCOE,
+		W_FT_PORT,
+		W_FT_VNIC_ID,
+		W_FT_VLAN,
+		W_FT_TOS,
+		W_FT_PROTOCOL,
+		W_FT_ETHERTYPE,
+		W_FT_MACMATCH,
+		W_FT_MPSHITTYPE,
+		W_FT_FRAGMENTATION
+	};
+	const uint8_t *width = chip_id(adap) >= CHELSIO_T7 ? width_t7 : width_t4;
+
+	if (filter_field < 0 || filter_field >= nopt)
+		return (0);
+	return (width[filter_field]);
+}
+
+/**
  *      t4_filter_field_shift - calculate filter field shift
  *      @adap: the adapter
  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
@@ -9767,6 +10792,56 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
 	if ((filter_mode & filter_sel) == 0)
 		return -1;
 
+	if (chip_id(adap) >= CHELSIO_T7) {
+		for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
+			switch (filter_mode & sel) {
+			case F_IPSECIDX:
+				field_shift += W_FT_IPSECIDX;
+				break;
+			case F_T7_FCOE:
+				field_shift += W_FT_FCOE;
+				break;
+			case F_T7_PORT:
+				field_shift += W_FT_PORT;
+				break;
+			case F_T7_VNIC_ID:
+				field_shift += W_FT_VNIC_ID;
+				break;
+			case F_T7_VLAN:
+				field_shift += W_FT_VLAN;
+				break;
+			case F_T7_TOS:
+				field_shift += W_FT_TOS;
+				break;
+			case F_T7_PROTOCOL:
+				field_shift += W_FT_PROTOCOL;
+				break;
+			case F_T7_ETHERTYPE:
+				field_shift += W_FT_ETHERTYPE;
+				break;
+			case F_T7_MACMATCH:
+				field_shift += W_FT_MACMATCH;
+				break;
+			case F_T7_MPSHITTYPE:
+				field_shift += W_FT_MPSHITTYPE;
+				break;
+			case F_T7_FRAGMENTATION:
+				field_shift += W_FT_FRAGMENTATION;
+				break;
+			case F_ROCE:
+				field_shift += W_FT_ROCE;
+				break;
+			case F_SYNONLY:
+				field_shift += W_FT_SYNONLY;
+				break;
+			case F_TCPFLAGS:
+				field_shift += W_FT_TCPFLAGS;
+				break;
+			}
+		}
+		return field_shift;
+	}
+
 	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
 		switch (filter_mode & sel) {
 		case F_FCOE:
@@ -9818,11 +10893,11 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
 		} while ((adap->params.portvec & (1 << j)) == 0);
 	}
 
+	p->hw_port = j;
 	p->tx_chan = t4_get_tx_c_chan(adap, j);
 	p->rx_chan = t4_get_rx_c_chan(adap, j);
 	p->mps_bg_map = t4_get_mps_bg_map(adap, j);
 	p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
-	p->lport = j;
 
 	if (!(adap->flags & IS_VF) ||
 	    adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
@@ -9851,232 +10926,321 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
 	return 0;
 }
 
+static void t4_read_cimq_cfg_ibq_core(struct adapter *adap, u8 coreid, u32 qid,
+				      u16 *base, u16 *size, u16 *thres)
+{
+	unsigned int v, m;
+
+	if (chip_id(adap) > CHELSIO_T6) {
+		v = F_T7_IBQSELECT | V_T7_QUENUMSELECT(qid) |
+		    V_CORESELECT(coreid);
+		/* value is in 512-byte units */
+		m = 512;
+	} else {
+		v = F_IBQSELECT | V_QUENUMSELECT(qid);
+		/* value is in 256-byte units */
+		m = 256;
+	}
+
+	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, v);
+	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
+	if (base)
+		*base = G_CIMQBASE(v) * m;
+	if (size)
+		*size = G_CIMQSIZE(v) * m;
+	if (thres)
+		*thres = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
+}
+
+static void t4_read_cimq_cfg_obq_core(struct adapter *adap, u8 coreid, u32 qid,
+				      u16 *base, u16 *size)
+{
+	unsigned int v, m;
+
+	if (chip_id(adap) > CHELSIO_T6) {
+		v = F_T7_OBQSELECT | V_T7_QUENUMSELECT(qid) |
+		    V_CORESELECT(coreid);
+		/* value is in 512-byte units */
+		m = 512;
+	} else {
+		v = F_OBQSELECT | V_QUENUMSELECT(qid);
+		/* value is in 256-byte units */
+		m = 256;
+	}
+
+	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, v);
+	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
+	if (base)
+		*base = G_CIMQBASE(v) * m;
+	if (size)
+		*size = G_CIMQSIZE(v) * m;
+}
+
 /**
- *	t4_read_cimq_cfg - read CIM queue configuration
+ *	t4_read_cimq_cfg_core - read CIM queue configuration on specific core
  *	@adap: the adapter
+ *	@coreid: the uP coreid
  *	@base: holds the queue base addresses in bytes
  *	@size: holds the queue sizes in bytes
  *	@thres: holds the queue full thresholds in bytes
  *
  *	Returns the current configuration of the CIM queues, starting with
- *	the IBQs, then the OBQs.
+ *	the IBQs, then the OBQs, on a specific @coreid.
  */
-void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
+void t4_read_cimq_cfg_core(struct adapter *adap, u8 coreid, u16 *base,
+			   u16 *size, u16 *thres)
 {
-	unsigned int i, v;
-	int cim_num_obq = adap->chip_params->cim_num_obq;
+	unsigned int cim_num_ibq = adap->chip_params->cim_num_ibq;
+	unsigned int cim_num_obq = adap->chip_params->cim_num_obq;
+	unsigned int i;
 
-	for (i = 0; i < CIM_NUM_IBQ; i++) {
-		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
-			     V_QUENUMSELECT(i));
-		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
-		/* value is in 256-byte units */
-		*base++ = G_CIMQBASE(v) * 256;
-		*size++ = G_CIMQSIZE(v) * 256;
-		*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
-	}
-	for (i = 0; i < cim_num_obq; i++) {
-		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
-			     V_QUENUMSELECT(i));
-		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
-		/* value is in 256-byte units */
-		*base++ = G_CIMQBASE(v) * 256;
-		*size++ = G_CIMQSIZE(v) * 256;
-	}
+	for (i = 0; i < cim_num_ibq; i++, base++, size++, thres++)
+		t4_read_cimq_cfg_ibq_core(adap, coreid, i, base, size, thres);
+
+	for (i = 0; i < cim_num_obq; i++, base++, size++)
+		t4_read_cimq_cfg_obq_core(adap, coreid, i, base, size);
+}
+
+static int t4_read_cim_ibq_data_core(struct adapter *adap, u8 coreid, u32 addr,
+				     u32 *data)
+{
+	int ret, attempts;
+	unsigned int v;
+
+	/* It might take 3-10ms before the IBQ debug read access is allowed.
+	 * Wait for 1 Sec with a delay of 1 usec.
+	 */
+	attempts = 1000000;
+
+	if (chip_id(adap) > CHELSIO_T6)
+		v = V_T7_IBQDBGADDR(addr) | V_IBQDBGCORE(coreid);
+	else
+		v = V_IBQDBGADDR(addr);
+
+	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, v | F_IBQDBGEN);
+	ret = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
+			      attempts, 1);
+	if (ret)
+		return ret;
+
+	*data = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
+	return 0;
 }
 
 /**
- *	t4_read_cim_ibq - read the contents of a CIM inbound queue
+ *	t4_read_cim_ibq_core - read the contents of a CIM inbound queue on
+ *	specific core
  *	@adap: the adapter
+ *	@coreid: the uP coreid
  *	@qid: the queue index
  *	@data: where to store the queue contents
  *	@n: capacity of @data in 32-bit words
  *
  *	Reads the contents of the selected CIM queue starting at address 0 up
- *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
- *	error and the number of 32-bit words actually read on success.
+ *	to the capacity of @data on a specific @coreid.  @n must be a multiple
+ *	of 4.  Returns < 0 on error and the number of 32-bit words actually
+ *	read on success.
  */
-int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+int t4_read_cim_ibq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+			 size_t n)
 {
-	int i, err, attempts;
-	unsigned int addr;
-	const unsigned int nwords = CIM_IBQ_SIZE * 4;
+	unsigned int cim_num_ibq = adap->chip_params->cim_num_ibq;
+	u16 i, addr, nwords;
+	int ret;
 
-	if (qid > 5 || (n & 3))
+	if (qid > (cim_num_ibq - 1) || (n & 3))
 		return -EINVAL;
 
-	addr = qid * nwords;
+	t4_read_cimq_cfg_ibq_core(adap, coreid, qid, &addr, &nwords, NULL);
+	addr >>= sizeof(u16);
+	nwords >>= sizeof(u16);
 	if (n > nwords)
 		n = nwords;
 
-	/* It might take 3-10ms before the IBQ debug read access is allowed.
-	 * Wait for 1 Sec with a delay of 1 usec.
-	 */
-	attempts = 1000000;
-
-	for (i = 0; i < n; i++, addr++) {
-		t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
-			     F_IBQDBGEN);
-		err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
-				      attempts, 1);
-		if (err)
-			return err;
-		*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
+	for (i = 0; i < n; i++, addr++, data++) {
+		ret = t4_read_cim_ibq_data_core(adap, coreid, addr, data);
+		if (ret < 0)
+			return ret;
 	}
+
 	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
 	return i;
 }
 
+static int t4_read_cim_obq_data_core(struct adapter *adap, u8 coreid, u32 addr,
+				     u32 *data)
+{
+	unsigned int v;
+	int ret;
+
+	if (chip_id(adap) > CHELSIO_T6)
+		v = V_T7_OBQDBGADDR(addr) | V_OBQDBGCORE(coreid);
+	else
+		v = V_OBQDBGADDR(addr);
+
+	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, v | F_OBQDBGEN);
+	ret = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 2, 1);
+	if (ret)
+		return ret;
+
+	*data = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
+	return 0;
+}
+
 /**
- *	t4_read_cim_obq - read the contents of a CIM outbound queue
+ *	t4_read_cim_obq_core - read the contents of a CIM outbound queue on
+ *	specific core
  *	@adap: the adapter
+ *	@coreid: the uP coreid
  *	@qid: the queue index
  *	@data: where to store the queue contents
  *	@n: capacity of @data in 32-bit words
  *
  *	Reads the contents of the selected CIM queue starting at address 0 up
- *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
- *	error and the number of 32-bit words actually read on success.
+ *	to the capacity of @data on specific @coreid.  @n must be a multiple
+ *	of 4.  Returns < 0 on error and the number of 32-bit words actually
+ *	read on success.
  */
-int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
+int t4_read_cim_obq_core(struct adapter *adap, u8 coreid, u32 qid, u32 *data,
+			 size_t n)
 {
-	int i, err;
-	unsigned int addr, v, nwords;
-	int cim_num_obq = adap->chip_params->cim_num_obq;
+	unsigned int cim_num_obq = adap->chip_params->cim_num_obq;
+	u16 i, addr, nwords;
+	int ret;
 
 	if ((qid > (cim_num_obq - 1)) || (n & 3))
 		return -EINVAL;
 
-	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
-		     V_QUENUMSELECT(qid));
-	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
-
-	addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
-	nwords = G_CIMQSIZE(v) * 64;  /* same */
+	t4_read_cimq_cfg_obq_core(adap, coreid, qid, &addr, &nwords);
+	addr >>= sizeof(u16);
+	nwords >>= sizeof(u16);
 	if (n > nwords)
 		n = nwords;
 
-	for (i = 0; i < n; i++, addr++) {
-		t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
-			     F_OBQDBGEN);
-		err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
-				      2, 1);
-		if (err)
-			return err;
-		*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
+	for (i = 0; i < n; i++, addr++, data++) {
+		ret = t4_read_cim_obq_data_core(adap, coreid, addr, data);
+		if (ret < 0)
+			return ret;
 	}
+
 	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
-	return i;
+ 	return i;
 }
 
-enum {
-	CIM_QCTL_BASE     = 0,
-	CIM_CTL_BASE      = 0x2000,
-	CIM_PBT_ADDR_BASE = 0x2800,
-	CIM_PBT_LRF_BASE  = 0x3000,
-	CIM_PBT_DATA_BASE = 0x3800
-};
-
 /**
- *	t4_cim_read - read a block from CIM internal address space
+ *	t4_cim_read_core - read a block from CIM internal address space
+ *	of a control register group on specific core.
  *	@adap: the adapter
+ *	@group: the control register group to select for read
+ *	@coreid: the uP coreid
  *	@addr: the start address within the CIM address space
  *	@n: number of words to read
  *	@valp: where to store the result
  *
- *	Reads a block of 4-byte words from the CIM intenal address space.
+ *	Reads a block of 4-byte words from the CIM intenal address space
+ *	of a control register @group on a specific @coreid.
  */
-int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
-		unsigned int *valp)
+int t4_cim_read_core(struct adapter *adap, u8 group, u8 coreid,
+		     unsigned int addr, unsigned int n,
+		     unsigned int *valp)
 {
+	unsigned int hostbusy, v = 0;
 	int ret = 0;
 
-	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
+	if (chip_id(adap) > CHELSIO_T6) {
+		hostbusy = F_T7_HOSTBUSY;
+		v = V_HOSTGRPSEL(group) | V_HOSTCORESEL(coreid);
+	} else {
+		hostbusy = F_HOSTBUSY;
+	}
+
+	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & hostbusy)
 		return -EBUSY;
 
 	for ( ; !ret && n--; addr += 4) {
-		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
-		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
+		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | v);
+		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, hostbusy,
 				      0, 5, 2);
 		if (!ret)
 			*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
 	}
+
 	return ret;
 }
 
 /**
- *	t4_cim_write - write a block into CIM internal address space
+ *	t4_cim_write_core - write a block into CIM internal address space
+ *	of a control register group on specific core.
  *	@adap: the adapter
+ *	@group: the control register group to select for write
+ *	@coreid: the uP coreid
  *	@addr: the start address within the CIM address space
  *	@n: number of words to write
  *	@valp: set of values to write
  *
- *	Writes a block of 4-byte words into the CIM intenal address space.
+ *	Writes a block of 4-byte words into the CIM intenal address space
+ *	of a control register @group on a specific @coreid.
  */
-int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
-		 const unsigned int *valp)
+int t4_cim_write_core(struct adapter *adap, u8 group, u8 coreid,
+		      unsigned int addr, unsigned int n,
+		      const unsigned int *valp)
 {
+	unsigned int hostbusy, v;
 	int ret = 0;
 
-	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
+	if (chip_id(adap) > CHELSIO_T6) {
+		hostbusy = F_T7_HOSTBUSY;
+		v = F_T7_HOSTWRITE | V_HOSTGRPSEL(group) |
+		    V_HOSTCORESEL(coreid);
+	} else {
+		hostbusy = F_HOSTBUSY;
+		v = F_HOSTWRITE;
+	}
+
+	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & hostbusy)
 		return -EBUSY;
 
 	for ( ; !ret && n--; addr += 4) {
 		t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
-		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
-		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
+		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | v);
+		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, hostbusy,
 				      0, 5, 2);
 	}
-	return ret;
-}
 
-static int t4_cim_write1(struct adapter *adap, unsigned int addr,
-			 unsigned int val)
-{
-	return t4_cim_write(adap, addr, 1, &val);
-}
-
-/**
- *	t4_cim_ctl_read - read a block from CIM control region
- *	@adap: the adapter
- *	@addr: the start address within the CIM control region
- *	@n: number of words to read
- *	@valp: where to store the result
- *
- *	Reads a block of 4-byte words from the CIM control region.
- */
-int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
-		    unsigned int *valp)
-{
-	return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
+	return ret;
 }
 
 /**
- *	t4_cim_read_la - read CIM LA capture buffer
+ *	t4_cim_read_la_core - read CIM LA capture buffer on specific core
  *	@adap: the adapter
+ *	@coreid: uP coreid
  *	@la_buf: where to store the LA data
  *	@wrptr: the HW write pointer within the capture buffer
  *
- *	Reads the contents of the CIM LA buffer with the most recent entry at
- *	the end	of the returned data and with the entry at @wrptr first.
- *	We try to leave the LA in the running state we find it in.
+ *	Reads the contents of the CIM LA buffer on a specific @coreid
+ *	with the most recent entry at the end of the returned data
+ *	and with the entry at @wrptr first. We try to leave the LA
+ *	in the running state we find it in.
  */
-int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
+int t4_cim_read_la_core(struct adapter *adap, u8 coreid, u32 *la_buf,
+			u32 *wrptr)
 {
-	int i, ret;
 	unsigned int cfg, val, idx;
+	int i, ret;
 
-	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
+	ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1, &cfg);
 	if (ret)
 		return ret;
 
 	if (cfg & F_UPDBGLAEN) {	/* LA is running, freeze it */
-		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
+		val = 0;
+		ret = t4_cim_write_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
+					&val);
 		if (ret)
 			return ret;
 	}
 
-	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
+	ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1, &val);
 	if (ret)
 		goto restart;
 
@@ -10085,25 +11249,28 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
 		*wrptr = idx;
 
 	for (i = 0; i < adap->params.cim_la_size; i++) {
-		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
-				    V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
+		val = V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN;
+		ret = t4_cim_write_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
+					&val);
 		if (ret)
 			break;
-		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
+		ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
+				       &val);
 		if (ret)
 			break;
 		if (val & F_UPDBGLARDEN) {
 			ret = -ETIMEDOUT;
 			break;
 		}
-		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
+		ret = t4_cim_read_core(adap, 1, coreid, A_UP_UP_DBG_LA_DATA, 1,
+				       &la_buf[i]);
 		if (ret)
 			break;
 
 		/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
 		 * identify the 32-bit portion of the full 312-bit data
 		 */
-		if (is_t6(adap) && (idx & 0xf) >= 9)
+		if ((chip_id(adap) > CHELSIO_T5) && (idx & 0xf) >= 9)
 			idx = (idx & 0xff0) + 0x10;
 		else
 			idx++;
@@ -10112,11 +11279,15 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
 	}
 restart:
 	if (cfg & F_UPDBGLAEN) {
-		int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
-				      cfg & ~F_UPDBGLARDEN);
+		int r;
+
+		val = cfg & ~F_UPDBGLARDEN;
+		r = t4_cim_write_core(adap, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
+				      &val);
 		if (!ret)
 			ret = r;
 	}
+
 	return ret;
 }
 
@@ -10403,25 +11574,20 @@ void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbp
 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
 {
 	int ret, i, n, cfg_addr;
-	unsigned int addr;
+	unsigned int addr, len;
 	unsigned int flash_cfg_start_sec;
-	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
 
-	cfg_addr = t4_flash_cfg_addr(adap);
+	cfg_addr = t4_flash_cfg_addr(adap, &len);
 	if (cfg_addr < 0)
 		return cfg_addr;
 
-	addr = cfg_addr;
-	flash_cfg_start_sec = addr / SF_SEC_SIZE;
-
-	if (size > FLASH_CFG_MAX_SIZE) {
-		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
-		       FLASH_CFG_MAX_SIZE);
+	if (size > len) {
+		CH_ERR(adap, "cfg file too large, max is %u bytes\n", len);
 		return -EFBIG;
 	}
 
-	i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,	/* # of sectors spanned */
-			 sf_sec_size);
+	flash_cfg_start_sec = cfg_addr / SF_SEC_SIZE;
+	i = DIV_ROUND_UP(len, SF_SEC_SIZE);
 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
 				     flash_cfg_start_sec + i - 1);
 	/*
@@ -10432,15 +11598,12 @@ int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
 		goto out;
 
 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
-	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
-		if ( (size - i) <  SF_PAGE_SIZE)
-			n = size - i;
-		else
-			n = SF_PAGE_SIZE;
+	addr = cfg_addr;
+	for (i = 0; i < size; i += SF_PAGE_SIZE) {
+		n = min(size - i, SF_PAGE_SIZE);
 		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
 		if (ret)
 			goto out;
-
 		addr += SF_PAGE_SIZE;
 		cfg_data += SF_PAGE_SIZE;
 	}
@@ -10644,25 +11807,25 @@ int t4_load_boot(struct adapter *adap, u8 *boot_data,
 	pcir_data_t *pcir_header;
 	int ret, addr;
 	uint16_t device_id;
-	unsigned int i;
-	unsigned int boot_sector = (boot_addr * 1024 );
-	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
+	unsigned int i, start, len;
+	unsigned int boot_sector = boot_addr * 1024;
 
 	/*
-	 * Make sure the boot image does not encroach on the firmware region
+	 * Make sure the boot image does not exceed its available space.
 	 */
-	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
-		CH_ERR(adap, "boot image encroaching on firmware region\n");
+	len = 0;
+	start = t4_flash_loc_start(adap, FLASH_LOC_BOOT_AREA, &len);
+	if (boot_sector + size > start + len) {
+		CH_ERR(adap, "boot data is larger than available BOOT area\n");
 		return -EFBIG;
 	}
 
 	/*
 	 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
 	 * and Boot configuration data sections. These 3 boot sections span
-	 * sectors 0 to 7 in flash and live right before the FW image location.
+	 * the entire FLASH_LOC_BOOT_AREA.
 	 */
-	i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
-			sf_sec_size);
+	i = DIV_ROUND_UP(size ? size : len, SF_SEC_SIZE);
 	ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
 				     (boot_sector >> 16) + i - 1);
 
@@ -10765,40 +11928,39 @@ out:
  *	is stored, or an error if the device FLASH is too small to contain
  *	a OptionROM Configuration.
  */
-static int t4_flash_bootcfg_addr(struct adapter *adapter)
+static int t4_flash_bootcfg_addr(struct adapter *adapter, unsigned int *lenp)
 {
+	unsigned int len = 0;
+	const int start = t4_flash_loc_start(adapter, FLASH_LOC_BOOTCFG, &len);
+
 	/*
 	 * If the device FLASH isn't large enough to hold a Firmware
 	 * Configuration File, return an error.
 	 */
-	if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
+	if (adapter->params.sf_size < start + len)
 		return -ENOSPC;
-
-	return FLASH_BOOTCFG_START;
+	if (lenp != NULL)
+		*lenp = len;
+	return (start);
 }
 
 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
 {
 	int ret, i, n, cfg_addr;
-	unsigned int addr;
+	unsigned int addr, len;
 	unsigned int flash_cfg_start_sec;
-	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
 
-	cfg_addr = t4_flash_bootcfg_addr(adap);
+	cfg_addr = t4_flash_bootcfg_addr(adap, &len);
 	if (cfg_addr < 0)
 		return cfg_addr;
 
-	addr = cfg_addr;
-	flash_cfg_start_sec = addr / SF_SEC_SIZE;
-
-	if (size > FLASH_BOOTCFG_MAX_SIZE) {
-		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
-			FLASH_BOOTCFG_MAX_SIZE);
+	if (size > len) {
+		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", len);
 		return -EFBIG;
 	}
 
-	i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
-			 sf_sec_size);
+	flash_cfg_start_sec = cfg_addr / SF_SEC_SIZE;
+	i = DIV_ROUND_UP(len, SF_SEC_SIZE);
 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
 					flash_cfg_start_sec + i - 1);
 
@@ -10810,15 +11972,12 @@ int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
 		goto out;
 
 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
-	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
-		if ( (size - i) <  SF_PAGE_SIZE)
-			n = size - i;
-		else
-			n = SF_PAGE_SIZE;
+	addr = cfg_addr;
+	for (i = 0; i < size; i += SF_PAGE_SIZE) {
+		n = min(size - i, SF_PAGE_SIZE);
 		ret = t4_write_flash(adap, addr, n, cfg_data, 0);
 		if (ret)
 			goto out;
-
 		addr += SF_PAGE_SIZE;
 		cfg_data += SF_PAGE_SIZE;
 	}
@@ -10844,19 +12003,20 @@ out:
  */
 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
 {
-	static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1};
 	int i, nbits, rc;
 	uint32_t param, val;
 	uint16_t fmode, fmask;
 	const int maxbits = adap->chip_params->filter_opt_len;
+	const int nopt = adap->chip_params->filter_num_opt;
+	int width;
 
 	if (mode != -1 || mask != -1) {
 		if (mode != -1) {
 			fmode = mode;
 			nbits = 0;
-			for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
+			for (i = 0; i < nopt; i++) {
 				if (fmode & (1 << i))
-					nbits += width[i];
+					nbits += t4_filter_field_width(adap, i);
 			}
 			if (nbits > maxbits) {
 				CH_ERR(adap, "optional fields in the filter "
@@ -10867,17 +12027,20 @@ int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
 			}
 
 			/*
-			 * Hardware wants the bits to be maxed out.  Keep
+			 * Hardware < T7 wants the bits to be maxed out.  Keep
 			 * setting them until there's no room for more.
 			 */
-			for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
-				if (fmode & (1 << i))
-					continue;
-				if (nbits + width[i] <= maxbits) {
-					fmode |= 1 << i;
-					nbits += width[i];
-					if (nbits == maxbits)
-						break;
+			if (chip_id(adap) < CHELSIO_T7) {
+				for (i = 0; i < nopt; i++) {
+					if (fmode & (1 << i))
+						continue;
+					width = t4_filter_field_width(adap, i);
+					if (nbits + width <= maxbits) {
+						fmode |= 1 << i;
+						nbits += width;
+						if (nbits == maxbits)
+							break;
+					}
 				}
 			}
 
@@ -10936,21 +12099,26 @@ int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
  */
 void t4_clr_port_stats(struct adapter *adap, int idx)
 {
-	unsigned int i;
-	u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
-	u32 port_base_addr;
+	struct port_info *pi;
+	int i, port_id, tx_chan;
+	u32 bgmap, port_base_addr;
 
-	if (is_t4(adap))
-		port_base_addr = PORT_BASE(idx);
-	else
-		port_base_addr = T5_PORT_BASE(idx);
-
-	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
-			i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
-		t4_write_reg(adap, port_base_addr + i, 0);
-	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
-			i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
-		t4_write_reg(adap, port_base_addr + i, 0);
+	port_id  = adap->port_map[idx];
+	MPASS(port_id >= 0 && port_id <= adap->params.nports);
+	pi = adap->port[port_id];
+
+	for (tx_chan = pi->tx_chan;
+	    tx_chan < pi->tx_chan + adap->params.tp.lb_nchan; tx_chan++) {
+		port_base_addr = t4_port_reg(adap, tx_chan, 0);
+
+		for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
+				i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
+			t4_write_reg(adap, port_base_addr + i, 0);
+		for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
+				i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
+			t4_write_reg(adap, port_base_addr + i, 0);
+	}
+	bgmap = pi->mps_bg_map;
 	for (i = 0; i < 4; i++)
 		if (bgmap & (1 << i)) {
 			t4_write_reg(adap,
@@ -11078,6 +12246,8 @@ int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
 		data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
 		data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
 		data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
+		if (chip_id(adap) > CHELSIO_T6)
+			data[6] = be32_to_cpu(c.u.idctxt.ctxt_data6);
 	}
 	return ret;
 }
@@ -11099,9 +12269,12 @@ int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type cty
 
 	t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
 	ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
-	if (!ret)
+	if (!ret) {
 		for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
 			*data++ = t4_read_reg(adap, i);
+		if (chip_id(adap) > CHELSIO_T6)
+			*data++ = t4_read_reg(adap, i);
+	}
 	return ret;
 }
 
diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h
index 79ec690cd5e6..09bd9ac9e637 100644
--- a/sys/dev/cxgbe/common/t4_hw.h
+++ b/sys/dev/cxgbe/common/t4_hw.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2016, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -42,30 +41,36 @@ enum {
 	EEPROMPFSIZE    = 1024,  /* EEPROM writable area size for PFn, n>0 */
 	RSS_NENTRIES    = 2048,  /* # of entries in RSS mapping table */
 	T6_RSS_NENTRIES = 4096,
+	T7_RSS_NENTRIES = 16384,
 	TCB_SIZE        = 128,   /* TCB size */
 	NMTUS           = 16,    /* size of MTU table */
 	NCCTRL_WIN      = 32,    /* # of congestion control windows */
 	NTX_SCHED       = 8,     /* # of HW Tx scheduling queues */
 	PM_NSTATS       = 5,     /* # of PM stats */
-	T6_PM_NSTATS    = 7,
+	T6_PM_NSTATS    = 7,     /* # of PM stats in T6 */
 	MAX_PM_NSTATS   = 7,
+	T7_PM_RX_CACHE_NSTATS = 27, /* # of PM Rx Cache stats in T7 */
 	MBOX_LEN        = 64,    /* mailbox size in bytes */
 	NTRACE          = 4,     /* # of tracing filters */
 	TRACE_LEN       = 112,   /* length of trace data and mask */
 	FILTER_OPT_LEN  = 36,    /* filter tuple width of optional components */
 	T5_FILTER_OPT_LEN = 40,
+	T7_FILTER_OPT_LEN = 63,
 	NWOL_PAT        = 8,     /* # of WoL patterns */
 	WOL_PAT_LEN     = 128,   /* length of WoL patterns */
 	UDBS_SEG_SIZE   = 128,   /* Segment size of BAR2 doorbells */
 	UDBS_SEG_SHIFT  = 7,     /* log2(UDBS_SEG_SIZE) */
 	UDBS_DB_OFFSET  = 8,     /* offset of the 4B doorbell in a segment */
 	UDBS_WR_OFFSET  = 64,    /* offset of the work request in a segment */
+	MAX_UP_CORES = 8, /* Max # of uP cores that can be enabled */
 };
 
 enum {
 	CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
+	CIM_NUM_IBQ_T7 = 16,    /* # of CIM IBQs for T7 */
 	CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
 	CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
+	CIM_NUM_OBQ_T7 = 16,    /* # of CIM OBQs for T7 adapter */
 	CIMLA_SIZE     = 256 * 8,  /* 256 rows * ceil(235/32) 32-bit words */
 	CIMLA_SIZE_T6  = 256 * 10, /* 256 rows * ceil(311/32) 32-bit words */
 	CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
@@ -91,6 +96,7 @@ enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
 enum {
 	SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
 	SGE_CTXT_SIZE = 24,       /* size of SGE context */
+	SGE_CTXT_SIZE_T7 = 28,    /* size of SGE context for T7 */
 	SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
 	SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
 	SGE_NDBQTIMERS = 8,       /* # of Doorbell Queue Timer values */
@@ -161,6 +167,18 @@ struct rsp_ctrl {
 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
 
+#define S_ARM_QTYPE	11
+#define M_ARM_QTYPE	1
+#define V_ARM_QTYPE(x)	((x) << S_ARM_QTYPE)
+
+#define S_ARM_PIDX    0
+#define M_ARM_PIDX    0x7ffU
+#define V_ARM_PIDX(x) ((x) << S_ARM_PIDX)
+
+#define S_ARM_CIDXINC    0
+#define M_ARM_CIDXINC    0x7ffU
+#define V_ARM_CIDXINC(x) ((x) << S_ARM_CIDXINC)
+
 /* # of pages a pagepod can hold without needing another pagepod */
 #define PPOD_PAGES 4U
 
@@ -206,95 +224,116 @@ struct pagepod {
  */
 #define FLASH_START(start)	((start) * SF_SEC_SIZE)
 #define FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
+#define FLASH_MIN_SIZE	FLASH_START(32)
 
-enum {
+enum t4_flash_loc {
 	/*
 	 * Various Expansion-ROM boot images, etc.
 	 */
-	FLASH_EXP_ROM_START_SEC = 0,
-	FLASH_EXP_ROM_NSECS = 6,
-	FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
-	FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
+	FLASH_LOC_EXP_ROM = 0,
 
 	/*
 	 * iSCSI Boot Firmware Table (iBFT) and other driver-related
 	 * parameters ...
 	 */
-	FLASH_IBFT_START_SEC = 6,
-	FLASH_IBFT_NSECS = 1,
-	FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
-	FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
+	FLASH_LOC_IBFT,
 
 	/*
 	 * Boot configuration data.
 	 */
-	FLASH_BOOTCFG_START_SEC = 7,
-	FLASH_BOOTCFG_NSECS = 1,
-	FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
-	FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
+	FLASH_LOC_BOOTCFG,
 
 	/*
 	 * Location of firmware image in FLASH.
 	 */
-	FLASH_FW_START_SEC = 8,
-	FLASH_FW_NSECS = 16,
-	FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
-	FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
+	FLASH_LOC_FW,
 
 	/*
 	 * Location of bootstrap firmware image in FLASH.
 	 */
-	FLASH_FWBOOTSTRAP_START_SEC = 27,
-	FLASH_FWBOOTSTRAP_NSECS = 1,
-	FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
-	FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
+	FLASH_LOC_FWBOOTSTRAP,
 
 	/*
 	 * iSCSI persistent/crash information.
 	 */
-	FLASH_ISCSI_CRASH_START_SEC = 29,
-	FLASH_ISCSI_CRASH_NSECS = 1,
-	FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
-	FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
+	FLASH_LOC_ISCSI_CRASH,
 
 	/*
 	 * FCoE persistent/crash information.
 	 */
-	FLASH_FCOE_CRASH_START_SEC = 30,
-	FLASH_FCOE_CRASH_NSECS = 1,
-	FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
-	FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
+	FLASH_LOC_FCOE_CRASH,
 
 	/*
 	 * Location of Firmware Configuration File in FLASH.
 	 */
-	FLASH_CFG_START_SEC = 31,
-	FLASH_CFG_NSECS = 1,
-	FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
-	FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
+	FLASH_LOC_CFG,
+
+	/*
+	 * CUDBG chip dump.
+	 */
+	FLASH_LOC_CUDBG,
+
+	/*
+	 * FW chip dump.
+	 */
+	FLASH_LOC_CHIP_DUMP,
+
+	/*
+	 * DPU boot information store.
+	 */
+	FLASH_LOC_DPU_BOOT,
+
+	/*
+	 * DPU peristent information store.
+	 */
+	FLASH_LOC_DPU_AREA,
 
 	/*
-	 * We don't support FLASH devices which can't support the full
-	 * standard set of sections which we need for normal operations.
+	 * VPD location.
 	 */
-	FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
+	FLASH_LOC_VPD,
 
 	/*
-	 * Sectors 32-63 for CUDBG.
+	 * Backup init/vpd.
 	 */
-	FLASH_CUDBG_START_SEC = 32,
-	FLASH_CUDBG_NSECS = 32,
-	FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC),
-	FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS),
+	FLASH_LOC_VPD_BACKUP,
 
 	/*
-	 * Size of defined FLASH regions.
+	 * Backup firmware image.
 	 */
-	FLASH_END_SEC = 64,
+	FLASH_LOC_FW_BACKUP,
+
+	/*
+	 * Backup bootstrap firmware image.
+	 */
+	FLASH_LOC_FWBOOTSTRAP_BACKUP,
+
+	/*
+	 * Backup Location of Firmware Configuration File in FLASH.
+	 */
+	FLASH_LOC_CFG_BACK,
+
+	/*
+	 * Helper to retrieve info that spans the entire Boot related area.
+	 */
+	FLASH_LOC_BOOT_AREA,
+
+	/*
+	 * Helper to determine minimum standard set of sections needed for
+	 * normal operations.
+	 */
+	FLASH_LOC_MIN_SIZE,
+
+	/*
+	 * End of FLASH regions.
+	 */
+	FLASH_LOC_END
 };
 
-#undef FLASH_START
-#undef FLASH_MAX_SIZE
+struct t4_flash_loc_entry {
+	u16 start_sec;
+	u16 nsecs;
+};
 
 #define S_SGE_TIMESTAMP 0
 #define M_SGE_TIMESTAMP 0xfffffffffffffffULL
diff --git a/sys/dev/cxgbe/common/t4_msg.h b/sys/dev/cxgbe/common/t4_msg.h
index d356d0d99f36..0d12ccf2e910 100644
--- a/sys/dev/cxgbe/common/t4_msg.h
+++ b/sys/dev/cxgbe/common/t4_msg.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2016, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -30,7 +29,7 @@
 #ifndef T4_MSG_H
 #define T4_MSG_H
 
-enum {
+enum cpl_opcodes {
 	CPL_PASS_OPEN_REQ     = 0x1,
 	CPL_PASS_ACCEPT_RPL   = 0x2,
 	CPL_ACT_OPEN_REQ      = 0x3,
@@ -68,13 +67,16 @@ enum {
 	CPL_PEER_CLOSE        = 0x26,
 	CPL_RTE_DELETE_RPL    = 0x27,
 	CPL_RTE_WRITE_RPL     = 0x28,
+	CPL_ROCE_FW_NOTIFY    = 0x28,
 	CPL_RX_URG_PKT        = 0x29,
 	CPL_TAG_WRITE_RPL     = 0x2A,
+	CPL_RDMA_ASYNC_EVENT  = 0x2A,
 	CPL_ABORT_REQ_RSS     = 0x2B,
 	CPL_RX_URG_NOTIFY     = 0x2C,
 	CPL_ABORT_RPL_RSS     = 0x2D,
 	CPL_SMT_WRITE_RPL     = 0x2E,
 	CPL_TX_DATA_ACK       = 0x2F,
+	CPL_RDMA_INV_REQ      = 0x2F,
 
 	CPL_RX_PHYS_ADDR      = 0x30,
 	CPL_PCMD_READ_RPL     = 0x31,
@@ -107,19 +109,30 @@ enum {
 	CPL_RX_DATA_DIF       = 0x4B,
 	CPL_ERR_NOTIFY	      = 0x4D,
 	CPL_RX_TLS_CMP        = 0x4E,
+	CPL_T6_TX_DATA_ACK    = 0x4F,
 
 	CPL_RDMA_READ_REQ     = 0x60,
 	CPL_RX_ISCSI_DIF      = 0x60,
+	CPL_RDMA_CQE_EXT      = 0x61,
+	CPL_RDMA_CQE_FW_EXT   = 0x62,
+	CPL_RDMA_CQE_ERR_EXT  = 0x63,
+	CPL_TX_DATA_ACK_XT    = 0x64,
+	CPL_ROCE_CQE          = 0x68,
+	CPL_ROCE_CQE_FW       = 0x69,
+	CPL_ROCE_CQE_ERR      = 0x6A,
+
+	CPL_SACK_REQ          = 0x70,
 
 	CPL_SET_LE_REQ        = 0x80,
 	CPL_PASS_OPEN_REQ6    = 0x81,
 	CPL_ACT_OPEN_REQ6     = 0x83,
 	CPL_TX_TLS_PDU        = 0x88,
 	CPL_TX_TLS_SFO        = 0x89,
-
 	CPL_TX_SEC_PDU        = 0x8A,
 	CPL_TX_TLS_ACK        = 0x8B,
+	CPL_RCB_UPD           = 0x8C,
 
+	CPL_SGE_FLR_FLUSH     = 0xA0,
 	CPL_RDMA_TERMINATE    = 0xA2,
 	CPL_RDMA_WRITE        = 0xA4,
 	CPL_SGE_EGR_UPDATE    = 0xA5,
@@ -138,15 +151,27 @@ enum {
 	CPL_TLS_DATA          = 0xB1,
 	CPL_ISCSI_DATA        = 0xB2,
 	CPL_FCOE_DATA         = 0xB3,
+	CPL_NVMT_DATA         = 0xB4,
+	CPL_NVMT_CMP          = 0xB5,
+	CPL_NVMT_CMP_IMM      = 0xB6,
+	CPL_NVMT_CMP_SRQ      = 0xB7,
+	CPL_ROCE_ACK_NAK_REQ  = 0xBC,
+	CPL_ROCE_ACK_NAK      = 0xBD,
 
 	CPL_FW4_MSG           = 0xC0,
 	CPL_FW4_PLD           = 0xC1,
+	CPL_RDMA_CQE_SRQ      = 0xC2,
+	CPL_ACCELERATOR_ACK   = 0xC4,
 	CPL_FW4_ACK           = 0xC3,
+	CPL_RX_PKT_IPSEC      = 0xC6,
 	CPL_SRQ_TABLE_RPL     = 0xCC,
+	CPL_TX_DATA_REQ       = 0xCF,
+
 	CPL_RX_PHYS_DSGL      = 0xD0,
 
 	CPL_FW6_MSG           = 0xE0,
 	CPL_FW6_PLD           = 0xE1,
+	CPL_ACCELERATOR_HDR   = 0xE8,
 	CPL_TX_TNL_LSO        = 0xEC,
 	CPL_TX_PKT_LSO        = 0xED,
 	CPL_TX_PKT_XT         = 0xEE,
@@ -233,6 +258,8 @@ enum {
 	ULP_MODE_TCPDDP        = 5,
 	ULP_MODE_FCOE          = 6,
 	ULP_MODE_TLS           = 8,
+	ULP_MODE_RDMA_V2       = 10,
+	ULP_MODE_NVMET         = 11,
 };
 
 enum {
@@ -325,9 +352,14 @@ union opcode_tid {
 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
 
 /* extract the TID from a CPL command */
-#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
+#define GET_TID(cmd) (G_TID(be32toh(OPCODE_TID(cmd))))
 #define GET_OPCODE(cmd) ((cmd)->ot.opcode)
 
+
+/*
+ * Note that this driver splits the 14b opaque atid into an 11b atid and a 3b
+ * cookie that is used to demux replies for shared CPLs.
+ */
 /* partitioning of TID fields that also carry a queue id */
 #define S_TID_TID    0
 #define M_TID_TID    0x7ff
@@ -717,7 +749,7 @@ struct cpl_pass_establish {
 struct cpl_pass_accept_req {
 	RSS_HDR
 	union opcode_tid ot;
-	__be16 rsvd;
+	__be16 ipsecen_outiphdrlen;
 	__be16 len;
 	__be32 hdr_len;
 	__be16 vlan;
@@ -775,6 +807,155 @@ struct cpl_pass_accept_req {
 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
 
+struct cpl_t7_pass_accept_req {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 ipsecen_to_outiphdrlen;
+	__be16 length;
+	__be32 ethhdrlen_to_rxchannel;
+	__be16 vlantag;
+	__be16 interface_to_mac_ix;
+	__be32 tos_ptid;
+	__be16 tcpmss;
+	__u8   tcpwsc;
+	__u8   tcptmstp_to_tcpunkn;
+};
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN	12
+#define M_CPL_T7_PASS_ACCEPT_REQ_IPSECEN	0x1
+#define V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_IPSECEN)
+#define F_CPL_PASS_T7_ACCEPT_REQ_IPSECEN	\
+    V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(1U)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE	10
+#define M_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE	0x3
+#define V_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE)
+#define G_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN	0
+#define M_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN	0x3ff
+#define V_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN	24
+#define M_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN	0xff
+#define V_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN	14
+#define M_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN	0x3ff
+#define V_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN	8
+#define M_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN	0x3f
+#define V_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL	0
+#define M_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL	0xf
+#define V_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL)
+#define G_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE	12
+#define M_CPL_T7_PASS_ACCEPT_REQ_INTERFACE	0xf
+#define V_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE)
+#define G_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_INTERFACE)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH	9
+#define M_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH	0x1
+#define V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH)
+#define G_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH)
+#define F_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH	\
+    V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(1U)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX		0
+#define M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX		0x1ff
+#define V_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX)
+#define G_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) & M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_TOS	24
+#define M_CPL_T7_PASS_ACCEPT_REQ_TOS	0xff
+#define V_CPL_T7_PASS_ACCEPT_REQ_TOS(x)	((x) << S_CPL_T7_PASS_ACCEPT_REQ_TOS)
+#define G_CPL_T7_PASS_ACCEPT_REQ_TOS(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TOS) & M_CPL_T7_PASS_ACCEPT_REQ_TOS)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_PTID		0
+#define M_CPL_T7_PASS_ACCEPT_REQ_PTID		0xffffff
+#define V_CPL_T7_PASS_ACCEPT_REQ_PTID(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_PTID)
+#define G_CPL_T7_PASS_ACCEPT_REQ_PTID(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_PTID) & M_CPL_T7_PASS_ACCEPT_REQ_PTID)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP	7
+#define M_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP	0x1
+#define V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP)
+#define G_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP)
+#define F_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP	\
+    V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(1U)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK	6
+#define M_CPL_T7_PASS_ACCEPT_REQ_TCPSACK	0x1
+#define V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK)
+#define G_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_TCPSACK)
+#define F_CPL_T7_PASS_ACCEPT_REQ_TCPSACK	\
+    V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(1U)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_TCPECN		5
+#define M_CPL_T7_PASS_ACCEPT_REQ_TCPECN		0x1
+#define V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPECN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPECN) & M_CPL_T7_PASS_ACCEPT_REQ_TCPECN)
+#define F_CPL_T7_PASS_ACCEPT_REQ_TCPECN		\
+    V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(1U)
+
+#define S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN	4
+#define M_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN	0x1
+#define V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x)	\
+    ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN)
+#define G_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x)	\
+    (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) & \
+     M_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN)
+#define F_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN	\
+    V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(1U)
+
 struct cpl_pass_accept_rpl {
 	WR_HDR;
 	union opcode_tid ot;
@@ -810,6 +991,7 @@ struct cpl_act_open_req {
 #define M_FILTER_TUPLE	0xFFFFFFFFFF
 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
+
 struct cpl_t5_act_open_req {
 	WR_HDR;
 	union opcode_tid ot;
@@ -843,6 +1025,26 @@ struct cpl_t6_act_open_req {
 #define V_AOPEN_FCOEMASK(x)	((x) << S_AOPEN_FCOEMASK)
 #define F_AOPEN_FCOEMASK	V_AOPEN_FCOEMASK(1U)
 
+struct cpl_t7_act_open_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be16 local_port;
+	__be16 peer_port;
+	__be32 local_ip;
+	__be32 peer_ip;
+	__be64 opt0;
+	__be32 iss;
+	__be32 opt2;
+	__be64 params;
+	__be32 rsvd2;
+	__be32 opt3;
+};
+
+#define S_T7_FILTER_TUPLE	1
+#define M_T7_FILTER_TUPLE	0x7FFFFFFFFFFFFFFFULL
+#define V_T7_FILTER_TUPLE(x)	((x) << S_T7_FILTER_TUPLE)
+#define G_T7_FILTER_TUPLE(x)	(((x) >> S_T7_FILTER_TUPLE) & M_T7_FILTER_TUPLE)
+
 struct cpl_act_open_req6 {
 	WR_HDR;
 	union opcode_tid ot;
@@ -889,6 +1091,23 @@ struct cpl_t6_act_open_req6 {
 	__be32 opt3;
 };
 
+struct cpl_t7_act_open_req6 {
+	WR_HDR;
+	union opcode_tid ot;
+	__be16 local_port;
+	__be16 peer_port;
+	__be64 local_ip_hi;
+	__be64 local_ip_lo;
+	__be64 peer_ip_hi;
+	__be64 peer_ip_lo;
+	__be64 opt0;
+	__be32 iss;
+	__be32 opt2;
+	__be64 params;
+	__be32 rsvd2;
+	__be32 opt3;
+};
+
 struct cpl_act_open_rpl {
 	RSS_HDR
 	union opcode_tid ot;
@@ -921,8 +1140,7 @@ struct cpl_get_tcb {
 	WR_HDR;
 	union opcode_tid ot;
 	__be16 reply_ctrl;
-	__u8 rsvd;
-	__u8 cookie;
+	__be16 cookie;
 };
 
 /* cpl_get_tcb.reply_ctrl fields */
@@ -931,10 +1149,20 @@ struct cpl_get_tcb {
 #define V_QUEUENO(x) ((x) << S_QUEUENO)
 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
 
+#define S_T7_QUEUENO    0
+#define M_T7_QUEUENO    0xFFF
+#define V_T7_QUEUENO(x) ((x) << S_T7_QUEUENO)
+#define G_T7_QUEUENO(x) (((x) >> S_T7_QUEUENO) & M_T7_QUEUENO)
+
 #define S_REPLY_CHAN    14
 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
 #define F_REPLY_CHAN    V_REPLY_CHAN(1U)
 
+#define S_T7_REPLY_CHAN		12
+#define M_T7_REPLY_CHAN		0x7
+#define V_T7_REPLY_CHAN(x)	((x) << S_T7_REPLY_CHAN)
+#define G_T7_REPLY_CHAN(x)	(((x) >> S_T7_REPLY_CHAN) & M_T7_REPLY_CHAN)
+
 #define S_NO_REPLY    15
 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
 #define F_NO_REPLY    V_NO_REPLY(1U)
@@ -1018,6 +1246,40 @@ struct cpl_close_listsvr_req {
 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
 #define F_LISTSVR_IPV6    V_LISTSVR_IPV6(1U)
 
+struct cpl_t7_close_listsvr_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be16 noreply_to_queue;
+	__be16 r2;
+};
+
+#define S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY	15
+#define M_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY	0x1
+#define V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x)	\
+    ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY)
+#define G_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x)	\
+    (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) & \
+     M_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY)
+#define F_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY	\
+    V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(1U)
+
+#define S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6		14
+#define M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6		0x1
+#define V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x)	\
+    ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6)
+#define G_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x)	\
+    (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) & M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6)
+#define F_CPL_T7_CLOSE_LISTSVR_REQ_IPV6		\
+    V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(1U)
+
+#define S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE	0
+#define M_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE	0xfff
+#define V_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x)	\
+    ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE)
+#define G_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x)	\
+    (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) & \
+     M_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE)
+
 struct cpl_close_listsvr_rpl {
 	RSS_HDR
 	union opcode_tid ot;
@@ -1250,6 +1512,71 @@ struct cpl_tx_data_ack {
 	__be32 snd_una;
 };
 
+struct cpl_tx_data_ack_xt {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 snd_una;
+	__be32 snd_end;
+	__be32 snd_nxt;
+	__be32 snd_adv;
+	__be16 rttvar;
+	__be16 srtt;
+	__be32 extinfoh[2];
+	__be32 extinfol[2];
+};
+
+struct cpl_tx_data_req {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 snd_una;
+	__be32 snd_end;
+	__be32 snd_nxt;
+	__be32 snd_adv;
+	__be16 rttvar;
+	__be16 srtt;
+};
+
+#define S_CPL_TX_DATA_REQ_TID		0
+#define M_CPL_TX_DATA_REQ_TID		0xffffff
+#define V_CPL_TX_DATA_REQ_TID(x)	((x) << S_CPL_TX_DATA_REQ_TID)
+#define G_CPL_TX_DATA_REQ_TID(x)	\
+    (((x) >> S_CPL_TX_DATA_REQ_TID) & M_CPL_TX_DATA_REQ_TID)
+
+struct cpl_sack_req {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 snd_una;
+	__be32 snd_end;
+	__be32 snd_nxt;
+	__be32 snd_adv;
+	__be16 rttvar;
+	__be16 srtt;
+	__be32 block1[2];
+	__be32 block2[2];
+	__be32 block3[2];
+};
+
+struct cpl_sge_flr_flush {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 cookievalue_cookiesel;
+};
+
+#define S_CPL_SGE_FLR_FLUSH_COOKIEVALUE	4
+#define M_CPL_SGE_FLR_FLUSH_COOKIEVALUE	0x3ff
+#define V_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \
+    ((x) << S_CPL_SGE_FLR_FLUSH_COOKIEVALUE)
+#define G_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \
+    (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIEVALUE) & \
+     M_CPL_SGE_FLR_FLUSH_COOKIEVALUE)
+
+#define S_CPL_SGE_FLR_FLUSH_COOKIESEL	0
+#define M_CPL_SGE_FLR_FLUSH_COOKIESEL	0xf
+#define V_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \
+    ((x) << S_CPL_SGE_FLR_FLUSH_COOKIESEL)
+#define G_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \
+    (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIESEL) & M_CPL_SGE_FLR_FLUSH_COOKIESEL)
+
 struct cpl_wr_ack {  /* XXX */
 	RSS_HDR
 	union opcode_tid ot;
@@ -1271,8 +1598,6 @@ struct cpl_tx_pkt {
 	struct cpl_tx_pkt_core c;
 };
 
-#define cpl_tx_pkt_xt cpl_tx_pkt
-
 /* cpl_tx_pkt_core.ctrl0 fields */
 #define S_TXPKT_VF    0
 #define M_TXPKT_VF    0xFF
@@ -1404,6 +1729,261 @@ struct cpl_tx_pkt {
 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
 #define F_TXPKT_L4CSUM_DIS    V_TXPKT_L4CSUM_DIS(1ULL)
 
+struct cpl_tx_pkt_xt {
+	WR_HDR;
+	__be32 ctrl0;
+	__be16 pack;
+	__be16 len;
+	__be32 ctrl1;
+	__be32 ctrl2;
+};
+
+/* cpl_tx_pkt_xt.core.ctrl0 fields */
+#define S_CPL_TX_PKT_XT_OPCODE		24
+#define M_CPL_TX_PKT_XT_OPCODE		0xff
+#define V_CPL_TX_PKT_XT_OPCODE(x)	((x) << S_CPL_TX_PKT_XT_OPCODE)
+#define G_CPL_TX_PKT_XT_OPCODE(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_OPCODE) & M_CPL_TX_PKT_XT_OPCODE)
+
+#define S_CPL_TX_PKT_XT_TIMESTAMP	23
+#define M_CPL_TX_PKT_XT_TIMESTAMP	0x1
+#define V_CPL_TX_PKT_XT_TIMESTAMP(x)	((x) << S_CPL_TX_PKT_XT_TIMESTAMP)
+#define G_CPL_TX_PKT_XT_TIMESTAMP(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_TIMESTAMP) & M_CPL_TX_PKT_XT_TIMESTAMP)
+#define F_CPL_TX_PKT_XT_TIMESTAMP	V_CPL_TX_PKT_XT_TIMESTAMP(1U)
+
+#define S_CPL_TX_PKT_XT_STATDISABLE	22
+#define M_CPL_TX_PKT_XT_STATDISABLE	0x1
+#define V_CPL_TX_PKT_XT_STATDISABLE(x)	((x) << S_CPL_TX_PKT_XT_STATDISABLE)
+#define G_CPL_TX_PKT_XT_STATDISABLE(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_STATDISABLE) & M_CPL_TX_PKT_XT_STATDISABLE)
+#define F_CPL_TX_PKT_XT_STATDISABLE	V_CPL_TX_PKT_XT_STATDISABLE(1U)
+
+#define S_CPL_TX_PKT_XT_FCSDIS		21
+#define M_CPL_TX_PKT_XT_FCSDIS		0x1
+#define V_CPL_TX_PKT_XT_FCSDIS(x)	((x) << S_CPL_TX_PKT_XT_FCSDIS)
+#define G_CPL_TX_PKT_XT_FCSDIS(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_FCSDIS) & M_CPL_TX_PKT_XT_FCSDIS)
+#define F_CPL_TX_PKT_XT_FCSDIS		V_CPL_TX_PKT_XT_FCSDIS(1U)
+
+#define S_CPL_TX_PKT_XT_STATSPECIAL	20
+#define M_CPL_TX_PKT_XT_STATSPECIAL	0x1
+#define V_CPL_TX_PKT_XT_STATSPECIAL(x)	((x) << S_CPL_TX_PKT_XT_STATSPECIAL)
+#define G_CPL_TX_PKT_XT_STATSPECIAL(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_STATSPECIAL) & M_CPL_TX_PKT_XT_STATSPECIAL)
+#define F_CPL_TX_PKT_XT_STATSPECIAL	V_CPL_TX_PKT_XT_STATSPECIAL(1U)
+
+#define S_CPL_TX_PKT_XT_INTERFACE	16
+#define M_CPL_TX_PKT_XT_INTERFACE	0xf
+#define V_CPL_TX_PKT_XT_INTERFACE(x)	((x) << S_CPL_TX_PKT_XT_INTERFACE)
+#define G_CPL_TX_PKT_XT_INTERFACE(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_INTERFACE) & M_CPL_TX_PKT_XT_INTERFACE)
+
+#define S_CPL_TX_PKT_XT_OVLAN		15
+#define M_CPL_TX_PKT_XT_OVLAN		0x1
+#define V_CPL_TX_PKT_XT_OVLAN(x)	((x) << S_CPL_TX_PKT_XT_OVLAN)
+#define G_CPL_TX_PKT_XT_OVLAN(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_OVLAN) & M_CPL_TX_PKT_XT_OVLAN)
+#define F_CPL_TX_PKT_XT_OVLAN		V_CPL_TX_PKT_XT_OVLAN(1U)
+
+#define S_CPL_TX_PKT_XT_OVLANIDX	12
+#define M_CPL_TX_PKT_XT_OVLANIDX	0x7
+#define V_CPL_TX_PKT_XT_OVLANIDX(x)	((x) << S_CPL_TX_PKT_XT_OVLANIDX)
+#define G_CPL_TX_PKT_XT_OVLANIDX(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_OVLANIDX) & M_CPL_TX_PKT_XT_OVLANIDX)
+
+#define S_CPL_TX_PKT_XT_VFVALID		11
+#define M_CPL_TX_PKT_XT_VFVALID		0x1
+#define V_CPL_TX_PKT_XT_VFVALID(x)	((x) << S_CPL_TX_PKT_XT_VFVALID)
+#define G_CPL_TX_PKT_XT_VFVALID(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_VFVALID) & M_CPL_TX_PKT_XT_VFVALID)
+#define F_CPL_TX_PKT_XT_VFVALID		V_CPL_TX_PKT_XT_VFVALID(1U)
+
+#define S_CPL_TX_PKT_XT_PF		8
+#define M_CPL_TX_PKT_XT_PF		0x7
+#define V_CPL_TX_PKT_XT_PF(x)		((x) << S_CPL_TX_PKT_XT_PF)
+#define G_CPL_TX_PKT_XT_PF(x)		\
+    (((x) >> S_CPL_TX_PKT_XT_PF) & M_CPL_TX_PKT_XT_PF)
+
+#define S_CPL_TX_PKT_XT_VF		0
+#define M_CPL_TX_PKT_XT_VF		0xff
+#define V_CPL_TX_PKT_XT_VF(x)		((x) << S_CPL_TX_PKT_XT_VF)
+#define G_CPL_TX_PKT_XT_VF(x)		\
+    (((x) >> S_CPL_TX_PKT_XT_VF) & M_CPL_TX_PKT_XT_VF)
+
+/* cpl_tx_pkt_xt.core.ctrl1 fields */
+#define S_CPL_TX_PKT_XT_L4CHKDISABLE	31
+#define M_CPL_TX_PKT_XT_L4CHKDISABLE	0x1
+#define V_CPL_TX_PKT_XT_L4CHKDISABLE(x)	((x) << S_CPL_TX_PKT_XT_L4CHKDISABLE)
+#define G_CPL_TX_PKT_XT_L4CHKDISABLE(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_L4CHKDISABLE) & M_CPL_TX_PKT_XT_L4CHKDISABLE)
+#define F_CPL_TX_PKT_XT_L4CHKDISABLE	V_CPL_TX_PKT_XT_L4CHKDISABLE(1U)
+
+#define S_CPL_TX_PKT_XT_L3CHKDISABLE	30
+#define M_CPL_TX_PKT_XT_L3CHKDISABLE	0x1
+#define V_CPL_TX_PKT_XT_L3CHKDISABLE(x)	((x) << S_CPL_TX_PKT_XT_L3CHKDISABLE)
+#define G_CPL_TX_PKT_XT_L3CHKDISABLE(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_L3CHKDISABLE) & M_CPL_TX_PKT_XT_L3CHKDISABLE)
+#define F_CPL_TX_PKT_XT_L3CHKDISABLE	V_CPL_TX_PKT_XT_L3CHKDISABLE(1U)
+
+#define S_CPL_TX_PKT_XT_OUTL4CHKEN	29
+#define M_CPL_TX_PKT_XT_OUTL4CHKEN	0x1
+#define V_CPL_TX_PKT_XT_OUTL4CHKEN(x)	((x) << S_CPL_TX_PKT_XT_OUTL4CHKEN)
+#define G_CPL_TX_PKT_XT_OUTL4CHKEN(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_OUTL4CHKEN) & M_CPL_TX_PKT_XT_OUTL4CHKEN)
+#define F_CPL_TX_PKT_XT_OUTL4CHKEN	V_CPL_TX_PKT_XT_OUTL4CHKEN(1U)
+
+#define S_CPL_TX_PKT_XT_IVLAN		28
+#define M_CPL_TX_PKT_XT_IVLAN		0x1
+#define V_CPL_TX_PKT_XT_IVLAN(x)	((x) << S_CPL_TX_PKT_XT_IVLAN)
+#define G_CPL_TX_PKT_XT_IVLAN(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_IVLAN) & M_CPL_TX_PKT_XT_IVLAN)
+#define F_CPL_TX_PKT_XT_IVLAN		V_CPL_TX_PKT_XT_IVLAN(1U)
+
+#define S_CPL_TX_PKT_XT_IVLANTAG	12
+#define M_CPL_TX_PKT_XT_IVLANTAG	0xffff
+#define V_CPL_TX_PKT_XT_IVLANTAG(x)	((x) << S_CPL_TX_PKT_XT_IVLANTAG)
+#define G_CPL_TX_PKT_XT_IVLANTAG(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_IVLANTAG) & M_CPL_TX_PKT_XT_IVLANTAG)
+
+#define S_CPL_TX_PKT_XT_CHKTYPE		8
+#define M_CPL_TX_PKT_XT_CHKTYPE		0xf
+#define V_CPL_TX_PKT_XT_CHKTYPE(x)	((x) << S_CPL_TX_PKT_XT_CHKTYPE)
+#define G_CPL_TX_PKT_XT_CHKTYPE(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_CHKTYPE) & M_CPL_TX_PKT_XT_CHKTYPE)
+
+#define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI 0
+#define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI 0xff
+#define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \
+    ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI)
+#define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \
+    (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) & \
+     M_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI)
+
+#define S_CPL_TX_PKT_XT_ETHHDRLEN	0
+#define M_CPL_TX_PKT_XT_ETHHDRLEN	0xff
+#define V_CPL_TX_PKT_XT_ETHHDRLEN(x)	((x) << S_CPL_TX_PKT_XT_ETHHDRLEN)
+#define G_CPL_TX_PKT_XT_ETHHDRLEN(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_ETHHDRLEN) & M_CPL_TX_PKT_XT_ETHHDRLEN)
+
+#define S_CPL_TX_PKT_XT_ROCECHKINSMODE	6
+#define M_CPL_TX_PKT_XT_ROCECHKINSMODE	0x3
+#define V_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \
+    ((x) << S_CPL_TX_PKT_XT_ROCECHKINSMODE)
+#define G_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \
+    (((x) >> S_CPL_TX_PKT_XT_ROCECHKINSMODE) & M_CPL_TX_PKT_XT_ROCECHKINSMODE)
+
+#define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI    0
+#define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI    0x3f
+#define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \
+    ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI)
+#define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \
+    (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) & \
+     M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI)
+
+#define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO    30
+#define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO    0x3
+#define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \
+    ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO)
+#define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \
+    (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) & \
+     M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO)
+
+/* cpl_tx_pkt_xt.core.ctrl2 fields */
+#define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 30
+#define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 0x3
+#define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \
+    ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO)
+#define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \
+    (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) & \
+     M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO)
+
+#define S_CPL_TX_PKT_XT_CHKSTARTOFFSET	20
+#define M_CPL_TX_PKT_XT_CHKSTARTOFFSET	0x3ff
+#define V_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \
+    ((x) << S_CPL_TX_PKT_XT_CHKSTARTOFFSET)
+#define G_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \
+    (((x) >> S_CPL_TX_PKT_XT_CHKSTARTOFFSET) & M_CPL_TX_PKT_XT_CHKSTARTOFFSET)
+
+#define S_CPL_TX_PKT_XT_IPHDRLEN	20
+#define M_CPL_TX_PKT_XT_IPHDRLEN	0xfff
+#define V_CPL_TX_PKT_XT_IPHDRLEN(x)	((x) << S_CPL_TX_PKT_XT_IPHDRLEN)
+#define G_CPL_TX_PKT_XT_IPHDRLEN(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_IPHDRLEN) & M_CPL_TX_PKT_XT_IPHDRLEN)
+
+#define S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET 20
+#define M_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET 0x3ff
+#define V_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \
+    ((x) << S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET)
+#define G_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \
+    (((x) >> S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) & \
+     M_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET)
+
+#define S_CPL_TX_PKT_XT_CHKSTOPOFFSET	12
+#define M_CPL_TX_PKT_XT_CHKSTOPOFFSET	0xff
+#define V_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \
+    ((x) << S_CPL_TX_PKT_XT_CHKSTOPOFFSET)
+#define G_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \
+    (((x) >> S_CPL_TX_PKT_XT_CHKSTOPOFFSET) & M_CPL_TX_PKT_XT_CHKSTOPOFFSET)
+
+#define S_CPL_TX_PKT_XT_IPSECIDX	0
+#define M_CPL_TX_PKT_XT_IPSECIDX	0xfff
+#define V_CPL_TX_PKT_XT_IPSECIDX(x)	((x) << S_CPL_TX_PKT_XT_IPSECIDX)
+#define G_CPL_TX_PKT_XT_IPSECIDX(x)	\
+    (((x) >> S_CPL_TX_PKT_XT_IPSECIDX) & M_CPL_TX_PKT_XT_IPSECIDX)
+
+#define S_CPL_TX_TNL_LSO_BTH_OPCODE             24
+#define M_CPL_TX_TNL_LSO_BTH_OPCODE             0xff
+#define V_CPL_TX_TNL_LSO_BTH_OPCODE(x)  ((x) << S_CPL_TX_TNL_LSO_BTH_OPCODE)
+#define G_CPL_TX_TNL_LSO_BTH_OPCODE(x)  \
+                (((x) >> S_CPL_TX_TNL_LSO_BTH_OPCODE) & \
+                 M_CPL_TX_TNL_LSO_BTH_OPCODE)
+
+#define S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN               0
+#define M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN               0xffffff
+#define V_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x)    \
+                ((x) << S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN)
+#define G_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x)    \
+                (((x) >> S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) & \
+                 M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN)
+
+#define S_CPL_TX_TNL_LSO_MSS_TVER               8
+#define M_CPL_TX_TNL_LSO_MSS_TVER               0xf
+#define V_CPL_TX_TNL_LSO_MSS_TVER(x)    ((x) << S_CPL_TX_TNL_LSO_MSS_TVER)
+#define G_CPL_TX_TNL_LSO_MSS_TVER(x)            \
+    (((x) >> S_CPL_TX_TNL_LSO_MSS_TVER) & M_CPL_TX_TNL_LSO_MSS_TVER)
+
+#define S_CPL_TX_TNL_LSO_MSS_M          7
+#define M_CPL_TX_TNL_LSO_MSS_M          0x1
+#define V_CPL_TX_TNL_LSO_MSS_M(x)       ((x) << S_CPL_TX_TNL_LSO_MSS_M)
+#define G_CPL_TX_TNL_LSO_MSS_M(x)               \
+    (((x) >> S_CPL_TX_TNL_LSO_MSS_M) & M_CPL_TX_TNL_LSO_MSS_M)
+
+#define S_CPL_TX_TNL_LSO_MSS_PMTU               4
+#define M_CPL_TX_TNL_LSO_MSS_PMTU               0x7
+#define V_CPL_TX_TNL_LSO_MSS_PMTU(x)    ((x) << S_CPL_TX_TNL_LSO_MSS_PMTU)
+#define G_CPL_TX_TNL_LSO_MSS_PMTU(x)            \
+    (((x) >> S_CPL_TX_TNL_LSO_MSS_PMTU) & M_CPL_TX_TNL_LSO_MSS_PMTU)
+
+#define S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR                3
+#define M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR                0x1
+#define V_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x)     \
+        ((x) << S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR)
+#define G_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x)             \
+    (((x) >> S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) & M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR)
+
+#define S_CPL_TX_TNL_LSO_MSS_ACKREQ             1
+#define M_CPL_TX_TNL_LSO_MSS_ACKREQ             0x3
+#define V_CPL_TX_TNL_LSO_MSS_ACKREQ(x)  ((x) << S_CPL_TX_TNL_LSO_MSS_ACKREQ)
+#define G_CPL_TX_TNL_LSO_MSS_ACKREQ(x)          \
+    (((x) >> S_CPL_TX_TNL_LSO_MSS_ACKREQ) & M_CPL_TX_TNL_LSO_MSS_ACKREQ)
+
+#define S_CPL_TX_TNL_LSO_MSS_SE         0
+#define M_CPL_TX_TNL_LSO_MSS_SE         0x1
+#define V_CPL_TX_TNL_LSO_MSS_SE(x)      ((x) << S_CPL_TX_TNL_LSO_MSS_SE)
+#define G_CPL_TX_TNL_LSO_MSS_SE(x)              \
+    (((x) >> S_CPL_TX_TNL_LSO_MSS_SE) & M_CPL_TX_TNL_LSO_MSS_SE)
+
 struct cpl_tx_pkt_lso_core {
 	__be32 lso_ctrl;
 	__be16 ipid_ofst;
@@ -1600,6 +2180,100 @@ struct cpl_tx_data_iso {
     (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \
      M_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
 
+struct cpl_t7_tx_data_iso {
+	__be32 op_to_scsi;
+	__u8   nvme_tcp_pkd;
+	__u8   ahs;
+	__be16 mpdu;
+	__be32 burst;
+	__be32 size;
+	__be32 num_pi_bytes_seglen_offset;
+	__be32 datasn_offset;
+	__be32 buffer_offset;
+	__be32 reserved3;
+};
+
+#define S_CPL_T7_TX_DATA_ISO_OPCODE	24
+#define M_CPL_T7_TX_DATA_ISO_OPCODE	0xff
+#define V_CPL_T7_TX_DATA_ISO_OPCODE(x)	((x) << S_CPL_T7_TX_DATA_ISO_OPCODE)
+#define G_CPL_T7_TX_DATA_ISO_OPCODE(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_OPCODE) & M_CPL_T7_TX_DATA_ISO_OPCODE)
+
+#define S_CPL_T7_TX_DATA_ISO_FIRST	23
+#define M_CPL_T7_TX_DATA_ISO_FIRST	0x1
+#define V_CPL_T7_TX_DATA_ISO_FIRST(x)	((x) << S_CPL_T7_TX_DATA_ISO_FIRST)
+#define G_CPL_T7_TX_DATA_ISO_FIRST(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_FIRST) & M_CPL_T7_TX_DATA_ISO_FIRST)
+#define F_CPL_T7_TX_DATA_ISO_FIRST	V_CPL_T7_TX_DATA_ISO_FIRST(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_LAST	22
+#define M_CPL_T7_TX_DATA_ISO_LAST	0x1
+#define V_CPL_T7_TX_DATA_ISO_LAST(x)	((x) << S_CPL_T7_TX_DATA_ISO_LAST)
+#define G_CPL_T7_TX_DATA_ISO_LAST(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_LAST) & M_CPL_T7_TX_DATA_ISO_LAST)
+#define F_CPL_T7_TX_DATA_ISO_LAST	V_CPL_T7_TX_DATA_ISO_LAST(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_CPLHDRLEN		21
+#define M_CPL_T7_TX_DATA_ISO_CPLHDRLEN		0x1
+#define V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x)	\
+    ((x) << S_CPL_T7_TX_DATA_ISO_CPLHDRLEN)
+#define G_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_CPLHDRLEN) & M_CPL_T7_TX_DATA_ISO_CPLHDRLEN)
+#define F_CPL_T7_TX_DATA_ISO_CPLHDRLEN	V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_HDRCRC	20
+#define M_CPL_T7_TX_DATA_ISO_HDRCRC	0x1
+#define V_CPL_T7_TX_DATA_ISO_HDRCRC(x)	((x) << S_CPL_T7_TX_DATA_ISO_HDRCRC)
+#define G_CPL_T7_TX_DATA_ISO_HDRCRC(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_HDRCRC) & M_CPL_T7_TX_DATA_ISO_HDRCRC)
+#define F_CPL_T7_TX_DATA_ISO_HDRCRC	V_CPL_T7_TX_DATA_ISO_HDRCRC(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_PLDCRC	19
+#define M_CPL_T7_TX_DATA_ISO_PLDCRC	0x1
+#define V_CPL_T7_TX_DATA_ISO_PLDCRC(x)	((x) << S_CPL_T7_TX_DATA_ISO_PLDCRC)
+#define G_CPL_T7_TX_DATA_ISO_PLDCRC(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_PLDCRC) & M_CPL_T7_TX_DATA_ISO_PLDCRC)
+#define F_CPL_T7_TX_DATA_ISO_PLDCRC	V_CPL_T7_TX_DATA_ISO_PLDCRC(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_IMMEDIATE		18
+#define M_CPL_T7_TX_DATA_ISO_IMMEDIATE		0x1
+#define V_CPL_T7_TX_DATA_ISO_IMMEDIATE(x)	\
+    ((x) << S_CPL_T7_TX_DATA_ISO_IMMEDIATE)
+#define G_CPL_T7_TX_DATA_ISO_IMMEDIATE(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_IMMEDIATE) & M_CPL_T7_TX_DATA_ISO_IMMEDIATE)
+#define F_CPL_T7_TX_DATA_ISO_IMMEDIATE		\
+    V_CPL_T7_TX_DATA_ISO_IMMEDIATE(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_SCSI	16
+#define M_CPL_T7_TX_DATA_ISO_SCSI	0x3
+#define V_CPL_T7_TX_DATA_ISO_SCSI(x)	((x) << S_CPL_T7_TX_DATA_ISO_SCSI)
+#define G_CPL_T7_TX_DATA_ISO_SCSI(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_SCSI) & M_CPL_T7_TX_DATA_ISO_SCSI)
+
+#define S_CPL_T7_TX_DATA_ISO_NVME_TCP		0
+#define M_CPL_T7_TX_DATA_ISO_NVME_TCP		0x1
+#define V_CPL_T7_TX_DATA_ISO_NVME_TCP(x)	\
+    ((x) << S_CPL_T7_TX_DATA_ISO_NVME_TCP)
+#define G_CPL_T7_TX_DATA_ISO_NVME_TCP(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_NVME_TCP) & M_CPL_T7_TX_DATA_ISO_NVME_TCP)
+#define F_CPL_T7_TX_DATA_ISO_NVME_TCP		\
+    V_CPL_T7_TX_DATA_ISO_NVME_TCP(1U)
+
+#define S_CPL_T7_TX_DATA_ISO_NUMPIBYTES		24
+#define M_CPL_T7_TX_DATA_ISO_NUMPIBYTES		0xff
+#define V_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x)	\
+    ((x) << S_CPL_T7_TX_DATA_ISO_NUMPIBYTES)
+#define G_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x)	\
+    (((x) >> S_CPL_T7_TX_DATA_ISO_NUMPIBYTES) & M_CPL_T7_TX_DATA_ISO_NUMPIBYTES)
+
+#define S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET	0
+#define M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET	0xffffff
+#define V_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \
+    ((x) << S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET)
+#define G_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \
+    (((x) >> S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) & \
+     M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET)
+
 struct cpl_iscsi_hdr {
 	RSS_HDR
 	union opcode_tid ot;
@@ -2324,6 +2998,18 @@ struct cpl_l2t_write_req {
 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
 #define F_L2T_W_NOREPLY    V_L2T_W_NOREPLY(1U)
 
+
+/* cpl_l2t_write_req.vlan fields */
+#define S_L2T_VLANTAG    0
+#define M_L2T_VLANTAG    0xFFF
+#define V_L2T_VLANTAG(x) ((x) << S_L2T_VLANTAG)
+#define G_L2T_VLANTAG(x) (((x) >> S_L2T_VLANTAG) & M_L2T_VLANTAG)
+
+#define S_L2T_VLANPRIO    13
+#define M_L2T_VLANPRIO    0x7
+#define V_L2T_VLANPRIO(x) ((x) << S_L2T_VLANPRIO)
+#define G_L2T_VLANPRIO(x) (((x) >> S_L2T_VLANPRIO) & M_L2T_VLANPRIO)
+
 #define CPL_L2T_VLAN_NONE 0xfff
 
 struct cpl_l2t_write_rpl {
@@ -2400,6 +3086,175 @@ struct cpl_srq_table_rpl {
 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX)
 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX)
 
+struct cpl_t7_srq_table_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 noreply_to_index;
+	__be16 srqlimit_pkd;
+	__be16 cqid;
+	__be16 xdid;
+	__be16 pdid;
+	__be32 quelen_quebase;
+	__be32 curmsn_maxmsn;
+};
+
+#define S_CPL_T7_SRQ_TABLE_REQ_NOREPLY		31
+#define M_CPL_T7_SRQ_TABLE_REQ_NOREPLY		0x1
+#define V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_NOREPLY)
+#define G_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_NOREPLY) & M_CPL_T7_SRQ_TABLE_REQ_NOREPLY)
+#define F_CPL_T7_SRQ_TABLE_REQ_NOREPLY		\
+    V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(1U)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_WRITE	30
+#define M_CPL_T7_SRQ_TABLE_REQ_WRITE	0x1
+#define V_CPL_T7_SRQ_TABLE_REQ_WRITE(x)	((x) << S_CPL_T7_SRQ_TABLE_REQ_WRITE)
+#define G_CPL_T7_SRQ_TABLE_REQ_WRITE(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_WRITE) & M_CPL_T7_SRQ_TABLE_REQ_WRITE)
+#define F_CPL_T7_SRQ_TABLE_REQ_WRITE	V_CPL_T7_SRQ_TABLE_REQ_WRITE(1U)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_INCR	28
+#define M_CPL_T7_SRQ_TABLE_REQ_INCR	0x3
+#define V_CPL_T7_SRQ_TABLE_REQ_INCR(x)	((x) << S_CPL_T7_SRQ_TABLE_REQ_INCR)
+#define G_CPL_T7_SRQ_TABLE_REQ_INCR(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INCR) & M_CPL_T7_SRQ_TABLE_REQ_INCR)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_OVER	24
+#define M_CPL_T7_SRQ_TABLE_REQ_OVER	0xf
+#define V_CPL_T7_SRQ_TABLE_REQ_OVER(x)	((x) << S_CPL_T7_SRQ_TABLE_REQ_OVER)
+#define G_CPL_T7_SRQ_TABLE_REQ_OVER(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_OVER) & M_CPL_T7_SRQ_TABLE_REQ_OVER)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD		23
+#define M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD		0x1
+#define V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD)
+#define G_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) & M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD)
+#define F_CPL_T7_SRQ_TABLE_REQ_LIMITUPD	V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(1U)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_INDEX	0
+#define M_CPL_T7_SRQ_TABLE_REQ_INDEX	0x3ff
+#define V_CPL_T7_SRQ_TABLE_REQ_INDEX(x)	((x) << S_CPL_T7_SRQ_TABLE_REQ_INDEX)
+#define G_CPL_T7_SRQ_TABLE_REQ_INDEX(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INDEX) & M_CPL_T7_SRQ_TABLE_REQ_INDEX)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT		0
+#define M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT		0x3f
+#define V_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT)
+#define G_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_QUELEN		28
+#define M_CPL_T7_SRQ_TABLE_REQ_QUELEN		0xf
+#define V_CPL_T7_SRQ_TABLE_REQ_QUELEN(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUELEN)
+#define G_CPL_T7_SRQ_TABLE_REQ_QUELEN(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUELEN) & M_CPL_T7_SRQ_TABLE_REQ_QUELEN)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_QUEBASE		0
+#define M_CPL_T7_SRQ_TABLE_REQ_QUEBASE		0x3ffffff
+#define V_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUEBASE)
+#define G_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUEBASE) & M_CPL_T7_SRQ_TABLE_REQ_QUEBASE)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_CURMSN		16
+#define M_CPL_T7_SRQ_TABLE_REQ_CURMSN		0xffff
+#define V_CPL_T7_SRQ_TABLE_REQ_CURMSN(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_CURMSN)
+#define G_CPL_T7_SRQ_TABLE_REQ_CURMSN(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_CURMSN) & M_CPL_T7_SRQ_TABLE_REQ_CURMSN)
+
+#define S_CPL_T7_SRQ_TABLE_REQ_MAXMSN		0
+#define M_CPL_T7_SRQ_TABLE_REQ_MAXMSN		0xffff
+#define V_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_REQ_MAXMSN)
+#define G_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_REQ_MAXMSN) & M_CPL_T7_SRQ_TABLE_REQ_MAXMSN)
+
+struct cpl_t7_srq_table_rpl {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 status_index;
+	__be16 srqlimit_pkd;
+	__be16 cqid;
+	__be16 xdid;
+	__be16 pdid;
+	__be32 quelen_quebase;
+	__be32 curmsn_maxmsn;
+};
+
+#define S_CPL_T7_SRQ_TABLE_RPL_STATUS		24
+#define M_CPL_T7_SRQ_TABLE_RPL_STATUS		0xff
+#define V_CPL_T7_SRQ_TABLE_RPL_STATUS(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_RPL_STATUS)
+#define G_CPL_T7_SRQ_TABLE_RPL_STATUS(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_STATUS) & M_CPL_T7_SRQ_TABLE_RPL_STATUS)
+
+#define S_CPL_T7_SRQ_TABLE_RPL_INDEX	0
+#define M_CPL_T7_SRQ_TABLE_RPL_INDEX	0x3ff
+#define V_CPL_T7_SRQ_TABLE_RPL_INDEX(x)	((x) << S_CPL_T7_SRQ_TABLE_RPL_INDEX)
+#define G_CPL_T7_SRQ_TABLE_RPL_INDEX(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_INDEX) & M_CPL_T7_SRQ_TABLE_RPL_INDEX)
+
+#define S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT		0
+#define M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT		0x3f
+#define V_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT)
+#define G_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT)
+
+#define S_CPL_T7_SRQ_TABLE_RPL_QUELEN		28
+#define M_CPL_T7_SRQ_TABLE_RPL_QUELEN		0xf
+#define V_CPL_T7_SRQ_TABLE_RPL_QUELEN(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUELEN)
+#define G_CPL_T7_SRQ_TABLE_RPL_QUELEN(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUELEN) & M_CPL_T7_SRQ_TABLE_RPL_QUELEN)
+
+#define S_CPL_T7_SRQ_TABLE_RPL_QUEBASE		0
+#define M_CPL_T7_SRQ_TABLE_RPL_QUEBASE		0x3ffffff
+#define V_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUEBASE)
+#define G_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUEBASE) & M_CPL_T7_SRQ_TABLE_RPL_QUEBASE)
+
+#define S_CPL_T7_SRQ_TABLE_RPL_CURMSN		16
+#define M_CPL_T7_SRQ_TABLE_RPL_CURMSN		0xffff
+#define V_CPL_T7_SRQ_TABLE_RPL_CURMSN(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_RPL_CURMSN)
+#define G_CPL_T7_SRQ_TABLE_RPL_CURMSN(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_CURMSN) & M_CPL_T7_SRQ_TABLE_RPL_CURMSN)
+
+#define S_CPL_T7_SRQ_TABLE_RPL_MAXMSN		0
+#define M_CPL_T7_SRQ_TABLE_RPL_MAXMSN		0xffff
+#define V_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x)	\
+    ((x) << S_CPL_T7_SRQ_TABLE_RPL_MAXMSN)
+#define G_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x)	\
+    (((x) >> S_CPL_T7_SRQ_TABLE_RPL_MAXMSN) & M_CPL_T7_SRQ_TABLE_RPL_MAXMSN)
+
+struct cpl_rdma_async_event {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 EventInfo;
+};
+
+#define S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE 16
+#define M_CPL_RDMA_ASYNC_EVENT_EVENTTYPE 0xf
+#define V_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \
+    ((x) << S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE)
+#define G_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \
+    (((x) >> S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) & \
+     M_CPL_RDMA_ASYNC_EVENT_EVENTTYPE)
+
+#define S_CPL_RDMA_ASYNC_EVENT_INDEX	0
+#define M_CPL_RDMA_ASYNC_EVENT_INDEX	0xffff
+#define V_CPL_RDMA_ASYNC_EVENT_INDEX(x)	((x) << S_CPL_RDMA_ASYNC_EVENT_INDEX)
+#define G_CPL_RDMA_ASYNC_EVENT_INDEX(x)	\
+    (((x) >> S_CPL_RDMA_ASYNC_EVENT_INDEX) & M_CPL_RDMA_ASYNC_EVENT_INDEX)
+
 struct cpl_smt_write_req {
 	WR_HDR;
 	union opcode_tid ot;
@@ -2479,6 +3334,118 @@ struct cpl_smt_read_rpl {
 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
 #define F_SMTW_VF_VLD    V_SMTW_VF_VLD(1U)
 
+struct cpl_t7_smt_write_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 noreply_to_mtu;
+	union smt_write_req {
+		struct smt_write_req_pfvf {
+			__be64 tagvalue;
+			__be32 pfvf_smac_hi;
+			__be32 smac_lo;
+			__be64 tagext;
+		} pfvf;
+		struct smt_write_req_ipv4 {
+			__be32 srcipv4;
+			__be32 destipv4;
+		} ipv4;
+		struct smt_write_req_ipv6 {
+			__be64 ipv6ms;
+			__be64 ipv6ls;
+		} ipv6;
+	} u;
+};
+
+#define S_CPL_T7_SMT_WRITE_REQ_NOREPLY		31
+#define M_CPL_T7_SMT_WRITE_REQ_NOREPLY		0x1
+#define V_CPL_T7_SMT_WRITE_REQ_NOREPLY(x)	\
+    ((x) << S_CPL_T7_SMT_WRITE_REQ_NOREPLY)
+#define G_CPL_T7_SMT_WRITE_REQ_NOREPLY(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_NOREPLY) & M_CPL_T7_SMT_WRITE_REQ_NOREPLY)
+#define F_CPL_T7_SMT_WRITE_REQ_NOREPLY		\
+    V_CPL_T7_SMT_WRITE_REQ_NOREPLY(1U)
+
+#define S_CPL_T7_SMT_WRITE_REQ_TAGINSERT	30
+#define M_CPL_T7_SMT_WRITE_REQ_TAGINSERT	0x1
+#define V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x)	\
+    ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGINSERT)
+#define G_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGINSERT) & \
+     M_CPL_T7_SMT_WRITE_REQ_TAGINSERT)
+#define F_CPL_T7_SMT_WRITE_REQ_TAGINSERT	\
+    V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(1U)
+
+#define S_CPL_T7_SMT_WRITE_REQ_TAGTYPE		28
+#define M_CPL_T7_SMT_WRITE_REQ_TAGTYPE		0x3
+#define V_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x)	\
+    ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGTYPE)
+#define G_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGTYPE) & M_CPL_T7_SMT_WRITE_REQ_TAGTYPE)
+
+#define S_CPL_T7_SMT_WRITE_REQ_INDEX	20
+#define M_CPL_T7_SMT_WRITE_REQ_INDEX	0xff
+#define V_CPL_T7_SMT_WRITE_REQ_INDEX(x)	((x) << S_CPL_T7_SMT_WRITE_REQ_INDEX)
+#define G_CPL_T7_SMT_WRITE_REQ_INDEX(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_INDEX) & M_CPL_T7_SMT_WRITE_REQ_INDEX)
+
+#define S_CPL_T7_SMT_WRITE_REQ_OVLAN	16
+#define M_CPL_T7_SMT_WRITE_REQ_OVLAN	0xf
+#define V_CPL_T7_SMT_WRITE_REQ_OVLAN(x)	((x) << S_CPL_T7_SMT_WRITE_REQ_OVLAN)
+#define G_CPL_T7_SMT_WRITE_REQ_OVLAN(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_OVLAN) & M_CPL_T7_SMT_WRITE_REQ_OVLAN)
+
+#define S_CPL_T7_SMT_WRITE_REQ_IPSEC	14
+#define M_CPL_T7_SMT_WRITE_REQ_IPSEC	0x1
+#define V_CPL_T7_SMT_WRITE_REQ_IPSEC(x)	((x) << S_CPL_T7_SMT_WRITE_REQ_IPSEC)
+#define G_CPL_T7_SMT_WRITE_REQ_IPSEC(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_IPSEC) & M_CPL_T7_SMT_WRITE_REQ_IPSEC)
+#define F_CPL_T7_SMT_WRITE_REQ_IPSEC	V_CPL_T7_SMT_WRITE_REQ_IPSEC(1U)
+
+#define S_CPL_T7_SMT_WRITE_REQ_MTU	0
+#define M_CPL_T7_SMT_WRITE_REQ_MTU	0x3fff
+#define V_CPL_T7_SMT_WRITE_REQ_MTU(x)	((x) << S_CPL_T7_SMT_WRITE_REQ_MTU)
+#define G_CPL_T7_SMT_WRITE_REQ_MTU(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_MTU) & M_CPL_T7_SMT_WRITE_REQ_MTU)
+
+#define S_CPL_T7_SMT_WRITE_REQ_PFVF	16
+#define M_CPL_T7_SMT_WRITE_REQ_PFVF	0xfff
+#define V_CPL_T7_SMT_WRITE_REQ_PFVF(x)	((x) << S_CPL_T7_SMT_WRITE_REQ_PFVF)
+#define G_CPL_T7_SMT_WRITE_REQ_PFVF(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_PFVF) & M_CPL_T7_SMT_WRITE_REQ_PFVF)
+
+#define S_CPL_T7_SMT_WRITE_REQ_SMAC_HI		0
+#define M_CPL_T7_SMT_WRITE_REQ_SMAC_HI		0xffff
+#define V_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x)	\
+    ((x) << S_CPL_T7_SMT_WRITE_REQ_SMAC_HI)
+#define G_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x)	\
+    (((x) >> S_CPL_T7_SMT_WRITE_REQ_SMAC_HI) & M_CPL_T7_SMT_WRITE_REQ_SMAC_HI)
+
+struct cpl_t7_smt_read_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 index_to_ipsecidx;
+};
+
+#define S_CPL_T7_SMT_READ_REQ_INDEX	20
+#define M_CPL_T7_SMT_READ_REQ_INDEX	0xff
+#define V_CPL_T7_SMT_READ_REQ_INDEX(x)	((x) << S_CPL_T7_SMT_READ_REQ_INDEX)
+#define G_CPL_T7_SMT_READ_REQ_INDEX(x)	\
+    (((x) >> S_CPL_SMT_READ_REQ_INDEX) & M_CPL_T7_SMT_READ_REQ_INDEX)
+
+#define S_CPL_T7_SMT_READ_REQ_IPSEC	14
+#define M_CPL_T7_SMT_READ_REQ_IPSEC	0x1
+#define V_CPL_T7_SMT_READ_REQ_IPSEC(x)	((x) << S_CPL_T7_SMT_READ_REQ_IPSEC)
+#define G_CPL_T7_SMT_READ_REQ_IPSEC(x)	\
+    (((x) >> S_CPL_T7_SMT_READ_REQ_IPSEC) & M_CPL_T7_SMT_READ_REQ_IPSEC)
+#define F_CPL_T7_SMT_READ_REQ_IPSEC	V_CPL_T7_SMT_READ_REQ_IPSEC(1U)
+
+#define S_CPL_T7_SMT_READ_REQ_IPSECIDX		0
+#define M_CPL_T7_SMT_READ_REQ_IPSECIDX		0x1fff
+#define V_CPL_T7_SMT_READ_REQ_IPSECIDX(x)	\
+    ((x) << S_CPL_T7_SMT_READ_REQ_IPSECIDX)
+#define G_CPL_T7_SMT_READ_REQ_IPSECIDX(x)	\
+    (((x) >> S_CPL_T7_SMT_READ_REQ_IPSECIDX) & M_CPL_T7_SMT_READ_REQ_IPSECIDX)
+
 struct cpl_tag_write_req {
 	WR_HDR;
 	union opcode_tid ot;
@@ -2611,6 +3578,352 @@ struct cpl_pkt_notify {
 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN)
 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN)
 
+struct cpl_t7_pkt_notify {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 r1;
+	__be16 length;
+	__be32 ethhdrlen_to_macindex;
+	__be32 lineinfo;
+};
+
+#define S_CPL_T7_PKT_NOTIFY_ETHHDRLEN		24
+#define M_CPL_T7_PKT_NOTIFY_ETHHDRLEN		0xff
+#define V_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x)	\
+    ((x) << S_CPL_T7_PKT_NOTIFY_ETHHDRLEN)
+#define G_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x)	\
+    (((x) >> S_CPL_T7_PKT_NOTIFY_ETHHDRLEN) & M_CPL_T7_PKT_NOTIFY_ETHHDRLEN)
+
+#define S_CPL_T7_PKT_NOTIFY_IPHDRLEN	18
+#define M_CPL_T7_PKT_NOTIFY_IPHDRLEN	0x3f
+#define V_CPL_T7_PKT_NOTIFY_IPHDRLEN(x)	((x) << S_CPL_T7_PKT_NOTIFY_IPHDRLEN)
+#define G_CPL_T7_PKT_NOTIFY_IPHDRLEN(x)	\
+    (((x) >> S_CPL_T7_PKT_NOTIFY_IPHDRLEN) & M_CPL_T7_PKT_NOTIFY_IPHDRLEN)
+
+#define S_CPL_T7_PKT_NOTIFY_TCPHDRLEN		14
+#define M_CPL_T7_PKT_NOTIFY_TCPHDRLEN		0xf
+#define V_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x)	\
+    ((x) << S_CPL_T7_PKT_NOTIFY_TCPHDRLEN)
+#define G_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x)	\
+    (((x) >> S_CPL_T7_PKT_NOTIFY_TCPHDRLEN) & M_CPL_T7_PKT_NOTIFY_TCPHDRLEN)
+
+#define S_CPL_T7_PKT_NOTIFY_INTERFACE		10
+#define M_CPL_T7_PKT_NOTIFY_INTERFACE		0xf
+#define V_CPL_T7_PKT_NOTIFY_INTERFACE(x)	\
+    ((x) << S_CPL_T7_PKT_NOTIFY_INTERFACE)
+#define G_CPL_T7_PKT_NOTIFY_INTERFACE(x)	\
+    (((x) >> S_CPL_T7_PKT_NOTIFY_INTERFACE) & M_CPL_T7_PKT_NOTIFY_INTERFACE)
+
+#define S_CPL_T7_PKT_NOTIFY_MACINDEX	0
+#define M_CPL_T7_PKT_NOTIFY_MACINDEX	0x1ff
+#define V_CPL_T7_PKT_NOTIFY_MACINDEX(x)	((x) << S_CPL_T7_PKT_NOTIFY_MACINDEX)
+#define G_CPL_T7_PKT_NOTIFY_MACINDEX(x)	\
+    (((x) >> S_CPL_T7_PKT_NOTIFY_MACINDEX) & M_CPL_T7_PKT_NOTIFY_MACINDEX)
+
+struct cpl_rdma_cqe {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+};
+
+#define S_CPL_RDMA_CQE_RSSCTRL		16
+#define M_CPL_RDMA_CQE_RSSCTRL		0xff
+#define V_CPL_RDMA_CQE_RSSCTRL(x)	((x) << S_CPL_RDMA_CQE_RSSCTRL)
+#define G_CPL_RDMA_CQE_RSSCTRL(x)	\
+    (((x) >> S_CPL_RDMA_CQE_RSSCTRL) & M_CPL_RDMA_CQE_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_CQID	0
+#define M_CPL_RDMA_CQE_CQID	0xffff
+#define V_CPL_RDMA_CQE_CQID(x)	((x) << S_CPL_RDMA_CQE_CQID)
+#define G_CPL_RDMA_CQE_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_CQID) & M_CPL_RDMA_CQE_CQID)
+
+#define S_CPL_RDMA_CQE_TID	8
+#define M_CPL_RDMA_CQE_TID	0xfffff
+#define V_CPL_RDMA_CQE_TID(x)	((x) << S_CPL_RDMA_CQE_TID)
+#define G_CPL_RDMA_CQE_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_TID) & M_CPL_RDMA_CQE_TID)
+
+#define S_CPL_RDMA_CQE_FLITCNT		0
+#define M_CPL_RDMA_CQE_FLITCNT		0xff
+#define V_CPL_RDMA_CQE_FLITCNT(x)	((x) << S_CPL_RDMA_CQE_FLITCNT)
+#define G_CPL_RDMA_CQE_FLITCNT(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FLITCNT) & M_CPL_RDMA_CQE_FLITCNT)
+
+#define S_CPL_RDMA_CQE_QPID		12
+#define M_CPL_RDMA_CQE_QPID		0xfffff
+#define V_CPL_RDMA_CQE_QPID(x)		((x) << S_CPL_RDMA_CQE_QPID)
+#define G_CPL_RDMA_CQE_QPID(x)		\
+    (((x) >> S_CPL_RDMA_CQE_QPID) & M_CPL_RDMA_CQE_QPID)
+
+#define S_CPL_RDMA_CQE_GENERATION_BIT	10
+#define M_CPL_RDMA_CQE_GENERATION_BIT	0x1
+#define V_CPL_RDMA_CQE_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_GENERATION_BIT) & M_CPL_RDMA_CQE_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_GENERATION_BIT	V_CPL_RDMA_CQE_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_STATUS		5
+#define M_CPL_RDMA_CQE_STATUS		0x1f
+#define V_CPL_RDMA_CQE_STATUS(x)	((x) << S_CPL_RDMA_CQE_STATUS)
+#define G_CPL_RDMA_CQE_STATUS(x)	\
+    (((x) >> S_CPL_RDMA_CQE_STATUS) & M_CPL_RDMA_CQE_STATUS)
+
+#define S_CPL_RDMA_CQE_CQE_TYPE		4
+#define M_CPL_RDMA_CQE_CQE_TYPE		0x1
+#define V_CPL_RDMA_CQE_CQE_TYPE(x)	((x) << S_CPL_RDMA_CQE_CQE_TYPE)
+#define G_CPL_RDMA_CQE_CQE_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_CQE_TYPE) & M_CPL_RDMA_CQE_CQE_TYPE)
+#define F_CPL_RDMA_CQE_CQE_TYPE		V_CPL_RDMA_CQE_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_WR_TYPE		0
+#define M_CPL_RDMA_CQE_WR_TYPE		0xf
+#define V_CPL_RDMA_CQE_WR_TYPE(x)	((x) << S_CPL_RDMA_CQE_WR_TYPE)
+#define G_CPL_RDMA_CQE_WR_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_WR_TYPE) & M_CPL_RDMA_CQE_WR_TYPE)
+
+struct cpl_rdma_cqe_srq {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+	__be32 r3;
+	__be32 rqe;
+};
+
+#define S_CPL_RDMA_CQE_SRQ_OPCODE	24
+#define M_CPL_RDMA_CQE_SRQ_OPCODE	0xff
+#define V_CPL_RDMA_CQE_SRQ_OPCODE(x)	((x) << S_CPL_RDMA_CQE_SRQ_OPCODE)
+#define G_CPL_RDMA_CQE_SRQ_OPCODE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_OPCODE) & M_CPL_RDMA_CQE_SRQ_OPCODE)
+
+#define S_CPL_RDMA_CQE_SRQ_RSSCTRL	16
+#define M_CPL_RDMA_CQE_SRQ_RSSCTRL	0xff
+#define V_CPL_RDMA_CQE_SRQ_RSSCTRL(x)	((x) << S_CPL_RDMA_CQE_SRQ_RSSCTRL)
+#define G_CPL_RDMA_CQE_SRQ_RSSCTRL(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_RSSCTRL) & M_CPL_RDMA_CQE_SRQ_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_SRQ_CQID		0
+#define M_CPL_RDMA_CQE_SRQ_CQID		0xffff
+#define V_CPL_RDMA_CQE_SRQ_CQID(x)	((x) << S_CPL_RDMA_CQE_SRQ_CQID)
+#define G_CPL_RDMA_CQE_SRQ_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_CQID) & M_CPL_RDMA_CQE_SRQ_CQID)
+
+#define S_CPL_RDMA_CQE_SRQ_TID		8
+#define M_CPL_RDMA_CQE_SRQ_TID		0xfffff
+#define V_CPL_RDMA_CQE_SRQ_TID(x)	((x) << S_CPL_RDMA_CQE_SRQ_TID)
+#define G_CPL_RDMA_CQE_SRQ_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_TID) & M_CPL_RDMA_CQE_SRQ_TID)
+
+#define S_CPL_RDMA_CQE_SRQ_FLITCNT	0
+#define M_CPL_RDMA_CQE_SRQ_FLITCNT	0xff
+#define V_CPL_RDMA_CQE_SRQ_FLITCNT(x)	((x) << S_CPL_RDMA_CQE_SRQ_FLITCNT)
+#define G_CPL_RDMA_CQE_SRQ_FLITCNT(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_FLITCNT) & M_CPL_RDMA_CQE_SRQ_FLITCNT)
+
+#define S_CPL_RDMA_CQE_SRQ_QPID		12
+#define M_CPL_RDMA_CQE_SRQ_QPID		0xfffff
+#define V_CPL_RDMA_CQE_SRQ_QPID(x)	((x) << S_CPL_RDMA_CQE_SRQ_QPID)
+#define G_CPL_RDMA_CQE_SRQ_QPID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_QPID) & M_CPL_RDMA_CQE_SRQ_QPID)
+
+#define S_CPL_RDMA_CQE_SRQ_GENERATION_BIT 10
+#define M_CPL_RDMA_CQE_SRQ_GENERATION_BIT 0x1
+#define V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_SRQ_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_SRQ_GENERATION_BIT) & \
+     M_CPL_RDMA_CQE_SRQ_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_SRQ_GENERATION_BIT \
+    V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_SRQ_STATUS	5
+#define M_CPL_RDMA_CQE_SRQ_STATUS	0x1f
+#define V_CPL_RDMA_CQE_SRQ_STATUS(x)	((x) << S_CPL_RDMA_CQE_SRQ_STATUS)
+#define G_CPL_RDMA_CQE_SRQ_STATUS(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_STATUS) & M_CPL_RDMA_CQE_SRQ_STATUS)
+
+#define S_CPL_RDMA_CQE_SRQ_CQE_TYPE	4
+#define M_CPL_RDMA_CQE_SRQ_CQE_TYPE	0x1
+#define V_CPL_RDMA_CQE_SRQ_CQE_TYPE(x)	((x) << S_CPL_RDMA_CQE_SRQ_CQE_TYPE)
+#define G_CPL_RDMA_CQE_SRQ_CQE_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_CQE_TYPE) & M_CPL_RDMA_CQE_SRQ_CQE_TYPE)
+#define F_CPL_RDMA_CQE_SRQ_CQE_TYPE	V_CPL_RDMA_CQE_SRQ_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_SRQ_WR_TYPE	0
+#define M_CPL_RDMA_CQE_SRQ_WR_TYPE	0xf
+#define V_CPL_RDMA_CQE_SRQ_WR_TYPE(x)	((x) << S_CPL_RDMA_CQE_SRQ_WR_TYPE)
+#define G_CPL_RDMA_CQE_SRQ_WR_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_SRQ_WR_TYPE) & M_CPL_RDMA_CQE_SRQ_WR_TYPE)
+
+struct cpl_rdma_cqe_read_rsp {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+};
+
+#define S_CPL_RDMA_CQE_READ_RSP_RSSCTRL	16
+#define M_CPL_RDMA_CQE_READ_RSP_RSSCTRL	0xff
+#define V_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \
+    ((x) << S_CPL_RDMA_CQE_READ_RSP_RSSCTRL)
+#define G_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_RSSCTRL) & \
+     M_CPL_RDMA_CQE_READ_RSP_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_READ_RSP_CQID	0
+#define M_CPL_RDMA_CQE_READ_RSP_CQID	0xffff
+#define V_CPL_RDMA_CQE_READ_RSP_CQID(x)	((x) << S_CPL_RDMA_CQE_READ_RSP_CQID)
+#define G_CPL_RDMA_CQE_READ_RSP_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQID) & M_CPL_RDMA_CQE_READ_RSP_CQID)
+
+#define S_CPL_RDMA_CQE_READ_RSP_TID	8
+#define M_CPL_RDMA_CQE_READ_RSP_TID	0xfffff
+#define V_CPL_RDMA_CQE_READ_RSP_TID(x)	((x) << S_CPL_RDMA_CQE_READ_RSP_TID)
+#define G_CPL_RDMA_CQE_READ_RSP_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_TID) & M_CPL_RDMA_CQE_READ_RSP_TID)
+
+#define S_CPL_RDMA_CQE_READ_RSP_FLITCNT	0
+#define M_CPL_RDMA_CQE_READ_RSP_FLITCNT	0xff
+#define V_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \
+    ((x) << S_CPL_RDMA_CQE_READ_RSP_FLITCNT)
+#define G_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_FLITCNT) & \
+     M_CPL_RDMA_CQE_READ_RSP_FLITCNT)
+
+#define S_CPL_RDMA_CQE_READ_RSP_QPID	12
+#define M_CPL_RDMA_CQE_READ_RSP_QPID	0xfffff
+#define V_CPL_RDMA_CQE_READ_RSP_QPID(x)	((x) << S_CPL_RDMA_CQE_READ_RSP_QPID)
+#define G_CPL_RDMA_CQE_READ_RSP_QPID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_QPID) & M_CPL_RDMA_CQE_READ_RSP_QPID)
+
+#define S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT 10
+#define M_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT 0x1
+#define V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) & \
+     M_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT \
+    V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_READ_RSP_STATUS	5
+#define M_CPL_RDMA_CQE_READ_RSP_STATUS	0x1f
+#define V_CPL_RDMA_CQE_READ_RSP_STATUS(x) \
+    ((x) << S_CPL_RDMA_CQE_READ_RSP_STATUS)
+#define G_CPL_RDMA_CQE_READ_RSP_STATUS(x) \
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_STATUS) & M_CPL_RDMA_CQE_READ_RSP_STATUS)
+
+#define S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE 4
+#define M_CPL_RDMA_CQE_READ_RSP_CQE_TYPE 0x1
+#define V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \
+    ((x) << S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE)
+#define G_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) & \
+     M_CPL_RDMA_CQE_READ_RSP_CQE_TYPE)
+#define F_CPL_RDMA_CQE_READ_RSP_CQE_TYPE V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_READ_RSP_WR_TYPE	0
+#define M_CPL_RDMA_CQE_READ_RSP_WR_TYPE	0xf
+#define V_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \
+    ((x) << S_CPL_RDMA_CQE_READ_RSP_WR_TYPE)
+#define G_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \
+    (((x) >> S_CPL_RDMA_CQE_READ_RSP_WR_TYPE) & \
+     M_CPL_RDMA_CQE_READ_RSP_WR_TYPE)
+
+struct cpl_rdma_cqe_err {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+};
+
+#define S_CPL_RDMA_CQE_ERR_RSSCTRL	16
+#define M_CPL_RDMA_CQE_ERR_RSSCTRL	0xff
+#define V_CPL_RDMA_CQE_ERR_RSSCTRL(x)	((x) << S_CPL_RDMA_CQE_ERR_RSSCTRL)
+#define G_CPL_RDMA_CQE_ERR_RSSCTRL(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_RSSCTRL) & M_CPL_RDMA_CQE_ERR_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_ERR_CQID		0
+#define M_CPL_RDMA_CQE_ERR_CQID		0xffff
+#define V_CPL_RDMA_CQE_ERR_CQID(x)	((x) << S_CPL_RDMA_CQE_ERR_CQID)
+#define G_CPL_RDMA_CQE_ERR_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_CQID) & M_CPL_RDMA_CQE_ERR_CQID)
+
+#define S_CPL_RDMA_CQE_ERR_TID		8
+#define M_CPL_RDMA_CQE_ERR_TID		0xfffff
+#define V_CPL_RDMA_CQE_ERR_TID(x)	((x) << S_CPL_RDMA_CQE_ERR_TID)
+#define G_CPL_RDMA_CQE_ERR_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_TID) & M_CPL_RDMA_CQE_ERR_TID)
+
+#define S_CPL_RDMA_CQE_ERR_FLITCNT	0
+#define M_CPL_RDMA_CQE_ERR_FLITCNT	0xff
+#define V_CPL_RDMA_CQE_ERR_FLITCNT(x)	((x) << S_CPL_RDMA_CQE_ERR_FLITCNT)
+#define G_CPL_RDMA_CQE_ERR_FLITCNT(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_FLITCNT) & M_CPL_RDMA_CQE_ERR_FLITCNT)
+
+#define S_CPL_RDMA_CQE_ERR_QPID		12
+#define M_CPL_RDMA_CQE_ERR_QPID		0xfffff
+#define V_CPL_RDMA_CQE_ERR_QPID(x)	((x) << S_CPL_RDMA_CQE_ERR_QPID)
+#define G_CPL_RDMA_CQE_ERR_QPID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_QPID) & M_CPL_RDMA_CQE_ERR_QPID)
+
+#define S_CPL_RDMA_CQE_ERR_GENERATION_BIT 10
+#define M_CPL_RDMA_CQE_ERR_GENERATION_BIT 0x1
+#define V_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_GENERATION_BIT) & \
+     M_CPL_RDMA_CQE_ERR_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_ERR_GENERATION_BIT \
+    V_CPL_RDMA_CQE_ERR_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_ERR_STATUS	5
+#define M_CPL_RDMA_CQE_ERR_STATUS	0x1f
+#define V_CPL_RDMA_CQE_ERR_STATUS(x)	((x) << S_CPL_RDMA_CQE_ERR_STATUS)
+#define G_CPL_RDMA_CQE_ERR_STATUS(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_STATUS) & M_CPL_RDMA_CQE_ERR_STATUS)
+
+#define S_CPL_RDMA_CQE_ERR_CQE_TYPE	4
+#define M_CPL_RDMA_CQE_ERR_CQE_TYPE	0x1
+#define V_CPL_RDMA_CQE_ERR_CQE_TYPE(x)	((x) << S_CPL_RDMA_CQE_ERR_CQE_TYPE)
+#define G_CPL_RDMA_CQE_ERR_CQE_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_CQE_TYPE) & M_CPL_RDMA_CQE_ERR_CQE_TYPE)
+#define F_CPL_RDMA_CQE_ERR_CQE_TYPE	V_CPL_RDMA_CQE_ERR_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_ERR_WR_TYPE	0
+#define M_CPL_RDMA_CQE_ERR_WR_TYPE	0xf
+#define V_CPL_RDMA_CQE_ERR_WR_TYPE(x)	((x) << S_CPL_RDMA_CQE_ERR_WR_TYPE)
+#define G_CPL_RDMA_CQE_ERR_WR_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_WR_TYPE) & M_CPL_RDMA_CQE_ERR_WR_TYPE)
+
+struct cpl_rdma_read_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be16 srq_pkd;
+	__be16 length;
+};
+
+#define S_CPL_RDMA_READ_REQ_SRQ		0
+#define M_CPL_RDMA_READ_REQ_SRQ		0xfff
+#define V_CPL_RDMA_READ_REQ_SRQ(x)	((x) << S_CPL_RDMA_READ_REQ_SRQ)
+#define G_CPL_RDMA_READ_REQ_SRQ(x)	\
+    (((x) >> S_CPL_RDMA_READ_REQ_SRQ) & M_CPL_RDMA_READ_REQ_SRQ)
+
 struct cpl_rdma_terminate {
 	RSS_HDR
 	union opcode_tid ot;
@@ -2618,6 +3931,404 @@ struct cpl_rdma_terminate {
 	__be16 len;
 };
 
+struct cpl_rdma_atomic_req {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 opcode_srq;
+	__be16 length;
+};
+
+#define S_CPL_RDMA_ATOMIC_REQ_OPCODE	12
+#define M_CPL_RDMA_ATOMIC_REQ_OPCODE	0xf
+#define V_CPL_RDMA_ATOMIC_REQ_OPCODE(x)	((x) << S_CPL_RDMA_ATOMIC_REQ_OPCODE)
+#define G_CPL_RDMA_ATOMIC_REQ_OPCODE(x)	\
+    (((x) >> S_CPL_RDMA_ATOMIC_REQ_OPCODE) & M_CPL_RDMA_ATOMIC_REQ_OPCODE)
+
+#define S_CPL_RDMA_ATOMIC_REQ_SRQ	0
+#define M_CPL_RDMA_ATOMIC_REQ_SRQ	0xfff
+#define V_CPL_RDMA_ATOMIC_REQ_SRQ(x)	((x) << S_CPL_RDMA_ATOMIC_REQ_SRQ)
+#define G_CPL_RDMA_ATOMIC_REQ_SRQ(x)	\
+    (((x) >> S_CPL_RDMA_ATOMIC_REQ_SRQ) & M_CPL_RDMA_ATOMIC_REQ_SRQ)
+
+struct cpl_rdma_atomic_rpl {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 opcode_srq;
+	__be16 length;
+};
+
+#define S_CPL_RDMA_ATOMIC_RPL_OPCODE	12
+#define M_CPL_RDMA_ATOMIC_RPL_OPCODE	0xf
+#define V_CPL_RDMA_ATOMIC_RPL_OPCODE(x)	((x) << S_CPL_RDMA_ATOMIC_RPL_OPCODE)
+#define G_CPL_RDMA_ATOMIC_RPL_OPCODE(x)	\
+    (((x) >> S_CPL_RDMA_ATOMIC_RPL_OPCODE) & M_CPL_RDMA_ATOMIC_RPL_OPCODE)
+
+#define S_CPL_RDMA_ATOMIC_RPL_SRQ	0
+#define M_CPL_RDMA_ATOMIC_RPL_SRQ	0xfff
+#define V_CPL_RDMA_ATOMIC_RPL_SRQ(x)	((x) << S_CPL_RDMA_ATOMIC_RPL_SRQ)
+#define G_CPL_RDMA_ATOMIC_RPL_SRQ(x)	\
+    (((x) >> S_CPL_RDMA_ATOMIC_RPL_SRQ) & M_CPL_RDMA_ATOMIC_RPL_SRQ)
+
+struct cpl_rdma_imm_data {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 r;
+	__be16 Length;
+};
+
+struct cpl_rdma_imm_data_se {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 r;
+	__be16 Length;
+};
+
+struct cpl_rdma_inv_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 stag;
+	__be32 cqid_pdid_hi;
+	__be32 pdid_lo_qpid;
+};
+
+#define S_CPL_RDMA_INV_REQ_CQID		8
+#define M_CPL_RDMA_INV_REQ_CQID		0xfffff
+#define V_CPL_RDMA_INV_REQ_CQID(x)	((x) << S_CPL_RDMA_INV_REQ_CQID)
+#define G_CPL_RDMA_INV_REQ_CQID(x)	\
+    (((x) >> S_CPL_RDMA_INV_REQ_CQID) & M_CPL_RDMA_INV_REQ_CQID)
+
+#define S_CPL_RDMA_INV_REQ_PDID_HI	0
+#define M_CPL_RDMA_INV_REQ_PDID_HI	0xff
+#define V_CPL_RDMA_INV_REQ_PDID_HI(x)	((x) << S_CPL_RDMA_INV_REQ_PDID_HI)
+#define G_CPL_RDMA_INV_REQ_PDID_HI(x)	\
+    (((x) >> S_CPL_RDMA_INV_REQ_PDID_HI) & M_CPL_RDMA_INV_REQ_PDID_HI)
+
+#define S_CPL_RDMA_INV_REQ_PDID_LO	20
+#define M_CPL_RDMA_INV_REQ_PDID_LO	0xfff
+#define V_CPL_RDMA_INV_REQ_PDID_LO(x)	((x) << S_CPL_RDMA_INV_REQ_PDID_LO)
+#define G_CPL_RDMA_INV_REQ_PDID_LO(x)	\
+    (((x) >> S_CPL_RDMA_INV_REQ_PDID_LO) & M_CPL_RDMA_INV_REQ_PDID_LO)
+
+#define S_CPL_RDMA_INV_REQ_QPID		0
+#define M_CPL_RDMA_INV_REQ_QPID		0xfffff
+#define V_CPL_RDMA_INV_REQ_QPID(x)	((x) << S_CPL_RDMA_INV_REQ_QPID)
+#define G_CPL_RDMA_INV_REQ_QPID(x)	\
+    (((x) >> S_CPL_RDMA_INV_REQ_QPID) & M_CPL_RDMA_INV_REQ_QPID)
+
+struct cpl_rdma_cqe_ext {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+	__be32 se_to_srq;
+	__be32 rqe;
+	__be32 extinfoms[2];
+	__be32 extinfols[2];
+};
+
+#define S_CPL_RDMA_CQE_EXT_RSSCTRL	16
+#define M_CPL_RDMA_CQE_EXT_RSSCTRL	0xff
+#define V_CPL_RDMA_CQE_EXT_RSSCTRL(x)	((x) << S_CPL_RDMA_CQE_EXT_RSSCTRL)
+#define G_CPL_RDMA_CQE_EXT_RSSCTRL(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_RSSCTRL) & M_CPL_RDMA_CQE_EXT_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_EXT_CQID		0
+#define M_CPL_RDMA_CQE_EXT_CQID		0xffff
+#define V_CPL_RDMA_CQE_EXT_CQID(x)	((x) << S_CPL_RDMA_CQE_EXT_CQID)
+#define G_CPL_RDMA_CQE_EXT_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_CQID) & M_CPL_RDMA_CQE_EXT_CQID)
+
+#define S_CPL_RDMA_CQE_EXT_TID		8
+#define M_CPL_RDMA_CQE_EXT_TID		0xfffff
+#define V_CPL_RDMA_CQE_EXT_TID(x)	((x) << S_CPL_RDMA_CQE_EXT_TID)
+#define G_CPL_RDMA_CQE_EXT_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_TID) & M_CPL_RDMA_CQE_EXT_TID)
+
+#define S_CPL_RDMA_CQE_EXT_FLITCNT	0
+#define M_CPL_RDMA_CQE_EXT_FLITCNT	0xff
+#define V_CPL_RDMA_CQE_EXT_FLITCNT(x)	((x) << S_CPL_RDMA_CQE_EXT_FLITCNT)
+#define G_CPL_RDMA_CQE_EXT_FLITCNT(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_FLITCNT) & M_CPL_RDMA_CQE_EXT_FLITCNT)
+
+#define S_CPL_RDMA_CQE_EXT_QPID		12
+#define M_CPL_RDMA_CQE_EXT_QPID		0xfffff
+#define V_CPL_RDMA_CQE_EXT_QPID(x)	((x) << S_CPL_RDMA_CQE_EXT_QPID)
+#define G_CPL_RDMA_CQE_EXT_QPID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_QPID) & M_CPL_RDMA_CQE_EXT_QPID)
+
+#define S_CPL_RDMA_CQE_EXT_EXTMODE	11
+#define M_CPL_RDMA_CQE_EXT_EXTMODE	0x1
+#define V_CPL_RDMA_CQE_EXT_EXTMODE(x)	((x) << S_CPL_RDMA_CQE_EXT_EXTMODE)
+#define G_CPL_RDMA_CQE_EXT_EXTMODE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_EXTMODE) & M_CPL_RDMA_CQE_EXT_EXTMODE)
+#define F_CPL_RDMA_CQE_EXT_EXTMODE	V_CPL_RDMA_CQE_EXT_EXTMODE(1U)
+
+#define S_CPL_RDMA_CQE_EXT_GENERATION_BIT 10
+#define M_CPL_RDMA_CQE_EXT_GENERATION_BIT 0x1
+#define V_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_EXT_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_EXT_GENERATION_BIT) & \
+     M_CPL_RDMA_CQE_EXT_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_EXT_GENERATION_BIT \
+    V_CPL_RDMA_CQE_EXT_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_EXT_STATUS	5
+#define M_CPL_RDMA_CQE_EXT_STATUS	0x1f
+#define V_CPL_RDMA_CQE_EXT_STATUS(x)	((x) << S_CPL_RDMA_CQE_EXT_STATUS)
+#define G_CPL_RDMA_CQE_EXT_STATUS(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_STATUS) & M_CPL_RDMA_CQE_EXT_STATUS)
+
+#define S_CPL_RDMA_CQE_EXT_CQE_TYPE	4
+#define M_CPL_RDMA_CQE_EXT_CQE_TYPE	0x1
+#define V_CPL_RDMA_CQE_EXT_CQE_TYPE(x)	((x) << S_CPL_RDMA_CQE_EXT_CQE_TYPE)
+#define G_CPL_RDMA_CQE_EXT_CQE_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_EXT_CQE_TYPE)
+#define F_CPL_RDMA_CQE_EXT_CQE_TYPE	V_CPL_RDMA_CQE_EXT_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_EXT_WR_TYPE	0
+#define M_CPL_RDMA_CQE_EXT_WR_TYPE	0xf
+#define V_CPL_RDMA_CQE_EXT_WR_TYPE(x)	((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE)
+#define G_CPL_RDMA_CQE_EXT_WR_TYPE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE) & M_CPL_RDMA_CQE_EXT_WR_TYPE)
+
+#define S_CPL_RDMA_CQE_EXT_SE		31
+#define M_CPL_RDMA_CQE_EXT_SE		0x1
+#define V_CPL_RDMA_CQE_EXT_SE(x)	((x) << S_CPL_RDMA_CQE_EXT_SE)
+#define G_CPL_RDMA_CQE_EXT_SE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_SE) & M_CPL_RDMA_CQE_EXT_SE)
+#define F_CPL_RDMA_CQE_EXT_SE		V_CPL_RDMA_CQE_EXT_SE(1U)
+
+#define S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT	24
+#define M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT	0x7f
+#define V_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \
+    ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT)
+#define G_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \
+    (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) & M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT)
+
+#define S_CPL_RDMA_CQE_EXT_SRQ		0
+#define M_CPL_RDMA_CQE_EXT_SRQ		0xfff
+#define V_CPL_RDMA_CQE_EXT_SRQ(x)	((x) << S_CPL_RDMA_CQE_EXT_SRQ)
+#define G_CPL_RDMA_CQE_EXT_SRQ(x)	\
+    (((x) >> S_CPL_RDMA_CQE_EXT_SRQ) & M_CPL_RDMA_CQE_EXT_SRQ)
+
+struct cpl_rdma_cqe_fw_ext {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+	__be32 se_to_srq;
+	__be32 rqe;
+	__be32 extinfoms[2];
+	__be32 extinfols[2];
+};
+
+#define S_CPL_RDMA_CQE_FW_EXT_RSSCTRL	16
+#define M_CPL_RDMA_CQE_FW_EXT_RSSCTRL	0xff
+#define V_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_RSSCTRL)
+#define G_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_RSSCTRL) & M_CPL_RDMA_CQE_FW_EXT_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_FW_EXT_CQID	0
+#define M_CPL_RDMA_CQE_FW_EXT_CQID	0xffff
+#define V_CPL_RDMA_CQE_FW_EXT_CQID(x)	((x) << S_CPL_RDMA_CQE_FW_EXT_CQID)
+#define G_CPL_RDMA_CQE_FW_EXT_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQID) & M_CPL_RDMA_CQE_FW_EXT_CQID)
+
+#define S_CPL_RDMA_CQE_FW_EXT_TID	8
+#define M_CPL_RDMA_CQE_FW_EXT_TID	0xfffff
+#define V_CPL_RDMA_CQE_FW_EXT_TID(x)	((x) << S_CPL_RDMA_CQE_FW_EXT_TID)
+#define G_CPL_RDMA_CQE_FW_EXT_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_TID) & M_CPL_RDMA_CQE_FW_EXT_TID)
+
+#define S_CPL_RDMA_CQE_FW_EXT_FLITCNT	0
+#define M_CPL_RDMA_CQE_FW_EXT_FLITCNT	0xff
+#define V_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_FLITCNT)
+#define G_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_FLITCNT) & M_CPL_RDMA_CQE_FW_EXT_FLITCNT)
+
+#define S_CPL_RDMA_CQE_FW_EXT_QPID	12
+#define M_CPL_RDMA_CQE_FW_EXT_QPID	0xfffff
+#define V_CPL_RDMA_CQE_FW_EXT_QPID(x)	((x) << S_CPL_RDMA_CQE_FW_EXT_QPID)
+#define G_CPL_RDMA_CQE_FW_EXT_QPID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_QPID) & M_CPL_RDMA_CQE_FW_EXT_QPID)
+
+#define S_CPL_RDMA_CQE_FW_EXT_EXTMODE	11
+#define M_CPL_RDMA_CQE_FW_EXT_EXTMODE	0x1
+#define V_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_EXTMODE)
+#define G_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_EXTMODE) & M_CPL_RDMA_CQE_FW_EXT_EXTMODE)
+#define F_CPL_RDMA_CQE_FW_EXT_EXTMODE	V_CPL_RDMA_CQE_FW_EXT_EXTMODE(1U)
+
+#define S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 10
+#define M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 0x1
+#define V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) & \
+     M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT \
+    V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_FW_EXT_STATUS	5
+#define M_CPL_RDMA_CQE_FW_EXT_STATUS	0x1f
+#define V_CPL_RDMA_CQE_FW_EXT_STATUS(x)	((x) << S_CPL_RDMA_CQE_FW_EXT_STATUS)
+#define G_CPL_RDMA_CQE_FW_EXT_STATUS(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_STATUS) & M_CPL_RDMA_CQE_FW_EXT_STATUS)
+
+#define S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE	4
+#define M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE	0x1
+#define V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE)
+#define G_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE)
+#define F_CPL_RDMA_CQE_FW_EXT_CQE_TYPE	V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_FW_EXT_WR_TYPE	0
+#define M_CPL_RDMA_CQE_FW_EXT_WR_TYPE	0xf
+#define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE)
+#define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE) & M_CPL_RDMA_CQE_FW_EXT_WR_TYPE)
+
+#define S_CPL_RDMA_CQE_FW_EXT_SE	31
+#define M_CPL_RDMA_CQE_FW_EXT_SE	0x1
+#define V_CPL_RDMA_CQE_FW_EXT_SE(x)	((x) << S_CPL_RDMA_CQE_FW_EXT_SE)
+#define G_CPL_RDMA_CQE_FW_EXT_SE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_SE) & M_CPL_RDMA_CQE_FW_EXT_SE)
+#define F_CPL_RDMA_CQE_FW_EXT_SE	V_CPL_RDMA_CQE_FW_EXT_SE(1U)
+
+#define S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT 24
+#define M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT 0x7f
+#define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \
+    ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT)
+#define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) & \
+     M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT)
+
+#define S_CPL_RDMA_CQE_FW_EXT_SRQ	0
+#define M_CPL_RDMA_CQE_FW_EXT_SRQ	0xfff
+#define V_CPL_RDMA_CQE_FW_EXT_SRQ(x)	((x) << S_CPL_RDMA_CQE_FW_EXT_SRQ)
+#define G_CPL_RDMA_CQE_FW_EXT_SRQ(x)	\
+    (((x) >> S_CPL_RDMA_CQE_FW_EXT_SRQ) & M_CPL_RDMA_CQE_FW_EXT_SRQ)
+
+struct cpl_rdma_cqe_err_ext {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+	__be32 se_to_srq;
+	__be32 rqe;
+	__be32 extinfoms[2];
+	__be32 extinfols[2];
+};
+
+#define S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL	16
+#define M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL	0xff
+#define V_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL)
+#define G_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) & M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_CQID	0
+#define M_CPL_RDMA_CQE_ERR_EXT_CQID	0xffff
+#define V_CPL_RDMA_CQE_ERR_EXT_CQID(x)	((x) << S_CPL_RDMA_CQE_ERR_EXT_CQID)
+#define G_CPL_RDMA_CQE_ERR_EXT_CQID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQID) & M_CPL_RDMA_CQE_ERR_EXT_CQID)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_TID	8
+#define M_CPL_RDMA_CQE_ERR_EXT_TID	0xfffff
+#define V_CPL_RDMA_CQE_ERR_EXT_TID(x)	((x) << S_CPL_RDMA_CQE_ERR_EXT_TID)
+#define G_CPL_RDMA_CQE_ERR_EXT_TID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_TID) & M_CPL_RDMA_CQE_ERR_EXT_TID)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_FLITCNT	0
+#define M_CPL_RDMA_CQE_ERR_EXT_FLITCNT	0xff
+#define V_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_FLITCNT)
+#define G_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_FLITCNT) & M_CPL_RDMA_CQE_ERR_EXT_FLITCNT)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_QPID	12
+#define M_CPL_RDMA_CQE_ERR_EXT_QPID	0xfffff
+#define V_CPL_RDMA_CQE_ERR_EXT_QPID(x)	((x) << S_CPL_RDMA_CQE_ERR_EXT_QPID)
+#define G_CPL_RDMA_CQE_ERR_EXT_QPID(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_QPID) & M_CPL_RDMA_CQE_ERR_EXT_QPID)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_EXTMODE	11
+#define M_CPL_RDMA_CQE_ERR_EXT_EXTMODE	0x1
+#define V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_EXTMODE)
+#define G_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) & M_CPL_RDMA_CQE_ERR_EXT_EXTMODE)
+#define F_CPL_RDMA_CQE_ERR_EXT_EXTMODE	V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(1U)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 10
+#define M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 0x1
+#define V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT)
+#define G_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) & \
+     M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT)
+#define F_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT \
+    V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(1U)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_STATUS	5
+#define M_CPL_RDMA_CQE_ERR_EXT_STATUS	0x1f
+#define V_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_STATUS)
+#define G_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_STATUS) & M_CPL_RDMA_CQE_ERR_EXT_STATUS)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE	4
+#define M_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE	0x1
+#define V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE)
+#define G_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) & \
+     M_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE)
+#define F_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE	V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(1U)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE	0
+#define M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE	0xf
+#define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE)
+#define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) & M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_SE	31
+#define M_CPL_RDMA_CQE_ERR_EXT_SE	0x1
+#define V_CPL_RDMA_CQE_ERR_EXT_SE(x)	((x) << S_CPL_RDMA_CQE_ERR_EXT_SE)
+#define G_CPL_RDMA_CQE_ERR_EXT_SE(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SE) & M_CPL_RDMA_CQE_ERR_EXT_SE)
+#define F_CPL_RDMA_CQE_ERR_EXT_SE	V_CPL_RDMA_CQE_ERR_EXT_SE(1U)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT 24
+#define M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT 0x7f
+#define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \
+    ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT)
+#define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) & \
+     M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT)
+
+#define S_CPL_RDMA_CQE_ERR_EXT_SRQ	0
+#define M_CPL_RDMA_CQE_ERR_EXT_SRQ	0xfff
+#define V_CPL_RDMA_CQE_ERR_EXT_SRQ(x)	((x) << S_CPL_RDMA_CQE_ERR_EXT_SRQ)
+#define G_CPL_RDMA_CQE_ERR_EXT_SRQ(x)	\
+    (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SRQ) & M_CPL_RDMA_CQE_ERR_EXT_SRQ)
+
 struct cpl_set_le_req {
 	WR_HDR;
 	union opcode_tid ot;
@@ -2630,6 +4341,13 @@ struct cpl_set_le_req {
 };
 
 /* cpl_set_le_req.reply_ctrl additional fields */
+#define S_LE_REQ_RXCHANNEL      14
+#define M_LE_REQ_RXCHANNEL      0x1
+#define V_LE_REQ_RXCHANNEL(x)   ((x) << S_LE_REQ_RXCHANNEL)
+#define G_LE_REQ_RXCHANNEL(x)   \
+    (((x) >> S_LE_REQ_RXCHANNEL) & M_LE_REQ_RXCHANNEL)
+#define F_LE_REQ_RXCHANNEL      V_LE_REQ_RXCHANNEL(1U)
+
 #define S_LE_REQ_IP6    13
 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
 #define F_LE_REQ_IP6    V_LE_REQ_IP6(1U)
@@ -2659,6 +4377,80 @@ struct cpl_set_le_req {
 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
 
+struct cpl_t7_set_le_req {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 noreply_to_channel;
+	__be32 mask1[2];
+	__be32 mask0[2];
+	__be32 value1[2];
+	__be32 value0[2];
+};
+
+#define S_CPL_T7_SET_LE_REQ_INDEX	0
+#define M_CPL_T7_SET_LE_REQ_INDEX	0xffffff
+#define V_CPL_T7_SET_LE_REQ_INDEX(x)	((x) << S_CPL_T7_SET_LE_REQ_INDEX)
+#define G_CPL_T7_SET_LE_REQ_INDEX(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_INDEX) & M_CPL_T7_SET_LE_REQ_INDEX)
+
+#define S_CPL_T7_SET_LE_REQ_NOREPLY	31
+#define M_CPL_T7_SET_LE_REQ_NOREPLY	0x1
+#define V_CPL_T7_SET_LE_REQ_NOREPLY(x)	((x) << S_CPL_T7_SET_LE_REQ_NOREPLY)
+#define G_CPL_T7_SET_LE_REQ_NOREPLY(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_NOREPLY) & M_CPL_T7_SET_LE_REQ_NOREPLY)
+#define F_CPL_T7_SET_LE_REQ_NOREPLY	V_CPL_T7_SET_LE_REQ_NOREPLY(1U)
+
+#define S_CPL_T7_SET_LE_REQ_RXCHANNEL		28
+#define M_CPL_T7_SET_LE_REQ_RXCHANNEL		0x7
+#define V_CPL_T7_SET_LE_REQ_RXCHANNEL(x)	\
+    ((x) << S_CPL_T7_SET_LE_REQ_RXCHANNEL)
+#define G_CPL_T7_SET_LE_REQ_RXCHANNEL(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_RXCHANNEL) & M_CPL_T7_SET_LE_REQ_RXCHANNEL)
+
+#define S_CPL_T7_SET_LE_REQ_QUEUE	16
+#define M_CPL_T7_SET_LE_REQ_QUEUE	0xfff
+#define V_CPL_T7_SET_LE_REQ_QUEUE(x)	((x) << S_CPL_T7_SET_LE_REQ_QUEUE)
+#define G_CPL_T7_SET_LE_REQ_QUEUE(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_QUEUE) & M_CPL_T7_SET_LE_REQ_QUEUE)
+
+#define S_CPL_T7_SET_LE_REQ_REQCMD	12
+#define M_CPL_T7_SET_LE_REQ_REQCMD	0xf
+#define V_CPL_T7_SET_LE_REQ_REQCMD(x)	((x) << S_CPL_T7_SET_LE_REQ_REQCMD)
+#define G_CPL_T7_SET_LE_REQ_REQCMD(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_REQCMD) & M_CPL_T7_SET_LE_REQ_REQCMD)
+
+#define S_CPL_T7_SET_LE_REQ_REQSIZE	9
+#define M_CPL_T7_SET_LE_REQ_REQSIZE	0x7
+#define V_CPL_T7_SET_LE_REQ_REQSIZE(x)	((x) << S_CPL_T7_SET_LE_REQ_REQSIZE)
+#define G_CPL_T7_SET_LE_REQ_REQSIZE(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_REQSIZE) & M_CPL_T7_SET_LE_REQ_REQSIZE)
+
+#define S_CPL_T7_SET_LE_REQ_MORE	8
+#define M_CPL_T7_SET_LE_REQ_MORE	0x1
+#define V_CPL_T7_SET_LE_REQ_MORE(x)	((x) << S_CPL_T7_SET_LE_REQ_MORE)
+#define G_CPL_T7_SET_LE_REQ_MORE(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_MORE) & M_CPL_T7_SET_LE_REQ_MORE)
+#define F_CPL_T7_SET_LE_REQ_MORE	V_CPL_T7_SET_LE_REQ_MORE(1U)
+
+#define S_CPL_T7_SET_LE_REQ_OFFSET	5
+#define M_CPL_T7_SET_LE_REQ_OFFSET	0x7
+#define V_CPL_T7_SET_LE_REQ_OFFSET(x)	((x) << S_CPL_T7_SET_LE_REQ_OFFSET)
+#define G_CPL_T7_SET_LE_REQ_OFFSET(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_OFFSET) & M_CPL_T7_SET_LE_REQ_OFFSET)
+
+#define S_CPL_T7_SET_LE_REQ_REQTYPE	4
+#define M_CPL_T7_SET_LE_REQ_REQTYPE	0x1
+#define V_CPL_T7_SET_LE_REQ_REQTYPE(x)	((x) << S_CPL_T7_SET_LE_REQ_REQTYPE)
+#define G_CPL_T7_SET_LE_REQ_REQTYPE(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_REQTYPE) & M_CPL_T7_SET_LE_REQ_REQTYPE)
+#define F_CPL_T7_SET_LE_REQ_REQTYPE	V_CPL_T7_SET_LE_REQ_REQTYPE(1U)
+
+#define S_CPL_T7_SET_LE_REQ_CHANNEL	0
+#define M_CPL_T7_SET_LE_REQ_CHANNEL	0x3
+#define V_CPL_T7_SET_LE_REQ_CHANNEL(x)	((x) << S_CPL_T7_SET_LE_REQ_CHANNEL)
+#define G_CPL_T7_SET_LE_REQ_CHANNEL(x)	\
+    (((x) >> S_CPL_T7_SET_LE_REQ_CHANNEL) & M_CPL_T7_SET_LE_REQ_CHANNEL)
+
 struct cpl_set_le_rpl {
 	RSS_HDR
 	union opcode_tid ot;
@@ -2710,6 +4502,7 @@ enum {
 	FW_TYPE_WRERR_RPL = 5,
 	FW_TYPE_PI_ERR = 6,
 	FW_TYPE_TLS_KEY = 7,
+	FW_TYPE_IPSEC_SA = 8,
 };
 
 struct cpl_fw2_pld {
@@ -2811,6 +4604,8 @@ enum {
 	FW6_TYPE_RSSCPL		= FW_TYPE_RSSCPL,
 	FW6_TYPE_WRERR_RPL	= FW_TYPE_WRERR_RPL,
 	FW6_TYPE_PI_ERR		= FW_TYPE_PI_ERR,
+	FW6_TYPE_TLS_KEY	= FW_TYPE_TLS_KEY,
+	FW6_TYPE_IPSEC_SA	= FW_TYPE_IPSEC_SA,
 	NUM_FW6_TYPES
 };
 
@@ -2932,6 +4727,10 @@ struct ulp_mem_io {
 #define M_ULP_MEMIO_DATA_LEN    0x1F
 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
 
+#define S_T7_ULP_MEMIO_DATA_LEN    0
+#define M_T7_ULP_MEMIO_DATA_LEN    0x7FF
+#define V_T7_ULP_MEMIO_DATA_LEN(x) ((x) << S_T7_ULP_MEMIO_DATA_LEN)
+
 /* ULP_TXPKT field values */
 enum {
 	ULP_TXPKT_DEST_TP = 0,
@@ -2960,11 +4759,25 @@ struct ulp_txpkt {
 	(((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID)
 #define F_ULP_TXPKT_CHANNELID        V_ULP_TXPKT_CHANNELID(1U)
 
+#define S_T7_ULP_TXPKT_CHANNELID        22
+#define M_T7_ULP_TXPKT_CHANNELID        0x3
+#define V_T7_ULP_TXPKT_CHANNELID(x)     ((x) << S_T7_ULP_TXPKT_CHANNELID)
+#define G_T7_ULP_TXPKT_CHANNELID(x)     \
+	(((x) >> S_T7_ULP_TXPKT_CHANNELID) & M_T7_ULP_TXPKT_CHANNELID)
+#define F_T7_ULP_TXPKT_CHANNELID        V_T7_ULP_TXPKT_CHANNELID(1U)
+
 /* ulp_txpkt.cmd_dest fields */
 #define S_ULP_TXPKT_DEST    16
 #define M_ULP_TXPKT_DEST    0x3
 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
 
+#define S_ULP_TXPKT_CMDMORE		15
+#define M_ULP_TXPKT_CMDMORE		0x1
+#define V_ULP_TXPKT_CMDMORE(x)	((x) << S_ULP_TXPKT_CMDMORE)
+#define G_ULP_TXPKT_CMDMORE(x)	\
+    (((x) >> S_ULP_TXPKT_CMDMORE) & M_ULP_TXPKT_CMDMORE)
+#define F_ULP_TXPKT_CMDMORE	V_ULP_TXPKT_CMDMORE(1U)
+
 #define S_ULP_TXPKT_FID	    4
 #define M_ULP_TXPKT_FID     0x7ff
 #define V_ULP_TXPKT_FID(x)  ((x) << S_ULP_TXPKT_FID)
@@ -2978,13 +4791,15 @@ enum cpl_tx_tnl_lso_type {
 	TX_TNL_TYPE_NVGRE,
 	TX_TNL_TYPE_VXLAN,
 	TX_TNL_TYPE_GENEVE,
+	TX_TNL_TYPE_IPSEC,
 };
 
 struct cpl_tx_tnl_lso {
 	__be32 op_to_IpIdSplitOut;
 	__be16 IpIdOffsetOut;
 	__be16 UdpLenSetOut_to_TnlHdrLen;
-	__be64 r1;
+	__be32 ipsecen_to_rocev2;
+	__be32 roce_eth;
 	__be32 Flow_to_TcpHdrLen;
 	__be16 IpIdOffset;
 	__be16 IpIdSplit_to_Mss;
@@ -3098,6 +4913,68 @@ struct cpl_tx_tnl_lso {
 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x)	\
     (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN)
 
+#define S_CPL_TX_TNL_LSO_IPSECEN	31
+#define M_CPL_TX_TNL_LSO_IPSECEN	0x1
+#define V_CPL_TX_TNL_LSO_IPSECEN(x)	((x) << S_CPL_TX_TNL_LSO_IPSECEN)
+#define G_CPL_TX_TNL_LSO_IPSECEN(x)	\
+    (((x) >> S_CPL_TX_TNL_LSO_IPSECEN) & M_CPL_TX_TNL_LSO_IPSECEN)
+#define F_CPL_TX_TNL_LSO_IPSECEN	V_CPL_TX_TNL_LSO_IPSECEN(1U)
+
+#define S_CPL_TX_TNL_LSO_ENCAPDIS	30
+#define M_CPL_TX_TNL_LSO_ENCAPDIS	0x1
+#define V_CPL_TX_TNL_LSO_ENCAPDIS(x)	((x) << S_CPL_TX_TNL_LSO_ENCAPDIS)
+#define G_CPL_TX_TNL_LSO_ENCAPDIS(x)	\
+    (((x) >> S_CPL_TX_TNL_LSO_ENCAPDIS) & M_CPL_TX_TNL_LSO_ENCAPDIS)
+#define F_CPL_TX_TNL_LSO_ENCAPDIS	V_CPL_TX_TNL_LSO_ENCAPDIS(1U)
+
+#define S_CPL_TX_TNL_LSO_IPSECMODE	29
+#define M_CPL_TX_TNL_LSO_IPSECMODE	0x1
+#define V_CPL_TX_TNL_LSO_IPSECMODE(x)	((x) << S_CPL_TX_TNL_LSO_IPSECMODE)
+#define G_CPL_TX_TNL_LSO_IPSECMODE(x)	\
+    (((x) >> S_CPL_TX_TNL_LSO_IPSECMODE) & M_CPL_TX_TNL_LSO_IPSECMODE)
+#define F_CPL_TX_TNL_LSO_IPSECMODE	V_CPL_TX_TNL_LSO_IPSECMODE(1U)
+
+#define S_CPL_TX_TNL_LSO_IPSECTNLIPV6	28
+#define M_CPL_TX_TNL_LSO_IPSECTNLIPV6	0x1
+#define V_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \
+    ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPV6)
+#define G_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \
+    (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPV6) & M_CPL_TX_TNL_LSO_IPSECTNLIPV6)
+#define F_CPL_TX_TNL_LSO_IPSECTNLIPV6	V_CPL_TX_TNL_LSO_IPSECTNLIPV6(1U)
+
+#define S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN 20
+#define M_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN 0xff
+#define V_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \
+    ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN)
+#define G_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \
+    (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) & \
+     M_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN)
+
+#define S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT 19
+#define M_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT 0x1
+#define V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \
+    ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT)
+#define G_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \
+    (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) & \
+     M_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT)
+#define F_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT \
+    V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(1U)
+
+#define S_CPL_TX_TNL_LSO_ROCEV2		18
+#define M_CPL_TX_TNL_LSO_ROCEV2		0x1
+#define V_CPL_TX_TNL_LSO_ROCEV2(x)	((x) << S_CPL_TX_TNL_LSO_ROCEV2)
+#define G_CPL_TX_TNL_LSO_ROCEV2(x)	\
+    (((x) >> S_CPL_TX_TNL_LSO_ROCEV2) & M_CPL_TX_TNL_LSO_ROCEV2)
+#define F_CPL_TX_TNL_LSO_ROCEV2		V_CPL_TX_TNL_LSO_ROCEV2(1U)
+
+#define S_CPL_TX_TNL_LSO_UDPCHKUPDOUT	17
+#define M_CPL_TX_TNL_LSO_UDPCHKUPDOUT	0x1
+#define V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \
+    ((x) << S_CPL_TX_TNL_LSO_UDPCHKUPDOUT)
+#define G_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \
+    (((x) >> S_CPL_TX_TNL_LSO_UDPCHKUPDOUT) & M_CPL_TX_TNL_LSO_UDPCHKUPDOUT)
+#define F_CPL_TX_TNL_LSO_UDPCHKUPDOUT	V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(1U)
+
 #define S_CPL_TX_TNL_LSO_FLOW		21
 #define M_CPL_TX_TNL_LSO_FLOW		0x1
 #define V_CPL_TX_TNL_LSO_FLOW(x)	((x) << S_CPL_TX_TNL_LSO_FLOW)
@@ -3180,6 +5057,12 @@ struct cpl_rx_mps_pkt {
 #define G_CPL_RX_MPS_PKT_TYPE(x)        \
 	(((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE)
 
+#define S_CPL_RX_MPS_PKT_LENGTH     0
+#define M_CPL_RX_MPS_PKT_LENGTH     0xffff
+#define V_CPL_RX_MPS_PKT_LENGTH(x)  ((x) << S_CPL_RX_MPS_PKT_LENGTH)
+#define G_CPL_RX_MPS_PKT_LENGTH(x)  \
+    (((x) >> S_CPL_RX_MPS_PKT_LENGTH) & M_CPL_RX_MPS_PKT_LENGTH)
+
 /*
  * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field.
  */
@@ -3188,6 +5071,88 @@ struct cpl_rx_mps_pkt {
 #define X_CPL_RX_MPS_PKT_TYPE_QFC	(1 << 2)
 #define X_CPL_RX_MPS_PKT_TYPE_PTP	(1 << 3)
 
+struct cpl_t7_rx_mps_pkt {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 length_pkd;
+};
+
+#define S_CPL_T7_RX_MPS_PKT_TYPE	20
+#define M_CPL_T7_RX_MPS_PKT_TYPE	0xf
+#define V_CPL_T7_RX_MPS_PKT_TYPE(x)	((x) << S_CPL_T7_RX_MPS_PKT_TYPE)
+#define G_CPL_T7_RX_MPS_PKT_TYPE(x)	\
+    (((x) >> S_CPL_T7_RX_MPS_PKT_TYPE) & M_CPL_T7_RX_MPS_PKT_TYPE)
+
+#define S_CPL_T7_RX_MPS_PKT_INTERFACE		16
+#define M_CPL_T7_RX_MPS_PKT_INTERFACE		0xf
+#define V_CPL_T7_RX_MPS_PKT_INTERFACE(x)	\
+    ((x) << S_CPL_T7_RX_MPS_PKT_INTERFACE)
+#define G_CPL_T7_RX_MPS_PKT_INTERFACE(x)	\
+    (((x) >> S_CPL_T7_RX_MPS_PKT_INTERFACE) & M_CPL_T7_RX_MPS_PKT_INTERFACE)
+
+#define S_CPL_T7_RX_MPS_PKT_TRUNCATED		7
+#define M_CPL_T7_RX_MPS_PKT_TRUNCATED		0x1
+#define V_CPL_T7_RX_MPS_PKT_TRUNCATED(x)	\
+    ((x) << S_CPL_T7_RX_MPS_PKT_TRUNCATED)
+#define G_CPL_T7_RX_MPS_PKT_TRUNCATED(x)	\
+    (((x) >> S_CPL_T7_RX_MPS_PKT_TRUNCATED) & M_CPL_T7_RX_MPS_PKT_TRUNCATED)
+#define F_CPL_T7_RX_MPS_PKT_TRUNCATED	V_CPL_T7_RX_MPS_PKT_TRUNCATED(1U)
+
+#define S_CPL_T7_RX_MPS_PKT_PKTERR	6
+#define M_CPL_T7_RX_MPS_PKT_PKTERR	0x1
+#define V_CPL_T7_RX_MPS_PKT_PKTERR(x)	((x) << S_CPL_T7_RX_MPS_PKT_PKTERR)
+#define G_CPL_T7_RX_MPS_PKT_PKTERR(x)	\
+    (((x) >> S_CPL_T7_RX_MPS_PKT_PKTERR) & M_CPL_T7_RX_MPS_PKT_PKTERR)
+#define F_CPL_T7_RX_MPS_PKT_PKTERR	V_CPL_T7_RX_MPS_PKT_PKTERR(1U)
+
+#define S_CPL_T7_RX_MPS_PKT_LENGTH	0
+#define M_CPL_T7_RX_MPS_PKT_LENGTH	0xffff
+#define V_CPL_T7_RX_MPS_PKT_LENGTH(x)	((x) << S_CPL_T7_RX_MPS_PKT_LENGTH)
+#define G_CPL_T7_RX_MPS_PKT_LENGTH(x)	\
+    (((x) >> S_CPL_T7_RX_MPS_PKT_LENGTH) & M_CPL_T7_RX_MPS_PKT_LENGTH)
+
+struct cpl_tx_tls_pdu {
+	WR_HDR;
+	union opcode_tid ot;
+	__be32 pldlen_pkd;
+	__be32 customtype_customprotover;
+	__be32 r2_lo;
+	__be32 scmd0[2];
+	__be32 scmd1[2];
+};
+
+#define S_CPL_TX_TLS_PDU_DATATYPE	20
+#define M_CPL_TX_TLS_PDU_DATATYPE	0xf
+#define V_CPL_TX_TLS_PDU_DATATYPE(x)	((x) << S_CPL_TX_TLS_PDU_DATATYPE)
+#define G_CPL_TX_TLS_PDU_DATATYPE(x)	\
+    (((x) >> S_CPL_TX_TLS_PDU_DATATYPE) & M_CPL_TX_TLS_PDU_DATATYPE)
+
+#define S_CPL_TX_TLS_PDU_CPLLEN		16
+#define M_CPL_TX_TLS_PDU_CPLLEN		0xf
+#define V_CPL_TX_TLS_PDU_CPLLEN(x)	((x) << S_CPL_TX_TLS_PDU_CPLLEN)
+#define G_CPL_TX_TLS_PDU_CPLLEN(x)	\
+    (((x) >> S_CPL_TX_TLS_PDU_CPLLEN) & M_CPL_TX_TLS_PDU_CPLLEN)
+
+#define S_CPL_TX_TLS_PDU_PLDLEN		0
+#define M_CPL_TX_TLS_PDU_PLDLEN		0xfffff
+#define V_CPL_TX_TLS_PDU_PLDLEN(x)	((x) << S_CPL_TX_TLS_PDU_PLDLEN)
+#define G_CPL_TX_TLS_PDU_PLDLEN(x)	\
+    (((x) >> S_CPL_TX_TLS_PDU_PLDLEN) & M_CPL_TX_TLS_PDU_PLDLEN)
+
+#define S_CPL_TX_TLS_PDU_CUSTOMTYPE	24
+#define M_CPL_TX_TLS_PDU_CUSTOMTYPE	0xff
+#define V_CPL_TX_TLS_PDU_CUSTOMTYPE(x)	((x) << S_CPL_TX_TLS_PDU_CUSTOMTYPE)
+#define G_CPL_TX_TLS_PDU_CUSTOMTYPE(x)	\
+    (((x) >> S_CPL_TX_TLS_PDU_CUSTOMTYPE) & M_CPL_TX_TLS_PDU_CUSTOMTYPE)
+
+#define S_CPL_TX_TLS_PDU_CUSTOMPROTOVER	8
+#define M_CPL_TX_TLS_PDU_CUSTOMPROTOVER	0xffff
+#define V_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \
+    ((x) << S_CPL_TX_TLS_PDU_CUSTOMPROTOVER)
+#define G_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \
+    (((x) >> S_CPL_TX_TLS_PDU_CUSTOMPROTOVER) & \
+     M_CPL_TX_TLS_PDU_CUSTOMPROTOVER)
+
 struct cpl_tx_tls_sfo {
 	__be32 op_to_seg_len;
 	__be32 pld_len;
@@ -3223,6 +5188,12 @@ struct cpl_tx_tls_sfo {
 #define G_CPL_TX_TLS_SFO_SEG_LEN(x)     \
 	(((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN)
 
+#define S_CPL_TX_TLS_SFO_PLDLEN		0
+#define M_CPL_TX_TLS_SFO_PLDLEN		0xfffff
+#define V_CPL_TX_TLS_SFO_PLDLEN(x)	((x) << S_CPL_TX_TLS_SFO_PLDLEN)
+#define G_CPL_TX_TLS_SFO_PLDLEN(x)	\
+    (((x) >> S_CPL_TX_TLS_SFO_PLDLEN) & M_CPL_TX_TLS_SFO_PLDLEN)
+
 #define S_CPL_TX_TLS_SFO_TYPE           24
 #define M_CPL_TX_TLS_SFO_TYPE           0xff
 #define V_CPL_TX_TLS_SFO_TYPE(x)        ((x) << S_CPL_TX_TLS_SFO_TYPE)
@@ -3454,6 +5425,119 @@ struct cpl_rx_tls_cmp {
 #define G_SCMD_HDR_LEN(x)   \
 	(((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN)
 
+struct cpl_rx_pkt_ipsec {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 vlan;
+	__be16 length;
+	__be32 rxchannel_to_ethhdrlen;
+	__be32 iphdrlen_to_rxerror;
+	__be64 timestamp;
+};
+
+#define S_CPL_RX_PKT_IPSEC_OPCODE	24
+#define M_CPL_RX_PKT_IPSEC_OPCODE	0xff
+#define V_CPL_RX_PKT_IPSEC_OPCODE(x)	((x) << S_CPL_RX_PKT_IPSEC_OPCODE)
+#define G_CPL_RX_PKT_IPSEC_OPCODE(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_OPCODE) & M_CPL_RX_PKT_IPSEC_OPCODE)
+
+#define S_CPL_RX_PKT_IPSEC_IPFRAG	23
+#define M_CPL_RX_PKT_IPSEC_IPFRAG	0x1
+#define V_CPL_RX_PKT_IPSEC_IPFRAG(x)	((x) << S_CPL_RX_PKT_IPSEC_IPFRAG)
+#define G_CPL_RX_PKT_IPSEC_IPFRAG(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_IPFRAG) & M_CPL_RX_PKT_IPSEC_IPFRAG)
+#define F_CPL_RX_PKT_IPSEC_IPFRAG	V_CPL_RX_PKT_IPSEC_IPFRAG(1U)
+
+#define S_CPL_RX_PKT_IPSEC_VLAN_EX	22
+#define M_CPL_RX_PKT_IPSEC_VLAN_EX	0x1
+#define V_CPL_RX_PKT_IPSEC_VLAN_EX(x)	((x) << S_CPL_RX_PKT_IPSEC_VLAN_EX)
+#define G_CPL_RX_PKT_IPSEC_VLAN_EX(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_VLAN_EX) & M_CPL_RX_PKT_IPSEC_VLAN_EX)
+#define F_CPL_RX_PKT_IPSEC_VLAN_EX	V_CPL_RX_PKT_IPSEC_VLAN_EX(1U)
+
+#define S_CPL_RX_PKT_IPSEC_IPMI		21
+#define M_CPL_RX_PKT_IPSEC_IPMI		0x1
+#define V_CPL_RX_PKT_IPSEC_IPMI(x)	((x) << S_CPL_RX_PKT_IPSEC_IPMI)
+#define G_CPL_RX_PKT_IPSEC_IPMI(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_IPMI) & M_CPL_RX_PKT_IPSEC_IPMI)
+#define F_CPL_RX_PKT_IPSEC_IPMI		V_CPL_RX_PKT_IPSEC_IPMI(1U)
+
+#define S_CPL_RX_PKT_IPSEC_INTERFACE	16
+#define M_CPL_RX_PKT_IPSEC_INTERFACE	0xf
+#define V_CPL_RX_PKT_IPSEC_INTERFACE(x)	((x) << S_CPL_RX_PKT_IPSEC_INTERFACE)
+#define G_CPL_RX_PKT_IPSEC_INTERFACE(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_INTERFACE) & M_CPL_RX_PKT_IPSEC_INTERFACE)
+
+#define S_CPL_RX_PKT_IPSEC_IPSECEXTERR	12
+#define M_CPL_RX_PKT_IPSEC_IPSECEXTERR	0xf
+#define V_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \
+    ((x) << S_CPL_RX_PKT_IPSEC_IPSECEXTERR)
+#define G_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \
+    (((x) >> S_CPL_RX_PKT_IPSEC_IPSECEXTERR) & M_CPL_RX_PKT_IPSEC_IPSECEXTERR)
+
+#define S_CPL_RX_PKT_IPSEC_IPSECTYPE	10
+#define M_CPL_RX_PKT_IPSEC_IPSECTYPE	0x3
+#define V_CPL_RX_PKT_IPSEC_IPSECTYPE(x)	((x) << S_CPL_RX_PKT_IPSEC_IPSECTYPE)
+#define G_CPL_RX_PKT_IPSEC_IPSECTYPE(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_IPSECTYPE) & M_CPL_RX_PKT_IPSEC_IPSECTYPE)
+
+#define S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN	0
+#define M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN	0x3ff
+#define V_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \
+    ((x) << S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN)
+#define G_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \
+    (((x) >> S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) & M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN)
+
+#define S_CPL_RX_PKT_IPSEC_RXCHANNEL	28
+#define M_CPL_RX_PKT_IPSEC_RXCHANNEL	0xf
+#define V_CPL_RX_PKT_IPSEC_RXCHANNEL(x)	((x) << S_CPL_RX_PKT_IPSEC_RXCHANNEL)
+#define G_CPL_RX_PKT_IPSEC_RXCHANNEL(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_RXCHANNEL) & M_CPL_RX_PKT_IPSEC_RXCHANNEL)
+
+#define S_CPL_RX_PKT_IPSEC_FLAGS	20
+#define M_CPL_RX_PKT_IPSEC_FLAGS	0xff
+#define V_CPL_RX_PKT_IPSEC_FLAGS(x)	((x) << S_CPL_RX_PKT_IPSEC_FLAGS)
+#define G_CPL_RX_PKT_IPSEC_FLAGS(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_FLAGS) & M_CPL_RX_PKT_IPSEC_FLAGS)
+
+#define S_CPL_RX_PKT_IPSEC_MACMATCHTYPE	17
+#define M_CPL_RX_PKT_IPSEC_MACMATCHTYPE	0x7
+#define V_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \
+    ((x) << S_CPL_RX_PKT_IPSEC_MACMATCHTYPE)
+#define G_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \
+    (((x) >> S_CPL_RX_PKT_IPSEC_MACMATCHTYPE) & \
+     M_CPL_RX_PKT_IPSEC_MACMATCHTYPE)
+
+#define S_CPL_RX_PKT_IPSEC_MACINDEX	8
+#define M_CPL_RX_PKT_IPSEC_MACINDEX	0x1ff
+#define V_CPL_RX_PKT_IPSEC_MACINDEX(x)	((x) << S_CPL_RX_PKT_IPSEC_MACINDEX)
+#define G_CPL_RX_PKT_IPSEC_MACINDEX(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_MACINDEX) & M_CPL_RX_PKT_IPSEC_MACINDEX)
+
+#define S_CPL_RX_PKT_IPSEC_ETHHDRLEN	0
+#define M_CPL_RX_PKT_IPSEC_ETHHDRLEN	0xff
+#define V_CPL_RX_PKT_IPSEC_ETHHDRLEN(x)	((x) << S_CPL_RX_PKT_IPSEC_ETHHDRLEN)
+#define G_CPL_RX_PKT_IPSEC_ETHHDRLEN(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_ETHHDRLEN) & M_CPL_RX_PKT_IPSEC_ETHHDRLEN)
+
+#define S_CPL_RX_PKT_IPSEC_IPHDRLEN	22
+#define M_CPL_RX_PKT_IPSEC_IPHDRLEN	0x3ff
+#define V_CPL_RX_PKT_IPSEC_IPHDRLEN(x)	((x) << S_CPL_RX_PKT_IPSEC_IPHDRLEN)
+#define G_CPL_RX_PKT_IPSEC_IPHDRLEN(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_IPHDRLEN) & M_CPL_RX_PKT_IPSEC_IPHDRLEN)
+
+#define S_CPL_RX_PKT_IPSEC_TCPHDRLEN	16
+#define M_CPL_RX_PKT_IPSEC_TCPHDRLEN	0x3f
+#define V_CPL_RX_PKT_IPSEC_TCPHDRLEN(x)	((x) << S_CPL_RX_PKT_IPSEC_TCPHDRLEN)
+#define G_CPL_RX_PKT_IPSEC_TCPHDRLEN(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_TCPHDRLEN) & M_CPL_RX_PKT_IPSEC_TCPHDRLEN)
+
+#define S_CPL_RX_PKT_IPSEC_RXERROR	0
+#define M_CPL_RX_PKT_IPSEC_RXERROR	0xffff
+#define V_CPL_RX_PKT_IPSEC_RXERROR(x)	((x) << S_CPL_RX_PKT_IPSEC_RXERROR)
+#define G_CPL_RX_PKT_IPSEC_RXERROR(x)	\
+    (((x) >> S_CPL_RX_PKT_IPSEC_RXERROR) & M_CPL_RX_PKT_IPSEC_RXERROR)
+
 struct cpl_tx_sec_pdu {
 	__be32 op_ivinsrtofst;
 	__be32 pldlen;
@@ -3478,6 +5562,13 @@ struct cpl_tx_sec_pdu {
 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID)
 #define F_CPL_TX_SEC_PDU_RXCHID  V_CPL_TX_SEC_PDU_RXCHID(1U)
 
+#define S_T7_CPL_TX_SEC_PDU_RXCHID  22
+#define M_T7_CPL_TX_SEC_PDU_RXCHID  0x3
+#define V_T7_CPL_TX_SEC_PDU_RXCHID(x)   ((x) << S_T7_CPL_TX_SEC_PDU_RXCHID)
+#define G_T7_CPL_TX_SEC_PDU_RXCHID(x)   \
+(((x) >> S_T7_CPL_TX_SEC_PDU_RXCHID) & M_T7_CPL_TX_SEC_PDU_RXCHID)
+#define F_T7_CPL_TX_SEC_PDU_RXCHID  V_T7_CPL_TX_SEC_PDU_RXCHID(1U)
+
 /* Ack Follows */
 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS  21
 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS  0x1
@@ -3501,6 +5592,13 @@ struct cpl_tx_sec_pdu {
 #define G_CPL_TX_SEC_PDU_CPLLEN(x)  \
 	(((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN)
 
+#define S_CPL_TX_SEC_PDU_ACKNEXT	15
+#define M_CPL_TX_SEC_PDU_ACKNEXT	0x1
+#define V_CPL_TX_SEC_PDU_ACKNEXT(x)	((x) << S_CPL_TX_SEC_PDU_ACKNEXT)
+#define G_CPL_TX_SEC_PDU_ACKNEXT(x)	\
+    (((x) >> S_CPL_TX_SEC_PDU_ACKNEXT) & M_CPL_TX_SEC_PDU_ACKNEXT)
+#define F_CPL_TX_SEC_PDU_ACKNEXT	V_CPL_TX_SEC_PDU_ACKNEXT(1U)
+
 /* PlaceHolder */
 #define S_CPL_TX_SEC_PDU_PLACEHOLDER    10
 #define M_CPL_TX_SEC_PDU_PLACEHOLDER    0x1
@@ -3517,6 +5615,12 @@ struct cpl_tx_sec_pdu {
 	(((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \
 	 M_CPL_TX_SEC_PDU_IVINSRTOFST)
 
+#define S_CPL_TX_SEC_PDU_PLDLEN		0
+#define M_CPL_TX_SEC_PDU_PLDLEN		0xfffff
+#define V_CPL_TX_SEC_PDU_PLDLEN(x)	((x) << S_CPL_TX_SEC_PDU_PLDLEN)
+#define G_CPL_TX_SEC_PDU_PLDLEN(x)	\
+    (((x) >> S_CPL_TX_SEC_PDU_PLDLEN) & M_CPL_TX_SEC_PDU_PLDLEN)
+
 /* AadStartOffset: Offset in bytes for AAD start from
  * the first byte following
  * the pkt headers (0-255
@@ -3666,6 +5770,62 @@ struct cpl_rx_phys_dsgl {
 	(((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \
 	 M_CPL_RX_PHYS_DSGL_NOOFSGENTR)
 
+struct cpl_t7_rx_phys_dsgl {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 PhysAddrFields_lo_to_NumSGE;
+	__be32 RSSCopy[2];
+};
+
+#define S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI 0
+#define M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI 0xffffff
+#define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \
+    ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI)
+#define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \
+    (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) & \
+     M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI)
+
+#define S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO 16
+#define M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO 0xffff
+#define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \
+    ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO)
+#define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \
+    (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) & \
+     M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO)
+
+#define S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR		11
+#define M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR		0x1
+#define V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x)	\
+    ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR)
+#define G_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x)	\
+    (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) & M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR)
+#define F_CPL_T7_RX_PHYS_DSGL_NUMSGEERR	V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(1U)
+
+#define S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE	10
+#define M_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE	0x1
+#define V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x)	\
+    ((x) << S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE)
+#define G_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x)	\
+    (((x) >> S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) & \
+     M_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE)
+#define F_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE	\
+    V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(1U)
+
+#define S_CPL_T7_RX_PHYS_DSGL_SPLITMODE		9
+#define M_CPL_T7_RX_PHYS_DSGL_SPLITMODE		0x1
+#define V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x)	\
+    ((x) << S_CPL_T7_RX_PHYS_DSGL_SPLITMODE)
+#define G_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x)	\
+    (((x) >> S_CPL_T7_RX_PHYS_DSGL_SPLITMODE) & M_CPL_T7_RX_PHYS_DSGL_SPLITMODE)
+#define F_CPL_T7_RX_PHYS_DSGL_SPLITMODE		\
+    V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(1U)
+
+#define S_CPL_T7_RX_PHYS_DSGL_NUMSGE	0
+#define M_CPL_T7_RX_PHYS_DSGL_NUMSGE	0x1ff
+#define V_CPL_T7_RX_PHYS_DSGL_NUMSGE(x)	((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGE)
+#define G_CPL_T7_RX_PHYS_DSGL_NUMSGE(x)	\
+    (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGE) & M_CPL_T7_RX_PHYS_DSGL_NUMSGE)
+
 /* CPL_TX_TLS_ACK */
 struct cpl_tx_tls_ack {
         __be32 op_to_Rsvd2;
@@ -3679,12 +5839,11 @@ struct cpl_tx_tls_ack {
 #define G_CPL_TX_TLS_ACK_OPCODE(x)      \
     (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE)
 
-#define S_CPL_TX_TLS_ACK_RSVD1          23
-#define M_CPL_TX_TLS_ACK_RSVD1          0x1
-#define V_CPL_TX_TLS_ACK_RSVD1(x)       ((x) << S_CPL_TX_TLS_ACK_RSVD1)
-#define G_CPL_TX_TLS_ACK_RSVD1(x)       \
-    (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1)
-#define F_CPL_TX_TLS_ACK_RSVD1  V_CPL_TX_TLS_ACK_RSVD1(1U)
+#define S_T7_CPL_TX_TLS_ACK_RXCHID		22
+#define M_T7_CPL_TX_TLS_ACK_RXCHID		0x3
+#define V_T7_CPL_TX_TLS_ACK_RXCHID(x)	((x) << S_T7_CPL_TX_TLS_ACK_RXCHID)
+#define G_T7_CPL_TX_TLS_ACK_RXCHID(x)	\
+    (((x) >> S_T7_CPL_TX_TLS_ACK_RXCHID) & M_T7_CPL_TX_TLS_ACK_RXCHID)
 
 #define S_CPL_TX_TLS_ACK_RXCHID         22
 #define M_CPL_TX_TLS_ACK_RXCHID         0x1
@@ -3740,4 +5899,822 @@ struct cpl_tx_tls_ack {
 #define G_CPL_TX_TLS_ACK_RSVD2(x)       \
     (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2)
 
+#define S_CPL_TX_TLS_ACK_PLDLEN		0
+#define M_CPL_TX_TLS_ACK_PLDLEN		0xfffff
+#define V_CPL_TX_TLS_ACK_PLDLEN(x)	((x) << S_CPL_TX_TLS_ACK_PLDLEN)
+#define G_CPL_TX_TLS_ACK_PLDLEN(x)	\
+    (((x) >> S_CPL_TX_TLS_ACK_PLDLEN) & M_CPL_TX_TLS_ACK_PLDLEN)
+
+struct cpl_rcb_upd {
+	__be32 op_to_tid;
+	__be32 opcode_psn;
+	__u8   nodata_to_cnprepclr;
+	__u8   r0;
+	__be16 wrptr;
+	__be32 length;
+};
+
+#define S_CPL_RCB_UPD_OPCODE		24
+#define M_CPL_RCB_UPD_OPCODE		0xff
+#define V_CPL_RCB_UPD_OPCODE(x)		((x) << S_CPL_RCB_UPD_OPCODE)
+#define G_CPL_RCB_UPD_OPCODE(x)		\
+    (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE)
+
+#define S_CPL_RCB_UPD_TID		0
+#define M_CPL_RCB_UPD_TID		0xffffff
+#define V_CPL_RCB_UPD_TID(x)		((x) << S_CPL_RCB_UPD_TID)
+#define G_CPL_RCB_UPD_TID(x)		\
+    (((x) >> S_CPL_RCB_UPD_TID) & M_CPL_RCB_UPD_TID)
+
+#define S_CPL_RCB_UPD_OPCODE		24
+#define M_CPL_RCB_UPD_OPCODE		0xff
+#define V_CPL_RCB_UPD_OPCODE(x)		((x) << S_CPL_RCB_UPD_OPCODE)
+#define G_CPL_RCB_UPD_OPCODE(x)		\
+    (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE)
+
+#define S_CPL_RCB_UPD_PSN		0
+#define M_CPL_RCB_UPD_PSN		0xffffff
+#define V_CPL_RCB_UPD_PSN(x)		((x) << S_CPL_RCB_UPD_PSN)
+#define G_CPL_RCB_UPD_PSN(x)		\
+    (((x) >> S_CPL_RCB_UPD_PSN) & M_CPL_RCB_UPD_PSN)
+
+#define S_CPL_RCB_UPD_NODATA		7
+#define M_CPL_RCB_UPD_NODATA		0x1
+#define V_CPL_RCB_UPD_NODATA(x)		((x) << S_CPL_RCB_UPD_NODATA)
+#define G_CPL_RCB_UPD_NODATA(x)		\
+    (((x) >> S_CPL_RCB_UPD_NODATA) & M_CPL_RCB_UPD_NODATA)
+#define F_CPL_RCB_UPD_NODATA		V_CPL_RCB_UPD_NODATA(1U)
+
+#define S_CPL_RCB_UPD_RTTSTAMP		6
+#define M_CPL_RCB_UPD_RTTSTAMP		0x1
+#define V_CPL_RCB_UPD_RTTSTAMP(x)	((x) << S_CPL_RCB_UPD_RTTSTAMP)
+#define G_CPL_RCB_UPD_RTTSTAMP(x)	\
+    (((x) >> S_CPL_RCB_UPD_RTTSTAMP) & M_CPL_RCB_UPD_RTTSTAMP)
+#define F_CPL_RCB_UPD_RTTSTAMP		V_CPL_RCB_UPD_RTTSTAMP(1U)
+
+#define S_CPL_RCB_UPD_ECNREPCLR		5
+#define M_CPL_RCB_UPD_ECNREPCLR		0x1
+#define V_CPL_RCB_UPD_ECNREPCLR(x)	((x) << S_CPL_RCB_UPD_ECNREPCLR)
+#define G_CPL_RCB_UPD_ECNREPCLR(x)	\
+    (((x) >> S_CPL_RCB_UPD_ECNREPCLR) & M_CPL_RCB_UPD_ECNREPCLR)
+#define F_CPL_RCB_UPD_ECNREPCLR		V_CPL_RCB_UPD_ECNREPCLR(1U)
+
+#define S_CPL_RCB_UPD_NAKSEQCLR		4
+#define M_CPL_RCB_UPD_NAKSEQCLR		0x1
+#define V_CPL_RCB_UPD_NAKSEQCLR(x)	((x) << S_CPL_RCB_UPD_NAKSEQCLR)
+#define G_CPL_RCB_UPD_NAKSEQCLR(x)	\
+    (((x) >> S_CPL_RCB_UPD_NAKSEQCLR) & M_CPL_RCB_UPD_NAKSEQCLR)
+#define F_CPL_RCB_UPD_NAKSEQCLR		V_CPL_RCB_UPD_NAKSEQCLR(1U)
+
+#define S_CPL_RCB_UPD_QPERRSET		3
+#define M_CPL_RCB_UPD_QPERRSET		0x1
+#define V_CPL_RCB_UPD_QPERRSET(x)	((x) << S_CPL_RCB_UPD_QPERRSET)
+#define G_CPL_RCB_UPD_QPERRSET(x)	\
+    (((x) >> S_CPL_RCB_UPD_QPERRSET) & M_CPL_RCB_UPD_QPERRSET)
+#define F_CPL_RCB_UPD_QPERRSET		V_CPL_RCB_UPD_QPERRSET(1U)
+
+#define S_CPL_RCB_UPD_RRQUPDEN		2
+#define M_CPL_RCB_UPD_RRQUPDEN		0x1
+#define V_CPL_RCB_UPD_RRQUPDEN(x)	((x) << S_CPL_RCB_UPD_RRQUPDEN)
+#define G_CPL_RCB_UPD_RRQUPDEN(x)	\
+    (((x) >> S_CPL_RCB_UPD_RRQUPDEN) & M_CPL_RCB_UPD_RRQUPDEN)
+#define F_CPL_RCB_UPD_RRQUPDEN		V_CPL_RCB_UPD_RRQUPDEN(1U)
+
+#define S_CPL_RCB_UPD_RQUPDEN		1
+#define M_CPL_RCB_UPD_RQUPDEN		0x1
+#define V_CPL_RCB_UPD_RQUPDEN(x)	((x) << S_CPL_RCB_UPD_RQUPDEN)
+#define G_CPL_RCB_UPD_RQUPDEN(x)	\
+    (((x) >> S_CPL_RCB_UPD_RQUPDEN) & M_CPL_RCB_UPD_RQUPDEN)
+#define F_CPL_RCB_UPD_RQUPDEN		V_CPL_RCB_UPD_RQUPDEN(1U)
+
+#define S_CPL_RCB_UPD_CNPREPCLR		0
+#define M_CPL_RCB_UPD_CNPREPCLR		0x1
+#define V_CPL_RCB_UPD_CNPREPCLR(x)	((x) << S_CPL_RCB_UPD_CNPREPCLR)
+#define G_CPL_RCB_UPD_CNPREPCLR(x)	\
+    (((x) >> S_CPL_RCB_UPD_CNPREPCLR) & M_CPL_RCB_UPD_CNPREPCLR)
+#define F_CPL_RCB_UPD_CNPREPCLR		V_CPL_RCB_UPD_CNPREPCLR(1U)
+
+#define S_CPL_RCB_UPD_RSPNAKSEQCLR	7
+#define M_CPL_RCB_UPD_RSPNAKSEQCLR	0x1
+#define V_CPL_RCB_UPD_RSPNAKSEQCLR(x)	((x) << S_CPL_RCB_UPD_RSPNAKSEQCLR)
+#define G_CPL_RCB_UPD_RSPNAKSEQCLR(x)	\
+    (((x) >> S_CPL_RCB_UPD_RSPNAKSEQCLR) & M_CPL_RCB_UPD_RSPNAKSEQCLR)
+#define F_CPL_RCB_UPD_RSPNAKSEQCLR	V_CPL_RCB_UPD_RSPNAKSEQCLR(1U)
+
+struct cpl_roce_fw_notify {
+	RSS_HDR
+	union opcode_tid ot;
+	__be32 type_pkd;
+};
+
+#define S_CPL_ROCE_FW_NOTIFY_OPCODE	24
+#define M_CPL_ROCE_FW_NOTIFY_OPCODE	0xff
+#define V_CPL_ROCE_FW_NOTIFY_OPCODE(x)	((x) << S_CPL_ROCE_FW_NOTIFY_OPCODE)
+#define G_CPL_ROCE_FW_NOTIFY_OPCODE(x)	\
+    (((x) >> S_CPL_ROCE_FW_NOTIFY_OPCODE) & M_CPL_ROCE_FW_NOTIFY_OPCODE)
+
+#define S_CPL_ROCE_FW_NOTIFY_TID	0
+#define M_CPL_ROCE_FW_NOTIFY_TID	0xffffff
+#define V_CPL_ROCE_FW_NOTIFY_TID(x)	((x) << S_CPL_ROCE_FW_NOTIFY_TID)
+#define G_CPL_ROCE_FW_NOTIFY_TID(x)	\
+    (((x) >> S_CPL_ROCE_FW_NOTIFY_TID) & M_CPL_ROCE_FW_NOTIFY_TID)
+
+#define S_CPL_ROCE_FW_NOTIFY_TYPE	28
+#define M_CPL_ROCE_FW_NOTIFY_TYPE	0xf
+#define V_CPL_ROCE_FW_NOTIFY_TYPE(x)	((x) << S_CPL_ROCE_FW_NOTIFY_TYPE)
+#define G_CPL_ROCE_FW_NOTIFY_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_FW_NOTIFY_TYPE) & M_CPL_ROCE_FW_NOTIFY_TYPE)
+
+struct cpl_roce_ack_nak_req {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 type_to_opcode;
+	__be16 length;
+	__be32 psn_msn_hi;
+	__be32 msn_lo_pkd;
+};
+
+#define S_CPL_ROCE_ACK_NAK_REQ_OPCODE	24
+#define M_CPL_ROCE_ACK_NAK_REQ_OPCODE	0xff
+#define V_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \
+    ((x) << S_CPL_ROCE_ACK_NAK_REQ_OPCODE)
+#define G_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_OPCODE)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_TID	0
+#define M_CPL_ROCE_ACK_NAK_REQ_TID	0xffffff
+#define V_CPL_ROCE_ACK_NAK_REQ_TID(x)	((x) << S_CPL_ROCE_ACK_NAK_REQ_TID)
+#define G_CPL_ROCE_ACK_NAK_REQ_TID(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TID) & M_CPL_ROCE_ACK_NAK_REQ_TID)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_TYPE	12
+#define M_CPL_ROCE_ACK_NAK_REQ_TYPE	0xf
+#define V_CPL_ROCE_ACK_NAK_REQ_TYPE(x)	((x) << S_CPL_ROCE_ACK_NAK_REQ_TYPE)
+#define G_CPL_ROCE_ACK_NAK_REQ_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TYPE) & M_CPL_ROCE_ACK_NAK_REQ_TYPE)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_STATUS	8
+#define M_CPL_ROCE_ACK_NAK_REQ_STATUS	0xf
+#define V_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \
+    ((x) << S_CPL_ROCE_ACK_NAK_REQ_STATUS)
+#define G_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_STATUS) & M_CPL_ROCE_ACK_NAK_REQ_STATUS)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE	0
+#define M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE	0xff
+#define V_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \
+    ((x) << S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE)
+#define G_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_PSN	8
+#define M_CPL_ROCE_ACK_NAK_REQ_PSN	0xffffff
+#define V_CPL_ROCE_ACK_NAK_REQ_PSN(x)	((x) << S_CPL_ROCE_ACK_NAK_REQ_PSN)
+#define G_CPL_ROCE_ACK_NAK_REQ_PSN(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_PSN) & M_CPL_ROCE_ACK_NAK_REQ_PSN)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_MSN_HI	0
+#define M_CPL_ROCE_ACK_NAK_REQ_MSN_HI	0xff
+#define V_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \
+    ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_HI)
+#define G_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_HI) & M_CPL_ROCE_ACK_NAK_REQ_MSN_HI)
+
+#define S_CPL_ROCE_ACK_NAK_REQ_MSN_LO	16
+#define M_CPL_ROCE_ACK_NAK_REQ_MSN_LO	0xffff
+#define V_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \
+    ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_LO)
+#define G_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \
+    (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_LO) & M_CPL_ROCE_ACK_NAK_REQ_MSN_LO)
+
+struct cpl_roce_ack_nak {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 type_to_opcode;
+	__be16 length;
+	__be32 psn_rtt_hi;
+	__be32 rtt_lo_to_rttbad;
+};
+
+#define S_CPL_ROCE_ACK_NAK_OPCODE	24
+#define M_CPL_ROCE_ACK_NAK_OPCODE	0xff
+#define V_CPL_ROCE_ACK_NAK_OPCODE(x)	((x) << S_CPL_ROCE_ACK_NAK_OPCODE)
+#define G_CPL_ROCE_ACK_NAK_OPCODE(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_OPCODE) & M_CPL_ROCE_ACK_NAK_OPCODE)
+
+#define S_CPL_ROCE_ACK_NAK_TID		0
+#define M_CPL_ROCE_ACK_NAK_TID		0xffffff
+#define V_CPL_ROCE_ACK_NAK_TID(x)	((x) << S_CPL_ROCE_ACK_NAK_TID)
+#define G_CPL_ROCE_ACK_NAK_TID(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_TID) & M_CPL_ROCE_ACK_NAK_TID)
+
+#define S_CPL_ROCE_ACK_NAK_TYPE		12
+#define M_CPL_ROCE_ACK_NAK_TYPE		0xf
+#define V_CPL_ROCE_ACK_NAK_TYPE(x)	((x) << S_CPL_ROCE_ACK_NAK_TYPE)
+#define G_CPL_ROCE_ACK_NAK_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_TYPE) & M_CPL_ROCE_ACK_NAK_TYPE)
+
+#define S_CPL_ROCE_ACK_NAK_STATUS	8
+#define M_CPL_ROCE_ACK_NAK_STATUS	0xf
+#define V_CPL_ROCE_ACK_NAK_STATUS(x)	((x) << S_CPL_ROCE_ACK_NAK_STATUS)
+#define G_CPL_ROCE_ACK_NAK_STATUS(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_STATUS) & M_CPL_ROCE_ACK_NAK_STATUS)
+
+#define S_CPL_ROCE_ACK_NAK_WIRE_OPCODE	0
+#define M_CPL_ROCE_ACK_NAK_WIRE_OPCODE	0xff
+#define V_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x)	((x) << S_CPL_ROCE_ACK_NAK_WIRE_OPCODE)
+#define G_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_WIRE_OPCODE)
+
+#define S_CPL_ROCE_ACK_NAK_PSN		8
+#define M_CPL_ROCE_ACK_NAK_PSN		0xffffff
+#define V_CPL_ROCE_ACK_NAK_PSN(x)	((x) << S_CPL_ROCE_ACK_NAK_PSN)
+#define G_CPL_ROCE_ACK_NAK_PSN(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_PSN) & M_CPL_ROCE_ACK_NAK_PSN)
+
+#define S_CPL_ROCE_ACK_NAK_RTT_HI	0
+#define M_CPL_ROCE_ACK_NAK_RTT_HI	0xff
+#define V_CPL_ROCE_ACK_NAK_RTT_HI(x)	((x) << S_CPL_ROCE_ACK_NAK_RTT_HI)
+#define G_CPL_ROCE_ACK_NAK_RTT_HI(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_RTT_HI) & M_CPL_ROCE_ACK_NAK_RTT_HI)
+
+#define S_CPL_ROCE_ACK_NAK_RTT_LO	24
+#define M_CPL_ROCE_ACK_NAK_RTT_LO	0xff
+#define V_CPL_ROCE_ACK_NAK_RTT_LO(x)	((x) << S_CPL_ROCE_ACK_NAK_RTT_LO)
+#define G_CPL_ROCE_ACK_NAK_RTT_LO(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_RTT_LO) & M_CPL_ROCE_ACK_NAK_RTT_LO)
+
+#define S_CPL_ROCE_ACK_NAK_RTTVALID	23
+#define M_CPL_ROCE_ACK_NAK_RTTVALID	0x1
+#define V_CPL_ROCE_ACK_NAK_RTTVALID(x)	((x) << S_CPL_ROCE_ACK_NAK_RTTVALID)
+#define G_CPL_ROCE_ACK_NAK_RTTVALID(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_RTTVALID) & M_CPL_ROCE_ACK_NAK_RTTVALID)
+#define F_CPL_ROCE_ACK_NAK_RTTVALID	V_CPL_ROCE_ACK_NAK_RTTVALID(1U)
+
+#define S_CPL_ROCE_ACK_NAK_RTTBAD	22
+#define M_CPL_ROCE_ACK_NAK_RTTBAD	0x1
+#define V_CPL_ROCE_ACK_NAK_RTTBAD(x)	((x) << S_CPL_ROCE_ACK_NAK_RTTBAD)
+#define G_CPL_ROCE_ACK_NAK_RTTBAD(x)	\
+    (((x) >> S_CPL_ROCE_ACK_NAK_RTTBAD) & M_CPL_ROCE_ACK_NAK_RTTBAD)
+#define F_CPL_ROCE_ACK_NAK_RTTBAD	V_CPL_ROCE_ACK_NAK_RTTBAD(1U)
+
+struct cpl_roce_cqe {
+	__be16 op_rssctrl;
+	__be16 cqid;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+	__be32 se_to_srq;
+	__be32 rqe;
+	__be32 extinfoms[2];
+	__be32 extinfols[2];
+};
+
+#define S_CPL_ROCE_CQE_OPCODE		8
+#define M_CPL_ROCE_CQE_OPCODE		0xff
+#define V_CPL_ROCE_CQE_OPCODE(x)	((x) << S_CPL_ROCE_CQE_OPCODE)
+#define G_CPL_ROCE_CQE_OPCODE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_OPCODE) & M_CPL_ROCE_CQE_OPCODE)
+
+#define S_CPL_ROCE_CQE_RSSCTRL		0
+#define M_CPL_ROCE_CQE_RSSCTRL		0xff
+#define V_CPL_ROCE_CQE_RSSCTRL(x)	((x) << S_CPL_ROCE_CQE_RSSCTRL)
+#define G_CPL_ROCE_CQE_RSSCTRL(x)	\
+    (((x) >> S_CPL_ROCE_CQE_RSSCTRL) & M_CPL_ROCE_CQE_RSSCTRL)
+
+#define S_CPL_ROCE_CQE_TID		8
+#define M_CPL_ROCE_CQE_TID		0xfffff
+#define V_CPL_ROCE_CQE_TID(x)		((x) << S_CPL_ROCE_CQE_TID)
+#define G_CPL_ROCE_CQE_TID(x)		\
+    (((x) >> S_CPL_ROCE_CQE_TID) & M_CPL_ROCE_CQE_TID)
+
+#define S_CPL_ROCE_CQE_FLITCNT		0
+#define M_CPL_ROCE_CQE_FLITCNT		0xff
+#define V_CPL_ROCE_CQE_FLITCNT(x)	((x) << S_CPL_ROCE_CQE_FLITCNT)
+#define G_CPL_ROCE_CQE_FLITCNT(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FLITCNT) & M_CPL_ROCE_CQE_FLITCNT)
+
+#define S_CPL_ROCE_CQE_QPID		12
+#define M_CPL_ROCE_CQE_QPID		0xfffff
+#define V_CPL_ROCE_CQE_QPID(x)		((x) << S_CPL_ROCE_CQE_QPID)
+#define G_CPL_ROCE_CQE_QPID(x)		\
+    (((x) >> S_CPL_ROCE_CQE_QPID) & M_CPL_ROCE_CQE_QPID)
+
+#define S_CPL_ROCE_CQE_EXTMODE		11
+#define M_CPL_ROCE_CQE_EXTMODE		0x1
+#define V_CPL_ROCE_CQE_EXTMODE(x)	((x) << S_CPL_ROCE_CQE_EXTMODE)
+#define G_CPL_ROCE_CQE_EXTMODE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_EXTMODE) & M_CPL_ROCE_CQE_EXTMODE)
+#define F_CPL_ROCE_CQE_EXTMODE		V_CPL_ROCE_CQE_EXTMODE(1U)
+
+#define S_CPL_ROCE_CQE_GENERATION_BIT	10
+#define M_CPL_ROCE_CQE_GENERATION_BIT	0x1
+#define V_CPL_ROCE_CQE_GENERATION_BIT(x) \
+    ((x) << S_CPL_ROCE_CQE_GENERATION_BIT)
+#define G_CPL_ROCE_CQE_GENERATION_BIT(x) \
+    (((x) >> S_CPL_ROCE_CQE_GENERATION_BIT) & M_CPL_ROCE_CQE_GENERATION_BIT)
+#define F_CPL_ROCE_CQE_GENERATION_BIT	V_CPL_ROCE_CQE_GENERATION_BIT(1U)
+
+#define S_CPL_ROCE_CQE_STATUS		5
+#define M_CPL_ROCE_CQE_STATUS		0x1f
+#define V_CPL_ROCE_CQE_STATUS(x)	((x) << S_CPL_ROCE_CQE_STATUS)
+#define G_CPL_ROCE_CQE_STATUS(x)	\
+    (((x) >> S_CPL_ROCE_CQE_STATUS) & M_CPL_ROCE_CQE_STATUS)
+
+#define S_CPL_ROCE_CQE_CQE_TYPE		4
+#define M_CPL_ROCE_CQE_CQE_TYPE		0x1
+#define V_CPL_ROCE_CQE_CQE_TYPE(x)	((x) << S_CPL_ROCE_CQE_CQE_TYPE)
+#define G_CPL_ROCE_CQE_CQE_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_CQE_TYPE) & M_CPL_ROCE_CQE_CQE_TYPE)
+#define F_CPL_ROCE_CQE_CQE_TYPE		V_CPL_ROCE_CQE_CQE_TYPE(1U)
+
+#define S_CPL_ROCE_CQE_WR_TYPE		0
+#define M_CPL_ROCE_CQE_WR_TYPE		0xf
+#define V_CPL_ROCE_CQE_WR_TYPE(x)	((x) << S_CPL_ROCE_CQE_WR_TYPE)
+#define G_CPL_ROCE_CQE_WR_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_WR_TYPE) & M_CPL_ROCE_CQE_WR_TYPE)
+
+#define S_CPL_ROCE_CQE_SE		31
+#define M_CPL_ROCE_CQE_SE		0x1
+#define V_CPL_ROCE_CQE_SE(x)		((x) << S_CPL_ROCE_CQE_SE)
+#define G_CPL_ROCE_CQE_SE(x)		\
+    (((x) >> S_CPL_ROCE_CQE_SE) & M_CPL_ROCE_CQE_SE)
+#define F_CPL_ROCE_CQE_SE		V_CPL_ROCE_CQE_SE(1U)
+
+#define S_CPL_ROCE_CQE_WR_TYPE_EXT	24
+#define M_CPL_ROCE_CQE_WR_TYPE_EXT	0x7f
+#define V_CPL_ROCE_CQE_WR_TYPE_EXT(x)	((x) << S_CPL_ROCE_CQE_WR_TYPE_EXT)
+#define G_CPL_ROCE_CQE_WR_TYPE_EXT(x)	\
+    (((x) >> S_CPL_ROCE_CQE_WR_TYPE_EXT) & M_CPL_ROCE_CQE_WR_TYPE_EXT)
+
+#define S_CPL_ROCE_CQE_SRQ		0
+#define M_CPL_ROCE_CQE_SRQ		0xfff
+#define V_CPL_ROCE_CQE_SRQ(x)		((x) << S_CPL_ROCE_CQE_SRQ)
+#define G_CPL_ROCE_CQE_SRQ(x)		\
+    (((x) >> S_CPL_ROCE_CQE_SRQ) & M_CPL_ROCE_CQE_SRQ)
+
+struct cpl_roce_cqe_fw {
+	__be32 op_to_cqid;
+	__be32 tid_flitcnt;
+	__be32 qpid_to_wr_type;
+	__be32 length;
+	__be32 tag;
+	__be32 msn;
+	__be32 se_to_srq;
+	__be32 rqe;
+	__be32 extinfoms[2];
+	__be32 extinfols[2];
+};
+
+#define S_CPL_ROCE_CQE_FW_OPCODE	24
+#define M_CPL_ROCE_CQE_FW_OPCODE	0xff
+#define V_CPL_ROCE_CQE_FW_OPCODE(x)	((x) << S_CPL_ROCE_CQE_FW_OPCODE)
+#define G_CPL_ROCE_CQE_FW_OPCODE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_OPCODE) & M_CPL_ROCE_CQE_FW_OPCODE)
+
+#define S_CPL_ROCE_CQE_FW_RSSCTRL	16
+#define M_CPL_ROCE_CQE_FW_RSSCTRL	0xff
+#define V_CPL_ROCE_CQE_FW_RSSCTRL(x)	((x) << S_CPL_ROCE_CQE_FW_RSSCTRL)
+#define G_CPL_ROCE_CQE_FW_RSSCTRL(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_RSSCTRL) & M_CPL_ROCE_CQE_FW_RSSCTRL)
+
+#define S_CPL_ROCE_CQE_FW_CQID		0
+#define M_CPL_ROCE_CQE_FW_CQID		0xffff
+#define V_CPL_ROCE_CQE_FW_CQID(x)	((x) << S_CPL_ROCE_CQE_FW_CQID)
+#define G_CPL_ROCE_CQE_FW_CQID(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_CQID) & M_CPL_ROCE_CQE_FW_CQID)
+
+#define S_CPL_ROCE_CQE_FW_TID		8
+#define M_CPL_ROCE_CQE_FW_TID		0xfffff
+#define V_CPL_ROCE_CQE_FW_TID(x)	((x) << S_CPL_ROCE_CQE_FW_TID)
+#define G_CPL_ROCE_CQE_FW_TID(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_TID) & M_CPL_ROCE_CQE_FW_TID)
+
+#define S_CPL_ROCE_CQE_FW_FLITCNT	0
+#define M_CPL_ROCE_CQE_FW_FLITCNT	0xff
+#define V_CPL_ROCE_CQE_FW_FLITCNT(x)	((x) << S_CPL_ROCE_CQE_FW_FLITCNT)
+#define G_CPL_ROCE_CQE_FW_FLITCNT(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_FLITCNT) & M_CPL_ROCE_CQE_FW_FLITCNT)
+
+#define S_CPL_ROCE_CQE_FW_QPID		12
+#define M_CPL_ROCE_CQE_FW_QPID		0xfffff
+#define V_CPL_ROCE_CQE_FW_QPID(x)	((x) << S_CPL_ROCE_CQE_FW_QPID)
+#define G_CPL_ROCE_CQE_FW_QPID(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_QPID) & M_CPL_ROCE_CQE_FW_QPID)
+
+#define S_CPL_ROCE_CQE_FW_EXTMODE	11
+#define M_CPL_ROCE_CQE_FW_EXTMODE	0x1
+#define V_CPL_ROCE_CQE_FW_EXTMODE(x)	((x) << S_CPL_ROCE_CQE_FW_EXTMODE)
+#define G_CPL_ROCE_CQE_FW_EXTMODE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_EXTMODE) & M_CPL_ROCE_CQE_FW_EXTMODE)
+#define F_CPL_ROCE_CQE_FW_EXTMODE	V_CPL_ROCE_CQE_FW_EXTMODE(1U)
+
+#define S_CPL_ROCE_CQE_FW_GENERATION_BIT 10
+#define M_CPL_ROCE_CQE_FW_GENERATION_BIT 0x1
+#define V_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \
+    ((x) << S_CPL_ROCE_CQE_FW_GENERATION_BIT)
+#define G_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \
+    (((x) >> S_CPL_ROCE_CQE_FW_GENERATION_BIT) & \
+     M_CPL_ROCE_CQE_FW_GENERATION_BIT)
+#define F_CPL_ROCE_CQE_FW_GENERATION_BIT V_CPL_ROCE_CQE_FW_GENERATION_BIT(1U)
+
+#define S_CPL_ROCE_CQE_FW_STATUS	5
+#define M_CPL_ROCE_CQE_FW_STATUS	0x1f
+#define V_CPL_ROCE_CQE_FW_STATUS(x)	((x) << S_CPL_ROCE_CQE_FW_STATUS)
+#define G_CPL_ROCE_CQE_FW_STATUS(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_STATUS) & M_CPL_ROCE_CQE_FW_STATUS)
+
+#define S_CPL_ROCE_CQE_FW_CQE_TYPE	4
+#define M_CPL_ROCE_CQE_FW_CQE_TYPE	0x1
+#define V_CPL_ROCE_CQE_FW_CQE_TYPE(x)	((x) << S_CPL_ROCE_CQE_FW_CQE_TYPE)
+#define G_CPL_ROCE_CQE_FW_CQE_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_CQE_TYPE) & M_CPL_ROCE_CQE_FW_CQE_TYPE)
+#define F_CPL_ROCE_CQE_FW_CQE_TYPE	V_CPL_ROCE_CQE_FW_CQE_TYPE(1U)
+
+#define S_CPL_ROCE_CQE_FW_WR_TYPE	0
+#define M_CPL_ROCE_CQE_FW_WR_TYPE	0xf
+#define V_CPL_ROCE_CQE_FW_WR_TYPE(x)	((x) << S_CPL_ROCE_CQE_FW_WR_TYPE)
+#define G_CPL_ROCE_CQE_FW_WR_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE) & M_CPL_ROCE_CQE_FW_WR_TYPE)
+
+#define S_CPL_ROCE_CQE_FW_SE		31
+#define M_CPL_ROCE_CQE_FW_SE		0x1
+#define V_CPL_ROCE_CQE_FW_SE(x)		((x) << S_CPL_ROCE_CQE_FW_SE)
+#define G_CPL_ROCE_CQE_FW_SE(x)		\
+    (((x) >> S_CPL_ROCE_CQE_FW_SE) & M_CPL_ROCE_CQE_FW_SE)
+#define F_CPL_ROCE_CQE_FW_SE		V_CPL_ROCE_CQE_FW_SE(1U)
+
+#define S_CPL_ROCE_CQE_FW_WR_TYPE_EXT	24
+#define M_CPL_ROCE_CQE_FW_WR_TYPE_EXT	0x7f
+#define V_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \
+    ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE_EXT)
+#define G_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \
+    (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) & M_CPL_ROCE_CQE_FW_WR_TYPE_EXT)
+
+#define S_CPL_ROCE_CQE_FW_SRQ		0
+#define M_CPL_ROCE_CQE_FW_SRQ		0xfff
+#define V_CPL_ROCE_CQE_FW_SRQ(x)	((x) << S_CPL_ROCE_CQE_FW_SRQ)
+#define G_CPL_ROCE_CQE_FW_SRQ(x)	\
+    (((x) >> S_CPL_ROCE_CQE_FW_SRQ) & M_CPL_ROCE_CQE_FW_SRQ)
+
+struct cpl_roce_cqe_err {
+	__be32 op_to_CQID;
+	__be32 Tid_FlitCnt;
+	__be32 QPID_to_WR_type;
+	__be32 Length;
+	__be32 TAG;
+	__be32 MSN;
+	__be32 SE_to_SRQ;
+	__be32 RQE;
+	__be32 ExtInfoMS[2];
+	__be32 ExtInfoLS[2];
+};
+
+#define S_CPL_ROCE_CQE_ERR_OPCODE	24
+#define M_CPL_ROCE_CQE_ERR_OPCODE	0xff
+#define V_CPL_ROCE_CQE_ERR_OPCODE(x)	((x) << S_CPL_ROCE_CQE_ERR_OPCODE)
+#define G_CPL_ROCE_CQE_ERR_OPCODE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_OPCODE) & M_CPL_ROCE_CQE_ERR_OPCODE)
+
+#define S_CPL_ROCE_CQE_ERR_RSSCTRL	16
+#define M_CPL_ROCE_CQE_ERR_RSSCTRL	0xff
+#define V_CPL_ROCE_CQE_ERR_RSSCTRL(x)	((x) << S_CPL_ROCE_CQE_ERR_RSSCTRL)
+#define G_CPL_ROCE_CQE_ERR_RSSCTRL(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_RSSCTRL) & M_CPL_ROCE_CQE_ERR_RSSCTRL)
+
+#define S_CPL_ROCE_CQE_ERR_CQID		0
+#define M_CPL_ROCE_CQE_ERR_CQID		0xffff
+#define V_CPL_ROCE_CQE_ERR_CQID(x)	((x) << S_CPL_ROCE_CQE_ERR_CQID)
+#define G_CPL_ROCE_CQE_ERR_CQID(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_CQID) & M_CPL_ROCE_CQE_ERR_CQID)
+
+#define S_CPL_ROCE_CQE_ERR_TID		8
+#define M_CPL_ROCE_CQE_ERR_TID		0xfffff
+#define V_CPL_ROCE_CQE_ERR_TID(x)	((x) << S_CPL_ROCE_CQE_ERR_TID)
+#define G_CPL_ROCE_CQE_ERR_TID(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_TID) & M_CPL_ROCE_CQE_ERR_TID)
+
+#define S_CPL_ROCE_CQE_ERR_FLITCNT	0
+#define M_CPL_ROCE_CQE_ERR_FLITCNT	0xff
+#define V_CPL_ROCE_CQE_ERR_FLITCNT(x)	((x) << S_CPL_ROCE_CQE_ERR_FLITCNT)
+#define G_CPL_ROCE_CQE_ERR_FLITCNT(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_FLITCNT) & M_CPL_ROCE_CQE_ERR_FLITCNT)
+
+#define S_CPL_ROCE_CQE_ERR_QPID		12
+#define M_CPL_ROCE_CQE_ERR_QPID		0xfffff
+#define V_CPL_ROCE_CQE_ERR_QPID(x)	((x) << S_CPL_ROCE_CQE_ERR_QPID)
+#define G_CPL_ROCE_CQE_ERR_QPID(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_QPID) & M_CPL_ROCE_CQE_ERR_QPID)
+
+#define S_CPL_ROCE_CQE_ERR_EXTMODE	11
+#define M_CPL_ROCE_CQE_ERR_EXTMODE	0x1
+#define V_CPL_ROCE_CQE_ERR_EXTMODE(x)	((x) << S_CPL_ROCE_CQE_ERR_EXTMODE)
+#define G_CPL_ROCE_CQE_ERR_EXTMODE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_EXTMODE) & M_CPL_ROCE_CQE_ERR_EXTMODE)
+#define F_CPL_ROCE_CQE_ERR_EXTMODE	V_CPL_ROCE_CQE_ERR_EXTMODE(1U)
+
+#define S_CPL_ROCE_CQE_ERR_GENERATION_BIT 10
+#define M_CPL_ROCE_CQE_ERR_GENERATION_BIT 0x1
+#define V_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \
+    ((x) << S_CPL_ROCE_CQE_ERR_GENERATION_BIT)
+#define G_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \
+    (((x) >> S_CPL_ROCE_CQE_ERR_GENERATION_BIT) & \
+     M_CPL_ROCE_CQE_ERR_GENERATION_BIT)
+#define F_CPL_ROCE_CQE_ERR_GENERATION_BIT \
+    V_CPL_ROCE_CQE_ERR_GENERATION_BIT(1U)
+
+#define S_CPL_ROCE_CQE_ERR_STATUS	5
+#define M_CPL_ROCE_CQE_ERR_STATUS	0x1f
+#define V_CPL_ROCE_CQE_ERR_STATUS(x)	((x) << S_CPL_ROCE_CQE_ERR_STATUS)
+#define G_CPL_ROCE_CQE_ERR_STATUS(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_STATUS) & M_CPL_ROCE_CQE_ERR_STATUS)
+
+#define S_CPL_ROCE_CQE_ERR_CQE_TYPE	4
+#define M_CPL_ROCE_CQE_ERR_CQE_TYPE	0x1
+#define V_CPL_ROCE_CQE_ERR_CQE_TYPE(x)	((x) << S_CPL_ROCE_CQE_ERR_CQE_TYPE)
+#define G_CPL_ROCE_CQE_ERR_CQE_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_CQE_TYPE) & M_CPL_ROCE_CQE_ERR_CQE_TYPE)
+#define F_CPL_ROCE_CQE_ERR_CQE_TYPE	V_CPL_ROCE_CQE_ERR_CQE_TYPE(1U)
+
+#define S_CPL_ROCE_CQE_ERR_WR_TYPE	0
+#define M_CPL_ROCE_CQE_ERR_WR_TYPE	0xf
+#define V_CPL_ROCE_CQE_ERR_WR_TYPE(x)	((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE)
+#define G_CPL_ROCE_CQE_ERR_WR_TYPE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE) & M_CPL_ROCE_CQE_ERR_WR_TYPE)
+
+#define S_CPL_ROCE_CQE_ERR_SE		31
+#define M_CPL_ROCE_CQE_ERR_SE		0x1
+#define V_CPL_ROCE_CQE_ERR_SE(x)	((x) << S_CPL_ROCE_CQE_ERR_SE)
+#define G_CPL_ROCE_CQE_ERR_SE(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_SE) & M_CPL_ROCE_CQE_ERR_SE)
+#define F_CPL_ROCE_CQE_ERR_SE		V_CPL_ROCE_CQE_ERR_SE(1U)
+
+#define S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT	24
+#define M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT	0x7f
+#define V_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \
+    ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT)
+#define G_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \
+    (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) & M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT)
+
+#define S_CPL_ROCE_CQE_ERR_SRQ		0
+#define M_CPL_ROCE_CQE_ERR_SRQ		0xfff
+#define V_CPL_ROCE_CQE_ERR_SRQ(x)	((x) << S_CPL_ROCE_CQE_ERR_SRQ)
+#define G_CPL_ROCE_CQE_ERR_SRQ(x)	\
+    (((x) >> S_CPL_ROCE_CQE_ERR_SRQ) & M_CPL_ROCE_CQE_ERR_SRQ)
+
+struct cpl_accelerator_hdr {
+	__be16 op_accelerator_id;
+	__be16 rxchid_payload_to_inner_cpl_length_ack;
+	__be32 inner_cpl_length_payload_status_loc;
+};
+
+#define S_CPL_ACCELERATOR_HDR_OPCODE	8
+#define M_CPL_ACCELERATOR_HDR_OPCODE	0xff
+#define V_CPL_ACCELERATOR_HDR_OPCODE(x)	((x) << S_CPL_ACCELERATOR_HDR_OPCODE)
+#define G_CPL_ACCELERATOR_HDR_OPCODE(x)	\
+    (((x) >> S_CPL_ACCELERATOR_HDR_OPCODE) & M_CPL_ACCELERATOR_HDR_OPCODE)
+
+#define S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID 0
+#define M_CPL_ACCELERATOR_HDR_ACCELERATOR_ID 0xff
+#define V_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID)
+#define G_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) & \
+     M_CPL_ACCELERATOR_HDR_ACCELERATOR_ID)
+
+#define S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD 14
+#define M_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD 0x3
+#define V_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD)
+#define G_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) & \
+     M_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD)
+
+#define S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD 12
+#define M_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD 0x3
+#define V_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD)
+#define G_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) & \
+     M_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD)
+
+#define S_CPL_ACCELERATOR_HDR_RXCHID_ACK 10
+#define M_CPL_ACCELERATOR_HDR_RXCHID_ACK 0x3
+#define V_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_ACK)
+#define G_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_ACK) & \
+     M_CPL_ACCELERATOR_HDR_RXCHID_ACK)
+
+#define S_CPL_ACCELERATOR_HDR_DESTID_ACK 8
+#define M_CPL_ACCELERATOR_HDR_DESTID_ACK 0x3
+#define V_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_DESTID_ACK)
+#define G_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_ACK) & \
+     M_CPL_ACCELERATOR_HDR_DESTID_ACK)
+
+#define S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK 0
+#define M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK 0xff
+#define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK)
+#define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) & \
+     M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK)
+
+#define S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD 24
+#define M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD 0xff
+#define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD)
+#define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) & \
+     M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD)
+
+#define S_CPL_ACCELERATOR_HDR_STATUS_LOC 22
+#define M_CPL_ACCELERATOR_HDR_STATUS_LOC 0x3
+#define V_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \
+    ((x) << S_CPL_ACCELERATOR_HDR_STATUS_LOC)
+#define G_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \
+    (((x) >> S_CPL_ACCELERATOR_HDR_STATUS_LOC) & \
+     M_CPL_ACCELERATOR_HDR_STATUS_LOC)
+
+struct cpl_accelerator_ack {
+	RSS_HDR
+	__be16 op_accelerator_id;
+	__be16 r0;
+	__be32 status;
+	__be64 r1;
+	__be64 r2;
+};
+
+#define S_CPL_ACCELERATOR_ACK_OPCODE	8
+#define M_CPL_ACCELERATOR_ACK_OPCODE	0xff
+#define V_CPL_ACCELERATOR_ACK_OPCODE(x)	((x) << S_CPL_ACCELERATOR_ACK_OPCODE)
+#define G_CPL_ACCELERATOR_ACK_OPCODE(x)	\
+    (((x) >> S_CPL_ACCELERATOR_ACK_OPCODE) & M_CPL_ACCELERATOR_ACK_OPCODE)
+
+#define S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID 0
+#define M_CPL_ACCELERATOR_ACK_ACCELERATOR_ID 0xff
+#define V_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \
+    ((x) << S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID)
+#define G_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \
+    (((x) >> S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) & \
+     M_CPL_ACCELERATOR_ACK_ACCELERATOR_ID)
+
+struct cpl_nvmt_data {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 r0;
+	__be16 length;
+	__be32 seq;
+	__be32 status_pkd;
+};
+
+#define S_CPL_NVMT_DATA_OPCODE		24
+#define M_CPL_NVMT_DATA_OPCODE		0xff
+#define V_CPL_NVMT_DATA_OPCODE(x)	((x) << S_CPL_NVMT_DATA_OPCODE)
+#define G_CPL_NVMT_DATA_OPCODE(x)	\
+    (((x) >> S_CPL_NVMT_DATA_OPCODE) & M_CPL_NVMT_DATA_OPCODE)
+
+#define S_CPL_NVMT_DATA_TID		0
+#define M_CPL_NVMT_DATA_TID		0xffffff
+#define V_CPL_NVMT_DATA_TID(x)		((x) << S_CPL_NVMT_DATA_TID)
+#define G_CPL_NVMT_DATA_TID(x)		\
+    (((x) >> S_CPL_NVMT_DATA_TID) & M_CPL_NVMT_DATA_TID)
+
+#define S_CPL_NVMT_DATA_STATUS		0
+#define M_CPL_NVMT_DATA_STATUS		0xff
+#define V_CPL_NVMT_DATA_STATUS(x)	((x) << S_CPL_NVMT_DATA_STATUS)
+#define G_CPL_NVMT_DATA_STATUS(x)	\
+    (((x) >> S_CPL_NVMT_DATA_STATUS) & M_CPL_NVMT_DATA_STATUS)
+
+struct cpl_nvmt_cmp {
+	RSS_HDR
+	union opcode_tid ot;
+	__be16 crch;
+	__be16 length;
+	__be32 seq;
+	__u8   t10status;
+	__u8   status;
+	__be16 crcl;
+};
+
+#define S_CPL_NVMT_CMP_OPCODE		24
+#define M_CPL_NVMT_CMP_OPCODE		0xff
+#define V_CPL_NVMT_CMP_OPCODE(x)	((x) << S_CPL_NVMT_CMP_OPCODE)
+#define G_CPL_NVMT_CMP_OPCODE(x)	\
+    (((x) >> S_CPL_NVMT_CMP_OPCODE) & M_CPL_NVMT_CMP_OPCODE)
+
+#define S_CPL_NVMT_CMP_TID		0
+#define M_CPL_NVMT_CMP_TID		0xffffff
+#define V_CPL_NVMT_CMP_TID(x)		((x) << S_CPL_NVMT_CMP_TID)
+#define G_CPL_NVMT_CMP_TID(x)		\
+    (((x) >> S_CPL_NVMT_CMP_TID) & M_CPL_NVMT_CMP_TID)
+
+struct cpl_nvmt_cmp_imm {
+	__be32 op_to_cqid;
+	__be32 generation_bit_to_oprqinc;
+	__be32 seq;
+	__be16 crch;
+	__be16 length;
+	__be16 crcl;
+	__u8   t10status;
+	__u8   status;
+	__be32 r1;
+};
+
+#define S_CPL_NVMT_CMP_IMM_OPCODE	24
+#define M_CPL_NVMT_CMP_IMM_OPCODE	0xff
+#define V_CPL_NVMT_CMP_IMM_OPCODE(x)	((x) << S_CPL_NVMT_CMP_IMM_OPCODE)
+#define G_CPL_NVMT_CMP_IMM_OPCODE(x)	\
+    (((x) >> S_CPL_NVMT_CMP_IMM_OPCODE) & M_CPL_NVMT_CMP_IMM_OPCODE)
+
+#define S_CPL_NVMT_CMP_IMM_RSSCTRL	16
+#define M_CPL_NVMT_CMP_IMM_RSSCTRL	0xff
+#define V_CPL_NVMT_CMP_IMM_RSSCTRL(x)	((x) << S_CPL_NVMT_CMP_IMM_RSSCTRL)
+#define G_CPL_NVMT_CMP_IMM_RSSCTRL(x)	\
+    (((x) >> S_CPL_NVMT_CMP_IMM_RSSCTRL) & M_CPL_NVMT_CMP_IMM_RSSCTRL)
+
+#define S_CPL_NVMT_CMP_IMM_CQID		0
+#define M_CPL_NVMT_CMP_IMM_CQID		0xffff
+#define V_CPL_NVMT_CMP_IMM_CQID(x)	((x) << S_CPL_NVMT_CMP_IMM_CQID)
+#define G_CPL_NVMT_CMP_IMM_CQID(x)	\
+    (((x) >> S_CPL_NVMT_CMP_IMM_CQID) & M_CPL_NVMT_CMP_IMM_CQID)
+
+#define S_CPL_NVMT_CMP_IMM_GENERATION_BIT 31
+#define M_CPL_NVMT_CMP_IMM_GENERATION_BIT 0x1
+#define V_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \
+    ((x) << S_CPL_NVMT_CMP_IMM_GENERATION_BIT)
+#define G_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \
+    (((x) >> S_CPL_NVMT_CMP_IMM_GENERATION_BIT) & \
+     M_CPL_NVMT_CMP_IMM_GENERATION_BIT)
+#define F_CPL_NVMT_CMP_IMM_GENERATION_BIT \
+    V_CPL_NVMT_CMP_IMM_GENERATION_BIT(1U)
+
+#define S_CPL_NVMT_CMP_IMM_TID		8
+#define M_CPL_NVMT_CMP_IMM_TID		0xfffff
+#define V_CPL_NVMT_CMP_IMM_TID(x)	((x) << S_CPL_NVMT_CMP_IMM_TID)
+#define G_CPL_NVMT_CMP_IMM_TID(x)	\
+    (((x) >> S_CPL_NVMT_CMP_IMM_TID) & M_CPL_NVMT_CMP_IMM_TID)
+
+#define S_CPL_NVMT_CMP_IMM_OPRQINC	0
+#define M_CPL_NVMT_CMP_IMM_OPRQINC	0xff
+#define V_CPL_NVMT_CMP_IMM_OPRQINC(x)	((x) << S_CPL_NVMT_CMP_IMM_OPRQINC)
+#define G_CPL_NVMT_CMP_IMM_OPRQINC(x)	\
+    (((x) >> S_CPL_NVMT_CMP_IMM_OPRQINC) & M_CPL_NVMT_CMP_IMM_OPRQINC)
+
+struct cpl_nvmt_cmp_srq {
+	__be32 op_to_cqid;
+	__be32 generation_bit_to_oprqinc;
+	__be32 seq;
+	__be16 crch;
+	__be16 length;
+	__be16 crcl;
+	__u8   t10status;
+	__u8   status;
+	__be32 rqe;
+};
+
+#define S_CPL_NVMT_CMP_SRQ_OPCODE	24
+#define M_CPL_NVMT_CMP_SRQ_OPCODE	0xff
+#define V_CPL_NVMT_CMP_SRQ_OPCODE(x)	((x) << S_CPL_NVMT_CMP_SRQ_OPCODE)
+#define G_CPL_NVMT_CMP_SRQ_OPCODE(x)	\
+    (((x) >> S_CPL_NVMT_CMP_SRQ_OPCODE) & M_CPL_NVMT_CMP_SRQ_OPCODE)
+
+#define S_CPL_NVMT_CMP_SRQ_RSSCTRL	16
+#define M_CPL_NVMT_CMP_SRQ_RSSCTRL	0xff
+#define V_CPL_NVMT_CMP_SRQ_RSSCTRL(x)	((x) << S_CPL_NVMT_CMP_SRQ_RSSCTRL)
+#define G_CPL_NVMT_CMP_SRQ_RSSCTRL(x)	\
+    (((x) >> S_CPL_NVMT_CMP_SRQ_RSSCTRL) & M_CPL_NVMT_CMP_SRQ_RSSCTRL)
+
+#define S_CPL_NVMT_CMP_SRQ_CQID		0
+#define M_CPL_NVMT_CMP_SRQ_CQID		0xffff
+#define V_CPL_NVMT_CMP_SRQ_CQID(x)	((x) << S_CPL_NVMT_CMP_SRQ_CQID)
+#define G_CPL_NVMT_CMP_SRQ_CQID(x)	\
+    (((x) >> S_CPL_NVMT_CMP_SRQ_CQID) & M_CPL_NVMT_CMP_SRQ_CQID)
+
+#define S_CPL_NVMT_CMP_SRQ_GENERATION_BIT 31
+#define M_CPL_NVMT_CMP_SRQ_GENERATION_BIT 0x1
+#define V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \
+    ((x) << S_CPL_NVMT_CMP_SRQ_GENERATION_BIT)
+#define G_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \
+    (((x) >> S_CPL_NVMT_CMP_SRQ_GENERATION_BIT) & \
+     M_CPL_NVMT_CMP_SRQ_GENERATION_BIT)
+#define F_CPL_NVMT_CMP_SRQ_GENERATION_BIT \
+    V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(1U)
+
+#define S_CPL_NVMT_CMP_SRQ_TID		8
+#define M_CPL_NVMT_CMP_SRQ_TID		0xfffff
+#define V_CPL_NVMT_CMP_SRQ_TID(x)	((x) << S_CPL_NVMT_CMP_SRQ_TID)
+#define G_CPL_NVMT_CMP_SRQ_TID(x)	\
+    (((x) >> S_CPL_NVMT_CMP_SRQ_TID) & M_CPL_NVMT_CMP_SRQ_TID)
+
+#define S_CPL_NVMT_CMP_SRQ_OPRQINC	0
+#define M_CPL_NVMT_CMP_SRQ_OPRQINC	0xff
+#define V_CPL_NVMT_CMP_SRQ_OPRQINC(x)	((x) << S_CPL_NVMT_CMP_SRQ_OPRQINC)
+#define G_CPL_NVMT_CMP_SRQ_OPRQINC(x)	\
+    (((x) >> S_CPL_NVMT_CMP_SRQ_OPRQINC) & M_CPL_NVMT_CMP_SRQ_OPRQINC)
+
 #endif  /* T4_MSG_H */
diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h
index e3b2a29b2ea9..8f500ec0fbdd 100644
--- a/sys/dev/cxgbe/common/t4_regs.h
+++ b/sys/dev/cxgbe/common/t4_regs.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2013, 2016 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2013, 2016, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -28,10 +27,11 @@
  */
 
 /* This file is automatically generated --- changes will be lost */
-/* Generation Date : Wed Jan 27 10:57:51 IST 2016 */
-/* Directory name: t4_reg.txt, Changeset:  */
-/* Directory name: t5_reg.txt, Changeset: 6936:7f6342b03d61 */
-/* Directory name: t6_reg.txt, Changeset: 4191:ce3ccd95c109 */
+/* Generation Date : Thu Sep 11 05:25:56 PM IST 2025 */
+/* Directory name: t4_reg.txt, Date: Not specified */
+/* Directory name: t5_reg.txt, Changeset: 6945:54ba4ba7ee8b */
+/* Directory name: t6_reg.txt, Changeset: 4277:9c165d0f4899 */
+/* Directory name: t7_reg.txt, Changeset: 5945:1487219ecb20 */
 
 #define MYPF_BASE 0x1b000
 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
@@ -285,9 +285,6 @@
 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
 
-#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
-#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
-
 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
 #define NUM_PCIE_PF_INT_INSTANCES 8
 
@@ -459,9 +456,6 @@
 #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
 #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
 
-#define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
-#define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11
-
 #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
 
@@ -501,12 +495,175 @@
 #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
 
+#define T7_MYPORT_BASE 0x2e000
+#define T7_MYPORT_REG(reg_addr) (T7_MYPORT_BASE + (reg_addr))
+
+#define T7_PORT0_BASE 0x30000
+#define T7_PORT0_REG(reg_addr) (T7_PORT0_BASE + (reg_addr))
+
+#define T7_PORT1_BASE 0x32000
+#define T7_PORT1_REG(reg_addr) (T7_PORT1_BASE + (reg_addr))
+
+#define T7_PORT2_BASE 0x34000
+#define T7_PORT2_REG(reg_addr) (T7_PORT2_BASE + (reg_addr))
+
+#define T7_PORT3_BASE 0x36000
+#define T7_PORT3_REG(reg_addr) (T7_PORT3_BASE + (reg_addr))
+
+#define T7_PORT_STRIDE 0x2000
+#define T7_PORT_BASE(idx) (T7_PORT0_BASE + (idx) * T7_PORT_STRIDE)
+#define T7_PORT_REG(idx, reg) (T7_PORT_BASE(idx) + (reg))
+
+#define PCIE_MEM_ACCESS_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_MEM_ACCESS_T7_INSTANCES 16
+
+#define PCIE_T7_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T7_CMD_INSTANCES 1
+
+#define PCIE_T5_ARM_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_ARM_INSTANCES 1
+
+#define PCIE_JBOF_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_JBOF_INSTANCES 16
+
+#define PCIE_EMUADRRMAP_REG(reg_addr, idx) ((reg_addr) + (idx) * 32)
+#define NUM_PCIE_EMUADRRMAP_INSTANCES 3
+
+#define CIM_GFT_MASK(idx) (A_CIM_GFT_MASK + (idx) * 4)
+#define NUM_CIM_GFT_MASK_INSTANCES 4
+
+#define T7_MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_T7_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
+#define NUM_T7_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 8
+
+#define T7_MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_T7_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
+#define NUM_T7_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 8
+
+#define T7_MPS_TRC_FILTER_RUNT_CTL(idx) (A_T7_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
+#define NUM_T7_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 8
+
+#define T7_MPS_TRC_FILTER_DROP(idx) (A_T7_MPS_TRC_FILTER_DROP + (idx) * 4)
+#define NUM_T7_MPS_TRC_FILTER_DROP_INSTANCES 8
+
+#define MPS_TRC_FILTER4_MATCH(idx) (A_MPS_TRC_FILTER4_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER4_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER4_DONT_CARE(idx) (A_MPS_TRC_FILTER4_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER4_DONT_CARE_INSTANCES 28
+
+#define MPS_TRC_FILTER5_MATCH(idx) (A_MPS_TRC_FILTER5_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER5_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER5_DONT_CARE(idx) (A_MPS_TRC_FILTER5_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER5_DONT_CARE_INSTANCES 28
+
+#define MPS_TRC_FILTER6_MATCH(idx) (A_MPS_TRC_FILTER6_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER6_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER6_DONT_CARE(idx) (A_MPS_TRC_FILTER6_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER6_DONT_CARE_INSTANCES 28
+
+#define MPS_TRC_FILTER7_MATCH(idx) (A_MPS_TRC_FILTER7_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER7_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER7_DONT_CARE(idx) (A_MPS_TRC_FILTER7_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER7_DONT_CARE_INSTANCES 28
+
+#define LE_DB_DBGI_REQ_DATA_T7(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_DATA_T7_INSTANCES 13
+
+#define LE_DB_DBGI_REQ_MASK_T7(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_MASK_T7_INSTANCES 13
+
+#define LE_DB_ACTIVE_MASK_IPV6_T7(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
+#define NUM_LE_DB_ACTIVE_MASK_IPV6_T7_INSTANCES 8
+
+#define LE_HASH_MASK_GEN_IPV4T7(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV4T7_INSTANCES 8
+
+#define T7_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T7_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
+#define NUM_T7_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
+
+#define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T7(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T7_INSTANCES 8
+
+#define TLS_TX_CH_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
+#define NUM_TLS_TX_CH_INSTANCES 6
+
+#define TLS_TX_CH_IND_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
+#define NUM_TLS_TX_CH_IND_INSTANCES 6
+
+#define ARM_CPU_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_ARM_CPU_INSTANCES 4
+
+#define ARM_CCIM_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_ARM_CCIM_INSTANCES 4
+
+#define ARM_CCIS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_ARM_CCIS_INSTANCES 5
+
+#define ARM_CCI_EVNTBUS(idx) (A_ARM_CCI_EVNTBUS + (idx) * 4)
+#define NUM_ARM_CCI_EVNTBUS_INSTANCES 5
+
+#define ARM_ARM_CFG1(idx) (A_ARM_ARM_CFG1 + (idx) * 4)
+#define NUM_ARM_ARM_CFG1_INSTANCES 2
+
+#define ARM_ARM_CFG2(idx) (A_ARM_ARM_CFG2 + (idx) * 4)
+#define NUM_ARM_ARM_CFG2_INSTANCES 2
+
+#define ARM_MSG_REG(reg_addr, idx) ((reg_addr) + (idx) * 48)
+#define NUM_ARM_MSG_INSTANCES 4
+
+#define ARM_MSG_PCIE_MESSAGE2AXI_CFG4(idx) (A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 + (idx) * 4)
+#define NUM_ARM_MSG_PCIE_MESSAGE2AXI_CFG4_INSTANCES 2
+
+#define MC_CE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_ERR_DATA_T7_INSTANCES 16
+
+#define MC_UE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_ERR_DATA_T7_INSTANCES 16
+
+#define MC_P_BIST_USER_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_P_BIST_USER_INSTANCES 36
+
+#define HMA_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_HMA_H_BIST_STATUS_INSTANCES 18
+
+#define GCACHE_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_GCACHE_P_BIST_STATUS_INSTANCES 18
+
+#define CIM_CTL_MAILBOX_VF_STATUS_T7(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VF_STATUS_T7_INSTANCES 8
+
+#define CIM_CTL_MAILBOX_VFN_CTL_T7(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VFN_CTL_T7_INSTANCES 256
+
+#define CIM_CTL_TID_MAP_EN(idx) (A_CIM_CTL_TID_MAP_EN + (idx) * 4)
+#define NUM_CIM_CTL_TID_MAP_EN_INSTANCES 8
+
+#define CIM_CTL_TID_MAP_CORE(idx) (A_CIM_CTL_TID_MAP_CORE + (idx) * 4)
+#define NUM_CIM_CTL_TID_MAP_CORE_INSTANCES 8
+
+#define CIM_CTL_CRYPTO_KEY_DATA(idx) (A_CIM_CTL_CRYPTO_KEY_DATA + (idx) * 4)
+#define NUM_CIM_CTL_CRYPTO_KEY_DATA_INSTANCES 17
+
+#define CIM_CTL_FLOWID_OP_VALID(idx) (A_CIM_CTL_FLOWID_OP_VALID + (idx) * 4)
+#define NUM_CIM_CTL_FLOWID_OP_VALID_INSTANCES 8
+
+#define CIM_CTL_SLV_REG(reg_addr, idx) ((reg_addr) + (idx) * 1024)
+#define NUM_CIM_CTL_SLV_INSTANCES 7
+
 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
 
 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
 
+#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
+#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
+
+#define MC_T7_STRIDE (MC_T71_BASE_ADDR - MC_T70_BASE_ADDR)
+#define MC_T7_REG(reg, idx) (reg + MC_T7_STRIDE * idx)
+
 /* registers for module SGE */
 #define SGE_BASE_ADDR 0x1000
 
@@ -637,6 +794,24 @@
 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
 
+#define S_NUMOFFID    19
+#define M_NUMOFFID    0x7U
+#define V_NUMOFFID(x) ((x) << S_NUMOFFID)
+#define G_NUMOFFID(x) (((x) >> S_NUMOFFID) & M_NUMOFFID)
+
+#define S_INGHINTENABLE2    16
+#define V_INGHINTENABLE2(x) ((x) << S_INGHINTENABLE2)
+#define F_INGHINTENABLE2    V_INGHINTENABLE2(1U)
+
+#define S_INGHINTENABLE3    3
+#define V_INGHINTENABLE3(x) ((x) << S_INGHINTENABLE3)
+#define F_INGHINTENABLE3    V_INGHINTENABLE3(1U)
+
+#define S_TF_MODE    1
+#define M_TF_MODE    0x3U
+#define V_TF_MODE(x) ((x) << S_TF_MODE)
+#define G_TF_MODE(x) (((x) >> S_TF_MODE) & M_TF_MODE)
+
 #define A_SGE_HOST_PAGE_SIZE 0x100c
 
 #define S_HOSTPAGESIZEPF7    28
@@ -792,6 +967,16 @@
 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
 
+#define S_WR_SENDPATH_ERROR_OPCODE    16
+#define M_WR_SENDPATH_ERROR_OPCODE    0xffU
+#define V_WR_SENDPATH_ERROR_OPCODE(x) ((x) << S_WR_SENDPATH_ERROR_OPCODE)
+#define G_WR_SENDPATH_ERROR_OPCODE(x) (((x) >> S_WR_SENDPATH_ERROR_OPCODE) & M_WR_SENDPATH_ERROR_OPCODE)
+
+#define S_WR_SENDPATH_OPCODE    8
+#define M_WR_SENDPATH_OPCODE    0xffU
+#define V_WR_SENDPATH_OPCODE(x) ((x) << S_WR_SENDPATH_OPCODE)
+#define G_WR_SENDPATH_OPCODE(x) (((x) >> S_WR_SENDPATH_OPCODE) & M_WR_SENDPATH_OPCODE)
+
 #define A_SGE_PERR_INJECT 0x1020
 
 #define S_MEMSEL    1
@@ -941,6 +1126,22 @@
 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
 #define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
 
+#define S_PERR_HEADERSPLIT_FIFO3    28
+#define V_PERR_HEADERSPLIT_FIFO3(x) ((x) << S_PERR_HEADERSPLIT_FIFO3)
+#define F_PERR_HEADERSPLIT_FIFO3    V_PERR_HEADERSPLIT_FIFO3(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO2    27
+#define V_PERR_HEADERSPLIT_FIFO2(x) ((x) << S_PERR_HEADERSPLIT_FIFO2)
+#define F_PERR_HEADERSPLIT_FIFO2    V_PERR_HEADERSPLIT_FIFO2(1U)
+
+#define S_PERR_PAYLOAD_FIFO3    26
+#define V_PERR_PAYLOAD_FIFO3(x) ((x) << S_PERR_PAYLOAD_FIFO3)
+#define F_PERR_PAYLOAD_FIFO3    V_PERR_PAYLOAD_FIFO3(1U)
+
+#define S_PERR_PAYLOAD_FIFO2    25
+#define V_PERR_PAYLOAD_FIFO2(x) ((x) << S_PERR_PAYLOAD_FIFO2)
+#define F_PERR_PAYLOAD_FIFO2    V_PERR_PAYLOAD_FIFO2(1U)
+
 #define A_SGE_INT_ENABLE1 0x1028
 #define A_SGE_PERR_ENABLE1 0x102c
 #define A_SGE_INT_CAUSE2 0x1030
@@ -1105,6 +1306,22 @@
 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
 #define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
 
+#define S_TF_FIFO_PERR    24
+#define V_TF_FIFO_PERR(x) ((x) << S_TF_FIFO_PERR)
+#define F_TF_FIFO_PERR    V_TF_FIFO_PERR(1U)
+
+#define S_PERR_ISW_IDMA3_FIFO    15
+#define V_PERR_ISW_IDMA3_FIFO(x) ((x) << S_PERR_ISW_IDMA3_FIFO)
+#define F_PERR_ISW_IDMA3_FIFO    V_PERR_ISW_IDMA3_FIFO(1U)
+
+#define S_PERR_ISW_IDMA2_FIFO    13
+#define V_PERR_ISW_IDMA2_FIFO(x) ((x) << S_PERR_ISW_IDMA2_FIFO)
+#define F_PERR_ISW_IDMA2_FIFO    V_PERR_ISW_IDMA2_FIFO(1U)
+
+#define S_SGE_IPP_FIFO_PERR    5
+#define V_SGE_IPP_FIFO_PERR(x) ((x) << S_SGE_IPP_FIFO_PERR)
+#define F_SGE_IPP_FIFO_PERR    V_SGE_IPP_FIFO_PERR(1U)
+
 #define A_SGE_INT_ENABLE2 0x1034
 #define A_SGE_PERR_ENABLE2 0x1038
 #define A_SGE_INT_CAUSE3 0x103c
@@ -1259,110 +1476,20 @@
 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
 
 #define A_SGE_FL_BUFFER_SIZE1 0x1048
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE2 0x104c
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE3 0x1050
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE4 0x1054
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE5 0x1058
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE6 0x105c
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE7 0x1060
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE8 0x1064
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE9 0x1068
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE10 0x106c
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE11 0x1070
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE12 0x1074
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE13 0x1078
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE14 0x107c
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_FL_BUFFER_SIZE15 0x1080
-
-#define S_T6_SIZE    4
-#define M_T6_SIZE    0xfffffU
-#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
-#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
-
 #define A_SGE_DBQ_CTXT_BADDR 0x1084
 
 #define S_BASEADDR    3
@@ -1426,6 +1553,10 @@
 #define V_NULLPTREN(x) ((x) << S_NULLPTREN)
 #define F_NULLPTREN    V_NULLPTREN(1U)
 
+#define S_HDRSTARTFLQ4K    1
+#define V_HDRSTARTFLQ4K(x) ((x) << S_HDRSTARTFLQ4K)
+#define F_HDRSTARTFLQ4K    V_HDRSTARTFLQ4K(1U)
+
 #define A_SGE_CONM_CTRL 0x1094
 
 #define S_EGRTHRESHOLD    8
@@ -2243,6 +2374,34 @@
 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
 
+#define S_PERR_POINTER_HDR_FIFO3    10
+#define V_PERR_POINTER_HDR_FIFO3(x) ((x) << S_PERR_POINTER_HDR_FIFO3)
+#define F_PERR_POINTER_HDR_FIFO3    V_PERR_POINTER_HDR_FIFO3(1U)
+
+#define S_PERR_POINTER_HDR_FIFO2    9
+#define V_PERR_POINTER_HDR_FIFO2(x) ((x) << S_PERR_POINTER_HDR_FIFO2)
+#define F_PERR_POINTER_HDR_FIFO2    V_PERR_POINTER_HDR_FIFO2(1U)
+
+#define S_PERR_POINTER_DATA_FIFO3    8
+#define V_PERR_POINTER_DATA_FIFO3(x) ((x) << S_PERR_POINTER_DATA_FIFO3)
+#define F_PERR_POINTER_DATA_FIFO3    V_PERR_POINTER_DATA_FIFO3(1U)
+
+#define S_PERR_POINTER_DATA_FIFO2    7
+#define V_PERR_POINTER_DATA_FIFO2(x) ((x) << S_PERR_POINTER_DATA_FIFO2)
+#define F_PERR_POINTER_DATA_FIFO2    V_PERR_POINTER_DATA_FIFO2(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO3    3
+#define V_PERR_IDMA2IMSG_FIFO3(x) ((x) << S_PERR_IDMA2IMSG_FIFO3)
+#define F_PERR_IDMA2IMSG_FIFO3    V_PERR_IDMA2IMSG_FIFO3(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO2    2
+#define V_PERR_IDMA2IMSG_FIFO2(x) ((x) << S_PERR_IDMA2IMSG_FIFO2)
+#define F_PERR_IDMA2IMSG_FIFO2    V_PERR_IDMA2IMSG_FIFO2(1U)
+
+#define S_PERR_HINT_DELAY_FIFO    0
+#define V_PERR_HINT_DELAY_FIFO(x) ((x) << S_PERR_HINT_DELAY_FIFO)
+#define F_PERR_HINT_DELAY_FIFO    V_PERR_HINT_DELAY_FIFO(1U)
+
 #define A_SGE_INT_ENABLE5 0x1110
 #define A_SGE_PERR_ENABLE5 0x1114
 #define A_SGE_DBFIFO_STATUS2 0x1118
@@ -2359,6 +2518,46 @@
 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
 #define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
 
+#define S_HINT_SGE_SEL    31
+#define V_HINT_SGE_SEL(x) ((x) << S_HINT_SGE_SEL)
+#define F_HINT_SGE_SEL    V_HINT_SGE_SEL(1U)
+
+#define S_HINT_SEL    30
+#define V_HINT_SEL(x) ((x) << S_HINT_SEL)
+#define F_HINT_SEL    V_HINT_SEL(1U)
+
+#define S_HINT_DISABLE    29
+#define V_HINT_DISABLE(x) ((x) << S_HINT_DISABLE)
+#define F_HINT_DISABLE    V_HINT_DISABLE(1U)
+
+#define S_RXCPLMODE_ISCSI    28
+#define V_RXCPLMODE_ISCSI(x) ((x) << S_RXCPLMODE_ISCSI)
+#define F_RXCPLMODE_ISCSI    V_RXCPLMODE_ISCSI(1U)
+
+#define S_RXCPLMODE_NVMT    27
+#define V_RXCPLMODE_NVMT(x) ((x) << S_RXCPLMODE_NVMT)
+#define F_RXCPLMODE_NVMT    V_RXCPLMODE_NVMT(1U)
+
+#define S_WRE_REPLAY_INORDER    26
+#define V_WRE_REPLAY_INORDER(x) ((x) << S_WRE_REPLAY_INORDER)
+#define F_WRE_REPLAY_INORDER    V_WRE_REPLAY_INORDER(1U)
+
+#define S_ETH2XEN    25
+#define V_ETH2XEN(x) ((x) << S_ETH2XEN)
+#define F_ETH2XEN    V_ETH2XEN(1U)
+
+#define S_ARMDBENDDIS    24
+#define V_ARMDBENDDIS(x) ((x) << S_ARMDBENDDIS)
+#define F_ARMDBENDDIS    V_ARMDBENDDIS(1U)
+
+#define S_PACKPADT7    23
+#define V_PACKPADT7(x) ((x) << S_PACKPADT7)
+#define F_PACKPADT7    V_PACKPADT7(1U)
+
+#define S_WRE_UPFLCREDIT    22
+#define V_WRE_UPFLCREDIT(x) ((x) << S_WRE_UPFLCREDIT)
+#define F_WRE_UPFLCREDIT    V_WRE_UPFLCREDIT(1U)
+
 #define A_SGE_DEEP_SLEEP 0x1128
 
 #define S_IDMA1_SLEEP_STATUS    11
@@ -2493,6 +2692,42 @@
 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
 #define F_FATAL_DEQ    V_FATAL_DEQ(1U)
 
+#define S_FATAL_DEQ0_DRDY    29
+#define M_FATAL_DEQ0_DRDY    0x7U
+#define V_FATAL_DEQ0_DRDY(x) ((x) << S_FATAL_DEQ0_DRDY)
+#define G_FATAL_DEQ0_DRDY(x) (((x) >> S_FATAL_DEQ0_DRDY) & M_FATAL_DEQ0_DRDY)
+
+#define S_FATAL_OUT0_DRDY    26
+#define M_FATAL_OUT0_DRDY    0x7U
+#define V_FATAL_OUT0_DRDY(x) ((x) << S_FATAL_OUT0_DRDY)
+#define G_FATAL_OUT0_DRDY(x) (((x) >> S_FATAL_OUT0_DRDY) & M_FATAL_OUT0_DRDY)
+
+#define S_IMSG_DBG3_STUCK    25
+#define V_IMSG_DBG3_STUCK(x) ((x) << S_IMSG_DBG3_STUCK)
+#define F_IMSG_DBG3_STUCK    V_IMSG_DBG3_STUCK(1U)
+
+#define S_IMSG_DBG2_STUCK    24
+#define V_IMSG_DBG2_STUCK(x) ((x) << S_IMSG_DBG2_STUCK)
+#define F_IMSG_DBG2_STUCK    V_IMSG_DBG2_STUCK(1U)
+
+#define S_IMSG_DBG1_STUCK    23
+#define V_IMSG_DBG1_STUCK(x) ((x) << S_IMSG_DBG1_STUCK)
+#define F_IMSG_DBG1_STUCK    V_IMSG_DBG1_STUCK(1U)
+
+#define S_IMSG_DBG0_STUCK    22
+#define V_IMSG_DBG0_STUCK(x) ((x) << S_IMSG_DBG0_STUCK)
+#define F_IMSG_DBG0_STUCK    V_IMSG_DBG0_STUCK(1U)
+
+#define S_FATAL_DEQ1_DRDY    3
+#define M_FATAL_DEQ1_DRDY    0x3U
+#define V_FATAL_DEQ1_DRDY(x) ((x) << S_FATAL_DEQ1_DRDY)
+#define G_FATAL_DEQ1_DRDY(x) (((x) >> S_FATAL_DEQ1_DRDY) & M_FATAL_DEQ1_DRDY)
+
+#define S_FATAL_OUT1_DRDY    1
+#define M_FATAL_OUT1_DRDY    0x3U
+#define V_FATAL_OUT1_DRDY(x) ((x) << S_FATAL_OUT1_DRDY)
+#define G_FATAL_OUT1_DRDY(x) (((x) >> S_FATAL_OUT1_DRDY) & M_FATAL_OUT1_DRDY)
+
 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
 
 #define S_THROTTLE_THRESHOLD_FL    16
@@ -2612,6 +2847,55 @@
 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
 
+#define A_SGE_TBUF_CONTROL0 0x114c
+#define A_SGE_TBUF_CONTROL1 0x1150
+
+#define S_DBPTBUFRSV3    9
+#define M_DBPTBUFRSV3    0x1ffU
+#define V_DBPTBUFRSV3(x) ((x) << S_DBPTBUFRSV3)
+#define G_DBPTBUFRSV3(x) (((x) >> S_DBPTBUFRSV3) & M_DBPTBUFRSV3)
+
+#define S_DBPTBUFRSV2    0
+#define M_DBPTBUFRSV2    0x1ffU
+#define V_DBPTBUFRSV2(x) ((x) << S_DBPTBUFRSV2)
+#define G_DBPTBUFRSV2(x) (((x) >> S_DBPTBUFRSV2) & M_DBPTBUFRSV2)
+
+#define A_SGE_TBUF_CONTROL2 0x1154
+
+#define S_DBPTBUFRSV5    9
+#define M_DBPTBUFRSV5    0x1ffU
+#define V_DBPTBUFRSV5(x) ((x) << S_DBPTBUFRSV5)
+#define G_DBPTBUFRSV5(x) (((x) >> S_DBPTBUFRSV5) & M_DBPTBUFRSV5)
+
+#define S_DBPTBUFRSV4    0
+#define M_DBPTBUFRSV4    0x1ffU
+#define V_DBPTBUFRSV4(x) ((x) << S_DBPTBUFRSV4)
+#define G_DBPTBUFRSV4(x) (((x) >> S_DBPTBUFRSV4) & M_DBPTBUFRSV4)
+
+#define A_SGE_TBUF_CONTROL3 0x1158
+
+#define S_DBPTBUFRSV7    9
+#define M_DBPTBUFRSV7    0x1ffU
+#define V_DBPTBUFRSV7(x) ((x) << S_DBPTBUFRSV7)
+#define G_DBPTBUFRSV7(x) (((x) >> S_DBPTBUFRSV7) & M_DBPTBUFRSV7)
+
+#define S_DBPTBUFRSV6    0
+#define M_DBPTBUFRSV6    0x1ffU
+#define V_DBPTBUFRSV6(x) ((x) << S_DBPTBUFRSV6)
+#define G_DBPTBUFRSV6(x) (((x) >> S_DBPTBUFRSV6) & M_DBPTBUFRSV6)
+
+#define A_SGE_TBUF_CONTROL4 0x115c
+
+#define S_DBPTBUFRSV9    9
+#define M_DBPTBUFRSV9    0x1ffU
+#define V_DBPTBUFRSV9(x) ((x) << S_DBPTBUFRSV9)
+#define G_DBPTBUFRSV9(x) (((x) >> S_DBPTBUFRSV9) & M_DBPTBUFRSV9)
+
+#define S_DBPTBUFRSV8    0
+#define M_DBPTBUFRSV8    0x1ffU
+#define V_DBPTBUFRSV8(x) ((x) << S_DBPTBUFRSV8)
+#define G_DBPTBUFRSV8(x) (((x) >> S_DBPTBUFRSV8) & M_DBPTBUFRSV8)
+
 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
@@ -2620,6 +2904,113 @@
 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
+#define A_SGE_DBQ_TIMER_THRESH0 0x11b8
+
+#define S_TXTIMETH3    24
+#define M_TXTIMETH3    0x3fU
+#define V_TXTIMETH3(x) ((x) << S_TXTIMETH3)
+#define G_TXTIMETH3(x) (((x) >> S_TXTIMETH3) & M_TXTIMETH3)
+
+#define S_TXTIMETH2    16
+#define M_TXTIMETH2    0x3fU
+#define V_TXTIMETH2(x) ((x) << S_TXTIMETH2)
+#define G_TXTIMETH2(x) (((x) >> S_TXTIMETH2) & M_TXTIMETH2)
+
+#define S_TXTIMETH1    8
+#define M_TXTIMETH1    0x3fU
+#define V_TXTIMETH1(x) ((x) << S_TXTIMETH1)
+#define G_TXTIMETH1(x) (((x) >> S_TXTIMETH1) & M_TXTIMETH1)
+
+#define S_TXTIMETH0    0
+#define M_TXTIMETH0    0x3fU
+#define V_TXTIMETH0(x) ((x) << S_TXTIMETH0)
+#define G_TXTIMETH0(x) (((x) >> S_TXTIMETH0) & M_TXTIMETH0)
+
+#define A_SGE_DBQ_TIMER_THRESH1 0x11bc
+
+#define S_TXTIMETH7    24
+#define M_TXTIMETH7    0x3fU
+#define V_TXTIMETH7(x) ((x) << S_TXTIMETH7)
+#define G_TXTIMETH7(x) (((x) >> S_TXTIMETH7) & M_TXTIMETH7)
+
+#define S_TXTIMETH6    16
+#define M_TXTIMETH6    0x3fU
+#define V_TXTIMETH6(x) ((x) << S_TXTIMETH6)
+#define G_TXTIMETH6(x) (((x) >> S_TXTIMETH6) & M_TXTIMETH6)
+
+#define S_TXTIMETH5    8
+#define M_TXTIMETH5    0x3fU
+#define V_TXTIMETH5(x) ((x) << S_TXTIMETH5)
+#define G_TXTIMETH5(x) (((x) >> S_TXTIMETH5) & M_TXTIMETH5)
+
+#define S_TXTIMETH4    0
+#define M_TXTIMETH4    0x3fU
+#define V_TXTIMETH4(x) ((x) << S_TXTIMETH4)
+#define G_TXTIMETH4(x) (((x) >> S_TXTIMETH4) & M_TXTIMETH4)
+
+#define A_SGE_DBQ_TIMER_CONFIG 0x11c0
+
+#define S_DBQ_TIMER_OP    0
+#define M_DBQ_TIMER_OP    0xffU
+#define V_DBQ_TIMER_OP(x) ((x) << S_DBQ_TIMER_OP)
+#define G_DBQ_TIMER_OP(x) (((x) >> S_DBQ_TIMER_OP) & M_DBQ_TIMER_OP)
+
+#define A_SGE_DBQ_TIMER_DBG 0x11c4
+
+#define S_DBQ_TIMER_CMD    31
+#define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD)
+#define F_DBQ_TIMER_CMD    V_DBQ_TIMER_CMD(1U)
+
+#define S_DBQ_TIMER_INDEX    24
+#define M_DBQ_TIMER_INDEX    0x3fU
+#define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX)
+#define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX)
+
+#define S_DBQ_TIMER_QCNT    0
+#define M_DBQ_TIMER_QCNT    0x1ffffU
+#define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT)
+#define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT)
+
+#define A_SGE_INT_CAUSE8 0x11c8
+
+#define S_TRACE_RXPERR    8
+#define V_TRACE_RXPERR(x) ((x) << S_TRACE_RXPERR)
+#define F_TRACE_RXPERR    V_TRACE_RXPERR(1U)
+
+#define S_U3_RXPERR    7
+#define V_U3_RXPERR(x) ((x) << S_U3_RXPERR)
+#define F_U3_RXPERR    V_U3_RXPERR(1U)
+
+#define S_U2_RXPERR    6
+#define V_U2_RXPERR(x) ((x) << S_U2_RXPERR)
+#define F_U2_RXPERR    V_U2_RXPERR(1U)
+
+#define S_U1_RXPERR    5
+#define V_U1_RXPERR(x) ((x) << S_U1_RXPERR)
+#define F_U1_RXPERR    V_U1_RXPERR(1U)
+
+#define S_U0_RXPERR    4
+#define V_U0_RXPERR(x) ((x) << S_U0_RXPERR)
+#define F_U0_RXPERR    V_U0_RXPERR(1U)
+
+#define S_T3_RXPERR    3
+#define V_T3_RXPERR(x) ((x) << S_T3_RXPERR)
+#define F_T3_RXPERR    V_T3_RXPERR(1U)
+
+#define S_T2_RXPERR    2
+#define V_T2_RXPERR(x) ((x) << S_T2_RXPERR)
+#define F_T2_RXPERR    V_T2_RXPERR(1U)
+
+#define S_T1_RXPERR    1
+#define V_T1_RXPERR(x) ((x) << S_T1_RXPERR)
+#define F_T1_RXPERR    V_T1_RXPERR(1U)
+
+#define S_T0_RXPERR    0
+#define V_T0_RXPERR(x) ((x) << S_T0_RXPERR)
+#define F_T0_RXPERR    V_T0_RXPERR(1U)
+
+#define A_SGE_INT_ENABLE8 0x11cc
+#define A_SGE_PERR_ENABLE8 0x11d0
 #define A_SGE_CTXT_CMD 0x11fc
 
 #define S_BUSY    31
@@ -2648,6 +3039,17 @@
 #define A_SGE_CTXT_DATA4 0x1210
 #define A_SGE_CTXT_DATA5 0x1214
 #define A_SGE_CTXT_DATA6 0x1218
+
+#define S_DATA_UNUSED    7
+#define M_DATA_UNUSED    0x1ffffffU
+#define V_DATA_UNUSED(x) ((x) << S_DATA_UNUSED)
+#define G_DATA_UNUSED(x) (((x) >> S_DATA_UNUSED) & M_DATA_UNUSED)
+
+#define S_DATA6    0
+#define M_DATA6    0x7fU
+#define V_DATA6(x) ((x) << S_DATA6)
+#define G_DATA6(x) (((x) >> S_DATA6) & M_DATA6)
+
 #define A_SGE_CTXT_DATA7 0x121c
 #define A_SGE_CTXT_MASK0 0x1220
 #define A_SGE_CTXT_MASK1 0x1224
@@ -2656,6 +3058,17 @@
 #define A_SGE_CTXT_MASK4 0x1230
 #define A_SGE_CTXT_MASK5 0x1234
 #define A_SGE_CTXT_MASK6 0x1238
+
+#define S_MASK_UNUSED    7
+#define M_MASK_UNUSED    0x1ffffffU
+#define V_MASK_UNUSED(x) ((x) << S_MASK_UNUSED)
+#define G_MASK_UNUSED(x) (((x) >> S_MASK_UNUSED) & M_MASK_UNUSED)
+
+#define S_MASK    0
+#define M_MASK    0x7fU
+#define V_MASK(x) ((x) << S_MASK)
+#define G_MASK(x) (((x) >> S_MASK) & M_MASK)
+
 #define A_SGE_CTXT_MASK7 0x123c
 #define A_SGE_QBASE_MAP0 0x1240
 
@@ -2674,6 +3087,10 @@
 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
 
+#define S_DESTINATION    31
+#define V_DESTINATION(x) ((x) << S_DESTINATION)
+#define F_DESTINATION    V_DESTINATION(1U)
+
 #define A_SGE_QBASE_MAP1 0x1244
 
 #define S_EGRESS0_BASE    0
@@ -2719,6 +3136,10 @@
 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
 
+#define S_CONENMIDDLE    7
+#define V_CONENMIDDLE(x) ((x) << S_CONENMIDDLE)
+#define F_CONENMIDDLE    V_CONENMIDDLE(1U)
+
 #define A_SGE_DEBUG_CONM 0x1258
 
 #define S_MPS_CH_CNG    16
@@ -2745,6 +3166,16 @@
 #define V_LAST_QID(x) ((x) << S_LAST_QID)
 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
 
+#define S_CH_CNG    16
+#define M_CH_CNG    0xffffU
+#define V_CH_CNG(x) ((x) << S_CH_CNG)
+#define G_CH_CNG(x) (((x) >> S_CH_CNG) & M_CH_CNG)
+
+#define S_CH_SEL    14
+#define M_CH_SEL    0x3U
+#define V_CH_SEL(x) ((x) << S_CH_SEL)
+#define G_CH_SEL(x) (((x) >> S_CH_SEL) & M_CH_SEL)
+
 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
 
 #define S_IMSG_GTS_SEL    18
@@ -2766,6 +3197,7 @@
 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
 #define A_SGE_DBG_DB_PKT_CNT 0x1270
 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_16 0x1278
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
 
 #define S_CIM_WM    24
@@ -3965,6 +4397,352 @@
 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
 
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_17 0x1340
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_18 0x1344
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_19 0x1348
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_20 0x134c
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_21 0x1350
+#define A_SGE_DEBUG_DATA_LOW_INDEX_16 0x1354
+#define A_SGE_DEBUG_DATA_LOW_INDEX_17 0x1358
+#define A_SGE_DEBUG_DATA_LOW_INDEX_18 0x135c
+#define A_SGE_INT_CAUSE7 0x1360
+
+#define S_HINT_FIFO_FULL    25
+#define V_HINT_FIFO_FULL(x) ((x) << S_HINT_FIFO_FULL)
+#define F_HINT_FIFO_FULL    V_HINT_FIFO_FULL(1U)
+
+#define S_CERR_HINT_DELAY_FIFO    24
+#define V_CERR_HINT_DELAY_FIFO(x) ((x) << S_CERR_HINT_DELAY_FIFO)
+#define F_CERR_HINT_DELAY_FIFO    V_CERR_HINT_DELAY_FIFO(1U)
+
+#define S_COAL_TIMER_FIFO_PERR    23
+#define V_COAL_TIMER_FIFO_PERR(x) ((x) << S_COAL_TIMER_FIFO_PERR)
+#define F_COAL_TIMER_FIFO_PERR    V_COAL_TIMER_FIFO_PERR(1U)
+
+#define S_CMP_FIFO_PERR    22
+#define V_CMP_FIFO_PERR(x) ((x) << S_CMP_FIFO_PERR)
+#define F_CMP_FIFO_PERR    V_CMP_FIFO_PERR(1U)
+
+#define S_SGE_IPP_FIFO_CERR    21
+#define V_SGE_IPP_FIFO_CERR(x) ((x) << S_SGE_IPP_FIFO_CERR)
+#define F_SGE_IPP_FIFO_CERR    V_SGE_IPP_FIFO_CERR(1U)
+
+#define S_CERR_ING_CTXT_CACHE    20
+#define V_CERR_ING_CTXT_CACHE(x) ((x) << S_CERR_ING_CTXT_CACHE)
+#define F_CERR_ING_CTXT_CACHE    V_CERR_ING_CTXT_CACHE(1U)
+
+#define S_IMSG_CNTX_PERR    19
+#define V_IMSG_CNTX_PERR(x) ((x) << S_IMSG_CNTX_PERR)
+#define F_IMSG_CNTX_PERR    V_IMSG_CNTX_PERR(1U)
+
+#define S_PD_FIFO_PERR    18
+#define V_PD_FIFO_PERR(x) ((x) << S_PD_FIFO_PERR)
+#define F_PD_FIFO_PERR    V_PD_FIFO_PERR(1U)
+
+#define S_IMSG_512_FIFO_PERR    17
+#define V_IMSG_512_FIFO_PERR(x) ((x) << S_IMSG_512_FIFO_PERR)
+#define F_IMSG_512_FIFO_PERR    V_IMSG_512_FIFO_PERR(1U)
+
+#define S_CPLSW_FIFO_PERR    16
+#define V_CPLSW_FIFO_PERR(x) ((x) << S_CPLSW_FIFO_PERR)
+#define F_CPLSW_FIFO_PERR    V_CPLSW_FIFO_PERR(1U)
+
+#define S_IMSG_FIFO_PERR    15
+#define V_IMSG_FIFO_PERR(x) ((x) << S_IMSG_FIFO_PERR)
+#define F_IMSG_FIFO_PERR    V_IMSG_FIFO_PERR(1U)
+
+#define S_CERR_ITP_EVR    14
+#define V_CERR_ITP_EVR(x) ((x) << S_CERR_ITP_EVR)
+#define F_CERR_ITP_EVR    V_CERR_ITP_EVR(1U)
+
+#define S_CERR_CONM_SRAM    13
+#define V_CERR_CONM_SRAM(x) ((x) << S_CERR_CONM_SRAM)
+#define F_CERR_CONM_SRAM    V_CERR_CONM_SRAM(1U)
+
+#define S_CERR_EGR_CTXT_CACHE    12
+#define V_CERR_EGR_CTXT_CACHE(x) ((x) << S_CERR_EGR_CTXT_CACHE)
+#define F_CERR_EGR_CTXT_CACHE    V_CERR_EGR_CTXT_CACHE(1U)
+
+#define S_CERR_FLM_CNTXMEM    11
+#define V_CERR_FLM_CNTXMEM(x) ((x) << S_CERR_FLM_CNTXMEM)
+#define F_CERR_FLM_CNTXMEM    V_CERR_FLM_CNTXMEM(1U)
+
+#define S_CERR_FUNC_QBASE    10
+#define V_CERR_FUNC_QBASE(x) ((x) << S_CERR_FUNC_QBASE)
+#define F_CERR_FUNC_QBASE    V_CERR_FUNC_QBASE(1U)
+
+#define S_IMSG_CNTX_CERR    9
+#define V_IMSG_CNTX_CERR(x) ((x) << S_IMSG_CNTX_CERR)
+#define F_IMSG_CNTX_CERR    V_IMSG_CNTX_CERR(1U)
+
+#define S_PD_FIFO_CERR    8
+#define V_PD_FIFO_CERR(x) ((x) << S_PD_FIFO_CERR)
+#define F_PD_FIFO_CERR    V_PD_FIFO_CERR(1U)
+
+#define S_IMSG_512_FIFO_CERR    7
+#define V_IMSG_512_FIFO_CERR(x) ((x) << S_IMSG_512_FIFO_CERR)
+#define F_IMSG_512_FIFO_CERR    V_IMSG_512_FIFO_CERR(1U)
+
+#define S_CPLSW_FIFO_CERR    6
+#define V_CPLSW_FIFO_CERR(x) ((x) << S_CPLSW_FIFO_CERR)
+#define F_CPLSW_FIFO_CERR    V_CPLSW_FIFO_CERR(1U)
+
+#define S_IMSG_FIFO_CERR    5
+#define V_IMSG_FIFO_CERR(x) ((x) << S_IMSG_FIFO_CERR)
+#define F_IMSG_FIFO_CERR    V_IMSG_FIFO_CERR(1U)
+
+#define S_CERR_HEADERSPLIT_FIFO3    4
+#define V_CERR_HEADERSPLIT_FIFO3(x) ((x) << S_CERR_HEADERSPLIT_FIFO3)
+#define F_CERR_HEADERSPLIT_FIFO3    V_CERR_HEADERSPLIT_FIFO3(1U)
+
+#define S_CERR_HEADERSPLIT_FIFO2    3
+#define V_CERR_HEADERSPLIT_FIFO2(x) ((x) << S_CERR_HEADERSPLIT_FIFO2)
+#define F_CERR_HEADERSPLIT_FIFO2    V_CERR_HEADERSPLIT_FIFO2(1U)
+
+#define S_CERR_HEADERSPLIT_FIFO1    2
+#define V_CERR_HEADERSPLIT_FIFO1(x) ((x) << S_CERR_HEADERSPLIT_FIFO1)
+#define F_CERR_HEADERSPLIT_FIFO1    V_CERR_HEADERSPLIT_FIFO1(1U)
+
+#define S_CERR_HEADERSPLIT_FIFO0    1
+#define V_CERR_HEADERSPLIT_FIFO0(x) ((x) << S_CERR_HEADERSPLIT_FIFO0)
+#define F_CERR_HEADERSPLIT_FIFO0    V_CERR_HEADERSPLIT_FIFO0(1U)
+
+#define S_CERR_FLM_L1CACHE    0
+#define V_CERR_FLM_L1CACHE(x) ((x) << S_CERR_FLM_L1CACHE)
+#define F_CERR_FLM_L1CACHE    V_CERR_FLM_L1CACHE(1U)
+
+#define A_SGE_INT_ENABLE7 0x1364
+#define A_SGE_PERR_ENABLE7 0x1368
+#define A_SGE_ING_COMP_COAL_CFG 0x1700
+
+#define S_USE_PTP_TIMER    27
+#define V_USE_PTP_TIMER(x) ((x) << S_USE_PTP_TIMER)
+#define F_USE_PTP_TIMER    V_USE_PTP_TIMER(1U)
+
+#define S_IMSG_SET_OFLOW_ALL_ENTRIES_43060    26
+#define V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(x) ((x) << S_IMSG_SET_OFLOW_ALL_ENTRIES_43060)
+#define F_IMSG_SET_OFLOW_ALL_ENTRIES_43060    V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(1U)
+
+#define S_IMSG_STUCK_INDIRECT_QUEUE_42907    25
+#define V_IMSG_STUCK_INDIRECT_QUEUE_42907(x) ((x) << S_IMSG_STUCK_INDIRECT_QUEUE_42907)
+#define F_IMSG_STUCK_INDIRECT_QUEUE_42907    V_IMSG_STUCK_INDIRECT_QUEUE_42907(1U)
+
+#define S_COMP_COAL_PIDX_INCR    24
+#define V_COMP_COAL_PIDX_INCR(x) ((x) << S_COMP_COAL_PIDX_INCR)
+#define F_COMP_COAL_PIDX_INCR    V_COMP_COAL_PIDX_INCR(1U)
+
+#define S_COMP_COAL_TIMER_CNT    16
+#define M_COMP_COAL_TIMER_CNT    0xffU
+#define V_COMP_COAL_TIMER_CNT(x) ((x) << S_COMP_COAL_TIMER_CNT)
+#define G_COMP_COAL_TIMER_CNT(x) (((x) >> S_COMP_COAL_TIMER_CNT) & M_COMP_COAL_TIMER_CNT)
+
+#define S_COMP_COAL_CNTR_TH    8
+#define M_COMP_COAL_CNTR_TH    0xffU
+#define V_COMP_COAL_CNTR_TH(x) ((x) << S_COMP_COAL_CNTR_TH)
+#define G_COMP_COAL_CNTR_TH(x) (((x) >> S_COMP_COAL_CNTR_TH) & M_COMP_COAL_CNTR_TH)
+
+#define S_COMP_COAL_OPCODE    0
+#define M_COMP_COAL_OPCODE    0xffU
+#define V_COMP_COAL_OPCODE(x) ((x) << S_COMP_COAL_OPCODE)
+#define G_COMP_COAL_OPCODE(x) (((x) >> S_COMP_COAL_OPCODE) & M_COMP_COAL_OPCODE)
+
+#define A_SGE_ING_IMSG_DBG 0x1704
+
+#define S_STUCK_CTR_TH    1
+#define M_STUCK_CTR_TH    0xffU
+#define V_STUCK_CTR_TH(x) ((x) << S_STUCK_CTR_TH)
+#define G_STUCK_CTR_TH(x) (((x) >> S_STUCK_CTR_TH) & M_STUCK_CTR_TH)
+
+#define S_STUCK_INT_EN    0
+#define V_STUCK_INT_EN(x) ((x) << S_STUCK_INT_EN)
+#define F_STUCK_INT_EN    V_STUCK_INT_EN(1U)
+
+#define A_SGE_ING_IMSG_RSP0_DBG 0x1708
+
+#define S_IDMA1_QID    16
+#define M_IDMA1_QID    0xffffU
+#define V_IDMA1_QID(x) ((x) << S_IDMA1_QID)
+#define G_IDMA1_QID(x) (((x) >> S_IDMA1_QID) & M_IDMA1_QID)
+
+#define S_IDMA0_QID    0
+#define M_IDMA0_QID    0xffffU
+#define V_IDMA0_QID(x) ((x) << S_IDMA0_QID)
+#define G_IDMA0_QID(x) (((x) >> S_IDMA0_QID) & M_IDMA0_QID)
+
+#define A_SGE_ING_IMSG_RSP1_DBG 0x170c
+
+#define S_IDMA3_QID    16
+#define M_IDMA3_QID    0xffffU
+#define V_IDMA3_QID(x) ((x) << S_IDMA3_QID)
+#define G_IDMA3_QID(x) (((x) >> S_IDMA3_QID) & M_IDMA3_QID)
+
+#define S_IDMA2_QID    0
+#define M_IDMA2_QID    0xffffU
+#define V_IDMA2_QID(x) ((x) << S_IDMA2_QID)
+#define G_IDMA2_QID(x) (((x) >> S_IDMA2_QID) & M_IDMA2_QID)
+
+#define A_SGE_LB_MODE 0x1710
+
+#define S_LB_MODE    0
+#define M_LB_MODE    0x3U
+#define V_LB_MODE(x) ((x) << S_LB_MODE)
+#define G_LB_MODE(x) (((x) >> S_LB_MODE) & M_LB_MODE)
+
+#define A_SGE_IMSG_QUESCENT 0x1714
+
+#define S_IMSG_QUESCENT    0
+#define V_IMSG_QUESCENT(x) ((x) << S_IMSG_QUESCENT)
+#define F_IMSG_QUESCENT    V_IMSG_QUESCENT(1U)
+
+#define A_SGE_LA_CTRL 0x1718
+
+#define S_LA_GLOBAL_EN    8
+#define V_LA_GLOBAL_EN(x) ((x) << S_LA_GLOBAL_EN)
+#define F_LA_GLOBAL_EN    V_LA_GLOBAL_EN(1U)
+
+#define S_PTP_TIMESTAMP_SEL    7
+#define V_PTP_TIMESTAMP_SEL(x) ((x) << S_PTP_TIMESTAMP_SEL)
+#define F_PTP_TIMESTAMP_SEL    V_PTP_TIMESTAMP_SEL(1U)
+
+#define S_CIM2SGE_ID_CHK_VLD    6
+#define V_CIM2SGE_ID_CHK_VLD(x) ((x) << S_CIM2SGE_ID_CHK_VLD)
+#define F_CIM2SGE_ID_CHK_VLD    V_CIM2SGE_ID_CHK_VLD(1U)
+
+#define S_CPLSW_ID_CHK_VLD    5
+#define V_CPLSW_ID_CHK_VLD(x) ((x) << S_CPLSW_ID_CHK_VLD)
+#define F_CPLSW_ID_CHK_VLD    V_CPLSW_ID_CHK_VLD(1U)
+
+#define S_FLM_ID_CHK_VLD    4
+#define V_FLM_ID_CHK_VLD(x) ((x) << S_FLM_ID_CHK_VLD)
+#define F_FLM_ID_CHK_VLD    V_FLM_ID_CHK_VLD(1U)
+
+#define S_IQ_DBP_ID_CHK_VLD    3
+#define V_IQ_DBP_ID_CHK_VLD(x) ((x) << S_IQ_DBP_ID_CHK_VLD)
+#define F_IQ_DBP_ID_CHK_VLD    V_IQ_DBP_ID_CHK_VLD(1U)
+
+#define S_UP_OBQ_ID_CHK_VLD    2
+#define V_UP_OBQ_ID_CHK_VLD(x) ((x) << S_UP_OBQ_ID_CHK_VLD)
+#define F_UP_OBQ_ID_CHK_VLD    V_UP_OBQ_ID_CHK_VLD(1U)
+
+#define S_CIM_ID_CHK_VLD    1
+#define V_CIM_ID_CHK_VLD(x) ((x) << S_CIM_ID_CHK_VLD)
+#define F_CIM_ID_CHK_VLD    V_CIM_ID_CHK_VLD(1U)
+
+#define S_DBP_ID_CHK_VLD    0
+#define V_DBP_ID_CHK_VLD(x) ((x) << S_DBP_ID_CHK_VLD)
+#define F_DBP_ID_CHK_VLD    V_DBP_ID_CHK_VLD(1U)
+
+#define A_SGE_LA_CTRL_EQID_LOW 0x171c
+
+#define S_EQ_ID_CHK_LOW    0
+#define M_EQ_ID_CHK_LOW    0x1ffffU
+#define V_EQ_ID_CHK_LOW(x) ((x) << S_EQ_ID_CHK_LOW)
+#define G_EQ_ID_CHK_LOW(x) (((x) >> S_EQ_ID_CHK_LOW) & M_EQ_ID_CHK_LOW)
+
+#define A_SGE_LA_CTRL_EQID_HIGH 0x1720
+
+#define S_EQ_ID_CHK_HIGH    0
+#define M_EQ_ID_CHK_HIGH    0x1ffffU
+#define V_EQ_ID_CHK_HIGH(x) ((x) << S_EQ_ID_CHK_HIGH)
+#define G_EQ_ID_CHK_HIGH(x) (((x) >> S_EQ_ID_CHK_HIGH) & M_EQ_ID_CHK_HIGH)
+
+#define A_SGE_LA_CTRL_IQID 0x1724
+
+#define S_IQ_ID_CHK_HIGH    16
+#define M_IQ_ID_CHK_HIGH    0xffffU
+#define V_IQ_ID_CHK_HIGH(x) ((x) << S_IQ_ID_CHK_HIGH)
+#define G_IQ_ID_CHK_HIGH(x) (((x) >> S_IQ_ID_CHK_HIGH) & M_IQ_ID_CHK_HIGH)
+
+#define S_IQ_ID_CHK_LOW    0
+#define M_IQ_ID_CHK_LOW    0xffffU
+#define V_IQ_ID_CHK_LOW(x) ((x) << S_IQ_ID_CHK_LOW)
+#define G_IQ_ID_CHK_LOW(x) (((x) >> S_IQ_ID_CHK_LOW) & M_IQ_ID_CHK_LOW)
+
+#define A_SGE_LA_CTRL_TID_LOW 0x1728
+
+#define S_TID_CHK_LOW    0
+#define M_TID_CHK_LOW    0xffffffU
+#define V_TID_CHK_LOW(x) ((x) << S_TID_CHK_LOW)
+#define G_TID_CHK_LOW(x) (((x) >> S_TID_CHK_LOW) & M_TID_CHK_LOW)
+
+#define A_SGE_LA_CTRL_TID_HIGH 0x172c
+
+#define S_TID_CHK_HIGH    0
+#define M_TID_CHK_HIGH    0xffffffU
+#define V_TID_CHK_HIGH(x) ((x) << S_TID_CHK_HIGH)
+#define G_TID_CHK_HIGH(x) (((x) >> S_TID_CHK_HIGH) & M_TID_CHK_HIGH)
+
+#define A_SGE_CFG_TP_ERR 0x173c
+
+#define S_TP_ERR_STATUS_CH3    30
+#define M_TP_ERR_STATUS_CH3    0x3U
+#define V_TP_ERR_STATUS_CH3(x) ((x) << S_TP_ERR_STATUS_CH3)
+#define G_TP_ERR_STATUS_CH3(x) (((x) >> S_TP_ERR_STATUS_CH3) & M_TP_ERR_STATUS_CH3)
+
+#define S_TP_ERR_STATUS_CH2    28
+#define M_TP_ERR_STATUS_CH2    0x3U
+#define V_TP_ERR_STATUS_CH2(x) ((x) << S_TP_ERR_STATUS_CH2)
+#define G_TP_ERR_STATUS_CH2(x) (((x) >> S_TP_ERR_STATUS_CH2) & M_TP_ERR_STATUS_CH2)
+
+#define S_TP_ERR_STATUS_CH1    26
+#define M_TP_ERR_STATUS_CH1    0x3U
+#define V_TP_ERR_STATUS_CH1(x) ((x) << S_TP_ERR_STATUS_CH1)
+#define G_TP_ERR_STATUS_CH1(x) (((x) >> S_TP_ERR_STATUS_CH1) & M_TP_ERR_STATUS_CH1)
+
+#define S_TP_ERR_STATUS_CH0    24
+#define M_TP_ERR_STATUS_CH0    0x3U
+#define V_TP_ERR_STATUS_CH0(x) ((x) << S_TP_ERR_STATUS_CH0)
+#define G_TP_ERR_STATUS_CH0(x) (((x) >> S_TP_ERR_STATUS_CH0) & M_TP_ERR_STATUS_CH0)
+
+#define S_CPL0_SIZE    16
+#define M_CPL0_SIZE    0xffU
+#define V_CPL0_SIZE(x) ((x) << S_CPL0_SIZE)
+#define G_CPL0_SIZE(x) (((x) >> S_CPL0_SIZE) & M_CPL0_SIZE)
+
+#define S_CPL1_SIZE    8
+#define M_CPL1_SIZE    0xffU
+#define V_CPL1_SIZE(x) ((x) << S_CPL1_SIZE)
+#define G_CPL1_SIZE(x) (((x) >> S_CPL1_SIZE) & M_CPL1_SIZE)
+
+#define S_SIZE_LATCH_CLR    3
+#define V_SIZE_LATCH_CLR(x) ((x) << S_SIZE_LATCH_CLR)
+#define F_SIZE_LATCH_CLR    V_SIZE_LATCH_CLR(1U)
+
+#define S_EXT_LATCH_CLR    2
+#define V_EXT_LATCH_CLR(x) ((x) << S_EXT_LATCH_CLR)
+#define F_EXT_LATCH_CLR    V_EXT_LATCH_CLR(1U)
+
+#define S_EXT_CHANGE_42875    1
+#define V_EXT_CHANGE_42875(x) ((x) << S_EXT_CHANGE_42875)
+#define F_EXT_CHANGE_42875    V_EXT_CHANGE_42875(1U)
+
+#define S_SIZE_CHANGE_42913    0
+#define V_SIZE_CHANGE_42913(x) ((x) << S_SIZE_CHANGE_42913)
+#define F_SIZE_CHANGE_42913    V_SIZE_CHANGE_42913(1U)
+
+#define A_SGE_CHNL0_CTX_ERROR_COUNT_PER_TID 0x1740
+#define A_SGE_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1744
+#define A_SGE_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1748
+#define A_SGE_CHNL3_CTX_ERROR_COUNT_PER_TID 0x174c
+#define A_SGE_CTX_ACC_CH0 0x1750
+
+#define S_RDMA_INV_HANDLING    24
+#define M_RDMA_INV_HANDLING    0x3U
+#define V_RDMA_INV_HANDLING(x) ((x) << S_RDMA_INV_HANDLING)
+#define G_RDMA_INV_HANDLING(x) (((x) >> S_RDMA_INV_HANDLING) & M_RDMA_INV_HANDLING)
+
+#define S_T7_TERMINATE_STATUS_EN    23
+#define V_T7_TERMINATE_STATUS_EN(x) ((x) << S_T7_TERMINATE_STATUS_EN)
+#define F_T7_TERMINATE_STATUS_EN    V_T7_TERMINATE_STATUS_EN(1U)
+
+#define S_T7_DISABLE    22
+#define V_T7_DISABLE(x) ((x) << S_T7_DISABLE)
+#define F_T7_DISABLE    V_T7_DISABLE(1U)
+
+#define A_SGE_CTX_ACC_CH1 0x1754
+#define A_SGE_CTX_ACC_CH2 0x1758
+#define A_SGE_CTX_ACC_CH3 0x175c
+#define A_SGE_CTX_BASE 0x1760
 #define A_SGE_LA_RDPTR_0 0x1800
 #define A_SGE_LA_RDDATA_0 0x1804
 #define A_SGE_LA_WRPTR_0 0x1808
@@ -4296,6 +5074,11 @@
 
 #define A_PCIE_INT_CAUSE 0x3004
 #define A_PCIE_PERR_ENABLE 0x3008
+
+#define S_TGTTAGQCLIENT1PERR    29
+#define V_TGTTAGQCLIENT1PERR(x) ((x) << S_TGTTAGQCLIENT1PERR)
+#define F_TGTTAGQCLIENT1PERR    V_TGTTAGQCLIENT1PERR(1U)
+
 #define A_PCIE_PERR_INJECT 0x300c
 
 #define S_IDE    0
@@ -4582,10 +5365,6 @@
 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
 #define F_LINKREQRSTPCIECRSTMODE    V_LINKREQRSTPCIECRSTMODE(1U)
 
-#define S_T6_PIOSTOPEN    31
-#define V_T6_PIOSTOPEN(x) ((x) << S_T6_PIOSTOPEN)
-#define F_T6_PIOSTOPEN    V_T6_PIOSTOPEN(1U)
-
 #define A_PCIE_DMA_CTRL 0x3018
 
 #define S_LITTLEENDIAN    7
@@ -4618,6 +5397,14 @@
 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
 #define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG)
 
+#define S_REG_VDM_ONLY    17
+#define V_REG_VDM_ONLY(x) ((x) << S_REG_VDM_ONLY)
+#define F_REG_VDM_ONLY    V_REG_VDM_ONLY(1U)
+
+#define S_MULT_REQID_SUP    16
+#define V_MULT_REQID_SUP(x) ((x) << S_MULT_REQID_SUP)
+#define F_MULT_REQID_SUP    V_MULT_REQID_SUP(1U)
+
 #define A_PCIE_DMA_CFG 0x301c
 
 #define S_MAXPYLDSIZE    28
@@ -4668,6 +5455,10 @@
 #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
 #define F_DMADCASTFIRSTONLY    V_DMADCASTFIRSTONLY(1U)
 
+#define S_ARMDCASTFIRSTONLY    7
+#define V_ARMDCASTFIRSTONLY(x) ((x) << S_ARMDCASTFIRSTONLY)
+#define F_ARMDCASTFIRSTONLY    V_ARMDCASTFIRSTONLY(1U)
+
 #define A_PCIE_DMA_STAT 0x3020
 
 #define S_STATEREQ    28
@@ -4748,7 +5539,157 @@
 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
 
 #define A_PCIE_CFG7 0x302c
+#define A_PCIE_INT_ENABLE_EXT 0x3030
+
+#define S_TCAMRSPERR    31
+#define V_TCAMRSPERR(x) ((x) << S_TCAMRSPERR)
+#define F_TCAMRSPERR    V_TCAMRSPERR(1U)
+
+#define S_IPFORMQPERR    30
+#define V_IPFORMQPERR(x) ((x) << S_IPFORMQPERR)
+#define F_IPFORMQPERR    V_IPFORMQPERR(1U)
+
+#define S_IPFORMQCERR    29
+#define V_IPFORMQCERR(x) ((x) << S_IPFORMQCERR)
+#define F_IPFORMQCERR    V_IPFORMQCERR(1U)
+
+#define S_TRGT1GRPCERR    28
+#define V_TRGT1GRPCERR(x) ((x) << S_TRGT1GRPCERR)
+#define F_TRGT1GRPCERR    V_TRGT1GRPCERR(1U)
+
+#define S_IPSOTCERR    27
+#define V_IPSOTCERR(x) ((x) << S_IPSOTCERR)
+#define F_IPSOTCERR    V_IPSOTCERR(1U)
+
+#define S_IPRETRYCERR    26
+#define V_IPRETRYCERR(x) ((x) << S_IPRETRYCERR)
+#define F_IPRETRYCERR    V_IPRETRYCERR(1U)
+
+#define S_IPRXDATAGRPCERR    25
+#define V_IPRXDATAGRPCERR(x) ((x) << S_IPRXDATAGRPCERR)
+#define F_IPRXDATAGRPCERR    V_IPRXDATAGRPCERR(1U)
+
+#define S_IPRXHDRGRPCERR    24
+#define V_IPRXHDRGRPCERR(x) ((x) << S_IPRXHDRGRPCERR)
+#define F_IPRXHDRGRPCERR    V_IPRXHDRGRPCERR(1U)
+
+#define S_A0ARBRSPORDFIFOPERR    19
+#define V_A0ARBRSPORDFIFOPERR(x) ((x) << S_A0ARBRSPORDFIFOPERR)
+#define F_A0ARBRSPORDFIFOPERR    V_A0ARBRSPORDFIFOPERR(1U)
+
+#define S_HRSPCERR    18
+#define V_HRSPCERR(x) ((x) << S_HRSPCERR)
+#define F_HRSPCERR    V_HRSPCERR(1U)
+
+#define S_HREQRDCERR    17
+#define V_HREQRDCERR(x) ((x) << S_HREQRDCERR)
+#define F_HREQRDCERR    V_HREQRDCERR(1U)
+
+#define S_HREQWRCERR    16
+#define V_HREQWRCERR(x) ((x) << S_HREQWRCERR)
+#define F_HREQWRCERR    V_HREQWRCERR(1U)
+
+#define S_DRSPCERR    15
+#define V_DRSPCERR(x) ((x) << S_DRSPCERR)
+#define F_DRSPCERR    V_DRSPCERR(1U)
+
+#define S_DREQRDCERR    14
+#define V_DREQRDCERR(x) ((x) << S_DREQRDCERR)
+#define F_DREQRDCERR    V_DREQRDCERR(1U)
+
+#define S_DREQWRCERR    13
+#define V_DREQWRCERR(x) ((x) << S_DREQWRCERR)
+#define F_DREQWRCERR    V_DREQWRCERR(1U)
+
+#define S_CRSPCERR    12
+#define V_CRSPCERR(x) ((x) << S_CRSPCERR)
+#define F_CRSPCERR    V_CRSPCERR(1U)
+
+#define S_ARSPPERR    11
+#define V_ARSPPERR(x) ((x) << S_ARSPPERR)
+#define F_ARSPPERR    V_ARSPPERR(1U)
+
+#define S_AREQRDPERR    10
+#define V_AREQRDPERR(x) ((x) << S_AREQRDPERR)
+#define F_AREQRDPERR    V_AREQRDPERR(1U)
+
+#define S_AREQWRPERR    9
+#define V_AREQWRPERR(x) ((x) << S_AREQWRPERR)
+#define F_AREQWRPERR    V_AREQWRPERR(1U)
+
+#define S_PIOREQGRPCERR    8
+#define V_PIOREQGRPCERR(x) ((x) << S_PIOREQGRPCERR)
+#define F_PIOREQGRPCERR    V_PIOREQGRPCERR(1U)
+
+#define S_ARSPCERR    7
+#define V_ARSPCERR(x) ((x) << S_ARSPCERR)
+#define F_ARSPCERR    V_ARSPCERR(1U)
+
+#define S_AREQRDCERR    6
+#define V_AREQRDCERR(x) ((x) << S_AREQRDCERR)
+#define F_AREQRDCERR    V_AREQRDCERR(1U)
+
+#define S_AREQWRCERR    5
+#define V_AREQWRCERR(x) ((x) << S_AREQWRCERR)
+#define F_AREQWRCERR    V_AREQWRCERR(1U)
+
+#define S_MARSPPERR    4
+#define V_MARSPPERR(x) ((x) << S_MARSPPERR)
+#define F_MARSPPERR    V_MARSPPERR(1U)
+
+#define S_INICMAWDATAORDPERR    3
+#define V_INICMAWDATAORDPERR(x) ((x) << S_INICMAWDATAORDPERR)
+#define F_INICMAWDATAORDPERR    V_INICMAWDATAORDPERR(1U)
+
+#define S_EMUPERR    2
+#define V_EMUPERR(x) ((x) << S_EMUPERR)
+#define F_EMUPERR    V_EMUPERR(1U)
+
+#define S_ERRSPPERR    1
+#define V_ERRSPPERR(x) ((x) << S_ERRSPPERR)
+#define F_ERRSPPERR    V_ERRSPPERR(1U)
+
+#define S_MSTGRPCERR    0
+#define V_MSTGRPCERR(x) ((x) << S_MSTGRPCERR)
+#define F_MSTGRPCERR    V_MSTGRPCERR(1U)
+
+#define A_PCIE_INT_ENABLE_X8 0x3034
+
+#define S_X8TGTGRPPERR    23
+#define V_X8TGTGRPPERR(x) ((x) << S_X8TGTGRPPERR)
+#define F_X8TGTGRPPERR    V_X8TGTGRPPERR(1U)
+
+#define S_X8IPSOTPERR    22
+#define V_X8IPSOTPERR(x) ((x) << S_X8IPSOTPERR)
+#define F_X8IPSOTPERR    V_X8IPSOTPERR(1U)
+
+#define S_X8IPRETRYPERR    21
+#define V_X8IPRETRYPERR(x) ((x) << S_X8IPRETRYPERR)
+#define F_X8IPRETRYPERR    V_X8IPRETRYPERR(1U)
+
+#define S_X8IPRXDATAGRPPERR    20
+#define V_X8IPRXDATAGRPPERR(x) ((x) << S_X8IPRXDATAGRPPERR)
+#define F_X8IPRXDATAGRPPERR    V_X8IPRXDATAGRPPERR(1U)
+
+#define S_X8IPRXHDRGRPPERR    19
+#define V_X8IPRXHDRGRPPERR(x) ((x) << S_X8IPRXHDRGRPPERR)
+#define F_X8IPRXHDRGRPPERR    V_X8IPRXHDRGRPPERR(1U)
+
+#define S_X8IPCORECERR    3
+#define V_X8IPCORECERR(x) ((x) << S_X8IPCORECERR)
+#define F_X8IPCORECERR    V_X8IPCORECERR(1U)
+
+#define S_X8MSTGRPPERR    2
+#define V_X8MSTGRPPERR(x) ((x) << S_X8MSTGRPPERR)
+#define F_X8MSTGRPPERR    V_X8MSTGRPPERR(1U)
+
+#define S_X8MSTGRPCERR    1
+#define V_X8MSTGRPCERR(x) ((x) << S_X8MSTGRPCERR)
+#define F_X8MSTGRPCERR    V_X8MSTGRPCERR(1U)
+
+#define A_PCIE_INT_CAUSE_EXT 0x3038
 #define A_PCIE_CMD_CTRL 0x303c
+#define A_PCIE_INT_CAUSE_X8 0x303c
 #define A_PCIE_CMD_CFG 0x3040
 
 #define S_MAXRSPCNT    16
@@ -4761,6 +5702,40 @@
 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
 
+#define A_PCIE_PERR_ENABLE_EXT 0x3040
+
+#define S_T7_ARSPPERR    18
+#define V_T7_ARSPPERR(x) ((x) << S_T7_ARSPPERR)
+#define F_T7_ARSPPERR    V_T7_ARSPPERR(1U)
+
+#define S_T7_AREQRDPERR    17
+#define V_T7_AREQRDPERR(x) ((x) << S_T7_AREQRDPERR)
+#define F_T7_AREQRDPERR    V_T7_AREQRDPERR(1U)
+
+#define S_T7_AREQWRPERR    16
+#define V_T7_AREQWRPERR(x) ((x) << S_T7_AREQWRPERR)
+#define F_T7_AREQWRPERR    V_T7_AREQWRPERR(1U)
+
+#define S_T7_A0ARBRSPORDFIFOPERR    15
+#define V_T7_A0ARBRSPORDFIFOPERR(x) ((x) << S_T7_A0ARBRSPORDFIFOPERR)
+#define F_T7_A0ARBRSPORDFIFOPERR    V_T7_A0ARBRSPORDFIFOPERR(1U)
+
+#define S_T7_MARSPPERR    14
+#define V_T7_MARSPPERR(x) ((x) << S_T7_MARSPPERR)
+#define F_T7_MARSPPERR    V_T7_MARSPPERR(1U)
+
+#define S_T7_INICMAWDATAORDPERR    13
+#define V_T7_INICMAWDATAORDPERR(x) ((x) << S_T7_INICMAWDATAORDPERR)
+#define F_T7_INICMAWDATAORDPERR    V_T7_INICMAWDATAORDPERR(1U)
+
+#define S_T7_EMUPERR    12
+#define V_T7_EMUPERR(x) ((x) << S_T7_EMUPERR)
+#define F_T7_EMUPERR    V_T7_EMUPERR(1U)
+
+#define S_T7_ERRSPPERR    11
+#define V_T7_ERRSPPERR(x) ((x) << S_T7_ERRSPPERR)
+#define F_T7_ERRSPPERR    V_T7_ERRSPPERR(1U)
+
 #define A_PCIE_CMD_STAT 0x3044
 
 #define S_RSPCNT    16
@@ -4773,6 +5748,32 @@
 #define V_REQCNT(x) ((x) << S_REQCNT)
 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
 
+#define A_PCIE_PERR_ENABLE_X8 0x3044
+
+#define S_T7_X8TGTGRPPERR    28
+#define V_T7_X8TGTGRPPERR(x) ((x) << S_T7_X8TGTGRPPERR)
+#define F_T7_X8TGTGRPPERR    V_T7_X8TGTGRPPERR(1U)
+
+#define S_T7_X8IPSOTPERR    27
+#define V_T7_X8IPSOTPERR(x) ((x) << S_T7_X8IPSOTPERR)
+#define F_T7_X8IPSOTPERR    V_T7_X8IPSOTPERR(1U)
+
+#define S_T7_X8IPRETRYPERR    26
+#define V_T7_X8IPRETRYPERR(x) ((x) << S_T7_X8IPRETRYPERR)
+#define F_T7_X8IPRETRYPERR    V_T7_X8IPRETRYPERR(1U)
+
+#define S_T7_X8IPRXDATAGRPPERR    25
+#define V_T7_X8IPRXDATAGRPPERR(x) ((x) << S_T7_X8IPRXDATAGRPPERR)
+#define F_T7_X8IPRXDATAGRPPERR    V_T7_X8IPRXDATAGRPPERR(1U)
+
+#define S_T7_X8IPRXHDRGRPPERR    24
+#define V_T7_X8IPRXHDRGRPPERR(x) ((x) << S_T7_X8IPRXHDRGRPPERR)
+#define F_T7_X8IPRXHDRGRPPERR    V_T7_X8IPRXHDRGRPPERR(1U)
+
+#define S_T7_X8MSTGRPPERR    0
+#define V_T7_X8MSTGRPPERR(x) ((x) << S_T7_X8MSTGRPPERR)
+#define F_T7_X8MSTGRPPERR    V_T7_X8MSTGRPPERR(1U)
+
 #define A_PCIE_HMA_CTRL 0x3050
 
 #define S_IPLTSSM    12
@@ -4889,9 +5890,9 @@
 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
 #define F_T6_ENABLE    V_T6_ENABLE(1U)
 
-#define S_T6_AI    30
-#define V_T6_AI(x) ((x) << S_T6_AI)
-#define F_T6_AI    V_T6_AI(1U)
+#define S_T6_1_AI    30
+#define V_T6_1_AI(x) ((x) << S_T6_1_AI)
+#define F_T6_1_AI    V_T6_1_AI(1U)
 
 #define S_T6_CS2    29
 #define V_T6_CS2(x) ((x) << S_T6_CS2)
@@ -4936,6 +5937,7 @@
 #define V_MEMOFST(x) ((x) << S_MEMOFST)
 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
 
+#define A_T7_PCIE_MAILBOX_BASE_WIN 0x30a4
 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
 
 #define S_MBOXPCIEOFST    6
@@ -4953,7 +5955,21 @@
 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
 
+#define A_PCIE_MAILBOX_OFFSET0 0x30a8
+
+#define S_MEMOFST0    3
+#define M_MEMOFST0    0x1fffffffU
+#define V_MEMOFST0(x) ((x) << S_MEMOFST0)
+#define G_MEMOFST0(x) (((x) >> S_MEMOFST0) & M_MEMOFST0)
+
 #define A_PCIE_MAILBOX_OFFSET 0x30ac
+#define A_PCIE_MAILBOX_OFFSET1 0x30ac
+
+#define S_MEMOFST1    0
+#define M_MEMOFST1    0xfU
+#define V_MEMOFST1(x) ((x) << S_MEMOFST1)
+#define G_MEMOFST1(x) (((x) >> S_MEMOFST1) & M_MEMOFST1)
+
 #define A_PCIE_MA_CTRL 0x30b0
 
 #define S_MA_TAGFREE    29
@@ -5098,6 +6114,11 @@
 #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
 #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
 
+#define S_T7_STATIC_SPARE3    0
+#define M_T7_STATIC_SPARE3    0x7fffU
+#define V_T7_STATIC_SPARE3(x) ((x) << S_T7_STATIC_SPARE3)
+#define G_T7_STATIC_SPARE3(x) (((x) >> S_T7_STATIC_SPARE3) & M_T7_STATIC_SPARE3)
+
 #define A_PCIE_DBG_INDIR_REQ 0x30ec
 
 #define S_DBGENABLE    31
@@ -5173,6 +6194,17 @@
 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
 
 #define A_PCIE_PF_INT_CFG 0x3140
+
+#define S_T7_VECNUM    12
+#define M_T7_VECNUM    0x7ffU
+#define V_T7_VECNUM(x) ((x) << S_T7_VECNUM)
+#define G_T7_VECNUM(x) (((x) >> S_T7_VECNUM) & M_T7_VECNUM)
+
+#define S_T7_VECBASE    0
+#define M_T7_VECBASE    0xfffU
+#define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
+#define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
+
 #define A_PCIE_PF_INT_CFG2 0x3144
 #define A_PCIE_VF_INT_CFG 0x3180
 #define A_PCIE_VF_INT_CFG2 0x3184
@@ -5198,6 +6230,20 @@
 #define A_PCIE_VF_MSIX_EN_1 0x35c4
 #define A_PCIE_VF_MSIX_EN_2 0x35c8
 #define A_PCIE_VF_MSIX_EN_3 0x35cc
+#define A_PCIE_FID_PASID 0x35e0
+#define A_PCIE_FID_VFID_CTL 0x35e4
+
+#define S_T7_WRITE    0
+#define V_T7_WRITE(x) ((x) << S_T7_WRITE)
+#define F_T7_WRITE    V_T7_WRITE(1U)
+
+#define A_T7_PCIE_FID_VFID_SEL 0x35e8
+
+#define S_T7_ADDR    2
+#define M_T7_ADDR    0x1fffU
+#define V_T7_ADDR(x) ((x) << S_T7_ADDR)
+#define G_T7_ADDR(x) (((x) >> S_T7_ADDR) & M_T7_ADDR)
+
 #define A_PCIE_FID_VFID_SEL 0x35ec
 
 #define S_FID_VFID_SEL_SELECT    0
@@ -5205,6 +6251,17 @@
 #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
 #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
 
+#define A_T7_PCIE_FID_VFID 0x35ec
+
+#define S_FID_VFID_NVMEGROUPEN    29
+#define V_FID_VFID_NVMEGROUPEN(x) ((x) << S_FID_VFID_NVMEGROUPEN)
+#define F_FID_VFID_NVMEGROUPEN    V_FID_VFID_NVMEGROUPEN(1U)
+
+#define S_FID_VFID_GROUPSEL    25
+#define M_FID_VFID_GROUPSEL    0xfU
+#define V_FID_VFID_GROUPSEL(x) ((x) << S_FID_VFID_GROUPSEL)
+#define G_FID_VFID_GROUPSEL(x) (((x) >> S_FID_VFID_GROUPSEL) & M_FID_VFID_GROUPSEL)
+
 #define A_PCIE_FID_VFID 0x3600
 
 #define S_FID_VFID_SELECT    30
@@ -5264,6 +6321,227 @@
 #define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF)
 #define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF)
 
+#define A_PCIE_JBOF_NVME_HIGH_DW_START_ADDR 0x3600
+#define A_PCIE_JBOF_NVME_LOW_DW_START_ADDR 0x3604
+#define A_PCIE_JBOF_NVME_LENGTH 0x3608
+
+#define S_NVMEDISABLE    31
+#define V_NVMEDISABLE(x) ((x) << S_NVMEDISABLE)
+#define F_NVMEDISABLE    V_NVMEDISABLE(1U)
+
+#define S_NVMELENGTH    0
+#define M_NVMELENGTH    0x3fffffffU
+#define V_NVMELENGTH(x) ((x) << S_NVMELENGTH)
+#define G_NVMELENGTH(x) (((x) >> S_NVMELENGTH) & M_NVMELENGTH)
+
+#define A_PCIE_JBOF_NVME_GROUP 0x360c
+
+#define S_NVMEGROUPSEL    0
+#define M_NVMEGROUPSEL    0xfU
+#define V_NVMEGROUPSEL(x) ((x) << S_NVMEGROUPSEL)
+#define G_NVMEGROUPSEL(x) (((x) >> S_NVMEGROUPSEL) & M_NVMEGROUPSEL)
+
+#define A_T7_PCIE_MEM_ACCESS_BASE_WIN 0x3700
+#define A_PCIE_MEM_ACCESS_BASE_WIN1 0x3704
+
+#define S_PCIEOFST1    0
+#define M_PCIEOFST1    0xffU
+#define V_PCIEOFST1(x) ((x) << S_PCIEOFST1)
+#define G_PCIEOFST1(x) (((x) >> S_PCIEOFST1) & M_PCIEOFST1)
+
+#define A_PCIE_MEM_ACCESS_OFFSET0 0x3708
+#define A_PCIE_MEM_ACCESS_OFFSET1 0x370c
+#define A_PCIE_PTM_EP_EXT_STROBE 0x3804
+
+#define S_PTM_AUTO_UPDATE    1
+#define V_PTM_AUTO_UPDATE(x) ((x) << S_PTM_AUTO_UPDATE)
+#define F_PTM_AUTO_UPDATE    V_PTM_AUTO_UPDATE(1U)
+
+#define S_PTM_EXT_STROBE    0
+#define V_PTM_EXT_STROBE(x) ((x) << S_PTM_EXT_STROBE)
+#define F_PTM_EXT_STROBE    V_PTM_EXT_STROBE(1U)
+
+#define A_PCIE_PTM_EP_EXT_TIME0 0x3808
+#define A_PCIE_PTM_EP_EXT_TIME1 0x380c
+#define A_PCIE_PTM_MAN_UPD_PULSE 0x3810
+
+#define S_PTM_MAN_UPD_PULSE    0
+#define V_PTM_MAN_UPD_PULSE(x) ((x) << S_PTM_MAN_UPD_PULSE)
+#define F_PTM_MAN_UPD_PULSE    V_PTM_MAN_UPD_PULSE(1U)
+
+#define A_PCIE_SWAP_DATA_B2L_X16 0x3814
+#define A_PCIE_PCIE_RC_RST 0x3818
+
+#define S_PERST    0
+#define V_PERST(x) ((x) << S_PERST)
+#define F_PERST    V_PERST(1U)
+
+#define A_PCIE_PCIE_LN_CLKSEL 0x3880
+
+#define S_DS8_SEL    30
+#define M_DS8_SEL    0x3U
+#define V_DS8_SEL(x) ((x) << S_DS8_SEL)
+#define G_DS8_SEL(x) (((x) >> S_DS8_SEL) & M_DS8_SEL)
+
+#define S_DS7_SEL    28
+#define M_DS7_SEL    0x3U
+#define V_DS7_SEL(x) ((x) << S_DS7_SEL)
+#define G_DS7_SEL(x) (((x) >> S_DS7_SEL) & M_DS7_SEL)
+
+#define S_DS6_SEL    26
+#define M_DS6_SEL    0x3U
+#define V_DS6_SEL(x) ((x) << S_DS6_SEL)
+#define G_DS6_SEL(x) (((x) >> S_DS6_SEL) & M_DS6_SEL)
+
+#define S_DS5_SEL    24
+#define M_DS5_SEL    0x3U
+#define V_DS5_SEL(x) ((x) << S_DS5_SEL)
+#define G_DS5_SEL(x) (((x) >> S_DS5_SEL) & M_DS5_SEL)
+
+#define S_DS4_SEL    22
+#define M_DS4_SEL    0x3U
+#define V_DS4_SEL(x) ((x) << S_DS4_SEL)
+#define G_DS4_SEL(x) (((x) >> S_DS4_SEL) & M_DS4_SEL)
+
+#define S_DS3_SEL    20
+#define M_DS3_SEL    0x3U
+#define V_DS3_SEL(x) ((x) << S_DS3_SEL)
+#define G_DS3_SEL(x) (((x) >> S_DS3_SEL) & M_DS3_SEL)
+
+#define S_DS2_SEL    18
+#define M_DS2_SEL    0x3U
+#define V_DS2_SEL(x) ((x) << S_DS2_SEL)
+#define G_DS2_SEL(x) (((x) >> S_DS2_SEL) & M_DS2_SEL)
+
+#define S_DS1_SEL    16
+#define M_DS1_SEL    0x3U
+#define V_DS1_SEL(x) ((x) << S_DS1_SEL)
+#define G_DS1_SEL(x) (((x) >> S_DS1_SEL) & M_DS1_SEL)
+
+#define S_LN14_SEL    14
+#define M_LN14_SEL    0x3U
+#define V_LN14_SEL(x) ((x) << S_LN14_SEL)
+#define G_LN14_SEL(x) (((x) >> S_LN14_SEL) & M_LN14_SEL)
+
+#define S_LN12_SEL    12
+#define M_LN12_SEL    0x3U
+#define V_LN12_SEL(x) ((x) << S_LN12_SEL)
+#define G_LN12_SEL(x) (((x) >> S_LN12_SEL) & M_LN12_SEL)
+
+#define S_LN10_SEL    10
+#define M_LN10_SEL    0x3U
+#define V_LN10_SEL(x) ((x) << S_LN10_SEL)
+#define G_LN10_SEL(x) (((x) >> S_LN10_SEL) & M_LN10_SEL)
+
+#define S_LN8_SEL    8
+#define M_LN8_SEL    0x3U
+#define V_LN8_SEL(x) ((x) << S_LN8_SEL)
+#define G_LN8_SEL(x) (((x) >> S_LN8_SEL) & M_LN8_SEL)
+
+#define S_LN6_SEL    6
+#define M_LN6_SEL    0x3U
+#define V_LN6_SEL(x) ((x) << S_LN6_SEL)
+#define G_LN6_SEL(x) (((x) >> S_LN6_SEL) & M_LN6_SEL)
+
+#define S_LN4_SEL    4
+#define M_LN4_SEL    0x3U
+#define V_LN4_SEL(x) ((x) << S_LN4_SEL)
+#define G_LN4_SEL(x) (((x) >> S_LN4_SEL) & M_LN4_SEL)
+
+#define S_LN2_SEL    2
+#define M_LN2_SEL    0x3U
+#define V_LN2_SEL(x) ((x) << S_LN2_SEL)
+#define G_LN2_SEL(x) (((x) >> S_LN2_SEL) & M_LN2_SEL)
+
+#define S_LN0_SEL    0
+#define M_LN0_SEL    0x3U
+#define V_LN0_SEL(x) ((x) << S_LN0_SEL)
+#define G_LN0_SEL(x) (((x) >> S_LN0_SEL) & M_LN0_SEL)
+
+#define A_PCIE_PCIE_MSIX_EN 0x3884
+
+#define S_MSIX_ENABLE    0
+#define M_MSIX_ENABLE    0xffU
+#define V_MSIX_ENABLE(x) ((x) << S_MSIX_ENABLE)
+#define G_MSIX_ENABLE(x) (((x) >> S_MSIX_ENABLE) & M_MSIX_ENABLE)
+
+#define A_PCIE_LFSR_WRCTRL 0x3888
+
+#define S_WR_LFSR_CMP_DATA    16
+#define M_WR_LFSR_CMP_DATA    0xffffU
+#define V_WR_LFSR_CMP_DATA(x) ((x) << S_WR_LFSR_CMP_DATA)
+#define G_WR_LFSR_CMP_DATA(x) (((x) >> S_WR_LFSR_CMP_DATA) & M_WR_LFSR_CMP_DATA)
+
+#define S_WR_LFSR_RSVD    2
+#define M_WR_LFSR_RSVD    0x3fffU
+#define V_WR_LFSR_RSVD(x) ((x) << S_WR_LFSR_RSVD)
+#define G_WR_LFSR_RSVD(x) (((x) >> S_WR_LFSR_RSVD) & M_WR_LFSR_RSVD)
+
+#define S_WR_LFSR_EN    1
+#define V_WR_LFSR_EN(x) ((x) << S_WR_LFSR_EN)
+#define F_WR_LFSR_EN    V_WR_LFSR_EN(1U)
+
+#define S_WR_LFSR_START    0
+#define V_WR_LFSR_START(x) ((x) << S_WR_LFSR_START)
+#define F_WR_LFSR_START    V_WR_LFSR_START(1U)
+
+#define A_PCIE_LFSR_RDCTRL 0x388c
+
+#define S_CMD_LFSR_CMP_DATA    24
+#define M_CMD_LFSR_CMP_DATA    0xffU
+#define V_CMD_LFSR_CMP_DATA(x) ((x) << S_CMD_LFSR_CMP_DATA)
+#define G_CMD_LFSR_CMP_DATA(x) (((x) >> S_CMD_LFSR_CMP_DATA) & M_CMD_LFSR_CMP_DATA)
+
+#define S_RD_LFSR_CMD_DATA    16
+#define M_RD_LFSR_CMD_DATA    0xffU
+#define V_RD_LFSR_CMD_DATA(x) ((x) << S_RD_LFSR_CMD_DATA)
+#define G_RD_LFSR_CMD_DATA(x) (((x) >> S_RD_LFSR_CMD_DATA) & M_RD_LFSR_CMD_DATA)
+
+#define S_RD_LFSR_RSVD    10
+#define M_RD_LFSR_RSVD    0x3fU
+#define V_RD_LFSR_RSVD(x) ((x) << S_RD_LFSR_RSVD)
+#define G_RD_LFSR_RSVD(x) (((x) >> S_RD_LFSR_RSVD) & M_RD_LFSR_RSVD)
+
+#define S_RD3_LFSR_EN    9
+#define V_RD3_LFSR_EN(x) ((x) << S_RD3_LFSR_EN)
+#define F_RD3_LFSR_EN    V_RD3_LFSR_EN(1U)
+
+#define S_RD3_LFSR_START    8
+#define V_RD3_LFSR_START(x) ((x) << S_RD3_LFSR_START)
+#define F_RD3_LFSR_START    V_RD3_LFSR_START(1U)
+
+#define S_RD2_LFSR_EN    7
+#define V_RD2_LFSR_EN(x) ((x) << S_RD2_LFSR_EN)
+#define F_RD2_LFSR_EN    V_RD2_LFSR_EN(1U)
+
+#define S_RD2_LFSR_START    6
+#define V_RD2_LFSR_START(x) ((x) << S_RD2_LFSR_START)
+#define F_RD2_LFSR_START    V_RD2_LFSR_START(1U)
+
+#define S_RD1_LFSR_EN    5
+#define V_RD1_LFSR_EN(x) ((x) << S_RD1_LFSR_EN)
+#define F_RD1_LFSR_EN    V_RD1_LFSR_EN(1U)
+
+#define S_RD1_LFSR_START    4
+#define V_RD1_LFSR_START(x) ((x) << S_RD1_LFSR_START)
+#define F_RD1_LFSR_START    V_RD1_LFSR_START(1U)
+
+#define S_RD0_LFSR_EN    3
+#define V_RD0_LFSR_EN(x) ((x) << S_RD0_LFSR_EN)
+#define F_RD0_LFSR_EN    V_RD0_LFSR_EN(1U)
+
+#define S_RD0_LFSR_START    2
+#define V_RD0_LFSR_START(x) ((x) << S_RD0_LFSR_START)
+#define F_RD0_LFSR_START    V_RD0_LFSR_START(1U)
+
+#define S_CMD_LFSR_EN    1
+#define V_CMD_LFSR_EN(x) ((x) << S_CMD_LFSR_EN)
+#define F_CMD_LFSR_EN    V_CMD_LFSR_EN(1U)
+
+#define S_CMD_LFSR_START    0
+#define V_CMD_LFSR_START(x) ((x) << S_CMD_LFSR_START)
+#define F_CMD_LFSR_START    V_CMD_LFSR_START(1U)
+
 #define A_PCIE_FID 0x3900
 
 #define S_PAD    11
@@ -5280,6 +6558,309 @@
 #define V_FUNC(x) ((x) << S_FUNC)
 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
 
+#define A_PCIE_EMU_ADDR 0x3900
+
+#define S_EMU_ADDR    0
+#define M_EMU_ADDR    0x1ffU
+#define V_EMU_ADDR(x) ((x) << S_EMU_ADDR)
+#define G_EMU_ADDR(x) (((x) >> S_EMU_ADDR) & M_EMU_ADDR)
+
+#define A_PCIE_EMU_CFG 0x3904
+
+#define S_EMUENABLE    16
+#define V_EMUENABLE(x) ((x) << S_EMUENABLE)
+#define F_EMUENABLE    V_EMUENABLE(1U)
+
+#define S_EMUTYPE    14
+#define M_EMUTYPE    0x3U
+#define V_EMUTYPE(x) ((x) << S_EMUTYPE)
+#define G_EMUTYPE(x) (((x) >> S_EMUTYPE) & M_EMUTYPE)
+
+#define S_BAR0TARGET    12
+#define M_BAR0TARGET    0x3U
+#define V_BAR0TARGET(x) ((x) << S_BAR0TARGET)
+#define G_BAR0TARGET(x) (((x) >> S_BAR0TARGET) & M_BAR0TARGET)
+
+#define S_BAR2TARGET    10
+#define M_BAR2TARGET    0x3U
+#define V_BAR2TARGET(x) ((x) << S_BAR2TARGET)
+#define G_BAR2TARGET(x) (((x) >> S_BAR2TARGET) & M_BAR2TARGET)
+
+#define S_BAR4TARGET    8
+#define M_BAR4TARGET    0x3U
+#define V_BAR4TARGET(x) ((x) << S_BAR4TARGET)
+#define G_BAR4TARGET(x) (((x) >> S_BAR4TARGET) & M_BAR4TARGET)
+
+#define S_RELEATIVEEMUID    0
+#define M_RELEATIVEEMUID    0xffU
+#define V_RELEATIVEEMUID(x) ((x) << S_RELEATIVEEMUID)
+#define G_RELEATIVEEMUID(x) (((x) >> S_RELEATIVEEMUID) & M_RELEATIVEEMUID)
+
+#define A_PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0 0x3910
+
+#define S_T7_MEMOFST0    0
+#define M_T7_MEMOFST0    0xfffffffU
+#define V_T7_MEMOFST0(x) ((x) << S_T7_MEMOFST0)
+#define G_T7_MEMOFST0(x) (((x) >> S_T7_MEMOFST0) & M_T7_MEMOFST0)
+
+#define A_PCIE_EMUADRRMAP_MEM_CFG0_BAR0 0x3914
+
+#define S_SIZE0    0
+#define M_SIZE0    0x1fU
+#define V_SIZE0(x) ((x) << S_SIZE0)
+#define G_SIZE0(x) (((x) >> S_SIZE0) & M_SIZE0)
+
+#define A_PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0 0x3918
+
+#define S_T7_MEMOFST1    0
+#define M_T7_MEMOFST1    0xfffffffU
+#define V_T7_MEMOFST1(x) ((x) << S_T7_MEMOFST1)
+#define G_T7_MEMOFST1(x) (((x) >> S_T7_MEMOFST1) & M_T7_MEMOFST1)
+
+#define A_PCIE_EMUADRRMAP_MEM_CFG1_BAR0 0x391c
+
+#define S_SIZE1    0
+#define M_SIZE1    0x1fU
+#define V_SIZE1(x) ((x) << S_SIZE1)
+#define G_SIZE1(x) (((x) >> S_SIZE1) & M_SIZE1)
+
+#define A_PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0 0x3920
+
+#define S_MEMOFST2    0
+#define M_MEMOFST2    0xfffffffU
+#define V_MEMOFST2(x) ((x) << S_MEMOFST2)
+#define G_MEMOFST2(x) (((x) >> S_MEMOFST2) & M_MEMOFST2)
+
+#define A_PCIE_EMUADRRMAP_MEM_CFG2_BAR0 0x3924
+
+#define S_SIZE2    0
+#define M_SIZE2    0x1fU
+#define V_SIZE2(x) ((x) << S_SIZE2)
+#define G_SIZE2(x) (((x) >> S_SIZE2) & M_SIZE2)
+
+#define A_PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0 0x3928
+
+#define S_MEMOFST3    0
+#define M_MEMOFST3    0xfffffffU
+#define V_MEMOFST3(x) ((x) << S_MEMOFST3)
+#define G_MEMOFST3(x) (((x) >> S_MEMOFST3) & M_MEMOFST3)
+
+#define A_PCIE_EMUADRRMAP_MEM_CFG3_BAR0 0x392c
+
+#define S_SIZE3    0
+#define M_SIZE3    0x1fU
+#define V_SIZE3(x) ((x) << S_SIZE3)
+#define G_SIZE3(x) (((x) >> S_SIZE3) & M_SIZE3)
+
+#define A_PCIE_TCAM_DATA 0x3970
+#define A_PCIE_TCAM_CTL 0x3974
+
+#define S_TCAMADDR    8
+#define M_TCAMADDR    0x3ffU
+#define V_TCAMADDR(x) ((x) << S_TCAMADDR)
+#define G_TCAMADDR(x) (((x) >> S_TCAMADDR) & M_TCAMADDR)
+
+#define S_CAMEN    0
+#define V_CAMEN(x) ((x) << S_CAMEN)
+#define F_CAMEN    V_CAMEN(1U)
+
+#define A_PCIE_TCAM_DBG 0x3978
+
+#define S_CBPASS    24
+#define V_CBPASS(x) ((x) << S_CBPASS)
+#define F_CBPASS    V_CBPASS(1U)
+
+#define S_CBBUSY    20
+#define V_CBBUSY(x) ((x) << S_CBBUSY)
+#define F_CBBUSY    V_CBBUSY(1U)
+
+#define S_CBSTART    17
+#define V_CBSTART(x) ((x) << S_CBSTART)
+#define F_CBSTART    V_CBSTART(1U)
+
+#define S_RSTCB    16
+#define V_RSTCB(x) ((x) << S_RSTCB)
+#define F_RSTCB    V_RSTCB(1U)
+
+#define S_TCAM_DBG_DATA    0
+#define M_TCAM_DBG_DATA    0xffffU
+#define V_TCAM_DBG_DATA(x) ((x) << S_TCAM_DBG_DATA)
+#define G_TCAM_DBG_DATA(x) (((x) >> S_TCAM_DBG_DATA) & M_TCAM_DBG_DATA)
+
+#define A_PCIE_TEST_CTRL0 0x3980
+#define A_PCIE_TEST_CTRL1 0x3984
+#define A_PCIE_TEST_CTRL2 0x3988
+#define A_PCIE_TEST_CTRL3 0x398c
+#define A_PCIE_TEST_STS0 0x3990
+#define A_PCIE_TEST_STS1 0x3994
+#define A_PCIE_TEST_STS2 0x3998
+#define A_PCIE_TEST_STS3 0x399c
+#define A_PCIE_X8_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x4700
+#define A_PCIE_X8_CORE_VENDOR_SPECIFIC_DLLP 0x4704
+#define A_PCIE_X8_CORE_PORT_FORCE_LINK 0x4708
+#define A_PCIE_X8_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x470c
+#define A_PCIE_X8_CORE_PORT_LINK_CONTROL 0x4710
+#define A_PCIE_X8_CORE_LANE_SKEW 0x4714
+#define A_PCIE_X8_CORE_SYMBOL_NUMBER 0x4718
+#define A_PCIE_X8_CORE_SYMBOL_TIMER_FILTER_MASK1 0x471c
+#define A_PCIE_X8_CORE_FILTER_MASK2 0x4720
+#define A_PCIE_X8_CORE_DEBUG_0 0x4728
+#define A_PCIE_X8_CORE_DEBUG_1 0x472c
+#define A_PCIE_X8_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x4730
+#define A_PCIE_X8_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x4734
+#define A_PCIE_X8_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x4738
+#define A_PCIE_X8_CORE_QUEUE_STATUS 0x473c
+#define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_1 0x4740
+#define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_2 0x4744
+#define A_PCIE_X8_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x4748
+#define A_PCIE_X8_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x474c
+#define A_PCIE_X8_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x4750
+#define A_PCIE_X8_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x4754
+#define A_PCIE_X8_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x4758
+#define A_PCIE_X8_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x475c
+#define A_PCIE_X8_CORE_LINK_WIDTH_SPEED_CHANGE 0x480c
+#define A_PCIE_X8_CORE_PHY_STATUS 0x4810
+#define A_PCIE_X8_CORE_PHY_CONTROL 0x4814
+#define A_PCIE_X8_CORE_GEN3_CONTROL 0x4890
+#define A_PCIE_X8_CORE_GEN3_EQ_FS_LF 0x4894
+#define A_PCIE_X8_CORE_GEN3_EQ_PRESET_COEFF 0x4898
+#define A_PCIE_X8_CORE_GEN3_EQ_PRESET_INDEX 0x489c
+#define A_PCIE_X8_CORE_GEN3_EQ_STATUS 0x48a4
+#define A_PCIE_X8_CORE_GEN3_EQ_CONTROL 0x48a8
+#define A_PCIE_X8_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x48ac
+#define A_PCIE_X8_CORE_PIPE_CONTROL 0x48b8
+#define A_PCIE_X8_CORE_DBI_RO_WE 0x48bc
+#define A_PCIE_X8_CFG_SPACE_REQ 0x48c0
+#define A_PCIE_X8_CFG_SPACE_DATA 0x48c4
+#define A_PCIE_X8_CFG_MPS_MRS 0x4900
+
+#define S_MRS    3
+#define M_MRS    0x7U
+#define V_MRS(x) ((x) << S_MRS)
+#define G_MRS(x) (((x) >> S_MRS) & M_MRS)
+
+#define S_T7_MPS    0
+#define M_T7_MPS    0x7U
+#define V_T7_MPS(x) ((x) << S_T7_MPS)
+#define G_T7_MPS(x) (((x) >> S_T7_MPS) & M_T7_MPS)
+
+#define A_PCIE_X8_CFG_ATTRIBUTES 0x4904
+
+#define S_T7_DCAEN    2
+#define V_T7_DCAEN(x) ((x) << S_T7_DCAEN)
+#define F_T7_DCAEN    V_T7_DCAEN(1U)
+
+#define S_DCASTFITTRAONLEN    1
+#define V_DCASTFITTRAONLEN(x) ((x) << S_DCASTFITTRAONLEN)
+#define F_DCASTFITTRAONLEN    V_DCASTFITTRAONLEN(1U)
+
+#define S_REQCTLDYNSTCLKEN    0
+#define V_REQCTLDYNSTCLKEN(x) ((x) << S_REQCTLDYNSTCLKEN)
+#define F_REQCTLDYNSTCLKEN    V_REQCTLDYNSTCLKEN(1U)
+
+#define A_PCIE_X8_CFG_LTSSM 0x4908
+
+#define S_APP_LTSSM_ENABLE    0
+#define V_APP_LTSSM_ENABLE(x) ((x) << S_APP_LTSSM_ENABLE)
+#define F_APP_LTSSM_ENABLE    V_APP_LTSSM_ENABLE(1U)
+
+#define A_PCIE_ARM_REQUESTER_ID_X8 0x490c
+
+#define S_A1_RSVD1    24
+#define M_A1_RSVD1    0xffU
+#define V_A1_RSVD1(x) ((x) << S_A1_RSVD1)
+#define G_A1_RSVD1(x) (((x) >> S_A1_RSVD1) & M_A1_RSVD1)
+
+#define S_A1_PRIMBUSNUMBER    16
+#define M_A1_PRIMBUSNUMBER    0xffU
+#define V_A1_PRIMBUSNUMBER(x) ((x) << S_A1_PRIMBUSNUMBER)
+#define G_A1_PRIMBUSNUMBER(x) (((x) >> S_A1_PRIMBUSNUMBER) & M_A1_PRIMBUSNUMBER)
+
+#define S_A1_REQUESTERID    0
+#define M_A1_REQUESTERID    0xffffU
+#define V_A1_REQUESTERID(x) ((x) << S_A1_REQUESTERID)
+#define G_A1_REQUESTERID(x) (((x) >> S_A1_REQUESTERID) & M_A1_REQUESTERID)
+
+#define A_PCIE_SWAP_DATA_B2L_X8 0x4910
+
+#define S_CFGRD_SWAP_EN    1
+#define V_CFGRD_SWAP_EN(x) ((x) << S_CFGRD_SWAP_EN)
+#define F_CFGRD_SWAP_EN    V_CFGRD_SWAP_EN(1U)
+
+#define S_CFGWR_SWAP_EN    0
+#define V_CFGWR_SWAP_EN(x) ((x) << S_CFGWR_SWAP_EN)
+#define F_CFGWR_SWAP_EN    V_CFGWR_SWAP_EN(1U)
+
+#define A_PCIE_PDEBUG_DATA0_X8 0x4914
+#define A_PCIE_PDEBUG_DATA1_X8 0x4918
+#define A_PCIE_PDEBUG_DATA2_X8 0x491c
+#define A_PCIE_PDEBUG_CTRL_X8 0x4920
+#define A_PCIE_PDEBUG_DATA_X8 0x4924
+#define A_PCIE_SPARE_REGISTER_SPACES_X8 0x4ffc
+#define A_PCIE_PIPE_LANE0_REG0 0x5500
+#define A_PCIE_PIPE_LANE0_REG1 0x5504
+#define A_PCIE_PIPE_LANE0_REG2 0x5508
+#define A_PCIE_PIPE_LANE0_REG3 0x550c
+#define A_PCIE_PIPE_LANE1_REG0 0x5510
+#define A_PCIE_PIPE_LANE1_REG1 0x5514
+#define A_PCIE_PIPE_LANE1_REG2 0x5518
+#define A_PCIE_PIPE_LANE1_REG3 0x551c
+#define A_PCIE_PIPE_LANE2_REG0 0x5520
+#define A_PCIE_PIPE_LANE2_REG1 0x5524
+#define A_PCIE_PIPE_LANE2_REG2 0x5528
+#define A_PCIE_PIPE_LANE2_REG3 0x552c
+#define A_PCIE_PIPE_LANE3_REG0 0x5530
+#define A_PCIE_PIPE_LANE3_REG1 0x5534
+#define A_PCIE_PIPE_LANE3_REG2 0x5538
+#define A_PCIE_PIPE_LANE3_REG3 0x553c
+#define A_PCIE_PIPE_LANE4_REG0 0x5540
+#define A_PCIE_PIPE_LANE4_REG1 0x5544
+#define A_PCIE_PIPE_LANE4_REG2 0x5548
+#define A_PCIE_PIPE_LANE4_REG3 0x554c
+#define A_PCIE_PIPE_LANE5_REG0 0x5550
+#define A_PCIE_PIPE_LANE5_REG1 0x5554
+#define A_PCIE_PIPE_LANE5_REG2 0x5558
+#define A_PCIE_PIPE_LANE5_REG3 0x555c
+#define A_PCIE_PIPE_LANE6_REG0 0x5560
+#define A_PCIE_PIPE_LANE6_REG1 0x5564
+#define A_PCIE_PIPE_LANE6_REG2 0x5568
+#define A_PCIE_PIPE_LANE6_REG3 0x556c
+#define A_PCIE_PIPE_LANE7_REG0 0x5570
+#define A_PCIE_PIPE_LANE7_REG1 0x5574
+#define A_PCIE_PIPE_LANE7_REG2 0x5578
+#define A_PCIE_PIPE_LANE7_REG3 0x557c
+#define A_PCIE_PIPE_LANE8_REG0 0x5580
+#define A_PCIE_PIPE_LANE8_REG1 0x5584
+#define A_PCIE_PIPE_LANE8_REG2 0x5588
+#define A_PCIE_PIPE_LANE8_REG3 0x558c
+#define A_PCIE_PIPE_LANE9_REG0 0x5590
+#define A_PCIE_PIPE_LANE9_REG1 0x5594
+#define A_PCIE_PIPE_LANE9_REG2 0x5598
+#define A_PCIE_PIPE_LANE9_REG3 0x559c
+#define A_PCIE_PIPE_LANE10_REG0 0x55a0
+#define A_PCIE_PIPE_LANE10_REG1 0x55a4
+#define A_PCIE_PIPE_LANE10_REG2 0x55a8
+#define A_PCIE_PIPE_LANE10_REG3 0x55ac
+#define A_PCIE_PIPE_LANE11_REG0 0x55b0
+#define A_PCIE_PIPE_LANE11_REG1 0x55b4
+#define A_PCIE_PIPE_LANE11_REG2 0x55b8
+#define A_PCIE_PIPE_LANE11_REG3 0x55bc
+#define A_PCIE_PIPE_LANE12_REG0 0x55c0
+#define A_PCIE_PIPE_LANE12_REG1 0x55c4
+#define A_PCIE_PIPE_LANE12_REG2 0x55c8
+#define A_PCIE_PIPE_LANE12_REG3 0x55cc
+#define A_PCIE_PIPE_LANE13_REG0 0x55d0
+#define A_PCIE_PIPE_LANE13_REG1 0x55d4
+#define A_PCIE_PIPE_LANE13_REG2 0x55d8
+#define A_PCIE_PIPE_LANE13_REG3 0x55dc
+#define A_PCIE_PIPE_LANE14_REG0 0x55e0
+#define A_PCIE_PIPE_LANE14_REG1 0x55e4
+#define A_PCIE_PIPE_LANE14_REG2 0x55e8
+#define A_PCIE_PIPE_LANE14_REG3 0x55ec
+#define A_PCIE_PIPE_LANE15_REG0 0x55f0
+#define A_PCIE_PIPE_LANE15_REG1 0x55f4
+#define A_PCIE_PIPE_LANE15_REG2 0x55f8
+#define A_PCIE_PIPE_LANE15_REG3 0x55fc
 #define A_PCIE_COOKIE_STAT 0x5600
 
 #define S_COOKIEB    16
@@ -5346,6 +6927,30 @@
 #define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE)
 #define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE)
 
+#define A_T7_PCIE_VC0_CDTS0 0x56c4
+
+#define S_T7_CPLD0    16
+#define M_T7_CPLD0    0xffffU
+#define V_T7_CPLD0(x) ((x) << S_T7_CPLD0)
+#define G_T7_CPLD0(x) (((x) >> S_T7_CPLD0) & M_T7_CPLD0)
+
+#define S_T7_CPLH0    0
+#define M_T7_CPLH0    0xfffU
+#define V_T7_CPLH0(x) ((x) << S_T7_CPLH0)
+#define G_T7_CPLH0(x) (((x) >> S_T7_CPLH0) & M_T7_CPLH0)
+
+#define A_T7_PCIE_VC0_CDTS1 0x56c8
+
+#define S_T7_PD0    16
+#define M_T7_PD0    0xffffU
+#define V_T7_PD0(x) ((x) << S_T7_PD0)
+#define G_T7_PD0(x) (((x) >> S_T7_PD0) & M_T7_PD0)
+
+#define S_T7_PH0    0
+#define M_T7_PH0    0xfffU
+#define V_T7_PH0(x) ((x) << S_T7_PH0)
+#define G_T7_PH0(x) (((x) >> S_T7_PH0) & M_T7_PH0)
+
 #define A_PCIE_VC0_CDTS0 0x56cc
 
 #define S_CPLD0    20
@@ -5363,6 +6968,18 @@
 #define V_PD0(x) ((x) << S_PD0)
 #define G_PD0(x) (((x) >> S_PD0) & M_PD0)
 
+#define A_PCIE_VC0_CDTS2 0x56cc
+
+#define S_T7_NPD0    16
+#define M_T7_NPD0    0xffffU
+#define V_T7_NPD0(x) ((x) << S_T7_NPD0)
+#define G_T7_NPD0(x) (((x) >> S_T7_NPD0) & M_T7_NPD0)
+
+#define S_T7_NPH0    0
+#define M_T7_NPH0    0xfffU
+#define V_T7_NPH0(x) ((x) << S_T7_NPH0)
+#define G_T7_NPH0(x) (((x) >> S_T7_NPH0) & M_T7_NPH0)
+
 #define A_PCIE_VC0_CDTS1 0x56d0
 
 #define S_CPLH0    20
@@ -5380,6 +6997,7 @@
 #define V_NPD0(x) ((x) << S_NPD0)
 #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
 
+#define A_T7_PCIE_VC1_CDTS0 0x56d0
 #define A_PCIE_VC1_CDTS0 0x56d4
 
 #define S_CPLD1    20
@@ -5397,6 +7015,7 @@
 #define V_PD1(x) ((x) << S_PD1)
 #define G_PD1(x) (((x) >> S_PD1) & M_PD1)
 
+#define A_T7_PCIE_VC1_CDTS1 0x56d4
 #define A_PCIE_VC1_CDTS1 0x56d8
 
 #define S_CPLH1    20
@@ -5414,6 +7033,7 @@
 #define V_NPD1(x) ((x) << S_NPD1)
 #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
 
+#define A_PCIE_VC1_CDTS2 0x56d8
 #define A_PCIE_FLR_PF_STATUS 0x56dc
 #define A_PCIE_FLR_VF0_STATUS 0x56e0
 #define A_PCIE_FLR_VF1_STATUS 0x56e4
@@ -5916,6 +7536,11 @@
 #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
 #define F_DISABLE_SCRAMBLER    V_DISABLE_SCRAMBLER(1U)
 
+#define S_RATE_SHADOW_SEL    24
+#define M_RATE_SHADOW_SEL    0x3U
+#define V_RATE_SHADOW_SEL(x) ((x) << S_RATE_SHADOW_SEL)
+#define G_RATE_SHADOW_SEL(x) (((x) >> S_RATE_SHADOW_SEL) & M_RATE_SHADOW_SEL)
+
 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
 
 #define S_FULL_SWING    6
@@ -6347,6 +7972,35 @@
 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
 
+#define S_DMA_COOKIECNT    24
+#define M_DMA_COOKIECNT    0xfU
+#define V_DMA_COOKIECNT(x) ((x) << S_DMA_COOKIECNT)
+#define G_DMA_COOKIECNT(x) (((x) >> S_DMA_COOKIECNT) & M_DMA_COOKIECNT)
+
+#define S_DMA_RDSEQNUMUPDCNT    20
+#define M_DMA_RDSEQNUMUPDCNT    0xfU
+#define V_DMA_RDSEQNUMUPDCNT(x) ((x) << S_DMA_RDSEQNUMUPDCNT)
+#define G_DMA_RDSEQNUMUPDCNT(x) (((x) >> S_DMA_RDSEQNUMUPDCNT) & M_DMA_RDSEQNUMUPDCNT)
+
+#define S_DMA_SIREQCNT    16
+#define M_DMA_SIREQCNT    0xfU
+#define V_DMA_SIREQCNT(x) ((x) << S_DMA_SIREQCNT)
+#define G_DMA_SIREQCNT(x) (((x) >> S_DMA_SIREQCNT) & M_DMA_SIREQCNT)
+
+#define S_DMA_WREOPMATCHSOP    12
+#define V_DMA_WREOPMATCHSOP(x) ((x) << S_DMA_WREOPMATCHSOP)
+#define F_DMA_WREOPMATCHSOP    V_DMA_WREOPMATCHSOP(1U)
+
+#define S_DMA_WRSOPCNT    8
+#define M_DMA_WRSOPCNT    0xfU
+#define V_DMA_WRSOPCNT(x) ((x) << S_DMA_WRSOPCNT)
+#define G_DMA_WRSOPCNT(x) (((x) >> S_DMA_WRSOPCNT) & M_DMA_WRSOPCNT)
+
+#define S_DMA_RDSOPCNT    0
+#define M_DMA_RDSOPCNT    0xffU
+#define V_DMA_RDSOPCNT(x) ((x) << S_DMA_RDSOPCNT)
+#define G_DMA_RDSOPCNT(x) (((x) >> S_DMA_RDSOPCNT) & M_DMA_RDSOPCNT)
+
 #define A_PCIE_T5_DMA_STAT3 0x594c
 
 #define S_ATMREQSOPCNT    24
@@ -6372,6 +8026,29 @@
 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
 
+#define S_DMA_ATMREQSOPCNT    24
+#define M_DMA_ATMREQSOPCNT    0xffU
+#define V_DMA_ATMREQSOPCNT(x) ((x) << S_DMA_ATMREQSOPCNT)
+#define G_DMA_ATMREQSOPCNT(x) (((x) >> S_DMA_ATMREQSOPCNT) & M_DMA_ATMREQSOPCNT)
+
+#define S_DMA_ATMEOPMATCHSOP    17
+#define V_DMA_ATMEOPMATCHSOP(x) ((x) << S_DMA_ATMEOPMATCHSOP)
+#define F_DMA_ATMEOPMATCHSOP    V_DMA_ATMEOPMATCHSOP(1U)
+
+#define S_DMA_RSPEOPMATCHSOP    16
+#define V_DMA_RSPEOPMATCHSOP(x) ((x) << S_DMA_RSPEOPMATCHSOP)
+#define F_DMA_RSPEOPMATCHSOP    V_DMA_RSPEOPMATCHSOP(1U)
+
+#define S_DMA_RSPERRCNT    8
+#define M_DMA_RSPERRCNT    0xffU
+#define V_DMA_RSPERRCNT(x) ((x) << S_DMA_RSPERRCNT)
+#define G_DMA_RSPERRCNT(x) (((x) >> S_DMA_RSPERRCNT) & M_DMA_RSPERRCNT)
+
+#define S_DMA_RSPSOPCNT    0
+#define M_DMA_RSPSOPCNT    0xffU
+#define V_DMA_RSPSOPCNT(x) ((x) << S_DMA_RSPSOPCNT)
+#define G_DMA_RSPSOPCNT(x) (((x) >> S_DMA_RSPSOPCNT) & M_DMA_RSPSOPCNT)
+
 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
 
 #define S_OP0H    24
@@ -6507,11 +8184,6 @@
 #define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL)
 #define F_T6_USECMDPOOL    V_T6_USECMDPOOL(1U)
 
-#define S_T6_MINTAG    0
-#define M_T6_MINTAG    0xffU
-#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
-#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
-
 #define A_PCIE_T5_CMD_STAT 0x5984
 
 #define S_T5_STAT_RSPCNT    20
@@ -6558,6 +8230,21 @@
 
 #define A_PCIE_T5_CMD_STAT2 0x5988
 #define A_PCIE_T5_CMD_STAT3 0x598c
+
+#define S_CMD_RSPEOPMATCHSOP    16
+#define V_CMD_RSPEOPMATCHSOP(x) ((x) << S_CMD_RSPEOPMATCHSOP)
+#define F_CMD_RSPEOPMATCHSOP    V_CMD_RSPEOPMATCHSOP(1U)
+
+#define S_CMD_RSPERRCNT    8
+#define M_CMD_RSPERRCNT    0xffU
+#define V_CMD_RSPERRCNT(x) ((x) << S_CMD_RSPERRCNT)
+#define G_CMD_RSPERRCNT(x) (((x) >> S_CMD_RSPERRCNT) & M_CMD_RSPERRCNT)
+
+#define S_CMD_RSPSOPCNT    0
+#define M_CMD_RSPSOPCNT    0xffU
+#define V_CMD_RSPSOPCNT(x) ((x) << S_CMD_RSPSOPCNT)
+#define G_CMD_RSPSOPCNT(x) (((x) >> S_CMD_RSPSOPCNT) & M_CMD_RSPSOPCNT)
+
 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
 
 #define S_OC0T    24
@@ -6868,14 +8555,14 @@
 #define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT)
 #define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT)
 
-#define S_T6_SEQCHKDIS    8
-#define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
-#define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
+#define S_T5_HMA_SEQCHKDIS    8
+#define V_T5_HMA_SEQCHKDIS(x) ((x) << S_T5_HMA_SEQCHKDIS)
+#define F_T5_HMA_SEQCHKDIS    V_T5_HMA_SEQCHKDIS(1U)
 
-#define S_T6_MINTAG    0
-#define M_T6_MINTAG    0xffU
-#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
-#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
+#define S_T5_MINTAG    0
+#define M_T5_MINTAG    0xffU
+#define V_T5_MINTAG(x) ((x) << S_T5_MINTAG)
+#define G_T5_MINTAG(x) (((x) >> S_T5_MINTAG) & M_T5_MINTAG)
 
 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
 
@@ -6992,6 +8679,31 @@
 #define F_CRSI    V_CRSI(1U)
 
 #define A_PCIE_T5_HMA_STAT2 0x59b8
+
+#define S_HMA_COOKIECNT    24
+#define M_HMA_COOKIECNT    0xfU
+#define V_HMA_COOKIECNT(x) ((x) << S_HMA_COOKIECNT)
+#define G_HMA_COOKIECNT(x) (((x) >> S_HMA_COOKIECNT) & M_HMA_COOKIECNT)
+
+#define S_HMA_RDSEQNUMUPDCNT    20
+#define M_HMA_RDSEQNUMUPDCNT    0xfU
+#define V_HMA_RDSEQNUMUPDCNT(x) ((x) << S_HMA_RDSEQNUMUPDCNT)
+#define G_HMA_RDSEQNUMUPDCNT(x) (((x) >> S_HMA_RDSEQNUMUPDCNT) & M_HMA_RDSEQNUMUPDCNT)
+
+#define S_HMA_WREOPMATCHSOP    12
+#define V_HMA_WREOPMATCHSOP(x) ((x) << S_HMA_WREOPMATCHSOP)
+#define F_HMA_WREOPMATCHSOP    V_HMA_WREOPMATCHSOP(1U)
+
+#define S_HMA_WRSOPCNT    8
+#define M_HMA_WRSOPCNT    0xfU
+#define V_HMA_WRSOPCNT(x) ((x) << S_HMA_WRSOPCNT)
+#define G_HMA_WRSOPCNT(x) (((x) >> S_HMA_WRSOPCNT) & M_HMA_WRSOPCNT)
+
+#define S_HMA_RDSOPCNT    0
+#define M_HMA_RDSOPCNT    0xffU
+#define V_HMA_RDSOPCNT(x) ((x) << S_HMA_RDSOPCNT)
+#define G_HMA_RDSOPCNT(x) (((x) >> S_HMA_RDSOPCNT) & M_HMA_RDSOPCNT)
+
 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
 
 #define S_PTOM    31
@@ -7035,6 +8747,21 @@
 #define F_PMC7    V_PMC7(1U)
 
 #define A_PCIE_T5_HMA_STAT3 0x59bc
+
+#define S_HMA_RSPEOPMATCHSOP    16
+#define V_HMA_RSPEOPMATCHSOP(x) ((x) << S_HMA_RSPEOPMATCHSOP)
+#define F_HMA_RSPEOPMATCHSOP    V_HMA_RSPEOPMATCHSOP(1U)
+
+#define S_HMA_RSPERRCNT    8
+#define M_HMA_RSPERRCNT    0xffU
+#define V_HMA_RSPERRCNT(x) ((x) << S_HMA_RSPERRCNT)
+#define G_HMA_RSPERRCNT(x) (((x) >> S_HMA_RSPERRCNT) & M_HMA_RSPERRCNT)
+
+#define S_HMA_RSPSOPCNT    0
+#define M_HMA_RSPSOPCNT    0xffU
+#define V_HMA_RSPSOPCNT(x) ((x) << S_HMA_RSPSOPCNT)
+#define G_HMA_RSPSOPCNT(x) (((x) >> S_HMA_RSPSOPCNT) & M_HMA_RSPSOPCNT)
+
 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
 
 #define S_PTOS    31
@@ -7187,6 +8914,14 @@
 #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
 #define F_STI_SLEEPREQ    V_STI_SLEEPREQ(1U)
 
+#define S_ARM_STATIC_CGEN    28
+#define V_ARM_STATIC_CGEN(x) ((x) << S_ARM_STATIC_CGEN)
+#define F_ARM_STATIC_CGEN    V_ARM_STATIC_CGEN(1U)
+
+#define S_ARM_DYNAMIC_CGEN    27
+#define V_ARM_DYNAMIC_CGEN(x) ((x) << S_ARM_DYNAMIC_CGEN)
+#define F_ARM_DYNAMIC_CGEN    V_ARM_DYNAMIC_CGEN(1U)
+
 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
 
 #define S_PTOI    31
@@ -7521,6 +9256,14 @@
 #define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR)
 #define F_PIOCPL_VDMTXDATAPERR    V_PIOCPL_VDMTXDATAPERR(1U)
 
+#define S_TGT1_MEM_PERR    28
+#define V_TGT1_MEM_PERR(x) ((x) << S_TGT1_MEM_PERR)
+#define F_TGT1_MEM_PERR    V_TGT1_MEM_PERR(1U)
+
+#define S_TGT2_MEM_PERR    27
+#define V_TGT2_MEM_PERR(x) ((x) << S_TGT2_MEM_PERR)
+#define F_TGT2_MEM_PERR    V_TGT2_MEM_PERR(1U)
+
 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
 
@@ -7622,6 +9365,16 @@
 #define V_T6_REQVFID(x) ((x) << S_T6_REQVFID)
 #define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID)
 
+#define S_LOGADDR10B    9
+#define M_LOGADDR10B    0x3ffU
+#define V_LOGADDR10B(x) ((x) << S_LOGADDR10B)
+#define G_LOGADDR10B(x) (((x) >> S_LOGADDR10B) & M_LOGADDR10B)
+
+#define S_LOGREQVFID    0
+#define M_LOGREQVFID    0x1ffU
+#define V_LOGREQVFID(x) ((x) << S_LOGREQVFID)
+#define G_LOGREQVFID(x) (((x) >> S_LOGREQVFID) & M_LOGREQVFID)
+
 #define A_PCIE_CHANGESET 0x59fc
 #define A_PCIE_REVISION 0x5a00
 #define A_PCIE_PDEBUG_INDEX 0x5a04
@@ -7646,6 +9399,16 @@
 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
 
+#define S_T7_1_PDEBUGSELH    16
+#define M_T7_1_PDEBUGSELH    0xffU
+#define V_T7_1_PDEBUGSELH(x) ((x) << S_T7_1_PDEBUGSELH)
+#define G_T7_1_PDEBUGSELH(x) (((x) >> S_T7_1_PDEBUGSELH) & M_T7_1_PDEBUGSELH)
+
+#define S_T7_1_PDEBUGSELL    0
+#define M_T7_1_PDEBUGSELL    0xffU
+#define V_T7_1_PDEBUGSELL(x) ((x) << S_T7_1_PDEBUGSELL)
+#define G_T7_1_PDEBUGSELL(x) (((x) >> S_T7_1_PDEBUGSELL) & M_T7_1_PDEBUGSELL)
+
 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
 #define A_PCIE_CDEBUG_INDEX 0x5a10
@@ -8468,6 +10231,21 @@
 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
 #define A_PCIE_STATIC_SPARE1 0x5bf8
 #define A_PCIE_STATIC_SPARE2 0x5bfc
+
+#define S_X8_SW_EN    30
+#define V_X8_SW_EN(x) ((x) << S_X8_SW_EN)
+#define F_X8_SW_EN    V_X8_SW_EN(1U)
+
+#define S_SWITCHCFG    28
+#define M_SWITCHCFG    0x3U
+#define V_SWITCHCFG(x) ((x) << S_SWITCHCFG)
+#define G_SWITCHCFG(x) (((x) >> S_SWITCHCFG) & M_SWITCHCFG)
+
+#define S_STATIC_SPARE2    0
+#define M_STATIC_SPARE2    0xfffffffU
+#define V_STATIC_SPARE2(x) ((x) << S_STATIC_SPARE2)
+#define G_STATIC_SPARE2(x) (((x) >> S_STATIC_SPARE2) & M_STATIC_SPARE2)
+
 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
 
 #define S_KDB_PF_LEN    24
@@ -8872,9 +10650,13 @@
 #define A_PCIE_FLR_VF6_STATUS 0x5e78
 #define A_PCIE_FLR_VF7_STATUS 0x5e7c
 #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
+#define A_T7_PCIE_BUS_MST_STAT_4 0x5e80
 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
+#define A_T7_PCIE_BUS_MST_STAT_5 0x5e84
 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
+#define A_T7_PCIE_BUS_MST_STAT_6 0x5e88
 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
+#define A_T7_PCIE_BUS_MST_STAT_7 0x5e8c
 #define A_PCIE_BUS_MST_STAT_8 0x5e90
 
 #define S_BUSMST_263_256    0
@@ -8895,9 +10677,13 @@
 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
 
 #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
+#define A_T7_PCIE_RSP_ERR_STAT_4 0x5ea0
 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
+#define A_T7_PCIE_RSP_ERR_STAT_5 0x5ea4
 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
+#define A_T7_PCIE_RSP_ERR_STAT_6 0x5ea8
 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
+#define A_T7_PCIE_RSP_ERR_STAT_7 0x5eac
 #define A_PCIE_RSP_ERR_STAT_8 0x5eb0
 
 #define S_RSPERR_263_256    0
@@ -9025,6 +10811,1028 @@
 #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
+#define A_PCIE_PHY_PGM_LOAD_CTRL 0x5f04
+
+#define S_HSS_PMLD_ACC_EN    31
+#define V_HSS_PMLD_ACC_EN(x) ((x) << S_HSS_PMLD_ACC_EN)
+#define F_HSS_PMLD_ACC_EN    V_HSS_PMLD_ACC_EN(1U)
+
+#define S_HSS_PMRDWR_ADDR    0
+#define M_HSS_PMRDWR_ADDR    0x3ffffU
+#define V_HSS_PMRDWR_ADDR(x) ((x) << S_HSS_PMRDWR_ADDR)
+#define G_HSS_PMRDWR_ADDR(x) (((x) >> S_HSS_PMRDWR_ADDR) & M_HSS_PMRDWR_ADDR)
+
+#define A_PCIE_PHY_PGM_LOAD_DATA 0x5f08
+#define A_PCIE_HSS_CFG 0x5f0c
+
+#define S_HSS_PCS_AGGREGATION_MODE    30
+#define M_HSS_PCS_AGGREGATION_MODE    0x3U
+#define V_HSS_PCS_AGGREGATION_MODE(x) ((x) << S_HSS_PCS_AGGREGATION_MODE)
+#define G_HSS_PCS_AGGREGATION_MODE(x) (((x) >> S_HSS_PCS_AGGREGATION_MODE) & M_HSS_PCS_AGGREGATION_MODE)
+
+#define S_HSS_PCS_FURCATE_MODE    28
+#define M_HSS_PCS_FURCATE_MODE    0x3U
+#define V_HSS_PCS_FURCATE_MODE(x) ((x) << S_HSS_PCS_FURCATE_MODE)
+#define G_HSS_PCS_FURCATE_MODE(x) (((x) >> S_HSS_PCS_FURCATE_MODE) & M_HSS_PCS_FURCATE_MODE)
+
+#define S_HSS_PCS_PCLK_ON_IN_P2    27
+#define V_HSS_PCS_PCLK_ON_IN_P2(x) ((x) << S_HSS_PCS_PCLK_ON_IN_P2)
+#define F_HSS_PCS_PCLK_ON_IN_P2    V_HSS_PCS_PCLK_ON_IN_P2(1U)
+
+#define S_HSS0_PHY_CTRL_REFCLK    17
+#define M_HSS0_PHY_CTRL_REFCLK    0x1fU
+#define V_HSS0_PHY_CTRL_REFCLK(x) ((x) << S_HSS0_PHY_CTRL_REFCLK)
+#define G_HSS0_PHY_CTRL_REFCLK(x) (((x) >> S_HSS0_PHY_CTRL_REFCLK) & M_HSS0_PHY_CTRL_REFCLK)
+
+#define S_HSS1_PHY_CTRL_REFCLK    12
+#define M_HSS1_PHY_CTRL_REFCLK    0x1fU
+#define V_HSS1_PHY_CTRL_REFCLK(x) ((x) << S_HSS1_PHY_CTRL_REFCLK)
+#define G_HSS1_PHY_CTRL_REFCLK(x) (((x) >> S_HSS1_PHY_CTRL_REFCLK) & M_HSS1_PHY_CTRL_REFCLK)
+
+#define S_HSS0_PHY_REXT_MASTER    11
+#define V_HSS0_PHY_REXT_MASTER(x) ((x) << S_HSS0_PHY_REXT_MASTER)
+#define F_HSS0_PHY_REXT_MASTER    V_HSS0_PHY_REXT_MASTER(1U)
+
+#define S_HSS1_PHY_REXT_MASTER    10
+#define V_HSS1_PHY_REXT_MASTER(x) ((x) << S_HSS1_PHY_REXT_MASTER)
+#define F_HSS1_PHY_REXT_MASTER    V_HSS1_PHY_REXT_MASTER(1U)
+
+#define S_HSS0_PHY_CTRL_VDDA_SEL    9
+#define V_HSS0_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDA_SEL)
+#define F_HSS0_PHY_CTRL_VDDA_SEL    V_HSS0_PHY_CTRL_VDDA_SEL(1U)
+
+#define S_HSS0_PHY_CTRL_VDDHA_SEL    8
+#define V_HSS0_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDHA_SEL)
+#define F_HSS0_PHY_CTRL_VDDHA_SEL    V_HSS0_PHY_CTRL_VDDHA_SEL(1U)
+
+#define S_HSS1_PHY_CTRL_VDDA_SEL    7
+#define V_HSS1_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDA_SEL)
+#define F_HSS1_PHY_CTRL_VDDA_SEL    V_HSS1_PHY_CTRL_VDDA_SEL(1U)
+
+#define S_HSS1_PHY_CTRL_VDDHA_SEL    6
+#define V_HSS1_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDHA_SEL)
+#define F_HSS1_PHY_CTRL_VDDHA_SEL    V_HSS1_PHY_CTRL_VDDHA_SEL(1U)
+
+#define S_HSS1_CPU_MEMPSACK    5
+#define V_HSS1_CPU_MEMPSACK(x) ((x) << S_HSS1_CPU_MEMPSACK)
+#define F_HSS1_CPU_MEMPSACK    V_HSS1_CPU_MEMPSACK(1U)
+
+#define S_HSS0_CPU_MEMPSACK    3
+#define V_HSS0_CPU_MEMPSACK(x) ((x) << S_HSS0_CPU_MEMPSACK)
+#define F_HSS0_CPU_MEMPSACK    V_HSS0_CPU_MEMPSACK(1U)
+
+#define S_HSS1_CPU_MEMACK    4
+#define V_HSS1_CPU_MEMACK(x) ((x) << S_HSS1_CPU_MEMACK)
+#define F_HSS1_CPU_MEMACK    V_HSS1_CPU_MEMACK(1U)
+
+#define S_HSS0_CPU_MEMACK    2
+#define V_HSS0_CPU_MEMACK(x) ((x) << S_HSS0_CPU_MEMACK)
+#define F_HSS0_CPU_MEMACK    V_HSS0_CPU_MEMACK(1U)
+
+#define S_HSS_PM_IS_ROM    1
+#define V_HSS_PM_IS_ROM(x) ((x) << S_HSS_PM_IS_ROM)
+#define F_HSS_PM_IS_ROM    V_HSS_PM_IS_ROM(1U)
+
+#define A_PCIE_HSS_RST 0x5f10
+
+#define S_HSS_RST_CTRL_BY_FW    31
+#define V_HSS_RST_CTRL_BY_FW(x) ((x) << S_HSS_RST_CTRL_BY_FW)
+#define F_HSS_RST_CTRL_BY_FW    V_HSS_RST_CTRL_BY_FW(1U)
+
+#define S_HSS_PIPE0_RESET_N    30
+#define V_HSS_PIPE0_RESET_N(x) ((x) << S_HSS_PIPE0_RESET_N)
+#define F_HSS_PIPE0_RESET_N    V_HSS_PIPE0_RESET_N(1U)
+
+#define S_HSS0_POR_N    29
+#define V_HSS0_POR_N(x) ((x) << S_HSS0_POR_N)
+#define F_HSS0_POR_N    V_HSS0_POR_N(1U)
+
+#define S_HSS1_POR_N    28
+#define V_HSS1_POR_N(x) ((x) << S_HSS1_POR_N)
+#define F_HSS1_POR_N    V_HSS1_POR_N(1U)
+
+#define S_HSS0_CPU_RESET    27
+#define V_HSS0_CPU_RESET(x) ((x) << S_HSS0_CPU_RESET)
+#define F_HSS0_CPU_RESET    V_HSS0_CPU_RESET(1U)
+
+#define S_HSS1_CPU_RESET    26
+#define V_HSS1_CPU_RESET(x) ((x) << S_HSS1_CPU_RESET)
+#define F_HSS1_CPU_RESET    V_HSS1_CPU_RESET(1U)
+
+#define S_HSS_PCS_POR_N    25
+#define V_HSS_PCS_POR_N(x) ((x) << S_HSS_PCS_POR_N)
+#define F_HSS_PCS_POR_N    V_HSS_PCS_POR_N(1U)
+
+#define S_SW_CRST_    24
+#define V_SW_CRST_(x) ((x) << S_SW_CRST_)
+#define F_SW_CRST_    V_SW_CRST_(1U)
+
+#define S_SW_PCIECRST_    23
+#define V_SW_PCIECRST_(x) ((x) << S_SW_PCIECRST_)
+#define F_SW_PCIECRST_    V_SW_PCIECRST_(1U)
+
+#define S_SW_PCIEPIPERST_    22
+#define V_SW_PCIEPIPERST_(x) ((x) << S_SW_PCIEPIPERST_)
+#define F_SW_PCIEPIPERST_    V_SW_PCIEPIPERST_(1U)
+
+#define S_SW_PCIEPHYRST_    21
+#define V_SW_PCIEPHYRST_(x) ((x) << S_SW_PCIEPHYRST_)
+#define F_SW_PCIEPHYRST_    V_SW_PCIEPHYRST_(1U)
+
+#define S_HSS1_ERR_O    3
+#define V_HSS1_ERR_O(x) ((x) << S_HSS1_ERR_O)
+#define F_HSS1_ERR_O    V_HSS1_ERR_O(1U)
+
+#define S_HSS0_ERR_O    2
+#define V_HSS0_ERR_O(x) ((x) << S_HSS0_ERR_O)
+#define F_HSS0_ERR_O    V_HSS0_ERR_O(1U)
+
+#define S_HSS1_PLL_LOCK    1
+#define V_HSS1_PLL_LOCK(x) ((x) << S_HSS1_PLL_LOCK)
+#define F_HSS1_PLL_LOCK    V_HSS1_PLL_LOCK(1U)
+
+#define S_HSS0_PLL_LOCK    0
+#define V_HSS0_PLL_LOCK(x) ((x) << S_HSS0_PLL_LOCK)
+#define F_HSS0_PLL_LOCK    V_HSS0_PLL_LOCK(1U)
+
+#define A_PCIE_T5_ARM_CFG 0x5f20
+
+#define S_T5_ARM_MAXREQCNT    20
+#define M_T5_ARM_MAXREQCNT    0x7fU
+#define V_T5_ARM_MAXREQCNT(x) ((x) << S_T5_ARM_MAXREQCNT)
+#define G_T5_ARM_MAXREQCNT(x) (((x) >> S_T5_ARM_MAXREQCNT) & M_T5_ARM_MAXREQCNT)
+
+#define S_T5_ARM_MAXRDREQSIZE    17
+#define M_T5_ARM_MAXRDREQSIZE    0x7U
+#define V_T5_ARM_MAXRDREQSIZE(x) ((x) << S_T5_ARM_MAXRDREQSIZE)
+#define G_T5_ARM_MAXRDREQSIZE(x) (((x) >> S_T5_ARM_MAXRDREQSIZE) & M_T5_ARM_MAXRDREQSIZE)
+
+#define S_T5_ARM_MAXRSPCNT    9
+#define M_T5_ARM_MAXRSPCNT    0xffU
+#define V_T5_ARM_MAXRSPCNT(x) ((x) << S_T5_ARM_MAXRSPCNT)
+#define G_T5_ARM_MAXRSPCNT(x) (((x) >> S_T5_ARM_MAXRSPCNT) & M_T5_ARM_MAXRSPCNT)
+
+#define A_PCIE_T5_ARM_STAT 0x5f24
+
+#define S_ARM_RESPCNT    20
+#define M_ARM_RESPCNT    0x1ffU
+#define V_ARM_RESPCNT(x) ((x) << S_ARM_RESPCNT)
+#define G_ARM_RESPCNT(x) (((x) >> S_ARM_RESPCNT) & M_ARM_RESPCNT)
+
+#define S_ARM_RDREQCNT    12
+#define M_ARM_RDREQCNT    0x3fU
+#define V_ARM_RDREQCNT(x) ((x) << S_ARM_RDREQCNT)
+#define G_ARM_RDREQCNT(x) (((x) >> S_ARM_RDREQCNT) & M_ARM_RDREQCNT)
+
+#define S_ARM_WRREQCNT    0
+#define M_ARM_WRREQCNT    0x1ffU
+#define V_ARM_WRREQCNT(x) ((x) << S_ARM_WRREQCNT)
+#define G_ARM_WRREQCNT(x) (((x) >> S_ARM_WRREQCNT) & M_ARM_WRREQCNT)
+
+#define A_PCIE_T5_ARM_STAT2 0x5f28
+
+#define S_ARM_COOKIECNT    24
+#define M_ARM_COOKIECNT    0xfU
+#define V_ARM_COOKIECNT(x) ((x) << S_ARM_COOKIECNT)
+#define G_ARM_COOKIECNT(x) (((x) >> S_ARM_COOKIECNT) & M_ARM_COOKIECNT)
+
+#define S_ARM_RDSEQNUMUPDCNT    20
+#define M_ARM_RDSEQNUMUPDCNT    0xfU
+#define V_ARM_RDSEQNUMUPDCNT(x) ((x) << S_ARM_RDSEQNUMUPDCNT)
+#define G_ARM_RDSEQNUMUPDCNT(x) (((x) >> S_ARM_RDSEQNUMUPDCNT) & M_ARM_RDSEQNUMUPDCNT)
+
+#define S_ARM_SIREQCNT    16
+#define M_ARM_SIREQCNT    0xfU
+#define V_ARM_SIREQCNT(x) ((x) << S_ARM_SIREQCNT)
+#define G_ARM_SIREQCNT(x) (((x) >> S_ARM_SIREQCNT) & M_ARM_SIREQCNT)
+
+#define S_ARM_WREOPMATCHSOP    12
+#define V_ARM_WREOPMATCHSOP(x) ((x) << S_ARM_WREOPMATCHSOP)
+#define F_ARM_WREOPMATCHSOP    V_ARM_WREOPMATCHSOP(1U)
+
+#define S_ARM_WRSOPCNT    8
+#define M_ARM_WRSOPCNT    0xfU
+#define V_ARM_WRSOPCNT(x) ((x) << S_ARM_WRSOPCNT)
+#define G_ARM_WRSOPCNT(x) (((x) >> S_ARM_WRSOPCNT) & M_ARM_WRSOPCNT)
+
+#define S_ARM_RDSOPCNT    0
+#define M_ARM_RDSOPCNT    0xffU
+#define V_ARM_RDSOPCNT(x) ((x) << S_ARM_RDSOPCNT)
+#define G_ARM_RDSOPCNT(x) (((x) >> S_ARM_RDSOPCNT) & M_ARM_RDSOPCNT)
+
+#define A_PCIE_T5_ARM_STAT3 0x5f2c
+
+#define S_ARM_ATMREQSOPCNT    24
+#define M_ARM_ATMREQSOPCNT    0xffU
+#define V_ARM_ATMREQSOPCNT(x) ((x) << S_ARM_ATMREQSOPCNT)
+#define G_ARM_ATMREQSOPCNT(x) (((x) >> S_ARM_ATMREQSOPCNT) & M_ARM_ATMREQSOPCNT)
+
+#define S_ARM_ATMEOPMATCHSOP    17
+#define V_ARM_ATMEOPMATCHSOP(x) ((x) << S_ARM_ATMEOPMATCHSOP)
+#define F_ARM_ATMEOPMATCHSOP    V_ARM_ATMEOPMATCHSOP(1U)
+
+#define S_ARM_RSPEOPMATCHSOP    16
+#define V_ARM_RSPEOPMATCHSOP(x) ((x) << S_ARM_RSPEOPMATCHSOP)
+#define F_ARM_RSPEOPMATCHSOP    V_ARM_RSPEOPMATCHSOP(1U)
+
+#define S_ARM_RSPERRCNT    8
+#define M_ARM_RSPERRCNT    0xffU
+#define V_ARM_RSPERRCNT(x) ((x) << S_ARM_RSPERRCNT)
+#define G_ARM_RSPERRCNT(x) (((x) >> S_ARM_RSPERRCNT) & M_ARM_RSPERRCNT)
+
+#define S_ARM_RSPSOPCNT    0
+#define M_ARM_RSPSOPCNT    0xffU
+#define V_ARM_RSPSOPCNT(x) ((x) << S_ARM_RSPSOPCNT)
+#define G_ARM_RSPSOPCNT(x) (((x) >> S_ARM_RSPSOPCNT) & M_ARM_RSPSOPCNT)
+
+#define A_PCIE_ARM_REQUESTER_ID 0x5f30
+
+#define S_A0_RSVD1    24
+#define M_A0_RSVD1    0xffU
+#define V_A0_RSVD1(x) ((x) << S_A0_RSVD1)
+#define G_A0_RSVD1(x) (((x) >> S_A0_RSVD1) & M_A0_RSVD1)
+
+#define S_A0_PRIMBUSNUMBER    16
+#define M_A0_PRIMBUSNUMBER    0xffU
+#define V_A0_PRIMBUSNUMBER(x) ((x) << S_A0_PRIMBUSNUMBER)
+#define G_A0_PRIMBUSNUMBER(x) (((x) >> S_A0_PRIMBUSNUMBER) & M_A0_PRIMBUSNUMBER)
+
+#define S_A0_REQUESTERID    0
+#define M_A0_REQUESTERID    0xffffU
+#define V_A0_REQUESTERID(x) ((x) << S_A0_REQUESTERID)
+#define G_A0_REQUESTERID(x) (((x) >> S_A0_REQUESTERID) & M_A0_REQUESTERID)
+
+#define A_PCIE_SWITCH_CFG_SPACE_REQ0 0x5f34
+
+#define S_REQ0ENABLE    31
+#define V_REQ0ENABLE(x) ((x) << S_REQ0ENABLE)
+#define F_REQ0ENABLE    V_REQ0ENABLE(1U)
+
+#define S_RDREQ0TYPE    19
+#define V_RDREQ0TYPE(x) ((x) << S_RDREQ0TYPE)
+#define F_RDREQ0TYPE    V_RDREQ0TYPE(1U)
+
+#define S_BYTEENABLE0    15
+#define M_BYTEENABLE0    0xfU
+#define V_BYTEENABLE0(x) ((x) << S_BYTEENABLE0)
+#define G_BYTEENABLE0(x) (((x) >> S_BYTEENABLE0) & M_BYTEENABLE0)
+
+#define S_REGADDR0    0
+#define M_REGADDR0    0x7fffU
+#define V_REGADDR0(x) ((x) << S_REGADDR0)
+#define G_REGADDR0(x) (((x) >> S_REGADDR0) & M_REGADDR0)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA0 0x5f38
+#define A_PCIE_SWITCH_CFG_SPACE_REQ1 0x5f3c
+
+#define S_REQ1ENABLE    31
+#define V_REQ1ENABLE(x) ((x) << S_REQ1ENABLE)
+#define F_REQ1ENABLE    V_REQ1ENABLE(1U)
+
+#define S_RDREQ1TYPE    26
+#define M_RDREQ1TYPE    0xfU
+#define V_RDREQ1TYPE(x) ((x) << S_RDREQ1TYPE)
+#define G_RDREQ1TYPE(x) (((x) >> S_RDREQ1TYPE) & M_RDREQ1TYPE)
+
+#define S_BYTEENABLE1    15
+#define M_BYTEENABLE1    0x7ffU
+#define V_BYTEENABLE1(x) ((x) << S_BYTEENABLE1)
+#define G_BYTEENABLE1(x) (((x) >> S_BYTEENABLE1) & M_BYTEENABLE1)
+
+#define S_REGADDR1    0
+#define M_REGADDR1    0x7fffU
+#define V_REGADDR1(x) ((x) << S_REGADDR1)
+#define G_REGADDR1(x) (((x) >> S_REGADDR1) & M_REGADDR1)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA1 0x5f40
+#define A_PCIE_SWITCH_CFG_SPACE_REQ2 0x5f44
+
+#define S_REQ2ENABLE    31
+#define V_REQ2ENABLE(x) ((x) << S_REQ2ENABLE)
+#define F_REQ2ENABLE    V_REQ2ENABLE(1U)
+
+#define S_RDREQ2TYPE    26
+#define M_RDREQ2TYPE    0xfU
+#define V_RDREQ2TYPE(x) ((x) << S_RDREQ2TYPE)
+#define G_RDREQ2TYPE(x) (((x) >> S_RDREQ2TYPE) & M_RDREQ2TYPE)
+
+#define S_BYTEENABLE2    15
+#define M_BYTEENABLE2    0x7ffU
+#define V_BYTEENABLE2(x) ((x) << S_BYTEENABLE2)
+#define G_BYTEENABLE2(x) (((x) >> S_BYTEENABLE2) & M_BYTEENABLE2)
+
+#define S_REGADDR2    0
+#define M_REGADDR2    0x7fffU
+#define V_REGADDR2(x) ((x) << S_REGADDR2)
+#define G_REGADDR2(x) (((x) >> S_REGADDR2) & M_REGADDR2)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA2 0x5f48
+#define A_PCIE_SWITCH_CFG_SPACE_REQ3 0x5f4c
+
+#define S_REQ3ENABLE    31
+#define V_REQ3ENABLE(x) ((x) << S_REQ3ENABLE)
+#define F_REQ3ENABLE    V_REQ3ENABLE(1U)
+
+#define S_RDREQ3TYPE    26
+#define M_RDREQ3TYPE    0xfU
+#define V_RDREQ3TYPE(x) ((x) << S_RDREQ3TYPE)
+#define G_RDREQ3TYPE(x) (((x) >> S_RDREQ3TYPE) & M_RDREQ3TYPE)
+
+#define S_BYTEENABLE3    15
+#define M_BYTEENABLE3    0x7ffU
+#define V_BYTEENABLE3(x) ((x) << S_BYTEENABLE3)
+#define G_BYTEENABLE3(x) (((x) >> S_BYTEENABLE3) & M_BYTEENABLE3)
+
+#define S_REGADDR3    0
+#define M_REGADDR3    0x7fffU
+#define V_REGADDR3(x) ((x) << S_REGADDR3)
+#define G_REGADDR3(x) (((x) >> S_REGADDR3) & M_REGADDR3)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA3 0x5f50
+#define A_PCIE_SWITCH_CFG_SPACE_REQ4 0x5f54
+
+#define S_REQ4ENABLE    31
+#define V_REQ4ENABLE(x) ((x) << S_REQ4ENABLE)
+#define F_REQ4ENABLE    V_REQ4ENABLE(1U)
+
+#define S_RDREQ4TYPE    26
+#define M_RDREQ4TYPE    0xfU
+#define V_RDREQ4TYPE(x) ((x) << S_RDREQ4TYPE)
+#define G_RDREQ4TYPE(x) (((x) >> S_RDREQ4TYPE) & M_RDREQ4TYPE)
+
+#define S_BYTEENABLE4    15
+#define M_BYTEENABLE4    0x7ffU
+#define V_BYTEENABLE4(x) ((x) << S_BYTEENABLE4)
+#define G_BYTEENABLE4(x) (((x) >> S_BYTEENABLE4) & M_BYTEENABLE4)
+
+#define S_REGADDR4    0
+#define M_REGADDR4    0x7fffU
+#define V_REGADDR4(x) ((x) << S_REGADDR4)
+#define G_REGADDR4(x) (((x) >> S_REGADDR4) & M_REGADDR4)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA4 0x5f58
+#define A_PCIE_SWITCH_CFG_SPACE_REQ5 0x5f5c
+
+#define S_REQ5ENABLE    31
+#define V_REQ5ENABLE(x) ((x) << S_REQ5ENABLE)
+#define F_REQ5ENABLE    V_REQ5ENABLE(1U)
+
+#define S_RDREQ5TYPE    26
+#define M_RDREQ5TYPE    0xfU
+#define V_RDREQ5TYPE(x) ((x) << S_RDREQ5TYPE)
+#define G_RDREQ5TYPE(x) (((x) >> S_RDREQ5TYPE) & M_RDREQ5TYPE)
+
+#define S_BYTEENABLE5    15
+#define M_BYTEENABLE5    0x7ffU
+#define V_BYTEENABLE5(x) ((x) << S_BYTEENABLE5)
+#define G_BYTEENABLE5(x) (((x) >> S_BYTEENABLE5) & M_BYTEENABLE5)
+
+#define S_REGADDR5    0
+#define M_REGADDR5    0x7fffU
+#define V_REGADDR5(x) ((x) << S_REGADDR5)
+#define G_REGADDR5(x) (((x) >> S_REGADDR5) & M_REGADDR5)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA5 0x5f60
+#define A_PCIE_SWITCH_CFG_SPACE_REQ6 0x5f64
+
+#define S_REQ6ENABLE    31
+#define V_REQ6ENABLE(x) ((x) << S_REQ6ENABLE)
+#define F_REQ6ENABLE    V_REQ6ENABLE(1U)
+
+#define S_RDREQ6TYPE    26
+#define M_RDREQ6TYPE    0xfU
+#define V_RDREQ6TYPE(x) ((x) << S_RDREQ6TYPE)
+#define G_RDREQ6TYPE(x) (((x) >> S_RDREQ6TYPE) & M_RDREQ6TYPE)
+
+#define S_BYTEENABLE6    15
+#define M_BYTEENABLE6    0x7ffU
+#define V_BYTEENABLE6(x) ((x) << S_BYTEENABLE6)
+#define G_BYTEENABLE6(x) (((x) >> S_BYTEENABLE6) & M_BYTEENABLE6)
+
+#define S_REGADDR6    0
+#define M_REGADDR6    0x7fffU
+#define V_REGADDR6(x) ((x) << S_REGADDR6)
+#define G_REGADDR6(x) (((x) >> S_REGADDR6) & M_REGADDR6)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA6 0x5f68
+#define A_PCIE_SWITCH_CFG_SPACE_REQ7 0x5f6c
+
+#define S_REQ7ENABLE    31
+#define V_REQ7ENABLE(x) ((x) << S_REQ7ENABLE)
+#define F_REQ7ENABLE    V_REQ7ENABLE(1U)
+
+#define S_RDREQ7TYPE    26
+#define M_RDREQ7TYPE    0xfU
+#define V_RDREQ7TYPE(x) ((x) << S_RDREQ7TYPE)
+#define G_RDREQ7TYPE(x) (((x) >> S_RDREQ7TYPE) & M_RDREQ7TYPE)
+
+#define S_BYTEENABLE7    15
+#define M_BYTEENABLE7    0x7ffU
+#define V_BYTEENABLE7(x) ((x) << S_BYTEENABLE7)
+#define G_BYTEENABLE7(x) (((x) >> S_BYTEENABLE7) & M_BYTEENABLE7)
+
+#define S_REGADDR7    0
+#define M_REGADDR7    0x7fffU
+#define V_REGADDR7(x) ((x) << S_REGADDR7)
+#define G_REGADDR7(x) (((x) >> S_REGADDR7) & M_REGADDR7)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA7 0x5f70
+#define A_PCIE_SWITCH_CFG_SPACE_REQ8 0x5f74
+
+#define S_REQ8ENABLE    31
+#define V_REQ8ENABLE(x) ((x) << S_REQ8ENABLE)
+#define F_REQ8ENABLE    V_REQ8ENABLE(1U)
+
+#define S_RDREQ8TYPE    26
+#define M_RDREQ8TYPE    0xfU
+#define V_RDREQ8TYPE(x) ((x) << S_RDREQ8TYPE)
+#define G_RDREQ8TYPE(x) (((x) >> S_RDREQ8TYPE) & M_RDREQ8TYPE)
+
+#define S_BYTEENABLE8    15
+#define M_BYTEENABLE8    0x7ffU
+#define V_BYTEENABLE8(x) ((x) << S_BYTEENABLE8)
+#define G_BYTEENABLE8(x) (((x) >> S_BYTEENABLE8) & M_BYTEENABLE8)
+
+#define S_REGADDR8    0
+#define M_REGADDR8    0x7fffU
+#define V_REGADDR8(x) ((x) << S_REGADDR8)
+#define G_REGADDR8(x) (((x) >> S_REGADDR8) & M_REGADDR8)
+
+#define A_PCIE_SWITCH_CFG_SPACE_DATA8 0x5f78
+#define A_PCIE_SNPS_G5_PHY_CR_REQ 0x5f7c
+
+#define S_REGSEL    31
+#define V_REGSEL(x) ((x) << S_REGSEL)
+#define F_REGSEL    V_REGSEL(1U)
+
+#define S_RDENABLE    30
+#define V_RDENABLE(x) ((x) << S_RDENABLE)
+#define F_RDENABLE    V_RDENABLE(1U)
+
+#define S_WRENABLE    29
+#define V_WRENABLE(x) ((x) << S_WRENABLE)
+#define F_WRENABLE    V_WRENABLE(1U)
+
+#define S_AUTOINCRVAL    21
+#define M_AUTOINCRVAL    0x3U
+#define V_AUTOINCRVAL(x) ((x) << S_AUTOINCRVAL)
+#define G_AUTOINCRVAL(x) (((x) >> S_AUTOINCRVAL) & M_AUTOINCRVAL)
+
+#define S_AUTOINCR    20
+#define V_AUTOINCR(x) ((x) << S_AUTOINCR)
+#define F_AUTOINCR    V_AUTOINCR(1U)
+
+#define S_PHYSEL    16
+#define M_PHYSEL    0xfU
+#define V_PHYSEL(x) ((x) << S_PHYSEL)
+#define G_PHYSEL(x) (((x) >> S_PHYSEL) & M_PHYSEL)
+
+#define S_T7_REGADDR    0
+#define M_T7_REGADDR    0xffffU
+#define V_T7_REGADDR(x) ((x) << S_T7_REGADDR)
+#define G_T7_REGADDR(x) (((x) >> S_T7_REGADDR) & M_T7_REGADDR)
+
+#define A_PCIE_SNPS_G5_PHY_CR_DATA 0x5f80
+#define A_PCIE_SNPS_G5_PHY_SRAM_CFG 0x5f84
+
+#define S_PHY3_SRAM_BOOTLOAD_BYPASS    27
+#define V_PHY3_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY3_SRAM_BOOTLOAD_BYPASS)
+#define F_PHY3_SRAM_BOOTLOAD_BYPASS    V_PHY3_SRAM_BOOTLOAD_BYPASS(1U)
+
+#define S_PHY3_SRAM_BYPASS    26
+#define V_PHY3_SRAM_BYPASS(x) ((x) << S_PHY3_SRAM_BYPASS)
+#define F_PHY3_SRAM_BYPASS    V_PHY3_SRAM_BYPASS(1U)
+
+#define S_PHY3_SRAM_ECC_EN    25
+#define V_PHY3_SRAM_ECC_EN(x) ((x) << S_PHY3_SRAM_ECC_EN)
+#define F_PHY3_SRAM_ECC_EN    V_PHY3_SRAM_ECC_EN(1U)
+
+#define S_PHY3_SRAM_EXT_LD_DONE    24
+#define V_PHY3_SRAM_EXT_LD_DONE(x) ((x) << S_PHY3_SRAM_EXT_LD_DONE)
+#define F_PHY3_SRAM_EXT_LD_DONE    V_PHY3_SRAM_EXT_LD_DONE(1U)
+
+#define S_PHY2_SRAM_BOOTLOAD_BYPASS    19
+#define V_PHY2_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY2_SRAM_BOOTLOAD_BYPASS)
+#define F_PHY2_SRAM_BOOTLOAD_BYPASS    V_PHY2_SRAM_BOOTLOAD_BYPASS(1U)
+
+#define S_PHY2_SRAM_BYPASS    18
+#define V_PHY2_SRAM_BYPASS(x) ((x) << S_PHY2_SRAM_BYPASS)
+#define F_PHY2_SRAM_BYPASS    V_PHY2_SRAM_BYPASS(1U)
+
+#define S_PHY2_SRAM_ECC_EN    17
+#define V_PHY2_SRAM_ECC_EN(x) ((x) << S_PHY2_SRAM_ECC_EN)
+#define F_PHY2_SRAM_ECC_EN    V_PHY2_SRAM_ECC_EN(1U)
+
+#define S_PHY2_SRAM_EXT_LD_DONE    16
+#define V_PHY2_SRAM_EXT_LD_DONE(x) ((x) << S_PHY2_SRAM_EXT_LD_DONE)
+#define F_PHY2_SRAM_EXT_LD_DONE    V_PHY2_SRAM_EXT_LD_DONE(1U)
+
+#define S_PHY1_SRAM_BOOTLOAD_BYPASS    11
+#define V_PHY1_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY1_SRAM_BOOTLOAD_BYPASS)
+#define F_PHY1_SRAM_BOOTLOAD_BYPASS    V_PHY1_SRAM_BOOTLOAD_BYPASS(1U)
+
+#define S_PHY1_SRAM_BYPASS    10
+#define V_PHY1_SRAM_BYPASS(x) ((x) << S_PHY1_SRAM_BYPASS)
+#define F_PHY1_SRAM_BYPASS    V_PHY1_SRAM_BYPASS(1U)
+
+#define S_PHY1_SRAM_ECC_EN    9
+#define V_PHY1_SRAM_ECC_EN(x) ((x) << S_PHY1_SRAM_ECC_EN)
+#define F_PHY1_SRAM_ECC_EN    V_PHY1_SRAM_ECC_EN(1U)
+
+#define S_PHY1_SRAM_EXT_LD_DONE    8
+#define V_PHY1_SRAM_EXT_LD_DONE(x) ((x) << S_PHY1_SRAM_EXT_LD_DONE)
+#define F_PHY1_SRAM_EXT_LD_DONE    V_PHY1_SRAM_EXT_LD_DONE(1U)
+
+#define S_PHY_CR_PARA_SEL    4
+#define M_PHY_CR_PARA_SEL    0xfU
+#define V_PHY_CR_PARA_SEL(x) ((x) << S_PHY_CR_PARA_SEL)
+#define G_PHY_CR_PARA_SEL(x) (((x) >> S_PHY_CR_PARA_SEL) & M_PHY_CR_PARA_SEL)
+
+#define S_PHY0_SRAM_BOOTLOAD_BYPASS    3
+#define V_PHY0_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY0_SRAM_BOOTLOAD_BYPASS)
+#define F_PHY0_SRAM_BOOTLOAD_BYPASS    V_PHY0_SRAM_BOOTLOAD_BYPASS(1U)
+
+#define S_PHY0_SRAM_BYPASS    2
+#define V_PHY0_SRAM_BYPASS(x) ((x) << S_PHY0_SRAM_BYPASS)
+#define F_PHY0_SRAM_BYPASS    V_PHY0_SRAM_BYPASS(1U)
+
+#define S_PHY0_SRAM_ECC_EN    1
+#define V_PHY0_SRAM_ECC_EN(x) ((x) << S_PHY0_SRAM_ECC_EN)
+#define F_PHY0_SRAM_ECC_EN    V_PHY0_SRAM_ECC_EN(1U)
+
+#define S_PHY0_SRAM_EXT_LD_DONE    0
+#define V_PHY0_SRAM_EXT_LD_DONE(x) ((x) << S_PHY0_SRAM_EXT_LD_DONE)
+#define F_PHY0_SRAM_EXT_LD_DONE    V_PHY0_SRAM_EXT_LD_DONE(1U)
+
+#define A_PCIE_SNPS_G5_PHY_SRAM_STS 0x5f88
+
+#define S_PHY3_SRAM_INIT_DONE    3
+#define V_PHY3_SRAM_INIT_DONE(x) ((x) << S_PHY3_SRAM_INIT_DONE)
+#define F_PHY3_SRAM_INIT_DONE    V_PHY3_SRAM_INIT_DONE(1U)
+
+#define S_PHY2_SRAM_INIT_DONE    2
+#define V_PHY2_SRAM_INIT_DONE(x) ((x) << S_PHY2_SRAM_INIT_DONE)
+#define F_PHY2_SRAM_INIT_DONE    V_PHY2_SRAM_INIT_DONE(1U)
+
+#define S_PHY1_SRAM_INIT_DONE    1
+#define V_PHY1_SRAM_INIT_DONE(x) ((x) << S_PHY1_SRAM_INIT_DONE)
+#define F_PHY1_SRAM_INIT_DONE    V_PHY1_SRAM_INIT_DONE(1U)
+
+#define S_PHY0_SRAM_INIT_DONE    0
+#define V_PHY0_SRAM_INIT_DONE(x) ((x) << S_PHY0_SRAM_INIT_DONE)
+#define F_PHY0_SRAM_INIT_DONE    V_PHY0_SRAM_INIT_DONE(1U)
+
+#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_TO_3 0x5f90
+#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_DATA 0x5f94
+#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_1_DATA 0x5f98
+#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_2_DATA 0x5f9c
+#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_3_DATA 0x5fa0
+#define A_PCIE_SNPS_G5_PHY_DEFAULTS 0x5fa4
+#define A_PCIE_SNPS_G5_PHY_0_VALUES 0x5fa8
+
+#define S_RX_TERM_OFFSET    28
+#define V_RX_TERM_OFFSET(x) ((x) << S_RX_TERM_OFFSET)
+#define F_RX_TERM_OFFSET    V_RX_TERM_OFFSET(1U)
+
+#define S_REFB_RAW_CLK_DIV2_EN    27
+#define V_REFB_RAW_CLK_DIV2_EN(x) ((x) << S_REFB_RAW_CLK_DIV2_EN)
+#define F_REFB_RAW_CLK_DIV2_EN    V_REFB_RAW_CLK_DIV2_EN(1U)
+
+#define S_REFB_RANGE    23
+#define M_REFB_RANGE    0xfU
+#define V_REFB_RANGE(x) ((x) << S_REFB_RANGE)
+#define G_REFB_RANGE(x) (((x) >> S_REFB_RANGE) & M_REFB_RANGE)
+
+#define S_REFB_LANE_CLK_EN    22
+#define V_REFB_LANE_CLK_EN(x) ((x) << S_REFB_LANE_CLK_EN)
+#define F_REFB_LANE_CLK_EN    V_REFB_LANE_CLK_EN(1U)
+
+#define S_REFB_CLK_DIV2_EN    21
+#define V_REFB_CLK_DIV2_EN(x) ((x) << S_REFB_CLK_DIV2_EN)
+#define F_REFB_CLK_DIV2_EN    V_REFB_CLK_DIV2_EN(1U)
+
+#define S_REFA_RAW_CLK_DIV2_EN    20
+#define V_REFA_RAW_CLK_DIV2_EN(x) ((x) << S_REFA_RAW_CLK_DIV2_EN)
+#define F_REFA_RAW_CLK_DIV2_EN    V_REFA_RAW_CLK_DIV2_EN(1U)
+
+#define S_REFA_RANGE    16
+#define M_REFA_RANGE    0xfU
+#define V_REFA_RANGE(x) ((x) << S_REFA_RANGE)
+#define G_REFA_RANGE(x) (((x) >> S_REFA_RANGE) & M_REFA_RANGE)
+
+#define S_REFA_LANE_CLK_EN    15
+#define V_REFA_LANE_CLK_EN(x) ((x) << S_REFA_LANE_CLK_EN)
+#define F_REFA_LANE_CLK_EN    V_REFA_LANE_CLK_EN(1U)
+
+#define S_REFA_CLK_DIV2_EN    14
+#define V_REFA_CLK_DIV2_EN(x) ((x) << S_REFA_CLK_DIV2_EN)
+#define F_REFA_CLK_DIV2_EN    V_REFA_CLK_DIV2_EN(1U)
+
+#define S_NOMINAL_VPH_SEL    10
+#define M_NOMINAL_VPH_SEL    0x3U
+#define V_NOMINAL_VPH_SEL(x) ((x) << S_NOMINAL_VPH_SEL)
+#define G_NOMINAL_VPH_SEL(x) (((x) >> S_NOMINAL_VPH_SEL) & M_NOMINAL_VPH_SEL)
+
+#define S_NOMINAL_VP_SEL    8
+#define M_NOMINAL_VP_SEL    0x3U
+#define V_NOMINAL_VP_SEL(x) ((x) << S_NOMINAL_VP_SEL)
+#define G_NOMINAL_VP_SEL(x) (((x) >> S_NOMINAL_VP_SEL) & M_NOMINAL_VP_SEL)
+
+#define S_MPLLB_WORD_CLK_EN    7
+#define V_MPLLB_WORD_CLK_EN(x) ((x) << S_MPLLB_WORD_CLK_EN)
+#define F_MPLLB_WORD_CLK_EN    V_MPLLB_WORD_CLK_EN(1U)
+
+#define S_MPLLB_SSC_EN    6
+#define V_MPLLB_SSC_EN(x) ((x) << S_MPLLB_SSC_EN)
+#define F_MPLLB_SSC_EN    V_MPLLB_SSC_EN(1U)
+
+#define S_MPLLB_SHORT_LOCK_EN    5
+#define V_MPLLB_SHORT_LOCK_EN(x) ((x) << S_MPLLB_SHORT_LOCK_EN)
+#define F_MPLLB_SHORT_LOCK_EN    V_MPLLB_SHORT_LOCK_EN(1U)
+
+#define S_MPLLB_FORCE_EN    4
+#define V_MPLLB_FORCE_EN(x) ((x) << S_MPLLB_FORCE_EN)
+#define F_MPLLB_FORCE_EN    V_MPLLB_FORCE_EN(1U)
+
+#define S_MPLLA_WORD_CLK_EN    3
+#define V_MPLLA_WORD_CLK_EN(x) ((x) << S_MPLLA_WORD_CLK_EN)
+#define F_MPLLA_WORD_CLK_EN    V_MPLLA_WORD_CLK_EN(1U)
+
+#define S_MPLLA_SSC_EN    2
+#define V_MPLLA_SSC_EN(x) ((x) << S_MPLLA_SSC_EN)
+#define F_MPLLA_SSC_EN    V_MPLLA_SSC_EN(1U)
+
+#define S_MPLLA_SHORT_LOCK_EN    1
+#define V_MPLLA_SHORT_LOCK_EN(x) ((x) << S_MPLLA_SHORT_LOCK_EN)
+#define F_MPLLA_SHORT_LOCK_EN    V_MPLLA_SHORT_LOCK_EN(1U)
+
+#define S_MPLLA_FORCE_EN    0
+#define V_MPLLA_FORCE_EN(x) ((x) << S_MPLLA_FORCE_EN)
+#define F_MPLLA_FORCE_EN    V_MPLLA_FORCE_EN(1U)
+
+#define A_PCIE_SNPS_G5_PHY_1_VALUES 0x5fac
+
+#define S_REF_ALT1_CLK_M    13
+#define V_REF_ALT1_CLK_M(x) ((x) << S_REF_ALT1_CLK_M)
+#define F_REF_ALT1_CLK_M    V_REF_ALT1_CLK_M(1U)
+
+#define S_REF_ALT1_CLK_P    12
+#define V_REF_ALT1_CLK_P(x) ((x) << S_REF_ALT1_CLK_P)
+#define F_REF_ALT1_CLK_P    V_REF_ALT1_CLK_P(1U)
+
+#define A_PCIE_SNPS_G5_PHY_2_VALUES 0x5fb0
+#define A_PCIE_SNPS_G5_PHY_3_VALUES 0x5fb4
+#define A_PCIE_SNPS_G5_PHY_0_RX_LANEPLL_BYPASS_MODE 0x5fb8
+
+#define S_T7_LANE3    15
+#define M_T7_LANE3    0x1fU
+#define V_T7_LANE3(x) ((x) << S_T7_LANE3)
+#define G_T7_LANE3(x) (((x) >> S_T7_LANE3) & M_T7_LANE3)
+
+#define S_T7_LANE2    10
+#define M_T7_LANE2    0x1fU
+#define V_T7_LANE2(x) ((x) << S_T7_LANE2)
+#define G_T7_LANE2(x) (((x) >> S_T7_LANE2) & M_T7_LANE2)
+
+#define S_T7_LANE1    5
+#define M_T7_LANE1    0x1fU
+#define V_T7_LANE1(x) ((x) << S_T7_LANE1)
+#define G_T7_LANE1(x) (((x) >> S_T7_LANE1) & M_T7_LANE1)
+
+#define S_T7_LANE0    0
+#define M_T7_LANE0    0x1fU
+#define V_T7_LANE0(x) ((x) << S_T7_LANE0)
+#define G_T7_LANE0(x) (((x) >> S_T7_LANE0) & M_T7_LANE0)
+
+#define A_PCIE_SNPS_G5_PHY_1_RX_LANEPLL_BYPASS_MODE 0x5fbc
+#define A_PCIE_SNPS_G5_PHY_2_RX_LANEPLL_BYPASS_MODE 0x5fc0
+#define A_PCIE_SNPS_G5_PHY_3_RX_LANEPLL_BYPASS_MODE 0x5fc4
+#define A_PCIE_SNPS_G5_PHY_0_1_RX_LANEPLL_SRC_SEL 0x5fc8
+
+#define S_LANE7_LANEPLL_SRC_SEL    28
+#define M_LANE7_LANEPLL_SRC_SEL    0xfU
+#define V_LANE7_LANEPLL_SRC_SEL(x) ((x) << S_LANE7_LANEPLL_SRC_SEL)
+#define G_LANE7_LANEPLL_SRC_SEL(x) (((x) >> S_LANE7_LANEPLL_SRC_SEL) & M_LANE7_LANEPLL_SRC_SEL)
+
+#define S_LANE6_LANEPLL_SRC_SEL    24
+#define M_LANE6_LANEPLL_SRC_SEL    0xfU
+#define V_LANE6_LANEPLL_SRC_SEL(x) ((x) << S_LANE6_LANEPLL_SRC_SEL)
+#define G_LANE6_LANEPLL_SRC_SEL(x) (((x) >> S_LANE6_LANEPLL_SRC_SEL) & M_LANE6_LANEPLL_SRC_SEL)
+
+#define S_LANE5_LANEPLL_SRC_SEL    20
+#define M_LANE5_LANEPLL_SRC_SEL    0xfU
+#define V_LANE5_LANEPLL_SRC_SEL(x) ((x) << S_LANE5_LANEPLL_SRC_SEL)
+#define G_LANE5_LANEPLL_SRC_SEL(x) (((x) >> S_LANE5_LANEPLL_SRC_SEL) & M_LANE5_LANEPLL_SRC_SEL)
+
+#define S_LANE4_LANEPLL_SRC_SEL    16
+#define M_LANE4_LANEPLL_SRC_SEL    0xfU
+#define V_LANE4_LANEPLL_SRC_SEL(x) ((x) << S_LANE4_LANEPLL_SRC_SEL)
+#define G_LANE4_LANEPLL_SRC_SEL(x) (((x) >> S_LANE4_LANEPLL_SRC_SEL) & M_LANE4_LANEPLL_SRC_SEL)
+
+#define S_LANE3_LANEPLL_SRC_SEL    12
+#define M_LANE3_LANEPLL_SRC_SEL    0xfU
+#define V_LANE3_LANEPLL_SRC_SEL(x) ((x) << S_LANE3_LANEPLL_SRC_SEL)
+#define G_LANE3_LANEPLL_SRC_SEL(x) (((x) >> S_LANE3_LANEPLL_SRC_SEL) & M_LANE3_LANEPLL_SRC_SEL)
+
+#define S_LANE2_LANEPLL_SRC_SEL    8
+#define M_LANE2_LANEPLL_SRC_SEL    0xfU
+#define V_LANE2_LANEPLL_SRC_SEL(x) ((x) << S_LANE2_LANEPLL_SRC_SEL)
+#define G_LANE2_LANEPLL_SRC_SEL(x) (((x) >> S_LANE2_LANEPLL_SRC_SEL) & M_LANE2_LANEPLL_SRC_SEL)
+
+#define S_LANE1_LANEPLL_SRC_SEL    4
+#define M_LANE1_LANEPLL_SRC_SEL    0xfU
+#define V_LANE1_LANEPLL_SRC_SEL(x) ((x) << S_LANE1_LANEPLL_SRC_SEL)
+#define G_LANE1_LANEPLL_SRC_SEL(x) (((x) >> S_LANE1_LANEPLL_SRC_SEL) & M_LANE1_LANEPLL_SRC_SEL)
+
+#define S_LANE0_LANEPLL_SRC_SEL    0
+#define M_LANE0_LANEPLL_SRC_SEL    0xfU
+#define V_LANE0_LANEPLL_SRC_SEL(x) ((x) << S_LANE0_LANEPLL_SRC_SEL)
+#define G_LANE0_LANEPLL_SRC_SEL(x) (((x) >> S_LANE0_LANEPLL_SRC_SEL) & M_LANE0_LANEPLL_SRC_SEL)
+
+#define A_PCIE_SNPS_G5_PHY_2_3_RX_LANEPLL_SRC_SEL 0x5fcc
+#define A_PCIE_SNPS_G5_PHY_RX_DECERR 0x5fd0
+
+#define S_LANE15_REC_OVRD_8B10B_DECERR    30
+#define M_LANE15_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE15_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE15_REC_OVRD_8B10B_DECERR)
+#define G_LANE15_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE15_REC_OVRD_8B10B_DECERR) & M_LANE15_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE14_REC_OVRD_8B10B_DECERR    28
+#define M_LANE14_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE14_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE14_REC_OVRD_8B10B_DECERR)
+#define G_LANE14_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE14_REC_OVRD_8B10B_DECERR) & M_LANE14_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE13_REC_OVRD_8B10B_DECERR    26
+#define M_LANE13_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE13_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE13_REC_OVRD_8B10B_DECERR)
+#define G_LANE13_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE13_REC_OVRD_8B10B_DECERR) & M_LANE13_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE12_REC_OVRD_8B10B_DECERR    24
+#define M_LANE12_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE12_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE12_REC_OVRD_8B10B_DECERR)
+#define G_LANE12_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE12_REC_OVRD_8B10B_DECERR) & M_LANE12_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE11_REC_OVRD_8B10B_DECERR    22
+#define M_LANE11_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE11_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE11_REC_OVRD_8B10B_DECERR)
+#define G_LANE11_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE11_REC_OVRD_8B10B_DECERR) & M_LANE11_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE10_REC_OVRD_8B10B_DECERR    20
+#define M_LANE10_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE10_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE10_REC_OVRD_8B10B_DECERR)
+#define G_LANE10_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE10_REC_OVRD_8B10B_DECERR) & M_LANE10_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE9_REC_OVRD_8B10B_DECERR    18
+#define M_LANE9_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE9_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE9_REC_OVRD_8B10B_DECERR)
+#define G_LANE9_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE9_REC_OVRD_8B10B_DECERR) & M_LANE9_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE8_REC_OVRD_8B10B_DECERR    16
+#define M_LANE8_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE8_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE8_REC_OVRD_8B10B_DECERR)
+#define G_LANE8_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE8_REC_OVRD_8B10B_DECERR) & M_LANE8_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE7_REC_OVRD_8B10B_DECERR    14
+#define M_LANE7_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE7_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE7_REC_OVRD_8B10B_DECERR)
+#define G_LANE7_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE7_REC_OVRD_8B10B_DECERR) & M_LANE7_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE6_REC_OVRD_8B10B_DECERR    12
+#define M_LANE6_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE6_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE6_REC_OVRD_8B10B_DECERR)
+#define G_LANE6_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE6_REC_OVRD_8B10B_DECERR) & M_LANE6_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE5_REC_OVRD_8B10B_DECERR    10
+#define M_LANE5_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE5_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE5_REC_OVRD_8B10B_DECERR)
+#define G_LANE5_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE5_REC_OVRD_8B10B_DECERR) & M_LANE5_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE4_REC_OVRD_8B10B_DECERR    8
+#define M_LANE4_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE4_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE4_REC_OVRD_8B10B_DECERR)
+#define G_LANE4_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE4_REC_OVRD_8B10B_DECERR) & M_LANE4_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE3_REC_OVRD_8B10B_DECERR    6
+#define M_LANE3_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE3_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE3_REC_OVRD_8B10B_DECERR)
+#define G_LANE3_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE3_REC_OVRD_8B10B_DECERR) & M_LANE3_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE2_REC_OVRD_8B10B_DECERR    4
+#define M_LANE2_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE2_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE2_REC_OVRD_8B10B_DECERR)
+#define G_LANE2_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE2_REC_OVRD_8B10B_DECERR) & M_LANE2_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE1_REC_OVRD_8B10B_DECERR    2
+#define M_LANE1_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE1_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE1_REC_OVRD_8B10B_DECERR)
+#define G_LANE1_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE1_REC_OVRD_8B10B_DECERR) & M_LANE1_REC_OVRD_8B10B_DECERR)
+
+#define S_LANE0_REC_OVRD_8B10B_DECERR    0
+#define M_LANE0_REC_OVRD_8B10B_DECERR    0x3U
+#define V_LANE0_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE0_REC_OVRD_8B10B_DECERR)
+#define G_LANE0_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE0_REC_OVRD_8B10B_DECERR) & M_LANE0_REC_OVRD_8B10B_DECERR)
+
+#define A_PCIE_SNPS_G5_PHY_TX2RX_LOOPBK_REC_OVRD_EN 0x5fd4
+
+#define S_LANE15_REC_OVRD_EN    31
+#define V_LANE15_REC_OVRD_EN(x) ((x) << S_LANE15_REC_OVRD_EN)
+#define F_LANE15_REC_OVRD_EN    V_LANE15_REC_OVRD_EN(1U)
+
+#define S_LANE14_REC_OVRD_EN    30
+#define V_LANE14_REC_OVRD_EN(x) ((x) << S_LANE14_REC_OVRD_EN)
+#define F_LANE14_REC_OVRD_EN    V_LANE14_REC_OVRD_EN(1U)
+
+#define S_LANE13_REC_OVRD_EN    29
+#define V_LANE13_REC_OVRD_EN(x) ((x) << S_LANE13_REC_OVRD_EN)
+#define F_LANE13_REC_OVRD_EN    V_LANE13_REC_OVRD_EN(1U)
+
+#define S_LANE11_REC_OVRD_EN    27
+#define V_LANE11_REC_OVRD_EN(x) ((x) << S_LANE11_REC_OVRD_EN)
+#define F_LANE11_REC_OVRD_EN    V_LANE11_REC_OVRD_EN(1U)
+
+#define S_LANE12_REC_OVRD_EN    28
+#define V_LANE12_REC_OVRD_EN(x) ((x) << S_LANE12_REC_OVRD_EN)
+#define F_LANE12_REC_OVRD_EN    V_LANE12_REC_OVRD_EN(1U)
+
+#define S_LANE10_REC_OVRD_EN    26
+#define V_LANE10_REC_OVRD_EN(x) ((x) << S_LANE10_REC_OVRD_EN)
+#define F_LANE10_REC_OVRD_EN    V_LANE10_REC_OVRD_EN(1U)
+
+#define S_LANE9_REC_OVRD_EN    25
+#define V_LANE9_REC_OVRD_EN(x) ((x) << S_LANE9_REC_OVRD_EN)
+#define F_LANE9_REC_OVRD_EN    V_LANE9_REC_OVRD_EN(1U)
+
+#define S_LANE8_REC_OVRD_EN    24
+#define V_LANE8_REC_OVRD_EN(x) ((x) << S_LANE8_REC_OVRD_EN)
+#define F_LANE8_REC_OVRD_EN    V_LANE8_REC_OVRD_EN(1U)
+
+#define S_LANE7_REC_OVRD_EN    23
+#define V_LANE7_REC_OVRD_EN(x) ((x) << S_LANE7_REC_OVRD_EN)
+#define F_LANE7_REC_OVRD_EN    V_LANE7_REC_OVRD_EN(1U)
+
+#define S_LANE6_REC_OVRD_EN    22
+#define V_LANE6_REC_OVRD_EN(x) ((x) << S_LANE6_REC_OVRD_EN)
+#define F_LANE6_REC_OVRD_EN    V_LANE6_REC_OVRD_EN(1U)
+
+#define S_LANE5_REC_OVRD_EN    21
+#define V_LANE5_REC_OVRD_EN(x) ((x) << S_LANE5_REC_OVRD_EN)
+#define F_LANE5_REC_OVRD_EN    V_LANE5_REC_OVRD_EN(1U)
+
+#define S_LANE4_REC_OVRD_EN    20
+#define V_LANE4_REC_OVRD_EN(x) ((x) << S_LANE4_REC_OVRD_EN)
+#define F_LANE4_REC_OVRD_EN    V_LANE4_REC_OVRD_EN(1U)
+
+#define S_LANE3_REC_OVRD_EN    19
+#define V_LANE3_REC_OVRD_EN(x) ((x) << S_LANE3_REC_OVRD_EN)
+#define F_LANE3_REC_OVRD_EN    V_LANE3_REC_OVRD_EN(1U)
+
+#define S_LANE2_REC_OVRD_EN    18
+#define V_LANE2_REC_OVRD_EN(x) ((x) << S_LANE2_REC_OVRD_EN)
+#define F_LANE2_REC_OVRD_EN    V_LANE2_REC_OVRD_EN(1U)
+
+#define S_LANE1_REC_OVRD_EN    17
+#define V_LANE1_REC_OVRD_EN(x) ((x) << S_LANE1_REC_OVRD_EN)
+#define F_LANE1_REC_OVRD_EN    V_LANE1_REC_OVRD_EN(1U)
+
+#define S_LANE0_REC_OVRD_EN    16
+#define V_LANE0_REC_OVRD_EN(x) ((x) << S_LANE0_REC_OVRD_EN)
+#define F_LANE0_REC_OVRD_EN    V_LANE0_REC_OVRD_EN(1U)
+
+#define S_LANE15_TX2RX_LOOPBK    15
+#define V_LANE15_TX2RX_LOOPBK(x) ((x) << S_LANE15_TX2RX_LOOPBK)
+#define F_LANE15_TX2RX_LOOPBK    V_LANE15_TX2RX_LOOPBK(1U)
+
+#define S_LANE14_TX2RX_LOOPBK    14
+#define V_LANE14_TX2RX_LOOPBK(x) ((x) << S_LANE14_TX2RX_LOOPBK)
+#define F_LANE14_TX2RX_LOOPBK    V_LANE14_TX2RX_LOOPBK(1U)
+
+#define S_LANE13_TX2RX_LOOPBK    13
+#define V_LANE13_TX2RX_LOOPBK(x) ((x) << S_LANE13_TX2RX_LOOPBK)
+#define F_LANE13_TX2RX_LOOPBK    V_LANE13_TX2RX_LOOPBK(1U)
+
+#define S_LANE12_TX2RX_LOOPBK    12
+#define V_LANE12_TX2RX_LOOPBK(x) ((x) << S_LANE12_TX2RX_LOOPBK)
+#define F_LANE12_TX2RX_LOOPBK    V_LANE12_TX2RX_LOOPBK(1U)
+
+#define S_LANE11_TX2RX_LOOPBK    11
+#define V_LANE11_TX2RX_LOOPBK(x) ((x) << S_LANE11_TX2RX_LOOPBK)
+#define F_LANE11_TX2RX_LOOPBK    V_LANE11_TX2RX_LOOPBK(1U)
+
+#define S_LANE10_TX2RX_LOOPBK    10
+#define V_LANE10_TX2RX_LOOPBK(x) ((x) << S_LANE10_TX2RX_LOOPBK)
+#define F_LANE10_TX2RX_LOOPBK    V_LANE10_TX2RX_LOOPBK(1U)
+
+#define S_LANE9_TX2RX_LOOPBK    9
+#define V_LANE9_TX2RX_LOOPBK(x) ((x) << S_LANE9_TX2RX_LOOPBK)
+#define F_LANE9_TX2RX_LOOPBK    V_LANE9_TX2RX_LOOPBK(1U)
+
+#define S_LANE8_TX2RX_LOOPBK    8
+#define V_LANE8_TX2RX_LOOPBK(x) ((x) << S_LANE8_TX2RX_LOOPBK)
+#define F_LANE8_TX2RX_LOOPBK    V_LANE8_TX2RX_LOOPBK(1U)
+
+#define S_LANE7_TX2RX_LOOPBK    7
+#define V_LANE7_TX2RX_LOOPBK(x) ((x) << S_LANE7_TX2RX_LOOPBK)
+#define F_LANE7_TX2RX_LOOPBK    V_LANE7_TX2RX_LOOPBK(1U)
+
+#define S_LANE6_TX2RX_LOOPBK    6
+#define V_LANE6_TX2RX_LOOPBK(x) ((x) << S_LANE6_TX2RX_LOOPBK)
+#define F_LANE6_TX2RX_LOOPBK    V_LANE6_TX2RX_LOOPBK(1U)
+
+#define S_LANE5_TX2RX_LOOPBK    5
+#define V_LANE5_TX2RX_LOOPBK(x) ((x) << S_LANE5_TX2RX_LOOPBK)
+#define F_LANE5_TX2RX_LOOPBK    V_LANE5_TX2RX_LOOPBK(1U)
+
+#define S_LANE4_TX2RX_LOOPBK    4
+#define V_LANE4_TX2RX_LOOPBK(x) ((x) << S_LANE4_TX2RX_LOOPBK)
+#define F_LANE4_TX2RX_LOOPBK    V_LANE4_TX2RX_LOOPBK(1U)
+
+#define S_LANE3_TX2RX_LOOPBK    3
+#define V_LANE3_TX2RX_LOOPBK(x) ((x) << S_LANE3_TX2RX_LOOPBK)
+#define F_LANE3_TX2RX_LOOPBK    V_LANE3_TX2RX_LOOPBK(1U)
+
+#define S_LANE2_TX2RX_LOOPBK    2
+#define V_LANE2_TX2RX_LOOPBK(x) ((x) << S_LANE2_TX2RX_LOOPBK)
+#define F_LANE2_TX2RX_LOOPBK    V_LANE2_TX2RX_LOOPBK(1U)
+
+#define S_LANE1_TX2RX_LOOPBK    1
+#define V_LANE1_TX2RX_LOOPBK(x) ((x) << S_LANE1_TX2RX_LOOPBK)
+#define F_LANE1_TX2RX_LOOPBK    V_LANE1_TX2RX_LOOPBK(1U)
+
+#define S_LANE0_TX2RX_LOOPBK    0
+#define V_LANE0_TX2RX_LOOPBK(x) ((x) << S_LANE0_TX2RX_LOOPBK)
+#define F_LANE0_TX2RX_LOOPBK    V_LANE0_TX2RX_LOOPBK(1U)
+
+#define A_PCIE_PHY_TX_DISABLE_UPCS_PIPE_CONFIG 0x5fd8
+
+#define S_UPCS_PIPE_CONFIG    16
+#define M_UPCS_PIPE_CONFIG    0xffffU
+#define V_UPCS_PIPE_CONFIG(x) ((x) << S_UPCS_PIPE_CONFIG)
+#define G_UPCS_PIPE_CONFIG(x) (((x) >> S_UPCS_PIPE_CONFIG) & M_UPCS_PIPE_CONFIG)
+
+#define S_TX15_DISABLE    15
+#define V_TX15_DISABLE(x) ((x) << S_TX15_DISABLE)
+#define F_TX15_DISABLE    V_TX15_DISABLE(1U)
+
+#define S_TX14_DISABLE    14
+#define V_TX14_DISABLE(x) ((x) << S_TX14_DISABLE)
+#define F_TX14_DISABLE    V_TX14_DISABLE(1U)
+
+#define S_TX13_DISABLE    13
+#define V_TX13_DISABLE(x) ((x) << S_TX13_DISABLE)
+#define F_TX13_DISABLE    V_TX13_DISABLE(1U)
+
+#define S_TX12_DISABLE    12
+#define V_TX12_DISABLE(x) ((x) << S_TX12_DISABLE)
+#define F_TX12_DISABLE    V_TX12_DISABLE(1U)
+
+#define S_TX11_DISABLE    11
+#define V_TX11_DISABLE(x) ((x) << S_TX11_DISABLE)
+#define F_TX11_DISABLE    V_TX11_DISABLE(1U)
+
+#define S_TX10_DISABLE    10
+#define V_TX10_DISABLE(x) ((x) << S_TX10_DISABLE)
+#define F_TX10_DISABLE    V_TX10_DISABLE(1U)
+
+#define S_TX9_DISABLE    9
+#define V_TX9_DISABLE(x) ((x) << S_TX9_DISABLE)
+#define F_TX9_DISABLE    V_TX9_DISABLE(1U)
+
+#define S_TX8_DISABLE    8
+#define V_TX8_DISABLE(x) ((x) << S_TX8_DISABLE)
+#define F_TX8_DISABLE    V_TX8_DISABLE(1U)
+
+#define S_TX7_DISABLE    7
+#define V_TX7_DISABLE(x) ((x) << S_TX7_DISABLE)
+#define F_TX7_DISABLE    V_TX7_DISABLE(1U)
+
+#define S_TX6_DISABLE    6
+#define V_TX6_DISABLE(x) ((x) << S_TX6_DISABLE)
+#define F_TX6_DISABLE    V_TX6_DISABLE(1U)
+
+#define S_TX5_DISABLE    5
+#define V_TX5_DISABLE(x) ((x) << S_TX5_DISABLE)
+#define F_TX5_DISABLE    V_TX5_DISABLE(1U)
+
+#define S_TX4_DISABLE    4
+#define V_TX4_DISABLE(x) ((x) << S_TX4_DISABLE)
+#define F_TX4_DISABLE    V_TX4_DISABLE(1U)
+
+#define S_TX3_DISABLE    3
+#define V_TX3_DISABLE(x) ((x) << S_TX3_DISABLE)
+#define F_TX3_DISABLE    V_TX3_DISABLE(1U)
+
+#define S_TX2_DISABLE    2
+#define V_TX2_DISABLE(x) ((x) << S_TX2_DISABLE)
+#define F_TX2_DISABLE    V_TX2_DISABLE(1U)
+
+#define S_TX1_DISABLE    1
+#define V_TX1_DISABLE(x) ((x) << S_TX1_DISABLE)
+#define F_TX1_DISABLE    V_TX1_DISABLE(1U)
+
+#define S_TX0_DISABLE    0
+#define V_TX0_DISABLE(x) ((x) << S_TX0_DISABLE)
+#define F_TX0_DISABLE    V_TX0_DISABLE(1U)
+
 #define A_PCIE_PDEBUG_REG_0X0 0x0
 #define A_PCIE_PDEBUG_REG_0X1 0x1
 #define A_PCIE_PDEBUG_REG_0X2 0x2
@@ -11668,6 +14476,40 @@
 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
 
+#define A_DBG_GPIO_OUT 0x6010
+
+#define S_GPIO23_OUT_VAL    23
+#define V_GPIO23_OUT_VAL(x) ((x) << S_GPIO23_OUT_VAL)
+#define F_GPIO23_OUT_VAL    V_GPIO23_OUT_VAL(1U)
+
+#define S_GPIO22_OUT_VAL    22
+#define V_GPIO22_OUT_VAL(x) ((x) << S_GPIO22_OUT_VAL)
+#define F_GPIO22_OUT_VAL    V_GPIO22_OUT_VAL(1U)
+
+#define S_GPIO21_OUT_VAL    21
+#define V_GPIO21_OUT_VAL(x) ((x) << S_GPIO21_OUT_VAL)
+#define F_GPIO21_OUT_VAL    V_GPIO21_OUT_VAL(1U)
+
+#define S_GPIO20_OUT_VAL    20
+#define V_GPIO20_OUT_VAL(x) ((x) << S_GPIO20_OUT_VAL)
+#define F_GPIO20_OUT_VAL    V_GPIO20_OUT_VAL(1U)
+
+#define S_T7_GPIO19_OUT_VAL    19
+#define V_T7_GPIO19_OUT_VAL(x) ((x) << S_T7_GPIO19_OUT_VAL)
+#define F_T7_GPIO19_OUT_VAL    V_T7_GPIO19_OUT_VAL(1U)
+
+#define S_T7_GPIO18_OUT_VAL    18
+#define V_T7_GPIO18_OUT_VAL(x) ((x) << S_T7_GPIO18_OUT_VAL)
+#define F_T7_GPIO18_OUT_VAL    V_T7_GPIO18_OUT_VAL(1U)
+
+#define S_T7_GPIO17_OUT_VAL    17
+#define V_T7_GPIO17_OUT_VAL(x) ((x) << S_T7_GPIO17_OUT_VAL)
+#define F_T7_GPIO17_OUT_VAL    V_T7_GPIO17_OUT_VAL(1U)
+
+#define S_T7_GPIO16_OUT_VAL    16
+#define V_T7_GPIO16_OUT_VAL(x) ((x) << S_T7_GPIO16_OUT_VAL)
+#define F_T7_GPIO16_OUT_VAL    V_T7_GPIO16_OUT_VAL(1U)
+
 #define A_DBG_GPIO_IN 0x6014
 
 #define S_GPIO15_CHG_DET    31
@@ -11798,6 +14640,38 @@
 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
 #define F_GPIO0_IN    V_GPIO0_IN(1U)
 
+#define S_GPIO23_IN    23
+#define V_GPIO23_IN(x) ((x) << S_GPIO23_IN)
+#define F_GPIO23_IN    V_GPIO23_IN(1U)
+
+#define S_GPIO22_IN    22
+#define V_GPIO22_IN(x) ((x) << S_GPIO22_IN)
+#define F_GPIO22_IN    V_GPIO22_IN(1U)
+
+#define S_GPIO21_IN    21
+#define V_GPIO21_IN(x) ((x) << S_GPIO21_IN)
+#define F_GPIO21_IN    V_GPIO21_IN(1U)
+
+#define S_GPIO20_IN    20
+#define V_GPIO20_IN(x) ((x) << S_GPIO20_IN)
+#define F_GPIO20_IN    V_GPIO20_IN(1U)
+
+#define S_T7_GPIO19_IN    19
+#define V_T7_GPIO19_IN(x) ((x) << S_T7_GPIO19_IN)
+#define F_T7_GPIO19_IN    V_T7_GPIO19_IN(1U)
+
+#define S_T7_GPIO18_IN    18
+#define V_T7_GPIO18_IN(x) ((x) << S_T7_GPIO18_IN)
+#define F_T7_GPIO18_IN    V_T7_GPIO18_IN(1U)
+
+#define S_T7_GPIO17_IN    17
+#define V_T7_GPIO17_IN(x) ((x) << S_T7_GPIO17_IN)
+#define F_T7_GPIO17_IN    V_T7_GPIO17_IN(1U)
+
+#define S_T7_GPIO16_IN    16
+#define V_T7_GPIO16_IN(x) ((x) << S_T7_GPIO16_IN)
+#define F_T7_GPIO16_IN    V_T7_GPIO16_IN(1U)
+
 #define A_DBG_INT_ENABLE 0x6018
 
 #define S_IBM_FDL_FAIL_INT_ENBL    25
@@ -11920,6 +14794,58 @@
 #define V_GPIO16(x) ((x) << S_GPIO16)
 #define F_GPIO16    V_GPIO16(1U)
 
+#define S_USBFIFOPARERR    12
+#define V_USBFIFOPARERR(x) ((x) << S_USBFIFOPARERR)
+#define F_USBFIFOPARERR    V_USBFIFOPARERR(1U)
+
+#define S_T7_IBM_FDL_FAIL_INT_ENBL    11
+#define V_T7_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_T7_IBM_FDL_FAIL_INT_ENBL)
+#define F_T7_IBM_FDL_FAIL_INT_ENBL    V_T7_IBM_FDL_FAIL_INT_ENBL(1U)
+
+#define S_T7_PLL_LOCK_LOST_INT_ENBL    10
+#define V_T7_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_T7_PLL_LOCK_LOST_INT_ENBL)
+#define F_T7_PLL_LOCK_LOST_INT_ENBL    V_T7_PLL_LOCK_LOST_INT_ENBL(1U)
+
+#define S_M1_LOCK    9
+#define V_M1_LOCK(x) ((x) << S_M1_LOCK)
+#define F_M1_LOCK    V_M1_LOCK(1U)
+
+#define S_T7_PCIE_LOCK    8
+#define V_T7_PCIE_LOCK(x) ((x) << S_T7_PCIE_LOCK)
+#define F_T7_PCIE_LOCK    V_T7_PCIE_LOCK(1U)
+
+#define S_T7_U_LOCK    7
+#define V_T7_U_LOCK(x) ((x) << S_T7_U_LOCK)
+#define F_T7_U_LOCK    V_T7_U_LOCK(1U)
+
+#define S_MAC_LOCK    6
+#define V_MAC_LOCK(x) ((x) << S_MAC_LOCK)
+#define F_MAC_LOCK    V_MAC_LOCK(1U)
+
+#define S_ARM_LOCK    5
+#define V_ARM_LOCK(x) ((x) << S_ARM_LOCK)
+#define F_ARM_LOCK    V_ARM_LOCK(1U)
+
+#define S_M0_LOCK    4
+#define V_M0_LOCK(x) ((x) << S_M0_LOCK)
+#define F_M0_LOCK    V_M0_LOCK(1U)
+
+#define S_XGPBUS_LOCK    3
+#define V_XGPBUS_LOCK(x) ((x) << S_XGPBUS_LOCK)
+#define F_XGPBUS_LOCK    V_XGPBUS_LOCK(1U)
+
+#define S_XGPHY_LOCK    2
+#define V_XGPHY_LOCK(x) ((x) << S_XGPHY_LOCK)
+#define F_XGPHY_LOCK    V_XGPHY_LOCK(1U)
+
+#define S_USB_LOCK    1
+#define V_USB_LOCK(x) ((x) << S_USB_LOCK)
+#define F_USB_LOCK    V_USB_LOCK(1U)
+
+#define S_T7_C_LOCK    0
+#define V_T7_C_LOCK(x) ((x) << S_T7_C_LOCK)
+#define F_T7_C_LOCK    V_T7_C_LOCK(1U)
+
 #define A_DBG_INT_CAUSE 0x601c
 
 #define S_IBM_FDL_FAIL_INT_CAUSE    25
@@ -11938,6 +14864,14 @@
 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
 #define F_PLL_LOCK_LOST_INT_CAUSE    V_PLL_LOCK_LOST_INT_CAUSE(1U)
 
+#define S_T7_IBM_FDL_FAIL_INT_CAUSE    11
+#define V_T7_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_T7_IBM_FDL_FAIL_INT_CAUSE)
+#define F_T7_IBM_FDL_FAIL_INT_CAUSE    V_T7_IBM_FDL_FAIL_INT_CAUSE(1U)
+
+#define S_T7_PLL_LOCK_LOST_INT_CAUSE    10
+#define V_T7_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_T7_PLL_LOCK_LOST_INT_CAUSE)
+#define F_T7_PLL_LOCK_LOST_INT_CAUSE    V_T7_PLL_LOCK_LOST_INT_CAUSE(1U)
+
 #define A_DBG_DBG0_RST_VALUE 0x6020
 
 #define S_DEBUGDATA    0
@@ -11977,6 +14911,10 @@
 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
 
+#define S_INIC_MODE_EN    0
+#define V_INIC_MODE_EN(x) ((x) << S_INIC_MODE_EN)
+#define F_INIC_MODE_EN    V_INIC_MODE_EN(1U)
+
 #define A_DBG_PLL_LOCK 0x602c
 
 #define S_PLL_P_LOCK    20
@@ -12003,6 +14941,38 @@
 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
 
+#define S_T7_PLL_M_LOCK    9
+#define V_T7_PLL_M_LOCK(x) ((x) << S_T7_PLL_M_LOCK)
+#define F_T7_PLL_M_LOCK    V_T7_PLL_M_LOCK(1U)
+
+#define S_PLL_PCIE_LOCK    8
+#define V_PLL_PCIE_LOCK(x) ((x) << S_PLL_PCIE_LOCK)
+#define F_PLL_PCIE_LOCK    V_PLL_PCIE_LOCK(1U)
+
+#define S_T7_PLL_U_LOCK    7
+#define V_T7_PLL_U_LOCK(x) ((x) << S_T7_PLL_U_LOCK)
+#define F_T7_PLL_U_LOCK    V_T7_PLL_U_LOCK(1U)
+
+#define S_PLL_MAC_LOCK    6
+#define V_PLL_MAC_LOCK(x) ((x) << S_PLL_MAC_LOCK)
+#define F_PLL_MAC_LOCK    V_PLL_MAC_LOCK(1U)
+
+#define S_PLL_ARM_LOCK    5
+#define V_PLL_ARM_LOCK(x) ((x) << S_PLL_ARM_LOCK)
+#define F_PLL_ARM_LOCK    V_PLL_ARM_LOCK(1U)
+
+#define S_PLL_XGPBUS_LOCK    3
+#define V_PLL_XGPBUS_LOCK(x) ((x) << S_PLL_XGPBUS_LOCK)
+#define F_PLL_XGPBUS_LOCK    V_PLL_XGPBUS_LOCK(1U)
+
+#define S_PLL_XGPHY_LOCK    2
+#define V_PLL_XGPHY_LOCK(x) ((x) << S_PLL_XGPHY_LOCK)
+#define F_PLL_XGPHY_LOCK    V_PLL_XGPHY_LOCK(1U)
+
+#define S_PLL_USB_LOCK    1
+#define V_PLL_USB_LOCK(x) ((x) << S_PLL_USB_LOCK)
+#define F_PLL_USB_LOCK    V_PLL_USB_LOCK(1U)
+
 #define A_DBG_GPIO_ACT_LOW 0x6030
 
 #define S_P_LOCK_ACT_LOW    21
@@ -12109,6 +15079,48 @@
 #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
 #define F_GPIO16_ACT_LOW    V_GPIO16_ACT_LOW(1U)
 
+#define A_DBG_PLL_LOCK_ACT_LOW 0x6030
+
+#define S_M1_LOCK_ACT_LOW    9
+#define V_M1_LOCK_ACT_LOW(x) ((x) << S_M1_LOCK_ACT_LOW)
+#define F_M1_LOCK_ACT_LOW    V_M1_LOCK_ACT_LOW(1U)
+
+#define S_PCIE_LOCK_ACT_LOW    8
+#define V_PCIE_LOCK_ACT_LOW(x) ((x) << S_PCIE_LOCK_ACT_LOW)
+#define F_PCIE_LOCK_ACT_LOW    V_PCIE_LOCK_ACT_LOW(1U)
+
+#define S_T7_U_LOCK_ACT_LOW    7
+#define V_T7_U_LOCK_ACT_LOW(x) ((x) << S_T7_U_LOCK_ACT_LOW)
+#define F_T7_U_LOCK_ACT_LOW    V_T7_U_LOCK_ACT_LOW(1U)
+
+#define S_MAC_LOCK_ACT_LOW    6
+#define V_MAC_LOCK_ACT_LOW(x) ((x) << S_MAC_LOCK_ACT_LOW)
+#define F_MAC_LOCK_ACT_LOW    V_MAC_LOCK_ACT_LOW(1U)
+
+#define S_ARM_LOCK_ACT_LOW    5
+#define V_ARM_LOCK_ACT_LOW(x) ((x) << S_ARM_LOCK_ACT_LOW)
+#define F_ARM_LOCK_ACT_LOW    V_ARM_LOCK_ACT_LOW(1U)
+
+#define S_M0_LOCK_ACT_LOW    4
+#define V_M0_LOCK_ACT_LOW(x) ((x) << S_M0_LOCK_ACT_LOW)
+#define F_M0_LOCK_ACT_LOW    V_M0_LOCK_ACT_LOW(1U)
+
+#define S_XGPBUS_LOCK_ACT_LOW    3
+#define V_XGPBUS_LOCK_ACT_LOW(x) ((x) << S_XGPBUS_LOCK_ACT_LOW)
+#define F_XGPBUS_LOCK_ACT_LOW    V_XGPBUS_LOCK_ACT_LOW(1U)
+
+#define S_XGPHY_LOCK_ACT_LOW    2
+#define V_XGPHY_LOCK_ACT_LOW(x) ((x) << S_XGPHY_LOCK_ACT_LOW)
+#define F_XGPHY_LOCK_ACT_LOW    V_XGPHY_LOCK_ACT_LOW(1U)
+
+#define S_USB_LOCK_ACT_LOW    1
+#define V_USB_LOCK_ACT_LOW(x) ((x) << S_USB_LOCK_ACT_LOW)
+#define F_USB_LOCK_ACT_LOW    V_USB_LOCK_ACT_LOW(1U)
+
+#define S_T7_C_LOCK_ACT_LOW    0
+#define V_T7_C_LOCK_ACT_LOW(x) ((x) << S_T7_C_LOCK_ACT_LOW)
+#define F_T7_C_LOCK_ACT_LOW    V_T7_C_LOCK_ACT_LOW(1U)
+
 #define A_DBG_EFUSE_BYTE0_3 0x6034
 #define A_DBG_EFUSE_BYTE4_7 0x6038
 #define A_DBG_EFUSE_BYTE8_11 0x603c
@@ -12140,6 +15152,32 @@
 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
 
+#define A_T7_DBG_STATIC_U_PLL_CONF1 0x6044
+
+#define S_STATIC_U_PLL_RANGE    22
+#define M_STATIC_U_PLL_RANGE    0x7U
+#define V_STATIC_U_PLL_RANGE(x) ((x) << S_STATIC_U_PLL_RANGE)
+#define G_STATIC_U_PLL_RANGE(x) (((x) >> S_STATIC_U_PLL_RANGE) & M_STATIC_U_PLL_RANGE)
+
+#define S_STATIC_U_PLL_DIVQ    17
+#define M_STATIC_U_PLL_DIVQ    0x1fU
+#define V_STATIC_U_PLL_DIVQ(x) ((x) << S_STATIC_U_PLL_DIVQ)
+#define G_STATIC_U_PLL_DIVQ(x) (((x) >> S_STATIC_U_PLL_DIVQ) & M_STATIC_U_PLL_DIVQ)
+
+#define S_STATIC_U_PLL_DIVFI    8
+#define M_STATIC_U_PLL_DIVFI    0x1ffU
+#define V_STATIC_U_PLL_DIVFI(x) ((x) << S_STATIC_U_PLL_DIVFI)
+#define G_STATIC_U_PLL_DIVFI(x) (((x) >> S_STATIC_U_PLL_DIVFI) & M_STATIC_U_PLL_DIVFI)
+
+#define S_STATIC_U_PLL_DIVR    2
+#define M_STATIC_U_PLL_DIVR    0x3fU
+#define V_STATIC_U_PLL_DIVR(x) ((x) << S_STATIC_U_PLL_DIVR)
+#define G_STATIC_U_PLL_DIVR(x) (((x) >> S_STATIC_U_PLL_DIVR) & M_STATIC_U_PLL_DIVR)
+
+#define S_T7_1_STATIC_U_PLL_BYPASS    1
+#define V_T7_1_STATIC_U_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_U_PLL_BYPASS)
+#define F_T7_1_STATIC_U_PLL_BYPASS    V_T7_1_STATIC_U_PLL_BYPASS(1U)
+
 #define A_DBG_STATIC_C_PLL_CONF 0x6048
 
 #define S_STATIC_C_PLL_MULT    23
@@ -12167,6 +15205,26 @@
 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
 
+#define A_T7_DBG_STATIC_U_PLL_CONF2 0x6048
+
+#define S_STATIC_U_PLL_SSMF    5
+#define M_STATIC_U_PLL_SSMF    0xfU
+#define V_STATIC_U_PLL_SSMF(x) ((x) << S_STATIC_U_PLL_SSMF)
+#define G_STATIC_U_PLL_SSMF(x) (((x) >> S_STATIC_U_PLL_SSMF) & M_STATIC_U_PLL_SSMF)
+
+#define S_STATIC_U_PLL_SSMD    2
+#define M_STATIC_U_PLL_SSMD    0x7U
+#define V_STATIC_U_PLL_SSMD(x) ((x) << S_STATIC_U_PLL_SSMD)
+#define G_STATIC_U_PLL_SSMD(x) (((x) >> S_STATIC_U_PLL_SSMD) & M_STATIC_U_PLL_SSMD)
+
+#define S_STATIC_U_PLL_SSDS    1
+#define V_STATIC_U_PLL_SSDS(x) ((x) << S_STATIC_U_PLL_SSDS)
+#define F_STATIC_U_PLL_SSDS    V_STATIC_U_PLL_SSDS(1U)
+
+#define S_STATIC_U_PLL_SSE    0
+#define V_STATIC_U_PLL_SSE(x) ((x) << S_STATIC_U_PLL_SSE)
+#define F_STATIC_U_PLL_SSE    V_STATIC_U_PLL_SSE(1U)
+
 #define A_DBG_STATIC_M_PLL_CONF 0x604c
 
 #define S_STATIC_M_PLL_MULT    23
@@ -12194,6 +15252,32 @@
 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
 
+#define A_T7_DBG_STATIC_C_PLL_CONF1 0x604c
+
+#define S_STATIC_C_PLL_RANGE    22
+#define M_STATIC_C_PLL_RANGE    0x7U
+#define V_STATIC_C_PLL_RANGE(x) ((x) << S_STATIC_C_PLL_RANGE)
+#define G_STATIC_C_PLL_RANGE(x) (((x) >> S_STATIC_C_PLL_RANGE) & M_STATIC_C_PLL_RANGE)
+
+#define S_STATIC_C_PLL_DIVQ    17
+#define M_STATIC_C_PLL_DIVQ    0x1fU
+#define V_STATIC_C_PLL_DIVQ(x) ((x) << S_STATIC_C_PLL_DIVQ)
+#define G_STATIC_C_PLL_DIVQ(x) (((x) >> S_STATIC_C_PLL_DIVQ) & M_STATIC_C_PLL_DIVQ)
+
+#define S_STATIC_C_PLL_DIVFI    8
+#define M_STATIC_C_PLL_DIVFI    0x1ffU
+#define V_STATIC_C_PLL_DIVFI(x) ((x) << S_STATIC_C_PLL_DIVFI)
+#define G_STATIC_C_PLL_DIVFI(x) (((x) >> S_STATIC_C_PLL_DIVFI) & M_STATIC_C_PLL_DIVFI)
+
+#define S_STATIC_C_PLL_DIVR    2
+#define M_STATIC_C_PLL_DIVR    0x3fU
+#define V_STATIC_C_PLL_DIVR(x) ((x) << S_STATIC_C_PLL_DIVR)
+#define G_STATIC_C_PLL_DIVR(x) (((x) >> S_STATIC_C_PLL_DIVR) & M_STATIC_C_PLL_DIVR)
+
+#define S_T7_1_STATIC_C_PLL_BYPASS    1
+#define V_T7_1_STATIC_C_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_C_PLL_BYPASS)
+#define F_T7_1_STATIC_C_PLL_BYPASS    V_T7_1_STATIC_C_PLL_BYPASS(1U)
+
 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
 
 #define S_STATIC_KX_PLL_C    21
@@ -12226,6 +15310,26 @@
 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
 
+#define A_T7_DBG_STATIC_C_PLL_CONF2 0x6050
+
+#define S_STATIC_C_PLL_SSMF    5
+#define M_STATIC_C_PLL_SSMF    0xfU
+#define V_STATIC_C_PLL_SSMF(x) ((x) << S_STATIC_C_PLL_SSMF)
+#define G_STATIC_C_PLL_SSMF(x) (((x) >> S_STATIC_C_PLL_SSMF) & M_STATIC_C_PLL_SSMF)
+
+#define S_STATIC_C_PLL_SSMD    2
+#define M_STATIC_C_PLL_SSMD    0x7U
+#define V_STATIC_C_PLL_SSMD(x) ((x) << S_STATIC_C_PLL_SSMD)
+#define G_STATIC_C_PLL_SSMD(x) (((x) >> S_STATIC_C_PLL_SSMD) & M_STATIC_C_PLL_SSMD)
+
+#define S_STATIC_C_PLL_SSDS    1
+#define V_STATIC_C_PLL_SSDS(x) ((x) << S_STATIC_C_PLL_SSDS)
+#define F_STATIC_C_PLL_SSDS    V_STATIC_C_PLL_SSDS(1U)
+
+#define S_STATIC_C_PLL_SSE    0
+#define V_STATIC_C_PLL_SSE(x) ((x) << S_STATIC_C_PLL_SSE)
+#define F_STATIC_C_PLL_SSE    V_STATIC_C_PLL_SSE(1U)
+
 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
 
 #define S_STATIC_KR_PLL_C    21
@@ -12258,6 +15362,38 @@
 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
 
+#define A_DBG_STATIC_PLL_DFS_CONF 0x6054
+
+#define S_STATIC_U_DFS_ACK    23
+#define V_STATIC_U_DFS_ACK(x) ((x) << S_STATIC_U_DFS_ACK)
+#define F_STATIC_U_DFS_ACK    V_STATIC_U_DFS_ACK(1U)
+
+#define S_STATIC_C_DFS_ACK    22
+#define V_STATIC_C_DFS_ACK(x) ((x) << S_STATIC_C_DFS_ACK)
+#define F_STATIC_C_DFS_ACK    V_STATIC_C_DFS_ACK(1U)
+
+#define S_STATIC_U_DFS_DIVFI    13
+#define M_STATIC_U_DFS_DIVFI    0x1ffU
+#define V_STATIC_U_DFS_DIVFI(x) ((x) << S_STATIC_U_DFS_DIVFI)
+#define G_STATIC_U_DFS_DIVFI(x) (((x) >> S_STATIC_U_DFS_DIVFI) & M_STATIC_U_DFS_DIVFI)
+
+#define S_STATIC_U_DFS_NEWDIV    12
+#define V_STATIC_U_DFS_NEWDIV(x) ((x) << S_STATIC_U_DFS_NEWDIV)
+#define F_STATIC_U_DFS_NEWDIV    V_STATIC_U_DFS_NEWDIV(1U)
+
+#define S_T7_STATIC_U_DFS_ENABLE    11
+#define V_T7_STATIC_U_DFS_ENABLE(x) ((x) << S_T7_STATIC_U_DFS_ENABLE)
+#define F_T7_STATIC_U_DFS_ENABLE    V_T7_STATIC_U_DFS_ENABLE(1U)
+
+#define S_STATIC_C_DFS_DIVFI    2
+#define M_STATIC_C_DFS_DIVFI    0x1ffU
+#define V_STATIC_C_DFS_DIVFI(x) ((x) << S_STATIC_C_DFS_DIVFI)
+#define G_STATIC_C_DFS_DIVFI(x) (((x) >> S_STATIC_C_DFS_DIVFI) & M_STATIC_C_DFS_DIVFI)
+
+#define S_STATIC_C_DFS_NEWDIV    1
+#define V_STATIC_C_DFS_NEWDIV(x) ((x) << S_STATIC_C_DFS_NEWDIV)
+#define F_STATIC_C_DFS_NEWDIV    V_STATIC_C_DFS_NEWDIV(1U)
+
 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
 
 #define S_STATIC_M_PLL_RESET    30
@@ -12343,6 +15479,14 @@
 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
 
+#define S_T7_STATIC_LVDS_CLKOUT_EN    21
+#define V_T7_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_T7_STATIC_LVDS_CLKOUT_EN)
+#define F_T7_STATIC_LVDS_CLKOUT_EN    V_T7_STATIC_LVDS_CLKOUT_EN(1U)
+
+#define S_T7_EXPHYCLK_SEL_EN    16
+#define V_T7_EXPHYCLK_SEL_EN(x) ((x) << S_T7_EXPHYCLK_SEL_EN)
+#define F_T7_EXPHYCLK_SEL_EN    V_T7_EXPHYCLK_SEL_EN(1U)
+
 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
 
 #define S_M_OCLK_MUXSEL    12
@@ -12467,16 +15611,6 @@
 #define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0)
 #define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0)
 
-#define S_T6_RD_ADDR1    11
-#define M_T6_RD_ADDR1    0x1ffU
-#define V_T6_RD_ADDR1(x) ((x) << S_T6_RD_ADDR1)
-#define G_T6_RD_ADDR1(x) (((x) >> S_T6_RD_ADDR1) & M_T6_RD_ADDR1)
-
-#define S_T6_RD_ADDR0    2
-#define M_T6_RD_ADDR0    0x1ffU
-#define V_T6_RD_ADDR0(x) ((x) << S_T6_RD_ADDR0)
-#define G_T6_RD_ADDR0(x) (((x) >> S_T6_RD_ADDR0) & M_T6_RD_ADDR0)
-
 #define A_DBG_TRACE_WRADDR 0x6090
 
 #define S_WR_POINTER_ADDR1    16
@@ -12499,16 +15633,6 @@
 #define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0)
 #define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0)
 
-#define S_T6_WR_POINTER_ADDR1    16
-#define M_T6_WR_POINTER_ADDR1    0x1ffU
-#define V_T6_WR_POINTER_ADDR1(x) ((x) << S_T6_WR_POINTER_ADDR1)
-#define G_T6_WR_POINTER_ADDR1(x) (((x) >> S_T6_WR_POINTER_ADDR1) & M_T6_WR_POINTER_ADDR1)
-
-#define S_T6_WR_POINTER_ADDR0    0
-#define M_T6_WR_POINTER_ADDR0    0x1ffU
-#define V_T6_WR_POINTER_ADDR0(x) ((x) << S_T6_WR_POINTER_ADDR0)
-#define G_T6_WR_POINTER_ADDR0(x) (((x) >> S_T6_WR_POINTER_ADDR0) & M_T6_WR_POINTER_ADDR0)
-
 #define A_DBG_TRACE0_DATA_OUT 0x6094
 #define A_DBG_TRACE1_DATA_OUT 0x6098
 #define A_DBG_FUSE_SENSE_DONE 0x609c
@@ -12575,7 +15699,52 @@
 #define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST)
 #define F_T6_TVSENSE_RST    V_T6_TVSENSE_RST(1U)
 
+#define A_DBG_PVT_EN1 0x60a8
+
+#define S_PVT_TRIMO    18
+#define M_PVT_TRIMO    0x3fU
+#define V_PVT_TRIMO(x) ((x) << S_PVT_TRIMO)
+#define G_PVT_TRIMO(x) (((x) >> S_PVT_TRIMO) & M_PVT_TRIMO)
+
+#define S_PVT_TRIMG    13
+#define M_PVT_TRIMG    0x1fU
+#define V_PVT_TRIMG(x) ((x) << S_PVT_TRIMG)
+#define G_PVT_TRIMG(x) (((x) >> S_PVT_TRIMG) & M_PVT_TRIMG)
+
+#define S_PVT_VSAMPLE    12
+#define V_PVT_VSAMPLE(x) ((x) << S_PVT_VSAMPLE)
+#define F_PVT_VSAMPLE    V_PVT_VSAMPLE(1U)
+
+#define S_PVT_PSAMPLE    10
+#define M_PVT_PSAMPLE    0x3U
+#define V_PVT_PSAMPLE(x) ((x) << S_PVT_PSAMPLE)
+#define G_PVT_PSAMPLE(x) (((x) >> S_PVT_PSAMPLE) & M_PVT_PSAMPLE)
+
+#define S_PVT_ENA    9
+#define V_PVT_ENA(x) ((x) << S_PVT_ENA)
+#define F_PVT_ENA    V_PVT_ENA(1U)
+
+#define S_PVT_RESET    8
+#define V_PVT_RESET(x) ((x) << S_PVT_RESET)
+#define F_PVT_RESET    V_PVT_RESET(1U)
+
+#define S_PVT_DIV    0
+#define M_PVT_DIV    0xffU
+#define V_PVT_DIV(x) ((x) << S_PVT_DIV)
+#define G_PVT_DIV(x) (((x) >> S_PVT_DIV) & M_PVT_DIV)
+
 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
+#define A_DBG_PVT_EN2 0x60ac
+
+#define S_PVT_DATA_OUT    1
+#define M_PVT_DATA_OUT    0x3ffU
+#define V_PVT_DATA_OUT(x) ((x) << S_PVT_DATA_OUT)
+#define G_PVT_DATA_OUT(x) (((x) >> S_PVT_DATA_OUT) & M_PVT_DATA_OUT)
+
+#define S_PVT_DATA_VALID    0
+#define V_PVT_DATA_VALID(x) ((x) << S_PVT_DATA_VALID)
+#define F_PVT_DATA_VALID    V_PVT_DATA_VALID(1U)
+
 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
 
@@ -12638,6 +15807,36 @@
 #define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE)
 #define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE)
 
+#define A_DBG_STATIC_M0_PLL_CONF1 0x60b8
+
+#define S_STATIC_M0_PLL_RANGE    22
+#define M_STATIC_M0_PLL_RANGE    0x7U
+#define V_STATIC_M0_PLL_RANGE(x) ((x) << S_STATIC_M0_PLL_RANGE)
+#define G_STATIC_M0_PLL_RANGE(x) (((x) >> S_STATIC_M0_PLL_RANGE) & M_STATIC_M0_PLL_RANGE)
+
+#define S_STATIC_M0_PLL_DIVQ    17
+#define M_STATIC_M0_PLL_DIVQ    0x1fU
+#define V_STATIC_M0_PLL_DIVQ(x) ((x) << S_STATIC_M0_PLL_DIVQ)
+#define G_STATIC_M0_PLL_DIVQ(x) (((x) >> S_STATIC_M0_PLL_DIVQ) & M_STATIC_M0_PLL_DIVQ)
+
+#define S_STATIC_M0_PLL_DIVFI    8
+#define M_STATIC_M0_PLL_DIVFI    0x1ffU
+#define V_STATIC_M0_PLL_DIVFI(x) ((x) << S_STATIC_M0_PLL_DIVFI)
+#define G_STATIC_M0_PLL_DIVFI(x) (((x) >> S_STATIC_M0_PLL_DIVFI) & M_STATIC_M0_PLL_DIVFI)
+
+#define S_STATIC_M0_PLL_DIVR    2
+#define M_STATIC_M0_PLL_DIVR    0x3fU
+#define V_STATIC_M0_PLL_DIVR(x) ((x) << S_STATIC_M0_PLL_DIVR)
+#define G_STATIC_M0_PLL_DIVR(x) (((x) >> S_STATIC_M0_PLL_DIVR) & M_STATIC_M0_PLL_DIVR)
+
+#define S_STATIC_M0_PLL_BYPASS    1
+#define V_STATIC_M0_PLL_BYPASS(x) ((x) << S_STATIC_M0_PLL_BYPASS)
+#define F_STATIC_M0_PLL_BYPASS    V_STATIC_M0_PLL_BYPASS(1U)
+
+#define S_STATIC_M0_PLL_RESET    0
+#define V_STATIC_M0_PLL_RESET(x) ((x) << S_STATIC_M0_PLL_RESET)
+#define F_STATIC_M0_PLL_RESET    V_STATIC_M0_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
 
 #define S_T5_STATIC_M_PLL_DCO_BYPASS    23
@@ -12715,6 +15914,50 @@
 #define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE)
 #define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE)
 
+#define A_DBG_STATIC_M0_PLL_CONF2 0x60bc
+
+#define S_T7_STATIC_SWMC1RST_    14
+#define V_T7_STATIC_SWMC1RST_(x) ((x) << S_T7_STATIC_SWMC1RST_)
+#define F_T7_STATIC_SWMC1RST_    V_T7_STATIC_SWMC1RST_(1U)
+
+#define S_T7_STATIC_SWMC1CFGRST_    13
+#define V_T7_STATIC_SWMC1CFGRST_(x) ((x) << S_T7_STATIC_SWMC1CFGRST_)
+#define F_T7_STATIC_SWMC1CFGRST_    V_T7_STATIC_SWMC1CFGRST_(1U)
+
+#define S_T7_STATIC_PHY0RECRST_    12
+#define V_T7_STATIC_PHY0RECRST_(x) ((x) << S_T7_STATIC_PHY0RECRST_)
+#define F_T7_STATIC_PHY0RECRST_    V_T7_STATIC_PHY0RECRST_(1U)
+
+#define S_T7_STATIC_PHY1RECRST_    11
+#define V_T7_STATIC_PHY1RECRST_(x) ((x) << S_T7_STATIC_PHY1RECRST_)
+#define F_T7_STATIC_PHY1RECRST_    V_T7_STATIC_PHY1RECRST_(1U)
+
+#define S_T7_STATIC_SWMC0RST_    10
+#define V_T7_STATIC_SWMC0RST_(x) ((x) << S_T7_STATIC_SWMC0RST_)
+#define F_T7_STATIC_SWMC0RST_    V_T7_STATIC_SWMC0RST_(1U)
+
+#define S_T7_STATIC_SWMC0CFGRST_    9
+#define V_T7_STATIC_SWMC0CFGRST_(x) ((x) << S_T7_STATIC_SWMC0CFGRST_)
+#define F_T7_STATIC_SWMC0CFGRST_    V_T7_STATIC_SWMC0CFGRST_(1U)
+
+#define S_STATIC_M0_PLL_SSMF    5
+#define M_STATIC_M0_PLL_SSMF    0xfU
+#define V_STATIC_M0_PLL_SSMF(x) ((x) << S_STATIC_M0_PLL_SSMF)
+#define G_STATIC_M0_PLL_SSMF(x) (((x) >> S_STATIC_M0_PLL_SSMF) & M_STATIC_M0_PLL_SSMF)
+
+#define S_STATIC_M0_PLL_SSMD    2
+#define M_STATIC_M0_PLL_SSMD    0x7U
+#define V_STATIC_M0_PLL_SSMD(x) ((x) << S_STATIC_M0_PLL_SSMD)
+#define G_STATIC_M0_PLL_SSMD(x) (((x) >> S_STATIC_M0_PLL_SSMD) & M_STATIC_M0_PLL_SSMD)
+
+#define S_STATIC_M0_PLL_SSDS    1
+#define V_STATIC_M0_PLL_SSDS(x) ((x) << S_STATIC_M0_PLL_SSDS)
+#define F_STATIC_M0_PLL_SSDS    V_STATIC_M0_PLL_SSDS(1U)
+
+#define S_STATIC_M0_PLL_SSE    0
+#define V_STATIC_M0_PLL_SSE(x) ((x) << S_STATIC_M0_PLL_SSE)
+#define F_STATIC_M0_PLL_SSE    V_STATIC_M0_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
 
 #define S_T5_STATIC_M_PLL_MULTPRE    30
@@ -12778,8 +16021,58 @@
 #define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA)
 #define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA)
 
+#define A_DBG_STATIC_MAC_PLL_CONF1 0x60c0
+
+#define S_STATIC_MAC_PLL_RANGE    22
+#define M_STATIC_MAC_PLL_RANGE    0x7U
+#define V_STATIC_MAC_PLL_RANGE(x) ((x) << S_STATIC_MAC_PLL_RANGE)
+#define G_STATIC_MAC_PLL_RANGE(x) (((x) >> S_STATIC_MAC_PLL_RANGE) & M_STATIC_MAC_PLL_RANGE)
+
+#define S_STATIC_MAC_PLL_DIVQ    17
+#define M_STATIC_MAC_PLL_DIVQ    0x1fU
+#define V_STATIC_MAC_PLL_DIVQ(x) ((x) << S_STATIC_MAC_PLL_DIVQ)
+#define G_STATIC_MAC_PLL_DIVQ(x) (((x) >> S_STATIC_MAC_PLL_DIVQ) & M_STATIC_MAC_PLL_DIVQ)
+
+#define S_STATIC_MAC_PLL_DIVFI    8
+#define M_STATIC_MAC_PLL_DIVFI    0x1ffU
+#define V_STATIC_MAC_PLL_DIVFI(x) ((x) << S_STATIC_MAC_PLL_DIVFI)
+#define G_STATIC_MAC_PLL_DIVFI(x) (((x) >> S_STATIC_MAC_PLL_DIVFI) & M_STATIC_MAC_PLL_DIVFI)
+
+#define S_STATIC_MAC_PLL_DIVR    2
+#define M_STATIC_MAC_PLL_DIVR    0x3fU
+#define V_STATIC_MAC_PLL_DIVR(x) ((x) << S_STATIC_MAC_PLL_DIVR)
+#define G_STATIC_MAC_PLL_DIVR(x) (((x) >> S_STATIC_MAC_PLL_DIVR) & M_STATIC_MAC_PLL_DIVR)
+
+#define S_STATIC_MAC_PLL_BYPASS    1
+#define V_STATIC_MAC_PLL_BYPASS(x) ((x) << S_STATIC_MAC_PLL_BYPASS)
+#define F_STATIC_MAC_PLL_BYPASS    V_STATIC_MAC_PLL_BYPASS(1U)
+
+#define S_STATIC_MAC_PLL_RESET    0
+#define V_STATIC_MAC_PLL_RESET(x) ((x) << S_STATIC_MAC_PLL_RESET)
+#define F_STATIC_MAC_PLL_RESET    V_STATIC_MAC_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4
+#define A_DBG_STATIC_MAC_PLL_CONF2 0x60c4
+
+#define S_STATIC_MAC_PLL_SSMF    5
+#define M_STATIC_MAC_PLL_SSMF    0xfU
+#define V_STATIC_MAC_PLL_SSMF(x) ((x) << S_STATIC_MAC_PLL_SSMF)
+#define G_STATIC_MAC_PLL_SSMF(x) (((x) >> S_STATIC_MAC_PLL_SSMF) & M_STATIC_MAC_PLL_SSMF)
+
+#define S_STATIC_MAC_PLL_SSMD    2
+#define M_STATIC_MAC_PLL_SSMD    0x7U
+#define V_STATIC_MAC_PLL_SSMD(x) ((x) << S_STATIC_MAC_PLL_SSMD)
+#define G_STATIC_MAC_PLL_SSMD(x) (((x) >> S_STATIC_MAC_PLL_SSMD) & M_STATIC_MAC_PLL_SSMD)
+
+#define S_STATIC_MAC_PLL_SSDS    1
+#define V_STATIC_MAC_PLL_SSDS(x) ((x) << S_STATIC_MAC_PLL_SSDS)
+#define F_STATIC_MAC_PLL_SSDS    V_STATIC_MAC_PLL_SSDS(1U)
+
+#define S_STATIC_MAC_PLL_SSE    0
+#define V_STATIC_MAC_PLL_SSE(x) ((x) << S_STATIC_MAC_PLL_SSE)
+#define F_STATIC_MAC_PLL_SSE    V_STATIC_MAC_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
 
 #define S_T5_STATIC_M_PLL_VCVTUNE    24
@@ -12835,6 +16128,36 @@
 #define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT)
 #define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT)
 
+#define A_DBG_STATIC_ARM_PLL_CONF1 0x60c8
+
+#define S_STATIC_ARM_PLL_RANGE    22
+#define M_STATIC_ARM_PLL_RANGE    0x7U
+#define V_STATIC_ARM_PLL_RANGE(x) ((x) << S_STATIC_ARM_PLL_RANGE)
+#define G_STATIC_ARM_PLL_RANGE(x) (((x) >> S_STATIC_ARM_PLL_RANGE) & M_STATIC_ARM_PLL_RANGE)
+
+#define S_STATIC_ARM_PLL_DIVQ    17
+#define M_STATIC_ARM_PLL_DIVQ    0x1fU
+#define V_STATIC_ARM_PLL_DIVQ(x) ((x) << S_STATIC_ARM_PLL_DIVQ)
+#define G_STATIC_ARM_PLL_DIVQ(x) (((x) >> S_STATIC_ARM_PLL_DIVQ) & M_STATIC_ARM_PLL_DIVQ)
+
+#define S_STATIC_ARM_PLL_DIVFI    8
+#define M_STATIC_ARM_PLL_DIVFI    0x1ffU
+#define V_STATIC_ARM_PLL_DIVFI(x) ((x) << S_STATIC_ARM_PLL_DIVFI)
+#define G_STATIC_ARM_PLL_DIVFI(x) (((x) >> S_STATIC_ARM_PLL_DIVFI) & M_STATIC_ARM_PLL_DIVFI)
+
+#define S_STATIC_ARM_PLL_DIVR    2
+#define M_STATIC_ARM_PLL_DIVR    0x3fU
+#define V_STATIC_ARM_PLL_DIVR(x) ((x) << S_STATIC_ARM_PLL_DIVR)
+#define G_STATIC_ARM_PLL_DIVR(x) (((x) >> S_STATIC_ARM_PLL_DIVR) & M_STATIC_ARM_PLL_DIVR)
+
+#define S_STATIC_ARM_PLL_BYPASS    1
+#define V_STATIC_ARM_PLL_BYPASS(x) ((x) << S_STATIC_ARM_PLL_BYPASS)
+#define F_STATIC_ARM_PLL_BYPASS    V_STATIC_ARM_PLL_BYPASS(1U)
+
+#define S_STATIC_ARM_PLL_RESET    0
+#define V_STATIC_ARM_PLL_RESET(x) ((x) << S_STATIC_ARM_PLL_RESET)
+#define F_STATIC_ARM_PLL_RESET    V_STATIC_ARM_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
 
 #define S_T5_STATIC_PHY0RECRST_    5
@@ -12913,6 +16236,26 @@
 #define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_)
 #define F_STATIC_SWMC1CFGRST_    V_STATIC_SWMC1CFGRST_(1U)
 
+#define A_DBG_STATIC_ARM_PLL_CONF2 0x60cc
+
+#define S_STATIC_ARM_PLL_SSMF    5
+#define M_STATIC_ARM_PLL_SSMF    0xfU
+#define V_STATIC_ARM_PLL_SSMF(x) ((x) << S_STATIC_ARM_PLL_SSMF)
+#define G_STATIC_ARM_PLL_SSMF(x) (((x) >> S_STATIC_ARM_PLL_SSMF) & M_STATIC_ARM_PLL_SSMF)
+
+#define S_STATIC_ARM_PLL_SSMD    2
+#define M_STATIC_ARM_PLL_SSMD    0x7U
+#define V_STATIC_ARM_PLL_SSMD(x) ((x) << S_STATIC_ARM_PLL_SSMD)
+#define G_STATIC_ARM_PLL_SSMD(x) (((x) >> S_STATIC_ARM_PLL_SSMD) & M_STATIC_ARM_PLL_SSMD)
+
+#define S_STATIC_ARM_PLL_SSDS    1
+#define V_STATIC_ARM_PLL_SSDS(x) ((x) << S_STATIC_ARM_PLL_SSDS)
+#define F_STATIC_ARM_PLL_SSDS    V_STATIC_ARM_PLL_SSDS(1U)
+
+#define S_STATIC_ARM_PLL_SSE    0
+#define V_STATIC_ARM_PLL_SSE(x) ((x) << S_STATIC_ARM_PLL_SSE)
+#define F_STATIC_ARM_PLL_SSE    V_STATIC_ARM_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
 
 #define S_T5_STATIC_C_PLL_MULTFRAC    8
@@ -12937,6 +16280,36 @@
 #define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE)
 #define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE)
 
+#define A_DBG_STATIC_USB_PLL_CONF1 0x60d0
+
+#define S_STATIC_USB_PLL_RANGE    22
+#define M_STATIC_USB_PLL_RANGE    0x7U
+#define V_STATIC_USB_PLL_RANGE(x) ((x) << S_STATIC_USB_PLL_RANGE)
+#define G_STATIC_USB_PLL_RANGE(x) (((x) >> S_STATIC_USB_PLL_RANGE) & M_STATIC_USB_PLL_RANGE)
+
+#define S_STATIC_USB_PLL_DIVQ    17
+#define M_STATIC_USB_PLL_DIVQ    0x1fU
+#define V_STATIC_USB_PLL_DIVQ(x) ((x) << S_STATIC_USB_PLL_DIVQ)
+#define G_STATIC_USB_PLL_DIVQ(x) (((x) >> S_STATIC_USB_PLL_DIVQ) & M_STATIC_USB_PLL_DIVQ)
+
+#define S_STATIC_USB_PLL_DIVFI    8
+#define M_STATIC_USB_PLL_DIVFI    0x1ffU
+#define V_STATIC_USB_PLL_DIVFI(x) ((x) << S_STATIC_USB_PLL_DIVFI)
+#define G_STATIC_USB_PLL_DIVFI(x) (((x) >> S_STATIC_USB_PLL_DIVFI) & M_STATIC_USB_PLL_DIVFI)
+
+#define S_STATIC_USB_PLL_DIVR    2
+#define M_STATIC_USB_PLL_DIVR    0x3fU
+#define V_STATIC_USB_PLL_DIVR(x) ((x) << S_STATIC_USB_PLL_DIVR)
+#define G_STATIC_USB_PLL_DIVR(x) (((x) >> S_STATIC_USB_PLL_DIVR) & M_STATIC_USB_PLL_DIVR)
+
+#define S_STATIC_USB_PLL_BYPASS    1
+#define V_STATIC_USB_PLL_BYPASS(x) ((x) << S_STATIC_USB_PLL_BYPASS)
+#define F_STATIC_USB_PLL_BYPASS    V_STATIC_USB_PLL_BYPASS(1U)
+
+#define S_STATIC_USB_PLL_RESET    0
+#define V_STATIC_USB_PLL_RESET(x) ((x) << S_STATIC_USB_PLL_RESET)
+#define F_STATIC_USB_PLL_RESET    V_STATIC_USB_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
 
 #define S_T5_STATIC_C_PLL_DCO_BYPASS    23
@@ -13019,6 +16392,26 @@
 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
 
+#define A_DBG_STATIC_USB_PLL_CONF2 0x60d4
+
+#define S_STATIC_USB_PLL_SSMF    5
+#define M_STATIC_USB_PLL_SSMF    0xfU
+#define V_STATIC_USB_PLL_SSMF(x) ((x) << S_STATIC_USB_PLL_SSMF)
+#define G_STATIC_USB_PLL_SSMF(x) (((x) >> S_STATIC_USB_PLL_SSMF) & M_STATIC_USB_PLL_SSMF)
+
+#define S_STATIC_USB_PLL_SSMD    2
+#define M_STATIC_USB_PLL_SSMD    0x7U
+#define V_STATIC_USB_PLL_SSMD(x) ((x) << S_STATIC_USB_PLL_SSMD)
+#define G_STATIC_USB_PLL_SSMD(x) (((x) >> S_STATIC_USB_PLL_SSMD) & M_STATIC_USB_PLL_SSMD)
+
+#define S_STATIC_USB_PLL_SSDS    1
+#define V_STATIC_USB_PLL_SSDS(x) ((x) << S_STATIC_USB_PLL_SSDS)
+#define F_STATIC_USB_PLL_SSDS    V_STATIC_USB_PLL_SSDS(1U)
+
+#define S_STATIC_USB_PLL_SSE    0
+#define V_STATIC_USB_PLL_SSE(x) ((x) << S_STATIC_USB_PLL_SSE)
+#define F_STATIC_USB_PLL_SSE    V_STATIC_USB_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
 
 #define S_T5_STATIC_C_PLL_MULTPRE    30
@@ -13082,8 +16475,58 @@
 #define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA)
 #define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA)
 
+#define A_DBG_STATIC_XGPHY_PLL_CONF1 0x60d8
+
+#define S_STATIC_XGPHY_PLL_RANGE    22
+#define M_STATIC_XGPHY_PLL_RANGE    0x7U
+#define V_STATIC_XGPHY_PLL_RANGE(x) ((x) << S_STATIC_XGPHY_PLL_RANGE)
+#define G_STATIC_XGPHY_PLL_RANGE(x) (((x) >> S_STATIC_XGPHY_PLL_RANGE) & M_STATIC_XGPHY_PLL_RANGE)
+
+#define S_STATIC_XGPHY_PLL_DIVQ    17
+#define M_STATIC_XGPHY_PLL_DIVQ    0x1fU
+#define V_STATIC_XGPHY_PLL_DIVQ(x) ((x) << S_STATIC_XGPHY_PLL_DIVQ)
+#define G_STATIC_XGPHY_PLL_DIVQ(x) (((x) >> S_STATIC_XGPHY_PLL_DIVQ) & M_STATIC_XGPHY_PLL_DIVQ)
+
+#define S_STATIC_XGPHY_PLL_DIVFI    8
+#define M_STATIC_XGPHY_PLL_DIVFI    0x1ffU
+#define V_STATIC_XGPHY_PLL_DIVFI(x) ((x) << S_STATIC_XGPHY_PLL_DIVFI)
+#define G_STATIC_XGPHY_PLL_DIVFI(x) (((x) >> S_STATIC_XGPHY_PLL_DIVFI) & M_STATIC_XGPHY_PLL_DIVFI)
+
+#define S_STATIC_XGPHY_PLL_DIVR    2
+#define M_STATIC_XGPHY_PLL_DIVR    0x3fU
+#define V_STATIC_XGPHY_PLL_DIVR(x) ((x) << S_STATIC_XGPHY_PLL_DIVR)
+#define G_STATIC_XGPHY_PLL_DIVR(x) (((x) >> S_STATIC_XGPHY_PLL_DIVR) & M_STATIC_XGPHY_PLL_DIVR)
+
+#define S_STATIC_XGPHY_PLL_BYPASS    1
+#define V_STATIC_XGPHY_PLL_BYPASS(x) ((x) << S_STATIC_XGPHY_PLL_BYPASS)
+#define F_STATIC_XGPHY_PLL_BYPASS    V_STATIC_XGPHY_PLL_BYPASS(1U)
+
+#define S_STATIC_XGPHY_PLL_RESET    0
+#define V_STATIC_XGPHY_PLL_RESET(x) ((x) << S_STATIC_XGPHY_PLL_RESET)
+#define F_STATIC_XGPHY_PLL_RESET    V_STATIC_XGPHY_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
 #define A_DBG_STATIC_C_PLL_CONF4 0x60dc
+#define A_DBG_STATIC_XGPHY_PLL_CONF2 0x60dc
+
+#define S_STATIC_XGPHY_PLL_SSMF    5
+#define M_STATIC_XGPHY_PLL_SSMF    0xfU
+#define V_STATIC_XGPHY_PLL_SSMF(x) ((x) << S_STATIC_XGPHY_PLL_SSMF)
+#define G_STATIC_XGPHY_PLL_SSMF(x) (((x) >> S_STATIC_XGPHY_PLL_SSMF) & M_STATIC_XGPHY_PLL_SSMF)
+
+#define S_STATIC_XGPHY_PLL_SSMD    2
+#define M_STATIC_XGPHY_PLL_SSMD    0x7U
+#define V_STATIC_XGPHY_PLL_SSMD(x) ((x) << S_STATIC_XGPHY_PLL_SSMD)
+#define G_STATIC_XGPHY_PLL_SSMD(x) (((x) >> S_STATIC_XGPHY_PLL_SSMD) & M_STATIC_XGPHY_PLL_SSMD)
+
+#define S_STATIC_XGPHY_PLL_SSDS    1
+#define V_STATIC_XGPHY_PLL_SSDS(x) ((x) << S_STATIC_XGPHY_PLL_SSDS)
+#define F_STATIC_XGPHY_PLL_SSDS    V_STATIC_XGPHY_PLL_SSDS(1U)
+
+#define S_STATIC_XGPHY_PLL_SSE    0
+#define V_STATIC_XGPHY_PLL_SSE(x) ((x) << S_STATIC_XGPHY_PLL_SSE)
+#define F_STATIC_XGPHY_PLL_SSE    V_STATIC_XGPHY_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
 
 #define S_T5_STATIC_C_PLL_VCVTUNE    22
@@ -13140,6 +16583,40 @@
 #define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT)
 #define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT)
 
+#define A_DBG_STATIC_XGPBUS_PLL_CONF1 0x60e0
+
+#define S_STATIC_XGPBUS_SWRST_    25
+#define V_STATIC_XGPBUS_SWRST_(x) ((x) << S_STATIC_XGPBUS_SWRST_)
+#define F_STATIC_XGPBUS_SWRST_    V_STATIC_XGPBUS_SWRST_(1U)
+
+#define S_STATIC_XGPBUS_PLL_RANGE    22
+#define M_STATIC_XGPBUS_PLL_RANGE    0x7U
+#define V_STATIC_XGPBUS_PLL_RANGE(x) ((x) << S_STATIC_XGPBUS_PLL_RANGE)
+#define G_STATIC_XGPBUS_PLL_RANGE(x) (((x) >> S_STATIC_XGPBUS_PLL_RANGE) & M_STATIC_XGPBUS_PLL_RANGE)
+
+#define S_STATIC_XGPBUS_PLL_DIVQ    17
+#define M_STATIC_XGPBUS_PLL_DIVQ    0x1fU
+#define V_STATIC_XGPBUS_PLL_DIVQ(x) ((x) << S_STATIC_XGPBUS_PLL_DIVQ)
+#define G_STATIC_XGPBUS_PLL_DIVQ(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVQ) & M_STATIC_XGPBUS_PLL_DIVQ)
+
+#define S_STATIC_XGPBUS_PLL_DIVFI    8
+#define M_STATIC_XGPBUS_PLL_DIVFI    0x1ffU
+#define V_STATIC_XGPBUS_PLL_DIVFI(x) ((x) << S_STATIC_XGPBUS_PLL_DIVFI)
+#define G_STATIC_XGPBUS_PLL_DIVFI(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVFI) & M_STATIC_XGPBUS_PLL_DIVFI)
+
+#define S_STATIC_XGPBUS_PLL_DIVR    2
+#define M_STATIC_XGPBUS_PLL_DIVR    0x3fU
+#define V_STATIC_XGPBUS_PLL_DIVR(x) ((x) << S_STATIC_XGPBUS_PLL_DIVR)
+#define G_STATIC_XGPBUS_PLL_DIVR(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVR) & M_STATIC_XGPBUS_PLL_DIVR)
+
+#define S_STATIC_XGPBUS_PLL_BYPASS    1
+#define V_STATIC_XGPBUS_PLL_BYPASS(x) ((x) << S_STATIC_XGPBUS_PLL_BYPASS)
+#define F_STATIC_XGPBUS_PLL_BYPASS    V_STATIC_XGPBUS_PLL_BYPASS(1U)
+
+#define S_STATIC_XGPBUS_PLL_RESET    0
+#define V_STATIC_XGPBUS_PLL_RESET(x) ((x) << S_STATIC_XGPBUS_PLL_RESET)
+#define F_STATIC_XGPBUS_PLL_RESET    V_STATIC_XGPBUS_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
 
 #define S_T5_STATIC_U_PLL_MULTFRAC    8
@@ -13164,6 +16641,26 @@
 #define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE)
 #define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE)
 
+#define A_DBG_STATIC_XGPBUS_PLL_CONF2 0x60e4
+
+#define S_STATIC_XGPBUS_PLL_SSMF    5
+#define M_STATIC_XGPBUS_PLL_SSMF    0xfU
+#define V_STATIC_XGPBUS_PLL_SSMF(x) ((x) << S_STATIC_XGPBUS_PLL_SSMF)
+#define G_STATIC_XGPBUS_PLL_SSMF(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMF) & M_STATIC_XGPBUS_PLL_SSMF)
+
+#define S_STATIC_XGPBUS_PLL_SSMD    2
+#define M_STATIC_XGPBUS_PLL_SSMD    0x7U
+#define V_STATIC_XGPBUS_PLL_SSMD(x) ((x) << S_STATIC_XGPBUS_PLL_SSMD)
+#define G_STATIC_XGPBUS_PLL_SSMD(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMD) & M_STATIC_XGPBUS_PLL_SSMD)
+
+#define S_STATIC_XGPBUS_PLL_SSDS    1
+#define V_STATIC_XGPBUS_PLL_SSDS(x) ((x) << S_STATIC_XGPBUS_PLL_SSDS)
+#define F_STATIC_XGPBUS_PLL_SSDS    V_STATIC_XGPBUS_PLL_SSDS(1U)
+
+#define S_STATIC_XGPBUS_PLL_SSE    0
+#define V_STATIC_XGPBUS_PLL_SSE(x) ((x) << S_STATIC_XGPBUS_PLL_SSE)
+#define F_STATIC_XGPBUS_PLL_SSE    V_STATIC_XGPBUS_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
 
 #define S_T5_STATIC_U_PLL_DCO_BYPASS    23
@@ -13246,6 +16743,36 @@
 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
 
+#define A_DBG_STATIC_M1_PLL_CONF1 0x60e8
+
+#define S_STATIC_M1_PLL_RANGE    22
+#define M_STATIC_M1_PLL_RANGE    0x7U
+#define V_STATIC_M1_PLL_RANGE(x) ((x) << S_STATIC_M1_PLL_RANGE)
+#define G_STATIC_M1_PLL_RANGE(x) (((x) >> S_STATIC_M1_PLL_RANGE) & M_STATIC_M1_PLL_RANGE)
+
+#define S_STATIC_M1_PLL_DIVQ    17
+#define M_STATIC_M1_PLL_DIVQ    0x1fU
+#define V_STATIC_M1_PLL_DIVQ(x) ((x) << S_STATIC_M1_PLL_DIVQ)
+#define G_STATIC_M1_PLL_DIVQ(x) (((x) >> S_STATIC_M1_PLL_DIVQ) & M_STATIC_M1_PLL_DIVQ)
+
+#define S_STATIC_M1_PLL_DIVFI    8
+#define M_STATIC_M1_PLL_DIVFI    0x1ffU
+#define V_STATIC_M1_PLL_DIVFI(x) ((x) << S_STATIC_M1_PLL_DIVFI)
+#define G_STATIC_M1_PLL_DIVFI(x) (((x) >> S_STATIC_M1_PLL_DIVFI) & M_STATIC_M1_PLL_DIVFI)
+
+#define S_STATIC_M1_PLL_DIVR    2
+#define M_STATIC_M1_PLL_DIVR    0x3fU
+#define V_STATIC_M1_PLL_DIVR(x) ((x) << S_STATIC_M1_PLL_DIVR)
+#define G_STATIC_M1_PLL_DIVR(x) (((x) >> S_STATIC_M1_PLL_DIVR) & M_STATIC_M1_PLL_DIVR)
+
+#define S_STATIC_M1_PLL_BYPASS    1
+#define V_STATIC_M1_PLL_BYPASS(x) ((x) << S_STATIC_M1_PLL_BYPASS)
+#define F_STATIC_M1_PLL_BYPASS    V_STATIC_M1_PLL_BYPASS(1U)
+
+#define S_STATIC_M1_PLL_RESET    0
+#define V_STATIC_M1_PLL_RESET(x) ((x) << S_STATIC_M1_PLL_RESET)
+#define F_STATIC_M1_PLL_RESET    V_STATIC_M1_PLL_RESET(1U)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
 
 #define S_T5_STATIC_U_PLL_MULTPRE    30
@@ -13309,6 +16836,26 @@
 #define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA)
 #define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA)
 
+#define A_DBG_STATIC_M1_PLL_CONF2 0x60ec
+
+#define S_STATIC_M1_PLL_SSMF    5
+#define M_STATIC_M1_PLL_SSMF    0xfU
+#define V_STATIC_M1_PLL_SSMF(x) ((x) << S_STATIC_M1_PLL_SSMF)
+#define G_STATIC_M1_PLL_SSMF(x) (((x) >> S_STATIC_M1_PLL_SSMF) & M_STATIC_M1_PLL_SSMF)
+
+#define S_STATIC_M1_PLL_SSMD    2
+#define M_STATIC_M1_PLL_SSMD    0x7U
+#define V_STATIC_M1_PLL_SSMD(x) ((x) << S_STATIC_M1_PLL_SSMD)
+#define G_STATIC_M1_PLL_SSMD(x) (((x) >> S_STATIC_M1_PLL_SSMD) & M_STATIC_M1_PLL_SSMD)
+
+#define S_STATIC_M1_PLL_SSDS    1
+#define V_STATIC_M1_PLL_SSDS(x) ((x) << S_STATIC_M1_PLL_SSDS)
+#define F_STATIC_M1_PLL_SSDS    V_STATIC_M1_PLL_SSDS(1U)
+
+#define S_STATIC_M1_PLL_SSE    0
+#define V_STATIC_M1_PLL_SSE(x) ((x) << S_STATIC_M1_PLL_SSE)
+#define F_STATIC_M1_PLL_SSE    V_STATIC_M1_PLL_SSE(1U)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0
 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
@@ -13557,6 +17104,104 @@
 #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
 #define F_GPIO19_OUT_VAL    V_GPIO19_OUT_VAL(1U)
 
+#define A_DBG_GPIO_OEN 0x6100
+
+#define S_GPIO23_OEN    23
+#define V_GPIO23_OEN(x) ((x) << S_GPIO23_OEN)
+#define F_GPIO23_OEN    V_GPIO23_OEN(1U)
+
+#define S_GPIO22_OEN    22
+#define V_GPIO22_OEN(x) ((x) << S_GPIO22_OEN)
+#define F_GPIO22_OEN    V_GPIO22_OEN(1U)
+
+#define S_GPIO21_OEN    21
+#define V_GPIO21_OEN(x) ((x) << S_GPIO21_OEN)
+#define F_GPIO21_OEN    V_GPIO21_OEN(1U)
+
+#define S_GPIO20_OEN    20
+#define V_GPIO20_OEN(x) ((x) << S_GPIO20_OEN)
+#define F_GPIO20_OEN    V_GPIO20_OEN(1U)
+
+#define S_T7_GPIO19_OEN    19
+#define V_T7_GPIO19_OEN(x) ((x) << S_T7_GPIO19_OEN)
+#define F_T7_GPIO19_OEN    V_T7_GPIO19_OEN(1U)
+
+#define S_T7_GPIO18_OEN    18
+#define V_T7_GPIO18_OEN(x) ((x) << S_T7_GPIO18_OEN)
+#define F_T7_GPIO18_OEN    V_T7_GPIO18_OEN(1U)
+
+#define S_T7_GPIO17_OEN    17
+#define V_T7_GPIO17_OEN(x) ((x) << S_T7_GPIO17_OEN)
+#define F_T7_GPIO17_OEN    V_T7_GPIO17_OEN(1U)
+
+#define S_T7_GPIO16_OEN    16
+#define V_T7_GPIO16_OEN(x) ((x) << S_T7_GPIO16_OEN)
+#define F_T7_GPIO16_OEN    V_T7_GPIO16_OEN(1U)
+
+#define S_T7_GPIO15_OEN    15
+#define V_T7_GPIO15_OEN(x) ((x) << S_T7_GPIO15_OEN)
+#define F_T7_GPIO15_OEN    V_T7_GPIO15_OEN(1U)
+
+#define S_T7_GPIO14_OEN    14
+#define V_T7_GPIO14_OEN(x) ((x) << S_T7_GPIO14_OEN)
+#define F_T7_GPIO14_OEN    V_T7_GPIO14_OEN(1U)
+
+#define S_T7_GPIO13_OEN    13
+#define V_T7_GPIO13_OEN(x) ((x) << S_T7_GPIO13_OEN)
+#define F_T7_GPIO13_OEN    V_T7_GPIO13_OEN(1U)
+
+#define S_T7_GPIO12_OEN    12
+#define V_T7_GPIO12_OEN(x) ((x) << S_T7_GPIO12_OEN)
+#define F_T7_GPIO12_OEN    V_T7_GPIO12_OEN(1U)
+
+#define S_T7_GPIO11_OEN    11
+#define V_T7_GPIO11_OEN(x) ((x) << S_T7_GPIO11_OEN)
+#define F_T7_GPIO11_OEN    V_T7_GPIO11_OEN(1U)
+
+#define S_T7_GPIO10_OEN    10
+#define V_T7_GPIO10_OEN(x) ((x) << S_T7_GPIO10_OEN)
+#define F_T7_GPIO10_OEN    V_T7_GPIO10_OEN(1U)
+
+#define S_T7_GPIO9_OEN    9
+#define V_T7_GPIO9_OEN(x) ((x) << S_T7_GPIO9_OEN)
+#define F_T7_GPIO9_OEN    V_T7_GPIO9_OEN(1U)
+
+#define S_T7_GPIO8_OEN    8
+#define V_T7_GPIO8_OEN(x) ((x) << S_T7_GPIO8_OEN)
+#define F_T7_GPIO8_OEN    V_T7_GPIO8_OEN(1U)
+
+#define S_T7_GPIO7_OEN    7
+#define V_T7_GPIO7_OEN(x) ((x) << S_T7_GPIO7_OEN)
+#define F_T7_GPIO7_OEN    V_T7_GPIO7_OEN(1U)
+
+#define S_T7_GPIO6_OEN    6
+#define V_T7_GPIO6_OEN(x) ((x) << S_T7_GPIO6_OEN)
+#define F_T7_GPIO6_OEN    V_T7_GPIO6_OEN(1U)
+
+#define S_T7_GPIO5_OEN    5
+#define V_T7_GPIO5_OEN(x) ((x) << S_T7_GPIO5_OEN)
+#define F_T7_GPIO5_OEN    V_T7_GPIO5_OEN(1U)
+
+#define S_T7_GPIO4_OEN    4
+#define V_T7_GPIO4_OEN(x) ((x) << S_T7_GPIO4_OEN)
+#define F_T7_GPIO4_OEN    V_T7_GPIO4_OEN(1U)
+
+#define S_T7_GPIO3_OEN    3
+#define V_T7_GPIO3_OEN(x) ((x) << S_T7_GPIO3_OEN)
+#define F_T7_GPIO3_OEN    V_T7_GPIO3_OEN(1U)
+
+#define S_T7_GPIO2_OEN    2
+#define V_T7_GPIO2_OEN(x) ((x) << S_T7_GPIO2_OEN)
+#define F_T7_GPIO2_OEN    V_T7_GPIO2_OEN(1U)
+
+#define S_T7_GPIO1_OEN    1
+#define V_T7_GPIO1_OEN(x) ((x) << S_T7_GPIO1_OEN)
+#define F_T7_GPIO1_OEN    V_T7_GPIO1_OEN(1U)
+
+#define S_T7_GPIO0_OEN    0
+#define V_T7_GPIO0_OEN(x) ((x) << S_T7_GPIO0_OEN)
+#define F_T7_GPIO0_OEN    V_T7_GPIO0_OEN(1U)
+
 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
 
 #define S_FAST_UPDATE    8
@@ -13605,6 +17250,104 @@
 #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
 #define F_GPIO16_IN    V_GPIO16_IN(1U)
 
+#define A_DBG_GPIO_CHG_DET 0x6104
+
+#define S_GPIO23_CHG_DET    23
+#define V_GPIO23_CHG_DET(x) ((x) << S_GPIO23_CHG_DET)
+#define F_GPIO23_CHG_DET    V_GPIO23_CHG_DET(1U)
+
+#define S_GPIO22_CHG_DET    22
+#define V_GPIO22_CHG_DET(x) ((x) << S_GPIO22_CHG_DET)
+#define F_GPIO22_CHG_DET    V_GPIO22_CHG_DET(1U)
+
+#define S_GPIO21_CHG_DET    21
+#define V_GPIO21_CHG_DET(x) ((x) << S_GPIO21_CHG_DET)
+#define F_GPIO21_CHG_DET    V_GPIO21_CHG_DET(1U)
+
+#define S_GPIO20_CHG_DET    20
+#define V_GPIO20_CHG_DET(x) ((x) << S_GPIO20_CHG_DET)
+#define F_GPIO20_CHG_DET    V_GPIO20_CHG_DET(1U)
+
+#define S_T7_GPIO19_CHG_DET    19
+#define V_T7_GPIO19_CHG_DET(x) ((x) << S_T7_GPIO19_CHG_DET)
+#define F_T7_GPIO19_CHG_DET    V_T7_GPIO19_CHG_DET(1U)
+
+#define S_T7_GPIO18_CHG_DET    18
+#define V_T7_GPIO18_CHG_DET(x) ((x) << S_T7_GPIO18_CHG_DET)
+#define F_T7_GPIO18_CHG_DET    V_T7_GPIO18_CHG_DET(1U)
+
+#define S_T7_GPIO17_CHG_DET    17
+#define V_T7_GPIO17_CHG_DET(x) ((x) << S_T7_GPIO17_CHG_DET)
+#define F_T7_GPIO17_CHG_DET    V_T7_GPIO17_CHG_DET(1U)
+
+#define S_T7_GPIO16_CHG_DET    16
+#define V_T7_GPIO16_CHG_DET(x) ((x) << S_T7_GPIO16_CHG_DET)
+#define F_T7_GPIO16_CHG_DET    V_T7_GPIO16_CHG_DET(1U)
+
+#define S_T7_GPIO15_CHG_DET    15
+#define V_T7_GPIO15_CHG_DET(x) ((x) << S_T7_GPIO15_CHG_DET)
+#define F_T7_GPIO15_CHG_DET    V_T7_GPIO15_CHG_DET(1U)
+
+#define S_T7_GPIO14_CHG_DET    14
+#define V_T7_GPIO14_CHG_DET(x) ((x) << S_T7_GPIO14_CHG_DET)
+#define F_T7_GPIO14_CHG_DET    V_T7_GPIO14_CHG_DET(1U)
+
+#define S_T7_GPIO13_CHG_DET    13
+#define V_T7_GPIO13_CHG_DET(x) ((x) << S_T7_GPIO13_CHG_DET)
+#define F_T7_GPIO13_CHG_DET    V_T7_GPIO13_CHG_DET(1U)
+
+#define S_T7_GPIO12_CHG_DET    12
+#define V_T7_GPIO12_CHG_DET(x) ((x) << S_T7_GPIO12_CHG_DET)
+#define F_T7_GPIO12_CHG_DET    V_T7_GPIO12_CHG_DET(1U)
+
+#define S_T7_GPIO11_CHG_DET    11
+#define V_T7_GPIO11_CHG_DET(x) ((x) << S_T7_GPIO11_CHG_DET)
+#define F_T7_GPIO11_CHG_DET    V_T7_GPIO11_CHG_DET(1U)
+
+#define S_T7_GPIO10_CHG_DET    10
+#define V_T7_GPIO10_CHG_DET(x) ((x) << S_T7_GPIO10_CHG_DET)
+#define F_T7_GPIO10_CHG_DET    V_T7_GPIO10_CHG_DET(1U)
+
+#define S_T7_GPIO9_CHG_DET    9
+#define V_T7_GPIO9_CHG_DET(x) ((x) << S_T7_GPIO9_CHG_DET)
+#define F_T7_GPIO9_CHG_DET    V_T7_GPIO9_CHG_DET(1U)
+
+#define S_T7_GPIO8_CHG_DET    8
+#define V_T7_GPIO8_CHG_DET(x) ((x) << S_T7_GPIO8_CHG_DET)
+#define F_T7_GPIO8_CHG_DET    V_T7_GPIO8_CHG_DET(1U)
+
+#define S_T7_GPIO7_CHG_DET    7
+#define V_T7_GPIO7_CHG_DET(x) ((x) << S_T7_GPIO7_CHG_DET)
+#define F_T7_GPIO7_CHG_DET    V_T7_GPIO7_CHG_DET(1U)
+
+#define S_T7_GPIO6_CHG_DET    6
+#define V_T7_GPIO6_CHG_DET(x) ((x) << S_T7_GPIO6_CHG_DET)
+#define F_T7_GPIO6_CHG_DET    V_T7_GPIO6_CHG_DET(1U)
+
+#define S_T7_GPIO5_CHG_DET    5
+#define V_T7_GPIO5_CHG_DET(x) ((x) << S_T7_GPIO5_CHG_DET)
+#define F_T7_GPIO5_CHG_DET    V_T7_GPIO5_CHG_DET(1U)
+
+#define S_T7_GPIO4_CHG_DET    4
+#define V_T7_GPIO4_CHG_DET(x) ((x) << S_T7_GPIO4_CHG_DET)
+#define F_T7_GPIO4_CHG_DET    V_T7_GPIO4_CHG_DET(1U)
+
+#define S_T7_GPIO3_CHG_DET    3
+#define V_T7_GPIO3_CHG_DET(x) ((x) << S_T7_GPIO3_CHG_DET)
+#define F_T7_GPIO3_CHG_DET    V_T7_GPIO3_CHG_DET(1U)
+
+#define S_T7_GPIO2_CHG_DET    2
+#define V_T7_GPIO2_CHG_DET(x) ((x) << S_T7_GPIO2_CHG_DET)
+#define F_T7_GPIO2_CHG_DET    V_T7_GPIO2_CHG_DET(1U)
+
+#define S_T7_GPIO1_CHG_DET    1
+#define V_T7_GPIO1_CHG_DET(x) ((x) << S_T7_GPIO1_CHG_DET)
+#define F_T7_GPIO1_CHG_DET    V_T7_GPIO1_CHG_DET(1U)
+
+#define S_T7_GPIO0_CHG_DET    0
+#define V_T7_GPIO0_CHG_DET(x) ((x) << S_T7_GPIO0_CHG_DET)
+#define F_T7_GPIO0_CHG_DET    V_T7_GPIO0_CHG_DET(1U)
+
 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
 
 #define S_LAST_MEASUREMENT_SELECT    8
@@ -13964,6 +17707,22 @@
 #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
 #define F_GPIO0_PE_EN    V_GPIO0_PE_EN(1U)
 
+#define S_GPIO23_PE_EN    23
+#define V_GPIO23_PE_EN(x) ((x) << S_GPIO23_PE_EN)
+#define F_GPIO23_PE_EN    V_GPIO23_PE_EN(1U)
+
+#define S_GPIO22_PE_EN    22
+#define V_GPIO22_PE_EN(x) ((x) << S_GPIO22_PE_EN)
+#define F_GPIO22_PE_EN    V_GPIO22_PE_EN(1U)
+
+#define S_GPIO21_PE_EN    21
+#define V_GPIO21_PE_EN(x) ((x) << S_GPIO21_PE_EN)
+#define F_GPIO21_PE_EN    V_GPIO21_PE_EN(1U)
+
+#define S_GPIO20_PE_EN    20
+#define V_GPIO20_PE_EN(x) ((x) << S_GPIO20_PE_EN)
+#define F_GPIO20_PE_EN    V_GPIO20_PE_EN(1U)
+
 #define A_DBG_PVT_REG_THRESHOLD 0x611c
 
 #define S_PVT_CALIBRATION_DONE    8
@@ -14084,6 +17843,22 @@
 #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
 #define F_GPIO0_PS_EN    V_GPIO0_PS_EN(1U)
 
+#define S_GPIO23_PS_EN    23
+#define V_GPIO23_PS_EN(x) ((x) << S_GPIO23_PS_EN)
+#define F_GPIO23_PS_EN    V_GPIO23_PS_EN(1U)
+
+#define S_GPIO22_PS_EN    22
+#define V_GPIO22_PS_EN(x) ((x) << S_GPIO22_PS_EN)
+#define F_GPIO22_PS_EN    V_GPIO22_PS_EN(1U)
+
+#define S_GPIO21_PS_EN    21
+#define V_GPIO21_PS_EN(x) ((x) << S_GPIO21_PS_EN)
+#define F_GPIO21_PS_EN    V_GPIO21_PS_EN(1U)
+
+#define S_GPIO20_PS_EN    20
+#define V_GPIO20_PS_EN(x) ((x) << S_GPIO20_PS_EN)
+#define F_GPIO20_PS_EN    V_GPIO20_PS_EN(1U)
+
 #define A_DBG_PVT_REG_IN_TERMP 0x6120
 
 #define S_REG_IN_TERMP_B    4
@@ -14254,6 +18029,17 @@
 #define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE)
 #define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE)
 
+#define A_DBG_STATIC_PLL_LOCK_WAIT_CONF 0x6150
+
+#define S_STATIC_WAIT_LOCK    24
+#define V_STATIC_WAIT_LOCK(x) ((x) << S_STATIC_WAIT_LOCK)
+#define F_STATIC_WAIT_LOCK    V_STATIC_WAIT_LOCK(1U)
+
+#define S_STATIC_LOCK_WAIT_TIME    0
+#define M_STATIC_LOCK_WAIT_TIME    0xffffffU
+#define V_STATIC_LOCK_WAIT_TIME(x) ((x) << S_STATIC_LOCK_WAIT_TIME)
+#define G_STATIC_LOCK_WAIT_TIME(x) (((x) >> S_STATIC_LOCK_WAIT_TIME) & M_STATIC_LOCK_WAIT_TIME)
+
 #define A_DBG_STATIC_C_PLL_CONF6 0x6154
 
 #define S_STATIC_C_PLL_VREGTUNE    0
@@ -14303,13 +18089,274 @@
 #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
 #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
+#define A_DBG_GPIO_INT_ENABLE 0x6180
+
+#define S_GPIO23    23
+#define V_GPIO23(x) ((x) << S_GPIO23)
+#define F_GPIO23    V_GPIO23(1U)
+
+#define S_GPIO22    22
+#define V_GPIO22(x) ((x) << S_GPIO22)
+#define F_GPIO22    V_GPIO22(1U)
+
+#define S_GPIO21    21
+#define V_GPIO21(x) ((x) << S_GPIO21)
+#define F_GPIO21    V_GPIO21(1U)
+
+#define S_GPIO20    20
+#define V_GPIO20(x) ((x) << S_GPIO20)
+#define F_GPIO20    V_GPIO20(1U)
+
+#define S_T7_GPIO19    19
+#define V_T7_GPIO19(x) ((x) << S_T7_GPIO19)
+#define F_T7_GPIO19    V_T7_GPIO19(1U)
+
+#define S_T7_GPIO18    18
+#define V_T7_GPIO18(x) ((x) << S_T7_GPIO18)
+#define F_T7_GPIO18    V_T7_GPIO18(1U)
+
+#define S_T7_GPIO17    17
+#define V_T7_GPIO17(x) ((x) << S_T7_GPIO17)
+#define F_T7_GPIO17    V_T7_GPIO17(1U)
+
+#define S_T7_GPIO16    16
+#define V_T7_GPIO16(x) ((x) << S_T7_GPIO16)
+#define F_T7_GPIO16    V_T7_GPIO16(1U)
+
 #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
+#define A_DBG_GPIO_INT_CAUSE 0x6184
 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
+#define A_T7_DBG_GPIO_ACT_LOW 0x6188
+
+#define S_GPIO23_ACT_LOW    23
+#define V_GPIO23_ACT_LOW(x) ((x) << S_GPIO23_ACT_LOW)
+#define F_GPIO23_ACT_LOW    V_GPIO23_ACT_LOW(1U)
+
+#define S_GPIO22_ACT_LOW    22
+#define V_GPIO22_ACT_LOW(x) ((x) << S_GPIO22_ACT_LOW)
+#define F_GPIO22_ACT_LOW    V_GPIO22_ACT_LOW(1U)
+
+#define S_GPIO21_ACT_LOW    21
+#define V_GPIO21_ACT_LOW(x) ((x) << S_GPIO21_ACT_LOW)
+#define F_GPIO21_ACT_LOW    V_GPIO21_ACT_LOW(1U)
+
+#define S_GPIO20_ACT_LOW    20
+#define V_GPIO20_ACT_LOW(x) ((x) << S_GPIO20_ACT_LOW)
+#define F_GPIO20_ACT_LOW    V_GPIO20_ACT_LOW(1U)
+
+#define S_T7_GPIO19_ACT_LOW    19
+#define V_T7_GPIO19_ACT_LOW(x) ((x) << S_T7_GPIO19_ACT_LOW)
+#define F_T7_GPIO19_ACT_LOW    V_T7_GPIO19_ACT_LOW(1U)
+
+#define S_T7_GPIO18_ACT_LOW    18
+#define V_T7_GPIO18_ACT_LOW(x) ((x) << S_T7_GPIO18_ACT_LOW)
+#define F_T7_GPIO18_ACT_LOW    V_T7_GPIO18_ACT_LOW(1U)
+
+#define S_T7_GPIO17_ACT_LOW    17
+#define V_T7_GPIO17_ACT_LOW(x) ((x) << S_T7_GPIO17_ACT_LOW)
+#define F_T7_GPIO17_ACT_LOW    V_T7_GPIO17_ACT_LOW(1U)
+
+#define S_T7_GPIO16_ACT_LOW    16
+#define V_T7_GPIO16_ACT_LOW(x) ((x) << S_T7_GPIO16_ACT_LOW)
+#define F_T7_GPIO16_ACT_LOW    V_T7_GPIO16_ACT_LOW(1U)
+
 #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
+#define A_DBG_DDR_CAL 0x618c
+
+#define S_CAL_ENDC    9
+#define V_CAL_ENDC(x) ((x) << S_CAL_ENDC)
+#define F_CAL_ENDC    V_CAL_ENDC(1U)
+
+#define S_CAL_MODE    8
+#define V_CAL_MODE(x) ((x) << S_CAL_MODE)
+#define F_CAL_MODE    V_CAL_MODE(1U)
+
+#define S_CAL_REFSEL    7
+#define V_CAL_REFSEL(x) ((x) << S_CAL_REFSEL)
+#define F_CAL_REFSEL    V_CAL_REFSEL(1U)
+
+#define S_PD    6
+#define V_PD(x) ((x) << S_PD)
+#define F_PD    V_PD(1U)
+
+#define S_CAL_RST    5
+#define V_CAL_RST(x) ((x) << S_CAL_RST)
+#define F_CAL_RST    V_CAL_RST(1U)
+
+#define S_CAL_READ    4
+#define V_CAL_READ(x) ((x) << S_CAL_READ)
+#define F_CAL_READ    V_CAL_READ(1U)
+
+#define S_CAL_SC    3
+#define V_CAL_SC(x) ((x) << S_CAL_SC)
+#define F_CAL_SC    V_CAL_SC(1U)
+
+#define S_CAL_LC    2
+#define V_CAL_LC(x) ((x) << S_CAL_LC)
+#define F_CAL_LC    V_CAL_LC(1U)
+
+#define S_CAL_CCAL    1
+#define V_CAL_CCAL(x) ((x) << S_CAL_CCAL)
+#define F_CAL_CCAL    V_CAL_CCAL(1U)
+
+#define S_CAL_RES    0
+#define V_CAL_RES(x) ((x) << S_CAL_RES)
+#define F_CAL_RES    V_CAL_RES(1U)
+
 #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
+#define A_DBG_EFUSE_CTL_0 0x6190
+
+#define S_EFUSE_CSB    31
+#define V_EFUSE_CSB(x) ((x) << S_EFUSE_CSB)
+#define F_EFUSE_CSB    V_EFUSE_CSB(1U)
+
+#define S_EFUSE_STROBE    30
+#define V_EFUSE_STROBE(x) ((x) << S_EFUSE_STROBE)
+#define F_EFUSE_STROBE    V_EFUSE_STROBE(1U)
+
+#define S_EFUSE_LOAD    29
+#define V_EFUSE_LOAD(x) ((x) << S_EFUSE_LOAD)
+#define F_EFUSE_LOAD    V_EFUSE_LOAD(1U)
+
+#define S_EFUSE_PGENB    28
+#define V_EFUSE_PGENB(x) ((x) << S_EFUSE_PGENB)
+#define F_EFUSE_PGENB    V_EFUSE_PGENB(1U)
+
+#define S_EFUSE_PS    27
+#define V_EFUSE_PS(x) ((x) << S_EFUSE_PS)
+#define F_EFUSE_PS    V_EFUSE_PS(1U)
+
+#define S_EFUSE_MR    26
+#define V_EFUSE_MR(x) ((x) << S_EFUSE_MR)
+#define F_EFUSE_MR    V_EFUSE_MR(1U)
+
+#define S_EFUSE_PD    25
+#define V_EFUSE_PD(x) ((x) << S_EFUSE_PD)
+#define F_EFUSE_PD    V_EFUSE_PD(1U)
+
+#define S_EFUSE_RWL    24
+#define V_EFUSE_RWL(x) ((x) << S_EFUSE_RWL)
+#define F_EFUSE_RWL    V_EFUSE_RWL(1U)
+
+#define S_EFUSE_RSB    23
+#define V_EFUSE_RSB(x) ((x) << S_EFUSE_RSB)
+#define F_EFUSE_RSB    V_EFUSE_RSB(1U)
+
+#define S_EFUSE_TRCS    22
+#define V_EFUSE_TRCS(x) ((x) << S_EFUSE_TRCS)
+#define F_EFUSE_TRCS    V_EFUSE_TRCS(1U)
+
+#define S_EFUSE_AT    20
+#define M_EFUSE_AT    0x3U
+#define V_EFUSE_AT(x) ((x) << S_EFUSE_AT)
+#define G_EFUSE_AT(x) (((x) >> S_EFUSE_AT) & M_EFUSE_AT)
+
+#define S_EFUSE_RD_STATE    16
+#define M_EFUSE_RD_STATE    0xfU
+#define V_EFUSE_RD_STATE(x) ((x) << S_EFUSE_RD_STATE)
+#define G_EFUSE_RD_STATE(x) (((x) >> S_EFUSE_RD_STATE) & M_EFUSE_RD_STATE)
+
+#define S_EFUSE_BUSY    15
+#define V_EFUSE_BUSY(x) ((x) << S_EFUSE_BUSY)
+#define F_EFUSE_BUSY    V_EFUSE_BUSY(1U)
+
+#define S_EFUSE_WR_RD    13
+#define M_EFUSE_WR_RD    0x3U
+#define V_EFUSE_WR_RD(x) ((x) << S_EFUSE_WR_RD)
+#define G_EFUSE_WR_RD(x) (((x) >> S_EFUSE_WR_RD) & M_EFUSE_WR_RD)
+
+#define S_EFUSE_A    0
+#define M_EFUSE_A    0x7ffU
+#define V_EFUSE_A(x) ((x) << S_EFUSE_A)
+#define G_EFUSE_A(x) (((x) >> S_EFUSE_A) & M_EFUSE_A)
+
 #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
+#define A_DBG_EFUSE_CTL_1 0x6194
 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
+#define A_DBG_EFUSE_RD_CTL 0x6198
+
+#define S_EFUSE_RD_ID    6
+#define M_EFUSE_RD_ID    0x3U
+#define V_EFUSE_RD_ID(x) ((x) << S_EFUSE_RD_ID)
+#define G_EFUSE_RD_ID(x) (((x) >> S_EFUSE_RD_ID) & M_EFUSE_RD_ID)
+
+#define S_EFUSE_RD_ADDR    0
+#define M_EFUSE_RD_ADDR    0x3fU
+#define V_EFUSE_RD_ADDR(x) ((x) << S_EFUSE_RD_ADDR)
+#define G_EFUSE_RD_ADDR(x) (((x) >> S_EFUSE_RD_ADDR) & M_EFUSE_RD_ADDR)
+
 #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
+#define A_DBG_EFUSE_RD_DATA 0x619c
+#define A_DBG_EFUSE_TIME_0 0x61a0
+
+#define S_EFUSE_TIME_1    16
+#define M_EFUSE_TIME_1    0xffffU
+#define V_EFUSE_TIME_1(x) ((x) << S_EFUSE_TIME_1)
+#define G_EFUSE_TIME_1(x) (((x) >> S_EFUSE_TIME_1) & M_EFUSE_TIME_1)
+
+#define S_EFUSE_TIME_0    0
+#define M_EFUSE_TIME_0    0xffffU
+#define V_EFUSE_TIME_0(x) ((x) << S_EFUSE_TIME_0)
+#define G_EFUSE_TIME_0(x) (((x) >> S_EFUSE_TIME_0) & M_EFUSE_TIME_0)
+
+#define A_DBG_EFUSE_TIME_1 0x61a4
+
+#define S_EFUSE_TIME_3    16
+#define M_EFUSE_TIME_3    0xffffU
+#define V_EFUSE_TIME_3(x) ((x) << S_EFUSE_TIME_3)
+#define G_EFUSE_TIME_3(x) (((x) >> S_EFUSE_TIME_3) & M_EFUSE_TIME_3)
+
+#define S_EFUSE_TIME_2    0
+#define M_EFUSE_TIME_2    0xffffU
+#define V_EFUSE_TIME_2(x) ((x) << S_EFUSE_TIME_2)
+#define G_EFUSE_TIME_2(x) (((x) >> S_EFUSE_TIME_2) & M_EFUSE_TIME_2)
+
+#define A_DBG_EFUSE_TIME_2 0x61a8
+
+#define S_EFUSE_TIME_5    16
+#define M_EFUSE_TIME_5    0xffffU
+#define V_EFUSE_TIME_5(x) ((x) << S_EFUSE_TIME_5)
+#define G_EFUSE_TIME_5(x) (((x) >> S_EFUSE_TIME_5) & M_EFUSE_TIME_5)
+
+#define S_EFUSE_TIME_4    0
+#define M_EFUSE_TIME_4    0xffffU
+#define V_EFUSE_TIME_4(x) ((x) << S_EFUSE_TIME_4)
+#define G_EFUSE_TIME_4(x) (((x) >> S_EFUSE_TIME_4) & M_EFUSE_TIME_4)
+
+#define A_DBG_EFUSE_TIME_3 0x61ac
+
+#define S_EFUSE_TIME_7    16
+#define M_EFUSE_TIME_7    0xffffU
+#define V_EFUSE_TIME_7(x) ((x) << S_EFUSE_TIME_7)
+#define G_EFUSE_TIME_7(x) (((x) >> S_EFUSE_TIME_7) & M_EFUSE_TIME_7)
+
+#define S_EFUSE_TIME_6    0
+#define M_EFUSE_TIME_6    0xffffU
+#define V_EFUSE_TIME_6(x) ((x) << S_EFUSE_TIME_6)
+#define G_EFUSE_TIME_6(x) (((x) >> S_EFUSE_TIME_6) & M_EFUSE_TIME_6)
+
+#define A_DBG_VREF_CTL 0x61b0
+
+#define S_VREF_SEL_1    15
+#define V_VREF_SEL_1(x) ((x) << S_VREF_SEL_1)
+#define F_VREF_SEL_1    V_VREF_SEL_1(1U)
+
+#define S_VREF_R_1    8
+#define M_VREF_R_1    0x7fU
+#define V_VREF_R_1(x) ((x) << S_VREF_R_1)
+#define G_VREF_R_1(x) (((x) >> S_VREF_R_1) & M_VREF_R_1)
+
+#define S_VREF_SEL_0    7
+#define V_VREF_SEL_0(x) ((x) << S_VREF_SEL_0)
+#define F_VREF_SEL_0    V_VREF_SEL_0(1U)
+
+#define S_VREF_R_0    0
+#define M_VREF_R_0    0x7fU
+#define V_VREF_R_0(x) ((x) << S_VREF_R_0)
+#define G_VREF_R_0(x) (((x) >> S_VREF_R_0) & M_VREF_R_0)
+
+#define A_DBG_FPGA_EFUSE_CTL 0x61b4
+#define A_DBG_FPGA_EFUSE_DATA 0x61b8
 
 /* registers for module MC */
 #define MC_BASE_ADDR 0x6200
@@ -16048,31 +20095,91 @@
 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
 #define F_THRESHOLD0_EN    V_THRESHOLD0_EN(1U)
 
+#define A_MA_CLIENT0_PR_THRESHOLD 0x7700
+
+#define S_T7_THRESHOLD1_EN    31
+#define V_T7_THRESHOLD1_EN(x) ((x) << S_T7_THRESHOLD1_EN)
+#define F_T7_THRESHOLD1_EN    V_T7_THRESHOLD1_EN(1U)
+
+#define S_T7_THRESHOLD1    16
+#define M_T7_THRESHOLD1    0x7fffU
+#define V_T7_THRESHOLD1(x) ((x) << S_T7_THRESHOLD1)
+#define G_T7_THRESHOLD1(x) (((x) >> S_T7_THRESHOLD1) & M_T7_THRESHOLD1)
+
+#define S_T7_THRESHOLD0_EN    15
+#define V_T7_THRESHOLD0_EN(x) ((x) << S_T7_THRESHOLD0_EN)
+#define F_T7_THRESHOLD0_EN    V_T7_THRESHOLD0_EN(1U)
+
+#define S_T7_THRESHOLD0    0
+#define M_T7_THRESHOLD0    0x7fffU
+#define V_T7_THRESHOLD0(x) ((x) << S_T7_THRESHOLD0)
+#define G_T7_THRESHOLD0(x) (((x) >> S_T7_THRESHOLD0) & M_T7_THRESHOLD0)
+
 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
+#define A_MA_CLIENT0_CR_THRESHOLD 0x7704
+
+#define S_CREDITSHAPER_EN    31
+#define V_CREDITSHAPER_EN(x) ((x) << S_CREDITSHAPER_EN)
+#define F_CREDITSHAPER_EN    V_CREDITSHAPER_EN(1U)
+
+#define S_CREDIT_MAX    16
+#define M_CREDIT_MAX    0xfffU
+#define V_CREDIT_MAX(x) ((x) << S_CREDIT_MAX)
+#define G_CREDIT_MAX(x) (((x) >> S_CREDIT_MAX) & M_CREDIT_MAX)
+
+#define S_CREDIT_VAL    0
+#define M_CREDIT_VAL    0xfffU
+#define V_CREDIT_VAL(x) ((x) << S_CREDIT_VAL)
+#define G_CREDIT_VAL(x) (((x) >> S_CREDIT_VAL) & M_CREDIT_VAL)
+
 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
+#define A_MA_CLIENT1_PR_THRESHOLD 0x7708
 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
+#define A_MA_CLIENT1_CR_THRESHOLD 0x770c
 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
+#define A_MA_CLIENT2_PR_THRESHOLD 0x7710
 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
+#define A_MA_CLIENT2_CR_THRESHOLD 0x7714
 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
+#define A_MA_CLIENT3_PR_THRESHOLD 0x7718
 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
+#define A_MA_CLIENT3_CR_THRESHOLD 0x771c
 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
+#define A_MA_CLIENT4_PR_THRESHOLD 0x7720
 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
+#define A_MA_CLIENT4_CR_THRESHOLD 0x7724
 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
+#define A_MA_CLIENT5_PR_THRESHOLD 0x7728
 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
+#define A_MA_CLIENT5_CR_THRESHOLD 0x772c
 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
+#define A_MA_CLIENT6_PR_THRESHOLD 0x7730
 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
+#define A_MA_CLIENT6_CR_THRESHOLD 0x7734
 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
+#define A_MA_CLIENT7_PR_THRESHOLD 0x7738
 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
+#define A_MA_CLIENT7_CR_THRESHOLD 0x773c
 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
+#define A_MA_CLIENT8_PR_THRESHOLD 0x7740
 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
+#define A_MA_CLIENT8_CR_THRESHOLD 0x7744
 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
+#define A_MA_CLIENT9_PR_THRESHOLD 0x7748
 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
+#define A_MA_CLIENT9_CR_THRESHOLD 0x774c
 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
+#define A_MA_CLIENT10_PR_THRESHOLD 0x7750
 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
+#define A_MA_CLIENT10_CR_THRESHOLD 0x7754
 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
+#define A_MA_CLIENT11_PR_THRESHOLD 0x7758
 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
+#define A_MA_CLIENT11_CR_THRESHOLD 0x775c
 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
+#define A_MA_CLIENT12_PR_THRESHOLD 0x7760
 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
+#define A_MA_CLIENT12_CR_THRESHOLD 0x7764
 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
 
 #define S_DBG_READ_DATA_CNT    24
@@ -16103,10 +20210,359 @@
 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
 #define A_MA_LE_DEBUG_CNT 0x7784
 #define A_MA_CIM_DEBUG_CNT 0x7788
+#define A_MA_CIM_TH0_DEBUG_CNT 0x7788
 #define A_MA_PCIE_DEBUG_CNT 0x778c
 #define A_MA_PMTX_DEBUG_CNT 0x7790
 #define A_MA_PMRX_DEBUG_CNT 0x7794
 #define A_MA_HMA_DEBUG_CNT 0x7798
+#define A_MA_COR_ERROR_ENABLE1 0x779c
+
+#define S_ARB4_COR_WRQUEUE_ERROR_EN    9
+#define V_ARB4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR_EN)
+#define F_ARB4_COR_WRQUEUE_ERROR_EN    V_ARB4_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB3_COR_WRQUEUE_ERROR_EN    8
+#define V_ARB3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR_EN)
+#define F_ARB3_COR_WRQUEUE_ERROR_EN    V_ARB3_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB2_COR_WRQUEUE_ERROR_EN    7
+#define V_ARB2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR_EN)
+#define F_ARB2_COR_WRQUEUE_ERROR_EN    V_ARB2_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB1_COR_WRQUEUE_ERROR_EN    6
+#define V_ARB1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR_EN)
+#define F_ARB1_COR_WRQUEUE_ERROR_EN    V_ARB1_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB0_COR_WRQUEUE_ERROR_EN    5
+#define V_ARB0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR_EN)
+#define F_ARB0_COR_WRQUEUE_ERROR_EN    V_ARB0_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB4_COR_RDQUEUE_ERROR_EN    4
+#define V_ARB4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR_EN)
+#define F_ARB4_COR_RDQUEUE_ERROR_EN    V_ARB4_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB3_COR_RDQUEUE_ERROR_EN    3
+#define V_ARB3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR_EN)
+#define F_ARB3_COR_RDQUEUE_ERROR_EN    V_ARB3_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB2_COR_RDQUEUE_ERROR_EN    2
+#define V_ARB2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR_EN)
+#define F_ARB2_COR_RDQUEUE_ERROR_EN    V_ARB2_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB1_COR_RDQUEUE_ERROR_EN    1
+#define V_ARB1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR_EN)
+#define F_ARB1_COR_RDQUEUE_ERROR_EN    V_ARB1_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB0_COR_RDQUEUE_ERROR_EN    0
+#define V_ARB0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR_EN)
+#define F_ARB0_COR_RDQUEUE_ERROR_EN    V_ARB0_COR_RDQUEUE_ERROR_EN(1U)
+
+#define A_MA_COR_ERROR_STATUS1 0x77a0
+
+#define S_ARB4_COR_WRQUEUE_ERROR    9
+#define V_ARB4_COR_WRQUEUE_ERROR(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR)
+#define F_ARB4_COR_WRQUEUE_ERROR    V_ARB4_COR_WRQUEUE_ERROR(1U)
+
+#define S_ARB3_COR_WRQUEUE_ERROR    8
+#define V_ARB3_COR_WRQUEUE_ERROR(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR)
+#define F_ARB3_COR_WRQUEUE_ERROR    V_ARB3_COR_WRQUEUE_ERROR(1U)
+
+#define S_ARB2_COR_WRQUEUE_ERROR    7
+#define V_ARB2_COR_WRQUEUE_ERROR(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR)
+#define F_ARB2_COR_WRQUEUE_ERROR    V_ARB2_COR_WRQUEUE_ERROR(1U)
+
+#define S_ARB1_COR_WRQUEUE_ERROR    6
+#define V_ARB1_COR_WRQUEUE_ERROR(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR)
+#define F_ARB1_COR_WRQUEUE_ERROR    V_ARB1_COR_WRQUEUE_ERROR(1U)
+
+#define S_ARB0_COR_WRQUEUE_ERROR    5
+#define V_ARB0_COR_WRQUEUE_ERROR(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR)
+#define F_ARB0_COR_WRQUEUE_ERROR    V_ARB0_COR_WRQUEUE_ERROR(1U)
+
+#define S_ARB4_COR_RDQUEUE_ERROR    4
+#define V_ARB4_COR_RDQUEUE_ERROR(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR)
+#define F_ARB4_COR_RDQUEUE_ERROR    V_ARB4_COR_RDQUEUE_ERROR(1U)
+
+#define S_ARB3_COR_RDQUEUE_ERROR    3
+#define V_ARB3_COR_RDQUEUE_ERROR(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR)
+#define F_ARB3_COR_RDQUEUE_ERROR    V_ARB3_COR_RDQUEUE_ERROR(1U)
+
+#define S_ARB2_COR_RDQUEUE_ERROR    2
+#define V_ARB2_COR_RDQUEUE_ERROR(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR)
+#define F_ARB2_COR_RDQUEUE_ERROR    V_ARB2_COR_RDQUEUE_ERROR(1U)
+
+#define S_ARB1_COR_RDQUEUE_ERROR    1
+#define V_ARB1_COR_RDQUEUE_ERROR(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR)
+#define F_ARB1_COR_RDQUEUE_ERROR    V_ARB1_COR_RDQUEUE_ERROR(1U)
+
+#define S_ARB0_COR_RDQUEUE_ERROR    0
+#define V_ARB0_COR_RDQUEUE_ERROR(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR)
+#define F_ARB0_COR_RDQUEUE_ERROR    V_ARB0_COR_RDQUEUE_ERROR(1U)
+
+#define A_MA_DBG_CTL 0x77a4
+
+#define S_DATAH_SEL    20
+#define V_DATAH_SEL(x) ((x) << S_DATAH_SEL)
+#define F_DATAH_SEL    V_DATAH_SEL(1U)
+
+#define S_EN_DBG    16
+#define V_EN_DBG(x) ((x) << S_EN_DBG)
+#define F_EN_DBG    V_EN_DBG(1U)
+
+#define S_T7_SEL    0
+#define M_T7_SEL    0xffU
+#define V_T7_SEL(x) ((x) << S_T7_SEL)
+#define G_T7_SEL(x) (((x) >> S_T7_SEL) & M_T7_SEL)
+
+#define A_MA_DBG_DATA 0x77a8
+#define A_MA_COR_ERROR_ENABLE2 0x77b0
+
+#define S_CL14_COR_WRQUEUE_ERROR_EN    14
+#define V_CL14_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_WRQUEUE_ERROR_EN)
+#define F_CL14_COR_WRQUEUE_ERROR_EN    V_CL14_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL13_COR_WRQUEUE_ERROR_EN    13
+#define V_CL13_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_WRQUEUE_ERROR_EN)
+#define F_CL13_COR_WRQUEUE_ERROR_EN    V_CL13_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL12_COR_WRQUEUE_ERROR_EN    12
+#define V_CL12_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_WRQUEUE_ERROR_EN)
+#define F_CL12_COR_WRQUEUE_ERROR_EN    V_CL12_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL11_COR_WRQUEUE_ERROR_EN    11
+#define V_CL11_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_WRQUEUE_ERROR_EN)
+#define F_CL11_COR_WRQUEUE_ERROR_EN    V_CL11_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL10_COR_WRQUEUE_ERROR_EN    10
+#define V_CL10_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_WRQUEUE_ERROR_EN)
+#define F_CL10_COR_WRQUEUE_ERROR_EN    V_CL10_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL9_COR_WRQUEUE_ERROR_EN    9
+#define V_CL9_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_WRQUEUE_ERROR_EN)
+#define F_CL9_COR_WRQUEUE_ERROR_EN    V_CL9_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL8_COR_WRQUEUE_ERROR_EN    8
+#define V_CL8_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_WRQUEUE_ERROR_EN)
+#define F_CL8_COR_WRQUEUE_ERROR_EN    V_CL8_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL7_COR_WRQUEUE_ERROR_EN    7
+#define V_CL7_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_WRQUEUE_ERROR_EN)
+#define F_CL7_COR_WRQUEUE_ERROR_EN    V_CL7_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL6_COR_WRQUEUE_ERROR_EN    6
+#define V_CL6_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_WRQUEUE_ERROR_EN)
+#define F_CL6_COR_WRQUEUE_ERROR_EN    V_CL6_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL5_COR_WRQUEUE_ERROR_EN    5
+#define V_CL5_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_WRQUEUE_ERROR_EN)
+#define F_CL5_COR_WRQUEUE_ERROR_EN    V_CL5_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL4_COR_WRQUEUE_ERROR_EN    4
+#define V_CL4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_WRQUEUE_ERROR_EN)
+#define F_CL4_COR_WRQUEUE_ERROR_EN    V_CL4_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL3_COR_WRQUEUE_ERROR_EN    3
+#define V_CL3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_WRQUEUE_ERROR_EN)
+#define F_CL3_COR_WRQUEUE_ERROR_EN    V_CL3_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL2_COR_WRQUEUE_ERROR_EN    2
+#define V_CL2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_WRQUEUE_ERROR_EN)
+#define F_CL2_COR_WRQUEUE_ERROR_EN    V_CL2_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL1_COR_WRQUEUE_ERROR_EN    1
+#define V_CL1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_WRQUEUE_ERROR_EN)
+#define F_CL1_COR_WRQUEUE_ERROR_EN    V_CL1_COR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL0_COR_WRQUEUE_ERROR_EN    0
+#define V_CL0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_WRQUEUE_ERROR_EN)
+#define F_CL0_COR_WRQUEUE_ERROR_EN    V_CL0_COR_WRQUEUE_ERROR_EN(1U)
+
+#define A_MA_COR_ERROR_STATUS2 0x77b4
+
+#define S_CL14_COR_WRQUEUE_ERROR    14
+#define V_CL14_COR_WRQUEUE_ERROR(x) ((x) << S_CL14_COR_WRQUEUE_ERROR)
+#define F_CL14_COR_WRQUEUE_ERROR    V_CL14_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL13_COR_WRQUEUE_ERROR    13
+#define V_CL13_COR_WRQUEUE_ERROR(x) ((x) << S_CL13_COR_WRQUEUE_ERROR)
+#define F_CL13_COR_WRQUEUE_ERROR    V_CL13_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL12_COR_WRQUEUE_ERROR    12
+#define V_CL12_COR_WRQUEUE_ERROR(x) ((x) << S_CL12_COR_WRQUEUE_ERROR)
+#define F_CL12_COR_WRQUEUE_ERROR    V_CL12_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL11_COR_WRQUEUE_ERROR    11
+#define V_CL11_COR_WRQUEUE_ERROR(x) ((x) << S_CL11_COR_WRQUEUE_ERROR)
+#define F_CL11_COR_WRQUEUE_ERROR    V_CL11_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL10_COR_WRQUEUE_ERROR    10
+#define V_CL10_COR_WRQUEUE_ERROR(x) ((x) << S_CL10_COR_WRQUEUE_ERROR)
+#define F_CL10_COR_WRQUEUE_ERROR    V_CL10_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL9_COR_WRQUEUE_ERROR    9
+#define V_CL9_COR_WRQUEUE_ERROR(x) ((x) << S_CL9_COR_WRQUEUE_ERROR)
+#define F_CL9_COR_WRQUEUE_ERROR    V_CL9_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL8_COR_WRQUEUE_ERROR    8
+#define V_CL8_COR_WRQUEUE_ERROR(x) ((x) << S_CL8_COR_WRQUEUE_ERROR)
+#define F_CL8_COR_WRQUEUE_ERROR    V_CL8_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL7_COR_WRQUEUE_ERROR    7
+#define V_CL7_COR_WRQUEUE_ERROR(x) ((x) << S_CL7_COR_WRQUEUE_ERROR)
+#define F_CL7_COR_WRQUEUE_ERROR    V_CL7_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL6_COR_WRQUEUE_ERROR    6
+#define V_CL6_COR_WRQUEUE_ERROR(x) ((x) << S_CL6_COR_WRQUEUE_ERROR)
+#define F_CL6_COR_WRQUEUE_ERROR    V_CL6_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL5_COR_WRQUEUE_ERROR    5
+#define V_CL5_COR_WRQUEUE_ERROR(x) ((x) << S_CL5_COR_WRQUEUE_ERROR)
+#define F_CL5_COR_WRQUEUE_ERROR    V_CL5_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL4_COR_WRQUEUE_ERROR    4
+#define V_CL4_COR_WRQUEUE_ERROR(x) ((x) << S_CL4_COR_WRQUEUE_ERROR)
+#define F_CL4_COR_WRQUEUE_ERROR    V_CL4_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL3_COR_WRQUEUE_ERROR    3
+#define V_CL3_COR_WRQUEUE_ERROR(x) ((x) << S_CL3_COR_WRQUEUE_ERROR)
+#define F_CL3_COR_WRQUEUE_ERROR    V_CL3_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL2_COR_WRQUEUE_ERROR    2
+#define V_CL2_COR_WRQUEUE_ERROR(x) ((x) << S_CL2_COR_WRQUEUE_ERROR)
+#define F_CL2_COR_WRQUEUE_ERROR    V_CL2_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL1_COR_WRQUEUE_ERROR    1
+#define V_CL1_COR_WRQUEUE_ERROR(x) ((x) << S_CL1_COR_WRQUEUE_ERROR)
+#define F_CL1_COR_WRQUEUE_ERROR    V_CL1_COR_WRQUEUE_ERROR(1U)
+
+#define S_CL0_COR_WRQUEUE_ERROR    0
+#define V_CL0_COR_WRQUEUE_ERROR(x) ((x) << S_CL0_COR_WRQUEUE_ERROR)
+#define F_CL0_COR_WRQUEUE_ERROR    V_CL0_COR_WRQUEUE_ERROR(1U)
+
+#define A_MA_COR_ERROR_ENABLE3 0x77b8
+
+#define S_CL14_COR_RDQUEUE_ERROR_EN    14
+#define V_CL14_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_RDQUEUE_ERROR_EN)
+#define F_CL14_COR_RDQUEUE_ERROR_EN    V_CL14_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL13_COR_RDQUEUE_ERROR_EN    13
+#define V_CL13_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_RDQUEUE_ERROR_EN)
+#define F_CL13_COR_RDQUEUE_ERROR_EN    V_CL13_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL12_COR_RDQUEUE_ERROR_EN    12
+#define V_CL12_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_RDQUEUE_ERROR_EN)
+#define F_CL12_COR_RDQUEUE_ERROR_EN    V_CL12_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL11_COR_RDQUEUE_ERROR_EN    11
+#define V_CL11_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_RDQUEUE_ERROR_EN)
+#define F_CL11_COR_RDQUEUE_ERROR_EN    V_CL11_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL10_COR_RDQUEUE_ERROR_EN    10
+#define V_CL10_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_RDQUEUE_ERROR_EN)
+#define F_CL10_COR_RDQUEUE_ERROR_EN    V_CL10_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL9_COR_RDQUEUE_ERROR_EN    9
+#define V_CL9_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_RDQUEUE_ERROR_EN)
+#define F_CL9_COR_RDQUEUE_ERROR_EN    V_CL9_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL8_COR_RDQUEUE_ERROR_EN    8
+#define V_CL8_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_RDQUEUE_ERROR_EN)
+#define F_CL8_COR_RDQUEUE_ERROR_EN    V_CL8_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL7_COR_RDQUEUE_ERROR_EN    7
+#define V_CL7_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_RDQUEUE_ERROR_EN)
+#define F_CL7_COR_RDQUEUE_ERROR_EN    V_CL7_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL6_COR_RDQUEUE_ERROR_EN    6
+#define V_CL6_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_RDQUEUE_ERROR_EN)
+#define F_CL6_COR_RDQUEUE_ERROR_EN    V_CL6_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL5_COR_RDQUEUE_ERROR_EN    5
+#define V_CL5_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_RDQUEUE_ERROR_EN)
+#define F_CL5_COR_RDQUEUE_ERROR_EN    V_CL5_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL4_COR_RDQUEUE_ERROR_EN    4
+#define V_CL4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_RDQUEUE_ERROR_EN)
+#define F_CL4_COR_RDQUEUE_ERROR_EN    V_CL4_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL3_COR_RDQUEUE_ERROR_EN    3
+#define V_CL3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_RDQUEUE_ERROR_EN)
+#define F_CL3_COR_RDQUEUE_ERROR_EN    V_CL3_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL2_COR_RDQUEUE_ERROR_EN    2
+#define V_CL2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_RDQUEUE_ERROR_EN)
+#define F_CL2_COR_RDQUEUE_ERROR_EN    V_CL2_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL1_COR_RDQUEUE_ERROR_EN    1
+#define V_CL1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_RDQUEUE_ERROR_EN)
+#define F_CL1_COR_RDQUEUE_ERROR_EN    V_CL1_COR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL0_COR_RDQUEUE_ERROR_EN    0
+#define V_CL0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_RDQUEUE_ERROR_EN)
+#define F_CL0_COR_RDQUEUE_ERROR_EN    V_CL0_COR_RDQUEUE_ERROR_EN(1U)
+
+#define A_MA_COR_ERROR_STATUS3 0x77bc
+
+#define S_CL14_COR_RDQUEUE_ERROR    14
+#define V_CL14_COR_RDQUEUE_ERROR(x) ((x) << S_CL14_COR_RDQUEUE_ERROR)
+#define F_CL14_COR_RDQUEUE_ERROR    V_CL14_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL13_COR_RDQUEUE_ERROR    13
+#define V_CL13_COR_RDQUEUE_ERROR(x) ((x) << S_CL13_COR_RDQUEUE_ERROR)
+#define F_CL13_COR_RDQUEUE_ERROR    V_CL13_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL12_COR_RDQUEUE_ERROR    12
+#define V_CL12_COR_RDQUEUE_ERROR(x) ((x) << S_CL12_COR_RDQUEUE_ERROR)
+#define F_CL12_COR_RDQUEUE_ERROR    V_CL12_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL11_COR_RDQUEUE_ERROR    11
+#define V_CL11_COR_RDQUEUE_ERROR(x) ((x) << S_CL11_COR_RDQUEUE_ERROR)
+#define F_CL11_COR_RDQUEUE_ERROR    V_CL11_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL10_COR_RDQUEUE_ERROR    10
+#define V_CL10_COR_RDQUEUE_ERROR(x) ((x) << S_CL10_COR_RDQUEUE_ERROR)
+#define F_CL10_COR_RDQUEUE_ERROR    V_CL10_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL9_COR_RDQUEUE_ERROR    9
+#define V_CL9_COR_RDQUEUE_ERROR(x) ((x) << S_CL9_COR_RDQUEUE_ERROR)
+#define F_CL9_COR_RDQUEUE_ERROR    V_CL9_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL8_COR_RDQUEUE_ERROR    8
+#define V_CL8_COR_RDQUEUE_ERROR(x) ((x) << S_CL8_COR_RDQUEUE_ERROR)
+#define F_CL8_COR_RDQUEUE_ERROR    V_CL8_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL7_COR_RDQUEUE_ERROR    7
+#define V_CL7_COR_RDQUEUE_ERROR(x) ((x) << S_CL7_COR_RDQUEUE_ERROR)
+#define F_CL7_COR_RDQUEUE_ERROR    V_CL7_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL6_COR_RDQUEUE_ERROR    6
+#define V_CL6_COR_RDQUEUE_ERROR(x) ((x) << S_CL6_COR_RDQUEUE_ERROR)
+#define F_CL6_COR_RDQUEUE_ERROR    V_CL6_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL5_COR_RDQUEUE_ERROR    5
+#define V_CL5_COR_RDQUEUE_ERROR(x) ((x) << S_CL5_COR_RDQUEUE_ERROR)
+#define F_CL5_COR_RDQUEUE_ERROR    V_CL5_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL4_COR_RDQUEUE_ERROR    4
+#define V_CL4_COR_RDQUEUE_ERROR(x) ((x) << S_CL4_COR_RDQUEUE_ERROR)
+#define F_CL4_COR_RDQUEUE_ERROR    V_CL4_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL3_COR_RDQUEUE_ERROR    3
+#define V_CL3_COR_RDQUEUE_ERROR(x) ((x) << S_CL3_COR_RDQUEUE_ERROR)
+#define F_CL3_COR_RDQUEUE_ERROR    V_CL3_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL2_COR_RDQUEUE_ERROR    2
+#define V_CL2_COR_RDQUEUE_ERROR(x) ((x) << S_CL2_COR_RDQUEUE_ERROR)
+#define F_CL2_COR_RDQUEUE_ERROR    V_CL2_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL1_COR_RDQUEUE_ERROR    1
+#define V_CL1_COR_RDQUEUE_ERROR(x) ((x) << S_CL1_COR_RDQUEUE_ERROR)
+#define F_CL1_COR_RDQUEUE_ERROR    V_CL1_COR_RDQUEUE_ERROR(1U)
+
+#define S_CL0_COR_RDQUEUE_ERROR    0
+#define V_CL0_COR_RDQUEUE_ERROR(x) ((x) << S_CL0_COR_RDQUEUE_ERROR)
+#define F_CL0_COR_RDQUEUE_ERROR    V_CL0_COR_RDQUEUE_ERROR(1U)
+
 #define A_MA_EDRAM0_BAR 0x77c0
 
 #define S_EDRAM0_BASE    16
@@ -16119,6 +20575,16 @@
 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
 
+#define S_T7_EDRAM0_BASE    16
+#define M_T7_EDRAM0_BASE    0xffffU
+#define V_T7_EDRAM0_BASE(x) ((x) << S_T7_EDRAM0_BASE)
+#define G_T7_EDRAM0_BASE(x) (((x) >> S_T7_EDRAM0_BASE) & M_T7_EDRAM0_BASE)
+
+#define S_T7_EDRAM0_SIZE    0
+#define M_T7_EDRAM0_SIZE    0xffffU
+#define V_T7_EDRAM0_SIZE(x) ((x) << S_T7_EDRAM0_SIZE)
+#define G_T7_EDRAM0_SIZE(x) (((x) >> S_T7_EDRAM0_SIZE) & M_T7_EDRAM0_SIZE)
+
 #define A_MA_EDRAM1_BAR 0x77c4
 
 #define S_EDRAM1_BASE    16
@@ -16131,6 +20597,16 @@
 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
 
+#define S_T7_EDRAM1_BASE    16
+#define M_T7_EDRAM1_BASE    0xffffU
+#define V_T7_EDRAM1_BASE(x) ((x) << S_T7_EDRAM1_BASE)
+#define G_T7_EDRAM1_BASE(x) (((x) >> S_T7_EDRAM1_BASE) & M_T7_EDRAM1_BASE)
+
+#define S_T7_EDRAM1_SIZE    0
+#define M_T7_EDRAM1_SIZE    0xffffU
+#define V_T7_EDRAM1_SIZE(x) ((x) << S_T7_EDRAM1_SIZE)
+#define G_T7_EDRAM1_SIZE(x) (((x) >> S_T7_EDRAM1_SIZE) & M_T7_EDRAM1_SIZE)
+
 #define A_MA_EXT_MEMORY_BAR 0x77c8
 
 #define S_EXT_MEM_BASE    16
@@ -16155,6 +20631,16 @@
 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
 
+#define S_T7_EXT_MEM0_BASE    16
+#define M_T7_EXT_MEM0_BASE    0xffffU
+#define V_T7_EXT_MEM0_BASE(x) ((x) << S_T7_EXT_MEM0_BASE)
+#define G_T7_EXT_MEM0_BASE(x) (((x) >> S_T7_EXT_MEM0_BASE) & M_T7_EXT_MEM0_BASE)
+
+#define S_T7_EXT_MEM0_SIZE    0
+#define M_T7_EXT_MEM0_SIZE    0xffffU
+#define V_T7_EXT_MEM0_SIZE(x) ((x) << S_T7_EXT_MEM0_SIZE)
+#define G_T7_EXT_MEM0_SIZE(x) (((x) >> S_T7_EXT_MEM0_SIZE) & M_T7_EXT_MEM0_SIZE)
+
 #define A_MA_HOST_MEMORY_BAR 0x77cc
 
 #define S_HMA_BASE    16
@@ -16167,6 +20653,16 @@
 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
 
+#define S_HMATARGETBASE    16
+#define M_HMATARGETBASE    0xffffU
+#define V_HMATARGETBASE(x) ((x) << S_HMATARGETBASE)
+#define G_HMATARGETBASE(x) (((x) >> S_HMATARGETBASE) & M_HMATARGETBASE)
+
+#define S_T7_HMA_SIZE    0
+#define M_T7_HMA_SIZE    0xffffU
+#define V_T7_HMA_SIZE(x) ((x) << S_T7_HMA_SIZE)
+#define G_T7_HMA_SIZE(x) (((x) >> S_T7_HMA_SIZE) & M_T7_HMA_SIZE)
+
 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
 
 #define S_BRC_MODE    2
@@ -16290,6 +20786,14 @@
 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
 #define F_MC_SPLIT    V_MC_SPLIT(1U)
 
+#define S_EDC512    8
+#define V_EDC512(x) ((x) << S_EDC512)
+#define F_EDC512    V_EDC512(1U)
+
+#define S_MC_SPLIT_BOUNDARY    7
+#define V_MC_SPLIT_BOUNDARY(x) ((x) << S_MC_SPLIT_BOUNDARY)
+#define F_MC_SPLIT_BOUNDARY    V_MC_SPLIT_BOUNDARY(1U)
+
 #define A_MA_INT_ENABLE 0x77dc
 
 #define S_MEM_PERR_INT_ENABLE    1
@@ -16475,6 +20979,55 @@
 #define F_CL0_PAR_RDQUEUE_ERROR_EN    V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
 
 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
+
+#define S_T7_ARB4_PAR_WRQUEUE_ERROR_EN    11
+#define V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_ARB4_PAR_WRQUEUE_ERROR_EN    V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB3_PAR_WRQUEUE_ERROR_EN    10
+#define V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_ARB3_PAR_WRQUEUE_ERROR_EN    V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB2_PAR_WRQUEUE_ERROR_EN    9
+#define V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_ARB2_PAR_WRQUEUE_ERROR_EN    V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB1_PAR_WRQUEUE_ERROR_EN    8
+#define V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_ARB1_PAR_WRQUEUE_ERROR_EN    V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB0_PAR_WRQUEUE_ERROR_EN    7
+#define V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_ARB0_PAR_WRQUEUE_ERROR_EN    V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB4_PAR_RDQUEUE_ERROR_EN    6
+#define V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR_EN)
+#define F_T7_ARB4_PAR_RDQUEUE_ERROR_EN    V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB3_PAR_RDQUEUE_ERROR_EN    5
+#define V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR_EN)
+#define F_T7_ARB3_PAR_RDQUEUE_ERROR_EN    V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB2_PAR_RDQUEUE_ERROR_EN    4
+#define V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR_EN)
+#define F_T7_ARB2_PAR_RDQUEUE_ERROR_EN    V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB1_PAR_RDQUEUE_ERROR_EN    3
+#define V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR_EN)
+#define F_T7_ARB1_PAR_RDQUEUE_ERROR_EN    V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_T7_ARB0_PAR_RDQUEUE_ERROR_EN    2
+#define V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR_EN)
+#define F_T7_ARB0_PAR_RDQUEUE_ERROR_EN    V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_T7_TP_DMARBT_PAR_ERROR_EN    1
+#define V_T7_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR_EN)
+#define F_T7_TP_DMARBT_PAR_ERROR_EN    V_T7_TP_DMARBT_PAR_ERROR_EN(1U)
+
+#define S_T7_LOGIC_FIFO_PAR_ERROR_EN    0
+#define V_T7_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR_EN)
+#define F_T7_LOGIC_FIFO_PAR_ERROR_EN    V_T7_LOGIC_FIFO_PAR_ERROR_EN(1U)
+
 #define A_MA_PARITY_ERROR_STATUS 0x77f4
 
 #define S_TP_DMARBT_PAR_ERROR    31
@@ -16606,6 +21159,55 @@
 #define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)
 
 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
+
+#define S_T7_ARB4_PAR_WRQUEUE_ERROR    11
+#define V_T7_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR)
+#define F_T7_ARB4_PAR_WRQUEUE_ERROR    V_T7_ARB4_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_ARB3_PAR_WRQUEUE_ERROR    10
+#define V_T7_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR)
+#define F_T7_ARB3_PAR_WRQUEUE_ERROR    V_T7_ARB3_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_ARB2_PAR_WRQUEUE_ERROR    9
+#define V_T7_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR)
+#define F_T7_ARB2_PAR_WRQUEUE_ERROR    V_T7_ARB2_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_ARB1_PAR_WRQUEUE_ERROR    8
+#define V_T7_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR)
+#define F_T7_ARB1_PAR_WRQUEUE_ERROR    V_T7_ARB1_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_ARB0_PAR_WRQUEUE_ERROR    7
+#define V_T7_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR)
+#define F_T7_ARB0_PAR_WRQUEUE_ERROR    V_T7_ARB0_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_ARB4_PAR_RDQUEUE_ERROR    6
+#define V_T7_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR)
+#define F_T7_ARB4_PAR_RDQUEUE_ERROR    V_T7_ARB4_PAR_RDQUEUE_ERROR(1U)
+
+#define S_T7_ARB3_PAR_RDQUEUE_ERROR    5
+#define V_T7_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR)
+#define F_T7_ARB3_PAR_RDQUEUE_ERROR    V_T7_ARB3_PAR_RDQUEUE_ERROR(1U)
+
+#define S_T7_ARB2_PAR_RDQUEUE_ERROR    4
+#define V_T7_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR)
+#define F_T7_ARB2_PAR_RDQUEUE_ERROR    V_T7_ARB2_PAR_RDQUEUE_ERROR(1U)
+
+#define S_T7_ARB1_PAR_RDQUEUE_ERROR    3
+#define V_T7_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR)
+#define F_T7_ARB1_PAR_RDQUEUE_ERROR    V_T7_ARB1_PAR_RDQUEUE_ERROR(1U)
+
+#define S_T7_ARB0_PAR_RDQUEUE_ERROR    2
+#define V_T7_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR)
+#define F_T7_ARB0_PAR_RDQUEUE_ERROR    V_T7_ARB0_PAR_RDQUEUE_ERROR(1U)
+
+#define S_T7_TP_DMARBT_PAR_ERROR    1
+#define V_T7_TP_DMARBT_PAR_ERROR(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR)
+#define F_T7_TP_DMARBT_PAR_ERROR    V_T7_TP_DMARBT_PAR_ERROR(1U)
+
+#define S_T7_LOGIC_FIFO_PAR_ERROR    0
+#define V_T7_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR)
+#define F_T7_LOGIC_FIFO_PAR_ERROR    V_T7_LOGIC_FIFO_PAR_ERROR(1U)
+
 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
 
 #define S_BONUS_REG    6
@@ -16653,6 +21255,66 @@
 #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
 #define F_ARB4_PAR_RDQUEUE_ERROR_EN    V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
 
+#define S_CL14_PAR_WRQUEUE_ERROR_EN    14
+#define V_CL14_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR_EN)
+#define F_CL14_PAR_WRQUEUE_ERROR_EN    V_CL14_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL13_PAR_WRQUEUE_ERROR_EN    13
+#define V_CL13_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR_EN)
+#define F_CL13_PAR_WRQUEUE_ERROR_EN    V_CL13_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL12_PAR_WRQUEUE_ERROR_EN    12
+#define V_CL12_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR_EN)
+#define F_CL12_PAR_WRQUEUE_ERROR_EN    V_CL12_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL11_PAR_WRQUEUE_ERROR_EN    11
+#define V_CL11_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR_EN)
+#define F_CL11_PAR_WRQUEUE_ERROR_EN    V_CL11_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL10_PAR_WRQUEUE_ERROR_EN    10
+#define V_T7_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL10_PAR_WRQUEUE_ERROR_EN    V_T7_CL10_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL9_PAR_WRQUEUE_ERROR_EN    9
+#define V_T7_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL9_PAR_WRQUEUE_ERROR_EN    V_T7_CL9_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL8_PAR_WRQUEUE_ERROR_EN    8
+#define V_T7_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL8_PAR_WRQUEUE_ERROR_EN    V_T7_CL8_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL7_PAR_WRQUEUE_ERROR_EN    7
+#define V_T7_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL7_PAR_WRQUEUE_ERROR_EN    V_T7_CL7_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL6_PAR_WRQUEUE_ERROR_EN    6
+#define V_T7_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL6_PAR_WRQUEUE_ERROR_EN    V_T7_CL6_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL5_PAR_WRQUEUE_ERROR_EN    5
+#define V_T7_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL5_PAR_WRQUEUE_ERROR_EN    V_T7_CL5_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL4_PAR_WRQUEUE_ERROR_EN    4
+#define V_T7_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL4_PAR_WRQUEUE_ERROR_EN    V_T7_CL4_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL3_PAR_WRQUEUE_ERROR_EN    3
+#define V_T7_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL3_PAR_WRQUEUE_ERROR_EN    V_T7_CL3_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL2_PAR_WRQUEUE_ERROR_EN    2
+#define V_T7_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL2_PAR_WRQUEUE_ERROR_EN    V_T7_CL2_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL1_PAR_WRQUEUE_ERROR_EN    1
+#define V_T7_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL1_PAR_WRQUEUE_ERROR_EN    V_T7_CL1_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_T7_CL0_PAR_WRQUEUE_ERROR_EN    0
+#define V_T7_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR_EN)
+#define F_T7_CL0_PAR_WRQUEUE_ERROR_EN    V_T7_CL0_PAR_WRQUEUE_ERROR_EN(1U)
+
 #define A_MA_PARITY_ERROR_STATUS2 0x7804
 
 #define S_ARB4_PAR_WRQUEUE_ERROR    1
@@ -16663,6 +21325,66 @@
 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
 #define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)
 
+#define S_CL14_PAR_WRQUEUE_ERROR    14
+#define V_CL14_PAR_WRQUEUE_ERROR(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR)
+#define F_CL14_PAR_WRQUEUE_ERROR    V_CL14_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL13_PAR_WRQUEUE_ERROR    13
+#define V_CL13_PAR_WRQUEUE_ERROR(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR)
+#define F_CL13_PAR_WRQUEUE_ERROR    V_CL13_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL12_PAR_WRQUEUE_ERROR    12
+#define V_CL12_PAR_WRQUEUE_ERROR(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR)
+#define F_CL12_PAR_WRQUEUE_ERROR    V_CL12_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL11_PAR_WRQUEUE_ERROR    11
+#define V_CL11_PAR_WRQUEUE_ERROR(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR)
+#define F_CL11_PAR_WRQUEUE_ERROR    V_CL11_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL10_PAR_WRQUEUE_ERROR    10
+#define V_T7_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR)
+#define F_T7_CL10_PAR_WRQUEUE_ERROR    V_T7_CL10_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL9_PAR_WRQUEUE_ERROR    9
+#define V_T7_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR)
+#define F_T7_CL9_PAR_WRQUEUE_ERROR    V_T7_CL9_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL8_PAR_WRQUEUE_ERROR    8
+#define V_T7_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR)
+#define F_T7_CL8_PAR_WRQUEUE_ERROR    V_T7_CL8_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL7_PAR_WRQUEUE_ERROR    7
+#define V_T7_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR)
+#define F_T7_CL7_PAR_WRQUEUE_ERROR    V_T7_CL7_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL6_PAR_WRQUEUE_ERROR    6
+#define V_T7_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR)
+#define F_T7_CL6_PAR_WRQUEUE_ERROR    V_T7_CL6_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL5_PAR_WRQUEUE_ERROR    5
+#define V_T7_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR)
+#define F_T7_CL5_PAR_WRQUEUE_ERROR    V_T7_CL5_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL4_PAR_WRQUEUE_ERROR    4
+#define V_T7_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR)
+#define F_T7_CL4_PAR_WRQUEUE_ERROR    V_T7_CL4_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL3_PAR_WRQUEUE_ERROR    3
+#define V_T7_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR)
+#define F_T7_CL3_PAR_WRQUEUE_ERROR    V_T7_CL3_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL2_PAR_WRQUEUE_ERROR    2
+#define V_T7_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR)
+#define F_T7_CL2_PAR_WRQUEUE_ERROR    V_T7_CL2_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL1_PAR_WRQUEUE_ERROR    1
+#define V_T7_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR)
+#define F_T7_CL1_PAR_WRQUEUE_ERROR    V_T7_CL1_PAR_WRQUEUE_ERROR(1U)
+
+#define S_T7_CL0_PAR_WRQUEUE_ERROR    0
+#define V_T7_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR)
+#define F_T7_CL0_PAR_WRQUEUE_ERROR    V_T7_CL0_PAR_WRQUEUE_ERROR(1U)
+
 #define A_MA_EXT_MEMORY1_BAR 0x7808
 
 #define S_EXT_MEM1_BASE    16
@@ -16675,6 +21397,16 @@
 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
 
+#define S_T7_EXT_MEM1_BASE    16
+#define M_T7_EXT_MEM1_BASE    0xffffU
+#define V_T7_EXT_MEM1_BASE(x) ((x) << S_T7_EXT_MEM1_BASE)
+#define G_T7_EXT_MEM1_BASE(x) (((x) >> S_T7_EXT_MEM1_BASE) & M_T7_EXT_MEM1_BASE)
+
+#define S_T7_EXT_MEM1_SIZE    0
+#define M_T7_EXT_MEM1_SIZE    0xffffU
+#define V_T7_EXT_MEM1_SIZE(x) ((x) << S_T7_EXT_MEM1_SIZE)
+#define G_T7_EXT_MEM1_SIZE(x) (((x) >> S_T7_EXT_MEM1_SIZE) & M_T7_EXT_MEM1_SIZE)
+
 #define A_MA_PMTX_THROTTLE 0x780c
 
 #define S_FL_ENABLE    31
@@ -16696,6 +21428,7 @@
 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
 #define A_MA_LE_WRDATA_CNT 0x7830
 #define A_MA_CIM_WRDATA_CNT 0x7834
+#define A_MA_CIM_TH0_WRDATA_CNT 0x7834
 #define A_MA_PCIE_WRDATA_CNT 0x7838
 #define A_MA_PMTX_WRDATA_CNT 0x783c
 #define A_MA_PMRX_WRDATA_CNT 0x7840
@@ -16709,6 +21442,7 @@
 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
 #define A_MA_LE_RDDATA_CNT 0x7864
 #define A_MA_CIM_RDDATA_CNT 0x7868
+#define A_MA_CIM_TH0_RDDATA_CNT 0x7868
 #define A_MA_PCIE_RDDATA_CNT 0x786c
 #define A_MA_PMTX_RDDATA_CNT 0x7870
 #define A_MA_PMRX_RDDATA_CNT 0x7874
@@ -16733,7 +21467,43 @@
 #define F_DDR_MODE    V_DDR_MODE(1U)
 
 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
+#define A_MA_PARITY_ERROR_ENABLE3 0x7884
+
+#define S_CL14_PAR_RDQUEUE_ERROR_EN    14
+#define V_CL14_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR_EN)
+#define F_CL14_PAR_RDQUEUE_ERROR_EN    V_CL14_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL13_PAR_RDQUEUE_ERROR_EN    13
+#define V_CL13_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR_EN)
+#define F_CL13_PAR_RDQUEUE_ERROR_EN    V_CL13_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL12_PAR_RDQUEUE_ERROR_EN    12
+#define V_CL12_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR_EN)
+#define F_CL12_PAR_RDQUEUE_ERROR_EN    V_CL12_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL11_PAR_RDQUEUE_ERROR_EN    11
+#define V_CL11_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR_EN)
+#define F_CL11_PAR_RDQUEUE_ERROR_EN    V_CL11_PAR_RDQUEUE_ERROR_EN(1U)
+
 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
+#define A_MA_PARITY_ERROR_STATUS3 0x7888
+
+#define S_CL14_PAR_RDQUEUE_ERROR    14
+#define V_CL14_PAR_RDQUEUE_ERROR(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR)
+#define F_CL14_PAR_RDQUEUE_ERROR    V_CL14_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL13_PAR_RDQUEUE_ERROR    13
+#define V_CL13_PAR_RDQUEUE_ERROR(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR)
+#define F_CL13_PAR_RDQUEUE_ERROR    V_CL13_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL12_PAR_RDQUEUE_ERROR    12
+#define V_CL12_PAR_RDQUEUE_ERROR(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR)
+#define F_CL12_PAR_RDQUEUE_ERROR    V_CL12_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL11_PAR_RDQUEUE_ERROR    11
+#define V_CL11_PAR_RDQUEUE_ERROR(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR)
+#define F_CL11_PAR_RDQUEUE_ERROR    V_CL11_PAR_RDQUEUE_ERROR(1U)
+
 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
@@ -16915,6 +21685,30 @@
 #define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE)
 #define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE)
 
+#define S_T7_FUTURE_CEXPANSION_WTE    31
+#define V_T7_FUTURE_CEXPANSION_WTE(x) ((x) << S_T7_FUTURE_CEXPANSION_WTE)
+#define F_T7_FUTURE_CEXPANSION_WTE    V_T7_FUTURE_CEXPANSION_WTE(1U)
+
+#define S_CL14_WR_CMD_TO_EN    30
+#define V_CL14_WR_CMD_TO_EN(x) ((x) << S_CL14_WR_CMD_TO_EN)
+#define F_CL14_WR_CMD_TO_EN    V_CL14_WR_CMD_TO_EN(1U)
+
+#define S_CL13_WR_CMD_TO_EN    29
+#define V_CL13_WR_CMD_TO_EN(x) ((x) << S_CL13_WR_CMD_TO_EN)
+#define F_CL13_WR_CMD_TO_EN    V_CL13_WR_CMD_TO_EN(1U)
+
+#define S_T7_FUTURE_DEXPANSION_WTE    15
+#define V_T7_FUTURE_DEXPANSION_WTE(x) ((x) << S_T7_FUTURE_DEXPANSION_WTE)
+#define F_T7_FUTURE_DEXPANSION_WTE    V_T7_FUTURE_DEXPANSION_WTE(1U)
+
+#define S_CL14_WR_DATA_TO_EN    14
+#define V_CL14_WR_DATA_TO_EN(x) ((x) << S_CL14_WR_DATA_TO_EN)
+#define F_CL14_WR_DATA_TO_EN    V_CL14_WR_DATA_TO_EN(1U)
+
+#define S_CL13_WR_DATA_TO_EN    13
+#define V_CL13_WR_DATA_TO_EN(x) ((x) << S_CL13_WR_DATA_TO_EN)
+#define F_CL13_WR_DATA_TO_EN    V_CL13_WR_DATA_TO_EN(1U)
+
 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
 
 #define S_CL12_WR_CMD_TO_ERROR    28
@@ -17031,6 +21825,30 @@
 #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
 #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
 
+#define S_T7_FUTURE_CEXPANSION_WTS    31
+#define V_T7_FUTURE_CEXPANSION_WTS(x) ((x) << S_T7_FUTURE_CEXPANSION_WTS)
+#define F_T7_FUTURE_CEXPANSION_WTS    V_T7_FUTURE_CEXPANSION_WTS(1U)
+
+#define S_CL14_WR_CMD_TO_ERROR    30
+#define V_CL14_WR_CMD_TO_ERROR(x) ((x) << S_CL14_WR_CMD_TO_ERROR)
+#define F_CL14_WR_CMD_TO_ERROR    V_CL14_WR_CMD_TO_ERROR(1U)
+
+#define S_CL13_WR_CMD_TO_ERROR    29
+#define V_CL13_WR_CMD_TO_ERROR(x) ((x) << S_CL13_WR_CMD_TO_ERROR)
+#define F_CL13_WR_CMD_TO_ERROR    V_CL13_WR_CMD_TO_ERROR(1U)
+
+#define S_T7_FUTURE_DEXPANSION_WTS    15
+#define V_T7_FUTURE_DEXPANSION_WTS(x) ((x) << S_T7_FUTURE_DEXPANSION_WTS)
+#define F_T7_FUTURE_DEXPANSION_WTS    V_T7_FUTURE_DEXPANSION_WTS(1U)
+
+#define S_CL14_WR_DATA_TO_ERROR    14
+#define V_CL14_WR_DATA_TO_ERROR(x) ((x) << S_CL14_WR_DATA_TO_ERROR)
+#define F_CL14_WR_DATA_TO_ERROR    V_CL14_WR_DATA_TO_ERROR(1U)
+
+#define S_CL13_WR_DATA_TO_ERROR    13
+#define V_CL13_WR_DATA_TO_ERROR(x) ((x) << S_CL13_WR_DATA_TO_ERROR)
+#define F_CL13_WR_DATA_TO_ERROR    V_CL13_WR_DATA_TO_ERROR(1U)
+
 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
 
 #define S_CL12_RD_CMD_TO_EN    28
@@ -17147,6 +21965,30 @@
 #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
 #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
 
+#define S_T7_FUTURE_CEXPANSION_RTE    31
+#define V_T7_FUTURE_CEXPANSION_RTE(x) ((x) << S_T7_FUTURE_CEXPANSION_RTE)
+#define F_T7_FUTURE_CEXPANSION_RTE    V_T7_FUTURE_CEXPANSION_RTE(1U)
+
+#define S_CL14_RD_CMD_TO_EN    30
+#define V_CL14_RD_CMD_TO_EN(x) ((x) << S_CL14_RD_CMD_TO_EN)
+#define F_CL14_RD_CMD_TO_EN    V_CL14_RD_CMD_TO_EN(1U)
+
+#define S_CL13_RD_CMD_TO_EN    29
+#define V_CL13_RD_CMD_TO_EN(x) ((x) << S_CL13_RD_CMD_TO_EN)
+#define F_CL13_RD_CMD_TO_EN    V_CL13_RD_CMD_TO_EN(1U)
+
+#define S_T7_FUTURE_DEXPANSION_RTE    15
+#define V_T7_FUTURE_DEXPANSION_RTE(x) ((x) << S_T7_FUTURE_DEXPANSION_RTE)
+#define F_T7_FUTURE_DEXPANSION_RTE    V_T7_FUTURE_DEXPANSION_RTE(1U)
+
+#define S_CL14_RD_DATA_TO_EN    14
+#define V_CL14_RD_DATA_TO_EN(x) ((x) << S_CL14_RD_DATA_TO_EN)
+#define F_CL14_RD_DATA_TO_EN    V_CL14_RD_DATA_TO_EN(1U)
+
+#define S_CL13_RD_DATA_TO_EN    13
+#define V_CL13_RD_DATA_TO_EN(x) ((x) << S_CL13_RD_DATA_TO_EN)
+#define F_CL13_RD_DATA_TO_EN    V_CL13_RD_DATA_TO_EN(1U)
+
 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
 
 #define S_CL12_RD_CMD_TO_ERROR    28
@@ -17263,6 +22105,27 @@
 #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
 #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
 
+#define S_T7_FUTURE_CEXPANSION_RTS    31
+#define V_T7_FUTURE_CEXPANSION_RTS(x) ((x) << S_T7_FUTURE_CEXPANSION_RTS)
+#define F_T7_FUTURE_CEXPANSION_RTS    V_T7_FUTURE_CEXPANSION_RTS(1U)
+
+#define S_CL14_RD_CMD_TO_ERROR    30
+#define V_CL14_RD_CMD_TO_ERROR(x) ((x) << S_CL14_RD_CMD_TO_ERROR)
+#define F_CL14_RD_CMD_TO_ERROR    V_CL14_RD_CMD_TO_ERROR(1U)
+
+#define S_CL13_RD_CMD_TO_ERROR    29
+#define V_CL13_RD_CMD_TO_ERROR(x) ((x) << S_CL13_RD_CMD_TO_ERROR)
+#define F_CL13_RD_CMD_TO_ERROR    V_CL13_RD_CMD_TO_ERROR(1U)
+
+#define S_T7_FUTURE_DEXPANSION_RTS    14
+#define M_T7_FUTURE_DEXPANSION_RTS    0x3U
+#define V_T7_FUTURE_DEXPANSION_RTS(x) ((x) << S_T7_FUTURE_DEXPANSION_RTS)
+#define G_T7_FUTURE_DEXPANSION_RTS(x) (((x) >> S_T7_FUTURE_DEXPANSION_RTS) & M_T7_FUTURE_DEXPANSION_RTS)
+
+#define S_CL13_RD_DATA_TO_ERROR    13
+#define V_CL13_RD_DATA_TO_ERROR(x) ((x) << S_CL13_RD_DATA_TO_ERROR)
+#define F_CL13_RD_DATA_TO_ERROR    V_CL13_RD_DATA_TO_ERROR(1U)
+
 #define A_MA_BKP_CNT_SEL 0x78e4
 
 #define S_BKP_CNT_TYPE    30
@@ -17361,12 +22224,16 @@
 #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
 #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
 
-#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
+#define S_T7_FUTURE_DEXPANSION_IPE    14
+#define M_T7_FUTURE_DEXPANSION_IPE    0x3ffffU
+#define V_T7_FUTURE_DEXPANSION_IPE(x) ((x) << S_T7_FUTURE_DEXPANSION_IPE)
+#define G_T7_FUTURE_DEXPANSION_IPE(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPE) & M_T7_FUTURE_DEXPANSION_IPE)
 
-#define S_T5_FUTURE_DEXPANSION    13
-#define M_T5_FUTURE_DEXPANSION    0x7ffffU
-#define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
-#define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
+#define S_CL13_IF_PAR_EN    13
+#define V_CL13_IF_PAR_EN(x) ((x) << S_CL13_IF_PAR_EN)
+#define F_CL13_IF_PAR_EN    V_CL13_IF_PAR_EN(1U)
+
+#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
 
 #define S_CL12_IF_PAR_ERROR    12
 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
@@ -17425,6 +22292,15 @@
 #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
 #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
 
+#define S_T7_FUTURE_DEXPANSION_IPS    14
+#define M_T7_FUTURE_DEXPANSION_IPS    0x3ffffU
+#define V_T7_FUTURE_DEXPANSION_IPS(x) ((x) << S_T7_FUTURE_DEXPANSION_IPS)
+#define G_T7_FUTURE_DEXPANSION_IPS(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPS) & M_T7_FUTURE_DEXPANSION_IPS)
+
+#define S_CL13_IF_PAR_ERROR    13
+#define V_CL13_IF_PAR_ERROR(x) ((x) << S_CL13_IF_PAR_ERROR)
+#define F_CL13_IF_PAR_ERROR    V_CL13_IF_PAR_ERROR(1U)
+
 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
 
 #define S_DEBUG_OR    15
@@ -17445,6 +22321,131 @@
 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
 
 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
+#define A_MA_CLIENT13_PR_THRESHOLD 0x7900
+#define A_MA_CLIENT13_CR_THRESHOLD 0x7904
+#define A_MA_CRYPTO_DEBUG_CNT 0x7908
+#define A_MA_CRYPTO_WRDATA_CNT 0x790c
+#define A_MA_CRYPTO_RDDATA_CNT 0x7910
+#define A_MA_LOCAL_DEBUG_PERF_CFG 0x7914
+#define A_MA_LOCAL_DEBUG_PERF_RPT 0x7918
+#define A_MA_PCIE_THROTTLE 0x791c
+#define A_MA_CLIENT14_PR_THRESHOLD 0x7920
+#define A_MA_CLIENT14_CR_THRESHOLD 0x7924
+#define A_MA_CIM_TH1_DEBUG_CNT 0x7928
+#define A_MA_CIM_TH1_WRDATA_CNT 0x792c
+#define A_MA_CIM_TH1_RDDATA_CNT 0x7930
+#define A_MA_CIM_THREAD1_MAPPER 0x7934
+
+#define S_CIM_THREAD1_EN    0
+#define M_CIM_THREAD1_EN    0xffU
+#define V_CIM_THREAD1_EN(x) ((x) << S_CIM_THREAD1_EN)
+#define G_CIM_THREAD1_EN(x) (((x) >> S_CIM_THREAD1_EN) & M_CIM_THREAD1_EN)
+
+#define A_MA_PIO_CI_SGE_TH0_BASE 0x7938
+
+#define S_SGE_TH0_BASE    0
+#define M_SGE_TH0_BASE    0xffffU
+#define V_SGE_TH0_BASE(x) ((x) << S_SGE_TH0_BASE)
+#define G_SGE_TH0_BASE(x) (((x) >> S_SGE_TH0_BASE) & M_SGE_TH0_BASE)
+
+#define A_MA_PIO_CI_SGE_TH1_BASE 0x793c
+
+#define S_SGE_TH1_BASE    0
+#define M_SGE_TH1_BASE    0xffffU
+#define V_SGE_TH1_BASE(x) ((x) << S_SGE_TH1_BASE)
+#define G_SGE_TH1_BASE(x) (((x) >> S_SGE_TH1_BASE) & M_SGE_TH1_BASE)
+
+#define A_MA_PIO_CI_ULPTX_BASE 0x7940
+
+#define S_ULPTX_BASE    0
+#define M_ULPTX_BASE    0xffffU
+#define V_ULPTX_BASE(x) ((x) << S_ULPTX_BASE)
+#define G_ULPTX_BASE(x) (((x) >> S_ULPTX_BASE) & M_ULPTX_BASE)
+
+#define A_MA_PIO_CI_ULPRX_BASE 0x7944
+
+#define S_ULPRX_BASE    0
+#define M_ULPRX_BASE    0xffffU
+#define V_ULPRX_BASE(x) ((x) << S_ULPRX_BASE)
+#define G_ULPRX_BASE(x) (((x) >> S_ULPRX_BASE) & M_ULPRX_BASE)
+
+#define A_MA_PIO_CI_ULPTXRX_BASE 0x7948
+
+#define S_ULPTXRX_BASE    0
+#define M_ULPTXRX_BASE    0xffffU
+#define V_ULPTXRX_BASE(x) ((x) << S_ULPTXRX_BASE)
+#define G_ULPTXRX_BASE(x) (((x) >> S_ULPTXRX_BASE) & M_ULPTXRX_BASE)
+
+#define A_MA_PIO_CI_TP_TH0_BASE 0x794c
+
+#define S_TP_TH0_BASE    0
+#define M_TP_TH0_BASE    0xffffU
+#define V_TP_TH0_BASE(x) ((x) << S_TP_TH0_BASE)
+#define G_TP_TH0_BASE(x) (((x) >> S_TP_TH0_BASE) & M_TP_TH0_BASE)
+
+#define A_MA_PIO_CI_TP_TH1_BASE 0x7950
+
+#define S_TP_TH1_BASE    0
+#define M_TP_TH1_BASE    0xffffU
+#define V_TP_TH1_BASE(x) ((x) << S_TP_TH1_BASE)
+#define G_TP_TH1_BASE(x) (((x) >> S_TP_TH1_BASE) & M_TP_TH1_BASE)
+
+#define A_MA_PIO_CI_LE_BASE 0x7954
+
+#define S_LE_BASE    0
+#define M_LE_BASE    0xffffU
+#define V_LE_BASE(x) ((x) << S_LE_BASE)
+#define G_LE_BASE(x) (((x) >> S_LE_BASE) & M_LE_BASE)
+
+#define A_MA_PIO_CI_CIM_TH0_BASE 0x7958
+
+#define S_CIM_TH0_BASE    0
+#define M_CIM_TH0_BASE    0xffffU
+#define V_CIM_TH0_BASE(x) ((x) << S_CIM_TH0_BASE)
+#define G_CIM_TH0_BASE(x) (((x) >> S_CIM_TH0_BASE) & M_CIM_TH0_BASE)
+
+#define A_MA_PIO_CI_PCIE_BASE 0x795c
+
+#define S_PCIE_BASE    0
+#define M_PCIE_BASE    0xffffU
+#define V_PCIE_BASE(x) ((x) << S_PCIE_BASE)
+#define G_PCIE_BASE(x) (((x) >> S_PCIE_BASE) & M_PCIE_BASE)
+
+#define A_MA_PIO_CI_PMTX_BASE 0x7960
+
+#define S_PMTX_BASE    0
+#define M_PMTX_BASE    0xffffU
+#define V_PMTX_BASE(x) ((x) << S_PMTX_BASE)
+#define G_PMTX_BASE(x) (((x) >> S_PMTX_BASE) & M_PMTX_BASE)
+
+#define A_MA_PIO_CI_PMRX_BASE 0x7964
+
+#define S_PMRX_BASE    0
+#define M_PMRX_BASE    0xffffU
+#define V_PMRX_BASE(x) ((x) << S_PMRX_BASE)
+#define G_PMRX_BASE(x) (((x) >> S_PMRX_BASE) & M_PMRX_BASE)
+
+#define A_MA_PIO_CI_HMA_BASE 0x7968
+
+#define S_HMACLIENTBASE    0
+#define M_HMACLIENTBASE    0xffffU
+#define V_HMACLIENTBASE(x) ((x) << S_HMACLIENTBASE)
+#define G_HMACLIENTBASE(x) (((x) >> S_HMACLIENTBASE) & M_HMACLIENTBASE)
+
+#define A_MA_PIO_CI_CRYPTO_BASE 0x796c
+
+#define S_CRYPTO_BASE    0
+#define M_CRYPTO_BASE    0xffffU
+#define V_CRYPTO_BASE(x) ((x) << S_CRYPTO_BASE)
+#define G_CRYPTO_BASE(x) (((x) >> S_CRYPTO_BASE) & M_CRYPTO_BASE)
+
+#define A_MA_PIO_CI_CIM_TH1_BASE 0x7970
+
+#define S_CIM_TH1_BASE    0
+#define M_CIM_TH1_BASE    0xffffU
+#define V_CIM_TH1_BASE(x) ((x) << S_CIM_TH1_BASE)
+#define G_CIM_TH1_BASE(x) (((x) >> S_CIM_TH1_BASE) & M_CIM_TH1_BASE)
+
 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
 
 #define S_CMDVLD0    31
@@ -20418,6 +25419,124 @@
 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
 
+#define A_T7_CIM_PERR_ENABLE 0x7b08
+
+#define S_T7_MA_CIM_INTFPERR    31
+#define V_T7_MA_CIM_INTFPERR(x) ((x) << S_T7_MA_CIM_INTFPERR)
+#define F_T7_MA_CIM_INTFPERR    V_T7_MA_CIM_INTFPERR(1U)
+
+#define S_T7_MBHOSTPARERR    30
+#define V_T7_MBHOSTPARERR(x) ((x) << S_T7_MBHOSTPARERR)
+#define F_T7_MBHOSTPARERR    V_T7_MBHOSTPARERR(1U)
+
+#define S_MAARBINVRSPTAG    29
+#define V_MAARBINVRSPTAG(x) ((x) << S_MAARBINVRSPTAG)
+#define F_MAARBINVRSPTAG    V_MAARBINVRSPTAG(1U)
+
+#define S_MAARBFIFOPARERR    28
+#define V_MAARBFIFOPARERR(x) ((x) << S_MAARBFIFOPARERR)
+#define F_MAARBFIFOPARERR    V_MAARBFIFOPARERR(1U)
+
+#define S_SEMSRAMPARERR    27
+#define V_SEMSRAMPARERR(x) ((x) << S_SEMSRAMPARERR)
+#define F_SEMSRAMPARERR    V_SEMSRAMPARERR(1U)
+
+#define S_RSACPARERR    26
+#define V_RSACPARERR(x) ((x) << S_RSACPARERR)
+#define F_RSACPARERR    V_RSACPARERR(1U)
+
+#define S_RSADPARERR    25
+#define V_RSADPARERR(x) ((x) << S_RSADPARERR)
+#define F_RSADPARERR    V_RSADPARERR(1U)
+
+#define S_T7_PLCIM_MSTRSPDATAPARERR    24
+#define V_T7_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_T7_PLCIM_MSTRSPDATAPARERR)
+#define F_T7_PLCIM_MSTRSPDATAPARERR    V_T7_PLCIM_MSTRSPDATAPARERR(1U)
+
+#define S_T7_PCIE2CIMINTFPARERR    23
+#define V_T7_PCIE2CIMINTFPARERR(x) ((x) << S_T7_PCIE2CIMINTFPARERR)
+#define F_T7_PCIE2CIMINTFPARERR    V_T7_PCIE2CIMINTFPARERR(1U)
+
+#define S_T7_NCSI2CIMINTFPARERR    22
+#define V_T7_NCSI2CIMINTFPARERR(x) ((x) << S_T7_NCSI2CIMINTFPARERR)
+#define F_T7_NCSI2CIMINTFPARERR    V_T7_NCSI2CIMINTFPARERR(1U)
+
+#define S_T7_SGE2CIMINTFPARERR    21
+#define V_T7_SGE2CIMINTFPARERR(x) ((x) << S_T7_SGE2CIMINTFPARERR)
+#define F_T7_SGE2CIMINTFPARERR    V_T7_SGE2CIMINTFPARERR(1U)
+
+#define S_T7_ULP2CIMINTFPARERR    20
+#define V_T7_ULP2CIMINTFPARERR(x) ((x) << S_T7_ULP2CIMINTFPARERR)
+#define F_T7_ULP2CIMINTFPARERR    V_T7_ULP2CIMINTFPARERR(1U)
+
+#define S_T7_TP2CIMINTFPARERR    19
+#define V_T7_TP2CIMINTFPARERR(x) ((x) << S_T7_TP2CIMINTFPARERR)
+#define F_T7_TP2CIMINTFPARERR    V_T7_TP2CIMINTFPARERR(1U)
+
+#define S_CORE7PARERR    18
+#define V_CORE7PARERR(x) ((x) << S_CORE7PARERR)
+#define F_CORE7PARERR    V_CORE7PARERR(1U)
+
+#define S_CORE6PARERR    17
+#define V_CORE6PARERR(x) ((x) << S_CORE6PARERR)
+#define F_CORE6PARERR    V_CORE6PARERR(1U)
+
+#define S_CORE5PARERR    16
+#define V_CORE5PARERR(x) ((x) << S_CORE5PARERR)
+#define F_CORE5PARERR    V_CORE5PARERR(1U)
+
+#define S_CORE4PARERR    15
+#define V_CORE4PARERR(x) ((x) << S_CORE4PARERR)
+#define F_CORE4PARERR    V_CORE4PARERR(1U)
+
+#define S_CORE3PARERR    14
+#define V_CORE3PARERR(x) ((x) << S_CORE3PARERR)
+#define F_CORE3PARERR    V_CORE3PARERR(1U)
+
+#define S_CORE2PARERR    13
+#define V_CORE2PARERR(x) ((x) << S_CORE2PARERR)
+#define F_CORE2PARERR    V_CORE2PARERR(1U)
+
+#define S_CORE1PARERR    12
+#define V_CORE1PARERR(x) ((x) << S_CORE1PARERR)
+#define F_CORE1PARERR    V_CORE1PARERR(1U)
+
+#define S_GFTPARERR    10
+#define V_GFTPARERR(x) ((x) << S_GFTPARERR)
+#define F_GFTPARERR    V_GFTPARERR(1U)
+
+#define S_MPSRSPDATAPARERR    9
+#define V_MPSRSPDATAPARERR(x) ((x) << S_MPSRSPDATAPARERR)
+#define F_MPSRSPDATAPARERR    V_MPSRSPDATAPARERR(1U)
+
+#define S_ER_RSPDATAPARERR    8
+#define V_ER_RSPDATAPARERR(x) ((x) << S_ER_RSPDATAPARERR)
+#define F_ER_RSPDATAPARERR    V_ER_RSPDATAPARERR(1U)
+
+#define S_FLOWFIFOPARERR    7
+#define V_FLOWFIFOPARERR(x) ((x) << S_FLOWFIFOPARERR)
+#define F_FLOWFIFOPARERR    V_FLOWFIFOPARERR(1U)
+
+#define S_OBQSRAMPARERR    6
+#define V_OBQSRAMPARERR(x) ((x) << S_OBQSRAMPARERR)
+#define F_OBQSRAMPARERR    V_OBQSRAMPARERR(1U)
+
+#define S_TIEQOUTPARERR    3
+#define V_TIEQOUTPARERR(x) ((x) << S_TIEQOUTPARERR)
+#define F_TIEQOUTPARERR    V_TIEQOUTPARERR(1U)
+
+#define S_TIEQINPARERR    2
+#define V_TIEQINPARERR(x) ((x) << S_TIEQINPARERR)
+#define F_TIEQINPARERR    V_TIEQINPARERR(1U)
+
+#define S_PIFRSPPARERR    1
+#define V_PIFRSPPARERR(x) ((x) << S_PIFRSPPARERR)
+#define F_PIFRSPPARERR    V_PIFRSPPARERR(1U)
+
+#define S_PIFREQPARERR    0
+#define V_PIFREQPARERR(x) ((x) << S_PIFREQPARERR)
+#define F_PIFREQPARERR    V_PIFREQPARERR(1U)
+
 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
 
 #define S_EEPROMBASEADDR    6
@@ -20425,6 +25544,7 @@
 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
 
+#define A_CIM_PERR_CAUSE 0x7b0c
 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
 
 #define S_EEPROMADDRSIZE    4
@@ -20593,6 +25713,38 @@
 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
 #define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)
 
+#define S_CORE7ACCINT    22
+#define V_CORE7ACCINT(x) ((x) << S_CORE7ACCINT)
+#define F_CORE7ACCINT    V_CORE7ACCINT(1U)
+
+#define S_CORE6ACCINT    21
+#define V_CORE6ACCINT(x) ((x) << S_CORE6ACCINT)
+#define F_CORE6ACCINT    V_CORE6ACCINT(1U)
+
+#define S_CORE5ACCINT    20
+#define V_CORE5ACCINT(x) ((x) << S_CORE5ACCINT)
+#define F_CORE5ACCINT    V_CORE5ACCINT(1U)
+
+#define S_CORE4ACCINT    19
+#define V_CORE4ACCINT(x) ((x) << S_CORE4ACCINT)
+#define F_CORE4ACCINT    V_CORE4ACCINT(1U)
+
+#define S_CORE3ACCINT    18
+#define V_CORE3ACCINT(x) ((x) << S_CORE3ACCINT)
+#define F_CORE3ACCINT    V_CORE3ACCINT(1U)
+
+#define S_CORE2ACCINT    17
+#define V_CORE2ACCINT(x) ((x) << S_CORE2ACCINT)
+#define F_CORE2ACCINT    V_CORE2ACCINT(1U)
+
+#define S_CORE1ACCINT    16
+#define V_CORE1ACCINT(x) ((x) << S_CORE1ACCINT)
+#define F_CORE1ACCINT    V_CORE1ACCINT(1U)
+
+#define S_PERRNONZERO    1
+#define V_PERRNONZERO(x) ((x) << S_PERRNONZERO)
+#define F_PERRNONZERO    V_PERRNONZERO(1U)
+
 #define A_CIM_HOST_INT_CAUSE 0x7b2c
 
 #define S_TIEQOUTPARERRINT    20
@@ -20745,6 +25897,10 @@
 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
 
+#define S_CONWRERRINTEN    31
+#define V_CONWRERRINTEN(x) ((x) << S_CONWRERRINTEN)
+#define F_CONWRERRINTEN    V_CONWRERRINTEN(1U)
+
 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
 
 #define S_EEPROMWRINT    30
@@ -20871,12 +26027,32 @@
 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
 
+#define S_CONWRERRINT    31
+#define V_CONWRERRINT(x) ((x) << S_CONWRERRINT)
+#define F_CONWRERRINT    V_CONWRERRINT(1U)
+
 #define A_CIM_UP_INT_ENABLE 0x7b38
 
 #define S_MSTPLINTEN    4
 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
 
+#define S_SEMINT    8
+#define V_SEMINT(x) ((x) << S_SEMINT)
+#define F_SEMINT    V_SEMINT(1U)
+
+#define S_RSAINT    7
+#define V_RSAINT(x) ((x) << S_RSAINT)
+#define F_RSAINT    V_RSAINT(1U)
+
+#define S_TRNGINT    6
+#define V_TRNGINT(x) ((x) << S_TRNGINT)
+#define F_TRNGINT    V_TRNGINT(1U)
+
+#define S_PEERHALTINT    5
+#define V_PEERHALTINT(x) ((x) << S_PEERHALTINT)
+#define F_PEERHALTINT    V_PEERHALTINT(1U)
+
 #define A_CIM_UP_INT_CAUSE 0x7b3c
 
 #define S_MSTPLINT    4
@@ -20900,6 +26076,33 @@
 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
 
+#define S_MAPOFFSET    11
+#define M_MAPOFFSET    0x1fU
+#define V_MAPOFFSET(x) ((x) << S_MAPOFFSET)
+#define G_MAPOFFSET(x) (((x) >> S_MAPOFFSET) & M_MAPOFFSET)
+
+#define S_MAPSELECT    10
+#define V_MAPSELECT(x) ((x) << S_MAPSELECT)
+#define F_MAPSELECT    V_MAPSELECT(1U)
+
+#define S_CORESELECT    6
+#define M_CORESELECT    0xfU
+#define V_CORESELECT(x) ((x) << S_CORESELECT)
+#define G_CORESELECT(x) (((x) >> S_CORESELECT) & M_CORESELECT)
+
+#define S_T7_OBQSELECT    5
+#define V_T7_OBQSELECT(x) ((x) << S_T7_OBQSELECT)
+#define F_T7_OBQSELECT    V_T7_OBQSELECT(1U)
+
+#define S_T7_IBQSELECT    4
+#define V_T7_IBQSELECT(x) ((x) << S_T7_IBQSELECT)
+#define F_T7_IBQSELECT    V_T7_IBQSELECT(1U)
+
+#define S_T7_QUENUMSELECT    0
+#define M_T7_QUENUMSELECT    0xfU
+#define V_T7_QUENUMSELECT(x) ((x) << S_T7_QUENUMSELECT)
+#define G_T7_QUENUMSELECT(x) (((x) >> S_T7_QUENUMSELECT) & M_T7_QUENUMSELECT)
+
 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
 
 #define S_CIMQSIZE    24
@@ -20940,6 +26143,29 @@
 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
 
+#define S_T7_HOSTBUSY    31
+#define V_T7_HOSTBUSY(x) ((x) << S_T7_HOSTBUSY)
+#define F_T7_HOSTBUSY    V_T7_HOSTBUSY(1U)
+
+#define S_T7_HOSTWRITE    30
+#define V_T7_HOSTWRITE(x) ((x) << S_T7_HOSTWRITE)
+#define F_T7_HOSTWRITE    V_T7_HOSTWRITE(1U)
+
+#define S_HOSTGRPSEL    28
+#define M_HOSTGRPSEL    0x3U
+#define V_HOSTGRPSEL(x) ((x) << S_HOSTGRPSEL)
+#define G_HOSTGRPSEL(x) (((x) >> S_HOSTGRPSEL) & M_HOSTGRPSEL)
+
+#define S_HOSTCORESEL    24
+#define M_HOSTCORESEL    0xfU
+#define V_HOSTCORESEL(x) ((x) << S_HOSTCORESEL)
+#define G_HOSTCORESEL(x) (((x) >> S_HOSTCORESEL) & M_HOSTCORESEL)
+
+#define S_T7_HOSTADDR    0
+#define M_T7_HOSTADDR    0xffffffU
+#define V_T7_HOSTADDR(x) ((x) << S_T7_HOSTADDR)
+#define G_T7_HOSTADDR(x) (((x) >> S_T7_HOSTADDR) & M_T7_HOSTADDR)
+
 #define A_CIM_HOST_ACC_DATA 0x7b54
 #define A_CIM_CDEBUGDATA 0x7b58
 
@@ -20953,6 +26179,31 @@
 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
 
+#define A_CIM_DEBUG_CFG 0x7b58
+
+#define S_OR_EN    20
+#define V_OR_EN(x) ((x) << S_OR_EN)
+#define F_OR_EN    V_OR_EN(1U)
+
+#define S_USEL    19
+#define V_USEL(x) ((x) << S_USEL)
+#define F_USEL    V_USEL(1U)
+
+#define S_HI    18
+#define V_HI(x) ((x) << S_HI)
+#define F_HI    V_HI(1U)
+
+#define S_SELH    9
+#define M_SELH    0x1ffU
+#define V_SELH(x) ((x) << S_SELH)
+#define G_SELH(x) (((x) >> S_SELH) & M_SELH)
+
+#define S_SELL    0
+#define M_SELL    0x1ffU
+#define V_SELL(x) ((x) << S_SELL)
+#define G_SELL(x) (((x) >> S_SELL) & M_SELL)
+
+#define A_CIM_DEBUG_DATA 0x7b5c
 #define A_CIM_IBQ_DBG_CFG 0x7b60
 
 #define S_IBQDBGADDR    16
@@ -20972,6 +26223,25 @@
 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
 #define F_IBQDBGEN    V_IBQDBGEN(1U)
 
+#define S_IBQDBGCORE    28
+#define M_IBQDBGCORE    0xfU
+#define V_IBQDBGCORE(x) ((x) << S_IBQDBGCORE)
+#define G_IBQDBGCORE(x) (((x) >> S_IBQDBGCORE) & M_IBQDBGCORE)
+
+#define S_T7_IBQDBGADDR    12
+#define M_T7_IBQDBGADDR    0x1fffU
+#define V_T7_IBQDBGADDR(x) ((x) << S_T7_IBQDBGADDR)
+#define G_T7_IBQDBGADDR(x) (((x) >> S_T7_IBQDBGADDR) & M_T7_IBQDBGADDR)
+
+#define S_IBQDBGSTATE    4
+#define M_IBQDBGSTATE    0x3U
+#define V_IBQDBGSTATE(x) ((x) << S_IBQDBGSTATE)
+#define G_IBQDBGSTATE(x) (((x) >> S_IBQDBGSTATE) & M_IBQDBGSTATE)
+
+#define S_PERRADDRCLR    3
+#define V_PERRADDRCLR(x) ((x) << S_PERRADDRCLR)
+#define F_PERRADDRCLR    V_PERRADDRCLR(1U)
+
 #define A_CIM_OBQ_DBG_CFG 0x7b64
 
 #define S_OBQDBGADDR    16
@@ -20991,6 +26261,21 @@
 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
 #define F_OBQDBGEN    V_OBQDBGEN(1U)
 
+#define S_OBQDBGCORE    28
+#define M_OBQDBGCORE    0xfU
+#define V_OBQDBGCORE(x) ((x) << S_OBQDBGCORE)
+#define G_OBQDBGCORE(x) (((x) >> S_OBQDBGCORE) & M_OBQDBGCORE)
+
+#define S_T7_OBQDBGADDR    12
+#define M_T7_OBQDBGADDR    0x1fffU
+#define V_T7_OBQDBGADDR(x) ((x) << S_T7_OBQDBGADDR)
+#define G_T7_OBQDBGADDR(x) (((x) >> S_T7_OBQDBGADDR) & M_T7_OBQDBGADDR)
+
+#define S_OBQDBGSTATE    4
+#define M_OBQDBGSTATE    0x3U
+#define V_OBQDBGSTATE(x) ((x) << S_OBQDBGSTATE)
+#define G_OBQDBGSTATE(x) (((x) >> S_OBQDBGSTATE) & M_OBQDBGSTATE)
+
 #define A_CIM_IBQ_DBG_DATA 0x7b68
 #define A_CIM_OBQ_DBG_DATA 0x7b6c
 #define A_CIM_DEBUGCFG 0x7b70
@@ -21075,6 +26360,11 @@
 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
 
+#define S_THREAD_ID    2
+#define M_THREAD_ID    0x7U
+#define V_THREAD_ID(x) ((x) << S_THREAD_ID)
+#define G_THREAD_ID(x) (((x) >> S_THREAD_ID) & M_THREAD_ID)
+
 #define A_CIM_MEM_ZONE0_LEN 0x7b98
 
 #define S_MEM_ZONE_LEN    4
@@ -21207,6 +26497,7 @@
 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
 
 #define A_CIM_PERR_INJECT 0x7c20
+#define A_CIM_FPGA_ROM_EFUSE_CMD 0x7c20
 #define A_CIM_PERR_ENABLE 0x7c24
 
 #define S_PERREN    0
@@ -21224,6 +26515,7 @@
 #define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN)
 #define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN)
 
+#define A_CIM_FPGA_ROM_EFUSE_DATA 0x7c24
 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
 
 #define S_EEPROMBUSY    0
@@ -21240,6 +26532,22 @@
 #define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE)
 #define F_SLOW_TIMER_ENABLE    V_SLOW_TIMER_ENABLE(1U)
 
+#define S_FLASHWRPAGEMORE    5
+#define V_FLASHWRPAGEMORE(x) ((x) << S_FLASHWRPAGEMORE)
+#define F_FLASHWRPAGEMORE    V_FLASHWRPAGEMORE(1U)
+
+#define S_FLASHWRENABLE    4
+#define V_FLASHWRENABLE(x) ((x) << S_FLASHWRENABLE)
+#define F_FLASHWRENABLE    V_FLASHWRENABLE(1U)
+
+#define S_FLASHMOREENABLE    3
+#define V_FLASHMOREENABLE(x) ((x) << S_FLASHMOREENABLE)
+#define F_FLASHMOREENABLE    V_FLASHMOREENABLE(1U)
+
+#define S_WR_RESP_ENABLE    2
+#define V_WR_RESP_ENABLE(x) ((x) << S_WR_RESP_ENABLE)
+#define F_WR_RESP_ENABLE    V_WR_RESP_ENABLE(1U)
+
 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
 
 #define S_UP_PO_SINGLE_OUTSTANDING    0
@@ -21271,6 +26579,18 @@
 #define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE)
 
 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
+#define A_CIM_QUE_PERR_ADDR 0x7c40
+
+#define S_IBQPERRADDR    16
+#define M_IBQPERRADDR    0xfffU
+#define V_IBQPERRADDR(x) ((x) << S_IBQPERRADDR)
+#define G_IBQPERRADDR(x) (((x) >> S_IBQPERRADDR) & M_IBQPERRADDR)
+
+#define S_OBQPERRADDR    0
+#define M_OBQPERRADDR    0xfffU
+#define V_OBQPERRADDR(x) ((x) << S_OBQPERRADDR)
+#define G_OBQPERRADDR(x) (((x) >> S_OBQPERRADDR) & M_OBQPERRADDR)
+
 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
 
 #define S_PIO_UP_MST_CFG_SEL    0
@@ -21309,6 +26629,20 @@
 #define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE)
 #define F_PCIE_OBQ_IF_DISABLE    V_PCIE_OBQ_IF_DISABLE(1U)
 
+#define S_ULP_OBQ_SIZE    8
+#define M_ULP_OBQ_SIZE    0x3U
+#define V_ULP_OBQ_SIZE(x) ((x) << S_ULP_OBQ_SIZE)
+#define G_ULP_OBQ_SIZE(x) (((x) >> S_ULP_OBQ_SIZE) & M_ULP_OBQ_SIZE)
+
+#define S_TP_IBQ_SIZE    6
+#define M_TP_IBQ_SIZE    0x3U
+#define V_TP_IBQ_SIZE(x) ((x) << S_TP_IBQ_SIZE)
+#define G_TP_IBQ_SIZE(x) (((x) >> S_TP_IBQ_SIZE) & M_TP_IBQ_SIZE)
+
+#define S_OBQ_EOM_ENABLE    5
+#define V_OBQ_EOM_ENABLE(x) ((x) << S_OBQ_EOM_ENABLE)
+#define F_OBQ_EOM_ENABLE    V_OBQ_EOM_ENABLE(1U)
+
 #define A_CIM_CGEN_GLOBAL 0x7c50
 
 #define S_CGEN_GLOBAL    0
@@ -21321,6 +26655,77 @@
 #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
 #define F_PIFDBGLA_DPSLP_EN    V_PIFDBGLA_DPSLP_EN(1U)
 
+#define A_CIM_GFT_CMM_CONFIG 0x7c58
+
+#define S_GLFL    31
+#define V_GLFL(x) ((x) << S_GLFL)
+#define F_GLFL    V_GLFL(1U)
+
+#define S_T7_WRCNTIDLE    16
+#define M_T7_WRCNTIDLE    0x7fffU
+#define V_T7_WRCNTIDLE(x) ((x) << S_T7_WRCNTIDLE)
+#define G_T7_WRCNTIDLE(x) (((x) >> S_T7_WRCNTIDLE) & M_T7_WRCNTIDLE)
+
+#define A_CIM_GFT_CONFIG 0x7c5c
+
+#define S_GFTMABASE    16
+#define M_GFTMABASE    0xffffU
+#define V_GFTMABASE(x) ((x) << S_GFTMABASE)
+#define G_GFTMABASE(x) (((x) >> S_GFTMABASE) & M_GFTMABASE)
+
+#define S_GFTHASHTBLSIZE    12
+#define M_GFTHASHTBLSIZE    0xfU
+#define V_GFTHASHTBLSIZE(x) ((x) << S_GFTHASHTBLSIZE)
+#define G_GFTHASHTBLSIZE(x) (((x) >> S_GFTHASHTBLSIZE) & M_GFTHASHTBLSIZE)
+
+#define S_GFTTCAMPRIORITY    11
+#define V_GFTTCAMPRIORITY(x) ((x) << S_GFTTCAMPRIORITY)
+#define F_GFTTCAMPRIORITY    V_GFTTCAMPRIORITY(1U)
+
+#define S_GFTMATHREADID    8
+#define M_GFTMATHREADID    0x7U
+#define V_GFTMATHREADID(x) ((x) << S_GFTMATHREADID)
+#define G_GFTMATHREADID(x) (((x) >> S_GFTMATHREADID) & M_GFTMATHREADID)
+
+#define S_GFTTCAMINIT    7
+#define V_GFTTCAMINIT(x) ((x) << S_GFTTCAMINIT)
+#define F_GFTTCAMINIT    V_GFTTCAMINIT(1U)
+
+#define S_GFTTCAMINITDONE    6
+#define V_GFTTCAMINITDONE(x) ((x) << S_GFTTCAMINITDONE)
+#define F_GFTTCAMINITDONE    V_GFTTCAMINITDONE(1U)
+
+#define S_GFTTBLMODEEN    0
+#define V_GFTTBLMODEEN(x) ((x) << S_GFTTBLMODEEN)
+#define F_GFTTBLMODEEN    V_GFTTBLMODEEN(1U)
+
+#define A_CIM_TCAM_BIST_CTRL 0x7c60
+
+#define S_RST_CB    31
+#define V_RST_CB(x) ((x) << S_RST_CB)
+#define F_RST_CB    V_RST_CB(1U)
+
+#define S_CB_START    0
+#define M_CB_START    0xfffffffU
+#define V_CB_START(x) ((x) << S_CB_START)
+#define G_CB_START(x) (((x) >> S_CB_START) & M_CB_START)
+
+#define A_CIM_TCAM_BIST_CB_PASS 0x7c64
+
+#define S_CB_PASS    0
+#define M_CB_PASS    0xfffffffU
+#define V_CB_PASS(x) ((x) << S_CB_PASS)
+#define G_CB_PASS(x) (((x) >> S_CB_PASS) & M_CB_PASS)
+
+#define A_CIM_TCAM_BIST_CB_BUSY 0x7c68
+
+#define S_CB_BUSY    0
+#define M_CB_BUSY    0xfffffffU
+#define V_CB_BUSY(x) ((x) << S_CB_BUSY)
+#define G_CB_BUSY(x) (((x) >> S_CB_BUSY) & M_CB_BUSY)
+
+#define A_CIM_GFT_MASK 0x7c70
+
 /* registers for module TP */
 #define TP_BASE_ADDR 0x7d00
 
@@ -21613,6 +27018,14 @@
 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
 #define F_CRXPKTXT    V_CRXPKTXT(1U)
 
+#define S_ETOEBYPCSUMNOWAIT    15
+#define V_ETOEBYPCSUMNOWAIT(x) ((x) << S_ETOEBYPCSUMNOWAIT)
+#define F_ETOEBYPCSUMNOWAIT    V_ETOEBYPCSUMNOWAIT(1U)
+
+#define S_ENICCSUMNOWAIT    14
+#define V_ENICCSUMNOWAIT(x) ((x) << S_ENICCSUMNOWAIT)
+#define F_ENICCSUMNOWAIT    V_ENICCSUMNOWAIT(1U)
+
 #define A_TP_GLOBAL_CONFIG 0x7d08
 
 #define S_SYNCOOKIEPARAMS    26
@@ -21703,6 +27116,31 @@
 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
 #define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)
 
+#define S_RXSACKPARSE    31
+#define V_RXSACKPARSE(x) ((x) << S_RXSACKPARSE)
+#define F_RXSACKPARSE    V_RXSACKPARSE(1U)
+
+#define S_RXSACKFWDMODE    29
+#define M_RXSACKFWDMODE    0x3U
+#define V_RXSACKFWDMODE(x) ((x) << S_RXSACKFWDMODE)
+#define G_RXSACKFWDMODE(x) (((x) >> S_RXSACKFWDMODE) & M_RXSACKFWDMODE)
+
+#define S_SRVRCHRSSEN    26
+#define V_SRVRCHRSSEN(x) ((x) << S_SRVRCHRSSEN)
+#define F_SRVRCHRSSEN    V_SRVRCHRSSEN(1U)
+
+#define S_LBCHNDISTEN    23
+#define V_LBCHNDISTEN(x) ((x) << S_LBCHNDISTEN)
+#define F_LBCHNDISTEN    V_LBCHNDISTEN(1U)
+
+#define S_ETHTNLLEN2X    20
+#define V_ETHTNLLEN2X(x) ((x) << S_ETHTNLLEN2X)
+#define F_ETHTNLLEN2X    V_ETHTNLLEN2X(1U)
+
+#define S_EGLBCHNDISTEN    19
+#define V_EGLBCHNDISTEN(x) ((x) << S_EGLBCHNDISTEN)
+#define F_EGLBCHNDISTEN    V_EGLBCHNDISTEN(1U)
+
 #define A_TP_DB_CONFIG 0x7d0c
 
 #define S_DBMAXOPCNT    24
@@ -21767,6 +27205,11 @@
 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
 
+#define S_T7_PMRXNUMCHN    29
+#define M_T7_PMRXNUMCHN    0x7U
+#define V_T7_PMRXNUMCHN(x) ((x) << S_T7_PMRXNUMCHN)
+#define G_T7_PMRXNUMCHN(x) (((x) >> S_T7_PMRXNUMCHN) & M_T7_PMRXNUMCHN)
+
 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
 
@@ -21780,6 +27223,83 @@
 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
 
+#define S_T7_PMTXNUMCHN    29
+#define M_T7_PMTXNUMCHN    0x7U
+#define V_T7_PMTXNUMCHN(x) ((x) << S_T7_PMTXNUMCHN)
+#define G_T7_PMTXNUMCHN(x) (((x) >> S_T7_PMTXNUMCHN) & M_T7_PMTXNUMCHN)
+
+#define A_TP_EXT_CONFIG 0x7d3c
+
+#define S_TNLERRORIPSECARW    29
+#define V_TNLERRORIPSECARW(x) ((x) << S_TNLERRORIPSECARW)
+#define F_TNLERRORIPSECARW    V_TNLERRORIPSECARW(1U)
+
+#define S_TNLERRORIPSECICV    28
+#define V_TNLERRORIPSECICV(x) ((x) << S_TNLERRORIPSECICV)
+#define F_TNLERRORIPSECICV    V_TNLERRORIPSECICV(1U)
+
+#define S_DROPERRORIPSECARW    25
+#define V_DROPERRORIPSECARW(x) ((x) << S_DROPERRORIPSECARW)
+#define F_DROPERRORIPSECARW    V_DROPERRORIPSECARW(1U)
+
+#define S_DROPERRORIPSECICV    24
+#define V_DROPERRORIPSECICV(x) ((x) << S_DROPERRORIPSECICV)
+#define F_DROPERRORIPSECICV    V_DROPERRORIPSECICV(1U)
+
+#define S_MIBRDMAROCEEN    19
+#define V_MIBRDMAROCEEN(x) ((x) << S_MIBRDMAROCEEN)
+#define F_MIBRDMAROCEEN    V_MIBRDMAROCEEN(1U)
+
+#define S_MIBRDMAIWARPEN    18
+#define V_MIBRDMAIWARPEN(x) ((x) << S_MIBRDMAIWARPEN)
+#define F_MIBRDMAIWARPEN    V_MIBRDMAIWARPEN(1U)
+
+#define S_BYPTXDATAACKALLEN    17
+#define V_BYPTXDATAACKALLEN(x) ((x) << S_BYPTXDATAACKALLEN)
+#define F_BYPTXDATAACKALLEN    V_BYPTXDATAACKALLEN(1U)
+
+#define S_DATAACKEXTEN    16
+#define V_DATAACKEXTEN(x) ((x) << S_DATAACKEXTEN)
+#define F_DATAACKEXTEN    V_DATAACKEXTEN(1U)
+
+#define S_MACMATCH11FWD    11
+#define V_MACMATCH11FWD(x) ((x) << S_MACMATCH11FWD)
+#define F_MACMATCH11FWD    V_MACMATCH11FWD(1U)
+
+#define S_USERTMSTPEN    10
+#define V_USERTMSTPEN(x) ((x) << S_USERTMSTPEN)
+#define F_USERTMSTPEN    V_USERTMSTPEN(1U)
+
+#define S_MMGRCACHEDIS    9
+#define V_MMGRCACHEDIS(x) ((x) << S_MMGRCACHEDIS)
+#define F_MMGRCACHEDIS    V_MMGRCACHEDIS(1U)
+
+#define S_TXPKTPACKOUTUDPEN    8
+#define V_TXPKTPACKOUTUDPEN(x) ((x) << S_TXPKTPACKOUTUDPEN)
+#define F_TXPKTPACKOUTUDPEN    V_TXPKTPACKOUTUDPEN(1U)
+
+#define S_IPSECROCECRCMODE    6
+#define M_IPSECROCECRCMODE    0x3U
+#define V_IPSECROCECRCMODE(x) ((x) << S_IPSECROCECRCMODE)
+#define G_IPSECROCECRCMODE(x) (((x) >> S_IPSECROCECRCMODE) & M_IPSECROCECRCMODE)
+
+#define S_IPSECIDXLOC    5
+#define V_IPSECIDXLOC(x) ((x) << S_IPSECIDXLOC)
+#define F_IPSECIDXLOC    V_IPSECIDXLOC(1U)
+
+#define S_IPSECIDXCAPEN    4
+#define V_IPSECIDXCAPEN(x) ((x) << S_IPSECIDXCAPEN)
+#define F_IPSECIDXCAPEN    V_IPSECIDXCAPEN(1U)
+
+#define S_IPSECOFEN    3
+#define V_IPSECOFEN(x) ((x) << S_IPSECOFEN)
+#define F_IPSECOFEN    V_IPSECOFEN(1U)
+
+#define S_IPSECCFG    0
+#define M_IPSECCFG    0x7U
+#define V_IPSECCFG(x) ((x) << S_IPSECCFG)
+#define G_IPSECCFG(x) (((x) >> S_IPSECCFG) & M_IPSECCFG)
+
 #define A_TP_TCP_OPTIONS 0x7d40
 
 #define S_MTUDEFAULT    16
@@ -22615,10 +28135,6 @@
 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
 
-#define S_ENABLECBYP    21
-#define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
-#define F_ENABLECBYP    V_ENABLECBYP(1U)
-
 #define S_LIMITEDTRANSMIT    20
 #define M_LIMITEDTRANSMIT    0xfU
 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
@@ -22779,6 +28295,18 @@
 #define V_ECNSYNECT(x) ((x) << S_ECNSYNECT)
 #define F_ECNSYNECT    V_ECNSYNECT(1U)
 
+#define A_TP_PARA_REG9 0x7d88
+
+#define S_PMMAXXFERLEN3    16
+#define M_PMMAXXFERLEN3    0xffffU
+#define V_PMMAXXFERLEN3(x) ((x) << S_PMMAXXFERLEN3)
+#define G_PMMAXXFERLEN3(x) (((x) >> S_PMMAXXFERLEN3) & M_PMMAXXFERLEN3)
+
+#define S_PMMAXXFERLEN2    0
+#define M_PMMAXXFERLEN2    0xffffU
+#define V_PMMAXXFERLEN2(x) ((x) << S_PMMAXXFERLEN2)
+#define G_PMMAXXFERLEN2(x) (((x) >> S_PMMAXXFERLEN2) & M_PMMAXXFERLEN2)
+
 #define A_TP_ERR_CONFIG 0x7d8c
 
 #define S_TNLERRORPING    30
@@ -22926,6 +28454,11 @@
 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
 
+#define S_ROCETIMERRESOLUTION    24
+#define M_ROCETIMERRESOLUTION    0xffU
+#define V_ROCETIMERRESOLUTION(x) ((x) << S_ROCETIMERRESOLUTION)
+#define G_ROCETIMERRESOLUTION(x) (((x) >> S_ROCETIMERRESOLUTION) & M_ROCETIMERRESOLUTION)
+
 #define A_TP_MSL 0x7d94
 
 #define S_MSL    0
@@ -23423,6 +28956,14 @@
 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
 
+#define S_RRCPLOPT1SMSELEN    11
+#define V_RRCPLOPT1SMSELEN(x) ((x) << S_RRCPLOPT1SMSELEN)
+#define F_RRCPLOPT1SMSELEN    V_RRCPLOPT1SMSELEN(1U)
+
+#define S_RRCPLOPT1BQEN    10
+#define V_RRCPLOPT1BQEN(x) ((x) << S_RRCPLOPT1BQEN)
+#define F_RRCPLOPT1BQEN    V_RRCPLOPT1BQEN(1U)
+
 #define A_TP_RSS_CONFIG_SYN 0x7dfc
 #define A_TP_RSS_CONFIG_VRT 0x7e00
 
@@ -23595,6 +29136,69 @@
 #define V_QUEUE(x) ((x) << S_QUEUE)
 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
 
+#define S_T7_UPDVLD    19
+#define V_T7_UPDVLD(x) ((x) << S_T7_UPDVLD)
+#define F_T7_UPDVLD    V_T7_UPDVLD(1U)
+
+#define S_T7_XOFF    18
+#define V_T7_XOFF(x) ((x) << S_T7_XOFF)
+#define F_T7_XOFF    V_T7_XOFF(1U)
+
+#define S_T7_UPDCHN3    17
+#define V_T7_UPDCHN3(x) ((x) << S_T7_UPDCHN3)
+#define F_T7_UPDCHN3    V_T7_UPDCHN3(1U)
+
+#define S_T7_UPDCHN2    16
+#define V_T7_UPDCHN2(x) ((x) << S_T7_UPDCHN2)
+#define F_T7_UPDCHN2    V_T7_UPDCHN2(1U)
+
+#define S_T7_UPDCHN1    15
+#define V_T7_UPDCHN1(x) ((x) << S_T7_UPDCHN1)
+#define F_T7_UPDCHN1    V_T7_UPDCHN1(1U)
+
+#define S_T7_UPDCHN0    14
+#define V_T7_UPDCHN0(x) ((x) << S_T7_UPDCHN0)
+#define F_T7_UPDCHN0    V_T7_UPDCHN0(1U)
+
+#define S_T7_QUEUE    0
+#define M_T7_QUEUE    0x3fffU
+#define V_T7_QUEUE(x) ((x) << S_T7_QUEUE)
+#define G_T7_QUEUE(x) (((x) >> S_T7_QUEUE) & M_T7_QUEUE)
+
+#define A_TP_RSS_CONFIG_4CH 0x7e08
+
+#define S_BASEQIDEN    1
+#define V_BASEQIDEN(x) ((x) << S_BASEQIDEN)
+#define F_BASEQIDEN    V_BASEQIDEN(1U)
+
+#define S_200GMODE    0
+#define V_200GMODE(x) ((x) << S_200GMODE)
+#define F_200GMODE    V_200GMODE(1U)
+
+#define A_TP_RSS_CONFIG_SRAM 0x7e0c
+
+#define S_SRAMRDDIS    20
+#define V_SRAMRDDIS(x) ((x) << S_SRAMRDDIS)
+#define F_SRAMRDDIS    V_SRAMRDDIS(1U)
+
+#define S_SRAMSTART    19
+#define V_SRAMSTART(x) ((x) << S_SRAMSTART)
+#define F_SRAMSTART    V_SRAMSTART(1U)
+
+#define S_SRAMWRITE    18
+#define V_SRAMWRITE(x) ((x) << S_SRAMWRITE)
+#define F_SRAMWRITE    V_SRAMWRITE(1U)
+
+#define S_SRAMSEL    16
+#define M_SRAMSEL    0x3U
+#define V_SRAMSEL(x) ((x) << S_SRAMSEL)
+#define G_SRAMSEL(x) (((x) >> S_SRAMSEL) & M_SRAMSEL)
+
+#define S_SRAMADDR    0
+#define M_SRAMADDR    0x3fffU
+#define V_SRAMADDR(x) ((x) << S_SRAMADDR)
+#define G_SRAMADDR(x) (((x) >> S_SRAMADDR) & M_SRAMADDR)
+
 #define A_TP_LA_TABLE_0 0x7e10
 
 #define S_VIRTPORT1TABLE    16
@@ -23621,6 +29225,18 @@
 
 #define A_TP_TM_PIO_ADDR 0x7e18
 #define A_TP_TM_PIO_DATA 0x7e1c
+#define A_TP_RX_MOD_CONFIG_CH3_CH2 0x7e20
+
+#define S_RXCHANNELWEIGHT3    8
+#define M_RXCHANNELWEIGHT3    0xffU
+#define V_RXCHANNELWEIGHT3(x) ((x) << S_RXCHANNELWEIGHT3)
+#define G_RXCHANNELWEIGHT3(x) (((x) >> S_RXCHANNELWEIGHT3) & M_RXCHANNELWEIGHT3)
+
+#define S_RXCHANNELWEIGHT2    0
+#define M_RXCHANNELWEIGHT2    0xffU
+#define V_RXCHANNELWEIGHT2(x) ((x) << S_RXCHANNELWEIGHT2)
+#define G_RXCHANNELWEIGHT2(x) (((x) >> S_RXCHANNELWEIGHT2) & M_RXCHANNELWEIGHT2)
+
 #define A_TP_MOD_CONFIG 0x7e24
 
 #define S_RXCHANNELWEIGHT1    24
@@ -23887,6 +29503,30 @@
 #define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR)
 #define F_SRQTABLEPERR    V_SRQTABLEPERR(1U)
 
+#define S_TPCERR    5
+#define V_TPCERR(x) ((x) << S_TPCERR)
+#define F_TPCERR    V_TPCERR(1U)
+
+#define S_OTHERPERR    4
+#define V_OTHERPERR(x) ((x) << S_OTHERPERR)
+#define F_OTHERPERR    V_OTHERPERR(1U)
+
+#define S_TPEING1PERR    3
+#define V_TPEING1PERR(x) ((x) << S_TPEING1PERR)
+#define F_TPEING1PERR    V_TPEING1PERR(1U)
+
+#define S_TPEING0PERR    2
+#define V_TPEING0PERR(x) ((x) << S_TPEING0PERR)
+#define F_TPEING0PERR    V_TPEING0PERR(1U)
+
+#define S_TPEEGPERR    1
+#define V_TPEEGPERR(x) ((x) << S_TPEEGPERR)
+#define F_TPEEGPERR    V_TPEEGPERR(1U)
+
+#define S_TPCPERR    0
+#define V_TPCPERR(x) ((x) << S_TPCPERR)
+#define F_TPCPERR    V_TPCPERR(1U)
+
 #define A_TP_INT_CAUSE 0x7e74
 #define A_TP_PER_ENABLE 0x7e78
 #define A_TP_FLM_FREE_PS_CNT 0x7e80
@@ -23907,6 +29547,11 @@
 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
 
+#define S_T7_FREERXPAGECHN    28
+#define M_T7_FREERXPAGECHN    0x7U
+#define V_T7_FREERXPAGECHN(x) ((x) << S_T7_FREERXPAGECHN)
+#define G_T7_FREERXPAGECHN(x) (((x) >> S_T7_FREERXPAGECHN) & M_T7_FREERXPAGECHN)
+
 #define A_TP_FLM_FREE_TX_CNT 0x7e88
 
 #define S_FREETXPAGECHN    28
@@ -23919,6 +29564,11 @@
 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
 
+#define S_T7_FREETXPAGECHN    28
+#define M_T7_FREETXPAGECHN    0x7U
+#define V_T7_FREETXPAGECHN(x) ((x) << S_T7_FREETXPAGECHN)
+#define G_T7_FREETXPAGECHN(x) (((x) >> S_T7_FREETXPAGECHN) & M_T7_FREETXPAGECHN)
+
 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
 #define A_TP_TM_HEAP_POP_CNT 0x7e90
 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
@@ -24111,6 +29761,38 @@
 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
 
+#define S_RXCOMMITRESET3    7
+#define V_RXCOMMITRESET3(x) ((x) << S_RXCOMMITRESET3)
+#define F_RXCOMMITRESET3    V_RXCOMMITRESET3(1U)
+
+#define S_RXCOMMITRESET2    6
+#define V_RXCOMMITRESET2(x) ((x) << S_RXCOMMITRESET2)
+#define F_RXCOMMITRESET2    V_RXCOMMITRESET2(1U)
+
+#define S_T7_RXCOMMITRESET1    5
+#define V_T7_RXCOMMITRESET1(x) ((x) << S_T7_RXCOMMITRESET1)
+#define F_T7_RXCOMMITRESET1    V_T7_RXCOMMITRESET1(1U)
+
+#define S_T7_RXCOMMITRESET0    4
+#define V_T7_RXCOMMITRESET0(x) ((x) << S_T7_RXCOMMITRESET0)
+#define F_T7_RXCOMMITRESET0    V_T7_RXCOMMITRESET0(1U)
+
+#define S_RXFORCECONG3    3
+#define V_RXFORCECONG3(x) ((x) << S_RXFORCECONG3)
+#define F_RXFORCECONG3    V_RXFORCECONG3(1U)
+
+#define S_RXFORCECONG2    2
+#define V_RXFORCECONG2(x) ((x) << S_RXFORCECONG2)
+#define F_RXFORCECONG2    V_RXFORCECONG2(1U)
+
+#define S_T7_RXFORCECONG1    1
+#define V_T7_RXFORCECONG1(x) ((x) << S_T7_RXFORCECONG1)
+#define F_T7_RXFORCECONG1    V_T7_RXFORCECONG1(1U)
+
+#define S_T7_RXFORCECONG0    0
+#define V_T7_RXFORCECONG0(x) ((x) << S_T7_RXFORCECONG0)
+#define F_T7_RXFORCECONG0    V_T7_RXFORCECONG0(1U)
+
 #define A_TP_TX_SCHED 0x7eb4
 
 #define S_COMMITRESET3    31
@@ -24229,6 +29911,14 @@
 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
 #define F_RXMODXOFF0    V_RXMODXOFF0(1U)
 
+#define S_RXMODXOFF3    3
+#define V_RXMODXOFF3(x) ((x) << S_RXMODXOFF3)
+#define F_RXMODXOFF3    V_RXMODXOFF3(1U)
+
+#define S_RXMODXOFF2    2
+#define V_RXMODXOFF2(x) ((x) << S_RXMODXOFF2)
+#define F_RXMODXOFF2    V_RXMODXOFF2(1U)
+
 #define A_TP_TX_ORATE 0x7ebc
 
 #define S_OFDRATE3    24
@@ -24313,6 +30003,37 @@
 
 #define A_TP_DBG_LA_DATAL 0x7ed8
 #define A_TP_DBG_LA_DATAH 0x7edc
+#define A_TP_DBG_LA_FILTER 0x7ee0
+
+#define S_FILTERTID    12
+#define M_FILTERTID    0xfffffU
+#define V_FILTERTID(x) ((x) << S_FILTERTID)
+#define G_FILTERTID(x) (((x) >> S_FILTERTID) & M_FILTERTID)
+
+#define S_ENTIDFILTER    5
+#define V_ENTIDFILTER(x) ((x) << S_ENTIDFILTER)
+#define F_ENTIDFILTER    V_ENTIDFILTER(1U)
+
+#define S_ENOFFLOAD    4
+#define V_ENOFFLOAD(x) ((x) << S_ENOFFLOAD)
+#define F_ENOFFLOAD    V_ENOFFLOAD(1U)
+
+#define S_ENTUNNEL    3
+#define V_ENTUNNEL(x) ((x) << S_ENTUNNEL)
+#define F_ENTUNNEL    V_ENTUNNEL(1U)
+
+#define S_ENI    2
+#define V_ENI(x) ((x) << S_ENI)
+#define F_ENI    V_ENI(1U)
+
+#define S_ENC    1
+#define V_ENC(x) ((x) << S_ENC)
+#define F_ENC    V_ENC(1U)
+
+#define S_ENE    0
+#define V_ENE(x) ((x) << S_ENE)
+#define F_ENE    V_ENE(1U)
+
 #define A_TP_PROTOCOL_CNTRL 0x7ee8
 
 #define S_WRITEENABLE    31
@@ -24348,6 +30069,546 @@
 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
 
+#define A_TP_INIC_CTRL0 0x7f00
+#define A_TP_INIC_DBG 0x7f04
+#define A_TP_INIC_PERR_ENABLE 0x7f08
+
+#define S_INICMAC1_ERR    16
+#define M_INICMAC1_ERR    0x3fU
+#define V_INICMAC1_ERR(x) ((x) << S_INICMAC1_ERR)
+#define G_INICMAC1_ERR(x) (((x) >> S_INICMAC1_ERR) & M_INICMAC1_ERR)
+
+#define S_INICMAC0_ERR    0
+#define M_INICMAC0_ERR    0x3fU
+#define V_INICMAC0_ERR(x) ((x) << S_INICMAC0_ERR)
+#define G_INICMAC0_ERR(x) (((x) >> S_INICMAC0_ERR) & M_INICMAC0_ERR)
+
+#define A_TP_INIC_PERR_CAUSE 0x7f0c
+#define A_TP_PARA_REG10 0x7f20
+
+#define S_DIS39320FIX    20
+#define V_DIS39320FIX(x) ((x) << S_DIS39320FIX)
+#define F_DIS39320FIX    V_DIS39320FIX(1U)
+
+#define S_IWARPMAXPDULEN    16
+#define M_IWARPMAXPDULEN    0xfU
+#define V_IWARPMAXPDULEN(x) ((x) << S_IWARPMAXPDULEN)
+#define G_IWARPMAXPDULEN(x) (((x) >> S_IWARPMAXPDULEN) & M_IWARPMAXPDULEN)
+
+#define S_TLSMAXRXDATA    0
+#define M_TLSMAXRXDATA    0xffffU
+#define V_TLSMAXRXDATA(x) ((x) << S_TLSMAXRXDATA)
+#define G_TLSMAXRXDATA(x) (((x) >> S_TLSMAXRXDATA) & M_TLSMAXRXDATA)
+
+#define A_TP_TCAM_BIST_CTRL 0x7f24
+#define A_TP_TCAM_BIST_CB_PASS 0x7f28
+#define A_TP_TCAM_BIST_CB_BUSY 0x7f2c
+#define A_TP_C_PERR_ENABLE 0x7f30
+
+#define S_DMXFIFOOVFL    26
+#define V_DMXFIFOOVFL(x) ((x) << S_DMXFIFOOVFL)
+#define F_DMXFIFOOVFL    V_DMXFIFOOVFL(1U)
+
+#define S_URX2TPCDDPINTF    25
+#define V_URX2TPCDDPINTF(x) ((x) << S_URX2TPCDDPINTF)
+#define F_URX2TPCDDPINTF    V_URX2TPCDDPINTF(1U)
+
+#define S_TPCDISPTOKENFIFO    24
+#define V_TPCDISPTOKENFIFO(x) ((x) << S_TPCDISPTOKENFIFO)
+#define F_TPCDISPTOKENFIFO    V_TPCDISPTOKENFIFO(1U)
+
+#define S_TPCDISPCPLFIFO3    23
+#define V_TPCDISPCPLFIFO3(x) ((x) << S_TPCDISPCPLFIFO3)
+#define F_TPCDISPCPLFIFO3    V_TPCDISPCPLFIFO3(1U)
+
+#define S_TPCDISPCPLFIFO2    22
+#define V_TPCDISPCPLFIFO2(x) ((x) << S_TPCDISPCPLFIFO2)
+#define F_TPCDISPCPLFIFO2    V_TPCDISPCPLFIFO2(1U)
+
+#define S_TPCDISPCPLFIFO1    21
+#define V_TPCDISPCPLFIFO1(x) ((x) << S_TPCDISPCPLFIFO1)
+#define F_TPCDISPCPLFIFO1    V_TPCDISPCPLFIFO1(1U)
+
+#define S_TPCDISPCPLFIFO0    20
+#define V_TPCDISPCPLFIFO0(x) ((x) << S_TPCDISPCPLFIFO0)
+#define F_TPCDISPCPLFIFO0    V_TPCDISPCPLFIFO0(1U)
+
+#define S_URXPLDINTFCRC3    19
+#define V_URXPLDINTFCRC3(x) ((x) << S_URXPLDINTFCRC3)
+#define F_URXPLDINTFCRC3    V_URXPLDINTFCRC3(1U)
+
+#define S_URXPLDINTFCRC2    18
+#define V_URXPLDINTFCRC2(x) ((x) << S_URXPLDINTFCRC2)
+#define F_URXPLDINTFCRC2    V_URXPLDINTFCRC2(1U)
+
+#define S_URXPLDINTFCRC1    17
+#define V_URXPLDINTFCRC1(x) ((x) << S_URXPLDINTFCRC1)
+#define F_URXPLDINTFCRC1    V_URXPLDINTFCRC1(1U)
+
+#define S_URXPLDINTFCRC0    16
+#define V_URXPLDINTFCRC0(x) ((x) << S_URXPLDINTFCRC0)
+#define F_URXPLDINTFCRC0    V_URXPLDINTFCRC0(1U)
+
+#define S_DMXDBFIFO    15
+#define V_DMXDBFIFO(x) ((x) << S_DMXDBFIFO)
+#define F_DMXDBFIFO    V_DMXDBFIFO(1U)
+
+#define S_DMXDBSRAM    14
+#define V_DMXDBSRAM(x) ((x) << S_DMXDBSRAM)
+#define F_DMXDBSRAM    V_DMXDBSRAM(1U)
+
+#define S_DMXCPLFIFO    13
+#define V_DMXCPLFIFO(x) ((x) << S_DMXCPLFIFO)
+#define F_DMXCPLFIFO    V_DMXCPLFIFO(1U)
+
+#define S_DMXCPLSRAM    12
+#define V_DMXCPLSRAM(x) ((x) << S_DMXCPLSRAM)
+#define F_DMXCPLSRAM    V_DMXCPLSRAM(1U)
+
+#define S_DMXCSUMFIFO    11
+#define V_DMXCSUMFIFO(x) ((x) << S_DMXCSUMFIFO)
+#define F_DMXCSUMFIFO    V_DMXCSUMFIFO(1U)
+
+#define S_DMXLENFIFO    10
+#define V_DMXLENFIFO(x) ((x) << S_DMXLENFIFO)
+#define F_DMXLENFIFO    V_DMXLENFIFO(1U)
+
+#define S_DMXCHECKFIFO    9
+#define V_DMXCHECKFIFO(x) ((x) << S_DMXCHECKFIFO)
+#define F_DMXCHECKFIFO    V_DMXCHECKFIFO(1U)
+
+#define S_DMXWINFIFO    8
+#define V_DMXWINFIFO(x) ((x) << S_DMXWINFIFO)
+#define F_DMXWINFIFO    V_DMXWINFIFO(1U)
+
+#define S_EGTOKENFIFO    7
+#define V_EGTOKENFIFO(x) ((x) << S_EGTOKENFIFO)
+#define F_EGTOKENFIFO    V_EGTOKENFIFO(1U)
+
+#define S_EGDATAFIFO    6
+#define V_EGDATAFIFO(x) ((x) << S_EGDATAFIFO)
+#define F_EGDATAFIFO    V_EGDATAFIFO(1U)
+
+#define S_UTX2TPCINTF3    5
+#define V_UTX2TPCINTF3(x) ((x) << S_UTX2TPCINTF3)
+#define F_UTX2TPCINTF3    V_UTX2TPCINTF3(1U)
+
+#define S_UTX2TPCINTF2    4
+#define V_UTX2TPCINTF2(x) ((x) << S_UTX2TPCINTF2)
+#define F_UTX2TPCINTF2    V_UTX2TPCINTF2(1U)
+
+#define S_UTX2TPCINTF1    3
+#define V_UTX2TPCINTF1(x) ((x) << S_UTX2TPCINTF1)
+#define F_UTX2TPCINTF1    V_UTX2TPCINTF1(1U)
+
+#define S_UTX2TPCINTF0    2
+#define V_UTX2TPCINTF0(x) ((x) << S_UTX2TPCINTF0)
+#define F_UTX2TPCINTF0    V_UTX2TPCINTF0(1U)
+
+#define S_LBKTOKENFIFO    1
+#define V_LBKTOKENFIFO(x) ((x) << S_LBKTOKENFIFO)
+#define F_LBKTOKENFIFO    V_LBKTOKENFIFO(1U)
+
+#define S_LBKDATAFIFO    0
+#define V_LBKDATAFIFO(x) ((x) << S_LBKDATAFIFO)
+#define F_LBKDATAFIFO    V_LBKDATAFIFO(1U)
+
+#define A_TP_C_PERR_CAUSE 0x7f34
+#define A_TP_E_EG_PERR_ENABLE 0x7f38
+
+#define S_MPSLPBKTOKENFIFO    25
+#define V_MPSLPBKTOKENFIFO(x) ((x) << S_MPSLPBKTOKENFIFO)
+#define F_MPSLPBKTOKENFIFO    V_MPSLPBKTOKENFIFO(1U)
+
+#define S_MPSMACTOKENFIFO    24
+#define V_MPSMACTOKENFIFO(x) ((x) << S_MPSMACTOKENFIFO)
+#define F_MPSMACTOKENFIFO    V_MPSMACTOKENFIFO(1U)
+
+#define S_DISPIPSECFIFO3    23
+#define V_DISPIPSECFIFO3(x) ((x) << S_DISPIPSECFIFO3)
+#define F_DISPIPSECFIFO3    V_DISPIPSECFIFO3(1U)
+
+#define S_DISPTCPFIFO3    22
+#define V_DISPTCPFIFO3(x) ((x) << S_DISPTCPFIFO3)
+#define F_DISPTCPFIFO3    V_DISPTCPFIFO3(1U)
+
+#define S_DISPIPFIFO3    21
+#define V_DISPIPFIFO3(x) ((x) << S_DISPIPFIFO3)
+#define F_DISPIPFIFO3    V_DISPIPFIFO3(1U)
+
+#define S_DISPETHFIFO3    20
+#define V_DISPETHFIFO3(x) ((x) << S_DISPETHFIFO3)
+#define F_DISPETHFIFO3    V_DISPETHFIFO3(1U)
+
+#define S_DISPGREFIFO3    19
+#define V_DISPGREFIFO3(x) ((x) << S_DISPGREFIFO3)
+#define F_DISPGREFIFO3    V_DISPGREFIFO3(1U)
+
+#define S_DISPCPL5FIFO3    18
+#define V_DISPCPL5FIFO3(x) ((x) << S_DISPCPL5FIFO3)
+#define F_DISPCPL5FIFO3    V_DISPCPL5FIFO3(1U)
+
+#define S_DISPIPSECFIFO2    17
+#define V_DISPIPSECFIFO2(x) ((x) << S_DISPIPSECFIFO2)
+#define F_DISPIPSECFIFO2    V_DISPIPSECFIFO2(1U)
+
+#define S_DISPTCPFIFO2    16
+#define V_DISPTCPFIFO2(x) ((x) << S_DISPTCPFIFO2)
+#define F_DISPTCPFIFO2    V_DISPTCPFIFO2(1U)
+
+#define S_DISPIPFIFO2    15
+#define V_DISPIPFIFO2(x) ((x) << S_DISPIPFIFO2)
+#define F_DISPIPFIFO2    V_DISPIPFIFO2(1U)
+
+#define S_DISPETHFIFO2    14
+#define V_DISPETHFIFO2(x) ((x) << S_DISPETHFIFO2)
+#define F_DISPETHFIFO2    V_DISPETHFIFO2(1U)
+
+#define S_DISPGREFIFO2    13
+#define V_DISPGREFIFO2(x) ((x) << S_DISPGREFIFO2)
+#define F_DISPGREFIFO2    V_DISPGREFIFO2(1U)
+
+#define S_DISPCPL5FIFO2    12
+#define V_DISPCPL5FIFO2(x) ((x) << S_DISPCPL5FIFO2)
+#define F_DISPCPL5FIFO2    V_DISPCPL5FIFO2(1U)
+
+#define S_DISPIPSECFIFO1    11
+#define V_DISPIPSECFIFO1(x) ((x) << S_DISPIPSECFIFO1)
+#define F_DISPIPSECFIFO1    V_DISPIPSECFIFO1(1U)
+
+#define S_DISPTCPFIFO1    10
+#define V_DISPTCPFIFO1(x) ((x) << S_DISPTCPFIFO1)
+#define F_DISPTCPFIFO1    V_DISPTCPFIFO1(1U)
+
+#define S_DISPIPFIFO1    9
+#define V_DISPIPFIFO1(x) ((x) << S_DISPIPFIFO1)
+#define F_DISPIPFIFO1    V_DISPIPFIFO1(1U)
+
+#define S_DISPETHFIFO1    8
+#define V_DISPETHFIFO1(x) ((x) << S_DISPETHFIFO1)
+#define F_DISPETHFIFO1    V_DISPETHFIFO1(1U)
+
+#define S_DISPGREFIFO1    7
+#define V_DISPGREFIFO1(x) ((x) << S_DISPGREFIFO1)
+#define F_DISPGREFIFO1    V_DISPGREFIFO1(1U)
+
+#define S_DISPCPL5FIFO1    6
+#define V_DISPCPL5FIFO1(x) ((x) << S_DISPCPL5FIFO1)
+#define F_DISPCPL5FIFO1    V_DISPCPL5FIFO1(1U)
+
+#define S_DISPIPSECFIFO0    5
+#define V_DISPIPSECFIFO0(x) ((x) << S_DISPIPSECFIFO0)
+#define F_DISPIPSECFIFO0    V_DISPIPSECFIFO0(1U)
+
+#define S_DISPTCPFIFO0    4
+#define V_DISPTCPFIFO0(x) ((x) << S_DISPTCPFIFO0)
+#define F_DISPTCPFIFO0    V_DISPTCPFIFO0(1U)
+
+#define S_DISPIPFIFO0    3
+#define V_DISPIPFIFO0(x) ((x) << S_DISPIPFIFO0)
+#define F_DISPIPFIFO0    V_DISPIPFIFO0(1U)
+
+#define S_DISPETHFIFO0    2
+#define V_DISPETHFIFO0(x) ((x) << S_DISPETHFIFO0)
+#define F_DISPETHFIFO0    V_DISPETHFIFO0(1U)
+
+#define S_DISPGREFIFO0    1
+#define V_DISPGREFIFO0(x) ((x) << S_DISPGREFIFO0)
+#define F_DISPGREFIFO0    V_DISPGREFIFO0(1U)
+
+#define S_DISPCPL5FIFO0    0
+#define V_DISPCPL5FIFO0(x) ((x) << S_DISPCPL5FIFO0)
+#define F_DISPCPL5FIFO0    V_DISPCPL5FIFO0(1U)
+
+#define A_TP_E_EG_PERR_CAUSE 0x7f3c
+#define A_TP_E_IN0_PERR_ENABLE 0x7f40
+
+#define S_DMXISSFIFO    30
+#define V_DMXISSFIFO(x) ((x) << S_DMXISSFIFO)
+#define F_DMXISSFIFO    V_DMXISSFIFO(1U)
+
+#define S_DMXERRFIFO    29
+#define V_DMXERRFIFO(x) ((x) << S_DMXERRFIFO)
+#define F_DMXERRFIFO    V_DMXERRFIFO(1U)
+
+#define S_DMXATTFIFO    28
+#define V_DMXATTFIFO(x) ((x) << S_DMXATTFIFO)
+#define F_DMXATTFIFO    V_DMXATTFIFO(1U)
+
+#define S_DMXTCPFIFO    27
+#define V_DMXTCPFIFO(x) ((x) << S_DMXTCPFIFO)
+#define F_DMXTCPFIFO    V_DMXTCPFIFO(1U)
+
+#define S_DMXMPAFIFO    26
+#define V_DMXMPAFIFO(x) ((x) << S_DMXMPAFIFO)
+#define F_DMXMPAFIFO    V_DMXMPAFIFO(1U)
+
+#define S_DMXOPTFIFO    25
+#define V_DMXOPTFIFO(x) ((x) << S_DMXOPTFIFO)
+#define F_DMXOPTFIFO    V_DMXOPTFIFO(1U)
+
+#define S_INGTOKENFIFO    24
+#define V_INGTOKENFIFO(x) ((x) << S_INGTOKENFIFO)
+#define F_INGTOKENFIFO    V_INGTOKENFIFO(1U)
+
+#define S_DMXPLDCHKOVFL1    21
+#define V_DMXPLDCHKOVFL1(x) ((x) << S_DMXPLDCHKOVFL1)
+#define F_DMXPLDCHKOVFL1    V_DMXPLDCHKOVFL1(1U)
+
+#define S_DMXPLDCHKFIFO1    20
+#define V_DMXPLDCHKFIFO1(x) ((x) << S_DMXPLDCHKFIFO1)
+#define F_DMXPLDCHKFIFO1    V_DMXPLDCHKFIFO1(1U)
+
+#define S_DMXOPTFIFO1    19
+#define V_DMXOPTFIFO1(x) ((x) << S_DMXOPTFIFO1)
+#define F_DMXOPTFIFO1    V_DMXOPTFIFO1(1U)
+
+#define S_DMXMPAFIFO1    18
+#define V_DMXMPAFIFO1(x) ((x) << S_DMXMPAFIFO1)
+#define F_DMXMPAFIFO1    V_DMXMPAFIFO1(1U)
+
+#define S_DMXDBFIFO1    17
+#define V_DMXDBFIFO1(x) ((x) << S_DMXDBFIFO1)
+#define F_DMXDBFIFO1    V_DMXDBFIFO1(1U)
+
+#define S_DMXATTFIFO1    16
+#define V_DMXATTFIFO1(x) ((x) << S_DMXATTFIFO1)
+#define F_DMXATTFIFO1    V_DMXATTFIFO1(1U)
+
+#define S_DMXISSFIFO1    15
+#define V_DMXISSFIFO1(x) ((x) << S_DMXISSFIFO1)
+#define F_DMXISSFIFO1    V_DMXISSFIFO1(1U)
+
+#define S_DMXTCPFIFO1    14
+#define V_DMXTCPFIFO1(x) ((x) << S_DMXTCPFIFO1)
+#define F_DMXTCPFIFO1    V_DMXTCPFIFO1(1U)
+
+#define S_DMXERRFIFO1    13
+#define V_DMXERRFIFO1(x) ((x) << S_DMXERRFIFO1)
+#define F_DMXERRFIFO1    V_DMXERRFIFO1(1U)
+
+#define S_MPS2TPINTF1    12
+#define V_MPS2TPINTF1(x) ((x) << S_MPS2TPINTF1)
+#define F_MPS2TPINTF1    V_MPS2TPINTF1(1U)
+
+#define S_DMXPLDCHKOVFL0    9
+#define V_DMXPLDCHKOVFL0(x) ((x) << S_DMXPLDCHKOVFL0)
+#define F_DMXPLDCHKOVFL0    V_DMXPLDCHKOVFL0(1U)
+
+#define S_DMXPLDCHKFIFO0    8
+#define V_DMXPLDCHKFIFO0(x) ((x) << S_DMXPLDCHKFIFO0)
+#define F_DMXPLDCHKFIFO0    V_DMXPLDCHKFIFO0(1U)
+
+#define S_DMXOPTFIFO0    7
+#define V_DMXOPTFIFO0(x) ((x) << S_DMXOPTFIFO0)
+#define F_DMXOPTFIFO0    V_DMXOPTFIFO0(1U)
+
+#define S_DMXMPAFIFO0    6
+#define V_DMXMPAFIFO0(x) ((x) << S_DMXMPAFIFO0)
+#define F_DMXMPAFIFO0    V_DMXMPAFIFO0(1U)
+
+#define S_DMXDBFIFO0    5
+#define V_DMXDBFIFO0(x) ((x) << S_DMXDBFIFO0)
+#define F_DMXDBFIFO0    V_DMXDBFIFO0(1U)
+
+#define S_DMXATTFIFO0    4
+#define V_DMXATTFIFO0(x) ((x) << S_DMXATTFIFO0)
+#define F_DMXATTFIFO0    V_DMXATTFIFO0(1U)
+
+#define S_DMXISSFIFO0    3
+#define V_DMXISSFIFO0(x) ((x) << S_DMXISSFIFO0)
+#define F_DMXISSFIFO0    V_DMXISSFIFO0(1U)
+
+#define S_DMXTCPFIFO0    2
+#define V_DMXTCPFIFO0(x) ((x) << S_DMXTCPFIFO0)
+#define F_DMXTCPFIFO0    V_DMXTCPFIFO0(1U)
+
+#define S_DMXERRFIFO0    1
+#define V_DMXERRFIFO0(x) ((x) << S_DMXERRFIFO0)
+#define F_DMXERRFIFO0    V_DMXERRFIFO0(1U)
+
+#define S_MPS2TPINTF0    0
+#define V_MPS2TPINTF0(x) ((x) << S_MPS2TPINTF0)
+#define F_MPS2TPINTF0    V_MPS2TPINTF0(1U)
+
+#define A_TP_E_IN0_PERR_CAUSE 0x7f44
+#define A_TP_E_IN1_PERR_ENABLE 0x7f48
+
+#define S_DMXPLDCHKOVFL3    21
+#define V_DMXPLDCHKOVFL3(x) ((x) << S_DMXPLDCHKOVFL3)
+#define F_DMXPLDCHKOVFL3    V_DMXPLDCHKOVFL3(1U)
+
+#define S_DMXPLDCHKFIFO3    20
+#define V_DMXPLDCHKFIFO3(x) ((x) << S_DMXPLDCHKFIFO3)
+#define F_DMXPLDCHKFIFO3    V_DMXPLDCHKFIFO3(1U)
+
+#define S_DMXOPTFIFO3    19
+#define V_DMXOPTFIFO3(x) ((x) << S_DMXOPTFIFO3)
+#define F_DMXOPTFIFO3    V_DMXOPTFIFO3(1U)
+
+#define S_DMXMPAFIFO3    18
+#define V_DMXMPAFIFO3(x) ((x) << S_DMXMPAFIFO3)
+#define F_DMXMPAFIFO3    V_DMXMPAFIFO3(1U)
+
+#define S_DMXDBFIFO3    17
+#define V_DMXDBFIFO3(x) ((x) << S_DMXDBFIFO3)
+#define F_DMXDBFIFO3    V_DMXDBFIFO3(1U)
+
+#define S_DMXATTFIFO3    16
+#define V_DMXATTFIFO3(x) ((x) << S_DMXATTFIFO3)
+#define F_DMXATTFIFO3    V_DMXATTFIFO3(1U)
+
+#define S_DMXISSFIFO3    15
+#define V_DMXISSFIFO3(x) ((x) << S_DMXISSFIFO3)
+#define F_DMXISSFIFO3    V_DMXISSFIFO3(1U)
+
+#define S_DMXTCPFIFO3    14
+#define V_DMXTCPFIFO3(x) ((x) << S_DMXTCPFIFO3)
+#define F_DMXTCPFIFO3    V_DMXTCPFIFO3(1U)
+
+#define S_DMXERRFIFO3    13
+#define V_DMXERRFIFO3(x) ((x) << S_DMXERRFIFO3)
+#define F_DMXERRFIFO3    V_DMXERRFIFO3(1U)
+
+#define S_MPS2TPINTF3    12
+#define V_MPS2TPINTF3(x) ((x) << S_MPS2TPINTF3)
+#define F_MPS2TPINTF3    V_MPS2TPINTF3(1U)
+
+#define S_DMXPLDCHKOVFL2    9
+#define V_DMXPLDCHKOVFL2(x) ((x) << S_DMXPLDCHKOVFL2)
+#define F_DMXPLDCHKOVFL2    V_DMXPLDCHKOVFL2(1U)
+
+#define S_DMXPLDCHKFIFO2    8
+#define V_DMXPLDCHKFIFO2(x) ((x) << S_DMXPLDCHKFIFO2)
+#define F_DMXPLDCHKFIFO2    V_DMXPLDCHKFIFO2(1U)
+
+#define S_DMXOPTFIFO2    7
+#define V_DMXOPTFIFO2(x) ((x) << S_DMXOPTFIFO2)
+#define F_DMXOPTFIFO2    V_DMXOPTFIFO2(1U)
+
+#define S_DMXMPAFIFO2    6
+#define V_DMXMPAFIFO2(x) ((x) << S_DMXMPAFIFO2)
+#define F_DMXMPAFIFO2    V_DMXMPAFIFO2(1U)
+
+#define S_DMXDBFIFO2    5
+#define V_DMXDBFIFO2(x) ((x) << S_DMXDBFIFO2)
+#define F_DMXDBFIFO2    V_DMXDBFIFO2(1U)
+
+#define S_DMXATTFIFO2    4
+#define V_DMXATTFIFO2(x) ((x) << S_DMXATTFIFO2)
+#define F_DMXATTFIFO2    V_DMXATTFIFO2(1U)
+
+#define S_DMXISSFIFO2    3
+#define V_DMXISSFIFO2(x) ((x) << S_DMXISSFIFO2)
+#define F_DMXISSFIFO2    V_DMXISSFIFO2(1U)
+
+#define S_DMXTCPFIFO2    2
+#define V_DMXTCPFIFO2(x) ((x) << S_DMXTCPFIFO2)
+#define F_DMXTCPFIFO2    V_DMXTCPFIFO2(1U)
+
+#define S_DMXERRFIFO2    1
+#define V_DMXERRFIFO2(x) ((x) << S_DMXERRFIFO2)
+#define F_DMXERRFIFO2    V_DMXERRFIFO2(1U)
+
+#define S_MPS2TPINTF2    0
+#define V_MPS2TPINTF2(x) ((x) << S_MPS2TPINTF2)
+#define F_MPS2TPINTF2    V_MPS2TPINTF2(1U)
+
+#define A_TP_E_IN1_PERR_CAUSE 0x7f4c
+#define A_TP_O_PERR_ENABLE 0x7f50
+
+#define S_DMARBTPERR    31
+#define V_DMARBTPERR(x) ((x) << S_DMARBTPERR)
+#define F_DMARBTPERR    V_DMARBTPERR(1U)
+
+#define S_MMGRCACHEDATASRAM    24
+#define V_MMGRCACHEDATASRAM(x) ((x) << S_MMGRCACHEDATASRAM)
+#define F_MMGRCACHEDATASRAM    V_MMGRCACHEDATASRAM(1U)
+
+#define S_MMGRCACHETAGFIFO    23
+#define V_MMGRCACHETAGFIFO(x) ((x) << S_MMGRCACHETAGFIFO)
+#define F_MMGRCACHETAGFIFO    V_MMGRCACHETAGFIFO(1U)
+
+#define S_TPPROTOSRAM    16
+#define V_TPPROTOSRAM(x) ((x) << S_TPPROTOSRAM)
+#define F_TPPROTOSRAM    V_TPPROTOSRAM(1U)
+
+#define S_HSPSRAM    15
+#define V_HSPSRAM(x) ((x) << S_HSPSRAM)
+#define F_HSPSRAM    V_HSPSRAM(1U)
+
+#define S_RATEGRPSRAM    14
+#define V_RATEGRPSRAM(x) ((x) << S_RATEGRPSRAM)
+#define F_RATEGRPSRAM    V_RATEGRPSRAM(1U)
+
+#define S_TXFBSEQFIFO    13
+#define V_TXFBSEQFIFO(x) ((x) << S_TXFBSEQFIFO)
+#define F_TXFBSEQFIFO    V_TXFBSEQFIFO(1U)
+
+#define S_CMDATASRAM    12
+#define V_CMDATASRAM(x) ((x) << S_CMDATASRAM)
+#define F_CMDATASRAM    V_CMDATASRAM(1U)
+
+#define S_CMTAGFIFO    11
+#define V_CMTAGFIFO(x) ((x) << S_CMTAGFIFO)
+#define F_CMTAGFIFO    V_CMTAGFIFO(1U)
+
+#define S_RFCOPFIFO    10
+#define V_RFCOPFIFO(x) ((x) << S_RFCOPFIFO)
+#define F_RFCOPFIFO    V_RFCOPFIFO(1U)
+
+#define S_DELINVFIFO    9
+#define V_DELINVFIFO(x) ((x) << S_DELINVFIFO)
+#define F_DELINVFIFO    V_DELINVFIFO(1U)
+
+#define S_RSSCFGSRAM    8
+#define V_RSSCFGSRAM(x) ((x) << S_RSSCFGSRAM)
+#define F_RSSCFGSRAM    V_RSSCFGSRAM(1U)
+
+#define S_RSSKEYSRAM    7
+#define V_RSSKEYSRAM(x) ((x) << S_RSSKEYSRAM)
+#define F_RSSKEYSRAM    V_RSSKEYSRAM(1U)
+
+#define S_RSSLKPSRAM    6
+#define V_RSSLKPSRAM(x) ((x) << S_RSSLKPSRAM)
+#define F_RSSLKPSRAM    V_RSSLKPSRAM(1U)
+
+#define S_SRQSRAM    5
+#define V_SRQSRAM(x) ((x) << S_SRQSRAM)
+#define F_SRQSRAM    V_SRQSRAM(1U)
+
+#define S_ARPDASRAM    4
+#define V_ARPDASRAM(x) ((x) << S_ARPDASRAM)
+#define F_ARPDASRAM    V_ARPDASRAM(1U)
+
+#define S_ARPSASRAM    3
+#define V_ARPSASRAM(x) ((x) << S_ARPSASRAM)
+#define F_ARPSASRAM    V_ARPSASRAM(1U)
+
+#define S_ARPGRESRAM    2
+#define V_ARPGRESRAM(x) ((x) << S_ARPGRESRAM)
+#define F_ARPGRESRAM    V_ARPGRESRAM(1U)
+
+#define S_ARPIPSECSRAM1    1
+#define V_ARPIPSECSRAM1(x) ((x) << S_ARPIPSECSRAM1)
+#define F_ARPIPSECSRAM1    V_ARPIPSECSRAM1(1U)
+
+#define S_ARPIPSECSRAM0    0
+#define V_ARPIPSECSRAM0(x) ((x) << S_ARPIPSECSRAM0)
+#define F_ARPIPSECSRAM0    V_ARPIPSECSRAM0(1U)
+
+#define A_TP_O_PERR_CAUSE 0x7f54
+#define A_TP_CERR_ENABLE 0x7f58
+
+#define S_TPCEGDATAFIFO    8
+#define V_TPCEGDATAFIFO(x) ((x) << S_TPCEGDATAFIFO)
+#define F_TPCEGDATAFIFO    V_TPCEGDATAFIFO(1U)
+
+#define S_TPCLBKDATAFIFO    7
+#define V_TPCLBKDATAFIFO(x) ((x) << S_TPCLBKDATAFIFO)
+#define F_TPCLBKDATAFIFO    V_TPCLBKDATAFIFO(1U)
+
+#define A_TP_CERR_CAUSE 0x7f5c
 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
 
 #define S_TXTIMERSEPQ7    16
@@ -24520,6 +30781,137 @@
 
 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
+#define A_TP_RX_MOD_Q3_Q2_TIMER_SEPARATOR 0xc
+
+#define S_RXTIMERSEPQ3    16
+#define M_RXTIMERSEPQ3    0xffffU
+#define V_RXTIMERSEPQ3(x) ((x) << S_RXTIMERSEPQ3)
+#define G_RXTIMERSEPQ3(x) (((x) >> S_RXTIMERSEPQ3) & M_RXTIMERSEPQ3)
+
+#define S_RXTIMERSEPQ2    0
+#define M_RXTIMERSEPQ2    0xffffU
+#define V_RXTIMERSEPQ2(x) ((x) << S_RXTIMERSEPQ2)
+#define G_RXTIMERSEPQ2(x) (((x) >> S_RXTIMERSEPQ2) & M_RXTIMERSEPQ2)
+
+#define A_TP_RX_MOD_Q3_Q2_RATE_LIMIT 0xd
+
+#define S_RXRATEINCQ3    24
+#define M_RXRATEINCQ3    0xffU
+#define V_RXRATEINCQ3(x) ((x) << S_RXRATEINCQ3)
+#define G_RXRATEINCQ3(x) (((x) >> S_RXRATEINCQ3) & M_RXRATEINCQ3)
+
+#define S_RXRATETCKQ3    16
+#define M_RXRATETCKQ3    0xffU
+#define V_RXRATETCKQ3(x) ((x) << S_RXRATETCKQ3)
+#define G_RXRATETCKQ3(x) (((x) >> S_RXRATETCKQ3) & M_RXRATETCKQ3)
+
+#define S_RXRATEINCQ2    8
+#define M_RXRATEINCQ2    0xffU
+#define V_RXRATEINCQ2(x) ((x) << S_RXRATEINCQ2)
+#define G_RXRATEINCQ2(x) (((x) >> S_RXRATEINCQ2) & M_RXRATEINCQ2)
+
+#define S_RXRATETCKQ2    0
+#define M_RXRATETCKQ2    0xffU
+#define V_RXRATETCKQ2(x) ((x) << S_RXRATETCKQ2)
+#define G_RXRATETCKQ2(x) (((x) >> S_RXRATETCKQ2) & M_RXRATETCKQ2)
+
+#define A_TP_RX_LPBK_CONG 0x1c
+#define A_TP_RX_SCHED_MOD 0x1d
+
+#define S_T7_ENABLELPBKFULL1    28
+#define M_T7_ENABLELPBKFULL1    0xfU
+#define V_T7_ENABLELPBKFULL1(x) ((x) << S_T7_ENABLELPBKFULL1)
+#define G_T7_ENABLELPBKFULL1(x) (((x) >> S_T7_ENABLELPBKFULL1) & M_T7_ENABLELPBKFULL1)
+
+#define S_T7_ENABLEFIFOFULL1    24
+#define M_T7_ENABLEFIFOFULL1    0xfU
+#define V_T7_ENABLEFIFOFULL1(x) ((x) << S_T7_ENABLEFIFOFULL1)
+#define G_T7_ENABLEFIFOFULL1(x) (((x) >> S_T7_ENABLEFIFOFULL1) & M_T7_ENABLEFIFOFULL1)
+
+#define S_T7_ENABLEPCMDFULL1    20
+#define M_T7_ENABLEPCMDFULL1    0xfU
+#define V_T7_ENABLEPCMDFULL1(x) ((x) << S_T7_ENABLEPCMDFULL1)
+#define G_T7_ENABLEPCMDFULL1(x) (((x) >> S_T7_ENABLEPCMDFULL1) & M_T7_ENABLEPCMDFULL1)
+
+#define S_T7_ENABLEHDRFULL1    16
+#define M_T7_ENABLEHDRFULL1    0xfU
+#define V_T7_ENABLEHDRFULL1(x) ((x) << S_T7_ENABLEHDRFULL1)
+#define G_T7_ENABLEHDRFULL1(x) (((x) >> S_T7_ENABLEHDRFULL1) & M_T7_ENABLEHDRFULL1)
+
+#define S_T7_ENABLELPBKFULL0    12
+#define M_T7_ENABLELPBKFULL0    0xfU
+#define V_T7_ENABLELPBKFULL0(x) ((x) << S_T7_ENABLELPBKFULL0)
+#define G_T7_ENABLELPBKFULL0(x) (((x) >> S_T7_ENABLELPBKFULL0) & M_T7_ENABLELPBKFULL0)
+
+#define S_T7_ENABLEFIFOFULL0    8
+#define M_T7_ENABLEFIFOFULL0    0xfU
+#define V_T7_ENABLEFIFOFULL0(x) ((x) << S_T7_ENABLEFIFOFULL0)
+#define G_T7_ENABLEFIFOFULL0(x) (((x) >> S_T7_ENABLEFIFOFULL0) & M_T7_ENABLEFIFOFULL0)
+
+#define S_T7_ENABLEPCMDFULL0    4
+#define M_T7_ENABLEPCMDFULL0    0xfU
+#define V_T7_ENABLEPCMDFULL0(x) ((x) << S_T7_ENABLEPCMDFULL0)
+#define G_T7_ENABLEPCMDFULL0(x) (((x) >> S_T7_ENABLEPCMDFULL0) & M_T7_ENABLEPCMDFULL0)
+
+#define S_T7_ENABLEHDRFULL0    0
+#define M_T7_ENABLEHDRFULL0    0xfU
+#define V_T7_ENABLEHDRFULL0(x) ((x) << S_T7_ENABLEHDRFULL0)
+#define G_T7_ENABLEHDRFULL0(x) (((x) >> S_T7_ENABLEHDRFULL0) & M_T7_ENABLEHDRFULL0)
+
+#define A_TP_RX_SCHED_MOD_CH3_CH2 0x1e
+
+#define S_ENABLELPBKFULL3    28
+#define M_ENABLELPBKFULL3    0xfU
+#define V_ENABLELPBKFULL3(x) ((x) << S_ENABLELPBKFULL3)
+#define G_ENABLELPBKFULL3(x) (((x) >> S_ENABLELPBKFULL3) & M_ENABLELPBKFULL3)
+
+#define S_ENABLEFIFOFULL3    24
+#define M_ENABLEFIFOFULL3    0xfU
+#define V_ENABLEFIFOFULL3(x) ((x) << S_ENABLEFIFOFULL3)
+#define G_ENABLEFIFOFULL3(x) (((x) >> S_ENABLEFIFOFULL3) & M_ENABLEFIFOFULL3)
+
+#define S_ENABLEPCMDFULL3    20
+#define M_ENABLEPCMDFULL3    0xfU
+#define V_ENABLEPCMDFULL3(x) ((x) << S_ENABLEPCMDFULL3)
+#define G_ENABLEPCMDFULL3(x) (((x) >> S_ENABLEPCMDFULL3) & M_ENABLEPCMDFULL3)
+
+#define S_ENABLEHDRFULL3    16
+#define M_ENABLEHDRFULL3    0xfU
+#define V_ENABLEHDRFULL3(x) ((x) << S_ENABLEHDRFULL3)
+#define G_ENABLEHDRFULL3(x) (((x) >> S_ENABLEHDRFULL3) & M_ENABLEHDRFULL3)
+
+#define S_ENABLELPBKFULL2    12
+#define M_ENABLELPBKFULL2    0xfU
+#define V_ENABLELPBKFULL2(x) ((x) << S_ENABLELPBKFULL2)
+#define G_ENABLELPBKFULL2(x) (((x) >> S_ENABLELPBKFULL2) & M_ENABLELPBKFULL2)
+
+#define S_ENABLEFIFOFULL2    8
+#define M_ENABLEFIFOFULL2    0xfU
+#define V_ENABLEFIFOFULL2(x) ((x) << S_ENABLEFIFOFULL2)
+#define G_ENABLEFIFOFULL2(x) (((x) >> S_ENABLEFIFOFULL2) & M_ENABLEFIFOFULL2)
+
+#define S_ENABLEPCMDFULL2    4
+#define M_ENABLEPCMDFULL2    0xfU
+#define V_ENABLEPCMDFULL2(x) ((x) << S_ENABLEPCMDFULL2)
+#define G_ENABLEPCMDFULL2(x) (((x) >> S_ENABLEPCMDFULL2) & M_ENABLEPCMDFULL2)
+
+#define S_ENABLEHDRFULL2    0
+#define M_ENABLEHDRFULL2    0xfU
+#define V_ENABLEHDRFULL2(x) ((x) << S_ENABLEHDRFULL2)
+#define G_ENABLEHDRFULL2(x) (((x) >> S_ENABLEHDRFULL2) & M_ENABLEHDRFULL2)
+
+#define A_TP_RX_SCHED_MAP_CH3_CH2 0x1f
+
+#define S_T7_RXMAPCHANNEL3    16
+#define M_T7_RXMAPCHANNEL3    0xffffU
+#define V_T7_RXMAPCHANNEL3(x) ((x) << S_T7_RXMAPCHANNEL3)
+#define G_T7_RXMAPCHANNEL3(x) (((x) >> S_T7_RXMAPCHANNEL3) & M_T7_RXMAPCHANNEL3)
+
+#define S_T7_RXMAPCHANNEL2    0
+#define M_T7_RXMAPCHANNEL2    0xffffU
+#define V_T7_RXMAPCHANNEL2(x) ((x) << S_T7_RXMAPCHANNEL2)
+#define G_T7_RXMAPCHANNEL2(x) (((x) >> S_T7_RXMAPCHANNEL2) & M_T7_RXMAPCHANNEL2)
+
 #define A_TP_RX_SCHED_MAP 0x20
 
 #define S_RXMAPCHANNEL3    24
@@ -24542,6 +30934,16 @@
 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
 
+#define S_T7_RXMAPCHANNEL1    16
+#define M_T7_RXMAPCHANNEL1    0xffffU
+#define V_T7_RXMAPCHANNEL1(x) ((x) << S_T7_RXMAPCHANNEL1)
+#define G_T7_RXMAPCHANNEL1(x) (((x) >> S_T7_RXMAPCHANNEL1) & M_T7_RXMAPCHANNEL1)
+
+#define S_T7_RXMAPCHANNEL0    0
+#define M_T7_RXMAPCHANNEL0    0xffffU
+#define V_T7_RXMAPCHANNEL0(x) ((x) << S_T7_RXMAPCHANNEL0)
+#define G_T7_RXMAPCHANNEL0(x) (((x) >> S_T7_RXMAPCHANNEL0) & M_T7_RXMAPCHANNEL0)
+
 #define A_TP_RX_SCHED_SGE 0x21
 
 #define S_RXSGEMOD1    12
@@ -24570,6 +30972,16 @@
 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
 #define F_RXSGECHANNEL0    V_RXSGECHANNEL0(1U)
 
+#define S_RXSGEMOD3    20
+#define M_RXSGEMOD3    0xfU
+#define V_RXSGEMOD3(x) ((x) << S_RXSGEMOD3)
+#define G_RXSGEMOD3(x) (((x) >> S_RXSGEMOD3) & M_RXSGEMOD3)
+
+#define S_RXSGEMOD2    16
+#define M_RXSGEMOD2    0xfU
+#define V_RXSGEMOD2(x) ((x) << S_RXSGEMOD2)
+#define G_RXSGEMOD2(x) (((x) >> S_RXSGEMOD2) & M_RXSGEMOD2)
+
 #define A_TP_TX_SCHED_MAP 0x22
 
 #define S_TXMAPCHANNEL3    12
@@ -24600,6 +31012,14 @@
 #define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0)
 #define F_TXLPKCHANNEL0    V_TXLPKCHANNEL0(1U)
 
+#define S_TXLPKCHANNEL3    19
+#define V_TXLPKCHANNEL3(x) ((x) << S_TXLPKCHANNEL3)
+#define F_TXLPKCHANNEL3    V_TXLPKCHANNEL3(1U)
+
+#define S_TXLPKCHANNEL2    18
+#define V_TXLPKCHANNEL2(x) ((x) << S_TXLPKCHANNEL2)
+#define F_TXLPKCHANNEL2    V_TXLPKCHANNEL2(1U)
+
 #define A_TP_TX_SCHED_HDR 0x23
 
 #define S_TXMAPHDRCHANNEL7    28
@@ -24827,6 +31247,69 @@
 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
 #define F_RXMAPE2CCHANNEL0    V_RXMAPE2CCHANNEL0(1U)
 
+#define S_T7_LB_MODE    30
+#define M_T7_LB_MODE    0x3U
+#define V_T7_LB_MODE(x) ((x) << S_T7_LB_MODE)
+#define G_T7_LB_MODE(x) (((x) >> S_T7_LB_MODE) & M_T7_LB_MODE)
+
+#define S_ING_LB_MODE    28
+#define M_ING_LB_MODE    0x3U
+#define V_ING_LB_MODE(x) ((x) << S_ING_LB_MODE)
+#define G_ING_LB_MODE(x) (((x) >> S_ING_LB_MODE) & M_ING_LB_MODE)
+
+#define S_RXC_LB_MODE    26
+#define M_RXC_LB_MODE    0x3U
+#define V_RXC_LB_MODE(x) ((x) << S_RXC_LB_MODE)
+#define G_RXC_LB_MODE(x) (((x) >> S_RXC_LB_MODE) & M_RXC_LB_MODE)
+
+#define S_SINGLERXCHANNEL    25
+#define V_SINGLERXCHANNEL(x) ((x) << S_SINGLERXCHANNEL)
+#define F_SINGLERXCHANNEL    V_SINGLERXCHANNEL(1U)
+
+#define S_RXCHANNELCHECK    24
+#define V_RXCHANNELCHECK(x) ((x) << S_RXCHANNELCHECK)
+#define F_RXCHANNELCHECK    V_RXCHANNELCHECK(1U)
+
+#define S_T7_RXMAPC2CCHANNEL3    21
+#define M_T7_RXMAPC2CCHANNEL3    0x7U
+#define V_T7_RXMAPC2CCHANNEL3(x) ((x) << S_T7_RXMAPC2CCHANNEL3)
+#define G_T7_RXMAPC2CCHANNEL3(x) (((x) >> S_T7_RXMAPC2CCHANNEL3) & M_T7_RXMAPC2CCHANNEL3)
+
+#define S_T7_RXMAPC2CCHANNEL2    18
+#define M_T7_RXMAPC2CCHANNEL2    0x7U
+#define V_T7_RXMAPC2CCHANNEL2(x) ((x) << S_T7_RXMAPC2CCHANNEL2)
+#define G_T7_RXMAPC2CCHANNEL2(x) (((x) >> S_T7_RXMAPC2CCHANNEL2) & M_T7_RXMAPC2CCHANNEL2)
+
+#define S_T7_RXMAPC2CCHANNEL1    15
+#define M_T7_RXMAPC2CCHANNEL1    0x7U
+#define V_T7_RXMAPC2CCHANNEL1(x) ((x) << S_T7_RXMAPC2CCHANNEL1)
+#define G_T7_RXMAPC2CCHANNEL1(x) (((x) >> S_T7_RXMAPC2CCHANNEL1) & M_T7_RXMAPC2CCHANNEL1)
+
+#define S_T7_RXMAPC2CCHANNEL0    12
+#define M_T7_RXMAPC2CCHANNEL0    0x7U
+#define V_T7_RXMAPC2CCHANNEL0(x) ((x) << S_T7_RXMAPC2CCHANNEL0)
+#define G_T7_RXMAPC2CCHANNEL0(x) (((x) >> S_T7_RXMAPC2CCHANNEL0) & M_T7_RXMAPC2CCHANNEL0)
+
+#define S_T7_RXMAPE2CCHANNEL3    9
+#define M_T7_RXMAPE2CCHANNEL3    0x7U
+#define V_T7_RXMAPE2CCHANNEL3(x) ((x) << S_T7_RXMAPE2CCHANNEL3)
+#define G_T7_RXMAPE2CCHANNEL3(x) (((x) >> S_T7_RXMAPE2CCHANNEL3) & M_T7_RXMAPE2CCHANNEL3)
+
+#define S_T7_RXMAPE2CCHANNEL2    6
+#define M_T7_RXMAPE2CCHANNEL2    0x7U
+#define V_T7_RXMAPE2CCHANNEL2(x) ((x) << S_T7_RXMAPE2CCHANNEL2)
+#define G_T7_RXMAPE2CCHANNEL2(x) (((x) >> S_T7_RXMAPE2CCHANNEL2) & M_T7_RXMAPE2CCHANNEL2)
+
+#define S_T7_RXMAPE2CCHANNEL1    3
+#define M_T7_RXMAPE2CCHANNEL1    0x7U
+#define V_T7_RXMAPE2CCHANNEL1(x) ((x) << S_T7_RXMAPE2CCHANNEL1)
+#define G_T7_RXMAPE2CCHANNEL1(x) (((x) >> S_T7_RXMAPE2CCHANNEL1) & M_T7_RXMAPE2CCHANNEL1)
+
+#define S_T7_RXMAPE2CCHANNEL0    0
+#define M_T7_RXMAPE2CCHANNEL0    0x7U
+#define V_T7_RXMAPE2CCHANNEL0(x) ((x) << S_T7_RXMAPE2CCHANNEL0)
+#define G_T7_RXMAPE2CCHANNEL0(x) (((x) >> S_T7_RXMAPE2CCHANNEL0) & M_T7_RXMAPE2CCHANNEL0)
+
 #define A_TP_RX_LPBK 0x28
 #define A_TP_TX_LPBK 0x29
 #define A_TP_TX_SCHED_PPP 0x2a
@@ -24873,6 +31356,55 @@
 #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
 #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
 
+#define A_TP_RX_SCHED_FIFO_CH3_CH2 0x2c
+
+#define S_COMMITLIMIT3H    24
+#define M_COMMITLIMIT3H    0xffU
+#define V_COMMITLIMIT3H(x) ((x) << S_COMMITLIMIT3H)
+#define G_COMMITLIMIT3H(x) (((x) >> S_COMMITLIMIT3H) & M_COMMITLIMIT3H)
+
+#define S_COMMITLIMIT3L    16
+#define M_COMMITLIMIT3L    0xffU
+#define V_COMMITLIMIT3L(x) ((x) << S_COMMITLIMIT3L)
+#define G_COMMITLIMIT3L(x) (((x) >> S_COMMITLIMIT3L) & M_COMMITLIMIT3L)
+
+#define S_COMMITLIMIT2H    8
+#define M_COMMITLIMIT2H    0xffU
+#define V_COMMITLIMIT2H(x) ((x) << S_COMMITLIMIT2H)
+#define G_COMMITLIMIT2H(x) (((x) >> S_COMMITLIMIT2H) & M_COMMITLIMIT2H)
+
+#define S_COMMITLIMIT2L    0
+#define M_COMMITLIMIT2L    0xffU
+#define V_COMMITLIMIT2L(x) ((x) << S_COMMITLIMIT2L)
+#define G_COMMITLIMIT2L(x) (((x) >> S_COMMITLIMIT2L) & M_COMMITLIMIT2L)
+
+#define A_TP_CHANNEL_MAP_LPBK 0x2d
+
+#define S_T7_RXMAPCHANNELELN    12
+#define M_T7_RXMAPCHANNELELN    0xfU
+#define V_T7_RXMAPCHANNELELN(x) ((x) << S_T7_RXMAPCHANNELELN)
+#define G_T7_RXMAPCHANNELELN(x) (((x) >> S_T7_RXMAPCHANNELELN) & M_T7_RXMAPCHANNELELN)
+
+#define S_T7_RXMAPE2LCHANNEL3    9
+#define M_T7_RXMAPE2LCHANNEL3    0x7U
+#define V_T7_RXMAPE2LCHANNEL3(x) ((x) << S_T7_RXMAPE2LCHANNEL3)
+#define G_T7_RXMAPE2LCHANNEL3(x) (((x) >> S_T7_RXMAPE2LCHANNEL3) & M_T7_RXMAPE2LCHANNEL3)
+
+#define S_T7_RXMAPE2LCHANNEL2    6
+#define M_T7_RXMAPE2LCHANNEL2    0x7U
+#define V_T7_RXMAPE2LCHANNEL2(x) ((x) << S_T7_RXMAPE2LCHANNEL2)
+#define G_T7_RXMAPE2LCHANNEL2(x) (((x) >> S_T7_RXMAPE2LCHANNEL2) & M_T7_RXMAPE2LCHANNEL2)
+
+#define S_T7_RXMAPE2LCHANNEL1    3
+#define M_T7_RXMAPE2LCHANNEL1    0x7U
+#define V_T7_RXMAPE2LCHANNEL1(x) ((x) << S_T7_RXMAPE2LCHANNEL1)
+#define G_T7_RXMAPE2LCHANNEL1(x) (((x) >> S_T7_RXMAPE2LCHANNEL1) & M_T7_RXMAPE2LCHANNEL1)
+
+#define S_T7_RXMAPE2LCHANNEL0    0
+#define M_T7_RXMAPE2LCHANNEL0    0x7U
+#define V_T7_RXMAPE2LCHANNEL0(x) ((x) << S_T7_RXMAPE2LCHANNEL0)
+#define G_T7_RXMAPE2LCHANNEL0(x) (((x) >> S_T7_RXMAPE2LCHANNEL0) & M_T7_RXMAPE2LCHANNEL0)
+
 #define A_TP_IPMI_CFG1 0x2e
 
 #define S_VLANENABLE    31
@@ -24966,47 +31498,12 @@
 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
 
 #define A_TP_RSS_PF1_CONFIG 0x31
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF2_CONFIG 0x32
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF3_CONFIG 0x33
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF4_CONFIG 0x34
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF5_CONFIG 0x35
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF6_CONFIG 0x36
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF7_CONFIG 0x37
-
-#define S_T6_CHNENABLE    29
-#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
-#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
-
 #define A_TP_RSS_PF_MAP 0x38
 
 #define S_LKPIDXSIZE    24
@@ -25097,6 +31594,22 @@
 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
 
 #define A_TP_RSS_VFL_CONFIG 0x3a
+
+#define S_BASEQID    16
+#define M_BASEQID    0xfffU
+#define V_BASEQID(x) ((x) << S_BASEQID)
+#define G_BASEQID(x) (((x) >> S_BASEQID) & M_BASEQID)
+
+#define S_MAXRRQID    8
+#define M_MAXRRQID    0xffU
+#define V_MAXRRQID(x) ((x) << S_MAXRRQID)
+#define G_MAXRRQID(x) (((x) >> S_MAXRRQID) & M_MAXRRQID)
+
+#define S_RRCOUNTER    0
+#define M_RRCOUNTER    0xffU
+#define V_RRCOUNTER(x) ((x) << S_RRCOUNTER)
+#define G_RRCOUNTER(x) (((x) >> S_RRCOUNTER) & M_RRCOUNTER)
+
 #define A_TP_RSS_VFH_CONFIG 0x3b
 
 #define S_ENABLEUDPHASH    31
@@ -25150,6 +31663,10 @@
 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
 
+#define S_ROUNDROBINEN    3
+#define V_ROUNDROBINEN(x) ((x) << S_ROUNDROBINEN)
+#define F_ROUNDROBINEN    V_ROUNDROBINEN(1U)
+
 #define A_TP_RSS_SECRET_KEY0 0x40
 #define A_TP_RSS_SECRET_KEY1 0x41
 #define A_TP_RSS_SECRET_KEY2 0x42
@@ -25283,6 +31800,36 @@
 #define V_SHAREDXRC(x) ((x) << S_SHAREDXRC)
 #define F_SHAREDXRC    V_SHAREDXRC(1U)
 
+#define S_VERIFYRSPOP    25
+#define M_VERIFYRSPOP    0x1fU
+#define V_VERIFYRSPOP(x) ((x) << S_VERIFYRSPOP)
+#define G_VERIFYRSPOP(x) (((x) >> S_VERIFYRSPOP) & M_VERIFYRSPOP)
+
+#define S_VERIFYREQOP    20
+#define M_VERIFYREQOP    0x1fU
+#define V_VERIFYREQOP(x) ((x) << S_VERIFYREQOP)
+#define G_VERIFYREQOP(x) (((x) >> S_VERIFYREQOP) & M_VERIFYREQOP)
+
+#define S_AWRITERSPOP    15
+#define M_AWRITERSPOP    0x1fU
+#define V_AWRITERSPOP(x) ((x) << S_AWRITERSPOP)
+#define G_AWRITERSPOP(x) (((x) >> S_AWRITERSPOP) & M_AWRITERSPOP)
+
+#define S_AWRITEREQOP    10
+#define M_AWRITEREQOP    0x1fU
+#define V_AWRITEREQOP(x) ((x) << S_AWRITEREQOP)
+#define G_AWRITEREQOP(x) (((x) >> S_AWRITEREQOP) & M_AWRITEREQOP)
+
+#define S_FLUSHRSPOP    5
+#define M_FLUSHRSPOP    0x1fU
+#define V_FLUSHRSPOP(x) ((x) << S_FLUSHRSPOP)
+#define G_FLUSHRSPOP(x) (((x) >> S_FLUSHRSPOP) & M_FLUSHRSPOP)
+
+#define S_FLUSHREQOP    0
+#define M_FLUSHREQOP    0x1fU
+#define V_FLUSHREQOP(x) ((x) << S_FLUSHREQOP)
+#define G_FLUSHREQOP(x) (((x) >> S_FLUSHREQOP) & M_FLUSHREQOP)
+
 #define A_TP_FRAG_CONFIG 0x56
 
 #define S_TLSMODE    16
@@ -25330,6 +31877,21 @@
 #define V_PASSMODE(x) ((x) << S_PASSMODE)
 #define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE)
 
+#define S_NVMTMODE    22
+#define M_NVMTMODE    0x3U
+#define V_NVMTMODE(x) ((x) << S_NVMTMODE)
+#define G_NVMTMODE(x) (((x) >> S_NVMTMODE) & M_NVMTMODE)
+
+#define S_ROCEMODE    20
+#define M_ROCEMODE    0x3U
+#define V_ROCEMODE(x) ((x) << S_ROCEMODE)
+#define G_ROCEMODE(x) (((x) >> S_ROCEMODE) & M_ROCEMODE)
+
+#define S_DTLSMODE    18
+#define M_DTLSMODE    0x3U
+#define V_DTLSMODE(x) ((x) << S_DTLSMODE)
+#define G_DTLSMODE(x) (((x) >> S_DTLSMODE) & M_DTLSMODE)
+
 #define A_TP_CMM_CONFIG 0x57
 
 #define S_WRCNTIDLE    16
@@ -25383,6 +31945,7 @@
 #define V_GRETYPE(x) ((x) << S_GRETYPE)
 #define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE)
 
+#define A_TP_MMGR_CMM_CONFIG 0x5a
 #define A_TP_DBG_CLEAR 0x60
 #define A_TP_DBG_CORE_HDR0 0x61
 
@@ -25843,14 +32406,6 @@
 #define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY)
 #define F_T5_EPCMDBUSY    V_T5_EPCMDBUSY(1U)
 
-#define S_T6_ETXBUSY    1
-#define V_T6_ETXBUSY(x) ((x) << S_T6_ETXBUSY)
-#define F_T6_ETXBUSY    V_T6_ETXBUSY(1U)
-
-#define S_T6_EPCMDBUSY    0
-#define V_T6_EPCMDBUSY(x) ((x) << S_T6_EPCMDBUSY)
-#define F_T6_EPCMDBUSY    V_T6_EPCMDBUSY(1U)
-
 #define A_TP_DBG_ENG_RES1 0x67
 
 #define S_RXCPLSRDY    31
@@ -26114,16 +32669,6 @@
 #define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG)
 #define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG)
 
-#define S_T6_RXFIFOCNG    20
-#define M_T6_RXFIFOCNG    0xfU
-#define V_T6_RXFIFOCNG(x) ((x) << S_T6_RXFIFOCNG)
-#define G_T6_RXFIFOCNG(x) (((x) >> S_T6_RXFIFOCNG) & M_T6_RXFIFOCNG)
-
-#define S_T6_RXPCMDCNG    14
-#define M_T6_RXPCMDCNG    0x3U
-#define V_T6_RXPCMDCNG(x) ((x) << S_T6_RXPCMDCNG)
-#define G_T6_RXPCMDCNG(x) (((x) >> S_T6_RXPCMDCNG) & M_T6_RXPCMDCNG)
-
 #define A_TP_DBG_ERROR_CNT 0x6c
 #define A_TP_DBG_CORE_CPL 0x6d
 
@@ -26191,6 +32736,244 @@
 #define A_TP_DBG_CACHE_RD_HIT 0x73
 #define A_TP_DBG_CACHE_MC_REQ 0x74
 #define A_TP_DBG_CACHE_MC_RSP 0x75
+#define A_TP_RSS_PF0_CONFIG_CH3_CH2 0x80
+
+#define S_PFMAPALWAYS    22
+#define V_PFMAPALWAYS(x) ((x) << S_PFMAPALWAYS)
+#define F_PFMAPALWAYS    V_PFMAPALWAYS(1U)
+
+#define S_PFROUNDROBINEN    21
+#define V_PFROUNDROBINEN(x) ((x) << S_PFROUNDROBINEN)
+#define F_PFROUNDROBINEN    V_PFROUNDROBINEN(1U)
+
+#define S_FOURCHNEN    20
+#define V_FOURCHNEN(x) ((x) << S_FOURCHNEN)
+#define F_FOURCHNEN    V_FOURCHNEN(1U)
+
+#define S_CH3DEFAULTQUEUE    10
+#define M_CH3DEFAULTQUEUE    0x3ffU
+#define V_CH3DEFAULTQUEUE(x) ((x) << S_CH3DEFAULTQUEUE)
+#define G_CH3DEFAULTQUEUE(x) (((x) >> S_CH3DEFAULTQUEUE) & M_CH3DEFAULTQUEUE)
+
+#define S_CH2DEFAULTQUEUE    0
+#define M_CH2DEFAULTQUEUE    0x3ffU
+#define V_CH2DEFAULTQUEUE(x) ((x) << S_CH2DEFAULTQUEUE)
+#define G_CH2DEFAULTQUEUE(x) (((x) >> S_CH2DEFAULTQUEUE) & M_CH2DEFAULTQUEUE)
+
+#define A_TP_RSS_PF1_CONFIG_CH3_CH2 0x81
+#define A_TP_RSS_PF2_CONFIG_CH3_CH2 0x82
+#define A_TP_RSS_PF3_CONFIG_CH3_CH2 0x83
+#define A_TP_RSS_PF4_CONFIG_CH3_CH2 0x84
+#define A_TP_RSS_PF5_CONFIG_CH3_CH2 0x85
+#define A_TP_RSS_PF6_CONFIG_CH3_CH2 0x86
+#define A_TP_RSS_PF7_CONFIG_CH3_CH2 0x87
+#define A_TP_RSS_PF0_EXT_CONFIG 0x88
+#define A_TP_RSS_PF1_EXT_CONFIG 0x89
+#define A_TP_RSS_PF2_EXT_CONFIG 0x8a
+#define A_TP_RSS_PF3_EXT_CONFIG 0x8b
+#define A_TP_RSS_PF4_EXT_CONFIG 0x8c
+#define A_TP_RSS_PF5_EXT_CONFIG 0x8d
+#define A_TP_RSS_PF6_EXT_CONFIG 0x8e
+#define A_TP_RSS_PF7_EXT_CONFIG 0x8f
+#define A_TP_ROCE_CONFIG 0x90
+
+#define S_IGNAETHMSB    24
+#define V_IGNAETHMSB(x) ((x) << S_IGNAETHMSB)
+#define F_IGNAETHMSB    V_IGNAETHMSB(1U)
+
+#define S_XDIDMMCTL    23
+#define V_XDIDMMCTL(x) ((x) << S_XDIDMMCTL)
+#define F_XDIDMMCTL    V_XDIDMMCTL(1U)
+
+#define S_WRRETHDBGFWDEN    22
+#define V_WRRETHDBGFWDEN(x) ((x) << S_WRRETHDBGFWDEN)
+#define F_WRRETHDBGFWDEN    V_WRRETHDBGFWDEN(1U)
+
+#define S_ACKINTGENCTRL    20
+#define M_ACKINTGENCTRL    0x3U
+#define V_ACKINTGENCTRL(x) ((x) << S_ACKINTGENCTRL)
+#define G_ACKINTGENCTRL(x) (((x) >> S_ACKINTGENCTRL) & M_ACKINTGENCTRL)
+
+#define S_ATOMICALIGNCHKEN    19
+#define V_ATOMICALIGNCHKEN(x) ((x) << S_ATOMICALIGNCHKEN)
+#define F_ATOMICALIGNCHKEN    V_ATOMICALIGNCHKEN(1U)
+
+#define S_RDRETHLENCHKEN    18
+#define V_RDRETHLENCHKEN(x) ((x) << S_RDRETHLENCHKEN)
+#define F_RDRETHLENCHKEN    V_RDRETHLENCHKEN(1U)
+
+#define S_WRTOTALLENCHKEN    17
+#define V_WRTOTALLENCHKEN(x) ((x) << S_WRTOTALLENCHKEN)
+#define F_WRTOTALLENCHKEN    V_WRTOTALLENCHKEN(1U)
+
+#define S_WRRETHLENCHKEN    16
+#define V_WRRETHLENCHKEN(x) ((x) << S_WRRETHLENCHKEN)
+#define F_WRRETHLENCHKEN    V_WRRETHLENCHKEN(1U)
+
+#define S_TNLERRORUDPLEN    11
+#define V_TNLERRORUDPLEN(x) ((x) << S_TNLERRORUDPLEN)
+#define F_TNLERRORUDPLEN    V_TNLERRORUDPLEN(1U)
+
+#define S_TNLERRORPKEY    10
+#define V_TNLERRORPKEY(x) ((x) << S_TNLERRORPKEY)
+#define F_TNLERRORPKEY    V_TNLERRORPKEY(1U)
+
+#define S_TNLERROROPCODE    9
+#define V_TNLERROROPCODE(x) ((x) << S_TNLERROROPCODE)
+#define F_TNLERROROPCODE    V_TNLERROROPCODE(1U)
+
+#define S_TNLERRORTVER    8
+#define V_TNLERRORTVER(x) ((x) << S_TNLERRORTVER)
+#define F_TNLERRORTVER    V_TNLERRORTVER(1U)
+
+#define S_DROPERRORUDPLEN    3
+#define V_DROPERRORUDPLEN(x) ((x) << S_DROPERRORUDPLEN)
+#define F_DROPERRORUDPLEN    V_DROPERRORUDPLEN(1U)
+
+#define S_DROPERRORPKEY    2
+#define V_DROPERRORPKEY(x) ((x) << S_DROPERRORPKEY)
+#define F_DROPERRORPKEY    V_DROPERRORPKEY(1U)
+
+#define S_DROPERROROPCODE    1
+#define V_DROPERROROPCODE(x) ((x) << S_DROPERROROPCODE)
+#define F_DROPERROROPCODE    V_DROPERROROPCODE(1U)
+
+#define S_DROPERRORTVER    0
+#define V_DROPERRORTVER(x) ((x) << S_DROPERRORTVER)
+#define F_DROPERRORTVER    V_DROPERRORTVER(1U)
+
+#define A_TP_NVMT_CONFIG 0x91
+
+#define S_PDACHKEN    2
+#define V_PDACHKEN(x) ((x) << S_PDACHKEN)
+#define F_PDACHKEN    V_PDACHKEN(1U)
+
+#define S_FORCERQNONDDP    1
+#define V_FORCERQNONDDP(x) ((x) << S_FORCERQNONDDP)
+#define F_FORCERQNONDDP    V_FORCERQNONDDP(1U)
+
+#define S_STRIPHCRC    0
+#define V_STRIPHCRC(x) ((x) << S_STRIPHCRC)
+#define F_STRIPHCRC    V_STRIPHCRC(1U)
+
+#define A_TP_NVMT_MAXHDR 0x92
+
+#define S_MAXHDR3    24
+#define M_MAXHDR3    0xffU
+#define V_MAXHDR3(x) ((x) << S_MAXHDR3)
+#define G_MAXHDR3(x) (((x) >> S_MAXHDR3) & M_MAXHDR3)
+
+#define S_MAXHDR2    16
+#define M_MAXHDR2    0xffU
+#define V_MAXHDR2(x) ((x) << S_MAXHDR2)
+#define G_MAXHDR2(x) (((x) >> S_MAXHDR2) & M_MAXHDR2)
+
+#define S_MAXHDR1    8
+#define M_MAXHDR1    0xffU
+#define V_MAXHDR1(x) ((x) << S_MAXHDR1)
+#define G_MAXHDR1(x) (((x) >> S_MAXHDR1) & M_MAXHDR1)
+
+#define S_MAXHDR0    0
+#define M_MAXHDR0    0xffU
+#define V_MAXHDR0(x) ((x) << S_MAXHDR0)
+#define G_MAXHDR0(x) (((x) >> S_MAXHDR0) & M_MAXHDR0)
+
+#define A_TP_NVMT_PDORSVD 0x93
+
+#define S_PDORSVD3    24
+#define M_PDORSVD3    0xffU
+#define V_PDORSVD3(x) ((x) << S_PDORSVD3)
+#define G_PDORSVD3(x) (((x) >> S_PDORSVD3) & M_PDORSVD3)
+
+#define S_PDORSVD2    16
+#define M_PDORSVD2    0xffU
+#define V_PDORSVD2(x) ((x) << S_PDORSVD2)
+#define G_PDORSVD2(x) (((x) >> S_PDORSVD2) & M_PDORSVD2)
+
+#define S_PDORSVD1    8
+#define M_PDORSVD1    0xffU
+#define V_PDORSVD1(x) ((x) << S_PDORSVD1)
+#define G_PDORSVD1(x) (((x) >> S_PDORSVD1) & M_PDORSVD1)
+
+#define S_PDORSVD0    0
+#define M_PDORSVD0    0xffU
+#define V_PDORSVD0(x) ((x) << S_PDORSVD0)
+#define G_PDORSVD0(x) (((x) >> S_PDORSVD0) & M_PDORSVD0)
+
+#define A_TP_RDMA_CONFIG 0x94
+
+#define S_SRQLIMITEN    20
+#define V_SRQLIMITEN(x) ((x) << S_SRQLIMITEN)
+#define F_SRQLIMITEN    V_SRQLIMITEN(1U)
+
+#define S_SNDIMMSEOP    15
+#define M_SNDIMMSEOP    0x1fU
+#define V_SNDIMMSEOP(x) ((x) << S_SNDIMMSEOP)
+#define G_SNDIMMSEOP(x) (((x) >> S_SNDIMMSEOP) & M_SNDIMMSEOP)
+
+#define S_SNDIMMOP    10
+#define M_SNDIMMOP    0x1fU
+#define V_SNDIMMOP(x) ((x) << S_SNDIMMOP)
+#define G_SNDIMMOP(x) (((x) >> S_SNDIMMOP) & M_SNDIMMOP)
+
+#define S_IWARPXRCIDCHKEN    4
+#define V_IWARPXRCIDCHKEN(x) ((x) << S_IWARPXRCIDCHKEN)
+#define F_IWARPXRCIDCHKEN    V_IWARPXRCIDCHKEN(1U)
+
+#define S_IWARPEXTOPEN    3
+#define V_IWARPEXTOPEN(x) ((x) << S_IWARPEXTOPEN)
+#define F_IWARPEXTOPEN    V_IWARPEXTOPEN(1U)
+
+#define S_XRCIMPLTYPE    1
+#define V_XRCIMPLTYPE(x) ((x) << S_XRCIMPLTYPE)
+#define F_XRCIMPLTYPE    V_XRCIMPLTYPE(1U)
+
+#define S_XRCEN    0
+#define V_XRCEN(x) ((x) << S_XRCEN)
+#define F_XRCEN    V_XRCEN(1U)
+
+#define A_TP_ROCE_RRQ_BASE 0x95
+#define A_TP_FILTER_RATE_CFG 0x96
+
+#define S_GRP_CFG_RD    30
+#define V_GRP_CFG_RD(x) ((x) << S_GRP_CFG_RD)
+#define F_GRP_CFG_RD    V_GRP_CFG_RD(1U)
+
+#define S_GRP_CFG_INIT    29
+#define V_GRP_CFG_INIT(x) ((x) << S_GRP_CFG_INIT)
+#define F_GRP_CFG_INIT    V_GRP_CFG_INIT(1U)
+
+#define S_GRP_CFG_RST    28
+#define V_GRP_CFG_RST(x) ((x) << S_GRP_CFG_RST)
+#define F_GRP_CFG_RST    V_GRP_CFG_RST(1U)
+
+#define S_GRP_CFG_SEL    16
+#define M_GRP_CFG_SEL    0xfffU
+#define V_GRP_CFG_SEL(x) ((x) << S_GRP_CFG_SEL)
+#define G_GRP_CFG_SEL(x) (((x) >> S_GRP_CFG_SEL) & M_GRP_CFG_SEL)
+
+#define S_US_TIMER_TICK    0
+#define M_US_TIMER_TICK    0xffffU
+#define V_US_TIMER_TICK(x) ((x) << S_US_TIMER_TICK)
+#define G_US_TIMER_TICK(x) (((x) >> S_US_TIMER_TICK) & M_US_TIMER_TICK)
+
+#define A_TP_TLS_CONFIG 0x99
+
+#define S_QUIESCETYPE1    24
+#define M_QUIESCETYPE1    0xffU
+#define V_QUIESCETYPE1(x) ((x) << S_QUIESCETYPE1)
+#define G_QUIESCETYPE1(x) (((x) >> S_QUIESCETYPE1) & M_QUIESCETYPE1)
+
+#define S_QUIESCETYPE2    16
+#define M_QUIESCETYPE2    0xffU
+#define V_QUIESCETYPE2(x) ((x) << S_QUIESCETYPE2)
+#define G_QUIESCETYPE2(x) (((x) >> S_QUIESCETYPE2) & M_QUIESCETYPE2)
+
+#define S_QUIESCETYPE3    8
+#define M_QUIESCETYPE3    0xffU
+#define V_QUIESCETYPE3(x) ((x) << S_QUIESCETYPE3)
+#define G_QUIESCETYPE3(x) (((x) >> S_QUIESCETYPE3) & M_QUIESCETYPE3)
+
 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
 #define A_TP_TX_DROP_CNT_CH2 0x122
@@ -26682,10 +33465,6 @@
 
 #define A_TP_DBG_ESIDE_DISP1 0x137
 
-#define S_T6_ESTATIC4    12
-#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
-#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
-
 #define S_TXFULL_ESIDE1    0
 #define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1)
 #define F_TXFULL_ESIDE1    V_TXFULL_ESIDE1(1U)
@@ -26719,20 +33498,12 @@
 
 #define A_TP_DBG_ESIDE_DISP2 0x13a
 
-#define S_T6_ESTATIC4    12
-#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
-#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
-
 #define S_TXFULL_ESIDE2    0
 #define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2)
 #define F_TXFULL_ESIDE2    V_TXFULL_ESIDE2(1U)
 
 #define A_TP_DBG_ESIDE_DISP3 0x13b
 
-#define S_T6_ESTATIC4    12
-#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
-#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
-
 #define S_TXFULL_ESIDE3    0
 #define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3)
 #define F_TXFULL_ESIDE3    V_TXFULL_ESIDE3(1U)
@@ -26836,6 +33607,94 @@
 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
 #define F_SRVRSRAM    V_SRVRSRAM(1U)
 
+#define S_T7_FILTERMODE    31
+#define V_T7_FILTERMODE(x) ((x) << S_T7_FILTERMODE)
+#define F_T7_FILTERMODE    V_T7_FILTERMODE(1U)
+
+#define S_T7_FCOEMASK    30
+#define V_T7_FCOEMASK(x) ((x) << S_T7_FCOEMASK)
+#define F_T7_FCOEMASK    V_T7_FCOEMASK(1U)
+
+#define S_T7_SRVRSRAM    29
+#define V_T7_SRVRSRAM(x) ((x) << S_T7_SRVRSRAM)
+#define F_T7_SRVRSRAM    V_T7_SRVRSRAM(1U)
+
+#define S_ROCEUDFORCEIPV6    28
+#define V_ROCEUDFORCEIPV6(x) ((x) << S_ROCEUDFORCEIPV6)
+#define F_ROCEUDFORCEIPV6    V_ROCEUDFORCEIPV6(1U)
+
+#define S_TCPFLAGS8    27
+#define V_TCPFLAGS8(x) ((x) << S_TCPFLAGS8)
+#define F_TCPFLAGS8    V_TCPFLAGS8(1U)
+
+#define S_MACMATCH11    26
+#define V_MACMATCH11(x) ((x) << S_MACMATCH11)
+#define F_MACMATCH11    V_MACMATCH11(1U)
+
+#define S_SMACMATCH10    25
+#define V_SMACMATCH10(x) ((x) << S_SMACMATCH10)
+#define F_SMACMATCH10    V_SMACMATCH10(1U)
+
+#define S_SMACMATCH    14
+#define V_SMACMATCH(x) ((x) << S_SMACMATCH)
+#define F_SMACMATCH    V_SMACMATCH(1U)
+
+#define S_TCPFLAGS    13
+#define V_TCPFLAGS(x) ((x) << S_TCPFLAGS)
+#define F_TCPFLAGS    V_TCPFLAGS(1U)
+
+#define S_SYNONLY    12
+#define V_SYNONLY(x) ((x) << S_SYNONLY)
+#define F_SYNONLY    V_SYNONLY(1U)
+
+#define S_ROCE    11
+#define V_ROCE(x) ((x) << S_ROCE)
+#define F_ROCE    V_ROCE(1U)
+
+#define S_T7_FRAGMENTATION    10
+#define V_T7_FRAGMENTATION(x) ((x) << S_T7_FRAGMENTATION)
+#define F_T7_FRAGMENTATION    V_T7_FRAGMENTATION(1U)
+
+#define S_T7_MPSHITTYPE    9
+#define V_T7_MPSHITTYPE(x) ((x) << S_T7_MPSHITTYPE)
+#define F_T7_MPSHITTYPE    V_T7_MPSHITTYPE(1U)
+
+#define S_T7_MACMATCH    8
+#define V_T7_MACMATCH(x) ((x) << S_T7_MACMATCH)
+#define F_T7_MACMATCH    V_T7_MACMATCH(1U)
+
+#define S_T7_ETHERTYPE    7
+#define V_T7_ETHERTYPE(x) ((x) << S_T7_ETHERTYPE)
+#define F_T7_ETHERTYPE    V_T7_ETHERTYPE(1U)
+
+#define S_T7_PROTOCOL    6
+#define V_T7_PROTOCOL(x) ((x) << S_T7_PROTOCOL)
+#define F_T7_PROTOCOL    V_T7_PROTOCOL(1U)
+
+#define S_T7_TOS    5
+#define V_T7_TOS(x) ((x) << S_T7_TOS)
+#define F_T7_TOS    V_T7_TOS(1U)
+
+#define S_T7_VLAN    4
+#define V_T7_VLAN(x) ((x) << S_T7_VLAN)
+#define F_T7_VLAN    V_T7_VLAN(1U)
+
+#define S_T7_VNIC_ID    3
+#define V_T7_VNIC_ID(x) ((x) << S_T7_VNIC_ID)
+#define F_T7_VNIC_ID    V_T7_VNIC_ID(1U)
+
+#define S_T7_PORT    2
+#define V_T7_PORT(x) ((x) << S_T7_PORT)
+#define F_T7_PORT    V_T7_PORT(1U)
+
+#define S_T7_FCOE    1
+#define V_T7_FCOE(x) ((x) << S_T7_FCOE)
+#define F_T7_FCOE    V_T7_FCOE(1U)
+
+#define S_IPSECIDX    0
+#define V_IPSECIDX(x) ((x) << S_IPSECIDX)
+#define F_IPSECIDX    V_IPSECIDX(1U)
+
 #define A_TP_INGRESS_CONFIG 0x141
 
 #define S_OPAQUE_TYPE    16
@@ -26888,6 +33747,14 @@
 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
 #define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)
 
+#define S_USE_MPS_ECN    15
+#define V_USE_MPS_ECN(x) ((x) << S_USE_MPS_ECN)
+#define F_USE_MPS_ECN    V_USE_MPS_ECN(1U)
+
+#define S_USE_MPS_CONG    14
+#define V_USE_MPS_CONG(x) ((x) << S_USE_MPS_CONG)
+#define F_USE_MPS_CONG    V_USE_MPS_CONG(1U)
+
 #define A_TP_TX_DROP_CFG_CH2 0x142
 #define A_TP_TX_DROP_CFG_CH3 0x143
 #define A_TP_EGRESS_CONFIG 0x145
@@ -27490,6 +34357,51 @@
 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
 
+#define S_IPSECTUNETHTRANSEN    29
+#define V_IPSECTUNETHTRANSEN(x) ((x) << S_IPSECTUNETHTRANSEN)
+#define F_IPSECTUNETHTRANSEN    V_IPSECTUNETHTRANSEN(1U)
+
+#define S_ROCEV2ZEROUDP6CSUM    28
+#define V_ROCEV2ZEROUDP6CSUM(x) ((x) << S_ROCEV2ZEROUDP6CSUM)
+#define F_ROCEV2ZEROUDP6CSUM    V_ROCEV2ZEROUDP6CSUM(1U)
+
+#define S_ROCEV2PROCEN    27
+#define V_ROCEV2PROCEN(x) ((x) << S_ROCEV2PROCEN)
+#define F_ROCEV2PROCEN    V_ROCEV2PROCEN(1U)
+
+#define A_TP_ESIDE_ROCE_PORT12 0x161
+
+#define S_ROCEV2UDPPORT2    16
+#define M_ROCEV2UDPPORT2    0xffffU
+#define V_ROCEV2UDPPORT2(x) ((x) << S_ROCEV2UDPPORT2)
+#define G_ROCEV2UDPPORT2(x) (((x) >> S_ROCEV2UDPPORT2) & M_ROCEV2UDPPORT2)
+
+#define S_ROCEV2UDPPORT1    0
+#define M_ROCEV2UDPPORT1    0xffffU
+#define V_ROCEV2UDPPORT1(x) ((x) << S_ROCEV2UDPPORT1)
+#define G_ROCEV2UDPPORT1(x) (((x) >> S_ROCEV2UDPPORT1) & M_ROCEV2UDPPORT1)
+
+#define A_TP_ESIDE_ROCE_PORT34 0x162
+
+#define S_ROCEV2UDPPORT4    16
+#define M_ROCEV2UDPPORT4    0xffffU
+#define V_ROCEV2UDPPORT4(x) ((x) << S_ROCEV2UDPPORT4)
+#define G_ROCEV2UDPPORT4(x) (((x) >> S_ROCEV2UDPPORT4) & M_ROCEV2UDPPORT4)
+
+#define S_ROCEV2UDPPORT3    0
+#define M_ROCEV2UDPPORT3    0xffffU
+#define V_ROCEV2UDPPORT3(x) ((x) << S_ROCEV2UDPPORT3)
+#define G_ROCEV2UDPPORT3(x) (((x) >> S_ROCEV2UDPPORT3) & M_ROCEV2UDPPORT3)
+
+#define A_TP_ESIDE_CONFIG1 0x163
+
+#define S_ROCEV2CRCIGN    0
+#define M_ROCEV2CRCIGN    0xfU
+#define V_ROCEV2CRCIGN(x) ((x) << S_ROCEV2CRCIGN)
+#define G_ROCEV2CRCIGN(x) (((x) >> S_ROCEV2CRCIGN) & M_ROCEV2CRCIGN)
+
+#define A_TP_ESIDE_DEBUG_CFG 0x16c
+#define A_TP_ESIDE_DEBUG_DATA 0x16d
 #define A_TP_DBG_CSIDE_RX0 0x230
 
 #define S_CRXSOPCNT    28
@@ -27962,56 +34874,7 @@
 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
 #define F_TXFULL2X    V_TXFULL2X(1U)
 
-#define S_T6_TXFULL    31
-#define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
-#define F_T6_TXFULL    V_T6_TXFULL(1U)
-
-#define S_T6_PLD_RXZEROP_SRDY    25
-#define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
-#define F_T6_PLD_RXZEROP_SRDY    V_T6_PLD_RXZEROP_SRDY(1U)
-
-#define S_T6_DDP_SRDY    22
-#define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
-#define F_T6_DDP_SRDY    V_T6_DDP_SRDY(1U)
-
-#define S_T6_DDP_DRDY    21
-#define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
-#define F_T6_DDP_DRDY    V_T6_DDP_DRDY(1U)
-
 #define A_TP_DBG_CSIDE_DISP1 0x23b
-
-#define S_T5_TXFULL    31
-#define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
-#define F_T5_TXFULL    V_T5_TXFULL(1U)
-
-#define S_T5_PLD_RXZEROP_SRDY    25
-#define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
-#define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
-
-#define S_T5_DDP_SRDY    22
-#define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
-#define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
-
-#define S_T5_DDP_DRDY    21
-#define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
-#define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
-
-#define S_T6_TXFULL    31
-#define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
-#define F_T6_TXFULL    V_T6_TXFULL(1U)
-
-#define S_T6_PLD_RXZEROP_SRDY    25
-#define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
-#define F_T6_PLD_RXZEROP_SRDY    V_T6_PLD_RXZEROP_SRDY(1U)
-
-#define S_T6_DDP_SRDY    22
-#define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
-#define F_T6_DDP_SRDY    V_T6_DDP_SRDY(1U)
-
-#define S_T6_DDP_DRDY    21
-#define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
-#define F_T6_DDP_DRDY    V_T6_DDP_DRDY(1U)
-
 #define A_TP_DBG_CSIDE_DDP0 0x23c
 
 #define S_DDPMSGLATEST7    28
@@ -28222,6 +35085,59 @@
 #define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE)
 #define F_ISCSICMDMODE    V_ISCSICMDMODE(1U)
 
+#define S_NVMTOPUPDEN    30
+#define V_NVMTOPUPDEN(x) ((x) << S_NVMTOPUPDEN)
+#define F_NVMTOPUPDEN    V_NVMTOPUPDEN(1U)
+
+#define S_NOPDIS    29
+#define V_NOPDIS(x) ((x) << S_NOPDIS)
+#define F_NOPDIS    V_NOPDIS(1U)
+
+#define S_IWARPINVREQEN    27
+#define V_IWARPINVREQEN(x) ((x) << S_IWARPINVREQEN)
+#define F_IWARPINVREQEN    V_IWARPINVREQEN(1U)
+
+#define S_ROCEINVREQEN    26
+#define V_ROCEINVREQEN(x) ((x) << S_ROCEINVREQEN)
+#define F_ROCEINVREQEN    V_ROCEINVREQEN(1U)
+
+#define S_ROCESRQFWEN    25
+#define V_ROCESRQFWEN(x) ((x) << S_ROCESRQFWEN)
+#define F_ROCESRQFWEN    V_ROCESRQFWEN(1U)
+
+#define S_T7_WRITEZEROOP    20
+#define M_T7_WRITEZEROOP    0x1fU
+#define V_T7_WRITEZEROOP(x) ((x) << S_T7_WRITEZEROOP)
+#define G_T7_WRITEZEROOP(x) (((x) >> S_T7_WRITEZEROOP) & M_T7_WRITEZEROOP)
+
+#define S_IWARPEXTMODE    9
+#define V_IWARPEXTMODE(x) ((x) << S_IWARPEXTMODE)
+#define F_IWARPEXTMODE    V_IWARPEXTMODE(1U)
+
+#define S_IWARPINVFWEN    8
+#define V_IWARPINVFWEN(x) ((x) << S_IWARPINVFWEN)
+#define F_IWARPINVFWEN    V_IWARPINVFWEN(1U)
+
+#define S_IWARPSRQFWEN    7
+#define V_IWARPSRQFWEN(x) ((x) << S_IWARPSRQFWEN)
+#define F_IWARPSRQFWEN    V_IWARPSRQFWEN(1U)
+
+#define S_T7_STARTSKIPPLD    3
+#define V_T7_STARTSKIPPLD(x) ((x) << S_T7_STARTSKIPPLD)
+#define F_T7_STARTSKIPPLD    V_T7_STARTSKIPPLD(1U)
+
+#define S_NVMTFLIMMEN    2
+#define V_NVMTFLIMMEN(x) ((x) << S_NVMTFLIMMEN)
+#define F_NVMTFLIMMEN    V_NVMTFLIMMEN(1U)
+
+#define S_NVMTOPCTRLEN    1
+#define V_NVMTOPCTRLEN(x) ((x) << S_NVMTOPCTRLEN)
+#define F_NVMTOPCTRLEN    V_NVMTOPCTRLEN(1U)
+
+#define S_T7_WRITEZEROEN    0
+#define V_T7_WRITEZEROEN(x) ((x) << S_T7_WRITEZEROEN)
+#define F_T7_WRITEZEROEN    V_T7_WRITEZEROEN(1U)
+
 #define A_TP_CSPI_POWER 0x243
 
 #define S_GATECHNTX3    11
@@ -28256,6 +35172,26 @@
 #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
 #define F_SLEEPREQUTRN    V_SLEEPREQUTRN(1U)
 
+#define S_GATECHNRX3    7
+#define V_GATECHNRX3(x) ((x) << S_GATECHNRX3)
+#define F_GATECHNRX3    V_GATECHNRX3(1U)
+
+#define S_GATECHNRX2    6
+#define V_GATECHNRX2(x) ((x) << S_GATECHNRX2)
+#define F_GATECHNRX2    V_GATECHNRX2(1U)
+
+#define S_T7_GATECHNRX1    5
+#define V_T7_GATECHNRX1(x) ((x) << S_T7_GATECHNRX1)
+#define F_T7_GATECHNRX1    V_T7_GATECHNRX1(1U)
+
+#define S_T7_GATECHNRX0    4
+#define V_T7_GATECHNRX0(x) ((x) << S_T7_GATECHNRX0)
+#define F_T7_GATECHNRX0    V_T7_GATECHNRX0(1U)
+
+#define S_T7_SLEEPRDYUTRN    3
+#define V_T7_SLEEPRDYUTRN(x) ((x) << S_T7_SLEEPRDYUTRN)
+#define F_T7_SLEEPRDYUTRN    V_T7_SLEEPRDYUTRN(1U)
+
 #define A_TP_TRC_CONFIG 0x244
 
 #define S_TRCRR    1
@@ -28266,6 +35202,19 @@
 #define V_TRCCH(x) ((x) << S_TRCCH)
 #define F_TRCCH    V_TRCCH(1U)
 
+#define S_DEBUGPG    3
+#define V_DEBUGPG(x) ((x) << S_DEBUGPG)
+#define F_DEBUGPG    V_DEBUGPG(1U)
+
+#define S_T7_TRCRR    2
+#define V_T7_TRCRR(x) ((x) << S_T7_TRCRR)
+#define F_T7_TRCRR    V_T7_TRCRR(1U)
+
+#define S_T7_TRCCH    0
+#define M_T7_TRCCH    0x3U
+#define V_T7_TRCCH(x) ((x) << S_T7_TRCCH)
+#define G_T7_TRCCH(x) (((x) >> S_T7_TRCCH) & M_T7_TRCCH)
+
 #define A_TP_TAG_CONFIG 0x245
 
 #define S_ETAGTYPE    16
@@ -28379,26 +35328,6 @@
 #define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0)
 #define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0)
 
-#define S_T6_CPRSSTATE3    24
-#define M_T6_CPRSSTATE3    0xfU
-#define V_T6_CPRSSTATE3(x) ((x) << S_T6_CPRSSTATE3)
-#define G_T6_CPRSSTATE3(x) (((x) >> S_T6_CPRSSTATE3) & M_T6_CPRSSTATE3)
-
-#define S_T6_CPRSSTATE2    16
-#define M_T6_CPRSSTATE2    0xfU
-#define V_T6_CPRSSTATE2(x) ((x) << S_T6_CPRSSTATE2)
-#define G_T6_CPRSSTATE2(x) (((x) >> S_T6_CPRSSTATE2) & M_T6_CPRSSTATE2)
-
-#define S_T6_CPRSSTATE1    8
-#define M_T6_CPRSSTATE1    0xfU
-#define V_T6_CPRSSTATE1(x) ((x) << S_T6_CPRSSTATE1)
-#define G_T6_CPRSSTATE1(x) (((x) >> S_T6_CPRSSTATE1) & M_T6_CPRSSTATE1)
-
-#define S_T6_CPRSSTATE0    0
-#define M_T6_CPRSSTATE0    0xfU
-#define V_T6_CPRSSTATE0(x) ((x) << S_T6_CPRSSTATE0)
-#define G_T6_CPRSSTATE0(x) (((x) >> S_T6_CPRSSTATE0) & M_T6_CPRSSTATE0)
-
 #define A_TP_DBG_CSIDE_DEMUX 0x247
 
 #define S_CALLDONE    28
@@ -28630,6 +35559,62 @@
 #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
 #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
 #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
+#define A_TP_CHDR_CONFIG1 0x259
+
+#define S_CH3HIGH    24
+#define M_CH3HIGH    0xffU
+#define V_CH3HIGH(x) ((x) << S_CH3HIGH)
+#define G_CH3HIGH(x) (((x) >> S_CH3HIGH) & M_CH3HIGH)
+
+#define S_CH3LOW    16
+#define M_CH3LOW    0xffU
+#define V_CH3LOW(x) ((x) << S_CH3LOW)
+#define G_CH3LOW(x) (((x) >> S_CH3LOW) & M_CH3LOW)
+
+#define S_CH2HIGH    8
+#define M_CH2HIGH    0xffU
+#define V_CH2HIGH(x) ((x) << S_CH2HIGH)
+#define G_CH2HIGH(x) (((x) >> S_CH2HIGH) & M_CH2HIGH)
+
+#define S_CH2LOW    0
+#define M_CH2LOW    0xffU
+#define V_CH2LOW(x) ((x) << S_CH2LOW)
+#define G_CH2LOW(x) (((x) >> S_CH2LOW) & M_CH2LOW)
+
+#define A_TP_CDSP_RDMA_CONFIG 0x260
+#define A_TP_NVMT_OP_CTRL 0x268
+
+#define S_DEFOPCTRL    30
+#define M_DEFOPCTRL    0x3U
+#define V_DEFOPCTRL(x) ((x) << S_DEFOPCTRL)
+#define G_DEFOPCTRL(x) (((x) >> S_DEFOPCTRL) & M_DEFOPCTRL)
+
+#define S_NVMTOPCTRL    0
+#define M_NVMTOPCTRL    0x3fffffffU
+#define V_NVMTOPCTRL(x) ((x) << S_NVMTOPCTRL)
+#define G_NVMTOPCTRL(x) (((x) >> S_NVMTOPCTRL) & M_NVMTOPCTRL)
+
+#define A_TP_CSIDE_DEBUG_CFG 0x26c
+
+#define S_T7_OR_EN    13
+#define V_T7_OR_EN(x) ((x) << S_T7_OR_EN)
+#define F_T7_OR_EN    V_T7_OR_EN(1U)
+
+#define S_T7_HI    12
+#define V_T7_HI(x) ((x) << S_T7_HI)
+#define F_T7_HI    V_T7_HI(1U)
+
+#define S_T7_SELH    6
+#define M_T7_SELH    0x3fU
+#define V_T7_SELH(x) ((x) << S_T7_SELH)
+#define G_T7_SELH(x) (((x) >> S_T7_SELH) & M_T7_SELH)
+
+#define S_T7_SELL    0
+#define M_T7_SELL    0x3fU
+#define V_T7_SELL(x) ((x) << S_T7_SELL)
+#define G_T7_SELL(x) (((x) >> S_T7_SELL) & M_T7_SELL)
+
+#define A_TP_CSIDE_DEBUG_DATA 0x26d
 #define A_TP_FIFO_CONFIG 0x8c0
 
 #define S_CH1_OUTPUT    27
@@ -28771,6 +35756,174 @@
 #define A_TP_MIB_TNL_ERR_1 0x71
 #define A_TP_MIB_TNL_ERR_2 0x72
 #define A_TP_MIB_TNL_ERR_3 0x73
+#define A_TP_MIB_RDMA_IN_PKT_0 0x80
+#define A_TP_MIB_RDMA_IN_PKT_1 0x81
+#define A_TP_MIB_RDMA_IN_PKT_2 0x82
+#define A_TP_MIB_RDMA_IN_PKT_3 0x83
+#define A_TP_MIB_RDMA_IN_BYTE_HI_0 0x84
+#define A_TP_MIB_RDMA_IN_BYTE_LO_0 0x85
+#define A_TP_MIB_RDMA_IN_BYTE_HI_1 0x86
+#define A_TP_MIB_RDMA_IN_BYTE_LO_1 0x87
+#define A_TP_MIB_RDMA_IN_BYTE_HI_2 0x88
+#define A_TP_MIB_RDMA_IN_BYTE_LO_2 0x89
+#define A_TP_MIB_RDMA_IN_BYTE_HI_3 0x8a
+#define A_TP_MIB_RDMA_IN_BYTE_LO_3 0x8b
+#define A_TP_MIB_RDMA_OUT_PKT_0 0x90
+#define A_TP_MIB_RDMA_OUT_PKT_1 0x91
+#define A_TP_MIB_RDMA_OUT_PKT_2 0x92
+#define A_TP_MIB_RDMA_OUT_PKT_3 0x93
+#define A_TP_MIB_RDMA_OUT_BYTE_HI_0 0x94
+#define A_TP_MIB_RDMA_OUT_BYTE_LO_0 0x95
+#define A_TP_MIB_RDMA_OUT_BYTE_HI_1 0x96
+#define A_TP_MIB_RDMA_OUT_BYTE_LO_1 0x97
+#define A_TP_MIB_RDMA_OUT_BYTE_HI_2 0x98
+#define A_TP_MIB_RDMA_OUT_BYTE_LO_2 0x99
+#define A_TP_MIB_RDMA_OUT_BYTE_HI_3 0x9a
+#define A_TP_MIB_RDMA_OUT_BYTE_LO_3 0x9b
+#define A_TP_MIB_ISCSI_IN_PKT_0 0xa0
+#define A_TP_MIB_ISCSI_IN_PKT_1 0xa1
+#define A_TP_MIB_ISCSI_IN_PKT_2 0xa2
+#define A_TP_MIB_ISCSI_IN_PKT_3 0xa3
+#define A_TP_MIB_ISCSI_IN_BYTE_HI_0 0xa4
+#define A_TP_MIB_ISCSI_IN_BYTE_LO_0 0xa5
+#define A_TP_MIB_ISCSI_IN_BYTE_HI_1 0xa6
+#define A_TP_MIB_ISCSI_IN_BYTE_LO_1 0xa7
+#define A_TP_MIB_ISCSI_IN_BYTE_HI_2 0xa8
+#define A_TP_MIB_ISCSI_IN_BYTE_LO_2 0xa9
+#define A_TP_MIB_ISCSI_IN_BYTE_HI_3 0xaa
+#define A_TP_MIB_ISCSI_IN_BYTE_LO_3 0xab
+#define A_TP_MIB_ISCSI_OUT_PKT_0 0xb0
+#define A_TP_MIB_ISCSI_OUT_PKT_1 0xb1
+#define A_TP_MIB_ISCSI_OUT_PKT_2 0xb2
+#define A_TP_MIB_ISCSI_OUT_PKT_3 0xb3
+#define A_TP_MIB_ISCSI_OUT_BYTE_HI_0 0xb4
+#define A_TP_MIB_ISCSI_OUT_BYTE_LO_0 0xb5
+#define A_TP_MIB_ISCSI_OUT_BYTE_HI_1 0xb6
+#define A_TP_MIB_ISCSI_OUT_BYTE_LO_1 0xb7
+#define A_TP_MIB_ISCSI_OUT_BYTE_HI_2 0xb8
+#define A_TP_MIB_ISCSI_OUT_BYTE_LO_2 0xb9
+#define A_TP_MIB_ISCSI_OUT_BYTE_HI_3 0xba
+#define A_TP_MIB_ISCSI_OUT_BYTE_LO_3 0xbb
+#define A_TP_MIB_NVMT_IN_PKT_0 0xc0
+#define A_TP_MIB_NVMT_IN_PKT_1 0xc1
+#define A_TP_MIB_NVMT_IN_PKT_2 0xc2
+#define A_TP_MIB_NVMT_IN_PKT_3 0xc3
+#define A_TP_MIB_NVMT_IN_BYTE_HI_0 0xc4
+#define A_TP_MIB_NVMT_IN_BYTE_LO_0 0xc5
+#define A_TP_MIB_NVMT_IN_BYTE_HI_1 0xc6
+#define A_TP_MIB_NVMT_IN_BYTE_LO_1 0xc7
+#define A_TP_MIB_NVMT_IN_BYTE_HI_2 0xc8
+#define A_TP_MIB_NVMT_IN_BYTE_LO_2 0xc9
+#define A_TP_MIB_NVMT_IN_BYTE_HI_3 0xca
+#define A_TP_MIB_NVMT_IN_BYTE_LO_3 0xcb
+#define A_TP_MIB_NVMT_OUT_PKT_0 0xd0
+#define A_TP_MIB_NVMT_OUT_PKT_1 0xd1
+#define A_TP_MIB_NVMT_OUT_PKT_2 0xd2
+#define A_TP_MIB_NVMT_OUT_PKT_3 0xd3
+#define A_TP_MIB_NVMT_OUT_BYTE_HI_0 0xd4
+#define A_TP_MIB_NVMT_OUT_BYTE_LO_0 0xd5
+#define A_TP_MIB_NVMT_OUT_BYTE_HI_1 0xd6
+#define A_TP_MIB_NVMT_OUT_BYTE_LO_1 0xd7
+#define A_TP_MIB_NVMT_OUT_BYTE_HI_2 0xd8
+#define A_TP_MIB_NVMT_OUT_BYTE_LO_2 0xd9
+#define A_TP_MIB_NVMT_OUT_BYTE_HI_3 0xda
+#define A_TP_MIB_NVMT_OUT_BYTE_LO_3 0xdb
+#define A_TP_MIB_TLS_IN_PKT_0 0xe0
+#define A_TP_MIB_TLS_IN_PKT_1 0xe1
+#define A_TP_MIB_TLS_IN_PKT_2 0xe2
+#define A_TP_MIB_TLS_IN_PKT_3 0xe3
+#define A_TP_MIB_TLS_IN_BYTE_HI_0 0xe4
+#define A_TP_MIB_TLS_IN_BYTE_LO_0 0xe5
+#define A_TP_MIB_TLS_IN_BYTE_HI_1 0xe6
+#define A_TP_MIB_TLS_IN_BYTE_LO_1 0xe7
+#define A_TP_MIB_TLS_IN_BYTE_HI_2 0xe8
+#define A_TP_MIB_TLS_IN_BYTE_LO_2 0xe9
+#define A_TP_MIB_TLS_IN_BYTE_HI_3 0xea
+#define A_TP_MIB_TLS_IN_BYTE_LO_3 0xeb
+#define A_TP_MIB_TLS_OUT_PKT_0 0xf0
+#define A_TP_MIB_TLS_OUT_PKT_1 0xf1
+#define A_TP_MIB_TLS_OUT_PKT_2 0xf2
+#define A_TP_MIB_TLS_OUT_PKT_3 0xf3
+#define A_TP_MIB_TLS_OUT_BYTE_HI_0 0xf4
+#define A_TP_MIB_TLS_OUT_BYTE_LO_0 0xf5
+#define A_TP_MIB_TLS_OUT_BYTE_HI_1 0xf6
+#define A_TP_MIB_TLS_OUT_BYTE_LO_1 0xf7
+#define A_TP_MIB_TLS_OUT_BYTE_HI_2 0xf8
+#define A_TP_MIB_TLS_OUT_BYTE_LO_2 0xf9
+#define A_TP_MIB_TLS_OUT_BYTE_HI_3 0xfa
+#define A_TP_MIB_TLS_OUT_BYTE_LO_3 0xfb
+#define A_TP_MIB_ROCE_IN_PKT_0 0x100
+#define A_TP_MIB_ROCE_IN_PKT_1 0x101
+#define A_TP_MIB_ROCE_IN_PKT_2 0x102
+#define A_TP_MIB_ROCE_IN_PKT_3 0x103
+#define A_TP_MIB_ROCE_IN_BYTE_HI_0 0x104
+#define A_TP_MIB_ROCE_IN_BYTE_LO_0 0x105
+#define A_TP_MIB_ROCE_IN_BYTE_HI_1 0x106
+#define A_TP_MIB_ROCE_IN_BYTE_LO_1 0x107
+#define A_TP_MIB_ROCE_IN_BYTE_HI_2 0x108
+#define A_TP_MIB_ROCE_IN_BYTE_LO_2 0x109
+#define A_TP_MIB_ROCE_IN_BYTE_HI_3 0x10a
+#define A_TP_MIB_ROCE_IN_BYTE_LO_3 0x10b
+#define A_TP_MIB_ROCE_OUT_PKT_0 0x110
+#define A_TP_MIB_ROCE_OUT_PKT_1 0x111
+#define A_TP_MIB_ROCE_OUT_PKT_2 0x112
+#define A_TP_MIB_ROCE_OUT_PKT_3 0x113
+#define A_TP_MIB_ROCE_OUT_BYTE_HI_0 0x114
+#define A_TP_MIB_ROCE_OUT_BYTE_LO_0 0x115
+#define A_TP_MIB_ROCE_OUT_BYTE_HI_1 0x116
+#define A_TP_MIB_ROCE_OUT_BYTE_LO_1 0x117
+#define A_TP_MIB_ROCE_OUT_BYTE_HI_2 0x118
+#define A_TP_MIB_ROCE_OUT_BYTE_LO_2 0x119
+#define A_TP_MIB_ROCE_OUT_BYTE_HI_3 0x11a
+#define A_TP_MIB_ROCE_OUT_BYTE_LO_3 0x11b
+#define A_TP_MIB_IPSEC_TNL_IN_PKT_0 0x120
+#define A_TP_MIB_IPSEC_TNL_IN_PKT_1 0x121
+#define A_TP_MIB_IPSEC_TNL_IN_PKT_2 0x122
+#define A_TP_MIB_IPSEC_TNL_IN_PKT_3 0x123
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_0 0x124
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_0 0x125
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_1 0x126
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_1 0x127
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_2 0x128
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_2 0x129
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_3 0x12a
+#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_3 0x12b
+#define A_TP_MIB_IPSEC_TNL_OUT_PKT_0 0x130
+#define A_TP_MIB_IPSEC_TNL_OUT_PKT_1 0x131
+#define A_TP_MIB_IPSEC_TNL_OUT_PKT_2 0x132
+#define A_TP_MIB_IPSEC_TNL_OUT_PKT_3 0x133
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_0 0x134
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_0 0x135
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_1 0x136
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_1 0x137
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_2 0x138
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_2 0x139
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_3 0x13a
+#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_3 0x13b
+#define A_TP_MIB_IPSEC_OFD_IN_PKT_0 0x140
+#define A_TP_MIB_IPSEC_OFD_IN_PKT_1 0x141
+#define A_TP_MIB_IPSEC_OFD_IN_PKT_2 0x142
+#define A_TP_MIB_IPSEC_OFD_IN_PKT_3 0x143
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_0 0x144
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_0 0x145
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_1 0x146
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_1 0x147
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_2 0x148
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_2 0x149
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_3 0x14a
+#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_3 0x14b
+#define A_TP_MIB_IPSEC_OFD_OUT_PKT_0 0x150
+#define A_TP_MIB_IPSEC_OFD_OUT_PKT_1 0x151
+#define A_TP_MIB_IPSEC_OFD_OUT_PKT_2 0x152
+#define A_TP_MIB_IPSEC_OFD_OUT_PKT_3 0x153
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_0 0x154
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_0 0x155
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_1 0x156
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_1 0x157
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_2 0x158
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_2 0x159
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_3 0x15a
+#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_3 0x15b
 
 /* registers for module ULP_TX */
 #define ULP_TX_BASE_ADDR 0x8dc0
@@ -28853,7 +36006,58 @@
 #define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS)
 #define F_ATOMIC_FIX_DIS    V_ATOMIC_FIX_DIS(1U)
 
+#define S_LB_LEN_SEL    28
+#define V_LB_LEN_SEL(x) ((x) << S_LB_LEN_SEL)
+#define F_LB_LEN_SEL    V_LB_LEN_SEL(1U)
+
+#define S_DISABLE_TPT_CREDIT_CHK    27
+#define V_DISABLE_TPT_CREDIT_CHK(x) ((x) << S_DISABLE_TPT_CREDIT_CHK)
+#define F_DISABLE_TPT_CREDIT_CHK    V_DISABLE_TPT_CREDIT_CHK(1U)
+
+#define S_REQSRC    26
+#define V_REQSRC(x) ((x) << S_REQSRC)
+#define F_REQSRC    V_REQSRC(1U)
+
+#define S_ERR2UP    25
+#define V_ERR2UP(x) ((x) << S_ERR2UP)
+#define F_ERR2UP    V_ERR2UP(1U)
+
+#define S_SGE_INVALIDATE_DIS    24
+#define V_SGE_INVALIDATE_DIS(x) ((x) << S_SGE_INVALIDATE_DIS)
+#define F_SGE_INVALIDATE_DIS    V_SGE_INVALIDATE_DIS(1U)
+
+#define S_ROCE_ACKREQ_CTRL    23
+#define V_ROCE_ACKREQ_CTRL(x) ((x) << S_ROCE_ACKREQ_CTRL)
+#define F_ROCE_ACKREQ_CTRL    V_ROCE_ACKREQ_CTRL(1U)
+
+#define S_MEM_ADDR_CTRL    21
+#define M_MEM_ADDR_CTRL    0x3U
+#define V_MEM_ADDR_CTRL(x) ((x) << S_MEM_ADDR_CTRL)
+#define G_MEM_ADDR_CTRL(x) (((x) >> S_MEM_ADDR_CTRL) & M_MEM_ADDR_CTRL)
+
+#define S_TPT_EXTENSION_MODE    20
+#define V_TPT_EXTENSION_MODE(x) ((x) << S_TPT_EXTENSION_MODE)
+#define F_TPT_EXTENSION_MODE    V_TPT_EXTENSION_MODE(1U)
+
+#define S_XRC_INDICATION    19
+#define V_XRC_INDICATION(x) ((x) << S_XRC_INDICATION)
+#define F_XRC_INDICATION    V_XRC_INDICATION(1U)
+
+#define S_LSO_1SEG_LEN_UPD_EN    18
+#define V_LSO_1SEG_LEN_UPD_EN(x) ((x) << S_LSO_1SEG_LEN_UPD_EN)
+#define F_LSO_1SEG_LEN_UPD_EN    V_LSO_1SEG_LEN_UPD_EN(1U)
+
+#define S_PKT_ISGL_ERR_ST_EN    17
+#define V_PKT_ISGL_ERR_ST_EN(x) ((x) << S_PKT_ISGL_ERR_ST_EN)
+#define F_PKT_ISGL_ERR_ST_EN    V_PKT_ISGL_ERR_ST_EN(1U)
+
 #define A_ULP_TX_PERR_INJECT 0x8dc4
+
+#define S_T7_1_MEMSEL    1
+#define M_T7_1_MEMSEL    0x7fU
+#define V_T7_1_MEMSEL(x) ((x) << S_T7_1_MEMSEL)
+#define G_T7_1_MEMSEL(x) (((x) >> S_T7_1_MEMSEL) & M_T7_1_MEMSEL)
+
 #define A_ULP_TX_INT_ENABLE 0x8dc8
 
 #define S_PBL_BOUND_ERR_CH3    31
@@ -28984,8 +36188,28 @@
 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
 
+#define A_ULP_TX_INT_ENABLE_1 0x8dc8
+
+#define S_TLS_DSGL_PARERR3    3
+#define V_TLS_DSGL_PARERR3(x) ((x) << S_TLS_DSGL_PARERR3)
+#define F_TLS_DSGL_PARERR3    V_TLS_DSGL_PARERR3(1U)
+
+#define S_TLS_DSGL_PARERR2    2
+#define V_TLS_DSGL_PARERR2(x) ((x) << S_TLS_DSGL_PARERR2)
+#define F_TLS_DSGL_PARERR2    V_TLS_DSGL_PARERR2(1U)
+
+#define S_TLS_DSGL_PARERR1    1
+#define V_TLS_DSGL_PARERR1(x) ((x) << S_TLS_DSGL_PARERR1)
+#define F_TLS_DSGL_PARERR1    V_TLS_DSGL_PARERR1(1U)
+
+#define S_TLS_DSGL_PARERR0    0
+#define V_TLS_DSGL_PARERR0(x) ((x) << S_TLS_DSGL_PARERR0)
+#define F_TLS_DSGL_PARERR0    V_TLS_DSGL_PARERR0(1U)
+
 #define A_ULP_TX_INT_CAUSE 0x8dcc
+#define A_ULP_TX_INT_CAUSE_1 0x8dcc
 #define A_ULP_TX_PERR_ENABLE 0x8dd0
+#define A_ULP_TX_PERR_ENABLE_1 0x8dd0
 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
@@ -29014,6 +36238,13 @@
 #define F_TLSDISABLE    V_TLSDISABLE(1U)
 
 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
+#define A_ULP_TX_FID_1 0x8de8
+
+#define S_FID_1    0
+#define M_FID_1    0x7ffU
+#define V_FID_1(x) ((x) << S_FID_1)
+#define G_FID_1(x) (((x) >> S_FID_1) & M_FID_1)
+
 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
@@ -29166,6 +36397,15 @@
 #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
 #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
 
+#define S_T7_GLOBALENABLE    31
+#define V_T7_GLOBALENABLE(x) ((x) << S_T7_GLOBALENABLE)
+#define F_T7_GLOBALENABLE    V_T7_GLOBALENABLE(1U)
+
+#define S_RDREQ_SZ    3
+#define M_RDREQ_SZ    0x7U
+#define V_RDREQ_SZ(x) ((x) << S_RDREQ_SZ)
+#define G_RDREQ_SZ(x) (((x) >> S_RDREQ_SZ) & M_RDREQ_SZ)
+
 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
 #define A_ULP_TX_PERR_INJECT_2 0x8e34
 
@@ -29385,6 +36625,200 @@
 
 #define A_ULP_TX_INT_CAUSE_2 0x8e80
 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
+#define A_ULP_TX_INT_ENABLE_3 0x8e88
+
+#define S_GF_SGE_FIFO_PARERR3    31
+#define V_GF_SGE_FIFO_PARERR3(x) ((x) << S_GF_SGE_FIFO_PARERR3)
+#define F_GF_SGE_FIFO_PARERR3    V_GF_SGE_FIFO_PARERR3(1U)
+
+#define S_GF_SGE_FIFO_PARERR2    30
+#define V_GF_SGE_FIFO_PARERR2(x) ((x) << S_GF_SGE_FIFO_PARERR2)
+#define F_GF_SGE_FIFO_PARERR2    V_GF_SGE_FIFO_PARERR2(1U)
+
+#define S_GF_SGE_FIFO_PARERR1    29
+#define V_GF_SGE_FIFO_PARERR1(x) ((x) << S_GF_SGE_FIFO_PARERR1)
+#define F_GF_SGE_FIFO_PARERR1    V_GF_SGE_FIFO_PARERR1(1U)
+
+#define S_GF_SGE_FIFO_PARERR0    28
+#define V_GF_SGE_FIFO_PARERR0(x) ((x) << S_GF_SGE_FIFO_PARERR0)
+#define F_GF_SGE_FIFO_PARERR0    V_GF_SGE_FIFO_PARERR0(1U)
+
+#define S_DEDUPE_SGE_FIFO_PARERR3    27
+#define V_DEDUPE_SGE_FIFO_PARERR3(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR3)
+#define F_DEDUPE_SGE_FIFO_PARERR3    V_DEDUPE_SGE_FIFO_PARERR3(1U)
+
+#define S_DEDUPE_SGE_FIFO_PARERR2    26
+#define V_DEDUPE_SGE_FIFO_PARERR2(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR2)
+#define F_DEDUPE_SGE_FIFO_PARERR2    V_DEDUPE_SGE_FIFO_PARERR2(1U)
+
+#define S_DEDUPE_SGE_FIFO_PARERR1    25
+#define V_DEDUPE_SGE_FIFO_PARERR1(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR1)
+#define F_DEDUPE_SGE_FIFO_PARERR1    V_DEDUPE_SGE_FIFO_PARERR1(1U)
+
+#define S_DEDUPE_SGE_FIFO_PARERR0    24
+#define V_DEDUPE_SGE_FIFO_PARERR0(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR0)
+#define F_DEDUPE_SGE_FIFO_PARERR0    V_DEDUPE_SGE_FIFO_PARERR0(1U)
+
+#define S_GF3_DSGL_FIFO_PARERR    23
+#define V_GF3_DSGL_FIFO_PARERR(x) ((x) << S_GF3_DSGL_FIFO_PARERR)
+#define F_GF3_DSGL_FIFO_PARERR    V_GF3_DSGL_FIFO_PARERR(1U)
+
+#define S_GF2_DSGL_FIFO_PARERR    22
+#define V_GF2_DSGL_FIFO_PARERR(x) ((x) << S_GF2_DSGL_FIFO_PARERR)
+#define F_GF2_DSGL_FIFO_PARERR    V_GF2_DSGL_FIFO_PARERR(1U)
+
+#define S_GF1_DSGL_FIFO_PARERR    21
+#define V_GF1_DSGL_FIFO_PARERR(x) ((x) << S_GF1_DSGL_FIFO_PARERR)
+#define F_GF1_DSGL_FIFO_PARERR    V_GF1_DSGL_FIFO_PARERR(1U)
+
+#define S_GF0_DSGL_FIFO_PARERR    20
+#define V_GF0_DSGL_FIFO_PARERR(x) ((x) << S_GF0_DSGL_FIFO_PARERR)
+#define F_GF0_DSGL_FIFO_PARERR    V_GF0_DSGL_FIFO_PARERR(1U)
+
+#define S_DEDUPE3_DSGL_FIFO_PARERR    19
+#define V_DEDUPE3_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE3_DSGL_FIFO_PARERR)
+#define F_DEDUPE3_DSGL_FIFO_PARERR    V_DEDUPE3_DSGL_FIFO_PARERR(1U)
+
+#define S_DEDUPE2_DSGL_FIFO_PARERR    18
+#define V_DEDUPE2_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE2_DSGL_FIFO_PARERR)
+#define F_DEDUPE2_DSGL_FIFO_PARERR    V_DEDUPE2_DSGL_FIFO_PARERR(1U)
+
+#define S_DEDUPE1_DSGL_FIFO_PARERR    17
+#define V_DEDUPE1_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE1_DSGL_FIFO_PARERR)
+#define F_DEDUPE1_DSGL_FIFO_PARERR    V_DEDUPE1_DSGL_FIFO_PARERR(1U)
+
+#define S_DEDUPE0_DSGL_FIFO_PARERR    16
+#define V_DEDUPE0_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE0_DSGL_FIFO_PARERR)
+#define F_DEDUPE0_DSGL_FIFO_PARERR    V_DEDUPE0_DSGL_FIFO_PARERR(1U)
+
+#define S_XP10_SGE_FIFO_PARERR    15
+#define V_XP10_SGE_FIFO_PARERR(x) ((x) << S_XP10_SGE_FIFO_PARERR)
+#define F_XP10_SGE_FIFO_PARERR    V_XP10_SGE_FIFO_PARERR(1U)
+
+#define S_DSGL_PAR_ERR    14
+#define V_DSGL_PAR_ERR(x) ((x) << S_DSGL_PAR_ERR)
+#define F_DSGL_PAR_ERR    V_DSGL_PAR_ERR(1U)
+
+#define S_CDDIP_INT    13
+#define V_CDDIP_INT(x) ((x) << S_CDDIP_INT)
+#define F_CDDIP_INT    V_CDDIP_INT(1U)
+
+#define S_CCEIP_INT    12
+#define V_CCEIP_INT(x) ((x) << S_CCEIP_INT)
+#define F_CCEIP_INT    V_CCEIP_INT(1U)
+
+#define S_TLS_SGE_FIFO_PARERR3    11
+#define V_TLS_SGE_FIFO_PARERR3(x) ((x) << S_TLS_SGE_FIFO_PARERR3)
+#define F_TLS_SGE_FIFO_PARERR3    V_TLS_SGE_FIFO_PARERR3(1U)
+
+#define S_TLS_SGE_FIFO_PARERR2    10
+#define V_TLS_SGE_FIFO_PARERR2(x) ((x) << S_TLS_SGE_FIFO_PARERR2)
+#define F_TLS_SGE_FIFO_PARERR2    V_TLS_SGE_FIFO_PARERR2(1U)
+
+#define S_TLS_SGE_FIFO_PARERR1    9
+#define V_TLS_SGE_FIFO_PARERR1(x) ((x) << S_TLS_SGE_FIFO_PARERR1)
+#define F_TLS_SGE_FIFO_PARERR1    V_TLS_SGE_FIFO_PARERR1(1U)
+
+#define S_TLS_SGE_FIFO_PARERR0    8
+#define V_TLS_SGE_FIFO_PARERR0(x) ((x) << S_TLS_SGE_FIFO_PARERR0)
+#define F_TLS_SGE_FIFO_PARERR0    V_TLS_SGE_FIFO_PARERR0(1U)
+
+#define S_ULP2SMARBT_RSP_PERR    6
+#define V_ULP2SMARBT_RSP_PERR(x) ((x) << S_ULP2SMARBT_RSP_PERR)
+#define F_ULP2SMARBT_RSP_PERR    V_ULP2SMARBT_RSP_PERR(1U)
+
+#define S_ULPTX2MA_RSP_PERR    5
+#define V_ULPTX2MA_RSP_PERR(x) ((x) << S_ULPTX2MA_RSP_PERR)
+#define F_ULPTX2MA_RSP_PERR    V_ULPTX2MA_RSP_PERR(1U)
+
+#define S_PCIE2ULP_PERR3    4
+#define V_PCIE2ULP_PERR3(x) ((x) << S_PCIE2ULP_PERR3)
+#define F_PCIE2ULP_PERR3    V_PCIE2ULP_PERR3(1U)
+
+#define S_PCIE2ULP_PERR2    3
+#define V_PCIE2ULP_PERR2(x) ((x) << S_PCIE2ULP_PERR2)
+#define F_PCIE2ULP_PERR2    V_PCIE2ULP_PERR2(1U)
+
+#define S_PCIE2ULP_PERR1    2
+#define V_PCIE2ULP_PERR1(x) ((x) << S_PCIE2ULP_PERR1)
+#define F_PCIE2ULP_PERR1    V_PCIE2ULP_PERR1(1U)
+
+#define S_PCIE2ULP_PERR0    1
+#define V_PCIE2ULP_PERR0(x) ((x) << S_PCIE2ULP_PERR0)
+#define F_PCIE2ULP_PERR0    V_PCIE2ULP_PERR0(1U)
+
+#define S_CIM2ULP_PERR    0
+#define V_CIM2ULP_PERR(x) ((x) << S_CIM2ULP_PERR)
+#define F_CIM2ULP_PERR    V_CIM2ULP_PERR(1U)
+
+#define A_ULP_TX_INT_CAUSE_3 0x8e8c
+#define A_ULP_TX_PERR_ENABLE_3 0x8e90
+#define A_ULP_TX_INT_ENABLE_4 0x8e94
+
+#define S_DMA_PAR_ERR3    28
+#define M_DMA_PAR_ERR3    0xfU
+#define V_DMA_PAR_ERR3(x) ((x) << S_DMA_PAR_ERR3)
+#define G_DMA_PAR_ERR3(x) (((x) >> S_DMA_PAR_ERR3) & M_DMA_PAR_ERR3)
+
+#define S_DMA_PAR_ERR2    24
+#define M_DMA_PAR_ERR2    0xfU
+#define V_DMA_PAR_ERR2(x) ((x) << S_DMA_PAR_ERR2)
+#define G_DMA_PAR_ERR2(x) (((x) >> S_DMA_PAR_ERR2) & M_DMA_PAR_ERR2)
+
+#define S_DMA_PAR_ERR1    20
+#define M_DMA_PAR_ERR1    0xfU
+#define V_DMA_PAR_ERR1(x) ((x) << S_DMA_PAR_ERR1)
+#define G_DMA_PAR_ERR1(x) (((x) >> S_DMA_PAR_ERR1) & M_DMA_PAR_ERR1)
+
+#define S_DMA_PAR_ERR0    16
+#define M_DMA_PAR_ERR0    0xfU
+#define V_DMA_PAR_ERR0(x) ((x) << S_DMA_PAR_ERR0)
+#define G_DMA_PAR_ERR0(x) (((x) >> S_DMA_PAR_ERR0) & M_DMA_PAR_ERR0)
+
+#define S_CORE_CMD_FIFO_LB1    12
+#define M_CORE_CMD_FIFO_LB1    0xfU
+#define V_CORE_CMD_FIFO_LB1(x) ((x) << S_CORE_CMD_FIFO_LB1)
+#define G_CORE_CMD_FIFO_LB1(x) (((x) >> S_CORE_CMD_FIFO_LB1) & M_CORE_CMD_FIFO_LB1)
+
+#define S_CORE_CMD_FIFO_LB0    8
+#define M_CORE_CMD_FIFO_LB0    0xfU
+#define V_CORE_CMD_FIFO_LB0(x) ((x) << S_CORE_CMD_FIFO_LB0)
+#define G_CORE_CMD_FIFO_LB0(x) (((x) >> S_CORE_CMD_FIFO_LB0) & M_CORE_CMD_FIFO_LB0)
+
+#define S_XP10_2_ULP_PERR    7
+#define V_XP10_2_ULP_PERR(x) ((x) << S_XP10_2_ULP_PERR)
+#define F_XP10_2_ULP_PERR    V_XP10_2_ULP_PERR(1U)
+
+#define S_ULP_2_XP10_PERR    6
+#define V_ULP_2_XP10_PERR(x) ((x) << S_ULP_2_XP10_PERR)
+#define F_ULP_2_XP10_PERR    V_ULP_2_XP10_PERR(1U)
+
+#define S_CMD_FIFO_LB1    5
+#define V_CMD_FIFO_LB1(x) ((x) << S_CMD_FIFO_LB1)
+#define F_CMD_FIFO_LB1    V_CMD_FIFO_LB1(1U)
+
+#define S_CMD_FIFO_LB0    4
+#define V_CMD_FIFO_LB0(x) ((x) << S_CMD_FIFO_LB0)
+#define F_CMD_FIFO_LB0    V_CMD_FIFO_LB0(1U)
+
+#define S_TF_TP_PERR    3
+#define V_TF_TP_PERR(x) ((x) << S_TF_TP_PERR)
+#define F_TF_TP_PERR    V_TF_TP_PERR(1U)
+
+#define S_TF_SGE_PERR    2
+#define V_TF_SGE_PERR(x) ((x) << S_TF_SGE_PERR)
+#define F_TF_SGE_PERR    V_TF_SGE_PERR(1U)
+
+#define S_TF_MEM_PERR    1
+#define V_TF_MEM_PERR(x) ((x) << S_TF_MEM_PERR)
+#define F_TF_MEM_PERR    V_TF_MEM_PERR(1U)
+
+#define S_TF_MP_PERR    0
+#define V_TF_MP_PERR(x) ((x) << S_TF_MP_PERR)
+#define F_TF_MP_PERR    V_TF_MP_PERR(1U)
+
+#define A_ULP_TX_INT_CAUSE_4 0x8e98
+#define A_ULP_TX_PERR_ENABLE_4 0x8e9c
 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
 
 #define S_ERR_CH3    12
@@ -29531,16 +36965,381 @@
 
 #define A_ULP_TX_CSU_REVISION 0x8ebc
 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
+#define A_ULP_TX_PL2APB_INFO 0x8ec0
+
+#define S_PL2APB_BRIDGE_HUNG    27
+#define V_PL2APB_BRIDGE_HUNG(x) ((x) << S_PL2APB_BRIDGE_HUNG)
+#define F_PL2APB_BRIDGE_HUNG    V_PL2APB_BRIDGE_HUNG(1U)
+
+#define S_PL2APB_BRIDGE_STATE    26
+#define V_PL2APB_BRIDGE_STATE(x) ((x) << S_PL2APB_BRIDGE_STATE)
+#define F_PL2APB_BRIDGE_STATE    V_PL2APB_BRIDGE_STATE(1U)
+
+#define S_PL2APB_BRIDGE_HUNG_TYPE    25
+#define V_PL2APB_BRIDGE_HUNG_TYPE(x) ((x) << S_PL2APB_BRIDGE_HUNG_TYPE)
+#define F_PL2APB_BRIDGE_HUNG_TYPE    V_PL2APB_BRIDGE_HUNG_TYPE(1U)
+
+#define S_PL2APB_BRIDGE_HUNG_ID    24
+#define V_PL2APB_BRIDGE_HUNG_ID(x) ((x) << S_PL2APB_BRIDGE_HUNG_ID)
+#define F_PL2APB_BRIDGE_HUNG_ID    V_PL2APB_BRIDGE_HUNG_ID(1U)
+
+#define S_PL2APB_BRIDGE_HUNG_ADDR    0
+#define M_PL2APB_BRIDGE_HUNG_ADDR    0xfffffU
+#define V_PL2APB_BRIDGE_HUNG_ADDR(x) ((x) << S_PL2APB_BRIDGE_HUNG_ADDR)
+#define G_PL2APB_BRIDGE_HUNG_ADDR(x) (((x) >> S_PL2APB_BRIDGE_HUNG_ADDR) & M_PL2APB_BRIDGE_HUNG_ADDR)
+
 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
+#define A_ULP_TX_INT_ENABLE_5 0x8ec4
+
+#define S_DEDUPE_PERR3    23
+#define V_DEDUPE_PERR3(x) ((x) << S_DEDUPE_PERR3)
+#define F_DEDUPE_PERR3    V_DEDUPE_PERR3(1U)
+
+#define S_DEDUPE_PERR2    22
+#define V_DEDUPE_PERR2(x) ((x) << S_DEDUPE_PERR2)
+#define F_DEDUPE_PERR2    V_DEDUPE_PERR2(1U)
+
+#define S_DEDUPE_PERR1    21
+#define V_DEDUPE_PERR1(x) ((x) << S_DEDUPE_PERR1)
+#define F_DEDUPE_PERR1    V_DEDUPE_PERR1(1U)
+
+#define S_DEDUPE_PERR0    20
+#define V_DEDUPE_PERR0(x) ((x) << S_DEDUPE_PERR0)
+#define F_DEDUPE_PERR0    V_DEDUPE_PERR0(1U)
+
+#define S_GF_PERR3    19
+#define V_GF_PERR3(x) ((x) << S_GF_PERR3)
+#define F_GF_PERR3    V_GF_PERR3(1U)
+
+#define S_GF_PERR2    18
+#define V_GF_PERR2(x) ((x) << S_GF_PERR2)
+#define F_GF_PERR2    V_GF_PERR2(1U)
+
+#define S_GF_PERR1    17
+#define V_GF_PERR1(x) ((x) << S_GF_PERR1)
+#define F_GF_PERR1    V_GF_PERR1(1U)
+
+#define S_GF_PERR0    16
+#define V_GF_PERR0(x) ((x) << S_GF_PERR0)
+#define F_GF_PERR0    V_GF_PERR0(1U)
+
+#define S_SGE2ULP_INV_PERR    13
+#define V_SGE2ULP_INV_PERR(x) ((x) << S_SGE2ULP_INV_PERR)
+#define F_SGE2ULP_INV_PERR    V_SGE2ULP_INV_PERR(1U)
+
+#define S_T7_PL_BUSPERR    12
+#define V_T7_PL_BUSPERR(x) ((x) << S_T7_PL_BUSPERR)
+#define F_T7_PL_BUSPERR    V_T7_PL_BUSPERR(1U)
+
+#define S_TLSTX2ULPTX_PERR3    11
+#define V_TLSTX2ULPTX_PERR3(x) ((x) << S_TLSTX2ULPTX_PERR3)
+#define F_TLSTX2ULPTX_PERR3    V_TLSTX2ULPTX_PERR3(1U)
+
+#define S_TLSTX2ULPTX_PERR2    10
+#define V_TLSTX2ULPTX_PERR2(x) ((x) << S_TLSTX2ULPTX_PERR2)
+#define F_TLSTX2ULPTX_PERR2    V_TLSTX2ULPTX_PERR2(1U)
+
+#define S_TLSTX2ULPTX_PERR1    9
+#define V_TLSTX2ULPTX_PERR1(x) ((x) << S_TLSTX2ULPTX_PERR1)
+#define F_TLSTX2ULPTX_PERR1    V_TLSTX2ULPTX_PERR1(1U)
+
+#define S_TLSTX2ULPTX_PERR0    8
+#define V_TLSTX2ULPTX_PERR0(x) ((x) << S_TLSTX2ULPTX_PERR0)
+#define F_TLSTX2ULPTX_PERR0    V_TLSTX2ULPTX_PERR0(1U)
+
+#define S_XP10_2_ULP_PL_PERR    1
+#define V_XP10_2_ULP_PL_PERR(x) ((x) << S_XP10_2_ULP_PL_PERR)
+#define F_XP10_2_ULP_PL_PERR    V_XP10_2_ULP_PL_PERR(1U)
+
+#define S_ULP_2_XP10_PL_PERR    0
+#define V_ULP_2_XP10_PL_PERR(x) ((x) << S_ULP_2_XP10_PL_PERR)
+#define F_ULP_2_XP10_PL_PERR    V_ULP_2_XP10_PL_PERR(1U)
+
 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
+#define A_ULP_TX_INT_CAUSE_5 0x8ec8
 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
+#define A_ULP_TX_PERR_ENABLE_5 0x8ecc
 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
+#define A_ULP_TX_INT_CAUSE_6 0x8ed0
+
+#define S_DDR_HDR_FIFO_PERR_SET3    12
+#define V_DDR_HDR_FIFO_PERR_SET3(x) ((x) << S_DDR_HDR_FIFO_PERR_SET3)
+#define F_DDR_HDR_FIFO_PERR_SET3    V_DDR_HDR_FIFO_PERR_SET3(1U)
+
+#define S_DDR_HDR_FIFO_PERR_SET2    11
+#define V_DDR_HDR_FIFO_PERR_SET2(x) ((x) << S_DDR_HDR_FIFO_PERR_SET2)
+#define F_DDR_HDR_FIFO_PERR_SET2    V_DDR_HDR_FIFO_PERR_SET2(1U)
+
+#define S_DDR_HDR_FIFO_PERR_SET1    10
+#define V_DDR_HDR_FIFO_PERR_SET1(x) ((x) << S_DDR_HDR_FIFO_PERR_SET1)
+#define F_DDR_HDR_FIFO_PERR_SET1    V_DDR_HDR_FIFO_PERR_SET1(1U)
+
+#define S_DDR_HDR_FIFO_PERR_SET0    9
+#define V_DDR_HDR_FIFO_PERR_SET0(x) ((x) << S_DDR_HDR_FIFO_PERR_SET0)
+#define F_DDR_HDR_FIFO_PERR_SET0    V_DDR_HDR_FIFO_PERR_SET0(1U)
+
+#define S_PRE_MP_RSP_PERR_SET3    8
+#define V_PRE_MP_RSP_PERR_SET3(x) ((x) << S_PRE_MP_RSP_PERR_SET3)
+#define F_PRE_MP_RSP_PERR_SET3    V_PRE_MP_RSP_PERR_SET3(1U)
+
+#define S_PRE_MP_RSP_PERR_SET2    7
+#define V_PRE_MP_RSP_PERR_SET2(x) ((x) << S_PRE_MP_RSP_PERR_SET2)
+#define F_PRE_MP_RSP_PERR_SET2    V_PRE_MP_RSP_PERR_SET2(1U)
+
+#define S_PRE_MP_RSP_PERR_SET1    6
+#define V_PRE_MP_RSP_PERR_SET1(x) ((x) << S_PRE_MP_RSP_PERR_SET1)
+#define F_PRE_MP_RSP_PERR_SET1    V_PRE_MP_RSP_PERR_SET1(1U)
+
+#define S_PRE_MP_RSP_PERR_SET0    5
+#define V_PRE_MP_RSP_PERR_SET0(x) ((x) << S_PRE_MP_RSP_PERR_SET0)
+#define F_PRE_MP_RSP_PERR_SET0    V_PRE_MP_RSP_PERR_SET0(1U)
+
+#define S_PRE_CQE_FIFO_PERR_SET3    4
+#define V_PRE_CQE_FIFO_PERR_SET3(x) ((x) << S_PRE_CQE_FIFO_PERR_SET3)
+#define F_PRE_CQE_FIFO_PERR_SET3    V_PRE_CQE_FIFO_PERR_SET3(1U)
+
+#define S_PRE_CQE_FIFO_PERR_SET2    3
+#define V_PRE_CQE_FIFO_PERR_SET2(x) ((x) << S_PRE_CQE_FIFO_PERR_SET2)
+#define F_PRE_CQE_FIFO_PERR_SET2    V_PRE_CQE_FIFO_PERR_SET2(1U)
+
+#define S_PRE_CQE_FIFO_PERR_SET1    2
+#define V_PRE_CQE_FIFO_PERR_SET1(x) ((x) << S_PRE_CQE_FIFO_PERR_SET1)
+#define F_PRE_CQE_FIFO_PERR_SET1    V_PRE_CQE_FIFO_PERR_SET1(1U)
+
+#define S_PRE_CQE_FIFO_PERR_SET0    1
+#define V_PRE_CQE_FIFO_PERR_SET0(x) ((x) << S_PRE_CQE_FIFO_PERR_SET0)
+#define F_PRE_CQE_FIFO_PERR_SET0    V_PRE_CQE_FIFO_PERR_SET0(1U)
+
+#define S_RSP_FIFO_PERR_SET    0
+#define V_RSP_FIFO_PERR_SET(x) ((x) << S_RSP_FIFO_PERR_SET)
+#define F_RSP_FIFO_PERR_SET    V_RSP_FIFO_PERR_SET(1U)
+
 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
+#define A_ULP_TX_INT_ENABLE_6 0x8ed4
 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
+#define A_ULP_TX_PERR_ENABLE_6 0x8ed8
 #define A_ULP_TX_LA_RESERVED_1 0x8edc
+#define A_ULP_TX_INT_CAUSE_7 0x8edc
+
+#define S_TLS_SGE_FIFO_CORERR3    23
+#define V_TLS_SGE_FIFO_CORERR3(x) ((x) << S_TLS_SGE_FIFO_CORERR3)
+#define F_TLS_SGE_FIFO_CORERR3    V_TLS_SGE_FIFO_CORERR3(1U)
+
+#define S_TLS_SGE_FIFO_CORERR2    22
+#define V_TLS_SGE_FIFO_CORERR2(x) ((x) << S_TLS_SGE_FIFO_CORERR2)
+#define F_TLS_SGE_FIFO_CORERR2    V_TLS_SGE_FIFO_CORERR2(1U)
+
+#define S_TLS_SGE_FIFO_CORERR1    21
+#define V_TLS_SGE_FIFO_CORERR1(x) ((x) << S_TLS_SGE_FIFO_CORERR1)
+#define F_TLS_SGE_FIFO_CORERR1    V_TLS_SGE_FIFO_CORERR1(1U)
+
+#define S_TLS_SGE_FIFO_CORERR0    20
+#define V_TLS_SGE_FIFO_CORERR0(x) ((x) << S_TLS_SGE_FIFO_CORERR0)
+#define F_TLS_SGE_FIFO_CORERR0    V_TLS_SGE_FIFO_CORERR0(1U)
+
+#define S_LSO_HDR_SRAM_CERR_SET3    19
+#define V_LSO_HDR_SRAM_CERR_SET3(x) ((x) << S_LSO_HDR_SRAM_CERR_SET3)
+#define F_LSO_HDR_SRAM_CERR_SET3    V_LSO_HDR_SRAM_CERR_SET3(1U)
+
+#define S_LSO_HDR_SRAM_CERR_SET2    18
+#define V_LSO_HDR_SRAM_CERR_SET2(x) ((x) << S_LSO_HDR_SRAM_CERR_SET2)
+#define F_LSO_HDR_SRAM_CERR_SET2    V_LSO_HDR_SRAM_CERR_SET2(1U)
+
+#define S_LSO_HDR_SRAM_CERR_SET1    17
+#define V_LSO_HDR_SRAM_CERR_SET1(x) ((x) << S_LSO_HDR_SRAM_CERR_SET1)
+#define F_LSO_HDR_SRAM_CERR_SET1    V_LSO_HDR_SRAM_CERR_SET1(1U)
+
+#define S_LSO_HDR_SRAM_CERR_SET0    16
+#define V_LSO_HDR_SRAM_CERR_SET0(x) ((x) << S_LSO_HDR_SRAM_CERR_SET0)
+#define F_LSO_HDR_SRAM_CERR_SET0    V_LSO_HDR_SRAM_CERR_SET0(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH3_LB1    15
+#define V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB1)
+#define F_CORE_CMD_FIFO_CERR_SET_CH3_LB1    V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH2_LB1    14
+#define V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB1)
+#define F_CORE_CMD_FIFO_CERR_SET_CH2_LB1    V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH1_LB1    13
+#define V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB1)
+#define F_CORE_CMD_FIFO_CERR_SET_CH1_LB1    V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH0_LB1    12
+#define V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB1)
+#define F_CORE_CMD_FIFO_CERR_SET_CH0_LB1    V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH3_LB0    11
+#define V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB0)
+#define F_CORE_CMD_FIFO_CERR_SET_CH3_LB0    V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH2_LB0    10
+#define V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB0)
+#define F_CORE_CMD_FIFO_CERR_SET_CH2_LB0    V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH1_LB0    9
+#define V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB0)
+#define F_CORE_CMD_FIFO_CERR_SET_CH1_LB0    V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(1U)
+
+#define S_CORE_CMD_FIFO_CERR_SET_CH0_LB0    8
+#define V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB0)
+#define F_CORE_CMD_FIFO_CERR_SET_CH0_LB0    V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(1U)
+
+#define S_CQE_FIFO_CERR_SET3    7
+#define V_CQE_FIFO_CERR_SET3(x) ((x) << S_CQE_FIFO_CERR_SET3)
+#define F_CQE_FIFO_CERR_SET3    V_CQE_FIFO_CERR_SET3(1U)
+
+#define S_CQE_FIFO_CERR_SET2    6
+#define V_CQE_FIFO_CERR_SET2(x) ((x) << S_CQE_FIFO_CERR_SET2)
+#define F_CQE_FIFO_CERR_SET2    V_CQE_FIFO_CERR_SET2(1U)
+
+#define S_CQE_FIFO_CERR_SET1    5
+#define V_CQE_FIFO_CERR_SET1(x) ((x) << S_CQE_FIFO_CERR_SET1)
+#define F_CQE_FIFO_CERR_SET1    V_CQE_FIFO_CERR_SET1(1U)
+
+#define S_CQE_FIFO_CERR_SET0    4
+#define V_CQE_FIFO_CERR_SET0(x) ((x) << S_CQE_FIFO_CERR_SET0)
+#define F_CQE_FIFO_CERR_SET0    V_CQE_FIFO_CERR_SET0(1U)
+
+#define S_PRE_CQE_FIFO_CERR_SET3    3
+#define V_PRE_CQE_FIFO_CERR_SET3(x) ((x) << S_PRE_CQE_FIFO_CERR_SET3)
+#define F_PRE_CQE_FIFO_CERR_SET3    V_PRE_CQE_FIFO_CERR_SET3(1U)
+
+#define S_PRE_CQE_FIFO_CERR_SET2    2
+#define V_PRE_CQE_FIFO_CERR_SET2(x) ((x) << S_PRE_CQE_FIFO_CERR_SET2)
+#define F_PRE_CQE_FIFO_CERR_SET2    V_PRE_CQE_FIFO_CERR_SET2(1U)
+
+#define S_PRE_CQE_FIFO_CERR_SET1    1
+#define V_PRE_CQE_FIFO_CERR_SET1(x) ((x) << S_PRE_CQE_FIFO_CERR_SET1)
+#define F_PRE_CQE_FIFO_CERR_SET1    V_PRE_CQE_FIFO_CERR_SET1(1U)
+
+#define S_PRE_CQE_FIFO_CERR_SET0    0
+#define V_PRE_CQE_FIFO_CERR_SET0(x) ((x) << S_PRE_CQE_FIFO_CERR_SET0)
+#define F_PRE_CQE_FIFO_CERR_SET0    V_PRE_CQE_FIFO_CERR_SET0(1U)
+
 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
+#define A_ULP_TX_INT_ENABLE_7 0x8ee0
 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
+#define A_ULP_TX_INT_CAUSE_8 0x8ee4
+
+#define S_MEM_RSP_FIFO_CERR_SET3    28
+#define V_MEM_RSP_FIFO_CERR_SET3(x) ((x) << S_MEM_RSP_FIFO_CERR_SET3)
+#define F_MEM_RSP_FIFO_CERR_SET3    V_MEM_RSP_FIFO_CERR_SET3(1U)
+
+#define S_MEM_RSP_FIFO_CERR_SET2    27
+#define V_MEM_RSP_FIFO_CERR_SET2(x) ((x) << S_MEM_RSP_FIFO_CERR_SET2)
+#define F_MEM_RSP_FIFO_CERR_SET2    V_MEM_RSP_FIFO_CERR_SET2(1U)
+
+#define S_MEM_RSP_FIFO_CERR_SET1    26
+#define V_MEM_RSP_FIFO_CERR_SET1(x) ((x) << S_MEM_RSP_FIFO_CERR_SET1)
+#define F_MEM_RSP_FIFO_CERR_SET1    V_MEM_RSP_FIFO_CERR_SET1(1U)
+
+#define S_MEM_RSP_FIFO_CERR_SET0    25
+#define V_MEM_RSP_FIFO_CERR_SET0(x) ((x) << S_MEM_RSP_FIFO_CERR_SET0)
+#define F_MEM_RSP_FIFO_CERR_SET0    V_MEM_RSP_FIFO_CERR_SET0(1U)
+
+#define S_PI_SRAM_CERR_SET3    24
+#define V_PI_SRAM_CERR_SET3(x) ((x) << S_PI_SRAM_CERR_SET3)
+#define F_PI_SRAM_CERR_SET3    V_PI_SRAM_CERR_SET3(1U)
+
+#define S_PI_SRAM_CERR_SET2    23
+#define V_PI_SRAM_CERR_SET2(x) ((x) << S_PI_SRAM_CERR_SET2)
+#define F_PI_SRAM_CERR_SET2    V_PI_SRAM_CERR_SET2(1U)
+
+#define S_PI_SRAM_CERR_SET1    22
+#define V_PI_SRAM_CERR_SET1(x) ((x) << S_PI_SRAM_CERR_SET1)
+#define F_PI_SRAM_CERR_SET1    V_PI_SRAM_CERR_SET1(1U)
+
+#define S_PI_SRAM_CERR_SET0    21
+#define V_PI_SRAM_CERR_SET0(x) ((x) << S_PI_SRAM_CERR_SET0)
+#define F_PI_SRAM_CERR_SET0    V_PI_SRAM_CERR_SET0(1U)
+
+#define S_PRE_MP_RSP_CERR_SET3    20
+#define V_PRE_MP_RSP_CERR_SET3(x) ((x) << S_PRE_MP_RSP_CERR_SET3)
+#define F_PRE_MP_RSP_CERR_SET3    V_PRE_MP_RSP_CERR_SET3(1U)
+
+#define S_PRE_MP_RSP_CERR_SET2    19
+#define V_PRE_MP_RSP_CERR_SET2(x) ((x) << S_PRE_MP_RSP_CERR_SET2)
+#define F_PRE_MP_RSP_CERR_SET2    V_PRE_MP_RSP_CERR_SET2(1U)
+
+#define S_PRE_MP_RSP_CERR_SET1    18
+#define V_PRE_MP_RSP_CERR_SET1(x) ((x) << S_PRE_MP_RSP_CERR_SET1)
+#define F_PRE_MP_RSP_CERR_SET1    V_PRE_MP_RSP_CERR_SET1(1U)
+
+#define S_PRE_MP_RSP_CERR_SET0    17
+#define V_PRE_MP_RSP_CERR_SET0(x) ((x) << S_PRE_MP_RSP_CERR_SET0)
+#define F_PRE_MP_RSP_CERR_SET0    V_PRE_MP_RSP_CERR_SET0(1U)
+
+#define S_DDR_HDR_FIFO_CERR_SET3    16
+#define V_DDR_HDR_FIFO_CERR_SET3(x) ((x) << S_DDR_HDR_FIFO_CERR_SET3)
+#define F_DDR_HDR_FIFO_CERR_SET3    V_DDR_HDR_FIFO_CERR_SET3(1U)
+
+#define S_DDR_HDR_FIFO_CERR_SET2    15
+#define V_DDR_HDR_FIFO_CERR_SET2(x) ((x) << S_DDR_HDR_FIFO_CERR_SET2)
+#define F_DDR_HDR_FIFO_CERR_SET2    V_DDR_HDR_FIFO_CERR_SET2(1U)
+
+#define S_DDR_HDR_FIFO_CERR_SET1    14
+#define V_DDR_HDR_FIFO_CERR_SET1(x) ((x) << S_DDR_HDR_FIFO_CERR_SET1)
+#define F_DDR_HDR_FIFO_CERR_SET1    V_DDR_HDR_FIFO_CERR_SET1(1U)
+
+#define S_DDR_HDR_FIFO_CERR_SET0    13
+#define V_DDR_HDR_FIFO_CERR_SET0(x) ((x) << S_DDR_HDR_FIFO_CERR_SET0)
+#define F_DDR_HDR_FIFO_CERR_SET0    V_DDR_HDR_FIFO_CERR_SET0(1U)
+
+#define S_CMD_FIFO_CERR_SET3    12
+#define V_CMD_FIFO_CERR_SET3(x) ((x) << S_CMD_FIFO_CERR_SET3)
+#define F_CMD_FIFO_CERR_SET3    V_CMD_FIFO_CERR_SET3(1U)
+
+#define S_CMD_FIFO_CERR_SET2    11
+#define V_CMD_FIFO_CERR_SET2(x) ((x) << S_CMD_FIFO_CERR_SET2)
+#define F_CMD_FIFO_CERR_SET2    V_CMD_FIFO_CERR_SET2(1U)
+
+#define S_CMD_FIFO_CERR_SET1    10
+#define V_CMD_FIFO_CERR_SET1(x) ((x) << S_CMD_FIFO_CERR_SET1)
+#define F_CMD_FIFO_CERR_SET1    V_CMD_FIFO_CERR_SET1(1U)
+
+#define S_CMD_FIFO_CERR_SET0    9
+#define V_CMD_FIFO_CERR_SET0(x) ((x) << S_CMD_FIFO_CERR_SET0)
+#define F_CMD_FIFO_CERR_SET0    V_CMD_FIFO_CERR_SET0(1U)
+
+#define S_GF_SGE_FIFO_CORERR3    8
+#define V_GF_SGE_FIFO_CORERR3(x) ((x) << S_GF_SGE_FIFO_CORERR3)
+#define F_GF_SGE_FIFO_CORERR3    V_GF_SGE_FIFO_CORERR3(1U)
+
+#define S_GF_SGE_FIFO_CORERR2    7
+#define V_GF_SGE_FIFO_CORERR2(x) ((x) << S_GF_SGE_FIFO_CORERR2)
+#define F_GF_SGE_FIFO_CORERR2    V_GF_SGE_FIFO_CORERR2(1U)
+
+#define S_GF_SGE_FIFO_CORERR1    6
+#define V_GF_SGE_FIFO_CORERR1(x) ((x) << S_GF_SGE_FIFO_CORERR1)
+#define F_GF_SGE_FIFO_CORERR1    V_GF_SGE_FIFO_CORERR1(1U)
+
+#define S_GF_SGE_FIFO_CORERR0    5
+#define V_GF_SGE_FIFO_CORERR0(x) ((x) << S_GF_SGE_FIFO_CORERR0)
+#define F_GF_SGE_FIFO_CORERR0    V_GF_SGE_FIFO_CORERR0(1U)
+
+#define S_DEDUPE_SGE_FIFO_CORERR3    4
+#define V_DEDUPE_SGE_FIFO_CORERR3(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR3)
+#define F_DEDUPE_SGE_FIFO_CORERR3    V_DEDUPE_SGE_FIFO_CORERR3(1U)
+
+#define S_DEDUPE_SGE_FIFO_CORERR2    3
+#define V_DEDUPE_SGE_FIFO_CORERR2(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR2)
+#define F_DEDUPE_SGE_FIFO_CORERR2    V_DEDUPE_SGE_FIFO_CORERR2(1U)
+
+#define S_DEDUPE_SGE_FIFO_CORERR1    2
+#define V_DEDUPE_SGE_FIFO_CORERR1(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR1)
+#define F_DEDUPE_SGE_FIFO_CORERR1    V_DEDUPE_SGE_FIFO_CORERR1(1U)
+
+#define S_DEDUPE_SGE_FIFO_CORERR0    1
+#define V_DEDUPE_SGE_FIFO_CORERR0(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR0)
+#define F_DEDUPE_SGE_FIFO_CORERR0    V_DEDUPE_SGE_FIFO_CORERR0(1U)
+
+#define S_RSP_FIFO_CERR_SET    0
+#define V_RSP_FIFO_CERR_SET(x) ((x) << S_RSP_FIFO_CERR_SET)
+#define F_RSP_FIFO_CERR_SET    V_RSP_FIFO_CERR_SET(1U)
+
 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
+#define A_ULP_TX_INT_ENABLE_8 0x8ee8
 #define A_ULP_TX_LA_RESERVED_2 0x8eec
 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
@@ -29671,6 +37470,97 @@
 #define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST)
 #define F_SHOVE_LAST    V_SHOVE_LAST(1U)
 
+#define A_ULP_TX_ACCELERATOR_CTL 0x8f90
+
+#define S_FIFO_THRESHOLD    8
+#define M_FIFO_THRESHOLD    0x1fU
+#define V_FIFO_THRESHOLD(x) ((x) << S_FIFO_THRESHOLD)
+#define G_FIFO_THRESHOLD(x) (((x) >> S_FIFO_THRESHOLD) & M_FIFO_THRESHOLD)
+
+#define S_COMPRESSION_XP10DISABLECFUSE    5
+#define V_COMPRESSION_XP10DISABLECFUSE(x) ((x) << S_COMPRESSION_XP10DISABLECFUSE)
+#define F_COMPRESSION_XP10DISABLECFUSE    V_COMPRESSION_XP10DISABLECFUSE(1U)
+
+#define S_COMPRESSION_XP10DISABLE    4
+#define V_COMPRESSION_XP10DISABLE(x) ((x) << S_COMPRESSION_XP10DISABLE)
+#define F_COMPRESSION_XP10DISABLE    V_COMPRESSION_XP10DISABLE(1U)
+
+#define S_DEDUPEDISABLECFUSE    3
+#define V_DEDUPEDISABLECFUSE(x) ((x) << S_DEDUPEDISABLECFUSE)
+#define F_DEDUPEDISABLECFUSE    V_DEDUPEDISABLECFUSE(1U)
+
+#define S_DEDUPEDISABLE    2
+#define V_DEDUPEDISABLE(x) ((x) << S_DEDUPEDISABLE)
+#define F_DEDUPEDISABLE    V_DEDUPEDISABLE(1U)
+
+#define S_GFDISABLECFUSE    1
+#define V_GFDISABLECFUSE(x) ((x) << S_GFDISABLECFUSE)
+#define F_GFDISABLECFUSE    V_GFDISABLECFUSE(1U)
+
+#define S_GFDISABLE    0
+#define V_GFDISABLE(x) ((x) << S_GFDISABLE)
+#define F_GFDISABLE    V_GFDISABLE(1U)
+
+#define A_ULP_TX_XP10_IND_ADDR 0x8f94
+
+#define S_XP10_CONTROL    31
+#define V_XP10_CONTROL(x) ((x) << S_XP10_CONTROL)
+#define F_XP10_CONTROL    V_XP10_CONTROL(1U)
+
+#define S_XP10_ADDR    0
+#define M_XP10_ADDR    0xfffffU
+#define V_XP10_ADDR(x) ((x) << S_XP10_ADDR)
+#define G_XP10_ADDR(x) (((x) >> S_XP10_ADDR) & M_XP10_ADDR)
+
+#define A_ULP_TX_XP10_IND_DATA 0x8f98
+#define A_ULP_TX_IWARP_PMOF_OPCODES_1 0x8f9c
+
+#define S_RDMA_VERIFY_RESPONSE    24
+#define M_RDMA_VERIFY_RESPONSE    0x1fU
+#define V_RDMA_VERIFY_RESPONSE(x) ((x) << S_RDMA_VERIFY_RESPONSE)
+#define G_RDMA_VERIFY_RESPONSE(x) (((x) >> S_RDMA_VERIFY_RESPONSE) & M_RDMA_VERIFY_RESPONSE)
+
+#define S_RDMA_VERIFY_REQUEST    16
+#define M_RDMA_VERIFY_REQUEST    0x1fU
+#define V_RDMA_VERIFY_REQUEST(x) ((x) << S_RDMA_VERIFY_REQUEST)
+#define G_RDMA_VERIFY_REQUEST(x) (((x) >> S_RDMA_VERIFY_REQUEST) & M_RDMA_VERIFY_REQUEST)
+
+#define S_RDMA_FLUSH_RESPONSE    8
+#define M_RDMA_FLUSH_RESPONSE    0x1fU
+#define V_RDMA_FLUSH_RESPONSE(x) ((x) << S_RDMA_FLUSH_RESPONSE)
+#define G_RDMA_FLUSH_RESPONSE(x) (((x) >> S_RDMA_FLUSH_RESPONSE) & M_RDMA_FLUSH_RESPONSE)
+
+#define S_RDMA_FLUSH_REQUEST    0
+#define M_RDMA_FLUSH_REQUEST    0x1fU
+#define V_RDMA_FLUSH_REQUEST(x) ((x) << S_RDMA_FLUSH_REQUEST)
+#define G_RDMA_FLUSH_REQUEST(x) (((x) >> S_RDMA_FLUSH_REQUEST) & M_RDMA_FLUSH_REQUEST)
+
+#define A_ULP_TX_IWARP_PMOF_OPCODES_2 0x8fa0
+
+#define S_RDMA_SEND_WITH_SE_IMMEDIATE    24
+#define M_RDMA_SEND_WITH_SE_IMMEDIATE    0x1fU
+#define V_RDMA_SEND_WITH_SE_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_SE_IMMEDIATE)
+#define G_RDMA_SEND_WITH_SE_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_SE_IMMEDIATE) & M_RDMA_SEND_WITH_SE_IMMEDIATE)
+
+#define S_RDMA_SEND_WITH_IMMEDIATE    16
+#define M_RDMA_SEND_WITH_IMMEDIATE    0x1fU
+#define V_RDMA_SEND_WITH_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_IMMEDIATE)
+#define G_RDMA_SEND_WITH_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_IMMEDIATE) & M_RDMA_SEND_WITH_IMMEDIATE)
+
+#define S_RDMA_ATOMIC_WRITE_RESPONSE    8
+#define M_RDMA_ATOMIC_WRITE_RESPONSE    0x1fU
+#define V_RDMA_ATOMIC_WRITE_RESPONSE(x) ((x) << S_RDMA_ATOMIC_WRITE_RESPONSE)
+#define G_RDMA_ATOMIC_WRITE_RESPONSE(x) (((x) >> S_RDMA_ATOMIC_WRITE_RESPONSE) & M_RDMA_ATOMIC_WRITE_RESPONSE)
+
+#define S_RDMA_ATOMIC_WRITE_REQUEST    0
+#define M_RDMA_ATOMIC_WRITE_REQUEST    0x1fU
+#define V_RDMA_ATOMIC_WRITE_REQUEST(x) ((x) << S_RDMA_ATOMIC_WRITE_REQUEST)
+#define G_RDMA_ATOMIC_WRITE_REQUEST(x) (((x) >> S_RDMA_ATOMIC_WRITE_REQUEST) & M_RDMA_ATOMIC_WRITE_REQUEST)
+
+#define A_ULP_TX_NVME_TCP_TPT_LLIMIT 0x8fa4
+#define A_ULP_TX_NVME_TCP_TPT_ULIMIT 0x8fa8
+#define A_ULP_TX_NVME_TCP_PBL_LLIMIT 0x8fac
+#define A_ULP_TX_NVME_TCP_PBL_ULIMIT 0x8fb0
 #define A_ULP_TX_TLS_IND_CMD 0x8fb8
 
 #define S_TLS_TX_REG_OFF_ADDR    0
@@ -29678,7 +37568,48 @@
 #define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR)
 #define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR)
 
+#define A_ULP_TX_DBG_CTL 0x8fb8
 #define A_ULP_TX_TLS_IND_DATA 0x8fbc
+#define A_ULP_TX_DBG_DATA 0x8fbc
+#define A_ULP_TX_TLS_CH0_PERR_CAUSE 0xc
+
+#define S_GLUE_PERR    3
+#define V_GLUE_PERR(x) ((x) << S_GLUE_PERR)
+#define F_GLUE_PERR    V_GLUE_PERR(1U)
+
+#define S_DSGL_PERR    2
+#define V_DSGL_PERR(x) ((x) << S_DSGL_PERR)
+#define F_DSGL_PERR    V_DSGL_PERR(1U)
+
+#define S_SGE_PERR    1
+#define V_SGE_PERR(x) ((x) << S_SGE_PERR)
+#define F_SGE_PERR    V_SGE_PERR(1U)
+
+#define S_KEX_PERR    0
+#define V_KEX_PERR(x) ((x) << S_KEX_PERR)
+#define F_KEX_PERR    V_KEX_PERR(1U)
+
+#define A_ULP_TX_TLS_CH0_PERR_ENABLE 0x10
+#define A_ULP_TX_TLS_CH0_HMACCTRL_CFG 0x20
+
+#define S_HMAC_CFG6    12
+#define M_HMAC_CFG6    0x3fU
+#define V_HMAC_CFG6(x) ((x) << S_HMAC_CFG6)
+#define G_HMAC_CFG6(x) (((x) >> S_HMAC_CFG6) & M_HMAC_CFG6)
+
+#define S_HMAC_CFG5    6
+#define M_HMAC_CFG5    0x3fU
+#define V_HMAC_CFG5(x) ((x) << S_HMAC_CFG5)
+#define G_HMAC_CFG5(x) (((x) >> S_HMAC_CFG5) & M_HMAC_CFG5)
+
+#define S_HMAC_CFG4    0
+#define M_HMAC_CFG4    0x3fU
+#define V_HMAC_CFG4(x) ((x) << S_HMAC_CFG4)
+#define G_HMAC_CFG4(x) (((x) >> S_HMAC_CFG4) & M_HMAC_CFG4)
+
+#define A_ULP_TX_TLS_CH1_PERR_CAUSE 0x4c
+#define A_ULP_TX_TLS_CH1_PERR_ENABLE 0x50
+#define A_ULP_TX_TLS_CH1_HMACCTRL_CFG 0x60
 
 /* registers for module PM_RX */
 #define PM_RX_BASE_ADDR 0x8fc0
@@ -29703,6 +37634,31 @@
 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
 #define F_PREFETCH_ENABLE    V_PREFETCH_ENABLE(1U)
 
+#define S_CACHE_HOLD    13
+#define V_CACHE_HOLD(x) ((x) << S_CACHE_HOLD)
+#define F_CACHE_HOLD    V_CACHE_HOLD(1U)
+
+#define S_CACHE_INIT_DONE    12
+#define V_CACHE_INIT_DONE(x) ((x) << S_CACHE_INIT_DONE)
+#define F_CACHE_INIT_DONE    V_CACHE_INIT_DONE(1U)
+
+#define S_CACHE_DEPTH    8
+#define M_CACHE_DEPTH    0xfU
+#define V_CACHE_DEPTH(x) ((x) << S_CACHE_DEPTH)
+#define G_CACHE_DEPTH(x) (((x) >> S_CACHE_DEPTH) & M_CACHE_DEPTH)
+
+#define S_CACHE_INIT    7
+#define V_CACHE_INIT(x) ((x) << S_CACHE_INIT)
+#define F_CACHE_INIT    V_CACHE_INIT(1U)
+
+#define S_CACHE_SLEEP    6
+#define V_CACHE_SLEEP(x) ((x) << S_CACHE_SLEEP)
+#define F_CACHE_SLEEP    V_CACHE_SLEEP(1U)
+
+#define S_CACHE_BYPASS    5
+#define V_CACHE_BYPASS(x) ((x) << S_CACHE_BYPASS)
+#define F_CACHE_BYPASS    V_CACHE_BYPASS(1U)
+
 #define A_PM_RX_STAT_CONFIG 0x8fc8
 #define A_PM_RX_STAT_COUNT 0x8fcc
 #define A_PM_RX_STAT_LSB 0x8fd0
@@ -29723,6 +37679,11 @@
 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
 
+#define S_T7_OSPIWRBUSY_T5    21
+#define M_T7_OSPIWRBUSY_T5    0xfU
+#define V_T7_OSPIWRBUSY_T5(x) ((x) << S_T7_OSPIWRBUSY_T5)
+#define G_T7_OSPIWRBUSY_T5(x) (((x) >> S_T7_OSPIWRBUSY_T5) & M_T7_OSPIWRBUSY_T5)
+
 #define A_PM_RX_STAT_MSB 0x8fd4
 #define A_PM_RX_DBG_DATA 0x8fd4
 #define A_PM_RX_INT_ENABLE 0x8fd8
@@ -29843,7 +37804,36 @@
 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
 #define F_SDC_ERR    V_SDC_ERR(1U)
 
+#define S_MASTER_PERR    31
+#define V_MASTER_PERR(x) ((x) << S_MASTER_PERR)
+#define F_MASTER_PERR    V_MASTER_PERR(1U)
+
+#define S_T7_OSPI_OVERFLOW3    30
+#define V_T7_OSPI_OVERFLOW3(x) ((x) << S_T7_OSPI_OVERFLOW3)
+#define F_T7_OSPI_OVERFLOW3    V_T7_OSPI_OVERFLOW3(1U)
+
+#define S_T7_OSPI_OVERFLOW2    29
+#define V_T7_OSPI_OVERFLOW2(x) ((x) << S_T7_OSPI_OVERFLOW2)
+#define F_T7_OSPI_OVERFLOW2    V_T7_OSPI_OVERFLOW2(1U)
+
 #define A_PM_RX_INT_CAUSE 0x8fdc
+
+#define S_CACHE_SRAM_ERROR    3
+#define V_CACHE_SRAM_ERROR(x) ((x) << S_CACHE_SRAM_ERROR)
+#define F_CACHE_SRAM_ERROR    V_CACHE_SRAM_ERROR(1U)
+
+#define S_CACHE_LRU_ERROR    2
+#define V_CACHE_LRU_ERROR(x) ((x) << S_CACHE_LRU_ERROR)
+#define F_CACHE_LRU_ERROR    V_CACHE_LRU_ERROR(1U)
+
+#define S_CACHE_ISLAND_ERROR    1
+#define V_CACHE_ISLAND_ERROR(x) ((x) << S_CACHE_ISLAND_ERROR)
+#define F_CACHE_ISLAND_ERROR    V_CACHE_ISLAND_ERROR(1U)
+
+#define S_CACHE_CTRL_ERROR    0
+#define V_CACHE_CTRL_ERROR(x) ((x) << S_CACHE_CTRL_ERROR)
+#define F_CACHE_CTRL_ERROR    V_CACHE_CTRL_ERROR(1U)
+
 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
@@ -29959,12 +37949,25 @@
 #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
 #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
 
+#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT0 0x1001c
 #define A_PM_RX_FEATURE_EN 0x1001d
 
 #define S_PIO_CH_DEFICIT_CTL_EN_RX    0
 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
 #define F_PIO_CH_DEFICIT_CTL_EN_RX    V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
 
+#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT1 0x1001d
+
+#define S_CHNL3_MAX_DEFICIT_CNT    16
+#define M_CHNL3_MAX_DEFICIT_CNT    0xffffU
+#define V_CHNL3_MAX_DEFICIT_CNT(x) ((x) << S_CHNL3_MAX_DEFICIT_CNT)
+#define G_CHNL3_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL3_MAX_DEFICIT_CNT) & M_CHNL3_MAX_DEFICIT_CNT)
+
+#define S_CHNL2_MAX_DEFICIT_CNT    0
+#define M_CHNL2_MAX_DEFICIT_CNT    0xffffU
+#define V_CHNL2_MAX_DEFICIT_CNT(x) ((x) << S_CHNL2_MAX_DEFICIT_CNT)
+#define G_CHNL2_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL2_MAX_DEFICIT_CNT) & M_CHNL2_MAX_DEFICIT_CNT)
+
 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
 
 #define S_CH0_OSPI_DEFICIT_THRSHLD    0
@@ -30245,16 +38248,6 @@
 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
 
-#define S_T6_RX_PCMD_DRDY    26
-#define M_T6_RX_PCMD_DRDY    0x3U
-#define V_T6_RX_PCMD_DRDY(x) ((x) << S_T6_RX_PCMD_DRDY)
-#define G_T6_RX_PCMD_DRDY(x) (((x) >> S_T6_RX_PCMD_DRDY) & M_T6_RX_PCMD_DRDY)
-
-#define S_T6_RX_PCMD_SRDY    24
-#define M_T6_RX_PCMD_SRDY    0x3U
-#define V_T6_RX_PCMD_SRDY(x) ((x) << S_T6_RX_PCMD_SRDY)
-#define G_T6_RX_PCMD_SRDY(x) (((x) >> S_T6_RX_PCMD_SRDY) & M_T6_RX_PCMD_SRDY)
-
 #define A_PM_RX_DBG_STAT6 0x10027
 
 #define S_RX_M_INTRNL_FIFO_CNT    4
@@ -30434,6 +38427,179 @@
 #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
 #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
 
+#define A_PM_RX_INT_CAUSE_MASK_HALT_2 0x10049
+#define A_PM_RX_INT_ENABLE_2 0x10060
+
+#define S_CACHE_SRAM_ODD_CERR    12
+#define V_CACHE_SRAM_ODD_CERR(x) ((x) << S_CACHE_SRAM_ODD_CERR)
+#define F_CACHE_SRAM_ODD_CERR    V_CACHE_SRAM_ODD_CERR(1U)
+
+#define S_CACHE_SRAM_EVEN_CERR    11
+#define V_CACHE_SRAM_EVEN_CERR(x) ((x) << S_CACHE_SRAM_EVEN_CERR)
+#define F_CACHE_SRAM_EVEN_CERR    V_CACHE_SRAM_EVEN_CERR(1U)
+
+#define S_CACHE_LRU_LEFT_CERR    10
+#define V_CACHE_LRU_LEFT_CERR(x) ((x) << S_CACHE_LRU_LEFT_CERR)
+#define F_CACHE_LRU_LEFT_CERR    V_CACHE_LRU_LEFT_CERR(1U)
+
+#define S_CACHE_LRU_RIGHT_CERR    9
+#define V_CACHE_LRU_RIGHT_CERR(x) ((x) << S_CACHE_LRU_RIGHT_CERR)
+#define F_CACHE_LRU_RIGHT_CERR    V_CACHE_LRU_RIGHT_CERR(1U)
+
+#define S_CACHE_ISLAND_CERR    8
+#define V_CACHE_ISLAND_CERR(x) ((x) << S_CACHE_ISLAND_CERR)
+#define F_CACHE_ISLAND_CERR    V_CACHE_ISLAND_CERR(1U)
+
+#define S_OCSPI_CERR    7
+#define V_OCSPI_CERR(x) ((x) << S_OCSPI_CERR)
+#define F_OCSPI_CERR    V_OCSPI_CERR(1U)
+
+#define S_IESPI_CERR    6
+#define V_IESPI_CERR(x) ((x) << S_IESPI_CERR)
+#define F_IESPI_CERR    V_IESPI_CERR(1U)
+
+#define S_OCSPI2_RX_FRAMING_ERROR    5
+#define V_OCSPI2_RX_FRAMING_ERROR(x) ((x) << S_OCSPI2_RX_FRAMING_ERROR)
+#define F_OCSPI2_RX_FRAMING_ERROR    V_OCSPI2_RX_FRAMING_ERROR(1U)
+
+#define S_OCSPI3_RX_FRAMING_ERROR    4
+#define V_OCSPI3_RX_FRAMING_ERROR(x) ((x) << S_OCSPI3_RX_FRAMING_ERROR)
+#define F_OCSPI3_RX_FRAMING_ERROR    V_OCSPI3_RX_FRAMING_ERROR(1U)
+
+#define S_OCSPI2_TX_FRAMING_ERROR    3
+#define V_OCSPI2_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_TX_FRAMING_ERROR)
+#define F_OCSPI2_TX_FRAMING_ERROR    V_OCSPI2_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI3_TX_FRAMING_ERROR    2
+#define V_OCSPI3_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_TX_FRAMING_ERROR)
+#define F_OCSPI3_TX_FRAMING_ERROR    V_OCSPI3_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR    1
+#define V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OCSPI2_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR    0
+#define V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OCSPI3_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define A_PM_RX_INT_CAUSE_2 0x10061
+#define A_PM_RX_PERR_ENABLE 0x10062
+
+#define S_T7_SDC_ERR    31
+#define V_T7_SDC_ERR(x) ((x) << S_T7_SDC_ERR)
+#define F_T7_SDC_ERR    V_T7_SDC_ERR(1U)
+
+#define S_T7_MA_INTF_SDC_ERR    30
+#define V_T7_MA_INTF_SDC_ERR(x) ((x) << S_T7_MA_INTF_SDC_ERR)
+#define F_T7_MA_INTF_SDC_ERR    V_T7_MA_INTF_SDC_ERR(1U)
+
+#define S_E_PCMD_PERR    21
+#define V_E_PCMD_PERR(x) ((x) << S_E_PCMD_PERR)
+#define F_E_PCMD_PERR    V_E_PCMD_PERR(1U)
+
+#define S_CACHE_RSP_DFIFO_PERR    20
+#define V_CACHE_RSP_DFIFO_PERR(x) ((x) << S_CACHE_RSP_DFIFO_PERR)
+#define F_CACHE_RSP_DFIFO_PERR    V_CACHE_RSP_DFIFO_PERR(1U)
+
+#define S_CACHE_SRAM_ODD_PERR    19
+#define V_CACHE_SRAM_ODD_PERR(x) ((x) << S_CACHE_SRAM_ODD_PERR)
+#define F_CACHE_SRAM_ODD_PERR    V_CACHE_SRAM_ODD_PERR(1U)
+
+#define S_CACHE_SRAM_EVEN_PERR    18
+#define V_CACHE_SRAM_EVEN_PERR(x) ((x) << S_CACHE_SRAM_EVEN_PERR)
+#define F_CACHE_SRAM_EVEN_PERR    V_CACHE_SRAM_EVEN_PERR(1U)
+
+#define S_CACHE_RSVD_PERR    17
+#define V_CACHE_RSVD_PERR(x) ((x) << S_CACHE_RSVD_PERR)
+#define F_CACHE_RSVD_PERR    V_CACHE_RSVD_PERR(1U)
+
+#define S_CACHE_LRU_LEFT_PERR    16
+#define V_CACHE_LRU_LEFT_PERR(x) ((x) << S_CACHE_LRU_LEFT_PERR)
+#define F_CACHE_LRU_LEFT_PERR    V_CACHE_LRU_LEFT_PERR(1U)
+
+#define S_CACHE_LRU_RIGHT_PERR    15
+#define V_CACHE_LRU_RIGHT_PERR(x) ((x) << S_CACHE_LRU_RIGHT_PERR)
+#define F_CACHE_LRU_RIGHT_PERR    V_CACHE_LRU_RIGHT_PERR(1U)
+
+#define S_CACHE_RSP_CMD_PERR    14
+#define V_CACHE_RSP_CMD_PERR(x) ((x) << S_CACHE_RSP_CMD_PERR)
+#define F_CACHE_RSP_CMD_PERR    V_CACHE_RSP_CMD_PERR(1U)
+
+#define S_CACHE_SRAM_CMD_PERR    13
+#define V_CACHE_SRAM_CMD_PERR(x) ((x) << S_CACHE_SRAM_CMD_PERR)
+#define F_CACHE_SRAM_CMD_PERR    V_CACHE_SRAM_CMD_PERR(1U)
+
+#define S_CACHE_MA_CMD_PERR    12
+#define V_CACHE_MA_CMD_PERR(x) ((x) << S_CACHE_MA_CMD_PERR)
+#define F_CACHE_MA_CMD_PERR    V_CACHE_MA_CMD_PERR(1U)
+
+#define S_CACHE_TCAM_PERR    11
+#define V_CACHE_TCAM_PERR(x) ((x) << S_CACHE_TCAM_PERR)
+#define F_CACHE_TCAM_PERR    V_CACHE_TCAM_PERR(1U)
+
+#define S_CACHE_ISLAND_PERR    10
+#define V_CACHE_ISLAND_PERR(x) ((x) << S_CACHE_ISLAND_PERR)
+#define F_CACHE_ISLAND_PERR    V_CACHE_ISLAND_PERR(1U)
+
+#define S_MC_WCNT_FIFO_PERR    9
+#define V_MC_WCNT_FIFO_PERR(x) ((x) << S_MC_WCNT_FIFO_PERR)
+#define F_MC_WCNT_FIFO_PERR    V_MC_WCNT_FIFO_PERR(1U)
+
+#define S_MC_WDATA_FIFO_PERR    8
+#define V_MC_WDATA_FIFO_PERR(x) ((x) << S_MC_WDATA_FIFO_PERR)
+#define F_MC_WDATA_FIFO_PERR    V_MC_WDATA_FIFO_PERR(1U)
+
+#define S_MC_RCNT_FIFO_PERR    7
+#define V_MC_RCNT_FIFO_PERR(x) ((x) << S_MC_RCNT_FIFO_PERR)
+#define F_MC_RCNT_FIFO_PERR    V_MC_RCNT_FIFO_PERR(1U)
+
+#define S_MC_RDATA_FIFO_PERR    6
+#define V_MC_RDATA_FIFO_PERR(x) ((x) << S_MC_RDATA_FIFO_PERR)
+#define F_MC_RDATA_FIFO_PERR    V_MC_RDATA_FIFO_PERR(1U)
+
+#define S_TOKEN_FIFO_PERR    5
+#define V_TOKEN_FIFO_PERR(x) ((x) << S_TOKEN_FIFO_PERR)
+#define F_TOKEN_FIFO_PERR    V_TOKEN_FIFO_PERR(1U)
+
+#define S_T7_BUNDLE_LEN_PARERR    4
+#define V_T7_BUNDLE_LEN_PARERR(x) ((x) << S_T7_BUNDLE_LEN_PARERR)
+#define F_T7_BUNDLE_LEN_PARERR    V_T7_BUNDLE_LEN_PARERR(1U)
+
+#define A_PM_RX_PERR_CAUSE 0x10063
+#define A_PM_RX_EXT_CFIFO_CONFIG0 0x10070
+
+#define S_CH1_PTR_MAX    17
+#define M_CH1_PTR_MAX    0x7fffU
+#define V_CH1_PTR_MAX(x) ((x) << S_CH1_PTR_MAX)
+#define G_CH1_PTR_MAX(x) (((x) >> S_CH1_PTR_MAX) & M_CH1_PTR_MAX)
+
+#define S_CH0_PTR_MAX    1
+#define M_CH0_PTR_MAX    0x7fffU
+#define V_CH0_PTR_MAX(x) ((x) << S_CH0_PTR_MAX)
+#define G_CH0_PTR_MAX(x) (((x) >> S_CH0_PTR_MAX) & M_CH0_PTR_MAX)
+
+#define S_STROBE    0
+#define V_STROBE(x) ((x) << S_STROBE)
+#define F_STROBE    V_STROBE(1U)
+
+#define A_PM_RX_EXT_CFIFO_CONFIG1 0x10071
+
+#define S_CH2_PTR_MAX    1
+#define M_CH2_PTR_MAX    0x7fffU
+#define V_CH2_PTR_MAX(x) ((x) << S_CH2_PTR_MAX)
+#define G_CH2_PTR_MAX(x) (((x) >> S_CH2_PTR_MAX) & M_CH2_PTR_MAX)
+
+#define A_PM_RX_EXT_EFIFO_CONFIG0 0x10072
+#define A_PM_RX_EXT_EFIFO_CONFIG1 0x10073
+#define A_T7_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x10074
+#define A_T7_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x10075
+#define A_PM_RX_CH2_OSPI_DEFICIT_THRSHLD 0x10076
+#define A_PM_RX_CH3_OSPI_DEFICIT_THRSHLD 0x10077
+#define A_T7_PM_RX_FEATURE_EN 0x10078
+#define A_PM_RX_TCAM_BIST_CTRL 0x10080
+#define A_PM_RX_TCAM_BIST_CB_PASS 0x10081
+#define A_PM_RX_TCAM_BIST_CB_BUSY 0x10082
+
 /* registers for module PM_TX */
 #define PM_TX_BASE_ADDR 0x8fe0
 
@@ -30613,6 +38779,118 @@
 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
 #define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)
 
+#define S_T7_ZERO_C_CMD_ERROR    30
+#define V_T7_ZERO_C_CMD_ERROR(x) ((x) << S_T7_ZERO_C_CMD_ERROR)
+#define F_T7_ZERO_C_CMD_ERROR    V_T7_ZERO_C_CMD_ERROR(1U)
+
+#define S_OESPI_COR_ERR    29
+#define V_OESPI_COR_ERR(x) ((x) << S_OESPI_COR_ERR)
+#define F_OESPI_COR_ERR    V_OESPI_COR_ERR(1U)
+
+#define S_ICSPI_COR_ERR    28
+#define V_ICSPI_COR_ERR(x) ((x) << S_ICSPI_COR_ERR)
+#define F_ICSPI_COR_ERR    V_ICSPI_COR_ERR(1U)
+
+#define S_ICSPI_OVFL    24
+#define V_ICSPI_OVFL(x) ((x) << S_ICSPI_OVFL)
+#define F_ICSPI_OVFL    V_ICSPI_OVFL(1U)
+
+#define S_PCMD_LEN_OVFL3    23
+#define V_PCMD_LEN_OVFL3(x) ((x) << S_PCMD_LEN_OVFL3)
+#define F_PCMD_LEN_OVFL3    V_PCMD_LEN_OVFL3(1U)
+
+#define S_T7_PCMD_LEN_OVFL2    22
+#define V_T7_PCMD_LEN_OVFL2(x) ((x) << S_T7_PCMD_LEN_OVFL2)
+#define F_T7_PCMD_LEN_OVFL2    V_T7_PCMD_LEN_OVFL2(1U)
+
+#define S_T7_PCMD_LEN_OVFL1    21
+#define V_T7_PCMD_LEN_OVFL1(x) ((x) << S_T7_PCMD_LEN_OVFL1)
+#define F_T7_PCMD_LEN_OVFL1    V_T7_PCMD_LEN_OVFL1(1U)
+
+#define S_T7_PCMD_LEN_OVFL0    20
+#define V_T7_PCMD_LEN_OVFL0(x) ((x) << S_T7_PCMD_LEN_OVFL0)
+#define F_T7_PCMD_LEN_OVFL0    V_T7_PCMD_LEN_OVFL0(1U)
+
+#define S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR    19
+#define V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
+#define F_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR    18
+#define V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
+#define F_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR    17
+#define V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
+#define F_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR    16
+#define V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
+#define F_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI0_TX_FRAMING_ERROR    15
+#define V_T7_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_TX_FRAMING_ERROR)
+#define F_T7_ICSPI0_TX_FRAMING_ERROR    V_T7_ICSPI0_TX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI1_TX_FRAMING_ERROR    14
+#define V_T7_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_TX_FRAMING_ERROR)
+#define F_T7_ICSPI1_TX_FRAMING_ERROR    V_T7_ICSPI1_TX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI2_TX_FRAMING_ERROR    13
+#define V_T7_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_TX_FRAMING_ERROR)
+#define F_T7_ICSPI2_TX_FRAMING_ERROR    V_T7_ICSPI2_TX_FRAMING_ERROR(1U)
+
+#define S_T7_ICSPI3_TX_FRAMING_ERROR    12
+#define V_T7_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_TX_FRAMING_ERROR)
+#define F_T7_ICSPI3_TX_FRAMING_ERROR    V_T7_ICSPI3_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI0_RX_FRAMING_ERROR    11
+#define V_T7_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_RX_FRAMING_ERROR)
+#define F_T7_OESPI0_RX_FRAMING_ERROR    V_T7_OESPI0_RX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI1_RX_FRAMING_ERROR    10
+#define V_T7_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_RX_FRAMING_ERROR)
+#define F_T7_OESPI1_RX_FRAMING_ERROR    V_T7_OESPI1_RX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI2_RX_FRAMING_ERROR    9
+#define V_T7_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_RX_FRAMING_ERROR)
+#define F_T7_OESPI2_RX_FRAMING_ERROR    V_T7_OESPI2_RX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI3_RX_FRAMING_ERROR    8
+#define V_T7_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_RX_FRAMING_ERROR)
+#define F_T7_OESPI3_RX_FRAMING_ERROR    V_T7_OESPI3_RX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI0_TX_FRAMING_ERROR    7
+#define V_T7_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_TX_FRAMING_ERROR)
+#define F_T7_OESPI0_TX_FRAMING_ERROR    V_T7_OESPI0_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI1_TX_FRAMING_ERROR    6
+#define V_T7_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_TX_FRAMING_ERROR)
+#define F_T7_OESPI1_TX_FRAMING_ERROR    V_T7_OESPI1_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI2_TX_FRAMING_ERROR    5
+#define V_T7_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_TX_FRAMING_ERROR)
+#define F_T7_OESPI2_TX_FRAMING_ERROR    V_T7_OESPI2_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI3_TX_FRAMING_ERROR    4
+#define V_T7_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_TX_FRAMING_ERROR)
+#define F_T7_OESPI3_TX_FRAMING_ERROR    V_T7_OESPI3_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR    3
+#define V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
+#define F_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR    2
+#define V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
+#define F_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR    1
+#define V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
+#define F_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR    0
+#define V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
+#define F_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
+
 #define A_PM_TX_INT_CAUSE 0x8ffc
 
 #define S_ZERO_C_CMD_ERROR    28
@@ -30624,23 +38902,51 @@
 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
 
 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
+#define A_T7_PM_TX_DBG_STAT_MSB 0x10000
 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
+#define A_T7_PM_TX_DBG_STAT_LSB 0x10001
 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
+#define A_T7_PM_TX_DBG_RSVD_FLIT_CNT 0x10002
 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
+#define A_T7_PM_TX_SDC_EN 0x10003
 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
+#define A_T7_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x10004
 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
+#define A_T7_PM_TX_INOUT_FIFO_DBG_WR 0x10005
 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
+#define A_T7_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10006
 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
+#define A_T7_PM_TX_FEATURE_EN 0x10007
+
+#define S_IN_AFULL_TH    5
+#define M_IN_AFULL_TH    0x3U
+#define V_IN_AFULL_TH(x) ((x) << S_IN_AFULL_TH)
+#define G_IN_AFULL_TH(x) (((x) >> S_IN_AFULL_TH) & M_IN_AFULL_TH)
+
+#define S_PIO_FROM_CH_EN    4
+#define V_PIO_FROM_CH_EN(x) ((x) << S_PIO_FROM_CH_EN)
+#define F_PIO_FROM_CH_EN    V_PIO_FROM_CH_EN(1U)
+
 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
+#define A_T7_PM_TX_T5_PM_TX_INT_ENABLE 0x10008
 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
+#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10009
 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
+#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x1000a
 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
+#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x1000b
 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
+#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x1000c
 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
+#define A_T7_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x1000d
 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
+#define A_T7_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x1000e
 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
+#define A_T7_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x1000f
 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
+#define A_T7_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x10010
 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
+#define A_T7_PM_TX_INT_CAUSE_MASK_HALT 0x10011
 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
@@ -30722,6 +39028,48 @@
 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
+#define A_PM_TX_PERR_ENABLE 0x10028
+
+#define S_T7_1_OSPI_OVERFLOW3    23
+#define V_T7_1_OSPI_OVERFLOW3(x) ((x) << S_T7_1_OSPI_OVERFLOW3)
+#define F_T7_1_OSPI_OVERFLOW3    V_T7_1_OSPI_OVERFLOW3(1U)
+
+#define S_T7_1_OSPI_OVERFLOW2    22
+#define V_T7_1_OSPI_OVERFLOW2(x) ((x) << S_T7_1_OSPI_OVERFLOW2)
+#define F_T7_1_OSPI_OVERFLOW2    V_T7_1_OSPI_OVERFLOW2(1U)
+
+#define S_T7_1_OSPI_OVERFLOW1    21
+#define V_T7_1_OSPI_OVERFLOW1(x) ((x) << S_T7_1_OSPI_OVERFLOW1)
+#define F_T7_1_OSPI_OVERFLOW1    V_T7_1_OSPI_OVERFLOW1(1U)
+
+#define S_T7_1_OSPI_OVERFLOW0    20
+#define V_T7_1_OSPI_OVERFLOW0(x) ((x) << S_T7_1_OSPI_OVERFLOW0)
+#define F_T7_1_OSPI_OVERFLOW0    V_T7_1_OSPI_OVERFLOW0(1U)
+
+#define S_T7_BUNDLE_LEN_OVFL_EN    18
+#define V_T7_BUNDLE_LEN_OVFL_EN(x) ((x) << S_T7_BUNDLE_LEN_OVFL_EN)
+#define F_T7_BUNDLE_LEN_OVFL_EN    V_T7_BUNDLE_LEN_OVFL_EN(1U)
+
+#define S_T7_M_INTFPERREN    17
+#define V_T7_M_INTFPERREN(x) ((x) << S_T7_M_INTFPERREN)
+#define F_T7_M_INTFPERREN    V_T7_M_INTFPERREN(1U)
+
+#define S_T7_1_SDC_ERR    16
+#define V_T7_1_SDC_ERR(x) ((x) << S_T7_1_SDC_ERR)
+#define F_T7_1_SDC_ERR    V_T7_1_SDC_ERR(1U)
+
+#define S_TOKEN_PAR_ERROR    5
+#define V_TOKEN_PAR_ERROR(x) ((x) << S_TOKEN_PAR_ERROR)
+#define F_TOKEN_PAR_ERROR    V_TOKEN_PAR_ERROR(1U)
+
+#define S_BUNDLE_LEN_PAR_ERROR    4
+#define V_BUNDLE_LEN_PAR_ERROR(x) ((x) << S_BUNDLE_LEN_PAR_ERROR)
+#define F_BUNDLE_LEN_PAR_ERROR    V_BUNDLE_LEN_PAR_ERROR(1U)
+
+#define S_C_PCMD_TOKEN_PAR_ERROR    0
+#define V_C_PCMD_TOKEN_PAR_ERROR(x) ((x) << S_C_PCMD_TOKEN_PAR_ERROR)
+#define F_C_PCMD_TOKEN_PAR_ERROR    V_C_PCMD_TOKEN_PAR_ERROR(1U)
+
 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
 
 #define S_CH2_OSPI_DEFICIT_THRSHLD    0
@@ -30729,6 +39077,7 @@
 #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
 #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
 
+#define A_PM_TX_PERR_CAUSE 0x10029
 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
 
 #define S_CH3_OSPI_DEFICIT_THRSHLD    0
@@ -31462,6 +39811,7 @@
 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
 
 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
+#define A_MPS_VF_TX_MAC_DROP_PP 0x24
 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
 
@@ -31547,6 +39897,24 @@
 #define V_TXPRTY0(x) ((x) << S_TXPRTY0)
 #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
 
+#define A_MPS_PORT_PRTY_GROUP_MAP 0x34
+#define A_MPS_PORT_TRACE_MAX_CAPTURE_SIZE 0x38
+
+#define S_TX2RX    6
+#define M_TX2RX    0x7U
+#define V_TX2RX(x) ((x) << S_TX2RX)
+#define G_TX2RX(x) (((x) >> S_TX2RX) & M_TX2RX)
+
+#define S_MAC2MPS    3
+#define M_MAC2MPS    0x7U
+#define V_MAC2MPS(x) ((x) << S_MAC2MPS)
+#define G_MAC2MPS(x) (((x) >> S_MAC2MPS) & M_MAC2MPS)
+
+#define S_MPS2MAC    0
+#define M_MPS2MAC    0x7U
+#define V_MPS2MAC(x) ((x) << S_MPS2MAC)
+#define G_MPS2MAC(x) (((x) >> S_MPS2MAC) & M_MPS2MAC)
+
 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
@@ -31578,7 +39946,9 @@
 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
+#define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_L 0xf8
 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
+#define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_H 0xfc
 #define A_MPS_PORT_RX_CTL 0x100
 
 #define S_NO_RPLCT_M    20
@@ -31682,6 +40052,26 @@
 #define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC)
 #define F_HASH_EN_MAC    V_HASH_EN_MAC(1U)
 
+#define S_TRANS_ENCAP_EN    30
+#define V_TRANS_ENCAP_EN(x) ((x) << S_TRANS_ENCAP_EN)
+#define F_TRANS_ENCAP_EN    V_TRANS_ENCAP_EN(1U)
+
+#define S_CRYPTO_DUMMY_PKT_CHK_EN    29
+#define V_CRYPTO_DUMMY_PKT_CHK_EN(x) ((x) << S_CRYPTO_DUMMY_PKT_CHK_EN)
+#define F_CRYPTO_DUMMY_PKT_CHK_EN    V_CRYPTO_DUMMY_PKT_CHK_EN(1U)
+
+#define S_PASS_HPROM    28
+#define V_PASS_HPROM(x) ((x) << S_PASS_HPROM)
+#define F_PASS_HPROM    V_PASS_HPROM(1U)
+
+#define S_PASS_PROM    27
+#define V_PASS_PROM(x) ((x) << S_PASS_PROM)
+#define F_PASS_PROM    V_PASS_PROM(1U)
+
+#define S_ENCAP_ONLY_IF_OUTER_HIT    26
+#define V_ENCAP_ONLY_IF_OUTER_HIT(x) ((x) << S_ENCAP_ONLY_IF_OUTER_HIT)
+#define F_ENCAP_ONLY_IF_OUTER_HIT    V_ENCAP_ONLY_IF_OUTER_HIT(1U)
+
 #define A_MPS_PORT_RX_MTU 0x104
 #define A_MPS_PORT_RX_PF_MAP 0x108
 #define A_MPS_PORT_RX_VF_MAP0 0x10c
@@ -31924,6 +40314,23 @@
 #define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL)
 #define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL)
 
+#define A_MPS_PORT_MAC_RX_DROP_EN_PP 0x16c
+
+#define S_PRIO    0
+#define M_PRIO    0xffU
+#define V_PRIO(x) ((x) << S_PRIO)
+#define G_PRIO(x) (((x) >> S_PRIO) & M_PRIO)
+
+#define A_MPS_PORT_RX_INT_RSS_HASH 0x170
+#define A_MPS_PORT_RX_INT_RSS_CONTROL 0x174
+#define A_MPS_PORT_RX_CNT_DBG_CTL 0x178
+
+#define S_DBG_TYPE    0
+#define M_DBG_TYPE    0x1fU
+#define V_DBG_TYPE(x) ((x) << S_DBG_TYPE)
+#define G_DBG_TYPE(x) (((x) >> S_DBG_TYPE) & M_DBG_TYPE)
+
+#define A_MPS_PORT_RX_CNT_DBG 0x17c
 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
 
 #define S_CREDIT    0
@@ -31984,6 +40391,10 @@
 #define V_ON_PENDING(x) ((x) << S_ON_PENDING)
 #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
 
+#define A_MPS_PORT_TX_MAC_DROP_PP 0x1d4
+#define A_MPS_PORT_TX_LPBK_DROP_PP 0x1d8
+#define A_MPS_PORT_TX_MAC_DROP_CNT 0x1dc
+#define A_MPS_PORT_TX_LPBK_DROP_CNT 0x1e0
 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
 
 #define S_VALID    20
@@ -32097,6 +40508,13 @@
 #define V_TAG(x) ((x) << S_TAG)
 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
 
+#define A_MPS_PF_TX_MAC_DROP_PP 0x2e4
+
+#define S_T7_DROPEN    0
+#define M_T7_DROPEN    0xffU
+#define V_T7_DROPEN(x) ((x) << S_T7_DROPEN)
+#define G_T7_DROPEN(x) (((x) >> S_T7_DROPEN) & M_T7_DROPEN)
+
 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
 #define A_MPS_PORT_CLS_HASH_CTL 0x304
@@ -32112,35 +40530,9 @@
 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
 #define F_PROMISCEN    V_PROMISCEN(1U)
 
-#define S_T6_MULTILISTEN    16
-#define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
-#define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
-
-#define S_T6_PRIORITY    13
-#define M_T6_PRIORITY    0x7U
-#define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
-#define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
-
-#define S_T6_REPLICATE    12
-#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
-#define F_T6_REPLICATE    V_T6_REPLICATE(1U)
-
-#define S_T6_PF    9
-#define M_T6_PF    0x7U
-#define V_T6_PF(x) ((x) << S_T6_PF)
-#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
-
-#define S_T6_VF_VALID    8
-#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
-#define F_T6_VF_VALID    V_T6_VF_VALID(1U)
-
-#define S_T6_VF    0
-#define M_T6_VF    0xffU
-#define V_T6_VF(x) ((x) << S_T6_VF)
-#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
-
 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
+#define A_MPS_PORT_CLS_BMC_MAC0_ADDR_L 0x30c
 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
 
@@ -32156,6 +40548,7 @@
 #define V_MATCHALL(x) ((x) << S_MATCHALL)
 #define F_MATCHALL    V_MATCHALL(1U)
 
+#define A_MPS_PORT_CLS_BMC_MAC0_ADDR_H 0x310
 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
 
@@ -32167,6 +40560,7 @@
 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
 #define F_VLAN_VLD    V_VLAN_VLD(1U)
 
+#define A_MPS_PORT_CLS_BMC_VLAN0 0x314
 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
 #define A_MPS_PORT_CLS_CTL 0x318
 
@@ -32218,6 +40612,18 @@
 #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
 
+#define S_SMAC_INDEX_EN    17
+#define V_SMAC_INDEX_EN(x) ((x) << S_SMAC_INDEX_EN)
+#define F_SMAC_INDEX_EN    V_SMAC_INDEX_EN(1U)
+
+#define S_LPBK_TCAM2_HIT_PRIORITY    16
+#define V_LPBK_TCAM2_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM2_HIT_PRIORITY)
+#define F_LPBK_TCAM2_HIT_PRIORITY    V_LPBK_TCAM2_HIT_PRIORITY(1U)
+
+#define S_TCAM2_HIT_PRIORITY    15
+#define V_TCAM2_HIT_PRIORITY(x) ((x) << S_TCAM2_HIT_PRIORITY)
+#define F_TCAM2_HIT_PRIORITY    V_TCAM2_HIT_PRIORITY(1U)
+
 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
 
@@ -32238,14 +40644,23 @@
 #define F_EN2    V_EN2(1U)
 
 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
+#define A_MPS_PORT_CLS_BMC_MAC1_ADDR_L 0x324
 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
+#define A_MPS_PORT_CLS_BMC_MAC1_ADDR_H 0x328
 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
+#define A_MPS_PORT_CLS_BMC_MAC2_ADDR_L 0x32c
 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
+#define A_MPS_PORT_CLS_BMC_MAC2_ADDR_H 0x330
 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
+#define A_MPS_PORT_CLS_BMC_MAC3_ADDR_L 0x334
 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
+#define A_MPS_PORT_CLS_BMC_MAC3_ADDR_H 0x338
 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
+#define A_MPS_PORT_CLS_BMC_VLAN1 0x33c
 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
+#define A_MPS_PORT_CLS_BMC_VLAN2 0x340
 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
+#define A_MPS_PORT_CLS_BMC_VLAN3 0x344
 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
@@ -32261,7 +40676,9 @@
 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
+#define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L 0x380
 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
+#define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H 0x384
 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
@@ -32393,6 +40810,22 @@
 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
+#define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L 0x620
+#define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H 0x624
+#define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L 0x628
+#define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H 0x62c
+#define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L 0x630
+#define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H 0x634
+#define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L 0x638
+#define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H 0x63c
+#define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L 0x640
+#define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H 0x644
+#define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L 0x648
+#define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H 0x64c
+#define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L 0x650
+#define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H 0x654
+#define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L 0x658
+#define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H 0x65c
 #define A_MPS_CMN_CTL 0x9000
 
 #define S_DETECT8023    3
@@ -32425,6 +40858,46 @@
 #define V_SPEEDMODE(x) ((x) << S_SPEEDMODE)
 #define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE)
 
+#define S_PT1_SEL_CFG    21
+#define V_PT1_SEL_CFG(x) ((x) << S_PT1_SEL_CFG)
+#define F_PT1_SEL_CFG    V_PT1_SEL_CFG(1U)
+
+#define S_BUG_42938_EN    20
+#define V_BUG_42938_EN(x) ((x) << S_BUG_42938_EN)
+#define F_BUG_42938_EN    V_BUG_42938_EN(1U)
+
+#define S_NO_BYPASS_PAUSE    19
+#define V_NO_BYPASS_PAUSE(x) ((x) << S_NO_BYPASS_PAUSE)
+#define F_NO_BYPASS_PAUSE    V_NO_BYPASS_PAUSE(1U)
+
+#define S_BYPASS_PAUSE    18
+#define V_BYPASS_PAUSE(x) ((x) << S_BYPASS_PAUSE)
+#define F_BYPASS_PAUSE    V_BYPASS_PAUSE(1U)
+
+#define S_PBUS_EN    16
+#define M_PBUS_EN    0x3U
+#define V_PBUS_EN(x) ((x) << S_PBUS_EN)
+#define G_PBUS_EN(x) (((x) >> S_PBUS_EN) & M_PBUS_EN)
+
+#define S_INIC_EN    14
+#define M_INIC_EN    0x3U
+#define V_INIC_EN(x) ((x) << S_INIC_EN)
+#define G_INIC_EN(x) (((x) >> S_INIC_EN) & M_INIC_EN)
+
+#define S_SBA_EN    12
+#define M_SBA_EN    0x3U
+#define V_SBA_EN(x) ((x) << S_SBA_EN)
+#define G_SBA_EN(x) (((x) >> S_SBA_EN) & M_SBA_EN)
+
+#define S_BG2TP_MAP_MODE    11
+#define V_BG2TP_MAP_MODE(x) ((x) << S_BG2TP_MAP_MODE)
+#define F_BG2TP_MAP_MODE    V_BG2TP_MAP_MODE(1U)
+
+#define S_MPS_LB_MODE    9
+#define M_MPS_LB_MODE    0x3U
+#define V_MPS_LB_MODE(x) ((x) << S_MPS_LB_MODE)
+#define G_MPS_LB_MODE(x) (((x) >> S_MPS_LB_MODE) & M_MPS_LB_MODE)
+
 #define A_MPS_INT_ENABLE 0x9004
 
 #define S_STATINTENB    5
@@ -32618,6 +41091,17 @@
 
 #define A_MPS_T5_BUILD_REVISION 0x9078
 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
+
+#define S_VALUE_1    16
+#define M_VALUE_1    0xffffU
+#define V_VALUE_1(x) ((x) << S_VALUE_1)
+#define G_VALUE_1(x) (((x) >> S_VALUE_1) & M_VALUE_1)
+
+#define S_VALUE_0    0
+#define M_VALUE_0    0xffffU
+#define V_VALUE_0(x) ((x) << S_VALUE_0)
+#define G_VALUE_0(x) (((x) >> S_VALUE_0) & M_VALUE_0)
+
 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
@@ -32671,11 +41155,130 @@
 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
 
 #define A_MPS_FPGA_BIST_CFG_P1 0x9124
-
-#define S_T6_BASEADDR    0
-#define M_T6_BASEADDR    0xffffU
-#define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
-#define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
+#define A_MPS_FPGA_BIST_CFG_P2 0x9128
+#define A_MPS_FPGA_BIST_CFG_P3 0x912c
+#define A_MPS_INIC_CTL 0x9130
+
+#define S_T7_RD_WRN    16
+#define V_T7_RD_WRN(x) ((x) << S_T7_RD_WRN)
+#define F_T7_RD_WRN    V_T7_RD_WRN(1U)
+
+#define A_MPS_INIC_DATA 0x9134
+#define A_MPS_TP_CSIDE_MUX_CTL_P2 0x9138
+#define A_MPS_TP_CSIDE_MUX_CTL_P3 0x913c
+#define A_MPS_RED_CTL 0x9140
+
+#define S_LPBK_SHIFT_0    28
+#define M_LPBK_SHIFT_0    0xfU
+#define V_LPBK_SHIFT_0(x) ((x) << S_LPBK_SHIFT_0)
+#define G_LPBK_SHIFT_0(x) (((x) >> S_LPBK_SHIFT_0) & M_LPBK_SHIFT_0)
+
+#define S_LPBK_SHIFT_1    24
+#define M_LPBK_SHIFT_1    0xfU
+#define V_LPBK_SHIFT_1(x) ((x) << S_LPBK_SHIFT_1)
+#define G_LPBK_SHIFT_1(x) (((x) >> S_LPBK_SHIFT_1) & M_LPBK_SHIFT_1)
+
+#define S_LPBK_SHIFT_2    20
+#define M_LPBK_SHIFT_2    0xfU
+#define V_LPBK_SHIFT_2(x) ((x) << S_LPBK_SHIFT_2)
+#define G_LPBK_SHIFT_2(x) (((x) >> S_LPBK_SHIFT_2) & M_LPBK_SHIFT_2)
+
+#define S_LPBK_SHIFT_3    16
+#define M_LPBK_SHIFT_3    0xfU
+#define V_LPBK_SHIFT_3(x) ((x) << S_LPBK_SHIFT_3)
+#define G_LPBK_SHIFT_3(x) (((x) >> S_LPBK_SHIFT_3) & M_LPBK_SHIFT_3)
+
+#define S_MAC_SHIFT_0    12
+#define M_MAC_SHIFT_0    0xfU
+#define V_MAC_SHIFT_0(x) ((x) << S_MAC_SHIFT_0)
+#define G_MAC_SHIFT_0(x) (((x) >> S_MAC_SHIFT_0) & M_MAC_SHIFT_0)
+
+#define S_MAC_SHIFT_1    8
+#define M_MAC_SHIFT_1    0xfU
+#define V_MAC_SHIFT_1(x) ((x) << S_MAC_SHIFT_1)
+#define G_MAC_SHIFT_1(x) (((x) >> S_MAC_SHIFT_1) & M_MAC_SHIFT_1)
+
+#define S_MAC_SHIFT_2    4
+#define M_MAC_SHIFT_2    0xfU
+#define V_MAC_SHIFT_2(x) ((x) << S_MAC_SHIFT_2)
+#define G_MAC_SHIFT_2(x) (((x) >> S_MAC_SHIFT_2) & M_MAC_SHIFT_2)
+
+#define S_MAC_SHIFT_3    0
+#define M_MAC_SHIFT_3    0xfU
+#define V_MAC_SHIFT_3(x) ((x) << S_MAC_SHIFT_3)
+#define G_MAC_SHIFT_3(x) (((x) >> S_MAC_SHIFT_3) & M_MAC_SHIFT_3)
+
+#define A_MPS_RED_EN 0x9144
+
+#define S_LPBK_EN3    7
+#define V_LPBK_EN3(x) ((x) << S_LPBK_EN3)
+#define F_LPBK_EN3    V_LPBK_EN3(1U)
+
+#define S_LPBK_EN2    6
+#define V_LPBK_EN2(x) ((x) << S_LPBK_EN2)
+#define F_LPBK_EN2    V_LPBK_EN2(1U)
+
+#define S_LPBK_EN1    5
+#define V_LPBK_EN1(x) ((x) << S_LPBK_EN1)
+#define F_LPBK_EN1    V_LPBK_EN1(1U)
+
+#define S_LPBK_EN0    4
+#define V_LPBK_EN0(x) ((x) << S_LPBK_EN0)
+#define F_LPBK_EN0    V_LPBK_EN0(1U)
+
+#define S_MAC_EN3    3
+#define V_MAC_EN3(x) ((x) << S_MAC_EN3)
+#define F_MAC_EN3    V_MAC_EN3(1U)
+
+#define S_MAC_EN2    2
+#define V_MAC_EN2(x) ((x) << S_MAC_EN2)
+#define F_MAC_EN2    V_MAC_EN2(1U)
+
+#define S_MAC_EN1    1
+#define V_MAC_EN1(x) ((x) << S_MAC_EN1)
+#define F_MAC_EN1    V_MAC_EN1(1U)
+
+#define S_MAC_EN0    0
+#define V_MAC_EN0(x) ((x) << S_MAC_EN0)
+#define F_MAC_EN0    V_MAC_EN0(1U)
+
+#define A_MPS_MAC0_RED_DROP_CNT_H 0x9148
+#define A_MPS_MAC0_RED_DROP_CNT_L 0x914c
+#define A_MPS_MAC1_RED_DROP_CNT_H 0x9150
+#define A_MPS_MAC1_RED_DROP_CNT_L 0x9154
+#define A_MPS_MAC2_RED_DROP_CNT_H 0x9158
+#define A_MPS_MAC2_RED_DROP_CNT_L 0x915c
+#define A_MPS_MAC3_RED_DROP_CNT_H 0x9160
+#define A_MPS_MAC3_RED_DROP_CNT_L 0x9164
+#define A_MPS_LPBK0_RED_DROP_CNT_H 0x9168
+#define A_MPS_LPBK0_RED_DROP_CNT_L 0x916c
+#define A_MPS_LPBK1_RED_DROP_CNT_H 0x9170
+#define A_MPS_LPBK1_RED_DROP_CNT_L 0x9174
+#define A_MPS_LPBK2_RED_DROP_CNT_H 0x9178
+#define A_MPS_LPBK2_RED_DROP_CNT_L 0x917c
+#define A_MPS_LPBK3_RED_DROP_CNT_H 0x9180
+#define A_MPS_LPBK3_RED_DROP_CNT_L 0x9184
+#define A_MPS_MAC_RED_PP_DROP_EN 0x9188
+
+#define S_T7_MAC3    24
+#define M_T7_MAC3    0xffU
+#define V_T7_MAC3(x) ((x) << S_T7_MAC3)
+#define G_T7_MAC3(x) (((x) >> S_T7_MAC3) & M_T7_MAC3)
+
+#define S_T7_MAC2    16
+#define M_T7_MAC2    0xffU
+#define V_T7_MAC2(x) ((x) << S_T7_MAC2)
+#define G_T7_MAC2(x) (((x) >> S_T7_MAC2) & M_T7_MAC2)
+
+#define S_T7_MAC1    8
+#define M_T7_MAC1    0xffU
+#define V_T7_MAC1(x) ((x) << S_T7_MAC1)
+#define G_T7_MAC1(x) (((x) >> S_T7_MAC1) & M_T7_MAC1)
+
+#define S_T7_MAC0    0
+#define M_T7_MAC0    0xffU
+#define V_T7_MAC0(x) ((x) << S_T7_MAC0)
+#define G_T7_MAC0(x) (((x) >> S_T7_MAC0) & M_T7_MAC0)
 
 #define A_MPS_TX_PRTY_SEL 0x9400
 
@@ -32714,6 +41317,26 @@
 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
 
+#define S_T7_CH4_PRTY    16
+#define M_T7_CH4_PRTY    0x7U
+#define V_T7_CH4_PRTY(x) ((x) << S_T7_CH4_PRTY)
+#define G_T7_CH4_PRTY(x) (((x) >> S_T7_CH4_PRTY) & M_T7_CH4_PRTY)
+
+#define S_T7_CH3_PRTY    13
+#define M_T7_CH3_PRTY    0x7U
+#define V_T7_CH3_PRTY(x) ((x) << S_T7_CH3_PRTY)
+#define G_T7_CH3_PRTY(x) (((x) >> S_T7_CH3_PRTY) & M_T7_CH3_PRTY)
+
+#define S_T7_CH2_PRTY    10
+#define M_T7_CH2_PRTY    0x7U
+#define V_T7_CH2_PRTY(x) ((x) << S_T7_CH2_PRTY)
+#define G_T7_CH2_PRTY(x) (((x) >> S_T7_CH2_PRTY) & M_T7_CH2_PRTY)
+
+#define S_T7_CH1_PRTY    7
+#define M_T7_CH1_PRTY    0x7U
+#define V_T7_CH1_PRTY(x) ((x) << S_T7_CH1_PRTY)
+#define G_T7_CH1_PRTY(x) (((x) >> S_T7_CH1_PRTY) & M_T7_CH1_PRTY)
+
 #define A_MPS_TX_INT_ENABLE 0x9404
 
 #define S_PORTERR    16
@@ -32751,9 +41374,52 @@
 #define V_TPFIFO(x) ((x) << S_TPFIFO)
 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
 
+#define S_T7_PORTERR    28
+#define V_T7_PORTERR(x) ((x) << S_T7_PORTERR)
+#define F_T7_PORTERR    V_T7_PORTERR(1U)
+
+#define S_T7_FRMERR    27
+#define V_T7_FRMERR(x) ((x) << S_T7_FRMERR)
+#define F_T7_FRMERR    V_T7_FRMERR(1U)
+
+#define S_T7_SECNTERR    26
+#define V_T7_SECNTERR(x) ((x) << S_T7_SECNTERR)
+#define F_T7_SECNTERR    V_T7_SECNTERR(1U)
+
+#define S_T7_BUBBLE    25
+#define V_T7_BUBBLE(x) ((x) << S_T7_BUBBLE)
+#define F_T7_BUBBLE    V_T7_BUBBLE(1U)
+
+#define S_TXTOKENFIFO    15
+#define M_TXTOKENFIFO    0x3ffU
+#define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
+#define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
+
+#define S_PERR_TP2MPS_TFIFO    13
+#define M_PERR_TP2MPS_TFIFO    0x3U
+#define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
+#define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
+
 #define A_MPS_TX_INT_CAUSE 0x9408
 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
 #define A_MPS_TX_PERR_ENABLE 0x9410
+
+#define S_PORTERRINT    28
+#define V_PORTERRINT(x) ((x) << S_PORTERRINT)
+#define F_PORTERRINT    V_PORTERRINT(1U)
+
+#define S_FRAMINGERRINT    27
+#define V_FRAMINGERRINT(x) ((x) << S_FRAMINGERRINT)
+#define F_FRAMINGERRINT    V_FRAMINGERRINT(1U)
+
+#define S_SECNTERRINT    26
+#define V_SECNTERRINT(x) ((x) << S_SECNTERRINT)
+#define F_SECNTERRINT    V_SECNTERRINT(1U)
+
+#define S_BUBBLEERRINT    25
+#define V_BUBBLEERRINT(x) ((x) << S_BUBBLEERRINT)
+#define F_BUBBLEERRINT    V_BUBBLEERRINT(1U)
+
 #define A_MPS_TX_PERR_INJECT 0x9414
 
 #define S_MPSTXMEMSEL    1
@@ -33481,6 +42147,41 @@
 #define F_TXINCH0_CGEN    V_TXINCH0_CGEN(1U)
 
 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
+#define A_MPS_TX2RX_CH_MAP 0x9474
+
+#define S_ENABLELBK_CH3    3
+#define V_ENABLELBK_CH3(x) ((x) << S_ENABLELBK_CH3)
+#define F_ENABLELBK_CH3    V_ENABLELBK_CH3(1U)
+
+#define S_ENABLELBK_CH2    2
+#define V_ENABLELBK_CH2(x) ((x) << S_ENABLELBK_CH2)
+#define F_ENABLELBK_CH2    V_ENABLELBK_CH2(1U)
+
+#define S_ENABLELBK_CH1    1
+#define V_ENABLELBK_CH1(x) ((x) << S_ENABLELBK_CH1)
+#define F_ENABLELBK_CH1    V_ENABLELBK_CH1(1U)
+
+#define S_ENABLELBK_CH0    0
+#define V_ENABLELBK_CH0(x) ((x) << S_ENABLELBK_CH0)
+#define F_ENABLELBK_CH0    V_ENABLELBK_CH0(1U)
+
+#define A_MPS_TX_DBG_CNT_CTL 0x9478
+
+#define S_DBG_CNT_CTL    0
+#define M_DBG_CNT_CTL    0xffU
+#define V_DBG_CNT_CTL(x) ((x) << S_DBG_CNT_CTL)
+#define G_DBG_CNT_CTL(x) (((x) >> S_DBG_CNT_CTL) & M_DBG_CNT_CTL)
+
+#define A_MPS_TX_DBG_CNT 0x947c
+#define A_MPS_TX_INT2_ENABLE 0x9498
+#define A_MPS_TX_INT2_CAUSE 0x949c
+#define A_MPS_TX_PERR2_ENABLE 0x94a0
+#define A_MPS_TX_INT3_ENABLE 0x94a4
+#define A_MPS_TX_INT3_CAUSE 0x94a8
+#define A_MPS_TX_PERR3_ENABLE 0x94ac
+#define A_MPS_TX_INT4_ENABLE 0x94b0
+#define A_MPS_TX_INT4_CAUSE 0x94b4
+#define A_MPS_TX_PERR4_ENABLE 0x94b8
 #define A_MPS_STAT_CTL 0x9600
 
 #define S_COUNTVFINPF    1
@@ -33810,6 +42511,7 @@
 
 #define A_MPS_TRC_RSS_HASH 0x9804
 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
+#define A_T7_MPS_TRC_PERR_INJECT 0x9804
 #define A_MPS_TRC_RSS_CONTROL 0x9808
 
 #define S_RSSCONTROL    16
@@ -33939,6 +42641,20 @@
 #define V_FILTMEM(x) ((x) << S_FILTMEM)
 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
 
+#define S_T7_MISCPERR    16
+#define V_T7_MISCPERR(x) ((x) << S_T7_MISCPERR)
+#define F_T7_MISCPERR    V_T7_MISCPERR(1U)
+
+#define S_T7_PKTFIFO    8
+#define M_T7_PKTFIFO    0xffU
+#define V_T7_PKTFIFO(x) ((x) << S_T7_PKTFIFO)
+#define G_T7_PKTFIFO(x) (((x) >> S_T7_PKTFIFO) & M_T7_PKTFIFO)
+
+#define S_T7_FILTMEM    0
+#define M_T7_FILTMEM    0xffU
+#define V_T7_FILTMEM(x) ((x) << S_T7_FILTMEM)
+#define G_T7_FILTMEM(x) (((x) >> S_T7_FILTMEM) & M_T7_FILTMEM)
+
 #define A_MPS_TRC_INT_ENABLE 0x9858
 
 #define S_TRCPLERRENB    9
@@ -33961,6 +42677,7 @@
 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
+#define A_MPS_TRC_FILTER4_MATCH 0xa000
 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
 #define A_MPS_T5_TRC_RSS_HASH 0xa008
 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
@@ -34043,125 +42760,8 @@
 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
 
 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
-
-#define S_T6_TRCMPS2TP_MACONLY    22
-#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
-#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
-
-#define S_T6_TRCALLMPS2TP    21
-#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
-#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
-
-#define S_T6_TRCALLTP2MPS    20
-#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
-#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
-
-#define S_T6_TRCALLVF    19
-#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
-#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
-
-#define S_T6_TRC_OFLD_EN    18
-#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
-#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
-
-#define S_T6_VFFILTEN    17
-#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
-#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
-
-#define S_T6_VFFILTMASK    9
-#define M_T6_VFFILTMASK    0xffU
-#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
-#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
-
-#define S_T6_VFFILTVALID    8
-#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
-#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
-
-#define S_T6_VFFILTDATA    0
-#define M_T6_VFFILTDATA    0xffU
-#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
-#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
-
 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
-
-#define S_T6_TRCMPS2TP_MACONLY    22
-#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
-#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
-
-#define S_T6_TRCALLMPS2TP    21
-#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
-#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
-
-#define S_T6_TRCALLTP2MPS    20
-#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
-#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
-
-#define S_T6_TRCALLVF    19
-#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
-#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
-
-#define S_T6_TRC_OFLD_EN    18
-#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
-#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
-
-#define S_T6_VFFILTEN    17
-#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
-#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
-
-#define S_T6_VFFILTMASK    9
-#define M_T6_VFFILTMASK    0xffU
-#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
-#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
-
-#define S_T6_VFFILTVALID    8
-#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
-#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
-
-#define S_T6_VFFILTDATA    0
-#define M_T6_VFFILTDATA    0xffU
-#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
-#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
-
 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
-
-#define S_T6_TRCMPS2TP_MACONLY    22
-#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
-#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
-
-#define S_T6_TRCALLMPS2TP    21
-#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
-#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
-
-#define S_T6_TRCALLTP2MPS    20
-#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
-#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
-
-#define S_T6_TRCALLVF    19
-#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
-#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
-
-#define S_T6_TRC_OFLD_EN    18
-#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
-#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
-
-#define S_T6_VFFILTEN    17
-#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
-#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
-
-#define S_T6_VFFILTMASK    9
-#define M_T6_VFFILTMASK    0xffU
-#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
-#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
-
-#define S_T6_VFFILTVALID    8
-#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
-#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
-
-#define S_T6_VFFILTDATA    0
-#define M_T6_VFFILTDATA    0xffU
-#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
-#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
-
 #define A_MPS_TRC_CGEN 0xa020
 
 #define S_MPSTRCCGEN    0
@@ -34169,6 +42769,129 @@
 #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
 #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
 
+#define A_MPS_TRC_FILTER4_DONT_CARE 0xa080
+#define A_MPS_TRC_FILTER5_MATCH 0xa100
+#define A_MPS_TRC_FILTER5_DONT_CARE 0xa180
+#define A_MPS_TRC_FILTER6_MATCH 0xa200
+#define A_MPS_TRC_FILTER6_DONT_CARE 0xa280
+#define A_MPS_TRC_FILTER7_MATCH 0xa300
+#define A_MPS_TRC_FILTER7_DONT_CARE 0xa380
+#define A_T7_MPS_TRC_FILTER0_RSS_HASH 0xa3f0
+#define A_T7_MPS_TRC_FILTER0_RSS_CONTROL 0xa3f4
+#define A_T7_MPS_TRC_FILTER1_RSS_HASH 0xa3f8
+#define A_T7_MPS_TRC_FILTER1_RSS_CONTROL 0xa3fc
+#define A_T7_MPS_TRC_FILTER2_RSS_HASH 0xa400
+#define A_T7_MPS_TRC_FILTER2_RSS_CONTROL 0xa404
+#define A_T7_MPS_TRC_FILTER3_RSS_HASH 0xa408
+#define A_T7_MPS_TRC_FILTER3_RSS_CONTROL 0xa40c
+#define A_MPS_TRC_FILTER4_RSS_HASH 0xa410
+#define A_MPS_TRC_FILTER4_RSS_CONTROL 0xa414
+#define A_MPS_TRC_FILTER5_RSS_HASH 0xa418
+#define A_MPS_TRC_FILTER5_RSS_CONTROL 0xa41c
+#define A_MPS_TRC_FILTER6_RSS_HASH 0xa420
+#define A_MPS_TRC_FILTER6_RSS_CONTROL 0xa424
+#define A_MPS_TRC_FILTER7_RSS_HASH 0xa428
+#define A_MPS_TRC_FILTER7_RSS_CONTROL 0xa42c
+#define A_T7_MPS_T5_TRC_RSS_HASH 0xa430
+#define A_T7_MPS_T5_TRC_RSS_CONTROL 0xa434
+#define A_T7_MPS_TRC_VF_OFF_FILTER_0 0xa438
+#define A_T7_MPS_TRC_VF_OFF_FILTER_1 0xa43c
+#define A_T7_MPS_TRC_VF_OFF_FILTER_2 0xa440
+#define A_T7_MPS_TRC_VF_OFF_FILTER_3 0xa444
+#define A_MPS_TRC_VF_OFF_FILTER_4 0xa448
+#define A_MPS_TRC_VF_OFF_FILTER_5 0xa44c
+#define A_MPS_TRC_VF_OFF_FILTER_6 0xa450
+#define A_MPS_TRC_VF_OFF_FILTER_7 0xa454
+#define A_T7_MPS_TRC_CGEN 0xa458
+
+#define S_T7_MPSTRCCGEN    0
+#define M_T7_MPSTRCCGEN    0xffU
+#define V_T7_MPSTRCCGEN(x) ((x) << S_T7_MPSTRCCGEN)
+#define G_T7_MPSTRCCGEN(x) (((x) >> S_T7_MPSTRCCGEN) & M_T7_MPSTRCCGEN)
+
+#define A_T7_MPS_TRC_FILTER_MATCH_CTL_A 0xa460
+#define A_T7_MPS_TRC_FILTER_MATCH_CTL_B 0xa480
+#define A_T7_MPS_TRC_FILTER_RUNT_CTL 0xa4a0
+#define A_T7_MPS_TRC_FILTER_DROP 0xa4c0
+#define A_T7_MPS_TRC_INT_ENABLE 0xa4e0
+
+#define S_T7_TRCPLERRENB    17
+#define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
+#define F_T7_TRCPLERRENB    V_T7_TRCPLERRENB(1U)
+
+#define A_T7_MPS_TRC_INT_CAUSE 0xa4e4
+#define A_T7_MPS_TRC_TIMESTAMP_L 0xa4e8
+#define A_T7_MPS_TRC_TIMESTAMP_H 0xa4ec
+#define A_MPS_TRC_PERR_ENABLE2 0xa4f0
+
+#define S_TRC_TF_ECC    24
+#define M_TRC_TF_ECC    0xffU
+#define V_TRC_TF_ECC(x) ((x) << S_TRC_TF_ECC)
+#define G_TRC_TF_ECC(x) (((x) >> S_TRC_TF_ECC) & M_TRC_TF_ECC)
+
+#define S_MPS2MAC_CONV_TRC_CERR    22
+#define M_MPS2MAC_CONV_TRC_CERR    0x3U
+#define V_MPS2MAC_CONV_TRC_CERR(x) ((x) << S_MPS2MAC_CONV_TRC_CERR)
+#define G_MPS2MAC_CONV_TRC_CERR(x) (((x) >> S_MPS2MAC_CONV_TRC_CERR) & M_MPS2MAC_CONV_TRC_CERR)
+
+#define S_MPS2MAC_CONV_TRC    18
+#define M_MPS2MAC_CONV_TRC    0xfU
+#define V_MPS2MAC_CONV_TRC(x) ((x) << S_MPS2MAC_CONV_TRC)
+#define G_MPS2MAC_CONV_TRC(x) (((x) >> S_MPS2MAC_CONV_TRC) & M_MPS2MAC_CONV_TRC)
+
+#define S_TF0_PERR_1    17
+#define V_TF0_PERR_1(x) ((x) << S_TF0_PERR_1)
+#define F_TF0_PERR_1    V_TF0_PERR_1(1U)
+
+#define S_TF1_PERR_1    16
+#define V_TF1_PERR_1(x) ((x) << S_TF1_PERR_1)
+#define F_TF1_PERR_1    V_TF1_PERR_1(1U)
+
+#define S_TF2_PERR_1    15
+#define V_TF2_PERR_1(x) ((x) << S_TF2_PERR_1)
+#define F_TF2_PERR_1    V_TF2_PERR_1(1U)
+
+#define S_TF3_PERR_1    14
+#define V_TF3_PERR_1(x) ((x) << S_TF3_PERR_1)
+#define F_TF3_PERR_1    V_TF3_PERR_1(1U)
+
+#define S_TF4_PERR_1    13
+#define V_TF4_PERR_1(x) ((x) << S_TF4_PERR_1)
+#define F_TF4_PERR_1    V_TF4_PERR_1(1U)
+
+#define S_TF0_PERR_0    12
+#define V_TF0_PERR_0(x) ((x) << S_TF0_PERR_0)
+#define F_TF0_PERR_0    V_TF0_PERR_0(1U)
+
+#define S_TF1_PERR_0    11
+#define V_TF1_PERR_0(x) ((x) << S_TF1_PERR_0)
+#define F_TF1_PERR_0    V_TF1_PERR_0(1U)
+
+#define S_TF2_PERR_0    10
+#define V_TF2_PERR_0(x) ((x) << S_TF2_PERR_0)
+#define F_TF2_PERR_0    V_TF2_PERR_0(1U)
+
+#define S_TF3_PERR_0    9
+#define V_TF3_PERR_0(x) ((x) << S_TF3_PERR_0)
+#define F_TF3_PERR_0    V_TF3_PERR_0(1U)
+
+#define S_TF4_PERR_0    8
+#define V_TF4_PERR_0(x) ((x) << S_TF4_PERR_0)
+#define F_TF4_PERR_0    V_TF4_PERR_0(1U)
+
+#define S_PERR_TF_IN_CTL    0
+#define M_PERR_TF_IN_CTL    0xffU
+#define V_PERR_TF_IN_CTL(x) ((x) << S_PERR_TF_IN_CTL)
+#define G_PERR_TF_IN_CTL(x) (((x) >> S_PERR_TF_IN_CTL) & M_PERR_TF_IN_CTL)
+
+#define A_MPS_TRC_INT_ENABLE2 0xa4f4
+#define A_MPS_TRC_INT_CAUSE2 0xa4f8
+
+#define S_T7_TRC_TF_ECC    22
+#define M_T7_TRC_TF_ECC    0xffU
+#define V_T7_TRC_TF_ECC(x) ((x) << S_T7_TRC_TF_ECC)
+#define G_T7_TRC_TF_ECC(x) (((x) >> S_T7_TRC_TF_ECC) & M_T7_TRC_TF_ECC)
+
 #define A_MPS_CLS_CTL 0xd000
 
 #define S_MEMWRITEFAULT    4
@@ -34246,12 +42969,24 @@
 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
 #define F_MATCHSRAM    V_MATCHSRAM(1U)
 
+#define S_CIM2MPS_INTF_PAR    4
+#define V_CIM2MPS_INTF_PAR(x) ((x) << S_CIM2MPS_INTF_PAR)
+#define F_CIM2MPS_INTF_PAR    V_CIM2MPS_INTF_PAR(1U)
+
+#define S_TCAM_CRC_SRAM    3
+#define V_TCAM_CRC_SRAM(x) ((x) << S_TCAM_CRC_SRAM)
+#define F_TCAM_CRC_SRAM    V_TCAM_CRC_SRAM(1U)
+
 #define A_MPS_CLS_INT_ENABLE 0xd024
 
 #define S_PLERRENB    3
 #define V_PLERRENB(x) ((x) << S_PLERRENB)
 #define F_PLERRENB    V_PLERRENB(1U)
 
+#define S_T7_PLERRENB    5
+#define V_T7_PLERRENB(x) ((x) << S_T7_PLERRENB)
+#define F_T7_PLERRENB    V_T7_PLERRENB(1U)
+
 #define A_MPS_CLS_INT_CAUSE 0xd028
 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
@@ -34314,6 +43049,25 @@
 #define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF)
 #define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF)
 
+#define S_T7_CLS_SPARE    30
+#define M_T7_CLS_SPARE    0x3U
+#define V_T7_CLS_SPARE(x) ((x) << S_T7_CLS_SPARE)
+#define G_T7_CLS_SPARE(x) (((x) >> S_T7_CLS_SPARE) & M_T7_CLS_SPARE)
+
+#define S_T7_1_CLS_PRIORITY    27
+#define M_T7_1_CLS_PRIORITY    0x7U
+#define V_T7_1_CLS_PRIORITY(x) ((x) << S_T7_1_CLS_PRIORITY)
+#define G_T7_1_CLS_PRIORITY(x) (((x) >> S_T7_1_CLS_PRIORITY) & M_T7_1_CLS_PRIORITY)
+
+#define S_T7_1_CLS_REPLICATE    26
+#define V_T7_1_CLS_REPLICATE(x) ((x) << S_T7_1_CLS_REPLICATE)
+#define F_T7_1_CLS_REPLICATE    V_T7_1_CLS_REPLICATE(1U)
+
+#define S_T7_1_CLS_INDEX    15
+#define M_T7_1_CLS_INDEX    0x7ffU
+#define V_T7_1_CLS_INDEX(x) ((x) << S_T7_1_CLS_INDEX)
+#define G_T7_1_CLS_INDEX(x) (((x) >> S_T7_1_CLS_INDEX) & M_T7_1_CLS_INDEX)
+
 #define A_MPS_CLS_PL_TEST_CTL 0xd038
 
 #define S_PLTESTCTL    0
@@ -34327,12 +43081,26 @@
 #define F_PRTBMCCTL    V_PRTBMCCTL(1U)
 
 #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
+#define A_MPS_CLS0_MATCH_CNT_TCAM 0xd100
 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104
+#define A_MPS_CLS0_MATCH_CNT_HASH 0xd104
 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
+#define A_MPS_CLS0_MATCH_CNT_BCAST 0xd108
 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
+#define A_MPS_CLS0_MATCH_CNT_BMC 0xd10c
 #define A_MPS_CLS_MATCH_CNT_PROM 0xd110
+#define A_MPS_CLS0_MATCH_CNT_PROM 0xd110
 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
+#define A_MPS_CLS0_MATCH_CNT_HPROM 0xd114
 #define A_MPS_CLS_MISS_CNT 0xd118
+#define A_MPS_CLS0_MISS_CNT 0xd118
+#define A_MPS_CLS1_MATCH_CNT_TCAM 0xd11c
+#define A_MPS_CLS1_MATCH_CNT_HASH 0xd120
+#define A_MPS_CLS1_MATCH_CNT_BCAST 0xd124
+#define A_MPS_CLS1_MATCH_CNT_BMC 0xd128
+#define A_MPS_CLS1_MATCH_CNT_PROM 0xd12c
+#define A_MPS_CLS1_MATCH_CNT_HPROM 0xd130
+#define A_MPS_CLS1_MISS_CNT 0xd134
 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
 
@@ -34428,6 +43196,15 @@
 #define V_CLSTRCVF(x) ((x) << S_CLSTRCVF)
 #define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF)
 
+#define S_T7_CLSTRCMATCH    23
+#define V_T7_CLSTRCMATCH(x) ((x) << S_T7_CLSTRCMATCH)
+#define F_T7_CLSTRCMATCH    V_T7_CLSTRCMATCH(1U)
+
+#define S_T7_CLSTRCINDEX    12
+#define M_T7_CLSTRCINDEX    0x7ffU
+#define V_T7_CLSTRCINDEX(x) ((x) << S_T7_CLSTRCINDEX)
+#define G_T7_CLSTRCINDEX(x) (((x) >> S_T7_CLSTRCINDEX) & M_T7_CLSTRCINDEX)
+
 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
 
 #define S_VLAN_MASK    16
@@ -34536,24 +43313,6 @@
 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
 #define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)
 
-#define S_T6_REPLICATE    12
-#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
-#define F_T6_REPLICATE    V_T6_REPLICATE(1U)
-
-#define S_T6_PF    9
-#define M_T6_PF    0x7U
-#define V_T6_PF(x) ((x) << S_T6_PF)
-#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
-
-#define S_T6_VF_VALID    8
-#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
-#define F_T6_VF_VALID    V_T6_VF_VALID(1U)
-
-#define S_T6_VF    0
-#define M_T6_VF    0xffU
-#define V_T6_VF(x) ((x) << S_T6_VF)
-#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
-
 #define A_MPS_CLS_SRAM_H 0xe004
 
 #define S_MACPARITY1    9
@@ -34580,6 +43339,41 @@
 #define V_MACPARITY2(x) ((x) << S_MACPARITY2)
 #define F_MACPARITY2    V_MACPARITY2(1U)
 
+#define S_SRAMWRN    31
+#define V_SRAMWRN(x) ((x) << S_SRAMWRN)
+#define F_SRAMWRN    V_SRAMWRN(1U)
+
+#define S_SRAMSPARE    27
+#define M_SRAMSPARE    0xfU
+#define V_SRAMSPARE(x) ((x) << S_SRAMSPARE)
+#define G_SRAMSPARE(x) (((x) >> S_SRAMSPARE) & M_SRAMSPARE)
+
+#define S_SRAMINDEX    16
+#define M_SRAMINDEX    0x7ffU
+#define V_SRAMINDEX(x) ((x) << S_SRAMINDEX)
+#define G_SRAMINDEX(x) (((x) >> S_SRAMINDEX) & M_SRAMINDEX)
+
+#define A_MPS_CLS_HASH_TCAM_CTL 0xe008
+
+#define S_T7_CTLCMDTYPE    15
+#define V_T7_CTLCMDTYPE(x) ((x) << S_T7_CTLCMDTYPE)
+#define F_T7_CTLCMDTYPE    V_T7_CTLCMDTYPE(1U)
+
+#define S_T7_CTLXYBITSEL    12
+#define V_T7_CTLXYBITSEL(x) ((x) << S_T7_CTLXYBITSEL)
+#define F_T7_CTLXYBITSEL    V_T7_CTLXYBITSEL(1U)
+
+#define S_T7_CTLTCAMINDEX    0
+#define M_T7_CTLTCAMINDEX    0x1ffU
+#define V_T7_CTLTCAMINDEX(x) ((x) << S_T7_CTLTCAMINDEX)
+#define G_T7_CTLTCAMINDEX(x) (((x) >> S_T7_CTLTCAMINDEX) & M_T7_CTLTCAMINDEX)
+
+#define A_MPS_CLS_HASH_TCAM_DATA 0xe00c
+
+#define S_LKPTYPE    24
+#define V_LKPTYPE(x) ((x) << S_LKPTYPE)
+#define F_LKPTYPE    V_LKPTYPE(1U)
+
 #define A_MPS_CLS_TCAM_Y_L 0xf000
 #define A_MPS_CLS_TCAM_DATA0 0xf000
 #define A_MPS_CLS_TCAM_Y_H 0xf004
@@ -34648,6 +43442,16 @@
 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
 
+#define S_T7_CTLTCAMSEL    26
+#define M_T7_CTLTCAMSEL    0x3U
+#define V_T7_CTLTCAMSEL(x) ((x) << S_T7_CTLTCAMSEL)
+#define G_T7_CTLTCAMSEL(x) (((x) >> S_T7_CTLTCAMSEL) & M_T7_CTLTCAMSEL)
+
+#define S_T7_1_CTLTCAMINDEX    17
+#define M_T7_1_CTLTCAMINDEX    0x1ffU
+#define V_T7_1_CTLTCAMINDEX(x) ((x) << S_T7_1_CTLTCAMINDEX)
+#define G_T7_1_CTLTCAMINDEX(x) (((x) >> S_T7_1_CTLTCAMINDEX) & M_T7_1_CTLTCAMINDEX)
+
 #define A_MPS_CLS_TCAM_X_H 0xf00c
 
 #define S_TCAMXH    0
@@ -34656,11 +43460,47 @@
 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
 
 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
+#define A_MPS_CLS_TCAM0_RDATA0_REQ_ID0 0xf010
 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
+#define A_MPS_CLS_TCAM0_RDATA1_REQ_ID0 0xf014
 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
+#define A_MPS_CLS_TCAM0_RDATA2_REQ_ID0 0xf018
+#define A_MPS_CLS_TCAM0_RDATA0_REQ_ID1 0xf01c
 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
+#define A_MPS_CLS_TCAM0_RDATA1_REQ_ID1 0xf020
 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
+#define A_MPS_CLS_TCAM0_RDATA2_REQ_ID1 0xf024
 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
+#define A_MPS_CLS_TCAM1_RDATA0_REQ_ID0 0xf028
+#define A_MPS_CLS_TCAM1_RDATA1_REQ_ID0 0xf02c
+#define A_MPS_CLS_TCAM1_RDATA2_REQ_ID0 0xf030
+#define A_MPS_CLS_TCAM1_RDATA0_REQ_ID1 0xf034
+#define A_MPS_CLS_TCAM1_RDATA1_REQ_ID1 0xf038
+#define A_MPS_CLS_TCAM1_RDATA2_REQ_ID1 0xf03c
+#define A_MPS_CLS_TCAM0_MASK_REG0 0xf040
+#define A_MPS_CLS_TCAM0_MASK_REG1 0xf044
+#define A_MPS_CLS_TCAM0_MASK_REG2 0xf048
+
+#define S_MASK_0_2    0
+#define M_MASK_0_2    0xffffU
+#define V_MASK_0_2(x) ((x) << S_MASK_0_2)
+#define G_MASK_0_2(x) (((x) >> S_MASK_0_2) & M_MASK_0_2)
+
+#define A_MPS_CLS_TCAM1_MASK_REG0 0xf04c
+#define A_MPS_CLS_TCAM1_MASK_REG1 0xf050
+#define A_MPS_CLS_TCAM1_MASK_REG2 0xf054
+
+#define S_MASK_1_2    0
+#define M_MASK_1_2    0xffffU
+#define V_MASK_1_2(x) ((x) << S_MASK_1_2)
+#define G_MASK_1_2(x) (((x) >> S_MASK_1_2) & M_MASK_1_2)
+
+#define A_MPS_CLS_TCAM_BIST_CTRL 0xf058
+#define A_MPS_CLS_TCAM_BIST_CB_PASS 0xf05c
+#define A_MPS_CLS_TCAM_BIST_CB_BUSY 0xf060
+#define A_MPS_CLS_TCAM2_MASK_REG0 0xf064
+#define A_MPS_CLS_TCAM2_MASK_REG1 0xf068
+#define A_MPS_CLS_TCAM2_MASK_REG2 0xf06c
 #define A_MPS_RX_CTL 0x11000
 
 #define S_FILT_VLAN_SEL    17
@@ -34686,6 +43526,14 @@
 #define V_SNF(x) ((x) << S_SNF)
 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
 
+#define S_HASH_TCAM_EN    19
+#define V_HASH_TCAM_EN(x) ((x) << S_HASH_TCAM_EN)
+#define F_HASH_TCAM_EN    V_HASH_TCAM_EN(1U)
+
+#define S_SND_ORG_PFVF    18
+#define V_SND_ORG_PFVF(x) ((x) << S_SND_ORG_PFVF)
+#define F_SND_ORG_PFVF    V_SND_ORG_PFVF(1U)
+
 #define A_MPS_RX_PORT_MUX_CTL 0x11004
 
 #define S_CTL_P3    12
@@ -34877,6 +43725,11 @@
 #define V_THRESH(x) ((x) << S_THRESH)
 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
 
+#define S_T7_THRESH    0
+#define M_T7_THRESH    0xfffU
+#define V_T7_THRESH(x) ((x) << S_T7_THRESH)
+#define G_T7_THRESH(x) (((x) >> S_T7_THRESH) & M_T7_THRESH)
+
 #define A_MPS_RX_LPBK_BP1 0x11060
 #define A_MPS_RX_LPBK_BP2 0x11064
 #define A_MPS_RX_LPBK_BP3 0x11068
@@ -34888,6 +43741,12 @@
 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
 
 #define A_MPS_RX_CHMN_CNT 0x11070
+#define A_MPS_CTL_STAT 0x11070
+
+#define S_T7_CTL    0
+#define V_T7_CTL(x) ((x) << S_T7_CTL)
+#define F_T7_CTL    V_T7_CTL(1U)
+
 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
 
 #define S_FF    23
@@ -34990,18 +43849,54 @@
 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
 
-#define A_MPS_RX_PERR_INT_ENABLE 0x11078
+#define S_MAC_IN_FIFO_768B    30
+#define V_MAC_IN_FIFO_768B(x) ((x) << S_MAC_IN_FIFO_768B)
+#define F_MAC_IN_FIFO_768B    V_MAC_IN_FIFO_768B(1U)
 
-#define S_T6_INT_ERR_INT    24
-#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
-#define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
+#define S_T7_1_INT_ERR_INT    29
+#define V_T7_1_INT_ERR_INT(x) ((x) << S_T7_1_INT_ERR_INT)
+#define F_T7_1_INT_ERR_INT    V_T7_1_INT_ERR_INT(1U)
 
-#define A_MPS_RX_PERR_ENABLE 0x1107c
+#define S_FLOP_PERR    28
+#define V_FLOP_PERR(x) ((x) << S_FLOP_PERR)
+#define F_FLOP_PERR    V_FLOP_PERR(1U)
 
-#define S_T6_INT_ERR_INT    24
-#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
-#define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
+#define S_RPLC_MAP    13
+#define M_RPLC_MAP    0x1fU
+#define V_RPLC_MAP(x) ((x) << S_RPLC_MAP)
+#define G_RPLC_MAP(x) (((x) >> S_RPLC_MAP) & M_RPLC_MAP)
+
+#define S_TKN_RUNT_DROP_FIFO    12
+#define V_TKN_RUNT_DROP_FIFO(x) ((x) << S_TKN_RUNT_DROP_FIFO)
+#define F_TKN_RUNT_DROP_FIFO    V_TKN_RUNT_DROP_FIFO(1U)
+
+#define S_T7_PPM3    9
+#define M_T7_PPM3    0x7U
+#define V_T7_PPM3(x) ((x) << S_T7_PPM3)
+#define G_T7_PPM3(x) (((x) >> S_T7_PPM3) & M_T7_PPM3)
 
+#define S_T7_PPM2    6
+#define M_T7_PPM2    0x7U
+#define V_T7_PPM2(x) ((x) << S_T7_PPM2)
+#define G_T7_PPM2(x) (((x) >> S_T7_PPM2) & M_T7_PPM2)
+
+#define S_T7_PPM1    3
+#define M_T7_PPM1    0x7U
+#define V_T7_PPM1(x) ((x) << S_T7_PPM1)
+#define G_T7_PPM1(x) (((x) >> S_T7_PPM1) & M_T7_PPM1)
+
+#define S_T7_PPM0    0
+#define M_T7_PPM0    0x7U
+#define V_T7_PPM0(x) ((x) << S_T7_PPM0)
+#define G_T7_PPM0(x) (((x) >> S_T7_PPM0) & M_T7_PPM0)
+
+#define A_MPS_RX_PERR_INT_ENABLE 0x11078
+
+#define S_T7_2_INT_ERR_INT    30
+#define V_T7_2_INT_ERR_INT(x) ((x) << S_T7_2_INT_ERR_INT)
+#define F_T7_2_INT_ERR_INT    V_T7_2_INT_ERR_INT(1U)
+
+#define A_MPS_RX_PERR_ENABLE 0x1107c
 #define A_MPS_RX_PERR_INJECT 0x11080
 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
 
@@ -35083,8 +43978,43 @@
 #define V_TH_LOW(x) ((x) << S_TH_LOW)
 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
 
+#define A_MPS_RX_PERR_INT_CAUSE2 0x1108c
+
+#define S_CRYPT2MPS_RX_INTF_FIFO    28
+#define M_CRYPT2MPS_RX_INTF_FIFO    0xfU
+#define V_CRYPT2MPS_RX_INTF_FIFO(x) ((x) << S_CRYPT2MPS_RX_INTF_FIFO)
+#define G_CRYPT2MPS_RX_INTF_FIFO(x) (((x) >> S_CRYPT2MPS_RX_INTF_FIFO) & M_CRYPT2MPS_RX_INTF_FIFO)
+
+#define S_INIC2MPS_TX0_PERR    27
+#define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
+#define F_INIC2MPS_TX0_PERR    V_INIC2MPS_TX0_PERR(1U)
+
+#define S_INIC2MPS_TX1_PERR    26
+#define V_INIC2MPS_TX1_PERR(x) ((x) << S_INIC2MPS_TX1_PERR)
+#define F_INIC2MPS_TX1_PERR    V_INIC2MPS_TX1_PERR(1U)
+
+#define S_XGMAC2MPS_RX0_PERR    25
+#define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
+#define F_XGMAC2MPS_RX0_PERR    V_XGMAC2MPS_RX0_PERR(1U)
+
+#define S_XGMAC2MPS_RX1_PERR    24
+#define V_XGMAC2MPS_RX1_PERR(x) ((x) << S_XGMAC2MPS_RX1_PERR)
+#define F_XGMAC2MPS_RX1_PERR    V_XGMAC2MPS_RX1_PERR(1U)
+
+#define S_MPS2CRYPTO_RX_INTF_FIFO    20
+#define M_MPS2CRYPTO_RX_INTF_FIFO    0xfU
+#define V_MPS2CRYPTO_RX_INTF_FIFO(x) ((x) << S_MPS2CRYPTO_RX_INTF_FIFO)
+#define G_MPS2CRYPTO_RX_INTF_FIFO(x) (((x) >> S_MPS2CRYPTO_RX_INTF_FIFO) & M_MPS2CRYPTO_RX_INTF_FIFO)
+
+#define S_RX_PRE_PROC_PERR    9
+#define M_RX_PRE_PROC_PERR    0x7ffU
+#define V_RX_PRE_PROC_PERR(x) ((x) << S_RX_PRE_PROC_PERR)
+#define G_RX_PRE_PROC_PERR(x) (((x) >> S_RX_PRE_PROC_PERR) & M_RX_PRE_PROC_PERR)
+
 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
+#define A_MPS_RX_PERR_INT_ENABLE2 0x11090
 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
+#define A_MPS_RX_PERR_ENABLE2 0x11094
 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
 #define A_MPS_RX_REPL_CTL 0x11098
 
@@ -35126,10 +44056,13 @@
 
 #define A_MPS_RX_PT_ARB1 0x110ac
 #define A_MPS_RX_PT_ARB2 0x110b0
+#define A_T7_MPS_RX_PT_ARB4 0x110b0
 #define A_MPS_RX_PT_ARB3 0x110b4
 #define A_T6_MPS_PF_OUT_EN 0x110b4
+#define A_T7_MPS_PF_OUT_EN 0x110b4
 #define A_MPS_RX_PT_ARB4 0x110b8
 #define A_T6_MPS_BMC_MTU 0x110b8
+#define A_T7_MPS_BMC_MTU 0x110b8
 #define A_MPS_PF_OUT_EN 0x110bc
 
 #define S_OUTEN    0
@@ -35138,6 +44071,7 @@
 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
 
 #define A_T6_MPS_BMC_PKT_CNT 0x110bc
+#define A_T7_MPS_BMC_PKT_CNT 0x110bc
 #define A_MPS_BMC_MTU 0x110c0
 
 #define S_MTU    0
@@ -35146,6 +44080,7 @@
 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
 
 #define A_T6_MPS_BMC_BYTE_CNT 0x110c0
+#define A_T7_MPS_BMC_BYTE_CNT 0x110c0
 #define A_MPS_BMC_PKT_CNT 0x110c4
 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
 
@@ -35154,6 +44089,7 @@
 #define V_T6_PFVF(x) ((x) << S_T6_PFVF)
 #define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF)
 
+#define A_T7_MPS_PFVF_ATRB_CTL 0x110c4
 #define A_MPS_BMC_BYTE_CNT 0x110c8
 #define A_T6_MPS_PFVF_ATRB 0x110c8
 
@@ -35161,6 +44097,12 @@
 #define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE)
 #define F_FULL_FRAME_MODE    V_FULL_FRAME_MODE(1U)
 
+#define A_T7_MPS_PFVF_ATRB 0x110c8
+
+#define S_EXTRACT_DEL_VLAN    31
+#define V_EXTRACT_DEL_VLAN(x) ((x) << S_EXTRACT_DEL_VLAN)
+#define F_EXTRACT_DEL_VLAN    V_EXTRACT_DEL_VLAN(1U)
+
 #define A_MPS_PFVF_ATRB_CTL 0x110cc
 
 #define S_RD_WRN    31
@@ -35173,6 +44115,7 @@
 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
 
 #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
+#define A_T7_MPS_PFVF_ATRB_FLTR0 0x110cc
 #define A_MPS_PFVF_ATRB 0x110d0
 
 #define S_ATTR_PF    28
@@ -35193,6 +44136,7 @@
 #define F_ATTR_MODE    V_ATTR_MODE(1U)
 
 #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
+#define A_T7_MPS_PFVF_ATRB_FLTR1 0x110d0
 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
 
 #define S_VLAN_EN    16
@@ -35205,36 +44149,58 @@
 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
 
 #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
+#define A_T7_MPS_PFVF_ATRB_FLTR2 0x110d4
 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
+#define A_T7_MPS_PFVF_ATRB_FLTR3 0x110d8
 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
 #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
+#define A_T7_MPS_PFVF_ATRB_FLTR4 0x110dc
 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
+#define A_T7_MPS_PFVF_ATRB_FLTR5 0x110e0
 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
+#define A_T7_MPS_PFVF_ATRB_FLTR6 0x110e4
 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
+#define A_T7_MPS_PFVF_ATRB_FLTR7 0x110e8
 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
 #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
+#define A_T7_MPS_PFVF_ATRB_FLTR8 0x110ec
 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
+#define A_T7_MPS_PFVF_ATRB_FLTR9 0x110f0
 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
+#define A_T7_MPS_PFVF_ATRB_FLTR10 0x110f4
 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
+#define A_T7_MPS_PFVF_ATRB_FLTR11 0x110f8
 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
 #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
+#define A_T7_MPS_PFVF_ATRB_FLTR12 0x110fc
 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
+#define A_T7_MPS_PFVF_ATRB_FLTR13 0x11100
 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
+#define A_T7_MPS_PFVF_ATRB_FLTR14 0x11104
 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
+#define A_T7_MPS_PFVF_ATRB_FLTR15 0x11108
 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
 #define A_T6_MPS_RPLC_MAP_CTL 0x1110c
+#define A_T7_MPS_RPLC_MAP_CTL 0x1110c
+
+#define S_T7_RPLC_MAP_ADDR    0
+#define M_T7_RPLC_MAP_ADDR    0xfffU
+#define V_T7_RPLC_MAP_ADDR(x) ((x) << S_T7_RPLC_MAP_ADDR)
+#define G_T7_RPLC_MAP_ADDR(x) (((x) >> S_T7_RPLC_MAP_ADDR) & M_T7_RPLC_MAP_ADDR)
+
 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
 #define A_T6_MPS_PF_RPLCT_MAP 0x11110
+#define A_T7_MPS_PF_RPLCT_MAP 0x11110
 #define A_MPS_RPLC_MAP_CTL 0x11114
 
 #define S_RPLC_MAP_ADDR    0
@@ -35243,6 +44209,7 @@
 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
 
 #define A_T6_MPS_VF_RPLCT_MAP0 0x11114
+#define A_T7_MPS_VF_RPLCT_MAP0 0x11114
 #define A_MPS_PF_RPLCT_MAP 0x11118
 
 #define S_PF_EN    0
@@ -35251,10 +44218,13 @@
 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
 
 #define A_T6_MPS_VF_RPLCT_MAP1 0x11118
+#define A_T7_MPS_VF_RPLCT_MAP1 0x11118
 #define A_MPS_VF_RPLCT_MAP0 0x1111c
 #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
+#define A_T7_MPS_VF_RPLCT_MAP2 0x1111c
 #define A_MPS_VF_RPLCT_MAP1 0x11120
 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120
+#define A_T7_MPS_VF_RPLCT_MAP3 0x11120
 #define A_MPS_VF_RPLCT_MAP2 0x11124
 #define A_MPS_VF_RPLCT_MAP3 0x11128
 #define A_MPS_MEM_DBG_CTL 0x1112c
@@ -35629,9 +44599,13 @@
 #define V_CONG_TH(x) ((x) << S_CONG_TH)
 #define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH)
 
+#define A_MPS_RX_LPBK_BG_PG_CNT2 0x11220
 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
+#define A_MPS_RX_LPBK_BG_PG_CNT3 0x11224
 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
+#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11228
 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
+#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG1 0x1122c
 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
 
 #define S_NVGRE_EN    9
@@ -35647,6 +44621,7 @@
 #define V_GRE(x) ((x) << S_GRE)
 #define G_GRE(x) (((x) >> S_GRE) & M_GRE)
 
+#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11230
 #define A_MPS_RX_VXLAN_TYPE 0x11234
 
 #define S_VXLAN_EN    16
@@ -35658,6 +44633,7 @@
 #define V_VXLAN(x) ((x) << S_VXLAN)
 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
 
+#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG3 0x11234
 #define A_MPS_RX_GENEVE_TYPE 0x11238
 
 #define S_GENEVE_EN    16
@@ -35669,12 +44645,14 @@
 #define V_GENEVE(x) ((x) << S_GENEVE)
 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
 
+#define A_T7_MPS_RX_GRE_PROT_TYPE 0x11238
 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
 
 #define S_T6_IVLAN_EN    16
 #define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN)
 #define F_T6_IVLAN_EN    V_T6_IVLAN_EN(1U)
 
+#define A_T7_MPS_RX_VXLAN_TYPE 0x1123c
 #define A_MPS_RX_ENCAP_NVGRE 0x11240
 
 #define S_ETYPE_EN    16
@@ -35686,13 +44664,9 @@
 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
 
+#define A_T7_MPS_RX_GENEVE_TYPE 0x11240
 #define A_MPS_RX_ENCAP_GENEVE 0x11244
-
-#define S_T6_ETYPE    0
-#define M_T6_ETYPE    0xffffU
-#define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
-#define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
-
+#define A_T7_MPS_RX_INNER_HDR_IVLAN 0x11244
 #define A_MPS_RX_TCP 0x11248
 
 #define S_PROT_TYPE_EN    8
@@ -35704,8 +44678,11 @@
 #define V_PROT_TYPE(x) ((x) << S_PROT_TYPE)
 #define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE)
 
+#define A_T7_MPS_RX_ENCAP_NVGRE 0x11248
 #define A_MPS_RX_UDP 0x1124c
+#define A_T7_MPS_RX_ENCAP_GENEVE 0x1124c
 #define A_MPS_RX_PAUSE 0x11250
+#define A_T7_MPS_RX_TCP 0x11250
 #define A_MPS_RX_LENGTH 0x11254
 
 #define S_SAP_VALUE    16
@@ -35718,6 +44695,7 @@
 #define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE)
 #define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE)
 
+#define A_T7_MPS_RX_UDP 0x11254
 #define A_MPS_RX_CTL_ORG 0x11258
 
 #define S_CTL_VALUE    24
@@ -35730,6 +44708,7 @@
 #define V_ORG_VALUE(x) ((x) << S_ORG_VALUE)
 #define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE)
 
+#define A_T7_MPS_RX_PAUSE 0x11258
 #define A_MPS_RX_IPV4 0x1125c
 
 #define S_ETYPE_IPV4    0
@@ -35737,6 +44716,7 @@
 #define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4)
 #define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4)
 
+#define A_T7_MPS_RX_LENGTH 0x1125c
 #define A_MPS_RX_IPV6 0x11260
 
 #define S_ETYPE_IPV6    0
@@ -35744,6 +44724,7 @@
 #define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6)
 #define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6)
 
+#define A_T7_MPS_RX_CTL_ORG 0x11260
 #define A_MPS_RX_TTL 0x11264
 
 #define S_TTL_IPV4    10
@@ -35764,6 +44745,7 @@
 #define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6)
 #define F_TTL_CHK_EN_IPV6    V_TTL_CHK_EN_IPV6(1U)
 
+#define A_T7_MPS_RX_IPV4 0x11264
 #define A_MPS_RX_DEFAULT_VNI 0x11268
 
 #define S_VNI    0
@@ -35771,6 +44753,7 @@
 #define V_VNI(x) ((x) << S_VNI)
 #define G_VNI(x) (((x) >> S_VNI) & M_VNI)
 
+#define A_T7_MPS_RX_IPV6 0x11268
 #define A_MPS_RX_PRS_CTL 0x1126c
 
 #define S_CTL_CHK_EN    28
@@ -35821,6 +44804,7 @@
 #define V_DIP_EN(x) ((x) << S_DIP_EN)
 #define F_DIP_EN    V_DIP_EN(1U)
 
+#define A_T7_MPS_RX_TTL 0x1126c
 #define A_MPS_RX_PRS_CTL_2 0x11270
 
 #define S_EN_UDP_CSUM_CHK    4
@@ -35843,7 +44827,9 @@
 #define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT)
 #define F_T6_IPV6_UDP_CSUM_COMPAT    V_T6_IPV6_UDP_CSUM_COMPAT(1U)
 
+#define A_T7_MPS_RX_DEFAULT_VNI 0x11270
 #define A_MPS_RX_MPS2NCSI_CNT 0x11274
+#define A_T7_MPS_RX_PRS_CTL 0x11274
 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
 
 #define S_T6_LEN    0
@@ -35851,38 +44837,222 @@
 #define V_T6_LEN(x) ((x) << S_T6_LEN)
 #define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN)
 
+#define A_T7_MPS_RX_PRS_CTL_2 0x11278
+
+#define S_IP_EXT_HDR_EN    5
+#define V_IP_EXT_HDR_EN(x) ((x) << S_IP_EXT_HDR_EN)
+#define F_IP_EXT_HDR_EN    V_IP_EXT_HDR_EN(1U)
+
 #define A_MPS_RX_PAUSE_DA_H 0x1127c
+#define A_T7_MPS_RX_MPS2NCSI_CNT 0x1127c
 #define A_MPS_RX_PAUSE_DA_L 0x11280
+#define A_T7_MPS_RX_MAX_TNL_HDR_LEN 0x11280
+
+#define S_MPS_TNL_HDR_LEN_MODE    9
+#define V_MPS_TNL_HDR_LEN_MODE(x) ((x) << S_MPS_TNL_HDR_LEN_MODE)
+#define F_MPS_TNL_HDR_LEN_MODE    V_MPS_TNL_HDR_LEN_MODE(1U)
+
+#define S_MPS_MAX_TNL_HDR_LEN    0
+#define M_MPS_MAX_TNL_HDR_LEN    0x1ffU
+#define V_MPS_MAX_TNL_HDR_LEN(x) ((x) << S_MPS_MAX_TNL_HDR_LEN)
+#define G_MPS_MAX_TNL_HDR_LEN(x) (((x) >> S_MPS_MAX_TNL_HDR_LEN) & M_MPS_MAX_TNL_HDR_LEN)
+
 #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
+#define A_T7_MPS_RX_PAUSE_DA_H 0x11284
 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
+#define A_T7_MPS_RX_PAUSE_DA_L 0x11288
 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
+#define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC0 0x1128c
 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
+#define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11290
 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
+#define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC0 0x11294
 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
+#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11298
 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
+#define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC1 0x1129c
 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
+#define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC1 0x112a0
 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
+#define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC1 0x112a4
 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
+#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a8
 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
+#define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112ac
 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
+#define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112b0
 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
+#define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112b4
 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
+#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b8
 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
+#define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112bc
 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
+#define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112c0
 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
+#define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112c4
 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
+#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c8
 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
+#define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112cc
 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
+#define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112d0
 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
+#define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112d4
 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
+#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d8
 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
+#define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112dc
 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
+#define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112e0
+#define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112e4
+#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e8
+#define A_MPS_RX_ESP 0x112ec
+#define A_MPS_EN_LPBK_BLK_SNDR 0x112f0
+
+#define S_EN_CH3    3
+#define V_EN_CH3(x) ((x) << S_EN_CH3)
+#define F_EN_CH3    V_EN_CH3(1U)
+
+#define S_EN_CH2    2
+#define V_EN_CH2(x) ((x) << S_EN_CH2)
+#define F_EN_CH2    V_EN_CH2(1U)
+
+#define S_EN_CH1    1
+#define V_EN_CH1(x) ((x) << S_EN_CH1)
+#define F_EN_CH1    V_EN_CH1(1U)
+
+#define S_EN_CH0    0
+#define V_EN_CH0(x) ((x) << S_EN_CH0)
+#define F_EN_CH0    V_EN_CH0(1U)
+
 #define A_MPS_VF_RPLCT_MAP4 0x11300
 #define A_MPS_VF_RPLCT_MAP5 0x11304
 #define A_MPS_VF_RPLCT_MAP6 0x11308
 #define A_MPS_VF_RPLCT_MAP7 0x1130c
+#define A_MPS_RX_PERR_INT_CAUSE3 0x11310
+#define A_MPS_RX_PERR_INT_ENABLE3 0x11314
+#define A_MPS_RX_PERR_ENABLE3 0x11318
+#define A_MPS_RX_PERR_INT_CAUSE4 0x1131c
+
+#define S_CLS    20
+#define M_CLS    0x3fU
+#define V_CLS(x) ((x) << S_CLS)
+#define G_CLS(x) (((x) >> S_CLS) & M_CLS)
+
+#define S_RX_PRE_PROC    16
+#define M_RX_PRE_PROC    0xfU
+#define V_RX_PRE_PROC(x) ((x) << S_RX_PRE_PROC)
+#define G_RX_PRE_PROC(x) (((x) >> S_RX_PRE_PROC) & M_RX_PRE_PROC)
+
+#define S_PPROC3    12
+#define M_PPROC3    0xfU
+#define V_PPROC3(x) ((x) << S_PPROC3)
+#define G_PPROC3(x) (((x) >> S_PPROC3) & M_PPROC3)
+
+#define S_PPROC2    8
+#define M_PPROC2    0xfU
+#define V_PPROC2(x) ((x) << S_PPROC2)
+#define G_PPROC2(x) (((x) >> S_PPROC2) & M_PPROC2)
+
+#define S_PPROC1    4
+#define M_PPROC1    0xfU
+#define V_PPROC1(x) ((x) << S_PPROC1)
+#define G_PPROC1(x) (((x) >> S_PPROC1) & M_PPROC1)
+
+#define S_PPROC0    0
+#define M_PPROC0    0xfU
+#define V_PPROC0(x) ((x) << S_PPROC0)
+#define G_PPROC0(x) (((x) >> S_PPROC0) & M_PPROC0)
+
+#define A_MPS_RX_PERR_INT_ENABLE4 0x11320
+#define A_MPS_RX_PERR_ENABLE4 0x11324
+#define A_MPS_RX_PERR_INT_CAUSE5 0x11328
+
+#define S_MPS2CRYP_RX_FIFO    26
+#define M_MPS2CRYP_RX_FIFO    0xfU
+#define V_MPS2CRYP_RX_FIFO(x) ((x) << S_MPS2CRYP_RX_FIFO)
+#define G_MPS2CRYP_RX_FIFO(x) (((x) >> S_MPS2CRYP_RX_FIFO) & M_MPS2CRYP_RX_FIFO)
+
+#define S_RX_OUT    20
+#define M_RX_OUT    0x3fU
+#define V_RX_OUT(x) ((x) << S_RX_OUT)
+#define G_RX_OUT(x) (((x) >> S_RX_OUT) & M_RX_OUT)
+
+#define S_MEM_WRAP    0
+#define M_MEM_WRAP    0xfffffU
+#define V_MEM_WRAP(x) ((x) << S_MEM_WRAP)
+#define G_MEM_WRAP(x) (((x) >> S_MEM_WRAP) & M_MEM_WRAP)
+
+#define A_MPS_RX_PERR_INT_ENABLE5 0x1132c
+#define A_MPS_RX_PERR_ENABLE5 0x11330
+#define A_MPS_RX_PERR_INT_CAUSE6 0x11334
+
+#define S_MPS_RX_MEM_WRAP    0
+#define M_MPS_RX_MEM_WRAP    0x1ffffffU
+#define V_MPS_RX_MEM_WRAP(x) ((x) << S_MPS_RX_MEM_WRAP)
+#define G_MPS_RX_MEM_WRAP(x) (((x) >> S_MPS_RX_MEM_WRAP) & M_MPS_RX_MEM_WRAP)
+
+#define A_MPS_RX_PERR_INT_ENABLE6 0x11338
+#define A_MPS_RX_PERR_ENABLE6 0x1133c
+#define A_MPS_RX_CNT_NVGRE_PKT_MAC2 0x11408
+#define A_MPS_RX_CNT_VXLAN_PKT_MAC2 0x1140c
+#define A_MPS_RX_CNT_GENEVE_PKT_MAC2 0x11410
+#define A_MPS_RX_CNT_TNL_ERR_PKT_MAC2 0x11414
+#define A_MPS_RX_CNT_NVGRE_PKT_MAC3 0x11418
+#define A_MPS_RX_CNT_VXLAN_PKT_MAC3 0x1141c
+#define A_MPS_RX_CNT_GENEVE_PKT_MAC3 0x11420
+#define A_MPS_RX_CNT_TNL_ERR_PKT_MAC3 0x11424
+#define A_MPS_RX_CNT_NVGRE_PKT_LPBK2 0x11428
+#define A_MPS_RX_CNT_VXLAN_PKT_LPBK2 0x1142c
+#define A_MPS_RX_CNT_GENEVE_PKT_LPBK2 0x11430
+#define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK2 0x11434
+#define A_MPS_RX_CNT_NVGRE_PKT_LPBK3 0x11438
+#define A_MPS_RX_CNT_VXLAN_PKT_LPBK3 0x1143c
+#define A_MPS_RX_CNT_GENEVE_PKT_LPBK3 0x11440
+#define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK3 0x11444
+#define A_MPS_RX_CNT_NVGRE_PKT_TO_TP2 0x11448
+#define A_MPS_RX_CNT_VXLAN_PKT_TO_TP2 0x1144c
+#define A_MPS_RX_CNT_GENEVE_PKT_TO_TP2 0x11450
+#define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP2 0x11454
+#define A_MPS_RX_CNT_NVGRE_PKT_TO_TP3 0x11458
+#define A_MPS_RX_CNT_VXLAN_PKT_TO_TP3 0x1145c
+#define A_MPS_RX_CNT_GENEVE_PKT_TO_TP3 0x11460
+#define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP3 0x11464
+#define A_T7_MPS_RX_PT_ARB2 0x11468
+#define A_T7_MPS_RX_PT_ARB3 0x1146c
 #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
+#define A_MPS_CLS_DIP_ID_TABLE_CTL 0x12000
+
+#define S_DIP_VLD    12
+#define V_DIP_VLD(x) ((x) << S_DIP_VLD)
+#define F_DIP_VLD    V_DIP_VLD(1U)
+
+#define S_DIP_TYPE    11
+#define V_DIP_TYPE(x) ((x) << S_DIP_TYPE)
+#define F_DIP_TYPE    V_DIP_TYPE(1U)
+
+#define S_DIP_WRN    10
+#define V_DIP_WRN(x) ((x) << S_DIP_WRN)
+#define F_DIP_WRN    V_DIP_WRN(1U)
+
+#define S_DIP_SEG    8
+#define M_DIP_SEG    0x3U
+#define V_DIP_SEG(x) ((x) << S_DIP_SEG)
+#define G_DIP_SEG(x) (((x) >> S_DIP_SEG) & M_DIP_SEG)
+
+#define S_DIP_TBL_RSVD1    5
+#define M_DIP_TBL_RSVD1    0x7U
+#define V_DIP_TBL_RSVD1(x) ((x) << S_DIP_TBL_RSVD1)
+#define G_DIP_TBL_RSVD1(x) (((x) >> S_DIP_TBL_RSVD1) & M_DIP_TBL_RSVD1)
+
+#define S_DIP_TBL_ADDR    0
+#define M_DIP_TBL_ADDR    0x1fU
+#define V_DIP_TBL_ADDR(x) ((x) << S_DIP_TBL_ADDR)
+#define G_DIP_TBL_ADDR(x) (((x) >> S_DIP_TBL_ADDR) & M_DIP_TBL_ADDR)
+
 #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
+#define A_MPS_CLS_DIP_ID_TABLE_DATA 0x12004
 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
@@ -35892,6 +45062,226 @@
 #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
 #define A_MPS_RX_HASH_LKP_TABLE 0x12060
+#define A_MPS_CLS_DROP_DMAC0_L 0x12070
+#define A_MPS_CLS_DROP_DMAC0_H 0x12074
+
+#define S_DMAC    0
+#define M_DMAC    0xffffU
+#define V_DMAC(x) ((x) << S_DMAC)
+#define G_DMAC(x) (((x) >> S_DMAC) & M_DMAC)
+
+#define A_MPS_CLS_DROP_DMAC1_L 0x12078
+#define A_MPS_CLS_DROP_DMAC1_H 0x1207c
+#define A_MPS_CLS_DROP_DMAC2_L 0x12080
+#define A_MPS_CLS_DROP_DMAC2_H 0x12084
+#define A_MPS_CLS_DROP_DMAC3_L 0x12088
+#define A_MPS_CLS_DROP_DMAC3_H 0x1208c
+#define A_MPS_CLS_DROP_DMAC4_L 0x12090
+#define A_MPS_CLS_DROP_DMAC4_H 0x12094
+#define A_MPS_CLS_DROP_DMAC5_L 0x12098
+#define A_MPS_CLS_DROP_DMAC5_H 0x1209c
+#define A_MPS_CLS_DROP_DMAC6_L 0x120a0
+#define A_MPS_CLS_DROP_DMAC6_H 0x120a4
+#define A_MPS_CLS_DROP_DMAC7_L 0x120a8
+#define A_MPS_CLS_DROP_DMAC7_H 0x120ac
+#define A_MPS_CLS_DROP_DMAC8_L 0x120b0
+#define A_MPS_CLS_DROP_DMAC8_H 0x120b4
+#define A_MPS_CLS_DROP_DMAC9_L 0x120b8
+#define A_MPS_CLS_DROP_DMAC9_H 0x120bc
+#define A_MPS_CLS_DROP_DMAC10_L 0x120c0
+#define A_MPS_CLS_DROP_DMAC10_H 0x120c4
+#define A_MPS_CLS_DROP_DMAC11_L 0x120c8
+#define A_MPS_CLS_DROP_DMAC11_H 0x120cc
+#define A_MPS_CLS_DROP_DMAC12_L 0x120d0
+#define A_MPS_CLS_DROP_DMAC12_H 0x120d4
+#define A_MPS_CLS_DROP_DMAC13_L 0x120d8
+#define A_MPS_CLS_DROP_DMAC13_H 0x120dc
+#define A_MPS_CLS_DROP_DMAC14_L 0x120e0
+#define A_MPS_CLS_DROP_DMAC14_H 0x120e4
+#define A_MPS_CLS_DROP_DMAC15_L 0x120e8
+#define A_MPS_CLS_DROP_DMAC15_H 0x120ec
+#define A_MPS_RX_ENCAP_VXLAN 0x120f0
+#define A_MPS_RX_INT_VXLAN 0x120f4
+
+#define S_INT_TYPE_EN    16
+#define V_INT_TYPE_EN(x) ((x) << S_INT_TYPE_EN)
+#define F_INT_TYPE_EN    V_INT_TYPE_EN(1U)
+
+#define S_INT_TYPE    0
+#define M_INT_TYPE    0xffffU
+#define V_INT_TYPE(x) ((x) << S_INT_TYPE)
+#define G_INT_TYPE(x) (((x) >> S_INT_TYPE) & M_INT_TYPE)
+
+#define A_MPS_RX_INT_GENEVE 0x120f8
+#define A_MPS_PFVF_ATRB2 0x120fc
+
+#define S_EXTRACT_DEL_ENCAP    31
+#define V_EXTRACT_DEL_ENCAP(x) ((x) << S_EXTRACT_DEL_ENCAP)
+#define F_EXTRACT_DEL_ENCAP    V_EXTRACT_DEL_ENCAP(1U)
+
+#define A_MPS_RX_TRANS_ENCAP_FLTR_CTL 0x12100
+
+#define S_TIMEOUT_FLT_CLR_EN    8
+#define V_TIMEOUT_FLT_CLR_EN(x) ((x) << S_TIMEOUT_FLT_CLR_EN)
+#define F_TIMEOUT_FLT_CLR_EN    V_TIMEOUT_FLT_CLR_EN(1U)
+
+#define S_FLTR_TIMOUT_VAL    0
+#define M_FLTR_TIMOUT_VAL    0xffU
+#define V_FLTR_TIMOUT_VAL(x) ((x) << S_FLTR_TIMOUT_VAL)
+#define G_FLTR_TIMOUT_VAL(x) (((x) >> S_FLTR_TIMOUT_VAL) & M_FLTR_TIMOUT_VAL)
+
+#define A_T7_MPS_RX_PAUSE_GEN_TH_0_0 0x12104
+#define A_T7_MPS_RX_PAUSE_GEN_TH_0_1 0x12108
+#define A_T7_MPS_RX_PAUSE_GEN_TH_0_2 0x1210c
+#define A_T7_MPS_RX_PAUSE_GEN_TH_0_3 0x12110
+#define A_MPS_RX_PAUSE_GEN_TH_0_4 0x12114
+#define A_MPS_RX_PAUSE_GEN_TH_0_5 0x12118
+#define A_MPS_RX_PAUSE_GEN_TH_0_6 0x1211c
+#define A_MPS_RX_PAUSE_GEN_TH_0_7 0x12120
+#define A_T7_MPS_RX_PAUSE_GEN_TH_1_0 0x12124
+#define A_T7_MPS_RX_PAUSE_GEN_TH_1_1 0x12128
+#define A_T7_MPS_RX_PAUSE_GEN_TH_1_2 0x1212c
+#define A_T7_MPS_RX_PAUSE_GEN_TH_1_3 0x12130
+#define A_MPS_RX_PAUSE_GEN_TH_1_4 0x12134
+#define A_MPS_RX_PAUSE_GEN_TH_1_5 0x12138
+#define A_MPS_RX_PAUSE_GEN_TH_1_6 0x1213c
+#define A_MPS_RX_PAUSE_GEN_TH_1_7 0x12140
+#define A_T7_MPS_RX_PAUSE_GEN_TH_2_0 0x12144
+#define A_T7_MPS_RX_PAUSE_GEN_TH_2_1 0x12148
+#define A_T7_MPS_RX_PAUSE_GEN_TH_2_2 0x1214c
+#define A_T7_MPS_RX_PAUSE_GEN_TH_2_3 0x12150
+#define A_MPS_RX_PAUSE_GEN_TH_2_4 0x12154
+#define A_MPS_RX_PAUSE_GEN_TH_2_5 0x12158
+#define A_MPS_RX_PAUSE_GEN_TH_2_6 0x1215c
+#define A_MPS_RX_PAUSE_GEN_TH_2_7 0x12160
+#define A_T7_MPS_RX_PAUSE_GEN_TH_3_0 0x12164
+#define A_T7_MPS_RX_PAUSE_GEN_TH_3_1 0x12168
+#define A_T7_MPS_RX_PAUSE_GEN_TH_3_2 0x1216c
+#define A_T7_MPS_RX_PAUSE_GEN_TH_3_3 0x12170
+#define A_MPS_RX_PAUSE_GEN_TH_3_4 0x12174
+#define A_MPS_RX_PAUSE_GEN_TH_3_5 0x12178
+#define A_MPS_RX_PAUSE_GEN_TH_3_6 0x1217c
+#define A_MPS_RX_PAUSE_GEN_TH_3_7 0x12180
+#define A_MPS_RX_DROP_0_0 0x12184
+
+#define S_DROP_TH    0
+#define M_DROP_TH    0xffffU
+#define V_DROP_TH(x) ((x) << S_DROP_TH)
+#define G_DROP_TH(x) (((x) >> S_DROP_TH) & M_DROP_TH)
+
+#define A_MPS_RX_DROP_0_1 0x12188
+#define A_MPS_RX_DROP_0_2 0x1218c
+#define A_MPS_RX_DROP_0_3 0x12190
+#define A_MPS_RX_DROP_0_4 0x12194
+#define A_MPS_RX_DROP_0_5 0x12198
+#define A_MPS_RX_DROP_0_6 0x1219c
+#define A_MPS_RX_DROP_0_7 0x121a0
+#define A_MPS_RX_DROP_1_0 0x121a4
+#define A_MPS_RX_DROP_1_1 0x121a8
+#define A_MPS_RX_DROP_1_2 0x121ac
+#define A_MPS_RX_DROP_1_3 0x121b0
+#define A_MPS_RX_DROP_1_4 0x121b4
+#define A_MPS_RX_DROP_1_5 0x121b8
+#define A_MPS_RX_DROP_1_6 0x121bc
+#define A_MPS_RX_DROP_1_7 0x121c0
+#define A_MPS_RX_DROP_2_0 0x121c4
+#define A_MPS_RX_DROP_2_1 0x121c8
+#define A_MPS_RX_DROP_2_2 0x121cc
+#define A_MPS_RX_DROP_2_3 0x121d0
+#define A_MPS_RX_DROP_2_4 0x121d4
+#define A_MPS_RX_DROP_2_5 0x121d8
+#define A_MPS_RX_DROP_2_6 0x121dc
+#define A_MPS_RX_DROP_2_7 0x121e0
+#define A_MPS_RX_DROP_3_0 0x121e4
+#define A_MPS_RX_DROP_3_1 0x121e8
+#define A_MPS_RX_DROP_3_2 0x121ec
+#define A_MPS_RX_DROP_3_3 0x121f0
+#define A_MPS_RX_DROP_3_4 0x121f4
+#define A_MPS_RX_DROP_3_5 0x121f8
+#define A_MPS_RX_DROP_3_6 0x121fc
+#define A_MPS_RX_DROP_3_7 0x12200
+#define A_MPS_RX_MAC_BG_PG_CNT0_0 0x12204
+#define A_MPS_RX_MAC_BG_PG_CNT0_1 0x12208
+#define A_MPS_RX_MAC_BG_PG_CNT0_2 0x1220c
+#define A_MPS_RX_MAC_BG_PG_CNT0_3 0x12210
+#define A_MPS_RX_MAC_BG_PG_CNT0_4 0x12214
+#define A_MPS_RX_MAC_BG_PG_CNT0_5 0x12218
+#define A_MPS_RX_MAC_BG_PG_CNT0_6 0x1221c
+#define A_MPS_RX_MAC_BG_PG_CNT0_7 0x12220
+#define A_MPS_RX_MAC_BG_PG_CNT1_0 0x12224
+#define A_MPS_RX_MAC_BG_PG_CNT1_1 0x12228
+#define A_MPS_RX_MAC_BG_PG_CNT1_2 0x1222c
+#define A_MPS_RX_MAC_BG_PG_CNT1_3 0x12230
+#define A_MPS_RX_MAC_BG_PG_CNT1_4 0x12234
+#define A_MPS_RX_MAC_BG_PG_CNT1_5 0x12238
+#define A_MPS_RX_MAC_BG_PG_CNT1_6 0x1223c
+#define A_MPS_RX_MAC_BG_PG_CNT1_7 0x12240
+#define A_MPS_RX_MAC_BG_PG_CNT2_0 0x12244
+#define A_MPS_RX_MAC_BG_PG_CNT2_1 0x12248
+#define A_MPS_RX_MAC_BG_PG_CNT2_2 0x1224c
+#define A_MPS_RX_MAC_BG_PG_CNT2_3 0x12250
+#define A_MPS_RX_MAC_BG_PG_CNT2_4 0x12254
+#define A_MPS_RX_MAC_BG_PG_CNT2_5 0x12258
+#define A_MPS_RX_MAC_BG_PG_CNT2_6 0x1225c
+#define A_MPS_RX_MAC_BG_PG_CNT2_7 0x12260
+#define A_MPS_RX_MAC_BG_PG_CNT3_0 0x12264
+#define A_MPS_RX_MAC_BG_PG_CNT3_1 0x12268
+#define A_MPS_RX_MAC_BG_PG_CNT3_2 0x1226c
+#define A_MPS_RX_MAC_BG_PG_CNT3_3 0x12270
+#define A_MPS_RX_MAC_BG_PG_CNT3_4 0x12274
+#define A_MPS_RX_MAC_BG_PG_CNT3_5 0x12278
+#define A_MPS_RX_MAC_BG_PG_CNT3_6 0x1227c
+#define A_MPS_RX_MAC_BG_PG_CNT3_7 0x12280
+#define A_T7_MPS_RX_PAUSE_GEN_TH_0 0x12284
+#define A_T7_MPS_RX_PAUSE_GEN_TH_1 0x12288
+#define A_T7_MPS_RX_PAUSE_GEN_TH_2 0x1228c
+#define A_T7_MPS_RX_PAUSE_GEN_TH_3 0x12290
+#define A_MPS_RX_BG0_IPSEC_CNT 0x12294
+#define A_MPS_RX_BG1_IPSEC_CNT 0x12298
+#define A_MPS_RX_BG2_IPSEC_CNT 0x1229c
+#define A_MPS_RX_BG3_IPSEC_CNT 0x122a0
+#define A_MPS_RX_MEM_FIFO_CONFIG0 0x122a4
+
+#define S_FIFO_CONFIG2    16
+#define M_FIFO_CONFIG2    0xffffU
+#define V_FIFO_CONFIG2(x) ((x) << S_FIFO_CONFIG2)
+#define G_FIFO_CONFIG2(x) (((x) >> S_FIFO_CONFIG2) & M_FIFO_CONFIG2)
+
+#define S_FIFO_CONFIG1    0
+#define M_FIFO_CONFIG1    0xffffU
+#define V_FIFO_CONFIG1(x) ((x) << S_FIFO_CONFIG1)
+#define G_FIFO_CONFIG1(x) (((x) >> S_FIFO_CONFIG1) & M_FIFO_CONFIG1)
+
+#define A_MPS_RX_MEM_FIFO_CONFIG1 0x122a8
+
+#define S_FIFO_CONFIG3    0
+#define M_FIFO_CONFIG3    0xffffU
+#define V_FIFO_CONFIG3(x) ((x) << S_FIFO_CONFIG3)
+#define G_FIFO_CONFIG3(x) (((x) >> S_FIFO_CONFIG3) & M_FIFO_CONFIG3)
+
+#define A_MPS_LPBK_MEM_FIFO_CONFIG0 0x122ac
+#define A_MPS_LPBK_MEM_FIFO_CONFIG1 0x122b0
+#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG0 0x122b4
+#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG1 0x122b8
+#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG2 0x122bc
+#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG3 0x122c0
+#define A_MPS_BG_PAUSE_CTL 0x122c4
+
+#define S_BG0_PAUSE_EN    3
+#define V_BG0_PAUSE_EN(x) ((x) << S_BG0_PAUSE_EN)
+#define F_BG0_PAUSE_EN    V_BG0_PAUSE_EN(1U)
+
+#define S_BG1_PAUSE_EN    2
+#define V_BG1_PAUSE_EN(x) ((x) << S_BG1_PAUSE_EN)
+#define F_BG1_PAUSE_EN    V_BG1_PAUSE_EN(1U)
+
+#define S_BG2_PAUSE_EN    1
+#define V_BG2_PAUSE_EN(x) ((x) << S_BG2_PAUSE_EN)
+#define F_BG2_PAUSE_EN    V_BG2_PAUSE_EN(1U)
+
+#define S_BG3_PAUSE_EN    0
+#define V_BG3_PAUSE_EN(x) ((x) << S_BG3_PAUSE_EN)
+#define F_BG3_PAUSE_EN    V_BG3_PAUSE_EN(1U)
 
 /* registers for module CPL_SWITCH */
 #define CPL_SWITCH_BASE_ADDR 0x19040
@@ -35931,6 +45321,7 @@
 #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
 #define F_CIM_SPLIT_ENABLE    V_CIM_SPLIT_ENABLE(1U)
 
+#define A_CNTRL 0x19040
 #define A_CPL_SWITCH_TBL_IDX 0x19044
 
 #define S_SWITCH_TBL_IDX    0
@@ -35938,7 +45329,9 @@
 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
 
+#define A_TBL_IDX 0x19044
 #define A_CPL_SWITCH_TBL_DATA 0x19048
+#define A_TBL_DATA 0x19048
 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
 
 #define S_ZERO_CMD_CH1    8
@@ -35951,6 +45344,18 @@
 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
 
+#define A_ZERO_ERROR 0x1904c
+
+#define S_ZERO_CMD_CH3    24
+#define M_ZERO_CMD_CH3    0xffU
+#define V_ZERO_CMD_CH3(x) ((x) << S_ZERO_CMD_CH3)
+#define G_ZERO_CMD_CH3(x) (((x) >> S_ZERO_CMD_CH3) & M_ZERO_CMD_CH3)
+
+#define S_ZERO_CMD_CH2    16
+#define M_ZERO_CMD_CH2    0xffU
+#define V_ZERO_CMD_CH2(x) ((x) << S_ZERO_CMD_CH2)
+#define G_ZERO_CMD_CH2(x) (((x) >> S_ZERO_CMD_CH2) & M_ZERO_CMD_CH2)
+
 #define A_CPL_INTR_ENABLE 0x19050
 
 #define S_CIM_OP_MAP_PERR    5
@@ -35985,7 +45390,18 @@
 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
 #define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)
 
+#define A_INTR_ENABLE 0x19050
+
+#define S_PERR_CPL_128TO128_3    9
+#define V_PERR_CPL_128TO128_3(x) ((x) << S_PERR_CPL_128TO128_3)
+#define F_PERR_CPL_128TO128_3    V_PERR_CPL_128TO128_3(1U)
+
+#define S_PERR_CPL_128TO128_2    8
+#define V_PERR_CPL_128TO128_2(x) ((x) << S_PERR_CPL_128TO128_2)
+#define F_PERR_CPL_128TO128_2    V_PERR_CPL_128TO128_2(1U)
+
 #define A_CPL_INTR_CAUSE 0x19054
+#define A_INTR_CAUSE 0x19054
 #define A_CPL_MAP_TBL_IDX 0x19058
 
 #define S_MAP_TBL_IDX    0
@@ -35997,6 +45413,13 @@
 #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
 #define F_CIM_SPLIT_OPCODE_PROGRAM    V_CIM_SPLIT_OPCODE_PROGRAM(1U)
 
+#define A_MAP_TBL_IDX 0x19058
+
+#define S_CPL_MAP_TBL_SEL    9
+#define M_CPL_MAP_TBL_SEL    0x3U
+#define V_CPL_MAP_TBL_SEL(x) ((x) << S_CPL_MAP_TBL_SEL)
+#define G_CPL_MAP_TBL_SEL(x) (((x) >> S_CPL_MAP_TBL_SEL) & M_CPL_MAP_TBL_SEL)
+
 #define A_CPL_MAP_TBL_DATA 0x1905c
 
 #define S_MAP_TBL_DATA    0
@@ -36004,6 +45427,8 @@
 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
 
+#define A_MAP_TBL_DATA 0x1905c
+
 /* registers for module SMB */
 #define SMB_BASE_ADDR 0x19060
 
@@ -36019,6 +45444,16 @@
 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
 
+#define S_T7_MACROCNTCFG    12
+#define M_T7_MACROCNTCFG    0x1fU
+#define V_T7_MACROCNTCFG(x) ((x) << S_T7_MACROCNTCFG)
+#define G_T7_MACROCNTCFG(x) (((x) >> S_T7_MACROCNTCFG) & M_T7_MACROCNTCFG)
+
+#define S_T7_MICROCNTCFG    0
+#define M_T7_MICROCNTCFG    0xfffU
+#define V_T7_MICROCNTCFG(x) ((x) << S_T7_MICROCNTCFG)
+#define G_T7_MICROCNTCFG(x) (((x) >> S_T7_MICROCNTCFG) & M_T7_MICROCNTCFG)
+
 #define A_SMB_MST_TIMEOUT_CFG 0x19064
 
 #define S_MSTTIMEOUTCFG    0
@@ -36685,6 +46120,26 @@
 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
 
+#define S_T7_STOPBITS    25
+#define M_T7_STOPBITS    0x3U
+#define V_T7_STOPBITS(x) ((x) << S_T7_STOPBITS)
+#define G_T7_STOPBITS(x) (((x) >> S_T7_STOPBITS) & M_T7_STOPBITS)
+
+#define S_T7_PARITY    23
+#define M_T7_PARITY    0x3U
+#define V_T7_PARITY(x) ((x) << S_T7_PARITY)
+#define G_T7_PARITY(x) (((x) >> S_T7_PARITY) & M_T7_PARITY)
+
+#define S_T7_DATABITS    19
+#define M_T7_DATABITS    0xfU
+#define V_T7_DATABITS(x) ((x) << S_T7_DATABITS)
+#define G_T7_DATABITS(x) (((x) >> S_T7_DATABITS) & M_T7_DATABITS)
+
+#define S_T7_UART_CLKDIV    0
+#define M_T7_UART_CLKDIV    0x3ffffU
+#define V_T7_UART_CLKDIV(x) ((x) << S_T7_UART_CLKDIV)
+#define G_T7_UART_CLKDIV(x) (((x) >> S_T7_UART_CLKDIV) & M_T7_UART_CLKDIV)
+
 /* registers for module PMU */
 #define PMU_BASE_ADDR 0x19120
 
@@ -36767,6 +46222,26 @@
 #define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK)
 #define F_PL_DIS_PRTY_CHK    V_PL_DIS_PRTY_CHK(1U)
 
+#define S_ARM_PART_CGEN    19
+#define V_ARM_PART_CGEN(x) ((x) << S_ARM_PART_CGEN)
+#define F_ARM_PART_CGEN    V_ARM_PART_CGEN(1U)
+
+#define S_CRYPTO_PART_CGEN    14
+#define V_CRYPTO_PART_CGEN(x) ((x) << S_CRYPTO_PART_CGEN)
+#define F_CRYPTO_PART_CGEN    V_CRYPTO_PART_CGEN(1U)
+
+#define S_NVME_PART_CGEN    9
+#define V_NVME_PART_CGEN(x) ((x) << S_NVME_PART_CGEN)
+#define F_NVME_PART_CGEN    V_NVME_PART_CGEN(1U)
+
+#define S_XP10_PART_CGEN    8
+#define V_XP10_PART_CGEN(x) ((x) << S_XP10_PART_CGEN)
+#define F_XP10_PART_CGEN    V_XP10_PART_CGEN(1U)
+
+#define S_GPEX_PART_CGEN    7
+#define V_GPEX_PART_CGEN(x) ((x) << S_GPEX_PART_CGEN)
+#define F_GPEX_PART_CGEN    V_GPEX_PART_CGEN(1U)
+
 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
 
 #define S_HWWAKEUPEN    5
@@ -36861,6 +46336,72 @@
 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
 
+#define S_ISCSI_PAGE_SIZE_CHK_ENB    31
+#define V_ISCSI_PAGE_SIZE_CHK_ENB(x) ((x) << S_ISCSI_PAGE_SIZE_CHK_ENB)
+#define F_ISCSI_PAGE_SIZE_CHK_ENB    V_ISCSI_PAGE_SIZE_CHK_ENB(1U)
+
+#define S_RDMA_0B_WR_OPCODE_HI    29
+#define V_RDMA_0B_WR_OPCODE_HI(x) ((x) << S_RDMA_0B_WR_OPCODE_HI)
+#define F_RDMA_0B_WR_OPCODE_HI    V_RDMA_0B_WR_OPCODE_HI(1U)
+
+#define S_RDMA_IMMEDIATE_CQE    28
+#define V_RDMA_IMMEDIATE_CQE(x) ((x) << S_RDMA_IMMEDIATE_CQE)
+#define F_RDMA_IMMEDIATE_CQE    V_RDMA_IMMEDIATE_CQE(1U)
+
+#define S_RDMA_ATOMIC_WR_RSP_CQE    27
+#define V_RDMA_ATOMIC_WR_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_WR_RSP_CQE)
+#define F_RDMA_ATOMIC_WR_RSP_CQE    V_RDMA_ATOMIC_WR_RSP_CQE(1U)
+
+#define S_RDMA_VERIFY_RSP_FLUSH    26
+#define V_RDMA_VERIFY_RSP_FLUSH(x) ((x) << S_RDMA_VERIFY_RSP_FLUSH)
+#define F_RDMA_VERIFY_RSP_FLUSH    V_RDMA_VERIFY_RSP_FLUSH(1U)
+
+#define S_RDMA_VERIFY_RSP_CQE    25
+#define V_RDMA_VERIFY_RSP_CQE(x) ((x) << S_RDMA_VERIFY_RSP_CQE)
+#define F_RDMA_VERIFY_RSP_CQE    V_RDMA_VERIFY_RSP_CQE(1U)
+
+#define S_RDMA_FLUSH_RSP_CQE    24
+#define V_RDMA_FLUSH_RSP_CQE(x) ((x) << S_RDMA_FLUSH_RSP_CQE)
+#define F_RDMA_FLUSH_RSP_CQE    V_RDMA_FLUSH_RSP_CQE(1U)
+
+#define S_RDMA_ATOMIC_RSP_CQE    23
+#define V_RDMA_ATOMIC_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_RSP_CQE)
+#define F_RDMA_ATOMIC_RSP_CQE    V_RDMA_ATOMIC_RSP_CQE(1U)
+
+#define S_T7_TPT_EXTENSION_MODE    22
+#define V_T7_TPT_EXTENSION_MODE(x) ((x) << S_T7_TPT_EXTENSION_MODE)
+#define F_T7_TPT_EXTENSION_MODE    V_T7_TPT_EXTENSION_MODE(1U)
+
+#define S_NVME_TCP_DDP_VAL_EN    21
+#define V_NVME_TCP_DDP_VAL_EN(x) ((x) << S_NVME_TCP_DDP_VAL_EN)
+#define F_NVME_TCP_DDP_VAL_EN    V_NVME_TCP_DDP_VAL_EN(1U)
+
+#define S_NVME_TCP_REMOVE_HDR_CRC    20
+#define V_NVME_TCP_REMOVE_HDR_CRC(x) ((x) << S_NVME_TCP_REMOVE_HDR_CRC)
+#define F_NVME_TCP_REMOVE_HDR_CRC    V_NVME_TCP_REMOVE_HDR_CRC(1U)
+
+#define S_NVME_TCP_LAST_PDU_CHECK_ENB    19
+#define V_NVME_TCP_LAST_PDU_CHECK_ENB(x) ((x) << S_NVME_TCP_LAST_PDU_CHECK_ENB)
+#define F_NVME_TCP_LAST_PDU_CHECK_ENB    V_NVME_TCP_LAST_PDU_CHECK_ENB(1U)
+
+#define S_NVME_TCP_OFFSET_SUBMODE    17
+#define M_NVME_TCP_OFFSET_SUBMODE    0x3U
+#define V_NVME_TCP_OFFSET_SUBMODE(x) ((x) << S_NVME_TCP_OFFSET_SUBMODE)
+#define G_NVME_TCP_OFFSET_SUBMODE(x) (((x) >> S_NVME_TCP_OFFSET_SUBMODE) & M_NVME_TCP_OFFSET_SUBMODE)
+
+#define S_NVME_TCP_OFFSET_MODE    16
+#define V_NVME_TCP_OFFSET_MODE(x) ((x) << S_NVME_TCP_OFFSET_MODE)
+#define F_NVME_TCP_OFFSET_MODE    V_NVME_TCP_OFFSET_MODE(1U)
+
+#define S_QPID_CHECK_DISABLE_FOR_SEND    15
+#define V_QPID_CHECK_DISABLE_FOR_SEND(x) ((x) << S_QPID_CHECK_DISABLE_FOR_SEND)
+#define F_QPID_CHECK_DISABLE_FOR_SEND    V_QPID_CHECK_DISABLE_FOR_SEND(1U)
+
+#define S_RDMA_0B_WR_OPCODE_LO    10
+#define M_RDMA_0B_WR_OPCODE_LO    0xfU
+#define V_RDMA_0B_WR_OPCODE_LO(x) ((x) << S_RDMA_0B_WR_OPCODE_LO)
+#define G_RDMA_0B_WR_OPCODE_LO(x) (((x) >> S_RDMA_0B_WR_OPCODE_LO) & M_RDMA_0B_WR_OPCODE_LO)
+
 #define A_ULP_RX_INT_ENABLE 0x19154
 
 #define S_ENABLE_CTX_1    24
@@ -36971,6 +46512,86 @@
 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
 #define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)
 
+#define S_CERR_PCMD_FIFO_3    19
+#define V_CERR_PCMD_FIFO_3(x) ((x) << S_CERR_PCMD_FIFO_3)
+#define F_CERR_PCMD_FIFO_3    V_CERR_PCMD_FIFO_3(1U)
+
+#define S_CERR_PCMD_FIFO_2    18
+#define V_CERR_PCMD_FIFO_2(x) ((x) << S_CERR_PCMD_FIFO_2)
+#define F_CERR_PCMD_FIFO_2    V_CERR_PCMD_FIFO_2(1U)
+
+#define S_CERR_PCMD_FIFO_1    17
+#define V_CERR_PCMD_FIFO_1(x) ((x) << S_CERR_PCMD_FIFO_1)
+#define F_CERR_PCMD_FIFO_1    V_CERR_PCMD_FIFO_1(1U)
+
+#define S_CERR_PCMD_FIFO_0    16
+#define V_CERR_PCMD_FIFO_0(x) ((x) << S_CERR_PCMD_FIFO_0)
+#define F_CERR_PCMD_FIFO_0    V_CERR_PCMD_FIFO_0(1U)
+
+#define S_CERR_DATA_FIFO_3    15
+#define V_CERR_DATA_FIFO_3(x) ((x) << S_CERR_DATA_FIFO_3)
+#define F_CERR_DATA_FIFO_3    V_CERR_DATA_FIFO_3(1U)
+
+#define S_CERR_DATA_FIFO_2    14
+#define V_CERR_DATA_FIFO_2(x) ((x) << S_CERR_DATA_FIFO_2)
+#define F_CERR_DATA_FIFO_2    V_CERR_DATA_FIFO_2(1U)
+
+#define S_CERR_DATA_FIFO_1    13
+#define V_CERR_DATA_FIFO_1(x) ((x) << S_CERR_DATA_FIFO_1)
+#define F_CERR_DATA_FIFO_1    V_CERR_DATA_FIFO_1(1U)
+
+#define S_CERR_DATA_FIFO_0    12
+#define V_CERR_DATA_FIFO_0(x) ((x) << S_CERR_DATA_FIFO_0)
+#define F_CERR_DATA_FIFO_0    V_CERR_DATA_FIFO_0(1U)
+
+#define S_SE_CNT_MISMATCH_3    11
+#define V_SE_CNT_MISMATCH_3(x) ((x) << S_SE_CNT_MISMATCH_3)
+#define F_SE_CNT_MISMATCH_3    V_SE_CNT_MISMATCH_3(1U)
+
+#define S_SE_CNT_MISMATCH_2    10
+#define V_SE_CNT_MISMATCH_2(x) ((x) << S_SE_CNT_MISMATCH_2)
+#define F_SE_CNT_MISMATCH_2    V_SE_CNT_MISMATCH_2(1U)
+
+#define S_T7_SE_CNT_MISMATCH_1    9
+#define V_T7_SE_CNT_MISMATCH_1(x) ((x) << S_T7_SE_CNT_MISMATCH_1)
+#define F_T7_SE_CNT_MISMATCH_1    V_T7_SE_CNT_MISMATCH_1(1U)
+
+#define S_T7_SE_CNT_MISMATCH_0    8
+#define V_T7_SE_CNT_MISMATCH_0(x) ((x) << S_T7_SE_CNT_MISMATCH_0)
+#define F_T7_SE_CNT_MISMATCH_0    V_T7_SE_CNT_MISMATCH_0(1U)
+
+#define S_ENABLE_CTX_3    7
+#define V_ENABLE_CTX_3(x) ((x) << S_ENABLE_CTX_3)
+#define F_ENABLE_CTX_3    V_ENABLE_CTX_3(1U)
+
+#define S_ENABLE_CTX_2    6
+#define V_ENABLE_CTX_2(x) ((x) << S_ENABLE_CTX_2)
+#define F_ENABLE_CTX_2    V_ENABLE_CTX_2(1U)
+
+#define S_T7_ENABLE_CTX_1    5
+#define V_T7_ENABLE_CTX_1(x) ((x) << S_T7_ENABLE_CTX_1)
+#define F_T7_ENABLE_CTX_1    V_T7_ENABLE_CTX_1(1U)
+
+#define S_T7_ENABLE_CTX_0    4
+#define V_T7_ENABLE_CTX_0(x) ((x) << S_T7_ENABLE_CTX_0)
+#define F_T7_ENABLE_CTX_0    V_T7_ENABLE_CTX_0(1U)
+
+#define S_ENABLE_ALN_SDC_ERR_3    3
+#define V_ENABLE_ALN_SDC_ERR_3(x) ((x) << S_ENABLE_ALN_SDC_ERR_3)
+#define F_ENABLE_ALN_SDC_ERR_3    V_ENABLE_ALN_SDC_ERR_3(1U)
+
+#define S_ENABLE_ALN_SDC_ERR_2    2
+#define V_ENABLE_ALN_SDC_ERR_2(x) ((x) << S_ENABLE_ALN_SDC_ERR_2)
+#define F_ENABLE_ALN_SDC_ERR_2    V_ENABLE_ALN_SDC_ERR_2(1U)
+
+#define S_T7_ENABLE_ALN_SDC_ERR_1    1
+#define V_T7_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_1)
+#define F_T7_ENABLE_ALN_SDC_ERR_1    V_T7_ENABLE_ALN_SDC_ERR_1(1U)
+
+#define S_T7_ENABLE_ALN_SDC_ERR_0    0
+#define V_T7_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_0)
+#define F_T7_ENABLE_ALN_SDC_ERR_0    V_T7_ENABLE_ALN_SDC_ERR_0(1U)
+
 #define A_ULP_RX_INT_CAUSE 0x19158
 
 #define S_CAUSE_CTX_1    24
@@ -37282,6 +46903,312 @@
 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
 
 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
+#define A_ULP_RX_CTX_ACC_CH2 0x191b4
+#define A_ULP_RX_CTX_ACC_CH3 0x191b8
+#define A_ULP_RX_CTL2 0x191bc
+
+#define S_PCMD3THRESHOLD    24
+#define M_PCMD3THRESHOLD    0xffU
+#define V_PCMD3THRESHOLD(x) ((x) << S_PCMD3THRESHOLD)
+#define G_PCMD3THRESHOLD(x) (((x) >> S_PCMD3THRESHOLD) & M_PCMD3THRESHOLD)
+
+#define S_PCMD2THRESHOLD    16
+#define M_PCMD2THRESHOLD    0xffU
+#define V_PCMD2THRESHOLD(x) ((x) << S_PCMD2THRESHOLD)
+#define G_PCMD2THRESHOLD(x) (((x) >> S_PCMD2THRESHOLD) & M_PCMD2THRESHOLD)
+
+#define S_T7_PCMD1THRESHOLD    8
+#define M_T7_PCMD1THRESHOLD    0xffU
+#define V_T7_PCMD1THRESHOLD(x) ((x) << S_T7_PCMD1THRESHOLD)
+#define G_T7_PCMD1THRESHOLD(x) (((x) >> S_T7_PCMD1THRESHOLD) & M_T7_PCMD1THRESHOLD)
+
+#define S_T7_PCMD0THRESHOLD    0
+#define M_T7_PCMD0THRESHOLD    0xffU
+#define V_T7_PCMD0THRESHOLD(x) ((x) << S_T7_PCMD0THRESHOLD)
+#define G_T7_PCMD0THRESHOLD(x) (((x) >> S_T7_PCMD0THRESHOLD) & M_T7_PCMD0THRESHOLD)
+
+#define A_ULP_RX_INT_ENABLE_INTERFACE 0x191c0
+
+#define S_ENABLE_ULPRX2SBT_RSPPERR    31
+#define V_ENABLE_ULPRX2SBT_RSPPERR(x) ((x) << S_ENABLE_ULPRX2SBT_RSPPERR)
+#define F_ENABLE_ULPRX2SBT_RSPPERR    V_ENABLE_ULPRX2SBT_RSPPERR(1U)
+
+#define S_ENABLE_ULPRX2MA_RSPPERR    30
+#define V_ENABLE_ULPRX2MA_RSPPERR(x) ((x) << S_ENABLE_ULPRX2MA_RSPPERR)
+#define F_ENABLE_ULPRX2MA_RSPPERR    V_ENABLE_ULPRX2MA_RSPPERR(1U)
+
+#define S_ENABME_PIO_BUS_PERR    29
+#define V_ENABME_PIO_BUS_PERR(x) ((x) << S_ENABME_PIO_BUS_PERR)
+#define F_ENABME_PIO_BUS_PERR    V_ENABME_PIO_BUS_PERR(1U)
+
+#define S_ENABLE_PM2ULP_SNOOPDATA_3    19
+#define V_ENABLE_PM2ULP_SNOOPDATA_3(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_3)
+#define F_ENABLE_PM2ULP_SNOOPDATA_3    V_ENABLE_PM2ULP_SNOOPDATA_3(1U)
+
+#define S_ENABLE_PM2ULP_SNOOPDATA_2    18
+#define V_ENABLE_PM2ULP_SNOOPDATA_2(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_2)
+#define F_ENABLE_PM2ULP_SNOOPDATA_2    V_ENABLE_PM2ULP_SNOOPDATA_2(1U)
+
+#define S_ENABLE_PM2ULP_SNOOPDATA_1    17
+#define V_ENABLE_PM2ULP_SNOOPDATA_1(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_1)
+#define F_ENABLE_PM2ULP_SNOOPDATA_1    V_ENABLE_PM2ULP_SNOOPDATA_1(1U)
+
+#define S_ENABLE_PM2ULP_SNOOPDATA_0    16
+#define V_ENABLE_PM2ULP_SNOOPDATA_0(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_0)
+#define F_ENABLE_PM2ULP_SNOOPDATA_0    V_ENABLE_PM2ULP_SNOOPDATA_0(1U)
+
+#define S_ENABLE_TLS2ULP_DATA_3    15
+#define V_ENABLE_TLS2ULP_DATA_3(x) ((x) << S_ENABLE_TLS2ULP_DATA_3)
+#define F_ENABLE_TLS2ULP_DATA_3    V_ENABLE_TLS2ULP_DATA_3(1U)
+
+#define S_ENABLE_TLS2ULP_DATA_2    14
+#define V_ENABLE_TLS2ULP_DATA_2(x) ((x) << S_ENABLE_TLS2ULP_DATA_2)
+#define F_ENABLE_TLS2ULP_DATA_2    V_ENABLE_TLS2ULP_DATA_2(1U)
+
+#define S_ENABLE_TLS2ULP_DATA_1    13
+#define V_ENABLE_TLS2ULP_DATA_1(x) ((x) << S_ENABLE_TLS2ULP_DATA_1)
+#define F_ENABLE_TLS2ULP_DATA_1    V_ENABLE_TLS2ULP_DATA_1(1U)
+
+#define S_ENABLE_TLS2ULP_DATA_0    12
+#define V_ENABLE_TLS2ULP_DATA_0(x) ((x) << S_ENABLE_TLS2ULP_DATA_0)
+#define F_ENABLE_TLS2ULP_DATA_0    V_ENABLE_TLS2ULP_DATA_0(1U)
+
+#define S_ENABLE_TLS2ULP_PLENDATA_3    11
+#define V_ENABLE_TLS2ULP_PLENDATA_3(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_3)
+#define F_ENABLE_TLS2ULP_PLENDATA_3    V_ENABLE_TLS2ULP_PLENDATA_3(1U)
+
+#define S_ENABLE_TLS2ULP_PLENDATA_2    10
+#define V_ENABLE_TLS2ULP_PLENDATA_2(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_2)
+#define F_ENABLE_TLS2ULP_PLENDATA_2    V_ENABLE_TLS2ULP_PLENDATA_2(1U)
+
+#define S_ENABLE_TLS2ULP_PLENDATA_1    9
+#define V_ENABLE_TLS2ULP_PLENDATA_1(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_1)
+#define F_ENABLE_TLS2ULP_PLENDATA_1    V_ENABLE_TLS2ULP_PLENDATA_1(1U)
+
+#define S_ENABLE_TLS2ULP_PLENDATA_0    8
+#define V_ENABLE_TLS2ULP_PLENDATA_0(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_0)
+#define F_ENABLE_TLS2ULP_PLENDATA_0    V_ENABLE_TLS2ULP_PLENDATA_0(1U)
+
+#define S_ENABLE_PM2ULP_DATA_3    7
+#define V_ENABLE_PM2ULP_DATA_3(x) ((x) << S_ENABLE_PM2ULP_DATA_3)
+#define F_ENABLE_PM2ULP_DATA_3    V_ENABLE_PM2ULP_DATA_3(1U)
+
+#define S_ENABLE_PM2ULP_DATA_2    6
+#define V_ENABLE_PM2ULP_DATA_2(x) ((x) << S_ENABLE_PM2ULP_DATA_2)
+#define F_ENABLE_PM2ULP_DATA_2    V_ENABLE_PM2ULP_DATA_2(1U)
+
+#define S_ENABLE_PM2ULP_DATA_1    5
+#define V_ENABLE_PM2ULP_DATA_1(x) ((x) << S_ENABLE_PM2ULP_DATA_1)
+#define F_ENABLE_PM2ULP_DATA_1    V_ENABLE_PM2ULP_DATA_1(1U)
+
+#define S_ENABLE_PM2ULP_DATA_0    4
+#define V_ENABLE_PM2ULP_DATA_0(x) ((x) << S_ENABLE_PM2ULP_DATA_0)
+#define F_ENABLE_PM2ULP_DATA_0    V_ENABLE_PM2ULP_DATA_0(1U)
+
+#define S_ENABLE_TP2ULP_PCMD_3    3
+#define V_ENABLE_TP2ULP_PCMD_3(x) ((x) << S_ENABLE_TP2ULP_PCMD_3)
+#define F_ENABLE_TP2ULP_PCMD_3    V_ENABLE_TP2ULP_PCMD_3(1U)
+
+#define S_ENABLE_TP2ULP_PCMD_2    2
+#define V_ENABLE_TP2ULP_PCMD_2(x) ((x) << S_ENABLE_TP2ULP_PCMD_2)
+#define F_ENABLE_TP2ULP_PCMD_2    V_ENABLE_TP2ULP_PCMD_2(1U)
+
+#define S_ENABLE_TP2ULP_PCMD_1    1
+#define V_ENABLE_TP2ULP_PCMD_1(x) ((x) << S_ENABLE_TP2ULP_PCMD_1)
+#define F_ENABLE_TP2ULP_PCMD_1    V_ENABLE_TP2ULP_PCMD_1(1U)
+
+#define S_ENABLE_TP2ULP_PCMD_0    0
+#define V_ENABLE_TP2ULP_PCMD_0(x) ((x) << S_ENABLE_TP2ULP_PCMD_0)
+#define F_ENABLE_TP2ULP_PCMD_0    V_ENABLE_TP2ULP_PCMD_0(1U)
+
+#define A_ULP_RX_INT_CAUSE_INTERFACE 0x191c4
+
+#define S_CAUSE_ULPRX2SBT_RSPPERR    31
+#define V_CAUSE_ULPRX2SBT_RSPPERR(x) ((x) << S_CAUSE_ULPRX2SBT_RSPPERR)
+#define F_CAUSE_ULPRX2SBT_RSPPERR    V_CAUSE_ULPRX2SBT_RSPPERR(1U)
+
+#define S_CAUSE_ULPRX2MA_RSPPERR    30
+#define V_CAUSE_ULPRX2MA_RSPPERR(x) ((x) << S_CAUSE_ULPRX2MA_RSPPERR)
+#define F_CAUSE_ULPRX2MA_RSPPERR    V_CAUSE_ULPRX2MA_RSPPERR(1U)
+
+#define S_CAUSE_PIO_BUS_PERR    29
+#define V_CAUSE_PIO_BUS_PERR(x) ((x) << S_CAUSE_PIO_BUS_PERR)
+#define F_CAUSE_PIO_BUS_PERR    V_CAUSE_PIO_BUS_PERR(1U)
+
+#define S_CAUSE_PM2ULP_SNOOPDATA_3    19
+#define V_CAUSE_PM2ULP_SNOOPDATA_3(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_3)
+#define F_CAUSE_PM2ULP_SNOOPDATA_3    V_CAUSE_PM2ULP_SNOOPDATA_3(1U)
+
+#define S_CAUSE_PM2ULP_SNOOPDATA_2    18
+#define V_CAUSE_PM2ULP_SNOOPDATA_2(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_2)
+#define F_CAUSE_PM2ULP_SNOOPDATA_2    V_CAUSE_PM2ULP_SNOOPDATA_2(1U)
+
+#define S_CAUSE_PM2ULP_SNOOPDATA_1    17
+#define V_CAUSE_PM2ULP_SNOOPDATA_1(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_1)
+#define F_CAUSE_PM2ULP_SNOOPDATA_1    V_CAUSE_PM2ULP_SNOOPDATA_1(1U)
+
+#define S_CAUSE_PM2ULP_SNOOPDATA_0    16
+#define V_CAUSE_PM2ULP_SNOOPDATA_0(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_0)
+#define F_CAUSE_PM2ULP_SNOOPDATA_0    V_CAUSE_PM2ULP_SNOOPDATA_0(1U)
+
+#define S_CAUSE_TLS2ULP_DATA_3    15
+#define V_CAUSE_TLS2ULP_DATA_3(x) ((x) << S_CAUSE_TLS2ULP_DATA_3)
+#define F_CAUSE_TLS2ULP_DATA_3    V_CAUSE_TLS2ULP_DATA_3(1U)
+
+#define S_CAUSE_TLS2ULP_DATA_2    14
+#define V_CAUSE_TLS2ULP_DATA_2(x) ((x) << S_CAUSE_TLS2ULP_DATA_2)
+#define F_CAUSE_TLS2ULP_DATA_2    V_CAUSE_TLS2ULP_DATA_2(1U)
+
+#define S_CAUSE_TLS2ULP_DATA_1    13
+#define V_CAUSE_TLS2ULP_DATA_1(x) ((x) << S_CAUSE_TLS2ULP_DATA_1)
+#define F_CAUSE_TLS2ULP_DATA_1    V_CAUSE_TLS2ULP_DATA_1(1U)
+
+#define S_CAUSE_TLS2ULP_DATA_0    12
+#define V_CAUSE_TLS2ULP_DATA_0(x) ((x) << S_CAUSE_TLS2ULP_DATA_0)
+#define F_CAUSE_TLS2ULP_DATA_0    V_CAUSE_TLS2ULP_DATA_0(1U)
+
+#define S_CAUSE_TLS2ULP_PLENDATA_3    11
+#define V_CAUSE_TLS2ULP_PLENDATA_3(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_3)
+#define F_CAUSE_TLS2ULP_PLENDATA_3    V_CAUSE_TLS2ULP_PLENDATA_3(1U)
+
+#define S_CAUSE_TLS2ULP_PLENDATA_2    10
+#define V_CAUSE_TLS2ULP_PLENDATA_2(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_2)
+#define F_CAUSE_TLS2ULP_PLENDATA_2    V_CAUSE_TLS2ULP_PLENDATA_2(1U)
+
+#define S_CAUSE_TLS2ULP_PLENDATA_1    9
+#define V_CAUSE_TLS2ULP_PLENDATA_1(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_1)
+#define F_CAUSE_TLS2ULP_PLENDATA_1    V_CAUSE_TLS2ULP_PLENDATA_1(1U)
+
+#define S_CAUSE_TLS2ULP_PLENDATA_0    8
+#define V_CAUSE_TLS2ULP_PLENDATA_0(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_0)
+#define F_CAUSE_TLS2ULP_PLENDATA_0    V_CAUSE_TLS2ULP_PLENDATA_0(1U)
+
+#define S_CAUSE_PM2ULP_DATA_3    7
+#define V_CAUSE_PM2ULP_DATA_3(x) ((x) << S_CAUSE_PM2ULP_DATA_3)
+#define F_CAUSE_PM2ULP_DATA_3    V_CAUSE_PM2ULP_DATA_3(1U)
+
+#define S_CAUSE_PM2ULP_DATA_2    6
+#define V_CAUSE_PM2ULP_DATA_2(x) ((x) << S_CAUSE_PM2ULP_DATA_2)
+#define F_CAUSE_PM2ULP_DATA_2    V_CAUSE_PM2ULP_DATA_2(1U)
+
+#define S_CAUSE_PM2ULP_DATA_1    5
+#define V_CAUSE_PM2ULP_DATA_1(x) ((x) << S_CAUSE_PM2ULP_DATA_1)
+#define F_CAUSE_PM2ULP_DATA_1    V_CAUSE_PM2ULP_DATA_1(1U)
+
+#define S_CAUSE_PM2ULP_DATA_0    4
+#define V_CAUSE_PM2ULP_DATA_0(x) ((x) << S_CAUSE_PM2ULP_DATA_0)
+#define F_CAUSE_PM2ULP_DATA_0    V_CAUSE_PM2ULP_DATA_0(1U)
+
+#define S_CAUSE_TP2ULP_PCMD_3    3
+#define V_CAUSE_TP2ULP_PCMD_3(x) ((x) << S_CAUSE_TP2ULP_PCMD_3)
+#define F_CAUSE_TP2ULP_PCMD_3    V_CAUSE_TP2ULP_PCMD_3(1U)
+
+#define S_CAUSE_TP2ULP_PCMD_2    2
+#define V_CAUSE_TP2ULP_PCMD_2(x) ((x) << S_CAUSE_TP2ULP_PCMD_2)
+#define F_CAUSE_TP2ULP_PCMD_2    V_CAUSE_TP2ULP_PCMD_2(1U)
+
+#define S_CAUSE_TP2ULP_PCMD_1    1
+#define V_CAUSE_TP2ULP_PCMD_1(x) ((x) << S_CAUSE_TP2ULP_PCMD_1)
+#define F_CAUSE_TP2ULP_PCMD_1    V_CAUSE_TP2ULP_PCMD_1(1U)
+
+#define S_CAUSE_TP2ULP_PCMD_0    0
+#define V_CAUSE_TP2ULP_PCMD_0(x) ((x) << S_CAUSE_TP2ULP_PCMD_0)
+#define F_CAUSE_TP2ULP_PCMD_0    V_CAUSE_TP2ULP_PCMD_0(1U)
+
+#define A_ULP_RX_PERR_ENABLE_INTERFACE 0x191c8
+
+#define S_PERR_ULPRX2SBT_RSPPERR    31
+#define V_PERR_ULPRX2SBT_RSPPERR(x) ((x) << S_PERR_ULPRX2SBT_RSPPERR)
+#define F_PERR_ULPRX2SBT_RSPPERR    V_PERR_ULPRX2SBT_RSPPERR(1U)
+
+#define S_PERR_ULPRX2MA_RSPPERR    30
+#define V_PERR_ULPRX2MA_RSPPERR(x) ((x) << S_PERR_ULPRX2MA_RSPPERR)
+#define F_PERR_ULPRX2MA_RSPPERR    V_PERR_ULPRX2MA_RSPPERR(1U)
+
+#define S_PERR_PIO_BUS_PERR    29
+#define V_PERR_PIO_BUS_PERR(x) ((x) << S_PERR_PIO_BUS_PERR)
+#define F_PERR_PIO_BUS_PERR    V_PERR_PIO_BUS_PERR(1U)
+
+#define S_PERR_PM2ULP_SNOOPDATA_3    19
+#define V_PERR_PM2ULP_SNOOPDATA_3(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_3)
+#define F_PERR_PM2ULP_SNOOPDATA_3    V_PERR_PM2ULP_SNOOPDATA_3(1U)
+
+#define S_PERR_PM2ULP_SNOOPDATA_2    18
+#define V_PERR_PM2ULP_SNOOPDATA_2(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_2)
+#define F_PERR_PM2ULP_SNOOPDATA_2    V_PERR_PM2ULP_SNOOPDATA_2(1U)
+
+#define S_PERR_PM2ULP_SNOOPDATA_1    17
+#define V_PERR_PM2ULP_SNOOPDATA_1(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_1)
+#define F_PERR_PM2ULP_SNOOPDATA_1    V_PERR_PM2ULP_SNOOPDATA_1(1U)
+
+#define S_PERR_PM2ULP_SNOOPDATA_0    16
+#define V_PERR_PM2ULP_SNOOPDATA_0(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_0)
+#define F_PERR_PM2ULP_SNOOPDATA_0    V_PERR_PM2ULP_SNOOPDATA_0(1U)
+
+#define S_PERR_TLS2ULP_DATA_3    15
+#define V_PERR_TLS2ULP_DATA_3(x) ((x) << S_PERR_TLS2ULP_DATA_3)
+#define F_PERR_TLS2ULP_DATA_3    V_PERR_TLS2ULP_DATA_3(1U)
+
+#define S_PERR_TLS2ULP_DATA_2    14
+#define V_PERR_TLS2ULP_DATA_2(x) ((x) << S_PERR_TLS2ULP_DATA_2)
+#define F_PERR_TLS2ULP_DATA_2    V_PERR_TLS2ULP_DATA_2(1U)
+
+#define S_PERR_TLS2ULP_DATA_1    13
+#define V_PERR_TLS2ULP_DATA_1(x) ((x) << S_PERR_TLS2ULP_DATA_1)
+#define F_PERR_TLS2ULP_DATA_1    V_PERR_TLS2ULP_DATA_1(1U)
+
+#define S_PERR_TLS2ULP_DATA_0    12
+#define V_PERR_TLS2ULP_DATA_0(x) ((x) << S_PERR_TLS2ULP_DATA_0)
+#define F_PERR_TLS2ULP_DATA_0    V_PERR_TLS2ULP_DATA_0(1U)
+
+#define S_PERR_TLS2ULP_PLENDATA_3    11
+#define V_PERR_TLS2ULP_PLENDATA_3(x) ((x) << S_PERR_TLS2ULP_PLENDATA_3)
+#define F_PERR_TLS2ULP_PLENDATA_3    V_PERR_TLS2ULP_PLENDATA_3(1U)
+
+#define S_PERR_TLS2ULP_PLENDATA_2    10
+#define V_PERR_TLS2ULP_PLENDATA_2(x) ((x) << S_PERR_TLS2ULP_PLENDATA_2)
+#define F_PERR_TLS2ULP_PLENDATA_2    V_PERR_TLS2ULP_PLENDATA_2(1U)
+
+#define S_PERR_TLS2ULP_PLENDATA_1    9
+#define V_PERR_TLS2ULP_PLENDATA_1(x) ((x) << S_PERR_TLS2ULP_PLENDATA_1)
+#define F_PERR_TLS2ULP_PLENDATA_1    V_PERR_TLS2ULP_PLENDATA_1(1U)
+
+#define S_PERR_TLS2ULP_PLENDATA_0    8
+#define V_PERR_TLS2ULP_PLENDATA_0(x) ((x) << S_PERR_TLS2ULP_PLENDATA_0)
+#define F_PERR_TLS2ULP_PLENDATA_0    V_PERR_TLS2ULP_PLENDATA_0(1U)
+
+#define S_PERR_PM2ULP_DATA_3    7
+#define V_PERR_PM2ULP_DATA_3(x) ((x) << S_PERR_PM2ULP_DATA_3)
+#define F_PERR_PM2ULP_DATA_3    V_PERR_PM2ULP_DATA_3(1U)
+
+#define S_PERR_PM2ULP_DATA_2    6
+#define V_PERR_PM2ULP_DATA_2(x) ((x) << S_PERR_PM2ULP_DATA_2)
+#define F_PERR_PM2ULP_DATA_2    V_PERR_PM2ULP_DATA_2(1U)
+
+#define S_PERR_PM2ULP_DATA_1    5
+#define V_PERR_PM2ULP_DATA_1(x) ((x) << S_PERR_PM2ULP_DATA_1)
+#define F_PERR_PM2ULP_DATA_1    V_PERR_PM2ULP_DATA_1(1U)
+
+#define S_PERR_PM2ULP_DATA_0    4
+#define V_PERR_PM2ULP_DATA_0(x) ((x) << S_PERR_PM2ULP_DATA_0)
+#define F_PERR_PM2ULP_DATA_0    V_PERR_PM2ULP_DATA_0(1U)
+
+#define S_PERR_TP2ULP_PCMD_3    3
+#define V_PERR_TP2ULP_PCMD_3(x) ((x) << S_PERR_TP2ULP_PCMD_3)
+#define F_PERR_TP2ULP_PCMD_3    V_PERR_TP2ULP_PCMD_3(1U)
+
+#define S_PERR_TP2ULP_PCMD_2    2
+#define V_PERR_TP2ULP_PCMD_2(x) ((x) << S_PERR_TP2ULP_PCMD_2)
+#define F_PERR_TP2ULP_PCMD_2    V_PERR_TP2ULP_PCMD_2(1U)
+
+#define S_PERR_TP2ULP_PCMD_1    1
+#define V_PERR_TP2ULP_PCMD_1(x) ((x) << S_PERR_TP2ULP_PCMD_1)
+#define F_PERR_TP2ULP_PCMD_1    V_PERR_TP2ULP_PCMD_1(1U)
+
+#define S_PERR_TP2ULP_PCMD_0    0
+#define V_PERR_TP2ULP_PCMD_0(x) ((x) << S_PERR_TP2ULP_PCMD_0)
+#define F_PERR_TP2ULP_PCMD_0    V_PERR_TP2ULP_PCMD_0(1U)
+
 #define A_ULP_RX_SE_CNT_ERR 0x191d0
 #define A_ULP_RX_SE_CNT_CLR 0x191d4
 
@@ -37295,6 +47222,26 @@
 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
 
+#define S_CLRCHAN3    12
+#define M_CLRCHAN3    0xfU
+#define V_CLRCHAN3(x) ((x) << S_CLRCHAN3)
+#define G_CLRCHAN3(x) (((x) >> S_CLRCHAN3) & M_CLRCHAN3)
+
+#define S_CLRCHAN2    8
+#define M_CLRCHAN2    0xfU
+#define V_CLRCHAN2(x) ((x) << S_CLRCHAN2)
+#define G_CLRCHAN2(x) (((x) >> S_CLRCHAN2) & M_CLRCHAN2)
+
+#define S_T7_CLRCHAN1    4
+#define M_T7_CLRCHAN1    0xfU
+#define V_T7_CLRCHAN1(x) ((x) << S_T7_CLRCHAN1)
+#define G_T7_CLRCHAN1(x) (((x) >> S_T7_CLRCHAN1) & M_T7_CLRCHAN1)
+
+#define S_T7_CLRCHAN0    0
+#define M_T7_CLRCHAN0    0xfU
+#define V_T7_CLRCHAN0(x) ((x) << S_T7_CLRCHAN0)
+#define G_T7_CLRCHAN0(x) (((x) >> S_T7_CLRCHAN0) & M_T7_CLRCHAN0)
+
 #define A_ULP_RX_SE_CNT_CH0 0x191d8
 
 #define S_SOP_CNT_OUT0    28
@@ -37400,6 +47347,7 @@
 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
 
 #define A_ULP_RX_DBG_DATAH 0x191e4
+#define A_ULP_RX_DBG_DATA 0x191e4
 #define A_ULP_RX_DBG_DATAL 0x191e8
 #define A_ULP_RX_LA_CHNL 0x19238
 
@@ -37581,6 +47529,11 @@
 #define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE)
 #define F_PIO_RDMA_SEND_RQE    V_PIO_RDMA_SEND_RQE(1U)
 
+#define S_TLS_KEYSIZECONF    26
+#define M_TLS_KEYSIZECONF    0x3U
+#define V_TLS_KEYSIZECONF(x) ((x) << S_TLS_KEYSIZECONF)
+#define G_TLS_KEYSIZECONF(x) (((x) >> S_TLS_KEYSIZECONF) & M_TLS_KEYSIZECONF)
+
 #define A_ULP_RX_CH0_CGEN 0x19260
 
 #define S_BYPASS_CGEN    7
@@ -37615,7 +47568,61 @@
 #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
 #define F_RDMA_DATAPATH_CGEN    V_RDMA_DATAPATH_CGEN(1U)
 
+#define A_ULP_RX_CH_CGEN 0x19260
+
+#define S_T7_BYPASS_CGEN    28
+#define M_T7_BYPASS_CGEN    0xfU
+#define V_T7_BYPASS_CGEN(x) ((x) << S_T7_BYPASS_CGEN)
+#define G_T7_BYPASS_CGEN(x) (((x) >> S_T7_BYPASS_CGEN) & M_T7_BYPASS_CGEN)
+
+#define S_T7_TDDP_CGEN    24
+#define M_T7_TDDP_CGEN    0xfU
+#define V_T7_TDDP_CGEN(x) ((x) << S_T7_TDDP_CGEN)
+#define G_T7_TDDP_CGEN(x) (((x) >> S_T7_TDDP_CGEN) & M_T7_TDDP_CGEN)
+
+#define S_T7_ISCSI_CGEN    20
+#define M_T7_ISCSI_CGEN    0xfU
+#define V_T7_ISCSI_CGEN(x) ((x) << S_T7_ISCSI_CGEN)
+#define G_T7_ISCSI_CGEN(x) (((x) >> S_T7_ISCSI_CGEN) & M_T7_ISCSI_CGEN)
+
+#define S_T7_RDMA_CGEN    16
+#define M_T7_RDMA_CGEN    0xfU
+#define V_T7_RDMA_CGEN(x) ((x) << S_T7_RDMA_CGEN)
+#define G_T7_RDMA_CGEN(x) (((x) >> S_T7_RDMA_CGEN) & M_T7_RDMA_CGEN)
+
+#define S_T7_CHANNEL_CGEN    12
+#define M_T7_CHANNEL_CGEN    0xfU
+#define V_T7_CHANNEL_CGEN(x) ((x) << S_T7_CHANNEL_CGEN)
+#define G_T7_CHANNEL_CGEN(x) (((x) >> S_T7_CHANNEL_CGEN) & M_T7_CHANNEL_CGEN)
+
+#define S_T7_ALL_DATAPATH_CGEN    8
+#define M_T7_ALL_DATAPATH_CGEN    0xfU
+#define V_T7_ALL_DATAPATH_CGEN(x) ((x) << S_T7_ALL_DATAPATH_CGEN)
+#define G_T7_ALL_DATAPATH_CGEN(x) (((x) >> S_T7_ALL_DATAPATH_CGEN) & M_T7_ALL_DATAPATH_CGEN)
+
+#define S_T7_T10DIFF_DATAPATH_CGEN    4
+#define M_T7_T10DIFF_DATAPATH_CGEN    0xfU
+#define V_T7_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T7_T10DIFF_DATAPATH_CGEN)
+#define G_T7_T10DIFF_DATAPATH_CGEN(x) (((x) >> S_T7_T10DIFF_DATAPATH_CGEN) & M_T7_T10DIFF_DATAPATH_CGEN)
+
+#define S_T7_RDMA_DATAPATH_CGEN    0
+#define M_T7_RDMA_DATAPATH_CGEN    0xfU
+#define V_T7_RDMA_DATAPATH_CGEN(x) ((x) << S_T7_RDMA_DATAPATH_CGEN)
+#define G_T7_RDMA_DATAPATH_CGEN(x) (((x) >> S_T7_RDMA_DATAPATH_CGEN) & M_T7_RDMA_DATAPATH_CGEN)
+
 #define A_ULP_RX_CH1_CGEN 0x19264
+#define A_ULP_RX_CH_CGEN_1 0x19264
+
+#define S_NVME_TCP_CGEN    4
+#define M_NVME_TCP_CGEN    0xfU
+#define V_NVME_TCP_CGEN(x) ((x) << S_NVME_TCP_CGEN)
+#define G_NVME_TCP_CGEN(x) (((x) >> S_NVME_TCP_CGEN) & M_NVME_TCP_CGEN)
+
+#define S_ROCE_CGEN    0
+#define M_ROCE_CGEN    0xfU
+#define V_ROCE_CGEN(x) ((x) << S_ROCE_CGEN)
+#define G_ROCE_CGEN(x) (((x) >> S_ROCE_CGEN) & M_ROCE_CGEN)
+
 #define A_ULP_RX_RFE_DISABLE 0x19268
 
 #define S_RQE_LIM_CHECK_RFE_DISABLE    0
@@ -37742,6 +47749,30 @@
 #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
 #define F_SKIP_MA_REQ_EN0    V_SKIP_MA_REQ_EN0(1U)
 
+#define S_CLEAR_CTX_ERR_CNT3    7
+#define V_CLEAR_CTX_ERR_CNT3(x) ((x) << S_CLEAR_CTX_ERR_CNT3)
+#define F_CLEAR_CTX_ERR_CNT3    V_CLEAR_CTX_ERR_CNT3(1U)
+
+#define S_CLEAR_CTX_ERR_CNT2    6
+#define V_CLEAR_CTX_ERR_CNT2(x) ((x) << S_CLEAR_CTX_ERR_CNT2)
+#define F_CLEAR_CTX_ERR_CNT2    V_CLEAR_CTX_ERR_CNT2(1U)
+
+#define S_T7_CLEAR_CTX_ERR_CNT1    5
+#define V_T7_CLEAR_CTX_ERR_CNT1(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT1)
+#define F_T7_CLEAR_CTX_ERR_CNT1    V_T7_CLEAR_CTX_ERR_CNT1(1U)
+
+#define S_T7_CLEAR_CTX_ERR_CNT0    4
+#define V_T7_CLEAR_CTX_ERR_CNT0(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT0)
+#define F_T7_CLEAR_CTX_ERR_CNT0    V_T7_CLEAR_CTX_ERR_CNT0(1U)
+
+#define S_SKIP_MA_REQ_EN3    3
+#define V_SKIP_MA_REQ_EN3(x) ((x) << S_SKIP_MA_REQ_EN3)
+#define F_SKIP_MA_REQ_EN3    V_SKIP_MA_REQ_EN3(1U)
+
+#define S_SKIP_MA_REQ_EN2    2
+#define V_SKIP_MA_REQ_EN2(x) ((x) << S_SKIP_MA_REQ_EN2)
+#define F_SKIP_MA_REQ_EN2    V_SKIP_MA_REQ_EN2(1U)
+
 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
@@ -37758,6 +47789,92 @@
 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
 #define F_SEND_MSN_CHECK_ENABLE    V_SEND_MSN_CHECK_ENABLE(1U)
 
+#define A_ULP_RX_SE_CNT_CH2 0x19294
+
+#define S_SOP_CNT_OUT2    28
+#define M_SOP_CNT_OUT2    0xfU
+#define V_SOP_CNT_OUT2(x) ((x) << S_SOP_CNT_OUT2)
+#define G_SOP_CNT_OUT2(x) (((x) >> S_SOP_CNT_OUT2) & M_SOP_CNT_OUT2)
+
+#define S_EOP_CNT_OUT2    24
+#define M_EOP_CNT_OUT2    0xfU
+#define V_EOP_CNT_OUT2(x) ((x) << S_EOP_CNT_OUT2)
+#define G_EOP_CNT_OUT2(x) (((x) >> S_EOP_CNT_OUT2) & M_EOP_CNT_OUT2)
+
+#define S_SOP_CNT_AL2    20
+#define M_SOP_CNT_AL2    0xfU
+#define V_SOP_CNT_AL2(x) ((x) << S_SOP_CNT_AL2)
+#define G_SOP_CNT_AL2(x) (((x) >> S_SOP_CNT_AL2) & M_SOP_CNT_AL2)
+
+#define S_EOP_CNT_AL2    16
+#define M_EOP_CNT_AL2    0xfU
+#define V_EOP_CNT_AL2(x) ((x) << S_EOP_CNT_AL2)
+#define G_EOP_CNT_AL2(x) (((x) >> S_EOP_CNT_AL2) & M_EOP_CNT_AL2)
+
+#define S_SOP_CNT_MR2    12
+#define M_SOP_CNT_MR2    0xfU
+#define V_SOP_CNT_MR2(x) ((x) << S_SOP_CNT_MR2)
+#define G_SOP_CNT_MR2(x) (((x) >> S_SOP_CNT_MR2) & M_SOP_CNT_MR2)
+
+#define S_EOP_CNT_MR2    8
+#define M_EOP_CNT_MR2    0xfU
+#define V_EOP_CNT_MR2(x) ((x) << S_EOP_CNT_MR2)
+#define G_EOP_CNT_MR2(x) (((x) >> S_EOP_CNT_MR2) & M_EOP_CNT_MR2)
+
+#define S_SOP_CNT_IN2    4
+#define M_SOP_CNT_IN2    0xfU
+#define V_SOP_CNT_IN2(x) ((x) << S_SOP_CNT_IN2)
+#define G_SOP_CNT_IN2(x) (((x) >> S_SOP_CNT_IN2) & M_SOP_CNT_IN2)
+
+#define S_EOP_CNT_IN2    0
+#define M_EOP_CNT_IN2    0xfU
+#define V_EOP_CNT_IN2(x) ((x) << S_EOP_CNT_IN2)
+#define G_EOP_CNT_IN2(x) (((x) >> S_EOP_CNT_IN2) & M_EOP_CNT_IN2)
+
+#define A_ULP_RX_SE_CNT_CH3 0x19298
+
+#define S_SOP_CNT_OUT3    28
+#define M_SOP_CNT_OUT3    0xfU
+#define V_SOP_CNT_OUT3(x) ((x) << S_SOP_CNT_OUT3)
+#define G_SOP_CNT_OUT3(x) (((x) >> S_SOP_CNT_OUT3) & M_SOP_CNT_OUT3)
+
+#define S_EOP_CNT_OUT3    24
+#define M_EOP_CNT_OUT3    0xfU
+#define V_EOP_CNT_OUT3(x) ((x) << S_EOP_CNT_OUT3)
+#define G_EOP_CNT_OUT3(x) (((x) >> S_EOP_CNT_OUT3) & M_EOP_CNT_OUT3)
+
+#define S_SOP_CNT_AL3    20
+#define M_SOP_CNT_AL3    0xfU
+#define V_SOP_CNT_AL3(x) ((x) << S_SOP_CNT_AL3)
+#define G_SOP_CNT_AL3(x) (((x) >> S_SOP_CNT_AL3) & M_SOP_CNT_AL3)
+
+#define S_EOP_CNT_AL3    16
+#define M_EOP_CNT_AL3    0xfU
+#define V_EOP_CNT_AL3(x) ((x) << S_EOP_CNT_AL3)
+#define G_EOP_CNT_AL3(x) (((x) >> S_EOP_CNT_AL3) & M_EOP_CNT_AL3)
+
+#define S_SOP_CNT_MR3    12
+#define M_SOP_CNT_MR3    0xfU
+#define V_SOP_CNT_MR3(x) ((x) << S_SOP_CNT_MR3)
+#define G_SOP_CNT_MR3(x) (((x) >> S_SOP_CNT_MR3) & M_SOP_CNT_MR3)
+
+#define S_EOP_CNT_MR3    8
+#define M_EOP_CNT_MR3    0xfU
+#define V_EOP_CNT_MR3(x) ((x) << S_EOP_CNT_MR3)
+#define G_EOP_CNT_MR3(x) (((x) >> S_EOP_CNT_MR3) & M_EOP_CNT_MR3)
+
+#define S_SOP_CNT_IN3    4
+#define M_SOP_CNT_IN3    0xfU
+#define V_SOP_CNT_IN3(x) ((x) << S_SOP_CNT_IN3)
+#define G_SOP_CNT_IN3(x) (((x) >> S_SOP_CNT_IN3) & M_SOP_CNT_IN3)
+
+#define S_EOP_CNT_IN3    0
+#define M_EOP_CNT_IN3    0xfU
+#define V_EOP_CNT_IN3(x) ((x) << S_EOP_CNT_IN3)
+#define G_EOP_CNT_IN3(x) (((x) >> S_EOP_CNT_IN3) & M_EOP_CNT_IN3)
+
+#define A_ULP_RX_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1929c
+#define A_ULP_RX_CHNL3_CTX_ERROR_COUNT_PER_TID 0x192a0
 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
 
 #define S_TLSPPLLIMIT    6
@@ -37787,6 +47904,933 @@
 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
 
 #define A_ULP_RX_TLS_CTL 0x192bc
+#define A_ULP_RX_RRQ_LLIMIT 0x192c0
+#define A_ULP_RX_RRQ_ULIMIT 0x192c4
+#define A_ULP_RX_NVME_TCP_STAG_LLIMIT 0x192c8
+#define A_ULP_RX_NVME_TCP_STAG_ULIMIT 0x192cc
+#define A_ULP_RX_NVME_TCP_RQ_LLIMIT 0x192d0
+#define A_ULP_RX_NVME_TCP_RQ_ULIMIT 0x192d4
+#define A_ULP_RX_NVME_TCP_PBL_LLIMIT 0x192d8
+#define A_ULP_RX_NVME_TCP_PBL_ULIMIT 0x192dc
+#define A_ULP_RX_NVME_TCP_MAX_LENGTH 0x192e0
+
+#define S_NVME_TCP_MAX_PLEN01    24
+#define M_NVME_TCP_MAX_PLEN01    0xffU
+#define V_NVME_TCP_MAX_PLEN01(x) ((x) << S_NVME_TCP_MAX_PLEN01)
+#define G_NVME_TCP_MAX_PLEN01(x) (((x) >> S_NVME_TCP_MAX_PLEN01) & M_NVME_TCP_MAX_PLEN01)
+
+#define S_NVME_TCP_MAX_PLEN23    16
+#define M_NVME_TCP_MAX_PLEN23    0xffU
+#define V_NVME_TCP_MAX_PLEN23(x) ((x) << S_NVME_TCP_MAX_PLEN23)
+#define G_NVME_TCP_MAX_PLEN23(x) (((x) >> S_NVME_TCP_MAX_PLEN23) & M_NVME_TCP_MAX_PLEN23)
+
+#define S_NVME_TCP_MAX_CMD_PDU_LENGTH    0
+#define M_NVME_TCP_MAX_CMD_PDU_LENGTH    0xffffU
+#define V_NVME_TCP_MAX_CMD_PDU_LENGTH(x) ((x) << S_NVME_TCP_MAX_CMD_PDU_LENGTH)
+#define G_NVME_TCP_MAX_CMD_PDU_LENGTH(x) (((x) >> S_NVME_TCP_MAX_CMD_PDU_LENGTH) & M_NVME_TCP_MAX_CMD_PDU_LENGTH)
+
+#define A_ULP_RX_NVME_TCP_IQE_SIZE 0x192e4
+#define A_ULP_RX_NVME_TCP_NEW_PDU_TYPES 0x192e8
+#define A_ULP_RX_IWARP_PMOF_OPCODES_1 0x192ec
+#define A_ULP_RX_IWARP_PMOF_OPCODES_2 0x192f0
+#define A_ULP_RX_INT_ENABLE_PCMD 0x19300
+
+#define S_ENABLE_PCMD_SFIFO_3    30
+#define V_ENABLE_PCMD_SFIFO_3(x) ((x) << S_ENABLE_PCMD_SFIFO_3)
+#define F_ENABLE_PCMD_SFIFO_3    V_ENABLE_PCMD_SFIFO_3(1U)
+
+#define S_ENABLE_PCMD_FIFO_3    29
+#define V_ENABLE_PCMD_FIFO_3(x) ((x) << S_ENABLE_PCMD_FIFO_3)
+#define F_ENABLE_PCMD_FIFO_3    V_ENABLE_PCMD_FIFO_3(1U)
+
+#define S_ENABLE_PCMD_DDP_HINT_3    28
+#define V_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_ENABLE_PCMD_DDP_HINT_3)
+#define F_ENABLE_PCMD_DDP_HINT_3    V_ENABLE_PCMD_DDP_HINT_3(1U)
+
+#define S_ENABLE_PCMD_TPT_3    27
+#define V_ENABLE_PCMD_TPT_3(x) ((x) << S_ENABLE_PCMD_TPT_3)
+#define F_ENABLE_PCMD_TPT_3    V_ENABLE_PCMD_TPT_3(1U)
+
+#define S_ENABLE_PCMD_DDP_3    26
+#define V_ENABLE_PCMD_DDP_3(x) ((x) << S_ENABLE_PCMD_DDP_3)
+#define F_ENABLE_PCMD_DDP_3    V_ENABLE_PCMD_DDP_3(1U)
+
+#define S_ENABLE_PCMD_MPAR_3    25
+#define V_ENABLE_PCMD_MPAR_3(x) ((x) << S_ENABLE_PCMD_MPAR_3)
+#define F_ENABLE_PCMD_MPAR_3    V_ENABLE_PCMD_MPAR_3(1U)
+
+#define S_ENABLE_PCMD_MPAC_3    24
+#define V_ENABLE_PCMD_MPAC_3(x) ((x) << S_ENABLE_PCMD_MPAC_3)
+#define F_ENABLE_PCMD_MPAC_3    V_ENABLE_PCMD_MPAC_3(1U)
+
+#define S_ENABLE_PCMD_SFIFO_2    22
+#define V_ENABLE_PCMD_SFIFO_2(x) ((x) << S_ENABLE_PCMD_SFIFO_2)
+#define F_ENABLE_PCMD_SFIFO_2    V_ENABLE_PCMD_SFIFO_2(1U)
+
+#define S_ENABLE_PCMD_FIFO_2    21
+#define V_ENABLE_PCMD_FIFO_2(x) ((x) << S_ENABLE_PCMD_FIFO_2)
+#define F_ENABLE_PCMD_FIFO_2    V_ENABLE_PCMD_FIFO_2(1U)
+
+#define S_ENABLE_PCMD_DDP_HINT_2    20
+#define V_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_ENABLE_PCMD_DDP_HINT_2)
+#define F_ENABLE_PCMD_DDP_HINT_2    V_ENABLE_PCMD_DDP_HINT_2(1U)
+
+#define S_ENABLE_PCMD_TPT_2    19
+#define V_ENABLE_PCMD_TPT_2(x) ((x) << S_ENABLE_PCMD_TPT_2)
+#define F_ENABLE_PCMD_TPT_2    V_ENABLE_PCMD_TPT_2(1U)
+
+#define S_ENABLE_PCMD_DDP_2    18
+#define V_ENABLE_PCMD_DDP_2(x) ((x) << S_ENABLE_PCMD_DDP_2)
+#define F_ENABLE_PCMD_DDP_2    V_ENABLE_PCMD_DDP_2(1U)
+
+#define S_ENABLE_PCMD_MPAR_2    17
+#define V_ENABLE_PCMD_MPAR_2(x) ((x) << S_ENABLE_PCMD_MPAR_2)
+#define F_ENABLE_PCMD_MPAR_2    V_ENABLE_PCMD_MPAR_2(1U)
+
+#define S_ENABLE_PCMD_MPAC_2    16
+#define V_ENABLE_PCMD_MPAC_2(x) ((x) << S_ENABLE_PCMD_MPAC_2)
+#define F_ENABLE_PCMD_MPAC_2    V_ENABLE_PCMD_MPAC_2(1U)
+
+#define S_ENABLE_PCMD_SFIFO_1    14
+#define V_ENABLE_PCMD_SFIFO_1(x) ((x) << S_ENABLE_PCMD_SFIFO_1)
+#define F_ENABLE_PCMD_SFIFO_1    V_ENABLE_PCMD_SFIFO_1(1U)
+
+#define S_ENABLE_PCMD_FIFO_1    13
+#define V_ENABLE_PCMD_FIFO_1(x) ((x) << S_ENABLE_PCMD_FIFO_1)
+#define F_ENABLE_PCMD_FIFO_1    V_ENABLE_PCMD_FIFO_1(1U)
+
+#define S_ENABLE_PCMD_DDP_HINT_1    12
+#define V_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_ENABLE_PCMD_DDP_HINT_1)
+#define F_ENABLE_PCMD_DDP_HINT_1    V_ENABLE_PCMD_DDP_HINT_1(1U)
+
+#define S_ENABLE_PCMD_TPT_1    11
+#define V_ENABLE_PCMD_TPT_1(x) ((x) << S_ENABLE_PCMD_TPT_1)
+#define F_ENABLE_PCMD_TPT_1    V_ENABLE_PCMD_TPT_1(1U)
+
+#define S_ENABLE_PCMD_DDP_1    10
+#define V_ENABLE_PCMD_DDP_1(x) ((x) << S_ENABLE_PCMD_DDP_1)
+#define F_ENABLE_PCMD_DDP_1    V_ENABLE_PCMD_DDP_1(1U)
+
+#define S_ENABLE_PCMD_MPAR_1    9
+#define V_ENABLE_PCMD_MPAR_1(x) ((x) << S_ENABLE_PCMD_MPAR_1)
+#define F_ENABLE_PCMD_MPAR_1    V_ENABLE_PCMD_MPAR_1(1U)
+
+#define S_ENABLE_PCMD_MPAC_1    8
+#define V_ENABLE_PCMD_MPAC_1(x) ((x) << S_ENABLE_PCMD_MPAC_1)
+#define F_ENABLE_PCMD_MPAC_1    V_ENABLE_PCMD_MPAC_1(1U)
+
+#define S_ENABLE_PCMD_SFIFO_0    6
+#define V_ENABLE_PCMD_SFIFO_0(x) ((x) << S_ENABLE_PCMD_SFIFO_0)
+#define F_ENABLE_PCMD_SFIFO_0    V_ENABLE_PCMD_SFIFO_0(1U)
+
+#define S_ENABLE_PCMD_FIFO_0    5
+#define V_ENABLE_PCMD_FIFO_0(x) ((x) << S_ENABLE_PCMD_FIFO_0)
+#define F_ENABLE_PCMD_FIFO_0    V_ENABLE_PCMD_FIFO_0(1U)
+
+#define S_ENABLE_PCMD_DDP_HINT_0    4
+#define V_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_ENABLE_PCMD_DDP_HINT_0)
+#define F_ENABLE_PCMD_DDP_HINT_0    V_ENABLE_PCMD_DDP_HINT_0(1U)
+
+#define S_ENABLE_PCMD_TPT_0    3
+#define V_ENABLE_PCMD_TPT_0(x) ((x) << S_ENABLE_PCMD_TPT_0)
+#define F_ENABLE_PCMD_TPT_0    V_ENABLE_PCMD_TPT_0(1U)
+
+#define S_ENABLE_PCMD_DDP_0    2
+#define V_ENABLE_PCMD_DDP_0(x) ((x) << S_ENABLE_PCMD_DDP_0)
+#define F_ENABLE_PCMD_DDP_0    V_ENABLE_PCMD_DDP_0(1U)
+
+#define S_ENABLE_PCMD_MPAR_0    1
+#define V_ENABLE_PCMD_MPAR_0(x) ((x) << S_ENABLE_PCMD_MPAR_0)
+#define F_ENABLE_PCMD_MPAR_0    V_ENABLE_PCMD_MPAR_0(1U)
+
+#define S_ENABLE_PCMD_MPAC_0    0
+#define V_ENABLE_PCMD_MPAC_0(x) ((x) << S_ENABLE_PCMD_MPAC_0)
+#define F_ENABLE_PCMD_MPAC_0    V_ENABLE_PCMD_MPAC_0(1U)
+
+#define A_ULP_RX_INT_CAUSE_PCMD 0x19304
+
+#define S_CAUSE_PCMD_SFIFO_3    30
+#define V_CAUSE_PCMD_SFIFO_3(x) ((x) << S_CAUSE_PCMD_SFIFO_3)
+#define F_CAUSE_PCMD_SFIFO_3    V_CAUSE_PCMD_SFIFO_3(1U)
+
+#define S_CAUSE_PCMD_FIFO_3    29
+#define V_CAUSE_PCMD_FIFO_3(x) ((x) << S_CAUSE_PCMD_FIFO_3)
+#define F_CAUSE_PCMD_FIFO_3    V_CAUSE_PCMD_FIFO_3(1U)
+
+#define S_CAUSE_PCMD_DDP_HINT_3    28
+#define V_CAUSE_PCMD_DDP_HINT_3(x) ((x) << S_CAUSE_PCMD_DDP_HINT_3)
+#define F_CAUSE_PCMD_DDP_HINT_3    V_CAUSE_PCMD_DDP_HINT_3(1U)
+
+#define S_CAUSE_PCMD_TPT_3    27
+#define V_CAUSE_PCMD_TPT_3(x) ((x) << S_CAUSE_PCMD_TPT_3)
+#define F_CAUSE_PCMD_TPT_3    V_CAUSE_PCMD_TPT_3(1U)
+
+#define S_CAUSE_PCMD_DDP_3    26
+#define V_CAUSE_PCMD_DDP_3(x) ((x) << S_CAUSE_PCMD_DDP_3)
+#define F_CAUSE_PCMD_DDP_3    V_CAUSE_PCMD_DDP_3(1U)
+
+#define S_CAUSE_PCMD_MPAR_3    25
+#define V_CAUSE_PCMD_MPAR_3(x) ((x) << S_CAUSE_PCMD_MPAR_3)
+#define F_CAUSE_PCMD_MPAR_3    V_CAUSE_PCMD_MPAR_3(1U)
+
+#define S_CAUSE_PCMD_MPAC_3    24
+#define V_CAUSE_PCMD_MPAC_3(x) ((x) << S_CAUSE_PCMD_MPAC_3)
+#define F_CAUSE_PCMD_MPAC_3    V_CAUSE_PCMD_MPAC_3(1U)
+
+#define S_CAUSE_PCMD_SFIFO_2    22
+#define V_CAUSE_PCMD_SFIFO_2(x) ((x) << S_CAUSE_PCMD_SFIFO_2)
+#define F_CAUSE_PCMD_SFIFO_2    V_CAUSE_PCMD_SFIFO_2(1U)
+
+#define S_CAUSE_PCMD_FIFO_2    21
+#define V_CAUSE_PCMD_FIFO_2(x) ((x) << S_CAUSE_PCMD_FIFO_2)
+#define F_CAUSE_PCMD_FIFO_2    V_CAUSE_PCMD_FIFO_2(1U)
+
+#define S_CAUSE_PCMD_DDP_HINT_2    20
+#define V_CAUSE_PCMD_DDP_HINT_2(x) ((x) << S_CAUSE_PCMD_DDP_HINT_2)
+#define F_CAUSE_PCMD_DDP_HINT_2    V_CAUSE_PCMD_DDP_HINT_2(1U)
+
+#define S_CAUSE_PCMD_TPT_2    19
+#define V_CAUSE_PCMD_TPT_2(x) ((x) << S_CAUSE_PCMD_TPT_2)
+#define F_CAUSE_PCMD_TPT_2    V_CAUSE_PCMD_TPT_2(1U)
+
+#define S_CAUSE_PCMD_DDP_2    18
+#define V_CAUSE_PCMD_DDP_2(x) ((x) << S_CAUSE_PCMD_DDP_2)
+#define F_CAUSE_PCMD_DDP_2    V_CAUSE_PCMD_DDP_2(1U)
+
+#define S_CAUSE_PCMD_MPAR_2    17
+#define V_CAUSE_PCMD_MPAR_2(x) ((x) << S_CAUSE_PCMD_MPAR_2)
+#define F_CAUSE_PCMD_MPAR_2    V_CAUSE_PCMD_MPAR_2(1U)
+
+#define S_CAUSE_PCMD_MPAC_2    16
+#define V_CAUSE_PCMD_MPAC_2(x) ((x) << S_CAUSE_PCMD_MPAC_2)
+#define F_CAUSE_PCMD_MPAC_2    V_CAUSE_PCMD_MPAC_2(1U)
+
+#define S_CAUSE_PCMD_SFIFO_1    14
+#define V_CAUSE_PCMD_SFIFO_1(x) ((x) << S_CAUSE_PCMD_SFIFO_1)
+#define F_CAUSE_PCMD_SFIFO_1    V_CAUSE_PCMD_SFIFO_1(1U)
+
+#define S_CAUSE_PCMD_FIFO_1    13
+#define V_CAUSE_PCMD_FIFO_1(x) ((x) << S_CAUSE_PCMD_FIFO_1)
+#define F_CAUSE_PCMD_FIFO_1    V_CAUSE_PCMD_FIFO_1(1U)
+
+#define S_CAUSE_PCMD_DDP_HINT_1    12
+#define V_CAUSE_PCMD_DDP_HINT_1(x) ((x) << S_CAUSE_PCMD_DDP_HINT_1)
+#define F_CAUSE_PCMD_DDP_HINT_1    V_CAUSE_PCMD_DDP_HINT_1(1U)
+
+#define S_CAUSE_PCMD_TPT_1    11
+#define V_CAUSE_PCMD_TPT_1(x) ((x) << S_CAUSE_PCMD_TPT_1)
+#define F_CAUSE_PCMD_TPT_1    V_CAUSE_PCMD_TPT_1(1U)
+
+#define S_CAUSE_PCMD_DDP_1    10
+#define V_CAUSE_PCMD_DDP_1(x) ((x) << S_CAUSE_PCMD_DDP_1)
+#define F_CAUSE_PCMD_DDP_1    V_CAUSE_PCMD_DDP_1(1U)
+
+#define S_CAUSE_PCMD_MPAR_1    9
+#define V_CAUSE_PCMD_MPAR_1(x) ((x) << S_CAUSE_PCMD_MPAR_1)
+#define F_CAUSE_PCMD_MPAR_1    V_CAUSE_PCMD_MPAR_1(1U)
+
+#define S_CAUSE_PCMD_MPAC_1    8
+#define V_CAUSE_PCMD_MPAC_1(x) ((x) << S_CAUSE_PCMD_MPAC_1)
+#define F_CAUSE_PCMD_MPAC_1    V_CAUSE_PCMD_MPAC_1(1U)
+
+#define S_CAUSE_PCMD_SFIFO_0    6
+#define V_CAUSE_PCMD_SFIFO_0(x) ((x) << S_CAUSE_PCMD_SFIFO_0)
+#define F_CAUSE_PCMD_SFIFO_0    V_CAUSE_PCMD_SFIFO_0(1U)
+
+#define S_CAUSE_PCMD_FIFO_0    5
+#define V_CAUSE_PCMD_FIFO_0(x) ((x) << S_CAUSE_PCMD_FIFO_0)
+#define F_CAUSE_PCMD_FIFO_0    V_CAUSE_PCMD_FIFO_0(1U)
+
+#define S_CAUSE_PCMD_DDP_HINT_0    4
+#define V_CAUSE_PCMD_DDP_HINT_0(x) ((x) << S_CAUSE_PCMD_DDP_HINT_0)
+#define F_CAUSE_PCMD_DDP_HINT_0    V_CAUSE_PCMD_DDP_HINT_0(1U)
+
+#define S_CAUSE_PCMD_TPT_0    3
+#define V_CAUSE_PCMD_TPT_0(x) ((x) << S_CAUSE_PCMD_TPT_0)
+#define F_CAUSE_PCMD_TPT_0    V_CAUSE_PCMD_TPT_0(1U)
+
+#define S_CAUSE_PCMD_DDP_0    2
+#define V_CAUSE_PCMD_DDP_0(x) ((x) << S_CAUSE_PCMD_DDP_0)
+#define F_CAUSE_PCMD_DDP_0    V_CAUSE_PCMD_DDP_0(1U)
+
+#define S_CAUSE_PCMD_MPAR_0    1
+#define V_CAUSE_PCMD_MPAR_0(x) ((x) << S_CAUSE_PCMD_MPAR_0)
+#define F_CAUSE_PCMD_MPAR_0    V_CAUSE_PCMD_MPAR_0(1U)
+
+#define S_CAUSE_PCMD_MPAC_0    0
+#define V_CAUSE_PCMD_MPAC_0(x) ((x) << S_CAUSE_PCMD_MPAC_0)
+#define F_CAUSE_PCMD_MPAC_0    V_CAUSE_PCMD_MPAC_0(1U)
+
+#define A_ULP_RX_PERR_ENABLE_PCMD 0x19308
+
+#define S_PERR_ENABLE_PCMD_SFIFO_3    30
+#define V_PERR_ENABLE_PCMD_SFIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_3)
+#define F_PERR_ENABLE_PCMD_SFIFO_3    V_PERR_ENABLE_PCMD_SFIFO_3(1U)
+
+#define S_PERR_ENABLE_PCMD_FIFO_3    29
+#define V_PERR_ENABLE_PCMD_FIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_3)
+#define F_PERR_ENABLE_PCMD_FIFO_3    V_PERR_ENABLE_PCMD_FIFO_3(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_HINT_3    28
+#define V_PERR_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_3)
+#define F_PERR_ENABLE_PCMD_DDP_HINT_3    V_PERR_ENABLE_PCMD_DDP_HINT_3(1U)
+
+#define S_PERR_ENABLE_PCMD_TPT_3    27
+#define V_PERR_ENABLE_PCMD_TPT_3(x) ((x) << S_PERR_ENABLE_PCMD_TPT_3)
+#define F_PERR_ENABLE_PCMD_TPT_3    V_PERR_ENABLE_PCMD_TPT_3(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_3    26
+#define V_PERR_ENABLE_PCMD_DDP_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_3)
+#define F_PERR_ENABLE_PCMD_DDP_3    V_PERR_ENABLE_PCMD_DDP_3(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAR_3    25
+#define V_PERR_ENABLE_PCMD_MPAR_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_3)
+#define F_PERR_ENABLE_PCMD_MPAR_3    V_PERR_ENABLE_PCMD_MPAR_3(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAC_3    24
+#define V_PERR_ENABLE_PCMD_MPAC_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_3)
+#define F_PERR_ENABLE_PCMD_MPAC_3    V_PERR_ENABLE_PCMD_MPAC_3(1U)
+
+#define S_PERR_ENABLE_PCMD_SFIFO_2    22
+#define V_PERR_ENABLE_PCMD_SFIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_2)
+#define F_PERR_ENABLE_PCMD_SFIFO_2    V_PERR_ENABLE_PCMD_SFIFO_2(1U)
+
+#define S_PERR_ENABLE_PCMD_FIFO_2    21
+#define V_PERR_ENABLE_PCMD_FIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_2)
+#define F_PERR_ENABLE_PCMD_FIFO_2    V_PERR_ENABLE_PCMD_FIFO_2(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_HINT_2    20
+#define V_PERR_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_2)
+#define F_PERR_ENABLE_PCMD_DDP_HINT_2    V_PERR_ENABLE_PCMD_DDP_HINT_2(1U)
+
+#define S_PERR_ENABLE_PCMD_TPT_2    19
+#define V_PERR_ENABLE_PCMD_TPT_2(x) ((x) << S_PERR_ENABLE_PCMD_TPT_2)
+#define F_PERR_ENABLE_PCMD_TPT_2    V_PERR_ENABLE_PCMD_TPT_2(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_2    18
+#define V_PERR_ENABLE_PCMD_DDP_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_2)
+#define F_PERR_ENABLE_PCMD_DDP_2    V_PERR_ENABLE_PCMD_DDP_2(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAR_2    17
+#define V_PERR_ENABLE_PCMD_MPAR_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_2)
+#define F_PERR_ENABLE_PCMD_MPAR_2    V_PERR_ENABLE_PCMD_MPAR_2(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAC_2    16
+#define V_PERR_ENABLE_PCMD_MPAC_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_2)
+#define F_PERR_ENABLE_PCMD_MPAC_2    V_PERR_ENABLE_PCMD_MPAC_2(1U)
+
+#define S_PERR_ENABLE_PCMD_SFIFO_1    14
+#define V_PERR_ENABLE_PCMD_SFIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_1)
+#define F_PERR_ENABLE_PCMD_SFIFO_1    V_PERR_ENABLE_PCMD_SFIFO_1(1U)
+
+#define S_PERR_ENABLE_PCMD_FIFO_1    13
+#define V_PERR_ENABLE_PCMD_FIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_1)
+#define F_PERR_ENABLE_PCMD_FIFO_1    V_PERR_ENABLE_PCMD_FIFO_1(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_HINT_1    12
+#define V_PERR_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_1)
+#define F_PERR_ENABLE_PCMD_DDP_HINT_1    V_PERR_ENABLE_PCMD_DDP_HINT_1(1U)
+
+#define S_PERR_ENABLE_PCMD_TPT_1    11
+#define V_PERR_ENABLE_PCMD_TPT_1(x) ((x) << S_PERR_ENABLE_PCMD_TPT_1)
+#define F_PERR_ENABLE_PCMD_TPT_1    V_PERR_ENABLE_PCMD_TPT_1(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_1    10
+#define V_PERR_ENABLE_PCMD_DDP_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_1)
+#define F_PERR_ENABLE_PCMD_DDP_1    V_PERR_ENABLE_PCMD_DDP_1(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAR_1    9
+#define V_PERR_ENABLE_PCMD_MPAR_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_1)
+#define F_PERR_ENABLE_PCMD_MPAR_1    V_PERR_ENABLE_PCMD_MPAR_1(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAC_1    8
+#define V_PERR_ENABLE_PCMD_MPAC_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_1)
+#define F_PERR_ENABLE_PCMD_MPAC_1    V_PERR_ENABLE_PCMD_MPAC_1(1U)
+
+#define S_PERR_ENABLE_PCMD_SFIFO_0    6
+#define V_PERR_ENABLE_PCMD_SFIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_0)
+#define F_PERR_ENABLE_PCMD_SFIFO_0    V_PERR_ENABLE_PCMD_SFIFO_0(1U)
+
+#define S_PERR_ENABLE_PCMD_FIFO_0    5
+#define V_PERR_ENABLE_PCMD_FIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_0)
+#define F_PERR_ENABLE_PCMD_FIFO_0    V_PERR_ENABLE_PCMD_FIFO_0(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_HINT_0    4
+#define V_PERR_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_0)
+#define F_PERR_ENABLE_PCMD_DDP_HINT_0    V_PERR_ENABLE_PCMD_DDP_HINT_0(1U)
+
+#define S_PERR_ENABLE_PCMD_TPT_0    3
+#define V_PERR_ENABLE_PCMD_TPT_0(x) ((x) << S_PERR_ENABLE_PCMD_TPT_0)
+#define F_PERR_ENABLE_PCMD_TPT_0    V_PERR_ENABLE_PCMD_TPT_0(1U)
+
+#define S_PERR_ENABLE_PCMD_DDP_0    2
+#define V_PERR_ENABLE_PCMD_DDP_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_0)
+#define F_PERR_ENABLE_PCMD_DDP_0    V_PERR_ENABLE_PCMD_DDP_0(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAR_0    1
+#define V_PERR_ENABLE_PCMD_MPAR_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_0)
+#define F_PERR_ENABLE_PCMD_MPAR_0    V_PERR_ENABLE_PCMD_MPAR_0(1U)
+
+#define S_PERR_ENABLE_PCMD_MPAC_0    0
+#define V_PERR_ENABLE_PCMD_MPAC_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_0)
+#define F_PERR_ENABLE_PCMD_MPAC_0    V_PERR_ENABLE_PCMD_MPAC_0(1U)
+
+#define A_ULP_RX_INT_ENABLE_DATA 0x19310
+
+#define S_ENABLE_DATA_SNOOP_3    29
+#define V_ENABLE_DATA_SNOOP_3(x) ((x) << S_ENABLE_DATA_SNOOP_3)
+#define F_ENABLE_DATA_SNOOP_3    V_ENABLE_DATA_SNOOP_3(1U)
+
+#define S_ENABLE_DATA_SFIFO_3    28
+#define V_ENABLE_DATA_SFIFO_3(x) ((x) << S_ENABLE_DATA_SFIFO_3)
+#define F_ENABLE_DATA_SFIFO_3    V_ENABLE_DATA_SFIFO_3(1U)
+
+#define S_ENABLE_DATA_FIFO_3    27
+#define V_ENABLE_DATA_FIFO_3(x) ((x) << S_ENABLE_DATA_FIFO_3)
+#define F_ENABLE_DATA_FIFO_3    V_ENABLE_DATA_FIFO_3(1U)
+
+#define S_ENABLE_DATA_DDP_3    26
+#define V_ENABLE_DATA_DDP_3(x) ((x) << S_ENABLE_DATA_DDP_3)
+#define F_ENABLE_DATA_DDP_3    V_ENABLE_DATA_DDP_3(1U)
+
+#define S_ENABLE_DATA_CTX_3    25
+#define V_ENABLE_DATA_CTX_3(x) ((x) << S_ENABLE_DATA_CTX_3)
+#define F_ENABLE_DATA_CTX_3    V_ENABLE_DATA_CTX_3(1U)
+
+#define S_ENABLE_DATA_PARSER_3    24
+#define V_ENABLE_DATA_PARSER_3(x) ((x) << S_ENABLE_DATA_PARSER_3)
+#define F_ENABLE_DATA_PARSER_3    V_ENABLE_DATA_PARSER_3(1U)
+
+#define S_ENABLE_DATA_SNOOP_2    21
+#define V_ENABLE_DATA_SNOOP_2(x) ((x) << S_ENABLE_DATA_SNOOP_2)
+#define F_ENABLE_DATA_SNOOP_2    V_ENABLE_DATA_SNOOP_2(1U)
+
+#define S_ENABLE_DATA_SFIFO_2    20
+#define V_ENABLE_DATA_SFIFO_2(x) ((x) << S_ENABLE_DATA_SFIFO_2)
+#define F_ENABLE_DATA_SFIFO_2    V_ENABLE_DATA_SFIFO_2(1U)
+
+#define S_ENABLE_DATA_FIFO_2    19
+#define V_ENABLE_DATA_FIFO_2(x) ((x) << S_ENABLE_DATA_FIFO_2)
+#define F_ENABLE_DATA_FIFO_2    V_ENABLE_DATA_FIFO_2(1U)
+
+#define S_ENABLE_DATA_DDP_2    18
+#define V_ENABLE_DATA_DDP_2(x) ((x) << S_ENABLE_DATA_DDP_2)
+#define F_ENABLE_DATA_DDP_2    V_ENABLE_DATA_DDP_2(1U)
+
+#define S_ENABLE_DATA_CTX_2    17
+#define V_ENABLE_DATA_CTX_2(x) ((x) << S_ENABLE_DATA_CTX_2)
+#define F_ENABLE_DATA_CTX_2    V_ENABLE_DATA_CTX_2(1U)
+
+#define S_ENABLE_DATA_PARSER_2    16
+#define V_ENABLE_DATA_PARSER_2(x) ((x) << S_ENABLE_DATA_PARSER_2)
+#define F_ENABLE_DATA_PARSER_2    V_ENABLE_DATA_PARSER_2(1U)
+
+#define S_ENABLE_DATA_SNOOP_1    13
+#define V_ENABLE_DATA_SNOOP_1(x) ((x) << S_ENABLE_DATA_SNOOP_1)
+#define F_ENABLE_DATA_SNOOP_1    V_ENABLE_DATA_SNOOP_1(1U)
+
+#define S_ENABLE_DATA_SFIFO_1    12
+#define V_ENABLE_DATA_SFIFO_1(x) ((x) << S_ENABLE_DATA_SFIFO_1)
+#define F_ENABLE_DATA_SFIFO_1    V_ENABLE_DATA_SFIFO_1(1U)
+
+#define S_ENABLE_DATA_FIFO_1    11
+#define V_ENABLE_DATA_FIFO_1(x) ((x) << S_ENABLE_DATA_FIFO_1)
+#define F_ENABLE_DATA_FIFO_1    V_ENABLE_DATA_FIFO_1(1U)
+
+#define S_ENABLE_DATA_DDP_1    10
+#define V_ENABLE_DATA_DDP_1(x) ((x) << S_ENABLE_DATA_DDP_1)
+#define F_ENABLE_DATA_DDP_1    V_ENABLE_DATA_DDP_1(1U)
+
+#define S_ENABLE_DATA_CTX_1    9
+#define V_ENABLE_DATA_CTX_1(x) ((x) << S_ENABLE_DATA_CTX_1)
+#define F_ENABLE_DATA_CTX_1    V_ENABLE_DATA_CTX_1(1U)
+
+#define S_ENABLE_DATA_PARSER_1    8
+#define V_ENABLE_DATA_PARSER_1(x) ((x) << S_ENABLE_DATA_PARSER_1)
+#define F_ENABLE_DATA_PARSER_1    V_ENABLE_DATA_PARSER_1(1U)
+
+#define S_ENABLE_DATA_SNOOP_0    5
+#define V_ENABLE_DATA_SNOOP_0(x) ((x) << S_ENABLE_DATA_SNOOP_0)
+#define F_ENABLE_DATA_SNOOP_0    V_ENABLE_DATA_SNOOP_0(1U)
+
+#define S_ENABLE_DATA_SFIFO_0    4
+#define V_ENABLE_DATA_SFIFO_0(x) ((x) << S_ENABLE_DATA_SFIFO_0)
+#define F_ENABLE_DATA_SFIFO_0    V_ENABLE_DATA_SFIFO_0(1U)
+
+#define S_ENABLE_DATA_FIFO_0    3
+#define V_ENABLE_DATA_FIFO_0(x) ((x) << S_ENABLE_DATA_FIFO_0)
+#define F_ENABLE_DATA_FIFO_0    V_ENABLE_DATA_FIFO_0(1U)
+
+#define S_ENABLE_DATA_DDP_0    2
+#define V_ENABLE_DATA_DDP_0(x) ((x) << S_ENABLE_DATA_DDP_0)
+#define F_ENABLE_DATA_DDP_0    V_ENABLE_DATA_DDP_0(1U)
+
+#define S_ENABLE_DATA_CTX_0    1
+#define V_ENABLE_DATA_CTX_0(x) ((x) << S_ENABLE_DATA_CTX_0)
+#define F_ENABLE_DATA_CTX_0    V_ENABLE_DATA_CTX_0(1U)
+
+#define S_ENABLE_DATA_PARSER_0    0
+#define V_ENABLE_DATA_PARSER_0(x) ((x) << S_ENABLE_DATA_PARSER_0)
+#define F_ENABLE_DATA_PARSER_0    V_ENABLE_DATA_PARSER_0(1U)
+
+#define A_ULP_RX_INT_CAUSE_DATA 0x19314
+
+#define S_CAUSE_DATA_SNOOP_3    29
+#define V_CAUSE_DATA_SNOOP_3(x) ((x) << S_CAUSE_DATA_SNOOP_3)
+#define F_CAUSE_DATA_SNOOP_3    V_CAUSE_DATA_SNOOP_3(1U)
+
+#define S_CAUSE_DATA_SFIFO_3    28
+#define V_CAUSE_DATA_SFIFO_3(x) ((x) << S_CAUSE_DATA_SFIFO_3)
+#define F_CAUSE_DATA_SFIFO_3    V_CAUSE_DATA_SFIFO_3(1U)
+
+#define S_CAUSE_DATA_FIFO_3    27
+#define V_CAUSE_DATA_FIFO_3(x) ((x) << S_CAUSE_DATA_FIFO_3)
+#define F_CAUSE_DATA_FIFO_3    V_CAUSE_DATA_FIFO_3(1U)
+
+#define S_CAUSE_DATA_DDP_3    26
+#define V_CAUSE_DATA_DDP_3(x) ((x) << S_CAUSE_DATA_DDP_3)
+#define F_CAUSE_DATA_DDP_3    V_CAUSE_DATA_DDP_3(1U)
+
+#define S_CAUSE_DATA_CTX_3    25
+#define V_CAUSE_DATA_CTX_3(x) ((x) << S_CAUSE_DATA_CTX_3)
+#define F_CAUSE_DATA_CTX_3    V_CAUSE_DATA_CTX_3(1U)
+
+#define S_CAUSE_DATA_PARSER_3    24
+#define V_CAUSE_DATA_PARSER_3(x) ((x) << S_CAUSE_DATA_PARSER_3)
+#define F_CAUSE_DATA_PARSER_3    V_CAUSE_DATA_PARSER_3(1U)
+
+#define S_CAUSE_DATA_SNOOP_2    21
+#define V_CAUSE_DATA_SNOOP_2(x) ((x) << S_CAUSE_DATA_SNOOP_2)
+#define F_CAUSE_DATA_SNOOP_2    V_CAUSE_DATA_SNOOP_2(1U)
+
+#define S_CAUSE_DATA_SFIFO_2    20
+#define V_CAUSE_DATA_SFIFO_2(x) ((x) << S_CAUSE_DATA_SFIFO_2)
+#define F_CAUSE_DATA_SFIFO_2    V_CAUSE_DATA_SFIFO_2(1U)
+
+#define S_CAUSE_DATA_FIFO_2    19
+#define V_CAUSE_DATA_FIFO_2(x) ((x) << S_CAUSE_DATA_FIFO_2)
+#define F_CAUSE_DATA_FIFO_2    V_CAUSE_DATA_FIFO_2(1U)
+
+#define S_CAUSE_DATA_DDP_2    18
+#define V_CAUSE_DATA_DDP_2(x) ((x) << S_CAUSE_DATA_DDP_2)
+#define F_CAUSE_DATA_DDP_2    V_CAUSE_DATA_DDP_2(1U)
+
+#define S_CAUSE_DATA_CTX_2    17
+#define V_CAUSE_DATA_CTX_2(x) ((x) << S_CAUSE_DATA_CTX_2)
+#define F_CAUSE_DATA_CTX_2    V_CAUSE_DATA_CTX_2(1U)
+
+#define S_CAUSE_DATA_PARSER_2    16
+#define V_CAUSE_DATA_PARSER_2(x) ((x) << S_CAUSE_DATA_PARSER_2)
+#define F_CAUSE_DATA_PARSER_2    V_CAUSE_DATA_PARSER_2(1U)
+
+#define S_CAUSE_DATA_SNOOP_1    13
+#define V_CAUSE_DATA_SNOOP_1(x) ((x) << S_CAUSE_DATA_SNOOP_1)
+#define F_CAUSE_DATA_SNOOP_1    V_CAUSE_DATA_SNOOP_1(1U)
+
+#define S_CAUSE_DATA_SFIFO_1    12
+#define V_CAUSE_DATA_SFIFO_1(x) ((x) << S_CAUSE_DATA_SFIFO_1)
+#define F_CAUSE_DATA_SFIFO_1    V_CAUSE_DATA_SFIFO_1(1U)
+
+#define S_CAUSE_DATA_FIFO_1    11
+#define V_CAUSE_DATA_FIFO_1(x) ((x) << S_CAUSE_DATA_FIFO_1)
+#define F_CAUSE_DATA_FIFO_1    V_CAUSE_DATA_FIFO_1(1U)
+
+#define S_CAUSE_DATA_DDP_1    10
+#define V_CAUSE_DATA_DDP_1(x) ((x) << S_CAUSE_DATA_DDP_1)
+#define F_CAUSE_DATA_DDP_1    V_CAUSE_DATA_DDP_1(1U)
+
+#define S_CAUSE_DATA_CTX_1    9
+#define V_CAUSE_DATA_CTX_1(x) ((x) << S_CAUSE_DATA_CTX_1)
+#define F_CAUSE_DATA_CTX_1    V_CAUSE_DATA_CTX_1(1U)
+
+#define S_CAUSE_DATA_PARSER_1    8
+#define V_CAUSE_DATA_PARSER_1(x) ((x) << S_CAUSE_DATA_PARSER_1)
+#define F_CAUSE_DATA_PARSER_1    V_CAUSE_DATA_PARSER_1(1U)
+
+#define S_CAUSE_DATA_SNOOP_0    5
+#define V_CAUSE_DATA_SNOOP_0(x) ((x) << S_CAUSE_DATA_SNOOP_0)
+#define F_CAUSE_DATA_SNOOP_0    V_CAUSE_DATA_SNOOP_0(1U)
+
+#define S_CAUSE_DATA_SFIFO_0    4
+#define V_CAUSE_DATA_SFIFO_0(x) ((x) << S_CAUSE_DATA_SFIFO_0)
+#define F_CAUSE_DATA_SFIFO_0    V_CAUSE_DATA_SFIFO_0(1U)
+
+#define S_CAUSE_DATA_FIFO_0    3
+#define V_CAUSE_DATA_FIFO_0(x) ((x) << S_CAUSE_DATA_FIFO_0)
+#define F_CAUSE_DATA_FIFO_0    V_CAUSE_DATA_FIFO_0(1U)
+
+#define S_CAUSE_DATA_DDP_0    2
+#define V_CAUSE_DATA_DDP_0(x) ((x) << S_CAUSE_DATA_DDP_0)
+#define F_CAUSE_DATA_DDP_0    V_CAUSE_DATA_DDP_0(1U)
+
+#define S_CAUSE_DATA_CTX_0    1
+#define V_CAUSE_DATA_CTX_0(x) ((x) << S_CAUSE_DATA_CTX_0)
+#define F_CAUSE_DATA_CTX_0    V_CAUSE_DATA_CTX_0(1U)
+
+#define S_CAUSE_DATA_PARSER_0    0
+#define V_CAUSE_DATA_PARSER_0(x) ((x) << S_CAUSE_DATA_PARSER_0)
+#define F_CAUSE_DATA_PARSER_0    V_CAUSE_DATA_PARSER_0(1U)
+
+#define A_ULP_RX_PERR_ENABLE_DATA 0x19318
+
+#define S_PERR_ENABLE_DATA_SNOOP_3    29
+#define V_PERR_ENABLE_DATA_SNOOP_3(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_3)
+#define F_PERR_ENABLE_DATA_SNOOP_3    V_PERR_ENABLE_DATA_SNOOP_3(1U)
+
+#define S_PERR_ENABLE_DATA_SFIFO_3    28
+#define V_PERR_ENABLE_DATA_SFIFO_3(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_3)
+#define F_PERR_ENABLE_DATA_SFIFO_3    V_PERR_ENABLE_DATA_SFIFO_3(1U)
+
+#define S_PERR_ENABLE_DATA_FIFO_3    27
+#define V_PERR_ENABLE_DATA_FIFO_3(x) ((x) << S_PERR_ENABLE_DATA_FIFO_3)
+#define F_PERR_ENABLE_DATA_FIFO_3    V_PERR_ENABLE_DATA_FIFO_3(1U)
+
+#define S_PERR_ENABLE_DATA_DDP_3    26
+#define V_PERR_ENABLE_DATA_DDP_3(x) ((x) << S_PERR_ENABLE_DATA_DDP_3)
+#define F_PERR_ENABLE_DATA_DDP_3    V_PERR_ENABLE_DATA_DDP_3(1U)
+
+#define S_PERR_ENABLE_DATA_CTX_3    25
+#define V_PERR_ENABLE_DATA_CTX_3(x) ((x) << S_PERR_ENABLE_DATA_CTX_3)
+#define F_PERR_ENABLE_DATA_CTX_3    V_PERR_ENABLE_DATA_CTX_3(1U)
+
+#define S_PERR_ENABLE_DATA_PARSER_3    24
+#define V_PERR_ENABLE_DATA_PARSER_3(x) ((x) << S_PERR_ENABLE_DATA_PARSER_3)
+#define F_PERR_ENABLE_DATA_PARSER_3    V_PERR_ENABLE_DATA_PARSER_3(1U)
+
+#define S_PERR_ENABLE_DATA_SNOOP_2    21
+#define V_PERR_ENABLE_DATA_SNOOP_2(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_2)
+#define F_PERR_ENABLE_DATA_SNOOP_2    V_PERR_ENABLE_DATA_SNOOP_2(1U)
+
+#define S_PERR_ENABLE_DATA_SFIFO_2    20
+#define V_PERR_ENABLE_DATA_SFIFO_2(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_2)
+#define F_PERR_ENABLE_DATA_SFIFO_2    V_PERR_ENABLE_DATA_SFIFO_2(1U)
+
+#define S_PERR_ENABLE_DATA_FIFO_2    19
+#define V_PERR_ENABLE_DATA_FIFO_2(x) ((x) << S_PERR_ENABLE_DATA_FIFO_2)
+#define F_PERR_ENABLE_DATA_FIFO_2    V_PERR_ENABLE_DATA_FIFO_2(1U)
+
+#define S_PERR_ENABLE_DATA_DDP_2    18
+#define V_PERR_ENABLE_DATA_DDP_2(x) ((x) << S_PERR_ENABLE_DATA_DDP_2)
+#define F_PERR_ENABLE_DATA_DDP_2    V_PERR_ENABLE_DATA_DDP_2(1U)
+
+#define S_PERR_ENABLE_DATA_CTX_2    17
+#define V_PERR_ENABLE_DATA_CTX_2(x) ((x) << S_PERR_ENABLE_DATA_CTX_2)
+#define F_PERR_ENABLE_DATA_CTX_2    V_PERR_ENABLE_DATA_CTX_2(1U)
+
+#define S_PERR_ENABLE_DATA_PARSER_2    16
+#define V_PERR_ENABLE_DATA_PARSER_2(x) ((x) << S_PERR_ENABLE_DATA_PARSER_2)
+#define F_PERR_ENABLE_DATA_PARSER_2    V_PERR_ENABLE_DATA_PARSER_2(1U)
+
+#define S_PERR_ENABLE_DATA_SNOOP_1    13
+#define V_PERR_ENABLE_DATA_SNOOP_1(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_1)
+#define F_PERR_ENABLE_DATA_SNOOP_1    V_PERR_ENABLE_DATA_SNOOP_1(1U)
+
+#define S_PERR_ENABLE_DATA_SFIFO_1    12
+#define V_PERR_ENABLE_DATA_SFIFO_1(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_1)
+#define F_PERR_ENABLE_DATA_SFIFO_1    V_PERR_ENABLE_DATA_SFIFO_1(1U)
+
+#define S_PERR_ENABLE_DATA_FIFO_1    11
+#define V_PERR_ENABLE_DATA_FIFO_1(x) ((x) << S_PERR_ENABLE_DATA_FIFO_1)
+#define F_PERR_ENABLE_DATA_FIFO_1    V_PERR_ENABLE_DATA_FIFO_1(1U)
+
+#define S_PERR_ENABLE_DATA_DDP_1    10
+#define V_PERR_ENABLE_DATA_DDP_1(x) ((x) << S_PERR_ENABLE_DATA_DDP_1)
+#define F_PERR_ENABLE_DATA_DDP_1    V_PERR_ENABLE_DATA_DDP_1(1U)
+
+#define S_PERR_ENABLE_DATA_CTX_1    9
+#define V_PERR_ENABLE_DATA_CTX_1(x) ((x) << S_PERR_ENABLE_DATA_CTX_1)
+#define F_PERR_ENABLE_DATA_CTX_1    V_PERR_ENABLE_DATA_CTX_1(1U)
+
+#define S_PERR_ENABLE_DATA_PARSER_1    8
+#define V_PERR_ENABLE_DATA_PARSER_1(x) ((x) << S_PERR_ENABLE_DATA_PARSER_1)
+#define F_PERR_ENABLE_DATA_PARSER_1    V_PERR_ENABLE_DATA_PARSER_1(1U)
+
+#define S_PERR_ENABLE_DATA_SNOOP_0    5
+#define V_PERR_ENABLE_DATA_SNOOP_0(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_0)
+#define F_PERR_ENABLE_DATA_SNOOP_0    V_PERR_ENABLE_DATA_SNOOP_0(1U)
+
+#define S_PERR_ENABLE_DATA_SFIFO_0    4
+#define V_PERR_ENABLE_DATA_SFIFO_0(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_0)
+#define F_PERR_ENABLE_DATA_SFIFO_0    V_PERR_ENABLE_DATA_SFIFO_0(1U)
+
+#define S_PERR_ENABLE_DATA_FIFO_0    3
+#define V_PERR_ENABLE_DATA_FIFO_0(x) ((x) << S_PERR_ENABLE_DATA_FIFO_0)
+#define F_PERR_ENABLE_DATA_FIFO_0    V_PERR_ENABLE_DATA_FIFO_0(1U)
+
+#define S_PERR_ENABLE_DATA_DDP_0    2
+#define V_PERR_ENABLE_DATA_DDP_0(x) ((x) << S_PERR_ENABLE_DATA_DDP_0)
+#define F_PERR_ENABLE_DATA_DDP_0    V_PERR_ENABLE_DATA_DDP_0(1U)
+
+#define S_PERR_ENABLE_DATA_CTX_0    1
+#define V_PERR_ENABLE_DATA_CTX_0(x) ((x) << S_PERR_ENABLE_DATA_CTX_0)
+#define F_PERR_ENABLE_DATA_CTX_0    V_PERR_ENABLE_DATA_CTX_0(1U)
+
+#define S_PERR_ENABLE_DATA_PARSER_0    0
+#define V_PERR_ENABLE_DATA_PARSER_0(x) ((x) << S_PERR_ENABLE_DATA_PARSER_0)
+#define F_PERR_ENABLE_DATA_PARSER_0    V_PERR_ENABLE_DATA_PARSER_0(1U)
+
+#define A_ULP_RX_INT_ENABLE_ARB 0x19320
+
+#define S_ENABLE_ARB_PBL_PF_3    27
+#define V_ENABLE_ARB_PBL_PF_3(x) ((x) << S_ENABLE_ARB_PBL_PF_3)
+#define F_ENABLE_ARB_PBL_PF_3    V_ENABLE_ARB_PBL_PF_3(1U)
+
+#define S_ENABLE_ARB_PF_3    26
+#define V_ENABLE_ARB_PF_3(x) ((x) << S_ENABLE_ARB_PF_3)
+#define F_ENABLE_ARB_PF_3    V_ENABLE_ARB_PF_3(1U)
+
+#define S_ENABLE_ARB_TPT_PF_3    25
+#define V_ENABLE_ARB_TPT_PF_3(x) ((x) << S_ENABLE_ARB_TPT_PF_3)
+#define F_ENABLE_ARB_TPT_PF_3    V_ENABLE_ARB_TPT_PF_3(1U)
+
+#define S_ENABLE_ARB_F_3    24
+#define V_ENABLE_ARB_F_3(x) ((x) << S_ENABLE_ARB_F_3)
+#define F_ENABLE_ARB_F_3    V_ENABLE_ARB_F_3(1U)
+
+#define S_ENABLE_ARB_PBL_PF_2    19
+#define V_ENABLE_ARB_PBL_PF_2(x) ((x) << S_ENABLE_ARB_PBL_PF_2)
+#define F_ENABLE_ARB_PBL_PF_2    V_ENABLE_ARB_PBL_PF_2(1U)
+
+#define S_ENABLE_ARB_PF_2    18
+#define V_ENABLE_ARB_PF_2(x) ((x) << S_ENABLE_ARB_PF_2)
+#define F_ENABLE_ARB_PF_2    V_ENABLE_ARB_PF_2(1U)
+
+#define S_ENABLE_ARB_TPT_PF_2    17
+#define V_ENABLE_ARB_TPT_PF_2(x) ((x) << S_ENABLE_ARB_TPT_PF_2)
+#define F_ENABLE_ARB_TPT_PF_2    V_ENABLE_ARB_TPT_PF_2(1U)
+
+#define S_ENABLE_ARB_F_2    16
+#define V_ENABLE_ARB_F_2(x) ((x) << S_ENABLE_ARB_F_2)
+#define F_ENABLE_ARB_F_2    V_ENABLE_ARB_F_2(1U)
+
+#define S_ENABLE_ARB_PBL_PF_1    11
+#define V_ENABLE_ARB_PBL_PF_1(x) ((x) << S_ENABLE_ARB_PBL_PF_1)
+#define F_ENABLE_ARB_PBL_PF_1    V_ENABLE_ARB_PBL_PF_1(1U)
+
+#define S_ENABLE_ARB_PF_1    10
+#define V_ENABLE_ARB_PF_1(x) ((x) << S_ENABLE_ARB_PF_1)
+#define F_ENABLE_ARB_PF_1    V_ENABLE_ARB_PF_1(1U)
+
+#define S_ENABLE_ARB_TPT_PF_1    9
+#define V_ENABLE_ARB_TPT_PF_1(x) ((x) << S_ENABLE_ARB_TPT_PF_1)
+#define F_ENABLE_ARB_TPT_PF_1    V_ENABLE_ARB_TPT_PF_1(1U)
+
+#define S_ENABLE_ARB_F_1    8
+#define V_ENABLE_ARB_F_1(x) ((x) << S_ENABLE_ARB_F_1)
+#define F_ENABLE_ARB_F_1    V_ENABLE_ARB_F_1(1U)
+
+#define S_ENABLE_ARB_PBL_PF_0    3
+#define V_ENABLE_ARB_PBL_PF_0(x) ((x) << S_ENABLE_ARB_PBL_PF_0)
+#define F_ENABLE_ARB_PBL_PF_0    V_ENABLE_ARB_PBL_PF_0(1U)
+
+#define S_ENABLE_ARB_PF_0    2
+#define V_ENABLE_ARB_PF_0(x) ((x) << S_ENABLE_ARB_PF_0)
+#define F_ENABLE_ARB_PF_0    V_ENABLE_ARB_PF_0(1U)
+
+#define S_ENABLE_ARB_TPT_PF_0    1
+#define V_ENABLE_ARB_TPT_PF_0(x) ((x) << S_ENABLE_ARB_TPT_PF_0)
+#define F_ENABLE_ARB_TPT_PF_0    V_ENABLE_ARB_TPT_PF_0(1U)
+
+#define S_ENABLE_ARB_F_0    0
+#define V_ENABLE_ARB_F_0(x) ((x) << S_ENABLE_ARB_F_0)
+#define F_ENABLE_ARB_F_0    V_ENABLE_ARB_F_0(1U)
+
+#define A_ULP_RX_INT_CAUSE_ARB 0x19324
+
+#define S_CAUSE_ARB_PBL_PF_3    27
+#define V_CAUSE_ARB_PBL_PF_3(x) ((x) << S_CAUSE_ARB_PBL_PF_3)
+#define F_CAUSE_ARB_PBL_PF_3    V_CAUSE_ARB_PBL_PF_3(1U)
+
+#define S_CAUSE_ARB_PF_3    26
+#define V_CAUSE_ARB_PF_3(x) ((x) << S_CAUSE_ARB_PF_3)
+#define F_CAUSE_ARB_PF_3    V_CAUSE_ARB_PF_3(1U)
+
+#define S_CAUSE_ARB_TPT_PF_3    25
+#define V_CAUSE_ARB_TPT_PF_3(x) ((x) << S_CAUSE_ARB_TPT_PF_3)
+#define F_CAUSE_ARB_TPT_PF_3    V_CAUSE_ARB_TPT_PF_3(1U)
+
+#define S_CAUSE_ARB_F_3    24
+#define V_CAUSE_ARB_F_3(x) ((x) << S_CAUSE_ARB_F_3)
+#define F_CAUSE_ARB_F_3    V_CAUSE_ARB_F_3(1U)
+
+#define S_CAUSE_ARB_PBL_PF_2    19
+#define V_CAUSE_ARB_PBL_PF_2(x) ((x) << S_CAUSE_ARB_PBL_PF_2)
+#define F_CAUSE_ARB_PBL_PF_2    V_CAUSE_ARB_PBL_PF_2(1U)
+
+#define S_CAUSE_ARB_PF_2    18
+#define V_CAUSE_ARB_PF_2(x) ((x) << S_CAUSE_ARB_PF_2)
+#define F_CAUSE_ARB_PF_2    V_CAUSE_ARB_PF_2(1U)
+
+#define S_CAUSE_ARB_TPT_PF_2    17
+#define V_CAUSE_ARB_TPT_PF_2(x) ((x) << S_CAUSE_ARB_TPT_PF_2)
+#define F_CAUSE_ARB_TPT_PF_2    V_CAUSE_ARB_TPT_PF_2(1U)
+
+#define S_CAUSE_ARB_F_2    16
+#define V_CAUSE_ARB_F_2(x) ((x) << S_CAUSE_ARB_F_2)
+#define F_CAUSE_ARB_F_2    V_CAUSE_ARB_F_2(1U)
+
+#define S_CAUSE_ARB_PBL_PF_1    11
+#define V_CAUSE_ARB_PBL_PF_1(x) ((x) << S_CAUSE_ARB_PBL_PF_1)
+#define F_CAUSE_ARB_PBL_PF_1    V_CAUSE_ARB_PBL_PF_1(1U)
+
+#define S_CAUSE_ARB_PF_1    10
+#define V_CAUSE_ARB_PF_1(x) ((x) << S_CAUSE_ARB_PF_1)
+#define F_CAUSE_ARB_PF_1    V_CAUSE_ARB_PF_1(1U)
+
+#define S_CAUSE_ARB_TPT_PF_1    9
+#define V_CAUSE_ARB_TPT_PF_1(x) ((x) << S_CAUSE_ARB_TPT_PF_1)
+#define F_CAUSE_ARB_TPT_PF_1    V_CAUSE_ARB_TPT_PF_1(1U)
+
+#define S_CAUSE_ARB_F_1    8
+#define V_CAUSE_ARB_F_1(x) ((x) << S_CAUSE_ARB_F_1)
+#define F_CAUSE_ARB_F_1    V_CAUSE_ARB_F_1(1U)
+
+#define S_CAUSE_ARB_PBL_PF_0    3
+#define V_CAUSE_ARB_PBL_PF_0(x) ((x) << S_CAUSE_ARB_PBL_PF_0)
+#define F_CAUSE_ARB_PBL_PF_0    V_CAUSE_ARB_PBL_PF_0(1U)
+
+#define S_CAUSE_ARB_PF_0    2
+#define V_CAUSE_ARB_PF_0(x) ((x) << S_CAUSE_ARB_PF_0)
+#define F_CAUSE_ARB_PF_0    V_CAUSE_ARB_PF_0(1U)
+
+#define S_CAUSE_ARB_TPT_PF_0    1
+#define V_CAUSE_ARB_TPT_PF_0(x) ((x) << S_CAUSE_ARB_TPT_PF_0)
+#define F_CAUSE_ARB_TPT_PF_0    V_CAUSE_ARB_TPT_PF_0(1U)
+
+#define S_CAUSE_ARB_F_0    0
+#define V_CAUSE_ARB_F_0(x) ((x) << S_CAUSE_ARB_F_0)
+#define F_CAUSE_ARB_F_0    V_CAUSE_ARB_F_0(1U)
+
+#define A_ULP_RX_PERR_ENABLE_ARB 0x19328
+
+#define S_PERR_ENABLE_ARB_PBL_PF_3    27
+#define V_PERR_ENABLE_ARB_PBL_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_3)
+#define F_PERR_ENABLE_ARB_PBL_PF_3    V_PERR_ENABLE_ARB_PBL_PF_3(1U)
+
+#define S_PERR_ENABLE_ARB_PF_3    26
+#define V_PERR_ENABLE_ARB_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PF_3)
+#define F_PERR_ENABLE_ARB_PF_3    V_PERR_ENABLE_ARB_PF_3(1U)
+
+#define S_PERR_ENABLE_ARB_TPT_PF_3    25
+#define V_PERR_ENABLE_ARB_TPT_PF_3(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_3)
+#define F_PERR_ENABLE_ARB_TPT_PF_3    V_PERR_ENABLE_ARB_TPT_PF_3(1U)
+
+#define S_PERR_ENABLE_ARB_F_3    24
+#define V_PERR_ENABLE_ARB_F_3(x) ((x) << S_PERR_ENABLE_ARB_F_3)
+#define F_PERR_ENABLE_ARB_F_3    V_PERR_ENABLE_ARB_F_3(1U)
+
+#define S_PERR_ENABLE_ARB_PBL_PF_2    19
+#define V_PERR_ENABLE_ARB_PBL_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_2)
+#define F_PERR_ENABLE_ARB_PBL_PF_2    V_PERR_ENABLE_ARB_PBL_PF_2(1U)
+
+#define S_PERR_ENABLE_ARB_PF_2    18
+#define V_PERR_ENABLE_ARB_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PF_2)
+#define F_PERR_ENABLE_ARB_PF_2    V_PERR_ENABLE_ARB_PF_2(1U)
+
+#define S_PERR_ENABLE_ARB_TPT_PF_2    17
+#define V_PERR_ENABLE_ARB_TPT_PF_2(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_2)
+#define F_PERR_ENABLE_ARB_TPT_PF_2    V_PERR_ENABLE_ARB_TPT_PF_2(1U)
+
+#define S_PERR_ENABLE_ARB_F_2    16
+#define V_PERR_ENABLE_ARB_F_2(x) ((x) << S_PERR_ENABLE_ARB_F_2)
+#define F_PERR_ENABLE_ARB_F_2    V_PERR_ENABLE_ARB_F_2(1U)
+
+#define S_PERR_ENABLE_ARB_PBL_PF_1    11
+#define V_PERR_ENABLE_ARB_PBL_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_1)
+#define F_PERR_ENABLE_ARB_PBL_PF_1    V_PERR_ENABLE_ARB_PBL_PF_1(1U)
+
+#define S_PERR_ENABLE_ARB_PF_1    10
+#define V_PERR_ENABLE_ARB_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PF_1)
+#define F_PERR_ENABLE_ARB_PF_1    V_PERR_ENABLE_ARB_PF_1(1U)
+
+#define S_PERR_ENABLE_ARB_TPT_PF_1    9
+#define V_PERR_ENABLE_ARB_TPT_PF_1(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_1)
+#define F_PERR_ENABLE_ARB_TPT_PF_1    V_PERR_ENABLE_ARB_TPT_PF_1(1U)
+
+#define S_PERR_ENABLE_ARB_F_1    8
+#define V_PERR_ENABLE_ARB_F_1(x) ((x) << S_PERR_ENABLE_ARB_F_1)
+#define F_PERR_ENABLE_ARB_F_1    V_PERR_ENABLE_ARB_F_1(1U)
+
+#define S_PERR_ENABLE_ARB_PBL_PF_0    3
+#define V_PERR_ENABLE_ARB_PBL_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_0)
+#define F_PERR_ENABLE_ARB_PBL_PF_0    V_PERR_ENABLE_ARB_PBL_PF_0(1U)
+
+#define S_PERR_ENABLE_ARB_PF_0    2
+#define V_PERR_ENABLE_ARB_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PF_0)
+#define F_PERR_ENABLE_ARB_PF_0    V_PERR_ENABLE_ARB_PF_0(1U)
+
+#define S_PERR_ENABLE_ARB_TPT_PF_0    1
+#define V_PERR_ENABLE_ARB_TPT_PF_0(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_0)
+#define F_PERR_ENABLE_ARB_TPT_PF_0    V_PERR_ENABLE_ARB_TPT_PF_0(1U)
+
+#define S_PERR_ENABLE_ARB_F_0    0
+#define V_PERR_ENABLE_ARB_F_0(x) ((x) << S_PERR_ENABLE_ARB_F_0)
+#define F_PERR_ENABLE_ARB_F_0    V_PERR_ENABLE_ARB_F_0(1U)
+
+#define A_ULP_RX_CTL1 0x19330
+
+#define S_ISCSI_CTL2    27
+#define V_ISCSI_CTL2(x) ((x) << S_ISCSI_CTL2)
+#define F_ISCSI_CTL2    V_ISCSI_CTL2(1U)
+
+#define S_ISCSI_CTL1    26
+#define V_ISCSI_CTL1(x) ((x) << S_ISCSI_CTL1)
+#define F_ISCSI_CTL1    V_ISCSI_CTL1(1U)
+
+#define S_ISCSI_CTL0    25
+#define V_ISCSI_CTL0(x) ((x) << S_ISCSI_CTL0)
+#define F_ISCSI_CTL0    V_ISCSI_CTL0(1U)
+
+#define S_NVME_TCP_DATA_ALIGNMENT    16
+#define M_NVME_TCP_DATA_ALIGNMENT    0x1ffU
+#define V_NVME_TCP_DATA_ALIGNMENT(x) ((x) << S_NVME_TCP_DATA_ALIGNMENT)
+#define G_NVME_TCP_DATA_ALIGNMENT(x) (((x) >> S_NVME_TCP_DATA_ALIGNMENT) & M_NVME_TCP_DATA_ALIGNMENT)
+
+#define S_NVME_TCP_INVLD_MSG_DIS    14
+#define M_NVME_TCP_INVLD_MSG_DIS    0x3U
+#define V_NVME_TCP_INVLD_MSG_DIS(x) ((x) << S_NVME_TCP_INVLD_MSG_DIS)
+#define G_NVME_TCP_INVLD_MSG_DIS(x) (((x) >> S_NVME_TCP_INVLD_MSG_DIS) & M_NVME_TCP_INVLD_MSG_DIS)
+
+#define S_NVME_TCP_DDP_PDU_CHK_TYPE    13
+#define V_NVME_TCP_DDP_PDU_CHK_TYPE(x) ((x) << S_NVME_TCP_DDP_PDU_CHK_TYPE)
+#define F_NVME_TCP_DDP_PDU_CHK_TYPE    V_NVME_TCP_DDP_PDU_CHK_TYPE(1U)
+
+#define S_T10_CONFIG_ENB    12
+#define V_T10_CONFIG_ENB(x) ((x) << S_T10_CONFIG_ENB)
+#define F_T10_CONFIG_ENB    V_T10_CONFIG_ENB(1U)
+
+#define S_NVME_TCP_COLOUR_ENB    10
+#define M_NVME_TCP_COLOUR_ENB    0x3U
+#define V_NVME_TCP_COLOUR_ENB(x) ((x) << S_NVME_TCP_COLOUR_ENB)
+#define G_NVME_TCP_COLOUR_ENB(x) (((x) >> S_NVME_TCP_COLOUR_ENB) & M_NVME_TCP_COLOUR_ENB)
+
+#define S_ROCE_SEND_RQE    8
+#define V_ROCE_SEND_RQE(x) ((x) << S_ROCE_SEND_RQE)
+#define F_ROCE_SEND_RQE    V_ROCE_SEND_RQE(1U)
+
+#define S_RDMA_INVLD_MSG_DIS    6
+#define M_RDMA_INVLD_MSG_DIS    0x3U
+#define V_RDMA_INVLD_MSG_DIS(x) ((x) << S_RDMA_INVLD_MSG_DIS)
+#define G_RDMA_INVLD_MSG_DIS(x) (((x) >> S_RDMA_INVLD_MSG_DIS) & M_RDMA_INVLD_MSG_DIS)
+
+#define S_ROCE_INVLD_MSG_DIS    4
+#define M_ROCE_INVLD_MSG_DIS    0x3U
+#define V_ROCE_INVLD_MSG_DIS(x) ((x) << S_ROCE_INVLD_MSG_DIS)
+#define G_ROCE_INVLD_MSG_DIS(x) (((x) >> S_ROCE_INVLD_MSG_DIS) & M_ROCE_INVLD_MSG_DIS)
+
+#define S_T7_MEM_ADDR_CTRL    2
+#define M_T7_MEM_ADDR_CTRL    0x3U
+#define V_T7_MEM_ADDR_CTRL(x) ((x) << S_T7_MEM_ADDR_CTRL)
+#define G_T7_MEM_ADDR_CTRL(x) (((x) >> S_T7_MEM_ADDR_CTRL) & M_T7_MEM_ADDR_CTRL)
+
+#define S_ENB_32K_PDU    1
+#define V_ENB_32K_PDU(x) ((x) << S_ENB_32K_PDU)
+#define F_ENB_32K_PDU    V_ENB_32K_PDU(1U)
+
+#define S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS    0
+#define V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(x) ((x) << S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS)
+#define F_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS    V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(1U)
+
 #define A_ULP_RX_TLS_IND_CMD 0x19348
 
 #define S_TLS_RX_REG_OFF_ADDR    0
@@ -37795,6 +48839,8 @@
 #define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR)
 
 #define A_ULP_RX_TLS_IND_DATA 0x1934c
+#define A_ULP_RX_TLS_CH0_HMACCTRL_CFG 0x20
+#define A_ULP_RX_TLS_CH1_HMACCTRL_CFG 0x60
 
 /* registers for module SF */
 #define SF_BASE_ADDR 0x193f8
@@ -37815,6 +48861,39 @@
 #define V_BYTECNT(x) ((x) << S_BYTECNT)
 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
 
+#define S_EN32BADDR    30
+#define V_EN32BADDR(x) ((x) << S_EN32BADDR)
+#define F_EN32BADDR    V_EN32BADDR(1U)
+
+#define S_NUM_OF_BYTES    1
+#define M_NUM_OF_BYTES    0x3U
+#define V_NUM_OF_BYTES(x) ((x) << S_NUM_OF_BYTES)
+#define G_NUM_OF_BYTES(x) (((x) >> S_NUM_OF_BYTES) & M_NUM_OF_BYTES)
+
+#define S_QUADREADDISABLE    5
+#define V_QUADREADDISABLE(x) ((x) << S_QUADREADDISABLE)
+#define F_QUADREADDISABLE    V_QUADREADDISABLE(1U)
+
+#define S_EXIT4B    6
+#define V_EXIT4B(x) ((x) << S_EXIT4B)
+#define F_EXIT4B    V_EXIT4B(1U)
+
+#define S_ENTER4B    7
+#define V_ENTER4B(x) ((x) << S_ENTER4B)
+#define F_ENTER4B    V_ENTER4B(1U)
+
+#define S_QUADWRENABLE    8
+#define V_QUADWRENABLE(x) ((x) << S_QUADWRENABLE)
+#define F_QUADWRENABLE    V_QUADWRENABLE(1U)
+
+#define S_REGDBG_SEL    9
+#define V_REGDBG_SEL(x) ((x) << S_REGDBG_SEL)
+#define F_REGDBG_SEL    V_REGDBG_SEL(1U)
+
+#define S_REGDBG_MODE    10
+#define V_REGDBG_MODE(x) ((x) << S_REGDBG_MODE)
+#define F_REGDBG_MODE    V_REGDBG_MODE(1U)
+
 /* registers for module PL */
 #define PL_BASE_ADDR 0x19400
 
@@ -37892,21 +48971,6 @@
 #define F_SWINT    V_SWINT(1U)
 
 #define A_PL_WHOAMI 0x19400
-
-#define S_T6_SOURCEPF    9
-#define M_T6_SOURCEPF    0x7U
-#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
-#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
-
-#define S_T6_ISVF    8
-#define V_T6_ISVF(x) ((x) << S_T6_ISVF)
-#define F_T6_ISVF    V_T6_ISVF(1U)
-
-#define S_T6_VFID    0
-#define M_T6_VFID    0xffU
-#define V_T6_VFID(x) ((x) << S_T6_VFID)
-#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
-
 #define A_PL_PERR_CAUSE 0x19404
 
 #define S_UART    28
@@ -38037,6 +49101,134 @@
 #define V_ANYMAC(x) ((x) << S_ANYMAC)
 #define F_ANYMAC    V_ANYMAC(1U)
 
+#define S_T7_PL_PERR_CRYPTO_KEY    31
+#define V_T7_PL_PERR_CRYPTO_KEY(x) ((x) << S_T7_PL_PERR_CRYPTO_KEY)
+#define F_T7_PL_PERR_CRYPTO_KEY    V_T7_PL_PERR_CRYPTO_KEY(1U)
+
+#define S_T7_PL_PERR_CRYPTO1    30
+#define V_T7_PL_PERR_CRYPTO1(x) ((x) << S_T7_PL_PERR_CRYPTO1)
+#define F_T7_PL_PERR_CRYPTO1    V_T7_PL_PERR_CRYPTO1(1U)
+
+#define S_T7_PL_PERR_CRYPTO0    29
+#define V_T7_PL_PERR_CRYPTO0(x) ((x) << S_T7_PL_PERR_CRYPTO0)
+#define F_T7_PL_PERR_CRYPTO0    V_T7_PL_PERR_CRYPTO0(1U)
+
+#define S_T7_PL_PERR_GCACHE    28
+#define V_T7_PL_PERR_GCACHE(x) ((x) << S_T7_PL_PERR_GCACHE)
+#define F_T7_PL_PERR_GCACHE    V_T7_PL_PERR_GCACHE(1U)
+
+#define S_T7_PL_PERR_ARM    27
+#define V_T7_PL_PERR_ARM(x) ((x) << S_T7_PL_PERR_ARM)
+#define F_T7_PL_PERR_ARM    V_T7_PL_PERR_ARM(1U)
+
+#define S_T7_PL_PERR_ULP_TX    26
+#define V_T7_PL_PERR_ULP_TX(x) ((x) << S_T7_PL_PERR_ULP_TX)
+#define F_T7_PL_PERR_ULP_TX    V_T7_PL_PERR_ULP_TX(1U)
+
+#define S_T7_PL_PERR_SGE    25
+#define V_T7_PL_PERR_SGE(x) ((x) << S_T7_PL_PERR_SGE)
+#define F_T7_PL_PERR_SGE    V_T7_PL_PERR_SGE(1U)
+
+#define S_T7_PL_PERR_HMA    24
+#define V_T7_PL_PERR_HMA(x) ((x) << S_T7_PL_PERR_HMA)
+#define F_T7_PL_PERR_HMA    V_T7_PL_PERR_HMA(1U)
+
+#define S_T7_PL_PERR_CPL_SWITCH    23
+#define V_T7_PL_PERR_CPL_SWITCH(x) ((x) << S_T7_PL_PERR_CPL_SWITCH)
+#define F_T7_PL_PERR_CPL_SWITCH    V_T7_PL_PERR_CPL_SWITCH(1U)
+
+#define S_T7_PL_PERR_ULP_RX    22
+#define V_T7_PL_PERR_ULP_RX(x) ((x) << S_T7_PL_PERR_ULP_RX)
+#define F_T7_PL_PERR_ULP_RX    V_T7_PL_PERR_ULP_RX(1U)
+
+#define S_T7_PL_PERR_PM_RX    21
+#define V_T7_PL_PERR_PM_RX(x) ((x) << S_T7_PL_PERR_PM_RX)
+#define F_T7_PL_PERR_PM_RX    V_T7_PL_PERR_PM_RX(1U)
+
+#define S_T7_PL_PERR_PM_TX    20
+#define V_T7_PL_PERR_PM_TX(x) ((x) << S_T7_PL_PERR_PM_TX)
+#define F_T7_PL_PERR_PM_TX    V_T7_PL_PERR_PM_TX(1U)
+
+#define S_T7_PL_PERR_MA    19
+#define V_T7_PL_PERR_MA(x) ((x) << S_T7_PL_PERR_MA)
+#define F_T7_PL_PERR_MA    V_T7_PL_PERR_MA(1U)
+
+#define S_T7_PL_PERR_TP    18
+#define V_T7_PL_PERR_TP(x) ((x) << S_T7_PL_PERR_TP)
+#define F_T7_PL_PERR_TP    V_T7_PL_PERR_TP(1U)
+
+#define S_T7_PL_PERR_LE    17
+#define V_T7_PL_PERR_LE(x) ((x) << S_T7_PL_PERR_LE)
+#define F_T7_PL_PERR_LE    V_T7_PL_PERR_LE(1U)
+
+#define S_T7_PL_PERR_EDC1    16
+#define V_T7_PL_PERR_EDC1(x) ((x) << S_T7_PL_PERR_EDC1)
+#define F_T7_PL_PERR_EDC1    V_T7_PL_PERR_EDC1(1U)
+
+#define S_T7_PL_PERR_EDC0    15
+#define V_T7_PL_PERR_EDC0(x) ((x) << S_T7_PL_PERR_EDC0)
+#define F_T7_PL_PERR_EDC0    V_T7_PL_PERR_EDC0(1U)
+
+#define S_T7_PL_PERR_MC1    14
+#define V_T7_PL_PERR_MC1(x) ((x) << S_T7_PL_PERR_MC1)
+#define F_T7_PL_PERR_MC1    V_T7_PL_PERR_MC1(1U)
+
+#define S_T7_PL_PERR_MC0    13
+#define V_T7_PL_PERR_MC0(x) ((x) << S_T7_PL_PERR_MC0)
+#define F_T7_PL_PERR_MC0    V_T7_PL_PERR_MC0(1U)
+
+#define S_T7_PL_PERR_PCIE    12
+#define V_T7_PL_PERR_PCIE(x) ((x) << S_T7_PL_PERR_PCIE)
+#define F_T7_PL_PERR_PCIE    V_T7_PL_PERR_PCIE(1U)
+
+#define S_T7_PL_PERR_UART    11
+#define V_T7_PL_PERR_UART(x) ((x) << S_T7_PL_PERR_UART)
+#define F_T7_PL_PERR_UART    V_T7_PL_PERR_UART(1U)
+
+#define S_T7_PL_PERR_PMU    10
+#define V_T7_PL_PERR_PMU(x) ((x) << S_T7_PL_PERR_PMU)
+#define F_T7_PL_PERR_PMU    V_T7_PL_PERR_PMU(1U)
+
+#define S_T7_PL_PERR_MAC    9
+#define V_T7_PL_PERR_MAC(x) ((x) << S_T7_PL_PERR_MAC)
+#define F_T7_PL_PERR_MAC    V_T7_PL_PERR_MAC(1U)
+
+#define S_T7_PL_PERR_SMB    8
+#define V_T7_PL_PERR_SMB(x) ((x) << S_T7_PL_PERR_SMB)
+#define F_T7_PL_PERR_SMB    V_T7_PL_PERR_SMB(1U)
+
+#define S_T7_PL_PERR_SF    7
+#define V_T7_PL_PERR_SF(x) ((x) << S_T7_PL_PERR_SF)
+#define F_T7_PL_PERR_SF    V_T7_PL_PERR_SF(1U)
+
+#define S_T7_PL_PERR_PL    6
+#define V_T7_PL_PERR_PL(x) ((x) << S_T7_PL_PERR_PL)
+#define F_T7_PL_PERR_PL    V_T7_PL_PERR_PL(1U)
+
+#define S_T7_PL_PERR_NCSI    5
+#define V_T7_PL_PERR_NCSI(x) ((x) << S_T7_PL_PERR_NCSI)
+#define F_T7_PL_PERR_NCSI    V_T7_PL_PERR_NCSI(1U)
+
+#define S_T7_PL_PERR_MPS    4
+#define V_T7_PL_PERR_MPS(x) ((x) << S_T7_PL_PERR_MPS)
+#define F_T7_PL_PERR_MPS    V_T7_PL_PERR_MPS(1U)
+
+#define S_T7_PL_PERR_MI    3
+#define V_T7_PL_PERR_MI(x) ((x) << S_T7_PL_PERR_MI)
+#define F_T7_PL_PERR_MI    V_T7_PL_PERR_MI(1U)
+
+#define S_T7_PL_PERR_DBG    2
+#define V_T7_PL_PERR_DBG(x) ((x) << S_T7_PL_PERR_DBG)
+#define F_T7_PL_PERR_DBG    V_T7_PL_PERR_DBG(1U)
+
+#define S_T7_PL_PERR_I2CM    1
+#define V_T7_PL_PERR_I2CM(x) ((x) << S_T7_PL_PERR_I2CM)
+#define F_T7_PL_PERR_I2CM    V_T7_PL_PERR_I2CM(1U)
+
+#define S_T7_PL_PERR_CIM    0
+#define V_T7_PL_PERR_CIM(x) ((x) << S_T7_PL_PERR_CIM)
+#define F_T7_PL_PERR_CIM    V_T7_PL_PERR_CIM(1U)
+
 #define A_PL_PERR_ENABLE 0x19408
 #define A_PL_INT_CAUSE 0x1940c
 
@@ -38064,6 +49256,78 @@
 #define V_MAC0(x) ((x) << S_MAC0)
 #define F_MAC0    V_MAC0(1U)
 
+#define S_T7_FLR    31
+#define V_T7_FLR(x) ((x) << S_T7_FLR)
+#define F_T7_FLR    V_T7_FLR(1U)
+
+#define S_T7_SW_CIM    30
+#define V_T7_SW_CIM(x) ((x) << S_T7_SW_CIM)
+#define F_T7_SW_CIM    V_T7_SW_CIM(1U)
+
+#define S_T7_ULP_TX    29
+#define V_T7_ULP_TX(x) ((x) << S_T7_ULP_TX)
+#define F_T7_ULP_TX    V_T7_ULP_TX(1U)
+
+#define S_T7_SGE    28
+#define V_T7_SGE(x) ((x) << S_T7_SGE)
+#define F_T7_SGE    V_T7_SGE(1U)
+
+#define S_T7_HMA    27
+#define V_T7_HMA(x) ((x) << S_T7_HMA)
+#define F_T7_HMA    V_T7_HMA(1U)
+
+#define S_T7_CPL_SWITCH    26
+#define V_T7_CPL_SWITCH(x) ((x) << S_T7_CPL_SWITCH)
+#define F_T7_CPL_SWITCH    V_T7_CPL_SWITCH(1U)
+
+#define S_T7_ULP_RX    25
+#define V_T7_ULP_RX(x) ((x) << S_T7_ULP_RX)
+#define F_T7_ULP_RX    V_T7_ULP_RX(1U)
+
+#define S_T7_PM_RX    24
+#define V_T7_PM_RX(x) ((x) << S_T7_PM_RX)
+#define F_T7_PM_RX    V_T7_PM_RX(1U)
+
+#define S_T7_PM_TX    23
+#define V_T7_PM_TX(x) ((x) << S_T7_PM_TX)
+#define F_T7_PM_TX    V_T7_PM_TX(1U)
+
+#define S_T7_MA    22
+#define V_T7_MA(x) ((x) << S_T7_MA)
+#define F_T7_MA    V_T7_MA(1U)
+
+#define S_T7_TP    21
+#define V_T7_TP(x) ((x) << S_T7_TP)
+#define F_T7_TP    V_T7_TP(1U)
+
+#define S_T7_LE    20
+#define V_T7_LE(x) ((x) << S_T7_LE)
+#define F_T7_LE    V_T7_LE(1U)
+
+#define S_T7_EDC1    19
+#define V_T7_EDC1(x) ((x) << S_T7_EDC1)
+#define F_T7_EDC1    V_T7_EDC1(1U)
+
+#define S_T7_EDC0    18
+#define V_T7_EDC0(x) ((x) << S_T7_EDC0)
+#define F_T7_EDC0    V_T7_EDC0(1U)
+
+#define S_T7_MC1    17
+#define V_T7_MC1(x) ((x) << S_T7_MC1)
+#define F_T7_MC1    V_T7_MC1(1U)
+
+#define S_T7_MC0    16
+#define V_T7_MC0(x) ((x) << S_T7_MC0)
+#define F_T7_MC0    V_T7_MC0(1U)
+
+#define S_T7_PCIE    15
+#define V_T7_PCIE(x) ((x) << S_T7_PCIE)
+#define F_T7_PCIE    V_T7_PCIE(1U)
+
+#define S_T7_UART    14
+#define V_T7_UART(x) ((x) << S_T7_UART)
+#define F_T7_UART    V_T7_UART(1U)
+
 #define A_PL_INT_ENABLE 0x19410
 #define A_PL_INT_MAP0 0x19414
 
@@ -38262,15 +49526,10 @@
 #define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD)
 #define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD)
 
-#define S_T6_STATECFGINITF    16
-#define M_T6_STATECFGINITF    0xffU
-#define V_T6_STATECFGINITF(x) ((x) << S_T6_STATECFGINITF)
-#define G_T6_STATECFGINITF(x) (((x) >> S_T6_STATECFGINITF) & M_T6_STATECFGINITF)
-
-#define S_T6_STATECFGINIT    12
-#define M_T6_STATECFGINIT    0xfU
-#define V_T6_STATECFGINIT(x) ((x) << S_T6_STATECFGINIT)
-#define G_T6_STATECFGINIT(x) (((x) >> S_T6_STATECFGINIT) & M_T6_STATECFGINIT)
+#define S_T6_1_STATECFGINITF    16
+#define M_T6_1_STATECFGINITF    0xffU
+#define V_T6_1_STATECFGINITF(x) ((x) << S_T6_1_STATECFGINITF)
+#define G_T6_1_STATECFGINITF(x) (((x) >> S_T6_1_STATECFGINITF) & M_T6_1_STATECFGINITF)
 
 #define S_PHY_STATUS    10
 #define V_PHY_STATUS(x) ((x) << S_PHY_STATUS)
@@ -38285,9 +49544,9 @@
 #define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL)
 #define F_PERSTTIMEOUT_PL    V_PERSTTIMEOUT_PL(1U)
 
-#define S_T6_LTSSMENABLE    6
-#define V_T6_LTSSMENABLE(x) ((x) << S_T6_LTSSMENABLE)
-#define F_T6_LTSSMENABLE    V_T6_LTSSMENABLE(1U)
+#define S_SPEEDMS    30
+#define V_SPEEDMS(x) ((x) << S_SPEEDMS)
+#define F_SPEEDMS    V_SPEEDMS(1U)
 
 #define A_PL_PCIE_CTL_STAT 0x19444
 
@@ -38382,6 +49641,37 @@
 #define V_MAP0(x) ((x) << S_MAP0)
 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
 
+#define A_PL_INT_CAUSE2 0x19478
+
+#define S_CRYPTO_KEY    4
+#define V_CRYPTO_KEY(x) ((x) << S_CRYPTO_KEY)
+#define F_CRYPTO_KEY    V_CRYPTO_KEY(1U)
+
+#define S_CRYPTO1    3
+#define V_CRYPTO1(x) ((x) << S_CRYPTO1)
+#define F_CRYPTO1    V_CRYPTO1(1U)
+
+#define S_CRYPTO0    2
+#define V_CRYPTO0(x) ((x) << S_CRYPTO0)
+#define F_CRYPTO0    V_CRYPTO0(1U)
+
+#define S_GCACHE    1
+#define V_GCACHE(x) ((x) << S_GCACHE)
+#define F_GCACHE    V_GCACHE(1U)
+
+#define S_ARM    0
+#define V_ARM(x) ((x) << S_ARM)
+#define F_ARM    V_ARM(1U)
+
+#define A_PL_INT_ENABLE2 0x1947c
+#define A_PL_ER_CMD 0x19488
+
+#define S_ER_ADDR    2
+#define M_ER_ADDR    0x3fffffffU
+#define V_ER_ADDR(x) ((x) << S_ER_ADDR)
+#define G_ER_ADDR(x) (((x) >> S_ER_ADDR) & M_ER_ADDR)
+
+#define A_PL_ER_DATA 0x1948c
 #define A_PL_VF_SLICE_L 0x19490
 
 #define S_LIMITADDR    16
@@ -38638,6 +49928,10 @@
 #define V_REGION_EN(x) ((x) << S_REGION_EN)
 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
 
+#define S_CACHEBYPASS    28
+#define V_CACHEBYPASS(x) ((x) << S_CACHEBYPASS)
+#define F_CACHEBYPASS    V_CACHEBYPASS(1U)
+
 #define A_LE_MISC 0x19c08
 
 #define S_CMPUNVAIL    0
@@ -38830,6 +50124,10 @@
 #define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE)
 #define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE)
 
+#define S_MLL_MASK    2
+#define V_MLL_MASK(x) ((x) << S_MLL_MASK)
+#define F_MLL_MASK    V_MLL_MASK(1U)
+
 #define A_LE_DB_INT_ENABLE 0x19c38
 
 #define S_MSGSEL    27
@@ -39045,40 +50343,15 @@
 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
 #define F_PIPELINEERR    V_PIPELINEERR(1U)
 
-#define A_LE_DB_INT_CAUSE 0x19c3c
-
-#define S_T6_ACTRGNFULL    21
-#define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
-#define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
+#define S_CACHEINTPERR    31
+#define V_CACHEINTPERR(x) ((x) << S_CACHEINTPERR)
+#define F_CACHEINTPERR    V_CACHEINTPERR(1U)
 
-#define S_T6_ACTCNTIPV6TZERO    20
-#define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
-#define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
-
-#define S_T6_ACTCNTIPV4TZERO    19
-#define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
-#define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
-
-#define S_T6_ACTCNTIPV6ZERO    18
-#define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
-#define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
-
-#define S_T6_ACTCNTIPV4ZERO    17
-#define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
-#define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
-
-#define S_T6_UNKNOWNCMD    3
-#define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
-#define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
-
-#define S_T6_LIP0    2
-#define V_T6_LIP0(x) ((x) << S_T6_LIP0)
-#define F_T6_LIP0    V_T6_LIP0(1U)
-
-#define S_T6_LIPMISS    1
-#define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
-#define F_T6_LIPMISS    V_T6_LIPMISS(1U)
+#define S_CACHESRAMPERR    30
+#define V_CACHESRAMPERR(x) ((x) << S_CACHESRAMPERR)
+#define F_CACHESRAMPERR    V_CACHESRAMPERR(1U)
 
+#define A_LE_DB_INT_CAUSE 0x19c3c
 #define A_LE_DB_INT_TID 0x19c40
 
 #define S_INTTID    0
@@ -39287,6 +50560,14 @@
 
 #define A_LE_DB_MASK_IPV6 0x19ca0
 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0
+#define A_LE_CMM_CONFIG 0x19cc0
+#define A_LE_CACHE_DBG 0x19cc4
+#define A_LE_CACHE_WR_ALL_CNT 0x19cc8
+#define A_LE_CACHE_WR_HIT_CNT 0x19ccc
+#define A_LE_CACHE_RD_ALL_CNT 0x19cd0
+#define A_LE_CACHE_RD_HIT_CNT 0x19cd4
+#define A_LE_CACHE_MC_WR_CNT 0x19cd8
+#define A_LE_CACHE_MC_RD_CNT 0x19cdc
 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
 
 #define S_T4_RSPCNT    16
@@ -39309,6 +50590,14 @@
 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
 
+#define A_LE_IND_ADDR 0x19ce8
+
+#define S_T7_1_ADDR    0
+#define M_T7_1_ADDR    0xffU
+#define V_T7_1_ADDR(x) ((x) << S_T7_1_ADDR)
+#define G_T7_1_ADDR(x) (((x) >> S_T7_1_ADDR) & M_T7_1_ADDR)
+
+#define A_LE_IND_DATA 0x19cec
 #define A_LE_DB_DBGI_CONFIG 0x19cf0
 
 #define S_DBGICMDPERR    31
@@ -39436,6 +50725,11 @@
 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
 #define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)
 
+#define S_T7_BKCHKPERIOD    22
+#define M_T7_BKCHKPERIOD    0xffU
+#define V_T7_BKCHKPERIOD(x) ((x) << S_T7_BKCHKPERIOD)
+#define G_T7_BKCHKPERIOD(x) (((x) >> S_T7_BKCHKPERIOD) & M_T7_BKCHKPERIOD)
+
 #define A_LE_SPARE 0x19cfc
 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
@@ -39551,6 +50845,7 @@
 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
 
+#define A_T7_LE_DB_HASH_TID_BASE 0x19df8
 #define A_LE_PERR_INJECT 0x19dfc
 
 #define S_LEMEMSEL    1
@@ -39573,6 +50868,7 @@
 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
+#define A_T7_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
@@ -39677,6 +50973,9 @@
 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
+#define A_LE_TCAM_BIST_CTRL 0x19fb0
+#define A_LE_TCAM_BIST_CB_PASS 0x19fb4
+#define A_LE_TCAM_BIST_CB_BUSY 0x19fbc
 #define A_LE_HASH_COLLISION 0x19fc4
 #define A_LE_GLOBAL_COLLISION 0x19fc8
 #define A_LE_FULL_CNT_COLLISION 0x19fcc
@@ -39686,6 +50985,38 @@
 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
+#define A_LE_TCAM_NEG_CTRL0 0x0
+#define A_LE_TCAM_NEG_CTRL1 0x1
+#define A_LE_TCAM_NEG_CTRL2 0x2
+#define A_LE_TCAM_NEG_CTRL3 0x3
+#define A_LE_TCAM_NEG_CTRL4 0x4
+#define A_LE_TCAM_NEG_CTRL5 0x5
+#define A_LE_TCAM_NEG_CTRL6 0x6
+#define A_LE_TCAM_NEG_CTRL7 0x7
+#define A_LE_TCAM_NEG_CTRL8 0x8
+#define A_LE_TCAM_NEG_CTRL9 0x9
+#define A_LE_TCAM_NEG_CTRL10 0xa
+#define A_LE_TCAM_NEG_CTRL11 0xb
+#define A_LE_TCAM_NEG_CTRL12 0xc
+#define A_LE_TCAM_NEG_CTRL13 0xd
+#define A_LE_TCAM_NEG_CTRL14 0xe
+#define A_LE_TCAM_NEG_CTRL15 0xf
+#define A_LE_TCAM_NEG_CTRL16 0x10
+#define A_LE_TCAM_NEG_CTRL17 0x11
+#define A_LE_TCAM_NEG_CTRL18 0x12
+#define A_LE_TCAM_NEG_CTRL19 0x13
+#define A_LE_TCAM_NEG_CTRL20 0x14
+#define A_LE_TCAM_NEG_CTRL21 0x15
+#define A_LE_TCAM_NEG_CTRL22 0x16
+#define A_LE_TCAM_NEG_CTRL23 0x17
+#define A_LE_TCAM_NEG_CTRL24 0x18
+#define A_LE_TCAM_NEG_CTRL25 0x19
+#define A_LE_TCAM_NEG_CTRL26 0x1a
+#define A_LE_TCAM_NEG_CTRL27 0x1b
+#define A_LE_TCAM_NEG_CTRL28 0x1c
+#define A_LE_TCAM_NEG_CTRL29 0x1d
+#define A_LE_TCAM_NEG_CTRL30 0x1e
+#define A_LE_TCAM_NEG_CTRL31 0x1f
 
 /* registers for module NCSI */
 #define NCSI_BASE_ADDR 0x1a000
@@ -39735,6 +51066,10 @@
 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
 #define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)
 
+#define S_XGMAC0_EN    0
+#define V_XGMAC0_EN(x) ((x) << S_XGMAC0_EN)
+#define F_XGMAC0_EN    V_XGMAC0_EN(1U)
+
 #define A_NCSI_RST_CTRL 0x1a004
 
 #define S_MAC_REF_RST    2
@@ -39991,6 +51326,10 @@
 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
 #define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)
 
+#define S_CIM2NC_PERR    9
+#define V_CIM2NC_PERR(x) ((x) << S_CIM2NC_PERR)
+#define F_CIM2NC_PERR    V_CIM2NC_PERR(1U)
+
 #define A_NCSI_INT_CAUSE 0x1a0d8
 #define A_NCSI_STATUS 0x1a0dc
 
@@ -40048,6 +51387,12 @@
 #define F_MCSIMELSEL    V_MCSIMELSEL(1U)
 
 #define A_NCSI_PERR_ENABLE 0x1a0f8
+#define A_NCSI_MODE_SEL 0x1a0fc
+
+#define S_XGMAC_MODE    0
+#define V_XGMAC_MODE(x) ((x) << S_XGMAC_MODE)
+#define F_XGMAC_MODE    V_XGMAC_MODE(1U)
+
 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
 
 #define S_TXSNDZEROPAUSE    12
@@ -40550,6 +51895,832 @@
 #define V_DESREV(x) ((x) << S_DESREV)
 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
 
+#define A_NCSI_TX_CTRL 0x1a200
+
+#define S_T7_TXEN    0
+#define V_T7_TXEN(x) ((x) << S_T7_TXEN)
+#define F_T7_TXEN    V_T7_TXEN(1U)
+
+#define A_NCSI_TX_CFG 0x1a204
+#define A_NCSI_TX_PAUSE_QUANTA 0x1a208
+#define A_NCSI_RX_CTRL 0x1a20c
+#define A_NCSI_RX_CFG 0x1a210
+#define A_NCSI_RX_HASH_LOW 0x1a214
+#define A_NCSI_RX_HASH_HIGH 0x1a218
+#define A_NCSI_RX_EXACT_MATCH_LOW_1 0x1a21c
+#define A_NCSI_RX_EXACT_MATCH_HIGH_1 0x1a220
+#define A_NCSI_RX_EXACT_MATCH_LOW_2 0x1a224
+#define A_NCSI_RX_EXACT_MATCH_HIGH_2 0x1a228
+#define A_NCSI_RX_EXACT_MATCH_LOW_3 0x1a22c
+#define A_NCSI_RX_EXACT_MATCH_HIGH_3 0x1a230
+#define A_NCSI_RX_EXACT_MATCH_LOW_4 0x1a234
+#define A_NCSI_RX_EXACT_MATCH_HIGH_4 0x1a238
+#define A_NCSI_RX_EXACT_MATCH_LOW_5 0x1a23c
+#define A_NCSI_RX_EXACT_MATCH_HIGH_5 0x1a240
+#define A_NCSI_RX_EXACT_MATCH_LOW_6 0x1a244
+#define A_NCSI_RX_EXACT_MATCH_HIGH_6 0x1a248
+#define A_NCSI_RX_EXACT_MATCH_LOW_7 0x1a24c
+#define A_NCSI_RX_EXACT_MATCH_HIGH_7 0x1a250
+#define A_NCSI_RX_EXACT_MATCH_LOW_8 0x1a254
+#define A_NCSI_RX_EXACT_MATCH_HIGH_8 0x1a258
+#define A_NCSI_RX_TYPE_MATCH_1 0x1a25c
+#define A_NCSI_RX_TYPE_MATCH_2 0x1a260
+#define A_NCSI_RX_TYPE_MATCH_3 0x1a264
+#define A_NCSI_RX_TYPE_MATCH_4 0x1a268
+#define A_NCSI_INT_STATUS 0x1a26c
+#define A_NCSI_XGM_INT_MASK 0x1a270
+#define A_NCSI_XGM_INT_ENABLE 0x1a274
+#define A_NCSI_XGM_INT_DISABLE 0x1a278
+#define A_NCSI_TX_PAUSE_TIMER 0x1a27c
+#define A_NCSI_STAT_CTRL 0x1a280
+#define A_NCSI_RXFIFO_CFG 0x1a284
+
+#define S_RXFIFO_EMPTY    31
+#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
+#define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
+
+#define S_RXFIFO_FULL    30
+#define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL)
+#define F_RXFIFO_FULL    V_RXFIFO_FULL(1U)
+
+#define S_RXFIFOPAUSEHWM    17
+#define M_RXFIFOPAUSEHWM    0xfffU
+#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
+#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
+
+#define S_RXFIFOPAUSELWM    5
+#define M_RXFIFOPAUSELWM    0xfffU
+#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
+#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
+
+#define S_FORCEDPAUSE    4
+#define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
+#define F_FORCEDPAUSE    V_FORCEDPAUSE(1U)
+
+#define S_EXTERNLOOPBACK    3
+#define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
+#define F_EXTERNLOOPBACK    V_EXTERNLOOPBACK(1U)
+
+#define S_RXBYTESWAP    2
+#define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
+#define F_RXBYTESWAP    V_RXBYTESWAP(1U)
+
+#define S_RXSTRFRWRD    1
+#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
+#define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
+
+#define S_DISERRFRAMES    0
+#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
+#define F_DISERRFRAMES    V_DISERRFRAMES(1U)
+
+#define A_NCSI_TXFIFO_CFG 0x1a288
+
+#define S_T7_TXFIFO_EMPTY    31
+#define V_T7_TXFIFO_EMPTY(x) ((x) << S_T7_TXFIFO_EMPTY)
+#define F_T7_TXFIFO_EMPTY    V_T7_TXFIFO_EMPTY(1U)
+
+#define S_T7_TXFIFO_FULL    30
+#define V_T7_TXFIFO_FULL(x) ((x) << S_T7_TXFIFO_FULL)
+#define F_T7_TXFIFO_FULL    V_T7_TXFIFO_FULL(1U)
+
+#define S_UNDERUNFIX    22
+#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
+#define F_UNDERUNFIX    V_UNDERUNFIX(1U)
+
+#define S_ENDROPPKT    21
+#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
+#define F_ENDROPPKT    V_ENDROPPKT(1U)
+
+#define S_TXIPG    13
+#define M_TXIPG    0xffU
+#define V_TXIPG(x) ((x) << S_TXIPG)
+#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
+
+#define S_TXFIFOTHRESH    4
+#define M_TXFIFOTHRESH    0x1ffU
+#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
+#define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
+
+#define S_INTERNLOOPBACK    3
+#define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
+#define F_INTERNLOOPBACK    V_INTERNLOOPBACK(1U)
+
+#define S_TXBYTESWAP    2
+#define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
+#define F_TXBYTESWAP    V_TXBYTESWAP(1U)
+
+#define S_DISCRC    1
+#define V_DISCRC(x) ((x) << S_DISCRC)
+#define F_DISCRC    V_DISCRC(1U)
+
+#define S_DISPREAMBLE    0
+#define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
+#define F_DISPREAMBLE    V_DISPREAMBLE(1U)
+
+#define A_NCSI_SLOW_TIMER 0x1a28c
+
+#define S_PAUSESLOWTIMEREN    31
+#define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
+#define F_PAUSESLOWTIMEREN    V_PAUSESLOWTIMEREN(1U)
+
+#define S_PAUSESLOWTIMER    0
+#define M_PAUSESLOWTIMER    0xfffffU
+#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
+#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
+
+#define A_NCSI_PAUSE_TIMER 0x1a290
+
+#define S_PAUSETIMER    0
+#define M_PAUSETIMER    0xfffffU
+#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
+#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
+
+#define A_NCSI_XAUI_PCS_TEST 0x1a294
+
+#define S_TESTPATTERN    1
+#define M_TESTPATTERN    0x3U
+#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
+#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
+
+#define S_ENTEST    0
+#define V_ENTEST(x) ((x) << S_ENTEST)
+#define F_ENTEST    V_ENTEST(1U)
+
+#define A_NCSI_RGMII_CTRL 0x1a298
+
+#define S_PHALIGNFIFOTHRESH    1
+#define M_PHALIGNFIFOTHRESH    0x3U
+#define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
+#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
+
+#define S_TXCLK90SHIFT    0
+#define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
+#define F_TXCLK90SHIFT    V_TXCLK90SHIFT(1U)
+
+#define A_NCSI_RGMII_IMP 0x1a29c
+
+#define S_CALRESET    8
+#define V_CALRESET(x) ((x) << S_CALRESET)
+#define F_CALRESET    V_CALRESET(1U)
+
+#define S_CALUPDATE    7
+#define V_CALUPDATE(x) ((x) << S_CALUPDATE)
+#define F_CALUPDATE    V_CALUPDATE(1U)
+
+#define S_IMPSETUPDATE    6
+#define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
+#define F_IMPSETUPDATE    V_IMPSETUPDATE(1U)
+
+#define S_RGMIIIMPPD    3
+#define M_RGMIIIMPPD    0x7U
+#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
+#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
+
+#define S_RGMIIIMPPU    0
+#define M_RGMIIIMPPU    0x7U
+#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
+#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
+
+#define A_NCSI_RX_MAX_PKT_SIZE 0x1a2a8
+
+#define S_RXMAXFRAMERSIZE    17
+#define M_RXMAXFRAMERSIZE    0x3fffU
+#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
+#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
+
+#define S_RXENERRORGATHER    16
+#define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER)
+#define F_RXENERRORGATHER    V_RXENERRORGATHER(1U)
+
+#define S_RXENSINGLEFLIT    15
+#define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT)
+#define F_RXENSINGLEFLIT    V_RXENSINGLEFLIT(1U)
+
+#define S_RXENFRAMER    14
+#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
+#define F_RXENFRAMER    V_RXENFRAMER(1U)
+
+#define S_RXMAXPKTSIZE    0
+#define M_RXMAXPKTSIZE    0x3fffU
+#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
+#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
+
+#define A_NCSI_RESET_CTRL 0x1a2ac
+
+#define S_XGMAC_STOP_EN    4
+#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
+#define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
+
+#define S_XG2G_RESET_    3
+#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
+#define F_XG2G_RESET_    V_XG2G_RESET_(1U)
+
+#define S_RGMII_RESET_    2
+#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
+#define F_RGMII_RESET_    V_RGMII_RESET_(1U)
+
+#define S_PCS_RESET_    1
+#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
+#define F_PCS_RESET_    V_PCS_RESET_(1U)
+
+#define S_MAC_RESET_    0
+#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
+#define F_MAC_RESET_    V_MAC_RESET_(1U)
+
+#define A_NCSI_XAUI1G_CTRL 0x1a2b0
+
+#define S_XAUI1GLINKID    0
+#define M_XAUI1GLINKID    0x3U
+#define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
+#define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
+
+#define A_NCSI_SERDES_LANE_CTRL 0x1a2b4
+
+#define S_LANEREVERSAL    8
+#define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
+#define F_LANEREVERSAL    V_LANEREVERSAL(1U)
+
+#define S_TXPOLARITY    4
+#define M_TXPOLARITY    0xfU
+#define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
+#define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
+
+#define S_RXPOLARITY    0
+#define M_RXPOLARITY    0xfU
+#define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
+#define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
+
+#define A_NCSI_PORT_CFG 0x1a2b8
+
+#define S_NCSI_SAFESPEEDCHANGE    4
+#define V_NCSI_SAFESPEEDCHANGE(x) ((x) << S_NCSI_SAFESPEEDCHANGE)
+#define F_NCSI_SAFESPEEDCHANGE    V_NCSI_SAFESPEEDCHANGE(1U)
+
+#define S_NCSI_CLKDIVRESET_    3
+#define V_NCSI_CLKDIVRESET_(x) ((x) << S_NCSI_CLKDIVRESET_)
+#define F_NCSI_CLKDIVRESET_    V_NCSI_CLKDIVRESET_(1U)
+
+#define S_NCSI_PORTSPEED    1
+#define M_NCSI_PORTSPEED    0x3U
+#define V_NCSI_PORTSPEED(x) ((x) << S_NCSI_PORTSPEED)
+#define G_NCSI_PORTSPEED(x) (((x) >> S_NCSI_PORTSPEED) & M_NCSI_PORTSPEED)
+
+#define S_NCSI_ENRGMII    0
+#define V_NCSI_ENRGMII(x) ((x) << S_NCSI_ENRGMII)
+#define F_NCSI_ENRGMII    V_NCSI_ENRGMII(1U)
+
+#define A_NCSI_EPIO_DATA0 0x1a2c0
+#define A_NCSI_EPIO_DATA1 0x1a2c4
+#define A_NCSI_EPIO_DATA2 0x1a2c8
+#define A_NCSI_EPIO_DATA3 0x1a2cc
+#define A_NCSI_EPIO_OP 0x1a2d0
+
+#define S_PIO_READY    31
+#define V_PIO_READY(x) ((x) << S_PIO_READY)
+#define F_PIO_READY    V_PIO_READY(1U)
+
+#define S_PIO_WRRD    24
+#define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
+#define F_PIO_WRRD    V_PIO_WRRD(1U)
+
+#define S_PIO_ADDRESS    0
+#define M_PIO_ADDRESS    0xffU
+#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
+#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
+
+#define A_NCSI_XGMAC0_INT_ENABLE 0x1a2d4
+
+#define S_XAUIPCSDECERR    24
+#define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR)
+#define F_XAUIPCSDECERR    V_XAUIPCSDECERR(1U)
+
+#define S_RGMIIRXFIFOOVERFLOW    23
+#define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
+#define F_RGMIIRXFIFOOVERFLOW    V_RGMIIRXFIFOOVERFLOW(1U)
+
+#define S_RGMIIRXFIFOUNDERFLOW    22
+#define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
+#define F_RGMIIRXFIFOUNDERFLOW    V_RGMIIRXFIFOUNDERFLOW(1U)
+
+#define S_RXPKTSIZEERROR    21
+#define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
+#define F_RXPKTSIZEERROR    V_RXPKTSIZEERROR(1U)
+
+#define S_WOLPATDETECTED    20
+#define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
+#define F_WOLPATDETECTED    V_WOLPATDETECTED(1U)
+
+#define S_T7_TXFIFO_PRTY_ERR    17
+#define M_T7_TXFIFO_PRTY_ERR    0x7U
+#define V_T7_TXFIFO_PRTY_ERR(x) ((x) << S_T7_TXFIFO_PRTY_ERR)
+#define G_T7_TXFIFO_PRTY_ERR(x) (((x) >> S_T7_TXFIFO_PRTY_ERR) & M_T7_TXFIFO_PRTY_ERR)
+
+#define S_T7_RXFIFO_PRTY_ERR    14
+#define M_T7_RXFIFO_PRTY_ERR    0x7U
+#define V_T7_RXFIFO_PRTY_ERR(x) ((x) << S_T7_RXFIFO_PRTY_ERR)
+#define G_T7_RXFIFO_PRTY_ERR(x) (((x) >> S_T7_RXFIFO_PRTY_ERR) & M_T7_RXFIFO_PRTY_ERR)
+
+#define S_TXFIFO_UNDERRUN    13
+#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
+#define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
+
+#define S_RXFIFO_OVERFLOW    12
+#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
+#define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
+
+#define S_SERDESBISTERR    8
+#define M_SERDESBISTERR    0xfU
+#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
+#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
+
+#define S_SERDESLOWSIGCHANGE    4
+#define M_SERDESLOWSIGCHANGE    0xfU
+#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
+#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
+
+#define S_XAUIPCSCTCERR    3
+#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
+#define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
+
+#define S_XAUIPCSALIGNCHANGE    2
+#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
+#define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
+
+#define S_RGMIILINKSTSCHANGE    1
+#define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
+#define F_RGMIILINKSTSCHANGE    V_RGMIILINKSTSCHANGE(1U)
+
+#define S_T7_XGM_INT    0
+#define V_T7_XGM_INT(x) ((x) << S_T7_XGM_INT)
+#define F_T7_XGM_INT    V_T7_XGM_INT(1U)
+
+#define A_NCSI_XGMAC0_INT_CAUSE 0x1a2d8
+#define A_NCSI_XAUI_ACT_CTRL 0x1a2dc
+#define A_NCSI_SERDES_CTRL0 0x1a2e0
+
+#define S_INTSERLPBK3    27
+#define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
+#define F_INTSERLPBK3    V_INTSERLPBK3(1U)
+
+#define S_INTSERLPBK2    26
+#define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
+#define F_INTSERLPBK2    V_INTSERLPBK2(1U)
+
+#define S_INTSERLPBK1    25
+#define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
+#define F_INTSERLPBK1    V_INTSERLPBK1(1U)
+
+#define S_INTSERLPBK0    24
+#define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
+#define F_INTSERLPBK0    V_INTSERLPBK0(1U)
+
+#define S_RESET3    23
+#define V_RESET3(x) ((x) << S_RESET3)
+#define F_RESET3    V_RESET3(1U)
+
+#define S_RESET2    22
+#define V_RESET2(x) ((x) << S_RESET2)
+#define F_RESET2    V_RESET2(1U)
+
+#define S_RESET1    21
+#define V_RESET1(x) ((x) << S_RESET1)
+#define F_RESET1    V_RESET1(1U)
+
+#define S_RESET0    20
+#define V_RESET0(x) ((x) << S_RESET0)
+#define F_RESET0    V_RESET0(1U)
+
+#define S_PWRDN3    19
+#define V_PWRDN3(x) ((x) << S_PWRDN3)
+#define F_PWRDN3    V_PWRDN3(1U)
+
+#define S_PWRDN2    18
+#define V_PWRDN2(x) ((x) << S_PWRDN2)
+#define F_PWRDN2    V_PWRDN2(1U)
+
+#define S_PWRDN1    17
+#define V_PWRDN1(x) ((x) << S_PWRDN1)
+#define F_PWRDN1    V_PWRDN1(1U)
+
+#define S_PWRDN0    16
+#define V_PWRDN0(x) ((x) << S_PWRDN0)
+#define F_PWRDN0    V_PWRDN0(1U)
+
+#define S_RESETPLL23    15
+#define V_RESETPLL23(x) ((x) << S_RESETPLL23)
+#define F_RESETPLL23    V_RESETPLL23(1U)
+
+#define S_RESETPLL01    14
+#define V_RESETPLL01(x) ((x) << S_RESETPLL01)
+#define F_RESETPLL01    V_RESETPLL01(1U)
+
+#define S_PW23    12
+#define M_PW23    0x3U
+#define V_PW23(x) ((x) << S_PW23)
+#define G_PW23(x) (((x) >> S_PW23) & M_PW23)
+
+#define S_PW01    10
+#define M_PW01    0x3U
+#define V_PW01(x) ((x) << S_PW01)
+#define G_PW01(x) (((x) >> S_PW01) & M_PW01)
+
+#define S_DEQ    6
+#define M_DEQ    0xfU
+#define V_DEQ(x) ((x) << S_DEQ)
+#define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
+
+#define S_DTX    2
+#define M_DTX    0xfU
+#define V_DTX(x) ((x) << S_DTX)
+#define G_DTX(x) (((x) >> S_DTX) & M_DTX)
+
+#define S_LODRV    1
+#define V_LODRV(x) ((x) << S_LODRV)
+#define F_LODRV    V_LODRV(1U)
+
+#define S_HIDRV    0
+#define V_HIDRV(x) ((x) << S_HIDRV)
+#define F_HIDRV    V_HIDRV(1U)
+
+#define A_NCSI_SERDES_CTRL1 0x1a2e4
+
+#define S_FMOFFSET3    19
+#define M_FMOFFSET3    0x1fU
+#define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
+#define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
+
+#define S_FMOFFSETEN3    18
+#define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
+#define F_FMOFFSETEN3    V_FMOFFSETEN3(1U)
+
+#define S_FMOFFSET2    13
+#define M_FMOFFSET2    0x1fU
+#define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
+#define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
+
+#define S_FMOFFSETEN2    12
+#define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
+#define F_FMOFFSETEN2    V_FMOFFSETEN2(1U)
+
+#define S_FMOFFSET1    7
+#define M_FMOFFSET1    0x1fU
+#define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
+#define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
+
+#define S_FMOFFSETEN1    6
+#define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
+#define F_FMOFFSETEN1    V_FMOFFSETEN1(1U)
+
+#define S_FMOFFSET0    1
+#define M_FMOFFSET0    0x1fU
+#define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
+#define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
+
+#define S_FMOFFSETEN0    0
+#define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
+#define F_FMOFFSETEN0    V_FMOFFSETEN0(1U)
+
+#define A_NCSI_SERDES_CTRL2 0x1a2e8
+
+#define S_DNIN3    11
+#define V_DNIN3(x) ((x) << S_DNIN3)
+#define F_DNIN3    V_DNIN3(1U)
+
+#define S_UPIN3    10
+#define V_UPIN3(x) ((x) << S_UPIN3)
+#define F_UPIN3    V_UPIN3(1U)
+
+#define S_RXSLAVE3    9
+#define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
+#define F_RXSLAVE3    V_RXSLAVE3(1U)
+
+#define S_DNIN2    8
+#define V_DNIN2(x) ((x) << S_DNIN2)
+#define F_DNIN2    V_DNIN2(1U)
+
+#define S_UPIN2    7
+#define V_UPIN2(x) ((x) << S_UPIN2)
+#define F_UPIN2    V_UPIN2(1U)
+
+#define S_RXSLAVE2    6
+#define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
+#define F_RXSLAVE2    V_RXSLAVE2(1U)
+
+#define S_DNIN1    5
+#define V_DNIN1(x) ((x) << S_DNIN1)
+#define F_DNIN1    V_DNIN1(1U)
+
+#define S_UPIN1    4
+#define V_UPIN1(x) ((x) << S_UPIN1)
+#define F_UPIN1    V_UPIN1(1U)
+
+#define S_RXSLAVE1    3
+#define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
+#define F_RXSLAVE1    V_RXSLAVE1(1U)
+
+#define S_DNIN0    2
+#define V_DNIN0(x) ((x) << S_DNIN0)
+#define F_DNIN0    V_DNIN0(1U)
+
+#define S_UPIN0    1
+#define V_UPIN0(x) ((x) << S_UPIN0)
+#define F_UPIN0    V_UPIN0(1U)
+
+#define S_RXSLAVE0    0
+#define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
+#define F_RXSLAVE0    V_RXSLAVE0(1U)
+
+#define A_NCSI_SERDES_CTRL3 0x1a2ec
+
+#define S_EXTBISTCHKERRCLR3    31
+#define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
+#define F_EXTBISTCHKERRCLR3    V_EXTBISTCHKERRCLR3(1U)
+
+#define S_EXTBISTCHKEN3    30
+#define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
+#define F_EXTBISTCHKEN3    V_EXTBISTCHKEN3(1U)
+
+#define S_EXTBISTGENEN3    29
+#define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
+#define F_EXTBISTGENEN3    V_EXTBISTGENEN3(1U)
+
+#define S_EXTBISTPAT3    26
+#define M_EXTBISTPAT3    0x7U
+#define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
+#define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
+
+#define S_EXTPARRESET3    25
+#define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
+#define F_EXTPARRESET3    V_EXTPARRESET3(1U)
+
+#define S_EXTPARLPBK3    24
+#define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
+#define F_EXTPARLPBK3    V_EXTPARLPBK3(1U)
+
+#define S_EXTBISTCHKERRCLR2    23
+#define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
+#define F_EXTBISTCHKERRCLR2    V_EXTBISTCHKERRCLR2(1U)
+
+#define S_EXTBISTCHKEN2    22
+#define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
+#define F_EXTBISTCHKEN2    V_EXTBISTCHKEN2(1U)
+
+#define S_EXTBISTGENEN2    21
+#define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
+#define F_EXTBISTGENEN2    V_EXTBISTGENEN2(1U)
+
+#define S_EXTBISTPAT2    18
+#define M_EXTBISTPAT2    0x7U
+#define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
+#define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
+
+#define S_EXTPARRESET2    17
+#define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
+#define F_EXTPARRESET2    V_EXTPARRESET2(1U)
+
+#define S_EXTPARLPBK2    16
+#define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
+#define F_EXTPARLPBK2    V_EXTPARLPBK2(1U)
+
+#define S_EXTBISTCHKERRCLR1    15
+#define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
+#define F_EXTBISTCHKERRCLR1    V_EXTBISTCHKERRCLR1(1U)
+
+#define S_EXTBISTCHKEN1    14
+#define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
+#define F_EXTBISTCHKEN1    V_EXTBISTCHKEN1(1U)
+
+#define S_EXTBISTGENEN1    13
+#define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
+#define F_EXTBISTGENEN1    V_EXTBISTGENEN1(1U)
+
+#define S_EXTBISTPAT1    10
+#define M_EXTBISTPAT1    0x7U
+#define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
+#define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
+
+#define S_EXTPARRESET1    9
+#define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
+#define F_EXTPARRESET1    V_EXTPARRESET1(1U)
+
+#define S_EXTPARLPBK1    8
+#define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
+#define F_EXTPARLPBK1    V_EXTPARLPBK1(1U)
+
+#define S_EXTBISTCHKERRCLR0    7
+#define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
+#define F_EXTBISTCHKERRCLR0    V_EXTBISTCHKERRCLR0(1U)
+
+#define S_EXTBISTCHKEN0    6
+#define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
+#define F_EXTBISTCHKEN0    V_EXTBISTCHKEN0(1U)
+
+#define S_EXTBISTGENEN0    5
+#define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
+#define F_EXTBISTGENEN0    V_EXTBISTGENEN0(1U)
+
+#define S_EXTBISTPAT0    2
+#define M_EXTBISTPAT0    0x7U
+#define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
+#define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
+
+#define S_EXTPARRESET0    1
+#define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
+#define F_EXTPARRESET0    V_EXTPARRESET0(1U)
+
+#define S_EXTPARLPBK0    0
+#define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
+#define F_EXTPARLPBK0    V_EXTPARLPBK0(1U)
+
+#define A_NCSI_SERDES_STAT0 0x1a2f0
+
+#define S_EXTBISTCHKERRCNT0    4
+#define M_EXTBISTCHKERRCNT0    0xffffffU
+#define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
+#define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
+
+#define S_EXTBISTCHKFMD0    3
+#define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
+#define F_EXTBISTCHKFMD0    V_EXTBISTCHKFMD0(1U)
+
+#define S_LOWSIGFORCEEN0    2
+#define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0)
+#define F_LOWSIGFORCEEN0    V_LOWSIGFORCEEN0(1U)
+
+#define S_LOWSIGFORCEVALUE0    1
+#define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0)
+#define F_LOWSIGFORCEVALUE0    V_LOWSIGFORCEVALUE0(1U)
+
+#define S_LOWSIG0    0
+#define V_LOWSIG0(x) ((x) << S_LOWSIG0)
+#define F_LOWSIG0    V_LOWSIG0(1U)
+
+#define A_NCSI_SERDES_STAT1 0x1a2f4
+
+#define S_EXTBISTCHKERRCNT1    4
+#define M_EXTBISTCHKERRCNT1    0xffffffU
+#define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
+#define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
+
+#define S_EXTBISTCHKFMD1    3
+#define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
+#define F_EXTBISTCHKFMD1    V_EXTBISTCHKFMD1(1U)
+
+#define S_LOWSIGFORCEEN1    2
+#define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1)
+#define F_LOWSIGFORCEEN1    V_LOWSIGFORCEEN1(1U)
+
+#define S_LOWSIGFORCEVALUE1    1
+#define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1)
+#define F_LOWSIGFORCEVALUE1    V_LOWSIGFORCEVALUE1(1U)
+
+#define S_LOWSIG1    0
+#define V_LOWSIG1(x) ((x) << S_LOWSIG1)
+#define F_LOWSIG1    V_LOWSIG1(1U)
+
+#define A_NCSI_SERDES_STAT2 0x1a2f8
+
+#define S_EXTBISTCHKERRCNT2    4
+#define M_EXTBISTCHKERRCNT2    0xffffffU
+#define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
+#define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
+
+#define S_EXTBISTCHKFMD2    3
+#define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
+#define F_EXTBISTCHKFMD2    V_EXTBISTCHKFMD2(1U)
+
+#define S_LOWSIGFORCEEN2    2
+#define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2)
+#define F_LOWSIGFORCEEN2    V_LOWSIGFORCEEN2(1U)
+
+#define S_LOWSIGFORCEVALUE2    1
+#define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2)
+#define F_LOWSIGFORCEVALUE2    V_LOWSIGFORCEVALUE2(1U)
+
+#define S_LOWSIG2    0
+#define V_LOWSIG2(x) ((x) << S_LOWSIG2)
+#define F_LOWSIG2    V_LOWSIG2(1U)
+
+#define A_NCSI_SERDES_STAT3 0x1a2fc
+
+#define S_EXTBISTCHKERRCNT3    4
+#define M_EXTBISTCHKERRCNT3    0xffffffU
+#define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
+#define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
+
+#define S_EXTBISTCHKFMD3    3
+#define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
+#define F_EXTBISTCHKFMD3    V_EXTBISTCHKFMD3(1U)
+
+#define S_LOWSIGFORCEEN3    2
+#define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3)
+#define F_LOWSIGFORCEEN3    V_LOWSIGFORCEEN3(1U)
+
+#define S_LOWSIGFORCEVALUE3    1
+#define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3)
+#define F_LOWSIGFORCEVALUE3    V_LOWSIGFORCEVALUE3(1U)
+
+#define S_LOWSIG3    0
+#define V_LOWSIG3(x) ((x) << S_LOWSIG3)
+#define F_LOWSIG3    V_LOWSIG3(1U)
+
+#define A_NCSI_STAT_TX_BYTE_LOW 0x1a300
+#define A_NCSI_STAT_TX_BYTE_HIGH 0x1a304
+#define A_NCSI_STAT_TX_FRAME_LOW 0x1a308
+#define A_NCSI_STAT_TX_FRAME_HIGH 0x1a30c
+#define A_NCSI_STAT_TX_BCAST 0x1a310
+#define A_NCSI_STAT_TX_MCAST 0x1a314
+#define A_NCSI_STAT_TX_PAUSE 0x1a318
+#define A_NCSI_STAT_TX_64B_FRAMES 0x1a31c
+#define A_NCSI_STAT_TX_65_127B_FRAMES 0x1a320
+#define A_NCSI_STAT_TX_128_255B_FRAMES 0x1a324
+#define A_NCSI_STAT_TX_256_511B_FRAMES 0x1a328
+#define A_NCSI_STAT_TX_512_1023B_FRAMES 0x1a32c
+#define A_NCSI_STAT_TX_1024_1518B_FRAMES 0x1a330
+#define A_NCSI_STAT_TX_1519_MAXB_FRAMES 0x1a334
+#define A_NCSI_STAT_TX_ERR_FRAMES 0x1a338
+#define A_NCSI_STAT_RX_BYTES_LOW 0x1a33c
+#define A_NCSI_STAT_RX_BYTES_HIGH 0x1a340
+#define A_NCSI_STAT_RX_FRAMES_LOW 0x1a344
+#define A_NCSI_STAT_RX_FRAMES_HIGH 0x1a348
+#define A_NCSI_STAT_RX_BCAST_FRAMES 0x1a34c
+#define A_NCSI_STAT_RX_MCAST_FRAMES 0x1a350
+#define A_NCSI_STAT_RX_PAUSE_FRAMES 0x1a354
+#define A_NCSI_STAT_RX_64B_FRAMES 0x1a358
+#define A_NCSI_STAT_RX_65_127B_FRAMES 0x1a35c
+#define A_NCSI_STAT_RX_128_255B_FRAMES 0x1a360
+#define A_NCSI_STAT_RX_256_511B_FRAMES 0x1a364
+#define A_NCSI_STAT_RX_512_1023B_FRAMES 0x1a368
+#define A_NCSI_STAT_RX_1024_1518B_FRAMES 0x1a36c
+#define A_NCSI_STAT_RX_1519_MAXB_FRAMES 0x1a370
+#define A_NCSI_STAT_RX_SHORT_FRAMES 0x1a374
+#define A_NCSI_STAT_RX_OVERSIZE_FRAMES 0x1a378
+#define A_NCSI_STAT_RX_JABBER_FRAMES 0x1a37c
+#define A_NCSI_STAT_RX_CRC_ERR_FRAMES 0x1a380
+#define A_NCSI_STAT_RX_LENGTH_ERR_FRAMES 0x1a384
+#define A_NCSI_STAT_RX_SYM_CODE_ERR_FRAMES 0x1a388
+#define A_NCSI_XAUI_PCS_ERR 0x1a398
+
+#define S_PCS_SYNCSTATUS    5
+#define M_PCS_SYNCSTATUS    0xfU
+#define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
+#define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
+
+#define S_PCS_CTCFIFOERR    1
+#define M_PCS_CTCFIFOERR    0xfU
+#define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
+#define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
+
+#define S_PCS_NOTALIGNED    0
+#define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
+#define F_PCS_NOTALIGNED    V_PCS_NOTALIGNED(1U)
+
+#define A_NCSI_RGMII_STATUS 0x1a39c
+
+#define S_GMIIDUPLEX    3
+#define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
+#define F_GMIIDUPLEX    V_GMIIDUPLEX(1U)
+
+#define S_GMIISPEED    1
+#define M_GMIISPEED    0x3U
+#define V_GMIISPEED(x) ((x) << S_GMIISPEED)
+#define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
+
+#define S_GMIILINKSTATUS    0
+#define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
+#define F_GMIILINKSTATUS    V_GMIILINKSTATUS(1U)
+
+#define A_NCSI_WOL_STATUS 0x1a3a0
+
+#define S_T7_PATDETECTED    31
+#define V_T7_PATDETECTED(x) ((x) << S_T7_PATDETECTED)
+#define F_T7_PATDETECTED    V_T7_PATDETECTED(1U)
+
+#define A_NCSI_RX_MAX_PKT_SIZE_ERR_CNT 0x1a3a4
+#define A_NCSI_TX_SPI4_SOP_EOP_CNT 0x1a3a8
+
+#define S_TXSPI4SOPCNT    16
+#define M_TXSPI4SOPCNT    0xffffU
+#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
+#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
+
+#define S_TXSPI4EOPCNT    0
+#define M_TXSPI4EOPCNT    0xffffU
+#define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
+#define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
+
+#define A_NCSI_RX_SPI4_SOP_EOP_CNT 0x1a3ac
+
+#define S_RXSPI4SOPCNT    16
+#define M_RXSPI4SOPCNT    0xffffU
+#define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
+#define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
+
+#define S_RXSPI4EOPCNT    0
+#define M_RXSPI4EOPCNT    0xffffU
+#define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
+#define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
+
 /* registers for module XGMAC */
 #define XGMAC_BASE_ADDR 0x0
 
@@ -44054,6 +56225,16 @@
 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
 
+#define S_T7_IBQGEN1    10
+#define M_T7_IBQGEN1    0x3fU
+#define V_T7_IBQGEN1(x) ((x) << S_T7_IBQGEN1)
+#define G_T7_IBQGEN1(x) (((x) >> S_T7_IBQGEN1) & M_T7_IBQGEN1)
+
+#define S_T7_IBQEMPTY    0
+#define M_T7_IBQEMPTY    0x3ffU
+#define V_T7_IBQEMPTY(x) ((x) << S_T7_IBQEMPTY)
+#define G_T7_IBQEMPTY(x) (((x) >> S_T7_IBQEMPTY) & M_T7_IBQEMPTY)
+
 #define A_UP_OBQ_GEN 0xc
 
 #define S_OBQGEN    6
@@ -44076,6 +56257,16 @@
 #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
 #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
 
+#define S_T7_T5_OBQGEN    16
+#define M_T7_T5_OBQGEN    0xffffU
+#define V_T7_T5_OBQGEN(x) ((x) << S_T7_T5_OBQGEN)
+#define G_T7_T5_OBQGEN(x) (((x) >> S_T7_T5_OBQGEN) & M_T7_T5_OBQGEN)
+
+#define S_T7_T5_OBQFULL    0
+#define M_T7_T5_OBQFULL    0xffffU
+#define V_T7_T5_OBQFULL(x) ((x) << S_T7_T5_OBQFULL)
+#define G_T7_T5_OBQFULL(x) (((x) >> S_T7_T5_OBQFULL) & M_T7_T5_OBQFULL)
+
 #define A_UP_IBQ_0_RDADDR 0x10
 
 #define S_QUEID    13
@@ -44088,6 +56279,13 @@
 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
 
+#define A_UP_IBQ_GEN_IPC 0x10
+
+#define S_IPCEMPTY    0
+#define M_IPCEMPTY    0x7fU
+#define V_IPCEMPTY(x) ((x) << S_IPCEMPTY)
+#define G_IPCEMPTY(x) (((x) >> S_IPCEMPTY) & M_IPCEMPTY)
+
 #define A_UP_IBQ_0_WRADDR 0x14
 
 #define S_IBQWRADDR    0
@@ -44160,10 +56358,15 @@
 #define A_UP_OBQ_0_STATUS 0x78
 #define A_UP_OBQ_0_PKTCNT 0x7c
 #define A_UP_OBQ_1_RDADDR 0x80
+#define A_UP_NXT_FLOWADDR0 0x80
 #define A_UP_OBQ_1_WRADDR 0x84
+#define A_UP_NXT_FLOWADDR1 0x84
 #define A_UP_OBQ_1_STATUS 0x88
+#define A_UP_NXT_FLOWADDR2 0x88
 #define A_UP_OBQ_1_PKTCNT 0x8c
+#define A_UP_NXT_FLOWADDR3 0x8c
 #define A_UP_OBQ_2_RDADDR 0x90
+#define A_UP_DFT_FLOWADDR 0x90
 #define A_UP_OBQ_2_WRADDR 0x94
 #define A_UP_OBQ_2_STATUS 0x98
 #define A_UP_OBQ_2_PKTCNT 0x9c
@@ -44176,9 +56379,33 @@
 #define A_UP_OBQ_4_STATUS 0xb8
 #define A_UP_OBQ_4_PKTCNT 0xbc
 #define A_UP_OBQ_5_RDADDR 0xc0
+#define A_UP_MAX_SEQ_NUM 0xc0
 #define A_UP_OBQ_5_WRADDR 0xc4
+#define A_UP_UNACK_SEQ_NUM 0xc4
 #define A_UP_OBQ_5_STATUS 0xc8
+#define A_UP_SEARCH_SEQ_NUM 0xc8
 #define A_UP_OBQ_5_PKTCNT 0xcc
+#define A_UP_SEQ_SEARCH_CTRL 0xcc
+
+#define S_FIFO_SIZE    29
+#define M_FIFO_SIZE    0x7U
+#define V_FIFO_SIZE(x) ((x) << S_FIFO_SIZE)
+#define G_FIFO_SIZE(x) (((x) >> S_FIFO_SIZE) & M_FIFO_SIZE)
+
+#define S_ROCE_MODE    28
+#define V_ROCE_MODE(x) ((x) << S_ROCE_MODE)
+#define F_ROCE_MODE    V_ROCE_MODE(1U)
+
+#define S_SEQ_WR_PTR    16
+#define M_SEQ_WR_PTR    0xfffU
+#define V_SEQ_WR_PTR(x) ((x) << S_SEQ_WR_PTR)
+#define G_SEQ_WR_PTR(x) (((x) >> S_SEQ_WR_PTR) & M_SEQ_WR_PTR)
+
+#define S_SEQ_RD_PTR    0
+#define M_SEQ_RD_PTR    0xfffU
+#define V_SEQ_RD_PTR(x) ((x) << S_SEQ_RD_PTR)
+#define G_SEQ_RD_PTR(x) (((x) >> S_SEQ_RD_PTR) & M_SEQ_RD_PTR)
+
 #define A_UP_IBQ_0_CONFIG 0xd0
 
 #define S_QUESIZE    26
@@ -44203,6 +56430,25 @@
 #define V_QUE1KEN(x) ((x) << S_QUE1KEN)
 #define F_QUE1KEN    V_QUE1KEN(1U)
 
+#define A_UP_SEQ_SEARCH_RES0 0xd0
+
+#define S_INV_SEQ    18
+#define V_INV_SEQ(x) ((x) << S_INV_SEQ)
+#define F_INV_SEQ    V_INV_SEQ(1U)
+
+#define S_DUP_SEQ    17
+#define V_DUP_SEQ(x) ((x) << S_DUP_SEQ)
+#define F_DUP_SEQ    V_DUP_SEQ(1U)
+
+#define S_MATCH_VLD    16
+#define V_MATCH_VLD(x) ((x) << S_MATCH_VLD)
+#define F_MATCH_VLD    V_MATCH_VLD(1U)
+
+#define S_MATCH_INDEX    0
+#define M_MATCH_INDEX    0xffffU
+#define V_MATCH_INDEX(x) ((x) << S_MATCH_INDEX)
+#define G_MATCH_INDEX(x) (((x) >> S_MATCH_INDEX) & M_MATCH_INDEX)
+
 #define A_UP_IBQ_0_REALADDR 0xd4
 
 #define S_QUERDADDRWRAP    31
@@ -44218,6 +56464,7 @@
 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
 
+#define A_UP_SEQ_SEARCH_RES1 0xd4
 #define A_UP_IBQ_1_CONFIG 0xd8
 #define A_UP_IBQ_1_REALADDR 0xdc
 #define A_UP_IBQ_2_CONFIG 0xe0
@@ -44229,14 +56476,34 @@
 #define A_UP_IBQ_5_CONFIG 0xf8
 #define A_UP_IBQ_5_REALADDR 0xfc
 #define A_UP_OBQ_0_CONFIG 0x100
+#define A_UP_PEER_HALT_STAT0 0x100
+
+#define S_HALTINFO    1
+#define M_HALTINFO    0x7fffffffU
+#define V_HALTINFO(x) ((x) << S_HALTINFO)
+#define G_HALTINFO(x) (((x) >> S_HALTINFO) & M_HALTINFO)
+
 #define A_UP_OBQ_0_REALADDR 0x104
+#define A_UP_PEER_HALT_STAT1 0x104
 #define A_UP_OBQ_1_CONFIG 0x108
+#define A_UP_PEER_HALT_STAT2 0x108
 #define A_UP_OBQ_1_REALADDR 0x10c
+#define A_UP_PEER_HALT_STAT3 0x10c
 #define A_UP_OBQ_2_CONFIG 0x110
+#define A_UP_PEER_HALT_STAT4 0x110
 #define A_UP_OBQ_2_REALADDR 0x114
+#define A_UP_PEER_HALT_STAT5 0x114
 #define A_UP_OBQ_3_CONFIG 0x118
+#define A_UP_PEER_HALT_STAT6 0x118
 #define A_UP_OBQ_3_REALADDR 0x11c
+#define A_UP_PEER_HALT_STAT7 0x11c
 #define A_UP_OBQ_4_CONFIG 0x120
+#define A_UP_PEER_HALT_CTL 0x120
+
+#define S_HALTREQ    0
+#define V_HALTREQ(x) ((x) << S_HALTREQ)
+#define F_HALTREQ    V_HALTREQ(1U)
+
 #define A_UP_OBQ_4_REALADDR 0x124
 #define A_UP_OBQ_5_CONFIG 0x128
 #define A_UP_OBQ_5_REALADDR 0x12c
@@ -44516,6 +56783,204 @@
 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
+#define A_T7_UP_IBQ_0_SHADOW_RDADDR 0x400
+#define A_T7_UP_IBQ_0_SHADOW_WRADDR 0x404
+#define A_T7_UP_IBQ_0_SHADOW_STATUS 0x408
+
+#define S_T7_QUEREMFLITS    0
+#define M_T7_QUEREMFLITS    0xfffU
+#define V_T7_QUEREMFLITS(x) ((x) << S_T7_QUEREMFLITS)
+#define G_T7_QUEREMFLITS(x) (((x) >> S_T7_QUEREMFLITS) & M_T7_QUEREMFLITS)
+
+#define A_T7_UP_IBQ_0_SHADOW_PKTCNT 0x40c
+#define A_T7_UP_IBQ_1_SHADOW_RDADDR 0x410
+#define A_T7_UP_IBQ_1_SHADOW_WRADDR 0x414
+#define A_T7_UP_IBQ_1_SHADOW_STATUS 0x418
+#define A_T7_UP_IBQ_1_SHADOW_PKTCNT 0x41c
+#define A_T7_UP_IBQ_2_SHADOW_RDADDR 0x420
+#define A_T7_UP_IBQ_2_SHADOW_WRADDR 0x424
+#define A_T7_UP_IBQ_2_SHADOW_STATUS 0x428
+#define A_T7_UP_IBQ_2_SHADOW_PKTCNT 0x42c
+#define A_T7_UP_IBQ_3_SHADOW_RDADDR 0x430
+#define A_T7_UP_IBQ_3_SHADOW_WRADDR 0x434
+#define A_T7_UP_IBQ_3_SHADOW_STATUS 0x438
+#define A_T7_UP_IBQ_3_SHADOW_PKTCNT 0x43c
+#define A_T7_UP_IBQ_4_SHADOW_RDADDR 0x440
+#define A_T7_UP_IBQ_4_SHADOW_WRADDR 0x444
+#define A_T7_UP_IBQ_4_SHADOW_STATUS 0x448
+#define A_T7_UP_IBQ_4_SHADOW_PKTCNT 0x44c
+#define A_T7_UP_IBQ_5_SHADOW_RDADDR 0x450
+#define A_T7_UP_IBQ_5_SHADOW_WRADDR 0x454
+#define A_T7_UP_IBQ_5_SHADOW_STATUS 0x458
+#define A_T7_UP_IBQ_5_SHADOW_PKTCNT 0x45c
+#define A_UP_IBQ_6_SHADOW_RDADDR 0x460
+#define A_UP_IBQ_6_SHADOW_WRADDR 0x464
+#define A_UP_IBQ_6_SHADOW_STATUS 0x468
+#define A_UP_IBQ_6_SHADOW_PKTCNT 0x46c
+#define A_UP_IBQ_7_SHADOW_RDADDR 0x470
+#define A_UP_IBQ_7_SHADOW_WRADDR 0x474
+#define A_UP_IBQ_7_SHADOW_STATUS 0x478
+#define A_UP_IBQ_7_SHADOW_PKTCNT 0x47c
+#define A_UP_IBQ_8_SHADOW_RDADDR 0x480
+#define A_UP_IBQ_8_SHADOW_WRADDR 0x484
+#define A_UP_IBQ_8_SHADOW_STATUS 0x488
+#define A_UP_IBQ_8_SHADOW_PKTCNT 0x48c
+#define A_UP_IBQ_9_SHADOW_RDADDR 0x490
+#define A_UP_IBQ_9_SHADOW_WRADDR 0x494
+#define A_UP_IBQ_9_SHADOW_STATUS 0x498
+#define A_UP_IBQ_9_SHADOW_PKTCNT 0x49c
+#define A_UP_IBQ_10_SHADOW_RDADDR 0x4a0
+#define A_UP_IBQ_10_SHADOW_WRADDR 0x4a4
+#define A_UP_IBQ_10_SHADOW_STATUS 0x4a8
+#define A_UP_IBQ_10_SHADOW_PKTCNT 0x4ac
+#define A_UP_IBQ_11_SHADOW_RDADDR 0x4b0
+#define A_UP_IBQ_11_SHADOW_WRADDR 0x4b4
+#define A_UP_IBQ_11_SHADOW_STATUS 0x4b8
+#define A_UP_IBQ_11_SHADOW_PKTCNT 0x4bc
+#define A_UP_IBQ_12_SHADOW_RDADDR 0x4c0
+#define A_UP_IBQ_12_SHADOW_WRADDR 0x4c4
+#define A_UP_IBQ_12_SHADOW_STATUS 0x4c8
+#define A_UP_IBQ_12_SHADOW_PKTCNT 0x4cc
+#define A_UP_IBQ_13_SHADOW_RDADDR 0x4d0
+#define A_UP_IBQ_13_SHADOW_WRADDR 0x4d4
+#define A_UP_IBQ_13_SHADOW_STATUS 0x4d8
+#define A_UP_IBQ_13_SHADOW_PKTCNT 0x4dc
+#define A_UP_IBQ_14_SHADOW_RDADDR 0x4e0
+#define A_UP_IBQ_14_SHADOW_WRADDR 0x4e4
+#define A_UP_IBQ_14_SHADOW_STATUS 0x4e8
+#define A_UP_IBQ_14_SHADOW_PKTCNT 0x4ec
+#define A_UP_IBQ_15_SHADOW_RDADDR 0x4f0
+#define A_UP_IBQ_15_SHADOW_WRADDR 0x4f4
+#define A_UP_IBQ_15_SHADOW_STATUS 0x4f8
+#define A_UP_IBQ_15_SHADOW_PKTCNT 0x4fc
+#define A_T7_UP_IBQ_0_SHADOW_CONFIG 0x500
+#define A_T7_UP_IBQ_0_SHADOW_REALADDR 0x504
+#define A_T7_UP_IBQ_1_SHADOW_CONFIG 0x510
+#define A_T7_UP_IBQ_1_SHADOW_REALADDR 0x514
+#define A_T7_UP_IBQ_2_SHADOW_CONFIG 0x520
+#define A_T7_UP_IBQ_2_SHADOW_REALADDR 0x524
+#define A_T7_UP_IBQ_3_SHADOW_CONFIG 0x530
+#define A_T7_UP_IBQ_3_SHADOW_REALADDR 0x534
+#define A_T7_UP_IBQ_4_SHADOW_CONFIG 0x540
+#define A_T7_UP_IBQ_4_SHADOW_REALADDR 0x544
+#define A_T7_UP_IBQ_5_SHADOW_CONFIG 0x550
+#define A_T7_UP_IBQ_5_SHADOW_REALADDR 0x554
+#define A_UP_IBQ_6_SHADOW_CONFIG 0x560
+#define A_UP_IBQ_6_SHADOW_REALADDR 0x564
+#define A_UP_IBQ_7_SHADOW_CONFIG 0x570
+#define A_UP_IBQ_7_SHADOW_REALADDR 0x574
+#define A_UP_IBQ_8_SHADOW_CONFIG 0x580
+#define A_UP_IBQ_8_SHADOW_REALADDR 0x584
+#define A_UP_IBQ_9_SHADOW_CONFIG 0x590
+#define A_UP_IBQ_9_SHADOW_REALADDR 0x594
+#define A_UP_IBQ_10_SHADOW_CONFIG 0x5a0
+#define A_UP_IBQ_10_SHADOW_REALADDR 0x5a4
+#define A_UP_IBQ_11_SHADOW_CONFIG 0x5b0
+#define A_UP_IBQ_11_SHADOW_REALADDR 0x5b4
+#define A_UP_IBQ_12_SHADOW_CONFIG 0x5c0
+#define A_UP_IBQ_12_SHADOW_REALADDR 0x5c4
+#define A_UP_IBQ_13_SHADOW_CONFIG 0x5d0
+#define A_UP_IBQ_13_SHADOW_REALADDR 0x5d4
+#define A_UP_IBQ_14_SHADOW_CONFIG 0x5e0
+#define A_UP_IBQ_14_SHADOW_REALADDR 0x5e4
+#define A_UP_IBQ_15_SHADOW_CONFIG 0x5f0
+#define A_UP_IBQ_15_SHADOW_REALADDR 0x5f4
+#define A_T7_UP_OBQ_0_SHADOW_RDADDR 0x600
+#define A_T7_UP_OBQ_0_SHADOW_WRADDR 0x604
+#define A_T7_UP_OBQ_0_SHADOW_STATUS 0x608
+#define A_T7_UP_OBQ_0_SHADOW_PKTCNT 0x60c
+#define A_T7_UP_OBQ_1_SHADOW_RDADDR 0x610
+#define A_T7_UP_OBQ_1_SHADOW_WRADDR 0x614
+#define A_T7_UP_OBQ_1_SHADOW_STATUS 0x618
+#define A_T7_UP_OBQ_1_SHADOW_PKTCNT 0x61c
+#define A_T7_UP_OBQ_2_SHADOW_RDADDR 0x620
+#define A_T7_UP_OBQ_2_SHADOW_WRADDR 0x624
+#define A_T7_UP_OBQ_2_SHADOW_STATUS 0x628
+#define A_T7_UP_OBQ_2_SHADOW_PKTCNT 0x62c
+#define A_T7_UP_OBQ_3_SHADOW_RDADDR 0x630
+#define A_T7_UP_OBQ_3_SHADOW_WRADDR 0x634
+#define A_T7_UP_OBQ_3_SHADOW_STATUS 0x638
+#define A_T7_UP_OBQ_3_SHADOW_PKTCNT 0x63c
+#define A_T7_UP_OBQ_4_SHADOW_RDADDR 0x640
+#define A_T7_UP_OBQ_4_SHADOW_WRADDR 0x644
+#define A_T7_UP_OBQ_4_SHADOW_STATUS 0x648
+#define A_T7_UP_OBQ_4_SHADOW_PKTCNT 0x64c
+#define A_T7_UP_OBQ_5_SHADOW_RDADDR 0x650
+#define A_T7_UP_OBQ_5_SHADOW_WRADDR 0x654
+#define A_T7_UP_OBQ_5_SHADOW_STATUS 0x658
+#define A_T7_UP_OBQ_5_SHADOW_PKTCNT 0x65c
+#define A_T7_UP_OBQ_6_SHADOW_RDADDR 0x660
+#define A_T7_UP_OBQ_6_SHADOW_WRADDR 0x664
+#define A_T7_UP_OBQ_6_SHADOW_STATUS 0x668
+#define A_T7_UP_OBQ_6_SHADOW_PKTCNT 0x66c
+#define A_T7_UP_OBQ_7_SHADOW_RDADDR 0x670
+#define A_T7_UP_OBQ_7_SHADOW_WRADDR 0x674
+#define A_T7_UP_OBQ_7_SHADOW_STATUS 0x678
+#define A_T7_UP_OBQ_7_SHADOW_PKTCNT 0x67c
+#define A_UP_OBQ_8_SHADOW_RDADDR 0x680
+#define A_UP_OBQ_8_SHADOW_WRADDR 0x684
+#define A_UP_OBQ_8_SHADOW_STATUS 0x688
+#define A_UP_OBQ_8_SHADOW_PKTCNT 0x68c
+#define A_UP_OBQ_9_SHADOW_RDADDR 0x690
+#define A_UP_OBQ_9_SHADOW_WRADDR 0x694
+#define A_UP_OBQ_9_SHADOW_STATUS 0x698
+#define A_UP_OBQ_9_SHADOW_PKTCNT 0x69c
+#define A_UP_OBQ_10_SHADOW_RDADDR 0x6a0
+#define A_UP_OBQ_10_SHADOW_WRADDR 0x6a4
+#define A_UP_OBQ_10_SHADOW_STATUS 0x6a8
+#define A_UP_OBQ_10_SHADOW_PKTCNT 0x6ac
+#define A_UP_OBQ_11_SHADOW_RDADDR 0x6b0
+#define A_UP_OBQ_11_SHADOW_WRADDR 0x6b4
+#define A_UP_OBQ_11_SHADOW_STATUS 0x6b8
+#define A_UP_OBQ_11_SHADOW_PKTCNT 0x6bc
+#define A_UP_OBQ_12_SHADOW_RDADDR 0x6c0
+#define A_UP_OBQ_12_SHADOW_WRADDR 0x6c4
+#define A_UP_OBQ_12_SHADOW_STATUS 0x6c8
+#define A_UP_OBQ_12_SHADOW_PKTCNT 0x6cc
+#define A_UP_OBQ_13_SHADOW_RDADDR 0x6d0
+#define A_UP_OBQ_13_SHADOW_WRADDR 0x6d4
+#define A_UP_OBQ_13_SHADOW_STATUS 0x6d8
+#define A_UP_OBQ_13_SHADOW_PKTCNT 0x6dc
+#define A_UP_OBQ_14_SHADOW_RDADDR 0x6e0
+#define A_UP_OBQ_14_SHADOW_WRADDR 0x6e4
+#define A_UP_OBQ_14_SHADOW_STATUS 0x6e8
+#define A_UP_OBQ_14_SHADOW_PKTCNT 0x6ec
+#define A_UP_OBQ_15_SHADOW_RDADDR 0x6f0
+#define A_UP_OBQ_15_SHADOW_WRADDR 0x6f4
+#define A_UP_OBQ_15_SHADOW_STATUS 0x6f8
+#define A_UP_OBQ_15_SHADOW_PKTCNT 0x6fc
+#define A_T7_UP_OBQ_0_SHADOW_CONFIG 0x700
+#define A_T7_UP_OBQ_0_SHADOW_REALADDR 0x704
+#define A_T7_UP_OBQ_1_SHADOW_CONFIG 0x710
+#define A_T7_UP_OBQ_1_SHADOW_REALADDR 0x714
+#define A_T7_UP_OBQ_2_SHADOW_CONFIG 0x720
+#define A_T7_UP_OBQ_2_SHADOW_REALADDR 0x724
+#define A_T7_UP_OBQ_3_SHADOW_CONFIG 0x730
+#define A_T7_UP_OBQ_3_SHADOW_REALADDR 0x734
+#define A_T7_UP_OBQ_4_SHADOW_CONFIG 0x740
+#define A_T7_UP_OBQ_4_SHADOW_REALADDR 0x744
+#define A_T7_UP_OBQ_5_SHADOW_CONFIG 0x750
+#define A_T7_UP_OBQ_5_SHADOW_REALADDR 0x754
+#define A_T7_UP_OBQ_6_SHADOW_CONFIG 0x760
+#define A_T7_UP_OBQ_6_SHADOW_REALADDR 0x764
+#define A_T7_UP_OBQ_7_SHADOW_CONFIG 0x770
+#define A_T7_UP_OBQ_7_SHADOW_REALADDR 0x774
+#define A_UP_OBQ_8_SHADOW_CONFIG 0x780
+#define A_UP_OBQ_8_SHADOW_REALADDR 0x784
+#define A_UP_OBQ_9_SHADOW_CONFIG 0x790
+#define A_UP_OBQ_9_SHADOW_REALADDR 0x794
+#define A_UP_OBQ_10_SHADOW_CONFIG 0x7a0
+#define A_UP_OBQ_10_SHADOW_REALADDR 0x7a4
+#define A_UP_OBQ_11_SHADOW_CONFIG 0x7b0
+#define A_UP_OBQ_11_SHADOW_REALADDR 0x7b4
+#define A_UP_OBQ_12_SHADOW_CONFIG 0x7c0
+#define A_UP_OBQ_12_SHADOW_REALADDR 0x7c4
+#define A_UP_OBQ_13_SHADOW_CONFIG 0x7d0
+#define A_UP_OBQ_13_SHADOW_REALADDR 0x7d4
+#define A_UP_OBQ_14_SHADOW_CONFIG 0x7e0
+#define A_UP_OBQ_14_SHADOW_REALADDR 0x7e4
+#define A_UP_OBQ_15_SHADOW_CONFIG 0x7f0
+#define A_UP_OBQ_15_SHADOW_REALADDR 0x7f4
 
 /* registers for module CIM_CTL */
 #define CIM_CTL_BASE_ADDR 0x0
@@ -44579,17 +57044,63 @@
 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
+#define A_CIM_CTL_SEM_CFG 0x40
+
+#define S_SEMINIT    31
+#define V_SEMINIT(x) ((x) << S_SEMINIT)
+#define F_SEMINIT    V_SEMINIT(1U)
+
+#define S_NUMSEM    0
+#define M_NUMSEM    0x3ffffU
+#define V_NUMSEM(x) ((x) << S_NUMSEM)
+#define G_NUMSEM(x) (((x) >> S_NUMSEM) & M_NUMSEM)
+
 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
+#define A_CIM_CTL_SEM_MA_CFG 0x44
+
+#define S_SEMMABASE    4
+#define M_SEMMABASE    0xfffffffU
+#define V_SEMMABASE(x) ((x) << S_SEMMABASE)
+#define G_SEMMABASE(x) (((x) >> S_SEMMABASE) & M_SEMMABASE)
+
+#define S_SEMMATHREADID    0
+#define M_SEMMATHREADID    0x7U
+#define V_SEMMATHREADID(x) ((x) << S_SEMMATHREADID)
+#define G_SEMMATHREADID(x) (((x) >> S_SEMMATHREADID) & M_SEMMATHREADID)
+
 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
+#define A_CIM_CTL_LOCK_CFG 0x50
+
+#define S_NUMLOCK    0
+#define M_NUMLOCK    0x3ffffU
+#define V_NUMLOCK(x) ((x) << S_NUMLOCK)
+#define G_NUMLOCK(x) (((x) >> S_NUMLOCK) & M_NUMLOCK)
+
 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
+#define A_CIM_CTL_LOCK_MA_CFG 0x54
+
+#define S_LOCKMABASE    4
+#define M_LOCKMABASE    0xfffffffU
+#define V_LOCKMABASE(x) ((x) << S_LOCKMABASE)
+#define G_LOCKMABASE(x) (((x) >> S_LOCKMABASE) & M_LOCKMABASE)
+
+#define S_LOCKMATHREADID    0
+#define M_LOCKMATHREADID    0x7U
+#define V_LOCKMATHREADID(x) ((x) << S_LOCKMATHREADID)
+#define G_LOCKMATHREADID(x) (((x) >> S_LOCKMATHREADID) & M_LOCKMATHREADID)
+
 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
+#define A_CIM_CTL_RSA_INT 0x60
 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
+#define A_CIM_CTL_RSA_BUSY 0x64
 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
+#define A_CIM_CTL_RSA_CPERR 0x68
 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
+#define A_CIM_CTL_RSA_DPERR 0x6c
 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
@@ -44650,6 +57161,66 @@
 #define A_CIM_CTL_GEN_TIMER3 0xd0
 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
+#define A_CIM_CTL_TID_MAP_EN 0x500
+#define A_CIM_CTL_TID_MAP_CORE 0x520
+#define A_CIM_CTL_TID_MAP_CONFIG 0x540
+
+#define S_TIDDEFCORE    4
+#define M_TIDDEFCORE    0xfU
+#define V_TIDDEFCORE(x) ((x) << S_TIDDEFCORE)
+#define G_TIDDEFCORE(x) (((x) >> S_TIDDEFCORE) & M_TIDDEFCORE)
+
+#define S_TIDVECBASE    0
+#define M_TIDVECBASE    0x7U
+#define V_TIDVECBASE(x) ((x) << S_TIDVECBASE)
+#define G_TIDVECBASE(x) (((x) >> S_TIDVECBASE) & M_TIDVECBASE)
+
+#define A_CIM_CTL_CRYPTO_KEY_DATA 0x600
+#define A_CIM_CTL_SECURE_CONFIG 0x6f8
+#define A_CIM_CTL_CRYPTO_KEY_CTRL 0x6fc
+
+#define S_CRYPTOKEYDATAREGNUM    8
+#define M_CRYPTOKEYDATAREGNUM    0xffU
+#define V_CRYPTOKEYDATAREGNUM(x) ((x) << S_CRYPTOKEYDATAREGNUM)
+#define G_CRYPTOKEYDATAREGNUM(x) (((x) >> S_CRYPTOKEYDATAREGNUM) & M_CRYPTOKEYDATAREGNUM)
+
+#define S_CRYPTOKEYSTARTBUSY    0
+#define V_CRYPTOKEYSTARTBUSY(x) ((x) << S_CRYPTOKEYSTARTBUSY)
+#define F_CRYPTOKEYSTARTBUSY    V_CRYPTOKEYSTARTBUSY(1U)
+
+#define A_CIM_CTL_FLOWID_OP_VALID 0x700
+#define A_CIM_CTL_FLOWID_CTL 0x720
+
+#define S_FLOWBASEADDR    8
+#define M_FLOWBASEADDR    0xffffffU
+#define V_FLOWBASEADDR(x) ((x) << S_FLOWBASEADDR)
+#define G_FLOWBASEADDR(x) (((x) >> S_FLOWBASEADDR) & M_FLOWBASEADDR)
+
+#define S_SEQSRCHALIGNCFG    4
+#define M_SEQSRCHALIGNCFG    0x3U
+#define V_SEQSRCHALIGNCFG(x) ((x) << S_SEQSRCHALIGNCFG)
+#define G_SEQSRCHALIGNCFG(x) (((x) >> S_SEQSRCHALIGNCFG) & M_SEQSRCHALIGNCFG)
+
+#define S_FLOWADDRSIZE    1
+#define M_FLOWADDRSIZE    0x3U
+#define V_FLOWADDRSIZE(x) ((x) << S_FLOWADDRSIZE)
+#define G_FLOWADDRSIZE(x) (((x) >> S_FLOWADDRSIZE) & M_FLOWADDRSIZE)
+
+#define S_FLOWIDEN    0
+#define V_FLOWIDEN(x) ((x) << S_FLOWIDEN)
+#define F_FLOWIDEN    V_FLOWIDEN(1U)
+
+#define A_CIM_CTL_FLOWID_MAX 0x724
+
+#define S_MAXFLOWID    0
+#define M_MAXFLOWID    0xffffffU
+#define V_MAXFLOWID(x) ((x) << S_MAXFLOWID)
+#define G_MAXFLOWID(x) (((x) >> S_MAXFLOWID) & M_MAXFLOWID)
+
+#define A_CIM_CTL_FLOWID_HINT0 0x728
+#define A_CIM_CTL_EFUSE_CTRL 0x780
+#define A_CIM_CTL_EFUSE_QOUT 0x784
+#define A_CIM_CTL_EFUSE_RFOUT 0x788
 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
 
 #define S_TSCHNLEN    31
@@ -45001,14 +57572,19 @@
 #define A_CIM_CTL_TSCH_TICK3 0xd8c
 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
+#define A_T7_CIM_CTL_MAILBOX_PF0_CTL 0xd90
 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
+#define A_T7_CIM_CTL_MAILBOX_PF1_CTL 0xd94
 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
+#define A_T7_CIM_CTL_MAILBOX_PF2_CTL 0xd98
 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
 #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
+#define A_T7_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
+#define A_T7_CIM_CTL_MAILBOX_PF4_CTL 0xda0
 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
 
 #define S_PF7_OWNER_PL    15
@@ -45076,6 +57652,7 @@
 #define F_PF0_OWNER_UP    V_PF0_OWNER_UP(1U)
 
 #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
+#define A_T7_CIM_CTL_MAILBOX_PF5_CTL 0xda4
 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
 
 #define S_T5_CTLRID    0
@@ -45084,15 +57661,13 @@
 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
 
 #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
+#define A_T7_CIM_CTL_MAILBOX_PF6_CTL 0xda8
 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
+#define A_T7_CIM_CTL_MAILBOX_PF7_CTL 0xdac
 #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
+#define A_T7_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
-
-#define S_T6_UPRID    0
-#define M_T6_UPRID    0x1ffU
-#define V_T6_UPRID(x) ((x) << S_T6_UPRID)
-#define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
-
+#define A_T7_CIM_CTL_PIO_MST_CONFIG 0xdb4
 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
@@ -45119,6 +57694,64 @@
 #define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT)
 #define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT)
 
+#define A_CIM_CTL_BREAK 0xf00
+
+#define S_XOCDMODE    8
+#define M_XOCDMODE    0xffU
+#define V_XOCDMODE(x) ((x) << S_XOCDMODE)
+#define G_XOCDMODE(x) (((x) >> S_XOCDMODE) & M_XOCDMODE)
+
+#define S_BREAKIN_CONTROL    0
+#define M_BREAKIN_CONTROL    0xffU
+#define V_BREAKIN_CONTROL(x) ((x) << S_BREAKIN_CONTROL)
+#define G_BREAKIN_CONTROL(x) (((x) >> S_BREAKIN_CONTROL) & M_BREAKIN_CONTROL)
+
+#define A_CIM_CTL_SLV_BOOT_CFG 0x4000
+
+#define S_T7_UPGEN    3
+#define M_T7_UPGEN    0x1fU
+#define V_T7_UPGEN(x) ((x) << S_T7_UPGEN)
+#define G_T7_UPGEN(x) (((x) >> S_T7_UPGEN) & M_T7_UPGEN)
+
+#define S_UPCLKEN    2
+#define V_UPCLKEN(x) ((x) << S_UPCLKEN)
+#define F_UPCLKEN    V_UPCLKEN(1U)
+
+#define A_CIM_CTL_SLV_BOOT_LEN 0x4004
+#define A_CIM_CTL_SLV_ACC_INT_ENABLE 0x4008
+#define A_CIM_CTL_SLV_ACC_INT_CAUSE 0x400c
+#define A_CIM_CTL_SLV_INT_ENABLE 0x4010
+#define A_CIM_CTL_SLV_INT_CAUSE 0x4014
+#define A_CIM_CTL_SLV_PERR_ENABLE 0x4018
+#define A_CIM_CTL_SLV_PERR_CAUSE 0x401c
+#define A_CIM_CTL_SLV_ADDR_TIMEOUT 0x4028
+#define A_CIM_CTL_SLV_ADDR_ILLEGAL 0x402c
+#define A_CIM_CTL_SLV_PIO_MST_CONFIG 0x4030
+#define A_CIM_CTL_SLV_MEM_ZONE0_VA 0x4040
+#define A_CIM_CTL_SLV_MEM_ZONE0_BA 0x4044
+#define A_CIM_CTL_SLV_MEM_ZONE0_LEN 0x4048
+#define A_CIM_CTL_SLV_MEM_ZONE1_VA 0x404c
+#define A_CIM_CTL_SLV_MEM_ZONE1_BA 0x4050
+#define A_CIM_CTL_SLV_MEM_ZONE1_LEN 0x4054
+#define A_CIM_CTL_SLV_MEM_ZONE2_VA 0x4058
+#define A_CIM_CTL_SLV_MEM_ZONE2_BA 0x405c
+#define A_CIM_CTL_SLV_MEM_ZONE2_LEN 0x4060
+#define A_CIM_CTL_SLV_MEM_ZONE3_VA 0x4064
+#define A_CIM_CTL_SLV_MEM_ZONE3_BA 0x4068
+#define A_CIM_CTL_SLV_MEM_ZONE3_LEN 0x406c
+#define A_CIM_CTL_SLV_MEM_ZONE4_VA 0x4070
+#define A_CIM_CTL_SLV_MEM_ZONE4_BA 0x4074
+#define A_CIM_CTL_SLV_MEM_ZONE4_LEN 0x4078
+#define A_CIM_CTL_SLV_MEM_ZONE5_VA 0x407c
+#define A_CIM_CTL_SLV_MEM_ZONE5_BA 0x4080
+#define A_CIM_CTL_SLV_MEM_ZONE5_LEN 0x4084
+#define A_CIM_CTL_SLV_MEM_ZONE6_VA 0x4088
+#define A_CIM_CTL_SLV_MEM_ZONE6_BA 0x408c
+#define A_CIM_CTL_SLV_MEM_ZONE6_LEN 0x4090
+#define A_CIM_CTL_SLV_MEM_ZONE7_VA 0x4094
+#define A_CIM_CTL_SLV_MEM_ZONE7_BA 0x4098
+#define A_CIM_CTL_SLV_MEM_ZONE7_LEN 0x409c
+
 /* registers for module MAC */
 #define MAC_BASE_ADDR 0x0
 
@@ -46613,33 +59246,7 @@
 #define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)
 
 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
-
-#define S_T6_PERR_PKT_RAM    31
-#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
-#define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
-
-#define S_T6_PERR_MASK_RAM    30
-#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
-#define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
-
-#define S_T6_PERR_CRC_RAM    29
-#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
-#define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
-
 #define A_MAC_PORT_PERR_ENABLE 0x8e8
-
-#define S_T6_PERR_PKT_RAM    31
-#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
-#define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
-
-#define S_T6_PERR_MASK_RAM    30
-#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
-#define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
-
-#define S_T6_PERR_CRC_RAM    29
-#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
-#define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
-
 #define A_MAC_PORT_PERR_INJECT 0x8ec
 
 #define S_MEMSEL_PERR    1
@@ -47304,10 +59911,12 @@
 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
 
+#if 0
 #define S_B    16
-#define CXGBE_M_B    0xffffU
+#define M_B    0xffffU
 #define V_B(x) ((x) << S_B)
-#define G_B(x) (((x) >> S_B) & CXGBE_M_B)
+#define G_B(x) (((x) >> S_B) & M_B)
+#endif
 
 #define S_A    0
 #define M_A    0xffffU
@@ -48454,10 +61063,6 @@
 #define V_LOW_POWER(x) ((x) << S_LOW_POWER)
 #define F_LOW_POWER    V_LOW_POWER(1U)
 
-#define S_T6_SPEED_SEL1    6
-#define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
-#define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
-
 #define S_SPEED_SEL2    2
 #define M_SPEED_SEL2    0xfU
 #define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2)
@@ -49016,7 +61621,7 @@
 #define S_VLANTAG    0
 #define CXGBE_M_VLANTAG    0xffffU
 #define V_VLANTAG(x) ((x) << S_VLANTAG)
-#define G_VLANTAG(x) (((x) >> S_VLANTAG) & CXGBE_M_VLANTAG)
+#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
 
 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
@@ -51279,75 +63884,24 @@
 #define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM)
 
 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
-
-#define S_T6_INIT_METH    12
-#define M_T6_INIT_METH    0xfU
-#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
-#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
-
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
 #define A_MAC_PORT_AET_STATUS_1 0x2b30
-
-#define S_T6_NEU_STATE    4
-#define M_T6_NEU_STATE    0xfU
-#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
-#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
-
-#define S_T6_CTRL_STATE    0
-#define M_T6_CTRL_STATE    0xfU
-#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
-#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
-
 #define A_MAC_PORT_AET_STATUS_21 0x2b34
 #define A_MAC_PORT_AET_LIMITS1 0x2b38
 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
-
-#define S_T6_INIT_METH    12
-#define M_T6_INIT_METH    0xfU
-#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
-#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
-
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
 #define A_MAC_PORT_AET_STATUS_2 0x2b50
-
-#define S_T6_NEU_STATE    4
-#define M_T6_NEU_STATE    0xfU
-#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
-#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
-
-#define S_T6_CTRL_STATE    0
-#define M_T6_CTRL_STATE    0xfU
-#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
-#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
-
 #define A_MAC_PORT_AET_STATUS_22 0x2b54
 #define A_MAC_PORT_AET_LIMITS2 0x2b58
 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
-
-#define S_T6_INIT_METH    12
-#define M_T6_INIT_METH    0xfU
-#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
-#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
-
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
 #define A_MAC_PORT_AET_STATUS_3 0x2b70
-
-#define S_T6_NEU_STATE    4
-#define M_T6_NEU_STATE    0xfU
-#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
-#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
-
-#define S_T6_CTRL_STATE    0
-#define M_T6_CTRL_STATE    0xfU
-#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
-#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
-
 #define A_MAC_PORT_AET_STATUS_23 0x2b74
 #define A_MAC_PORT_AET_LIMITS3 0x2b78
 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00
@@ -52384,103 +64938,21 @@
 #define F_BSOUTP    V_BSOUTP(1U)
 
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
-
-#define S_T6_T5_TX_RXLOOP    5
-#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
-#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
-
-#define S_T6_T5_TX_BWSEL    2
-#define M_T6_T5_TX_BWSEL    0x3U
-#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
-#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
-
-#define S_T6_ERROR    9
-#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
-#define F_T6_ERROR    V_T6_ERROR(1U)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
-
-#define S_T6_CALSSTN    8
-#define M_T6_CALSSTN    0x3fU
-#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
-#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
-
-#define S_T6_CALSSTP    0
-#define M_T6_CALSSTP    0x3fU
-#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
-#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
-
-#define S_T6_DRTOL    2
-#define M_T6_DRTOL    0x7U
-#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
-#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
-
-#define S_T6_NXTT0    0
-#define M_T6_NXTT0    0x3fU
-#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
-#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
-
-#define S_T6_NXTT2    0
-#define M_T6_NXTT2    0x3fU
-#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
-#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
-
-#define S_T6_NXTPOL    0
-#define M_T6_NXTPOL    0xfU
-#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
-#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
-
-#define S_T6_C0UPDT    6
-#define M_T6_C0UPDT    0x3U
-#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
-#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
-
-#define S_T6_C2UPDT    2
-#define M_T6_C2UPDT    0x3U
-#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
-#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
-
-#define S_T6_C1UPDT    0
-#define M_T6_C1UPDT    0x3U
-#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
-#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
-
-#define S_T6_C0STAT    6
-#define M_T6_C0STAT    0x3U
-#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
-#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
-
-#define S_T6_C2STAT    2
-#define M_T6_C2STAT    0x3U
-#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
-#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
-
-#define S_T6_C1STAT    0
-#define M_T6_C1STAT    0x3U
-#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
-#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
@@ -52503,12 +64975,6 @@
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
-
-#define S_T6_XADDR    1
-#define M_T6_XADDR    0x1fU
-#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
-#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
@@ -52521,21 +64987,6 @@
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
 
-#define S_T6_DCCTIMEEN    13
-#define M_T6_DCCTIMEEN    0x3U
-#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
-#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
-
-#define S_T6_DCCLOCK    11
-#define M_T6_DCCLOCK    0x3U
-#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
-#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
-
-#define S_T6_DCCOFFSET    8
-#define M_T6_DCCOFFSET    0x7U
-#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
-#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
-
 #define S_TX_LINKB_DCCSTEP_CTL    6
 #define M_TX_LINKB_DCCSTEP_CTL    0x3U
 #define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL)
@@ -52553,20 +65004,9 @@
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
-
-#define S_T6_SDOVRD    0
-#define M_T6_SDOVRD    0xffffU
-#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
-#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
-
-#define S_T6_SDOVRDEN    15
-#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
-#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
-
 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
 
 #define S_T5_RX_LINKEN    15
@@ -54442,56 +66882,15 @@
 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
-
-#define S_T6_TMSCAL    8
-#define M_T6_TMSCAL    0x3U
-#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
-#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
-
-#define S_T6_APADJ    7
-#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
-#define F_T6_APADJ    V_T6_APADJ(1U)
-
-#define S_T6_RSEL    6
-#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
-#define F_T6_RSEL    V_T6_RSEL(1U)
-
-#define S_T6_PHOFFS    0
-#define M_T6_PHOFFS    0x3fU
-#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
-#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
-
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
-
-#define S_T6_SPIFMT    8
-#define M_T6_SPIFMT    0xfU
-#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
-#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
-
 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
-
-#define S_T6_WRAPSEL    15
-#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
-#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
-
-#define S_T6_PEAK    9
-#define M_T6_PEAK    0x1fU
-#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
-#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
-
 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
-
-#define S_T6_T5VGAIN    0
-#define M_T6_T5VGAIN    0x7fU
-#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
-#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
-
 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
@@ -54515,12 +66914,6 @@
 #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
-
-#define S_T6_ODEC    0
-#define M_T6_ODEC    0xfU
-#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
-#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
-
 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
 
 #define S_RX_LINKB_ACCCMP_RIS    11
@@ -54550,20 +66943,6 @@
 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
-
-#define S_T6_EMMD    3
-#define M_T6_EMMD    0x3U
-#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
-#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
-
-#define S_T6_EMBRDY    2
-#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
-#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
-
-#define S_T6_EMBUMP    1
-#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
-#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
-
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
@@ -54611,103 +66990,21 @@
 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
-
-#define S_T6_T5_TX_RXLOOP    5
-#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
-#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
-
-#define S_T6_T5_TX_BWSEL    2
-#define M_T6_T5_TX_BWSEL    0x3U
-#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
-#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
-
-#define S_T6_ERROR    9
-#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
-#define F_T6_ERROR    V_T6_ERROR(1U)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
-
-#define S_T6_CALSSTN    8
-#define M_T6_CALSSTN    0x3fU
-#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
-#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
-
-#define S_T6_CALSSTP    0
-#define M_T6_CALSSTP    0x3fU
-#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
-#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
-
-#define S_T6_DRTOL    2
-#define M_T6_DRTOL    0x7U
-#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
-#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
-
-#define S_T6_NXTT0    0
-#define M_T6_NXTT0    0x3fU
-#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
-#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
-
-#define S_T6_NXTT2    0
-#define M_T6_NXTT2    0x3fU
-#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
-#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
-
-#define S_T6_NXTPOL    0
-#define M_T6_NXTPOL    0xfU
-#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
-#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
-
-#define S_T6_C0UPDT    6
-#define M_T6_C0UPDT    0x3U
-#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
-#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
-
-#define S_T6_C2UPDT    2
-#define M_T6_C2UPDT    0x3U
-#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
-#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
-
-#define S_T6_C1UPDT    0
-#define M_T6_C1UPDT    0x3U
-#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
-#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
-
-#define S_T6_C0STAT    6
-#define M_T6_C0STAT    0x3U
-#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
-#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
-
-#define S_T6_C2STAT    2
-#define M_T6_C2STAT    0x3U
-#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
-#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
-
-#define S_T6_C1STAT    0
-#define M_T6_C1STAT    0x3U
-#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
-#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
@@ -54730,12 +67027,6 @@
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
-
-#define S_T6_XADDR    1
-#define M_T6_XADDR    0x1fU
-#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
-#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
@@ -54748,21 +67039,6 @@
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
 
-#define S_T6_DCCTIMEEN    13
-#define M_T6_DCCTIMEEN    0x3U
-#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
-#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
-
-#define S_T6_DCCLOCK    11
-#define M_T6_DCCLOCK    0x3U
-#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
-#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
-
-#define S_T6_DCCOFFSET    8
-#define M_T6_DCCOFFSET    0x7U
-#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
-#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
-
 #define S_TX_LINKC_DCCSTEP_CTL    6
 #define M_TX_LINKC_DCCSTEP_CTL    0x3U
 #define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL)
@@ -54780,118 +67056,25 @@
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
-
-#define S_T6_SDOVRD    0
-#define M_T6_SDOVRD    0xffffU
-#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
-#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
-
-#define S_T6_SDOVRDEN    15
-#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
-#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
-
-#define S_T6_T5_TX_RXLOOP    5
-#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
-#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
-
-#define S_T6_T5_TX_BWSEL    2
-#define M_T6_T5_TX_BWSEL    0x3U
-#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
-#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
-
-#define S_T6_ERROR    9
-#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
-#define F_T6_ERROR    V_T6_ERROR(1U)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
-
-#define S_T6_CALSSTN    8
-#define M_T6_CALSSTN    0x3fU
-#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
-#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
-
-#define S_T6_CALSSTP    0
-#define M_T6_CALSSTP    0x3fU
-#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
-#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
-
-#define S_T6_DRTOL    2
-#define M_T6_DRTOL    0x7U
-#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
-#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
-
-#define S_T6_NXTT0    0
-#define M_T6_NXTT0    0x3fU
-#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
-#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
-
-#define S_T6_NXTT2    0
-#define M_T6_NXTT2    0x3fU
-#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
-#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
-
-#define S_T6_NXTPOL    0
-#define M_T6_NXTPOL    0xfU
-#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
-#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
-
-#define S_T6_C0UPDT    6
-#define M_T6_C0UPDT    0x3U
-#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
-#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
-
-#define S_T6_C2UPDT    2
-#define M_T6_C2UPDT    0x3U
-#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
-#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
-
-#define S_T6_C1UPDT    0
-#define M_T6_C1UPDT    0x3U
-#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
-#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
-
-#define S_T6_C0STAT    6
-#define M_T6_C0STAT    0x3U
-#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
-#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
-
-#define S_T6_C2STAT    2
-#define M_T6_C2STAT    0x3U
-#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
-#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
-
-#define S_T6_C1STAT    0
-#define M_T6_C1STAT    0x3U
-#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
-#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
@@ -54914,12 +67097,6 @@
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
-
-#define S_T6_XADDR    1
-#define M_T6_XADDR    0x1fU
-#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
-#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
@@ -54932,21 +67109,6 @@
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
 
-#define S_T6_DCCTIMEEN    13
-#define M_T6_DCCTIMEEN    0x3U
-#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
-#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
-
-#define S_T6_DCCLOCK    11
-#define M_T6_DCCLOCK    0x3U
-#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
-#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
-
-#define S_T6_DCCOFFSET    8
-#define M_T6_DCCOFFSET    0x7U
-#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
-#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
-
 #define S_TX_LINKD_DCCSTEP_CTL    6
 #define M_TX_LINKD_DCCSTEP_CTL    0x3U
 #define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL)
@@ -54964,74 +67126,22 @@
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
-
-#define S_T6_SDOVRD    0
-#define M_T6_SDOVRD    0xffffU
-#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
-#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
-
-#define S_T6_SDOVRDEN    15
-#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
-#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
-
 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
-
-#define S_T6_TMSCAL    8
-#define M_T6_TMSCAL    0x3U
-#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
-#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
-
-#define S_T6_APADJ    7
-#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
-#define F_T6_APADJ    V_T6_APADJ(1U)
-
-#define S_T6_RSEL    6
-#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
-#define F_T6_RSEL    V_T6_RSEL(1U)
-
-#define S_T6_PHOFFS    0
-#define M_T6_PHOFFS    0x3fU
-#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
-#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
-
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
-
-#define S_T6_SPIFMT    8
-#define M_T6_SPIFMT    0xfU
-#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
-#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
-
 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
-
-#define S_T6_WRAPSEL    15
-#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
-#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
-
-#define S_T6_PEAK    9
-#define M_T6_PEAK    0x1fU
-#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
-#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
-
 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
-
-#define S_T6_T5VGAIN    0
-#define M_T6_T5VGAIN    0x7fU
-#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
-#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
-
 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
@@ -55055,12 +67165,6 @@
 #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
-
-#define S_T6_ODEC    0
-#define M_T6_ODEC    0xfU
-#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
-#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
-
 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
 
 #define S_RX_LINKC_ACCCMP_RIS    11
@@ -55090,20 +67194,6 @@
 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
-
-#define S_T6_EMMD    3
-#define M_T6_EMMD    0x3U
-#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
-#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
-
-#define S_T6_EMBRDY    2
-#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
-#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
-
-#define S_T6_EMBUMP    1
-#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
-#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
-
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
@@ -55154,56 +67244,15 @@
 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
-
-#define S_T6_TMSCAL    8
-#define M_T6_TMSCAL    0x3U
-#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
-#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
-
-#define S_T6_APADJ    7
-#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
-#define F_T6_APADJ    V_T6_APADJ(1U)
-
-#define S_T6_RSEL    6
-#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
-#define F_T6_RSEL    V_T6_RSEL(1U)
-
-#define S_T6_PHOFFS    0
-#define M_T6_PHOFFS    0x3fU
-#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
-#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
-
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
-
-#define S_T6_SPIFMT    8
-#define M_T6_SPIFMT    0xfU
-#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
-#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
-
 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
-
-#define S_T6_WRAPSEL    15
-#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
-#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
-
-#define S_T6_PEAK    9
-#define M_T6_PEAK    0x1fU
-#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
-#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
-
 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
-
-#define S_T6_T5VGAIN    0
-#define M_T6_T5VGAIN    0x7fU
-#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
-#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
-
 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
@@ -55227,12 +67276,6 @@
 #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
-
-#define S_T6_ODEC    0
-#define M_T6_ODEC    0xfU
-#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
-#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
-
 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
 
 #define S_RX_LINKD_ACCCMP_RIS    11
@@ -55262,20 +67305,6 @@
 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
-
-#define S_T6_EMMD    3
-#define M_T6_EMMD    0x3U
-#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
-#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
-
-#define S_T6_EMBRDY    2
-#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
-#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
-
-#define S_T6_EMBUMP    1
-#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
-#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
-
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
@@ -55597,103 +67626,21 @@
 #define F_MACROTEST    V_MACROTEST(1U)
 
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
-
-#define S_T6_T5_TX_RXLOOP    5
-#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
-#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
-
-#define S_T6_T5_TX_BWSEL    2
-#define M_T6_T5_TX_BWSEL    0x3U
-#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
-#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
-
-#define S_T6_ERROR    9
-#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
-#define F_T6_ERROR    V_T6_ERROR(1U)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
-
-#define S_T6_CALSSTN    8
-#define M_T6_CALSSTN    0x3fU
-#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
-#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
-
-#define S_T6_CALSSTP    0
-#define M_T6_CALSSTP    0x3fU
-#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
-#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
-
-#define S_T6_DRTOL    2
-#define M_T6_DRTOL    0x7U
-#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
-#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
-
-#define S_T6_NXTT0    0
-#define M_T6_NXTT0    0x3fU
-#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
-#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
-
-#define S_T6_NXTT2    0
-#define M_T6_NXTT2    0x3fU
-#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
-#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
-
-#define S_T6_NXTPOL    0
-#define M_T6_NXTPOL    0xfU
-#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
-#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
-
-#define S_T6_C0UPDT    6
-#define M_T6_C0UPDT    0x3U
-#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
-#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
-
-#define S_T6_C2UPDT    2
-#define M_T6_C2UPDT    0x3U
-#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
-#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
-
-#define S_T6_C1UPDT    0
-#define M_T6_C1UPDT    0x3U
-#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
-#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
-
-#define S_T6_C0STAT    6
-#define M_T6_C0STAT    0x3U
-#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
-#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
-
-#define S_T6_C2STAT    2
-#define M_T6_C2STAT    0x3U
-#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
-#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
-
-#define S_T6_C1STAT    0
-#define M_T6_C1STAT    0x3U
-#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
-#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
@@ -55716,12 +67663,6 @@
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
-
-#define S_T6_XADDR    1
-#define M_T6_XADDR    0x1fU
-#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
-#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
@@ -55734,21 +67675,6 @@
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
 
-#define S_T6_DCCTIMEEN    13
-#define M_T6_DCCTIMEEN    0x3U
-#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
-#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
-
-#define S_T6_DCCLOCK    11
-#define M_T6_DCCLOCK    0x3U
-#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
-#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
-
-#define S_T6_DCCOFFSET    8
-#define M_T6_DCCOFFSET    0x7U
-#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
-#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
-
 #define S_TX_LINK_BCST_DCCSTEP_CTL    6
 #define M_TX_LINK_BCST_DCCSTEP_CTL    0x3U
 #define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL)
@@ -55766,74 +67692,22 @@
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
-
-#define S_T6_SDOVRD    0
-#define M_T6_SDOVRD    0xffffU
-#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
-#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
-
-#define S_T6_SDOVRDEN    15
-#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
-#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
-
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
-
-#define S_T6_TMSCAL    8
-#define M_T6_TMSCAL    0x3U
-#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
-#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
-
-#define S_T6_APADJ    7
-#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
-#define F_T6_APADJ    V_T6_APADJ(1U)
-
-#define S_T6_RSEL    6
-#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
-#define F_T6_RSEL    V_T6_RSEL(1U)
-
-#define S_T6_PHOFFS    0
-#define M_T6_PHOFFS    0x3fU
-#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
-#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
-
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
-
-#define S_T6_SPIFMT    8
-#define M_T6_SPIFMT    0xfU
-#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
-#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
-
 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
-
-#define S_T6_WRAPSEL    15
-#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
-#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
-
-#define S_T6_PEAK    9
-#define M_T6_PEAK    0x1fU
-#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
-#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
-
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
-
-#define S_T6_T5VGAIN    0
-#define M_T6_T5VGAIN    0x7fU
-#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
-#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
-
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
@@ -55857,12 +67731,6 @@
 #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
-
-#define S_T6_ODEC    0
-#define M_T6_ODEC    0xfU
-#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
-#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
-
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
 
 #define S_RX_LINK_BCST_ACCCMP_RIS    11
@@ -55892,20 +67760,6 @@
 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
-
-#define S_T6_EMMD    3
-#define M_T6_EMMD    0x3U
-#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
-#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
-
-#define S_T6_EMBRDY    2
-#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
-#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
-
-#define S_T6_EMBUMP    1
-#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
-#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
-
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
@@ -56304,17 +68158,6 @@
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
-
-#define S_T6_C0MAX    8
-#define M_T6_C0MAX    0x7fU
-#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
-#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
-
-#define S_T6_C0MIN    0
-#define M_T6_C0MIN    0x7fU
-#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
-#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
@@ -56323,17 +68166,6 @@
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
-
-#define S_T6_C2MAX    8
-#define M_T6_C2MAX    0x7fU
-#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
-#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
-
-#define S_T6_C2MIN    0
-#define M_T6_C2MIN    0x7fU
-#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
-#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
-
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
@@ -56349,17 +68181,6 @@
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
-
-#define S_T6_C0MAX    8
-#define M_T6_C0MAX    0x7fU
-#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
-#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
-
-#define S_T6_C0MIN    0
-#define M_T6_C0MIN    0x7fU
-#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
-#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
@@ -56368,17 +68189,6 @@
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
-
-#define S_T6_C2MAX    8
-#define M_T6_C2MAX    0x7fU
-#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
-#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
-
-#define S_T6_C2MIN    0
-#define M_T6_C2MIN    0x7fU
-#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
-#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
-
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
@@ -56394,17 +68204,6 @@
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
-
-#define S_T6_C0MAX    8
-#define M_T6_C0MAX    0x7fU
-#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
-#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
-
-#define S_T6_C0MIN    0
-#define M_T6_C0MIN    0x7fU
-#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
-#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
@@ -56413,17 +68212,6 @@
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
-
-#define S_T6_C2MAX    8
-#define M_T6_C2MAX    0x7fU
-#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
-#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
-
-#define S_T6_C2MIN    0
-#define M_T6_C2MIN    0x7fU
-#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
-#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
-
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
@@ -56439,17 +68227,6 @@
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
-
-#define S_T6_C0MAX    8
-#define M_T6_C0MAX    0x7fU
-#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
-#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
-
-#define S_T6_C0MIN    0
-#define M_T6_C0MIN    0x7fU
-#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
-#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
@@ -56458,17 +68235,6 @@
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
-
-#define S_T6_C2MAX    8
-#define M_T6_C2MAX    0x7fU
-#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
-#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
-
-#define S_T6_C2MIN    0
-#define M_T6_C2MIN    0x7fU
-#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
-#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
-
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
@@ -56639,17 +68405,6 @@
 #define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN)
 
 #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
-
-#define S_T6_H1OSN    13
-#define M_T6_H1OSN    0x7U
-#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
-#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
-
-#define S_T6_H1OMAG    8
-#define M_T6_H1OMAG    0x1fU
-#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
-#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
-
 #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
 #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
@@ -56668,17 +68423,6 @@
 #define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN)
 
 #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
-
-#define S_T6_H1OSN    13
-#define M_T6_H1OSN    0x7U
-#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
-#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
-
-#define S_T6_H1OMAG    8
-#define M_T6_H1OMAG    0x1fU
-#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
-#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
-
 #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
 #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
@@ -56697,17 +68441,6 @@
 #define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN)
 
 #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
-
-#define S_T6_H1OSN    13
-#define M_T6_H1OSN    0x7U
-#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
-#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
-
-#define S_T6_H1OMAG    8
-#define M_T6_H1OMAG    0x1fU
-#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
-#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
-
 #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
 #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
@@ -56726,17 +68459,6 @@
 #define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN)
 
 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
-
-#define S_T6_H1OSN    13
-#define M_T6_H1OSN    0x7U
-#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
-#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
-
-#define S_T6_H1OMAG    8
-#define M_T6_H1OMAG    0x1fU
-#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
-#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
-
 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
@@ -57294,69 +69016,21 @@
 #define G_BANK(x) (((x) >> S_BANK) & M_BANK)
 
 #define A_MC_LMC_INITSEQ1 0x40148
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD1 0x4014c
 #define A_MC_LMC_INITSEQ2 0x40150
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD2 0x40154
 #define A_MC_LMC_INITSEQ3 0x40158
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD3 0x4015c
 #define A_MC_LMC_INITSEQ4 0x40160
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD4 0x40164
 #define A_MC_LMC_INITSEQ5 0x40168
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD5 0x4016c
 #define A_MC_LMC_INITSEQ6 0x40170
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD6 0x40174
 #define A_MC_LMC_INITSEQ7 0x40178
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD7 0x4017c
 #define A_MC_UPCTL_ECCCFG 0x40180
 #define A_MC_LMC_INITSEQ8 0x40180
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_UPCTL_ECCTST 0x40184
 
 #define S_ECC_TEST_MASK0    0
@@ -57367,61 +69041,19 @@
 #define A_MC_LMC_CMD8 0x40184
 #define A_MC_UPCTL_ECCCLR 0x40188
 #define A_MC_LMC_INITSEQ9 0x40188
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_UPCTL_ECCLOG 0x4018c
 #define A_MC_LMC_CMD9 0x4018c
 #define A_MC_LMC_INITSEQ10 0x40190
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD10 0x40194
 #define A_MC_LMC_INITSEQ11 0x40198
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD11 0x4019c
 #define A_MC_LMC_INITSEQ12 0x401a0
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD12 0x401a4
 #define A_MC_LMC_INITSEQ13 0x401a8
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD13 0x401ac
 #define A_MC_LMC_INITSEQ14 0x401b0
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD14 0x401b4
 #define A_MC_LMC_INITSEQ15 0x401b8
-
-#define S_T6_RANK    0
-#define M_T6_RANK    0xfU
-#define V_T6_RANK(x) ((x) << S_T6_RANK)
-#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
-
 #define A_MC_LMC_CMD15 0x401bc
 #define A_MC_UPCTL_DTUWACTL 0x40200
 
@@ -61990,6 +73622,11 @@
 #define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES)
 #define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES)
 
+#define S_DRAMREFENABLE    27
+#define M_DRAMREFENABLE    0x3U
+#define V_DRAMREFENABLE(x) ((x) << S_DRAMREFENABLE)
+#define G_DRAMREFENABLE(x) (((x) >> S_DRAMREFENABLE) & M_DRAMREFENABLE)
+
 #define A_EDC_H_DBG_MA_CMD_INTF 0x50300
 
 #define S_MCMDADDR    12
@@ -62372,12 +74009,51 @@
 #define V_REFCNT(x) ((x) << S_REFCNT)
 #define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT)
 
+#define A_EDC_H_PAR_CAUSE 0x50404
+
+#define S_STG_CMDQ_PARERR_CAUSE    7
+#define V_STG_CMDQ_PARERR_CAUSE(x) ((x) << S_STG_CMDQ_PARERR_CAUSE)
+#define F_STG_CMDQ_PARERR_CAUSE    V_STG_CMDQ_PARERR_CAUSE(1U)
+
+#define S_STG_WRDQ_PARERR_CAUSE    6
+#define V_STG_WRDQ_PARERR_CAUSE(x) ((x) << S_STG_WRDQ_PARERR_CAUSE)
+#define F_STG_WRDQ_PARERR_CAUSE    V_STG_WRDQ_PARERR_CAUSE(1U)
+
+#define S_INP_CMDQ_PARERR_CAUSE    5
+#define V_INP_CMDQ_PARERR_CAUSE(x) ((x) << S_INP_CMDQ_PARERR_CAUSE)
+#define F_INP_CMDQ_PARERR_CAUSE    V_INP_CMDQ_PARERR_CAUSE(1U)
+
+#define S_INP_WRDQ_PARERR_CAUSE    4
+#define V_INP_WRDQ_PARERR_CAUSE(x) ((x) << S_INP_WRDQ_PARERR_CAUSE)
+#define F_INP_WRDQ_PARERR_CAUSE    V_INP_WRDQ_PARERR_CAUSE(1U)
+
+#define S_INP_BEQ_PARERR_CAUSE    3
+#define V_INP_BEQ_PARERR_CAUSE(x) ((x) << S_INP_BEQ_PARERR_CAUSE)
+#define F_INP_BEQ_PARERR_CAUSE    V_INP_BEQ_PARERR_CAUSE(1U)
+
+#define S_ECC_CE_PAR_ENABLE_CAUSE    2
+#define V_ECC_CE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_CE_PAR_ENABLE_CAUSE)
+#define F_ECC_CE_PAR_ENABLE_CAUSE    V_ECC_CE_PAR_ENABLE_CAUSE(1U)
+
+#define S_ECC_UE_PAR_ENABLE_CAUSE    1
+#define V_ECC_UE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_UE_PAR_ENABLE_CAUSE)
+#define F_ECC_UE_PAR_ENABLE_CAUSE    V_ECC_UE_PAR_ENABLE_CAUSE(1U)
+
+#define S_RDDQ_PARERR_CAUSE    0
+#define V_RDDQ_PARERR_CAUSE(x) ((x) << S_RDDQ_PARERR_CAUSE)
+#define F_RDDQ_PARERR_CAUSE    V_RDDQ_PARERR_CAUSE(1U)
+
 /* registers for module EDC_T61 */
 #define EDC_T61_BASE_ADDR 0x50800
 
 /* registers for module HMA_T6 */
 #define HMA_T6_BASE_ADDR 0x51000
 
+#define S_T7_CLIENT_EN    0
+#define M_T7_CLIENT_EN    0x7fffU
+#define V_T7_CLIENT_EN(x) ((x) << S_T7_CLIENT_EN)
+#define G_T7_CLIENT_EN(x) (((x) >> S_T7_CLIENT_EN) & M_T7_CLIENT_EN)
+
 #define S_TPH    12
 #define M_TPH    0x3U
 #define V_TPH(x) ((x) << S_TPH)
@@ -62398,6 +74074,14 @@
 #define V_OP_MODE(x) ((x) << S_OP_MODE)
 #define F_OP_MODE    V_OP_MODE(1U)
 
+#define S_GK_ENABLE    30
+#define V_GK_ENABLE(x) ((x) << S_GK_ENABLE)
+#define F_GK_ENABLE    V_GK_ENABLE(1U)
+
+#define S_DBGCNTRST    29
+#define V_DBGCNTRST(x) ((x) << S_DBGCNTRST)
+#define F_DBGCNTRST    V_DBGCNTRST(1U)
+
 #define A_HMA_TLB_ACCESS 0x51028
 
 #define S_INV_ALL    29
@@ -62437,6 +74121,11 @@
 #define V_REGION(x) ((x) << S_REGION)
 #define G_REGION(x) (((x) >> S_REGION) & M_REGION)
 
+#define S_T7_VA    8
+#define M_T7_VA    0xffffffU
+#define V_T7_VA(x) ((x) << S_T7_VA)
+#define G_T7_VA(x) (((x) >> S_T7_VA) & M_T7_VA)
+
 #define A_HMA_TLB_DESC_0_H 0x51030
 #define A_HMA_TLB_DESC_0_L 0x51034
 #define A_HMA_TLB_DESC_1_H 0x51038
@@ -62460,6 +74149,11 @@
 #define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN)
 #define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN)
 
+#define S_REG0MINADDR0MIN    8
+#define M_REG0MINADDR0MIN    0xffffffU
+#define V_REG0MINADDR0MIN(x) ((x) << S_REG0MINADDR0MIN)
+#define G_REG0MINADDR0MIN(x) (((x) >> S_REG0MINADDR0MIN) & M_REG0MINADDR0MIN)
+
 #define A_HMA_REG0_MAX 0x51074
 
 #define S_ADDR0_MAX    12
@@ -62467,6 +74161,11 @@
 #define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX)
 #define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX)
 
+#define S_REG0MAXADDR0MAX    8
+#define M_REG0MAXADDR0MAX    0xffffffU
+#define V_REG0MAXADDR0MAX(x) ((x) << S_REG0MAXADDR0MAX)
+#define G_REG0MAXADDR0MAX(x) (((x) >> S_REG0MAXADDR0MAX) & M_REG0MAXADDR0MAX)
+
 #define A_HMA_REG0_MASK 0x51078
 
 #define S_PAGE_SIZE0    12
@@ -62475,6 +74174,7 @@
 #define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0)
 
 #define A_HMA_REG0_BASE 0x5107c
+#define A_HMA_REG0_BASE_LSB 0x5107c
 #define A_HMA_REG1_MIN 0x51080
 
 #define S_ADDR1_MIN    12
@@ -62482,6 +74182,11 @@
 #define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN)
 #define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN)
 
+#define S_REG1MINADDR1MIN    8
+#define M_REG1MINADDR1MIN    0xffffffU
+#define V_REG1MINADDR1MIN(x) ((x) << S_REG1MINADDR1MIN)
+#define G_REG1MINADDR1MIN(x) (((x) >> S_REG1MINADDR1MIN) & M_REG1MINADDR1MIN)
+
 #define A_HMA_REG1_MAX 0x51084
 
 #define S_ADDR1_MAX    12
@@ -62489,6 +74194,11 @@
 #define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX)
 #define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX)
 
+#define S_REG1MAXADDR1MAX    8
+#define M_REG1MAXADDR1MAX    0xffffffU
+#define V_REG1MAXADDR1MAX(x) ((x) << S_REG1MAXADDR1MAX)
+#define G_REG1MAXADDR1MAX(x) (((x) >> S_REG1MAXADDR1MAX) & M_REG1MAXADDR1MAX)
+
 #define A_HMA_REG1_MASK 0x51088
 
 #define S_PAGE_SIZE1    12
@@ -62497,6 +74207,7 @@
 #define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1)
 
 #define A_HMA_REG1_BASE 0x5108c
+#define A_HMA_REG1_BASE_LSB 0x5108c
 #define A_HMA_REG2_MIN 0x51090
 
 #define S_ADDR2_MIN    12
@@ -62504,6 +74215,11 @@
 #define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN)
 #define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN)
 
+#define S_REG2MINADDR2MIN    8
+#define M_REG2MINADDR2MIN    0xffffffU
+#define V_REG2MINADDR2MIN(x) ((x) << S_REG2MINADDR2MIN)
+#define G_REG2MINADDR2MIN(x) (((x) >> S_REG2MINADDR2MIN) & M_REG2MINADDR2MIN)
+
 #define A_HMA_REG2_MAX 0x51094
 
 #define S_ADDR2_MAX    12
@@ -62511,6 +74227,11 @@
 #define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX)
 #define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX)
 
+#define S_REG2MAXADDR2MAX    8
+#define M_REG2MAXADDR2MAX    0xffffffU
+#define V_REG2MAXADDR2MAX(x) ((x) << S_REG2MAXADDR2MAX)
+#define G_REG2MAXADDR2MAX(x) (((x) >> S_REG2MAXADDR2MAX) & M_REG2MAXADDR2MAX)
+
 #define A_HMA_REG2_MASK 0x51098
 
 #define S_PAGE_SIZE2    12
@@ -62519,6 +74240,7 @@
 #define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2)
 
 #define A_HMA_REG2_BASE 0x5109c
+#define A_HMA_REG2_BASE_LSB 0x5109c
 #define A_HMA_REG3_MIN 0x510a0
 
 #define S_ADDR3_MIN    12
@@ -62526,6 +74248,11 @@
 #define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN)
 #define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN)
 
+#define S_REG3MINADDR3MIN    8
+#define M_REG3MINADDR3MIN    0xffffffU
+#define V_REG3MINADDR3MIN(x) ((x) << S_REG3MINADDR3MIN)
+#define G_REG3MINADDR3MIN(x) (((x) >> S_REG3MINADDR3MIN) & M_REG3MINADDR3MIN)
+
 #define A_HMA_REG3_MAX 0x510a4
 
 #define S_ADDR3_MAX    12
@@ -62533,6 +74260,11 @@
 #define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX)
 #define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX)
 
+#define S_REG3MAXADDR3MAX    8
+#define M_REG3MAXADDR3MAX    0xffffffU
+#define V_REG3MAXADDR3MAX(x) ((x) << S_REG3MAXADDR3MAX)
+#define G_REG3MAXADDR3MAX(x) (((x) >> S_REG3MAXADDR3MAX) & M_REG3MAXADDR3MAX)
+
 #define A_HMA_REG3_MASK 0x510a8
 
 #define S_PAGE_SIZE3    12
@@ -62541,6 +74273,7 @@
 #define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3)
 
 #define A_HMA_REG3_BASE 0x510ac
+#define A_HMA_REG3_BASE_LSB 0x510ac
 #define A_HMA_SW_SYNC 0x510b0
 
 #define S_ENTER_SYNC    31
@@ -62551,6 +74284,84 @@
 #define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC)
 #define F_EXIT_SYNC    V_EXIT_SYNC(1U)
 
+#define A_HMA_GC_MODE_SEL 0x510b4
+
+#define S_MODE_SEL    8
+#define M_MODE_SEL    0x3U
+#define V_MODE_SEL(x) ((x) << S_MODE_SEL)
+#define G_MODE_SEL(x) (((x) >> S_MODE_SEL) & M_MODE_SEL)
+
+#define S_FLUSH_REQ    4
+#define V_FLUSH_REQ(x) ((x) << S_FLUSH_REQ)
+#define F_FLUSH_REQ    V_FLUSH_REQ(1U)
+
+#define S_CLEAR_REQ    0
+#define V_CLEAR_REQ(x) ((x) << S_CLEAR_REQ)
+#define F_CLEAR_REQ    V_CLEAR_REQ(1U)
+
+#define A_HMA_REG0_BASE_MSB 0x510b8
+
+#define S_BASE0_MSB    0
+#define M_BASE0_MSB    0xfU
+#define V_BASE0_MSB(x) ((x) << S_BASE0_MSB)
+#define G_BASE0_MSB(x) (((x) >> S_BASE0_MSB) & M_BASE0_MSB)
+
+#define A_HMA_REG1_BASE_MSB 0x510bc
+
+#define S_BASE1_MSB    0
+#define M_BASE1_MSB    0xfU
+#define V_BASE1_MSB(x) ((x) << S_BASE1_MSB)
+#define G_BASE1_MSB(x) (((x) >> S_BASE1_MSB) & M_BASE1_MSB)
+
+#define A_HMA_REG2_BASE_MSB 0x510c0
+
+#define S_BASE2_MSB    0
+#define M_BASE2_MSB    0xfU
+#define V_BASE2_MSB(x) ((x) << S_BASE2_MSB)
+#define G_BASE2_MSB(x) (((x) >> S_BASE2_MSB) & M_BASE2_MSB)
+
+#define A_HMA_REG3_BASE_MSB 0x510c4
+
+#define S_BASE3_MSB    0
+#define M_BASE3_MSB    0xfU
+#define V_BASE3_MSB(x) ((x) << S_BASE3_MSB)
+#define G_BASE3_MSB(x) (((x) >> S_BASE3_MSB) & M_BASE3_MSB)
+
+#define A_HMA_DBG_CTL 0x51104
+#define A_HMA_DBG_DATA 0x51108
+#define A_HMA_H_BIST_CMD 0x51200
+#define A_HMA_H_BIST_CMD_ADDR 0x51204
+#define A_HMA_H_BIST_CMD_LEN 0x51208
+#define A_HMA_H_BIST_DATA_PATTERN 0x5120c
+#define A_HMA_H_BIST_USER_WDATA0 0x51210
+#define A_HMA_H_BIST_USER_WDATA1 0x51214
+#define A_HMA_H_BIST_USER_WDATA2 0x51218
+#define A_HMA_H_BIST_NUM_ERR 0x5121c
+#define A_HMA_H_BIST_ERR_FIRST_ADDR 0x51220
+#define A_HMA_H_BIST_STATUS_RDATA 0x51224
+#define A_HMA_H_BIST_CRC_SEED 0x5126c
+#define A_HMA_TABLE_LINE1_MSB 0x51270
+
+#define S_STARTA    0
+#define M_STARTA    0xfU
+#define V_STARTA(x) ((x) << S_STARTA)
+#define G_STARTA(x) (((x) >> S_STARTA) & M_STARTA)
+
+#define A_HMA_TABLE_LINE2_MSB 0x51274
+
+#define S_ENDA    0
+#define M_ENDA    0xfU
+#define V_ENDA(x) ((x) << S_ENDA)
+#define G_ENDA(x) (((x) >> S_ENDA) & M_ENDA)
+
+#define S_GK_UF_PAR_ENABLE    6
+#define V_GK_UF_PAR_ENABLE(x) ((x) << S_GK_UF_PAR_ENABLE)
+#define F_GK_UF_PAR_ENABLE    V_GK_UF_PAR_ENABLE(1U)
+
+#define S_PCIEMST_PAR_ENABLE    2
+#define V_PCIEMST_PAR_ENABLE(x) ((x) << S_PCIEMST_PAR_ENABLE)
+#define F_PCIEMST_PAR_ENABLE    V_PCIEMST_PAR_ENABLE(1U)
+
 #define S_IDTF_INT_ENABLE    5
 #define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE)
 #define F_IDTF_INT_ENABLE    V_IDTF_INT_ENABLE(1U)
@@ -62571,6 +74382,10 @@
 #define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE)
 #define F_MAMST_INT_ENABLE    V_MAMST_INT_ENABLE(1U)
 
+#define S_GK_UF_INT_ENABLE    6
+#define V_GK_UF_INT_ENABLE(x) ((x) << S_GK_UF_INT_ENABLE)
+#define F_GK_UF_INT_ENABLE    V_GK_UF_INT_ENABLE(1U)
+
 #define S_IDTF_INT_CAUSE    5
 #define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE)
 #define F_IDTF_INT_CAUSE    V_IDTF_INT_CAUSE(1U)
@@ -62591,6 +74406,10 @@
 #define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE)
 #define F_MAMST_INT_CAUSE    V_MAMST_INT_CAUSE(1U)
 
+#define S_GK_UF_INT_CAUSE    6
+#define V_GK_UF_INT_CAUSE(x) ((x) << S_GK_UF_INT_CAUSE)
+#define F_GK_UF_INT_CAUSE    V_GK_UF_INT_CAUSE(1U)
+
 #define A_HMA_MA_MST_ERR 0x5130c
 #define A_HMA_RTF_ERR 0x51310
 #define A_HMA_OTF_ERR 0x51314
@@ -62904,3 +74723,12365 @@
 #define M_RD_EOP_CNT    0xffU
 #define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT)
 #define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT)
+
+#define S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT    16
+#define M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT    0xffU
+#define V_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT)
+#define G_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT)
+
+#define S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT    8
+#define M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT    0xffU
+#define V_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT)
+#define G_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT)
+
+#define S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT    0
+#define M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT    0xffU
+#define V_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT)
+#define G_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT)
+
+/* registers for module MAC_T7 */
+#define MAC_T7_BASE_ADDR 0x38000
+
+#define S_T7_PORT_MAP    21
+#define M_T7_PORT_MAP    0x7U
+#define V_T7_PORT_MAP(x) ((x) << S_T7_PORT_MAP)
+#define G_T7_PORT_MAP(x) (((x) >> S_T7_PORT_MAP) & M_T7_PORT_MAP)
+
+#define S_T7_SMUX_RX_LOOP    17
+#define M_T7_SMUX_RX_LOOP    0xfU
+#define V_T7_SMUX_RX_LOOP(x) ((x) << S_T7_SMUX_RX_LOOP)
+#define G_T7_SMUX_RX_LOOP(x) (((x) >> S_T7_SMUX_RX_LOOP) & M_T7_SMUX_RX_LOOP)
+
+#define S_T7_SIGNAL_DET    15
+#define V_T7_SIGNAL_DET(x) ((x) << S_T7_SIGNAL_DET)
+#define F_T7_SIGNAL_DET    V_T7_SIGNAL_DET(1U)
+
+#define S_CFG_MAC_2_MPS_FULL    13
+#define V_CFG_MAC_2_MPS_FULL(x) ((x) << S_CFG_MAC_2_MPS_FULL)
+#define F_CFG_MAC_2_MPS_FULL    V_CFG_MAC_2_MPS_FULL(1U)
+
+#define S_MPS_FULL_SEL    12
+#define V_MPS_FULL_SEL(x) ((x) << S_MPS_FULL_SEL)
+#define F_MPS_FULL_SEL    V_MPS_FULL_SEL(1U)
+
+#define S_T7_SMUXTXSEL    8
+#define M_T7_SMUXTXSEL    0xfU
+#define V_T7_SMUXTXSEL(x) ((x) << S_T7_SMUXTXSEL)
+#define G_T7_SMUXTXSEL(x) (((x) >> S_T7_SMUXTXSEL) & M_T7_SMUXTXSEL)
+
+#define S_T7_PORTSPEED    4
+#define M_T7_PORTSPEED    0xfU
+#define V_T7_PORTSPEED(x) ((x) << S_T7_PORTSPEED)
+#define G_T7_PORTSPEED(x) (((x) >> S_T7_PORTSPEED) & M_T7_PORTSPEED)
+
+#define S_MTIP_REG_RESET    25
+#define V_MTIP_REG_RESET(x) ((x) << S_MTIP_REG_RESET)
+#define F_MTIP_REG_RESET    V_MTIP_REG_RESET(1U)
+
+#define S_RESET_REG_CLK_I    24
+#define V_RESET_REG_CLK_I(x) ((x) << S_RESET_REG_CLK_I)
+#define F_RESET_REG_CLK_I    V_RESET_REG_CLK_I(1U)
+
+#define S_T7_LED1_CFG1    15
+#define M_T7_LED1_CFG1    0x7U
+#define V_T7_LED1_CFG1(x) ((x) << S_T7_LED1_CFG1)
+#define G_T7_LED1_CFG1(x) (((x) >> S_T7_LED1_CFG1) & M_T7_LED1_CFG1)
+
+#define S_T7_LED0_CFG1    12
+#define M_T7_LED0_CFG1    0x7U
+#define V_T7_LED0_CFG1(x) ((x) << S_T7_LED0_CFG1)
+#define G_T7_LED0_CFG1(x) (((x) >> S_T7_LED0_CFG1) & M_T7_LED0_CFG1)
+
+#define A_T7_MAC_PORT_MAGIC_MACID_LO 0x820
+#define A_T7_MAC_PORT_MAGIC_MACID_HI 0x824
+#define A_T7_MAC_PORT_LINK_STATUS 0x828
+
+#define S_EGR_SE_CNT_ERR    9
+#define V_EGR_SE_CNT_ERR(x) ((x) << S_EGR_SE_CNT_ERR)
+#define F_EGR_SE_CNT_ERR    V_EGR_SE_CNT_ERR(1U)
+
+#define S_INGR_SE_CNT_ERR    8
+#define V_INGR_SE_CNT_ERR(x) ((x) << S_INGR_SE_CNT_ERR)
+#define F_INGR_SE_CNT_ERR    V_INGR_SE_CNT_ERR(1U)
+
+#define A_T7_MAC_PORT_PERR_INT_EN_100G 0x82c
+
+#define S_PERR_PCSR_FDM_3    21
+#define V_PERR_PCSR_FDM_3(x) ((x) << S_PERR_PCSR_FDM_3)
+#define F_PERR_PCSR_FDM_3    V_PERR_PCSR_FDM_3(1U)
+
+#define S_PERR_PCSR_FDM_2    20
+#define V_PERR_PCSR_FDM_2(x) ((x) << S_PERR_PCSR_FDM_2)
+#define F_PERR_PCSR_FDM_2    V_PERR_PCSR_FDM_2(1U)
+
+#define S_PERR_PCSR_FDM_1    19
+#define V_PERR_PCSR_FDM_1(x) ((x) << S_PERR_PCSR_FDM_1)
+#define F_PERR_PCSR_FDM_1    V_PERR_PCSR_FDM_1(1U)
+
+#define S_PERR_PCSR_FDM_0    18
+#define V_PERR_PCSR_FDM_0(x) ((x) << S_PERR_PCSR_FDM_0)
+#define F_PERR_PCSR_FDM_0    V_PERR_PCSR_FDM_0(1U)
+
+#define S_PERR_PCSR_FM_3    17
+#define V_PERR_PCSR_FM_3(x) ((x) << S_PERR_PCSR_FM_3)
+#define F_PERR_PCSR_FM_3    V_PERR_PCSR_FM_3(1U)
+
+#define S_PERR_PCSR_FM_2    16
+#define V_PERR_PCSR_FM_2(x) ((x) << S_PERR_PCSR_FM_2)
+#define F_PERR_PCSR_FM_2    V_PERR_PCSR_FM_2(1U)
+
+#define S_PERR_PCSR_FM_1    15
+#define V_PERR_PCSR_FM_1(x) ((x) << S_PERR_PCSR_FM_1)
+#define F_PERR_PCSR_FM_1    V_PERR_PCSR_FM_1(1U)
+
+#define S_PERR_PCSR_FM_0    14
+#define V_PERR_PCSR_FM_0(x) ((x) << S_PERR_PCSR_FM_0)
+#define F_PERR_PCSR_FM_0    V_PERR_PCSR_FM_0(1U)
+
+#define S_PERR_PCSR_DM_1    13
+#define V_PERR_PCSR_DM_1(x) ((x) << S_PERR_PCSR_DM_1)
+#define F_PERR_PCSR_DM_1    V_PERR_PCSR_DM_1(1U)
+
+#define S_PERR_PCSR_DM_0    12
+#define V_PERR_PCSR_DM_0(x) ((x) << S_PERR_PCSR_DM_0)
+#define F_PERR_PCSR_DM_0    V_PERR_PCSR_DM_0(1U)
+
+#define S_PERR_PCSR_DK_3    11
+#define V_PERR_PCSR_DK_3(x) ((x) << S_PERR_PCSR_DK_3)
+#define F_PERR_PCSR_DK_3    V_PERR_PCSR_DK_3(1U)
+
+#define S_PERR_PCSR_DK_2    10
+#define V_PERR_PCSR_DK_2(x) ((x) << S_PERR_PCSR_DK_2)
+#define F_PERR_PCSR_DK_2    V_PERR_PCSR_DK_2(1U)
+
+#define S_PERR_PCSR_DK_1    9
+#define V_PERR_PCSR_DK_1(x) ((x) << S_PERR_PCSR_DK_1)
+#define F_PERR_PCSR_DK_1    V_PERR_PCSR_DK_1(1U)
+
+#define S_PERR_PCSR_DK_0    8
+#define V_PERR_PCSR_DK_0(x) ((x) << S_PERR_PCSR_DK_0)
+#define F_PERR_PCSR_DK_0    V_PERR_PCSR_DK_0(1U)
+
+#define S_PERR_F91RO_1    7
+#define V_PERR_F91RO_1(x) ((x) << S_PERR_F91RO_1)
+#define F_PERR_F91RO_1    V_PERR_F91RO_1(1U)
+
+#define S_PERR_F91RO_0    6
+#define V_PERR_F91RO_0(x) ((x) << S_PERR_F91RO_0)
+#define F_PERR_F91RO_0    V_PERR_F91RO_0(1U)
+
+#define S_PERR_PCSR_F91DM    5
+#define V_PERR_PCSR_F91DM(x) ((x) << S_PERR_PCSR_F91DM)
+#define F_PERR_PCSR_F91DM    V_PERR_PCSR_F91DM(1U)
+
+#define S_PERR_PCSR_F91TI    4
+#define V_PERR_PCSR_F91TI(x) ((x) << S_PERR_PCSR_F91TI)
+#define F_PERR_PCSR_F91TI    V_PERR_PCSR_F91TI(1U)
+
+#define S_PERR_PCSR_F91TO    3
+#define V_PERR_PCSR_F91TO(x) ((x) << S_PERR_PCSR_F91TO)
+#define F_PERR_PCSR_F91TO    V_PERR_PCSR_F91TO(1U)
+
+#define S_PERR_PCSR_F91M    2
+#define V_PERR_PCSR_F91M(x) ((x) << S_PERR_PCSR_F91M)
+#define F_PERR_PCSR_F91M    V_PERR_PCSR_F91M(1U)
+
+#define S_PERR_PCSR_80_16_1    1
+#define V_PERR_PCSR_80_16_1(x) ((x) << S_PERR_PCSR_80_16_1)
+#define F_PERR_PCSR_80_16_1    V_PERR_PCSR_80_16_1(1U)
+
+#define S_PERR_PCSR_80_16_0    0
+#define V_PERR_PCSR_80_16_0(x) ((x) << S_PERR_PCSR_80_16_0)
+#define F_PERR_PCSR_80_16_0    V_PERR_PCSR_80_16_0(1U)
+
+#define A_T7_MAC_PORT_PERR_INT_CAUSE_100G 0x830
+#define A_T7_MAC_PORT_PERR_ENABLE_100G 0x834
+#define A_MAC_PORT_MAC10G100G_CONFIG_0 0x838
+
+#define S_PEER_DELAY_VAL    31
+#define V_PEER_DELAY_VAL(x) ((x) << S_PEER_DELAY_VAL)
+#define F_PEER_DELAY_VAL    V_PEER_DELAY_VAL(1U)
+
+#define S_PEER_DELAY    1
+#define M_PEER_DELAY    0x3fffffffU
+#define V_PEER_DELAY(x) ((x) << S_PEER_DELAY)
+#define G_PEER_DELAY(x) (((x) >> S_PEER_DELAY) & M_PEER_DELAY)
+
+#define S_MODE1S_ENA    0
+#define V_MODE1S_ENA(x) ((x) << S_MODE1S_ENA)
+#define F_MODE1S_ENA    V_MODE1S_ENA(1U)
+
+#define A_MAC_PORT_MAC10G100G_CONFIG_1 0x83c
+
+#define S_TX_STOP    25
+#define V_TX_STOP(x) ((x) << S_TX_STOP)
+#define F_TX_STOP    V_TX_STOP(1U)
+
+#define S_T7_MODE1S_ENA    24
+#define V_T7_MODE1S_ENA(x) ((x) << S_T7_MODE1S_ENA)
+#define F_T7_MODE1S_ENA    V_T7_MODE1S_ENA(1U)
+
+#define S_TX_TS_ID    12
+#define M_TX_TS_ID    0xfffU
+#define V_TX_TS_ID(x) ((x) << S_TX_TS_ID)
+#define G_TX_TS_ID(x) (((x) >> S_TX_TS_ID) & M_TX_TS_ID)
+
+#define S_T7_TX_LI_FAULT    11
+#define V_T7_TX_LI_FAULT(x) ((x) << S_T7_TX_LI_FAULT)
+#define F_T7_TX_LI_FAULT    V_T7_TX_LI_FAULT(1U)
+
+#define S_XOFF_GEN    3
+#define M_XOFF_GEN    0xffU
+#define V_XOFF_GEN(x) ((x) << S_XOFF_GEN)
+#define G_XOFF_GEN(x) (((x) >> S_XOFF_GEN) & M_XOFF_GEN)
+
+#define S_TX_REM_FAULT    1
+#define V_TX_REM_FAULT(x) ((x) << S_TX_REM_FAULT)
+#define F_TX_REM_FAULT    V_TX_REM_FAULT(1U)
+
+#define S_TX_LOC_FAULT    0
+#define V_TX_LOC_FAULT(x) ((x) << S_TX_LOC_FAULT)
+#define F_TX_LOC_FAULT    V_TX_LOC_FAULT(1U)
+
+#define A_MAC_PORT_MAC10G100G_CONFIG_2 0x840
+
+#define S_FF_TX_RX_TS_NS    0
+#define M_FF_TX_RX_TS_NS    0x3fffffffU
+#define V_FF_TX_RX_TS_NS(x) ((x) << S_FF_TX_RX_TS_NS)
+#define G_FF_TX_RX_TS_NS(x) (((x) >> S_FF_TX_RX_TS_NS) & M_FF_TX_RX_TS_NS)
+
+#define A_MAC_PORT_MAC10G100G_STATUS 0x844
+
+#define S_REG_LOWP    21
+#define V_REG_LOWP(x) ((x) << S_REG_LOWP)
+#define F_REG_LOWP    V_REG_LOWP(1U)
+
+#define S_LI_FAULT    20
+#define V_LI_FAULT(x) ((x) << S_LI_FAULT)
+#define F_LI_FAULT    V_LI_FAULT(1U)
+
+#define S_TX_ISIDLE    19
+#define V_TX_ISIDLE(x) ((x) << S_TX_ISIDLE)
+#define F_TX_ISIDLE    V_TX_ISIDLE(1U)
+
+#define S_TX_UNDERFLOW    18
+#define V_TX_UNDERFLOW(x) ((x) << S_TX_UNDERFLOW)
+#define F_TX_UNDERFLOW    V_TX_UNDERFLOW(1U)
+
+#define S_T7_TX_EMPTY    17
+#define V_T7_TX_EMPTY(x) ((x) << S_T7_TX_EMPTY)
+#define F_T7_TX_EMPTY    V_T7_TX_EMPTY(1U)
+
+#define S_T7_1_REM_FAULT    16
+#define V_T7_1_REM_FAULT(x) ((x) << S_T7_1_REM_FAULT)
+#define F_T7_1_REM_FAULT    V_T7_1_REM_FAULT(1U)
+
+#define S_REG_TS_AVAIL    15
+#define V_REG_TS_AVAIL(x) ((x) << S_REG_TS_AVAIL)
+#define F_REG_TS_AVAIL    V_REG_TS_AVAIL(1U)
+
+#define S_T7_PHY_TXENA    14
+#define V_T7_PHY_TXENA(x) ((x) << S_T7_PHY_TXENA)
+#define F_T7_PHY_TXENA    V_T7_PHY_TXENA(1U)
+
+#define S_T7_PFC_MODE    13
+#define V_T7_PFC_MODE(x) ((x) << S_T7_PFC_MODE)
+#define F_T7_PFC_MODE    V_T7_PFC_MODE(1U)
+
+#define S_PAUSE_ON    5
+#define M_PAUSE_ON    0xffU
+#define V_PAUSE_ON(x) ((x) << S_PAUSE_ON)
+#define G_PAUSE_ON(x) (((x) >> S_PAUSE_ON) & M_PAUSE_ON)
+
+#define S_MAC_PAUSE_EN    4
+#define V_MAC_PAUSE_EN(x) ((x) << S_MAC_PAUSE_EN)
+#define F_MAC_PAUSE_EN    V_MAC_PAUSE_EN(1U)
+
+#define S_MAC_ENABLE    3
+#define V_MAC_ENABLE(x) ((x) << S_MAC_ENABLE)
+#define F_MAC_ENABLE    V_MAC_ENABLE(1U)
+
+#define S_LOOP_ENA    2
+#define V_LOOP_ENA(x) ((x) << S_LOOP_ENA)
+#define F_LOOP_ENA    V_LOOP_ENA(1U)
+
+#define S_LOC_FAULT    1
+#define V_LOC_FAULT(x) ((x) << S_LOC_FAULT)
+#define F_LOC_FAULT    V_LOC_FAULT(1U)
+
+#define S_FF_RX_EMPTY    0
+#define V_FF_RX_EMPTY(x) ((x) << S_FF_RX_EMPTY)
+#define F_FF_RX_EMPTY    V_FF_RX_EMPTY(1U)
+
+#define A_MAC_PORT_MAC_AN_STATE_STATUS0 0x848
+
+#define S_AN_VAL_AN    15
+#define V_AN_VAL_AN(x) ((x) << S_AN_VAL_AN)
+#define F_AN_VAL_AN    V_AN_VAL_AN(1U)
+
+#define S_AN_TR_DIS_STATUS_AN    14
+#define V_AN_TR_DIS_STATUS_AN(x) ((x) << S_AN_TR_DIS_STATUS_AN)
+#define F_AN_TR_DIS_STATUS_AN    V_AN_TR_DIS_STATUS_AN(1U)
+
+#define S_AN_STATUS_AN    13
+#define V_AN_STATUS_AN(x) ((x) << S_AN_STATUS_AN)
+#define F_AN_STATUS_AN    V_AN_STATUS_AN(1U)
+
+#define S_AN_SELECT_AN    8
+#define M_AN_SELECT_AN    0x1fU
+#define V_AN_SELECT_AN(x) ((x) << S_AN_SELECT_AN)
+#define G_AN_SELECT_AN(x) (((x) >> S_AN_SELECT_AN) & M_AN_SELECT_AN)
+
+#define S_AN_RS_FEC_ENA_AN    7
+#define V_AN_RS_FEC_ENA_AN(x) ((x) << S_AN_RS_FEC_ENA_AN)
+#define F_AN_RS_FEC_ENA_AN    V_AN_RS_FEC_ENA_AN(1U)
+
+#define S_AN_INT_AN    6
+#define V_AN_INT_AN(x) ((x) << S_AN_INT_AN)
+#define F_AN_INT_AN    V_AN_INT_AN(1U)
+
+#define S_AN_FEC_ENA_AN    5
+#define V_AN_FEC_ENA_AN(x) ((x) << S_AN_FEC_ENA_AN)
+#define F_AN_FEC_ENA_AN    V_AN_FEC_ENA_AN(1U)
+
+#define S_AN_DONE_AN    4
+#define V_AN_DONE_AN(x) ((x) << S_AN_DONE_AN)
+#define F_AN_DONE_AN    V_AN_DONE_AN(1U)
+
+#define S_AN_STATE    0
+#define M_AN_STATE    0xfU
+#define V_AN_STATE(x) ((x) << S_AN_STATE)
+#define G_AN_STATE(x) (((x) >> S_AN_STATE) & M_AN_STATE)
+
+#define A_MAC_PORT_MAC_AN_STATE_STATUS1 0x84c
+#define A_T7_MAC_PORT_EPIO_DATA0 0x850
+#define A_T7_MAC_PORT_EPIO_DATA1 0x854
+#define A_T7_MAC_PORT_EPIO_DATA2 0x858
+#define A_T7_MAC_PORT_EPIO_DATA3 0x85c
+#define A_T7_MAC_PORT_EPIO_OP 0x860
+#define A_T7_MAC_PORT_WOL_STATUS 0x864
+#define A_T7_MAC_PORT_INT_EN 0x868
+
+#define S_MAC2MPS_PERR    31
+#define V_MAC2MPS_PERR(x) ((x) << S_MAC2MPS_PERR)
+#define F_MAC2MPS_PERR    V_MAC2MPS_PERR(1U)
+
+#define S_MAC_PPS_INT_EN    30
+#define V_MAC_PPS_INT_EN(x) ((x) << S_MAC_PPS_INT_EN)
+#define F_MAC_PPS_INT_EN    V_MAC_PPS_INT_EN(1U)
+
+#define S_MAC_TX_TS_AVAIL_INT_EN    29
+#define V_MAC_TX_TS_AVAIL_INT_EN(x) ((x) << S_MAC_TX_TS_AVAIL_INT_EN)
+#define F_MAC_TX_TS_AVAIL_INT_EN    V_MAC_TX_TS_AVAIL_INT_EN(1U)
+
+#define S_MAC_SINGLE_ALARM_INT_EN    28
+#define V_MAC_SINGLE_ALARM_INT_EN(x) ((x) << S_MAC_SINGLE_ALARM_INT_EN)
+#define F_MAC_SINGLE_ALARM_INT_EN    V_MAC_SINGLE_ALARM_INT_EN(1U)
+
+#define S_MAC_PERIODIC_ALARM_INT_EN    27
+#define V_MAC_PERIODIC_ALARM_INT_EN(x) ((x) << S_MAC_PERIODIC_ALARM_INT_EN)
+#define F_MAC_PERIODIC_ALARM_INT_EN    V_MAC_PERIODIC_ALARM_INT_EN(1U)
+
+#define S_MAC_PATDETWAKE_INT_EN    26
+#define V_MAC_PATDETWAKE_INT_EN(x) ((x) << S_MAC_PATDETWAKE_INT_EN)
+#define F_MAC_PATDETWAKE_INT_EN    V_MAC_PATDETWAKE_INT_EN(1U)
+
+#define S_MAC_MAGIC_WAKE_INT_EN    25
+#define V_MAC_MAGIC_WAKE_INT_EN(x) ((x) << S_MAC_MAGIC_WAKE_INT_EN)
+#define F_MAC_MAGIC_WAKE_INT_EN    V_MAC_MAGIC_WAKE_INT_EN(1U)
+
+#define S_MAC_SIGDETCHG_INT_EN    24
+#define V_MAC_SIGDETCHG_INT_EN(x) ((x) << S_MAC_SIGDETCHG_INT_EN)
+#define F_MAC_SIGDETCHG_INT_EN    V_MAC_SIGDETCHG_INT_EN(1U)
+
+#define S_MAC_PCS_LINK_GOOD_EN    12
+#define V_MAC_PCS_LINK_GOOD_EN(x) ((x) << S_MAC_PCS_LINK_GOOD_EN)
+#define F_MAC_PCS_LINK_GOOD_EN    V_MAC_PCS_LINK_GOOD_EN(1U)
+
+#define S_MAC_PCS_LINK_FAIL_EN    11
+#define V_MAC_PCS_LINK_FAIL_EN(x) ((x) << S_MAC_PCS_LINK_FAIL_EN)
+#define F_MAC_PCS_LINK_FAIL_EN    V_MAC_PCS_LINK_FAIL_EN(1U)
+
+#define S_MAC_OVRFLOW_INT_EN    10
+#define V_MAC_OVRFLOW_INT_EN(x) ((x) << S_MAC_OVRFLOW_INT_EN)
+#define F_MAC_OVRFLOW_INT_EN    V_MAC_OVRFLOW_INT_EN(1U)
+
+#define S_MAC_REM_FAULT_INT_EN    7
+#define V_MAC_REM_FAULT_INT_EN(x) ((x) << S_MAC_REM_FAULT_INT_EN)
+#define F_MAC_REM_FAULT_INT_EN    V_MAC_REM_FAULT_INT_EN(1U)
+
+#define S_MAC_LOC_FAULT_INT_EN    6
+#define V_MAC_LOC_FAULT_INT_EN(x) ((x) << S_MAC_LOC_FAULT_INT_EN)
+#define F_MAC_LOC_FAULT_INT_EN    V_MAC_LOC_FAULT_INT_EN(1U)
+
+#define S_MAC_LINK_DOWN_INT_EN    5
+#define V_MAC_LINK_DOWN_INT_EN(x) ((x) << S_MAC_LINK_DOWN_INT_EN)
+#define F_MAC_LINK_DOWN_INT_EN    V_MAC_LINK_DOWN_INT_EN(1U)
+
+#define S_MAC_LINK_UP_INT_EN    4
+#define V_MAC_LINK_UP_INT_EN(x) ((x) << S_MAC_LINK_UP_INT_EN)
+#define F_MAC_LINK_UP_INT_EN    V_MAC_LINK_UP_INT_EN(1U)
+
+#define S_MAC_AN_DONE_INT_EN    3
+#define V_MAC_AN_DONE_INT_EN(x) ((x) << S_MAC_AN_DONE_INT_EN)
+#define F_MAC_AN_DONE_INT_EN    V_MAC_AN_DONE_INT_EN(1U)
+
+#define S_MAC_AN_PGRD_INT_EN    2
+#define V_MAC_AN_PGRD_INT_EN(x) ((x) << S_MAC_AN_PGRD_INT_EN)
+#define F_MAC_AN_PGRD_INT_EN    V_MAC_AN_PGRD_INT_EN(1U)
+
+#define S_MAC_TXFIFO_ERR_INT_EN    1
+#define V_MAC_TXFIFO_ERR_INT_EN(x) ((x) << S_MAC_TXFIFO_ERR_INT_EN)
+#define F_MAC_TXFIFO_ERR_INT_EN    V_MAC_TXFIFO_ERR_INT_EN(1U)
+
+#define S_MAC_RXFIFO_ERR_INT_EN    0
+#define V_MAC_RXFIFO_ERR_INT_EN(x) ((x) << S_MAC_RXFIFO_ERR_INT_EN)
+#define F_MAC_RXFIFO_ERR_INT_EN    V_MAC_RXFIFO_ERR_INT_EN(1U)
+
+#define A_T7_MAC_PORT_INT_CAUSE 0x86c
+
+#define S_MAC2MPS_PERR_CAUSE    31
+#define V_MAC2MPS_PERR_CAUSE(x) ((x) << S_MAC2MPS_PERR_CAUSE)
+#define F_MAC2MPS_PERR_CAUSE    V_MAC2MPS_PERR_CAUSE(1U)
+
+#define S_MAC_PPS_INT_CAUSE    30
+#define V_MAC_PPS_INT_CAUSE(x) ((x) << S_MAC_PPS_INT_CAUSE)
+#define F_MAC_PPS_INT_CAUSE    V_MAC_PPS_INT_CAUSE(1U)
+
+#define S_MAC_TX_TS_AVAIL_INT_CAUSE    29
+#define V_MAC_TX_TS_AVAIL_INT_CAUSE(x) ((x) << S_MAC_TX_TS_AVAIL_INT_CAUSE)
+#define F_MAC_TX_TS_AVAIL_INT_CAUSE    V_MAC_TX_TS_AVAIL_INT_CAUSE(1U)
+
+#define S_MAC_SINGLE_ALARM_INT_CAUSE    28
+#define V_MAC_SINGLE_ALARM_INT_CAUSE(x) ((x) << S_MAC_SINGLE_ALARM_INT_CAUSE)
+#define F_MAC_SINGLE_ALARM_INT_CAUSE    V_MAC_SINGLE_ALARM_INT_CAUSE(1U)
+
+#define S_MAC_PERIODIC_ALARM_INT_CAUSE    27
+#define V_MAC_PERIODIC_ALARM_INT_CAUSE(x) ((x) << S_MAC_PERIODIC_ALARM_INT_CAUSE)
+#define F_MAC_PERIODIC_ALARM_INT_CAUSE    V_MAC_PERIODIC_ALARM_INT_CAUSE(1U)
+
+#define S_MAC_PATDETWAKE_INT_CAUSE    26
+#define V_MAC_PATDETWAKE_INT_CAUSE(x) ((x) << S_MAC_PATDETWAKE_INT_CAUSE)
+#define F_MAC_PATDETWAKE_INT_CAUSE    V_MAC_PATDETWAKE_INT_CAUSE(1U)
+
+#define S_MAC_MAGIC_WAKE_INT_CAUSE    25
+#define V_MAC_MAGIC_WAKE_INT_CAUSE(x) ((x) << S_MAC_MAGIC_WAKE_INT_CAUSE)
+#define F_MAC_MAGIC_WAKE_INT_CAUSE    V_MAC_MAGIC_WAKE_INT_CAUSE(1U)
+
+#define S_MAC_SIGDETCHG_INT_CAUSE    24
+#define V_MAC_SIGDETCHG_INT_CAUSE(x) ((x) << S_MAC_SIGDETCHG_INT_CAUSE)
+#define F_MAC_SIGDETCHG_INT_CAUSE    V_MAC_SIGDETCHG_INT_CAUSE(1U)
+
+#define S_MAC_PCS_LINK_GOOD_CAUSE    12
+#define V_MAC_PCS_LINK_GOOD_CAUSE(x) ((x) << S_MAC_PCS_LINK_GOOD_CAUSE)
+#define F_MAC_PCS_LINK_GOOD_CAUSE    V_MAC_PCS_LINK_GOOD_CAUSE(1U)
+
+#define S_MAC_PCS_LINK_FAIL_CAUSE    11
+#define V_MAC_PCS_LINK_FAIL_CAUSE(x) ((x) << S_MAC_PCS_LINK_FAIL_CAUSE)
+#define F_MAC_PCS_LINK_FAIL_CAUSE    V_MAC_PCS_LINK_FAIL_CAUSE(1U)
+
+#define S_MAC_OVRFLOW_INT_CAUSE    10
+#define V_MAC_OVRFLOW_INT_CAUSE(x) ((x) << S_MAC_OVRFLOW_INT_CAUSE)
+#define F_MAC_OVRFLOW_INT_CAUSE    V_MAC_OVRFLOW_INT_CAUSE(1U)
+
+#define S_MAC_REM_FAULT_INT_CAUSE    7
+#define V_MAC_REM_FAULT_INT_CAUSE(x) ((x) << S_MAC_REM_FAULT_INT_CAUSE)
+#define F_MAC_REM_FAULT_INT_CAUSE    V_MAC_REM_FAULT_INT_CAUSE(1U)
+
+#define S_MAC_LOC_FAULT_INT_CAUSE    6
+#define V_MAC_LOC_FAULT_INT_CAUSE(x) ((x) << S_MAC_LOC_FAULT_INT_CAUSE)
+#define F_MAC_LOC_FAULT_INT_CAUSE    V_MAC_LOC_FAULT_INT_CAUSE(1U)
+
+#define S_MAC_LINK_DOWN_INT_CAUSE    5
+#define V_MAC_LINK_DOWN_INT_CAUSE(x) ((x) << S_MAC_LINK_DOWN_INT_CAUSE)
+#define F_MAC_LINK_DOWN_INT_CAUSE    V_MAC_LINK_DOWN_INT_CAUSE(1U)
+
+#define S_MAC_LINK_UP_INT_CAUSE    4
+#define V_MAC_LINK_UP_INT_CAUSE(x) ((x) << S_MAC_LINK_UP_INT_CAUSE)
+#define F_MAC_LINK_UP_INT_CAUSE    V_MAC_LINK_UP_INT_CAUSE(1U)
+
+#define S_MAC_AN_DONE_INT_CAUSE    3
+#define V_MAC_AN_DONE_INT_CAUSE(x) ((x) << S_MAC_AN_DONE_INT_CAUSE)
+#define F_MAC_AN_DONE_INT_CAUSE    V_MAC_AN_DONE_INT_CAUSE(1U)
+
+#define S_MAC_AN_PGRD_INT_CAUSE    2
+#define V_MAC_AN_PGRD_INT_CAUSE(x) ((x) << S_MAC_AN_PGRD_INT_CAUSE)
+#define F_MAC_AN_PGRD_INT_CAUSE    V_MAC_AN_PGRD_INT_CAUSE(1U)
+
+#define S_MAC_TXFIFO_ERR_INT_CAUSE    1
+#define V_MAC_TXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_TXFIFO_ERR_INT_CAUSE)
+#define F_MAC_TXFIFO_ERR_INT_CAUSE    V_MAC_TXFIFO_ERR_INT_CAUSE(1U)
+
+#define S_MAC_RXFIFO_ERR_INT_CAUSE    0
+#define V_MAC_RXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_RXFIFO_ERR_INT_CAUSE)
+#define F_MAC_RXFIFO_ERR_INT_CAUSE    V_MAC_RXFIFO_ERR_INT_CAUSE(1U)
+
+#define A_T7_MAC_PORT_PERR_INT_EN 0x870
+#define A_T7_MAC_PORT_PERR_INT_CAUSE 0x874
+#define A_T7_MAC_PORT_PERR_ENABLE 0x878
+#define A_T7_MAC_PORT_PERR_INJECT 0x87c
+
+#define S_T7_MEMSEL_PERR    1
+#define M_T7_MEMSEL_PERR    0xffU
+#define V_T7_MEMSEL_PERR(x) ((x) << S_T7_MEMSEL_PERR)
+#define G_T7_MEMSEL_PERR(x) (((x) >> S_T7_MEMSEL_PERR) & M_T7_MEMSEL_PERR)
+
+#define A_T7_MAC_PORT_RUNT_FRAME 0x880
+#define A_T7_MAC_PORT_EEE_STATUS 0x884
+#define A_T7_MAC_PORT_TX_TS_ID 0x888
+
+#define S_TS_ID_MSB    3
+#define V_TS_ID_MSB(x) ((x) << S_TS_ID_MSB)
+#define F_TS_ID_MSB    V_TS_ID_MSB(1U)
+
+#define A_T7_MAC_PORT_TX_TS_VAL_LO 0x88c
+#define A_T7_MAC_PORT_TX_TS_VAL_HI 0x890
+#define A_T7_MAC_PORT_EEE_CTL 0x894
+#define A_T7_MAC_PORT_EEE_TX_CTL 0x898
+#define A_T7_MAC_PORT_EEE_RX_CTL 0x89c
+#define A_T7_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x8a0
+#define A_T7_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x8a4
+#define A_T7_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x8a8
+#define A_T7_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x8b8
+#define A_T7_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x8bc
+#define A_T7_MAC_PORT_EEE_RX_10G_WF_TIMER 0x8c0
+#define A_T7_MAC_PORT_EEE_WF_COUNT 0x8cc
+#define A_MAC_PORT_WOL_EN 0x8d0
+
+#define S_WOL_ENABLE    1
+#define V_WOL_ENABLE(x) ((x) << S_WOL_ENABLE)
+#define F_WOL_ENABLE    V_WOL_ENABLE(1U)
+
+#define S_WOL_INDICATOR    0
+#define V_WOL_INDICATOR(x) ((x) << S_WOL_INDICATOR)
+#define F_WOL_INDICATOR    V_WOL_INDICATOR(1U)
+
+#define A_MAC_PORT_INT_TRACE 0x8d4
+
+#define S_INTERRUPT    0
+#define M_INTERRUPT    0x7fffffffU
+#define V_INTERRUPT(x) ((x) << S_INTERRUPT)
+#define G_INTERRUPT(x) (((x) >> S_INTERRUPT) & M_INTERRUPT)
+
+#define A_MAC_PORT_TRACE_TS_LO 0x8d8
+#define A_MAC_PORT_TRACE_TS_HI 0x8dc
+#define A_MAC_PORT_MTIP_10G100G_REVISION 0x900
+
+#define S_VER_10G100G    8
+#define M_VER_10G100G    0xffU
+#define V_VER_10G100G(x) ((x) << S_VER_10G100G)
+#define G_VER_10G100G(x) (((x) >> S_VER_10G100G) & M_VER_10G100G)
+
+#define S_REV_10G100G    0
+#define M_REV_10G100G    0xffU
+#define V_REV_10G100G(x) ((x) << S_REV_10G100G)
+#define G_REV_10G100G(x) (((x) >> S_REV_10G100G) & M_REV_10G100G)
+
+#define A_MAC_PORT_MTIP_10G100G_SCRATCH 0x904
+#define A_MAC_PORT_MTIP_10G100G_COMMAND_CONFIG 0x908
+
+#define S_NO_PREAM    31
+#define V_NO_PREAM(x) ((x) << S_NO_PREAM)
+#define F_NO_PREAM    V_NO_PREAM(1U)
+
+#define S_SHORT_PREAM    30
+#define V_SHORT_PREAM(x) ((x) << S_SHORT_PREAM)
+#define F_SHORT_PREAM    V_SHORT_PREAM(1U)
+
+#define S_FLT_HDL_DIS    27
+#define V_FLT_HDL_DIS(x) ((x) << S_FLT_HDL_DIS)
+#define F_FLT_HDL_DIS    V_FLT_HDL_DIS(1U)
+
+#define S_TX_FIFO_RESET    26
+#define V_TX_FIFO_RESET(x) ((x) << S_TX_FIFO_RESET)
+#define F_TX_FIFO_RESET    V_TX_FIFO_RESET(1U)
+
+#define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_0 0x90c
+#define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_1 0x910
+#define A_MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU 0x914
+#define A_MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS 0x91c
+
+#define S_RX10G100G_EMPTY    16
+#define M_RX10G100G_EMPTY    0xffffU
+#define V_RX10G100G_EMPTY(x) ((x) << S_RX10G100G_EMPTY)
+#define G_RX10G100G_EMPTY(x) (((x) >> S_RX10G100G_EMPTY) & M_RX10G100G_EMPTY)
+
+#define S_RX10G100G_AVAIL    0
+#define M_RX10G100G_AVAIL    0xffffU
+#define V_RX10G100G_AVAIL(x) ((x) << S_RX10G100G_AVAIL)
+#define G_RX10G100G_AVAIL(x) (((x) >> S_RX10G100G_AVAIL) & M_RX10G100G_AVAIL)
+
+#define A_MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS 0x920
+
+#define S_TX10G100G_EMPTY    16
+#define M_TX10G100G_EMPTY    0xffffU
+#define V_TX10G100G_EMPTY(x) ((x) << S_TX10G100G_EMPTY)
+#define G_TX10G100G_EMPTY(x) (((x) >> S_TX10G100G_EMPTY) & M_TX10G100G_EMPTY)
+
+#define S_TX10G100G_AVAIL    0
+#define M_TX10G100G_AVAIL    0xffffU
+#define V_TX10G100G_AVAIL(x) ((x) << S_TX10G100G_AVAIL)
+#define G_TX10G100G_AVAIL(x) (((x) >> S_TX10G100G_AVAIL) & M_TX10G100G_AVAIL)
+
+#define A_MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E 0x924
+#define A_MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E 0x928
+#define A_MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS 0x930
+#define A_MAC_PORT_MTIP_10G100G_MDIO_COMMAND 0x934
+#define A_MAC_PORT_MTIP_10G100G_MDIO_DATA 0x938
+#define A_MAC_PORT_MTIP_10G100G_MDIO_REGADDR 0x93c
+#define A_MAC_PORT_MTIP_10G100G_STATUS 0x940
+
+#define S_T7_TX_ISIDLE    8
+#define V_T7_TX_ISIDLE(x) ((x) << S_T7_TX_ISIDLE)
+#define F_T7_TX_ISIDLE    V_T7_TX_ISIDLE(1U)
+
+#define A_MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH 0x944
+
+#define S_IPG_COMP_CNT    16
+#define M_IPG_COMP_CNT    0xffffU
+#define V_IPG_COMP_CNT(x) ((x) << S_IPG_COMP_CNT)
+#define G_IPG_COMP_CNT(x) (((x) >> S_IPG_COMP_CNT) & M_IPG_COMP_CNT)
+
+#define S_AVG_IPG_LEN    2
+#define M_AVG_IPG_LEN    0xfU
+#define V_AVG_IPG_LEN(x) ((x) << S_AVG_IPG_LEN)
+#define G_AVG_IPG_LEN(x) (((x) >> S_AVG_IPG_LEN) & M_AVG_IPG_LEN)
+
+#define S_DSBL_DIC    0
+#define V_DSBL_DIC(x) ((x) << S_DSBL_DIC)
+#define F_DSBL_DIC    V_DSBL_DIC(1U)
+
+#define A_MAC_PORT_MTIP_10G100G_CRC_MODE 0x948
+#define A_MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA 0x954
+#define A_MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA 0x958
+#define A_MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA 0x95c
+#define A_MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA 0x960
+#define A_MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH 0x964
+#define A_MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH 0x968
+#define A_MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH 0x96c
+#define A_MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH 0x970
+#define A_MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS 0x974
+#define A_MAC_PORT_MTIP_10G100G_TS_TIMESTAMP 0x97c
+#define A_MAC_PORT_MTIP_10G100G_XIF_MODE 0x980
+
+#define S_RX_CNT_MODE    16
+#define V_RX_CNT_MODE(x) ((x) << S_RX_CNT_MODE)
+#define F_RX_CNT_MODE    V_RX_CNT_MODE(1U)
+
+#define S_TS_UPD64_MODE    12
+#define V_TS_UPD64_MODE(x) ((x) << S_TS_UPD64_MODE)
+#define F_TS_UPD64_MODE    V_TS_UPD64_MODE(1U)
+
+#define S_TS_BINARY_MODE    11
+#define V_TS_BINARY_MODE(x) ((x) << S_TS_BINARY_MODE)
+#define F_TS_BINARY_MODE    V_TS_BINARY_MODE(1U)
+
+#define S_TS_DELAY_MODE    10
+#define V_TS_DELAY_MODE(x) ((x) << S_TS_DELAY_MODE)
+#define F_TS_DELAY_MODE    V_TS_DELAY_MODE(1U)
+
+#define S_TS_DELTA_MODE    9
+#define V_TS_DELTA_MODE(x) ((x) << S_TS_DELTA_MODE)
+#define F_TS_DELTA_MODE    V_TS_DELTA_MODE(1U)
+
+#define S_TX_MAC_RS_ERR    8
+#define V_TX_MAC_RS_ERR(x) ((x) << S_TX_MAC_RS_ERR)
+#define F_TX_MAC_RS_ERR    V_TX_MAC_RS_ERR(1U)
+
+#define S_RX_PAUSE_BYPASS    6
+#define V_RX_PAUSE_BYPASS(x) ((x) << S_RX_PAUSE_BYPASS)
+#define F_RX_PAUSE_BYPASS    V_RX_PAUSE_BYPASS(1U)
+
+#define S_ONE_STEP_ENA    5
+#define V_ONE_STEP_ENA(x) ((x) << S_ONE_STEP_ENA)
+#define F_ONE_STEP_ENA    V_ONE_STEP_ENA(1U)
+
+#define S_PAUSETIMERX8    4
+#define V_PAUSETIMERX8(x) ((x) << S_PAUSETIMERX8)
+#define F_PAUSETIMERX8    V_PAUSETIMERX8(1U)
+
+#define S_XGMII_ENA    0
+#define V_XGMII_ENA(x) ((x) << S_XGMII_ENA)
+#define F_XGMII_ENA    V_XGMII_ENA(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_CONTROL_1 0xa00
+#define A_MAC_PORT_MTIP_CR4_0_STATUS_1 0xa04
+
+#define S_CR4_0_RX_LINK_STATUS    2
+#define V_CR4_0_RX_LINK_STATUS(x) ((x) << S_CR4_0_RX_LINK_STATUS)
+#define F_CR4_0_RX_LINK_STATUS    V_CR4_0_RX_LINK_STATUS(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID0 0xa08
+
+#define S_CR4_0_DEVICE_ID0    0
+#define M_CR4_0_DEVICE_ID0    0xffffU
+#define V_CR4_0_DEVICE_ID0(x) ((x) << S_CR4_0_DEVICE_ID0)
+#define G_CR4_0_DEVICE_ID0(x) (((x) >> S_CR4_0_DEVICE_ID0) & M_CR4_0_DEVICE_ID0)
+
+#define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID1 0xa0c
+
+#define S_CR4_0_DEVICE_ID1    0
+#define M_CR4_0_DEVICE_ID1    0xffffU
+#define V_CR4_0_DEVICE_ID1(x) ((x) << S_CR4_0_DEVICE_ID1)
+#define G_CR4_0_DEVICE_ID1(x) (((x) >> S_CR4_0_DEVICE_ID1) & M_CR4_0_DEVICE_ID1)
+
+#define A_MAC_PORT_MTIP_CR4_0_SPEED_ABILITY 0xa10
+
+#define S_50G_CAPABLE    5
+#define V_50G_CAPABLE(x) ((x) << S_50G_CAPABLE)
+#define F_50G_CAPABLE    V_50G_CAPABLE(1U)
+
+#define S_25G_CAPABLE    4
+#define V_25G_CAPABLE(x) ((x) << S_25G_CAPABLE)
+#define F_25G_CAPABLE    V_25G_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1 0xa14
+#define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2 0xa18
+#define A_MAC_PORT_MTIP_CR4_0_CONTROL_2 0xa1c
+
+#define S_T7_PCS_TYPE_SELECTION    0
+#define M_T7_PCS_TYPE_SELECTION    0xfU
+#define V_T7_PCS_TYPE_SELECTION(x) ((x) << S_T7_PCS_TYPE_SELECTION)
+#define G_T7_PCS_TYPE_SELECTION(x) (((x) >> S_T7_PCS_TYPE_SELECTION) & M_T7_PCS_TYPE_SELECTION)
+
+#define A_MAC_PORT_MTIP_CR4_0_STATUS_2 0xa20
+
+#define S_50GBASE_R_CAPABLE    8
+#define V_50GBASE_R_CAPABLE(x) ((x) << S_50GBASE_R_CAPABLE)
+#define F_50GBASE_R_CAPABLE    V_50GBASE_R_CAPABLE(1U)
+
+#define S_25GBASE_R_CAPABLE    7
+#define V_25GBASE_R_CAPABLE(x) ((x) << S_25GBASE_R_CAPABLE)
+#define F_25GBASE_R_CAPABLE    V_25GBASE_R_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_PKG_ID0 0xa38
+#define A_MAC_PORT_MTIP_CR4_0_PKG_ID1 0xa3c
+#define A_MAC_PORT_MTIP_CR4_0_EEE_CTRL 0xa50
+
+#define S_50GBASE_R_FW    14
+#define V_50GBASE_R_FW(x) ((x) << S_50GBASE_R_FW)
+#define F_50GBASE_R_FW    V_50GBASE_R_FW(1U)
+
+#define S_100GBASE_R_DS    13
+#define V_100GBASE_R_DS(x) ((x) << S_100GBASE_R_DS)
+#define F_100GBASE_R_DS    V_100GBASE_R_DS(1U)
+
+#define S_100GBASE_R_FW    12
+#define V_100GBASE_R_FW(x) ((x) << S_100GBASE_R_FW)
+#define F_100GBASE_R_FW    V_100GBASE_R_FW(1U)
+
+#define S_25GBASE_R_DS    11
+#define V_25GBASE_R_DS(x) ((x) << S_25GBASE_R_DS)
+#define F_25GBASE_R_DS    V_25GBASE_R_DS(1U)
+
+#define S_25GBASE_R_FW    10
+#define V_25GBASE_R_FW(x) ((x) << S_25GBASE_R_FW)
+#define F_25GBASE_R_FW    V_25GBASE_R_FW(1U)
+
+#define S_40GBASE_R_DS    9
+#define V_40GBASE_R_DS(x) ((x) << S_40GBASE_R_DS)
+#define F_40GBASE_R_DS    V_40GBASE_R_DS(1U)
+
+#define S_40GBASE_R_FW    8
+#define V_40GBASE_R_FW(x) ((x) << S_40GBASE_R_FW)
+#define F_40GBASE_R_FW    V_40GBASE_R_FW(1U)
+
+#define S_10GBASE_KE_EEE    6
+#define V_10GBASE_KE_EEE(x) ((x) << S_10GBASE_KE_EEE)
+#define F_10GBASE_KE_EEE    V_10GBASE_KE_EEE(1U)
+
+#define S_FAST_WAKE    1
+#define M_FAST_WAKE    0x1fU
+#define V_FAST_WAKE(x) ((x) << S_FAST_WAKE)
+#define G_FAST_WAKE(x) (((x) >> S_FAST_WAKE) & M_FAST_WAKE)
+
+#define S_DEEP_SLEEP    0
+#define V_DEEP_SLEEP(x) ((x) << S_DEEP_SLEEP)
+#define F_DEEP_SLEEP    V_DEEP_SLEEP(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER 0xa58
+
+#define S_WAKE_ERROR_COUNTER    0
+#define M_WAKE_ERROR_COUNTER    0x1ffffU
+#define V_WAKE_ERROR_COUNTER(x) ((x) << S_WAKE_ERROR_COUNTER)
+#define G_WAKE_ERROR_COUNTER(x) (((x) >> S_WAKE_ERROR_COUNTER) & M_WAKE_ERROR_COUNTER)
+
+#define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1 0xa80
+
+#define S_CR4_0_BR_BLOCK_LOCK    0
+#define V_CR4_0_BR_BLOCK_LOCK(x) ((x) << S_CR4_0_BR_BLOCK_LOCK)
+#define F_CR4_0_BR_BLOCK_LOCK    V_CR4_0_BR_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2 0xa84
+#define A_MAC_PORT_MTIP_CR4_0_SEED_A_0 0xa88
+
+#define S_SEED_A_0    0
+#define M_SEED_A_0    0xffffU
+#define V_SEED_A_0(x) ((x) << S_SEED_A_0)
+#define G_SEED_A_0(x) (((x) >> S_SEED_A_0) & M_SEED_A_0)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_A_1 0xa8c
+
+#define S_SEED_A_1    0
+#define M_SEED_A_1    0xffffU
+#define V_SEED_A_1(x) ((x) << S_SEED_A_1)
+#define G_SEED_A_1(x) (((x) >> S_SEED_A_1) & M_SEED_A_1)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_A_2 0xa90
+
+#define S_SEED_A_2    0
+#define M_SEED_A_2    0xffffU
+#define V_SEED_A_2(x) ((x) << S_SEED_A_2)
+#define G_SEED_A_2(x) (((x) >> S_SEED_A_2) & M_SEED_A_2)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_A_3 0xa94
+
+#define S_SEED_A_3    0
+#define M_SEED_A_3    0xffffU
+#define V_SEED_A_3(x) ((x) << S_SEED_A_3)
+#define G_SEED_A_3(x) (((x) >> S_SEED_A_3) & M_SEED_A_3)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_B_0 0xa98
+
+#define S_SEED_B_0    0
+#define M_SEED_B_0    0xffffU
+#define V_SEED_B_0(x) ((x) << S_SEED_B_0)
+#define G_SEED_B_0(x) (((x) >> S_SEED_B_0) & M_SEED_B_0)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_B_1 0xa9c
+
+#define S_SEED_B_1    0
+#define M_SEED_B_1    0xffffU
+#define V_SEED_B_1(x) ((x) << S_SEED_B_1)
+#define G_SEED_B_1(x) (((x) >> S_SEED_B_1) & M_SEED_B_1)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_B_2 0xaa0
+
+#define S_SEED_B_2    0
+#define M_SEED_B_2    0xffffU
+#define V_SEED_B_2(x) ((x) << S_SEED_B_2)
+#define G_SEED_B_2(x) (((x) >> S_SEED_B_2) & M_SEED_B_2)
+
+#define A_MAC_PORT_MTIP_CR4_0_SEED_B_3 0xaa4
+
+#define S_SEED_B_3    0
+#define M_SEED_B_3    0xffffU
+#define V_SEED_B_3(x) ((x) << S_SEED_B_3)
+#define G_SEED_B_3(x) (((x) >> S_SEED_B_3) & M_SEED_B_3)
+
+#define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL 0xaa8
+
+#define S_TEST_PATTERN_40G    7
+#define V_TEST_PATTERN_40G(x) ((x) << S_TEST_PATTERN_40G)
+#define F_TEST_PATTERN_40G    V_TEST_PATTERN_40G(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT 0xaac
+#define A_MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT 0xab0
+
+#define S_BASE_R_BER_HIGH_ORDER_CNT    0
+#define M_BASE_R_BER_HIGH_ORDER_CNT    0xffffU
+#define V_BASE_R_BER_HIGH_ORDER_CNT(x) ((x) << S_BASE_R_BER_HIGH_ORDER_CNT)
+#define G_BASE_R_BER_HIGH_ORDER_CNT(x) (((x) >> S_BASE_R_BER_HIGH_ORDER_CNT) & M_BASE_R_BER_HIGH_ORDER_CNT)
+
+#define A_MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT 0xab4
+#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1 0xac8
+#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2 0xacc
+#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3 0xad0
+#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4 0xad4
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0 0xad8
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1 0xadc
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2 0xae0
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3 0xae4
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4 0xae8
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5 0xaec
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6 0xaf0
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7 0xaf4
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8 0xaf8
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9 0xafc
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10 0xb00
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11 0xb04
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12 0xb08
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13 0xb0c
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14 0xb10
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15 0xb14
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16 0xb18
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17 0xb1c
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18 0xb20
+#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19 0xb24
+#define A_MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING 0xb28
+#define A_MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING 0xb2c
+#define A_MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING 0xb30
+#define A_MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING 0xb34
+#define A_MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING 0xb38
+#define A_MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING 0xb3c
+#define A_MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING 0xb40
+#define A_MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING 0xb44
+#define A_MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING 0xb48
+#define A_MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING 0xb4c
+#define A_MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING 0xb50
+#define A_MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING 0xb54
+#define A_MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING 0xb58
+#define A_MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING 0xb5c
+#define A_MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING 0xb60
+#define A_MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING 0xb64
+#define A_MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING 0xb68
+#define A_MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING 0xb6c
+#define A_MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING 0xb70
+#define A_MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING 0xb74
+#define A_MAC_PORT_MTIP_CR4_0_SCRATCH 0xb78
+#define A_MAC_PORT_MTIP_CR4_0_CORE_REVISION 0xb7c
+#define A_MAC_PORT_MTIP_CR4_0_VL_INTVL 0xb80
+
+#define S_VL_INTCL    0
+#define M_VL_INTCL    0xffffU
+#define V_VL_INTCL(x) ((x) << S_VL_INTCL)
+#define G_VL_INTCL(x) (((x) >> S_VL_INTCL) & M_VL_INTCL)
+
+#define A_MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH 0xb84
+
+#define S_LANE6_LANE7    12
+#define M_LANE6_LANE7    0xfU
+#define V_LANE6_LANE7(x) ((x) << S_LANE6_LANE7)
+#define G_LANE6_LANE7(x) (((x) >> S_LANE6_LANE7) & M_LANE6_LANE7)
+
+#define S_LANE4_LANE5    8
+#define M_LANE4_LANE5    0xfU
+#define V_LANE4_LANE5(x) ((x) << S_LANE4_LANE5)
+#define G_LANE4_LANE5(x) (((x) >> S_LANE4_LANE5) & M_LANE4_LANE5)
+
+#define S_LANE2_LANE3    4
+#define M_LANE2_LANE3    0xfU
+#define V_LANE2_LANE3(x) ((x) << S_LANE2_LANE3)
+#define G_LANE2_LANE3(x) (((x) >> S_LANE2_LANE3) & M_LANE2_LANE3)
+
+#define S_LANE0_LANE1    0
+#define M_LANE0_LANE1    0xfU
+#define V_LANE0_LANE1(x) ((x) << S_LANE0_LANE1)
+#define G_LANE0_LANE1(x) (((x) >> S_LANE0_LANE1) & M_LANE0_LANE1)
+
+#define A_MAC_PORT_MTIP_CR4_0_VL0_0 0xb98
+
+#define S_M1    8
+#define M_M1    0xffU
+#define V_M1(x) ((x) << S_M1)
+#define G_M1(x) (((x) >> S_M1) & M_M1)
+
+#define S_M0    0
+#define M_M0    0xffU
+#define V_M0(x) ((x) << S_M0)
+#define G_M0(x) (((x) >> S_M0) & M_M0)
+
+#define A_MAC_PORT_MTIP_CR4_0_VL0_1 0xb9c
+
+#define S_M2    0
+#define M_M2    0xffU
+#define V_M2(x) ((x) << S_M2)
+#define G_M2(x) (((x) >> S_M2) & M_M2)
+
+#define A_MAC_PORT_MTIP_CR4_0_VL1_0 0xba0
+#define A_MAC_PORT_MTIP_CR4_0_VL1_1 0xba4
+#define A_MAC_PORT_MTIP_CR4_0_VL2_0 0xba8
+#define A_MAC_PORT_MTIP_CR4_0_VL2_1 0xbac
+#define A_MAC_PORT_MTIP_CR4_0_VL3_0 0xbb0
+#define A_MAC_PORT_MTIP_CR4_0_VL3_1 0xbb4
+#define A_MAC_PORT_MTIP_CR4_0_PCS_MODE 0xbb8
+
+#define S_ST_DISABLE_MLD    9
+#define V_ST_DISABLE_MLD(x) ((x) << S_ST_DISABLE_MLD)
+#define F_ST_DISABLE_MLD    V_ST_DISABLE_MLD(1U)
+
+#define S_ST_EN_CLAUSE49    8
+#define V_ST_EN_CLAUSE49(x) ((x) << S_ST_EN_CLAUSE49)
+#define F_ST_EN_CLAUSE49    V_ST_EN_CLAUSE49(1U)
+
+#define S_HI_BER25    2
+#define V_HI_BER25(x) ((x) << S_HI_BER25)
+#define F_HI_BER25    V_HI_BER25(1U)
+
+#define S_DISABLE_MLD    1
+#define V_DISABLE_MLD(x) ((x) << S_DISABLE_MLD)
+#define F_DISABLE_MLD    V_DISABLE_MLD(1U)
+
+#define S_ENA_CLAUSE49    0
+#define V_ENA_CLAUSE49(x) ((x) << S_ENA_CLAUSE49)
+#define F_ENA_CLAUSE49    V_ENA_CLAUSE49(1U)
+
+#define A_MAC_PORT_MTIP_CR4_0_VL4_0 0xc98
+#define A_MAC_PORT_MTIP_CR4_0_VL4_1 0xc9c
+#define A_MAC_PORT_MTIP_CR4_0_VL5_0 0xca0
+#define A_MAC_PORT_MTIP_CR4_0_VL5_1 0xca4
+#define A_MAC_PORT_MTIP_CR4_0_VL6_0 0xca8
+#define A_MAC_PORT_MTIP_CR4_0_VL6_1 0xcac
+#define A_MAC_PORT_MTIP_CR4_0_VL7_0 0xcb0
+#define A_MAC_PORT_MTIP_CR4_0_VL7_1 0xcb4
+#define A_MAC_PORT_MTIP_CR4_0_VL8_0 0xcb8
+#define A_MAC_PORT_MTIP_CR4_0_VL8_1 0xcbc
+#define A_MAC_PORT_MTIP_CR4_0_VL9_0 0xcc0
+#define A_MAC_PORT_MTIP_CR4_0_VL9_1 0xcc4
+#define A_MAC_PORT_MTIP_CR4_0_VL10_0 0xcc8
+#define A_MAC_PORT_MTIP_CR4_0_VL10_1 0xccc
+#define A_MAC_PORT_MTIP_CR4_0_VL11_0 0xcd0
+#define A_MAC_PORT_MTIP_CR4_0_VL11_1 0xcd4
+#define A_MAC_PORT_MTIP_CR4_0_VL12_0 0xcd8
+#define A_MAC_PORT_MTIP_CR4_0_VL12_1 0xcdc
+#define A_MAC_PORT_MTIP_CR4_0_VL13_0 0xce0
+#define A_MAC_PORT_MTIP_CR4_0_VL13_1 0xce4
+#define A_MAC_PORT_MTIP_CR4_0_VL14_0 0xce8
+#define A_MAC_PORT_MTIP_CR4_0_VL14_1 0xcec
+#define A_MAC_PORT_MTIP_CR4_0_VL15_0 0xcf0
+#define A_MAC_PORT_MTIP_CR4_0_VL15_1 0xcf4
+#define A_MAC_PORT_MTIP_CR4_0_VL16_0 0xcf8
+#define A_MAC_PORT_MTIP_CR4_0_VL16_1 0xcfc
+#define A_MAC_PORT_MTIP_CR4_0_VL17_0 0xd00
+#define A_MAC_PORT_MTIP_CR4_0_VL17_1 0xd04
+#define A_MAC_PORT_MTIP_CR4_0_VL18_0 0xd08
+#define A_MAC_PORT_MTIP_CR4_0_VL18_1 0xd0c
+#define A_MAC_PORT_MTIP_CR4_0_VL19_0 0xd10
+#define A_MAC_PORT_MTIP_CR4_0_VL19_1 0xd14
+#define A_MAC_PORT_MTIP_CR4_1_CONTROL_1 0x1000
+#define A_MAC_PORT_MTIP_CR4_1_STATUS_1 0x1004
+
+#define S_CR4_RX_LINK_STATUS_1    2
+#define V_CR4_RX_LINK_STATUS_1(x) ((x) << S_CR4_RX_LINK_STATUS_1)
+#define F_CR4_RX_LINK_STATUS_1    V_CR4_RX_LINK_STATUS_1(1U)
+
+#define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID0 0x1008
+
+#define S_CR4_1_DEVICE_ID0    0
+#define M_CR4_1_DEVICE_ID0    0xffffU
+#define V_CR4_1_DEVICE_ID0(x) ((x) << S_CR4_1_DEVICE_ID0)
+#define G_CR4_1_DEVICE_ID0(x) (((x) >> S_CR4_1_DEVICE_ID0) & M_CR4_1_DEVICE_ID0)
+
+#define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID1 0x100c
+
+#define S_CR4_1_DEVICE_ID1    0
+#define M_CR4_1_DEVICE_ID1    0xffffU
+#define V_CR4_1_DEVICE_ID1(x) ((x) << S_CR4_1_DEVICE_ID1)
+#define G_CR4_1_DEVICE_ID1(x) (((x) >> S_CR4_1_DEVICE_ID1) & M_CR4_1_DEVICE_ID1)
+
+#define A_MAC_PORT_MTIP_CR4_1_SPEED_ABILITY 0x1010
+#define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1 0x1014
+#define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2 0x1018
+#define A_MAC_PORT_MTIP_CR4_1_CONTROL_2 0x101c
+#define A_MAC_PORT_MTIP_CR4_1_STATUS_2 0x1020
+#define A_MAC_PORT_MTIP_CR4_1_PKG_ID0 0x1038
+#define A_MAC_PORT_MTIP_CR4_1_PKG_ID1 0x103c
+#define A_MAC_PORT_MTIP_CR4_1_EEE_CTRL 0x1050
+#define A_MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER 0x1058
+#define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1 0x1080
+
+#define S_CR4_1_BR_BLOCK_LOCK    0
+#define V_CR4_1_BR_BLOCK_LOCK(x) ((x) << S_CR4_1_BR_BLOCK_LOCK)
+#define F_CR4_1_BR_BLOCK_LOCK    V_CR4_1_BR_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2 0x1084
+#define A_MAC_PORT_MTIP_CR4_1_SEED_A_0 0x1088
+#define A_MAC_PORT_MTIP_CR4_1_SEED_A_1 0x108c
+#define A_MAC_PORT_MTIP_CR4_1_SEED_A_2 0x1090
+#define A_MAC_PORT_MTIP_CR4_1_SEED_A_3 0x1094
+#define A_MAC_PORT_MTIP_CR4_1_SEED_B_0 0x1098
+#define A_MAC_PORT_MTIP_CR4_1_SEED_B_1 0x109c
+#define A_MAC_PORT_MTIP_CR4_1_SEED_B_2 0x10a0
+#define A_MAC_PORT_MTIP_CR4_1_SEED_B_3 0x10a4
+#define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL 0x10a8
+#define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT 0x10ac
+#define A_MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT 0x10b0
+#define A_MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT 0x10b4
+#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1 0x10c8
+#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2 0x10cc
+#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3 0x10d0
+#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4 0x10d4
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0 0x10d8
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1 0x10dc
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2 0x10e0
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3 0x10e4
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4 0x10e8
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5 0x10ec
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6 0x10f0
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7 0x10f4
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8 0x10f8
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9 0x10fc
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10 0x1100
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11 0x1104
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12 0x1108
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13 0x110c
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14 0x1110
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15 0x1114
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16 0x1118
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17 0x111c
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18 0x1120
+#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19 0x1124
+#define A_MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING 0x1128
+#define A_MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING 0x112c
+#define A_MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING 0x1130
+#define A_MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING 0x1134
+#define A_MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING 0x1138
+#define A_MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING 0x113c
+#define A_MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING 0x1140
+#define A_MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING 0x1144
+#define A_MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING 0x1148
+#define A_MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING 0x114c
+#define A_MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING 0x1150
+#define A_MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING 0x1154
+#define A_MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING 0x1158
+#define A_MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING 0x115c
+#define A_MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING 0x1160
+#define A_MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING 0x1164
+#define A_MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING 0x1168
+#define A_MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING 0x116c
+#define A_MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING 0x1170
+#define A_MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING 0x1174
+#define A_MAC_PORT_MTIP_CR4_1_SCRATCH 0x1178
+#define A_MAC_PORT_MTIP_CR4_1_CORE_REVISION 0x117c
+#define A_MAC_PORT_MTIP_CR4_1_VL_INTVL 0x1180
+#define A_MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH 0x1184
+#define A_MAC_PORT_MTIP_CR4_1_VL0_0 0x1198
+#define A_MAC_PORT_MTIP_CR4_1_VL0_1 0x119c
+#define A_MAC_PORT_MTIP_CR4_1_VL1_0 0x11a0
+#define A_MAC_PORT_MTIP_CR4_1_VL1_1 0x11a4
+#define A_MAC_PORT_MTIP_CR4_1_VL2_0 0x11a8
+#define A_MAC_PORT_MTIP_CR4_1_VL2_1 0x11ac
+#define A_MAC_PORT_MTIP_CR4_1_VL3_0 0x11b0
+#define A_MAC_PORT_MTIP_CR4_1_VL3_1 0x11b4
+#define A_MAC_PORT_MTIP_CR4_1_PCS_MODE 0x11b8
+#define A_MAC_COMMON_CFG_0 0x38000
+
+#define S_T7_RX_POLARITY_INV    24
+#define M_T7_RX_POLARITY_INV    0xffU
+#define V_T7_RX_POLARITY_INV(x) ((x) << S_T7_RX_POLARITY_INV)
+#define G_T7_RX_POLARITY_INV(x) (((x) >> S_T7_RX_POLARITY_INV) & M_T7_RX_POLARITY_INV)
+
+#define S_T7_TX_POLARITY_INV    16
+#define M_T7_TX_POLARITY_INV    0xffU
+#define V_T7_TX_POLARITY_INV(x) ((x) << S_T7_TX_POLARITY_INV)
+#define G_T7_TX_POLARITY_INV(x) (((x) >> S_T7_TX_POLARITY_INV) & M_T7_TX_POLARITY_INV)
+
+#define S_T7_DEBUG_PORT_SEL    14
+#define M_T7_DEBUG_PORT_SEL    0x3U
+#define V_T7_DEBUG_PORT_SEL(x) ((x) << S_T7_DEBUG_PORT_SEL)
+#define G_T7_DEBUG_PORT_SEL(x) (((x) >> S_T7_DEBUG_PORT_SEL) & M_T7_DEBUG_PORT_SEL)
+
+#define S_MAC_SEPTY_CTL    8
+#define M_MAC_SEPTY_CTL    0x3fU
+#define V_MAC_SEPTY_CTL(x) ((x) << S_MAC_SEPTY_CTL)
+#define G_MAC_SEPTY_CTL(x) (((x) >> S_MAC_SEPTY_CTL) & M_MAC_SEPTY_CTL)
+
+#define S_T7_DEBUG_TX_RX_SEL    7
+#define V_T7_DEBUG_TX_RX_SEL(x) ((x) << S_T7_DEBUG_TX_RX_SEL)
+#define F_T7_DEBUG_TX_RX_SEL    V_T7_DEBUG_TX_RX_SEL(1U)
+
+#define S_MAC_RDY_CTL    0
+#define M_MAC_RDY_CTL    0x3fU
+#define V_MAC_RDY_CTL(x) ((x) << S_MAC_RDY_CTL)
+#define G_MAC_RDY_CTL(x) (((x) >> S_MAC_RDY_CTL) & M_MAC_RDY_CTL)
+
+#define A_MAC_MTIP_RESET_CTRL_0 0x38004
+
+#define S_RESET_F91_REF_CLK_I    31
+#define V_RESET_F91_REF_CLK_I(x) ((x) << S_RESET_F91_REF_CLK_I)
+#define F_RESET_F91_REF_CLK_I    V_RESET_F91_REF_CLK_I(1U)
+
+#define S_RESET_PCS000_REF_CLK_I    30
+#define V_RESET_PCS000_REF_CLK_I(x) ((x) << S_RESET_PCS000_REF_CLK_I)
+#define F_RESET_PCS000_REF_CLK_I    V_RESET_PCS000_REF_CLK_I(1U)
+
+#define S_RESET_REF_CLK_I    29
+#define V_RESET_REF_CLK_I(x) ((x) << S_RESET_REF_CLK_I)
+#define F_RESET_REF_CLK_I    V_RESET_REF_CLK_I(1U)
+
+#define S_RESET_SD_RX_CLK_I_0    28
+#define V_RESET_SD_RX_CLK_I_0(x) ((x) << S_RESET_SD_RX_CLK_I_0)
+#define F_RESET_SD_RX_CLK_I_0    V_RESET_SD_RX_CLK_I_0(1U)
+
+#define S_RESET_SD_RX_CLK_I_1    27
+#define V_RESET_SD_RX_CLK_I_1(x) ((x) << S_RESET_SD_RX_CLK_I_1)
+#define F_RESET_SD_RX_CLK_I_1    V_RESET_SD_RX_CLK_I_1(1U)
+
+#define S_RESET_SD_RX_CLK_I_2    26
+#define V_RESET_SD_RX_CLK_I_2(x) ((x) << S_RESET_SD_RX_CLK_I_2)
+#define F_RESET_SD_RX_CLK_I_2    V_RESET_SD_RX_CLK_I_2(1U)
+
+#define S_RESET_SD_RX_CLK_I_3    25
+#define V_RESET_SD_RX_CLK_I_3(x) ((x) << S_RESET_SD_RX_CLK_I_3)
+#define F_RESET_SD_RX_CLK_I_3    V_RESET_SD_RX_CLK_I_3(1U)
+
+#define S_RESET_SD_RX_CLK_I_4    24
+#define V_RESET_SD_RX_CLK_I_4(x) ((x) << S_RESET_SD_RX_CLK_I_4)
+#define F_RESET_SD_RX_CLK_I_4    V_RESET_SD_RX_CLK_I_4(1U)
+
+#define S_RESET_SD_RX_CLK_I_5    23
+#define V_RESET_SD_RX_CLK_I_5(x) ((x) << S_RESET_SD_RX_CLK_I_5)
+#define F_RESET_SD_RX_CLK_I_5    V_RESET_SD_RX_CLK_I_5(1U)
+
+#define S_RESET_SD_RX_CLK_I_6    22
+#define V_RESET_SD_RX_CLK_I_6(x) ((x) << S_RESET_SD_RX_CLK_I_6)
+#define F_RESET_SD_RX_CLK_I_6    V_RESET_SD_RX_CLK_I_6(1U)
+
+#define S_RESET_SD_RX_CLK_I_7    21
+#define V_RESET_SD_RX_CLK_I_7(x) ((x) << S_RESET_SD_RX_CLK_I_7)
+#define F_RESET_SD_RX_CLK_I_7    V_RESET_SD_RX_CLK_I_7(1U)
+
+#define S_RESET_SD_TX_CLK_I_0    20
+#define V_RESET_SD_TX_CLK_I_0(x) ((x) << S_RESET_SD_TX_CLK_I_0)
+#define F_RESET_SD_TX_CLK_I_0    V_RESET_SD_TX_CLK_I_0(1U)
+
+#define S_RESET_SD_TX_CLK_I_1    19
+#define V_RESET_SD_TX_CLK_I_1(x) ((x) << S_RESET_SD_TX_CLK_I_1)
+#define F_RESET_SD_TX_CLK_I_1    V_RESET_SD_TX_CLK_I_1(1U)
+
+#define S_RESET_SD_TX_CLK_I_2    18
+#define V_RESET_SD_TX_CLK_I_2(x) ((x) << S_RESET_SD_TX_CLK_I_2)
+#define F_RESET_SD_TX_CLK_I_2    V_RESET_SD_TX_CLK_I_2(1U)
+
+#define S_RESET_SD_TX_CLK_I_3    17
+#define V_RESET_SD_TX_CLK_I_3(x) ((x) << S_RESET_SD_TX_CLK_I_3)
+#define F_RESET_SD_TX_CLK_I_3    V_RESET_SD_TX_CLK_I_3(1U)
+
+#define S_RESET_SD_TX_CLK_I_4    16
+#define V_RESET_SD_TX_CLK_I_4(x) ((x) << S_RESET_SD_TX_CLK_I_4)
+#define F_RESET_SD_TX_CLK_I_4    V_RESET_SD_TX_CLK_I_4(1U)
+
+#define S_RESET_SD_TX_CLK_I_5    15
+#define V_RESET_SD_TX_CLK_I_5(x) ((x) << S_RESET_SD_TX_CLK_I_5)
+#define F_RESET_SD_TX_CLK_I_5    V_RESET_SD_TX_CLK_I_5(1U)
+
+#define S_RESET_SD_TX_CLK_I_6    14
+#define V_RESET_SD_TX_CLK_I_6(x) ((x) << S_RESET_SD_TX_CLK_I_6)
+#define F_RESET_SD_TX_CLK_I_6    V_RESET_SD_TX_CLK_I_6(1U)
+
+#define S_RESET_SD_TX_CLK_I_7    13
+#define V_RESET_SD_TX_CLK_I_7(x) ((x) << S_RESET_SD_TX_CLK_I_7)
+#define F_RESET_SD_TX_CLK_I_7    V_RESET_SD_TX_CLK_I_7(1U)
+
+#define S_RESET_XPCS_REF_CLK_I_0    12
+#define V_RESET_XPCS_REF_CLK_I_0(x) ((x) << S_RESET_XPCS_REF_CLK_I_0)
+#define F_RESET_XPCS_REF_CLK_I_0    V_RESET_XPCS_REF_CLK_I_0(1U)
+
+#define S_RESET_XPCS_REF_CLK_I_1    11
+#define V_RESET_XPCS_REF_CLK_I_1(x) ((x) << S_RESET_XPCS_REF_CLK_I_1)
+#define F_RESET_XPCS_REF_CLK_I_1    V_RESET_XPCS_REF_CLK_I_1(1U)
+
+#define S_RESET_FF_RX_CLK_0_I    9
+#define V_RESET_FF_RX_CLK_0_I(x) ((x) << S_RESET_FF_RX_CLK_0_I)
+#define F_RESET_FF_RX_CLK_0_I    V_RESET_FF_RX_CLK_0_I(1U)
+
+#define S_RESET_FF_TX_CLK_0_I    8
+#define V_RESET_FF_TX_CLK_0_I(x) ((x) << S_RESET_FF_TX_CLK_0_I)
+#define F_RESET_FF_TX_CLK_0_I    V_RESET_FF_TX_CLK_0_I(1U)
+
+#define S_RESET_RXCLK_0_I    7
+#define V_RESET_RXCLK_0_I(x) ((x) << S_RESET_RXCLK_0_I)
+#define F_RESET_RXCLK_0_I    V_RESET_RXCLK_0_I(1U)
+
+#define S_RESET_TXCLK_0_I    6
+#define V_RESET_TXCLK_0_I(x) ((x) << S_RESET_TXCLK_0_I)
+#define F_RESET_TXCLK_0_I    V_RESET_TXCLK_0_I(1U)
+
+#define S_RESET_FF_RX_CLK_1_I    5
+#define V_RESET_FF_RX_CLK_1_I(x) ((x) << S_RESET_FF_RX_CLK_1_I)
+#define F_RESET_FF_RX_CLK_1_I    V_RESET_FF_RX_CLK_1_I(1U)
+
+#define S_RESET_FF_TX_CLK_1_I    4
+#define V_RESET_FF_TX_CLK_1_I(x) ((x) << S_RESET_FF_TX_CLK_1_I)
+#define F_RESET_FF_TX_CLK_1_I    V_RESET_FF_TX_CLK_1_I(1U)
+
+#define S_RESET_RXCLK_1_I    3
+#define V_RESET_RXCLK_1_I(x) ((x) << S_RESET_RXCLK_1_I)
+#define F_RESET_RXCLK_1_I    V_RESET_RXCLK_1_I(1U)
+
+#define S_RESET_TXCLK_1_I    2
+#define V_RESET_TXCLK_1_I(x) ((x) << S_RESET_TXCLK_1_I)
+#define F_RESET_TXCLK_1_I    V_RESET_TXCLK_1_I(1U)
+
+#define S_XGMII_CLK_RESET_0    0
+#define V_XGMII_CLK_RESET_0(x) ((x) << S_XGMII_CLK_RESET_0)
+#define F_XGMII_CLK_RESET_0    V_XGMII_CLK_RESET_0(1U)
+
+#define A_MAC_MTIP_RESET_CTRL_1 0x38008
+
+#define S_RESET_FF_RX_CLK_2_I    31
+#define V_RESET_FF_RX_CLK_2_I(x) ((x) << S_RESET_FF_RX_CLK_2_I)
+#define F_RESET_FF_RX_CLK_2_I    V_RESET_FF_RX_CLK_2_I(1U)
+
+#define S_RESET_FF_TX_CLK_2_I    30
+#define V_RESET_FF_TX_CLK_2_I(x) ((x) << S_RESET_FF_TX_CLK_2_I)
+#define F_RESET_FF_TX_CLK_2_I    V_RESET_FF_TX_CLK_2_I(1U)
+
+#define S_RESET_RXCLK_2_I    29
+#define V_RESET_RXCLK_2_I(x) ((x) << S_RESET_RXCLK_2_I)
+#define F_RESET_RXCLK_2_I    V_RESET_RXCLK_2_I(1U)
+
+#define S_RESET_TXCLK_2_I    28
+#define V_RESET_TXCLK_2_I(x) ((x) << S_RESET_TXCLK_2_I)
+#define F_RESET_TXCLK_2_I    V_RESET_TXCLK_2_I(1U)
+
+#define S_RESET_FF_RX_CLK_3_I    27
+#define V_RESET_FF_RX_CLK_3_I(x) ((x) << S_RESET_FF_RX_CLK_3_I)
+#define F_RESET_FF_RX_CLK_3_I    V_RESET_FF_RX_CLK_3_I(1U)
+
+#define S_RESET_FF_TX_CLK_3_I    26
+#define V_RESET_FF_TX_CLK_3_I(x) ((x) << S_RESET_FF_TX_CLK_3_I)
+#define F_RESET_FF_TX_CLK_3_I    V_RESET_FF_TX_CLK_3_I(1U)
+
+#define S_RESET_RXCLK_3_I    25
+#define V_RESET_RXCLK_3_I(x) ((x) << S_RESET_RXCLK_3_I)
+#define F_RESET_RXCLK_3_I    V_RESET_RXCLK_3_I(1U)
+
+#define S_RESET_TXCLK_3_I    24
+#define V_RESET_TXCLK_3_I(x) ((x) << S_RESET_TXCLK_3_I)
+#define F_RESET_TXCLK_3_I    V_RESET_TXCLK_3_I(1U)
+
+#define S_RESET_FF_RX_CLK_4_I    23
+#define V_RESET_FF_RX_CLK_4_I(x) ((x) << S_RESET_FF_RX_CLK_4_I)
+#define F_RESET_FF_RX_CLK_4_I    V_RESET_FF_RX_CLK_4_I(1U)
+
+#define S_RESET_FF_TX_CLK_4_I    22
+#define V_RESET_FF_TX_CLK_4_I(x) ((x) << S_RESET_FF_TX_CLK_4_I)
+#define F_RESET_FF_TX_CLK_4_I    V_RESET_FF_TX_CLK_4_I(1U)
+
+#define S_RESET_RXCLK_4_I    21
+#define V_RESET_RXCLK_4_I(x) ((x) << S_RESET_RXCLK_4_I)
+#define F_RESET_RXCLK_4_I    V_RESET_RXCLK_4_I(1U)
+
+#define S_RESET_TXCLK_4_I    20
+#define V_RESET_TXCLK_4_I(x) ((x) << S_RESET_TXCLK_4_I)
+#define F_RESET_TXCLK_4_I    V_RESET_TXCLK_4_I(1U)
+
+#define S_RESET_FF_RX_CLK_5_I    19
+#define V_RESET_FF_RX_CLK_5_I(x) ((x) << S_RESET_FF_RX_CLK_5_I)
+#define F_RESET_FF_RX_CLK_5_I    V_RESET_FF_RX_CLK_5_I(1U)
+
+#define S_RESET_FF_TX_CLK_5_I    18
+#define V_RESET_FF_TX_CLK_5_I(x) ((x) << S_RESET_FF_TX_CLK_5_I)
+#define F_RESET_FF_TX_CLK_5_I    V_RESET_FF_TX_CLK_5_I(1U)
+
+#define S_RESET_RXCLK_5_I    17
+#define V_RESET_RXCLK_5_I(x) ((x) << S_RESET_RXCLK_5_I)
+#define F_RESET_RXCLK_5_I    V_RESET_RXCLK_5_I(1U)
+
+#define S_RESET_TXCLK_5_I    16
+#define V_RESET_TXCLK_5_I(x) ((x) << S_RESET_TXCLK_5_I)
+#define F_RESET_TXCLK_5_I    V_RESET_TXCLK_5_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_0_I    15
+#define V_RESET_SD_RX_CLK_AN_0_I(x) ((x) << S_RESET_SD_RX_CLK_AN_0_I)
+#define F_RESET_SD_RX_CLK_AN_0_I    V_RESET_SD_RX_CLK_AN_0_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_0_I    14
+#define V_RESET_SD_TX_CLK_AN_0_I(x) ((x) << S_RESET_SD_TX_CLK_AN_0_I)
+#define F_RESET_SD_TX_CLK_AN_0_I    V_RESET_SD_TX_CLK_AN_0_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_1_I    13
+#define V_RESET_SD_RX_CLK_AN_1_I(x) ((x) << S_RESET_SD_RX_CLK_AN_1_I)
+#define F_RESET_SD_RX_CLK_AN_1_I    V_RESET_SD_RX_CLK_AN_1_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_1_I    12
+#define V_RESET_SD_TX_CLK_AN_1_I(x) ((x) << S_RESET_SD_TX_CLK_AN_1_I)
+#define F_RESET_SD_TX_CLK_AN_1_I    V_RESET_SD_TX_CLK_AN_1_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_2_I    11
+#define V_RESET_SD_RX_CLK_AN_2_I(x) ((x) << S_RESET_SD_RX_CLK_AN_2_I)
+#define F_RESET_SD_RX_CLK_AN_2_I    V_RESET_SD_RX_CLK_AN_2_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_2_I    10
+#define V_RESET_SD_TX_CLK_AN_2_I(x) ((x) << S_RESET_SD_TX_CLK_AN_2_I)
+#define F_RESET_SD_TX_CLK_AN_2_I    V_RESET_SD_TX_CLK_AN_2_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_3_I    9
+#define V_RESET_SD_RX_CLK_AN_3_I(x) ((x) << S_RESET_SD_RX_CLK_AN_3_I)
+#define F_RESET_SD_RX_CLK_AN_3_I    V_RESET_SD_RX_CLK_AN_3_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_3_I    8
+#define V_RESET_SD_TX_CLK_AN_3_I(x) ((x) << S_RESET_SD_TX_CLK_AN_3_I)
+#define F_RESET_SD_TX_CLK_AN_3_I    V_RESET_SD_TX_CLK_AN_3_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_4_I    7
+#define V_RESET_SD_RX_CLK_AN_4_I(x) ((x) << S_RESET_SD_RX_CLK_AN_4_I)
+#define F_RESET_SD_RX_CLK_AN_4_I    V_RESET_SD_RX_CLK_AN_4_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_4_I    6
+#define V_RESET_SD_TX_CLK_AN_4_I(x) ((x) << S_RESET_SD_TX_CLK_AN_4_I)
+#define F_RESET_SD_TX_CLK_AN_4_I    V_RESET_SD_TX_CLK_AN_4_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_5_I    5
+#define V_RESET_SD_RX_CLK_AN_5_I(x) ((x) << S_RESET_SD_RX_CLK_AN_5_I)
+#define F_RESET_SD_RX_CLK_AN_5_I    V_RESET_SD_RX_CLK_AN_5_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_5_I    4
+#define V_RESET_SD_TX_CLK_AN_5_I(x) ((x) << S_RESET_SD_TX_CLK_AN_5_I)
+#define F_RESET_SD_TX_CLK_AN_5_I    V_RESET_SD_TX_CLK_AN_5_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_6_I    3
+#define V_RESET_SD_RX_CLK_AN_6_I(x) ((x) << S_RESET_SD_RX_CLK_AN_6_I)
+#define F_RESET_SD_RX_CLK_AN_6_I    V_RESET_SD_RX_CLK_AN_6_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_6_I    2
+#define V_RESET_SD_TX_CLK_AN_6_I(x) ((x) << S_RESET_SD_TX_CLK_AN_6_I)
+#define F_RESET_SD_TX_CLK_AN_6_I    V_RESET_SD_TX_CLK_AN_6_I(1U)
+
+#define S_RESET_SD_RX_CLK_AN_7_I    1
+#define V_RESET_SD_RX_CLK_AN_7_I(x) ((x) << S_RESET_SD_RX_CLK_AN_7_I)
+#define F_RESET_SD_RX_CLK_AN_7_I    V_RESET_SD_RX_CLK_AN_7_I(1U)
+
+#define S_RESET_SD_TX_CLK_AN_7_I    0
+#define V_RESET_SD_TX_CLK_AN_7_I(x) ((x) << S_RESET_SD_TX_CLK_AN_7_I)
+#define F_RESET_SD_TX_CLK_AN_7_I    V_RESET_SD_TX_CLK_AN_7_I(1U)
+
+#define A_MAC_MTIP_RESET_CTRL_2 0x3800c
+
+#define S_RESET_SGMII_TXCLK_I_3    31
+#define V_RESET_SGMII_TXCLK_I_3(x) ((x) << S_RESET_SGMII_TXCLK_I_3)
+#define F_RESET_SGMII_TXCLK_I_3    V_RESET_SGMII_TXCLK_I_3(1U)
+
+#define S_RESET_SGMII_RXCLK_I_3    30
+#define V_RESET_SGMII_RXCLK_I_3(x) ((x) << S_RESET_SGMII_RXCLK_I_3)
+#define F_RESET_SGMII_RXCLK_I_3    V_RESET_SGMII_RXCLK_I_3(1U)
+
+#define S_RESET_SGMII_TXCLK_I_2    29
+#define V_RESET_SGMII_TXCLK_I_2(x) ((x) << S_RESET_SGMII_TXCLK_I_2)
+#define F_RESET_SGMII_TXCLK_I_2    V_RESET_SGMII_TXCLK_I_2(1U)
+
+#define S_RESET_SGMII_RXCLK_I_2    28
+#define V_RESET_SGMII_RXCLK_I_2(x) ((x) << S_RESET_SGMII_RXCLK_I_2)
+#define F_RESET_SGMII_RXCLK_I_2    V_RESET_SGMII_RXCLK_I_2(1U)
+
+#define S_RESET_SGMII_TXCLK_I_1    27
+#define V_RESET_SGMII_TXCLK_I_1(x) ((x) << S_RESET_SGMII_TXCLK_I_1)
+#define F_RESET_SGMII_TXCLK_I_1    V_RESET_SGMII_TXCLK_I_1(1U)
+
+#define S_RESET_SGMII_RXCLK_I_1    26
+#define V_RESET_SGMII_RXCLK_I_1(x) ((x) << S_RESET_SGMII_RXCLK_I_1)
+#define F_RESET_SGMII_RXCLK_I_1    V_RESET_SGMII_RXCLK_I_1(1U)
+
+#define S_RESET_SGMII_TXCLK_I_0    25
+#define V_RESET_SGMII_TXCLK_I_0(x) ((x) << S_RESET_SGMII_TXCLK_I_0)
+#define F_RESET_SGMII_TXCLK_I_0    V_RESET_SGMII_TXCLK_I_0(1U)
+
+#define S_RESET_SGMII_RXCLK_I_0    24
+#define V_RESET_SGMII_RXCLK_I_0(x) ((x) << S_RESET_SGMII_RXCLK_I_0)
+#define F_RESET_SGMII_RXCLK_I_0    V_RESET_SGMII_RXCLK_I_0(1U)
+
+#define S_MTIPSD7TXRST    23
+#define V_MTIPSD7TXRST(x) ((x) << S_MTIPSD7TXRST)
+#define F_MTIPSD7TXRST    V_MTIPSD7TXRST(1U)
+
+#define S_MTIPSD6TXRST    22
+#define V_MTIPSD6TXRST(x) ((x) << S_MTIPSD6TXRST)
+#define F_MTIPSD6TXRST    V_MTIPSD6TXRST(1U)
+
+#define S_MTIPSD5TXRST    21
+#define V_MTIPSD5TXRST(x) ((x) << S_MTIPSD5TXRST)
+#define F_MTIPSD5TXRST    V_MTIPSD5TXRST(1U)
+
+#define S_MTIPSD4TXRST    20
+#define V_MTIPSD4TXRST(x) ((x) << S_MTIPSD4TXRST)
+#define F_MTIPSD4TXRST    V_MTIPSD4TXRST(1U)
+
+#define S_T7_MTIPSD3TXRST    19
+#define V_T7_MTIPSD3TXRST(x) ((x) << S_T7_MTIPSD3TXRST)
+#define F_T7_MTIPSD3TXRST    V_T7_MTIPSD3TXRST(1U)
+
+#define S_T7_MTIPSD2TXRST    18
+#define V_T7_MTIPSD2TXRST(x) ((x) << S_T7_MTIPSD2TXRST)
+#define F_T7_MTIPSD2TXRST    V_T7_MTIPSD2TXRST(1U)
+
+#define S_T7_MTIPSD1TXRST    17
+#define V_T7_MTIPSD1TXRST(x) ((x) << S_T7_MTIPSD1TXRST)
+#define F_T7_MTIPSD1TXRST    V_T7_MTIPSD1TXRST(1U)
+
+#define S_T7_MTIPSD0TXRST    16
+#define V_T7_MTIPSD0TXRST(x) ((x) << S_T7_MTIPSD0TXRST)
+#define F_T7_MTIPSD0TXRST    V_T7_MTIPSD0TXRST(1U)
+
+#define S_MTIPSD7RXRST    15
+#define V_MTIPSD7RXRST(x) ((x) << S_MTIPSD7RXRST)
+#define F_MTIPSD7RXRST    V_MTIPSD7RXRST(1U)
+
+#define S_MTIPSD6RXRST    14
+#define V_MTIPSD6RXRST(x) ((x) << S_MTIPSD6RXRST)
+#define F_MTIPSD6RXRST    V_MTIPSD6RXRST(1U)
+
+#define S_MTIPSD5RXRST    13
+#define V_MTIPSD5RXRST(x) ((x) << S_MTIPSD5RXRST)
+#define F_MTIPSD5RXRST    V_MTIPSD5RXRST(1U)
+
+#define S_MTIPSD4RXRST    12
+#define V_MTIPSD4RXRST(x) ((x) << S_MTIPSD4RXRST)
+#define F_MTIPSD4RXRST    V_MTIPSD4RXRST(1U)
+
+#define S_T7_MTIPSD3RXRST    11
+#define V_T7_MTIPSD3RXRST(x) ((x) << S_T7_MTIPSD3RXRST)
+#define F_T7_MTIPSD3RXRST    V_T7_MTIPSD3RXRST(1U)
+
+#define S_T7_MTIPSD2RXRST    10
+#define V_T7_MTIPSD2RXRST(x) ((x) << S_T7_MTIPSD2RXRST)
+#define F_T7_MTIPSD2RXRST    V_T7_MTIPSD2RXRST(1U)
+
+#define S_T7_MTIPSD1RXRST    9
+#define V_T7_MTIPSD1RXRST(x) ((x) << S_T7_MTIPSD1RXRST)
+#define F_T7_MTIPSD1RXRST    V_T7_MTIPSD1RXRST(1U)
+
+#define S_T7_MTIPSD0RXRST    8
+#define V_T7_MTIPSD0RXRST(x) ((x) << S_T7_MTIPSD0RXRST)
+#define F_T7_MTIPSD0RXRST    V_T7_MTIPSD0RXRST(1U)
+
+#define S_RESET_REG_CLK_AN_0_I    7
+#define V_RESET_REG_CLK_AN_0_I(x) ((x) << S_RESET_REG_CLK_AN_0_I)
+#define F_RESET_REG_CLK_AN_0_I    V_RESET_REG_CLK_AN_0_I(1U)
+
+#define S_RESET_REG_CLK_AN_1_I    6
+#define V_RESET_REG_CLK_AN_1_I(x) ((x) << S_RESET_REG_CLK_AN_1_I)
+#define F_RESET_REG_CLK_AN_1_I    V_RESET_REG_CLK_AN_1_I(1U)
+
+#define S_RESET_REG_CLK_AN_2_I    5
+#define V_RESET_REG_CLK_AN_2_I(x) ((x) << S_RESET_REG_CLK_AN_2_I)
+#define F_RESET_REG_CLK_AN_2_I    V_RESET_REG_CLK_AN_2_I(1U)
+
+#define S_RESET_REG_CLK_AN_3_I    4
+#define V_RESET_REG_CLK_AN_3_I(x) ((x) << S_RESET_REG_CLK_AN_3_I)
+#define F_RESET_REG_CLK_AN_3_I    V_RESET_REG_CLK_AN_3_I(1U)
+
+#define S_RESET_REG_CLK_AN_4_I    3
+#define V_RESET_REG_CLK_AN_4_I(x) ((x) << S_RESET_REG_CLK_AN_4_I)
+#define F_RESET_REG_CLK_AN_4_I    V_RESET_REG_CLK_AN_4_I(1U)
+
+#define S_RESET_REG_CLK_AN_5_I    2
+#define V_RESET_REG_CLK_AN_5_I(x) ((x) << S_RESET_REG_CLK_AN_5_I)
+#define F_RESET_REG_CLK_AN_5_I    V_RESET_REG_CLK_AN_5_I(1U)
+
+#define S_RESET_REG_CLK_AN_6_I    1
+#define V_RESET_REG_CLK_AN_6_I(x) ((x) << S_RESET_REG_CLK_AN_6_I)
+#define F_RESET_REG_CLK_AN_6_I    V_RESET_REG_CLK_AN_6_I(1U)
+
+#define S_RESET_REG_CLK_AN_7_I    0
+#define V_RESET_REG_CLK_AN_7_I(x) ((x) << S_RESET_REG_CLK_AN_7_I)
+#define F_RESET_REG_CLK_AN_7_I    V_RESET_REG_CLK_AN_7_I(1U)
+
+#define A_MAC_MTIP_CLK_CTRL_0 0x38010
+
+#define S_F91_REF_CLK_I_G    31
+#define V_F91_REF_CLK_I_G(x) ((x) << S_F91_REF_CLK_I_G)
+#define F_F91_REF_CLK_I_G    V_F91_REF_CLK_I_G(1U)
+
+#define S_PCS000_REF_CLK_I_G    30
+#define V_PCS000_REF_CLK_I_G(x) ((x) << S_PCS000_REF_CLK_I_G)
+#define F_PCS000_REF_CLK_I_G    V_PCS000_REF_CLK_I_G(1U)
+
+#define S_REF_CLK_I_G    29
+#define V_REF_CLK_I_G(x) ((x) << S_REF_CLK_I_G)
+#define F_REF_CLK_I_G    V_REF_CLK_I_G(1U)
+
+#define S_SD_RX_CLK_I_0_G    28
+#define V_SD_RX_CLK_I_0_G(x) ((x) << S_SD_RX_CLK_I_0_G)
+#define F_SD_RX_CLK_I_0_G    V_SD_RX_CLK_I_0_G(1U)
+
+#define S_SD_RX_CLK_I_1_G    27
+#define V_SD_RX_CLK_I_1_G(x) ((x) << S_SD_RX_CLK_I_1_G)
+#define F_SD_RX_CLK_I_1_G    V_SD_RX_CLK_I_1_G(1U)
+
+#define S_SD_RX_CLK_I_2_G    26
+#define V_SD_RX_CLK_I_2_G(x) ((x) << S_SD_RX_CLK_I_2_G)
+#define F_SD_RX_CLK_I_2_G    V_SD_RX_CLK_I_2_G(1U)
+
+#define S_SD_RX_CLK_I_3_G    25
+#define V_SD_RX_CLK_I_3_G(x) ((x) << S_SD_RX_CLK_I_3_G)
+#define F_SD_RX_CLK_I_3_G    V_SD_RX_CLK_I_3_G(1U)
+
+#define S_SD_RX_CLK_I_4_G    24
+#define V_SD_RX_CLK_I_4_G(x) ((x) << S_SD_RX_CLK_I_4_G)
+#define F_SD_RX_CLK_I_4_G    V_SD_RX_CLK_I_4_G(1U)
+
+#define S_SD_RX_CLK_I_5_G    23
+#define V_SD_RX_CLK_I_5_G(x) ((x) << S_SD_RX_CLK_I_5_G)
+#define F_SD_RX_CLK_I_5_G    V_SD_RX_CLK_I_5_G(1U)
+
+#define S_SD_RX_CLK_I_6_G    22
+#define V_SD_RX_CLK_I_6_G(x) ((x) << S_SD_RX_CLK_I_6_G)
+#define F_SD_RX_CLK_I_6_G    V_SD_RX_CLK_I_6_G(1U)
+
+#define S_SD_RX_CLK_I_7_G    21
+#define V_SD_RX_CLK_I_7_G(x) ((x) << S_SD_RX_CLK_I_7_G)
+#define F_SD_RX_CLK_I_7_G    V_SD_RX_CLK_I_7_G(1U)
+
+#define S_SD_TX_CLK_I_0_G    20
+#define V_SD_TX_CLK_I_0_G(x) ((x) << S_SD_TX_CLK_I_0_G)
+#define F_SD_TX_CLK_I_0_G    V_SD_TX_CLK_I_0_G(1U)
+
+#define S_SD_TX_CLK_I_1_G    19
+#define V_SD_TX_CLK_I_1_G(x) ((x) << S_SD_TX_CLK_I_1_G)
+#define F_SD_TX_CLK_I_1_G    V_SD_TX_CLK_I_1_G(1U)
+
+#define S_SD_TX_CLK_I_2_G    18
+#define V_SD_TX_CLK_I_2_G(x) ((x) << S_SD_TX_CLK_I_2_G)
+#define F_SD_TX_CLK_I_2_G    V_SD_TX_CLK_I_2_G(1U)
+
+#define S_SD_TX_CLK_I_3_G    17
+#define V_SD_TX_CLK_I_3_G(x) ((x) << S_SD_TX_CLK_I_3_G)
+#define F_SD_TX_CLK_I_3_G    V_SD_TX_CLK_I_3_G(1U)
+
+#define S_SD_TX_CLK_I_4_G    16
+#define V_SD_TX_CLK_I_4_G(x) ((x) << S_SD_TX_CLK_I_4_G)
+#define F_SD_TX_CLK_I_4_G    V_SD_TX_CLK_I_4_G(1U)
+
+#define S_SD_TX_CLK_I_5_G    15
+#define V_SD_TX_CLK_I_5_G(x) ((x) << S_SD_TX_CLK_I_5_G)
+#define F_SD_TX_CLK_I_5_G    V_SD_TX_CLK_I_5_G(1U)
+
+#define S_SD_TX_CLK_I_6_G    14
+#define V_SD_TX_CLK_I_6_G(x) ((x) << S_SD_TX_CLK_I_6_G)
+#define F_SD_TX_CLK_I_6_G    V_SD_TX_CLK_I_6_G(1U)
+
+#define S_SD_TX_CLK_I_7_G    13
+#define V_SD_TX_CLK_I_7_G(x) ((x) << S_SD_TX_CLK_I_7_G)
+#define F_SD_TX_CLK_I_7_G    V_SD_TX_CLK_I_7_G(1U)
+
+#define S_XPCS_REF_CLK_I_0_G    12
+#define V_XPCS_REF_CLK_I_0_G(x) ((x) << S_XPCS_REF_CLK_I_0_G)
+#define F_XPCS_REF_CLK_I_0_G    V_XPCS_REF_CLK_I_0_G(1U)
+
+#define S_XPCS_REF_CLK_I_1_G    11
+#define V_XPCS_REF_CLK_I_1_G(x) ((x) << S_XPCS_REF_CLK_I_1_G)
+#define F_XPCS_REF_CLK_I_1_G    V_XPCS_REF_CLK_I_1_G(1U)
+
+#define S_REG_CLK_I_G    10
+#define V_REG_CLK_I_G(x) ((x) << S_REG_CLK_I_G)
+#define F_REG_CLK_I_G    V_REG_CLK_I_G(1U)
+
+#define S_FF_RX_CLK_0_I_G    9
+#define V_FF_RX_CLK_0_I_G(x) ((x) << S_FF_RX_CLK_0_I_G)
+#define F_FF_RX_CLK_0_I_G    V_FF_RX_CLK_0_I_G(1U)
+
+#define S_FF_TX_CLK_0_I_G    8
+#define V_FF_TX_CLK_0_I_G(x) ((x) << S_FF_TX_CLK_0_I_G)
+#define F_FF_TX_CLK_0_I_G    V_FF_TX_CLK_0_I_G(1U)
+
+#define S_RXCLK_0_I_G    7
+#define V_RXCLK_0_I_G(x) ((x) << S_RXCLK_0_I_G)
+#define F_RXCLK_0_I_G    V_RXCLK_0_I_G(1U)
+
+#define S_TXCLK_0_I_G    6
+#define V_TXCLK_0_I_G(x) ((x) << S_TXCLK_0_I_G)
+#define F_TXCLK_0_I_G    V_TXCLK_0_I_G(1U)
+
+#define S_FF_RX_CLK_1_I_G    5
+#define V_FF_RX_CLK_1_I_G(x) ((x) << S_FF_RX_CLK_1_I_G)
+#define F_FF_RX_CLK_1_I_G    V_FF_RX_CLK_1_I_G(1U)
+
+#define S_FF_TX_CLK_1_I_G    4
+#define V_FF_TX_CLK_1_I_G(x) ((x) << S_FF_TX_CLK_1_I_G)
+#define F_FF_TX_CLK_1_I_G    V_FF_TX_CLK_1_I_G(1U)
+
+#define S_RXCLK_1_I_G    3
+#define V_RXCLK_1_I_G(x) ((x) << S_RXCLK_1_I_G)
+#define F_RXCLK_1_I_G    V_RXCLK_1_I_G(1U)
+
+#define S_TXCLK_1_I_G    2
+#define V_TXCLK_1_I_G(x) ((x) << S_TXCLK_1_I_G)
+#define F_TXCLK_1_I_G    V_TXCLK_1_I_G(1U)
+
+#define A_MAC_MTIP_CLK_CTRL_1 0x38014
+
+#define S_FF_RX_CLK_2_I_G    31
+#define V_FF_RX_CLK_2_I_G(x) ((x) << S_FF_RX_CLK_2_I_G)
+#define F_FF_RX_CLK_2_I_G    V_FF_RX_CLK_2_I_G(1U)
+
+#define S_FF_TX_CLK_2_I_G    30
+#define V_FF_TX_CLK_2_I_G(x) ((x) << S_FF_TX_CLK_2_I_G)
+#define F_FF_TX_CLK_2_I_G    V_FF_TX_CLK_2_I_G(1U)
+
+#define S_RXCLK_2_I_G    29
+#define V_RXCLK_2_I_G(x) ((x) << S_RXCLK_2_I_G)
+#define F_RXCLK_2_I_G    V_RXCLK_2_I_G(1U)
+
+#define S_TXCLK_2_I_G    28
+#define V_TXCLK_2_I_G(x) ((x) << S_TXCLK_2_I_G)
+#define F_TXCLK_2_I_G    V_TXCLK_2_I_G(1U)
+
+#define S_FF_RX_CLK_3_I_G    27
+#define V_FF_RX_CLK_3_I_G(x) ((x) << S_FF_RX_CLK_3_I_G)
+#define F_FF_RX_CLK_3_I_G    V_FF_RX_CLK_3_I_G(1U)
+
+#define S_FF_TX_CLK_3_I_G    26
+#define V_FF_TX_CLK_3_I_G(x) ((x) << S_FF_TX_CLK_3_I_G)
+#define F_FF_TX_CLK_3_I_G    V_FF_TX_CLK_3_I_G(1U)
+
+#define S_RXCLK_3_I_G    25
+#define V_RXCLK_3_I_G(x) ((x) << S_RXCLK_3_I_G)
+#define F_RXCLK_3_I_G    V_RXCLK_3_I_G(1U)
+
+#define S_TXCLK_3_I_G    24
+#define V_TXCLK_3_I_G(x) ((x) << S_TXCLK_3_I_G)
+#define F_TXCLK_3_I_G    V_TXCLK_3_I_G(1U)
+
+#define S_FF_RX_CLK_4_I_G    23
+#define V_FF_RX_CLK_4_I_G(x) ((x) << S_FF_RX_CLK_4_I_G)
+#define F_FF_RX_CLK_4_I_G    V_FF_RX_CLK_4_I_G(1U)
+
+#define S_FF_TX_CLK_4_I_G    22
+#define V_FF_TX_CLK_4_I_G(x) ((x) << S_FF_TX_CLK_4_I_G)
+#define F_FF_TX_CLK_4_I_G    V_FF_TX_CLK_4_I_G(1U)
+
+#define S_RXCLK_4_I_G    21
+#define V_RXCLK_4_I_G(x) ((x) << S_RXCLK_4_I_G)
+#define F_RXCLK_4_I_G    V_RXCLK_4_I_G(1U)
+
+#define S_TXCLK_4_I_G    20
+#define V_TXCLK_4_I_G(x) ((x) << S_TXCLK_4_I_G)
+#define F_TXCLK_4_I_G    V_TXCLK_4_I_G(1U)
+
+#define S_FF_RX_CLK_5_I_G    19
+#define V_FF_RX_CLK_5_I_G(x) ((x) << S_FF_RX_CLK_5_I_G)
+#define F_FF_RX_CLK_5_I_G    V_FF_RX_CLK_5_I_G(1U)
+
+#define S_FF_TX_CLK_5_I_G    18
+#define V_FF_TX_CLK_5_I_G(x) ((x) << S_FF_TX_CLK_5_I_G)
+#define F_FF_TX_CLK_5_I_G    V_FF_TX_CLK_5_I_G(1U)
+
+#define S_RXCLK_5_I_G    17
+#define V_RXCLK_5_I_G(x) ((x) << S_RXCLK_5_I_G)
+#define F_RXCLK_5_I_G    V_RXCLK_5_I_G(1U)
+
+#define S_TXCLK_5_I_G    16
+#define V_TXCLK_5_I_G(x) ((x) << S_TXCLK_5_I_G)
+#define F_TXCLK_5_I_G    V_TXCLK_5_I_G(1U)
+
+#define S_SD_RX_CLK_AN_0_I_G    15
+#define V_SD_RX_CLK_AN_0_I_G(x) ((x) << S_SD_RX_CLK_AN_0_I_G)
+#define F_SD_RX_CLK_AN_0_I_G    V_SD_RX_CLK_AN_0_I_G(1U)
+
+#define S_SD_TX_CLK_AN_0_I_G    14
+#define V_SD_TX_CLK_AN_0_I_G(x) ((x) << S_SD_TX_CLK_AN_0_I_G)
+#define F_SD_TX_CLK_AN_0_I_G    V_SD_TX_CLK_AN_0_I_G(1U)
+
+#define S_SD_RX_CLK_AN_1_I_G    13
+#define V_SD_RX_CLK_AN_1_I_G(x) ((x) << S_SD_RX_CLK_AN_1_I_G)
+#define F_SD_RX_CLK_AN_1_I_G    V_SD_RX_CLK_AN_1_I_G(1U)
+
+#define S_SD_TX_CLK_AN_1_I_G    12
+#define V_SD_TX_CLK_AN_1_I_G(x) ((x) << S_SD_TX_CLK_AN_1_I_G)
+#define F_SD_TX_CLK_AN_1_I_G    V_SD_TX_CLK_AN_1_I_G(1U)
+
+#define S_SD_RX_CLK_AN_2_I_G    11
+#define V_SD_RX_CLK_AN_2_I_G(x) ((x) << S_SD_RX_CLK_AN_2_I_G)
+#define F_SD_RX_CLK_AN_2_I_G    V_SD_RX_CLK_AN_2_I_G(1U)
+
+#define S_SD_TX_CLK_AN_2_I_G    10
+#define V_SD_TX_CLK_AN_2_I_G(x) ((x) << S_SD_TX_CLK_AN_2_I_G)
+#define F_SD_TX_CLK_AN_2_I_G    V_SD_TX_CLK_AN_2_I_G(1U)
+
+#define S_SD_RX_CLK_AN_3_I_G    9
+#define V_SD_RX_CLK_AN_3_I_G(x) ((x) << S_SD_RX_CLK_AN_3_I_G)
+#define F_SD_RX_CLK_AN_3_I_G    V_SD_RX_CLK_AN_3_I_G(1U)
+
+#define S_SD_TX_CLK_AN_3_I_G    8
+#define V_SD_TX_CLK_AN_3_I_G(x) ((x) << S_SD_TX_CLK_AN_3_I_G)
+#define F_SD_TX_CLK_AN_3_I_G    V_SD_TX_CLK_AN_3_I_G(1U)
+
+#define S_SD_RX_CLK_AN_4_I_G    7
+#define V_SD_RX_CLK_AN_4_I_G(x) ((x) << S_SD_RX_CLK_AN_4_I_G)
+#define F_SD_RX_CLK_AN_4_I_G    V_SD_RX_CLK_AN_4_I_G(1U)
+
+#define S_SD_TX_CLK_AN_4_I_G    6
+#define V_SD_TX_CLK_AN_4_I_G(x) ((x) << S_SD_TX_CLK_AN_4_I_G)
+#define F_SD_TX_CLK_AN_4_I_G    V_SD_TX_CLK_AN_4_I_G(1U)
+
+#define S_SD_RX_CLK_AN_5_I_G    5
+#define V_SD_RX_CLK_AN_5_I_G(x) ((x) << S_SD_RX_CLK_AN_5_I_G)
+#define F_SD_RX_CLK_AN_5_I_G    V_SD_RX_CLK_AN_5_I_G(1U)
+
+#define S_SD_TX_CLK_AN_5_I_G    4
+#define V_SD_TX_CLK_AN_5_I_G(x) ((x) << S_SD_TX_CLK_AN_5_I_G)
+#define F_SD_TX_CLK_AN_5_I_G    V_SD_TX_CLK_AN_5_I_G(1U)
+
+#define S_SD_RX_CLK_AN_6_I_G    3
+#define V_SD_RX_CLK_AN_6_I_G(x) ((x) << S_SD_RX_CLK_AN_6_I_G)
+#define F_SD_RX_CLK_AN_6_I_G    V_SD_RX_CLK_AN_6_I_G(1U)
+
+#define S_SD_TX_CLK_AN_6_I_G    2
+#define V_SD_TX_CLK_AN_6_I_G(x) ((x) << S_SD_TX_CLK_AN_6_I_G)
+#define F_SD_TX_CLK_AN_6_I_G    V_SD_TX_CLK_AN_6_I_G(1U)
+
+#define S_SD_RX_CLK_AN_7_I_G    1
+#define V_SD_RX_CLK_AN_7_I_G(x) ((x) << S_SD_RX_CLK_AN_7_I_G)
+#define F_SD_RX_CLK_AN_7_I_G    V_SD_RX_CLK_AN_7_I_G(1U)
+
+#define S_SD_TX_CLK_AN_7_I_G    0
+#define V_SD_TX_CLK_AN_7_I_G(x) ((x) << S_SD_TX_CLK_AN_7_I_G)
+#define F_SD_TX_CLK_AN_7_I_G    V_SD_TX_CLK_AN_7_I_G(1U)
+
+#define A_MAC_MTIP_CLK_CTRL_2 0x38018
+
+#define S_SD_RX_CLK_0_G    31
+#define V_SD_RX_CLK_0_G(x) ((x) << S_SD_RX_CLK_0_G)
+#define F_SD_RX_CLK_0_G    V_SD_RX_CLK_0_G(1U)
+
+#define S_SD_RX_CLK_1_G    30
+#define V_SD_RX_CLK_1_G(x) ((x) << S_SD_RX_CLK_1_G)
+#define F_SD_RX_CLK_1_G    V_SD_RX_CLK_1_G(1U)
+
+#define S_SD_RX_CLK_2_G    29
+#define V_SD_RX_CLK_2_G(x) ((x) << S_SD_RX_CLK_2_G)
+#define F_SD_RX_CLK_2_G    V_SD_RX_CLK_2_G(1U)
+
+#define S_SD_RX_CLK_3_G    28
+#define V_SD_RX_CLK_3_G(x) ((x) << S_SD_RX_CLK_3_G)
+#define F_SD_RX_CLK_3_G    V_SD_RX_CLK_3_G(1U)
+
+#define S_SD_RX_CLK_4_G    27
+#define V_SD_RX_CLK_4_G(x) ((x) << S_SD_RX_CLK_4_G)
+#define F_SD_RX_CLK_4_G    V_SD_RX_CLK_4_G(1U)
+
+#define S_SD_RX_CLK_5_G    26
+#define V_SD_RX_CLK_5_G(x) ((x) << S_SD_RX_CLK_5_G)
+#define F_SD_RX_CLK_5_G    V_SD_RX_CLK_5_G(1U)
+
+#define S_SD_RX_CLK_6_G    25
+#define V_SD_RX_CLK_6_G(x) ((x) << S_SD_RX_CLK_6_G)
+#define F_SD_RX_CLK_6_G    V_SD_RX_CLK_6_G(1U)
+
+#define S_SD_RX_CLK_7_G    24
+#define V_SD_RX_CLK_7_G(x) ((x) << S_SD_RX_CLK_7_G)
+#define F_SD_RX_CLK_7_G    V_SD_RX_CLK_7_G(1U)
+
+#define S_SD_TX_CLK_0_G    23
+#define V_SD_TX_CLK_0_G(x) ((x) << S_SD_TX_CLK_0_G)
+#define F_SD_TX_CLK_0_G    V_SD_TX_CLK_0_G(1U)
+
+#define S_SD_TX_CLK_1_G    22
+#define V_SD_TX_CLK_1_G(x) ((x) << S_SD_TX_CLK_1_G)
+#define F_SD_TX_CLK_1_G    V_SD_TX_CLK_1_G(1U)
+
+#define S_SD_TX_CLK_2_G    21
+#define V_SD_TX_CLK_2_G(x) ((x) << S_SD_TX_CLK_2_G)
+#define F_SD_TX_CLK_2_G    V_SD_TX_CLK_2_G(1U)
+
+#define S_SD_TX_CLK_3_G    20
+#define V_SD_TX_CLK_3_G(x) ((x) << S_SD_TX_CLK_3_G)
+#define F_SD_TX_CLK_3_G    V_SD_TX_CLK_3_G(1U)
+
+#define S_SD_TX_CLK_4_G    19
+#define V_SD_TX_CLK_4_G(x) ((x) << S_SD_TX_CLK_4_G)
+#define F_SD_TX_CLK_4_G    V_SD_TX_CLK_4_G(1U)
+
+#define S_SD_TX_CLK_5_G    18
+#define V_SD_TX_CLK_5_G(x) ((x) << S_SD_TX_CLK_5_G)
+#define F_SD_TX_CLK_5_G    V_SD_TX_CLK_5_G(1U)
+
+#define S_SD_TX_CLK_6_G    17
+#define V_SD_TX_CLK_6_G(x) ((x) << S_SD_TX_CLK_6_G)
+#define F_SD_TX_CLK_6_G    V_SD_TX_CLK_6_G(1U)
+
+#define S_SD_TX_CLK_7_G    16
+#define V_SD_TX_CLK_7_G(x) ((x) << S_SD_TX_CLK_7_G)
+#define F_SD_TX_CLK_7_G    V_SD_TX_CLK_7_G(1U)
+
+#define S_SD_RX_CLK_AEC_0_G    15
+#define V_SD_RX_CLK_AEC_0_G(x) ((x) << S_SD_RX_CLK_AEC_0_G)
+#define F_SD_RX_CLK_AEC_0_G    V_SD_RX_CLK_AEC_0_G(1U)
+
+#define S_SD_RX_CLK_AEC_1_G    14
+#define V_SD_RX_CLK_AEC_1_G(x) ((x) << S_SD_RX_CLK_AEC_1_G)
+#define F_SD_RX_CLK_AEC_1_G    V_SD_RX_CLK_AEC_1_G(1U)
+
+#define S_SD_RX_CLK_AEC_2_G    13
+#define V_SD_RX_CLK_AEC_2_G(x) ((x) << S_SD_RX_CLK_AEC_2_G)
+#define F_SD_RX_CLK_AEC_2_G    V_SD_RX_CLK_AEC_2_G(1U)
+
+#define S_SD_RX_CLK_AEC_3_G    12
+#define V_SD_RX_CLK_AEC_3_G(x) ((x) << S_SD_RX_CLK_AEC_3_G)
+#define F_SD_RX_CLK_AEC_3_G    V_SD_RX_CLK_AEC_3_G(1U)
+
+#define S_SD_RX_CLK_AEC_4_G    11
+#define V_SD_RX_CLK_AEC_4_G(x) ((x) << S_SD_RX_CLK_AEC_4_G)
+#define F_SD_RX_CLK_AEC_4_G    V_SD_RX_CLK_AEC_4_G(1U)
+
+#define S_SD_RX_CLK_AEC_5_G    10
+#define V_SD_RX_CLK_AEC_5_G(x) ((x) << S_SD_RX_CLK_AEC_5_G)
+#define F_SD_RX_CLK_AEC_5_G    V_SD_RX_CLK_AEC_5_G(1U)
+
+#define S_SD_RX_CLK_AEC_6_G    9
+#define V_SD_RX_CLK_AEC_6_G(x) ((x) << S_SD_RX_CLK_AEC_6_G)
+#define F_SD_RX_CLK_AEC_6_G    V_SD_RX_CLK_AEC_6_G(1U)
+
+#define S_SD_RX_CLK_AEC_7_G    8
+#define V_SD_RX_CLK_AEC_7_G(x) ((x) << S_SD_RX_CLK_AEC_7_G)
+#define F_SD_RX_CLK_AEC_7_G    V_SD_RX_CLK_AEC_7_G(1U)
+
+#define S_SD_TX_CLK_AEC_0_G    7
+#define V_SD_TX_CLK_AEC_0_G(x) ((x) << S_SD_TX_CLK_AEC_0_G)
+#define F_SD_TX_CLK_AEC_0_G    V_SD_TX_CLK_AEC_0_G(1U)
+
+#define S_SD_TX_CLK_AEC_1_G    6
+#define V_SD_TX_CLK_AEC_1_G(x) ((x) << S_SD_TX_CLK_AEC_1_G)
+#define F_SD_TX_CLK_AEC_1_G    V_SD_TX_CLK_AEC_1_G(1U)
+
+#define S_SD_TX_CLK_AEC_2_G    5
+#define V_SD_TX_CLK_AEC_2_G(x) ((x) << S_SD_TX_CLK_AEC_2_G)
+#define F_SD_TX_CLK_AEC_2_G    V_SD_TX_CLK_AEC_2_G(1U)
+
+#define S_SD_TX_CLK_AEC_3_G    4
+#define V_SD_TX_CLK_AEC_3_G(x) ((x) << S_SD_TX_CLK_AEC_3_G)
+#define F_SD_TX_CLK_AEC_3_G    V_SD_TX_CLK_AEC_3_G(1U)
+
+#define S_SD_TX_CLK_AEC_4_G    3
+#define V_SD_TX_CLK_AEC_4_G(x) ((x) << S_SD_TX_CLK_AEC_4_G)
+#define F_SD_TX_CLK_AEC_4_G    V_SD_TX_CLK_AEC_4_G(1U)
+
+#define S_SD_TX_CLK_AEC_5_G    2
+#define V_SD_TX_CLK_AEC_5_G(x) ((x) << S_SD_TX_CLK_AEC_5_G)
+#define F_SD_TX_CLK_AEC_5_G    V_SD_TX_CLK_AEC_5_G(1U)
+
+#define S_SD_TX_CLK_AEC_6_G    1
+#define V_SD_TX_CLK_AEC_6_G(x) ((x) << S_SD_TX_CLK_AEC_6_G)
+#define F_SD_TX_CLK_AEC_6_G    V_SD_TX_CLK_AEC_6_G(1U)
+
+#define S_SD_TX_CLK_AEC_7_G    0
+#define V_SD_TX_CLK_AEC_7_G(x) ((x) << S_SD_TX_CLK_AEC_7_G)
+#define F_SD_TX_CLK_AEC_7_G    V_SD_TX_CLK_AEC_7_G(1U)
+
+#define A_MAC_MTIP_CLK_CTRL_3 0x3801c
+
+#define S_PCS_RX_CLK_0_G    31
+#define V_PCS_RX_CLK_0_G(x) ((x) << S_PCS_RX_CLK_0_G)
+#define F_PCS_RX_CLK_0_G    V_PCS_RX_CLK_0_G(1U)
+
+#define S_PCS_RX_CLK_1_G    30
+#define V_PCS_RX_CLK_1_G(x) ((x) << S_PCS_RX_CLK_1_G)
+#define F_PCS_RX_CLK_1_G    V_PCS_RX_CLK_1_G(1U)
+
+#define S_PCS_RX_CLK_2_G    29
+#define V_PCS_RX_CLK_2_G(x) ((x) << S_PCS_RX_CLK_2_G)
+#define F_PCS_RX_CLK_2_G    V_PCS_RX_CLK_2_G(1U)
+
+#define S_PCS_RX_CLK_3_G    28
+#define V_PCS_RX_CLK_3_G(x) ((x) << S_PCS_RX_CLK_3_G)
+#define F_PCS_RX_CLK_3_G    V_PCS_RX_CLK_3_G(1U)
+
+#define S_PCS_RX_CLK_4_G    27
+#define V_PCS_RX_CLK_4_G(x) ((x) << S_PCS_RX_CLK_4_G)
+#define F_PCS_RX_CLK_4_G    V_PCS_RX_CLK_4_G(1U)
+
+#define S_PCS_RX_CLK_5_G    26
+#define V_PCS_RX_CLK_5_G(x) ((x) << S_PCS_RX_CLK_5_G)
+#define F_PCS_RX_CLK_5_G    V_PCS_RX_CLK_5_G(1U)
+
+#define S_PCS_RX_CLK_6_G    25
+#define V_PCS_RX_CLK_6_G(x) ((x) << S_PCS_RX_CLK_6_G)
+#define F_PCS_RX_CLK_6_G    V_PCS_RX_CLK_6_G(1U)
+
+#define S_PCS_RX_CLK_7_G    24
+#define V_PCS_RX_CLK_7_G(x) ((x) << S_PCS_RX_CLK_7_G)
+#define F_PCS_RX_CLK_7_G    V_PCS_RX_CLK_7_G(1U)
+
+#define S_PCS_TX_CLK_0_G    23
+#define V_PCS_TX_CLK_0_G(x) ((x) << S_PCS_TX_CLK_0_G)
+#define F_PCS_TX_CLK_0_G    V_PCS_TX_CLK_0_G(1U)
+
+#define S_PCS_TX_CLK_1_G    22
+#define V_PCS_TX_CLK_1_G(x) ((x) << S_PCS_TX_CLK_1_G)
+#define F_PCS_TX_CLK_1_G    V_PCS_TX_CLK_1_G(1U)
+
+#define S_PCS_TX_CLK_2_G    21
+#define V_PCS_TX_CLK_2_G(x) ((x) << S_PCS_TX_CLK_2_G)
+#define F_PCS_TX_CLK_2_G    V_PCS_TX_CLK_2_G(1U)
+
+#define S_PCS_TX_CLK_3_G    20
+#define V_PCS_TX_CLK_3_G(x) ((x) << S_PCS_TX_CLK_3_G)
+#define F_PCS_TX_CLK_3_G    V_PCS_TX_CLK_3_G(1U)
+
+#define S_PCS_TX_CLK_4_G    19
+#define V_PCS_TX_CLK_4_G(x) ((x) << S_PCS_TX_CLK_4_G)
+#define F_PCS_TX_CLK_4_G    V_PCS_TX_CLK_4_G(1U)
+
+#define S_PCS_TX_CLK_5_G    18
+#define V_PCS_TX_CLK_5_G(x) ((x) << S_PCS_TX_CLK_5_G)
+#define F_PCS_TX_CLK_5_G    V_PCS_TX_CLK_5_G(1U)
+
+#define S_PCS_TX_CLK_6_G    17
+#define V_PCS_TX_CLK_6_G(x) ((x) << S_PCS_TX_CLK_6_G)
+#define F_PCS_TX_CLK_6_G    V_PCS_TX_CLK_6_G(1U)
+
+#define S_PCS_TX_CLK_7_G    16
+#define V_PCS_TX_CLK_7_G(x) ((x) << S_PCS_TX_CLK_7_G)
+#define F_PCS_TX_CLK_7_G    V_PCS_TX_CLK_7_G(1U)
+
+#define S_SD_RX_CLK_EN_0    15
+#define V_SD_RX_CLK_EN_0(x) ((x) << S_SD_RX_CLK_EN_0)
+#define F_SD_RX_CLK_EN_0    V_SD_RX_CLK_EN_0(1U)
+
+#define S_SD_RX_CLK_EN_1    14
+#define V_SD_RX_CLK_EN_1(x) ((x) << S_SD_RX_CLK_EN_1)
+#define F_SD_RX_CLK_EN_1    V_SD_RX_CLK_EN_1(1U)
+
+#define S_SD_RX_CLK_EN_2    13
+#define V_SD_RX_CLK_EN_2(x) ((x) << S_SD_RX_CLK_EN_2)
+#define F_SD_RX_CLK_EN_2    V_SD_RX_CLK_EN_2(1U)
+
+#define S_SD_RX_CLK_EN_3    12
+#define V_SD_RX_CLK_EN_3(x) ((x) << S_SD_RX_CLK_EN_3)
+#define F_SD_RX_CLK_EN_3    V_SD_RX_CLK_EN_3(1U)
+
+#define S_SD_RX_CLK_EN_4    11
+#define V_SD_RX_CLK_EN_4(x) ((x) << S_SD_RX_CLK_EN_4)
+#define F_SD_RX_CLK_EN_4    V_SD_RX_CLK_EN_4(1U)
+
+#define S_SD_RX_CLK_EN_5    10
+#define V_SD_RX_CLK_EN_5(x) ((x) << S_SD_RX_CLK_EN_5)
+#define F_SD_RX_CLK_EN_5    V_SD_RX_CLK_EN_5(1U)
+
+#define S_SD_RX_CLK_EN_6    9
+#define V_SD_RX_CLK_EN_6(x) ((x) << S_SD_RX_CLK_EN_6)
+#define F_SD_RX_CLK_EN_6    V_SD_RX_CLK_EN_6(1U)
+
+#define S_SD_RX_CLK_EN_7    8
+#define V_SD_RX_CLK_EN_7(x) ((x) << S_SD_RX_CLK_EN_7)
+#define F_SD_RX_CLK_EN_7    V_SD_RX_CLK_EN_7(1U)
+
+#define S_SD_TX_CLK_EN_0    7
+#define V_SD_TX_CLK_EN_0(x) ((x) << S_SD_TX_CLK_EN_0)
+#define F_SD_TX_CLK_EN_0    V_SD_TX_CLK_EN_0(1U)
+
+#define S_SD_TX_CLK_EN_1    6
+#define V_SD_TX_CLK_EN_1(x) ((x) << S_SD_TX_CLK_EN_1)
+#define F_SD_TX_CLK_EN_1    V_SD_TX_CLK_EN_1(1U)
+
+#define S_SD_TX_CLK_EN_2    5
+#define V_SD_TX_CLK_EN_2(x) ((x) << S_SD_TX_CLK_EN_2)
+#define F_SD_TX_CLK_EN_2    V_SD_TX_CLK_EN_2(1U)
+
+#define S_SD_TX_CLK_EN_3    4
+#define V_SD_TX_CLK_EN_3(x) ((x) << S_SD_TX_CLK_EN_3)
+#define F_SD_TX_CLK_EN_3    V_SD_TX_CLK_EN_3(1U)
+
+#define S_SD_TX_CLK_EN_4    3
+#define V_SD_TX_CLK_EN_4(x) ((x) << S_SD_TX_CLK_EN_4)
+#define F_SD_TX_CLK_EN_4    V_SD_TX_CLK_EN_4(1U)
+
+#define S_SD_TX_CLK_EN_5    2
+#define V_SD_TX_CLK_EN_5(x) ((x) << S_SD_TX_CLK_EN_5)
+#define F_SD_TX_CLK_EN_5    V_SD_TX_CLK_EN_5(1U)
+
+#define S_SD_TX_CLK_EN_6    1
+#define V_SD_TX_CLK_EN_6(x) ((x) << S_SD_TX_CLK_EN_6)
+#define F_SD_TX_CLK_EN_6    V_SD_TX_CLK_EN_6(1U)
+
+#define S_SD_TX_CLK_EN_7    0
+#define V_SD_TX_CLK_EN_7(x) ((x) << S_SD_TX_CLK_EN_7)
+#define F_SD_TX_CLK_EN_7    V_SD_TX_CLK_EN_7(1U)
+
+#define A_MAC_MTIP_CLK_CTRL_4 0x38020
+
+#define S_SGMII_TX_CLK_0_G    7
+#define V_SGMII_TX_CLK_0_G(x) ((x) << S_SGMII_TX_CLK_0_G)
+#define F_SGMII_TX_CLK_0_G    V_SGMII_TX_CLK_0_G(1U)
+
+#define S_SGMII_TX_CLK_1_G    6
+#define V_SGMII_TX_CLK_1_G(x) ((x) << S_SGMII_TX_CLK_1_G)
+#define F_SGMII_TX_CLK_1_G    V_SGMII_TX_CLK_1_G(1U)
+
+#define S_SGMII_TX_CLK_2_G    5
+#define V_SGMII_TX_CLK_2_G(x) ((x) << S_SGMII_TX_CLK_2_G)
+#define F_SGMII_TX_CLK_2_G    V_SGMII_TX_CLK_2_G(1U)
+
+#define S_SGMII_TX_CLK_3_G    4
+#define V_SGMII_TX_CLK_3_G(x) ((x) << S_SGMII_TX_CLK_3_G)
+#define F_SGMII_TX_CLK_3_G    V_SGMII_TX_CLK_3_G(1U)
+
+#define S_SGMII_RX_CLK_0_G    3
+#define V_SGMII_RX_CLK_0_G(x) ((x) << S_SGMII_RX_CLK_0_G)
+#define F_SGMII_RX_CLK_0_G    V_SGMII_RX_CLK_0_G(1U)
+
+#define S_SGMII_RX_CLK_1_G    2
+#define V_SGMII_RX_CLK_1_G(x) ((x) << S_SGMII_RX_CLK_1_G)
+#define F_SGMII_RX_CLK_1_G    V_SGMII_RX_CLK_1_G(1U)
+
+#define S_SGMII_RX_CLK_2_G    1
+#define V_SGMII_RX_CLK_2_G(x) ((x) << S_SGMII_RX_CLK_2_G)
+#define F_SGMII_RX_CLK_2_G    V_SGMII_RX_CLK_2_G(1U)
+
+#define S_SGMII_RX_CLK_3_G    0
+#define V_SGMII_RX_CLK_3_G(x) ((x) << S_SGMII_RX_CLK_3_G)
+#define F_SGMII_RX_CLK_3_G    V_SGMII_RX_CLK_3_G(1U)
+
+#define A_MAC_PCS_CONFIG_0 0x38024
+
+#define S_KP_MODE_IN    24
+#define M_KP_MODE_IN    0xffU
+#define V_KP_MODE_IN(x) ((x) << S_KP_MODE_IN)
+#define G_KP_MODE_IN(x) (((x) >> S_KP_MODE_IN) & M_KP_MODE_IN)
+
+#define S_FEC91_ENA_IN    16
+#define M_FEC91_ENA_IN    0xffU
+#define V_FEC91_ENA_IN(x) ((x) << S_FEC91_ENA_IN)
+#define G_FEC91_ENA_IN(x) (((x) >> S_FEC91_ENA_IN) & M_FEC91_ENA_IN)
+
+#define S_SD_8X    8
+#define M_SD_8X    0xffU
+#define V_SD_8X(x) ((x) << S_SD_8X)
+#define G_SD_8X(x) (((x) >> S_SD_8X) & M_SD_8X)
+
+#define S_SD_N2    0
+#define M_SD_N2    0xffU
+#define V_SD_N2(x) ((x) << S_SD_N2)
+#define G_SD_N2(x) (((x) >> S_SD_N2) & M_SD_N2)
+
+#define A_MAC_PCS_CONFIG_1 0x38028
+
+#define S_FAST_1LANE_MODE    24
+#define M_FAST_1LANE_MODE    0xffU
+#define V_FAST_1LANE_MODE(x) ((x) << S_FAST_1LANE_MODE)
+#define G_FAST_1LANE_MODE(x) (((x) >> S_FAST_1LANE_MODE) & M_FAST_1LANE_MODE)
+
+#define S_PACER_10G    16
+#define M_PACER_10G    0xffU
+#define V_PACER_10G(x) ((x) << S_PACER_10G)
+#define G_PACER_10G(x) (((x) >> S_PACER_10G) & M_PACER_10G)
+
+#define S_PCS400_ENA_IN    14
+#define M_PCS400_ENA_IN    0x3U
+#define V_PCS400_ENA_IN(x) ((x) << S_PCS400_ENA_IN)
+#define G_PCS400_ENA_IN(x) (((x) >> S_PCS400_ENA_IN) & M_PCS400_ENA_IN)
+
+#define S_MODE40_ENA_IN4    13
+#define V_MODE40_ENA_IN4(x) ((x) << S_MODE40_ENA_IN4)
+#define F_MODE40_ENA_IN4    V_MODE40_ENA_IN4(1U)
+
+#define S_MODE40_ENA_IN0    12
+#define V_MODE40_ENA_IN0(x) ((x) << S_MODE40_ENA_IN0)
+#define F_MODE40_ENA_IN0    V_MODE40_ENA_IN0(1U)
+
+#define S_PCS100_ENA_IN6    11
+#define V_PCS100_ENA_IN6(x) ((x) << S_PCS100_ENA_IN6)
+#define F_PCS100_ENA_IN6    V_PCS100_ENA_IN6(1U)
+
+#define S_PCS100_ENA_IN4    10
+#define V_PCS100_ENA_IN4(x) ((x) << S_PCS100_ENA_IN4)
+#define F_PCS100_ENA_IN4    V_PCS100_ENA_IN4(1U)
+
+#define S_PCS100_ENA_IN2    9
+#define V_PCS100_ENA_IN2(x) ((x) << S_PCS100_ENA_IN2)
+#define F_PCS100_ENA_IN2    V_PCS100_ENA_IN2(1U)
+
+#define S_PCS100_ENA_IN0    8
+#define V_PCS100_ENA_IN0(x) ((x) << S_PCS100_ENA_IN0)
+#define F_PCS100_ENA_IN0    V_PCS100_ENA_IN0(1U)
+
+#define S_RXLAUI_ENA_IN6    7
+#define V_RXLAUI_ENA_IN6(x) ((x) << S_RXLAUI_ENA_IN6)
+#define F_RXLAUI_ENA_IN6    V_RXLAUI_ENA_IN6(1U)
+
+#define S_RXLAUI_ENA_IN4    6
+#define V_RXLAUI_ENA_IN4(x) ((x) << S_RXLAUI_ENA_IN4)
+#define F_RXLAUI_ENA_IN4    V_RXLAUI_ENA_IN4(1U)
+
+#define S_RXLAUI_ENA_IN2    5
+#define V_RXLAUI_ENA_IN2(x) ((x) << S_RXLAUI_ENA_IN2)
+#define F_RXLAUI_ENA_IN2    V_RXLAUI_ENA_IN2(1U)
+
+#define S_RXLAUI_ENA_IN0    4
+#define V_RXLAUI_ENA_IN0(x) ((x) << S_RXLAUI_ENA_IN0)
+#define F_RXLAUI_ENA_IN0    V_RXLAUI_ENA_IN0(1U)
+
+#define S_FEC91_LANE_IN6    3
+#define V_FEC91_LANE_IN6(x) ((x) << S_FEC91_LANE_IN6)
+#define F_FEC91_LANE_IN6    V_FEC91_LANE_IN6(1U)
+
+#define S_FEC91_LANE_IN4    2
+#define V_FEC91_LANE_IN4(x) ((x) << S_FEC91_LANE_IN4)
+#define F_FEC91_LANE_IN4    V_FEC91_LANE_IN4(1U)
+
+#define S_FEC91_LANE_IN2    1
+#define V_FEC91_LANE_IN2(x) ((x) << S_FEC91_LANE_IN2)
+#define F_FEC91_LANE_IN2    V_FEC91_LANE_IN2(1U)
+
+#define S_FEC91_LANE_IN0    0
+#define V_FEC91_LANE_IN0(x) ((x) << S_FEC91_LANE_IN0)
+#define F_FEC91_LANE_IN0    V_FEC91_LANE_IN0(1U)
+
+#define A_MAC_PCS_CONFIG_2 0x3802c
+
+#define S_SGPCS_EN_3    29
+#define V_SGPCS_EN_3(x) ((x) << S_SGPCS_EN_3)
+#define F_SGPCS_EN_3    V_SGPCS_EN_3(1U)
+
+#define S_SGPCS_EN_2    28
+#define V_SGPCS_EN_2(x) ((x) << S_SGPCS_EN_2)
+#define F_SGPCS_EN_2    V_SGPCS_EN_2(1U)
+
+#define S_SGPCS_EN_1    27
+#define V_SGPCS_EN_1(x) ((x) << S_SGPCS_EN_1)
+#define F_SGPCS_EN_1    V_SGPCS_EN_1(1U)
+
+#define S_SGPCS_EN_0    26
+#define V_SGPCS_EN_0(x) ((x) << S_SGPCS_EN_0)
+#define F_SGPCS_EN_0    V_SGPCS_EN_0(1U)
+
+#define S_CFG_CLOCK_RATE    22
+#define M_CFG_CLOCK_RATE    0xfU
+#define V_CFG_CLOCK_RATE(x) ((x) << S_CFG_CLOCK_RATE)
+#define G_CFG_CLOCK_RATE(x) (((x) >> S_CFG_CLOCK_RATE) & M_CFG_CLOCK_RATE)
+
+#define S_FEC_ERR_ENA    14
+#define M_FEC_ERR_ENA    0xffU
+#define V_FEC_ERR_ENA(x) ((x) << S_FEC_ERR_ENA)
+#define G_FEC_ERR_ENA(x) (((x) >> S_FEC_ERR_ENA) & M_FEC_ERR_ENA)
+
+#define S_FEC_ENA    6
+#define M_FEC_ENA    0xffU
+#define V_FEC_ENA(x) ((x) << S_FEC_ENA)
+#define G_FEC_ENA(x) (((x) >> S_FEC_ENA) & M_FEC_ENA)
+
+#define S_PCS001_TX_AM_SF    3
+#define M_PCS001_TX_AM_SF    0x7U
+#define V_PCS001_TX_AM_SF(x) ((x) << S_PCS001_TX_AM_SF)
+#define G_PCS001_TX_AM_SF(x) (((x) >> S_PCS001_TX_AM_SF) & M_PCS001_TX_AM_SF)
+
+#define S_PCS000_TX_AM_SF    0
+#define M_PCS000_TX_AM_SF    0x7U
+#define V_PCS000_TX_AM_SF(x) ((x) << S_PCS000_TX_AM_SF)
+#define G_PCS000_TX_AM_SF(x) (((x) >> S_PCS000_TX_AM_SF) & M_PCS000_TX_AM_SF)
+
+#define A_MAC_PCS_STATUS_0 0x38030
+
+#define S_PCS000_ALIGN_LOCK    30
+#define M_PCS000_ALIGN_LOCK    0x3U
+#define V_PCS000_ALIGN_LOCK(x) ((x) << S_PCS000_ALIGN_LOCK)
+#define G_PCS000_ALIGN_LOCK(x) (((x) >> S_PCS000_ALIGN_LOCK) & M_PCS000_ALIGN_LOCK)
+
+#define S_PCS000_HI_SER    28
+#define M_PCS000_HI_SER    0x3U
+#define V_PCS000_HI_SER(x) ((x) << S_PCS000_HI_SER)
+#define G_PCS000_HI_SER(x) (((x) >> S_PCS000_HI_SER) & M_PCS000_HI_SER)
+
+#define S_BER_TIMER_DONE    20
+#define M_BER_TIMER_DONE    0xffU
+#define V_BER_TIMER_DONE(x) ((x) << S_BER_TIMER_DONE)
+#define G_BER_TIMER_DONE(x) (((x) >> S_BER_TIMER_DONE) & M_BER_TIMER_DONE)
+
+#define S_T7_AMPS_LOCK    4
+#define M_T7_AMPS_LOCK    0xffffU
+#define V_T7_AMPS_LOCK(x) ((x) << S_T7_AMPS_LOCK)
+#define G_T7_AMPS_LOCK(x) (((x) >> S_T7_AMPS_LOCK) & M_T7_AMPS_LOCK)
+
+#define S_T7_ALIGN_DONE    0
+#define M_T7_ALIGN_DONE    0xfU
+#define V_T7_ALIGN_DONE(x) ((x) << S_T7_ALIGN_DONE)
+#define G_T7_ALIGN_DONE(x) (((x) >> S_T7_ALIGN_DONE) & M_T7_ALIGN_DONE)
+
+#define A_MAC_PCS_STATUS_1 0x38034
+#define A_MAC_PCS_STATUS_2 0x38038
+
+#define S_RSFEC_ALIGNED    24
+#define M_RSFEC_ALIGNED    0xffU
+#define V_RSFEC_ALIGNED(x) ((x) << S_RSFEC_ALIGNED)
+#define G_RSFEC_ALIGNED(x) (((x) >> S_RSFEC_ALIGNED) & M_RSFEC_ALIGNED)
+
+#define S_T7_FEC_LOCKED    8
+#define M_T7_FEC_LOCKED    0xffffU
+#define V_T7_FEC_LOCKED(x) ((x) << S_T7_FEC_LOCKED)
+#define G_T7_FEC_LOCKED(x) (((x) >> S_T7_FEC_LOCKED) & M_T7_FEC_LOCKED)
+
+#define S_T7_BLOCK_LOCK    0
+#define M_T7_BLOCK_LOCK    0xffU
+#define V_T7_BLOCK_LOCK(x) ((x) << S_T7_BLOCK_LOCK)
+#define G_T7_BLOCK_LOCK(x) (((x) >> S_T7_BLOCK_LOCK) & M_T7_BLOCK_LOCK)
+
+#define A_MAC_PCS_STATUS_3 0x3803c
+
+#define S_FEC_NCERR    16
+#define M_FEC_NCERR    0xffffU
+#define V_FEC_NCERR(x) ((x) << S_FEC_NCERR)
+#define G_FEC_NCERR(x) (((x) >> S_FEC_NCERR) & M_FEC_NCERR)
+
+#define S_FEC_CERR    0
+#define M_FEC_CERR    0xffffU
+#define V_FEC_CERR(x) ((x) << S_FEC_CERR)
+#define G_FEC_CERR(x) (((x) >> S_FEC_CERR) & M_FEC_CERR)
+
+#define A_MAC_PCS_STATUS_4 0x38040
+
+#define S_MAC1_RES_SPEED    23
+#define M_MAC1_RES_SPEED    0xffU
+#define V_MAC1_RES_SPEED(x) ((x) << S_MAC1_RES_SPEED)
+#define G_MAC1_RES_SPEED(x) (((x) >> S_MAC1_RES_SPEED) & M_MAC1_RES_SPEED)
+
+#define S_MAC0_RES_SPEED    14
+#define M_MAC0_RES_SPEED    0xffU
+#define V_MAC0_RES_SPEED(x) ((x) << S_MAC0_RES_SPEED)
+#define G_MAC0_RES_SPEED(x) (((x) >> S_MAC0_RES_SPEED) & M_MAC0_RES_SPEED)
+
+#define S_PCS400_ENA_IN_REF    12
+#define M_PCS400_ENA_IN_REF    0x3U
+#define V_PCS400_ENA_IN_REF(x) ((x) << S_PCS400_ENA_IN_REF)
+#define G_PCS400_ENA_IN_REF(x) (((x) >> S_PCS400_ENA_IN_REF) & M_PCS400_ENA_IN_REF)
+
+#define S_PCS000_DEGRADE_SER    10
+#define M_PCS000_DEGRADE_SER    0x3U
+#define V_PCS000_DEGRADE_SER(x) ((x) << S_PCS000_DEGRADE_SER)
+#define G_PCS000_DEGRADE_SER(x) (((x) >> S_PCS000_DEGRADE_SER) & M_PCS000_DEGRADE_SER)
+
+#define S_P4X_SIGNAL_OK    8
+#define M_P4X_SIGNAL_OK    0x3U
+#define V_P4X_SIGNAL_OK(x) ((x) << S_P4X_SIGNAL_OK)
+#define G_P4X_SIGNAL_OK(x) (((x) >> S_P4X_SIGNAL_OK) & M_P4X_SIGNAL_OK)
+
+#define S_MODE200_IND_REF    7
+#define V_MODE200_IND_REF(x) ((x) << S_MODE200_IND_REF)
+#define F_MODE200_IND_REF    V_MODE200_IND_REF(1U)
+
+#define S_MODE200_8X26_IND_REF    6
+#define V_MODE200_8X26_IND_REF(x) ((x) << S_MODE200_8X26_IND_REF)
+#define F_MODE200_8X26_IND_REF    V_MODE200_8X26_IND_REF(1U)
+
+#define S_PCS001_RX_AM_SF    3
+#define M_PCS001_RX_AM_SF    0x7U
+#define V_PCS001_RX_AM_SF(x) ((x) << S_PCS001_RX_AM_SF)
+#define G_PCS001_RX_AM_SF(x) (((x) >> S_PCS001_RX_AM_SF) & M_PCS001_RX_AM_SF)
+
+#define S_PCS000_RX_AM_SF    0
+#define M_PCS000_RX_AM_SF    0x7U
+#define V_PCS000_RX_AM_SF(x) ((x) << S_PCS000_RX_AM_SF)
+#define G_PCS000_RX_AM_SF(x) (((x) >> S_PCS000_RX_AM_SF) & M_PCS000_RX_AM_SF)
+
+#define A_MAC_PCS_STATUS_5 0x38044
+
+#define S_MAC5_RES_SPEED    24
+#define M_MAC5_RES_SPEED    0xffU
+#define V_MAC5_RES_SPEED(x) ((x) << S_MAC5_RES_SPEED)
+#define G_MAC5_RES_SPEED(x) (((x) >> S_MAC5_RES_SPEED) & M_MAC5_RES_SPEED)
+
+#define S_MAC4_RES_SPEED    16
+#define M_MAC4_RES_SPEED    0xffU
+#define V_MAC4_RES_SPEED(x) ((x) << S_MAC4_RES_SPEED)
+#define G_MAC4_RES_SPEED(x) (((x) >> S_MAC4_RES_SPEED) & M_MAC4_RES_SPEED)
+
+#define S_MAC3_RES_SPEED    8
+#define M_MAC3_RES_SPEED    0xffU
+#define V_MAC3_RES_SPEED(x) ((x) << S_MAC3_RES_SPEED)
+#define G_MAC3_RES_SPEED(x) (((x) >> S_MAC3_RES_SPEED) & M_MAC3_RES_SPEED)
+
+#define S_MAC2_RES_SPEED    0
+#define M_MAC2_RES_SPEED    0xffU
+#define V_MAC2_RES_SPEED(x) ((x) << S_MAC2_RES_SPEED)
+#define G_MAC2_RES_SPEED(x) (((x) >> S_MAC2_RES_SPEED) & M_MAC2_RES_SPEED)
+
+#define A_MAC_PCS_STATUS_6 0x38048
+
+#define S_MARKER_INS_CNT_100_00    16
+#define M_MARKER_INS_CNT_100_00    0x7fffU
+#define V_MARKER_INS_CNT_100_00(x) ((x) << S_MARKER_INS_CNT_100_00)
+#define G_MARKER_INS_CNT_100_00(x) (((x) >> S_MARKER_INS_CNT_100_00) & M_MARKER_INS_CNT_100_00)
+
+#define S_MAC7_RES_SPEED    8
+#define M_MAC7_RES_SPEED    0xffU
+#define V_MAC7_RES_SPEED(x) ((x) << S_MAC7_RES_SPEED)
+#define G_MAC7_RES_SPEED(x) (((x) >> S_MAC7_RES_SPEED) & M_MAC7_RES_SPEED)
+
+#define S_MAC6_RES_SPEED    0
+#define M_MAC6_RES_SPEED    0xffU
+#define V_MAC6_RES_SPEED(x) ((x) << S_MAC6_RES_SPEED)
+#define G_MAC6_RES_SPEED(x) (((x) >> S_MAC6_RES_SPEED) & M_MAC6_RES_SPEED)
+
+#define A_MAC_PCS_STATUS_7 0x3804c
+
+#define S_PCS000_LINK_STATUS    30
+#define M_PCS000_LINK_STATUS    0x3U
+#define V_PCS000_LINK_STATUS(x) ((x) << S_PCS000_LINK_STATUS)
+#define G_PCS000_LINK_STATUS(x) (((x) >> S_PCS000_LINK_STATUS) & M_PCS000_LINK_STATUS)
+
+#define S_MARKER_INS_CNT_100_02    15
+#define M_MARKER_INS_CNT_100_02    0x7fffU
+#define V_MARKER_INS_CNT_100_02(x) ((x) << S_MARKER_INS_CNT_100_02)
+#define G_MARKER_INS_CNT_100_02(x) (((x) >> S_MARKER_INS_CNT_100_02) & M_MARKER_INS_CNT_100_02)
+
+#define S_MARKER_INS_CNT_100_01    0
+#define M_MARKER_INS_CNT_100_01    0x7fffU
+#define V_MARKER_INS_CNT_100_01(x) ((x) << S_MARKER_INS_CNT_100_01)
+#define G_MARKER_INS_CNT_100_01(x) (((x) >> S_MARKER_INS_CNT_100_01) & M_MARKER_INS_CNT_100_01)
+
+#define A_MAC_PCS_STATUS_8 0x38050
+
+#define S_MARKER_INS_CNT_25_1    15
+#define M_MARKER_INS_CNT_25_1    0xffffU
+#define V_MARKER_INS_CNT_25_1(x) ((x) << S_MARKER_INS_CNT_25_1)
+#define G_MARKER_INS_CNT_25_1(x) (((x) >> S_MARKER_INS_CNT_25_1) & M_MARKER_INS_CNT_25_1)
+
+#define S_MARKER_INS_CNT_100_03    0
+#define M_MARKER_INS_CNT_100_03    0x7fffU
+#define V_MARKER_INS_CNT_100_03(x) ((x) << S_MARKER_INS_CNT_100_03)
+#define G_MARKER_INS_CNT_100_03(x) (((x) >> S_MARKER_INS_CNT_100_03) & M_MARKER_INS_CNT_100_03)
+
+#define A_MAC_PCS_STATUS_9 0x38054
+
+#define S_MARKER_INS_CNT_25_5    16
+#define M_MARKER_INS_CNT_25_5    0xffffU
+#define V_MARKER_INS_CNT_25_5(x) ((x) << S_MARKER_INS_CNT_25_5)
+#define G_MARKER_INS_CNT_25_5(x) (((x) >> S_MARKER_INS_CNT_25_5) & M_MARKER_INS_CNT_25_5)
+
+#define S_MARKER_INS_CNT_25_3    0
+#define M_MARKER_INS_CNT_25_3    0xffffU
+#define V_MARKER_INS_CNT_25_3(x) ((x) << S_MARKER_INS_CNT_25_3)
+#define G_MARKER_INS_CNT_25_3(x) (((x) >> S_MARKER_INS_CNT_25_3) & M_MARKER_INS_CNT_25_3)
+
+#define A_MAC_PCS_STATUS_10 0x38058
+
+#define S_MARKER_INS_CNT_25_50_2    16
+#define M_MARKER_INS_CNT_25_50_2    0xffffU
+#define V_MARKER_INS_CNT_25_50_2(x) ((x) << S_MARKER_INS_CNT_25_50_2)
+#define G_MARKER_INS_CNT_25_50_2(x) (((x) >> S_MARKER_INS_CNT_25_50_2) & M_MARKER_INS_CNT_25_50_2)
+
+#define S_MARKER_INS_CNT_25_50_0    0
+#define M_MARKER_INS_CNT_25_50_0    0xffffU
+#define V_MARKER_INS_CNT_25_50_0(x) ((x) << S_MARKER_INS_CNT_25_50_0)
+#define G_MARKER_INS_CNT_25_50_0(x) (((x) >> S_MARKER_INS_CNT_25_50_0) & M_MARKER_INS_CNT_25_50_0)
+
+#define A_MAC_PCS_STATUS_11 0x3805c
+
+#define S_MARKER_INS_CNT_25_50_6    16
+#define M_MARKER_INS_CNT_25_50_6    0xffffU
+#define V_MARKER_INS_CNT_25_50_6(x) ((x) << S_MARKER_INS_CNT_25_50_6)
+#define G_MARKER_INS_CNT_25_50_6(x) (((x) >> S_MARKER_INS_CNT_25_50_6) & M_MARKER_INS_CNT_25_50_6)
+
+#define S_MARKER_INS_CNT_25_50_4    0
+#define M_MARKER_INS_CNT_25_50_4    0xffffU
+#define V_MARKER_INS_CNT_25_50_4(x) ((x) << S_MARKER_INS_CNT_25_50_4)
+#define G_MARKER_INS_CNT_25_50_4(x) (((x) >> S_MARKER_INS_CNT_25_50_4) & M_MARKER_INS_CNT_25_50_4)
+
+#define A_MAC_PCS_STATUS_12 0x38060
+
+#define S_T7_LINK_STATUS    24
+#define M_T7_LINK_STATUS    0xffU
+#define V_T7_LINK_STATUS(x) ((x) << S_T7_LINK_STATUS)
+#define G_T7_LINK_STATUS(x) (((x) >> S_T7_LINK_STATUS) & M_T7_LINK_STATUS)
+
+#define S_T7_HI_BER    16
+#define M_T7_HI_BER    0xffU
+#define V_T7_HI_BER(x) ((x) << S_T7_HI_BER)
+#define G_T7_HI_BER(x) (((x) >> S_T7_HI_BER) & M_T7_HI_BER)
+
+#define S_MARKER_INS_CNT_25_7    0
+#define M_MARKER_INS_CNT_25_7    0xffffU
+#define V_MARKER_INS_CNT_25_7(x) ((x) << S_MARKER_INS_CNT_25_7)
+#define G_MARKER_INS_CNT_25_7(x) (((x) >> S_MARKER_INS_CNT_25_7) & M_MARKER_INS_CNT_25_7)
+
+#define A_MAC_MAC200G400G_0_CONFIG_0 0x38064
+#define A_MAC_MAC200G400G_0_CONFIG_1 0x38068
+
+#define S_FF_TX_CRC_OVR    11
+#define V_FF_TX_CRC_OVR(x) ((x) << S_FF_TX_CRC_OVR)
+#define F_FF_TX_CRC_OVR    V_FF_TX_CRC_OVR(1U)
+
+#define S_TX_SMHOLD    2
+#define V_TX_SMHOLD(x) ((x) << S_TX_SMHOLD)
+#define F_TX_SMHOLD    V_TX_SMHOLD(1U)
+
+#define A_MAC_MAC200G400G_0_CONFIG_2 0x3806c
+#define A_MAC_MAC200G400G_0_CONFIG_3 0x38070
+#define A_MAC_MAC200G400G_0_CONFIG_4 0x38074
+
+#define S_FRC_DELTA    0
+#define M_FRC_DELTA    0xffffU
+#define V_FRC_DELTA(x) ((x) << S_FRC_DELTA)
+#define G_FRC_DELTA(x) (((x) >> S_FRC_DELTA) & M_FRC_DELTA)
+
+#define A_MAC_MAC200G400G_0_STATUS 0x38078
+
+#define S_T7_LOOP_ENA    4
+#define V_T7_LOOP_ENA(x) ((x) << S_T7_LOOP_ENA)
+#define F_T7_LOOP_ENA    V_T7_LOOP_ENA(1U)
+
+#define S_T7_LOC_FAULT    3
+#define V_T7_LOC_FAULT(x) ((x) << S_T7_LOC_FAULT)
+#define F_T7_LOC_FAULT    V_T7_LOC_FAULT(1U)
+
+#define S_FRM_DROP    2
+#define V_FRM_DROP(x) ((x) << S_FRM_DROP)
+#define F_FRM_DROP    V_FRM_DROP(1U)
+
+#define S_FF_TX_CREDIT    1
+#define V_FF_TX_CREDIT(x) ((x) << S_FF_TX_CREDIT)
+#define F_FF_TX_CREDIT    V_FF_TX_CREDIT(1U)
+
+#define A_MAC_MAC200G400G_1_CONFIG_0 0x3807c
+#define A_MAC_MAC200G400G_1_CONFIG_1 0x38080
+#define A_MAC_MAC200G400G_1_CONFIG_2 0x38084
+#define A_MAC_MAC200G400G_1_CONFIG_3 0x38088
+#define A_MAC_MAC200G400G_1_CONFIG_4 0x3808c
+#define A_MAC_MAC200G400G_1_STATUS 0x38090
+#define A_MAC_AN_CFG_0 0x38094
+
+#define S_T7_AN_DATA_CTL    24
+#define M_T7_AN_DATA_CTL    0xffU
+#define V_T7_AN_DATA_CTL(x) ((x) << S_T7_AN_DATA_CTL)
+#define G_T7_AN_DATA_CTL(x) (((x) >> S_T7_AN_DATA_CTL) & M_T7_AN_DATA_CTL)
+
+#define S_T7_AN_ENA    16
+#define M_T7_AN_ENA    0xffU
+#define V_T7_AN_ENA(x) ((x) << S_T7_AN_ENA)
+#define G_T7_AN_ENA(x) (((x) >> S_T7_AN_ENA) & M_T7_AN_ENA)
+
+#define A_MAC_AN_CFG_1 0x38098
+
+#define S_AN_DIS_TIMER_AN_7    7
+#define V_AN_DIS_TIMER_AN_7(x) ((x) << S_AN_DIS_TIMER_AN_7)
+#define F_AN_DIS_TIMER_AN_7    V_AN_DIS_TIMER_AN_7(1U)
+
+#define S_AN_DIS_TIMER_AN_6    6
+#define V_AN_DIS_TIMER_AN_6(x) ((x) << S_AN_DIS_TIMER_AN_6)
+#define F_AN_DIS_TIMER_AN_6    V_AN_DIS_TIMER_AN_6(1U)
+
+#define S_AN_DIS_TIMER_AN_5    5
+#define V_AN_DIS_TIMER_AN_5(x) ((x) << S_AN_DIS_TIMER_AN_5)
+#define F_AN_DIS_TIMER_AN_5    V_AN_DIS_TIMER_AN_5(1U)
+
+#define S_AN_DIS_TIMER_AN_4    4
+#define V_AN_DIS_TIMER_AN_4(x) ((x) << S_AN_DIS_TIMER_AN_4)
+#define F_AN_DIS_TIMER_AN_4    V_AN_DIS_TIMER_AN_4(1U)
+
+#define S_AN_DIS_TIMER_AN_3    3
+#define V_AN_DIS_TIMER_AN_3(x) ((x) << S_AN_DIS_TIMER_AN_3)
+#define F_AN_DIS_TIMER_AN_3    V_AN_DIS_TIMER_AN_3(1U)
+
+#define S_AN_DIS_TIMER_AN_2    2
+#define V_AN_DIS_TIMER_AN_2(x) ((x) << S_AN_DIS_TIMER_AN_2)
+#define F_AN_DIS_TIMER_AN_2    V_AN_DIS_TIMER_AN_2(1U)
+
+#define S_AN_DIS_TIMER_AN_1    1
+#define V_AN_DIS_TIMER_AN_1(x) ((x) << S_AN_DIS_TIMER_AN_1)
+#define F_AN_DIS_TIMER_AN_1    V_AN_DIS_TIMER_AN_1(1U)
+
+#define S_AN_DIS_TIMER_AN_0    0
+#define V_AN_DIS_TIMER_AN_0(x) ((x) << S_AN_DIS_TIMER_AN_0)
+#define F_AN_DIS_TIMER_AN_0    V_AN_DIS_TIMER_AN_0(1U)
+
+#define A_MAC_AN_SERDES25G_ENA 0x3809c
+
+#define S_AN_SD25_TX_ENA_7    15
+#define V_AN_SD25_TX_ENA_7(x) ((x) << S_AN_SD25_TX_ENA_7)
+#define F_AN_SD25_TX_ENA_7    V_AN_SD25_TX_ENA_7(1U)
+
+#define S_AN_SD25_TX_ENA_6    14
+#define V_AN_SD25_TX_ENA_6(x) ((x) << S_AN_SD25_TX_ENA_6)
+#define F_AN_SD25_TX_ENA_6    V_AN_SD25_TX_ENA_6(1U)
+
+#define S_AN_SD25_TX_ENA_5    13
+#define V_AN_SD25_TX_ENA_5(x) ((x) << S_AN_SD25_TX_ENA_5)
+#define F_AN_SD25_TX_ENA_5    V_AN_SD25_TX_ENA_5(1U)
+
+#define S_AN_SD25_TX_ENA_4    12
+#define V_AN_SD25_TX_ENA_4(x) ((x) << S_AN_SD25_TX_ENA_4)
+#define F_AN_SD25_TX_ENA_4    V_AN_SD25_TX_ENA_4(1U)
+
+#define S_AN_SD25_TX_ENA_3    11
+#define V_AN_SD25_TX_ENA_3(x) ((x) << S_AN_SD25_TX_ENA_3)
+#define F_AN_SD25_TX_ENA_3    V_AN_SD25_TX_ENA_3(1U)
+
+#define S_AN_SD25_TX_ENA_2    10
+#define V_AN_SD25_TX_ENA_2(x) ((x) << S_AN_SD25_TX_ENA_2)
+#define F_AN_SD25_TX_ENA_2    V_AN_SD25_TX_ENA_2(1U)
+
+#define S_AN_SD25_TX_ENA_1    9
+#define V_AN_SD25_TX_ENA_1(x) ((x) << S_AN_SD25_TX_ENA_1)
+#define F_AN_SD25_TX_ENA_1    V_AN_SD25_TX_ENA_1(1U)
+
+#define S_AN_SD25_TX_ENA_0    8
+#define V_AN_SD25_TX_ENA_0(x) ((x) << S_AN_SD25_TX_ENA_0)
+#define F_AN_SD25_TX_ENA_0    V_AN_SD25_TX_ENA_0(1U)
+
+#define S_AN_SD25_RX_ENA_7    7
+#define V_AN_SD25_RX_ENA_7(x) ((x) << S_AN_SD25_RX_ENA_7)
+#define F_AN_SD25_RX_ENA_7    V_AN_SD25_RX_ENA_7(1U)
+
+#define S_AN_SD25_RX_ENA_6    6
+#define V_AN_SD25_RX_ENA_6(x) ((x) << S_AN_SD25_RX_ENA_6)
+#define F_AN_SD25_RX_ENA_6    V_AN_SD25_RX_ENA_6(1U)
+
+#define S_AN_SD25_RX_ENA_5    5
+#define V_AN_SD25_RX_ENA_5(x) ((x) << S_AN_SD25_RX_ENA_5)
+#define F_AN_SD25_RX_ENA_5    V_AN_SD25_RX_ENA_5(1U)
+
+#define S_AN_SD25_RX_ENA_4    4
+#define V_AN_SD25_RX_ENA_4(x) ((x) << S_AN_SD25_RX_ENA_4)
+#define F_AN_SD25_RX_ENA_4    V_AN_SD25_RX_ENA_4(1U)
+
+#define S_AN_SD25_RX_ENA_3    3
+#define V_AN_SD25_RX_ENA_3(x) ((x) << S_AN_SD25_RX_ENA_3)
+#define F_AN_SD25_RX_ENA_3    V_AN_SD25_RX_ENA_3(1U)
+
+#define S_AN_SD25_RX_ENA_2    2
+#define V_AN_SD25_RX_ENA_2(x) ((x) << S_AN_SD25_RX_ENA_2)
+#define F_AN_SD25_RX_ENA_2    V_AN_SD25_RX_ENA_2(1U)
+
+#define S_AN_SD25_RX_ENA_1    1
+#define V_AN_SD25_RX_ENA_1(x) ((x) << S_AN_SD25_RX_ENA_1)
+#define F_AN_SD25_RX_ENA_1    V_AN_SD25_RX_ENA_1(1U)
+
+#define S_AN_SD25_RX_ENA_0    0
+#define V_AN_SD25_RX_ENA_0(x) ((x) << S_AN_SD25_RX_ENA_0)
+#define F_AN_SD25_RX_ENA_0    V_AN_SD25_RX_ENA_0(1U)
+
+#define A_MAC_PLL_CFG_0 0x380a0
+
+#define S_USE_RX_CDR_CLK_FOR_TX    7
+#define V_USE_RX_CDR_CLK_FOR_TX(x) ((x) << S_USE_RX_CDR_CLK_FOR_TX)
+#define F_USE_RX_CDR_CLK_FOR_TX    V_USE_RX_CDR_CLK_FOR_TX(1U)
+
+#define S_HSSPLLSEL0    5
+#define M_HSSPLLSEL0    0x3U
+#define V_HSSPLLSEL0(x) ((x) << S_HSSPLLSEL0)
+#define G_HSSPLLSEL0(x) (((x) >> S_HSSPLLSEL0) & M_HSSPLLSEL0)
+
+#define S_HSSTXDIV2CLK_SEL0    3
+#define M_HSSTXDIV2CLK_SEL0    0x3U
+#define V_HSSTXDIV2CLK_SEL0(x) ((x) << S_HSSTXDIV2CLK_SEL0)
+#define G_HSSTXDIV2CLK_SEL0(x) (((x) >> S_HSSTXDIV2CLK_SEL0) & M_HSSTXDIV2CLK_SEL0)
+
+#define S_HSS_RESET0    2
+#define V_HSS_RESET0(x) ((x) << S_HSS_RESET0)
+#define F_HSS_RESET0    V_HSS_RESET0(1U)
+
+#define S_APB_RESET0    1
+#define V_APB_RESET0(x) ((x) << S_APB_RESET0)
+#define F_APB_RESET0    V_APB_RESET0(1U)
+
+#define S_HSSCLK32DIV2_RESET0    0
+#define V_HSSCLK32DIV2_RESET0(x) ((x) << S_HSSCLK32DIV2_RESET0)
+#define F_HSSCLK32DIV2_RESET0    V_HSSCLK32DIV2_RESET0(1U)
+
+#define A_MAC_PLL_CFG_1 0x380a4
+
+#define S_HSSPLLSEL1    5
+#define M_HSSPLLSEL1    0x3U
+#define V_HSSPLLSEL1(x) ((x) << S_HSSPLLSEL1)
+#define G_HSSPLLSEL1(x) (((x) >> S_HSSPLLSEL1) & M_HSSPLLSEL1)
+
+#define S_HSSTXDIV2CLK_SEL1    3
+#define M_HSSTXDIV2CLK_SEL1    0x3U
+#define V_HSSTXDIV2CLK_SEL1(x) ((x) << S_HSSTXDIV2CLK_SEL1)
+#define G_HSSTXDIV2CLK_SEL1(x) (((x) >> S_HSSTXDIV2CLK_SEL1) & M_HSSTXDIV2CLK_SEL1)
+
+#define S_HSS_RESET1    2
+#define V_HSS_RESET1(x) ((x) << S_HSS_RESET1)
+#define F_HSS_RESET1    V_HSS_RESET1(1U)
+
+#define S_APB_RESET1    1
+#define V_APB_RESET1(x) ((x) << S_APB_RESET1)
+#define F_APB_RESET1    V_APB_RESET1(1U)
+
+#define S_HSSCLK32DIV2_RESET1    0
+#define V_HSSCLK32DIV2_RESET1(x) ((x) << S_HSSCLK32DIV2_RESET1)
+#define F_HSSCLK32DIV2_RESET1    V_HSSCLK32DIV2_RESET1(1U)
+
+#define A_MAC_PLL_CFG_2 0x380a8
+
+#define S_HSSPLLSEL2    5
+#define M_HSSPLLSEL2    0x3U
+#define V_HSSPLLSEL2(x) ((x) << S_HSSPLLSEL2)
+#define G_HSSPLLSEL2(x) (((x) >> S_HSSPLLSEL2) & M_HSSPLLSEL2)
+
+#define S_HSSTXDIV2CLK_SEL2    3
+#define M_HSSTXDIV2CLK_SEL2    0x3U
+#define V_HSSTXDIV2CLK_SEL2(x) ((x) << S_HSSTXDIV2CLK_SEL2)
+#define G_HSSTXDIV2CLK_SEL2(x) (((x) >> S_HSSTXDIV2CLK_SEL2) & M_HSSTXDIV2CLK_SEL2)
+
+#define S_HSS_RESET2    2
+#define V_HSS_RESET2(x) ((x) << S_HSS_RESET2)
+#define F_HSS_RESET2    V_HSS_RESET2(1U)
+
+#define S_APB_RESET2    1
+#define V_APB_RESET2(x) ((x) << S_APB_RESET2)
+#define F_APB_RESET2    V_APB_RESET2(1U)
+
+#define S_HSSCLK32DIV2_RESET2    0
+#define V_HSSCLK32DIV2_RESET2(x) ((x) << S_HSSCLK32DIV2_RESET2)
+#define F_HSSCLK32DIV2_RESET2    V_HSSCLK32DIV2_RESET2(1U)
+
+#define A_MAC_PLL_CFG_3 0x380ac
+
+#define S_HSSPLLSEL3    5
+#define M_HSSPLLSEL3    0x3U
+#define V_HSSPLLSEL3(x) ((x) << S_HSSPLLSEL3)
+#define G_HSSPLLSEL3(x) (((x) >> S_HSSPLLSEL3) & M_HSSPLLSEL3)
+
+#define S_HSSTXDIV2CLK_SEL3    3
+#define M_HSSTXDIV2CLK_SEL3    0x3U
+#define V_HSSTXDIV2CLK_SEL3(x) ((x) << S_HSSTXDIV2CLK_SEL3)
+#define G_HSSTXDIV2CLK_SEL3(x) (((x) >> S_HSSTXDIV2CLK_SEL3) & M_HSSTXDIV2CLK_SEL3)
+
+#define S_HSS_RESET3    2
+#define V_HSS_RESET3(x) ((x) << S_HSS_RESET3)
+#define F_HSS_RESET3    V_HSS_RESET3(1U)
+
+#define S_APB_RESET3    1
+#define V_APB_RESET3(x) ((x) << S_APB_RESET3)
+#define F_APB_RESET3    V_APB_RESET3(1U)
+
+#define S_HSSCLK32DIV2_RESET3    0
+#define V_HSSCLK32DIV2_RESET3(x) ((x) << S_HSSCLK32DIV2_RESET3)
+#define F_HSSCLK32DIV2_RESET3    V_HSSCLK32DIV2_RESET3(1U)
+
+#define A_MAC_HSS_STATUS 0x380b0
+
+#define S_TX_LANE_PLL_SEL_3    30
+#define M_TX_LANE_PLL_SEL_3    0x3U
+#define V_TX_LANE_PLL_SEL_3(x) ((x) << S_TX_LANE_PLL_SEL_3)
+#define G_TX_LANE_PLL_SEL_3(x) (((x) >> S_TX_LANE_PLL_SEL_3) & M_TX_LANE_PLL_SEL_3)
+
+#define S_TX_LANE_PLL_SEL_2    28
+#define M_TX_LANE_PLL_SEL_2    0x3U
+#define V_TX_LANE_PLL_SEL_2(x) ((x) << S_TX_LANE_PLL_SEL_2)
+#define G_TX_LANE_PLL_SEL_2(x) (((x) >> S_TX_LANE_PLL_SEL_2) & M_TX_LANE_PLL_SEL_2)
+
+#define S_TX_LANE_PLL_SEL_1    26
+#define M_TX_LANE_PLL_SEL_1    0x3U
+#define V_TX_LANE_PLL_SEL_1(x) ((x) << S_TX_LANE_PLL_SEL_1)
+#define G_TX_LANE_PLL_SEL_1(x) (((x) >> S_TX_LANE_PLL_SEL_1) & M_TX_LANE_PLL_SEL_1)
+
+#define S_TX_LANE_PLL_SEL_0    24
+#define M_TX_LANE_PLL_SEL_0    0x3U
+#define V_TX_LANE_PLL_SEL_0(x) ((x) << S_TX_LANE_PLL_SEL_0)
+#define G_TX_LANE_PLL_SEL_0(x) (((x) >> S_TX_LANE_PLL_SEL_0) & M_TX_LANE_PLL_SEL_0)
+
+#define S_HSSPLLLOCKB_HSS3    7
+#define V_HSSPLLLOCKB_HSS3(x) ((x) << S_HSSPLLLOCKB_HSS3)
+#define F_HSSPLLLOCKB_HSS3    V_HSSPLLLOCKB_HSS3(1U)
+
+#define S_HSSPLLLOCKA_HSS3    6
+#define V_HSSPLLLOCKA_HSS3(x) ((x) << S_HSSPLLLOCKA_HSS3)
+#define F_HSSPLLLOCKA_HSS3    V_HSSPLLLOCKA_HSS3(1U)
+
+#define S_HSSPLLLOCKB_HSS2    5
+#define V_HSSPLLLOCKB_HSS2(x) ((x) << S_HSSPLLLOCKB_HSS2)
+#define F_HSSPLLLOCKB_HSS2    V_HSSPLLLOCKB_HSS2(1U)
+
+#define S_HSSPLLLOCKA_HSS2    4
+#define V_HSSPLLLOCKA_HSS2(x) ((x) << S_HSSPLLLOCKA_HSS2)
+#define F_HSSPLLLOCKA_HSS2    V_HSSPLLLOCKA_HSS2(1U)
+
+#define S_HSSPLLLOCKB_HSS1    3
+#define V_HSSPLLLOCKB_HSS1(x) ((x) << S_HSSPLLLOCKB_HSS1)
+#define F_HSSPLLLOCKB_HSS1    V_HSSPLLLOCKB_HSS1(1U)
+
+#define S_HSSPLLLOCKA_HSS1    2
+#define V_HSSPLLLOCKA_HSS1(x) ((x) << S_HSSPLLLOCKA_HSS1)
+#define F_HSSPLLLOCKA_HSS1    V_HSSPLLLOCKA_HSS1(1U)
+
+#define S_HSSPLLLOCKB_HSS0    1
+#define V_HSSPLLLOCKB_HSS0(x) ((x) << S_HSSPLLLOCKB_HSS0)
+#define F_HSSPLLLOCKB_HSS0    V_HSSPLLLOCKB_HSS0(1U)
+
+#define S_HSSPLLLOCKA_HSS0    0
+#define V_HSSPLLLOCKA_HSS0(x) ((x) << S_HSSPLLLOCKA_HSS0)
+#define F_HSSPLLLOCKA_HSS0    V_HSSPLLLOCKA_HSS0(1U)
+
+#define A_MAC_HSS_SIGDET_STATUS 0x380b4
+
+#define S_HSS3_SIGDET    6
+#define M_HSS3_SIGDET    0x3U
+#define V_HSS3_SIGDET(x) ((x) << S_HSS3_SIGDET)
+#define G_HSS3_SIGDET(x) (((x) >> S_HSS3_SIGDET) & M_HSS3_SIGDET)
+
+#define S_HSS2_SIGDET    4
+#define M_HSS2_SIGDET    0x3U
+#define V_HSS2_SIGDET(x) ((x) << S_HSS2_SIGDET)
+#define G_HSS2_SIGDET(x) (((x) >> S_HSS2_SIGDET) & M_HSS2_SIGDET)
+
+#define S_HSS1_SIGDET    2
+#define M_HSS1_SIGDET    0x3U
+#define V_HSS1_SIGDET(x) ((x) << S_HSS1_SIGDET)
+#define G_HSS1_SIGDET(x) (((x) >> S_HSS1_SIGDET) & M_HSS1_SIGDET)
+
+#define S_HSS0_SIGDET    0
+#define M_HSS0_SIGDET    0x3U
+#define V_HSS0_SIGDET(x) ((x) << S_HSS0_SIGDET)
+#define G_HSS0_SIGDET(x) (((x) >> S_HSS0_SIGDET) & M_HSS0_SIGDET)
+
+#define A_MAC_FPGA_CFG_0 0x380b8
+#define A_MAC_PMD_STATUS 0x380bc
+
+#define S_SIGNAL_DETECT    0
+#define M_SIGNAL_DETECT    0xffU
+#define V_SIGNAL_DETECT(x) ((x) << S_SIGNAL_DETECT)
+#define G_SIGNAL_DETECT(x) (((x) >> S_SIGNAL_DETECT) & M_SIGNAL_DETECT)
+
+#define A_MAC_PMD_AN_CONFIG0 0x380c0
+
+#define S_AN3_RATE_SELECT    25
+#define M_AN3_RATE_SELECT    0x1fU
+#define V_AN3_RATE_SELECT(x) ((x) << S_AN3_RATE_SELECT)
+#define G_AN3_RATE_SELECT(x) (((x) >> S_AN3_RATE_SELECT) & M_AN3_RATE_SELECT)
+
+#define S_AN3_STATUS    24
+#define V_AN3_STATUS(x) ((x) << S_AN3_STATUS)
+#define F_AN3_STATUS    V_AN3_STATUS(1U)
+
+#define S_AN2_RATE_SELECT    17
+#define M_AN2_RATE_SELECT    0x1fU
+#define V_AN2_RATE_SELECT(x) ((x) << S_AN2_RATE_SELECT)
+#define G_AN2_RATE_SELECT(x) (((x) >> S_AN2_RATE_SELECT) & M_AN2_RATE_SELECT)
+
+#define S_AN2_STATUS    16
+#define V_AN2_STATUS(x) ((x) << S_AN2_STATUS)
+#define F_AN2_STATUS    V_AN2_STATUS(1U)
+
+#define S_AN1_RATE_SELECT    9
+#define M_AN1_RATE_SELECT    0x1fU
+#define V_AN1_RATE_SELECT(x) ((x) << S_AN1_RATE_SELECT)
+#define G_AN1_RATE_SELECT(x) (((x) >> S_AN1_RATE_SELECT) & M_AN1_RATE_SELECT)
+
+#define S_AN1_STATUS    8
+#define V_AN1_STATUS(x) ((x) << S_AN1_STATUS)
+#define F_AN1_STATUS    V_AN1_STATUS(1U)
+
+#define S_AN0_RATE_SELECT    1
+#define M_AN0_RATE_SELECT    0x1fU
+#define V_AN0_RATE_SELECT(x) ((x) << S_AN0_RATE_SELECT)
+#define G_AN0_RATE_SELECT(x) (((x) >> S_AN0_RATE_SELECT) & M_AN0_RATE_SELECT)
+
+#define S_AN0_STATUS    0
+#define V_AN0_STATUS(x) ((x) << S_AN0_STATUS)
+#define F_AN0_STATUS    V_AN0_STATUS(1U)
+
+#define A_MAC_PMD_AN_CONFIG1 0x380c4
+
+#define S_AN7_RATE_SELECT    25
+#define M_AN7_RATE_SELECT    0x1fU
+#define V_AN7_RATE_SELECT(x) ((x) << S_AN7_RATE_SELECT)
+#define G_AN7_RATE_SELECT(x) (((x) >> S_AN7_RATE_SELECT) & M_AN7_RATE_SELECT)
+
+#define S_AN7_STATUS    24
+#define V_AN7_STATUS(x) ((x) << S_AN7_STATUS)
+#define F_AN7_STATUS    V_AN7_STATUS(1U)
+
+#define S_AN6_RATE_SELECT    17
+#define M_AN6_RATE_SELECT    0x1fU
+#define V_AN6_RATE_SELECT(x) ((x) << S_AN6_RATE_SELECT)
+#define G_AN6_RATE_SELECT(x) (((x) >> S_AN6_RATE_SELECT) & M_AN6_RATE_SELECT)
+
+#define S_AN6_STATUS    16
+#define V_AN6_STATUS(x) ((x) << S_AN6_STATUS)
+#define F_AN6_STATUS    V_AN6_STATUS(1U)
+
+#define S_AN5_RATE_SELECT    9
+#define M_AN5_RATE_SELECT    0x1fU
+#define V_AN5_RATE_SELECT(x) ((x) << S_AN5_RATE_SELECT)
+#define G_AN5_RATE_SELECT(x) (((x) >> S_AN5_RATE_SELECT) & M_AN5_RATE_SELECT)
+
+#define S_AN5_STATUS    8
+#define V_AN5_STATUS(x) ((x) << S_AN5_STATUS)
+#define F_AN5_STATUS    V_AN5_STATUS(1U)
+
+#define S_AN4_RATE_SELECT    1
+#define M_AN4_RATE_SELECT    0x1fU
+#define V_AN4_RATE_SELECT(x) ((x) << S_AN4_RATE_SELECT)
+#define G_AN4_RATE_SELECT(x) (((x) >> S_AN4_RATE_SELECT) & M_AN4_RATE_SELECT)
+
+#define S_AN4_STATUS    0
+#define V_AN4_STATUS(x) ((x) << S_AN4_STATUS)
+#define F_AN4_STATUS    V_AN4_STATUS(1U)
+
+#define A_MAC_INT_EN_CMN 0x380c8
+
+#define S_HSS3PLL1_LOCK_LOST_INT_EN    21
+#define V_HSS3PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_EN)
+#define F_HSS3PLL1_LOCK_LOST_INT_EN    V_HSS3PLL1_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS3PLL1_LOCK_INT_EN    20
+#define V_HSS3PLL1_LOCK_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_INT_EN)
+#define F_HSS3PLL1_LOCK_INT_EN    V_HSS3PLL1_LOCK_INT_EN(1U)
+
+#define S_HSS3PLL0_LOCK_LOST_INT_EN    19
+#define V_HSS3PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_EN)
+#define F_HSS3PLL0_LOCK_LOST_INT_EN    V_HSS3PLL0_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS3PLL0_LOCK_INT_EN    18
+#define V_HSS3PLL0_LOCK_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_INT_EN)
+#define F_HSS3PLL0_LOCK_INT_EN    V_HSS3PLL0_LOCK_INT_EN(1U)
+
+#define S_HSS2PLL1_LOCK_LOST_INT_EN    17
+#define V_HSS2PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_LOST_INT_EN)
+#define F_HSS2PLL1_LOCK_LOST_INT_EN    V_HSS2PLL1_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS2PLL1_LOCK_INT_EN    16
+#define V_HSS2PLL1_LOCK_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_INT_EN)
+#define F_HSS2PLL1_LOCK_INT_EN    V_HSS2PLL1_LOCK_INT_EN(1U)
+
+#define S_HSS2PLL0_LOCK_LOST_INT_EN    15
+#define V_HSS2PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_EN)
+#define F_HSS2PLL0_LOCK_LOST_INT_EN    V_HSS2PLL0_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS2PLL0_LOCK_INT_EN    14
+#define V_HSS2PLL0_LOCK_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_INT_EN)
+#define F_HSS2PLL0_LOCK_INT_EN    V_HSS2PLL0_LOCK_INT_EN(1U)
+
+#define S_HSS1PLL1_LOCK_LOST_INT_EN    13
+#define V_HSS1PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_EN)
+#define F_HSS1PLL1_LOCK_LOST_INT_EN    V_HSS1PLL1_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS1PLL1_LOCK_INT_EN    12
+#define V_HSS1PLL1_LOCK_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_INT_EN)
+#define F_HSS1PLL1_LOCK_INT_EN    V_HSS1PLL1_LOCK_INT_EN(1U)
+
+#define S_HSS1PLL0_LOCK_LOST_INT_EN    11
+#define V_HSS1PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_EN)
+#define F_HSS1PLL0_LOCK_LOST_INT_EN    V_HSS1PLL0_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS1PLL0_LOCK_INT_EN    10
+#define V_HSS1PLL0_LOCK_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_INT_EN)
+#define F_HSS1PLL0_LOCK_INT_EN    V_HSS1PLL0_LOCK_INT_EN(1U)
+
+#define S_HSS0PLL1_LOCK_LOST_INT_EN    9
+#define V_HSS0PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_EN)
+#define F_HSS0PLL1_LOCK_LOST_INT_EN    V_HSS0PLL1_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS0PLL1_LOCK_INT_EN    8
+#define V_HSS0PLL1_LOCK_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_INT_EN)
+#define F_HSS0PLL1_LOCK_INT_EN    V_HSS0PLL1_LOCK_INT_EN(1U)
+
+#define S_HSS0PLL0_LOCK_LOST_INT_EN    7
+#define V_HSS0PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_EN)
+#define F_HSS0PLL0_LOCK_LOST_INT_EN    V_HSS0PLL0_LOCK_LOST_INT_EN(1U)
+
+#define S_HSS0PLL0_LOCK_INT_EN    6
+#define V_HSS0PLL0_LOCK_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_INT_EN)
+#define F_HSS0PLL0_LOCK_INT_EN    V_HSS0PLL0_LOCK_INT_EN(1U)
+
+#define S_FLOCK_ASSERTED    5
+#define V_FLOCK_ASSERTED(x) ((x) << S_FLOCK_ASSERTED)
+#define F_FLOCK_ASSERTED    V_FLOCK_ASSERTED(1U)
+
+#define S_FLOCK_LOST    4
+#define V_FLOCK_LOST(x) ((x) << S_FLOCK_LOST)
+#define F_FLOCK_LOST    V_FLOCK_LOST(1U)
+
+#define S_PHASE_LOCK_ASSERTED    3
+#define V_PHASE_LOCK_ASSERTED(x) ((x) << S_PHASE_LOCK_ASSERTED)
+#define F_PHASE_LOCK_ASSERTED    V_PHASE_LOCK_ASSERTED(1U)
+
+#define S_PHASE_LOCK_LOST    2
+#define V_PHASE_LOCK_LOST(x) ((x) << S_PHASE_LOCK_LOST)
+#define F_PHASE_LOCK_LOST    V_PHASE_LOCK_LOST(1U)
+
+#define S_LOCK_ASSERTED    1
+#define V_LOCK_ASSERTED(x) ((x) << S_LOCK_ASSERTED)
+#define F_LOCK_ASSERTED    V_LOCK_ASSERTED(1U)
+
+#define S_LOCK_LOST    0
+#define V_LOCK_LOST(x) ((x) << S_LOCK_LOST)
+#define F_LOCK_LOST    V_LOCK_LOST(1U)
+
+#define A_MAC_INT_CAUSE_CMN 0x380cc
+
+#define S_HSS3PLL1_LOCK_LOST_INT_CAUSE    21
+#define V_HSS3PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_CAUSE)
+#define F_HSS3PLL1_LOCK_LOST_INT_CAUSE    V_HSS3PLL1_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS3PLL1_LOCK_INT_CAUSE    20
+#define V_HSS3PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_INT_CAUSE)
+#define F_HSS3PLL1_LOCK_INT_CAUSE    V_HSS3PLL1_LOCK_INT_CAUSE(1U)
+
+#define S_HSS3PLL0_LOCK_LOST_INT_CAUSE    19
+#define V_HSS3PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_CAUSE)
+#define F_HSS3PLL0_LOCK_LOST_INT_CAUSE    V_HSS3PLL0_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS3PLL0_LOCK_INT_CAUSE    18
+#define V_HSS3PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_INT_CAUSE)
+#define F_HSS3PLL0_LOCK_INT_CAUSE    V_HSS3PLL0_LOCK_INT_CAUSE(1U)
+
+#define S_HSS2PLL1_LOCK_LOST_CAUSE    17
+#define V_HSS2PLL1_LOCK_LOST_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_LOST_CAUSE)
+#define F_HSS2PLL1_LOCK_LOST_CAUSE    V_HSS2PLL1_LOCK_LOST_CAUSE(1U)
+
+#define S_HSS2PLL1_LOCK_INT_CAUSE    16
+#define V_HSS2PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_INT_CAUSE)
+#define F_HSS2PLL1_LOCK_INT_CAUSE    V_HSS2PLL1_LOCK_INT_CAUSE(1U)
+
+#define S_HSS2PLL0_LOCK_LOST_INT_CAUSE    15
+#define V_HSS2PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_CAUSE)
+#define F_HSS2PLL0_LOCK_LOST_INT_CAUSE    V_HSS2PLL0_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS2PLL0_LOCK_INT_CAUSE    14
+#define V_HSS2PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_INT_CAUSE)
+#define F_HSS2PLL0_LOCK_INT_CAUSE    V_HSS2PLL0_LOCK_INT_CAUSE(1U)
+
+#define S_HSS1PLL1_LOCK_LOST_INT_CAUSE    13
+#define V_HSS1PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_CAUSE)
+#define F_HSS1PLL1_LOCK_LOST_INT_CAUSE    V_HSS1PLL1_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS1PLL1_LOCK_INT_CAUSE    12
+#define V_HSS1PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_INT_CAUSE)
+#define F_HSS1PLL1_LOCK_INT_CAUSE    V_HSS1PLL1_LOCK_INT_CAUSE(1U)
+
+#define S_HSS1PLL0_LOCK_LOST_INT_CAUSE    11
+#define V_HSS1PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_CAUSE)
+#define F_HSS1PLL0_LOCK_LOST_INT_CAUSE    V_HSS1PLL0_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS1PLL0_LOCK_INT_CAUSE    10
+#define V_HSS1PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_INT_CAUSE)
+#define F_HSS1PLL0_LOCK_INT_CAUSE    V_HSS1PLL0_LOCK_INT_CAUSE(1U)
+
+#define S_HSS0PLL1_LOCK_LOST_INT_CAUSE    9
+#define V_HSS0PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_CAUSE)
+#define F_HSS0PLL1_LOCK_LOST_INT_CAUSE    V_HSS0PLL1_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS0PLL1_LOCK_INT_CAUSE    8
+#define V_HSS0PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_INT_CAUSE)
+#define F_HSS0PLL1_LOCK_INT_CAUSE    V_HSS0PLL1_LOCK_INT_CAUSE(1U)
+
+#define S_HSS0PLL0_LOCK_LOST_INT_CAUSE    7
+#define V_HSS0PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_CAUSE)
+#define F_HSS0PLL0_LOCK_LOST_INT_CAUSE    V_HSS0PLL0_LOCK_LOST_INT_CAUSE(1U)
+
+#define S_HSS0PLL0_LOCK_INT_CAUSE    6
+#define V_HSS0PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_INT_CAUSE)
+#define F_HSS0PLL0_LOCK_INT_CAUSE    V_HSS0PLL0_LOCK_INT_CAUSE(1U)
+
+#define A_MAC_PERR_INT_EN_MTIP 0x380d0
+
+#define S_PERR_MAC0_TX    19
+#define V_PERR_MAC0_TX(x) ((x) << S_PERR_MAC0_TX)
+#define F_PERR_MAC0_TX    V_PERR_MAC0_TX(1U)
+
+#define S_PERR_MAC1_TX    18
+#define V_PERR_MAC1_TX(x) ((x) << S_PERR_MAC1_TX)
+#define F_PERR_MAC1_TX    V_PERR_MAC1_TX(1U)
+
+#define S_PERR_MAC2_TX    17
+#define V_PERR_MAC2_TX(x) ((x) << S_PERR_MAC2_TX)
+#define F_PERR_MAC2_TX    V_PERR_MAC2_TX(1U)
+
+#define S_PERR_MAC3_TX    16
+#define V_PERR_MAC3_TX(x) ((x) << S_PERR_MAC3_TX)
+#define F_PERR_MAC3_TX    V_PERR_MAC3_TX(1U)
+
+#define S_PERR_MAC4_TX    15
+#define V_PERR_MAC4_TX(x) ((x) << S_PERR_MAC4_TX)
+#define F_PERR_MAC4_TX    V_PERR_MAC4_TX(1U)
+
+#define S_PERR_MAC5_TX    14
+#define V_PERR_MAC5_TX(x) ((x) << S_PERR_MAC5_TX)
+#define F_PERR_MAC5_TX    V_PERR_MAC5_TX(1U)
+
+#define S_PERR_MAC0_RX    13
+#define V_PERR_MAC0_RX(x) ((x) << S_PERR_MAC0_RX)
+#define F_PERR_MAC0_RX    V_PERR_MAC0_RX(1U)
+
+#define S_PERR_MAC1_RX    12
+#define V_PERR_MAC1_RX(x) ((x) << S_PERR_MAC1_RX)
+#define F_PERR_MAC1_RX    V_PERR_MAC1_RX(1U)
+
+#define S_PERR_MAC2_RX    11
+#define V_PERR_MAC2_RX(x) ((x) << S_PERR_MAC2_RX)
+#define F_PERR_MAC2_RX    V_PERR_MAC2_RX(1U)
+
+#define S_PERR_MAC3_RX    10
+#define V_PERR_MAC3_RX(x) ((x) << S_PERR_MAC3_RX)
+#define F_PERR_MAC3_RX    V_PERR_MAC3_RX(1U)
+
+#define S_PERR_MAC4_RX    9
+#define V_PERR_MAC4_RX(x) ((x) << S_PERR_MAC4_RX)
+#define F_PERR_MAC4_RX    V_PERR_MAC4_RX(1U)
+
+#define S_PERR_MAC5_RX    8
+#define V_PERR_MAC5_RX(x) ((x) << S_PERR_MAC5_RX)
+#define F_PERR_MAC5_RX    V_PERR_MAC5_RX(1U)
+
+#define S_PERR_MAC_STAT2_RX    7
+#define V_PERR_MAC_STAT2_RX(x) ((x) << S_PERR_MAC_STAT2_RX)
+#define F_PERR_MAC_STAT2_RX    V_PERR_MAC_STAT2_RX(1U)
+
+#define S_PERR_MAC_STAT3_RX    6
+#define V_PERR_MAC_STAT3_RX(x) ((x) << S_PERR_MAC_STAT3_RX)
+#define F_PERR_MAC_STAT3_RX    V_PERR_MAC_STAT3_RX(1U)
+
+#define S_PERR_MAC_STAT4_RX    5
+#define V_PERR_MAC_STAT4_RX(x) ((x) << S_PERR_MAC_STAT4_RX)
+#define F_PERR_MAC_STAT4_RX    V_PERR_MAC_STAT4_RX(1U)
+
+#define S_PERR_MAC_STAT5_RX    4
+#define V_PERR_MAC_STAT5_RX(x) ((x) << S_PERR_MAC_STAT5_RX)
+#define F_PERR_MAC_STAT5_RX    V_PERR_MAC_STAT5_RX(1U)
+
+#define S_PERR_MAC_STAT2_TX    3
+#define V_PERR_MAC_STAT2_TX(x) ((x) << S_PERR_MAC_STAT2_TX)
+#define F_PERR_MAC_STAT2_TX    V_PERR_MAC_STAT2_TX(1U)
+
+#define S_PERR_MAC_STAT3_TX    2
+#define V_PERR_MAC_STAT3_TX(x) ((x) << S_PERR_MAC_STAT3_TX)
+#define F_PERR_MAC_STAT3_TX    V_PERR_MAC_STAT3_TX(1U)
+
+#define S_PERR_MAC_STAT4_TX    1
+#define V_PERR_MAC_STAT4_TX(x) ((x) << S_PERR_MAC_STAT4_TX)
+#define F_PERR_MAC_STAT4_TX    V_PERR_MAC_STAT4_TX(1U)
+
+#define S_PERR_MAC_STAT5_TX    0
+#define V_PERR_MAC_STAT5_TX(x) ((x) << S_PERR_MAC_STAT5_TX)
+#define F_PERR_MAC_STAT5_TX    V_PERR_MAC_STAT5_TX(1U)
+
+#define A_MAC_PERR_INT_CAUSE_MTIP 0x380d4
+
+#define S_PERR_MAC_STAT_RX    7
+#define V_PERR_MAC_STAT_RX(x) ((x) << S_PERR_MAC_STAT_RX)
+#define F_PERR_MAC_STAT_RX    V_PERR_MAC_STAT_RX(1U)
+
+#define S_PERR_MAC_STAT_TX    3
+#define V_PERR_MAC_STAT_TX(x) ((x) << S_PERR_MAC_STAT_TX)
+#define F_PERR_MAC_STAT_TX    V_PERR_MAC_STAT_TX(1U)
+
+#define S_PERR_MAC_STAT_CAP    2
+#define V_PERR_MAC_STAT_CAP(x) ((x) << S_PERR_MAC_STAT_CAP)
+#define F_PERR_MAC_STAT_CAP    V_PERR_MAC_STAT_CAP(1U)
+
+#define A_MAC_PERR_ENABLE_MTIP 0x380d8
+#define A_MAC_PCS_1G_CONFIG_0 0x380dc
+
+#define S_SEQ_ENA_3    19
+#define V_SEQ_ENA_3(x) ((x) << S_SEQ_ENA_3)
+#define F_SEQ_ENA_3    V_SEQ_ENA_3(1U)
+
+#define S_SEQ_ENA_2    18
+#define V_SEQ_ENA_2(x) ((x) << S_SEQ_ENA_2)
+#define F_SEQ_ENA_2    V_SEQ_ENA_2(1U)
+
+#define S_SEQ_ENA_1    17
+#define V_SEQ_ENA_1(x) ((x) << S_SEQ_ENA_1)
+#define F_SEQ_ENA_1    V_SEQ_ENA_1(1U)
+
+#define S_SEQ_ENA_0    16
+#define V_SEQ_ENA_0(x) ((x) << S_SEQ_ENA_0)
+#define F_SEQ_ENA_0    V_SEQ_ENA_0(1U)
+
+#define S_TX_LANE_THRESH_3    12
+#define M_TX_LANE_THRESH_3    0xfU
+#define V_TX_LANE_THRESH_3(x) ((x) << S_TX_LANE_THRESH_3)
+#define G_TX_LANE_THRESH_3(x) (((x) >> S_TX_LANE_THRESH_3) & M_TX_LANE_THRESH_3)
+
+#define S_TX_LANE_THRESH_2    8
+#define M_TX_LANE_THRESH_2    0xfU
+#define V_TX_LANE_THRESH_2(x) ((x) << S_TX_LANE_THRESH_2)
+#define G_TX_LANE_THRESH_2(x) (((x) >> S_TX_LANE_THRESH_2) & M_TX_LANE_THRESH_2)
+
+#define S_TX_LANE_THRESH_1    4
+#define M_TX_LANE_THRESH_1    0xfU
+#define V_TX_LANE_THRESH_1(x) ((x) << S_TX_LANE_THRESH_1)
+#define G_TX_LANE_THRESH_1(x) (((x) >> S_TX_LANE_THRESH_1) & M_TX_LANE_THRESH_1)
+
+#define S_TX_LANE_THRESH_0    0
+#define M_TX_LANE_THRESH_0    0xfU
+#define V_TX_LANE_THRESH_0(x) ((x) << S_TX_LANE_THRESH_0)
+#define G_TX_LANE_THRESH_0(x) (((x) >> S_TX_LANE_THRESH_0) & M_TX_LANE_THRESH_0)
+
+#define A_MAC_PCS_1G_CONFIG_1 0x380e0
+
+#define S_TX_LANE_CKMULT_3    9
+#define M_TX_LANE_CKMULT_3    0x7U
+#define V_TX_LANE_CKMULT_3(x) ((x) << S_TX_LANE_CKMULT_3)
+#define G_TX_LANE_CKMULT_3(x) (((x) >> S_TX_LANE_CKMULT_3) & M_TX_LANE_CKMULT_3)
+
+#define S_TX_LANE_CKMULT_2    6
+#define M_TX_LANE_CKMULT_2    0x7U
+#define V_TX_LANE_CKMULT_2(x) ((x) << S_TX_LANE_CKMULT_2)
+#define G_TX_LANE_CKMULT_2(x) (((x) >> S_TX_LANE_CKMULT_2) & M_TX_LANE_CKMULT_2)
+
+#define S_TX_LANE_CKMULT_1    3
+#define M_TX_LANE_CKMULT_1    0x7U
+#define V_TX_LANE_CKMULT_1(x) ((x) << S_TX_LANE_CKMULT_1)
+#define G_TX_LANE_CKMULT_1(x) (((x) >> S_TX_LANE_CKMULT_1) & M_TX_LANE_CKMULT_1)
+
+#define S_TX_LANE_CKMULT_0    0
+#define M_TX_LANE_CKMULT_0    0x7U
+#define V_TX_LANE_CKMULT_0(x) ((x) << S_TX_LANE_CKMULT_0)
+#define G_TX_LANE_CKMULT_0(x) (((x) >> S_TX_LANE_CKMULT_0) & M_TX_LANE_CKMULT_0)
+
+#define A_MAC_PTP_TIMER_RD0_LO 0x380e4
+#define A_MAC_PTP_TIMER_RD0_HI 0x380e8
+#define A_MAC_PTP_TIMER_RD1_LO 0x380ec
+#define A_MAC_PTP_TIMER_RD1_HI 0x380f0
+#define A_MAC_PTP_TIMER_WR_LO 0x380f4
+#define A_MAC_PTP_TIMER_WR_HI 0x380f8
+#define A_MAC_PTP_TIMER_OFFSET_0 0x380fc
+#define A_MAC_PTP_TIMER_OFFSET_1 0x38100
+#define A_MAC_PTP_TIMER_OFFSET_2 0x38104
+#define A_MAC_PTP_SUM_LO 0x38108
+#define A_MAC_PTP_SUM_HI 0x3810c
+#define A_MAC_PTP_TIMER_INCR0 0x38110
+#define A_MAC_PTP_TIMER_INCR1 0x38114
+#define A_MAC_PTP_DRIFT_ADJUST_COUNT 0x38118
+#define A_MAC_PTP_OFFSET_ADJUST_FINE 0x3811c
+#define A_MAC_PTP_OFFSET_ADJUST_TOTAL 0x38120
+#define A_MAC_PTP_CFG 0x38124
+#define A_MAC_PTP_PPS 0x38128
+#define A_MAC_PTP_SINGLE_ALARM 0x3812c
+#define A_MAC_PTP_PERIODIC_ALARM 0x38130
+#define A_MAC_PTP_STATUS 0x38134
+#define A_MAC_STS_GPIO_SEL 0x38140
+
+#define S_STSOUTSEL    1
+#define V_STSOUTSEL(x) ((x) << S_STSOUTSEL)
+#define F_STSOUTSEL    V_STSOUTSEL(1U)
+
+#define S_STSINSEL    0
+#define V_STSINSEL(x) ((x) << S_STSINSEL)
+#define F_STSINSEL    V_STSINSEL(1U)
+
+#define A_MAC_CERR_INT_EN_MTIP 0x38150
+
+#define S_CERR_MAC0_TX    11
+#define V_CERR_MAC0_TX(x) ((x) << S_CERR_MAC0_TX)
+#define F_CERR_MAC0_TX    V_CERR_MAC0_TX(1U)
+
+#define S_CERR_MAC1_TX    10
+#define V_CERR_MAC1_TX(x) ((x) << S_CERR_MAC1_TX)
+#define F_CERR_MAC1_TX    V_CERR_MAC1_TX(1U)
+
+#define S_CERR_MAC2_TX    9
+#define V_CERR_MAC2_TX(x) ((x) << S_CERR_MAC2_TX)
+#define F_CERR_MAC2_TX    V_CERR_MAC2_TX(1U)
+
+#define S_CERR_MAC3_TX    8
+#define V_CERR_MAC3_TX(x) ((x) << S_CERR_MAC3_TX)
+#define F_CERR_MAC3_TX    V_CERR_MAC3_TX(1U)
+
+#define S_CERR_MAC4_TX    7
+#define V_CERR_MAC4_TX(x) ((x) << S_CERR_MAC4_TX)
+#define F_CERR_MAC4_TX    V_CERR_MAC4_TX(1U)
+
+#define S_CERR_MAC5_TX    6
+#define V_CERR_MAC5_TX(x) ((x) << S_CERR_MAC5_TX)
+#define F_CERR_MAC5_TX    V_CERR_MAC5_TX(1U)
+
+#define S_CERR_MAC0_RX    5
+#define V_CERR_MAC0_RX(x) ((x) << S_CERR_MAC0_RX)
+#define F_CERR_MAC0_RX    V_CERR_MAC0_RX(1U)
+
+#define S_CERR_MAC1_RX    4
+#define V_CERR_MAC1_RX(x) ((x) << S_CERR_MAC1_RX)
+#define F_CERR_MAC1_RX    V_CERR_MAC1_RX(1U)
+
+#define S_CERR_MAC2_RX    3
+#define V_CERR_MAC2_RX(x) ((x) << S_CERR_MAC2_RX)
+#define F_CERR_MAC2_RX    V_CERR_MAC2_RX(1U)
+
+#define S_CERR_MAC3_RX    2
+#define V_CERR_MAC3_RX(x) ((x) << S_CERR_MAC3_RX)
+#define F_CERR_MAC3_RX    V_CERR_MAC3_RX(1U)
+
+#define S_CERR_MAC4_RX    1
+#define V_CERR_MAC4_RX(x) ((x) << S_CERR_MAC4_RX)
+#define F_CERR_MAC4_RX    V_CERR_MAC4_RX(1U)
+
+#define S_CERR_MAC5_RX    0
+#define V_CERR_MAC5_RX(x) ((x) << S_CERR_MAC5_RX)
+#define F_CERR_MAC5_RX    V_CERR_MAC5_RX(1U)
+
+#define A_MAC_CERR_INT_CAUSE_MTIP 0x38154
+#define A_MAC_1G_PCS0_STATUS 0x38160
+
+#define S_1G_PCS0_LOOPBACK    12
+#define V_1G_PCS0_LOOPBACK(x) ((x) << S_1G_PCS0_LOOPBACK)
+#define F_1G_PCS0_LOOPBACK    V_1G_PCS0_LOOPBACK(1U)
+
+#define S_1G_PCS0_LINK_STATUS    11
+#define V_1G_PCS0_LINK_STATUS(x) ((x) << S_1G_PCS0_LINK_STATUS)
+#define F_1G_PCS0_LINK_STATUS    V_1G_PCS0_LINK_STATUS(1U)
+
+#define S_1G_PCS0_RX_SYNC    10
+#define V_1G_PCS0_RX_SYNC(x) ((x) << S_1G_PCS0_RX_SYNC)
+#define F_1G_PCS0_RX_SYNC    V_1G_PCS0_RX_SYNC(1U)
+
+#define S_1G_PCS0_AN_DONE    9
+#define V_1G_PCS0_AN_DONE(x) ((x) << S_1G_PCS0_AN_DONE)
+#define F_1G_PCS0_AN_DONE    V_1G_PCS0_AN_DONE(1U)
+
+#define S_1G_PCS0_PGRCVD    8
+#define V_1G_PCS0_PGRCVD(x) ((x) << S_1G_PCS0_PGRCVD)
+#define F_1G_PCS0_PGRCVD    V_1G_PCS0_PGRCVD(1U)
+
+#define S_1G_PCS0_SPEED_SEL    6
+#define M_1G_PCS0_SPEED_SEL    0x3U
+#define V_1G_PCS0_SPEED_SEL(x) ((x) << S_1G_PCS0_SPEED_SEL)
+#define G_1G_PCS0_SPEED_SEL(x) (((x) >> S_1G_PCS0_SPEED_SEL) & M_1G_PCS0_SPEED_SEL)
+
+#define S_1G_PCS0_HALF_DUPLEX    5
+#define V_1G_PCS0_HALF_DUPLEX(x) ((x) << S_1G_PCS0_HALF_DUPLEX)
+#define F_1G_PCS0_HALF_DUPLEX    V_1G_PCS0_HALF_DUPLEX(1U)
+
+#define S_1G_PCS0_TX_MODE_QUIET    4
+#define V_1G_PCS0_TX_MODE_QUIET(x) ((x) << S_1G_PCS0_TX_MODE_QUIET)
+#define F_1G_PCS0_TX_MODE_QUIET    V_1G_PCS0_TX_MODE_QUIET(1U)
+
+#define S_1G_PCS0_TX_LPI_ACTIVE    3
+#define V_1G_PCS0_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_TX_LPI_ACTIVE)
+#define F_1G_PCS0_TX_LPI_ACTIVE    V_1G_PCS0_TX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS0_RX_MODE_QUIET    2
+#define V_1G_PCS0_RX_MODE_QUIET(x) ((x) << S_1G_PCS0_RX_MODE_QUIET)
+#define F_1G_PCS0_RX_MODE_QUIET    V_1G_PCS0_RX_MODE_QUIET(1U)
+
+#define S_1G_PCS0_RX_LPI_ACTIVE    1
+#define V_1G_PCS0_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_RX_LPI_ACTIVE)
+#define F_1G_PCS0_RX_LPI_ACTIVE    V_1G_PCS0_RX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS0_RX_WAKE_ERR    0
+#define V_1G_PCS0_RX_WAKE_ERR(x) ((x) << S_1G_PCS0_RX_WAKE_ERR)
+#define F_1G_PCS0_RX_WAKE_ERR    V_1G_PCS0_RX_WAKE_ERR(1U)
+
+#define A_MAC_1G_PCS1_STATUS 0x38164
+
+#define S_1G_PCS1_LOOPBACK    12
+#define V_1G_PCS1_LOOPBACK(x) ((x) << S_1G_PCS1_LOOPBACK)
+#define F_1G_PCS1_LOOPBACK    V_1G_PCS1_LOOPBACK(1U)
+
+#define S_1G_PCS1_LINK_STATUS    11
+#define V_1G_PCS1_LINK_STATUS(x) ((x) << S_1G_PCS1_LINK_STATUS)
+#define F_1G_PCS1_LINK_STATUS    V_1G_PCS1_LINK_STATUS(1U)
+
+#define S_1G_PCS1_RX_SYNC    10
+#define V_1G_PCS1_RX_SYNC(x) ((x) << S_1G_PCS1_RX_SYNC)
+#define F_1G_PCS1_RX_SYNC    V_1G_PCS1_RX_SYNC(1U)
+
+#define S_1G_PCS1_AN_DONE    9
+#define V_1G_PCS1_AN_DONE(x) ((x) << S_1G_PCS1_AN_DONE)
+#define F_1G_PCS1_AN_DONE    V_1G_PCS1_AN_DONE(1U)
+
+#define S_1G_PCS1_PGRCVD    8
+#define V_1G_PCS1_PGRCVD(x) ((x) << S_1G_PCS1_PGRCVD)
+#define F_1G_PCS1_PGRCVD    V_1G_PCS1_PGRCVD(1U)
+
+#define S_1G_PCS1_SPEED_SEL    6
+#define M_1G_PCS1_SPEED_SEL    0x3U
+#define V_1G_PCS1_SPEED_SEL(x) ((x) << S_1G_PCS1_SPEED_SEL)
+#define G_1G_PCS1_SPEED_SEL(x) (((x) >> S_1G_PCS1_SPEED_SEL) & M_1G_PCS1_SPEED_SEL)
+
+#define S_1G_PCS1_HALF_DUPLEX    5
+#define V_1G_PCS1_HALF_DUPLEX(x) ((x) << S_1G_PCS1_HALF_DUPLEX)
+#define F_1G_PCS1_HALF_DUPLEX    V_1G_PCS1_HALF_DUPLEX(1U)
+
+#define S_1G_PCS1_TX_MODE_QUIET    4
+#define V_1G_PCS1_TX_MODE_QUIET(x) ((x) << S_1G_PCS1_TX_MODE_QUIET)
+#define F_1G_PCS1_TX_MODE_QUIET    V_1G_PCS1_TX_MODE_QUIET(1U)
+
+#define S_1G_PCS1_TX_LPI_ACTIVE    3
+#define V_1G_PCS1_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_TX_LPI_ACTIVE)
+#define F_1G_PCS1_TX_LPI_ACTIVE    V_1G_PCS1_TX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS1_RX_MODE_QUIET    2
+#define V_1G_PCS1_RX_MODE_QUIET(x) ((x) << S_1G_PCS1_RX_MODE_QUIET)
+#define F_1G_PCS1_RX_MODE_QUIET    V_1G_PCS1_RX_MODE_QUIET(1U)
+
+#define S_1G_PCS1_RX_LPI_ACTIVE    1
+#define V_1G_PCS1_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_RX_LPI_ACTIVE)
+#define F_1G_PCS1_RX_LPI_ACTIVE    V_1G_PCS1_RX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS1_RX_WAKE_ERR    0
+#define V_1G_PCS1_RX_WAKE_ERR(x) ((x) << S_1G_PCS1_RX_WAKE_ERR)
+#define F_1G_PCS1_RX_WAKE_ERR    V_1G_PCS1_RX_WAKE_ERR(1U)
+
+#define A_MAC_1G_PCS2_STATUS 0x38168
+
+#define S_1G_PCS2_LOOPBACK    12
+#define V_1G_PCS2_LOOPBACK(x) ((x) << S_1G_PCS2_LOOPBACK)
+#define F_1G_PCS2_LOOPBACK    V_1G_PCS2_LOOPBACK(1U)
+
+#define S_1G_PCS2_LINK_STATUS    11
+#define V_1G_PCS2_LINK_STATUS(x) ((x) << S_1G_PCS2_LINK_STATUS)
+#define F_1G_PCS2_LINK_STATUS    V_1G_PCS2_LINK_STATUS(1U)
+
+#define S_1G_PCS2_RX_SYNC    10
+#define V_1G_PCS2_RX_SYNC(x) ((x) << S_1G_PCS2_RX_SYNC)
+#define F_1G_PCS2_RX_SYNC    V_1G_PCS2_RX_SYNC(1U)
+
+#define S_1G_PCS2_AN_DONE    9
+#define V_1G_PCS2_AN_DONE(x) ((x) << S_1G_PCS2_AN_DONE)
+#define F_1G_PCS2_AN_DONE    V_1G_PCS2_AN_DONE(1U)
+
+#define S_1G_PCS2_PGRCVD    8
+#define V_1G_PCS2_PGRCVD(x) ((x) << S_1G_PCS2_PGRCVD)
+#define F_1G_PCS2_PGRCVD    V_1G_PCS2_PGRCVD(1U)
+
+#define S_1G_PCS2_SPEED_SEL    6
+#define M_1G_PCS2_SPEED_SEL    0x3U
+#define V_1G_PCS2_SPEED_SEL(x) ((x) << S_1G_PCS2_SPEED_SEL)
+#define G_1G_PCS2_SPEED_SEL(x) (((x) >> S_1G_PCS2_SPEED_SEL) & M_1G_PCS2_SPEED_SEL)
+
+#define S_1G_PCS2_HALF_DUPLEX    5
+#define V_1G_PCS2_HALF_DUPLEX(x) ((x) << S_1G_PCS2_HALF_DUPLEX)
+#define F_1G_PCS2_HALF_DUPLEX    V_1G_PCS2_HALF_DUPLEX(1U)
+
+#define S_1G_PCS2_TX_MODE_QUIET    4
+#define V_1G_PCS2_TX_MODE_QUIET(x) ((x) << S_1G_PCS2_TX_MODE_QUIET)
+#define F_1G_PCS2_TX_MODE_QUIET    V_1G_PCS2_TX_MODE_QUIET(1U)
+
+#define S_1G_PCS2_TX_LPI_ACTIVE    3
+#define V_1G_PCS2_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_TX_LPI_ACTIVE)
+#define F_1G_PCS2_TX_LPI_ACTIVE    V_1G_PCS2_TX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS2_RX_MODE_QUIET    2
+#define V_1G_PCS2_RX_MODE_QUIET(x) ((x) << S_1G_PCS2_RX_MODE_QUIET)
+#define F_1G_PCS2_RX_MODE_QUIET    V_1G_PCS2_RX_MODE_QUIET(1U)
+
+#define S_1G_PCS2_RX_LPI_ACTIVE    1
+#define V_1G_PCS2_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_RX_LPI_ACTIVE)
+#define F_1G_PCS2_RX_LPI_ACTIVE    V_1G_PCS2_RX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS2_RX_WAKE_ERR    0
+#define V_1G_PCS2_RX_WAKE_ERR(x) ((x) << S_1G_PCS2_RX_WAKE_ERR)
+#define F_1G_PCS2_RX_WAKE_ERR    V_1G_PCS2_RX_WAKE_ERR(1U)
+
+#define A_MAC_1G_PCS3_STATUS 0x3816c
+
+#define S_1G_PCS3_LOOPBACK    12
+#define V_1G_PCS3_LOOPBACK(x) ((x) << S_1G_PCS3_LOOPBACK)
+#define F_1G_PCS3_LOOPBACK    V_1G_PCS3_LOOPBACK(1U)
+
+#define S_1G_PCS3_LINK_STATUS    11
+#define V_1G_PCS3_LINK_STATUS(x) ((x) << S_1G_PCS3_LINK_STATUS)
+#define F_1G_PCS3_LINK_STATUS    V_1G_PCS3_LINK_STATUS(1U)
+
+#define S_1G_PCS3_RX_SYNC    10
+#define V_1G_PCS3_RX_SYNC(x) ((x) << S_1G_PCS3_RX_SYNC)
+#define F_1G_PCS3_RX_SYNC    V_1G_PCS3_RX_SYNC(1U)
+
+#define S_1G_PCS3_AN_DONE    9
+#define V_1G_PCS3_AN_DONE(x) ((x) << S_1G_PCS3_AN_DONE)
+#define F_1G_PCS3_AN_DONE    V_1G_PCS3_AN_DONE(1U)
+
+#define S_1G_PCS3_PGRCVD    8
+#define V_1G_PCS3_PGRCVD(x) ((x) << S_1G_PCS3_PGRCVD)
+#define F_1G_PCS3_PGRCVD    V_1G_PCS3_PGRCVD(1U)
+
+#define S_1G_PCS3_SPEED_SEL    6
+#define M_1G_PCS3_SPEED_SEL    0x3U
+#define V_1G_PCS3_SPEED_SEL(x) ((x) << S_1G_PCS3_SPEED_SEL)
+#define G_1G_PCS3_SPEED_SEL(x) (((x) >> S_1G_PCS3_SPEED_SEL) & M_1G_PCS3_SPEED_SEL)
+
+#define S_1G_PCS3_HALF_DUPLEX    5
+#define V_1G_PCS3_HALF_DUPLEX(x) ((x) << S_1G_PCS3_HALF_DUPLEX)
+#define F_1G_PCS3_HALF_DUPLEX    V_1G_PCS3_HALF_DUPLEX(1U)
+
+#define S_1G_PCS3_TX_MODE_QUIET    4
+#define V_1G_PCS3_TX_MODE_QUIET(x) ((x) << S_1G_PCS3_TX_MODE_QUIET)
+#define F_1G_PCS3_TX_MODE_QUIET    V_1G_PCS3_TX_MODE_QUIET(1U)
+
+#define S_1G_PCS3_TX_LPI_ACTIVE    3
+#define V_1G_PCS3_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_TX_LPI_ACTIVE)
+#define F_1G_PCS3_TX_LPI_ACTIVE    V_1G_PCS3_TX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS3_RX_MODE_QUIET    2
+#define V_1G_PCS3_RX_MODE_QUIET(x) ((x) << S_1G_PCS3_RX_MODE_QUIET)
+#define F_1G_PCS3_RX_MODE_QUIET    V_1G_PCS3_RX_MODE_QUIET(1U)
+
+#define S_1G_PCS3_RX_LPI_ACTIVE    1
+#define V_1G_PCS3_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_RX_LPI_ACTIVE)
+#define F_1G_PCS3_RX_LPI_ACTIVE    V_1G_PCS3_RX_LPI_ACTIVE(1U)
+
+#define S_1G_PCS3_RX_WAKE_ERR    0
+#define V_1G_PCS3_RX_WAKE_ERR(x) ((x) << S_1G_PCS3_RX_WAKE_ERR)
+#define F_1G_PCS3_RX_WAKE_ERR    V_1G_PCS3_RX_WAKE_ERR(1U)
+
+#define A_MAC_PCS_LPI_STATUS_0 0x38170
+
+#define S_TX_LPI_STATE    0
+#define M_TX_LPI_STATE    0xffffffU
+#define V_TX_LPI_STATE(x) ((x) << S_TX_LPI_STATE)
+#define G_TX_LPI_STATE(x) (((x) >> S_TX_LPI_STATE) & M_TX_LPI_STATE)
+
+#define A_MAC_PCS_LPI_STATUS_1 0x38174
+
+#define S_TX_LPI_MODE    0
+#define M_TX_LPI_MODE    0xffffU
+#define V_TX_LPI_MODE(x) ((x) << S_TX_LPI_MODE)
+#define G_TX_LPI_MODE(x) (((x) >> S_TX_LPI_MODE) & M_TX_LPI_MODE)
+
+#define A_MAC_PCS_LPI_STATUS_2 0x38178
+
+#define S_RX_LPI_MODE    24
+#define M_RX_LPI_MODE    0xffU
+#define V_RX_LPI_MODE(x) ((x) << S_RX_LPI_MODE)
+#define G_RX_LPI_MODE(x) (((x) >> S_RX_LPI_MODE) & M_RX_LPI_MODE)
+
+#define S_RX_LPI_STATE    0
+#define M_RX_LPI_STATE    0xffffffU
+#define V_RX_LPI_STATE(x) ((x) << S_RX_LPI_STATE)
+#define G_RX_LPI_STATE(x) (((x) >> S_RX_LPI_STATE) & M_RX_LPI_STATE)
+
+#define A_MAC_PCS_LPI_STATUS_3 0x3817c
+
+#define S_T7_RX_LPI_ACTIVE    0
+#define M_T7_RX_LPI_ACTIVE    0xffU
+#define V_T7_RX_LPI_ACTIVE(x) ((x) << S_T7_RX_LPI_ACTIVE)
+#define G_T7_RX_LPI_ACTIVE(x) (((x) >> S_T7_RX_LPI_ACTIVE) & M_T7_RX_LPI_ACTIVE)
+
+#define A_MAC_TX0_CLK_DIV 0x38180
+#define A_MAC_TX1_CLK_DIV 0x38184
+#define A_MAC_TX2_CLK_DIV 0x38188
+#define A_MAC_TX3_CLK_DIV 0x3818c
+#define A_MAC_TX4_CLK_DIV 0x38190
+#define A_MAC_TX5_CLK_DIV 0x38194
+#define A_MAC_TX6_CLK_DIV 0x38198
+#define A_MAC_TX7_CLK_DIV 0x3819c
+#define A_MAC_RX0_CLK_DIV 0x381a0
+#define A_MAC_RX1_CLK_DIV 0x381a4
+#define A_MAC_RX2_CLK_DIV 0x381a8
+#define A_MAC_RX3_CLK_DIV 0x381ac
+#define A_MAC_RX4_CLK_DIV 0x381b0
+#define A_MAC_RX5_CLK_DIV 0x381b4
+#define A_MAC_RX6_CLK_DIV 0x381b8
+#define A_MAC_RX7_CLK_DIV 0x381bc
+#define A_MAC_SYNC_E_CDR_LANE_SEL 0x381c0
+
+#define S_CML_MUX_SEL    11
+#define V_CML_MUX_SEL(x) ((x) << S_CML_MUX_SEL)
+#define F_CML_MUX_SEL    V_CML_MUX_SEL(1U)
+
+#define S_CMOS_OUT_EN    10
+#define V_CMOS_OUT_EN(x) ((x) << S_CMOS_OUT_EN)
+#define F_CMOS_OUT_EN    V_CMOS_OUT_EN(1U)
+
+#define S_CML_OUT_EN    9
+#define V_CML_OUT_EN(x) ((x) << S_CML_OUT_EN)
+#define F_CML_OUT_EN    V_CML_OUT_EN(1U)
+
+#define S_LOC_FAULT_PORT_SEL    6
+#define M_LOC_FAULT_PORT_SEL    0x3U
+#define V_LOC_FAULT_PORT_SEL(x) ((x) << S_LOC_FAULT_PORT_SEL)
+#define G_LOC_FAULT_PORT_SEL(x) (((x) >> S_LOC_FAULT_PORT_SEL) & M_LOC_FAULT_PORT_SEL)
+
+#define S_TX_CDR_LANE_SEL    3
+#define M_TX_CDR_LANE_SEL    0x7U
+#define V_TX_CDR_LANE_SEL(x) ((x) << S_TX_CDR_LANE_SEL)
+#define G_TX_CDR_LANE_SEL(x) (((x) >> S_TX_CDR_LANE_SEL) & M_TX_CDR_LANE_SEL)
+
+#define S_RX_CDR_LANE_SEL    0
+#define M_RX_CDR_LANE_SEL    0x7U
+#define V_RX_CDR_LANE_SEL(x) ((x) << S_RX_CDR_LANE_SEL)
+#define G_RX_CDR_LANE_SEL(x) (((x) >> S_RX_CDR_LANE_SEL) & M_RX_CDR_LANE_SEL)
+
+#define A_MAC_DEBUG_PL_IF_1 0x381c4
+#define A_MAC_SIGNAL_DETECT_CTRL 0x381f0
+
+#define S_SIGNAL_DET_LN7    15
+#define V_SIGNAL_DET_LN7(x) ((x) << S_SIGNAL_DET_LN7)
+#define F_SIGNAL_DET_LN7    V_SIGNAL_DET_LN7(1U)
+
+#define S_SIGNAL_DET_LN6    14
+#define V_SIGNAL_DET_LN6(x) ((x) << S_SIGNAL_DET_LN6)
+#define F_SIGNAL_DET_LN6    V_SIGNAL_DET_LN6(1U)
+
+#define S_SIGNAL_DET_LN5    13
+#define V_SIGNAL_DET_LN5(x) ((x) << S_SIGNAL_DET_LN5)
+#define F_SIGNAL_DET_LN5    V_SIGNAL_DET_LN5(1U)
+
+#define S_SIGNAL_DET_LN4    12
+#define V_SIGNAL_DET_LN4(x) ((x) << S_SIGNAL_DET_LN4)
+#define F_SIGNAL_DET_LN4    V_SIGNAL_DET_LN4(1U)
+
+#define S_SIGNAL_DET_LN3    11
+#define V_SIGNAL_DET_LN3(x) ((x) << S_SIGNAL_DET_LN3)
+#define F_SIGNAL_DET_LN3    V_SIGNAL_DET_LN3(1U)
+
+#define S_SIGNAL_DET_LN2    10
+#define V_SIGNAL_DET_LN2(x) ((x) << S_SIGNAL_DET_LN2)
+#define F_SIGNAL_DET_LN2    V_SIGNAL_DET_LN2(1U)
+
+#define S_SIGNAL_DET_LN1    9
+#define V_SIGNAL_DET_LN1(x) ((x) << S_SIGNAL_DET_LN1)
+#define F_SIGNAL_DET_LN1    V_SIGNAL_DET_LN1(1U)
+
+#define S_SIGNAL_DET_LN0    8
+#define V_SIGNAL_DET_LN0(x) ((x) << S_SIGNAL_DET_LN0)
+#define F_SIGNAL_DET_LN0    V_SIGNAL_DET_LN0(1U)
+
+#define S_SIGDETCTRL_LN7    7
+#define V_SIGDETCTRL_LN7(x) ((x) << S_SIGDETCTRL_LN7)
+#define F_SIGDETCTRL_LN7    V_SIGDETCTRL_LN7(1U)
+
+#define S_SIGDETCTRL_LN6    6
+#define V_SIGDETCTRL_LN6(x) ((x) << S_SIGDETCTRL_LN6)
+#define F_SIGDETCTRL_LN6    V_SIGDETCTRL_LN6(1U)
+
+#define S_SIGDETCTRL_LN5    5
+#define V_SIGDETCTRL_LN5(x) ((x) << S_SIGDETCTRL_LN5)
+#define F_SIGDETCTRL_LN5    V_SIGDETCTRL_LN5(1U)
+
+#define S_SIGDETCTRL_LN4    4
+#define V_SIGDETCTRL_LN4(x) ((x) << S_SIGDETCTRL_LN4)
+#define F_SIGDETCTRL_LN4    V_SIGDETCTRL_LN4(1U)
+
+#define S_SIGDETCTRL_LN3    3
+#define V_SIGDETCTRL_LN3(x) ((x) << S_SIGDETCTRL_LN3)
+#define F_SIGDETCTRL_LN3    V_SIGDETCTRL_LN3(1U)
+
+#define S_SIGDETCTRL_LN2    2
+#define V_SIGDETCTRL_LN2(x) ((x) << S_SIGDETCTRL_LN2)
+#define F_SIGDETCTRL_LN2    V_SIGDETCTRL_LN2(1U)
+
+#define S_SIGDETCTRL_LN1    1
+#define V_SIGDETCTRL_LN1(x) ((x) << S_SIGDETCTRL_LN1)
+#define F_SIGDETCTRL_LN1    V_SIGDETCTRL_LN1(1U)
+
+#define S_SIGDETCTRL_LN0    0
+#define V_SIGDETCTRL_LN0(x) ((x) << S_SIGDETCTRL_LN0)
+#define F_SIGDETCTRL_LN0    V_SIGDETCTRL_LN0(1U)
+
+#define A_MAC_FPGA_STATUS_FRM_BOARD 0x381f4
+
+#define S_SFP3_RX_LOS    15
+#define V_SFP3_RX_LOS(x) ((x) << S_SFP3_RX_LOS)
+#define F_SFP3_RX_LOS    V_SFP3_RX_LOS(1U)
+
+#define S_SFP3_TX_FAULT    14
+#define V_SFP3_TX_FAULT(x) ((x) << S_SFP3_TX_FAULT)
+#define F_SFP3_TX_FAULT    V_SFP3_TX_FAULT(1U)
+
+#define S_SFP3_MOD_PRES    13
+#define V_SFP3_MOD_PRES(x) ((x) << S_SFP3_MOD_PRES)
+#define F_SFP3_MOD_PRES    V_SFP3_MOD_PRES(1U)
+
+#define S_SFP2_RX_LOS    12
+#define V_SFP2_RX_LOS(x) ((x) << S_SFP2_RX_LOS)
+#define F_SFP2_RX_LOS    V_SFP2_RX_LOS(1U)
+
+#define S_SFP2_TX_FAULT    11
+#define V_SFP2_TX_FAULT(x) ((x) << S_SFP2_TX_FAULT)
+#define F_SFP2_TX_FAULT    V_SFP2_TX_FAULT(1U)
+
+#define S_SFP2_MOD_PRES    10
+#define V_SFP2_MOD_PRES(x) ((x) << S_SFP2_MOD_PRES)
+#define F_SFP2_MOD_PRES    V_SFP2_MOD_PRES(1U)
+
+#define S_SFP1_RX_LOS    9
+#define V_SFP1_RX_LOS(x) ((x) << S_SFP1_RX_LOS)
+#define F_SFP1_RX_LOS    V_SFP1_RX_LOS(1U)
+
+#define S_SFP1_TX_FAULT    8
+#define V_SFP1_TX_FAULT(x) ((x) << S_SFP1_TX_FAULT)
+#define F_SFP1_TX_FAULT    V_SFP1_TX_FAULT(1U)
+
+#define S_SFP1_MOD_PRES    7
+#define V_SFP1_MOD_PRES(x) ((x) << S_SFP1_MOD_PRES)
+#define F_SFP1_MOD_PRES    V_SFP1_MOD_PRES(1U)
+
+#define S_SFP0_RX_LOS    6
+#define V_SFP0_RX_LOS(x) ((x) << S_SFP0_RX_LOS)
+#define F_SFP0_RX_LOS    V_SFP0_RX_LOS(1U)
+
+#define S_SFP0_TX_FAULT    5
+#define V_SFP0_TX_FAULT(x) ((x) << S_SFP0_TX_FAULT)
+#define F_SFP0_TX_FAULT    V_SFP0_TX_FAULT(1U)
+
+#define S_SFP0_MOD_PRES    4
+#define V_SFP0_MOD_PRES(x) ((x) << S_SFP0_MOD_PRES)
+#define F_SFP0_MOD_PRES    V_SFP0_MOD_PRES(1U)
+
+#define S_QSFP1_INT_L    3
+#define V_QSFP1_INT_L(x) ((x) << S_QSFP1_INT_L)
+#define F_QSFP1_INT_L    V_QSFP1_INT_L(1U)
+
+#define S_QSFP1_MOD_PRES    2
+#define V_QSFP1_MOD_PRES(x) ((x) << S_QSFP1_MOD_PRES)
+#define F_QSFP1_MOD_PRES    V_QSFP1_MOD_PRES(1U)
+
+#define S_QSFP0_INT_L    1
+#define V_QSFP0_INT_L(x) ((x) << S_QSFP0_INT_L)
+#define F_QSFP0_INT_L    V_QSFP0_INT_L(1U)
+
+#define S_QSFP0_MOD_PRES    0
+#define V_QSFP0_MOD_PRES(x) ((x) << S_QSFP0_MOD_PRES)
+#define F_QSFP0_MOD_PRES    V_QSFP0_MOD_PRES(1U)
+
+#define A_MAC_FPGA_CONTROL_TO_BOARD 0x381f8
+
+#define S_T7_1_LB_MODE    10
+#define M_T7_1_LB_MODE    0x3U
+#define V_T7_1_LB_MODE(x) ((x) << S_T7_1_LB_MODE)
+#define G_T7_1_LB_MODE(x) (((x) >> S_T7_1_LB_MODE) & M_T7_1_LB_MODE)
+
+#define S_SFP3_TX_DISABLE    9
+#define V_SFP3_TX_DISABLE(x) ((x) << S_SFP3_TX_DISABLE)
+#define F_SFP3_TX_DISABLE    V_SFP3_TX_DISABLE(1U)
+
+#define S_SFP2_TX_DISABLE    8
+#define V_SFP2_TX_DISABLE(x) ((x) << S_SFP2_TX_DISABLE)
+#define F_SFP2_TX_DISABLE    V_SFP2_TX_DISABLE(1U)
+
+#define S_SFP1_TX_DISABLE    7
+#define V_SFP1_TX_DISABLE(x) ((x) << S_SFP1_TX_DISABLE)
+#define F_SFP1_TX_DISABLE    V_SFP1_TX_DISABLE(1U)
+
+#define S_SFP0_TX_DISABLE    6
+#define V_SFP0_TX_DISABLE(x) ((x) << S_SFP0_TX_DISABLE)
+#define F_SFP0_TX_DISABLE    V_SFP0_TX_DISABLE(1U)
+
+#define S_QSFP1_LPMODE    5
+#define V_QSFP1_LPMODE(x) ((x) << S_QSFP1_LPMODE)
+#define F_QSFP1_LPMODE    V_QSFP1_LPMODE(1U)
+
+#define S_QSFP1_MODSEL_L    4
+#define V_QSFP1_MODSEL_L(x) ((x) << S_QSFP1_MODSEL_L)
+#define F_QSFP1_MODSEL_L    V_QSFP1_MODSEL_L(1U)
+
+#define S_QSFP1_RESET_L    3
+#define V_QSFP1_RESET_L(x) ((x) << S_QSFP1_RESET_L)
+#define F_QSFP1_RESET_L    V_QSFP1_RESET_L(1U)
+
+#define S_QSFP0_LPMODE    2
+#define V_QSFP0_LPMODE(x) ((x) << S_QSFP0_LPMODE)
+#define F_QSFP0_LPMODE    V_QSFP0_LPMODE(1U)
+
+#define S_QSFP0_MODSEL_L    1
+#define V_QSFP0_MODSEL_L(x) ((x) << S_QSFP0_MODSEL_L)
+#define F_QSFP0_MODSEL_L    V_QSFP0_MODSEL_L(1U)
+
+#define S_QSFP0_RESET_L    0
+#define V_QSFP0_RESET_L(x) ((x) << S_QSFP0_RESET_L)
+#define F_QSFP0_RESET_L    V_QSFP0_RESET_L(1U)
+
+#define A_MAC_FPGA_LINK_STATUS 0x381fc
+
+#define S_PORT3_FPGA_LINK_UP    3
+#define V_PORT3_FPGA_LINK_UP(x) ((x) << S_PORT3_FPGA_LINK_UP)
+#define F_PORT3_FPGA_LINK_UP    V_PORT3_FPGA_LINK_UP(1U)
+
+#define S_PORT2_FPGA_LINK_UP    2
+#define V_PORT2_FPGA_LINK_UP(x) ((x) << S_PORT2_FPGA_LINK_UP)
+#define F_PORT2_FPGA_LINK_UP    V_PORT2_FPGA_LINK_UP(1U)
+
+#define S_PORT1_FPGA_LINK_UP    1
+#define V_PORT1_FPGA_LINK_UP(x) ((x) << S_PORT1_FPGA_LINK_UP)
+#define F_PORT1_FPGA_LINK_UP    V_PORT1_FPGA_LINK_UP(1U)
+
+#define S_PORT0_FPGA_LINK_UP    0
+#define V_PORT0_FPGA_LINK_UP(x) ((x) << S_PORT0_FPGA_LINK_UP)
+#define F_PORT0_FPGA_LINK_UP    V_PORT0_FPGA_LINK_UP(1U)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_REVISION 0x38200
+
+#define S_MTIP_REV_400G_0    0
+#define M_MTIP_REV_400G_0    0xffU
+#define V_MTIP_REV_400G_0(x) ((x) << S_MTIP_REV_400G_0)
+#define G_MTIP_REV_400G_0(x) (((x) >> S_MTIP_REV_400G_0) & M_MTIP_REV_400G_0)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_SCRATCH 0x38204
+#define A_MAC_MTIP_MAC400G_0_MTIP_COMMAND_CONFIG 0x38208
+
+#define S_INV_LOOP    31
+#define V_INV_LOOP(x) ((x) << S_INV_LOOP)
+#define F_INV_LOOP    V_INV_LOOP(1U)
+
+#define S_TX_FLUSH_ENABLE_400G_0    22
+#define V_TX_FLUSH_ENABLE_400G_0(x) ((x) << S_TX_FLUSH_ENABLE_400G_0)
+#define F_TX_FLUSH_ENABLE_400G_0    V_TX_FLUSH_ENABLE_400G_0(1U)
+
+#define S_PHY_LOOPBACK_EN_400G    10
+#define V_PHY_LOOPBACK_EN_400G(x) ((x) << S_PHY_LOOPBACK_EN_400G)
+#define F_PHY_LOOPBACK_EN_400G    V_PHY_LOOPBACK_EN_400G(1U)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_0 0x3820c
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1 0x38210
+#define A_MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH 0x38214
+#define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS 0x3821c
+#define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS 0x38220
+#define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E 0x38224
+#define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_ALMOST_F_E 0x38228
+#define A_MAC_MTIP_MAC400G_0_MTIP_HASHTABLE_LOAD 0x3822c
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_STATUS 0x38240
+#define A_MAC_MTIP_MAC400G_0_MTIP_TX_IPG_LENGTH 0x38244
+
+#define S_T7_IPG    19
+#define M_T7_IPG    0x1fffU
+#define V_T7_IPG(x) ((x) << S_T7_IPG)
+#define G_T7_IPG(x) (((x) >> S_T7_IPG) & M_T7_IPG)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA 0x38254
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA 0x38258
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA 0x3825c
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA 0x38260
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38264
+
+#define S_CL1_PAUSE_QUANTA_THRESH    16
+#define M_CL1_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL1_PAUSE_QUANTA_THRESH(x) ((x) << S_CL1_PAUSE_QUANTA_THRESH)
+#define G_CL1_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL1_PAUSE_QUANTA_THRESH) & M_CL1_PAUSE_QUANTA_THRESH)
+
+#define S_CL0_PAUSE_QUANTA_THRESH    0
+#define M_CL0_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL0_PAUSE_QUANTA_THRESH(x) ((x) << S_CL0_PAUSE_QUANTA_THRESH)
+#define G_CL0_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL0_PAUSE_QUANTA_THRESH) & M_CL0_PAUSE_QUANTA_THRESH)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38268
+
+#define S_CL3_PAUSE_QUANTA_THRESH    16
+#define M_CL3_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL3_PAUSE_QUANTA_THRESH(x) ((x) << S_CL3_PAUSE_QUANTA_THRESH)
+#define G_CL3_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL3_PAUSE_QUANTA_THRESH) & M_CL3_PAUSE_QUANTA_THRESH)
+
+#define S_CL2_PAUSE_QUANTA_THRESH    0
+#define M_CL2_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL2_PAUSE_QUANTA_THRESH(x) ((x) << S_CL2_PAUSE_QUANTA_THRESH)
+#define G_CL2_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL2_PAUSE_QUANTA_THRESH) & M_CL2_PAUSE_QUANTA_THRESH)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3826c
+
+#define S_CL5_PAUSE_QUANTA_THRESH    16
+#define M_CL5_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL5_PAUSE_QUANTA_THRESH(x) ((x) << S_CL5_PAUSE_QUANTA_THRESH)
+#define G_CL5_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL5_PAUSE_QUANTA_THRESH) & M_CL5_PAUSE_QUANTA_THRESH)
+
+#define S_CL4_PAUSE_QUANTA_THRESH    0
+#define M_CL4_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL4_PAUSE_QUANTA_THRESH(x) ((x) << S_CL4_PAUSE_QUANTA_THRESH)
+#define G_CL4_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL4_PAUSE_QUANTA_THRESH) & M_CL4_PAUSE_QUANTA_THRESH)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38270
+
+#define S_CL7_PAUSE_QUANTA_THRESH    16
+#define M_CL7_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL7_PAUSE_QUANTA_THRESH(x) ((x) << S_CL7_PAUSE_QUANTA_THRESH)
+#define G_CL7_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL7_PAUSE_QUANTA_THRESH) & M_CL7_PAUSE_QUANTA_THRESH)
+
+#define S_CL6_PAUSE_QUANTA_THRESH    0
+#define M_CL6_PAUSE_QUANTA_THRESH    0xffffU
+#define V_CL6_PAUSE_QUANTA_THRESH(x) ((x) << S_CL6_PAUSE_QUANTA_THRESH)
+#define G_CL6_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL6_PAUSE_QUANTA_THRESH) & M_CL6_PAUSE_QUANTA_THRESH)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_RX_PAUSE_STATUS 0x38274
+
+#define S_RX_PAUSE_STATUS    0
+#define M_RX_PAUSE_STATUS    0xffU
+#define V_RX_PAUSE_STATUS(x) ((x) << S_RX_PAUSE_STATUS)
+#define G_RX_PAUSE_STATUS(x) (((x) >> S_RX_PAUSE_STATUS) & M_RX_PAUSE_STATUS)
+
+#define A_MAC_MTIP_MAC400G_0_MTIP_TS_TIMESTAMP 0x3827c
+#define A_MAC_MTIP_MAC400G_0_MTIP_XIF_MODE 0x38280
+#define A_MAC_MTIP_MAC400G_1_MTIP_REVISION 0x38300
+
+#define S_MTIP_REV_400G_1    0
+#define M_MTIP_REV_400G_1    0xffU
+#define V_MTIP_REV_400G_1(x) ((x) << S_MTIP_REV_400G_1)
+#define G_MTIP_REV_400G_1(x) (((x) >> S_MTIP_REV_400G_1) & M_MTIP_REV_400G_1)
+
+#define A_MAC_MTIP_MAC400G_1_MTIP_SCRATCH 0x38304
+#define A_MAC_MTIP_MAC400G_1_MTIP_COMMAND_CONFIG 0x38308
+
+#define S_TX_FLUSH_ENABLE_400G_1    22
+#define V_TX_FLUSH_ENABLE_400G_1(x) ((x) << S_TX_FLUSH_ENABLE_400G_1)
+#define F_TX_FLUSH_ENABLE_400G_1    V_TX_FLUSH_ENABLE_400G_1(1U)
+
+#define S_PHY_LOOPBACK_EN_400G_1    10
+#define V_PHY_LOOPBACK_EN_400G_1(x) ((x) << S_PHY_LOOPBACK_EN_400G_1)
+#define F_PHY_LOOPBACK_EN_400G_1    V_PHY_LOOPBACK_EN_400G_1(1U)
+
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_0 0x3830c
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_1 0x38310
+#define A_MAC_MTIP_MAC400G_1_MTIP_FRM_LENGTH 0x38314
+#define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_SECTIONS 0x3831c
+#define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_SECTIONS 0x38320
+#define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_ALMOST_F_E 0x38324
+#define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_ALMOST_F_E 0x38328
+#define A_MAC_MTIP_MAC400G_1_MTIP_HASHTABLE_LOAD 0x3832c
+
+#define S_ENABLE_MCAST_RX_400G_1    8
+#define V_ENABLE_MCAST_RX_400G_1(x) ((x) << S_ENABLE_MCAST_RX_400G_1)
+#define F_ENABLE_MCAST_RX_400G_1    V_ENABLE_MCAST_RX_400G_1(1U)
+
+#define S_HASHTABLE_ADDR_400G_1    0
+#define M_HASHTABLE_ADDR_400G_1    0x3fU
+#define V_HASHTABLE_ADDR_400G_1(x) ((x) << S_HASHTABLE_ADDR_400G_1)
+#define G_HASHTABLE_ADDR_400G_1(x) (((x) >> S_HASHTABLE_ADDR_400G_1) & M_HASHTABLE_ADDR_400G_1)
+
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_STATUS 0x38340
+#define A_MAC_MTIP_MAC400G_1_MTIP_TX_IPG_LENGTH 0x38344
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA 0x38354
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA 0x38358
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA 0x3835c
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA 0x38360
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38364
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38368
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3836c
+#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38370
+#define A_MAC_MTIP_MAC400G_1_MTIP_RX_PAUSE_STATUS 0x38374
+#define A_MAC_MTIP_MAC400G_1_MTIP_TS_TIMESTAMP 0x3837c
+#define A_MAC_MTIP_MAC400G_1_MTIP_XIF_MODE 0x38380
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_1 0x38400
+
+#define S_T7_SPEED_SELECTION    2
+#define V_T7_SPEED_SELECTION(x) ((x) << S_T7_SPEED_SELECTION)
+#define F_T7_SPEED_SELECTION    V_T7_SPEED_SELECTION(1U)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_1 0x38404
+
+#define S_400G_RX_LINK_STATUS    2
+#define V_400G_RX_LINK_STATUS(x) ((x) << S_400G_RX_LINK_STATUS)
+#define F_400G_RX_LINK_STATUS    V_400G_RX_LINK_STATUS(1U)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID0 0x38408
+
+#define S_400G_DEVICE_ID0_0    0
+#define M_400G_DEVICE_ID0_0    0xffffU
+#define V_400G_DEVICE_ID0_0(x) ((x) << S_400G_DEVICE_ID0_0)
+#define G_400G_DEVICE_ID0_0(x) (((x) >> S_400G_DEVICE_ID0_0) & M_400G_DEVICE_ID0_0)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID1 0x3840c
+
+#define S_400G_DEVICE_ID1_0    0
+#define M_400G_DEVICE_ID1_0    0xffffU
+#define V_400G_DEVICE_ID1_0(x) ((x) << S_400G_DEVICE_ID1_0)
+#define G_400G_DEVICE_ID1_0(x) (((x) >> S_400G_DEVICE_ID1_0) & M_400G_DEVICE_ID1_0)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_SPEED_ABILITY 0x38410
+
+#define S_400G_CAPABLE_0    9
+#define V_400G_CAPABLE_0(x) ((x) << S_400G_CAPABLE_0)
+#define F_400G_CAPABLE_0    V_400G_CAPABLE_0(1U)
+
+#define S_200G_CAPABLE_0    8
+#define V_200G_CAPABLE_0(x) ((x) << S_200G_CAPABLE_0)
+#define F_200G_CAPABLE_0    V_200G_CAPABLE_0(1U)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG1 0x38414
+
+#define S_DEVICE_PACKAGE    3
+#define V_DEVICE_PACKAGE(x) ((x) << S_DEVICE_PACKAGE)
+#define F_DEVICE_PACKAGE    V_DEVICE_PACKAGE(1U)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG2 0x38418
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_2 0x3841c
+
+#define S_400G_PCS_TYPE_SELECTION_0    0
+#define M_400G_PCS_TYPE_SELECTION_0    0xfU
+#define V_400G_PCS_TYPE_SELECTION_0(x) ((x) << S_400G_PCS_TYPE_SELECTION_0)
+#define G_400G_PCS_TYPE_SELECTION_0(x) (((x) >> S_400G_PCS_TYPE_SELECTION_0) & M_400G_PCS_TYPE_SELECTION_0)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_2 0x38420
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_3 0x38424
+
+#define S_T7_DEVICE_PRESENT    2
+#define M_T7_DEVICE_PRESENT    0x3fffU
+#define V_T7_DEVICE_PRESENT(x) ((x) << S_T7_DEVICE_PRESENT)
+#define G_T7_DEVICE_PRESENT(x) (((x) >> S_T7_DEVICE_PRESENT) & M_T7_DEVICE_PRESENT)
+
+#define S_400GBASE_R    1
+#define V_400GBASE_R(x) ((x) << S_400GBASE_R)
+#define F_400GBASE_R    V_400GBASE_R(1U)
+
+#define S_200GBASE_R    0
+#define V_200GBASE_R(x) ((x) << S_200GBASE_R)
+#define F_200GBASE_R    V_200GBASE_R(1U)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID0 0x38438
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID1 0x3843c
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_1 0x38480
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_2 0x38484
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_CONTROL 0x384a8
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_ERR_CNT 0x384ac
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BER_HIGH_ORDER_CNT 0x384b0
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x384b4
+
+#define S_HIGH_ORDER    15
+#define V_HIGH_ORDER(x) ((x) << S_HIGH_ORDER)
+#define F_HIGH_ORDER    V_HIGH_ORDER(1U)
+
+#define S_ERROR_BLOCK_COUNTER    0
+#define M_ERROR_BLOCK_COUNTER    0x3fffU
+#define V_ERROR_BLOCK_COUNTER(x) ((x) << S_ERROR_BLOCK_COUNTER)
+#define G_ERROR_BLOCK_COUNTER(x) (((x) >> S_ERROR_BLOCK_COUNTER) & M_ERROR_BLOCK_COUNTER)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x384c8
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x384cc
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x384d0
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x384d4
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_0_MAPPING 0x384d8
+
+#define S_T7_LANE_0_MAPPING    0
+#define M_T7_LANE_0_MAPPING    0xfU
+#define V_T7_LANE_0_MAPPING(x) ((x) << S_T7_LANE_0_MAPPING)
+#define G_T7_LANE_0_MAPPING(x) (((x) >> S_T7_LANE_0_MAPPING) & M_T7_LANE_0_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_1_MAPPING 0x384dc
+
+#define S_T7_LANE_1_MAPPING    0
+#define M_T7_LANE_1_MAPPING    0xfU
+#define V_T7_LANE_1_MAPPING(x) ((x) << S_T7_LANE_1_MAPPING)
+#define G_T7_LANE_1_MAPPING(x) (((x) >> S_T7_LANE_1_MAPPING) & M_T7_LANE_1_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_2_MAPPING 0x384e0
+
+#define S_T7_LANE_2_MAPPING    0
+#define M_T7_LANE_2_MAPPING    0xfU
+#define V_T7_LANE_2_MAPPING(x) ((x) << S_T7_LANE_2_MAPPING)
+#define G_T7_LANE_2_MAPPING(x) (((x) >> S_T7_LANE_2_MAPPING) & M_T7_LANE_2_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_3_MAPPING 0x384e4
+
+#define S_T7_LANE_3_MAPPING    0
+#define M_T7_LANE_3_MAPPING    0xfU
+#define V_T7_LANE_3_MAPPING(x) ((x) << S_T7_LANE_3_MAPPING)
+#define G_T7_LANE_3_MAPPING(x) (((x) >> S_T7_LANE_3_MAPPING) & M_T7_LANE_3_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_4_MAPPING 0x384e8
+
+#define S_T7_LANE_4_MAPPING    0
+#define M_T7_LANE_4_MAPPING    0xfU
+#define V_T7_LANE_4_MAPPING(x) ((x) << S_T7_LANE_4_MAPPING)
+#define G_T7_LANE_4_MAPPING(x) (((x) >> S_T7_LANE_4_MAPPING) & M_T7_LANE_4_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_5_MAPPING 0x384ec
+
+#define S_T7_LANE_5_MAPPING    0
+#define M_T7_LANE_5_MAPPING    0xfU
+#define V_T7_LANE_5_MAPPING(x) ((x) << S_T7_LANE_5_MAPPING)
+#define G_T7_LANE_5_MAPPING(x) (((x) >> S_T7_LANE_5_MAPPING) & M_T7_LANE_5_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_6_MAPPING 0x384f0
+
+#define S_T7_LANE_6_MAPPING    0
+#define M_T7_LANE_6_MAPPING    0xfU
+#define V_T7_LANE_6_MAPPING(x) ((x) << S_T7_LANE_6_MAPPING)
+#define G_T7_LANE_6_MAPPING(x) (((x) >> S_T7_LANE_6_MAPPING) & M_T7_LANE_6_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_7_MAPPING 0x384f4
+
+#define S_T7_LANE_7_MAPPING    0
+#define M_T7_LANE_7_MAPPING    0xfU
+#define V_T7_LANE_7_MAPPING(x) ((x) << S_T7_LANE_7_MAPPING)
+#define G_T7_LANE_7_MAPPING(x) (((x) >> S_T7_LANE_7_MAPPING) & M_T7_LANE_7_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_8_MAPPING 0x384f8
+
+#define S_T7_LANE_8_MAPPING    0
+#define M_T7_LANE_8_MAPPING    0xfU
+#define V_T7_LANE_8_MAPPING(x) ((x) << S_T7_LANE_8_MAPPING)
+#define G_T7_LANE_8_MAPPING(x) (((x) >> S_T7_LANE_8_MAPPING) & M_T7_LANE_8_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_9_MAPPING 0x384fc
+
+#define S_T7_LANE_9_MAPPING    0
+#define M_T7_LANE_9_MAPPING    0xfU
+#define V_T7_LANE_9_MAPPING(x) ((x) << S_T7_LANE_9_MAPPING)
+#define G_T7_LANE_9_MAPPING(x) (((x) >> S_T7_LANE_9_MAPPING) & M_T7_LANE_9_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_10_MAPPING 0x38500
+
+#define S_T7_LANE_10_MAPPING    0
+#define M_T7_LANE_10_MAPPING    0xfU
+#define V_T7_LANE_10_MAPPING(x) ((x) << S_T7_LANE_10_MAPPING)
+#define G_T7_LANE_10_MAPPING(x) (((x) >> S_T7_LANE_10_MAPPING) & M_T7_LANE_10_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_11_MAPPING 0x38504
+
+#define S_T7_LANE_11_MAPPING    0
+#define M_T7_LANE_11_MAPPING    0xfU
+#define V_T7_LANE_11_MAPPING(x) ((x) << S_T7_LANE_11_MAPPING)
+#define G_T7_LANE_11_MAPPING(x) (((x) >> S_T7_LANE_11_MAPPING) & M_T7_LANE_11_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_12_MAPPING 0x38508
+
+#define S_T7_LANE_12_MAPPING    0
+#define M_T7_LANE_12_MAPPING    0xfU
+#define V_T7_LANE_12_MAPPING(x) ((x) << S_T7_LANE_12_MAPPING)
+#define G_T7_LANE_12_MAPPING(x) (((x) >> S_T7_LANE_12_MAPPING) & M_T7_LANE_12_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_13_MAPPING 0x3850c
+
+#define S_T7_LANE_13_MAPPING    0
+#define M_T7_LANE_13_MAPPING    0xfU
+#define V_T7_LANE_13_MAPPING(x) ((x) << S_T7_LANE_13_MAPPING)
+#define G_T7_LANE_13_MAPPING(x) (((x) >> S_T7_LANE_13_MAPPING) & M_T7_LANE_13_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_14_MAPPING 0x38510
+
+#define S_T7_LANE_14_MAPPING    0
+#define M_T7_LANE_14_MAPPING    0xfU
+#define V_T7_LANE_14_MAPPING(x) ((x) << S_T7_LANE_14_MAPPING)
+#define G_T7_LANE_14_MAPPING(x) (((x) >> S_T7_LANE_14_MAPPING) & M_T7_LANE_14_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_15_MAPPING 0x38514
+
+#define S_T7_LANE_15_MAPPING    0
+#define M_T7_LANE_15_MAPPING    0xfU
+#define V_T7_LANE_15_MAPPING(x) ((x) << S_T7_LANE_15_MAPPING)
+#define G_T7_LANE_15_MAPPING(x) (((x) >> S_T7_LANE_15_MAPPING) & M_T7_LANE_15_MAPPING)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_SCRATCH 0x38600
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CORE_REVISION 0x38604
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CL_INTVL 0x38608
+
+#define S_T7_VL_INTVL    0
+#define M_T7_VL_INTVL    0xffffU
+#define V_T7_VL_INTVL(x) ((x) << S_T7_VL_INTVL)
+#define G_T7_VL_INTVL(x) (((x) >> S_T7_VL_INTVL) & M_T7_VL_INTVL)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_LANE_THRESH 0x3860c
+
+#define S_TX_LANE_THRESH    0
+#define M_TX_LANE_THRESH    0xfU
+#define V_TX_LANE_THRESH(x) ((x) << S_TX_LANE_THRESH)
+#define G_TX_LANE_THRESH(x) (((x) >> S_TX_LANE_THRESH) & M_TX_LANE_THRESH)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_CDMII_PACE 0x3861c
+
+#define S_TX_CDMII_PACE    0
+#define M_TX_CDMII_PACE    0xfU
+#define V_TX_CDMII_PACE(x) ((x) << S_TX_CDMII_PACE)
+#define G_TX_CDMII_PACE(x) (((x) >> S_TX_CDMII_PACE) & M_TX_CDMII_PACE)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_0 0x38620
+
+#define S_AM_0    0
+#define M_AM_0    0xffffU
+#define V_AM_0(x) ((x) << S_AM_0)
+#define G_AM_0(x) (((x) >> S_AM_0) & M_AM_0)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_1 0x38624
+
+#define S_AM_1    0
+#define M_AM_1    0xffffU
+#define V_AM_1(x) ((x) << S_AM_1)
+#define G_AM_1(x) (((x) >> S_AM_1) & M_AM_1)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO0 0x38800
+
+#define S_DBGINFO0    0
+#define M_DBGINFO0    0xffffU
+#define V_DBGINFO0(x) ((x) << S_DBGINFO0)
+#define G_DBGINFO0(x) (((x) >> S_DBGINFO0) & M_DBGINFO0)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO1 0x38804
+
+#define S_DBGINFO1    0
+#define M_DBGINFO1    0xffffU
+#define V_DBGINFO1(x) ((x) << S_DBGINFO1)
+#define G_DBGINFO1(x) (((x) >> S_DBGINFO1) & M_DBGINFO1)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO2 0x38808
+
+#define S_DBGINFO2    0
+#define M_DBGINFO2    0xffffU
+#define V_DBGINFO2(x) ((x) << S_DBGINFO2)
+#define G_DBGINFO2(x) (((x) >> S_DBGINFO2) & M_DBGINFO2)
+
+#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO3 0x3880c
+
+#define S_DBGINFO3    0
+#define M_DBGINFO3    0xffffU
+#define V_DBGINFO3(x) ((x) << S_DBGINFO3)
+#define G_DBGINFO3(x) (((x) >> S_DBGINFO3) & M_DBGINFO3)
+
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_1 0x38900
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_1 0x38904
+
+#define S_400G_RX_LINK_STATUS_1    2
+#define V_400G_RX_LINK_STATUS_1(x) ((x) << S_400G_RX_LINK_STATUS_1)
+#define F_400G_RX_LINK_STATUS_1    V_400G_RX_LINK_STATUS_1(1U)
+
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID0 0x38908
+
+#define S_400G_DEVICE_ID0_1    0
+#define M_400G_DEVICE_ID0_1    0xffffU
+#define V_400G_DEVICE_ID0_1(x) ((x) << S_400G_DEVICE_ID0_1)
+#define G_400G_DEVICE_ID0_1(x) (((x) >> S_400G_DEVICE_ID0_1) & M_400G_DEVICE_ID0_1)
+
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID1 0x3890c
+
+#define S_400G_DEVICE_ID1_1    0
+#define M_400G_DEVICE_ID1_1    0xffffU
+#define V_400G_DEVICE_ID1_1(x) ((x) << S_400G_DEVICE_ID1_1)
+#define G_400G_DEVICE_ID1_1(x) (((x) >> S_400G_DEVICE_ID1_1) & M_400G_DEVICE_ID1_1)
+
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_SPEED_ABILITY 0x38910
+
+#define S_400G_CAPABLE_1    9
+#define V_400G_CAPABLE_1(x) ((x) << S_400G_CAPABLE_1)
+#define F_400G_CAPABLE_1    V_400G_CAPABLE_1(1U)
+
+#define S_200G_CAPABLE_1    8
+#define V_200G_CAPABLE_1(x) ((x) << S_200G_CAPABLE_1)
+#define F_200G_CAPABLE_1    V_200G_CAPABLE_1(1U)
+
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG1 0x38914
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG2 0x38918
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_2 0x3891c
+
+#define S_400G_PCS_TYPE_SELECTION_1    0
+#define M_400G_PCS_TYPE_SELECTION_1    0xfU
+#define V_400G_PCS_TYPE_SELECTION_1(x) ((x) << S_400G_PCS_TYPE_SELECTION_1)
+#define G_400G_PCS_TYPE_SELECTION_1(x) (((x) >> S_400G_PCS_TYPE_SELECTION_1) & M_400G_PCS_TYPE_SELECTION_1)
+
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_2 0x38920
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_3 0x38924
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID0 0x38938
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID1 0x3893c
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_1 0x38980
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_2 0x38984
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_CONTROL 0x389a8
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_ERR_CNT 0x389ac
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BER_HIGH_ORDER_CNT 0x389b0
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x389b4
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x389c8
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x389cc
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x389d0
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x389d4
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_0_MAPPING 0x389d8
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_1_MAPPING 0x389dc
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_2_MAPPING 0x389e0
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_3_MAPPING 0x389e4
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_4_MAPPING 0x389e8
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_5_MAPPING 0x389ec
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_6_MAPPING 0x389f0
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_7_MAPPING 0x389f4
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_8_MAPPING 0x389f8
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_9_MAPPING 0x389fc
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_10_MAPPING 0x38a00
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_11_MAPPING 0x38a04
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_12_MAPPING 0x38a08
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_13_MAPPING 0x38a0c
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_14_MAPPING 0x38a10
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_15_MAPPING 0x38a14
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_SCRATCH 0x38b00
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CORE_REVISION 0x38b04
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CL_INTVL 0x38b08
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_LANE_THRESH 0x38b0c
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_CDMII_PACE 0x38b1c
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_0 0x38b20
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_1 0x38b24
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO0 0x38d00
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO1 0x38d04
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO2 0x38d08
+#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO3 0x38d0c
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_0 0x38e00
+
+#define S_TC_PAD_ALTER    10
+#define V_TC_PAD_ALTER(x) ((x) << S_TC_PAD_ALTER)
+#define F_TC_PAD_ALTER    V_TC_PAD_ALTER(1U)
+
+#define S_TC_PAD_VALUE    9
+#define V_TC_PAD_VALUE(x) ((x) << S_TC_PAD_VALUE)
+#define F_TC_PAD_VALUE    V_TC_PAD_VALUE(1U)
+
+#define S_KP_ENABLE    8
+#define V_KP_ENABLE(x) ((x) << S_KP_ENABLE)
+#define F_KP_ENABLE    V_KP_ENABLE(1U)
+
+#define S_AM16_COPY_DIS    3
+#define V_AM16_COPY_DIS(x) ((x) << S_AM16_COPY_DIS)
+#define F_AM16_COPY_DIS    V_AM16_COPY_DIS(1U)
+
+#define S_RS_FEC_DEGRADE_OPTION_ENA    2
+#define V_RS_FEC_DEGRADE_OPTION_ENA(x) ((x) << S_RS_FEC_DEGRADE_OPTION_ENA)
+#define F_RS_FEC_DEGRADE_OPTION_ENA    V_RS_FEC_DEGRADE_OPTION_ENA(1U)
+
+#define A_MAC_MTIP_RS_FEC_STATUS_0_0 0x38e04
+
+#define S_FEC_STATUS_0_14    14
+#define V_FEC_STATUS_0_14(x) ((x) << S_FEC_STATUS_0_14)
+#define F_FEC_STATUS_0_14    V_FEC_STATUS_0_14(1U)
+
+#define S_FEC_STATUS_0_11    8
+#define M_FEC_STATUS_0_11    0xfU
+#define V_FEC_STATUS_0_11(x) ((x) << S_FEC_STATUS_0_11)
+#define G_FEC_STATUS_0_11(x) (((x) >> S_FEC_STATUS_0_11) & M_FEC_STATUS_0_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED0_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED0_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED0_0    V_RS_FEC_DEGRADE_SER_RECEIVED0_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED0_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED0_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED0_1    V_RS_FEC_DEGRADE_SER_RECEIVED0_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED0_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED0_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED0_2    V_RS_FEC_DEGRADE_SER_RECEIVED0_2(1U)
+
+#define S_FEC_STATUS_0_4    4
+#define V_FEC_STATUS_0_4(x) ((x) << S_FEC_STATUS_0_4)
+#define F_FEC_STATUS_0_4    V_FEC_STATUS_0_4(1U)
+
+#define S_FEC_STATUS_0_3    3
+#define V_FEC_STATUS_0_3(x) ((x) << S_FEC_STATUS_0_3)
+#define F_FEC_STATUS_0_3    V_FEC_STATUS_0_3(1U)
+
+#define S_FEC_STATUS_0_2    2
+#define V_FEC_STATUS_0_2(x) ((x) << S_FEC_STATUS_0_2)
+#define F_FEC_STATUS_0_2    V_FEC_STATUS_0_2(1U)
+
+#define S_FEC_STATUS_0_1    1
+#define V_FEC_STATUS_0_1(x) ((x) << S_FEC_STATUS_0_1)
+#define F_FEC_STATUS_0_1    V_FEC_STATUS_0_1(1U)
+
+#define S_FEC_STATUS_0_0    0
+#define V_FEC_STATUS_0_0(x) ((x) << S_FEC_STATUS_0_0)
+#define F_FEC_STATUS_0_0    V_FEC_STATUS_0_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_0 0x38e08
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_0 0x38e0c
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_0 0x38e10
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_0 0x38e14
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_0 0x38e18
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_0 0x38e1c
+
+#define S_DEC_TRESH    0
+#define M_DEC_TRESH    0x3fU
+#define V_DEC_TRESH(x) ((x) << S_DEC_TRESH)
+#define G_DEC_TRESH(x) (((x) >> S_DEC_TRESH) & M_DEC_TRESH)
+
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_1 0x38e20
+#define A_MAC_MTIP_RS_FEC_STATUS_0_1 0x38e24
+
+#define S_FEC_STATUS_1_14    14
+#define V_FEC_STATUS_1_14(x) ((x) << S_FEC_STATUS_1_14)
+#define F_FEC_STATUS_1_14    V_FEC_STATUS_1_14(1U)
+
+#define S_FEC_STATUS_1_11    8
+#define M_FEC_STATUS_1_11    0xfU
+#define V_FEC_STATUS_1_11(x) ((x) << S_FEC_STATUS_1_11)
+#define G_FEC_STATUS_1_11(x) (((x) >> S_FEC_STATUS_1_11) & M_FEC_STATUS_1_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED1_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED1_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED1_0    V_RS_FEC_DEGRADE_SER_RECEIVED1_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED1_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED1_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED1_1    V_RS_FEC_DEGRADE_SER_RECEIVED1_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED1_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED1_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED1_2    V_RS_FEC_DEGRADE_SER_RECEIVED1_2(1U)
+
+#define S_FEC_STATUS_1_4    4
+#define V_FEC_STATUS_1_4(x) ((x) << S_FEC_STATUS_1_4)
+#define F_FEC_STATUS_1_4    V_FEC_STATUS_1_4(1U)
+
+#define S_FEC_STATUS_1_3    3
+#define V_FEC_STATUS_1_3(x) ((x) << S_FEC_STATUS_1_3)
+#define F_FEC_STATUS_1_3    V_FEC_STATUS_1_3(1U)
+
+#define S_FEC_STATUS_1_2    2
+#define V_FEC_STATUS_1_2(x) ((x) << S_FEC_STATUS_1_2)
+#define F_FEC_STATUS_1_2    V_FEC_STATUS_1_2(1U)
+
+#define S_FEC_STATUS_1_1    1
+#define V_FEC_STATUS_1_1(x) ((x) << S_FEC_STATUS_1_1)
+#define F_FEC_STATUS_1_1    V_FEC_STATUS_1_1(1U)
+
+#define S_FEC_STATUS_1_0    0
+#define V_FEC_STATUS_1_0(x) ((x) << S_FEC_STATUS_1_0)
+#define F_FEC_STATUS_1_0    V_FEC_STATUS_1_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_1 0x38e28
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_1 0x38e2c
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_1 0x38e30
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_1 0x38e34
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_1 0x38e38
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_1 0x38e3c
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_2 0x38e40
+#define A_MAC_MTIP_RS_FEC_STATUS_0_2 0x38e44
+
+#define S_FEC_STATUS_2_14    14
+#define V_FEC_STATUS_2_14(x) ((x) << S_FEC_STATUS_2_14)
+#define F_FEC_STATUS_2_14    V_FEC_STATUS_2_14(1U)
+
+#define S_FEC_STATUS_2_11    8
+#define M_FEC_STATUS_2_11    0xfU
+#define V_FEC_STATUS_2_11(x) ((x) << S_FEC_STATUS_2_11)
+#define G_FEC_STATUS_2_11(x) (((x) >> S_FEC_STATUS_2_11) & M_FEC_STATUS_2_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED2_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED2_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED2_0    V_RS_FEC_DEGRADE_SER_RECEIVED2_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED2_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED2_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED2_1    V_RS_FEC_DEGRADE_SER_RECEIVED2_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED2_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED2_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED2_2    V_RS_FEC_DEGRADE_SER_RECEIVED2_2(1U)
+
+#define S_FEC_STATUS_2_4    4
+#define V_FEC_STATUS_2_4(x) ((x) << S_FEC_STATUS_2_4)
+#define F_FEC_STATUS_2_4    V_FEC_STATUS_2_4(1U)
+
+#define S_FEC_STATUS_2_3    3
+#define V_FEC_STATUS_2_3(x) ((x) << S_FEC_STATUS_2_3)
+#define F_FEC_STATUS_2_3    V_FEC_STATUS_2_3(1U)
+
+#define S_FEC_STATUS_2_2    2
+#define V_FEC_STATUS_2_2(x) ((x) << S_FEC_STATUS_2_2)
+#define F_FEC_STATUS_2_2    V_FEC_STATUS_2_2(1U)
+
+#define S_FEC_STATUS_2_1    1
+#define V_FEC_STATUS_2_1(x) ((x) << S_FEC_STATUS_2_1)
+#define F_FEC_STATUS_2_1    V_FEC_STATUS_2_1(1U)
+
+#define S_FEC_STATUS_2_0    0
+#define V_FEC_STATUS_2_0(x) ((x) << S_FEC_STATUS_2_0)
+#define F_FEC_STATUS_2_0    V_FEC_STATUS_2_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_2 0x38e48
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_2 0x38e4c
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_2 0x38e50
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_2 0x38e54
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_2 0x38e58
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_2 0x38e5c
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_3 0x38e60
+#define A_MAC_MTIP_RS_FEC_STATUS_0_3 0x38e64
+
+#define S_FEC_STATUS_3_14    14
+#define V_FEC_STATUS_3_14(x) ((x) << S_FEC_STATUS_3_14)
+#define F_FEC_STATUS_3_14    V_FEC_STATUS_3_14(1U)
+
+#define S_FEC_STATUS_3_11    8
+#define M_FEC_STATUS_3_11    0xfU
+#define V_FEC_STATUS_3_11(x) ((x) << S_FEC_STATUS_3_11)
+#define G_FEC_STATUS_3_11(x) (((x) >> S_FEC_STATUS_3_11) & M_FEC_STATUS_3_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED3_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED3_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED3_0    V_RS_FEC_DEGRADE_SER_RECEIVED3_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED3_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED3_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED3_1    V_RS_FEC_DEGRADE_SER_RECEIVED3_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED3_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED3_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED3_2    V_RS_FEC_DEGRADE_SER_RECEIVED3_2(1U)
+
+#define S_FEC_STATUS_3_4    4
+#define V_FEC_STATUS_3_4(x) ((x) << S_FEC_STATUS_3_4)
+#define F_FEC_STATUS_3_4    V_FEC_STATUS_3_4(1U)
+
+#define S_FEC_STATUS_3_3    3
+#define V_FEC_STATUS_3_3(x) ((x) << S_FEC_STATUS_3_3)
+#define F_FEC_STATUS_3_3    V_FEC_STATUS_3_3(1U)
+
+#define S_FEC_STATUS_3_2    2
+#define V_FEC_STATUS_3_2(x) ((x) << S_FEC_STATUS_3_2)
+#define F_FEC_STATUS_3_2    V_FEC_STATUS_3_2(1U)
+
+#define S_FEC_STATUS_3_1    1
+#define V_FEC_STATUS_3_1(x) ((x) << S_FEC_STATUS_3_1)
+#define F_FEC_STATUS_3_1    V_FEC_STATUS_3_1(1U)
+
+#define S_FEC_STATUS_3_0    0
+#define V_FEC_STATUS_3_0(x) ((x) << S_FEC_STATUS_3_0)
+#define F_FEC_STATUS_3_0    V_FEC_STATUS_3_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_3 0x38e68
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_3 0x38e6c
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_3 0x38e70
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_3 0x38e74
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_3 0x38e78
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_3 0x38e7c
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_4 0x38e80
+#define A_MAC_MTIP_RS_FEC_STATUS_0_4 0x38e84
+
+#define S_FEC_STATUS_4_14    14
+#define V_FEC_STATUS_4_14(x) ((x) << S_FEC_STATUS_4_14)
+#define F_FEC_STATUS_4_14    V_FEC_STATUS_4_14(1U)
+
+#define S_FEC_STATUS_4_11    8
+#define M_FEC_STATUS_4_11    0xfU
+#define V_FEC_STATUS_4_11(x) ((x) << S_FEC_STATUS_4_11)
+#define G_FEC_STATUS_4_11(x) (((x) >> S_FEC_STATUS_4_11) & M_FEC_STATUS_4_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED4_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED4_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED4_0    V_RS_FEC_DEGRADE_SER_RECEIVED4_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED4_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED4_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED4_1    V_RS_FEC_DEGRADE_SER_RECEIVED4_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED4_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED4_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED4_2    V_RS_FEC_DEGRADE_SER_RECEIVED4_2(1U)
+
+#define S_FEC_STATUS_4_4    4
+#define V_FEC_STATUS_4_4(x) ((x) << S_FEC_STATUS_4_4)
+#define F_FEC_STATUS_4_4    V_FEC_STATUS_4_4(1U)
+
+#define S_FEC_STATUS_4_3    3
+#define V_FEC_STATUS_4_3(x) ((x) << S_FEC_STATUS_4_3)
+#define F_FEC_STATUS_4_3    V_FEC_STATUS_4_3(1U)
+
+#define S_FEC_STATUS_4_2    2
+#define V_FEC_STATUS_4_2(x) ((x) << S_FEC_STATUS_4_2)
+#define F_FEC_STATUS_4_2    V_FEC_STATUS_4_2(1U)
+
+#define S_FEC_STATUS_4_1    1
+#define V_FEC_STATUS_4_1(x) ((x) << S_FEC_STATUS_4_1)
+#define F_FEC_STATUS_4_1    V_FEC_STATUS_4_1(1U)
+
+#define S_FEC_STATUS_4_0    0
+#define V_FEC_STATUS_4_0(x) ((x) << S_FEC_STATUS_4_0)
+#define F_FEC_STATUS_4_0    V_FEC_STATUS_4_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_4 0x38e88
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_4 0x38e8c
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_4 0x38e90
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_4 0x38e94
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_4 0x38e98
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_4 0x38e9c
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_5 0x38ea0
+#define A_MAC_MTIP_RS_FEC_STATUS_0_5 0x38ea4
+
+#define S_FEC_STATUS_5_14    14
+#define V_FEC_STATUS_5_14(x) ((x) << S_FEC_STATUS_5_14)
+#define F_FEC_STATUS_5_14    V_FEC_STATUS_5_14(1U)
+
+#define S_FEC_STATUS_5_11    8
+#define M_FEC_STATUS_5_11    0xfU
+#define V_FEC_STATUS_5_11(x) ((x) << S_FEC_STATUS_5_11)
+#define G_FEC_STATUS_5_11(x) (((x) >> S_FEC_STATUS_5_11) & M_FEC_STATUS_5_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED5_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED5_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED5_0    V_RS_FEC_DEGRADE_SER_RECEIVED5_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED5_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED5_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED5_1    V_RS_FEC_DEGRADE_SER_RECEIVED5_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED5_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED5_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED5_2    V_RS_FEC_DEGRADE_SER_RECEIVED5_2(1U)
+
+#define S_FEC_STATUS_5_4    4
+#define V_FEC_STATUS_5_4(x) ((x) << S_FEC_STATUS_5_4)
+#define F_FEC_STATUS_5_4    V_FEC_STATUS_5_4(1U)
+
+#define S_FEC_STATUS_5_3    3
+#define V_FEC_STATUS_5_3(x) ((x) << S_FEC_STATUS_5_3)
+#define F_FEC_STATUS_5_3    V_FEC_STATUS_5_3(1U)
+
+#define S_FEC_STATUS_5_2    2
+#define V_FEC_STATUS_5_2(x) ((x) << S_FEC_STATUS_5_2)
+#define F_FEC_STATUS_5_2    V_FEC_STATUS_5_2(1U)
+
+#define S_FEC_STATUS_5_1    1
+#define V_FEC_STATUS_5_1(x) ((x) << S_FEC_STATUS_5_1)
+#define F_FEC_STATUS_5_1    V_FEC_STATUS_5_1(1U)
+
+#define S_FEC_STATUS_5_0    0
+#define V_FEC_STATUS_5_0(x) ((x) << S_FEC_STATUS_5_0)
+#define F_FEC_STATUS_5_0    V_FEC_STATUS_5_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_5 0x38ea8
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_5 0x38eac
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_5 0x38eb0
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_5 0x38eb4
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_5 0x38eb8
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_5 0x38ebc
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_6 0x38ec0
+#define A_MAC_MTIP_RS_FEC_STATUS_0_6 0x38ec4
+
+#define S_FEC_STATUS_6_14    14
+#define V_FEC_STATUS_6_14(x) ((x) << S_FEC_STATUS_6_14)
+#define F_FEC_STATUS_6_14    V_FEC_STATUS_6_14(1U)
+
+#define S_FEC_STATUS_6_11    8
+#define M_FEC_STATUS_6_11    0xfU
+#define V_FEC_STATUS_6_11(x) ((x) << S_FEC_STATUS_6_11)
+#define G_FEC_STATUS_6_11(x) (((x) >> S_FEC_STATUS_6_11) & M_FEC_STATUS_6_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED6_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED6_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED6_0    V_RS_FEC_DEGRADE_SER_RECEIVED6_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED6_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED6_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED6_1    V_RS_FEC_DEGRADE_SER_RECEIVED6_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED6_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED6_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED6_2    V_RS_FEC_DEGRADE_SER_RECEIVED6_2(1U)
+
+#define S_FEC_STATUS_6_4    4
+#define V_FEC_STATUS_6_4(x) ((x) << S_FEC_STATUS_6_4)
+#define F_FEC_STATUS_6_4    V_FEC_STATUS_6_4(1U)
+
+#define S_FEC_STATUS_6_3    3
+#define V_FEC_STATUS_6_3(x) ((x) << S_FEC_STATUS_6_3)
+#define F_FEC_STATUS_6_3    V_FEC_STATUS_6_3(1U)
+
+#define S_FEC_STATUS_6_2    2
+#define V_FEC_STATUS_6_2(x) ((x) << S_FEC_STATUS_6_2)
+#define F_FEC_STATUS_6_2    V_FEC_STATUS_6_2(1U)
+
+#define S_FEC_STATUS_6_1    1
+#define V_FEC_STATUS_6_1(x) ((x) << S_FEC_STATUS_6_1)
+#define F_FEC_STATUS_6_1    V_FEC_STATUS_6_1(1U)
+
+#define S_FEC_STATUS_6_0    0
+#define V_FEC_STATUS_6_0(x) ((x) << S_FEC_STATUS_6_0)
+#define F_FEC_STATUS_6_0    V_FEC_STATUS_6_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_6 0x38ec8
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_6 0x38ecc
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_6 0x38ed0
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_6 0x38ed4
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_6 0x38ed8
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_6 0x38edc
+#define A_MAC_MTIP_RS_FEC_CONTROL_0_7 0x38ee0
+#define A_MAC_MTIP_RS_FEC_STATUS_0_7 0x38ee4
+
+#define S_FEC_STATUS_7_14    14
+#define V_FEC_STATUS_7_14(x) ((x) << S_FEC_STATUS_7_14)
+#define F_FEC_STATUS_7_14    V_FEC_STATUS_7_14(1U)
+
+#define S_FEC_STATUS_7_11    8
+#define M_FEC_STATUS_7_11    0xfU
+#define V_FEC_STATUS_7_11(x) ((x) << S_FEC_STATUS_7_11)
+#define G_FEC_STATUS_7_11(x) (((x) >> S_FEC_STATUS_7_11) & M_FEC_STATUS_7_11)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED7_0    7
+#define V_RS_FEC_DEGRADE_SER_RECEIVED7_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_0)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED7_0    V_RS_FEC_DEGRADE_SER_RECEIVED7_0(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED7_1    6
+#define V_RS_FEC_DEGRADE_SER_RECEIVED7_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_1)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED7_1    V_RS_FEC_DEGRADE_SER_RECEIVED7_1(1U)
+
+#define S_RS_FEC_DEGRADE_SER_RECEIVED7_2    5
+#define V_RS_FEC_DEGRADE_SER_RECEIVED7_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_2)
+#define F_RS_FEC_DEGRADE_SER_RECEIVED7_2    V_RS_FEC_DEGRADE_SER_RECEIVED7_2(1U)
+
+#define S_FEC_STATUS_7_4    4
+#define V_FEC_STATUS_7_4(x) ((x) << S_FEC_STATUS_7_4)
+#define F_FEC_STATUS_7_4    V_FEC_STATUS_7_4(1U)
+
+#define S_FEC_STATUS_7_3    3
+#define V_FEC_STATUS_7_3(x) ((x) << S_FEC_STATUS_7_3)
+#define F_FEC_STATUS_7_3    V_FEC_STATUS_7_3(1U)
+
+#define S_FEC_STATUS_7_2    2
+#define V_FEC_STATUS_7_2(x) ((x) << S_FEC_STATUS_7_2)
+#define F_FEC_STATUS_7_2    V_FEC_STATUS_7_2(1U)
+
+#define S_FEC_STATUS_7_1    1
+#define V_FEC_STATUS_7_1(x) ((x) << S_FEC_STATUS_7_1)
+#define F_FEC_STATUS_7_1    V_FEC_STATUS_7_1(1U)
+
+#define S_FEC_STATUS_7_0    0
+#define V_FEC_STATUS_7_0(x) ((x) << S_FEC_STATUS_7_0)
+#define F_FEC_STATUS_7_0    V_FEC_STATUS_7_0(1U)
+
+#define A_MAC_MTIP_RS_FEC_CCW_LO_0_7 0x38ee8
+#define A_MAC_MTIP_RS_FEC_CCW_HI_0_7 0x38eec
+#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_7 0x38ef0
+#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_7 0x38ef4
+#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_7 0x38ef8
+#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_7 0x38efc
+#define A_MAC_MTIP_RS_FEC_HISER_CW 0x38f00
+
+#define S_HISER_CW    0
+#define M_HISER_CW    0xffffU
+#define V_HISER_CW(x) ((x) << S_HISER_CW)
+#define G_HISER_CW(x) (((x) >> S_HISER_CW) & M_HISER_CW)
+
+#define A_MAC_MTIP_RS_FEC_HISER_THRESH 0x38f04
+
+#define S_HISER_THRESH    0
+#define M_HISER_THRESH    0xffffU
+#define V_HISER_THRESH(x) ((x) << S_HISER_THRESH)
+#define G_HISER_THRESH(x) (((x) >> S_HISER_THRESH) & M_HISER_THRESH)
+
+#define A_MAC_MTIP_RS_FEC_HISER_TIME 0x38f08
+
+#define S_HISER_TIME    0
+#define M_HISER_TIME    0xffffU
+#define V_HISER_TIME(x) ((x) << S_HISER_TIME)
+#define G_HISER_TIME(x) (((x) >> S_HISER_TIME) & M_HISER_TIME)
+
+#define A_MAC_MTIP_RS_DEGRADE_SET_CW 0x38f10
+
+#define S_DEGRADE_SET_CW    0
+#define M_DEGRADE_SET_CW    0xffffU
+#define V_DEGRADE_SET_CW(x) ((x) << S_DEGRADE_SET_CW)
+#define G_DEGRADE_SET_CW(x) (((x) >> S_DEGRADE_SET_CW) & M_DEGRADE_SET_CW)
+
+#define A_MAC_MTIP_RS_DEGRADE_SET_CW_HI 0x38f14
+
+#define S_DEGRADE_SET_CW_HI    0
+#define M_DEGRADE_SET_CW_HI    0xffffU
+#define V_DEGRADE_SET_CW_HI(x) ((x) << S_DEGRADE_SET_CW_HI)
+#define G_DEGRADE_SET_CW_HI(x) (((x) >> S_DEGRADE_SET_CW_HI) & M_DEGRADE_SET_CW_HI)
+
+#define A_MAC_MTIP_RS_DEGRADE_SET_THRESH 0x38f18
+
+#define S_DEGRADE_SET_THRESH    0
+#define M_DEGRADE_SET_THRESH    0xffffU
+#define V_DEGRADE_SET_THRESH(x) ((x) << S_DEGRADE_SET_THRESH)
+#define G_DEGRADE_SET_THRESH(x) (((x) >> S_DEGRADE_SET_THRESH) & M_DEGRADE_SET_THRESH)
+
+#define A_MAC_MTIP_RS_DEGRADE_SET_THRESH_HI 0x38f1c
+
+#define S_DEGRADE_SET_THRESH_HI    0
+#define M_DEGRADE_SET_THRESH_HI    0xffffU
+#define V_DEGRADE_SET_THRESH_HI(x) ((x) << S_DEGRADE_SET_THRESH_HI)
+#define G_DEGRADE_SET_THRESH_HI(x) (((x) >> S_DEGRADE_SET_THRESH_HI) & M_DEGRADE_SET_THRESH_HI)
+
+#define A_MAC_MTIP_RS_DEGRADE_CLEAR 0x38f20
+
+#define S_DEGRADE_SET_CLEAR    0
+#define M_DEGRADE_SET_CLEAR    0xffffU
+#define V_DEGRADE_SET_CLEAR(x) ((x) << S_DEGRADE_SET_CLEAR)
+#define G_DEGRADE_SET_CLEAR(x) (((x) >> S_DEGRADE_SET_CLEAR) & M_DEGRADE_SET_CLEAR)
+
+#define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_HI 0x38f24
+
+#define S_DEGRADE_SET_CLEAR_HI    0
+#define M_DEGRADE_SET_CLEAR_HI    0xffffU
+#define V_DEGRADE_SET_CLEAR_HI(x) ((x) << S_DEGRADE_SET_CLEAR_HI)
+#define G_DEGRADE_SET_CLEAR_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_HI) & M_DEGRADE_SET_CLEAR_HI)
+
+#define A_MAC_MTIP_RS_DEGRADE_CLEAR_THRESH 0x38f28
+
+#define S_DEGRADE_SET_CLEAR_THRESH    0
+#define M_DEGRADE_SET_CLEAR_THRESH    0xffffU
+#define V_DEGRADE_SET_CLEAR_THRESH(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH)
+#define G_DEGRADE_SET_CLEAR_THRESH(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH) & M_DEGRADE_SET_CLEAR_THRESH)
+
+#define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_THRESH_HI 0x38f2c
+
+#define S_DEGRADE_SET_CLEAR_THRESH_HI    0
+#define M_DEGRADE_SET_CLEAR_THRESH_HI    0xffffU
+#define V_DEGRADE_SET_CLEAR_THRESH_HI(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH_HI)
+#define G_DEGRADE_SET_CLEAR_THRESH_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH_HI) & M_DEGRADE_SET_CLEAR_THRESH_HI)
+
+#define A_MAC_MTIP_RS_VL0_0 0x38f80
+#define A_MAC_MTIP_RS_VL0_1 0x38f84
+#define A_MAC_MTIP_RS_VL1_0 0x38f88
+#define A_MAC_MTIP_RS_VL1_1 0x38f8c
+#define A_MAC_MTIP_RS_VL2_0 0x38f90
+#define A_MAC_MTIP_RS_VL2_1 0x38f94
+#define A_MAC_MTIP_RS_VL3_0 0x38f98
+#define A_MAC_MTIP_RS_VL3_1 0x38f9c
+#define A_MAC_MTIP_RS_VL4_0 0x38fa0
+#define A_MAC_MTIP_RS_VL4_1 0x38fa4
+#define A_MAC_MTIP_RS_VL5_0 0x38fa8
+#define A_MAC_MTIP_RS_VL5_1 0x38fac
+#define A_MAC_MTIP_RS_VL6_0 0x38fb0
+#define A_MAC_MTIP_RS_VL6_1 0x38fb4
+#define A_MAC_MTIP_RS_VL7_0 0x38fb8
+#define A_MAC_MTIP_RS_VL7_1 0x38fbc
+#define A_MAC_MTIP_RS_VL8_0 0x38fc0
+#define A_MAC_MTIP_RS_VL8_1 0x38fc4
+#define A_MAC_MTIP_RS_VL9_0 0x38fc8
+#define A_MAC_MTIP_RS_VL9_1 0x38fcc
+#define A_MAC_MTIP_RS_VL10_0 0x38fd0
+#define A_MAC_MTIP_RS_VL10_1 0x38fd4
+#define A_MAC_MTIP_RS_VL11_0 0x38fd8
+#define A_MAC_MTIP_RS_VL11_1 0x38fdc
+#define A_MAC_MTIP_RS_VL12_0 0x38fe0
+#define A_MAC_MTIP_RS_VL12_1 0x38fe4
+#define A_MAC_MTIP_RS_VL13_0 0x38fe8
+#define A_MAC_MTIP_RS_VL13_1 0x38fec
+#define A_MAC_MTIP_RS_VL14_0 0x38ff0
+#define A_MAC_MTIP_RS_VL14_1 0x38ff4
+#define A_MAC_MTIP_RS_VL15_0 0x38ff8
+#define A_MAC_MTIP_RS_VL15_1 0x38ffc
+#define A_MAC_MTIP_RS_FEC_SYMBLERR0_LO 0x39000
+#define A_MAC_MTIP_RS_FEC_SYMBLERR0_HI 0x39004
+#define A_MAC_MTIP_RS_FEC_SYMBLERR1_LO 0x39008
+#define A_MAC_MTIP_RS_FEC_SYMBLERR1_HI 0x3900c
+#define A_MAC_MTIP_RS_FEC_SYMBLERR2_LO 0x39010
+#define A_MAC_MTIP_RS_FEC_SYMBLERR2_HI 0x39014
+#define A_MAC_MTIP_RS_FEC_SYMBLERR3_LO 0x39018
+#define A_MAC_MTIP_RS_FEC_SYMBLERR3_HI 0x3901c
+#define A_MAC_MTIP_RS_FEC_SYMBLERR4_LO 0x39020
+
+#define S_RS_FEC_SYMBLERR4_LO    0
+#define V_RS_FEC_SYMBLERR4_LO(x) ((x) << S_RS_FEC_SYMBLERR4_LO)
+#define F_RS_FEC_SYMBLERR4_LO    V_RS_FEC_SYMBLERR4_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR4_HI 0x39024
+
+#define S_RS_FEC_SYMBLERR4_HI    0
+#define V_RS_FEC_SYMBLERR4_HI(x) ((x) << S_RS_FEC_SYMBLERR4_HI)
+#define F_RS_FEC_SYMBLERR4_HI    V_RS_FEC_SYMBLERR4_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR5_LO 0x39028
+
+#define S_RS_FEC_SYMBLERR5_LO    0
+#define V_RS_FEC_SYMBLERR5_LO(x) ((x) << S_RS_FEC_SYMBLERR5_LO)
+#define F_RS_FEC_SYMBLERR5_LO    V_RS_FEC_SYMBLERR5_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR5_HI 0x3902c
+
+#define S_RS_FEC_SYMBLERR5_HI    0
+#define V_RS_FEC_SYMBLERR5_HI(x) ((x) << S_RS_FEC_SYMBLERR5_HI)
+#define F_RS_FEC_SYMBLERR5_HI    V_RS_FEC_SYMBLERR5_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR6_LO 0x39030
+
+#define S_RS_FEC_SYMBLERR6_LO    0
+#define V_RS_FEC_SYMBLERR6_LO(x) ((x) << S_RS_FEC_SYMBLERR6_LO)
+#define F_RS_FEC_SYMBLERR6_LO    V_RS_FEC_SYMBLERR6_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR6_HI 0x39034
+
+#define S_RS_FEC_SYMBLERR6_HI    0
+#define V_RS_FEC_SYMBLERR6_HI(x) ((x) << S_RS_FEC_SYMBLERR6_HI)
+#define F_RS_FEC_SYMBLERR6_HI    V_RS_FEC_SYMBLERR6_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR7_LO 0x39038
+
+#define S_RS_FEC_SYMBLERR7_LO    0
+#define V_RS_FEC_SYMBLERR7_LO(x) ((x) << S_RS_FEC_SYMBLERR7_LO)
+#define F_RS_FEC_SYMBLERR7_LO    V_RS_FEC_SYMBLERR7_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR7_HI 0x3903c
+
+#define S_RS_FEC_SYMBLERR7_HI    0
+#define V_RS_FEC_SYMBLERR7_HI(x) ((x) << S_RS_FEC_SYMBLERR7_HI)
+#define F_RS_FEC_SYMBLERR7_HI    V_RS_FEC_SYMBLERR7_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR8_LO 0x39040
+
+#define S_RS_FEC_SYMBLERR8_LO    0
+#define V_RS_FEC_SYMBLERR8_LO(x) ((x) << S_RS_FEC_SYMBLERR8_LO)
+#define F_RS_FEC_SYMBLERR8_LO    V_RS_FEC_SYMBLERR8_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR8_HI 0x39044
+
+#define S_RS_FEC_SYMBLERR8_HI    0
+#define V_RS_FEC_SYMBLERR8_HI(x) ((x) << S_RS_FEC_SYMBLERR8_HI)
+#define F_RS_FEC_SYMBLERR8_HI    V_RS_FEC_SYMBLERR8_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR9_LO 0x39048
+
+#define S_RS_FEC_SYMBLERR9_LO    0
+#define V_RS_FEC_SYMBLERR9_LO(x) ((x) << S_RS_FEC_SYMBLERR9_LO)
+#define F_RS_FEC_SYMBLERR9_LO    V_RS_FEC_SYMBLERR9_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR9_HI 0x3904c
+
+#define S_RS_FEC_SYMBLERR9_HI    0
+#define V_RS_FEC_SYMBLERR9_HI(x) ((x) << S_RS_FEC_SYMBLERR9_HI)
+#define F_RS_FEC_SYMBLERR9_HI    V_RS_FEC_SYMBLERR9_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR10_LO 0x39050
+
+#define S_RS_FEC_SYMBLERR10_LO    0
+#define V_RS_FEC_SYMBLERR10_LO(x) ((x) << S_RS_FEC_SYMBLERR10_LO)
+#define F_RS_FEC_SYMBLERR10_LO    V_RS_FEC_SYMBLERR10_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR10_HI 0x39054
+
+#define S_RS_FEC_SYMBLERR10_HI    0
+#define V_RS_FEC_SYMBLERR10_HI(x) ((x) << S_RS_FEC_SYMBLERR10_HI)
+#define F_RS_FEC_SYMBLERR10_HI    V_RS_FEC_SYMBLERR10_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR11_LO 0x39058
+
+#define S_RS_FEC_SYMBLERR11_LO    0
+#define V_RS_FEC_SYMBLERR11_LO(x) ((x) << S_RS_FEC_SYMBLERR11_LO)
+#define F_RS_FEC_SYMBLERR11_LO    V_RS_FEC_SYMBLERR11_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR11_HI 0x3905c
+
+#define S_RS_FEC_SYMBLERR11_HI    0
+#define V_RS_FEC_SYMBLERR11_HI(x) ((x) << S_RS_FEC_SYMBLERR11_HI)
+#define F_RS_FEC_SYMBLERR11_HI    V_RS_FEC_SYMBLERR11_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR12_LO 0x39060
+
+#define S_RS_FEC_SYMBLERR12_LO    0
+#define V_RS_FEC_SYMBLERR12_LO(x) ((x) << S_RS_FEC_SYMBLERR12_LO)
+#define F_RS_FEC_SYMBLERR12_LO    V_RS_FEC_SYMBLERR12_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR12_HI 0x39064
+
+#define S_RS_FEC_SYMBLERR12_HI    0
+#define V_RS_FEC_SYMBLERR12_HI(x) ((x) << S_RS_FEC_SYMBLERR12_HI)
+#define F_RS_FEC_SYMBLERR12_HI    V_RS_FEC_SYMBLERR12_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR13_LO 0x39068
+
+#define S_RS_FEC_SYMBLERR13_LO    0
+#define V_RS_FEC_SYMBLERR13_LO(x) ((x) << S_RS_FEC_SYMBLERR13_LO)
+#define F_RS_FEC_SYMBLERR13_LO    V_RS_FEC_SYMBLERR13_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR13_HI 0x3906c
+
+#define S_RS_FEC_SYMBLERR13_HI    0
+#define V_RS_FEC_SYMBLERR13_HI(x) ((x) << S_RS_FEC_SYMBLERR13_HI)
+#define F_RS_FEC_SYMBLERR13_HI    V_RS_FEC_SYMBLERR13_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR14_LO 0x39070
+
+#define S_RS_FEC_SYMBLERR14_LO    0
+#define V_RS_FEC_SYMBLERR14_LO(x) ((x) << S_RS_FEC_SYMBLERR14_LO)
+#define F_RS_FEC_SYMBLERR14_LO    V_RS_FEC_SYMBLERR14_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR14_HI 0x39074
+
+#define S_RS_FEC_SYMBLERR14_HI    0
+#define V_RS_FEC_SYMBLERR14_HI(x) ((x) << S_RS_FEC_SYMBLERR14_HI)
+#define F_RS_FEC_SYMBLERR14_HI    V_RS_FEC_SYMBLERR14_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR15_LO 0x39078
+
+#define S_RS_FEC_SYMBLERR15_LO    0
+#define V_RS_FEC_SYMBLERR15_LO(x) ((x) << S_RS_FEC_SYMBLERR15_LO)
+#define F_RS_FEC_SYMBLERR15_LO    V_RS_FEC_SYMBLERR15_LO(1U)
+
+#define A_MAC_MTIP_RS_FEC_SYMBLERR15_HI 0x3907c
+
+#define S_RS_FEC_SYMBLERR15_HI    0
+#define V_RS_FEC_SYMBLERR15_HI(x) ((x) << S_RS_FEC_SYMBLERR15_HI)
+#define F_RS_FEC_SYMBLERR15_HI    V_RS_FEC_SYMBLERR15_HI(1U)
+
+#define A_MAC_MTIP_RS_FEC_VENDOR_CONTROL 0x39080
+#define A_MAC_MTIP_RS_FEC_VENDOR_INFO_1 0x39084
+
+#define S_VENDOR_INFO_1_AMPS_LOCK    0
+#define V_VENDOR_INFO_1_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_1_AMPS_LOCK)
+#define F_VENDOR_INFO_1_AMPS_LOCK    V_VENDOR_INFO_1_AMPS_LOCK(1U)
+
+#define A_MAC_MTIP_RS_FEC_VENDOR_INFO_2 0x39088
+
+#define S_VENDOR_INFO_2_AMPS_LOCK    0
+#define M_VENDOR_INFO_2_AMPS_LOCK    0xffffU
+#define V_VENDOR_INFO_2_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_2_AMPS_LOCK)
+#define G_VENDOR_INFO_2_AMPS_LOCK(x) (((x) >> S_VENDOR_INFO_2_AMPS_LOCK) & M_VENDOR_INFO_2_AMPS_LOCK)
+
+#define A_MAC_MTIP_RS_FEC_VENDOR_REVISION 0x3908c
+#define A_MAC_MTIP_RS_FEC_VENDOR_ALIGN_STATUS 0x39090
+
+#define S_RS_FEC_VENDOR_ALIGN_STATUS    0
+#define M_RS_FEC_VENDOR_ALIGN_STATUS    0xffffU
+#define V_RS_FEC_VENDOR_ALIGN_STATUS(x) ((x) << S_RS_FEC_VENDOR_ALIGN_STATUS)
+#define G_RS_FEC_VENDOR_ALIGN_STATUS(x) (((x) >> S_RS_FEC_VENDOR_ALIGN_STATUS) & M_RS_FEC_VENDOR_ALIGN_STATUS)
+
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_0 0x39100
+
+#define S_FEC74_FEC_ABILITY_0_B1    1
+#define V_FEC74_FEC_ABILITY_0_B1(x) ((x) << S_FEC74_FEC_ABILITY_0_B1)
+#define F_FEC74_FEC_ABILITY_0_B1    V_FEC74_FEC_ABILITY_0_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_0_B0    0
+#define V_FEC74_FEC_ABILITY_0_B0(x) ((x) << S_FEC74_FEC_ABILITY_0_B0)
+#define F_FEC74_FEC_ABILITY_0_B0    V_FEC74_FEC_ABILITY_0_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_0 0x39104
+
+#define S_FEC_ENABLE_ERROR_INDICATION    1
+#define V_FEC_ENABLE_ERROR_INDICATION(x) ((x) << S_FEC_ENABLE_ERROR_INDICATION)
+#define F_FEC_ENABLE_ERROR_INDICATION    V_FEC_ENABLE_ERROR_INDICATION(1U)
+
+#define S_T7_FEC_ENABLE    0
+#define V_T7_FEC_ENABLE(x) ((x) << S_T7_FEC_ENABLE)
+#define F_T7_FEC_ENABLE    V_T7_FEC_ENABLE(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_STATUS_0 0x39108
+
+#define S_FEC_LOCKED_1    1
+#define V_FEC_LOCKED_1(x) ((x) << S_FEC_LOCKED_1)
+#define F_FEC_LOCKED_1    V_FEC_LOCKED_1(1U)
+
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_0 0x3910c
+
+#define S_VL0_CCW_LO    0
+#define M_VL0_CCW_LO    0xffffU
+#define V_VL0_CCW_LO(x) ((x) << S_VL0_CCW_LO)
+#define G_VL0_CCW_LO(x) (((x) >> S_VL0_CCW_LO) & M_VL0_CCW_LO)
+
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_0 0x39110
+
+#define S_VL0_NCCW_LO    0
+#define M_VL0_NCCW_LO    0xffffU
+#define V_VL0_NCCW_LO(x) ((x) << S_VL0_NCCW_LO)
+#define G_VL0_NCCW_LO(x) (((x) >> S_VL0_NCCW_LO) & M_VL0_NCCW_LO)
+
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_0 0x39114
+
+#define S_VL1_CCW_LO    0
+#define M_VL1_CCW_LO    0xffffU
+#define V_VL1_CCW_LO(x) ((x) << S_VL1_CCW_LO)
+#define G_VL1_CCW_LO(x) (((x) >> S_VL1_CCW_LO) & M_VL1_CCW_LO)
+
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_0 0x39118
+
+#define S_VL1_NCCW_LO    0
+#define M_VL1_NCCW_LO    0xffffU
+#define V_VL1_NCCW_LO(x) ((x) << S_VL1_NCCW_LO)
+#define G_VL1_NCCW_LO(x) (((x) >> S_VL1_NCCW_LO) & M_VL1_NCCW_LO)
+
+#define A_MAC_MTIP_FEC74_COUNTER_HI_0 0x3911c
+
+#define S_COUNTER_HI    0
+#define M_COUNTER_HI    0xffffU
+#define V_COUNTER_HI(x) ((x) << S_COUNTER_HI)
+#define G_COUNTER_HI(x) (((x) >> S_COUNTER_HI) & M_COUNTER_HI)
+
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_1 0x39120
+
+#define S_FEC74_FEC_ABILITY_1_B1    1
+#define V_FEC74_FEC_ABILITY_1_B1(x) ((x) << S_FEC74_FEC_ABILITY_1_B1)
+#define F_FEC74_FEC_ABILITY_1_B1    V_FEC74_FEC_ABILITY_1_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_1_B0    0
+#define V_FEC74_FEC_ABILITY_1_B0(x) ((x) << S_FEC74_FEC_ABILITY_1_B0)
+#define F_FEC74_FEC_ABILITY_1_B0    V_FEC74_FEC_ABILITY_1_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_1 0x39124
+#define A_MAC_MTIP_FEC74_FEC_STATUS_1 0x39128
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_1 0x3912c
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_1 0x39130
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_1 0x39134
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_1 0x39138
+#define A_MAC_MTIP_FEC74_COUNTER_HI_1 0x3913c
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_2 0x39140
+
+#define S_FEC74_FEC_ABILITY_2_B1    1
+#define V_FEC74_FEC_ABILITY_2_B1(x) ((x) << S_FEC74_FEC_ABILITY_2_B1)
+#define F_FEC74_FEC_ABILITY_2_B1    V_FEC74_FEC_ABILITY_2_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_2_B0    0
+#define V_FEC74_FEC_ABILITY_2_B0(x) ((x) << S_FEC74_FEC_ABILITY_2_B0)
+#define F_FEC74_FEC_ABILITY_2_B0    V_FEC74_FEC_ABILITY_2_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_2 0x39144
+#define A_MAC_MTIP_FEC74_FEC_STATUS_2 0x39148
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_2 0x3914c
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_2 0x39150
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_2 0x39154
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_2 0x39158
+#define A_MAC_MTIP_FEC74_COUNTER_HI_2 0x3915c
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_3 0x39160
+
+#define S_FEC74_FEC_ABILITY_3_B1    1
+#define V_FEC74_FEC_ABILITY_3_B1(x) ((x) << S_FEC74_FEC_ABILITY_3_B1)
+#define F_FEC74_FEC_ABILITY_3_B1    V_FEC74_FEC_ABILITY_3_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_3_B0    0
+#define V_FEC74_FEC_ABILITY_3_B0(x) ((x) << S_FEC74_FEC_ABILITY_3_B0)
+#define F_FEC74_FEC_ABILITY_3_B0    V_FEC74_FEC_ABILITY_3_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_3 0x39164
+#define A_MAC_MTIP_FEC74_FEC_STATUS_3 0x39168
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_3 0x3916c
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_3 0x39170
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_3 0x39174
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_3 0x39178
+#define A_MAC_MTIP_FEC74_COUNTER_HI_3 0x3917c
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_4 0x39180
+
+#define S_FEC74_FEC_ABILITY_4_B1    1
+#define V_FEC74_FEC_ABILITY_4_B1(x) ((x) << S_FEC74_FEC_ABILITY_4_B1)
+#define F_FEC74_FEC_ABILITY_4_B1    V_FEC74_FEC_ABILITY_4_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_4_B0    0
+#define V_FEC74_FEC_ABILITY_4_B0(x) ((x) << S_FEC74_FEC_ABILITY_4_B0)
+#define F_FEC74_FEC_ABILITY_4_B0    V_FEC74_FEC_ABILITY_4_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_4 0x39184
+#define A_MAC_MTIP_FEC74_FEC_STATUS_4 0x39188
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_4 0x3918c
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_4 0x39190
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_4 0x39194
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_4 0x39198
+#define A_MAC_MTIP_FEC74_COUNTER_HI_4 0x3919c
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_5 0x391a0
+
+#define S_FEC74_FEC_ABILITY_5_B1    1
+#define V_FEC74_FEC_ABILITY_5_B1(x) ((x) << S_FEC74_FEC_ABILITY_5_B1)
+#define F_FEC74_FEC_ABILITY_5_B1    V_FEC74_FEC_ABILITY_5_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_5_B0    0
+#define V_FEC74_FEC_ABILITY_5_B0(x) ((x) << S_FEC74_FEC_ABILITY_5_B0)
+#define F_FEC74_FEC_ABILITY_5_B0    V_FEC74_FEC_ABILITY_5_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_5 0x391a4
+#define A_MAC_MTIP_FEC74_FEC_STATUS_5 0x391a8
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_5 0x391ac
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_5 0x391b0
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_5 0x391b4
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_5 0x391b8
+#define A_MAC_MTIP_FEC74_COUNTER_HI_5 0x391bc
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_6 0x391c0
+
+#define S_FEC74_FEC_ABILITY_6_B1    1
+#define V_FEC74_FEC_ABILITY_6_B1(x) ((x) << S_FEC74_FEC_ABILITY_6_B1)
+#define F_FEC74_FEC_ABILITY_6_B1    V_FEC74_FEC_ABILITY_6_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_6_B0    0
+#define V_FEC74_FEC_ABILITY_6_B0(x) ((x) << S_FEC74_FEC_ABILITY_6_B0)
+#define F_FEC74_FEC_ABILITY_6_B0    V_FEC74_FEC_ABILITY_6_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_6 0x391c4
+#define A_MAC_MTIP_FEC74_FEC_STATUS_6 0x391c8
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_6 0x391cc
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_6 0x391d0
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_6 0x391d4
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_6 0x391d8
+#define A_MAC_MTIP_FEC74_COUNTER_HI_6 0x391dc
+#define A_MAC_MTIP_FEC74_FEC_ABILITY_7 0x391e0
+
+#define S_FEC74_FEC_ABILITY_7_B1    1
+#define V_FEC74_FEC_ABILITY_7_B1(x) ((x) << S_FEC74_FEC_ABILITY_7_B1)
+#define F_FEC74_FEC_ABILITY_7_B1    V_FEC74_FEC_ABILITY_7_B1(1U)
+
+#define S_FEC74_FEC_ABILITY_7_B0    0
+#define V_FEC74_FEC_ABILITY_7_B0(x) ((x) << S_FEC74_FEC_ABILITY_7_B0)
+#define F_FEC74_FEC_ABILITY_7_B0    V_FEC74_FEC_ABILITY_7_B0(1U)
+
+#define A_MAC_MTIP_FEC74_FEC_CONTROL_7 0x391e4
+#define A_MAC_MTIP_FEC74_FEC_STATUS_7 0x391e8
+#define A_MAC_MTIP_FEC74_VL0_CCW_LO_7 0x391ec
+#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_7 0x391f0
+#define A_MAC_MTIP_FEC74_VL1_CCW_LO_7 0x391f4
+#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_7 0x391f8
+#define A_MAC_MTIP_FEC74_COUNTER_HI_7 0x391fc
+#define A_MAC_BEAN0_CTL 0x39200
+#define A_MAC_BEAN0_STATUS 0x39204
+#define A_MAC_BEAN0_ABILITY_0 0x39208
+
+#define S_BEAN0_REM_FAULT    13
+#define V_BEAN0_REM_FAULT(x) ((x) << S_BEAN0_REM_FAULT)
+#define F_BEAN0_REM_FAULT    V_BEAN0_REM_FAULT(1U)
+
+#define A_MAC_BEAN0_ABILITY_1 0x3920c
+#define A_MAC_BEAN0_ABILITY_2 0x39210
+
+#define S_BEAN0_AB_2_15_12    12
+#define M_BEAN0_AB_2_15_12    0xfU
+#define V_BEAN0_AB_2_15_12(x) ((x) << S_BEAN0_AB_2_15_12)
+#define G_BEAN0_AB_2_15_12(x) (((x) >> S_BEAN0_AB_2_15_12) & M_BEAN0_AB_2_15_12)
+
+#define S_BEAN0_AB_2_11_0    0
+#define M_BEAN0_AB_2_11_0    0xfffU
+#define V_BEAN0_AB_2_11_0(x) ((x) << S_BEAN0_AB_2_11_0)
+#define G_BEAN0_AB_2_11_0(x) (((x) >> S_BEAN0_AB_2_11_0) & M_BEAN0_AB_2_11_0)
+
+#define A_MAC_BEAN0_REM_ABILITY_0 0x39214
+
+#define S_BEAN0_ABL_REM_FAULT    13
+#define V_BEAN0_ABL_REM_FAULT(x) ((x) << S_BEAN0_ABL_REM_FAULT)
+#define F_BEAN0_ABL_REM_FAULT    V_BEAN0_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN0_REM_ABILITY_1 0x39218
+#define A_MAC_BEAN0_REM_ABILITY_2 0x3921c
+
+#define S_BEAN0_REM_AB_15_12    12
+#define M_BEAN0_REM_AB_15_12    0xfU
+#define V_BEAN0_REM_AB_15_12(x) ((x) << S_BEAN0_REM_AB_15_12)
+#define G_BEAN0_REM_AB_15_12(x) (((x) >> S_BEAN0_REM_AB_15_12) & M_BEAN0_REM_AB_15_12)
+
+#define S_BEAN0_REM_AB_11_0    0
+#define M_BEAN0_REM_AB_11_0    0xfffU
+#define V_BEAN0_REM_AB_11_0(x) ((x) << S_BEAN0_REM_AB_11_0)
+#define G_BEAN0_REM_AB_11_0(x) (((x) >> S_BEAN0_REM_AB_11_0) & M_BEAN0_REM_AB_11_0)
+
+#define A_MAC_BEAN0_MS_COUNT 0x39220
+#define A_MAC_BEAN0_XNP_0 0x39224
+#define A_MAC_BEAN0_XNP_1 0x39228
+#define A_MAC_BEAN0_XNP_2 0x3922c
+#define A_MAC_LP_BEAN0_XNP_0 0x39230
+#define A_MAC_LP_BEAN0_XNP_1 0x39234
+#define A_MAC_LP_BEAN0_XNP_2 0x39238
+#define A_MAC_BEAN0_ETH_STATUS 0x3923c
+
+#define S_5GKR    15
+#define V_5GKR(x) ((x) << S_5GKR)
+#define F_5GKR    V_5GKR(1U)
+
+#define S_2P5GKX    14
+#define V_2P5GKX(x) ((x) << S_2P5GKX)
+#define F_2P5GKX    V_2P5GKX(1U)
+
+#define S_25G_KR    13
+#define V_25G_KR(x) ((x) << S_25G_KR)
+#define F_25G_KR    V_25G_KR(1U)
+
+#define S_25G_KR_S    12
+#define V_25G_KR_S(x) ((x) << S_25G_KR_S)
+#define F_25G_KR_S    V_25G_KR_S(1U)
+
+#define S_RS_FEC    7
+#define V_RS_FEC(x) ((x) << S_RS_FEC)
+#define F_RS_FEC    V_RS_FEC(1U)
+
+#define S_FC_FEC    4
+#define V_FC_FEC(x) ((x) << S_FC_FEC)
+#define F_FC_FEC    V_FC_FEC(1U)
+
+#define A_MAC_BEAN0_ETH_STATUS_2 0x39240
+
+#define S_RS_FEC_NEGOTIATED    6
+#define V_RS_FEC_NEGOTIATED(x) ((x) << S_RS_FEC_NEGOTIATED)
+#define F_RS_FEC_NEGOTIATED    V_RS_FEC_NEGOTIATED(1U)
+
+#define S_400GKR4CR4    5
+#define V_400GKR4CR4(x) ((x) << S_400GKR4CR4)
+#define F_400GKR4CR4    V_400GKR4CR4(1U)
+
+#define S_200GKR2CR2    4
+#define V_200GKR2CR2(x) ((x) << S_200GKR2CR2)
+#define F_200GKR2CR2    V_200GKR2CR2(1U)
+
+#define S_100GKR1CR1    3
+#define V_100GKR1CR1(x) ((x) << S_100GKR1CR1)
+#define F_100GKR1CR1    V_100GKR1CR1(1U)
+
+#define S_200GKR4CR4    2
+#define V_200GKR4CR4(x) ((x) << S_200GKR4CR4)
+#define F_200GKR4CR4    V_200GKR4CR4(1U)
+
+#define S_100GKR2CR2    1
+#define V_100GKR2CR2(x) ((x) << S_100GKR2CR2)
+#define F_100GKR2CR2    V_100GKR2CR2(1U)
+
+#define S_50GKRCR    0
+#define V_50GKRCR(x) ((x) << S_50GKRCR)
+#define F_50GKRCR    V_50GKRCR(1U)
+
+#define A_MAC_BEAN1_CTL 0x39300
+#define A_MAC_BEAN1_STATUS 0x39304
+#define A_MAC_BEAN1_ABILITY_0 0x39308
+
+#define S_BEAN1_REM_FAULT    13
+#define V_BEAN1_REM_FAULT(x) ((x) << S_BEAN1_REM_FAULT)
+#define F_BEAN1_REM_FAULT    V_BEAN1_REM_FAULT(1U)
+
+#define A_MAC_BEAN1_ABILITY_1 0x3930c
+#define A_MAC_BEAN1_ABILITY_2 0x39310
+
+#define S_BEAN1_AB_2_15_12    12
+#define M_BEAN1_AB_2_15_12    0xfU
+#define V_BEAN1_AB_2_15_12(x) ((x) << S_BEAN1_AB_2_15_12)
+#define G_BEAN1_AB_2_15_12(x) (((x) >> S_BEAN1_AB_2_15_12) & M_BEAN1_AB_2_15_12)
+
+#define S_BEAN1_AB_2_11_0    0
+#define M_BEAN1_AB_2_11_0    0xfffU
+#define V_BEAN1_AB_2_11_0(x) ((x) << S_BEAN1_AB_2_11_0)
+#define G_BEAN1_AB_2_11_0(x) (((x) >> S_BEAN1_AB_2_11_0) & M_BEAN1_AB_2_11_0)
+
+#define A_MAC_BEAN1_REM_ABILITY_0 0x39314
+
+#define S_BEAN1_ABL_REM_FAULT    13
+#define V_BEAN1_ABL_REM_FAULT(x) ((x) << S_BEAN1_ABL_REM_FAULT)
+#define F_BEAN1_ABL_REM_FAULT    V_BEAN1_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN1_REM_ABILITY_1 0x39318
+#define A_MAC_BEAN1_REM_ABILITY_2 0x3931c
+
+#define S_BEAN1_REM_AB_15_12    12
+#define M_BEAN1_REM_AB_15_12    0xfU
+#define V_BEAN1_REM_AB_15_12(x) ((x) << S_BEAN1_REM_AB_15_12)
+#define G_BEAN1_REM_AB_15_12(x) (((x) >> S_BEAN1_REM_AB_15_12) & M_BEAN1_REM_AB_15_12)
+
+#define S_BEAN1_REM_AB_11_0    0
+#define M_BEAN1_REM_AB_11_0    0xfffU
+#define V_BEAN1_REM_AB_11_0(x) ((x) << S_BEAN1_REM_AB_11_0)
+#define G_BEAN1_REM_AB_11_0(x) (((x) >> S_BEAN1_REM_AB_11_0) & M_BEAN1_REM_AB_11_0)
+
+#define A_MAC_BEAN1_MS_COUNT 0x39320
+#define A_MAC_BEAN1_XNP_0 0x39324
+#define A_MAC_BEAN1_XNP_1 0x39328
+#define A_MAC_BEAN1_XNP_2 0x3932c
+#define A_MAC_LP_BEAN1_XNP_0 0x39330
+#define A_MAC_LP_BEAN1_XNP_1 0x39334
+#define A_MAC_LP_BEAN1_XNP_2 0x39338
+#define A_MAC_BEAN1_ETH_STATUS 0x3933c
+#define A_MAC_BEAN1_ETH_STATUS_2 0x39340
+#define A_MAC_BEAN2_CTL 0x39400
+#define A_MAC_BEAN2_STATUS 0x39404
+#define A_MAC_BEAN2_ABILITY_0 0x39408
+
+#define S_BEAN2_REM_FAULT    13
+#define V_BEAN2_REM_FAULT(x) ((x) << S_BEAN2_REM_FAULT)
+#define F_BEAN2_REM_FAULT    V_BEAN2_REM_FAULT(1U)
+
+#define A_MAC_BEAN2_ABILITY_1 0x3940c
+#define A_MAC_BEAN2_ABILITY_2 0x39410
+
+#define S_BEAN2_AB_2_15_12    12
+#define M_BEAN2_AB_2_15_12    0xfU
+#define V_BEAN2_AB_2_15_12(x) ((x) << S_BEAN2_AB_2_15_12)
+#define G_BEAN2_AB_2_15_12(x) (((x) >> S_BEAN2_AB_2_15_12) & M_BEAN2_AB_2_15_12)
+
+#define S_BEAN2_AB_2_11_0    0
+#define M_BEAN2_AB_2_11_0    0xfffU
+#define V_BEAN2_AB_2_11_0(x) ((x) << S_BEAN2_AB_2_11_0)
+#define G_BEAN2_AB_2_11_0(x) (((x) >> S_BEAN2_AB_2_11_0) & M_BEAN2_AB_2_11_0)
+
+#define A_MAC_BEAN2_REM_ABILITY_0 0x39414
+
+#define S_BEAN2_ABL_REM_FAULT    13
+#define V_BEAN2_ABL_REM_FAULT(x) ((x) << S_BEAN2_ABL_REM_FAULT)
+#define F_BEAN2_ABL_REM_FAULT    V_BEAN2_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN2_REM_ABILITY_1 0x39418
+#define A_MAC_BEAN2_REM_ABILITY_2 0x3941c
+
+#define S_BEAN2_REM_AB_15_12    12
+#define M_BEAN2_REM_AB_15_12    0xfU
+#define V_BEAN2_REM_AB_15_12(x) ((x) << S_BEAN2_REM_AB_15_12)
+#define G_BEAN2_REM_AB_15_12(x) (((x) >> S_BEAN2_REM_AB_15_12) & M_BEAN2_REM_AB_15_12)
+
+#define S_BEAN2_REM_AB_11_0    0
+#define M_BEAN2_REM_AB_11_0    0xfffU
+#define V_BEAN2_REM_AB_11_0(x) ((x) << S_BEAN2_REM_AB_11_0)
+#define G_BEAN2_REM_AB_11_0(x) (((x) >> S_BEAN2_REM_AB_11_0) & M_BEAN2_REM_AB_11_0)
+
+#define A_MAC_BEAN2_MS_COUNT 0x39420
+#define A_MAC_BEAN2_XNP_0 0x39424
+#define A_MAC_BEAN2_XNP_1 0x39428
+#define A_MAC_BEAN2_XNP_2 0x3942c
+#define A_MAC_LP_BEAN2_XNP_0 0x39430
+#define A_MAC_LP_BEAN2_XNP_1 0x39434
+#define A_MAC_LP_BEAN2_XNP_2 0x39438
+#define A_MAC_BEAN2_ETH_STATUS 0x3943c
+#define A_MAC_BEAN2_ETH_STATUS_2 0x39440
+#define A_MAC_BEAN3_CTL 0x39500
+#define A_MAC_BEAN3_STATUS 0x39504
+#define A_MAC_BEAN3_ABILITY_0 0x39508
+
+#define S_BEAN3_REM_FAULT    13
+#define V_BEAN3_REM_FAULT(x) ((x) << S_BEAN3_REM_FAULT)
+#define F_BEAN3_REM_FAULT    V_BEAN3_REM_FAULT(1U)
+
+#define A_MAC_BEAN3_ABILITY_1 0x3950c
+#define A_MAC_BEAN3_ABILITY_2 0x39510
+
+#define S_BEAN3_AB_2_15_12    12
+#define M_BEAN3_AB_2_15_12    0xfU
+#define V_BEAN3_AB_2_15_12(x) ((x) << S_BEAN3_AB_2_15_12)
+#define G_BEAN3_AB_2_15_12(x) (((x) >> S_BEAN3_AB_2_15_12) & M_BEAN3_AB_2_15_12)
+
+#define S_BEAN3_AB_2_11_0    0
+#define M_BEAN3_AB_2_11_0    0xfffU
+#define V_BEAN3_AB_2_11_0(x) ((x) << S_BEAN3_AB_2_11_0)
+#define G_BEAN3_AB_2_11_0(x) (((x) >> S_BEAN3_AB_2_11_0) & M_BEAN3_AB_2_11_0)
+
+#define A_MAC_BEAN3_REM_ABILITY_0 0x39514
+
+#define S_BEAN3_ABL_REM_FAULT    13
+#define V_BEAN3_ABL_REM_FAULT(x) ((x) << S_BEAN3_ABL_REM_FAULT)
+#define F_BEAN3_ABL_REM_FAULT    V_BEAN3_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN3_REM_ABILITY_1 0x39518
+#define A_MAC_BEAN3_REM_ABILITY_2 0x3951c
+
+#define S_BEAN3_REM_AB_15_12    12
+#define M_BEAN3_REM_AB_15_12    0xfU
+#define V_BEAN3_REM_AB_15_12(x) ((x) << S_BEAN3_REM_AB_15_12)
+#define G_BEAN3_REM_AB_15_12(x) (((x) >> S_BEAN3_REM_AB_15_12) & M_BEAN3_REM_AB_15_12)
+
+#define S_BEAN3_REM_AB_11_0    0
+#define M_BEAN3_REM_AB_11_0    0xfffU
+#define V_BEAN3_REM_AB_11_0(x) ((x) << S_BEAN3_REM_AB_11_0)
+#define G_BEAN3_REM_AB_11_0(x) (((x) >> S_BEAN3_REM_AB_11_0) & M_BEAN3_REM_AB_11_0)
+
+#define A_MAC_BEAN3_MS_COUNT 0x39520
+#define A_MAC_BEAN3_XNP_0 0x39524
+#define A_MAC_BEAN3_XNP_1 0x39528
+#define A_MAC_BEAN3_XNP_2 0x3952c
+#define A_MAC_LP_BEAN3_XNP_0 0x39530
+#define A_MAC_LP_BEAN3_XNP_1 0x39534
+#define A_MAC_LP_BEAN3_XNP_2 0x39538
+#define A_MAC_BEAN3_ETH_STATUS 0x3953c
+#define A_MAC_BEAN3_ETH_STATUS_2 0x39540
+#define A_MAC_BEAN4_CTL 0x39600
+#define A_MAC_BEAN4_STATUS 0x39604
+#define A_MAC_BEAN4_ABILITY_0 0x39608
+
+#define S_BEAN4_REM_FAULT    13
+#define V_BEAN4_REM_FAULT(x) ((x) << S_BEAN4_REM_FAULT)
+#define F_BEAN4_REM_FAULT    V_BEAN4_REM_FAULT(1U)
+
+#define A_MAC_BEAN4_ABILITY_1 0x3960c
+#define A_MAC_BEAN4_ABILITY_2 0x39610
+
+#define S_BEAN4_AB_2_15_12    12
+#define M_BEAN4_AB_2_15_12    0xfU
+#define V_BEAN4_AB_2_15_12(x) ((x) << S_BEAN4_AB_2_15_12)
+#define G_BEAN4_AB_2_15_12(x) (((x) >> S_BEAN4_AB_2_15_12) & M_BEAN4_AB_2_15_12)
+
+#define S_BEAN4_AB_2_11_0    0
+#define M_BEAN4_AB_2_11_0    0xfffU
+#define V_BEAN4_AB_2_11_0(x) ((x) << S_BEAN4_AB_2_11_0)
+#define G_BEAN4_AB_2_11_0(x) (((x) >> S_BEAN4_AB_2_11_0) & M_BEAN4_AB_2_11_0)
+
+#define A_MAC_BEAN4_REM_ABILITY_0 0x39614
+
+#define S_BEAN4_ABL_REM_FAULT    13
+#define V_BEAN4_ABL_REM_FAULT(x) ((x) << S_BEAN4_ABL_REM_FAULT)
+#define F_BEAN4_ABL_REM_FAULT    V_BEAN4_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN4_REM_ABILITY_1 0x39618
+#define A_MAC_BEAN4_REM_ABILITY_2 0x3961c
+
+#define S_BEAN4_REM_AB_15_12    12
+#define M_BEAN4_REM_AB_15_12    0xfU
+#define V_BEAN4_REM_AB_15_12(x) ((x) << S_BEAN4_REM_AB_15_12)
+#define G_BEAN4_REM_AB_15_12(x) (((x) >> S_BEAN4_REM_AB_15_12) & M_BEAN4_REM_AB_15_12)
+
+#define S_BEAN4_REM_AB_11_0    0
+#define M_BEAN4_REM_AB_11_0    0xfffU
+#define V_BEAN4_REM_AB_11_0(x) ((x) << S_BEAN4_REM_AB_11_0)
+#define G_BEAN4_REM_AB_11_0(x) (((x) >> S_BEAN4_REM_AB_11_0) & M_BEAN4_REM_AB_11_0)
+
+#define A_MAC_BEAN4_MS_COUNT 0x39620
+#define A_MAC_BEAN4_XNP_0 0x39624
+#define A_MAC_BEAN4_XNP_1 0x39628
+#define A_MAC_BEAN4_XNP_2 0x3962c
+#define A_MAC_LP_BEAN4_XNP_0 0x39630
+#define A_MAC_LP_BEAN4_XNP_1 0x39634
+#define A_MAC_LP_BEAN4_XNP_2 0x39638
+#define A_MAC_BEAN4_ETH_STATUS 0x3963c
+#define A_MAC_BEAN4_ETH_STATUS_2 0x39640
+#define A_MAC_BEAN5_CTL 0x39700
+#define A_MAC_BEAN5_STATUS 0x39704
+#define A_MAC_BEAN5_ABILITY_0 0x39708
+
+#define S_BEAN5_REM_FAULT    13
+#define V_BEAN5_REM_FAULT(x) ((x) << S_BEAN5_REM_FAULT)
+#define F_BEAN5_REM_FAULT    V_BEAN5_REM_FAULT(1U)
+
+#define A_MAC_BEAN5_ABILITY_1 0x3970c
+#define A_MAC_BEAN5_ABILITY_2 0x39710
+
+#define S_BEAN5_AB_2_15_12    12
+#define M_BEAN5_AB_2_15_12    0xfU
+#define V_BEAN5_AB_2_15_12(x) ((x) << S_BEAN5_AB_2_15_12)
+#define G_BEAN5_AB_2_15_12(x) (((x) >> S_BEAN5_AB_2_15_12) & M_BEAN5_AB_2_15_12)
+
+#define S_BEAN5_AB_2_11_0    0
+#define M_BEAN5_AB_2_11_0    0xfffU
+#define V_BEAN5_AB_2_11_0(x) ((x) << S_BEAN5_AB_2_11_0)
+#define G_BEAN5_AB_2_11_0(x) (((x) >> S_BEAN5_AB_2_11_0) & M_BEAN5_AB_2_11_0)
+
+#define A_MAC_BEAN5_REM_ABILITY_0 0x39714
+
+#define S_BEAN5_ABL_REM_FAULT    13
+#define V_BEAN5_ABL_REM_FAULT(x) ((x) << S_BEAN5_ABL_REM_FAULT)
+#define F_BEAN5_ABL_REM_FAULT    V_BEAN5_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN5_REM_ABILITY_1 0x39718
+#define A_MAC_BEAN5_REM_ABILITY_2 0x3971c
+
+#define S_BEAN5_REM_AB_15_12    12
+#define M_BEAN5_REM_AB_15_12    0xfU
+#define V_BEAN5_REM_AB_15_12(x) ((x) << S_BEAN5_REM_AB_15_12)
+#define G_BEAN5_REM_AB_15_12(x) (((x) >> S_BEAN5_REM_AB_15_12) & M_BEAN5_REM_AB_15_12)
+
+#define S_BEAN5_REM_AB_11_0    0
+#define M_BEAN5_REM_AB_11_0    0xfffU
+#define V_BEAN5_REM_AB_11_0(x) ((x) << S_BEAN5_REM_AB_11_0)
+#define G_BEAN5_REM_AB_11_0(x) (((x) >> S_BEAN5_REM_AB_11_0) & M_BEAN5_REM_AB_11_0)
+
+#define A_MAC_BEAN5_MS_COUNT 0x39720
+#define A_MAC_BEAN5_XNP_0 0x39724
+#define A_MAC_BEAN5_XNP_1 0x39728
+#define A_MAC_BEAN5_XNP_2 0x3972c
+#define A_MAC_LP_BEAN5_XNP_0 0x39730
+#define A_MAC_LP_BEAN5_XNP_1 0x39734
+#define A_MAC_LP_BEAN5_XNP_2 0x39738
+#define A_MAC_BEAN5_ETH_STATUS 0x3973c
+#define A_MAC_BEAN5_ETH_STATUS_2 0x39740
+#define A_MAC_BEAN6_CTL 0x39800
+#define A_MAC_BEAN6_STATUS 0x39804
+#define A_MAC_BEAN6_ABILITY_0 0x39808
+
+#define S_BEAN6_REM_FAULT    13
+#define V_BEAN6_REM_FAULT(x) ((x) << S_BEAN6_REM_FAULT)
+#define F_BEAN6_REM_FAULT    V_BEAN6_REM_FAULT(1U)
+
+#define A_MAC_BEAN6_ABILITY_1 0x3980c
+#define A_MAC_BEAN6_ABILITY_2 0x39810
+
+#define S_BEAN6_AB_2_15_12    12
+#define M_BEAN6_AB_2_15_12    0xfU
+#define V_BEAN6_AB_2_15_12(x) ((x) << S_BEAN6_AB_2_15_12)
+#define G_BEAN6_AB_2_15_12(x) (((x) >> S_BEAN6_AB_2_15_12) & M_BEAN6_AB_2_15_12)
+
+#define S_BEAN6_AB_2_11_0    0
+#define M_BEAN6_AB_2_11_0    0xfffU
+#define V_BEAN6_AB_2_11_0(x) ((x) << S_BEAN6_AB_2_11_0)
+#define G_BEAN6_AB_2_11_0(x) (((x) >> S_BEAN6_AB_2_11_0) & M_BEAN6_AB_2_11_0)
+
+#define A_MAC_BEAN6_REM_ABILITY_0 0x39814
+
+#define S_BEAN6_ABL_REM_FAULT    13
+#define V_BEAN6_ABL_REM_FAULT(x) ((x) << S_BEAN6_ABL_REM_FAULT)
+#define F_BEAN6_ABL_REM_FAULT    V_BEAN6_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN6_REM_ABILITY_1 0x39818
+#define A_MAC_BEAN6_REM_ABILITY_2 0x3981c
+
+#define S_BEAN6_REM_AB_15_12    12
+#define M_BEAN6_REM_AB_15_12    0xfU
+#define V_BEAN6_REM_AB_15_12(x) ((x) << S_BEAN6_REM_AB_15_12)
+#define G_BEAN6_REM_AB_15_12(x) (((x) >> S_BEAN6_REM_AB_15_12) & M_BEAN6_REM_AB_15_12)
+
+#define S_BEAN6_REM_AB_11_0    0
+#define M_BEAN6_REM_AB_11_0    0xfffU
+#define V_BEAN6_REM_AB_11_0(x) ((x) << S_BEAN6_REM_AB_11_0)
+#define G_BEAN6_REM_AB_11_0(x) (((x) >> S_BEAN6_REM_AB_11_0) & M_BEAN6_REM_AB_11_0)
+
+#define A_MAC_BEAN6_MS_COUNT 0x39820
+#define A_MAC_BEAN6_XNP_0 0x39824
+#define A_MAC_BEAN6_XNP_1 0x39828
+#define A_MAC_BEAN6_XNP_2 0x3982c
+#define A_MAC_LP_BEAN6_XNP_0 0x39830
+#define A_MAC_LP_BEAN6_XNP_1 0x39834
+#define A_MAC_LP_BEAN6_XNP_2 0x39838
+#define A_MAC_BEAN6_ETH_STATUS 0x3983c
+#define A_MAC_BEAN6_ETH_STATUS_2 0x39840
+#define A_MAC_BEAN7_CTL 0x39900
+#define A_MAC_BEAN7_STATUS 0x39904
+#define A_MAC_BEAN7_ABILITY_0 0x39908
+
+#define S_BEAN7_REM_FAULT    13
+#define V_BEAN7_REM_FAULT(x) ((x) << S_BEAN7_REM_FAULT)
+#define F_BEAN7_REM_FAULT    V_BEAN7_REM_FAULT(1U)
+
+#define A_MAC_BEAN7_ABILITY_1 0x3990c
+#define A_MAC_BEAN7_ABILITY_2 0x39910
+
+#define S_BEAN7_AB_2_15_12    12
+#define M_BEAN7_AB_2_15_12    0xfU
+#define V_BEAN7_AB_2_15_12(x) ((x) << S_BEAN7_AB_2_15_12)
+#define G_BEAN7_AB_2_15_12(x) (((x) >> S_BEAN7_AB_2_15_12) & M_BEAN7_AB_2_15_12)
+
+#define S_BEAN7_AB_2_11_0    0
+#define M_BEAN7_AB_2_11_0    0xfffU
+#define V_BEAN7_AB_2_11_0(x) ((x) << S_BEAN7_AB_2_11_0)
+#define G_BEAN7_AB_2_11_0(x) (((x) >> S_BEAN7_AB_2_11_0) & M_BEAN7_AB_2_11_0)
+
+#define A_MAC_BEAN7_REM_ABILITY_0 0x39914
+
+#define S_BEAN7_ABL_REM_FAULT    13
+#define V_BEAN7_ABL_REM_FAULT(x) ((x) << S_BEAN7_ABL_REM_FAULT)
+#define F_BEAN7_ABL_REM_FAULT    V_BEAN7_ABL_REM_FAULT(1U)
+
+#define A_MAC_BEAN7_REM_ABILITY_1 0x39918
+#define A_MAC_BEAN7_REM_ABILITY_2 0x3991c
+
+#define S_BEAN7_REM_AB_15_12    12
+#define M_BEAN7_REM_AB_15_12    0xfU
+#define V_BEAN7_REM_AB_15_12(x) ((x) << S_BEAN7_REM_AB_15_12)
+#define G_BEAN7_REM_AB_15_12(x) (((x) >> S_BEAN7_REM_AB_15_12) & M_BEAN7_REM_AB_15_12)
+
+#define S_BEAN7_REM_AB_11_0    0
+#define M_BEAN7_REM_AB_11_0    0xfffU
+#define V_BEAN7_REM_AB_11_0(x) ((x) << S_BEAN7_REM_AB_11_0)
+#define G_BEAN7_REM_AB_11_0(x) (((x) >> S_BEAN7_REM_AB_11_0) & M_BEAN7_REM_AB_11_0)
+
+#define A_MAC_BEAN7_MS_COUNT 0x39920
+#define A_MAC_BEAN7_XNP_0 0x39924
+#define A_MAC_BEAN7_XNP_1 0x39928
+#define A_MAC_BEAN7_XNP_2 0x3992c
+#define A_MAC_LP_BEAN7_XNP_0 0x39930
+#define A_MAC_LP_BEAN7_XNP_1 0x39934
+#define A_MAC_LP_BEAN7_XNP_2 0x39938
+#define A_MAC_BEAN7_ETH_STATUS 0x3993c
+#define A_MAC_BEAN7_ETH_STATUS_2 0x39940
+#define A_MAC_MTIP_ETHERSTATS_DATA_HI 0x39a00
+#define A_MAC_MTIP_ETHERSTATS_STATN_STATUS 0x39a04
+#define A_MAC_MTIP_ETHERSTATS_STATN_CONFIG 0x39a08
+
+#define S_T7_RESET    31
+#define V_T7_RESET(x) ((x) << S_T7_RESET)
+#define F_T7_RESET    V_T7_RESET(1U)
+
+#define A_MAC_MTIP_ETHERSTATS_STATN_CONTROL 0x39a0c
+
+#define S_CMD_CLEAR_TX    31
+#define V_CMD_CLEAR_TX(x) ((x) << S_CMD_CLEAR_TX)
+#define F_CMD_CLEAR_TX    V_CMD_CLEAR_TX(1U)
+
+#define S_CMD_CLEAR_RX    30
+#define V_CMD_CLEAR_RX(x) ((x) << S_CMD_CLEAR_RX)
+#define F_CMD_CLEAR_RX    V_CMD_CLEAR_RX(1U)
+
+#define S_CLEAR_PRE    29
+#define V_CLEAR_PRE(x) ((x) << S_CLEAR_PRE)
+#define F_CLEAR_PRE    V_CLEAR_PRE(1U)
+
+#define S_CMD_CAPTURE_TX    28
+#define V_CMD_CAPTURE_TX(x) ((x) << S_CMD_CAPTURE_TX)
+#define F_CMD_CAPTURE_TX    V_CMD_CAPTURE_TX(1U)
+
+#define S_CMD_CAPTURE_RX    27
+#define V_CMD_CAPTURE_RX(x) ((x) << S_CMD_CAPTURE_RX)
+#define F_CMD_CAPTURE_RX    V_CMD_CAPTURE_RX(1U)
+
+#define S_PORTMASK    0
+#define M_PORTMASK    0xffU
+#define V_PORTMASK(x) ((x) << S_PORTMASK)
+#define G_PORTMASK(x) (((x) >> S_PORTMASK) & M_PORTMASK)
+
+#define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_LO 0x39a10
+
+#define S_STATN_CLEARVALUE_LO    0
+#define V_STATN_CLEARVALUE_LO(x) ((x) << S_STATN_CLEARVALUE_LO)
+#define F_STATN_CLEARVALUE_LO    V_STATN_CLEARVALUE_LO(1U)
+
+#define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_HI 0x39a14
+
+#define S_STATN_CLEARVALUE_HI    0
+#define V_STATN_CLEARVALUE_HI(x) ((x) << S_STATN_CLEARVALUE_HI)
+#define F_STATN_CLEARVALUE_HI    V_STATN_CLEARVALUE_HI(1U)
+
+#define A_MAC_MTIP_ETHERSTATS_DATA_HI_1 0x39a1c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_0 0x39a20
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_1 0x39a24
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_2 0x39a28
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_3 0x39a2c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_4 0x39a30
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_5 0x39a34
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_6 0x39a38
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_7 0x39a3c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_8 0x39a40
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_9 0x39a44
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_10 0x39a48
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_11 0x39a4c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_12 0x39a50
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_13 0x39a54
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_14 0x39a58
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_15 0x39a5c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_16 0x39a60
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_17 0x39a64
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_18 0x39a68
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_19 0x39a6c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_20 0x39a70
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_21 0x39a74
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_22 0x39a78
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_23 0x39a7c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_24 0x39a80
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_25 0x39a84
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_26 0x39a88
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_27 0x39a8c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_28 0x39a90
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_29 0x39a94
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_30 0x39a98
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_31 0x39a9c
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_32 0x39aa0
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_33 0x39aa4
+#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_34 0x39aa8
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS 0x39b00
+#define A_MAC_MTIP_ETHERSTATS0_OCTETSRECEIVEDOK 0x39b04
+#define A_MAC_MTIP_ETHERSTATS0_AALIGNMENTERRORS 0x39b08
+#define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESRECEIVED 0x39b0c
+#define A_MAC_MTIP_ETHERSTATS0_AFRAMETOOLONGERRORS 0x39b10
+#define A_MAC_MTIP_ETHERSTATS0_AINRANGELENGTHERRORS 0x39b14
+#define A_MAC_MTIP_ETHERSTATS0_AFRAMESRECEIVEDOK 0x39b18
+#define A_MAC_MTIP_ETHERSTATS0_AFRAMECHECKSEQUENCEERRORS 0x39b1c
+#define A_MAC_MTIP_ETHERSTATS0_VLANRECEIVEDOK 0x39b20
+#define A_MAC_MTIP_ETHERSTATS0_IFINERRORS_RX 0x39b24
+#define A_MAC_MTIP_ETHERSTATS0_IFINUCASTPKTS_RX 0x39b28
+#define A_MAC_MTIP_ETHERSTATS0_IFINMULTICASTPKTS_RX 0x39b2c
+#define A_MAC_MTIP_ETHERSTATS0_IFINBROADCASTPKTS_RX 0x39b30
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSDROPEVENTS_RX 0x39b34
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_RX 0x39b38
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSUNDERSIZEPKTS_RX 0x39b3c
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_RX 0x39b40
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_RX 0x39b44
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_RX 0x39b48
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_RX 0x39b4c
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39b50
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39b54
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39b58
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOVERSIZEPKTS_RX 0x39b5c
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSJABBERS_RX 0x39b60
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSFRAGMENTS_RX 0x39b64
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39b68
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39b6c
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39b70
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39b74
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39b78
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39b7c
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39b80
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39b84
+#define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESRECEIVED_RX 0x39b88
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS 0x39b8c
+#define A_MAC_MTIP_ETHERSTATS1_OCTETSRECEIVEDOK 0x39b90
+#define A_MAC_MTIP_ETHERSTATS1_AALIGNMENTERRORS 0x39b94
+#define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESRECEIVED 0x39b98
+#define A_MAC_MTIP_ETHERSTATS1_AFRAMETOOLONGERRORS 0x39b9c
+#define A_MAC_MTIP_ETHERSTATS1_AINRANGELENGTHERRORS 0x39ba0
+#define A_MAC_MTIP_ETHERSTATS1_AFRAMESRECEIVEDOK 0x39ba4
+#define A_MAC_MTIP_ETHERSTATS1_AFRAMECHECKSEQUENCEERRORS 0x39ba8
+#define A_MAC_MTIP_ETHERSTATS1_VLANRECEIVEDOK 0x39bac
+#define A_MAC_MTIP_ETHERSTATS1_IFINERRORS_RX 0x39bb0
+#define A_MAC_MTIP_ETHERSTATS1_IFINUCASTPKTS_RX 0x39bb4
+#define A_MAC_MTIP_ETHERSTATS1_IFINMULTICASTPKTS_RX 0x39bb8
+#define A_MAC_MTIP_ETHERSTATS1_IFINBROADCASTPKTS_RX 0x39bbc
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSDROPEVENTS_RX 0x39bc0
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_RX 0x39bc4
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSUNDERSIZEPKTS_RX 0x39bc8
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_RX 0x39bcc
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_RX 0x39bd0
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_RX 0x39bd4
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_RX 0x39bd8
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39bdc
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39be0
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39be4
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOVERSIZEPKTS_RX 0x39be8
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSJABBERS_RX 0x39bec
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSFRAGMENTS_RX 0x39bf0
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39bf4
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39bf8
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39bfc
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c00
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c04
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c08
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c0c
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c10
+#define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESRECEIVED_RX 0x39c14
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS 0x39c18
+#define A_MAC_MTIP_ETHERSTATS2_OCTETSRECEIVEDOK 0x39c1c
+#define A_MAC_MTIP_ETHERSTATS2_AALIGNMENTERRORS 0x39c20
+#define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESRECEIVED 0x39c24
+#define A_MAC_MTIP_ETHERSTATS2_AFRAMETOOLONGERRORS 0x39c28
+#define A_MAC_MTIP_ETHERSTATS2_AINRANGELENGTHERRORS 0x39c2c
+#define A_MAC_MTIP_ETHERSTATS2_AFRAMESRECEIVEDOK 0x39c30
+#define A_MAC_MTIP_ETHERSTATS2_AFRAMECHECKSEQUENCEERRORS 0x39c34
+#define A_MAC_MTIP_ETHERSTATS2_VLANRECEIVEDOK 0x39c38
+#define A_MAC_MTIP_ETHERSTATS2_IFINERRORS_RX 0x39c3c
+#define A_MAC_MTIP_ETHERSTATS2_IFINUCASTPKTS_RX 0x39c40
+#define A_MAC_MTIP_ETHERSTATS2_IFINMULTICASTPKTS_RX 0x39c44
+#define A_MAC_MTIP_ETHERSTATS2_IFINBROADCASTPKTS_RX 0x39c48
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSDROPEVENTS_RX 0x39c4c
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_RX 0x39c50
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSUNDERSIZEPKTS_RX 0x39c54
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_RX 0x39c58
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_RX 0x39c5c
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_RX 0x39c60
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_RX 0x39c64
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39c68
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39c6c
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39c70
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOVERSIZEPKTS_RX 0x39c74
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSJABBERS_RX 0x39c78
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSFRAGMENTS_RX 0x39c7c
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39c80
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39c84
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39c88
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c8c
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c90
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c94
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c98
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c9c
+#define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESRECEIVED_RX 0x39ca0
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS 0x39ca4
+#define A_MAC_MTIP_ETHERSTATS3_OCTETSRECEIVEDOK 0x39ca8
+#define A_MAC_MTIP_ETHERSTATS3_AALIGNMENTERRORS 0x39cac
+#define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESRECEIVED 0x39cb0
+#define A_MAC_MTIP_ETHERSTATS3_AFRAMETOOLONGERRORS 0x39cb4
+#define A_MAC_MTIP_ETHERSTATS3_AINRANGELENGTHERRORS 0x39cb8
+#define A_MAC_MTIP_ETHERSTATS3_AFRAMESRECEIVEDOK 0x39cbc
+#define A_MAC_MTIP_ETHERSTATS3_AFRAMECHECKSEQUENCEERRORS 0x39cc0
+#define A_MAC_MTIP_ETHERSTATS3_VLANRECEIVEDOK 0x39cc4
+#define A_MAC_MTIP_ETHERSTATS3_IFINERRORS_RX 0x39cc8
+#define A_MAC_MTIP_ETHERSTATS3_IFINUCASTPKTS_RX 0x39ccc
+#define A_MAC_MTIP_ETHERSTATS3_IFINMULTICASTPKTS_RX 0x39cd0
+#define A_MAC_MTIP_ETHERSTATS3_IFINBROADCASTPKTS_RX 0x39cd4
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSDROPEVENTS_RX 0x39cd8
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_RX 0x39cdc
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSUNDERSIZEPKTS_RX 0x39ce0
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_RX 0x39ce4
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_RX 0x39ce8
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_RX 0x39cec
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_RX 0x39cf0
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39cf4
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39cf8
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39cfc
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOVERSIZEPKTS_RX 0x39d00
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSJABBERS_RX 0x39d04
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSFRAGMENTS_RX 0x39d08
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39d0c
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39d10
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39d14
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39d18
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39d1c
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39d20
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39d24
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39d28
+#define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESRECEIVED_RX 0x39d2c
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS_TX 0x39d30
+#define A_MAC_MTIP_ETHERSTATS0_OCTETSTRANSMITTEDOK_TX 0x39d34
+#define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39d38
+#define A_MAC_MTIP_ETHERSTATS0_AFRAMESTRANSMITTEDOK_TX 0x39d3c
+#define A_MAC_MTIP_ETHERSTATS0_VLANTRANSMITTEDOK_TX 0x39d40
+#define A_MAC_MTIP_ETHERSTATS0_IFOUTERRORS_TX 0x39d44
+#define A_MAC_MTIP_ETHERSTATS0_IFOUTUCASTPKTS_TX 0x39d48
+#define A_MAC_MTIP_ETHERSTATS0IFOUTMULTICASTPKTS_TX 0x39d4c
+#define A_MAC_MTIP_ETHERSTATS0_IFOUTBROADCASTPKTS_TX 0x39d50
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_TX 0x39d54
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_TX 0x39d58
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_TX 0x39d5c
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_TX 0x39d60
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39d64
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39d68
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39d6c
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39d70
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39d74
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39d78
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39d7c
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39d80
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39d84
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39d88
+#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39d8c
+#define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESTRANSMITTED_TX 0x39d90
+#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_TX 0x39d94
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS_TX 0x39d98
+#define A_MAC_MTIP_ETHERSTATS1_OCTETSTRANSMITTEDOK_TX 0x39d9c
+#define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39da0
+#define A_MAC_MTIP_ETHERSTATS1_AFRAMESTRANSMITTEDOK_TX 0x39da4
+#define A_MAC_MTIP_ETHERSTATS1_VLANTRANSMITTEDOK_TX 0x39da8
+#define A_MAC_MTIP_ETHERSTATS1_IFOUTERRORS_TX 0x39dac
+#define A_MAC_MTIP_ETHERSTATS1_IFOUTUCASTPKTS_TX 0x39db0
+#define A_MAC_MTIP_ETHERSTATS1IFOUTMULTICASTPKTS_TX 0x39db4
+#define A_MAC_MTIP_ETHERSTATS1_IFOUTBROADCASTPKTS_TX 0x39db8
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_TX 0x39dbc
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_TX 0x39dc0
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_TX 0x39dc4
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_TX 0x39dc8
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39dcc
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39dd0
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39dd4
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39dd8
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39ddc
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39de0
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39de4
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39de8
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39dec
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39df0
+#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39df4
+#define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESTRANSMITTED_TX 0x39df8
+#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_TX 0x39dfc
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS_TX 0x39e00
+#define A_MAC_MTIP_ETHERSTATS2_OCTETSTRANSMITTEDOK_TX 0x39e04
+#define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e08
+#define A_MAC_MTIP_ETHERSTATS2_AFRAMESTRANSMITTEDOK_TX 0x39e0c
+#define A_MAC_MTIP_ETHERSTATS2_VLANTRANSMITTEDOK_TX 0x39e10
+#define A_MAC_MTIP_ETHERSTATS2_IFOUTERRORS_TX 0x39e14
+#define A_MAC_MTIP_ETHERSTATS2_IFOUTUCASTPKTS_TX 0x39e18
+#define A_MAC_MTIP_ETHERSTATS2IFOUTMULTICASTPKTS_TX 0x39e1c
+#define A_MAC_MTIP_ETHERSTATS2_IFOUTBROADCASTPKTS_TX 0x39e20
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_TX 0x39e24
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e28
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e2c
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e30
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e34
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39e38
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39e3c
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39e40
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39e44
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39e48
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39e4c
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39e50
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39e54
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39e58
+#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39e5c
+#define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESTRANSMITTED_TX 0x39e60
+#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_TX 0x39e64
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS_TX 0x39e68
+#define A_MAC_MTIP_ETHERSTATS3_OCTETSTRANSMITTEDOK_TX 0x39e6c
+#define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e70
+#define A_MAC_MTIP_ETHERSTATS3_AFRAMESTRANSMITTEDOK_TX 0x39e74
+#define A_MAC_MTIP_ETHERSTATS3_VLANTRANSMITTEDOK_TX 0x39e78
+#define A_MAC_MTIP_ETHERSTATS3_IFOUTERRORS_TX 0x39e7c
+#define A_MAC_MTIP_ETHERSTATS3_IFOUTUCASTPKTS_TX 0x39e80
+#define A_MAC_MTIP_ETHERSTATS3IFOUTMULTICASTPKTS_TX 0x39e84
+#define A_MAC_MTIP_ETHERSTATS3_IFOUTBROADCASTPKTS_TX 0x39e88
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_TX 0x39e8c
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e90
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e94
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e98
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e9c
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39ea0
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39ea4
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39ea8
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39eac
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39eb0
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39eb4
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39eb8
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39ebc
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39ec0
+#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39ec4
+#define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESTRANSMITTED_TX 0x39ec8
+#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_TX 0x39ecc
+#define A_MAC_IOS_CTRL 0x3a000
+
+#define S_SUB_BLOCK_SEL    28
+#define M_SUB_BLOCK_SEL    0x7U
+#define V_SUB_BLOCK_SEL(x) ((x) << S_SUB_BLOCK_SEL)
+#define G_SUB_BLOCK_SEL(x) (((x) >> S_SUB_BLOCK_SEL) & M_SUB_BLOCK_SEL)
+
+#define S_QUAD_BROADCAST_EN    24
+#define V_QUAD_BROADCAST_EN(x) ((x) << S_QUAD_BROADCAST_EN)
+#define F_QUAD_BROADCAST_EN    V_QUAD_BROADCAST_EN(1U)
+
+#define S_AUTO_INCR    20
+#define V_AUTO_INCR(x) ((x) << S_AUTO_INCR)
+#define F_AUTO_INCR    V_AUTO_INCR(1U)
+
+#define S_T7_2_ADDR    0
+#define M_T7_2_ADDR    0x7ffffU
+#define V_T7_2_ADDR(x) ((x) << S_T7_2_ADDR)
+#define G_T7_2_ADDR(x) (((x) >> S_T7_2_ADDR) & M_T7_2_ADDR)
+
+#define A_MAC_IOS_DATA 0x3a004
+#define A_MAC_IOS_BGR_RST 0x3a050
+
+#define S_BGR_RSTN    0
+#define V_BGR_RSTN(x) ((x) << S_BGR_RSTN)
+#define F_BGR_RSTN    V_BGR_RSTN(1U)
+
+#define A_MAC_IOS_BGR_CFG 0x3a054
+
+#define S_SOC_REFCLK_EN    0
+#define V_SOC_REFCLK_EN(x) ((x) << S_SOC_REFCLK_EN)
+#define F_SOC_REFCLK_EN    V_SOC_REFCLK_EN(1U)
+
+#define A_MAC_IOS_QUAD0_CFG 0x3a058
+
+#define S_QUAD0_CH3_RSTN    5
+#define V_QUAD0_CH3_RSTN(x) ((x) << S_QUAD0_CH3_RSTN)
+#define F_QUAD0_CH3_RSTN    V_QUAD0_CH3_RSTN(1U)
+
+#define S_QUAD0_CH2_RSTN    4
+#define V_QUAD0_CH2_RSTN(x) ((x) << S_QUAD0_CH2_RSTN)
+#define F_QUAD0_CH2_RSTN    V_QUAD0_CH2_RSTN(1U)
+
+#define S_QUAD0_CH1_RSTN    3
+#define V_QUAD0_CH1_RSTN(x) ((x) << S_QUAD0_CH1_RSTN)
+#define F_QUAD0_CH1_RSTN    V_QUAD0_CH1_RSTN(1U)
+
+#define S_QUAD0_CH0_RSTN    2
+#define V_QUAD0_CH0_RSTN(x) ((x) << S_QUAD0_CH0_RSTN)
+#define F_QUAD0_CH0_RSTN    V_QUAD0_CH0_RSTN(1U)
+
+#define S_QUAD0_RSTN    1
+#define V_QUAD0_RSTN(x) ((x) << S_QUAD0_RSTN)
+#define F_QUAD0_RSTN    V_QUAD0_RSTN(1U)
+
+#define S_PLL0_RSTN    0
+#define V_PLL0_RSTN(x) ((x) << S_PLL0_RSTN)
+#define F_PLL0_RSTN    V_PLL0_RSTN(1U)
+
+#define A_MAC_IOS_QUAD1_CFG 0x3a05c
+
+#define S_QUAD1_CH3_RSTN    5
+#define V_QUAD1_CH3_RSTN(x) ((x) << S_QUAD1_CH3_RSTN)
+#define F_QUAD1_CH3_RSTN    V_QUAD1_CH3_RSTN(1U)
+
+#define S_QUAD1_CH2_RSTN    4
+#define V_QUAD1_CH2_RSTN(x) ((x) << S_QUAD1_CH2_RSTN)
+#define F_QUAD1_CH2_RSTN    V_QUAD1_CH2_RSTN(1U)
+
+#define S_QUAD1_CH1_RSTN    3
+#define V_QUAD1_CH1_RSTN(x) ((x) << S_QUAD1_CH1_RSTN)
+#define F_QUAD1_CH1_RSTN    V_QUAD1_CH1_RSTN(1U)
+
+#define S_QUAD1_CH0_RSTN    2
+#define V_QUAD1_CH0_RSTN(x) ((x) << S_QUAD1_CH0_RSTN)
+#define F_QUAD1_CH0_RSTN    V_QUAD1_CH0_RSTN(1U)
+
+#define S_QUAD1_RSTN    1
+#define V_QUAD1_RSTN(x) ((x) << S_QUAD1_RSTN)
+#define F_QUAD1_RSTN    V_QUAD1_RSTN(1U)
+
+#define S_PLL1_RSTN    0
+#define V_PLL1_RSTN(x) ((x) << S_PLL1_RSTN)
+#define F_PLL1_RSTN    V_PLL1_RSTN(1U)
+
+#define A_MAC_IOS_SCRATCHPAD0 0x3a060
+#define A_MAC_IOS_SCRATCHPAD1 0x3a064
+#define A_MAC_IOS_SCRATCHPAD2 0x3a068
+#define A_MAC_IOS_SCRATCHPAD3 0x3a06c
+
+#define S_DATA0    1
+#define M_DATA0    0x7fffffffU
+#define V_DATA0(x) ((x) << S_DATA0)
+#define G_DATA0(x) (((x) >> S_DATA0) & M_DATA0)
+
+#define S_I2C_MODE    0
+#define V_I2C_MODE(x) ((x) << S_I2C_MODE)
+#define F_I2C_MODE    V_I2C_MODE(1U)
+
+#define A_MAC_IOS_BGR_DBG_COUNTER 0x3a070
+#define A_MAC_IOS_QUAD0_DBG_COUNTER 0x3a074
+#define A_MAC_IOS_PLL0_DBG_COUNTER 0x3a078
+#define A_MAC_IOS_QUAD1_DBG_COUNTER 0x3a07c
+#define A_MAC_IOS_PLL1_DBG_COUNTER 0x3a080
+#define A_MAC_IOS_DBG_CLK_CFG 0x3a084
+
+#define S_DBG_CLK_MUX_GPIO    3
+#define V_DBG_CLK_MUX_GPIO(x) ((x) << S_DBG_CLK_MUX_GPIO)
+#define F_DBG_CLK_MUX_GPIO    V_DBG_CLK_MUX_GPIO(1U)
+
+#define S_DBG_CLK_MUX_SEL    0
+#define M_DBG_CLK_MUX_SEL    0x7U
+#define V_DBG_CLK_MUX_SEL(x) ((x) << S_DBG_CLK_MUX_SEL)
+#define G_DBG_CLK_MUX_SEL(x) (((x) >> S_DBG_CLK_MUX_SEL) & M_DBG_CLK_MUX_SEL)
+
+#define A_MAC_IOS_INTR_EN_QUAD0 0x3a090
+
+#define S_Q0_MAILBOX_INT_ASSERT    24
+#define V_Q0_MAILBOX_INT_ASSERT(x) ((x) << S_Q0_MAILBOX_INT_ASSERT)
+#define F_Q0_MAILBOX_INT_ASSERT    V_Q0_MAILBOX_INT_ASSERT(1U)
+
+#define S_Q0_TRAINING_FAILURE_3_ASSERT    23
+#define V_Q0_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_3_ASSERT)
+#define F_Q0_TRAINING_FAILURE_3_ASSERT    V_Q0_TRAINING_FAILURE_3_ASSERT(1U)
+
+#define S_Q0_TRAINING_FAILURE_2_ASSERT    22
+#define V_Q0_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_2_ASSERT)
+#define F_Q0_TRAINING_FAILURE_2_ASSERT    V_Q0_TRAINING_FAILURE_2_ASSERT(1U)
+
+#define S_Q0_TRAINING_FAILURE_1_ASSERT    21
+#define V_Q0_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_1_ASSERT)
+#define F_Q0_TRAINING_FAILURE_1_ASSERT    V_Q0_TRAINING_FAILURE_1_ASSERT(1U)
+
+#define S_Q0_TRAINING_FAILURE_0_ASSERT    20
+#define V_Q0_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_0_ASSERT)
+#define F_Q0_TRAINING_FAILURE_0_ASSERT    V_Q0_TRAINING_FAILURE_0_ASSERT(1U)
+
+#define S_Q0_TRAINING_COMPLETE_3_ASSERT    19
+#define V_Q0_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_3_ASSERT)
+#define F_Q0_TRAINING_COMPLETE_3_ASSERT    V_Q0_TRAINING_COMPLETE_3_ASSERT(1U)
+
+#define S_Q0_TRAINING_COMPLETE_2_ASSERT    18
+#define V_Q0_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_2_ASSERT)
+#define F_Q0_TRAINING_COMPLETE_2_ASSERT    V_Q0_TRAINING_COMPLETE_2_ASSERT(1U)
+
+#define S_Q0_TRAINING_COMPLETE_1_ASSERT    17
+#define V_Q0_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_1_ASSERT)
+#define F_Q0_TRAINING_COMPLETE_1_ASSERT    V_Q0_TRAINING_COMPLETE_1_ASSERT(1U)
+
+#define S_Q0_TRAINING_COMPLETE_0_ASSERT    16
+#define V_Q0_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_0_ASSERT)
+#define F_Q0_TRAINING_COMPLETE_0_ASSERT    V_Q0_TRAINING_COMPLETE_0_ASSERT(1U)
+
+#define S_Q0_AN_TX_INT_3_ASSERT    15
+#define V_Q0_AN_TX_INT_3_ASSERT(x) ((x) << S_Q0_AN_TX_INT_3_ASSERT)
+#define F_Q0_AN_TX_INT_3_ASSERT    V_Q0_AN_TX_INT_3_ASSERT(1U)
+
+#define S_Q0_AN_TX_INT_2_ASSERT    14
+#define V_Q0_AN_TX_INT_2_ASSERT(x) ((x) << S_Q0_AN_TX_INT_2_ASSERT)
+#define F_Q0_AN_TX_INT_2_ASSERT    V_Q0_AN_TX_INT_2_ASSERT(1U)
+
+#define S_Q0_AN_TX_INT_1_ASSERT    13
+#define V_Q0_AN_TX_INT_1_ASSERT(x) ((x) << S_Q0_AN_TX_INT_1_ASSERT)
+#define F_Q0_AN_TX_INT_1_ASSERT    V_Q0_AN_TX_INT_1_ASSERT(1U)
+
+#define S_Q0_AN_TX_INT_0_ASSERT    12
+#define V_Q0_AN_TX_INT_0_ASSERT(x) ((x) << S_Q0_AN_TX_INT_0_ASSERT)
+#define F_Q0_AN_TX_INT_0_ASSERT    V_Q0_AN_TX_INT_0_ASSERT(1U)
+
+#define S_Q0_SIGNAL_DETECT_3_ASSERT    11
+#define V_Q0_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_3_ASSERT)
+#define F_Q0_SIGNAL_DETECT_3_ASSERT    V_Q0_SIGNAL_DETECT_3_ASSERT(1U)
+
+#define S_Q0_SIGNAL_DETECT_2_ASSERT    10
+#define V_Q0_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_2_ASSERT)
+#define F_Q0_SIGNAL_DETECT_2_ASSERT    V_Q0_SIGNAL_DETECT_2_ASSERT(1U)
+
+#define S_Q0_SIGNAL_DETECT_1_ASSERT    9
+#define V_Q0_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_1_ASSERT)
+#define F_Q0_SIGNAL_DETECT_1_ASSERT    V_Q0_SIGNAL_DETECT_1_ASSERT(1U)
+
+#define S_Q0_SIGNAL_DETECT_0_ASSERT    8
+#define V_Q0_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_0_ASSERT)
+#define F_Q0_SIGNAL_DETECT_0_ASSERT    V_Q0_SIGNAL_DETECT_0_ASSERT(1U)
+
+#define S_Q0_CDR_LOL_3_ASSERT    7
+#define V_Q0_CDR_LOL_3_ASSERT(x) ((x) << S_Q0_CDR_LOL_3_ASSERT)
+#define F_Q0_CDR_LOL_3_ASSERT    V_Q0_CDR_LOL_3_ASSERT(1U)
+
+#define S_Q0_CDR_LOL_2_ASSERT    6
+#define V_Q0_CDR_LOL_2_ASSERT(x) ((x) << S_Q0_CDR_LOL_2_ASSERT)
+#define F_Q0_CDR_LOL_2_ASSERT    V_Q0_CDR_LOL_2_ASSERT(1U)
+
+#define S_Q0_CDR_LOL_1_ASSERT    5
+#define V_Q0_CDR_LOL_1_ASSERT(x) ((x) << S_Q0_CDR_LOL_1_ASSERT)
+#define F_Q0_CDR_LOL_1_ASSERT    V_Q0_CDR_LOL_1_ASSERT(1U)
+
+#define S_Q0_CDR_LOL_0_ASSERT    4
+#define V_Q0_CDR_LOL_0_ASSERT(x) ((x) << S_Q0_CDR_LOL_0_ASSERT)
+#define F_Q0_CDR_LOL_0_ASSERT    V_Q0_CDR_LOL_0_ASSERT(1U)
+
+#define S_Q0_LOS_3_ASSERT    3
+#define V_Q0_LOS_3_ASSERT(x) ((x) << S_Q0_LOS_3_ASSERT)
+#define F_Q0_LOS_3_ASSERT    V_Q0_LOS_3_ASSERT(1U)
+
+#define S_Q0_LOS_2_ASSERT    2
+#define V_Q0_LOS_2_ASSERT(x) ((x) << S_Q0_LOS_2_ASSERT)
+#define F_Q0_LOS_2_ASSERT    V_Q0_LOS_2_ASSERT(1U)
+
+#define S_Q0_LOS_1_ASSERT    1
+#define V_Q0_LOS_1_ASSERT(x) ((x) << S_Q0_LOS_1_ASSERT)
+#define F_Q0_LOS_1_ASSERT    V_Q0_LOS_1_ASSERT(1U)
+
+#define S_Q0_LOS_0_ASSERT    0
+#define V_Q0_LOS_0_ASSERT(x) ((x) << S_Q0_LOS_0_ASSERT)
+#define F_Q0_LOS_0_ASSERT    V_Q0_LOS_0_ASSERT(1U)
+
+#define A_MAC_IOS_INTR_CAUSE_QUAD0 0x3a094
+#define A_MAC_IOS_INTR_EN_QUAD1 0x3a098
+
+#define S_Q1_MAILBOX_INT_ASSERT    24
+#define V_Q1_MAILBOX_INT_ASSERT(x) ((x) << S_Q1_MAILBOX_INT_ASSERT)
+#define F_Q1_MAILBOX_INT_ASSERT    V_Q1_MAILBOX_INT_ASSERT(1U)
+
+#define S_Q1_TRAINING_FAILURE_3_ASSERT    23
+#define V_Q1_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_3_ASSERT)
+#define F_Q1_TRAINING_FAILURE_3_ASSERT    V_Q1_TRAINING_FAILURE_3_ASSERT(1U)
+
+#define S_Q1_TRAINING_FAILURE_2_ASSERT    22
+#define V_Q1_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_2_ASSERT)
+#define F_Q1_TRAINING_FAILURE_2_ASSERT    V_Q1_TRAINING_FAILURE_2_ASSERT(1U)
+
+#define S_Q1_TRAINING_FAILURE_1_ASSERT    21
+#define V_Q1_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_1_ASSERT)
+#define F_Q1_TRAINING_FAILURE_1_ASSERT    V_Q1_TRAINING_FAILURE_1_ASSERT(1U)
+
+#define S_Q1_TRAINING_FAILURE_0_ASSERT    20
+#define V_Q1_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_0_ASSERT)
+#define F_Q1_TRAINING_FAILURE_0_ASSERT    V_Q1_TRAINING_FAILURE_0_ASSERT(1U)
+
+#define S_Q1_TRAINING_COMPLETE_3_ASSERT    19
+#define V_Q1_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_3_ASSERT)
+#define F_Q1_TRAINING_COMPLETE_3_ASSERT    V_Q1_TRAINING_COMPLETE_3_ASSERT(1U)
+
+#define S_Q1_TRAINING_COMPLETE_2_ASSERT    18
+#define V_Q1_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_2_ASSERT)
+#define F_Q1_TRAINING_COMPLETE_2_ASSERT    V_Q1_TRAINING_COMPLETE_2_ASSERT(1U)
+
+#define S_Q1_TRAINING_COMPLETE_1_ASSERT    17
+#define V_Q1_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_1_ASSERT)
+#define F_Q1_TRAINING_COMPLETE_1_ASSERT    V_Q1_TRAINING_COMPLETE_1_ASSERT(1U)
+
+#define S_Q1_TRAINING_COMPLETE_0_ASSERT    16
+#define V_Q1_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_0_ASSERT)
+#define F_Q1_TRAINING_COMPLETE_0_ASSERT    V_Q1_TRAINING_COMPLETE_0_ASSERT(1U)
+
+#define S_Q1_AN_TX_INT_3_ASSERT    15
+#define V_Q1_AN_TX_INT_3_ASSERT(x) ((x) << S_Q1_AN_TX_INT_3_ASSERT)
+#define F_Q1_AN_TX_INT_3_ASSERT    V_Q1_AN_TX_INT_3_ASSERT(1U)
+
+#define S_Q1_AN_TX_INT_2_ASSERT    14
+#define V_Q1_AN_TX_INT_2_ASSERT(x) ((x) << S_Q1_AN_TX_INT_2_ASSERT)
+#define F_Q1_AN_TX_INT_2_ASSERT    V_Q1_AN_TX_INT_2_ASSERT(1U)
+
+#define S_Q1_AN_TX_INT_1_ASSERT    13
+#define V_Q1_AN_TX_INT_1_ASSERT(x) ((x) << S_Q1_AN_TX_INT_1_ASSERT)
+#define F_Q1_AN_TX_INT_1_ASSERT    V_Q1_AN_TX_INT_1_ASSERT(1U)
+
+#define S_Q1_AN_TX_INT_0_ASSERT    12
+#define V_Q1_AN_TX_INT_0_ASSERT(x) ((x) << S_Q1_AN_TX_INT_0_ASSERT)
+#define F_Q1_AN_TX_INT_0_ASSERT    V_Q1_AN_TX_INT_0_ASSERT(1U)
+
+#define S_Q1_SIGNAL_DETECT_3_ASSERT    11
+#define V_Q1_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_3_ASSERT)
+#define F_Q1_SIGNAL_DETECT_3_ASSERT    V_Q1_SIGNAL_DETECT_3_ASSERT(1U)
+
+#define S_Q1_SIGNAL_DETECT_2_ASSERT    10
+#define V_Q1_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_2_ASSERT)
+#define F_Q1_SIGNAL_DETECT_2_ASSERT    V_Q1_SIGNAL_DETECT_2_ASSERT(1U)
+
+#define S_Q1_SIGNAL_DETECT_1_ASSERT    9
+#define V_Q1_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_1_ASSERT)
+#define F_Q1_SIGNAL_DETECT_1_ASSERT    V_Q1_SIGNAL_DETECT_1_ASSERT(1U)
+
+#define S_Q1_SIGNAL_DETECT_0_ASSERT    8
+#define V_Q1_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_0_ASSERT)
+#define F_Q1_SIGNAL_DETECT_0_ASSERT    V_Q1_SIGNAL_DETECT_0_ASSERT(1U)
+
+#define S_Q1_CDR_LOL_3_ASSERT    7
+#define V_Q1_CDR_LOL_3_ASSERT(x) ((x) << S_Q1_CDR_LOL_3_ASSERT)
+#define F_Q1_CDR_LOL_3_ASSERT    V_Q1_CDR_LOL_3_ASSERT(1U)
+
+#define S_Q1_CDR_LOL_2_ASSERT    6
+#define V_Q1_CDR_LOL_2_ASSERT(x) ((x) << S_Q1_CDR_LOL_2_ASSERT)
+#define F_Q1_CDR_LOL_2_ASSERT    V_Q1_CDR_LOL_2_ASSERT(1U)
+
+#define S_Q1_CDR_LOL_1_ASSERT    5
+#define V_Q1_CDR_LOL_1_ASSERT(x) ((x) << S_Q1_CDR_LOL_1_ASSERT)
+#define F_Q1_CDR_LOL_1_ASSERT    V_Q1_CDR_LOL_1_ASSERT(1U)
+
+#define S_Q1_CDR_LOL_0_ASSERT    4
+#define V_Q1_CDR_LOL_0_ASSERT(x) ((x) << S_Q1_CDR_LOL_0_ASSERT)
+#define F_Q1_CDR_LOL_0_ASSERT    V_Q1_CDR_LOL_0_ASSERT(1U)
+
+#define S_Q1_LOS_3_ASSERT    3
+#define V_Q1_LOS_3_ASSERT(x) ((x) << S_Q1_LOS_3_ASSERT)
+#define F_Q1_LOS_3_ASSERT    V_Q1_LOS_3_ASSERT(1U)
+
+#define S_Q1_LOS_2_ASSERT    2
+#define V_Q1_LOS_2_ASSERT(x) ((x) << S_Q1_LOS_2_ASSERT)
+#define F_Q1_LOS_2_ASSERT    V_Q1_LOS_2_ASSERT(1U)
+
+#define S_Q1_LOS_1_ASSERT    1
+#define V_Q1_LOS_1_ASSERT(x) ((x) << S_Q1_LOS_1_ASSERT)
+#define F_Q1_LOS_1_ASSERT    V_Q1_LOS_1_ASSERT(1U)
+
+#define S_Q1_LOS_0_ASSERT    0
+#define V_Q1_LOS_0_ASSERT(x) ((x) << S_Q1_LOS_0_ASSERT)
+#define F_Q1_LOS_0_ASSERT    V_Q1_LOS_0_ASSERT(1U)
+
+#define A_MAC_IOS_INTR_CAUSE_QUAD1 0x3a09c
+#define A_MAC_MTIP_PCS_1G_0_CONTROL 0x3e000
+
+#define S_SPEED_SEL_1    13
+#define V_SPEED_SEL_1(x) ((x) << S_SPEED_SEL_1)
+#define F_SPEED_SEL_1    V_SPEED_SEL_1(1U)
+
+#define S_AUTO_NEG_ENA    12
+#define V_AUTO_NEG_ENA(x) ((x) << S_AUTO_NEG_ENA)
+#define F_AUTO_NEG_ENA    V_AUTO_NEG_ENA(1U)
+
+#define S_T7_POWER_DOWN    11
+#define V_T7_POWER_DOWN(x) ((x) << S_T7_POWER_DOWN)
+#define F_T7_POWER_DOWN    V_T7_POWER_DOWN(1U)
+
+#define S_RESTART_AUTO_NEG    9
+#define V_RESTART_AUTO_NEG(x) ((x) << S_RESTART_AUTO_NEG)
+#define F_RESTART_AUTO_NEG    V_RESTART_AUTO_NEG(1U)
+
+#define S_SPEED_SEL_0    6
+#define V_SPEED_SEL_0(x) ((x) << S_SPEED_SEL_0)
+#define F_SPEED_SEL_0    V_SPEED_SEL_0(1U)
+
+#define A_MAC_MTIP_PCS_1G_0_STATUS 0x3e004
+
+#define S_100BASE_T4    15
+#define V_100BASE_T4(x) ((x) << S_100BASE_T4)
+#define F_100BASE_T4    V_100BASE_T4(1U)
+
+#define S_100BASE_X_FULL_DUPLEX    14
+#define V_100BASE_X_FULL_DUPLEX(x) ((x) << S_100BASE_X_FULL_DUPLEX)
+#define F_100BASE_X_FULL_DUPLEX    V_100BASE_X_FULL_DUPLEX(1U)
+
+#define S_100BASE_X_HALF_DUPLEX    13
+#define V_100BASE_X_HALF_DUPLEX(x) ((x) << S_100BASE_X_HALF_DUPLEX)
+#define F_100BASE_X_HALF_DUPLEX    V_100BASE_X_HALF_DUPLEX(1U)
+
+#define S_10MBPS_FULL_DUPLEX    12
+#define V_10MBPS_FULL_DUPLEX(x) ((x) << S_10MBPS_FULL_DUPLEX)
+#define F_10MBPS_FULL_DUPLEX    V_10MBPS_FULL_DUPLEX(1U)
+
+#define S_10MBPS_HALF_DUPLEX    11
+#define V_10MBPS_HALF_DUPLEX(x) ((x) << S_10MBPS_HALF_DUPLEX)
+#define F_10MBPS_HALF_DUPLEX    V_10MBPS_HALF_DUPLEX(1U)
+
+#define S_100BASE_T2_HALF_DUPLEX1    10
+#define V_100BASE_T2_HALF_DUPLEX1(x) ((x) << S_100BASE_T2_HALF_DUPLEX1)
+#define F_100BASE_T2_HALF_DUPLEX1    V_100BASE_T2_HALF_DUPLEX1(1U)
+
+#define S_100BASE_T2_HALF_DUPLEX0    9
+#define V_100BASE_T2_HALF_DUPLEX0(x) ((x) << S_100BASE_T2_HALF_DUPLEX0)
+#define F_100BASE_T2_HALF_DUPLEX0    V_100BASE_T2_HALF_DUPLEX0(1U)
+
+#define S_T7_EXTENDED_STATUS    8
+#define V_T7_EXTENDED_STATUS(x) ((x) << S_T7_EXTENDED_STATUS)
+#define F_T7_EXTENDED_STATUS    V_T7_EXTENDED_STATUS(1U)
+
+#define S_AUTO_NEG_COMPLETE    5
+#define V_AUTO_NEG_COMPLETE(x) ((x) << S_AUTO_NEG_COMPLETE)
+#define F_AUTO_NEG_COMPLETE    V_AUTO_NEG_COMPLETE(1U)
+
+#define S_T7_REMOTE_FAULT    4
+#define V_T7_REMOTE_FAULT(x) ((x) << S_T7_REMOTE_FAULT)
+#define F_T7_REMOTE_FAULT    V_T7_REMOTE_FAULT(1U)
+
+#define S_AUTO_NEG_ABILITY    3
+#define V_AUTO_NEG_ABILITY(x) ((x) << S_AUTO_NEG_ABILITY)
+#define F_AUTO_NEG_ABILITY    V_AUTO_NEG_ABILITY(1U)
+
+#define S_JABBER_DETECT    1
+#define V_JABBER_DETECT(x) ((x) << S_JABBER_DETECT)
+#define F_JABBER_DETECT    V_JABBER_DETECT(1U)
+
+#define S_EXTENDED_CAPABILITY    0
+#define V_EXTENDED_CAPABILITY(x) ((x) << S_EXTENDED_CAPABILITY)
+#define F_EXTENDED_CAPABILITY    V_EXTENDED_CAPABILITY(1U)
+
+#define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_0 0x3e008
+#define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_1 0x3e00c
+#define A_MAC_MTIP_PCS_1G_0_DEV_ABILITY 0x3e010
+
+#define S_EEE_CLOCK_STOP_ENABLE    8
+#define V_EEE_CLOCK_STOP_ENABLE(x) ((x) << S_EEE_CLOCK_STOP_ENABLE)
+#define F_EEE_CLOCK_STOP_ENABLE    V_EEE_CLOCK_STOP_ENABLE(1U)
+
+#define A_MAC_MTIP_PCS_1G_0_PARTNER_ABILITY 0x3e014
+
+#define S_COPPER_LINK_STATUS    15
+#define V_COPPER_LINK_STATUS(x) ((x) << S_COPPER_LINK_STATUS)
+#define F_COPPER_LINK_STATUS    V_COPPER_LINK_STATUS(1U)
+
+#define S_COPPER_DUPLEX_STATUS    12
+#define V_COPPER_DUPLEX_STATUS(x) ((x) << S_COPPER_DUPLEX_STATUS)
+#define F_COPPER_DUPLEX_STATUS    V_COPPER_DUPLEX_STATUS(1U)
+
+#define S_COPPER_SPEED    10
+#define M_COPPER_SPEED    0x3U
+#define V_COPPER_SPEED(x) ((x) << S_COPPER_SPEED)
+#define G_COPPER_SPEED(x) (((x) >> S_COPPER_SPEED) & M_COPPER_SPEED)
+
+#define S_EEE_CAPABILITY    9
+#define V_EEE_CAPABILITY(x) ((x) << S_EEE_CAPABILITY)
+#define F_EEE_CAPABILITY    V_EEE_CAPABILITY(1U)
+
+#define S_EEE_CLOCK_STOP_CAPABILITY    8
+#define V_EEE_CLOCK_STOP_CAPABILITY(x) ((x) << S_EEE_CLOCK_STOP_CAPABILITY)
+#define F_EEE_CLOCK_STOP_CAPABILITY    V_EEE_CLOCK_STOP_CAPABILITY(1U)
+
+#define A_MAC_MTIP_PCS_1G_0_AN_EXPANSION 0x3e018
+#define A_MAC_MTIP_PCS_1G_0_NP_TX 0x3e01c
+#define A_MAC_MTIP_PCS_1G_0_LP_NP_RX 0x3e020
+
+#define S_T7_DATA    0
+#define M_T7_DATA    0x7ffU
+#define V_T7_DATA(x) ((x) << S_T7_DATA)
+#define G_T7_DATA(x) (((x) >> S_T7_DATA) & M_T7_DATA)
+
+#define A_MAC_MTIP_PCS_1G_0_EXTENDED_STATUS 0x3e03c
+#define A_MAC_MTIP_PCS_1G_0_SCRATCH 0x3e040
+#define A_MAC_MTIP_PCS_1G_0_REV 0x3e044
+#define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_0 0x3e048
+
+#define S_LINK_TIMER_VAL    0
+#define M_LINK_TIMER_VAL    0xffffU
+#define V_LINK_TIMER_VAL(x) ((x) << S_LINK_TIMER_VAL)
+#define G_LINK_TIMER_VAL(x) (((x) >> S_LINK_TIMER_VAL) & M_LINK_TIMER_VAL)
+
+#define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_1 0x3e04c
+
+#define S_T7_LINK_TIMER_VAL    0
+#define M_T7_LINK_TIMER_VAL    0x1fU
+#define V_T7_LINK_TIMER_VAL(x) ((x) << S_T7_LINK_TIMER_VAL)
+#define G_T7_LINK_TIMER_VAL(x) (((x) >> S_T7_LINK_TIMER_VAL) & M_T7_LINK_TIMER_VAL)
+
+#define A_MAC_MTIP_PCS_1G_0_IF_MODE 0x3e050
+#define A_MAC_MTIP_PCS_1G_0_DEC_ERR_CNT 0x3e054
+#define A_MAC_MTIP_PCS_1G_0_VENDOR_CONTROL 0x3e058
+
+#define S_SGPCS_ENA_ST    15
+#define V_SGPCS_ENA_ST(x) ((x) << S_SGPCS_ENA_ST)
+#define F_SGPCS_ENA_ST    V_SGPCS_ENA_ST(1U)
+
+#define S_T7_CFG_CLOCK_RATE    4
+#define M_T7_CFG_CLOCK_RATE    0xfU
+#define V_T7_CFG_CLOCK_RATE(x) ((x) << S_T7_CFG_CLOCK_RATE)
+#define G_T7_CFG_CLOCK_RATE(x) (((x) >> S_T7_CFG_CLOCK_RATE) & M_T7_CFG_CLOCK_RATE)
+
+#define S_SGPCS_ENA_R    0
+#define V_SGPCS_ENA_R(x) ((x) << S_SGPCS_ENA_R)
+#define F_SGPCS_ENA_R    V_SGPCS_ENA_R(1U)
+
+#define A_MAC_MTIP_PCS_1G_0_SD_BIT_SLIP 0x3e05c
+
+#define S_SD_BIT_SLIP    0
+#define M_SD_BIT_SLIP    0xfU
+#define V_SD_BIT_SLIP(x) ((x) << S_SD_BIT_SLIP)
+#define G_SD_BIT_SLIP(x) (((x) >> S_SD_BIT_SLIP) & M_SD_BIT_SLIP)
+
+#define A_MAC_MTIP_PCS_1G_1_CONTROL 0x3e100
+#define A_MAC_MTIP_PCS_1G_1_STATUS 0x3e104
+#define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_0 0x3e108
+#define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_1 0x3e10c
+#define A_MAC_MTIP_PCS_1G_1_DEV_ABILITY 0x3e110
+#define A_MAC_MTIP_PCS_1G_1_PARTNER_ABILITY 0x3e114
+#define A_MAC_MTIP_PCS_1G_1_AN_EXPANSION 0x3e118
+#define A_MAC_MTIP_PCS_1G_1_NP_TX 0x3e11c
+#define A_MAC_MTIP_PCS_1G_1_LP_NP_RX 0x3e120
+#define A_MAC_MTIP_PCS_1G_1_EXTENDED_STATUS 0x3e13c
+#define A_MAC_MTIP_PCS_1G_1_SCRATCH 0x3e140
+#define A_MAC_MTIP_PCS_1G_1_REV 0x3e144
+#define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_0 0x3e148
+#define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_1 0x3e14c
+#define A_MAC_MTIP_PCS_1G_1_IF_MODE 0x3e150
+#define A_MAC_MTIP_PCS_1G_1_DEC_ERR_CNT 0x3e154
+#define A_MAC_MTIP_PCS_1G_1_VENDOR_CONTROL 0x3e158
+#define A_MAC_MTIP_PCS_1G_1_SD_BIT_SLIP 0x3e15c
+#define A_MAC_MTIP_PCS_1G_2_CONTROL 0x3e200
+#define A_MAC_MTIP_PCS_1G_2_STATUS 0x3e204
+#define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_0 0x3e208
+#define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_1 0x3e20c
+#define A_MAC_MTIP_PCS_1G_2_DEV_ABILITY 0x3e210
+#define A_MAC_MTIP_PCS_1G_2_PARTNER_ABILITY 0x3e214
+#define A_MAC_MTIP_PCS_1G_2_AN_EXPANSION 0x3e218
+#define A_MAC_MTIP_PCS_1G_2_NP_TX 0x3e21c
+#define A_MAC_MTIP_PCS_1G_2_LP_NP_RX 0x3e220
+#define A_MAC_MTIP_PCS_1G_2_EXTENDED_STATUS 0x3e23c
+#define A_MAC_MTIP_PCS_1G_2_SCRATCH 0x3e240
+#define A_MAC_MTIP_PCS_1G_2_REV 0x3e244
+#define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_0 0x3e248
+#define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_1 0x3e24c
+#define A_MAC_MTIP_PCS_1G_2_IF_MODE 0x3e250
+#define A_MAC_MTIP_PCS_1G_2_DEC_ERR_CNT 0x3e254
+#define A_MAC_MTIP_PCS_1G_2_VENDOR_CONTROL 0x3e258
+#define A_MAC_MTIP_PCS_1G_2_SD_BIT_SLIP 0x3e25c
+#define A_MAC_MTIP_PCS_1G_3_CONTROL 0x3e300
+#define A_MAC_MTIP_PCS_1G_3_STATUS 0x3e304
+#define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_0 0x3e308
+#define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_1 0x3e30c
+#define A_MAC_MTIP_PCS_1G_3_DEV_ABILITY 0x3e310
+#define A_MAC_MTIP_PCS_1G_3_PARTNER_ABILITY 0x3e314
+#define A_MAC_MTIP_PCS_1G_3_AN_EXPANSION 0x3e318
+#define A_MAC_MTIP_PCS_1G_3_NP_TX 0x3e31c
+#define A_MAC_MTIP_PCS_1G_3_LP_NP_RX 0x3e320
+#define A_MAC_MTIP_PCS_1G_3_EXTENDED_STATUS 0x3e33c
+#define A_MAC_MTIP_PCS_1G_3_SCRATCH 0x3e340
+#define A_MAC_MTIP_PCS_1G_3_REV 0x3e344
+#define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_0 0x3e348
+#define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_1 0x3e34c
+#define A_MAC_MTIP_PCS_1G_3_IF_MODE 0x3e350
+#define A_MAC_MTIP_PCS_1G_3_DEC_ERR_CNT 0x3e354
+#define A_MAC_MTIP_PCS_1G_3_VENDOR_CONTROL 0x3e358
+#define A_MAC_MTIP_PCS_1G_3_SD_BIT_SLIP 0x3e35c
+#define A_MAC_DPLL_CTRL_0 0x3f000
+
+#define S_LOCAL_FAULT_OVRD    18
+#define V_LOCAL_FAULT_OVRD(x) ((x) << S_LOCAL_FAULT_OVRD)
+#define F_LOCAL_FAULT_OVRD    V_LOCAL_FAULT_OVRD(1U)
+
+#define S_LOCAL_FAULT_HOLD_EN    17
+#define V_LOCAL_FAULT_HOLD_EN(x) ((x) << S_LOCAL_FAULT_HOLD_EN)
+#define F_LOCAL_FAULT_HOLD_EN    V_LOCAL_FAULT_HOLD_EN(1U)
+
+#define S_DPLL_RST    16
+#define V_DPLL_RST(x) ((x) << S_DPLL_RST)
+#define F_DPLL_RST    V_DPLL_RST(1U)
+
+#define S_CNTOFFSET    0
+#define M_CNTOFFSET    0xffffU
+#define V_CNTOFFSET(x) ((x) << S_CNTOFFSET)
+#define G_CNTOFFSET(x) (((x) >> S_CNTOFFSET) & M_CNTOFFSET)
+
+#define A_MAC_DPLL_CTRL_1 0x3f004
+
+#define S_DELAYK    0
+#define M_DELAYK    0xffffffU
+#define V_DELAYK(x) ((x) << S_DELAYK)
+#define G_DELAYK(x) (((x) >> S_DELAYK) & M_DELAYK)
+
+#define A_MAC_DPLL_CTRL_2 0x3f008
+
+#define S_DIVFFB    16
+#define M_DIVFFB    0xffffU
+#define V_DIVFFB(x) ((x) << S_DIVFFB)
+#define G_DIVFFB(x) (((x) >> S_DIVFFB) & M_DIVFFB)
+
+#define S_DIVFIN    0
+#define M_DIVFIN    0xffffU
+#define V_DIVFIN(x) ((x) << S_DIVFIN)
+#define G_DIVFIN(x) (((x) >> S_DIVFIN) & M_DIVFIN)
+
+#define A_MAC_DPLL_CTRL_3 0x3f00c
+
+#define S_ISHIFT_HOLD    28
+#define M_ISHIFT_HOLD    0xfU
+#define V_ISHIFT_HOLD(x) ((x) << S_ISHIFT_HOLD)
+#define G_ISHIFT_HOLD(x) (((x) >> S_ISHIFT_HOLD) & M_ISHIFT_HOLD)
+
+#define S_ISHIFT    24
+#define M_ISHIFT    0xfU
+#define V_ISHIFT(x) ((x) << S_ISHIFT)
+#define G_ISHIFT(x) (((x) >> S_ISHIFT) & M_ISHIFT)
+
+#define S_INT_PRESET    12
+#define M_INT_PRESET    0xfffU
+#define V_INT_PRESET(x) ((x) << S_INT_PRESET)
+#define G_INT_PRESET(x) (((x) >> S_INT_PRESET) & M_INT_PRESET)
+
+#define S_FMI    4
+#define M_FMI    0xffU
+#define V_FMI(x) ((x) << S_FMI)
+#define G_FMI(x) (((x) >> S_FMI) & M_FMI)
+
+#define S_DPLL_PROGRAM    3
+#define V_DPLL_PROGRAM(x) ((x) << S_DPLL_PROGRAM)
+#define F_DPLL_PROGRAM    V_DPLL_PROGRAM(1U)
+
+#define S_PRESET_EN    2
+#define V_PRESET_EN(x) ((x) << S_PRESET_EN)
+#define F_PRESET_EN    V_PRESET_EN(1U)
+
+#define S_ONTARGETOV    1
+#define V_ONTARGETOV(x) ((x) << S_ONTARGETOV)
+#define F_ONTARGETOV    V_ONTARGETOV(1U)
+
+#define S_FDONLY    0
+#define V_FDONLY(x) ((x) << S_FDONLY)
+#define F_FDONLY    V_FDONLY(1U)
+
+#define A_MAC_DPLL_CTRL_4 0x3f010
+
+#define S_FKI    24
+#define M_FKI    0x1fU
+#define V_FKI(x) ((x) << S_FKI)
+#define G_FKI(x) (((x) >> S_FKI) & M_FKI)
+
+#define S_FRAC_PRESET    0
+#define M_FRAC_PRESET    0xffffffU
+#define V_FRAC_PRESET(x) ((x) << S_FRAC_PRESET)
+#define G_FRAC_PRESET(x) (((x) >> S_FRAC_PRESET) & M_FRAC_PRESET)
+
+#define A_MAC_DPLL_CTRL_5 0x3f014
+
+#define S_PH_STEP_CNT_HOLD    24
+#define M_PH_STEP_CNT_HOLD    0x1fU
+#define V_PH_STEP_CNT_HOLD(x) ((x) << S_PH_STEP_CNT_HOLD)
+#define G_PH_STEP_CNT_HOLD(x) (((x) >> S_PH_STEP_CNT_HOLD) & M_PH_STEP_CNT_HOLD)
+
+#define S_CFG_RESET    23
+#define V_CFG_RESET(x) ((x) << S_CFG_RESET)
+#define F_CFG_RESET    V_CFG_RESET(1U)
+
+#define S_PH_STEP_CNT    16
+#define M_PH_STEP_CNT    0x1fU
+#define V_PH_STEP_CNT(x) ((x) << S_PH_STEP_CNT)
+#define G_PH_STEP_CNT(x) (((x) >> S_PH_STEP_CNT) & M_PH_STEP_CNT)
+
+#define S_OTDLY    0
+#define M_OTDLY    0xffffU
+#define V_OTDLY(x) ((x) << S_OTDLY)
+#define G_OTDLY(x) (((x) >> S_OTDLY) & M_OTDLY)
+
+#define A_MAC_DPLL_CTRL_6 0x3f018
+
+#define S_TARGETCNT    16
+#define M_TARGETCNT    0xffffU
+#define V_TARGETCNT(x) ((x) << S_TARGETCNT)
+#define G_TARGETCNT(x) (((x) >> S_TARGETCNT) & M_TARGETCNT)
+
+#define S_PKP    8
+#define M_PKP    0x1fU
+#define V_PKP(x) ((x) << S_PKP)
+#define G_PKP(x) (((x) >> S_PKP) & M_PKP)
+
+#define S_PMP    0
+#define M_PMP    0xffU
+#define V_PMP(x) ((x) << S_PMP)
+#define G_PMP(x) (((x) >> S_PMP) & M_PMP)
+
+#define A_MAC_DPLL_CTRL_7 0x3f01c
+#define A_MAC_DPLL_STATUS_0 0x3f020
+
+#define S_FRAC    0
+#define M_FRAC    0xffffffU
+#define V_FRAC(x) ((x) << S_FRAC)
+#define G_FRAC(x) (((x) >> S_FRAC) & M_FRAC)
+
+#define A_MAC_DPLL_STATUS_1 0x3f024
+
+#define S_FRAC_PD_OUT    0
+#define M_FRAC_PD_OUT    0xffffffU
+#define V_FRAC_PD_OUT(x) ((x) << S_FRAC_PD_OUT)
+#define G_FRAC_PD_OUT(x) (((x) >> S_FRAC_PD_OUT) & M_FRAC_PD_OUT)
+
+#define A_MAC_DPLL_STATUS_2 0x3f028
+
+#define S_INT    12
+#define M_INT    0xfffU
+#define V_INT(x) ((x) << S_INT)
+#define G_INT(x) (((x) >> S_INT) & M_INT)
+
+#define S_INT_PD_OUT    0
+#define M_INT_PD_OUT    0xfffU
+#define V_INT_PD_OUT(x) ((x) << S_INT_PD_OUT)
+#define G_INT_PD_OUT(x) (((x) >> S_INT_PD_OUT) & M_INT_PD_OUT)
+
+#define A_MAC_FRAC_N_PLL_CTRL_0 0x3f02c
+
+#define S_FRAC_N_DSKEWCALCNT    29
+#define M_FRAC_N_DSKEWCALCNT    0x7U
+#define V_FRAC_N_DSKEWCALCNT(x) ((x) << S_FRAC_N_DSKEWCALCNT)
+#define G_FRAC_N_DSKEWCALCNT(x) (((x) >> S_FRAC_N_DSKEWCALCNT) & M_FRAC_N_DSKEWCALCNT)
+
+#define S_PLLEN    28
+#define V_PLLEN(x) ((x) << S_PLLEN)
+#define F_PLLEN    V_PLLEN(1U)
+
+#define S_T7_BYPASS    24
+#define M_T7_BYPASS    0xfU
+#define V_T7_BYPASS(x) ((x) << S_T7_BYPASS)
+#define G_T7_BYPASS(x) (((x) >> S_T7_BYPASS) & M_T7_BYPASS)
+
+#define S_POSTDIV3A    21
+#define M_POSTDIV3A    0x7U
+#define V_POSTDIV3A(x) ((x) << S_POSTDIV3A)
+#define G_POSTDIV3A(x) (((x) >> S_POSTDIV3A) & M_POSTDIV3A)
+
+#define S_POSTDIV3B    18
+#define M_POSTDIV3B    0x7U
+#define V_POSTDIV3B(x) ((x) << S_POSTDIV3B)
+#define G_POSTDIV3B(x) (((x) >> S_POSTDIV3B) & M_POSTDIV3B)
+
+#define S_POSTDIV2A    15
+#define M_POSTDIV2A    0x7U
+#define V_POSTDIV2A(x) ((x) << S_POSTDIV2A)
+#define G_POSTDIV2A(x) (((x) >> S_POSTDIV2A) & M_POSTDIV2A)
+
+#define S_POSTDIV2B    12
+#define M_POSTDIV2B    0x7U
+#define V_POSTDIV2B(x) ((x) << S_POSTDIV2B)
+#define G_POSTDIV2B(x) (((x) >> S_POSTDIV2B) & M_POSTDIV2B)
+
+#define S_POSTDIV1A    9
+#define M_POSTDIV1A    0x7U
+#define V_POSTDIV1A(x) ((x) << S_POSTDIV1A)
+#define G_POSTDIV1A(x) (((x) >> S_POSTDIV1A) & M_POSTDIV1A)
+
+#define S_POSTDIV1B    6
+#define M_POSTDIV1B    0x7U
+#define V_POSTDIV1B(x) ((x) << S_POSTDIV1B)
+#define G_POSTDIV1B(x) (((x) >> S_POSTDIV1B) & M_POSTDIV1B)
+
+#define S_POSTDIV0A    3
+#define M_POSTDIV0A    0x7U
+#define V_POSTDIV0A(x) ((x) << S_POSTDIV0A)
+#define G_POSTDIV0A(x) (((x) >> S_POSTDIV0A) & M_POSTDIV0A)
+
+#define S_POSTDIV0B    0
+#define M_POSTDIV0B    0x7U
+#define V_POSTDIV0B(x) ((x) << S_POSTDIV0B)
+#define G_POSTDIV0B(x) (((x) >> S_POSTDIV0B) & M_POSTDIV0B)
+
+#define A_MAC_FRAC_N_PLL_CTRL_1 0x3f030
+
+#define S_FRAC_N_FRAC_N_FOUTEN    28
+#define M_FRAC_N_FRAC_N_FOUTEN    0xfU
+#define V_FRAC_N_FRAC_N_FOUTEN(x) ((x) << S_FRAC_N_FRAC_N_FOUTEN)
+#define G_FRAC_N_FRAC_N_FOUTEN(x) (((x) >> S_FRAC_N_FRAC_N_FOUTEN) & M_FRAC_N_FRAC_N_FOUTEN)
+
+#define S_FRAC_N_DSKEWCALIN    16
+#define M_FRAC_N_DSKEWCALIN    0xfffU
+#define V_FRAC_N_DSKEWCALIN(x) ((x) << S_FRAC_N_DSKEWCALIN)
+#define G_FRAC_N_DSKEWCALIN(x) (((x) >> S_FRAC_N_DSKEWCALIN) & M_FRAC_N_DSKEWCALIN)
+
+#define S_FRAC_N_REFDIV    10
+#define M_FRAC_N_REFDIV    0x3fU
+#define V_FRAC_N_REFDIV(x) ((x) << S_FRAC_N_REFDIV)
+#define G_FRAC_N_REFDIV(x) (((x) >> S_FRAC_N_REFDIV) & M_FRAC_N_REFDIV)
+
+#define S_FRAC_N_DSMEN    9
+#define V_FRAC_N_DSMEN(x) ((x) << S_FRAC_N_DSMEN)
+#define F_FRAC_N_DSMEN    V_FRAC_N_DSMEN(1U)
+
+#define S_FRAC_N_PLLEN    8
+#define V_FRAC_N_PLLEN(x) ((x) << S_FRAC_N_PLLEN)
+#define F_FRAC_N_PLLEN    V_FRAC_N_PLLEN(1U)
+
+#define S_FRAC_N_DACEN    7
+#define V_FRAC_N_DACEN(x) ((x) << S_FRAC_N_DACEN)
+#define F_FRAC_N_DACEN    V_FRAC_N_DACEN(1U)
+
+#define S_FRAC_N_POSTDIV0PRE    6
+#define V_FRAC_N_POSTDIV0PRE(x) ((x) << S_FRAC_N_POSTDIV0PRE)
+#define F_FRAC_N_POSTDIV0PRE    V_FRAC_N_POSTDIV0PRE(1U)
+
+#define S_FRAC_N_DSKEWCALBYP    5
+#define V_FRAC_N_DSKEWCALBYP(x) ((x) << S_FRAC_N_DSKEWCALBYP)
+#define F_FRAC_N_DSKEWCALBYP    V_FRAC_N_DSKEWCALBYP(1U)
+
+#define S_FRAC_N_DSKEWFASTCAL    4
+#define V_FRAC_N_DSKEWFASTCAL(x) ((x) << S_FRAC_N_DSKEWFASTCAL)
+#define F_FRAC_N_DSKEWFASTCAL    V_FRAC_N_DSKEWFASTCAL(1U)
+
+#define S_FRAC_N_DSKEWCALEN    3
+#define V_FRAC_N_DSKEWCALEN(x) ((x) << S_FRAC_N_DSKEWCALEN)
+#define F_FRAC_N_DSKEWCALEN    V_FRAC_N_DSKEWCALEN(1U)
+
+#define S_FRAC_N_FREFCMLEN    2
+#define V_FRAC_N_FREFCMLEN(x) ((x) << S_FRAC_N_FREFCMLEN)
+#define F_FRAC_N_FREFCMLEN    V_FRAC_N_FREFCMLEN(1U)
+
+#define A_MAC_FRAC_N_PLL_STATUS_0 0x3f034
+
+#define S_DSKEWCALLOCK    12
+#define V_DSKEWCALLOCK(x) ((x) << S_DSKEWCALLOCK)
+#define F_DSKEWCALLOCK    V_DSKEWCALLOCK(1U)
+
+#define S_DSKEWCALOUT    0
+#define M_DSKEWCALOUT    0xfffU
+#define V_DSKEWCALOUT(x) ((x) << S_DSKEWCALOUT)
+#define G_DSKEWCALOUT(x) (((x) >> S_DSKEWCALOUT) & M_DSKEWCALOUT)
+
+#define A_MAC_MTIP_PCS_STATUS_0 0x3f100
+
+#define S_XLGMII7_TX_TSU    22
+#define M_XLGMII7_TX_TSU    0x3U
+#define V_XLGMII7_TX_TSU(x) ((x) << S_XLGMII7_TX_TSU)
+#define G_XLGMII7_TX_TSU(x) (((x) >> S_XLGMII7_TX_TSU) & M_XLGMII7_TX_TSU)
+
+#define S_XLGMII6_TX_TSU    20
+#define M_XLGMII6_TX_TSU    0x3U
+#define V_XLGMII6_TX_TSU(x) ((x) << S_XLGMII6_TX_TSU)
+#define G_XLGMII6_TX_TSU(x) (((x) >> S_XLGMII6_TX_TSU) & M_XLGMII6_TX_TSU)
+
+#define S_XLGMII5_TX_TSU    18
+#define M_XLGMII5_TX_TSU    0x3U
+#define V_XLGMII5_TX_TSU(x) ((x) << S_XLGMII5_TX_TSU)
+#define G_XLGMII5_TX_TSU(x) (((x) >> S_XLGMII5_TX_TSU) & M_XLGMII5_TX_TSU)
+
+#define S_XLGMII4_TX_TSU    16
+#define M_XLGMII4_TX_TSU    0x3U
+#define V_XLGMII4_TX_TSU(x) ((x) << S_XLGMII4_TX_TSU)
+#define G_XLGMII4_TX_TSU(x) (((x) >> S_XLGMII4_TX_TSU) & M_XLGMII4_TX_TSU)
+
+#define S_XLGMII3_TX_TSU    14
+#define M_XLGMII3_TX_TSU    0x3U
+#define V_XLGMII3_TX_TSU(x) ((x) << S_XLGMII3_TX_TSU)
+#define G_XLGMII3_TX_TSU(x) (((x) >> S_XLGMII3_TX_TSU) & M_XLGMII3_TX_TSU)
+
+#define S_XLGMII2_TX_TSU    12
+#define M_XLGMII2_TX_TSU    0x3U
+#define V_XLGMII2_TX_TSU(x) ((x) << S_XLGMII2_TX_TSU)
+#define G_XLGMII2_TX_TSU(x) (((x) >> S_XLGMII2_TX_TSU) & M_XLGMII2_TX_TSU)
+
+#define S_XLGMII1_TX_TSU    10
+#define M_XLGMII1_TX_TSU    0x3U
+#define V_XLGMII1_TX_TSU(x) ((x) << S_XLGMII1_TX_TSU)
+#define G_XLGMII1_TX_TSU(x) (((x) >> S_XLGMII1_TX_TSU) & M_XLGMII1_TX_TSU)
+
+#define S_XLGMII0_TX_TSU    8
+#define M_XLGMII0_TX_TSU    0x3U
+#define V_XLGMII0_TX_TSU(x) ((x) << S_XLGMII0_TX_TSU)
+#define G_XLGMII0_TX_TSU(x) (((x) >> S_XLGMII0_TX_TSU) & M_XLGMII0_TX_TSU)
+
+#define S_CGMII3_TX_TSU    6
+#define M_CGMII3_TX_TSU    0x3U
+#define V_CGMII3_TX_TSU(x) ((x) << S_CGMII3_TX_TSU)
+#define G_CGMII3_TX_TSU(x) (((x) >> S_CGMII3_TX_TSU) & M_CGMII3_TX_TSU)
+
+#define S_CGMII2_TX_TSU    4
+#define M_CGMII2_TX_TSU    0x3U
+#define V_CGMII2_TX_TSU(x) ((x) << S_CGMII2_TX_TSU)
+#define G_CGMII2_TX_TSU(x) (((x) >> S_CGMII2_TX_TSU) & M_CGMII2_TX_TSU)
+
+#define S_CGMII1_TX_TSU    2
+#define M_CGMII1_TX_TSU    0x3U
+#define V_CGMII1_TX_TSU(x) ((x) << S_CGMII1_TX_TSU)
+#define G_CGMII1_TX_TSU(x) (((x) >> S_CGMII1_TX_TSU) & M_CGMII1_TX_TSU)
+
+#define S_CGMII0_TX_TSU    0
+#define M_CGMII0_TX_TSU    0x3U
+#define V_CGMII0_TX_TSU(x) ((x) << S_CGMII0_TX_TSU)
+#define G_CGMII0_TX_TSU(x) (((x) >> S_CGMII0_TX_TSU) & M_CGMII0_TX_TSU)
+
+#define A_MAC_MTIP_PCS_STATUS_1 0x3f104
+
+#define S_CDMII1_RX_TSU    26
+#define M_CDMII1_RX_TSU    0x3U
+#define V_CDMII1_RX_TSU(x) ((x) << S_CDMII1_RX_TSU)
+#define G_CDMII1_RX_TSU(x) (((x) >> S_CDMII1_RX_TSU) & M_CDMII1_RX_TSU)
+
+#define S_CDMII0_RX_TSU    24
+#define M_CDMII0_RX_TSU    0x3U
+#define V_CDMII0_RX_TSU(x) ((x) << S_CDMII0_RX_TSU)
+#define G_CDMII0_RX_TSU(x) (((x) >> S_CDMII0_RX_TSU) & M_CDMII0_RX_TSU)
+
+#define S_XLGMII7_RX_TSU    22
+#define M_XLGMII7_RX_TSU    0x3U
+#define V_XLGMII7_RX_TSU(x) ((x) << S_XLGMII7_RX_TSU)
+#define G_XLGMII7_RX_TSU(x) (((x) >> S_XLGMII7_RX_TSU) & M_XLGMII7_RX_TSU)
+
+#define S_XLGMII6_RX_TSU    20
+#define M_XLGMII6_RX_TSU    0x3U
+#define V_XLGMII6_RX_TSU(x) ((x) << S_XLGMII6_RX_TSU)
+#define G_XLGMII6_RX_TSU(x) (((x) >> S_XLGMII6_RX_TSU) & M_XLGMII6_RX_TSU)
+
+#define S_XLGMII5_RX_TSU    18
+#define M_XLGMII5_RX_TSU    0x3U
+#define V_XLGMII5_RX_TSU(x) ((x) << S_XLGMII5_RX_TSU)
+#define G_XLGMII5_RX_TSU(x) (((x) >> S_XLGMII5_RX_TSU) & M_XLGMII5_RX_TSU)
+
+#define S_XLGMII4_RX_TSU    16
+#define M_XLGMII4_RX_TSU    0x3U
+#define V_XLGMII4_RX_TSU(x) ((x) << S_XLGMII4_RX_TSU)
+#define G_XLGMII4_RX_TSU(x) (((x) >> S_XLGMII4_RX_TSU) & M_XLGMII4_RX_TSU)
+
+#define S_XLGMII3_RX_TSU    14
+#define M_XLGMII3_RX_TSU    0x3U
+#define V_XLGMII3_RX_TSU(x) ((x) << S_XLGMII3_RX_TSU)
+#define G_XLGMII3_RX_TSU(x) (((x) >> S_XLGMII3_RX_TSU) & M_XLGMII3_RX_TSU)
+
+#define S_XLGMII2_RX_TSU    12
+#define M_XLGMII2_RX_TSU    0x3U
+#define V_XLGMII2_RX_TSU(x) ((x) << S_XLGMII2_RX_TSU)
+#define G_XLGMII2_RX_TSU(x) (((x) >> S_XLGMII2_RX_TSU) & M_XLGMII2_RX_TSU)
+
+#define S_XLGMII1_RX_TSU    10
+#define M_XLGMII1_RX_TSU    0x3U
+#define V_XLGMII1_RX_TSU(x) ((x) << S_XLGMII1_RX_TSU)
+#define G_XLGMII1_RX_TSU(x) (((x) >> S_XLGMII1_RX_TSU) & M_XLGMII1_RX_TSU)
+
+#define S_XLGMII0_RX_TSU    8
+#define M_XLGMII0_RX_TSU    0x3U
+#define V_XLGMII0_RX_TSU(x) ((x) << S_XLGMII0_RX_TSU)
+#define G_XLGMII0_RX_TSU(x) (((x) >> S_XLGMII0_RX_TSU) & M_XLGMII0_RX_TSU)
+
+#define S_CGMII3_RX_TSU    6
+#define M_CGMII3_RX_TSU    0x3U
+#define V_CGMII3_RX_TSU(x) ((x) << S_CGMII3_RX_TSU)
+#define G_CGMII3_RX_TSU(x) (((x) >> S_CGMII3_RX_TSU) & M_CGMII3_RX_TSU)
+
+#define S_CGMII2_RX_TSU    4
+#define M_CGMII2_RX_TSU    0x3U
+#define V_CGMII2_RX_TSU(x) ((x) << S_CGMII2_RX_TSU)
+#define G_CGMII2_RX_TSU(x) (((x) >> S_CGMII2_RX_TSU) & M_CGMII2_RX_TSU)
+
+#define S_CGMII1_RX_TSU    2
+#define M_CGMII1_RX_TSU    0x3U
+#define V_CGMII1_RX_TSU(x) ((x) << S_CGMII1_RX_TSU)
+#define G_CGMII1_RX_TSU(x) (((x) >> S_CGMII1_RX_TSU) & M_CGMII1_RX_TSU)
+
+#define S_CGMII0_RX_TSU    0
+#define M_CGMII0_RX_TSU    0x3U
+#define V_CGMII0_RX_TSU(x) ((x) << S_CGMII0_RX_TSU)
+#define G_CGMII0_RX_TSU(x) (((x) >> S_CGMII0_RX_TSU) & M_CGMII0_RX_TSU)
+
+#define A_MAC_MTIP_PCS_STATUS_2 0x3f108
+
+#define S_SD_BIT_SLIP_0    0
+#define M_SD_BIT_SLIP_0    0x3fffffffU
+#define V_SD_BIT_SLIP_0(x) ((x) << S_SD_BIT_SLIP_0)
+#define G_SD_BIT_SLIP_0(x) (((x) >> S_SD_BIT_SLIP_0) & M_SD_BIT_SLIP_0)
+
+#define A_MAC_MTIP_PCS_STATUS_3 0x3f10c
+
+#define S_SD_BIT_SLIP_1    0
+#define M_SD_BIT_SLIP_1    0x3ffffU
+#define V_SD_BIT_SLIP_1(x) ((x) << S_SD_BIT_SLIP_1)
+#define G_SD_BIT_SLIP_1(x) (((x) >> S_SD_BIT_SLIP_1) & M_SD_BIT_SLIP_1)
+
+#define A_MAC_MTIP_PCS_STATUS_4 0x3f110
+
+#define S_TSU_RX_SD    0
+#define M_TSU_RX_SD    0xffffU
+#define V_TSU_RX_SD(x) ((x) << S_TSU_RX_SD)
+#define G_TSU_RX_SD(x) (((x) >> S_TSU_RX_SD) & M_TSU_RX_SD)
+
+#define A_MAC_MTIP_PCS_STATUS_5 0x3f114
+
+#define S_RSFEC_XSTATS_STRB    0
+#define M_RSFEC_XSTATS_STRB    0xffffffU
+#define V_RSFEC_XSTATS_STRB(x) ((x) << S_RSFEC_XSTATS_STRB)
+#define G_RSFEC_XSTATS_STRB(x) (((x) >> S_RSFEC_XSTATS_STRB) & M_RSFEC_XSTATS_STRB)
+
+#define A_MAC_MTIP_PCS_STATUS_6 0x3f118
+#define A_MAC_MTIP_PCS_STATUS_7 0x3f11c
+#define A_MAC_MTIP_MAC_10G_100G_STATUS_0 0x3f120
+
+#define S_TSV_XON_STB_2    24
+#define M_TSV_XON_STB_2    0xffU
+#define V_TSV_XON_STB_2(x) ((x) << S_TSV_XON_STB_2)
+#define G_TSV_XON_STB_2(x) (((x) >> S_TSV_XON_STB_2) & M_TSV_XON_STB_2)
+
+#define S_TSV_XOFF_STB_2    16
+#define M_TSV_XOFF_STB_2    0xffU
+#define V_TSV_XOFF_STB_2(x) ((x) << S_TSV_XOFF_STB_2)
+#define G_TSV_XOFF_STB_2(x) (((x) >> S_TSV_XOFF_STB_2) & M_TSV_XOFF_STB_2)
+
+#define S_RSV_XON_STB_2    8
+#define M_RSV_XON_STB_2    0xffU
+#define V_RSV_XON_STB_2(x) ((x) << S_RSV_XON_STB_2)
+#define G_RSV_XON_STB_2(x) (((x) >> S_RSV_XON_STB_2) & M_RSV_XON_STB_2)
+
+#define S_RSV_XOFF_STB_2    0
+#define M_RSV_XOFF_STB_2    0xffU
+#define V_RSV_XOFF_STB_2(x) ((x) << S_RSV_XOFF_STB_2)
+#define G_RSV_XOFF_STB_2(x) (((x) >> S_RSV_XOFF_STB_2) & M_RSV_XOFF_STB_2)
+
+#define A_MAC_MTIP_MAC_10G_100G_STATUS_1 0x3f124
+
+#define S_TSV_XON_STB_3    24
+#define M_TSV_XON_STB_3    0xffU
+#define V_TSV_XON_STB_3(x) ((x) << S_TSV_XON_STB_3)
+#define G_TSV_XON_STB_3(x) (((x) >> S_TSV_XON_STB_3) & M_TSV_XON_STB_3)
+
+#define S_TSV_XOFF_STB_3    16
+#define M_TSV_XOFF_STB_3    0xffU
+#define V_TSV_XOFF_STB_3(x) ((x) << S_TSV_XOFF_STB_3)
+#define G_TSV_XOFF_STB_3(x) (((x) >> S_TSV_XOFF_STB_3) & M_TSV_XOFF_STB_3)
+
+#define S_RSV_XON_STB_3    8
+#define M_RSV_XON_STB_3    0xffU
+#define V_RSV_XON_STB_3(x) ((x) << S_RSV_XON_STB_3)
+#define G_RSV_XON_STB_3(x) (((x) >> S_RSV_XON_STB_3) & M_RSV_XON_STB_3)
+
+#define S_RSV_XOFF_STB_3    0
+#define M_RSV_XOFF_STB_3    0xffU
+#define V_RSV_XOFF_STB_3(x) ((x) << S_RSV_XOFF_STB_3)
+#define G_RSV_XOFF_STB_3(x) (((x) >> S_RSV_XOFF_STB_3) & M_RSV_XOFF_STB_3)
+
+#define A_MAC_MTIP_MAC_10G_100G_STATUS_2 0x3f128
+
+#define S_TSV_XON_STB_4    24
+#define M_TSV_XON_STB_4    0xffU
+#define V_TSV_XON_STB_4(x) ((x) << S_TSV_XON_STB_4)
+#define G_TSV_XON_STB_4(x) (((x) >> S_TSV_XON_STB_4) & M_TSV_XON_STB_4)
+
+#define S_TSV_XOFF_STB_4    16
+#define M_TSV_XOFF_STB_4    0xffU
+#define V_TSV_XOFF_STB_4(x) ((x) << S_TSV_XOFF_STB_4)
+#define G_TSV_XOFF_STB_4(x) (((x) >> S_TSV_XOFF_STB_4) & M_TSV_XOFF_STB_4)
+
+#define S_RSV_XON_STB_4    8
+#define M_RSV_XON_STB_4    0xffU
+#define V_RSV_XON_STB_4(x) ((x) << S_RSV_XON_STB_4)
+#define G_RSV_XON_STB_4(x) (((x) >> S_RSV_XON_STB_4) & M_RSV_XON_STB_4)
+
+#define S_RSV_XOFF_STB_4    0
+#define M_RSV_XOFF_STB_4    0xffU
+#define V_RSV_XOFF_STB_4(x) ((x) << S_RSV_XOFF_STB_4)
+#define G_RSV_XOFF_STB_4(x) (((x) >> S_RSV_XOFF_STB_4) & M_RSV_XOFF_STB_4)
+
+#define A_MAC_MTIP_MAC_10G_100G_STATUS_3 0x3f12c
+
+#define S_TSV_XON_STB_5    24
+#define M_TSV_XON_STB_5    0xffU
+#define V_TSV_XON_STB_5(x) ((x) << S_TSV_XON_STB_5)
+#define G_TSV_XON_STB_5(x) (((x) >> S_TSV_XON_STB_5) & M_TSV_XON_STB_5)
+
+#define S_TSV_XOFF_STB_5    16
+#define M_TSV_XOFF_STB_5    0xffU
+#define V_TSV_XOFF_STB_5(x) ((x) << S_TSV_XOFF_STB_5)
+#define G_TSV_XOFF_STB_5(x) (((x) >> S_TSV_XOFF_STB_5) & M_TSV_XOFF_STB_5)
+
+#define S_RSV_XON_STB_5    8
+#define M_RSV_XON_STB_5    0xffU
+#define V_RSV_XON_STB_5(x) ((x) << S_RSV_XON_STB_5)
+#define G_RSV_XON_STB_5(x) (((x) >> S_RSV_XON_STB_5) & M_RSV_XON_STB_5)
+
+#define S_RSV_XOFF_STB_5    0
+#define M_RSV_XOFF_STB_5    0xffU
+#define V_RSV_XOFF_STB_5(x) ((x) << S_RSV_XOFF_STB_5)
+#define G_RSV_XOFF_STB_5(x) (((x) >> S_RSV_XOFF_STB_5) & M_RSV_XOFF_STB_5)
+
+#define A_MAC_MTIP_MAC_10G_100G_STATUS_4 0x3f130
+
+#define S_TX_SFD_O_5    19
+#define V_TX_SFD_O_5(x) ((x) << S_TX_SFD_O_5)
+#define F_TX_SFD_O_5    V_TX_SFD_O_5(1U)
+
+#define S_TX_SFD_O_4    18
+#define V_TX_SFD_O_4(x) ((x) << S_TX_SFD_O_4)
+#define F_TX_SFD_O_4    V_TX_SFD_O_4(1U)
+
+#define S_TX_SFD_O_3    17
+#define V_TX_SFD_O_3(x) ((x) << S_TX_SFD_O_3)
+#define F_TX_SFD_O_3    V_TX_SFD_O_3(1U)
+
+#define S_TX_SFD_O_2    16
+#define V_TX_SFD_O_2(x) ((x) << S_TX_SFD_O_2)
+#define F_TX_SFD_O_2    V_TX_SFD_O_2(1U)
+
+#define S_RX_SFD_O_5    15
+#define V_RX_SFD_O_5(x) ((x) << S_RX_SFD_O_5)
+#define F_RX_SFD_O_5    V_RX_SFD_O_5(1U)
+
+#define S_RX_SFD_O_4    14
+#define V_RX_SFD_O_4(x) ((x) << S_RX_SFD_O_4)
+#define F_RX_SFD_O_4    V_RX_SFD_O_4(1U)
+
+#define S_RX_SFD_O_3    13
+#define V_RX_SFD_O_3(x) ((x) << S_RX_SFD_O_3)
+#define F_RX_SFD_O_3    V_RX_SFD_O_3(1U)
+
+#define S_RX_SFD_O_2    12
+#define V_RX_SFD_O_2(x) ((x) << S_RX_SFD_O_2)
+#define F_RX_SFD_O_2    V_RX_SFD_O_2(1U)
+
+#define S_RX_SFD_SHIFT_O_5    11
+#define V_RX_SFD_SHIFT_O_5(x) ((x) << S_RX_SFD_SHIFT_O_5)
+#define F_RX_SFD_SHIFT_O_5    V_RX_SFD_SHIFT_O_5(1U)
+
+#define S_RX_SFD_SHIFT_O_4    10
+#define V_RX_SFD_SHIFT_O_4(x) ((x) << S_RX_SFD_SHIFT_O_4)
+#define F_RX_SFD_SHIFT_O_4    V_RX_SFD_SHIFT_O_4(1U)
+
+#define S_RX_SFD_SHIFT_O_3    9
+#define V_RX_SFD_SHIFT_O_3(x) ((x) << S_RX_SFD_SHIFT_O_3)
+#define F_RX_SFD_SHIFT_O_3    V_RX_SFD_SHIFT_O_3(1U)
+
+#define S_RX_SFD_SHIFT_O_2    8
+#define V_RX_SFD_SHIFT_O_2(x) ((x) << S_RX_SFD_SHIFT_O_2)
+#define F_RX_SFD_SHIFT_O_2    V_RX_SFD_SHIFT_O_2(1U)
+
+#define S_TX_SFD_SHIFT_O_5    7
+#define V_TX_SFD_SHIFT_O_5(x) ((x) << S_TX_SFD_SHIFT_O_5)
+#define F_TX_SFD_SHIFT_O_5    V_TX_SFD_SHIFT_O_5(1U)
+
+#define S_TX_SFD_SHIFT_O_4    6
+#define V_TX_SFD_SHIFT_O_4(x) ((x) << S_TX_SFD_SHIFT_O_4)
+#define F_TX_SFD_SHIFT_O_4    V_TX_SFD_SHIFT_O_4(1U)
+
+#define S_TX_SFD_SHIFT_O_3    5
+#define V_TX_SFD_SHIFT_O_3(x) ((x) << S_TX_SFD_SHIFT_O_3)
+#define F_TX_SFD_SHIFT_O_3    V_TX_SFD_SHIFT_O_3(1U)
+
+#define S_TX_SFD_SHIFT_O_2    4
+#define V_TX_SFD_SHIFT_O_2(x) ((x) << S_TX_SFD_SHIFT_O_2)
+#define F_TX_SFD_SHIFT_O_2    V_TX_SFD_SHIFT_O_2(1U)
+
+#define S_TS_SFD_ENA_5    3
+#define V_TS_SFD_ENA_5(x) ((x) << S_TS_SFD_ENA_5)
+#define F_TS_SFD_ENA_5    V_TS_SFD_ENA_5(1U)
+
+#define S_TS_SFD_ENA_4    2
+#define V_TS_SFD_ENA_4(x) ((x) << S_TS_SFD_ENA_4)
+#define F_TS_SFD_ENA_4    V_TS_SFD_ENA_4(1U)
+
+#define S_TS_SFD_ENA_3    1
+#define V_TS_SFD_ENA_3(x) ((x) << S_TS_SFD_ENA_3)
+#define F_TS_SFD_ENA_3    V_TS_SFD_ENA_3(1U)
+
+#define S_TS_SFD_ENA_2    0
+#define V_TS_SFD_ENA_2(x) ((x) << S_TS_SFD_ENA_2)
+#define F_TS_SFD_ENA_2    V_TS_SFD_ENA_2(1U)
+
+#define A_MAC_STS_CONFIG 0x3f200
+
+#define S_STS_ENA    30
+#define V_STS_ENA(x) ((x) << S_STS_ENA)
+#define F_STS_ENA    V_STS_ENA(1U)
+
+#define S_N_PPS_ENA    29
+#define V_N_PPS_ENA(x) ((x) << S_N_PPS_ENA)
+#define F_N_PPS_ENA    V_N_PPS_ENA(1U)
+
+#define S_STS_RESET    28
+#define V_STS_RESET(x) ((x) << S_STS_RESET)
+#define F_STS_RESET    V_STS_RESET(1U)
+
+#define S_DEBOUNCE_CNT    0
+#define M_DEBOUNCE_CNT    0xfffffffU
+#define V_DEBOUNCE_CNT(x) ((x) << S_DEBOUNCE_CNT)
+#define G_DEBOUNCE_CNT(x) (((x) >> S_DEBOUNCE_CNT) & M_DEBOUNCE_CNT)
+
+#define A_MAC_STS_COUNTER 0x3f204
+#define A_MAC_STS_COUNT_1 0x3f208
+#define A_MAC_STS_COUNT_2 0x3f20c
+#define A_MAC_STS_N_PPS_COUNT_HI 0x3f210
+#define A_MAC_STS_N_PPS_COUNT_LO 0x3f214
+#define A_MAC_STS_N_PPS_COUNTER 0x3f218
+#define A_MAC_BGR_PQ0_FIRMWARE_COMMON_0 0x4030
+
+#define S_MAC_BGR_BGR_REG_APB_SEL    0
+#define V_MAC_BGR_BGR_REG_APB_SEL(x) ((x) << S_MAC_BGR_BGR_REG_APB_SEL)
+#define F_MAC_BGR_BGR_REG_APB_SEL    V_MAC_BGR_BGR_REG_APB_SEL(1U)
+
+#define A_MAC_BGR_TOP_DIG_CTRL1_REG_LSB 0x4430
+
+#define S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS    15
+#define V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(x) ((x) << S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS)
+#define F_MAC_BGR_BGR_REFCLK_CTRL_BYPASS    V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(1U)
+
+#define S_MAC_BGR_BGR_COREREFCLK_SEL    14
+#define V_MAC_BGR_BGR_COREREFCLK_SEL(x) ((x) << S_MAC_BGR_BGR_COREREFCLK_SEL)
+#define F_MAC_BGR_BGR_COREREFCLK_SEL    V_MAC_BGR_BGR_COREREFCLK_SEL(1U)
+
+#define S_MAC_BGR_BGR_TEST_CLK_DIV    8
+#define M_MAC_BGR_BGR_TEST_CLK_DIV    0x7U
+#define V_MAC_BGR_BGR_TEST_CLK_DIV(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_DIV)
+#define G_MAC_BGR_BGR_TEST_CLK_DIV(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_DIV) & M_MAC_BGR_BGR_TEST_CLK_DIV)
+
+#define S_MAC_BGR_BGR_TEST_CLK_EN    7
+#define V_MAC_BGR_BGR_TEST_CLK_EN(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_EN)
+#define F_MAC_BGR_BGR_TEST_CLK_EN    V_MAC_BGR_BGR_TEST_CLK_EN(1U)
+
+#define S_MAC_BGR_BGR_TEST_CLK_BGRSEL    5
+#define M_MAC_BGR_BGR_TEST_CLK_BGRSEL    0x3U
+#define V_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_BGRSEL)
+#define G_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_BGRSEL) & M_MAC_BGR_BGR_TEST_CLK_BGRSEL)
+
+#define S_MAC_BGR_BGR_TEST_CLK_SEL    0
+#define M_MAC_BGR_BGR_TEST_CLK_SEL    0x1fU
+#define V_MAC_BGR_BGR_TEST_CLK_SEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_SEL)
+#define G_MAC_BGR_BGR_TEST_CLK_SEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_SEL) & M_MAC_BGR_BGR_TEST_CLK_SEL)
+
+#define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_0 0x6000
+
+#define S_MAC_BGR_BGR_REG_PRG_EN    0
+#define V_MAC_BGR_BGR_REG_PRG_EN(x) ((x) << S_MAC_BGR_BGR_REG_PRG_EN)
+#define F_MAC_BGR_BGR_REG_PRG_EN    V_MAC_BGR_BGR_REG_PRG_EN(1U)
+
+#define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_1 0x6020
+
+#define S_MAC_BGR_BGR_REG_GPO    0
+#define V_MAC_BGR_BGR_REG_GPO(x) ((x) << S_MAC_BGR_BGR_REG_GPO)
+#define F_MAC_BGR_BGR_REG_GPO    V_MAC_BGR_BGR_REG_GPO(1U)
+
+#define A_MAC_BGR_MGMT_SPINE_MACRO_PMA_0 0x40000
+
+#define S_MAC_BGR_CUREFCLKSEL1    0
+#define M_MAC_BGR_CUREFCLKSEL1    0x3U
+#define V_MAC_BGR_CUREFCLKSEL1(x) ((x) << S_MAC_BGR_CUREFCLKSEL1)
+#define G_MAC_BGR_CUREFCLKSEL1(x) (((x) >> S_MAC_BGR_CUREFCLKSEL1) & M_MAC_BGR_CUREFCLKSEL1)
+
+#define A_MAC_BGR_REFCLK_CONTROL_1 0x40004
+
+#define S_MAC_BGR_IM_CUREFCLKLR_EN    0
+#define V_MAC_BGR_IM_CUREFCLKLR_EN(x) ((x) << S_MAC_BGR_IM_CUREFCLKLR_EN)
+#define F_MAC_BGR_IM_CUREFCLKLR_EN    V_MAC_BGR_IM_CUREFCLKLR_EN(1U)
+
+#define A_MAC_BGR_REFCLK_CONTROL_2 0x40080
+
+#define S_MAC_BGR_IM_REF_EN    0
+#define V_MAC_BGR_IM_REF_EN(x) ((x) << S_MAC_BGR_IM_REF_EN)
+#define F_MAC_BGR_IM_REF_EN    V_MAC_BGR_IM_REF_EN(1U)
+
+#define A_MAC_PLL0_PLL_TOP_CUPLL_LOCK 0x4438
+
+#define S_MAC_PLL0_PLL2_LOCK_STATUS    2
+#define V_MAC_PLL0_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL2_LOCK_STATUS)
+#define F_MAC_PLL0_PLL2_LOCK_STATUS    V_MAC_PLL0_PLL2_LOCK_STATUS(1U)
+
+#define S_MAC_PLL0_PLL1_LOCK_STATUS    1
+#define V_MAC_PLL0_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL1_LOCK_STATUS)
+#define F_MAC_PLL0_PLL1_LOCK_STATUS    V_MAC_PLL0_PLL1_LOCK_STATUS(1U)
+
+#define S_MAC_PLL0_PLL0_LOCK_STATUS    0
+#define V_MAC_PLL0_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL0_LOCK_STATUS)
+#define F_MAC_PLL0_PLL0_LOCK_STATUS    V_MAC_PLL0_PLL0_LOCK_STATUS(1U)
+
+#define A_MAC_PLL0_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020
+
+#define S_MAC_PLL0_PLL_PRG_EN    0
+#define M_MAC_PLL0_PLL_PRG_EN    0xfU
+#define V_MAC_PLL0_PLL_PRG_EN(x) ((x) << S_MAC_PLL0_PLL_PRG_EN)
+#define G_MAC_PLL0_PLL_PRG_EN(x) (((x) >> S_MAC_PLL0_PLL_PRG_EN) & M_MAC_PLL0_PLL_PRG_EN)
+
+#define A_MAC_PLL0_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00
+
+#define S_MAC_PLL0_PMA_MACRO_SELECT    0
+#define M_MAC_PLL0_PMA_MACRO_SELECT    0x3ffU
+#define V_MAC_PLL0_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL0_PMA_MACRO_SELECT)
+#define G_MAC_PLL0_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL0_PMA_MACRO_SELECT) & M_MAC_PLL0_PMA_MACRO_SELECT)
+
+#define A_MAC_PLL1_PLL_TOP_CUPLL_LOCK 0x4438
+
+#define S_MAC_PLL1_PLL2_LOCK_STATUS    2
+#define V_MAC_PLL1_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL2_LOCK_STATUS)
+#define F_MAC_PLL1_PLL2_LOCK_STATUS    V_MAC_PLL1_PLL2_LOCK_STATUS(1U)
+
+#define S_MAC_PLL1_PLL1_LOCK_STATUS    1
+#define V_MAC_PLL1_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL1_LOCK_STATUS)
+#define F_MAC_PLL1_PLL1_LOCK_STATUS    V_MAC_PLL1_PLL1_LOCK_STATUS(1U)
+
+#define S_MAC_PLL1_PLL0_LOCK_STATUS    0
+#define V_MAC_PLL1_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL0_LOCK_STATUS)
+#define F_MAC_PLL1_PLL0_LOCK_STATUS    V_MAC_PLL1_PLL0_LOCK_STATUS(1U)
+
+#define A_MAC_PLL1_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020
+
+#define S_MAC_PLL1_PLL_PRG_EN    0
+#define M_MAC_PLL1_PLL_PRG_EN    0xfU
+#define V_MAC_PLL1_PLL_PRG_EN(x) ((x) << S_MAC_PLL1_PLL_PRG_EN)
+#define G_MAC_PLL1_PLL_PRG_EN(x) (((x) >> S_MAC_PLL1_PLL_PRG_EN) & M_MAC_PLL1_PLL_PRG_EN)
+
+#define A_MAC_PLL1_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00
+
+#define S_MAC_PLL1_PMA_MACRO_SELECT    0
+#define M_MAC_PLL1_PMA_MACRO_SELECT    0x3ffU
+#define V_MAC_PLL1_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL1_PMA_MACRO_SELECT)
+#define G_MAC_PLL1_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL1_PMA_MACRO_SELECT) & M_MAC_PLL1_PMA_MACRO_SELECT)
+
+/* registers for module CRYPTO_0 */
+#define CRYPTO_0_BASE_ADDR 0x44000
+
+#define A_TLS_TX_CH_CONFIG 0x44000
+
+#define S_SMALL_LEN_THRESH    16
+#define M_SMALL_LEN_THRESH    0xffffU
+#define V_SMALL_LEN_THRESH(x) ((x) << S_SMALL_LEN_THRESH)
+#define G_SMALL_LEN_THRESH(x) (((x) >> S_SMALL_LEN_THRESH) & M_SMALL_LEN_THRESH)
+
+#define S_CIPH0_CTL_SEL    12
+#define M_CIPH0_CTL_SEL    0x7U
+#define V_CIPH0_CTL_SEL(x) ((x) << S_CIPH0_CTL_SEL)
+#define G_CIPH0_CTL_SEL(x) (((x) >> S_CIPH0_CTL_SEL) & M_CIPH0_CTL_SEL)
+
+#define S_CIPHN_CTL_SEL    9
+#define M_CIPHN_CTL_SEL    0x7U
+#define V_CIPHN_CTL_SEL(x) ((x) << S_CIPHN_CTL_SEL)
+#define G_CIPHN_CTL_SEL(x) (((x) >> S_CIPHN_CTL_SEL) & M_CIPHN_CTL_SEL)
+
+#define S_MAC_CTL_SEL    6
+#define M_MAC_CTL_SEL    0x7U
+#define V_MAC_CTL_SEL(x) ((x) << S_MAC_CTL_SEL)
+#define G_MAC_CTL_SEL(x) (((x) >> S_MAC_CTL_SEL) & M_MAC_CTL_SEL)
+
+#define S_CIPH0_XOR_SEL    5
+#define V_CIPH0_XOR_SEL(x) ((x) << S_CIPH0_XOR_SEL)
+#define F_CIPH0_XOR_SEL    V_CIPH0_XOR_SEL(1U)
+
+#define S_CIPHN_XOR_SEL    4
+#define V_CIPHN_XOR_SEL(x) ((x) << S_CIPHN_XOR_SEL)
+#define F_CIPHN_XOR_SEL    V_CIPHN_XOR_SEL(1U)
+
+#define S_MAC_XOR_SEL    3
+#define V_MAC_XOR_SEL(x) ((x) << S_MAC_XOR_SEL)
+#define F_MAC_XOR_SEL    V_MAC_XOR_SEL(1U)
+
+#define S_CIPH0_DP_SEL    2
+#define V_CIPH0_DP_SEL(x) ((x) << S_CIPH0_DP_SEL)
+#define F_CIPH0_DP_SEL    V_CIPH0_DP_SEL(1U)
+
+#define S_CIPHN_DP_SEL    1
+#define V_CIPHN_DP_SEL(x) ((x) << S_CIPHN_DP_SEL)
+#define F_CIPHN_DP_SEL    V_CIPHN_DP_SEL(1U)
+
+#define S_MAC_DP_SEL    0
+#define V_MAC_DP_SEL(x) ((x) << S_MAC_DP_SEL)
+#define F_MAC_DP_SEL    V_MAC_DP_SEL(1U)
+
+#define A_TLS_TX_CH_PERR_INJECT 0x44004
+#define A_TLS_TX_CH_INT_ENABLE 0x44008
+
+#define S_KEYLENERR    3
+#define V_KEYLENERR(x) ((x) << S_KEYLENERR)
+#define F_KEYLENERR    V_KEYLENERR(1U)
+
+#define S_INTF1_PERR    2
+#define V_INTF1_PERR(x) ((x) << S_INTF1_PERR)
+#define F_INTF1_PERR    V_INTF1_PERR(1U)
+
+#define S_INTF0_PERR    1
+#define V_INTF0_PERR(x) ((x) << S_INTF0_PERR)
+#define F_INTF0_PERR    V_INTF0_PERR(1U)
+
+#define A_TLS_TX_CH_INT_CAUSE 0x4400c
+
+#define S_KEX_CERR    4
+#define V_KEX_CERR(x) ((x) << S_KEX_CERR)
+#define F_KEX_CERR    V_KEX_CERR(1U)
+
+#define A_TLS_TX_CH_PERR_ENABLE 0x44010
+#define A_TLS_TX_CH_DEBUG_FLAGS 0x44014
+#define A_TLS_TX_CH_HMACCTRL_CFG 0x44020
+#define A_TLS_TX_CH_ERR_RSP_HDR 0x44024
+#define A_TLS_TX_CH_HANG_TIMEOUT 0x44028
+
+#define S_T7_TIMEOUT    0
+#define M_T7_TIMEOUT    0xffU
+#define V_T7_TIMEOUT(x) ((x) << S_T7_TIMEOUT)
+#define G_T7_TIMEOUT(x) (((x) >> S_T7_TIMEOUT) & M_T7_TIMEOUT)
+
+#define A_TLS_TX_CH_DBG_STEP_CTRL 0x44030
+
+#define S_DBG_STEP_CTRL    1
+#define V_DBG_STEP_CTRL(x) ((x) << S_DBG_STEP_CTRL)
+#define F_DBG_STEP_CTRL    V_DBG_STEP_CTRL(1U)
+
+#define S_DBG_STEP_EN    0
+#define V_DBG_STEP_EN(x) ((x) << S_DBG_STEP_EN)
+#define F_DBG_STEP_EN    V_DBG_STEP_EN(1U)
+
+#define A_TLS_TX_DBG_SELL_DATA 0x44714
+#define A_TLS_TX_DBG_SELH_DATA 0x44718
+#define A_TLS_TX_DBG_SEL_CTRL 0x44730
+#define A_TLS_TX_GLOBAL_CONFIG 0x447c0
+
+#define S_QUIC_EN    2
+#define V_QUIC_EN(x) ((x) << S_QUIC_EN)
+#define F_QUIC_EN    V_QUIC_EN(1U)
+
+#define S_IPSEC_IDX_UPD_EN    1
+#define V_IPSEC_IDX_UPD_EN(x) ((x) << S_IPSEC_IDX_UPD_EN)
+#define F_IPSEC_IDX_UPD_EN    V_IPSEC_IDX_UPD_EN(1U)
+
+#define S_IPSEC_IDX_CTL    0
+#define V_IPSEC_IDX_CTL(x) ((x) << S_IPSEC_IDX_CTL)
+#define F_IPSEC_IDX_CTL    V_IPSEC_IDX_CTL(1U)
+
+#define A_TLS_TX_CGEN 0x447f0
+
+#define S_CHCGEN    0
+#define M_CHCGEN    0x3fU
+#define V_CHCGEN(x) ((x) << S_CHCGEN)
+#define G_CHCGEN(x) (((x) >> S_CHCGEN) & M_CHCGEN)
+
+#define A_TLS_TX_IND_ADDR 0x447f8
+
+#define S_T7_3_ADDR    0
+#define M_T7_3_ADDR    0xfffU
+#define V_T7_3_ADDR(x) ((x) << S_T7_3_ADDR)
+#define G_T7_3_ADDR(x) (((x) >> S_T7_3_ADDR) & M_T7_3_ADDR)
+
+#define A_TLS_TX_IND_DATA 0x447fc
+#define A_TLS_TX_CH_IND_ING_BYTE_CNT_LO 0x0
+#define A_TLS_TX_CH_IND_ING_BYTE_CNT_HI 0x1
+#define A_TLS_TX_CH_IND_ING_PKT_CNT 0x2
+#define A_TLS_TX_CH_IND_DISPATCH_PKT_CNT 0x4
+#define A_TLS_TX_CH_IND_ERROR_CNTS0 0x5
+#define A_TLS_TX_CH_IND_DEC_ERROR_CNTS 0x7
+#define A_TLS_TX_CH_IND_DBG_SPP_CFG 0x1f
+
+#define S_DIS_IF_ERR    11
+#define V_DIS_IF_ERR(x) ((x) << S_DIS_IF_ERR)
+#define F_DIS_IF_ERR    V_DIS_IF_ERR(1U)
+
+#define S_DIS_ERR_MSG    10
+#define V_DIS_ERR_MSG(x) ((x) << S_DIS_ERR_MSG)
+#define F_DIS_ERR_MSG    V_DIS_ERR_MSG(1U)
+
+#define S_DIS_BP_SEQF    9
+#define V_DIS_BP_SEQF(x) ((x) << S_DIS_BP_SEQF)
+#define F_DIS_BP_SEQF    V_DIS_BP_SEQF(1U)
+
+#define S_DIS_BP_LENF    8
+#define V_DIS_BP_LENF(x) ((x) << S_DIS_BP_LENF)
+#define F_DIS_BP_LENF    V_DIS_BP_LENF(1U)
+
+#define S_DIS_KEX_ERR    6
+#define V_DIS_KEX_ERR(x) ((x) << S_DIS_KEX_ERR)
+#define F_DIS_KEX_ERR    V_DIS_KEX_ERR(1U)
+
+#define S_CLR_STS    5
+#define V_CLR_STS(x) ((x) << S_CLR_STS)
+#define F_CLR_STS    V_CLR_STS(1U)
+
+#define S_TGL_CNT    4
+#define V_TGL_CNT(x) ((x) << S_TGL_CNT)
+#define F_TGL_CNT    V_TGL_CNT(1U)
+
+#define S_ENB_PAZ    3
+#define V_ENB_PAZ(x) ((x) << S_ENB_PAZ)
+#define F_ENB_PAZ    V_ENB_PAZ(1U)
+
+#define S_DIS_NOP    2
+#define V_DIS_NOP(x) ((x) << S_DIS_NOP)
+#define F_DIS_NOP    V_DIS_NOP(1U)
+
+#define S_DIS_CPL_ERR    1
+#define V_DIS_CPL_ERR(x) ((x) << S_DIS_CPL_ERR)
+#define F_DIS_CPL_ERR    V_DIS_CPL_ERR(1U)
+
+#define S_DIS_OFF_ERR    0
+#define V_DIS_OFF_ERR(x) ((x) << S_DIS_OFF_ERR)
+#define F_DIS_OFF_ERR    V_DIS_OFF_ERR(1U)
+
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID0 0x20
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID1 0x21
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID2 0x22
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID3 0x23
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID4 0x24
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID5 0x25
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID6 0x26
+#define A_TLS_TX_CH_IND_DBG_SPP_PKTID7 0x27
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W0 0x28
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W1 0x29
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W2 0x2a
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W3 0x2b
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W0 0x2c
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W1 0x2d
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W2 0x2e
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W3 0x2f
+#define A_TLS_TX_CH_IND_DBG_SPP_SPR_ERR 0x30
+#define A_TLS_TX_CH_IND_DBG_SPP_SFO_BP 0x31
+#define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_M 0x32
+#define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_L 0x33
+#define A_TLS_TX_CH_IND_DBG_PKT_STAT 0x3f
+
+/* registers for module CRYPTO_1 */
+#define CRYPTO_1_BASE_ADDR 0x45000
+
+/* registers for module CRYPTO_KEY */
+#define CRYPTO_KEY_BASE_ADDR 0x46000
+
+#define A_CRYPTO_KEY_CONFIG 0x46000
+
+#define S_ESNWIN    1
+#define M_ESNWIN    0x7U
+#define V_ESNWIN(x) ((x) << S_ESNWIN)
+#define G_ESNWIN(x) (((x) >> S_ESNWIN) & M_ESNWIN)
+
+#define S_INGKEY96    0
+#define V_INGKEY96(x) ((x) << S_INGKEY96)
+#define F_INGKEY96    V_INGKEY96(1U)
+
+#define A_CRYPTO_KEY_RST 0x46004
+
+#define S_CORE1RST    1
+#define V_CORE1RST(x) ((x) << S_CORE1RST)
+#define F_CORE1RST    V_CORE1RST(1U)
+
+#define S_CORE0RST    0
+#define V_CORE0RST(x) ((x) << S_CORE0RST)
+#define F_CORE0RST    V_CORE0RST(1U)
+
+#define A_CRYPTO_KEY_INT_ENABLE 0x46008
+
+#define S_MA_FIFO_PERR    22
+#define V_MA_FIFO_PERR(x) ((x) << S_MA_FIFO_PERR)
+#define F_MA_FIFO_PERR    V_MA_FIFO_PERR(1U)
+
+#define S_MA_RSP_PERR    21
+#define V_MA_RSP_PERR(x) ((x) << S_MA_RSP_PERR)
+#define F_MA_RSP_PERR    V_MA_RSP_PERR(1U)
+
+#define S_ING_CACHE_DATA_PERR    19
+#define V_ING_CACHE_DATA_PERR(x) ((x) << S_ING_CACHE_DATA_PERR)
+#define F_ING_CACHE_DATA_PERR    V_ING_CACHE_DATA_PERR(1U)
+
+#define S_ING_CACHE_TAG_PERR    18
+#define V_ING_CACHE_TAG_PERR(x) ((x) << S_ING_CACHE_TAG_PERR)
+#define F_ING_CACHE_TAG_PERR    V_ING_CACHE_TAG_PERR(1U)
+
+#define S_LKP_KEY_REQ_PERR    17
+#define V_LKP_KEY_REQ_PERR(x) ((x) << S_LKP_KEY_REQ_PERR)
+#define F_LKP_KEY_REQ_PERR    V_LKP_KEY_REQ_PERR(1U)
+
+#define S_LKP_CLIP_TCAM_PERR    16
+#define V_LKP_CLIP_TCAM_PERR(x) ((x) << S_LKP_CLIP_TCAM_PERR)
+#define F_LKP_CLIP_TCAM_PERR    V_LKP_CLIP_TCAM_PERR(1U)
+
+#define S_LKP_MAIN_TCAM_PERR    15
+#define V_LKP_MAIN_TCAM_PERR(x) ((x) << S_LKP_MAIN_TCAM_PERR)
+#define F_LKP_MAIN_TCAM_PERR    V_LKP_MAIN_TCAM_PERR(1U)
+
+#define S_EGR_KEY_REQ_PERR    14
+#define V_EGR_KEY_REQ_PERR(x) ((x) << S_EGR_KEY_REQ_PERR)
+#define F_EGR_KEY_REQ_PERR    V_EGR_KEY_REQ_PERR(1U)
+
+#define S_EGR_CACHE_DATA_PERR    13
+#define V_EGR_CACHE_DATA_PERR(x) ((x) << S_EGR_CACHE_DATA_PERR)
+#define F_EGR_CACHE_DATA_PERR    V_EGR_CACHE_DATA_PERR(1U)
+
+#define S_EGR_CACHE_TAG_PERR    12
+#define V_EGR_CACHE_TAG_PERR(x) ((x) << S_EGR_CACHE_TAG_PERR)
+#define F_EGR_CACHE_TAG_PERR    V_EGR_CACHE_TAG_PERR(1U)
+
+#define S_CIM_PERR    11
+#define V_CIM_PERR(x) ((x) << S_CIM_PERR)
+#define F_CIM_PERR    V_CIM_PERR(1U)
+
+#define S_MA_INV_RSP_TAG    10
+#define V_MA_INV_RSP_TAG(x) ((x) << S_MA_INV_RSP_TAG)
+#define F_MA_INV_RSP_TAG    V_MA_INV_RSP_TAG(1U)
+
+#define S_ING_KEY_RANGE_ERR    9
+#define V_ING_KEY_RANGE_ERR(x) ((x) << S_ING_KEY_RANGE_ERR)
+#define F_ING_KEY_RANGE_ERR    V_ING_KEY_RANGE_ERR(1U)
+
+#define S_ING_MFIFO_OVFL    8
+#define V_ING_MFIFO_OVFL(x) ((x) << S_ING_MFIFO_OVFL)
+#define F_ING_MFIFO_OVFL    V_ING_MFIFO_OVFL(1U)
+
+#define S_LKP_REQ_OVFL    7
+#define V_LKP_REQ_OVFL(x) ((x) << S_LKP_REQ_OVFL)
+#define F_LKP_REQ_OVFL    V_LKP_REQ_OVFL(1U)
+
+#define S_EOK_WAIT_ERR    6
+#define V_EOK_WAIT_ERR(x) ((x) << S_EOK_WAIT_ERR)
+#define F_EOK_WAIT_ERR    V_EOK_WAIT_ERR(1U)
+
+#define S_EGR_KEY_RANGE_ERR    5
+#define V_EGR_KEY_RANGE_ERR(x) ((x) << S_EGR_KEY_RANGE_ERR)
+#define F_EGR_KEY_RANGE_ERR    V_EGR_KEY_RANGE_ERR(1U)
+
+#define S_EGR_MFIFO_OVFL    4
+#define V_EGR_MFIFO_OVFL(x) ((x) << S_EGR_MFIFO_OVFL)
+#define F_EGR_MFIFO_OVFL    V_EGR_MFIFO_OVFL(1U)
+
+#define S_SEQ_WRAP_HP_OVFL    3
+#define V_SEQ_WRAP_HP_OVFL(x) ((x) << S_SEQ_WRAP_HP_OVFL)
+#define F_SEQ_WRAP_HP_OVFL    V_SEQ_WRAP_HP_OVFL(1U)
+
+#define S_SEQ_WRAP_LP_OVFL    2
+#define V_SEQ_WRAP_LP_OVFL(x) ((x) << S_SEQ_WRAP_LP_OVFL)
+#define F_SEQ_WRAP_LP_OVFL    V_SEQ_WRAP_LP_OVFL(1U)
+
+#define S_EGR_SEQ_WRAP_HP    1
+#define V_EGR_SEQ_WRAP_HP(x) ((x) << S_EGR_SEQ_WRAP_HP)
+#define F_EGR_SEQ_WRAP_HP    V_EGR_SEQ_WRAP_HP(1U)
+
+#define S_EGR_SEQ_WRAP_LP    0
+#define V_EGR_SEQ_WRAP_LP(x) ((x) << S_EGR_SEQ_WRAP_LP)
+#define F_EGR_SEQ_WRAP_LP    V_EGR_SEQ_WRAP_LP(1U)
+
+#define A_CRYPTO_KEY_INT_CAUSE 0x4600c
+#define A_CRYPTO_KEY_PERR_ENABLE 0x46010
+#define A_CRYPTO_KEY_EGR_SEQ_WRAP_LP_KEY_ID 0x46018
+
+#define S_KEY_VALID    31
+#define V_KEY_VALID(x) ((x) << S_KEY_VALID)
+#define F_KEY_VALID    V_KEY_VALID(1U)
+
+#define S_KEY_ID    0
+#define M_KEY_ID    0x7fffffffU
+#define V_KEY_ID(x) ((x) << S_KEY_ID)
+#define G_KEY_ID(x) (((x) >> S_KEY_ID) & M_KEY_ID)
+
+#define A_CRYPTO_KEY_EGR_SEQ_WRAP_HP_KEY_ID 0x4601c
+#define A_CRYPTO_KEY_TCAM_DATA0 0x46020
+#define A_CRYPTO_KEY_TCAM_DATA1 0x46024
+#define A_CRYPTO_KEY_TCAM_DATA2 0x46028
+#define A_CRYPTO_KEY_TCAM_DATA3 0x4602c
+#define A_CRYPTO_KEY_TCAM_CTL 0x46030
+
+#define S_SRCHMHIT    21
+#define V_SRCHMHIT(x) ((x) << S_SRCHMHIT)
+#define F_SRCHMHIT    V_SRCHMHIT(1U)
+
+#define S_T7_BUSY    20
+#define V_T7_BUSY(x) ((x) << S_T7_BUSY)
+#define F_T7_BUSY    V_T7_BUSY(1U)
+
+#define S_SRCHHIT    19
+#define V_SRCHHIT(x) ((x) << S_SRCHHIT)
+#define F_SRCHHIT    V_SRCHHIT(1U)
+
+#define S_IPVERSION    18
+#define V_IPVERSION(x) ((x) << S_IPVERSION)
+#define F_IPVERSION    V_IPVERSION(1U)
+
+#define S_BITSEL    17
+#define V_BITSEL(x) ((x) << S_BITSEL)
+#define F_BITSEL    V_BITSEL(1U)
+
+#define S_TCAMSEL    16
+#define V_TCAMSEL(x) ((x) << S_TCAMSEL)
+#define F_TCAMSEL    V_TCAMSEL(1U)
+
+#define S_CMDTYPE    14
+#define M_CMDTYPE    0x3U
+#define V_CMDTYPE(x) ((x) << S_CMDTYPE)
+#define G_CMDTYPE(x) (((x) >> S_CMDTYPE) & M_CMDTYPE)
+
+#define S_TCAMINDEX    0
+#define M_TCAMINDEX    0x3fffU
+#define V_TCAMINDEX(x) ((x) << S_TCAMINDEX)
+#define G_TCAMINDEX(x) (((x) >> S_TCAMINDEX) & M_TCAMINDEX)
+
+#define A_CRYPTO_KEY_TCAM_CONFIG 0x46034
+
+#define S_T7_CLTCAMDEEPSLEEP_STAT    3
+#define V_T7_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_T7_CLTCAMDEEPSLEEP_STAT)
+#define F_T7_CLTCAMDEEPSLEEP_STAT    V_T7_CLTCAMDEEPSLEEP_STAT(1U)
+
+#define S_T7_TCAMDEEPSLEEP_STAT    2
+#define V_T7_TCAMDEEPSLEEP_STAT(x) ((x) << S_T7_TCAMDEEPSLEEP_STAT)
+#define F_T7_TCAMDEEPSLEEP_STAT    V_T7_TCAMDEEPSLEEP_STAT(1U)
+
+#define S_T7_CLTCAMDEEPSLEEP    1
+#define V_T7_CLTCAMDEEPSLEEP(x) ((x) << S_T7_CLTCAMDEEPSLEEP)
+#define F_T7_CLTCAMDEEPSLEEP    V_T7_CLTCAMDEEPSLEEP(1U)
+
+#define S_T7_TCAMDEEPSLEEP    0
+#define V_T7_TCAMDEEPSLEEP(x) ((x) << S_T7_TCAMDEEPSLEEP)
+#define F_T7_TCAMDEEPSLEEP    V_T7_TCAMDEEPSLEEP(1U)
+
+#define A_CRYPTO_KEY_TX_CMM_CONFIG 0x46040
+#define A_CRYPTO_KEY_TX_TNL_BASE 0x46044
+#define A_CRYPTO_KEY_TX_TRN_BASE 0x46048
+#define A_CRYPTO_KEY_TX_MAX_KEYS 0x4604c
+
+#define S_TNL_MAX    16
+#define M_TNL_MAX    0xffffU
+#define V_TNL_MAX(x) ((x) << S_TNL_MAX)
+#define G_TNL_MAX(x) (((x) >> S_TNL_MAX) & M_TNL_MAX)
+
+#define S_TRN_MAX    0
+#define M_TRN_MAX    0xffffU
+#define V_TRN_MAX(x) ((x) << S_TRN_MAX)
+#define G_TRN_MAX(x) (((x) >> S_TRN_MAX) & M_TRN_MAX)
+
+#define A_CRYPTO_KEY_TX_SEQ_STAT 0x46050
+
+#define S_ESN    24
+#define V_ESN(x) ((x) << S_ESN)
+#define F_ESN    V_ESN(1U)
+
+#define S_SEQHI    20
+#define M_SEQHI    0xfU
+#define V_SEQHI(x) ((x) << S_SEQHI)
+#define G_SEQHI(x) (((x) >> S_SEQHI) & M_SEQHI)
+
+#define S_KEYID    0
+#define M_KEYID    0xfffffU
+#define V_KEYID(x) ((x) << S_KEYID)
+#define G_KEYID(x) (((x) >> S_KEYID) & M_KEYID)
+
+#define A_CRYPTO_KEY_RX_CMM_CONFIG 0x46060
+#define A_CRYPTO_KEY_RX_BASE 0x46064
+#define A_CRYPTO_KEY_RX_MAX_KEYS 0x46068
+
+#define S_MAXKEYS    0
+#define M_MAXKEYS    0xffffU
+#define V_MAXKEYS(x) ((x) << S_MAXKEYS)
+#define G_MAXKEYS(x) (((x) >> S_MAXKEYS) & M_MAXKEYS)
+
+#define A_CRYPTO_KEY_CRYPTO_REVISION 0x4606c
+#define A_CRYPTO_KEY_RX_SEQ_STAT 0x46070
+#define A_CRYPTO_KEY_TCAM_BIST_CTRL 0x46074
+#define A_CRYPTO_KEY_TCAM_BIST_CB_PASS 0x46078
+#define A_CRYPTO_KEY_TCAM_BIST_CB_BUSY 0x4607c
+#define A_CRYPTO_KEY_DBG_SEL_CTRL 0x46080
+
+#define S_SEL_OVR_EN    16
+#define V_SEL_OVR_EN(x) ((x) << S_SEL_OVR_EN)
+#define F_SEL_OVR_EN    V_SEL_OVR_EN(1U)
+
+#define S_T7_1_SELH    8
+#define M_T7_1_SELH    0xffU
+#define V_T7_1_SELH(x) ((x) << S_T7_1_SELH)
+#define G_T7_1_SELH(x) (((x) >> S_T7_1_SELH) & M_T7_1_SELH)
+
+#define S_T7_1_SELL    0
+#define M_T7_1_SELL    0xffU
+#define V_T7_1_SELL(x) ((x) << S_T7_1_SELL)
+#define G_T7_1_SELL(x) (((x) >> S_T7_1_SELL) & M_T7_1_SELL)
+
+#define A_CRYPTO_KEY_DBG_SELL_DATA 0x46084
+#define A_CRYPTO_KEY_DBG_SELH_DATA 0x46088
+
+/* registers for module ARM */
+#define ARM_BASE_ADDR 0x47000
+
+#define A_ARM_CPU_POR_RST 0x47000
+
+#define S_CPUPORRSTN3    3
+#define V_CPUPORRSTN3(x) ((x) << S_CPUPORRSTN3)
+#define F_CPUPORRSTN3    V_CPUPORRSTN3(1U)
+
+#define S_CPUPORRSTN2    2
+#define V_CPUPORRSTN2(x) ((x) << S_CPUPORRSTN2)
+#define F_CPUPORRSTN2    V_CPUPORRSTN2(1U)
+
+#define S_CPUPORRSTN1    1
+#define V_CPUPORRSTN1(x) ((x) << S_CPUPORRSTN1)
+#define F_CPUPORRSTN1    V_CPUPORRSTN1(1U)
+
+#define S_CPUPORRSTN0    0
+#define V_CPUPORRSTN0(x) ((x) << S_CPUPORRSTN0)
+#define F_CPUPORRSTN0    V_CPUPORRSTN0(1U)
+
+#define A_ARM_CPU_CORE_RST 0x47004
+
+#define S_CPUCORERSTN3    3
+#define V_CPUCORERSTN3(x) ((x) << S_CPUCORERSTN3)
+#define F_CPUCORERSTN3    V_CPUCORERSTN3(1U)
+
+#define S_CPUCORERSTN2    2
+#define V_CPUCORERSTN2(x) ((x) << S_CPUCORERSTN2)
+#define F_CPUCORERSTN2    V_CPUCORERSTN2(1U)
+
+#define S_CPUCORERSTN1    1
+#define V_CPUCORERSTN1(x) ((x) << S_CPUCORERSTN1)
+#define F_CPUCORERSTN1    V_CPUCORERSTN1(1U)
+
+#define S_CPUCORERSTN0    0
+#define V_CPUCORERSTN0(x) ((x) << S_CPUCORERSTN0)
+#define F_CPUCORERSTN0    V_CPUCORERSTN0(1U)
+
+#define A_ARM_CPU_WARM_RST_REQ 0x47008
+
+#define S_CPUWARMRSTREQ3    3
+#define V_CPUWARMRSTREQ3(x) ((x) << S_CPUWARMRSTREQ3)
+#define F_CPUWARMRSTREQ3    V_CPUWARMRSTREQ3(1U)
+
+#define S_CPUWARMRSTREQ2    2
+#define V_CPUWARMRSTREQ2(x) ((x) << S_CPUWARMRSTREQ2)
+#define F_CPUWARMRSTREQ2    V_CPUWARMRSTREQ2(1U)
+
+#define S_CPUWARMRSTREQ1    1
+#define V_CPUWARMRSTREQ1(x) ((x) << S_CPUWARMRSTREQ1)
+#define F_CPUWARMRSTREQ1    V_CPUWARMRSTREQ1(1U)
+
+#define S_CPUWARMRSTREQ0    0
+#define V_CPUWARMRSTREQ0(x) ((x) << S_CPUWARMRSTREQ0)
+#define F_CPUWARMRSTREQ0    V_CPUWARMRSTREQ0(1U)
+
+#define A_ARM_CPU_L2_RST 0x4700c
+
+#define S_CPUL2RSTN    0
+#define V_CPUL2RSTN(x) ((x) << S_CPUL2RSTN)
+#define F_CPUL2RSTN    V_CPUL2RSTN(1U)
+
+#define A_ARM_CPU_L2_RST_DIS 0x47010
+
+#define S_CPUL2RSTDISABLE    0
+#define V_CPUL2RSTDISABLE(x) ((x) << S_CPUL2RSTDISABLE)
+#define F_CPUL2RSTDISABLE    V_CPUL2RSTDISABLE(1U)
+
+#define A_ARM_CPU_PRESET_DBG 0x47014
+
+#define S_CPUPRESETDBGN    0
+#define V_CPUPRESETDBGN(x) ((x) << S_CPUPRESETDBGN)
+#define F_CPUPRESETDBGN    V_CPUPRESETDBGN(1U)
+
+#define A_ARM_PL_DMA_AW_OFFSET 0x47018
+
+#define S_PL_DMA_AW_OFFSET    0
+#define M_PL_DMA_AW_OFFSET    0x3fffffffU
+#define V_PL_DMA_AW_OFFSET(x) ((x) << S_PL_DMA_AW_OFFSET)
+#define G_PL_DMA_AW_OFFSET(x) (((x) >> S_PL_DMA_AW_OFFSET) & M_PL_DMA_AW_OFFSET)
+
+#define A_ARM_PL_DMA_AR_OFFSET 0x4701c
+
+#define S_PL_DMA_AR_OFFSET    0
+#define M_PL_DMA_AR_OFFSET    0x3fffffffU
+#define V_PL_DMA_AR_OFFSET(x) ((x) << S_PL_DMA_AR_OFFSET)
+#define G_PL_DMA_AR_OFFSET(x) (((x) >> S_PL_DMA_AR_OFFSET) & M_PL_DMA_AR_OFFSET)
+
+#define A_ARM_CPU_RESET_VECTOR_BASE_ADDR0 0x47020
+#define A_ARM_CPU_RESET_VECTOR_BASE_ADDR1 0x47024
+
+#define S_CPURESETVECBA1    0
+#define M_CPURESETVECBA1    0x3ffU
+#define V_CPURESETVECBA1(x) ((x) << S_CPURESETVECBA1)
+#define G_CPURESETVECBA1(x) (((x) >> S_CPURESETVECBA1) & M_CPURESETVECBA1)
+
+#define A_ARM_CPU_PMU_EVENT 0x47028
+
+#define S_CPUPMUEVENT    0
+#define M_CPUPMUEVENT    0x1ffffffU
+#define V_CPUPMUEVENT(x) ((x) << S_CPUPMUEVENT)
+#define G_CPUPMUEVENT(x) (((x) >> S_CPUPMUEVENT) & M_CPUPMUEVENT)
+
+#define A_ARM_DMA_RST 0x4702c
+
+#define S_DMA_PL_RST_N    0
+#define V_DMA_PL_RST_N(x) ((x) << S_DMA_PL_RST_N)
+#define F_DMA_PL_RST_N    V_DMA_PL_RST_N(1U)
+
+#define A_ARM_PLM_RID_CFG 0x4703c
+#define A_ARM_PLM_EROM_CFG 0x47040
+#define A_ARM_PL_ARM_HDR_CFG 0x4704c
+#define A_ARM_RC_INT_STATUS 0x4705c
+
+#define S_RC_INT_STATUS_REG    0
+#define M_RC_INT_STATUS_REG    0x3fU
+#define V_RC_INT_STATUS_REG(x) ((x) << S_RC_INT_STATUS_REG)
+#define G_RC_INT_STATUS_REG(x) (((x) >> S_RC_INT_STATUS_REG) & M_RC_INT_STATUS_REG)
+
+#define A_ARM_CPU_DBG_PWR_UP_REQ 0x47060
+
+#define S_CPUDBGPWRUPREQ3    3
+#define V_CPUDBGPWRUPREQ3(x) ((x) << S_CPUDBGPWRUPREQ3)
+#define F_CPUDBGPWRUPREQ3    V_CPUDBGPWRUPREQ3(1U)
+
+#define S_CPUDBGPWRUPREQ2    2
+#define V_CPUDBGPWRUPREQ2(x) ((x) << S_CPUDBGPWRUPREQ2)
+#define F_CPUDBGPWRUPREQ2    V_CPUDBGPWRUPREQ2(1U)
+
+#define S_CPUDBGPWRUPREQ1    1
+#define V_CPUDBGPWRUPREQ1(x) ((x) << S_CPUDBGPWRUPREQ1)
+#define F_CPUDBGPWRUPREQ1    V_CPUDBGPWRUPREQ1(1U)
+
+#define S_CPUDBGPWRUPREQ0    0
+#define V_CPUDBGPWRUPREQ0(x) ((x) << S_CPUDBGPWRUPREQ0)
+#define F_CPUDBGPWRUPREQ0    V_CPUDBGPWRUPREQ0(1U)
+
+#define A_ARM_CPU_STANDBY_WFE_WFI 0x47064
+
+#define S_CPUSTANDBYWFIL2    8
+#define V_CPUSTANDBYWFIL2(x) ((x) << S_CPUSTANDBYWFIL2)
+#define F_CPUSTANDBYWFIL2    V_CPUSTANDBYWFIL2(1U)
+
+#define S_CPUSTANDBYWFI3    7
+#define V_CPUSTANDBYWFI3(x) ((x) << S_CPUSTANDBYWFI3)
+#define F_CPUSTANDBYWFI3    V_CPUSTANDBYWFI3(1U)
+
+#define S_CPUSTANDBYWFI2    6
+#define V_CPUSTANDBYWFI2(x) ((x) << S_CPUSTANDBYWFI2)
+#define F_CPUSTANDBYWFI2    V_CPUSTANDBYWFI2(1U)
+
+#define S_CPUSTANDBYWFI1    5
+#define V_CPUSTANDBYWFI1(x) ((x) << S_CPUSTANDBYWFI1)
+#define F_CPUSTANDBYWFI1    V_CPUSTANDBYWFI1(1U)
+
+#define S_CPUSTANDBYWFI0    4
+#define V_CPUSTANDBYWFI0(x) ((x) << S_CPUSTANDBYWFI0)
+#define F_CPUSTANDBYWFI0    V_CPUSTANDBYWFI0(1U)
+
+#define S_CPUSTANDBYWFE3    3
+#define V_CPUSTANDBYWFE3(x) ((x) << S_CPUSTANDBYWFE3)
+#define F_CPUSTANDBYWFE3    V_CPUSTANDBYWFE3(1U)
+
+#define S_CPUSTANDBYWFE2    2
+#define V_CPUSTANDBYWFE2(x) ((x) << S_CPUSTANDBYWFE2)
+#define F_CPUSTANDBYWFE2    V_CPUSTANDBYWFE2(1U)
+
+#define S_CPUSTANDBYWFE1    1
+#define V_CPUSTANDBYWFE1(x) ((x) << S_CPUSTANDBYWFE1)
+#define F_CPUSTANDBYWFE1    V_CPUSTANDBYWFE1(1U)
+
+#define S_CPUSTANDBYWFE0    0
+#define V_CPUSTANDBYWFE0(x) ((x) << S_CPUSTANDBYWFE0)
+#define F_CPUSTANDBYWFE0    V_CPUSTANDBYWFE0(1U)
+
+#define A_ARM_CPU_SMPEN 0x47068
+
+#define S_CPUSMPEN3    3
+#define V_CPUSMPEN3(x) ((x) << S_CPUSMPEN3)
+#define F_CPUSMPEN3    V_CPUSMPEN3(1U)
+
+#define S_CPUSMPEN2    2
+#define V_CPUSMPEN2(x) ((x) << S_CPUSMPEN2)
+#define F_CPUSMPEN2    V_CPUSMPEN2(1U)
+
+#define S_CPUSMPEN1    1
+#define V_CPUSMPEN1(x) ((x) << S_CPUSMPEN1)
+#define F_CPUSMPEN1    V_CPUSMPEN1(1U)
+
+#define S_CPUSMPEN0    0
+#define V_CPUSMPEN0(x) ((x) << S_CPUSMPEN0)
+#define F_CPUSMPEN0    V_CPUSMPEN0(1U)
+
+#define A_ARM_CPU_QACTIVE 0x4706c
+
+#define S_CPUQACTIVE3    3
+#define V_CPUQACTIVE3(x) ((x) << S_CPUQACTIVE3)
+#define F_CPUQACTIVE3    V_CPUQACTIVE3(1U)
+
+#define S_CPUQACTIVE2    2
+#define V_CPUQACTIVE2(x) ((x) << S_CPUQACTIVE2)
+#define F_CPUQACTIVE2    V_CPUQACTIVE2(1U)
+
+#define S_CPUQACTIVE1    1
+#define V_CPUQACTIVE1(x) ((x) << S_CPUQACTIVE1)
+#define F_CPUQACTIVE1    V_CPUQACTIVE1(1U)
+
+#define S_CPUQACTIVE0    0
+#define V_CPUQACTIVE0(x) ((x) << S_CPUQACTIVE0)
+#define F_CPUQACTIVE0    V_CPUQACTIVE0(1U)
+
+#define A_ARM_CPU_QREQ 0x47070
+
+#define S_CPUL2FLUSHREQ    5
+#define V_CPUL2FLUSHREQ(x) ((x) << S_CPUL2FLUSHREQ)
+#define F_CPUL2FLUSHREQ    V_CPUL2FLUSHREQ(1U)
+
+#define S_CPUL2QREQN    4
+#define V_CPUL2QREQN(x) ((x) << S_CPUL2QREQN)
+#define F_CPUL2QREQN    V_CPUL2QREQN(1U)
+
+#define S_CPUQREQ3N    3
+#define V_CPUQREQ3N(x) ((x) << S_CPUQREQ3N)
+#define F_CPUQREQ3N    V_CPUQREQ3N(1U)
+
+#define S_CPUQREQ2N    2
+#define V_CPUQREQ2N(x) ((x) << S_CPUQREQ2N)
+#define F_CPUQREQ2N    V_CPUQREQ2N(1U)
+
+#define S_CPUQREQ1N    1
+#define V_CPUQREQ1N(x) ((x) << S_CPUQREQ1N)
+#define F_CPUQREQ1N    V_CPUQREQ1N(1U)
+
+#define S_CPUQREQ0N    0
+#define V_CPUQREQ0N(x) ((x) << S_CPUQREQ0N)
+#define F_CPUQREQ0N    V_CPUQREQ0N(1U)
+
+#define A_ARM_CPU_QREQ_STATUS 0x47074
+
+#define S_CPUL2FLUSHDONE    10
+#define V_CPUL2FLUSHDONE(x) ((x) << S_CPUL2FLUSHDONE)
+#define F_CPUL2FLUSHDONE    V_CPUL2FLUSHDONE(1U)
+
+#define S_CPUL2QDENY    9
+#define V_CPUL2QDENY(x) ((x) << S_CPUL2QDENY)
+#define F_CPUL2QDENY    V_CPUL2QDENY(1U)
+
+#define S_CPUL2QACCEPTN    8
+#define V_CPUL2QACCEPTN(x) ((x) << S_CPUL2QACCEPTN)
+#define F_CPUL2QACCEPTN    V_CPUL2QACCEPTN(1U)
+
+#define S_CPUQDENY3    7
+#define V_CPUQDENY3(x) ((x) << S_CPUQDENY3)
+#define F_CPUQDENY3    V_CPUQDENY3(1U)
+
+#define S_CPUQDENY2    6
+#define V_CPUQDENY2(x) ((x) << S_CPUQDENY2)
+#define F_CPUQDENY2    V_CPUQDENY2(1U)
+
+#define S_CPUQDENY1    5
+#define V_CPUQDENY1(x) ((x) << S_CPUQDENY1)
+#define F_CPUQDENY1    V_CPUQDENY1(1U)
+
+#define S_CPUQDENY0    4
+#define V_CPUQDENY0(x) ((x) << S_CPUQDENY0)
+#define F_CPUQDENY0    V_CPUQDENY0(1U)
+
+#define S_CPUQACCEPT3N    3
+#define V_CPUQACCEPT3N(x) ((x) << S_CPUQACCEPT3N)
+#define F_CPUQACCEPT3N    V_CPUQACCEPT3N(1U)
+
+#define S_CPUQACCEPT2N    2
+#define V_CPUQACCEPT2N(x) ((x) << S_CPUQACCEPT2N)
+#define F_CPUQACCEPT2N    V_CPUQACCEPT2N(1U)
+
+#define S_CPUQACCEPT1N    1
+#define V_CPUQACCEPT1N(x) ((x) << S_CPUQACCEPT1N)
+#define F_CPUQACCEPT1N    V_CPUQACCEPT1N(1U)
+
+#define S_CPUQACCEPT0N    0
+#define V_CPUQACCEPT0N(x) ((x) << S_CPUQACCEPT0N)
+#define F_CPUQACCEPT0N    V_CPUQACCEPT0N(1U)
+
+#define A_ARM_CPU_DBG_EN 0x47078
+
+#define S_CPUDBGL1RSTDISABLE    28
+#define V_CPUDBGL1RSTDISABLE(x) ((x) << S_CPUDBGL1RSTDISABLE)
+#define F_CPUDBGL1RSTDISABLE    V_CPUDBGL1RSTDISABLE(1U)
+
+#define S_CPUDBGRSTREQ3    27
+#define V_CPUDBGRSTREQ3(x) ((x) << S_CPUDBGRSTREQ3)
+#define F_CPUDBGRSTREQ3    V_CPUDBGRSTREQ3(1U)
+
+#define S_CPUDBGRSTREQ2    26
+#define V_CPUDBGRSTREQ2(x) ((x) << S_CPUDBGRSTREQ2)
+#define F_CPUDBGRSTREQ2    V_CPUDBGRSTREQ2(1U)
+
+#define S_CPUDBGRSTREQ1    25
+#define V_CPUDBGRSTREQ1(x) ((x) << S_CPUDBGRSTREQ1)
+#define F_CPUDBGRSTREQ1    V_CPUDBGRSTREQ1(1U)
+
+#define S_CPUDBGRSTREQ0    24
+#define V_CPUDBGRSTREQ0(x) ((x) << S_CPUDBGRSTREQ0)
+#define F_CPUDBGRSTREQ0    V_CPUDBGRSTREQ0(1U)
+
+#define S_CPUDBGPWRDUP3    23
+#define V_CPUDBGPWRDUP3(x) ((x) << S_CPUDBGPWRDUP3)
+#define F_CPUDBGPWRDUP3    V_CPUDBGPWRDUP3(1U)
+
+#define S_CPUDBGPWRDUP2    22
+#define V_CPUDBGPWRDUP2(x) ((x) << S_CPUDBGPWRDUP2)
+#define F_CPUDBGPWRDUP2    V_CPUDBGPWRDUP2(1U)
+
+#define S_CPUDBGPWRDUP1    21
+#define V_CPUDBGPWRDUP1(x) ((x) << S_CPUDBGPWRDUP1)
+#define F_CPUDBGPWRDUP1    V_CPUDBGPWRDUP1(1U)
+
+#define S_CPUDBGPWRDUP0    20
+#define V_CPUDBGPWRDUP0(x) ((x) << S_CPUDBGPWRDUP0)
+#define F_CPUDBGPWRDUP0    V_CPUDBGPWRDUP0(1U)
+
+#define S_CPUEXTDBGREQ3    19
+#define V_CPUEXTDBGREQ3(x) ((x) << S_CPUEXTDBGREQ3)
+#define F_CPUEXTDBGREQ3    V_CPUEXTDBGREQ3(1U)
+
+#define S_CPUEXTDBGREQ2    18
+#define V_CPUEXTDBGREQ2(x) ((x) << S_CPUEXTDBGREQ2)
+#define F_CPUEXTDBGREQ2    V_CPUEXTDBGREQ2(1U)
+
+#define S_CPUEXTDBGREQ1    17
+#define V_CPUEXTDBGREQ1(x) ((x) << S_CPUEXTDBGREQ1)
+#define F_CPUEXTDBGREQ1    V_CPUEXTDBGREQ1(1U)
+
+#define S_CPUEXTDBGREQ0    16
+#define V_CPUEXTDBGREQ0(x) ((x) << S_CPUEXTDBGREQ0)
+#define F_CPUEXTDBGREQ0    V_CPUEXTDBGREQ0(1U)
+
+#define S_CPUSPNIDEN3    15
+#define V_CPUSPNIDEN3(x) ((x) << S_CPUSPNIDEN3)
+#define F_CPUSPNIDEN3    V_CPUSPNIDEN3(1U)
+
+#define S_CPUSPNIDEN2    14
+#define V_CPUSPNIDEN2(x) ((x) << S_CPUSPNIDEN2)
+#define F_CPUSPNIDEN2    V_CPUSPNIDEN2(1U)
+
+#define S_CPUSPNIDEN1    13
+#define V_CPUSPNIDEN1(x) ((x) << S_CPUSPNIDEN1)
+#define F_CPUSPNIDEN1    V_CPUSPNIDEN1(1U)
+
+#define S_CPUSPNIDEN0    12
+#define V_CPUSPNIDEN0(x) ((x) << S_CPUSPNIDEN0)
+#define F_CPUSPNIDEN0    V_CPUSPNIDEN0(1U)
+
+#define S_CPUSPDBGEN3    11
+#define V_CPUSPDBGEN3(x) ((x) << S_CPUSPDBGEN3)
+#define F_CPUSPDBGEN3    V_CPUSPDBGEN3(1U)
+
+#define S_CPUSPDBGEN2    10
+#define V_CPUSPDBGEN2(x) ((x) << S_CPUSPDBGEN2)
+#define F_CPUSPDBGEN2    V_CPUSPDBGEN2(1U)
+
+#define S_CPUSPDBGEN1    9
+#define V_CPUSPDBGEN1(x) ((x) << S_CPUSPDBGEN1)
+#define F_CPUSPDBGEN1    V_CPUSPDBGEN1(1U)
+
+#define S_CPUSPDBGEN0    8
+#define V_CPUSPDBGEN0(x) ((x) << S_CPUSPDBGEN0)
+#define F_CPUSPDBGEN0    V_CPUSPDBGEN0(1U)
+
+#define S_CPUNIDEN3    7
+#define V_CPUNIDEN3(x) ((x) << S_CPUNIDEN3)
+#define F_CPUNIDEN3    V_CPUNIDEN3(1U)
+
+#define S_CPUNIDEN2    6
+#define V_CPUNIDEN2(x) ((x) << S_CPUNIDEN2)
+#define F_CPUNIDEN2    V_CPUNIDEN2(1U)
+
+#define S_CPUNIDEN1    5
+#define V_CPUNIDEN1(x) ((x) << S_CPUNIDEN1)
+#define F_CPUNIDEN1    V_CPUNIDEN1(1U)
+
+#define S_CPUNIDEN0    4
+#define V_CPUNIDEN0(x) ((x) << S_CPUNIDEN0)
+#define F_CPUNIDEN0    V_CPUNIDEN0(1U)
+
+#define S_CPUDBGEN3    3
+#define V_CPUDBGEN3(x) ((x) << S_CPUDBGEN3)
+#define F_CPUDBGEN3    V_CPUDBGEN3(1U)
+
+#define S_CPUDBGEN2    2
+#define V_CPUDBGEN2(x) ((x) << S_CPUDBGEN2)
+#define F_CPUDBGEN2    V_CPUDBGEN2(1U)
+
+#define S_CPUDBGEN1    1
+#define V_CPUDBGEN1(x) ((x) << S_CPUDBGEN1)
+#define F_CPUDBGEN1    V_CPUDBGEN1(1U)
+
+#define S_CPUDBGEN0    0
+#define V_CPUDBGEN0(x) ((x) << S_CPUDBGEN0)
+#define F_CPUDBGEN0    V_CPUDBGEN0(1U)
+
+#define A_ARM_CPU_DBG_ACK 0x4707c
+
+#define S_CPUDBGNOPWRDWN3    11
+#define V_CPUDBGNOPWRDWN3(x) ((x) << S_CPUDBGNOPWRDWN3)
+#define F_CPUDBGNOPWRDWN3    V_CPUDBGNOPWRDWN3(1U)
+
+#define S_CPUDBGNOPWRDWN2    10
+#define V_CPUDBGNOPWRDWN2(x) ((x) << S_CPUDBGNOPWRDWN2)
+#define F_CPUDBGNOPWRDWN2    V_CPUDBGNOPWRDWN2(1U)
+
+#define S_CPUDBGNOPWRDWN1    9
+#define V_CPUDBGNOPWRDWN1(x) ((x) << S_CPUDBGNOPWRDWN1)
+#define F_CPUDBGNOPWRDWN1    V_CPUDBGNOPWRDWN1(1U)
+
+#define S_CPUDBGNOPWRDWN0    8
+#define V_CPUDBGNOPWRDWN0(x) ((x) << S_CPUDBGNOPWRDWN0)
+#define F_CPUDBGNOPWRDWN0    V_CPUDBGNOPWRDWN0(1U)
+
+#define S_CPUDGNRSTREQ3    7
+#define V_CPUDGNRSTREQ3(x) ((x) << S_CPUDGNRSTREQ3)
+#define F_CPUDGNRSTREQ3    V_CPUDGNRSTREQ3(1U)
+
+#define S_CPUDGNRSTREQ2    6
+#define V_CPUDGNRSTREQ2(x) ((x) << S_CPUDGNRSTREQ2)
+#define F_CPUDGNRSTREQ2    V_CPUDGNRSTREQ2(1U)
+
+#define S_CPUDGNRSTREQ1    5
+#define V_CPUDGNRSTREQ1(x) ((x) << S_CPUDGNRSTREQ1)
+#define F_CPUDGNRSTREQ1    V_CPUDGNRSTREQ1(1U)
+
+#define S_CPUDGNRSTREQ0    4
+#define V_CPUDGNRSTREQ0(x) ((x) << S_CPUDGNRSTREQ0)
+#define F_CPUDGNRSTREQ0    V_CPUDGNRSTREQ0(1U)
+
+#define S_CPUDBGACK3    3
+#define V_CPUDBGACK3(x) ((x) << S_CPUDBGACK3)
+#define F_CPUDBGACK3    V_CPUDBGACK3(1U)
+
+#define S_CPUDBGACK2    2
+#define V_CPUDBGACK2(x) ((x) << S_CPUDBGACK2)
+#define F_CPUDBGACK2    V_CPUDBGACK2(1U)
+
+#define S_CPUDBGACK1    1
+#define V_CPUDBGACK1(x) ((x) << S_CPUDBGACK1)
+#define F_CPUDBGACK1    V_CPUDBGACK1(1U)
+
+#define S_CPUDBGACK0    0
+#define V_CPUDBGACK0(x) ((x) << S_CPUDBGACK0)
+#define F_CPUDBGACK0    V_CPUDBGACK0(1U)
+
+#define A_ARM_CPU_PMU_SNAPSHOT_REQ 0x47080
+
+#define S_CPUPMUSNAPSHOTREQ3    3
+#define V_CPUPMUSNAPSHOTREQ3(x) ((x) << S_CPUPMUSNAPSHOTREQ3)
+#define F_CPUPMUSNAPSHOTREQ3    V_CPUPMUSNAPSHOTREQ3(1U)
+
+#define S_CPUPMUSNAPSHOTREQ2    2
+#define V_CPUPMUSNAPSHOTREQ2(x) ((x) << S_CPUPMUSNAPSHOTREQ2)
+#define F_CPUPMUSNAPSHOTREQ2    V_CPUPMUSNAPSHOTREQ2(1U)
+
+#define S_CPUPMUSNAPSHOTREQ1    1
+#define V_CPUPMUSNAPSHOTREQ1(x) ((x) << S_CPUPMUSNAPSHOTREQ1)
+#define F_CPUPMUSNAPSHOTREQ1    V_CPUPMUSNAPSHOTREQ1(1U)
+
+#define S_CPUPMUSNAPSHOTREQ0    0
+#define V_CPUPMUSNAPSHOTREQ0(x) ((x) << S_CPUPMUSNAPSHOTREQ0)
+#define F_CPUPMUSNAPSHOTREQ0    V_CPUPMUSNAPSHOTREQ0(1U)
+
+#define A_ARM_CPU_PMU_SNAPSHOT_ACK 0x47084
+
+#define S_CPUPMUSNAPSHOTACK3    3
+#define V_CPUPMUSNAPSHOTACK3(x) ((x) << S_CPUPMUSNAPSHOTACK3)
+#define F_CPUPMUSNAPSHOTACK3    V_CPUPMUSNAPSHOTACK3(1U)
+
+#define S_CPUPMUSNAPSHOTACK2    2
+#define V_CPUPMUSNAPSHOTACK2(x) ((x) << S_CPUPMUSNAPSHOTACK2)
+#define F_CPUPMUSNAPSHOTACK2    V_CPUPMUSNAPSHOTACK2(1U)
+
+#define S_CPUPMUSNAPSHOTACK1    1
+#define V_CPUPMUSNAPSHOTACK1(x) ((x) << S_CPUPMUSNAPSHOTACK1)
+#define F_CPUPMUSNAPSHOTACK1    V_CPUPMUSNAPSHOTACK1(1U)
+
+#define S_CPUPMUSNAPSHOTACK0    0
+#define V_CPUPMUSNAPSHOTACK0(x) ((x) << S_CPUPMUSNAPSHOTACK0)
+#define F_CPUPMUSNAPSHOTACK0    V_CPUPMUSNAPSHOTACK0(1U)
+
+#define A_ARM_EMMC_CTRL 0x47088
+
+#define S_EMMC_DATA_P2    24
+#define M_EMMC_DATA_P2    0xffU
+#define V_EMMC_DATA_P2(x) ((x) << S_EMMC_DATA_P2)
+#define G_EMMC_DATA_P2(x) (((x) >> S_EMMC_DATA_P2) & M_EMMC_DATA_P2)
+
+#define S_EMMC_DATA_P1    16
+#define M_EMMC_DATA_P1    0xffU
+#define V_EMMC_DATA_P1(x) ((x) << S_EMMC_DATA_P1)
+#define G_EMMC_DATA_P1(x) (((x) >> S_EMMC_DATA_P1) & M_EMMC_DATA_P1)
+
+#define S_EMMC_CMD_P2    15
+#define V_EMMC_CMD_P2(x) ((x) << S_EMMC_CMD_P2)
+#define F_EMMC_CMD_P2    V_EMMC_CMD_P2(1U)
+
+#define S_EMMC_CMD_P1    14
+#define V_EMMC_CMD_P1(x) ((x) << S_EMMC_CMD_P1)
+#define F_EMMC_CMD_P1    V_EMMC_CMD_P1(1U)
+
+#define S_EMMC_RST_P2    13
+#define V_EMMC_RST_P2(x) ((x) << S_EMMC_RST_P2)
+#define F_EMMC_RST_P2    V_EMMC_RST_P2(1U)
+
+#define S_EMMC_RST_P1    12
+#define V_EMMC_RST_P1(x) ((x) << S_EMMC_RST_P1)
+#define F_EMMC_RST_P1    V_EMMC_RST_P1(1U)
+
+#define S_EMMC_GP_IN_P2    10
+#define M_EMMC_GP_IN_P2    0x3U
+#define V_EMMC_GP_IN_P2(x) ((x) << S_EMMC_GP_IN_P2)
+#define G_EMMC_GP_IN_P2(x) (((x) >> S_EMMC_GP_IN_P2) & M_EMMC_GP_IN_P2)
+
+#define S_EMMC_GP_IN_P1    8
+#define M_EMMC_GP_IN_P1    0x3U
+#define V_EMMC_GP_IN_P1(x) ((x) << S_EMMC_GP_IN_P1)
+#define G_EMMC_GP_IN_P1(x) (((x) >> S_EMMC_GP_IN_P1) & M_EMMC_GP_IN_P1)
+
+#define S_EMMC_CLK_SEL    0
+#define M_EMMC_CLK_SEL    0xffU
+#define V_EMMC_CLK_SEL(x) ((x) << S_EMMC_CLK_SEL)
+#define G_EMMC_CLK_SEL(x) (((x) >> S_EMMC_CLK_SEL) & M_EMMC_CLK_SEL)
+
+#define A_ARM_CPU_CFG_END_VINI_TE 0x4708c
+
+#define S_CPUSYSBARDISABLE    23
+#define V_CPUSYSBARDISABLE(x) ((x) << S_CPUSYSBARDISABLE)
+#define F_CPUSYSBARDISABLE    V_CPUSYSBARDISABLE(1U)
+
+#define S_CPUBROADCACHEMAIN    22
+#define V_CPUBROADCACHEMAIN(x) ((x) << S_CPUBROADCACHEMAIN)
+#define F_CPUBROADCACHEMAIN    V_CPUBROADCACHEMAIN(1U)
+
+#define S_CPUBROADOUTER    21
+#define V_CPUBROADOUTER(x) ((x) << S_CPUBROADOUTER)
+#define F_CPUBROADOUTER    V_CPUBROADOUTER(1U)
+
+#define S_CPUBROADINNER    20
+#define V_CPUBROADINNER(x) ((x) << S_CPUBROADINNER)
+#define F_CPUBROADINNER    V_CPUBROADINNER(1U)
+
+#define S_CPUCRYPTODISABLE3    19
+#define V_CPUCRYPTODISABLE3(x) ((x) << S_CPUCRYPTODISABLE3)
+#define F_CPUCRYPTODISABLE3    V_CPUCRYPTODISABLE3(1U)
+
+#define S_CPUCRYPTODISABLE2    18
+#define V_CPUCRYPTODISABLE2(x) ((x) << S_CPUCRYPTODISABLE2)
+#define F_CPUCRYPTODISABLE2    V_CPUCRYPTODISABLE2(1U)
+
+#define S_CPUCRYPTODISABLE1    17
+#define V_CPUCRYPTODISABLE1(x) ((x) << S_CPUCRYPTODISABLE1)
+#define F_CPUCRYPTODISABLE1    V_CPUCRYPTODISABLE1(1U)
+
+#define S_CPUCRYPTODISABLE0    16
+#define V_CPUCRYPTODISABLE0(x) ((x) << S_CPUCRYPTODISABLE0)
+#define F_CPUCRYPTODISABLE0    V_CPUCRYPTODISABLE0(1U)
+
+#define S_CPUAA64NAA323    15
+#define V_CPUAA64NAA323(x) ((x) << S_CPUAA64NAA323)
+#define F_CPUAA64NAA323    V_CPUAA64NAA323(1U)
+
+#define S_CPUAA64NAA322    14
+#define V_CPUAA64NAA322(x) ((x) << S_CPUAA64NAA322)
+#define F_CPUAA64NAA322    V_CPUAA64NAA322(1U)
+
+#define S_CPUAA64NAA321    13
+#define V_CPUAA64NAA321(x) ((x) << S_CPUAA64NAA321)
+#define F_CPUAA64NAA321    V_CPUAA64NAA321(1U)
+
+#define S_CPUAA64NAA320    12
+#define V_CPUAA64NAA320(x) ((x) << S_CPUAA64NAA320)
+#define F_CPUAA64NAA320    V_CPUAA64NAA320(1U)
+
+#define S_CPUCFGTE3    11
+#define V_CPUCFGTE3(x) ((x) << S_CPUCFGTE3)
+#define F_CPUCFGTE3    V_CPUCFGTE3(1U)
+
+#define S_CPUCFGTE2    10
+#define V_CPUCFGTE2(x) ((x) << S_CPUCFGTE2)
+#define F_CPUCFGTE2    V_CPUCFGTE2(1U)
+
+#define S_CPUCFGTE1    9
+#define V_CPUCFGTE1(x) ((x) << S_CPUCFGTE1)
+#define F_CPUCFGTE1    V_CPUCFGTE1(1U)
+
+#define S_CPUCFGTE0    8
+#define V_CPUCFGTE0(x) ((x) << S_CPUCFGTE0)
+#define F_CPUCFGTE0    V_CPUCFGTE0(1U)
+
+#define S_CPUVINIHI3    7
+#define V_CPUVINIHI3(x) ((x) << S_CPUVINIHI3)
+#define F_CPUVINIHI3    V_CPUVINIHI3(1U)
+
+#define S_CPUVINIHI2    6
+#define V_CPUVINIHI2(x) ((x) << S_CPUVINIHI2)
+#define F_CPUVINIHI2    V_CPUVINIHI2(1U)
+
+#define S_CPUVINIHI1    5
+#define V_CPUVINIHI1(x) ((x) << S_CPUVINIHI1)
+#define F_CPUVINIHI1    V_CPUVINIHI1(1U)
+
+#define S_CPUVINIHI0    4
+#define V_CPUVINIHI0(x) ((x) << S_CPUVINIHI0)
+#define F_CPUVINIHI0    V_CPUVINIHI0(1U)
+
+#define S_CPUCFGEND3    3
+#define V_CPUCFGEND3(x) ((x) << S_CPUCFGEND3)
+#define F_CPUCFGEND3    V_CPUCFGEND3(1U)
+
+#define S_CPUCFGEND2    2
+#define V_CPUCFGEND2(x) ((x) << S_CPUCFGEND2)
+#define F_CPUCFGEND2    V_CPUCFGEND2(1U)
+
+#define S_CPUCFGEND1    1
+#define V_CPUCFGEND1(x) ((x) << S_CPUCFGEND1)
+#define F_CPUCFGEND1    V_CPUCFGEND1(1U)
+
+#define S_CPUCFGEND0    0
+#define V_CPUCFGEND0(x) ((x) << S_CPUCFGEND0)
+#define F_CPUCFGEND0    V_CPUCFGEND0(1U)
+
+#define A_ARM_CPU_CP15_SDISABLE 0x47090
+
+#define S_CPUCP15SDISABLE3    3
+#define V_CPUCP15SDISABLE3(x) ((x) << S_CPUCP15SDISABLE3)
+#define F_CPUCP15SDISABLE3    V_CPUCP15SDISABLE3(1U)
+
+#define S_CPUCP15SDISABLE2    2
+#define V_CPUCP15SDISABLE2(x) ((x) << S_CPUCP15SDISABLE2)
+#define F_CPUCP15SDISABLE2    V_CPUCP15SDISABLE2(1U)
+
+#define S_CPUCP15SDISABLE1    1
+#define V_CPUCP15SDISABLE1(x) ((x) << S_CPUCP15SDISABLE1)
+#define F_CPUCP15SDISABLE1    V_CPUCP15SDISABLE1(1U)
+
+#define S_CPUCP15SDISABLE0    0
+#define V_CPUCP15SDISABLE0(x) ((x) << S_CPUCP15SDISABLE0)
+#define F_CPUCP15SDISABLE0    V_CPUCP15SDISABLE0(1U)
+
+#define A_ARM_CPU_CLUSTER_ID_AFF 0x47094
+
+#define S_CPUCLUSTERIDAFF2    8
+#define M_CPUCLUSTERIDAFF2    0xffU
+#define V_CPUCLUSTERIDAFF2(x) ((x) << S_CPUCLUSTERIDAFF2)
+#define G_CPUCLUSTERIDAFF2(x) (((x) >> S_CPUCLUSTERIDAFF2) & M_CPUCLUSTERIDAFF2)
+
+#define S_CPUCLUSTERIDAFF1    0
+#define M_CPUCLUSTERIDAFF1    0xffU
+#define V_CPUCLUSTERIDAFF1(x) ((x) << S_CPUCLUSTERIDAFF1)
+#define G_CPUCLUSTERIDAFF1(x) (((x) >> S_CPUCLUSTERIDAFF1) & M_CPUCLUSTERIDAFF1)
+
+#define A_ARM_CPU_CLK_CFG 0x47098
+
+#define S_CPUACINACTIVEM    1
+#define V_CPUACINACTIVEM(x) ((x) << S_CPUACINACTIVEM)
+#define F_CPUACINACTIVEM    V_CPUACINACTIVEM(1U)
+
+#define S_CPUACLKENM    0
+#define V_CPUACLKENM(x) ((x) << S_CPUACLKENM)
+#define F_CPUACLKENM    V_CPUACLKENM(1U)
+
+#define A_ARM_NVME_DB_EMU_INT_CAUSE 0x4709c
+
+#define S_INVALID_BRESP    3
+#define V_INVALID_BRESP(x) ((x) << S_INVALID_BRESP)
+#define F_INVALID_BRESP    V_INVALID_BRESP(1U)
+
+#define S_DATA_LEN_OF    2
+#define V_DATA_LEN_OF(x) ((x) << S_DATA_LEN_OF)
+#define F_DATA_LEN_OF    V_DATA_LEN_OF(1U)
+
+#define S_INVALID_EMU_ADDR    1
+#define V_INVALID_EMU_ADDR(x) ((x) << S_INVALID_EMU_ADDR)
+#define F_INVALID_EMU_ADDR    V_INVALID_EMU_ADDR(1U)
+
+#define S_INVALID_AXI_ADDR_CFG    0
+#define V_INVALID_AXI_ADDR_CFG(x) ((x) << S_INVALID_AXI_ADDR_CFG)
+#define F_INVALID_AXI_ADDR_CFG    V_INVALID_AXI_ADDR_CFG(1U)
+
+#define A_ARM_CS_RST 0x470c0
+
+#define S_ATCLKEN    9
+#define V_ATCLKEN(x) ((x) << S_ATCLKEN)
+#define F_ATCLKEN    V_ATCLKEN(1U)
+
+#define S_CXAPBICRSTN    8
+#define V_CXAPBICRSTN(x) ((x) << S_CXAPBICRSTN)
+#define F_CXAPBICRSTN    V_CXAPBICRSTN(1U)
+
+#define S_CSDBGEN    7
+#define V_CSDBGEN(x) ((x) << S_CSDBGEN)
+#define F_CSDBGEN    V_CSDBGEN(1U)
+
+#define S_JTAGNPOTRST    6
+#define V_JTAGNPOTRST(x) ((x) << S_JTAGNPOTRST)
+#define F_JTAGNPOTRST    V_JTAGNPOTRST(1U)
+
+#define S_JTAGNTRST    5
+#define V_JTAGNTRST(x) ((x) << S_JTAGNTRST)
+#define F_JTAGNTRST    V_JTAGNTRST(1U)
+
+#define S_PADDR31S0    4
+#define V_PADDR31S0(x) ((x) << S_PADDR31S0)
+#define F_PADDR31S0    V_PADDR31S0(1U)
+
+#define S_CTICLKEN    3
+#define V_CTICLKEN(x) ((x) << S_CTICLKEN)
+#define F_CTICLKEN    V_CTICLKEN(1U)
+
+#define S_PCLKENDBG    2
+#define V_PCLKENDBG(x) ((x) << S_PCLKENDBG)
+#define F_PCLKENDBG    V_PCLKENDBG(1U)
+
+#define S_CPU_NIDEN    1
+#define V_CPU_NIDEN(x) ((x) << S_CPU_NIDEN)
+#define F_CPU_NIDEN    V_CPU_NIDEN(1U)
+
+#define S_CPU_DBGEN    0
+#define V_CPU_DBGEN(x) ((x) << S_CPU_DBGEN)
+#define F_CPU_DBGEN    V_CPU_DBGEN(1U)
+
+#define A_ARM_CS_ADDRL 0x470c4
+#define A_ARM_CS_ADDRH 0x470c8
+#define A_ARM_CS_DFT_CONTROL 0x470cc
+
+#define S_DFTMBISTADDR    5
+#define M_DFTMBISTADDR    0x7ffU
+#define V_DFTMBISTADDR(x) ((x) << S_DFTMBISTADDR)
+#define G_DFTMBISTADDR(x) (((x) >> S_DFTMBISTADDR) & M_DFTMBISTADDR)
+
+#define S_DFTMTESTON    3
+#define V_DFTMTESTON(x) ((x) << S_DFTMTESTON)
+#define F_DFTMTESTON    V_DFTMTESTON(1U)
+
+#define S_DFTMBISTCE    2
+#define V_DFTMBISTCE(x) ((x) << S_DFTMBISTCE)
+#define F_DFTMBISTCE    V_DFTMBISTCE(1U)
+
+#define S_DFTMBITWR    1
+#define V_DFTMBITWR(x) ((x) << S_DFTMBITWR)
+#define F_DFTMBITWR    V_DFTMBITWR(1U)
+
+#define S_DFTSE    0
+#define V_DFTSE(x) ((x) << S_DFTSE)
+#define F_DFTSE    V_DFTSE(1U)
+
+#define A_ARM_CS_DFT_IN 0x470d0
+#define A_ARM_CS_DFT_OUT 0x470d4
+#define A_ARM_CPU_EVENT_I 0x47100
+
+#define S_CPUEVENTI    0
+#define V_CPUEVENTI(x) ((x) << S_CPUEVENTI)
+#define F_CPUEVENTI    V_CPUEVENTI(1U)
+
+#define A_ARM_CPU_EVENT_O 0x47104
+
+#define S_CPUEVENTO    0
+#define V_CPUEVENTO(x) ((x) << S_CPUEVENTO)
+#define F_CPUEVENTO    V_CPUEVENTO(1U)
+
+#define A_ARM_CPU_CLR_EXMON_REQ 0x47108
+
+#define S_CPUCLREXMONREQ    0
+#define V_CPUCLREXMONREQ(x) ((x) << S_CPUCLREXMONREQ)
+#define F_CPUCLREXMONREQ    V_CPUCLREXMONREQ(1U)
+
+#define A_ARM_CPU_CLR_EXMON_ACK 0x4710c
+
+#define S_CPUCLREXMONACK    0
+#define V_CPUCLREXMONACK(x) ((x) << S_CPUCLREXMONACK)
+#define F_CPUCLREXMONACK    V_CPUCLREXMONACK(1U)
+
+#define A_ARM_UART_MSTR_RXD 0x47110
+#define A_ARM_UART_MSTR_RXC 0x47114
+
+#define S_UART_MSTR_RXC    0
+#define V_UART_MSTR_RXC(x) ((x) << S_UART_MSTR_RXC)
+#define F_UART_MSTR_RXC    V_UART_MSTR_RXC(1U)
+
+#define A_ARM_UART_MSTR_TXD 0x47118
+#define A_ARM_UART_MSTR_TXC 0x4711c
+
+#define S_T7_INT    1
+#define V_T7_INT(x) ((x) << S_T7_INT)
+#define F_T7_INT    V_T7_INT(1U)
+
+#define S_UART_MSTC_TXC    0
+#define V_UART_MSTC_TXC(x) ((x) << S_UART_MSTC_TXC)
+#define F_UART_MSTC_TXC    V_UART_MSTC_TXC(1U)
+
+#define A_ARM_UART_SLV_SEL 0x47120
+
+#define S_UART_SLV_SEL    0
+#define V_UART_SLV_SEL(x) ((x) << S_UART_SLV_SEL)
+#define F_UART_SLV_SEL    V_UART_SLV_SEL(1U)
+
+#define A_ARM_CPU_PERIPH_BASE 0x47124
+#define A_ARM_PERR_INT_ENB2 0x47128
+#define A_ARM_PERR_ENABLE2 0x4712c
+#define A_ARM_UART_CONFIG 0x47130
+#define A_ARM_UART_STAT 0x47134
+
+#define S_RSV1    6
+#define M_RSV1    0x3ffffffU
+#define V_RSV1(x) ((x) << S_RSV1)
+#define G_RSV1(x) (((x) >> S_RSV1) & M_RSV1)
+
+#define S_RXFRMERR    5
+#define V_RXFRMERR(x) ((x) << S_RXFRMERR)
+#define F_RXFRMERR    V_RXFRMERR(1U)
+
+#define S_RXPARERR    4
+#define V_RXPARERR(x) ((x) << S_RXPARERR)
+#define F_RXPARERR    V_RXPARERR(1U)
+
+#define S_RXOVRN    3
+#define V_RXOVRN(x) ((x) << S_RXOVRN)
+#define F_RXOVRN    V_RXOVRN(1U)
+
+#define S_CTL_RXRDY    2
+#define V_CTL_RXRDY(x) ((x) << S_CTL_RXRDY)
+#define F_CTL_RXRDY    V_CTL_RXRDY(1U)
+
+#define S_TXOVRN    1
+#define V_TXOVRN(x) ((x) << S_TXOVRN)
+#define F_TXOVRN    V_TXOVRN(1U)
+
+#define S_CTL_TXRDY    0
+#define V_CTL_TXRDY(x) ((x) << S_CTL_TXRDY)
+#define F_CTL_TXRDY    V_CTL_TXRDY(1U)
+
+#define A_ARM_UART_TX_DATA 0x47138
+
+#define S_TX_DATA    0
+#define M_TX_DATA    0xffU
+#define V_TX_DATA(x) ((x) << S_TX_DATA)
+#define G_TX_DATA(x) (((x) >> S_TX_DATA) & M_TX_DATA)
+
+#define A_ARM_UART_RX_DATA 0x4713c
+
+#define S_RX_DATA    0
+#define M_RX_DATA    0xffU
+#define V_RX_DATA(x) ((x) << S_RX_DATA)
+#define G_RX_DATA(x) (((x) >> S_RX_DATA) & M_RX_DATA)
+
+#define A_ARM_UART_DBG0 0x47140
+#define A_ARM_UART_DBG1 0x47144
+#define A_ARM_UART_DBG2 0x47148
+#define A_ARM_UART_DBG3 0x4714c
+#define A_ARM_ARM_CPU_PC0 0x47150
+#define A_ARM_ARM_CPU_PC1 0x47154
+#define A_ARM_ARM_UART_INT_CAUSE 0x47158
+
+#define S_RX_FIFO_NOT_EMPTY    1
+#define V_RX_FIFO_NOT_EMPTY(x) ((x) << S_RX_FIFO_NOT_EMPTY)
+#define F_RX_FIFO_NOT_EMPTY    V_RX_FIFO_NOT_EMPTY(1U)
+
+#define S_TX_FIFO_EMPTY    0
+#define V_TX_FIFO_EMPTY(x) ((x) << S_TX_FIFO_EMPTY)
+#define F_TX_FIFO_EMPTY    V_TX_FIFO_EMPTY(1U)
+
+#define A_ARM_ARM_UART_INT_EN 0x4715c
+
+#define S_RX_FIFO_INT_NOT_EMPTY    1
+#define V_RX_FIFO_INT_NOT_EMPTY(x) ((x) << S_RX_FIFO_INT_NOT_EMPTY)
+#define F_RX_FIFO_INT_NOT_EMPTY    V_RX_FIFO_INT_NOT_EMPTY(1U)
+
+#define S_TX_FIFO_INT_EMPTY    0
+#define V_TX_FIFO_INT_EMPTY(x) ((x) << S_TX_FIFO_INT_EMPTY)
+#define F_TX_FIFO_INT_EMPTY    V_TX_FIFO_INT_EMPTY(1U)
+
+#define A_ARM_ARM_UART_GPIO_SEL 0x47160
+
+#define S_PC_SEL    1
+#define M_PC_SEL    0x7U
+#define V_PC_SEL(x) ((x) << S_PC_SEL)
+#define G_PC_SEL(x) (((x) >> S_PC_SEL) & M_PC_SEL)
+
+#define S_UART_GPIO_SEL    0
+#define V_UART_GPIO_SEL(x) ((x) << S_UART_GPIO_SEL)
+#define F_UART_GPIO_SEL    V_UART_GPIO_SEL(1U)
+
+#define A_ARM_ARM_SCRATCH_PAD0 0x47164
+#define A_ARM_ARM_SCRATCH_PAD1 0x47168
+#define A_ARM_ARM_SCRATCH_PAD2 0x4716c
+#define A_ARM_PERR_INT_CAUSE0 0x47170
+
+#define S_INIC_WRDATA_FIFO_PERR    31
+#define V_INIC_WRDATA_FIFO_PERR(x) ((x) << S_INIC_WRDATA_FIFO_PERR)
+#define F_INIC_WRDATA_FIFO_PERR    V_INIC_WRDATA_FIFO_PERR(1U)
+
+#define S_INIC_RDATA_FIFO_PERR    30
+#define V_INIC_RDATA_FIFO_PERR(x) ((x) << S_INIC_RDATA_FIFO_PERR)
+#define F_INIC_RDATA_FIFO_PERR    V_INIC_RDATA_FIFO_PERR(1U)
+
+#define S_MSI_MEM_PERR    29
+#define V_MSI_MEM_PERR(x) ((x) << S_MSI_MEM_PERR)
+#define F_MSI_MEM_PERR    V_MSI_MEM_PERR(1U)
+
+#define S_ARM_DB_SRAM_PERR    27
+#define M_ARM_DB_SRAM_PERR    0x3U
+#define V_ARM_DB_SRAM_PERR(x) ((x) << S_ARM_DB_SRAM_PERR)
+#define G_ARM_DB_SRAM_PERR(x) (((x) >> S_ARM_DB_SRAM_PERR) & M_ARM_DB_SRAM_PERR)
+
+#define S_EMMC_FIFOPARINT    26
+#define V_EMMC_FIFOPARINT(x) ((x) << S_EMMC_FIFOPARINT)
+#define F_EMMC_FIFOPARINT    V_EMMC_FIFOPARINT(1U)
+
+#define S_ICB_RAM_PERR    25
+#define V_ICB_RAM_PERR(x) ((x) << S_ICB_RAM_PERR)
+#define F_ICB_RAM_PERR    V_ICB_RAM_PERR(1U)
+
+#define S_MESS2AXI4_WRFIFO_PERR    24
+#define V_MESS2AXI4_WRFIFO_PERR(x) ((x) << S_MESS2AXI4_WRFIFO_PERR)
+#define F_MESS2AXI4_WRFIFO_PERR    V_MESS2AXI4_WRFIFO_PERR(1U)
+
+#define S_RC_WFIFO_OUTPERR    23
+#define V_RC_WFIFO_OUTPERR(x) ((x) << S_RC_WFIFO_OUTPERR)
+#define F_RC_WFIFO_OUTPERR    V_RC_WFIFO_OUTPERR(1U)
+
+#define S_RC_SRAM_PERR    21
+#define M_RC_SRAM_PERR    0x3U
+#define V_RC_SRAM_PERR(x) ((x) << S_RC_SRAM_PERR)
+#define G_RC_SRAM_PERR(x) (((x) >> S_RC_SRAM_PERR) & M_RC_SRAM_PERR)
+
+#define S_MSI_FIFO_PAR_ERR    20
+#define V_MSI_FIFO_PAR_ERR(x) ((x) << S_MSI_FIFO_PAR_ERR)
+#define F_MSI_FIFO_PAR_ERR    V_MSI_FIFO_PAR_ERR(1U)
+
+#define S_INIC2MA_INTFPERR    19
+#define V_INIC2MA_INTFPERR(x) ((x) << S_INIC2MA_INTFPERR)
+#define F_INIC2MA_INTFPERR    V_INIC2MA_INTFPERR(1U)
+
+#define S_RDATAFIFO0_PERR    18
+#define V_RDATAFIFO0_PERR(x) ((x) << S_RDATAFIFO0_PERR)
+#define F_RDATAFIFO0_PERR    V_RDATAFIFO0_PERR(1U)
+
+#define S_RDATAFIFO1_PERR    17
+#define V_RDATAFIFO1_PERR(x) ((x) << S_RDATAFIFO1_PERR)
+#define F_RDATAFIFO1_PERR    V_RDATAFIFO1_PERR(1U)
+
+#define S_WRDATAFIFO0_PERR    16
+#define V_WRDATAFIFO0_PERR(x) ((x) << S_WRDATAFIFO0_PERR)
+#define F_WRDATAFIFO0_PERR    V_WRDATAFIFO0_PERR(1U)
+
+#define S_WRDATAFIFO1_PERR    15
+#define V_WRDATAFIFO1_PERR(x) ((x) << S_WRDATAFIFO1_PERR)
+#define F_WRDATAFIFO1_PERR    V_WRDATAFIFO1_PERR(1U)
+
+#define S_WR512DATAFIFO0_PERR    14
+#define V_WR512DATAFIFO0_PERR(x) ((x) << S_WR512DATAFIFO0_PERR)
+#define F_WR512DATAFIFO0_PERR    V_WR512DATAFIFO0_PERR(1U)
+
+#define S_WR512DATAFIFO1_PERR    13
+#define V_WR512DATAFIFO1_PERR(x) ((x) << S_WR512DATAFIFO1_PERR)
+#define F_WR512DATAFIFO1_PERR    V_WR512DATAFIFO1_PERR(1U)
+
+#define S_ROBUFF_PARERR3    12
+#define V_ROBUFF_PARERR3(x) ((x) << S_ROBUFF_PARERR3)
+#define F_ROBUFF_PARERR3    V_ROBUFF_PARERR3(1U)
+
+#define S_ROBUFF_PARERR2    11
+#define V_ROBUFF_PARERR2(x) ((x) << S_ROBUFF_PARERR2)
+#define F_ROBUFF_PARERR2    V_ROBUFF_PARERR2(1U)
+
+#define S_ROBUFF_PARERR1    10
+#define V_ROBUFF_PARERR1(x) ((x) << S_ROBUFF_PARERR1)
+#define F_ROBUFF_PARERR1    V_ROBUFF_PARERR1(1U)
+
+#define S_ROBUFF_PARERR0    9
+#define V_ROBUFF_PARERR0(x) ((x) << S_ROBUFF_PARERR0)
+#define F_ROBUFF_PARERR0    V_ROBUFF_PARERR0(1U)
+
+#define S_MA2AXI_REQDATAPARERR    8
+#define V_MA2AXI_REQDATAPARERR(x) ((x) << S_MA2AXI_REQDATAPARERR)
+#define F_MA2AXI_REQDATAPARERR    V_MA2AXI_REQDATAPARERR(1U)
+
+#define S_MA2AXI_REQCTLPARERR    7
+#define V_MA2AXI_REQCTLPARERR(x) ((x) << S_MA2AXI_REQCTLPARERR)
+#define F_MA2AXI_REQCTLPARERR    V_MA2AXI_REQCTLPARERR(1U)
+
+#define S_MA_RSPPERR    6
+#define V_MA_RSPPERR(x) ((x) << S_MA_RSPPERR)
+#define F_MA_RSPPERR    V_MA_RSPPERR(1U)
+
+#define S_PCIE2MA_REQCTLPARERR    5
+#define V_PCIE2MA_REQCTLPARERR(x) ((x) << S_PCIE2MA_REQCTLPARERR)
+#define F_PCIE2MA_REQCTLPARERR    V_PCIE2MA_REQCTLPARERR(1U)
+
+#define S_PCIE2MA_REQDATAPARERR    4
+#define V_PCIE2MA_REQDATAPARERR(x) ((x) << S_PCIE2MA_REQDATAPARERR)
+#define F_PCIE2MA_REQDATAPARERR    V_PCIE2MA_REQDATAPARERR(1U)
+
+#define S_INIC2MA_REQCTLPARERR    3
+#define V_INIC2MA_REQCTLPARERR(x) ((x) << S_INIC2MA_REQCTLPARERR)
+#define F_INIC2MA_REQCTLPARERR    V_INIC2MA_REQCTLPARERR(1U)
+
+#define S_INIC2MA_REQDATAPARERR    2
+#define V_INIC2MA_REQDATAPARERR(x) ((x) << S_INIC2MA_REQDATAPARERR)
+#define F_INIC2MA_REQDATAPARERR    V_INIC2MA_REQDATAPARERR(1U)
+
+#define S_MA_RSPUE    1
+#define V_MA_RSPUE(x) ((x) << S_MA_RSPUE)
+#define F_MA_RSPUE    V_MA_RSPUE(1U)
+
+#define S_APB2PL_RSPDATAPERR    0
+#define V_APB2PL_RSPDATAPERR(x) ((x) << S_APB2PL_RSPDATAPERR)
+#define F_APB2PL_RSPDATAPERR    V_APB2PL_RSPDATAPERR(1U)
+
+#define A_ARM_PERR_INT_ENB0 0x47174
+#define A_ARM_SCRATCH_PAD3 0x47178
+
+#define S_ECO_43187    31
+#define V_ECO_43187(x) ((x) << S_ECO_43187)
+#define F_ECO_43187    V_ECO_43187(1U)
+
+#define S_TIMER_SEL    28
+#define M_TIMER_SEL    0x7U
+#define V_TIMER_SEL(x) ((x) << S_TIMER_SEL)
+#define G_TIMER_SEL(x) (((x) >> S_TIMER_SEL) & M_TIMER_SEL)
+
+#define S_TIMER    4
+#define M_TIMER    0xffffffU
+#define V_TIMER(x) ((x) << S_TIMER)
+#define G_TIMER(x) (((x) >> S_TIMER) & M_TIMER)
+
+#define S_T7_1_INT    0
+#define M_T7_1_INT    0x3U
+#define V_T7_1_INT(x) ((x) << S_T7_1_INT)
+#define G_T7_1_INT(x) (((x) >> S_T7_1_INT) & M_T7_1_INT)
+
+#define A_ARM_PERR_INT_CAUSE2 0x4717c
+
+#define S_INIC_WSTRB_FIFO_PERR    31
+#define V_INIC_WSTRB_FIFO_PERR(x) ((x) << S_INIC_WSTRB_FIFO_PERR)
+#define F_INIC_WSTRB_FIFO_PERR    V_INIC_WSTRB_FIFO_PERR(1U)
+
+#define S_INIC_BID_FIFO_PERR    30
+#define V_INIC_BID_FIFO_PERR(x) ((x) << S_INIC_BID_FIFO_PERR)
+#define F_INIC_BID_FIFO_PERR    V_INIC_BID_FIFO_PERR(1U)
+
+#define S_CC_SRAM_PKA_PERR    29
+#define V_CC_SRAM_PKA_PERR(x) ((x) << S_CC_SRAM_PKA_PERR)
+#define F_CC_SRAM_PKA_PERR    V_CC_SRAM_PKA_PERR(1U)
+
+#define S_CC_SRAM_SEC_PERR    28
+#define V_CC_SRAM_SEC_PERR(x) ((x) << S_CC_SRAM_SEC_PERR)
+#define F_CC_SRAM_SEC_PERR    V_CC_SRAM_SEC_PERR(1U)
+
+#define S_MESS2AXI4_PARERR    27
+#define V_MESS2AXI4_PARERR(x) ((x) << S_MESS2AXI4_PARERR)
+#define F_MESS2AXI4_PARERR    V_MESS2AXI4_PARERR(1U)
+
+#define S_CCI2INIC_INTF_PARERR    26
+#define V_CCI2INIC_INTF_PARERR(x) ((x) << S_CCI2INIC_INTF_PARERR)
+#define F_CCI2INIC_INTF_PARERR    V_CCI2INIC_INTF_PARERR(1U)
+
+#define A_ARM_MA2AXI_AW_ATTR 0x47180
+
+#define S_AWLOCKR1    29
+#define V_AWLOCKR1(x) ((x) << S_AWLOCKR1)
+#define F_AWLOCKR1    V_AWLOCKR1(1U)
+
+#define S_AWCACHER1    25
+#define M_AWCACHER1    0xfU
+#define V_AWCACHER1(x) ((x) << S_AWCACHER1)
+#define G_AWCACHER1(x) (((x) >> S_AWCACHER1) & M_AWCACHER1)
+
+#define S_AWPROTR1    21
+#define M_AWPROTR1    0xfU
+#define V_AWPROTR1(x) ((x) << S_AWPROTR1)
+#define G_AWPROTR1(x) (((x) >> S_AWPROTR1) & M_AWPROTR1)
+
+#define S_AWSNOOPR1    18
+#define M_AWSNOOPR1    0x7U
+#define V_AWSNOOPR1(x) ((x) << S_AWSNOOPR1)
+#define G_AWSNOOPR1(x) (((x) >> S_AWSNOOPR1) & M_AWSNOOPR1)
+
+#define S_AWDOMAINR1    16
+#define M_AWDOMAINR1    0x3U
+#define V_AWDOMAINR1(x) ((x) << S_AWDOMAINR1)
+#define G_AWDOMAINR1(x) (((x) >> S_AWDOMAINR1) & M_AWDOMAINR1)
+
+#define S_AWLOCKR0    13
+#define V_AWLOCKR0(x) ((x) << S_AWLOCKR0)
+#define F_AWLOCKR0    V_AWLOCKR0(1U)
+
+#define S_AWCACHER0    9
+#define M_AWCACHER0    0xfU
+#define V_AWCACHER0(x) ((x) << S_AWCACHER0)
+#define G_AWCACHER0(x) (((x) >> S_AWCACHER0) & M_AWCACHER0)
+
+#define S_AWPROTR0    5
+#define M_AWPROTR0    0xfU
+#define V_AWPROTR0(x) ((x) << S_AWPROTR0)
+#define G_AWPROTR0(x) (((x) >> S_AWPROTR0) & M_AWPROTR0)
+
+#define S_AWSNOOPR0    2
+#define M_AWSNOOPR0    0x7U
+#define V_AWSNOOPR0(x) ((x) << S_AWSNOOPR0)
+#define G_AWSNOOPR0(x) (((x) >> S_AWSNOOPR0) & M_AWSNOOPR0)
+
+#define S_AWDOMAINR0    0
+#define M_AWDOMAINR0    0x3U
+#define V_AWDOMAINR0(x) ((x) << S_AWDOMAINR0)
+#define G_AWDOMAINR0(x) (((x) >> S_AWDOMAINR0) & M_AWDOMAINR0)
+
+#define A_ARM_MA2AXI_AR_ATTR 0x47184
+
+#define S_ARLOCKR1    29
+#define V_ARLOCKR1(x) ((x) << S_ARLOCKR1)
+#define F_ARLOCKR1    V_ARLOCKR1(1U)
+
+#define S_ARCACHER1    25
+#define M_ARCACHER1    0xfU
+#define V_ARCACHER1(x) ((x) << S_ARCACHER1)
+#define G_ARCACHER1(x) (((x) >> S_ARCACHER1) & M_ARCACHER1)
+
+#define S_ARPROTR1    21
+#define M_ARPROTR1    0xfU
+#define V_ARPROTR1(x) ((x) << S_ARPROTR1)
+#define G_ARPROTR1(x) (((x) >> S_ARPROTR1) & M_ARPROTR1)
+
+#define S_ARSNOOPR1    18
+#define M_ARSNOOPR1    0x7U
+#define V_ARSNOOPR1(x) ((x) << S_ARSNOOPR1)
+#define G_ARSNOOPR1(x) (((x) >> S_ARSNOOPR1) & M_ARSNOOPR1)
+
+#define S_ARDOMAINR1    16
+#define M_ARDOMAINR1    0x3U
+#define V_ARDOMAINR1(x) ((x) << S_ARDOMAINR1)
+#define G_ARDOMAINR1(x) (((x) >> S_ARDOMAINR1) & M_ARDOMAINR1)
+
+#define S_ARLOCKR0    13
+#define V_ARLOCKR0(x) ((x) << S_ARLOCKR0)
+#define F_ARLOCKR0    V_ARLOCKR0(1U)
+
+#define S_ARCACHER0    9
+#define M_ARCACHER0    0xfU
+#define V_ARCACHER0(x) ((x) << S_ARCACHER0)
+#define G_ARCACHER0(x) (((x) >> S_ARCACHER0) & M_ARCACHER0)
+
+#define S_ARPROTR0    5
+#define M_ARPROTR0    0xfU
+#define V_ARPROTR0(x) ((x) << S_ARPROTR0)
+#define G_ARPROTR0(x) (((x) >> S_ARPROTR0) & M_ARPROTR0)
+
+#define S_ARSNOOPR0    2
+#define M_ARSNOOPR0    0x7U
+#define V_ARSNOOPR0(x) ((x) << S_ARSNOOPR0)
+#define G_ARSNOOPR0(x) (((x) >> S_ARSNOOPR0) & M_ARSNOOPR0)
+
+#define S_ARDOMAINR0    0
+#define M_ARDOMAINR0    0x3U
+#define V_ARDOMAINR0(x) ((x) << S_ARDOMAINR0)
+#define G_ARDOMAINR0(x) (((x) >> S_ARDOMAINR0) & M_ARDOMAINR0)
+
+#define A_ARM_MA2AXI_SNOOP_RGN 0x47188
+
+#define S_SNOOP_END    16
+#define M_SNOOP_END    0xffffU
+#define V_SNOOP_END(x) ((x) << S_SNOOP_END)
+#define G_SNOOP_END(x) (((x) >> S_SNOOP_END) & M_SNOOP_END)
+
+#define S_SNOOP_START    0
+#define M_SNOOP_START    0xffffU
+#define V_SNOOP_START(x) ((x) << S_SNOOP_START)
+#define G_SNOOP_START(x) (((x) >> S_SNOOP_START) & M_SNOOP_START)
+
+#define A_ARM_PERIPHERAL_INT_CAUSE 0x4718c
+
+#define S_TIMER_INT    5
+#define V_TIMER_INT(x) ((x) << S_TIMER_INT)
+#define F_TIMER_INT    V_TIMER_INT(1U)
+
+#define S_NVME_INT    4
+#define V_NVME_INT(x) ((x) << S_NVME_INT)
+#define F_NVME_INT    V_NVME_INT(1U)
+
+#define S_EMMC_WAKEUP_INT    3
+#define V_EMMC_WAKEUP_INT(x) ((x) << S_EMMC_WAKEUP_INT)
+#define F_EMMC_WAKEUP_INT    V_EMMC_WAKEUP_INT(1U)
+
+#define S_EMMC_INT    2
+#define V_EMMC_INT(x) ((x) << S_EMMC_INT)
+#define F_EMMC_INT    V_EMMC_INT(1U)
+
+#define S_USB_MC_INT    1
+#define V_USB_MC_INT(x) ((x) << S_USB_MC_INT)
+#define F_USB_MC_INT    V_USB_MC_INT(1U)
+
+#define S_USB_DMA_INT    0
+#define V_USB_DMA_INT(x) ((x) << S_USB_DMA_INT)
+#define F_USB_DMA_INT    V_USB_DMA_INT(1U)
+
+#define A_ARM_SCRATCH_PAD4 0x47190
+
+#define S_PAD4    15
+#define M_PAD4    0x1ffffU
+#define V_PAD4(x) ((x) << S_PAD4)
+#define G_PAD4(x) (((x) >> S_PAD4) & M_PAD4)
+
+#define S_ARM_DB_CNT    0
+#define M_ARM_DB_CNT    0x7fffU
+#define V_ARM_DB_CNT(x) ((x) << S_ARM_DB_CNT)
+#define G_ARM_DB_CNT(x) (((x) >> S_ARM_DB_CNT) & M_ARM_DB_CNT)
+
+#define A_ARM_SCRATCH_PAD5 0x47194
+#define A_ARM_SCRATCH_PAD6 0x47198
+#define A_ARM_SCRATCH_PAD7 0x4719c
+#define A_ARM_NVME_DB_EMU_INDEX 0x471a0
+#define A_ARM_NVME_DB_EMU_REGION_CTL 0x471a4
+
+#define S_WINDOW_EN    4
+#define V_WINDOW_EN(x) ((x) << S_WINDOW_EN)
+#define F_WINDOW_EN    V_WINDOW_EN(1U)
+
+#define S_RGN2_INT_EN    3
+#define V_RGN2_INT_EN(x) ((x) << S_RGN2_INT_EN)
+#define F_RGN2_INT_EN    V_RGN2_INT_EN(1U)
+
+#define S_RGN1_INT_EN    2
+#define V_RGN1_INT_EN(x) ((x) << S_RGN1_INT_EN)
+#define F_RGN1_INT_EN    V_RGN1_INT_EN(1U)
+
+#define S_QUEUE_EN    1
+#define V_QUEUE_EN(x) ((x) << S_QUEUE_EN)
+#define F_QUEUE_EN    V_QUEUE_EN(1U)
+
+#define S_RGN0_INT_EN    0
+#define V_RGN0_INT_EN(x) ((x) << S_RGN0_INT_EN)
+#define F_RGN0_INT_EN    V_RGN0_INT_EN(1U)
+
+#define A_ARM_NVME_DB_EMU_DEVICE_CTL 0x471a8
+
+#define S_DEVICE_SIZE    8
+#define M_DEVICE_SIZE    0xfU
+#define V_DEVICE_SIZE(x) ((x) << S_DEVICE_SIZE)
+#define G_DEVICE_SIZE(x) (((x) >> S_DEVICE_SIZE) & M_DEVICE_SIZE)
+
+#define S_RGN1_SIZE    4
+#define M_RGN1_SIZE    0xfU
+#define V_RGN1_SIZE(x) ((x) << S_RGN1_SIZE)
+#define G_RGN1_SIZE(x) (((x) >> S_RGN1_SIZE) & M_RGN1_SIZE)
+
+#define S_RGN0_SIZE    0
+#define M_RGN0_SIZE    0xfU
+#define V_RGN0_SIZE(x) ((x) << S_RGN0_SIZE)
+#define G_RGN0_SIZE(x) (((x) >> S_RGN0_SIZE) & M_RGN0_SIZE)
+
+#define A_ARM_NVME_DB_EMU_WINDOW_START_ADDR 0x471b0
+
+#define S_T7_4_ADDR    0
+#define M_T7_4_ADDR    0xfffffffU
+#define V_T7_4_ADDR(x) ((x) << S_T7_4_ADDR)
+#define G_T7_4_ADDR(x) (((x) >> S_T7_4_ADDR) & M_T7_4_ADDR)
+
+#define A_ARM_NVME_DB_EMU_WINDOW_END_ADDR 0x471b4
+#define A_ARM_NVME_DB_EMU_QBASE_ADDR 0x471b8
+#define A_ARM_NVME_DB_EMU_QUEUE_CID 0x471bc
+
+#define S_T7_CID    0
+#define M_T7_CID    0x1ffffU
+#define V_T7_CID(x) ((x) << S_T7_CID)
+#define G_T7_CID(x) (((x) >> S_T7_CID) & M_T7_CID)
+
+#define A_ARM_NVME_DB_EMU_QUEUE_CTL 0x471c0
+
+#define S_INT_EN    27
+#define V_INT_EN(x) ((x) << S_INT_EN)
+#define F_INT_EN    V_INT_EN(1U)
+
+#define S_THRESHOLD    10
+#define M_THRESHOLD    0x1ffffU
+#define V_THRESHOLD(x) ((x) << S_THRESHOLD)
+#define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
+
+#define S_T7_1_SIZE    0
+#define M_T7_1_SIZE    0x3ffU
+#define V_T7_1_SIZE(x) ((x) << S_T7_1_SIZE)
+#define G_T7_1_SIZE(x) (((x) >> S_T7_1_SIZE) & M_T7_1_SIZE)
+
+#define A_ARM_NVME_DB_EMU_MSIX_ADDR_L 0x471c4
+#define A_ARM_NVME_DB_EMU_MSIX_ADDR_H 0x471c8
+#define A_ARM_NVME_DB_EMU_MSIX_OFFSET 0x471cc
+#define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_L 0x471d0
+#define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_H 0x471d4
+#define A_ARM_NVME_DB_EMU_QUEUE_MSIX_OFFSET 0x471d8
+#define A_ARM_CERR_INT_CAUSE0 0x471dc
+
+#define S_WRDATA_FIFO0_CERR    31
+#define V_WRDATA_FIFO0_CERR(x) ((x) << S_WRDATA_FIFO0_CERR)
+#define F_WRDATA_FIFO0_CERR    V_WRDATA_FIFO0_CERR(1U)
+
+#define S_WRDATA_FIFO1_CERR    30
+#define V_WRDATA_FIFO1_CERR(x) ((x) << S_WRDATA_FIFO1_CERR)
+#define F_WRDATA_FIFO1_CERR    V_WRDATA_FIFO1_CERR(1U)
+
+#define S_WR512DATAFIFO0_CERR    29
+#define V_WR512DATAFIFO0_CERR(x) ((x) << S_WR512DATAFIFO0_CERR)
+#define F_WR512DATAFIFO0_CERR    V_WR512DATAFIFO0_CERR(1U)
+
+#define S_WR512DATAFIFO1_CERR    28
+#define V_WR512DATAFIFO1_CERR(x) ((x) << S_WR512DATAFIFO1_CERR)
+#define F_WR512DATAFIFO1_CERR    V_WR512DATAFIFO1_CERR(1U)
+
+#define S_RDATAFIFO0_CERR    27
+#define V_RDATAFIFO0_CERR(x) ((x) << S_RDATAFIFO0_CERR)
+#define F_RDATAFIFO0_CERR    V_RDATAFIFO0_CERR(1U)
+
+#define S_RDATAFIFO1_CERR    26
+#define V_RDATAFIFO1_CERR(x) ((x) << S_RDATAFIFO1_CERR)
+#define F_RDATAFIFO1_CERR    V_RDATAFIFO1_CERR(1U)
+
+#define S_ROBUFF_CORERR0    25
+#define V_ROBUFF_CORERR0(x) ((x) << S_ROBUFF_CORERR0)
+#define F_ROBUFF_CORERR0    V_ROBUFF_CORERR0(1U)
+
+#define S_ROBUFF_CORERR1    24
+#define V_ROBUFF_CORERR1(x) ((x) << S_ROBUFF_CORERR1)
+#define F_ROBUFF_CORERR1    V_ROBUFF_CORERR1(1U)
+
+#define S_ROBUFF_CORERR2    23
+#define V_ROBUFF_CORERR2(x) ((x) << S_ROBUFF_CORERR2)
+#define F_ROBUFF_CORERR2    V_ROBUFF_CORERR2(1U)
+
+#define S_ROBUFF_CORERR3    22
+#define V_ROBUFF_CORERR3(x) ((x) << S_ROBUFF_CORERR3)
+#define F_ROBUFF_CORERR3    V_ROBUFF_CORERR3(1U)
+
+#define S_MA2AXI_RSPDATACORERR    21
+#define V_MA2AXI_RSPDATACORERR(x) ((x) << S_MA2AXI_RSPDATACORERR)
+#define F_MA2AXI_RSPDATACORERR    V_MA2AXI_RSPDATACORERR(1U)
+
+#define S_RC_SRAM_CERR    19
+#define M_RC_SRAM_CERR    0x3U
+#define V_RC_SRAM_CERR(x) ((x) << S_RC_SRAM_CERR)
+#define G_RC_SRAM_CERR(x) (((x) >> S_RC_SRAM_CERR) & M_RC_SRAM_CERR)
+
+#define S_RC_WFIFO_OUTCERR    18
+#define V_RC_WFIFO_OUTCERR(x) ((x) << S_RC_WFIFO_OUTCERR)
+#define F_RC_WFIFO_OUTCERR    V_RC_WFIFO_OUTCERR(1U)
+
+#define S_RC_RSPFIFO_CERR    17
+#define V_RC_RSPFIFO_CERR(x) ((x) << S_RC_RSPFIFO_CERR)
+#define F_RC_RSPFIFO_CERR    V_RC_RSPFIFO_CERR(1U)
+
+#define S_MSI_MEM_CERR    16
+#define V_MSI_MEM_CERR(x) ((x) << S_MSI_MEM_CERR)
+#define F_MSI_MEM_CERR    V_MSI_MEM_CERR(1U)
+
+#define S_INIC_WRDATA_FIFO_CERR    15
+#define V_INIC_WRDATA_FIFO_CERR(x) ((x) << S_INIC_WRDATA_FIFO_CERR)
+#define F_INIC_WRDATA_FIFO_CERR    V_INIC_WRDATA_FIFO_CERR(1U)
+
+#define S_INIC_RDATAFIFO_CERR    14
+#define V_INIC_RDATAFIFO_CERR(x) ((x) << S_INIC_RDATAFIFO_CERR)
+#define F_INIC_RDATAFIFO_CERR    V_INIC_RDATAFIFO_CERR(1U)
+
+#define S_ARM_DB_SRAM_CERR    12
+#define M_ARM_DB_SRAM_CERR    0x3U
+#define V_ARM_DB_SRAM_CERR(x) ((x) << S_ARM_DB_SRAM_CERR)
+#define G_ARM_DB_SRAM_CERR(x) (((x) >> S_ARM_DB_SRAM_CERR) & M_ARM_DB_SRAM_CERR)
+
+#define S_ICB_RAM_CERR    11
+#define V_ICB_RAM_CERR(x) ((x) << S_ICB_RAM_CERR)
+#define F_ICB_RAM_CERR    V_ICB_RAM_CERR(1U)
+
+#define S_CC_SRAM_PKA_CERR    10
+#define V_CC_SRAM_PKA_CERR(x) ((x) << S_CC_SRAM_PKA_CERR)
+#define F_CC_SRAM_PKA_CERR    V_CC_SRAM_PKA_CERR(1U)
+
+#define S_CC_SRAM_SEC_CERR    9
+#define V_CC_SRAM_SEC_CERR(x) ((x) << S_CC_SRAM_SEC_CERR)
+#define F_CC_SRAM_SEC_CERR    V_CC_SRAM_SEC_CERR(1U)
+
+#define A_ARM_NVME_DB_EMU_QUEUE_CTL_2 0x471e0
+
+#define S_INTERRUPT_CLEAR    0
+#define V_INTERRUPT_CLEAR(x) ((x) << S_INTERRUPT_CLEAR)
+#define F_INTERRUPT_CLEAR    V_INTERRUPT_CLEAR(1U)
+
+#define A_ARM_PERIPHERAL_INT_ENB 0x471e4
+#define A_ARM_CERR_INT_ENB0 0x471e8
+#define A_ARM_CPU_DBG_ROM_ADDR0 0x47200
+
+#define S_CPUDBGROMADDR0    0
+#define M_CPUDBGROMADDR0    0xfffffU
+#define V_CPUDBGROMADDR0(x) ((x) << S_CPUDBGROMADDR0)
+#define G_CPUDBGROMADDR0(x) (((x) >> S_CPUDBGROMADDR0) & M_CPUDBGROMADDR0)
+
+#define A_ARM_CPU_DBG_ROM_ADDR1 0x47204
+
+#define S_CPUDBGROMADDR1    0
+#define M_CPUDBGROMADDR1    0x3ffU
+#define V_CPUDBGROMADDR1(x) ((x) << S_CPUDBGROMADDR1)
+#define G_CPUDBGROMADDR1(x) (((x) >> S_CPUDBGROMADDR1) & M_CPUDBGROMADDR1)
+
+#define A_ARM_CPU_DBG_ROM_ADDR_VALID 0x47208
+
+#define S_CPUDBGROMADDRVALID    0
+#define V_CPUDBGROMADDRVALID(x) ((x) << S_CPUDBGROMADDRVALID)
+#define F_CPUDBGROMADDRVALID    V_CPUDBGROMADDRVALID(1U)
+
+#define A_ARM_PERR_ENABLE0 0x4720c
+#define A_ARM_SRAM2_WRITE_DATA3 0x47210
+#define A_ARM_SRAM2_READ_DATA3 0x4721c
+#define A_ARM_CPU_DFT_CFG 0x47220
+
+#define S_CPUMBISTREQ    11
+#define V_CPUMBISTREQ(x) ((x) << S_CPUMBISTREQ)
+#define F_CPUMBISTREQ    V_CPUMBISTREQ(1U)
+
+#define S_CPUMBISTRSTN    10
+#define V_CPUMBISTRSTN(x) ((x) << S_CPUMBISTRSTN)
+#define F_CPUMBISTRSTN    V_CPUMBISTRSTN(1U)
+
+#define S_CPUDFTDFTSE    9
+#define V_CPUDFTDFTSE(x) ((x) << S_CPUDFTDFTSE)
+#define F_CPUDFTDFTSE    V_CPUDFTDFTSE(1U)
+
+#define S_CPUDFTRSTDISABLE    8
+#define V_CPUDFTRSTDISABLE(x) ((x) << S_CPUDFTRSTDISABLE)
+#define F_CPUDFTRSTDISABLE    V_CPUDFTRSTDISABLE(1U)
+
+#define S_CPUDFTRAMDISABLE    7
+#define V_CPUDFTRAMDISABLE(x) ((x) << S_CPUDFTRAMDISABLE)
+#define F_CPUDFTRAMDISABLE    V_CPUDFTRAMDISABLE(1U)
+
+#define S_CPUDFTMCPDISABLE    6
+#define V_CPUDFTMCPDISABLE(x) ((x) << S_CPUDFTMCPDISABLE)
+#define F_CPUDFTMCPDISABLE    V_CPUDFTMCPDISABLE(1U)
+
+#define S_CPUDFTL2CLKDISABLE    5
+#define V_CPUDFTL2CLKDISABLE(x) ((x) << S_CPUDFTL2CLKDISABLE)
+#define F_CPUDFTL2CLKDISABLE    V_CPUDFTL2CLKDISABLE(1U)
+
+#define S_CPUDFTCLKDISABLE3    4
+#define V_CPUDFTCLKDISABLE3(x) ((x) << S_CPUDFTCLKDISABLE3)
+#define F_CPUDFTCLKDISABLE3    V_CPUDFTCLKDISABLE3(1U)
+
+#define S_CPUDFTCLKDISABLE2    3
+#define V_CPUDFTCLKDISABLE2(x) ((x) << S_CPUDFTCLKDISABLE2)
+#define F_CPUDFTCLKDISABLE2    V_CPUDFTCLKDISABLE2(1U)
+
+#define S_CPUDFTCLKDISABLE1    2
+#define V_CPUDFTCLKDISABLE1(x) ((x) << S_CPUDFTCLKDISABLE1)
+#define F_CPUDFTCLKDISABLE1    V_CPUDFTCLKDISABLE1(1U)
+
+#define S_CPUDFTCLKDISABLE0    1
+#define V_CPUDFTCLKDISABLE0(x) ((x) << S_CPUDFTCLKDISABLE0)
+#define F_CPUDFTCLKDISABLE0    V_CPUDFTCLKDISABLE0(1U)
+
+#define S_CPUDFTCLKBYPASS    0
+#define V_CPUDFTCLKBYPASS(x) ((x) << S_CPUDFTCLKBYPASS)
+#define F_CPUDFTCLKBYPASS    V_CPUDFTCLKBYPASS(1U)
+
+#define A_ARM_APB_CFG 0x47224
+
+#define S_APB_CFG    0
+#define M_APB_CFG    0x3ffffU
+#define V_APB_CFG(x) ((x) << S_APB_CFG)
+#define G_APB_CFG(x) (((x) >> S_APB_CFG) & M_APB_CFG)
+
+#define A_ARM_EMMC_BUFS 0x47228
+
+#define S_EMMC_BUFS_OEN    2
+#define M_EMMC_BUFS_OEN    0x3U
+#define V_EMMC_BUFS_OEN(x) ((x) << S_EMMC_BUFS_OEN)
+#define G_EMMC_BUFS_OEN(x) (((x) >> S_EMMC_BUFS_OEN) & M_EMMC_BUFS_OEN)
+
+#define S_EMMC_BUFS_I    0
+#define M_EMMC_BUFS_I    0x3U
+#define V_EMMC_BUFS_I(x) ((x) << S_EMMC_BUFS_I)
+#define G_EMMC_BUFS_I(x) (((x) >> S_EMMC_BUFS_I) & M_EMMC_BUFS_I)
+
+#define A_ARM_SWP_EN 0x4722c
+#define A_ARM_ADB_PWR_DWN_REQ_N 0x47230
+
+#define S_ADBPWRDWNREQN    0
+#define V_ADBPWRDWNREQN(x) ((x) << S_ADBPWRDWNREQN)
+#define F_ADBPWRDWNREQN    V_ADBPWRDWNREQN(1U)
+
+#define A_ARM_GIC_USER 0x47238
+
+#define S_CPU_GIC_USER    0
+#define M_CPU_GIC_USER    0x7fU
+#define V_CPU_GIC_USER(x) ((x) << S_CPU_GIC_USER)
+#define G_CPU_GIC_USER(x) (((x) >> S_CPU_GIC_USER) & M_CPU_GIC_USER)
+
+#define A_ARM_DBPROC_SRAM_TH_ADDR 0x47240
+
+#define S_DBPROC_TH_ADDR    0
+#define M_DBPROC_TH_ADDR    0x1ffU
+#define V_DBPROC_TH_ADDR(x) ((x) << S_DBPROC_TH_ADDR)
+#define G_DBPROC_TH_ADDR(x) (((x) >> S_DBPROC_TH_ADDR) & M_DBPROC_TH_ADDR)
+
+#define A_ARM_DBPROC_SRAM_TH_READ_DATA0 0x47244
+#define A_ARM_DBPROC_SRAM_TH_READ_DATA1 0x47248
+#define A_ARM_DBPROC_SRAM_TH_READ_DATA2 0x4724c
+#define A_ARM_DBPROC_SRAM_TH_READ_DATA3 0x47250
+#define A_ARM_DBPROC_SRAM_TH_WR_DATA0 0x47254
+#define A_ARM_DBPROC_SRAM_TH_WR_DATA1 0x47258
+#define A_ARM_DBPROC_SRAM_TH_WR_DATA2 0x4725c
+#define A_ARM_DBPROC_SRAM_TH_WR_DATA3 0x47260
+#define A_ARM_SWP_EN_2 0x47264
+
+#define S_SWP_EN_2    0
+#define M_SWP_EN_2    0x3U
+#define V_SWP_EN_2(x) ((x) << S_SWP_EN_2)
+#define G_SWP_EN_2(x) (((x) >> S_SWP_EN_2) & M_SWP_EN_2)
+
+#define A_ARM_GIC_ERR 0x47268
+
+#define S_ECC_FATAL    1
+#define V_ECC_FATAL(x) ((x) << S_ECC_FATAL)
+#define F_ECC_FATAL    V_ECC_FATAL(1U)
+
+#define S_AXIM_ERR    0
+#define V_AXIM_ERR(x) ((x) << S_AXIM_ERR)
+#define F_AXIM_ERR    V_AXIM_ERR(1U)
+
+#define A_ARM_CPU_STAT 0x4726c
+
+#define S_CPU_L2_QACTIVE    12
+#define V_CPU_L2_QACTIVE(x) ((x) << S_CPU_L2_QACTIVE)
+#define F_CPU_L2_QACTIVE    V_CPU_L2_QACTIVE(1U)
+
+#define S_WAKEUPM_O_ADB    11
+#define V_WAKEUPM_O_ADB(x) ((x) << S_WAKEUPM_O_ADB)
+#define F_WAKEUPM_O_ADB    V_WAKEUPM_O_ADB(1U)
+
+#define S_PWRQACTIVEM_ADB    10
+#define V_PWRQACTIVEM_ADB(x) ((x) << S_PWRQACTIVEM_ADB)
+#define F_PWRQACTIVEM_ADB    V_PWRQACTIVEM_ADB(1U)
+
+#define S_CLKQACTIVEM_ADB    9
+#define V_CLKQACTIVEM_ADB(x) ((x) << S_CLKQACTIVEM_ADB)
+#define F_CLKQACTIVEM_ADB    V_CLKQACTIVEM_ADB(1U)
+
+#define S_CLKQDENYM_ADB    8
+#define V_CLKQDENYM_ADB(x) ((x) << S_CLKQDENYM_ADB)
+#define F_CLKQDENYM_ADB    V_CLKQDENYM_ADB(1U)
+
+#define S_CLKQACCEPTNM_ADB    7
+#define V_CLKQACCEPTNM_ADB(x) ((x) << S_CLKQACCEPTNM_ADB)
+#define F_CLKQACCEPTNM_ADB    V_CLKQACCEPTNM_ADB(1U)
+
+#define S_WAKEUPS_O_ADB    6
+#define V_WAKEUPS_O_ADB(x) ((x) << S_WAKEUPS_O_ADB)
+#define F_WAKEUPS_O_ADB    V_WAKEUPS_O_ADB(1U)
+
+#define S_PWRQACTIVES_ADB    5
+#define V_PWRQACTIVES_ADB(x) ((x) << S_PWRQACTIVES_ADB)
+#define F_PWRQACTIVES_ADB    V_PWRQACTIVES_ADB(1U)
+
+#define S_CLKQACTIVES_ADB    4
+#define V_CLKQACTIVES_ADB(x) ((x) << S_CLKQACTIVES_ADB)
+#define F_CLKQACTIVES_ADB    V_CLKQACTIVES_ADB(1U)
+
+#define S_CLKQDENYS_ADB    3
+#define V_CLKQDENYS_ADB(x) ((x) << S_CLKQDENYS_ADB)
+#define F_CLKQDENYS_ADB    V_CLKQDENYS_ADB(1U)
+
+#define S_CLKQACCEPTNS_ADB    2
+#define V_CLKQACCEPTNS_ADB(x) ((x) << S_CLKQACCEPTNS_ADB)
+#define F_CLKQACCEPTNS_ADB    V_CLKQACCEPTNS_ADB(1U)
+
+#define S_PWRQDENYS_ADB    1
+#define V_PWRQDENYS_ADB(x) ((x) << S_PWRQDENYS_ADB)
+#define F_PWRQDENYS_ADB    V_PWRQDENYS_ADB(1U)
+
+#define S_PWRQACCEPTNS_ADB    0
+#define V_PWRQACCEPTNS_ADB(x) ((x) << S_PWRQACCEPTNS_ADB)
+#define F_PWRQACCEPTNS_ADB    V_PWRQACCEPTNS_ADB(1U)
+
+#define A_ARM_DEBUG_INT_WRITE_DATA 0x47270
+
+#define S_DEBUG_INT_WRITE_DATA    0
+#define M_DEBUG_INT_WRITE_DATA    0xfffU
+#define V_DEBUG_INT_WRITE_DATA(x) ((x) << S_DEBUG_INT_WRITE_DATA)
+#define G_DEBUG_INT_WRITE_DATA(x) (((x) >> S_DEBUG_INT_WRITE_DATA) & M_DEBUG_INT_WRITE_DATA)
+
+#define A_ARM_DEBUG_INT_STAT 0x47274
+
+#define S_DEBUG_INT_STATUS_REG    0
+#define M_DEBUG_INT_STATUS_REG    0xfffU
+#define V_DEBUG_INT_STATUS_REG(x) ((x) << S_DEBUG_INT_STATUS_REG)
+#define G_DEBUG_INT_STATUS_REG(x) (((x) >> S_DEBUG_INT_STATUS_REG) & M_DEBUG_INT_STATUS_REG)
+
+#define A_ARM_DEBUG_STAT 0x47278
+
+#define S_ARM_DEBUG_STAT    0
+#define M_ARM_DEBUG_STAT    0x3fffU
+#define V_ARM_DEBUG_STAT(x) ((x) << S_ARM_DEBUG_STAT)
+#define G_ARM_DEBUG_STAT(x) (((x) >> S_ARM_DEBUG_STAT) & M_ARM_DEBUG_STAT)
+
+#define A_ARM_SIZE_STAT 0x4727c
+
+#define S_ARM_SIZE_STAT    0
+#define M_ARM_SIZE_STAT    0x3fffffffU
+#define V_ARM_SIZE_STAT(x) ((x) << S_ARM_SIZE_STAT)
+#define G_ARM_SIZE_STAT(x) (((x) >> S_ARM_SIZE_STAT) & M_ARM_SIZE_STAT)
+
+#define A_ARM_CCI_CFG0 0x47280
+
+#define S_CCIBROADCASTCACHEMAINT    28
+#define M_CCIBROADCASTCACHEMAINT    0x7U
+#define V_CCIBROADCASTCACHEMAINT(x) ((x) << S_CCIBROADCASTCACHEMAINT)
+#define G_CCIBROADCASTCACHEMAINT(x) (((x) >> S_CCIBROADCASTCACHEMAINT) & M_CCIBROADCASTCACHEMAINT)
+
+#define S_CCISTRIPINGGRANULE    25
+#define M_CCISTRIPINGGRANULE    0x7U
+#define V_CCISTRIPINGGRANULE(x) ((x) << S_CCISTRIPINGGRANULE)
+#define G_CCISTRIPINGGRANULE(x) (((x) >> S_CCISTRIPINGGRANULE) & M_CCISTRIPINGGRANULE)
+
+#define S_CCIPERIPHBASE    0
+#define M_CCIPERIPHBASE    0x1ffffffU
+#define V_CCIPERIPHBASE(x) ((x) << S_CCIPERIPHBASE)
+#define G_CCIPERIPHBASE(x) (((x) >> S_CCIPERIPHBASE) & M_CCIPERIPHBASE)
+
+#define A_ARM_CCI_CFG1 0x47284
+
+#define S_CCIDFTRSTDISABLE    18
+#define V_CCIDFTRSTDISABLE(x) ((x) << S_CCIDFTRSTDISABLE)
+#define F_CCIDFTRSTDISABLE    V_CCIDFTRSTDISABLE(1U)
+
+#define S_CCISPNIDEN    17
+#define V_CCISPNIDEN(x) ((x) << S_CCISPNIDEN)
+#define F_CCISPNIDEN    V_CCISPNIDEN(1U)
+
+#define S_CCINIDEN    16
+#define V_CCINIDEN(x) ((x) << S_CCINIDEN)
+#define F_CCINIDEN    V_CCINIDEN(1U)
+
+#define S_CCIACCHANNELN    11
+#define M_CCIACCHANNELN    0x1fU
+#define V_CCIACCHANNELN(x) ((x) << S_CCIACCHANNELN)
+#define G_CCIACCHANNELN(x) (((x) >> S_CCIACCHANNELN) & M_CCIACCHANNELN)
+
+#define S_CCIQOSOVERRIDE    6
+#define M_CCIQOSOVERRIDE    0x1fU
+#define V_CCIQOSOVERRIDE(x) ((x) << S_CCIQOSOVERRIDE)
+#define G_CCIQOSOVERRIDE(x) (((x) >> S_CCIQOSOVERRIDE) & M_CCIQOSOVERRIDE)
+
+#define S_CCIBUFFERABLEOVERRIDE    3
+#define M_CCIBUFFERABLEOVERRIDE    0x7U
+#define V_CCIBUFFERABLEOVERRIDE(x) ((x) << S_CCIBUFFERABLEOVERRIDE)
+#define G_CCIBUFFERABLEOVERRIDE(x) (((x) >> S_CCIBUFFERABLEOVERRIDE) & M_CCIBUFFERABLEOVERRIDE)
+
+#define S_CCIBARRIERTERMINATE    0
+#define M_CCIBARRIERTERMINATE    0x7U
+#define V_CCIBARRIERTERMINATE(x) ((x) << S_CCIBARRIERTERMINATE)
+#define G_CCIBARRIERTERMINATE(x) (((x) >> S_CCIBARRIERTERMINATE) & M_CCIBARRIERTERMINATE)
+
+#define A_ARM_CCI_CFG2 0x47288
+
+#define S_CCIADDRMAP15    30
+#define M_CCIADDRMAP15    0x3U
+#define V_CCIADDRMAP15(x) ((x) << S_CCIADDRMAP15)
+#define G_CCIADDRMAP15(x) (((x) >> S_CCIADDRMAP15) & M_CCIADDRMAP15)
+
+#define S_CCIADDRMAP14    28
+#define M_CCIADDRMAP14    0x3U
+#define V_CCIADDRMAP14(x) ((x) << S_CCIADDRMAP14)
+#define G_CCIADDRMAP14(x) (((x) >> S_CCIADDRMAP14) & M_CCIADDRMAP14)
+
+#define S_CCIADDRMAP13    26
+#define M_CCIADDRMAP13    0x3U
+#define V_CCIADDRMAP13(x) ((x) << S_CCIADDRMAP13)
+#define G_CCIADDRMAP13(x) (((x) >> S_CCIADDRMAP13) & M_CCIADDRMAP13)
+
+#define S_CCIADDRMAP12    24
+#define M_CCIADDRMAP12    0x3U
+#define V_CCIADDRMAP12(x) ((x) << S_CCIADDRMAP12)
+#define G_CCIADDRMAP12(x) (((x) >> S_CCIADDRMAP12) & M_CCIADDRMAP12)
+
+#define S_CCIADDRMAP11    22
+#define M_CCIADDRMAP11    0x3U
+#define V_CCIADDRMAP11(x) ((x) << S_CCIADDRMAP11)
+#define G_CCIADDRMAP11(x) (((x) >> S_CCIADDRMAP11) & M_CCIADDRMAP11)
+
+#define S_CCIADDRMAP10    20
+#define M_CCIADDRMAP10    0x3U
+#define V_CCIADDRMAP10(x) ((x) << S_CCIADDRMAP10)
+#define G_CCIADDRMAP10(x) (((x) >> S_CCIADDRMAP10) & M_CCIADDRMAP10)
+
+#define S_CCIADDRMAP9    18
+#define M_CCIADDRMAP9    0x3U
+#define V_CCIADDRMAP9(x) ((x) << S_CCIADDRMAP9)
+#define G_CCIADDRMAP9(x) (((x) >> S_CCIADDRMAP9) & M_CCIADDRMAP9)
+
+#define S_CCIADDRMAP8    16
+#define M_CCIADDRMAP8    0x3U
+#define V_CCIADDRMAP8(x) ((x) << S_CCIADDRMAP8)
+#define G_CCIADDRMAP8(x) (((x) >> S_CCIADDRMAP8) & M_CCIADDRMAP8)
+
+#define S_CCIADDRMAP7    14
+#define M_CCIADDRMAP7    0x3U
+#define V_CCIADDRMAP7(x) ((x) << S_CCIADDRMAP7)
+#define G_CCIADDRMAP7(x) (((x) >> S_CCIADDRMAP7) & M_CCIADDRMAP7)
+
+#define S_CCIADDRMAP6    12
+#define M_CCIADDRMAP6    0x3U
+#define V_CCIADDRMAP6(x) ((x) << S_CCIADDRMAP6)
+#define G_CCIADDRMAP6(x) (((x) >> S_CCIADDRMAP6) & M_CCIADDRMAP6)
+
+#define S_CCIADDRMAP5    10
+#define M_CCIADDRMAP5    0x3U
+#define V_CCIADDRMAP5(x) ((x) << S_CCIADDRMAP5)
+#define G_CCIADDRMAP5(x) (((x) >> S_CCIADDRMAP5) & M_CCIADDRMAP5)
+
+#define S_CCIADDRMAP4    8
+#define M_CCIADDRMAP4    0x3U
+#define V_CCIADDRMAP4(x) ((x) << S_CCIADDRMAP4)
+#define G_CCIADDRMAP4(x) (((x) >> S_CCIADDRMAP4) & M_CCIADDRMAP4)
+
+#define S_CCIADDRMAP3    6
+#define M_CCIADDRMAP3    0x3U
+#define V_CCIADDRMAP3(x) ((x) << S_CCIADDRMAP3)
+#define G_CCIADDRMAP3(x) (((x) >> S_CCIADDRMAP3) & M_CCIADDRMAP3)
+
+#define S_CCIADDRMAP2    4
+#define M_CCIADDRMAP2    0x3U
+#define V_CCIADDRMAP2(x) ((x) << S_CCIADDRMAP2)
+#define G_CCIADDRMAP2(x) (((x) >> S_CCIADDRMAP2) & M_CCIADDRMAP2)
+
+#define S_CCIADDRMAP1    2
+#define M_CCIADDRMAP1    0x3U
+#define V_CCIADDRMAP1(x) ((x) << S_CCIADDRMAP1)
+#define G_CCIADDRMAP1(x) (((x) >> S_CCIADDRMAP1) & M_CCIADDRMAP1)
+
+#define S_CCIADDRMAP0    0
+#define M_CCIADDRMAP0    0x3U
+#define V_CCIADDRMAP0(x) ((x) << S_CCIADDRMAP0)
+#define G_CCIADDRMAP0(x) (((x) >> S_CCIADDRMAP0) & M_CCIADDRMAP0)
+
+#define A_ARM_CCI_STATUS 0x4728c
+
+#define S_CCICACTIVE    6
+#define V_CCICACTIVE(x) ((x) << S_CCICACTIVE)
+#define F_CCICACTIVE    V_CCICACTIVE(1U)
+
+#define S_CCICSYSACK    5
+#define V_CCICSYSACK(x) ((x) << S_CCICSYSACK)
+#define F_CCICSYSACK    V_CCICSYSACK(1U)
+
+#define S_CCINEVNTCNTOVERFLOW    0
+#define M_CCINEVNTCNTOVERFLOW    0x1fU
+#define V_CCINEVNTCNTOVERFLOW(x) ((x) << S_CCINEVNTCNTOVERFLOW)
+#define G_CCINEVNTCNTOVERFLOW(x) (((x) >> S_CCINEVNTCNTOVERFLOW) & M_CCINEVNTCNTOVERFLOW)
+
+#define A_ARM_CCIM_CCI_QVN_MASTER_CFG 0x47290
+
+#define S_CCIVWREADYVN3M    20
+#define V_CCIVWREADYVN3M(x) ((x) << S_CCIVWREADYVN3M)
+#define F_CCIVWREADYVN3M    V_CCIVWREADYVN3M(1U)
+
+#define S_CCIVAWREADYVN3M    19
+#define V_CCIVAWREADYVN3M(x) ((x) << S_CCIVAWREADYVN3M)
+#define F_CCIVAWREADYVN3M    V_CCIVAWREADYVN3M(1U)
+
+#define S_CCIVARREADYVN3M    18
+#define V_CCIVARREADYVN3M(x) ((x) << S_CCIVARREADYVN3M)
+#define F_CCIVARREADYVN3M    V_CCIVARREADYVN3M(1U)
+
+#define S_CCIVWREADYVN2M    17
+#define V_CCIVWREADYVN2M(x) ((x) << S_CCIVWREADYVN2M)
+#define F_CCIVWREADYVN2M    V_CCIVWREADYVN2M(1U)
+
+#define S_CCIVAWREADYVN2M    16
+#define V_CCIVAWREADYVN2M(x) ((x) << S_CCIVAWREADYVN2M)
+#define F_CCIVAWREADYVN2M    V_CCIVAWREADYVN2M(1U)
+
+#define S_CCIVARREADYVN2M    15
+#define V_CCIVARREADYVN2M(x) ((x) << S_CCIVARREADYVN2M)
+#define F_CCIVARREADYVN2M    V_CCIVARREADYVN2M(1U)
+
+#define S_CCIVWREADYVN1M    14
+#define V_CCIVWREADYVN1M(x) ((x) << S_CCIVWREADYVN1M)
+#define F_CCIVWREADYVN1M    V_CCIVWREADYVN1M(1U)
+
+#define S_CCIVAWREADYVN1M    13
+#define V_CCIVAWREADYVN1M(x) ((x) << S_CCIVAWREADYVN1M)
+#define F_CCIVAWREADYVN1M    V_CCIVAWREADYVN1M(1U)
+
+#define S_CCIVARREADYVN1M    12
+#define V_CCIVARREADYVN1M(x) ((x) << S_CCIVARREADYVN1M)
+#define F_CCIVARREADYVN1M    V_CCIVARREADYVN1M(1U)
+
+#define S_CCIVWREADYVN0M    11
+#define V_CCIVWREADYVN0M(x) ((x) << S_CCIVWREADYVN0M)
+#define F_CCIVWREADYVN0M    V_CCIVWREADYVN0M(1U)
+
+#define S_CCIVAWREADYVN0M    10
+#define V_CCIVAWREADYVN0M(x) ((x) << S_CCIVAWREADYVN0M)
+#define F_CCIVAWREADYVN0M    V_CCIVAWREADYVN0M(1U)
+
+#define S_CCIVARREADYVN0M    9
+#define V_CCIVARREADYVN0M(x) ((x) << S_CCIVARREADYVN0M)
+#define F_CCIVARREADYVN0M    V_CCIVARREADYVN0M(1U)
+
+#define S_CCIQVNPREALLOCWM    5
+#define M_CCIQVNPREALLOCWM    0xfU
+#define V_CCIQVNPREALLOCWM(x) ((x) << S_CCIQVNPREALLOCWM)
+#define G_CCIQVNPREALLOCWM(x) (((x) >> S_CCIQVNPREALLOCWM) & M_CCIQVNPREALLOCWM)
+
+#define S_CCIQVNPREALLOCRM    1
+#define M_CCIQVNPREALLOCRM    0xfU
+#define V_CCIQVNPREALLOCRM(x) ((x) << S_CCIQVNPREALLOCRM)
+#define G_CCIQVNPREALLOCRM(x) (((x) >> S_CCIQVNPREALLOCRM) & M_CCIQVNPREALLOCRM)
+
+#define S_CCIQVNENABLEM    0
+#define V_CCIQVNENABLEM(x) ((x) << S_CCIQVNENABLEM)
+#define F_CCIQVNENABLEM    V_CCIQVNENABLEM(1U)
+
+#define A_ARM_CCIM_CCI_QVN_MASTER_STATUS 0x47294
+
+#define S_CCIVWVALIDN3M    31
+#define V_CCIVWVALIDN3M(x) ((x) << S_CCIVWVALIDN3M)
+#define F_CCIVWVALIDN3M    V_CCIVWVALIDN3M(1U)
+
+#define S_CCIVAWVALIDN3M    30
+#define V_CCIVAWVALIDN3M(x) ((x) << S_CCIVAWVALIDN3M)
+#define F_CCIVAWVALIDN3M    V_CCIVAWVALIDN3M(1U)
+
+#define S_CCIVAWQOSN3M    29
+#define V_CCIVAWQOSN3M(x) ((x) << S_CCIVAWQOSN3M)
+#define F_CCIVAWQOSN3M    V_CCIVAWQOSN3M(1U)
+
+#define S_CCIVARVALIDN3M    28
+#define V_CCIVARVALIDN3M(x) ((x) << S_CCIVARVALIDN3M)
+#define F_CCIVARVALIDN3M    V_CCIVARVALIDN3M(1U)
+
+#define S_CCIVARQOSN3M    24
+#define M_CCIVARQOSN3M    0xfU
+#define V_CCIVARQOSN3M(x) ((x) << S_CCIVARQOSN3M)
+#define G_CCIVARQOSN3M(x) (((x) >> S_CCIVARQOSN3M) & M_CCIVARQOSN3M)
+
+#define S_CCIVWVALIDN2M    23
+#define V_CCIVWVALIDN2M(x) ((x) << S_CCIVWVALIDN2M)
+#define F_CCIVWVALIDN2M    V_CCIVWVALIDN2M(1U)
+
+#define S_CCIVAWVALIDN2M    22
+#define V_CCIVAWVALIDN2M(x) ((x) << S_CCIVAWVALIDN2M)
+#define F_CCIVAWVALIDN2M    V_CCIVAWVALIDN2M(1U)
+
+#define S_CCIVAWQOSN2M    21
+#define V_CCIVAWQOSN2M(x) ((x) << S_CCIVAWQOSN2M)
+#define F_CCIVAWQOSN2M    V_CCIVAWQOSN2M(1U)
+
+#define S_CCIVARVALIDN2M    20
+#define V_CCIVARVALIDN2M(x) ((x) << S_CCIVARVALIDN2M)
+#define F_CCIVARVALIDN2M    V_CCIVARVALIDN2M(1U)
+
+#define S_CCIVARQOSN2M    16
+#define M_CCIVARQOSN2M    0xfU
+#define V_CCIVARQOSN2M(x) ((x) << S_CCIVARQOSN2M)
+#define G_CCIVARQOSN2M(x) (((x) >> S_CCIVARQOSN2M) & M_CCIVARQOSN2M)
+
+#define S_CCIVWVALIDN1M    15
+#define V_CCIVWVALIDN1M(x) ((x) << S_CCIVWVALIDN1M)
+#define F_CCIVWVALIDN1M    V_CCIVWVALIDN1M(1U)
+
+#define S_CCIVAWVALIDN1M    14
+#define V_CCIVAWVALIDN1M(x) ((x) << S_CCIVAWVALIDN1M)
+#define F_CCIVAWVALIDN1M    V_CCIVAWVALIDN1M(1U)
+
+#define S_CCIVAWQOSN1M    13
+#define V_CCIVAWQOSN1M(x) ((x) << S_CCIVAWQOSN1M)
+#define F_CCIVAWQOSN1M    V_CCIVAWQOSN1M(1U)
+
+#define S_CCIVARVALIDN1M    12
+#define V_CCIVARVALIDN1M(x) ((x) << S_CCIVARVALIDN1M)
+#define F_CCIVARVALIDN1M    V_CCIVARVALIDN1M(1U)
+
+#define S_CCIVARQOSN1M    8
+#define M_CCIVARQOSN1M    0xfU
+#define V_CCIVARQOSN1M(x) ((x) << S_CCIVARQOSN1M)
+#define G_CCIVARQOSN1M(x) (((x) >> S_CCIVARQOSN1M) & M_CCIVARQOSN1M)
+
+#define S_CCIVWVALIDN0M    7
+#define V_CCIVWVALIDN0M(x) ((x) << S_CCIVWVALIDN0M)
+#define F_CCIVWVALIDN0M    V_CCIVWVALIDN0M(1U)
+
+#define S_CCIVAWVALIDN0M    6
+#define V_CCIVAWVALIDN0M(x) ((x) << S_CCIVAWVALIDN0M)
+#define F_CCIVAWVALIDN0M    V_CCIVAWVALIDN0M(1U)
+
+#define S_CCIVAWQOSN0M    5
+#define V_CCIVAWQOSN0M(x) ((x) << S_CCIVAWQOSN0M)
+#define F_CCIVAWQOSN0M    V_CCIVAWQOSN0M(1U)
+
+#define S_CCIVARVALIDN0M    4
+#define V_CCIVARVALIDN0M(x) ((x) << S_CCIVARVALIDN0M)
+#define F_CCIVARVALIDN0M    V_CCIVARVALIDN0M(1U)
+
+#define S_CCIVARQOSN0M    0
+#define M_CCIVARQOSN0M    0xfU
+#define V_CCIVARQOSN0M(x) ((x) << S_CCIVARQOSN0M)
+#define G_CCIVARQOSN0M(x) (((x) >> S_CCIVARQOSN0M) & M_CCIVARQOSN0M)
+
+#define A_ARM_CCIS_CCI_QVN_SLAVE_CFG 0x472d0
+
+#define S_CCIQVNVNETS    0
+#define M_CCIQVNVNETS    0x3U
+#define V_CCIQVNVNETS(x) ((x) << S_CCIQVNVNETS)
+#define G_CCIQVNVNETS(x) (((x) >> S_CCIQVNVNETS) & M_CCIQVNVNETS)
+
+#define A_ARM_CCIS_CCI_QVN_SLAVE_STATUS 0x472d4
+
+#define S_CCIEVNTAWQOS    4
+#define M_CCIEVNTAWQOS    0xfU
+#define V_CCIEVNTAWQOS(x) ((x) << S_CCIEVNTAWQOS)
+#define G_CCIEVNTAWQOS(x) (((x) >> S_CCIEVNTAWQOS) & M_CCIEVNTAWQOS)
+
+#define S_CCIEVNTARQOS    0
+#define M_CCIEVNTARQOS    0xfU
+#define V_CCIEVNTARQOS(x) ((x) << S_CCIEVNTARQOS)
+#define G_CCIEVNTARQOS(x) (((x) >> S_CCIEVNTARQOS) & M_CCIEVNTARQOS)
+
+#define A_ARM_CCI_EVNTBUS 0x47300
+#define A_ARM_CCI_RST_N 0x47318
+
+#define S_CCIRSTN    0
+#define V_CCIRSTN(x) ((x) << S_CCIRSTN)
+#define F_CCIRSTN    V_CCIRSTN(1U)
+
+#define A_ARM_CCI_CSYREQ 0x4731c
+
+#define S_CCICSYSREQ    0
+#define V_CCICSYSREQ(x) ((x) << S_CCICSYSREQ)
+#define F_CCICSYSREQ    V_CCICSYSREQ(1U)
+
+#define A_ARM_CCI_TR_DEBUGS0 0x47320
+
+#define S_CCIS0RCNT    24
+#define M_CCIS0RCNT    0xffU
+#define V_CCIS0RCNT(x) ((x) << S_CCIS0RCNT)
+#define G_CCIS0RCNT(x) (((x) >> S_CCIS0RCNT) & M_CCIS0RCNT)
+
+#define S_CCIS0ARCNT    16
+#define M_CCIS0ARCNT    0xffU
+#define V_CCIS0ARCNT(x) ((x) << S_CCIS0ARCNT)
+#define G_CCIS0ARCNT(x) (((x) >> S_CCIS0ARCNT) & M_CCIS0ARCNT)
+
+#define S_CCIS0WCNT    8
+#define M_CCIS0WCNT    0xffU
+#define V_CCIS0WCNT(x) ((x) << S_CCIS0WCNT)
+#define G_CCIS0WCNT(x) (((x) >> S_CCIS0WCNT) & M_CCIS0WCNT)
+
+#define S_CCIS0AWCNT    0
+#define M_CCIS0AWCNT    0xffU
+#define V_CCIS0AWCNT(x) ((x) << S_CCIS0AWCNT)
+#define G_CCIS0AWCNT(x) (((x) >> S_CCIS0AWCNT) & M_CCIS0AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGS1 0x47324
+
+#define S_CCIS1RCNT    24
+#define M_CCIS1RCNT    0xffU
+#define V_CCIS1RCNT(x) ((x) << S_CCIS1RCNT)
+#define G_CCIS1RCNT(x) (((x) >> S_CCIS1RCNT) & M_CCIS1RCNT)
+
+#define S_CCIS1ARCNT    16
+#define M_CCIS1ARCNT    0xffU
+#define V_CCIS1ARCNT(x) ((x) << S_CCIS1ARCNT)
+#define G_CCIS1ARCNT(x) (((x) >> S_CCIS1ARCNT) & M_CCIS1ARCNT)
+
+#define S_CCIS1WCNT    8
+#define M_CCIS1WCNT    0xffU
+#define V_CCIS1WCNT(x) ((x) << S_CCIS1WCNT)
+#define G_CCIS1WCNT(x) (((x) >> S_CCIS1WCNT) & M_CCIS1WCNT)
+
+#define S_CCIS1AWCNT    0
+#define M_CCIS1AWCNT    0xffU
+#define V_CCIS1AWCNT(x) ((x) << S_CCIS1AWCNT)
+#define G_CCIS1AWCNT(x) (((x) >> S_CCIS1AWCNT) & M_CCIS1AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGS2 0x47328
+
+#define S_CCIS2RCNT    24
+#define M_CCIS2RCNT    0xffU
+#define V_CCIS2RCNT(x) ((x) << S_CCIS2RCNT)
+#define G_CCIS2RCNT(x) (((x) >> S_CCIS2RCNT) & M_CCIS2RCNT)
+
+#define S_CCIS2ARCNT    16
+#define M_CCIS2ARCNT    0xffU
+#define V_CCIS2ARCNT(x) ((x) << S_CCIS2ARCNT)
+#define G_CCIS2ARCNT(x) (((x) >> S_CCIS2ARCNT) & M_CCIS2ARCNT)
+
+#define S_CCIS2WCNT    8
+#define M_CCIS2WCNT    0xffU
+#define V_CCIS2WCNT(x) ((x) << S_CCIS2WCNT)
+#define G_CCIS2WCNT(x) (((x) >> S_CCIS2WCNT) & M_CCIS2WCNT)
+
+#define S_CCIS2AWCNT    0
+#define M_CCIS2AWCNT    0xffU
+#define V_CCIS2AWCNT(x) ((x) << S_CCIS2AWCNT)
+#define G_CCIS2AWCNT(x) (((x) >> S_CCIS2AWCNT) & M_CCIS2AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGS3 0x4732c
+
+#define S_CCIS3RCNT    24
+#define M_CCIS3RCNT    0xffU
+#define V_CCIS3RCNT(x) ((x) << S_CCIS3RCNT)
+#define G_CCIS3RCNT(x) (((x) >> S_CCIS3RCNT) & M_CCIS3RCNT)
+
+#define S_CCIS3ARCNT    16
+#define M_CCIS3ARCNT    0xffU
+#define V_CCIS3ARCNT(x) ((x) << S_CCIS3ARCNT)
+#define G_CCIS3ARCNT(x) (((x) >> S_CCIS3ARCNT) & M_CCIS3ARCNT)
+
+#define S_CCIS3WCNT    8
+#define M_CCIS3WCNT    0xffU
+#define V_CCIS3WCNT(x) ((x) << S_CCIS3WCNT)
+#define G_CCIS3WCNT(x) (((x) >> S_CCIS3WCNT) & M_CCIS3WCNT)
+
+#define S_CCIS3AWCNT    0
+#define M_CCIS3AWCNT    0xffU
+#define V_CCIS3AWCNT(x) ((x) << S_CCIS3AWCNT)
+#define G_CCIS3AWCNT(x) (((x) >> S_CCIS3AWCNT) & M_CCIS3AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGS4 0x47330
+
+#define S_CCIS4RCNT    24
+#define M_CCIS4RCNT    0xffU
+#define V_CCIS4RCNT(x) ((x) << S_CCIS4RCNT)
+#define G_CCIS4RCNT(x) (((x) >> S_CCIS4RCNT) & M_CCIS4RCNT)
+
+#define S_CCIS4ARCNT    16
+#define M_CCIS4ARCNT    0xffU
+#define V_CCIS4ARCNT(x) ((x) << S_CCIS4ARCNT)
+#define G_CCIS4ARCNT(x) (((x) >> S_CCIS4ARCNT) & M_CCIS4ARCNT)
+
+#define S_CCIS4WCNT    8
+#define M_CCIS4WCNT    0xffU
+#define V_CCIS4WCNT(x) ((x) << S_CCIS4WCNT)
+#define G_CCIS4WCNT(x) (((x) >> S_CCIS4WCNT) & M_CCIS4WCNT)
+
+#define S_CCIS4AWCNT    0
+#define M_CCIS4AWCNT    0xffU
+#define V_CCIS4AWCNT(x) ((x) << S_CCIS4AWCNT)
+#define G_CCIS4AWCNT(x) (((x) >> S_CCIS4AWCNT) & M_CCIS4AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGS34 0x47334
+
+#define S_CCIS4RSPCNT    24
+#define M_CCIS4RSPCNT    0xffU
+#define V_CCIS4RSPCNT(x) ((x) << S_CCIS4RSPCNT)
+#define G_CCIS4RSPCNT(x) (((x) >> S_CCIS4RSPCNT) & M_CCIS4RSPCNT)
+
+#define S_CCIS4ACCNT    16
+#define M_CCIS4ACCNT    0xffU
+#define V_CCIS4ACCNT(x) ((x) << S_CCIS4ACCNT)
+#define G_CCIS4ACCNT(x) (((x) >> S_CCIS4ACCNT) & M_CCIS4ACCNT)
+
+#define S_CCIS3RSPCNT    8
+#define M_CCIS3RSPCNT    0xffU
+#define V_CCIS3RSPCNT(x) ((x) << S_CCIS3RSPCNT)
+#define G_CCIS3RSPCNT(x) (((x) >> S_CCIS3RSPCNT) & M_CCIS3RSPCNT)
+
+#define S_CCIS3ACCNT    0
+#define M_CCIS3ACCNT    0xffU
+#define V_CCIS3ACCNT(x) ((x) << S_CCIS3ACCNT)
+#define G_CCIS3ACCNT(x) (((x) >> S_CCIS3ACCNT) & M_CCIS3ACCNT)
+
+#define A_ARM_CCI_TR_DEBUGM0 0x47338
+
+#define S_CCIM0RCNT    24
+#define M_CCIM0RCNT    0xffU
+#define V_CCIM0RCNT(x) ((x) << S_CCIM0RCNT)
+#define G_CCIM0RCNT(x) (((x) >> S_CCIM0RCNT) & M_CCIM0RCNT)
+
+#define S_CCIM0ARCNT    16
+#define M_CCIM0ARCNT    0xffU
+#define V_CCIM0ARCNT(x) ((x) << S_CCIM0ARCNT)
+#define G_CCIM0ARCNT(x) (((x) >> S_CCIM0ARCNT) & M_CCIM0ARCNT)
+
+#define S_CCIM0WCNT    8
+#define M_CCIM0WCNT    0xffU
+#define V_CCIM0WCNT(x) ((x) << S_CCIM0WCNT)
+#define G_CCIM0WCNT(x) (((x) >> S_CCIM0WCNT) & M_CCIM0WCNT)
+
+#define S_CCIM0AWCNT    0
+#define M_CCIM0AWCNT    0xffU
+#define V_CCIM0AWCNT(x) ((x) << S_CCIM0AWCNT)
+#define G_CCIM0AWCNT(x) (((x) >> S_CCIM0AWCNT) & M_CCIM0AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGM1 0x4733c
+
+#define S_CCIM1RCNT    24
+#define M_CCIM1RCNT    0xffU
+#define V_CCIM1RCNT(x) ((x) << S_CCIM1RCNT)
+#define G_CCIM1RCNT(x) (((x) >> S_CCIM1RCNT) & M_CCIM1RCNT)
+
+#define S_CCIM1ARCNT    16
+#define M_CCIM1ARCNT    0xffU
+#define V_CCIM1ARCNT(x) ((x) << S_CCIM1ARCNT)
+#define G_CCIM1ARCNT(x) (((x) >> S_CCIM1ARCNT) & M_CCIM1ARCNT)
+
+#define S_CCIM1WCNT    8
+#define M_CCIM1WCNT    0xffU
+#define V_CCIM1WCNT(x) ((x) << S_CCIM1WCNT)
+#define G_CCIM1WCNT(x) (((x) >> S_CCIM1WCNT) & M_CCIM1WCNT)
+
+#define S_CCIM1AWCNT    0
+#define M_CCIM1AWCNT    0xffU
+#define V_CCIM1AWCNT(x) ((x) << S_CCIM1AWCNT)
+#define G_CCIM1AWCNT(x) (((x) >> S_CCIM1AWCNT) & M_CCIM1AWCNT)
+
+#define A_ARM_CCI_TR_DEBUGM2 0x47340
+
+#define S_CCIM2RCNT    24
+#define M_CCIM2RCNT    0xffU
+#define V_CCIM2RCNT(x) ((x) << S_CCIM2RCNT)
+#define G_CCIM2RCNT(x) (((x) >> S_CCIM2RCNT) & M_CCIM2RCNT)
+
+#define S_CCIM2ARCNT    16
+#define M_CCIM2ARCNT    0xffU
+#define V_CCIM2ARCNT(x) ((x) << S_CCIM2ARCNT)
+#define G_CCIM2ARCNT(x) (((x) >> S_CCIM2ARCNT) & M_CCIM2ARCNT)
+
+#define S_CCIM2WCNT    8
+#define M_CCIM2WCNT    0xffU
+#define V_CCIM2WCNT(x) ((x) << S_CCIM2WCNT)
+#define G_CCIM2WCNT(x) (((x) >> S_CCIM2WCNT) & M_CCIM2WCNT)
+
+#define S_CCIM2AWCNT    0
+#define M_CCIM2AWCNT    0xffU
+#define V_CCIM2AWCNT(x) ((x) << S_CCIM2AWCNT)
+#define G_CCIM2AWCNT(x) (((x) >> S_CCIM2AWCNT) & M_CCIM2AWCNT)
+
+#define A_ARM_MA_TR_DEBUG 0x47344
+
+#define S_MA1_RD_CNT    24
+#define M_MA1_RD_CNT    0xffU
+#define V_MA1_RD_CNT(x) ((x) << S_MA1_RD_CNT)
+#define G_MA1_RD_CNT(x) (((x) >> S_MA1_RD_CNT) & M_MA1_RD_CNT)
+
+#define S_MA1_WR_CNT    16
+#define M_MA1_WR_CNT    0xffU
+#define V_MA1_WR_CNT(x) ((x) << S_MA1_WR_CNT)
+#define G_MA1_WR_CNT(x) (((x) >> S_MA1_WR_CNT) & M_MA1_WR_CNT)
+
+#define S_MA0_RD_CNT    8
+#define M_MA0_RD_CNT    0xffU
+#define V_MA0_RD_CNT(x) ((x) << S_MA0_RD_CNT)
+#define G_MA0_RD_CNT(x) (((x) >> S_MA0_RD_CNT) & M_MA0_RD_CNT)
+
+#define S_MA0_WR_CNT    0
+#define M_MA0_WR_CNT    0xffU
+#define V_MA0_WR_CNT(x) ((x) << S_MA0_WR_CNT)
+#define G_MA0_WR_CNT(x) (((x) >> S_MA0_WR_CNT) & M_MA0_WR_CNT)
+
+#define A_ARM_GP_INT 0x47348
+
+#define S_GP_INT    0
+#define M_GP_INT    0xffU
+#define V_GP_INT(x) ((x) << S_GP_INT)
+#define G_GP_INT(x) (((x) >> S_GP_INT) & M_GP_INT)
+
+#define A_ARM_DMA_CFG0 0x47350
+#define A_ARM_DMA_CFG1 0x47354
+
+#define S_DMABOOTPERIPHNS    16
+#define M_DMABOOTPERIPHNS    0x3ffU
+#define V_DMABOOTPERIPHNS(x) ((x) << S_DMABOOTPERIPHNS)
+#define G_DMABOOTPERIPHNS(x) (((x) >> S_DMABOOTPERIPHNS) & M_DMABOOTPERIPHNS)
+
+#define S_DMABOOTIRQNS    4
+#define M_DMABOOTIRQNS    0x3ffU
+#define V_DMABOOTIRQNS(x) ((x) << S_DMABOOTIRQNS)
+#define G_DMABOOTIRQNS(x) (((x) >> S_DMABOOTIRQNS) & M_DMABOOTIRQNS)
+
+#define S_DMABOOTMANAGERNS    1
+#define V_DMABOOTMANAGERNS(x) ((x) << S_DMABOOTMANAGERNS)
+#define F_DMABOOTMANAGERNS    V_DMABOOTMANAGERNS(1U)
+
+#define S_DMABOOTFROMPC    0
+#define V_DMABOOTFROMPC(x) ((x) << S_DMABOOTFROMPC)
+#define F_DMABOOTFROMPC    V_DMABOOTFROMPC(1U)
+
+#define A_ARM_ARM_CFG0 0x47380
+
+#define S_MESSAGEBYPASS_DATA    2
+#define V_MESSAGEBYPASS_DATA(x) ((x) << S_MESSAGEBYPASS_DATA)
+#define F_MESSAGEBYPASS_DATA    V_MESSAGEBYPASS_DATA(1U)
+
+#define S_MESSAGEBYPASS    1
+#define V_MESSAGEBYPASS(x) ((x) << S_MESSAGEBYPASS)
+#define F_MESSAGEBYPASS    V_MESSAGEBYPASS(1U)
+
+#define S_PCIEBYPASS    0
+#define V_PCIEBYPASS(x) ((x) << S_PCIEBYPASS)
+#define F_PCIEBYPASS    V_PCIEBYPASS(1U)
+
+#define A_ARM_ARM_CFG1 0x47384
+#define A_ARM_ARM_CFG2 0x47390
+#define A_ARM_PCIE_MA_ADDR_REGION0 0x47400
+
+#define S_ADDRREG0    0
+#define M_ADDRREG0    0xfffffffU
+#define V_ADDRREG0(x) ((x) << S_ADDRREG0)
+#define G_ADDRREG0(x) (((x) >> S_ADDRREG0) & M_ADDRREG0)
+
+#define A_ARM_PCIE_MA_ADDR_REGION1 0x47404
+
+#define S_ADDRREG1    0
+#define M_ADDRREG1    0xfffffffU
+#define V_ADDRREG1(x) ((x) << S_ADDRREG1)
+#define G_ADDRREG1(x) (((x) >> S_ADDRREG1) & M_ADDRREG1)
+
+#define A_ARM_PCIE_MA_ADDR_REGION2 0x47408
+
+#define S_ADDRREG2    0
+#define M_ADDRREG2    0xfffffffU
+#define V_ADDRREG2(x) ((x) << S_ADDRREG2)
+#define G_ADDRREG2(x) (((x) >> S_ADDRREG2) & M_ADDRREG2)
+
+#define A_ARM_PCIE_MA_ADDR_REGION3 0x4740c
+
+#define S_ADDRREG3    0
+#define M_ADDRREG3    0xfffffffU
+#define V_ADDRREG3(x) ((x) << S_ADDRREG3)
+#define G_ADDRREG3(x) (((x) >> S_ADDRREG3) & M_ADDRREG3)
+
+#define A_ARM_PCIE_MA_ADDR_REGION4 0x47410
+
+#define S_ADDRREG4    0
+#define M_ADDRREG4    0xfffffffU
+#define V_ADDRREG4(x) ((x) << S_ADDRREG4)
+#define G_ADDRREG4(x) (((x) >> S_ADDRREG4) & M_ADDRREG4)
+
+#define A_ARM_PCIE_MA_ADDR_REGION5 0x47414
+
+#define S_ADDRREG5    0
+#define M_ADDRREG5    0xfffffffU
+#define V_ADDRREG5(x) ((x) << S_ADDRREG5)
+#define G_ADDRREG5(x) (((x) >> S_ADDRREG5) & M_ADDRREG5)
+
+#define A_ARM_PCIE_MA_ADDR_REGION6 0x47418
+
+#define S_ADDRREG6    0
+#define M_ADDRREG6    0xfffffffU
+#define V_ADDRREG6(x) ((x) << S_ADDRREG6)
+#define G_ADDRREG6(x) (((x) >> S_ADDRREG6) & M_ADDRREG6)
+
+#define A_ARM_PCIE_MA_ADDR_REGION7 0x4741c
+
+#define S_ADDRREG7    0
+#define M_ADDRREG7    0xfffffffU
+#define V_ADDRREG7(x) ((x) << S_ADDRREG7)
+#define G_ADDRREG7(x) (((x) >> S_ADDRREG7) & M_ADDRREG7)
+
+#define A_ARM_INTERRUPT_GEN 0x47420
+
+#define S_INT_GEN    0
+#define M_INT_GEN    0x3U
+#define V_INT_GEN(x) ((x) << S_INT_GEN)
+#define G_INT_GEN(x) (((x) >> S_INT_GEN) & M_INT_GEN)
+
+#define A_ARM_INTERRUPT_CLEAR 0x47424
+
+#define S_INT_CLEAR    0
+#define M_INT_CLEAR    0x3U
+#define V_INT_CLEAR(x) ((x) << S_INT_CLEAR)
+#define G_INT_CLEAR(x) (((x) >> S_INT_CLEAR) & M_INT_CLEAR)
+
+#define A_ARM_DEBUG_STATUS_0 0x47428
+#define A_ARM_DBPROC_CONTROL 0x4742c
+
+#define S_NO_OF_INTERRUPTS    0
+#define M_NO_OF_INTERRUPTS    0x3U
+#define V_NO_OF_INTERRUPTS(x) ((x) << S_NO_OF_INTERRUPTS)
+#define G_NO_OF_INTERRUPTS(x) (((x) >> S_NO_OF_INTERRUPTS) & M_NO_OF_INTERRUPTS)
+
+#define A_ARM_PERR_INT_CAUSE1 0x47430
+
+#define S_ARWFIFO0_PERR    31
+#define V_ARWFIFO0_PERR(x) ((x) << S_ARWFIFO0_PERR)
+#define F_ARWFIFO0_PERR    V_ARWFIFO0_PERR(1U)
+
+#define S_ARWFIFO1_PERR    30
+#define V_ARWFIFO1_PERR(x) ((x) << S_ARWFIFO1_PERR)
+#define F_ARWFIFO1_PERR    V_ARWFIFO1_PERR(1U)
+
+#define S_ARWIDFIFO0_PERR    29
+#define V_ARWIDFIFO0_PERR(x) ((x) << S_ARWIDFIFO0_PERR)
+#define F_ARWIDFIFO0_PERR    V_ARWIDFIFO0_PERR(1U)
+
+#define S_ARWIDFIFO1_PERR    28
+#define V_ARWIDFIFO1_PERR(x) ((x) << S_ARWIDFIFO1_PERR)
+#define F_ARWIDFIFO1_PERR    V_ARWIDFIFO1_PERR(1U)
+
+#define S_ARIDFIFO0_PERR    27
+#define V_ARIDFIFO0_PERR(x) ((x) << S_ARIDFIFO0_PERR)
+#define F_ARIDFIFO0_PERR    V_ARIDFIFO0_PERR(1U)
+
+#define S_ARIDFIFO1_PERR    26
+#define V_ARIDFIFO1_PERR(x) ((x) << S_ARIDFIFO1_PERR)
+#define F_ARIDFIFO1_PERR    V_ARIDFIFO1_PERR(1U)
+
+#define S_RRSPADDR_FIFO0_PERR    25
+#define V_RRSPADDR_FIFO0_PERR(x) ((x) << S_RRSPADDR_FIFO0_PERR)
+#define F_RRSPADDR_FIFO0_PERR    V_RRSPADDR_FIFO0_PERR(1U)
+
+#define S_RRSPADDR_FIFO1_PERR    24
+#define V_RRSPADDR_FIFO1_PERR(x) ((x) << S_RRSPADDR_FIFO1_PERR)
+#define F_RRSPADDR_FIFO1_PERR    V_RRSPADDR_FIFO1_PERR(1U)
+
+#define S_WRSTRB_FIFO0_PERR    23
+#define V_WRSTRB_FIFO0_PERR(x) ((x) << S_WRSTRB_FIFO0_PERR)
+#define F_WRSTRB_FIFO0_PERR    V_WRSTRB_FIFO0_PERR(1U)
+
+#define S_WRSTRB_FIFO1_PERR    22
+#define V_WRSTRB_FIFO1_PERR(x) ((x) << S_WRSTRB_FIFO1_PERR)
+#define F_WRSTRB_FIFO1_PERR    V_WRSTRB_FIFO1_PERR(1U)
+
+#define S_MA2AXI_RSPDATAPARERR    21
+#define V_MA2AXI_RSPDATAPARERR(x) ((x) << S_MA2AXI_RSPDATAPARERR)
+#define F_MA2AXI_RSPDATAPARERR    V_MA2AXI_RSPDATAPARERR(1U)
+
+#define S_MA2AXI_DATA_PAR_ERR    20
+#define V_MA2AXI_DATA_PAR_ERR(x) ((x) << S_MA2AXI_DATA_PAR_ERR)
+#define F_MA2AXI_DATA_PAR_ERR    V_MA2AXI_DATA_PAR_ERR(1U)
+
+#define S_MA2AXI_WR_ORD_FIFO_PARERR    19
+#define V_MA2AXI_WR_ORD_FIFO_PARERR(x) ((x) << S_MA2AXI_WR_ORD_FIFO_PARERR)
+#define F_MA2AXI_WR_ORD_FIFO_PARERR    V_MA2AXI_WR_ORD_FIFO_PARERR(1U)
+
+#define S_NVME_DB_EMU_TRACKER_FIFO_PERR    18
+#define V_NVME_DB_EMU_TRACKER_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_TRACKER_FIFO_PERR)
+#define F_NVME_DB_EMU_TRACKER_FIFO_PERR    V_NVME_DB_EMU_TRACKER_FIFO_PERR(1U)
+
+#define S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR    17
+#define V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR)
+#define F_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR    V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(1U)
+
+#define S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR    16
+#define V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR)
+#define F_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR    V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(1U)
+
+#define S_NVME_DB_EMU_ID_FIFO0_PERR    15
+#define V_NVME_DB_EMU_ID_FIFO0_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO0_PERR)
+#define F_NVME_DB_EMU_ID_FIFO0_PERR    V_NVME_DB_EMU_ID_FIFO0_PERR(1U)
+
+#define S_NVME_DB_EMU_ID_FIFO1_PERR    14
+#define V_NVME_DB_EMU_ID_FIFO1_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO1_PERR)
+#define F_NVME_DB_EMU_ID_FIFO1_PERR    V_NVME_DB_EMU_ID_FIFO1_PERR(1U)
+
+#define S_RC_ARWFIFO_PERR    13
+#define V_RC_ARWFIFO_PERR(x) ((x) << S_RC_ARWFIFO_PERR)
+#define F_RC_ARWFIFO_PERR    V_RC_ARWFIFO_PERR(1U)
+
+#define S_RC_ARIDBURSTADDRFIFO_PERR    12
+#define V_RC_ARIDBURSTADDRFIFO_PERR(x) ((x) << S_RC_ARIDBURSTADDRFIFO_PERR)
+#define F_RC_ARIDBURSTADDRFIFO_PERR    V_RC_ARIDBURSTADDRFIFO_PERR(1U)
+
+#define S_RC_CFG_FIFO_PERR    11
+#define V_RC_CFG_FIFO_PERR(x) ((x) << S_RC_CFG_FIFO_PERR)
+#define F_RC_CFG_FIFO_PERR    V_RC_CFG_FIFO_PERR(1U)
+
+#define S_RC_RSPFIFO_PERR    10
+#define V_RC_RSPFIFO_PERR(x) ((x) << S_RC_RSPFIFO_PERR)
+#define F_RC_RSPFIFO_PERR    V_RC_RSPFIFO_PERR(1U)
+
+#define S_INIC_ARIDFIFO_PERR    9
+#define V_INIC_ARIDFIFO_PERR(x) ((x) << S_INIC_ARIDFIFO_PERR)
+#define F_INIC_ARIDFIFO_PERR    V_INIC_ARIDFIFO_PERR(1U)
+
+#define S_INIC_ARWFIFO_PERR    8
+#define V_INIC_ARWFIFO_PERR(x) ((x) << S_INIC_ARWFIFO_PERR)
+#define F_INIC_ARWFIFO_PERR    V_INIC_ARWFIFO_PERR(1U)
+
+#define S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR    7
+#define V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR)
+#define F_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR    V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(1U)
+
+#define S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR    6
+#define V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR)
+#define F_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR    V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(1U)
+
+#define S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR    5
+#define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR)
+#define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR    V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(1U)
+
+#define S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR    4
+#define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR)
+#define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR    V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(1U)
+
+#define S_ARM_MA_512B_ARB_FIFO_PERR    3
+#define V_ARM_MA_512B_ARB_FIFO_PERR(x) ((x) << S_ARM_MA_512B_ARB_FIFO_PERR)
+#define F_ARM_MA_512B_ARB_FIFO_PERR    V_ARM_MA_512B_ARB_FIFO_PERR(1U)
+
+#define S_PCIE_INIC_MA_ARB_FIFO_PERR    2
+#define V_PCIE_INIC_MA_ARB_FIFO_PERR(x) ((x) << S_PCIE_INIC_MA_ARB_FIFO_PERR)
+#define F_PCIE_INIC_MA_ARB_FIFO_PERR    V_PCIE_INIC_MA_ARB_FIFO_PERR(1U)
+
+#define S_PCIE_INIC_ARB_RSPPERR    1
+#define V_PCIE_INIC_ARB_RSPPERR(x) ((x) << S_PCIE_INIC_ARB_RSPPERR)
+#define F_PCIE_INIC_ARB_RSPPERR    V_PCIE_INIC_ARB_RSPPERR(1U)
+
+#define S_ITE_CACHE_PERR    0
+#define V_ITE_CACHE_PERR(x) ((x) << S_ITE_CACHE_PERR)
+#define F_ITE_CACHE_PERR    V_ITE_CACHE_PERR(1U)
+
+#define A_ARM_PERR_INT_ENB1 0x47434
+#define A_ARM_PERR_ENABLE1 0x47438
+#define A_ARM_DEBUG_STATUS_1 0x4743c
+#define A_ARM_PCIE_MA_ADDR_REGION_DST 0x47440
+
+#define S_ADDRREGDST    0
+#define M_ADDRREGDST    0x1ffU
+#define V_ADDRREGDST(x) ((x) << S_ADDRREGDST)
+#define G_ADDRREGDST(x) (((x) >> S_ADDRREGDST) & M_ADDRREGDST)
+
+#define A_ARM_ERR_INT_CAUSE0 0x47444
+
+#define S_STRB0_ERROR    31
+#define V_STRB0_ERROR(x) ((x) << S_STRB0_ERROR)
+#define F_STRB0_ERROR    V_STRB0_ERROR(1U)
+
+#define S_STRB1_ERROR    30
+#define V_STRB1_ERROR(x) ((x) << S_STRB1_ERROR)
+#define F_STRB1_ERROR    V_STRB1_ERROR(1U)
+
+#define S_PCIE_INIC_MA_ARB_INV_RSP_TAG    29
+#define V_PCIE_INIC_MA_ARB_INV_RSP_TAG(x) ((x) << S_PCIE_INIC_MA_ARB_INV_RSP_TAG)
+#define F_PCIE_INIC_MA_ARB_INV_RSP_TAG    V_PCIE_INIC_MA_ARB_INV_RSP_TAG(1U)
+
+#define S_ERROR0_NOCMD_DATA    28
+#define V_ERROR0_NOCMD_DATA(x) ((x) << S_ERROR0_NOCMD_DATA)
+#define F_ERROR0_NOCMD_DATA    V_ERROR0_NOCMD_DATA(1U)
+
+#define S_ERROR1_NOCMD_DATA    27
+#define V_ERROR1_NOCMD_DATA(x) ((x) << S_ERROR1_NOCMD_DATA)
+#define F_ERROR1_NOCMD_DATA    V_ERROR1_NOCMD_DATA(1U)
+
+#define S_INIC_STRB_ERROR    26
+#define V_INIC_STRB_ERROR(x) ((x) << S_INIC_STRB_ERROR)
+#define F_INIC_STRB_ERROR    V_INIC_STRB_ERROR(1U)
+
+#define A_ARM_ERR_INT_ENB0 0x47448
+#define A_ARM_DEBUG_INDEX 0x47450
+#define A_ARM_DEBUG_DATA_HIGH 0x47454
+#define A_ARM_DEBUG_DATA_LOW 0x47458
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_BA0 0x47500
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_BA1 0x47504
+
+#define S_BASEADDRESS    0
+#define M_BASEADDRESS    0x3U
+#define V_BASEADDRESS(x) ((x) << S_BASEADDRESS)
+#define G_BASEADDRESS(x) (((x) >> S_BASEADDRESS) & M_BASEADDRESS)
+
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG0 0x47508
+
+#define S_WATERMARK    16
+#define M_WATERMARK    0x3ffU
+#define V_WATERMARK(x) ((x) << S_WATERMARK)
+#define G_WATERMARK(x) (((x) >> S_WATERMARK) & M_WATERMARK)
+
+#define S_SIZEMAX    0
+#define M_SIZEMAX    0x3ffU
+#define V_SIZEMAX(x) ((x) << S_SIZEMAX)
+#define G_SIZEMAX(x) (((x) >> S_SIZEMAX) & M_SIZEMAX)
+
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG1 0x4750c
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG2 0x47510
+
+#define S_CPUREADADDRESS    0
+#define M_CPUREADADDRESS    0x3ffU
+#define V_CPUREADADDRESS(x) ((x) << S_CPUREADADDRESS)
+#define G_CPUREADADDRESS(x) (((x) >> S_CPUREADADDRESS) & M_CPUREADADDRESS)
+
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG3 0x47514
+
+#define S_CPUREADADDRESSVLD    0
+#define V_CPUREADADDRESSVLD(x) ((x) << S_CPUREADADDRESSVLD)
+#define F_CPUREADADDRESSVLD    V_CPUREADADDRESSVLD(1U)
+
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 0x47518
+#define A_ARM_APB2MSI_INTERRUPT_0_STATUS 0x47600
+#define A_ARM_APB2MSI_INTERRUPT_1_STATUS 0x47604
+#define A_ARM_APB2MSI_INTERRUPT_2_STATUS 0x47608
+#define A_ARM_APB2MSI_INTERRUPT_3_STATUS 0x4760c
+#define A_ARM_APB2MSI_INTERRUPT_0_ENABLE 0x47610
+#define A_ARM_APB2MSI_INTERRUPT_1_ENABLE 0x47614
+#define A_ARM_APB2MSI_INTERRUPT_2_ENABLE 0x47618
+#define A_ARM_APB2MSI_INTERRUPT_3_ENABLE 0x4761c
+#define A_ARM_APB2MSI_INTERRUPT_PRIORITY_LEVEL 0x47620
+
+#define S_ARM_APB2MSI_INT_PRIORITY_LEVEL    0
+#define M_ARM_APB2MSI_INT_PRIORITY_LEVEL    0x7U
+#define V_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) ((x) << S_ARM_APB2MSI_INT_PRIORITY_LEVEL)
+#define G_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) (((x) >> S_ARM_APB2MSI_INT_PRIORITY_LEVEL) & M_ARM_APB2MSI_INT_PRIORITY_LEVEL)
+
+#define A_ARM_APB2MSI_MEM_READ_ADDR 0x47624
+
+#define S_ARM_APB2MSI_MEM_READ_ADDR    0
+#define M_ARM_APB2MSI_MEM_READ_ADDR    0x7fU
+#define V_ARM_APB2MSI_MEM_READ_ADDR(x) ((x) << S_ARM_APB2MSI_MEM_READ_ADDR)
+#define G_ARM_APB2MSI_MEM_READ_ADDR(x) (((x) >> S_ARM_APB2MSI_MEM_READ_ADDR) & M_ARM_APB2MSI_MEM_READ_ADDR)
+
+#define A_ARM_MSI_MEMORY_DATA 0x47628
+#define A_ARM_MSI_MEMORY_ADDR 0x4762c
+#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG5 0x47630
+
+#define S_CONFIGDONE    0
+#define V_CONFIGDONE(x) ((x) << S_CONFIGDONE)
+#define F_CONFIGDONE    V_CONFIGDONE(1U)
+
+#define A_ARM_AXI2MA_TIMERCNT 0x47640
+#define A_ARM_AXI2MA_TRTYPE 0x47644
+
+#define S_ARMMA2AXI1ARTRTYPE    3
+#define V_ARMMA2AXI1ARTRTYPE(x) ((x) << S_ARMMA2AXI1ARTRTYPE)
+#define F_ARMMA2AXI1ARTRTYPE    V_ARMMA2AXI1ARTRTYPE(1U)
+
+#define S_ARMMA2AXI1AWTRTYPE    2
+#define V_ARMMA2AXI1AWTRTYPE(x) ((x) << S_ARMMA2AXI1AWTRTYPE)
+#define F_ARMMA2AXI1AWTRTYPE    V_ARMMA2AXI1AWTRTYPE(1U)
+
+#define S_ARMMA2AXI0ARTRTYPE    1
+#define V_ARMMA2AXI0ARTRTYPE(x) ((x) << S_ARMMA2AXI0ARTRTYPE)
+#define F_ARMMA2AXI0ARTRTYPE    V_ARMMA2AXI0ARTRTYPE(1U)
+
+#define S_ARMMA2AXI0AWTRTYPE    0
+#define V_ARMMA2AXI0AWTRTYPE(x) ((x) << S_ARMMA2AXI0AWTRTYPE)
+#define F_ARMMA2AXI0AWTRTYPE    V_ARMMA2AXI0AWTRTYPE(1U)
+
+#define A_ARM_AXI2PCIE_VENDOR 0x47660
+
+#define S_T7_VENDORID    4
+#define M_T7_VENDORID    0xffffU
+#define V_T7_VENDORID(x) ((x) << S_T7_VENDORID)
+#define G_T7_VENDORID(x) (((x) >> S_T7_VENDORID) & M_T7_VENDORID)
+
+#define S_OBFFCODE    0
+#define M_OBFFCODE    0xfU
+#define V_OBFFCODE(x) ((x) << S_OBFFCODE)
+#define G_OBFFCODE(x) (((x) >> S_OBFFCODE) & M_OBFFCODE)
+
+#define A_ARM_AXI2PCIE_VENMSGHDR_DW3 0x47664
+#define A_ARM_CLUSTER_SEL 0x47668
+
+#define S_ARM_CLUSTER_SEL    0
+#define V_ARM_CLUSTER_SEL(x) ((x) << S_ARM_CLUSTER_SEL)
+#define F_ARM_CLUSTER_SEL    V_ARM_CLUSTER_SEL(1U)
+
+#define A_ARM_PWRREQ_PERMIT_ADB 0x4766c
+
+#define S_PWRQ_PERMIT_DENY_SAR    1
+#define V_PWRQ_PERMIT_DENY_SAR(x) ((x) << S_PWRQ_PERMIT_DENY_SAR)
+#define F_PWRQ_PERMIT_DENY_SAR    V_PWRQ_PERMIT_DENY_SAR(1U)
+
+#define S_PWRQREQNS_ADB    0
+#define V_PWRQREQNS_ADB(x) ((x) << S_PWRQREQNS_ADB)
+#define F_PWRQREQNS_ADB    V_PWRQREQNS_ADB(1U)
+
+#define A_ARM_CLK_REQ_ADB 0x47670
+
+#define S_CLKQREQNS_ADB    0
+#define V_CLKQREQNS_ADB(x) ((x) << S_CLKQREQNS_ADB)
+#define F_CLKQREQNS_ADB    V_CLKQREQNS_ADB(1U)
+
+#define A_ARM_WAKEUPM 0x47674
+
+#define S_DFTRSTDISABLEM_ADB    2
+#define V_DFTRSTDISABLEM_ADB(x) ((x) << S_DFTRSTDISABLEM_ADB)
+#define F_DFTRSTDISABLEM_ADB    V_DFTRSTDISABLEM_ADB(1U)
+
+#define S_DFTRSTDISABLES_ADB    1
+#define V_DFTRSTDISABLES_ADB(x) ((x) << S_DFTRSTDISABLES_ADB)
+#define F_DFTRSTDISABLES_ADB    V_DFTRSTDISABLES_ADB(1U)
+
+#define S_WAKEUPM_I_ADB    0
+#define V_WAKEUPM_I_ADB(x) ((x) << S_WAKEUPM_I_ADB)
+#define F_WAKEUPM_I_ADB    V_WAKEUPM_I_ADB(1U)
+
+#define A_ARM_CC_APB_FILTERING 0x47678
+
+#define S_CC_DFTSCANMODE    11
+#define V_CC_DFTSCANMODE(x) ((x) << S_CC_DFTSCANMODE)
+#define F_CC_DFTSCANMODE    V_CC_DFTSCANMODE(1U)
+
+#define S_CC_OTP_FILTERING_DISABLE    10
+#define V_CC_OTP_FILTERING_DISABLE(x) ((x) << S_CC_OTP_FILTERING_DISABLE)
+#define F_CC_OTP_FILTERING_DISABLE    V_CC_OTP_FILTERING_DISABLE(1U)
+
+#define S_CC_APB_FILTERING    0
+#define M_CC_APB_FILTERING    0x3ffU
+#define V_CC_APB_FILTERING(x) ((x) << S_CC_APB_FILTERING)
+#define G_CC_APB_FILTERING(x) (((x) >> S_CC_APB_FILTERING) & M_CC_APB_FILTERING)
+
+#define A_ARM_DCU_EN0 0x4767c
+#define A_ARM_DCU_EN1 0x47680
+#define A_ARM_DCU_EN2 0x47684
+#define A_ARM_DCU_EN3 0x47688
+#define A_ARM_DCU_LOCK0 0x4768c
+#define A_ARM_DCU_LOCK1 0x47690
+#define A_ARM_DCU_LOCK2 0x47694
+#define A_ARM_DCU_LOCK3 0x47698
+#define A_ARM_GPPC 0x4769c
+
+#define S_CC_SEC_DEBUG_RESET    24
+#define V_CC_SEC_DEBUG_RESET(x) ((x) << S_CC_SEC_DEBUG_RESET)
+#define F_CC_SEC_DEBUG_RESET    V_CC_SEC_DEBUG_RESET(1U)
+
+#define S_CC_DFTSE    23
+#define V_CC_DFTSE(x) ((x) << S_CC_DFTSE)
+#define F_CC_DFTSE    V_CC_DFTSE(1U)
+
+#define S_CC_DFTCGEN    22
+#define V_CC_DFTCGEN(x) ((x) << S_CC_DFTCGEN)
+#define F_CC_DFTCGEN    V_CC_DFTCGEN(1U)
+
+#define S_CC_DFTRAMHOLD    21
+#define V_CC_DFTRAMHOLD(x) ((x) << S_CC_DFTRAMHOLD)
+#define F_CC_DFTRAMHOLD    V_CC_DFTRAMHOLD(1U)
+
+#define S_CC_LOCK_BITS    12
+#define M_CC_LOCK_BITS    0x1ffU
+#define V_CC_LOCK_BITS(x) ((x) << S_CC_LOCK_BITS)
+#define G_CC_LOCK_BITS(x) (((x) >> S_CC_LOCK_BITS) & M_CC_LOCK_BITS)
+
+#define S_CC_LCS_IS_VALID    11
+#define V_CC_LCS_IS_VALID(x) ((x) << S_CC_LCS_IS_VALID)
+#define F_CC_LCS_IS_VALID    V_CC_LCS_IS_VALID(1U)
+
+#define S_CC_LCS    8
+#define M_CC_LCS    0x7U
+#define V_CC_LCS(x) ((x) << S_CC_LCS)
+#define G_CC_LCS(x) (((x) >> S_CC_LCS) & M_CC_LCS)
+
+#define S_CC_GPPC    0
+#define M_CC_GPPC    0xffU
+#define V_CC_GPPC(x) ((x) << S_CC_GPPC)
+#define G_CC_GPPC(x) (((x) >> S_CC_GPPC) & M_CC_GPPC)
+
+#define A_ARM_EMMC 0x47700
+
+#define S_EMMC_CARD_CLK_EN    31
+#define V_EMMC_CARD_CLK_EN(x) ((x) << S_EMMC_CARD_CLK_EN)
+#define F_EMMC_CARD_CLK_EN    V_EMMC_CARD_CLK_EN(1U)
+
+#define S_EMMC_LED_CONTROL    30
+#define V_EMMC_LED_CONTROL(x) ((x) << S_EMMC_LED_CONTROL)
+#define F_EMMC_LED_CONTROL    V_EMMC_LED_CONTROL(1U)
+
+#define S_EMMC_UHS1_SWVOLT_EN    29
+#define V_EMMC_UHS1_SWVOLT_EN(x) ((x) << S_EMMC_UHS1_SWVOLT_EN)
+#define F_EMMC_UHS1_SWVOLT_EN    V_EMMC_UHS1_SWVOLT_EN(1U)
+
+#define S_EMMC_UHS1_DRV_STH    27
+#define M_EMMC_UHS1_DRV_STH    0x3U
+#define V_EMMC_UHS1_DRV_STH(x) ((x) << S_EMMC_UHS1_DRV_STH)
+#define G_EMMC_UHS1_DRV_STH(x) (((x) >> S_EMMC_UHS1_DRV_STH) & M_EMMC_UHS1_DRV_STH)
+
+#define S_EMMC_SD_VDD1_ON    26
+#define V_EMMC_SD_VDD1_ON(x) ((x) << S_EMMC_SD_VDD1_ON)
+#define F_EMMC_SD_VDD1_ON    V_EMMC_SD_VDD1_ON(1U)
+
+#define S_EMMC_SD_VDD1_SEL    23
+#define M_EMMC_SD_VDD1_SEL    0x7U
+#define V_EMMC_SD_VDD1_SEL(x) ((x) << S_EMMC_SD_VDD1_SEL)
+#define G_EMMC_SD_VDD1_SEL(x) (((x) >> S_EMMC_SD_VDD1_SEL) & M_EMMC_SD_VDD1_SEL)
+
+#define S_EMMC_INTCLK_EN    22
+#define V_EMMC_INTCLK_EN(x) ((x) << S_EMMC_INTCLK_EN)
+#define F_EMMC_INTCLK_EN    V_EMMC_INTCLK_EN(1U)
+
+#define S_EMMC_CARD_CLK_FREQ_SEL    12
+#define M_EMMC_CARD_CLK_FREQ_SEL    0x3ffU
+#define V_EMMC_CARD_CLK_FREQ_SEL(x) ((x) << S_EMMC_CARD_CLK_FREQ_SEL)
+#define G_EMMC_CARD_CLK_FREQ_SEL(x) (((x) >> S_EMMC_CARD_CLK_FREQ_SEL) & M_EMMC_CARD_CLK_FREQ_SEL)
+
+#define S_EMMC_CARD_CLK_GEN_SEL    11
+#define V_EMMC_CARD_CLK_GEN_SEL(x) ((x) << S_EMMC_CARD_CLK_GEN_SEL)
+#define F_EMMC_CARD_CLK_GEN_SEL    V_EMMC_CARD_CLK_GEN_SEL(1U)
+
+#define S_EMMC_CLK2CARD_ON    10
+#define V_EMMC_CLK2CARD_ON(x) ((x) << S_EMMC_CLK2CARD_ON)
+#define F_EMMC_CLK2CARD_ON    V_EMMC_CLK2CARD_ON(1U)
+
+#define S_EMMC_CARD_CLK_STABLE    9
+#define V_EMMC_CARD_CLK_STABLE(x) ((x) << S_EMMC_CARD_CLK_STABLE)
+#define F_EMMC_CARD_CLK_STABLE    V_EMMC_CARD_CLK_STABLE(1U)
+
+#define S_EMMC_INT_BCLK_STABLE    8
+#define V_EMMC_INT_BCLK_STABLE(x) ((x) << S_EMMC_INT_BCLK_STABLE)
+#define F_EMMC_INT_BCLK_STABLE    V_EMMC_INT_BCLK_STABLE(1U)
+
+#define S_EMMC_INT_ACLK_STABLE    7
+#define V_EMMC_INT_ACLK_STABLE(x) ((x) << S_EMMC_INT_ACLK_STABLE)
+#define F_EMMC_INT_ACLK_STABLE    V_EMMC_INT_ACLK_STABLE(1U)
+
+#define S_EMMC_INT_TMCLK_STABLE    6
+#define V_EMMC_INT_TMCLK_STABLE(x) ((x) << S_EMMC_INT_TMCLK_STABLE)
+#define F_EMMC_INT_TMCLK_STABLE    V_EMMC_INT_TMCLK_STABLE(1U)
+
+#define S_EMMC_HOST_REG_VOL_STABLE    5
+#define V_EMMC_HOST_REG_VOL_STABLE(x) ((x) << S_EMMC_HOST_REG_VOL_STABLE)
+#define F_EMMC_HOST_REG_VOL_STABLE    V_EMMC_HOST_REG_VOL_STABLE(1U)
+
+#define S_EMMC_CARD_DETECT_N    4
+#define V_EMMC_CARD_DETECT_N(x) ((x) << S_EMMC_CARD_DETECT_N)
+#define F_EMMC_CARD_DETECT_N    V_EMMC_CARD_DETECT_N(1U)
+
+#define S_EMMC_CARD_WRITE_PROT    3
+#define V_EMMC_CARD_WRITE_PROT(x) ((x) << S_EMMC_CARD_WRITE_PROT)
+#define F_EMMC_CARD_WRITE_PROT    V_EMMC_CARD_WRITE_PROT(1U)
+
+#define S_EMMC_GP_IN    2
+#define V_EMMC_GP_IN(x) ((x) << S_EMMC_GP_IN)
+#define F_EMMC_GP_IN    V_EMMC_GP_IN(1U)
+
+#define S_EMMC_TEST_SCAN_MODE    1
+#define V_EMMC_TEST_SCAN_MODE(x) ((x) << S_EMMC_TEST_SCAN_MODE)
+#define F_EMMC_TEST_SCAN_MODE    V_EMMC_TEST_SCAN_MODE(1U)
+
+#define S_EMMC_FIFOINJDATAERR    0
+#define V_EMMC_FIFOINJDATAERR(x) ((x) << S_EMMC_FIFOINJDATAERR)
+#define F_EMMC_FIFOINJDATAERR    V_EMMC_FIFOINJDATAERR(1U)
+
+#define A_ARM_WAKEUPS 0x47704
+
+#define S_WAKEUPS_I_ADB    0
+#define V_WAKEUPS_I_ADB(x) ((x) << S_WAKEUPS_I_ADB)
+#define F_WAKEUPS_I_ADB    V_WAKEUPS_I_ADB(1U)
+
+#define A_ARM_CLKREQNM_ADB 0x47708
+
+#define S_CLKQREQNM_ADB    0
+#define V_CLKQREQNM_ADB(x) ((x) << S_CLKQREQNM_ADB)
+#define F_CLKQREQNM_ADB    V_CLKQREQNM_ADB(1U)
+
+#define A_ARM_ATOMICDATA0_0 0x4770c
+#define A_ARM_ATOMICDATA1_0 0x47710
+#define A_ARM_NVME_DB_EMU_INT_ENABLE 0x47740
+#define A_ARM_TCAM_WRITE_DATA 0x47744
+
+#define S_TCAM_WRITE_DATA    0
+#define M_TCAM_WRITE_DATA    0x3fffffffU
+#define V_TCAM_WRITE_DATA(x) ((x) << S_TCAM_WRITE_DATA)
+#define G_TCAM_WRITE_DATA(x) (((x) >> S_TCAM_WRITE_DATA) & M_TCAM_WRITE_DATA)
+
+#define A_ARM_TCAM_WRITE_ADDR 0x47748
+
+#define S_TCAM_WRITE_ADDR    0
+#define M_TCAM_WRITE_ADDR    0x1ffU
+#define V_TCAM_WRITE_ADDR(x) ((x) << S_TCAM_WRITE_ADDR)
+#define G_TCAM_WRITE_ADDR(x) (((x) >> S_TCAM_WRITE_ADDR) & M_TCAM_WRITE_ADDR)
+
+#define A_ARM_TCAM_READ_ADDR 0x4774c
+
+#define S_TCAM_READ_ADDR    0
+#define M_TCAM_READ_ADDR    0x1ffU
+#define V_TCAM_READ_ADDR(x) ((x) << S_TCAM_READ_ADDR)
+#define G_TCAM_READ_ADDR(x) (((x) >> S_TCAM_READ_ADDR) & M_TCAM_READ_ADDR)
+
+#define A_ARM_TCAM_CTL 0x47750
+
+#define S_TCAMCBBUSY    6
+#define V_TCAMCBBUSY(x) ((x) << S_TCAMCBBUSY)
+#define F_TCAMCBBUSY    V_TCAMCBBUSY(1U)
+
+#define S_TCAMCBPASS    5
+#define V_TCAMCBPASS(x) ((x) << S_TCAMCBPASS)
+#define F_TCAMCBPASS    V_TCAMCBPASS(1U)
+
+#define S_TCAMCBSTART    4
+#define V_TCAMCBSTART(x) ((x) << S_TCAMCBSTART)
+#define F_TCAMCBSTART    V_TCAMCBSTART(1U)
+
+#define S_TCAMRSTCB    3
+#define V_TCAMRSTCB(x) ((x) << S_TCAMRSTCB)
+#define F_TCAMRSTCB    V_TCAMRSTCB(1U)
+
+#define S_TCAM_REQBITPOS    2
+#define V_TCAM_REQBITPOS(x) ((x) << S_TCAM_REQBITPOS)
+#define F_TCAM_REQBITPOS    V_TCAM_REQBITPOS(1U)
+
+#define S_TCAM_WRITE    1
+#define V_TCAM_WRITE(x) ((x) << S_TCAM_WRITE)
+#define F_TCAM_WRITE    V_TCAM_WRITE(1U)
+
+#define S_TCAM_ENABLE    0
+#define V_TCAM_ENABLE(x) ((x) << S_TCAM_ENABLE)
+#define F_TCAM_ENABLE    V_TCAM_ENABLE(1U)
+
+#define A_ARM_TCAM_READ_DATA 0x4775c
+
+#define S_TCAM_READ_DATA    0
+#define M_TCAM_READ_DATA    0x3fffffffU
+#define V_TCAM_READ_DATA(x) ((x) << S_TCAM_READ_DATA)
+#define G_TCAM_READ_DATA(x) (((x) >> S_TCAM_READ_DATA) & M_TCAM_READ_DATA)
+
+#define A_ARM_SRAM1_WRITE_DATA 0x47760
+
+#define S_SRAM1_WRITE_DATA    0
+#define M_SRAM1_WRITE_DATA    0x7fffffU
+#define V_SRAM1_WRITE_DATA(x) ((x) << S_SRAM1_WRITE_DATA)
+#define G_SRAM1_WRITE_DATA(x) (((x) >> S_SRAM1_WRITE_DATA) & M_SRAM1_WRITE_DATA)
+
+#define A_ARM_SRAM1_WRITE_ADDR 0x47764
+
+#define S_SRAM1_WRITE_ADDR    0
+#define M_SRAM1_WRITE_ADDR    0x1ffU
+#define V_SRAM1_WRITE_ADDR(x) ((x) << S_SRAM1_WRITE_ADDR)
+#define G_SRAM1_WRITE_ADDR(x) (((x) >> S_SRAM1_WRITE_ADDR) & M_SRAM1_WRITE_ADDR)
+
+#define A_ARM_SRAM1_READ_ADDR 0x47768
+
+#define S_SRAM1_READ_ADDR    0
+#define M_SRAM1_READ_ADDR    0x1ffU
+#define V_SRAM1_READ_ADDR(x) ((x) << S_SRAM1_READ_ADDR)
+#define G_SRAM1_READ_ADDR(x) (((x) >> S_SRAM1_READ_ADDR) & M_SRAM1_READ_ADDR)
+
+#define A_ARM_SRAM1_CTL 0x4776c
+
+#define S_SRAM1_WRITE    1
+#define V_SRAM1_WRITE(x) ((x) << S_SRAM1_WRITE)
+#define F_SRAM1_WRITE    V_SRAM1_WRITE(1U)
+
+#define S_SRAM1_ENABLE    0
+#define V_SRAM1_ENABLE(x) ((x) << S_SRAM1_ENABLE)
+#define F_SRAM1_ENABLE    V_SRAM1_ENABLE(1U)
+
+#define A_ARM_SRAM1_READ_DATA 0x47770
+
+#define S_SRAM1_READ_DATA    0
+#define M_SRAM1_READ_DATA    0x7fffffU
+#define V_SRAM1_READ_DATA(x) ((x) << S_SRAM1_READ_DATA)
+#define G_SRAM1_READ_DATA(x) (((x) >> S_SRAM1_READ_DATA) & M_SRAM1_READ_DATA)
+
+#define A_ARM_SRAM2_WRITE_DATA0 0x47774
+#define A_ARM_SRAM2_WRITE_DATA1 0x47778
+#define A_ARM_SRAM2_WRITE_DATA2 0x4777c
+#define A_ARM_SRAM2_WRITE_ADDR 0x47780
+
+#define S_SRAM2_WRITE_ADDR    0
+#define M_SRAM2_WRITE_ADDR    0x1fffU
+#define V_SRAM2_WRITE_ADDR(x) ((x) << S_SRAM2_WRITE_ADDR)
+#define G_SRAM2_WRITE_ADDR(x) (((x) >> S_SRAM2_WRITE_ADDR) & M_SRAM2_WRITE_ADDR)
+
+#define A_ARM_SRAM2_READ_ADDR 0x47784
+
+#define S_SRAM2_READ_ADDR    0
+#define M_SRAM2_READ_ADDR    0x1fffU
+#define V_SRAM2_READ_ADDR(x) ((x) << S_SRAM2_READ_ADDR)
+#define G_SRAM2_READ_ADDR(x) (((x) >> S_SRAM2_READ_ADDR) & M_SRAM2_READ_ADDR)
+
+#define A_ARM_SRAM2_CTL 0x47788
+
+#define S_SRAM2_WRITE    1
+#define V_SRAM2_WRITE(x) ((x) << S_SRAM2_WRITE)
+#define F_SRAM2_WRITE    V_SRAM2_WRITE(1U)
+
+#define S_SRAM2_ENABLE    0
+#define V_SRAM2_ENABLE(x) ((x) << S_SRAM2_ENABLE)
+#define F_SRAM2_ENABLE    V_SRAM2_ENABLE(1U)
+
+#define A_ARM_SRAM2_READ_DATA0 0x4778c
+#define A_ARM_SRAM2_READ_DATA1 0x47790
+#define A_ARM_SRAM2_READ_DATA2 0x47794
+#define A_ARM_DBPROC_SRAM_CTL 0x47798
+
+#define S_DBPROC_RD_EN    0
+#define V_DBPROC_RD_EN(x) ((x) << S_DBPROC_RD_EN)
+#define F_DBPROC_RD_EN    V_DBPROC_RD_EN(1U)
+
+#define A_ARM_DBPROC_SRAM_READ_ADDR 0x4779c
+
+#define S_DBPROC_RD_ADDR    0
+#define M_DBPROC_RD_ADDR    0x1ffU
+#define V_DBPROC_RD_ADDR(x) ((x) << S_DBPROC_RD_ADDR)
+#define G_DBPROC_RD_ADDR(x) (((x) >> S_DBPROC_RD_ADDR) & M_DBPROC_RD_ADDR)
+
+#define A_ARM_DBPROC_SRAM_READ_DATA0 0x477a0
+#define A_ARM_DBPROC_SRAM_READ_DATA1 0x477a4
+#define A_ARM_DBPROC_SRAM_READ_DATA2 0x477a8
+#define A_ARM_DBPROC_SRAM_READ_DATA3 0x477ac
+#define A_ARM_ATOMICDATA0_1 0x477b0
+#define A_ARM_ATOMICDATA1_1 0x477b4
+#define A_ARM_SPIDEN 0x477b8
+
+#define S_SPIDEN    0
+#define V_SPIDEN(x) ((x) << S_SPIDEN)
+#define F_SPIDEN    V_SPIDEN(1U)
+
+#define A_ARM_RC_INT_WRITE_DATA 0x477bc
+
+#define S_RC_INT_STATUS_WRITE_DATA    0
+#define M_RC_INT_STATUS_WRITE_DATA    0x3fU
+#define V_RC_INT_STATUS_WRITE_DATA(x) ((x) << S_RC_INT_STATUS_WRITE_DATA)
+#define G_RC_INT_STATUS_WRITE_DATA(x) (((x) >> S_RC_INT_STATUS_WRITE_DATA) & M_RC_INT_STATUS_WRITE_DATA)
+
+#define A_ARM_DFT_MBI 0x477c4
+
+#define S_MBISTREQ    3
+#define V_MBISTREQ(x) ((x) << S_MBISTREQ)
+#define F_MBISTREQ    V_MBISTREQ(1U)
+
+#define S_MBISTRESETN    2
+#define V_MBISTRESETN(x) ((x) << S_MBISTRESETN)
+#define F_MBISTRESETN    V_MBISTRESETN(1U)
+
+#define S_DFTRAMHOLD    1
+#define V_DFTRAMHOLD(x) ((x) << S_DFTRAMHOLD)
+#define F_DFTRAMHOLD    V_DFTRAMHOLD(1U)
+
+#define S_DFTCGEN    0
+#define V_DFTCGEN(x) ((x) << S_DFTCGEN)
+#define F_DFTCGEN    V_DFTCGEN(1U)
+
+#define A_ARM_DBPROC_SRAM_TH_CTL 0x477c8
+
+#define S_DBPROC_TH_WR_EN    1
+#define V_DBPROC_TH_WR_EN(x) ((x) << S_DBPROC_TH_WR_EN)
+#define F_DBPROC_TH_WR_EN    V_DBPROC_TH_WR_EN(1U)
+
+#define S_DBPROC_TH_RD_EN    0
+#define V_DBPROC_TH_RD_EN(x) ((x) << S_DBPROC_TH_RD_EN)
+#define F_DBPROC_TH_RD_EN    V_DBPROC_TH_RD_EN(1U)
+
+#define A_ARM_MBISTACK 0x477d4
+
+#define S_MBISTACK    0
+#define V_MBISTACK(x) ((x) << S_MBISTACK)
+#define F_MBISTACK    V_MBISTACK(1U)
+
+#define A_ARM_MBISTADDR 0x477d8
+
+#define S_MBISTADDR    0
+#define M_MBISTADDR    0xfffU
+#define V_MBISTADDR(x) ((x) << S_MBISTADDR)
+#define G_MBISTADDR(x) (((x) >> S_MBISTADDR) & M_MBISTADDR)
+
+#define A_ARM_MBISTREADEN 0x477dc
+
+#define S_MBISTREADEN    0
+#define V_MBISTREADEN(x) ((x) << S_MBISTREADEN)
+#define F_MBISTREADEN    V_MBISTREADEN(1U)
+
+#define A_ARM_MBISTWRITEEN 0x477e0
+
+#define S_MBISTWRITEEN    0
+#define V_MBISTWRITEEN(x) ((x) << S_MBISTWRITEEN)
+#define F_MBISTWRITEEN    V_MBISTWRITEEN(1U)
+
+#define A_ARM_MBISTARRAY 0x477e4
+
+#define S_MBISTARRAY    0
+#define M_MBISTARRAY    0x3U
+#define V_MBISTARRAY(x) ((x) << S_MBISTARRAY)
+#define G_MBISTARRAY(x) (((x) >> S_MBISTARRAY) & M_MBISTARRAY)
+
+#define A_ARM_MBISTCFG 0x477e8
+
+#define S_MBISTCFG    0
+#define V_MBISTCFG(x) ((x) << S_MBISTCFG)
+#define F_MBISTCFG    V_MBISTCFG(1U)
+
+#define A_ARM_MBISTINDATA0 0x477ec
+#define A_ARM_MBISTINDATA1 0x477f0
+#define A_ARM_MBISTOUTDATA1 0x477f4
+#define A_ARM_MBISTOUTDATA0 0x477f8
+#define A_ARM_NVME_DB_EMU_EN 0x477fc
+
+#define S_NVME_DB_EN    0
+#define V_NVME_DB_EN(x) ((x) << S_NVME_DB_EN)
+#define F_NVME_DB_EN    V_NVME_DB_EN(1U)
+
+/* registers for module MC_T70 */
+#define MC_T70_BASE_ADDR 0x48000
+
+#define A_MC_IND_ADDR 0x48000
+
+#define S_T7_AUTOINCR    30
+#define M_T7_AUTOINCR    0x3U
+#define V_T7_AUTOINCR(x) ((x) << S_T7_AUTOINCR)
+#define G_T7_AUTOINCR(x) (((x) >> S_T7_AUTOINCR) & M_T7_AUTOINCR)
+
+#define S_IND_ADDR_ADDR    0
+#define M_IND_ADDR_ADDR    0x1ffffffU
+#define V_IND_ADDR_ADDR(x) ((x) << S_IND_ADDR_ADDR)
+#define G_IND_ADDR_ADDR(x) (((x) >> S_IND_ADDR_ADDR) & M_IND_ADDR_ADDR)
+
+#define A_MC_IND_DATA 0x48004
+#define A_MC_DBG_CTL 0x48018
+#define A_MC_DBG_DATA 0x4801c
+#define A_T7_MC_P_DDRPHY_RST_CTRL 0x49300
+#define A_T7_MC_P_PERFORMANCE_CTRL 0x49304
+#define A_T7_MC_P_ECC_CTRL 0x49308
+
+#define S_BISTECCHBWCTL    7
+#define M_BISTECCHBWCTL    0x3U
+#define V_BISTECCHBWCTL(x) ((x) << S_BISTECCHBWCTL)
+#define G_BISTECCHBWCTL(x) (((x) >> S_BISTECCHBWCTL) & M_BISTECCHBWCTL)
+
+#define S_BISTTESTMODE    6
+#define V_BISTTESTMODE(x) ((x) << S_BISTTESTMODE)
+#define F_BISTTESTMODE    V_BISTTESTMODE(1U)
+
+#define S_RMW_CTL_CFG    4
+#define M_RMW_CTL_CFG    0x3U
+#define V_RMW_CTL_CFG(x) ((x) << S_RMW_CTL_CFG)
+#define G_RMW_CTL_CFG(x) (((x) >> S_RMW_CTL_CFG) & M_RMW_CTL_CFG)
+
+#define A_MC_P_DDRCTL_INT_ENABLE 0x4930c
+
+#define S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE    5
+#define V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE)
+#define F_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE    V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(1U)
+
+#define S_HIF_RDATA_CRC_ERR_DCH1_ENABLE    4
+#define V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_DCH1_ENABLE)
+#define F_HIF_RDATA_CRC_ERR_DCH1_ENABLE    V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(1U)
+
+#define S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE    3
+#define V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE)
+#define F_HIF_RDATA_ADDR_ERR_DCH1_ENABLE    V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(1U)
+
+#define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE    2
+#define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE)
+#define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(1U)
+
+#define S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE    1
+#define V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE)
+#define F_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE    V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(1U)
+
+#define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE    0
+#define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE)
+#define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE    V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(1U)
+
+#define A_MC_P_DDRCTL_INT_CAUSE 0x49310
+
+#define S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    25
+#define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
+#define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
+
+#define S_WR_CRC_ERR_INTR_DCH1_CAUSE    24
+#define V_WR_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH1_CAUSE)
+#define F_WR_CRC_ERR_INTR_DCH1_CAUSE    V_WR_CRC_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE    23
+#define V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
+#define F_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
+
+#define S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    22
+#define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
+#define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
+
+#define S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE    21
+#define V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE)
+#define F_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE    V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(1U)
+
+#define S_SWCMD_ERR_INTR_DCH1_CAUSE    20
+#define V_SWCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH1_CAUSE)
+#define F_SWCMD_ERR_INTR_DCH1_CAUSE    V_SWCMD_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_DUCMD_ERR_INTR_DCH1_CAUSE    19
+#define V_DUCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH1_CAUSE)
+#define F_DUCMD_ERR_INTR_DCH1_CAUSE    V_DUCMD_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_LCCMD_ERR_INTR_DCH1_CAUSE    18
+#define V_LCCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH1_CAUSE)
+#define F_LCCMD_ERR_INTR_DCH1_CAUSE    V_LCCMD_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_CTRLUPD_ERR_INTR_DCH1_CAUSE    17
+#define V_CTRLUPD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH1_CAUSE)
+#define F_CTRLUPD_ERR_INTR_DCH1_CAUSE    V_CTRLUPD_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_RFM_ALERT_INTR_DCH1_CAUSE    16
+#define V_RFM_ALERT_INTR_DCH1_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH1_CAUSE)
+#define F_RFM_ALERT_INTR_DCH1_CAUSE    V_RFM_ALERT_INTR_DCH1_CAUSE(1U)
+
+#define S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    15
+#define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
+#define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
+
+#define S_WR_CRC_ERR_INTR_DCH0_CAUSE    14
+#define V_WR_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH0_CAUSE)
+#define F_WR_CRC_ERR_INTR_DCH0_CAUSE    V_WR_CRC_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE    13
+#define V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
+#define F_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
+
+#define S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    12
+#define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
+#define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
+
+#define S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE    11
+#define V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE)
+#define F_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE    V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(1U)
+
+#define S_SWCMD_ERR_INTR_DCH0_CAUSE    10
+#define V_SWCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH0_CAUSE)
+#define F_SWCMD_ERR_INTR_DCH0_CAUSE    V_SWCMD_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_DUCMD_ERR_INTR_DCH0_CAUSE    9
+#define V_DUCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH0_CAUSE)
+#define F_DUCMD_ERR_INTR_DCH0_CAUSE    V_DUCMD_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_LCCMD_ERR_INTR_DCH0_CAUSE    8
+#define V_LCCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH0_CAUSE)
+#define F_LCCMD_ERR_INTR_DCH0_CAUSE    V_LCCMD_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_CTRLUPD_ERR_INTR_DCH0_CAUSE    7
+#define V_CTRLUPD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH0_CAUSE)
+#define F_CTRLUPD_ERR_INTR_DCH0_CAUSE    V_CTRLUPD_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_RFM_ALERT_INTR_DCH0_CAUSE    6
+#define V_RFM_ALERT_INTR_DCH0_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH0_CAUSE)
+#define F_RFM_ALERT_INTR_DCH0_CAUSE    V_RFM_ALERT_INTR_DCH0_CAUSE(1U)
+
+#define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE    5
+#define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE)
+#define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE    4
+#define V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE)
+#define F_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE    V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE    3
+#define V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE)
+#define F_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE    V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(1U)
+
+#define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE    2
+#define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE)
+#define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE    1
+#define V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE)
+#define F_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE    V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(1U)
+
+#define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE    0
+#define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE)
+#define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE    V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(1U)
+
+#define A_T7_MC_P_PAR_ENABLE 0x49314
+
+#define S_HIF_WDATA_Q_PARERR_DCH1_ENABLE    13
+#define V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_ENABLE)
+#define F_HIF_WDATA_Q_PARERR_DCH1_ENABLE    V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(1U)
+
+#define S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE    12
+#define V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE)
+#define F_DDRCTL_ECC_CE_PAR_DCH1_ENABLE    V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(1U)
+
+#define S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE    11
+#define V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE)
+#define F_DDRCTL_ECC_CE_PAR_DCH0_ENABLE    V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(1U)
+
+#define S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE    10
+#define V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE)
+#define F_DDRCTL_ECC_UE_PAR_DCH1_ENABLE    V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(1U)
+
+#define S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE    9
+#define V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE)
+#define F_DDRCTL_ECC_UE_PAR_DCH0_ENABLE    V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(1U)
+
+#define S_WDATARAM_PARERR_DCH1_ENABLE    8
+#define V_WDATARAM_PARERR_DCH1_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH1_ENABLE)
+#define F_WDATARAM_PARERR_DCH1_ENABLE    V_WDATARAM_PARERR_DCH1_ENABLE(1U)
+
+#define S_WDATARAM_PARERR_DCH0_ENABLE    7
+#define V_WDATARAM_PARERR_DCH0_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH0_ENABLE)
+#define F_WDATARAM_PARERR_DCH0_ENABLE    V_WDATARAM_PARERR_DCH0_ENABLE(1U)
+
+#define S_BIST_ADDR_FIFO_PARERR_ENABLE    6
+#define V_BIST_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_ENABLE)
+#define F_BIST_ADDR_FIFO_PARERR_ENABLE    V_BIST_ADDR_FIFO_PARERR_ENABLE(1U)
+
+#define S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE    5
+#define V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE)
+#define F_BIST_ERR_ADDR_FIFO_PARERR_ENABLE    V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(1U)
+
+#define S_HIF_WDATA_Q_PARERR_DCH0_ENABLE    4
+#define V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_ENABLE)
+#define F_HIF_WDATA_Q_PARERR_DCH0_ENABLE    V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(1U)
+
+#define S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE    3
+#define V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE)
+#define F_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE    V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(1U)
+
+#define S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE    2
+#define V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE)
+#define F_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE    V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(1U)
+
+#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE    1
+#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE)
+#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(1U)
+
+#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE    0
+#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE)
+#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(1U)
+
+#define A_T7_MC_P_PAR_CAUSE 0x49318
+
+#define S_HIF_WDATA_Q_PARERR_DCH1_CAUSE    13
+#define V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_CAUSE)
+#define F_HIF_WDATA_Q_PARERR_DCH1_CAUSE    V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(1U)
+
+#define S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE    12
+#define V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE)
+#define F_DDRCTL_ECC_CE_PAR_DCH1_CAUSE    V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(1U)
+
+#define S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE    11
+#define V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE)
+#define F_DDRCTL_ECC_CE_PAR_DCH0_CAUSE    V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(1U)
+
+#define S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE    10
+#define V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE)
+#define F_DDRCTL_ECC_UE_PAR_DCH1_CAUSE    V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(1U)
+
+#define S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE    9
+#define V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE)
+#define F_DDRCTL_ECC_UE_PAR_DCH0_CAUSE    V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(1U)
+
+#define S_WDATARAM_PARERR_DCH1_CAUSE    8
+#define V_WDATARAM_PARERR_DCH1_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH1_CAUSE)
+#define F_WDATARAM_PARERR_DCH1_CAUSE    V_WDATARAM_PARERR_DCH1_CAUSE(1U)
+
+#define S_WDATARAM_PARERR_DCH0_CAUSE    7
+#define V_WDATARAM_PARERR_DCH0_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH0_CAUSE)
+#define F_WDATARAM_PARERR_DCH0_CAUSE    V_WDATARAM_PARERR_DCH0_CAUSE(1U)
+
+#define S_BIST_ADDR_FIFO_PARERR_CAUSE    6
+#define V_BIST_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_CAUSE)
+#define F_BIST_ADDR_FIFO_PARERR_CAUSE    V_BIST_ADDR_FIFO_PARERR_CAUSE(1U)
+
+#define S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE    5
+#define V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE)
+#define F_BIST_ERR_ADDR_FIFO_PARERR_CAUSE    V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(1U)
+
+#define S_HIF_WDATA_Q_PARERR_DCH0_CAUSE    4
+#define V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_CAUSE)
+#define F_HIF_WDATA_Q_PARERR_DCH0_CAUSE    V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(1U)
+
+#define S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE    3
+#define V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE)
+#define F_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE    V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(1U)
+
+#define S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE    2
+#define V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE)
+#define F_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE    V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(1U)
+
+#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE    1
+#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE)
+#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(1U)
+
+#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE    0
+#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE)
+#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(1U)
+
+#define A_T7_MC_P_INT_ENABLE 0x4931c
+
+#define S_DDRPHY_INT_ENABLE    4
+#define V_DDRPHY_INT_ENABLE(x) ((x) << S_DDRPHY_INT_ENABLE)
+#define F_DDRPHY_INT_ENABLE    V_DDRPHY_INT_ENABLE(1U)
+
+#define S_DDRCTL_INT_ENABLE    3
+#define V_DDRCTL_INT_ENABLE(x) ((x) << S_DDRCTL_INT_ENABLE)
+#define F_DDRCTL_INT_ENABLE    V_DDRCTL_INT_ENABLE(1U)
+
+#define S_T7_ECC_CE_INT_ENABLE    2
+#define V_T7_ECC_CE_INT_ENABLE(x) ((x) << S_T7_ECC_CE_INT_ENABLE)
+#define F_T7_ECC_CE_INT_ENABLE    V_T7_ECC_CE_INT_ENABLE(1U)
+
+#define S_T7_ECC_UE_INT_ENABLE    1
+#define V_T7_ECC_UE_INT_ENABLE(x) ((x) << S_T7_ECC_UE_INT_ENABLE)
+#define F_T7_ECC_UE_INT_ENABLE    V_T7_ECC_UE_INT_ENABLE(1U)
+
+#define A_T7_MC_P_INT_CAUSE 0x49320
+
+#define S_DDRPHY_INT_CAUSE    4
+#define V_DDRPHY_INT_CAUSE(x) ((x) << S_DDRPHY_INT_CAUSE)
+#define F_DDRPHY_INT_CAUSE    V_DDRPHY_INT_CAUSE(1U)
+
+#define S_DDRCTL_INT_CAUSE    3
+#define V_DDRCTL_INT_CAUSE(x) ((x) << S_DDRCTL_INT_CAUSE)
+#define F_DDRCTL_INT_CAUSE    V_DDRCTL_INT_CAUSE(1U)
+
+#define S_T7_ECC_CE_INT_CAUSE    2
+#define V_T7_ECC_CE_INT_CAUSE(x) ((x) << S_T7_ECC_CE_INT_CAUSE)
+#define F_T7_ECC_CE_INT_CAUSE    V_T7_ECC_CE_INT_CAUSE(1U)
+
+#define S_T7_ECC_UE_INT_CAUSE    1
+#define V_T7_ECC_UE_INT_CAUSE(x) ((x) << S_T7_ECC_UE_INT_CAUSE)
+#define F_T7_ECC_UE_INT_CAUSE    V_T7_ECC_UE_INT_CAUSE(1U)
+
+#define A_MC_P_ECC_UE_INT_ENABLE 0x49324
+
+#define S_BIST_RSP_SRAM_UERR_ENABLE    0
+#define V_BIST_RSP_SRAM_UERR_ENABLE(x) ((x) << S_BIST_RSP_SRAM_UERR_ENABLE)
+#define F_BIST_RSP_SRAM_UERR_ENABLE    V_BIST_RSP_SRAM_UERR_ENABLE(1U)
+
+#define A_MC_P_ECC_UE_INT_CAUSE 0x49328
+
+#define S_BIST_RSP_SRAM_UERR_CAUSE    0
+#define V_BIST_RSP_SRAM_UERR_CAUSE(x) ((x) << S_BIST_RSP_SRAM_UERR_CAUSE)
+#define F_BIST_RSP_SRAM_UERR_CAUSE    V_BIST_RSP_SRAM_UERR_CAUSE(1U)
+
+#define A_T7_MC_P_ECC_STATUS 0x4932c
+#define A_T7_MC_P_PHY_CTRL 0x49330
+#define A_T7_MC_P_STATIC_CFG_STATUS 0x49334
+
+#define S_DFIFREQRATIO    27
+#define V_DFIFREQRATIO(x) ((x) << S_DFIFREQRATIO)
+#define F_DFIFREQRATIO    V_DFIFREQRATIO(1U)
+
+#define S_STATIC_DDR5_HBW_CHANNEL    3
+#define V_STATIC_DDR5_HBW_CHANNEL(x) ((x) << S_STATIC_DDR5_HBW_CHANNEL)
+#define F_STATIC_DDR5_HBW_CHANNEL    V_STATIC_DDR5_HBW_CHANNEL(1U)
+
+#define S_STATIC_DDR5_HBW    2
+#define V_STATIC_DDR5_HBW(x) ((x) << S_STATIC_DDR5_HBW)
+#define F_STATIC_DDR5_HBW    V_STATIC_DDR5_HBW(1U)
+
+#define S_T7_STATIC_WIDTH    1
+#define V_T7_STATIC_WIDTH(x) ((x) << S_T7_STATIC_WIDTH)
+#define F_T7_STATIC_WIDTH    V_T7_STATIC_WIDTH(1U)
+
+#define A_T7_MC_P_CORE_PCTL_STAT 0x49338
+#define A_T7_MC_P_DEBUG_CNT 0x4933c
+#define A_T7_MC_CE_ERR_DATA_RDATA 0x49340
+#define A_T7_MC_UE_ERR_DATA_RDATA 0x49380
+#define A_T7_MC_CE_ADDR 0x493c0
+#define A_T7_MC_UE_ADDR 0x493c4
+#define A_T7_MC_P_DEEP_SLEEP 0x493c8
+#define A_T7_MC_P_FPGA_BONUS 0x493cc
+#define A_T7_MC_P_DEBUG_CFG 0x493d0
+#define A_T7_MC_P_DEBUG_RPT 0x493d4
+#define A_T7_MC_P_PHY_ADR_CK_EN 0x493d8
+#define A_MC_P_WDATARAM_INIT 0x493dc
+
+#define S_ENABLE_DCH1    1
+#define V_ENABLE_DCH1(x) ((x) << S_ENABLE_DCH1)
+#define F_ENABLE_DCH1    V_ENABLE_DCH1(1U)
+
+#define S_ENABLE_DCH0    0
+#define V_ENABLE_DCH0(x) ((x) << S_ENABLE_DCH0)
+#define F_ENABLE_DCH0    V_ENABLE_DCH0(1U)
+
+#define A_T7_MC_CE_ERR_ECC_DATA0 0x493e0
+#define A_T7_MC_CE_ERR_ECC_DATA1 0x493e4
+#define A_T7_MC_UE_ERR_ECC_DATA0 0x493e8
+#define A_T7_MC_UE_ERR_ECC_DATA1 0x493ec
+#define A_T7_MC_P_RMW_PRIO 0x493f0
+#define A_T7_MC_P_BIST_CMD 0x49400
+
+#define S_FIFO_ERROR_FLAG    30
+#define V_FIFO_ERROR_FLAG(x) ((x) << S_FIFO_ERROR_FLAG)
+#define F_FIFO_ERROR_FLAG    V_FIFO_ERROR_FLAG(1U)
+
+#define A_T7_MC_P_BIST_CMD_ADDR 0x49404
+
+#define S_T7_VALUE    0
+#define M_T7_VALUE    0x1fffffffU
+#define V_T7_VALUE(x) ((x) << S_T7_VALUE)
+#define G_T7_VALUE(x) (((x) >> S_T7_VALUE) & M_T7_VALUE)
+
+#define A_MC_P_BIST_NUM_BURST 0x49408
+#define A_T7_MC_P_BIST_DATA_PATTERN 0x4940c
+
+#define S_DATA_TYPE    0
+#define M_DATA_TYPE    0xfU
+#define V_DATA_TYPE(x) ((x) << S_DATA_TYPE)
+#define G_DATA_TYPE(x) (((x) >> S_DATA_TYPE) & M_DATA_TYPE)
+
+#define A_T7_MC_P_BIST_CRC_SEED 0x49410
+#define A_T7_MC_P_BIST_NUM_ERR 0x49460
+#define A_MC_P_BIST_ERR_ADDR 0x49464
+
+#define S_ERROR_ADDR    0
+#define M_ERROR_ADDR    0x3fffffffU
+#define V_ERROR_ADDR(x) ((x) << S_ERROR_ADDR)
+#define G_ERROR_ADDR(x) (((x) >> S_ERROR_ADDR) & M_ERROR_ADDR)
+
+#define A_MC_P_BIST_USER_RWEDATA 0x49468
+#define A_MC_REGB_DDRC_CH0_SCHED0 0x10380
+
+#define S_OPT_VPRW_SCH    31
+#define V_OPT_VPRW_SCH(x) ((x) << S_OPT_VPRW_SCH)
+#define F_OPT_VPRW_SCH    V_OPT_VPRW_SCH(1U)
+
+#define S_DIS_SPECULATIVE_ACT    30
+#define V_DIS_SPECULATIVE_ACT(x) ((x) << S_DIS_SPECULATIVE_ACT)
+#define F_DIS_SPECULATIVE_ACT    V_DIS_SPECULATIVE_ACT(1U)
+
+#define S_OPT_ACT_LAT    27
+#define V_OPT_ACT_LAT(x) ((x) << S_OPT_ACT_LAT)
+#define F_OPT_ACT_LAT    V_OPT_ACT_LAT(1U)
+
+#define S_LPR_NUM_ENTRIES    8
+#define M_LPR_NUM_ENTRIES    0x3fU
+#define V_LPR_NUM_ENTRIES(x) ((x) << S_LPR_NUM_ENTRIES)
+#define G_LPR_NUM_ENTRIES(x) (((x) >> S_LPR_NUM_ENTRIES) & M_LPR_NUM_ENTRIES)
+
+#define S_AUTOPRE_RMW    7
+#define V_AUTOPRE_RMW(x) ((x) << S_AUTOPRE_RMW)
+#define F_AUTOPRE_RMW    V_AUTOPRE_RMW(1U)
+
+#define S_DIS_OPT_NTT_BY_PRE    6
+#define V_DIS_OPT_NTT_BY_PRE(x) ((x) << S_DIS_OPT_NTT_BY_PRE)
+#define F_DIS_OPT_NTT_BY_PRE    V_DIS_OPT_NTT_BY_PRE(1U)
+
+#define S_DIS_OPT_NTT_BY_ACT    5
+#define V_DIS_OPT_NTT_BY_ACT(x) ((x) << S_DIS_OPT_NTT_BY_ACT)
+#define F_DIS_OPT_NTT_BY_ACT    V_DIS_OPT_NTT_BY_ACT(1U)
+
+#define S_OPT_WRCAM_FILL_LEVEL    4
+#define V_OPT_WRCAM_FILL_LEVEL(x) ((x) << S_OPT_WRCAM_FILL_LEVEL)
+#define F_OPT_WRCAM_FILL_LEVEL    V_OPT_WRCAM_FILL_LEVEL(1U)
+
+#define S_PAGECLOSE    2
+#define V_PAGECLOSE(x) ((x) << S_PAGECLOSE)
+#define F_PAGECLOSE    V_PAGECLOSE(1U)
+
+#define S_PREFER_WRITE    1
+#define V_PREFER_WRITE(x) ((x) << S_PREFER_WRITE)
+#define F_PREFER_WRITE    V_PREFER_WRITE(1U)
+
+#define A_MC_REGB_DDRC_CH0_ECCCFG0 0x10600
+
+#define S_DIS_SCRUB    23
+#define V_DIS_SCRUB(x) ((x) << S_DIS_SCRUB)
+#define F_DIS_SCRUB    V_DIS_SCRUB(1U)
+
+#define S_ECC_TYPE    4
+#define M_ECC_TYPE    0x3U
+#define V_ECC_TYPE(x) ((x) << S_ECC_TYPE)
+#define G_ECC_TYPE(x) (((x) >> S_ECC_TYPE) & M_ECC_TYPE)
+
+#define S_TEST_MODE    3
+#define V_TEST_MODE(x) ((x) << S_TEST_MODE)
+#define F_TEST_MODE    V_TEST_MODE(1U)
+
+#define S_ECC_MODE    0
+#define M_ECC_MODE    0x7U
+#define V_ECC_MODE(x) ((x) << S_ECC_MODE)
+#define G_ECC_MODE(x) (((x) >> S_ECC_MODE) & M_ECC_MODE)
+
+#define A_MC_REGB_DDRC_CH0_ECCCFG1 0x10604
+
+#define S_DATA_POISON_BIT    1
+#define V_DATA_POISON_BIT(x) ((x) << S_DATA_POISON_BIT)
+#define F_DATA_POISON_BIT    V_DATA_POISON_BIT(1U)
+
+#define S_DATA_POISON_EN    0
+#define V_DATA_POISON_EN(x) ((x) << S_DATA_POISON_EN)
+#define F_DATA_POISON_EN    V_DATA_POISON_EN(1U)
+
+#define A_MC_REGB_DDRC_CH0_ECCSTAT 0x10608
+
+#define S_ECC_UNCORRECTED_ERR    16
+#define M_ECC_UNCORRECTED_ERR    0xffU
+#define V_ECC_UNCORRECTED_ERR(x) ((x) << S_ECC_UNCORRECTED_ERR)
+#define G_ECC_UNCORRECTED_ERR(x) (((x) >> S_ECC_UNCORRECTED_ERR) & M_ECC_UNCORRECTED_ERR)
+
+#define S_ECC_CORRECTED_ERR    8
+#define M_ECC_CORRECTED_ERR    0xffU
+#define V_ECC_CORRECTED_ERR(x) ((x) << S_ECC_CORRECTED_ERR)
+#define G_ECC_CORRECTED_ERR(x) (((x) >> S_ECC_CORRECTED_ERR) & M_ECC_CORRECTED_ERR)
+
+#define S_ECC_CORRECTED_BIT_NUM    0
+#define M_ECC_CORRECTED_BIT_NUM    0x7fU
+#define V_ECC_CORRECTED_BIT_NUM(x) ((x) << S_ECC_CORRECTED_BIT_NUM)
+#define G_ECC_CORRECTED_BIT_NUM(x) (((x) >> S_ECC_CORRECTED_BIT_NUM) & M_ECC_CORRECTED_BIT_NUM)
+
+#define A_MC_REGB_DDRC_CH0_ECCCTL 0x1060c
+
+#define S_ECC_UNCORRECTED_ERR_INTR_FORCE    17
+#define V_ECC_UNCORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_FORCE)
+#define F_ECC_UNCORRECTED_ERR_INTR_FORCE    V_ECC_UNCORRECTED_ERR_INTR_FORCE(1U)
+
+#define S_ECC_CORRECTED_ERR_INTR_FORCE    16
+#define V_ECC_CORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_CORRECTED_ERR_INTR_FORCE)
+#define F_ECC_CORRECTED_ERR_INTR_FORCE    V_ECC_CORRECTED_ERR_INTR_FORCE(1U)
+
+#define S_ECC_UNCORRECTED_ERR_INTR_EN    9
+#define V_ECC_UNCORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_EN)
+#define F_ECC_UNCORRECTED_ERR_INTR_EN    V_ECC_UNCORRECTED_ERR_INTR_EN(1U)
+
+#define S_ECC_CORRECTED_ERR_INTR_EN    8
+#define V_ECC_CORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_CORRECTED_ERR_INTR_EN)
+#define F_ECC_CORRECTED_ERR_INTR_EN    V_ECC_CORRECTED_ERR_INTR_EN(1U)
+
+#define S_ECC_UNCORR_ERR_CNT_CLR    3
+#define V_ECC_UNCORR_ERR_CNT_CLR(x) ((x) << S_ECC_UNCORR_ERR_CNT_CLR)
+#define F_ECC_UNCORR_ERR_CNT_CLR    V_ECC_UNCORR_ERR_CNT_CLR(1U)
+
+#define S_ECC_CORR_ERR_CNT_CLR    2
+#define V_ECC_CORR_ERR_CNT_CLR(x) ((x) << S_ECC_CORR_ERR_CNT_CLR)
+#define F_ECC_CORR_ERR_CNT_CLR    V_ECC_CORR_ERR_CNT_CLR(1U)
+
+#define S_ECC_UNCORRECTED_ERR_CLR    1
+#define V_ECC_UNCORRECTED_ERR_CLR(x) ((x) << S_ECC_UNCORRECTED_ERR_CLR)
+#define F_ECC_UNCORRECTED_ERR_CLR    V_ECC_UNCORRECTED_ERR_CLR(1U)
+
+#define S_ECC_CORRECTED_ERR_CLR    0
+#define V_ECC_CORRECTED_ERR_CLR(x) ((x) << S_ECC_CORRECTED_ERR_CLR)
+#define F_ECC_CORRECTED_ERR_CLR    V_ECC_CORRECTED_ERR_CLR(1U)
+
+#define A_MC_REGB_DDRC_CH0_ECCERRCNT 0x10610
+
+#define S_ECC_UNCORR_ERR_CNT    16
+#define M_ECC_UNCORR_ERR_CNT    0xffffU
+#define V_ECC_UNCORR_ERR_CNT(x) ((x) << S_ECC_UNCORR_ERR_CNT)
+#define G_ECC_UNCORR_ERR_CNT(x) (((x) >> S_ECC_UNCORR_ERR_CNT) & M_ECC_UNCORR_ERR_CNT)
+
+#define S_ECC_CORR_ERR_CNT    0
+#define M_ECC_CORR_ERR_CNT    0xffffU
+#define V_ECC_CORR_ERR_CNT(x) ((x) << S_ECC_CORR_ERR_CNT)
+#define G_ECC_CORR_ERR_CNT(x) (((x) >> S_ECC_CORR_ERR_CNT) & M_ECC_CORR_ERR_CNT)
+
+#define A_MC_REGB_DDRC_CH0_ECCCADDR0 0x10614
+
+#define S_ECC_CORR_RANK    24
+#define V_ECC_CORR_RANK(x) ((x) << S_ECC_CORR_RANK)
+#define F_ECC_CORR_RANK    V_ECC_CORR_RANK(1U)
+
+#define S_ECC_CORR_ROW    0
+#define M_ECC_CORR_ROW    0x3ffffU
+#define V_ECC_CORR_ROW(x) ((x) << S_ECC_CORR_ROW)
+#define G_ECC_CORR_ROW(x) (((x) >> S_ECC_CORR_ROW) & M_ECC_CORR_ROW)
+
+#define A_MC_REGB_DDRC_CH0_ECCCADDR1 0x10618
+
+#define S_ECC_CORR_BG    24
+#define M_ECC_CORR_BG    0x7U
+#define V_ECC_CORR_BG(x) ((x) << S_ECC_CORR_BG)
+#define G_ECC_CORR_BG(x) (((x) >> S_ECC_CORR_BG) & M_ECC_CORR_BG)
+
+#define S_ECC_CORR_BANK    16
+#define M_ECC_CORR_BANK    0x3U
+#define V_ECC_CORR_BANK(x) ((x) << S_ECC_CORR_BANK)
+#define G_ECC_CORR_BANK(x) (((x) >> S_ECC_CORR_BANK) & M_ECC_CORR_BANK)
+
+#define S_ECC_CORR_COL    0
+#define M_ECC_CORR_COL    0x7ffU
+#define V_ECC_CORR_COL(x) ((x) << S_ECC_CORR_COL)
+#define G_ECC_CORR_COL(x) (((x) >> S_ECC_CORR_COL) & M_ECC_CORR_COL)
+
+#define A_MC_REGB_DDRC_CH0_ECCCSYN0 0x1061c
+#define A_MC_REGB_DDRC_CH0_ECCCSYN1 0x10620
+#define A_MC_REGB_DDRC_CH0_ECCCSYN2 0x10624
+
+#define S_CB_CORR_SYNDROME    16
+#define M_CB_CORR_SYNDROME    0xffU
+#define V_CB_CORR_SYNDROME(x) ((x) << S_CB_CORR_SYNDROME)
+#define G_CB_CORR_SYNDROME(x) (((x) >> S_CB_CORR_SYNDROME) & M_CB_CORR_SYNDROME)
+
+#define S_ECC_CORR_SYNDROMES_71_64    0
+#define M_ECC_CORR_SYNDROMES_71_64    0xffU
+#define V_ECC_CORR_SYNDROMES_71_64(x) ((x) << S_ECC_CORR_SYNDROMES_71_64)
+#define G_ECC_CORR_SYNDROMES_71_64(x) (((x) >> S_ECC_CORR_SYNDROMES_71_64) & M_ECC_CORR_SYNDROMES_71_64)
+
+#define A_MC_REGB_DDRC_CH0_ECCBITMASK0 0x10628
+#define A_MC_REGB_DDRC_CH0_ECCBITMASK1 0x1062c
+#define A_MC_REGB_DDRC_CH0_ECCBITMASK2 0x10630
+
+#define S_ECC_CORR_BIT_MASK_71_64    0
+#define M_ECC_CORR_BIT_MASK_71_64    0xffU
+#define V_ECC_CORR_BIT_MASK_71_64(x) ((x) << S_ECC_CORR_BIT_MASK_71_64)
+#define G_ECC_CORR_BIT_MASK_71_64(x) (((x) >> S_ECC_CORR_BIT_MASK_71_64) & M_ECC_CORR_BIT_MASK_71_64)
+
+#define A_MC_REGB_DDRC_CH0_ECCUADDR0 0x10634
+
+#define S_ECC_UNCORR_RANK    24
+#define V_ECC_UNCORR_RANK(x) ((x) << S_ECC_UNCORR_RANK)
+#define F_ECC_UNCORR_RANK    V_ECC_UNCORR_RANK(1U)
+
+#define S_ECC_UNCORR_ROW    0
+#define M_ECC_UNCORR_ROW    0x3ffffU
+#define V_ECC_UNCORR_ROW(x) ((x) << S_ECC_UNCORR_ROW)
+#define G_ECC_UNCORR_ROW(x) (((x) >> S_ECC_UNCORR_ROW) & M_ECC_UNCORR_ROW)
+
+#define A_MC_REGB_DDRC_CH0_ECCUADDR1 0x10638
+
+#define S_ECC_UNCORR_BG    24
+#define M_ECC_UNCORR_BG    0x7U
+#define V_ECC_UNCORR_BG(x) ((x) << S_ECC_UNCORR_BG)
+#define G_ECC_UNCORR_BG(x) (((x) >> S_ECC_UNCORR_BG) & M_ECC_UNCORR_BG)
+
+#define S_ECC_UNCORR_BANK    16
+#define M_ECC_UNCORR_BANK    0x3U
+#define V_ECC_UNCORR_BANK(x) ((x) << S_ECC_UNCORR_BANK)
+#define G_ECC_UNCORR_BANK(x) (((x) >> S_ECC_UNCORR_BANK) & M_ECC_UNCORR_BANK)
+
+#define S_ECC_UNCORR_COL    0
+#define M_ECC_UNCORR_COL    0x7ffU
+#define V_ECC_UNCORR_COL(x) ((x) << S_ECC_UNCORR_COL)
+#define G_ECC_UNCORR_COL(x) (((x) >> S_ECC_UNCORR_COL) & M_ECC_UNCORR_COL)
+
+#define A_MC_REGB_DDRC_CH0_ECCUSYN0 0x1063c
+#define A_MC_REGB_DDRC_CH0_ECCUSYN1 0x10640
+#define A_MC_REGB_DDRC_CH0_ECCUSYN2 0x10644
+
+#define S_CB_UNCORR_SYNDROME    16
+#define M_CB_UNCORR_SYNDROME    0xffU
+#define V_CB_UNCORR_SYNDROME(x) ((x) << S_CB_UNCORR_SYNDROME)
+#define G_CB_UNCORR_SYNDROME(x) (((x) >> S_CB_UNCORR_SYNDROME) & M_CB_UNCORR_SYNDROME)
+
+#define S_ECC_UNCORR_SYNDROMES_71_64    0
+#define M_ECC_UNCORR_SYNDROMES_71_64    0xffU
+#define V_ECC_UNCORR_SYNDROMES_71_64(x) ((x) << S_ECC_UNCORR_SYNDROMES_71_64)
+#define G_ECC_UNCORR_SYNDROMES_71_64(x) (((x) >> S_ECC_UNCORR_SYNDROMES_71_64) & M_ECC_UNCORR_SYNDROMES_71_64)
+
+#define A_MC_REGB_DDRC_CH0_ECCPOISONADDR0 0x10648
+
+#define S_ECC_POISON_RANK    24
+#define V_ECC_POISON_RANK(x) ((x) << S_ECC_POISON_RANK)
+#define F_ECC_POISON_RANK    V_ECC_POISON_RANK(1U)
+
+#define S_ECC_POISON_COL    0
+#define M_ECC_POISON_COL    0xfffU
+#define V_ECC_POISON_COL(x) ((x) << S_ECC_POISON_COL)
+#define G_ECC_POISON_COL(x) (((x) >> S_ECC_POISON_COL) & M_ECC_POISON_COL)
+
+#define A_MC_REGB_DDRC_CH0_ECCPOISONADDR1 0x1064c
+
+#define S_ECC_POISON_BG    28
+#define M_ECC_POISON_BG    0x7U
+#define V_ECC_POISON_BG(x) ((x) << S_ECC_POISON_BG)
+#define G_ECC_POISON_BG(x) (((x) >> S_ECC_POISON_BG) & M_ECC_POISON_BG)
+
+#define S_ECC_POISON_BANK    24
+#define M_ECC_POISON_BANK    0x3U
+#define V_ECC_POISON_BANK(x) ((x) << S_ECC_POISON_BANK)
+#define G_ECC_POISON_BANK(x) (((x) >> S_ECC_POISON_BANK) & M_ECC_POISON_BANK)
+
+#define S_ECC_POISON_ROW    0
+#define M_ECC_POISON_ROW    0x3ffffU
+#define V_ECC_POISON_ROW(x) ((x) << S_ECC_POISON_ROW)
+#define G_ECC_POISON_ROW(x) (((x) >> S_ECC_POISON_ROW) & M_ECC_POISON_ROW)
+
+#define A_MC_REGB_DDRC_CH0_ECCPOISONPAT0 0x10658
+#define A_MC_REGB_DDRC_CH0_ECCPOISONPAT1 0x1065c
+#define A_MC_REGB_DDRC_CH0_ECCPOISONPAT2 0x10660
+
+#define S_ECC_POISON_DATA_71_64    0
+#define M_ECC_POISON_DATA_71_64    0xffU
+#define V_ECC_POISON_DATA_71_64(x) ((x) << S_ECC_POISON_DATA_71_64)
+#define G_ECC_POISON_DATA_71_64(x) (((x) >> S_ECC_POISON_DATA_71_64) & M_ECC_POISON_DATA_71_64)
+
+#define A_MC_REGB_DDRC_CH0_ECCCFG2 0x10668
+
+#define S_FLIP_BIT_POS1    24
+#define M_FLIP_BIT_POS1    0x7fU
+#define V_FLIP_BIT_POS1(x) ((x) << S_FLIP_BIT_POS1)
+#define G_FLIP_BIT_POS1(x) (((x) >> S_FLIP_BIT_POS1) & M_FLIP_BIT_POS1)
+
+#define S_FLIP_BIT_POS0    16
+#define M_FLIP_BIT_POS0    0x7fU
+#define V_FLIP_BIT_POS0(x) ((x) << S_FLIP_BIT_POS0)
+#define G_FLIP_BIT_POS0(x) (((x) >> S_FLIP_BIT_POS0) & M_FLIP_BIT_POS0)
+
+#define A_MC_REGB_DDRC_CH1_ECCCTL 0x1160c
+#define A_MC_REGB_DDRC_CH1_ECCERRCNT 0x11610
+#define A_MC_REGB_DDRC_CH1_ECCCADDR0 0x11614
+#define A_MC_REGB_DDRC_CH1_ECCCADDR1 0x11618
+#define A_MC_REGB_DDRC_CH1_ECCCSYN0 0x1161c
+#define A_MC_REGB_DDRC_CH1_ECCCSYN1 0x11620
+#define A_MC_REGB_DDRC_CH1_ECCCSYN2 0x11624
+#define A_MC_REGB_DDRC_CH1_ECCBITMASK0 0x11628
+#define A_MC_REGB_DDRC_CH1_ECCBITMASK1 0x1162c
+#define A_MC_REGB_DDRC_CH1_ECCBITMASK2 0x11630
+#define A_MC_REGB_DDRC_CH1_ECCUADDR0 0x11634
+#define A_MC_REGB_DDRC_CH1_ECCUADDR1 0x11638
+#define A_MC_REGB_DDRC_CH1_ECCUSYN0 0x1163c
+#define A_MC_REGB_DDRC_CH1_ECCUSYN1 0x11640
+#define A_MC_REGB_DDRC_CH1_ECCUSYN2 0x11644
+#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTENABLE 0x20100
+
+#define S_PHYSTICKYUNLOCKEN    15
+#define V_PHYSTICKYUNLOCKEN(x) ((x) << S_PHYSTICKYUNLOCKEN)
+#define F_PHYSTICKYUNLOCKEN    V_PHYSTICKYUNLOCKEN(1U)
+
+#define S_PHYBSIEN    14
+#define V_PHYBSIEN(x) ((x) << S_PHYBSIEN)
+#define F_PHYBSIEN    V_PHYBSIEN(1U)
+
+#define S_PHYANIBRCVERREN    13
+#define V_PHYANIBRCVERREN(x) ((x) << S_PHYANIBRCVERREN)
+#define F_PHYANIBRCVERREN    V_PHYANIBRCVERREN(1U)
+
+#define S_PHYD5ACSM1PARITYEN    12
+#define V_PHYD5ACSM1PARITYEN(x) ((x) << S_PHYD5ACSM1PARITYEN)
+#define F_PHYD5ACSM1PARITYEN    V_PHYD5ACSM1PARITYEN(1U)
+
+#define S_PHYD5ACSM0PARITYEN    11
+#define V_PHYD5ACSM0PARITYEN(x) ((x) << S_PHYD5ACSM0PARITYEN)
+#define F_PHYD5ACSM0PARITYEN    V_PHYD5ACSM0PARITYEN(1U)
+
+#define S_PHYRXFIFOCHECKEN    10
+#define V_PHYRXFIFOCHECKEN(x) ((x) << S_PHYRXFIFOCHECKEN)
+#define F_PHYRXFIFOCHECKEN    V_PHYRXFIFOCHECKEN(1U)
+
+#define S_PHYTXPPTEN    9
+#define V_PHYTXPPTEN(x) ((x) << S_PHYTXPPTEN)
+#define F_PHYTXPPTEN    V_PHYTXPPTEN(1U)
+
+#define S_PHYECCEN    8
+#define V_PHYECCEN(x) ((x) << S_PHYECCEN)
+#define F_PHYECCEN    V_PHYECCEN(1U)
+
+#define S_PHYFWRESERVEDEN    3
+#define M_PHYFWRESERVEDEN    0x1fU
+#define V_PHYFWRESERVEDEN(x) ((x) << S_PHYFWRESERVEDEN)
+#define G_PHYFWRESERVEDEN(x) (((x) >> S_PHYFWRESERVEDEN) & M_PHYFWRESERVEDEN)
+
+#define S_PHYTRNGFAILEN    2
+#define V_PHYTRNGFAILEN(x) ((x) << S_PHYTRNGFAILEN)
+#define F_PHYTRNGFAILEN    V_PHYTRNGFAILEN(1U)
+
+#define S_PHYINITCMPLTEN    1
+#define V_PHYINITCMPLTEN(x) ((x) << S_PHYINITCMPLTEN)
+#define F_PHYINITCMPLTEN    V_PHYINITCMPLTEN(1U)
+
+#define S_PHYTRNGCMPLTEN    0
+#define V_PHYTRNGCMPLTEN(x) ((x) << S_PHYTRNGCMPLTEN)
+#define F_PHYTRNGCMPLTEN    V_PHYTRNGCMPLTEN(1U)
+
+#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTFWCONTROL 0x20101
+
+#define S_PHYFWRESERVEDFW    3
+#define M_PHYFWRESERVEDFW    0x1fU
+#define V_PHYFWRESERVEDFW(x) ((x) << S_PHYFWRESERVEDFW)
+#define G_PHYFWRESERVEDFW(x) (((x) >> S_PHYFWRESERVEDFW) & M_PHYFWRESERVEDFW)
+
+#define S_PHYTRNGFAILFW    2
+#define V_PHYTRNGFAILFW(x) ((x) << S_PHYTRNGFAILFW)
+#define F_PHYTRNGFAILFW    V_PHYTRNGFAILFW(1U)
+
+#define S_PHYINITCMPLTFW    1
+#define V_PHYINITCMPLTFW(x) ((x) << S_PHYINITCMPLTFW)
+#define F_PHYINITCMPLTFW    V_PHYINITCMPLTFW(1U)
+
+#define S_PHYTRNGCMPLTFW    0
+#define V_PHYTRNGCMPLTFW(x) ((x) << S_PHYTRNGCMPLTFW)
+#define F_PHYTRNGCMPLTFW    V_PHYTRNGCMPLTFW(1U)
+
+#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTMASK 0x20102
+
+#define S_PHYSTICKYUNLOCKMSK    15
+#define V_PHYSTICKYUNLOCKMSK(x) ((x) << S_PHYSTICKYUNLOCKMSK)
+#define F_PHYSTICKYUNLOCKMSK    V_PHYSTICKYUNLOCKMSK(1U)
+
+#define S_PHYBSIMSK    14
+#define V_PHYBSIMSK(x) ((x) << S_PHYBSIMSK)
+#define F_PHYBSIMSK    V_PHYBSIMSK(1U)
+
+#define S_PHYANIBRCVERRMSK    13
+#define V_PHYANIBRCVERRMSK(x) ((x) << S_PHYANIBRCVERRMSK)
+#define F_PHYANIBRCVERRMSK    V_PHYANIBRCVERRMSK(1U)
+
+#define S_PHYD5ACSM1PARITYMSK    12
+#define V_PHYD5ACSM1PARITYMSK(x) ((x) << S_PHYD5ACSM1PARITYMSK)
+#define F_PHYD5ACSM1PARITYMSK    V_PHYD5ACSM1PARITYMSK(1U)
+
+#define S_PHYD5ACSM0PARITYMSK    11
+#define V_PHYD5ACSM0PARITYMSK(x) ((x) << S_PHYD5ACSM0PARITYMSK)
+#define F_PHYD5ACSM0PARITYMSK    V_PHYD5ACSM0PARITYMSK(1U)
+
+#define S_PHYRXFIFOCHECKMSK    10
+#define V_PHYRXFIFOCHECKMSK(x) ((x) << S_PHYRXFIFOCHECKMSK)
+#define F_PHYRXFIFOCHECKMSK    V_PHYRXFIFOCHECKMSK(1U)
+
+#define S_PHYTXPPTMSK    9
+#define V_PHYTXPPTMSK(x) ((x) << S_PHYTXPPTMSK)
+#define F_PHYTXPPTMSK    V_PHYTXPPTMSK(1U)
+
+#define S_PHYECCMSK    8
+#define V_PHYECCMSK(x) ((x) << S_PHYECCMSK)
+#define F_PHYECCMSK    V_PHYECCMSK(1U)
+
+#define S_PHYFWRESERVEDMSK    3
+#define M_PHYFWRESERVEDMSK    0x1fU
+#define V_PHYFWRESERVEDMSK(x) ((x) << S_PHYFWRESERVEDMSK)
+#define G_PHYFWRESERVEDMSK(x) (((x) >> S_PHYFWRESERVEDMSK) & M_PHYFWRESERVEDMSK)
+
+#define S_PHYTRNGFAILMSK    2
+#define V_PHYTRNGFAILMSK(x) ((x) << S_PHYTRNGFAILMSK)
+#define F_PHYTRNGFAILMSK    V_PHYTRNGFAILMSK(1U)
+
+#define S_PHYINITCMPLTMSK    1
+#define V_PHYINITCMPLTMSK(x) ((x) << S_PHYINITCMPLTMSK)
+#define F_PHYINITCMPLTMSK    V_PHYINITCMPLTMSK(1U)
+
+#define S_PHYTRNGCMPLTMSK    0
+#define V_PHYTRNGCMPLTMSK(x) ((x) << S_PHYTRNGCMPLTMSK)
+#define F_PHYTRNGCMPLTMSK    V_PHYTRNGCMPLTMSK(1U)
+
+#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTCLEAR 0x20103
+
+#define S_PHYSTICKYUNLOCKCLR    15
+#define V_PHYSTICKYUNLOCKCLR(x) ((x) << S_PHYSTICKYUNLOCKCLR)
+#define F_PHYSTICKYUNLOCKCLR    V_PHYSTICKYUNLOCKCLR(1U)
+
+#define S_PHYBSICLR    14
+#define V_PHYBSICLR(x) ((x) << S_PHYBSICLR)
+#define F_PHYBSICLR    V_PHYBSICLR(1U)
+
+#define S_PHYANIBRCVERRCLR    13
+#define V_PHYANIBRCVERRCLR(x) ((x) << S_PHYANIBRCVERRCLR)
+#define F_PHYANIBRCVERRCLR    V_PHYANIBRCVERRCLR(1U)
+
+#define S_PHYD5ACSM1PARITYCLR    12
+#define V_PHYD5ACSM1PARITYCLR(x) ((x) << S_PHYD5ACSM1PARITYCLR)
+#define F_PHYD5ACSM1PARITYCLR    V_PHYD5ACSM1PARITYCLR(1U)
+
+#define S_PHYD5ACSM0PARITYCLR    11
+#define V_PHYD5ACSM0PARITYCLR(x) ((x) << S_PHYD5ACSM0PARITYCLR)
+#define F_PHYD5ACSM0PARITYCLR    V_PHYD5ACSM0PARITYCLR(1U)
+
+#define S_PHYRXFIFOCHECKCLR    10
+#define V_PHYRXFIFOCHECKCLR(x) ((x) << S_PHYRXFIFOCHECKCLR)
+#define F_PHYRXFIFOCHECKCLR    V_PHYRXFIFOCHECKCLR(1U)
+
+#define S_PHYTXPPTCLR    9
+#define V_PHYTXPPTCLR(x) ((x) << S_PHYTXPPTCLR)
+#define F_PHYTXPPTCLR    V_PHYTXPPTCLR(1U)
+
+#define S_PHYECCCLR    8
+#define V_PHYECCCLR(x) ((x) << S_PHYECCCLR)
+#define F_PHYECCCLR    V_PHYECCCLR(1U)
+
+#define S_PHYFWRESERVEDCLR    3
+#define M_PHYFWRESERVEDCLR    0x1fU
+#define V_PHYFWRESERVEDCLR(x) ((x) << S_PHYFWRESERVEDCLR)
+#define G_PHYFWRESERVEDCLR(x) (((x) >> S_PHYFWRESERVEDCLR) & M_PHYFWRESERVEDCLR)
+
+#define S_PHYTRNGFAILCLR    2
+#define V_PHYTRNGFAILCLR(x) ((x) << S_PHYTRNGFAILCLR)
+#define F_PHYTRNGFAILCLR    V_PHYTRNGFAILCLR(1U)
+
+#define S_PHYINITCMPLTCLR    1
+#define V_PHYINITCMPLTCLR(x) ((x) << S_PHYINITCMPLTCLR)
+#define F_PHYINITCMPLTCLR    V_PHYINITCMPLTCLR(1U)
+
+#define S_PHYTRNGCMPLTCLR    0
+#define V_PHYTRNGCMPLTCLR(x) ((x) << S_PHYTRNGCMPLTCLR)
+#define F_PHYTRNGCMPLTCLR    V_PHYTRNGCMPLTCLR(1U)
+
+#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTSTATUS 0x20104
+
+#define S_PHYSTICKYUNLOCKERR    15
+#define V_PHYSTICKYUNLOCKERR(x) ((x) << S_PHYSTICKYUNLOCKERR)
+#define F_PHYSTICKYUNLOCKERR    V_PHYSTICKYUNLOCKERR(1U)
+
+#define S_PHYBSIINT    14
+#define V_PHYBSIINT(x) ((x) << S_PHYBSIINT)
+#define F_PHYBSIINT    V_PHYBSIINT(1U)
+
+#define S_PHYANIBRCVERR    13
+#define V_PHYANIBRCVERR(x) ((x) << S_PHYANIBRCVERR)
+#define F_PHYANIBRCVERR    V_PHYANIBRCVERR(1U)
+
+#define S_PHYD5ACSM1PARITYERR    12
+#define V_PHYD5ACSM1PARITYERR(x) ((x) << S_PHYD5ACSM1PARITYERR)
+#define F_PHYD5ACSM1PARITYERR    V_PHYD5ACSM1PARITYERR(1U)
+
+#define S_PHYD5ACSM0PARITYERR    11
+#define V_PHYD5ACSM0PARITYERR(x) ((x) << S_PHYD5ACSM0PARITYERR)
+#define F_PHYD5ACSM0PARITYERR    V_PHYD5ACSM0PARITYERR(1U)
+
+#define S_PHYRXFIFOCHECKERR    10
+#define V_PHYRXFIFOCHECKERR(x) ((x) << S_PHYRXFIFOCHECKERR)
+#define F_PHYRXFIFOCHECKERR    V_PHYRXFIFOCHECKERR(1U)
+
+#define S_PHYRXTXPPTERR    9
+#define V_PHYRXTXPPTERR(x) ((x) << S_PHYRXTXPPTERR)
+#define F_PHYRXTXPPTERR    V_PHYRXTXPPTERR(1U)
+
+#define S_PHYECCERR    8
+#define V_PHYECCERR(x) ((x) << S_PHYECCERR)
+#define F_PHYECCERR    V_PHYECCERR(1U)
+
+#define S_PHYFWRESERVED    3
+#define M_PHYFWRESERVED    0x1fU
+#define V_PHYFWRESERVED(x) ((x) << S_PHYFWRESERVED)
+#define G_PHYFWRESERVED(x) (((x) >> S_PHYFWRESERVED) & M_PHYFWRESERVED)
+
+#define S_PHYTRNGFAIL    2
+#define V_PHYTRNGFAIL(x) ((x) << S_PHYTRNGFAIL)
+#define F_PHYTRNGFAIL    V_PHYTRNGFAIL(1U)
+
+#define S_PHYINITCMPLT    1
+#define V_PHYINITCMPLT(x) ((x) << S_PHYINITCMPLT)
+#define F_PHYINITCMPLT    V_PHYINITCMPLT(1U)
+
+#define S_PHYTRNGCMPLT    0
+#define V_PHYTRNGCMPLT(x) ((x) << S_PHYTRNGCMPLT)
+#define F_PHYTRNGCMPLT    V_PHYTRNGCMPLT(1U)
+
+#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTOVERRIDE 0x20107
+
+#define S_PHYINTERRUPTOVERRIDE    0
+#define M_PHYINTERRUPTOVERRIDE    0xffffU
+#define V_PHYINTERRUPTOVERRIDE(x) ((x) << S_PHYINTERRUPTOVERRIDE)
+#define G_PHYINTERRUPTOVERRIDE(x) (((x) >> S_PHYINTERRUPTOVERRIDE) & M_PHYINTERRUPTOVERRIDE)
+
+/* registers for module MC_T71 */
+#define MC_T71_BASE_ADDR 0x58000
+
+/* registers for module GCACHE */
+#define GCACHE_BASE_ADDR 0x51400
+
+#define A_GCACHE_MODE_SEL0 0x51400
+
+#define S_GC_MA_RSP    16
+#define V_GC_MA_RSP(x) ((x) << S_GC_MA_RSP)
+#define F_GC_MA_RSP    V_GC_MA_RSP(1U)
+
+#define A_GCACHE_MEMZONE0_REGION1 0x51404
+
+#define S_REGION_EN1    18
+#define V_REGION_EN1(x) ((x) << S_REGION_EN1)
+#define F_REGION_EN1    V_REGION_EN1(1U)
+
+#define S_EDC_REGION1    17
+#define V_EDC_REGION1(x) ((x) << S_EDC_REGION1)
+#define F_EDC_REGION1    V_EDC_REGION1(1U)
+
+#define S_CACHE_REGION1    16
+#define V_CACHE_REGION1(x) ((x) << S_CACHE_REGION1)
+#define F_CACHE_REGION1    V_CACHE_REGION1(1U)
+
+#define S_END1    0
+#define M_END1    0xffffU
+#define V_END1(x) ((x) << S_END1)
+#define G_END1(x) (((x) >> S_END1) & M_END1)
+
+#define A_GCACHE_MEMZONE0_REGION2 0x51408
+
+#define S_REGION_EN2    18
+#define V_REGION_EN2(x) ((x) << S_REGION_EN2)
+#define F_REGION_EN2    V_REGION_EN2(1U)
+
+#define S_EDC_REGION2    17
+#define V_EDC_REGION2(x) ((x) << S_EDC_REGION2)
+#define F_EDC_REGION2    V_EDC_REGION2(1U)
+
+#define S_CACHE_REGION2    16
+#define V_CACHE_REGION2(x) ((x) << S_CACHE_REGION2)
+#define F_CACHE_REGION2    V_CACHE_REGION2(1U)
+
+#define S_END2    0
+#define M_END2    0xffffU
+#define V_END2(x) ((x) << S_END2)
+#define G_END2(x) (((x) >> S_END2) & M_END2)
+
+#define A_GCACHE_MEMZONE0_REGION3 0x5140c
+
+#define S_REGION_EN3    18
+#define V_REGION_EN3(x) ((x) << S_REGION_EN3)
+#define F_REGION_EN3    V_REGION_EN3(1U)
+
+#define S_EDC_REGION3    17
+#define V_EDC_REGION3(x) ((x) << S_EDC_REGION3)
+#define F_EDC_REGION3    V_EDC_REGION3(1U)
+
+#define S_CACHE_REGION3    16
+#define V_CACHE_REGION3(x) ((x) << S_CACHE_REGION3)
+#define F_CACHE_REGION3    V_CACHE_REGION3(1U)
+
+#define S_END3    0
+#define M_END3    0xffffU
+#define V_END3(x) ((x) << S_END3)
+#define G_END3(x) (((x) >> S_END3) & M_END3)
+
+#define A_GCACHE_MEMZONE0_REGION4 0x51410
+
+#define S_REGION_EN4    18
+#define V_REGION_EN4(x) ((x) << S_REGION_EN4)
+#define F_REGION_EN4    V_REGION_EN4(1U)
+
+#define S_EDC_REGION4    17
+#define V_EDC_REGION4(x) ((x) << S_EDC_REGION4)
+#define F_EDC_REGION4    V_EDC_REGION4(1U)
+
+#define S_CACHE_REGION4    16
+#define V_CACHE_REGION4(x) ((x) << S_CACHE_REGION4)
+#define F_CACHE_REGION4    V_CACHE_REGION4(1U)
+
+#define S_END4    0
+#define M_END4    0xffffU
+#define V_END4(x) ((x) << S_END4)
+#define G_END4(x) (((x) >> S_END4) & M_END4)
+
+#define A_GCACHE_MEMZONE0_REGION5 0x51414
+
+#define S_REGION_EN5    18
+#define V_REGION_EN5(x) ((x) << S_REGION_EN5)
+#define F_REGION_EN5    V_REGION_EN5(1U)
+
+#define S_EDC_REGION5    17
+#define V_EDC_REGION5(x) ((x) << S_EDC_REGION5)
+#define F_EDC_REGION5    V_EDC_REGION5(1U)
+
+#define S_CACHE_REGION5    16
+#define V_CACHE_REGION5(x) ((x) << S_CACHE_REGION5)
+#define F_CACHE_REGION5    V_CACHE_REGION5(1U)
+
+#define S_END5    0
+#define M_END5    0xffffU
+#define V_END5(x) ((x) << S_END5)
+#define G_END5(x) (((x) >> S_END5) & M_END5)
+
+#define A_GCACHE_MEMZONE0_REGION6 0x51418
+
+#define S_REGION_EN6    18
+#define V_REGION_EN6(x) ((x) << S_REGION_EN6)
+#define F_REGION_EN6    V_REGION_EN6(1U)
+
+#define S_EDC_REGION6    17
+#define V_EDC_REGION6(x) ((x) << S_EDC_REGION6)
+#define F_EDC_REGION6    V_EDC_REGION6(1U)
+
+#define S_CACHE_REGION6    16
+#define V_CACHE_REGION6(x) ((x) << S_CACHE_REGION6)
+#define F_CACHE_REGION6    V_CACHE_REGION6(1U)
+
+#define S_END6    0
+#define M_END6    0xffffU
+#define V_END6(x) ((x) << S_END6)
+#define G_END6(x) (((x) >> S_END6) & M_END6)
+
+#define A_GCACHE_MEMZONE0_REGION7 0x5141c
+
+#define S_REGION_EN7    18
+#define V_REGION_EN7(x) ((x) << S_REGION_EN7)
+#define F_REGION_EN7    V_REGION_EN7(1U)
+
+#define S_EDC_REGION7    17
+#define V_EDC_REGION7(x) ((x) << S_EDC_REGION7)
+#define F_EDC_REGION7    V_EDC_REGION7(1U)
+
+#define S_CACHE_REGION7    16
+#define V_CACHE_REGION7(x) ((x) << S_CACHE_REGION7)
+#define F_CACHE_REGION7    V_CACHE_REGION7(1U)
+
+#define S_END7    0
+#define M_END7    0xffffU
+#define V_END7(x) ((x) << S_END7)
+#define G_END7(x) (((x) >> S_END7) & M_END7)
+
+#define A_GCACHE_MEMZONE0_REGION8 0x51420
+
+#define S_REGION_EN8    18
+#define V_REGION_EN8(x) ((x) << S_REGION_EN8)
+#define F_REGION_EN8    V_REGION_EN8(1U)
+
+#define S_EDC_REGION8    17
+#define V_EDC_REGION8(x) ((x) << S_EDC_REGION8)
+#define F_EDC_REGION8    V_EDC_REGION8(1U)
+
+#define S_CACHE_REGION8    16
+#define V_CACHE_REGION8(x) ((x) << S_CACHE_REGION8)
+#define F_CACHE_REGION8    V_CACHE_REGION8(1U)
+
+#define S_END8    0
+#define M_END8    0xffffU
+#define V_END8(x) ((x) << S_END8)
+#define G_END8(x) (((x) >> S_END8) & M_END8)
+
+#define A_GCACHE_REG0_BASE_MSB 0x51424
+#define A_GCACHE_MEMZONE0_REGION1_MSB 0x51428
+
+#define S_START1    0
+#define M_START1    0xffffU
+#define V_START1(x) ((x) << S_START1)
+#define G_START1(x) (((x) >> S_START1) & M_START1)
+
+#define A_GCACHE_MEMZONE0_REGION2_MSB 0x5142c
+
+#define S_START2    0
+#define M_START2    0xffffU
+#define V_START2(x) ((x) << S_START2)
+#define G_START2(x) (((x) >> S_START2) & M_START2)
+
+#define A_GCACHE_MEMZONE0_REGION3_MSB 0x51430
+
+#define S_START3    0
+#define M_START3    0xffffU
+#define V_START3(x) ((x) << S_START3)
+#define G_START3(x) (((x) >> S_START3) & M_START3)
+
+#define A_GCACHE_MEMZONE0_REGION4_MSB 0x51434
+
+#define S_START4    0
+#define M_START4    0xffffU
+#define V_START4(x) ((x) << S_START4)
+#define G_START4(x) (((x) >> S_START4) & M_START4)
+
+#define A_GCACHE_MEMZONE0_REGION5_MSB 0x51438
+
+#define S_START5    0
+#define M_START5    0xffffU
+#define V_START5(x) ((x) << S_START5)
+#define G_START5(x) (((x) >> S_START5) & M_START5)
+
+#define A_GCACHE_MEMZONE0_REGION6_MSB 0x5143c
+
+#define S_START6    0
+#define M_START6    0xffffU
+#define V_START6(x) ((x) << S_START6)
+#define G_START6(x) (((x) >> S_START6) & M_START6)
+
+#define A_GCACHE_MEMZONE0_REGION7_MSB 0x51440
+
+#define S_START7    0
+#define M_START7    0xffffU
+#define V_START7(x) ((x) << S_START7)
+#define G_START7(x) (((x) >> S_START7) & M_START7)
+
+#define A_GCACHE_MEMZONE0_REGION8_MSB 0x51444
+
+#define S_START8    0
+#define M_START8    0xffffU
+#define V_START8(x) ((x) << S_START8)
+#define G_START8(x) (((x) >> S_START8) & M_START8)
+
+#define A_GCACHE_MODE_SEL1 0x51448
+#define A_GCACHE_MEMZONE1_REGION1 0x5144c
+#define A_GCACHE_MEMZONE1_REGION2 0x51450
+#define A_GCACHE_MEMZONE1_REGION3 0x51454
+#define A_GCACHE_MEMZONE1_REGION4 0x51458
+#define A_GCACHE_MEMZONE1_REGION5 0x5145c
+#define A_GCACHE_MEMZONE1_REGION6 0x51460
+#define A_GCACHE_MEMZONE1_REGION7 0x51464
+#define A_GCACHE_MEMZONE1_REGION8 0x51468
+#define A_GCACHE_MEMZONE1_REGION1_MSB 0x5146c
+#define A_GCACHE_MEMZONE1_REGION2_MSB 0x51470
+#define A_GCACHE_MEMZONE1_REGION3_MSB 0x51474
+#define A_GCACHE_MEMZONE1_REGION4_MSB 0x51478
+#define A_GCACHE_MEMZONE1_REGION5_MSB 0x5147c
+#define A_GCACHE_MEMZONE1_REGION6_MSB 0x51480
+#define A_GCACHE_MEMZONE1_REGION7_MSB 0x51484
+#define A_GCACHE_MEMZONE1_REGION8_MSB 0x51488
+#define A_GCACHE_HMA_MC1_EN 0x5148c
+
+#define S_MC1_EN    1
+#define V_MC1_EN(x) ((x) << S_MC1_EN)
+#define F_MC1_EN    V_MC1_EN(1U)
+
+#define S_HMA_EN    0
+#define V_HMA_EN(x) ((x) << S_HMA_EN)
+#define F_HMA_EN    V_HMA_EN(1U)
+
+#define A_GCACHE_P_BIST_CMD 0x51490
+#define A_GCACHE_P_BIST_CMD_ADDR 0x51494
+#define A_GCACHE_P_BIST_CMD_LEN 0x51498
+#define A_GCACHE_P_BIST_DATA_PATTERN 0x5149c
+#define A_GCACHE_P_BIST_USER_WDATA0 0x514a0
+#define A_GCACHE_P_BIST_USER_WDATA1 0x514a4
+#define A_GCACHE_P_BIST_USER_WDATA2 0x514a8
+#define A_GCACHE_P_BIST_NUM_ERR 0x514ac
+#define A_GCACHE_P_BIST_ERR_FIRST_ADDR 0x514b0
+#define A_GCACHE_P_BIST_STATUS_RDATA 0x514b4
+#define A_GCACHE_P_BIST_CRC_SEED 0x514fc
+#define A_GCACHE_CACHE_SIZE 0x51500
+
+#define S_HMA_2MB    1
+#define V_HMA_2MB(x) ((x) << S_HMA_2MB)
+#define F_HMA_2MB    V_HMA_2MB(1U)
+
+#define S_MC0_2MB    0
+#define V_MC0_2MB(x) ((x) << S_MC0_2MB)
+#define F_MC0_2MB    V_MC0_2MB(1U)
+
+#define A_GCACHE_HINT_MAPPING 0x51504
+
+#define S_CLIENT_HINT_EN    16
+#define M_CLIENT_HINT_EN    0x7fffU
+#define V_CLIENT_HINT_EN(x) ((x) << S_CLIENT_HINT_EN)
+#define G_CLIENT_HINT_EN(x) (((x) >> S_CLIENT_HINT_EN) & M_CLIENT_HINT_EN)
+
+#define S_HINT_ADDR_SPLIT_EN    8
+#define V_HINT_ADDR_SPLIT_EN(x) ((x) << S_HINT_ADDR_SPLIT_EN)
+#define F_HINT_ADDR_SPLIT_EN    V_HINT_ADDR_SPLIT_EN(1U)
+
+#define S_TP_HINT_HMA_MC    2
+#define V_TP_HINT_HMA_MC(x) ((x) << S_TP_HINT_HMA_MC)
+#define F_TP_HINT_HMA_MC    V_TP_HINT_HMA_MC(1U)
+
+#define S_CIM_HINT_HMA_MC    1
+#define V_CIM_HINT_HMA_MC(x) ((x) << S_CIM_HINT_HMA_MC)
+#define F_CIM_HINT_HMA_MC    V_CIM_HINT_HMA_MC(1U)
+
+#define S_LE_HINT_HMA_MC    0
+#define V_LE_HINT_HMA_MC(x) ((x) << S_LE_HINT_HMA_MC)
+#define F_LE_HINT_HMA_MC    V_LE_HINT_HMA_MC(1U)
+
+#define A_GCACHE_PERF_EN 0x51508
+
+#define S_PERF_CLEAR_GC1    3
+#define V_PERF_CLEAR_GC1(x) ((x) << S_PERF_CLEAR_GC1)
+#define F_PERF_CLEAR_GC1    V_PERF_CLEAR_GC1(1U)
+
+#define S_PERF_CLEAR_GC0    2
+#define V_PERF_CLEAR_GC0(x) ((x) << S_PERF_CLEAR_GC0)
+#define F_PERF_CLEAR_GC0    V_PERF_CLEAR_GC0(1U)
+
+#define S_PERF_EN_GC1    1
+#define V_PERF_EN_GC1(x) ((x) << S_PERF_EN_GC1)
+#define F_PERF_EN_GC1    V_PERF_EN_GC1(1U)
+
+#define S_PERF_EN_GC0    0
+#define V_PERF_EN_GC0(x) ((x) << S_PERF_EN_GC0)
+#define F_PERF_EN_GC0    V_PERF_EN_GC0(1U)
+
+#define A_GCACHE_PERF_GC0_RD_HIT 0x5150c
+#define A_GCACHE_PERF_GC1_RD_HIT 0x51510
+#define A_GCACHE_PERF_GC0_WR_HIT 0x51514
+#define A_GCACHE_PERF_GC1_WR_HIT 0x51518
+#define A_GCACHE_PERF_GC0_RD_MISS 0x5151c
+#define A_GCACHE_PERF_GC1_RD_MISS 0x51520
+#define A_GCACHE_PERF_GC0_WR_MISS 0x51524
+#define A_GCACHE_PERF_GC1_WR_MISS 0x51528
+#define A_GCACHE_PERF_GC0_RD_REQ 0x5152c
+#define A_GCACHE_PERF_GC1_RD_REQ 0x51530
+#define A_GCACHE_PERF_GC0_WR_REQ 0x51534
+#define A_GCACHE_PERF_GC1_WR_REQ 0x51538
+#define A_GCACHE_PAR_CAUSE 0x5153c
+
+#define S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    27
+#define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE)
+#define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U)
+
+#define S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    26
+#define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE)
+#define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U)
+
+#define S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE    25
+#define V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE)
+#define F_GC1_WQDATA_FIFO_PERR_PAR_CAUSE    V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(1U)
+
+#define S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE    24
+#define V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE)
+#define F_GC0_WQDATA_FIFO_PERR_PAR_CAUSE    V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(1U)
+
+#define S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE    23
+#define V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE)
+#define F_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
+
+#define S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE    22
+#define V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE)
+#define F_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
+
+#define S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    21
+#define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE)
+#define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
+
+#define S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    20
+#define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE)
+#define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
+
+#define S_GC1_RSP_PERR_PAR_CAUSE    19
+#define V_GC1_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC1_RSP_PERR_PAR_CAUSE)
+#define F_GC1_RSP_PERR_PAR_CAUSE    V_GC1_RSP_PERR_PAR_CAUSE(1U)
+
+#define S_GC0_RSP_PERR_PAR_CAUSE    18
+#define V_GC0_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC0_RSP_PERR_PAR_CAUSE)
+#define F_GC0_RSP_PERR_PAR_CAUSE    V_GC0_RSP_PERR_PAR_CAUSE(1U)
+
+#define S_GC1_LRU_UERR_PAR_CAUSE    17
+#define V_GC1_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_UERR_PAR_CAUSE)
+#define F_GC1_LRU_UERR_PAR_CAUSE    V_GC1_LRU_UERR_PAR_CAUSE(1U)
+
+#define S_GC0_LRU_UERR_PAR_CAUSE    16
+#define V_GC0_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_UERR_PAR_CAUSE)
+#define F_GC0_LRU_UERR_PAR_CAUSE    V_GC0_LRU_UERR_PAR_CAUSE(1U)
+
+#define S_GC1_TAG_UERR_PAR_CAUSE    15
+#define V_GC1_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_UERR_PAR_CAUSE)
+#define F_GC1_TAG_UERR_PAR_CAUSE    V_GC1_TAG_UERR_PAR_CAUSE(1U)
+
+#define S_GC0_TAG_UERR_PAR_CAUSE    14
+#define V_GC0_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_UERR_PAR_CAUSE)
+#define F_GC0_TAG_UERR_PAR_CAUSE    V_GC0_TAG_UERR_PAR_CAUSE(1U)
+
+#define S_GC1_LRU_CERR_PAR_CAUSE    13
+#define V_GC1_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_CERR_PAR_CAUSE)
+#define F_GC1_LRU_CERR_PAR_CAUSE    V_GC1_LRU_CERR_PAR_CAUSE(1U)
+
+#define S_GC0_LRU_CERR_PAR_CAUSE    12
+#define V_GC0_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_CERR_PAR_CAUSE)
+#define F_GC0_LRU_CERR_PAR_CAUSE    V_GC0_LRU_CERR_PAR_CAUSE(1U)
+
+#define S_GC1_TAG_CERR_PAR_CAUSE    11
+#define V_GC1_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_CERR_PAR_CAUSE)
+#define F_GC1_TAG_CERR_PAR_CAUSE    V_GC1_TAG_CERR_PAR_CAUSE(1U)
+
+#define S_GC0_TAG_CERR_PAR_CAUSE    10
+#define V_GC0_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_CERR_PAR_CAUSE)
+#define F_GC0_TAG_CERR_PAR_CAUSE    V_GC0_TAG_CERR_PAR_CAUSE(1U)
+
+#define S_GC1_CE_PAR_CAUSE    9
+#define V_GC1_CE_PAR_CAUSE(x) ((x) << S_GC1_CE_PAR_CAUSE)
+#define F_GC1_CE_PAR_CAUSE    V_GC1_CE_PAR_CAUSE(1U)
+
+#define S_GC0_CE_PAR_CAUSE    8
+#define V_GC0_CE_PAR_CAUSE(x) ((x) << S_GC0_CE_PAR_CAUSE)
+#define F_GC0_CE_PAR_CAUSE    V_GC0_CE_PAR_CAUSE(1U)
+
+#define S_GC1_UE_PAR_CAUSE    7
+#define V_GC1_UE_PAR_CAUSE(x) ((x) << S_GC1_UE_PAR_CAUSE)
+#define F_GC1_UE_PAR_CAUSE    V_GC1_UE_PAR_CAUSE(1U)
+
+#define S_GC0_UE_PAR_CAUSE    6
+#define V_GC0_UE_PAR_CAUSE(x) ((x) << S_GC0_UE_PAR_CAUSE)
+#define F_GC0_UE_PAR_CAUSE    V_GC0_UE_PAR_CAUSE(1U)
+
+#define S_GC1_CMD_PAR_CAUSE    5
+#define V_GC1_CMD_PAR_CAUSE(x) ((x) << S_GC1_CMD_PAR_CAUSE)
+#define F_GC1_CMD_PAR_CAUSE    V_GC1_CMD_PAR_CAUSE(1U)
+
+#define S_GC1_DATA_PAR_CAUSE    4
+#define V_GC1_DATA_PAR_CAUSE(x) ((x) << S_GC1_DATA_PAR_CAUSE)
+#define F_GC1_DATA_PAR_CAUSE    V_GC1_DATA_PAR_CAUSE(1U)
+
+#define S_GC0_CMD_PAR_CAUSE    3
+#define V_GC0_CMD_PAR_CAUSE(x) ((x) << S_GC0_CMD_PAR_CAUSE)
+#define F_GC0_CMD_PAR_CAUSE    V_GC0_CMD_PAR_CAUSE(1U)
+
+#define S_GC0_DATA_PAR_CAUSE    2
+#define V_GC0_DATA_PAR_CAUSE(x) ((x) << S_GC0_DATA_PAR_CAUSE)
+#define F_GC0_DATA_PAR_CAUSE    V_GC0_DATA_PAR_CAUSE(1U)
+
+#define S_ILLADDRACCESS1_PAR_CAUSE    1
+#define V_ILLADDRACCESS1_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS1_PAR_CAUSE)
+#define F_ILLADDRACCESS1_PAR_CAUSE    V_ILLADDRACCESS1_PAR_CAUSE(1U)
+
+#define S_ILLADDRACCESS0_PAR_CAUSE    0
+#define V_ILLADDRACCESS0_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS0_PAR_CAUSE)
+#define F_ILLADDRACCESS0_PAR_CAUSE    V_ILLADDRACCESS0_PAR_CAUSE(1U)
+
+#define A_GCACHE_PAR_ENABLE 0x51540
+
+#define S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    27
+#define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE)
+#define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U)
+
+#define S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    26
+#define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE)
+#define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U)
+
+#define S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE    25
+#define V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE)
+#define F_GC1_WQDATA_FIFO_PERR_PAR_ENABLE    V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(1U)
+
+#define S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE    24
+#define V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE)
+#define F_GC0_WQDATA_FIFO_PERR_PAR_ENABLE    V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(1U)
+
+#define S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE    23
+#define V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE)
+#define F_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
+
+#define S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE    22
+#define V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE)
+#define F_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
+
+#define S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    21
+#define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE)
+#define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
+
+#define S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    20
+#define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE)
+#define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
+
+#define S_GC1_RSP_PERR_PAR_ENABLE    19
+#define V_GC1_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC1_RSP_PERR_PAR_ENABLE)
+#define F_GC1_RSP_PERR_PAR_ENABLE    V_GC1_RSP_PERR_PAR_ENABLE(1U)
+
+#define S_GC0_RSP_PERR_PAR_ENABLE    18
+#define V_GC0_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC0_RSP_PERR_PAR_ENABLE)
+#define F_GC0_RSP_PERR_PAR_ENABLE    V_GC0_RSP_PERR_PAR_ENABLE(1U)
+
+#define S_GC1_LRU_UERR_PAR_ENABLE    17
+#define V_GC1_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_UERR_PAR_ENABLE)
+#define F_GC1_LRU_UERR_PAR_ENABLE    V_GC1_LRU_UERR_PAR_ENABLE(1U)
+
+#define S_GC0_LRU_UERR_PAR_ENABLE    16
+#define V_GC0_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_UERR_PAR_ENABLE)
+#define F_GC0_LRU_UERR_PAR_ENABLE    V_GC0_LRU_UERR_PAR_ENABLE(1U)
+
+#define S_GC1_TAG_UERR_PAR_ENABLE    15
+#define V_GC1_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_UERR_PAR_ENABLE)
+#define F_GC1_TAG_UERR_PAR_ENABLE    V_GC1_TAG_UERR_PAR_ENABLE(1U)
+
+#define S_GC0_TAG_UERR_PAR_ENABLE    14
+#define V_GC0_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_UERR_PAR_ENABLE)
+#define F_GC0_TAG_UERR_PAR_ENABLE    V_GC0_TAG_UERR_PAR_ENABLE(1U)
+
+#define S_GC1_LRU_CERR_PAR_ENABLE    13
+#define V_GC1_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_CERR_PAR_ENABLE)
+#define F_GC1_LRU_CERR_PAR_ENABLE    V_GC1_LRU_CERR_PAR_ENABLE(1U)
+
+#define S_GC0_LRU_CERR_PAR_ENABLE    12
+#define V_GC0_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_CERR_PAR_ENABLE)
+#define F_GC0_LRU_CERR_PAR_ENABLE    V_GC0_LRU_CERR_PAR_ENABLE(1U)
+
+#define S_GC1_TAG_CERR_PAR_ENABLE    11
+#define V_GC1_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_CERR_PAR_ENABLE)
+#define F_GC1_TAG_CERR_PAR_ENABLE    V_GC1_TAG_CERR_PAR_ENABLE(1U)
+
+#define S_GC0_TAG_CERR_PAR_ENABLE    10
+#define V_GC0_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_CERR_PAR_ENABLE)
+#define F_GC0_TAG_CERR_PAR_ENABLE    V_GC0_TAG_CERR_PAR_ENABLE(1U)
+
+#define S_GC1_CE_PAR_ENABLE    9
+#define V_GC1_CE_PAR_ENABLE(x) ((x) << S_GC1_CE_PAR_ENABLE)
+#define F_GC1_CE_PAR_ENABLE    V_GC1_CE_PAR_ENABLE(1U)
+
+#define S_GC0_CE_PAR_ENABLE    8
+#define V_GC0_CE_PAR_ENABLE(x) ((x) << S_GC0_CE_PAR_ENABLE)
+#define F_GC0_CE_PAR_ENABLE    V_GC0_CE_PAR_ENABLE(1U)
+
+#define S_GC1_UE_PAR_ENABLE    7
+#define V_GC1_UE_PAR_ENABLE(x) ((x) << S_GC1_UE_PAR_ENABLE)
+#define F_GC1_UE_PAR_ENABLE    V_GC1_UE_PAR_ENABLE(1U)
+
+#define S_GC0_UE_PAR_ENABLE    6
+#define V_GC0_UE_PAR_ENABLE(x) ((x) << S_GC0_UE_PAR_ENABLE)
+#define F_GC0_UE_PAR_ENABLE    V_GC0_UE_PAR_ENABLE(1U)
+
+#define S_GC1_CMD_PAR_ENABLE    5
+#define V_GC1_CMD_PAR_ENABLE(x) ((x) << S_GC1_CMD_PAR_ENABLE)
+#define F_GC1_CMD_PAR_ENABLE    V_GC1_CMD_PAR_ENABLE(1U)
+
+#define S_GC1_DATA_PAR_ENABLE    4
+#define V_GC1_DATA_PAR_ENABLE(x) ((x) << S_GC1_DATA_PAR_ENABLE)
+#define F_GC1_DATA_PAR_ENABLE    V_GC1_DATA_PAR_ENABLE(1U)
+
+#define S_GC0_CMD_PAR_ENABLE    3
+#define V_GC0_CMD_PAR_ENABLE(x) ((x) << S_GC0_CMD_PAR_ENABLE)
+#define F_GC0_CMD_PAR_ENABLE    V_GC0_CMD_PAR_ENABLE(1U)
+
+#define S_GC0_DATA_PAR_ENABLE    2
+#define V_GC0_DATA_PAR_ENABLE(x) ((x) << S_GC0_DATA_PAR_ENABLE)
+#define F_GC0_DATA_PAR_ENABLE    V_GC0_DATA_PAR_ENABLE(1U)
+
+#define S_ILLADDRACCESS1_PAR_ENABLE    1
+#define V_ILLADDRACCESS1_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS1_PAR_ENABLE)
+#define F_ILLADDRACCESS1_PAR_ENABLE    V_ILLADDRACCESS1_PAR_ENABLE(1U)
+
+#define S_ILLADDRACCESS0_PAR_ENABLE    0
+#define V_ILLADDRACCESS0_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS0_PAR_ENABLE)
+#define F_ILLADDRACCESS0_PAR_ENABLE    V_ILLADDRACCESS0_PAR_ENABLE(1U)
+
+#define A_GCACHE_INT_ENABLE 0x51544
+
+#define S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE    27
+#define V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE)
+#define F_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE    V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U)
+
+#define S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE    26
+#define V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE)
+#define F_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE    V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U)
+
+#define S_GC1_WQDATA_FIFO_PERR_INT_ENABLE    25
+#define V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_ENABLE)
+#define F_GC1_WQDATA_FIFO_PERR_INT_ENABLE    V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(1U)
+
+#define S_GC0_WQDATA_FIFO_PERR_INT_ENABLE    24
+#define V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_ENABLE)
+#define F_GC0_WQDATA_FIFO_PERR_INT_ENABLE    V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(1U)
+
+#define S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE    23
+#define V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE)
+#define F_GC1_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
+
+#define S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE    22
+#define V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE)
+#define F_GC0_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
+
+#define S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    21
+#define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE)
+#define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
+
+#define S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    20
+#define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE)
+#define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
+
+#define S_GC1_RSP_PERR_INT_ENABLE    19
+#define V_GC1_RSP_PERR_INT_ENABLE(x) ((x) << S_GC1_RSP_PERR_INT_ENABLE)
+#define F_GC1_RSP_PERR_INT_ENABLE    V_GC1_RSP_PERR_INT_ENABLE(1U)
+
+#define S_GC0_RSP_PERR_INT_ENABLE    18
+#define V_GC0_RSP_PERR_INT_ENABLE(x) ((x) << S_GC0_RSP_PERR_INT_ENABLE)
+#define F_GC0_RSP_PERR_INT_ENABLE    V_GC0_RSP_PERR_INT_ENABLE(1U)
+
+#define S_GC1_LRU_UERR_INT_ENABLE    17
+#define V_GC1_LRU_UERR_INT_ENABLE(x) ((x) << S_GC1_LRU_UERR_INT_ENABLE)
+#define F_GC1_LRU_UERR_INT_ENABLE    V_GC1_LRU_UERR_INT_ENABLE(1U)
+
+#define S_GC0_LRU_UERR_INT_ENABLE    16
+#define V_GC0_LRU_UERR_INT_ENABLE(x) ((x) << S_GC0_LRU_UERR_INT_ENABLE)
+#define F_GC0_LRU_UERR_INT_ENABLE    V_GC0_LRU_UERR_INT_ENABLE(1U)
+
+#define S_GC1_TAG_UERR_INT_ENABLE    15
+#define V_GC1_TAG_UERR_INT_ENABLE(x) ((x) << S_GC1_TAG_UERR_INT_ENABLE)
+#define F_GC1_TAG_UERR_INT_ENABLE    V_GC1_TAG_UERR_INT_ENABLE(1U)
+
+#define S_GC0_TAG_UERR_INT_ENABLE    14
+#define V_GC0_TAG_UERR_INT_ENABLE(x) ((x) << S_GC0_TAG_UERR_INT_ENABLE)
+#define F_GC0_TAG_UERR_INT_ENABLE    V_GC0_TAG_UERR_INT_ENABLE(1U)
+
+#define S_GC1_LRU_CERR_INT_ENABLE    13
+#define V_GC1_LRU_CERR_INT_ENABLE(x) ((x) << S_GC1_LRU_CERR_INT_ENABLE)
+#define F_GC1_LRU_CERR_INT_ENABLE    V_GC1_LRU_CERR_INT_ENABLE(1U)
+
+#define S_GC0_LRU_CERR_INT_ENABLE    12
+#define V_GC0_LRU_CERR_INT_ENABLE(x) ((x) << S_GC0_LRU_CERR_INT_ENABLE)
+#define F_GC0_LRU_CERR_INT_ENABLE    V_GC0_LRU_CERR_INT_ENABLE(1U)
+
+#define S_GC1_TAG_CERR_INT_ENABLE    11
+#define V_GC1_TAG_CERR_INT_ENABLE(x) ((x) << S_GC1_TAG_CERR_INT_ENABLE)
+#define F_GC1_TAG_CERR_INT_ENABLE    V_GC1_TAG_CERR_INT_ENABLE(1U)
+
+#define S_GC0_TAG_CERR_INT_ENABLE    10
+#define V_GC0_TAG_CERR_INT_ENABLE(x) ((x) << S_GC0_TAG_CERR_INT_ENABLE)
+#define F_GC0_TAG_CERR_INT_ENABLE    V_GC0_TAG_CERR_INT_ENABLE(1U)
+
+#define S_GC1_CE_INT_ENABLE    9
+#define V_GC1_CE_INT_ENABLE(x) ((x) << S_GC1_CE_INT_ENABLE)
+#define F_GC1_CE_INT_ENABLE    V_GC1_CE_INT_ENABLE(1U)
+
+#define S_GC0_CE_INT_ENABLE    8
+#define V_GC0_CE_INT_ENABLE(x) ((x) << S_GC0_CE_INT_ENABLE)
+#define F_GC0_CE_INT_ENABLE    V_GC0_CE_INT_ENABLE(1U)
+
+#define S_GC1_UE_INT_ENABLE    7
+#define V_GC1_UE_INT_ENABLE(x) ((x) << S_GC1_UE_INT_ENABLE)
+#define F_GC1_UE_INT_ENABLE    V_GC1_UE_INT_ENABLE(1U)
+
+#define S_GC0_UE_INT_ENABLE    6
+#define V_GC0_UE_INT_ENABLE(x) ((x) << S_GC0_UE_INT_ENABLE)
+#define F_GC0_UE_INT_ENABLE    V_GC0_UE_INT_ENABLE(1U)
+
+#define S_GC1_CMD_PAR_INT_ENABLE    5
+#define V_GC1_CMD_PAR_INT_ENABLE(x) ((x) << S_GC1_CMD_PAR_INT_ENABLE)
+#define F_GC1_CMD_PAR_INT_ENABLE    V_GC1_CMD_PAR_INT_ENABLE(1U)
+
+#define S_GC1_DATA_PAR_INT_ENABLE    4
+#define V_GC1_DATA_PAR_INT_ENABLE(x) ((x) << S_GC1_DATA_PAR_INT_ENABLE)
+#define F_GC1_DATA_PAR_INT_ENABLE    V_GC1_DATA_PAR_INT_ENABLE(1U)
+
+#define S_GC0_CMD_PAR_INT_ENABLE    3
+#define V_GC0_CMD_PAR_INT_ENABLE(x) ((x) << S_GC0_CMD_PAR_INT_ENABLE)
+#define F_GC0_CMD_PAR_INT_ENABLE    V_GC0_CMD_PAR_INT_ENABLE(1U)
+
+#define S_GC0_DATA_PAR_INT_ENABLE    2
+#define V_GC0_DATA_PAR_INT_ENABLE(x) ((x) << S_GC0_DATA_PAR_INT_ENABLE)
+#define F_GC0_DATA_PAR_INT_ENABLE    V_GC0_DATA_PAR_INT_ENABLE(1U)
+
+#define S_ILLADDRACCESS1_INT_ENABLE    1
+#define V_ILLADDRACCESS1_INT_ENABLE(x) ((x) << S_ILLADDRACCESS1_INT_ENABLE)
+#define F_ILLADDRACCESS1_INT_ENABLE    V_ILLADDRACCESS1_INT_ENABLE(1U)
+
+#define S_ILLADDRACCESS0_INT_ENABLE    0
+#define V_ILLADDRACCESS0_INT_ENABLE(x) ((x) << S_ILLADDRACCESS0_INT_ENABLE)
+#define F_ILLADDRACCESS0_INT_ENABLE    V_ILLADDRACCESS0_INT_ENABLE(1U)
+
+#define A_GCACHE_INT_CAUSE 0x51548
+
+#define S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE    27
+#define V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE)
+#define F_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE    V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U)
+
+#define S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE    26
+#define V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE)
+#define F_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE    V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U)
+
+#define S_GC1_WQDATA_FIFO_PERR_INT_CAUSE    25
+#define V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_CAUSE)
+#define F_GC1_WQDATA_FIFO_PERR_INT_CAUSE    V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(1U)
+
+#define S_GC0_WQDATA_FIFO_PERR_INT_CAUSE    24
+#define V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_CAUSE)
+#define F_GC0_WQDATA_FIFO_PERR_INT_CAUSE    V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(1U)
+
+#define S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE    23
+#define V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE)
+#define F_GC1_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
+
+#define S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE    22
+#define V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE)
+#define F_GC0_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
+
+#define S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    21
+#define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE)
+#define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
+
+#define S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    20
+#define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE)
+#define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
+
+#define S_GC1_RSP_PERR_INT_CAUSE    19
+#define V_GC1_RSP_PERR_INT_CAUSE(x) ((x) << S_GC1_RSP_PERR_INT_CAUSE)
+#define F_GC1_RSP_PERR_INT_CAUSE    V_GC1_RSP_PERR_INT_CAUSE(1U)
+
+#define S_GC0_RSP_PERR_INT_CAUSE    18
+#define V_GC0_RSP_PERR_INT_CAUSE(x) ((x) << S_GC0_RSP_PERR_INT_CAUSE)
+#define F_GC0_RSP_PERR_INT_CAUSE    V_GC0_RSP_PERR_INT_CAUSE(1U)
+
+#define S_GC1_LRU_UERR_INT_CAUSE    17
+#define V_GC1_LRU_UERR_INT_CAUSE(x) ((x) << S_GC1_LRU_UERR_INT_CAUSE)
+#define F_GC1_LRU_UERR_INT_CAUSE    V_GC1_LRU_UERR_INT_CAUSE(1U)
+
+#define S_GC0_LRU_UERR_INT_CAUSE    16
+#define V_GC0_LRU_UERR_INT_CAUSE(x) ((x) << S_GC0_LRU_UERR_INT_CAUSE)
+#define F_GC0_LRU_UERR_INT_CAUSE    V_GC0_LRU_UERR_INT_CAUSE(1U)
+
+#define S_GC1_TAG_UERR_INT_CAUSE    15
+#define V_GC1_TAG_UERR_INT_CAUSE(x) ((x) << S_GC1_TAG_UERR_INT_CAUSE)
+#define F_GC1_TAG_UERR_INT_CAUSE    V_GC1_TAG_UERR_INT_CAUSE(1U)
+
+#define S_GC0_TAG_UERR_INT_CAUSE    14
+#define V_GC0_TAG_UERR_INT_CAUSE(x) ((x) << S_GC0_TAG_UERR_INT_CAUSE)
+#define F_GC0_TAG_UERR_INT_CAUSE    V_GC0_TAG_UERR_INT_CAUSE(1U)
+
+#define S_GC1_LRU_CERR_INT_CAUSE    13
+#define V_GC1_LRU_CERR_INT_CAUSE(x) ((x) << S_GC1_LRU_CERR_INT_CAUSE)
+#define F_GC1_LRU_CERR_INT_CAUSE    V_GC1_LRU_CERR_INT_CAUSE(1U)
+
+#define S_GC0_LRU_CERR_INT_CAUSE    12
+#define V_GC0_LRU_CERR_INT_CAUSE(x) ((x) << S_GC0_LRU_CERR_INT_CAUSE)
+#define F_GC0_LRU_CERR_INT_CAUSE    V_GC0_LRU_CERR_INT_CAUSE(1U)
+
+#define S_GC1_TAG_CERR_INT_CAUSE    11
+#define V_GC1_TAG_CERR_INT_CAUSE(x) ((x) << S_GC1_TAG_CERR_INT_CAUSE)
+#define F_GC1_TAG_CERR_INT_CAUSE    V_GC1_TAG_CERR_INT_CAUSE(1U)
+
+#define S_GC0_TAG_CERR_INT_CAUSE    10
+#define V_GC0_TAG_CERR_INT_CAUSE(x) ((x) << S_GC0_TAG_CERR_INT_CAUSE)
+#define F_GC0_TAG_CERR_INT_CAUSE    V_GC0_TAG_CERR_INT_CAUSE(1U)
+
+#define S_GC1_CE_INT_CAUSE    9
+#define V_GC1_CE_INT_CAUSE(x) ((x) << S_GC1_CE_INT_CAUSE)
+#define F_GC1_CE_INT_CAUSE    V_GC1_CE_INT_CAUSE(1U)
+
+#define S_GC0_CE_INT_CAUSE    8
+#define V_GC0_CE_INT_CAUSE(x) ((x) << S_GC0_CE_INT_CAUSE)
+#define F_GC0_CE_INT_CAUSE    V_GC0_CE_INT_CAUSE(1U)
+
+#define S_GC1_UE_INT_CAUSE    7
+#define V_GC1_UE_INT_CAUSE(x) ((x) << S_GC1_UE_INT_CAUSE)
+#define F_GC1_UE_INT_CAUSE    V_GC1_UE_INT_CAUSE(1U)
+
+#define S_GC0_UE_INT_CAUSE    6
+#define V_GC0_UE_INT_CAUSE(x) ((x) << S_GC0_UE_INT_CAUSE)
+#define F_GC0_UE_INT_CAUSE    V_GC0_UE_INT_CAUSE(1U)
+
+#define S_GC1_CMD_PAR_INT_CAUSE    5
+#define V_GC1_CMD_PAR_INT_CAUSE(x) ((x) << S_GC1_CMD_PAR_INT_CAUSE)
+#define F_GC1_CMD_PAR_INT_CAUSE    V_GC1_CMD_PAR_INT_CAUSE(1U)
+
+#define S_GC1_DATA_PAR_INT_CAUSE    4
+#define V_GC1_DATA_PAR_INT_CAUSE(x) ((x) << S_GC1_DATA_PAR_INT_CAUSE)
+#define F_GC1_DATA_PAR_INT_CAUSE    V_GC1_DATA_PAR_INT_CAUSE(1U)
+
+#define S_GC0_CMD_PAR_INT_CAUSE    3
+#define V_GC0_CMD_PAR_INT_CAUSE(x) ((x) << S_GC0_CMD_PAR_INT_CAUSE)
+#define F_GC0_CMD_PAR_INT_CAUSE    V_GC0_CMD_PAR_INT_CAUSE(1U)
+
+#define S_GC0_DATA_PAR_INT_CAUSE    2
+#define V_GC0_DATA_PAR_INT_CAUSE(x) ((x) << S_GC0_DATA_PAR_INT_CAUSE)
+#define F_GC0_DATA_PAR_INT_CAUSE    V_GC0_DATA_PAR_INT_CAUSE(1U)
+
+#define S_ILLADDRACCESS1_INT_CAUSE    1
+#define V_ILLADDRACCESS1_INT_CAUSE(x) ((x) << S_ILLADDRACCESS1_INT_CAUSE)
+#define F_ILLADDRACCESS1_INT_CAUSE    V_ILLADDRACCESS1_INT_CAUSE(1U)
+
+#define S_ILLADDRACCESS0_INT_CAUSE    0
+#define V_ILLADDRACCESS0_INT_CAUSE(x) ((x) << S_ILLADDRACCESS0_INT_CAUSE)
+#define F_ILLADDRACCESS0_INT_CAUSE    V_ILLADDRACCESS0_INT_CAUSE(1U)
+
+#define A_GCACHE_DBG_SEL_CTRL 0x51550
+
+#define S_DBG_SEL_CTRLSEL_OVR_EN    31
+#define V_DBG_SEL_CTRLSEL_OVR_EN(x) ((x) << S_DBG_SEL_CTRLSEL_OVR_EN)
+#define F_DBG_SEL_CTRLSEL_OVR_EN    V_DBG_SEL_CTRLSEL_OVR_EN(1U)
+
+#define S_T7_DEBUG_HI    16
+#define V_T7_DEBUG_HI(x) ((x) << S_T7_DEBUG_HI)
+#define F_T7_DEBUG_HI    V_T7_DEBUG_HI(1U)
+
+#define S_DBG_SEL_CTRLSELH    8
+#define M_DBG_SEL_CTRLSELH    0xffU
+#define V_DBG_SEL_CTRLSELH(x) ((x) << S_DBG_SEL_CTRLSELH)
+#define G_DBG_SEL_CTRLSELH(x) (((x) >> S_DBG_SEL_CTRLSELH) & M_DBG_SEL_CTRLSELH)
+
+#define S_DBG_SEL_CTRLSELL    0
+#define M_DBG_SEL_CTRLSELL    0xffU
+#define V_DBG_SEL_CTRLSELL(x) ((x) << S_DBG_SEL_CTRLSELL)
+#define G_DBG_SEL_CTRLSELL(x) (((x) >> S_DBG_SEL_CTRLSELL) & M_DBG_SEL_CTRLSELL)
+
+#define A_GCACHE_LOCAL_DEBUG_RPT 0x51554
+#define A_GCACHE_DBG_ILL_ACC 0x5155c
+#define A_GCACHE_DBG_ILL_ADDR0 0x51560
+#define A_GCACHE_DBG_ILL_ADDR1 0x51564
+#define A_GCACHE_GC0_DBG_ADDR_0_32 0x51568
+#define A_GCACHE_GC0_DBG_ADDR_32_32 0x5156c
+#define A_GCACHE_GC0_DBG_ADDR_64_32 0x51570
+#define A_GCACHE_GC0_DBG_ADDR_96_32 0x51574
+#define A_GCACHE_GC0_DBG_ADDR_0_64 0x51578
+#define A_GCACHE_GC0_DBG_ADDR_64_64 0x5157c
+#define A_GCACHE_GC0_DBG_ADDR_0_96 0x51580
+#define A_GCACHE_GC0_DBG_ADDR_32_96 0x51584
+#define A_GCACHE_GC1_DBG_ADDR_0_32 0x5158c
+#define A_GCACHE_GC1_DBG_ADDR_32_32 0x51590
+#define A_GCACHE_GC1_DBG_ADDR_64_32 0x51594
+#define A_GCACHE_GC1_DBG_ADDR_96_32 0x51598
+#define A_GCACHE_GC1_DBG_ADDR_0_64 0x5159c
+#define A_GCACHE_GC1_DBG_ADDR_64_64 0x515a0
+#define A_GCACHE_GC1_DBG_ADDR_0_96 0x515a4
+#define A_GCACHE_GC1_DBG_ADDR_32_96 0x515a8
+#define A_GCACHE_GC0_DBG_ADDR_32_64 0x515ac
+#define A_GCACHE_GC1_DBG_ADDR_32_64 0x515b0
+#define A_GCACHE_PERF_GC0_EVICT 0x515b4
+#define A_GCACHE_PERF_GC1_EVICT 0x515b8
+#define A_GCACHE_PERF_GC0_CE_COUNT 0x515bc
+#define A_GCACHE_PERF_GC1_CE_COUNT 0x515c0
+#define A_GCACHE_PERF_GC0_UE_COUNT 0x515c4
+#define A_GCACHE_PERF_GC1_UE_COUNT 0x515c8
+#define A_GCACHE_DBG_CTL 0x515f0
+#define A_GCACHE_DBG_DATA 0x515f4
diff --git a/sys/dev/cxgbe/common/t4_regs_values.h b/sys/dev/cxgbe/common/t4_regs_values.h
index 830828097802..6485fa50bd08 100644
--- a/sys/dev/cxgbe/common/t4_regs_values.h
+++ b/sys/dev/cxgbe/common/t4_regs_values.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2016, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -269,6 +268,7 @@
 
 #define X_WINDOW_SHIFT			10
 #define X_PCIEOFST_SHIFT		10
+#define X_T7_MEMOFST_SHIFT		4
 
 /*
  * TP definitions.
@@ -284,6 +284,10 @@
 #define S_FT_FIRST			S_FCOE
 #define S_FT_LAST			S_FRAGMENTATION
 
+#define S_T7_FT_FIRST			S_IPSECIDX
+#define S_T7_FT_LAST			S_TCPFLAGS
+
+#define W_FT_IPSECIDX			12
 #define W_FT_FCOE			1
 #define W_FT_PORT			3
 #define W_FT_VNIC_ID			17
@@ -294,17 +298,9 @@
 #define W_FT_MACMATCH			9
 #define W_FT_MPSHITTYPE			3
 #define W_FT_FRAGMENTATION		1
-
-#define M_FT_FCOE			((1ULL << W_FT_FCOE) - 1)
-#define M_FT_PORT			((1ULL << W_FT_PORT) - 1)
-#define M_FT_VNIC_ID			((1ULL << W_FT_VNIC_ID) - 1)
-#define M_FT_VLAN			((1ULL << W_FT_VLAN) - 1)
-#define M_FT_TOS			((1ULL << W_FT_TOS) - 1)
-#define M_FT_PROTOCOL			((1ULL << W_FT_PROTOCOL) - 1)
-#define M_FT_ETHERTYPE			((1ULL << W_FT_ETHERTYPE) - 1)
-#define M_FT_MACMATCH			((1ULL << W_FT_MACMATCH) - 1)
-#define M_FT_MPSHITTYPE			((1ULL << W_FT_MPSHITTYPE) - 1)
-#define M_FT_FRAGMENTATION		((1ULL << W_FT_FRAGMENTATION) - 1)
+#define W_FT_ROCE			1
+#define W_FT_SYNONLY			1
+#define W_FT_TCPFLAGS			12
 
 /*
  * Some of the Compressed Filter Tuple fields have internal structure.  These
@@ -327,6 +323,6 @@
 
 #define S_FT_VNID_ID_VLD		16
 #define V_FT_VNID_ID_VLD(x)		((x) << S_FT_VNID_ID_VLD)
-#define F_FT_VNID_ID_VLD(x)		V_FT_VNID_ID_VLD(1U)
+#define F_FT_VNID_ID_VLD		V_FT_VNID_ID_VLD(1U)
 
 #endif /* __T4_REGS_VALUES_H__ */
diff --git a/sys/dev/cxgbe/common/t4_tcb.h b/sys/dev/cxgbe/common/t4_tcb.h
index f9631ba58418..8bff15f04e7a 100644
--- a/sys/dev/cxgbe/common/t4_tcb.h
+++ b/sys/dev/cxgbe/common/t4_tcb.h
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2016, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -340,10 +339,9 @@
 
 /* 1023:1020 */
 #define W_TCB_ULP_EXT    31
-#define S_TCP_ULP_EXT    28
+#define S_TCB_ULP_EXT    28
 #define M_TCB_ULP_EXT    0xfULL
-#define V_TCB_ULP_EXT(x) ((x) << S_TCP_ULP_EXT)
-
+#define V_TCB_ULP_EXT(x) ((x) << S_TCB_ULP_EXT)
 
 /* 840:832 */
 #define W_TCB_IRS_ULP    26
@@ -495,31 +493,31 @@
 #define M_TCB_RX_DDP_BUF1_TAG    0xffffffffULL
 #define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG)
 
-/* 855:832  */
+/* 855:832 */
 #define W_TCB_RX_TLS_BUF_OFFSET    26
 #define S_TCB_RX_TLS_BUF_OFFSET    0
 #define M_TCB_RX_TLS_BUF_OFFSET    0xffffffULL
 #define V_TCB_RX_TLS_BUF_OFFSET(x) ((x) << S_TCB_RX_TLS_BUF_OFFSET)
 
-/* 876:856  */
+/* 879:856 */
 #define W_TCB_RX_TLS_BUF_LEN    26
 #define S_TCB_RX_TLS_BUF_LEN    24
 #define M_TCB_RX_TLS_BUF_LEN    0xffffffULL
 #define V_TCB_RX_TLS_BUF_LEN(x) ((__u64)(x) << S_TCB_RX_TLS_BUF_LEN)
 
-/* 895:880  */
-#define W_TCB_RX_TLS_FLAGS    26
-#define S_TCB_RX_TLS_FLAGS    48
+/* 895:880 */
+#define W_TCB_RX_TLS_FLAGS    27
+#define S_TCB_RX_TLS_FLAGS    16
 #define M_TCB_RX_TLS_FLAGS    0xffffULL
 #define V_TCB_RX_TLS_FLAGS(x) ((__u64)(x) << S_TCB_RX_TLS_FLAGS)
 
-/* 959:896  */
-#define W_TCB_TLS_SEQ    28
-#define S_TCB_TLS_SEQ    0
-#define M_TCB_TLS_SEQ    0xffffffffffffffffULL
-#define V_TCB_TLS_SEQ(x) ((__u64)(x) << S_TCB_TLS_SEQ)
+/* 959:896 */
+#define W_TCB_RX_TLS_SEQ    28
+#define S_TCB_RX_TLS_SEQ    0
+#define M_TCB_RX_TLS_SEQ    0xffffffffffffffffULL
+#define V_TCB_RX_TLS_SEQ(x) ((__u64)(x) << S_TCB_RX_TLS_SEQ)
 
-/* 991:960  */
+/* 991:960 */
 #define W_TCB_RX_TLS_BUF_TAG    30
 #define S_TCB_RX_TLS_BUF_TAG    0
 #define M_TCB_RX_TLS_BUF_TAG    0xffffffffULL
@@ -531,17 +529,113 @@
 #define M_TCB_RX_TLS_KEY_TAG    0xffffffffULL
 #define V_TCB_RX_TLS_KEY_TAG(x) ((x) << S_TCB_RX_TLS_KEY_TAG)
 
+#define S_TF_TLS_ENABLE    0
+#define V_TF_TLS_ENABLE(x) ((x) << S_TF_TLS_ENABLE)
+
+#define S_TF_TLS_ACTIVE    1
+#define V_TF_TLS_ACTIVE(x) ((x) << S_TF_TLS_ACTIVE)
+
+#define S_TF_TLS_CONTROL    2
+#define V_TF_TLS_CONTROL(x) ((x) << S_TF_TLS_CONTROL)
+
 #define S_TF_TLS_KEY_SIZE    7
 #define V_TF_TLS_KEY_SIZE(x) ((x) << S_TF_TLS_KEY_SIZE)
 
-#define S_TF_TLS_CONTROL     2
-#define V_TF_TLS_CONTROL(x) ((x) << S_TF_TLS_CONTROL)
+/* 853:832 */
+#define W_TCB_TPT_OFFSET    26
+#define S_TCB_TPT_OFFSET    0
+#define M_TCB_TPT_OFFSET    0x3fffffULL
+#define V_TCB_TPT_OFFSET(x) ((x) << S_TCB_TPT_OFFSET)
+
+/* 863:854 */
+#define W_TCB_T10_CONFIG    26
+#define S_TCB_T10_CONFIG    22
+#define M_TCB_T10_CONFIG    0x3ffULL
+#define V_TCB_T10_CONFIG(x) ((x) << S_TCB_T10_CONFIG)
+
+/* 871:864 */
+#define W_TCB_PDU_HLEN    27
+#define S_TCB_PDU_HLEN    0
+#define M_TCB_PDU_HLEN    0xffULL
+#define V_TCB_PDU_HLEN(x) ((x) << S_TCB_PDU_HLEN)
+
+/* 879:872 */
+#define W_TCB_PDU_PDO    27
+#define S_TCB_PDU_PDO    8
+#define M_TCB_PDU_PDO    0xffULL
+#define V_TCB_PDU_PDO(x) ((x) << S_TCB_PDU_PDO)
 
-#define S_TF_TLS_ACTIVE      1
-#define V_TF_TLS_ACTIVE(x) ((x) << S_TF_TLS_ACTIVE)
+/* 895:880 */
+#define W_TCB_N_CQ_IDX_RQ    27
+#define S_TCB_N_CQ_IDX_RQ    16
+#define M_TCB_N_CQ_IDX_RQ    0xffffULL
+#define V_TCB_N_CQ_IDX_RQ(x) ((x) << S_TCB_N_CQ_IDX_RQ)
+
+/* 900:896 */
+#define W_TCB_NVMT_PDA    28
+#define S_TCB_NVMT_PDA    0
+#define M_TCB_NVMT_PDA    0x1fULL
+#define V_TCB_NVMT_PDA(x) ((x) << S_TCB_NVMT_PDA)
+
+/* 911:901 */
+#define W_TCB_RSVD    28
+#define S_TCB_RSVD    5
+#define M_TCB_RSVD    0x7ffULL
+#define V_TCB_RSVD(x) ((x) << S_TCB_RSVD)
 
-#define S_TF_TLS_ENABLE      0
-#define V_TF_TLS_ENABLE(x) ((x) << S_TF_TLS_ENABLE)
+/* 927:912 */
+#define W_TCB_N_PD_ID    28
+#define S_TCB_N_PD_ID    16
+#define M_TCB_N_PD_ID    0xffffULL
+#define V_TCB_N_PD_ID(x) ((x) << S_TCB_N_PD_ID)
+
+/* 929:928 */
+#define W_TCB_CMP_IMM_SZ    29
+#define S_TCB_CMP_IMM_SZ    0
+#define M_TCB_CMP_IMM_SZ    0x3ULL
+#define V_TCB_CMP_IMM_SZ(x) ((x) << S_TCB_CMP_IMM_SZ)
+
+/* 931:930 */
+#define W_TCB_PDU_DGST_FLAGS    29
+#define S_TCB_PDU_DGST_FLAGS    2
+#define M_TCB_PDU_DGST_FLAGS    0x3ULL
+#define V_TCB_PDU_DGST_FLAGS(x) ((x) << S_TCB_PDU_DGST_FLAGS)
+
+/* 959:932 */
+#define W_TCB_RSVD1    29
+#define S_TCB_RSVD1    4
+#define M_TCB_RSVD1    0xfffffffULL
+#define V_TCB_RSVD1(x) ((x) << S_TCB_RSVD1)
+
+/* 985:960 */
+#define W_TCB_N_RQ_START    30
+#define S_TCB_N_RQ_START    0
+#define M_TCB_N_RQ_START    0x3ffffffULL
+#define V_TCB_N_RQ_START(x) ((x) << S_TCB_N_RQ_START)
+
+/* 998:986 */
+#define W_TCB_N_RQ_MSN    30
+#define S_TCB_N_RQ_MSN    26
+#define M_TCB_N_RQ_MSN    0x1fffULL
+#define V_TCB_N_RQ_MSN(x) ((__u64)(x) << S_TCB_N_RQ_MSN)
+
+/* 1002:999 */
+#define W_TCB_N_RQ_MAX_OFFSET    31
+#define S_TCB_N_RQ_MAX_OFFSET    7
+#define M_TCB_N_RQ_MAX_OFFSET    0xfULL
+#define V_TCB_N_RQ_MAX_OFFSET(x) ((x) << S_TCB_N_RQ_MAX_OFFSET)
+
+/* 1015:1003 */
+#define W_TCB_N_RQ_WRITE_PTR    31
+#define S_TCB_N_RQ_WRITE_PTR    11
+#define M_TCB_N_RQ_WRITE_PTR    0x1fffULL
+#define V_TCB_N_RQ_WRITE_PTR(x) ((x) << S_TCB_N_RQ_WRITE_PTR)
+
+/* 1023:1016 */
+#define W_TCB_N_PDU_TYPE    31
+#define S_TCB_N_PDU_TYPE    24
+#define M_TCB_N_PDU_TYPE    0xffULL
+#define V_TCB_N_PDU_TYPE(x) ((x) << S_TCB_N_PDU_TYPE)
 
 #define S_TF_MIGRATING    0
 #define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING)
@@ -549,15 +643,24 @@
 #define S_TF_NON_OFFLOAD    1
 #define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD)
 
+#define S_TF_FILTER    1
+#define V_TF_FILTER(x) ((x) << S_TF_FILTER)
+
 #define S_TF_LOCK_TID    2
 #define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID)
 
 #define S_TF_KEEPALIVE    3
 #define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE)
 
+#define S_TF_DROP_ENCAPS_HDR    3
+#define V_TF_DROP_ENCAPS_HDR(x) ((x) << S_TF_DROP_ENCAPS_HDR)
+
 #define S_TF_DACK    4
 #define V_TF_DACK(x) ((x) << S_TF_DACK)
 
+#define S_TF_COUNT_HITS    4
+#define V_TF_COUNT_HITS(x) ((x) << S_TF_COUNT_HITS)
+
 #define S_TF_DACK_MSS    5
 #define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS)
 
@@ -567,6 +670,9 @@
 #define S_TF_NAGLE    7
 #define V_TF_NAGLE(x) ((x) << S_TF_NAGLE)
 
+#define S_TF_REMOVE_VLAN    7
+#define V_TF_REMOVE_VLAN(x) ((x) << S_TF_REMOVE_VLAN)
+
 #define S_TF_SSWS_DISABLED    8
 #define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED)
 
@@ -576,15 +682,24 @@
 #define S_TF_RX_FLOW_CONTROL_DISABLE    10
 #define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE)
 
+#define S_TF_NAT_SEQ_CHECK    10
+#define V_TF_NAT_SEQ_CHECK(x) ((x) << S_TF_NAT_SEQ_CHECK)
+
 #define S_TF_RX_CHANNEL    11
 #define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL)
 
 #define S_TF_TX_CHANNEL0    12
 #define V_TF_TX_CHANNEL0(x) ((x) << S_TF_TX_CHANNEL0)
 
+#define S_TF_LPBK_TX_CHANNEL0    12
+#define V_TF_LPBK_TX_CHANNEL0(x) ((x) << S_TF_LPBK_TX_CHANNEL0)
+
 #define S_TF_TX_CHANNEL1    13
 #define V_TF_TX_CHANNEL1(x) ((x) << S_TF_TX_CHANNEL1)
 
+#define S_TF_LPBK_TX_CHANNEL1    13
+#define V_TF_LPBK_TX_CHANNEL1(x) ((x) << S_TF_LPBK_TX_CHANNEL1)
+
 #define S_TF_TX_QUIESCE    14
 #define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE)
 
@@ -607,6 +722,10 @@
 #define M_TF_TX_QUEUE    0x7ULL
 #define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE)
 
+#define S_TF_NAT_MODE    18
+#define M_TF_NAT_MODE    0x7ULL
+#define V_TF_NAT_MODE(x) ((x) << S_TF_NAT_MODE)
+
 #define S_TF_TURBO    21
 #define V_TF_TURBO(x) ((x) << S_TF_TURBO)
 
@@ -652,8 +771,8 @@
 #define S_TF_RCV_COALESCE_HEARTBEAT    32
 #define V_TF_RCV_COALESCE_HEARTBEAT(x) ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT)
 
-#define S_TF_INIT    33
-#define V_TF_INIT(x) ((__u64)(x) << S_TF_INIT)
+#define S_TF_RSS_FW    33
+#define V_TF_RSS_FW(x) ((__u64)(x) << S_TF_RSS_FW)
 
 #define S_TF_ACTIVE_OPEN    34
 #define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN)
@@ -712,12 +831,21 @@
 #define S_TF_RECV_SCALE    52
 #define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE)
 
+#define S_TF_NAT_FLAG_CHECK    52
+#define V_TF_NAT_FLAG_CHECK(x) ((__u64)(x) << S_TF_NAT_FLAG_CHECK)
+
 #define S_TF_RECV_TSTMP    53
 #define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP)
 
+#define S_TF_LPBK_TX_LPBK    53
+#define V_TF_LPBK_TX_LPBK(x) ((__u64)(x) << S_TF_LPBK_TX_LPBK)
+
 #define S_TF_RECV_SACK    54
 #define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK)
 
+#define S_TF_SWAP_MAC_ADDR    54
+#define V_TF_SWAP_MAC_ADDR(x) ((__u64)(x) << S_TF_SWAP_MAC_ADDR)
+
 #define S_TF_PEND_CTL0    55
 #define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0)
 
@@ -751,6 +879,9 @@
 #define S_TF_CCTRL_RFR    62
 #define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR)
 
+#define S_TF_INSERT_VLAN    62
+#define V_TF_INSERT_VLAN(x) ((__u64)(x) << S_TF_INSERT_VLAN)
+
 #define S_TF_CORE_BYPASS    63
 #define V_TF_CORE_BYPASS(x) ((__u64)(x) << S_TF_CORE_BYPASS)
 
@@ -772,6 +903,9 @@
 #define S_TF_DDP_RX2TX    21
 #define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX)
 
+#define S_TF_DDP_INDICATE_FLL    22
+#define V_TF_DDP_INDICATE_FLL(x) ((x) << S_TF_DDP_INDICATE_FLL)
+
 #define S_TF_DDP_BUF0_VALID    24
 #define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID)
 
diff --git a/sys/dev/cxgbe/crypto/t4_crypto.c b/sys/dev/cxgbe/crypto/t4_crypto.c
index 2c83b10b13d6..80e31b1159fd 100644
--- a/sys/dev/cxgbe/crypto/t4_crypto.c
+++ b/sys/dev/cxgbe/crypto/t4_crypto.c
@@ -208,6 +208,7 @@ struct ccr_softc {
 	counter_u64_t stats_pad_error;
 	counter_u64_t stats_sglist_error;
 	counter_u64_t stats_process_error;
+	counter_u64_t stats_pointer_error;
 	counter_u64_t stats_sw_fallback;
 
 	struct sysctl_ctx_list ctx;
@@ -458,8 +459,9 @@ ccr_populate_wreq(struct ccr_softc *sc, struct ccr_session *s,
 
 	crwr->ulptx.cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
 	    V_ULP_TXPKT_DATAMODIFY(0) |
-	    V_ULP_TXPKT_CHANNELID(s->port->tx_channel_id) |
+	    V_T7_ULP_TXPKT_CHANNELID(s->port->tx_channel_id) |
 	    V_ULP_TXPKT_DEST(0) |
+	    (is_t7(sc->adapter) ? V_ULP_TXPKT_CMDMORE(1) : 0) |
 	    V_ULP_TXPKT_FID(sc->first_rxq_id) | V_ULP_TXPKT_RO(1));
 	crwr->ulptx.len = htobe32(
 	    ((wr_len - sizeof(struct fw_crypto_lookaside_wr)) / 16));
@@ -545,7 +547,7 @@ ccr_hash(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
 
 	crwr->sec_cpl.op_ivinsrtofst = htobe32(
 	    V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
-	    V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
+	    V_T7_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
 	    V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
 	    V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
 	    V_CPL_TX_SEC_PDU_IVINSRTOFST(0));
@@ -705,7 +707,7 @@ ccr_cipher(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
 
 	crwr->sec_cpl.op_ivinsrtofst = htobe32(
 	    V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
-	    V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
+	    V_T7_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
 	    V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
 	    V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
 	    V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
@@ -1006,7 +1008,7 @@ ccr_eta(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
 
 	crwr->sec_cpl.op_ivinsrtofst = htobe32(
 	    V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
-	    V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
+	    V_T7_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
 	    V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
 	    V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
 	    V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
@@ -1293,7 +1295,7 @@ ccr_gcm(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
 
 	crwr->sec_cpl.op_ivinsrtofst = htobe32(
 	    V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
-	    V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
+	    V_T7_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
 	    V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
 	    V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
 	    V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
@@ -1645,7 +1647,7 @@ ccr_ccm(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
 
 	crwr->sec_cpl.op_ivinsrtofst = htobe32(
 	    V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
-	    V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
+	    V_T7_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
 	    V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
 	    V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
 	    V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
@@ -1883,6 +1885,9 @@ ccr_sysctls(struct ccr_softc *sc)
 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "process_error",
 	    CTLFLAG_RD, &sc->stats_process_error,
 	    "Requests failed during queueing");
+	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "pointer_error",
+	    CTLFLAG_RD, &sc->stats_pointer_error,
+	    "Requests with a misaligned request pointer");
 	SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "sw_fallback",
 	    CTLFLAG_RD, &sc->stats_sw_fallback,
 	    "Requests processed by falling back to software");
@@ -1932,13 +1937,15 @@ ccr_init_port(struct ccr_softc *sc, int port)
 	    "Too many ports to fit in port_mask");
 
 	/*
-	 * Completions for crypto requests on port 1 can sometimes
+	 * Completions for crypto requests on port 1 on T6 can sometimes
 	 * return a stale cookie value due to a firmware bug.  Disable
 	 * requests on port 1 by default on affected firmware.
 	 */
-	if (sc->adapter->params.fw_vers >= FW_VERSION32(1, 25, 4, 0) ||
-	    port == 0)
-		sc->port_mask |= 1u << port;
+	if (port != 0 && is_t6(sc->adapter) &&
+	    sc->adapter->params.fw_vers < FW_VERSION32(1, 25, 4, 0))
+		return;
+
+	sc->port_mask |= 1u << port;
 }
 
 static int
@@ -1988,6 +1995,7 @@ ccr_attach(device_t dev)
 	sc->stats_pad_error = counter_u64_alloc(M_WAITOK);
 	sc->stats_sglist_error = counter_u64_alloc(M_WAITOK);
 	sc->stats_process_error = counter_u64_alloc(M_WAITOK);
+	sc->stats_pointer_error = counter_u64_alloc(M_WAITOK);
 	sc->stats_sw_fallback = counter_u64_alloc(M_WAITOK);
 	ccr_sysctls(sc);
 
@@ -2034,6 +2042,7 @@ ccr_detach(device_t dev)
 	counter_u64_free(sc->stats_pad_error);
 	counter_u64_free(sc->stats_sglist_error);
 	counter_u64_free(sc->stats_process_error);
+	counter_u64_free(sc->stats_pointer_error);
 	counter_u64_free(sc->stats_sw_fallback);
 	for_each_port(sc->adapter, i) {
 		ccr_free_port(sc, i);
@@ -2531,6 +2540,16 @@ ccr_process(device_t dev, struct cryptop *crp, int hint)
 	s = crypto_get_driver_session(crp->crp_session);
 	sc = device_get_softc(dev);
 
+	/*
+	 * Request pointers with the low bit set in the pointer can't
+	 * be stored as the cookie in the CPL_FW6_PLD reply.
+	 */
+	if (((uintptr_t)crp & CPL_FW6_COOKIE_MASK) != 0) {
+		counter_u64_add(sc->stats_pointer_error, 1);
+		error = EINVAL;
+		goto out_unlocked;
+	}
+
 	mtx_lock(&s->lock);
 	error = ccr_populate_sglist(s->sg_input, &crp->crp_buf);
 	if (error == 0 && CRYPTO_HAS_OUTPUT_BUFFER(crp))
@@ -2637,6 +2656,7 @@ ccr_process(device_t dev, struct cryptop *crp, int hint)
 out:
 	mtx_unlock(&s->lock);
 
+out_unlocked:
 	if (error) {
 		crp->crp_etype = error;
 		crypto_done(crp);
@@ -2646,7 +2666,7 @@ out:
 }
 
 static int
-do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss,
+fw6_pld_ccr(struct sge_iq *iq, const struct rss_header *rss,
     struct mbuf *m)
 {
 	struct ccr_softc *sc;
@@ -2661,7 +2681,7 @@ do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss,
 	else
 		cpl = (const void *)(rss + 1);
 
-	crp = (struct cryptop *)(uintptr_t)be64toh(cpl->data[1]);
+	crp = (struct cryptop *)(uintptr_t)CPL_FW6_PLD_COOKIE(cpl);
 	s = crypto_get_driver_session(crp->crp_session);
 	status = be64toh(cpl->data[0]);
 	if (CHK_MAC_ERR_BIT(status) || CHK_PAD_ERR_BIT(status))
@@ -2715,10 +2735,12 @@ ccr_modevent(module_t mod, int cmd, void *arg)
 
 	switch (cmd) {
 	case MOD_LOAD:
-		t4_register_cpl_handler(CPL_FW6_PLD, do_cpl6_fw_pld);
+		t4_register_shared_cpl_handler(CPL_FW6_PLD, fw6_pld_ccr,
+		    CPL_FW6_COOKIE_CCR);
 		return (0);
 	case MOD_UNLOAD:
-		t4_register_cpl_handler(CPL_FW6_PLD, NULL);
+		t4_register_shared_cpl_handler(CPL_FW6_PLD, NULL,
+		    CPL_FW6_COOKIE_CCR);
 		return (0);
 	default:
 		return (EOPNOTSUPP);
@@ -2745,7 +2767,9 @@ static driver_t ccr_driver = {
 	sizeof(struct ccr_softc)
 };
 
-DRIVER_MODULE(ccr, t6nex, ccr_driver, ccr_modevent, NULL);
+DRIVER_MODULE(ccr, chnex, ccr_driver, ccr_modevent, NULL);
+DRIVER_MODULE(ccr, t6nex, ccr_driver, NULL, NULL);
 MODULE_VERSION(ccr, 1);
 MODULE_DEPEND(ccr, crypto, 1, 1, 1);
+MODULE_DEPEND(ccr, chnex, 1, 1, 1);
 MODULE_DEPEND(ccr, t6nex, 1, 1, 1);
diff --git a/sys/dev/cxgbe/crypto/t4_crypto.h b/sys/dev/cxgbe/crypto/t4_crypto.h
index 452e48d20dfd..71c9ec3903ef 100644
--- a/sys/dev/cxgbe/crypto/t4_crypto.h
+++ b/sys/dev/cxgbe/crypto/t4_crypto.h
@@ -139,6 +139,7 @@ struct phys_sge_pairs {
 #define SCMD_PROTO_VERSION_TLS_1_2 0
 #define SCMD_PROTO_VERSION_TLS_1_1 1
 #define SCMD_PROTO_VERSION_GENERIC 4
+#define SCMD_PROTO_VERSION_TLS_1_3 8
 
 #define SCMD_CIPH_MODE_NOP               0
 #define SCMD_CIPH_MODE_AES_CBC           1
diff --git a/sys/dev/cxgbe/crypto/t4_keyctx.c b/sys/dev/cxgbe/crypto/t4_keyctx.c
index 50e339ac2e05..b85e50fd6cb1 100644
--- a/sys/dev/cxgbe/crypto/t4_keyctx.c
+++ b/sys/dev/cxgbe/crypto/t4_keyctx.c
@@ -437,10 +437,16 @@ t4_tls_key_info_size(const struct ktls_session *tls)
 int
 t4_tls_proto_ver(const struct ktls_session *tls)
 {
-	if (tls->params.tls_vminor == TLS_MINOR_VER_ONE)
+	switch (tls->params.tls_vminor) {
+	case TLS_MINOR_VER_ONE:
 		return (SCMD_PROTO_VERSION_TLS_1_1);
-	else
+	case TLS_MINOR_VER_TWO:
 		return (SCMD_PROTO_VERSION_TLS_1_2);
+	case TLS_MINOR_VER_THREE:
+		return (SCMD_PROTO_VERSION_TLS_1_3);
+	default:
+		__assert_unreachable();
+	}
 }
 
 int
@@ -492,6 +498,17 @@ t4_tls_hmac_ctrl(const struct ktls_session *tls)
 }
 
 static int
+tls_seqnum_ctrl(const struct ktls_session *tls)
+{
+	switch (tls->params.tls_vminor) {
+	case TLS_MINOR_VER_THREE:
+		return (0);
+	default:
+		return (3);
+	}
+}
+
+static int
 tls_cipher_key_size(const struct ktls_session *tls)
 {
 	switch (tls->params.cipher_key_len) {
@@ -557,7 +574,7 @@ t4_tls_key_ctx(const struct ktls_session *tls, int direction,
 
 		kctx->u.rxhdr.authmode_to_rxvalid =
 		    V_TLS_KEYCTX_TX_WR_AUTHMODE(t4_tls_auth_mode(tls)) |
-		    V_TLS_KEYCTX_TX_WR_SEQNUMCTRL(3) |
+		    V_TLS_KEYCTX_TX_WR_SEQNUMCTRL(tls_seqnum_ctrl(tls)) |
 		    V_TLS_KEYCTX_TX_WR_RXVALID(1);
 
 		kctx->u.rxhdr.ivpresent_to_rxmk_size =
@@ -607,7 +624,8 @@ t4_tls_key_ctx(const struct ktls_session *tls, int direction,
 		_Static_assert(offsetof(struct tx_keyctx_hdr, txsalt) ==
 		    offsetof(struct rx_keyctx_hdr, rxsalt),
 		    "salt offset mismatch");
-		memcpy(kctx->u.txhdr.txsalt, tls->params.iv, SALT_SIZE);
+		memcpy(kctx->u.txhdr.txsalt, tls->params.iv,
+		    tls->params.iv_len);
 		t4_init_gmac_hash(tls->params.cipher_key,
 		    tls->params.cipher_key_len, hash);
 	} else {
@@ -665,6 +683,10 @@ t4_write_tlskey_wr(const struct ktls_session *tls, int direction, int tid,
 	kwr->reneg_to_write_rx = V_KEY_GET_LOC(direction == KTLS_TX ?
 	    KEY_WRITE_TX : KEY_WRITE_RX);
 
+	/* We don't need to use V_T7_ULP_MEMIO_DATA_LEN in this routine. */
+	_Static_assert(V_T7_ULP_MEMIO_DATA_LEN(TLS_KEY_CONTEXT_SZ >> 5) ==
+	    V_ULP_MEMIO_DATA_LEN(TLS_KEY_CONTEXT_SZ >> 5), "datalen mismatch");
+
 	/* master command */
 	kwr->cmd = htobe32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) |
 	    V_T5_ULP_MEMIO_ORDER(1) | V_T5_ULP_MEMIO_IMM(1));
diff --git a/sys/dev/cxgbe/crypto/t6_kern_tls.c b/sys/dev/cxgbe/crypto/t6_kern_tls.c
index 04bb6c944050..454b2e264a0e 100644
--- a/sys/dev/cxgbe/crypto/t6_kern_tls.c
+++ b/sys/dev/cxgbe/crypto/t6_kern_tls.c
@@ -2003,7 +2003,7 @@ t6_ktls_write_wr(struct sge_txq *txq, void *dst, struct mbuf *m,
 		if (tlsp->l2te)
 			t4_l2t_release(tlsp->l2te);
 		tlsp->l2te = t4_l2t_alloc_tls(tlsp->sc, txq, dst, &ndesc,
-		    vlan_tag, tlsp->vi->pi->lport, eh->ether_dhost);
+		    vlan_tag, tlsp->vi->pi->hw_port, eh->ether_dhost);
 		if (tlsp->l2te == NULL)
 			CXGBE_UNIMPLEMENTED("failed to allocate TLS L2TE");
 		if (ndesc != 0) {
diff --git a/sys/dev/cxgbe/crypto/t7_kern_tls.c b/sys/dev/cxgbe/crypto/t7_kern_tls.c
new file mode 100644
index 000000000000..217459126361
--- /dev/null
+++ b/sys/dev/cxgbe/crypto/t7_kern_tls.c
@@ -0,0 +1,2196 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2025 Chelsio Communications
+ * Written by: John Baldwin <jhb@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_inet.h"
+#include "opt_inet6.h"
+#include "opt_kern_tls.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/ktr.h>
+#include <sys/ktls.h>
+#include <sys/sglist.h>
+#include <sys/socket.h>
+#include <sys/socketvar.h>
+#include <sys/sockbuf.h>
+#include <netinet/in.h>
+#include <netinet/in_pcb.h>
+#include <netinet/ip.h>
+#include <netinet/ip6.h>
+#include <netinet/tcp_var.h>
+#include <opencrypto/cryptodev.h>
+#include <opencrypto/xform.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include "common/common.h"
+#include "common/t4_regs.h"
+#include "common/t4_regs_values.h"
+#include "common/t4_tcb.h"
+#include "t4_l2t.h"
+#include "t4_clip.h"
+#include "t4_mp_ring.h"
+#include "crypto/t4_crypto.h"
+
+#if defined(INET) || defined(INET6)
+
+#define TLS_HEADER_LENGTH		5
+
+struct tls_scmd {
+	__be32 seqno_numivs;
+	__be32 ivgen_hdrlen;
+};
+
+struct tlspcb {
+	struct m_snd_tag com;
+	struct vi_info *vi;	/* virtual interface */
+	struct adapter *sc;
+	struct sge_txq *txq;
+
+	int tx_key_addr;
+	bool inline_key;
+	bool tls13;
+	unsigned char enc_mode;
+
+	struct tls_scmd scmd0;
+	struct tls_scmd scmd0_partial;
+	struct tls_scmd scmd0_short;
+
+	unsigned int tx_key_info_size;
+
+	uint16_t prev_mss;
+
+	/* Fields used for GCM records using GHASH state. */
+	uint16_t ghash_offset;
+	uint64_t ghash_tls_seqno;
+	char ghash[AES_GMAC_HASH_LEN];
+	bool ghash_valid;
+	bool ghash_pending;
+	bool ghash_lcb;
+	bool queue_mbufs;
+	uint8_t rx_chid;
+	uint16_t rx_qid;
+	struct mbufq pending_mbufs;
+
+	/*
+	 * Only used outside of setup and teardown when using inline
+	 * keys or for partial GCM mode.
+	 */
+	struct tls_keyctx keyctx;
+};
+
+static void t7_tls_tag_free(struct m_snd_tag *mst);
+static int ktls_setup_keys(struct tlspcb *tlsp,
+    const struct ktls_session *tls, struct sge_txq *txq);
+
+static void *zero_buffer;
+static vm_paddr_t zero_buffer_pa;
+
+static const struct if_snd_tag_sw t7_tls_tag_sw = {
+	.snd_tag_free = t7_tls_tag_free,
+	.type = IF_SND_TAG_TYPE_TLS
+};
+
+static inline struct tlspcb *
+mst_to_tls(struct m_snd_tag *t)
+{
+	return (__containerof(t, struct tlspcb, com));
+}
+
+static struct tlspcb *
+alloc_tlspcb(struct ifnet *ifp, struct vi_info *vi, int flags)
+{
+	struct port_info *pi = vi->pi;
+	struct adapter *sc = pi->adapter;
+	struct tlspcb *tlsp;
+
+	tlsp = malloc(sizeof(*tlsp), M_CXGBE, M_ZERO | flags);
+	if (tlsp == NULL)
+		return (NULL);
+
+	m_snd_tag_init(&tlsp->com, ifp, &t7_tls_tag_sw);
+	tlsp->vi = vi;
+	tlsp->sc = sc;
+	tlsp->tx_key_addr = -1;
+	tlsp->ghash_offset = -1;
+	tlsp->rx_chid = pi->rx_chan;
+	tlsp->rx_qid = sc->sge.rxq[pi->vi->first_rxq].iq.abs_id;
+	mbufq_init(&tlsp->pending_mbufs, INT_MAX);
+
+	return (tlsp);
+}
+
+int
+t7_tls_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params,
+    struct m_snd_tag **pt)
+{
+	const struct ktls_session *tls;
+	struct tlspcb *tlsp;
+	struct adapter *sc;
+	struct vi_info *vi;
+	struct inpcb *inp;
+	struct sge_txq *txq;
+	int error, iv_size, keyid, mac_first;
+
+	tls = params->tls.tls;
+
+	/* TLS 1.1 through TLS 1.3 are currently supported. */
+	if (tls->params.tls_vmajor != TLS_MAJOR_VER_ONE ||
+	    tls->params.tls_vminor < TLS_MINOR_VER_ONE ||
+	    tls->params.tls_vminor > TLS_MINOR_VER_THREE)
+		return (EPROTONOSUPPORT);
+
+	/* Sanity check values in *tls. */
+	switch (tls->params.cipher_algorithm) {
+	case CRYPTO_AES_CBC:
+		/* XXX: Explicitly ignore any provided IV. */
+		switch (tls->params.cipher_key_len) {
+		case 128 / 8:
+		case 192 / 8:
+		case 256 / 8:
+			break;
+		default:
+			return (EINVAL);
+		}
+		switch (tls->params.auth_algorithm) {
+		case CRYPTO_SHA1_HMAC:
+		case CRYPTO_SHA2_256_HMAC:
+		case CRYPTO_SHA2_384_HMAC:
+			break;
+		default:
+			return (EPROTONOSUPPORT);
+		}
+		iv_size = AES_BLOCK_LEN;
+		mac_first = 1;
+		break;
+	case CRYPTO_AES_NIST_GCM_16:
+		switch (tls->params.cipher_key_len) {
+		case 128 / 8:
+		case 192 / 8:
+		case 256 / 8:
+			break;
+		default:
+			return (EINVAL);
+		}
+
+		/*
+		 * The IV size for TLS 1.2 is the explicit IV in the
+		 * record header.  For TLS 1.3 it is the size of the
+		 * sequence number.
+		 */
+		iv_size = 8;
+		mac_first = 0;
+		break;
+	default:
+		return (EPROTONOSUPPORT);
+	}
+
+	vi = if_getsoftc(ifp);
+	sc = vi->adapter;
+
+	tlsp = alloc_tlspcb(ifp, vi, M_WAITOK);
+
+	/*
+	 * Pointers with the low bit set in the pointer can't
+	 * be stored as the cookie in the CPL_FW6_PLD reply.
+	 */
+	if (((uintptr_t)tlsp & CPL_FW6_COOKIE_MASK) != 0) {
+		error = EINVAL;
+		goto failed;
+	}
+
+	tlsp->tls13 = tls->params.tls_vminor == TLS_MINOR_VER_THREE;
+
+	if (sc->tlst.inline_keys)
+		keyid = -1;
+	else
+		keyid = t4_alloc_tls_keyid(sc);
+	if (keyid < 0) {
+		CTR(KTR_CXGBE, "%s: %p using immediate key ctx", __func__,
+		    tlsp);
+		tlsp->inline_key = true;
+	} else {
+		tlsp->tx_key_addr = keyid;
+		CTR(KTR_CXGBE, "%s: %p allocated TX key addr %#x", __func__,
+		    tlsp, tlsp->tx_key_addr);
+	}
+
+	inp = params->tls.inp;
+	INP_RLOCK(inp);
+	if (inp->inp_flags & INP_DROPPED) {
+		INP_RUNLOCK(inp);
+		error = ECONNRESET;
+		goto failed;
+	}
+
+	txq = &sc->sge.txq[vi->first_txq];
+	if (inp->inp_flowtype != M_HASHTYPE_NONE)
+		txq += ((inp->inp_flowid % (vi->ntxq - vi->rsrv_noflowq)) +
+		    vi->rsrv_noflowq);
+	tlsp->txq = txq;
+	INP_RUNLOCK(inp);
+
+	error = ktls_setup_keys(tlsp, tls, txq);
+	if (error)
+		goto failed;
+
+	tlsp->enc_mode = t4_tls_cipher_mode(tls);
+	tlsp->tx_key_info_size = t4_tls_key_info_size(tls);
+
+	/* The SCMD fields used when encrypting a full TLS record. */
+	if (tlsp->tls13)
+		tlsp->scmd0.seqno_numivs = V_SCMD_SEQ_NO_CTRL(0);
+	else
+		tlsp->scmd0.seqno_numivs = V_SCMD_SEQ_NO_CTRL(3);
+	tlsp->scmd0.seqno_numivs |=
+	    V_SCMD_PROTO_VERSION(t4_tls_proto_ver(tls)) |
+	    V_SCMD_ENC_DEC_CTRL(SCMD_ENCDECCTRL_ENCRYPT) |
+	    V_SCMD_CIPH_AUTH_SEQ_CTRL((mac_first == 0)) |
+	    V_SCMD_CIPH_MODE(tlsp->enc_mode) |
+	    V_SCMD_AUTH_MODE(t4_tls_auth_mode(tls)) |
+	    V_SCMD_HMAC_CTRL(t4_tls_hmac_ctrl(tls)) |
+	    V_SCMD_IV_SIZE(iv_size / 2) | V_SCMD_NUM_IVS(1);
+	tlsp->scmd0.seqno_numivs = htobe32(tlsp->scmd0.seqno_numivs);
+
+	tlsp->scmd0.ivgen_hdrlen = V_SCMD_IV_GEN_CTRL(0) |
+	    V_SCMD_TLS_FRAG_ENABLE(0);
+	if (tlsp->inline_key)
+		tlsp->scmd0.ivgen_hdrlen |= V_SCMD_KEY_CTX_INLINE(1);
+
+	/*
+	 * The SCMD fields used when encrypting a short TLS record
+	 * (no trailer and possibly a truncated payload).
+	 */
+	tlsp->scmd0_short.seqno_numivs = V_SCMD_SEQ_NO_CTRL(0) |
+	    V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
+	    V_SCMD_ENC_DEC_CTRL(SCMD_ENCDECCTRL_ENCRYPT) |
+	    V_SCMD_CIPH_AUTH_SEQ_CTRL((mac_first == 0)) |
+	    V_SCMD_AUTH_MODE(SCMD_AUTH_MODE_NOP) |
+	    V_SCMD_HMAC_CTRL(SCMD_HMAC_CTRL_NOP) |
+	    V_SCMD_IV_SIZE(AES_BLOCK_LEN / 2) | V_SCMD_NUM_IVS(0);
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM)
+		tlsp->scmd0_short.seqno_numivs |=
+		    V_SCMD_CIPH_MODE(SCMD_CIPH_MODE_AES_CTR);
+	else
+		tlsp->scmd0_short.seqno_numivs |=
+		    V_SCMD_CIPH_MODE(tlsp->enc_mode);
+	tlsp->scmd0_short.seqno_numivs =
+	    htobe32(tlsp->scmd0_short.seqno_numivs);
+
+	tlsp->scmd0_short.ivgen_hdrlen = V_SCMD_IV_GEN_CTRL(0) |
+	    V_SCMD_TLS_FRAG_ENABLE(0) | V_SCMD_AADIVDROP(1);
+	if (tlsp->inline_key)
+		tlsp->scmd0_short.ivgen_hdrlen |= V_SCMD_KEY_CTX_INLINE(1);
+
+	/*
+	 * The SCMD fields used when encrypting a short TLS record
+	 * using a partial GHASH.
+	 */
+	tlsp->scmd0_partial.seqno_numivs = V_SCMD_SEQ_NO_CTRL(0) |
+	    V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
+	    V_SCMD_ENC_DEC_CTRL(SCMD_ENCDECCTRL_ENCRYPT) |
+	    V_SCMD_CIPH_AUTH_SEQ_CTRL((mac_first == 0)) |
+	    V_SCMD_CIPH_MODE(tlsp->enc_mode) |
+	    V_SCMD_AUTH_MODE(t4_tls_auth_mode(tls)) |
+	    V_SCMD_HMAC_CTRL(t4_tls_hmac_ctrl(tls)) |
+	    V_SCMD_IV_SIZE(AES_BLOCK_LEN / 2) | V_SCMD_NUM_IVS(1);
+	tlsp->scmd0_partial.seqno_numivs =
+	    htobe32(tlsp->scmd0_partial.seqno_numivs);
+
+	tlsp->scmd0_partial.ivgen_hdrlen = V_SCMD_IV_GEN_CTRL(0) |
+	    V_SCMD_TLS_FRAG_ENABLE(0) | V_SCMD_AADIVDROP(1) |
+	    V_SCMD_KEY_CTX_INLINE(1);
+
+	TXQ_LOCK(txq);
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM)
+		txq->kern_tls_gcm++;
+	else
+		txq->kern_tls_cbc++;
+	TXQ_UNLOCK(txq);
+	*pt = &tlsp->com;
+	return (0);
+
+failed:
+	m_snd_tag_rele(&tlsp->com);
+	return (error);
+}
+
+static int
+ktls_setup_keys(struct tlspcb *tlsp, const struct ktls_session *tls,
+    struct sge_txq *txq)
+{
+	struct tls_key_req *kwr;
+	struct tls_keyctx *kctx;
+	void *items[1];
+	struct mbuf *m;
+	int error;
+
+	/*
+	 * Store the salt and keys in the key context.  For
+	 * connections with an inline key, this key context is passed
+	 * as immediate data in each work request.  For connections
+	 * storing the key in DDR, a work request is used to store a
+	 * copy of the key context in DDR.
+	 */
+	t4_tls_key_ctx(tls, KTLS_TX, &tlsp->keyctx);
+	if (tlsp->inline_key)
+		return (0);
+
+	/* Populate key work request. */
+        m = alloc_wr_mbuf(TLS_KEY_WR_SZ, M_NOWAIT);
+	if (m == NULL) {
+		CTR(KTR_CXGBE, "%s: %p failed to alloc WR mbuf", __func__,
+		    tlsp);
+		return (ENOMEM);
+	}
+	m->m_pkthdr.snd_tag = m_snd_tag_ref(&tlsp->com);
+	m->m_pkthdr.csum_flags |= CSUM_SND_TAG;
+	kwr = mtod(m, void *);
+	memset(kwr, 0, TLS_KEY_WR_SZ);
+
+	t4_write_tlskey_wr(tls, KTLS_TX, 0, 0, tlsp->tx_key_addr, kwr);
+	kctx = (struct tls_keyctx *)(kwr + 1);
+	memcpy(kctx, &tlsp->keyctx, sizeof(*kctx));
+
+	/*
+	 * Place the key work request in the transmit queue.  It
+	 * should be sent to the NIC before any TLS packets using this
+	 * session.
+	 */
+	items[0] = m;
+	error = mp_ring_enqueue(txq->r, items, 1, 1);
+	if (error)
+		m_free(m);
+	else
+		CTR(KTR_CXGBE, "%s: %p sent key WR", __func__, tlsp);
+	return (error);
+}
+
+static u_int
+ktls_base_wr_size(struct tlspcb *tlsp, bool inline_key)
+{
+	u_int wr_len;
+
+	wr_len = sizeof(struct fw_ulptx_wr);	// 16
+	wr_len += sizeof(struct ulp_txpkt);	// 8
+	wr_len += sizeof(struct ulptx_idata);	// 8
+	wr_len += sizeof(struct cpl_tx_sec_pdu);// 32
+	if (inline_key)
+		wr_len += tlsp->tx_key_info_size;
+	else {
+		wr_len += sizeof(struct ulptx_sc_memrd);// 8
+		wr_len += sizeof(struct ulptx_idata);	// 8
+	}
+	/* SplitMode CPL_RX_PHYS_DSGL here if needed. */
+	/* CPL_TX_*_LSO here if needed. */
+	wr_len += sizeof(struct cpl_tx_pkt_core);// 16
+	return (wr_len);
+}
+
+static u_int
+ktls_sgl_size(u_int nsegs)
+{
+	u_int wr_len;
+
+	/* First segment is part of ulptx_sgl. */
+	nsegs--;
+
+	wr_len = sizeof(struct ulptx_sgl);
+	wr_len += 8 * ((3 * nsegs) / 2 + (nsegs & 1));
+	return (wr_len);
+}
+
+/*
+ * A request that doesn't need to generate the TLS trailer is a short
+ * record.  For these requests, part of the TLS record payload is
+ * encrypted without invoking the MAC.
+ *
+ * Returns true if this record should be sent as a short record.  In
+ * either case, the remaining outputs describe the how much of the
+ * TLS record to send as input to the crypto block and the amount of
+ * crypto output to trim via SplitMode:
+ *
+ * *header_len - Number of bytes of TLS header to pass as immediate
+ *               data
+ *
+ * *offset - Start offset of TLS record payload to pass as DSGL data
+ *
+ * *plen - Length of TLS record payload to pass as DSGL data
+ *
+ * *leading_waste - amount of non-packet-header bytes to drop at the
+ *                  start of the crypto output
+ *
+ * *trailing_waste - amount of crypto output to drop from the end
+ */
+static bool
+ktls_is_short_record(struct tlspcb *tlsp, struct mbuf *m_tls, u_int tlen,
+    u_int rlen, u_int *header_len, u_int *offset, u_int *plen,
+    u_int *leading_waste, u_int *trailing_waste, bool send_partial_ghash,
+    bool request_ghash)
+{
+	u_int new_tlen, trailer_len;
+
+	MPASS(tlen > m_tls->m_epg_hdrlen);
+
+	/*
+	 * For TLS 1.3 treat the inner record type stored as the first
+	 * byte of the trailer as part of the payload rather than part
+	 * of the trailer.
+	 */
+	trailer_len = m_tls->m_epg_trllen;
+	if (tlsp->tls13)
+		trailer_len--;
+
+	/*
+	 * Default to sending the full record as input to the crypto
+	 * engine and relying on SplitMode to drop any waste.
+	 */
+	*header_len = m_tls->m_epg_hdrlen;
+	*offset = 0;
+	*plen = rlen - (m_tls->m_epg_hdrlen + trailer_len);
+	*leading_waste = mtod(m_tls, vm_offset_t);
+	*trailing_waste = rlen - tlen;
+	if (!tlsp->sc->tlst.short_records)
+		return (false);
+
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_CBC) {
+		/*
+		 * For AES-CBC we have to send input from the start of
+		 * the TLS record payload that is a multiple of the
+		 * block size.  new_tlen rounds up tlen to the end of
+		 * the containing AES block.  If this last block
+		 * overlaps with the trailer, send the full record to
+		 * generate the MAC.
+		 */
+		new_tlen = TLS_HEADER_LENGTH +
+		    roundup2(tlen - TLS_HEADER_LENGTH, AES_BLOCK_LEN);
+		if (rlen - new_tlen < trailer_len)
+			return (false);
+
+		*trailing_waste = new_tlen - tlen;
+		*plen = new_tlen - m_tls->m_epg_hdrlen;
+	} else {
+		if (rlen - tlen < trailer_len ||
+		    (rlen - tlen == trailer_len && request_ghash)) {
+			/*
+			 * For AES-GCM we have to send the full record
+			 * if the end overlaps with the trailer and a
+			 * partial GHASH isn't being sent.
+			 */
+			if (!send_partial_ghash)
+				return (false);
+
+			/*
+			 * Will need to treat any excess trailer bytes as
+			 * trailing waste.  *trailing_waste is already
+			 * correct.
+			 */
+		} else {
+			/*
+			 * We can use AES-CTR or AES-GCM in partial GHASH
+			 * mode to encrypt a partial PDU.
+			 *
+			 * The last block can be partially encrypted
+			 * without any trailing waste.
+			 */
+			*trailing_waste = 0;
+			*plen = tlen - m_tls->m_epg_hdrlen;
+		}
+
+		/*
+		 * If this request starts at the first byte of the
+		 * payload (so the previous request sent the full TLS
+		 * header as a tunnel packet) and a partial GHASH is
+		 * being requested, the full TLS header must be sent
+		 * as input for the GHASH.
+		 */
+		if (mtod(m_tls, vm_offset_t) == m_tls->m_epg_hdrlen &&
+		    request_ghash)
+			return (true);
+
+		/*
+		 * In addition, we can minimize leading waste by
+		 * starting encryption at the start of the closest AES
+		 * block.
+		 */
+		if (mtod(m_tls, vm_offset_t) >= m_tls->m_epg_hdrlen) {
+			*header_len = 0;
+			*offset = mtod(m_tls, vm_offset_t) -
+			    m_tls->m_epg_hdrlen;
+			if (*offset >= *plen)
+				*offset = *plen;
+			else
+				*offset = rounddown2(*offset, AES_BLOCK_LEN);
+
+			/*
+			 * If the request is just bytes from the trailer,
+			 * trim the offset to the end of the payload.
+			 */
+			*offset = min(*offset, *plen);
+			*plen -= *offset;
+			*leading_waste -= (m_tls->m_epg_hdrlen + *offset);
+		}
+	}
+	return (true);
+}
+
+/* Size of the AES-GCM TLS AAD for a given connection. */
+static int
+ktls_gcm_aad_len(struct tlspcb *tlsp)
+{
+	return (tlsp->tls13 ? sizeof(struct tls_aead_data_13) :
+	    sizeof(struct tls_aead_data));
+}
+
+static int
+ktls_wr_len(struct tlspcb *tlsp, struct mbuf *m, struct mbuf *m_tls,
+    int *nsegsp)
+{
+	const struct tls_record_layer *hdr;
+	u_int header_len, imm_len, offset, plen, rlen, tlen, wr_len;
+	u_int leading_waste, trailing_waste;
+	bool inline_key, last_ghash_frag, request_ghash, send_partial_ghash;
+	bool short_record;
+
+	M_ASSERTEXTPG(m_tls);
+
+	/*
+	 * The relative offset of the last byte to send from the TLS
+	 * record.
+	 */
+	tlen = mtod(m_tls, vm_offset_t) + m_tls->m_len;
+	if (tlen <= m_tls->m_epg_hdrlen) {
+		/*
+		 * For requests that only want to send the TLS header,
+		 * send a tunnelled packet as immediate data.
+		 */
+		wr_len = sizeof(struct fw_eth_tx_pkt_wr) +
+		    sizeof(struct cpl_tx_pkt_core) +
+		    roundup2(m->m_len + m_tls->m_len, 16);
+		if (wr_len > SGE_MAX_WR_LEN) {
+			CTR(KTR_CXGBE,
+		    "%s: %p TLS header-only packet too long (len %d)",
+			    __func__, tlsp, m->m_len + m_tls->m_len);
+		}
+
+		/* This should always be the last TLS record in a chain. */
+		MPASS(m_tls->m_next == NULL);
+		*nsegsp = 0;
+		return (wr_len);
+	}
+
+	hdr = (void *)m_tls->m_epg_hdr;
+	rlen = TLS_HEADER_LENGTH + ntohs(hdr->tls_length);
+
+	/*
+	 * See if this request might make use of GHASH state.  This
+	 * errs on the side of over-budgeting the WR size.
+	 */
+	last_ghash_frag = false;
+	request_ghash = false;
+	send_partial_ghash = false;
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM &&
+	    tlsp->sc->tlst.partial_ghash && tlsp->sc->tlst.short_records) {
+		u_int trailer_len;
+
+		trailer_len = m_tls->m_epg_trllen;
+		if (tlsp->tls13)
+			trailer_len--;
+		KASSERT(trailer_len == AES_GMAC_HASH_LEN,
+		    ("invalid trailer length for AES-GCM"));
+
+		/* Is this the start of a TLS record? */
+		if (mtod(m_tls, vm_offset_t) <= m_tls->m_epg_hdrlen) {
+			/*
+			 * Might use partial GHASH if this doesn't
+			 * send the full record.
+			 */
+			if (tlen < rlen) {
+				if (tlen < (rlen - trailer_len))
+					send_partial_ghash = true;
+				request_ghash = true;
+			}
+		} else {
+			send_partial_ghash = true;
+			if (tlen < rlen)
+				request_ghash = true;
+			if (tlen >= (rlen - trailer_len))
+				last_ghash_frag = true;
+		}
+	}
+
+	/*
+	 * Assume not sending partial GHASH for this call to get the
+	 * larger size.
+	 */
+	short_record = ktls_is_short_record(tlsp, m_tls, tlen, rlen,
+	    &header_len, &offset, &plen, &leading_waste, &trailing_waste,
+	    false, request_ghash);
+
+	inline_key = send_partial_ghash || tlsp->inline_key;
+
+	/* Calculate the size of the work request. */
+	wr_len = ktls_base_wr_size(tlsp, inline_key);
+
+	if (send_partial_ghash)
+		wr_len += AES_GMAC_HASH_LEN;
+
+	if (leading_waste != 0 || trailing_waste != 0) {
+		/*
+		 * Partial records might require a SplitMode
+		 * CPL_RX_PHYS_DSGL.
+		 */
+		wr_len += sizeof(struct cpl_t7_rx_phys_dsgl);
+	}
+
+	/* Budget for an LSO header even if we don't use it. */
+	wr_len += sizeof(struct cpl_tx_pkt_lso_core);
+
+	/*
+	 * Headers (including the TLS header) are always sent as
+	 * immediate data.  Short records include a raw AES IV as
+	 * immediate data.  TLS 1.3 non-short records include a
+	 * placeholder for the sequence number as immediate data.
+	 * Short records using a partial hash may also need to send
+	 * TLS AAD.  If a partial hash might be sent, assume a short
+	 * record to get the larger size.
+	 */
+	imm_len = m->m_len + header_len;
+	if (short_record || send_partial_ghash) {
+		imm_len += AES_BLOCK_LEN;
+		if (send_partial_ghash && header_len != 0)
+			imm_len += ktls_gcm_aad_len(tlsp);
+	} else if (tlsp->tls13)
+		imm_len += sizeof(uint64_t);
+	wr_len += roundup2(imm_len, 16);
+
+	/*
+	 * TLS record payload via DSGL.  For partial GCM mode we
+	 * might need an extra SG entry for a placeholder.
+	 */
+	*nsegsp = sglist_count_mbuf_epg(m_tls, m_tls->m_epg_hdrlen + offset,
+	    plen);
+	wr_len += ktls_sgl_size(*nsegsp + (last_ghash_frag ? 1 : 0));
+
+	if (request_ghash) {
+		/* AES-GCM records might return a partial hash. */
+		wr_len += sizeof(struct ulp_txpkt);
+		wr_len += sizeof(struct ulptx_idata);
+		wr_len += sizeof(struct cpl_tx_tls_ack);
+		wr_len += sizeof(struct rss_header) +
+		    sizeof(struct cpl_fw6_pld);
+		wr_len += AES_GMAC_HASH_LEN;
+	}
+
+	wr_len = roundup2(wr_len, 16);
+	return (wr_len);
+}
+
+/* Queue the next pending packet. */
+static void
+ktls_queue_next_packet(struct tlspcb *tlsp, bool enqueue_only)
+{
+#ifdef KTR
+	struct ether_header *eh;
+	struct tcphdr *tcp;
+	tcp_seq tcp_seqno;
+#endif
+	struct mbuf *m;
+	void *items[1];
+	int rc;
+
+	TXQ_LOCK_ASSERT_OWNED(tlsp->txq);
+	KASSERT(tlsp->queue_mbufs, ("%s: mbufs not being queued for %p",
+	    __func__, tlsp));
+	for (;;) {
+		m = mbufq_dequeue(&tlsp->pending_mbufs);
+		if (m == NULL) {
+			tlsp->queue_mbufs = false;
+			return;
+		}
+
+#ifdef KTR
+		eh = mtod(m, struct ether_header *);
+		tcp = (struct tcphdr *)((char *)eh + m->m_pkthdr.l2hlen +
+		    m->m_pkthdr.l3hlen);
+		tcp_seqno = ntohl(tcp->th_seq);
+#ifdef VERBOSE_TRACES
+		CTR(KTR_CXGBE, "%s: pkt len %d TCP seq %u", __func__,
+		    m->m_pkthdr.len, tcp_seqno);
+#endif
+#endif
+
+		items[0] = m;
+		if (enqueue_only)
+			rc = mp_ring_enqueue_only(tlsp->txq->r, items, 1);
+		else {
+			TXQ_UNLOCK(tlsp->txq);
+			rc = mp_ring_enqueue(tlsp->txq->r, items, 1, 256);
+			TXQ_LOCK(tlsp->txq);
+		}
+		if (__predict_true(rc == 0))
+			return;
+
+		CTR(KTR_CXGBE, "%s: pkt len %d TCP seq %u dropped", __func__,
+		    m->m_pkthdr.len, tcp_seqno);
+		m_freem(m);
+	}
+}
+
+int
+t7_ktls_parse_pkt(struct mbuf *m)
+{
+	struct tlspcb *tlsp;
+	struct ether_header *eh;
+	struct ip *ip;
+	struct ip6_hdr *ip6;
+	struct tcphdr *tcp;
+	struct mbuf *m_tls;
+	void *items[1];
+	int error, nsegs;
+	u_int wr_len, tot_len;
+	uint16_t eh_type;
+
+	/*
+	 * Locate headers in initial mbuf.
+	 *
+	 * XXX: This assumes all of the headers are in the initial mbuf.
+	 * Could perhaps use m_advance() like parse_pkt() if that turns
+	 * out to not be true.
+	 */
+	M_ASSERTPKTHDR(m);
+	MPASS(m->m_pkthdr.snd_tag != NULL);
+	tlsp = mst_to_tls(m->m_pkthdr.snd_tag);
+
+	if (m->m_len <= sizeof(*eh) + sizeof(*ip)) {
+		CTR(KTR_CXGBE, "%s: %p header mbuf too short", __func__, tlsp);
+		return (EINVAL);
+	}
+	eh = mtod(m, struct ether_header *);
+	eh_type = ntohs(eh->ether_type);
+	if (eh_type == ETHERTYPE_VLAN) {
+		struct ether_vlan_header *evh = (void *)eh;
+
+		eh_type = ntohs(evh->evl_proto);
+		m->m_pkthdr.l2hlen = sizeof(*evh);
+	} else
+		m->m_pkthdr.l2hlen = sizeof(*eh);
+
+	switch (eh_type) {
+	case ETHERTYPE_IP:
+		ip = (struct ip *)(eh + 1);
+		if (ip->ip_p != IPPROTO_TCP) {
+			CTR(KTR_CXGBE, "%s: %p mbuf not IPPROTO_TCP", __func__,
+			    tlsp);
+			return (EINVAL);
+		}
+		m->m_pkthdr.l3hlen = ip->ip_hl * 4;
+		break;
+	case ETHERTYPE_IPV6:
+		ip6 = (struct ip6_hdr *)(eh + 1);
+		if (ip6->ip6_nxt != IPPROTO_TCP) {
+			CTR(KTR_CXGBE, "%s: %p, mbuf not IPPROTO_TCP (%u)",
+			    __func__, tlsp, ip6->ip6_nxt);
+			return (EINVAL);
+		}
+		m->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
+		break;
+	default:
+		CTR(KTR_CXGBE, "%s: %p mbuf not ETHERTYPE_IP{,V6}", __func__,
+		    tlsp);
+		return (EINVAL);
+	}
+	if (m->m_len < m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
+	    sizeof(*tcp)) {
+		CTR(KTR_CXGBE, "%s: %p header mbuf too short (2)", __func__,
+		    tlsp);
+		return (EINVAL);
+	}
+	tcp = (struct tcphdr *)((char *)(eh + 1) + m->m_pkthdr.l3hlen);
+	m->m_pkthdr.l4hlen = tcp->th_off * 4;
+
+	/* Bail if there is TCP payload before the TLS record. */
+	if (m->m_len != m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
+	    m->m_pkthdr.l4hlen) {
+		CTR(KTR_CXGBE,
+		    "%s: %p header mbuf bad length (%d + %d + %d != %d)",
+		    __func__, tlsp, m->m_pkthdr.l2hlen, m->m_pkthdr.l3hlen,
+		    m->m_pkthdr.l4hlen, m->m_len);
+		return (EINVAL);
+	}
+
+	/* Assume all headers are in 'm' for now. */
+	MPASS(m->m_next != NULL);
+	MPASS(m->m_next->m_flags & M_EXTPG);
+
+	tot_len = 0;
+
+	/*
+	 * Each of the remaining mbufs in the chain should reference a
+	 * TLS record.
+	 */
+	for (m_tls = m->m_next; m_tls != NULL; m_tls = m_tls->m_next) {
+		MPASS(m_tls->m_flags & M_EXTPG);
+
+		wr_len = ktls_wr_len(tlsp, m, m_tls, &nsegs);
+#ifdef VERBOSE_TRACES
+		CTR(KTR_CXGBE, "%s: %p wr_len %d nsegs %d", __func__, tlsp,
+		    wr_len, nsegs);
+#endif
+		if (wr_len > SGE_MAX_WR_LEN || nsegs > TX_SGL_SEGS)
+			return (EFBIG);
+		tot_len += roundup2(wr_len, EQ_ESIZE);
+
+		/*
+		 * Store 'nsegs' for the first TLS record in the
+		 * header mbuf's metadata.
+		 */
+		if (m_tls == m->m_next)
+			set_mbuf_nsegs(m, nsegs);
+	}
+
+	MPASS(tot_len != 0);
+	set_mbuf_len16(m, tot_len / 16);
+
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM) {
+		/* Defer packets beyond what has been sent so far. */
+		TXQ_LOCK(tlsp->txq);
+		if (tlsp->queue_mbufs) {
+			error = mbufq_enqueue(&tlsp->pending_mbufs, m);
+			if (error == 0) {
+#ifdef VERBOSE_TRACES
+				CTR(KTR_CXGBE,
+				    "%s: %p len16 %d nsegs %d TCP seq %u deferred",
+				    __func__, tlsp, mbuf_len16(m),
+				    mbuf_nsegs(m), ntohl(tcp->th_seq));
+#endif
+			}
+			TXQ_UNLOCK(tlsp->txq);
+			return (error);
+		}
+		tlsp->queue_mbufs = true;
+		TXQ_UNLOCK(tlsp->txq);
+	}
+
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: %p len16 %d nsegs %d", __func__, tlsp,
+	    mbuf_len16(m), mbuf_nsegs(m));
+#endif
+	items[0] = m;
+	error = mp_ring_enqueue(tlsp->txq->r, items, 1, 256);
+	if (__predict_false(error != 0)) {
+		if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM) {
+			TXQ_LOCK(tlsp->txq);
+			ktls_queue_next_packet(tlsp, false);
+			TXQ_UNLOCK(tlsp->txq);
+		}
+	}
+	return (error);
+}
+
+static inline bool
+needs_vlan_insertion(struct mbuf *m)
+{
+
+	M_ASSERTPKTHDR(m);
+
+	return (m->m_flags & M_VLANTAG);
+}
+
+static inline uint64_t
+pkt_ctrl1(struct sge_txq *txq, struct mbuf *m, uint16_t eh_type)
+{
+	uint64_t ctrl1;
+
+	/* Checksums are always offloaded */
+	if (eh_type == ETHERTYPE_IP) {
+		ctrl1 = V_TXPKT_CSUM_TYPE(TX_CSUM_TCPIP) |
+		    V_T6_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN) |
+		    V_TXPKT_IPHDR_LEN(m->m_pkthdr.l3hlen);
+	} else {
+		MPASS(m->m_pkthdr.l3hlen == sizeof(struct ip6_hdr));
+		ctrl1 = V_TXPKT_CSUM_TYPE(TX_CSUM_TCPIP6) |
+		    V_T6_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN) |
+		    V_TXPKT_IPHDR_LEN(m->m_pkthdr.l3hlen);
+	}
+	txq->txcsum++;
+
+	/* VLAN tag insertion */
+	if (needs_vlan_insertion(m)) {
+		ctrl1 |= F_TXPKT_VLAN_VLD |
+		    V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
+		txq->vlan_insertion++;
+	}
+
+	return (ctrl1);
+}
+
+static inline void *
+write_lso_cpl(void *cpl, struct mbuf *m0, uint16_t mss, uint16_t eh_type,
+    int total_len)
+{
+	struct cpl_tx_pkt_lso_core *lso;
+	uint32_t ctrl;
+
+	KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
+	    m0->m_pkthdr.l4hlen > 0,
+	    ("%s: mbuf %p needs TSO but missing header lengths",
+		__func__, m0));
+
+	ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
+	    F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
+	    V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
+	    V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
+	    V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
+	if (eh_type == ETHERTYPE_IPV6)
+		ctrl |= F_LSO_IPV6;
+
+	lso = cpl;
+	lso->lso_ctrl = htobe32(ctrl);
+	lso->ipid_ofst = htobe16(0);
+	lso->mss = htobe16(mss);
+	lso->seqno_offset = htobe32(0);
+	lso->len = htobe32(total_len);
+
+	return (lso + 1);
+}
+
+static inline void *
+write_tx_tls_ack(void *dst, u_int rx_chid, u_int hash_len, bool ghash_lcb)
+{
+	struct cpl_tx_tls_ack *cpl;
+	uint32_t flags;
+
+	flags = ghash_lcb ? F_CPL_TX_TLS_ACK_LCB : F_CPL_TX_TLS_ACK_PHASH;
+	cpl = dst;
+	cpl->op_to_Rsvd2 = htobe32(V_CPL_TX_TLS_ACK_OPCODE(CPL_TX_TLS_ACK) |
+	    V_T7_CPL_TX_TLS_ACK_RXCHID(rx_chid) | F_CPL_TX_TLS_ACK_ULPTXLPBK |
+	    flags);
+
+	/* 32 == AckEncCpl, 16 == LCB */
+	cpl->PldLen = htobe32(V_CPL_TX_TLS_ACK_PLDLEN(32 + 16 + hash_len));
+	cpl->Rsvd3 = 0;
+
+	return (cpl + 1);
+}
+
+static inline void *
+write_fw6_pld(void *dst, u_int rx_chid, u_int rx_qid, u_int hash_len,
+    uint64_t cookie)
+{
+	struct rss_header *rss;
+	struct cpl_fw6_pld *cpl;
+
+	rss = dst;
+	memset(rss, 0, sizeof(*rss));
+	rss->opcode = CPL_FW6_PLD;
+	rss->qid = htobe16(rx_qid);
+	rss->channel = rx_chid;
+
+	cpl = (void *)(rss + 1);
+	memset(cpl, 0, sizeof(*cpl));
+	cpl->opcode = CPL_FW6_PLD;
+	cpl->len = htobe16(hash_len);
+	cpl->data[1] = htobe64(cookie);
+
+	return (cpl + 1);
+}
+
+static inline void *
+write_split_mode_rx_phys(void *dst, struct mbuf *m, struct mbuf *m_tls,
+    u_int crypto_hdr_len, u_int leading_waste, u_int trailing_waste)
+{
+	struct cpl_t7_rx_phys_dsgl *cpl;
+	uint16_t *len;
+	uint8_t numsge;
+
+	/* Forward first (3) and third (1) segments. */
+	numsge = 0xa;
+
+	cpl = dst;
+	cpl->ot.opcode = CPL_RX_PHYS_DSGL;
+	cpl->PhysAddrFields_lo_to_NumSGE =
+	    htobe32(F_CPL_T7_RX_PHYS_DSGL_SPLITMODE |
+	    V_CPL_T7_RX_PHYS_DSGL_NUMSGE(numsge));
+
+	len = (uint16_t *)(cpl->RSSCopy);
+
+	/*
+	 * First segment always contains packet headers as well as
+	 * transmit-related CPLs.
+	 */
+	len[0] = htobe16(crypto_hdr_len);
+
+	/*
+	 * Second segment is "gap" of data to drop at the front of the
+	 * TLS record.
+	 */
+	len[1] = htobe16(leading_waste);
+
+	/* Third segment is how much of the TLS record to send. */
+	len[2] = htobe16(m_tls->m_len);
+
+	/* Fourth segment is how much data to drop at the end. */
+	len[3] = htobe16(trailing_waste);
+
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: forward %u skip %u forward %u skip %u",
+	    __func__, be16toh(len[0]), be16toh(len[1]), be16toh(len[2]),
+	    be16toh(len[3]));
+#endif
+	return (cpl + 1);
+}
+
+/*
+ * If the SGL ends on an address that is not 16 byte aligned, this function will
+ * add a 0 filled flit at the end.
+ */
+static void *
+write_gl_to_buf(struct sglist *gl, caddr_t to)
+{
+	struct sglist_seg *seg;
+	__be64 *flitp;
+	struct ulptx_sgl *usgl;
+	int i, nflits, nsegs;
+
+	KASSERT(((uintptr_t)to & 0xf) == 0,
+	    ("%s: SGL must start at a 16 byte boundary: %p", __func__, to));
+
+	nsegs = gl->sg_nseg;
+	MPASS(nsegs > 0);
+
+	nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
+	flitp = (__be64 *)to;
+	seg = &gl->sg_segs[0];
+	usgl = (void *)flitp;
+
+	usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
+	    V_ULPTX_NSGE(nsegs));
+	usgl->len0 = htobe32(seg->ss_len);
+	usgl->addr0 = htobe64(seg->ss_paddr);
+	seg++;
+
+	for (i = 0; i < nsegs - 1; i++, seg++) {
+		usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
+		usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
+	}
+	if (i & 1)
+		usgl->sge[i / 2].len[1] = htobe32(0);
+	flitp += nflits;
+
+	if (nflits & 1) {
+		MPASS(((uintptr_t)flitp) & 0xf);
+		*flitp++ = 0;
+	}
+
+	MPASS((((uintptr_t)flitp) & 0xf) == 0);
+	return (flitp);
+}
+
+static inline void
+copy_to_txd(struct sge_eq *eq, const char *from, caddr_t *to, int len)
+{
+
+	MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
+	MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
+
+	if (__predict_true((uintptr_t)(*to) + len <=
+	    (uintptr_t)&eq->desc[eq->sidx])) {
+		bcopy(from, *to, len);
+		(*to) += len;
+		if ((uintptr_t)(*to) == (uintptr_t)&eq->desc[eq->sidx])
+			(*to) = (caddr_t)eq->desc;
+	} else {
+		int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
+
+		bcopy(from, *to, portion);
+		from += portion;
+		portion = len - portion;	/* remaining */
+		bcopy(from, (void *)eq->desc, portion);
+		(*to) = (caddr_t)eq->desc + portion;
+	}
+}
+
+static int
+ktls_write_tunnel_packet(struct sge_txq *txq, void *dst, struct mbuf *m,
+    const void *src, u_int len, u_int available, tcp_seq tcp_seqno, u_int pidx,
+    uint16_t eh_type, bool last_wr)
+{
+	struct tx_sdesc *txsd;
+	struct fw_eth_tx_pkt_wr *wr;
+	struct cpl_tx_pkt_core *cpl;
+	uint32_t ctrl;
+	int len16, ndesc, pktlen;
+	struct ether_header *eh;
+	struct ip *ip, newip;
+	struct ip6_hdr *ip6, newip6;
+	struct tcphdr *tcp, newtcp;
+	caddr_t out;
+
+	TXQ_LOCK_ASSERT_OWNED(txq);
+	M_ASSERTPKTHDR(m);
+
+	wr = dst;
+	pktlen = m->m_len + len;
+	ctrl = sizeof(struct cpl_tx_pkt_core) + pktlen;
+	len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) + ctrl, 16);
+	ndesc = tx_len16_to_desc(len16);
+	MPASS(ndesc <= available);
+
+	/* Firmware work request header */
+	/* TODO: Handle VF work request. */
+	wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
+	    V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
+
+	ctrl = V_FW_WR_LEN16(len16);
+	wr->equiq_to_len16 = htobe32(ctrl);
+	wr->r3 = 0;
+
+	cpl = (void *)(wr + 1);
+
+	/* CPL header */
+	cpl->ctrl0 = txq->cpl_ctrl0;
+	cpl->pack = 0;
+	cpl->len = htobe16(pktlen);
+
+	out = (void *)(cpl + 1);
+
+	/* Copy over Ethernet header. */
+	eh = mtod(m, struct ether_header *);
+	copy_to_txd(&txq->eq, (caddr_t)eh, &out, m->m_pkthdr.l2hlen);
+
+	/* Fixup length in IP header and copy out. */
+	if (eh_type == ETHERTYPE_IP) {
+		ip = (void *)((char *)eh + m->m_pkthdr.l2hlen);
+		newip = *ip;
+		newip.ip_len = htons(pktlen - m->m_pkthdr.l2hlen);
+		copy_to_txd(&txq->eq, (caddr_t)&newip, &out, sizeof(newip));
+		if (m->m_pkthdr.l3hlen > sizeof(*ip))
+			copy_to_txd(&txq->eq, (caddr_t)(ip + 1), &out,
+			    m->m_pkthdr.l3hlen - sizeof(*ip));
+	} else {
+		ip6 = (void *)((char *)eh + m->m_pkthdr.l2hlen);
+		newip6 = *ip6;
+		newip6.ip6_plen = htons(pktlen - m->m_pkthdr.l2hlen -
+		    sizeof(*ip6));
+		copy_to_txd(&txq->eq, (caddr_t)&newip6, &out, sizeof(newip6));
+		MPASS(m->m_pkthdr.l3hlen == sizeof(*ip6));
+	}
+	cpl->ctrl1 = htobe64(pkt_ctrl1(txq, m, eh_type));
+
+	/* Set sequence number in TCP header. */
+	tcp = (void *)((char *)eh + m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen);
+	newtcp = *tcp;
+	newtcp.th_seq = htonl(tcp_seqno);
+	copy_to_txd(&txq->eq, (caddr_t)&newtcp, &out, sizeof(newtcp));
+
+	/* Copy rest of TCP header. */
+	copy_to_txd(&txq->eq, (caddr_t)(tcp + 1), &out, m->m_len -
+	    (m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen + sizeof(*tcp)));
+
+	/* Copy the payload data. */
+	copy_to_txd(&txq->eq, src, &out, len);
+	txq->imm_wrs++;
+
+	txq->txpkt_wrs++;
+
+	txsd = &txq->sdesc[pidx];
+	if (last_wr)
+		txsd->m = m;
+	else
+		txsd->m = NULL;
+	txsd->desc_used = ndesc;
+
+	return (ndesc);
+}
+
+static int
+ktls_write_tls_wr(struct tlspcb *tlsp, struct sge_txq *txq,
+    void *dst, struct mbuf *m, struct tcphdr *tcp, struct mbuf *m_tls,
+    u_int available, tcp_seq tcp_seqno, u_int pidx, uint16_t eh_type,
+    uint16_t mss)
+{
+	struct sge_eq *eq = &txq->eq;
+	struct tx_sdesc *txsd;
+	struct fw_ulptx_wr *wr;
+	struct ulp_txpkt *txpkt;
+	struct ulptx_sc_memrd *memrd;
+	struct ulptx_idata *idata;
+	struct cpl_tx_sec_pdu *sec_pdu;
+	struct cpl_tx_pkt_core *tx_pkt;
+	const struct tls_record_layer *hdr;
+	struct ip *ip;
+	struct ip6_hdr *ip6;
+	struct tcphdr *newtcp;
+	char *iv, *out;
+	u_int aad_start, aad_stop;
+	u_int auth_start, auth_stop, auth_insert;
+	u_int cipher_start, cipher_stop, iv_offset;
+	u_int header_len, offset, plen, rlen, tlen;
+	u_int imm_len, ndesc, nsegs, txpkt_lens[2], wr_len;
+	u_int cpl_len, crypto_hdr_len, post_key_context_len;
+	u_int leading_waste, trailing_waste;
+	u_short ip_len;
+	bool inline_key, ghash_lcb, last_ghash_frag, last_wr, need_lso;
+	bool request_ghash, send_partial_ghash, short_record, split_mode;
+	bool using_scratch;
+
+	MPASS(tlsp->txq == txq);
+	M_ASSERTEXTPG(m_tls);
+
+	/* Final work request for this mbuf chain? */
+	last_wr = (m_tls->m_next == NULL);
+
+	/*
+	 * The relative offset of the last byte to send from the TLS
+	 * record.
+	 */
+	tlen = mtod(m_tls, vm_offset_t) + m_tls->m_len;
+	if (tlen <= m_tls->m_epg_hdrlen) {
+		/*
+		 * For requests that only want to send the TLS header,
+		 * send a tunnelled packet as immediate data.
+		 */
+#ifdef VERBOSE_TRACES
+		CTR(KTR_CXGBE, "%s: %p header-only TLS record %u", __func__,
+		    tlsp, (u_int)m_tls->m_epg_seqno);
+#endif
+		/* This should always be the last TLS record in a chain. */
+		MPASS(last_wr);
+
+		txq->kern_tls_header++;
+
+		return (ktls_write_tunnel_packet(txq, dst, m,
+		    (char *)m_tls->m_epg_hdr + mtod(m_tls, vm_offset_t),
+		    m_tls->m_len, available, tcp_seqno, pidx, eh_type,
+		    last_wr));
+	}
+
+	/* Locate the TLS header. */
+	hdr = (void *)m_tls->m_epg_hdr;
+	rlen = TLS_HEADER_LENGTH + ntohs(hdr->tls_length);
+
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: offset %lu len %u TCP seq %u TLS record %u",
+	    __func__, mtod(m_tls, vm_offset_t), m_tls->m_len, tcp_seqno,
+	    (u_int)m_tls->m_epg_seqno);
+#endif
+
+	/* Should this request make use of GHASH state? */
+	ghash_lcb = false;
+	last_ghash_frag = false;
+	request_ghash = false;
+	send_partial_ghash = false;
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM &&
+	    tlsp->sc->tlst.partial_ghash && tlsp->sc->tlst.short_records) {
+		u_int trailer_len;
+
+		trailer_len = m_tls->m_epg_trllen;
+		if (tlsp->tls13)
+			trailer_len--;
+		KASSERT(trailer_len == AES_GMAC_HASH_LEN,
+		    ("invalid trailer length for AES-GCM"));
+
+		/* Is this the start of a TLS record? */
+		if (mtod(m_tls, vm_offset_t) <= m_tls->m_epg_hdrlen) {
+			/*
+			 * If this is the very first TLS record or
+			 * if this is a newer TLS record, request a partial
+			 * hash, but not if we are going to send the whole
+			 * thing.
+			 */
+			if ((tlsp->ghash_tls_seqno == 0 ||
+			    tlsp->ghash_tls_seqno < m_tls->m_epg_seqno) &&
+			    tlen < rlen) {
+				/*
+				 * If we are only missing part or all
+				 * of the trailer, send a normal full
+				 * record but request the hash.
+				 * Otherwise, use partial GHASH mode.
+				 */
+				if (tlen >= (rlen - trailer_len))
+					ghash_lcb = true;
+				else
+					send_partial_ghash = true;
+				request_ghash = true;
+				tlsp->ghash_tls_seqno = m_tls->m_epg_seqno;
+			}
+		} else if (tlsp->ghash_tls_seqno == m_tls->m_epg_seqno &&
+		    tlsp->ghash_valid) {
+			/*
+			 * Compute the offset of the first AES block as
+			 * is done in ktls_is_short_record.
+			 */
+			if (rlen - tlen < trailer_len)
+				plen = rlen - (m_tls->m_epg_hdrlen +
+				    trailer_len);
+			else
+				plen = tlen - m_tls->m_epg_hdrlen;
+			offset = mtod(m_tls, vm_offset_t) - m_tls->m_epg_hdrlen;
+			if (offset >= plen)
+				offset = plen;
+			else
+				offset = rounddown2(offset, AES_BLOCK_LEN);
+			if (tlsp->ghash_offset == offset) {
+				if (offset == plen) {
+					/*
+					 * Send a partial trailer as a
+					 * tunnelled packet as
+					 * immediate data.
+					 */
+#ifdef VERBOSE_TRACES
+					CTR(KTR_CXGBE,
+					    "%s: %p trailer-only TLS record %u",
+					    __func__, tlsp,
+					    (u_int)m_tls->m_epg_seqno);
+#endif
+
+					txq->kern_tls_trailer++;
+
+					offset = mtod(m_tls, vm_offset_t) -
+					    (m_tls->m_epg_hdrlen + plen);
+					KASSERT(offset <= AES_GMAC_HASH_LEN,
+					    ("offset outside of trailer"));
+					return (ktls_write_tunnel_packet(txq,
+					    dst, m, tlsp->ghash + offset,
+					    m_tls->m_len, available, tcp_seqno,
+					    pidx, eh_type, last_wr));
+				}
+
+				/*
+				 * If this request sends the end of
+				 * the payload, it is the last
+				 * fragment.
+				 */
+				if (tlen >= (rlen - trailer_len)) {
+					last_ghash_frag = true;
+					ghash_lcb = true;
+				}
+
+				/*
+				 * Only use partial GCM mode (rather
+				 * than an AES-CTR short record) if
+				 * there is input auth data to pass to
+				 * the GHASH.  That is true so long as
+				 * there is at least one full block of
+				 * payload data, or if the remaining
+				 * payload data is the final partial
+				 * block.
+				 */
+				if (plen - offset >= GMAC_BLOCK_LEN ||
+				    last_ghash_frag) {
+					send_partial_ghash = true;
+
+					/*
+					 * If not sending the complete
+					 * end of the record, this is
+					 * a middle request so needs
+					 * to request an updated
+					 * partial hash.
+					 */
+					if (tlen < rlen)
+						request_ghash = true;
+				}
+			}
+		}
+	}
+
+	short_record = ktls_is_short_record(tlsp, m_tls, tlen, rlen,
+	    &header_len, &offset, &plen, &leading_waste, &trailing_waste,
+	    send_partial_ghash, request_ghash);
+
+	if (short_record) {
+#ifdef VERBOSE_TRACES
+		CTR(KTR_CXGBE,
+		    "%s: %p short TLS record %u hdr %u offs %u plen %u",
+		    __func__, tlsp, (u_int)m_tls->m_epg_seqno, header_len,
+		    offset, plen);
+		if (send_partial_ghash) {
+			if (header_len != 0)
+				CTR(KTR_CXGBE, "%s: %p sending initial GHASH",
+				    __func__, tlsp);
+			else
+				CTR(KTR_CXGBE, "%s: %p sending partial GHASH for offset %u%s",
+				    __func__, tlsp, tlsp->ghash_offset,
+				    last_ghash_frag ? ", last_frag" : "");
+		}
+#endif
+		KASSERT(send_partial_ghash || !request_ghash,
+		    ("requesting but not sending partial hash for short record"));
+	} else {
+		KASSERT(!send_partial_ghash,
+		    ("sending partial hash with full record"));
+	}
+
+	if (tlen < rlen && m_tls->m_next == NULL &&
+	    (tcp->th_flags & TH_FIN) != 0) {
+		txq->kern_tls_fin_short++;
+#ifdef INVARIANTS
+		panic("%s: FIN on short TLS record", __func__);
+#endif
+	}
+
+	/*
+	 * Use cached value for first record in chain if not using
+	 * partial GCM mode. ktls_parse_pkt() calculates nsegs based
+	 * on send_partial_ghash being false.
+	 */
+	if (m->m_next == m_tls && !send_partial_ghash)
+		nsegs = mbuf_nsegs(m);
+	else
+		nsegs = sglist_count_mbuf_epg(m_tls,
+		    m_tls->m_epg_hdrlen + offset, plen);
+
+	/* Determine if we need an LSO header. */
+	need_lso = (m_tls->m_len > mss);
+
+	/* Calculate the size of the TLS work request. */
+	inline_key = send_partial_ghash || tlsp->inline_key;
+	wr_len = ktls_base_wr_size(tlsp, inline_key);
+
+	if (send_partial_ghash) {
+		/* Inline key context includes partial hash in OPAD. */
+		wr_len += AES_GMAC_HASH_LEN;
+	}
+
+	/*
+	 * SplitMode is required if there is any thing we need to trim
+	 * from the crypto output, either at the front or end of the
+	 * record.  Note that short records might not need trimming.
+	 */
+	split_mode = leading_waste != 0 || trailing_waste != 0;
+	if (split_mode) {
+		/*
+		 * Partial records require a SplitMode
+		 * CPL_RX_PHYS_DSGL.
+		 */
+		wr_len += sizeof(struct cpl_t7_rx_phys_dsgl);
+	}
+
+	if (need_lso)
+		wr_len += sizeof(struct cpl_tx_pkt_lso_core);
+
+	imm_len = m->m_len + header_len;
+	if (short_record) {
+		imm_len += AES_BLOCK_LEN;
+		if (send_partial_ghash && header_len != 0)
+			imm_len += ktls_gcm_aad_len(tlsp);
+	} else if (tlsp->tls13)
+		imm_len += sizeof(uint64_t);
+	wr_len += roundup2(imm_len, 16);
+	wr_len += ktls_sgl_size(nsegs + (last_ghash_frag ? 1 : 0));
+	wr_len = roundup2(wr_len, 16);
+	txpkt_lens[0] = wr_len - sizeof(*wr);
+
+	if (request_ghash) {
+		/*
+		 * Requesting the hash entails a second ULP_TX_PKT
+		 * containing CPL_TX_TLS_ACK, CPL_FW6_PLD, and space
+		 * for the hash.
+		 */
+		txpkt_lens[1] = sizeof(struct ulp_txpkt);
+		txpkt_lens[1] += sizeof(struct ulptx_idata);
+		txpkt_lens[1] += sizeof(struct cpl_tx_tls_ack);
+		txpkt_lens[1] += sizeof(struct rss_header) +
+		    sizeof(struct cpl_fw6_pld);
+		txpkt_lens[1] += AES_GMAC_HASH_LEN;
+		wr_len += txpkt_lens[1];
+	} else
+		txpkt_lens[1] = 0;
+
+	ndesc = howmany(wr_len, EQ_ESIZE);
+	MPASS(ndesc <= available);
+
+	/*
+	 * Use the per-txq scratch pad if near the end of the ring to
+	 * simplify handling of wrap-around.
+	 */
+	using_scratch = (eq->sidx - pidx < ndesc);
+	if (using_scratch)
+		wr = (void *)txq->ss;
+	else
+		wr = dst;
+
+	/* FW_ULPTX_WR */
+	wr->op_to_compl = htobe32(V_FW_WR_OP(FW_ULPTX_WR));
+	wr->flowid_len16 = htobe32(F_FW_ULPTX_WR_DATA |
+	    V_FW_WR_LEN16(wr_len / 16));
+	wr->cookie = 0;
+
+	/* ULP_TXPKT */
+	txpkt = (void *)(wr + 1);
+	txpkt->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
+	    V_ULP_TXPKT_DATAMODIFY(0) |
+	    V_T7_ULP_TXPKT_CHANNELID(tlsp->vi->pi->port_id) |
+	    V_ULP_TXPKT_DEST(0) |
+	    V_ULP_TXPKT_CMDMORE(request_ghash ? 1 : 0) |
+	    V_ULP_TXPKT_FID(txq->eq.cntxt_id) | V_ULP_TXPKT_RO(1));
+	txpkt->len = htobe32(howmany(txpkt_lens[0], 16));
+
+	/* ULPTX_IDATA sub-command */
+	idata = (void *)(txpkt + 1);
+	idata->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
+	    V_ULP_TX_SC_MORE(1));
+	idata->len = sizeof(struct cpl_tx_sec_pdu);
+
+	/*
+	 * After the key context comes CPL_RX_PHYS_DSGL, CPL_TX_*, and
+	 * immediate data containing headers.  When using an inline
+	 * key, these are counted as part of this ULPTX_IDATA.  When
+	 * reading the key from memory, these are part of a separate
+	 * ULPTX_IDATA.
+	 */
+	cpl_len = sizeof(struct cpl_tx_pkt_core);
+	if (need_lso)
+		cpl_len += sizeof(struct cpl_tx_pkt_lso_core);
+	if (split_mode)
+		cpl_len += sizeof(struct cpl_t7_rx_phys_dsgl);
+	post_key_context_len = cpl_len + imm_len;
+
+	if (inline_key) {
+		idata->len += tlsp->tx_key_info_size + post_key_context_len;
+		if (send_partial_ghash) {
+			/* Partial GHASH in key context. */
+			idata->len += AES_GMAC_HASH_LEN;
+		}
+	}
+	idata->len = htobe32(idata->len);
+
+	/* CPL_TX_SEC_PDU */
+	sec_pdu = (void *)(idata + 1);
+
+	/*
+	 * Packet headers are passed through unchanged by the crypto
+	 * engine by marking them as header data in SCMD0.
+	 */
+	crypto_hdr_len = m->m_len;
+
+	if (send_partial_ghash) {
+		/*
+		 * For short records using a partial hash, the TLS
+		 * header is counted as header data in SCMD0.  TLS AAD
+		 * is next (if AAD is present) followed by the AES-CTR
+		 * IV.  Last is the cipher region for the payload.
+		 */
+		if (header_len != 0) {
+			aad_start = 1;
+			aad_stop = ktls_gcm_aad_len(tlsp);
+		} else {
+			aad_start = 0;
+			aad_stop = 0;
+		}
+		iv_offset = aad_stop + 1;
+		cipher_start = iv_offset + AES_BLOCK_LEN;
+		cipher_stop = 0;
+		if (last_ghash_frag) {
+			auth_start = cipher_start;
+			auth_stop = AES_GMAC_HASH_LEN;
+			auth_insert = auth_stop;
+		} else if (plen < GMAC_BLOCK_LEN) {
+			/*
+			 * A request that sends part of the first AES
+			 * block will only have AAD.
+			 */
+			KASSERT(header_len != 0,
+			    ("%s: partial GHASH with no auth", __func__));
+			auth_start = 0;
+			auth_stop = 0;
+			auth_insert = 0;
+		} else {
+			auth_start = cipher_start;
+			auth_stop = plen % GMAC_BLOCK_LEN;
+			auth_insert = 0;
+		}
+
+		sec_pdu->pldlen = htobe32(aad_stop + AES_BLOCK_LEN + plen +
+		    (last_ghash_frag ? AES_GMAC_HASH_LEN : 0));
+
+		/*
+		 * For short records, the TLS header is treated as
+		 * header data.
+		 */
+		crypto_hdr_len += header_len;
+
+		/* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
+		sec_pdu->seqno_numivs = tlsp->scmd0_partial.seqno_numivs;
+		sec_pdu->ivgen_hdrlen = tlsp->scmd0_partial.ivgen_hdrlen;
+		if (last_ghash_frag)
+			sec_pdu->ivgen_hdrlen |= V_SCMD_LAST_FRAG(1);
+		else
+			sec_pdu->ivgen_hdrlen |= V_SCMD_MORE_FRAGS(1);
+		sec_pdu->ivgen_hdrlen = htobe32(sec_pdu->ivgen_hdrlen |
+		    V_SCMD_HDR_LEN(crypto_hdr_len));
+
+		txq->kern_tls_partial_ghash++;
+	} else if (short_record) {
+		/*
+		 * For short records without a partial hash, the TLS
+		 * header is counted as header data in SCMD0 and the
+		 * IV is next, followed by a cipher region for the
+		 * payload.
+		 */
+		aad_start = 0;
+		aad_stop = 0;
+		iv_offset = 1;
+		auth_start = 0;
+		auth_stop = 0;
+		auth_insert = 0;
+		cipher_start = AES_BLOCK_LEN + 1;
+		cipher_stop = 0;
+
+		sec_pdu->pldlen = htobe32(AES_BLOCK_LEN + plen);
+
+		/*
+		 * For short records, the TLS header is treated as
+		 * header data.
+		 */
+		crypto_hdr_len += header_len;
+
+		/* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
+		sec_pdu->seqno_numivs = tlsp->scmd0_short.seqno_numivs;
+		sec_pdu->ivgen_hdrlen = htobe32(
+		    tlsp->scmd0_short.ivgen_hdrlen |
+		    V_SCMD_HDR_LEN(crypto_hdr_len));
+
+		txq->kern_tls_short++;
+	} else {
+		/*
+		 * AAD is TLS header.  IV is after AAD for TLS < 1.3.
+		 * For TLS 1.3, a placeholder for the TLS sequence
+		 * number is provided as an IV before the AAD.  The
+		 * cipher region starts after the AAD and IV.  See
+		 * comments in ccr_authenc() and ccr_gmac() in
+		 * t4_crypto.c regarding cipher and auth start/stop
+		 * values.
+		 */
+		if (tlsp->tls13) {
+			iv_offset = 1;
+			aad_start = 1 + sizeof(uint64_t);
+			aad_stop = sizeof(uint64_t) + TLS_HEADER_LENGTH;
+			cipher_start = aad_stop + 1;
+		} else {
+			aad_start = 1;
+			aad_stop = TLS_HEADER_LENGTH;
+			iv_offset = TLS_HEADER_LENGTH + 1;
+			cipher_start = m_tls->m_epg_hdrlen + 1;
+		}
+		if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM) {
+			cipher_stop = 0;
+			auth_start = cipher_start;
+			auth_stop = 0;
+			auth_insert = 0;
+		} else {
+			cipher_stop = 0;
+			auth_start = cipher_start;
+			auth_stop = 0;
+			auth_insert = 0;
+		}
+
+		sec_pdu->pldlen = htobe32((tlsp->tls13 ? sizeof(uint64_t) : 0) +
+		    m_tls->m_epg_hdrlen + plen);
+
+		/* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
+		sec_pdu->seqno_numivs = tlsp->scmd0.seqno_numivs;
+		sec_pdu->ivgen_hdrlen = htobe32(tlsp->scmd0.ivgen_hdrlen |
+		    V_SCMD_HDR_LEN(crypto_hdr_len));
+
+		if (split_mode)
+			txq->kern_tls_partial++;
+		else
+			txq->kern_tls_full++;
+	}
+	sec_pdu->op_ivinsrtofst = htobe32(
+	    V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
+	    V_CPL_TX_SEC_PDU_CPLLEN(cpl_len / 8) |
+	    V_CPL_TX_SEC_PDU_PLACEHOLDER(send_partial_ghash ? 1 : 0) |
+	    V_CPL_TX_SEC_PDU_IVINSRTOFST(iv_offset));
+	sec_pdu->aadstart_cipherstop_hi = htobe32(
+	    V_CPL_TX_SEC_PDU_AADSTART(aad_start) |
+	    V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) |
+	    V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) |
+	    V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(cipher_stop >> 4));
+	sec_pdu->cipherstop_lo_authinsert = htobe32(
+	    V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(cipher_stop & 0xf) |
+	    V_CPL_TX_SEC_PDU_AUTHSTART(auth_start) |
+	    V_CPL_TX_SEC_PDU_AUTHSTOP(auth_stop) |
+	    V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert));
+
+	if (send_partial_ghash && last_ghash_frag) {
+		uint64_t aad_len, cipher_len;
+
+		aad_len = ktls_gcm_aad_len(tlsp);
+		cipher_len = rlen - (m_tls->m_epg_hdrlen + AES_GMAC_HASH_LEN);
+		sec_pdu->scmd1 = htobe64(aad_len << 44 | cipher_len);
+	} else
+		sec_pdu->scmd1 = htobe64(m_tls->m_epg_seqno);
+
+	/* Key context */
+	out = (void *)(sec_pdu + 1);
+	if (inline_key) {
+		memcpy(out, &tlsp->keyctx, tlsp->tx_key_info_size);
+		if (send_partial_ghash) {
+			struct tls_keyctx *keyctx = (void *)out;
+
+			keyctx->u.txhdr.ctxlen++;
+			keyctx->u.txhdr.dualck_to_txvalid &= ~htobe16(
+			    V_KEY_CONTEXT_MK_SIZE(M_KEY_CONTEXT_MK_SIZE));
+			keyctx->u.txhdr.dualck_to_txvalid |= htobe16(
+			    F_KEY_CONTEXT_OPAD_PRESENT |
+			    V_KEY_CONTEXT_MK_SIZE(0));
+		}
+		out += tlsp->tx_key_info_size;
+		if (send_partial_ghash) {
+			if (header_len != 0)
+				memset(out, 0, AES_GMAC_HASH_LEN);
+			else
+				memcpy(out, tlsp->ghash, AES_GMAC_HASH_LEN);
+			out += AES_GMAC_HASH_LEN;
+		}
+	} else {
+		/* ULPTX_SC_MEMRD to read key context. */
+		memrd = (void *)out;
+		memrd->cmd_to_len = htobe32(V_ULPTX_CMD(ULP_TX_SC_MEMRD) |
+		    V_ULP_TX_SC_MORE(1) |
+		    V_ULPTX_LEN16(tlsp->tx_key_info_size >> 4));
+		memrd->addr = htobe32(tlsp->tx_key_addr >> 5);
+
+		/* ULPTX_IDATA for CPL_TX_* and headers. */
+		idata = (void *)(memrd + 1);
+		idata->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
+		    V_ULP_TX_SC_MORE(1));
+		idata->len = htobe32(post_key_context_len);
+
+		out = (void *)(idata + 1);
+	}
+
+	/* CPL_RX_PHYS_DSGL */
+	if (split_mode) {
+		crypto_hdr_len = sizeof(struct cpl_tx_pkt_core);
+		if (need_lso)
+			crypto_hdr_len += sizeof(struct cpl_tx_pkt_lso_core);
+		crypto_hdr_len += m->m_len;
+		out = write_split_mode_rx_phys(out, m, m_tls, crypto_hdr_len,
+		    leading_waste, trailing_waste);
+	}
+
+	/* CPL_TX_PKT_LSO */
+	if (need_lso) {
+		out = write_lso_cpl(out, m, mss, eh_type, m->m_len +
+		    m_tls->m_len);
+		txq->tso_wrs++;
+	}
+
+	/* CPL_TX_PKT_XT */
+	tx_pkt = (void *)out;
+	tx_pkt->ctrl0 = txq->cpl_ctrl0;
+	tx_pkt->ctrl1 = htobe64(pkt_ctrl1(txq, m, eh_type));
+	tx_pkt->pack = 0;
+	tx_pkt->len = htobe16(m->m_len + m_tls->m_len);
+
+	/* Copy the packet headers. */
+	out = (void *)(tx_pkt + 1);
+	memcpy(out, mtod(m, char *), m->m_len);
+
+	/* Modify the packet length in the IP header. */
+	ip_len = m->m_len + m_tls->m_len - m->m_pkthdr.l2hlen;
+	if (eh_type == ETHERTYPE_IP) {
+		ip = (void *)(out + m->m_pkthdr.l2hlen);
+		be16enc(&ip->ip_len, ip_len);
+	} else {
+		ip6 = (void *)(out + m->m_pkthdr.l2hlen);
+		be16enc(&ip6->ip6_plen, ip_len - sizeof(*ip6));
+	}
+
+	/* Modify sequence number and flags in TCP header. */
+	newtcp = (void *)(out + m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen);
+	be32enc(&newtcp->th_seq, tcp_seqno);
+	if (!last_wr)
+		newtcp->th_flags = tcp->th_flags & ~(TH_PUSH | TH_FIN);
+	out += m->m_len;
+
+	/*
+	 * Insert placeholder for sequence number as IV for TLS 1.3
+	 * non-short records.
+	 */
+	if (tlsp->tls13 && !short_record) {
+		memset(out, 0, sizeof(uint64_t));
+		out += sizeof(uint64_t);
+	}
+
+	/* Populate the TLS header */
+	memcpy(out, m_tls->m_epg_hdr, header_len);
+	out += header_len;
+
+	/* TLS AAD for short records using a partial hash. */
+	if (send_partial_ghash && header_len != 0) {
+		if (tlsp->tls13) {
+			struct tls_aead_data_13 ad;
+
+			ad.type = hdr->tls_type;
+			ad.tls_vmajor = hdr->tls_vmajor;
+			ad.tls_vminor = hdr->tls_vminor;
+			ad.tls_length = hdr->tls_length;
+			memcpy(out, &ad, sizeof(ad));
+			out += sizeof(ad);
+		} else {
+			struct tls_aead_data ad;
+			uint16_t cipher_len;
+
+			cipher_len = rlen -
+			    (m_tls->m_epg_hdrlen + AES_GMAC_HASH_LEN);
+			ad.seq = htobe64(m_tls->m_epg_seqno);
+			ad.type = hdr->tls_type;
+			ad.tls_vmajor = hdr->tls_vmajor;
+			ad.tls_vminor = hdr->tls_vminor;
+			ad.tls_length = htons(cipher_len);
+			memcpy(out, &ad, sizeof(ad));
+			out += sizeof(ad);
+		}
+	}
+
+	/* AES IV for a short record. */
+	if (short_record) {
+		iv = out;
+		if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM) {
+			memcpy(iv, tlsp->keyctx.u.txhdr.txsalt, SALT_SIZE);
+			if (tlsp->tls13) {
+				uint64_t value;
+
+				value = be64dec(tlsp->keyctx.u.txhdr.txsalt +
+				    4);
+				value ^= m_tls->m_epg_seqno;
+				be64enc(iv + 4, value);
+			} else
+				memcpy(iv + 4, hdr + 1, 8);
+			if (send_partial_ghash)
+				be32enc(iv + 12, 1 + offset / AES_BLOCK_LEN);
+			else
+				be32enc(iv + 12, 2 + offset / AES_BLOCK_LEN);
+		} else
+			memcpy(iv, hdr + 1, AES_BLOCK_LEN);
+		out += AES_BLOCK_LEN;
+	}
+
+	if (imm_len % 16 != 0) {
+		if (imm_len % 8 != 0) {
+			/* Zero pad to an 8-byte boundary. */
+			memset(out, 0, 8 - (imm_len % 8));
+			out += 8 - (imm_len % 8);
+		}
+
+		/*
+		 * Insert a ULP_TX_SC_NOOP if needed so the SGL is
+		 * 16-byte aligned.
+		 */
+		if (imm_len % 16 <= 8) {
+			idata = (void *)out;
+			idata->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_NOOP) |
+			    V_ULP_TX_SC_MORE(1));
+			idata->len = htobe32(0);
+			out = (void *)(idata + 1);
+		}
+	}
+
+	/* SGL for record payload */
+	sglist_reset(txq->gl);
+	if (sglist_append_mbuf_epg(txq->gl, m_tls, m_tls->m_epg_hdrlen + offset,
+	    plen) != 0) {
+#ifdef INVARIANTS
+		panic("%s: failed to append sglist", __func__);
+#endif
+	}
+	if (last_ghash_frag) {
+		if (sglist_append_phys(txq->gl, zero_buffer_pa,
+		    AES_GMAC_HASH_LEN) != 0) {
+#ifdef INVARIANTS
+			panic("%s: failed to append sglist (2)", __func__);
+#endif
+		}
+	}
+	out = write_gl_to_buf(txq->gl, out);
+
+	if (request_ghash) {
+		/* ULP_TXPKT */
+		txpkt = (void *)out;
+		txpkt->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
+		    V_ULP_TXPKT_DATAMODIFY(0) |
+		    V_T7_ULP_TXPKT_CHANNELID(tlsp->vi->pi->port_id) |
+		    V_ULP_TXPKT_DEST(0) |
+		    V_ULP_TXPKT_FID(txq->eq.cntxt_id) | V_ULP_TXPKT_RO(1));
+		txpkt->len = htobe32(howmany(txpkt_lens[1], 16));
+
+		/* ULPTX_IDATA sub-command */
+		idata = (void *)(txpkt + 1);
+		idata->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
+		    V_ULP_TX_SC_MORE(0));
+		idata->len = sizeof(struct cpl_tx_tls_ack);
+		idata->len += sizeof(struct rss_header) +
+		    sizeof(struct cpl_fw6_pld);
+		idata->len += AES_GMAC_HASH_LEN;
+		idata->len = htobe32(idata->len);
+		out = (void *)(idata + 1);
+
+		/* CPL_TX_TLS_ACK */
+		out = write_tx_tls_ack(out, tlsp->rx_chid, AES_GMAC_HASH_LEN,
+		    ghash_lcb);
+
+		/* CPL_FW6_PLD */
+		out = write_fw6_pld(out, tlsp->rx_chid, tlsp->rx_qid,
+		    AES_GMAC_HASH_LEN, (uintptr_t)tlsp | CPL_FW6_COOKIE_KTLS);
+
+		/* Space for partial hash. */
+		memset(out, 0, AES_GMAC_HASH_LEN);
+		out += AES_GMAC_HASH_LEN;
+
+		tlsp->ghash_pending = true;
+		tlsp->ghash_valid = false;
+		tlsp->ghash_lcb = ghash_lcb;
+		if (last_ghash_frag)
+			tlsp->ghash_offset = offset + plen;
+		else
+			tlsp->ghash_offset = rounddown2(offset + plen,
+			    GMAC_BLOCK_LEN);
+#ifdef VERBOSE_TRACES
+		CTR(KTR_CXGBE, "%s: %p requesting GHASH for offset %u",
+		    __func__, tlsp, tlsp->ghash_offset);
+#endif
+		m_snd_tag_ref(&tlsp->com);
+
+		txq->kern_tls_ghash_requested++;
+	}
+
+	if (using_scratch) {
+		out = dst;
+		copy_to_txd(eq, txq->ss, &out, wr_len);
+	}
+
+	txq->kern_tls_records++;
+	txq->kern_tls_octets += m_tls->m_len;
+	if (split_mode) {
+		txq->kern_tls_splitmode++;
+		txq->kern_tls_waste += leading_waste + trailing_waste;
+	}
+	if (need_lso)
+		txq->kern_tls_lso++;
+
+	txsd = &txq->sdesc[pidx];
+	if (last_wr)
+		txsd->m = m;
+	else
+		txsd->m = NULL;
+	txsd->desc_used = ndesc;
+
+	return (ndesc);
+}
+
+int
+t7_ktls_write_wr(struct sge_txq *txq, void *dst, struct mbuf *m,
+    u_int available)
+{
+	struct sge_eq *eq = &txq->eq;
+	struct tlspcb *tlsp;
+	struct tcphdr *tcp;
+	struct mbuf *m_tls;
+	struct ether_header *eh;
+	tcp_seq tcp_seqno;
+	u_int ndesc, pidx, totdesc;
+	uint16_t eh_type, mss;
+
+	TXQ_LOCK_ASSERT_OWNED(txq);
+	M_ASSERTPKTHDR(m);
+	MPASS(m->m_pkthdr.snd_tag != NULL);
+	tlsp = mst_to_tls(m->m_pkthdr.snd_tag);
+
+	totdesc = 0;
+	eh = mtod(m, struct ether_header *);
+	eh_type = ntohs(eh->ether_type);
+	if (eh_type == ETHERTYPE_VLAN) {
+		struct ether_vlan_header *evh = (void *)eh;
+
+		eh_type = ntohs(evh->evl_proto);
+	}
+
+	tcp = (struct tcphdr *)((char *)eh + m->m_pkthdr.l2hlen +
+	    m->m_pkthdr.l3hlen);
+	pidx = eq->pidx;
+
+	/* Determine MSS. */
+	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
+		mss = m->m_pkthdr.tso_segsz;
+		tlsp->prev_mss = mss;
+	} else if (tlsp->prev_mss != 0)
+		mss = tlsp->prev_mss;
+	else
+		mss = if_getmtu(tlsp->vi->ifp) -
+		    (m->m_pkthdr.l3hlen + m->m_pkthdr.l4hlen);
+
+	/* Fetch the starting TCP sequence number for this chain. */
+	tcp_seqno = ntohl(tcp->th_seq);
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: pkt len %d TCP seq %u", __func__, m->m_pkthdr.len,
+	    tcp_seqno);
+#endif
+	KASSERT(!tlsp->ghash_pending, ("%s: GHASH pending for send", __func__));
+
+	/*
+	 * Iterate over each TLS record constructing a work request
+	 * for that record.
+	 */
+	for (m_tls = m->m_next; m_tls != NULL; m_tls = m_tls->m_next) {
+		MPASS(m_tls->m_flags & M_EXTPG);
+
+		ndesc = ktls_write_tls_wr(tlsp, txq, dst, m, tcp, m_tls,
+		    available - totdesc, tcp_seqno, pidx, eh_type, mss);
+		totdesc += ndesc;
+		IDXINCR(pidx, ndesc, eq->sidx);
+		dst = &eq->desc[pidx];
+
+		tcp_seqno += m_tls->m_len;
+	}
+
+	/*
+	 * Queue another packet if this was a GCM request that didn't
+	 * request a GHASH response.
+	 */
+	if (tlsp->enc_mode == SCMD_CIPH_MODE_AES_GCM && !tlsp->ghash_pending)
+		ktls_queue_next_packet(tlsp, true);
+
+	MPASS(totdesc <= available);
+	return (totdesc);
+}
+
+static void
+t7_tls_tag_free(struct m_snd_tag *mst)
+{
+	struct adapter *sc;
+	struct tlspcb *tlsp;
+
+	tlsp = mst_to_tls(mst);
+	sc = tlsp->sc;
+
+	CTR2(KTR_CXGBE, "%s: %p", __func__, tlsp);
+
+	if (tlsp->tx_key_addr >= 0)
+		t4_free_tls_keyid(sc, tlsp->tx_key_addr);
+
+	KASSERT(mbufq_len(&tlsp->pending_mbufs) == 0,
+	    ("%s: pending mbufs", __func__));
+
+	zfree(tlsp, M_CXGBE);
+}
+
+static int
+ktls_fw6_pld(struct sge_iq *iq, const struct rss_header *rss,
+    struct mbuf *m)
+{
+	const struct cpl_fw6_pld *cpl;
+	struct tlspcb *tlsp;
+	const void *ghash;
+
+	if (m != NULL)
+		cpl = mtod(m, const void *);
+	else
+		cpl = (const void *)(rss + 1);
+
+	tlsp = (struct tlspcb *)(uintptr_t)CPL_FW6_PLD_COOKIE(cpl);
+	KASSERT(cpl->data[0] == 0, ("%s: error status returned", __func__));
+
+	TXQ_LOCK(tlsp->txq);
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: %p received GHASH for offset %u%s", __func__, tlsp,
+	    tlsp->ghash_offset, tlsp->ghash_lcb ? " in LCB" : "");
+#endif
+	if (tlsp->ghash_lcb)
+		ghash = &cpl->data[2];
+	else
+		ghash = cpl + 1;
+	memcpy(tlsp->ghash, ghash, AES_GMAC_HASH_LEN);
+	tlsp->ghash_valid = true;
+	tlsp->ghash_pending = false;
+	tlsp->txq->kern_tls_ghash_received++;
+
+	ktls_queue_next_packet(tlsp, false);
+	TXQ_UNLOCK(tlsp->txq);
+
+	m_snd_tag_rele(&tlsp->com);
+	m_freem(m);
+	return (0);
+}
+
+void
+t7_ktls_modload(void)
+{
+	zero_buffer = malloc_aligned(AES_GMAC_HASH_LEN, AES_GMAC_HASH_LEN,
+	    M_CXGBE, M_ZERO | M_WAITOK);
+	zero_buffer_pa = vtophys(zero_buffer);
+	t4_register_shared_cpl_handler(CPL_FW6_PLD, ktls_fw6_pld,
+	    CPL_FW6_COOKIE_KTLS);
+}
+
+void
+t7_ktls_modunload(void)
+{
+	free(zero_buffer, M_CXGBE);
+	t4_register_shared_cpl_handler(CPL_FW6_PLD, NULL, CPL_FW6_COOKIE_KTLS);
+}
+
+#else
+
+int
+t7_tls_tag_alloc(struct ifnet *ifp, union if_snd_tag_alloc_params *params,
+    struct m_snd_tag **pt)
+{
+	return (ENXIO);
+}
+
+int
+t7_ktls_parse_pkt(struct mbuf *m)
+{
+	return (EINVAL);
+}
+
+int
+t7_ktls_write_wr(struct sge_txq *txq, void *dst, struct mbuf *m,
+    u_int available)
+{
+	panic("can't happen");
+}
+
+void
+t7_ktls_modload(void)
+{
+}
+
+void
+t7_ktls_modunload(void)
+{
+}
+
+#endif
diff --git a/sys/dev/cxgbe/cudbg/cudbg_flash_utils.c b/sys/dev/cxgbe/cudbg/cudbg_flash_utils.c
index b8e6eeba0280..2cd24c635325 100644
--- a/sys/dev/cxgbe/cudbg/cudbg_flash_utils.c
+++ b/sys/dev/cxgbe/cudbg/cudbg_flash_utils.c
@@ -32,19 +32,6 @@
 #include "cudbg.h"
 #include "cudbg_lib_common.h"
 
-enum {
-	SF_ATTEMPTS = 10,		/* max retries for SF operations */
-
-	/* flash command opcodes */
-	SF_PROG_PAGE	= 2,	/* program page */
-	SF_WR_DISABLE	= 4,	/* disable writes */
-	SF_RD_STATUS	= 5,	/* read status register */
-	SF_WR_ENABLE	= 6,	/* enable writes */
-	SF_RD_DATA_FAST = 0xb,	/* read flash */
-	SF_RD_ID	= 0x9f, /* read ID */
-	SF_ERASE_SECTOR = 0xd8, /* erase sector */
-};
-
 int write_flash(struct adapter *adap, u32 start_sec, void *data, u32 size);
 int read_flash(struct adapter *adap, u32 start_sec , void *data, u32 size,
 		u32 start_address);
@@ -56,10 +43,12 @@ update_skip_size(struct cudbg_flash_sec_info *sec_info, u32 size)
 }
 
 static
-void set_sector_availability(struct cudbg_flash_sec_info *sec_info,
-    int sector_nu, int avail)
+void set_sector_availability(struct adapter *adap,
+    struct cudbg_flash_sec_info *sec_info, int sector_nu, int avail)
 {
-	sector_nu -= CUDBG_START_SEC;
+	int start = t4_flash_loc_start(adap, FLASH_LOC_CUDBG, NULL);
+
+	sector_nu -= start / SF_SEC_SIZE;;
 	if (avail)
 		set_dbg_bitmap(sec_info->sec_bitmap, sector_nu);
 	else
@@ -68,13 +57,17 @@ void set_sector_availability(struct cudbg_flash_sec_info *sec_info,
 
 /* This function will return empty sector available for filling */
 static int
-find_empty_sec(struct cudbg_flash_sec_info *sec_info)
+find_empty_sec(struct adapter *adap, struct cudbg_flash_sec_info *sec_info)
 {
 	int i, index, bit;
-
-	for (i = CUDBG_START_SEC; i < CUDBG_SF_MAX_SECTOR; i++) {
-		index = (i - CUDBG_START_SEC) / 8;
-		bit = (i - CUDBG_START_SEC) % 8;
+	unsigned int len = 0;
+	int start = t4_flash_loc_start(adap, FLASH_LOC_CUDBG, &len);
+
+	start /= SF_SEC_SIZE;	/* addr -> sector */
+	len /= SF_SEC_SIZE;
+	for (i = start; i < start + len; i++) {
+		index = (i - start) / 8;
+		bit = (i - start) % 8;
 		if (!(sec_info->sec_bitmap[index] & (1 << bit)))
 			return i;
 	}
@@ -102,7 +95,7 @@ static void update_headers(void *handle, struct cudbg_buffer *dbg_buff,
 	data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
 				sizeof(struct cudbg_hdr);
 	total_hdr_size = data_hdr_size + sizeof(struct cudbg_flash_hdr);
-	sec_hdr_start_addr = CUDBG_SF_SECTOR_SIZE - total_hdr_size;
+	sec_hdr_start_addr = SF_SEC_SIZE - total_hdr_size;
 	sec_hdr  = sec_info->sec_data + sec_hdr_start_addr;
 
 	flash_hdr = (struct cudbg_flash_hdr *)(sec_hdr);
@@ -166,11 +159,13 @@ int cudbg_write_flash(void *handle, u64 timestamp, void *data,
 	u32 space_left;
 	int rc = 0;
 	int sec;
+	unsigned int cudbg_max_size = 0;
 
+	t4_flash_loc_start(adap, FLASH_LOC_CUDBG, &cudbg_max_size);
 	data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
 			sizeof(struct cudbg_hdr);
 	total_hdr_size = data_hdr_size + sizeof(struct cudbg_flash_hdr);
-	sec_hdr_start_addr = CUDBG_SF_SECTOR_SIZE - total_hdr_size;
+	sec_hdr_start_addr = SF_SEC_SIZE - total_hdr_size;
 	sec_data_size = sec_hdr_start_addr;
 
 	cudbg_init->print("\tWriting %u bytes to flash\n", cur_entity_size);
@@ -191,12 +186,12 @@ int cudbg_write_flash(void *handle, u64 timestamp, void *data,
 	flash_hdr = (struct cudbg_flash_hdr *)(sec_info->sec_data +
 			sec_hdr_start_addr);
 
-	if (flash_hdr->data_len > CUDBG_FLASH_SIZE) {
+	if (flash_hdr->data_len > cudbg_max_size) {
 		rc = CUDBG_STATUS_FLASH_FULL;
 		goto out;
 	}
 
-	space_left = CUDBG_FLASH_SIZE - flash_hdr->data_len;
+	space_left = cudbg_max_size - flash_hdr->data_len;
 
 	if (cur_entity_size > space_left) {
 		rc = CUDBG_STATUS_FLASH_FULL;
@@ -204,10 +199,11 @@ int cudbg_write_flash(void *handle, u64 timestamp, void *data,
 	}
 
 	while (cur_entity_size > 0) {
-		sec = find_empty_sec(sec_info);
+		sec = find_empty_sec(adap, sec_info);
 		if (sec_info->par_sec) {
 			sec_data_offset = sec_info->par_sec_offset;
-			set_sector_availability(sec_info, sec_info->par_sec, 0);
+			set_sector_availability(adap, sec_info,
+			    sec_info->par_sec, 0);
 			sec_info->par_sec = 0;
 			sec_info->par_sec_offset = 0;
 
@@ -230,13 +226,12 @@ int cudbg_write_flash(void *handle, u64 timestamp, void *data,
 		       (void *)((char *)dbg_buff->data + start_offset),
 		       tmp_size);
 
-		rc = write_flash(adap, sec, sec_info->sec_data,
-				CUDBG_SF_SECTOR_SIZE);
+		rc = write_flash(adap, sec, sec_info->sec_data, SF_SEC_SIZE);
 		if (rc)
 			goto out;
 
 		cur_entity_size -= tmp_size;
-		set_sector_availability(sec_info, sec, 1);
+		set_sector_availability(adap, sec_info, sec, 1);
 		start_offset += tmp_size;
 	}
 out:
@@ -247,19 +242,14 @@ int write_flash(struct adapter *adap, u32 start_sec, void *data, u32 size)
 {
 	unsigned int addr;
 	unsigned int i, n;
-	unsigned int sf_sec_size;
 	int rc = 0;
 
 	u8 *ptr = (u8 *)data;
 
-	sf_sec_size = adap->params.sf_size/adap->params.sf_nsec;
-
-	addr =  start_sec * CUDBG_SF_SECTOR_SIZE;
-	i = DIV_ROUND_UP(size,/* # of sectors spanned */
-			sf_sec_size);
+	addr =  start_sec * SF_SEC_SIZE;
+	i = DIV_ROUND_UP(size, SF_SEC_SIZE);
 
-	rc = t4_flash_erase_sectors(adap, start_sec,
-		   start_sec + i - 1);
+	rc = t4_flash_erase_sectors(adap, start_sec, start_sec + i - 1);
 	/*
 	 * If size == 0 then we're simply erasing the FLASH sectors associated
 	 * with the on-adapter OptionROM Configuration File.
@@ -337,6 +327,9 @@ int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
 	u32 data_offset = 0;
 	u32 i, j;
 	int rc;
+	unsigned int cudbg_len = 0;
+	int cudbg_start_sec = t4_flash_loc_start(adap, FLASH_LOC_CUDBG,
+	    &cudbg_len) / SF_SEC_SIZE;
 
 	rc = t4_get_flash_params(adap);
 	if (rc) {
@@ -348,7 +341,7 @@ int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
 	data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
 			sizeof(struct cudbg_hdr);
 	total_hdr_size = data_hdr_size + sizeof(struct cudbg_flash_hdr);
-	sec_hdr_start_addr = CUDBG_SF_SECTOR_SIZE - total_hdr_size;
+	sec_hdr_start_addr = SF_SEC_SIZE - total_hdr_size;
 
 	if (!data_flag) {
 		/* fill header */
@@ -357,14 +350,14 @@ int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
 			 * have older filled sector also
 			 */
 			memset(&flash_hdr, 0, sizeof(struct cudbg_flash_hdr));
-			rc = read_flash(adap, CUDBG_START_SEC, &flash_hdr,
+			rc = read_flash(adap, cudbg_start_sec, &flash_hdr,
 				sizeof(struct cudbg_flash_hdr),
 				sec_hdr_start_addr);
 
 			if (flash_hdr.signature == CUDBG_FL_SIGNATURE) {
 				sec_info->max_timestamp = flash_hdr.timestamp;
 			} else {
-				rc = read_flash(adap, CUDBG_START_SEC + 1,
+				rc = read_flash(adap, cudbg_start_sec + 1,
 					&flash_hdr,
 					sizeof(struct cudbg_flash_hdr),
 					sec_hdr_start_addr);
@@ -383,8 +376,8 @@ int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
 			/* finding max sequence number because max sequenced
 			 * sector has updated header
 			 */
-			for (i = CUDBG_START_SEC; i <
-					CUDBG_SF_MAX_SECTOR; i++) {
+			for (i = cudbg_start_sec; i < cudbg_start_sec +
+			    cudbg_len / SF_SEC_SIZE; i++) {
 				memset(&flash_hdr, 0,
 				       sizeof(struct cudbg_flash_hdr));
 				rc = read_flash(adap, i, &flash_hdr,
@@ -423,7 +416,8 @@ int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
 
 	/* finding sector sequence sorted */
 	for (i = 1; i <= sec_info->max_seq_no; i++) {
-		for (j = CUDBG_START_SEC; j < CUDBG_SF_MAX_SECTOR; j++) {
+		for (j = cudbg_start_sec; j < cudbg_start_sec +
+		    cudbg_len / SF_SEC_SIZE; j++) {
 			memset(&flash_hdr, 0, sizeof(struct cudbg_flash_hdr));
 			rc = read_flash(adap, j, &flash_hdr,
 				sizeof(struct cudbg_flash_hdr),
@@ -434,10 +428,8 @@ int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
 					sec_info->max_timestamp ==
 					flash_hdr.timestamp &&
 					flash_hdr.sec_seq_no == i) {
-				if (size + total_hdr_size >
-						CUDBG_SF_SECTOR_SIZE)
-					tmp_size = CUDBG_SF_SECTOR_SIZE -
-						total_hdr_size;
+				if (size + total_hdr_size > SF_SEC_SIZE)
+					tmp_size = SF_SEC_SIZE - total_hdr_size;
 				else
 					tmp_size =  size;
 
@@ -468,7 +460,7 @@ int read_flash(struct adapter *adap, u32 start_sec , void *data, u32 size,
 	unsigned int addr, i, n;
 	int rc;
 	u32 *ptr = (u32 *)data;
-	addr = start_sec * CUDBG_SF_SECTOR_SIZE + start_address;
+	addr = start_sec * SF_SEC_SIZE + start_address;
 	size = size / 4;
 	for (i = 0; i < size; i += SF_PAGE_SIZE) {
 		if ((size - i) <  SF_PAGE_SIZE)
diff --git a/sys/dev/cxgbe/cudbg/cudbg_lib.c b/sys/dev/cxgbe/cudbg/cudbg_lib.c
index a36c53f68223..f0273349263a 100644
--- a/sys/dev/cxgbe/cudbg/cudbg_lib.c
+++ b/sys/dev/cxgbe/cudbg/cudbg_lib.c
@@ -155,23 +155,25 @@ static int wr_entity_to_flash(void *handle, struct cudbg_buffer *dbg_buff,
 	u32 flash_data_offset;
 	u32 data_hdr_size;
 	int rc = -1;
+	unsigned int cudbg_len;
 
 	data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
 			sizeof(struct cudbg_hdr);
+	t4_flash_loc_start(cudbg_init->adap, FLASH_LOC_CUDBG, &cudbg_len);
 
-	flash_data_offset = (FLASH_CUDBG_NSECS *
+	flash_data_offset = ((cudbg_len / SF_SEC_SIZE) *
 			     (sizeof(struct cudbg_flash_hdr) +
 			      data_hdr_size)) +
 			    (cur_entity_data_offset - data_hdr_size);
 
-	if (flash_data_offset > CUDBG_FLASH_SIZE) {
+	if (flash_data_offset > cudbg_len) {
 		update_skip_size(sec_info, cur_entity_size);
 		if (cudbg_init->verbose)
 			cudbg_init->print("Large entity skipping...\n");
 		return rc;
 	}
 
-	remain_flash_size = CUDBG_FLASH_SIZE - flash_data_offset;
+	remain_flash_size = cudbg_len - flash_data_offset;
 
 	if (cur_entity_size > remain_flash_size) {
 		update_skip_size(sec_info, cur_entity_size);
@@ -1292,6 +1294,7 @@ static int collect_macstats(struct cudbg_init *pdbg_init,
 
 	mac_stats_buff->port_count = n;
 	for (i = 0; i <  mac_stats_buff->port_count; i++)
+		/* Incorrect, should use hport instead of i */
 		t4_get_port_stats(padap, i, &mac_stats_buff->stats[i]);
 
 	rc = write_compression_hdr(&scratch_buff, dbg_buff);
@@ -1967,7 +1970,7 @@ static int collect_fw_devlog(struct cudbg_init *pdbg_init,
 	u32 offset;
 	int rc = 0, i;
 
-	rc = t4_init_devlog_params(padap, 1);
+	rc = t4_init_devlog_ncores_params(padap, 1);
 
 	if (rc < 0) {
 		pdbg_init->print("%s(), t4_init_devlog_params failed!, rc: "\
diff --git a/sys/dev/cxgbe/cudbg/cudbg_lib_common.h b/sys/dev/cxgbe/cudbg/cudbg_lib_common.h
index 86390eb4399d..b6a85f436db0 100644
--- a/sys/dev/cxgbe/cudbg/cudbg_lib_common.h
+++ b/sys/dev/cxgbe/cudbg/cudbg_lib_common.h
@@ -59,11 +59,6 @@
 #include "common/t4_hw.h"
 #endif
 
-#define CUDBG_SF_MAX_SECTOR         (FLASH_CUDBG_START_SEC + FLASH_CUDBG_NSECS)
-#define CUDBG_SF_SECTOR_SIZE        SF_SEC_SIZE
-#define CUDBG_START_SEC             FLASH_CUDBG_START_SEC
-#define CUDBG_FLASH_SIZE            FLASH_CUDBG_MAX_SIZE
-
 #define CUDBG_EXT_DATA_BIT          0
 #define CUDBG_EXT_DATA_VALID        (1 << CUDBG_EXT_DATA_BIT)
 
@@ -121,7 +116,7 @@ struct cudbg_flash_sec_info {
 	u32 hdr_data_len;	   /* Total data */
 	u32 skip_size;		   /* Total size of large entities. */
 	u64 max_timestamp;
-	char sec_data[CUDBG_SF_SECTOR_SIZE];
+	char sec_data[SF_SEC_SIZE];
 	u8 sec_bitmap[8];
 };
 
diff --git a/sys/dev/cxgbe/cxgbei/icl_cxgbei.c b/sys/dev/cxgbe/cxgbei/icl_cxgbei.c
index d805642541d3..9cdfd0fb9652 100644
--- a/sys/dev/cxgbe/cxgbei/icl_cxgbei.c
+++ b/sys/dev/cxgbe/cxgbei/icl_cxgbei.c
@@ -976,42 +976,6 @@ icl_cxgbei_setsockopt(struct icl_conn *ic, struct socket *so, int sspace,
 	return (0);
 }
 
-/*
- * Request/response structure used to find out the adapter offloading a socket.
- */
-struct find_ofld_adapter_rr {
-	struct socket *so;
-	struct adapter *sc;	/* result */
-};
-
-static void
-find_offload_adapter(struct adapter *sc, void *arg)
-{
-	struct find_ofld_adapter_rr *fa = arg;
-	struct socket *so = fa->so;
-	struct tom_data *td = sc->tom_softc;
-	struct tcpcb *tp;
-	struct inpcb *inp;
-
-	/* Non-TCP were filtered out earlier. */
-	MPASS(so->so_proto->pr_protocol == IPPROTO_TCP);
-
-	if (fa->sc != NULL)
-		return;	/* Found already. */
-
-	if (td == NULL)
-		return;	/* TOE not enabled on this adapter. */
-
-	inp = sotoinpcb(so);
-	INP_WLOCK(inp);
-	if ((inp->inp_flags & INP_DROPPED) == 0) {
-		tp = intotcpcb(inp);
-		if (tp->t_flags & TF_TOE && tp->tod == &td->tod)
-			fa->sc = sc;	/* Found. */
-	}
-	INP_WUNLOCK(inp);
-}
-
 static bool
 is_memfree(struct adapter *sc)
 {
@@ -1025,48 +989,6 @@ is_memfree(struct adapter *sc)
 	return (true);
 }
 
-/* XXXNP: move this to t4_tom. */
-static void
-send_iscsi_flowc_wr(struct adapter *sc, struct toepcb *toep, int maxlen)
-{
-	struct wrqe *wr;
-	struct fw_flowc_wr *flowc;
-	const u_int nparams = 1;
-	u_int flowclen;
-	struct ofld_tx_sdesc *txsd = &toep->txsd[toep->txsd_pidx];
-
-	flowclen = sizeof(*flowc) + nparams * sizeof(struct fw_flowc_mnemval);
-
-	wr = alloc_wrqe(roundup2(flowclen, 16), &toep->ofld_txq->wrq);
-	if (wr == NULL) {
-		/* XXX */
-		panic("%s: allocation failure.", __func__);
-	}
-	flowc = wrtod(wr);
-	memset(flowc, 0, wr->wr_len);
-
-	flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
-	    V_FW_FLOWC_WR_NPARAMS(nparams));
-	flowc->flowid_len16 = htonl(V_FW_WR_LEN16(howmany(flowclen, 16)) |
-	    V_FW_WR_FLOWID(toep->tid));
-
-	flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_TXDATAPLEN_MAX;
-	flowc->mnemval[0].val = htobe32(maxlen);
-
-	KASSERT(howmany(flowclen, 16) <= MAX_OFLD_TX_SDESC_CREDITS,
-	    ("%s: tx_credits %u too large", __func__, howmany(flowclen, 16)));
-	txsd->tx_credits = howmany(flowclen, 16);
-	txsd->plen = 0;
-	KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0,
-	    ("%s: not enough credits (%d)", __func__, toep->tx_credits));
-	toep->tx_credits -= txsd->tx_credits;
-	if (__predict_false(++toep->txsd_pidx == toep->txsd_total))
-		toep->txsd_pidx = 0;
-	toep->txsd_avail--;
-
-	t4_wrq_tx(sc, wr);
-}
-
 static void
 set_ulp_mode_iscsi(struct adapter *sc, struct toepcb *toep, u_int ulp_submode)
 {
@@ -1095,7 +1017,6 @@ int
 icl_cxgbei_conn_handoff(struct icl_conn *ic, int fd)
 {
 	struct icl_cxgbei_conn *icc = ic_to_icc(ic);
-	struct find_ofld_adapter_rr fa;
 	struct file *fp;
 	struct socket *so;
 	struct inpcb *inp;
@@ -1139,15 +1060,11 @@ icl_cxgbei_conn_handoff(struct icl_conn *ic, int fd)
 	fdrop(fp, curthread);
 	ICL_CONN_UNLOCK(ic);
 
-	/* Find the adapter offloading this socket. */
-	fa.sc = NULL;
-	fa.so = so;
-	t4_iterate(find_offload_adapter, &fa);
-	if (fa.sc == NULL) {
+	icc->sc = find_offload_adapter(so);
+	if (icc->sc == NULL) {
 		error = EINVAL;
 		goto out;
 	}
-	icc->sc = fa.sc;
 
 	max_rx_pdu_len = ISCSI_BHS_SIZE + ic->ic_max_recv_data_segment_length;
 	max_tx_pdu_len = ISCSI_BHS_SIZE + ic->ic_max_send_data_segment_length;
@@ -1205,7 +1122,7 @@ icl_cxgbei_conn_handoff(struct icl_conn *ic, int fd)
 	toep->params.ulp_mode = ULP_MODE_ISCSI;
 	toep->ulpcb = icc;
 
-	send_iscsi_flowc_wr(icc->sc, toep,
+	send_txdataplen_max_flowc_wr(icc->sc, toep,
 	    roundup(max_iso_pdus * max_tx_pdu_len, tp->t_maxseg));
 	set_ulp_mode_iscsi(icc->sc, toep, icc->ulp_submode);
 	INP_WUNLOCK(inp);
@@ -1778,7 +1695,6 @@ cxgbei_limits(struct adapter *sc, void *arg)
 static int
 cxgbei_limits_fd(struct icl_drv_limits *idl, int fd)
 {
-	struct find_ofld_adapter_rr fa;
 	struct file *fp;
 	struct socket *so;
 	struct adapter *sc;
@@ -1801,17 +1717,13 @@ cxgbei_limits_fd(struct icl_drv_limits *idl, int fd)
 		return (EINVAL);
 	}
 
-	/* Find the adapter offloading this socket. */
-	fa.sc = NULL;
-	fa.so = so;
-	t4_iterate(find_offload_adapter, &fa);
-	if (fa.sc == NULL) {
+	sc = find_offload_adapter(so);
+	if (sc == NULL) {
 		fdrop(fp, curthread);
 		return (ENXIO);
 	}
 	fdrop(fp, curthread);
 
-	sc = fa.sc;
 	error = begin_synchronized_op(sc, NULL, HOLD_LOCK, "t4lims");
 	if (error != 0)
 		return (error);
diff --git a/sys/dev/cxgbe/firmware/t4fw_interface.h b/sys/dev/cxgbe/firmware/t4fw_interface.h
index 2794bae9474b..5874f0343b03 100644
--- a/sys/dev/cxgbe/firmware/t4fw_interface.h
+++ b/sys/dev/cxgbe/firmware/t4fw_interface.h
@@ -1,6 +1,5 @@
 /*-
- * Copyright (c) 2012-2017 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2012-2017, 2025 Chelsio Communications.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -67,8 +66,8 @@ enum fw_retval {
 	FW_FCOE_NO_XCHG		= 136,	/* */
 	FW_SCSI_RSP_ERR		= 137,	/* */
 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
-	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
-	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
+	FW_SCSI_UNDER_FLOW_ERR	= 139,	/* */
+	FW_SCSI_OVER_FLOW_ERR	= 140,	/* */
 	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
 	FW_SCSI_IO_BLOCK	= 143,	/* IO is going to be blocked due to resource failure */
@@ -85,7 +84,7 @@ enum fw_memtype {
 	FW_MEMTYPE_FLASH	= 0x4,
 	FW_MEMTYPE_INTERNAL	= 0x5,
 	FW_MEMTYPE_EXTMEM1	= 0x6,
-	FW_MEMTYPE_HMA          = 0x7,
+	FW_MEMTYPE_HMA		= 0x7,
 };
 
 /******************************************************************************
@@ -106,10 +105,14 @@ enum fw_wr_opcodes {
 	FW_OFLD_CONNECTION_WR	= 0x2f,
 	FW_FLOWC_WR		= 0x0a,
 	FW_OFLD_TX_DATA_WR	= 0x0b,
+	FW_OFLD_TX_DATA_V2_WR	= 0x0f,
 	FW_CMD_WR		= 0x10,
 	FW_ETH_TX_PKT_VM_WR	= 0x11,
 	FW_ETH_TX_PKTS_VM_WR	= 0x12,
 	FW_RI_RES_WR		= 0x0c,
+	FW_QP_RES_WR		= FW_RI_RES_WR,
+	/* iwarp wr used from rdma kernel and user space */
+	FW_V2_NVMET_TX_DATA_WR	= 0x13,
 	FW_RI_RDMA_WRITE_WR	= 0x14,
 	FW_RI_SEND_WR		= 0x15,
 	FW_RI_RDMA_READ_WR	= 0x16,
@@ -118,6 +121,15 @@ enum fw_wr_opcodes {
 	FW_RI_FR_NSMR_WR	= 0x19,
 	FW_RI_FR_NSMR_TPTE_WR	= 0x20,
 	FW_RI_RDMA_WRITE_CMPL_WR =  0x21,
+	/* rocev2 wr used from rdma kernel and user space */
+	FW_RI_V2_RDMA_WRITE_WR	= 0x22,
+	FW_RI_V2_SEND_WR	= 0x23,
+	FW_RI_V2_RDMA_READ_WR	= 0x24,
+	FW_RI_V2_BIND_MW_WR	= 0x25,
+	FW_RI_V2_FR_NSMR_WR	= 0x26,
+	FW_RI_V2_ATOMIC_WR	= 0x27,
+	FW_NVMET_V2_FR_NSMR_WR	= 0x28,
+	FW_RI_V2_INV_LSTAG_WR	= 0x1e,
 	FW_RI_INV_LSTAG_WR	= 0x1a,
 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
 	FW_RI_ATOMIC_WR		= 0x16,
@@ -138,10 +150,11 @@ enum fw_wr_opcodes {
 	FW_POFCOE_TCB_WR	= 0x42,
 	FW_POFCOE_ULPTX_WR	= 0x43,
 	FW_ISCSI_TX_DATA_WR	= 0x45,
-	FW_PTP_TX_PKT_WR        = 0x46,
+	FW_PTP_TX_PKT_WR	= 0x46,
 	FW_TLSTX_DATA_WR	= 0x68,
 	FW_TLS_TUNNEL_OFLD_WR	= 0x69,
 	FW_CRYPTO_LOOKASIDE_WR	= 0x6d,
+	FW_CRYPTO_UPDATE_SA_WR	= 0x6e,
 	FW_COISCSI_TGT_WR	= 0x70,
 	FW_COISCSI_TGT_CONN_WR	= 0x71,
 	FW_COISCSI_TGT_XMIT_WR	= 0x72,
@@ -149,7 +162,8 @@ enum fw_wr_opcodes {
 	FW_ISNS_WR		= 0x75,
 	FW_ISNS_XMIT_WR		= 0x76,
 	FW_FILTER2_WR		= 0x77,
-	FW_LASTC2E_WR		= 0x80
+	/* FW_LASTC2E_WR		= 0x80 */
+	FW_LASTC2E_WR		= 0xB0
 };
 
 /*
@@ -308,7 +322,7 @@ enum fw_filter_wr_cookie {
 
 enum fw_filter_wr_nat_mode {
 	FW_FILTER_WR_NATMODE_NONE = 0,
-	FW_FILTER_WR_NATMODE_DIP ,
+	FW_FILTER_WR_NATMODE_DIP,
 	FW_FILTER_WR_NATMODE_DIPDP,
 	FW_FILTER_WR_NATMODE_DIPDPSIP,
 	FW_FILTER_WR_NATMODE_DIPDPSP,
@@ -387,7 +401,7 @@ struct fw_filter2_wr {
 	__u8   newlip[16];
 	__u8   newfip[16];
 	__be32 natseqcheck;
-	__be32 r9;
+	__be32 rocev2_qpn;
 	__be64 r10;
 	__be64 r11;
 	__be64 r12;
@@ -675,6 +689,19 @@ struct fw_filter2_wr {
 #define G_FW_FILTER_WR_MATCHTYPEM(x)	\
     (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
 
+#define S_FW_FILTER2_WR_ROCEV2		31
+#define M_FW_FILTER2_WR_ROCEV2		0x1
+#define V_FW_FILTER2_WR_ROCEV2(x)	((x) << S_FW_FILTER2_WR_ROCEV2)
+#define G_FW_FILTER2_WR_ROCEV2(x)	\
+    (((x) >> S_FW_FILTER2_WR_ROCEV2) & M_FW_FILTER2_WR_ROCEV2)
+#define F_FW_FILTER2_WR_ROCEV2	V_FW_FILTER2_WR_ROCEV2(1U)
+
+#define S_FW_FILTER2_WR_QPN	0
+#define M_FW_FILTER2_WR_QPN	0xffffff
+#define V_FW_FILTER2_WR_QPN(x)	((x) << S_FW_FILTER2_WR_QPN)
+#define G_FW_FILTER2_WR_QPN(x)	\
+    (((x) >> S_FW_FILTER2_WR_QPN) & M_FW_FILTER2_WR_QPN)
+
 struct fw_ulptx_wr {
 	__be32 op_to_compl;
 	__be32 flowid_len16;
@@ -1034,7 +1061,10 @@ enum fw_flowc_mnem {
 	FW_FLOWC_MNEM_SND_SCALE		= 13,
 	FW_FLOWC_MNEM_RCV_SCALE		= 14,
 	FW_FLOWC_MNEM_ULP_MODE		= 15,
-	FW_FLOWC_MNEM_MAX		= 16,
+	FW_FLOWC_MNEM_EQID		= 16,
+	FW_FLOWC_MNEM_CONG_ALG	= 17,
+	FW_FLOWC_MNEM_TXDATAPLEN_MIN	= 18,
+	FW_FLOWC_MNEM_MAX		= 19,
 };
 
 struct fw_flowc_mnemval {
@@ -1153,6 +1183,55 @@ struct fw_ofld_tx_data_wr {
 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
 
+struct fw_ofld_tx_data_v2_wr {
+	__be32 op_to_immdlen;
+	__be32 flowid_len16;
+	__be32 r4;
+	__be16 r5;
+	__be16 wrid;
+	__be32 r6;
+	__be32 seqno;
+	__be32 plen;
+	__be32 lsodisable_to_flags;
+};
+
+#define S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE	31
+#define M_FW_OFLD_TX_DATA_V2_WR_LSODISABLE	0x1
+#define V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE)
+#define G_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) & \
+     M_FW_OFLD_TX_DATA_V2_WR_LSODISABLE)
+#define F_FW_OFLD_TX_DATA_V2_WR_LSODISABLE	\
+    V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(1U)
+
+#define S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD	30
+#define M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD	0x1
+#define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD)
+#define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) & \
+     M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD)
+#define F_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD	\
+    V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(1U)
+
+#define S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE		29
+#define M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE		0x1
+#define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE)
+#define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) & \
+     M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE)
+#define F_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE	\
+    V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(1U)
+
+#define S_FW_OFLD_TX_DATA_V2_WR_FLAGS		0
+#define M_FW_OFLD_TX_DATA_V2_WR_FLAGS		0xfffffff
+#define V_FW_OFLD_TX_DATA_V2_WR_FLAGS(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_V2_WR_FLAGS)
+#define G_FW_OFLD_TX_DATA_V2_WR_FLAGS(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_V2_WR_FLAGS) & M_FW_OFLD_TX_DATA_V2_WR_FLAGS)
+
 struct fw_cmd_wr {
 	__be32 op_dma;
 	__be32 len16_pkd;
@@ -1218,8 +1297,15 @@ enum fw_ri_wr_opcode {
 	FW_RI_FAST_REGISTER		= 0xd,
 	FW_RI_LOCAL_INV			= 0xe,
 #endif
+	/* Chelsio specific */
 	FW_RI_SGE_EC_CR_RETURN		= 0xf,
 	FW_RI_WRITE_IMMEDIATE	= FW_RI_RDMA_INIT,
+	FW_RI_SEND_IMMEDIATE	= FW_RI_RDMA_INIT,
+
+	FW_RI_ROCEV2_SEND			= 0x0,
+	FW_RI_ROCEV2_WRITE			= 0x0,
+	FW_RI_ROCEV2_SEND_WITH_INV	= 0x5,
+	FW_RI_ROCEV2_SEND_IMMEDIATE	= 0xa,
 };
 
 enum fw_ri_wr_flags {
@@ -1229,7 +1315,8 @@ enum fw_ri_wr_flags {
 	FW_RI_READ_FENCE_FLAG		= 0x08,
 	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
 	FW_RI_RDMA_READ_INVALIDATE	= 0x20,
-	FW_RI_RDMA_WRITE_WITH_IMMEDIATE	= 0x40
+	FW_RI_RDMA_WRITE_WITH_IMMEDIATE	= 0x40,
+	//FW_RI_REPLAYED_WR_FLAG		= 0x80,
 };
 
 enum fw_ri_mpa_attrs {
@@ -1522,18 +1609,302 @@ struct fw_ri_cqe {
 #define G_FW_RI_CQE_TYPE(x)   \
     (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
 
-enum fw_ri_res_type {
+enum fw_res_type {
 	FW_RI_RES_TYPE_SQ,
 	FW_RI_RES_TYPE_RQ,
 	FW_RI_RES_TYPE_CQ,
 	FW_RI_RES_TYPE_SRQ,
+	FW_QP_RES_TYPE_SQ = FW_RI_RES_TYPE_SQ,
+	FW_QP_RES_TYPE_CQ = FW_RI_RES_TYPE_CQ,
 };
 
-enum fw_ri_res_op {
+enum fw_res_op {
 	FW_RI_RES_OP_WRITE,
 	FW_RI_RES_OP_RESET,
+	FW_QP_RES_OP_WRITE = FW_RI_RES_OP_WRITE,
+	FW_QP_RES_OP_RESET = FW_RI_RES_OP_RESET,
+};
+
+enum fw_qp_transport_type {
+	FW_QP_TRANSPORT_TYPE_IWARP,
+	FW_QP_TRANSPORT_TYPE_ROCEV2_UD,
+	FW_QP_TRANSPORT_TYPE_ROCEV2_RC,
+	FW_QP_TRANSPORT_TYPE_ROCEV2_XRC_INI,
+	FW_QP_TRANSPORT_TYPE_ROCEV2_XRC_TGT,
+	FW_QP_TRANSPORT_TYPE_NVMET,
+	FW_QP_TRANSPORT_TYPE_TOE,
+	FW_QP_TRANSPORT_TYPE_ISCSI,
+};
+
+struct fw_qp_res {
+	union fw_qp_restype {
+		struct fw_qp_res_sqrq {
+			__u8   restype;
+			__u8   op;
+			__be16 r3;
+			__be32 eqid;
+			__be32 r4[2];
+			__be32 fetchszm_to_iqid;
+			__be32 dcaen_to_eqsize;
+			__be64 eqaddr;
+		} sqrq;
+		struct fw_qp_res_cq {
+			__u8   restype;
+			__u8   op;
+			__be16 r3;
+			__be32 iqid;
+			__be32 r4[2];
+			__be32 iqandst_to_iqandstindex;
+			__be16 iqdroprss_to_iqesize;
+			__be16 iqsize;
+			__be64 iqaddr;
+			__be32 iqns_iqro;
+			__be32 r6_lo;
+			__be64 r7;
+		} cq;
+	} u;
+};
+
+struct fw_qp_res_wr {
+	__be32 op_to_nres;
+	__be32 len16_pkd;
+	__u64  cookie;
+#ifndef C99_NOT_SUPPORTED
+	struct fw_qp_res res[0];
+#endif
 };
 
+#define S_FW_QP_RES_WR_TRANSPORT_TYPE		16
+#define M_FW_QP_RES_WR_TRANSPORT_TYPE		0x7
+#define V_FW_QP_RES_WR_TRANSPORT_TYPE(x)	\
+    ((x) << S_FW_QP_RES_WR_TRANSPORT_TYPE)
+#define G_FW_QP_RES_WR_TRANSPORT_TYPE(x)	\
+    (((x) >> S_FW_QP_RES_WR_TRANSPORT_TYPE) & M_FW_QP_RES_WR_TRANSPORT_TYPE)
+
+#define S_FW_QP_RES_WR_VFN	8
+#define M_FW_QP_RES_WR_VFN	0xff
+#define V_FW_QP_RES_WR_VFN(x)	((x) << S_FW_QP_RES_WR_VFN)
+#define G_FW_QP_RES_WR_VFN(x)	\
+    (((x) >> S_FW_QP_RES_WR_VFN) & M_FW_QP_RES_WR_VFN)
+
+#define S_FW_QP_RES_WR_NRES	0
+#define M_FW_QP_RES_WR_NRES	0xff
+#define V_FW_QP_RES_WR_NRES(x)	((x) << S_FW_QP_RES_WR_NRES)
+#define G_FW_QP_RES_WR_NRES(x)	\
+    (((x) >> S_FW_QP_RES_WR_NRES) & M_FW_QP_RES_WR_NRES)
+
+#define S_FW_QP_RES_WR_FETCHSZM		26
+#define M_FW_QP_RES_WR_FETCHSZM		0x1
+#define V_FW_QP_RES_WR_FETCHSZM(x)	((x) << S_FW_QP_RES_WR_FETCHSZM)
+#define G_FW_QP_RES_WR_FETCHSZM(x)	\
+    (((x) >> S_FW_QP_RES_WR_FETCHSZM) & M_FW_QP_RES_WR_FETCHSZM)
+#define F_FW_QP_RES_WR_FETCHSZM	V_FW_QP_RES_WR_FETCHSZM(1U)
+
+#define S_FW_QP_RES_WR_STATUSPGNS	25
+#define M_FW_QP_RES_WR_STATUSPGNS	0x1
+#define V_FW_QP_RES_WR_STATUSPGNS(x)	((x) << S_FW_QP_RES_WR_STATUSPGNS)
+#define G_FW_QP_RES_WR_STATUSPGNS(x)	\
+    (((x) >> S_FW_QP_RES_WR_STATUSPGNS) & M_FW_QP_RES_WR_STATUSPGNS)
+#define F_FW_QP_RES_WR_STATUSPGNS	V_FW_QP_RES_WR_STATUSPGNS(1U)
+
+#define S_FW_QP_RES_WR_STATUSPGRO	24
+#define M_FW_QP_RES_WR_STATUSPGRO	0x1
+#define V_FW_QP_RES_WR_STATUSPGRO(x)	((x) << S_FW_QP_RES_WR_STATUSPGRO)
+#define G_FW_QP_RES_WR_STATUSPGRO(x)	\
+    (((x) >> S_FW_QP_RES_WR_STATUSPGRO) & M_FW_QP_RES_WR_STATUSPGRO)
+#define F_FW_QP_RES_WR_STATUSPGRO	V_FW_QP_RES_WR_STATUSPGRO(1U)
+
+#define S_FW_QP_RES_WR_FETCHNS		23
+#define M_FW_QP_RES_WR_FETCHNS		0x1
+#define V_FW_QP_RES_WR_FETCHNS(x)	((x) << S_FW_QP_RES_WR_FETCHNS)
+#define G_FW_QP_RES_WR_FETCHNS(x)	\
+    (((x) >> S_FW_QP_RES_WR_FETCHNS) & M_FW_QP_RES_WR_FETCHNS)
+#define F_FW_QP_RES_WR_FETCHNS	V_FW_QP_RES_WR_FETCHNS(1U)
+
+#define S_FW_QP_RES_WR_FETCHRO		22
+#define M_FW_QP_RES_WR_FETCHRO		0x1
+#define V_FW_QP_RES_WR_FETCHRO(x)	((x) << S_FW_QP_RES_WR_FETCHRO)
+#define G_FW_QP_RES_WR_FETCHRO(x)	\
+    (((x) >> S_FW_QP_RES_WR_FETCHRO) & M_FW_QP_RES_WR_FETCHRO)
+#define F_FW_QP_RES_WR_FETCHRO	V_FW_QP_RES_WR_FETCHRO(1U)
+
+#define S_FW_QP_RES_WR_HOSTFCMODE	20
+#define M_FW_QP_RES_WR_HOSTFCMODE	0x3
+#define V_FW_QP_RES_WR_HOSTFCMODE(x)	((x) << S_FW_QP_RES_WR_HOSTFCMODE)
+#define G_FW_QP_RES_WR_HOSTFCMODE(x)	\
+    (((x) >> S_FW_QP_RES_WR_HOSTFCMODE) & M_FW_QP_RES_WR_HOSTFCMODE)
+
+#define S_FW_QP_RES_WR_CPRIO	19
+#define M_FW_QP_RES_WR_CPRIO	0x1
+#define V_FW_QP_RES_WR_CPRIO(x)	((x) << S_FW_QP_RES_WR_CPRIO)
+#define G_FW_QP_RES_WR_CPRIO(x)	\
+    (((x) >> S_FW_QP_RES_WR_CPRIO) & M_FW_QP_RES_WR_CPRIO)
+#define F_FW_QP_RES_WR_CPRIO	V_FW_QP_RES_WR_CPRIO(1U)
+
+#define S_FW_QP_RES_WR_ONCHIP		18
+#define M_FW_QP_RES_WR_ONCHIP		0x1
+#define V_FW_QP_RES_WR_ONCHIP(x)	((x) << S_FW_QP_RES_WR_ONCHIP)
+#define G_FW_QP_RES_WR_ONCHIP(x)	\
+    (((x) >> S_FW_QP_RES_WR_ONCHIP) & M_FW_QP_RES_WR_ONCHIP)
+#define F_FW_QP_RES_WR_ONCHIP	V_FW_QP_RES_WR_ONCHIP(1U)
+
+#define S_FW_QP_RES_WR_PCIECHN		16
+#define M_FW_QP_RES_WR_PCIECHN		0x3
+#define V_FW_QP_RES_WR_PCIECHN(x)	((x) << S_FW_QP_RES_WR_PCIECHN)
+#define G_FW_QP_RES_WR_PCIECHN(x)	\
+    (((x) >> S_FW_QP_RES_WR_PCIECHN) & M_FW_QP_RES_WR_PCIECHN)
+
+#define S_FW_QP_RES_WR_IQID	0
+#define M_FW_QP_RES_WR_IQID	0xffff
+#define V_FW_QP_RES_WR_IQID(x)	((x) << S_FW_QP_RES_WR_IQID)
+#define G_FW_QP_RES_WR_IQID(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQID) & M_FW_QP_RES_WR_IQID)
+
+#define S_FW_QP_RES_WR_DCAEN	31
+#define M_FW_QP_RES_WR_DCAEN	0x1
+#define V_FW_QP_RES_WR_DCAEN(x)	((x) << S_FW_QP_RES_WR_DCAEN)
+#define G_FW_QP_RES_WR_DCAEN(x)	\
+    (((x) >> S_FW_QP_RES_WR_DCAEN) & M_FW_QP_RES_WR_DCAEN)
+#define F_FW_QP_RES_WR_DCAEN	V_FW_QP_RES_WR_DCAEN(1U)
+
+#define S_FW_QP_RES_WR_DCACPU		26
+#define M_FW_QP_RES_WR_DCACPU		0x1f
+#define V_FW_QP_RES_WR_DCACPU(x)	((x) << S_FW_QP_RES_WR_DCACPU)
+#define G_FW_QP_RES_WR_DCACPU(x)	\
+    (((x) >> S_FW_QP_RES_WR_DCACPU) & M_FW_QP_RES_WR_DCACPU)
+
+#define S_FW_QP_RES_WR_FBMIN	23
+#define M_FW_QP_RES_WR_FBMIN	0x7
+#define V_FW_QP_RES_WR_FBMIN(x)	((x) << S_FW_QP_RES_WR_FBMIN)
+#define G_FW_QP_RES_WR_FBMIN(x)	\
+    (((x) >> S_FW_QP_RES_WR_FBMIN) & M_FW_QP_RES_WR_FBMIN)
+
+#define S_FW_QP_RES_WR_FBMAX	20
+#define M_FW_QP_RES_WR_FBMAX	0x7
+#define V_FW_QP_RES_WR_FBMAX(x)	((x) << S_FW_QP_RES_WR_FBMAX)
+#define G_FW_QP_RES_WR_FBMAX(x)	\
+    (((x) >> S_FW_QP_RES_WR_FBMAX) & M_FW_QP_RES_WR_FBMAX)
+
+#define S_FW_QP_RES_WR_CIDXFTHRESHO	19
+#define M_FW_QP_RES_WR_CIDXFTHRESHO	0x1
+#define V_FW_QP_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_QP_RES_WR_CIDXFTHRESHO)
+#define G_FW_QP_RES_WR_CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_QP_RES_WR_CIDXFTHRESHO) & M_FW_QP_RES_WR_CIDXFTHRESHO)
+#define F_FW_QP_RES_WR_CIDXFTHRESHO	V_FW_QP_RES_WR_CIDXFTHRESHO(1U)
+
+#define S_FW_QP_RES_WR_CIDXFTHRESH	16
+#define M_FW_QP_RES_WR_CIDXFTHRESH	0x7
+#define V_FW_QP_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_QP_RES_WR_CIDXFTHRESH)
+#define G_FW_QP_RES_WR_CIDXFTHRESH(x)	\
+    (((x) >> S_FW_QP_RES_WR_CIDXFTHRESH) & M_FW_QP_RES_WR_CIDXFTHRESH)
+
+#define S_FW_QP_RES_WR_EQSIZE		0
+#define M_FW_QP_RES_WR_EQSIZE		0xffff
+#define V_FW_QP_RES_WR_EQSIZE(x)	((x) << S_FW_QP_RES_WR_EQSIZE)
+#define G_FW_QP_RES_WR_EQSIZE(x)	\
+    (((x) >> S_FW_QP_RES_WR_EQSIZE) & M_FW_QP_RES_WR_EQSIZE)
+
+#define S_FW_QP_RES_WR_IQANDST		15
+#define M_FW_QP_RES_WR_IQANDST		0x1
+#define V_FW_QP_RES_WR_IQANDST(x)	((x) << S_FW_QP_RES_WR_IQANDST)
+#define G_FW_QP_RES_WR_IQANDST(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQANDST) & M_FW_QP_RES_WR_IQANDST)
+#define F_FW_QP_RES_WR_IQANDST	V_FW_QP_RES_WR_IQANDST(1U)
+
+#define S_FW_QP_RES_WR_IQANUS		14
+#define M_FW_QP_RES_WR_IQANUS		0x1
+#define V_FW_QP_RES_WR_IQANUS(x)	((x) << S_FW_QP_RES_WR_IQANUS)
+#define G_FW_QP_RES_WR_IQANUS(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQANUS) & M_FW_QP_RES_WR_IQANUS)
+#define F_FW_QP_RES_WR_IQANUS	V_FW_QP_RES_WR_IQANUS(1U)
+
+#define S_FW_QP_RES_WR_IQANUD		12
+#define M_FW_QP_RES_WR_IQANUD		0x3
+#define V_FW_QP_RES_WR_IQANUD(x)	((x) << S_FW_QP_RES_WR_IQANUD)
+#define G_FW_QP_RES_WR_IQANUD(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQANUD) & M_FW_QP_RES_WR_IQANUD)
+
+#define S_FW_QP_RES_WR_IQANDSTINDEX	0
+#define M_FW_QP_RES_WR_IQANDSTINDEX	0xfff
+#define V_FW_QP_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_QP_RES_WR_IQANDSTINDEX)
+#define G_FW_QP_RES_WR_IQANDSTINDEX(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQANDSTINDEX) & M_FW_QP_RES_WR_IQANDSTINDEX)
+
+#define S_FW_QP_RES_WR_IQDROPRSS	15
+#define M_FW_QP_RES_WR_IQDROPRSS	0x1
+#define V_FW_QP_RES_WR_IQDROPRSS(x)	((x) << S_FW_QP_RES_WR_IQDROPRSS)
+#define G_FW_QP_RES_WR_IQDROPRSS(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQDROPRSS) & M_FW_QP_RES_WR_IQDROPRSS)
+#define F_FW_QP_RES_WR_IQDROPRSS	V_FW_QP_RES_WR_IQDROPRSS(1U)
+
+#define S_FW_QP_RES_WR_IQGTSMODE	14
+#define M_FW_QP_RES_WR_IQGTSMODE	0x1
+#define V_FW_QP_RES_WR_IQGTSMODE(x)	((x) << S_FW_QP_RES_WR_IQGTSMODE)
+#define G_FW_QP_RES_WR_IQGTSMODE(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQGTSMODE) & M_FW_QP_RES_WR_IQGTSMODE)
+#define F_FW_QP_RES_WR_IQGTSMODE	V_FW_QP_RES_WR_IQGTSMODE(1U)
+
+#define S_FW_QP_RES_WR_IQPCIECH		12
+#define M_FW_QP_RES_WR_IQPCIECH		0x3
+#define V_FW_QP_RES_WR_IQPCIECH(x)	((x) << S_FW_QP_RES_WR_IQPCIECH)
+#define G_FW_QP_RES_WR_IQPCIECH(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQPCIECH) & M_FW_QP_RES_WR_IQPCIECH)
+
+#define S_FW_QP_RES_WR_IQDCAEN		11
+#define M_FW_QP_RES_WR_IQDCAEN		0x1
+#define V_FW_QP_RES_WR_IQDCAEN(x)	((x) << S_FW_QP_RES_WR_IQDCAEN)
+#define G_FW_QP_RES_WR_IQDCAEN(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQDCAEN) & M_FW_QP_RES_WR_IQDCAEN)
+#define F_FW_QP_RES_WR_IQDCAEN	V_FW_QP_RES_WR_IQDCAEN(1U)
+
+#define S_FW_QP_RES_WR_IQDCACPU		6
+#define M_FW_QP_RES_WR_IQDCACPU		0x1f
+#define V_FW_QP_RES_WR_IQDCACPU(x)	((x) << S_FW_QP_RES_WR_IQDCACPU)
+#define G_FW_QP_RES_WR_IQDCACPU(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQDCACPU) & M_FW_QP_RES_WR_IQDCACPU)
+
+#define S_FW_QP_RES_WR_IQINTCNTTHRESH		4
+#define M_FW_QP_RES_WR_IQINTCNTTHRESH		0x3
+#define V_FW_QP_RES_WR_IQINTCNTTHRESH(x)	\
+    ((x) << S_FW_QP_RES_WR_IQINTCNTTHRESH)
+#define G_FW_QP_RES_WR_IQINTCNTTHRESH(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQINTCNTTHRESH) & M_FW_QP_RES_WR_IQINTCNTTHRESH)
+
+#define S_FW_QP_RES_WR_IQO	3
+#define M_FW_QP_RES_WR_IQO	0x1
+#define V_FW_QP_RES_WR_IQO(x)	((x) << S_FW_QP_RES_WR_IQO)
+#define G_FW_QP_RES_WR_IQO(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQO) & M_FW_QP_RES_WR_IQO)
+#define F_FW_QP_RES_WR_IQO	V_FW_QP_RES_WR_IQO(1U)
+
+#define S_FW_QP_RES_WR_IQCPRIO		2
+#define M_FW_QP_RES_WR_IQCPRIO		0x1
+#define V_FW_QP_RES_WR_IQCPRIO(x)	((x) << S_FW_QP_RES_WR_IQCPRIO)
+#define G_FW_QP_RES_WR_IQCPRIO(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQCPRIO) & M_FW_QP_RES_WR_IQCPRIO)
+#define F_FW_QP_RES_WR_IQCPRIO	V_FW_QP_RES_WR_IQCPRIO(1U)
+
+#define S_FW_QP_RES_WR_IQESIZE		0
+#define M_FW_QP_RES_WR_IQESIZE		0x3
+#define V_FW_QP_RES_WR_IQESIZE(x)	((x) << S_FW_QP_RES_WR_IQESIZE)
+#define G_FW_QP_RES_WR_IQESIZE(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQESIZE) & M_FW_QP_RES_WR_IQESIZE)
+
+#define S_FW_QP_RES_WR_IQNS	31
+#define M_FW_QP_RES_WR_IQNS	0x1
+#define V_FW_QP_RES_WR_IQNS(x)	((x) << S_FW_QP_RES_WR_IQNS)
+#define G_FW_QP_RES_WR_IQNS(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQNS) & M_FW_QP_RES_WR_IQNS)
+#define F_FW_QP_RES_WR_IQNS	V_FW_QP_RES_WR_IQNS(1U)
+
+#define S_FW_QP_RES_WR_IQRO	30
+#define M_FW_QP_RES_WR_IQRO	0x1
+#define V_FW_QP_RES_WR_IQRO(x)	((x) << S_FW_QP_RES_WR_IQRO)
+#define G_FW_QP_RES_WR_IQRO(x)	\
+    (((x) >> S_FW_QP_RES_WR_IQRO) & M_FW_QP_RES_WR_IQRO)
+#define F_FW_QP_RES_WR_IQRO	V_FW_QP_RES_WR_IQRO(1U)
+
+
 struct fw_ri_res {
 	union fw_ri_restype {
 		struct fw_ri_res_sqrq {
@@ -1586,6 +1957,13 @@ struct fw_ri_res_wr {
 #endif
 };
 
+#define S_FW_RI_RES_WR_TRANSPORT_TYPE		16
+#define M_FW_RI_RES_WR_TRANSPORT_TYPE		0x7
+#define V_FW_RI_RES_WR_TRANSPORT_TYPE(x)	\
+    ((x) << S_FW_RI_RES_WR_TRANSPORT_TYPE)
+#define G_FW_RI_RES_WR_TRANSPORT_TYPE(x)	\
+    (((x) >> S_FW_RI_RES_WR_TRANSPORT_TYPE) & M_FW_RI_RES_WR_TRANSPORT_TYPE)
+
 #define S_FW_RI_RES_WR_VFN		8
 #define M_FW_RI_RES_WR_VFN		0xff
 #define V_FW_RI_RES_WR_VFN(x)		((x) << S_FW_RI_RES_WR_VFN)
@@ -2092,8 +2470,18 @@ enum fw_ri_init_rqeqid_srq {
 	FW_RI_INIT_RQEQID_SRQ			= 1 << 31,
 };
 
+enum fw_nvmet_ulpsubmode {
+	FW_NVMET_ULPSUBMODE_HCRC		= 0x1<<0,
+	FW_NVMET_ULPSUBMODE_DCRC		= 0x1<<1,
+	FW_NVMET_ULPSUBMODE_ING_DIR		= 0x1<<2,
+	FW_NVMET_ULPSUBMODE_SRQ_ENABLE	= 0x1<<3,
+	FW_NVMET_ULPSUBMODE_PER_PDU_CMP	= 0x1<<4,
+	FW_NVMET_ULPSUBMODE_PI_ENABLE	= 0x1<<5,
+	FW_NVMET_ULPSUBMODE_USER_MODE	= 0x1<<6,
+};
+
 struct fw_ri_wr {
-	__be32 op_compl;
+	__be32 op_compl; /* op_to_transport_type */
 	__be32 flowid_len16;
 	__u64  cookie;
 	union fw_ri {
@@ -2123,6 +2511,55 @@ struct fw_ri_wr {
 				struct fw_ri_send_wr send;
 			} u;
 		} init;
+		struct fw_ri_rocev2_init {
+			__u8   type;
+			__u8   r3[3];
+			__u8   rocev2_flags;
+			__u8   qp_caps;
+			__be16 nrqe;
+			__be32 pdid;
+			__be32 qpid;
+			__be32 sq_eqid;
+			__be32 rq_eqid;
+			__be32 scqid;
+			__be32 rcqid;
+			__be32 ord_max;
+			__be32 ird_max;
+			__be32 psn_pkd;
+			__be32 epsn_pkd;
+			__be32 hwrqsize;
+			__be32 hwrqaddr;
+			__be32 q_key;
+			__u8   pkthdrsize;
+			__u8   r;
+			__be16 p_key;
+			//struct cpl_tx_tnl_lso tnl_lso;
+			__u8   tnl_lso[48]; /* cpl_tx_tnl_lso + cpl_tx_pkt_xt */
+#ifndef C99_NOT_SUPPORTED
+			struct fw_ri_immd pkthdr[0];
+#endif
+		} rocev2_init;
+		struct fw_ri_nvmet_init {
+			__u8   type;
+			__u8   r3[3];
+			__u8   nvmt_flags;
+			__u8   qp_caps;
+			__be16 nrqe;
+			__be32 pdid;
+			__be32 qpid;
+			__be32 sq_eqid;
+			__be32 rq_eqid;
+			__be32 scqid;
+			__be32 rcqid;
+			__be32 r4[4];
+			__be32 hwrqsize;
+			__be32 hwrqaddr;
+			__u8   ulpsubmode;
+			__u8   nvmt_pda_cmp_imm_sz;
+			__be16 r7;
+			__be32 tpt_offset_t10_config;
+			__be32 r8[2];
+		} nvmet_init;
 		struct fw_ri_fini {
 			__u8   type;
 			__u8   r3[7];
@@ -2137,6 +2574,12 @@ struct fw_ri_wr {
 	} u;
 };
 
+#define S_FW_RI_WR_TRANSPORT_TYPE	16
+#define M_FW_RI_WR_TRANSPORT_TYPE	0x7
+#define V_FW_RI_WR_TRANSPORT_TYPE(x)	((x) << S_FW_RI_WR_TRANSPORT_TYPE)
+#define G_FW_RI_WR_TRANSPORT_TYPE(x)	\
+    (((x) >> S_FW_RI_WR_TRANSPORT_TYPE) & M_FW_RI_WR_TRANSPORT_TYPE)
+
 #define S_FW_RI_WR_MPAREQBIT	7
 #define M_FW_RI_WR_MPAREQBIT	0x1
 #define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
@@ -2157,6 +2600,414 @@ struct fw_ri_wr {
 #define G_FW_RI_WR_P2PTYPE(x)	\
     (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
 
+#define S_FW_RI_WR_PSN		0
+#define M_FW_RI_WR_PSN		0xffffff
+#define V_FW_RI_WR_PSN(x)	((x) << S_FW_RI_WR_PSN)
+#define G_FW_RI_WR_PSN(x)	(((x) >> S_FW_RI_WR_PSN) & M_FW_RI_WR_PSN)
+
+#define S_FW_RI_WR_EPSN		0
+#define M_FW_RI_WR_EPSN		0xffffff
+#define V_FW_RI_WR_EPSN(x)	((x) << S_FW_RI_WR_EPSN)
+#define G_FW_RI_WR_EPSN(x)	(((x) >> S_FW_RI_WR_EPSN) & M_FW_RI_WR_EPSN)
+
+#define S_FW_RI_WR_NVMT_PDA	3
+#define M_FW_RI_WR_NVMT_PDA	0x1f
+#define V_FW_RI_WR_NVMT_PDA(x)	((x) << S_FW_RI_WR_NVMT_PDA)
+#define G_FW_RI_WR_NVMT_PDA(x)	\
+    (((x) >> S_FW_RI_WR_NVMT_PDA) & M_FW_RI_WR_NVMT_PDA)
+
+#define S_FW_RI_WR_CMP_IMM_SZ		1
+#define M_FW_RI_WR_CMP_IMM_SZ		0x3
+#define V_FW_RI_WR_CMP_IMM_SZ(x)	((x) << S_FW_RI_WR_CMP_IMM_SZ)
+#define G_FW_RI_WR_CMP_IMM_SZ(x)	\
+    (((x) >> S_FW_RI_WR_CMP_IMM_SZ) & M_FW_RI_WR_CMP_IMM_SZ)
+
+#define S_FW_RI_WR_TPT_OFFSET		10
+#define M_FW_RI_WR_TPT_OFFSET		0x3fffff
+#define V_FW_RI_WR_TPT_OFFSET(x)	((x) << S_FW_RI_WR_TPT_OFFSET)
+#define G_FW_RI_WR_TPT_OFFSET(x)	\
+    (((x) >> S_FW_RI_WR_TPT_OFFSET) & M_FW_RI_WR_TPT_OFFSET)
+
+#define S_FW_RI_WR_T10_CONFIG		0
+#define M_FW_RI_WR_T10_CONFIG		0x3ff
+#define V_FW_RI_WR_T10_CONFIG(x)	((x) << S_FW_RI_WR_T10_CONFIG)
+#define G_FW_RI_WR_T10_CONFIG(x)	\
+    (((x) >> S_FW_RI_WR_T10_CONFIG) & M_FW_RI_WR_T10_CONFIG)
+
+
+/******************************************************************************
+ *   R o C E V 2    W O R K   R E Q U E S T s
+ **************************************/
+enum fw_rocev2_wr_opcode {
+	/* RC */
+	FW_ROCEV2_RC_SEND_FIRST			= 0x00,
+	FW_ROCEV2_RC_SEND_MIDDLE		= 0x01,
+	FW_ROCEV2_RC_SEND_LAST			= 0x02,
+	FW_ROCEV2_RC_SEND_LAST_WITH_IMMD 	= 0x03,
+	FW_ROCEV2_RC_SEND_ONLY			= 0x04,
+	FW_ROCEV2_RC_SEND_ONLY_WITH_IMMD	= 0x05,
+	FW_ROCEV2_RC_RDMA_WRITE_FIRST		= 0x06,
+	FW_ROCEV2_RC_RDMA_WRITE_MIDDLE		= 0x07,
+	FW_ROCEV2_RC_RDMA_WRITE_LAST		= 0x08,
+	FW_ROCEV2_RC_RDMA_WRITE_LAST_WITH_IMMD	= 0x09,
+	FW_ROCEV2_RC_RDMA_WRITE_ONLY		= 0x0a,
+	FW_ROCEV2_RC_RDMA_WRITE_ONLY_WITH_IMMD	= 0x0b,
+	FW_ROCEV2_RC_RDMA_READ_REQ		= 0x0c,
+	FW_ROCEV2_RC_RDMA_READ_RESP_FIRST	= 0x0d,
+	FW_ROCEV2_RC_RDMA_READ_RESP_MIDDLE	= 0x0e,
+	FW_ROCEV2_RC_RDMA_READ_RESP_LAST	= 0x0f,
+	FW_ROCEV2_RC_RDMA_READ_RESP_ONLY	= 0x10,
+	FW_ROCEV2_RC_ACK			= 0x11,
+	FW_ROCEV2_RC_ATOMIC_ACK			= 0x12,
+	FW_ROCEV2_RC_CMP_SWAP			= 0x13,
+	FW_ROCEV2_RC_FETCH_ADD			= 0x14,
+	FW_ROCEV2_RC_SEND_LAST_WITH_INV		= 0x16,
+	FW_ROCEV2_RC_SEND_ONLY_WITH_INV		= 0x17,
+
+	/* XRC */
+	FW_ROCEV2_XRC_SEND_FIRST		= 0xa0,
+	FW_ROCEV2_XRC_SEND_MIDDLE		= 0xa1,
+	FW_ROCEV2_XRC_SEND_LAST			= 0xa2,
+	FW_ROCEV2_XRC_SEND_LAST_WITH_IMMD	= 0xa3,
+	FW_ROCEV2_XRC_SEND_ONLY			= 0xa4,
+	FW_ROCEV2_XRC_SEND_ONLY_WITH_IMMD	= 0xa5,
+	FW_ROCEV2_XRC_RDMA_WRITE_FIRST		= 0xa6,
+	FW_ROCEV2_XRC_RDMA_WRITE_MIDDLE		= 0xa7,
+	FW_ROCEV2_XRC_RDMA_WRITE_LAST		= 0xa8,
+	FW_ROCEV2_XRC_RDMA_WRITE_LAST_WITH_IMMD	= 0xa9,
+	FW_ROCEV2_XRC_RDMA_WRITE_ONLY		= 0xaa,
+	FW_ROCEV2_XRC_RDMA_WRITE_ONLY_WITH_IMMD	= 0xab,
+	FW_ROCEV2_XRC_RDMA_READ_REQ		= 0xac,
+	FW_ROCEV2_XRC_RDMA_READ_RESP_FIRST	= 0xad,
+	FW_ROCEV2_XRC_RDMA_READ_RESP_MIDDLE	= 0xae,
+	FW_ROCEV2_XRC_RDMA_READ_RESP_LAST	= 0xaf,
+	FW_ROCEV2_XRC_RDMA_READ_RESP_ONLY	= 0xb0,
+	FW_ROCEV2_XRC_ACK			= 0xb1,
+	FW_ROCEV2_XRC_ATOMIC_ACK		= 0xb2,
+	FW_ROCEV2_XRC_CMP_SWAP			= 0xb3,
+	FW_ROCEV2_XRC_FETCH_ADD			= 0xb4,
+	FW_ROCEV2_XRC_SEND_LAST_WITH_INV	= 0xb6,
+	FW_ROCEV2_XRC_SEND_ONLY_WITH_INV	= 0xb7,
+};
+
+#if 0
+enum fw_rocev2_cqe_err {
+	/* TODO */
+};
+#endif
+
+struct fw_ri_v2_rdma_write_wr {
+	__u8   opcode;
+	__u8   v2_flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2; /* set to 0 */
+	__be32 psn_pkd;
+	__be32 r4[2];
+	__be32 r5;
+	__be32 immd_data;
+	__be64 to_sink;
+	__be32 stag_sink;
+	__be32 plen;
+#ifndef C99_NOT_SUPPORTED
+	union {
+		struct fw_ri_immd immd_src[0];
+		struct fw_ri_isgl isgl_src[0];
+	} u;
+#endif
+};
+
+#define S_FW_RI_V2_RDMA_WRITE_WR_PSN	0
+#define M_FW_RI_V2_RDMA_WRITE_WR_PSN	0xffffff
+#define V_FW_RI_V2_RDMA_WRITE_WR_PSN(x)	((x) << S_FW_RI_V2_RDMA_WRITE_WR_PSN)
+#define G_FW_RI_V2_RDMA_WRITE_WR_PSN(x)	\
+    (((x) >> S_FW_RI_V2_RDMA_WRITE_WR_PSN) & M_FW_RI_V2_RDMA_WRITE_WR_PSN)
+
+struct fw_ri_v2_send_wr {
+	__u8   opcode;
+	__u8   v2_flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2; /* set to 0 */
+	__be32 stag_inv;
+	__be32 plen;
+	__be32 sendop_psn;
+	__u8   immdlen;
+	__u8   r3[3];
+	__be32 r4;
+	/* CPL_TX_TNL_LSO, CPL_TX_PKT_XT and Eth/IP/UDP/BTH
+	 * headers in UD QP case, align size to 16B */
+#ifndef C99_NOT_SUPPORTED
+	union {
+		struct fw_ri_immd immd_src[0];
+		struct fw_ri_isgl isgl_src[0];
+	} u;
+#endif
+};
+
+#define S_FW_RI_V2_SEND_WR_SENDOP	24
+#define M_FW_RI_V2_SEND_WR_SENDOP	0xff
+#define V_FW_RI_V2_SEND_WR_SENDOP(x)	((x) << S_FW_RI_V2_SEND_WR_SENDOP)
+#define G_FW_RI_V2_SEND_WR_SENDOP(x)	\
+    (((x) >> S_FW_RI_V2_SEND_WR_SENDOP) & M_FW_RI_V2_SEND_WR_SENDOP)
+
+#define S_FW_RI_V2_SEND_WR_PSN		0
+#define M_FW_RI_V2_SEND_WR_PSN		0xffffff
+#define V_FW_RI_V2_SEND_WR_PSN(x)	((x) << S_FW_RI_V2_SEND_WR_PSN)
+#define G_FW_RI_V2_SEND_WR_PSN(x)	\
+    (((x) >> S_FW_RI_V2_SEND_WR_PSN) & M_FW_RI_V2_SEND_WR_PSN)
+
+struct fw_ri_v2_rdma_read_wr {
+	__u8   opcode;
+	__u8   v2_flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2; /* set to 0 */
+	__be32 psn_pkd;
+	__be64 to_src;
+	__be32 stag_src;
+	__be32 plen;
+	struct fw_ri_isgl isgl_sink; /* RRQ, max 4 nsge in rocev2, 1 in iwarp */
+};
+
+#define S_FW_RI_V2_RDMA_READ_WR_PSN	0
+#define M_FW_RI_V2_RDMA_READ_WR_PSN	0xffffff
+#define V_FW_RI_V2_RDMA_READ_WR_PSN(x)	((x) << S_FW_RI_V2_RDMA_READ_WR_PSN)
+#define G_FW_RI_V2_RDMA_READ_WR_PSN(x)	\
+    (((x) >> S_FW_RI_V2_RDMA_READ_WR_PSN) & M_FW_RI_V2_RDMA_READ_WR_PSN)
+
+struct fw_ri_v2_atomic_wr {
+	__u8   opcode;
+	__u8   v2_flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2; /* set to 0 */
+	__be32 atomicop_psn;
+};
+
+#define S_FW_RI_V2_ATOMIC_WR_ATOMICOP		28
+#define M_FW_RI_V2_ATOMIC_WR_ATOMICOP		0xf
+#define V_FW_RI_V2_ATOMIC_WR_ATOMICOP(x)	\
+    ((x) << S_FW_RI_V2_ATOMIC_WR_ATOMICOP)
+#define G_FW_RI_V2_ATOMIC_WR_ATOMICOP(x)	\
+    (((x) >> S_FW_RI_V2_ATOMIC_WR_ATOMICOP) & M_FW_RI_V2_ATOMIC_WR_ATOMICOP)
+
+#define S_FW_RI_V2_ATOMIC_WR_PSN	0
+#define M_FW_RI_V2_ATOMIC_WR_PSN	0xffffff
+#define V_FW_RI_V2_ATOMIC_WR_PSN(x)	((x) << S_FW_RI_V2_ATOMIC_WR_PSN)
+#define G_FW_RI_V2_ATOMIC_WR_PSN(x)	\
+    (((x) >> S_FW_RI_V2_ATOMIC_WR_PSN) & M_FW_RI_V2_ATOMIC_WR_PSN)
+
+struct fw_ri_v2_bind_mw_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2;
+	__be32 r5;
+	__be32 r6[2];
+	__u8   qpbinde_to_dcacpu;
+	__u8   pgsz_shift;
+	__u8   addr_type;
+	__u8   mem_perms;
+	__be32 stag_mr;
+	__be32 stag_mw;
+	__be32 r3;
+	__be64 len_mw;
+	__be64 va_fbo;
+	__be64 r4;
+};
+
+
+#define S_FW_RI_V2_BIND_MW_WR_QPBINDE		6
+#define M_FW_RI_V2_BIND_MW_WR_QPBINDE		0x1
+#define V_FW_RI_V2_BIND_MW_WR_QPBINDE(x)	\
+    ((x) << S_FW_RI_V2_BIND_MW_WR_QPBINDE)
+#define G_FW_RI_V2_BIND_MW_WR_QPBINDE(x)	\
+    (((x) >> S_FW_RI_V2_BIND_MW_WR_QPBINDE) & M_FW_RI_V2_BIND_MW_WR_QPBINDE)
+#define F_FW_RI_V2_BIND_MW_WR_QPBINDE	V_FW_RI_V2_BIND_MW_WR_QPBINDE(1U)
+
+#define S_FW_RI_V2_BIND_MW_WR_NS	5
+#define M_FW_RI_V2_BIND_MW_WR_NS	0x1
+#define V_FW_RI_V2_BIND_MW_WR_NS(x)	((x) << S_FW_RI_V2_BIND_MW_WR_NS)
+#define G_FW_RI_V2_BIND_MW_WR_NS(x)	\
+    (((x) >> S_FW_RI_V2_BIND_MW_WR_NS) & M_FW_RI_V2_BIND_MW_WR_NS)
+#define F_FW_RI_V2_BIND_MW_WR_NS	V_FW_RI_V2_BIND_MW_WR_NS(1U)
+
+#define S_FW_RI_V2_BIND_MW_WR_DCACPU	0
+#define M_FW_RI_V2_BIND_MW_WR_DCACPU	0x1f
+#define V_FW_RI_V2_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_V2_BIND_MW_WR_DCACPU)
+#define G_FW_RI_V2_BIND_MW_WR_DCACPU(x)	\
+    (((x) >> S_FW_RI_V2_BIND_MW_WR_DCACPU) & M_FW_RI_V2_BIND_MW_WR_DCACPU)
+
+struct fw_ri_v2_fr_nsmr_wr {
+	__u8   opcode;
+	__u8   v2_flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2;
+	__be32 r3;
+	__be32 r4[2];
+	__u8   qpbinde_to_dcacpu;
+	__u8   pgsz_shift;
+	__u8   addr_type;
+	__u8   mem_perms;
+	__be32 stag;
+	__be32 len_hi;
+	__be32 len_lo;
+	__be32 va_hi;
+	__be32 va_lo_fbo;
+};
+
+#define S_FW_RI_V2_FR_NSMR_WR_QPBINDE		6
+#define M_FW_RI_V2_FR_NSMR_WR_QPBINDE		0x1
+#define V_FW_RI_V2_FR_NSMR_WR_QPBINDE(x)	\
+    ((x) << S_FW_RI_V2_FR_NSMR_WR_QPBINDE)
+#define G_FW_RI_V2_FR_NSMR_WR_QPBINDE(x)	\
+    (((x) >> S_FW_RI_V2_FR_NSMR_WR_QPBINDE) & M_FW_RI_V2_FR_NSMR_WR_QPBINDE)
+#define F_FW_RI_V2_FR_NSMR_WR_QPBINDE	V_FW_RI_V2_FR_NSMR_WR_QPBINDE(1U)
+
+#define S_FW_RI_V2_FR_NSMR_WR_NS	5
+#define M_FW_RI_V2_FR_NSMR_WR_NS	0x1
+#define V_FW_RI_V2_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_V2_FR_NSMR_WR_NS)
+#define G_FW_RI_V2_FR_NSMR_WR_NS(x)	\
+    (((x) >> S_FW_RI_V2_FR_NSMR_WR_NS) & M_FW_RI_V2_FR_NSMR_WR_NS)
+#define F_FW_RI_V2_FR_NSMR_WR_NS	V_FW_RI_V2_FR_NSMR_WR_NS(1U)
+
+#define S_FW_RI_V2_FR_NSMR_WR_DCACPU	0
+#define M_FW_RI_V2_FR_NSMR_WR_DCACPU	0x1f
+#define V_FW_RI_V2_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_V2_FR_NSMR_WR_DCACPU)
+#define G_FW_RI_V2_FR_NSMR_WR_DCACPU(x)	\
+    (((x) >> S_FW_RI_V2_FR_NSMR_WR_DCACPU) & M_FW_RI_V2_FR_NSMR_WR_DCACPU)
+
+/******************************************************************************
+ *  N V M E - T C P  W O R K R E Q U E S T s
+ *****************************************************************************/
+
+struct fw_nvmet_v2_fr_nsmr_wr {
+	__be32 op_to_wrid;
+	__be32 flowid_len16;
+	__be32 r3;
+	__be32 r4;
+	__be32 mem_write_addr32;
+	__u8   r5;
+	__u8   imm_data_len32;
+	union {
+		__be16 dsgl_data_len32;
+		__be16 reset_mem_len32;
+	};
+	__be64 r6;
+};
+
+#define S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL	23
+#define M_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL	0x1
+#define V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x)	\
+    ((x) << S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL)
+#define G_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x)	\
+    (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) & \
+     M_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL)
+#define F_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL	\
+    V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(1U)
+
+#define S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM	22
+#define M_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM	0x1
+#define V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x)	\
+    ((x) << S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM)
+#define G_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x)	\
+    (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) & \
+     M_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM)
+#define F_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM	\
+    V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(1U)
+
+#define S_FW_NVMET_V2_FR_NSMR_WR_WRID		0
+#define M_FW_NVMET_V2_FR_NSMR_WR_WRID		0xffff
+#define V_FW_NVMET_V2_FR_NSMR_WR_WRID(x)	\
+    ((x) << S_FW_NVMET_V2_FR_NSMR_WR_WRID)
+#define G_FW_NVMET_V2_FR_NSMR_WR_WRID(x)	\
+    (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_WRID) & M_FW_NVMET_V2_FR_NSMR_WR_WRID)
+
+struct fw_v2_nvmet_tx_data_wr {
+	__be32 op_to_immdlen;
+	__be32 flowid_len16;
+	__be32 r4;
+	__be16 r5;
+	__be16 wrid;
+	__be32 r6;
+	__be32 seqno;
+	__be32 plen;
+	__be32 flags_hi_to_flags_lo;
+	/* optional immdlen data (fw_tx_pi_hdr, iso cpl, nvmet header etc) */
+#ifndef C99_NOT_SUPPORTED
+	union {
+		struct fw_ri_dsgl dsgl_src[0];
+		struct fw_ri_isgl isgl_src[0];
+	} u;
+#endif
+};
+
+#define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI	10
+#define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI	0x3fffff
+#define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x)	\
+    ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI)
+#define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x)	\
+    (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) & \
+     M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI)
+
+#define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO		9
+#define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO		0x1
+#define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
+    ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO)
+#define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
+    (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) & \
+     M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO)
+#define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO	\
+    V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(1U)
+
+#define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI		8
+#define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI		0x1
+#define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x)	\
+    ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI)
+#define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x)	\
+    (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) & \
+     M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI)
+#define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI	\
+    V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(1U)
+
+#define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC	7
+#define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC	0x1
+#define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
+    ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC)
+#define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
+    (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) & \
+     M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC)
+#define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC	\
+    V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
+
+#define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC	6
+#define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC	0x1
+#define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
+    ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC)
+#define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
+    (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) & \
+     M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC)
+#define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC	\
+    V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
+
+#define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO	0
+#define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO	0x3f
+#define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x)	\
+    ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO)
+#define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x)	\
+    (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) & \
+     M_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO)
+
+
 /******************************************************************************
  *  F O i S C S I   W O R K R E Q U E S T s
  *********************************************/
@@ -3827,17 +4678,17 @@ struct fw_pi_error {
     (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
 
 struct fw_tlstx_data_wr {
-        __be32 op_to_immdlen;
-        __be32 flowid_len16;
-        __be32 plen;
-        __be32 lsodisable_to_flags;
-        __be32 r5;
-        __be32 ctxloc_to_exp;
-        __be16 mfs;
-        __be16 adjustedplen_pkd;
-        __be16 expinplenmax_pkd;
-        __u8   pdusinplenmax_pkd;
-        __u8   r10;
+	__be32 op_to_immdlen;
+	__be32 flowid_len16;
+	__be32 plen;
+	__be32 lsodisable_to_flags;
+	__be32 r5;
+	__be32 ctxloc_to_exp;
+	__be16 mfs;
+	__be16 adjustedplen_pkd;
+	__be16 expinplenmax_pkd;
+	__u8   pdusinplenmax_pkd;
+	__u8   r10;
 };
 
 #define S_FW_TLSTX_DATA_WR_OPCODE       24
@@ -4092,6 +4943,265 @@ struct fw_tls_tunnel_ofld_wr {
 	__be32 r4;
 };
 
+struct fw_crypto_update_sa_wr {
+	__u8   opcode;
+	__u8   saop_to_txrx;
+	__u8   vfn;
+	__u8   r1;
+	__u8   r2[3];
+	__u8   len16;
+	__be64 cookie;
+	__be16 r3;
+	__be16 ipsecidx;
+	__be32 SPI;
+	__be64 dip_hi;
+	__be64 dip_lo;
+	__be64 lip_hi;
+	__be64 lip_lo;
+	union fw_crypto_update_sa_sa {
+		struct egress_sa {
+			__be32 valid_SPI_hi;
+			__be32 SPI_lo_eSeqNum_hi;
+			__be32 eSeqNum_lo_Salt_hi;
+			__be32 Salt_lo_to_keyID;
+		} egress;
+		struct ingress_sa {
+			__be32 valid_to_iSeqNum_hi;
+			__be32 iSeqNum_mi;
+			__be32 iSeqNum_lo_Salt_hi;
+			__be32 Salt_lo_to_IPVer;
+		} ingress;
+	} sa;
+	union fw_crypto_update_sa_key {
+		struct _aes128 {
+			__u8   key128[16];
+			__u8   H128[16];
+			__u8   rsvd[16];
+		} aes128;
+		struct _aes192 {
+			__u8   key192[24];
+			__be64 r3;
+			__u8   H192[16];
+		} aes192;
+		struct _aes256 {
+			__u8   key256[32];
+			__u8   H256[16];
+		} aes256;
+	} key;
+};
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SAOP		2
+#define M_FW_CRYPTO_UPDATE_SA_WR_SAOP		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_SAOP(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SAOP)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SAOP(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SAOP) & M_FW_CRYPTO_UPDATE_SA_WR_SAOP)
+#define F_FW_CRYPTO_UPDATE_SA_WR_SAOP	V_FW_CRYPTO_UPDATE_SA_WR_SAOP(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_MODE		1
+#define M_FW_CRYPTO_UPDATE_SA_WR_MODE		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE)
+#define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE)
+#define F_FW_CRYPTO_UPDATE_SA_WR_MODE	V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_TXRX		0
+#define M_FW_CRYPTO_UPDATE_SA_WR_TXRX		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_TXRX(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_TXRX)
+#define G_FW_CRYPTO_UPDATE_SA_WR_TXRX(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_TXRX) & M_FW_CRYPTO_UPDATE_SA_WR_TXRX)
+#define F_FW_CRYPTO_UPDATE_SA_WR_TXRX	V_FW_CRYPTO_UPDATE_SA_WR_TXRX(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_VALID		31
+#define M_FW_CRYPTO_UPDATE_SA_WR_VALID		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID)
+#define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID)
+#define F_FW_CRYPTO_UPDATE_SA_WR_VALID	V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI		0
+#define M_FW_CRYPTO_UPDATE_SA_WR_SPI_HI		0x7fffffff
+#define V_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_SPI_HI)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO		31
+#define M_FW_CRYPTO_UPDATE_SA_WR_SPI_LO		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_SPI_LO)
+#define F_FW_CRYPTO_UPDATE_SA_WR_SPI_LO	V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI	0
+#define M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI	0x7fffffff
+#define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO	7
+#define M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO	0x1ffffff
+#define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI	0
+#define M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI	0x7f
+#define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO	7
+#define M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO	0x1ffffff
+#define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN		5
+#define M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN		0x3
+#define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN)
+#define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE	4
+#define M_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE	0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE)
+#define F_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE	\
+    V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_KEYID		0
+#define M_FW_CRYPTO_UPDATE_SA_WR_KEYID		0xf
+#define V_FW_CRYPTO_UPDATE_SA_WR_KEYID(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYID)
+#define G_FW_CRYPTO_UPDATE_SA_WR_KEYID(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYID) & M_FW_CRYPTO_UPDATE_SA_WR_KEYID)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_VALID		31
+#define M_FW_CRYPTO_UPDATE_SA_WR_VALID		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID)
+#define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID)
+#define F_FW_CRYPTO_UPDATE_SA_WR_VALID	V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID	12
+#define M_FW_CRYPTO_UPDATE_SA_WR_EGKEYID	0xfff
+#define V_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID)
+#define G_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_EGKEYID)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN	11
+#define M_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN	0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN)
+#define G_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN)
+#define F_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN	\
+    V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW	7
+#define M_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW	0xf
+#define V_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI	0
+#define M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI	0x7f
+#define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO	7
+#define M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO	0x1ffffff
+#define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI	0
+#define M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI	0x7f
+#define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO	7
+#define M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO	0x1ffffff
+#define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO)
+#define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN		5
+#define M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN		0x3
+#define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN)
+#define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH	3
+#define M_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH	0x3
+#define V_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) & \
+     M_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_ESNEN		2
+#define M_FW_CRYPTO_UPDATE_SA_WR_ESNEN		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNEN)
+#define G_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNEN) & M_FW_CRYPTO_UPDATE_SA_WR_ESNEN)
+#define F_FW_CRYPTO_UPDATE_SA_WR_ESNEN	V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_MODE		1
+#define M_FW_CRYPTO_UPDATE_SA_WR_MODE		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE)
+#define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE)
+#define F_FW_CRYPTO_UPDATE_SA_WR_MODE	V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U)
+
+#define S_FW_CRYPTO_UPDATE_SA_WR_IPVER		0
+#define M_FW_CRYPTO_UPDATE_SA_WR_IPVER		0x1
+#define V_FW_CRYPTO_UPDATE_SA_WR_IPVER(x)	\
+    ((x) << S_FW_CRYPTO_UPDATE_SA_WR_IPVER)
+#define G_FW_CRYPTO_UPDATE_SA_WR_IPVER(x)	\
+    (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_IPVER) & M_FW_CRYPTO_UPDATE_SA_WR_IPVER)
+#define F_FW_CRYPTO_UPDATE_SA_WR_IPVER	V_FW_CRYPTO_UPDATE_SA_WR_IPVER(1U)
+
 /******************************************************************************
  *  C O M M A N D s
  *********************/
@@ -4157,11 +5267,12 @@ enum fw_cmd_opcodes {
 	FW_FCOE_SPARAMS_CMD            = 0x35,
 	FW_FCOE_STATS_CMD              = 0x37,
 	FW_FCOE_FCF_CMD                = 0x38,
-	FW_DCB_IEEE_CMD		       = 0x3a,
-	FW_DIAG_CMD		       = 0x3d,
+	FW_DCB_IEEE_CMD                = 0x3a,
+	FW_DIAG_CMD                    = 0x3d,
 	FW_PTP_CMD                     = 0x3e,
 	FW_HMA_CMD                     = 0x3f,
-	FW_LASTC2E_CMD                 = 0x40,
+	FW_JBOF_WIN_REG_CMD            = 0x40,
+	FW_LASTC2E_CMD                 = 0x41,
 	FW_ERROR_CMD                   = 0x80,
 	FW_DEBUG_CMD                   = 0x81,
 };
@@ -4246,7 +5357,7 @@ enum fw_ldst_addrspc {
 	FW_LDST_ADDRSPC_FUNC      = 0x0028,
 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
-	FW_LDST_ADDRSPC_LE	  = 0x0030,
+	FW_LDST_ADDRSPC_LE        = 0x0030,
 	FW_LDST_ADDRSPC_I2C       = 0x0038,
 	FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
 	FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,
@@ -4665,11 +5776,17 @@ enum fw_caps_config_nic {
 
 enum fw_caps_config_toe {
 	FW_CAPS_CONFIG_TOE		= 0x00000001,
+	FW_CAPS_CONFIG_TOE_SENDPATH = 0x00000002,
 };
 
 enum fw_caps_config_rdma {
 	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
 	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
+	FW_CAPS_CONFIG_RDMA_ROCEV2	= 0x00000004,
+};
+
+enum fw_caps_config_nvme {
+	FW_CAPS_CONFIG_NVME_TCP		= 0x00000001,
 };
 
 enum fw_caps_config_iscsi {
@@ -4687,8 +5804,9 @@ enum fw_caps_config_iscsi {
 enum fw_caps_config_crypto {
 	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
 	FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
-	FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
+	FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,  /* NIC over ipsecofld */
 	FW_CAPS_CONFIG_TLS_HW = 0x00000008,
+	FW_CAPS_CONFIG_OFLD_OVER_IPSEC_INLINE = 0x00000010,/* ofld over ipsecofld */
 };
 
 enum fw_caps_config_fcoe {
@@ -4716,7 +5834,7 @@ struct fw_caps_config_cmd {
 	__be16 nbmcaps;
 	__be16 linkcaps;
 	__be16 switchcaps;
-	__be16 r3;
+	__be16 nvmecaps;
 	__be16 niccaps;
 	__be16 toecaps;
 	__be16 rdmacaps;
@@ -4840,6 +5958,8 @@ enum fw_params_param_dev {
 	FW_PARAMS_PARAM_DEV_DEV_512SGL_MR = 0x30,
 	FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,
 	FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32,
+	FW_PARAMS_PARAM_DEV_TID_QID_SEL_MASK = 0x33,
+	FW_PARAMS_PARAM_DEV_TX_TPCHMAP	= 0x3A,
 };
 
 /*
@@ -4911,6 +6031,8 @@ enum fw_params_param_pfvf {
 	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
 	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
 	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
+	/* no separate STAG/PBL START/END for nvmet.
+	 * use same rdma stag/pbl memory range */
 	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
 	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
 	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
@@ -4943,7 +6065,7 @@ enum fw_params_param_pfvf {
 	FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
 	FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
 	FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
-        FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
+	FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
 	FW_PARAMS_PARAM_PFVF_RAWF_START	= 0x36,
 	FW_PARAMS_PARAM_PFVF_RAWF_END	= 0x37,
 	FW_PARAMS_PARAM_PFVF_RSSKEYINFO	= 0x38,
@@ -4955,6 +6077,13 @@ enum fw_params_param_pfvf {
 	FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
 	FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
 	FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
+	FW_PARAMS_PARAM_PFVF_RRQ_START = 0x41,
+	FW_PARAMS_PARAM_PFVF_RRQ_END = 0x42,
+	FW_PARAMS_PARAM_PFVF_PKTHDR_START = 0x43,
+	FW_PARAMS_PARAM_PFVF_PKTHDR_END = 0x44,
+	FW_PARAMS_PARAM_PFVF_NIPSEC_TUNNEL = 0x45,
+	FW_PARAMS_PARAM_PFVF_NIPSEC_TRANSPORT = 0x46,
+	FW_PARAMS_PARAM_PFVF_OFLD_NIPSEC_TUNNEL = 0x47,
 };
 
 /*
@@ -4984,6 +6113,19 @@ enum fw_params_param_dmaq {
 	FW_PARAMS_PARAM_DMAQ_FLM_DCA	= 0x30
 };
 
+#define S_T7_DMAQ_CONM_CTXT_CNGTPMODE 0
+#define M_T7_DMAQ_CONM_CTXT_CNGTPMODE 0x3
+#define V_T7_DMAQ_CONM_CTXT_CNGTPMODE(x)  ((x) << S_T7_DMAQ_CONM_CTXT_CNGTPMODE)
+#define G_T7_DMAQ_CONM_CTXT_CNGTPMODE(x)  \
+	(((x) >> S_T7_DMAQ_CONM_CTXT_CNGTPMODE) & M_T7_DMAQ_CONM_CTXT_CNGTPMODE)
+
+#define S_T7_DMAQ_CONM_CTXT_CH_VEC 2
+#define M_T7_DMAQ_CONM_CTXT_CH_VEC 0xf
+#define V_T7_DMAQ_CONM_CTXT_CH_VEC(x)  ((x) << S_T7_DMAQ_CONM_CTXT_CH_VEC)
+#define G_T7_DMAQ_CONM_CTXT_CH_VEC(x)  \
+	(((x) >> S_T7_DMAQ_CONM_CTXT_CH_VEC) & M_T7_DMAQ_CONM_CTXT_CH_VEC)
+
+
 /*
  * chnet parameters
  */
@@ -5199,7 +6341,8 @@ struct fw_pfvf_cmd {
 enum fw_iq_type {
 	FW_IQ_TYPE_FL_INT_CAP,
 	FW_IQ_TYPE_NO_FL_INT_CAP,
-	FW_IQ_TYPE_VF_CQ
+	FW_IQ_TYPE_VF_CQ,
+	FW_IQ_TYPE_CQ,
 };
 
 enum fw_iq_iqtype {
@@ -5787,6 +6930,12 @@ struct fw_eq_mngt_cmd {
     (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
 #define F_FW_EQ_MNGT_CMD_EQSTOP		V_FW_EQ_MNGT_CMD_EQSTOP(1U)
 
+#define S_FW_EQ_MNGT_CMD_COREGROUP	16
+#define M_FW_EQ_MNGT_CMD_COREGROUP	0x3f
+#define V_FW_EQ_MNGT_CMD_COREGROUP(x)	((x) << S_FW_EQ_MNGT_CMD_COREGROUP)
+#define G_FW_EQ_MNGT_CMD_COREGROUP(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_COREGROUP) & M_FW_EQ_MNGT_CMD_COREGROUP)
+
 #define S_FW_EQ_MNGT_CMD_CMPLIQID	20
 #define M_FW_EQ_MNGT_CMD_CMPLIQID	0xfff
 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x)	((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
@@ -5977,6 +7126,12 @@ struct fw_eq_eth_cmd {
     (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
 #define F_FW_EQ_ETH_CMD_EQSTOP		V_FW_EQ_ETH_CMD_EQSTOP(1U)
 
+#define S_FW_EQ_ETH_CMD_COREGROUP	16
+#define M_FW_EQ_ETH_CMD_COREGROUP	0x3f
+#define V_FW_EQ_ETH_CMD_COREGROUP(x)	((x) << S_FW_EQ_ETH_CMD_COREGROUP)
+#define G_FW_EQ_ETH_CMD_COREGROUP(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_COREGROUP) & M_FW_EQ_ETH_CMD_COREGROUP)
+
 #define S_FW_EQ_ETH_CMD_EQID		0
 #define M_FW_EQ_ETH_CMD_EQID		0xfffff
 #define V_FW_EQ_ETH_CMD_EQID(x)		((x) << S_FW_EQ_ETH_CMD_EQID)
@@ -6190,6 +7345,12 @@ struct fw_eq_ctrl_cmd {
     (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
 #define F_FW_EQ_CTRL_CMD_EQSTOP		V_FW_EQ_CTRL_CMD_EQSTOP(1U)
 
+#define S_FW_EQ_CTRL_CMD_COREGROUP	16
+#define M_FW_EQ_CTRL_CMD_COREGROUP	0x3f
+#define V_FW_EQ_CTRL_CMD_COREGROUP(x)	((x) << S_FW_EQ_CTRL_CMD_COREGROUP)
+#define G_FW_EQ_CTRL_CMD_COREGROUP(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_COREGROUP) & M_FW_EQ_CTRL_CMD_COREGROUP)
+
 #define S_FW_EQ_CTRL_CMD_CMPLIQID	20
 #define M_FW_EQ_CTRL_CMD_CMPLIQID	0xfff
 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x)	((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
@@ -6377,6 +7538,12 @@ struct fw_eq_ofld_cmd {
     (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
 #define F_FW_EQ_OFLD_CMD_EQSTOP		V_FW_EQ_OFLD_CMD_EQSTOP(1U)
 
+#define S_FW_EQ_OFLD_CMD_COREGROUP	16
+#define M_FW_EQ_OFLD_CMD_COREGROUP	0x3f
+#define V_FW_EQ_OFLD_CMD_COREGROUP(x)	((x) << S_FW_EQ_OFLD_CMD_COREGROUP)
+#define G_FW_EQ_OFLD_CMD_COREGROUP(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_COREGROUP) & M_FW_EQ_OFLD_CMD_COREGROUP)
+
 #define S_FW_EQ_OFLD_CMD_EQID		0
 #define M_FW_EQ_OFLD_CMD_EQID		0xfffff
 #define V_FW_EQ_OFLD_CMD_EQID(x)	((x) << S_FW_EQ_OFLD_CMD_EQID)
@@ -7285,7 +8452,8 @@ fec_supported(uint32_t caps)
 {
 
 	return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G |
-	    FW_PORT_CAP32_SPEED_100G)) != 0);
+	    FW_PORT_CAP32_SPEED_100G | FW_PORT_CAP32_SPEED_200G |
+	    FW_PORT_CAP32_SPEED_400G)) != 0);
 }
 
 enum fw_port_action {
@@ -7799,6 +8967,8 @@ enum fw_port_type {
 	FW_PORT_TYPE_SFP28	= 20,	/* No, 1, 25G/10G/1G */
 	FW_PORT_TYPE_KR_SFP28	= 21,	/* No, 1, 25G/10G/1G using Backplane */
 	FW_PORT_TYPE_KR_XLAUI	= 22,	/* No, 4, 40G/10G/1G, No AN*/
+	FW_PORT_TYPE_SFP56	= 26,
+	FW_PORT_TYPE_QSFP56	= 27,
 	FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
 };
 
@@ -8862,7 +10032,9 @@ struct fw_devlog_cmd {
 	__u8   r2[7];
 	__be32 memtype_devlog_memaddr16_devlog;
 	__be32 memsize_devlog;
-	__be32 r3[2];
+	__u8   num_devlog;
+	__u8   r3[3];
+	__be32 r4;
 };
 
 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG	28
@@ -9786,6 +10958,45 @@ struct fw_hma_cmd {
 #define G_FW_HMA_CMD_ADDR_SIZE(x)	\
     (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
 
+struct fw_jbof_win_reg_cmd {
+	__be32 op_pkd;
+	__be32 alloc_to_len16;
+	__be32 window_num_pcie_params;
+	__be32 window_size;
+	__be64 bus_addr;
+	__be64 phy_address;
+};
+
+#define S_FW_JBOF_WIN_REG_CMD_ALLOC	31
+#define M_FW_JBOF_WIN_REG_CMD_ALLOC	0x1
+#define V_FW_JBOF_WIN_REG_CMD_ALLOC(x)	((x) << S_FW_JBOF_WIN_REG_CMD_ALLOC)
+#define G_FW_JBOF_WIN_REG_CMD_ALLOC(x)	\
+    (((x) >> S_FW_JBOF_WIN_REG_CMD_ALLOC) & M_FW_JBOF_WIN_REG_CMD_ALLOC)
+#define F_FW_JBOF_WIN_REG_CMD_ALLOC	V_FW_JBOF_WIN_REG_CMD_ALLOC(1U)
+
+#define S_FW_JBOF_WIN_REG_CMD_FREE	30
+#define M_FW_JBOF_WIN_REG_CMD_FREE	0x1
+#define V_FW_JBOF_WIN_REG_CMD_FREE(x)	((x) << S_FW_JBOF_WIN_REG_CMD_FREE)
+#define G_FW_JBOF_WIN_REG_CMD_FREE(x)	\
+    (((x) >> S_FW_JBOF_WIN_REG_CMD_FREE) & M_FW_JBOF_WIN_REG_CMD_FREE)
+#define F_FW_JBOF_WIN_REG_CMD_FREE	V_FW_JBOF_WIN_REG_CMD_FREE(1U)
+
+#define S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM	7
+#define M_FW_JBOF_WIN_REG_CMD_WINDOW_NUM	0xf
+#define V_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x)	\
+    ((x) << S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM)
+#define G_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x)	\
+    (((x) >> S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) & \
+     M_FW_JBOF_WIN_REG_CMD_WINDOW_NUM)
+
+#define S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS	0
+#define M_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS	0x7f
+#define V_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x)	\
+    ((x) << S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS)
+#define G_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x)	\
+    (((x) >> S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) & \
+     M_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS)
+
 /******************************************************************************
  *   P C I E   F W   R E G I S T E R
  **************************************/
@@ -9914,8 +11125,15 @@ enum pcie_fw_eval {
  */
 #define PCIE_FW_PF_DEVLOG		7
 
+#define S_PCIE_FW_PF_DEVLOG_COUNT_MSB	31
+#define M_PCIE_FW_PF_DEVLOG_COUNT_MSB	0x1
+#define V_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \
+	((x) << S_PCIE_FW_PF_DEVLOG_COUNT_MSB)
+#define G_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \
+	(((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_MSB) & M_PCIE_FW_PF_DEVLOG_COUNT_MSB)
+
 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128	28
-#define M_PCIE_FW_PF_DEVLOG_NENTRIES128	0xf
+#define M_PCIE_FW_PF_DEVLOG_NENTRIES128	0x7
 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
 	((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
@@ -9928,8 +11146,15 @@ enum pcie_fw_eval {
 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
 	(((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
 
+#define S_PCIE_FW_PF_DEVLOG_COUNT_LSB	3
+#define M_PCIE_FW_PF_DEVLOG_COUNT_LSB	0x1
+#define V_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \
+	((x) << S_PCIE_FW_PF_DEVLOG_COUNT_LSB)
+#define G_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \
+	(((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_LSB) & M_PCIE_FW_PF_DEVLOG_COUNT_LSB)
+
 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE	0
-#define M_PCIE_FW_PF_DEVLOG_MEMTYPE	0xf
+#define M_PCIE_FW_PF_DEVLOG_MEMTYPE	0x7
 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x)	((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
 	(((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
@@ -9969,7 +11194,8 @@ struct fw_hdr {
 enum fw_hdr_chip {
 	FW_HDR_CHIP_T4,
 	FW_HDR_CHIP_T5,
-	FW_HDR_CHIP_T6
+	FW_HDR_CHIP_T6,
+	FW_HDR_CHIP_T7
 };
 
 #define S_FW_HDR_FW_VER_MAJOR	24
@@ -10015,6 +11241,11 @@ enum {
 	T6FW_VERSION_MINOR	= 27,
 	T6FW_VERSION_MICRO	= 5,
 	T6FW_VERSION_BUILD	= 0,
+
+	T7FW_VERSION_MAJOR	= 2,
+	T7FW_VERSION_MINOR	= 0,
+	T7FW_VERSION_MICRO	= 0,
+	T7FW_VERSION_BUILD	= 0,
 };
 
 enum {
@@ -10050,6 +11281,17 @@ enum {
 	T6FW_HDR_INTFVER_ISCSI	= 0x00,
 	T6FW_HDR_INTFVER_FCOEPDU= 0x00,
 	T6FW_HDR_INTFVER_FCOE	= 0x00,
+
+	/* T7
+	 */
+	T7FW_HDR_INTFVER_NIC	= 0x00,
+	T7FW_HDR_INTFVER_VNIC	= 0x00,
+	T7FW_HDR_INTFVER_OFLD	= 0x00,
+	T7FW_HDR_INTFVER_RI	= 0x00,
+	T7FW_HDR_INTFVER_ISCSIPDU= 0x00,
+	T7FW_HDR_INTFVER_ISCSI	= 0x00,
+	T7FW_HDR_INTFVER_FCOEPDU= 0x00,
+	T7FW_HDR_INTFVER_FCOE	= 0x00,
 };
 
 #define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \
@@ -10085,7 +11327,7 @@ struct fw_ephy_hdr {
 enum {
 	FW_EPHY_HDR_MAGIC	= 0x65706879,
 };
-	
+
 struct fw_ifconf_dhcp_info {
 	__be32		addr;
 	__be32		mask;
diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg.txt b/sys/dev/cxgbe/firmware/t7fw_cfg.txt
new file mode 100644
index 000000000000..499af3675bd9
--- /dev/null
+++ b/sys/dev/cxgbe/firmware/t7fw_cfg.txt
@@ -0,0 +1,644 @@
+# Chelsio T6 Factory Default configuration file.
+#
+# Copyright (C) 2014-2015 Chelsio Communications.  All rights reserved.
+#
+#   DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES.  MODIFICATION OF THIS FILE
+#   WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
+#   TO ADAPTERS.
+
+
+# This file provides the default, power-on configuration for 2-port T6-based
+# adapters shipped from the factory.  These defaults are designed to address
+# the needs of the vast majority of Terminator customers.  The basic idea is to
+# have a default configuration which allows a customer to plug a Terminator
+# adapter in and have it work regardless of OS, driver or application except in
+# the most unusual and/or demanding customer applications.
+#
+# Many of the Terminator resources which are described by this configuration
+# are finite.  This requires balancing the configuration/operation needs of
+# device drivers across OSes and a large number of customer application.
+#
+# Some of the more important resources to allocate and their constaints are:
+#  1. Virtual Interfaces: 256.
+#  2. Ingress Queues with Free Lists: 1024.
+#  3. Egress Queues: 128K.
+#  4. MSI-X Vectors: 1088.
+#  5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
+#     address matching on Ingress Packets.
+#
+# Some of the important OS/Driver resource needs are:
+#  6. Some OS Drivers will manage all resources through a single Physical
+#     Function (currently PF4 but it could be any Physical Function).
+#  7. Some OS Drivers will manage different ports and functions (NIC,
+#     storage, etc.) on different Physical Functions.  For example, NIC
+#     functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
+#
+# Some of the customer application needs which need to be accommodated:
+#  8. Some customers will want to support large CPU count systems with
+#     good scaling.  Thus, we'll need to accommodate a number of
+#     Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
+#     to be involved per port and per application function.  For example,
+#     in the case where all ports and application functions will be
+#     managed via a single Unified PF and we want to accommodate scaling up
+#     to 8 CPUs, we would want:
+#
+#         2 ports *
+#         3 application functions (NIC, FCoE, iSCSI) per port *
+#         16 Ingress Queue/MSI-X Vectors per application function
+#
+#     for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
+#     (Plus a few for Firmware Event Queues, etc.)
+#
+#  9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
+#     Machines to directly access T6 functionality via SR-IOV Virtual Functions
+#     and "PCI Device Passthrough" -- this is especially true for the NIC
+#     application functionality.
+#
+
+
+# Global configuration settings.
+#
+[global]
+	rss_glb_config_mode = basicvirtual
+	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
+
+	# PL_TIMEOUT register
+	pl_timeout_value = 200		# the timeout value in units of us
+
+	# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
+	# Page Size and a 64B L1 Cache Line Size. It programs the
+	# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
+	# If a Master PF Driver finds itself on a machine with different
+	# parameters, then the Master PF Driver is responsible for initializing
+	# these parameters to appropriate values.
+	#
+	# Notes:
+	#  1. The Free List Buffer Sizes below are raw and the firmware will
+	#     round them up to the Ingress Padding Boundary.
+	#  2. The SGE Timer Values below are expressed below in microseconds.
+	#     The firmware will convert these values to Core Clock Ticks when
+	#     it processes the configuration parameters.
+	#
+	reg[0x1008] = 0x40810/0x21c70	# SGE_CONTROL
+	reg[0x100c] = 0x22222222	# SGE_HOST_PAGE_SIZE
+	reg[0x10a0] = 0x01040810	# SGE_INGRESS_RX_THRESHOLD
+	reg[0x1044] = 4096		# SGE_FL_BUFFER_SIZE0
+	reg[0x1048] = 65536		# SGE_FL_BUFFER_SIZE1
+	reg[0x104c] = 1536		# SGE_FL_BUFFER_SIZE2
+	reg[0x1050] = 9024		# SGE_FL_BUFFER_SIZE3
+	reg[0x1054] = 9216		# SGE_FL_BUFFER_SIZE4
+	reg[0x1058] = 2048		# SGE_FL_BUFFER_SIZE5
+	reg[0x105c] = 128		# SGE_FL_BUFFER_SIZE6
+	reg[0x1060] = 8192		# SGE_FL_BUFFER_SIZE7
+	reg[0x1064] = 16384		# SGE_FL_BUFFER_SIZE8
+	reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
+	reg[0x10a8] = 0x402000/0x402000	# SGE_DOORBELL_CONTROL
+	sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
+	reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
+	reg[0x173c] = 0x2/0x2
+
+	reg[0x1750] = 0x01000000/0x03c00000 # RDMA_INV_Handling = 1
+                                        # terminate_status_en = 0
+                                        # DISABLE = 0
+
+	#DBQ Timer duration = 1 cclk cycle duration * (sge_dbq_timertick+1) * sge_dbq_timer
+	#SGE DBQ tick value. All timers are multiple of this value
+	sge_dbq_timertick = 50 #in usecs
+	sge_dbq_timer = 1, 2, 4, 6, 8, 10, 12, 16
+
+	#CIM_QUEUE_FEATURE_DISABLE.obq_eom_enable bit needs to be set to 1 for CmdMore handling support
+	reg[0x7c4c] = 0x20/0x20
+
+	# enable TP_OUT_CONFIG.IPIDSPLITMODE
+	reg[0x7d04] = 0x00010000/0x00010000
+
+	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
+
+    reg[0x46004] = 0x3/0x3      #Crypto core reset
+
+	#Tick granularities in kbps
+	tsch_ticks = 100000, 10000, 1000, 10
+
+	# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
+	# filter control: compact, fcoemask
+	# server sram   : srvrsram
+	# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
+	#		  protocol, tos, vlan, vnic_id, port, fcoe
+	# valid filterModes are described the Terminator 5 Data Book
+	filterMode = fcoemask, srvrsram, ipsec, rocev2, fragmentation, mpshittype, protocol, vlan, port, fcoe
+
+	# filter tuples enforced in LE active region (equal to or subset of filterMode)
+	filterMask = protocol, ipsec, rocev2, fcoe
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP RX payload
+	tp_pmrx = 30
+
+	# TP RX payload page size
+	tp_pmrx_pagesize = 64K
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP TX payload
+	tp_pmtx = 50
+
+	# TP TX payload page size
+	tp_pmtx_pagesize = 64K
+
+	# TP OFLD MTUs
+	tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
+
+	# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
+	reg[0x7d04] = 0x00010008/0x00010008
+
+	# TP_GLOBAL_CONFIG
+	reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
+
+	# TP_PC_CONFIG
+	reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
+
+	# TP_PARA_REG0
+	reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
+
+	# ULPRX iSCSI Page Sizes
+	reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
+
+	# LE_DB_CONFIG
+	reg[0x19c04] = 0x00400000/0x00440000 # LE Server SRAM Enable, 
+					     # LE IPv4 compression disabled 
+	# LE_DB_HASH_CONFIG
+	reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 
+
+	# ULP_TX_CONFIG
+	reg[0x8dc0] = 0x00000104/0x02000104 # Enable ITT on PI err
+					    # Enable more error msg for ...
+					    # TPT error.
+						# Err2uP = 0
+
+	#ULP_RX_CTL1
+	reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3
+	                                     # ROCE_Invld_Msg_Dis = 3
+
+	#Enable iscsi completion moderation feature, disable rdma invlidate in ulptx
+	reg[0x1925c] = 0x000041c0/0x000031d0	# Enable offset decrement after
+						# PI extraction and before DDP.
+						# ulp insert pi source info in
+						# DIF.
+						# Enable iscsi hdr cmd mode.
+						# iscsi force cmd mode.
+						# Enable iscsi cmp mode.
+						# terminate_status_en = 0
+
+	#ULP_RX_CQE_GEN_EN
+	reg[0x19250] = 0x0/0x3   # Termimate_msg = 0
+	                         # Terminate_with_err = 0
+
+	gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
+				    # 2 - disable gc for mc1/hma enable mc0,
+				    # 1 - enable gc for mc1/hma disable mc0,
+				    # 0 - enable gc for mc1/hma and for mc0,
+				    # default gc enabled.
+
+	# HMA configuration (uncomment following lines to enable HMA)
+	hma_size = 92 			# Size (in MBs) of host memory expected
+	hma_regions = 	iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq	# What all regions to place in host memory
+
+    #mc[0]=0
+    #mc[1]=0
+
+# Some "definitions" to make the rest of this a bit more readable.  We support
+# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
+# per function per port ...
+#
+# NMSIX = 1088			# available MSI-X Vectors
+# NVI = 256			# available Virtual Interfaces
+# NMPSTCAM = 336		# MPS TCAM entries
+#
+# NPORTS = 2			# ports
+# NCPUS = 16			# CPUs we want to support scalably
+# NFUNCS = 3			# functions per port (NIC, FCoE, iSCSI)
+
+# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
+# PF" which many OS Drivers will use to manage most or all functions.
+#
+# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
+# use Forwarded Interrupt Ingress Queues.  For these latter, an Ingress Queue
+# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
+# will be specified as the "Ingress Queue Asynchronous Destination Index."
+# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
+# than or equal to the number of Ingress Queues ...
+#
+# NVI_NIC = 4			# NIC access to NPORTS
+# NFLIQ_NIC = 32		# NIC Ingress Queues with Free Lists
+# NETHCTRL_NIC = 32		# NIC Ethernet Control/TX Queues
+# NEQ_NIC = 64			# NIC Egress Queues (FL, ETHCTRL/TX)
+# NMPSTCAM_NIC = 16		# NIC MPS TCAM Entries (NPORTS*4)
+# NMSIX_NIC = 32		# NIC MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_OFLD = 0			# Offload uses NIC function to access ports
+# NFLIQ_OFLD = 16		# Offload Ingress Queues with Free Lists
+# NETHCTRL_OFLD = 0		# Offload Ethernet Control/TX Queues
+# NEQ_OFLD = 16			# Offload Egress Queues (FL)
+# NMPSTCAM_OFLD = 0		# Offload MPS TCAM Entries (uses NIC's)
+# NMSIX_OFLD = 16		# Offload MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_RDMA = 0			# RDMA uses NIC function to access ports
+# NFLIQ_RDMA = 4		# RDMA Ingress Queues with Free Lists
+# NETHCTRL_RDMA = 0		# RDMA Ethernet Control/TX Queues
+# NEQ_RDMA = 4			# RDMA Egress Queues (FL)
+# NMPSTCAM_RDMA = 0		# RDMA MPS TCAM Entries (uses NIC's)
+# NMSIX_RDMA = 4		# RDMA MSI-X Interrupt Vectors (FLIQ)
+#
+# NEQ_WD = 128			# Wire Direct TX Queues and FLs
+# NETHCTRL_WD = 64		# Wire Direct TX Queues
+# NFLIQ_WD = 64	`		# Wire Direct Ingress Queues with Free Lists
+#
+# NVI_ISCSI = 4			# ISCSI access to NPORTS
+# NFLIQ_ISCSI = 4		# ISCSI Ingress Queues with Free Lists
+# NETHCTRL_ISCSI = 0		# ISCSI Ethernet Control/TX Queues
+# NEQ_ISCSI = 4			# ISCSI Egress Queues (FL)
+# NMPSTCAM_ISCSI = 4		# ISCSI MPS TCAM Entries (NPORTS)
+# NMSIX_ISCSI = 4		# ISCSI MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_FCOE = 4			# FCOE access to NPORTS
+# NFLIQ_FCOE = 34		# FCOE Ingress Queues with Free Lists
+# NETHCTRL_FCOE = 32		# FCOE Ethernet Control/TX Queues
+# NEQ_FCOE = 66			# FCOE Egress Queues (FL)
+# NMPSTCAM_FCOE = 32 		# FCOE MPS TCAM Entries (NPORTS)
+# NMSIX_FCOE = 34		# FCOE MSI-X Interrupt Vectors (FLIQ)
+
+# Two extra Ingress Queues per function for Firmware Events and Forwarded
+# Interrupts, and two extra interrupts per function for Firmware Events (or a
+# Forwarded Interrupt Queue) and General Interrupts per function.
+#
+# NFLIQ_EXTRA = 6		# "extra" Ingress Queues 2*NFUNCS (Firmware and
+# 				#   Forwarded Interrupts
+# NMSIX_EXTRA = 6		# extra interrupts 2*NFUNCS (Firmware and
+# 				#   General Interrupts
+
+# Microsoft HyperV resources.  The HyperV Virtual Ingress Queues will have
+# their interrupts forwarded to another set of Forwarded Interrupt Queues.
+#
+# NVI_HYPERV = 16		# VMs we want to support
+# NVIIQ_HYPERV = 2		# Virtual Ingress Queues with Free Lists per VM
+# NFLIQ_HYPERV = 40		# VIQs + NCPUS Forwarded Interrupt Queues
+# NEQ_HYPERV = 32		# VIQs Free Lists
+# NMPSTCAM_HYPERV = 16		# MPS TCAM Entries (NVI_HYPERV)
+# NMSIX_HYPERV = 8		# NCPUS Forwarded Interrupt Queues
+
+# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
+# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
+#
+# NVI_UNIFIED = 28
+# NFLIQ_UNIFIED = 106
+# NETHCTRL_UNIFIED = 32
+# NEQ_UNIFIED = 124
+# NMPSTCAM_UNIFIED = 40
+#
+# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
+# that up to 128 to make sure the Unified PF doesn't run out of resources.
+#
+# NMSIX_UNIFIED = 128
+#
+# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
+# which is 34 but they're probably safe with 32.
+#
+# NMSIX_STORAGE = 32
+
+# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
+# associated with it.  Thus, the MSI-X Vector allocations we give to the
+# UnifiedPF aren't inherited by any Virtual Functions.  As a result we can
+# provision many more Virtual Functions than we can if the UnifiedPF were
+# one of PF0-1.
+#
+
+# All of the below PCI-E parameters are actually stored in various *_init.txt
+# files.  We include them below essentially as comments.
+#
+# For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated
+# ports 0-1.
+#
+# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
+#
+# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
+# storage applications across all four possible ports.
+#
+# Additionally, since the UnifiedPF isn't one of the per-port Physical
+# Functions, we give the UnifiedPF and the PF0-1 Physical Functions
+# different PCI Device IDs which will allow Unified and Per-Port Drivers
+# to directly select the type of Physical Function to which they wish to be
+# attached.
+#
+# Note that the actual values used for the PCI-E Intelectual Property will be
+# 1 less than those below since that's the way it "counts" things.  For
+# readability, we use the number we actually mean ...
+#
+# PF0_INT = 8			# NCPUS
+# PF1_INT = 8			# NCPUS
+# PF0_3_INT = 32		# PF0_INT + PF1_INT + PF2_INT + PF3_INT
+#
+# PF4_INT = 128			# NMSIX_UNIFIED
+# PF5_INT = 32			# NMSIX_STORAGE
+# PF6_INT = 32			# NMSIX_STORAGE
+# PF7_INT = 0			# Nothing Assigned
+# PF4_7_INT = 192		# PF4_INT + PF5_INT + PF6_INT + PF7_INT
+#
+# PF0_7_INT = 224		# PF0_3_INT + PF4_7_INT
+#
+# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
+# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
+#
+# NVF = 16
+
+
+# For those OSes which manage different ports on different PFs, we need
+# only enough resources to support a single port's NIC application functions
+# on PF0-3.  The below assumes that we're only doing NIC with NCPUS "Queue
+# Sets" for ports 0-3.  The FCoE and iSCSI functions for such OSes will be
+# managed on the "storage PFs" (see below).
+#
+
+[function "0"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port
+
+
+[function "1"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port
+
+[function "2"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	#pmask = 0x4		# access to only one port
+	pmask = 0x1		# access to only one port
+
+[function "3"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	#pmask = 0x2		# access to only one port
+
+# Some OS Drivers manage all application functions for all ports via PF4.
+# Thus we need to provide a large number of resources here.  For Egress
+# Queues we need to account for both TX Queues as well as Free List Queues
+# (because the host is responsible for producing Free List Buffers for the
+# hardware to consume).
+#
+
+[function "4"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 28		# NVI_UNIFIED
+	niqflint = 170		# NFLIQ_UNIFIED + NLFIQ_WD
+	nethctrl = 224 		# NETHCTRL_UNIFIED + NETHCTRL_WD
+	neq = 252		# NEQ_UNIFIED + NEQ_WD
+	nqpcq = 12288
+	nexactf = 40		# NMPSTCAM_UNIFIED
+	nrawf = 4
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nethofld = 1024		# number of user mode ethernet flow contexts
+	ncrypto_lookaside = 32
+	nclip = 320		# number of clip region entries
+	nfilter = 480		# number of filter region entries
+	nserver = 480		# number of server region entries
+	nhash = 12288		# number of hash region entries
+	nhpfilter = 64		# number of high priority filter region entries
+	#protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath
+	protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp
+	tp_l2t = 3072
+	tp_ddp = 2
+	tp_ddp_iscsi = 2
+	tp_tls_key = 3
+	tp_tls_mxrxsize = 33792    # 32768 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes
+	tp_stag = 2
+	tp_pbl = 5
+	tp_rq = 7
+	tp_rrq = 4
+	tp_srq = 128
+	nipsec_tunnel16 = 64	# in unit of 16
+	nipsec_transport16 = 191 # in unit of 16
+
+
+# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
+# need to have Virtual Interfaces on each of the four ports with up to NCPUS
+# "Queue Sets" each.
+#
+[function "5"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nexactf = 16		# (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nserver = 16
+	nhash = 1536
+	tp_l2t = 508
+	protocol = iscsi_initiator_fofld
+	tp_ddp_iscsi = 2
+	iscsi_ntask = 2048
+	iscsi_nsess = 2048
+	iscsi_nconn_per_session = 1
+	iscsi_ninitiator_instance = 64
+
+[function "6"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 66		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
+	nexactf = 32		# NPORTS + adding 28 exact entries for FCoE
+				# which is OK since < MIN(SUM PF0..3, PF4)
+				# and we never load PF0..3 and PF4 concurrently
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nhash = 1536
+	tp_l2t = 4
+	protocol = fcoe_initiator
+	tp_ddp = 1
+	fcoe_nfcf = 16
+	fcoe_nvnp = 32
+	fcoe_nssn = 1024
+
+# Following function 7 is used by embedded ARM to communicate to
+# the firmware.
+[function "7"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NVI_UNIFIED
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nexactf = 8		# NPORTS + DCBX +
+	nfilter = 16		# number of filter region entries
+	#nhpfilter = 16		# number of high priority filter region entries
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nserver = 16
+	nhash = 1024
+	tp_l2t = 512
+	protocol = nic_vm, ofld, rddp, rdmac, tlskeys, ipsec_inline, rocev2, nvme_tcp
+
+# The following function, 1023, is not an actual PCIE function but is used to
+# configure and reserve firmware internal resources that come from the global
+# resource pool.
+#
+[function "1023"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NVI_UNIFIED
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nexactf = 8		# NPORTS + DCBX +
+	nfilter = 16		# number of filter region entries
+	#nhpfilter = 0		# number of high priority filter region entries
+
+
+# For Virtual functions, we only allow NIC functionality and we only allow
+# access to one port (1 << PF).  Note that because of limitations in the
+# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
+# and GTS registers, the number of Ingress and Egress Queues must be a power
+# of 2.
+#
+[function "0/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port ...
+
+
+[function "1/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port ...
+
+[function "2/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port ...
+
+
+[function "3/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port ...
+
+# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
+# for packets from the wire as well as the loopback path of the L2 switch. The
+# folling params control how the buffer memory is distributed and the L2 flow
+# control settings:
+#
+# bg_mem:	%-age of mem to use for port/buffer group
+# lpbk_mem:	%-age of port/bg mem to use for loopback
+# hwm:		high watermark; bytes available when starting to send pause
+#		frames (in units of 0.1 MTU)
+# lwm:		low watermark; bytes remaining when sending 'unpause' frame
+#		(in inuits of 0.1 MTU)
+# dwm:		minimum delta between high and low watermark (in units of 100
+#		Bytes)
+#
+[port "0"]
+	#dcb = ppp, dcbx, b2b	# configure for DCB PPP and enable DCBX offload
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+
+[port "1"]
+	#dcb = ppp, dcbx, b2b
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+[port "2"]
+	#dcb = ppp, dcbx, b2b	# configure for DCB PPP and enable DCBX offload
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+
+[port "3"]
+	#dcb = ppp, dcbx, b2b
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+[fini]
+	version = 0x1425001d
+	checksum = 0x684e23fb
+
+# Total resources used by above allocations:
+#   Virtual Interfaces: 104
+#   Ingress Queues/w Free Lists and Interrupts: 526
+#   Egress Queues: 702
+#   MPS TCAM Entries: 336
+#   MSI-X Vectors: 736
+#   Virtual Functions: 64
diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg_fpga.txt b/sys/dev/cxgbe/firmware/t7fw_cfg_fpga.txt
new file mode 100644
index 000000000000..f06f059f4112
--- /dev/null
+++ b/sys/dev/cxgbe/firmware/t7fw_cfg_fpga.txt
@@ -0,0 +1,530 @@
+# Chelsio T6 Factory Default configuration file.
+#
+# Copyright (C) 2014-2015 Chelsio Communications.  All rights reserved.
+#
+#   DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES.  MODIFICATION OF THIS FILE
+#   WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
+#   TO ADAPTERS.
+
+
+# This file provides the default, power-on configuration for 2-port T6-based
+# adapters shipped from the factory.  These defaults are designed to address
+# the needs of the vast majority of Terminator customers.  The basic idea is to
+# have a default configuration which allows a customer to plug a Terminator
+# adapter in and have it work regardless of OS, driver or application except in
+# the most unusual and/or demanding customer applications.
+#
+# Many of the Terminator resources which are described by this configuration
+# are finite.  This requires balancing the configuration/operation needs of
+# device drivers across OSes and a large number of customer application.
+#
+# Some of the more important resources to allocate and their constaints are:
+#  1. Virtual Interfaces: 256.
+#  2. Ingress Queues with Free Lists: 1024.
+#  3. Egress Queues: 128K.
+#  4. MSI-X Vectors: 1088.
+#  5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
+#     address matching on Ingress Packets.
+#
+# Some of the important OS/Driver resource needs are:
+#  6. Some OS Drivers will manage all resources through a single Physical
+#     Function (currently PF4 but it could be any Physical Function).
+#  7. Some OS Drivers will manage different ports and functions (NIC,
+#     storage, etc.) on different Physical Functions.  For example, NIC
+#     functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
+#
+# Some of the customer application needs which need to be accommodated:
+#  8. Some customers will want to support large CPU count systems with
+#     good scaling.  Thus, we'll need to accommodate a number of
+#     Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
+#     to be involved per port and per application function.  For example,
+#     in the case where all ports and application functions will be
+#     managed via a single Unified PF and we want to accommodate scaling up
+#     to 8 CPUs, we would want:
+#
+#         2 ports *
+#         3 application functions (NIC, FCoE, iSCSI) per port *
+#         16 Ingress Queue/MSI-X Vectors per application function
+#
+#     for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
+#     (Plus a few for Firmware Event Queues, etc.)
+#
+#  9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
+#     Machines to directly access T6 functionality via SR-IOV Virtual Functions
+#     and "PCI Device Passthrough" -- this is especially true for the NIC
+#     application functionality.
+#
+
+
+# Global configuration settings.
+#
+[global]
+	rss_glb_config_mode = basicvirtual
+	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
+
+	# PL_TIMEOUT register
+	pl_timeout_value = 1000		# the timeout value in units of us
+
+	# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
+	# Page Size and a 64B L1 Cache Line Size. It programs the
+	# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
+	# If a Master PF Driver finds itself on a machine with different
+	# parameters, then the Master PF Driver is responsible for initializing
+	# these parameters to appropriate values.
+	#
+	# Notes:
+	#  1. The Free List Buffer Sizes below are raw and the firmware will
+	#     round them up to the Ingress Padding Boundary.
+	#  2. The SGE Timer Values below are expressed below in microseconds.
+	#     The firmware will convert these values to Core Clock Ticks when
+	#     it processes the configuration parameters.
+	#
+	reg[0x1008] = 0x40810/0x21c70	# SGE_CONTROL
+	reg[0x100c] = 0x22222222	# SGE_HOST_PAGE_SIZE
+	reg[0x10a0] = 0x01040810	# SGE_INGRESS_RX_THRESHOLD
+	reg[0x1044] = 4096		# SGE_FL_BUFFER_SIZE0
+	reg[0x1048] = 65536		# SGE_FL_BUFFER_SIZE1
+	reg[0x104c] = 1536		# SGE_FL_BUFFER_SIZE2
+	reg[0x1050] = 9024		# SGE_FL_BUFFER_SIZE3
+	reg[0x1054] = 9216		# SGE_FL_BUFFER_SIZE4
+	reg[0x1058] = 2048		# SGE_FL_BUFFER_SIZE5
+	reg[0x105c] = 128		# SGE_FL_BUFFER_SIZE6
+	reg[0x1060] = 8192		# SGE_FL_BUFFER_SIZE7
+	reg[0x1064] = 16384		# SGE_FL_BUFFER_SIZE8
+	reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
+	reg[0x10a8] = 0x402000/0x402000	# SGE_DOORBELL_CONTROL
+	sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
+	reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
+	reg[0x173c] = 0x2/0x2
+
+	reg[0x1750] = 0x01000000/0x03c00000 # RDMA_INV_Handling = 1
+                                        # terminate_status_en = 0
+                                        # DISABLE = 0
+
+	#DBQ Timer duration = 1 cclk cycle duration * (sge_dbq_timertick+1) * sge_dbq_timer
+	#SGE DBQ tick value. All timers are multiple of this value
+	sge_dbq_timertick = 1 #in usecs
+	sge_dbq_timer = 1, 2, 4, 6, 8, 10, 12, 16
+	# enable TP_OUT_CONFIG.IPIDSPLITMODE
+	reg[0x7d04] = 0x00010000/0x00010000
+
+	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
+
+	reg[0x46004] = 0x3/0x3	# Crypto core reset
+    reg[0x46000] = 0xa/0xe  # 16K ESH Hi Extraction window
+
+	#Tick granularities in kbps
+	tsch_ticks = 1000, 100, 10, 1
+
+	# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
+	# filter control: compact, fcoemask
+	# server sram   : srvrsram
+	# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
+	#		  protocol, tos, vlan, vnic_id, port, fcoe
+	# valid filterModes are described the Terminator 5 Data Book
+	filterMode = fcoemask, srvrsram, ipsec, rocev2, fragmentation, mpshittype, protocol, vlan, port, fcoe
+
+	# filter tuples enforced in LE active region (equal to or subset of filterMode)
+	filterMask = protocol, ipsec, rocev2, fcoe
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP RX payload
+	tp_pmrx = 30
+
+	# TP RX payload page size
+	tp_pmrx_pagesize = 64K
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP TX payload
+	tp_pmtx = 50
+
+	# TP TX payload page size
+	tp_pmtx_pagesize = 64K
+
+	# TP OFLD MTUs
+	tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
+
+	# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
+	reg[0x7d04] = 0x00010008/0x00010008
+
+	# TP_GLOBAL_CONFIG
+	reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
+
+	# TP_PC_CONFIG
+	reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
+
+	# TP_PARA_REG0
+	reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
+
+	# ULPRX iSCSI Page Sizes
+	reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
+
+	# LE_DB_CONFIG
+	reg[0x19c04] = 0x00400000/0x00440000 # LE Server SRAM Enable, 
+					     # LE IPv4 compression disabled 
+	# LE_DB_HASH_CONFIG
+	reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 
+
+	# ULP_TX_CONFIG
+	reg[0x8dc0] = 0x00000104/0x02000104 # Enable ITT on PI err
+					    # Enable more error msg for ...
+					    # TPT error.
+						# Err2uP = 0
+
+	#ULP_RX_CTL1
+	reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3
+	                                     # ROCE_Invld_Msg_Dis = 3
+
+	#Enable iscsi completion moderation feature, disable rdma invlidate in ulptx
+	reg[0x1925c] = 0x000041c0/0x000031d0	# Enable offset decrement after
+						# PI extraction and before DDP.
+						# ulp insert pi source info in
+						# DIF.
+						# Enable iscsi hdr cmd mode.
+						# iscsi force cmd mode.
+						# Enable iscsi cmp mode.
+						# terminate_status_en = 0
+
+	#ULP_RX_CQE_GEN_EN
+	reg[0x19250] = 0x0/0x3   # Termimate_msg = 0
+	                         # Terminate_with_err = 0
+
+	#gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
+				    # 2 - disable gc for mc1/hma enable mc0,
+				    # 1 - enable gc for mc1/hma disable mc0,
+				    # 0 - enable gc for mc1/hma and for mc0,
+				    # default gc enabled.
+
+	# HMA configuration (uncomment following lines to enable HMA)
+	hma_size = 92 			# Size (in MBs) of host memory expected
+	hma_regions = 	iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq	# What all regions to place in host memory
+
+    #mc[0]=0
+    #mc[1]=0
+
+# Some "definitions" to make the rest of this a bit more readable.  We support
+# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
+# per function per port ...
+#
+# NMSIX = 1088			# available MSI-X Vectors
+# NVI = 256			# available Virtual Interfaces
+# NMPSTCAM = 336		# MPS TCAM entries
+#
+# NPORTS = 2			# ports
+# NCPUS = 16			# CPUs we want to support scalably
+# NFUNCS = 3			# functions per port (NIC, FCoE, iSCSI)
+
+# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
+# PF" which many OS Drivers will use to manage most or all functions.
+#
+# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
+# use Forwarded Interrupt Ingress Queues.  For these latter, an Ingress Queue
+# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
+# will be specified as the "Ingress Queue Asynchronous Destination Index."
+# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
+# than or equal to the number of Ingress Queues ...
+#
+# NVI_NIC = 4			# NIC access to NPORTS
+# NFLIQ_NIC = 32		# NIC Ingress Queues with Free Lists
+# NETHCTRL_NIC = 32		# NIC Ethernet Control/TX Queues
+# NEQ_NIC = 64			# NIC Egress Queues (FL, ETHCTRL/TX)
+# NMPSTCAM_NIC = 16		# NIC MPS TCAM Entries (NPORTS*4)
+# NMSIX_NIC = 32		# NIC MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_OFLD = 0			# Offload uses NIC function to access ports
+# NFLIQ_OFLD = 16		# Offload Ingress Queues with Free Lists
+# NETHCTRL_OFLD = 0		# Offload Ethernet Control/TX Queues
+# NEQ_OFLD = 16			# Offload Egress Queues (FL)
+# NMPSTCAM_OFLD = 0		# Offload MPS TCAM Entries (uses NIC's)
+# NMSIX_OFLD = 16		# Offload MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_RDMA = 0			# RDMA uses NIC function to access ports
+# NFLIQ_RDMA = 4		# RDMA Ingress Queues with Free Lists
+# NETHCTRL_RDMA = 0		# RDMA Ethernet Control/TX Queues
+# NEQ_RDMA = 4			# RDMA Egress Queues (FL)
+# NMPSTCAM_RDMA = 0		# RDMA MPS TCAM Entries (uses NIC's)
+# NMSIX_RDMA = 4		# RDMA MSI-X Interrupt Vectors (FLIQ)
+#
+# NEQ_WD = 128			# Wire Direct TX Queues and FLs
+# NETHCTRL_WD = 64		# Wire Direct TX Queues
+# NFLIQ_WD = 64	`		# Wire Direct Ingress Queues with Free Lists
+#
+# NVI_ISCSI = 4			# ISCSI access to NPORTS
+# NFLIQ_ISCSI = 4		# ISCSI Ingress Queues with Free Lists
+# NETHCTRL_ISCSI = 0		# ISCSI Ethernet Control/TX Queues
+# NEQ_ISCSI = 4			# ISCSI Egress Queues (FL)
+# NMPSTCAM_ISCSI = 4		# ISCSI MPS TCAM Entries (NPORTS)
+# NMSIX_ISCSI = 4		# ISCSI MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_FCOE = 4			# FCOE access to NPORTS
+# NFLIQ_FCOE = 34		# FCOE Ingress Queues with Free Lists
+# NETHCTRL_FCOE = 32		# FCOE Ethernet Control/TX Queues
+# NEQ_FCOE = 66			# FCOE Egress Queues (FL)
+# NMPSTCAM_FCOE = 32 		# FCOE MPS TCAM Entries (NPORTS)
+# NMSIX_FCOE = 34		# FCOE MSI-X Interrupt Vectors (FLIQ)
+
+# Two extra Ingress Queues per function for Firmware Events and Forwarded
+# Interrupts, and two extra interrupts per function for Firmware Events (or a
+# Forwarded Interrupt Queue) and General Interrupts per function.
+#
+# NFLIQ_EXTRA = 6		# "extra" Ingress Queues 2*NFUNCS (Firmware and
+# 				#   Forwarded Interrupts
+# NMSIX_EXTRA = 6		# extra interrupts 2*NFUNCS (Firmware and
+# 				#   General Interrupts
+
+# Microsoft HyperV resources.  The HyperV Virtual Ingress Queues will have
+# their interrupts forwarded to another set of Forwarded Interrupt Queues.
+#
+# NVI_HYPERV = 16		# VMs we want to support
+# NVIIQ_HYPERV = 2		# Virtual Ingress Queues with Free Lists per VM
+# NFLIQ_HYPERV = 40		# VIQs + NCPUS Forwarded Interrupt Queues
+# NEQ_HYPERV = 32		# VIQs Free Lists
+# NMPSTCAM_HYPERV = 16		# MPS TCAM Entries (NVI_HYPERV)
+# NMSIX_HYPERV = 8		# NCPUS Forwarded Interrupt Queues
+
+# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
+# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
+#
+# NVI_UNIFIED = 28
+# NFLIQ_UNIFIED = 106
+# NETHCTRL_UNIFIED = 32
+# NEQ_UNIFIED = 124
+# NMPSTCAM_UNIFIED = 40
+#
+# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
+# that up to 128 to make sure the Unified PF doesn't run out of resources.
+#
+# NMSIX_UNIFIED = 128
+#
+# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
+# which is 34 but they're probably safe with 32.
+#
+# NMSIX_STORAGE = 32
+
+# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
+# associated with it.  Thus, the MSI-X Vector allocations we give to the
+# UnifiedPF aren't inherited by any Virtual Functions.  As a result we can
+# provision many more Virtual Functions than we can if the UnifiedPF were
+# one of PF0-1.
+#
+
+# All of the below PCI-E parameters are actually stored in various *_init.txt
+# files.  We include them below essentially as comments.
+#
+# For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated
+# ports 0-1.
+#
+# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
+#
+# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
+# storage applications across all four possible ports.
+#
+# Additionally, since the UnifiedPF isn't one of the per-port Physical
+# Functions, we give the UnifiedPF and the PF0-1 Physical Functions
+# different PCI Device IDs which will allow Unified and Per-Port Drivers
+# to directly select the type of Physical Function to which they wish to be
+# attached.
+#
+# Note that the actual values used for the PCI-E Intelectual Property will be
+# 1 less than those below since that's the way it "counts" things.  For
+# readability, we use the number we actually mean ...
+#
+# PF0_INT = 8			# NCPUS
+# PF1_INT = 8			# NCPUS
+# PF0_3_INT = 32		# PF0_INT + PF1_INT + PF2_INT + PF3_INT
+#
+# PF4_INT = 128			# NMSIX_UNIFIED
+# PF5_INT = 32			# NMSIX_STORAGE
+# PF6_INT = 32			# NMSIX_STORAGE
+# PF7_INT = 0			# Nothing Assigned
+# PF4_7_INT = 192		# PF4_INT + PF5_INT + PF6_INT + PF7_INT
+#
+# PF0_7_INT = 224		# PF0_3_INT + PF4_7_INT
+#
+# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
+# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
+#
+# NVF = 16
+
+
+# For those OSes which manage different ports on different PFs, we need
+# only enough resources to support a single port's NIC application functions
+# on PF0-3.  The below assumes that we're only doing NIC with NCPUS "Queue
+# Sets" for ports 0-3.  The FCoE and iSCSI functions for such OSes will be
+# managed on the "storage PFs" (see below).
+#
+
+# Some OS Drivers manage all application functions for all ports via PF4.
+# Thus we need to provide a large number of resources here.  For Egress
+# Queues we need to account for both TX Queues as well as Free List Queues
+# (because the host is responsible for producing Free List Buffers for the
+# hardware to consume).
+#
+[function "0"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 28		# NVI_UNIFIED
+	niqflint = 170		# NFLIQ_UNIFIED + NLFIQ_WD
+	nethctrl = 96 		# NETHCTRL_UNIFIED + NETHCTRL_WD
+	neq = 252		# NEQ_UNIFIED + NEQ_WD
+	nqpcq = 12288
+	nexactf = 40		# NMPSTCAM_UNIFIED
+	nrawf = 4
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nethofld = 1024		# number of user mode ethernet flow contexts
+	ncrypto_lookaside = 32
+	nclip = 32		# number of clip region entries
+	nfilter = 48		# number of filter region entries
+	nserver = 48		# number of server region entries
+	nhash = 12288		# number of hash region entries
+	nhpfilter = 64		# number of high priority filter region entries
+	#protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath
+	protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp
+	tp_l2t = 3072
+	tp_ddp = 2
+	tp_ddp_iscsi = 2
+	tp_tls_key = 3
+	tp_tls_mxrxsize = 33792    # 32768 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes
+	tp_stag = 2
+	tp_pbl = 5
+	tp_rq = 7
+	tp_rrq = 4
+	tp_srq = 128
+	nipsec_tunnel16 = 64	# in unit of 16
+	nipsec_transport16 = 191 # in unit of 16
+
+
+# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
+# need to have Virtual Interfaces on each of the four ports with up to NCPUS
+# "Queue Sets" each.
+#
+[function "1"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nexactf = 16		# (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nserver = 16
+	nhash = 2048
+	tp_l2t = 1020
+	protocol = iscsi_initiator_fofld
+	tp_ddp_iscsi = 2
+	iscsi_ntask = 2048
+	iscsi_nsess = 2048
+	iscsi_nconn_per_session = 1
+	iscsi_ninitiator_instance = 64
+
+
+# The following function, 1023, is not an actual PCIE function but is used to
+# configure and reserve firmware internal resources that come from the global
+# resource pool.
+#
+[function "1023"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NVI_UNIFIED
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nexactf = 8		# NPORTS + DCBX +
+	nfilter = 16		# number of filter region entries
+	#nhpfilter = 0		# number of high priority filter region entries
+
+
+# For Virtual functions, we only allow NIC functionality and we only allow
+# access to one port (1 << PF).  Note that because of limitations in the
+# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
+# and GTS registers, the number of Ingress and Egress Queues must be a power
+# of 2.
+#
+[function "0/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port ...
+
+
+[function "1/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port ...
+
+
+# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
+# for packets from the wire as well as the loopback path of the L2 switch. The
+# folling params control how the buffer memory is distributed and the L2 flow
+# control settings:
+#
+# bg_mem:	%-age of mem to use for port/buffer group
+# lpbk_mem:	%-age of port/bg mem to use for loopback
+# hwm:		high watermark; bytes available when starting to send pause
+#		frames (in units of 0.1 MTU)
+# lwm:		low watermark; bytes remaining when sending 'unpause' frame
+#		(in inuits of 0.1 MTU)
+# dwm:		minimum delta between high and low watermark (in units of 100
+#		Bytes)
+#
+[port "0"]
+	dcb = ppp, dcbx, b2b	# configure for DCB PPP and enable DCBX offload
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+
+[port "1"]
+	dcb = ppp, dcbx, b2b
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+[port "2"]
+	dcb = ppp, dcbx, b2b	# configure for DCB PPP and enable DCBX offload
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+
+[port "3"]
+	dcb = ppp, dcbx, b2b
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+[fini]
+	version = 0x1425001d
+	checksum = 0x22432d98
+
+# Total resources used by above allocations:
+#   Virtual Interfaces: 104
+#   Ingress Queues/w Free Lists and Interrupts: 526
+#   Egress Queues: 702
+#   MPS TCAM Entries: 336
+#   MSI-X Vectors: 736
+#   Virtual Functions: 64
diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt b/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt
new file mode 100644
index 000000000000..0bca1c194af8
--- /dev/null
+++ b/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt
@@ -0,0 +1,644 @@
+# Chelsio T6 Factory Default configuration file.
+#
+# Copyright (C) 2014-2015 Chelsio Communications.  All rights reserved.
+#
+#   DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES.  MODIFICATION OF THIS FILE
+#   WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
+#   TO ADAPTERS.
+
+
+# This file provides the default, power-on configuration for 2-port T6-based
+# adapters shipped from the factory.  These defaults are designed to address
+# the needs of the vast majority of Terminator customers.  The basic idea is to
+# have a default configuration which allows a customer to plug a Terminator
+# adapter in and have it work regardless of OS, driver or application except in
+# the most unusual and/or demanding customer applications.
+#
+# Many of the Terminator resources which are described by this configuration
+# are finite.  This requires balancing the configuration/operation needs of
+# device drivers across OSes and a large number of customer application.
+#
+# Some of the more important resources to allocate and their constaints are:
+#  1. Virtual Interfaces: 256.
+#  2. Ingress Queues with Free Lists: 1024.
+#  3. Egress Queues: 128K.
+#  4. MSI-X Vectors: 1088.
+#  5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
+#     address matching on Ingress Packets.
+#
+# Some of the important OS/Driver resource needs are:
+#  6. Some OS Drivers will manage all resources through a single Physical
+#     Function (currently PF4 but it could be any Physical Function).
+#  7. Some OS Drivers will manage different ports and functions (NIC,
+#     storage, etc.) on different Physical Functions.  For example, NIC
+#     functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
+#
+# Some of the customer application needs which need to be accommodated:
+#  8. Some customers will want to support large CPU count systems with
+#     good scaling.  Thus, we'll need to accommodate a number of
+#     Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
+#     to be involved per port and per application function.  For example,
+#     in the case where all ports and application functions will be
+#     managed via a single Unified PF and we want to accommodate scaling up
+#     to 8 CPUs, we would want:
+#
+#         2 ports *
+#         3 application functions (NIC, FCoE, iSCSI) per port *
+#         16 Ingress Queue/MSI-X Vectors per application function
+#
+#     for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
+#     (Plus a few for Firmware Event Queues, etc.)
+#
+#  9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
+#     Machines to directly access T6 functionality via SR-IOV Virtual Functions
+#     and "PCI Device Passthrough" -- this is especially true for the NIC
+#     application functionality.
+#
+
+
+# Global configuration settings.
+#
+[global]
+	rss_glb_config_mode = basicvirtual
+	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
+
+	# PL_TIMEOUT register
+	pl_timeout_value = 200		# the timeout value in units of us
+
+	# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
+	# Page Size and a 64B L1 Cache Line Size. It programs the
+	# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
+	# If a Master PF Driver finds itself on a machine with different
+	# parameters, then the Master PF Driver is responsible for initializing
+	# these parameters to appropriate values.
+	#
+	# Notes:
+	#  1. The Free List Buffer Sizes below are raw and the firmware will
+	#     round them up to the Ingress Padding Boundary.
+	#  2. The SGE Timer Values below are expressed below in microseconds.
+	#     The firmware will convert these values to Core Clock Ticks when
+	#     it processes the configuration parameters.
+	#
+	reg[0x1008] = 0x40810/0x21c70	# SGE_CONTROL
+	reg[0x100c] = 0x22222222	# SGE_HOST_PAGE_SIZE
+	reg[0x10a0] = 0x01040810	# SGE_INGRESS_RX_THRESHOLD
+	reg[0x1044] = 4096		# SGE_FL_BUFFER_SIZE0
+	reg[0x1048] = 65536		# SGE_FL_BUFFER_SIZE1
+	reg[0x104c] = 1536		# SGE_FL_BUFFER_SIZE2
+	reg[0x1050] = 9024		# SGE_FL_BUFFER_SIZE3
+	reg[0x1054] = 9216		# SGE_FL_BUFFER_SIZE4
+	reg[0x1058] = 2048		# SGE_FL_BUFFER_SIZE5
+	reg[0x105c] = 128		# SGE_FL_BUFFER_SIZE6
+	reg[0x1060] = 8192		# SGE_FL_BUFFER_SIZE7
+	reg[0x1064] = 16384		# SGE_FL_BUFFER_SIZE8
+	reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
+	reg[0x10a8] = 0x402000/0x402000	# SGE_DOORBELL_CONTROL
+	sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
+	reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
+	reg[0x173c] = 0x2/0x2
+
+	reg[0x1750] = 0x01000000/0x03c00000 # RDMA_INV_Handling = 1
+                                        # terminate_status_en = 0
+                                        # DISABLE = 0
+
+	#DBQ Timer duration = 1 cclk cycle duration * (sge_dbq_timertick+1) * sge_dbq_timer
+	#SGE DBQ tick value. All timers are multiple of this value
+	sge_dbq_timertick = 50 #in usecs
+	sge_dbq_timer = 1, 2, 4, 6, 8, 10, 12, 16
+
+	#CIM_QUEUE_FEATURE_DISABLE.obq_eom_enable bit needs to be set to 1 for CmdMore handling support
+	reg[0x7c4c] = 0x20/0x20
+
+	# enable TP_OUT_CONFIG.IPIDSPLITMODE
+	reg[0x7d04] = 0x00010000/0x00010000
+
+	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
+
+    reg[0x46004] = 0x3/0x3      #Crypto core reset
+
+	#Tick granularities in kbps
+	tsch_ticks = 100000, 10000, 1000, 10
+
+	# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
+	# filter control: compact, fcoemask
+	# server sram   : srvrsram
+	# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
+	#		  protocol, tos, vlan, vnic_id, port, fcoe
+	# valid filterModes are described the Terminator 5 Data Book
+	filterMode = fcoemask, srvrsram, ipsec, rocev2, fragmentation, mpshittype, protocol, vlan, port, fcoe
+
+	# filter tuples enforced in LE active region (equal to or subset of filterMode)
+	filterMask = protocol, ipsec, rocev2, fcoe
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP RX payload
+	tp_pmrx = 30
+
+	# TP RX payload page size
+	tp_pmrx_pagesize = 64K
+
+	# Percentage of dynamic memory (in either the EDRAM or external MEM)
+	# to use for TP TX payload
+	tp_pmtx = 50
+
+	# TP TX payload page size
+	tp_pmtx_pagesize = 64K
+
+	# TP OFLD MTUs
+	tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
+
+	# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
+	reg[0x7d04] = 0x00010008/0x00010008
+
+	# TP_GLOBAL_CONFIG
+	reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
+
+	# TP_PC_CONFIG
+	reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
+
+	# TP_PARA_REG0
+	reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
+
+	# ULPRX iSCSI Page Sizes
+	reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
+
+	# LE_DB_CONFIG
+	reg[0x19c04] = 0x00400000/0x00440000 # LE Server SRAM Enable, 
+					     # LE IPv4 compression disabled 
+	# LE_DB_HASH_CONFIG
+	reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 
+
+	# ULP_TX_CONFIG
+	reg[0x8dc0] = 0x00000104/0x02000104 # Enable ITT on PI err
+					    # Enable more error msg for ...
+					    # TPT error.
+						# Err2uP = 0
+
+	#ULP_RX_CTL1
+	reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3
+	                                     # ROCE_Invld_Msg_Dis = 3
+
+	#Enable iscsi completion moderation feature, disable rdma invlidate in ulptx
+	reg[0x1925c] = 0x000041c0/0x000031d0	# Enable offset decrement after
+						# PI extraction and before DDP.
+						# ulp insert pi source info in
+						# DIF.
+						# Enable iscsi hdr cmd mode.
+						# iscsi force cmd mode.
+						# Enable iscsi cmp mode.
+						# terminate_status_en = 0
+
+	#ULP_RX_CQE_GEN_EN
+	reg[0x19250] = 0x0/0x3   # Termimate_msg = 0
+	                         # Terminate_with_err = 0
+
+	gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
+				    # 2 - disable gc for mc1/hma enable mc0,
+				    # 1 - enable gc for mc1/hma disable mc0,
+				    # 0 - enable gc for mc1/hma and for mc0,
+				    # default gc enabled.
+
+	# HMA configuration (uncomment following lines to enable HMA)
+	hma_size = 92 			# Size (in MBs) of host memory expected
+	hma_regions = 	iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq	# What all regions to place in host memory
+
+    #mc[0]=0
+    #mc[1]=0
+
+# Some "definitions" to make the rest of this a bit more readable.  We support
+# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
+# per function per port ...
+#
+# NMSIX = 1088			# available MSI-X Vectors
+# NVI = 256			# available Virtual Interfaces
+# NMPSTCAM = 336		# MPS TCAM entries
+#
+# NPORTS = 2			# ports
+# NCPUS = 16			# CPUs we want to support scalably
+# NFUNCS = 3			# functions per port (NIC, FCoE, iSCSI)
+
+# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
+# PF" which many OS Drivers will use to manage most or all functions.
+#
+# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
+# use Forwarded Interrupt Ingress Queues.  For these latter, an Ingress Queue
+# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
+# will be specified as the "Ingress Queue Asynchronous Destination Index."
+# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
+# than or equal to the number of Ingress Queues ...
+#
+# NVI_NIC = 4			# NIC access to NPORTS
+# NFLIQ_NIC = 32		# NIC Ingress Queues with Free Lists
+# NETHCTRL_NIC = 32		# NIC Ethernet Control/TX Queues
+# NEQ_NIC = 64			# NIC Egress Queues (FL, ETHCTRL/TX)
+# NMPSTCAM_NIC = 16		# NIC MPS TCAM Entries (NPORTS*4)
+# NMSIX_NIC = 32		# NIC MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_OFLD = 0			# Offload uses NIC function to access ports
+# NFLIQ_OFLD = 16		# Offload Ingress Queues with Free Lists
+# NETHCTRL_OFLD = 0		# Offload Ethernet Control/TX Queues
+# NEQ_OFLD = 16			# Offload Egress Queues (FL)
+# NMPSTCAM_OFLD = 0		# Offload MPS TCAM Entries (uses NIC's)
+# NMSIX_OFLD = 16		# Offload MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_RDMA = 0			# RDMA uses NIC function to access ports
+# NFLIQ_RDMA = 4		# RDMA Ingress Queues with Free Lists
+# NETHCTRL_RDMA = 0		# RDMA Ethernet Control/TX Queues
+# NEQ_RDMA = 4			# RDMA Egress Queues (FL)
+# NMPSTCAM_RDMA = 0		# RDMA MPS TCAM Entries (uses NIC's)
+# NMSIX_RDMA = 4		# RDMA MSI-X Interrupt Vectors (FLIQ)
+#
+# NEQ_WD = 128			# Wire Direct TX Queues and FLs
+# NETHCTRL_WD = 64		# Wire Direct TX Queues
+# NFLIQ_WD = 64	`		# Wire Direct Ingress Queues with Free Lists
+#
+# NVI_ISCSI = 4			# ISCSI access to NPORTS
+# NFLIQ_ISCSI = 4		# ISCSI Ingress Queues with Free Lists
+# NETHCTRL_ISCSI = 0		# ISCSI Ethernet Control/TX Queues
+# NEQ_ISCSI = 4			# ISCSI Egress Queues (FL)
+# NMPSTCAM_ISCSI = 4		# ISCSI MPS TCAM Entries (NPORTS)
+# NMSIX_ISCSI = 4		# ISCSI MSI-X Interrupt Vectors (FLIQ)
+#
+# NVI_FCOE = 4			# FCOE access to NPORTS
+# NFLIQ_FCOE = 34		# FCOE Ingress Queues with Free Lists
+# NETHCTRL_FCOE = 32		# FCOE Ethernet Control/TX Queues
+# NEQ_FCOE = 66			# FCOE Egress Queues (FL)
+# NMPSTCAM_FCOE = 32 		# FCOE MPS TCAM Entries (NPORTS)
+# NMSIX_FCOE = 34		# FCOE MSI-X Interrupt Vectors (FLIQ)
+
+# Two extra Ingress Queues per function for Firmware Events and Forwarded
+# Interrupts, and two extra interrupts per function for Firmware Events (or a
+# Forwarded Interrupt Queue) and General Interrupts per function.
+#
+# NFLIQ_EXTRA = 6		# "extra" Ingress Queues 2*NFUNCS (Firmware and
+# 				#   Forwarded Interrupts
+# NMSIX_EXTRA = 6		# extra interrupts 2*NFUNCS (Firmware and
+# 				#   General Interrupts
+
+# Microsoft HyperV resources.  The HyperV Virtual Ingress Queues will have
+# their interrupts forwarded to another set of Forwarded Interrupt Queues.
+#
+# NVI_HYPERV = 16		# VMs we want to support
+# NVIIQ_HYPERV = 2		# Virtual Ingress Queues with Free Lists per VM
+# NFLIQ_HYPERV = 40		# VIQs + NCPUS Forwarded Interrupt Queues
+# NEQ_HYPERV = 32		# VIQs Free Lists
+# NMPSTCAM_HYPERV = 16		# MPS TCAM Entries (NVI_HYPERV)
+# NMSIX_HYPERV = 8		# NCPUS Forwarded Interrupt Queues
+
+# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
+# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
+#
+# NVI_UNIFIED = 28
+# NFLIQ_UNIFIED = 106
+# NETHCTRL_UNIFIED = 32
+# NEQ_UNIFIED = 124
+# NMPSTCAM_UNIFIED = 40
+#
+# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
+# that up to 128 to make sure the Unified PF doesn't run out of resources.
+#
+# NMSIX_UNIFIED = 128
+#
+# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
+# which is 34 but they're probably safe with 32.
+#
+# NMSIX_STORAGE = 32
+
+# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
+# associated with it.  Thus, the MSI-X Vector allocations we give to the
+# UnifiedPF aren't inherited by any Virtual Functions.  As a result we can
+# provision many more Virtual Functions than we can if the UnifiedPF were
+# one of PF0-1.
+#
+
+# All of the below PCI-E parameters are actually stored in various *_init.txt
+# files.  We include them below essentially as comments.
+#
+# For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated
+# ports 0-1.
+#
+# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
+#
+# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
+# storage applications across all four possible ports.
+#
+# Additionally, since the UnifiedPF isn't one of the per-port Physical
+# Functions, we give the UnifiedPF and the PF0-1 Physical Functions
+# different PCI Device IDs which will allow Unified and Per-Port Drivers
+# to directly select the type of Physical Function to which they wish to be
+# attached.
+#
+# Note that the actual values used for the PCI-E Intelectual Property will be
+# 1 less than those below since that's the way it "counts" things.  For
+# readability, we use the number we actually mean ...
+#
+# PF0_INT = 8			# NCPUS
+# PF1_INT = 8			# NCPUS
+# PF0_3_INT = 32		# PF0_INT + PF1_INT + PF2_INT + PF3_INT
+#
+# PF4_INT = 128			# NMSIX_UNIFIED
+# PF5_INT = 32			# NMSIX_STORAGE
+# PF6_INT = 32			# NMSIX_STORAGE
+# PF7_INT = 0			# Nothing Assigned
+# PF4_7_INT = 192		# PF4_INT + PF5_INT + PF6_INT + PF7_INT
+#
+# PF0_7_INT = 224		# PF0_3_INT + PF4_7_INT
+#
+# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
+# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
+#
+# NVF = 16
+
+
+# For those OSes which manage different ports on different PFs, we need
+# only enough resources to support a single port's NIC application functions
+# on PF0-3.  The below assumes that we're only doing NIC with NCPUS "Queue
+# Sets" for ports 0-3.  The FCoE and iSCSI functions for such OSes will be
+# managed on the "storage PFs" (see below).
+#
+
+[function "0"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port
+
+
+[function "1"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port
+
+[function "2"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	#pmask = 0x4		# access to only one port
+	pmask = 0x1		# access to only one port
+
+[function "3"]
+	nvf = 16		# NVF on this function
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 1			# 1 port
+	niqflint = 8		# NCPUS "Queue Sets"
+	nethctrl = 8		# NCPUS "Queue Sets"
+	neq = 16		# niqflint + nethctrl Egress Queues
+	nexactf = 8		# number of exact MPSTCAM MAC filters
+	cmask = all		# access to all channels
+	#pmask = 0x2		# access to only one port
+
+# Some OS Drivers manage all application functions for all ports via PF4.
+# Thus we need to provide a large number of resources here.  For Egress
+# Queues we need to account for both TX Queues as well as Free List Queues
+# (because the host is responsible for producing Free List Buffers for the
+# hardware to consume).
+#
+
+[function "4"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 28		# NVI_UNIFIED
+	niqflint = 170		# NFLIQ_UNIFIED + NLFIQ_WD
+	nethctrl = 224 		# NETHCTRL_UNIFIED + NETHCTRL_WD
+	neq = 252		# NEQ_UNIFIED + NEQ_WD
+	nqpcq = 12288
+	nexactf = 40		# NMPSTCAM_UNIFIED
+	nrawf = 4
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nethofld = 1024		# number of user mode ethernet flow contexts
+	ncrypto_lookaside = 32
+	nclip = 320		# number of clip region entries
+	nfilter = 480		# number of filter region entries
+	nserver = 480		# number of server region entries
+	nhash = 12288		# number of hash region entries
+	nhpfilter = 64		# number of high priority filter region entries
+	#protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath
+	protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp
+	tp_l2t = 3072
+	tp_ddp = 2
+	tp_ddp_iscsi = 2
+	tp_tls_key = 3
+	tp_tls_mxrxsize = 33792    # 32768 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes
+	tp_stag = 2
+	tp_pbl = 5
+	tp_rq = 7
+	tp_rrq = 4
+	tp_srq = 128
+	nipsec_tunnel16 = 64	# in unit of 16
+	nipsec_transport16 = 191 # in unit of 16
+
+
+# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
+# need to have Virtual Interfaces on each of the four ports with up to NCPUS
+# "Queue Sets" each.
+#
+[function "5"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nexactf = 16		# (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nserver = 16
+	nhash = 1536
+	tp_l2t = 508
+	protocol = iscsi_initiator_fofld
+	tp_ddp_iscsi = 2
+	iscsi_ntask = 2048
+	iscsi_nsess = 2048
+	iscsi_nconn_per_session = 1
+	iscsi_ninitiator_instance = 64
+
+[function "6"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NPORTS
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 66		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
+	nexactf = 32		# NPORTS + adding 28 exact entries for FCoE
+				# which is OK since < MIN(SUM PF0..3, PF4)
+				# and we never load PF0..3 and PF4 concurrently
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nhash = 1536
+	tp_l2t = 4
+	protocol = fcoe_initiator
+	tp_ddp = 1
+	fcoe_nfcf = 16
+	fcoe_nvnp = 32
+	fcoe_nssn = 1024
+
+# Following function 7 is used by embedded ARM to communicate to
+# the firmware.
+[function "7"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NVI_UNIFIED
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nexactf = 8		# NPORTS + DCBX +
+	nfilter = 16		# number of filter region entries
+	#nhpfilter = 16		# number of high priority filter region entries
+	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
+	nethctrl = 32		# NPORTS*NCPUS
+	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nserver = 16
+	nhash = 1024
+	tp_l2t = 512
+	protocol = nic_vm, ofld, rddp, rdmac, tlskeys, ipsec_inline, rocev2, nvme_tcp
+
+# The following function, 1023, is not an actual PCIE function but is used to
+# configure and reserve firmware internal resources that come from the global
+# resource pool.
+#
+[function "1023"]
+	wx_caps = all		# write/execute permissions for all commands
+	r_caps = all		# read permissions for all commands
+	nvi = 4			# NVI_UNIFIED
+	cmask = all		# access to all channels
+	pmask = all		# access to all four ports ...
+	nexactf = 8		# NPORTS + DCBX +
+	nfilter = 16		# number of filter region entries
+	#nhpfilter = 0		# number of high priority filter region entries
+
+
+# For Virtual functions, we only allow NIC functionality and we only allow
+# access to one port (1 << PF).  Note that because of limitations in the
+# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
+# and GTS registers, the number of Ingress and Egress Queues must be a power
+# of 2.
+#
+[function "0/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port ...
+
+
+[function "1/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port ...
+
+[function "2/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x1		# access to only one port ...
+
+
+[function "3/*"]		# NVF
+	wx_caps = 0x82		# DMAQ | VF
+	r_caps = 0x86		# DMAQ | VF | PORT
+	nvi = 1			# 1 port
+	niqflint = 6		# 2 "Queue Sets" + NXIQ
+	nethctrl = 4		# 2 "Queue Sets"
+	neq = 8			# 2 "Queue Sets" * 2
+	nexactf = 4
+	cmask = all		# access to all channels
+	pmask = 0x2		# access to only one port ...
+
+# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
+# for packets from the wire as well as the loopback path of the L2 switch. The
+# folling params control how the buffer memory is distributed and the L2 flow
+# control settings:
+#
+# bg_mem:	%-age of mem to use for port/buffer group
+# lpbk_mem:	%-age of port/bg mem to use for loopback
+# hwm:		high watermark; bytes available when starting to send pause
+#		frames (in units of 0.1 MTU)
+# lwm:		low watermark; bytes remaining when sending 'unpause' frame
+#		(in inuits of 0.1 MTU)
+# dwm:		minimum delta between high and low watermark (in units of 100
+#		Bytes)
+#
+[port "0"]
+	dcb = ppp, dcbx	# configure for DCB PPP and enable DCBX offload
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+
+[port "1"]
+	dcb = ppp, dcbx
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+[port "2"]
+	dcb = ppp, dcbx	# configure for DCB PPP and enable DCBX offload
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+
+[port "3"]
+	dcb = ppp, dcbx
+	hwm = 30
+	lwm = 15
+	dwm = 30
+	dcb_app_tlv[0] = 0x8906, ethertype, 3
+	dcb_app_tlv[1] = 0x8914, ethertype, 3
+	dcb_app_tlv[2] = 3260, socketnum, 5
+
+[fini]
+	version = 0x1425001d
+	checksum = 0x5cab62d4
+
+# Total resources used by above allocations:
+#   Virtual Interfaces: 104
+#   Ingress Queues/w Free Lists and Interrupts: 526
+#   Egress Queues: 702
+#   MPS TCAM Entries: 336
+#   MSI-X Vectors: 736
+#   Virtual Functions: 64
diff --git a/sys/dev/cxgbe/iw_cxgbe/device.c b/sys/dev/cxgbe/iw_cxgbe/device.c
index 3c4d269f6c69..4610f91e96ac 100644
--- a/sys/dev/cxgbe/iw_cxgbe/device.c
+++ b/sys/dev/cxgbe/iw_cxgbe/device.c
@@ -132,26 +132,21 @@ c4iw_rdev_open(struct c4iw_rdev *rdev)
 	rdev->stats.rqt.total = sc->vres.rq.size;
 	rdev->stats.qid.total = sc->vres.qp.size;
 
-	rc = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
+	rc = c4iw_init_resource(rdev, T4_MAX_NUM_PD);
 	if (rc) {
 		device_printf(sc->dev, "error %d initializing resources\n", rc);
 		goto err1;
 	}
-	rc = c4iw_pblpool_create(rdev);
-	if (rc) {
-		device_printf(sc->dev, "error %d initializing pbl pool\n", rc);
-		goto err2;
-	}
 	rc = c4iw_rqtpool_create(rdev);
 	if (rc) {
 		device_printf(sc->dev, "error %d initializing rqt pool\n", rc);
-		goto err3;
+		goto err2;
 	}
 	rdev->status_page = (struct t4_dev_status_page *)
 				__get_free_page(GFP_KERNEL);
 	if (!rdev->status_page) {
 		rc = -ENOMEM;
-		goto err4;
+		goto err3;
 	}
 	rdev->status_page->qp_start = sc->vres.qp.start;
 	rdev->status_page->qp_size = sc->vres.qp.size;
@@ -168,15 +163,13 @@ c4iw_rdev_open(struct c4iw_rdev *rdev)
 	rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
 	if (!rdev->free_workq) {
 		rc = -ENOMEM;
-		goto err5;
+		goto err4;
 	}
 	return (0);
-err5:
-	free_page((unsigned long)rdev->status_page);
 err4:
-	c4iw_rqtpool_destroy(rdev);
+	free_page((unsigned long)rdev->status_page);
 err3:
-	c4iw_pblpool_destroy(rdev);
+	c4iw_rqtpool_destroy(rdev);
 err2:
 	c4iw_destroy_resource(&rdev->resource);
 err1:
@@ -186,7 +179,6 @@ err1:
 static void c4iw_rdev_close(struct c4iw_rdev *rdev)
 {
 	free_page((unsigned long)rdev->status_page);
-	c4iw_pblpool_destroy(rdev);
 	c4iw_rqtpool_destroy(rdev);
 	c4iw_destroy_resource(&rdev->resource);
 }
diff --git a/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h b/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
index ca2595b65b02..47ce10562c66 100644
--- a/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
+++ b/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
@@ -99,7 +99,6 @@ struct c4iw_id_table {
 };
 
 struct c4iw_resource {
-	struct c4iw_id_table tpt_table;
 	struct c4iw_id_table qid_table;
 	struct c4iw_id_table pdid_table;
 };
@@ -904,11 +903,9 @@ int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 		     struct l2t_entry *l2t);
 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
-int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
+int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_pdid);
 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
-int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
-void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
diff --git a/sys/dev/cxgbe/iw_cxgbe/mem.c b/sys/dev/cxgbe/iw_cxgbe/mem.c
index 4a1adc118b7c..ae0aa0edc17a 100644
--- a/sys/dev/cxgbe/iw_cxgbe/mem.c
+++ b/sys/dev/cxgbe/iw_cxgbe/mem.c
@@ -56,46 +56,23 @@ mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
 
 static int
 _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, u32 len,
-				void *data, int wait)
+			    dma_addr_t data, int wait)
 {
 	struct adapter *sc = rdev->adap;
-	struct ulp_mem_io *ulpmc;
-	struct ulptx_sgl *sgl;
 	u8 wr_len;
 	int ret = 0;
 	struct c4iw_wr_wait wr_wait;
 	struct wrqe *wr;
 
-	addr &= 0x7FFFFFF;
-
 	if (wait)
 		c4iw_init_wr_wait(&wr_wait);
-	wr_len = roundup(sizeof *ulpmc + sizeof *sgl, 16);
+	wr_len = T4_WRITE_MEM_DMA_LEN;
 
 	wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]);
 	if (wr == NULL)
 		return -ENOMEM;
-	ulpmc = wrtod(wr);
-
-	memset(ulpmc, 0, wr_len);
-	INIT_ULPTX_WR(ulpmc, wr_len, 0, 0);
-	ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) |
-				    (wait ? F_FW_WR_COMPL : 0));
-	ulpmc->wr.wr_lo = wait ? (u64)(unsigned long)&wr_wait : 0;
-	ulpmc->wr.wr_mid = cpu_to_be32(V_FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16)));
-	ulpmc->cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) |
-			       V_T5_ULP_MEMIO_ORDER(1) |
-			V_T5_ULP_MEMIO_FID(sc->sge.ofld_rxq[0].iq.abs_id));
-	ulpmc->dlen = cpu_to_be32(V_ULP_MEMIO_DATA_LEN(len>>5));
-	ulpmc->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(ulpmc->wr), 16));
-	ulpmc->lock_addr = cpu_to_be32(V_ULP_MEMIO_ADDR(addr));
-
-	sgl = (struct ulptx_sgl *)(ulpmc + 1);
-	sgl->cmd_nsge = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
-				    V_ULPTX_NSGE(1));
-	sgl->len0 = cpu_to_be32(len);
-	sgl->addr0 = cpu_to_be64((u64)data);
-
+	t4_write_mem_dma_wr(sc, wrtod(wr), wr_len, 0, addr, len, data,
+	    wait ? (u64)(unsigned long)&wr_wait : 0);
 	t4_wrq_tx(sc, wr);
 
 	if (wait)
@@ -108,70 +85,32 @@ static int
 _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
 {
 	struct adapter *sc = rdev->adap;
-	struct ulp_mem_io *ulpmc;
-	struct ulptx_idata *ulpsc;
-	u8 wr_len, *to_dp, *from_dp;
+	u8 wr_len, *from_dp;
 	int copy_len, num_wqe, i, ret = 0;
 	struct c4iw_wr_wait wr_wait;
 	struct wrqe *wr;
-	u32 cmd;
-
-	cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE));
 
-	cmd |= cpu_to_be32(F_T5_ULP_MEMIO_IMM);
-
-	addr &= 0x7FFFFFF;
 	CTR3(KTR_IW_CXGBE, "%s addr 0x%x len %u", __func__, addr, len);
-	num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
 	c4iw_init_wr_wait(&wr_wait);
+	num_wqe = DIV_ROUND_UP(len, T4_MAX_INLINE_SIZE);
+	from_dp = data;
 	for (i = 0; i < num_wqe; i++) {
-
-		copy_len = min(len, C4IW_MAX_INLINE_SIZE);
-		wr_len = roundup(sizeof *ulpmc + sizeof *ulpsc +
-				 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
+		copy_len = min(len, T4_MAX_INLINE_SIZE);
+		wr_len = T4_WRITE_MEM_INLINE_LEN(copy_len);
 
 		wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]);
 		if (wr == NULL)
 			return -ENOMEM;
-		ulpmc = wrtod(wr);
-
-		memset(ulpmc, 0, wr_len);
-		INIT_ULPTX_WR(ulpmc, wr_len, 0, 0);
-
-		if (i == (num_wqe-1)) {
-			ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) |
-						    F_FW_WR_COMPL);
-			ulpmc->wr.wr_lo =
-				       (__force __be64)(unsigned long) &wr_wait;
-		} else
-			ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR));
-		ulpmc->wr.wr_mid = cpu_to_be32(
-				       V_FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16)));
-
-		ulpmc->cmd = cmd;
-		ulpmc->dlen = cpu_to_be32(V_ULP_MEMIO_DATA_LEN(
-		    DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
-		ulpmc->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(ulpmc->wr),
-						      16));
-		ulpmc->lock_addr = cpu_to_be32(V_ULP_MEMIO_ADDR(addr + i * 3));
-
-		ulpsc = (struct ulptx_idata *)(ulpmc + 1);
-		ulpsc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
-		ulpsc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
-
-		to_dp = (u8 *)(ulpsc + 1);
-		from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
-		if (data)
-			memcpy(to_dp, from_dp, copy_len);
-		else
-			memset(to_dp, 0, copy_len);
-		if (copy_len % T4_ULPTX_MIN_IO)
-			memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
-			       (copy_len % T4_ULPTX_MIN_IO));
+		t4_write_mem_inline_wr(sc, wrtod(wr), wr_len, 0, addr, copy_len,
+		    from_dp, i == (num_wqe - 1) ?
+		    (__force __be64)(unsigned long) &wr_wait : 0);
 		t4_wrq_tx(sc, wr);
-		len -= C4IW_MAX_INLINE_SIZE;
-	}
 
+		if (from_dp != NULL)
+			from_dp += T4_MAX_INLINE_SIZE;
+		addr += T4_MAX_INLINE_SIZE >> 5;
+		len -= T4_MAX_INLINE_SIZE;
+	}
 	ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, NULL, __func__);
 	return ret;
 }
@@ -201,7 +140,7 @@ _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
 			dmalen = T4_ULPTX_MAX_DMA;
 		remain -= dmalen;
 		ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen,
-				(void *)daddr, !remain);
+				daddr, !remain);
 		if (ret)
 			goto out;
 		addr += dmalen >> 5;
@@ -263,8 +202,8 @@ static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
 	stag_idx = (*stag) >> 8;
 
 	if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
-		stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
-		if (!stag_idx) {
+		stag_idx = t4_stag_alloc(rdev->adap, 1);
+		if (stag_idx == T4_STAG_UNSET) {
 			mutex_lock(&rdev->stats.lock);
 			rdev->stats.stag.fail++;
 			mutex_unlock(&rdev->stats.lock);
@@ -309,7 +248,7 @@ static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
 				sizeof(tpt), &tpt);
 
 	if (reset_tpt_entry) {
-		c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
+		t4_stag_free(rdev->adap, stag_idx, 1);
 		mutex_lock(&rdev->stats.lock);
 		rdev->stats.stag.cur -= 32;
 		mutex_unlock(&rdev->stats.lock);
diff --git a/sys/dev/cxgbe/iw_cxgbe/resource.c b/sys/dev/cxgbe/iw_cxgbe/resource.c
index 644ea0c631bf..cd20f1eafdd6 100644
--- a/sys/dev/cxgbe/iw_cxgbe/resource.c
+++ b/sys/dev/cxgbe/iw_cxgbe/resource.c
@@ -59,13 +59,9 @@ static int c4iw_init_qid_table(struct c4iw_rdev *rdev)
 }
 
 /* nr_* must be power of 2 */
-int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid)
+int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_pdid)
 {
 	int err = 0;
-	err = c4iw_id_table_alloc(&rdev->resource.tpt_table, 0, nr_tpt, 1,
-					C4IW_ID_TABLE_F_RANDOM);
-	if (err)
-		goto tpt_err;
 	err = c4iw_init_qid_table(rdev);
 	if (err)
 		goto qid_err;
@@ -77,8 +73,6 @@ int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid)
  pdid_err:
 	c4iw_id_table_free(&rdev->resource.qid_table);
  qid_err:
-	c4iw_id_table_free(&rdev->resource.tpt_table);
- tpt_err:
 	return -ENOMEM;
 }
 
@@ -243,7 +237,6 @@ void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
 
 void c4iw_destroy_resource(struct c4iw_resource *rscp)
 {
-	c4iw_id_table_free(&rscp->tpt_table);
 	c4iw_id_table_free(&rscp->qid_table);
 	c4iw_id_table_free(&rscp->pdid_table);
 }
@@ -254,12 +247,9 @@ void c4iw_destroy_resource(struct c4iw_resource *rscp)
 
 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size)
 {
-	unsigned long addr;
+	u32 addr;
 
-	vmem_xalloc(rdev->pbl_arena, roundup(size, (1 << MIN_PBL_SHIFT)),
-			4, 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX,
-			M_FIRSTFIT|M_NOWAIT, &addr);
-	CTR3(KTR_IW_CXGBE, "%s addr 0x%x size %d", __func__, (u32)addr, size);
+	addr = t4_pblpool_alloc(rdev->adap, size);
 	mutex_lock(&rdev->stats.lock);
 	if (addr) {
 		rdev->stats.pbl.cur += roundup(size, 1 << MIN_PBL_SHIFT);
@@ -268,33 +258,15 @@ u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size)
 	} else
 		rdev->stats.pbl.fail++;
 	mutex_unlock(&rdev->stats.lock);
-	return (u32)addr;
+	return addr;
 }
 
 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size)
 {
-	CTR3(KTR_IW_CXGBE, "%s addr 0x%x size %d", __func__, addr, size);
 	mutex_lock(&rdev->stats.lock);
 	rdev->stats.pbl.cur -= roundup(size, 1 << MIN_PBL_SHIFT);
 	mutex_unlock(&rdev->stats.lock);
-	vmem_xfree(rdev->pbl_arena, addr, roundup(size,(1 << MIN_PBL_SHIFT)));
-}
-
-int c4iw_pblpool_create(struct c4iw_rdev *rdev)
-{
-	rdev->pbl_arena = vmem_create("PBL_MEM_POOL",
-					rdev->adap->vres.pbl.start,
-					rdev->adap->vres.pbl.size,
-					1, 0, M_FIRSTFIT| M_NOWAIT);
-	if (!rdev->pbl_arena)
-		return -ENOMEM;
-
-	return 0;
-}
-
-void c4iw_pblpool_destroy(struct c4iw_rdev *rdev)
-{
-	vmem_destroy(rdev->pbl_arena);
+	t4_pblpool_free(rdev->adap, addr, size);
 }
 
 /* RQT Memory Manager. */
diff --git a/sys/dev/cxgbe/iw_cxgbe/t4.h b/sys/dev/cxgbe/iw_cxgbe/t4.h
index 48f85cf7965b..ffb610420640 100644
--- a/sys/dev/cxgbe/iw_cxgbe/t4.h
+++ b/sys/dev/cxgbe/iw_cxgbe/t4.h
@@ -64,7 +64,6 @@
 #define T4_MAX_NUM_PD 65536
 #define T4_MAX_MR_SIZE (~0ULL)
 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */
-#define T4_STAG_UNSET 0xffffffff
 #define T4_FW_MAJ 0
 #define A_PCIE_MA_SYNC 0x30b4
 
diff --git a/sys/dev/cxgbe/offload.h b/sys/dev/cxgbe/offload.h
index b57c03f076b5..91a43785aaca 100644
--- a/sys/dev/cxgbe/offload.h
+++ b/sys/dev/cxgbe/offload.h
@@ -229,7 +229,17 @@ struct iw_tunables {
 
 struct tls_tunables {
 	int inline_keys;
-	int combo_wrs;
+	union {
+		struct {
+			/* T6 only. */
+			int combo_wrs;
+		};
+		struct {
+			/* T7 only. */
+			int short_records;
+			int partial_ghash;
+		};
+	};
 };
 
 #ifdef TCP_OFFLOAD
diff --git a/sys/dev/cxgbe/t4_filter.c b/sys/dev/cxgbe/t4_filter.c
index 8d4552116d96..4b583b67ba07 100644
--- a/sys/dev/cxgbe/t4_filter.c
+++ b/sys/dev/cxgbe/t4_filter.c
@@ -322,48 +322,85 @@ remove_hftid(struct adapter *sc, struct filter_entry *f)
 	LIST_REMOVE(f, link_tid);
 }
 
-/*
- * Input: driver's 32b filter mode.
- * Returns: hardware filter mode (bits to set in vlan_pri_map) for the input.
- */
 static uint16_t
-mode_to_fconf(uint32_t mode)
+mode_to_fconf_t4(uint32_t mode)
 {
 	uint32_t fconf = 0;
 
 	if (mode & T4_FILTER_IP_FRAGMENT)
 		fconf |= F_FRAGMENTATION;
-
 	if (mode & T4_FILTER_MPS_HIT_TYPE)
 		fconf |= F_MPSHITTYPE;
-
 	if (mode & T4_FILTER_MAC_IDX)
 		fconf |= F_MACMATCH;
-
 	if (mode & T4_FILTER_ETH_TYPE)
 		fconf |= F_ETHERTYPE;
-
 	if (mode & T4_FILTER_IP_PROTO)
 		fconf |= F_PROTOCOL;
-
 	if (mode & T4_FILTER_IP_TOS)
 		fconf |= F_TOS;
-
 	if (mode & T4_FILTER_VLAN)
 		fconf |= F_VLAN;
-
 	if (mode & T4_FILTER_VNIC)
 		fconf |= F_VNIC_ID;
-
 	if (mode & T4_FILTER_PORT)
 		fconf |= F_PORT;
-
 	if (mode & T4_FILTER_FCoE)
 		fconf |= F_FCOE;
 
 	return (fconf);
 }
 
+static uint16_t
+mode_to_fconf_t7(uint32_t mode)
+{
+	uint32_t fconf = 0;
+
+	if (mode & T4_FILTER_TCPFLAGS)
+		fconf |= F_TCPFLAGS;
+	if (mode & T4_FILTER_SYNONLY)
+		fconf |= F_SYNONLY;
+	if (mode & T4_FILTER_ROCE)
+		fconf |= F_ROCE;
+	if (mode & T4_FILTER_IP_FRAGMENT)
+		fconf |= F_T7_FRAGMENTATION;
+	if (mode & T4_FILTER_MPS_HIT_TYPE)
+		fconf |= F_T7_MPSHITTYPE;
+	if (mode & T4_FILTER_MAC_IDX)
+		fconf |= F_T7_MACMATCH;
+	if (mode & T4_FILTER_ETH_TYPE)
+		fconf |= F_T7_ETHERTYPE;
+	if (mode & T4_FILTER_IP_PROTO)
+		fconf |= F_T7_PROTOCOL;
+	if (mode & T4_FILTER_IP_TOS)
+		fconf |= F_T7_TOS;
+	if (mode & T4_FILTER_VLAN)
+		fconf |= F_T7_VLAN;
+	if (mode & T4_FILTER_VNIC)
+		fconf |= F_T7_VNIC_ID;
+	if (mode & T4_FILTER_PORT)
+		fconf |= F_T7_PORT;
+	if (mode & T4_FILTER_FCoE)
+		fconf |= F_T7_FCOE;
+	if (mode & T4_FILTER_IPSECIDX)
+		fconf |= F_IPSECIDX;
+
+	return (fconf);
+}
+
+/*
+ * Input: driver's 32b filter mode.
+ * Returns: hardware filter mode (bits to set in vlan_pri_map) for the input.
+ */
+static uint16_t
+mode_to_fconf(struct adapter *sc, uint32_t mode)
+{
+	if (chip_id(sc) >= CHELSIO_T7)
+		return (mode_to_fconf_t7(mode));
+	else
+		return (mode_to_fconf_t4(mode));
+}
+
 /*
  * Input: driver's 32b filter mode.
  * Returns: hardware vnic mode (ingress config) matching the input.
@@ -389,65 +426,100 @@ check_fspec_against_fconf_iconf(struct adapter *sc,
 	struct tp_params *tpp = &sc->params.tp;
 	uint32_t fconf = 0;
 
-	if (fs->val.frag || fs->mask.frag)
-		fconf |= F_FRAGMENTATION;
-
-	if (fs->val.matchtype || fs->mask.matchtype)
-		fconf |= F_MPSHITTYPE;
-
-	if (fs->val.macidx || fs->mask.macidx)
-		fconf |= F_MACMATCH;
-
-	if (fs->val.ethtype || fs->mask.ethtype)
-		fconf |= F_ETHERTYPE;
-
-	if (fs->val.proto || fs->mask.proto)
-		fconf |= F_PROTOCOL;
-
-	if (fs->val.tos || fs->mask.tos)
-		fconf |= F_TOS;
-
-	if (fs->val.vlan_vld || fs->mask.vlan_vld)
-		fconf |= F_VLAN;
-
-	if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
-		if (tpp->vnic_mode != FW_VNIC_MODE_OUTER_VLAN)
-			return (EINVAL);
-		fconf |= F_VNIC_ID;
-	}
-
-	if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
-		if (tpp->vnic_mode != FW_VNIC_MODE_PF_VF)
-			return (EINVAL);
-		fconf |= F_VNIC_ID;
-	}
-
+	if (chip_id(sc) >= CHELSIO_T7) {
+		if (fs->val.tcpflags || fs->mask.tcpflags)
+			fconf |= F_TCPFLAGS;
+		if (fs->val.synonly || fs->mask.synonly)
+			fconf |= F_SYNONLY;
+		if (fs->val.roce || fs->mask.roce)
+			fconf |= F_ROCE;
+		if (fs->val.frag || fs->mask.frag)
+			fconf |= F_T7_FRAGMENTATION;
+		if (fs->val.matchtype || fs->mask.matchtype)
+			fconf |= F_T7_MPSHITTYPE;
+		if (fs->val.macidx || fs->mask.macidx)
+			fconf |= F_T7_MACMATCH;
+		if (fs->val.ethtype || fs->mask.ethtype)
+			fconf |= F_T7_ETHERTYPE;
+		if (fs->val.proto || fs->mask.proto)
+			fconf |= F_T7_PROTOCOL;
+		if (fs->val.tos || fs->mask.tos)
+			fconf |= F_T7_TOS;
+		if (fs->val.vlan_vld || fs->mask.vlan_vld)
+			fconf |= F_T7_VLAN;
+		if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
+			if (tpp->vnic_mode != FW_VNIC_MODE_OUTER_VLAN)
+				return (EINVAL);
+			fconf |= F_T7_VNIC_ID;
+		}
+		if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
+			if (tpp->vnic_mode != FW_VNIC_MODE_PF_VF)
+				return (EINVAL);
+			fconf |= F_T7_VNIC_ID;
+		}
 #ifdef notyet
-	if (fs->val.encap_vld || fs->mask.encap_vld) {
-		if (tpp->vnic_mode != FW_VNIC_MODE_ENCAP_EN);
+		if (fs->val.encap_vld || fs->mask.encap_vld) {
+			if (tpp->vnic_mode != FW_VNIC_MODE_ENCAP_EN);
+				return (EINVAL);
+			fconf |= F_T7_VNIC_ID;
+		}
+#endif
+		if (fs->val.iport || fs->mask.iport)
+			fconf |= F_T7_PORT;
+		if (fs->val.fcoe || fs->mask.fcoe)
+			fconf |= F_T7_FCOE;
+		if (fs->val.ipsecidx || fs->mask.ipsecidx)
+			fconf |= F_IPSECIDX;
+	} else {
+		if (fs->val.tcpflags || fs->mask.tcpflags ||
+		    fs->val.synonly || fs->mask.synonly ||
+		    fs->val.roce || fs->mask.roce ||
+		    fs->val.ipsecidx || fs->mask.ipsecidx)
 			return (EINVAL);
-		fconf |= F_VNIC_ID;
-	}
+		if (fs->val.frag || fs->mask.frag)
+			fconf |= F_FRAGMENTATION;
+		if (fs->val.matchtype || fs->mask.matchtype)
+			fconf |= F_MPSHITTYPE;
+		if (fs->val.macidx || fs->mask.macidx)
+			fconf |= F_MACMATCH;
+		if (fs->val.ethtype || fs->mask.ethtype)
+			fconf |= F_ETHERTYPE;
+		if (fs->val.proto || fs->mask.proto)
+			fconf |= F_PROTOCOL;
+		if (fs->val.tos || fs->mask.tos)
+			fconf |= F_TOS;
+		if (fs->val.vlan_vld || fs->mask.vlan_vld)
+			fconf |= F_VLAN;
+		if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
+			if (tpp->vnic_mode != FW_VNIC_MODE_OUTER_VLAN)
+				return (EINVAL);
+			fconf |= F_VNIC_ID;
+		}
+		if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
+			if (tpp->vnic_mode != FW_VNIC_MODE_PF_VF)
+				return (EINVAL);
+			fconf |= F_VNIC_ID;
+		}
+#ifdef notyet
+		if (fs->val.encap_vld || fs->mask.encap_vld) {
+			if (tpp->vnic_mode != FW_VNIC_MODE_ENCAP_EN);
+				return (EINVAL);
+			fconf |= F_VNIC_ID;
+		}
 #endif
-
-	if (fs->val.iport || fs->mask.iport)
-		fconf |= F_PORT;
-
-	if (fs->val.fcoe || fs->mask.fcoe)
-		fconf |= F_FCOE;
-
+		if (fs->val.iport || fs->mask.iport)
+			fconf |= F_PORT;
+		if (fs->val.fcoe || fs->mask.fcoe)
+			fconf |= F_FCOE;
+	}
 	if ((tpp->filter_mode | fconf) != tpp->filter_mode)
 		return (E2BIG);
 
 	return (0);
 }
 
-/*
- * Input: hardware filter configuration (filter mode/mask, ingress config).
- * Input: driver's 32b filter mode matching the input.
- */
 static uint32_t
-fconf_to_mode(uint16_t hwmode, int vnic_mode)
+fconf_to_mode_t4(uint16_t hwmode, int vnic_mode)
 {
 	uint32_t mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
 	    T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
@@ -488,6 +560,69 @@ fconf_to_mode(uint16_t hwmode, int vnic_mode)
 	return (mode);
 }
 
+static uint32_t
+fconf_to_mode_t7(uint16_t hwmode, int vnic_mode)
+{
+	uint32_t mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
+	    T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
+
+	if (hwmode & F_TCPFLAGS)
+		mode |= T4_FILTER_TCPFLAGS;
+	if (hwmode & F_SYNONLY)
+		mode |= T4_FILTER_SYNONLY;
+	if (hwmode & F_ROCE)
+		mode |= T4_FILTER_ROCE;
+	if (hwmode & F_T7_FRAGMENTATION)
+		mode |= T4_FILTER_IP_FRAGMENT;
+	if (hwmode & F_T7_MPSHITTYPE)
+		mode |= T4_FILTER_MPS_HIT_TYPE;
+	if (hwmode & F_T7_MACMATCH)
+		mode |= T4_FILTER_MAC_IDX;
+	if (hwmode & F_T7_ETHERTYPE)
+		mode |= T4_FILTER_ETH_TYPE;
+	if (hwmode & F_T7_PROTOCOL)
+		mode |= T4_FILTER_IP_PROTO;
+	if (hwmode & F_T7_TOS)
+		mode |= T4_FILTER_IP_TOS;
+	if (hwmode & F_T7_VLAN)
+		mode |= T4_FILTER_VLAN;
+	if (hwmode & F_T7_VNIC_ID)
+		mode |= T4_FILTER_VNIC; /* real meaning depends on vnic_mode. */
+	if (hwmode & F_T7_PORT)
+		mode |= T4_FILTER_PORT;
+	if (hwmode & F_T7_FCOE)
+		mode |= T4_FILTER_FCoE;
+	if (hwmode & F_IPSECIDX)
+		mode |= T4_FILTER_IPSECIDX;
+
+	switch (vnic_mode) {
+	case FW_VNIC_MODE_PF_VF:
+		mode |= T4_FILTER_IC_VNIC;
+		break;
+	case FW_VNIC_MODE_ENCAP_EN:
+		mode |= T4_FILTER_IC_ENCAP;
+		break;
+	case FW_VNIC_MODE_OUTER_VLAN:
+	default:
+		break;
+	}
+
+	return (mode);
+}
+
+/*
+ * Input: hardware filter configuration (filter mode/mask, ingress config).
+ * Output: driver's 32b filter mode matching the input.
+ */
+static inline uint32_t
+fconf_to_mode(struct adapter *sc, uint16_t hwmode, int vnic_mode)
+{
+	if (chip_id(sc) >= CHELSIO_T7)
+		return (fconf_to_mode_t7(hwmode, vnic_mode));
+	else
+		return (fconf_to_mode_t4(hwmode, vnic_mode));
+}
+
 int
 get_filter_mode(struct adapter *sc, uint32_t *mode)
 {
@@ -499,7 +634,7 @@ get_filter_mode(struct adapter *sc, uint32_t *mode)
 
 	/* Non-zero incoming value in mode means "hashfilter mode". */
 	filter_mode = *mode ? tp->filter_mask : tp->filter_mode;
-	*mode = fconf_to_mode(filter_mode, tp->vnic_mode);
+	*mode = fconf_to_mode(sc, filter_mode, tp->vnic_mode);
 
 	return (0);
 }
@@ -512,7 +647,7 @@ set_filter_mode(struct adapter *sc, uint32_t mode)
 	uint16_t fconf;
 
 	iconf = mode_to_iconf(mode);
-	fconf = mode_to_fconf(mode);
+	fconf = mode_to_fconf(sc, mode);
 	if ((iconf == -1 || iconf == tp->vnic_mode) && fconf == tp->filter_mode)
 		return (0);	/* Nothing to do */
 
@@ -554,7 +689,7 @@ set_filter_mask(struct adapter *sc, uint32_t mode)
 	uint16_t fmask;
 
 	iconf = mode_to_iconf(mode);
-	fmask = mode_to_fconf(mode);
+	fmask = mode_to_fconf(sc, mode);
 	if ((iconf == -1 || iconf == tp->vnic_mode) && fmask == tp->filter_mask)
 		return (0);	/* Nothing to do */
 
@@ -811,71 +946,138 @@ hashfilter_ntuple(struct adapter *sc, const struct t4_filter_specification *fs,
 	struct tp_params *tp = &sc->params.tp;
 	uint16_t fmask;
 
-	*ftuple = fmask = 0;
-
 	/*
 	 * Initialize each of the fields which we care about which are present
 	 * in the Compressed Filter Tuple.
 	 */
-	if (tp->vlan_shift >= 0 && fs->mask.vlan) {
-		*ftuple |= (uint64_t)(F_FT_VLAN_VLD | fs->val.vlan) <<
-		    tp->vlan_shift;
-		fmask |= F_VLAN;
-	}
-
-	if (tp->port_shift >= 0 && fs->mask.iport) {
-		*ftuple |= (uint64_t)fs->val.iport << tp->port_shift;
-		fmask |= F_PORT;
-	}
-
-	if (tp->protocol_shift >= 0 && fs->mask.proto) {
-		*ftuple |= (uint64_t)fs->val.proto << tp->protocol_shift;
-		fmask |= F_PROTOCOL;
-	}
-
-	if (tp->tos_shift >= 0 && fs->mask.tos) {
-		*ftuple |= (uint64_t)(fs->val.tos) << tp->tos_shift;
-		fmask |= F_TOS;
-	}
-
-	if (tp->vnic_shift >= 0 && fs->mask.vnic) {
-		/* vnic_mode was already validated. */
-		if (tp->vnic_mode == FW_VNIC_MODE_PF_VF)
-			MPASS(fs->mask.pfvf_vld);
-		else if (tp->vnic_mode == FW_VNIC_MODE_OUTER_VLAN)
-			MPASS(fs->mask.ovlan_vld);
+#define SFF(V, S) ((uint64_t)(V) << S) /* Shifted Filter Field. */
+	*ftuple = fmask = 0;
+	if (chip_id(sc) >= CHELSIO_T7) {
+		if (tp->ipsecidx_shift >= 0 && fs->mask.ipsecidx) {
+			*ftuple |= SFF(fs->val.ipsecidx, tp->ipsecidx_shift);
+			fmask |= F_IPSECIDX;
+		}
+		if (tp->fcoe_shift >= 0 && fs->mask.fcoe) {
+			*ftuple |= SFF(fs->val.fcoe, tp->fcoe_shift);
+			fmask |= F_T7_FCOE;
+		}
+		if (tp->port_shift >= 0 && fs->mask.iport) {
+			*ftuple |= (uint64_t)fs->val.iport << tp->port_shift;
+			fmask |= F_T7_PORT;
+		}
+		if (tp->vnic_shift >= 0 && fs->mask.vnic) {
+			/* vnic_mode was already validated. */
+			if (tp->vnic_mode == FW_VNIC_MODE_PF_VF)
+				MPASS(fs->mask.pfvf_vld);
+			else if (tp->vnic_mode == FW_VNIC_MODE_OUTER_VLAN)
+				MPASS(fs->mask.ovlan_vld);
 #ifdef notyet
-		else if (tp->vnic_mode == FW_VNIC_MODE_ENCAP_EN)
-			MPASS(fs->mask.encap_vld);
+			else if (tp->vnic_mode == FW_VNIC_MODE_ENCAP_EN)
+				MPASS(fs->mask.encap_vld);
 #endif
-		*ftuple |= ((1ULL << 16) | fs->val.vnic) << tp->vnic_shift;
-		fmask |= F_VNIC_ID;
-	}
-
-	if (tp->macmatch_shift >= 0 && fs->mask.macidx) {
-		*ftuple |= (uint64_t)(fs->val.macidx) << tp->macmatch_shift;
-		fmask |= F_MACMATCH;
-	}
-
-	if (tp->ethertype_shift >= 0 && fs->mask.ethtype) {
-		*ftuple |= (uint64_t)(fs->val.ethtype) << tp->ethertype_shift;
-		fmask |= F_ETHERTYPE;
-	}
-
-	if (tp->matchtype_shift >= 0 && fs->mask.matchtype) {
-		*ftuple |= (uint64_t)(fs->val.matchtype) << tp->matchtype_shift;
-		fmask |= F_MPSHITTYPE;
-	}
-
-	if (tp->frag_shift >= 0 && fs->mask.frag) {
-		*ftuple |= (uint64_t)(fs->val.frag) << tp->frag_shift;
-		fmask |= F_FRAGMENTATION;
-	}
-
-	if (tp->fcoe_shift >= 0 && fs->mask.fcoe) {
-		*ftuple |= (uint64_t)(fs->val.fcoe) << tp->fcoe_shift;
-		fmask |= F_FCOE;
+			*ftuple |= SFF(F_FT_VNID_ID_VLD | fs->val.vnic, tp->vnic_shift);
+			fmask |= F_T7_VNIC_ID;
+		}
+		if (tp->vlan_shift >= 0 && fs->mask.vlan) {
+			*ftuple |= SFF(F_FT_VLAN_VLD | fs->val.vlan, tp->vlan_shift);
+			fmask |= F_T7_VLAN;
+		}
+		if (tp->tos_shift >= 0 && fs->mask.tos) {
+			*ftuple |= SFF(fs->val.tos, tp->tos_shift);
+			fmask |= F_T7_TOS;
+		}
+		if (tp->protocol_shift >= 0 && fs->mask.proto) {
+			*ftuple |= SFF(fs->val.proto, tp->protocol_shift);
+			fmask |= F_T7_PROTOCOL;
+		}
+		if (tp->ethertype_shift >= 0 && fs->mask.ethtype) {
+			*ftuple |= SFF(fs->val.ethtype, tp->ethertype_shift);
+			fmask |= F_T7_ETHERTYPE;
+		}
+		if (tp->macmatch_shift >= 0 && fs->mask.macidx) {
+			*ftuple |= SFF(fs->val.macidx, tp->macmatch_shift);
+			fmask |= F_T7_MACMATCH;
+		}
+		if (tp->matchtype_shift >= 0 && fs->mask.matchtype) {
+			*ftuple |= SFF(fs->val.matchtype, tp->matchtype_shift);
+			fmask |= F_T7_MPSHITTYPE;
+		}
+		if (tp->frag_shift >= 0 && fs->mask.frag) {
+			*ftuple |= SFF(fs->val.frag, tp->frag_shift);
+			fmask |= F_T7_FRAGMENTATION;
+		}
+		if (tp->roce_shift >= 0 && fs->mask.roce) {
+			*ftuple |= SFF(fs->val.roce, tp->roce_shift);
+			fmask |= F_ROCE;
+		}
+		if (tp->synonly_shift >= 0 && fs->mask.synonly) {
+			*ftuple |= SFF(fs->val.synonly, tp->synonly_shift);
+			fmask |= F_SYNONLY;
+		}
+		if (tp->tcpflags_shift >= 0 && fs->mask.tcpflags) {
+			*ftuple |= SFF(fs->val.tcpflags, tp->synonly_shift);
+			fmask |= F_TCPFLAGS;
+		}
+	} else {
+		if (fs->mask.ipsecidx || fs->mask.roce || fs->mask.synonly ||
+		    fs->mask.tcpflags) {
+			MPASS(tp->ipsecidx_shift == -1);
+			MPASS(tp->roce_shift == -1);
+			MPASS(tp->synonly_shift == -1);
+			MPASS(tp->tcpflags_shift == -1);
+			return (EINVAL);
+		}
+		if (tp->fcoe_shift >= 0 && fs->mask.fcoe) {
+			*ftuple |= SFF(fs->val.fcoe, tp->fcoe_shift);
+			fmask |= F_FCOE;
+		}
+		if (tp->port_shift >= 0 && fs->mask.iport) {
+			*ftuple |= (uint64_t)fs->val.iport << tp->port_shift;
+			fmask |= F_PORT;
+		}
+		if (tp->vnic_shift >= 0 && fs->mask.vnic) {
+			/* vnic_mode was already validated. */
+			if (tp->vnic_mode == FW_VNIC_MODE_PF_VF)
+				MPASS(fs->mask.pfvf_vld);
+			else if (tp->vnic_mode == FW_VNIC_MODE_OUTER_VLAN)
+				MPASS(fs->mask.ovlan_vld);
+#ifdef notyet
+			else if (tp->vnic_mode == FW_VNIC_MODE_ENCAP_EN)
+				MPASS(fs->mask.encap_vld);
+#endif
+			*ftuple |= SFF(F_FT_VNID_ID_VLD | fs->val.vnic, tp->vnic_shift);
+			fmask |= F_VNIC_ID;
+		}
+		if (tp->vlan_shift >= 0 && fs->mask.vlan) {
+			*ftuple |= SFF(F_FT_VLAN_VLD | fs->val.vlan, tp->vlan_shift);
+			fmask |= F_VLAN;
+		}
+		if (tp->tos_shift >= 0 && fs->mask.tos) {
+			*ftuple |= SFF(fs->val.tos, tp->tos_shift);
+			fmask |= F_TOS;
+		}
+		if (tp->protocol_shift >= 0 && fs->mask.proto) {
+			*ftuple |= SFF(fs->val.proto, tp->protocol_shift);
+			fmask |= F_PROTOCOL;
+		}
+		if (tp->ethertype_shift >= 0 && fs->mask.ethtype) {
+			*ftuple |= SFF(fs->val.ethtype, tp->ethertype_shift);
+			fmask |= F_ETHERTYPE;
+		}
+		if (tp->macmatch_shift >= 0 && fs->mask.macidx) {
+			*ftuple |= SFF(fs->val.macidx, tp->macmatch_shift);
+			fmask |= F_MACMATCH;
+		}
+		if (tp->matchtype_shift >= 0 && fs->mask.matchtype) {
+			*ftuple |= SFF(fs->val.matchtype, tp->matchtype_shift);
+			fmask |= F_MPSHITTYPE;
+		}
+		if (tp->frag_shift >= 0 && fs->mask.frag) {
+			*ftuple |= SFF(fs->val.frag, tp->frag_shift);
+			fmask |= F_FRAGMENTATION;
+		}
 	}
+#undef SFF
 
 	/* A hashfilter must conform to the hardware filter mask. */
 	if (fmask != tp->filter_mask)
@@ -1195,11 +1397,19 @@ set_tcb_field(struct adapter *sc, u_int tid, uint16_t word, uint64_t mask,
 		return (ENOMEM);
 	bzero(req, sizeof(*req));
 	INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, tid);
-	if (no_reply == 0) {
-		req->reply_ctrl = htobe16(V_QUEUENO(sc->sge.fwq.abs_id) |
-		    V_NO_REPLY(0));
-	} else
-		req->reply_ctrl = htobe16(V_NO_REPLY(1));
+	if (no_reply) {
+		req->reply_ctrl = htobe16(F_NO_REPLY);
+	} else {
+		const int qid = sc->sge.fwq.abs_id;
+
+		if (chip_id(sc) >= CHELSIO_T7) {
+			req->reply_ctrl = htobe16(V_T7_QUEUENO(qid) |
+			    V_T7_REPLY_CHAN(0) | V_NO_REPLY(0));
+		} else {
+			req->reply_ctrl = htobe16(V_QUEUENO(qid) |
+			    V_REPLY_CHAN(0) | V_NO_REPLY(0));
+		}
+	}
 	req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(CPL_COOKIE_HASHFILTER));
 	req->mask = htobe64(mask);
 	req->val = htobe64(val);
@@ -1594,7 +1804,7 @@ static int
 act_open_cpl_len16(struct adapter *sc, int isipv6)
 {
 	int idx;
-	static const int sz_table[3][2] = {
+	static const int sz_table[4][2] = {
 		{
 			howmany(sizeof (struct cpl_act_open_req), 16),
 			howmany(sizeof (struct cpl_act_open_req6), 16)
@@ -1607,10 +1817,14 @@ act_open_cpl_len16(struct adapter *sc, int isipv6)
 			howmany(sizeof (struct cpl_t6_act_open_req), 16),
 			howmany(sizeof (struct cpl_t6_act_open_req6), 16)
 		},
+		{
+			howmany(sizeof (struct cpl_t7_act_open_req), 16),
+			howmany(sizeof (struct cpl_t7_act_open_req6), 16)
+		},
 	};
 
 	MPASS(chip_id(sc) >= CHELSIO_T4);
-	idx = min(chip_id(sc) - CHELSIO_T4, 2);
+	idx = min(chip_id(sc) - CHELSIO_T4, 3);
 
 	return (sz_table[idx][!!isipv6]);
 }
diff --git a/sys/dev/cxgbe/t4_ioctl.h b/sys/dev/cxgbe/t4_ioctl.h
index ba9a17dbaddf..f7c8ee24d596 100644
--- a/sys/dev/cxgbe/t4_ioctl.h
+++ b/sys/dev/cxgbe/t4_ioctl.h
@@ -64,6 +64,7 @@ enum {
 	T4_SET_FILTER_MASK,		/* set filter mask (hashfilter mode) */
 	T4_HOLD_CLIP_ADDR,		/* add ref on an IP in the CLIP */
 	T4_RELEASE_CLIP_ADDR,		/* remove ref from an IP in the CLIP */
+	T4_GET_SGE_CTXT,		/* get SGE context for a queue */
 };
 
 struct t4_reg {
@@ -119,6 +120,10 @@ struct t4_i2c_data {
 #define T4_FILTER_MAC_IDX	0x2000	/* MPS MAC address match index */
 #define T4_FILTER_MPS_HIT_TYPE	0x4000	/* MPS match type */
 #define T4_FILTER_IP_FRAGMENT	0x8000	/* IP fragment */
+#define T4_FILTER_IPSECIDX	0x10000
+#define T4_FILTER_ROCE		0x20000
+#define T4_FILTER_SYNONLY	0x40000
+#define T4_FILTER_TCPFLAGS	0x80000
 /*
  * T4_FILTER_VNIC's real meaning depends on the ingress config.
  */
@@ -199,6 +204,10 @@ struct t4_filter_tuple {
 	uint32_t vlan_vld:1;	/* VLAN valid */
 	uint32_t ovlan_vld:1;	/* outer VLAN tag valid, value in "vnic" */
 	uint32_t pfvf_vld:1;	/* VNIC id (PF/VF) valid, value in "vnic" */
+	uint32_t roce:1;
+	uint32_t synonly:1;
+	uint32_t tcpflags:6;
+	uint32_t ipsecidx:12;
 };
 
 struct t4_filter_specification {
@@ -322,6 +331,7 @@ struct t4_sched_queue {
 };
 
 #define T4_SGE_CONTEXT_SIZE 24
+#define T7_SGE_CONTEXT_SIZE 28
 enum {
 	SGE_CONTEXT_EGRESS,
 	SGE_CONTEXT_INGRESS,
@@ -335,6 +345,12 @@ struct t4_sge_context {
 	uint32_t data[T4_SGE_CONTEXT_SIZE / 4];
 };
 
+struct t4_sge_ctxt {
+	uint32_t mem_id;
+	uint32_t cid;
+	uint32_t data[T7_SGE_CONTEXT_SIZE / 4];
+};
+
 struct t4_mem_range {
 	uint32_t addr;
 	uint32_t len;
@@ -444,4 +460,5 @@ struct t4_clip_addr {
 #define CHELSIO_T4_SET_FILTER_MASK _IOW('f', T4_SET_FILTER_MASK, uint32_t)
 #define CHELSIO_T4_HOLD_CLIP_ADDR _IOW('f', T4_HOLD_CLIP_ADDR, struct t4_clip_addr)
 #define CHELSIO_T4_RELEASE_CLIP_ADDR _IOW('f', T4_RELEASE_CLIP_ADDR, struct t4_clip_addr)
+#define CHELSIO_T4_GET_SGE_CTXT _IOWR('f', T4_GET_SGE_CTXT, struct t4_sge_ctxt)
 #endif
diff --git a/sys/dev/cxgbe/t4_iov.c b/sys/dev/cxgbe/t4_iov.c
index bfd1613e9795..452ebaaf0172 100644
--- a/sys/dev/cxgbe/t4_iov.c
+++ b/sys/dev/cxgbe/t4_iov.c
@@ -119,6 +119,28 @@ struct {
 	{0x6085, "Chelsio T6240-SO 85"},
 	{0x6086, "Chelsio T6225-SO-CR 86"},
 	{0x6087, "Chelsio T6225-CR 87"},
+}, t7iov_pciids[] = {
+	{0xd000, "Chelsio Terminator 7 FPGA"},	/* T7 PE12K FPGA */
+	{0x7000, "Chelsio T72200-DBG"},		/* 2 x 200G, debug */
+	{0x7001, "Chelsio T7250"},		/* 2 x 10/25/50G, 1 mem */
+	{0x7002, "Chelsio S7250"},		/* 2 x 10/25/50G, nomem */
+	{0x7003, "Chelsio T7450"},		/* 4 x 10/25/50G, 1 mem */
+	{0x7004, "Chelsio S7450"},		/* 4 x 10/25/50G, nomem */
+	{0x7005, "Chelsio T72200"},		/* 2 x 40/100/200G, 1 mem */
+	{0x7006, "Chelsio S72200"},		/* 2 x 40/100/200G, nomem */
+	{0x7007, "Chelsio T72200-FH"},		/* 2 x 40/100/200G, 2 mem */
+	{0x7008, "Chelsio T71400"},		/* 1 x 400G, nomem */
+	{0x7009, "Chelsio S7210-BT"},		/* 2 x 10GBASE-T, nomem */
+	{0x700a, "Chelsio T7450-RC"},		/* 4 x 10/25/50G, 1 mem, RC */
+	{0x700b, "Chelsio T72200-RC"},		/* 2 x 40/100/200G, 1 mem, RC */
+	{0x700c, "Chelsio T72200-FH-RC"},	/* 2 x 40/100/200G, 2 mem, RC */
+	{0x700d, "Chelsio S72200-OCP3"},	/* 2 x 40/100/200G OCP3 */
+	{0x700e, "Chelsio S7450-OCP3"},		/* 4 x 1/20/25/50G OCP3 */
+	{0x700f, "Chelsio S7410-BT-OCP3"},	/* 4 x 10GBASE-T OCP3 */
+	{0x7010, "Chelsio S7210-BT-A"},		/* 2 x 10GBASE-T */
+	{0x7011, "Chelsio T7_MAYRA_7"},		/* Motherboard */
+
+	{0x7080, "Custom T7"},
 };
 
 static inline uint32_t
@@ -191,6 +213,26 @@ t6iov_probe(device_t dev)
 }
 
 static int
+chiov_probe(device_t dev)
+{
+	uint16_t d;
+	size_t i;
+
+	if (pci_get_vendor(dev) != PCI_VENDOR_ID_CHELSIO)
+		return (ENXIO);
+
+	d = pci_get_device(dev);
+	for (i = 0; i < nitems(t7iov_pciids); i++) {
+		if (d == t7iov_pciids[i].device) {
+			device_set_desc(dev, t7iov_pciids[i].desc);
+			device_quiet(dev);
+			return (BUS_PROBE_DEFAULT);
+		}
+	}
+	return (ENXIO);
+}
+
+static int
 t4iov_attach(device_t dev)
 {
 	struct t4iov_softc *sc;
@@ -460,6 +502,28 @@ static driver_t t6iov_driver = {
 	sizeof(struct t4iov_softc)
 };
 
+static device_method_t chiov_methods[] = {
+	DEVMETHOD(device_probe,		chiov_probe),
+	DEVMETHOD(device_attach,	t4iov_attach),
+	DEVMETHOD(device_detach,	t4iov_detach),
+
+#ifdef PCI_IOV
+	DEVMETHOD(pci_iov_init,		t4iov_iov_init),
+	DEVMETHOD(pci_iov_uninit,	t4iov_iov_uninit),
+	DEVMETHOD(pci_iov_add_vf,	t4iov_add_vf),
+#endif
+
+	DEVMETHOD(t4_attach_child,	t4iov_attach_child),
+	DEVMETHOD(t4_detach_child,	t4iov_detach_child),
+
+	DEVMETHOD_END
+};
+
+static driver_t chiov_driver = {
+	"chiov",
+	chiov_methods,
+	sizeof(struct t4iov_softc)
+};
 DRIVER_MODULE(t4iov, pci, t4iov_driver, 0, 0);
 MODULE_VERSION(t4iov, 1);
 
@@ -468,3 +532,6 @@ MODULE_VERSION(t5iov, 1);
 
 DRIVER_MODULE(t6iov, pci, t6iov_driver, 0, 0);
 MODULE_VERSION(t6iov, 1);
+
+DRIVER_MODULE(chiov, pci, chiov_driver, 0, 0);
+MODULE_VERSION(chiov, 1);
diff --git a/sys/dev/cxgbe/t4_l2t.c b/sys/dev/cxgbe/t4_l2t.c
index b1307bf2ace5..5f9c26a0f720 100644
--- a/sys/dev/cxgbe/t4_l2t.c
+++ b/sys/dev/cxgbe/t4_l2t.c
@@ -119,7 +119,7 @@ find_or_alloc_l2e(struct l2t_data *d, uint16_t vlan, uint8_t port, uint8_t *dmac
 				first_free = e;
 		} else if (e->state == L2T_STATE_SWITCHING &&
 		    memcmp(e->dmac, dmac, ETHER_ADDR_LEN) == 0 &&
-		    e->vlan == vlan && e->lport == port)
+		    e->vlan == vlan && e->hw_port == port)
 			return (e);	/* Found existing entry that matches. */
 	}
 
@@ -156,7 +156,7 @@ mk_write_l2e(struct adapter *sc, struct l2t_entry *e, int sync, int reply,
 	INIT_TP_WR(req, 0);
 	OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, idx |
 	    V_SYNC_WR(sync) | V_TID_QID(e->iqid)));
-	req->params = htons(V_L2T_W_PORT(e->lport) | V_L2T_W_NOREPLY(!reply));
+	req->params = htons(V_L2T_W_PORT(e->hw_port) | V_L2T_W_NOREPLY(!reply));
 	req->l2t_idx = htons(idx);
 	req->vlan = htons(e->vlan);
 	memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac));
@@ -227,7 +227,7 @@ t4_l2t_alloc_tls(struct adapter *sc, struct sge_txq *txq, void *dst,
 		e = &d->l2tab[i];
 		if (e->state != L2T_STATE_TLS)
 			continue;
-		if (e->vlan == vlan && e->lport == port &&
+		if (e->vlan == vlan && e->hw_port == port &&
 		    e->wrq == (struct sge_wrq *)txq &&
 		    memcmp(e->dmac, eth_addr, ETHER_ADDR_LEN) == 0) {
 			if (atomic_fetchadd_int(&e->refcnt, 1) == 0) {
@@ -263,7 +263,7 @@ t4_l2t_alloc_tls(struct adapter *sc, struct sge_txq *txq, void *dst,
 	/* Initialize the entry. */
 	e->state = L2T_STATE_TLS;
 	e->vlan = vlan;
-	e->lport = port;
+	e->hw_port = port;
 	e->iqid = sc->sge.fwq.abs_id;
 	e->wrq = (struct sge_wrq *)txq;
 	memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN);
@@ -303,7 +303,7 @@ t4_l2t_alloc_switching(struct adapter *sc, uint16_t vlan, uint8_t port,
 			e->iqid = sc->sge.fwq.abs_id;
 			e->state = L2T_STATE_SWITCHING;
 			e->vlan = vlan;
-			e->lport = port;
+			e->hw_port = port;
 			memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN);
 			atomic_store_rel_int(&e->refcnt, 1);
 			atomic_subtract_int(&d->nfree, 1);
@@ -313,7 +313,7 @@ t4_l2t_alloc_switching(struct adapter *sc, uint16_t vlan, uint8_t port,
 				e = NULL;
 		} else {
 			MPASS(e->vlan == vlan);
-			MPASS(e->lport == port);
+			MPASS(e->hw_port == port);
 			atomic_add_int(&e->refcnt, 1);
 		}
 	}
@@ -488,7 +488,7 @@ sysctl_l2t(SYSCTL_HANDLER_ARGS)
 			   " %u %2u   %c   %5u %s",
 			   e->idx, ip, e->dmac[0], e->dmac[1], e->dmac[2],
 			   e->dmac[3], e->dmac[4], e->dmac[5],
-			   e->vlan & 0xfff, vlan_prio(e), e->lport,
+			   e->vlan & 0xfff, vlan_prio(e), e->hw_port,
 			   l2e_state(e), atomic_load_acq_int(&e->refcnt),
 			   e->ifp ? if_name(e->ifp) : "-");
 skip:
diff --git a/sys/dev/cxgbe/t4_l2t.h b/sys/dev/cxgbe/t4_l2t.h
index 13e085bb7467..989d2d5ec8f3 100644
--- a/sys/dev/cxgbe/t4_l2t.h
+++ b/sys/dev/cxgbe/t4_l2t.h
@@ -71,7 +71,7 @@ struct l2t_entry {
 	volatile int refcnt;		/* entry reference count */
 	uint16_t hash;			/* hash bucket the entry is on */
 	uint8_t ipv6;			/* entry is for an IPv6 address */
-	uint8_t lport;			/* associated offload logical port */
+	uint8_t hw_port;		/* associated hardware port idx */
 	uint8_t dmac[ETHER_ADDR_LEN];	/* next hop's MAC address */
 };
 
diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c
index 9756a6945384..22d2f504c257 100644
--- a/sys/dev/cxgbe/t4_main.c
+++ b/sys/dev/cxgbe/t4_main.c
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2025 Chelsio Communications.
  * Written by: Navdeep Parhar <np@FreeBSD.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -241,6 +240,45 @@ static driver_t vcc_driver = {
 	sizeof(struct vi_info)
 };
 
+/* T7+ bus driver interface */
+static int ch_probe(device_t);
+static device_method_t ch_methods[] = {
+	DEVMETHOD(device_probe,		ch_probe),
+	DEVMETHOD(device_attach,	t4_attach),
+	DEVMETHOD(device_detach,	t4_detach),
+	DEVMETHOD(device_suspend,	t4_suspend),
+	DEVMETHOD(device_resume,	t4_resume),
+
+	DEVMETHOD(bus_child_location,	t4_child_location),
+	DEVMETHOD(bus_reset_prepare, 	t4_reset_prepare),
+	DEVMETHOD(bus_reset_post, 	t4_reset_post),
+
+	DEVMETHOD(t4_is_main_ready,	t4_ready),
+	DEVMETHOD(t4_read_port_device,	t4_read_port_device),
+
+	DEVMETHOD_END
+};
+static driver_t ch_driver = {
+	"chnex",
+	ch_methods,
+	sizeof(struct adapter)
+};
+
+
+/* T7+ port (che) interface */
+static driver_t che_driver = {
+	"che",
+	cxgbe_methods,
+	sizeof(struct port_info)
+};
+
+/* T7+ VI (vche) interface */
+static driver_t vche_driver = {
+	"vche",
+	vcxgbe_methods,
+	sizeof(struct vi_info)
+};
+
 /* ifnet interface */
 static void cxgbe_init(void *);
 static int cxgbe_ioctl(if_t, unsigned long, caddr_t);
@@ -519,6 +557,9 @@ static int t4_fec = -1;
 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0,
     "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
 
+static const char *
+t4_fec_bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2\6auto\7module";
+
 /*
  * Controls when the driver sets the FORCE_FEC bit in the L1_CFG32 that it
  * issues to the firmware.  If the firmware doesn't support FORCE_FEC then the
@@ -570,6 +611,10 @@ static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
 SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN,
     &t4_switchcaps_allowed, 0, "Default switch capabilities");
 
+static int t4_nvmecaps_allowed = 0;
+SYSCTL_INT(_hw_cxgbe, OID_AUTO, nvmecaps_allowed, CTLFLAG_RDTUN,
+    &t4_nvmecaps_allowed, 0, "Default NVMe capabilities");
+
 #ifdef RATELIMIT
 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC |
 	FW_CAPS_CONFIG_NIC_HASHFILTER | FW_CAPS_CONFIG_NIC_ETHOFLD;
@@ -716,6 +761,14 @@ SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, inline_keys, CTLFLAG_RDTUN,
 static int t4_tls_combo_wrs = 0;
 SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, combo_wrs, CTLFLAG_RDTUN, &t4_tls_combo_wrs,
     0, "Attempt to combine TCB field updates with TLS record work requests.");
+
+static int t4_tls_short_records = 1;
+SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, short_records, CTLFLAG_RDTUN,
+    &t4_tls_short_records, 0, "Use cipher-only mode for short records.");
+
+static int t4_tls_partial_ghash = 1;
+SYSCTL_INT(_hw_cxgbe_tls, OID_AUTO, partial_ghash, CTLFLAG_RDTUN,
+    &t4_tls_partial_ghash, 0, "Use partial GHASH for AES-GCM records.");
 #endif
 
 /* Functions used by VIs to obtain unique MAC addresses for each VI. */
@@ -809,17 +862,20 @@ static int sysctl_requested_fec(SYSCTL_HANDLER_ARGS);
 static int sysctl_module_fec(SYSCTL_HANDLER_ARGS);
 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
 static int sysctl_force_fec(SYSCTL_HANDLER_ARGS);
+static int sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS);
 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
 static int sysctl_vdd(SYSCTL_HANDLER_ARGS);
 static int sysctl_reset_sensor(SYSCTL_HANDLER_ARGS);
 static int sysctl_loadavg(SYSCTL_HANDLER_ARGS);
 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
-static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
+static int sysctl_cim_ibq(SYSCTL_HANDLER_ARGS);
+static int sysctl_cim_obq(SYSCTL_HANDLER_ARGS);
 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
+static int sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS);
 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
 static int sysctl_tid_stats(SYSCTL_HANDLER_ARGS);
@@ -831,6 +887,7 @@ static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
+static int sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS);
 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
@@ -855,7 +912,7 @@ static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS);
 static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS);
 static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS);
 #endif
-static int get_sge_context(struct adapter *, struct t4_sge_context *);
+static int get_sge_context(struct adapter *, int, uint32_t, int, uint32_t *);
 static int load_fw(struct adapter *, struct t4_data *);
 static int load_cfg(struct adapter *, struct t4_data *);
 static int load_boot(struct adapter *, struct t4_bootrom *);
@@ -960,6 +1017,29 @@ struct {
 	{0x6485, "Custom T6240-SO"},
 	{0x6486, "Custom T6225-SO-CR"},
 	{0x6487, "Custom T6225-CR"},
+}, t7_pciids[] = {
+	{0xd000, "Chelsio Terminator 7 FPGA"},	/* T7 PE12K FPGA */
+	{0x7400, "Chelsio T72200-DBG"},		/* 2 x 200G, debug */
+	{0x7401, "Chelsio T7250"},		/* 2 x 10/25/50G, 1 mem */
+	{0x7402, "Chelsio S7250"},		/* 2 x 10/25/50G, nomem */
+	{0x7403, "Chelsio T7450"},		/* 4 x 10/25/50G, 1 mem */
+	{0x7404, "Chelsio S7450"},		/* 4 x 10/25/50G, nomem */
+	{0x7405, "Chelsio T72200"},		/* 2 x 40/100/200G, 1 mem */
+	{0x7406, "Chelsio S72200"},		/* 2 x 40/100/200G, nomem */
+	{0x7407, "Chelsio T72200-FH"},		/* 2 x 40/100/200G, 2 mem */
+	{0x7408, "Chelsio S71400"},		/* 1 x 400G, nomem */
+	{0x7409, "Chelsio S7210-BT"},		/* 2 x 10GBASE-T, nomem */
+	{0x740a, "Chelsio T7450-RC"},		/* 4 x 10/25/50G, 1 mem, RC */
+	{0x740b, "Chelsio T72200-RC"},		/* 2 x 40/100/200G, 1 mem, RC */
+	{0x740c, "Chelsio T72200-FH-RC"},	/* 2 x 40/100/200G, 2 mem, RC */
+	{0x740d, "Chelsio S72200-OCP3"},	/* 2 x 40/100/200G OCP3 */
+	{0x740e, "Chelsio S7450-OCP3"},		/* 4 x 1/20/25/50G OCP3 */
+	{0x740f, "Chelsio S7410-BT-OCP3"},	/* 4 x 10GBASE-T OCP3 */
+	{0x7410, "Chelsio S7210-BT-A"},		/* 2 x 10GBASE-T */
+	{0x7411, "Chelsio T7_MAYRA_7"},		/* Motherboard */
+
+	/* Custom */
+	{0x7480, "Custom T7"},
 };
 
 #ifdef TCP_OFFLOAD
@@ -1042,6 +1122,31 @@ t6_probe(device_t dev)
 	return (ENXIO);
 }
 
+static int
+ch_probe(device_t dev)
+{
+	int i;
+	uint16_t v = pci_get_vendor(dev);
+	uint16_t d = pci_get_device(dev);
+	uint8_t f = pci_get_function(dev);
+
+	if (v != PCI_VENDOR_ID_CHELSIO)
+		return (ENXIO);
+
+	/* Attach only to PF0 of the FPGA */
+	if (d == 0xd000 && f != 0)
+		return (ENXIO);
+
+	for (i = 0; i < nitems(t7_pciids); i++) {
+		if (d == t7_pciids[i].device) {
+			device_set_desc(dev, t7_pciids[i].desc);
+			return (BUS_PROBE_DEFAULT);
+		}
+	}
+
+	return (ENXIO);
+}
+
 static void
 t5_attribute_workaround(device_t dev)
 {
@@ -1091,6 +1196,13 @@ static const struct devnames devnames[] = {
 		.pf03_drv_name = "t6iov",
 		.vf_nexus_name = "t6vf",
 		.vf_ifnet_name = "ccv"
+	}, {
+		.nexus_name = "chnex",
+		.ifnet_name = "che",
+		.vi_ifnet_name = "vche",
+		.pf03_drv_name = "chiov",
+		.vf_nexus_name = "chvf",
+		.vf_ifnet_name = "chev"
 	}
 };
 
@@ -1100,12 +1212,13 @@ t4_init_devnames(struct adapter *sc)
 	int id;
 
 	id = chip_id(sc);
-	if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
-		sc->names = &devnames[id - CHELSIO_T4];
-	else {
+	if (id < CHELSIO_T4) {
 		device_printf(sc->dev, "chip id %d is not supported.\n", id);
 		sc->names = NULL;
-	}
+	} else if (id - CHELSIO_T4 < nitems(devnames))
+		sc->names = &devnames[id - CHELSIO_T4];
+	else
+		sc->names = &devnames[nitems(devnames) - 1];
 }
 
 static int
@@ -1277,6 +1390,7 @@ t4_attach(device_t dev)
 		goto done; /* error message displayed already */
 
 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
+	memset(sc->port_map, 0xff, sizeof(sc->port_map));
 
 	/* Prepare the adapter for operation. */
 	buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
@@ -1309,7 +1423,7 @@ t4_attach(device_t dev)
 	 * will work even in "recovery mode".
 	 */
 	setup_memwin(sc);
-	if (t4_init_devlog_params(sc, 0) == 0)
+	if (t4_init_devlog_ncores_params(sc, 0) == 0)
 		fixup_devlog_params(sc);
 	make_dev_args_init(&mda);
 	mda.mda_devsw = &t4_cdevsw;
@@ -1407,14 +1521,16 @@ t4_attach(device_t dev)
 		}
 
 		if (is_bt(pi->port_type))
-			setbit(&sc->bt_map, pi->tx_chan);
+			setbit(&sc->bt_map, pi->hw_port);
 		else
-			MPASS(!isset(&sc->bt_map, pi->tx_chan));
+			MPASS(!isset(&sc->bt_map, pi->hw_port));
 
 		snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
 		    device_get_nameunit(dev), i);
 		mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
-		sc->chan_map[pi->tx_chan] = i;
+		for (j = 0; j < sc->params.tp.lb_nchan; j++)
+			sc->chan_map[pi->tx_chan + j] = i;
+		sc->port_map[pi->hw_port] = i;
 
 		/*
 		 * The MPS counter for FCS errors doesn't work correctly on the
@@ -1424,10 +1540,8 @@ t4_attach(device_t dev)
 		 */
 		if (is_t6(sc))
 			pi->fcs_reg = -1;
-		else {
-			pi->fcs_reg = t4_port_reg(sc, pi->tx_chan,
-			    A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L);
-		}
+		else
+			pi->fcs_reg = A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L;
 		pi->fcs_base = 0;
 
 		/* All VIs on this port share this media. */
@@ -1467,6 +1581,7 @@ t4_attach(device_t dev)
 	sc->intr_count = iaq.nirq;
 
 	s = &sc->sge;
+	s->nctrlq = max(sc->params.nports, sc->params.ncores);
 	s->nrxq = nports * iaq.nrxq;
 	s->ntxq = nports * iaq.ntxq;
 	if (num_vis > 1) {
@@ -1521,7 +1636,7 @@ t4_attach(device_t dev)
 	MPASS(s->niq <= s->iqmap_sz);
 	MPASS(s->neq <= s->eqmap_sz);
 
-	s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
+	s->ctrlq = malloc(s->nctrlq * sizeof(struct sge_wrq), M_CXGBE,
 	    M_ZERO | M_WAITOK);
 	s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
 	    M_ZERO | M_WAITOK);
@@ -1548,6 +1663,7 @@ t4_attach(device_t dev)
 	if (sc->vres.key.size != 0)
 		sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start,
 		    sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK);
+	t4_init_tpt(sc);
 
 	/*
 	 * Second pass over the ports.  This time we know the number of rx and
@@ -1849,6 +1965,7 @@ t4_detach_common(device_t dev)
 #endif
 	if (sc->key_map)
 		vmem_destroy(sc->key_map);
+	t4_free_tpt(sc);
 #ifdef INET6
 	t4_destroy_clip_table(sc);
 #endif
@@ -2156,6 +2273,7 @@ struct adapter_pre_reset_state {
 	uint16_t nbmcaps;
 	uint16_t linkcaps;
 	uint16_t switchcaps;
+	uint16_t nvmecaps;
 	uint16_t niccaps;
 	uint16_t toecaps;
 	uint16_t rdmacaps;
@@ -2187,6 +2305,7 @@ save_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
 	o->nbmcaps =  sc->nbmcaps;
 	o->linkcaps = sc->linkcaps;
 	o->switchcaps = sc->switchcaps;
+	o->nvmecaps = sc->nvmecaps;
 	o->niccaps = sc->niccaps;
 	o->toecaps = sc->toecaps;
 	o->rdmacaps = sc->rdmacaps;
@@ -2225,6 +2344,7 @@ compare_caps_and_params(struct adapter *sc, struct adapter_pre_reset_state *o)
 	COMPARE_CAPS(nbm);
 	COMPARE_CAPS(link);
 	COMPARE_CAPS(switch);
+	COMPARE_CAPS(nvme);
 	COMPARE_CAPS(nic);
 	COMPARE_CAPS(toe);
 	COMPARE_CAPS(rdma);
@@ -2417,11 +2537,7 @@ restart_lld(struct adapter *sc)
 				}
 				if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
 					sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
-					t4_write_reg(sc, is_t4(sc) ?
-					    A_MPS_TRC_RSS_CONTROL :
-					    A_MPS_T5_TRC_RSS_CONTROL,
-					    V_RSSCONTROL(pi->tx_chan) |
-					    V_QUEUENUMBER(sc->traceq));
+					t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
 					pi->flags |= HAS_TRACEQ;
 				}
 
@@ -3407,7 +3523,7 @@ cxgbe_snd_tag_alloc(if_t ifp, union if_snd_tag_alloc_params *params,
 		if (is_t6(vi->pi->adapter))
 			error = t6_tls_tag_alloc(ifp, params, pt);
 		else
-			error = EOPNOTSUPP;
+			error = t7_tls_tag_alloc(ifp, params, pt);
 		break;
 	}
 #endif
@@ -3534,6 +3650,8 @@ port_mword(struct port_info *pi, uint32_t speed)
 	case FW_PORT_TYPE_CR_QSFP:
 	case FW_PORT_TYPE_CR2_QSFP:
 	case FW_PORT_TYPE_SFP28:
+	case FW_PORT_TYPE_SFP56:
+	case FW_PORT_TYPE_QSFP56:
 		/* Pluggable transceiver */
 		switch (pi->mod_type) {
 		case FW_PORT_MOD_TYPE_LR:
@@ -3551,6 +3669,8 @@ port_mword(struct port_info *pi, uint32_t speed)
 				return (IFM_50G_LR2);
 			case FW_PORT_CAP32_SPEED_100G:
 				return (IFM_100G_LR4);
+			case FW_PORT_CAP32_SPEED_200G:
+				return (IFM_200G_LR4);
 			}
 			break;
 		case FW_PORT_MOD_TYPE_SR:
@@ -3567,6 +3687,8 @@ port_mword(struct port_info *pi, uint32_t speed)
 				return (IFM_50G_SR2);
 			case FW_PORT_CAP32_SPEED_100G:
 				return (IFM_100G_SR4);
+			case FW_PORT_CAP32_SPEED_200G:
+				return (IFM_200G_SR4);
 			}
 			break;
 		case FW_PORT_MOD_TYPE_ER:
@@ -3588,6 +3710,8 @@ port_mword(struct port_info *pi, uint32_t speed)
 				return (IFM_50G_CR2);
 			case FW_PORT_CAP32_SPEED_100G:
 				return (IFM_100G_CR4);
+			case FW_PORT_CAP32_SPEED_200G:
+				return (IFM_200G_CR4_PAM4);
 			}
 			break;
 		case FW_PORT_MOD_TYPE_LRM:
@@ -3597,6 +3721,8 @@ port_mword(struct port_info *pi, uint32_t speed)
 		case FW_PORT_MOD_TYPE_DR:
 			if (speed == FW_PORT_CAP32_SPEED_100G)
 				return (IFM_100G_DR);
+			if (speed == FW_PORT_CAP32_SPEED_200G)
+				return (IFM_200G_DR4);
 			break;
 		case FW_PORT_MOD_TYPE_NA:
 			MPASS(0);	/* Not pluggable? */
@@ -3684,7 +3810,7 @@ alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi)
 	    ("%s: VI %s doesn't have a MAC func", __func__,
 	    device_get_nameunit(vi->dev)));
 	func = vi_mac_funcs[index];
-	rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
+	rc = t4_alloc_vi_func(sc, sc->mbox, pi->hw_port, sc->pf, 0, 1,
 	    vi->hw_addr, &vi->rss_size, &vi->vfvld, &vi->vin, func, 0);
 	if (rc < 0) {
 		CH_ERR(vi, "failed to allocate virtual interface %d"
@@ -3954,7 +4080,7 @@ setup_memwin(struct adapter *sc)
 	const struct memwin_init *mw_init;
 	struct memwin *mw;
 	int i;
-	uint32_t bar0;
+	uint32_t bar0, reg;
 
 	if (is_t4(sc)) {
 		/*
@@ -3982,9 +4108,10 @@ setup_memwin(struct adapter *sc)
 			mw->mw_aperture = mw_init->aperture;
 			mw->mw_curpos = 0;
 		}
-		t4_write_reg(sc,
-		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
-		    (mw->mw_base + bar0) | V_BIR(0) |
+		reg = chip_id(sc) > CHELSIO_T6 ?
+		    PCIE_MEM_ACCESS_T7_REG(A_T7_PCIE_MEM_ACCESS_BASE_WIN, i) :
+		    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i);
+		t4_write_reg(sc, reg, (mw->mw_base + bar0) | V_BIR(0) |
 		    V_WINDOW(ilog2(mw->mw_aperture) - 10));
 		rw_wlock(&mw->mw_lock);
 		position_memwin(sc, i, mw->mw_curpos);
@@ -3992,7 +4119,7 @@ setup_memwin(struct adapter *sc)
 	}
 
 	/* flush */
-	t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
+	t4_read_reg(sc, reg);
 }
 
 /*
@@ -4005,8 +4132,7 @@ static void
 position_memwin(struct adapter *sc, int idx, uint32_t addr)
 {
 	struct memwin *mw;
-	uint32_t pf;
-	uint32_t reg;
+	uint32_t pf, reg, val;
 
 	MPASS(idx >= 0 && idx < NUM_MEMWIN);
 	mw = &sc->memwin[idx];
@@ -4019,8 +4145,14 @@ position_memwin(struct adapter *sc, int idx, uint32_t addr)
 		pf = V_PFNUM(sc->pf);
 		mw->mw_curpos = addr & ~0x7f;	/* start must be 128B aligned */
 	}
-	reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
-	t4_write_reg(sc, reg, mw->mw_curpos | pf);
+	if (chip_id(sc) > CHELSIO_T6) {
+		reg = PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, idx);
+		val = (mw->mw_curpos >> X_T7_MEMOFST_SHIFT) | pf;
+	} else {
+		reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
+		val = mw->mw_curpos | pf;
+	}
+	t4_write_reg(sc, reg, val);
 	t4_read_reg(sc, reg);	/* flush */
 }
 
@@ -4453,8 +4585,27 @@ calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
 	iaq->nrxq_vi = t4_nrxq_vi;
 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
 	if (is_offload(sc) || is_ethoffload(sc)) {
-		iaq->nofldtxq = t4_nofldtxq;
-		iaq->nofldtxq_vi = t4_nofldtxq_vi;
+		if (sc->params.tid_qid_sel_mask == 0) {
+			iaq->nofldtxq = t4_nofldtxq;
+			iaq->nofldtxq_vi = t4_nofldtxq_vi;
+		} else {
+			iaq->nofldtxq = roundup(t4_nofldtxq, sc->params.ncores);
+			iaq->nofldtxq_vi = roundup(t4_nofldtxq_vi,
+			    sc->params.ncores);
+			if (iaq->nofldtxq != t4_nofldtxq)
+				device_printf(sc->dev,
+				    "nofldtxq updated (%d -> %d) for correct"
+				    " operation with %d firmware cores.\n",
+				    t4_nofldtxq, iaq->nofldtxq,
+				    sc->params.ncores);
+			if (iaq->num_vis > 1 &&
+			    iaq->nofldtxq_vi != t4_nofldtxq_vi)
+				device_printf(sc->dev,
+				    "nofldtxq_vi updated (%d -> %d) for correct"
+				    " operation with %d firmware cores.\n",
+				    t4_nofldtxq_vi, iaq->nofldtxq_vi,
+				    sc->params.ncores);
+		}
 	}
 #endif
 #ifdef TCP_OFFLOAD
@@ -4555,6 +4706,10 @@ calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype,
 	if (iaq->nofldrxq > 0) {
 		iaq->nofldrxq = 1;
 		iaq->nofldtxq = 1;
+		if (sc->params.tid_qid_sel_mask == 0)
+			iaq->nofldtxq = 1;
+		else
+			iaq->nofldtxq = sc->params.ncores;
 	}
 	iaq->nnmtxq = 0;
 	iaq->nnmrxq = 0;
@@ -4567,9 +4722,10 @@ done:
 	MPASS(iaq->nirq > 0);
 	MPASS(iaq->nrxq > 0);
 	MPASS(iaq->ntxq > 0);
-	if (itype == INTR_MSI) {
+	if (itype == INTR_MSI)
 		MPASS(powerof2(iaq->nirq));
-	}
+	if (sc->params.tid_qid_sel_mask != 0)
+		MPASS(iaq->nofldtxq % sc->params.ncores == 0);
 }
 
 static int
@@ -4711,6 +4867,22 @@ struct fw_info {
 			.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
 			.intfver_fcoe = FW_INTFVER(T6, FCOE),
 		},
+	}, {
+		.chip = CHELSIO_T7,
+		.kld_name = "t7fw_cfg",
+		.fw_mod_name = "t7fw",
+		.fw_h = {
+			.chip = FW_HDR_CHIP_T7,
+			.fw_ver = htobe32(FW_VERSION(T7)),
+			.intfver_nic = FW_INTFVER(T7, NIC),
+			.intfver_vnic = FW_INTFVER(T7, VNIC),
+			.intfver_ofld = FW_INTFVER(T7, OFLD),
+			.intfver_ri = FW_INTFVER(T7, RI),
+			.intfver_iscsipdu = FW_INTFVER(T7, ISCSIPDU),
+			.intfver_iscsi = FW_INTFVER(T7, ISCSI),
+			.intfver_fcoepdu = FW_INTFVER(T7, FCOEPDU),
+			.intfver_fcoe = FW_INTFVER(T7, FCOE),
+		},
 	}
 };
 
@@ -5032,7 +5204,7 @@ done:
 
 static int
 copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
-    uint32_t mtype, uint32_t moff)
+    uint32_t mtype, uint32_t moff, u_int maxlen)
 {
 	struct fw_info *fw_info;
 	const struct firmware *dcfg, *rcfg = NULL;
@@ -5084,10 +5256,10 @@ copy_cfg_file_to_card(struct adapter *sc, char *cfg_file,
 		cflen = rcfg->datasize & ~3;
 	}
 
-	if (cflen > FLASH_CFG_MAX_SIZE) {
+	if (cflen > maxlen) {
 		device_printf(sc->dev,
 		    "config file too long (%d, max allowed is %d).\n",
-		    cflen, FLASH_CFG_MAX_SIZE);
+		    cflen, maxlen);
 		rc = EINVAL;
 		goto done;
 	}
@@ -5112,6 +5284,7 @@ struct caps_allowed {
 	uint16_t nbmcaps;
 	uint16_t linkcaps;
 	uint16_t switchcaps;
+	uint16_t nvmecaps;
 	uint16_t niccaps;
 	uint16_t toecaps;
 	uint16_t rdmacaps;
@@ -5139,6 +5312,8 @@ apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
 	int rc;
 	struct fw_caps_config_cmd caps;
 	uint32_t mtype, moff, finicsum, cfcsum, param, val;
+	unsigned int maxlen = 0;
+	const int cfg_addr = t4_flash_cfg_addr(sc, &maxlen);
 
 	rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST);
 	if (rc != 0) {
@@ -5155,7 +5330,7 @@ apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
 		caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
 	} else if (strncmp(cfg_file, FLASH_CF, sizeof(t4_cfg_file)) == 0) {
 		mtype = FW_MEMTYPE_FLASH;
-		moff = t4_flash_cfg_addr(sc);
+		moff = cfg_addr;
 		caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 		    V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
@@ -5179,7 +5354,7 @@ apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
 		    V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) |
 		    FW_LEN16(caps));
 
-		rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff);
+		rc = copy_cfg_file_to_card(sc, cfg_file, mtype, moff, maxlen);
 		if (rc != 0) {
 			device_printf(sc->dev,
 			    "failed to upload config file to card: %d.\n", rc);
@@ -5213,6 +5388,7 @@ apply_cfg_and_initialize(struct adapter *sc, char *cfg_file,
 	LIMIT_CAPS(nbm);
 	LIMIT_CAPS(link);
 	LIMIT_CAPS(switch);
+	LIMIT_CAPS(nvme);
 	LIMIT_CAPS(nic);
 	LIMIT_CAPS(toe);
 	LIMIT_CAPS(rdma);
@@ -5278,6 +5454,7 @@ partition_resources(struct adapter *sc)
 	COPY_CAPS(nbm);
 	COPY_CAPS(link);
 	COPY_CAPS(switch);
+	COPY_CAPS(nvme);
 	COPY_CAPS(nic);
 	COPY_CAPS(toe);
 	COPY_CAPS(rdma);
@@ -5354,7 +5531,7 @@ get_params__pre_init(struct adapter *sc)
 	sc->params.vpd.cclk = val[1];
 
 	/* Read device log parameters. */
-	rc = -t4_init_devlog_params(sc, 1);
+	rc = -t4_init_devlog_ncores_params(sc, 1);
 	if (rc == 0)
 		fixup_devlog_params(sc);
 	else {
@@ -5508,6 +5685,14 @@ get_params__post_init(struct adapter *sc)
 		}
 	}
 
+	if (sc->params.ncores > 1) {
+		MPASS(chip_id(sc) >= CHELSIO_T7);
+
+		param[0] = FW_PARAM_DEV(TID_QID_SEL_MASK);
+		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
+		sc->params.tid_qid_sel_mask = rc == 0 ? val[0] : 0;
+	}
+
 	/*
 	 * The parameters that follow may not be available on all firmwares.  We
 	 * query them individually rather than in a compound query because old
@@ -5533,6 +5718,14 @@ get_params__post_init(struct adapter *sc)
 	else
 		sc->params.tp_ch_map = UINT32_MAX;	/* Not a legal value. */
 
+	param[0] = FW_PARAM_DEV(TX_TPCHMAP);
+	val[0] = 0;
+	rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val);
+	if (rc == 0)
+		sc->params.tx_tp_ch_map = val[0];
+	else
+		sc->params.tx_tp_ch_map = UINT32_MAX;	/* Not a legal value. */
+
 	/*
 	 * Determine whether the firmware supports the filter2 work request.
 	 */
@@ -5604,6 +5797,7 @@ get_params__post_init(struct adapter *sc)
 	READ_CAPS(nbmcaps);
 	READ_CAPS(linkcaps);
 	READ_CAPS(switchcaps);
+	READ_CAPS(nvmecaps);
 	READ_CAPS(niccaps);
 	READ_CAPS(toecaps);
 	READ_CAPS(rdmacaps);
@@ -5946,9 +6140,13 @@ set_params__post_init(struct adapter *sc)
 #ifdef KERN_TLS
 	if (is_ktls(sc)) {
 		sc->tlst.inline_keys = t4_tls_inline_keys;
-		sc->tlst.combo_wrs = t4_tls_combo_wrs;
-		if (t4_kern_tls != 0 && is_t6(sc))
+		if (t4_kern_tls != 0 && is_t6(sc)) {
+			sc->tlst.combo_wrs = t4_tls_combo_wrs;
 			t6_config_kern_tls(sc, true);
+		} else {
+			sc->tlst.short_records = t4_tls_short_records;
+			sc->tlst.partial_ghash = t4_tls_partial_ghash;
+		}
 	}
 #endif
 	return (0);
@@ -6220,7 +6418,7 @@ apply_link_config(struct port_info *pi)
 		MPASS(lc->pcaps & FW_PORT_CAP32_FEC_BASER_RS);
 #endif
 	if (!(sc->flags & IS_VF)) {
-		rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
+		rc = -t4_link_l1cfg(sc, sc->mbox, pi->hw_port, lc);
 		if (rc != 0) {
 			device_printf(pi->dev, "l1cfg failed: %d\n", rc);
 			return (rc);
@@ -6581,9 +6779,7 @@ cxgbe_init_synchronized(struct vi_info *vi)
 	 */
 	if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
 		sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
-		t4_write_reg(sc, is_t4(sc) ?  A_MPS_TRC_RSS_CONTROL :
-		    A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
-		    V_QUEUENUMBER(sc->traceq));
+		t4_set_trace_rss_control(sc, pi->tx_chan, sc->traceq);
 		pi->flags |= HAS_TRACEQ;
 	}
 
@@ -7443,7 +7639,7 @@ cxgbe_refresh_stats(struct vi_info *vi)
 	pi = vi->pi;
 	sc = vi->adapter;
 	tnl_cong_drops = 0;
-	t4_get_port_stats(sc, pi->port_id, &pi->stats);
+	t4_get_port_stats(sc, pi->hw_port, &pi->stats);
 	chan_map = pi->rx_e_chan_map;
 	while (chan_map) {
 		i = ffs(chan_map) - 1;
@@ -7481,6 +7677,150 @@ vi_tick(void *arg)
 	callout_schedule(&vi->tick, hz);
 }
 
+/* CIM inbound queues */
+static const char *t4_ibq[CIM_NUM_IBQ] = {
+	"ibq_tp0", "ibq_tp1", "ibq_ulp", "ibq_sge0", "ibq_sge1", "ibq_ncsi"
+};
+static const char *t7_ibq[CIM_NUM_IBQ_T7] = {
+	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
+	"ibq_sge1", "ibq_ncsi", NULL, "ibq_ipc1", "ibq_ipc2", "ibq_ipc3",
+	"ibq_ipc4", "ibq_ipc5", "ibq_ipc6", "ibq_ipc7"
+};
+static const char *t7_ibq_sec[] = {
+	"ibq_tp0", "ibq_tp1", "ibq_tp2", "ibq_tp3", "ibq_ulp", "ibq_sge0",
+	NULL, NULL, NULL, "ibq_ipc0"
+};
+
+/* CIM outbound queues */
+static const char *t4_obq[CIM_NUM_OBQ_T5] = {
+	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
+	"obq_sge_rx_q0", "obq_sge_rx_q1" /* These two are T5/T6 only */
+};
+static const char *t7_obq[CIM_NUM_OBQ_T7] = {
+	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", "obq_ncsi",
+	"obq_sge_rx_q0", NULL, NULL, "obq_ipc1", "obq_ipc2", "obq_ipc3",
+	"obq_ipc4", "obq_ipc5", "obq_ipc6", "obq_ipc7"
+};
+static const char *t7_obq_sec[] = {
+	"obq_ulp0", "obq_ulp1", "obq_ulp2", "obq_ulp3", "obq_sge", NULL,
+	"obq_sge_rx_q0", NULL, NULL, "obq_ipc0"
+};
+
+static void
+cim_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
+    struct sysctl_oid_list *c0)
+{
+	struct sysctl_oid *oid;
+	struct sysctl_oid_list *children1;
+	int i, j, qcount;
+	char s[16];
+	const char **qname;
+
+	oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "cim",
+	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM block");
+	c0 = SYSCTL_CHILDREN(oid);
+
+	SYSCTL_ADD_U8(ctx, c0, OID_AUTO, "ncores", CTLFLAG_RD, NULL,
+	    sc->params.ncores, "# of active CIM cores");
+
+	for (i = 0; i < sc->params.ncores; i++) {
+		snprintf(s, sizeof(s), "%u", i);
+		oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, s,
+		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "CIM core");
+		children1 = SYSCTL_CHILDREN(oid);
+
+		/*
+		 * CTLFLAG_SKIP because the misc.devlog sysctl already displays
+		 * the log for all cores.  Use this sysctl to get the log for a
+		 * particular core only.
+		 */
+		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "devlog",
+		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
+		    sc, i, sysctl_devlog, "A", "firmware's device log");
+
+		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "loadavg",
+		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
+		    sysctl_loadavg, "A",
+		    "microprocessor load averages (select firmwares only)");
+
+		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "qcfg",
+		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
+		    chip_id(sc) > CHELSIO_T6 ? sysctl_cim_qcfg_t7 : sysctl_cim_qcfg,
+		    "A", "Queue configuration");
+
+		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "la",
+		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
+		    sysctl_cim_la, "A", "Logic analyzer");
+
+		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "ma_la",
+		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
+		    sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
+
+		SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, "pif_la",
+		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i,
+		    sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
+
+		/* IBQs */
+		switch (chip_id(sc)) {
+		case CHELSIO_T4:
+		case CHELSIO_T5:
+		case CHELSIO_T6:
+			qname = &t4_ibq[0];
+			qcount = nitems(t4_ibq);
+			break;
+		case CHELSIO_T7:
+		default:
+			if (i == 0) {
+				qname = &t7_ibq[0];
+				qcount = nitems(t7_ibq);
+			} else {
+				qname = &t7_ibq_sec[0];
+				qcount = nitems(t7_ibq_sec);
+			}
+			break;
+		}
+		MPASS(qcount <= sc->chip_params->cim_num_ibq);
+		for (j = 0; j < qcount; j++) {
+			if (qname[j] == NULL)
+				continue;
+			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
+			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
+			    (i << 16) | j, sysctl_cim_ibq, "A", NULL);
+		}
+
+		/* OBQs */
+		switch (chip_id(sc)) {
+		case CHELSIO_T4:
+			qname = t4_obq;
+			qcount = CIM_NUM_OBQ;
+			break;
+		case CHELSIO_T5:
+		case CHELSIO_T6:
+			qname = t4_obq;
+			qcount = nitems(t4_obq);
+			break;
+		case CHELSIO_T7:
+		default:
+			if (i == 0) {
+				qname = t7_obq;
+				qcount = nitems(t7_obq);
+			} else {
+				qname = t7_obq_sec;
+				qcount = nitems(t7_obq_sec);
+			}
+			break;
+		}
+		MPASS(qcount <= sc->chip_params->cim_num_obq);
+		for (j = 0; j < qcount; j++) {
+			if (qname[j] == NULL)
+				continue;
+			SYSCTL_ADD_PROC(ctx, children1, OID_AUTO, qname[j],
+			    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
+			    (i << 16) | j, sysctl_cim_obq, "A", NULL);
+		}
+	}
+}
+
 /*
  * Should match fw_caps_config_<foo> enums in t4fw_interface.h
  */
@@ -7490,17 +7830,18 @@ static char *caps_decoder[] = {
 	"\20\001INGRESS\002EGRESS",			/* 2: switch */
 	"\20\001NIC\002VM\003IDS\004UM\005UM_ISGL"	/* 3: NIC */
 	    "\006HASHFILTER\007ETHOFLD",
-	"\20\001TOE",					/* 4: TOE */
-	"\20\001RDDP\002RDMAC",				/* 5: RDMA */
+	"\20\001TOE\002SENDPATH",			/* 4: TOE */
+	"\20\001RDDP\002RDMAC\003ROCEv2",		/* 5: RDMA */
 	"\20\001INITIATOR_PDU\002TARGET_PDU"		/* 6: iSCSI */
 	    "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
 	    "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
 	    "\007T10DIF"
 	    "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
 	"\20\001LOOKASIDE\002TLSKEYS\003IPSEC_INLINE"	/* 7: Crypto */
-	    "\004TLS_HW",
+	    "\004TLS_HW,\005TOE_IPSEC",
 	"\20\001INITIATOR\002TARGET\003CTRL_OFLD"	/* 8: FCoE */
 		    "\004PO_INITIATOR\005PO_TARGET",
+	"\20\001NVMe_TCP",				/* 9: NVMe */
 };
 
 void
@@ -7605,6 +7946,7 @@ t4_sysctls(struct adapter *sc)
 	SYSCTL_CAP(nbmcaps, 0, "NBM");
 	SYSCTL_CAP(linkcaps, 1, "link");
 	SYSCTL_CAP(switchcaps, 2, "switch");
+	SYSCTL_CAP(nvmecaps, 9, "NVMe");
 	SYSCTL_CAP(niccaps, 3, "NIC");
 	SYSCTL_CAP(toecaps, 4, "TCP offload");
 	SYSCTL_CAP(rdmacaps, 5, "RDMA");
@@ -7623,11 +7965,6 @@ t4_sysctls(struct adapter *sc)
 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
 	    sysctl_reset_sensor, "I", "reset the chip's temperature sensor.");
 
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_loadavg, "A",
-	    "microprocessor load averages (debug firmwares only)");
-
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "core_vdd",
 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_vdd,
 	    "I", "core Vdd (in mV)");
@@ -7659,81 +7996,7 @@ t4_sysctls(struct adapter *sc)
 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
 	    sysctl_cctrl, "A", "congestion control");
 
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 1,
-	    sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 2,
-	    sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 3,
-	    sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 4,
-	    sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 5,
-	    sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_cim_la, "A", "CIM logic analyzer");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-	    0 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-	    1 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-	    2 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-	    3 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-	    4 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-	    5 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
-
-	if (chip_id(sc) > CHELSIO_T4) {
-		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
-		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-		    6 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
-		    "CIM OBQ 6 (SGE0-RX)");
-
-		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
-		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc,
-		    7 + CIM_NUM_IBQ, sysctl_cim_ibq_obq, "A",
-		    "CIM OBQ 7 (SGE1-RX)");
-	}
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_cim_qcfg, "A", "CIM queue configuration");
+	cim_sysctls(sc, ctx, children);
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
@@ -7748,8 +8011,8 @@ t4_sysctls(struct adapter *sc)
 	    sysctl_tid_stats, "A", "tid stats");
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    sysctl_devlog, "A", "firmware's device log");
+	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, -1,
+	    sysctl_devlog, "A", "firmware's device log (all cores)");
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
@@ -7783,7 +8046,8 @@ t4_sysctls(struct adapter *sc)
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
 	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
+	    chip_id(sc) >= CHELSIO_T7 ? sysctl_mps_tcam_t7 :
+	    (chip_id(sc) >= CHELSIO_T6 ? sysctl_mps_tcam_t6 : sysctl_mps_tcam),
 	    "A", "MPS TCAM entries");
 
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
@@ -7855,6 +8119,14 @@ t4_sysctls(struct adapter *sc)
 			    CTLFLAG_RW, &sc->tlst.combo_wrs, 0, "Attempt to "
 			    "combine TCB field updates with TLS record work "
 			    "requests.");
+		else {
+			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "short_records",
+			    CTLFLAG_RW, &sc->tlst.short_records, 0,
+			    "Use cipher-only mode for short records.");
+			SYSCTL_ADD_INT(ctx, children, OID_AUTO, "partial_ghash",
+			    CTLFLAG_RW, &sc->tlst.partial_ghash, 0,
+			    "Use partial GHASH for AES-GCM records.");
+		}
 	}
 #endif
 
@@ -8230,86 +8502,112 @@ cxgbe_sysctls(struct port_info *pi)
 	    &pi->tx_parse_error, 0,
 	    "# of tx packets with invalid length or # of segments");
 
-#define T4_REGSTAT(name, stat, desc) \
-    SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
-	CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
-	t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \
-        sysctl_handle_t4_reg64, "QU", desc)
-
-/* We get these from port_stats and they may be stale by up to 1s */
-#define T4_PORTSTAT(name, desc) \
-	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
-	    &pi->stats.name, desc)
-
-	T4_REGSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
-	T4_REGSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
-	T4_REGSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
-	T4_REGSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
-	T4_REGSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
-	T4_REGSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
-	T4_REGSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
-	T4_REGSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
-	T4_REGSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
-	T4_REGSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
-	T4_REGSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
-	T4_REGSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
-	T4_REGSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
-	T4_REGSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
-	T4_REGSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
-	T4_REGSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
-	T4_REGSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
-	T4_REGSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
-	T4_REGSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
-	T4_REGSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
-	T4_REGSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
-	T4_REGSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
-	T4_REGSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
-
-	T4_REGSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
-	T4_REGSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
-	T4_REGSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
-	T4_REGSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
-	T4_REGSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
-	T4_REGSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
-	T4_REGSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
+#define T4_LBSTAT(name, stat, desc) do { \
+	if (sc->params.tp.lb_mode) { \
+		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
+		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, pi, \
+		    A_MPS_PORT_STAT_##stat##_L, \
+		    sysctl_handle_t4_portstat64, "QU", desc); \
+	} else { \
+		SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
+		    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
+		    t4_port_reg(sc, pi->tx_chan, A_MPS_PORT_STAT_##stat##_L), \
+		    sysctl_handle_t4_reg64, "QU", desc); \
+	} \
+} while (0)
+
+	T4_LBSTAT(tx_octets, TX_PORT_BYTES, "# of octets in good frames");
+	T4_LBSTAT(tx_frames, TX_PORT_FRAMES, "total # of good frames");
+	T4_LBSTAT(tx_bcast_frames, TX_PORT_BCAST, "# of broadcast frames");
+	T4_LBSTAT(tx_mcast_frames, TX_PORT_MCAST, "# of multicast frames");
+	T4_LBSTAT(tx_ucast_frames, TX_PORT_UCAST, "# of unicast frames");
+	T4_LBSTAT(tx_error_frames, TX_PORT_ERROR, "# of error frames");
+	T4_LBSTAT(tx_frames_64, TX_PORT_64B, "# of tx frames in this range");
+	T4_LBSTAT(tx_frames_65_127, TX_PORT_65B_127B, "# of tx frames in this range");
+	T4_LBSTAT(tx_frames_128_255, TX_PORT_128B_255B, "# of tx frames in this range");
+	T4_LBSTAT(tx_frames_256_511, TX_PORT_256B_511B, "# of tx frames in this range");
+	T4_LBSTAT(tx_frames_512_1023, TX_PORT_512B_1023B, "# of tx frames in this range");
+	T4_LBSTAT(tx_frames_1024_1518, TX_PORT_1024B_1518B, "# of tx frames in this range");
+	T4_LBSTAT(tx_frames_1519_max, TX_PORT_1519B_MAX, "# of tx frames in this range");
+	T4_LBSTAT(tx_drop, TX_PORT_DROP, "# of dropped tx frames");
+	T4_LBSTAT(tx_pause, TX_PORT_PAUSE, "# of pause frames transmitted");
+	T4_LBSTAT(tx_ppp0, TX_PORT_PPP0, "# of PPP prio 0 frames transmitted");
+	T4_LBSTAT(tx_ppp1, TX_PORT_PPP1, "# of PPP prio 1 frames transmitted");
+	T4_LBSTAT(tx_ppp2, TX_PORT_PPP2, "# of PPP prio 2 frames transmitted");
+	T4_LBSTAT(tx_ppp3, TX_PORT_PPP3, "# of PPP prio 3 frames transmitted");
+	T4_LBSTAT(tx_ppp4, TX_PORT_PPP4, "# of PPP prio 4 frames transmitted");
+	T4_LBSTAT(tx_ppp5, TX_PORT_PPP5, "# of PPP prio 5 frames transmitted");
+	T4_LBSTAT(tx_ppp6, TX_PORT_PPP6, "# of PPP prio 6 frames transmitted");
+	T4_LBSTAT(tx_ppp7, TX_PORT_PPP7, "# of PPP prio 7 frames transmitted");
+
+	T4_LBSTAT(rx_octets, RX_PORT_BYTES, "# of octets in good frames");
+	T4_LBSTAT(rx_frames, RX_PORT_FRAMES, "total # of good frames");
+	T4_LBSTAT(rx_bcast_frames, RX_PORT_BCAST, "# of broadcast frames");
+	T4_LBSTAT(rx_mcast_frames, RX_PORT_MCAST, "# of multicast frames");
+	T4_LBSTAT(rx_ucast_frames, RX_PORT_UCAST, "# of unicast frames");
+	T4_LBSTAT(rx_too_long, RX_PORT_MTU_ERROR, "# of frames exceeding MTU");
+	T4_LBSTAT(rx_jabber, RX_PORT_MTU_CRC_ERROR, "# of jabber frames");
 	if (is_t6(sc)) {
-		T4_PORTSTAT(rx_fcs_err,
+		/* Read from port_stats and may be stale by up to 1s */
+		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rx_fcs_err",
+		    CTLFLAG_RD, &pi->stats.rx_fcs_err,
 		    "# of frames received with bad FCS since last link up");
 	} else {
-		T4_REGSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
+		T4_LBSTAT(rx_fcs_err, RX_PORT_CRC_ERROR,
 		    "# of frames received with bad FCS");
 	}
-	T4_REGSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
-	T4_REGSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
-	T4_REGSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
-	T4_REGSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
-	T4_REGSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
-	T4_REGSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
-	T4_REGSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
-	T4_REGSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
-	T4_REGSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
-	T4_REGSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
-	T4_REGSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
-	T4_REGSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
-	T4_REGSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
-	T4_REGSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
-	T4_REGSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
-	T4_REGSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
-	T4_REGSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
-	T4_REGSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
-	T4_REGSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
-
-	T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows");
-	T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows");
-	T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows");
-	T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows");
-	T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets");
-	T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets");
-	T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets");
-	T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets");
+	T4_LBSTAT(rx_len_err, RX_PORT_LEN_ERROR, "# of frames received with length error");
+	T4_LBSTAT(rx_symbol_err, RX_PORT_SYM_ERROR, "symbol errors");
+	T4_LBSTAT(rx_runt, RX_PORT_LESS_64B, "# of short frames received");
+	T4_LBSTAT(rx_frames_64, RX_PORT_64B, "# of rx frames in this range");
+	T4_LBSTAT(rx_frames_65_127, RX_PORT_65B_127B, "# of rx frames in this range");
+	T4_LBSTAT(rx_frames_128_255, RX_PORT_128B_255B, "# of rx frames in this range");
+	T4_LBSTAT(rx_frames_256_511, RX_PORT_256B_511B, "# of rx frames in this range");
+	T4_LBSTAT(rx_frames_512_1023, RX_PORT_512B_1023B, "# of rx frames in this range");
+	T4_LBSTAT(rx_frames_1024_1518, RX_PORT_1024B_1518B, "# of rx frames in this range");
+	T4_LBSTAT(rx_frames_1519_max, RX_PORT_1519B_MAX, "# of rx frames in this range");
+	T4_LBSTAT(rx_pause, RX_PORT_PAUSE, "# of pause frames received");
+	T4_LBSTAT(rx_ppp0, RX_PORT_PPP0, "# of PPP prio 0 frames received");
+	T4_LBSTAT(rx_ppp1, RX_PORT_PPP1, "# of PPP prio 1 frames received");
+	T4_LBSTAT(rx_ppp2, RX_PORT_PPP2, "# of PPP prio 2 frames received");
+	T4_LBSTAT(rx_ppp3, RX_PORT_PPP3, "# of PPP prio 3 frames received");
+	T4_LBSTAT(rx_ppp4, RX_PORT_PPP4, "# of PPP prio 4 frames received");
+	T4_LBSTAT(rx_ppp5, RX_PORT_PPP5, "# of PPP prio 5 frames received");
+	T4_LBSTAT(rx_ppp6, RX_PORT_PPP6, "# of PPP prio 6 frames received");
+	T4_LBSTAT(rx_ppp7, RX_PORT_PPP7, "# of PPP prio 7 frames received");
+#undef T4_LBSTAT
+
+#define T4_REGSTAT(name, stat, desc) do { \
+	SYSCTL_ADD_OID(ctx, children, OID_AUTO, #name, \
+	    CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, \
+	    A_MPS_STAT_##stat##_L, sysctl_handle_t4_reg64, "QU", desc); \
+} while (0)
 
+	if (pi->mps_bg_map & 1) {
+		T4_REGSTAT(rx_ovflow0, RX_BG_0_MAC_DROP_FRAME,
+		    "# drops due to buffer-group 0 overflows");
+		T4_REGSTAT(rx_trunc0, RX_BG_0_MAC_TRUNC_FRAME,
+		    "# of buffer-group 0 truncated packets");
+	}
+	if (pi->mps_bg_map & 2) {
+		T4_REGSTAT(rx_ovflow1, RX_BG_1_MAC_DROP_FRAME,
+		    "# drops due to buffer-group 1 overflows");
+		T4_REGSTAT(rx_trunc1, RX_BG_1_MAC_TRUNC_FRAME,
+		    "# of buffer-group 1 truncated packets");
+	}
+	if (pi->mps_bg_map & 4) {
+		T4_REGSTAT(rx_ovflow2, RX_BG_2_MAC_DROP_FRAME,
+		    "# drops due to buffer-group 2 overflows");
+		T4_REGSTAT(rx_trunc2, RX_BG_2_MAC_TRUNC_FRAME,
+		    "# of buffer-group 2 truncated packets");
+	}
+	if (pi->mps_bg_map & 8) {
+		T4_REGSTAT(rx_ovflow3, RX_BG_3_MAC_DROP_FRAME,
+		    "# drops due to buffer-group 3 overflows");
+		T4_REGSTAT(rx_trunc3, RX_BG_3_MAC_TRUNC_FRAME,
+		    "# of buffer-group 3 truncated packets");
+	}
 #undef T4_REGSTAT
-#undef T4_PORTSTAT
 }
 
 static int
@@ -8452,14 +8750,14 @@ sysctl_tx_vm_wr(SYSCTL_HANDLER_ARGS)
 			vi->flags |= TX_USES_VM_WR;
 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_VM_TSO);
 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
-			    V_TXPKT_INTF(pi->tx_chan));
+			    V_TXPKT_INTF(pi->hw_port));
 			if (!(sc->flags & IS_VF))
 				npkt--;
 		} else {
 			vi->flags &= ~TX_USES_VM_WR;
 			if_sethwtsomaxsegcount(vi->ifp, TX_SGL_SEGS_TSO);
 			ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
-			    V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
+			    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
 		}
 		for_each_txq(vi, i, txq) {
@@ -8669,13 +8967,12 @@ sysctl_link_fec(SYSCTL_HANDLER_ARGS)
 	struct link_config *lc = &pi->link_cfg;
 	int rc;
 	struct sbuf *sb;
-	static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD1\5RSVD2";
 
 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (sb == NULL)
 		return (ENOMEM);
 	if (lc->link_ok)
-		sbuf_printf(sb, "%b", lc->fec, bits);
+		sbuf_printf(sb, "%b", lc->fec, t4_fec_bits);
 	else
 		sbuf_printf(sb, "no link");
 	rc = sbuf_finish(sb);
@@ -8695,14 +8992,12 @@ sysctl_requested_fec(SYSCTL_HANDLER_ARGS)
 
 	if (req->newptr == NULL) {
 		struct sbuf *sb;
-		static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2"
-		    "\5RSVD3\6auto\7module";
 
 		sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 		if (sb == NULL)
 			return (ENOMEM);
 
-		sbuf_printf(sb, "%b", lc->requested_fec, bits);
+		sbuf_printf(sb, "%b", lc->requested_fec, t4_fec_bits);
 		rc = sbuf_finish(sb);
 		sbuf_delete(sb);
 	} else {
@@ -8771,7 +9066,6 @@ sysctl_module_fec(SYSCTL_HANDLER_ARGS)
 	int rc;
 	int8_t fec;
 	struct sbuf *sb;
-	static char *bits = "\20\1RS-FEC\2FC-FEC\3NO-FEC\4RSVD2\5RSVD3";
 
 	sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (sb == NULL)
@@ -8805,7 +9099,7 @@ sysctl_module_fec(SYSCTL_HANDLER_ARGS)
 		if (fec == 0)
 			fec = FEC_NONE;
 		PORT_UNLOCK(pi);
-		sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, bits);
+		sbuf_printf(sb, "%b", fec & M_FW_PORT_CAP32_FEC, t4_fec_bits);
 	}
 	rc = sbuf_finish(sb);
 done:
@@ -8913,6 +9207,31 @@ sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
 }
 
 static int
+sysctl_handle_t4_portstat64(SYSCTL_HANDLER_ARGS)
+{
+	struct port_info *pi = arg1;
+	struct adapter *sc = pi->adapter;
+	int rc, i, reg = arg2;
+	uint64_t val;
+
+	mtx_lock(&sc->reg_lock);
+	if (hw_off_limits(sc))
+		rc = ENXIO;
+	else {
+		val = 0;
+		for (i = 0; i < sc->params.tp.lb_nchan; i++) {
+			val += t4_read_reg64(sc,
+			    t4_port_reg(sc, pi->tx_chan + i, reg));
+		}
+		rc = 0;
+	}
+	mtx_unlock(&sc->reg_lock);
+	if (rc == 0)
+		rc = sysctl_handle_64(oidp, &val, 0, req);
+	return (rc);
+}
+
+static int
 sysctl_temperature(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
@@ -9012,6 +9331,10 @@ sysctl_loadavg(SYSCTL_HANDLER_ARGS)
 	struct sbuf *sb;
 	int rc;
 	uint32_t param, val;
+	uint8_t coreid = (uint8_t)arg2;
+
+	KASSERT(coreid < sc->params.ncores,
+	    ("%s: bad coreid %u\n", __func__, coreid));
 
 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg");
 	if (rc)
@@ -9020,7 +9343,8 @@ sysctl_loadavg(SYSCTL_HANDLER_ARGS)
 		rc = ENXIO;
 	else {
 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
-		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD);
+		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD) |
+		    V_FW_PARAMS_PARAM_Y(coreid);
 		rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
 	}
 	end_synchronized_op(sc, 0);
@@ -9086,50 +9410,30 @@ done:
 	return (rc);
 }
 
-static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
-	"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",	/* ibq's */
-	"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",	/* obq's */
-	"SGE0-RX", "SGE1-RX"	/* additional obq's (T5 onwards) */
-};
-
 static int
-sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
+sysctl_cim_ibq(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
 	struct sbuf *sb;
-	int rc, i, n, qid = arg2;
+	int rc, i, n, qid, coreid;
 	uint32_t *buf, *p;
-	char *qtype;
-	u_int cim_num_obq = sc->chip_params->cim_num_obq;
 
-	KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
-	    ("%s: bad qid %d\n", __func__, qid));
+	qid = arg2 & 0xffff;
+	coreid = arg2 >> 16;
 
-	if (qid < CIM_NUM_IBQ) {
-		/* inbound queue */
-		qtype = "IBQ";
-		n = 4 * CIM_IBQ_SIZE;
-		buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
-		mtx_lock(&sc->reg_lock);
-		if (hw_off_limits(sc))
-			rc = -ENXIO;
-		else
-			rc = t4_read_cim_ibq(sc, qid, buf, n);
-		mtx_unlock(&sc->reg_lock);
-	} else {
-		/* outbound queue */
-		qtype = "OBQ";
-		qid -= CIM_NUM_IBQ;
-		n = 4 * cim_num_obq * CIM_OBQ_SIZE;
-		buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
-		mtx_lock(&sc->reg_lock);
-		if (hw_off_limits(sc))
-			rc = -ENXIO;
-		else
-			rc = t4_read_cim_obq(sc, qid, buf, n);
-		mtx_unlock(&sc->reg_lock);
-	}
+	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_ibq,
+	    ("%s: bad ibq qid %d\n", __func__, qid));
+	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
+	    ("%s: bad coreid %d\n", __func__, coreid));
 
+	n = 4 * CIM_IBQ_SIZE;
+	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
+	mtx_lock(&sc->reg_lock);
+	if (hw_off_limits(sc))
+		rc = -ENXIO;
+	else
+		rc = t4_read_cim_ibq_core(sc, coreid, qid, buf, n);
+	mtx_unlock(&sc->reg_lock);
 	if (rc < 0) {
 		rc = -rc;
 		goto done;
@@ -9141,12 +9445,58 @@ sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
 		rc = ENOMEM;
 		goto done;
 	}
-
-	sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
 	for (i = 0, p = buf; i < n; i += 16, p += 4)
 		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
 		    p[2], p[3]);
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+done:
+	free(buf, M_CXGBE);
+	return (rc);
+}
+
+static int
+sysctl_cim_obq(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i, n, qid, coreid;
+	uint32_t *buf, *p;
+
+	qid = arg2 & 0xffff;
+	coreid = arg2 >> 16;
+
+	KASSERT(qid >= 0 && qid < sc->chip_params->cim_num_obq,
+	    ("%s: bad obq qid %d\n", __func__, qid));
+	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
+	    ("%s: bad coreid %d\n", __func__, coreid));
+
+	n = 6 * CIM_OBQ_SIZE * 4;
+	buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
+	mtx_lock(&sc->reg_lock);
+	if (hw_off_limits(sc))
+		rc = -ENXIO;
+	else
+		rc = t4_read_cim_obq_core(sc, coreid, qid, buf, n);
+	mtx_unlock(&sc->reg_lock);
+	if (rc < 0) {
+		rc = -rc;
+		goto done;
+	}
+	n = rc * sizeof(uint32_t);	/* rc has # of words actually read */
 
+	rc = sysctl_wire_old_buffer(req, 0);
+	if (rc != 0)
+		goto done;
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
+	if (sb == NULL) {
+		rc = ENOMEM;
+		goto done;
+	}
+	for (i = 0, p = buf; i < n; i += 16, p += 4)
+		sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
+		    p[2], p[3]);
 	rc = sbuf_finish(sb);
 	sbuf_delete(sb);
 done:
@@ -9217,7 +9567,7 @@ sbuf_cim_la6(struct adapter *sc, struct sbuf *sb, uint32_t *buf, uint32_t cfg)
 }
 
 static int
-sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
+sbuf_cim_la(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
 {
 	uint32_t cfg, *buf;
 	int rc;
@@ -9232,9 +9582,10 @@ sbuf_cim_la(struct adapter *sc, struct sbuf *sb, int flags)
 	if (hw_off_limits(sc))
 		rc = ENXIO;
 	else {
-		rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
+		rc = -t4_cim_read_core(sc, 1, coreid, A_UP_UP_DBG_LA_CFG, 1,
+		    &cfg);
 		if (rc == 0)
-			rc = -t4_cim_read_la(sc, buf, NULL);
+			rc = -t4_cim_read_la_core(sc, coreid, buf, NULL);
 	}
 	mtx_unlock(&sc->reg_lock);
 	if (rc == 0) {
@@ -9251,6 +9602,7 @@ static int
 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
+	int coreid = arg2;
 	struct sbuf *sb;
 	int rc;
 
@@ -9258,7 +9610,7 @@ sysctl_cim_la(SYSCTL_HANDLER_ARGS)
 	if (sb == NULL)
 		return (ENOMEM);
 
-	rc = sbuf_cim_la(sc, sb, M_WAITOK);
+	rc = sbuf_cim_la(sc, coreid, sb, M_WAITOK);
 	if (rc == 0)
 		rc = sbuf_finish(sb);
 	sbuf_delete(sb);
@@ -9295,7 +9647,7 @@ dump_cimla(struct adapter *sc)
 		    device_get_nameunit(sc->dev));
 		return;
 	}
-	rc = sbuf_cim_la(sc, &sb, M_WAITOK);
+	rc = sbuf_cim_la(sc, 0, &sb, M_WAITOK);
 	if (rc == 0) {
 		rc = sbuf_finish(&sb);
 		if (rc == 0) {
@@ -9419,6 +9771,13 @@ sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
 	uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
 	uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
 	u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
+	static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
+		"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",	/* ibq's */
+		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",	/* obq's */
+		"SGE0-RX", "SGE1-RX"	/* additional obq's (T5 onwards) */
+	};
+
+	MPASS(chip_id(sc) < CHELSIO_T7);
 
 	cim_num_obq = sc->chip_params->cim_num_obq;
 	if (is_t4(sc)) {
@@ -9471,6 +9830,104 @@ sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
 }
 
 static int
+sysctl_cim_qcfg_t7(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	u_int coreid = arg2;
+	struct sbuf *sb;
+	int rc, i;
+	u_int addr;
+	uint16_t base[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+	uint16_t size[CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7];
+	uint16_t thres[CIM_NUM_IBQ_T7];
+	uint32_t obq_wr[2 * CIM_NUM_OBQ_T7], *wr = obq_wr;
+	uint32_t stat[4 * (CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7)], *p = stat;
+	static const char * const qname_ibq_t7[] = {
+		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "SGE1", "NC-SI",
+		"RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5", "IPC6", "IPC7",
+	};
+	static const char * const qname_obq_t7[] = {
+		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", "SGE0-RX",
+		"RSVD", "RSVD", "IPC1", "IPC2", "IPC3", "IPC4", "IPC5",
+		"IPC6", "IPC7"
+	};
+	static const char * const qname_ibq_sec_t7[] = {
+		"TP0", "TP1", "TP2", "TP3", "ULP", "SGE0", "RSVD", "RSVD",
+		"RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",	"RSVD", "RSVD",
+	};
+	static const char * const qname_obq_sec_t7[] = {
+		"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "RSVD", "SGE0-RX",
+		"RSVD", "RSVD", "IPC0", "RSVD", "RSVD", "RSVD", "RSVD",
+		"RSVD", "RSVD",
+	};
+
+	MPASS(chip_id(sc) >= CHELSIO_T7);
+
+	mtx_lock(&sc->reg_lock);
+	if (hw_off_limits(sc))
+		rc = ENXIO;
+	else {
+		rc = -t4_cim_read_core(sc, 1, coreid,
+		    A_T7_UP_IBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_IBQ_T7, stat);
+		if (rc != 0)
+			goto unlock;
+
+		rc = -t4_cim_read_core(sc, 1, coreid,
+		    A_T7_UP_OBQ_0_SHADOW_RDADDR, 4 * CIM_NUM_OBQ_T7,
+		    &stat[4 * CIM_NUM_IBQ_T7]);
+		if (rc != 0)
+			goto unlock;
+
+		addr = A_T7_UP_OBQ_0_SHADOW_REALADDR;
+		for (i = 0; i < CIM_NUM_OBQ_T7 * 2; i++, addr += 8) {
+			rc = -t4_cim_read_core(sc, 1, coreid, addr, 1,
+			    &obq_wr[i]);
+			if (rc != 0)
+				goto unlock;
+		}
+		t4_read_cimq_cfg_core(sc, coreid, base, size, thres);
+	}
+unlock:
+	mtx_unlock(&sc->reg_lock);
+	if (rc)
+		return (rc);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	sbuf_printf(sb,
+	    "  Queue  Base  Size Thres  RdPtr WrPtr  SOP  EOP Avail");
+
+	for (i = 0; i < CIM_NUM_IBQ_T7; i++, p += 4) {
+		if (!size[i])
+			continue;
+
+		sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
+		    coreid == 0 ? qname_ibq_t7[i] : qname_ibq_sec_t7[i],
+		    base[i], size[i], thres[i], G_IBQRDADDR(p[0]) & 0xfff,
+		    G_IBQWRADDR(p[1]) & 0xfff, G_QUESOPCNT(p[3]),
+		    G_QUEEOPCNT(p[3]), G_T7_QUEREMFLITS(p[2]) * 16);
+	}
+
+	for ( ; i < CIM_NUM_IBQ_T7 + CIM_NUM_OBQ_T7; i++, p += 4, wr += 2) {
+		if (!size[i])
+			continue;
+
+		sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u",
+		    coreid == 0 ? qname_obq_t7[i - CIM_NUM_IBQ_T7] :
+		    qname_obq_sec_t7[i - CIM_NUM_IBQ_T7],
+		    base[i], size[i], G_QUERDADDR(p[0]) & 0xfff,
+		    wr[0] << 1, G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
+		    G_T7_QUEREMFLITS(p[2]) * 16);
+	}
+
+	rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+	return (rc);
+}
+
+static int
 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
@@ -9612,18 +10069,25 @@ static const char * const devlog_facility_strings[] = {
 };
 
 static int
-sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
+sbuf_devlog(struct adapter *sc, int coreid, struct sbuf *sb, int flags)
 {
 	int i, j, rc, nentries, first = 0;
 	struct devlog_params *dparams = &sc->params.devlog;
 	struct fw_devlog_e *buf, *e;
+	uint32_t addr, size;
 	uint64_t ftstamp = UINT64_MAX;
 
+	KASSERT(coreid >= 0 && coreid < sc->params.ncores,
+	    ("%s: bad coreid %d\n", __func__, coreid));
+
 	if (dparams->addr == 0)
 		return (ENXIO);
 
+	size = dparams->size / sc->params.ncores;
+	addr = dparams->addr + coreid * size;
+
 	MPASS(flags == M_WAITOK || flags == M_NOWAIT);
-	buf = malloc(dparams->size, M_CXGBE, M_ZERO | flags);
+	buf = malloc(size, M_CXGBE, M_ZERO | flags);
 	if (buf == NULL)
 		return (ENOMEM);
 
@@ -9631,13 +10095,12 @@ sbuf_devlog(struct adapter *sc, struct sbuf *sb, int flags)
 	if (hw_off_limits(sc))
 		rc = ENXIO;
 	else
-		rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf,
-		    dparams->size);
+		rc = read_via_memwin(sc, 1, addr, (void *)buf, size);
 	mtx_unlock(&sc->reg_lock);
 	if (rc != 0)
 		goto done;
 
-	nentries = dparams->size / sizeof(struct fw_devlog_e);
+	nentries = size / sizeof(struct fw_devlog_e);
 	for (i = 0; i < nentries; i++) {
 		e = &buf[i];
 
@@ -9689,14 +10152,24 @@ static int
 sysctl_devlog(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
-	int rc;
+	int rc, i, coreid = arg2;
 	struct sbuf *sb;
 
 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
 	if (sb == NULL)
 		return (ENOMEM);
-
-	rc = sbuf_devlog(sc, sb, M_WAITOK);
+	if (coreid == -1) {
+		/* -1 means all cores */
+		for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
+			if (sc->params.ncores > 0)
+				sbuf_printf(sb, "=== CIM core %u ===\n", i);
+			rc = sbuf_devlog(sc, i, sb, M_WAITOK);
+		}
+	} else {
+		KASSERT(coreid >= 0 && coreid < sc->params.ncores,
+		    ("%s: bad coreid %d\n", __func__, coreid));
+		rc = sbuf_devlog(sc, coreid, sb, M_WAITOK);
+	}
 	if (rc == 0)
 		rc = sbuf_finish(sb);
 	sbuf_delete(sb);
@@ -9706,7 +10179,7 @@ sysctl_devlog(SYSCTL_HANDLER_ARGS)
 static void
 dump_devlog(struct adapter *sc)
 {
-	int rc;
+	int rc, i;
 	struct sbuf sb;
 
 	if (sbuf_new(&sb, NULL, 4096, SBUF_AUTOEXTEND) != &sb) {
@@ -9714,13 +10187,15 @@ dump_devlog(struct adapter *sc)
 		    device_get_nameunit(sc->dev));
 		return;
 	}
-	rc = sbuf_devlog(sc, &sb, M_WAITOK);
+	for (i = rc = 0; i < sc->params.ncores && rc == 0; i++) {
+		if (sc->params.ncores > 0)
+			sbuf_printf(&sb, "=== CIM core %u ===\n", i);
+		rc = sbuf_devlog(sc, i, &sb, M_WAITOK);
+	}
 	if (rc == 0) {
-		rc = sbuf_finish(&sb);
-		if (rc == 0) {
-			log(LOG_DEBUG, "%s: device log follows.\n%s",
-			    device_get_nameunit(sc->dev), sbuf_data(&sb));
-		}
+		sbuf_finish(&sb);
+		log(LOG_DEBUG, "%s: device log follows.\n%s",
+		    device_get_nameunit(sc->dev), sbuf_data(&sb));
 	}
 	sbuf_delete(&sb);
 }
@@ -9909,16 +10384,16 @@ sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
 }
 
 struct mem_desc {
-	u_int base;
-	u_int limit;
+	uint64_t base;
+	uint64_t limit;
 	u_int idx;
 };
 
 static int
 mem_desc_cmp(const void *a, const void *b)
 {
-	const u_int v1 = ((const struct mem_desc *)a)->base;
-	const u_int v2 = ((const struct mem_desc *)b)->base;
+	const uint64_t v1 = ((const struct mem_desc *)a)->base;
+	const uint64_t v2 = ((const struct mem_desc *)b)->base;
 
 	if (v1 < v2)
 		return (-1);
@@ -9929,10 +10404,9 @@ mem_desc_cmp(const void *a, const void *b)
 }
 
 static void
-mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
-    unsigned int to)
+mem_region_show(struct sbuf *sb, const char *name, uint64_t from, uint64_t to)
 {
-	unsigned int size;
+	uintmax_t size;
 
 	if (from == to)
 		return;
@@ -9941,8 +10415,12 @@ mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
 	if (size == 0)
 		return;
 
-	/* XXX: need humanize_number(3) in libkern for a more readable 'size' */
-	sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
+	if (from > UINT32_MAX || to > UINT32_MAX)
+		sbuf_printf(sb, "%-18s 0x%012jx-0x%012jx [%ju]\n", name,
+		    (uintmax_t)from, (uintmax_t)to, size);
+	else
+		sbuf_printf(sb, "%-18s 0x%08jx-0x%08jx [%ju]\n", name,
+		    (uintmax_t)from, (uintmax_t)to, size);
 }
 
 static int
@@ -9950,7 +10428,7 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
 	struct sbuf *sb;
-	int rc, i, n;
+	int rc, i, n, nchan;
 	uint32_t lo, hi, used, free, alloc;
 	static const char *memory[] = {
 		"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:", "HMA:"
@@ -9961,12 +10439,14 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 		"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
 		"TDDP region:", "TPT region:", "STAG region:", "RQ region:",
 		"RQUDP region:", "PBL region:", "TXPBL region:",
-		"TLSKey region:", "DBVFIFO region:", "ULPRX state:",
-		"ULPTX state:", "On-chip queues:",
+		"TLSKey region:", "RRQ region:", "NVMe STAG region:",
+		"NVMe RQ region:", "NVMe RXPBL region:", "NVMe TPT region:",
+		"NVMe TXPBL region:", "DBVFIFO region:", "ULPRX state:",
+		"ULPTX state:", "RoCE RRQ region:", "On-chip queues:",
 	};
 	struct mem_desc avail[4];
 	struct mem_desc mem[nitems(region) + 3];	/* up to 3 holes */
-	struct mem_desc *md = mem;
+	struct mem_desc *md;
 
 	rc = sysctl_wire_old_buffer(req, 0);
 	if (rc != 0)
@@ -9992,36 +10472,91 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 	lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
 	if (lo & F_EDRAM0_ENABLE) {
 		hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
-		avail[i].base = G_EDRAM0_BASE(hi) << 20;
-		avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
+		if (chip_id(sc) >= CHELSIO_T7) {
+			avail[i].base = (uint64_t)G_T7_EDRAM0_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_T7_EDRAM0_SIZE(hi) << 20);
+		} else {
+			avail[i].base = (uint64_t)G_EDRAM0_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_EDRAM0_SIZE(hi) << 20);
+		}
 		avail[i].idx = 0;
 		i++;
 	}
 	if (lo & F_EDRAM1_ENABLE) {
 		hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
-		avail[i].base = G_EDRAM1_BASE(hi) << 20;
-		avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
+		if (chip_id(sc) >= CHELSIO_T7) {
+			avail[i].base = (uint64_t)G_T7_EDRAM1_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_T7_EDRAM1_SIZE(hi) << 20);
+		} else {
+			avail[i].base = (uint64_t)G_EDRAM1_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_EDRAM1_SIZE(hi) << 20);
+		}
 		avail[i].idx = 1;
 		i++;
 	}
 	if (lo & F_EXT_MEM_ENABLE) {
-		hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
-		avail[i].base = G_EXT_MEM_BASE(hi) << 20;
-		avail[i].limit = avail[i].base + (G_EXT_MEM_SIZE(hi) << 20);
-		avail[i].idx = is_t5(sc) ? 3 : 2;	/* Call it MC0 for T5 */
+		switch (chip_id(sc)) {
+		case CHELSIO_T4:
+		case CHELSIO_T6:
+			hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
+			avail[i].base = (uint64_t)G_EXT_MEM_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_EXT_MEM_SIZE(hi) << 20);
+			avail[i].idx = 2;
+			break;
+		case CHELSIO_T5:
+			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
+			avail[i].base = (uint64_t)G_EXT_MEM0_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_EXT_MEM0_SIZE(hi) << 20);
+			avail[i].idx = 3;	/* Call it MC0 for T5 */
+			break;
+		default:
+			hi = t4_read_reg(sc, A_MA_EXT_MEMORY0_BAR);
+			avail[i].base = (uint64_t)G_T7_EXT_MEM0_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_T7_EXT_MEM0_SIZE(hi) << 20);
+			avail[i].idx = 3;	/* Call it MC0 for T7+ */
+			break;
+		}
 		i++;
 	}
-	if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
+	if (lo & F_EXT_MEM1_ENABLE && !(lo & F_MC_SPLIT)) {
+		/* Only T5 and T7+ have 2 MCs. */
+		MPASS(is_t5(sc) || chip_id(sc) >= CHELSIO_T7);
+
 		hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
-		avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
-		avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20);
+		if (chip_id(sc) >= CHELSIO_T7) {
+			avail[i].base = (uint64_t)G_T7_EXT_MEM1_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_T7_EXT_MEM1_SIZE(hi) << 20);
+		} else {
+			avail[i].base = (uint64_t)G_EXT_MEM1_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_EXT_MEM1_SIZE(hi) << 20);
+		}
 		avail[i].idx = 4;
 		i++;
 	}
-	if (is_t6(sc) && lo & F_HMA_MUX) {
-		hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
-		avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
-		avail[i].limit = avail[i].base + (G_EXT_MEM1_SIZE(hi) << 20);
+	if (lo & F_HMA_MUX) {
+		/* Only T6+ have HMA. */
+		MPASS(chip_id(sc) >= CHELSIO_T6);
+
+		if (chip_id(sc) >= CHELSIO_T7) {
+			hi = t4_read_reg(sc, A_MA_HOST_MEMORY_BAR);
+			avail[i].base = (uint64_t)G_HMATARGETBASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_T7_HMA_SIZE(hi) << 20);
+		} else {
+			hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
+			avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
+			avail[i].limit = avail[i].base +
+			    (G_EXT_MEM1_SIZE(hi) << 20);
+		}
 		avail[i].idx = 5;
 		i++;
 	}
@@ -10030,6 +10565,7 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 		goto done;
 	qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
 
+	md = &mem[0];
 	(md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
 	(md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
 	(md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
@@ -10065,22 +10601,52 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 	}
 	md++;
 
-#define ulp_region(reg) \
-	md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
-	(md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
+#define ulp_region(reg) do {\
+		const u_int shift = chip_id(sc) >= CHELSIO_T7 ? 4 : 0; \
+		md->base = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT) << shift; \
+		md->limit = (uint64_t)t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) << shift; \
+		md->limit += (1 << shift) - 1; \
+		md++; \
+	} while (0)
+
+#define	hide_ulp_region() do { \
+		md->base = 0; \
+		md->idx = nitems(region); \
+		md++; \
+	} while (0)
 
 	ulp_region(RX_ISCSI);
 	ulp_region(RX_TDDP);
 	ulp_region(TX_TPT);
 	ulp_region(RX_STAG);
 	ulp_region(RX_RQ);
-	ulp_region(RX_RQUDP);
+	if (chip_id(sc) < CHELSIO_T7)
+		ulp_region(RX_RQUDP);
+	else
+		hide_ulp_region();
 	ulp_region(RX_PBL);
 	ulp_region(TX_PBL);
-	if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) {
+	if (chip_id(sc) >= CHELSIO_T6)
 		ulp_region(RX_TLS_KEY);
+	else
+		hide_ulp_region();
+	if (chip_id(sc) >= CHELSIO_T7) {
+		ulp_region(RX_RRQ);
+		ulp_region(RX_NVME_TCP_STAG);
+		ulp_region(RX_NVME_TCP_RQ);
+		ulp_region(RX_NVME_TCP_PBL);
+		ulp_region(TX_NVME_TCP_TPT);
+		ulp_region(TX_NVME_TCP_PBL);
+	} else {
+		hide_ulp_region();
+		hide_ulp_region();
+		hide_ulp_region();
+		hide_ulp_region();
+		hide_ulp_region();
+		hide_ulp_region();
 	}
 #undef ulp_region
+#undef hide_ulp_region
 
 	md->base = 0;
 	if (is_t4(sc))
@@ -10111,6 +10677,15 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 	md->limit = 0;
 	md++;
 
+	if (chip_id(sc) >= CHELSIO_T7) {
+		t4_tp_pio_read(sc, &lo, 1, A_TP_ROCE_RRQ_BASE, false);
+		md->base = lo;
+	} else {
+		md->base = 0;
+		md->idx = nitems(region);
+	}
+	md++;
+
 	md->base = sc->vres.ocq.start;
 	if (sc->vres.ocq.size)
 		md->limit = md->base + sc->vres.ocq.size - 1;
@@ -10143,31 +10718,41 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 				mem[i].limit);
 	}
 
-	sbuf_printf(sb, "\n");
 	lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
 	hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
-	mem_region_show(sb, "uP RAM:", lo, hi);
+	if (hi != lo  - 1) {
+		sbuf_printf(sb, "\n");
+		mem_region_show(sb, "uP RAM:", lo, hi);
+	}
 
 	lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
 	hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
-	mem_region_show(sb, "uP Extmem2:", lo, hi);
+	if (hi != lo  - 1)
+		mem_region_show(sb, "uP Extmem2:", lo, hi);
 
 	lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
-	for (i = 0, free = 0; i < 2; i++)
+	if (chip_id(sc) >= CHELSIO_T7)
+		nchan = 1 << G_T7_PMRXNUMCHN(lo);
+	else
+		nchan = lo & F_PMRXNUMCHN ? 2 : 1;
+	for (i = 0, free = 0; i < nchan; i++)
 		free += G_FREERXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_RX_CNT));
 	sbuf_printf(sb, "\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
 		   G_PMRXMAXPAGE(lo), free,
-		   t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
-		   (lo & F_PMRXNUMCHN) ? 2 : 1);
+		   t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, nchan);
 
 	lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
 	hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
-	for (i = 0, free = 0; i < 4; i++)
+	if (chip_id(sc) >= CHELSIO_T7)
+		nchan = 1 << G_T7_PMTXNUMCHN(lo);
+	else
+		nchan = 1 << G_PMTXNUMCHN(lo);
+	for (i = 0, free = 0; i < nchan; i++)
 		free += G_FREETXPAGECOUNT(t4_read_reg(sc, A_TP_FLM_FREE_TX_CNT));
 	sbuf_printf(sb, "%u Tx pages (%u free) of size %u%ciB for %u channels\n",
 		   G_PMTXMAXPAGE(lo), free,
 		   hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
-		   hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
+		   hi >= (1 << 20) ? 'M' : 'K', nchan);
 	sbuf_printf(sb, "%u p-structs (%u free)\n",
 		   t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT),
 		   G_FREEPSTRUCTCOUNT(t4_read_reg(sc, A_TP_FLM_FREE_PS_CNT)));
@@ -10184,7 +10769,7 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 			used = G_USED(lo);
 			alloc = G_ALLOC(lo);
 		}
-		/* For T6 these are MAC buffer groups */
+		/* For T6+ these are MAC buffer groups */
 		sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
 		    i, used, alloc);
 	}
@@ -10200,7 +10785,7 @@ sysctl_meminfo(SYSCTL_HANDLER_ARGS)
 			used = G_USED(lo);
 			alloc = G_ALLOC(lo);
 		}
-		/* For T6 these are MAC buffer groups */
+		/* For T6+ these are MAC buffer groups */
 		sbuf_printf(sb,
 		    "\nLoopback %d using %u pages out of %u allocated",
 		    i, used, alloc);
@@ -10329,7 +10914,7 @@ sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
 	struct sbuf *sb;
 	int rc, i;
 
-	MPASS(chip_id(sc) > CHELSIO_T5);
+	MPASS(chip_id(sc) == CHELSIO_T6);
 
 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
 	if (sb == NULL)
@@ -10338,7 +10923,7 @@ sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
 	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
 	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
 	    "                           Replication"
-	    "                                    P0 P1 P2 P3  ML\n");
+	    "                                    P0 P1 P2 P3  ML");
 
 	rc = 0;
 	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
@@ -10503,6 +11088,206 @@ sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
 }
 
 static int
+sysctl_mps_tcam_t7(SYSCTL_HANDLER_ARGS)
+{
+	struct adapter *sc = arg1;
+	struct sbuf *sb;
+	int rc, i;
+
+	MPASS(chip_id(sc) >= CHELSIO_T7);
+
+	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
+	if (sb == NULL)
+		return (ENOMEM);
+
+	sbuf_printf(sb, "Idx  Ethernet address     Mask       VNI   Mask"
+	    "   IVLAN Vld DIP_Hit   Lookup  Port Vld Ports PF  VF"
+	    "                           Replication"
+	    "                                    P0 P1 P2 P3  ML");
+
+	rc = 0;
+	for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
+		uint8_t dip_hit, vlan_vld, lookup_type, port_num;
+		uint16_t ivlan;
+		uint64_t tcamx, tcamy, val, mask;
+		uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
+		uint8_t addr[ETHER_ADDR_LEN];
+
+		/* Read tcamy */
+		ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
+		if (chip_rev(sc) == 0) {
+			if (i < 256)
+				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
+			else
+				ctl |= V_CTLTCAMINDEX(i - 256) | V_T7_CTLTCAMSEL(1);
+		} else {
+#if 0
+			ctl = (V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
+#endif
+			if (i < 512)
+				ctl |= V_CTLTCAMINDEX(i) | V_T7_CTLTCAMSEL(0);
+			else if (i < 1024)
+				ctl |= V_CTLTCAMINDEX(i - 512) | V_T7_CTLTCAMSEL(1);
+			else
+				ctl |= V_CTLTCAMINDEX(i - 1024) | V_T7_CTLTCAMSEL(2);
+		}
+
+		mtx_lock(&sc->reg_lock);
+		if (hw_off_limits(sc))
+			rc = ENXIO;
+		else {
+			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
+			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
+			tcamy = G_DMACH(val) << 32;
+			tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
+			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
+		}
+		mtx_unlock(&sc->reg_lock);
+		if (rc != 0)
+			break;
+
+		lookup_type = G_DATALKPTYPE(data2);
+		port_num = G_DATAPORTNUM(data2);
+		if (lookup_type && lookup_type != M_DATALKPTYPE) {
+			/* Inner header VNI */
+			vniy = (((data2 & F_DATAVIDH2) |
+			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
+			dip_hit = data2 & F_DATADIPHIT;
+			vlan_vld = 0;
+		} else {
+			vniy = 0;
+			dip_hit = 0;
+			vlan_vld = data2 & F_DATAVIDH2;
+			ivlan = G_VIDL(val);
+		}
+
+		ctl |= V_CTLXYBITSEL(1);
+		mtx_lock(&sc->reg_lock);
+		if (hw_off_limits(sc))
+			rc = ENXIO;
+		else {
+			t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
+			val = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA1_REQ_ID1);
+			tcamx = G_DMACH(val) << 32;
+			tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA0_REQ_ID1);
+			data2 = t4_read_reg(sc, A_MPS_CLS_TCAM0_RDATA2_REQ_ID1);
+		}
+		mtx_unlock(&sc->reg_lock);
+		if (rc != 0)
+			break;
+
+		if (lookup_type && lookup_type != M_DATALKPTYPE) {
+			/* Inner header VNI mask */
+			vnix = (((data2 & F_DATAVIDH2) |
+			    G_DATAVIDH1(data2)) << 16) | G_VIDL(val);
+		} else
+			vnix = 0;
+
+		if (tcamx & tcamy)
+			continue;
+		tcamxy2valmask(tcamx, tcamy, addr, &mask);
+
+		mtx_lock(&sc->reg_lock);
+		if (hw_off_limits(sc))
+			rc = ENXIO;
+		else {
+			if (chip_rev(sc) == 0) {
+				cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
+				cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
+			} else {
+				t4_write_reg(sc, A_MPS_CLS_SRAM_H,
+				    V_SRAMWRN(0) | V_SRAMINDEX(i));
+				cls_lo = t4_read_reg(sc, A_MPS_CLS_SRAM_L);
+				cls_hi = t4_read_reg(sc, A_MPS_CLS_SRAM_H);
+			}
+		}
+		mtx_unlock(&sc->reg_lock);
+		if (rc != 0)
+			break;
+
+		if (lookup_type && lookup_type != M_DATALKPTYPE) {
+			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
+			    "%012jx %06x %06x    -    -   %3c"
+			    "        I  %4x   %3c   %#x%4u%4d", i, addr[0],
+			    addr[1], addr[2], addr[3], addr[4], addr[5],
+			    (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
+			    port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
+			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
+			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
+		} else {
+			sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
+			    "%012jx    -       -   ", i, addr[0], addr[1],
+			    addr[2], addr[3], addr[4], addr[5],
+			    (uintmax_t)mask);
+
+			if (vlan_vld)
+				sbuf_printf(sb, "%4u   Y     ", ivlan);
+			else
+				sbuf_printf(sb, "  -    N     ");
+
+			sbuf_printf(sb, "-      %3c  %4x   %3c   %#x%4u%4d",
+			    lookup_type ? 'I' : 'O', port_num,
+			    cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
+			    G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
+			    cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
+		}
+
+		if (cls_lo & F_T6_REPLICATE) {
+			struct fw_ldst_cmd ldst_cmd;
+
+			memset(&ldst_cmd, 0, sizeof(ldst_cmd));
+			ldst_cmd.op_to_addrspace =
+			    htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
+				F_FW_CMD_REQUEST | F_FW_CMD_READ |
+				V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
+			ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
+			ldst_cmd.u.mps.rplc.fid_idx =
+			    htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
+				V_FW_LDST_CMD_IDX(i));
+
+			rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
+			    "t6mps");
+			if (rc)
+				break;
+			if (hw_off_limits(sc))
+				rc = ENXIO;
+			else
+				rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
+				    sizeof(ldst_cmd), &ldst_cmd);
+			end_synchronized_op(sc, 0);
+			if (rc != 0)
+				break;
+			else {
+				sbuf_printf(sb, " %08x %08x %08x %08x"
+				    " %08x %08x %08x %08x",
+				    be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
+				    be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
+			}
+		} else
+			sbuf_printf(sb, "%72s", "");
+
+		sbuf_printf(sb, "%4u%3u%3u%3u %#x",
+		    G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
+		    G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
+		    (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
+	}
+
+	if (rc)
+		(void) sbuf_finish(sb);
+	else
+		rc = sbuf_finish(sb);
+	sbuf_delete(sb);
+
+	return (rc);
+}
+
+static int
 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
 {
 	struct adapter *sc = arg1;
@@ -10543,6 +11328,7 @@ sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
 	int rc, i;
 	uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
 	uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
+	uint32_t stats[T7_PM_RX_CACHE_NSTATS];
 	static const char *tx_stats[MAX_PM_NSTATS] = {
 		"Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
 		"Tx FIFO wait", NULL, "Tx latency"
@@ -10559,12 +11345,14 @@ sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
 	else {
 		t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
 		t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
+		if (chip_id(sc) >= CHELSIO_T7)
+			t4_pmrx_cache_get_stats(sc, stats);
 	}
 	mtx_unlock(&sc->reg_lock);
 	if (rc != 0)
 		return (rc);
 
-	sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
+	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
 	if (sb == NULL)
 		return (ENOMEM);
 
@@ -10599,6 +11387,61 @@ sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
 		    rx_cyc[i]);
 	}
 
+	if (chip_id(sc) >= CHELSIO_T7) {
+		i = 0;
+		sbuf_printf(sb, "\n\nPM RX Cache Stats\n");
+		sbuf_printf(sb, "%-40s    %u\n", "ReqWrite", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "ReqReadInv", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "ReqReadNoInv", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Write Split Request",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Normal Read Split (Read Invalidate)", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Feedback Read Split (Read NoInvalidate)",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Write Hit", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Feedback Read Hit",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full Avail",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Hit Full UnAvail",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Normal Read Hit Partial Avail",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full Avail",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Full UnAvail",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "FB Read Hit Partial Avail",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Normal Read Full Free",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Normal Read Part-avail Mul-Regions",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "FB Read Part-avail Mul-Regions",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Write Miss FL Used",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Write Miss LRU Used",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Write Miss LRU-Multiple Evict", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Write Hit Increasing Islands", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n",
+			   "Normal Read Island Read split", stats[i++]);
+		sbuf_printf(sb, "%-40s    %u\n", "Write Overflow Eviction",
+			   stats[i++]);
+		sbuf_printf(sb, "%-40s    %u", "Read Overflow Eviction",
+			   stats[i++]);
+	}
+
 	rc = sbuf_finish(sb);
 	sbuf_delete(sb);
 
@@ -11609,15 +12452,17 @@ sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS)
 #endif
 
 static int
-get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
+get_sge_context(struct adapter *sc, int mem_id, uint32_t cid, int len,
+    uint32_t *data)
 {
 	int rc;
 
-	if (cntxt->cid > M_CTXTQID)
+	if (len < sc->chip_params->sge_ctxt_size)
+		return (ENOBUFS);
+	if (cid > M_CTXTQID)
 		return (EINVAL);
-
-	if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
-	    cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
+	if (mem_id != CTXT_EGRESS && mem_id != CTXT_INGRESS &&
+	    mem_id != CTXT_FLM && mem_id != CTXT_CNM)
 		return (EINVAL);
 
 	rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
@@ -11630,8 +12475,7 @@ get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
 	}
 
 	if (sc->flags & FW_OK) {
-		rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
-		    &cntxt->data[0]);
+		rc = -t4_sge_ctxt_rd(sc, sc->mbox, cid, mem_id, data);
 		if (rc == 0)
 			goto done;
 	}
@@ -11640,7 +12484,7 @@ get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
 	 * Read via firmware failed or wasn't even attempted.  Read directly via
 	 * the backdoor.
 	 */
-	rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
+	rc = -t4_sge_ctxt_rd_bd(sc, cid, mem_id, data);
 done:
 	end_synchronized_op(sc, 0);
 	return (rc);
@@ -12048,10 +12892,11 @@ clear_stats(struct adapter *sc, u_int port_id)
 	mtx_lock(&sc->reg_lock);
 	if (!hw_off_limits(sc)) {
 		/* MAC stats */
-		t4_clr_port_stats(sc, pi->tx_chan);
+		t4_clr_port_stats(sc, pi->hw_port);
 		if (is_t6(sc)) {
 			if (pi->fcs_reg != -1)
-				pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg);
+				pi->fcs_base = t4_read_reg64(sc,
+				    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
 			else
 				pi->stats.rx_fcs_err = 0;
 		}
@@ -12114,12 +12959,21 @@ clear_stats(struct adapter *sc, u_int port_id)
 				txq->kern_tls_full = 0;
 				txq->kern_tls_octets = 0;
 				txq->kern_tls_waste = 0;
-				txq->kern_tls_options = 0;
 				txq->kern_tls_header = 0;
-				txq->kern_tls_fin = 0;
 				txq->kern_tls_fin_short = 0;
 				txq->kern_tls_cbc = 0;
 				txq->kern_tls_gcm = 0;
+				if (is_t6(sc)) {
+					txq->kern_tls_options = 0;
+					txq->kern_tls_fin = 0;
+				} else {
+					txq->kern_tls_ghash_received = 0;
+					txq->kern_tls_ghash_requested = 0;
+					txq->kern_tls_lso = 0;
+					txq->kern_tls_partial_ghash = 0;
+					txq->kern_tls_splitmode = 0;
+					txq->kern_tls_trailer = 0;
+				}
 				mp_ring_reset_stats(txq->r);
 			}
 
@@ -12264,14 +13118,12 @@ t4_os_link_changed(struct port_info *pi)
 	if (is_t6(sc)) {
 		if (lc->link_ok) {
 			if (lc->speed > 25000 ||
-			    (lc->speed == 25000 && lc->fec == FEC_RS)) {
-				pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
-				    A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS);
-			} else {
-				pi->fcs_reg = T5_PORT_REG(pi->tx_chan,
-				    A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS);
-			}
-			pi->fcs_base = t4_read_reg64(sc, pi->fcs_reg);
+			    (lc->speed == 25000 && lc->fec == FEC_RS))
+				pi->fcs_reg = A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS;
+			else
+				pi->fcs_reg = A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS;
+			pi->fcs_base = t4_read_reg64(sc,
+			    t4_port_reg(sc, pi->tx_chan, pi->fcs_reg));
 			pi->stats.rx_fcs_err = 0;
 		} else {
 			pi->fcs_reg = -1;
@@ -12404,9 +13256,13 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
 	case CHELSIO_T4_DEL_FILTER:
 		rc = del_filter(sc, (struct t4_filter *)data);
 		break;
-	case CHELSIO_T4_GET_SGE_CONTEXT:
-		rc = get_sge_context(sc, (struct t4_sge_context *)data);
+	case CHELSIO_T4_GET_SGE_CONTEXT: {
+		struct t4_sge_context *ctxt = (struct t4_sge_context *)data;
+
+		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
+		    sizeof(ctxt->data), &ctxt->data[0]);
 		break;
+	}
 	case CHELSIO_T4_LOAD_FW:
 		rc = load_fw(sc, (struct t4_data *)data);
 		break;
@@ -12452,6 +13308,13 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
 	case CHELSIO_T4_RELEASE_CLIP_ADDR:
 		rc = release_clip_addr(sc, (struct t4_clip_addr *)data);
 		break;
+	case CHELSIO_T4_GET_SGE_CTXT: {
+		struct t4_sge_ctxt *ctxt = (struct t4_sge_ctxt *)data;
+
+		rc = get_sge_context(sc, ctxt->mem_id, ctxt->cid,
+		    sizeof(ctxt->data), &ctxt->data[0]);
+		break;
+	}
 	default:
 		rc = ENOTTY;
 	}
@@ -12898,7 +13761,9 @@ t4_dump_mem(struct adapter *sc, u_int addr, u_int len)
 {
 	uint32_t base, j, off, pf, reg, save, win_pos;
 
-	reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
+	reg = chip_id(sc) > CHELSIO_T6 ?
+	    PCIE_MEM_ACCESS_T7_REG(A_PCIE_MEM_ACCESS_OFFSET0, 2) :
+	    PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
 	save = t4_read_reg(sc, reg);
 	base = sc->memwin[2].mw_base;
 
@@ -12910,6 +13775,8 @@ t4_dump_mem(struct adapter *sc, u_int addr, u_int len)
 		win_pos = addr & ~0x7f;	/* start must be 128B aligned */
 	}
 	off = addr - win_pos;
+	if (chip_id(sc) > CHELSIO_T6)
+		win_pos >>= X_T7_MEMOFST_SHIFT;
 	t4_write_reg(sc, reg, win_pos | pf);
 	t4_read_reg(sc, reg);
 
@@ -13274,6 +14141,7 @@ mod_event(module_t mod, int cmd, void *arg)
 #endif
 #ifdef KERN_TLS
 			t6_ktls_modload();
+			t7_ktls_modload();
 #endif
 			t4_tracer_modload();
 			tweak_tunables();
@@ -13337,6 +14205,7 @@ mod_event(module_t mod, int cmd, void *arg)
 				    vxlan_stop_evtag);
 				t4_tracer_modunload();
 #ifdef KERN_TLS
+				t7_ktls_modunload();
 				t6_ktls_modunload();
 #endif
 #ifdef INET6
@@ -13383,6 +14252,14 @@ MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
 #endif /* DEV_NETMAP */
 
+DRIVER_MODULE(chnex, pci, ch_driver, mod_event, 0);
+MODULE_VERSION(chnex, 1);
+MODULE_DEPEND(chnex, crypto, 1, 1, 1);
+MODULE_DEPEND(chnex, firmware, 1, 1, 1);
+#ifdef DEV_NETMAP
+MODULE_DEPEND(chnex, netmap, 1, 1, 1);
+#endif /* DEV_NETMAP */
+
 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, 0, 0);
 MODULE_VERSION(cxgbe, 1);
 
@@ -13392,6 +14269,9 @@ MODULE_VERSION(cxl, 1);
 DRIVER_MODULE(cc, t6nex, cc_driver, 0, 0);
 MODULE_VERSION(cc, 1);
 
+DRIVER_MODULE(che, chnex, che_driver, 0, 0);
+MODULE_VERSION(che, 1);
+
 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, 0, 0);
 MODULE_VERSION(vcxgbe, 1);
 
@@ -13400,3 +14280,6 @@ MODULE_VERSION(vcxl, 1);
 
 DRIVER_MODULE(vcc, cc, vcc_driver, 0, 0);
 MODULE_VERSION(vcc, 1);
+
+DRIVER_MODULE(vche, che, vche_driver, 0, 0);
+MODULE_VERSION(vche, 1);
diff --git a/sys/dev/cxgbe/t4_mp_ring.c b/sys/dev/cxgbe/t4_mp_ring.c
index 531fd356728e..916c363a0c2a 100644
--- a/sys/dev/cxgbe/t4_mp_ring.c
+++ b/sys/dev/cxgbe/t4_mp_ring.c
@@ -305,7 +305,6 @@ failed:
 }
 
 void
-
 mp_ring_free(struct mp_ring *r)
 {
 	int i;
@@ -472,6 +471,86 @@ mp_ring_enqueue(struct mp_ring *r, void **items, int n, int budget)
 	return (0);
 }
 
+/*
+ * Enqueue n items but never drain the ring.  Can be called
+ * to enqueue new items while draining the ring.
+ *
+ * Returns an errno.
+ */
+int
+mp_ring_enqueue_only(struct mp_ring *r, void **items, int n)
+{
+	union ring_state os, ns;
+	uint16_t pidx_start, pidx_stop;
+	int i;
+
+	MPASS(items != NULL);
+	MPASS(n > 0);
+
+	/*
+	 * Reserve room for the new items.  Our reservation, if successful, is
+	 * from 'pidx_start' to 'pidx_stop'.
+	 */
+	os.state = atomic_load_64(&r->state);
+
+	/* Should only be used from the drain callback. */
+	MPASS(os.flags == BUSY || os.flags == TOO_BUSY ||
+	    os.flags == TAKING_OVER);
+
+	for (;;) {
+		if (__predict_false(space_available(r, os) < n)) {
+			/* Not enough room in the ring. */
+			counter_u64_add(r->dropped, n);
+			return (ENOBUFS);
+		}
+
+		/* There is room in the ring. */
+
+		ns.state = os.state;
+		ns.pidx_head = increment_idx(r, os.pidx_head, n);
+		critical_enter();
+		if (atomic_fcmpset_64(&r->state, &os.state, ns.state))
+			break;
+		critical_exit();
+		cpu_spinwait();
+	};
+
+	pidx_start = os.pidx_head;
+	pidx_stop = ns.pidx_head;
+
+	/*
+	 * Wait for other producers who got in ahead of us to enqueue their
+	 * items, one producer at a time.  It is our turn when the ring's
+	 * pidx_tail reaches the beginning of our reservation (pidx_start).
+	 */
+	while (ns.pidx_tail != pidx_start) {
+		cpu_spinwait();
+		ns.state = atomic_load_64(&r->state);
+	}
+
+	/* Now it is our turn to fill up the area we reserved earlier. */
+	i = pidx_start;
+	do {
+		r->items[i] = *items++;
+		if (__predict_false(++i == r->size))
+			i = 0;
+	} while (i != pidx_stop);
+
+	/*
+	 * Update the ring's pidx_tail.  The release style atomic guarantees
+	 * that the items are visible to any thread that sees the updated pidx.
+	 */
+	os.state = atomic_load_64(&r->state);
+	do {
+		ns.state = os.state;
+		ns.pidx_tail = pidx_stop;
+	} while (atomic_fcmpset_rel_64(&r->state, &os.state, ns.state) == 0);
+	critical_exit();
+
+	counter_u64_add(r->not_consumer, 1);
+	return (0);
+}
+
 void
 mp_ring_check_drainage(struct mp_ring *r, int budget)
 {
diff --git a/sys/dev/cxgbe/t4_mp_ring.h b/sys/dev/cxgbe/t4_mp_ring.h
index 949174b9056d..07b15906cd43 100644
--- a/sys/dev/cxgbe/t4_mp_ring.h
+++ b/sys/dev/cxgbe/t4_mp_ring.h
@@ -62,6 +62,7 @@ int mp_ring_alloc(struct mp_ring **, int, void *, ring_drain_t,
     ring_can_drain_t, struct malloc_type *, struct mtx *, int);
 void mp_ring_free(struct mp_ring *);
 int mp_ring_enqueue(struct mp_ring *, void **, int, int);
+int mp_ring_enqueue_only(struct mp_ring *, void **, int);
 void mp_ring_check_drainage(struct mp_ring *, int);
 void mp_ring_reset_stats(struct mp_ring *);
 bool mp_ring_is_idle(struct mp_ring *);
diff --git a/sys/dev/cxgbe/t4_netmap.c b/sys/dev/cxgbe/t4_netmap.c
index e53fb5054316..0135bec6e2c1 100644
--- a/sys/dev/cxgbe/t4_netmap.c
+++ b/sys/dev/cxgbe/t4_netmap.c
@@ -232,7 +232,7 @@ alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx)
 	nm_txq->nid = idx;
 	nm_txq->iqidx = iqidx;
 	nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
-	    V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
+	    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
 	    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
 	if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0))
 		nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
@@ -276,7 +276,7 @@ free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 static int
 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
 {
-	int rc, cntxt_id;
+	int rc, cntxt_id, cong_map;
 	__be32 v;
 	struct adapter *sc = vi->adapter;
 	struct port_info *pi = vi->pi;
@@ -284,7 +284,6 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
 	struct netmap_adapter *na = NA(vi->ifp);
 	struct fw_iq_cmd c;
 	const int cong_drop = nm_cong_drop;
-	const int cong_map = pi->rx_e_chan_map;
 
 	MPASS(na != NULL);
 	MPASS(nm_rxq->iq_desc != NULL);
@@ -314,13 +313,17 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
 	    V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
 	    V_FW_IQ_CMD_VIID(vi->viid) |
 	    V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
-	c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
+	c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->hw_port) |
 	    F_FW_IQ_CMD_IQGTSMODE |
 	    V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
 	    V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
 	c.iqsize = htobe16(vi->qsize_rxq);
 	c.iqaddr = htobe64(nm_rxq->iq_ba);
 	if (cong_drop != -1) {
+		if (chip_id(sc) >= CHELSIO_T7)
+			cong_map = 1 << pi->hw_port;
+		else
+			cong_map = pi->rx_e_chan_map;
 		c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
 		    V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) | F_FW_IQ_CMD_FL0CONGCIF |
 		    F_FW_IQ_CMD_FL0CONGEN);
@@ -421,15 +424,19 @@ alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
 	    V_FW_EQ_ETH_CMD_VFN(0));
 	c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
-	if (nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID)
-		c.alloc_to_len16 |= htobe32(F_FW_EQ_ETH_CMD_ALLOC);
-	else
+	if (nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) {
+		const int core = sc->params.ncores > 1 ?
+		    nm_txq->nid % sc->params.ncores : 0;
+
+		c.alloc_to_len16 |= htobe32(F_FW_EQ_ETH_CMD_ALLOC |
+		    V_FW_EQ_ETH_CMD_COREGROUP(core));
+	} else
 		c.eqid_pkd = htobe32(V_FW_EQ_ETH_CMD_EQID(nm_txq->cntxt_id));
 	c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
 	    F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
 	c.fetchszm_to_iqid =
 	    htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
-		V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
+		V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->hw_port) | F_FW_EQ_ETH_CMD_FETCHRO |
 		V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
 	c.dcaen_to_eqsize =
 	    htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
diff --git a/sys/dev/cxgbe/t4_sched.c b/sys/dev/cxgbe/t4_sched.c
index 2186c8aa2ac0..65c2720d692c 100644
--- a/sys/dev/cxgbe/t4_sched.c
+++ b/sys/dev/cxgbe/t4_sched.c
@@ -272,7 +272,7 @@ update_tx_sched(void *context, int pending)
 			}
 			rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED,
 			    FW_SCHED_PARAMS_LEVEL_CL_RL, tc->mode, tc->rateunit,
-			    tc->ratemode, pi->tx_chan, j, 0, tc->maxrate, 0,
+			    tc->ratemode, pi->hw_port, j, 0, tc->maxrate, 0,
 			    tc->pktsize, tc->burstsize, 1);
 			end_synchronized_op(sc, 0);
 
@@ -291,7 +291,7 @@ update_tx_sched(void *context, int pending)
 			    "params: mode %d, rateunit %d, ratemode %d, "
 			    "channel %d, minrate %d, maxrate %d, pktsize %d, "
 			    "burstsize %d\n", j, rc, tc->mode, tc->rateunit,
-			    tc->ratemode, pi->tx_chan, 0, tc->maxrate,
+			    tc->ratemode, pi->hw_port, 0, tc->maxrate,
 			    tc->pktsize, tc->burstsize);
 		}
 	}
@@ -839,7 +839,7 @@ failed:
 	cst->tx_total = cst->tx_credits;
 	cst->plen = 0;
 	cst->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
-	    V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
+	    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
 	    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
 
 	/*
diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c
index 86454bc4fe10..2f9cb1a4ebb5 100644
--- a/sys/dev/cxgbe/t4_sge.c
+++ b/sys/dev/cxgbe/t4_sge.c
@@ -1,8 +1,7 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause
  *
- * Copyright (c) 2011 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2025 Chelsio Communications.
  * Written by: Navdeep Parhar <np@FreeBSD.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -259,17 +258,20 @@ static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
     struct sge_ofld_rxq *);
 #endif
-static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
-static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
+static int ctrl_eq_alloc(struct adapter *, struct sge_eq *, int);
+static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *,
+    int);
 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
-static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
+static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *,
+    int);
 #endif
 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *,
     struct sysctl_oid *);
 static void free_eq(struct adapter *, struct sge_eq *);
 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *,
     struct sysctl_oid *, struct sge_eq *);
-static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
+static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *,
+    int);
 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
     struct sysctl_ctx_list *, struct sysctl_oid *);
@@ -348,6 +350,7 @@ cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
+cpl_handler_t fw6_pld_handlers[NUM_CPL_FW6_COOKIES];
 
 void
 t4_register_an_handler(an_handler_t h)
@@ -477,6 +480,21 @@ fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
 	return (fw4_ack_handlers[cookie](iq, rss, m));
 }
 
+static int
+fw6_pld_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
+{
+	const struct cpl_fw6_pld *cpl;
+	uint64_t cookie;
+
+	if (m != NULL)
+		cpl = mtod(m, const void *);
+	else
+		cpl = (const void *)(rss + 1);
+	cookie = be64toh(cpl->data[1]) & CPL_FW6_COOKIE_MASK;
+
+	return (fw6_pld_handlers[cookie](iq, rss, m));
+}
+
 static void
 t4_init_shared_cpl_handlers(void)
 {
@@ -486,6 +504,7 @@ t4_init_shared_cpl_handlers(void)
 	t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
 	t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
 	t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
+	t4_register_cpl_handler(CPL_FW6_PLD, fw6_pld_handler);
 }
 
 void
@@ -494,8 +513,12 @@ t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
 	uintptr_t *loc;
 
 	MPASS(opcode < nitems(t4_cpl_handler));
-	MPASS(cookie > CPL_COOKIE_RESERVED);
-	MPASS(cookie < NUM_CPL_COOKIES);
+	if (opcode == CPL_FW6_PLD) {
+		MPASS(cookie < NUM_CPL_FW6_COOKIES);
+	} else {
+		MPASS(cookie > CPL_COOKIE_RESERVED);
+		MPASS(cookie < NUM_CPL_COOKIES);
+	}
 	MPASS(t4_cpl_handler[opcode] != NULL);
 
 	switch (opcode) {
@@ -514,6 +537,9 @@ t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
 	case CPL_FW4_ACK:
 		loc = (uintptr_t *)&fw4_ack_handlers[cookie];
 		break;
+	case CPL_FW6_PLD:
+		loc = (uintptr_t *)&fw6_pld_handlers[cookie];
+		break;
 	default:
 		MPASS(0);
 		return;
@@ -1064,9 +1090,9 @@ t4_setup_adapter_queues(struct adapter *sc)
 	 */
 
 	/*
-	 * Control queues, one per port.
+	 * Control queues.  At least one per port and per internal core.
 	 */
-	for_each_port(sc, i) {
+	for (i = 0; i < sc->sge.nctrlq; i++) {
 		rc = alloc_ctrlq(sc, i);
 		if (rc != 0)
 			return (rc);
@@ -1087,7 +1113,7 @@ t4_teardown_adapter_queues(struct adapter *sc)
 
 	if (sc->sge.ctrlq != NULL) {
 		MPASS(!(sc->flags & IS_VF));	/* VFs don't allocate ctrlq. */
-		for_each_port(sc, i)
+		for (i = 0; i < sc->sge.nctrlq; i++)
 			free_ctrlq(sc, i);
 	}
 	free_fwq(sc);
@@ -2701,9 +2727,14 @@ restart:
 #endif
 #ifdef KERN_TLS
 	if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) {
+		struct vi_info *vi = if_getsoftc(mst->ifp);
+
 		cflags |= MC_TLS;
 		set_mbuf_cflags(m0, cflags);
-		rc = t6_ktls_parse_pkt(m0);
+		if (is_t6(vi->pi->adapter))
+			rc = t6_ktls_parse_pkt(m0);
+		else
+			rc = t7_ktls_parse_pkt(m0);
 		if (rc != 0)
 			goto fail;
 		return (EINPROGRESS);
@@ -3273,7 +3304,10 @@ skip_coalescing:
 #ifdef KERN_TLS
 		} else if (mbuf_cflags(m0) & MC_TLS) {
 			ETHER_BPF_MTAP(ifp, m0);
-			n = t6_ktls_write_wr(txq, wr, m0, avail);
+			if (is_t6(sc))
+				n = t6_ktls_write_wr(txq, wr, m0, avail);
+			else
+				n = t7_ktls_write_wr(txq, wr, m0, avail);
 #endif
 		} else {
 			ETHER_BPF_MTAP(ifp, m0);
@@ -3414,6 +3448,7 @@ init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
 	eq->type = eqtype;
 	eq->port_id = port_id;
 	eq->tx_chan = sc->port[port_id]->tx_chan;
+	eq->hw_port = sc->port[port_id]->hw_port;
 	eq->iq = iq;
 	eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
 	strlcpy(eq->lockname, name, sizeof(eq->lockname));
@@ -3577,7 +3612,7 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
 	    V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
 	    V_FW_IQ_CMD_VIID(vi->viid) |
 	    V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
-	c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
+	c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->hw_port) |
 	    F_FW_IQ_CMD_IQGTSMODE |
 	    V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
 	    V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
@@ -3585,7 +3620,13 @@ alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
 	c.iqaddr = htobe64(iq->ba);
 	c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype));
 	if (iq->cong_drop != -1) {
-		cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0;
+		if (iq->qtype == IQ_ETH) {
+			if (chip_id(sc) >= CHELSIO_T7)
+				cong_map = 1 << pi->hw_port;
+			else
+				cong_map = pi->rx_e_chan_map;
+		} else
+			cong_map = 0;
 		c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
 	}
 
@@ -3842,7 +3883,7 @@ alloc_ctrlq(struct adapter *sc, int idx)
 	struct sysctl_oid *oid;
 	struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
 
-	MPASS(idx < sc->params.nports);
+	MPASS(idx < sc->sge.nctrlq);
 
 	if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) {
 		MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
@@ -3854,8 +3895,8 @@ alloc_ctrlq(struct adapter *sc, int idx)
 
 		snprintf(name, sizeof(name), "%s ctrlq%d",
 		    device_get_nameunit(sc->dev), idx);
-		init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, idx,
-		    &sc->sge.fwq, name);
+		init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE,
+		    idx % sc->params.nports, &sc->sge.fwq, name);
 		rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid);
 		if (rc != 0) {
 			CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc);
@@ -3870,7 +3911,7 @@ alloc_ctrlq(struct adapter *sc, int idx)
 		MPASS(ctrlq->nwr_pending == 0);
 		MPASS(ctrlq->ndesc_needed == 0);
 
-		rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq);
+		rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq, idx);
 		if (rc != 0) {
 			CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc);
 			return (rc);
@@ -3938,14 +3979,19 @@ t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop,
 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
 	    V_FW_PARAMS_PARAM_YZ(cntxt_id);
-	val = V_CONMCTXT_CNGTPMODE(cong_mode);
-	if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL ||
-	    cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) {
-		for (i = 0, ch_map = 0; i < 4; i++) {
-			if (cong_map & (1 << i))
-				ch_map |= 1 << (i << cng_ch_bits_log);
+	if (chip_id(sc) >= CHELSIO_T7) {
+		val = V_T7_DMAQ_CONM_CTXT_CNGTPMODE(cong_mode) |
+		    V_T7_DMAQ_CONM_CTXT_CH_VEC(cong_map);
+	} else {
+		val = V_CONMCTXT_CNGTPMODE(cong_mode);
+		if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL ||
+		    cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) {
+			for (i = 0, ch_map = 0; i < 4; i++) {
+				if (cong_map & (1 << i))
+					ch_map |= 1 << (i << cng_ch_bits_log);
+			}
+			val |= V_CONMCTXT_CNGCHMAP(ch_map);
 		}
-		val |= V_CONMCTXT_CNGCHMAP(ch_map);
 	}
 	rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
 	if (rc != 0) {
@@ -4253,24 +4299,26 @@ qsize_to_fthresh(int qsize)
 }
 
 static int
-ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
+ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq, int idx)
 {
-	int rc, cntxt_id;
+	int rc, cntxt_id, core;
 	struct fw_eq_ctrl_cmd c;
 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
 
+	core = sc->params.tid_qid_sel_mask != 0 ? idx % sc->params.ncores : 0;
 	bzero(&c, sizeof(c));
 
 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
 	    V_FW_EQ_CTRL_CMD_VFN(0));
 	c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
+	    V_FW_EQ_CTRL_CMD_COREGROUP(core) |
 	    F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
 	c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
 	c.physeqid_pkd = htobe32(0);
 	c.fetchszm_to_iqid =
 	    htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
-		V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
+		V_FW_EQ_CTRL_CMD_PCIECHN(eq->hw_port) |
 		F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
 	c.dcaen_to_eqsize =
 	    htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
@@ -4282,8 +4330,8 @@ ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
 
 	rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
 	if (rc != 0) {
-		CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n",
-		    eq->tx_chan, rc);
+		CH_ERR(sc, "failed to create hw ctrlq for port %d: %d\n",
+		    eq->port_id, rc);
 		return (rc);
 	}
 
@@ -4299,24 +4347,26 @@ ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
 }
 
 static int
-eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
+eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, int idx)
 {
-	int rc, cntxt_id;
+	int rc, cntxt_id, core;
 	struct fw_eq_eth_cmd c;
 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
 
+	core = sc->params.ncores > 1 ? idx % sc->params.ncores : 0;
 	bzero(&c, sizeof(c));
 
 	c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
 	    V_FW_EQ_ETH_CMD_VFN(0));
 	c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
+	    V_FW_EQ_ETH_CMD_COREGROUP(core) |
 	    F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
 	c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
 	    F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
 	c.fetchszm_to_iqid =
 	    htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
-		V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
+		V_FW_EQ_ETH_CMD_PCIECHN(eq->hw_port) | F_FW_EQ_ETH_CMD_FETCHRO |
 		V_FW_EQ_ETH_CMD_IQID(eq->iqid));
 	c.dcaen_to_eqsize =
 	    htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
@@ -4344,23 +4394,44 @@ eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
 }
 
 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
+/*
+ * ncores	number of uP cores.
+ * nq		number of queues for this VI
+ * idx		queue index
+ */
+static inline int
+qidx_to_core(int ncores, int nq, int idx)
+{
+	MPASS(nq % ncores == 0);
+	MPASS(idx >= 0 && idx < nq);
+
+	return (idx * ncores / nq);
+}
+
 static int
-ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
+ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq,
+    int idx)
 {
-	int rc, cntxt_id;
+	int rc, cntxt_id, core;
 	struct fw_eq_ofld_cmd c;
 	int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
 
+	if (sc->params.tid_qid_sel_mask != 0)
+		core = qidx_to_core(sc->params.ncores, vi->nofldtxq, idx);
+	else
+		core = 0;
+
 	bzero(&c, sizeof(c));
 
 	c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
 	    F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
 	    V_FW_EQ_OFLD_CMD_VFN(0));
 	c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
+	    V_FW_EQ_OFLD_CMD_COREGROUP(core) |
 	    F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
 	c.fetchszm_to_iqid =
 		htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
-		    V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
+		    V_FW_EQ_OFLD_CMD_PCIECHN(eq->hw_port) |
 		    F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
 	c.dcaen_to_eqsize =
 	    htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
@@ -4449,7 +4520,7 @@ add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
 }
 
 static int
-alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
+alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq, int idx)
 {
 	int rc;
 
@@ -4464,16 +4535,16 @@ alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
 
 	switch (eq->type) {
 	case EQ_CTRL:
-		rc = ctrl_eq_alloc(sc, eq);
+		rc = ctrl_eq_alloc(sc, eq, idx);
 		break;
 
 	case EQ_ETH:
-		rc = eth_eq_alloc(sc, vi, eq);
+		rc = eth_eq_alloc(sc, vi, eq, idx);
 		break;
 
 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
 	case EQ_OFLD:
-		rc = ofld_eq_alloc(sc, vi, eq);
+		rc = ofld_eq_alloc(sc, vi, eq, idx);
 		break;
 #endif
 
@@ -4653,7 +4724,7 @@ failed:
 
 	if (!(eq->flags & EQ_HW_ALLOCATED)) {
 		MPASS(eq->flags & EQ_SW_ALLOCATED);
-		rc = alloc_eq_hwq(sc, vi, eq);
+		rc = alloc_eq_hwq(sc, vi, eq, idx);
 		if (rc != 0) {
 			CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc);
 			return (rc);
@@ -4678,10 +4749,10 @@ failed:
 
 		if (vi->flags & TX_USES_VM_WR)
 			txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
-			    V_TXPKT_INTF(pi->tx_chan));
+			    V_TXPKT_INTF(pi->hw_port));
 		else
 			txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
-			    V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
+			    V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
 			    V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
 
 		txq->tc_idx = -1;
@@ -4788,18 +4859,46 @@ add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx,
 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste",
 		    CTLFLAG_RD, &txq->kern_tls_waste,
 		    "# of octets DMAd but not transmitted in NIC TLS records");
-		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options",
-		    CTLFLAG_RD, &txq->kern_tls_options,
-		    "# of NIC TLS options-only packets transmitted");
 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header",
 		    CTLFLAG_RD, &txq->kern_tls_header,
 		    "# of NIC TLS header-only packets transmitted");
-		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin",
-		    CTLFLAG_RD, &txq->kern_tls_fin,
-		    "# of NIC TLS FIN-only packets transmitted");
 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short",
 		    CTLFLAG_RD, &txq->kern_tls_fin_short,
 		    "# of NIC TLS padded FIN packets on short TLS records");
+		if (is_t6(sc)) {
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_options", CTLFLAG_RD,
+			    &txq->kern_tls_options,
+			    "# of NIC TLS options-only packets transmitted");
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin,
+			    "# of NIC TLS FIN-only packets transmitted");
+		} else {
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_ghash_received", CTLFLAG_RD,
+			    &txq->kern_tls_ghash_received,
+			    "# of NIC TLS GHASHes received");
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_ghash_requested", CTLFLAG_RD,
+			    &txq->kern_tls_ghash_requested,
+			    "# of NIC TLS GHASHes requested");
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_lso", CTLFLAG_RD,
+			    &txq->kern_tls_lso,
+			    "# of NIC TLS records transmitted using LSO");
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_partial_ghash", CTLFLAG_RD,
+			    &txq->kern_tls_partial_ghash,
+			    "# of NIC TLS records encrypted using a partial GHASH");
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_splitmode", CTLFLAG_RD,
+			    &txq->kern_tls_splitmode,
+			    "# of NIC TLS records using SplitMode");
+			SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO,
+			    "kern_tls_trailer", CTLFLAG_RD,
+			    &txq->kern_tls_trailer,
+			    "# of NIC TLS trailer-only packets transmitted");
+		}
 		SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc",
 		    CTLFLAG_RD, &txq->kern_tls_cbc,
 		    "# of NIC TLS sessions using AES-CBC");
@@ -4869,7 +4968,7 @@ alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx)
 		MPASS(eq->flags & EQ_SW_ALLOCATED);
 		MPASS(ofld_txq->wrq.nwr_pending == 0);
 		MPASS(ofld_txq->wrq.ndesc_needed == 0);
-		rc = alloc_eq_hwq(sc, vi, eq);
+		rc = alloc_eq_hwq(sc, vi, eq, idx);
 		if (rc != 0) {
 			CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx,
 			    rc);
@@ -5418,7 +5517,8 @@ write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
 			m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
 			m0->m_pkthdr.l5hlen) |
 		    V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
-	tnl_lso->r1 = 0;
+	tnl_lso->ipsecen_to_rocev2 = 0;
+	tnl_lso->roce_eth = 0;
 
 	/* Inner headers. */
 	ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
@@ -6583,10 +6683,11 @@ send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
 	    V_FW_WR_FLOWID(cst->etid));
 	flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
 	flowc->mnemval[0].val = htobe32(pfvf);
+	/* Firmware expects hw port and will translate to channel itself. */
 	flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
-	flowc->mnemval[1].val = htobe32(pi->tx_chan);
+	flowc->mnemval[1].val = htobe32(pi->hw_port);
 	flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
-	flowc->mnemval[2].val = htobe32(pi->tx_chan);
+	flowc->mnemval[2].val = htobe32(pi->hw_port);
 	flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
 	flowc->mnemval[3].val = htobe32(cst->iqid);
 	flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
diff --git a/sys/dev/cxgbe/t4_tpt.c b/sys/dev/cxgbe/t4_tpt.c
new file mode 100644
index 000000000000..d18eabb026f1
--- /dev/null
+++ b/sys/dev/cxgbe/t4_tpt.c
@@ -0,0 +1,193 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Chelsio Communications, Inc.
+ * Written by: John Baldwin <jhb@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "common/common.h"
+
+/*
+ * Support routines to manage TPT entries used for both RDMA and NVMe
+ * offloads.  This includes allocating STAG indices and managing the
+ * PBL pool.
+ */
+
+#define T4_ULPTX_MIN_IO 32
+#define T4_MAX_INLINE_SIZE 96
+#define T4_ULPTX_MAX_DMA 1024
+
+/* PBL and STAG Memory Managers. */
+
+#define MIN_PBL_SHIFT 5			/* 32B == min PBL size (4 entries) */
+
+uint32_t
+t4_pblpool_alloc(struct adapter *sc, int size)
+{
+	vmem_addr_t addr;
+
+	if (vmem_xalloc(sc->pbl_arena, roundup(size, (1 << MIN_PBL_SHIFT)),
+	    4, 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_FIRSTFIT | M_NOWAIT,
+	    &addr) != 0)
+		return (0);
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: addr 0x%lx size %d", __func__, addr, size);
+#endif
+	return (addr);
+}
+
+void
+t4_pblpool_free(struct adapter *sc, uint32_t addr, int size)
+{
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: addr 0x%x size %d", __func__, addr, size);
+#endif
+	vmem_xfree(sc->pbl_arena, addr, roundup(size, (1 << MIN_PBL_SHIFT)));
+}
+
+uint32_t
+t4_stag_alloc(struct adapter *sc, int size)
+{
+	vmem_addr_t stag_idx;
+
+	if (vmem_alloc(sc->stag_arena, size, M_FIRSTFIT | M_NOWAIT,
+	    &stag_idx) != 0)
+		return (T4_STAG_UNSET);
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: idx 0x%lx size %d", __func__, stag_idx, size);
+#endif
+	return (stag_idx);
+}
+
+void
+t4_stag_free(struct adapter *sc, uint32_t stag_idx, int size)
+{
+#ifdef VERBOSE_TRACES
+	CTR(KTR_CXGBE, "%s: idx 0x%x size %d", __func__, stag_idx, size);
+#endif
+	vmem_free(sc->stag_arena, stag_idx, size);
+}
+
+void
+t4_init_tpt(struct adapter *sc)
+{
+	if (sc->vres.pbl.size != 0)
+		sc->pbl_arena = vmem_create("PBL_MEM_POOL", sc->vres.pbl.start,
+		    sc->vres.pbl.size, 1, 0, M_FIRSTFIT | M_WAITOK);
+	if (sc->vres.stag.size != 0)
+		sc->stag_arena = vmem_create("STAG", 1,
+		    sc->vres.stag.size >> 5, 1, 0, M_FIRSTFIT | M_WAITOK);
+}
+
+void
+t4_free_tpt(struct adapter *sc)
+{
+	if (sc->pbl_arena != NULL)
+		vmem_destroy(sc->pbl_arena);
+	if (sc->stag_arena != NULL)
+		vmem_destroy(sc->stag_arena);
+}
+
+/*
+ * TPT support routines.  TPT entries are stored in the STAG adapter
+ * memory region and are written to via ULP_TX_MEM_WRITE commands in
+ * FW_ULPTX_WR work requests.
+ */
+
+void
+t4_write_mem_dma_wr(struct adapter *sc, void *wr, int wr_len, int tid,
+    uint32_t addr, uint32_t len, vm_paddr_t data, uint64_t cookie)
+{
+	struct ulp_mem_io *ulpmc;
+	struct ulptx_sgl *sgl;
+
+	MPASS(wr_len == T4_WRITE_MEM_DMA_LEN);
+
+	addr &= 0x7FFFFFF;
+
+	memset(wr, 0, wr_len);
+	ulpmc = wr;
+	INIT_ULPTX_WR(ulpmc, wr_len, 0, tid);
+	if (cookie != 0) {
+		ulpmc->wr.wr_hi |= htobe32(F_FW_WR_COMPL);
+		ulpmc->wr.wr_lo = cookie;
+	}
+	ulpmc->cmd = htobe32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) |
+	    V_T5_ULP_MEMIO_ORDER(1) |
+	    V_T5_ULP_MEMIO_FID(sc->sge.ofld_rxq[0].iq.abs_id));
+	if (chip_id(sc) >= CHELSIO_T7)
+		ulpmc->dlen = htobe32(V_T7_ULP_MEMIO_DATA_LEN(len >> 5));
+	else
+		ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(len >> 5));
+	ulpmc->len16 = htobe32((tid << 8) |
+	    DIV_ROUND_UP(wr_len - sizeof(ulpmc->wr), 16));
+	ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(addr));
+
+	sgl = (struct ulptx_sgl *)(ulpmc + 1);
+	sgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | V_ULPTX_NSGE(1));
+	sgl->len0 = htobe32(len);
+	sgl->addr0 = htobe64(data);
+}
+
+void
+t4_write_mem_inline_wr(struct adapter *sc, void *wr, int wr_len, int tid,
+    uint32_t addr, uint32_t len, void *data, uint64_t cookie)
+{
+	struct ulp_mem_io *ulpmc;
+	struct ulptx_idata *ulpsc;
+
+	MPASS(len > 0 && len <= T4_MAX_INLINE_SIZE);
+	MPASS(wr_len == T4_WRITE_MEM_INLINE_LEN(len));
+
+	addr &= 0x7FFFFFF;
+
+	memset(wr, 0, wr_len);
+	ulpmc = wr;
+	INIT_ULPTX_WR(ulpmc, wr_len, 0, tid);
+
+	if (cookie != 0) {
+		ulpmc->wr.wr_hi |= htobe32(F_FW_WR_COMPL);
+		ulpmc->wr.wr_lo = cookie;
+	}
+
+	ulpmc->cmd = htobe32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) |
+	    F_T5_ULP_MEMIO_IMM);
+
+	if (chip_id(sc) >= CHELSIO_T7)
+		ulpmc->dlen = htobe32(V_T7_ULP_MEMIO_DATA_LEN(
+			DIV_ROUND_UP(len, T4_ULPTX_MIN_IO)));
+	else
+		ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(
+			DIV_ROUND_UP(len, T4_ULPTX_MIN_IO)));
+	ulpmc->len16 = htobe32((tid << 8) |
+	    DIV_ROUND_UP(wr_len - sizeof(ulpmc->wr), 16));
+	ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(addr));
+
+	ulpsc = (struct ulptx_idata *)(ulpmc + 1);
+	ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM));
+	ulpsc->len = htobe32(roundup(len, T4_ULPTX_MIN_IO));
+
+	if (data != NULL)
+		memcpy(ulpsc + 1, data, len);
+}
diff --git a/sys/dev/cxgbe/t4_tracer.c b/sys/dev/cxgbe/t4_tracer.c
index 80689a543e83..4f8d28626bc9 100644
--- a/sys/dev/cxgbe/t4_tracer.c
+++ b/sys/dev/cxgbe/t4_tracer.c
@@ -123,9 +123,8 @@ static int
 t4_cloner_match(struct if_clone *ifc, const char *name)
 {
 
-	if (strncmp(name, "t4nex", 5) != 0 &&
-	    strncmp(name, "t5nex", 5) != 0 &&
-	    strncmp(name, "t6nex", 5) != 0)
+	if (strncmp(name, "t4nex", 5) != 0 && strncmp(name, "t5nex", 5) != 0 &&
+	    strncmp(name, "t6nex", 5) != 0 && strncmp(name, "chnex", 5) != 0)
 		return (0);
 	if (name[5] < '0' || name[5] > '9')
 		return (0);
diff --git a/sys/dev/cxgbe/t4_vf.c b/sys/dev/cxgbe/t4_vf.c
index b7b08e226a57..89dae02e9332 100644
--- a/sys/dev/cxgbe/t4_vf.c
+++ b/sys/dev/cxgbe/t4_vf.c
@@ -125,6 +125,28 @@ struct {
 	{0x6885, "Chelsio T6240-SO 85 VF"},
 	{0x6886, "Chelsio T6225-SO-CR 86 VF"},
 	{0x6887, "Chelsio T6225-CR 87 VF"},
+}, t7vf_pciids[] = {
+	{0xd800, "Chelsio T7 FPGA VF"},		/* T7 PE12K FPGA */
+	{0x7800, "Chelsio T72200-DBG VF"},	/* 2 x 200G, debug */
+	{0x7801, "Chelsio T7250 VF"},		/* 2 x 10/25/50G, 1 mem */
+	{0x7802, "Chelsio S7250 VF"},		/* 2 x 10/25/50G, nomem */
+	{0x7803, "Chelsio T7450 VF"},		/* 4 x 10/25/50G, 1 mem */
+	{0x7804, "Chelsio S7450 VF"},		/* 4 x 10/25/50G, nomem */
+	{0x7805, "Chelsio T72200 VF"},		/* 2 x 40/100/200G, 1 mem */
+	{0x7806, "Chelsio S72200 VF"},		/* 2 x 40/100/200G, nomem */
+	{0x7807, "Chelsio T72200-FH VF"},	/* 2 x 40/100/200G, 2 mem */
+	{0x7808, "Chelsio T71400 VF"},		/* 1 x 400G, nomem */
+	{0x7809, "Chelsio S7210-BT VF"},	/* 2 x 10GBASE-T, nomem */
+	{0x780a, "Chelsio T7450-RC VF"},	/* 4 x 10/25/50G, 1 mem, RC */
+	{0x780b, "Chelsio T72200-RC VF"},	/* 2 x 40/100/200G, 1 mem, RC */
+	{0x780c, "Chelsio T72200-FH-RC VF"},	/* 2 x 40/100/200G, 2 mem, RC */
+	{0x780d, "Chelsio S72200-OCP3 VF"},	/* 2 x 40/100/200G OCP3 */
+	{0x780e, "Chelsio S7450-OCP3 VF"},	/* 4 x 1/20/25/50G OCP3 */
+	{0x780f, "Chelsio S7410-BT-OCP3 VF"},	/* 4 x 10GBASE-T OCP3 */
+	{0x7810, "Chelsio S7210-BT-A VF"},	/* 2 x 10GBASE-T */
+	{0x7811, "Chelsio T7_MAYRA_7 VF"},	/* Motherboard */
+
+	{0x7880, "Custom T7 VF"},
 };
 
 static d_ioctl_t t4vf_ioctl;
@@ -183,6 +205,22 @@ t6vf_probe(device_t dev)
 	return (ENXIO);
 }
 
+static int
+chvf_probe(device_t dev)
+{
+	uint16_t d;
+	size_t i;
+
+	d = pci_get_device(dev);
+	for (i = 0; i < nitems(t7vf_pciids); i++) {
+		if (d == t7vf_pciids[i].device) {
+			device_set_desc(dev, t7vf_pciids[i].desc);
+			return (BUS_PROBE_DEFAULT);
+		}
+	}
+	return (ENXIO);
+}
+
 #define FW_PARAM_DEV(param) \
 	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
@@ -956,6 +994,20 @@ static driver_t t6vf_driver = {
 	sizeof(struct adapter)
 };
 
+static device_method_t chvf_methods[] = {
+	DEVMETHOD(device_probe,		chvf_probe),
+	DEVMETHOD(device_attach,	t4vf_attach),
+	DEVMETHOD(device_detach,	t4_detach_common),
+
+	DEVMETHOD_END
+};
+
+static driver_t chvf_driver = {
+	"chvf",
+	chvf_methods,
+	sizeof(struct adapter)
+};
+
 static driver_t cxgbev_driver = {
 	"cxgbev",
 	cxgbe_methods,
@@ -974,6 +1026,12 @@ static driver_t ccv_driver = {
 	sizeof(struct port_info)
 };
 
+static driver_t chev_driver = {
+	"chev",
+	cxgbe_methods,
+	sizeof(struct port_info)
+};
+
 DRIVER_MODULE(t4vf, pci, t4vf_driver, 0, 0);
 MODULE_VERSION(t4vf, 1);
 MODULE_DEPEND(t4vf, t4nex, 1, 1, 1);
@@ -986,6 +1044,10 @@ DRIVER_MODULE(t6vf, pci, t6vf_driver, 0, 0);
 MODULE_VERSION(t6vf, 1);
 MODULE_DEPEND(t6vf, t6nex, 1, 1, 1);
 
+DRIVER_MODULE(chvf, pci, chvf_driver, 0, 0);
+MODULE_VERSION(chvf, 1);
+MODULE_DEPEND(chvf, chnex, 1, 1, 1);
+
 DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, 0, 0);
 MODULE_VERSION(cxgbev, 1);
 
@@ -994,3 +1056,6 @@ MODULE_VERSION(cxlv, 1);
 
 DRIVER_MODULE(ccv, t6vf, ccv_driver, 0, 0);
 MODULE_VERSION(ccv, 1);
+
+DRIVER_MODULE(chev, chvf, chev_driver, 0, 0);
+MODULE_VERSION(chev, 1);
diff --git a/sys/dev/cxgbe/tom/t4_connect.c b/sys/dev/cxgbe/tom/t4_connect.c
index 99e4c222996d..c236ee060bc2 100644
--- a/sys/dev/cxgbe/tom/t4_connect.c
+++ b/sys/dev/cxgbe/tom/t4_connect.c
@@ -89,6 +89,12 @@ do_act_establish(struct sge_iq *iq, const struct rss_header *rss,
 	INP_WLOCK(inp);
 	toep->tid = tid;
 	insert_tid(sc, tid, toep, inp->inp_vflag & INP_IPV6 ? 2 : 1);
+	if (sc->params.tid_qid_sel_mask != 0) {
+		update_tid_qid_sel(toep->vi, &toep->params, tid);
+		toep->ofld_txq = &sc->sge.ofld_txq[toep->params.txq_idx];
+		toep->ctrlq = &sc->sge.ctrlq[toep->params.ctrlq_idx];
+	}
+
 	if (inp->inp_flags & INP_DROPPED) {
 
 		/* socket closed by the kernel before hw told us it connected */
@@ -205,7 +211,7 @@ static inline int
 act_open_cpl_size(struct adapter *sc, int isipv6)
 {
 	int idx;
-	static const int sz_table[3][2] = {
+	static const int sz_table[4][2] = {
 		{
 			sizeof (struct cpl_act_open_req),
 			sizeof (struct cpl_act_open_req6)
@@ -218,10 +224,14 @@ act_open_cpl_size(struct adapter *sc, int isipv6)
 			sizeof (struct cpl_t6_act_open_req),
 			sizeof (struct cpl_t6_act_open_req6)
 		},
+		{
+			sizeof (struct cpl_t7_act_open_req),
+			sizeof (struct cpl_t7_act_open_req6)
+		},
 	};
 
 	MPASS(chip_id(sc) >= CHELSIO_T4);
-	idx = min(chip_id(sc) - CHELSIO_T4, 2);
+	idx = min(chip_id(sc) - CHELSIO_T4, 3);
 
 	return (sz_table[idx][!!isipv6]);
 }
@@ -255,6 +265,7 @@ t4_connect(struct toedev *tod, struct socket *so, struct nhop_object *nh,
 	struct offload_settings settings;
 	struct epoch_tracker et;
 	uint16_t vid = 0xfff, pcp = 0;
+	uint64_t ntuple;
 
 	INP_WLOCK_ASSERT(inp);
 	KASSERT(nam->sa_family == AF_INET || nam->sa_family == AF_INET6,
@@ -308,10 +319,12 @@ t4_connect(struct toedev *tod, struct socket *so, struct nhop_object *nh,
 	qid_atid = V_TID_QID(toep->ofld_rxq->iq.abs_id) | V_TID_TID(toep->tid) |
 	    V_TID_COOKIE(CPL_COOKIE_TOM);
 
+	ntuple = select_ntuple(vi, toep->l2te);
 	if (isipv6) {
 		struct cpl_act_open_req6 *cpl = wrtod(wr);
 		struct cpl_t5_act_open_req6 *cpl5 = (void *)cpl;
 		struct cpl_t6_act_open_req6 *cpl6 = (void *)cpl;
+		struct cpl_t7_act_open_req6 *cpl7 = (void *)cpl;
 
 		if ((inp->inp_vflag & INP_IPV6) == 0)
 			DONT_OFFLOAD_ACTIVE_OPEN(ENOTSUP);
@@ -323,18 +336,23 @@ t4_connect(struct toedev *tod, struct socket *so, struct nhop_object *nh,
 		switch (chip_id(sc)) {
 		case CHELSIO_T4:
 			INIT_TP_WR(cpl, 0);
-			cpl->params = select_ntuple(vi, toep->l2te);
+			cpl->params = htobe32((uint32_t)ntuple);
 			break;
 		case CHELSIO_T5:
 			INIT_TP_WR(cpl5, 0);
 			cpl5->iss = htobe32(tp->iss);
-			cpl5->params = select_ntuple(vi, toep->l2te);
+			cpl5->params = htobe64(V_FILTER_TUPLE(ntuple));
 			break;
 		case CHELSIO_T6:
-		default:
 			INIT_TP_WR(cpl6, 0);
 			cpl6->iss = htobe32(tp->iss);
-			cpl6->params = select_ntuple(vi, toep->l2te);
+			cpl6->params = htobe64(V_FILTER_TUPLE(ntuple));
+			break;
+		case CHELSIO_T7:
+		default:
+			INIT_TP_WR(cpl7, 0);
+			cpl7->iss = htobe32(tp->iss);
+			cpl7->params = htobe64(V_T7_FILTER_TUPLE(ntuple));
 			break;
 		}
 		OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
@@ -356,23 +374,28 @@ t4_connect(struct toedev *tod, struct socket *so, struct nhop_object *nh,
 		struct cpl_act_open_req *cpl = wrtod(wr);
 		struct cpl_t5_act_open_req *cpl5 = (void *)cpl;
 		struct cpl_t6_act_open_req *cpl6 = (void *)cpl;
+		struct cpl_t7_act_open_req *cpl7 = (void *)cpl;
 
 		switch (chip_id(sc)) {
 		case CHELSIO_T4:
 			INIT_TP_WR(cpl, 0);
-			cpl->params = select_ntuple(vi, toep->l2te);
+			cpl->params = htobe32((uint32_t)ntuple);
 			break;
 		case CHELSIO_T5:
 			INIT_TP_WR(cpl5, 0);
 			cpl5->iss = htobe32(tp->iss);
-			cpl5->params = select_ntuple(vi, toep->l2te);
+			cpl5->params = htobe64(V_FILTER_TUPLE(ntuple));
 			break;
 		case CHELSIO_T6:
-		default:
 			INIT_TP_WR(cpl6, 0);
 			cpl6->iss = htobe32(tp->iss);
-			cpl6->params = select_ntuple(vi, toep->l2te);
+			cpl6->params = htobe64(V_FILTER_TUPLE(ntuple));
 			break;
+		case CHELSIO_T7:
+		default:
+			INIT_TP_WR(cpl7, 0);
+			cpl7->iss = htobe32(tp->iss);
+			cpl7->params = htobe64(V_T7_FILTER_TUPLE(ntuple));
 		}
 		OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 		    qid_atid));
diff --git a/sys/dev/cxgbe/tom/t4_cpl_io.c b/sys/dev/cxgbe/tom/t4_cpl_io.c
index be20ea42474e..84e31efa8b58 100644
--- a/sys/dev/cxgbe/tom/t4_cpl_io.c
+++ b/sys/dev/cxgbe/tom/t4_cpl_io.c
@@ -127,8 +127,9 @@ send_flowc_wr(struct toepcb *toep, struct tcpcb *tp)
 	paramidx = 0;
 
 	FLOWC_PARAM(PFNVFN, pfvf);
-	FLOWC_PARAM(CH, pi->tx_chan);
-	FLOWC_PARAM(PORT, pi->tx_chan);
+	/* Firmware expects hw port and will translate to channel itself. */
+	FLOWC_PARAM(CH, pi->hw_port);
+	FLOWC_PARAM(PORT, pi->hw_port);
 	FLOWC_PARAM(IQID, toep->ofld_rxq->iq.abs_id);
 	FLOWC_PARAM(SNDBUF, toep->params.sndbuf);
 	if (tp) {
@@ -2050,9 +2051,18 @@ write_set_tcb_field(struct adapter *sc, void *dst, struct toepcb *toep,
 	}
 
 	INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, toep->tid);
-	req->reply_ctrl = htobe16(V_QUEUENO(toep->ofld_rxq->iq.abs_id));
-	if (reply == 0)
-		req->reply_ctrl |= htobe16(F_NO_REPLY);
+	if (reply == 0) {
+		req->reply_ctrl = htobe16(F_NO_REPLY);
+	} else {
+		const int qid = toep->ofld_rxq->iq.abs_id;
+		if (chip_id(sc) >= CHELSIO_T7) {
+			req->reply_ctrl = htobe16(V_T7_QUEUENO(qid) |
+			    V_T7_REPLY_CHAN(0) | V_NO_REPLY(0));
+		} else {
+			req->reply_ctrl = htobe16(V_QUEUENO(qid) |
+			    V_REPLY_CHAN(0) | V_NO_REPLY(0));
+		}
+	}
 	req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(cookie));
 	req->mask = htobe64(mask);
 	req->val = htobe64(val);
diff --git a/sys/dev/cxgbe/tom/t4_ddp.c b/sys/dev/cxgbe/tom/t4_ddp.c
index da0753296532..35fb1061d867 100644
--- a/sys/dev/cxgbe/tom/t4_ddp.c
+++ b/sys/dev/cxgbe/tom/t4_ddp.c
@@ -1655,7 +1655,10 @@ t4_write_page_pods_for_ps(struct adapter *sc, struct sge_wrq *wrq, int tid,
 
 		INIT_ULPTX_WR(ulpmc, len, 0, 0);
 		ulpmc->cmd = cmd;
-		ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk / 32));
+		if (chip_id(sc) >= CHELSIO_T7)
+			ulpmc->dlen = htobe32(V_T7_ULP_MEMIO_DATA_LEN(chunk >> 5));
+		else
+			ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk >> 5));
 		ulpmc->len16 = htobe32(howmany(len - sizeof(ulpmc->wr), 16));
 		ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(ppod_addr >> 5));
 
@@ -1842,7 +1845,10 @@ t4_write_page_pods_for_bio(struct adapter *sc, struct toepcb *toep,
 		ulpmc = mtod(m, struct ulp_mem_io *);
 		INIT_ULPTX_WR(ulpmc, len, 0, toep->tid);
 		ulpmc->cmd = cmd;
-		ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk / 32));
+		if (chip_id(sc) >= CHELSIO_T7)
+			ulpmc->dlen = htobe32(V_T7_ULP_MEMIO_DATA_LEN(chunk >> 5));
+		else
+			ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk >> 5));
 		ulpmc->len16 = htobe32(howmany(len - sizeof(ulpmc->wr), 16));
 		ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(ppod_addr >> 5));
 
@@ -1922,7 +1928,10 @@ t4_write_page_pods_for_buf(struct adapter *sc, struct toepcb *toep,
 
 		INIT_ULPTX_WR(ulpmc, len, 0, toep->tid);
 		ulpmc->cmd = cmd;
-		ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk / 32));
+		if (chip_id(sc) >= CHELSIO_T7)
+			ulpmc->dlen = htobe32(V_T7_ULP_MEMIO_DATA_LEN(chunk >> 5));
+		else
+			ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk >> 5));
 		ulpmc->len16 = htobe32(howmany(len - sizeof(ulpmc->wr), 16));
 		ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(ppod_addr >> 5));
 
@@ -2013,7 +2022,10 @@ t4_write_page_pods_for_sgl(struct adapter *sc, struct toepcb *toep,
 
 		INIT_ULPTX_WR(ulpmc, len, 0, toep->tid);
 		ulpmc->cmd = cmd;
-		ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk / 32));
+		if (chip_id(sc) >= CHELSIO_T7)
+			ulpmc->dlen = htobe32(V_T7_ULP_MEMIO_DATA_LEN(chunk >> 5));
+		else
+			ulpmc->dlen = htobe32(V_ULP_MEMIO_DATA_LEN(chunk >> 5));
 		ulpmc->len16 = htobe32(howmany(len - sizeof(ulpmc->wr), 16));
 		ulpmc->lock_addr = htobe32(V_ULP_MEMIO_ADDR(ppod_addr >> 5));
 
diff --git a/sys/dev/cxgbe/tom/t4_listen.c b/sys/dev/cxgbe/tom/t4_listen.c
index 06c495dcafc3..b879f6883f25 100644
--- a/sys/dev/cxgbe/tom/t4_listen.c
+++ b/sys/dev/cxgbe/tom/t4_listen.c
@@ -508,10 +508,11 @@ send_flowc_wr_synqe(struct adapter *sc, struct synq_entry *synqe)
 	    V_FW_WR_FLOWID(synqe->tid));
 	flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
 	flowc->mnemval[0].val = htobe32(pfvf);
+	/* Firmware expects hw port and will translate to channel itself. */
 	flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
-	flowc->mnemval[1].val = htobe32(pi->tx_chan);
+	flowc->mnemval[1].val = htobe32(pi->hw_port);
 	flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
-	flowc->mnemval[2].val = htobe32(pi->tx_chan);
+	flowc->mnemval[2].val = htobe32(pi->hw_port);
 	flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
 	flowc->mnemval[3].val = htobe32(ofld_rxq->iq.abs_id);
 	flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_SNDBUF;
@@ -1507,6 +1508,8 @@ found:
 
 	init_conn_params(vi, &settings, &inc, so, &cpl->tcpopt, e->idx,
 	    &synqe->params);
+	if (sc->params.tid_qid_sel_mask != 0)
+		update_tid_qid_sel(vi, &synqe->params, tid);
 
 	/*
 	 * If all goes well t4_syncache_respond will get called during
diff --git a/sys/dev/cxgbe/tom/t4_tls.c b/sys/dev/cxgbe/tom/t4_tls.c
index ad72c6a6b025..bbcc1c88c3db 100644
--- a/sys/dev/cxgbe/tom/t4_tls.c
+++ b/sys/dev/cxgbe/tom/t4_tls.c
@@ -207,7 +207,7 @@ int
 tls_alloc_ktls(struct toepcb *toep, struct ktls_session *tls, int direction)
 {
 	struct adapter *sc = td_adapter(toep->td);
-	int error, explicit_iv_size, mac_first;
+	int error, iv_size, mac_first;
 
 	if (!can_tls_offload(sc))
 		return (EINVAL);
@@ -228,6 +228,21 @@ tls_alloc_ktls(struct toepcb *toep, struct ktls_session *tls, int direction)
 		}
 	}
 
+	/* TLS 1.1 through TLS 1.3 are currently supported. */
+	if (tls->params.tls_vmajor != TLS_MAJOR_VER_ONE ||
+	    tls->params.tls_vminor < TLS_MINOR_VER_ONE ||
+	    tls->params.tls_vminor > TLS_MINOR_VER_THREE) {
+		return (EPROTONOSUPPORT);
+	}
+
+	/* TLS 1.3 is only supported on T7+. */
+	if (tls->params.tls_vminor == TLS_MINOR_VER_THREE) {
+		if (is_t6(sc)) {
+			return (EPROTONOSUPPORT);
+		}
+	}
+
+	/* Sanity check values in *tls. */
 	switch (tls->params.cipher_algorithm) {
 	case CRYPTO_AES_CBC:
 		/* XXX: Explicitly ignore any provided IV. */
@@ -247,13 +262,10 @@ tls_alloc_ktls(struct toepcb *toep, struct ktls_session *tls, int direction)
 		default:
 			return (EPROTONOSUPPORT);
 		}
-		explicit_iv_size = AES_BLOCK_LEN;
+		iv_size = AES_BLOCK_LEN;
 		mac_first = 1;
 		break;
 	case CRYPTO_AES_NIST_GCM_16:
-		if (tls->params.iv_len != SALT_SIZE) {
-			return (EINVAL);
-		}
 		switch (tls->params.cipher_key_len) {
 		case 128 / 8:
 		case 192 / 8:
@@ -262,20 +274,19 @@ tls_alloc_ktls(struct toepcb *toep, struct ktls_session *tls, int direction)
 		default:
 			return (EINVAL);
 		}
-		explicit_iv_size = 8;
+
+		/*
+		 * The IV size for TLS 1.2 is the explicit IV in the
+		 * record header.  For TLS 1.3 it is the size of the
+		 * sequence number.
+		 */
+		iv_size = 8;
 		mac_first = 0;
 		break;
 	default:
 		return (EPROTONOSUPPORT);
 	}
 
-	/* Only TLS 1.1 and TLS 1.2 are currently supported. */
-	if (tls->params.tls_vmajor != TLS_MAJOR_VER_ONE ||
-	    tls->params.tls_vminor < TLS_MINOR_VER_ONE ||
-	    tls->params.tls_vminor > TLS_MINOR_VER_TWO) {
-		return (EPROTONOSUPPORT);
-	}
-
 	/* Bail if we already have a key. */
 	if (direction == KTLS_TX) {
 		if (toep->tls.tx_key_addr != -1)
@@ -289,6 +300,7 @@ tls_alloc_ktls(struct toepcb *toep, struct ktls_session *tls, int direction)
 	if (error)
 		return (error);
 
+	toep->tls.tls13 = tls->params.tls_vminor == TLS_MINOR_VER_THREE;
 	if (direction == KTLS_TX) {
 		toep->tls.scmd0.seqno_numivs =
 			(V_SCMD_SEQ_NO_CTRL(3) |
@@ -298,14 +310,14 @@ tls_alloc_ktls(struct toepcb *toep, struct ktls_session *tls, int direction)
 			 V_SCMD_CIPH_MODE(t4_tls_cipher_mode(tls)) |
 			 V_SCMD_AUTH_MODE(t4_tls_auth_mode(tls)) |
 			 V_SCMD_HMAC_CTRL(t4_tls_hmac_ctrl(tls)) |
-			 V_SCMD_IV_SIZE(explicit_iv_size / 2));
+			 V_SCMD_IV_SIZE(iv_size / 2));
 
 		toep->tls.scmd0.ivgen_hdrlen =
 			(V_SCMD_IV_GEN_CTRL(1) |
 			 V_SCMD_KEY_CTX_INLINE(0) |
 			 V_SCMD_TLS_FRAG_ENABLE(1));
 
-		toep->tls.iv_len = explicit_iv_size;
+		toep->tls.iv_len = iv_size;
 		toep->tls.frag_size = tls->params.max_frame_len;
 		toep->tls.fcplenmax = get_tp_plen_max(tls);
 		toep->tls.expn_per_ulp = tls->params.tls_hlen +
@@ -352,7 +364,8 @@ tls_uninit_toep(struct toepcb *toep)
 
 static void
 write_tlstx_wr(struct fw_tlstx_data_wr *txwr, struct toepcb *toep,
-    unsigned int plen, unsigned int expn, uint8_t credits, int shove)
+    unsigned int plen, unsigned int expn, uint8_t credits, int shove,
+    int num_ivs)
 {
 	struct tls_ofld_info *tls_ofld = &toep->tls;
 	unsigned int len = plen + expn;
@@ -365,7 +378,7 @@ write_tlstx_wr(struct fw_tlstx_data_wr *txwr, struct toepcb *toep,
 	txwr->plen = htobe32(len);
 	txwr->lsodisable_to_flags = htobe32(V_TX_ULP_MODE(ULP_MODE_TLS) |
 	    V_TX_URG(0) | /* F_T6_TX_FORCE | */ V_TX_SHOVE(shove));
-	txwr->ctxloc_to_exp = htobe32(V_FW_TLSTX_DATA_WR_NUMIVS(1) |
+	txwr->ctxloc_to_exp = htobe32(V_FW_TLSTX_DATA_WR_NUMIVS(num_ivs) |
 	    V_FW_TLSTX_DATA_WR_EXP(expn) |
 	    V_FW_TLSTX_DATA_WR_CTXLOC(TLS_SFO_WR_CONTEXTLOC_DDR) |
 	    V_FW_TLSTX_DATA_WR_IVDSGL(0) |
@@ -381,20 +394,20 @@ write_tlstx_wr(struct fw_tlstx_data_wr *txwr, struct toepcb *toep,
 
 static void
 write_tlstx_cpl(struct cpl_tx_tls_sfo *cpl, struct toepcb *toep,
-    struct tls_hdr *tls_hdr, unsigned int plen, uint64_t seqno)
+    struct tls_hdr *tls_hdr, unsigned int plen, uint8_t rec_type,
+    uint64_t seqno)
 {
 	struct tls_ofld_info *tls_ofld = &toep->tls;
 	int data_type, seglen;
 
 	seglen = plen;
-	data_type = tls_content_type(tls_hdr->type);
+	data_type = tls_content_type(rec_type);
 	cpl->op_to_seg_len = htobe32(V_CPL_TX_TLS_SFO_OPCODE(CPL_TX_TLS_SFO) |
 	    V_CPL_TX_TLS_SFO_DATA_TYPE(data_type) |
 	    V_CPL_TX_TLS_SFO_CPL_LEN(2) | V_CPL_TX_TLS_SFO_SEG_LEN(seglen));
 	cpl->pld_len = htobe32(plen);
 	if (data_type == CPL_TX_TLS_SFO_TYPE_CUSTOM)
-		cpl->type_protover = htobe32(
-		    V_CPL_TX_TLS_SFO_TYPE(tls_hdr->type));
+		cpl->type_protover = htobe32(V_CPL_TX_TLS_SFO_TYPE(rec_type));
 	cpl->seqno_numivs = htobe32(tls_ofld->scmd0.seqno_numivs |
 	    V_SCMD_NUM_IVS(1));
 	cpl->ivgen_hdrlen = htobe32(tls_ofld->scmd0.ivgen_hdrlen);
@@ -498,6 +511,7 @@ t4_push_ktls(struct adapter *sc, struct toepcb *toep, int drop)
 	int tls_size, tx_credits, shove, sowwakeup;
 	struct ofld_tx_sdesc *txsd;
 	char *buf;
+	bool tls13;
 
 	INP_WLOCK_ASSERT(inp);
 	KASSERT(toep->flags & TPF_FLOWC_WR_SENT,
@@ -533,6 +547,7 @@ t4_push_ktls(struct adapter *sc, struct toepcb *toep, int drop)
 		return;
 	}
 
+	tls13 = toep->tls.tls13;
 	txsd = &toep->txsd[toep->txsd_pidx];
 	for (;;) {
 		tx_credits = min(toep->tx_credits, MAX_OFLD_TX_CREDITS);
@@ -599,9 +614,11 @@ t4_push_ktls(struct adapter *sc, struct toepcb *toep, int drop)
 		    sizeof(struct cpl_tx_tls_sfo) +
 		    sizeof(struct ulptx_idata) + sizeof(struct ulptx_sc_memrd);
 
-		/* Explicit IVs for AES-CBC and AES-GCM are <= 16. */
-		MPASS(toep->tls.iv_len <= AES_BLOCK_LEN);
-		wr_len += AES_BLOCK_LEN;
+		if (!tls13) {
+			/* Explicit IVs for AES-CBC and AES-GCM are <= 16. */
+			MPASS(toep->tls.iv_len <= AES_BLOCK_LEN);
+			wr_len += AES_BLOCK_LEN;
+		}
 
 		/* Account for SGL in work request length. */
 		nsegs = count_ext_pgs_segs(m);
@@ -671,8 +688,10 @@ t4_push_ktls(struct adapter *sc, struct toepcb *toep, int drop)
 		expn_size = m->m_epg_hdrlen +
 		    m->m_epg_trllen;
 		tls_size = m->m_len - expn_size;
-		write_tlstx_wr(txwr, toep, tls_size, expn_size, credits, shove);
-		write_tlstx_cpl(cpl, toep, thdr, tls_size, m->m_epg_seqno);
+		write_tlstx_wr(txwr, toep, tls_size, expn_size, credits, shove,
+		    tls13 ? 0 : 1);
+		write_tlstx_cpl(cpl, toep, thdr, tls_size,
+		    tls13 ? m->m_epg_record_type : thdr->type, m->m_epg_seqno);
 
 		idata = (struct ulptx_idata *)(cpl + 1);
 		idata->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
@@ -683,10 +702,12 @@ t4_push_ktls(struct adapter *sc, struct toepcb *toep, int drop)
 		    V_ULPTX_LEN16(toep->tls.tx_key_info_size >> 4));
 		memrd->addr = htobe32(toep->tls.tx_key_addr >> 5);
 
-		/* Copy IV. */
 		buf = (char *)(memrd + 1);
-		memcpy(buf, thdr + 1, toep->tls.iv_len);
-		buf += AES_BLOCK_LEN;
+		if (!tls13) {
+			/* Copy IV. */
+			memcpy(buf, thdr + 1, toep->tls.iv_len);
+			buf += AES_BLOCK_LEN;
+		}
 
 		write_ktlstx_sgl(buf, m, nsegs);
 
@@ -808,8 +829,8 @@ do_rx_tls_cmp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
 	struct sockbuf *sb;
 	struct mbuf *tls_data;
 	struct tls_get_record *tgr;
-	struct mbuf *control;
-	int pdu_length, trailer_len;
+	struct mbuf *control, *n;
+	int pdu_length, resid, trailer_len;
 #if defined(KTR) || defined(INVARIANTS)
 	int len;
 #endif
@@ -857,7 +878,9 @@ do_rx_tls_cmp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
 
 	/*
 	 * The payload of this CPL is the TLS header followed by
-	 * additional fields.
+	 * additional fields.  For TLS 1.3 the type field holds the
+	 * inner record type and the length field has been updated to
+	 * strip the inner record type, padding, and MAC.
 	 */
 	KASSERT(m->m_len >= sizeof(*tls_hdr_pkt),
 	    ("%s: payload too small", __func__));
@@ -869,7 +892,14 @@ do_rx_tls_cmp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
 		    ("%s: sequence mismatch", __func__));
 	}
 
-	/* Report decryption errors as EBADMSG. */
+	/*
+	 * Report decryption errors as EBADMSG.
+	 *
+	 * XXX: To support rekeying for TLS 1.3 this will eventually
+	 * have to be updated to recrypt the data with the old key and
+	 * then decrypt with the new key.  Punt for now as KTLS
+	 * doesn't yet support rekeying.
+	 */
 	if ((tls_hdr_pkt->res_to_mac_error & M_TLSRX_HDR_PKT_ERROR) != 0) {
 		CTR4(KTR_CXGBE, "%s: tid %u TLS error %#x ddp_vld %#x",
 		    __func__, toep->tid, tls_hdr_pkt->res_to_mac_error,
@@ -887,6 +917,33 @@ do_rx_tls_cmp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
 		return (0);
 	}
 
+	/* For TLS 1.3 trim the header and trailer. */
+	if (toep->tls.tls13) {
+		KASSERT(tls_data != NULL, ("%s: TLS 1.3 record without data",
+		    __func__));
+		MPASS(tls_data->m_pkthdr.len == pdu_length);
+		m_adj(tls_data, sizeof(struct tls_record_layer));
+		if (tls_data->m_pkthdr.len > be16toh(tls_hdr_pkt->length))
+			tls_data->m_pkthdr.len = be16toh(tls_hdr_pkt->length);
+		resid = tls_data->m_pkthdr.len;
+		if (resid == 0) {
+			m_freem(tls_data);
+			tls_data = NULL;
+		} else {
+			for (n = tls_data;; n = n->m_next) {
+				if (n->m_len < resid) {
+					resid -= n->m_len;
+					continue;
+				}
+
+				n->m_len = resid;
+				m_freem(n->m_next);
+				n->m_next = NULL;
+				break;
+			}
+		}
+	}
+
 	/* Handle data received after the socket is closed. */
 	sb = &so->so_rcv;
 	SOCKBUF_LOCK(sb);
@@ -1091,33 +1148,60 @@ out:
 }
 
 /*
- * Send a work request setting multiple TCB fields to enable
- * ULP_MODE_TLS.
+ * Send a work request setting one or more TCB fields to partially or
+ * fully enable ULP_MODE_TLS.
+ *
+ * - If resid == 0, the socket buffer ends at a record boundary
+ *   (either empty or contains one or more complete records).  Switch
+ *   to ULP_MODE_TLS (if not already) and enable TLS decryption.
+ *
+ * - If resid != 0, the socket buffer contains a partial record.  In
+ *   this case, switch to ULP_MODE_TLS partially and configure the TCB
+ *   to pass along the remaining resid bytes undecrypted.  Once they
+ *   arrive, this is called again with resid == 0 and enables TLS
+ *   decryption.
  */
 static void
-tls_update_tcb(struct adapter *sc, struct toepcb *toep, uint64_t seqno)
+tls_update_tcb(struct adapter *sc, struct toepcb *toep, uint64_t seqno,
+    size_t resid)
 {
 	struct mbuf *m;
 	struct work_request_hdr *wrh;
 	struct ulp_txpkt *ulpmc;
 	int fields, key_offset, len;
 
-	KASSERT(ulp_mode(toep) == ULP_MODE_NONE,
-	    ("%s: tid %d already ULP_MODE_TLS", __func__, toep->tid));
+	/*
+	 * If we are already in ULP_MODE_TLS, then we should now be at
+	 * a record boundary and ready to finish enabling TLS RX.
+	 */
+	KASSERT(resid == 0 || ulp_mode(toep) == ULP_MODE_NONE,
+	    ("%s: tid %d needs %zu more data but already ULP_MODE_TLS",
+	    __func__, toep->tid, resid));
 
 	fields = 0;
+	if (ulp_mode(toep) == ULP_MODE_NONE) {
+		/* 2 writes for the overlay region */
+		fields += 2;
+	}
 
-	/* 2 writes for the overlay region */
-	fields += 2;
+	if (resid == 0) {
+		/* W_TCB_TLS_SEQ */
+		fields++;
 
-	/* W_TCB_TLS_SEQ */
-	fields++;
+		/* W_TCB_ULP_RAW */
+		fields++;
+	} else {
+		/* W_TCB_PDU_LEN */
+		fields++;
 
-	/* W_TCB_ULP_RAW */
-	fields++;
+		/* W_TCB_ULP_RAW */
+		fields++;
+	}
 
-	/* W_TCB_ULP_TYPE */
-	fields ++;
+	if (ulp_mode(toep) == ULP_MODE_NONE) {
+		/* W_TCB_ULP_TYPE */
+		fields ++;
+	}
 
 	/* W_TCB_T_FLAGS */
 	fields++;
@@ -1136,43 +1220,78 @@ tls_update_tcb(struct adapter *sc, struct toepcb *toep, uint64_t seqno)
 	INIT_ULPTX_WRH(wrh, len, 1, toep->tid);	/* atomic */
 	ulpmc = (struct ulp_txpkt *)(wrh + 1);
 
-	/*
-	 * Clear the TLS overlay region: 1023:832.
-	 *
-	 * Words 26/27 are always set to zero.  Words 28/29
-	 * contain seqno and are set when enabling TLS
-	 * decryption.  Word 30 is zero and Word 31 contains
-	 * the keyid.
-	 */
-	ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, 26,
-	    0xffffffffffffffff, 0);
+	if (ulp_mode(toep) == ULP_MODE_NONE) {
+		/*
+		 * Clear the TLS overlay region: 1023:832.
+		 *
+		 * Words 26/27 are always set to zero.  Words 28/29
+		 * contain seqno and are set when enabling TLS
+		 * decryption.  Word 30 is zero and Word 31 contains
+		 * the keyid.
+		 */
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, 26,
+		    0xffffffffffffffff, 0);
 
-	/*
-	 * RX key tags are an index into the key portion of MA
-	 * memory stored as an offset from the base address in
-	 * units of 64 bytes.
-	 */
-	key_offset = toep->tls.rx_key_addr - sc->vres.key.start;
-	ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, 30,
-	    0xffffffffffffffff,
-	    (uint64_t)V_TCB_RX_TLS_KEY_TAG(key_offset / 64) << 32);
-
-	CTR3(KTR_CXGBE, "%s: tid %d enable TLS seqno %lu", __func__,
-	    toep->tid, seqno);
-	ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, W_TCB_TLS_SEQ,
-	    V_TCB_TLS_SEQ(M_TCB_TLS_SEQ), V_TCB_TLS_SEQ(seqno));
-	ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, W_TCB_ULP_RAW,
-	    V_TCB_ULP_RAW(M_TCB_ULP_RAW),
-	    V_TCB_ULP_RAW((V_TF_TLS_KEY_SIZE(3) | V_TF_TLS_CONTROL(1) |
-	    V_TF_TLS_ACTIVE(1) | V_TF_TLS_ENABLE(1))));
-
-	toep->flags &= ~TPF_TLS_STARTING;
-	toep->flags |= TPF_TLS_RECEIVE;
-
-	/* Set the ULP mode to ULP_MODE_TLS. */
-	toep->params.ulp_mode = ULP_MODE_TLS;
-	ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, W_TCB_ULP_TYPE,
-	    V_TCB_ULP_TYPE(M_TCB_ULP_TYPE), V_TCB_ULP_TYPE(ULP_MODE_TLS));
+		/*
+		 * RX key tags are an index into the key portion of MA
+		 * memory stored as an offset from the base address in
+		 * units of 64 bytes.
+		 */
+		key_offset = toep->tls.rx_key_addr - sc->vres.key.start;
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, 30,
+		    0xffffffffffffffff,
+		    (uint64_t)V_TCB_RX_TLS_KEY_TAG(key_offset / 64) << 32);
+	}
+
+	if (resid == 0) {
+		/*
+		 * The socket buffer is empty or only contains
+		 * complete TLS records: Set the sequence number and
+		 * enable TLS decryption.
+		 */
+		CTR3(KTR_CXGBE, "%s: tid %d enable TLS seqno %lu", __func__,
+		    toep->tid, seqno);
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid,
+		    W_TCB_RX_TLS_SEQ, V_TCB_RX_TLS_SEQ(M_TCB_RX_TLS_SEQ),
+		    V_TCB_RX_TLS_SEQ(seqno));
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid,
+		    W_TCB_ULP_RAW, V_TCB_ULP_RAW(M_TCB_ULP_RAW),
+		    V_TCB_ULP_RAW((V_TF_TLS_KEY_SIZE(3) | V_TF_TLS_CONTROL(1) |
+		    V_TF_TLS_ACTIVE(1) | V_TF_TLS_ENABLE(1))));
+
+		toep->flags &= ~TPF_TLS_STARTING;
+		toep->flags |= TPF_TLS_RECEIVE;
+	} else {
+		/*
+		 * The socket buffer ends with a partial record with a
+		 * full header and needs at least 6 bytes.
+		 *
+		 * Set PDU length.  This is treating the 'resid' bytes
+		 * as a TLS PDU, so the first 5 bytes are a fake
+		 * header and the rest are the PDU length.
+		 */
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid,
+		    W_TCB_PDU_LEN, V_TCB_PDU_LEN(M_TCB_PDU_LEN),
+		    V_TCB_PDU_LEN(resid - sizeof(struct tls_hdr)));
+		CTR3(KTR_CXGBE, "%s: tid %d setting PDU_LEN to %zu",
+		    __func__, toep->tid, resid - sizeof(struct tls_hdr));
+
+		/* Clear all bits in ULP_RAW except for ENABLE. */
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid,
+		    W_TCB_ULP_RAW, V_TCB_ULP_RAW(M_TCB_ULP_RAW),
+		    V_TCB_ULP_RAW(V_TF_TLS_ENABLE(1)));
+
+		/* Wait for 'resid' bytes to be delivered as CPL_RX_DATA. */
+		toep->tls.rx_resid = resid;
+	}
+
+	if (ulp_mode(toep) == ULP_MODE_NONE) {
+		/* Set the ULP mode to ULP_MODE_TLS. */
+		toep->params.ulp_mode = ULP_MODE_TLS;
+		ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid,
+		    W_TCB_ULP_TYPE, V_TCB_ULP_TYPE(M_TCB_ULP_TYPE),
+		    V_TCB_ULP_TYPE(ULP_MODE_TLS));
+	}
 
 	/* Clear TF_RX_QUIESCE. */
 	ulpmc = mk_set_tcb_field_ulp(sc, ulpmc, toep->tid, W_TCB_T_FLAGS,
@@ -1205,7 +1324,8 @@ tls_check_rx_sockbuf(struct adapter *sc, struct toepcb *toep,
 	 * size of a TLS record, re-enable receive and pause again once
 	 * we get more data to try again.
 	 */
-	if (!have_header || resid != 0) {
+	if (!have_header || (resid != 0 && (resid < sizeof(struct tls_hdr) ||
+	    is_t6(sc)))) {
 		CTR(KTR_CXGBE, "%s: tid %d waiting for more data", __func__,
 		    toep->tid);
 		toep->flags &= ~TPF_TLS_RX_QUIESCED;
@@ -1213,7 +1333,7 @@ tls_check_rx_sockbuf(struct adapter *sc, struct toepcb *toep,
 		return;
 	}
 
-	tls_update_tcb(sc, toep, seqno);
+	tls_update_tcb(sc, toep, seqno, resid);
 }
 
 void
diff --git a/sys/dev/cxgbe/tom/t4_tls.h b/sys/dev/cxgbe/tom/t4_tls.h
index 753a30890fdc..6faf946e9e3c 100644
--- a/sys/dev/cxgbe/tom/t4_tls.h
+++ b/sys/dev/cxgbe/tom/t4_tls.h
@@ -74,6 +74,7 @@ struct tls_ofld_info {
 	unsigned short adjusted_plen;
 	unsigned short expn_per_ulp;
 	unsigned short pdus_per_ulp;
+	bool tls13;
 	struct tls_scmd scmd0;
 	u_int iv_len;
 	unsigned int tx_key_info_size;
diff --git a/sys/dev/cxgbe/tom/t4_tom.c b/sys/dev/cxgbe/tom/t4_tom.c
index 0b54fdaa5c80..53a945f8b4cc 100644
--- a/sys/dev/cxgbe/tom/t4_tom.c
+++ b/sys/dev/cxgbe/tom/t4_tom.c
@@ -182,7 +182,7 @@ init_toepcb(struct vi_info *vi, struct toepcb *toep)
 	}
 	toep->ofld_txq = &sc->sge.ofld_txq[cp->txq_idx];
 	toep->ofld_rxq = &sc->sge.ofld_rxq[cp->rxq_idx];
-	toep->ctrlq = &sc->sge.ctrlq[pi->port_id];
+	toep->ctrlq = &sc->sge.ctrlq[cp->ctrlq_idx];
 
 	tls_init_toep(toep);
 	MPASS(ulp_mode(toep) != ULP_MODE_TCPDDP);
@@ -494,8 +494,15 @@ send_get_tcb(struct adapter *sc, u_int tid)
 	bzero(cpl, sizeof(*cpl));
 	INIT_TP_WR(cpl, tid);
 	OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_GET_TCB, tid));
-	cpl->reply_ctrl = htobe16(V_REPLY_CHAN(0) |
-	    V_QUEUENO(sc->sge.ofld_rxq[0].iq.cntxt_id));
+	if (chip_id(sc) >= CHELSIO_T7) {
+		cpl->reply_ctrl =
+		    htobe16(V_T7_QUEUENO(sc->sge.ofld_rxq[0].iq.cntxt_id) |
+			V_T7_REPLY_CHAN(0) | V_NO_REPLY(0));
+	} else {
+		cpl->reply_ctrl =
+		    htobe16(V_QUEUENO(sc->sge.ofld_rxq[0].iq.cntxt_id) |
+			V_REPLY_CHAN(0) | V_NO_REPLY(0));
+	}
 	cpl->cookie = 0xff;
 	commit_wrq_wr(&sc->sge.ctrlq[0], cpl, &cookie);
 
@@ -1221,7 +1228,7 @@ select_ntuple(struct vi_info *vi, struct l2t_entry *e)
 		ntuple |= (uint64_t)(F_FT_VLAN_VLD | e->vlan) << tp->vlan_shift;
 
 	if (tp->port_shift >= 0)
-		ntuple |= (uint64_t)e->lport << tp->port_shift;
+		ntuple |= (uint64_t)e->hw_port << tp->port_shift;
 
 	if (tp->protocol_shift >= 0)
 		ntuple |= (uint64_t)IPPROTO_TCP << tp->protocol_shift;
@@ -1232,10 +1239,7 @@ select_ntuple(struct vi_info *vi, struct l2t_entry *e)
 		    tp->vnic_shift;
 	}
 
-	if (is_t4(sc))
-		return (htobe32((uint32_t)ntuple));
-	else
-		return (htobe64(V_FILTER_TUPLE(ntuple)));
+	return (ntuple);
 }
 
 /*
@@ -1326,6 +1330,9 @@ init_conn_params(struct vi_info *vi , struct offload_settings *s,
 	 */
 	cp->mtu_idx = find_best_mtu_idx(sc, inc, s);
 
+	/* Control queue. */
+	cp->ctrlq_idx = vi->pi->port_id;
+
 	/* Tx queue for this connection. */
 	if (s->txq == QUEUE_RANDOM)
 		q_idx = arc4random();
@@ -1438,6 +1445,32 @@ init_conn_params(struct vi_info *vi , struct offload_settings *s,
 	cp->emss = 0;
 }
 
+void
+update_tid_qid_sel(struct vi_info *vi, struct conn_params *cp, int tid)
+{
+	struct adapter *sc = vi->adapter;
+	const int mask = sc->params.tid_qid_sel_mask;
+	struct sge_ofld_txq *ofld_txq = &sc->sge.ofld_txq[cp->txq_idx];
+	uint32_t ngroup;
+	int g, nqpg;
+
+	cp->ctrlq_idx = ofld_txq_group(tid, mask);
+	CTR(KTR_CXGBE, "tid %u is on core %u", tid, cp->ctrlq_idx);
+	if ((ofld_txq->wrq.eq.cntxt_id & mask) == (tid & mask))
+		return;
+
+	ngroup = 1 << bitcount32(mask);
+	MPASS(vi->nofldtxq % ngroup == 0);
+	g = ofld_txq_group(tid, mask);
+	nqpg = vi->nofldtxq / ngroup;
+	cp->txq_idx = vi->first_ofld_txq + g * nqpg + arc4random() % nqpg;
+#ifdef INVARIANTS
+	MPASS(cp->txq_idx < vi->first_ofld_txq + vi->nofldtxq);
+	ofld_txq = &sc->sge.ofld_txq[cp->txq_idx];
+	MPASS((ofld_txq->wrq.eq.cntxt_id & mask) == (tid & mask));
+#endif
+}
+
 int
 negative_advice(int status)
 {
@@ -2233,6 +2266,98 @@ t4_aio_queue_tom(struct socket *so, struct kaiocb *job)
 		return (0);
 }
 
+/*
+ * Request/response structure used to find out the adapter offloading
+ * a socket.
+ */
+struct find_offload_adapter_data {
+	struct socket *so;
+	struct adapter *sc;	/* result */
+};
+
+static void
+find_offload_adapter_cb(struct adapter *sc, void *arg)
+{
+	struct find_offload_adapter_data *fa = arg;
+	struct socket *so = fa->so;
+	struct tom_data *td = sc->tom_softc;
+	struct tcpcb *tp;
+	struct inpcb *inp;
+
+	/* Non-TCP were filtered out earlier. */
+	MPASS(so->so_proto->pr_protocol == IPPROTO_TCP);
+
+	if (fa->sc != NULL)
+		return;	/* Found already. */
+
+	if (td == NULL)
+		return;	/* TOE not enabled on this adapter. */
+
+	inp = sotoinpcb(so);
+	INP_WLOCK(inp);
+	if ((inp->inp_flags & INP_DROPPED) == 0) {
+		tp = intotcpcb(inp);
+		if (tp->t_flags & TF_TOE && tp->tod == &td->tod)
+			fa->sc = sc;	/* Found. */
+	}
+	INP_WUNLOCK(inp);
+}
+
+struct adapter *
+find_offload_adapter(struct socket *so)
+{
+	struct find_offload_adapter_data fa;
+
+	fa.sc = NULL;
+	fa.so = so;
+	t4_iterate(find_offload_adapter_cb, &fa);
+	return (fa.sc);
+}
+
+void
+send_txdataplen_max_flowc_wr(struct adapter *sc, struct toepcb *toep,
+    int maxlen)
+{
+	struct wrqe *wr;
+	struct fw_flowc_wr *flowc;
+	const u_int nparams = 1;
+	u_int flowclen;
+	struct ofld_tx_sdesc *txsd = &toep->txsd[toep->txsd_pidx];
+
+	CTR(KTR_CXGBE, "%s: tid %u maxlen=%d", __func__, toep->tid, maxlen);
+
+	flowclen = sizeof(*flowc) + nparams * sizeof(struct fw_flowc_mnemval);
+
+	wr = alloc_wrqe(roundup2(flowclen, 16), &toep->ofld_txq->wrq);
+	if (wr == NULL) {
+		/* XXX */
+		panic("%s: allocation failure.", __func__);
+	}
+	flowc = wrtod(wr);
+	memset(flowc, 0, wr->wr_len);
+
+	flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
+	    V_FW_FLOWC_WR_NPARAMS(nparams));
+	flowc->flowid_len16 = htonl(V_FW_WR_LEN16(howmany(flowclen, 16)) |
+	    V_FW_WR_FLOWID(toep->tid));
+
+	flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_TXDATAPLEN_MAX;
+	flowc->mnemval[0].val = htobe32(maxlen);
+
+	KASSERT(howmany(flowclen, 16) <= MAX_OFLD_TX_SDESC_CREDITS,
+	    ("%s: tx_credits %u too large", __func__, howmany(flowclen, 16)));
+	txsd->tx_credits = howmany(flowclen, 16);
+	txsd->plen = 0;
+	KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0,
+	    ("%s: not enough credits (%d)", __func__, toep->tx_credits));
+	toep->tx_credits -= txsd->tx_credits;
+	if (__predict_false(++toep->txsd_pidx == toep->txsd_total))
+		toep->txsd_pidx = 0;
+	toep->txsd_avail--;
+
+	t4_wrq_tx(sc, wr);
+}
+
 static int
 t4_tom_mod_load(void)
 {
diff --git a/sys/dev/cxgbe/tom/t4_tom.h b/sys/dev/cxgbe/tom/t4_tom.h
index 4fb87d92d91e..c8c2d432b8f1 100644
--- a/sys/dev/cxgbe/tom/t4_tom.h
+++ b/sys/dev/cxgbe/tom/t4_tom.h
@@ -113,6 +113,7 @@ struct conn_params {
 	int8_t mtu_idx;
 	int8_t ulp_mode;
 	int8_t tx_align;
+	int8_t ctrlq_idx;	/* ctrlq = &sc->sge.ctrlq[ctrlq_idx] */
 	int16_t txq_idx;	/* ofld_txq = &sc->sge.ofld_txq[txq_idx] */
 	int16_t rxq_idx;	/* ofld_rxq = &sc->sge.ofld_rxq[rxq_idx] */
 	int16_t l2t_idx;
@@ -477,11 +478,14 @@ int select_rcv_wscale(void);
 void init_conn_params(struct vi_info *, struct offload_settings *,
     struct in_conninfo *, struct socket *, const struct tcp_options *, int16_t,
     struct conn_params *cp);
+void update_tid_qid_sel(struct vi_info *, struct conn_params *, int);
 __be64 calc_options0(struct vi_info *, struct conn_params *);
 __be32 calc_options2(struct vi_info *, struct conn_params *);
 uint64_t select_ntuple(struct vi_info *, struct l2t_entry *);
 int negative_advice(int);
 int add_tid_to_history(struct adapter *, u_int);
+struct adapter *find_offload_adapter(struct socket *);
+void send_txdataplen_max_flowc_wr(struct adapter *, struct toepcb *, int);
 void t4_pcb_detach(struct toedev *, struct tcpcb *);
 
 /* t4_connect.c */
@@ -582,4 +586,10 @@ int tls_tx_key(struct toepcb *);
 void tls_uninit_toep(struct toepcb *);
 int tls_alloc_ktls(struct toepcb *, struct ktls_session *, int);
 
+/* t4_tpt.c */
+uint32_t t4_pblpool_alloc(struct adapter *, int);
+void t4_pblpool_free(struct adapter *, uint32_t, int);
+int t4_pblpool_create(struct adapter *);
+void t4_pblpool_destroy(struct adapter *);
+
 #endif
diff --git a/sys/dev/cxgbe/tom/t4_tom_l2t.c b/sys/dev/cxgbe/tom/t4_tom_l2t.c
index 3fd0d5ca41d4..e245c2b6fd5b 100644
--- a/sys/dev/cxgbe/tom/t4_tom_l2t.c
+++ b/sys/dev/cxgbe/tom/t4_tom_l2t.c
@@ -403,7 +403,7 @@ t4_l2t_get(struct port_info *pi, if_t ifp, struct sockaddr *sa)
 		l2_store(sa, e);
 		e->ifp = ifp;
 		e->hash = hash;
-		e->lport = pi->lport;
+		e->hw_port = pi->hw_port;
 		e->wrq = &sc->sge.ctrlq[pi->port_id];
 		e->iqid = sc->sge.ofld_rxq[pi->vi[0].first_ofld_rxq].iq.abs_id;
 		atomic_store_rel_int(&e->refcnt, 1);
diff --git a/sys/dev/gpio/gpioc.c b/sys/dev/gpio/gpioc.c
index 5a60f939dc78..6c6f79227166 100644
--- a/sys/dev/gpio/gpioc.c
+++ b/sys/dev/gpio/gpioc.c
@@ -704,7 +704,7 @@ gpioc_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
 	 * npins isn't a horrible fifo size for that either.
 	 */
 	priv->numevents = priv->sc->sc_npins * 2;
-	priv->events = malloc(priv->numevents * sizeof(struct gpio_event_detail),
+	priv->events = malloc(priv->numevents * sizeof(struct gpioc_pin_event),
 	    M_GPIOC, M_WAITOK | M_ZERO);
 
 	priv->evidx_head = priv->evidx_tail = 0;
@@ -793,6 +793,7 @@ gpioc_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int fflag,
 	struct gpio_access_32 *a32;
 	struct gpio_config_32 *c32;
 	struct gpio_event_config *evcfg;
+	struct gpioc_pin_event *tmp;
 	uint32_t caps, intrflags;
 
 	switch (cmd) {
@@ -908,27 +909,35 @@ gpioc_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int fflag,
 		res = devfs_get_cdevpriv((void **)&priv);
 		if (res != 0)
 			break;
-		/* If any pins have been configured, changes aren't allowed. */
-		if (!SLIST_EMPTY(&priv->pins)) {
-			res = EINVAL;
-			break;
-		}
 		if (evcfg->gp_report_type != GPIO_EVENT_REPORT_DETAIL &&
 		    evcfg->gp_report_type != GPIO_EVENT_REPORT_SUMMARY) {
 			res = EINVAL;
 			break;
 		}
-		priv->report_option = evcfg->gp_report_type;
 		/* Reallocate the events buffer if the user wants it bigger. */
-		if (priv->report_option == GPIO_EVENT_REPORT_DETAIL &&
+		tmp = NULL;
+		if (evcfg->gp_report_type == GPIO_EVENT_REPORT_DETAIL &&
 		    priv->numevents < evcfg->gp_fifo_size) {
+			tmp = malloc(evcfg->gp_fifo_size *
+			    sizeof(struct gpioc_pin_event), M_GPIOC,
+			    M_WAITOK | M_ZERO);
+		}
+		mtx_lock(&priv->mtx);
+		/* If any pins have been configured, changes aren't allowed. */
+		if (!SLIST_EMPTY(&priv->pins)) {
+			mtx_unlock(&priv->mtx);
+			free(tmp, M_GPIOC);
+			res = EINVAL;
+			break;
+		}
+		if (tmp != NULL) {
 			free(priv->events, M_GPIOC);
+			priv->events = tmp;
 			priv->numevents = evcfg->gp_fifo_size;
-			priv->events = malloc(priv->numevents *
-			    sizeof(struct gpio_event_detail), M_GPIOC,
-			    M_WAITOK | M_ZERO);
 			priv->evidx_head = priv->evidx_tail = 0;
 		}
+		priv->report_option = evcfg->gp_report_type;
+		mtx_unlock(&priv->mtx);
 		break;
 	case FIONBIO:
 		/*
diff --git a/sys/dev/gpio/pl061.c b/sys/dev/gpio/pl061.c
index 32109e5982bc..9996b0253c7d 100644
--- a/sys/dev/gpio/pl061.c
+++ b/sys/dev/gpio/pl061.c
@@ -558,8 +558,7 @@ static device_method_t pl061_methods[] = {
 
 	/* Bus interface */
 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
-	DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
-	DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 
 	/* GPIO protocol */
 	DEVMETHOD(gpio_get_bus,		pl061_get_bus),
diff --git a/sys/dev/iwx/if_iwx.c b/sys/dev/iwx/if_iwx.c
index 8422fcb787c3..04ed09f04604 100644
--- a/sys/dev/iwx/if_iwx.c
+++ b/sys/dev/iwx/if_iwx.c
@@ -4805,6 +4805,8 @@ iwx_rx_tx_cmd(struct iwx_softc *sc, struct iwx_rx_packet *pkt,
 static void
 iwx_clear_oactive(struct iwx_softc *sc, struct iwx_tx_ring *ring)
 {
+	IWX_ASSERT_LOCKED(sc);
+
 	if (ring->queued < iwx_lomark) {
 		sc->qfullmsk &= ~(1 << ring->qid);
 		if (sc->qfullmsk == 0 /* && ifq_is_oactive(&ifp->if_snd) */) {
@@ -4890,11 +4892,19 @@ iwx_rx_bmiss(struct iwx_softc *sc, struct iwx_rx_packet *pkt,
 	bus_dmamap_sync(sc->rxq.data_dmat, data->map,
 	    BUS_DMASYNC_POSTREAD);
 
+	IWX_DPRINTF(sc, IWX_DEBUG_BEACON,
+	    "%s: mac_id=%u, cmslrx=%u, cmb=%u, neb=%d, nrb=%u\n",
+	    __func__,
+	    le32toh(mbn->mac_id),
+	    le32toh(mbn->consec_missed_beacons_since_last_rx),
+	    le32toh(mbn->consec_missed_beacons),
+	    le32toh(mbn->num_expected_beacons),
+	    le32toh(mbn->num_recvd_beacons));
+
 	missed = le32toh(mbn->consec_missed_beacons_since_last_rx);
 	if (missed > vap->iv_bmissthreshold) {
 		ieee80211_beacon_miss(ic);
 	}
-
 }
 
 static int
@@ -5491,6 +5501,9 @@ iwx_tx_fill_cmd(struct iwx_softc *sc, struct iwx_node *in,
 		/* for non-data, use the lowest supported rate */
 		ridx = min_ridx;
 		*flags |= IWX_TX_FLAGS_CMD_RATE;
+	} else if (ni->ni_flags & IEEE80211_NODE_VHT) {
+		/* TODO: VHT - the ridx / rate array doesn't have VHT rates yet */
+		ridx = iwx_min_basic_rate(ic);
 	} else if (ni->ni_flags & IEEE80211_NODE_HT) {
 		ridx = iwx_mcs2ridx[ieee80211_node_get_txrate_dot11rate(ni)
 		    & ~IEEE80211_RATE_MCS];
@@ -5622,6 +5635,8 @@ iwx_tx(struct iwx_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
 	struct mbuf *m1;
 	size_t txcmd_size;
 
+	IWX_ASSERT_LOCKED(sc);
+
 	wh = mtod(m, struct ieee80211_frame *);
 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
 	subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
@@ -7308,97 +7323,107 @@ iwx_rs_init(struct iwx_softc *sc, struct iwx_node *in)
 		return iwx_rs_init_v3(sc, in);
 }
 
-static void
-iwx_rs_update(struct iwx_softc *sc, struct iwx_tlc_update_notif *notif)
+
+/**
+ * @brief Turn the given TX rate control notification into an ieee80211_node_txrate
+ *
+ * This populates the given txrate node with the TX rate control notification.
+ *
+ * @param sc driver softc
+ * @param notif firmware notification
+ * @param ni ieee80211_node update
+ * @returns true if updated, false if not
+ */
+static bool
+iwx_rs_update_node_txrate(struct iwx_softc *sc,
+    const struct iwx_tlc_update_notif *notif, struct ieee80211_node *ni)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
-	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
-	struct ieee80211_node *ni = (void *)vap->iv_bss;
+	/* XXX TODO: create an inline function in if_iwxreg.h? */
+	static int cck_idx_to_rate[] = { 2, 4, 11, 22, 2, 2, 2, 2 };
+	static int ofdm_idx_to_rate[] = { 12, 18, 24, 36, 48, 72, 96, 108 };
 
-	struct ieee80211_rateset *rs = &ni->ni_rates;
 	uint32_t rate_n_flags;
-	uint8_t plcp, rval;
-	int i, cmd_ver, rate_n_flags_ver2 = 0;
-
-	if (notif->sta_id != IWX_STATION_ID ||
-	    (le32toh(notif->flags) & IWX_TLC_NOTIF_FLAG_RATE) == 0)
-		return;
+	uint32_t type;
 
+	/* Extract the rate and command version */
 	rate_n_flags = le32toh(notif->rate);
 
+	if (sc->sc_rate_n_flags_version != 2) {
+		net80211_ic_printf(ic,
+		    "%s: unsupported rate_n_flags version (%d)\n",
+		    __func__,
+		    sc->sc_rate_n_flags_version);
+		return (false);
+	}
+
 	if (sc->sc_debug & IWX_DEBUG_TXRATE)
 		print_ratenflags(__func__, __LINE__,
 		    rate_n_flags, sc->sc_rate_n_flags_version);
 
-	cmd_ver = iwx_lookup_notif_ver(sc, IWX_DATA_PATH_GROUP,
-	    IWX_TLC_MNG_UPDATE_NOTIF);
-	if (cmd_ver != IWX_FW_CMD_VER_UNKNOWN && cmd_ver >= 3)
-		rate_n_flags_ver2 = 1;
-
-	if (rate_n_flags_ver2) {
-		uint32_t mod_type = (rate_n_flags & IWX_RATE_MCS_MOD_TYPE_MSK);
-		if (mod_type == IWX_RATE_MCS_HT_MSK) {
-
-			ieee80211_node_set_txrate_dot11rate(ni,
-				IWX_RATE_HT_MCS_INDEX(rate_n_flags) |
-				IEEE80211_RATE_MCS);
-			IWX_DPRINTF(sc, IWX_DEBUG_TXRATE,
-			    "%s:%d new MCS: %d rate_n_flags: %x\n",
-			    __func__, __LINE__,
-			    ieee80211_node_get_txrate_dot11rate(ni) & ~IEEE80211_RATE_MCS,
-			    rate_n_flags);
-			return;
-		}
-	} else {
-		if (rate_n_flags & IWX_RATE_MCS_HT_MSK_V1) {
-			ieee80211_node_set_txrate_dot11rate(ni,
-			    rate_n_flags & (IWX_RATE_HT_MCS_RATE_CODE_MSK_V1 |
-			    IWX_RATE_HT_MCS_NSS_MSK_V1));
-
-			IWX_DPRINTF(sc, IWX_DEBUG_TXRATE,
-			    "%s:%d new MCS idx: %d rate_n_flags: %x\n",
-			    __func__, __LINE__,
-			    ieee80211_node_get_txrate_dot11rate(ni), rate_n_flags);
-			return;
-		}
+	type = (rate_n_flags & IWX_RATE_MCS_MOD_TYPE_MSK);
+	switch (type) {
+	case IWX_RATE_MCS_CCK_MSK:
+		ieee80211_node_set_txrate_dot11rate(ni,
+		    cck_idx_to_rate[rate_n_flags & IWX_RATE_LEGACY_RATE_MSK]);
+		return (true);
+	case IWX_RATE_MCS_LEGACY_OFDM_MSK:
+		ieee80211_node_set_txrate_dot11rate(ni,
+		    ofdm_idx_to_rate[rate_n_flags & IWX_RATE_LEGACY_RATE_MSK]);
+		return (true);
+	case IWX_RATE_MCS_HT_MSK:
+		/*
+		 * TODO: the current API doesn't include channel width
+		 * and other flags, so we can't accurately store them yet!
+		 *
+		 * channel width: (flags & IWX_RATE_MCS_CHAN_WIDTH_MSK)
+		 *    >> IWX_RATE_MCS_CHAN_WIDTH_POS)
+		 * LDPC: (flags & (1 << 16))
+		 */
+		ieee80211_node_set_txrate_ht_mcsrate(ni,
+		    IWX_RATE_HT_MCS_INDEX(rate_n_flags));
+		return (true);
+	case IWX_RATE_MCS_VHT_MSK:
+		/* TODO: same comment on channel width, etc above */
+		ieee80211_node_set_txrate_vht_rate(ni,
+		    IWX_RATE_VHT_MCS_CODE(rate_n_flags),
+		    IWX_RATE_VHT_MCS_NSS(rate_n_flags));
+		return (true);
+	default:
+		net80211_ic_printf(ic,
+		    "%s: unsupported chosen rate type in "
+		    "IWX_RATE_MCS_MOD_TYPE (%d)\n", __func__,
+		    type >> IWX_RATE_MCS_MOD_TYPE_POS);
+		return (false);
 	}
 
-	if (rate_n_flags_ver2) {
-		const struct ieee80211_rateset *rs;
-		uint32_t ridx = (rate_n_flags & IWX_RATE_LEGACY_RATE_MSK);
-		if (rate_n_flags & IWX_RATE_MCS_LEGACY_OFDM_MSK)
-			rs = &ieee80211_std_rateset_11a;
-		else
-			rs = &ieee80211_std_rateset_11b;
-		if (ridx < rs->rs_nrates)
-			rval = (rs->rs_rates[ridx] & IEEE80211_RATE_VAL);
-		else
-			rval = 0;
-	} else {
-		plcp = (rate_n_flags & IWX_RATE_LEGACY_RATE_MSK_V1);
+	/* Default: if we get here, we didn't successfully update anything */
+	return (false);
+}
 
-		rval = 0;
-		for (i = IWX_RATE_1M_INDEX; i < nitems(iwx_rates); i++) {
-			if (iwx_rates[i].plcp == plcp) {
-				rval = iwx_rates[i].rate;
-				break;
-			}
-		}
-	}
+/**
+ * @brief Process a firmware rate control update and update net80211.
+ *
+ * Since firmware is doing rate control, this just needs to update
+ * the txrate in the ieee80211_node entry.
+ */
+static void
+iwx_rs_update(struct iwx_softc *sc, struct iwx_tlc_update_notif *notif)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
+	/* XXX TODO: get a node ref! */
+	struct ieee80211_node *ni = (void *)vap->iv_bss;
 
-	if (rval) {
-		uint8_t rv;
-		for (i = 0; i < rs->rs_nrates; i++) {
-			rv = rs->rs_rates[i] & IEEE80211_RATE_VAL;
-			if (rv == rval) {
-				ieee80211_node_set_txrate_dot11rate(ni, i);
-				break;
-			}
-		}
-		IWX_DPRINTF(sc, IWX_DEBUG_TXRATE,
-		    "%s:%d new rate %d\n", __func__, __LINE__,
-		    ieee80211_node_get_txrate_dot11rate(ni));
-	}
+	/*
+	 * For now the iwx driver only supports a single vdev with a single
+	 * node; it doesn't yet support ibss/hostap/multiple vdevs.
+	 */
+	if (notif->sta_id != IWX_STATION_ID ||
+	    (le32toh(notif->flags) & IWX_TLC_NOTIF_FLAG_RATE) == 0)
+		return;
+
+	iwx_rs_update_node_txrate(sc, notif, ni);
 }
 
 static int
@@ -8526,6 +8551,8 @@ iwx_start(struct iwx_softc *sc)
         struct ieee80211_node *ni;
         struct mbuf *m;
 
+        IWX_ASSERT_LOCKED(sc);
+
         while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
                 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
                 if (iwx_tx(sc, m, ni) != 0) {
@@ -8985,10 +9012,10 @@ iwx_rx_pkt(struct iwx_softc *sc, struct iwx_rx_data *data, struct mbuf *ml)
 			break;
 
 		case IWX_MISSED_BEACONS_NOTIFICATION:
+			IWX_DPRINTF(sc, IWX_DEBUG_BEACON,
+			    "%s: IWX_MISSED_BEACONS_NOTIFICATION\n",
+			    __func__);
 			iwx_rx_bmiss(sc, pkt, data);
-			DPRINTF(("%s: IWX_MISSED_BEACONS_NOTIFICATION\n",
-			    __func__));
-			ieee80211_beacon_miss(ic);
 			break;
 
 		case IWX_MFUART_LOAD_NOTIFICATION:
diff --git a/sys/dev/iwx/if_iwxreg.h b/sys/dev/iwx/if_iwxreg.h
index 6755b93fa0ba..f3d1f078b48e 100644
--- a/sys/dev/iwx/if_iwxreg.h
+++ b/sys/dev/iwx/if_iwxreg.h
@@ -5176,6 +5176,10 @@ enum {
 #define IWX_RATE_HT_MCS_INDEX(r)	((((r) & IWX_RATE_MCS_NSS_MSK) >> 1) | \
 					 ((r) & IWX_RATE_HT_MCS_CODE_MSK))
 
+#define IWX_RATE_VHT_MCS_CODE(r)	((r) & IWX_RATE_HT_MCS_CODE_MSK)
+#define IWX_RATE_VHT_MCS_NSS(r)		\
+	    ((((r) & IWX_RATE_MCS_NSS_MSK) == 0) >> IWX_RATE_MCS_NSS_POS)
+
 /* Bits 7-5: reserved */
 
 /*
diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index 9e43a4c1909f..cde98cb62cef 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -240,6 +240,7 @@ struct pci_quirk {
 #define	PCI_QUIRK_DISABLE_MSIX	5 /* MSI-X doesn't work */
 #define	PCI_QUIRK_MSI_INTX_BUG	6 /* PCIM_CMD_INTxDIS disables MSI */
 #define	PCI_QUIRK_REALLOC_BAR	7 /* Can't allocate memory at the default address */
+#define	PCI_QUIRK_DISABLE_FLR	8 /* Function-Level Reset (FLR) not working. */
 	int	arg1;
 	int	arg2;
 };
@@ -319,6 +320,13 @@ static const struct pci_quirk pci_quirks[] = {
 	 * expected place.
 	 */
 	{ 0x98741002, PCI_QUIRK_REALLOC_BAR,	0, 	0 },
+
+	/*
+	 * With some MediaTek mt76 WiFi FLR does not work despite advertised.
+	 */
+	{ 0x061614c3, PCI_QUIRK_DISABLE_FLR,	0,	0 }, /* mt76 7922 */
+
+	/* end of table */
 	{ 0 }
 };
 
@@ -6740,6 +6748,8 @@ pcie_flr(device_t dev, u_int max_delay, bool force)
 
 	if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR))
 		return (false);
+	if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_FLR))
+		return (false);
 
 	/*
 	 * Disable busmastering to prevent generation of new
diff --git a/sys/dev/sound/pci/hda/hdaa.c b/sys/dev/sound/pci/hda/hdaa.c
index 1e486b01b168..5dbb5c4f4453 100644
--- a/sys/dev/sound/pci/hda/hdaa.c
+++ b/sys/dev/sound/pci/hda/hdaa.c
@@ -532,9 +532,11 @@ static void
 hdaa_presence_handler(struct hdaa_widget *w)
 {
 	struct hdaa_devinfo *devinfo = w->devinfo;
-	struct hdaa_audio_as *as;
+	struct hdaa_audio_as *as, *asp;
+	char buf[32];
 	uint32_t res;
-	int connected, old;
+	int connected, old, i;
+	bool active;
 
 	if (w->enable == 0 || w->type !=
 	    HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
@@ -552,13 +554,6 @@ hdaa_presence_handler(struct hdaa_widget *w)
 	if (connected == old)
 		return;
 	w->wclass.pin.connected = connected;
-	HDA_BOOTVERBOSE(
-		if (connected || old != 2) {
-			device_printf(devinfo->dev,
-			    "Pin sense: nid=%d sense=0x%08x (%sconnected)\n",
-			    w->nid, res, !connected ? "dis" : "");
-		}
-	);
 
 	as = &devinfo->as[w->bindas];
 	if (as->hpredir >= 0 && as->pins[15] == w->nid)
@@ -567,6 +562,38 @@ hdaa_presence_handler(struct hdaa_widget *w)
 		hdaa_autorecsrc_handler(as, w);
 	if (old != 2)
 		hdaa_channels_handler(as);
+
+	if (connected || old != 2) {
+		HDA_BOOTVERBOSE(
+			device_printf(devinfo->dev,
+			    "Pin sense: nid=%d sense=0x%08x (%sconnected)\n",
+			    w->nid, res, !connected ? "dis" : "");
+		);
+		if (as->hpredir >= 0)
+			return;
+		for (i = 0, active = false; i < devinfo->num_devs; i++) {
+			if (device_get_unit(devinfo->devs[i].dev) == snd_unit) {
+				active = true;
+				break;
+			}
+		}
+		/* Proceed only if we are currently using this codec. */
+		if (!active)
+			return;
+		for (i = 0; i < devinfo->ascnt; i++) {
+			asp = &devinfo->as[i];
+			if (!asp->enable)
+				continue;
+			if ((connected && asp->index == as->index) ||
+			    (!connected && asp->dir == as->dir)) {
+				snprintf(buf, sizeof(buf), "cdev=dsp%d",
+				    device_get_unit(asp->pdevinfo->dev));
+				devctl_notify("SND", "CONN",
+				    asp->dir == HDAA_CTL_IN ? "IN" : "OUT", buf);
+				break;
+			}
+		}
+	}
 }
 
 /*
@@ -6194,15 +6221,15 @@ hdaa_configure(device_t dev)
 	);
 	hdaa_patch_direct(devinfo);
 	HDA_BOOTHVERBOSE(
-		device_printf(dev, "Pin sense init...\n");
-	);
-	hdaa_sense_init(devinfo);
-	HDA_BOOTHVERBOSE(
 		device_printf(dev, "Creating PCM devices...\n");
 	);
 	hdaa_unlock(devinfo);
 	hdaa_create_pcms(devinfo);
 	hdaa_lock(devinfo);
+	HDA_BOOTHVERBOSE(
+		device_printf(dev, "Pin sense init...\n");
+	);
+	hdaa_sense_init(devinfo);
 
 	HDA_BOOTVERBOSE(
 		if (devinfo->quirks != 0) {
diff --git a/sys/dev/virtio/network/if_vtnet.c b/sys/dev/virtio/network/if_vtnet.c
index 634ba0de2d55..471c6b3714b2 100644
--- a/sys/dev/virtio/network/if_vtnet.c
+++ b/sys/dev/virtio/network/if_vtnet.c
@@ -281,7 +281,7 @@ static int vtnet_tso_disable = 0;
 SYSCTL_INT(_hw_vtnet, OID_AUTO, tso_disable, CTLFLAG_RDTUN,
     &vtnet_tso_disable, 0, "Disables TSO");
 
-static int vtnet_lro_disable = 0;
+static int vtnet_lro_disable = 1;
 SYSCTL_INT(_hw_vtnet, OID_AUTO, lro_disable, CTLFLAG_RDTUN,
     &vtnet_lro_disable, 0, "Disables hardware LRO");
 
diff --git a/sys/dev/vmware/vmxnet3/if_vmx.c b/sys/dev/vmware/vmxnet3/if_vmx.c
index 62b5f313a137..1a314ca6660e 100644
--- a/sys/dev/vmware/vmxnet3/if_vmx.c
+++ b/sys/dev/vmware/vmxnet3/if_vmx.c
@@ -2056,7 +2056,12 @@ vmxnet3_update_admin_status(if_ctx_t ctx)
 	struct vmxnet3_softc *sc;
 
 	sc = iflib_get_softc(ctx);
-	if (sc->vmx_ds->event != 0)
+	/*
+	 * iflib may invoke this routine before vmxnet3_attach_post() has
+	 * run, which is before the top level shared data area is
+	 * initialized and the device made aware of it.
+	 */
+	if (sc->vmx_ds != NULL && sc->vmx_ds->event != 0)
 		vmxnet3_evintr(sc);
 
 	vmxnet3_refresh_host_stats(sc);
diff --git a/sys/dev/vt/vt_core.c b/sys/dev/vt/vt_core.c
index b51ef6766de4..bcf67ddc9689 100644
--- a/sys/dev/vt/vt_core.c
+++ b/sys/dev/vt/vt_core.c
@@ -195,8 +195,8 @@ static void vt_update_static(void *);
 #ifndef SC_NO_CUTPASTE
 static void vt_mouse_paste(void);
 #endif
-static void vt_suspend_handler(void *priv);
-static void vt_resume_handler(void *priv);
+static void vt_suspend_handler(void *priv, enum power_stype stype);
+static void vt_resume_handler(void *priv, enum power_stype stype);
 
 SET_DECLARE(vt_drv_set, struct vt_driver);
 
@@ -3330,7 +3330,7 @@ vt_replace_backend(const struct vt_driver *drv, void *softc)
 }
 
 static void
-vt_suspend_handler(void *priv)
+vt_suspend_handler(void *priv, enum power_stype stype)
 {
 	struct vt_device *vd;
 
@@ -3341,7 +3341,7 @@ vt_suspend_handler(void *priv)
 }
 
 static void
-vt_resume_handler(void *priv)
+vt_resume_handler(void *priv, enum power_stype stype)
 {
 	struct vt_device *vd;
 
diff --git a/sys/dev/watchdog/watchdog.c b/sys/dev/watchdog/watchdog.c
index e1b2e08c3f10..c599db56bf95 100644
--- a/sys/dev/watchdog/watchdog.c
+++ b/sys/dev/watchdog/watchdog.c
@@ -204,6 +204,7 @@ wd_valid_act(int act)
 	return true;
 }
 
+#ifdef	COMPAT_FREEBSD14
 static int
 wd_ioctl_patpat(caddr_t data)
 {
@@ -223,6 +224,7 @@ wd_ioctl_patpat(caddr_t data)
 
 	return (wdog_kern_pat(u));
 }
+#endif
 
 static int
 wd_get_time_left(struct thread *td, time_t *remainp)
diff --git a/sys/dev/xen/control/control.c b/sys/dev/xen/control/control.c
index 123df4992894..2c61b48c0451 100644
--- a/sys/dev/xen/control/control.c
+++ b/sys/dev/xen/control/control.c
@@ -91,6 +91,7 @@
 #include <sys/smp.h>
 #include <sys/eventhandler.h>
 #include <sys/timetc.h>
+#include <sys/power.h>
 
 #include <geom/geom.h>
 
@@ -175,12 +176,12 @@ xctrl_suspend(void)
 	cpuset_t cpu_suspend_map;
 #endif
 
-	EVENTHANDLER_INVOKE(power_suspend_early);
+	EVENTHANDLER_INVOKE(power_suspend_early, POWER_STYPE_SUSPEND_TO_MEM);
 	xs_lock();
 	stop_all_proc();
 	xs_unlock();
 	suspend_all_fs();
-	EVENTHANDLER_INVOKE(power_suspend);
+	EVENTHANDLER_INVOKE(power_suspend, POWER_STYPE_SUSPEND_TO_MEM);
 
 #ifdef EARLY_AP_STARTUP
 	MPASS(mp_ncpus == 1 || smp_started);
@@ -297,7 +298,7 @@ xctrl_suspend(void)
 	resume_all_fs();
 	resume_all_proc();
 
-	EVENTHANDLER_INVOKE(power_resume);
+	EVENTHANDLER_INVOKE(power_resume, POWER_STYPE_SUSPEND_TO_MEM);
 
 	if (bootverbose)
 		printf("System resumed after suspension\n");
diff --git a/sys/fs/nullfs/null.h b/sys/fs/nullfs/null.h
index 0a93878c859f..ad3f7779e108 100644
--- a/sys/fs/nullfs/null.h
+++ b/sys/fs/nullfs/null.h
@@ -37,6 +37,9 @@
 
 #define	NULLM_CACHE	0x0001
 
+#include <sys/ck.h>
+#include <vm/uma.h>
+
 struct null_mount {
 	struct mount	*nullm_vfs;
 	struct vnode	*nullm_lowerrootvp;	/* Ref to lower root vnode */
@@ -50,7 +53,7 @@ struct null_mount {
  * A cache of vnode references
  */
 struct null_node {
-	LIST_ENTRY(null_node)	null_hash;	/* Hash list */
+	CK_SLIST_ENTRY(null_node) null_hash;	/* Hash list */
 	struct vnode	        *null_lowervp;	/* VREFed once */
 	struct vnode		*null_vnode;	/* Back pointer */
 	u_int			null_flags;
@@ -61,6 +64,7 @@ struct null_node {
 
 #define	MOUNTTONULLMOUNT(mp) ((struct null_mount *)((mp)->mnt_data))
 #define	VTONULL(vp) ((struct null_node *)(vp)->v_data)
+#define	VTONULL_SMR(vp) ((struct null_node *)vn_load_v_data_smr(vp))
 #define	NULLTOV(xp) ((xp)->null_vnode)
 
 int nullfs_init(struct vfsconf *vfsp);
@@ -79,9 +83,7 @@ struct vnode *null_checkvp(struct vnode *vp, char *fil, int lno);
 
 extern struct vop_vector null_vnodeops;
 
-#ifdef MALLOC_DECLARE
-MALLOC_DECLARE(M_NULLFSNODE);
-#endif
+extern uma_zone_t null_node_zone;
 
 #ifdef NULLFS_DEBUG
 #define NULLFSDEBUG(format, args...) printf(format ,## args)
diff --git a/sys/fs/nullfs/null_subr.c b/sys/fs/nullfs/null_subr.c
index 053614b6910d..d7f847d449d0 100644
--- a/sys/fs/nullfs/null_subr.c
+++ b/sys/fs/nullfs/null_subr.c
@@ -36,14 +36,19 @@
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/lock.h>
-#include <sys/rwlock.h>
 #include <sys/malloc.h>
 #include <sys/mount.h>
 #include <sys/proc.h>
+#include <sys/rwlock.h>
+#include <sys/smr.h>
 #include <sys/vnode.h>
 
 #include <fs/nullfs/null.h>
 
+#include <vm/uma.h>
+
+VFS_SMR_DECLARE;
+
 /*
  * Null layer cache:
  * Each cache entry holds a reference to the lower vnode
@@ -54,12 +59,12 @@
 
 #define	NULL_NHASH(vp) (&null_node_hashtbl[vfs_hash_index(vp) & null_hash_mask])
 
-static LIST_HEAD(null_node_hashhead, null_node) *null_node_hashtbl;
+static CK_SLIST_HEAD(null_node_hashhead, null_node) *null_node_hashtbl;
 static struct rwlock null_hash_lock;
 static u_long null_hash_mask;
 
 static MALLOC_DEFINE(M_NULLFSHASH, "nullfs_hash", "NULLFS hash table");
-MALLOC_DEFINE(M_NULLFSNODE, "nullfs_node", "NULLFS vnode private part");
+uma_zone_t __read_mostly null_node_zone;
 
 static void null_hashins(struct mount *, struct null_node *);
 
@@ -73,6 +78,10 @@ nullfs_init(struct vfsconf *vfsp)
 	null_node_hashtbl = hashinit(desiredvnodes, M_NULLFSHASH,
 	    &null_hash_mask);
 	rw_init(&null_hash_lock, "nullhs");
+	null_node_zone = uma_zcreate("nullfs node", sizeof(struct null_node),
+	    NULL, NULL, NULL, NULL, 0, UMA_ZONE_ZINIT);
+	VFS_SMR_ZONE_SET(null_node_zone);
+
 	return (0);
 }
 
@@ -80,6 +89,7 @@ int
 nullfs_uninit(struct vfsconf *vfsp)
 {
 
+	uma_zdestroy(null_node_zone);
 	rw_destroy(&null_hash_lock);
 	hashdestroy(null_node_hashtbl, M_NULLFSHASH, null_hash_mask);
 	return (0);
@@ -96,7 +106,7 @@ null_hashget_locked(struct mount *mp, struct vnode *lowervp)
 	struct null_node *a;
 	struct vnode *vp;
 
-	ASSERT_VOP_LOCKED(lowervp, "null_hashget");
+	ASSERT_VOP_LOCKED(lowervp, __func__);
 	rw_assert(&null_hash_lock, RA_LOCKED);
 
 	/*
@@ -106,18 +116,21 @@ null_hashget_locked(struct mount *mp, struct vnode *lowervp)
 	 * reference count (but NOT the lower vnode's VREF counter).
 	 */
 	hd = NULL_NHASH(lowervp);
-	LIST_FOREACH(a, hd, null_hash) {
-		if (a->null_lowervp == lowervp && NULLTOV(a)->v_mount == mp) {
-			/*
-			 * Since we have the lower node locked the nullfs
-			 * node can not be in the process of recycling.  If
-			 * it had been recycled before we grabed the lower
-			 * lock it would not have been found on the hash.
-			 */
-			vp = NULLTOV(a);
-			vref(vp);
-			return (vp);
-		}
+	CK_SLIST_FOREACH(a, hd, null_hash) {
+		if (a->null_lowervp != lowervp)
+			continue;
+		/*
+		 * Since we have the lower node locked the nullfs
+		 * node can not be in the process of recycling.  If
+		 * it had been recycled before we grabed the lower
+		 * lock it would not have been found on the hash.
+		 */
+		vp = NULLTOV(a);
+		VNPASS(!VN_IS_DOOMED(vp), vp);
+		if (vp->v_mount != mp)
+			continue;
+		vref(vp);
+		return (vp);
 	}
 	return (NULL);
 }
@@ -126,17 +139,34 @@ struct vnode *
 null_hashget(struct mount *mp, struct vnode *lowervp)
 {
 	struct null_node_hashhead *hd;
+	struct null_node *a;
 	struct vnode *vp;
+	enum vgetstate vs;
 
-	hd = NULL_NHASH(lowervp);
-	if (LIST_EMPTY(hd))
-		return (NULL);
-
-	rw_rlock(&null_hash_lock);
-	vp = null_hashget_locked(mp, lowervp);
-	rw_runlock(&null_hash_lock);
+	ASSERT_VOP_LOCKED(lowervp, __func__);
+	rw_assert(&null_hash_lock, RA_UNLOCKED);
 
-	return (vp);
+	vfs_smr_enter();
+	hd = NULL_NHASH(lowervp);
+	CK_SLIST_FOREACH(a, hd, null_hash) {
+		if (a->null_lowervp != lowervp)
+			continue;
+		/*
+		 * See null_hashget_locked as to why the nullfs vnode can't be
+		 * doomed here.
+		 */
+		vp = NULLTOV(a);
+		VNPASS(!VN_IS_DOOMED(vp), vp);
+		if (vp->v_mount != mp)
+			continue;
+		vs = vget_prep_smr(vp);
+		vfs_smr_exit();
+		VNPASS(vs != VGET_NONE, vp);
+		vget_finish_ref(vp, vs);
+		return (vp);
+	}
+	vfs_smr_exit();
+	return (NULL);
 }
 
 static void
@@ -151,7 +181,7 @@ null_hashins(struct mount *mp, struct null_node *xp)
 
 	hd = NULL_NHASH(xp->null_lowervp);
 #ifdef INVARIANTS
-	LIST_FOREACH(oxp, hd, null_hash) {
+	CK_SLIST_FOREACH(oxp, hd, null_hash) {
 		if (oxp->null_lowervp == xp->null_lowervp &&
 		    NULLTOV(oxp)->v_mount == mp) {
 			VNASSERT(0, NULLTOV(oxp),
@@ -159,7 +189,7 @@ null_hashins(struct mount *mp, struct null_node *xp)
 		}
 	}
 #endif
-	LIST_INSERT_HEAD(hd, xp, null_hash);
+	CK_SLIST_INSERT_HEAD(hd, xp, null_hash);
 }
 
 static void
@@ -174,7 +204,7 @@ null_destroy_proto(struct vnode *vp, void *xp)
 	VI_UNLOCK(vp);
 	vgone(vp);
 	vput(vp);
-	free(xp, M_NULLFSNODE);
+	uma_zfree_smr(null_node_zone, xp);
 }
 
 /*
@@ -208,12 +238,12 @@ null_nodeget(struct mount *mp, struct vnode *lowervp, struct vnode **vpp)
 	 * Note that duplicate can only appear in hash if the lowervp is
 	 * locked LK_SHARED.
 	 */
-	xp = malloc(sizeof(struct null_node), M_NULLFSNODE, M_WAITOK);
+	xp = uma_zalloc_smr(null_node_zone, M_WAITOK);
 
 	error = getnewvnode("nullfs", mp, &null_vnodeops, &vp);
 	if (error) {
 		vput(lowervp);
-		free(xp, M_NULLFSNODE);
+		uma_zfree_smr(null_node_zone, xp);
 		return (error);
 	}
 
@@ -261,8 +291,8 @@ null_nodeget(struct mount *mp, struct vnode *lowervp, struct vnode **vpp)
 		return (error);
 	}
 
-	null_hashins(mp, xp);
 	vn_set_state(vp, VSTATE_CONSTRUCTED);
+	null_hashins(mp, xp);
 	rw_wunlock(&null_hash_lock);
 	*vpp = vp;
 
@@ -275,9 +305,11 @@ null_nodeget(struct mount *mp, struct vnode *lowervp, struct vnode **vpp)
 void
 null_hashrem(struct null_node *xp)
 {
+	struct null_node_hashhead *hd;
 
+	hd = NULL_NHASH(xp->null_lowervp);
 	rw_wlock(&null_hash_lock);
-	LIST_REMOVE(xp, null_hash);
+	CK_SLIST_REMOVE(hd, xp, null_node, null_hash);
 	rw_wunlock(&null_hash_lock);
 }
 
diff --git a/sys/fs/nullfs/null_vnops.c b/sys/fs/nullfs/null_vnops.c
index e9d598014a2f..ec8a6b10b13f 100644
--- a/sys/fs/nullfs/null_vnops.c
+++ b/sys/fs/nullfs/null_vnops.c
@@ -174,6 +174,8 @@
 #include <sys/mount.h>
 #include <sys/mutex.h>
 #include <sys/namei.h>
+#include <sys/proc.h>
+#include <sys/smr.h>
 #include <sys/sysctl.h>
 #include <sys/vnode.h>
 #include <sys/stat.h>
@@ -185,6 +187,8 @@
 #include <vm/vm_object.h>
 #include <vm/vnode_pager.h>
 
+VFS_SMR_DECLARE;
+
 static int null_bug_bypass = 0;   /* for debugging: enables bypass printf'ing */
 SYSCTL_INT(_debug, OID_AUTO, nullfs_bug_bypass, CTLFLAG_RW, 
 	&null_bug_bypass, 0, "");
@@ -768,83 +772,111 @@ null_rmdir(struct vop_rmdir_args *ap)
 }
 
 /*
- * We need to process our own vnode lock and then clear the
- * interlock flag as it applies only to our vnode, not the
- * vnodes below us on the stack.
+ * We need to process our own vnode lock and then clear the interlock flag as
+ * it applies only to our vnode, not the vnodes below us on the stack.
+ *
+ * We have to hold the vnode here to solve a potential reclaim race.  If we're
+ * forcibly vgone'd while we still have refs, a thread could be sleeping inside
+ * the lowervp's vop_lock routine.  When we vgone we will drop our last ref to
+ * the lowervp, which would allow it to be reclaimed.  The lowervp could then
+ * be recycled, in which case it is not legal to be sleeping in its VOP.  We
+ * prevent it from being recycled by holding the vnode here.
  */
+static struct vnode *
+null_lock_prep_with_smr(struct vop_lock1_args *ap)
+{
+	struct null_node *nn;
+	struct vnode *lvp;
+
+	lvp = NULL;
+
+	vfs_smr_enter();
+
+	nn = VTONULL_SMR(ap->a_vp);
+	if (__predict_true(nn != NULL)) {
+		lvp = nn->null_lowervp;
+		if (lvp != NULL && !vhold_smr(lvp))
+			lvp = NULL;
+	}
+
+	vfs_smr_exit();
+	return (lvp);
+}
+
+static struct vnode *
+null_lock_prep_with_interlock(struct vop_lock1_args *ap)
+{
+	struct null_node *nn;
+	struct vnode *lvp;
+
+	ASSERT_VI_LOCKED(ap->a_vp, __func__);
+
+	ap->a_flags &= ~LK_INTERLOCK;
+
+	lvp = NULL;
+
+	nn = VTONULL(ap->a_vp);
+	if (__predict_true(nn != NULL)) {
+		lvp = nn->null_lowervp;
+		if (lvp != NULL)
+			vholdnz(lvp);
+	}
+	VI_UNLOCK(ap->a_vp);
+	return (lvp);
+}
+
 static int
 null_lock(struct vop_lock1_args *ap)
 {
-	struct vnode *vp = ap->a_vp;
-	int flags;
-	struct null_node *nn;
 	struct vnode *lvp;
-	int error;
+	int error, flags;
 
-	if ((ap->a_flags & LK_INTERLOCK) == 0)
-		VI_LOCK(vp);
-	else
-		ap->a_flags &= ~LK_INTERLOCK;
-	flags = ap->a_flags;
-	nn = VTONULL(vp);
+	if (__predict_true((ap->a_flags & LK_INTERLOCK) == 0)) {
+		lvp = null_lock_prep_with_smr(ap);
+		if (__predict_false(lvp == NULL)) {
+			VI_LOCK(ap->a_vp);
+			lvp = null_lock_prep_with_interlock(ap);
+		}
+	} else {
+		lvp = null_lock_prep_with_interlock(ap);
+	}
+
+	ASSERT_VI_UNLOCKED(ap->a_vp, __func__);
+
+	if (__predict_false(lvp == NULL))
+		return (vop_stdlock(ap));
+
+	VNPASS(lvp->v_holdcnt > 0, lvp);
+	error = VOP_LOCK(lvp, ap->a_flags);
 	/*
-	 * If we're still active we must ask the lower layer to
-	 * lock as ffs has special lock considerations in its
-	 * vop lock.
+	 * We might have slept to get the lock and someone might have
+	 * clean our vnode already, switching vnode lock from one in
+	 * lowervp to v_lock in our own vnode structure.  Handle this
+	 * case by reacquiring correct lock in requested mode.
 	 */
-	if (nn != NULL && (lvp = NULLVPTOLOWERVP(vp)) != NULL) {
-		/*
-		 * We have to hold the vnode here to solve a potential
-		 * reclaim race.  If we're forcibly vgone'd while we
-		 * still have refs, a thread could be sleeping inside
-		 * the lowervp's vop_lock routine.  When we vgone we will
-		 * drop our last ref to the lowervp, which would allow it
-		 * to be reclaimed.  The lowervp could then be recycled,
-		 * in which case it is not legal to be sleeping in its VOP.
-		 * We prevent it from being recycled by holding the vnode
-		 * here.
-		 */
-		vholdnz(lvp);
-		VI_UNLOCK(vp);
-		error = VOP_LOCK(lvp, flags);
-
-		/*
-		 * We might have slept to get the lock and someone might have
-		 * clean our vnode already, switching vnode lock from one in
-		 * lowervp to v_lock in our own vnode structure.  Handle this
-		 * case by reacquiring correct lock in requested mode.
-		 */
-		if (VTONULL(vp) == NULL && error == 0) {
-			ap->a_flags &= ~LK_TYPE_MASK;
-			switch (flags & LK_TYPE_MASK) {
-			case LK_SHARED:
-				ap->a_flags |= LK_SHARED;
-				break;
-			case LK_UPGRADE:
-			case LK_EXCLUSIVE:
-				ap->a_flags |= LK_EXCLUSIVE;
-				break;
-			default:
-				panic("Unsupported lock request %d\n",
-				    ap->a_flags);
-			}
-			VOP_UNLOCK(lvp);
-			error = vop_stdlock(ap);
+	if (VTONULL(ap->a_vp) == NULL && error == 0) {
+		VOP_UNLOCK(lvp);
+
+		flags = ap->a_flags;
+		ap->a_flags &= ~LK_TYPE_MASK;
+		switch (flags & LK_TYPE_MASK) {
+		case LK_SHARED:
+			ap->a_flags |= LK_SHARED;
+			break;
+		case LK_UPGRADE:
+		case LK_EXCLUSIVE:
+			ap->a_flags |= LK_EXCLUSIVE;
+			break;
+		default:
+			panic("Unsupported lock request %d\n",
+			    flags);
 		}
-		vdrop(lvp);
-	} else {
-		VI_UNLOCK(vp);
 		error = vop_stdlock(ap);
 	}
-
+	vdrop(lvp);
 	return (error);
 }
 
-/*
- * We need to process our own vnode unlock and then clear the
- * interlock flag as it applies only to our vnode, not the
- * vnodes below us on the stack.
- */
 static int
 null_unlock(struct vop_unlock_args *ap)
 {
@@ -853,11 +885,20 @@ null_unlock(struct vop_unlock_args *ap)
 	struct vnode *lvp;
 	int error;
 
+	/*
+	 * Contrary to null_lock, we don't need to hold the vnode around
+	 * unlock.
+	 *
+	 * We hold the lock, which means we can't be racing against vgone.
+	 *
+	 * At the same time VOP_UNLOCK promises to not touch anything after
+	 * it finishes unlock, just like we don't.
+	 *
+	 * vop_stdunlock for a doomed vnode matches doomed locking in null_lock.
+	 */
 	nn = VTONULL(vp);
 	if (nn != NULL && (lvp = NULLVPTOLOWERVP(vp)) != NULL) {
-		vholdnz(lvp);
 		error = VOP_UNLOCK(lvp);
-		vdrop(lvp);
 	} else {
 		error = vop_stdunlock(ap);
 	}
@@ -961,7 +1002,7 @@ null_reclaim(struct vop_reclaim_args *ap)
 		vunref(lowervp);
 	else
 		vput(lowervp);
-	free(xp, M_NULLFSNODE);
+	uma_zfree_smr(null_node_zone, xp);
 
 	return (0);
 }
diff --git a/sys/i386/acpica/acpi_wakeup.c b/sys/i386/acpica/acpi_wakeup.c
index 2d60d5e037a0..96be64de017b 100644
--- a/sys/i386/acpica/acpi_wakeup.c
+++ b/sys/i386/acpica/acpi_wakeup.c
@@ -84,7 +84,7 @@ static cpuset_t		suspcpus;
 static struct susppcb	**susppcbs;
 #endif
 
-static void		acpi_stop_beep(void *);
+static void		acpi_stop_beep(void *, enum power_stype);
 
 #ifdef SMP
 static int		acpi_wakeup_ap(struct acpi_softc *, int);
@@ -100,7 +100,7 @@ static void		acpi_wakeup_cpus(struct acpi_softc *);
 } while (0)
 
 static void
-acpi_stop_beep(void *arg)
+acpi_stop_beep(void *arg, enum power_stype stype)
 {
 
 	if (acpi_resume_beep != 0)
diff --git a/sys/isa/isa_common.c b/sys/isa/isa_common.c
index 8e4064af1455..1a6df7bf6046 100644
--- a/sys/isa/isa_common.c
+++ b/sys/isa/isa_common.c
@@ -1114,7 +1114,7 @@ isab_attach(device_t dev)
 {
 	device_t child;
 
-	child = device_add_child(dev, "isa", 0);
+	child = device_add_child(dev, "isa", DEVICE_UNIT_ANY);
 	if (child == NULL)
 		return (ENXIO);
 	bus_attach_children(dev);
diff --git a/sys/kern/kern_exit.c b/sys/kern/kern_exit.c
index a32b5a1b3354..ab8ed32ad189 100644
--- a/sys/kern/kern_exit.c
+++ b/sys/kern/kern_exit.c
@@ -127,6 +127,27 @@ proc_realparent(struct proc *child)
 	return (parent);
 }
 
+static void
+reaper_clear(struct proc *p, struct proc *rp)
+{
+	struct proc *p1;
+	bool clear;
+
+	sx_assert(&proctree_lock, SX_XLOCKED);
+	LIST_REMOVE(p, p_reapsibling);
+	if (p->p_reapsubtree == 1)
+		return;
+	clear = true;
+	LIST_FOREACH(p1, &rp->p_reaplist, p_reapsibling) {
+		if (p1->p_reapsubtree == p->p_reapsubtree) {
+			clear = false;
+			break;
+		}
+	}
+	if (clear)
+		proc_id_clear(PROC_ID_REAP, p->p_reapsubtree);
+}
+
 void
 reaper_abandon_children(struct proc *p, bool exiting)
 {
@@ -138,7 +159,7 @@ reaper_abandon_children(struct proc *p, bool exiting)
 		return;
 	p1 = p->p_reaper;
 	LIST_FOREACH_SAFE(p2, &p->p_reaplist, p_reapsibling, ptmp) {
-		LIST_REMOVE(p2, p_reapsibling);
+		reaper_clear(p2, p);
 		p2->p_reaper = p1;
 		p2->p_reapsubtree = p->p_reapsubtree;
 		LIST_INSERT_HEAD(&p1->p_reaplist, p2, p_reapsibling);
@@ -152,27 +173,6 @@ reaper_abandon_children(struct proc *p, bool exiting)
 	p->p_treeflag &= ~P_TREE_REAPER;
 }
 
-static void
-reaper_clear(struct proc *p)
-{
-	struct proc *p1;
-	bool clear;
-
-	sx_assert(&proctree_lock, SX_LOCKED);
-	LIST_REMOVE(p, p_reapsibling);
-	if (p->p_reapsubtree == 1)
-		return;
-	clear = true;
-	LIST_FOREACH(p1, &p->p_reaper->p_reaplist, p_reapsibling) {
-		if (p1->p_reapsubtree == p->p_reapsubtree) {
-			clear = false;
-			break;
-		}
-	}
-	if (clear)
-		proc_id_clear(PROC_ID_REAP, p->p_reapsubtree);
-}
-
 void
 proc_clear_orphan(struct proc *p)
 {
@@ -972,7 +972,7 @@ proc_reap(struct thread *td, struct proc *p, int *status, int options)
 	sx_xunlock(PIDHASHLOCK(p->p_pid));
 	LIST_REMOVE(p, p_sibling);
 	reaper_abandon_children(p, true);
-	reaper_clear(p);
+	reaper_clear(p, p->p_reaper);
 	PROC_LOCK(p);
 	proc_clear_orphan(p);
 	PROC_UNLOCK(p);
diff --git a/sys/kern/kern_lock.c b/sys/kern/kern_lock.c
index 31bff6d2c1aa..76f68677e292 100644
--- a/sys/kern/kern_lock.c
+++ b/sys/kern/kern_lock.c
@@ -1780,9 +1780,11 @@ lockmgr_chain(struct thread *td, struct thread **ownerp)
 
 	lk = td->td_wchan;
 
-	if (LOCK_CLASS(&lk->lock_object) != &lock_class_lockmgr)
+	if (!TD_ON_SLEEPQ(td) || sleepq_type(td->td_wchan) != SLEEPQ_LK ||
+	    LOCK_CLASS(&lk->lock_object) != &lock_class_lockmgr)
 		return (0);
-	db_printf("blocked on lockmgr %s", lk->lock_object.lo_name);
+	db_printf("blocked on lock %p (%s) \"%s\" ", &lk->lock_object,
+	    lock_class_lockmgr.lc_name, lk->lock_object.lo_name);
 	if (lk->lk_lock & LK_SHARE)
 		db_printf("SHARED (count %ju)\n",
 		    (uintmax_t)LK_SHARERS(lk->lk_lock));
diff --git a/sys/kern/kern_mutex.c b/sys/kern/kern_mutex.c
index 8b5908f5219a..d67c70984528 100644
--- a/sys/kern/kern_mutex.c
+++ b/sys/kern/kern_mutex.c
@@ -503,8 +503,8 @@ _mtx_trylock_flags_(volatile uintptr_t *c, int opts, const char *file, int line)
 /*
  * __mtx_lock_sleep: the tougher part of acquiring an MTX_DEF lock.
  *
- * We call this if the lock is either contested (i.e. we need to go to
- * sleep waiting for it), or if we need to recurse on it.
+ * We get here if lock profiling is enabled, the lock is already held by
+ * someone else or we are recursing on it.
  */
 #if LOCK_DEBUG > 0
 void
@@ -660,13 +660,8 @@ retry_turnstile:
 		}
 #endif
 
-		/*
-		 * If the mutex isn't already contested and a failure occurs
-		 * setting the contested bit, the mutex was either released
-		 * or the state of the MTX_RECURSED bit changed.
-		 */
-		if ((v & MTX_CONTESTED) == 0 &&
-		    !atomic_fcmpset_ptr(&m->mtx_lock, &v, v | MTX_CONTESTED)) {
+		if ((v & MTX_WAITERS) == 0 &&
+		    !atomic_fcmpset_ptr(&m->mtx_lock, &v, v | MTX_WAITERS)) {
 			goto retry_turnstile;
 		}
 
@@ -869,7 +864,7 @@ _thread_lock(struct thread *td)
 		WITNESS_LOCK(&m->lock_object, LOP_EXCLUSIVE, file, line);
 		return;
 	}
-	_mtx_release_lock_quick(m);
+	atomic_store_rel_ptr(&m->mtx_lock, MTX_UNOWNED);
 slowpath_unlocked:
 	spinlock_exit();
 slowpath_noirq:
@@ -959,7 +954,7 @@ retry:
 		}
 		if (m == td->td_lock)
 			break;
-		_mtx_release_lock_quick(m);
+		atomic_store_rel_ptr(&m->mtx_lock, MTX_UNOWNED);
 	}
 	LOCK_LOG_LOCK("LOCK", &m->lock_object, opts, m->mtx_recurse, file,
 	    line);
@@ -1029,8 +1024,8 @@ thread_lock_set(struct thread *td, struct mtx *new)
 /*
  * __mtx_unlock_sleep: the tougher part of releasing an MTX_DEF lock.
  *
- * We are only called here if the lock is recursed, contested (i.e. we
- * need to wake up a blocked thread) or lockstat probe is active.
+ * We get here if lock profiling is enabled, the lock is already held by
+ * someone else or we are recursing on it.
  */
 #if LOCK_DEBUG > 0
 void
@@ -1071,7 +1066,7 @@ __mtx_unlock_sleep(volatile uintptr_t *c, uintptr_t v)
 	 * can be removed from the hash list if it is empty.
 	 */
 	turnstile_chain_lock(&m->lock_object);
-	_mtx_release_lock_quick(m);
+	atomic_store_rel_ptr(&m->mtx_lock, MTX_UNOWNED);
 	ts = turnstile_lookup(&m->lock_object);
 	MPASS(ts != NULL);
 	if (LOCK_LOG_TEST(&m->lock_object, opts))
@@ -1207,7 +1202,7 @@ _mtx_destroy(volatile uintptr_t *c)
 	if (!mtx_owned(m))
 		MPASS(mtx_unowned(m));
 	else {
-		MPASS((m->mtx_lock & (MTX_RECURSED|MTX_CONTESTED)) == 0);
+		MPASS((m->mtx_lock & (MTX_RECURSED|MTX_WAITERS)) == 0);
 
 		/* Perform the non-mtx related part of mtx_unlock_spin(). */
 		if (LOCK_CLASS(&m->lock_object) == &lock_class_mtx_spin) {
@@ -1359,8 +1354,8 @@ db_show_mtx(const struct lock_object *lock)
 		db_printf("DESTROYED");
 	else {
 		db_printf("OWNED");
-		if (m->mtx_lock & MTX_CONTESTED)
-			db_printf(", CONTESTED");
+		if (m->mtx_lock & MTX_WAITERS)
+			db_printf(", WAITERS");
 		if (m->mtx_lock & MTX_RECURSED)
 			db_printf(", RECURSED");
 	}
diff --git a/sys/kern/kern_sx.c b/sys/kern/kern_sx.c
index c005e112d3b9..249faf5b1ec4 100644
--- a/sys/kern/kern_sx.c
+++ b/sys/kern/kern_sx.c
@@ -1539,16 +1539,19 @@ sx_chain(struct thread *td, struct thread **ownerp)
 
 	/*
 	 * Check to see if this thread is blocked on an sx lock.
-	 * First, we check the lock class.  If that is ok, then we
-	 * compare the lock name against the wait message.
+	 * The thread should be on a sleep queue with type SLEEPQ_SX, the
+	 * purported lock should have the lock class index of sx, and the lock
+	 * name should match the wait message.
 	 */
 	sx = td->td_wchan;
-	if (LOCK_CLASS(&sx->lock_object) != &lock_class_sx ||
+	if (!TD_ON_SLEEPQ(td) || sleepq_type(td->td_wchan) != SLEEPQ_SX ||
+	    LOCK_CLASS(&sx->lock_object) != &lock_class_sx ||
 	    sx->lock_object.lo_name != td->td_wmesg)
 		return (0);
 
 	/* We think we have an sx lock, so output some details. */
-	db_printf("blocked on sx \"%s\" ", td->td_wmesg);
+	db_printf("blocked on lock %p (%s) \"%s\" ", &sx->lock_object,
+	    lock_class_sx.lc_name, td->td_wmesg);
 	*ownerp = sx_xholder(sx);
 	if (sx->sx_lock & SX_LOCK_SHARED)
 		db_printf("SLOCK (count %ju)\n",
diff --git a/sys/kern/link_elf.c b/sys/kern/link_elf.c
index bbebadc4c395..ebd203858b66 100644
--- a/sys/kern/link_elf.c
+++ b/sys/kern/link_elf.c
@@ -518,9 +518,15 @@ link_elf_init(void* arg)
 	(void)link_elf_link_common_finish(linker_kernel_file);
 	linker_kernel_file->flags |= LINKER_FILE_LINKED;
 	TAILQ_INIT(&set_pcpu_list);
+	ef->pcpu_start = DPCPU_START;
+	ef->pcpu_stop = DPCPU_STOP;
+	ef->pcpu_base = DPCPU_START;
 #ifdef VIMAGE
 	TAILQ_INIT(&set_vnet_list);
 	vnet_save_init((void *)VNET_START, VNET_STOP - VNET_START);
+	ef->vnet_start = VNET_START;
+	ef->vnet_stop = VNET_STOP;
+	ef->vnet_base = VNET_START;
 #endif
 }
 
diff --git a/sys/kern/link_elf_obj.c b/sys/kern/link_elf_obj.c
index 151aab96f9be..a3a53a39bfd6 100644
--- a/sys/kern/link_elf_obj.c
+++ b/sys/kern/link_elf_obj.c
@@ -70,6 +70,7 @@
 
 typedef struct {
 	void		*addr;
+	void		*origaddr; /* Used by debuggers. */
 	Elf_Off		size;
 	int		flags;	/* Section flags. */
 	int		sec;	/* Original section number. */
@@ -492,7 +493,8 @@ link_elf_link_preload(linker_class_t cls, const char *filename,
 		case SHT_FINI_ARRAY:
 			if (shdr[i].sh_addr == 0)
 				break;
-			ef->progtab[pb].addr = (void *)shdr[i].sh_addr;
+			ef->progtab[pb].addr = ef->progtab[pb].origaddr =
+			    (void *)shdr[i].sh_addr;
 			if (shdr[i].sh_type == SHT_PROGBITS)
 				ef->progtab[pb].name = "<<PROGBITS>>";
 #ifdef __amd64__
@@ -1088,6 +1090,8 @@ link_elf_load_file(linker_class_t cls, const char *filename,
 				ef->progtab[pb].name = "<<NOBITS>>";
 			if (ef->progtab[pb].name != NULL && 
 			    !strcmp(ef->progtab[pb].name, DPCPU_SETNAME)) {
+				ef->progtab[pb].origaddr =
+				    (void *)(uintptr_t)mapbase;
 				ef->progtab[pb].addr =
 				    dpcpu_alloc(shdr[i].sh_size);
 				if (ef->progtab[pb].addr == NULL) {
@@ -1101,6 +1105,8 @@ link_elf_load_file(linker_class_t cls, const char *filename,
 #ifdef VIMAGE
 			else if (ef->progtab[pb].name != NULL &&
 			    !strcmp(ef->progtab[pb].name, VNET_SETNAME)) {
+				ef->progtab[pb].origaddr =
+				    (void *)(uintptr_t)mapbase;
 				ef->progtab[pb].addr =
 				    vnet_data_alloc(shdr[i].sh_size);
 				if (ef->progtab[pb].addr == NULL) {
diff --git a/sys/kern/sys_generic.c b/sys/kern/sys_generic.c
index 5606b36f772f..7d666da9f88b 100644
--- a/sys/kern/sys_generic.c
+++ b/sys/kern/sys_generic.c
@@ -729,7 +729,7 @@ kern_ioctl(struct thread *td, int fd, u_long com, caddr_t data)
 {
 	struct file *fp;
 	struct filedesc *fdp;
-	int error, tmp, locked;
+	int error, f_flag, tmp, locked;
 
 	AUDIT_ARG_FD(fd);
 	AUDIT_ARG_CMD(com);
@@ -782,30 +782,36 @@ kern_ioctl(struct thread *td, int fd, u_long com, caddr_t data)
 		goto out;
 	}
 
+	f_flag = 0;
 	switch (com) {
 	case FIONCLEX:
 		fdp->fd_ofiles[fd].fde_flags &= ~UF_EXCLOSE;
-		goto out;
+		break;
 	case FIOCLEX:
 		fdp->fd_ofiles[fd].fde_flags |= UF_EXCLOSE;
-		goto out;
-	case FIONBIO:
-		if ((tmp = *(int *)data))
-			atomic_set_int(&fp->f_flag, FNONBLOCK);
-		else
-			atomic_clear_int(&fp->f_flag, FNONBLOCK);
-		data = (void *)&tmp;
 		break;
+	case FIONBIO:
 	case FIOASYNC:
-		if ((tmp = *(int *)data))
-			atomic_set_int(&fp->f_flag, FASYNC);
-		else
-			atomic_clear_int(&fp->f_flag, FASYNC);
-		data = (void *)&tmp;
+		f_flag = com == FIONBIO ? FNONBLOCK : FASYNC;
+		tmp = *(int *)data;
+		fsetfl_lock(fp);
+		if (((fp->f_flag & f_flag) != 0) != (tmp != 0)) {
+			error = fo_ioctl(fp, com, (void *)&tmp, td->td_ucred,
+			    td);
+			if (error == 0) {
+				if (tmp != 0)
+					atomic_set_int(&fp->f_flag, f_flag);
+				else
+					atomic_clear_int(&fp->f_flag, f_flag);
+			}
+		}
+		fsetfl_unlock(fp);
+		break;
+	default:
+		error = fo_ioctl(fp, com, data, td->td_ucred, td);
 		break;
 	}
 
-	error = fo_ioctl(fp, com, data, td->td_ucred, td);
 out:
 	switch (locked) {
 	case LA_XLOCKED:
diff --git a/sys/kern/sys_pipe.c b/sys/kern/sys_pipe.c
index 30527fdd4fd0..57ebe8dc85f0 100644
--- a/sys/kern/sys_pipe.c
+++ b/sys/kern/sys_pipe.c
@@ -567,7 +567,7 @@ pipespace_new(struct pipe *cpipe, int size)
 	static int curfail = 0;
 	static struct timeval lastfail;
 
-	KASSERT(!mtx_owned(PIPE_MTX(cpipe)), ("pipespace: pipe mutex locked"));
+	PIPE_LOCK_ASSERT(cpipe, MA_NOTOWNED);
 	KASSERT(!(cpipe->pipe_state & PIPE_DIRECTW),
 		("pipespace: resize of direct writes not allowed"));
 retry:
@@ -1679,8 +1679,7 @@ static void
 pipe_free_kmem(struct pipe *cpipe)
 {
 
-	KASSERT(!mtx_owned(PIPE_MTX(cpipe)),
-	    ("pipe_free_kmem: pipe mutex locked"));
+	PIPE_LOCK_ASSERT(cpipe, MA_NOTOWNED);
 
 	if (cpipe->pipe_buffer.buffer != NULL) {
 		atomic_subtract_long(&amountpipekva, cpipe->pipe_buffer.size);
diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c
index 13abb9171234..557e451f9a45 100644
--- a/sys/kern/vfs_cache.c
+++ b/sys/kern/vfs_cache.c
@@ -3340,12 +3340,10 @@ sys___realpathat(struct thread *td, struct __realpathat_args *uap)
 	    uap->flags, UIO_USERSPACE));
 }
 
-/*
- * Retrieve the full filesystem path that correspond to a vnode from the name
- * cache (if available)
- */
-int
-vn_fullpath(struct vnode *vp, char **retbuf, char **freebuf)
+static int
+vn_fullpath_up_to_pwd_vnode(struct vnode *vp,
+    struct vnode *(*const get_pwd_vnode)(const struct pwd *),
+    char **retbuf, char **freebuf)
 {
 	struct pwd *pwd;
 	char *buf;
@@ -3359,11 +3357,13 @@ vn_fullpath(struct vnode *vp, char **retbuf, char **freebuf)
 	buf = malloc(buflen, M_TEMP, M_WAITOK);
 	vfs_smr_enter();
 	pwd = pwd_get_smr();
-	error = vn_fullpath_any_smr(vp, pwd->pwd_rdir, buf, retbuf, &buflen, 0);
+	error = vn_fullpath_any_smr(vp, get_pwd_vnode(pwd), buf, retbuf,
+	    &buflen, 0);
 	VFS_SMR_ASSERT_NOT_ENTERED();
 	if (error < 0) {
 		pwd = pwd_hold(curthread);
-		error = vn_fullpath_any(vp, pwd->pwd_rdir, buf, retbuf, &buflen);
+		error = vn_fullpath_any(vp, get_pwd_vnode(pwd), buf, retbuf,
+		    &buflen);
 		pwd_drop(pwd);
 	}
 	if (error == 0)
@@ -3373,6 +3373,42 @@ vn_fullpath(struct vnode *vp, char **retbuf, char **freebuf)
 	return (error);
 }
 
+static inline struct vnode *
+get_rdir(const struct pwd *pwd)
+{
+	return (pwd->pwd_rdir);
+}
+
+/*
+ * Produce a filesystem path that starts from the current chroot directory and
+ * corresponds to the passed vnode, using the name cache (if available).
+ */
+int
+vn_fullpath(struct vnode *vp, char **retbuf, char **freebuf)
+{
+	return (vn_fullpath_up_to_pwd_vnode(vp, get_rdir, retbuf, freebuf));
+}
+
+static inline struct vnode *
+get_jdir(const struct pwd *pwd)
+{
+	return (pwd->pwd_jdir);
+}
+
+/*
+ * Produce a filesystem path that starts from the current jail's root directory
+ * and corresponds to the passed vnode, using the name cache (if available).
+ *
+ * This function allows to ignore chroots done inside a jail (or the host),
+ * allowing path checks to remain unaffected by privileged or unprivileged
+ * chroot calls.
+ */
+int
+vn_fullpath_jail(struct vnode *vp, char **retbuf, char **freebuf)
+{
+	return (vn_fullpath_up_to_pwd_vnode(vp, get_jdir, retbuf, freebuf));
+}
+
 /*
  * This function is similar to vn_fullpath, but it attempts to lookup the
  * pathname relative to the global root mount point.  This is required for the
diff --git a/sys/kern/vfs_vnops.c b/sys/kern/vfs_vnops.c
index 3d4567b6ab1e..a53df50c06bd 100644
--- a/sys/kern/vfs_vnops.c
+++ b/sys/kern/vfs_vnops.c
@@ -806,9 +806,12 @@ file_v_lock(struct file *fp, short lock_bit, short lock_wait_bit)
 
 	flagsp = &fp->f_vflags;
 	state = atomic_load_16(flagsp);
-	if ((state & lock_bit) == 0 &&
-	    atomic_cmpset_acq_16(flagsp, state, state | lock_bit))
-		return;
+	for (;;) {
+		if ((state & lock_bit) != 0)
+			break;
+		if (atomic_fcmpset_acq_16(flagsp, &state, state | lock_bit))
+			return;
+	}
 
 	sleepq_lock(flagsp);
 	state = atomic_load_16(flagsp);
@@ -842,9 +845,12 @@ file_v_unlock(struct file *fp, short lock_bit, short lock_wait_bit)
 
 	flagsp = &fp->f_vflags;
 	state = atomic_load_16(flagsp);
-	if ((state & lock_wait_bit) == 0 &&
-	    atomic_cmpset_rel_16(flagsp, state, state & ~lock_bit))
-		return;
+	for (;;) {
+		if ((state & lock_wait_bit) != 0)
+			break;
+		if (atomic_fcmpset_rel_16(flagsp, &state, state & ~lock_bit))
+			return;
+	}
 
 	sleepq_lock(flagsp);
 	MPASS((*flagsp & lock_bit) != 0);
@@ -864,10 +870,6 @@ foffset_lock(struct file *fp, int flags)
 		    FILE_V_FOFFSET_LOCK_WAITING);
 	}
 
-	/*
-	 * According to McKusick the vn lock was protecting f_offset here.
-	 * It is now protected by the FOFFSET_LOCKED flag.
-	 */
 	return (atomic_load_long(&fp->f_offset));
 }
 
diff --git a/sys/modules/cxgbe/Makefile b/sys/modules/cxgbe/Makefile
index f94d3ae07f66..c2ee71465789 100644
--- a/sys/modules/cxgbe/Makefile
+++ b/sys/modules/cxgbe/Makefile
@@ -1,6 +1,3 @@
-#
-#
-
 SYSDIR?=${SRCTOP}/sys
 .include "${SYSDIR}/conf/kern.opts.mk"
 
@@ -13,6 +10,7 @@ SUBDIR+=	if_ccv
 SUBDIR+=	t4_firmware
 SUBDIR+=	t5_firmware
 SUBDIR+=	t6_firmware
+SUBDIR+=	t7_firmware
 SUBDIR+=	${_tom}
 SUBDIR+=	${_iw_cxgbe}
 SUBDIR+=	${_cxgbei}
diff --git a/sys/modules/cxgbe/if_cxgbe/Makefile b/sys/modules/cxgbe/if_cxgbe/Makefile
index 981c3466c452..33383c84837f 100644
--- a/sys/modules/cxgbe/if_cxgbe/Makefile
+++ b/sys/modules/cxgbe/if_cxgbe/Makefile
@@ -23,6 +23,7 @@ SRCS+=	t4_hw.c
 SRCS+=	t4_if.c t4_if.h
 SRCS+=	t4_iov.c
 SRCS.KERN_TLS+=	t6_kern_tls.c
+SRCS.KERN_TLS+=	t7_kern_tls.c
 SRCS+=	t4_keyctx.c
 SRCS+=	t4_l2t.c
 SRCS+=	t4_main.c
@@ -31,6 +32,7 @@ SRCS+=	t4_netmap.c
 SRCS+=	t4_sched.c
 SRCS+=	t4_sge.c
 SRCS+=	t4_smt.c
+SRCS+=	t4_tpt.c
 SRCS+=	t4_tracer.c
 SRCS+=  cudbg_common.c
 SRCS+=  cudbg_flash_utils.c
diff --git a/sys/modules/cxgbe/t7_firmware/Makefile b/sys/modules/cxgbe/t7_firmware/Makefile
new file mode 100644
index 000000000000..afce06487f22
--- /dev/null
+++ b/sys/modules/cxgbe/t7_firmware/Makefile
@@ -0,0 +1,23 @@
+#
+# $FreeBSD$
+#
+
+T7FW=	${SRCTOP}/sys/dev/cxgbe/firmware
+.PATH: ${T7FW}
+
+KMOD=	t7fw_cfg
+FIRMWS=	${KMOD}.txt:${KMOD}:1.0.0.0
+
+# You can have additional configuration files in the ${T7FW} directory.
+# t7fw_cfg_<name>.txt
+CFG_FILES != cd ${T7FW} && echo ${KMOD}_*.txt
+.for F in ${CFG_FILES}
+.if exists(${F})
+FIRMWS+=	${F}:${F:C/.txt//}:1.0.0.0
+.endif
+.endfor
+
+#T7FW_VER=	1.27.0.71
+#FIRMWS+=	t7fw-${T7FW_VER}.bin:t7fw:${T7FW_VER}
+
+.include <bsd.kmod.mk>
diff --git a/sys/modules/zfs/zfs_config.h b/sys/modules/zfs/zfs_config.h
index c595030ed4a0..db1b6f33a8ef 100644
--- a/sys/modules/zfs/zfs_config.h
+++ b/sys/modules/zfs/zfs_config.h
@@ -843,7 +843,7 @@
 /* #undef ZFS_DEVICE_MINOR */
 
 /* Define the project alias string. */
-#define ZFS_META_ALIAS "zfs-2.4.99-72-FreeBSD_gb2196fbed"
+#define ZFS_META_ALIAS "zfs-2.4.99-95-FreeBSD_g5605a6d79"
 
 /* Define the project author. */
 #define ZFS_META_AUTHOR "OpenZFS"
@@ -852,7 +852,7 @@
 /* #undef ZFS_META_DATA */
 
 /* Define the maximum compatible kernel version. */
-#define ZFS_META_KVER_MAX "6.16"
+#define ZFS_META_KVER_MAX "6.17"
 
 /* Define the minimum compatible kernel version. */
 #define ZFS_META_KVER_MIN "4.18"
@@ -873,7 +873,7 @@
 #define ZFS_META_NAME "zfs"
 
 /* Define the project release. */
-#define ZFS_META_RELEASE "72-FreeBSD_gb2196fbed"
+#define ZFS_META_RELEASE "95-FreeBSD_g5605a6d79"
 
 /* Define the project version. */
 #define ZFS_META_VERSION "2.4.99"
diff --git a/sys/modules/zfs/zfs_gitrev.h b/sys/modules/zfs/zfs_gitrev.h
index 9eae1e8573c0..8a1802f5480b 100644
--- a/sys/modules/zfs/zfs_gitrev.h
+++ b/sys/modules/zfs/zfs_gitrev.h
@@ -1 +1 @@
-#define	ZFS_META_GITREV "zfs-2.4.99-72-gb2196fbed"
+#define	ZFS_META_GITREV "zfs-2.4.99-95-g5605a6d79"
diff --git a/sys/net/iflib.c b/sys/net/iflib.c
index 1e6d98291c04..d2625da19cd2 100644
--- a/sys/net/iflib.c
+++ b/sys/net/iflib.c
@@ -142,7 +142,9 @@ struct iflib_ctx;
 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
 static void iflib_timer(void *arg);
 static void iflib_tqg_detach(if_ctx_t ctx);
+#ifndef ALTQ
 static int  iflib_simple_transmit(if_t ifp, struct mbuf *m);
+#endif
 
 typedef struct iflib_filter_info {
 	driver_filter_t *ifi_filter;
@@ -200,6 +202,8 @@ struct iflib_ctx {
 	uint16_t ifc_sysctl_extra_msix_vectors;
 	bool     ifc_cpus_are_physical_cores;
 	bool     ifc_sysctl_simple_tx;
+	uint16_t ifc_sysctl_tx_reclaim_thresh;
+	uint16_t ifc_sysctl_tx_reclaim_ticks;
 
 	qidx_t ifc_sysctl_ntxds[8];
 	qidx_t ifc_sysctl_nrxds[8];
@@ -343,7 +347,9 @@ struct iflib_txq {
 	uint16_t	ift_npending;
 	uint16_t	ift_db_pending;
 	uint16_t	ift_rs_pending;
-	/* implicit pad */
+	uint32_t	ift_last_reclaim;
+	uint16_t	ift_reclaim_thresh;
+	uint16_t	ift_reclaim_ticks;
 	uint8_t		ift_txd_size[8];
 	uint64_t	ift_processed;
 	uint64_t	ift_cleaned;
@@ -727,7 +733,7 @@ static void iflib_free_intr_mem(if_ctx_t ctx);
 #ifndef __NO_STRICT_ALIGNMENT
 static struct mbuf *iflib_fixup_rx(struct mbuf *m);
 #endif
-static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh);
+static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq);
 
 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
     SLIST_HEAD_INITIALIZER(cpu_offsets);
@@ -3082,8 +3088,6 @@ txq_max_rs_deferred(iflib_txq_t txq)
 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
 
-/* XXX we should be setting this to something other than zero */
-#define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
 #define	MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
     (ctx)->ifc_softc_ctx.isc_tx_nsegments)
 
@@ -3640,7 +3644,7 @@ defrag:
 	 *        cxgb
 	 */
 	if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
-		(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
+		(void)iflib_completed_tx_reclaim(txq);
 		if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
 			txq->ift_no_desc_avail++;
 			bus_dmamap_unload(buf_tag, map);
@@ -3783,14 +3787,21 @@ iflib_tx_desc_free(iflib_txq_t txq, int n)
 }
 
 static __inline int
-iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
+iflib_completed_tx_reclaim(iflib_txq_t txq)
 {
-	int reclaim;
+	int reclaim, thresh;
+	uint32_t now;
 	if_ctx_t ctx = txq->ift_ctx;
 
+	thresh = txq->ift_reclaim_thresh;
 	KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
 	MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
 
+	now = ticks;
+	if (now <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) &&
+	    txq->ift_in_use < thresh)
+		return (0);
+	txq->ift_last_reclaim = now;
 	/*
 	 * Need a rate-limiting check so that this isn't called every time
 	 */
@@ -3871,7 +3882,7 @@ iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
 		DBG_COUNTER_INC(txq_drain_notready);
 		return (0);
 	}
-	reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
+	reclaimed = iflib_completed_tx_reclaim(txq);
 	rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
 	avail = IDXDIFF(pidx, cidx, r->size);
 
@@ -3950,7 +3961,7 @@ iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
 	}
 
 	/* deliberate use of bitwise or to avoid gratuitous short-circuit */
-	ring = rang ? false  : (iflib_min_tx_latency | err);
+	ring = rang ? false  : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh));
 	iflib_txd_db_check(txq, ring);
 	if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
@@ -4030,7 +4041,7 @@ _task_fn_tx(void *context)
 #endif
         if (ctx->ifc_sysctl_simple_tx) {
                 mtx_lock(&txq->ift_mtx);
-                (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
+                (void)iflib_completed_tx_reclaim(txq);
                 mtx_unlock(&txq->ift_mtx);
                 goto skip_ifmp;
         }
@@ -5881,6 +5892,7 @@ iflib_queues_alloc(if_ctx_t ctx)
 			device_printf(dev, "Unable to allocate buf_ring\n");
 			goto err_tx_desc;
 		}
+		txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh;
 	}
 
 	for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
@@ -6772,6 +6784,74 @@ mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
 	return (rc);
 }
 
+static int
+iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS)
+{
+	if_ctx_t ctx = (void *)arg1;
+	iflib_txq_t txq;
+	int i, err;
+	int thresh;
+
+	thresh = ctx->ifc_sysctl_tx_reclaim_thresh;
+	err = sysctl_handle_int(oidp, &thresh, arg2, req);
+	if (err != 0) {
+		return err;
+	}
+
+	if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh)
+		return 0;
+
+	if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) {
+		device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n",
+		    ctx->ifc_softc_ctx.isc_ntxd[0] / 2);
+		return (EINVAL);
+	}
+
+	ctx->ifc_sysctl_tx_reclaim_thresh = thresh;
+	if (ctx->ifc_txqs == NULL)
+		return (err);
+
+	txq = &ctx->ifc_txqs[0];
+	for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
+		txq->ift_reclaim_thresh = thresh;
+	}
+	return (err);
+}
+
+static int
+iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS)
+{
+	if_ctx_t ctx = (void *)arg1;
+	iflib_txq_t txq;
+	int i, err;
+	int ticks;
+
+	ticks = ctx->ifc_sysctl_tx_reclaim_ticks;
+	err = sysctl_handle_int(oidp, &ticks, arg2, req);
+	if (err != 0) {
+		return err;
+	}
+
+	if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks)
+		return 0;
+
+	if (ticks > hz) {
+		device_printf(ctx->ifc_dev,
+		    "TX Reclaim ticks must be <= hz (%d)\n", hz);
+		return (EINVAL);
+	}
+
+	ctx->ifc_sysctl_tx_reclaim_ticks = ticks;
+	if (ctx->ifc_txqs == NULL)
+		return (err);
+
+	txq = &ctx->ifc_txqs[0];
+	for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
+		txq->ift_reclaim_ticks = ticks;
+	}
+	return (err);
+}
+
 #define NAME_BUFLEN 32
 static void
 iflib_add_device_sysctl_pre(if_ctx_t ctx)
@@ -6860,6 +6940,16 @@ iflib_add_device_sysctl_post(if_ctx_t ctx)
 	node = ctx->ifc_sysctl_node;
 	child = SYSCTL_CHILDREN(node);
 
+       SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh",
+           CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
+           0, iflib_handle_tx_reclaim_thresh, "I",
+           "Number of TX descs outstanding before reclaim is called");
+
+       SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks",
+           CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
+           0, iflib_handle_tx_reclaim_ticks, "I",
+           "Number of ticks before a TX reclaim is forced");
+
 	if (scctx->isc_ntxqsets > 100)
 		qfmt = "txq%03d";
 	else if (scctx->isc_ntxqsets > 10)
@@ -7107,7 +7197,7 @@ iflib_debugnet_poll(if_t ifp, int count)
 		return (EBUSY);
 
 	txq = &ctx->ifc_txqs[0];
-	(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
+	(void)iflib_completed_tx_reclaim(txq);
 
 	NET_EPOCH_ENTER(et);
 	for (i = 0; i < scctx->isc_nrxqsets; i++)
@@ -7117,7 +7207,7 @@ iflib_debugnet_poll(if_t ifp, int count)
 }
 #endif /* DEBUGNET */
 
-
+#ifndef ALTQ
 static inline iflib_txq_t
 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m)
 {
@@ -7157,7 +7247,7 @@ iflib_simple_transmit(if_t ifp, struct mbuf *m)
 		else
 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 	}
-	(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
+	(void)iflib_completed_tx_reclaim(txq);
 	mtx_unlock(&txq->ift_mtx);
 	if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
@@ -7166,3 +7256,4 @@ iflib_simple_transmit(if_t ifp, struct mbuf *m)
 
 	return (error);
 }
+#endif
diff --git a/sys/net/iflib.h b/sys/net/iflib.h
index 3817445228d0..e65c936fc4b4 100644
--- a/sys/net/iflib.h
+++ b/sys/net/iflib.h
@@ -272,7 +272,7 @@ struct if_shared_ctx {
 	int isc_ntxqs;			/* # of tx queues per tx qset - usually 1 */
 	int isc_nrxqs;			/* # of rx queues per rx qset - intel 1, chelsio 2, broadcom 3 */
 	int __spare0__;
-	int isc_tx_reclaim_thresh;
+	int __spare1__;
 	int isc_flags;
 };
 
diff --git a/sys/net/pfvar.h b/sys/net/pfvar.h
index c6a3448584ac..8aefe514946e 100644
--- a/sys/net/pfvar.h
+++ b/sys/net/pfvar.h
@@ -1166,7 +1166,6 @@ struct pf_test_ctx {
 	int			 rewrite;
 	u_short			 reason;
 	struct pf_src_node	*sns[PF_SN_MAX];
-	struct pf_krule_slist	 rules;
 	struct pf_krule		*nr;
 	struct pf_krule		*tr;
 	struct pf_krule		**rm;
@@ -2724,8 +2723,10 @@ int	pf_osfp_match(struct pf_osfp_enlist *, pf_osfp_t);
 #ifdef _KERNEL
 void			 pf_print_host(struct pf_addr *, u_int16_t, sa_family_t);
 
-enum pf_test_status	 pf_step_into_anchor(struct pf_test_ctx *, struct pf_krule *);
-enum pf_test_status	 pf_match_rule(struct pf_test_ctx *, struct pf_kruleset *);
+enum pf_test_status	 pf_step_into_anchor(struct pf_test_ctx *, struct pf_krule *,
+			    struct pf_krule_slist *match_rules);
+enum pf_test_status	 pf_match_rule(struct pf_test_ctx *, struct pf_kruleset *,
+			    struct pf_krule_slist *);
 void			 pf_step_into_keth_anchor(struct pf_keth_anchor_stackframe *,
 			    int *, struct pf_keth_ruleset **,
 			    struct pf_keth_rule **, struct pf_keth_rule **,
diff --git a/sys/net80211/ieee80211_var.h b/sys/net80211/ieee80211_var.h
index b9bc2357428d..7b45261f59b1 100644
--- a/sys/net80211/ieee80211_var.h
+++ b/sys/net80211/ieee80211_var.h
@@ -1013,7 +1013,7 @@ ieee80211_get_node_txpower(struct ieee80211_node *ni)
  * Debugging facilities compiled in when IEEE80211_DEBUG is defined.
  *
  * The intent is that any problem in the net80211 layer can be
- * diagnosed by inspecting the statistics (dumped by the wlanstats
+ * diagnosed by inspecting the statistics (dumped by the wlanstat
  * program) and/or the msgs generated by net80211.  Messages are
  * broken into functional classes and can be controlled with the
  * wlandebug program.  Certain of these msg groups are for facilities
diff --git a/sys/netgraph/netflow/netflow.c b/sys/netgraph/netflow/netflow.c
index 978d6fd0b54d..05c6062463be 100644
--- a/sys/netgraph/netflow/netflow.c
+++ b/sys/netgraph/netflow/netflow.c
@@ -960,7 +960,7 @@ struct ngnf_show_header *resp)
 
 		list_id = 0;
 		TAILQ_FOREACH(fle, &hsh->head, fle_hash) {
-			if (hsh->mtx.mtx_lock & MTX_CONTESTED) {
+			if (hsh->mtx.mtx_lock & MTX_WAITERS) {
 				resp->hash_id = i;
 				resp->list_id = list_id;
 				mtx_unlock(&hsh->mtx);
@@ -1111,7 +1111,7 @@ ng_netflow_expire(void *arg)
 			 * Interrupt thread wants this entry!
 			 * Quick! Quick! Bail out!
 			 */
-			if (hsh->mtx.mtx_lock & MTX_CONTESTED)
+			if (hsh->mtx.mtx_lock & MTX_WAITERS)
 				break;
 
 			/*
@@ -1150,7 +1150,7 @@ ng_netflow_expire(void *arg)
 			 * Interrupt thread wants this entry!
 			 * Quick! Quick! Bail out!
 			 */
-			if (hsh->mtx.mtx_lock & MTX_CONTESTED)
+			if (hsh->mtx.mtx_lock & MTX_WAITERS)
 				break;
 
 			/*
diff --git a/sys/netinet/ip_carp.c b/sys/netinet/ip_carp.c
index d3d7957cf087..4f553b9aac5e 100644
--- a/sys/netinet/ip_carp.c
+++ b/sys/netinet/ip_carp.c
@@ -1640,18 +1640,31 @@ carp_iamatch(struct ifaddr *ifa, uint8_t **enaddr)
 static void
 carp_send_na(struct carp_softc *sc)
 {
-	static struct in6_addr mcast = IN6ADDR_LINKLOCAL_ALLNODES_INIT;
 	struct ifaddr *ifa;
-	struct in6_addr *in6;
+	int flags;
 
+	/*
+	 * Sending Unsolicited Neighbor Advertisements
+	 *
+	 * If the node is a router, we MUST set the Router flag to one.
+	 * We set Override flag to one and send link-layer address option,
+	 * thus neighboring nodes will install the new link-layer address.
+	 */
+	flags = ND_NA_FLAG_OVERRIDE;
+	if (V_ip6_forwarding)
+		flags |= ND_NA_FLAG_ROUTER;
 	CARP_FOREACH_IFA(sc, ifa) {
 		if (ifa->ifa_addr->sa_family != AF_INET6)
 			continue;
-
-		in6 = IFA_IN6(ifa);
-		nd6_na_output(sc->sc_carpdev, &mcast, in6,
-		    ND_NA_FLAG_OVERRIDE, 1, NULL);
-		DELAY(1000);	/* XXX */
+		/*
+		 * We use unspecified address as destination here to avoid
+		 * scope initialization for each call.
+		 * nd6_na_output() will use all nodes multicast address if
+		 * destinaion address is unspecified.
+		 */
+		nd6_na_output(sc->sc_carpdev, &in6addr_any, IFA_IN6(ifa),
+		    flags, ND6_NA_OPT_LLA | ND6_NA_CARP_MASTER, NULL);
+		DELAY(1000);	/* RetransTimer */
 	}
 }
 
diff --git a/sys/netinet/sctp_lock_bsd.h b/sys/netinet/sctp_lock_bsd.h
index ec66be0cf371..a60983cb30e3 100644
--- a/sys/netinet/sctp_lock_bsd.h
+++ b/sys/netinet/sctp_lock_bsd.h
@@ -263,10 +263,10 @@
 } while (0)
 
 #define SCTP_INP_LOCK_CONTENDED(_inp)					\
-	((_inp)->inp_mtx.mtx_lock & MTX_CONTESTED)
+	((_inp)->inp_mtx.mtx_lock & MTX_WAITERS)
 
 #define SCTP_INP_READ_CONTENDED(_inp)					\
-	((_inp)->inp_rdata_mtx.mtx_lock & MTX_CONTESTED)
+	((_inp)->inp_rdata_mtx.mtx_lock & MTX_WAITERS)
 
 #ifdef SCTP_LOCK_LOGGING
 #define SCTP_INP_RLOCK(_inp)	do { 					\
@@ -337,7 +337,7 @@
 } while (0)
 
 #define SCTP_ASOC_CREATE_LOCK_CONTENDED(_inp)				\
-	((_inp)->inp_create_mtx.mtx_lock & MTX_CONTESTED)
+	((_inp)->inp_create_mtx.mtx_lock & MTX_WAITERS)
 
 /*
  * For the majority of things (once we have found the association) we will
diff --git a/sys/netinet/tcp_syncache.c b/sys/netinet/tcp_syncache.c
index 1ee6c6e31f33..f842a5678fa1 100644
--- a/sys/netinet/tcp_syncache.c
+++ b/sys/netinet/tcp_syncache.c
@@ -122,6 +122,7 @@ static void	 syncache_drop(struct syncache *, struct syncache_head *);
 static void	 syncache_free(struct syncache *);
 static void	 syncache_insert(struct syncache *, struct syncache_head *);
 static int	 syncache_respond(struct syncache *, const struct mbuf *, int);
+static void	 syncache_send_challenge_ack(struct syncache *, struct mbuf *);
 static struct	 socket *syncache_socket(struct syncache *, struct socket *,
 		    struct mbuf *m);
 static void	 syncache_timeout(struct syncache *sc, struct syncache_head *sch,
@@ -694,13 +695,7 @@ syncache_chkrst(struct in_conninfo *inc, struct tcphdr *th, struct mbuf *m,
 				    "sending challenge ACK\n",
 				    s, __func__,
 				    th->th_seq, sc->sc_irs + 1, sc->sc_wnd);
-			if (syncache_respond(sc, m, TH_ACK) == 0) {
-				TCPSTAT_INC(tcps_sndacks);
-				TCPSTAT_INC(tcps_sndtotal);
-			} else {
-				syncache_drop(sc, sch);
-				TCPSTAT_INC(tcps_sc_dropped);
-			}
+			syncache_send_challenge_ack(sc, m);
 		}
 	} else {
 		if ((s = tcp_log_addrs(inc, th, NULL, NULL)))
@@ -963,6 +958,10 @@ syncache_socket(struct syncache *sc, struct socket *lso, struct mbuf *m)
 	if (sc->sc_rxmits > 1)
 		tp->snd_cwnd = 1;
 
+	/* Copy over the challenge ACK state. */
+	tp->t_challenge_ack_end = sc->sc_challenge_ack_end;
+	tp->t_challenge_ack_cnt = sc->sc_challenge_ack_cnt;
+
 #ifdef TCP_OFFLOAD
 	/*
 	 * Allow a TOE driver to install its hooks.  Note that we hold the
@@ -1202,7 +1201,6 @@ syncache_expand(struct in_conninfo *inc, struct tcpopt *to, struct tcphdr *th,
 		 */
 		if (sc->sc_flags & SCF_TIMESTAMP && to->to_flags & TOF_TS &&
 		    TSTMP_LT(to->to_tsval, sc->sc_tsreflect)) {
-			SCH_UNLOCK(sch);
 			if ((s = tcp_log_addrs(inc, th, NULL, NULL))) {
 				log(LOG_DEBUG,
 				    "%s; %s: SEG.TSval %u < TS.Recent %u, "
@@ -1210,6 +1208,7 @@ syncache_expand(struct in_conninfo *inc, struct tcpopt *to, struct tcphdr *th,
 				    to->to_tsval, sc->sc_tsreflect);
 				free(s, M_TCPLOG);
 			}
+			SCH_UNLOCK(sch);
 			return (-1);  /* Do not send RST */
 		}
 
@@ -1258,6 +1257,38 @@ syncache_expand(struct in_conninfo *inc, struct tcpopt *to, struct tcphdr *th,
 				return (-1);  /* Do not send RST */
 			}
 		}
+
+		/*
+		 * SEG.SEQ validation:
+		 * The SEG.SEQ must be in the window starting at our
+		 * initial receive sequence number + 1.
+		 */
+		if (SEQ_LEQ(th->th_seq, sc->sc_irs) ||
+		    SEQ_GT(th->th_seq, sc->sc_irs + sc->sc_wnd)) {
+			if ((s = tcp_log_addrs(inc, th, NULL, NULL)))
+				log(LOG_DEBUG, "%s; %s: SEQ %u != IRS+1 %u, "
+				    "sending challenge ACK\n",
+				    s, __func__, th->th_seq, sc->sc_irs + 1);
+			syncache_send_challenge_ack(sc, m);
+			SCH_UNLOCK(sch);
+			free(s, M_TCPLOG);
+			return (-1);  /* Do not send RST */
+		}
+
+		/*
+		 * SEG.ACK validation:
+		 * SEG.ACK must match our initial send sequence number + 1.
+		 */
+		if (th->th_ack != sc->sc_iss + 1) {
+			if ((s = tcp_log_addrs(inc, th, NULL, NULL)))
+				log(LOG_DEBUG, "%s; %s: ACK %u != ISS+1 %u, "
+				    "segment rejected\n",
+				    s, __func__, th->th_ack, sc->sc_iss + 1);
+			SCH_UNLOCK(sch);
+			free(s, M_TCPLOG);
+			return (0);  /* Do send RST, do not free sc. */
+		}
+
 		TAILQ_REMOVE(&sch->sch_bucket, sc, sc_hash);
 		sch->sch_length--;
 #ifdef TCP_OFFLOAD
@@ -1270,29 +1301,6 @@ syncache_expand(struct in_conninfo *inc, struct tcpopt *to, struct tcphdr *th,
 		SCH_UNLOCK(sch);
 	}
 
-	/*
-	 * Segment validation:
-	 * ACK must match our initial sequence number + 1 (the SYN|ACK).
-	 */
-	if (th->th_ack != sc->sc_iss + 1) {
-		if ((s = tcp_log_addrs(inc, th, NULL, NULL)))
-			log(LOG_DEBUG, "%s; %s: ACK %u != ISS+1 %u, segment "
-			    "rejected\n", s, __func__, th->th_ack, sc->sc_iss);
-		goto failed;
-	}
-
-	/*
-	 * The SEQ must fall in the window starting at the received
-	 * initial receive sequence number + 1 (the SYN).
-	 */
-	if (SEQ_LEQ(th->th_seq, sc->sc_irs) ||
-	    SEQ_GT(th->th_seq, sc->sc_irs + sc->sc_wnd)) {
-		if ((s = tcp_log_addrs(inc, th, NULL, NULL)))
-			log(LOG_DEBUG, "%s; %s: SEQ %u != IRS+1 %u, segment "
-			    "rejected\n", s, __func__, th->th_seq, sc->sc_irs);
-		goto failed;
-	}
-
 	*lsop = syncache_socket(sc, *lsop, m);
 
 	if (__predict_false(*lsop == NULL)) {
@@ -2053,6 +2061,18 @@ syncache_respond(struct syncache *sc, const struct mbuf *m0, int flags)
 	return (error);
 }
 
+static void
+syncache_send_challenge_ack(struct syncache *sc, struct mbuf *m)
+{
+	if (tcp_challenge_ack_check(&sc->sc_challenge_ack_end,
+	    &sc->sc_challenge_ack_cnt)) {
+		if (syncache_respond(sc, m, TH_ACK) == 0) {
+			TCPSTAT_INC(tcps_sndacks);
+			TCPSTAT_INC(tcps_sndtotal);
+		}
+	}
+}
+
 /*
  * The purpose of syncookies is to handle spoofed SYN flooding DoS attacks
  * that exceed the capacity of the syncache by avoiding the storage of any
diff --git a/sys/netinet/tcp_syncache.h b/sys/netinet/tcp_syncache.h
index a336571f12c9..37f6ff3d6ca9 100644
--- a/sys/netinet/tcp_syncache.h
+++ b/sys/netinet/tcp_syncache.h
@@ -67,6 +67,8 @@ struct syncache {
 	u_int8_t	sc_requested_s_scale:4,
 			sc_requested_r_scale:4;
 	u_int16_t	sc_flags;
+	u_int32_t	sc_challenge_ack_cnt;	/* chall. ACKs sent in epoch */
+	sbintime_t	sc_challenge_ack_end;	/* End of chall. ack epoch */
 #if defined(TCP_OFFLOAD)
 	struct toedev	*sc_tod;		/* entry added by this TOE */
 	void		*sc_todctx;		/* TOE driver context */
diff --git a/sys/netinet6/in6.c b/sys/netinet6/in6.c
index 8ef755e2dc0a..b98703bdfbfe 100644
--- a/sys/netinet6/in6.c
+++ b/sys/netinet6/in6.c
@@ -1295,8 +1295,8 @@ in6_addifaddr(struct ifnet *ifp, struct in6_aliasreq *ifra, struct in6_ifaddr *i
 	 */
 	bzero(&pr0, sizeof(pr0));
 	pr0.ndpr_ifp = ifp;
-	pr0.ndpr_plen = in6_mask2len(&ifra->ifra_prefixmask.sin6_addr,
-	    NULL);
+	pr0.ndpr_plen = ia->ia_plen =
+	    in6_mask2len(&ifra->ifra_prefixmask.sin6_addr, NULL);
 	if (pr0.ndpr_plen == 128) {
 		/* we don't need to install a host route. */
 		goto aifaddr_out;
@@ -1490,16 +1490,16 @@ in6_unlink_ifa(struct in6_ifaddr *ia, struct ifnet *ifp)
 	 * positive reference.
 	 */
 	remove_lle = 0;
-	if (ia->ia6_ndpr == NULL) {
-		nd6log((LOG_NOTICE,
-		    "in6_unlink_ifa: autoconf'ed address "
-		    "%s has no prefix\n", ip6_sprintf(ip6buf, IA6_IN6(ia))));
-	} else {
+	if (ia->ia6_ndpr != NULL) {
 		ia->ia6_ndpr->ndpr_addrcnt--;
 		/* Do not delete lles within prefix if refcont != 0 */
 		if (ia->ia6_ndpr->ndpr_addrcnt == 0)
 			remove_lle = 1;
 		ia->ia6_ndpr = NULL;
+	} else if (ia->ia_plen < 128) {
+		nd6log((LOG_NOTICE,
+		    "in6_unlink_ifa: autoconf'ed address "
+		    "%s has no prefix\n", ip6_sprintf(ip6buf, IA6_IN6(ia))));
 	}
 
 	nd6_rem_ifa_lle(ia, remove_lle);
@@ -2604,8 +2604,6 @@ in6_domifattach(struct ifnet *ifp)
 	COUNTER_ARRAY_ALLOC(ext->icmp6_ifstat,
 	    sizeof(struct icmp6_ifstat) / sizeof(uint64_t), M_WAITOK);
 
-	ext->dad_failures = counter_u64_alloc(M_WAITOK);
-
 	ext->nd_ifinfo = nd6_ifattach(ifp);
 	ext->scope6_id = scope6_ifattach(ifp);
 	ext->lltable = in6_lltattach(ifp);
@@ -2641,7 +2639,6 @@ in6_domifdetach(struct ifnet *ifp, void *aux)
 	COUNTER_ARRAY_FREE(ext->icmp6_ifstat,
 	    sizeof(struct icmp6_ifstat) / sizeof(uint64_t));
 	free(ext->icmp6_ifstat, M_IFADDR);
-	counter_u64_free(ext->dad_failures);
 	free(ext, M_IFADDR);
 }
 
diff --git a/sys/netinet6/in6_ifattach.c b/sys/netinet6/in6_ifattach.c
index 4fde346fb691..090ba610460b 100644
--- a/sys/netinet6/in6_ifattach.c
+++ b/sys/netinet6/in6_ifattach.c
@@ -44,7 +44,6 @@
 #include <sys/rmlock.h>
 #include <sys/syslog.h>
 #include <sys/md5.h>
-#include <crypto/sha2/sha256.h>
 
 #include <net/if.h>
 #include <net/if_var.h>
@@ -72,6 +71,9 @@
 #include <netinet6/mld6_var.h>
 #include <netinet6/scope6_var.h>
 
+#include <crypto/sha2/sha256.h>
+#include <machine/atomic.h>
+
 #ifdef IP6_AUTO_LINKLOCAL
 VNET_DEFINE(int, ip6_auto_linklocal) = IP6_AUTO_LINKLOCAL;
 #else
@@ -377,7 +379,7 @@ in6_get_stableifid(struct ifnet *ifp, struct in6_addr *in6, int prefixlen)
 	}
 	hostuuid_len = strlen(hostuuid);
 
-	dad_failures = counter_u64_fetch(DAD_FAILURES(ifp));
+	dad_failures = atomic_load_int(&DAD_FAILURES(ifp));
 
 	/*
 	 * RFC 7217 section 7
diff --git a/sys/netinet6/in6_proto.c b/sys/netinet6/in6_proto.c
index 6669a2ba56ce..f567b42b42ca 100644
--- a/sys/netinet6/in6_proto.c
+++ b/sys/netinet6/in6_proto.c
@@ -167,7 +167,7 @@ VNET_DEFINE(int, ip6_rr_prune) = 5;	/* router renumbering prefix
 					 * walk list every 5 sec. */
 VNET_DEFINE(int, ip6_mcast_pmtu) = 0;	/* enable pMTU discovery for multicast? */
 VNET_DEFINE(int, ip6_v6only) = 1;
-VNET_DEFINE(int, ip6_stableaddr_maxretries) = IP6_IDGEN_RETRIES;
+VNET_DEFINE(u_int, ip6_stableaddr_maxretries) = IP6_IDGEN_RETRIES;
 
 #ifdef IPSTEALTH
 VNET_DEFINE(int, ip6stealth) = 0;
@@ -317,7 +317,7 @@ SYSCTL_INT(_net_inet6_ip6, IPV6CTL_USETEMPADDR, use_tempaddr,
 SYSCTL_BOOL(_net_inet6_ip6, IPV6CTL_USESTABLEADDR, use_stableaddr,
 	CTLFLAG_VNET | CTLFLAG_RWTUN, &VNET_NAME(ip6_use_stableaddr), 0,
 	"Create RFC7217 semantically opaque address for autoconfigured addresses (default for new interfaces)");
-SYSCTL_INT(_net_inet6_ip6, IPV6CTL_STABLEADDR_MAXRETRIES, stableaddr_maxretries,
+SYSCTL_UINT(_net_inet6_ip6, IPV6CTL_STABLEADDR_MAXRETRIES, stableaddr_maxretries,
 	CTLFLAG_VNET | CTLFLAG_RW, &VNET_NAME(ip6_stableaddr_maxretries), IP6_IDGEN_RETRIES,
 	"RFC7217 semantically opaque address DAD max retries");
 SYSCTL_INT(_net_inet6_ip6, IPV6CTL_STABLEADDR_NETIFSRC, stableaddr_netifsource,
diff --git a/sys/netinet6/in6_src.c b/sys/netinet6/in6_src.c
index dd6864482b3c..3e55c6e5fc05 100644
--- a/sys/netinet6/in6_src.c
+++ b/sys/netinet6/in6_src.c
@@ -132,8 +132,8 @@ static int in6_selectif(struct sockaddr_in6 *, struct ip6_pktopts *,
 	struct ip6_moptions *, struct ifnet **,
 	struct ifnet *, u_int);
 static int in6_selectsrc(uint32_t, struct sockaddr_in6 *,
-	struct ip6_pktopts *, struct inpcb *, struct ucred *,
-	struct ifnet **, struct in6_addr *);
+	struct ip6_pktopts *, struct ip6_moptions *, struct inpcb *,
+	struct ucred *, struct ifnet **, struct in6_addr *);
 
 static struct in6_addrpolicy *lookup_addrsel_policy(struct sockaddr_in6 *);
 
@@ -173,8 +173,8 @@ static struct in6_addrpolicy *match_addrsel_policy(struct sockaddr_in6 *);
 
 static int
 in6_selectsrc(uint32_t fibnum, struct sockaddr_in6 *dstsock,
-    struct ip6_pktopts *opts, struct inpcb *inp, struct ucred *cred,
-    struct ifnet **ifpp, struct in6_addr *srcp)
+    struct ip6_pktopts *opts, struct ip6_moptions *mopts, struct inpcb *inp,
+    struct ucred *cred, struct ifnet **ifpp, struct in6_addr *srcp)
 {
 	struct rm_priotracker in6_ifa_tracker;
 	struct in6_addr dst, tmp;
@@ -186,7 +186,6 @@ in6_selectsrc(uint32_t fibnum, struct sockaddr_in6 *dstsock,
 	u_int32_t odstzone;
 	int prefer_tempaddr;
 	int error;
-	struct ip6_moptions *mopts;
 
 	NET_EPOCH_ASSERT();
 	KASSERT(srcp != NULL, ("%s: srcp is NULL", __func__));
@@ -205,13 +204,6 @@ in6_selectsrc(uint32_t fibnum, struct sockaddr_in6 *dstsock,
 		*ifpp = NULL;
 	}
 
-	if (inp != NULL) {
-		INP_LOCK_ASSERT(inp);
-		mopts = inp->in6p_moptions;
-	} else {
-		mopts = NULL;
-	}
-
 	/*
 	 * If the source address is explicitly specified by the caller,
 	 * check if the requested source address is indeed a unicast address
@@ -552,10 +544,13 @@ in6_selectsrc_socket(struct sockaddr_in6 *dstsock, struct ip6_pktopts *opts,
 	uint32_t fibnum;
 	int error;
 
+	INP_LOCK_ASSERT(inp);
+
 	fibnum = inp->inp_inc.inc_fibnum;
 	retifp = NULL;
 
-	error = in6_selectsrc(fibnum, dstsock, opts, inp, cred, &retifp, srcp);
+	error = in6_selectsrc(fibnum, dstsock, opts, inp->in6p_moptions,
+	    inp, cred, &retifp, srcp);
 	if (error != 0)
 		return (error);
 
@@ -583,7 +578,7 @@ in6_selectsrc_socket(struct sockaddr_in6 *dstsock, struct ip6_pktopts *opts,
  * Stores selected address to @srcp.
  * Returns 0 on success.
  *
- * Used by non-socket based consumers (ND code mostly)
+ * Used by non-socket based consumers
  */
 int
 in6_selectsrc_addr(uint32_t fibnum, const struct in6_addr *dst,
@@ -602,13 +597,42 @@ in6_selectsrc_addr(uint32_t fibnum, const struct in6_addr *dst,
 	dst_sa.sin6_scope_id = scopeid;
 	sa6_embedscope(&dst_sa, 0);
 
-	error = in6_selectsrc(fibnum, &dst_sa, NULL, NULL, NULL, &retifp, srcp);
+	error = in6_selectsrc(fibnum, &dst_sa, NULL, NULL,
+	    NULL, NULL, &retifp, srcp);
 	if (hlim != NULL)
 		*hlim = in6_selecthlim(NULL, retifp);
 
 	return (error);
 }
 
+/*
+ * Select source address based on @fibnum, @dst and @mopts.
+ * Stores selected address to @srcp.
+ * Returns 0 on success.
+ *
+ * Used by non-socket based consumers (ND code mostly)
+ */
+int
+in6_selectsrc_nbr(uint32_t fibnum, const struct in6_addr *dst,
+    struct ip6_moptions *mopts, struct ifnet *ifp, struct in6_addr *srcp)
+{
+	struct sockaddr_in6 dst_sa;
+	struct ifnet *retifp;
+	int error;
+
+	retifp = ifp;
+	bzero(&dst_sa, sizeof(dst_sa));
+	dst_sa.sin6_family = AF_INET6;
+	dst_sa.sin6_len = sizeof(dst_sa);
+	dst_sa.sin6_addr = *dst;
+	dst_sa.sin6_scope_id = ntohs(in6_getscope(dst));
+	sa6_embedscope(&dst_sa, 0);
+
+	error = in6_selectsrc(fibnum, &dst_sa, NULL, mopts,
+	    NULL, NULL, &retifp, srcp);
+	return (error);
+}
+
 static struct nhop_object *
 cache_route(uint32_t fibnum, const struct sockaddr_in6 *dst, struct route_in6 *ro,
     uint32_t flowid)
diff --git a/sys/netinet6/in6_var.h b/sys/netinet6/in6_var.h
index e511ead24f08..1414cc71388d 100644
--- a/sys/netinet6/in6_var.h
+++ b/sys/netinet6/in6_var.h
@@ -106,7 +106,7 @@ struct in6_ifextra {
 	struct scope6_id *scope6_id;
 	struct lltable *lltable;
 	struct mld_ifsoftc *mld_ifinfo;
-	counter_u64_t dad_failures;	/* DAD failures when using RFC 7217 stable addresses */
+	u_int dad_failures;	/* DAD failures when using RFC 7217 stable addresses */
 };
 
 #define	LLTABLE6(ifp)	(((struct in6_ifextra *)(ifp)->if_afdata[AF_INET6])->lltable)
diff --git a/sys/netinet6/ip6_var.h b/sys/netinet6/ip6_var.h
index e1a4e8678ebb..db1631736c4a 100644
--- a/sys/netinet6/ip6_var.h
+++ b/sys/netinet6/ip6_var.h
@@ -344,7 +344,7 @@ VNET_DECLARE(bool, ip6_use_stableaddr);	/* Whether to use stable address generat
 #define	V_ip6_use_stableaddr		VNET(ip6_use_stableaddr)
 
 #define IP6_IDGEN_RETRIES		3 /* RFC 7217 section 7 default max retries */
-VNET_DECLARE(int, ip6_stableaddr_maxretries);
+VNET_DECLARE(u_int, ip6_stableaddr_maxretries);
 #define	V_ip6_stableaddr_maxretries	VNET(ip6_stableaddr_maxretries)
 
 #define IP6_STABLEADDR_NETIFSRC_NAME	0
@@ -440,6 +440,8 @@ int	in6_selectsrc_socket(struct sockaddr_in6 *, struct ip6_pktopts *,
     struct inpcb *, struct ucred *, int, struct in6_addr *, int *);
 int	in6_selectsrc_addr(uint32_t, const struct in6_addr *,
     uint32_t, struct ifnet *, struct in6_addr *, int *);
+int	in6_selectsrc_nbr(uint32_t, const struct in6_addr *,
+    struct ip6_moptions *, struct ifnet *, struct in6_addr *);
 int in6_selectroute(struct sockaddr_in6 *, struct ip6_pktopts *,
 	struct ip6_moptions *, struct route_in6 *, struct ifnet **,
 	struct nhop_object **, u_int, uint32_t);
diff --git a/sys/netinet6/nd6.h b/sys/netinet6/nd6.h
index 5fe027ac5e7c..e484c709e29a 100644
--- a/sys/netinet6/nd6.h
+++ b/sys/netinet6/nd6.h
@@ -171,6 +171,10 @@ struct	in6_ndifreq {
 #define NDPRF_ONLINK		0x1
 #define NDPRF_DETACHED		0x2
 
+/* ND6 NA output flags */
+#define	ND6_NA_OPT_LLA		0x01
+#define	ND6_NA_CARP_MASTER	0x02
+
 /* protocol constants */
 #define MAX_RTR_SOLICITATION_DELAY	1	/* 1sec */
 #define RTR_SOLICITATION_INTERVAL	4	/* 4sec */
diff --git a/sys/netinet6/nd6_nbr.c b/sys/netinet6/nd6_nbr.c
index cc17b4e1a402..29151b29a071 100644
--- a/sys/netinet6/nd6_nbr.c
+++ b/sys/netinet6/nd6_nbr.c
@@ -77,6 +77,8 @@
 #include <netinet/ip_carp.h>
 #include <netinet6/send.h>
 
+#include <machine/atomic.h>
+
 #define SDL(s) ((struct sockaddr_dl *)s)
 
 struct dadq;
@@ -245,10 +247,9 @@ nd6_ns_input(struct mbuf *m, int off, int icmp6len)
 	 * In implementation, we add target link-layer address by default.
 	 * We do not add one in MUST NOT cases.
 	 */
-	if (!IN6_IS_ADDR_MULTICAST(&daddr6))
-		tlladdr = 0;
-	else
-		tlladdr = 1;
+	tlladdr = 0;
+	if (IN6_IS_ADDR_MULTICAST(&daddr6))
+		tlladdr |= ND6_NA_OPT_LLA;
 
 	/*
 	 * Target address (taddr6) must be either:
@@ -257,9 +258,11 @@ nd6_ns_input(struct mbuf *m, int off, int icmp6len)
 	 * (3) "tentative" address on which DAD is being performed.
 	 */
 	/* (1) and (3) check. */
-	if (ifp->if_carp)
+	if (ifp->if_carp) {
 		ifa = (*carp_iamatch6_p)(ifp, &taddr6);
-	else
+		if (ifa != NULL)
+			tlladdr |= ND6_NA_CARP_MASTER;
+	} else
 		ifa = (struct ifaddr *)in6ifa_ifpwithaddr(ifp, &taddr6);
 
 	/* (2) check. */
@@ -323,32 +326,28 @@ nd6_ns_input(struct mbuf *m, int off, int icmp6len)
 	}
 
 	/*
+	 * If the Target Address is either an anycast address or a unicast
+	 * address for which the node is providing proxy service, or the Target
+	 * Link-Layer Address option is not included, the Override flag SHOULD
+	 * be set to zero.  Otherwise, the Override flag SHOULD be set to one.
+	 */
+	if (anycast == 0 && proxy == 0 && (tlladdr & ND6_NA_OPT_LLA) != 0)
+		rflag |= ND_NA_FLAG_OVERRIDE;
+	/*
 	 * If the source address is unspecified address, entries must not
 	 * be created or updated.
-	 * It looks that sender is performing DAD.  Output NA toward
-	 * all-node multicast address, to tell the sender that I'm using
-	 * the address.
+	 * It looks that sender is performing DAD. nd6_na_output() will
+	 * send NA toward all-node multicast address, to tell the sender
+	 * that I'm using the address.
 	 * S bit ("solicited") must be zero.
 	 */
-	if (IN6_IS_ADDR_UNSPECIFIED(&saddr6)) {
-		struct in6_addr in6_all;
-
-		in6_all = in6addr_linklocal_allnodes;
-		if (in6_setscope(&in6_all, ifp, NULL) != 0)
-			goto bad;
-		nd6_na_output_fib(ifp, &in6_all, &taddr6,
-		    ((anycast || proxy || !tlladdr) ? 0 : ND_NA_FLAG_OVERRIDE) |
-		    rflag, tlladdr, proxy ? (struct sockaddr *)&proxydl : NULL,
-		    M_GETFIB(m));
-		goto freeit;
+	if (!IN6_IS_ADDR_UNSPECIFIED(&saddr6)) {
+		nd6_cache_lladdr(ifp, &saddr6, lladdr, lladdrlen,
+		    ND_NEIGHBOR_SOLICIT, 0);
+		rflag |= ND_NA_FLAG_SOLICITED;
 	}
 
-	nd6_cache_lladdr(ifp, &saddr6, lladdr, lladdrlen,
-	    ND_NEIGHBOR_SOLICIT, 0);
-
-	nd6_na_output_fib(ifp, &saddr6, &taddr6,
-	    ((anycast || proxy || !tlladdr) ? 0 : ND_NA_FLAG_OVERRIDE) |
-	    rflag | ND_NA_FLAG_SOLICITED, tlladdr,
+	nd6_na_output_fib(ifp, &saddr6, &taddr6, rflag, tlladdr,
 	    proxy ? (struct sockaddr *)&proxydl : NULL, M_GETFIB(m));
  freeit:
 	if (ifa != NULL)
@@ -440,13 +439,6 @@ nd6_ns_output_fib(struct ifnet *ifp, const struct in6_addr *saddr6,
 		return;
 	M_SETFIB(m, fibnum);
 
-	if (daddr6 == NULL || IN6_IS_ADDR_MULTICAST(daddr6)) {
-		m->m_flags |= M_MCAST;
-		im6o.im6o_multicast_ifp = ifp;
-		im6o.im6o_multicast_hlim = 255;
-		im6o.im6o_multicast_loop = 0;
-	}
-
 	icmp6len = sizeof(*nd_ns);
 	m->m_pkthdr.len = m->m_len = sizeof(*ip6) + icmp6len;
 	m->m_data += max_linkhdr;	/* or M_ALIGN() equivalent? */
@@ -471,6 +463,12 @@ nd6_ns_output_fib(struct ifnet *ifp, const struct in6_addr *saddr6,
 		if (in6_setscope(&ip6->ip6_dst, ifp, NULL) != 0)
 			goto bad;
 	}
+	if (IN6_IS_ADDR_MULTICAST(&ip6->ip6_dst)) {
+		m->m_flags |= M_MCAST;
+		im6o.im6o_multicast_ifp = ifp;
+		im6o.im6o_multicast_hlim = 255;
+		im6o.im6o_multicast_loop = 0;
+	}
 	if (nonce == NULL) {
 		char ip6buf[INET6_ADDRSTRLEN];
 		struct ifaddr *ifa = NULL;
@@ -492,20 +490,16 @@ nd6_ns_output_fib(struct ifnet *ifp, const struct in6_addr *saddr6,
 			ifa = (struct ifaddr *)in6ifa_ifpwithaddr(ifp, saddr6);
 		if (ifa == NULL) {
 			int error;
-			struct in6_addr dst6, src6;
-			uint32_t scopeid;
 
-			in6_splitscope(&ip6->ip6_dst, &dst6, &scopeid);
-			error = in6_selectsrc_addr(fibnum, &dst6,
-			    scopeid, ifp, &src6, NULL);
+			error = in6_selectsrc_nbr(fibnum, &ip6->ip6_dst, &im6o,
+			    ifp, &ip6->ip6_src);
 			if (error) {
 				nd6log((LOG_DEBUG, "%s: source can't be "
 				    "determined: dst=%s, error=%d\n", __func__,
-				    ip6_sprintf(ip6buf, &dst6),
+				    ip6_sprintf(ip6buf, &ip6->ip6_dst),
 				    error));
 				goto bad;
 			}
-			ip6->ip6_src = src6;
 		} else
 			ip6->ip6_src = *saddr6;
 
@@ -968,7 +962,9 @@ nd6_na_input(struct mbuf *m, int off, int icmp6len)
  * - proxy advertisement delay rule (RFC2461 7.2.8, last paragraph, SHOULD)
  * - anycast advertisement delay rule (RFC2461 7.2.7, SHOULD)
  *
- * tlladdr - 1 if include target link-layer address
+ * tlladdr:
+ * - 0x01 if include target link-layer address
+ * - 0x02 if target address is CARP MASTER
  * sdl0 - sockaddr_dl (= proxy NA) or NULL
  */
 static void
@@ -981,8 +977,7 @@ nd6_na_output_fib(struct ifnet *ifp, const struct in6_addr *daddr6_0,
 	struct ip6_hdr *ip6;
 	struct nd_neighbor_advert *nd_na;
 	struct ip6_moptions im6o;
-	struct in6_addr daddr6, dst6, src6;
-	uint32_t scopeid;
+	struct in6_addr daddr6;
 
 	NET_EPOCH_ASSERT();
 
@@ -1006,13 +1001,6 @@ nd6_na_output_fib(struct ifnet *ifp, const struct in6_addr *daddr6_0,
 		return;
 	M_SETFIB(m, fibnum);
 
-	if (IN6_IS_ADDR_MULTICAST(&daddr6)) {
-		m->m_flags |= M_MCAST;
-		im6o.im6o_multicast_ifp = ifp;
-		im6o.im6o_multicast_hlim = 255;
-		im6o.im6o_multicast_loop = 0;
-	}
-
 	icmp6len = sizeof(*nd_na);
 	m->m_pkthdr.len = m->m_len = sizeof(struct ip6_hdr) + icmp6len;
 	m->m_data += max_linkhdr;	/* or M_ALIGN() equivalent? */
@@ -1024,26 +1012,24 @@ nd6_na_output_fib(struct ifnet *ifp, const struct in6_addr *daddr6_0,
 	ip6->ip6_vfc |= IPV6_VERSION;
 	ip6->ip6_nxt = IPPROTO_ICMPV6;
 	ip6->ip6_hlim = 255;
+
 	if (IN6_IS_ADDR_UNSPECIFIED(&daddr6)) {
 		/* reply to DAD */
-		daddr6.s6_addr16[0] = IPV6_ADDR_INT16_MLL;
-		daddr6.s6_addr16[1] = 0;
-		daddr6.s6_addr32[1] = 0;
-		daddr6.s6_addr32[2] = 0;
-		daddr6.s6_addr32[3] = IPV6_ADDR_INT32_ONE;
+		daddr6 = in6addr_linklocal_allnodes;
 		if (in6_setscope(&daddr6, ifp, NULL))
 			goto bad;
 
 		flags &= ~ND_NA_FLAG_SOLICITED;
 	}
-	ip6->ip6_dst = daddr6;
+	if (IN6_IS_ADDR_MULTICAST(&daddr6)) {
+		m->m_flags |= M_MCAST;
+		im6o.im6o_multicast_ifp = ifp;
+		im6o.im6o_multicast_hlim = 255;
+		im6o.im6o_multicast_loop = 0;
+	}
 
-	/*
-	 * Select a source whose scope is the same as that of the dest.
-	 */
-	in6_splitscope(&daddr6, &dst6, &scopeid);
-	error = in6_selectsrc_addr(fibnum, &dst6,
-	    scopeid, ifp, &src6, NULL);
+	ip6->ip6_dst = daddr6;
+	error = in6_selectsrc_nbr(fibnum, &daddr6, &im6o, ifp, &ip6->ip6_src);
 	if (error) {
 		char ip6buf[INET6_ADDRSTRLEN];
 		nd6log((LOG_DEBUG, "nd6_na_output: source can't be "
@@ -1051,7 +1037,6 @@ nd6_na_output_fib(struct ifnet *ifp, const struct in6_addr *daddr6_0,
 		    ip6_sprintf(ip6buf, &daddr6), error));
 		goto bad;
 	}
-	ip6->ip6_src = src6;
 	nd_na = (struct nd_neighbor_advert *)(ip6 + 1);
 	nd_na->nd_na_type = ND_NEIGHBOR_ADVERT;
 	nd_na->nd_na_code = 0;
@@ -1059,20 +1044,24 @@ nd6_na_output_fib(struct ifnet *ifp, const struct in6_addr *daddr6_0,
 	in6_clearscope(&nd_na->nd_na_target); /* XXX */
 
 	/*
+	 * If we respond from CARP address, we need to prepare mac address
+	 * for carp_output().
+	 */
+	if (ifp->if_carp && (tlladdr & ND6_NA_CARP_MASTER))
+		mac = (*carp_macmatch6_p)(ifp, m, taddr6);
+	/*
 	 * "tlladdr" indicates NS's condition for adding tlladdr or not.
 	 * see nd6_ns_input() for details.
 	 * Basically, if NS packet is sent to unicast/anycast addr,
 	 * target lladdr option SHOULD NOT be included.
 	 */
-	if (tlladdr) {
+	if (tlladdr & ND6_NA_OPT_LLA) {
 		/*
 		 * sdl0 != NULL indicates proxy NA.  If we do proxy, use
 		 * lladdr in sdl0.  If we are not proxying (sending NA for
 		 * my address) use lladdr configured for the interface.
 		 */
 		if (sdl0 == NULL) {
-			if (ifp->if_carp)
-				mac = (*carp_macmatch6_p)(ifp, m, taddr6);
 			if (mac == NULL)
 				mac = nd6_ifptomac(ifp);
 		} else if (sdl0->sa_family == AF_LINK) {
@@ -1082,7 +1071,7 @@ nd6_na_output_fib(struct ifnet *ifp, const struct in6_addr *daddr6_0,
 				mac = LLADDR(sdl);
 		}
 	}
-	if (tlladdr && mac) {
+	if ((tlladdr & ND6_NA_OPT_LLA) && mac != NULL) {
 		int optlen = sizeof(struct nd_opt_hdr) + ifp->if_addrlen;
 		struct nd_opt_hdr *nd_opt = (struct nd_opt_hdr *)(nd_na + 1);
 
@@ -1473,7 +1462,7 @@ nd6_dad_timer(void *arg)
 			if ((ND_IFINFO(ifp)->flags & ND6_IFF_IFDISABLED) == 0) {
 				ia->ia6_flags &= ~IN6_IFF_TENTATIVE;
 				if ((ND_IFINFO(ifp)->flags & ND6_IFF_STABLEADDR) && !(ia->ia6_flags & IN6_IFF_TEMPORARY))
-					counter_u64_zero(DAD_FAILURES(ifp));
+					atomic_store_int(&DAD_FAILURES(ifp), 0);
 			}
 
 			nd6log((LOG_DEBUG,
@@ -1522,10 +1511,10 @@ nd6_dad_duplicated(struct ifaddr *ifa, struct dadq *dp)
 	 * More addresses will be generated as long as retries are not exhausted.
 	 */
 	if ((ND_IFINFO(ifp)->flags & ND6_IFF_STABLEADDR) && !(ia->ia6_flags & IN6_IFF_TEMPORARY)) {
-		uint64_t dad_failures = counter_u64_fetch(DAD_FAILURES(ifp));
+		u_int dad_failures = atomic_load_int(&DAD_FAILURES(ifp));
 
 		if (dad_failures <= V_ip6_stableaddr_maxretries) {
-			counter_u64_add(DAD_FAILURES(ifp), 1);
+			atomic_add_int(&DAD_FAILURES(ifp), 1);
 			/* if retries exhausted, output an informative error message */
 			if (dad_failures == V_ip6_stableaddr_maxretries)
 				log(LOG_ERR, "%s: manual intervention required, consider disabling \"stableaddr\" on the interface"
diff --git a/sys/netinet6/nd6_rtr.c b/sys/netinet6/nd6_rtr.c
index 78dc55dd292f..10f0342f2bc4 100644
--- a/sys/netinet6/nd6_rtr.c
+++ b/sys/netinet6/nd6_rtr.c
@@ -74,6 +74,8 @@
 #include <netinet/icmp6.h>
 #include <netinet6/scope6_var.h>
 
+#include <machine/atomic.h>
+
 static struct nd_defrouter *defrtrlist_update(struct nd_defrouter *);
 static int prelist_update(struct nd_prefixctl *, struct nd_defrouter *,
     struct mbuf *, int);
@@ -1243,9 +1245,8 @@ in6_ifadd(struct nd_prefixctl *pr, int mcast)
 
 		/* No suitable LL address, get the ifid directly */
 		if (ifid_addr == NULL) {
-			struct in6_addr taddr;
-			ifa = ifa_alloc(sizeof(taddr), M_WAITOK);
-			if (ifa) {
+			ifa = ifa_alloc(sizeof(struct in6_ifaddr), M_NOWAIT);
+			if (ifa != NULL) {
 				ib = (struct in6_ifaddr *)ifa;
 				ifid_addr = &ib->ia_addr.sin6_addr;
 				if(in6_get_ifid(ifp, NULL, ifid_addr) != 0) {
@@ -1757,7 +1758,7 @@ prelist_update(struct nd_prefixctl *new, struct nd_defrouter *dr,
 		 * to fail and no further retries should happen.
 		 */
 		if (ND_IFINFO(ifp)->flags & ND6_IFF_STABLEADDR &&
-		    counter_u64_fetch(DAD_FAILURES(ifp)) <= V_ip6_stableaddr_maxretries &&
+		    atomic_load_int(&DAD_FAILURES(ifp)) <= V_ip6_stableaddr_maxretries &&
 		    ifa6->ia6_flags & (IN6_IFF_DUPLICATED | IN6_IFF_TEMPORARY))
 			continue;
 
diff --git a/sys/netlink/netlink_snl.h b/sys/netlink/netlink_snl.h
index 6dd8a9cbdb35..57f7e1e29d08 100644
--- a/sys/netlink/netlink_snl.h
+++ b/sys/netlink/netlink_snl.h
@@ -1068,14 +1068,14 @@ snl_init_writer(struct snl_state *ss, struct snl_writer *nw)
 {
 	nw->size = SNL_WRITER_BUFFER_SIZE;
 	nw->base = (char *)snl_allocz(ss, nw->size);
-	if (nw->base == NULL) {
+	if (__predict_false(nw->base == NULL)) {
 		nw->error = true;
 		nw->size = 0;
-	}
+	} else
+		nw->error = false;
 
 	nw->offset = 0;
 	nw->hdr = NULL;
-	nw->error = false;
 	nw->ss = ss;
 }
 
diff --git a/sys/netpfil/pf/pf.c b/sys/netpfil/pf/pf.c
index ec6960180413..d6fc24a23fe9 100644
--- a/sys/netpfil/pf/pf.c
+++ b/sys/netpfil/pf/pf.c
@@ -344,10 +344,12 @@ static int		 pf_test_eth_rule(int, struct pfi_kkif *,
 			    struct mbuf **);
 static int		 pf_test_rule(struct pf_krule **, struct pf_kstate **,
 			    struct pf_pdesc *, struct pf_krule **,
-			    struct pf_kruleset **, u_short *, struct inpcb *);
+			    struct pf_kruleset **, u_short *, struct inpcb *,
+			    struct pf_krule_slist *);
 static int		 pf_create_state(struct pf_krule *,
 			    struct pf_test_ctx *,
-			    struct pf_kstate **, u_int16_t, u_int16_t);
+			    struct pf_kstate **, u_int16_t, u_int16_t,
+			    struct pf_krule_slist *match_rules);
 static int		 pf_state_key_addr_setup(struct pf_pdesc *,
 			    struct pf_state_key_cmp *, int);
 static int		 pf_tcp_track_full(struct pf_kstate *,
@@ -393,7 +395,7 @@ static bool		 pf_src_connlimit(struct pf_kstate *);
 static int		 pf_match_rcvif(struct mbuf *, struct pf_krule *);
 static void		 pf_counters_inc(int, struct pf_pdesc *,
 			    struct pf_kstate *, struct pf_krule *,
-			    struct pf_krule *);
+			    struct pf_krule *, struct pf_krule_slist *);
 static void		 pf_log_matches(struct pf_pdesc *, struct pf_krule *,
 			    struct pf_krule *, struct pf_kruleset *,
 			    struct pf_krule_slist *);
@@ -489,26 +491,30 @@ BOUND_IFACE(struct pf_kstate *st, struct pf_pdesc *pd)
 			counter_u64_add(s->anchor->states_cur, 1);	\
 			counter_u64_add(s->anchor->states_tot, 1);	\
 		}							\
-		if (s->nat_rule != NULL) {				\
-			counter_u64_add(s->nat_rule->states_cur, 1);\
-			counter_u64_add(s->nat_rule->states_tot, 1);\
+		if (s->nat_rule != NULL && s->nat_rule != s->rule) {	\
+			counter_u64_add(s->nat_rule->states_cur, 1);	\
+			counter_u64_add(s->nat_rule->states_tot, 1);	\
 		}							\
 		SLIST_FOREACH(mrm, &s->match_rules, entry) {		\
-			counter_u64_add(mrm->r->states_cur, 1);		\
-			counter_u64_add(mrm->r->states_tot, 1);		\
+			if (s->nat_rule != mrm->r) {			\
+				counter_u64_add(mrm->r->states_cur, 1);	\
+				counter_u64_add(mrm->r->states_tot, 1);	\
+			}						\
 		}							\
 	} while (0)
 
 #define	STATE_DEC_COUNTERS(s)						\
 	do {								\
 		struct pf_krule_item *mrm;				\
-		if (s->nat_rule != NULL)				\
-			counter_u64_add(s->nat_rule->states_cur, -1);\
-		if (s->anchor != NULL)				\
-			counter_u64_add(s->anchor->states_cur, -1);	\
 		counter_u64_add(s->rule->states_cur, -1);		\
+		if (s->anchor != NULL)					\
+			counter_u64_add(s->anchor->states_cur, -1);	\
+		if (s->nat_rule != NULL && s->nat_rule != s->rule)	\
+			counter_u64_add(s->nat_rule->states_cur, -1);	\
 		SLIST_FOREACH(mrm, &s->match_rules, entry)		\
-			counter_u64_add(mrm->r->states_cur, -1);	\
+			if (s->nat_rule != mrm->r) {			\
+				counter_u64_add(mrm->r->states_cur, -1);\
+			}						\
 	} while (0)
 
 MALLOC_DEFINE(M_PFHASH, "pf_hash", "pf(4) hash header structures");
@@ -2869,20 +2875,24 @@ pf_alloc_state(int flags)
 	return (uma_zalloc(V_pf_state_z, flags | M_ZERO));
 }
 
+static __inline void
+pf_free_match_rules(struct pf_krule_slist *match_rules) {
+	struct pf_krule_item	*ri;
+
+	while ((ri = SLIST_FIRST(match_rules))) {
+		SLIST_REMOVE_HEAD(match_rules, entry);
+		free(ri, M_PF_RULE_ITEM);
+	}
+}
+
 void
 pf_free_state(struct pf_kstate *cur)
 {
-	struct pf_krule_item *ri;
-
 	KASSERT(cur->refs == 0, ("%s: %p has refs", __func__, cur));
 	KASSERT(cur->timeout == PFTM_UNLINKED, ("%s: timeout %u", __func__,
 	    cur->timeout));
 
-	while ((ri = SLIST_FIRST(&cur->match_rules))) {
-		SLIST_REMOVE_HEAD(&cur->match_rules, entry);
-		free(ri, M_PF_RULE_ITEM);
-	}
-
+	pf_free_match_rules(&(cur->match_rules));
 	pf_normalize_tcp_cleanup(cur);
 	uma_zfree(V_pf_state_z, cur);
 	pf_counter_u64_add(&V_pf_status.fcounters[FCNT_STATE_REMOVALS], 1);
@@ -3354,7 +3364,7 @@ pf_change_ap(struct pf_pdesc *pd, struct pf_addr *a, u_int16_t *p,
 	u_int16_t	po;
 	uint8_t		u = pd->virtual_proto == IPPROTO_UDP;
 
-	MPASS(pd->pcksum);
+	MPASS(pd->pcksum != NULL);
 	if (pd->af == AF_INET) {
 		MPASS(pd->ip_sum);
 	}
@@ -4740,7 +4750,8 @@ pf_tag_packet(struct pf_pdesc *pd, int tag)
 } while (0)
 
 enum pf_test_status
-pf_step_into_anchor(struct pf_test_ctx *ctx, struct pf_krule *r)
+pf_step_into_anchor(struct pf_test_ctx *ctx, struct pf_krule *r,
+    struct pf_krule_slist *match_rules)
 {
 	enum pf_test_status	rv;
 
@@ -4758,7 +4769,7 @@ pf_step_into_anchor(struct pf_test_ctx *ctx, struct pf_krule *r)
 		struct pf_kanchor *child;
 		rv = PF_TEST_OK;
 		RB_FOREACH(child, pf_kanchor_node, &r->anchor->children) {
-			rv = pf_match_rule(ctx, &child->ruleset);
+			rv = pf_match_rule(ctx, &child->ruleset, match_rules);
 			if ((rv == PF_TEST_QUICK) || (rv == PF_TEST_FAIL)) {
 				/*
 				 * we either hit a rule with quick action
@@ -4769,7 +4780,7 @@ pf_step_into_anchor(struct pf_test_ctx *ctx, struct pf_krule *r)
 			}
 		}
 	} else {
-		rv = pf_match_rule(ctx, &r->anchor->ruleset);
+		rv = pf_match_rule(ctx, &r->anchor->ruleset, match_rules);
 		/*
 		 * Unless errors occured, stop iff any rule matched
 		 * within quick anchors.
@@ -5618,9 +5629,10 @@ pf_rule_apply_nat(struct pf_test_ctx *ctx, struct pf_krule *r)
 }
 
 enum pf_test_status
-pf_match_rule(struct pf_test_ctx *ctx, struct pf_kruleset *ruleset)
+pf_match_rule(struct pf_test_ctx *ctx, struct pf_kruleset *ruleset,
+    struct pf_krule_slist *match_rules)
 {
-	struct pf_krule_item	*ri;
+	struct pf_krule_item	*ri, *rt;
 	struct pf_krule		*r;
 	struct pf_krule		*save_a;
 	struct pf_kruleset	*save_aruleset;
@@ -5777,11 +5789,14 @@ pf_match_rule(struct pf_test_ctx *ctx, struct pf_kruleset *ruleset)
 					return (PF_TEST_FAIL);
 				}
 				ri->r = r;
-				SLIST_INSERT_HEAD(&ctx->rules, ri, entry);
-				pf_counter_u64_critical_enter();
-				pf_counter_u64_add_protected(&r->packets[pd->dir == PF_OUT], 1);
-				pf_counter_u64_add_protected(&r->bytes[pd->dir == PF_OUT], pd->tot_len);
-				pf_counter_u64_critical_exit();
+
+				if (SLIST_EMPTY(match_rules)) {
+					SLIST_INSERT_HEAD(match_rules, ri, entry);
+				} else {
+					SLIST_INSERT_AFTER(rt, ri, entry);
+				}
+				rt = ri;
+
 				pf_rule_to_actions(r, &pd->act);
 				if (r->log)
 					PFLOG_PACKET(r->action, PFRES_MATCH, r,
@@ -5805,7 +5820,7 @@ pf_match_rule(struct pf_test_ctx *ctx, struct pf_kruleset *ruleset)
 				ctx->arsm = ctx->aruleset;
 			}
 			if (pd->act.log & PF_LOG_MATCHES)
-				pf_log_matches(pd, r, ctx->a, ruleset, &ctx->rules);
+				pf_log_matches(pd, r, ctx->a, ruleset, match_rules);
 			if (r->quick) {
 				ctx->test_status = PF_TEST_QUICK;
 				break;
@@ -5822,7 +5837,7 @@ pf_match_rule(struct pf_test_ctx *ctx, struct pf_kruleset *ruleset)
 			 * Note: we don't need to restore if we are not going
 			 * to continue with ruleset evaluation.
 			 */
-			if (pf_step_into_anchor(ctx, r) != PF_TEST_OK) {
+			if (pf_step_into_anchor(ctx, r, match_rules) != PF_TEST_OK) {
 				break;
 			}
 			ctx->a = save_a;
@@ -5838,11 +5853,11 @@ pf_match_rule(struct pf_test_ctx *ctx, struct pf_kruleset *ruleset)
 static int
 pf_test_rule(struct pf_krule **rm, struct pf_kstate **sm,
     struct pf_pdesc *pd, struct pf_krule **am,
-    struct pf_kruleset **rsm, u_short *reason, struct inpcb *inp)
+    struct pf_kruleset **rsm, u_short *reason, struct inpcb *inp,
+    struct pf_krule_slist *match_rules)
 {
 	struct pf_krule		*r = NULL;
 	struct pf_kruleset	*ruleset = NULL;
-	struct pf_krule_item	*ri;
 	struct pf_test_ctx	 ctx;
 	u_short			 transerror;
 	int			 action = PF_PASS;
@@ -5859,7 +5874,6 @@ pf_test_rule(struct pf_krule **rm, struct pf_kstate **sm,
 	ctx.rsm = rsm;
 	ctx.th = &pd->hdr.tcp;
 	ctx.reason = *reason;
-	SLIST_INIT(&ctx.rules);
 
 	pf_addrcpy(&pd->nsaddr, pd->src, pd->af);
 	pf_addrcpy(&pd->ndaddr, pd->dst, pd->af);
@@ -5951,44 +5965,49 @@ pf_test_rule(struct pf_krule **rm, struct pf_kstate **sm,
 		ctx.nat_pool = &(ctx.nr->rdr);
 	}
 
-	ruleset = &pf_main_ruleset;
-	rv = pf_match_rule(&ctx, ruleset);
-	if (rv == PF_TEST_FAIL) {
-		/*
-		 * Reason has been set in pf_match_rule() already.
-		 */
-		goto cleanup;
-	}
-
-	r = *ctx.rm;			/* matching rule */
-	ctx.a = *ctx.am;		/* rule that defines an anchor containing 'r' */
-	ruleset = *ctx.rsm;		/* ruleset of the anchor defined by the rule 'a' */
-	ctx.aruleset = ctx.arsm;	/* ruleset of the 'a' rule itself */
+	if (ctx.nr && ctx.nr->natpass) {
+		r = ctx.nr;
+		ruleset = *ctx.rsm;
+	} else {
+		ruleset = &pf_main_ruleset;
+		rv = pf_match_rule(&ctx, ruleset, match_rules);
+		if (rv == PF_TEST_FAIL) {
+			/*
+			 * Reason has been set in pf_match_rule() already.
+			 */
+			goto cleanup;
+		}
 
-	REASON_SET(&ctx.reason, PFRES_MATCH);
+		r = *ctx.rm;			/* matching rule */
+		ctx.a = *ctx.am;		/* rule that defines an anchor containing 'r' */
+		ruleset = *ctx.rsm;		/* ruleset of the anchor defined by the rule 'a' */
+		ctx.aruleset = ctx.arsm;	/* ruleset of the 'a' rule itself */
 
-	/* apply actions for last matching pass/block rule */
-	pf_rule_to_actions(r, &pd->act);
-	transerror = pf_rule_apply_nat(&ctx, r);
-	switch (transerror) {
-	case PFRES_MATCH:
-		/* Translation action found in rule and applied successfully */
-	case PFRES_MAX:
-		/* No translation action found in rule */
-		break;
-	default:
-		/* Translation action found in rule but failed to apply */
-		REASON_SET(&ctx.reason, transerror);
-		goto cleanup;
+		/* apply actions for last matching pass/block rule */
+		pf_rule_to_actions(r, &pd->act);
+		transerror = pf_rule_apply_nat(&ctx, r);
+		switch (transerror) {
+		case PFRES_MATCH:
+			/* Translation action found in rule and applied successfully */
+		case PFRES_MAX:
+			/* No translation action found in rule */
+			break;
+		default:
+			/* Translation action found in rule but failed to apply */
+			REASON_SET(&ctx.reason, transerror);
+			goto cleanup;
+		}
 	}
 
+	REASON_SET(&ctx.reason, PFRES_MATCH);
+
 	if (r->log) {
 		if (ctx.rewrite)
 			m_copyback(pd->m, pd->off, pd->hdrlen, pd->hdr.any);
 		PFLOG_PACKET(r->action, ctx.reason, r, ctx.a, ruleset, pd, 1, NULL);
 	}
 	if (pd->act.log & PF_LOG_MATCHES)
-		pf_log_matches(pd, r, ctx.a, ruleset, &ctx.rules);
+		pf_log_matches(pd, r, ctx.a, ruleset, match_rules);
 	if (pd->virtual_proto != PF_VPROTO_FRAGMENT &&
 	   (r->action == PF_DROP) &&
 	    ((r->rule_flag & PFRULE_RETURNRST) ||
@@ -6033,7 +6052,8 @@ pf_test_rule(struct pf_krule **rm, struct pf_kstate **sm,
 	    (pd->flags & PFDESC_TCP_NORM)))) {
 		bool nat64;
 
-		action = pf_create_state(r, &ctx, sm, bproto_sum, bip_sum);
+		action = pf_create_state(r, &ctx, sm, bproto_sum, bip_sum,
+		    match_rules);
 		ctx.sk = ctx.nk = NULL;
 		if (action != PF_PASS) {
 			pf_udp_mapping_release(ctx.udp_mapping);
@@ -6079,11 +6099,6 @@ pf_test_rule(struct pf_krule **rm, struct pf_kstate **sm,
 				action = PF_AFRT;
 		}
 	} else {
-		while ((ri = SLIST_FIRST(&ctx.rules))) {
-			SLIST_REMOVE_HEAD(&ctx.rules, entry);
-			free(ri, M_PF_RULE_ITEM);
-		}
-
 		uma_zfree(V_pf_state_key_z, ctx.sk);
 		uma_zfree(V_pf_state_key_z, ctx.nk);
 		ctx.sk = ctx.nk = NULL;
@@ -6111,11 +6126,6 @@ pf_test_rule(struct pf_krule **rm, struct pf_kstate **sm,
 	return (action);
 
 cleanup:
-	while ((ri = SLIST_FIRST(&ctx.rules))) {
-		SLIST_REMOVE_HEAD(&ctx.rules, entry);
-		free(ri, M_PF_RULE_ITEM);
-	}
-
 	uma_zfree(V_pf_state_key_z, ctx.sk);
 	uma_zfree(V_pf_state_key_z, ctx.nk);
 	pf_udp_mapping_release(ctx.udp_mapping);
@@ -6126,7 +6136,8 @@ cleanup:
 
 static int
 pf_create_state(struct pf_krule *r, struct pf_test_ctx *ctx,
-    struct pf_kstate **sm, u_int16_t bproto_sum, u_int16_t bip_sum)
+    struct pf_kstate **sm, u_int16_t bproto_sum, u_int16_t bip_sum,
+    struct pf_krule_slist *match_rules)
 {
 	struct pf_pdesc		*pd = ctx->pd;
 	struct pf_kstate	*s = NULL;
@@ -6140,7 +6151,6 @@ pf_create_state(struct pf_krule *r, struct pf_test_ctx *ctx,
 	struct tcphdr		*th = &pd->hdr.tcp;
 	u_int16_t		 mss = V_tcp_mssdflt;
 	u_short			 sn_reason;
-	struct pf_krule_item	*ri;
 
 	/* check maximums */
 	if (r->max_states &&
@@ -6192,7 +6202,7 @@ pf_create_state(struct pf_krule *r, struct pf_test_ctx *ctx,
 	s->rule = r;
 	s->nat_rule = ctx->nr;
 	s->anchor = ctx->a;
-	memcpy(&s->match_rules, &ctx->rules, sizeof(s->match_rules));
+	s->match_rules = *match_rules;
 	memcpy(&s->act, &pd->act, sizeof(struct pf_rule_actions));
 
 	if (pd->act.allow_opts)
@@ -6356,11 +6366,6 @@ pf_create_state(struct pf_krule *r, struct pf_test_ctx *ctx,
 	return (PF_PASS);
 
 csfailed:
-	while ((ri = SLIST_FIRST(&ctx->rules))) {
-		SLIST_REMOVE_HEAD(&ctx->rules, entry);
-		free(ri, M_PF_RULE_ITEM);
-	}
-
 	uma_zfree(V_pf_state_key_z, ctx->sk);
 	uma_zfree(V_pf_state_key_z, ctx->nk);
 
@@ -7518,6 +7523,7 @@ static void
 pf_sctp_multihome_delayed(struct pf_pdesc *pd, struct pfi_kkif *kif,
     struct pf_kstate *s, int action)
 {
+	struct pf_krule_slist		 match_rules;
 	struct pf_sctp_multihome_job	*j, *tmp;
 	struct pf_sctp_source		*i;
 	int			 ret;
@@ -7565,8 +7571,14 @@ again:
 			if (s->rule->rule_flag & PFRULE_ALLOW_RELATED) {
 				j->pd.related_rule = s->rule;
 			}
+			SLIST_INIT(&match_rules);
 			ret = pf_test_rule(&r, &sm,
-			    &j->pd, &ra, &rs, &reason, NULL);
+			    &j->pd, &ra, &rs, &reason, NULL, &match_rules);
+			/*
+			 * Nothing to do about match rules, the processed
+			 * packet has already increased the counters.
+			 */
+			pf_free_match_rules(&match_rules);
 			PF_RULES_RUNLOCK();
 			SDT_PROBE4(pf, sctp, multihome, test, kif, r, j->pd.m, ret);
 			if (ret != PF_DROP && sm != NULL) {
@@ -7627,6 +7639,7 @@ again:
 				nj->pd.m = j->pd.m;
 				nj->op = j->op;
 
+				MPASS(nj->pd.pcksum);
 				TAILQ_INSERT_TAIL(&pd->sctp_multihome_jobs, nj, next);
 			}
 			PF_SCTP_ENDPOINTS_UNLOCK();
@@ -7746,6 +7759,7 @@ pf_multihome_scan(int start, int len, struct pf_pdesc *pd, int op)
 			job->pd.m = pd->m;
 			job->op = op;
 
+			MPASS(job->pd.pcksum);
 			TAILQ_INSERT_TAIL(&pd->sctp_multihome_jobs, job, next);
 			break;
 		}
@@ -7779,6 +7793,7 @@ pf_multihome_scan(int start, int len, struct pf_pdesc *pd, int op)
 			job->pd.m = pd->m;
 			job->op = op;
 
+			MPASS(job->pd.pcksum);
 			TAILQ_INSERT_TAIL(&pd->sctp_multihome_jobs, job, next);
 			break;
 		}
@@ -9221,28 +9236,41 @@ pf_route(struct pf_krule *r, struct ifnet *oifp,
 		}
 	}
 
-	if (r->rt == PF_DUPTO)
+	if (r->rt == PF_DUPTO || (pd->af != pd->naf && s->direction == PF_IN))
 		skip_test = true;
 
-	if (pd->dir == PF_IN && !skip_test) {
-		if (pf_test(AF_INET, PF_OUT, PFIL_FWD, ifp, &m0, inp,
-		    &pd->act) != PF_PASS) {
-			action = PF_DROP;
-			SDT_PROBE1(pf, ip, route_to, drop, __LINE__);
-			goto bad;
-		} else if (m0 == NULL) {
-			action = PF_DROP;
-			SDT_PROBE1(pf, ip, route_to, drop, __LINE__);
-			goto done;
-		}
-		if (m0->m_len < sizeof(struct ip)) {
-			DPFPRINTF(PF_DEBUG_URGENT,
-			    "%s: m0->m_len < sizeof(struct ip)", __func__);
-			SDT_PROBE1(pf, ip, route_to, drop, __LINE__);
-			action = PF_DROP;
-			goto bad;
+	if (pd->dir == PF_IN) {
+		if (skip_test) {
+			struct pfi_kkif *out_kif = (struct pfi_kkif *)ifp->if_pf_kif;
+			MPASS(s != NULL);
+			pf_counter_u64_critical_enter();
+			pf_counter_u64_add_protected(
+			    &out_kif->pfik_bytes[pd->naf == AF_INET6][1]
+			    [action != PF_PASS && action != PF_AFRT], pd->tot_len);
+			pf_counter_u64_add_protected(
+			    &out_kif->pfik_packets[pd->naf == AF_INET6][1]
+			    [action != PF_PASS && action != PF_AFRT], 1);
+			pf_counter_u64_critical_exit();
+		} else {
+			if (pf_test(AF_INET, PF_OUT, PFIL_FWD, ifp, &m0, inp,
+			    &pd->act) != PF_PASS) {
+				action = PF_DROP;
+				SDT_PROBE1(pf, ip, route_to, drop, __LINE__);
+				goto bad;
+			} else if (m0 == NULL) {
+				action = PF_DROP;
+				SDT_PROBE1(pf, ip, route_to, drop, __LINE__);
+				goto done;
+			}
+			if (m0->m_len < sizeof(struct ip)) {
+				DPFPRINTF(PF_DEBUG_URGENT,
+				    "%s: m0->m_len < sizeof(struct ip)", __func__);
+				SDT_PROBE1(pf, ip, route_to, drop, __LINE__);
+				action = PF_DROP;
+				goto bad;
+			}
+			ip = mtod(m0, struct ip *);
 		}
-		ip = mtod(m0, struct ip *);
 	}
 
 	if (ifp->if_flags & IFF_LOOPBACK)
@@ -9538,29 +9566,42 @@ pf_route6(struct pf_krule *r, struct ifnet *oifp,
 		}
 	}
 
-	if (r->rt == PF_DUPTO)
+	if (r->rt == PF_DUPTO || (pd->af != pd->naf && s->direction == PF_IN))
 		skip_test = true;
 
-	if (pd->dir == PF_IN && !skip_test) {
-		if (pf_test(AF_INET6, PF_OUT, PFIL_FWD | PF_PFIL_NOREFRAGMENT,
-		    ifp, &m0, inp, &pd->act) != PF_PASS) {
-			action = PF_DROP;
-			SDT_PROBE1(pf, ip6, route_to, drop, __LINE__);
-			goto bad;
-		} else if (m0 == NULL) {
-			action = PF_DROP;
-			SDT_PROBE1(pf, ip6, route_to, drop, __LINE__);
-			goto done;
-		}
-		if (m0->m_len < sizeof(struct ip6_hdr)) {
-			DPFPRINTF(PF_DEBUG_URGENT,
-			    "%s: m0->m_len < sizeof(struct ip6_hdr)",
-			    __func__);
-			action = PF_DROP;
-			SDT_PROBE1(pf, ip6, route_to, drop, __LINE__);
-			goto bad;
+	if (pd->dir == PF_IN) {
+		if (skip_test) {
+			struct pfi_kkif *out_kif = (struct pfi_kkif *)ifp->if_pf_kif;
+			MPASS(s != NULL);
+			pf_counter_u64_critical_enter();
+			pf_counter_u64_add_protected(
+			    &out_kif->pfik_bytes[pd->naf == AF_INET6][1]
+			    [action != PF_PASS && action != PF_AFRT], pd->tot_len);
+			pf_counter_u64_add_protected(
+			    &out_kif->pfik_packets[pd->naf == AF_INET6][1]
+			    [action != PF_PASS && action != PF_AFRT], 1);
+			pf_counter_u64_critical_exit();
+		} else {
+			if (pf_test(AF_INET6, PF_OUT, PFIL_FWD | PF_PFIL_NOREFRAGMENT,
+			    ifp, &m0, inp, &pd->act) != PF_PASS) {
+				action = PF_DROP;
+				SDT_PROBE1(pf, ip6, route_to, drop, __LINE__);
+				goto bad;
+			} else if (m0 == NULL) {
+				action = PF_DROP;
+				SDT_PROBE1(pf, ip6, route_to, drop, __LINE__);
+				goto done;
+			}
+			if (m0->m_len < sizeof(struct ip6_hdr)) {
+				DPFPRINTF(PF_DEBUG_URGENT,
+				    "%s: m0->m_len < sizeof(struct ip6_hdr)",
+				    __func__);
+				action = PF_DROP;
+				SDT_PROBE1(pf, ip6, route_to, drop, __LINE__);
+				goto bad;
+			}
+			ip6 = mtod(m0, struct ip6_hdr *);
 		}
-		ip6 = mtod(m0, struct ip6_hdr *);
 	}
 
 	if (ifp->if_flags & IFF_LOOPBACK)
@@ -10410,28 +10451,28 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			    __func__);
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 
 		h = mtod(pd->m, struct ip *);
 		if (pd->m->m_pkthdr.len < ntohs(h->ip_len)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 
 		if (pf_normalize_ip(reason, pd) != PF_PASS) {
 			/* We do IP header normalization and packet reassembly here */
 			*m0 = pd->m;
 			*action = PF_DROP;
-			return (-1);
+			return (PF_DROP);
 		}
 		*m0 = pd->m;
 		h = mtod(pd->m, struct ip *);
 
 		if (pf_walk_header(pd, h, reason) != PF_PASS) {
 			*action = PF_DROP;
-			return (-1);
+			return (PF_DROP);
 		}
 
 		pd->src = (struct pf_addr *)&h->ip_src;
@@ -10461,7 +10502,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			     ", pullup failed", __func__);
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 
 		h = mtod(pd->m, struct ip6_hdr *);
@@ -10469,7 +10510,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 		    sizeof(struct ip6_hdr) + ntohs(h->ip6_plen)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 
 		/*
@@ -10478,12 +10519,12 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 		 */
 		if (htons(h->ip6_plen) == 0) {
 			*action = PF_DROP;
-			return (-1);
+			return (PF_DROP);
 		}
 
 		if (pf_walk_header6(pd, h, reason) != PF_PASS) {
 			*action = PF_DROP;
-			return (-1);
+			return (PF_DROP);
 		}
 
 		h = mtod(pd->m, struct ip6_hdr *);
@@ -10505,13 +10546,13 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 		    PF_PASS) {
 			*m0 = pd->m;
 			*action = PF_DROP;
-			return (-1);
+			return (PF_DROP);
 		}
 		*m0 = pd->m;
 		if (pd->m == NULL) {
 			/* packet sits in reassembly queue, no error */
 			*action = PF_PASS;
-			return (-1);
+			return (PF_DROP);
 		}
 
 		/* Update pointers into the packet. */
@@ -10523,7 +10564,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 
 		if (pf_walk_header6(pd, h, reason) != PF_PASS) {
 			*action = PF_DROP;
-			return (-1);
+			return (PF_DROP);
 		}
 
 		if (m_tag_find(pd->m, PACKET_TAG_PF_REASSEMBLED, NULL) != NULL) {
@@ -10553,7 +10594,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			reason, af)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		pd->hdrlen = sizeof(*th);
 		pd->p_len = pd->tot_len - pd->off - (th->th_off << 2);
@@ -10569,7 +10610,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			reason, af)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		pd->hdrlen = sizeof(*uh);
 		if (uh->uh_dport == 0 ||
@@ -10577,7 +10618,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 		    ntohs(uh->uh_ulen) < sizeof(struct udphdr)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		pd->sport = &uh->uh_sport;
 		pd->dport = &uh->uh_dport;
@@ -10589,7 +10630,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 		    reason, af)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		pd->hdrlen = sizeof(pd->hdr.sctp);
 		pd->p_len = pd->tot_len - pd->off;
@@ -10599,19 +10640,23 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 		if (pd->hdr.sctp.src_port == 0 || pd->hdr.sctp.dest_port == 0) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
-		}
-		if (pf_scan_sctp(pd) != PF_PASS) {
-			*action = PF_DROP;
-			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
+
 		/*
 		 * Placeholder. The SCTP checksum is 32-bits, but
 		 * pf_test_state() expects to update a 16-bit checksum.
 		 * Provide a dummy value which we'll subsequently ignore.
+		 * Do this before pf_scan_sctp() so any jobs we enqueue
+		 * have a pcksum set.
 		 */
 		pd->pcksum = &pd->sctp_dummy_sum;
+
+		if (pf_scan_sctp(pd) != PF_PASS) {
+			*action = PF_DROP;
+			REASON_SET(reason, PFRES_SHORT);
+			return (PF_DROP);
+		}
 		break;
 	}
 	case IPPROTO_ICMP: {
@@ -10619,7 +10664,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			reason, af)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		pd->pcksum = &pd->hdr.icmp.icmp_cksum;
 		pd->hdrlen = ICMP_MINLEN;
@@ -10633,7 +10678,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			reason, af)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		/* ICMP headers we look further into to match state */
 		switch (pd->hdr.icmp6.icmp6_type) {
@@ -10659,7 +10704,7 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 			reason, af)) {
 			*action = PF_DROP;
 			REASON_SET(reason, PFRES_SHORT);
-			return (-1);
+			return (PF_DROP);
 		}
 		pd->hdrlen = icmp_hlen;
 		pd->pcksum = &pd->hdr.icmp6.icmp6_cksum;
@@ -10682,111 +10727,173 @@ pf_setup_pdesc(sa_family_t af, int dir, struct pf_pdesc *pd, struct mbuf **m0,
 
 	MPASS(pd->pcksum != NULL);
 
-	return (0);
+	return (PF_PASS);
+}
+
+static __inline void
+pf_rule_counters_inc(struct pf_pdesc *pd, struct pf_krule *r, int dir_out,
+    int op_pass, sa_family_t af, struct pf_addr *src_host,
+    struct pf_addr *dst_host)
+{
+	pf_counter_u64_add_protected(&(r->packets[dir_out]), 1);
+	pf_counter_u64_add_protected(&(r->bytes[dir_out]), pd->tot_len);
+	pf_update_timestamp(r);
+
+	if (r->src.addr.type == PF_ADDR_TABLE)
+		pfr_update_stats(r->src.addr.p.tbl, src_host, af,
+		    pd->tot_len, dir_out, op_pass, r->src.neg);
+	if (r->dst.addr.type == PF_ADDR_TABLE)
+		pfr_update_stats(r->dst.addr.p.tbl, dst_host, af,
+		    pd->tot_len, dir_out, op_pass, r->dst.neg);
 }
 
 static void
-pf_counters_inc(int action, struct pf_pdesc *pd,
-    struct pf_kstate *s, struct pf_krule *r, struct pf_krule *a)
+pf_counters_inc(int action, struct pf_pdesc *pd, struct pf_kstate *s,
+    struct pf_krule *r, struct pf_krule *a, struct pf_krule_slist *match_rules)
 {
-	struct pf_krule		*tr;
-	int			 dir = pd->dir;
-	int			 dirndx;
+	struct pf_krule_slist	*mr = match_rules;
+	struct pf_krule_item	*ri;
+	struct pf_krule		*nr = NULL;
+	struct pf_addr		*src_host = pd->src;
+	struct pf_addr		*dst_host = pd->dst;
+	struct pf_state_key	*key;
+	int			 dir_out = (pd->dir == PF_OUT);
+	int			 op_r_pass = (r->action == PF_PASS);
+	int			 op_pass = (action == PF_PASS || action == PF_AFRT);
+	int			 s_dir_in, s_dir_out, s_dir_rev;
+	sa_family_t		 af = pd->af;
 
 	pf_counter_u64_critical_enter();
+
+	/*
+	 * Set AF for interface counters, it will be later overwritten for
+	 * rule and state counters with value from proper state key.
+	 */
+	if (action == PF_AFRT) {
+		MPASS(s != NULL);
+		if (s->direction == PF_OUT && dir_out)
+			af = pd->naf;
+	}
+
 	pf_counter_u64_add_protected(
-	    &pd->kif->pfik_bytes[pd->af == AF_INET6][dir == PF_OUT][action != PF_PASS],
+	    &pd->kif->pfik_bytes[af == AF_INET6][dir_out][!op_pass],
 	    pd->tot_len);
 	pf_counter_u64_add_protected(
-	    &pd->kif->pfik_packets[pd->af == AF_INET6][dir == PF_OUT][action != PF_PASS],
+	    &pd->kif->pfik_packets[af == AF_INET6][dir_out][!op_pass],
 	    1);
 
-	if (action == PF_PASS || action == PF_AFRT || r->action == PF_DROP) {
-		dirndx = (dir == PF_OUT);
-		pf_counter_u64_add_protected(&r->packets[dirndx], 1);
-		pf_counter_u64_add_protected(&r->bytes[dirndx], pd->tot_len);
-		pf_update_timestamp(r);
+	/* If the rule has failed to apply, don't increase its counters */
+	if (!(op_pass || r->action == PF_DROP)) {
+		pf_counter_u64_critical_exit();
+		return;
+	}
+
+	if (s != NULL) {
+		PF_STATE_LOCK_ASSERT(s);
+		mr = &(s->match_rules);
 
-		if (a != NULL) {
-			pf_counter_u64_add_protected(&a->packets[dirndx], 1);
-			pf_counter_u64_add_protected(&a->bytes[dirndx], pd->tot_len);
+		/*
+		 * For af-to on the inbound direction we can determine
+		 * the direction of passing packet only by checking direction
+		 * of AF translation. The af-to in "in" direction covers both
+		 * the inbound and the outbound side of state tracking,
+		 * so pd->dir is always PF_IN. We set dir_out and s_dir_rev
+		 * in a way to count packets as if the state was outbound,
+		 * because pfctl -ss shows the state with "->", as if it was
+		 * oubound.
+		 */
+		if (action == PF_AFRT && s->direction == PF_IN) {
+			dir_out = (pd->naf == s->rule->naf);
+			s_dir_in = 1;
+			s_dir_out = 0;
+			s_dir_rev = (pd->naf == s->rule->af);
+		} else {
+			dir_out = (pd->dir == PF_OUT);
+			s_dir_in = (s->direction == PF_IN);
+			s_dir_out = (s->direction == PF_OUT);
+			s_dir_rev = (pd->dir != s->direction);
 		}
-		if (s != NULL) {
-			struct pf_krule_item	*ri;
 
-			if (s->nat_rule != NULL) {
-				pf_counter_u64_add_protected(&s->nat_rule->packets[dirndx],
+		/* pd->tot_len is a problematic with af-to rules. Sure, we can
+		 * agree that it's the post-af-to packet length that was
+		 * forwarded through a state, but what about tables which match
+		 * on pre-af-to addresses? We don't have access the the original
+		 * packet length anymore.
+		 */
+		s->packets[s_dir_rev]++;
+		s->bytes[s_dir_rev] += pd->tot_len;
+
+		/*
+		 * Source nodes are accessed unlocked here. But since we are
+		 * operating with stateful tracking and the state is locked,
+		 * those SNs could not have been freed.
+		 */
+		for (pf_sn_types_t sn_type=0; sn_type<PF_SN_MAX; sn_type++) {
+			if (s->sns[sn_type] != NULL) {
+				counter_u64_add(
+				    s->sns[sn_type]->packets[dir_out],
 				    1);
-				pf_counter_u64_add_protected(&s->nat_rule->bytes[dirndx],
+				counter_u64_add(
+				    s->sns[sn_type]->bytes[dir_out],
 				    pd->tot_len);
 			}
-			/*
-			 * Source nodes are accessed unlocked here.
-			 * But since we are operating with stateful tracking
-			 * and the state is locked, those SNs could not have
-			 * been freed.
-			 */
-			for (pf_sn_types_t sn_type=0; sn_type<PF_SN_MAX; sn_type++) {
-				if (s->sns[sn_type] != NULL) {
-					counter_u64_add(
-					    s->sns[sn_type]->packets[dirndx],
-					    1);
-					counter_u64_add(
-					    s->sns[sn_type]->bytes[dirndx],
-					    pd->tot_len);
-				}
-			}
-			dirndx = (dir == s->direction) ? 0 : 1;
-			s->packets[dirndx]++;
-			s->bytes[dirndx] += pd->tot_len;
-
-			SLIST_FOREACH(ri, &s->match_rules, entry) {
-				pf_counter_u64_add_protected(&ri->r->packets[dirndx], 1);
-				pf_counter_u64_add_protected(&ri->r->bytes[dirndx], pd->tot_len);
+		}
 
-				if (ri->r->src.addr.type == PF_ADDR_TABLE)
-					pfr_update_stats(ri->r->src.addr.p.tbl,
-					    (s == NULL) ? pd->src :
-					    &s->key[(s->direction == PF_IN)]->
-						addr[(s->direction == PF_OUT)],
-					    pd->af, pd->tot_len, dir == PF_OUT,
-					    r->action == PF_PASS, ri->r->src.neg);
-				if (ri->r->dst.addr.type == PF_ADDR_TABLE)
-					pfr_update_stats(ri->r->dst.addr.p.tbl,
-					    (s == NULL) ? pd->dst :
-					    &s->key[(s->direction == PF_IN)]->
-						addr[(s->direction == PF_IN)],
-					    pd->af, pd->tot_len, dir == PF_OUT,
-					    r->action == PF_PASS, ri->r->dst.neg);
+		/* Start with pre-NAT addresses */
+		key = s->key[(s->direction == PF_OUT)];
+		src_host = &(key->addr[s_dir_out]);
+		dst_host = &(key->addr[s_dir_in]);
+		af = key->af;
+		if (s->nat_rule) {
+			/* Old-style NAT rules */
+			if (s->nat_rule->action == PF_NAT ||
+			    s->nat_rule->action == PF_RDR ||
+			    s->nat_rule->action == PF_BINAT) {
+				nr = s->nat_rule;
+				pf_rule_counters_inc(pd, s->nat_rule, dir_out,
+				    op_r_pass, af, src_host, dst_host);
+				/* Use post-NAT addresses from now on */
+				key = s->key[s_dir_in];
+				src_host = &(key->addr[s_dir_out]);
+				dst_host = &(key->addr[s_dir_in]);
+				af = key->af;
 			}
 		}
+	}
 
-		tr = r;
-		if (s != NULL && s->nat_rule != NULL &&
-		    r == &V_pf_default_rule)
-			tr = s->nat_rule;
-
-		if (tr->src.addr.type == PF_ADDR_TABLE)
-			pfr_update_stats(tr->src.addr.p.tbl,
-			    (s == NULL) ? pd->src :
-			    &s->key[(s->direction == PF_IN)]->
-				addr[(s->direction == PF_OUT)],
-			    pd->af, pd->tot_len, dir == PF_OUT,
-			    r->action == PF_PASS, tr->src.neg);
-		if (tr->dst.addr.type == PF_ADDR_TABLE)
-			pfr_update_stats(tr->dst.addr.p.tbl,
-			    (s == NULL) ? pd->dst :
-			    &s->key[(s->direction == PF_IN)]->
-				addr[(s->direction == PF_IN)],
-			    pd->af, pd->tot_len, dir == PF_OUT,
-			    r->action == PF_PASS, tr->dst.neg);
+	SLIST_FOREACH(ri, mr, entry) {
+		pf_rule_counters_inc(pd, ri->r, dir_out, op_r_pass, af,
+		    src_host, dst_host);
+		if (s && s->nat_rule == ri->r) {
+			/* Use post-NAT addresses after a match NAT rule */
+			key = s->key[s_dir_in];
+			src_host = &(key->addr[s_dir_out]);
+			dst_host = &(key->addr[s_dir_in]);
+			af = key->af;
+		}
 	}
+
+	if (s == NULL) {
+		pf_free_match_rules(mr);
+	}
+
+	if (a != NULL) {
+		pf_rule_counters_inc(pd, a, dir_out, op_r_pass, af,
+		    src_host, dst_host);
+	}
+
+	if (r != nr) {
+		pf_rule_counters_inc(pd, r, dir_out, op_r_pass, af,
+		    src_host, dst_host);
+	}
+
 	pf_counter_u64_critical_exit();
 }
+
 static void
 pf_log_matches(struct pf_pdesc *pd, struct pf_krule *rm,
     struct pf_krule *am, struct pf_kruleset *ruleset,
-    struct pf_krule_slist *matchrules)
+    struct pf_krule_slist *match_rules)
 {
 	struct pf_krule_item	*ri;
 
@@ -10794,7 +10901,7 @@ pf_log_matches(struct pf_pdesc *pd, struct pf_krule *rm,
 	if (rm->log & PF_LOG_MATCHES)
 		return;
 
-	SLIST_FOREACH(ri, matchrules, entry)
+	SLIST_FOREACH(ri, match_rules, entry)
 		if (ri->r->log & PF_LOG_MATCHES)
 			PFLOG_PACKET(rm->action, PFRES_MATCH, rm, am,
 			    ruleset, pd, 1, ri->r);
@@ -10811,6 +10918,8 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 	struct pf_krule		*a = NULL, *r = &V_pf_default_rule;
 	struct pf_kstate	*s = NULL;
 	struct pf_kruleset	*ruleset = NULL;
+	struct pf_krule_item	*ri;
+	struct pf_krule_slist	 match_rules;
 	struct pf_pdesc		 pd;
 	int			 use_2nd_queue = 0;
 	uint16_t		 tag;
@@ -10847,6 +10956,7 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 	}
 
 	pf_init_pdesc(&pd, *m0);
+	SLIST_INIT(&match_rules);
 
 	if (pd.pf_mtag != NULL && (pd.pf_mtag->flags & PF_MTAG_FLAG_ROUTE_TO)) {
 		pd.pf_mtag->flags &= ~PF_MTAG_FLAG_ROUTE_TO;
@@ -10879,7 +10989,7 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 	PF_RULES_RLOCK();
 
 	if (pf_setup_pdesc(af, dir, &pd, m0, &action, &reason,
-		kif, default_actions) == -1) {
+		kif, default_actions) != PF_PASS) {
 		if (action != PF_PASS)
 			pd.act.log |= PF_LOG_FORCE;
 		goto done;
@@ -10943,7 +11053,7 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 			action = PF_DROP;
 		else
 			action = pf_test_rule(&r, &s, &pd, &a,
-			    &ruleset, &reason, inp);
+			    &ruleset, &reason, inp, &match_rules);
 		if (action != PF_PASS)
 			REASON_SET(&reason, PFRES_FRAG);
 		break;
@@ -11001,7 +11111,7 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 				break;
 			} else {
 				action = pf_test_rule(&r, &s, &pd,
-				    &a, &ruleset, &reason, inp);
+				    &a, &ruleset, &reason, inp, &match_rules);
 			}
 		}
 		break;
@@ -11022,7 +11132,7 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 			a = s->anchor;
 		} else if (s == NULL) {
 			action = pf_test_rule(&r, &s,
-			    &pd, &a, &ruleset, &reason, inp);
+			    &pd, &a, &ruleset, &reason, inp, &match_rules);
 		}
 		break;
 
@@ -11050,7 +11160,7 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 			a = s->anchor;
 		} else if (s == NULL)
 			action = pf_test_rule(&r, &s, &pd,
-			    &a, &ruleset, &reason, inp);
+			    &a, &ruleset, &reason, inp, &match_rules);
 		break;
 	}
 
@@ -11059,8 +11169,11 @@ pf_test(sa_family_t af, int dir, int pflags, struct ifnet *ifp, struct mbuf **m0
 done:
 	PF_RULES_RUNLOCK();
 
-	if (pd.m == NULL)
+	/* if packet sits in reassembly queue, return without error */
+	if (pd.m == NULL) {
+		pf_free_match_rules(&match_rules);
 		goto eat_pkt;
+	}
 
 	if (s)
 		memcpy(&pd.act, &s->act, sizeof(s->act));
@@ -11157,6 +11270,8 @@ done:
 			    (dir == PF_IN) ? PF_DIVERT_MTAG_DIR_IN :
 			    PF_DIVERT_MTAG_DIR_OUT;
 
+			pf_counters_inc(action, &pd, s, r, a, &match_rules);
+
 			if (s)
 				PF_STATE_UNLOCK(s);
 
@@ -11198,7 +11313,6 @@ done:
 
 	if (pd.act.log) {
 		struct pf_krule		*lr;
-		struct pf_krule_item	*ri;
 
 		if (s != NULL && s->nat_rule != NULL &&
 		    s->nat_rule->log & PF_LOG_ALL)
@@ -11217,7 +11331,7 @@ done:
 		}
 	}
 
-	pf_counters_inc(action, &pd, s, r, a);
+	pf_counters_inc(action, &pd, s, r, a, &match_rules);
 
 	switch (action) {
 	case PF_SYNPROXY_DROP:
diff --git a/sys/netpfil/pf/pf_lb.c b/sys/netpfil/pf/pf_lb.c
index b8b5157c9b15..fb1b121d0bc0 100644
--- a/sys/netpfil/pf/pf_lb.c
+++ b/sys/netpfil/pf/pf_lb.c
@@ -73,7 +73,7 @@ VNET_DEFINE_STATIC(int, pf_rdr_srcport_rewrite_tries) = 16;
 
 static uint64_t		 pf_hash(struct pf_addr *, struct pf_addr *,
 			    struct pf_poolhashkey *, sa_family_t);
-struct pf_krule		*pf_match_translation(int, struct pf_test_ctx *);
+static struct pf_krule	*pf_match_translation(int, struct pf_test_ctx *);
 static enum pf_test_status pf_step_into_translation_anchor(int, struct pf_test_ctx *,
 			    struct pf_krule *);
 static int		 pf_get_sport(struct pf_pdesc *, struct pf_krule *,
@@ -273,7 +273,7 @@ pf_step_into_translation_anchor(int rs_num, struct pf_test_ctx *ctx, struct pf_k
 	return (rv);
 }
 
-struct pf_krule *
+static struct pf_krule *
 pf_match_translation(int rs_num, struct pf_test_ctx *ctx)
 {
 	enum pf_test_status rv;
diff --git a/sys/security/mac_do/mac_do.c b/sys/security/mac_do/mac_do.c
index 6f3e63d06198..2bcff7bba973 100644
--- a/sys/security/mac_do/mac_do.c
+++ b/sys/security/mac_do/mac_do.c
@@ -1992,6 +1992,10 @@ check_proc(void)
 	/*
 	 * Only grant privileges if requested by the right executable.
 	 *
+	 * As MAC/do configuration is per-jail, in order to avoid confused
+	 * deputy situations in chroots (privileged or unprivileged), make sure
+	 * to check the path from the current jail's root.
+	 *
 	 * XXXOC: We may want to base this check on a tunable path and/or
 	 * a specific MAC label.  Going even further, e.g., envisioning to
 	 * completely replace the path check with the latter, we would need to
@@ -2003,7 +2007,7 @@ check_proc(void)
 	 * setting a MAC label per file (perhaps via additions to mtree(1)).  So
 	 * this probably isn't going to happen overnight, if ever.
 	 */
-	if (vn_fullpath(curproc->p_textvp, &path, &to_free) != 0)
+	if (vn_fullpath_jail(curproc->p_textvp, &path, &to_free) != 0)
 		return (EPERM);
 	error = strcmp(path, "/usr/bin/mdo") == 0 ? 0 : EPERM;
 	free(to_free, M_TEMP);
diff --git a/sys/sys/eventhandler.h b/sys/sys/eventhandler.h
index c0d9811dd1b9..29a16b393b52 100644
--- a/sys/sys/eventhandler.h
+++ b/sys/sys/eventhandler.h
@@ -33,6 +33,7 @@
 #include <sys/lock.h>
 #include <sys/ktr.h>
 #include <sys/mutex.h>
+#include <sys/power.h>
 #include <sys/queue.h>
 
 #ifdef VIMAGE
@@ -201,7 +202,7 @@ EVENTHANDLER_DECLARE(shutdown_post_sync, shutdown_fn);	/* after fs sync */
 EVENTHANDLER_DECLARE(shutdown_final, shutdown_fn);
 
 /* Power state change events */
-typedef void (*power_change_fn)(void *);
+typedef void (*power_change_fn)(void *, enum power_stype stype);
 EVENTHANDLER_DECLARE(power_resume, power_change_fn);
 EVENTHANDLER_DECLARE(power_suspend, power_change_fn);
 EVENTHANDLER_DECLARE(power_suspend_early, power_change_fn);
diff --git a/sys/sys/mutex.h b/sys/sys/mutex.h
index 08d4e2d28b33..4f6b45d78a88 100644
--- a/sys/sys/mutex.h
+++ b/sys/sys/mutex.h
@@ -68,9 +68,9 @@
  */
 #define	MTX_UNOWNED	0x00000000	/* Cookie for free mutex */
 #define	MTX_RECURSED	0x00000001	/* lock recursed (for MTX_DEF only) */
-#define	MTX_CONTESTED	0x00000002	/* lock contested (for MTX_DEF only) */
+#define	MTX_WAITERS	0x00000002	/* lock has waiters (for MTX_DEF only) */
 #define	MTX_DESTROYED	0x00000004	/* lock destroyed */
-#define	MTX_FLAGMASK	(MTX_RECURSED | MTX_CONTESTED | MTX_DESTROYED)
+#define	MTX_FLAGMASK	(MTX_RECURSED | MTX_WAITERS | MTX_DESTROYED)
 
 /*
  * Prototypes
@@ -217,14 +217,10 @@ void	_thread_lock(struct thread *);
 #define _mtx_obtain_lock_fetch(mp, vp, tid)				\
 	atomic_fcmpset_acq_ptr(&(mp)->mtx_lock, vp, (tid))
 
-/* Try to release mtx_lock if it is unrecursed and uncontested. */
+/* Try to release mtx_lock if it is unrecursed and without waiters. */
 #define _mtx_release_lock(mp, tid)					\
 	atomic_cmpset_rel_ptr(&(mp)->mtx_lock, (tid), MTX_UNOWNED)
 
-/* Release mtx_lock quickly, assuming we own it. */
-#define _mtx_release_lock_quick(mp)					\
-	atomic_store_rel_ptr(&(mp)->mtx_lock, MTX_UNOWNED)
-
 #define	_mtx_release_lock_fetch(mp, vp)					\
 	atomic_fcmpset_rel_ptr(&(mp)->mtx_lock, (vp), MTX_UNOWNED)
 
@@ -246,10 +242,10 @@ void	_thread_lock(struct thread *);
 })
 
 /*
- * Lock a spin mutex.  For spinlocks, we handle recursion inline (it
- * turns out that function calls can be significantly expensive on
- * some architectures).  Since spin locks are not _too_ common,
- * inlining this code is not too big a deal.
+ * Lock a spin mutex.
+ *
+ * FIXME: spinlock_enter is a function call, defeating the point of inlining in
+ * this.
  */
 #ifdef SMP
 #define __mtx_lock_spin(mp, tid, opts, file, line) __extension__ ({	\
@@ -317,10 +313,10 @@ void	_thread_lock(struct thread *);
 })
 
 /*
- * Unlock a spin mutex.  For spinlocks, we can handle everything
- * inline, as it's pretty simple and a function call would be too
- * expensive (at least on some architectures).  Since spin locks are
- * not _too_ common, inlining this code is not too big a deal.
+ * Unlock a spin mutex.
+ *
+ * FIXME: spinlock_exit is a function call, defeating the point of inlining in
+ * this.
  *
  * Since we always perform a spinlock_enter() when attempting to acquire a
  * spin lock, we need to always perform a matching spinlock_exit() when
@@ -332,7 +328,7 @@ void	_thread_lock(struct thread *);
 		(mp)->mtx_recurse--;					\
 	else {								\
 		LOCKSTAT_PROFILE_RELEASE_SPIN_LOCK(spin__release, mp);	\
-		_mtx_release_lock_quick((mp));				\
+		atomic_store_rel_ptr(&(mp)->mtx_lock, MTX_UNOWNED);	\
 	}								\
 	spinlock_exit();						\
 })
diff --git a/sys/sys/param.h b/sys/sys/param.h
index ce91430909ce..8a71693cff3d 100644
--- a/sys/sys/param.h
+++ b/sys/sys/param.h
@@ -74,7 +74,7 @@
  * cannot include sys/param.h and should only be updated here.
  */
 #undef __FreeBSD_version
-#define __FreeBSD_version 1600000
+#define __FreeBSD_version 1600001
 
 /*
  * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,
diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h
index 6d50583dc1b3..0bf438a1b821 100644
--- a/sys/sys/vnode.h
+++ b/sys/sys/vnode.h
@@ -714,6 +714,7 @@ int	speedup_syncer(void);
 int	vn_vptocnp(struct vnode **vp, char *buf, size_t *buflen);
 int	vn_getcwd(char *buf, char **retbuf, size_t *buflen);
 int	vn_fullpath(struct vnode *vp, char **retbuf, char **freebuf);
+int	vn_fullpath_jail(struct vnode *vp, char **retbuf, char **freebuf);
 int	vn_fullpath_global(struct vnode *vp, char **retbuf, char **freebuf);
 int	vn_fullpath_hardlink(struct vnode *vp, struct vnode *dvp,
 	    const char *hdrl_name, size_t hrdl_name_length, char **retbuf,
diff --git a/sys/tools/gdb/README.txt b/sys/tools/gdb/README.txt
new file mode 100644
index 000000000000..8c31565ddc42
--- /dev/null
+++ b/sys/tools/gdb/README.txt
@@ -0,0 +1,21 @@
+This directory contains Python scripts that can be loaded by GDB to help debug
+FreeBSD kernel crashes.
+
+Add new commands and functions in their own files.  Functions with general
+utility should be added to freebsd.py.  sys/tools/kernel-gdb.py is installed
+into the kernel debug directory (typically /usr/lib/debug/boot/kernel).  It will
+be automatically loaded by kgdb when opening a vmcore, so if you add new GDB
+commands or functions, that script should be updated to import them, and you
+should document them here.
+
+To provide some rudimentary testing, selftest.py tries to exercise all of the
+commands and functions defined here.  To use it, run selftest.sh to panic the
+system.  Then, create a kernel dump or attach to the panicked kernel, and invoke
+the script with "python import selftest" in (k)gdb.
+
+Commands:
+acttrace	Display a backtrace for all on-CPU threads
+
+Functions:
+$PCPU(<field>[, <cpuid>])	Display the value of a PCPU/DPCPU field
+$V(<variable>[, <vnet>])	Display the value of a VNET variable
diff --git a/libexec/kgdb/acttrace.py b/sys/tools/gdb/acttrace.py
index 3229ff708de1..147effbbddf1 100644
--- a/libexec/kgdb/acttrace.py
+++ b/sys/tools/gdb/acttrace.py
@@ -1,38 +1,23 @@
-#-
+#
 # Copyright (c) 2022 The FreeBSD Foundation
 #
 # This software was developed by Mark Johnston under sponsorship from the
 # FreeBSD Foundation.
 #
+# SPDX-License-Identifier: BSD-2-Clause
+#
 
 import gdb
-
-
-def symval(name):
-    return gdb.lookup_global_symbol(name).value()
-
-
-def tid_to_gdb_thread(tid):
-    for thread in gdb.inferiors()[0].threads():
-        if thread.ptid[2] == tid:
-            return thread
-    else:
-        return None
-
-
-def all_pcpus():
-    mp_maxid = symval("mp_maxid")
-    cpuid_to_pcpu = symval("cpuid_to_pcpu")
-
-    cpu = 0
-    while cpu <= mp_maxid:
-        pcpu = cpuid_to_pcpu[cpu]
-        if pcpu:
-            yield pcpu
-        cpu = cpu + 1
-
+from freebsd import *
+from pcpu import *
 
 class acttrace(gdb.Command):
+    """
+    Register an acttrace command with gdb.
+
+    When run, acttrace prints the stack trace of all threads that were on-CPU
+    at the time of the panic.
+    """
     def __init__(self):
         super(acttrace, self).__init__("acttrace", gdb.COMMAND_USER)
 
@@ -40,13 +25,13 @@ class acttrace(gdb.Command):
         # Save the current thread so that we can switch back after.
         curthread = gdb.selected_thread()
 
-        for pcpu in all_pcpus():
+        for pcpu in pcpu_foreach():
             td = pcpu['pc_curthread']
             tid = td['td_tid']
 
             gdb_thread = tid_to_gdb_thread(tid)
             if gdb_thread is None:
-                print("failed to find GDB thread with TID {}".format(tid))
+                raise gdb.error(f"failed to find GDB thread with TID {tid}")
             else:
                 gdb_thread.switch()
 
diff --git a/sys/tools/gdb/freebsd.py b/sys/tools/gdb/freebsd.py
new file mode 100644
index 000000000000..81ea60373348
--- /dev/null
+++ b/sys/tools/gdb/freebsd.py
@@ -0,0 +1,75 @@
+#
+# Copyright (c) 2025 Mark Johnston <markj@FreeBSD.org>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import gdb
+
+def symval(name):
+    sym = gdb.lookup_global_symbol(name)
+    if sym is None:
+        sym = gdb.lookup_static_symbol(name)
+        if sym is None:
+            raise gdb.GdbError(f"Symbol '{name}' not found")
+    return sym.value()
+
+
+def _queue_foreach(head, field, headf, nextf):
+    elm = head[headf]
+    while elm != 0:
+        yield elm
+        elm = elm[field][nextf]
+
+
+def list_foreach(head, field):
+    """sys/queue.h-style iterator."""
+    return _queue_foreach(head, field, "lh_first", "le_next")
+
+
+def tailq_foreach(head, field):
+    """sys/queue.h-style iterator."""
+    return _queue_foreach(head, field, "tqh_first", "tqe_next")
+
+
+def linker_file_foreach():
+    """Iterate over loaded linker files."""
+    return tailq_foreach(symval("linker_files"), "link")
+
+
+def pcpu_foreach():
+    mp_maxid = symval("mp_maxid")
+    cpuid_to_pcpu = symval("cpuid_to_pcpu")
+
+    cpu = 0
+    while cpu <= mp_maxid:
+        pcpu = cpuid_to_pcpu[cpu]
+        if pcpu:
+            yield pcpu
+        cpu = cpu + 1
+
+
+def tid_to_gdb_thread(tid):
+    """Convert a FreeBSD kernel thread ID to a gdb inferior thread."""
+    for thread in gdb.inferiors()[0].threads():
+        if thread.ptid[2] == tid:
+            return thread
+    else:
+        return None
+
+
+def tdfind(tid, pid=-1):
+    """Convert a FreeBSD kernel thread ID to a struct thread pointer."""
+    td = tdfind.cached_threads.get(int(tid))
+    if td:
+        return td
+
+    for p in list_foreach(symval("allproc"), "p_list"):
+        if pid != -1 and pid != p['p_pid']:
+            continue
+        for td in tailq_foreach(p['p_threads'], "td_plist"):
+            ntid = td['td_tid']
+            tdfind.cached_threads[int(ntid)] = td
+            if ntid == tid:
+                return td
+tdfind.cached_threads = dict()
diff --git a/sys/tools/gdb/pcpu.py b/sys/tools/gdb/pcpu.py
new file mode 100644
index 000000000000..aadc4b2d42df
--- /dev/null
+++ b/sys/tools/gdb/pcpu.py
@@ -0,0 +1,77 @@
+#
+# Copyright (c) 2025 Mark Johnston <markj@FreeBSD.org>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import gdb
+from freebsd import *
+
+class pcpu(gdb.Function):
+    """
+    Register a function to lookup PCPU and DPCPU variables by name.
+
+    To look up the value of the PCPU field foo on CPU n, use
+    $PCPU("foo", n).  This works for DPCPU fields too.  If the CPU ID is
+    omitted, and the currently selected thread is on-CPU, that CPU is
+    used, otherwise an error is raised.
+    """
+    def __init__(self):
+        super(pcpu, self).__init__("PCPU")
+
+    def invoke(self, field, cpuid=-1):
+        if cpuid == -1:
+            cpuid = tdfind(gdb.selected_thread().ptid[2])['td_oncpu']
+            if cpuid == -1:
+                raise gdb.error("Currently selected thread is off-CPU")
+            if cpuid < 0 or cpuid > symval("mp_maxid"):
+                raise gdb.error(f"Currently selected on invalid CPU {cpuid}")
+        pcpu = symval("cpuid_to_pcpu")[cpuid]
+
+        # Are we dealing with a PCPU or DPCPU field?
+        field = field.string()
+        for f in gdb.lookup_type("struct pcpu").fields():
+            if f.name == "pc_" + field:
+                return pcpu["pc_" + field]
+
+        def uintptr_t(val):
+            return val.cast(gdb.lookup_type("uintptr_t"))
+
+        # We're dealing with a DPCPU field.  This is handled similarly
+        # to VNET symbols, see vnet.py for comments.
+        pcpu_base = pcpu['pc_dynamic']
+        pcpu_entry = symval("pcpu_entry_" + field)
+        pcpu_entry_addr = uintptr_t(pcpu_entry.address)
+
+        for lf in linker_file_foreach():
+            block = gdb.block_for_pc(lf['ops']['cls']['methods'][0]['func'])
+            elf_file_t = gdb.lookup_type("elf_file_t", block).target()
+            ef = lf.cast(elf_file_t)
+
+            file_type = lf['ops']['cls']['name'].string()
+            if file_type == "elf64":
+                start = uintptr_t(ef['pcpu_start'])
+                if start == 0:
+                    continue
+                end = uintptr_t(ef['pcpu_stop'])
+                base = uintptr_t(ef['pcpu_base'])
+            elif file_type == "elf64_obj":
+                for i in range(ef['nprogtab']):
+                    pe = ef['progtab'][i]
+                    if pe['name'].string() == "set_pcpu":
+                        start = uintptr_t(pe['origaddr'])
+                        end = start + uintptr_t(pe['size'])
+                        base = uintptr_t(pe['addr'])
+                        break
+                else:
+                    continue
+            else:
+                path = lf['pathname'].string()
+                raise gdb.error(f"{path} has unexpected linker file type {file_type}")
+
+            if pcpu_entry_addr >= start and pcpu_entry_addr < end:
+                obj = gdb.Value(pcpu_base + pcpu_entry_addr - start + base)
+                return obj.cast(pcpu_entry.type.pointer()).dereference()
+
+# Register with gdb.
+pcpu()
diff --git a/sys/tools/gdb/selftest.py b/sys/tools/gdb/selftest.py
new file mode 100644
index 000000000000..41e9211c4bb3
--- /dev/null
+++ b/sys/tools/gdb/selftest.py
@@ -0,0 +1,31 @@
+#
+# Copyright (c) 2025 Mark Johnston <markj@FreeBSD.org>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import gdb
+
+cmds = ["acttrace",
+        "p $V(\"tcbinfo\")",
+        "p $V(\"tcbinfo\", vnet0)",
+        "p $V(\"pf_status\")",
+        "p $V(\"pf_status\", \"gdbselftest\")",
+        "p $PCPU(\"curthread\")",
+        "p $PCPU(\"curthread\", 0)",
+        "p/x $PCPU(\"hardclocktime\", 1)",
+        "p $PCPU(\"pqbatch\")[0][0]",
+        "p $PCPU(\"ss\", 1)",
+        ]
+
+for cmd in cmds:
+    try:
+        print(f"Running command: '{cmd}'")
+        gdb.execute(cmd)
+    except gdb.error as e:
+        print(f"Command '{cmd}' failed: {e}")
+        break
+
+# We didn't hit any unexpected errors.  This isn't as good as actually
+# verifying the output, but it's better than nothing.
+print("Everything seems OK")
diff --git a/sys/tools/gdb/selftest.sh b/sys/tools/gdb/selftest.sh
new file mode 100644
index 000000000000..252fae14af17
--- /dev/null
+++ b/sys/tools/gdb/selftest.sh
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2025 Mark Johnston <markj@FreeBSD.org>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+set -e
+
+n=$(sysctl -n hw.ncpu)
+if [ $n -lt 2 ]; then
+    echo "This test requires at least 2 CPUs"
+    exit 1
+fi
+
+# Set up some things expected by selftest.py.
+kldload -n pf siftr
+pfctl -e || true
+jail -c name=gdbselftest vnet persist
+
+echo "I'm about to panic your system, ctrl-C now if that's not what you want."
+sleep 10
+sysctl debug.debugger_on_panic=0
+sysctl debug.kdb.panic=1
diff --git a/sys/tools/gdb/vnet.py b/sys/tools/gdb/vnet.py
new file mode 100644
index 000000000000..36b4d512a3eb
--- /dev/null
+++ b/sys/tools/gdb/vnet.py
@@ -0,0 +1,100 @@
+#
+# Copyright (c) 2025 Mark Johnston <markj@FreeBSD.org>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import gdb
+import traceback
+from freebsd import *
+
+class vnet(gdb.Function):
+    """
+    Register a function to look up VNET variables by name.
+
+    To look at the value of a VNET variable V_foo, print $V("foo").  The
+    currently selected thread's VNET is used by default, but can be optionally
+    specified as a second parameter, e.g., $V("foo", <vnet>), where <vnet> is a
+    pointer to a struct vnet (e.g., vnet0 or allprison.tqh_first->pr_vnet) or a
+    string naming a jail.
+    """
+    def __init__(self):
+        super(vnet, self).__init__("V")
+
+    def invoke(self, sym, vnet=None):
+        sym = sym.string()
+        if sym.startswith("V_"):
+            sym = sym[len("V_"):]
+        if gdb.lookup_symbol("sysctl___kern_features_vimage")[0] is None:
+            return symval(sym)
+
+        # Look up the VNET's base address.
+        if vnet is None:
+            vnet = tdfind(gdb.selected_thread().ptid[2])['td_vnet']
+            if not vnet:
+                # If curthread->td_vnet == NULL, vnet0 is the current vnet.
+                vnet = symval("vnet0")
+        elif vnet.type.is_string_like:
+            vnet = vnet.string()
+            for prison in tailq_foreach(symval("allprison"), "pr_list"):
+                if prison['pr_name'].string() == vnet:
+                    vnet = prison['pr_vnet']
+                    break
+            else:
+                raise gdb.error(f"No prison named {vnet}")
+
+        def uintptr_t(val):
+            return val.cast(gdb.lookup_type("uintptr_t"))
+
+        # Now the tricky part: compute the address of the symbol relative
+        # to the selected VNET.  In the compiled kernel this is done at
+        # load time by applying a magic transformation to relocations
+        # against symbols in the vnet linker set.  Here we have to apply
+        # the transformation manually.
+        vnet_data_base = vnet['vnet_data_base']
+        vnet_entry = symval("vnet_entry_" + sym)
+        vnet_entry_addr = uintptr_t(vnet_entry.address)
+
+        # First, which kernel module does the symbol belong to?
+        for lf in linker_file_foreach():
+            # Find the bounds of this linker file's VNET linker set.  The
+            # struct containing the bounds depends on the type of the linker
+            # file, and unfortunately both are called elf_file_t.  So we use a
+            # PC value from the compilation unit (either link_elf.c or
+            # link_elf_obj.c) to disambiguate.
+            block = gdb.block_for_pc(lf['ops']['cls']['methods'][0]['func'])
+            elf_file_t = gdb.lookup_type("elf_file_t", block).target()
+            ef = lf.cast(elf_file_t)
+
+            file_type = lf['ops']['cls']['name'].string()
+            if file_type == "elf64":
+                start = uintptr_t(ef['vnet_start'])
+                if start == 0:
+                    # This linker file doesn't have a VNET linker set.
+                    continue
+                end = uintptr_t(ef['vnet_stop'])
+                base = uintptr_t(ef['vnet_base'])
+            elif file_type == "elf64_obj":
+                for i in range(ef['nprogtab']):
+                    pe = ef['progtab'][i]
+                    if pe['name'].string() == "set_vnet":
+                        start = uintptr_t(pe['origaddr'])
+                        end = start + uintptr_t(pe['size'])
+                        base = uintptr_t(pe['addr'])
+                        break
+                else:
+                    # This linker file doesn't have a VNET linker set.
+                    continue
+            else:
+                path = lf['pathname'].string()
+                raise gdb.error(f"{path} has unexpected linker file type {file_type}")
+
+            if vnet_entry_addr >= start and vnet_entry_addr < end:
+                # The symbol belongs to this linker file, so compute the final
+                # address.
+                obj = gdb.Value(vnet_data_base + vnet_entry_addr - start + base)
+                return obj.cast(vnet_entry.type.pointer()).dereference()
+
+
+# Register with gdb.
+vnet()
diff --git a/sys/tools/kernel-gdb.py b/sys/tools/kernel-gdb.py
new file mode 100644
index 000000000000..8a41ef6efab1
--- /dev/null
+++ b/sys/tools/kernel-gdb.py
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2025 Mark Johnston <markj@FreeBSD.org>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+import os
+import sys
+
+sys.path.append(os.path.join(os.path.dirname(__file__), "gdb"))
+
+# Import FreeBSD kernel debugging commands and modules below.
+import acttrace
+import pcpu
+import vnet
diff --git a/sys/ufs/ufs/ufs_vnops.c b/sys/ufs/ufs/ufs_vnops.c
index 0921eee92b9d..736c5a66267e 100644
--- a/sys/ufs/ufs/ufs_vnops.c
+++ b/sys/ufs/ufs/ufs_vnops.c
@@ -2592,8 +2592,12 @@ ufs_print(
 
 	printf("\tnlink=%d, effnlink=%d, size=%jd", ip->i_nlink,
 	    ip->i_effnlink, (intmax_t)ip->i_size);
-	if (I_IS_UFS2(ip))
-		printf(", extsize %d", ip->i_din2->di_extsize);
+	if (I_IS_UFS2(ip)) {
+		if (ip->i_din2 == NULL)
+			printf(", dinode=NULL (fields omitted)");
+		else
+			printf(", extsize=%d", ip->i_din2->di_extsize);
+	}
 	printf("\n\tgeneration=%jx, uid=%d, gid=%d, flags=0x%b\n",
 	    (uintmax_t)ip->i_gen, ip->i_uid, ip->i_gid,
 	    (uint32_t)ip->i_flags, PRINT_INODE_FLAGS);
diff --git a/sys/x86/include/mca.h b/sys/x86/include/mca.h
index 183480625f6d..553b5d765f17 100644
--- a/sys/x86/include/mca.h
+++ b/sys/x86/include/mca.h
@@ -44,6 +44,31 @@ struct mca_record {
 	int		mr_cpu;
 };
 
+enum mca_stat_types {
+	MCA_T_NONE = 0,
+	MCA_T_UNCLASSIFIED,
+	MCA_T_UCODE_ROM_PARITY,
+	MCA_T_EXTERNAL,
+	MCA_T_FRC,
+	MCA_T_INTERNAL_PARITY,
+	MCA_T_SMM_HANDLER,
+	MCA_T_INTERNAL_TIMER,
+	MCA_T_GENERIC_IO,
+	MCA_T_INTERNAL,
+	MCA_T_MEMORY,
+	MCA_T_TLB,
+	MCA_T_MEMCONTROLLER_GEN,
+	MCA_T_MEMCONTROLLER_RD,
+	MCA_T_MEMCONTROLLER_WR,
+	MCA_T_MEMCONTROLLER_AC,
+	MCA_T_MEMCONTROLLER_MS,
+	MCA_T_MEMCONTROLLER_OTHER,
+	MCA_T_CACHE,
+	MCA_T_BUS,
+	MCA_T_UNKNOWN,
+	MCA_T_COUNT /* Must stay last */
+};
+
 #ifdef _KERNEL
 
 void	cmc_intr(void);
diff --git a/sys/x86/x86/mca.c b/sys/x86/x86/mca.c
index 4ba49469d3a2..e43c88b3a27b 100644
--- a/sys/x86/x86/mca.c
+++ b/sys/x86/x86/mca.c
@@ -131,8 +131,16 @@ static STAILQ_HEAD(, mca_internal) mca_pending;
 static int mca_ticks = 300;
 static struct taskqueue *mca_tq;
 static struct task mca_resize_task;
+static struct task mca_postscan_task;
 static struct timeout_task mca_scan_task;
 static struct mtx mca_lock;
+static bool mca_startup_done = false;
+
+/* Statistics on number of MCA events by type, updated atomically. */
+static uint64_t mca_stats[MCA_T_COUNT];
+SYSCTL_OPAQUE(_hw_mca, OID_AUTO, stats, CTLFLAG_RD | CTLFLAG_SKIP,
+    mca_stats, MCA_T_COUNT * sizeof(mca_stats[0]),
+    "S", "Array of MCA events by type");
 
 static unsigned int
 mca_ia32_ctl_reg(int bank)
@@ -356,21 +364,27 @@ mca_error_request(uint16_t mca_error)
 }
 
 static const char *
-mca_error_mmtype(uint16_t mca_error)
+mca_error_mmtype(uint16_t mca_error, enum mca_stat_types *event_type)
 {
 
 	switch ((mca_error & 0x70) >> 4) {
 	case 0x0:
+		*event_type = MCA_T_MEMCONTROLLER_GEN;
 		return ("GEN");
 	case 0x1:
+		*event_type = MCA_T_MEMCONTROLLER_RD;
 		return ("RD");
 	case 0x2:
+		*event_type = MCA_T_MEMCONTROLLER_WR;
 		return ("WR");
 	case 0x3:
+		*event_type = MCA_T_MEMCONTROLLER_AC;
 		return ("AC");
 	case 0x4:
+		*event_type = MCA_T_MEMCONTROLLER_MS;
 		return ("MS");
 	}
+	*event_type = MCA_T_MEMCONTROLLER_OTHER;
 	return ("???");
 }
 
@@ -426,6 +440,7 @@ static void
 mca_log(const struct mca_record *rec)
 {
 	uint16_t mca_error;
+	enum mca_stat_types event_type;
 
 	if (mca_mute(rec))
 		return;
@@ -473,34 +488,44 @@ mca_log(const struct mca_record *rec)
 	if (rec->mr_status & MC_STATUS_OVER)
 		printf("OVER ");
 	mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
+	event_type = MCA_T_COUNT;
 	switch (mca_error) {
 		/* Simple error codes. */
 	case 0x0000:
 		printf("no error");
+		event_type = MCA_T_NONE;
 		break;
 	case 0x0001:
 		printf("unclassified error");
+		event_type = MCA_T_UNCLASSIFIED;
 		break;
 	case 0x0002:
 		printf("ucode ROM parity error");
+		event_type = MCA_T_UCODE_ROM_PARITY;
 		break;
 	case 0x0003:
 		printf("external error");
+		event_type = MCA_T_EXTERNAL;
 		break;
 	case 0x0004:
 		printf("FRC error");
+		event_type = MCA_T_FRC;
 		break;
 	case 0x0005:
 		printf("internal parity error");
+		event_type = MCA_T_INTERNAL_PARITY;
 		break;
 	case 0x0006:
 		printf("SMM handler code access violation");
+		event_type = MCA_T_SMM_HANDLER;
 		break;
 	case 0x0400:
 		printf("internal timer error");
+		event_type = MCA_T_INTERNAL_TIMER;
 		break;
 	case 0x0e0b:
 		printf("generic I/O error");
+		event_type = MCA_T_GENERIC_IO;
 		if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL &&
 		    (rec->mr_status & MC_STATUS_MISCV)) {
 			printf(" (pci%d:%d:%d:%d)",
@@ -513,6 +538,7 @@ mca_log(const struct mca_record *rec)
 	default:
 		if ((mca_error & 0xfc00) == 0x0400) {
 			printf("internal error %x", mca_error & 0x03ff);
+			event_type = MCA_T_INTERNAL;
 			break;
 		}
 
@@ -521,6 +547,7 @@ mca_log(const struct mca_record *rec)
 		/* Memory hierarchy error. */
 		if ((mca_error & 0xeffc) == 0x000c) {
 			printf("%s memory error", mca_error_level(mca_error));
+			event_type = MCA_T_MEMORY;
 			break;
 		}
 
@@ -528,12 +555,14 @@ mca_log(const struct mca_record *rec)
 		if ((mca_error & 0xeff0) == 0x0010) {
 			printf("%sTLB %s error", mca_error_ttype(mca_error),
 			    mca_error_level(mca_error));
+			event_type = MCA_T_TLB;
 			break;
 		}
 
 		/* Memory controller error. */
 		if ((mca_error & 0xef80) == 0x0080) {
-			printf("%s channel ", mca_error_mmtype(mca_error));
+			printf("%s channel ", mca_error_mmtype(mca_error,
+			    &event_type));
 			if ((mca_error & 0x000f) != 0x000f)
 				printf("%d", mca_error & 0x000f);
 			else
@@ -548,12 +577,14 @@ mca_log(const struct mca_record *rec)
 			    mca_error_ttype(mca_error),
 			    mca_error_level(mca_error),
 			    mca_error_request(mca_error));
+			event_type = MCA_T_CACHE;
 			break;
 		}
 
 		/* Extended memory error. */
 		if ((mca_error & 0xef80) == 0x0280) {
-			printf("%s channel ", mca_error_mmtype(mca_error));
+			printf("%s channel ", mca_error_mmtype(mca_error,
+			    &event_type));
 			if ((mca_error & 0x000f) != 0x000f)
 				printf("%d", mca_error & 0x000f);
 			else
@@ -565,6 +596,7 @@ mca_log(const struct mca_record *rec)
 		/* Bus and/or Interconnect error. */
 		if ((mca_error & 0xe800) == 0x0800) {
 			printf("BUS%s ", mca_error_level(mca_error));
+			event_type = MCA_T_BUS;
 			switch ((mca_error & 0x0600) >> 9) {
 			case 0:
 				printf("Source");
@@ -600,6 +632,7 @@ mca_log(const struct mca_record *rec)
 		}
 
 		printf("unknown error %x", mca_error);
+		event_type = MCA_T_UNKNOWN;
 		break;
 	}
 	printf("\n");
@@ -615,6 +648,12 @@ mca_log(const struct mca_record *rec)
 	}
 	if (rec->mr_status & MC_STATUS_MISCV)
 		printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
+	if (event_type < 0 || event_type >= MCA_T_COUNT) {
+		KASSERT(0, ("%s: invalid event type (%d)", __func__,
+		    event_type));
+		event_type = MCA_T_UNKNOWN;
+	}
+	atomic_add_64(&mca_stats[event_type], 1);
 }
 
 static bool
@@ -979,6 +1018,16 @@ mca_process_records(enum scan_mode mode)
 {
 	struct mca_internal *mca;
 
+	/*
+	 * If in an interrupt context, defer the post-scan activities to a
+	 * task queue.
+	 */
+	if (mode != POLLED) {
+		if (mca_startup_done)
+			taskqueue_enqueue(mca_tq, &mca_postscan_task);
+		return;
+	}
+
 	mtx_lock_spin(&mca_lock);
 	while ((mca = STAILQ_FIRST(&mca_pending)) != NULL) {
 		STAILQ_REMOVE_HEAD(&mca_pending, link);
@@ -986,10 +1035,19 @@ mca_process_records(enum scan_mode mode)
 		mca_store_record(mca);
 	}
 	mtx_unlock_spin(&mca_lock);
-	if (mode == POLLED)
-		mca_resize_freelist();
-	else if (!cold)
-		taskqueue_enqueue(mca_tq, &mca_resize_task);
+	mca_resize_freelist();
+}
+
+/*
+ * Emit log entries and resize the free list. This is intended to be called
+ * from a task queue to handle work which does not need to be done (or cannot
+ * be done) in an interrupt context.
+ */
+static void
+mca_postscan(void *context __unused, int pending __unused)
+{
+
+	mca_process_records(POLLED);
 }
 
 /*
@@ -1060,7 +1118,7 @@ sysctl_mca_maxcount(SYSCTL_HANDLER_ARGS)
 			doresize = true;
 		}
 	mtx_unlock_spin(&mca_lock);
-	if (doresize && !cold)
+	if (doresize && mca_startup_done)
 		taskqueue_enqueue(mca_tq, &mca_resize_task);
 	return (error);
 }
@@ -1072,12 +1130,16 @@ mca_startup(void *dummy)
 	if (mca_banks <= 0)
 		return;
 
-	/* CMCIs during boot may have claimed items from the freelist. */
-	mca_resize_freelist();
-
 	taskqueue_start_threads(&mca_tq, 1, PI_SWI(SWI_TQ), "mca taskq");
 	taskqueue_enqueue_timeout_sbt(mca_tq, &mca_scan_task,
 	    mca_ticks * SBT_1S, 0, C_PREL(1));
+	mca_startup_done = true;
+
+	/*
+	 * CMCIs during boot may have recorded entries. Conduct the post-scan
+	 * activities now.
+	 */
+	mca_postscan(NULL, 0);
 }
 SYSINIT(mca_startup, SI_SUB_KICK_SCHEDULER, SI_ORDER_ANY, mca_startup, NULL);
 
@@ -1137,6 +1199,7 @@ mca_setup(uint64_t mcg_cap)
 	TIMEOUT_TASK_INIT(mca_tq, &mca_scan_task, 0, mca_scan_cpus, NULL);
 	STAILQ_INIT(&mca_freelist);
 	TASK_INIT(&mca_resize_task, 0, mca_resize, NULL);
+	TASK_INIT(&mca_postscan_task, 0, mca_postscan, NULL);
 	mca_resize_freelist();
 	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
 	    "count", CTLFLAG_RD, (int *)(uintptr_t)&mca_count, 0,
@@ -1540,6 +1603,9 @@ mca_intr(void)
 		panic("Unrecoverable machine check exception");
 	}
 
+	if (count)
+		mca_process_records(MCE);
+
 	/* Clear MCIP. */
 	wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
 }
diff --git a/tests/atf_python/sys/net/vnet.py b/tests/atf_python/sys/net/vnet.py
index c96eb5d671fc..f75a3eaa693e 100644
--- a/tests/atf_python/sys/net/vnet.py
+++ b/tests/atf_python/sys/net/vnet.py
@@ -283,14 +283,15 @@ class VnetFactory(object):
             time.sleep(0.1)
         return not_matched
 
-    def create_vnet(self, vnet_alias: str, ifaces: List[VnetInterface]):
+    def create_vnet(self, vnet_alias: str, ifaces: List[VnetInterface], opts: List[str]):
         vnet_name = "pytest:{}".format(convert_test_name(self.topology_id))
         if self._vnets:
             # add number to distinguish jails
             vnet_name = "{}_{}".format(vnet_name, len(self._vnets) + 1)
         iface_cmds = " ".join(["vnet.interface={}".format(i.name) for i in ifaces])
-        cmd = "/usr/sbin/jail -i -c name={} persist vnet {}".format(
-            vnet_name, iface_cmds
+        opt_cmds = " ".join(["{}".format(i) for i in opts])
+        cmd = "/usr/sbin/jail -i -c name={} persist vnet {} {}".format(
+            vnet_name, iface_cmds, opt_cmds
         )
         jid = 0
         try:
@@ -421,7 +422,10 @@ class VnetTestTemplate(BaseTest):
                     idx = len(iface_map[iface_alias].vnet_aliases)
                     iface_map[iface_alias].vnet_aliases.append(obj_name)
                     vnet_ifaces.append(iface_map[iface_alias].ifaces[idx])
-                vnet = vnet_factory.create_vnet(obj_name, vnet_ifaces)
+                opts = []
+                if "opts" in obj_data:
+                    opts = obj_data["opts"]
+                vnet = vnet_factory.create_vnet(obj_name, vnet_ifaces, opts)
                 vnet_map[obj_name] = vnet
                 # Allow reference to VNETs as attributes
                 setattr(self, obj_name, vnet)
diff --git a/tests/atf_python/sys/netpfil/ipfw/insns.py b/tests/atf_python/sys/netpfil/ipfw/insns.py
index 12f145f49393..f8a56de901ae 100644
--- a/tests/atf_python/sys/netpfil/ipfw/insns.py
+++ b/tests/atf_python/sys/netpfil/ipfw/insns.py
@@ -510,7 +510,7 @@ class InsnIp6(Insn):
 
 insn_attrs = prepare_attrs_map(
     [
-        AttrDescr(IpFwOpcode.O_CHECK_STATE, Insn),
+        AttrDescr(IpFwOpcode.O_CHECK_STATE, InsnU32),
         AttrDescr(IpFwOpcode.O_ACCEPT, InsnEmpty),
         AttrDescr(IpFwOpcode.O_COUNT, InsnEmpty),
 
@@ -521,16 +521,19 @@ insn_attrs = prepare_attrs_map(
         AttrDescr(IpFwOpcode.O_COUNT, InsnEmpty),
         AttrDescr(IpFwOpcode.O_QUEUE, Insn),
         AttrDescr(IpFwOpcode.O_PIPE, Insn),
-        AttrDescr(IpFwOpcode.O_SKIPTO, Insn),
+        AttrDescr(IpFwOpcode.O_SKIPTO, InsnU32),
         AttrDescr(IpFwOpcode.O_NETGRAPH, Insn),
         AttrDescr(IpFwOpcode.O_NGTEE, Insn),
         AttrDescr(IpFwOpcode.O_DIVERT, Insn),
         AttrDescr(IpFwOpcode.O_TEE, Insn),
-        AttrDescr(IpFwOpcode.O_CALLRETURN, Insn),
+        AttrDescr(IpFwOpcode.O_CALLRETURN, InsnU32),
         AttrDescr(IpFwOpcode.O_SETFIB, Insn),
         AttrDescr(IpFwOpcode.O_SETDSCP, Insn),
         AttrDescr(IpFwOpcode.O_REASS, InsnEmpty),
-        AttrDescr(IpFwOpcode.O_SETMARK, Insn),
+        AttrDescr(IpFwOpcode.O_SETMARK, InsnU32),
+
+        AttrDescr(IpFwOpcode.O_EXTERNAL_ACTION, InsnU32),
+        AttrDescr(IpFwOpcode.O_EXTERNAL_INSTANCE, InsnU32),
 
 
 
@@ -545,11 +548,11 @@ insn_attrs = prepare_attrs_map(
         AttrDescr(IpFwOpcode.O_IP_DST, InsnIp),
         AttrDescr(IpFwOpcode.O_IP6_DST, InsnIp6),
         AttrDescr(IpFwOpcode.O_IP6_SRC, InsnIp6),
-        AttrDescr(IpFwOpcode.O_IP_SRC_LOOKUP, InsnTable),
-        AttrDescr(IpFwOpcode.O_IP_DST_LOOKUP, InsnTable),
+        AttrDescr(IpFwOpcode.O_IP_SRC_LOOKUP, InsnU32),
+        AttrDescr(IpFwOpcode.O_IP_DST_LOOKUP, InsnU32),
         AttrDescr(IpFwOpcode.O_IP_SRCPORT, InsnPorts),
         AttrDescr(IpFwOpcode.O_IP_DSTPORT, InsnPorts),
-        AttrDescr(IpFwOpcode.O_PROBE_STATE, Insn),
-        AttrDescr(IpFwOpcode.O_KEEP_STATE, Insn),
+        AttrDescr(IpFwOpcode.O_PROBE_STATE, InsnU32),
+        AttrDescr(IpFwOpcode.O_KEEP_STATE, InsnU32),
     ]
 )
diff --git a/tests/oclo/Makefile b/tests/oclo/Makefile
index 350c9f857c85..6f73aec0ff7c 100644
--- a/tests/oclo/Makefile
+++ b/tests/oclo/Makefile
@@ -5,7 +5,6 @@ TESTSDIR=	${TESTSBASE}/cddl/oclo
 PLAIN_TESTS_C=	oclo oclo_errors ocloexec_verify
 
 SRCS.oclo=	oclo.c
-LIBADD.oclo+=	openbsd
 LIBADD.ocloexec_verify+= util
 
 .include <bsd.test.mk>
diff --git a/tests/sys/file/Makefile b/tests/sys/file/Makefile
index f80d1b271b85..beb4452359b7 100644
--- a/tests/sys/file/Makefile
+++ b/tests/sys/file/Makefile
@@ -5,7 +5,7 @@ BINDIR=		${TESTSDIR}
 ATF_TESTS_C+=	path_test
 TAP_TESTS_C+=	closefrom_test
 TAP_TESTS_C+=	dup_test
-TAP_TESTS_C+=	fcntlflags_test
+ATF_TESTS_C+=	fcntlflags_test
 TAP_TESTS_SH+=	flock_test
 PLAIN_TESTS_C+=	ftruncate_test
 PLAIN_TESTS_C+=	newfileops_on_fork_test
diff --git a/tests/sys/file/fcntlflags_test.c b/tests/sys/file/fcntlflags_test.c
index c5026e38c48b..15a18c113c4a 100644
--- a/tests/sys/file/fcntlflags_test.c
+++ b/tests/sys/file/fcntlflags_test.c
@@ -24,85 +24,110 @@
  * SUCH DAMAGE.
  */
 
-#include <sys/cdefs.h>
-
+#include <sys/filio.h>
+#include <errno.h>
 #include <fcntl.h>
 #include <stdio.h>
 #include <unistd.h>
 
+#include <atf-c.h>
+
 /*
  * O_ACCMODE is currently defined incorrectly. This is what it should be.
  * Various code depends on the incorrect value.
  */
 #define CORRECT_O_ACCMODE (O_ACCMODE | O_EXEC)
 
-static int testnum;
-
 static void
-subtests(const char *path, int omode, const char *omodetext)
+basic_tests(const char *path, int omode, const char *omodetext)
 {
 	int fd, flags1, flags2, flags3;
 
 	fd = open(path, omode);
-	if (fd == -1)
-		printf("not ok %d - open(\"%s\", %s) failed\n",
-		    testnum++, path, omodetext);
-	else
-		printf("ok %d - open(\"%s\", %s) succeeded\n",
-		    testnum++, path, omodetext);
+	ATF_REQUIRE_MSG(fd != -1, "open(\"%s\", %s) failed: %s", path,
+	    omodetext, strerror(errno));
+
 	flags1 = fcntl(fd, F_GETFL);
-	if (flags1 == -1)
-		printf("not ok %d - fcntl(F_GETFL) failed\n", testnum++);
-	else if ((flags1 & CORRECT_O_ACCMODE) == omode)
-		printf("ok %d - fcntl(F_GETFL) gave correct result\n",
-		    testnum++);
-	else
-		printf("not ok %d - fcntl(F_GETFL) gave incorrect result "
-		    "(%#x & %#x != %#x)\n",
-		    testnum++, flags1, CORRECT_O_ACCMODE, omode);
-	if (fcntl(fd, F_SETFL, flags1) == -1)
-		printf("not ok %d - fcntl(F_SETFL) same flags failed\n",
-		    testnum++);
-	else
-		printf("ok %d - fcntl(F_SETFL) same flags succeeded\n",
-		    testnum++);
+	ATF_REQUIRE_MSG(flags1 != -1, "fcntl(F_GETFL) (1) failed: %s",
+	    strerror(errno));
+	ATF_REQUIRE_INTEQ(omode, flags1 & CORRECT_O_ACCMODE);
+	ATF_REQUIRE((flags1 & O_NONBLOCK) == 0);
+
+	ATF_REQUIRE_MSG(fcntl(fd, F_SETFL, flags1) != -1,
+	    "fcntl(F_SETFL) same flags failed: %s", strerror(errno));
+
 	flags2 = fcntl(fd, F_GETFL);
-	if (flags2 == -1)
-		printf("not ok %d - fcntl(F_GETFL) failed\n", testnum++);
-	else if (flags2 == flags1)
-		printf("ok %d - fcntl(F_GETFL) gave same result\n",
-		    testnum++);
-	else
-		printf("not ok %d - fcntl(F_SETFL) caused fcntl(F_GETFL) to "
-		    "change from %#x to %#x\n",
-		    testnum++, flags1, flags2);
-	if (fcntl(fd, F_SETFL, flags2 | O_NONBLOCK) == -1)
-		printf("not ok %d - fcntl(F_SETFL) O_NONBLOCK failed\n",
-		    testnum++);
-	else
-		printf("ok %d - fcntl(F_SETFL) O_NONBLOCK succeeded\n",
-		    testnum++);
+	ATF_REQUIRE_MSG(flags2 != -1, "fcntl(F_GETFL) (2) failed: %s",
+	    strerror(errno));
+	ATF_REQUIRE_INTEQ(flags1, flags2);
+
+	ATF_REQUIRE_MSG(fcntl(fd, F_SETFL, flags2 | O_NONBLOCK) != -1,
+	    "fcntl(F_SETFL) O_NONBLOCK failed: %s", strerror(errno));
+
 	flags3 = fcntl(fd, F_GETFL);
-	if (flags3 == -1)
-		printf("not ok %d - fcntl(F_GETFL) failed\n", testnum++);
-	else if (flags3 == (flags2 | O_NONBLOCK))
-		printf("ok %d - fcntl(F_GETFL) gave expected result\n",
-		    testnum++);
-	else
-		printf("not ok %d - fcntl(F_SETFL) gave unexpected result "
-		    "(%#x != %#x)\n",
-		    testnum++, flags3, flags2 | O_NONBLOCK);
+	ATF_REQUIRE_MSG(flags3 != -1, "fcntl(F_GETFL) (3) failed: %s",
+	    strerror(errno));
+	ATF_REQUIRE_INTEQ(flags2 | O_NONBLOCK, flags3);
+
 	(void)close(fd);
 }
 
-int
-main(int argc __unused, char **argv __unused)
+ATF_TC_WITHOUT_HEAD(read_only_null);
+ATF_TC_BODY(read_only_null, tc)
 {
-	printf("1..24\n");
-	testnum = 1;
-	subtests("/dev/null", O_RDONLY, "O_RDONLY");
-	subtests("/dev/null", O_WRONLY, "O_WRONLY");
-	subtests("/dev/null", O_RDWR, "O_RDWR");
-	subtests("/bin/sh", O_EXEC, "O_EXEC");
-	return (0);
+	basic_tests("/dev/null", O_RDONLY, "O_RDONLY");
+}
+
+ATF_TC_WITHOUT_HEAD(write_only_null);
+ATF_TC_BODY(write_only_null, tc)
+{
+	basic_tests("/dev/null", O_WRONLY, "O_WRONLY");
+}
+
+ATF_TC_WITHOUT_HEAD(read_write_null);
+ATF_TC_BODY(read_write_null, tc)
+{
+	basic_tests("/dev/null", O_RDWR, "O_RDWR");
+}
+
+ATF_TC_WITHOUT_HEAD(exec_only_sh);
+ATF_TC_BODY(exec_only_sh, tc)
+{
+	basic_tests("/bin/sh", O_EXEC, "O_EXEC");
+}
+
+ATF_TC_WITHOUT_HEAD(fioasync_dev_null);
+ATF_TC_BODY(fioasync_dev_null, tc)
+{
+	int fd, flags1, flags2, val;
+
+	fd = open("/dev/null", O_RDONLY);
+	ATF_REQUIRE_MSG(fd != -1, "open(\"/dev/null\") failed: %s",
+	    strerror(errno));
+
+	flags1 = fcntl(fd, F_GETFL);
+	ATF_REQUIRE_MSG(flags1 != -1, "fcntl(F_GETFL) (1) failed: %s",
+	    strerror(errno));
+	ATF_REQUIRE((flags1 & O_ASYNC) == 0);
+
+	val = 1;
+	ATF_REQUIRE_ERRNO(EINVAL, ioctl(fd, FIOASYNC, &val) == -1);
+
+	flags2 = fcntl(fd, F_GETFL);
+	ATF_REQUIRE_MSG(flags2 != -1, "fcntl(F_GETFL) (2) failed: %s",
+	    strerror(errno));
+	ATF_REQUIRE_INTEQ(flags1, flags2);
+
+	(void)close(fd);
+}
+
+ATF_TP_ADD_TCS(tp)
+{
+	ATF_TP_ADD_TC(tp, read_only_null);
+	ATF_TP_ADD_TC(tp, write_only_null);
+	ATF_TP_ADD_TC(tp, read_write_null);
+	ATF_TP_ADD_TC(tp, exec_only_sh);
+	ATF_TP_ADD_TC(tp, fioasync_dev_null);
+
+	return (atf_no_error());
 }
diff --git a/tests/sys/netinet/Makefile b/tests/sys/netinet/Makefile
index cc525bf24480..b742342beecb 100644
--- a/tests/sys/netinet/Makefile
+++ b/tests/sys/netinet/Makefile
@@ -48,7 +48,7 @@ TEST_METADATA.forward+=	required_programs="python"	\
 TEST_METADATA.output+=	required_programs="python"
 TEST_METADATA.redirect+= required_programs="python"
 
-PROGS=	udp_dontroute tcp_user_cookie sendto-IP_MULTICAST_IF
+PROGS=	udp_dontroute tcp_user_cookie multicast-send multicast-receive
 
 ${PACKAGE}FILES+=		redirect.py
 
diff --git a/tests/sys/netinet/multicast-receive.c b/tests/sys/netinet/multicast-receive.c
new file mode 100644
index 000000000000..81d0f10f5cfe
--- /dev/null
+++ b/tests/sys/netinet/multicast-receive.c
@@ -0,0 +1,130 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2025 Gleb Smirnoff <glebius@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <arpa/inet.h>
+#include <net/if.h>
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <limits.h>
+#include <err.h>
+
+static in_port_t
+atop(const char *c)
+{
+	unsigned long ul;
+
+	errno = 0;
+	if ((ul = strtol(c, NULL, 10)) < 1 || ul > IPPORT_MAX || errno != 0)
+		err(1, "can't parse %s", c);
+
+	return ((in_port_t)ul);
+}
+
+int
+main(int argc, char *argv[])
+{
+	char buf[IP_MAXPACKET + 1];
+	struct sockaddr_in sin = {
+		.sin_family = AF_INET,
+		.sin_len = sizeof(struct sockaddr_in),
+	};
+	socklen_t slen = sizeof(struct sockaddr_in);
+	struct in_addr maddr, ifaddr;
+	ssize_t len;
+	int s, ifindex;
+	bool index;
+
+	if (argc < 4)
+usage:
+		errx(1, "Usage: %s (ip_mreq|ip_mreqn|group_req) "
+		    "IPv4-group port interface", argv[0]);
+
+	if (inet_pton(AF_INET, argv[2], &maddr) != 1)
+		err(1, "inet_pton(%s) failed", argv[2]);
+	sin.sin_port = htons(atop(argv[3]));
+	if (inet_pton(AF_INET, argv[4], &ifaddr) == 1)
+		index = false;
+	else if ((ifindex = if_nametoindex(argv[4])) > 0)
+		index = true;
+	else if (strcmp(argv[4], "0") == 0) {
+		ifindex = 0;
+		index = true;
+	} else
+		err(1, "if_nametoindex(%s) failed", argv[4]);
+
+	assert((s = socket(PF_INET, SOCK_DGRAM, 0)) > 0);
+	assert(bind(s, (struct sockaddr *)&sin, sizeof(sin)) == 0);
+
+	if (strcmp(argv[1], "ip_mreq") == 0) {
+		if (index)
+			errx(1, "ip_mreq doesn't accept index");
+		struct ip_mreq mreq = {
+			.imr_multiaddr = maddr,
+			.imr_interface = ifaddr,
+		};
+		assert(setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, &mreq,
+		    sizeof(mreq)) == 0);
+	} else if (strcmp(argv[1], "ip_mreqn") == 0) {
+		/*
+		 * ip_mreqn shall be used with index, but for testing
+		 * purposes accept address too.
+		 */
+		struct ip_mreqn mreqn = {
+			.imr_multiaddr = maddr,
+			.imr_address = index ? (struct in_addr){ 0 } : ifaddr,
+			.imr_ifindex = index ? ifindex : 0,
+		};
+		assert(setsockopt(s, IPPROTO_IP, IP_ADD_MEMBERSHIP, &mreqn,
+		    sizeof(mreqn)) == 0);
+	} else if (strcmp(argv[1], "group_req") == 0) {
+		if (!index)
+			errx(1, "group_req expects index");
+		struct group_req greq = { .gr_interface = ifindex };
+		struct sockaddr_in *gsa = (struct sockaddr_in *)&greq.gr_group;
+
+		gsa->sin_family = AF_INET;
+		gsa->sin_len = sizeof(struct sockaddr_in);
+		gsa->sin_addr = maddr;
+		assert(setsockopt(s, IPPROTO_IP, MCAST_JOIN_GROUP, &greq,
+		    sizeof(greq)) == 0);
+	} else
+		goto usage;
+
+	assert((len = recvfrom(s, buf, sizeof(buf) - 1, 0,
+	    (struct sockaddr *)&sin, &slen)) > 0);
+	buf[len] = '\0';
+	printf("%s:%u %s\n", inet_ntoa(sin.sin_addr), ntohs(sin.sin_port), buf);
+
+	return (0);
+}
diff --git a/tests/sys/netinet/sendto-IP_MULTICAST_IF.c b/tests/sys/netinet/multicast-send.c
index d478e4da0b3b..f10b2b6338dd 100644
--- a/tests/sys/netinet/sendto-IP_MULTICAST_IF.c
+++ b/tests/sys/netinet/multicast-send.c
@@ -28,35 +28,69 @@
 #include <sys/socket.h>
 #include <netinet/in.h>
 #include <arpa/inet.h>
+#include <net/if.h>
 #include <assert.h>
+#include <errno.h>
+#include <limits.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
 #include <err.h>
 
+static in_port_t
+atop(const char *c)
+{
+	unsigned long ul;
+
+	errno = 0;
+	if ((ul = strtol(c, NULL, 10)) < 1 || ul > IPPORT_MAX || errno != 0)
+		err(1, "can't parse %s", c);
+
+	return ((in_port_t)ul);
+}
+
 int
 main(int argc, char *argv[])
 {
-	struct sockaddr_in sin = {
+	struct sockaddr_in src = {
+		.sin_family = AF_INET,
+		.sin_len = sizeof(struct sockaddr_in),
+	}, dst = {
 		.sin_family = AF_INET,
 		.sin_len = sizeof(struct sockaddr_in),
 	};
+	struct ip_mreqn mreqn;
 	struct in_addr in;
-	int s, rv;
+	int s;
+	bool index;
 
-	if (argc < 2)
-		errx(1, "Usage: %s IPv4-address", argv[0]);
+	if (argc < 7)
+		errx(1, "Usage: %s src-IPv4 src-port dst-IPv4 dst-port "
+		    "interface payload", argv[0]);
 
-	if (inet_pton(AF_INET, argv[1], &in) != 1)
+	if (inet_pton(AF_INET, argv[1], &src.sin_addr) != 1)
 		err(1, "inet_pton(%s) failed", argv[1]);
+	src.sin_port = htons(atop(argv[2]));
+	if (inet_pton(AF_INET, argv[3], &dst.sin_addr) != 1)
+		err(1, "inet_pton(%s) failed", argv[3]);
+	dst.sin_port = htons(atop(argv[4]));
+	if (inet_pton(AF_INET, argv[5], &in) == 1)
+		index = false;
+	else if ((mreqn.imr_ifindex = if_nametoindex(argv[5])) > 0)
+		index = true;
+	else
+		err(1, "if_nametoindex(%s) failed", argv[5]);
 
 	assert((s = socket(PF_INET, SOCK_DGRAM, 0)) > 0);
-	assert(bind(s, (struct sockaddr *)&sin, sizeof(sin)) == 0);
-	assert(setsockopt(s, IPPROTO_IP, IP_MULTICAST_IF, &in, sizeof(in))
-	  == 0);
-	/* RFC 6676 */
-	assert(inet_pton(AF_INET, "233.252.0.1", &sin.sin_addr) == 1);
-	sin.sin_port = htons(6676);
-	rv = sendto(s, &sin, sizeof(sin), 0,
-	    (struct sockaddr *)&sin, sizeof(sin));
-	if (rv != sizeof(sin))
+	assert(bind(s, (struct sockaddr *)&src, sizeof(src)) == 0);
+	if (index)
+		assert(setsockopt(s, IPPROTO_IP, IP_MULTICAST_IF, &mreqn,
+		    sizeof(mreqn)) == 0);
+	else
+		assert(setsockopt(s, IPPROTO_IP, IP_MULTICAST_IF, &in,
+		    sizeof(in)) == 0);
+	if (sendto(s, argv[6], strlen(argv[6]) + 1, 0, (struct sockaddr *)&dst,
+	    sizeof(dst)) != (ssize_t)strlen(argv[6]) + 1)
 		err(1, "sendto failed");
 
 	return (0);
diff --git a/tests/sys/netinet/multicast.sh b/tests/sys/netinet/multicast.sh
index eb2b962dac70..a3854fd2fd20 100644..100755
--- a/tests/sys/netinet/multicast.sh
+++ b/tests/sys/netinet/multicast.sh
@@ -26,36 +26,130 @@
 
 . $(atf_get_srcdir)/../common/vnet.subr
 
-# See regression fixed in baad45c9c12028964acd0b58096f3aaa0fb22859
-atf_test_case "IP_MULTICAST_IF" "cleanup"
-IP_MULTICAST_IF_head()
+# Set up two jails, mjail1 and mjail2, connected with two interface pairs
+multicast_vnet_init()
 {
-	atf_set descr \
-	    'sendto() for IP_MULTICAST_IF socket does not do routing lookup'
+
+	vnet_init
+	epair1=$(vnet_mkepair)
+	epair2=$(vnet_mkepair)
+	vnet_mkjail mjail1 ${epair1}a ${epair2}a
+	jexec mjail1 ifconfig ${epair1}a up
+	jexec mjail1 ifconfig ${epair1}a 192.0.2.1/24
+	jexec mjail1 ifconfig ${epair2}a up
+	jexec mjail1 ifconfig ${epair2}a 192.0.3.1/24
+	vnet_mkjail mjail2 ${epair1}b ${epair2}b
+	jexec mjail2 ifconfig ${epair1}b up
+	jexec mjail2 ifconfig ${epair1}b 192.0.2.2/24
+	jexec mjail2 ifconfig ${epair2}b up
+	jexec mjail2 ifconfig ${epair2}b 192.0.3.2/24
+}
+
+atf_test_case "IP_ADD_MEMBERSHIP_ip_mreq" "cleanup"
+IP_ADD_MEMBERSHIP_ip_mreq_head()
+{
+	atf_set descr 'IP_ADD_MEMBERSHIP / IP_MULTICAST_IF with ip_mreq'
 	atf_set require.user root
+}
+IP_ADD_MEMBERSHIP_ip_mreq_body()
+{
+	multicast_vnet_init
+
+	# join group on interface with IP address 192.0.2.2
+	jexec mjail2 $(atf_get_srcdir)/multicast-receive \
+	    ip_mreq 233.252.0.1 6676 192.0.2.2 > out & pid=$!
+	atf_check -s exit:0 -o empty \
+	    jexec mjail1 $(atf_get_srcdir)/multicast-send \
+	    0.0.0.0 6676 233.252.0.1 6676 192.0.2.1 hello
+	atf_check -s exit:0 sh -c "wait $pid; exit $?"
+	atf_check -s exit:0 -o inline:"192.0.2.1:6676 hello\n" cat out
 
+	# join group on interface with IP address 192.0.3.2
+	jexec mjail2 $(atf_get_srcdir)/multicast-receive \
+	    ip_mreq 233.252.0.1 6676 192.0.3.2 > out & pid=$!
+	atf_check -s exit:0 -o empty \
+	    jexec mjail1 $(atf_get_srcdir)/multicast-send \
+	    0.0.0.0 6676 233.252.0.1 6676 192.0.3.1 hello
+	atf_check -s exit:0 sh -c "wait $pid; exit $?"
+	atf_check -s exit:0 -o inline:"192.0.3.1:6676 hello\n" cat out
+}
+IP_ADD_MEMBERSHIP_ip_mreq_cleanup()
+{
+	rm out
+	vnet_cleanup
 }
 
-IP_MULTICAST_IF_body()
+atf_test_case "IP_ADD_MEMBERSHIP_ip_mreqn" "cleanup"
+IP_ADD_MEMBERSHIP_ip_mreqn_head()
+{
+	atf_set descr 'IP_ADD_MEMBERSHIP / IP_MULTICAST_IF with ip_mreqn'
+	atf_set require.user root
+}
+IP_ADD_MEMBERSHIP_ip_mreqn_body()
 {
-	local epair mjail
+	multicast_vnet_init
 
-	vnet_init
-	# The test doesn't use our half of epair
-	epair=$(vnet_mkepair)
-	vnet_mkjail mjail ${epair}a
-	jexec mjail ifconfig ${epair}a up
-	jexec mjail ifconfig ${epair}a 192.0.2.1/24
+	# join group on interface epair2
+	jexec mjail2 $(atf_get_srcdir)/multicast-receive \
+	    ip_mreqn 233.252.0.1 6676 ${epair1}b > out & pid=$!
+	atf_check -s exit:0 -o empty \
+	    jexec mjail1 $(atf_get_srcdir)/multicast-send \
+	    0.0.0.0 6676 233.252.0.1 6676 ${epair1}a hello
+	atf_check -s exit:0 sh -c "wait $pid; exit $?"
+	atf_check -s exit:0 -o inline:"192.0.2.1:6676 hello\n" cat out
+
+	# join group on interface epair2
+	jexec mjail2 $(atf_get_srcdir)/multicast-receive \
+	    ip_mreqn 233.252.0.1 6676 ${epair2}b > out & pid=$!
 	atf_check -s exit:0 -o empty \
-	    jexec mjail $(atf_get_srcdir)/sendto-IP_MULTICAST_IF 192.0.2.1
+	    jexec mjail1 $(atf_get_srcdir)/multicast-send \
+	    0.0.0.0 6676 233.252.0.1 6676 ${epair2}a hello
+	atf_check -s exit:0 sh -c "wait $pid; exit $?"
+	atf_check -s exit:0 -o inline:"192.0.3.1:6676 hello\n" cat out
+}
+IP_ADD_MEMBERSHIP_ip_mreqn_cleanup()
+{
+	rm out
+	vnet_cleanup
 }
 
-IP_MULTICAST_IF_cleanup()
+atf_test_case "MCAST_JOIN_GROUP" "cleanup"
+MCAST_JOIN_GROUP_head()
+{
+	atf_set descr 'MCAST_JOIN_GROUP'
+	atf_set require.user root
+}
+MCAST_JOIN_GROUP_body()
+{
+	multicast_vnet_init
+
+	# join group on interface epair2
+	jexec mjail2 $(atf_get_srcdir)/multicast-receive \
+	    group_req 233.252.0.1 6676 ${epair1}b > out & pid=$!
+	atf_check -s exit:0 -o empty \
+	    jexec mjail1 $(atf_get_srcdir)/multicast-send \
+	    0.0.0.0 6676 233.252.0.1 6676 ${epair1}a hello
+	atf_check -s exit:0 sh -c "wait $pid; exit $?"
+	atf_check -s exit:0 -o inline:"192.0.2.1:6676 hello\n" cat out
+
+	# join group on interface epair2
+	jexec mjail2 $(atf_get_srcdir)/multicast-receive \
+	    group_req 233.252.0.1 6676 ${epair2}b > out & pid=$!
+	atf_check -s exit:0 -o empty \
+	    jexec mjail1 $(atf_get_srcdir)/multicast-send \
+	    0.0.0.0 6676 233.252.0.1 6676 ${epair2}a hello
+	atf_check -s exit:0 sh -c "wait $pid; exit $?"
+	atf_check -s exit:0 -o inline:"192.0.3.1:6676 hello\n" cat out
+}
+MCAST_JOIN_GROUP_cleanup()
 {
+	rm out
 	vnet_cleanup
 }
 
 atf_init_test_cases()
 {
-	atf_add_test_case "IP_MULTICAST_IF"
+	atf_add_test_case "IP_ADD_MEMBERSHIP_ip_mreq"
+	atf_add_test_case "IP_ADD_MEMBERSHIP_ip_mreqn"
+	atf_add_test_case "MCAST_JOIN_GROUP"
 }
diff --git a/tests/sys/netinet6/ndp.sh b/tests/sys/netinet6/ndp.sh
index bac9764ee3c9..21a50cda02ba 100755
--- a/tests/sys/netinet6/ndp.sh
+++ b/tests/sys/netinet6/ndp.sh
@@ -188,9 +188,48 @@ ndp_slaac_default_route_cleanup() {
 	vnet_cleanup
 }
 
+atf_test_case "ndp_prefix_len_mismatch" "cleanup"
+ndp_prefix_len_mismatch_head() {
+	atf_set descr 'Test RAs on an interface without a /64 lladdr'
+	atf_set require.user root
+	atf_set require.progs python3 scapy
+}
+
+ndp_prefix_len_mismatch_body() {
+	vnet_init
+
+	epair=$(vnet_mkepair)
+
+	vnet_mkjail alcatraz ${epair}a
+
+	jexec alcatraz ifconfig ${epair}a inet6 -auto_linklocal
+	jexec alcatraz ifconfig ${epair}a inet6 -ifdisabled
+	jexec alcatraz ifconfig ${epair}a inet6 accept_rtadv
+	jexec alcatraz ifconfig ${epair}a inet6 fe80::5a9c:fcff:fe10:5d07/127
+	jexec alcatraz ifconfig ${epair}a up
+
+	ifconfig ${epair}b inet6 -ifdisabled
+	ifconfig ${epair}b up
+
+	atf_check -e ignore python3 $(atf_get_srcdir)/ra.py \
+	    --sendif ${epair}b \
+	    --dst $(ndp_if_lladdr ${epair}a alcatraz) \
+	    --src $(ndp_if_lladdr ${epair}b) \
+	    --prefix "2001:db8:ffff:1000::" --prefixlen 64
+
+	atf_check \
+	    -o match:"inet6 2001:db8:ffff:1000:.* prefixlen 64.*autoconf.*" \
+	    jexec alcatraz ifconfig ${epair}a
+}
+
+ndp_prefix_len_mismatch_cleanup() {
+	vnet_cleanup
+}
+
 atf_init_test_cases()
 {
 	atf_add_test_case "ndp_add_gu_success"
 	atf_add_test_case "ndp_del_gu_success"
 	atf_add_test_case "ndp_slaac_default_route"
+	atf_add_test_case "ndp_prefix_len_mismatch"
 }
diff --git a/tests/sys/netpfil/pf/Makefile b/tests/sys/netpfil/pf/Makefile
index 7ddeb5369f47..b363e0b17c76 100644
--- a/tests/sys/netpfil/pf/Makefile
+++ b/tests/sys/netpfil/pf/Makefile
@@ -5,6 +5,7 @@ TESTS_SUBDIRS+=	ioctl
 
 ATF_TESTS_SH+=	altq \
 		anchor \
+		counters \
 		debug \
 		divert-to \
 		dup \
@@ -71,7 +72,7 @@ ATF_TESTS_PYTEST+=	tcp.py
 
 # Allow tests to run in parallel in their own jails
 TEST_METADATA+= execenv="jail"
-TEST_METADATA+= execenv_jail_params="vnet allow.raw_sockets"
+TEST_METADATA+= execenv_jail_params="vnet allow.raw_sockets allow.read_msgbuf"
 
 ${PACKAGE}FILES+=	\
 			bsnmpd.conf \
diff --git a/tests/sys/netpfil/pf/counters.sh b/tests/sys/netpfil/pf/counters.sh
new file mode 100644
index 000000000000..20d7dc3c6d89
--- /dev/null
+++ b/tests/sys/netpfil/pf/counters.sh
@@ -0,0 +1,831 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2025 Kajetan Staszkiewicz
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+
+. $(atf_get_srcdir)/utils.subr
+
+get_counters()
+{
+	echo " === rules ==="
+	rules=$(mktemp) || exit
+	(jexec router pfctl -qvvsn ; jexec router pfctl -qvvsr) | normalize_pfctl_s > $rules
+	cat $rules
+
+	echo " === tables ==="
+	tables=$(mktemp) || exit 1
+	jexec router pfctl -qvvsT > $tables
+	cat $tables
+
+	echo " === states ==="
+	states=$(mktemp) || exit 1
+	jexec router pfctl -qvvss | normalize_pfctl_s > $states
+	cat $states
+
+	echo " === nodes ==="
+	nodes=$(mktemp) || exit 1
+	jexec router pfctl -qvvsS | normalize_pfctl_s > $nodes
+	cat $nodes
+}
+
+atf_test_case "match_pass_state" "cleanup"
+match_pass_state_head()
+{
+	atf_set descr 'Counters on match and pass rules'
+	atf_set require.user root
+}
+
+match_pass_state_body()
+{
+	setup_router_server_ipv6
+
+	# Thest counters for a statefull firewall. Expose the behaviour of
+	# increasing table counters if a table is used multiple times.
+	# The table "tbl_in" is used both in match and pass rule. It's counters
+	# are incremented twice. The tables "tbl_out_match" and "tbl_out_pass"
+	# are used only once and have their countes increased only once.
+	# Test source node counters for this simple scenario too.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_in>  { ${net_tester_host_tester} }" \
+		"table <tbl_out_pass> { ${net_server_host_server} }" \
+		"table <tbl_out_match> { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"match in  on ${epair_tester}b inet6 proto tcp from <tbl_in>  scrub (random-id)" \
+		"pass  in  on ${epair_tester}b inet6 proto tcp from <tbl_in>  keep state (max-src-states 3 source-track rule)" \
+		"match out on ${epair_server}a inet6 proto tcp to   <tbl_out_match> scrub (random-id)" \
+		"pass  out on ${epair_server}a inet6 proto tcp to   <tbl_out_pass> keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_server} echo"
+	# Let FINs pass through.
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@3 match in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+		"@4 pass in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+		"@5 match out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@6 pass out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	table_counters_single="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	table_counters_double="Evaluations: NoMatch: 0 Match: 2 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 12 Bytes: 910 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 8 Bytes: 622 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_in___${table_counters_double}" \
+		"tbl_out_match___${table_counters_single}" \
+		"tbl_out_pass___${table_counters_single}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_tester}b tcp ${net_server_host_server}.* <- ${net_tester_host_tester}.* 6:4 pkts, 455:311 bytes, rule 4," \
+		"${epair_server}a tcp ${net_server_host_tester}.* -> ${net_server_host_server}.* 6:4 pkts, 455:311 bytes, rule 6," \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+
+	for node_regexp in \
+		"${net_tester_host_tester} -> :: .* 10 pkts, 766 bytes, filter rule 4, limit source-track"\
+	; do
+		grep -qE "${node_regexp}" $nodes || atf_fail "Source node not found for '${node_regexp}'"
+	done
+}
+
+match_pass_state_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "match_pass_no_state" "cleanup"
+match_pass_no_state_head()
+{
+	atf_set descr 'Counters on match and pass rules without keep state'
+	atf_set require.user root
+}
+
+match_pass_no_state_body()
+{
+	setup_router_server_ipv6
+
+	# Test counters for a stateless firewall.
+	# The table "tbl_in" is used both in match and pass rule in the inbound
+	# direction. The "In/Pass" counter is incremented twice. The table
+	# "tbl_inout" matches the same host on inbound and outbound direction.
+	# It will also be incremented twice. The tables "tbl_out_match" and
+	# "tbl_out_pass" will have their counters increased only once.
+	pft_set_rules router \
+		"table <tbl_in>        { ${net_tester_host_tester} }" \
+		"table <tbl_inout>     { ${net_tester_host_tester} }" \
+		"table <tbl_out_match> { ${net_server_host_server} }" \
+		"table <tbl_out_pass>  { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"match in  on ${epair_tester}b inet6 proto tcp from <tbl_inout>" \
+		"match in  on ${epair_tester}b inet6 proto tcp from <tbl_in>" \
+		"pass  in  on ${epair_tester}b inet6 proto tcp from <tbl_in> no state" \
+		"pass  out on ${epair_tester}b inet6 proto tcp to   <tbl_in> no state" \
+		"match in  on ${epair_server}a inet6 proto tcp from <tbl_out_match>" \
+		"pass  in  on ${epair_server}a inet6 proto tcp from <tbl_out_pass>  no state" \
+		"match out on ${epair_server}a inet6 proto tcp from <tbl_inout> no state" \
+		"pass  out on ${epair_server}a inet6 proto tcp to   <tbl_out_pass>  no state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_server} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@3 match in on ${epair_tester}b .* Packets: 6 Bytes: 455 " \
+		"@4 match in on ${epair_tester}b .* Packets: 6 Bytes: 455 " \
+		"@5 pass in on ${epair_tester}b .* Packets: 6 Bytes: 455 " \
+		"@6 pass out on ${epair_tester}b .* Packets: 4 Bytes: 311 " \
+		"@7 match in on ${epair_server}a .* Packets: 4 Bytes: 311 " \
+		"@8 pass in on ${epair_server}a .* Packets: 4 Bytes: 311 " \
+		"@10 pass out on ${epair_server}a .* Packets: 6 Bytes: 455 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	for table_test in \
+		"tbl_in___Evaluations: NoMatch: 0 Match: 16 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 12 Bytes: 910 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 4 Bytes: 311 Out/XPass: Packets: 0 Bytes: 0" \
+		"tbl_out_match___Evaluations: NoMatch: 0 Match: 4 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 0 Bytes: 0 Out/XPass: Packets: 0 Bytes: 0" \
+		"tbl_out_pass___Evaluations: NoMatch: 0 Match: 10 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0" \
+		"tbl_inout___Evaluations: NoMatch: 0 Match: 12 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 6 Bytes: 455 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+}
+
+match_pass_no_state_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "match_block" "cleanup"
+match_block_head()
+{
+	atf_set descr 'Counters on match and block rules'
+	atf_set require.user root
+}
+
+match_block_body()
+{
+	setup_router_server_ipv6
+
+	# Stateful firewall with a blocking rule. The rule will have its
+	# counters increased because it matches and applies correctly.
+	# The "match" rule before the "pass" rule will have its counters
+	# increased for blocked traffic too.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_in_match> { ${net_server_host_server} }" \
+		"table <tbl_in_block> { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"match  in on ${epair_tester}b inet6 proto tcp to   <tbl_in_match> scrub (random-id)" \
+		"block  in on ${epair_tester}b inet6 proto tcp to   <tbl_in_block>" \
+		"pass  out on ${epair_server}a inet6 proto tcp keep state"
+
+	# Wait 3 seconds, that will cause 2 SYNs to be sent out.
+	echo 'This is a test' | nc -w3 ${net_server_host_server} echo
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@3 match in on ${epair_tester}b .* Packets: 2 Bytes: 160 States: 0 " \
+		"@4 block drop in on ${epair_tester}b .* Packets: 2 Bytes: 160 States: 0 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# OpenBSD has (In|Out)/Match. We don't (yet) have it in FreeBSD
+	# so we follow the action of the "pass" rule ("block" for this test)
+	# in "match" rules.
+	for table_test in \
+		"tbl_in_match___Evaluations: NoMatch: 0 Match: 2 In/Block: Packets: 2 Bytes: 160 In/Pass: Packets: 0 Bytes: 0 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 0 Bytes: 0 Out/XPass: Packets: 0 Bytes: 0" \
+		"tbl_in_block___Evaluations: NoMatch: 0 Match: 2 In/Block: Packets: 2 Bytes: 160 In/Pass: Packets: 0 Bytes: 0 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 0 Bytes: 0 Out/XPass: Packets: 0 Bytes: 0" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+}
+
+match_block_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "match_fail" "cleanup"
+match_fail_head()
+{
+	atf_set descr 'Counters on match and failing pass rules'
+	atf_set require.user root
+}
+
+match_fail_body()
+{
+	setup_router_server_ipv6
+
+	# Statefull firewall with a failing "pass" rule.
+	# When the rule can't apply it will not have its counters increased.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_in_match> { ${net_server_host_server} }" \
+		"table <tbl_in_fail> { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"match  in on ${epair_tester}b inet6 proto tcp to <tbl_in_match> scrub (random-id)" \
+		"pass   in on ${epair_tester}b inet6 proto tcp to <tbl_in_fail> keep state (max 1)" \
+		"pass  out on ${epair_server}a inet6 proto tcp keep state"
+
+	# The first test will pass and increase the counters for all rules.
+	echo 'This is a test' | nc -w3 ${net_server_host_server} echo
+	# The second test will go through the "match" rules but fail
+	# on the "pass" rule due to 'keep state (max 1)'.
+	# Wait 3 seconds, that will cause 2 SYNs to be sent out.
+	echo 'This is a test' | nc -w3 ${net_server_host_server} echo
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@3 match in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+		"@4 pass in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	$table_counters_single="Evaluations: NoMatch: 0 Match: 3 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 6 Bytes: 455 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 4 Bytes: 311 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_in_match___${table_counters_single}" \
+		"tbl_in_fail___${table_counters_single}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+}
+
+match_fail_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "nat_natonly" "cleanup"
+nat_natonly_head()
+{
+	atf_set descr 'Counters on only a NAT rule creating state'
+	atf_set require.user root
+}
+
+nat_natonly_body()
+{
+	setup_router_server_ipv6
+
+	# NAT is applied on the "nat" rule.
+	# The "nat" rule matches on pre-NAT addresses. There is no separate
+	# "pass" rule so the "nat" rule creates the state.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_nat> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_nat> { ${net_server_host_server} }" \
+		"nat on ${epair_server}a inet6 proto tcp from <tbl_src_nat> to <tbl_dst_nat> -> ${net_server_host_router}"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_server} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@0 nat on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# All tables have counters increased for In/Pass and Out/Pass, not XPass.
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_nat___${table_counters}" \
+		"tbl_dst_nat___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"all tcp ${net_server_host_router}.* -> ${net_server_host_server}.* 6:4 pkts, 455:311 bytes" \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+}
+
+nat_natonly_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "nat_nat" "cleanup"
+nat_nat_head()
+{
+	atf_set descr 'Counters on NAT, match and pass rules with keep state'
+	atf_set require.user root
+}
+
+nat_nat_body()
+{
+	setup_router_server_ipv6
+
+	# NAT is applied in the NAT ruleset.
+	# The "nat" rule matches on pre-NAT addresses.
+	# The "match" rule matches on post-NAT addresses.
+	# The "pass" rule matches on post-NAT addresses and creates the state.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_nat> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_nat> { ${net_server_host_server} }" \
+		"table <tbl_src_match> { ${net_server_host_router} }" \
+		"table <tbl_dst_match> { ${net_server_host_server} }" \
+		"table <tbl_src_pass> { ${net_server_host_router} }" \
+		"table <tbl_dst_pass> { ${net_server_host_server} }" \
+		"nat on ${epair_server}a inet6 proto tcp from <tbl_src_nat> to <tbl_dst_nat> -> ${net_server_host_router}" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"pass  in  on ${epair_tester}b inet6 proto tcp keep state" \
+		"match out on ${epair_server}a inet6 proto tcp from <tbl_src_match> to <tbl_dst_match> scrub (random-id)" \
+		"pass  out on ${epair_server}a inet6 proto tcp from <tbl_src_pass>  to <tbl_dst_pass>  keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_server} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@0 nat on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@4 match out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@5 pass out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# All tables have counters increased for In/Pass and Out/Pass, not XPass nor Block.
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_nat___${table_counters}" \
+		"tbl_dst_nat___${table_counters}" \
+		"tbl_src_match___${table_counters}" \
+		"tbl_dst_match___${table_counters}" \
+		"tbl_src_pass___${table_counters}" \
+		"tbl_dst_pass___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_server}a tcp ${net_server_host_router}.* -> ${net_server_host_server}.* 6:4 pkts, 455:311 bytes, rule 5," \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+}
+
+nat_nat_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "nat_match" "cleanup"
+nat_match_head()
+{
+	atf_set descr 'Counters on match with NAT and pass rules'
+	atf_set require.user root
+}
+
+nat_match_body()
+{
+	setup_router_server_ipv6
+
+	# NAT is applied on the "match" rule.
+	# The "match" rule up to and including the NAT rule match on pre-NAT addresses.
+	# The "match" rule after NAT matches on post-NAT addresses.
+	# The "pass" rule matches on post-NAT addresses and creates the state.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_match1> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_match1> { ${net_server_host_server} }" \
+		"table <tbl_src_match2> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_match2> { ${net_server_host_server} }" \
+		"table <tbl_src_match3> { ${net_server_host_router} }" \
+		"table <tbl_dst_match3> { ${net_server_host_server} }" \
+		"table <tbl_src_pass> { ${net_server_host_router} }" \
+		"table <tbl_dst_pass> { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"pass  in  on ${epair_tester}b inet6 proto tcp keep state" \
+		"match out on ${epair_server}a inet6 proto tcp from <tbl_src_match1> to <tbl_dst_match1> scrub (random-id)" \
+		"match out on ${epair_server}a inet6 proto tcp from <tbl_src_match2> to <tbl_dst_match2> nat-to ${net_server_host_router}" \
+		"match out on ${epair_server}a inet6 proto tcp from <tbl_src_match3> to <tbl_dst_match3> scrub (random-id)" \
+		"pass  out on ${epair_server}a inet6 proto tcp from <tbl_src_pass>  to <tbl_dst_pass>  keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_server} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@4 match out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@5 match out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@6 match out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@7 pass out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# All tables have counters increased for In/Pass and Out/Pass, not XPass nor Block.
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_match1___${table_counters}" \
+		"tbl_dst_match1___${table_counters}" \
+		"tbl_src_match2___${table_counters}" \
+		"tbl_dst_match2___${table_counters}" \
+		"tbl_src_match3___${table_counters}" \
+		"tbl_dst_match3___${table_counters}" \
+		"tbl_src_pass___${table_counters}" \
+		"tbl_dst_pass___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_server}a tcp ${net_server_host_tester}.* -> ${net_server_host_server}.* 6:4 pkts, 455:311 bytes, rule 7, " \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+}
+
+nat_match_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "nat_pass" "cleanup"
+nat_pass_head()
+{
+	atf_set descr 'Counters on match, and pass with NAT rules'
+	atf_set require.user root
+}
+
+nat_pass_body()
+{
+	setup_router_server_ipv6
+
+	# NAT is applied on the "pass" rule which also creates the state.
+	# All rules match on pre-NAT addresses.
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_match> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_match> { ${net_server_host_server} }" \
+		"table <tbl_src_pass> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_pass> { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"pass  in  on ${epair_tester}b inet6 proto tcp keep state" \
+		"match out on ${epair_server}a inet6 proto tcp from <tbl_src_match> to <tbl_dst_match> scrub (random-id)" \
+		"pass  out on ${epair_server}a inet6 proto tcp from <tbl_src_pass>  to <tbl_dst_pass>  nat-to ${net_server_host_router} keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_server} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@4 match out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+		"@5 pass out on ${epair_server}a .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 311 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_match___${table_counters}" \
+		"tbl_dst_match___${table_counters}" \
+		"tbl_src_pass___${table_counters}" \
+		"tbl_dst_pass___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_server}a tcp ${net_server_host_router}.* -> ${net_server_host_server}.* 6:4 pkts, 455:311 bytes, rule 5," \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+}
+
+nat_pass_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "rdr_match" "cleanup"
+rdr_match_head()
+{
+	atf_set descr 'Counters on match with RDR and pass rules'
+	atf_set require.user root
+}
+
+rdr_match_body()
+{
+	setup_router_server_ipv6
+
+	# Similar to the nat_match test but for the RDR action.
+	# Hopefully we don't need all other tests duplicated for RDR.
+	# Send traffic to a non-existing host, RDR it to the server.
+	#
+	# The "match" rule up to and including the RDR rule match on pre-RDR dst address.
+	# The "match" rule after NAT matches on post-RDR dst address.
+	# The "pass" rule matches on post-RDR dst address.
+	net_server_host_notserver=${net_server_host_server%%::*}::3
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_match1> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_match1> { ${net_server_host_notserver} }" \
+		"table <tbl_src_match2> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_match2> { ${net_server_host_notserver} }" \
+		"table <tbl_src_match3> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_match3> { ${net_server_host_server} }" \
+		"table <tbl_src_pass> { ${net_tester_host_tester} }" \
+		"table <tbl_dst_pass> { ${net_server_host_server} }" \
+		"block" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"pass  out on ${epair_server}a inet6 proto tcp keep state" \
+		"match  in on ${epair_tester}b inet6 proto tcp from <tbl_src_match1> to <tbl_dst_match1> scrub (random-id)" \
+		"match  in on ${epair_tester}b inet6 proto tcp from <tbl_src_match2> to <tbl_dst_match2> rdr-to ${net_server_host_server}" \
+		"match  in on ${epair_tester}b inet6 proto tcp from <tbl_src_match3> to <tbl_dst_match3> scrub (random-id)" \
+		"pass   in on ${epair_tester}b inet6 proto tcp from <tbl_src_pass>  to <tbl_dst_pass>  keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 ${net_server_host_notserver} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@4 match in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+		"@5 match in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+		"@6 match in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+		"@7 pass in on ${epair_tester}b .* Packets: 10 Bytes: 766 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# All tables have counters increased for In/Pass and Out/Pass, not XPass nor Block.
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 6 Bytes: 455 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 4 Bytes: 311 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_match1___${table_counters}" \
+		"tbl_dst_match1___${table_counters}" \
+		"tbl_src_match2___${table_counters}" \
+		"tbl_dst_match2___${table_counters}" \
+		"tbl_src_match3___${table_counters}" \
+		"tbl_dst_match3___${table_counters}" \
+		"tbl_src_pass___${table_counters}" \
+		"tbl_dst_pass___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_tester}b tcp ${net_server_host_server}.* 6:4 pkts, 455:311 bytes, rule 7, " \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+}
+
+rdr_match_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "nat64_in" "cleanup"
+nat64_in_head()
+{
+	atf_set descr 'Counters on match and inbound af-to rules'
+	atf_set require.user root
+}
+
+nat64_in_body()
+{
+	setup_router_server_nat64
+
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_match> { ${net_tester_6_host_tester} }" \
+		"table <tbl_dst_match> { 64:ff9b::${net_server1_4_host_server} }" \
+		"table <tbl_src_pass>  { ${net_tester_6_host_tester} }" \
+		"table <tbl_dst_pass>  { 64:ff9b::${net_server1_4_host_server} }" \
+		"block log" \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"match  in on ${epair_tester}b inet6 proto tcp from <tbl_src_match> to <tbl_dst_match> scrub (random-id)" \
+		"pass   in on ${epair_tester}b inet6 proto tcp from <tbl_src_pass>  to <tbl_dst_pass> \
+			af-to inet from (${epair_server1}a) \
+			keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 64:ff9b::${net_server1_4_host_server} echo"
+	sleep 1
+	get_counters
+
+	# The amount of packets is counted properly but sizes are not because
+	# pd->tot_len is always post-nat, even when updating pre-nat counters.
+	for rule_regexp in \
+		"@3 match in on ${epair_tester}b .* Packets: 10 Bytes: 686 States: 1 " \
+		"@4 pass in on ${epair_tester}b .* Packets: 10 Bytes: 686 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# All tables have counters increased for In/Pass and Out/Pass, not XPass nor Block.
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 231 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_match___${table_counters}" \
+		"tbl_dst_match___${table_counters}" \
+		"tbl_src_pass___${table_counters}" \
+		"tbl_dst_pass___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_server1}a tcp ${net_server_host_tester}.* 6:4 pkts, 455:231 bytes, rule 4, " \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+
+	echo " === interfaces === "
+	echo " === tester === "
+	jexec router pfctl -qvvsI -i ${epair_tester}b
+	echo " === server === "
+	jexec router pfctl -qvvsI -i ${epair_server1}a
+	echo " === "
+}
+
+nat64_in_cleanup()
+{
+	pft_cleanup
+}
+
+atf_test_case "nat64_out" "cleanup"
+nat64_out_head()
+{
+	atf_set descr 'Counters on match and outbound af-to rules'
+	atf_set require.user root
+}
+
+nat64_out_body()
+{
+	setup_router_server_nat64
+
+	# af-to in outbound path requires routes for the pre-af-to traffic.
+	jexec router route add -inet6 64:ff9b::/96 -iface ${epair_server1}a
+
+	pft_set_rules router \
+		"set state-policy if-bound" \
+		"table <tbl_src_match> { ${net_tester_6_host_tester} }" \
+		"table <tbl_dst_match> { 64:ff9b::${net_server1_4_host_server} }" \
+		"table <tbl_src_pass>  { ${net_tester_6_host_tester} }" \
+		"table <tbl_dst_pass>  { 64:ff9b::${net_server1_4_host_server} }" \
+		"block log " \
+		"pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
+		"pass  in  on ${epair_tester}b inet6 proto tcp keep state" \
+		"match out on ${epair_server1}a inet6 proto tcp from <tbl_src_match> to <tbl_dst_match> scrub (random-id)" \
+		"pass  out on ${epair_server1}a inet6 proto tcp from <tbl_src_pass>  to <tbl_dst_pass> \
+			af-to inet from (${epair_server1}a) \
+			keep state"
+
+	# Use a real TCP connection so that it will be properly closed, guaranteeing the amount of packets.
+	atf_check -s exit:0 -o match:"This is a test" -x \
+		"echo 'This is a test' | nc -w3 64:ff9b::${net_server1_4_host_server} echo"
+	sleep 1
+	get_counters
+
+	for rule_regexp in \
+		"@4 match out on ${epair_server1}a .* Packets: 10 Bytes: 686 States: 1 " \
+		"@5 pass out on ${epair_server1}a .* Packets: 10 Bytes: 686 States: 1 " \
+	; do
+		grep -qE "${rule_regexp}" $rules || atf_fail "Rule regexp not found for '${rule_regexp}'"
+	done
+
+	# All tables have counters increased for In/Pass and Out/Pass, not XPass nor Block.
+	table_counters="Evaluations: NoMatch: 0 Match: 1 In/Block: Packets: 0 Bytes: 0 In/Pass: Packets: 4 Bytes: 231 In/XPass: Packets: 0 Bytes: 0 Out/Block: Packets: 0 Bytes: 0 Out/Pass: Packets: 6 Bytes: 455 Out/XPass: Packets: 0 Bytes: 0"
+	for table_test in \
+		"tbl_src_match___${table_counters}" \
+		"tbl_dst_match___${table_counters}" \
+		"tbl_src_pass___${table_counters}" \
+		"tbl_dst_pass___${table_counters}" \
+	; do
+		table_name=${table_test%%___*}
+		table_regexp=${table_test##*___}
+		table=$(mktemp) || exit 1
+		cat $tables | grep -A10 $table_name | tr '\n' ' ' | awk '{gsub("[\\[\\]]", " ", $0); gsub("[[:blank:]]+"," ",$0); print $0}' > ${table}
+		grep -qE "${table_regexp}" ${table} || atf_fail "Bad counters for table ${table_name}"
+	done;
+
+	for state_regexp in \
+		"${epair_server1}a tcp 198.51.100.17:[0-9]+ \(64:ff9b::c633:6412\[7\]\) -> 198.51.100.18:7 \(2001:db8:4200::2\[[0-9]+\]\) .* 6:4 pkts, 455:231 bytes, rule 5," \
+	; do
+		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
+	done
+
+	echo " === interfaces === "
+	echo " === tester === "
+	jexec router pfctl -qvvsI -i ${epair_tester}b
+	echo " === server === "
+	jexec router pfctl -qvvsI -i ${epair_server1}a
+	echo " === "
+}
+
+nat64_out_cleanup()
+{
+	pft_cleanup
+}
+
+atf_init_test_cases()
+{
+	atf_add_test_case "match_pass_state"
+	atf_add_test_case "match_pass_no_state"
+	atf_add_test_case "match_block"
+	atf_add_test_case "match_fail"
+	atf_add_test_case "nat_natonly"
+	atf_add_test_case "nat_nat"
+	atf_add_test_case "nat_match"
+	atf_add_test_case "nat_pass"
+	atf_add_test_case "rdr_match"
+	atf_add_test_case "nat64_in"
+	atf_add_test_case "nat64_out"
+}
diff --git a/tests/sys/netpfil/pf/mld.py b/tests/sys/netpfil/pf/mld.py
index d118a34c8a7d..b3ef6c21b3de 100644
--- a/tests/sys/netpfil/pf/mld.py
+++ b/tests/sys/netpfil/pf/mld.py
@@ -32,23 +32,22 @@ from atf_python.sys.net.vnet import VnetTestTemplate
 class TestMLD(VnetTestTemplate):
     REQUIRED_MODULES = [ "pf" ]
     TOPOLOGY = {
-        "vnet1": {"ifaces": ["if1"]},
+        "vnet1": {"ifaces": ["if1"], "opts": ["allow.read_msgbuf"]},
         "vnet2": {"ifaces": ["if1"]},
         "if1": {"prefixes6": [("2001:db8::2/64", "2001:db8::1/64")]},
     }
 
     def vnet2_handler(self, vnet):
         ifname = vnet.iface_alias_map["if1"].name
-        #ToolsHelper.print_output("/sbin/pfctl -e")
+        ToolsHelper.print_output("/sbin/pfctl -e")
         ToolsHelper.pf_rules([
             "pass",
             ])
         ToolsHelper.print_output("/sbin/pfctl -x loud")
-        #ToolsHelper.print_output("echo \"j 230.0.0.1 %s\ns 3600\nq\" | /usr/sbin/mtest" % ifname)
 
     def find_mld_reply(self, pkt, ifname):
         pkt.show()
-        s = DelayedSend(pkt)
+        s = DelayedSend(pkt, ifname)
 
         found = False
         packets = self.sp.sniff(iface=ifname, timeout=5)
@@ -66,7 +65,6 @@ class TestMLD(VnetTestTemplate):
     def test_router_alert(self):
         """Verify that we allow MLD packets with router alert extension header"""
         ifname = self.vnet.iface_alias_map["if1"].name
-        #ToolsHelper.print_output("/sbin/ifconfig %s inet6 -ifdisable" % ifname)
         ToolsHelper.print_output("/sbin/ifconfig")
 
         # Import in the correct vnet, so at to not confuse Scapy
@@ -76,20 +74,17 @@ class TestMLD(VnetTestTemplate):
         self.sp = sp
         self.sc = sc
 
-        # A correct MLD query gets a reply
-        pkt = sp.IPv6(src="fe80::1%%%s" % ifname, dst="ff02::1", hlim=1) \
-            / sp.RouterAlert(value=0) \
+        # MLD packets with an incorrect hop limit get dropped.
+        pkt = sp.Ether() \
+            / sp.IPv6(src="fe80::1%%%s" % ifname, dst="ff02::1", hlim=2) \
+            / sp.IPv6ExtHdrHopByHop(options=[ \
+                sp.RouterAlert(value=0) \
+                ]) \
             / sp.ICMPv6MLQuery2()
-        assert self.find_mld_reply(pkt, ifname)
+        # We can't reliably test this by checking for a reply, because
+        # the other jail may just send a spontaneous MLD reply.
+        self.find_mld_reply(pkt, ifname)
 
-        # The wrong extension header does not
-        pkt = sp.IPv6(src="fe80::1%%%s" % ifname, dst="ff02::1", hlim=1) \
-            / sp.IPv6ExtHdrRouting() \
-            / sp.ICMPv6MLQuery2()
-        assert not self.find_mld_reply(pkt, ifname)
-
-        # Neither does an incorrect hop limit
-        pkt = sp.IPv6(src="fe80::1%%%s" % ifname, dst="ff02::1", hlim=2) \
-            / sp.RouterAlert(value=0) \
-            / sp.ICMPv6MLQuery2()
-        assert not self.find_mld_reply(pkt, ifname)
+        # Check if we logged dropping the MLD paacket
+        dmesg = ToolsHelper.get_output("/sbin/dmesg")
+        assert dmesg.find("Invalid MLD") != -1
diff --git a/tests/sys/netpfil/pf/nat.sh b/tests/sys/netpfil/pf/nat.sh
index 170d813d57fe..e55f46418221 100644
--- a/tests/sys/netpfil/pf/nat.sh
+++ b/tests/sys/netpfil/pf/nat.sh
@@ -838,7 +838,7 @@ dummynet_mask_body()
 	jexec gw dnctl pipe 1 config delay 100 mask src-ip 0xffffff00
 	jexec gw pfctl -e
 	pft_set_rules gw \
-	    "nat pass on ${epair_srv}b inet from 192.0.2.0/24 to any -> (${epair_srv}b)" \
+	    "nat on ${epair_srv}b inet from 192.0.2.0/24 to any -> (${epair_srv}b)" \
 	    "pass out dnpipe 1"
 
 	atf_check -s exit:0 -o ignore \
diff --git a/tests/sys/netpfil/pf/nat64.sh b/tests/sys/netpfil/pf/nat64.sh
index d930e2ee5763..6631e3eca2c7 100644
--- a/tests/sys/netpfil/pf/nat64.sh
+++ b/tests/sys/netpfil/pf/nat64.sh
@@ -213,12 +213,14 @@ tcp_in_if_bound_body()
 		atf_fail "Failed to connect to TCP server"
 	fi
 
+	sleep 1
+
 	# Interfaces of the state are reversed when doing inbound NAT64!
-	# FIXME: Packets counters seem wrong!
+	# FIXME: Packets from both directions are counted only on the inbound direction!
 	states=$(mktemp) || exit 1
 	jexec rtr pfctl -qvvss | normalize_pfctl_s > $states
 	for state_regexp in \
-		"${epair_link}a tcp 192.0.2.1:[0-9]+ \(2001:db8::2\[[0-9]+\]\) -> 192.0.2.2:1234 \(64:ff9b::c000:202\[1234\]\) .* 9:9 pkts.* rule 3 .* origif: ${epair}b" \
+		"${epair_link}a tcp 192.0.2.1:[0-9]+ \(2001:db8::2\[[0-9]+\]\) -> 192.0.2.2:1234 \(64:ff9b::c000:202\[1234\]\) .* 5:4 pkts.* rule 3 .* origif: ${epair}b" \
 	; do
 		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
 	done
@@ -254,6 +256,8 @@ tcp_out_if_bound_body()
 		atf_fail "Failed to connect to TCP server"
 	fi
 
+	sleep 1
+
 	# Origif is not printed when identical as if.
 	states=$(mktemp) || exit 1
 	jexec rtr pfctl -qvvss | normalize_pfctl_s > $states
@@ -295,12 +299,14 @@ tcp_in_floating_body()
 		atf_fail "Failed to connect to TCP server"
 	fi
 
+	sleep 1
+
 	# Interfaces of the state are reversed when doing inbound NAT64!
-	# FIXME: Packets counters seem wrong!
+	# FIXME: Packets from both directions are counted only on the inbound direction!
 	states=$(mktemp) || exit 1
 	jexec rtr pfctl -qvvss | normalize_pfctl_s > $states
 	for state_regexp in \
-		"all tcp 192.0.2.1:[0-9]+ \(2001:db8::2\[[0-9]+\]\) -> 192.0.2.2:1234 \(64:ff9b::c000:202\[1234\]\).* 9:9 pkts.* rule 3 .* origif: ${epair}b" \
+		"all tcp 192.0.2.1:[0-9]+ \(2001:db8::2\[[0-9]+\]\) -> 192.0.2.2:1234 \(64:ff9b::c000:202\[1234\]\).* 5:4 pkts.* rule 3 .* origif: ${epair}b" \
 	; do
 		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
 	done
@@ -336,6 +342,8 @@ tcp_out_floating_body()
 		atf_fail "Failed to connect to TCP server"
 	fi
 
+	sleep 1
+
 	# Origif is not printed when identical as if.
 	states=$(mktemp) || exit 1
 	jexec rtr pfctl -qvvss | normalize_pfctl_s > $states
@@ -1011,20 +1019,19 @@ route_to_body()
 	pft_init
 
 	epair_link=$(vnet_mkepair)
-	epair_null=$(vnet_mkepair)
 	epair=$(vnet_mkepair)
 
 	ifconfig ${epair}a inet6 2001:db8::2/64 up no_dad
 	route -6 add default 2001:db8::1
 
-	vnet_mkjail rtr ${epair}b ${epair_link}a ${epair_null}a
+	vnet_mkjail rtr ${epair}b ${epair_link}a
 	jexec rtr ifconfig ${epair}b inet6 2001:db8::1/64 up no_dad
-	jexec rtr ifconfig ${epair_null}a 192.0.2.3/24 up
 	jexec rtr ifconfig ${epair_link}a 192.0.2.1/24 up
 
 	vnet_mkjail dst ${epair_link}b
 	jexec dst ifconfig ${epair_link}b 192.0.2.2/24 up
-	jexec dst route add default 192.0.2.1
+	jexec dst ifconfig lo0 203.0.113.1/32 alias
+	jexec dst route add default 192.0.2.2
 
 	# Sanity checks
 	atf_check -s exit:0 -o ignore \
@@ -1033,8 +1040,9 @@ route_to_body()
 	jexec rtr pfctl -e
 	pft_set_rules rtr \
 	    "set reassemble yes" \
+	    "set debug loud" \
 	    "set state-policy if-bound" \
-	    "block" \
+	    "block log (all)" \
 	    "pass inet6 proto icmp6 icmp6-type { neighbrsol, neighbradv }" \
 	    "pass in on ${epair}b route-to (${epair_link}a 192.0.2.2) inet6 from any to 64:ff9b::/96 af-to inet from (${epair_link}a)"
 
@@ -1044,9 +1052,11 @@ route_to_body()
 
 	states=$(mktemp) || exit 1
 	jexec rtr pfctl -qvvss | normalize_pfctl_s > $states
+	cat $states
 
+	# Interfaces of the state are reversed when doing inbound NAT64!
 	for state_regexp in \
-		"${epair_link}a ipv6-icmp 192.0.2.1:.* \(2001:db8::2\[[0-9]+\]\) -> 192.0.2.2:8 \(64:ff9b::c000:202\[[0-9]+\]\).*6:6 pkts.*route-to: 192.0.2.2@${epair_link}a origif: ${epair}b" \
+		"${epair_link}a ipv6-icmp 192.0.2.1:.* \(2001:db8::2\[[0-9]+\]\) -> 192.0.2.2:8 \(64:ff9b::c000:202\[[0-9]+\]\).* 3:3 pkts.*route-to: 192.0.2.2@${epair_link}a origif: ${epair}b" \
 	; do
 		grep -qE "${state_regexp}" $states || atf_fail "State not found for '${state_regexp}'"
 	done
diff --git a/tests/sys/netpfil/pf/rdr.sh b/tests/sys/netpfil/pf/rdr.sh
index f7c920bbfa8f..24b95b2047f4 100644
--- a/tests/sys/netpfil/pf/rdr.sh
+++ b/tests/sys/netpfil/pf/rdr.sh
@@ -281,8 +281,66 @@ srcport_pass_cleanup()
 	pft_cleanup
 }
 
+atf_test_case "natpass" "cleanup"
+natpass_head()
+{
+	atf_set descr 'Test rdr pass'
+	atf_set require.user root
+}
+
+natpass_body()
+{
+	pft_init
+
+	epair=$(vnet_mkepair)
+	epair_link=$(vnet_mkepair)
+
+	ifconfig ${epair}a 192.0.2.2/24 up
+
+	vnet_mkjail alcatraz ${epair}b ${epair_link}a
+	jexec alcatraz ifconfig lo0 inet 127.0.0.1/8 up
+	jexec alcatraz ifconfig ${epair}b inet 192.0.2.1/24 up
+	jexec alcatraz ifconfig ${epair_link}a 198.51.100.1/24 up
+	jexec alcatraz sysctl net.inet.ip.forwarding=1
+
+	vnet_mkjail srv ${epair_link}b
+	jexec srv ifconfig ${epair_link}b inet 198.51.100.2/24 up
+	jexec srv route add default 198.51.100.1
+
+	# Sanity check
+	atf_check -s exit:0 -o ignore \
+	    ping -c 1 192.0.2.1
+	atf_check -s exit:0 -o ignore \
+	    jexec alcatraz ping -c 1 198.51.100.2
+
+	jexec alcatraz pfctl -e
+	pft_set_rules alcatraz \
+	    "rdr pass on ${epair}b proto udp from any to 192.0.2.1 port 80 -> 198.51.100.2" \
+	    "nat on ${epair}b inet from 198.51.100.0/24 to any -> 192.0.2.1" \
+	    "block in proto udp from any to any port 80" \
+	    "pass in proto icmp"
+
+	echo "foo" | jexec srv nc -u -l 80 &
+	sleep 1 # Give the above a moment to start
+
+	out=$(echo 1 | nc -u -w 1 192.0.2.1 80)
+	echo "out ${out}"
+	if [ "${out}" != "foo" ];
+	then
+		jexec alcatraz pfctl -sn -vv
+		jexec alcatraz pfctl -ss -vv
+		atf_fail "rdr failed"
+	fi
+}
+
+natpass_cleanup()
+{
+	pft_cleanup
+}
+
 atf_init_test_cases()
 {
+	atf_add_test_case "natpass"
 	atf_add_test_case "tcp_v6_compat"
 	atf_add_test_case "tcp_v6_pass"
 	atf_add_test_case "srcport_compat"
diff --git a/tests/sys/netpfil/pf/utils.subr b/tests/sys/netpfil/pf/utils.subr
index a48f26653f8c..8b3b06bf3bba 100644
--- a/tests/sys/netpfil/pf/utils.subr
+++ b/tests/sys/netpfil/pf/utils.subr
@@ -217,6 +217,7 @@ setup_router_server_ipv4()
 	jexec server route add -net ${net_tester} ${net_server_host_router}
 	inetd_conf=$(mktemp)
 	echo "discard stream tcp nowait root internal" > $inetd_conf
+	echo "echo stream tcp nowait root internal" >> $inetd_conf
 	jexec server inetd -p ${PWD}/inetd.pid $inetd_conf
 }
 
@@ -271,6 +272,7 @@ setup_router_server_ipv6()
 	jexec server route add -6 ${net_tester} ${net_server_host_router}
 	inetd_conf=$(mktemp)
 	echo "discard stream tcp6 nowait root internal" > $inetd_conf
+	echo "echo stream tcp6 nowait root internal" >> $inetd_conf
 	jexec server inetd -p ${PWD}/inetd.pid $inetd_conf
 }
 
@@ -353,6 +355,7 @@ setup_router_server_nat64()
 
 	inetd_conf=$(mktemp)
 	echo "discard stream tcp46 nowait root internal" >> $inetd_conf
+	echo "echo stream tcp46 nowait root internal" >> $inetd_conf
 
 	vnet_mkjail server1 ${epair_server1}b
 	jexec server1 /etc/rc.d/netif start lo0
diff --git a/tests/sys/sys/bitstring_test.c b/tests/sys/sys/bitstring_test.c
index a48042a4a063..bf436040c00f 100644
--- a/tests/sys/sys/bitstring_test.c
+++ b/tests/sys/sys/bitstring_test.c
@@ -559,14 +559,13 @@ BITSTRING_TC_DEFINE(bit_nclear)
 			bit_nclear(bitstr, i, j);
 
 			bit_ffc(bitstr, nbits, &found_clear_bit);
-			ATF_REQUIRE_MSG(
-			    found_clear_bit == i,
+			ATF_REQUIRE_INTEQ_MSG(i, found_clear_bit,
 			    "bit_nclear_%d_%d_%d%s: Failed with result %d",
 			    nbits, i, j, memloc, found_clear_bit);
 
 			bit_ffs_at(bitstr, i, nbits, &found_set_bit);
-			ATF_REQUIRE_MSG(
-			    (j + 1 < nbits) ? found_set_bit == j + 1 : -1,
+			ATF_REQUIRE_INTEQ_MSG((j + 1 < nbits) ? j + 1 : -1,
+			    found_set_bit,
 			    "bit_nset_%d_%d_%d%s: Failed with result %d",
 			    nbits, i, j, memloc, found_set_bit);
 		}
@@ -586,14 +585,13 @@ BITSTRING_TC_DEFINE(bit_nset)
 			bit_nset(bitstr, i, j);
 
 			bit_ffs(bitstr, nbits, &found_set_bit);
-			ATF_REQUIRE_MSG(
-			    found_set_bit == i,
+			ATF_REQUIRE_INTEQ_MSG(i, found_set_bit,
 			    "bit_nset_%d_%d_%d%s: Failed with result %d",
 			    nbits, i, j, memloc, found_set_bit);
 
 			bit_ffc_at(bitstr, i, nbits, &found_clear_bit);
-			ATF_REQUIRE_MSG(
-			    (j + 1 < nbits) ? found_clear_bit == j + 1 : -1,
+			ATF_REQUIRE_INTEQ_MSG((j + 1 < nbits) ? j + 1 : -1,
+			    found_clear_bit,
 			    "bit_nset_%d_%d_%d%s: Failed with result %d",
 			    nbits, i, j, memloc, found_clear_bit);
 		}
diff --git a/tools/build/Makefile b/tools/build/Makefile
index 3c4e07e3cfc2..09351900599a 100644
--- a/tools/build/Makefile
+++ b/tools/build/Makefile
@@ -497,6 +497,7 @@ INSTALLDIR_LIST= \
 	usr/include/casper \
 	usr/include/openssl \
 	usr/include/private/ucl \
+	usr/include/private/yaml \
 	usr/include/private/zstd \
 	usr/lib \
 	usr/libdata/pkgconfig \
diff --git a/tools/build/mk/OptionalObsoleteFiles.inc b/tools/build/mk/OptionalObsoleteFiles.inc
index 2ca0c3275f41..13d7703148d2 100644
--- a/tools/build/mk/OptionalObsoleteFiles.inc
+++ b/tools/build/mk/OptionalObsoleteFiles.inc
@@ -2045,21 +2045,14 @@ OLD_FILES+=usr/share/man/man8/phttpget.8.gz
 .endif
 
 .if ${MK_FTP} == no
-OLD_FILES+=etc/ftpusers
-OLD_FILES+=etc/newsyslog.conf.d/ftp.conf
 OLD_FILES+=etc/pam.d/ftp
 OLD_FILES+=etc/pam.d/ftpd
-OLD_FILES+=etc/rc.d/ftpd
-OLD_FILES+=etc/syslog.d/ftp.conf
 OLD_FILES+=usr/bin/ftp
 OLD_FILES+=usr/bin/gate-ftp
 OLD_FILES+=usr/bin/pftp
-OLD_FILES+=usr/libexec/ftpd
 OLD_FILES+=usr/share/man/man1/ftp.1.gz
 OLD_FILES+=usr/share/man/man1/gate-ftp.1.gz
 OLD_FILES+=usr/share/man/man1/pftp.1.gz
-OLD_FILES+=usr/share/man/man5/ftpchroot.5.gz
-OLD_FILES+=usr/share/man/man8/ftpd.8.gz
 .endif
 
 .if ${MK_GAMES} == no
diff --git a/tools/build/options/WITHOUT_BLACKLIST_SUPPORT b/tools/build/options/WITHOUT_BLACKLIST_SUPPORT
index 2bf22ea42ab6..ff1c2c43d595 100644
--- a/tools/build/options/WITHOUT_BLACKLIST_SUPPORT
+++ b/tools/build/options/WITHOUT_BLACKLIST_SUPPORT
@@ -1,7 +1,6 @@
 Build some programs without
 .Xr libblacklist 3
 support, like
-.Xr fingerd 8 ,
-.Xr ftpd 8 ,
+.Xr fingerd 8
 and
 .Xr sshd 8 .
diff --git a/tools/build/options/WITHOUT_FTP b/tools/build/options/WITHOUT_FTP
index 2e55ccc46ef6..a1db09d2fe8f 100644
--- a/tools/build/options/WITHOUT_FTP
+++ b/tools/build/options/WITHOUT_FTP
@@ -1,4 +1,2 @@
 Do not build or install
-.Xr ftp 1
-and
-.Xr ftpd 8 .
+.Xr ftp 1 .
diff --git a/tools/build/options/WITHOUT_PAM_SUPPORT b/tools/build/options/WITHOUT_PAM_SUPPORT
index 323a83cf6192..89cf0e248f3f 100644
--- a/tools/build/options/WITHOUT_PAM_SUPPORT
+++ b/tools/build/options/WITHOUT_PAM_SUPPORT
@@ -1,4 +1,3 @@
-Build some programs without PAM support, particularly
-.Xr ftpd 8
-and
-.Xr ppp 8 .
+Build
+.Xr ppp 8
+without PAM support.
diff --git a/tools/test/stress2/misc/all.exclude b/tools/test/stress2/misc/all.exclude
index f9b32db95799..0658bfdc0c1b 100644
--- a/tools/test/stress2/misc/all.exclude
+++ b/tools/test/stress2/misc/all.exclude
@@ -25,6 +25,7 @@ gnop13.sh		https://people.freebsd.org/~pho/stress/log/log0386.txt		20221113
 gnop7.sh		Waiting for patch commit					20190820
 gnop8.sh		Waiting for patch commit					20201214
 gnop9.sh		Waiting for patch commit					20201214
+graid1_3.sh		Hang seen							20250915
 graid1_8.sh		Known issue							20170909
 graid1_9.sh		panic: Bad effnlink						20180212
 lockf5.sh		Spinning threads seen						20160718
@@ -74,10 +75,13 @@ syzkaller67.sh		panic: ASan: Invalid access, 8-byte read at ...			20230621
 syzkaller80.sh		panic								20250711
 syzkaller81.sh		panic								20250711
 syzkaller82.sh		panic: m_apply, length > size of mbuf chain			20250724
+syzkaller84.sh		panic: Assertion !(sb->sb_state & SBS_CANTRCVMORE)		20250810
+syzkaller85.sh		panic: Assertion uio->uio_resid < 0 failed			20250928
+syzkaller86.sh		Fatal trap 12: page fault while in kernel mode			20251001
+write2.sh		panic: sndbuf_acquire: count 255 > free 0			20251003
 quota3.sh		https://people.freebsd.org/~pho/stress/log/log0604.txt		20250728
 quota6.sh		https://people.freebsd.org/~pho/stress/log/log0456.txt		20240707
 truss3.sh		WiP								20200915
-zfs18.sh		https://people.freebsd.org/~pho/stress/log/log0560.txt		20241118
 zfs9.sh			panic: sacked_bytes < 0						20250711
 
 # Test not to run for other reasons:
diff --git a/tools/test/stress2/misc/fuzz.sh b/tools/test/stress2/misc/fuzz.sh
index 189cdbfebd01..add3d0d19a21 100755
--- a/tools/test/stress2/misc/fuzz.sh
+++ b/tools/test/stress2/misc/fuzz.sh
@@ -49,6 +49,7 @@
 . ../default.cfg
 
 D=$diskimage
+backup=/tmp/fuzz.sh.diskimage.`date +%Y%m%dT%H%M%S`.gz
 
 tst() {
    rm -f $D
@@ -62,6 +63,7 @@ tst() {
 
    for i in `jot 50`; do
       ./fuzz -n 50 $D
+      gzip < $D > $backup
       if fsck -f -y /dev/md$mdstart 2>&1 | egrep "^[A-Z]" > /dev/null; then
          if fsck -f -y /dev/md$mdstart 2>&1 | egrep "^[A-Z]" > /dev/null; then
             if fsck -f -y /dev/md$mdstart 2>&1 | egrep "^[A-Z]" > /dev/null; then
@@ -73,7 +75,7 @@ tst() {
       sync;sync;sync
       if mount /dev/md$mdstart $mntpoint; then
          ls -l $mntpoint > /dev/null
-         find $mntpoint  -exec dd if={} of=/dev/null bs=1m count=3 \; > /dev/null 2>&1
+         find $mntpoint  -type f -exec dd if={} of=/dev/null bs=1m count=3 \; > /dev/null 2>&1
          umount $mntpoint
       else
          echo "Giving up at loop $i"
@@ -96,7 +98,7 @@ for j in `jot 10`; do
    date '+%T'
    tst
 done
-rm -f fuzz
+rm -f fuzz $backup
 
 exit
 
diff --git a/tools/test/stress2/misc/syzkaller84.sh b/tools/test/stress2/misc/syzkaller84.sh
new file mode 100755
index 000000000000..a7976be2eeb6
--- /dev/null
+++ b/tools/test/stress2/misc/syzkaller84.sh
@@ -0,0 +1,402 @@
+#!/bin/sh
+
+# panic: Assertion !(sb->sb_state & SBS_CANTRCVMORE) failed at ../../../kern/uipc_usrreq.c:1549
+# cpuid = 6
+# time = 1754809105
+# KDB: stack backtrace:
+# db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe0176ef6a80
+# vpanic() at vpanic+0x136/frame 0xfffffe0176ef6bb0
+# panic() at panic+0x43/frame 0xfffffe0176ef6c10
+# uipc_soreceive_stream_or_seqpacket() at uipc_soreceive_stream_or_seqpacket+0x968/frame 0xfffffe0176ef6cd0
+# soreceive() at soreceive+0x45/frame 0xfffffe0176ef6cf0
+# kern_recvit() at kern_recvit+0x181/frame 0xfffffe0176ef6da0
+# sys_recvmsg() at sys_recvmsg+0x67/frame 0xfffffe0176ef6e00
+# amd64_syscall() at amd64_syscall+0x169/frame 0xfffffe0176ef6f30
+# fast_syscall_common() at fast_syscall_common+0xf8/frame 0xfffffe0176ef6f30
+# --- syscall (0, FreeBSD ELF64, syscall), rip = 0x821d3da8a, rsp = 0x824440f68, rbp = 0x824440f90 ---
+# KDB: enter: panic
+# [ thread pid 17448 tid 292963 ]
+# Stopped at      kdb_enter+0x33: movq    $0,0x12304a2(%rip)
+# db> x/s version
+# version: FreeBSD 15.0-PRERELEASE #0 main-n279510-db7c0e32a05d-dirty: Sat Aug  9 17:21:54 CEST 2025
+# pho@mercat1.netperf.freebsd.org:/usr/src/sys/amd64/compile/PHO
+# db> 
+
+[ `id -u ` -ne 0 ] && echo "Must be root!" && exit 1
+
+. ../default.cfg
+set -u
+prog=$(basename "$0" .sh)
+cat > /tmp/$prog.c <<EOF
+// https://syzkaller.appspot.com/bug?id=79d6de939eb5c7de69e8e4993b6239aa0ae67335
+// autogenerated by syzkaller (https://github.com/google/syzkaller)
+// syzbot+ffcc3612ea266e36604e@syzkaller.appspotmail.com
+
+#define _GNU_SOURCE
+
+#include <sys/types.h>
+
+#include <errno.h>
+#include <pthread.h>
+#include <pwd.h>
+#include <signal.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/endian.h>
+#include <sys/resource.h>
+#include <sys/syscall.h>
+#include <sys/wait.h>
+#include <time.h>
+#include <unistd.h>
+
+static unsigned long long procid;
+
+static void kill_and_wait(int pid, int* status)
+{
+  kill(pid, SIGKILL);
+  while (waitpid(-1, status, 0) != pid) {
+  }
+}
+
+static void sleep_ms(uint64_t ms)
+{
+  usleep(ms * 1000);
+}
+
+static uint64_t current_time_ms(void)
+{
+  struct timespec ts;
+  if (clock_gettime(CLOCK_MONOTONIC, &ts))
+    exit(1);
+  return (uint64_t)ts.tv_sec * 1000 + (uint64_t)ts.tv_nsec / 1000000;
+}
+
+static void thread_start(void* (*fn)(void*), void* arg)
+{
+  pthread_t th;
+  pthread_attr_t attr;
+  pthread_attr_init(&attr);
+  pthread_attr_setstacksize(&attr, 128 << 10);
+  int i = 0;
+  for (; i < 100; i++) {
+    if (pthread_create(&th, &attr, fn, arg) == 0) {
+      pthread_attr_destroy(&attr);
+      return;
+    }
+    if (errno == EAGAIN) {
+      usleep(50);
+      continue;
+    }
+    break;
+  }
+  exit(1);
+}
+
+typedef struct {
+  pthread_mutex_t mu;
+  pthread_cond_t cv;
+  int state;
+} event_t;
+
+static void event_init(event_t* ev)
+{
+  if (pthread_mutex_init(&ev->mu, 0))
+    exit(1);
+  if (pthread_cond_init(&ev->cv, 0))
+    exit(1);
+  ev->state = 0;
+}
+
+static void event_reset(event_t* ev)
+{
+  ev->state = 0;
+}
+
+static void event_set(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  if (ev->state)
+    exit(1);
+  ev->state = 1;
+  pthread_mutex_unlock(&ev->mu);
+  pthread_cond_broadcast(&ev->cv);
+}
+
+static void event_wait(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  while (!ev->state)
+    pthread_cond_wait(&ev->cv, &ev->mu);
+  pthread_mutex_unlock(&ev->mu);
+}
+
+static int event_isset(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  int res = ev->state;
+  pthread_mutex_unlock(&ev->mu);
+  return res;
+}
+
+static int event_timedwait(event_t* ev, uint64_t timeout)
+{
+  uint64_t start = current_time_ms();
+  uint64_t now = start;
+  pthread_mutex_lock(&ev->mu);
+  for (;;) {
+    if (ev->state)
+      break;
+    uint64_t remain = timeout - (now - start);
+    struct timespec ts;
+    ts.tv_sec = remain / 1000;
+    ts.tv_nsec = (remain % 1000) * 1000 * 1000;
+    pthread_cond_timedwait(&ev->cv, &ev->mu, &ts);
+    now = current_time_ms();
+    if (now - start > timeout)
+      break;
+  }
+  int res = ev->state;
+  pthread_mutex_unlock(&ev->mu);
+  return res;
+}
+
+static void sandbox_common()
+{
+  struct rlimit rlim;
+  rlim.rlim_cur = rlim.rlim_max = 128 << 20;
+  setrlimit(RLIMIT_AS, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 8 << 20;
+  setrlimit(RLIMIT_MEMLOCK, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 1 << 20;
+  setrlimit(RLIMIT_FSIZE, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 1 << 20;
+  setrlimit(RLIMIT_STACK, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 0;
+  setrlimit(RLIMIT_CORE, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 256;
+  setrlimit(RLIMIT_NOFILE, &rlim);
+}
+
+static void loop();
+
+static int do_sandbox_none(void)
+{
+  sandbox_common();
+  loop();
+  return 0;
+}
+
+struct thread_t {
+  int created, call;
+  event_t ready, done;
+};
+
+static struct thread_t threads[16];
+static void execute_call(int call);
+static int running;
+
+static void* thr(void* arg)
+{
+  struct thread_t* th = (struct thread_t*)arg;
+  for (;;) {
+    event_wait(&th->ready);
+    event_reset(&th->ready);
+    execute_call(th->call);
+    __atomic_fetch_sub(&running, 1, __ATOMIC_RELAXED);
+    event_set(&th->done);
+  }
+  return 0;
+}
+
+static void execute_one(void)
+{
+  if (write(1, "executing program\n", sizeof("executing program\n") - 1)) {
+  }
+  int i, call, thread;
+  for (call = 0; call < 4; call++) {
+    for (thread = 0; thread < (int)(sizeof(threads) / sizeof(threads[0]));
+         thread++) {
+      struct thread_t* th = &threads[thread];
+      if (!th->created) {
+        th->created = 1;
+        event_init(&th->ready);
+        event_init(&th->done);
+        event_set(&th->done);
+        thread_start(thr, th);
+      }
+      if (!event_isset(&th->done))
+        continue;
+      event_reset(&th->done);
+      th->call = call;
+      __atomic_fetch_add(&running, 1, __ATOMIC_RELAXED);
+      event_set(&th->ready);
+      event_timedwait(&th->done, 50);
+      break;
+    }
+  }
+  for (i = 0; i < 100 && __atomic_load_n(&running, __ATOMIC_RELAXED); i++)
+    sleep_ms(1);
+}
+
+static void execute_one(void);
+
+#define WAIT_FLAGS 0
+
+static void loop(void)
+{
+//  int iter = 0;
+  for (;; /*iter++*/) {
+    int pid = fork();
+    if (pid < 0)
+      exit(1);
+    if (pid == 0) {
+      execute_one();
+      exit(0);
+    }
+    int status = 0;
+    uint64_t start = current_time_ms();
+    for (;;) {
+      sleep_ms(10);
+      if (waitpid(-1, &status, WNOHANG | WAIT_FLAGS) == pid)
+        break;
+      if (current_time_ms() - start < 5000)
+        continue;
+      kill_and_wait(pid, &status);
+      break;
+    }
+  }
+}
+
+uint64_t r[2] = {0xffffffffffffffff, 0xffffffffffffffff};
+
+void execute_call(int call)
+{
+  intptr_t res = 0;
+  switch (call) {
+  case 0:
+    //  socketpair\$unix arguments: [
+    //    domain: const = 0x1 (8 bytes)
+    //    type: unix_socket_type = 0x5 (8 bytes)
+    //    proto: const = 0x0 (1 bytes)
+    //    fds: ptr[out, unix_pair] {
+    //      unix_pair {
+    //        fd0: sock_unix (resource)
+    //        fd1: sock_unix (resource)
+    //      }
+    //    }
+    //  ]
+    res = syscall(SYS_socketpair, /*domain=*/1ul, /*type=SOCK_SEQPACKET*/ 5ul,
+                  /*proto=*/0, /*fds=*/0x200000000440ul);
+    if (res != -1) {
+      r[0] = *(uint32_t*)0x200000000440;
+      r[1] = *(uint32_t*)0x200000000444;
+    }
+    break;
+  case 1:
+    //  sendmsg arguments: [
+    //    fd: sock (resource)
+    //    msg: ptr[in, send_msghdr] {
+    //      send_msghdr {
+    //        msg_name: nil
+    //        msg_namelen: len = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //        msg_iov: nil
+    //        msg_iovlen: len = 0x0 (8 bytes)
+    //        msg_control: ptr[inout, array[ANYUNION]] {
+    //          array[ANYUNION] {
+    //            union ANYUNION {
+    //              ANYBLOB: buffer: {04 01 00 00 ff ff 00 00 01} (length 0x9)
+    //            }
+    //          }
+    //        }
+    //        msg_controllen: bytesize = 0x104 (8 bytes)
+    //        msg_flags: const = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //      }
+    //    }
+    //    f: send_flags = 0x0 (8 bytes)
+    //  ]
+    *(uint64_t*)0x200000000000 = 0;
+    *(uint32_t*)0x200000000008 = 0;
+    *(uint64_t*)0x200000000010 = 0;
+    *(uint64_t*)0x200000000018 = 0;
+    *(uint64_t*)0x200000000020 = 0x2000000007c0;
+    memcpy((void*)0x2000000007c0, "\x04\x01\x00\x00\xff\xff\x00\x00\x01", 9);
+    *(uint64_t*)0x200000000028 = 0x104;
+    *(uint32_t*)0x200000000030 = 0;
+    syscall(SYS_sendmsg, /*fd=*/r[1], /*msg=*/0x200000000000ul, /*f=*/0ul);
+    for (int i = 0; i < 32; i++) {
+      syscall(SYS_sendmsg, /*fd=*/r[1], /*msg=*/0x200000000000ul, /*f=*/0ul);
+    }
+    break;
+  case 2:
+    //  close arguments: [
+    //    fd: fd (resource)
+    //  ]
+    syscall(SYS_close, /*fd=*/r[1]);
+    break;
+  case 3:
+    //  recvmsg arguments: [
+    //    fd: sock (resource)
+    //    msg: ptr[inout, recv_msghdr] {
+    //      recv_msghdr {
+    //        msg_name: nil
+    //        msg_namelen: len = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //        msg_iov: nil
+    //        msg_iovlen: len = 0x0 (8 bytes)
+    //        msg_control: ptr[out, buffer] {
+    //          buffer: (DirOut)
+    //        }
+    //        msg_controllen: len = 0x19 (8 bytes)
+    //        msg_flags: const = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //      }
+    //    }
+    //    f: recv_flags = 0x80 (8 bytes)
+    //  ]
+    *(uint64_t*)0x2000000005c0 = 0;
+    *(uint32_t*)0x2000000005c8 = 0;
+    *(uint64_t*)0x2000000005d0 = 0;
+    *(uint64_t*)0x2000000005d8 = 0;
+    *(uint64_t*)0x2000000005e0 = 0x200000000580;
+    *(uint64_t*)0x2000000005e8 = 0x19;
+    *(uint32_t*)0x2000000005f0 = 0;
+    syscall(SYS_recvmsg, /*fd=*/r[0], /*msg=*/0x2000000005c0ul,
+            /*f=MSG_DONTWAIT*/ 0x80ul);
+    break;
+  }
+}
+int main(void)
+{
+  syscall(SYS_mmap, /*addr=*/0x200000000000ul, /*len=*/0x1000000ul,
+          /*prot=PROT_WRITE|PROT_READ|PROT_EXEC*/ 7ul,
+          /*flags=MAP_FIXED|MAP_ANONYMOUS|MAP_PRIVATE*/ 0x1012ul,
+          /*fd=*/(intptr_t)-1, /*offset=*/0ul);
+  const char* reason;
+  (void)reason;
+  for (procid = 0; procid < 4; procid++) {
+    if (fork() == 0) {
+      do_sandbox_none();
+    }
+  }
+  sleep(1000000);
+  return 0;
+}
+EOF
+mycc -o /tmp/$prog -Wall -Wextra -O0 /tmp/$prog.c -pthread || exit 1
+
+work=/tmp/$prog.dir
+rm -rf $work
+mkdir $work
+cd /tmp/$prog.dir
+kldstat | grep -q sctp || { kldload sctp.ko && loaded=1; }
+timeout 3m /tmp/$prog > /dev/null 2>&1
+
+rm -rf /tmp/$prog /tmp/$prog.c /tmp/$prog.core $work
+[ $loaded ] && kldunload sctp.ko
+exit 0
diff --git a/tools/test/stress2/misc/syzkaller85.sh b/tools/test/stress2/misc/syzkaller85.sh
new file mode 100755
index 000000000000..1772c0dc58b8
--- /dev/null
+++ b/tools/test/stress2/misc/syzkaller85.sh
@@ -0,0 +1,499 @@
+#!/bin/sh
+
+# panic: Assertion uio->uio_resid < 0 failed at ../../../netlink/netlink_domain.c:808
+# cpuid = 8
+# time = 1759044376
+# KDB: stack backtrace:
+# db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe0184d17a70
+# vpanic() at vpanic+0x136/frame 0xfffffe0184d17ba0
+# panic() at panic+0x43/frame 0xfffffe0184d17c00
+# nl_soreceive() at nl_soreceive+0x433/frame 0xfffffe0184d17ca0
+# soreceive() at soreceive+0x45/frame 0xfffffe0184d17cc0
+# kern_recvit() at kern_recvit+0x181/frame 0xfffffe0184d17d70
+# sys_recvfrom() at sys_recvfrom+0xa2/frame 0xfffffe0184d17e00
+# amd64_syscall() at amd64_syscall+0x169/frame 0xfffffe0184d17f30
+# fast_syscall_common() at fast_syscall_common+0xf8/frame 0xfffffe0184d17f30
+# --- syscall (0, FreeBSD ELF64, syscall), rip = 0x822882cca, rsp = 0x823572e88, rbp = 0x823572f90 ---
+# KDB: enter: panic
+# [ thread pid 11012 tid 138112 ]
+# Stopped at         $0,0x121a722(%rip)
+# db> x/s version
+# version: FreeBSD 16.0-CURRENT #0 main-n280667-52eb7e394a7e-dirty: Sun Sep 28 08:56:14 CEST 2025
+# pho@mercat1.netperf.freebsd.org:/usr/src/sys/amd64/compile/PHO
+# db> 
+
+[ `id -u ` -ne 0 ] && echo "Must be root!" && exit 1
+
+. ../default.cfg
+set -u
+prog=$(basename "$0" .sh)
+cat > /tmp/$prog.c <<EOF
+// https://syzkaller.appspot.com/bug?id=e33cdff88b17af77553159c4b372cac4e4bcd652
+// autogenerated by syzkaller (https://github.com/google/syzkaller)
+// syzbot+194f95f2c5fdffef1ef5@syzkaller.appspotmail.com
+
+#define _GNU_SOURCE
+
+#include <sys/types.h>
+
+#include <dirent.h>
+#include <errno.h>
+#include <pthread.h>
+#include <pwd.h>
+#include <setjmp.h>
+#include <signal.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/endian.h>
+#include <sys/resource.h>
+#include <sys/stat.h>
+#include <sys/syscall.h>
+#include <sys/wait.h>
+#include <time.h>
+#include <unistd.h>
+
+static unsigned long long procid;
+
+static __thread int clone_ongoing;
+static __thread int skip_segv;
+static __thread jmp_buf segv_env;
+
+static void segv_handler(int sig, siginfo_t* info, void* ctx __unused)
+{
+  if (__atomic_load_n(&clone_ongoing, __ATOMIC_RELAXED) != 0) {
+    exit(sig);
+  }
+  uintptr_t addr = (uintptr_t)info->si_addr;
+  const uintptr_t prog_start = 1 << 20;
+  const uintptr_t prog_end = 100 << 20;
+  int skip = __atomic_load_n(&skip_segv, __ATOMIC_RELAXED) != 0;
+  int valid = addr < prog_start || addr > prog_end;
+  if (sig == SIGBUS)
+    valid = 1;
+  if (skip && valid) {
+    _longjmp(segv_env, 1);
+  }
+  exit(sig);
+}
+
+static void install_segv_handler(void)
+{
+  struct sigaction sa;
+  memset(&sa, 0, sizeof(sa));
+  sa.sa_sigaction = segv_handler;
+  sa.sa_flags = SA_NODEFER | SA_SIGINFO;
+  sigaction(SIGSEGV, &sa, NULL);
+  sigaction(SIGBUS, &sa, NULL);
+}
+
+#define NONFAILING(...)                                                        \
+  ({                                                                           \
+    int ok = 1;                                                                \
+    __atomic_fetch_add(&skip_segv, 1, __ATOMIC_SEQ_CST);                       \
+    if (_setjmp(segv_env) == 0) {                                              \
+      __VA_ARGS__;                                                             \
+    } else                                                                     \
+      ok = 0;                                                                  \
+    __atomic_fetch_sub(&skip_segv, 1, __ATOMIC_SEQ_CST);                       \
+    ok;                                                                        \
+  })
+
+static void kill_and_wait(int pid, int* status)
+{
+  kill(pid, SIGKILL);
+  while (waitpid(-1, status, 0) != pid) {
+  }
+}
+
+static void sleep_ms(uint64_t ms)
+{
+  usleep(ms * 1000);
+}
+
+static uint64_t current_time_ms(void)
+{
+  struct timespec ts;
+  if (clock_gettime(CLOCK_MONOTONIC, &ts))
+    exit(1);
+  return (uint64_t)ts.tv_sec * 1000 + (uint64_t)ts.tv_nsec / 1000000;
+}
+
+static void use_temporary_dir(void)
+{
+  char tmpdir_template[] = "./syzkaller.XXXXXX";
+  char* tmpdir = mkdtemp(tmpdir_template);
+  if (!tmpdir)
+    exit(1);
+  if (chmod(tmpdir, 0777))
+    exit(1);
+  if (chdir(tmpdir))
+    exit(1);
+}
+
+static void reset_flags(const char* filename)
+{
+  struct stat st;
+  if (lstat(filename, &st))
+    exit(1);
+  st.st_flags &= ~(SF_NOUNLINK | UF_NOUNLINK | SF_IMMUTABLE | UF_IMMUTABLE |
+                   SF_APPEND | UF_APPEND);
+  if (lchflags(filename, st.st_flags))
+    exit(1);
+}
+static void __attribute__((noinline)) remove_dir(const char* dir)
+{
+  DIR* dp = opendir(dir);
+  if (dp == NULL) {
+    if (errno == EACCES) {
+      if (rmdir(dir))
+        exit(1);
+      return;
+    }
+    exit(1);
+  }
+  struct dirent* ep = 0;
+  while ((ep = readdir(dp))) {
+    if (strcmp(ep->d_name, ".") == 0 || strcmp(ep->d_name, "..") == 0)
+      continue;
+    char filename[FILENAME_MAX];
+    snprintf(filename, sizeof(filename), "%s/%s", dir, ep->d_name);
+    struct stat st;
+    if (lstat(filename, &st))
+      exit(1);
+    if (S_ISDIR(st.st_mode)) {
+      remove_dir(filename);
+      continue;
+    }
+    if (unlink(filename)) {
+      if (errno == EPERM) {
+        reset_flags(filename);
+        reset_flags(dir);
+        if (unlink(filename) == 0)
+          continue;
+      }
+      exit(1);
+    }
+  }
+  closedir(dp);
+  while (rmdir(dir)) {
+    if (errno == EPERM) {
+      reset_flags(dir);
+      if (rmdir(dir) == 0)
+        break;
+    }
+    exit(1);
+  }
+}
+
+static void thread_start(void* (*fn)(void*), void* arg)
+{
+  pthread_t th;
+  pthread_attr_t attr;
+  pthread_attr_init(&attr);
+  pthread_attr_setstacksize(&attr, 128 << 10);
+  int i = 0;
+  for (; i < 100; i++) {
+    if (pthread_create(&th, &attr, fn, arg) == 0) {
+      pthread_attr_destroy(&attr);
+      return;
+    }
+    if (errno == EAGAIN) {
+      usleep(50);
+      continue;
+    }
+    break;
+  }
+  exit(1);
+}
+
+typedef struct {
+  pthread_mutex_t mu;
+  pthread_cond_t cv;
+  int state;
+} event_t;
+
+static void event_init(event_t* ev)
+{
+  if (pthread_mutex_init(&ev->mu, 0))
+    exit(1);
+  if (pthread_cond_init(&ev->cv, 0))
+    exit(1);
+  ev->state = 0;
+}
+
+static void event_reset(event_t* ev)
+{
+  ev->state = 0;
+}
+
+static void event_set(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  if (ev->state)
+    exit(1);
+  ev->state = 1;
+  pthread_mutex_unlock(&ev->mu);
+  pthread_cond_broadcast(&ev->cv);
+}
+
+static void event_wait(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  while (!ev->state)
+    pthread_cond_wait(&ev->cv, &ev->mu);
+  pthread_mutex_unlock(&ev->mu);
+}
+
+static int event_isset(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  int res = ev->state;
+  pthread_mutex_unlock(&ev->mu);
+  return res;
+}
+
+static int event_timedwait(event_t* ev, uint64_t timeout)
+{
+  uint64_t start = current_time_ms();
+  uint64_t now = start;
+  pthread_mutex_lock(&ev->mu);
+  for (;;) {
+    if (ev->state)
+      break;
+    uint64_t remain = timeout - (now - start);
+    struct timespec ts;
+    ts.tv_sec = remain / 1000;
+    ts.tv_nsec = (remain % 1000) * 1000 * 1000;
+    pthread_cond_timedwait(&ev->cv, &ev->mu, &ts);
+    now = current_time_ms();
+    if (now - start > timeout)
+      break;
+  }
+  int res = ev->state;
+  pthread_mutex_unlock(&ev->mu);
+  return res;
+}
+
+static void sandbox_common()
+{
+  struct rlimit rlim;
+  rlim.rlim_cur = rlim.rlim_max = 128 << 20;
+  setrlimit(RLIMIT_AS, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 8 << 20;
+  setrlimit(RLIMIT_MEMLOCK, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 1 << 20;
+  setrlimit(RLIMIT_FSIZE, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 1 << 20;
+  setrlimit(RLIMIT_STACK, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 0;
+  setrlimit(RLIMIT_CORE, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 256;
+  setrlimit(RLIMIT_NOFILE, &rlim);
+}
+
+static void loop();
+
+static int do_sandbox_none(void)
+{
+  sandbox_common();
+  loop();
+  return 0;
+}
+
+struct thread_t {
+  int created, call;
+  event_t ready, done;
+};
+
+static struct thread_t threads[16];
+static void execute_call(int call);
+static int running;
+
+static void* thr(void* arg)
+{
+  struct thread_t* th = (struct thread_t*)arg;
+  for (;;) {
+    event_wait(&th->ready);
+    event_reset(&th->ready);
+    execute_call(th->call);
+    __atomic_fetch_sub(&running, 1, __ATOMIC_RELAXED);
+    event_set(&th->done);
+  }
+  return 0;
+}
+
+static void execute_one(void)
+{
+  if (write(1, "executing program\n", sizeof("executing program\n") - 1)) {
+  }
+  int i, call, thread;
+  for (call = 0; call < 3; call++) {
+    for (thread = 0; thread < (int)(sizeof(threads) / sizeof(threads[0]));
+         thread++) {
+      struct thread_t* th = &threads[thread];
+      if (!th->created) {
+        th->created = 1;
+        event_init(&th->ready);
+        event_init(&th->done);
+        event_set(&th->done);
+        thread_start(thr, th);
+      }
+      if (!event_isset(&th->done))
+        continue;
+      event_reset(&th->done);
+      th->call = call;
+      __atomic_fetch_add(&running, 1, __ATOMIC_RELAXED);
+      event_set(&th->ready);
+      event_timedwait(&th->done, 50);
+      break;
+    }
+  }
+  for (i = 0; i < 100 && __atomic_load_n(&running, __ATOMIC_RELAXED); i++)
+    sleep_ms(1);
+}
+
+static void execute_one(void);
+
+#define WAIT_FLAGS 0
+
+static void loop(void)
+{
+  int iter = 0;
+  for (;; iter++) {
+    char cwdbuf[32];
+    sprintf(cwdbuf, "./%d", iter);
+    if (mkdir(cwdbuf, 0777))
+      exit(1);
+    int pid = fork();
+    if (pid < 0)
+      exit(1);
+    if (pid == 0) {
+      if (chdir(cwdbuf))
+        exit(1);
+      execute_one();
+      exit(0);
+    }
+    int status = 0;
+    uint64_t start = current_time_ms();
+    for (;;) {
+      sleep_ms(10);
+      if (waitpid(-1, &status, WNOHANG | WAIT_FLAGS) == pid)
+        break;
+      if (current_time_ms() - start < 5000)
+        continue;
+      kill_and_wait(pid, &status);
+      break;
+    }
+    remove_dir(cwdbuf);
+  }
+}
+
+uint64_t r[1] = {0xffffffffffffffff};
+
+void execute_call(int call)
+{
+  intptr_t res = 0;
+  switch (call) {
+  case 0:
+    //  socket arguments: [
+    //    domain: socket_domain = 0x26 (8 bytes)
+    //    type: socket_type = 0x2 (8 bytes)
+    //    proto: int8 = 0x0 (1 bytes)
+    //  ]
+    //  returns sock
+    res = syscall(SYS_socket, /*domain=AF_INET|0x24*/ 0x26ul,
+                  /*type=SOCK_DGRAM*/ 2ul, /*proto=*/0);
+    if (res != -1)
+      r[0] = res;
+    break;
+  case 1:
+    //  bind arguments: [
+    //    fd: sock (resource)
+    //    addr: ptr[in, sockaddr_storage] {
+    //      union sockaddr_storage {
+    //        in6: sockaddr_in6 {
+    //          len: len = 0x22 (1 bytes)
+    //          family: const = 0x1c (1 bytes)
+    //          port: proc = 0x3 (2 bytes)
+    //          flow: int32 = 0x0 (4 bytes)
+    //          addr: union ipv6_addr {
+    //            mcast1: ipv6_addr_multicast1 {
+    //              a0: const = 0xff (1 bytes)
+    //              a1: const = 0x1 (1 bytes)
+    //              a2: buffer: {00 00 00 00 00 00 00 00 00 00 00 00 00} (length
+    //              0xd) a3: const = 0x1 (1 bytes)
+    //            }
+    //          }
+    //          scope: int32 = 0x0 (4 bytes)
+    //        }
+    //      }
+    //    }
+    //    addrlen: len = 0xc (8 bytes)
+    //  ]
+    NONFAILING(*(uint8_t*)0x200000000040 = 0x22);
+    NONFAILING(*(uint8_t*)0x200000000041 = 0x1c);
+    NONFAILING(*(uint16_t*)0x200000000042 = htobe16(0x4e23 + procid * 4));
+    NONFAILING(*(uint32_t*)0x200000000044 = 0);
+    NONFAILING(*(uint8_t*)0x200000000048 = -1);
+    NONFAILING(*(uint8_t*)0x200000000049 = 1);
+    NONFAILING(memset((void*)0x20000000004a, 0, 13));
+    NONFAILING(*(uint8_t*)0x200000000057 = 1);
+    NONFAILING(*(uint32_t*)0x200000000058 = 0);
+    syscall(SYS_bind, /*fd=*/r[0], /*addr=*/0x200000000040ul,
+            /*addrlen=*/0xcul);
+    break;
+  case 2:
+    //  recvfrom\$inet arguments: [
+    //    fd: sock_in (resource)
+    //    buf: nil
+    //    len: len = 0x51 (8 bytes)
+    //    f: recv_flags = 0x401313ab1a02f21f (8 bytes)
+    //    addr: nil
+    //    addrlen: len = 0x0 (8 bytes)
+    //  ]
+    syscall(SYS_recvfrom, /*fd=*/r[0], /*buf=*/0ul, /*len=*/0x51ul,
+            /*f=MSG_PEEK|MSG_OOB|0x401313ab1a02f21c*/ 0x401313ab1a02f21ful,
+            /*addr=*/0ul, /*addrlen=*/0ul);
+    break;
+  }
+}
+int main(void)
+{
+  syscall(SYS_mmap, /*addr=*/0x200000000000ul, /*len=*/0x1000000ul,
+          /*prot=PROT_WRITE|PROT_READ|PROT_EXEC*/ 7ul,
+          /*flags=MAP_FIXED|MAP_ANONYMOUS|MAP_PRIVATE*/ 0x1012ul,
+          /*fd=*/(intptr_t)-1, /*offset=*/0ul);
+  const char* reason;
+  (void)reason;
+  install_segv_handler();
+  for (procid = 0; procid < 4; procid++) {
+    if (fork() == 0) {
+      use_temporary_dir();
+      do_sandbox_none();
+    }
+  }
+  sleep(1000000);
+  return 0;
+}
+EOF
+mycc -o /tmp/$prog -Wall -Wextra -O0 /tmp/$prog.c -pthread || exit 1
+
+(cd ../testcases/swap; ./swap -t 5m -i 20 -l 100 > /dev/null 2>&1) &
+sleep 5
+
+work=/tmp/$prog.dir
+rm -rf $work
+mkdir $work
+cd /tmp/$prog.dir
+
+timeout 5m /tmp/$prog > /dev/null 2>&1
+
+while pkill swap; do :; done
+wait
+
+rm -rf /tmp/$prog /tmp/$prog.c /tmp/$prog.core /tmp/syzkaller.?????? $work
+exit 0
diff --git a/tools/test/stress2/misc/syzkaller86.sh b/tools/test/stress2/misc/syzkaller86.sh
new file mode 100755
index 000000000000..12922a2d05fa
--- /dev/null
+++ b/tools/test/stress2/misc/syzkaller86.sh
@@ -0,0 +1,555 @@
+#!/bin/sh
+
+# Fatal trap 12: page fault while in kernel mode
+# cpuid = 1; apic id = 01
+# fault virtual address   = 0x18
+# fault code              = supervisor read data, page not present
+# instruction pointer     = 0x20:0xffffffff80b69835
+# stack pointer           = 0x28:0xfffffe00ff8e7d90
+# frame pointer           = 0x28:0xfffffe00ff8e7d90
+# code segment            = base 0x0, limit 0xfffff, type 0x1b
+#                         = DPL 0, pres 1, long 1, def32 0, gran 1
+# processor eflags        = interrupt enabled, resume, IOPL = 0
+# current process         = 0 (thread taskq)
+# rdi: 0000000000000018 rsi: 0000000000000004 rdx: ffffffff812b3f65
+# rcx: 00000000000008ba  r8: fffff800044b8780  r9: fffff80003397000
+# rax: 0000000000000001 rbx: fffff8004221fa00 rbp: fffffe00ff8e7d90
+# r10: 0000000000000001 r11: fffffe00dc47b000 r12: fffffe0177ed0000
+# r13: fffff800044b8780 r14: fffff8004221f800 r15: fffff8004221f800
+# trap number             = 12
+# panic: page fault
+# cpuid = 1
+# time = 1759322830
+# KDB: stack backtrace:
+# db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe00ff8e7ac0
+# vpanic() at vpanic+0x136/frame 0xfffffe00ff8e7bf0
+# panic() at panic+0x43/frame 0xfffffe00ff8e7c50
+# trap_pfault() at trap_pfault+0x47c/frame 0xfffffe00ff8e7cc0
+# calltrap() at calltrap+0x8/frame 0xfffffe00ff8e7cc0
+# --- trap 0xc, rip = 0xffffffff80b69835, rsp = 0xfffffe00ff8e7d90, rbp = 0xfffffe00ff8e7d90 ---
+# __mtx_assert() at __mtx_assert+0x35/frame 0xfffffe00ff8e7d90
+# ktls_check_rx() at ktls_check_rx+0x2f/frame 0xfffffe00ff8e7dd0
+# socantrcvmore() at socantrcvmore+0x5e/frame 0xfffffe00ff8e7df0
+# unp_gc() at unp_gc+0x5df/frame 0xfffffe00ff8e7e40
+# taskqueue_run_locked() at taskqueue_run_locked+0x1c2/frame 0xfffffe00ff8e7ec0
+# taskqueue_thread_loop() at taskqueue_thread_loop+0xd3/frame 0xfffffe00ff8e7ef0
+# fork_exit() at fork_exit+0x82/frame 0xfffffe00ff8e7f30
+# fork_trampoline() at fork_trampoline+0xe/frame 0xfffffe00ff8e7f30
+# --- trap 0, rip = 0, rsp = 0, rbp = 0 ---
+# KDB: enter: panic
+# [ thread pid 0 tid 100045 ]
+# Stopped at      kdb_enter+0x33: movq    $0,0x121a9e2(%rip)
+# db> x/s version
+# version: FreeBSD 16.0-CURRENT #0 vmfqe-n280784-b7f165e45d6d: Wed Oct  1 13:48:43 CEST 2025
+# pho@mercat1.netperf.freebsd.org:/var/tmp/deviant3/sys/amd64/compile/PHO
+# db> 
+
+[ `id -u ` -ne 0 ] && echo "Must be root!" && exit 1
+
+. ../default.cfg
+set -u
+prog=$(basename "$0" .sh)
+cat > /tmp/$prog.c <<EOF
+// https://syzkaller.appspot.com/bug?id=ec40fe3e3e2b41218d1d417bc10d0be2517bf751
+// autogenerated by syzkaller (https://github.com/google/syzkaller)
+// syzbot+a62883292a5c257703be@syzkaller.appspotmail.com
+
+#define _GNU_SOURCE
+
+#include <sys/types.h>
+
+#include <dirent.h>
+#include <errno.h>
+#include <pthread.h>
+#include <pwd.h>
+#include <signal.h>
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/endian.h>
+#include <sys/resource.h>
+#include <sys/stat.h>
+#include <sys/syscall.h>
+#include <sys/wait.h>
+#include <time.h>
+#include <unistd.h>
+
+static unsigned long long procid;
+
+static void kill_and_wait(int pid, int* status)
+{
+  kill(pid, SIGKILL);
+  while (waitpid(-1, status, 0) != pid) {
+  }
+}
+
+static void sleep_ms(uint64_t ms)
+{
+  usleep(ms * 1000);
+}
+
+static uint64_t current_time_ms(void)
+{
+  struct timespec ts;
+  if (clock_gettime(CLOCK_MONOTONIC, &ts))
+    exit(1);
+  return (uint64_t)ts.tv_sec * 1000 + (uint64_t)ts.tv_nsec / 1000000;
+}
+
+static void use_temporary_dir(void)
+{
+  char tmpdir_template[] = "./syzkaller.XXXXXX";
+  char* tmpdir = mkdtemp(tmpdir_template);
+  if (!tmpdir)
+    exit(1);
+  if (chmod(tmpdir, 0777))
+    exit(1);
+  if (chdir(tmpdir))
+    exit(1);
+}
+
+static void reset_flags(const char* filename)
+{
+  struct stat st;
+  if (lstat(filename, &st))
+    exit(1);
+  st.st_flags &= ~(SF_NOUNLINK | UF_NOUNLINK | SF_IMMUTABLE | UF_IMMUTABLE |
+                   SF_APPEND | UF_APPEND);
+  if (lchflags(filename, st.st_flags))
+    exit(1);
+}
+static void __attribute__((noinline)) remove_dir(const char* dir)
+{
+  DIR* dp = opendir(dir);
+  if (dp == NULL) {
+    if (errno == EACCES) {
+      if (rmdir(dir))
+        exit(1);
+      return;
+    }
+    exit(1);
+  }
+  struct dirent* ep = 0;
+  while ((ep = readdir(dp))) {
+    if (strcmp(ep->d_name, ".") == 0 || strcmp(ep->d_name, "..") == 0)
+      continue;
+    char filename[FILENAME_MAX];
+    snprintf(filename, sizeof(filename), "%s/%s", dir, ep->d_name);
+    struct stat st;
+    if (lstat(filename, &st))
+      exit(1);
+    if (S_ISDIR(st.st_mode)) {
+      remove_dir(filename);
+      continue;
+    }
+    if (unlink(filename)) {
+      if (errno == EPERM) {
+        reset_flags(filename);
+        reset_flags(dir);
+        if (unlink(filename) == 0)
+          continue;
+      }
+      exit(1);
+    }
+  }
+  closedir(dp);
+  while (rmdir(dir)) {
+    if (errno == EPERM) {
+      reset_flags(dir);
+      if (rmdir(dir) == 0)
+        break;
+    }
+    exit(1);
+  }
+}
+
+static void thread_start(void* (*fn)(void*), void* arg)
+{
+  pthread_t th;
+  pthread_attr_t attr;
+  pthread_attr_init(&attr);
+  pthread_attr_setstacksize(&attr, 128 << 10);
+  int i = 0;
+  for (; i < 100; i++) {
+    if (pthread_create(&th, &attr, fn, arg) == 0) {
+      pthread_attr_destroy(&attr);
+      return;
+    }
+    if (errno == EAGAIN) {
+      usleep(50);
+      continue;
+    }
+    break;
+  }
+  exit(1);
+}
+
+typedef struct {
+  pthread_mutex_t mu;
+  pthread_cond_t cv;
+  int state;
+} event_t;
+
+static void event_init(event_t* ev)
+{
+  if (pthread_mutex_init(&ev->mu, 0))
+    exit(1);
+  if (pthread_cond_init(&ev->cv, 0))
+    exit(1);
+  ev->state = 0;
+}
+
+static void event_reset(event_t* ev)
+{
+  ev->state = 0;
+}
+
+static void event_set(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  if (ev->state)
+    exit(1);
+  ev->state = 1;
+  pthread_mutex_unlock(&ev->mu);
+  pthread_cond_broadcast(&ev->cv);
+}
+
+static void event_wait(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  while (!ev->state)
+    pthread_cond_wait(&ev->cv, &ev->mu);
+  pthread_mutex_unlock(&ev->mu);
+}
+
+static int event_isset(event_t* ev)
+{
+  pthread_mutex_lock(&ev->mu);
+  int res = ev->state;
+  pthread_mutex_unlock(&ev->mu);
+  return res;
+}
+
+static int event_timedwait(event_t* ev, uint64_t timeout)
+{
+  uint64_t start = current_time_ms();
+  uint64_t now = start;
+  pthread_mutex_lock(&ev->mu);
+  for (;;) {
+    if (ev->state)
+      break;
+    uint64_t remain = timeout - (now - start);
+    struct timespec ts;
+    ts.tv_sec = remain / 1000;
+    ts.tv_nsec = (remain % 1000) * 1000 * 1000;
+    pthread_cond_timedwait(&ev->cv, &ev->mu, &ts);
+    now = current_time_ms();
+    if (now - start > timeout)
+      break;
+  }
+  int res = ev->state;
+  pthread_mutex_unlock(&ev->mu);
+  return res;
+}
+
+static void sandbox_common()
+{
+  struct rlimit rlim;
+  rlim.rlim_cur = rlim.rlim_max = 128 << 20;
+  setrlimit(RLIMIT_AS, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 8 << 20;
+  setrlimit(RLIMIT_MEMLOCK, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 1 << 20;
+  setrlimit(RLIMIT_FSIZE, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 1 << 20;
+  setrlimit(RLIMIT_STACK, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 0;
+  setrlimit(RLIMIT_CORE, &rlim);
+  rlim.rlim_cur = rlim.rlim_max = 256;
+  setrlimit(RLIMIT_NOFILE, &rlim);
+}
+
+static void loop();
+
+static int do_sandbox_none(void)
+{
+  sandbox_common();
+  loop();
+  return 0;
+}
+
+struct thread_t {
+  int created, call;
+  event_t ready, done;
+};
+
+static struct thread_t threads[16];
+static void execute_call(int call);
+static int running;
+
+static void* thr(void* arg)
+{
+  struct thread_t* th = (struct thread_t*)arg;
+  for (;;) {
+    event_wait(&th->ready);
+    event_reset(&th->ready);
+    execute_call(th->call);
+    __atomic_fetch_sub(&running, 1, __ATOMIC_RELAXED);
+    event_set(&th->done);
+  }
+  return 0;
+}
+
+static void execute_one(void)
+{
+  if (write(1, "executing program\n", sizeof("executing program\n") - 1)) {
+  }
+  int i, call, thread;
+  for (call = 0; call < 8; call++) {
+    for (thread = 0; thread < (int)(sizeof(threads) / sizeof(threads[0]));
+         thread++) {
+      struct thread_t* th = &threads[thread];
+      if (!th->created) {
+        th->created = 1;
+        event_init(&th->ready);
+        event_init(&th->done);
+        event_set(&th->done);
+        thread_start(thr, th);
+      }
+      if (!event_isset(&th->done))
+        continue;
+      event_reset(&th->done);
+      th->call = call;
+      __atomic_fetch_add(&running, 1, __ATOMIC_RELAXED);
+      event_set(&th->ready);
+      event_timedwait(&th->done, 50);
+      break;
+    }
+  }
+  for (i = 0; i < 100 && __atomic_load_n(&running, __ATOMIC_RELAXED); i++)
+    sleep_ms(1);
+}
+
+static void execute_one(void);
+
+#define WAIT_FLAGS 0
+
+static void loop(void)
+{
+  int iter = 0;
+  for (;; iter++) {
+    char cwdbuf[32];
+    sprintf(cwdbuf, "./%d", iter);
+    if (mkdir(cwdbuf, 0777))
+      exit(1);
+    int pid = fork();
+    if (pid < 0)
+      exit(1);
+    if (pid == 0) {
+      if (chdir(cwdbuf))
+        exit(1);
+      execute_one();
+      exit(0);
+    }
+    int status = 0;
+    uint64_t start = current_time_ms();
+    for (;;) {
+      sleep_ms(10);
+      if (waitpid(-1, &status, WNOHANG | WAIT_FLAGS) == pid)
+        break;
+      if (current_time_ms() - start < 5000)
+        continue;
+      kill_and_wait(pid, &status);
+      break;
+    }
+    remove_dir(cwdbuf);
+  }
+}
+
+uint64_t r[3] = {0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff};
+
+void execute_call(int call)
+{
+  intptr_t res = 0;
+  switch (call) {
+  case 0:
+    //  freebsd10_pipe arguments: [
+    //    pipefd: ptr[out, pipefd] {
+    //      pipefd {
+    //        rfd: fd (resource)
+    //        wfd: fd (resource)
+    //      }
+    //    }
+    //  ]
+    res = syscall(SYS_freebsd10_pipe, /*pipefd=*/0x2000000001c0ul);
+    if (res != -1)
+      r[0] = *(uint32_t*)0x2000000001c4;
+    break;
+  case 1:
+    //  close arguments: [
+    //    fd: fd (resource)
+    //  ]
+    syscall(SYS_close, /*fd=*/r[0]);
+    break;
+  case 2:
+    //  socket\$unix arguments: [
+    //    domain: const = 0x1 (8 bytes)
+    //    type: unix_socket_type = 0x5 (8 bytes)
+    //    proto: const = 0x0 (1 bytes)
+    //  ]
+    //  returns sock_unix
+    res = syscall(SYS_socket, /*domain=*/1ul, /*type=SOCK_SEQPACKET*/ 5ul,
+                  /*proto=*/0);
+    if (res != -1)
+      r[1] = res;
+    break;
+  case 3:
+    //  bind\$unix arguments: [
+    //    fd: sock_unix (resource)
+    //    addr: ptr[in, sockaddr_un] {
+    //      union sockaddr_un {
+    //        file: sockaddr_un_file {
+    //          len: len = 0xa (1 bytes)
+    //          family: unix_socket_family = 0x1 (1 bytes)
+    //          path: buffer: {2e 2f 66 69 6c 65 31 00} (length 0x8)
+    //        }
+    //      }
+    //    }
+    //    addrlen: len = 0xa (8 bytes)
+    //  ]
+    *(uint8_t*)0x2000000002c0 = 0xa;
+    *(uint8_t*)0x2000000002c1 = 1;
+    memcpy((void*)0x2000000002c2, "./file1\000", 8);
+    syscall(SYS_bind, /*fd=*/r[1], /*addr=*/0x2000000002c0ul,
+            /*addrlen=*/0xaul);
+    break;
+  case 4:
+    //  listen arguments: [
+    //    fd: sock (resource)
+    //    backlog: int32 = 0xfffffffe (4 bytes)
+    //  ]
+    syscall(SYS_listen, /*fd=*/r[1], /*backlog=*/0xfffffffe);
+    break;
+  case 5:
+    //  sendmsg\$unix arguments: [
+    //    fd: sock_unix (resource)
+    //    msg: ptr[in, msghdr_un] {
+    //      msghdr_un {
+    //        addr: nil
+    //        addrlen: len = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //        vec: nil
+    //        vlen: len = 0x0 (8 bytes)
+    //        ctrl: ptr[inout, array[ANYUNION]] {
+    //          array[ANYUNION] {
+    //            union ANYUNION {
+    //              ANYBLOB: buffer: {89 00 00 00 ff ff 00 00 01} (length 0x9)
+    //            }
+    //          }
+    //        }
+    //        ctrllen: bytesize = 0x9 (8 bytes)
+    //        f: send_flags = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //      }
+    //    }
+    //    f: send_flags = 0x0 (8 bytes)
+    //  ]
+    *(uint64_t*)0x200000000080 = 0;
+    *(uint32_t*)0x200000000088 = 0;
+    *(uint64_t*)0x200000000090 = 0;
+    *(uint64_t*)0x200000000098 = 0;
+    *(uint64_t*)0x2000000000a0 = 0x200000000000;
+    memcpy((void*)0x200000000000, "\x89\x00\x00\x00\xff\xff\x00\x00\x01", 9);
+    *(uint64_t*)0x2000000000a8 = 9;
+    *(uint32_t*)0x2000000000b0 = 0;
+    syscall(SYS_sendmsg, /*fd=*/(intptr_t)-1, /*msg=*/0x200000000080ul,
+            /*f=*/0ul);
+    break;
+  case 6:
+    //  socketpair\$unix arguments: [
+    //    domain: const = 0x1 (8 bytes)
+    //    type: unix_socket_type = 0x2 (8 bytes)
+    //    proto: const = 0x0 (1 bytes)
+    //    fds: ptr[out, unix_pair] {
+    //      unix_pair {
+    //        fd0: sock_unix (resource)
+    //        fd1: sock_unix (resource)
+    //      }
+    //    }
+    //  ]
+    res = syscall(SYS_socketpair, /*domain=*/1ul, /*type=SOCK_DGRAM*/ 2ul,
+                  /*proto=*/0, /*fds=*/0x200000000040ul);
+    if (res != -1)
+      r[2] = *(uint32_t*)0x200000000040;
+    break;
+  case 7:
+    //  sendmsg arguments: [
+    //    fd: sock (resource)
+    //    msg: ptr[in, send_msghdr] {
+    //      send_msghdr {
+    //        msg_name: nil
+    //        msg_namelen: len = 0x32c (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //        msg_iov: nil
+    //        msg_iovlen: len = 0x0 (8 bytes)
+    //        msg_control: ptr[in, array[cmsghdr]] {
+    //          array[cmsghdr] {
+    //          }
+    //        }
+    //        msg_controllen: bytesize = 0x90 (8 bytes)
+    //        msg_flags: const = 0x0 (4 bytes)
+    //        pad = 0x0 (4 bytes)
+    //      }
+    //    }
+    //    f: send_flags = 0x0 (8 bytes)
+    //  ]
+    *(uint64_t*)0x200000000380 = 0;
+    *(uint32_t*)0x200000000388 = 0x32c;
+    *(uint64_t*)0x200000000390 = 0;
+    *(uint64_t*)0x200000000398 = 0;
+    *(uint64_t*)0x2000000003a0 = 0x200000000000;
+    *(uint64_t*)0x2000000003a8 = 0x90;
+    *(uint32_t*)0x2000000003b0 = 0;
+    syscall(SYS_sendmsg, /*fd=*/r[2], /*msg=*/0x200000000380ul, /*f=*/0ul);
+    break;
+  }
+}
+int main(void)
+{
+  syscall(SYS_mmap, /*addr=*/0x200000000000ul, /*len=*/0x1000000ul,
+          /*prot=PROT_WRITE|PROT_READ|PROT_EXEC*/ 7ul,
+          /*flags=MAP_FIXED|MAP_ANONYMOUS|MAP_PRIVATE*/ 0x1012ul,
+          /*fd=*/(intptr_t)-1, /*offset=*/0ul);
+  const char* reason;
+  (void)reason;
+  for (procid = 0; procid < 4; procid++) {
+    if (fork() == 0) {
+      use_temporary_dir();
+      do_sandbox_none();
+    }
+  }
+  sleep(1000000);
+  return 0;
+}
+EOF
+mycc -o /tmp/$prog -Wall -Wextra -O0 /tmp/$prog.c -pthread || exit 1
+
+work=/tmp/$prog.dir
+rm -rf $work
+mkdir $work
+cd /tmp/$prog.dir
+for i in `jot 30`; do
+	(
+		mkdir d$i
+		cd d$i
+		timeout 3m /tmp/$prog > /dev/null 2>&1 &
+	)
+done
+while pgrep -q $prog; do sleep 2; done
+wait
+
+rm -rf /tmp/$prog /tmp/$prog.c /tmp/$prog.core $work
+exit 0
diff --git a/tools/tools/git/mfc-candidates.lua b/tools/tools/git/mfc-candidates.lua
index d2865a892971..a1420dc726da 100755
--- a/tools/tools/git/mfc-candidates.lua
+++ b/tools/tools/git/mfc-candidates.lua
@@ -129,16 +129,18 @@ local function main()
 	local author = os.getenv("USER") or ""
 	local dirspec = nil
 
-	local url = exec_command("git remote get-url freebsd")
-	local freebsd_repo = string.match(url, "[^/]+$")
-	freebsd_repo = string.gsub(freebsd_repo, ".git$", "")
+	local url = exec_command("git remote get-url freebsd 2>/dev/null")
+	local freebsd_repo
+	if url and url ~= "" then
+		freebsd_repo = string.match(url, "[^/]+$")
+		freebsd_repo = string.gsub(freebsd_repo, "%.git$", "")
+	end
 	if freebsd_repo == "ports" or freebsd_repo == "freebsd-ports" then
 		local year = os.date("%Y")
 		local month = os.date("%m")
 		local qtr = math.ceil(month / 3)
 		to_branch = "freebsd/" .. year .. "Q" .. qtr
 	elseif freebsd_repo == "src" or freebsd_repo == "freebsd-src" then
-		to_branch = "freebsd/stable/14"
 		-- If pwd is a stable or release branch tree, default to it.
 		local cur_branch = exec_command("git symbolic-ref --short HEAD")
 		if string.match(cur_branch, "^stable/") then
@@ -147,6 +149,11 @@ local function main()
 			to_branch = cur_branch
 			local major = string.match(cur_branch, "%d+")
 			from_branch = "freebsd/stable/" .. major
+		else
+			-- Use latest stable branch.
+			to_branch = exec_command("git for-each-ref --sort=-v:refname " ..
+				"--format='%(refname:lstrip=2)' " ..
+				"refs/remotes/freebsd/stable/* --count=1")
 		end
 	else
 		print("pwd is not under a ports or src repository.")
diff --git a/tools/tools/net80211/Makefile b/tools/tools/net80211/Makefile
index b4b32899cd26..e87b754c4635 100644
--- a/tools/tools/net80211/Makefile
+++ b/tools/tools/net80211/Makefile
@@ -1,3 +1,3 @@
-SUBDIR=	stumbler w00t wesside wlaninject wlanstats wlantxtime wlanwatch wlanwds
+SUBDIR=	stumbler w00t wesside wlaninject wlantxtime wlanwatch wlanwds
 
 .include <bsd.subdir.mk>
diff --git a/tools/tools/net80211/README b/tools/tools/net80211/README
index a73f086f5589..b34bcfedec73 100644
--- a/tools/tools/net80211/README
+++ b/tools/tools/net80211/README
@@ -8,7 +8,6 @@ stumbler	view nearby networks using raw packet interface
 w00t		variety of programs that use the raw packet interface
 wesside		WEP frag attack tool using raw packet interface
 wlaninject	inject 802.11 packets using the raw packet interface
-wlanstats	dump net80211 statistics
 wlanwatch	monitor net80211 events via the routing socket
 wlanwds		handling of WDS dynamic links using vaps
 
diff --git a/usr.bin/beep/Makefile b/usr.bin/beep/Makefile
index 1f2548c24819..79735e6f354a 100644
--- a/usr.bin/beep/Makefile
+++ b/usr.bin/beep/Makefile
@@ -1,3 +1,5 @@
+PACKAGE=sound
+
 PROG=	beep
 MAN=	beep.1
 LIBADD=	m
diff --git a/usr.bin/calendar/calendars/calendar.freebsd b/usr.bin/calendar/calendars/calendar.freebsd
index 1ca63b371f65..b6e18083e24b 100644
--- a/usr.bin/calendar/calendars/calendar.freebsd
+++ b/usr.bin/calendar/calendars/calendar.freebsd
@@ -146,6 +146,7 @@
 03/29	Dave Cottlehuber <dch@FreeBSD.org> born in Christchurch, New Zealand, 1973
 03/29	Thierry Thomas <thierry@FreeBSD.org> born in Luxeuil les Bains, France, 1961
 03/30	Po-Chuan Hsieh <sunpoet@FreeBSD.org> born in Taipei, Taiwan, Republic of China, 1978
+03/31   Vladlen Popolitov <vladlen@FreeBSD.org> born in Lipetsk region, USSR, 1969
 04/01	Matthew Jacob <mjacob@FreeBSD.org> born in San Francisco, California, United States, 1958
 04/01	Alexander V. Chernikov <melifaro@FreeBSD.org> born in Moscow, Russian Federation, 1984
 04/01	Bill Fenner <fenner@FreeBSD.org> born in Bellefonte, Pennsylvania, United States, 1971
@@ -479,6 +480,7 @@
 12/05	Ivan Voras <ivoras@FreeBSD.org> born in Slavonski Brod, Croatia, 1981
 12/06	Stefan Farfeleder <stefanf@FreeBSD.org> born in Wien, Austria, 1980
 12/08	Michael Tuexen <tuexen@FreeBSD.org> born in Oldenburg, Germany, 1966
+12/09	Tiago Gasiba <tiga@FreeBSD.org> born in Porto, Portugal, 1978
 12/10	Hiroki Tagato <tagattie@FreeBSD.org> born in Shiga, Japan, 1971
 12/11	Ganael Laplanche <martymac@FreeBSD.org> born in Reims, France, 1980
 12/11	Koichiro Iwao <meta@FreeBSD.org> born in Oita, Japan, 1987
diff --git a/usr.bin/getconf/sysconf.gperf b/usr.bin/getconf/sysconf.gperf
index baf341c8962b..2bd75dd47851 100644
--- a/usr.bin/getconf/sysconf.gperf
+++ b/usr.bin/getconf/sysconf.gperf
@@ -47,6 +47,7 @@ OPEN_MAX, _SC_OPEN_MAX
 PAGESIZE, _SC_PAGESIZE
 PAGE_SIZE, _SC_PAGESIZE
 PASS_MAX, _SC_PASS_MAX
+PHYS_PAGES, _SC_PHYS_PAGES
 PTHREAD_DESTRUCTOR_ITERATIONS, _SC_THREAD_DESTRUCTOR_ITERATIONS 
 PTHREAD_KEYS_MAX, _SC_THREAD_KEYS_MAX 
 PTHREAD_STACK_MIN, _SC_THREAD_STACK_MIN 
diff --git a/usr.bin/lsvfs/lsvfs.c b/usr.bin/lsvfs/lsvfs.c
index 5477d96434ac..8925b8988cd3 100644
--- a/usr.bin/lsvfs/lsvfs.c
+++ b/usr.bin/lsvfs/lsvfs.c
@@ -5,10 +5,12 @@
  *
  */
 
+#include <sys/capsicum.h>
 #include <sys/param.h>
 #include <sys/mount.h>
 #include <sys/sysctl.h>
 
+#include <capsicum_helpers.h>
 #include <err.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -38,41 +40,42 @@ static const char *fmt_flags(int);
 int
 main(int argc, char **argv)
 {
-	struct xvfsconf vfc, *xvfsp;
+	struct xvfsconf *xvfsp;
 	size_t cnt, buflen;
 	int rv = 0;
 
 	argc--, argv++;
 
+	if (sysctlbyname("vfs.conflist", NULL, &buflen, NULL, 0) < 0)
+		err(EXIT_FAILURE, "sysctl(vfs.conflist)");
+	if ((xvfsp = malloc(buflen)) == NULL)
+		errx(EXIT_FAILURE, "malloc failed");
+	if (sysctlbyname("vfs.conflist", xvfsp, &buflen, NULL, 0) < 0)
+		err(EXIT_FAILURE, "sysctl(vfs.conflist)");
+	cnt = buflen / sizeof(struct xvfsconf);
+
+	caph_cache_catpages();
+	if (caph_enter() != 0)
+		err(EXIT_FAILURE, "failed to enter capability mode");
+
 	printf(HDRFMT, "Filesystem", "Num", "Refs", "Flags");
 	fputs(DASHES, stdout);
 
-	if (argc > 0) {
-		for (; argc > 0; argc--, argv++) {
-			if (getvfsbyname(*argv, &vfc) == 0) {
-				printf(FMT, vfc.vfc_name, vfc.vfc_typenum,
-				    vfc.vfc_refcount, fmt_flags(vfc.vfc_flags));
-			} else {
-				warnx("VFS %s unknown or not loaded", *argv);
-				rv++;
+	for (size_t i = 0; i < cnt; i++) {
+		if (argc > 0) {
+			int j;
+			for (j = 0; j < argc; j++) {
+				if (strcmp(argv[j], xvfsp[i].vfc_name) == 0)
+					break;
 			}
+			if (j == argc)
+				continue;
 		}
-	} else {
-		if (sysctlbyname("vfs.conflist", NULL, &buflen, NULL, 0) < 0)
-			err(EXIT_FAILURE, "sysctl(vfs.conflist)");
-		if ((xvfsp = malloc(buflen)) == NULL)
-			errx(EXIT_FAILURE, "malloc failed");
-		if (sysctlbyname("vfs.conflist", xvfsp, &buflen, NULL, 0) < 0)
-			err(EXIT_FAILURE, "sysctl(vfs.conflist)");
-		cnt = buflen / sizeof(struct xvfsconf);
-
-		for (size_t i = 0; i < cnt; i++) {
-			printf(FMT, xvfsp[i].vfc_name, xvfsp[i].vfc_typenum,
-			    xvfsp[i].vfc_refcount,
-			    fmt_flags(xvfsp[i].vfc_flags));
-		}
-		free(xvfsp);
+
+		printf(FMT, xvfsp[i].vfc_name, xvfsp[i].vfc_typenum,
+		    xvfsp[i].vfc_refcount, fmt_flags(xvfsp[i].vfc_flags));
 	}
+	free(xvfsp);
 
 	return (rv);
 }
diff --git a/usr.bin/lzmainfo/Makefile b/usr.bin/lzmainfo/Makefile
index afde07163a01..e537e4c86083 100644
--- a/usr.bin/lzmainfo/Makefile
+++ b/usr.bin/lzmainfo/Makefile
@@ -1,3 +1,5 @@
+PACKAGE=xz
+
 PROG=	lzmainfo
 
 XZDIR=	${SRCTOP}/contrib/xz/src
diff --git a/usr.bin/mandoc/Makefile b/usr.bin/mandoc/Makefile
index 2c7c3ed85040..181d4e16c8ee 100644
--- a/usr.bin/mandoc/Makefile
+++ b/usr.bin/mandoc/Makefile
@@ -60,8 +60,7 @@ LIB_SRCS=	${LIBMAN_SRCS} \
 		mandoc_xr.c \
 		msec.c \
 		preconv.c \
-		read.c \
-		compat_recallocarray.c \
+		read.c
 
 HTML_SRCS=	eqn_html.c \
 		html.c \
diff --git a/usr.bin/mdo/mdo.c b/usr.bin/mdo/mdo.c
index 8435fc17f26f..3eb5d4e5c23f 100644
--- a/usr.bin/mdo/mdo.c
+++ b/usr.bin/mdo/mdo.c
@@ -1,13 +1,24 @@
 /*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
  * Copyright(c) 2024 Baptiste Daroussin <bapt@FreeBSD.org>
+ * Copyright (c) 2025 Kushagra Srivastava <kushagra1403@gmail.com>
+ * Copyright (c) 2025 The FreeBSD Foundation
  *
- * SPDX-License-Identifier: BSD-2-Clause
+ * Portions of this software were developed by Olivier Certner
+ * <olce@FreeBSD.org> at Kumacom SARL under sponsorship from the FreeBSD
+ * Foundation.
  */
 
+#include <sys/errno.h>
 #include <sys/limits.h>
+#include <sys/types.h>
 #include <sys/ucred.h>
 
+#include <assert.h>
 #include <err.h>
+#include <getopt.h>
+#include <grp.h>
 #include <paths.h>
 #include <pwd.h>
 #include <stdbool.h>
@@ -16,84 +27,848 @@
 #include <string.h>
 #include <unistd.h>
 
+
 static void
 usage(void)
 {
-	fprintf(stderr, "usage: mdo [-u username] [-i] [--] [command [args]]\n");
-	exit(EXIT_FAILURE);
+	fprintf(stderr,
+	    "Usage: mdo [options] [--] [command [args...]]\n"
+	    "\n"
+	    "Options:\n"
+	    "  -u <user>         Target user (name or UID; name sets groups)\n"
+	    "  -k                Keep current user, allows selective overrides "
+	    "(implies -i)\n"
+	    "  -i                Keep current groups, unless explicitly overridden\n"
+	    "  -g <group>        Override primary group (name or GID)\n"
+	    "  -G <g1,g2,...>    Set supplementary groups (name or GID list)\n"
+	    "  -s <mods>         Modify supplementary groups using:\n"
+	    "                      @ (first) to reset, +group to add, -group to remove\n"
+	    "\n"
+	    "Advanced UID/GID overrides:\n"
+	    "  --euid <uid>      Set effective UID\n"
+	    "  --ruid <uid>      Set real UID\n"
+	    "  --svuid <uid>     Set saved UID\n"
+	    "  --egid <gid>      Set effective GID\n"
+	    "  --rgid <gid>      Set real GID\n"
+	    "  --svgid <gid>     Set saved GID\n"
+	    "\n"
+	    "  -h                Show this help message\n"
+	    "\n"
+	    "Examples:\n"
+	    "  mdo -u alice id\n"
+	    "  mdo -u 1001 -g wheel -G staff,operator sh\n"
+	    "  mdo -u bob -s +wheel,+operator id\n"
+	    "  mdo -k --ruid 1002 --egid 1004 id\n"
+	);
+	exit(1);
+}
+
+struct alloc {
+	void	*start;
+	size_t	 size;
+};
+
+static const struct alloc ALLOC_INITIALIZER = {
+	.start = NULL,
+	.size = 0,
+};
+
+/*
+ * The default value should cover almost all cases.
+ *
+ * For getpwnam_r(), we assume:
+ * - 88 bytes for 'struct passwd'
+ * - Less than 16 bytes for the user name
+ * - A typical shadow hash of 106 bytes
+ * - Less than 16 bytes for the login class name
+ * - Less than 64 bytes for GECOS info
+ * - Less than 128 bytes for the home directory
+ * - Less than 32 bytes for the shell path
+ * Total: 256 + 88 + 106 = 450.
+ *
+ * For getgrnam_r(), we assume:
+ * - 32 bytes for 'struct group'
+ * - Less than 16 bytes for the group name
+ * - Some hash of 106 bytes
+ * - No more than 16 members, each of less than 16 bytes (=> 256 bytes)
+ * Total: 256 + 32 + 16 + 106 = 410.
+ *
+ * We thus choose 512 (leeway, power of 2).
+ */
+static const size_t ALLOC_FIRST_SIZE = 512;
+
+static bool
+alloc_is_empty(const struct alloc *const alloc)
+{
+	if (alloc->size == 0) {
+		assert(alloc->start == NULL);
+		return (true);
+	} else {
+		assert(alloc->start != NULL);
+		return (false);
+	}
+}
+
+static void
+alloc_realloc(struct alloc *const alloc)
+{
+	const size_t old_size = alloc->size;
+	size_t new_size;
+
+	if (old_size == 0) {
+		assert(alloc->start == NULL);
+		new_size = ALLOC_FIRST_SIZE;
+	} else if (old_size < PAGE_SIZE)
+		new_size = 2 * old_size;
+	else
+		/*
+		 * We never allocate more than a page at a time when reaching
+		 * a page (except perhaps for the first increment, up to two).
+		 * Use roundup2() to be immune to previous cases' changes. */
+		new_size = roundup2(old_size, PAGE_SIZE) + PAGE_SIZE;
+
+	alloc->start = realloc(alloc->start, new_size);
+	if (alloc->start == NULL)
+		errx(EXIT_FAILURE,
+		    "cannot realloc allocation (old size: %zu, new: %zu)",
+		    old_size, new_size);
+	alloc->size = new_size;
+}
+
+static void
+alloc_free(struct alloc *const alloc)
+{
+	if (!alloc_is_empty(alloc)) {
+		free(alloc->start);
+		*alloc = ALLOC_INITIALIZER;
+	}
+}
+
+struct alloc_wrap_data {
+	int (*func)(void *data, const struct alloc *alloc);
+};
+
+/*
+ * Wraps functions needing a backing allocation.
+ *
+ * Uses 'alloc' as the starting allocation, and may extend it as necessary.
+ * 'alloc' is never freed, even on failure of the wrapped function.
+ *
+ * The function is expected to return ERANGE if and only if the provided
+ * allocation is not big enough.  All other values are passed through.
+ */
+static int
+alloc_wrap(struct alloc_wrap_data *const data, struct alloc *alloc)
+{
+	int error;
+
+	/* Avoid a systematic ERANGE on first iteration. */
+	if (alloc_is_empty(alloc))
+		alloc_realloc(alloc);
+
+	for (;;) {
+		error = data->func(data, alloc);
+		if (error != ERANGE)
+			break;
+		alloc_realloc(alloc);
+	}
+
+	return (error);
+}
+
+struct getpwnam_wrapper_data {
+	struct alloc_wrap_data	  wrapped;
+	const char		 *name;
+	struct passwd		**pwdp;
+};
+
+static int
+wrapped_getpwnam_r(void *data, const struct alloc *alloc)
+{
+	struct passwd *const pwd = alloc->start;
+	struct passwd *result;
+	struct getpwnam_wrapper_data *d = data;
+	int error;
+
+	assert(alloc->size >= sizeof(*pwd));
+
+	error = getpwnam_r(d->name, pwd, (char *)(pwd + 1),
+	    alloc->size - sizeof(*pwd), &result);
+
+	if (error == 0) {
+		if (result == NULL)
+			error = ENOENT;
+	} else
+		assert(result == NULL);
+	*d->pwdp = result;
+	return (error);
+}
+
+/*
+ * Wraps getpwnam_r(), automatically dealing with memory allocation.
+ *
+ * 'alloc' may be any allocation (even empty), and will be extended as
+ * necessary.  It is not freed on error.
+ *
+ * On success, '*pwdp' is filled with a pointer to the returned 'struct passwd',
+ * and on failure, is set to NULL.
+ */
+static int
+alloc_getpwnam(const char *name, struct passwd **pwdp,
+    struct alloc *const alloc)
+{
+	struct getpwnam_wrapper_data data;
+
+	data.wrapped.func = wrapped_getpwnam_r;
+	data.name = name;
+	data.pwdp = pwdp;
+	return (alloc_wrap((struct alloc_wrap_data *)&data, alloc));
+}
+
+struct getgrnam_wrapper_data {
+	struct alloc_wrap_data	  wrapped;
+	const char		 *name;
+	struct group		**grpp;
+};
+
+static int
+wrapped_getgrnam_r(void *data, const struct alloc *alloc)
+{
+	struct group *grp = alloc->start;
+	struct group *result;
+	struct getgrnam_wrapper_data *d = data;
+	int error;
+
+	assert(alloc->size >= sizeof(*grp));
+
+	error = getgrnam_r(d->name, grp, (char *)(grp + 1),
+	    alloc->size - sizeof(*grp), &result);
+
+	if (error == 0) {
+		if (result == NULL)
+			error = ENOENT;
+	} else
+		assert(result == NULL);
+	*d->grpp = result;
+	return (error);
+}
+
+/*
+ * Wraps getgrnam_r(), automatically dealing with memory allocation.
+ *
+ * 'alloc' may be any allocation (even empty), and will be extended as
+ * necessary.  It is not freed on error.
+ *
+ * On success, '*grpp' is filled with a pointer to the returned 'struct group',
+ * and on failure, is set to NULL.
+ */
+static int
+alloc_getgrnam(const char *const name, struct group **const grpp,
+    struct alloc *const alloc)
+{
+	struct getgrnam_wrapper_data data;
+
+	data.wrapped.func = wrapped_getgrnam_r;
+	data.name = name;
+	data.grpp = grpp;
+	return (alloc_wrap((struct alloc_wrap_data *)&data, alloc));
+}
+
+/*
+ * Retrieve the UID from a user string.
+ *
+ * Tries first to interpret the string as a user name, then as a numeric ID
+ * (this order is prescribed by POSIX for a number of utilities).
+ *
+ * 'pwdp' and 'allocp' must be NULL or non-NULL together.  If non-NULL, then
+ * 'allocp' can be any allocation (possibly empty) and will be extended to
+ * contain the result if necessary.  It will not be freed (even on failure).
+ */
+static uid_t
+parse_user_pwd(const char *s, struct passwd **pwdp, struct alloc *allocp)
+{
+	struct passwd *pwd;
+	struct alloc alloc = ALLOC_INITIALIZER;
+	const char *errp;
+	uid_t uid;
+	int error;
+
+	assert((pwdp == NULL && allocp == NULL) ||
+	    (pwdp != NULL && allocp != NULL));
+
+	if (pwdp == NULL) {
+		pwdp = &pwd;
+		allocp = &alloc;
+	}
+
+	error = alloc_getpwnam(s, pwdp, allocp);
+	if (error == 0) {
+		uid = (*pwdp)->pw_uid;
+		goto finish;
+	} else if (error != ENOENT)
+		errc(EXIT_FAILURE, error,
+		    "cannot access the password database");
+
+	uid = strtonum(s, 0, UID_MAX, &errp);
+	if (errp != NULL)
+		errx(EXIT_FAILURE, "invalid UID '%s': %s", s, errp);
+
+finish:
+	if (allocp == &alloc)
+		alloc_free(allocp);
+	return (uid);
+}
+
+/* See parse_user_pwd() for the doc. */
+static uid_t
+parse_user(const char *s)
+{
+	return (parse_user_pwd(s, NULL, NULL));
+}
+
+/*
+ * Retrieve the GID from a group string.
+ *
+ * Tries first to interpret the string as a group name, then as a numeric ID
+ * (this order is prescribed by POSIX for a number of utilities).
+ */
+static gid_t
+parse_group(const char *s)
+{
+	struct group *grp;
+	struct alloc alloc = ALLOC_INITIALIZER;
+	const char *errp;
+	gid_t gid;
+	int error;
+
+	error = alloc_getgrnam(s, &grp, &alloc);
+	if (error == 0) {
+		gid = grp->gr_gid;
+		goto finish;
+	} else if (error != ENOENT)
+		errc(EXIT_FAILURE, error, "cannot access the group database");
+
+	gid = strtonum(s, 0, GID_MAX, &errp);
+	if (errp != NULL)
+		errx(EXIT_FAILURE, "invalid GID '%s': %s", s, errp);
+
+finish:
+	alloc_free(&alloc);
+	return (gid);
+}
+
+struct group_array {
+	u_int	 nb;
+	gid_t	*groups;
+};
+
+static const struct group_array GROUP_ARRAY_INITIALIZER = {
+	.nb = 0,
+	.groups = NULL,
+};
+
+static bool
+group_array_is_empty(const struct group_array *const ga)
+{
+	return (ga->nb == 0);
+}
+
+static void
+realloc_groups(struct group_array *const ga, const u_int diff)
+{
+	const u_int new_nb = ga->nb + diff;
+	const size_t new_size = new_nb * sizeof(*ga->groups);
+
+	assert(new_nb >= diff && new_size >= new_nb);
+	ga->groups = realloc(ga->groups, new_size);
+	if (ga->groups == NULL)
+		err(EXIT_FAILURE, "realloc of groups failed");
+	ga->nb = new_nb;
+}
+
+static int
+gidp_cmp(const void *p1, const void *p2)
+{
+	const gid_t g1 = *(const gid_t *)p1;
+	const gid_t g2 = *(const gid_t *)p2;
+
+	return ((g1 > g2) - (g1 < g2));
+}
+
+static void
+sort_uniq_groups(struct group_array *const ga)
+{
+	size_t j = 0;
+
+	if (ga->nb <= 1)
+		return;
+
+	qsort(ga->groups, ga->nb, sizeof(gid_t), gidp_cmp);
+
+	for (size_t i = 1; i < ga->nb; ++i)
+		if (ga->groups[i] != ga->groups[j])
+			ga->groups[++j] = ga->groups[i];
+}
+
+/*
+ * Remove elements in 'set' that are in 'remove'.
+ *
+ * Expects both arrays to have been treated with sort_uniq_groups(). Works in
+ * O(n + m), modifying 'set' in place.
+ */
+static void
+remove_groups(struct group_array *const set,
+    const struct group_array *const remove)
+{
+	u_int from = 0, to = 0, rem = 0;
+	gid_t cand, to_rem;
+
+	if (set->nb == 0 || remove->nb == 0)
+		/* Nothing to remove. */
+		return;
+
+	cand = set->groups[0];
+	to_rem = remove->groups[0];
+
+	for (;;) {
+		if (cand < to_rem) {
+			/* Keep. */
+			if (to != from)
+				set->groups[to] = cand;
+			++to;
+			cand = set->groups[++from];
+			if (from == set->nb)
+				break;
+		} else if (cand == to_rem) {
+			cand = set->groups[++from];
+			if (from == set->nb)
+				break;
+			to_rem = remove->groups[++rem]; /* No duplicates. */
+			if (rem == remove->nb)
+				break;
+		} else {
+			to_rem = remove->groups[++rem];
+			if (rem == remove->nb)
+				break;
+		}
+	}
+
+	/* All remaining groups in 'set' must be kept. */
+	if (from == to)
+		/* Nothing was removed.  'set' will stay the same. */
+		return;
+	memmove(set->groups + to, set->groups + from,
+	    (set->nb - from) * sizeof(gid_t));
+	set->nb = to + (set->nb - from);
 }
 
 int
 main(int argc, char **argv)
 {
-	struct passwd *pw;
-	const char *username = "root";
+	const char *const default_user = "root";
+
+	const char *user_name = NULL;
+	const char *primary_group = NULL;
+	char *supp_groups_str = NULL;
+	char *supp_mod_str = NULL;
+	bool start_from_current_groups = false;
+	bool start_from_current_users = false;
+	const char *euid_str = NULL;
+	const char *ruid_str = NULL;
+	const char *svuid_str = NULL;
+	const char *egid_str = NULL;
+	const char *rgid_str = NULL;
+	const char *svgid_str = NULL;
+	bool need_user = false; /* '-u' or '-k' needed. */
+
+	const int go_euid = 1000;
+	const int go_ruid = 1001;
+	const int go_svuid = 1002;
+	const int go_egid = 1003;
+	const int go_rgid = 1004;
+	const int go_svgid = 1005;
+	const struct option longopts[] = {
+		{"euid", required_argument, NULL, go_euid},
+		{"ruid", required_argument, NULL, go_ruid},
+		{"svuid", required_argument, NULL, go_svuid},
+		{"egid", required_argument, NULL, go_egid},
+		{"rgid", required_argument, NULL, go_rgid},
+		{"svgid", required_argument, NULL, go_svgid},
+		{NULL, 0, NULL, 0}
+	};
+	int ch;
+
 	struct setcred wcred = SETCRED_INITIALIZER;
 	u_int setcred_flags = 0;
-	bool uidonly = false;
-	int ch;
 
-	while ((ch = getopt(argc, argv, "u:i")) != -1) {
+	struct passwd *pw = NULL;
+	struct alloc pw_alloc = ALLOC_INITIALIZER;
+	struct group_array supp_groups = GROUP_ARRAY_INITIALIZER;
+	struct group_array supp_rem = GROUP_ARRAY_INITIALIZER;
+
+
+	/*
+	 * Process options.
+	 */
+	while (ch = getopt_long(argc, argv, "+G:g:hiks:u:", longopts, NULL),
+	    ch != -1) {
 		switch (ch) {
-		case 'u':
-			username = optarg;
+		case 'G':
+			supp_groups_str = optarg;
+			need_user = true;
+			break;
+		case 'g':
+			primary_group = optarg;
+			need_user = true;
 			break;
+		case 'h':
+			usage();
 		case 'i':
-			uidonly = true;
+			start_from_current_groups = true;
+			break;
+		case 'k':
+			start_from_current_users = true;
+			break;
+		case 's':
+			supp_mod_str = optarg;
+			need_user = true;
+			break;
+		case 'u':
+			user_name = optarg;
+			break;
+		case go_euid:
+			euid_str = optarg;
+			need_user = true;
+			break;
+		case go_ruid:
+			ruid_str = optarg;
+			need_user = true;
+			break;
+		case go_svuid:
+			svuid_str = optarg;
+			need_user = true;
+			break;
+		case go_egid:
+			egid_str = optarg;
+			need_user = true;
+			break;
+		case go_rgid:
+			rgid_str = optarg;
+			need_user = true;
+			break;
+		case go_svgid:
+			svgid_str = optarg;
+			need_user = true;
 			break;
 		default:
 			usage();
 		}
 	}
+
 	argc -= optind;
 	argv += optind;
 
-	if ((pw = getpwnam(username)) == NULL) {
-		if (strspn(username, "0123456789") == strlen(username)) {
-			const char *errp = NULL;
-			uid_t uid = strtonum(username, 0, UID_MAX, &errp);
-			if (errp != NULL)
-				err(EXIT_FAILURE, "invalid user ID '%s'",
-				    username);
-			pw = getpwuid(uid);
+	/*
+	 * Determine users.
+	 *
+	 * We do that first as in some cases we need to retrieve the
+	 * corresponding password database entry to be able to set the primary
+	 * groups.
+	 */
+
+	if (start_from_current_users) {
+		if (user_name != NULL)
+			errx(EXIT_FAILURE, "-k incompatible with -u");
+
+		/*
+		 * If starting from the current user(s) as a base, finding one
+		 * of them in the password database and using its groups would
+		 * be quite surprising, so we instead let '-k' imply '-i'.
+		 */
+		start_from_current_groups = true;
+	} else {
+		uid_t uid;
+
+		/*
+		 * In the case of any overrides, we impose an explicit base user
+		 * via '-u' or '-k' instead of implicitly taking 'root' as the
+		 * base.
+		 */
+		if (user_name == NULL) {
+			if (need_user)
+				errx(EXIT_FAILURE,
+				    "Some overrides specified, "
+				    "'-u' or '-k' needed.");
+			user_name = default_user;
 		}
+
+		/*
+		 * Even if all user overrides are present as well as primary and
+		 * supplementary groups ones, in which case the final result
+		 * doesn't depend on '-u', we still call parse_user_pwd() to
+		 * check that the passed username is correct.
+		 */
+		uid = parse_user_pwd(user_name, &pw, &pw_alloc);
+		wcred.sc_uid = wcred.sc_ruid = wcred.sc_svuid = uid;
+		setcred_flags |= SETCREDF_UID | SETCREDF_RUID |
+		    SETCREDF_SVUID;
+	}
+
+	if (euid_str != NULL) {
+		wcred.sc_uid = parse_user(euid_str);
+		setcred_flags |= SETCREDF_UID;
+	}
+
+	if (ruid_str != NULL) {
+		wcred.sc_ruid = parse_user(ruid_str);
+		setcred_flags |= SETCREDF_RUID;
+	}
+
+	if (svuid_str != NULL) {
+		wcred.sc_svuid = parse_user(svuid_str);
+		setcred_flags |= SETCREDF_SVUID;
+	}
+
+	/*
+	 * Determine primary groups.
+	 */
+
+	/*
+	 * When not starting from the current groups, we need to set all
+	 * primary groups.  If '-g' was not passed, we use the primary
+	 * group from the password database as the "base" to which
+	 * overrides '--egid', '--rgid' and '--svgid' apply.  But if all
+	 * overrides were specified, we in fact just don't need the
+	 * password database at all.
+	 *
+	 * '-g' is treated outside of this 'if' as it can also be used
+	 * as an override.
+	 */
+	if (!start_from_current_groups && primary_group == NULL &&
+	    (egid_str == NULL || rgid_str == NULL || svgid_str == NULL)) {
 		if (pw == NULL)
-			err(EXIT_FAILURE, "invalid username '%s'", username);
+			errx(EXIT_FAILURE,
+			    "must specify primary groups or a user name "
+			    "with an entry in the password database");
+
+		wcred.sc_gid = wcred.sc_rgid = wcred.sc_svgid =
+		    pw->pw_gid;
+		setcred_flags |= SETCREDF_GID | SETCREDF_RGID |
+		    SETCREDF_SVGID;
+	}
+
+	if (primary_group != NULL) {
+		/*
+		 * We always call parse_group() even in case all overrides are
+		 * present to check that the passed group is valid.
+		 */
+		wcred.sc_gid = wcred.sc_rgid = wcred.sc_svgid =
+		    parse_group(primary_group);
+		setcred_flags |= SETCREDF_GID | SETCREDF_RGID | SETCREDF_SVGID;
+	}
+
+	if (egid_str != NULL) {
+		wcred.sc_gid = parse_group(egid_str);
+		setcred_flags |= SETCREDF_GID;
+	}
+
+	if (rgid_str != NULL) {
+		wcred.sc_rgid = parse_group(rgid_str);
+		setcred_flags |= SETCREDF_RGID;
+	}
+
+	if (svgid_str != NULL) {
+		wcred.sc_svgid = parse_group(svgid_str);
+		setcred_flags |= SETCREDF_SVGID;
+	}
+
+	/*
+	 * Determine supplementary groups.
+	 */
+
+	/*
+	 * This makes sense to catch user's mistakes.  It is not a strong
+	 * limitation of the code below (allowing this case is just a matter of,
+	 * in the block treating '-s' with '@' below, replacing an assert() by
+	 * a reset of 'supp_groups').
+	 */
+	if (supp_groups_str != NULL && supp_mod_str != NULL &&
+	    supp_mod_str[0] == '@')
+		errx(EXIT_FAILURE, "'-G' and '-s' with '@' are incompatible");
+
+	/*
+	 * Determine the supplementary groups to start with, but only if we
+	 * really need to operate on them later (and set them back).
+	 */
+	if (!start_from_current_groups) {
+		assert(!start_from_current_users);
+
+		if (supp_groups_str == NULL && (supp_mod_str == NULL ||
+		    supp_mod_str[0] != '@')) {
+			/*
+			 * If we are to replace supplementary groups (i.e.,
+			 * neither '-i' nor '-k' was specified) and they are not
+			 * completely specified (with '-g' or '-s' with '@'), we
+			 * start from those in the groups database if we were
+			 * passed a user name that is in the password database
+			 * (this is a protection against erroneous ID/name
+			 * conflation in the groups database), else we simply
+			 * error.
+			 */
+
+			if (pw == NULL)
+				errx(EXIT_FAILURE,
+				    "must specify the full supplementary "
+				    "groups set or a user name with an entry "
+				    "in the password database");
+
+			const long ngroups_alloc = sysconf(_SC_NGROUPS_MAX) + 1;
+			gid_t *groups;
+			int ngroups;
+
+			groups = malloc(sizeof(*groups) * ngroups_alloc);
+			if (groups == NULL)
+				errx(EXIT_FAILURE,
+				    "cannot allocate memory to retrieve "
+				    "user groups from the groups database");
+
+			ngroups = ngroups_alloc;
+			getgrouplist(user_name, pw->pw_gid, groups, &ngroups);
+
+			if (ngroups > ngroups_alloc)
+				err(EXIT_FAILURE,
+				    "too many groups for user '%s'",
+				    user_name);
+
+			realloc_groups(&supp_groups, ngroups);
+			memcpy(supp_groups.groups + supp_groups.nb - ngroups,
+			    groups, ngroups * sizeof(*groups));
+			free(groups);
+
+			/*
+			 * Have to set SETCREDF_SUPP_GROUPS here since we may be
+			 * in the case where neither '-G' nor '-s' was passed,
+			 * but we still have to set the supplementary groups to
+			 * those of the groups database.
+			 */
+			setcred_flags |= SETCREDF_SUPP_GROUPS;
+		}
+	} else if (supp_groups_str == NULL && (supp_mod_str == NULL ||
+	    supp_mod_str[0] != '@')) {
+		const int ngroups = getgroups(0, NULL);
+
+		if (ngroups > 0) {
+			realloc_groups(&supp_groups, ngroups);
+
+			if (getgroups(ngroups, supp_groups.groups +
+			    supp_groups.nb - ngroups) < 0)
+				err(EXIT_FAILURE, "getgroups() failed");
+		}
+
+		/*
+		 * Setting SETCREDF_SUPP_GROUPS here is not necessary, we will
+		 * do it below since 'supp_mod_str' != NULL.
+		 */
 	}
 
-	wcred.sc_uid = wcred.sc_ruid = wcred.sc_svuid = pw->pw_uid;
-	setcred_flags |= SETCREDF_UID | SETCREDF_RUID | SETCREDF_SVUID;
+	if (supp_groups_str != NULL) {
+		char *p = supp_groups_str;
+		char *tok;
 
-	if (!uidonly) {
 		/*
-		 * If there are too many groups specified for some UID, setting
-		 * the groups will fail.  We preserve this condition by
-		 * allocating one more group slot than allowed, as
-		 * getgrouplist() itself is just some getter function and thus
-		 * doesn't (and shouldn't) check the limit, and to allow
-		 * setcred() to actually check for overflow.
+		 * We will set the supplementary groups to exactly the set
+		 * passed with '-G', and we took care above not to retrieve
+		 * "base" groups (current ones or those from the groups
+		 * database) in this case.
 		 */
-		const long ngroups_alloc = sysconf(_SC_NGROUPS_MAX) + 2;
-		gid_t *const groups = malloc(sizeof(*groups) * ngroups_alloc);
-		int ngroups = ngroups_alloc;
+		assert(group_array_is_empty(&supp_groups));
+
+		/* WARNING: 'supp_groups_str' going to be modified. */
+		while ((tok = strsep(&p, ",")) != NULL) {
+			gid_t g;
+
+			if (*tok == '\0')
+				continue;
+
+			g = parse_group(tok);
+			realloc_groups(&supp_groups, 1);
+			supp_groups.groups[supp_groups.nb - 1] = g;
+		}
+
+		setcred_flags |= SETCREDF_SUPP_GROUPS;
+	}
+
+	if (supp_mod_str != NULL) {
+		char *p = supp_mod_str;
+		char *tok;
+		gid_t gid;
 
-		if (groups == NULL)
-			err(EXIT_FAILURE, "cannot allocate memory for groups");
+		/* WARNING: 'supp_mod_str' going to be modified. */
+		while ((tok = strsep(&p, ",")) != NULL) {
+			switch (tok[0]) {
+			case '\0':
+			        break;
 
-		getgrouplist(pw->pw_name, pw->pw_gid, groups, &ngroups);
+			case '@':
+				if (tok != supp_mod_str)
+					errx(EXIT_FAILURE, "'@' must be "
+					    "the first token in '-s' option");
+				/* See same assert() above. */
+				assert(group_array_is_empty(&supp_groups));
+				break;
+
+			case '+':
+			case '-':
+				gid = parse_group(tok + 1);
+				if (tok[0] == '+') {
+					realloc_groups(&supp_groups, 1);
+					supp_groups.groups[supp_groups.nb - 1] = gid;
+				} else {
+					realloc_groups(&supp_rem, 1);
+					supp_rem.groups[supp_rem.nb - 1] = gid;
+				}
+				break;
+
+			default:
+				errx(EXIT_FAILURE,
+				    "invalid '-s' token '%s' at index %zu",
+				    tok, tok - supp_mod_str);
+			}
+		}
 
-		wcred.sc_gid = wcred.sc_rgid = wcred.sc_svgid = pw->pw_gid;
-		wcred.sc_supp_groups = groups + 1;
-		wcred.sc_supp_groups_nb = ngroups - 1;
-		setcred_flags |= SETCREDF_GID | SETCREDF_RGID | SETCREDF_SVGID |
-		    SETCREDF_SUPP_GROUPS;
+		setcred_flags |= SETCREDF_SUPP_GROUPS;
+	}
+
+	/*
+	 * We don't need to pass the kernel a normalized representation of the
+	 * new supplementary groups set (array sorted and without duplicates),
+	 * so we don't do it here unless we need to remove some groups, where it
+	 * enables more efficient algorithms (if the number of groups for some
+	 * reason grows out of control).
+	 */
+	if (!group_array_is_empty(&supp_groups) &&
+	    !group_array_is_empty(&supp_rem)) {
+		sort_uniq_groups(&supp_groups);
+		sort_uniq_groups(&supp_rem);
+		remove_groups(&supp_groups, &supp_rem);
+	}
+
+	if ((setcred_flags & SETCREDF_SUPP_GROUPS) != 0) {
+		wcred.sc_supp_groups = supp_groups.groups;
+		wcred.sc_supp_groups_nb = supp_groups.nb;
 	}
 
 	if (setcred(setcred_flags, &wcred, sizeof(wcred)) != 0)
-		err(EXIT_FAILURE, "calling setcred() failed");
+		err(EXIT_FAILURE, "setcred()");
+
+	/*
+	 * We don't bother freeing memory still allocated at this point as we
+	 * are about to exec() or exit.
+	 */
 
 	if (*argv == NULL) {
 		const char *sh = getenv("SHELL");
+
 		if (sh == NULL)
 			sh = _PATH_BSHELL;
 		execlp(sh, sh, "-i", NULL);
diff --git a/usr.bin/mididump/Makefile b/usr.bin/mididump/Makefile
index 758bbb3a1189..5b22376b7bb8 100644
--- a/usr.bin/mididump/Makefile
+++ b/usr.bin/mididump/Makefile
@@ -1,5 +1,7 @@
 .include <src.opts.mk>
 
+PACKAGE=	sound
+
 PROG=		mididump
 SRCS=		${PROG}.c
 MAN=		${PROG}.1
diff --git a/usr.bin/netstat/if.c b/usr.bin/netstat/if.c
index 622141e4ff69..7ee03eb3689b 100644
--- a/usr.bin/netstat/if.c
+++ b/usr.bin/netstat/if.c
@@ -282,7 +282,8 @@ next_ifma(struct ifmaddrs *ifma, const char *name, const sa_family_t family)
 
 		sdl = (struct sockaddr_dl *)ifma->ifma_name;
 		if (ifma->ifma_addr->sa_family == family &&
-		    strcmp(sdl->sdl_data, name) == 0)
+		    sdl->sdl_nlen == strlen(name) &&
+		    strncmp(sdl->sdl_data, name, sdl->sdl_nlen) == 0)
 			break;
 	}
 
diff --git a/usr.bin/tcopy/tcopy.cc b/usr.bin/tcopy/tcopy.cc
index 37a146376c2e..a1dd35682aac 100644
--- a/usr.bin/tcopy/tcopy.cc
+++ b/usr.bin/tcopy/tcopy.cc
@@ -580,7 +580,9 @@ getspace(size_t blk)
 static void
 usage(void)
 {
-	fprintf(stderr, "usage: tcopy [-cvx] [-s maxblk] [src [dest]]\n");
+	fprintf(stderr,
+            "usage: tcopy [-crvx] [-l logfile] [-s maxblk] [src [dest]]\n"
+        );
 	exit(1);
 }
 
diff --git a/usr.bin/xz/Makefile b/usr.bin/xz/Makefile
index 0d5bce4c16f0..0a9103d60a13 100644
--- a/usr.bin/xz/Makefile
+++ b/usr.bin/xz/Makefile
@@ -1,5 +1,7 @@
 .include <src.opts.mk>
 
+PACKAGE=xz
+
 PROG=	xz
 
 LINKS=	${BINDIR}/xz ${BINDIR}/unxz
diff --git a/usr.bin/xzdec/Makefile b/usr.bin/xzdec/Makefile
index 7c43b2e03d78..6bf3dc07a408 100644
--- a/usr.bin/xzdec/Makefile
+++ b/usr.bin/xzdec/Makefile
@@ -1,3 +1,5 @@
+PACKAGE=xz
+
 PROG=	xzdec
 
 LINKS=	${BINDIR}/xzdec ${BINDIR}/lzdec
diff --git a/usr.sbin/Makefile b/usr.sbin/Makefile
index 90b360ac55e6..3c5fd0973a43 100644
--- a/usr.sbin/Makefile
+++ b/usr.sbin/Makefile
@@ -99,7 +99,6 @@ SUBDIR=	adduser \
 	valectl \
 	vigr \
 	vipw \
-	virtual_oss \
 	wake \
 	watch \
 	watchdogd \
@@ -129,6 +128,7 @@ SUBDIR.${MK_BSNMP}+=	bsnmpd
 .if ${MK_CAROOT} != "no"
 SUBDIR.${MK_OPENSSL}+=	certctl
 .endif
+SUBDIR.${MK_CUSE}+=	virtual_oss
 SUBDIR.${MK_CXGBETOOL}+=	cxgbetool
 SUBDIR.${MK_EFI}+=	efivar efidp efibootmgr efitable efiwake
 .if ${MK_OPENSSL} != "no"
@@ -210,7 +210,7 @@ SUBDIR.${MK_UTMPX}+=	ac
 SUBDIR.${MK_UTMPX}+=	lastlogin
 SUBDIR.${MK_UTMPX}+=	utx
 SUBDIR.${MK_WIRELESS}+=	wlandebug
-SUBDIR.${MK_WIRELESS}+=	wlanstats
+SUBDIR.${MK_WIRELESS}+=	wlanstat
 SUBDIR.${MK_WIRELESS}+=	wpa
 
 SUBDIR.${MK_TESTS}+=	tests
diff --git a/usr.sbin/acpi/acpidump/acpi.c b/usr.sbin/acpi/acpidump/acpi.c
index a8a3c953d72d..63613d5a4707 100644
--- a/usr.sbin/acpi/acpidump/acpi.c
+++ b/usr.sbin/acpi/acpidump/acpi.c
@@ -1764,7 +1764,7 @@ acpi_handle_ivrs_ivhd_devs(ACPI_IVRS_DE_HEADER *d, char *de)
 			d8b = (ACPI_IVRS_DEVICE8B *)db;
 			len = sizeof(*d8b);
 			printf("\t\tDev Type=%#x Id=%#06x",
-			    d8a->Header.Type, d8a->Header.Id);
+			    d8b->Header.Type, d8b->Header.Id);
 			acpi_handle_ivrs_ivhd_dte(d8b->Header.DataSetting);
 			printf("\t\t");
 			acpi_handle_ivrs_ivhd_edte(d8b->ExtendedData);
@@ -1774,7 +1774,7 @@ acpi_handle_ivrs_ivhd_devs(ACPI_IVRS_DE_HEADER *d, char *de)
 			d4 = (ACPI_IVRS_DEVICE4 *)(db + sizeof(*d8b));
 			len = sizeof(*d8b) + sizeof(*d4);
 			printf("\t\tDev Type=%#x Id=%#06x-%#06x",
-			    d8a->Header.Type, d8a->Header.Id, d4->Header.Id);
+			    d8b->Header.Type, d8b->Header.Id, d4->Header.Id);
 			acpi_handle_ivrs_ivhd_dte(d8b->Header.DataSetting);
 			acpi_handle_ivrs_ivhd_edte(d8b->ExtendedData);
 		} else if (d->Type == ACPI_IVRS_TYPE_SPECIAL) {
diff --git a/usr.sbin/bsdinstall/bsdinstall.8 b/usr.sbin/bsdinstall/bsdinstall.8
index 5ccbaef87835..6175d26b4fd3 100644
--- a/usr.sbin/bsdinstall/bsdinstall.8
+++ b/usr.sbin/bsdinstall/bsdinstall.8
@@ -1,4 +1,6 @@
-.\"-
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
 .\" Copyright (c) 2011-2013 Nathan Whitehorn <nwhitehorn@FreeBSD.org> All rights reserved.
 .\" Copyright (c) 2018 Roberto Fernandez Cueto <roberfern@gmail.com>
 .\" Copyright (c) 2024 The FreeBSD Foundation
@@ -27,7 +29,7 @@
 .\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 .\" POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd November 4, 2024
+.Dd October 3, 2025
 .Dt BSDINSTALL 8
 .Os
 .Sh NAME
@@ -40,9 +42,10 @@
 .Op Ar ...
 .Sh DESCRIPTION
 .Nm
-is used for installation of new systems, both for system setup from
-installation media, e.g., CD-ROMs, and for use on live systems to prepare
-VM images and jails.
+is used for installation of new systems,
+both for system setup from installation media,
+such as discs, USBs, or network boot environments,
+and for use on live systems to prepare jails and virtual machine images.
 .Pp
 Much like
 .Xr make 1 , Nm
@@ -56,7 +59,7 @@ these subtargets can be invoked separately by an installation script.
 .Sh OPTIONS
 .Nm
 supports the following options, global to all targets:
-.Bl -tag -width indent+
+.Bl -tag -width "-D file"
 .It Fl D Ar file
 Provide a path for the installation log file
 .Pq overrides Ev BSDINSTALL_LOG .
@@ -73,7 +76,7 @@ For interactive use, most users will be interested only in the
 and
 .Cm script
 targets.
-.Bl -tag -width "jail destination"
+.Bl -tag -width "-D file"
 .It Cm auto
 Run the standard interactive installation, including disk partitioning.
 .It Cm jail Ar destination
@@ -244,7 +247,7 @@ Extracts the distributions listed in
 .Ev DISTRIBUTIONS
 into
 .Ev BSDINSTALL_CHROOT .
-.It Cm pkgbase Op Fl --no-kernel
+.It Cm pkgbase Op Fl --jail
 Fetch and install base system packages to
 .Ev BSDINSTALL_CHROOT .
 Packages are fetched according to repository configuration in
@@ -253,8 +256,10 @@ if set, or
 .Lk pkg.freebsd.org
 otherwise.
 If the
-.Fl --no-kernel
-option is passed, no kernel is installed.
+.Fl --jail
+option is passed, no kernel is installed, and the
+.Dq jail
+variant of each package set will be selected where applicable.
 .It Cm firmware
 executes
 .Xr fwget 8
@@ -293,7 +298,7 @@ Many are used internally during installation and have reasonable default values
 for most installation scenarios.
 Others are set by various interactive user prompts, and can be usefully
 overridden when making scripted or customized installers.
-.Bl -tag -width "BSDINSTALL_DISTSITE"
+.Bl -tag -width "-D file"
 .It Ev TMPDIR
 The directory to use for temporary files.
 Default:
diff --git a/usr.sbin/bsdinstall/scripts/auto b/usr.sbin/bsdinstall/scripts/auto
index 0b47d496fdbd..61d52065af2a 100755
--- a/usr.sbin/bsdinstall/scripts/auto
+++ b/usr.sbin/bsdinstall/scripts/auto
@@ -178,6 +178,9 @@ environment_save
 rm -rf $BSDINSTALL_TMPETC
 mkdir $BSDINSTALL_TMPETC
 
+# Reset the ESP list
+: > ${TMPDIR:-"/tmp"}/bsdinstall-esps
+
 # With pkgbase, pkg OOM has been observed with QEMU-default 128 MiB memory size.
 # Ensure we have at least about 256 MiB (with an allowance for rounding etc.).
 physmem=$(($(sysctl -n hw.physmem) / 1048576))
diff --git a/usr.sbin/bsdinstall/scripts/bootconfig b/usr.sbin/bsdinstall/scripts/bootconfig
index 41243ad14b9b..6736e78b450a 100755
--- a/usr.sbin/bsdinstall/scripts/bootconfig
+++ b/usr.sbin/bsdinstall/scripts/bootconfig
@@ -63,6 +63,24 @@ dialog_uefi_entryname()
 		2>&1 >&$DIALOG_TERMINAL_PASSTHRU_FD
 }
 
+# Copy to the normal FreeBSD location. Also copy to the default location if it
+# doesn't exist. This covers setups where UEFI NV variables can't be set and
+# some buggy firmware, while preserving complex UEFI setups for multiple booting
+# (rEFInd, etc).
+uefi_copy_loader()
+{
+    local ldr=$1
+    local freebsd_dir=$2
+    local default_dir=$3
+    local dest=$4
+
+    mkdir -p "${freebsd_dir}" "${default_dir}"
+    cp "${ldr}" "${freebsd_dir}"
+    if [ ! -f "${default_dir}/${dest}" ]; then
+	cp "${ldr}" "${default_dir}/${dest}"
+    fi
+}
+
 update_uefi_bootentry()
 {
 	nentries=$(efibootmgr | grep -c "${EFI_LABEL_NAME}$")
@@ -113,6 +131,7 @@ if [ -n "$(awk '{if ($2=="/boot/efi") printf("%s\n",$1);}' $PATH_FSTAB)" ]; then
 	    *)		die "Unsupported arch $(uname -m) for UEFI install"
 	esac
 
+	# Support the weird 32-bit firmware loading 64-bit kernels
 	if [ `sysctl -n machdep.efi_arch` == i386 ]; then
 		ARCHBOOTNAME=ia32
 		file=loader_ia32.efi
@@ -120,31 +139,31 @@ if [ -n "$(awk '{if ($2=="/boot/efi") printf("%s\n",$1);}' $PATH_FSTAB)" ]; then
 		file=loader.efi
 	fi
 
-	BOOTDIR="/efi/boot"
-	BOOTNAME="${BOOTDIR}/boot${ARCHBOOTNAME}.efi"
-	FREEBSD_BOOTDIR="/efi/freebsd"
-	FREEBSD_BOOTNAME="${FREEBSD_BOOTDIR}/${file}"
+	# Copy the boot loader
 	mntpt="$BSDINSTALL_CHROOT/boot/efi"
-
 	f_dprintf "Installing ${file} onto ESP"
-	mkdir -p "${mntpt}/${FREEBSD_BOOTDIR}" "${mntpt}/${BOOTDIR}"
-	cp "$BSDINSTALL_CHROOT/boot/${file}" "${mntpt}/${FREEBSD_BOOTNAME}"
-
-	#
-	# UEFI defines a way to specifically select what to boot
-	# (which we do via efibootmgr). However, if we booted from an ia32
-	# UEFI environment, we wouldn't have access to efirt. In addition,
-	# virtual environments often times lack support for the NV variables
-	# efibootmgr sets, and some UEFI implementations have features that
-	# interfere with the setting of these variables. To combat that, we
-	# install the default removable media boot file if it doesn't exist.
-	# We don't install it all the time since that can interfere with other
-	# installations on the drive (like rEFInd).
-	#
-	if [ ! -f "${mntpt}/${BOOTNAME}" ]; then
-		cp "$BSDINSTALL_CHROOT/boot/${file}" "${mntpt}/${BOOTNAME}"
+	uefi_copy_loader "$BSDINSTALL_CHROOT/boot/${file}" \
+		"${mntpt}/efi/freebsd" "${mntpt}/efi/boot" \
+		boot${ARCHBOOTNAME}.efi
+
+	# zfsboot records the extra esp partitions it creates to -esps.  These
+	# are newfs'd at the time of creation. We don't support installing ufs
+	# over gmirror, so we only do this for ZFS.
+	esps=${TMPDIR:-"/tmp"}/bsdinstall-esps
+	if [ -f "$esps" ]; then
+		mntpt=$(mktemp -d -t bsdinstall-esp)
+		for dev in $(cat $esps); do
+			f_dprintf "Installing ${file} onto redundant ESP ${dev}"
+			mount -t msdos "$dev" "$mntpt"
+			uefi_copy_loader "$BSDINSTALL_CHROOT/boot/${file}" \
+				"${mntpt}/efi/freebsd" "${mntpt}/efi/boot" \
+				boot${ARCHBOOTNAME}.efi
+			umount "$mntpt"
+		done
+		rmdir "${mntpt}"
 	fi
 
+	# Try to set the UEFI NV BootXXXX variables to recod the boot location
 	if [ "$BSDINSTALL_CONFIGCURRENT" ] && [ "$ARCHBOOTNAME" != ia32 ]; then
 		update_uefi_bootentry
 	fi
diff --git a/usr.sbin/bsdinstall/scripts/jail b/usr.sbin/bsdinstall/scripts/jail
index 0c3c7e125fdd..f2c7ef2b37de 100755
--- a/usr.sbin/bsdinstall/scripts/jail
+++ b/usr.sbin/bsdinstall/scripts/jail
@@ -183,7 +183,7 @@ if [ ! "$nonInteractive" == "YES" ]; then
 fi
 
 if [ "$PKGBASE" == yes ]; then
-	bsdinstall pkgbase --no-kernel || error "Installation of base system packages failed"
+	bsdinstall pkgbase --jail || error "Installation of base system packages failed"
 else
 	distbase
 fi
diff --git a/usr.sbin/bsdinstall/scripts/pkgbase.in b/usr.sbin/bsdinstall/scripts/pkgbase.in
index 0b7554644028..5299d34fcb71 100755
--- a/usr.sbin/bsdinstall/scripts/pkgbase.in
+++ b/usr.sbin/bsdinstall/scripts/pkgbase.in
@@ -79,7 +79,10 @@ local function select_components(components, options)
 	local descriptions = {
 		["kernel-dbg"] = "Debug symbols for the kernel",
 		["devel"] = "C/C++ compilers and related utilities",
-		["base"] = "The complete base system (includes devel)",
+		["optional"] = "Optional software (excluding compilers)",
+		["optional-jail"] = "Optional software (excluding compilers)",
+		["base"] = "The complete base system (includes devel and optional)",
+		["base-jail"] = "The complete base system (includes devel and optional)",
 		["src"] = "System source tree",
 		["tests"] = "Test suite",
 		["lib32"] = "32-bit compatibility libraries",
@@ -90,6 +93,7 @@ local function select_components(components, options)
 	-- by default.
 	local defaults = {
 		["base"] = "on",
+		["base-jail"] = "on",
 		["kernel-dbg"] = "on",
 	}
 	-- Enable compat sets by default.
@@ -100,40 +104,66 @@ local function select_components(components, options)
 	-- Sorting the components is necessary to ensure that the ordering is
 	-- consistent in the UI.
 	local sorted_components = {}
+
+	-- Determine which components we want to offer the user.
+	local show_component = function (component)
+		-- "pkg" is always installed if present.
+		if component == "pkg" then return false end
+
+		-- Don't include individual "-dbg" components, because those
+		-- are handled via the "debug" component, except for kernel-dbg
+		-- which is always shown for non-jail installations.
+		if component == "kernel-dbg" then
+			return (not options.jail)
+		end
+		if component:match("%-dbg$") then return false end
+
+		-- Some sets have "-jail" variants which are jail-specific
+		-- variants of the base set.
+
+		if options.jail and components[component.."-jail"] then
+			-- If we're installing in a jail, and this component
+			-- has a jail variant, hide it.
+			return false
+		end
+
+		if not options.jail and component:match("%-jail$") then
+			-- Otherwise if we're not installing in a jail, and
+			-- this is a jail variant, hide it.
+			return false
+		end
+
+		-- "minimal(-jail)" is always installed if present.
+		if component == "minimal" or component == "minimal-jail" then
+			return false
+		end
+
+		-- "kernel" (the generic kernel) and "kernels" (the set) are
+		-- never offered; we always install the kernel for a non-jail
+		-- installation.
+		if component == "kernel" or component == "kernels" then
+			return false
+		end
+
+		-- If we didn't find a reason to hide this component, show it.
+		return true
+	end
+
 	for component, _ in pairs(components) do
-		-- Decide which sets we want to offer to the user:
-		--
-		-- "minimal" is not offered since it's always included, as is
-		-- "pkg" if it's present.
-		--
-		-- "-dbg" sets are never offered, because those are handled
-		-- via the "debug" component.
-		--
-		-- "kernels" is never offered because we only want one kernel,
-		-- which is handled separately.
-		--
-		-- Sets whose name ends in "-jail" are intended for jails, and
-		-- are only offered if no_kernel is set.
-		if component ~= "pkg" and
-		   not component:match("^minimal") and
-		   not component:match("%-dbg$") and
-		   not (component == "kernels") and
-		   not (not options.no_kernel and component:match("%-jail$")) then
+		if show_component(component) then
 			table.insert(sorted_components, component)
 		end
 	end
+
 	table.sort(sorted_components)
 
 	local checklist_items = {}
 	for _, component in ipairs(sorted_components) do
-		if component ~= "kernel" and not
-		    (component == "kernel-dbg" and options.no_kernel) then
-			local description = descriptions[component] or ""
-			local default = defaults[component] or "off"
-			table.insert(checklist_items, component)
-			table.insert(checklist_items, description)
-			table.insert(checklist_items, default)
-		end
+		local description = descriptions[component] or ""
+		local default = defaults[component] or "off"
+		table.insert(checklist_items, component)
+		table.insert(checklist_items, description)
+		table.insert(checklist_items, default)
 	end
 
 	local bsddialog_args = {
@@ -161,7 +191,12 @@ local function select_components(components, options)
 	-- to work.  The base set depends on minimal, but it's fine to install
 	-- both, and this way the user can remove the base set without pkg
 	-- autoremove then trying to remove minimal.
-	local selected = {"minimal"}
+	local selected = {}
+	if options.jail then
+		table.insert(selected, "minimal-jail")
+	else
+		table.insert(selected, "minimal")
+	end
 
 	-- If pkg is available, always install it so the user can manage the
 	-- installed system.  This is optional, because a repository built
@@ -170,7 +205,7 @@ local function select_components(components, options)
 		table.insert(selected, "pkg")
 	end
 
-	if not options.no_kernel then
+	if not options.jail then
 		table.insert(selected, "kernel")
 	end
 
@@ -263,8 +298,8 @@ end
 local function parse_options()
 	local options = {}
 	for _, a in ipairs(arg) do
-		if a == "--no-kernel" then
-			options.no_kernel = true
+		if a == "--jail" then
+			options.jail = true
 		else
 			io.stderr:write("Error: unknown option " .. a .. "\n")
 			os.exit(1)
diff --git a/usr.sbin/bsdinstall/scripts/services b/usr.sbin/bsdinstall/scripts/services
index 93282effbb3f..110b6f321ed1 100755
--- a/usr.sbin/bsdinstall/scripts/services
+++ b/usr.sbin/bsdinstall/scripts/services
@@ -40,21 +40,44 @@ fi
 
 echo -n > $BSDINSTALL_TMPETC/rc.conf.services
 
+DAEMON_OPTIONS=""
+
+if [ -x "${BSDINSTALL_CHROOT}/etc/rc.d/sshd" ]; then
+	DAEMON_OPTIONS="$DAEMON_OPTIONS \
+	    sshd \"Secure shell daemon\" ${sshd_enable:-off}"
+fi
+
+if [ -x "${BSDINSTALL_CHROOT}/etc/rc.d/ntpd" ]; then
+	DAEMON_OPTIONS="$DAEMON_OPTIONS \
+	    ntpd \"Synchronize system and network time\" ${ntpd_enable:-off} \
+	    ntpd_sync_on_start \"Sync time on ntpd startup, even if offset is high\" \
+		${ntpd_sync_on_start:-off}"
+fi
+
+if [ -x "${BSDINSTALL_CHROOT}/etc/rc.d/local_unbound" ]; then
+	DAEMON_OPTIONS="$DAEMON_OPTIONS \
+	    local_unbound \"Local caching validating resolver\" \
+		${local_unbound_enable:-off}"
+fi
+
+if [ -x "${BSDINSTALL_CHROOT}/etc/rc.d/powerd" ]; then
+	DAEMON_OPTIONS="$DAEMON_OPTIONS \
+	    powerd \"Adjust CPU frequency dynamically if supported\" \
+		${powerd_enable:-off}"
+fi
+
+if [ -x "${BSDINSTALL_CHROOT}/etc/rc.d/moused" ]; then
+	DAEMON_OPTIONS="$DAEMON_OPTIONS \
+	    moused \"PS/2 mouse pointer on console\" ${moused_enable:-off}"
+fi
+
 exec 5>&1
-DAEMONS=$( bsddialog --backtitle "$OSNAME Installer" \
-    --title "System Configuration" --no-cancel --separate-output \
-    --checklist "Choose the services you would like to be started at boot:" \
+DAEMONS=$(eval bsddialog --backtitle \"$OSNAME Installer\" \
+    --title \"System Configuration\" --no-cancel --separate-output \
+    --checklist \"Choose the services you would like to be started at boot:\" \
     0 0 0 \
-	local_unbound "Local caching validating resolver" \
-		${local_unbound_enable:-off} \
-	sshd	"Secure shell daemon" ${sshd_enable:-off} \
-	moused	"PS/2 mouse pointer on console" ${moused_enable:-off} \
-	ntpd	"Synchronize system and network time" ${ntpd_enable:-off} \
-	ntpd_sync_on_start	"Sync time on ntpd startup, even if offset is high" \
-		${ntpd_sync_on_start:-off} \
-	powerd	"Adjust CPU frequency dynamically if supported" \
-		${powerd_enable:-off} \
-	dumpdev "Enable kernel crash dumps to /var/crash" ${dumpdev:-on} \
+	$DAEMON_OPTIONS \
+	dumpdev \"Enable kernel crash dumps to /var/crash\" ${dumpdev:-on} \
 2>&1 1>&5 )
 retval=$?
 exec 5>&-
diff --git a/usr.sbin/bsdinstall/scripts/zfsboot b/usr.sbin/bsdinstall/scripts/zfsboot
index 5fbf56ea59ac..95cbba3fa131 100755
--- a/usr.sbin/bsdinstall/scripts/zfsboot
+++ b/usr.sbin/bsdinstall/scripts/zfsboot
@@ -760,6 +760,7 @@ zfs_create_diskpart()
 {
 	local funcname=zfs_create_diskpart
 	local disk="$1" index="$2"
+	local efibootpart
 
 	# Check arguments
 	if [ ! "$disk" ]; then
@@ -867,18 +868,22 @@ zfs_create_diskpart()
 			             $disk || return $FAILURE
 
 			# We'll configure the ESP in bootconfig
-			if [ -z "$efibootpart" ]; then
-				efibootpart="/dev/gpt/efiboot$index"
-				f_dprintf "$funcname: configuring ESP at [%s]" \
-				          "${efibootpart}"
-
-				f_eval_catch $funcname newfs_msdos "$NEWFS_ESP"\
-				             "$efibootpart" \
-				             || return $FAILURE
+			# Note: This will always be p1
+			efibootpart="/dev/gpt/efiboot$index"
+			f_dprintf "$funcname: configuring ESP at [%s]" \
+			          "${efibootpart}"
+
+			f_eval_catch $funcname newfs_msdos "$NEWFS_ESP"\
+			             "$efibootpart" \
+			             || return $FAILURE
+			if [ $index -eq 0 ]; then
 				f_eval_catch $funcname printf "$PRINTF_FSTAB" \
-					     $efibootpart /boot/efi msdosfs \
-				             rw 2 2 "$BSDINSTALL_TMPETC/fstab" \
-				             || return $FAILURE
+					$efibootpart /boot/efi msdosfs \
+					rw 2 2 "$BSDINSTALL_TMPETC/fstab" \
+					|| return $FAILURE
+			else
+				# Record the extra ones
+				echo "${efibootpart}" >> ${TMPDIR:-"/tmp"}/bsdinstall-esps
 			fi
 		fi
 
@@ -1021,7 +1026,6 @@ zfs_create_boot()
 	local isswapmirror
 	local bootpart targetpart swappart # Set by zfs_create_diskpart() below
 	local create_options
-	local efibootpart
 
 	#
 	# Pedantic checks; should never be seen
diff --git a/usr.sbin/crashinfo/crashinfo.sh b/usr.sbin/crashinfo/crashinfo.sh
index 3bb1e1456462..68115f09f9d4 100755
--- a/usr.sbin/crashinfo/crashinfo.sh
+++ b/usr.sbin/crashinfo/crashinfo.sh
@@ -217,10 +217,7 @@ echo
 
 file=`mktemp /tmp/crashinfo.XXXXXX`
 if [ $? -eq 0 ]; then
-	scriptdir=/usr/libexec/kgdb
-
 	echo "bt -full" >> $file
-	echo "source ${scriptdir}/acttrace.py" >> $file
 	echo "acttrace" >> $file
 	echo "quit" >> $file
 	${GDB%gdb}kgdb -q $KERNEL $VMCORE < $file
diff --git a/usr.sbin/cxgbetool/Makefile b/usr.sbin/cxgbetool/Makefile
index cc5290b8aaf5..bf24b11c18c8 100644
--- a/usr.sbin/cxgbetool/Makefile
+++ b/usr.sbin/cxgbetool/Makefile
@@ -6,6 +6,7 @@ SRCS+=	tcb_common.c
 SRCS+=	tcbinfot4.c tcbshowt4.c
 SRCS+=	tcbinfot5.c tcbshowt5.c
 SRCS+=	tcbinfot6.c tcbshowt6.c
+SRCS+=	tcbinfot7.c tcbshowt7.c
 CFLAGS+= -I${SRCTOP}/sys/dev/cxgbe -I${SRCTOP}/sys -I.
 LIBADD=	pcap
 WARNS?= 2
diff --git a/usr.sbin/cxgbetool/cxgbetool.c b/usr.sbin/cxgbetool/cxgbetool.c
index c3bd883b39fc..68de86d74092 100644
--- a/usr.sbin/cxgbetool/cxgbetool.c
+++ b/usr.sbin/cxgbetool/cxgbetool.c
@@ -1,6 +1,5 @@
 /*-
- * Copyright (c) 2011 Chelsio Communications, Inc.
- * All rights reserved.
+ * Copyright (c) 2011, 2025 Chelsio Communications.
  * Written by: Navdeep Parhar <np@FreeBSD.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -92,6 +91,7 @@ struct field_desc {
 #include "reg_defs_t4.c"
 #include "reg_defs_t5.c"
 #include "reg_defs_t6.c"
+#include "reg_defs_t7.c"
 #include "reg_defs_t4vf.c"
 
 static void
@@ -436,6 +436,48 @@ dump_regs_t6(int argc, const char *argv[], const uint32_t *regs)
 }
 #undef T6_MODREGS
 
+#define T7_MODREGS(name) { #name, t7_##name##_regs }
+static int
+dump_regs_t7(int argc, const char *argv[], const uint32_t *regs)
+{
+	static struct mod_regs t7_mod[] = {
+		T7_MODREGS(sge),
+		{ "pci", t7_pcie_regs },
+		T7_MODREGS(dbg),
+		{ "mc0", t7_mc_t70_regs },
+		T7_MODREGS(ma),
+		{ "edc0", t7_edc_t60_regs },
+		{ "edc1", t7_edc_t61_regs },
+		T7_MODREGS(cim),
+		T7_MODREGS(tp),
+		{ "ulprx", t7_ulp_rx_regs },
+		{ "ulptx", t7_ulp_tx_regs },
+		{ "pmrx", t7_pm_rx_regs },
+		{ "pmtx", t7_pm_tx_regs },
+		T7_MODREGS(mps),
+		{ "cplsw", t7_cpl_switch_regs },
+		T7_MODREGS(smb),
+		{ "i2c", t7_i2cm_regs },
+		T7_MODREGS(mi),
+		T7_MODREGS(uart),
+		T7_MODREGS(pmu),
+		T7_MODREGS(sf),
+		T7_MODREGS(pl),
+		T7_MODREGS(le),
+		T7_MODREGS(ncsi),
+		{ "mac", t7_mac_t7_regs },
+		{ "hma", t7_hma_t6_regs },
+		{ "crypto0", t7_crypto_0_regs },
+		{ "crypto1", t7_crypto_1_regs },
+		{ "cryptokey", t7_crypto_key_regs },
+		T7_MODREGS(arm),
+		T7_MODREGS(gcache),
+	};
+
+	return dump_regs_table(argc, argv, regs, t7_mod, nitems(t7_mod));
+}
+#undef T7_MODREGS
+
 static int
 dump_regs_t4vf(int argc, const char *argv[], const uint32_t *regs)
 {
@@ -479,6 +521,20 @@ dump_regs_t6vf(int argc, const char *argv[], const uint32_t *regs)
 }
 
 static int
+dump_regs_t7vf(int argc, const char *argv[], const uint32_t *regs)
+{
+	static struct mod_regs t7vf_mod[] = {
+		{ "sge", t5vf_sge_regs },
+		{ "mps", t4vf_mps_regs },
+		{ "pl", t7vf_pl_regs },
+		{ "mbdata", t4vf_mbdata_regs },
+		{ "cim", t4vf_cim_regs },
+	};
+
+	return dump_regs_table(argc, argv, regs, t7vf_mod, nitems(t7vf_mod));
+}
+
+static int
 dump_regs(int argc, const char *argv[])
 {
 	int vers, revision, rc;
@@ -515,6 +571,11 @@ dump_regs(int argc, const char *argv[])
 			rc = dump_regs_t6vf(argc, argv, regs.data);
 		else
 			rc = dump_regs_t6(argc, argv, regs.data);
+	} else if (vers == 7) {
+		if (revision == 0x3f)
+			rc =  dump_regs_t7vf(argc, argv, regs.data);
+		else
+			rc =  dump_regs_t7(argc, argv, regs.data);
 	} else {
 		warnx("%s (type %d, rev %d) is not a known card.",
 		    g.nexus, vers, revision);
@@ -1492,7 +1553,180 @@ show_struct(const uint32_t *words, int nwords, const struct field_desc *fd)
 #define FIELD1(name, start) FIELD(name, start, start)
 
 static void
-show_t5t6_ctxt(const struct t4_sge_context *p, int vers)
+show_t7_ctxt(const struct t4_sge_ctxt *p)
+{
+	static struct field_desc egress_t7[] = {
+		FIELD("uPToken_4k:", 197, 198),
+		FIELD("WrLength_5:", 196, 196),
+		FIELD("CpuId:", 193, 195),
+		FIELD("PCIeDataChannel_1:", 192, 192),
+		FIELD("DCA_ST:", 181, 191),
+		FIELD("StatusPgNS:", 180, 180),
+		FIELD("StatusPgRO:", 179, 179),
+		FIELD("FetchNS:", 178, 178),
+		FIELD("FetchRO:", 177, 177),
+		FIELD("Valid:", 176, 176),
+		FIELD("ReschedulePending_1:", 175, 175),
+		FIELD("PCIeDataChannel:", 174, 174),
+		FIELD("StatusPgTPHintEn:", 173, 173),
+		FIELD("StatusPgTPHint:", 171, 172),
+		FIELD("FetchTPHintEn:", 170, 170),
+		FIELD("FetchTPHint:", 168, 169),
+		FIELD("FCThreshOverride:", 167, 167),
+		{ "WRLength:", 162, 166, 9, 0, 1 },
+		FIELD("WRLengthKnown:", 161, 161),
+		FIELD("ReschedulePending:", 160, 160),
+		FIELD("TimerIx:", 157, 159),
+		FIELD("FetchBurstMin:", 156, 156),
+		FIELD("FLMPacking:", 155, 155),
+		FIELD("FetchBurstMax:", 153, 154),
+		FIELD("uPToken:", 133, 152),
+		FIELD("uPTokenEn:", 132, 132),
+		FIELD("UserModeIO:", 131, 131),
+		FIELD("uPFLCredits:", 123, 130),
+		FIELD("uPFLCreditEn:", 122, 122),
+		FIELD("FID:", 111, 121),
+		FIELD("HostFCMode:", 109, 110),
+		FIELD("HostFCOwner:", 108, 108),
+		{ "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
+		FIELD("CIDX:", 89, 104),
+		FIELD("PIDX:", 73, 88),
+		{ "BaseAddress:", 18, 72, 9, 1 },
+		FIELD("QueueSize:", 2, 17),
+		FIELD("QueueType:", 1, 1),
+		FIELD("FetchSizeMode:", 0, 0),
+		{ NULL }
+	};
+	static struct field_desc fl_t7[] = {
+		FIELD("FLMcontextID_4k:", 197, 198),
+		FIELD("CpuId:", 193, 195),
+		FIELD("PCIeDataChannel_1:", 192, 192),
+		FIELD("DCA_ST:", 181, 191),
+		FIELD("StatusPgNS:", 180, 180),
+		FIELD("StatusPgRO:", 179, 179),
+		FIELD("FetchNS:", 178, 178),
+		FIELD("FetchRO:", 177, 177),
+		FIELD("Valid:", 176, 176),
+		FIELD("PCIeDataChannel:", 174, 175),
+		FIELD("StatusPgTPHintEn:", 173, 173),
+		FIELD("StatusPgTPHint:", 171, 172),
+		FIELD("FetchTPHintEn:", 170, 170),
+		FIELD("FetchTPHint:", 168, 169),
+		FIELD("FCThreshOverride:", 167, 167),
+		FIELD("ReschedulePending:", 160, 160),
+		FIELD("OnChipQueue:", 159, 159),
+		FIELD("FetchSizeMode:", 158, 158),
+		{ "FetchBurstMin:", 156, 157, 4, 0, 1 },
+		FIELD("FLMPacking:", 155, 155),
+		FIELD("FetchBurstMax:", 153, 154),
+		FIELD("FLMcongMode:", 152, 152),
+		FIELD("MaxuPFLCredits:", 144, 151),
+		FIELD("FLMcontextID:", 133, 143),
+		FIELD("uPTokenEn:", 132, 132),
+		FIELD("UserModeIO:", 131, 131),
+		FIELD("uPFLCredits:", 123, 130),
+		FIELD("uPFLCreditEn:", 122, 122),
+		FIELD("FID:", 111, 121),
+		FIELD("HostFCMode:", 109, 110),
+		FIELD("HostFCOwner:", 108, 108),
+		{ "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
+		FIELD("CIDX:", 89, 104),
+		FIELD("PIDX:", 73, 88),
+		{ "BaseAddress:", 18, 72, 9, 1 },
+		FIELD("QueueSize:", 2, 17),
+		FIELD("QueueType:", 1, 1),
+		FIELD("CachePriority:", 0, 0),
+		{ NULL }
+	};
+	static struct field_desc ingress_t7[] = {
+		FIELD("Fid:", 171, 182),
+		FIELD("InterruptIDX4K:", 170, 170),
+		FIELD("CoalEn:", 169, 169),
+		FIELD("CoalAbort:", 168, 168),
+		FIELD("CoalCntr:", 161, 167),
+		FIELD("CoalCompTimerStatus:", 160, 160),
+		FIELD("CoalCompCntrStatus:", 159, 159),
+		FIELD("SP_NS:", 158, 158),
+		FIELD("SP_RO:", 157, 157),
+		FIELD("SP_TPHintEn:", 156, 156),
+		FIELD("SP_TPHint:", 154, 155),
+		FIELD("DCA_ST:", 143, 153),
+		FIELD("ISCSICoalescing:", 142, 142),
+		FIELD("Queue_Valid:", 141, 141),
+		FIELD("TimerPending:", 140, 140),
+		FIELD("DropRSS:", 139, 139),
+		FIELD("PCIeChannel:", 137, 138),
+		FIELD("SEInterruptArmed:", 136, 136),
+		FIELD("CongestionMgtEnable:", 135, 135),
+		FIELD("NoSnoop:", 134, 134),
+		FIELD("RelaxedOrdering:", 133, 133),
+		FIELD("GTSmode:", 132, 132),
+		FIELD("TPHintEn:", 131, 131),
+		FIELD("TPHint:", 129, 130),
+		FIELD("UpdateScheduling:", 128, 128),
+		FIELD("UpdateDelivery:", 126, 127),
+		FIELD("InterruptSent:", 125, 125),
+		FIELD("InterruptIDX:", 114, 124),
+		FIELD("InterruptDestination:", 113, 113),
+		FIELD("InterruptArmed:", 112, 112),
+		FIELD("RxIntCounter:", 106, 111),
+		FIELD("RxIntCounterThreshold:", 104, 105),
+		FIELD("Generation:", 103, 103),
+		{ "BaseAddress:", 48, 102, 9, 1 },
+		FIELD("PIDX:", 32, 47),
+		FIELD("CIDX:", 16, 31),
+		{ "QueueSize:", 4, 15, 4, 0 },
+		{ "QueueEntrySize:", 2, 3, 4, 0, 1 },
+		FIELD("QueueEntryOverride:", 1, 1),
+		FIELD("CachePriority:", 0, 0),
+		{ NULL }
+	};
+	static struct field_desc flm_t7[] = {
+		FIELD("MidCongEn:", 154, 154),
+		FIELD("FlPtr:", 90, 153),
+		FIELD("Valid:", 89, 89),
+		FIELD("SplitLenMode:", 87, 88),
+		FIELD("TPHintEn:", 86, 86),
+		FIELD("TPHint:", 84, 85),
+		FIELD("NoSnoop:", 83, 83),
+		FIELD("RelaxedOrdering:", 82, 82),
+		FIELD("DCA_ST:", 71, 81),
+		FIELD("EQid:", 54, 70),
+		FIELD("SplitEn:", 52, 53),
+		FIELD("PadEn:", 51, 51),
+		FIELD("PackEn:", 50, 50),
+		FIELD("Cache_Lock :", 49, 49),
+		FIELD("CongDrop:", 48, 48),
+		FIELD("Inflifght:", 47, 47),
+		FIELD("CongEn:", 46, 46),
+		FIELD("CongMode:", 45, 45),
+		FIELD("PackOffset:", 20, 39),
+		FIELD("CIDX:", 8, 15),
+		FIELD("PIDX:", 0, 7),
+		{ NULL }
+	};
+	static struct field_desc conm_t7[] = {
+		FIELD("CngMPSEnable:", 37, 37),
+		FIELD("CngTPMode:", 35, 36),
+		FIELD("CngDBPHdr:", 34, 34),
+		FIELD("CngDBPData:", 33, 33),
+		FIELD("CngIMSG:", 32, 32),
+		{ "CngChMap:", 0, 31, 0, 1, 0 },
+		{ NULL }
+	};
+
+	if (p->mem_id == SGE_CONTEXT_EGRESS)
+		show_struct(p->data, 7, (p->data[0] & 2) ? fl_t7 : egress_t7);
+	else if (p->mem_id == SGE_CONTEXT_FLM)
+		show_struct(p->data, 5, flm_t7);
+	else if (p->mem_id == SGE_CONTEXT_INGRESS)
+		show_struct(p->data, 6, ingress_t7);
+	else if (p->mem_id == SGE_CONTEXT_CNM)
+		show_struct(p->data, 2, conm_t7);
+}
+
+static void
+show_t5t6_ctxt(const struct t4_sge_ctxt *p, int vers)
 {
 	static struct field_desc egress_t5[] = {
 		FIELD("DCA_ST:", 181, 191),
@@ -1743,7 +1977,7 @@ show_t5t6_ctxt(const struct t4_sge_context *p, int vers)
 }
 
 static void
-show_t4_ctxt(const struct t4_sge_context *p)
+show_t4_ctxt(const struct t4_sge_ctxt *p)
 {
 	static struct field_desc egress_t4[] = {
 		FIELD1("StatusPgNS:", 180),
@@ -1887,7 +2121,7 @@ get_sge_context(int argc, const char *argv[])
 	int rc;
 	char *p;
 	long cid;
-	struct t4_sge_context cntxt = {0};
+	struct t4_sge_ctxt cntxt = {0};
 
 	if (argc != 2) {
 		warnx("sge_context: incorrect number of arguments.");
@@ -1915,14 +2149,21 @@ get_sge_context(int argc, const char *argv[])
 	}
 	cntxt.cid = cid;
 
-	rc = doit(CHELSIO_T4_GET_SGE_CONTEXT, &cntxt);
+	rc = doit(CHELSIO_T4_GET_SGE_CTXT, &cntxt);
 	if (rc != 0)
 		return (rc);
 
-	if (g.chip_id == 4)
+	switch (g.chip_id) {
+	case 4:
 		show_t4_ctxt(&cntxt);
-	else
+		break;
+	case 5:
+	case 6:
 		show_t5t6_ctxt(&cntxt, g.chip_id);
+		break;
+	default:
+		show_t7_ctxt(&cntxt);
+	}
 
 	return (0);
 }
diff --git a/usr.sbin/cxgbetool/reg_defs_t4vf.c b/usr.sbin/cxgbetool/reg_defs_t4vf.c
index 5ea7d4f276dd..bf60ee8a8356 100644
--- a/usr.sbin/cxgbetool/reg_defs_t4vf.c
+++ b/usr.sbin/cxgbetool/reg_defs_t4vf.c
@@ -122,6 +122,21 @@ struct reg_info t6vf_pl_regs[] = {
 	{ NULL, 0, 0 }
 };
 
+struct reg_info t7vf_pl_regs[] = {
+	{ "PL_WHOAMI",				0x200, 0 },
+		{ "PortxMap", 24, 3 },
+		{ "SourceBus", 16, 2 },
+		{ "SourcePF", 9, 3 },
+		{ "IsVF", 8, 1 },
+		{ "VFID", 0, 8 },
+	{ "PL_VF_REV",				0x204, 0 },
+		{ "ChipID", 4, 4 },
+		{ "Rev", 0, 4 },
+	{ "PL_VF_REVISION",			0x208, 0 },
+
+	{ NULL, 0, 0 }
+};
+
 struct reg_info t4vf_cim_regs[] = {
 	/*
 	 * Note: the Mailbox Control register has read side-effects so
diff --git a/usr.sbin/cxgbetool/reg_defs_t7.c b/usr.sbin/cxgbetool/reg_defs_t7.c
new file mode 100644
index 000000000000..549db9c546d5
--- /dev/null
+++ b/usr.sbin/cxgbetool/reg_defs_t7.c
@@ -0,0 +1,28216 @@
+/* This file is automatically generated --- changes will be lost */
+/* Generation Date : Thu Sep 11 05:26:14 PM IST 2025 */
+/* Directory name: t7_reg.txt, Changeset: 5945:1487219ecb20 */
+
+struct reg_info t7_sge_regs[] = {
+	{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1e004, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1e400, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1e404, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1e800, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1e804, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1ec00, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1ec04, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1f000, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1f004, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1f400, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1f404, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1f800, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1f804, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 },
+	{ "SGE_PF_KDOORBELL", 0x1fc00, 0 },
+		{ "QID", 15, 17 },
+		{ "Sync", 14, 1 },
+		{ "Type", 13, 1 },
+		{ "PIDX", 0, 13 },
+	{ "SGE_PF_GTS", 0x1fc04, 0 },
+		{ "IngressQID", 16, 16 },
+		{ "TimerReg", 13, 3 },
+		{ "SEIntArm", 12, 1 },
+		{ "CIDXInc", 0, 12 },
+	{ "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 },
+	{ "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 },
+	{ "SGE_CONTROL", 0x1008, 0 },
+		{ "IgrAllCPLtoFL", 31, 1 },
+		{ "FLSplitMin", 22, 9 },
+		{ "NumOfFid", 19, 3 },
+		{ "RxPktCPLMode", 18, 1 },
+		{ "EgrStatusPageSize", 17, 1 },
+		{ "IngHintEnable2", 16, 1 },
+		{ "IngHintEnable1", 15, 1 },
+		{ "IngHintEnable0", 14, 1 },
+		{ "IngIntCompareIDX", 13, 1 },
+		{ "PktShift", 10, 3 },
+		{ "IngPCIeBoundary", 7, 3 },
+		{ "IngPadBoundary", 4, 3 },
+		{ "IngHintEnable3", 3, 1 },
+		{ "tf_mode", 1, 2 },
+		{ "GlobalEnable", 0, 1 },
+	{ "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
+		{ "HostPageSizePF7", 28, 4 },
+		{ "HostPageSizePF6", 24, 4 },
+		{ "HostPageSizePF5", 20, 4 },
+		{ "HostPageSizePF4", 16, 4 },
+		{ "HostPageSizePF3", 12, 4 },
+		{ "HostPageSizePF2", 8, 4 },
+		{ "HostPageSizePF1", 4, 4 },
+		{ "HostPageSizePF0", 0, 4 },
+	{ "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
+		{ "QueuesPerPagePF7", 28, 4 },
+		{ "QueuesPerPagePF6", 24, 4 },
+		{ "QueuesPerPagePF5", 20, 4 },
+		{ "QueuesPerPagePF4", 16, 4 },
+		{ "QueuesPerPagePF3", 12, 4 },
+		{ "QueuesPerPagePF2", 8, 4 },
+		{ "QueuesPerPagePF1", 4, 4 },
+		{ "QueuesPerPagePF0", 0, 4 },
+	{ "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
+		{ "QueuesPerPageVFPF7", 28, 4 },
+		{ "QueuesPerPageVFPF6", 24, 4 },
+		{ "QueuesPerPageVFPF5", 20, 4 },
+		{ "QueuesPerPageVFPF4", 16, 4 },
+		{ "QueuesPerPageVFPF3", 12, 4 },
+		{ "QueuesPerPageVFPF2", 8, 4 },
+		{ "QueuesPerPageVFPF1", 4, 4 },
+		{ "QueuesPerPageVFPF0", 0, 4 },
+	{ "SGE_USER_MODE_LIMITS", 0x1018, 0 },
+		{ "Opcode_Min", 24, 8 },
+		{ "Opcode_Max", 16, 8 },
+		{ "Length_Min", 8, 8 },
+		{ "Length_Max", 0, 8 },
+	{ "SGE_WR_ERROR", 0x101c, 0 },
+		{ "WR_Sendpath_Error_Opcode", 16, 8 },
+		{ "WR_Sendpath_Opcode", 8, 8 },
+		{ "WR_Error_Opcode", 0, 8 },
+	{ "SGE_INT_CAUSE1", 0x1024, 0 },
+		{ "perr_flm_CreditFifo", 30, 1 },
+		{ "perr_imsg_hint_fifo", 29, 1 },
+		{ "perr_headersplit_fifo3", 28, 1 },
+		{ "perr_headersplit_fifo2", 27, 1 },
+		{ "perr_payload_fifo3", 26, 1 },
+		{ "perr_payload_fifo2", 25, 1 },
+		{ "perr_pc_rsp", 23, 1 },
+		{ "perr_pc_req", 22, 1 },
+		{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
+		{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
+		{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
+		{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
+		{ "perr_dmarbt", 17, 1 },
+		{ "perr_flm_DbpFifo", 16, 1 },
+		{ "perr_flm_MCReq_fifo", 15, 1 },
+		{ "perr_flm_HintFifo", 14, 1 },
+		{ "perr_align_ctl_fifo3", 13, 1 },
+		{ "perr_align_ctl_fifo2", 12, 1 },
+		{ "perr_align_ctl_fifo1", 11, 1 },
+		{ "perr_align_ctl_fifo0", 10, 1 },
+		{ "perr_edma_fifo3", 9, 1 },
+		{ "perr_edma_fifo2", 8, 1 },
+		{ "perr_edma_fifo1", 7, 1 },
+		{ "perr_edma_fifo0", 6, 1 },
+		{ "perr_pd_fifo3", 5, 1 },
+		{ "perr_pd_fifo2", 4, 1 },
+		{ "perr_pd_fifo1", 3, 1 },
+		{ "perr_pd_fifo0", 2, 1 },
+		{ "perr_ing_ctxt_mifrsp", 1, 1 },
+		{ "perr_egr_ctxt_mifrsp", 0, 1 },
+	{ "SGE_INT_ENABLE1", 0x1028, 0 },
+		{ "perr_flm_CreditFifo", 30, 1 },
+		{ "perr_imsg_hint_fifo", 29, 1 },
+		{ "perr_headersplit_fifo3", 28, 1 },
+		{ "perr_headersplit_fifo2", 27, 1 },
+		{ "perr_payload_fifo3", 26, 1 },
+		{ "perr_payload_fifo2", 25, 1 },
+		{ "perr_pc_rsp", 23, 1 },
+		{ "perr_pc_req", 22, 1 },
+		{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
+		{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
+		{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
+		{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
+		{ "perr_dmarbt", 17, 1 },
+		{ "perr_flm_DbpFifo", 16, 1 },
+		{ "perr_flm_MCReq_fifo", 15, 1 },
+		{ "perr_flm_HintFifo", 14, 1 },
+		{ "perr_align_ctl_fifo3", 13, 1 },
+		{ "perr_align_ctl_fifo2", 12, 1 },
+		{ "perr_align_ctl_fifo1", 11, 1 },
+		{ "perr_align_ctl_fifo0", 10, 1 },
+		{ "perr_edma_fifo3", 9, 1 },
+		{ "perr_edma_fifo2", 8, 1 },
+		{ "perr_edma_fifo1", 7, 1 },
+		{ "perr_edma_fifo0", 6, 1 },
+		{ "perr_pd_fifo3", 5, 1 },
+		{ "perr_pd_fifo2", 4, 1 },
+		{ "perr_pd_fifo1", 3, 1 },
+		{ "perr_pd_fifo0", 2, 1 },
+		{ "perr_ing_ctxt_mifrsp", 1, 1 },
+		{ "perr_egr_ctxt_mifrsp", 0, 1 },
+	{ "SGE_PERR_ENABLE1", 0x102c, 0 },
+		{ "perr_flm_CreditFifo", 30, 1 },
+		{ "perr_imsg_hint_fifo", 29, 1 },
+		{ "perr_headersplit_fifo3", 28, 1 },
+		{ "perr_headersplit_fifo2", 27, 1 },
+		{ "perr_payload_fifo3", 26, 1 },
+		{ "perr_payload_fifo2", 25, 1 },
+		{ "perr_pc_rsp", 23, 1 },
+		{ "perr_pc_req", 22, 1 },
+		{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
+		{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
+		{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
+		{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
+		{ "perr_dmarbt", 17, 1 },
+		{ "perr_flm_DbpFifo", 16, 1 },
+		{ "perr_flm_MCReq_fifo", 15, 1 },
+		{ "perr_flm_HintFifo", 14, 1 },
+		{ "perr_align_ctl_fifo3", 13, 1 },
+		{ "perr_align_ctl_fifo2", 12, 1 },
+		{ "perr_align_ctl_fifo1", 11, 1 },
+		{ "perr_align_ctl_fifo0", 10, 1 },
+		{ "perr_edma_fifo3", 9, 1 },
+		{ "perr_edma_fifo2", 8, 1 },
+		{ "perr_edma_fifo1", 7, 1 },
+		{ "perr_edma_fifo0", 6, 1 },
+		{ "perr_pd_fifo3", 5, 1 },
+		{ "perr_pd_fifo2", 4, 1 },
+		{ "perr_pd_fifo1", 3, 1 },
+		{ "perr_pd_fifo0", 2, 1 },
+		{ "perr_ing_ctxt_mifrsp", 1, 1 },
+		{ "perr_egr_ctxt_mifrsp", 0, 1 },
+	{ "SGE_INT_CAUSE2", 0x1030, 0 },
+		{ "tf_fifo_perr", 24, 1 },
+		{ "perr_egr_dbp_tx_coal", 23, 1 },
+		{ "perr_dbp_fl_fifo", 22, 1 },
+		{ "deq_ll_perr", 21, 1 },
+		{ "enq_perr", 20, 1 },
+		{ "deq_out_perr", 19, 1 },
+		{ "buf_perr", 18, 1 },
+		{ "perr_isw_idma3_fifo", 15, 1 },
+		{ "perr_conm_sram", 14, 1 },
+		{ "perr_isw_idma2_fifo", 13, 1 },
+		{ "perr_isw_idma0_fifo", 12, 1 },
+		{ "perr_isw_idma1_fifo", 11, 1 },
+		{ "perr_isw_dbp_fifo", 10, 1 },
+		{ "perr_isw_gts_fifo", 9, 1 },
+		{ "perr_itp_evr", 8, 1 },
+		{ "perr_flm_cntxmem", 7, 1 },
+		{ "perr_flm_l1Cache", 6, 1 },
+		{ "sge_ipp_fifo_perr", 5, 1 },
+		{ "perr_dbp_hp_fifo", 4, 1 },
+		{ "perr_db_fifo", 3, 1 },
+		{ "perr_ing_ctxt_cache", 2, 1 },
+		{ "perr_egr_ctxt_cache", 1, 1 },
+		{ "perr_base_size", 0, 1 },
+	{ "SGE_INT_ENABLE2", 0x1034, 0 },
+		{ "tf_fifo_perr", 24, 1 },
+		{ "perr_egr_dbp_tx_coal", 23, 1 },
+		{ "perr_dbp_fl_fifo", 22, 1 },
+		{ "deq_ll_perr", 21, 1 },
+		{ "enq_perr", 20, 1 },
+		{ "deq_out_perr", 19, 1 },
+		{ "buf_perr", 18, 1 },
+		{ "perr_isw_idma3_fifo", 15, 1 },
+		{ "perr_conm_sram", 14, 1 },
+		{ "perr_isw_idma2_fifo", 13, 1 },
+		{ "perr_isw_idma0_fifo", 12, 1 },
+		{ "perr_isw_idma1_fifo", 11, 1 },
+		{ "perr_isw_dbp_fifo", 10, 1 },
+		{ "perr_isw_gts_fifo", 9, 1 },
+		{ "perr_itp_evr", 8, 1 },
+		{ "perr_flm_cntxmem", 7, 1 },
+		{ "perr_flm_l1Cache", 6, 1 },
+		{ "sge_ipp_fifo_perr", 5, 1 },
+		{ "perr_dbp_hp_fifo", 4, 1 },
+		{ "perr_db_fifo", 3, 1 },
+		{ "perr_ing_ctxt_cache", 2, 1 },
+		{ "perr_egr_ctxt_cache", 1, 1 },
+		{ "perr_base_size", 0, 1 },
+	{ "SGE_PERR_ENABLE2", 0x1038, 0 },
+		{ "tf_fifo_perr", 24, 1 },
+		{ "perr_egr_dbp_tx_coal", 23, 1 },
+		{ "perr_dbp_fl_fifo", 22, 1 },
+		{ "deq_ll_perr", 21, 1 },
+		{ "enq_perr", 20, 1 },
+		{ "deq_out_perr", 19, 1 },
+		{ "buf_perr", 18, 1 },
+		{ "perr_isw_idma3_fifo", 15, 1 },
+		{ "perr_conm_sram", 14, 1 },
+		{ "perr_isw_idma2_fifo", 13, 1 },
+		{ "perr_isw_idma0_fifo", 12, 1 },
+		{ "perr_isw_idma1_fifo", 11, 1 },
+		{ "perr_isw_dbp_fifo", 10, 1 },
+		{ "perr_isw_gts_fifo", 9, 1 },
+		{ "perr_itp_evr", 8, 1 },
+		{ "perr_flm_cntxmem", 7, 1 },
+		{ "perr_flm_l1Cache", 6, 1 },
+		{ "sge_ipp_fifo_perr", 5, 1 },
+		{ "perr_dbp_hp_fifo", 4, 1 },
+		{ "perr_dbp_lp_fifo", 3, 1 },
+		{ "perr_ing_ctxt_cache", 2, 1 },
+		{ "perr_egr_ctxt_cache", 1, 1 },
+		{ "perr_base_size", 0, 1 },
+	{ "SGE_INT_CAUSE3", 0x103c, 0 },
+		{ "err_flm_dbp", 31, 1 },
+		{ "err_flm_idma1", 30, 1 },
+		{ "err_flm_idma0", 29, 1 },
+		{ "err_flm_hint", 28, 1 },
+		{ "err_pcie_error3", 27, 1 },
+		{ "err_pcie_error2", 26, 1 },
+		{ "err_pcie_error1", 25, 1 },
+		{ "err_pcie_error0", 24, 1 },
+		{ "err_timer_above_max_qid", 23, 1 },
+		{ "err_cpl_exceed_iqe_size", 22, 1 },
+		{ "err_invalid_cidx_inc", 21, 1 },
+		{ "err_itp_time_paused", 20, 1 },
+		{ "err_cpl_opcode_0", 19, 1 },
+		{ "err_dropped_db", 18, 1 },
+		{ "err_data_cpl_on_high_qid1", 17, 1 },
+		{ "err_data_cpl_on_high_qid0", 16, 1 },
+		{ "err_bad_db_pidx3", 15, 1 },
+		{ "err_bad_db_pidx2", 14, 1 },
+		{ "err_bad_db_pidx1", 13, 1 },
+		{ "err_bad_db_pidx0", 12, 1 },
+		{ "err_ing_pcie_chan", 11, 1 },
+		{ "err_ing_ctxt_prio", 10, 1 },
+		{ "err_egr_ctxt_prio", 9, 1 },
+		{ "dbp_tbuf_full", 8, 1 },
+		{ "fatal_wre_len", 7, 1 },
+		{ "reg_address_err", 6, 1 },
+		{ "ingress_size_err", 5, 1 },
+		{ "egress_size_err", 4, 1 },
+		{ "err_inv_ctxt3", 3, 1 },
+		{ "err_inv_ctxt2", 2, 1 },
+		{ "err_inv_ctxt1", 1, 1 },
+		{ "err_inv_ctxt0", 0, 1 },
+	{ "SGE_INT_ENABLE3", 0x1040, 0 },
+		{ "err_flm_dbp", 31, 1 },
+		{ "err_flm_idma1", 30, 1 },
+		{ "err_flm_idma0", 29, 1 },
+		{ "err_flm_hint", 28, 1 },
+		{ "err_pcie_error3", 27, 1 },
+		{ "err_pcie_error2", 26, 1 },
+		{ "err_pcie_error1", 25, 1 },
+		{ "err_pcie_error0", 24, 1 },
+		{ "err_timer_above_max_qid", 23, 1 },
+		{ "err_cpl_exceed_iqe_size", 22, 1 },
+		{ "err_invalid_cidx_inc", 21, 1 },
+		{ "err_itp_time_paused", 20, 1 },
+		{ "err_cpl_opcode_0", 19, 1 },
+		{ "err_dropped_db", 18, 1 },
+		{ "err_data_cpl_on_high_qid1", 17, 1 },
+		{ "err_data_cpl_on_high_qid0", 16, 1 },
+		{ "err_bad_db_pidx3", 15, 1 },
+		{ "err_bad_db_pidx2", 14, 1 },
+		{ "err_bad_db_pidx1", 13, 1 },
+		{ "err_bad_db_pidx0", 12, 1 },
+		{ "err_ing_pcie_chan", 11, 1 },
+		{ "err_ing_ctxt_prio", 10, 1 },
+		{ "err_egr_ctxt_prio", 9, 1 },
+		{ "dbp_tbuf_full", 8, 1 },
+		{ "fatal_wre_len", 7, 1 },
+		{ "reg_address_err", 6, 1 },
+		{ "ingress_size_err", 5, 1 },
+		{ "egress_size_err", 4, 1 },
+		{ "err_inv_ctxt3", 3, 1 },
+		{ "err_inv_ctxt2", 2, 1 },
+		{ "err_inv_ctxt1", 1, 1 },
+		{ "err_inv_ctxt0", 0, 1 },
+	{ "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
+		{ "Size", 4, 20 },
+	{ "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
+		{ "BaseAddr", 3, 29 },
+	{ "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
+		{ "BaseAddr", 3, 29 },
+	{ "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
+		{ "BaseAddr", 3, 29 },
+	{ "SGE_FLM_CFG", 0x1090, 0 },
+		{ "OpMode", 26, 6 },
+		{ "NullPtr", 20, 4 },
+		{ "NullPtrEn", 19, 1 },
+		{ "NoHdr", 18, 1 },
+		{ "CachePtrCnt", 16, 2 },
+		{ "EDRAMPtrCnt", 14, 2 },
+		{ "HdrStartFLQ", 11, 3 },
+		{ "FetchThresh", 6, 5 },
+		{ "CreditCnt", 4, 2 },
+		{ "CreditCntPacking", 2, 2 },
+		{ "HdrStartFLQ4K", 1, 1 },
+		{ "NoEDRAM", 0, 1 },
+	{ "SGE_CONM_CTRL", 0x1094, 0 },
+		{ "EgrThresholdPacking", 16, 8 },
+		{ "EgrThreshold", 8, 8 },
+		{ "IngThreshold", 2, 6 },
+	{ "SGE_TIMESTAMP_LO", 0x1098, 0 },
+	{ "SGE_TIMESTAMP_HI", 0x109c, 0 },
+		{ "Opcode", 28, 2 },
+		{ "Value", 0, 28 },
+	{ "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
+		{ "Threshold_0", 24, 6 },
+		{ "Threshold_1", 16, 6 },
+		{ "Threshold_2", 8, 6 },
+		{ "Threshold_3", 0, 6 },
+	{ "SGE_DBFIFO_STATUS", 0x10a4, 0 },
+		{ "vfifo_cnt", 15, 17 },
+		{ "coal_ctl_fifo_cnt", 8, 6 },
+		{ "merge_fifo_cnt", 0, 6 },
+	{ "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
+		{ "HintDepthCtl", 27, 5 },
+		{ "NoCoalesce", 26, 1 },
+		{ "HP_Weight", 24, 2 },
+		{ "HP_Disable", 23, 1 },
+		{ "ForceUserDBtoLP", 22, 1 },
+		{ "ForceVFPF0DBtoLP", 21, 1 },
+		{ "ForceVFPF1DBtoLP", 20, 1 },
+		{ "ForceVFPF2DBtoLP", 19, 1 },
+		{ "ForceVFPF3DBtoLP", 18, 1 },
+		{ "ForceVFPF4DBtoLP", 17, 1 },
+		{ "ForceVFPF5DBtoLP", 16, 1 },
+		{ "ForceVFPF6DBtoLP", 15, 1 },
+		{ "ForceVFPF7DBtoLP", 14, 1 },
+		{ "Enable_Drop", 13, 1 },
+		{ "Drop_Timeout", 7, 6 },
+		{ "InvOnDBSync", 6, 1 },
+		{ "InvOnGTSSync", 5, 1 },
+		{ "db_dbg_en", 4, 1 },
+		{ "gts_dbg_timer_reg", 1, 3 },
+		{ "gts_dbg_en", 0, 1 },
+	{ "SGE_ITP_CONTROL", 0x10b4, 0 },
+		{ "TScale", 28, 4 },
+		{ "Critical_Time", 10, 15 },
+		{ "LL_Empty", 4, 6 },
+		{ "LL_Read_Wait_Disable", 0, 1 },
+	{ "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
+		{ "TimerValue0", 16, 16 },
+		{ "TimerValue1", 0, 16 },
+	{ "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
+		{ "TimerValue2", 16, 16 },
+		{ "TimerValue3", 0, 16 },
+	{ "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
+		{ "TimerValue4", 16, 16 },
+		{ "TimerValue5", 0, 16 },
+	{ "SGE_GK_CONTROL", 0x10c4, 0 },
+		{ "en_flm_fifth", 29, 1 },
+		{ "fl_prog_thresh", 20, 9 },
+		{ "coal_all_thread", 19, 1 },
+		{ "en_pshb", 18, 1 },
+		{ "en_db_fifth", 17, 1 },
+		{ "db_prog_thresh", 8, 9 },
+		{ "100ns_timer", 0, 8 },
+	{ "SGE_GK_CONTROL2", 0x10c8, 0 },
+		{ "dbq_timer_tick", 16, 16 },
+		{ "fl_merge_cnt_thresh", 8, 4 },
+		{ "merge_cnt_thresh", 0, 6 },
+	{ "SGE_DEBUG_INDEX", 0x10cc, 0 },
+	{ "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
+	{ "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
+	{ "SGE_REVISION", 0x10d8, 0 },
+	{ "SGE_INT_CAUSE4", 0x10dc, 0 },
+		{ "err_ishift_ur1", 31, 1 },
+		{ "err_ishift_ur0", 30, 1 },
+		{ "bar2_egress_len_or_addr_err", 29, 1 },
+		{ "err_cpl_exceed_max_iqe_size1", 28, 1 },
+		{ "err_cpl_exceed_max_iqe_size0", 27, 1 },
+		{ "err_wr_len_too_large3", 26, 1 },
+		{ "err_wr_len_too_large2", 25, 1 },
+		{ "err_wr_len_too_large1", 24, 1 },
+		{ "err_wr_len_too_large0", 23, 1 },
+		{ "err_large_minfetch_with_txcoal3", 22, 1 },
+		{ "err_large_minfetch_with_txcoal2", 21, 1 },
+		{ "err_large_minfetch_with_txcoal1", 20, 1 },
+		{ "err_large_minfetch_with_txcoal0", 19, 1 },
+		{ "coal_with_hp_disable_err", 18, 1 },
+		{ "bar2_egress_coal0_err", 17, 1 },
+		{ "bar2_egress_size_err", 16, 1 },
+		{ "flm_pc_rsp_err", 15, 1 },
+		{ "err_th3_max_fetch", 14, 1 },
+		{ "err_th2_max_fetch", 13, 1 },
+		{ "err_th1_max_fetch", 12, 1 },
+		{ "err_th0_max_fetch", 11, 1 },
+		{ "err_rx_cpl_packet_size1", 10, 1 },
+		{ "err_rx_cpl_packet_size0", 9, 1 },
+		{ "err_bad_upfl_inc_credit3", 8, 1 },
+		{ "err_bad_upfl_inc_credit2", 7, 1 },
+		{ "err_bad_upfl_inc_credit1", 6, 1 },
+		{ "err_bad_upfl_inc_credit0", 5, 1 },
+		{ "err_physaddr_len0_idma1", 4, 1 },
+		{ "err_physaddr_len0_idma0", 3, 1 },
+		{ "err_flm_invalid_pkt_drop1", 2, 1 },
+		{ "err_flm_invalid_pkt_drop0", 1, 1 },
+		{ "err_unexpected_timer", 0, 1 },
+	{ "SGE_INT_ENABLE4", 0x10e0, 0 },
+		{ "err_ishift_ur1", 31, 1 },
+		{ "err_ishift_ur0", 30, 1 },
+		{ "bar2_egress_len_or_addr_err", 29, 1 },
+		{ "err_cpl_exceed_max_iqe_size1", 28, 1 },
+		{ "err_cpl_exceed_max_iqe_size0", 27, 1 },
+		{ "err_wr_len_too_large3", 26, 1 },
+		{ "err_wr_len_too_large2", 25, 1 },
+		{ "err_wr_len_too_large1", 24, 1 },
+		{ "err_wr_len_too_large0", 23, 1 },
+		{ "err_large_minfetch_with_txcoal3", 22, 1 },
+		{ "err_large_minfetch_with_txcoal2", 21, 1 },
+		{ "err_large_minfetch_with_txcoal1", 20, 1 },
+		{ "err_large_minfetch_with_txcoal0", 19, 1 },
+		{ "coal_with_hp_disable_err", 18, 1 },
+		{ "bar2_egress_coal0_err", 17, 1 },
+		{ "bar2_egress_size_err", 16, 1 },
+		{ "flm_pc_rsp_err", 15, 1 },
+		{ "err_th3_max_fetch", 14, 1 },
+		{ "err_th2_max_fetch", 13, 1 },
+		{ "err_th1_max_fetch", 12, 1 },
+		{ "err_th0_max_fetch", 11, 1 },
+		{ "err_rx_cpl_packet_size1", 10, 1 },
+		{ "err_rx_cpl_packet_size0", 9, 1 },
+		{ "err_bad_upfl_inc_credit3", 8, 1 },
+		{ "err_bad_upfl_inc_credit2", 7, 1 },
+		{ "err_bad_upfl_inc_credit1", 6, 1 },
+		{ "err_bad_upfl_inc_credit0", 5, 1 },
+		{ "err_physaddr_len0_idma1", 4, 1 },
+		{ "err_physaddr_len0_idma0", 3, 1 },
+		{ "err_flm_invalid_pkt_drop1", 2, 1 },
+		{ "err_flm_invalid_pkt_drop0", 1, 1 },
+		{ "err_unexpected_timer", 0, 1 },
+	{ "SGE_STAT_TOTAL", 0x10e4, 0 },
+	{ "SGE_STAT_MATCH", 0x10e8, 0 },
+	{ "SGE_STAT_CFG", 0x10ec, 0 },
+		{ "StatSource", 9, 4 },
+		{ "ITPOpMode", 8, 1 },
+		{ "EgrCtxtOpMode", 6, 2 },
+		{ "IngCtxtOpMode", 4, 2 },
+		{ "StatMode", 0, 4 },
+	{ "SGE_HINT_CFG", 0x10f0, 0 },
+		{ "uPCutoffThreshLp", 12, 11 },
+		{ "HintsAllowedNoHdr", 6, 6 },
+		{ "HintsAllowedHdr", 0, 6 },
+	{ "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
+		{ "QueuesPerPagePF7", 28, 4 },
+		{ "QueuesPerPagePF6", 24, 4 },
+		{ "QueuesPerPagePF5", 20, 4 },
+		{ "QueuesPerPagePF4", 16, 4 },
+		{ "QueuesPerPagePF3", 12, 4 },
+		{ "QueuesPerPagePF2", 8, 4 },
+		{ "QueuesPerPagePF1", 4, 4 },
+		{ "QueuesPerPagePF0", 0, 4 },
+	{ "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
+		{ "QueuesPerPageVFPF7", 28, 4 },
+		{ "QueuesPerPageVFPF6", 24, 4 },
+		{ "QueuesPerPageVFPF5", 20, 4 },
+		{ "QueuesPerPageVFPF4", 16, 4 },
+		{ "QueuesPerPageVFPF3", 12, 4 },
+		{ "QueuesPerPageVFPF2", 8, 4 },
+		{ "QueuesPerPageVFPF1", 4, 4 },
+		{ "QueuesPerPageVFPF0", 0, 4 },
+	{ "SGE_ERROR_STATS", 0x1100, 0 },
+		{ "Cause_Register", 24, 3 },
+		{ "Cause_Bit", 19, 5 },
+		{ "Uncaptured_Error", 18, 1 },
+		{ "Error_QID_Valid", 17, 1 },
+		{ "Error_QID", 0, 17 },
+	{ "SGE_IDMA0_DROP_CNT", 0x1104, 0 },
+	{ "SGE_IDMA1_DROP_CNT", 0x1108, 0 },
+	{ "SGE_INT_CAUSE5", 0x110c, 0 },
+		{ "err_T_RxCRC", 31, 1 },
+		{ "perr_MC_RspData", 30, 1 },
+		{ "perr_PC_RspData", 29, 1 },
+		{ "perr_PD_RdRspData", 28, 1 },
+		{ "perr_U_RxData", 27, 1 },
+		{ "perr_UD_RxData", 26, 1 },
+		{ "perr_uP_Data", 25, 1 },
+		{ "perr_CIM2SGE_RxData", 24, 1 },
+		{ "perr_imsg_pd_fifo", 21, 1 },
+		{ "perr_ulptx_fifo1", 20, 1 },
+		{ "perr_ulptx_fifo0", 19, 1 },
+		{ "perr_idma2imsg_fifo1", 18, 1 },
+		{ "perr_idma2imsg_fifo0", 17, 1 },
+		{ "perr_pointer_data_fifo0", 16, 1 },
+		{ "perr_pointer_data_fifo1", 15, 1 },
+		{ "perr_pointer_hdr_fifo0", 14, 1 },
+		{ "perr_pointer_hdr_fifo1", 13, 1 },
+		{ "perr_payload_fifo0", 12, 1 },
+		{ "perr_payload_fifo1", 11, 1 },
+		{ "perr_pointer_hdr_fifo3", 10, 1 },
+		{ "perr_pointer_hdr_fifo2", 9, 1 },
+		{ "perr_pointer_data_fifo3", 8, 1 },
+		{ "perr_pointer_data_fifo2", 7, 1 },
+		{ "perr_mgt_bar2_fifo", 6, 1 },
+		{ "perr_headersplit_fifo1", 5, 1 },
+		{ "perr_headersplit_fifo0", 4, 1 },
+		{ "perr_idma2imsg_fifo3", 3, 1 },
+		{ "perr_idma2imsg_fifo2", 2, 1 },
+		{ "perr_hint_delay_fifo", 0, 1 },
+	{ "SGE_INT_ENABLE5", 0x1110, 0 },
+		{ "err_T_RxCRC", 31, 1 },
+		{ "perr_MC_RspData", 30, 1 },
+		{ "perr_PC_RspData", 29, 1 },
+		{ "perr_PD_RdRspData", 28, 1 },
+		{ "perr_U_RxData", 27, 1 },
+		{ "perr_UD_RxData", 26, 1 },
+		{ "perr_uP_Data", 25, 1 },
+		{ "perr_CIM2SGE_RxData", 24, 1 },
+		{ "perr_imsg_pd_fifo", 21, 1 },
+		{ "perr_ulptx_fifo1", 20, 1 },
+		{ "perr_ulptx_fifo0", 19, 1 },
+		{ "perr_idma2imsg_fifo1", 18, 1 },
+		{ "perr_idma2imsg_fifo0", 17, 1 },
+		{ "perr_pointer_data_fifo0", 16, 1 },
+		{ "perr_pointer_data_fifo1", 15, 1 },
+		{ "perr_pointer_hdr_fifo0", 14, 1 },
+		{ "perr_pointer_hdr_fifo1", 13, 1 },
+		{ "perr_payload_fifo0", 12, 1 },
+		{ "perr_payload_fifo1", 11, 1 },
+		{ "perr_pointer_hdr_fifo3", 10, 1 },
+		{ "perr_pointer_hdr_fifo2", 9, 1 },
+		{ "perr_pointer_data_fifo3", 8, 1 },
+		{ "perr_pointer_data_fifo2", 7, 1 },
+		{ "perr_mgt_bar2_fifo", 6, 1 },
+		{ "perr_headersplit_fifo1", 5, 1 },
+		{ "perr_headersplit_fifo0", 4, 1 },
+		{ "perr_idma2imsg_fifo3", 3, 1 },
+		{ "perr_idma2imsg_fifo2", 2, 1 },
+		{ "perr_hint_delay_fifo", 0, 1 },
+	{ "SGE_PERR_ENABLE5", 0x1114, 0 },
+		{ "err_T_RxCRC", 31, 1 },
+		{ "perr_MC_RspData", 30, 1 },
+		{ "perr_PC_RspData", 29, 1 },
+		{ "perr_PD_RdRspData", 28, 1 },
+		{ "perr_U_RxData", 27, 1 },
+		{ "perr_UD_RxData", 26, 1 },
+		{ "perr_uP_Data", 25, 1 },
+		{ "perr_CIM2SGE_RxData", 24, 1 },
+		{ "perr_imsg_pd_fifo", 21, 1 },
+		{ "perr_ulptx_fifo1", 20, 1 },
+		{ "perr_ulptx_fifo0", 19, 1 },
+		{ "perr_idma2imsg_fifo1", 18, 1 },
+		{ "perr_idma2imsg_fifo0", 17, 1 },
+		{ "perr_pointer_data_fifo0", 16, 1 },
+		{ "perr_pointer_data_fifo1", 15, 1 },
+		{ "perr_pointer_hdr_fifo0", 14, 1 },
+		{ "perr_pointer_hdr_fifo1", 13, 1 },
+		{ "perr_payload_fifo0", 12, 1 },
+		{ "perr_payload_fifo1", 11, 1 },
+		{ "perr_pointer_hdr_fifo3", 10, 1 },
+		{ "perr_pointer_hdr_fifo2", 9, 1 },
+		{ "perr_pointer_data_fifo3", 8, 1 },
+		{ "perr_pointer_data_fifo2", 7, 1 },
+		{ "perr_mgt_bar2_fifo", 6, 1 },
+		{ "perr_headersplit_fifo1", 5, 1 },
+		{ "perr_headersplit_fifo0", 4, 1 },
+		{ "perr_idma2imsg_fifo3", 3, 1 },
+		{ "perr_idma2imsg_fifo2", 2, 1 },
+		{ "perr_hint_delay_fifo", 0, 1 },
+	{ "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 },
+		{ "FetchBurstMax0", 16, 10 },
+		{ "FetchBurstMax1", 0, 10 },
+	{ "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 },
+		{ "FetchBurstMax2", 16, 10 },
+		{ "FetchBurstMax3", 0, 10 },
+	{ "SGE_CONTROL2", 0x1124, 0 },
+		{ "hint_sge_sel", 31, 1 },
+		{ "hint_sel", 30, 1 },
+		{ "hint_disable", 29, 1 },
+		{ "rxcplmode_iscsi", 28, 1 },
+		{ "rxcplmode_nvmt", 27, 1 },
+		{ "wre_replay_inorder", 26, 1 },
+		{ "Eth2xEn", 25, 1 },
+		{ "ArmDbEndDis", 24, 1 },
+		{ "PackPadT7", 23, 1 },
+		{ "wre_upFLCredit", 22, 1 },
+		{ "uPFLCutoffDis", 21, 1 },
+		{ "RxCplSizeAutocorrect", 20, 1 },
+		{ "IdmaArbRoundRobin", 19, 1 },
+		{ "IngPackBoundary", 16, 3 },
+		{ "CGEN_Egress_Context", 15, 1 },
+		{ "CGEN_Ingress_Context", 14, 1 },
+		{ "CGEN_IDMA", 13, 1 },
+		{ "CGEN_DBP", 12, 1 },
+		{ "CGEN_EDMA", 11, 1 },
+		{ "VFIFO_Enable", 10, 1 },
+		{ "FLM_Reschedule_Mode", 9, 1 },
+		{ "HintDepthCtlFL", 4, 5 },
+		{ "Force_Ordering", 3, 1 },
+		{ "TX_Coalesce_Size", 2, 1 },
+		{ "Coal_Strict_CIM_Pri", 1, 1 },
+		{ "TX_Coalesce_Pri", 0, 1 },
+	{ "SGE_INT_CAUSE6", 0x1128, 0 },
+		{ "fatal_deq0_drdy", 29, 3 },
+		{ "fatal_out0_drdy", 26, 3 },
+		{ "imsg_dbg3_stuck", 25, 1 },
+		{ "imsg_dbg2_stuck", 24, 1 },
+		{ "imsg_dbg1_stuck", 23, 1 },
+		{ "imsg_dbg0_stuck", 22, 1 },
+		{ "err_db_sync", 21, 1 },
+		{ "err_gts_sync", 20, 1 },
+		{ "fatal_large_coal", 19, 1 },
+		{ "pl_bar2_frm_err", 18, 1 },
+		{ "silent_drop_tx_coal", 17, 1 },
+		{ "err_inv_ctxt4", 16, 1 },
+		{ "err_bad_db_pidx4", 15, 1 },
+		{ "err_bad_upfl_inc_credit4", 14, 1 },
+		{ "fatal_tag_mismatch", 13, 1 },
+		{ "fatal_enq_ctl_rdy", 12, 1 },
+		{ "err_pc_rsp_len3", 11, 1 },
+		{ "err_pc_rsp_len2", 10, 1 },
+		{ "err_pc_rsp_len1", 9, 1 },
+		{ "err_pc_rsp_len0", 8, 1 },
+		{ "fatal_enq2ll_vld", 7, 1 },
+		{ "fatal_ll_empty", 6, 1 },
+		{ "fatal_off_wdenq", 5, 1 },
+		{ "fatal_deq1_drdy", 3, 2 },
+		{ "fatal_out1_drdy", 1, 2 },
+		{ "fatal_deq", 0, 1 },
+	{ "SGE_INT_ENABLE6", 0x112c, 0 },
+		{ "imsg_dbg3_stuck", 25, 1 },
+		{ "imsg_dbg2_stuck", 24, 1 },
+		{ "imsg_dbg1_stuck", 23, 1 },
+		{ "imsg_dbg0_stuck", 22, 1 },
+		{ "err_db_sync", 21, 1 },
+		{ "err_gts_sync", 20, 1 },
+		{ "fatal_large_coal", 19, 1 },
+		{ "pl_bar2_frm_err", 18, 1 },
+		{ "silent_drop_tx_coal", 17, 1 },
+		{ "err_inv_ctxt4", 16, 1 },
+		{ "err_bad_db_pidx4", 15, 1 },
+		{ "err_bad_upfl_inc_credit4", 14, 1 },
+		{ "fatal_tag_mismatch", 13, 1 },
+		{ "fatal_enq_ctl_rdy", 12, 1 },
+		{ "err_pc_rsp_len3", 11, 1 },
+		{ "err_pc_rsp_len2", 10, 1 },
+		{ "err_pc_rsp_len1", 9, 1 },
+		{ "err_pc_rsp_len0", 8, 1 },
+		{ "fatal_enq2ll_vld", 7, 1 },
+		{ "fatal_ll_empty", 6, 1 },
+		{ "fatal_off_wdenq", 5, 1 },
+		{ "fatal_deq_drdy", 3, 2 },
+		{ "fatal_outp_drdy", 1, 2 },
+		{ "fatal_deq", 0, 1 },
+	{ "SGE_DBVFIFO_BADDR", 0x1138, 0 },
+		{ "BaseAddr", 3, 29 },
+	{ "SGE_DBVFIFO_SIZE", 0x113c, 0 },
+	{ "SGE_CHANGESET", 0x1144, 0 },
+	{ "SGE_PC_RSP_ERROR", 0x1148, 0 },
+	{ "SGE_TBUF_CONTROL0", 0x114c, 0 },
+		{ "DbpTbufRsv1", 9, 9 },
+		{ "DbpTbufRsv0", 0, 9 },
+	{ "SGE_TBUF_CONTROL1", 0x1150, 0 },
+		{ "DbpTbufRsv3", 9, 9 },
+		{ "DbpTbufRsv2", 0, 9 },
+	{ "SGE_TBUF_CONTROL2", 0x1154, 0 },
+		{ "DbpTbufRsv5", 9, 9 },
+		{ "DbpTbufRsv4", 0, 9 },
+	{ "SGE_TBUF_CONTROL3", 0x1158, 0 },
+		{ "DbpTbufRsv7", 9, 9 },
+		{ "DbpTbufRsv6", 0, 9 },
+	{ "SGE_TBUF_CONTROL4", 0x115c, 0 },
+		{ "DbpTbufRsv9", 9, 9 },
+		{ "DbpTbufRsv8", 0, 9 },
+	{ "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
+	{ "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
+	{ "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
+	{ "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
+	{ "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
+	{ "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
+	{ "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
+	{ "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
+	{ "SGE_DBQ_TIMER_THRESH0", 0x11b8, 0 },
+		{ "TxTimeTh3", 24, 6 },
+		{ "TxTimeTh2", 16, 6 },
+		{ "TxTimeTh1", 8, 6 },
+		{ "TxTimeTh0", 0, 6 },
+	{ "SGE_DBQ_TIMER_THRESH1", 0x11bc, 0 },
+		{ "TxTimeTh7", 24, 6 },
+		{ "TxTimeTh6", 16, 6 },
+		{ "TxTimeTh5", 8, 6 },
+		{ "TxTimeTh4", 0, 6 },
+	{ "SGE_DBQ_TIMER_CONFIG", 0x11c0, 0 },
+	{ "SGE_DBQ_TIMER_DBG", 0x11c4, 0 },
+		{ "dbq_timer_cmd", 31, 1 },
+		{ "dbq_timer_index", 24, 6 },
+		{ "dbq_timer_qcnt", 0, 17 },
+	{ "SGE_INT_CAUSE8", 0x11c8, 0 },
+		{ "Trace_RxPerr", 8, 1 },
+		{ "U3_RxPerr", 7, 1 },
+		{ "U2_RxPerr", 6, 1 },
+		{ "U1_RxPerr", 5, 1 },
+		{ "U0_RxPerr", 4, 1 },
+		{ "T3_RxPerr", 3, 1 },
+		{ "T2_RxPerr", 2, 1 },
+		{ "T1_RxPerr", 1, 1 },
+		{ "T0_RxPerr", 0, 1 },
+	{ "SGE_INT_ENABLE8", 0x11cc, 0 },
+		{ "Trace_RxPerr", 8, 1 },
+		{ "U3_RxPerr", 7, 1 },
+		{ "U2_RxPerr", 6, 1 },
+		{ "U1_RxPerr", 5, 1 },
+		{ "U0_RxPerr", 4, 1 },
+		{ "T3_RxPerr", 3, 1 },
+		{ "T2_RxPerr", 2, 1 },
+		{ "T1_RxPerr", 1, 1 },
+		{ "T0_RxPerr", 0, 1 },
+	{ "SGE_PERR_ENABLE8", 0x11d0, 0 },
+		{ "Trace_RxPerr", 8, 1 },
+		{ "U3_RxPerr", 7, 1 },
+		{ "U2_RxPerr", 6, 1 },
+		{ "U1_RxPerr", 5, 1 },
+		{ "U0_RxPerr", 4, 1 },
+		{ "T3_RxPerr", 3, 1 },
+		{ "T2_RxPerr", 2, 1 },
+		{ "T1_RxPerr", 1, 1 },
+		{ "T0_RxPerr", 0, 1 },
+	{ "SGE_CTXT_CMD", 0x11fc, 0 },
+		{ "Busy", 31, 1 },
+		{ "Opcode", 28, 2 },
+		{ "CtxtType", 24, 2 },
+		{ "QID", 0, 17 },
+	{ "SGE_CTXT_DATA0", 0x1200, 0 },
+	{ "SGE_CTXT_DATA1", 0x1204, 0 },
+	{ "SGE_CTXT_DATA2", 0x1208, 0 },
+	{ "SGE_CTXT_DATA3", 0x120c, 0 },
+	{ "SGE_CTXT_DATA4", 0x1210, 0 },
+	{ "SGE_CTXT_DATA5", 0x1214, 0 },
+	{ "SGE_CTXT_DATA6", 0x1218, 0 },
+		{ "Data_Unused", 7, 25 },
+		{ "Data", 0, 7 },
+	{ "SGE_CTXT_DATA7", 0x121c, 0 },
+	{ "SGE_CTXT_MASK0", 0x1220, 0 },
+	{ "SGE_CTXT_MASK1", 0x1224, 0 },
+	{ "SGE_CTXT_MASK2", 0x1228, 0 },
+	{ "SGE_CTXT_MASK3", 0x122c, 0 },
+	{ "SGE_CTXT_MASK4", 0x1230, 0 },
+	{ "SGE_CTXT_MASK5", 0x1234, 0 },
+	{ "SGE_CTXT_MASK6", 0x1238, 0 },
+		{ "Mask_Unused", 7, 25 },
+		{ "Mask", 0, 7 },
+	{ "SGE_CTXT_MASK7", 0x123c, 0 },
+	{ "SGE_QBASE_MAP0", 0x1240, 0 },
+		{ "Destination", 31, 1 },
+		{ "Egress0_Size", 24, 5 },
+		{ "Egress1_Size", 16, 5 },
+		{ "Ingress0_Size", 8, 5 },
+		{ "Ingress1_Size", 0, 5 },
+	{ "SGE_QBASE_MAP1", 0x1244, 0 },
+	{ "SGE_QBASE_MAP2", 0x1248, 0 },
+	{ "SGE_QBASE_MAP3", 0x124c, 0 },
+		{ "Ingress1_Base", 16, 16 },
+		{ "Ingress0_Base", 0, 16 },
+	{ "SGE_QBASE_INDEX", 0x1250, 0 },
+	{ "SGE_CONM_CTRL2", 0x1254, 0 },
+		{ "FlmThreshPack", 8, 7 },
+		{ "ConEnMiddle", 7, 1 },
+		{ "FlmThresh", 0, 7 },
+	{ "SGE_DEBUG_CONM", 0x1258, 0 },
+		{ "ch_cng", 16, 16 },
+		{ "ch_sel", 14, 2 },
+		{ "st_cong", 12, 2 },
+		{ "last_xoff", 10, 1 },
+		{ "last_qid", 0, 10 },
+	{ "SGE_DBG_QUEUE_STAT0_CTRL", 0x125c, 0 },
+		{ "imsg_gts_sel", 18, 1 },
+		{ "mgt_sel", 17, 1 },
+		{ "db_gts_qid", 0, 17 },
+	{ "SGE_DBG_QUEUE_STAT1_CTRL", 0x1260, 0 },
+		{ "imsg_gts_sel", 18, 1 },
+		{ "mgt_sel", 17, 1 },
+		{ "db_gts_qid", 0, 17 },
+	{ "SGE_DBG_QUEUE_STAT0", 0x1264, 0 },
+	{ "SGE_DBG_QUEUE_STAT1", 0x1268, 0 },
+	{ "SGE_DBG_BAR2_PKT_CNT", 0x126c, 0 },
+	{ "SGE_DBG_DB_PKT_CNT", 0x1270, 0 },
+	{ "SGE_DBG_GTS_PKT_CNT", 0x1274, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_16", 0x1278, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 },
+	{ "SGE_DEBUG1_DBP_THREAD", 0x128c, 0 },
+	{ "SGE_DEBUG1_DBP_THREAD", 0x1290, 0 },
+	{ "SGE_DEBUG1_DBP_THREAD", 0x1294, 0 },
+	{ "SGE_DEBUG1_DBP_THREAD", 0x1298, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 },
+	{ "SGE_DEBUG0_DBP_THREAD", 0x12d4, 0 },
+	{ "SGE_DEBUG0_DBP_THREAD", 0x12d8, 0 },
+	{ "SGE_DEBUG0_DBP_THREAD", 0x12dc, 0 },
+	{ "SGE_DEBUG0_DBP_THREAD", 0x12e0, 0 },
+	{ "SGE_DEBUG0_DBP_THREAD", 0x12e4, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc, 0 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1300, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1304, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1308, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x130c, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1310, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1314, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x1318, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_PF", 0x131c, 0 },
+		{ "PfIQsPerPage", 28, 4 },
+		{ "PfEQsPerPage", 24, 4 },
+		{ "PfWCQsPerPage", 20, 4 },
+		{ "PfWCOffEn", 19, 1 },
+		{ "PfMaxWCSize", 17, 2 },
+		{ "PfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1320, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1324, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1328, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x132c, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1330, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1334, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x1338, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_WC_EGRS_BAR2_OFF_VF", 0x133c, 0 },
+		{ "VfIQsPerPage", 28, 4 },
+		{ "VfEQsPerPage", 24, 4 },
+		{ "VfWCQsPerPage", 20, 4 },
+		{ "VfWCOffEn", 19, 1 },
+		{ "VfMaxWCSize", 17, 2 },
+		{ "VfWCOffset", 0, 17 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_17", 0x1340, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_18", 0x1344, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_19", 0x1348, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_20", 0x134c, 0 },
+	{ "SGE_DEBUG_DATA_HIGH_INDEX_21", 0x1350, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_16", 0x1354, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_17", 0x1358, 0 },
+	{ "SGE_DEBUG_DATA_LOW_INDEX_18", 0x135c, 0 },
+	{ "SGE_INT_CAUSE7", 0x1360, 0 },
+		{ "hint_fifo_full", 25, 1 },
+		{ "cerr_hint_delay_fifo", 24, 1 },
+		{ "coal_timer_fifo_perr", 23, 1 },
+		{ "cmp_fifo_perr", 22, 1 },
+		{ "sge_ipp_fifo_cerr", 21, 1 },
+		{ "cerr_ing_ctxt_cache", 20, 1 },
+		{ "imsg_cntx_perr", 19, 1 },
+		{ "pd_fifo_perr", 18, 1 },
+		{ "imsg_512_fifo_perr", 17, 1 },
+		{ "cplsw_fifo_perr", 16, 1 },
+		{ "imsg_fifo_perr", 15, 1 },
+		{ "cerr_itp_evr", 14, 1 },
+		{ "cerr_conm_sram", 13, 1 },
+		{ "cerr_egr_ctxt_cache", 12, 1 },
+		{ "cerr_flm_cntxmem", 11, 1 },
+		{ "cerr_func_qbase", 10, 1 },
+		{ "imsg_cntx_cerr", 9, 1 },
+		{ "pd_fifo_cerr", 8, 1 },
+		{ "imsg_512_fifo_cerr", 7, 1 },
+		{ "cplsw_fifo_cerr", 6, 1 },
+		{ "imsg_fifo_cerr", 5, 1 },
+		{ "cerr_headersplit_fifo3", 4, 1 },
+		{ "cerr_headersplit_fifo2", 3, 1 },
+		{ "cerr_headersplit_fifo1", 2, 1 },
+		{ "cerr_headersplit_fifo0", 1, 1 },
+		{ "cerr_flm_l1Cache", 0, 1 },
+	{ "SGE_INT_ENABLE7", 0x1364, 0 },
+		{ "hint_fifo_full", 25, 1 },
+		{ "cerr_hint_delay_fifo", 24, 1 },
+		{ "coal_timer_fifo_perr", 23, 1 },
+		{ "cmp_fifo_perr", 22, 1 },
+		{ "sge_ipp_fifo_cerr", 21, 1 },
+		{ "cerr_ing_ctxt_cache", 20, 1 },
+		{ "imsg_cntx_perr", 19, 1 },
+		{ "pd_fifo_perr", 18, 1 },
+		{ "imsg_512_fifo_perr", 17, 1 },
+		{ "cplsw_fifo_perr", 16, 1 },
+		{ "imsg_fifo_perr", 15, 1 },
+		{ "cerr_itp_evr", 14, 1 },
+		{ "cerr_conm_sram", 13, 1 },
+		{ "cerr_egr_ctxt_cache", 12, 1 },
+		{ "cerr_flm_cntxmem", 11, 1 },
+		{ "cerr_func_qbase", 10, 1 },
+		{ "imsg_cntx_cerr", 9, 1 },
+		{ "pd_fifo_cerr", 8, 1 },
+		{ "imsg_512_fifo_cerr", 7, 1 },
+		{ "cplsw_fifo_cerr", 6, 1 },
+		{ "imsg_fifo_cerr", 5, 1 },
+		{ "cerr_headersplit_fifo3", 4, 1 },
+		{ "cerr_headersplit_fifo2", 3, 1 },
+		{ "cerr_headersplit_fifo1", 2, 1 },
+		{ "cerr_headersplit_fifo0", 1, 1 },
+		{ "cerr_flm_l1Cache", 0, 1 },
+	{ "SGE_PERR_ENABLE7", 0x1368, 0 },
+		{ "coal_timer_fifo_perr", 23, 1 },
+		{ "cmp_fifo_perr", 22, 1 },
+		{ "imsg_cntx_perr", 19, 1 },
+		{ "pd_fifo_perr", 18, 1 },
+		{ "imsg_512_fifo_perr", 17, 1 },
+		{ "cplsw_fifo_perr", 16, 1 },
+		{ "imsg_fifo_perr", 15, 1 },
+	{ "SGE_ING_COMP_COAL_CFG", 0x1700, 0 },
+		{ "use_ptp_timer", 27, 1 },
+		{ "imsg_set_oflow_all_entries_43060", 26, 1 },
+		{ "imsg_stuck_indirect_queue_42907", 25, 1 },
+		{ "comp_coal_pidx_incr", 24, 1 },
+		{ "comp_coal_timer_cnt", 16, 8 },
+		{ "comp_coal_cntr_th", 8, 8 },
+		{ "comp_coal_opcode", 0, 8 },
+	{ "SGE_ING_IMSG_DBG", 0x1704, 0 },
+		{ "stuck_ctr_th", 1, 8 },
+		{ "stuck_int_en", 0, 1 },
+	{ "SGE_ING_IMSG_RSP0_DBG", 0x1708, 0 },
+		{ "idma1_qid", 16, 16 },
+		{ "idma0_qid", 0, 16 },
+	{ "SGE_ING_IMSG_RSP1_DBG", 0x170c, 0 },
+		{ "idma3_qid", 16, 16 },
+		{ "idma2_qid", 0, 16 },
+	{ "SGE_LB_MODE", 0x1710, 0 },
+	{ "SGE_IMSG_QUESCENT", 0x1714, 0 },
+	{ "SGE_LA_CTRL", 0x1718, 0 },
+		{ "la_global_en", 8, 1 },
+		{ "ptp_timestamp_sel", 7, 1 },
+		{ "cim2sge_id_chk_vld", 6, 1 },
+		{ "cplsw_id_chk_vld", 5, 1 },
+		{ "flm_id_chk_vld", 4, 1 },
+		{ "iq_dbp_id_chk_vld", 3, 1 },
+		{ "up_obq_id_chk_vld", 2, 1 },
+		{ "cim_id_chk_vld", 1, 1 },
+		{ "dbp_id_chk_vld", 0, 1 },
+	{ "SGE_LA_CTRL_EQID_LOW", 0x171c, 0 },
+	{ "SGE_LA_CTRL_EQID_HIGH", 0x1720, 0 },
+	{ "SGE_LA_CTRL_IQID", 0x1724, 0 },
+		{ "iq_id_chk_high", 16, 16 },
+		{ "iq_id_chk_low", 0, 16 },
+	{ "SGE_LA_CTRL_TID_LOW", 0x1728, 0 },
+	{ "SGE_LA_CTRL_TID_HIGH", 0x172c, 0 },
+	{ "SGE_CFG_TP_ERR", 0x173c, 0 },
+		{ "tp_err_status_ch3", 30, 2 },
+		{ "tp_err_status_ch2", 28, 2 },
+		{ "tp_err_status_ch1", 26, 2 },
+		{ "tp_err_status_ch0", 24, 2 },
+		{ "cpl0_size", 16, 8 },
+		{ "cpl1_size", 8, 8 },
+		{ "size_latch_clr", 3, 1 },
+		{ "ext_latch_clr", 2, 1 },
+		{ "ext_change_42875", 1, 1 },
+		{ "size_change_42913", 0, 1 },
+	{ "SGE_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x1740, 0 },
+	{ "SGE_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1744, 0 },
+	{ "SGE_CHNL2_CTX_ERROR_COUNT_PER_TID", 0x1748, 0 },
+	{ "SGE_CHNL3_CTX_ERROR_COUNT_PER_TID", 0x174c, 0 },
+	{ "SGE_CTX_ACC_CH0", 0x1750, 0 },
+		{ "RDMA_INV_Handling", 24, 2 },
+		{ "terminate_status_en", 23, 1 },
+		{ "DISABLE", 22, 1 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "SGE_CTX_ACC_CH1", 0x1754, 0 },
+		{ "RDMA_INV_Handling", 24, 2 },
+		{ "terminate_status_en", 23, 1 },
+		{ "DISABLE", 22, 1 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "SGE_CTX_ACC_CH2", 0x1758, 0 },
+		{ "RDMA_INV_Handling", 24, 2 },
+		{ "terminate_status_en", 23, 1 },
+		{ "DISABLE", 22, 1 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "SGE_CTX_ACC_CH3", 0x175c, 0 },
+		{ "RDMA_INV_Handling", 24, 2 },
+		{ "terminate_status_en", 23, 1 },
+		{ "DISABLE", 22, 1 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "SGE_CTX_BASE", 0x1760, 0 },
+	{ "SGE_LA_RDPTR_0", 0x1800, 0 },
+	{ "SGE_LA_RDDATA_0", 0x1804, 0 },
+	{ "SGE_LA_WRPTR_0", 0x1808, 0 },
+	{ "SGE_LA_RESERVED_0", 0x180c, 0 },
+	{ "SGE_LA_RDPTR_1", 0x1810, 0 },
+	{ "SGE_LA_RDDATA_1", 0x1814, 0 },
+	{ "SGE_LA_WRPTR_1", 0x1818, 0 },
+	{ "SGE_LA_RESERVED_1", 0x181c, 0 },
+	{ "SGE_LA_RDPTR_2", 0x1820, 0 },
+	{ "SGE_LA_RDDATA_2", 0x1824, 0 },
+	{ "SGE_LA_WRPTR_2", 0x1828, 0 },
+	{ "SGE_LA_RESERVED_2", 0x182c, 0 },
+	{ "SGE_LA_RDPTR_3", 0x1830, 0 },
+	{ "SGE_LA_RDDATA_3", 0x1834, 0 },
+	{ "SGE_LA_WRPTR_3", 0x1838, 0 },
+	{ "SGE_LA_RESERVED_3", 0x183c, 0 },
+	{ "SGE_LA_RDPTR_4", 0x1840, 0 },
+	{ "SGE_LA_RDDATA_4", 0x1844, 0 },
+	{ "SGE_LA_WRPTR_4", 0x1848, 0 },
+	{ "SGE_LA_RESERVED_4", 0x184c, 0 },
+	{ "SGE_LA_RDPTR_5", 0x1850, 0 },
+	{ "SGE_LA_RDDATA_5", 0x1854, 0 },
+	{ "SGE_LA_WRPTR_5", 0x1858, 0 },
+	{ "SGE_LA_RESERVED_5", 0x185c, 0 },
+	{ "SGE_LA_RDPTR_6", 0x1860, 0 },
+	{ "SGE_LA_RDDATA_6", 0x1864, 0 },
+	{ "SGE_LA_WRPTR_6", 0x1868, 0 },
+	{ "SGE_LA_RESERVED_6", 0x186c, 0 },
+	{ "SGE_LA_RDPTR_7", 0x1870, 0 },
+	{ "SGE_LA_RDDATA_7", 0x1874, 0 },
+	{ "SGE_LA_WRPTR_7", 0x1878, 0 },
+	{ "SGE_LA_RESERVED_7", 0x187c, 0 },
+	{ "SGE_LA_RDPTR_8", 0x1880, 0 },
+	{ "SGE_LA_RDDATA_8", 0x1884, 0 },
+	{ "SGE_LA_WRPTR_8", 0x1888, 0 },
+	{ "SGE_LA_RESERVED_8", 0x188c, 0 },
+	{ "SGE_LA_RDPTR_9", 0x1890, 0 },
+	{ "SGE_LA_RDDATA_9", 0x1894, 0 },
+	{ "SGE_LA_WRPTR_9", 0x1898, 0 },
+	{ "SGE_LA_RESERVED_9", 0x189c, 0 },
+	{ "SGE_LA_RDPTR_10", 0x18a0, 0 },
+	{ "SGE_LA_RDDATA_10", 0x18a4, 0 },
+	{ "SGE_LA_WRPTR_10", 0x18a8, 0 },
+	{ "SGE_LA_RESERVED_10", 0x18ac, 0 },
+	{ "SGE_LA_RDPTR_11", 0x18b0, 0 },
+	{ "SGE_LA_RDDATA_11", 0x18b4, 0 },
+	{ "SGE_LA_WRPTR_11", 0x18b8, 0 },
+	{ "SGE_LA_RESERVED_11", 0x18bc, 0 },
+	{ "SGE_LA_RDPTR_12", 0x18c0, 0 },
+	{ "SGE_LA_RDDATA_12", 0x18c4, 0 },
+	{ "SGE_LA_WRPTR_12", 0x18c8, 0 },
+	{ "SGE_LA_RESERVED_12", 0x18cc, 0 },
+	{ "SGE_LA_RDPTR_13", 0x18d0, 0 },
+	{ "SGE_LA_RDDATA_13", 0x18d4, 0 },
+	{ "SGE_LA_WRPTR_13", 0x18d8, 0 },
+	{ "SGE_LA_RESERVED_13", 0x18dc, 0 },
+	{ "SGE_LA_RDPTR_14", 0x18e0, 0 },
+	{ "SGE_LA_RDDATA_14", 0x18e4, 0 },
+	{ "SGE_LA_WRPTR_14", 0x18e8, 0 },
+	{ "SGE_LA_RESERVED_14", 0x18ec, 0 },
+	{ "SGE_LA_RDPTR_15", 0x18f0, 0 },
+	{ "SGE_LA_RDDATA_15", 0x18f4, 0 },
+	{ "SGE_LA_WRPTR_15", 0x18f8, 0 },
+	{ "SGE_LA_RESERVED_15", 0x18fc, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_pcie_regs[] = {
+	{ "PCIE_INT_ENABLE", 0x3000, 0 },
+		{ "IPGrpPerr", 31, 1 },
+		{ "NonFatalErr", 30, 1 },
+		{ "RdRspErr", 29, 1 },
+		{ "TRGT1GrpPerr", 28, 1 },
+		{ "IPSOTPerr", 27, 1 },
+		{ "IPRetryPerr", 26, 1 },
+		{ "IPRxDataGrpPerr", 25, 1 },
+		{ "IPRxHdrGrpPerr", 24, 1 },
+		{ "PIOTagQPerr", 23, 1 },
+		{ "MAGrpPerr", 22, 1 },
+		{ "VFIDPerr", 21, 1 },
+		{ "FIDPerr", 20, 1 },
+		{ "CfgSnpPerr", 19, 1 },
+		{ "HRspPerr", 18, 1 },
+		{ "HReqRdPerr", 17, 1 },
+		{ "HReqWrPerr", 16, 1 },
+		{ "DRspPerr", 15, 1 },
+		{ "DReqRdPerr", 14, 1 },
+		{ "DReqWrPerr", 13, 1 },
+		{ "CRspPerr", 12, 1 },
+		{ "CReqRdPerr", 11, 1 },
+		{ "MstTagQPerr", 10, 1 },
+		{ "TgtTagQPerr", 9, 1 },
+		{ "PIOReqGrpPerr", 8, 1 },
+		{ "PIOCplGrpPerr", 7, 1 },
+		{ "MSIXDIPerr", 6, 1 },
+		{ "MSIXDataPerr", 5, 1 },
+		{ "MSIXAddrHPerr", 4, 1 },
+		{ "MSIXAddrLPerr", 3, 1 },
+		{ "MSIXStiPerr", 2, 1 },
+		{ "MstTimeoutPerr", 1, 1 },
+		{ "MstGrpPerr", 0, 1 },
+	{ "PCIE_INT_ENABLE_EXT", 0x3030, 0 },
+		{ "TcamRspErr", 31, 1 },
+		{ "IPFormQPerr", 30, 1 },
+		{ "IPFormQCerr", 29, 1 },
+		{ "TRGT1GrpCerr", 28, 1 },
+		{ "IPSOTCerr", 27, 1 },
+		{ "IPRetryCerr", 26, 1 },
+		{ "IPRxDataGrpCerr", 25, 1 },
+		{ "IPRxHdrGrpCerr", 24, 1 },
+		{ "A0arbrspordfifoPerr", 19, 1 },
+		{ "HRspCerr", 18, 1 },
+		{ "HReqRdCerr", 17, 1 },
+		{ "HReqWrCerr", 16, 1 },
+		{ "DRspCerr", 15, 1 },
+		{ "DReqRdCerr", 14, 1 },
+		{ "DReqWrCerr", 13, 1 },
+		{ "CRspCerr", 12, 1 },
+		{ "ARspPerr", 11, 1 },
+		{ "AReqRdPerr", 10, 1 },
+		{ "AReqWrPerr", 9, 1 },
+		{ "PIOReqGrpCerr", 8, 1 },
+		{ "ARspCerr", 7, 1 },
+		{ "AReqRdCerr", 6, 1 },
+		{ "AReqWrCerr", 5, 1 },
+		{ "MARspPerr", 4, 1 },
+		{ "inicmawdataordPerr", 3, 1 },
+		{ "emuPerr", 2, 1 },
+		{ "ERRspPerr", 1, 1 },
+		{ "MstGrpCerr", 0, 1 },
+	{ "PCIE_INT_ENABLE_X8", 0x3034, 0 },
+		{ "x8TGTGrpPerr", 23, 1 },
+		{ "x8IPSOTPerr", 22, 1 },
+		{ "x8IPRetryPerr", 21, 1 },
+		{ "x8IPRxDataGrpPerr", 20, 1 },
+		{ "x8IPRxHdrGrpPerr", 19, 1 },
+		{ "x8IPCoreCerr", 3, 1 },
+		{ "x8MstGrpPerr", 2, 1 },
+		{ "x8MstGrpCerr", 1, 1 },
+	{ "PCIE_INT_CAUSE", 0x3004, 0 },
+		{ "IPGrpPerr", 31, 1 },
+		{ "NonFatalErr", 30, 1 },
+		{ "RdRspErr", 29, 1 },
+		{ "TRGT1GrpPerr", 28, 1 },
+		{ "IPSOTPerr", 27, 1 },
+		{ "IPRetryPerr", 26, 1 },
+		{ "IPRxDataGrpPerr", 25, 1 },
+		{ "IPRxHdrGrpPerr", 24, 1 },
+		{ "PIOTagQPerr", 23, 1 },
+		{ "MAGrpPerr", 22, 1 },
+		{ "VFIDPerr", 21, 1 },
+		{ "FIDPerr", 20, 1 },
+		{ "CfgSnpPerr", 19, 1 },
+		{ "HRspPerr", 18, 1 },
+		{ "HReqRdPerr", 17, 1 },
+		{ "HReqWrPerr", 16, 1 },
+		{ "DRspPerr", 15, 1 },
+		{ "DReqRdPerr", 14, 1 },
+		{ "DReqWrPerr", 13, 1 },
+		{ "CRspPerr", 12, 1 },
+		{ "CReqRdPerr", 11, 1 },
+		{ "MstTagQPerr", 10, 1 },
+		{ "TgtTagQPerr", 9, 1 },
+		{ "PIOReqGrpPerr", 8, 1 },
+		{ "PIOCplGrpPerr", 7, 1 },
+		{ "MSIXDIPerr", 6, 1 },
+		{ "MSIXDataPerr", 5, 1 },
+		{ "MSIXAddrHPerr", 4, 1 },
+		{ "MSIXAddrLPerr", 3, 1 },
+		{ "MSIXStiPerr", 2, 1 },
+		{ "MstTimeoutPerr", 1, 1 },
+		{ "MstGrpPerr", 0, 1 },
+	{ "PCIE_INT_CAUSE_EXT", 0x3038, 0 },
+		{ "IPFormQPerr", 30, 1 },
+		{ "IPFormQCerr", 29, 1 },
+		{ "TRGT1GrpCerr", 28, 1 },
+		{ "IPSOTCerr", 27, 1 },
+		{ "IPRetryCerr", 26, 1 },
+		{ "IPRxDataGrpCerr", 25, 1 },
+		{ "IPRxHdrGrpCerr", 24, 1 },
+		{ "A0arbrspordfifoPerr", 19, 1 },
+		{ "HRspCerr", 18, 1 },
+		{ "HReqRdCerr", 17, 1 },
+		{ "HReqWrCerr", 16, 1 },
+		{ "DRspCerr", 15, 1 },
+		{ "DReqRdCerr", 14, 1 },
+		{ "DReqWrCerr", 13, 1 },
+		{ "CRspCerr", 12, 1 },
+		{ "ARspPerr", 11, 1 },
+		{ "AReqRdPerr", 10, 1 },
+		{ "AReqWrPerr", 9, 1 },
+		{ "PIOReqGrpCerr", 8, 1 },
+		{ "ARspCerr", 7, 1 },
+		{ "AReqRdCerr", 6, 1 },
+		{ "AReqWrCerr", 5, 1 },
+		{ "MARspPerr", 4, 1 },
+		{ "inicmawdataordPerr", 3, 1 },
+		{ "emuPerr", 2, 1 },
+		{ "ERRspPerr", 1, 1 },
+		{ "MstGrpCerr", 0, 1 },
+	{ "PCIE_INT_CAUSE_X8", 0x303c, 0 },
+		{ "x8TGTGrpPerr", 23, 1 },
+		{ "x8IPSOTPerr", 22, 1 },
+		{ "x8IPRetryPerr", 21, 1 },
+		{ "x8IPRxDataGrpPerr", 20, 1 },
+		{ "x8IPRxHdrGrpPerr", 19, 1 },
+		{ "x8IPCoreCerr", 3, 1 },
+		{ "x8MstGrpPerr", 2, 1 },
+		{ "x8MstGrpCerr", 1, 1 },
+	{ "PCIE_PERR_ENABLE", 0x3008, 0 },
+		{ "IPGrpPerr", 31, 1 },
+		{ "TgtTagQCLIENT1Perr", 29, 1 },
+		{ "TRGT1GrpPerr", 28, 1 },
+		{ "IPSOTPerr", 27, 1 },
+		{ "IPRetryPerr", 26, 1 },
+		{ "IPRxDataGrpPerr", 25, 1 },
+		{ "IPRxHdrGrpPerr", 24, 1 },
+		{ "PIOTagQPerr", 23, 1 },
+		{ "MAGrpPerr", 22, 1 },
+		{ "VFIDPerr", 21, 1 },
+		{ "FIDPerr", 20, 1 },
+		{ "CfgSnpPerr", 19, 1 },
+		{ "HRspPerr", 18, 1 },
+		{ "HReqRdPerr", 17, 1 },
+		{ "HReqWrPerr", 16, 1 },
+		{ "DRspPerr", 15, 1 },
+		{ "DReqRdPerr", 14, 1 },
+		{ "DReqWrPerr", 13, 1 },
+		{ "CRspPerr", 12, 1 },
+		{ "CReqRdPerr", 11, 1 },
+		{ "MstTagQPerr", 10, 1 },
+		{ "TgtTagQPerr", 9, 1 },
+		{ "PIOReqGrpPerr", 8, 1 },
+		{ "PIOCplGrpPerr", 7, 1 },
+		{ "MSIXDIPerr", 6, 1 },
+		{ "MSIXDataPerr", 5, 1 },
+		{ "MSIXAddrHPerr", 4, 1 },
+		{ "MSIXAddrLPerr", 3, 1 },
+		{ "MSIXStiPerr", 2, 1 },
+		{ "MstTimeoutPerr", 1, 1 },
+		{ "MstGrpPerr", 0, 1 },
+	{ "PCIE_PERR_ENABLE_EXT", 0x3040, 0 },
+		{ "TcamRspErr", 31, 1 },
+		{ "IPFormQPerr", 30, 1 },
+		{ "ARspPerr", 18, 1 },
+		{ "AReqRdPerr", 17, 1 },
+		{ "AReqWrPerr", 16, 1 },
+		{ "A0arbrspordfifoPerr", 15, 1 },
+		{ "MARspPerr", 14, 1 },
+		{ "inicmawdataordPerr", 13, 1 },
+		{ "emuPerr", 12, 1 },
+		{ "ERRspPerr", 11, 1 },
+	{ "PCIE_PERR_ENABLE_X8", 0x3044, 0 },
+		{ "x8TGTGrpPerr", 28, 1 },
+		{ "x8IPSOTPerr", 27, 1 },
+		{ "x8IPRetryPerr", 26, 1 },
+		{ "x8IPRxDataGrpPerr", 25, 1 },
+		{ "x8IPRxHdrGrpPerr", 24, 1 },
+		{ "x8MstGrpPerr", 0, 1 },
+	{ "PCIE_PERR_INJECT", 0x300c, 0 },
+		{ "MemSel", 1, 5 },
+		{ "IDE", 0, 1 },
+	{ "PCIE_NONFAT_ERR", 0x3010, 0 },
+		{ "MARspUE", 30, 1 },
+		{ "MAReqTimeout", 29, 1 },
+		{ "TRGT1BARTypeErr", 28, 1 },
+		{ "MAExtraRspErr", 27, 1 },
+		{ "MARspTimeout", 26, 1 },
+		{ "INTVFAllMSIDisErr", 25, 1 },
+		{ "INTVFRangeErr", 24, 1 },
+		{ "INTPLIRspErr", 23, 1 },
+		{ "MEMReqRdTagErr", 22, 1 },
+		{ "CFGInitDoneErr", 21, 1 },
+		{ "BAR2Timeout", 20, 1 },
+		{ "VPDTimeout", 19, 1 },
+		{ "MEMRspRdTagErr", 18, 1 },
+		{ "MEMRspWrTagErr", 17, 1 },
+		{ "PIORspRdTagErr", 16, 1 },
+		{ "PIORspWrTagErr", 15, 1 },
+		{ "DBITimeout", 14, 1 },
+		{ "PIOUnAlindWr", 13, 1 },
+		{ "BAR2RdErr", 12, 1 },
+		{ "MAWrEOPErr", 11, 1 },
+		{ "MARdEOPErr", 10, 1 },
+		{ "RdRspErr", 9, 1 },
+		{ "VPDRspErr", 8, 1 },
+		{ "KDBEOPErr", 7, 1 },
+		{ "MemReq", 4, 1 },
+		{ "PIOReq", 3, 1 },
+		{ "BAR2Req", 2, 1 },
+		{ "CfgSnp", 0, 1 },
+	{ "PCIE_CFG", 0x3014, 0 },
+		{ "PIOStopEn", 31, 1 },
+		{ "DiagCtrlBus", 28, 3 },
+		{ "IPPerrEn", 27, 1 },
+		{ "CfgdExtTagEn", 26, 1 },
+		{ "CfgdMaxPyldSz", 23, 3 },
+		{ "CfgdMaxRdReqSz", 20, 3 },
+		{ "DCAEn", 17, 1 },
+		{ "CMDReqPriority", 16, 1 },
+		{ "VPDReqProtect", 14, 2 },
+		{ "DroppedRdRspData", 12, 1 },
+		{ "AI_INTX_ReAssertEn", 11, 1 },
+		{ "AutoTxnDisable", 10, 1 },
+		{ "TC0_Stamp", 9, 1 },
+		{ "AI_TCVal", 6, 3 },
+		{ "DMAStopEn", 5, 1 },
+		{ "DevStateRstMode", 4, 1 },
+		{ "LinkReqRstPCIeCRstMode", 3, 1 },
+		{ "LinkDnRstEn", 0, 1 },
+	{ "PCIE_CFG2", 0x3018, 0 },
+		{ "reg_vdm_only", 17, 1 },
+		{ "Mult_ReqID_Sup", 16, 1 },
+		{ "BAR2Timer", 4, 12 },
+		{ "MstReqRdRRASimple", 3, 1 },
+		{ "TotMaxTag", 0, 3 },
+	{ "PCIE_CFG3", 0x301c, 0 },
+		{ "ARMDCASTFirstOnly", 7, 1 },
+		{ "AutoPIOCookieMatch", 6, 1 },
+		{ "FLRPndCplMode", 4, 2 },
+		{ "HMADCASTFirstOnly", 2, 1 },
+		{ "CMDDCASTFirstOnly", 1, 1 },
+		{ "DMADCASTFirstOnly", 0, 1 },
+	{ "PCIE_CFG4", 0x3020, 0 },
+		{ "L1ClkRemovalEn", 17, 1 },
+		{ "ReadyEnterL23", 16, 1 },
+		{ "ExitL1", 12, 1 },
+		{ "EnterL1", 8, 1 },
+		{ "GenPME", 0, 8 },
+	{ "PCIE_CFG5", 0x3024, 0 },
+		{ "EnableSKPParityFix", 2, 1 },
+		{ "EnableL2EntryInL1", 1, 1 },
+		{ "HoldCplEnteringL1", 0, 1 },
+	{ "PCIE_CFG6", 0x3028, 0 },
+		{ "PERstTimerCount", 12, 14 },
+		{ "PERstTimeout", 8, 1 },
+		{ "PERstTimer", 0, 4 },
+	{ "PCIE_CFG7", 0x302c, 0 },
+	{ "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
+		{ "Enable", 31, 1 },
+		{ "AI", 30, 1 },
+		{ "CS2", 29, 1 },
+		{ "WrBE", 25, 4 },
+		{ "VFVld", 24, 1 },
+		{ "RVF", 16, 8 },
+		{ "PF", 12, 3 },
+		{ "ExtRegister", 8, 4 },
+		{ "Register", 0, 8 },
+	{ "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
+	{ "PCIE_MAILBOX_BASE_WIN", 0x30a4, 0 },
+		{ "PCIEOfst", 6, 26 },
+		{ "BIR", 4, 2 },
+		{ "Window", 0, 2 },
+	{ "PCIE_MAILBOX_OFFSET0", 0x30a8, 0 },
+		{ "MemOfst0", 3, 29 },
+	{ "PCIE_MAILBOX_OFFSET1", 0x30ac, 0 },
+	{ "PCIE_MA_CTRL", 0x30b0, 0 },
+		{ "TagFree", 29, 1 },
+		{ "MaxRspCnt", 24, 5 },
+		{ "MaxReqCnt", 16, 7 },
+		{ "MaxReqSize", 8, 3 },
+		{ "MaxTag", 0, 5 },
+	{ "PCIE_FW", 0x30b8, 0 },
+	{ "PCIE_FW_PF", 0x30bc, 0 },
+	{ "PCIE_FW_PF", 0x30c0, 0 },
+	{ "PCIE_FW_PF", 0x30c4, 0 },
+	{ "PCIE_FW_PF", 0x30c8, 0 },
+	{ "PCIE_FW_PF", 0x30cc, 0 },
+	{ "PCIE_FW_PF", 0x30d0, 0 },
+	{ "PCIE_FW_PF", 0x30d4, 0 },
+	{ "PCIE_FW_PF", 0x30d8, 0 },
+	{ "PCIE_PIO_PAUSE", 0x30dc, 0 },
+		{ "PIOPauseDone", 31, 1 },
+		{ "MSTPauseDone", 30, 1 },
+		{ "PauseTime", 4, 24 },
+		{ "MSTPause", 1, 1 },
+		{ "PIOPause", 0, 1 },
+	{ "PCIE_MA_STAT", 0x30e0, 0 },
+	{ "PCIE_STATIC_CFG1", 0x30e4, 0 },
+		{ "AUXPOWER_DETECTED", 27, 1 },
+	{ "PCIE_STATIC_CFG2", 0x30e8, 0 },
+		{ "PL_CONTROL", 16, 16 },
+		{ "STATIC_SPARE3", 0, 15 },
+	{ "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
+		{ "Enable", 31, 1 },
+		{ "AI", 30, 1 },
+		{ "Pointer", 8, 16 },
+		{ "Select", 0, 4 },
+	{ "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
+	{ "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
+	{ "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
+	{ "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
+	{ "PCIE_PF_INT_CFG", 0x3140, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x3144, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3148, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x314c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3150, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x3154, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3158, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x315c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3160, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x3164, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3168, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x316c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3170, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x3174, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_INT_CFG", 0x3178, 0 },
+		{ "PBAOfst", 28, 4 },
+		{ "TABOfst", 24, 4 },
+		{ "VecNum", 12, 11 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_PF_INT_CFG2", 0x317c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3180, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3184, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3188, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x318c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3190, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3194, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3198, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x319c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31a0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31a4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31a8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31ac, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31b0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31b4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31b8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31bc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31c0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31c4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31c8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31cc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31d0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31d4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31d8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31dc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31e0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31e4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31e8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31ec, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31f0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31f4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x31f8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x31fc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3200, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3204, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3208, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x320c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3210, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3214, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3218, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x321c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3220, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3224, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3228, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x322c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3230, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3234, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3238, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x323c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3240, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3244, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3248, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x324c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3250, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3254, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3258, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x325c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3260, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3264, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3268, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x326c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3270, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3274, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3278, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x327c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3280, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3284, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3288, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x328c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3290, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3294, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3298, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x329c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32a0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32a4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32a8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32ac, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32b0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32b4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32b8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32bc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32c0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32c4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32c8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32cc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32d0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32d4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32d8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32dc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32e0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32e4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32e8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32ec, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32f0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32f4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x32f8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x32fc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3300, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3304, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3308, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x330c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3310, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3314, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3318, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x331c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3320, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3324, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3328, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x332c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3330, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3334, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3338, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x333c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3340, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3344, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3348, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x334c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3350, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3354, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3358, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x335c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3360, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3364, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3368, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x336c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3370, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3374, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3378, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x337c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3380, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3384, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3388, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x338c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3390, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3394, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3398, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x339c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33a0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33a4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33a8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33ac, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33b0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33b4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33b8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33bc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33c0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33c4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33c8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33cc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33d0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33d4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33d8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33dc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33e0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33e4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33e8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33ec, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33f0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33f4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x33f8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x33fc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3400, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3404, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3408, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x340c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3410, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3414, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3418, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x341c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3420, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3424, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3428, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x342c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3430, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3434, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3438, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x343c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3440, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3444, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3448, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x344c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3450, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3454, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3458, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x345c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3460, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3464, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3468, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x346c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3470, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3474, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3478, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x347c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3480, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3484, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3488, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x348c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3490, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3494, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3498, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x349c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34a0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34a4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34a8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34ac, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34b0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34b4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34b8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34bc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34c0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34c4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34c8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34cc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34d0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34d4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34d8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34dc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34e0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34e4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34e8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34ec, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34f0, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34f4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x34f8, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x34fc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3500, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3504, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3508, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x350c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3510, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3514, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3518, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x351c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3520, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3524, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3528, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x352c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3530, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3534, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3538, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x353c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3540, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3544, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3548, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x354c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3550, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3554, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3558, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x355c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3560, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3564, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3568, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x356c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3570, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x3574, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_INT_CFG", 0x3578, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 11 },
+	{ "PCIE_VF_INT_CFG2", 0x357c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_PF_MSI_EN", 0x35a8, 0 },
+	{ "PCIE_VF_MSI_EN_0", 0x35ac, 0 },
+	{ "PCIE_VF_MSI_EN_1", 0x35b0, 0 },
+	{ "PCIE_VF_MSI_EN_2", 0x35b4, 0 },
+	{ "PCIE_VF_MSI_EN_3", 0x35b8, 0 },
+	{ "PCIE_PF_MSIX_EN", 0x35bc, 0 },
+	{ "PCIE_VF_MSIX_EN_0", 0x35c0, 0 },
+	{ "PCIE_VF_MSIX_EN_1", 0x35c4, 0 },
+	{ "PCIE_VF_MSIX_EN_2", 0x35c8, 0 },
+	{ "PCIE_VF_MSIX_EN_3", 0x35cc, 0 },
+	{ "PCIE_FID_VFID_CTL", 0x35e4, 0 },
+	{ "PCIE_FID_PASID", 0x35e0, 0 },
+	{ "PCIE_FID_VFID_SEL", 0x35e8, 0 },
+		{ "Addr", 2, 13 },
+		{ "Select", 0, 2 },
+	{ "PCIE_FID_VFID", 0x35ec, 0 },
+		{ "Select", 30, 2 },
+		{ "NvmeGroupEn", 29, 1 },
+		{ "GroupSel", 25, 4 },
+		{ "IDO", 24, 1 },
+		{ "VFID", 15, 9 },
+		{ "TC", 12, 3 },
+		{ "VFVld", 11, 1 },
+		{ "PF", 8, 3 },
+		{ "RVF", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3700, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3704, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3708, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x370c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3710, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3714, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3718, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x371c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3720, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3724, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3728, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x372c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3730, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3734, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3738, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x373c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3740, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3744, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3748, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x374c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3750, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3754, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3758, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x375c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3760, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3764, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3768, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x376c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3770, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3774, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3778, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x377c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3780, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3784, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3788, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x378c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3790, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x3794, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x3798, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x379c, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x37a0, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x37a4, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x37a8, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x37ac, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x37b0, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x37b4, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x37b8, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x37bc, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x37c0, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x37c4, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x37c8, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x37cc, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x37d0, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x37d4, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x37d8, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x37dc, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x37e0, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x37e4, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x37e8, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x37ec, 0 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN", 0x37f0, 0 },
+		{ "PCIEOfst", 10, 22 },
+		{ "BIR", 8, 2 },
+		{ "Window", 0, 8 },
+	{ "PCIE_MEM_ACCESS_BASE_WIN1", 0x37f4, 0 },
+	{ "PCIE_MEM_ACCESS_OFFSET0", 0x37f8, 0 },
+		{ "MemOfst0", 3, 29 },
+		{ "PFNum", 0, 3 },
+	{ "PCIE_MEM_ACCESS_OFFSET1", 0x37fc, 0 },
+	{ "PCIE_COOKIE_STAT", 0x5600, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x5604, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x5608, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x560c, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x5610, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x5614, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x5618, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_COOKIE_STAT", 0x561c, 0 },
+		{ "CookieB", 16, 10 },
+		{ "CookieA", 0, 10 },
+	{ "PCIE_FLR_PIO", 0x5620, 0 },
+		{ "RcvdBAR2Cookie", 24, 8 },
+		{ "RcvdMARspCookie", 16, 8 },
+		{ "RcvdPIORspCookie", 8, 8 },
+		{ "ExpdCookie", 0, 8 },
+	{ "PCIE_FLR_PIO2", 0x5624, 0 },
+		{ "RcvdVDMRxCookie", 24, 8 },
+		{ "RcvdVDMTxCookie", 16, 8 },
+		{ "RcvdMAReqCookie", 8, 8 },
+		{ "RcvdPIOReqCookie", 0, 8 },
+	{ "PCIE_VC0_CDTS0", 0x56c4, 0 },
+		{ "CPLD0", 16, 16 },
+		{ "CPLH0", 0, 12 },
+	{ "PCIE_VC0_CDTS1", 0x56c8, 0 },
+		{ "PD0", 16, 16 },
+		{ "PH0", 0, 12 },
+	{ "PCIE_VC0_CDTS2", 0x56cc, 0 },
+		{ "NPD0", 16, 16 },
+		{ "NPH0", 0, 12 },
+	{ "PCIE_VC1_CDTS0", 0x56d0, 0 },
+		{ "CPLD0", 16, 16 },
+		{ "CPLH0", 0, 12 },
+	{ "PCIE_VC1_CDTS1", 0x56d4, 0 },
+		{ "PD0", 16, 16 },
+		{ "PH0", 0, 12 },
+	{ "PCIE_VC1_CDTS2", 0x56d8, 0 },
+		{ "NPD0", 16, 16 },
+		{ "NPH0", 0, 12 },
+	{ "PCIE_FLR_PF_STATUS", 0x56dc, 0 },
+	{ "PCIE_FLR_VF0_STATUS", 0x56e0, 0 },
+	{ "PCIE_FLR_VF1_STATUS", 0x56e4, 0 },
+	{ "PCIE_FLR_VF2_STATUS", 0x56e8, 0 },
+	{ "PCIE_FLR_VF3_STATUS", 0x56ec, 0 },
+	{ "PCIE_STAT", 0x56f4, 0 },
+		{ "PM_Status", 24, 8 },
+		{ "PM_CurrentState", 20, 3 },
+		{ "LTSSMEnable", 12, 1 },
+		{ "StateCfgInitF", 4, 8 },
+		{ "StateCfgInit", 0, 4 },
+	{ "PCIE_CRS", 0x56f8, 0 },
+	{ "PCIE_LTSSM", 0x56fc, 0 },
+		{ "Stall_Disable", 1, 1 },
+		{ "Enable", 0, 1 },
+	{ "PCIE_PF_CFG", 0x1e040, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1e044, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1e440, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1e444, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1e840, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1e844, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1ec40, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1ec44, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1f040, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1f044, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1f440, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1f444, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1f840, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1f844, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_PF_CFG", 0x1fc40, 0 },
+		{ "INTXStat", 16, 1 },
+		{ "AIVec", 4, 10 },
+		{ "D3HotEn", 1, 1 },
+		{ "CLIDecEn", 0, 1 },
+	{ "PCIE_PF_CLI", 0x1fc44, 0 },
+	{ "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
+		{ "Offset", 10, 14 },
+	{ "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 },
+		{ "Replay_Time_Limit", 16, 16 },
+		{ "Ack_Latency_Timer_Limit", 0, 16 },
+	{ "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 },
+	{ "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 },
+		{ "Low_Power_Entrance_Count", 24, 8 },
+		{ "Link_State", 16, 6 },
+		{ "Force_Link", 15, 1 },
+		{ "Link_Number", 0, 8 },
+	{ "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 },
+		{ "Enter_ASPM_L1_wo_L0s", 30, 1 },
+		{ "L1_Entrance_Latency", 27, 3 },
+		{ "L0s_Entrance_Latency", 24, 3 },
+		{ "Common_Clock_N_FTS", 16, 8 },
+		{ "N_FTS", 8, 8 },
+		{ "Ack_Frequency", 0, 8 },
+	{ "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 },
+		{ "Crosslink_Active", 23, 1 },
+		{ "Crosslink_Enable", 22, 1 },
+		{ "Link_Mode_Enable", 16, 6 },
+		{ "Fast_Link_Mode", 7, 1 },
+		{ "DLL_Link_Enable", 5, 1 },
+		{ "Reset_Assert", 3, 1 },
+		{ "Loopback_Enable", 2, 1 },
+		{ "Scramble_Disable", 1, 1 },
+		{ "Vendor_Specific_DLLP_Request", 0, 1 },
+	{ "PCIE_CORE_LANE_SKEW", 0x5714, 0 },
+		{ "Disable_DeSkew", 31, 1 },
+		{ "Ack_Nak_Disable", 25, 1 },
+		{ "Flow_Control_Disable", 24, 1 },
+		{ "Insert_TxSkew", 0, 24 },
+	{ "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 },
+		{ "Ack_Nak_Timer_Modifier", 19, 5 },
+		{ "Replay_Timer_Modifier", 14, 5 },
+		{ "MaxFunc", 0, 3 },
+	{ "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 },
+		{ "Mask_RADM_Filter", 16, 16 },
+		{ "Disable_FC_Watchdog", 15, 1 },
+		{ "SKP_Interval", 0, 11 },
+	{ "PCIE_CORE_FILTER_MASK2", 0x5720, 0 },
+	{ "PCIE_CORE_DEBUG_0", 0x5728, 0 },
+	{ "PCIE_CORE_DEBUG_1", 0x572c, 0 },
+	{ "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 },
+		{ "TxPH_FC", 12, 8 },
+		{ "TxPD_FC", 0, 12 },
+	{ "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 },
+		{ "TxNPH_FC", 12, 8 },
+		{ "TxNPD_FC", 0, 12 },
+	{ "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 },
+		{ "TxCPLH_FC", 12, 8 },
+		{ "TxCPLD_FC", 0, 12 },
+	{ "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 },
+		{ "RxQueue_Not_Empty", 2, 1 },
+		{ "TxRetryBuf_Not_Empty", 1, 1 },
+		{ "RxTLP_FC_Not_Returned", 0, 1 },
+	{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 },
+		{ "VC3_WRR", 24, 8 },
+		{ "VC2_WRR", 16, 8 },
+		{ "VC1_WRR", 8, 8 },
+		{ "VC0_WRR", 0, 8 },
+	{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 },
+		{ "VC7_WRR", 24, 8 },
+		{ "VC6_WRR", 16, 8 },
+		{ "VC5_WRR", 8, 8 },
+		{ "VC4_WRR", 0, 8 },
+	{ "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 },
+		{ "VC0_Rx_Ordering", 31, 1 },
+		{ "VC0_TLP_Ordering", 30, 1 },
+		{ "VC0_PTLP_Queue_Mode", 21, 3 },
+		{ "VC0_PH_Credits", 12, 8 },
+		{ "VC0_PD_Credits", 0, 12 },
+	{ "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 },
+		{ "VC0_NPTLP_Queue_Mode", 21, 3 },
+		{ "VC0_NPH_Credits", 12, 8 },
+		{ "VC0_NPD_Credits", 0, 12 },
+	{ "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 },
+		{ "VC0_CPLTLP_Queue_Mode", 21, 3 },
+		{ "VC0_CPLH_Credits", 12, 8 },
+		{ "VC0_CPLD_Credits", 0, 12 },
+	{ "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 },
+		{ "VC1_TLP_Ordering", 30, 1 },
+		{ "VC1_PTLP_Queue_Mode", 21, 3 },
+		{ "VC1_PH_Credits", 12, 8 },
+		{ "VC1_PD_Credits", 0, 12 },
+	{ "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 },
+		{ "VC1_NPTLP_Queue_Mode", 21, 3 },
+		{ "VC1_NPH_Credits", 12, 8 },
+		{ "VC1_NPD_Credits", 0, 12 },
+	{ "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 },
+		{ "VC1_CPLTLP_Queue_Mode", 21, 3 },
+		{ "VC1_CPLH_Credits", 12, 8 },
+		{ "VC1_CPLD_Credits", 0, 12 },
+	{ "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 },
+		{ "Sel_DeEmphasis", 20, 1 },
+		{ "TxCmplRcv", 19, 1 },
+		{ "PhyTxSwing", 18, 1 },
+		{ "DirSpdChange", 17, 1 },
+		{ "Auto_Lane_Flip_Ctrl_En", 16, 1 },
+		{ "Num_Lanes", 8, 5 },
+		{ "NFTS_Gen2_3", 0, 8 },
+	{ "PCIE_CORE_PHY_STATUS", 0x5810, 0 },
+	{ "PCIE_CORE_PHY_CONTROL", 0x5814, 0 },
+	{ "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 },
+		{ "Rate_Shadow_Sel", 24, 2 },
+		{ "DC_Balance_Disable", 18, 1 },
+		{ "DLLP_Delay_Disable", 17, 1 },
+		{ "Eql_Disable", 16, 1 },
+		{ "Eql_Redo_Disable", 11, 1 },
+		{ "Eql_EIEOS_CntRst_Disable", 10, 1 },
+		{ "Eql_PH2_PH3_Disable", 9, 1 },
+		{ "Disable_Scrambler", 8, 1 },
+	{ "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 },
+		{ "Full_Swing", 6, 6 },
+		{ "Low_Frequency", 0, 6 },
+	{ "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 },
+		{ "PostCursor", 12, 6 },
+		{ "Cursor", 6, 6 },
+		{ "PreCursor", 0, 6 },
+	{ "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 },
+	{ "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 },
+	{ "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 },
+		{ "Include_Initial_FOM", 24, 1 },
+		{ "Preset_Request_Vector", 8, 16 },
+		{ "Phase23_2ms_Timeout_Disable", 5, 1 },
+		{ "After24ms", 4, 1 },
+		{ "Feedback_Mode", 0, 4 },
+	{ "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 },
+		{ "WinAperture_CPlus1", 14, 4 },
+		{ "WinAperture_CMins1", 10, 4 },
+		{ "Convergence_WinDepth", 5, 5 },
+		{ "EQMasterPhase_MinTime", 0, 5 },
+	{ "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 },
+		{ "Loopback_Enable", 31, 1 },
+	{ "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 },
+	{ "PCIE_X8_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x4700, 0 },
+		{ "Replay_Time_Limit", 16, 16 },
+		{ "Ack_Latency_Timer_Limit", 0, 16 },
+	{ "PCIE_X8_CORE_VENDOR_SPECIFIC_DLLP", 0x4704, 0 },
+	{ "PCIE_X8_CORE_PORT_FORCE_LINK", 0x4708, 0 },
+		{ "Low_Power_Entrance_Count", 24, 8 },
+		{ "Link_State", 16, 6 },
+		{ "Force_Link", 15, 1 },
+		{ "Link_Number", 0, 8 },
+	{ "PCIE_X8_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x470c, 0 },
+		{ "Enter_ASPM_L1_wo_L0s", 30, 1 },
+		{ "L1_Entrance_Latency", 27, 3 },
+		{ "L0s_Entrance_Latency", 24, 3 },
+		{ "Common_Clock_N_FTS", 16, 8 },
+		{ "N_FTS", 8, 8 },
+		{ "Ack_Frequency", 0, 8 },
+	{ "PCIE_X8_CORE_PORT_LINK_CONTROL", 0x4710, 0 },
+		{ "Crosslink_Active", 23, 1 },
+		{ "Crosslink_Enable", 22, 1 },
+		{ "Link_Mode_Enable", 16, 6 },
+		{ "Fast_Link_Mode", 7, 1 },
+		{ "DLL_Link_Enable", 5, 1 },
+		{ "Reset_Assert", 3, 1 },
+		{ "Loopback_Enable", 2, 1 },
+		{ "Scramble_Disable", 1, 1 },
+		{ "Vendor_Specific_DLLP_Request", 0, 1 },
+	{ "PCIE_X8_CORE_LANE_SKEW", 0x4714, 0 },
+		{ "Disable_DeSkew", 31, 1 },
+		{ "Ack_Nak_Disable", 25, 1 },
+		{ "Flow_Control_Disable", 24, 1 },
+		{ "Insert_TxSkew", 0, 24 },
+	{ "PCIE_X8_CORE_SYMBOL_NUMBER", 0x4718, 0 },
+		{ "Ack_Nak_Timer_Modifier", 19, 5 },
+		{ "Replay_Timer_Modifier", 14, 5 },
+		{ "MaxFunc", 0, 3 },
+	{ "PCIE_X8_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x471c, 0 },
+		{ "Mask_RADM_Filter", 16, 16 },
+		{ "Disable_FC_Watchdog", 15, 1 },
+		{ "SKP_Interval", 0, 11 },
+	{ "PCIE_X8_CORE_FILTER_MASK2", 0x4720, 0 },
+	{ "PCIE_X8_CORE_DEBUG_0", 0x4728, 0 },
+	{ "PCIE_X8_CORE_DEBUG_1", 0x472c, 0 },
+	{ "PCIE_X8_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x4730, 0 },
+		{ "TxPH_FC", 12, 8 },
+		{ "TxPD_FC", 0, 12 },
+	{ "PCIE_X8_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x4734, 0 },
+		{ "TxNPH_FC", 12, 8 },
+		{ "TxNPD_FC", 0, 12 },
+	{ "PCIE_X8_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x4738, 0 },
+		{ "TxCPLH_FC", 12, 8 },
+		{ "TxCPLD_FC", 0, 12 },
+	{ "PCIE_X8_CORE_QUEUE_STATUS", 0x473c, 0 },
+		{ "RxQueue_Not_Empty", 2, 1 },
+		{ "TxRetryBuf_Not_Empty", 1, 1 },
+		{ "RxTLP_FC_Not_Returned", 0, 1 },
+	{ "PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_1", 0x4740, 0 },
+		{ "VC3_WRR", 24, 8 },
+		{ "VC2_WRR", 16, 8 },
+		{ "VC1_WRR", 8, 8 },
+		{ "VC0_WRR", 0, 8 },
+	{ "PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_2", 0x4744, 0 },
+		{ "VC7_WRR", 24, 8 },
+		{ "VC6_WRR", 16, 8 },
+		{ "VC5_WRR", 8, 8 },
+		{ "VC4_WRR", 0, 8 },
+	{ "PCIE_X8_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x4748, 0 },
+		{ "VC0_Rx_Ordering", 31, 1 },
+		{ "VC0_TLP_Ordering", 30, 1 },
+		{ "VC0_PTLP_Queue_Mode", 21, 3 },
+		{ "VC0_PH_Credits", 12, 8 },
+		{ "VC0_PD_Credits", 0, 12 },
+	{ "PCIE_X8_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x474c, 0 },
+		{ "VC0_NPTLP_Queue_Mode", 21, 3 },
+		{ "VC0_NPH_Credits", 12, 8 },
+		{ "VC0_NPD_Credits", 0, 12 },
+	{ "PCIE_X8_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x4750, 0 },
+		{ "VC0_CPLTLP_Queue_Mode", 21, 3 },
+		{ "VC0_CPLH_Credits", 12, 8 },
+		{ "VC0_CPLD_Credits", 0, 12 },
+	{ "PCIE_X8_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x4754, 0 },
+		{ "VC1_TLP_Ordering", 30, 1 },
+		{ "VC1_PTLP_Queue_Mode", 21, 3 },
+		{ "VC1_PH_Credits", 12, 8 },
+		{ "VC1_PD_Credits", 0, 12 },
+	{ "PCIE_X8_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x4758, 0 },
+		{ "VC1_NPTLP_Queue_Mode", 21, 3 },
+		{ "VC1_NPH_Credits", 12, 8 },
+		{ "VC1_NPD_Credits", 0, 12 },
+	{ "PCIE_X8_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x475c, 0 },
+		{ "VC1_CPLTLP_Queue_Mode", 21, 3 },
+		{ "VC1_CPLH_Credits", 12, 8 },
+		{ "VC1_CPLD_Credits", 0, 12 },
+	{ "PCIE_X8_CORE_LINK_WIDTH_SPEED_CHANGE", 0x480c, 0 },
+		{ "Sel_DeEmphasis", 20, 1 },
+		{ "TxCmplRcv", 19, 1 },
+		{ "PhyTxSwing", 18, 1 },
+		{ "DirSpdChange", 17, 1 },
+		{ "Auto_Lane_Flip_Ctrl_En", 16, 1 },
+		{ "Num_Lanes", 8, 5 },
+		{ "NFTS_Gen2_3", 0, 8 },
+	{ "PCIE_X8_CORE_PHY_STATUS", 0x4810, 0 },
+	{ "PCIE_X8_CORE_PHY_CONTROL", 0x4814, 0 },
+	{ "PCIE_X8_CORE_GEN3_CONTROL", 0x4890, 0 },
+		{ "Rate_Shadow_Sel", 24, 2 },
+		{ "DC_Balance_Disable", 18, 1 },
+		{ "DLLP_Delay_Disable", 17, 1 },
+		{ "Eql_Disable", 16, 1 },
+		{ "Eql_Redo_Disable", 11, 1 },
+		{ "Eql_EIEOS_CntRst_Disable", 10, 1 },
+		{ "Eql_PH2_PH3_Disable", 9, 1 },
+		{ "Disable_Scrambler", 8, 1 },
+	{ "PCIE_X8_CORE_GEN3_EQ_FS_LF", 0x4894, 0 },
+		{ "Full_Swing", 6, 6 },
+		{ "Low_Frequency", 0, 6 },
+	{ "PCIE_X8_CORE_GEN3_EQ_PRESET_COEFF", 0x4898, 0 },
+		{ "PostCursor", 12, 6 },
+		{ "Cursor", 6, 6 },
+		{ "PreCursor", 0, 6 },
+	{ "PCIE_X8_CORE_GEN3_EQ_PRESET_INDEX", 0x489c, 0 },
+	{ "PCIE_X8_CORE_GEN3_EQ_STATUS", 0x48a4, 0 },
+	{ "PCIE_X8_CORE_GEN3_EQ_CONTROL", 0x48a8, 0 },
+		{ "Include_Initial_FOM", 24, 1 },
+		{ "Preset_Request_Vector", 8, 16 },
+		{ "Phase23_2ms_Timeout_Disable", 5, 1 },
+		{ "After24ms", 4, 1 },
+		{ "Feedback_Mode", 0, 4 },
+	{ "PCIE_X8_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x48ac, 0 },
+		{ "WinAperture_CPlus1", 14, 4 },
+		{ "WinAperture_CMins1", 10, 4 },
+		{ "Convergence_WinDepth", 5, 5 },
+		{ "EQMasterPhase_MinTime", 0, 5 },
+	{ "PCIE_X8_CORE_PIPE_CONTROL", 0x48b8, 0 },
+		{ "Loopback_Enable", 31, 1 },
+	{ "PCIE_X8_CORE_DBI_RO_WE", 0x48bc, 0 },
+	{ "PCIE_X8_CFG_SPACE_REQ", 0x48c0, 0 },
+		{ "Enable", 31, 1 },
+		{ "AI", 30, 1 },
+		{ "CS2", 29, 1 },
+		{ "WrBE", 25, 4 },
+		{ "ExtRegister", 8, 4 },
+		{ "Register", 0, 8 },
+	{ "PCIE_X8_CFG_SPACE_DATA", 0x48c4, 0 },
+	{ "PCIE_X8_CFG_MPS_MRS", 0x4900, 0 },
+		{ "MRS", 3, 3 },
+		{ "MPS", 0, 3 },
+	{ "PCIE_X8_CFG_ATTRIBUTES", 0x4904, 0 },
+		{ "DcaEn", 2, 1 },
+		{ "DcaStFitTraOnlEn", 1, 1 },
+		{ "ReqCtlDynStClkEn", 0, 1 },
+	{ "PCIE_X8_CFG_LTSSM", 0x4908, 0 },
+	{ "PCIE_ARM_REQUESTER_ID_X8", 0x490c, 0 },
+		{ "PrimBusnumber", 16, 8 },
+		{ "RequesterId", 0, 16 },
+	{ "PCIE_SWAP_DATA_B2L_X8", 0x4910, 0 },
+		{ "cfgrd_swap_en", 1, 1 },
+		{ "cfgwr_swap_en", 0, 1 },
+	{ "PCIE_PDEBUG_DATA0_X8", 0x4914, 0 },
+	{ "PCIE_PDEBUG_DATA1_X8", 0x4918, 0 },
+	{ "PCIE_PDEBUG_DATA2_X8", 0x491c, 0 },
+	{ "PCIE_PDEBUG_CTRL_X8", 0x4920, 0 },
+	{ "PCIE_PDEBUG_DATA_X8", 0x4924, 0 },
+	{ "PCIE_SPARE_REGISTER_SPACES_X8", 0x4ffc, 0 },
+	{ "PCIE_DMA_CFG", 0x5940, 0 },
+		{ "MaxPyldSize", 28, 3 },
+		{ "MaxReqCnt", 20, 7 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 8 },
+		{ "SeqChkDis", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_DMA_STAT", 0x5944, 0 },
+		{ "RspCnt", 20, 10 },
+		{ "RdReqCnt", 12, 6 },
+		{ "WrReqCnt", 0, 9 },
+	{ "PCIE_DMA_STAT2", 0x5948, 0 },
+		{ "CookieCnt", 24, 4 },
+		{ "RdSeqNumUpdCnt", 20, 4 },
+		{ "SIReqCnt", 16, 4 },
+		{ "WrEOPMatchSOP", 12, 1 },
+		{ "WrSOPCnt", 8, 4 },
+		{ "RdSOPCnt", 0, 8 },
+	{ "PCIE_DMA_STAT3", 0x594c, 0 },
+		{ "AtmReqSOPCnt", 24, 8 },
+		{ "AtmEOPMatchSOP", 17, 1 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_DMA_CFG", 0x5950, 0 },
+		{ "MaxPyldSize", 28, 3 },
+		{ "MaxReqCnt", 20, 7 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 8 },
+		{ "SeqChkDis", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_DMA_STAT", 0x5954, 0 },
+		{ "RspCnt", 20, 10 },
+		{ "RdReqCnt", 12, 6 },
+		{ "WrReqCnt", 0, 9 },
+	{ "PCIE_DMA_STAT2", 0x5958, 0 },
+		{ "CookieCnt", 24, 4 },
+		{ "RdSeqNumUpdCnt", 20, 4 },
+		{ "SIReqCnt", 16, 4 },
+		{ "WrEOPMatchSOP", 12, 1 },
+		{ "WrSOPCnt", 8, 4 },
+		{ "RdSOPCnt", 0, 8 },
+	{ "PCIE_DMA_STAT3", 0x595c, 0 },
+		{ "AtmReqSOPCnt", 24, 8 },
+		{ "AtmEOPMatchSOP", 17, 1 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_DMA_CFG", 0x5960, 0 },
+		{ "MaxPyldSize", 28, 3 },
+		{ "MaxReqCnt", 20, 7 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 8 },
+		{ "SeqChkDis", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_DMA_STAT", 0x5964, 0 },
+		{ "RspCnt", 20, 10 },
+		{ "RdReqCnt", 12, 6 },
+		{ "WrReqCnt", 0, 9 },
+	{ "PCIE_DMA_STAT2", 0x5968, 0 },
+		{ "CookieCnt", 24, 4 },
+		{ "RdSeqNumUpdCnt", 20, 4 },
+		{ "SIReqCnt", 16, 4 },
+		{ "WrEOPMatchSOP", 12, 1 },
+		{ "WrSOPCnt", 8, 4 },
+		{ "RdSOPCnt", 0, 8 },
+	{ "PCIE_DMA_STAT3", 0x596c, 0 },
+		{ "AtmReqSOPCnt", 24, 8 },
+		{ "AtmEOPMatchSOP", 17, 1 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_DMA_CFG", 0x5970, 0 },
+		{ "MaxPyldSize", 28, 3 },
+		{ "MaxReqCnt", 20, 7 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 8 },
+		{ "SeqChkDis", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_DMA_STAT", 0x5974, 0 },
+		{ "RspCnt", 20, 10 },
+		{ "RdReqCnt", 12, 6 },
+		{ "WrReqCnt", 0, 9 },
+	{ "PCIE_DMA_STAT2", 0x5978, 0 },
+		{ "CookieCnt", 24, 4 },
+		{ "RdSeqNumUpdCnt", 20, 4 },
+		{ "SIReqCnt", 16, 4 },
+		{ "WrEOPMatchSOP", 12, 1 },
+		{ "WrSOPCnt", 8, 4 },
+		{ "RdSOPCnt", 0, 8 },
+	{ "PCIE_DMA_STAT3", 0x597c, 0 },
+		{ "AtmReqSOPCnt", 24, 8 },
+		{ "AtmEOPMatchSOP", 17, 1 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_CMD_CFG", 0x5980, 0 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 6 },
+		{ "UseCmdPool", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_CMD_STAT", 0x5984, 0 },
+		{ "RspCnt", 20, 8 },
+		{ "RdReqCnt", 12, 4 },
+	{ "PCIE_CMD_STAT2", 0x5988, 0 },
+	{ "PCIE_CMD_STAT3", 0x598c, 0 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_HMA_CFG", 0x59b0, 0 },
+		{ "MaxPyldSize", 28, 3 },
+		{ "MaxReqCnt", 20, 7 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 8 },
+		{ "SeqChkDis", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_HMA_STAT", 0x59b4, 0 },
+		{ "RspCnt", 20, 10 },
+		{ "RdReqCnt", 12, 6 },
+		{ "WrReqCnt", 0, 9 },
+	{ "PCIE_HMA_STAT2", 0x59b8, 0 },
+		{ "CookieCnt", 24, 4 },
+		{ "RdSeqNumUpdCnt", 20, 4 },
+		{ "WrEOPMatchSOP", 12, 1 },
+		{ "WrSOPCnt", 8, 4 },
+		{ "RdSOPCnt", 0, 8 },
+	{ "PCIE_HMA_STAT3", 0x59bc, 0 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_CGEN", 0x59c0, 0 },
+		{ "ARM_Static_CGEN", 28, 1 },
+		{ "ARM_Dynamic_CGEN", 27, 1 },
+		{ "VPD_Dynamic_CGEN", 26, 1 },
+		{ "MA_Dynamic_CGEN", 25, 1 },
+		{ "Tagq_Dynamic_CGEN", 24, 1 },
+		{ "ReqCtl_Dynamic_CGEN", 23, 1 },
+		{ "RspDataProc_Dynamic_CGEN", 22, 1 },
+		{ "RspRdq_Dynamic_CGEN", 21, 1 },
+		{ "RspIPif_Dynamic_CGEN", 20, 1 },
+		{ "HMA_Static_CGEN", 19, 1 },
+		{ "HMA_Dynamic_CGEN", 18, 1 },
+		{ "CMD_Static_CGEN", 16, 1 },
+		{ "CMD_Dynamic_CGEN", 15, 1 },
+		{ "DMA_Static_CGEN", 13, 1 },
+		{ "DMA_Dynamic_CGEN", 12, 1 },
+		{ "VFID_SleepStatus", 10, 1 },
+		{ "VC1_SleepStatus", 9, 1 },
+		{ "STI_SleepStatus", 8, 1 },
+		{ "VFID_SleepReq", 2, 1 },
+		{ "VC1_SleepReq", 1, 1 },
+		{ "STI_SleepReq", 0, 1 },
+	{ "PCIE_MA_RSP", 0x59c4, 0 },
+		{ "TimerValue", 8, 24 },
+		{ "MAReqTimerEn", 1, 1 },
+		{ "TimerEn", 0, 1 },
+	{ "PCIE_HPRD", 0x59c8, 0 },
+		{ "NPH_CreditsAvailVC0", 19, 2 },
+		{ "NPD_CreditsAvailVC0", 17, 2 },
+		{ "NPH_CreditsAvailVC1", 15, 2 },
+		{ "NPD_CreditsAvailVC1", 13, 2 },
+		{ "NPH_CreditsRequired", 11, 2 },
+		{ "NPD_CreditsRequired", 9, 2 },
+		{ "ReqBurstCount", 5, 4 },
+		{ "ReqBurstFrequency", 1, 4 },
+		{ "EnableVC1", 0, 1 },
+	{ "PCIE_PERR_GROUP", 0x59d0, 0 },
+		{ "TGT1_MEM_Perr", 28, 1 },
+		{ "TGT2_MEM_Perr", 27, 1 },
+		{ "MA_RspCtlPerr", 26, 1 },
+		{ "MST_DataPathPerr", 25, 1 },
+		{ "MST_RspRdQPerr", 24, 1 },
+		{ "TRGT1_FIDLkUpHdrPerr", 20, 1 },
+		{ "TRGT1_AlindDataPerr", 19, 1 },
+		{ "TRGT1_UnAlinDataPerr", 18, 1 },
+		{ "TRGT1_ReqDataPerr", 17, 1 },
+		{ "TRGT1_ReqHdrPerr", 16, 1 },
+		{ "IPRxData_VC0Perr", 15, 1 },
+		{ "IPRxHdr_VC0Perr", 14, 1 },
+		{ "PIOCpl_VDMTxCtlPerr", 13, 1 },
+		{ "PIOCpl_VDMTxDataPerr", 12, 1 },
+		{ "MA_RspDataPerr", 11, 1 },
+		{ "MA_CplTagQPerr", 10, 1 },
+		{ "MA_ReqTagQPerr", 9, 1 },
+		{ "PIOReq_BAR2CtlPerr", 8, 1 },
+		{ "PIOReq_MEMCtlPerr", 7, 1 },
+		{ "PIOReq_PLMCtlPerr", 6, 1 },
+		{ "PIOReq_BAR2DataPerr", 5, 1 },
+		{ "PIOReq_MEMDataPerr", 4, 1 },
+		{ "PIOReq_PLMDataPerr", 3, 1 },
+		{ "PIOCpl_CtlPerr", 2, 1 },
+		{ "PIOCpl_DataPerr", 1, 1 },
+		{ "PIOCpl_PLMRspPerr", 0, 1 },
+	{ "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 },
+		{ "CplStatusIntEn", 12, 1 },
+		{ "TimeoutIntEn", 11, 1 },
+		{ "DisabledIntEn", 10, 1 },
+		{ "RspDropFLRIntEn", 9, 1 },
+		{ "ReqUnderFLRIntEn", 8, 1 },
+		{ "CplStatusLogEn", 4, 1 },
+		{ "TimeoutLogEn", 3, 1 },
+		{ "DisabledLogEn", 2, 1 },
+		{ "RspDropFLRLogEn", 1, 1 },
+		{ "ReqUnderFLRLogEn", 0, 1 },
+	{ "PCIE_RSP_ERR_LOG1", 0x59d8, 0 },
+		{ "Tag", 25, 7 },
+		{ "CID", 22, 3 },
+		{ "ChNum", 19, 3 },
+		{ "ByteLen", 6, 13 },
+		{ "Reason", 3, 3 },
+		{ "CplStatus", 0, 3 },
+	{ "PCIE_RSP_ERR_LOG2", 0x59dc, 0 },
+		{ "Valid", 31, 1 },
+		{ "Addr10b", 9, 10 },
+		{ "VFID", 0, 9 },
+	{ "PCIE_REVISION", 0x5a00, 0 },
+	{ "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
+		{ "PDEBUGSelH", 16, 8 },
+		{ "PDEBUGSelL", 0, 8 },
+	{ "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
+	{ "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
+	{ "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
+		{ "CDEBUGSelH", 16, 8 },
+		{ "CDEBUGSelL", 0, 8 },
+	{ "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
+	{ "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
+	{ "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
+	{ "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
+	{ "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
+	{ "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
+	{ "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
+	{ "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
+	{ "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
+	{ "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
+	{ "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 },
+	{ "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 },
+	{ "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 },
+		{ "Valid", 31, 1 },
+		{ "Source", 17, 2 },
+		{ "Write", 13, 4 },
+		{ "CS2", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VFVld", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "PCIE_PB_CTL", 0x5b94, 0 },
+		{ "PB_Sel", 16, 8 },
+		{ "PB_SelReg", 8, 8 },
+		{ "PB_Func", 0, 3 },
+	{ "PCIE_PB_DATA", 0x5b98, 0 },
+	{ "PCIE_CHANGESET", 0x59fc, 0 },
+	{ "PCIE_CUR_LINK", 0x5b9c, 0 },
+		{ "CfgInitCoeffDoneSeen", 22, 1 },
+		{ "CfgInitCoeffDone", 21, 1 },
+		{ "xmlh_link_up", 20, 1 },
+		{ "pm_linkst_in_l0s", 19, 1 },
+		{ "pm_linkst_in_l1", 18, 1 },
+		{ "pm_linkst_in_l2", 17, 1 },
+		{ "pm_linkst_l2_exit", 16, 1 },
+		{ "xmlh_in_rl0s", 15, 1 },
+		{ "xmlh_ltssm_state_rcvry_eq", 14, 1 },
+		{ "NegotiatedWidth", 8, 6 },
+		{ "ActiveLanes", 0, 8 },
+	{ "PCIE_PHY_REQRXPWR", 0x5ba0, 0 },
+		{ "Req_LnH_RxStateDone", 31, 1 },
+		{ "Req_LnH_RxStateReq", 30, 1 },
+		{ "Req_LnH_RxPwrState", 28, 2 },
+		{ "Req_LnG_RxStateDone", 27, 1 },
+		{ "Req_LnG_RxStateReq", 26, 1 },
+		{ "Req_LnG_RxPwrState", 24, 2 },
+		{ "Req_LnF_RxStateDone", 23, 1 },
+		{ "Req_LnF_RxStateReq", 22, 1 },
+		{ "Req_LnF_RxPwrState", 20, 2 },
+		{ "Req_LnE_RxStateDone", 19, 1 },
+		{ "Req_LnE_RxStateReq", 18, 1 },
+		{ "Req_LnE_RxPwrState", 16, 2 },
+		{ "Req_LnD_RxStateDone", 15, 1 },
+		{ "Req_LnD_RxStateReq", 14, 1 },
+		{ "Req_LnD_RxPwrState", 12, 2 },
+		{ "Req_LnC_RxStateDone", 11, 1 },
+		{ "Req_LnC_RxStateReq", 10, 1 },
+		{ "Req_LnC_RxPwrState", 8, 2 },
+		{ "Req_LnB_RxStateDone", 7, 1 },
+		{ "Req_LnB_RxStateReq", 6, 1 },
+		{ "Req_LnB_RxPwrState", 4, 2 },
+		{ "Req_LnA_RxStateDone", 3, 1 },
+		{ "Req_LnA_RxStateReq", 2, 1 },
+		{ "Req_LnA_RxPwrState", 0, 2 },
+	{ "PCIE_PHY_CURRXPWR", 0x5ba4, 0 },
+		{ "Cur_LnH_RxPwrState", 28, 3 },
+		{ "Cur_LnG_RxPwrState", 24, 3 },
+		{ "Cur_LnF_RxPwrState", 20, 3 },
+		{ "Cur_LnE_RxPwrState", 16, 3 },
+		{ "Cur_LnD_RxPwrState", 12, 3 },
+		{ "Cur_LnC_RxPwrState", 8, 3 },
+		{ "Cur_LnB_RxPwrState", 4, 3 },
+		{ "Cur_LnA_RxPwrState", 0, 3 },
+	{ "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 },
+		{ "LnD_STAT", 28, 3 },
+		{ "LnD_CMD", 24, 3 },
+		{ "LnC_STAT", 20, 3 },
+		{ "LnC_CMD", 16, 3 },
+		{ "LnB_STAT", 12, 3 },
+		{ "LnB_CMD", 8, 3 },
+		{ "LnA_STAT", 4, 3 },
+		{ "LnA_CMD", 0, 3 },
+	{ "PCIE_PHY_GEN3_AE1", 0x5bac, 0 },
+		{ "LnH_STAT", 28, 3 },
+		{ "LnH_CMD", 24, 3 },
+		{ "LnG_STAT", 20, 3 },
+		{ "LnG_CMD", 16, 3 },
+		{ "LnF_STAT", 12, 3 },
+		{ "LnF_CMD", 8, 3 },
+		{ "LnE_STAT", 4, 3 },
+		{ "LnE_CMD", 0, 3 },
+	{ "PCIE_PHY_FS_LF0", 0x5bb0, 0 },
+		{ "Lane1LF", 24, 6 },
+		{ "Lane1FS", 16, 6 },
+		{ "Lane0LF", 8, 6 },
+		{ "Lane0FS", 0, 6 },
+	{ "PCIE_PHY_FS_LF1", 0x5bb4, 0 },
+		{ "Lane3LF", 24, 6 },
+		{ "Lane3FS", 16, 6 },
+		{ "Lane2LF", 8, 6 },
+		{ "Lane2FS", 0, 6 },
+	{ "PCIE_PHY_FS_LF2", 0x5bb8, 0 },
+		{ "Lane5LF", 24, 6 },
+		{ "Lane5FS", 16, 6 },
+		{ "Lane4LF", 8, 6 },
+		{ "Lane4FS", 0, 6 },
+	{ "PCIE_PHY_FS_LF3", 0x5bbc, 0 },
+		{ "Lane7LF", 24, 6 },
+		{ "Lane7FS", 16, 6 },
+		{ "Lane6LF", 8, 6 },
+		{ "Lane6FS", 0, 6 },
+	{ "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 },
+		{ "CoeffDone", 16, 1 },
+		{ "CoeffLane", 8, 4 },
+		{ "CoeffStart", 0, 1 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
+	{ "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
+	{ "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
+		{ "Enable", 31, 1 },
+		{ "RegAddr", 0, 16 },
+	{ "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
+	{ "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
+	{ "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
+		{ "x8_sw_en", 30, 1 },
+		{ "SwitchCfg", 28, 2 },
+		{ "STATIC_SPARE2", 0, 28 },
+	{ "PCIE_KDOORBELL_GTS_PF_BASE_LEN", 0x5c10, 0 },
+		{ "KDB_PF_Len", 24, 5 },
+		{ "KDB_PF_BaseAddr", 0, 20 },
+	{ "PCIE_KDOORBELL_GTS_VF_BASE_LEN", 0x5c14, 0 },
+		{ "KDB_VF_Len", 24, 5 },
+		{ "KDB_VF_BaseAddr", 0, 20 },
+	{ "PCIE_KDOORBELL_GTS_VF_OFFSET", 0x5c18, 0 },
+	{ "PCIE_PHY_REQRXPWR1", 0x5c1c, 0 },
+		{ "Req_LnP_RxStateDone", 31, 1 },
+		{ "Req_LnP_RxStateReq", 30, 1 },
+		{ "Req_LnP_RxPwrState", 28, 2 },
+		{ "Req_LnO_RxStateDone", 27, 1 },
+		{ "Req_LnO_RxStateReq", 26, 1 },
+		{ "Req_LnO_RxPwrState", 24, 2 },
+		{ "Req_LnN_RxStateDone", 23, 1 },
+		{ "Req_LnN_RxStateReq", 22, 1 },
+		{ "Req_LnN_RxPwrState", 20, 2 },
+		{ "Req_LnM_RxStateDone", 19, 1 },
+		{ "Req_LnM_RxStateReq", 18, 1 },
+		{ "Req_LnM_RxPwrState", 16, 2 },
+		{ "Req_LnL_RxStateDone", 15, 1 },
+		{ "Req_LnL_RxStateReq", 14, 1 },
+		{ "Req_LnL_RxPwrState", 12, 2 },
+		{ "Req_LnK_RxStateDone", 11, 1 },
+		{ "Req_LnK_RxStateReq", 10, 1 },
+		{ "Req_LnK_RxPwrState", 8, 2 },
+		{ "Req_LnJ_RxStateDone", 7, 1 },
+		{ "Req_LnJ_RxStateReq", 6, 1 },
+		{ "Req_LnJ_RxPwrState", 4, 2 },
+		{ "Req_LnI_RxStateDone", 3, 1 },
+		{ "Req_LnI_RxStateReq", 2, 1 },
+		{ "Req_LnI_RxPwrState", 0, 2 },
+	{ "PCIE_PHY_CURRXPWR1", 0x5c20, 0 },
+		{ "Cur_LnP_RxPwrState", 28, 3 },
+		{ "Cur_LnO_RxPwrState", 24, 3 },
+		{ "Cur_LnN_RxPwrState", 20, 3 },
+		{ "Cur_LnM_RxPwrState", 16, 3 },
+		{ "Cur_LnL_RxPwrState", 12, 3 },
+		{ "Cur_LnK_RxPwrState", 8, 3 },
+		{ "Cur_LnJ_RxPwrState", 4, 3 },
+		{ "Cur_LnI_RxPwrState", 0, 3 },
+	{ "PCIE_PHY_GEN3_AE2", 0x5c24, 0 },
+		{ "LnL_STAT", 28, 3 },
+		{ "LnL_CMD", 24, 3 },
+		{ "LnK_STAT", 20, 3 },
+		{ "LnK_CMD", 16, 3 },
+		{ "LnJ_STAT", 12, 3 },
+		{ "LnJ_CMD", 8, 3 },
+		{ "LnI_STAT", 4, 3 },
+		{ "LnI_CMD", 0, 3 },
+	{ "PCIE_PHY_GEN3_AE3", 0x5c28, 0 },
+		{ "LnP_STAT", 28, 3 },
+		{ "LnP_CMD", 24, 3 },
+		{ "LnO_STAT", 20, 3 },
+		{ "LnO_CMD", 16, 3 },
+		{ "LnN_STAT", 12, 3 },
+		{ "LnN_CMD", 8, 3 },
+		{ "LnM_STAT", 4, 3 },
+		{ "LnM_CMD", 0, 3 },
+	{ "PCIE_PHY_FS_LF4", 0x5c2c, 0 },
+		{ "Lane9LF", 24, 6 },
+		{ "Lane9FS", 16, 6 },
+		{ "Lane8LF", 8, 6 },
+		{ "Lane8FS", 0, 6 },
+	{ "PCIE_PHY_FS_LF5", 0x5c30, 0 },
+		{ "Lane11LF", 24, 6 },
+		{ "Lane11FS", 16, 6 },
+		{ "Lane10LF", 8, 6 },
+		{ "Lane10FS", 0, 6 },
+	{ "PCIE_PHY_FS_LF6", 0x5c34, 0 },
+		{ "Lane13LF", 24, 6 },
+		{ "Lane13FS", 16, 6 },
+		{ "Lane12LF", 8, 6 },
+		{ "Lane12FS", 0, 6 },
+	{ "PCIE_PHY_FS_LF7", 0x5c38, 0 },
+		{ "Lane15LF", 24, 6 },
+		{ "Lane15FS", 16, 6 },
+		{ "Lane14LF", 8, 6 },
+		{ "Lane14FS", 0, 6 },
+	{ "PCIE_MULTI_PHY_INDIR_REQ", 0x5c3c, 0 },
+		{ "Phy_Reg_Enable", 31, 1 },
+		{ "Phy_Reg_Select", 22, 2 },
+		{ "Phy_Reg_RegAddr", 0, 16 },
+	{ "PCIE_MULTI_PHY_INDIR_DATA", 0x5c40, 0 },
+	{ "PCIE_VF_INT_INDIR_REQ", 0x5c44, 0 },
+		{ "Enable", 24, 1 },
+		{ "AI", 23, 1 },
+		{ "VFID", 0, 10 },
+	{ "PCIE_VF_INT_INDIR_DATA", 0x5c48, 0 },
+		{ "VecNum", 12, 10 },
+		{ "VecBase", 0, 12 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c4c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c50, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c54, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c58, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c5c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c60, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c64, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c68, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c6c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c70, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c74, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c78, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c7c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c80, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c84, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c88, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c8c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c90, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c94, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c98, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5c9c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ca0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ca4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ca8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cac, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cb0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cb4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cb8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cbc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cc0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cc4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cc8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ccc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cd0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cd4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cd8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cdc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ce0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ce4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ce8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cec, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cf0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cf4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cf8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5cfc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d00, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d04, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d08, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d0c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d10, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d14, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d18, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d1c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d20, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d24, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d28, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d2c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d30, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d34, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d38, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d3c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d40, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d44, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d48, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d4c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d50, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d54, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d58, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d5c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d60, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d64, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d68, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d6c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d70, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d74, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d78, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d7c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d80, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d84, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d88, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d8c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d90, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d94, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d98, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5d9c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5da0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5da4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5da8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dac, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5db0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5db4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5db8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dbc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dc0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dc4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dc8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dcc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dd0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dd4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dd8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5ddc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5de0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5de4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5de8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dec, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5df0, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5df4, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5df8, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5dfc, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e00, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e04, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e08, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e0c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e10, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e14, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e18, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e1c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e20, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e24, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e28, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e2c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e30, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e34, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e38, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e3c, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e40, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e44, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_256_INT_CFG2", 0x5e48, 0 },
+		{ "SendFLRRsp", 31, 1 },
+		{ "ImmFLRRsp", 24, 1 },
+		{ "TxnDisable", 20, 1 },
+	{ "PCIE_VF_MSI_EN_4", 0x5e50, 0 },
+	{ "PCIE_VF_MSI_EN_5", 0x5e54, 0 },
+	{ "PCIE_VF_MSI_EN_6", 0x5e58, 0 },
+	{ "PCIE_VF_MSI_EN_7", 0x5e5c, 0 },
+	{ "PCIE_VF_MSIX_EN_4", 0x5e60, 0 },
+	{ "PCIE_VF_MSIX_EN_5", 0x5e64, 0 },
+	{ "PCIE_VF_MSIX_EN_6", 0x5e68, 0 },
+	{ "PCIE_VF_MSIX_EN_7", 0x5e6c, 0 },
+	{ "PCIE_FLR_VF4_STATUS", 0x5e70, 0 },
+	{ "PCIE_FLR_VF5_STATUS", 0x5e74, 0 },
+	{ "PCIE_FLR_VF6_STATUS", 0x5e78, 0 },
+	{ "PCIE_FLR_VF7_STATUS", 0x5e7c, 0 },
+	{ "PCIE_BUS_MST_STAT_4", 0x5e80, 0 },
+	{ "PCIE_BUS_MST_STAT_5", 0x5e84, 0 },
+	{ "PCIE_BUS_MST_STAT_6", 0x5e88, 0 },
+	{ "PCIE_BUS_MST_STAT_7", 0x5e8c, 0 },
+	{ "PCIE_BUS_MST_STAT_8", 0x5e90, 0 },
+	{ "PCIE_TGT_SKID_FIFO", 0x5e94, 0 },
+		{ "HdrFreeCnt", 16, 12 },
+		{ "DataFreeCnt", 0, 12 },
+	{ "PCIE_RSP_ERR_STAT_4", 0x5ea0, 0 },
+	{ "PCIE_RSP_ERR_STAT_5", 0x5ea4, 0 },
+	{ "PCIE_RSP_ERR_STAT_6", 0x5ea8, 0 },
+	{ "PCIE_RSP_ERR_STAT_7", 0x5eac, 0 },
+	{ "PCIE_RSP_ERR_STAT_8", 0x5eb0, 0 },
+	{ "PCIE_PHY_STAT1", 0x5ec0, 0 },
+		{ "PHY0_RTune_Ack", 31, 1 },
+		{ "PHY1_RTune_Ack", 30, 1 },
+	{ "PCIE_PHY_CTRL1", 0x5ec4, 0 },
+		{ "PHY0_RTune_Req", 31, 1 },
+		{ "PHY1_RTune_Req", 30, 1 },
+		{ "TxDeemph_gen1", 16, 8 },
+		{ "TxDeemph_gen2_3p5db", 8, 8 },
+		{ "TxDeemph_gen2_6db", 0, 8 },
+	{ "PCIE_PCIE_SPARE0", 0x5ec8, 0 },
+	{ "PCIE_RESET_STAT", 0x5ecc, 0 },
+		{ "PON_RST_STATE_flag", 11, 1 },
+		{ "BUS_RST_STATE_flag", 10, 1 },
+		{ "DL_DOWN_PCIeCRST_MODE0_STATE_flag", 9, 1 },
+		{ "DL_DOWN_PCIeCRST_MODE1_STATE_flag", 8, 1 },
+		{ "PCIe_WARM_RST_MODE0_STATE_flag", 7, 1 },
+		{ "PCIe_WARM_RST_MODE1_STATE_flag", 6, 1 },
+		{ "PIO_WARM_RST_MODE0_STATE_flag", 5, 1 },
+		{ "PIO_WARM_RST_MODE1_STATE_flag", 4, 1 },
+		{ "LastResetState", 0, 3 },
+	{ "PCIE_FUNC_DSTATE", 0x5ed0, 0 },
+		{ "PF7_DState", 21, 3 },
+		{ "PF6_DState", 18, 3 },
+		{ "PF5_DState", 15, 3 },
+		{ "PF4_DState", 12, 3 },
+		{ "PF3_DState", 9, 3 },
+		{ "PF2_DState", 6, 3 },
+		{ "PF1_DState", 3, 3 },
+		{ "PF0_DState", 0, 3 },
+	{ "PCIE_DEBUG_ADDR_RANGE1", 0x5ee0, 0 },
+	{ "PCIE_DEBUG_ADDR_RANGE2", 0x5ef0, 0 },
+	{ "PCIE_DEBUG_ADDR_RANGE_CNT", 0x5f00, 0 },
+	{ "PCIE_PHY_PGM_LOAD_CTRL", 0x5f04, 0 },
+		{ "HSS_PMLD_ACC_EN", 31, 1 },
+		{ "HSS_PmRdWr_Addr", 0, 18 },
+	{ "PCIE_PHY_PGM_LOAD_DATA", 0x5f08, 0 },
+	{ "PCIE_HSS_CFG", 0x5f0c, 0 },
+		{ "HSS_PCS_AGGREGATION_MODE", 30, 2 },
+		{ "HSS_PCS_FURCATE_MODE", 28, 2 },
+		{ "HSS_PCS_PCLK_ON_IN_P2", 27, 1 },
+		{ "HSS0_PHY_CTRL_REFCLK", 17, 5 },
+		{ "HSS1_PHY_CTRL_REFCLK", 12, 5 },
+		{ "HSS0_PHY_REXT_MASTER", 11, 1 },
+		{ "HSS1_PHY_REXT_MASTER", 10, 1 },
+		{ "HSS0_PHY_CTRL_VDDA_SEL", 9, 1 },
+		{ "HSS0_PHY_CTRL_VDDHA_SEL", 8, 1 },
+		{ "HSS1_PHY_CTRL_VDDA_SEL", 7, 1 },
+		{ "HSS1_PHY_CTRL_VDDHA_SEL", 6, 1 },
+		{ "HSS1_CPU_MEMPSACK", 5, 1 },
+		{ "HSS1_CPU_MEMACK", 4, 1 },
+		{ "HSS0_CPU_MEMPSACK", 3, 1 },
+		{ "HSS0_CPU_MEMACK", 2, 1 },
+		{ "HSS_PM_IS_ROM", 1, 1 },
+	{ "PCIE_HSS_RST", 0x5f10, 0 },
+		{ "HSS_RST_CTRL_BY_FW", 31, 1 },
+		{ "HSS_PIPE0_RESET_N", 30, 1 },
+		{ "HSS0_POR_N", 29, 1 },
+		{ "HSS1_POR_N", 28, 1 },
+		{ "HSS0_CPU_RESET", 27, 1 },
+		{ "HSS1_CPU_RESET", 26, 1 },
+		{ "HSS_PCS_POR_N", 25, 1 },
+		{ "SW_CRst_", 24, 1 },
+		{ "SW_PCIeCRst_", 23, 1 },
+		{ "SW_PCIePipeRst_", 22, 1 },
+		{ "SW_PCIePhyRst_", 21, 1 },
+		{ "HSS1_ERR_O", 3, 1 },
+		{ "HSS0_ERR_O", 2, 1 },
+		{ "HSS1_PLL_LOCK", 1, 1 },
+		{ "HSS0_PLL_LOCK", 0, 1 },
+	{ "PCIE_ARM_CFG", 0x5f20, 0 },
+		{ "MaxPyldSize", 28, 3 },
+		{ "MaxReqCnt", 20, 7 },
+		{ "MaxRdReqSize", 17, 3 },
+		{ "MaxRspCnt", 9, 8 },
+		{ "SeqChkDis", 8, 1 },
+		{ "MinTag", 0, 8 },
+	{ "PCIE_ARM_STAT", 0x5f24, 0 },
+		{ "RspCnt", 20, 9 },
+		{ "RdReqCnt", 12, 6 },
+		{ "WrReqCnt", 0, 9 },
+	{ "PCIE_ARM_STAT2", 0x5f28, 0 },
+		{ "CookieCnt", 24, 4 },
+		{ "RdSeqNumUpdCnt", 20, 4 },
+		{ "SIReqCnt", 16, 4 },
+		{ "WrEOPMatchSOP", 12, 1 },
+		{ "WrSOPCnt", 8, 4 },
+		{ "RdSOPCnt", 0, 8 },
+	{ "PCIE_ARM_STAT3", 0x5f2c, 0 },
+		{ "AtmReqSOPCnt", 24, 8 },
+		{ "AtmEOPMatchSOP", 17, 1 },
+		{ "RspEOPMatchSOP", 16, 1 },
+		{ "RspErrCnt", 8, 8 },
+		{ "RspSOPCnt", 0, 8 },
+	{ "PCIE_ARM_REQUESTER_ID", 0x5f30, 0 },
+		{ "PrimBusnumber", 16, 8 },
+		{ "RequesterId", 0, 16 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ0", 0x5f34, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 19, 1 },
+		{ "ByteEnable", 15, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA0", 0x5f38, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ1", 0x5f3c, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA1", 0x5f40, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ2", 0x5f44, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA2", 0x5f48, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ3", 0x5f4c, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA3", 0x5f50, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ4", 0x5f54, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA4", 0x5f58, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ5", 0x5f5c, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA5", 0x5f60, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ6", 0x5f64, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA6", 0x5f68, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ7", 0x5f6c, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA7", 0x5f70, 0 },
+	{ "PCIE_SWITCH_CFG_SPACE_REQ8", 0x5f74, 0 },
+		{ "ReqEnable", 31, 1 },
+		{ "RdReqType", 30, 1 },
+		{ "ByteEnable", 26, 4 },
+		{ "RegAddr", 0, 15 },
+	{ "PCIE_SWITCH_CFG_SPACE_DATA8", 0x5f78, 0 },
+	{ "PCIE_SNPS_G5_PHY_CR_REQ", 0x5f7c, 0 },
+		{ "RegSel", 31, 1 },
+		{ "RdEnable", 30, 1 },
+		{ "WrEnable", 29, 1 },
+		{ "AutoIncrVal", 21, 2 },
+		{ "AutoIncr", 20, 1 },
+		{ "PhySel", 16, 4 },
+		{ "RegAddr", 0, 16 },
+	{ "PCIE_SNPS_G5_PHY_CR_DATA", 0x5f80, 0 },
+	{ "PCIE_SNPS_G5_PHY_SRAM_CFG", 0x5f84, 0 },
+		{ "phy3_sram_bootload_bypass", 27, 1 },
+		{ "phy3_sram_bypass", 26, 1 },
+		{ "phy3_sram_ecc_en", 25, 1 },
+		{ "phy3_sram_ext_ld_done", 24, 1 },
+		{ "phy2_sram_bootload_bypass", 19, 1 },
+		{ "phy2_sram_bypass", 18, 1 },
+		{ "phy2_sram_ecc_en", 17, 1 },
+		{ "phy2_sram_ext_ld_done", 16, 1 },
+		{ "phy1_sram_bootload_bypass", 11, 1 },
+		{ "phy1_sram_bypass", 10, 1 },
+		{ "phy1_sram_ecc_en", 9, 1 },
+		{ "phy1_sram_ext_ld_done", 8, 1 },
+		{ "phy_cr_para_sel", 4, 4 },
+		{ "phy0_sram_bootload_bypass", 3, 1 },
+		{ "phy0_sram_bypass", 2, 1 },
+		{ "phy0_sram_ecc_en", 1, 1 },
+		{ "phy0_sram_ext_ld_done", 0, 1 },
+	{ "PCIE_SNPS_G5_PHY_SRAM_STS", 0x5f88, 0 },
+		{ "phy3_sram_init_done", 3, 1 },
+		{ "phy2_sram_init_done", 2, 1 },
+		{ "phy1_sram_init_done", 1, 1 },
+		{ "phy0_sram_init_done", 0, 1 },
+	{ "PCIE_SNPS_G5_PHY_CTRL_PHY_0_TO_3", 0x5f90, 0 },
+	{ "PCIE_SNPS_G5_PHY_CTRL_PHY_0_DATA", 0x5f94, 0 },
+	{ "PCIE_SNPS_G5_PHY_CTRL_PHY_1_DATA", 0x5f98, 0 },
+	{ "PCIE_SNPS_G5_PHY_CTRL_PHY_2_DATA", 0x5f9c, 0 },
+	{ "PCIE_SNPS_G5_PHY_CTRL_PHY_3_DATA", 0x5fa0, 0 },
+	{ "PCIE_SNPS_G5_PHY_DEFAULTS", 0x5fa4, 0 },
+	{ "PCIE_SNPS_G5_PHY_0_VALUES", 0x5fa8, 0 },
+		{ "rx_term_offset", 28, 1 },
+		{ "refb_raw_clk_div2_en", 27, 1 },
+		{ "refb_range", 23, 4 },
+		{ "refb_lane_clk_en", 22, 1 },
+		{ "refb_clk_div2_en", 21, 1 },
+		{ "refa_raw_clk_div2_en", 20, 1 },
+		{ "refa_range", 16, 4 },
+		{ "refa_lane_clk_en", 15, 1 },
+		{ "refa_clk_div2_en", 14, 1 },
+		{ "nominal_vph_sel", 10, 2 },
+		{ "nominal_vp_sel", 8, 2 },
+		{ "mpllb_word_clk_en", 7, 1 },
+		{ "mpllb_ssc_en", 6, 1 },
+		{ "mpllb_short_lock_en", 5, 1 },
+		{ "mpllb_force_en", 4, 1 },
+		{ "mplla_word_clk_en", 3, 1 },
+		{ "mplla_ssc_en", 2, 1 },
+		{ "mplla_short_lock_en", 1, 1 },
+		{ "mplla_force_en", 0, 1 },
+	{ "PCIE_SNPS_G5_PHY_1_VALUES", 0x5fac, 0 },
+		{ "rx_term_offset", 28, 1 },
+		{ "refb_raw_clk_div2_en", 27, 1 },
+		{ "refb_range", 23, 4 },
+		{ "refb_lane_clk_en", 22, 1 },
+		{ "refb_clk_div2_en", 21, 1 },
+		{ "refa_raw_clk_div2_en", 20, 1 },
+		{ "refa_range", 16, 4 },
+		{ "refa_lane_clk_en", 15, 1 },
+		{ "refa_clk_div2_en", 14, 1 },
+		{ "ref_alt1_clk_m", 13, 1 },
+		{ "ref_alt1_clk_p", 12, 1 },
+		{ "nominal_vph_sel", 10, 2 },
+		{ "nominal_vp_sel", 8, 2 },
+		{ "mpllb_word_clk_en", 7, 1 },
+		{ "mpllb_ssc_en", 6, 1 },
+		{ "mpllb_short_lock_en", 5, 1 },
+		{ "mpllb_force_en", 4, 1 },
+		{ "mplla_word_clk_en", 3, 1 },
+		{ "mplla_ssc_en", 2, 1 },
+		{ "mplla_short_lock_en", 1, 1 },
+		{ "mplla_force_en", 0, 1 },
+	{ "PCIE_SNPS_G5_PHY_2_VALUES", 0x5fb0, 0 },
+		{ "rx_term_offset", 28, 1 },
+		{ "refb_raw_clk_div2_en", 27, 1 },
+		{ "refb_range", 23, 4 },
+		{ "refb_lane_clk_en", 22, 1 },
+		{ "refb_clk_div2_en", 21, 1 },
+		{ "refa_raw_clk_div2_en", 20, 1 },
+		{ "refa_range", 16, 4 },
+		{ "refa_lane_clk_en", 15, 1 },
+		{ "refa_clk_div2_en", 14, 1 },
+		{ "ref_alt1_clk_m", 13, 1 },
+		{ "ref_alt1_clk_p", 12, 1 },
+		{ "nominal_vph_sel", 10, 2 },
+		{ "nominal_vp_sel", 8, 2 },
+		{ "mpllb_word_clk_en", 7, 1 },
+		{ "mpllb_ssc_en", 6, 1 },
+		{ "mpllb_short_lock_en", 5, 1 },
+		{ "mpllb_force_en", 4, 1 },
+		{ "mplla_word_clk_en", 3, 1 },
+		{ "mplla_ssc_en", 2, 1 },
+		{ "mplla_short_lock_en", 1, 1 },
+		{ "mplla_force_en", 0, 1 },
+	{ "PCIE_SNPS_G5_PHY_3_VALUES", 0x5fb4, 0 },
+		{ "rx_term_offset", 28, 1 },
+		{ "refb_raw_clk_div2_en", 27, 1 },
+		{ "refb_range", 23, 4 },
+		{ "refb_lane_clk_en", 22, 1 },
+		{ "refb_clk_div2_en", 21, 1 },
+		{ "refa_raw_clk_div2_en", 20, 1 },
+		{ "refa_range", 16, 4 },
+		{ "refa_lane_clk_en", 15, 1 },
+		{ "refa_clk_div2_en", 14, 1 },
+		{ "ref_alt1_clk_m", 13, 1 },
+		{ "ref_alt1_clk_p", 12, 1 },
+		{ "nominal_vph_sel", 10, 2 },
+		{ "nominal_vp_sel", 8, 2 },
+		{ "mpllb_word_clk_en", 7, 1 },
+		{ "mpllb_ssc_en", 6, 1 },
+		{ "mpllb_short_lock_en", 5, 1 },
+		{ "mpllb_force_en", 4, 1 },
+		{ "mplla_word_clk_en", 3, 1 },
+		{ "mplla_ssc_en", 2, 1 },
+		{ "mplla_short_lock_en", 1, 1 },
+		{ "mplla_force_en", 0, 1 },
+	{ "PCIE_SNPS_G5_PHY_0_RX_LANEPLL_BYPASS_MODE", 0x5fb8, 0 },
+		{ "lane3", 15, 5 },
+		{ "lane2", 10, 5 },
+		{ "lane1", 5, 5 },
+		{ "lane0", 0, 5 },
+	{ "PCIE_SNPS_G5_PHY_1_RX_LANEPLL_BYPASS_MODE", 0x5fbc, 0 },
+		{ "lane3", 15, 5 },
+		{ "lane2", 10, 5 },
+		{ "lane1", 5, 5 },
+		{ "lane0", 0, 5 },
+	{ "PCIE_SNPS_G5_PHY_2_RX_LANEPLL_BYPASS_MODE", 0x5fc0, 0 },
+		{ "lane3", 15, 5 },
+		{ "lane2", 10, 5 },
+		{ "lane1", 5, 5 },
+		{ "lane0", 0, 5 },
+	{ "PCIE_SNPS_G5_PHY_3_RX_LANEPLL_BYPASS_MODE", 0x5fc4, 0 },
+		{ "lane3", 15, 5 },
+		{ "lane2", 10, 5 },
+		{ "lane1", 5, 5 },
+		{ "lane0", 0, 5 },
+	{ "PCIE_SNPS_G5_PHY_0_1_RX_LANEPLL_SRC_SEL", 0x5fc8, 0 },
+		{ "lane7_lanepll_src_sel", 28, 4 },
+		{ "lane6_lanepll_src_sel", 24, 4 },
+		{ "lane5_lanepll_src_sel", 20, 4 },
+		{ "lane4_lanepll_src_sel", 16, 4 },
+		{ "lane3_lanepll_src_sel", 12, 4 },
+		{ "lane2_lanepll_src_sel", 8, 4 },
+		{ "lane1_lanepll_src_sel", 4, 4 },
+		{ "lane0_lanepll_src_sel", 0, 4 },
+	{ "PCIE_SNPS_G5_PHY_2_3_RX_LANEPLL_SRC_SEL", 0x5fcc, 0 },
+		{ "lane7_lanepll_src_sel", 28, 4 },
+		{ "lane6_lanepll_src_sel", 24, 4 },
+		{ "lane5_lanepll_src_sel", 20, 4 },
+		{ "lane4_lanepll_src_sel", 16, 4 },
+		{ "lane3_lanepll_src_sel", 12, 4 },
+		{ "lane2_lanepll_src_sel", 8, 4 },
+		{ "lane1_lanepll_src_sel", 4, 4 },
+		{ "lane0_lanepll_src_sel", 0, 4 },
+	{ "PCIE_SNPS_G5_PHY_RX_DECERR", 0x5fd0, 0 },
+		{ "lane15_rec_ovrd_8b10b_decerr", 30, 2 },
+		{ "lane14_rec_ovrd_8b10b_decerr", 28, 2 },
+		{ "lane13_rec_ovrd_8b10b_decerr", 26, 2 },
+		{ "lane12_rec_ovrd_8b10b_decerr", 24, 2 },
+		{ "lane11_rec_ovrd_8b10b_decerr", 22, 2 },
+		{ "lane10_rec_ovrd_8b10b_decerr", 20, 2 },
+		{ "lane9_rec_ovrd_8b10b_decerr", 18, 2 },
+		{ "lane8_rec_ovrd_8b10b_decerr", 16, 2 },
+		{ "lane7_rec_ovrd_8b10b_decerr", 14, 2 },
+		{ "lane6_rec_ovrd_8b10b_decerr", 12, 2 },
+		{ "lane5_rec_ovrd_8b10b_decerr", 10, 2 },
+		{ "lane4_rec_ovrd_8b10b_decerr", 8, 2 },
+		{ "lane3_rec_ovrd_8b10b_decerr", 6, 2 },
+		{ "lane2_rec_ovrd_8b10b_decerr", 4, 2 },
+		{ "lane1_rec_ovrd_8b10b_decerr", 2, 2 },
+		{ "lane0_rec_ovrd_8b10b_decerr", 0, 2 },
+	{ "PCIE_SNPS_G5_PHY_TX2RX_LOOPBK_REC_OVRD_EN", 0x5fd4, 0 },
+		{ "lane15_rec_ovrd_en", 31, 1 },
+		{ "lane14_rec_ovrd_en", 30, 1 },
+		{ "lane13_rec_ovrd_en", 29, 1 },
+		{ "lane12_rec_ovrd_en", 28, 1 },
+		{ "lane11_rec_ovrd_en", 27, 1 },
+		{ "lane10_rec_ovrd_en", 26, 1 },
+		{ "lane9_rec_ovrd_en", 25, 1 },
+		{ "lane8_rec_ovrd_en", 24, 1 },
+		{ "lane7_rec_ovrd_en", 23, 1 },
+		{ "lane6_rec_ovrd_en", 22, 1 },
+		{ "lane5_rec_ovrd_en", 21, 1 },
+		{ "lane4_rec_ovrd_en", 20, 1 },
+		{ "lane3_rec_ovrd_en", 19, 1 },
+		{ "lane2_rec_ovrd_en", 18, 1 },
+		{ "lane1_rec_ovrd_en", 17, 1 },
+		{ "lane0_rec_ovrd_en", 16, 1 },
+		{ "lane15_tx2rx_loopbk", 15, 1 },
+		{ "lane14_tx2rx_loopbk", 14, 1 },
+		{ "lane13_tx2rx_loopbk", 13, 1 },
+		{ "lane12_tx2rx_loopbk", 12, 1 },
+		{ "lane11_tx2rx_loopbk", 11, 1 },
+		{ "lane10_tx2rx_loopbk", 10, 1 },
+		{ "lane9_tx2rx_loopbk", 9, 1 },
+		{ "lane8_tx2rx_loopbk", 8, 1 },
+		{ "lane7_tx2rx_loopbk", 7, 1 },
+		{ "lane6_tx2rx_loopbk", 6, 1 },
+		{ "lane5_tx2rx_loopbk", 5, 1 },
+		{ "lane4_tx2rx_loopbk", 4, 1 },
+		{ "lane3_tx2rx_loopbk", 3, 1 },
+		{ "lane2_tx2rx_loopbk", 2, 1 },
+		{ "lane1_tx2rx_loopbk", 1, 1 },
+		{ "lane0_tx2rx_loopbk", 0, 1 },
+	{ "PCIE_PHY_TX_DISABLE_UPCS_PIPE_CONFIG", 0x5fd8, 0 },
+		{ "upcs_pipe_config", 16, 16 },
+		{ "tx15_disable", 15, 1 },
+		{ "tx14_disable", 14, 1 },
+		{ "tx13_disable", 13, 1 },
+		{ "tx12_disable", 12, 1 },
+		{ "tx11_disable", 11, 1 },
+		{ "tx10_disable", 10, 1 },
+		{ "tx9_disable", 9, 1 },
+		{ "tx8_disable", 8, 1 },
+		{ "tx7_disable", 7, 1 },
+		{ "tx6_disable", 6, 1 },
+		{ "tx5_disable", 5, 1 },
+		{ "tx4_disable", 4, 1 },
+		{ "tx3_disable", 3, 1 },
+		{ "tx2_disable", 2, 1 },
+		{ "tx1_disable", 1, 1 },
+		{ "tx0_disable", 0, 1 },
+	{ "PCIE_PIPE_LANE0_REG0", 0x5500, 0 },
+	{ "PCIE_PIPE_LANE0_REG1", 0x5504, 0 },
+	{ "PCIE_PIPE_LANE0_REG2", 0x5508, 0 },
+	{ "PCIE_PIPE_LANE0_REG3", 0x550c, 0 },
+	{ "PCIE_PIPE_LANE1_REG0", 0x5510, 0 },
+	{ "PCIE_PIPE_LANE1_REG1", 0x5514, 0 },
+	{ "PCIE_PIPE_LANE1_REG2", 0x5518, 0 },
+	{ "PCIE_PIPE_LANE1_REG3", 0x551c, 0 },
+	{ "PCIE_PIPE_LANE2_REG0", 0x5520, 0 },
+	{ "PCIE_PIPE_LANE2_REG1", 0x5524, 0 },
+	{ "PCIE_PIPE_LANE2_REG2", 0x5528, 0 },
+	{ "PCIE_PIPE_LANE2_REG3", 0x552c, 0 },
+	{ "PCIE_PIPE_LANE3_REG0", 0x5530, 0 },
+	{ "PCIE_PIPE_LANE3_REG1", 0x5534, 0 },
+	{ "PCIE_PIPE_LANE3_REG2", 0x5538, 0 },
+	{ "PCIE_PIPE_LANE3_REG3", 0x553c, 0 },
+	{ "PCIE_PIPE_LANE4_REG0", 0x5540, 0 },
+	{ "PCIE_PIPE_LANE4_REG1", 0x5544, 0 },
+	{ "PCIE_PIPE_LANE4_REG2", 0x5548, 0 },
+	{ "PCIE_PIPE_LANE4_REG3", 0x554c, 0 },
+	{ "PCIE_PIPE_LANE5_REG0", 0x5550, 0 },
+	{ "PCIE_PIPE_LANE5_REG1", 0x5554, 0 },
+	{ "PCIE_PIPE_LANE5_REG2", 0x5558, 0 },
+	{ "PCIE_PIPE_LANE5_REG3", 0x555c, 0 },
+	{ "PCIE_PIPE_LANE6_REG0", 0x5560, 0 },
+	{ "PCIE_PIPE_LANE6_REG1", 0x5564, 0 },
+	{ "PCIE_PIPE_LANE6_REG2", 0x5568, 0 },
+	{ "PCIE_PIPE_LANE6_REG3", 0x556c, 0 },
+	{ "PCIE_PIPE_LANE7_REG0", 0x5570, 0 },
+	{ "PCIE_PIPE_LANE7_REG1", 0x5574, 0 },
+	{ "PCIE_PIPE_LANE7_REG2", 0x5578, 0 },
+	{ "PCIE_PIPE_LANE7_REG3", 0x557c, 0 },
+	{ "PCIE_PIPE_LANE8_REG0", 0x5580, 0 },
+	{ "PCIE_PIPE_LANE8_REG1", 0x5584, 0 },
+	{ "PCIE_PIPE_LANE8_REG2", 0x5588, 0 },
+	{ "PCIE_PIPE_LANE8_REG3", 0x558c, 0 },
+	{ "PCIE_PIPE_LANE9_REG0", 0x5590, 0 },
+	{ "PCIE_PIPE_LANE9_REG1", 0x5594, 0 },
+	{ "PCIE_PIPE_LANE9_REG2", 0x5598, 0 },
+	{ "PCIE_PIPE_LANE9_REG3", 0x559c, 0 },
+	{ "PCIE_PIPE_LANE10_REG0", 0x55a0, 0 },
+	{ "PCIE_PIPE_LANE10_REG1", 0x55a4, 0 },
+	{ "PCIE_PIPE_LANE10_REG2", 0x55a8, 0 },
+	{ "PCIE_PIPE_LANE10_REG3", 0x55ac, 0 },
+	{ "PCIE_PIPE_LANE11_REG0", 0x55b0, 0 },
+	{ "PCIE_PIPE_LANE11_REG1", 0x55b4, 0 },
+	{ "PCIE_PIPE_LANE11_REG2", 0x55b8, 0 },
+	{ "PCIE_PIPE_LANE11_REG3", 0x55bc, 0 },
+	{ "PCIE_PIPE_LANE12_REG0", 0x55c0, 0 },
+	{ "PCIE_PIPE_LANE12_REG1", 0x55c4, 0 },
+	{ "PCIE_PIPE_LANE12_REG2", 0x55c8, 0 },
+	{ "PCIE_PIPE_LANE12_REG3", 0x55cc, 0 },
+	{ "PCIE_PIPE_LANE13_REG0", 0x55d0, 0 },
+	{ "PCIE_PIPE_LANE13_REG1", 0x55d4, 0 },
+	{ "PCIE_PIPE_LANE13_REG2", 0x55d8, 0 },
+	{ "PCIE_PIPE_LANE13_REG3", 0x55dc, 0 },
+	{ "PCIE_PIPE_LANE14_REG0", 0x55e0, 0 },
+	{ "PCIE_PIPE_LANE14_REG1", 0x55e4, 0 },
+	{ "PCIE_PIPE_LANE14_REG2", 0x55e8, 0 },
+	{ "PCIE_PIPE_LANE14_REG3", 0x55ec, 0 },
+	{ "PCIE_PIPE_LANE15_REG0", 0x55f0, 0 },
+	{ "PCIE_PIPE_LANE15_REG1", 0x55f4, 0 },
+	{ "PCIE_PIPE_LANE15_REG2", 0x55f8, 0 },
+	{ "PCIE_PIPE_LANE15_REG3", 0x55fc, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3600, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3604, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3608, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x360c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3610, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3614, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3618, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x361c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3620, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3624, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3628, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x362c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3630, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3634, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3638, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x363c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3640, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3644, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3648, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x364c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3650, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3654, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3658, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x365c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3660, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3664, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3668, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x366c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3670, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3674, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3678, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x367c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3680, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3684, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3688, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x368c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x3690, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x3694, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x3698, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x369c, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x36a0, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x36a4, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x36a8, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x36ac, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x36b0, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x36b4, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x36b8, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x36bc, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x36c0, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x36c4, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x36c8, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x36cc, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x36d0, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x36d4, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x36d8, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x36dc, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x36e0, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x36e4, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x36e8, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x36ec, 0 },
+	{ "PCIE_JBOF_NVME_HIGH_DW_START_ADDR", 0x36f0, 0 },
+	{ "PCIE_JBOF_NVME_LOW_DW_START_ADDR", 0x36f4, 0 },
+	{ "PCIE_JBOF_NVME_LENGTH", 0x36f8, 0 },
+		{ "NVMeDisable", 31, 1 },
+		{ "NVMeLength", 0, 30 },
+	{ "PCIE_JBOF_NVME_GROUP", 0x36fc, 0 },
+	{ "PCIE_PTM_EP_EXT_STROBE", 0x3804, 0 },
+		{ "ptm_auto_update", 1, 1 },
+		{ "ptm_ext_strobe", 0, 1 },
+	{ "PCIE_PTM_EP_EXT_TIME0", 0x3808, 0 },
+	{ "PCIE_PTM_EP_EXT_TIME1", 0x380c, 0 },
+	{ "PCIE_PTM_MAN_UPD_PULSE", 0x3810, 0 },
+	{ "PCIE_SWAP_DATA_B2L_X16", 0x3814, 0 },
+		{ "cfgrd_swap_en", 1, 1 },
+		{ "cfgwr_swap_en", 0, 1 },
+	{ "PCIE_PCIE_RC_RST", 0x3818, 0 },
+	{ "PCIE_PCIE_LN_CLKSEL", 0x3880, 0 },
+		{ "ds8_sel", 30, 2 },
+		{ "ds7_sel", 28, 2 },
+		{ "ds6_sel", 26, 2 },
+		{ "ds5_sel", 24, 2 },
+		{ "ds4_sel", 22, 2 },
+		{ "ds3_sel", 20, 2 },
+		{ "ds2_sel", 18, 2 },
+		{ "ds1_sel", 16, 2 },
+		{ "ln14_sel", 14, 2 },
+		{ "ln12_sel", 12, 2 },
+		{ "ln10_sel", 10, 2 },
+		{ "ln8_sel", 8, 2 },
+		{ "ln6_sel", 6, 2 },
+		{ "ln4_sel", 4, 2 },
+		{ "ln2_sel", 2, 2 },
+		{ "ln0_sel", 0, 2 },
+	{ "PCIE_PCIE_MSIX_EN", 0x3884, 0 },
+	{ "PCIE_LFSR_WRCTRL", 0x3888, 0 },
+		{ "wr_lfsr_cmp_data", 16, 16 },
+		{ "wr_lfsr_rsvd", 2, 14 },
+		{ "wr_lfsr_en", 1, 1 },
+		{ "wr_lfsr_start", 0, 1 },
+	{ "PCIE_LFSR_RDCTRL", 0x388c, 0 },
+		{ "cmd_lfsr_cmp_data", 24, 8 },
+		{ "rd_lfsr_cmd_data", 16, 8 },
+		{ "rd_lfsr_rsvd", 10, 6 },
+		{ "rd3_lfsr_en", 9, 1 },
+		{ "rd3_lfsr_start", 8, 1 },
+		{ "rd2_lfsr_en", 7, 1 },
+		{ "rd2_lfsr_start", 6, 1 },
+		{ "rd1_lfsr_en", 5, 1 },
+		{ "rd1_lfsr_start", 4, 1 },
+		{ "rd0_lfsr_en", 3, 1 },
+		{ "rd0_lfsr_start", 2, 1 },
+		{ "cmd_lfsr_en", 1, 1 },
+		{ "cmd_lfsr_start", 0, 1 },
+	{ "PCIE_EMU_ADDR", 0x3900, 0 },
+	{ "PCIE_EMU_CFG", 0x3904, 0 },
+		{ "EmuEnable", 16, 1 },
+		{ "EmuType", 14, 2 },
+		{ "BAR0Target", 12, 2 },
+		{ "BAR2Target", 10, 2 },
+		{ "BAR4Target", 8, 2 },
+		{ "ReleativeEmuID", 0, 8 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0", 0x3910, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG0_BAR0", 0x3914, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0", 0x3918, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG1_BAR0", 0x391c, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0", 0x3920, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG2_BAR0", 0x3924, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0", 0x3928, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG3_BAR0", 0x392c, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0", 0x3930, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG0_BAR0", 0x3934, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0", 0x3938, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG1_BAR0", 0x393c, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0", 0x3940, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG2_BAR0", 0x3944, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0", 0x3948, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG3_BAR0", 0x394c, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0", 0x3950, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG0_BAR0", 0x3954, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0", 0x3958, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG1_BAR0", 0x395c, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0", 0x3960, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG2_BAR0", 0x3964, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0", 0x3968, 0 },
+	{ "PCIE_EMUADRRMAP_MEM_CFG3_BAR0", 0x396c, 0 },
+	{ "PCIE_TCAM_DATA", 0x3970, 0 },
+	{ "PCIE_TCAM_CTL", 0x3974, 0 },
+		{ "TcamAddr", 8, 10 },
+		{ "CamEn", 0, 1 },
+	{ "PCIE_TCAM_DBG", 0x3978, 0 },
+		{ "CbPass", 24, 1 },
+		{ "CbBusy", 20, 1 },
+		{ "CbStart", 17, 1 },
+		{ "RstCb", 16, 1 },
+		{ "tcam_dbg_data", 0, 16 },
+	{ "PCIE_TEST_CTRL0", 0x3980, 0 },
+	{ "PCIE_TEST_CTRL1", 0x3984, 0 },
+	{ "PCIE_TEST_CTRL2", 0x3988, 0 },
+	{ "PCIE_TEST_CTRL3", 0x398c, 0 },
+	{ "PCIE_TEST_STS0", 0x3990, 0 },
+	{ "PCIE_TEST_STS1", 0x3994, 0 },
+	{ "PCIE_TEST_STS2", 0x3998, 0 },
+	{ "PCIE_TEST_STS3", 0x399c, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_dbg_regs[] = {
+	{ "DBG_DBG0_CFG", 0x6000, 0 },
+		{ "ModuleSelect", 12, 8 },
+		{ "RegSelect", 4, 8 },
+		{ "ClkSelect", 0, 4 },
+	{ "DBG_DBG0_EN", 0x6004, 0 },
+		{ "SDRHalfWord0", 8, 1 },
+		{ "DDREn", 4, 1 },
+		{ "PortEn", 0, 1 },
+	{ "DBG_DBG1_CFG", 0x6008, 0 },
+		{ "ModuleSelect", 12, 8 },
+		{ "RegSelect", 4, 8 },
+		{ "ClkSelect", 0, 4 },
+	{ "DBG_DBG1_EN", 0x600c, 0 },
+		{ "Clk_en_on_dbg1", 20, 1 },
+		{ "SDRHalfWord0", 8, 1 },
+		{ "DDREn", 4, 1 },
+		{ "PortEn", 0, 1 },
+	{ "DBG_GPIO_OUT", 0x6010, 0 },
+		{ "GPIO23_Out_Val", 23, 1 },
+		{ "GPIO22_Out_Val", 22, 1 },
+		{ "GPIO21_Out_Val", 21, 1 },
+		{ "GPIO20_Out_Val", 20, 1 },
+		{ "GPIO19_Out_Val", 19, 1 },
+		{ "GPIO18_Out_Val", 18, 1 },
+		{ "GPIO17_Out_Val", 17, 1 },
+		{ "GPIO16_Out_Val", 16, 1 },
+		{ "GPIO15_Out_Val", 15, 1 },
+		{ "GPIO14_Out_Val", 14, 1 },
+		{ "GPIO13_Out_Val", 13, 1 },
+		{ "GPIO12_Out_Val", 12, 1 },
+		{ "GPIO11_Out_Val", 11, 1 },
+		{ "GPIO10_Out_Val", 10, 1 },
+		{ "GPIO9_Out_Val", 9, 1 },
+		{ "GPIO8_Out_Val", 8, 1 },
+		{ "GPIO7_Out_Val", 7, 1 },
+		{ "GPIO6_Out_Val", 6, 1 },
+		{ "GPIO5_Out_Val", 5, 1 },
+		{ "GPIO4_Out_Val", 4, 1 },
+		{ "GPIO3_Out_Val", 3, 1 },
+		{ "GPIO2_Out_Val", 2, 1 },
+		{ "GPIO1_Out_Val", 1, 1 },
+		{ "GPIO0_Out_Val", 0, 1 },
+	{ "DBG_GPIO_IN", 0x6014, 0 },
+		{ "GPIO23_IN", 23, 1 },
+		{ "GPIO22_IN", 22, 1 },
+		{ "GPIO21_IN", 21, 1 },
+		{ "GPIO20_IN", 20, 1 },
+		{ "GPIO19_IN", 19, 1 },
+		{ "GPIO18_IN", 18, 1 },
+		{ "GPIO17_IN", 17, 1 },
+		{ "GPIO16_IN", 16, 1 },
+		{ "GPIO15_IN", 15, 1 },
+		{ "GPIO14_IN", 14, 1 },
+		{ "GPIO13_IN", 13, 1 },
+		{ "GPIO12_IN", 12, 1 },
+		{ "GPIO11_IN", 11, 1 },
+		{ "GPIO10_IN", 10, 1 },
+		{ "GPIO9_IN", 9, 1 },
+		{ "GPIO8_IN", 8, 1 },
+		{ "GPIO7_IN", 7, 1 },
+		{ "GPIO6_IN", 6, 1 },
+		{ "GPIO5_IN", 5, 1 },
+		{ "GPIO4_IN", 4, 1 },
+		{ "GPIO3_IN", 3, 1 },
+		{ "GPIO2_IN", 2, 1 },
+		{ "GPIO1_IN", 1, 1 },
+		{ "GPIO0_IN", 0, 1 },
+	{ "DBG_GPIO_OEN", 0x6100, 0 },
+		{ "GPIO23_OEn", 23, 1 },
+		{ "GPIO22_OEn", 22, 1 },
+		{ "GPIO21_OEn", 21, 1 },
+		{ "GPIO20_OEn", 20, 1 },
+		{ "GPIO19_OEn", 19, 1 },
+		{ "GPIO18_OEn", 18, 1 },
+		{ "GPIO17_OEn", 17, 1 },
+		{ "GPIO16_OEn", 16, 1 },
+		{ "GPIO15_OEn", 15, 1 },
+		{ "GPIO14_OEn", 14, 1 },
+		{ "GPIO13_OEn", 13, 1 },
+		{ "GPIO12_OEn", 12, 1 },
+		{ "GPIO11_OEn", 11, 1 },
+		{ "GPIO10_OEn", 10, 1 },
+		{ "GPIO9_OEn", 9, 1 },
+		{ "GPIO8_OEn", 8, 1 },
+		{ "GPIO7_OEn", 7, 1 },
+		{ "GPIO6_OEn", 6, 1 },
+		{ "GPIO5_OEn", 5, 1 },
+		{ "GPIO4_OEn", 4, 1 },
+		{ "GPIO3_OEn", 3, 1 },
+		{ "GPIO2_OEn", 2, 1 },
+		{ "GPIO1_OEn", 1, 1 },
+		{ "GPIO0_OEn", 0, 1 },
+	{ "DBG_GPIO_CHG_DET", 0x6104, 0 },
+		{ "GPIO23_CHG_DET", 23, 1 },
+		{ "GPIO22_CHG_DET", 22, 1 },
+		{ "GPIO21_CHG_DET", 21, 1 },
+		{ "GPIO20_CHG_DET", 20, 1 },
+		{ "GPIO19_CHG_DET", 19, 1 },
+		{ "GPIO18_CHG_DET", 18, 1 },
+		{ "GPIO17_CHG_DET", 17, 1 },
+		{ "GPIO16_CHG_DET", 16, 1 },
+		{ "GPIO15_CHG_DET", 15, 1 },
+		{ "GPIO14_CHG_DET", 14, 1 },
+		{ "GPIO13_CHG_DET", 13, 1 },
+		{ "GPIO12_CHG_DET", 12, 1 },
+		{ "GPIO11_CHG_DET", 11, 1 },
+		{ "GPIO10_CHG_DET", 10, 1 },
+		{ "GPIO9_CHG_DET", 9, 1 },
+		{ "GPIO8_CHG_DET", 8, 1 },
+		{ "GPIO7_CHG_DET", 7, 1 },
+		{ "GPIO6_CHG_DET", 6, 1 },
+		{ "GPIO5_CHG_DET", 5, 1 },
+		{ "GPIO4_CHG_DET", 4, 1 },
+		{ "GPIO3_CHG_DET", 3, 1 },
+		{ "GPIO2_CHG_DET", 2, 1 },
+		{ "GPIO1_CHG_DET", 1, 1 },
+		{ "GPIO0_CHG_DET", 0, 1 },
+	{ "DBG_INT_ENABLE", 0x6018, 0 },
+		{ "USBFifoParErr", 12, 1 },
+		{ "IBM_FDL_FAIL_int_enbl", 11, 1 },
+		{ "pll_lock_lost_int_enbl", 10, 1 },
+		{ "M1_LOCK", 9, 1 },
+		{ "PCIE_LOCK", 8, 1 },
+		{ "U_LOCK", 7, 1 },
+		{ "MAC_LOCK", 6, 1 },
+		{ "ARM_LOCK", 5, 1 },
+		{ "M0_LOCK", 4, 1 },
+		{ "XGPBUS_LOCK", 3, 1 },
+		{ "XGPHY_LOCK", 2, 1 },
+		{ "USB_LOCK", 1, 1 },
+		{ "C_LOCK", 0, 1 },
+	{ "DBG_INT_CAUSE", 0x601c, 0 },
+		{ "USBFifoParErr", 12, 1 },
+		{ "IBM_FDL_FAIL_int_cause", 11, 1 },
+		{ "pll_lock_lost_int_cause", 10, 1 },
+		{ "M1_LOCK", 9, 1 },
+		{ "PCIE_LOCK", 8, 1 },
+		{ "U_LOCK", 7, 1 },
+		{ "MAC_LOCK", 6, 1 },
+		{ "ARM_LOCK", 5, 1 },
+		{ "M0_LOCK", 4, 1 },
+		{ "XGPBUS_LOCK", 3, 1 },
+		{ "XGPHY_LOCK", 2, 1 },
+		{ "USB_LOCK", 1, 1 },
+		{ "C_LOCK", 0, 1 },
+	{ "DBG_GPIO_INT_ENABLE", 0x6180, 0 },
+		{ "GPIO23", 23, 1 },
+		{ "GPIO22", 22, 1 },
+		{ "GPIO21", 21, 1 },
+		{ "GPIO20", 20, 1 },
+		{ "GPIO19", 19, 1 },
+		{ "GPIO18", 18, 1 },
+		{ "GPIO17", 17, 1 },
+		{ "GPIO16", 16, 1 },
+		{ "GPIO15", 15, 1 },
+		{ "GPIO14", 14, 1 },
+		{ "GPIO13", 13, 1 },
+		{ "GPIO12", 12, 1 },
+		{ "GPIO11", 11, 1 },
+		{ "GPIO10", 10, 1 },
+		{ "GPIO9", 9, 1 },
+		{ "GPIO8", 8, 1 },
+		{ "GPIO7", 7, 1 },
+		{ "GPIO6", 6, 1 },
+		{ "GPIO5", 5, 1 },
+		{ "GPIO4", 4, 1 },
+		{ "GPIO3", 3, 1 },
+		{ "GPIO2", 2, 1 },
+		{ "GPIO1", 1, 1 },
+		{ "GPIO0", 0, 1 },
+	{ "DBG_GPIO_INT_CAUSE", 0x6184, 0 },
+		{ "GPIO23", 23, 1 },
+		{ "GPIO22", 22, 1 },
+		{ "GPIO21", 21, 1 },
+		{ "GPIO20", 20, 1 },
+		{ "GPIO19", 19, 1 },
+		{ "GPIO18", 18, 1 },
+		{ "GPIO17", 17, 1 },
+		{ "GPIO16", 16, 1 },
+		{ "GPIO15", 15, 1 },
+		{ "GPIO14", 14, 1 },
+		{ "GPIO13", 13, 1 },
+		{ "GPIO12", 12, 1 },
+		{ "GPIO11", 11, 1 },
+		{ "GPIO10", 10, 1 },
+		{ "GPIO9", 9, 1 },
+		{ "GPIO8", 8, 1 },
+		{ "GPIO7", 7, 1 },
+		{ "GPIO6", 6, 1 },
+		{ "GPIO5", 5, 1 },
+		{ "GPIO4", 4, 1 },
+		{ "GPIO3", 3, 1 },
+		{ "GPIO2", 2, 1 },
+		{ "GPIO1", 1, 1 },
+		{ "GPIO0", 0, 1 },
+	{ "DBG_GPIO_ACT_LOW", 0x6188, 0 },
+		{ "GPIO23_ACT_LOW", 23, 1 },
+		{ "GPIO22_ACT_LOW", 22, 1 },
+		{ "GPIO21_ACT_LOW", 21, 1 },
+		{ "GPIO20_ACT_LOW", 20, 1 },
+		{ "GPIO19_ACT_LOW", 19, 1 },
+		{ "GPIO18_ACT_LOW", 18, 1 },
+		{ "GPIO17_ACT_LOW", 17, 1 },
+		{ "GPIO16_ACT_LOW", 16, 1 },
+		{ "GPIO15_ACT_LOW", 15, 1 },
+		{ "GPIO14_ACT_LOW", 14, 1 },
+		{ "GPIO13_ACT_LOW", 13, 1 },
+		{ "GPIO12_ACT_LOW", 12, 1 },
+		{ "GPIO11_ACT_LOW", 11, 1 },
+		{ "GPIO10_ACT_LOW", 10, 1 },
+		{ "GPIO9_ACT_LOW", 9, 1 },
+		{ "GPIO8_ACT_LOW", 8, 1 },
+		{ "GPIO7_ACT_LOW", 7, 1 },
+		{ "GPIO6_ACT_LOW", 6, 1 },
+		{ "GPIO5_ACT_LOW", 5, 1 },
+		{ "GPIO4_ACT_LOW", 4, 1 },
+		{ "GPIO3_ACT_LOW", 3, 1 },
+		{ "GPIO2_ACT_LOW", 2, 1 },
+		{ "GPIO1_ACT_LOW", 1, 1 },
+		{ "GPIO0_ACT_LOW", 0, 1 },
+	{ "DBG_DDR_CAL", 0x618c, 0 },
+		{ "CAL_ENDC", 9, 1 },
+		{ "CAL_MODE", 8, 1 },
+		{ "CAL_REFSEL", 7, 1 },
+		{ "PD", 6, 1 },
+		{ "CAL_RST", 5, 1 },
+		{ "CAL_READ", 4, 1 },
+		{ "CAL_SC", 3, 1 },
+		{ "CAL_LC", 2, 1 },
+		{ "CAL_CCAL", 1, 1 },
+		{ "CAL_RES", 0, 1 },
+	{ "DBG_EFUSE_CTL_0", 0x6190, 0 },
+		{ "EFUSE_CSB", 31, 1 },
+		{ "EFUSE_STROBE", 30, 1 },
+		{ "EFUSE_LOAD", 29, 1 },
+		{ "EFUSE_PGENB", 28, 1 },
+		{ "EFUSE_PS", 27, 1 },
+		{ "EFUSE_MR", 26, 1 },
+		{ "EFUSE_PD", 25, 1 },
+		{ "EFUSE_RWL", 24, 1 },
+		{ "EFUSE_RSB", 23, 1 },
+		{ "EFUSE_TRCS", 22, 1 },
+		{ "EFUSE_AT", 20, 2 },
+		{ "EFUSE_RD_STATE", 16, 4 },
+		{ "EFUSE_BUSY", 15, 1 },
+		{ "EFUSE_WR_RD", 13, 2 },
+		{ "EFUSE_A", 0, 11 },
+	{ "DBG_EFUSE_CTL_1", 0x6194, 0 },
+		{ "EFUSE_CSB", 31, 1 },
+		{ "EFUSE_STROBE", 30, 1 },
+		{ "EFUSE_LOAD", 29, 1 },
+		{ "EFUSE_PGENB", 28, 1 },
+		{ "EFUSE_PS", 27, 1 },
+		{ "EFUSE_MR", 26, 1 },
+		{ "EFUSE_PD", 25, 1 },
+		{ "EFUSE_RWL", 24, 1 },
+		{ "EFUSE_RSB", 23, 1 },
+		{ "EFUSE_TRCS", 22, 1 },
+		{ "EFUSE_AT", 20, 2 },
+		{ "EFUSE_RD_STATE", 16, 4 },
+		{ "EFUSE_BUSY", 15, 1 },
+		{ "EFUSE_WR_RD", 13, 2 },
+		{ "EFUSE_A", 0, 11 },
+	{ "DBG_EFUSE_RD_CTL", 0x6198, 0 },
+		{ "EFUSE_RD_ID", 6, 2 },
+		{ "EFUSE_RD_ADDR", 0, 6 },
+	{ "DBG_EFUSE_RD_DATA", 0x619c, 0 },
+	{ "DBG_EFUSE_TIME_0", 0x61a0, 0 },
+		{ "EFUSE_TIME_1", 16, 16 },
+		{ "EFUSE_TIME_0", 0, 16 },
+	{ "DBG_EFUSE_TIME_1", 0x61a4, 0 },
+		{ "EFUSE_TIME_3", 16, 16 },
+		{ "EFUSE_TIME_2", 0, 16 },
+	{ "DBG_EFUSE_TIME_2", 0x61a8, 0 },
+		{ "EFUSE_TIME_5", 16, 16 },
+		{ "EFUSE_TIME_4", 0, 16 },
+	{ "DBG_EFUSE_TIME_3", 0x61ac, 0 },
+		{ "EFUSE_TIME_7", 16, 16 },
+		{ "EFUSE_TIME_6", 0, 16 },
+	{ "DBG_VREF_CTL", 0x61b0, 0 },
+		{ "VREF_SEL_1", 15, 1 },
+		{ "VREF_R_1", 8, 7 },
+		{ "VREF_SEL_0", 7, 1 },
+		{ "VREF_R_0", 0, 7 },
+	{ "DBG_FPGA_EFUSE_CTL", 0x61b4, 0 },
+	{ "DBG_FPGA_EFUSE_DATA", 0x61b8, 0 },
+	{ "DBG_DBG0_RST_VALUE", 0x6020, 0 },
+	{ "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
+	{ "DBG_PLL_LOCK", 0x602c, 0 },
+		{ "M1_LOCK", 9, 1 },
+		{ "PCIE_LOCK", 8, 1 },
+		{ "U_LOCK", 7, 1 },
+		{ "MAC_LOCK", 6, 1 },
+		{ "ARM_LOCK", 5, 1 },
+		{ "M0_LOCK", 4, 1 },
+		{ "XGPBUS_LOCK", 3, 1 },
+		{ "XGPHY_LOCK", 2, 1 },
+		{ "USB_LOCK", 1, 1 },
+		{ "C_LOCK", 0, 1 },
+	{ "DBG_PLL_LOCK_ACT_LOW", 0x6030, 0 },
+		{ "M1_LOCK_ACT_LOW", 9, 1 },
+		{ "PCIE_LOCK_ACT_LOW", 8, 1 },
+		{ "U_LOCK_ACT_LOW", 7, 1 },
+		{ "MAC_LOCK_ACT_LOW", 6, 1 },
+		{ "ARM_LOCK_ACT_LOW", 5, 1 },
+		{ "M0_LOCK_ACT_LOW", 4, 1 },
+		{ "XGPBUS_LOCK_ACT_LOW", 3, 1 },
+		{ "XGPHY_LOCK_ACT_LOW", 2, 1 },
+		{ "USB_LOCK_ACT_LOW", 1, 1 },
+		{ "C_LOCK_ACT_LOW", 0, 1 },
+	{ "DBG_STATIC_U_PLL_CONF1", 0x6044, 0 },
+		{ "STATIC_U_PLL_RANGE", 22, 3 },
+		{ "STATIC_U_PLL_DIVQ", 17, 5 },
+		{ "STATIC_U_PLL_DIVFI", 8, 9 },
+		{ "STATIC_U_PLL_DIVR", 2, 6 },
+		{ "STATIC_U_PLL_BYPASS", 1, 1 },
+	{ "DBG_STATIC_U_PLL_CONF2", 0x6048, 0 },
+		{ "STATIC_U_PLL_SSMF", 5, 4 },
+		{ "STATIC_U_PLL_SSMD", 2, 3 },
+		{ "STATIC_U_PLL_SSDS", 1, 1 },
+		{ "STATIC_U_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_C_PLL_CONF1", 0x604c, 0 },
+		{ "STATIC_C_PLL_RANGE", 22, 3 },
+		{ "STATIC_C_PLL_DIVQ", 17, 5 },
+		{ "STATIC_C_PLL_DIVFI", 8, 9 },
+		{ "STATIC_C_PLL_DIVR", 2, 6 },
+		{ "STATIC_C_PLL_BYPASS", 1, 1 },
+	{ "DBG_STATIC_C_PLL_CONF2", 0x6050, 0 },
+		{ "STATIC_C_PLL_SSMF", 5, 4 },
+		{ "STATIC_C_PLL_SSMD", 2, 3 },
+		{ "STATIC_C_PLL_SSDS", 1, 1 },
+		{ "STATIC_C_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_PLL_DFS_CONF", 0x6054, 0 },
+		{ "STATIC_U_DFS_ACK", 23, 1 },
+		{ "STATIC_C_DFS_ACK", 22, 1 },
+		{ "STATIC_U_DFS_DIVFI", 13, 9 },
+		{ "STATIC_U_DFS_NEWDIV", 12, 1 },
+		{ "STATIC_U_DFS_ENABLE", 11, 1 },
+		{ "STATIC_C_DFS_DIVFI", 2, 9 },
+		{ "STATIC_C_DFS_NEWDIV", 1, 1 },
+		{ "STATIC_C_DFS_ENABLE", 0, 1 },
+	{ "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
+		{ "STATIC_LVDS_CLKOUT_EN", 21, 1 },
+		{ "ExPHYClk_sel_en", 16, 1 },
+	{ "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
+		{ "P_OCLK_MUXSEL", 13, 4 },
+	{ "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
+	{ "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
+	{ "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
+	{ "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
+	{ "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
+	{ "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
+	{ "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
+	{ "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
+	{ "DBG_TRACE_COUNTER", 0x6080, 0 },
+		{ "Counter1", 16, 16 },
+		{ "Counter0", 0, 16 },
+	{ "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
+	{ "DBG_TRACE_CONF", 0x6088, 0 },
+		{ "dbg_trace_operate_with_trg", 5, 1 },
+		{ "dbg_trace_operate_en", 4, 1 },
+		{ "dbg_operate_indv_combined", 3, 1 },
+		{ "dbg_operate_order_of_trigger", 2, 1 },
+		{ "dbg_operate_sgl_dbl_trigger", 1, 1 },
+		{ "dbg_operate0_or_1", 0, 1 },
+	{ "DBG_TRACE_RDEN", 0x608c, 0 },
+		{ "RD_ADDR1", 11, 9 },
+		{ "RD_ADDR0", 2, 9 },
+		{ "Rd_en1", 1, 1 },
+		{ "Rd_en0", 0, 1 },
+	{ "DBG_TRACE_WRADDR", 0x6090, 0 },
+		{ "Wr_pointer_addr1", 16, 9 },
+		{ "Wr_pointer_addr0", 0, 9 },
+	{ "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
+	{ "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
+	{ "DBG_FUSE_SENSE_DONE", 0x609c, 0 },
+		{ "PSRO_sel", 1, 4 },
+		{ "FUSE_DONE_SENSE", 0, 1 },
+	{ "DBG_PVT_EN1", 0x60a8, 0 },
+		{ "PVT_TRIMO", 18, 6 },
+		{ "PVT_TRIMG", 13, 5 },
+		{ "PVT_VSAMPLE", 12, 1 },
+		{ "PVT_PSAMPLE", 10, 2 },
+		{ "PVT_ENA", 9, 1 },
+		{ "PVT_RESET", 8, 1 },
+		{ "PVT_DIV", 0, 8 },
+	{ "DBG_PVT_EN2", 0x60ac, 0 },
+		{ "PVT_DATA_OUT", 1, 10 },
+		{ "PVT_DATA_VALID", 0, 1 },
+	{ "DBG_STATIC_M0_PLL_CONF1", 0x60b8, 0 },
+		{ "STATIC_M0_PLL_RANGE", 22, 3 },
+		{ "STATIC_M0_PLL_DIVQ", 17, 5 },
+		{ "STATIC_M0_PLL_DIVFI", 8, 9 },
+		{ "STATIC_M0_PLL_DIVR", 2, 6 },
+		{ "STATIC_M0_PLL_BYPASS", 1, 1 },
+		{ "STATIC_M0_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_M0_PLL_CONF2", 0x60bc, 0 },
+		{ "STATIC_SWMC1Rst_", 14, 1 },
+		{ "STATIC_SWMC1CfgRst_", 13, 1 },
+		{ "STATIC_PHY0RecRst_", 12, 1 },
+		{ "STATIC_PHY1RecRst_", 11, 1 },
+		{ "STATIC_SWMC0Rst_", 10, 1 },
+		{ "STATIC_SWMC0CfgRst_", 9, 1 },
+		{ "STATIC_M0_PLL_SSMF", 5, 4 },
+		{ "STATIC_M0_PLL_SSMD", 2, 3 },
+		{ "STATIC_M0_PLL_SSDS", 1, 1 },
+		{ "STATIC_M0_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_MAC_PLL_CONF1", 0x60c0, 0 },
+		{ "STATIC_MAC_PLL_RANGE", 22, 3 },
+		{ "STATIC_MAC_PLL_DIVQ", 17, 5 },
+		{ "STATIC_MAC_PLL_DIVFI", 8, 9 },
+		{ "STATIC_MAC_PLL_DIVR", 2, 6 },
+		{ "STATIC_MAC_PLL_BYPASS", 1, 1 },
+		{ "STATIC_MAC_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_MAC_PLL_CONF2", 0x60c4, 0 },
+		{ "STATIC_MAC_PLL_SSMF", 5, 4 },
+		{ "STATIC_MAC_PLL_SSMD", 2, 3 },
+		{ "STATIC_MAC_PLL_SSDS", 1, 1 },
+		{ "STATIC_MAC_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_ARM_PLL_CONF1", 0x60c8, 0 },
+		{ "STATIC_ARM_PLL_RANGE", 22, 3 },
+		{ "STATIC_ARM_PLL_DIVQ", 17, 5 },
+		{ "STATIC_ARM_PLL_DIVFI", 8, 9 },
+		{ "STATIC_ARM_PLL_DIVR", 2, 6 },
+		{ "STATIC_ARM_PLL_BYPASS", 1, 1 },
+		{ "STATIC_ARM_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_ARM_PLL_CONF2", 0x60cc, 0 },
+		{ "STATIC_ARM_PLL_SSMF", 5, 4 },
+		{ "STATIC_ARM_PLL_SSMD", 2, 3 },
+		{ "STATIC_ARM_PLL_SSDS", 1, 1 },
+		{ "STATIC_ARM_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_USB_PLL_CONF1", 0x60d0, 0 },
+		{ "STATIC_USB_PLL_RANGE", 22, 3 },
+		{ "STATIC_USB_PLL_DIVQ", 17, 5 },
+		{ "STATIC_USB_PLL_DIVFI", 8, 9 },
+		{ "STATIC_USB_PLL_DIVR", 2, 6 },
+		{ "STATIC_USB_PLL_BYPASS", 1, 1 },
+		{ "STATIC_USB_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_USB_PLL_CONF2", 0x60d4, 0 },
+		{ "STATIC_USB_PLL_SSMF", 5, 4 },
+		{ "STATIC_USB_PLL_SSMD", 2, 3 },
+		{ "STATIC_USB_PLL_SSDS", 1, 1 },
+		{ "STATIC_USB_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_XGPHY_PLL_CONF1", 0x60d8, 0 },
+		{ "STATIC_XGPHY_PLL_RANGE", 22, 3 },
+		{ "STATIC_XGPHY_PLL_DIVQ", 17, 5 },
+		{ "STATIC_XGPHY_PLL_DIVFI", 8, 9 },
+		{ "STATIC_XGPHY_PLL_DIVR", 2, 6 },
+		{ "STATIC_XGPHY_PLL_BYPASS", 1, 1 },
+		{ "STATIC_XGPHY_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_XGPHY_PLL_CONF2", 0x60dc, 0 },
+		{ "STATIC_XGPHY_PLL_SSMF", 5, 4 },
+		{ "STATIC_XGPHY_PLL_SSMD", 2, 3 },
+		{ "STATIC_XGPHY_PLL_SSDS", 1, 1 },
+		{ "STATIC_XGPHY_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_XGPBUS_PLL_CONF1", 0x60e0, 0 },
+		{ "STATIC_XGPBUS_SWRst_", 25, 1 },
+		{ "STATIC_XGPBUS_PLL_RANGE", 22, 3 },
+		{ "STATIC_XGPBUS_PLL_DIVQ", 17, 5 },
+		{ "STATIC_XGPBUS_PLL_DIVFI", 8, 9 },
+		{ "STATIC_XGPBUS_PLL_DIVR", 2, 6 },
+		{ "STATIC_XGPBUS_PLL_BYPASS", 1, 1 },
+		{ "STATIC_XGPBUS_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_XGPBUS_PLL_CONF2", 0x60e4, 0 },
+		{ "STATIC_XGPBUS_PLL_SSMF", 5, 4 },
+		{ "STATIC_XGPBUS_PLL_SSMD", 2, 3 },
+		{ "STATIC_XGPBUS_PLL_SSDS", 1, 1 },
+		{ "STATIC_XGPBUS_PLL_SSE", 0, 1 },
+	{ "DBG_STATIC_M1_PLL_CONF1", 0x60e8, 0 },
+		{ "STATIC_M1_PLL_RANGE", 22, 3 },
+		{ "STATIC_M1_PLL_DIVQ", 17, 5 },
+		{ "STATIC_M1_PLL_DIVFI", 8, 9 },
+		{ "STATIC_M1_PLL_DIVR", 2, 6 },
+		{ "STATIC_M1_PLL_BYPASS", 1, 1 },
+		{ "STATIC_M1_PLL_RESET", 0, 1 },
+	{ "DBG_STATIC_M1_PLL_CONF2", 0x60ec, 0 },
+		{ "STATIC_M1_PLL_SSMF", 5, 4 },
+		{ "STATIC_M1_PLL_SSMD", 2, 3 },
+		{ "STATIC_M1_PLL_SSDS", 1, 1 },
+		{ "STATIC_M1_PLL_SSE", 0, 1 },
+	{ "DBG_GPIO_PE_EN", 0x6118, 0 },
+		{ "GPIO23_PE_En", 23, 1 },
+		{ "GPIO22_PE_En", 22, 1 },
+		{ "GPIO21_PE_En", 21, 1 },
+		{ "GPIO20_PE_En", 20, 1 },
+		{ "GPIO19_PE_En", 19, 1 },
+		{ "GPIO18_PE_En", 18, 1 },
+		{ "GPIO17_PE_En", 17, 1 },
+		{ "GPIO16_PE_En", 16, 1 },
+		{ "GPIO15_PE_En", 15, 1 },
+		{ "GPIO14_PE_En", 14, 1 },
+		{ "GPIO13_PE_En", 13, 1 },
+		{ "GPIO12_PE_En", 12, 1 },
+		{ "GPIO11_PE_En", 11, 1 },
+		{ "GPIO10_PE_En", 10, 1 },
+		{ "GPIO9_PE_En", 9, 1 },
+		{ "GPIO8_PE_En", 8, 1 },
+		{ "GPIO7_PE_En", 7, 1 },
+		{ "GPIO6_PE_En", 6, 1 },
+		{ "GPIO5_PE_En", 5, 1 },
+		{ "GPIO4_PE_En", 4, 1 },
+		{ "GPIO3_PE_En", 3, 1 },
+		{ "GPIO2_PE_En", 2, 1 },
+		{ "GPIO1_PE_En", 1, 1 },
+		{ "GPIO0_PE_En", 0, 1 },
+	{ "DBG_GPIO_PS_EN", 0x611c, 0 },
+		{ "GPIO23_PS_En", 23, 1 },
+		{ "GPIO22_PS_En", 22, 1 },
+		{ "GPIO21_PS_En", 21, 1 },
+		{ "GPIO20_PS_En", 20, 1 },
+		{ "GPIO19_PS_En", 19, 1 },
+		{ "GPIO18_PS_En", 18, 1 },
+		{ "GPIO17_PS_En", 17, 1 },
+		{ "GPIO16_PS_En", 16, 1 },
+		{ "GPIO15_PS_En", 15, 1 },
+		{ "GPIO14_PS_En", 14, 1 },
+		{ "GPIO13_PS_En", 13, 1 },
+		{ "GPIO12_PS_En", 12, 1 },
+		{ "GPIO11_PS_En", 11, 1 },
+		{ "GPIO10_PS_En", 10, 1 },
+		{ "GPIO9_PS_En", 9, 1 },
+		{ "GPIO8_PS_En", 8, 1 },
+		{ "GPIO7_PS_En", 7, 1 },
+		{ "GPIO6_PS_En", 6, 1 },
+		{ "GPIO5_PS_En", 5, 1 },
+		{ "GPIO4_PS_En", 4, 1 },
+		{ "GPIO3_PS_En", 3, 1 },
+		{ "GPIO2_PS_En", 2, 1 },
+		{ "GPIO1_PS_En", 1, 1 },
+		{ "GPIO0_PS_En", 0, 1 },
+	{ "DBG_STATIC_PLL_LOCK_WAIT_CONF", 0x6150, 0 },
+		{ "STATIC_WAIT_LOCK", 24, 1 },
+		{ "STATIC_LOCK_WAIT_TIME", 0, 24 },
+	{ NULL }
+};
+
+struct reg_info t7_ma_regs[] = {
+	{ "MA_CLIENT0_PR_THRESHOLD", 0x7700, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT0_CR_THRESHOLD", 0x7704, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT1_PR_THRESHOLD", 0x7708, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT1_CR_THRESHOLD", 0x770c, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT2_PR_THRESHOLD", 0x7710, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT2_CR_THRESHOLD", 0x7714, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT3_PR_THRESHOLD", 0x7718, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT3_CR_THRESHOLD", 0x771c, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT4_PR_THRESHOLD", 0x7720, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT4_CR_THRESHOLD", 0x7724, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT5_PR_THRESHOLD", 0x7728, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT5_CR_THRESHOLD", 0x772c, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT6_PR_THRESHOLD", 0x7730, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT6_CR_THRESHOLD", 0x7734, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT7_PR_THRESHOLD", 0x7738, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT7_CR_THRESHOLD", 0x773c, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT8_PR_THRESHOLD", 0x7740, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT8_CR_THRESHOLD", 0x7744, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT9_PR_THRESHOLD", 0x7748, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT9_CR_THRESHOLD", 0x774c, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT10_PR_THRESHOLD", 0x7750, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT10_CR_THRESHOLD", 0x7754, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT11_PR_THRESHOLD", 0x7758, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT11_CR_THRESHOLD", 0x775c, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CLIENT12_PR_THRESHOLD", 0x7760, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT12_CR_THRESHOLD", 0x7764, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_LE_DEBUG_CNT", 0x7784, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_CIM_TH0_DEBUG_CNT", 0x7788, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_HMA_DEBUG_CNT", 0x7798, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_EDRAM0_BAR", 0x77c0, 0 },
+		{ "EDRAM0_BASE", 16, 16 },
+		{ "EDRAM0_SIZE", 0, 16 },
+	{ "MA_EDRAM1_BAR", 0x77c4, 0 },
+		{ "EDRAM1_BASE", 16, 16 },
+		{ "EDRAM1_SIZE", 0, 16 },
+	{ "MA_EXT_MEMORY0_BAR", 0x77c8, 0 },
+		{ "EXT_MEM0_BASE", 16, 16 },
+		{ "EXT_MEM0_SIZE", 0, 16 },
+	{ "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
+		{ "HMA_BASE", 16, 16 },
+		{ "HMA_SIZE", 0, 16 },
+	{ "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
+		{ "BRBC_MODE", 4, 1 },
+		{ "BRC_MODE", 3, 1 },
+		{ "EXT_MEM_PAGE_SIZE", 0, 3 },
+	{ "MA_ARB_CTRL", 0x77d4, 0 },
+		{ "HMA_WRT_EN", 26, 1 },
+		{ "HMA_NUM_PG_128B_FDBK", 21, 5 },
+		{ "HMA_DIS_128B_PG_CNT_FDBK", 20, 1 },
+		{ "HMA_DIS_BG_ARB", 19, 1 },
+		{ "HMA_DIS_BANK_FAIR", 18, 1 },
+		{ "HMA_DIS_PAGE_HINT", 17, 1 },
+		{ "HMA_DIS_ADV_ARB", 16, 1 },
+		{ "NUM_PG_128B_FDBK", 5, 5 },
+		{ "DIS_128B_PG_CNT_FDBK", 4, 1 },
+		{ "DIS_BG_ARB", 3, 1 },
+		{ "DIS_BANK_FAIR", 2, 1 },
+		{ "DIS_PAGE_HINT", 1, 1 },
+		{ "DIS_ADV_ARB", 0, 1 },
+	{ "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
+		{ "EDC512", 8, 1 },
+		{ "MC_SPLIT_BOUNDARY", 7, 1 },
+		{ "MC_SPLIT", 6, 1 },
+		{ "HMA_MUX", 5, 1 },
+		{ "EXT_MEM1_ENABLE", 4, 1 },
+		{ "HMA_ENABLE", 3, 1 },
+		{ "EXT_MEM0_ENABLE", 2, 1 },
+		{ "EDRAM1_ENABLE", 1, 1 },
+		{ "EDRAM0_ENABLE", 0, 1 },
+	{ "MA_INT_ENABLE", 0x77dc, 0 },
+		{ "MEM_TO_INT_ENABLE", 2, 1 },
+		{ "MEM_PERR_INT_ENABLE", 1, 1 },
+		{ "MEM_WRAP_INT_ENABLE", 0, 1 },
+	{ "MA_INT_CAUSE", 0x77e0, 0 },
+		{ "MEM_TO_INT_CAUSE", 2, 1 },
+		{ "MEM_PERR_INT_CAUSE", 1, 1 },
+		{ "MEM_WRAP_INT_CAUSE", 0, 1 },
+	{ "MA_INT_WRAP_STATUS", 0x77e4, 0 },
+		{ "MEM_WRAP_ADDRESS", 4, 28 },
+		{ "MEM_WRAP_CLIENT_NUM", 0, 4 },
+	{ "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
+	{ "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
+	{ "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 },
+		{ "ARB4_PAR_WRQUEUE_ERROR_EN", 11, 1 },
+		{ "ARB3_PAR_WRQUEUE_ERROR_EN", 10, 1 },
+		{ "ARB2_PAR_WRQUEUE_ERROR_EN", 9, 1 },
+		{ "ARB1_PAR_WRQUEUE_ERROR_EN", 8, 1 },
+		{ "ARB0_PAR_WRQUEUE_ERROR_EN", 7, 1 },
+		{ "ARB4_PAR_RDQUEUE_ERROR_EN", 6, 1 },
+		{ "ARB3_PAR_RDQUEUE_ERROR_EN", 5, 1 },
+		{ "ARB2_PAR_RDQUEUE_ERROR_EN", 4, 1 },
+		{ "ARB1_PAR_RDQUEUE_ERROR_EN", 3, 1 },
+		{ "ARB0_PAR_RDQUEUE_ERROR_EN", 2, 1 },
+		{ "TP_DMARBT_PAR_ERROR_EN", 1, 1 },
+		{ "LOGIC_FIFO_PAR_ERROR_EN", 0, 1 },
+	{ "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 },
+		{ "ARB4_PAR_WRQUEUE_ERROR", 11, 1 },
+		{ "ARB3_PAR_WRQUEUE_ERROR", 10, 1 },
+		{ "ARB2_PAR_WRQUEUE_ERROR", 9, 1 },
+		{ "ARB1_PAR_WRQUEUE_ERROR", 8, 1 },
+		{ "ARB0_PAR_WRQUEUE_ERROR", 7, 1 },
+		{ "ARB4_PAR_RDQUEUE_ERROR", 6, 1 },
+		{ "ARB3_PAR_RDQUEUE_ERROR", 5, 1 },
+		{ "ARB2_PAR_RDQUEUE_ERROR", 4, 1 },
+		{ "ARB1_PAR_RDQUEUE_ERROR", 3, 1 },
+		{ "ARB0_PAR_RDQUEUE_ERROR", 2, 1 },
+		{ "TP_DMARBT_PAR_ERROR", 1, 1 },
+		{ "LOGIC_FIFO_PAR_ERROR", 0, 1 },
+	{ "MA_COR_ERROR_ENABLE1", 0x779c, 0 },
+		{ "ARB4_COR_WRQUEUE_ERROR_EN", 9, 1 },
+		{ "ARB3_COR_WRQUEUE_ERROR_EN", 8, 1 },
+		{ "ARB2_COR_WRQUEUE_ERROR_EN", 7, 1 },
+		{ "ARB1_COR_WRQUEUE_ERROR_EN", 6, 1 },
+		{ "ARB0_COR_WRQUEUE_ERROR_EN", 5, 1 },
+		{ "ARB4_COR_RDQUEUE_ERROR_EN", 4, 1 },
+		{ "ARB3_COR_RDQUEUE_ERROR_EN", 3, 1 },
+		{ "ARB2_COR_RDQUEUE_ERROR_EN", 2, 1 },
+		{ "ARB1_COR_RDQUEUE_ERROR_EN", 1, 1 },
+		{ "ARB0_COR_RDQUEUE_ERROR_EN", 0, 1 },
+	{ "MA_COR_ERROR_STATUS1", 0x77a0, 0 },
+		{ "ARB4_COR_WRQUEUE_ERROR", 9, 1 },
+		{ "ARB3_COR_WRQUEUE_ERROR", 8, 1 },
+		{ "ARB2_COR_WRQUEUE_ERROR", 7, 1 },
+		{ "ARB1_COR_WRQUEUE_ERROR", 6, 1 },
+		{ "ARB0_COR_WRQUEUE_ERROR", 5, 1 },
+		{ "ARB4_COR_RDQUEUE_ERROR", 4, 1 },
+		{ "ARB3_COR_RDQUEUE_ERROR", 3, 1 },
+		{ "ARB2_COR_RDQUEUE_ERROR", 2, 1 },
+		{ "ARB1_COR_RDQUEUE_ERROR", 1, 1 },
+		{ "ARB0_COR_RDQUEUE_ERROR", 0, 1 },
+	{ "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 },
+		{ "CL14_PAR_WRQUEUE_ERROR_EN", 14, 1 },
+		{ "CL13_PAR_WRQUEUE_ERROR_EN", 13, 1 },
+		{ "CL12_PAR_WRQUEUE_ERROR_EN", 12, 1 },
+		{ "CL11_PAR_WRQUEUE_ERROR_EN", 11, 1 },
+		{ "CL10_PAR_WRQUEUE_ERROR_EN", 10, 1 },
+		{ "CL9_PAR_WRQUEUE_ERROR_EN", 9, 1 },
+		{ "CL8_PAR_WRQUEUE_ERROR_EN", 8, 1 },
+		{ "CL7_PAR_WRQUEUE_ERROR_EN", 7, 1 },
+		{ "CL6_PAR_WRQUEUE_ERROR_EN", 6, 1 },
+		{ "CL5_PAR_WRQUEUE_ERROR_EN", 5, 1 },
+		{ "CL4_PAR_WRQUEUE_ERROR_EN", 4, 1 },
+		{ "CL3_PAR_WRQUEUE_ERROR_EN", 3, 1 },
+		{ "CL2_PAR_WRQUEUE_ERROR_EN", 2, 1 },
+		{ "CL1_PAR_WRQUEUE_ERROR_EN", 1, 1 },
+		{ "CL0_PAR_WRQUEUE_ERROR_EN", 0, 1 },
+	{ "MA_PARITY_ERROR_STATUS2", 0x7804, 0 },
+		{ "CL14_PAR_WRQUEUE_ERROR", 14, 1 },
+		{ "CL13_PAR_WRQUEUE_ERROR", 13, 1 },
+		{ "CL12_PAR_WRQUEUE_ERROR", 12, 1 },
+		{ "CL11_PAR_WRQUEUE_ERROR", 11, 1 },
+		{ "CL10_PAR_WRQUEUE_ERROR", 10, 1 },
+		{ "CL9_PAR_WRQUEUE_ERROR", 9, 1 },
+		{ "CL8_PAR_WRQUEUE_ERROR", 8, 1 },
+		{ "CL7_PAR_WRQUEUE_ERROR", 7, 1 },
+		{ "CL6_PAR_WRQUEUE_ERROR", 6, 1 },
+		{ "CL5_PAR_WRQUEUE_ERROR", 5, 1 },
+		{ "CL4_PAR_WRQUEUE_ERROR", 4, 1 },
+		{ "CL3_PAR_WRQUEUE_ERROR", 3, 1 },
+		{ "CL2_PAR_WRQUEUE_ERROR", 2, 1 },
+		{ "CL1_PAR_WRQUEUE_ERROR", 1, 1 },
+		{ "CL0_PAR_WRQUEUE_ERROR", 0, 1 },
+	{ "MA_PARITY_ERROR_ENABLE3", 0x7884, 0 },
+		{ "CL14_PAR_RDQUEUE_ERROR_EN", 14, 1 },
+		{ "CL13_PAR_RDQUEUE_ERROR_EN", 13, 1 },
+		{ "CL12_PAR_RDQUEUE_ERROR_EN", 12, 1 },
+		{ "CL11_PAR_RDQUEUE_ERROR_EN", 11, 1 },
+		{ "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 },
+		{ "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 },
+		{ "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 },
+		{ "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 },
+		{ "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 },
+		{ "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 },
+		{ "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 },
+		{ "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 },
+		{ "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 },
+		{ "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 },
+		{ "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
+	{ "MA_PARITY_ERROR_STATUS3", 0x7888, 0 },
+		{ "CL14_PAR_RDQUEUE_ERROR", 14, 1 },
+		{ "CL13_PAR_RDQUEUE_ERROR", 13, 1 },
+		{ "CL12_PAR_RDQUEUE_ERROR", 12, 1 },
+		{ "CL11_PAR_RDQUEUE_ERROR", 11, 1 },
+		{ "CL10_PAR_RDQUEUE_ERROR", 10, 1 },
+		{ "CL9_PAR_RDQUEUE_ERROR", 9, 1 },
+		{ "CL8_PAR_RDQUEUE_ERROR", 8, 1 },
+		{ "CL7_PAR_RDQUEUE_ERROR", 7, 1 },
+		{ "CL6_PAR_RDQUEUE_ERROR", 6, 1 },
+		{ "CL5_PAR_RDQUEUE_ERROR", 5, 1 },
+		{ "CL4_PAR_RDQUEUE_ERROR", 4, 1 },
+		{ "CL3_PAR_RDQUEUE_ERROR", 3, 1 },
+		{ "CL2_PAR_RDQUEUE_ERROR", 2, 1 },
+		{ "CL1_PAR_RDQUEUE_ERROR", 1, 1 },
+		{ "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
+	{ "MA_COR_ERROR_ENABLE2", 0x77b0, 0 },
+		{ "CL14_COR_WRQUEUE_ERROR_EN", 14, 1 },
+		{ "CL13_COR_WRQUEUE_ERROR_EN", 13, 1 },
+		{ "CL12_COR_WRQUEUE_ERROR_EN", 12, 1 },
+		{ "CL11_COR_WRQUEUE_ERROR_EN", 11, 1 },
+		{ "CL10_COR_WRQUEUE_ERROR_EN", 10, 1 },
+		{ "CL9_COR_WRQUEUE_ERROR_EN", 9, 1 },
+		{ "CL8_COR_WRQUEUE_ERROR_EN", 8, 1 },
+		{ "CL7_COR_WRQUEUE_ERROR_EN", 7, 1 },
+		{ "CL6_COR_WRQUEUE_ERROR_EN", 6, 1 },
+		{ "CL5_COR_WRQUEUE_ERROR_EN", 5, 1 },
+		{ "CL4_COR_WRQUEUE_ERROR_EN", 4, 1 },
+		{ "CL3_COR_WRQUEUE_ERROR_EN", 3, 1 },
+		{ "CL2_COR_WRQUEUE_ERROR_EN", 2, 1 },
+		{ "CL1_COR_WRQUEUE_ERROR_EN", 1, 1 },
+		{ "CL0_COR_WRQUEUE_ERROR_EN", 0, 1 },
+	{ "MA_COR_ERROR_STATUS2", 0x77b4, 0 },
+		{ "CL14_COR_WRQUEUE_ERROR", 14, 1 },
+		{ "CL13_COR_WRQUEUE_ERROR", 13, 1 },
+		{ "CL12_COR_WRQUEUE_ERROR", 12, 1 },
+		{ "CL11_COR_WRQUEUE_ERROR", 11, 1 },
+		{ "CL10_COR_WRQUEUE_ERROR", 10, 1 },
+		{ "CL9_COR_WRQUEUE_ERROR", 9, 1 },
+		{ "CL8_COR_WRQUEUE_ERROR", 8, 1 },
+		{ "CL7_COR_WRQUEUE_ERROR", 7, 1 },
+		{ "CL6_COR_WRQUEUE_ERROR", 6, 1 },
+		{ "CL5_COR_WRQUEUE_ERROR", 5, 1 },
+		{ "CL4_COR_WRQUEUE_ERROR", 4, 1 },
+		{ "CL3_COR_WRQUEUE_ERROR", 3, 1 },
+		{ "CL2_COR_WRQUEUE_ERROR", 2, 1 },
+		{ "CL1_COR_WRQUEUE_ERROR", 1, 1 },
+		{ "CL0_COR_WRQUEUE_ERROR", 0, 1 },
+	{ "MA_COR_ERROR_ENABLE3", 0x77b8, 0 },
+		{ "CL14_COR_RDQUEUE_ERROR_EN", 14, 1 },
+		{ "CL13_COR_RDQUEUE_ERROR_EN", 13, 1 },
+		{ "CL12_COR_RDQUEUE_ERROR_EN", 12, 1 },
+		{ "CL11_COR_RDQUEUE_ERROR_EN", 11, 1 },
+		{ "CL10_COR_RDQUEUE_ERROR_EN", 10, 1 },
+		{ "CL9_COR_RDQUEUE_ERROR_EN", 9, 1 },
+		{ "CL8_COR_RDQUEUE_ERROR_EN", 8, 1 },
+		{ "CL7_COR_RDQUEUE_ERROR_EN", 7, 1 },
+		{ "CL6_COR_RDQUEUE_ERROR_EN", 6, 1 },
+		{ "CL5_COR_RDQUEUE_ERROR_EN", 5, 1 },
+		{ "CL4_COR_RDQUEUE_ERROR_EN", 4, 1 },
+		{ "CL3_COR_RDQUEUE_ERROR_EN", 3, 1 },
+		{ "CL2_COR_RDQUEUE_ERROR_EN", 2, 1 },
+		{ "CL1_COR_RDQUEUE_ERROR_EN", 1, 1 },
+		{ "CL0_COR_RDQUEUE_ERROR_EN", 0, 1 },
+	{ "MA_COR_ERROR_STATUS3", 0x77bc, 0 },
+		{ "CL14_COR_RDQUEUE_ERROR", 14, 1 },
+		{ "CL13_COR_RDQUEUE_ERROR", 13, 1 },
+		{ "CL12_COR_RDQUEUE_ERROR", 12, 1 },
+		{ "CL11_COR_RDQUEUE_ERROR", 11, 1 },
+		{ "CL10_COR_RDQUEUE_ERROR", 10, 1 },
+		{ "CL9_COR_RDQUEUE_ERROR", 9, 1 },
+		{ "CL8_COR_RDQUEUE_ERROR", 8, 1 },
+		{ "CL7_COR_RDQUEUE_ERROR", 7, 1 },
+		{ "CL6_COR_RDQUEUE_ERROR", 6, 1 },
+		{ "CL5_COR_RDQUEUE_ERROR", 5, 1 },
+		{ "CL4_COR_RDQUEUE_ERROR", 4, 1 },
+		{ "CL3_COR_RDQUEUE_ERROR", 3, 1 },
+		{ "CL2_COR_RDQUEUE_ERROR", 2, 1 },
+		{ "CL1_COR_RDQUEUE_ERROR", 1, 1 },
+		{ "CL0_COR_RDQUEUE_ERROR", 0, 1 },
+	{ "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
+		{ "BONUS_REG", 6, 26 },
+		{ "COHERANCY_CMD_TYPE", 4, 2 },
+		{ "COHERANCY_THREAD_NUM", 1, 3 },
+		{ "COHERANCY_ENABLE", 0, 1 },
+	{ "MA_ERROR_ENABLE", 0x77fc, 0 },
+		{ "FUTURE_EXPANSION_EE", 1, 31 },
+		{ "UE_ENABLE", 0, 1 },
+	{ "MA_EXT_MEMORY1_BAR", 0x7808, 0 },
+		{ "EXT_MEM1_BASE", 16, 16 },
+		{ "EXT_MEM1_SIZE", 0, 16 },
+	{ "MA_PMTX_THROTTLE", 0x780c, 0 },
+		{ "FL_ENABLE", 31, 1 },
+		{ "FL_LIMIT", 0, 8 },
+	{ "MA_PMRX_THROTTLE", 0x7810, 0 },
+		{ "FL_ENABLE", 31, 1 },
+		{ "FL_LIMIT", 0, 8 },
+	{ "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 },
+	{ "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 },
+	{ "MA_ULPTX_WRDATA_CNT", 0x781c, 0 },
+	{ "MA_ULPRX_WRDATA_CNT", 0x7820, 0 },
+	{ "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 },
+	{ "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 },
+	{ "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 },
+	{ "MA_LE_WRDATA_CNT", 0x7830, 0 },
+	{ "MA_CIM_TH0_WRDATA_CNT", 0x7834, 0 },
+	{ "MA_PCIE_WRDATA_CNT", 0x7838, 0 },
+	{ "MA_PMTX_WRDATA_CNT", 0x783c, 0 },
+	{ "MA_PMRX_WRDATA_CNT", 0x7840, 0 },
+	{ "MA_HMA_WRDATA_CNT", 0x7844, 0 },
+	{ "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 },
+	{ "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 },
+	{ "MA_ULPTX_RDDATA_CNT", 0x7850, 0 },
+	{ "MA_ULPRX_RDDATA_CNT", 0x7854, 0 },
+	{ "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 },
+	{ "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 },
+	{ "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 },
+	{ "MA_LE_RDDATA_CNT", 0x7864, 0 },
+	{ "MA_CIM_TH0_RDDATA_CNT", 0x7868, 0 },
+	{ "MA_PCIE_RDDATA_CNT", 0x786c, 0 },
+	{ "MA_PMTX_RDDATA_CNT", 0x7870, 0 },
+	{ "MA_PMRX_RDDATA_CNT", 0x7874, 0 },
+	{ "MA_HMA_RDDATA_CNT", 0x7878, 0 },
+	{ "MA_EXIT_ADDR_FAULT", 0x787c, 0 },
+	{ "MA_DDR_DEVICE_CFG", 0x7880, 0 },
+		{ "MEM_WIDTH", 1, 3 },
+		{ "DDR_MODE", 0, 1 },
+	{ "MA_TIMEOUT_CFG", 0x78cc, 0 },
+		{ "CLR", 31, 1 },
+		{ "CNT_LOCK", 30, 1 },
+		{ "WRN", 24, 1 },
+		{ "DIR", 23, 1 },
+		{ "TYPE", 22, 1 },
+		{ "CLIENT", 16, 4 },
+		{ "DELAY", 0, 16 },
+	{ "MA_TIMEOUT_CNT", 0x78d0, 0 },
+		{ "DIR", 23, 1 },
+		{ "TYPE", 22, 1 },
+		{ "CLIENT", 16, 4 },
+		{ "CNT_VAL", 0, 16 },
+	{ "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 },
+		{ "FUTURE_CEXPANSION_WTE", 31, 1 },
+		{ "CL14_WR_CMD_TO_EN", 30, 1 },
+		{ "CL13_WR_CMD_TO_EN", 29, 1 },
+		{ "CL12_WR_CMD_TO_EN", 28, 1 },
+		{ "CL11_WR_CMD_TO_EN", 27, 1 },
+		{ "CL10_WR_CMD_TO_EN", 26, 1 },
+		{ "CL9_WR_CMD_TO_EN", 25, 1 },
+		{ "CL8_WR_CMD_TO_EN", 24, 1 },
+		{ "CL7_WR_CMD_TO_EN", 23, 1 },
+		{ "CL6_WR_CMD_TO_EN", 22, 1 },
+		{ "CL5_WR_CMD_TO_EN", 21, 1 },
+		{ "CL4_WR_CMD_TO_EN", 20, 1 },
+		{ "CL3_WR_CMD_TO_EN", 19, 1 },
+		{ "CL2_WR_CMD_TO_EN", 18, 1 },
+		{ "CL1_WR_CMD_TO_EN", 17, 1 },
+		{ "CL0_WR_CMD_TO_EN", 16, 1 },
+		{ "FUTURE_DEXPANSION_WTE", 15, 1 },
+		{ "CL14_WR_DATA_TO_EN", 14, 1 },
+		{ "CL13_WR_DATA_TO_EN", 13, 1 },
+		{ "CL12_WR_DATA_TO_EN", 12, 1 },
+		{ "CL11_WR_DATA_TO_EN", 11, 1 },
+		{ "CL10_WR_DATA_TO_EN", 10, 1 },
+		{ "CL9_WR_DATA_TO_EN", 9, 1 },
+		{ "CL8_WR_DATA_TO_EN", 8, 1 },
+		{ "CL7_WR_DATA_TO_EN", 7, 1 },
+		{ "CL6_WR_DATA_TO_EN", 6, 1 },
+		{ "CL5_WR_DATA_TO_EN", 5, 1 },
+		{ "CL4_WR_DATA_TO_EN", 4, 1 },
+		{ "CL3_WR_DATA_TO_EN", 3, 1 },
+		{ "CL2_WR_DATA_TO_EN", 2, 1 },
+		{ "CL1_WR_DATA_TO_EN", 1, 1 },
+		{ "CL0_WR_DATA_TO_EN", 0, 1 },
+	{ "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
+		{ "FUTURE_CEXPANSION_WTS", 31, 1 },
+		{ "CL14_WR_CMD_TO_ERROR", 30, 1 },
+		{ "CL13_WR_CMD_TO_ERROR", 29, 1 },
+		{ "CL12_WR_CMD_TO_ERROR", 28, 1 },
+		{ "CL11_WR_CMD_TO_ERROR", 27, 1 },
+		{ "CL10_WR_CMD_TO_ERROR", 26, 1 },
+		{ "CL9_WR_CMD_TO_ERROR", 25, 1 },
+		{ "CL8_WR_CMD_TO_ERROR", 24, 1 },
+		{ "CL7_WR_CMD_TO_ERROR", 23, 1 },
+		{ "CL6_WR_CMD_TO_ERROR", 22, 1 },
+		{ "CL5_WR_CMD_TO_ERROR", 21, 1 },
+		{ "CL4_WR_CMD_TO_ERROR", 20, 1 },
+		{ "CL3_WR_CMD_TO_ERROR", 19, 1 },
+		{ "CL2_WR_CMD_TO_ERROR", 18, 1 },
+		{ "CL1_WR_CMD_TO_ERROR", 17, 1 },
+		{ "CL0_WR_CMD_TO_ERROR", 16, 1 },
+		{ "FUTURE_DEXPANSION_WTS", 15, 1 },
+		{ "CL14_WR_DATA_TO_ERROR", 14, 1 },
+		{ "CL13_WR_DATA_TO_ERROR", 13, 1 },
+		{ "CL12_WR_DATA_TO_ERROR", 12, 1 },
+		{ "CL11_WR_DATA_TO_ERROR", 11, 1 },
+		{ "CL10_WR_DATA_TO_ERROR", 10, 1 },
+		{ "CL9_WR_DATA_TO_ERROR", 9, 1 },
+		{ "CL8_WR_DATA_TO_ERROR", 8, 1 },
+		{ "CL7_WR_DATA_TO_ERROR", 7, 1 },
+		{ "CL6_WR_DATA_TO_ERROR", 6, 1 },
+		{ "CL5_WR_DATA_TO_ERROR", 5, 1 },
+		{ "CL4_WR_DATA_TO_ERROR", 4, 1 },
+		{ "CL3_WR_DATA_TO_ERROR", 3, 1 },
+		{ "CL2_WR_DATA_TO_ERROR", 2, 1 },
+		{ "CL1_WR_DATA_TO_ERROR", 1, 1 },
+		{ "CL0_WR_DATA_TO_ERROR", 0, 1 },
+	{ "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
+		{ "FUTURE_CEXPANSION_RTE", 31, 1 },
+		{ "CL14_RD_CMD_TO_EN", 30, 1 },
+		{ "CL13_RD_CMD_TO_EN", 29, 1 },
+		{ "CL12_RD_CMD_TO_EN", 28, 1 },
+		{ "CL11_RD_CMD_TO_EN", 27, 1 },
+		{ "CL10_RD_CMD_TO_EN", 26, 1 },
+		{ "CL9_RD_CMD_TO_EN", 25, 1 },
+		{ "CL8_RD_CMD_TO_EN", 24, 1 },
+		{ "CL7_RD_CMD_TO_EN", 23, 1 },
+		{ "CL6_RD_CMD_TO_EN", 22, 1 },
+		{ "CL5_RD_CMD_TO_EN", 21, 1 },
+		{ "CL4_RD_CMD_TO_EN", 20, 1 },
+		{ "CL3_RD_CMD_TO_EN", 19, 1 },
+		{ "CL2_RD_CMD_TO_EN", 18, 1 },
+		{ "CL1_RD_CMD_TO_EN", 17, 1 },
+		{ "CL0_RD_CMD_TO_EN", 16, 1 },
+		{ "FUTURE_DEXPANSION_RTE", 15, 1 },
+		{ "CL14_RD_DATA_TO_EN", 14, 1 },
+		{ "CL13_RD_DATA_TO_EN", 13, 1 },
+		{ "CL12_RD_DATA_TO_EN", 12, 1 },
+		{ "CL11_RD_DATA_TO_EN", 11, 1 },
+		{ "CL10_RD_DATA_TO_EN", 10, 1 },
+		{ "CL9_RD_DATA_TO_EN", 9, 1 },
+		{ "CL8_RD_DATA_TO_EN", 8, 1 },
+		{ "CL7_RD_DATA_TO_EN", 7, 1 },
+		{ "CL6_RD_DATA_TO_EN", 6, 1 },
+		{ "CL5_RD_DATA_TO_EN", 5, 1 },
+		{ "CL4_RD_DATA_TO_EN", 4, 1 },
+		{ "CL3_RD_DATA_TO_EN", 3, 1 },
+		{ "CL2_RD_DATA_TO_EN", 2, 1 },
+		{ "CL1_RD_DATA_TO_EN", 1, 1 },
+		{ "CL0_RD_DATA_TO_EN", 0, 1 },
+	{ "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
+		{ "FUTURE_CEXPANSION_RTS", 31, 1 },
+		{ "CL14_RD_CMD_TO_ERROR", 30, 1 },
+		{ "CL13_RD_CMD_TO_ERROR", 29, 1 },
+		{ "CL12_RD_CMD_TO_ERROR", 28, 1 },
+		{ "CL11_RD_CMD_TO_ERROR", 27, 1 },
+		{ "CL10_RD_CMD_TO_ERROR", 26, 1 },
+		{ "CL9_RD_CMD_TO_ERROR", 25, 1 },
+		{ "CL8_RD_CMD_TO_ERROR", 24, 1 },
+		{ "CL7_RD_CMD_TO_ERROR", 23, 1 },
+		{ "CL6_RD_CMD_TO_ERROR", 22, 1 },
+		{ "CL5_RD_CMD_TO_ERROR", 21, 1 },
+		{ "CL4_RD_CMD_TO_ERROR", 20, 1 },
+		{ "CL3_RD_CMD_TO_ERROR", 19, 1 },
+		{ "CL2_RD_CMD_TO_ERROR", 18, 1 },
+		{ "CL1_RD_CMD_TO_ERROR", 17, 1 },
+		{ "CL0_RD_CMD_TO_ERROR", 16, 1 },
+		{ "FUTURE_DEXPANSION_RTS", 14, 2 },
+		{ "CL13_RD_DATA_TO_ERROR", 13, 1 },
+		{ "CL12_RD_DATA_TO_ERROR", 12, 1 },
+		{ "CL11_RD_DATA_TO_ERROR", 11, 1 },
+		{ "CL10_RD_DATA_TO_ERROR", 10, 1 },
+		{ "CL9_RD_DATA_TO_ERROR", 9, 1 },
+		{ "CL8_RD_DATA_TO_ERROR", 8, 1 },
+		{ "CL7_RD_DATA_TO_ERROR", 7, 1 },
+		{ "CL6_RD_DATA_TO_ERROR", 6, 1 },
+		{ "CL5_RD_DATA_TO_ERROR", 5, 1 },
+		{ "CL4_RD_DATA_TO_ERROR", 4, 1 },
+		{ "CL3_RD_DATA_TO_ERROR", 3, 1 },
+		{ "CL2_RD_DATA_TO_ERROR", 2, 1 },
+		{ "CL1_RD_DATA_TO_ERROR", 1, 1 },
+		{ "CL0_RD_DATA_TO_ERROR", 0, 1 },
+	{ "MA_BKP_CNT_SEL", 0x78e4, 0 },
+		{ "TYPE", 30, 2 },
+		{ "CLIENT", 24, 4 },
+	{ "MA_BKP_CNT", 0x78e8, 0 },
+	{ "MA_WRT_ARB", 0x78ec, 0 },
+		{ "WRT_EN", 31, 1 },
+		{ "WR_TIM", 16, 8 },
+		{ "RD_WIN", 8, 8 },
+		{ "WR_WIN", 0, 8 },
+	{ "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
+		{ "FUTURE_DEXPANSION_IPE", 14, 18 },
+		{ "CL13_IF_PAR_EN", 13, 1 },
+		{ "CL12_IF_PAR_EN", 12, 1 },
+		{ "CL11_IF_PAR_EN", 11, 1 },
+		{ "CL10_IF_PAR_EN", 10, 1 },
+		{ "CL9_IF_PAR_EN", 9, 1 },
+		{ "CL8_IF_PAR_EN", 8, 1 },
+		{ "CL7_IF_PAR_EN", 7, 1 },
+		{ "CL6_IF_PAR_EN", 6, 1 },
+		{ "CL5_IF_PAR_EN", 5, 1 },
+		{ "CL4_IF_PAR_EN", 4, 1 },
+		{ "CL3_IF_PAR_EN", 3, 1 },
+		{ "CL2_IF_PAR_EN", 2, 1 },
+		{ "CL1_IF_PAR_EN", 1, 1 },
+		{ "CL0_IF_PAR_EN", 0, 1 },
+	{ "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
+		{ "FUTURE_DEXPANSION_IPS", 14, 18 },
+		{ "CL13_IF_PAR_ERROR", 13, 1 },
+		{ "CL12_IF_PAR_ERROR", 12, 1 },
+		{ "CL11_IF_PAR_ERROR", 11, 1 },
+		{ "CL10_IF_PAR_ERROR", 10, 1 },
+		{ "CL9_IF_PAR_ERROR", 9, 1 },
+		{ "CL8_IF_PAR_ERROR", 8, 1 },
+		{ "CL7_IF_PAR_ERROR", 7, 1 },
+		{ "CL6_IF_PAR_ERROR", 6, 1 },
+		{ "CL5_IF_PAR_ERROR", 5, 1 },
+		{ "CL4_IF_PAR_ERROR", 4, 1 },
+		{ "CL3_IF_PAR_ERROR", 3, 1 },
+		{ "CL2_IF_PAR_ERROR", 2, 1 },
+		{ "CL1_IF_PAR_ERROR", 1, 1 },
+		{ "CL0_IF_PAR_ERROR", 0, 1 },
+	{ "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 },
+		{ "DEBUG_OR", 15, 1 },
+		{ "DEBUG_HI", 14, 1 },
+		{ "DEBUG_RPT", 13, 1 },
+		{ "DEBUGPAGE", 10, 3 },
+		{ "DEBUGSELH", 5, 5 },
+		{ "DEBUGSELL", 0, 5 },
+	{ "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 },
+	{ "MA_DBG_CTL", 0x77a4, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG", 16, 1 },
+		{ "SEL", 0, 8 },
+	{ "MA_DBG_DATA", 0x77a8, 0 },
+	{ "MA_CLIENT13_PR_THRESHOLD", 0x7900, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT13_CR_THRESHOLD", 0x7904, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CRYPTO_DEBUG_CNT", 0x7908, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_CRYPTO_WRDATA_CNT", 0x790c, 0 },
+	{ "MA_CRYPTO_RDDATA_CNT", 0x7910, 0 },
+	{ "MA_LOCAL_DEBUG_PERF_CFG", 0x7914, 0 },
+		{ "DEBUG_OR", 15, 1 },
+		{ "DEBUG_HI", 14, 1 },
+		{ "DEBUG_RPT", 13, 1 },
+		{ "DEBUGPAGE", 10, 3 },
+		{ "DEBUGSELH", 5, 5 },
+		{ "DEBUGSELL", 0, 5 },
+	{ "MA_LOCAL_DEBUG_PERF_RPT", 0x7918, 0 },
+	{ "MA_PCIE_THROTTLE", 0x791c, 0 },
+		{ "FL_ENABLE", 31, 1 },
+		{ "FL_LIMIT", 0, 8 },
+	{ "MA_CLIENT14_PR_THRESHOLD", 0x7920, 0 },
+		{ "THRESHOLD1_EN", 31, 1 },
+		{ "THRESHOLD1", 16, 15 },
+		{ "THRESHOLD0_EN", 15, 1 },
+		{ "THRESHOLD0", 0, 15 },
+	{ "MA_CLIENT14_CR_THRESHOLD", 0x7924, 0 },
+		{ "CREDITSHAPER_EN", 31, 1 },
+		{ "CREDIT_MAX", 16, 12 },
+		{ "CREDIT_VAL", 0, 12 },
+	{ "MA_CIM_TH1_DEBUG_CNT", 0x7928, 0 },
+		{ "DBG_READ_DATA_CNT", 24, 8 },
+		{ "DBG_READ_REQ_CNT", 16, 8 },
+		{ "DBG_WRITE_DATA_CNT", 8, 8 },
+		{ "DBG_WRITE_REQ_CNT", 0, 8 },
+	{ "MA_CIM_TH1_WRDATA_CNT", 0x792c, 0 },
+	{ "MA_CIM_TH1_RDDATA_CNT", 0x7930, 0 },
+	{ "MA_CIM_THREAD1_MAPPER", 0x7934, 0 },
+	{ "MA_PIO_CI_SGE_TH0_BASE", 0x7938, 0 },
+	{ "MA_PIO_CI_SGE_TH1_BASE", 0x793c, 0 },
+	{ "MA_PIO_CI_ULPTX_BASE", 0x7940, 0 },
+	{ "MA_PIO_CI_ULPRX_BASE", 0x7944, 0 },
+	{ "MA_PIO_CI_ULPTXRX_BASE", 0x7948, 0 },
+	{ "MA_PIO_CI_TP_TH0_BASE", 0x794c, 0 },
+	{ "MA_PIO_CI_TP_TH1_BASE", 0x7950, 0 },
+	{ "MA_PIO_CI_LE_BASE", 0x7954, 0 },
+	{ "MA_PIO_CI_CIM_TH0_BASE", 0x7958, 0 },
+	{ "MA_PIO_CI_PCIE_BASE", 0x795c, 0 },
+	{ "MA_PIO_CI_PMTX_BASE", 0x7960, 0 },
+	{ "MA_PIO_CI_PMRX_BASE", 0x7964, 0 },
+	{ "MA_PIO_CI_HMA_BASE", 0x7968, 0 },
+	{ "MA_PIO_CI_CRYPTO_BASE", 0x796c, 0 },
+	{ "MA_PIO_CI_CIM_TH1_BASE", 0x7970, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_cim_regs[] = {
+	{ "CIM_BOOT_CFG", 0x7b00, 0 },
+		{ "BootAddr", 8, 24 },
+		{ "uPGen", 2, 6 },
+		{ "BootSdram", 1, 1 },
+		{ "uPCRst", 0, 1 },
+	{ "CIM_BOOT_LEN", 0x7bf0, 0 },
+		{ "BootLen", 4, 28 },
+	{ "CIM_PERR_ENABLE", 0x7b08, 0 },
+		{ "ma_cim_IntfPerr", 31, 1 },
+		{ "MBHostParErr", 30, 1 },
+		{ "MaArbInvRspTag", 29, 1 },
+		{ "MaArbFIFOParErr", 28, 1 },
+		{ "SemSramParErr", 27, 1 },
+		{ "RSACParErr", 26, 1 },
+		{ "RSADParErr", 25, 1 },
+		{ "PLCIM_MstRspDataParErr", 24, 1 },
+		{ "PCIE2CIMIntfParErr", 23, 1 },
+		{ "NCSI2CIMIntfParErr", 22, 1 },
+		{ "SGE2CIMIntfParErr", 21, 1 },
+		{ "ULP2CIMIntfParErr", 20, 1 },
+		{ "TP2CIMIntfParErr", 19, 1 },
+		{ "Core7ParErr", 18, 1 },
+		{ "Core6ParErr", 17, 1 },
+		{ "Core5ParErr", 16, 1 },
+		{ "Core4ParErr", 15, 1 },
+		{ "Core3ParErr", 14, 1 },
+		{ "Core2ParErr", 13, 1 },
+		{ "Core1ParErr", 12, 1 },
+		{ "GftParErr", 10, 1 },
+		{ "MPSRspDataParErr", 9, 1 },
+		{ "ER_RspDataParErr", 8, 1 },
+		{ "FlowFIFOParErr", 7, 1 },
+		{ "ObqSramParErr", 6, 1 },
+		{ "TieQOutParErr", 3, 1 },
+		{ "TieQInParErr", 2, 1 },
+		{ "PifRspParErr", 1, 1 },
+		{ "PifReqParErr", 0, 1 },
+	{ "CIM_PERR_CAUSE", 0x7b0c, 0 },
+		{ "ma_cim_IntfPerr", 31, 1 },
+		{ "MBHostParErr", 30, 1 },
+		{ "MaArbInvRspTag", 29, 1 },
+		{ "MaArbFIFOParErr", 28, 1 },
+		{ "SemSramParErr", 27, 1 },
+		{ "RSACParErr", 26, 1 },
+		{ "RSADParErr", 25, 1 },
+		{ "PLCIM_MstRspDataParErr", 24, 1 },
+		{ "PCIE2CIMIntfParErr", 23, 1 },
+		{ "NCSI2CIMIntfParErr", 22, 1 },
+		{ "SGE2CIMIntfParErr", 21, 1 },
+		{ "ULP2CIMIntfParErr", 20, 1 },
+		{ "TP2CIMIntfParErr", 19, 1 },
+		{ "Core7ParErr", 18, 1 },
+		{ "Core6ParErr", 17, 1 },
+		{ "Core5ParErr", 16, 1 },
+		{ "Core4ParErr", 15, 1 },
+		{ "Core3ParErr", 14, 1 },
+		{ "Core2ParErr", 13, 1 },
+		{ "Core1ParErr", 12, 1 },
+		{ "GftParErr", 10, 1 },
+		{ "MPSRspDataParErr", 9, 1 },
+		{ "ER_RspDataParErr", 8, 1 },
+		{ "FlowFIFOParErr", 7, 1 },
+		{ "ObqSramParErr", 6, 1 },
+		{ "TieQOutParErr", 3, 1 },
+		{ "TieQInParErr", 2, 1 },
+		{ "PifRspParErr", 1, 1 },
+		{ "PifReqParErr", 0, 1 },
+	{ "CIM_UP_SPARE_INT", 0x7b24, 0 },
+		{ "TDebugInt", 4, 1 },
+		{ "BootVecSel", 3, 1 },
+		{ "uPSpareInt", 0, 3 },
+	{ "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
+		{ "Core7AccInt", 22, 1 },
+		{ "Core6AccInt", 21, 1 },
+		{ "Core5AccInt", 20, 1 },
+		{ "Core4AccInt", 19, 1 },
+		{ "Core3AccInt", 18, 1 },
+		{ "Core2AccInt", 17, 1 },
+		{ "Core1AccInt", 16, 1 },
+		{ "Timer1IntEn", 3, 1 },
+		{ "Timer0IntEn", 2, 1 },
+		{ "PErrNonZero", 1, 1 },
+	{ "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
+		{ "Core7AccInt", 22, 1 },
+		{ "Core6AccInt", 21, 1 },
+		{ "Core5AccInt", 20, 1 },
+		{ "Core4AccInt", 19, 1 },
+		{ "Core3AccInt", 18, 1 },
+		{ "Core2AccInt", 17, 1 },
+		{ "Core1AccInt", 16, 1 },
+		{ "Timer1Int", 3, 1 },
+		{ "Timer0Int", 2, 1 },
+		{ "PErrNonZero", 1, 1 },
+		{ "uPAccNonZero", 0, 1 },
+	{ "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
+		{ "ConWrErrIntEn", 31, 1 },
+		{ "EEPROMWRIntEn", 30, 1 },
+		{ "TimeOutMAIntEn", 29, 1 },
+		{ "TimeOutIntEn", 28, 1 },
+		{ "RspOvrLookupIntEn", 27, 1 },
+		{ "ReqOvrLookupIntEn", 26, 1 },
+		{ "BlkWrPlIntEn", 25, 1 },
+		{ "BlkRdPlIntEn", 24, 1 },
+		{ "SglWrPlIntEn", 23, 1 },
+		{ "SglRdPlIntEn", 22, 1 },
+		{ "BlkWrCtlIntEn", 21, 1 },
+		{ "BlkRdCtlIntEn", 20, 1 },
+		{ "SglWrCtlIntEn", 19, 1 },
+		{ "SglRdCtlIntEn", 18, 1 },
+		{ "BlkWrEEPROMIntEn", 17, 1 },
+		{ "BlkRdEEPROMIntEn", 16, 1 },
+		{ "SglWrEEPROMIntEn", 15, 1 },
+		{ "SglRdEEPROMIntEn", 14, 1 },
+		{ "BlkWrFlashIntEn", 13, 1 },
+		{ "BlkRdFlashIntEn", 12, 1 },
+		{ "SglWrFlashIntEn", 11, 1 },
+		{ "SglRdFlashIntEn", 10, 1 },
+		{ "BlkWrBootIntEn", 9, 1 },
+		{ "BlkRdBootIntEn", 8, 1 },
+		{ "SglWrBootIntEn", 7, 1 },
+		{ "SglRdBootIntEn", 6, 1 },
+		{ "IllWrBEIntEn", 5, 1 },
+		{ "IllRdBEIntEn", 4, 1 },
+		{ "IllRdIntEn", 3, 1 },
+		{ "IllWrIntEn", 2, 1 },
+		{ "IllTransIntEn", 1, 1 },
+		{ "RsvdSpaceIntEn", 0, 1 },
+	{ "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
+		{ "ConWrErrInt", 31, 1 },
+		{ "EEPROMWRInt", 30, 1 },
+		{ "TimeOutMAInt", 29, 1 },
+		{ "TimeOutInt", 28, 1 },
+		{ "RspOvrLookupInt", 27, 1 },
+		{ "ReqOvrLookupInt", 26, 1 },
+		{ "BlkWrPlInt", 25, 1 },
+		{ "BlkRdPlInt", 24, 1 },
+		{ "SglWrPlInt", 23, 1 },
+		{ "SglRdPlInt", 22, 1 },
+		{ "BlkWrCtlInt", 21, 1 },
+		{ "BlkRdCtlInt", 20, 1 },
+		{ "SglWrCtlInt", 19, 1 },
+		{ "SglRdCtlInt", 18, 1 },
+		{ "BlkWrEEPROMInt", 17, 1 },
+		{ "BlkRdEEPROMInt", 16, 1 },
+		{ "SglWrEEPROMInt", 15, 1 },
+		{ "SglRdEEPROMInt", 14, 1 },
+		{ "BlkWrFlashInt", 13, 1 },
+		{ "BlkRdFlashInt", 12, 1 },
+		{ "SglWrFlashInt", 11, 1 },
+		{ "SglRdFlashInt", 10, 1 },
+		{ "BlkWrBootInt", 9, 1 },
+		{ "BlkRdBootInt", 8, 1 },
+		{ "SglWrBootInt", 7, 1 },
+		{ "SglRdBootInt", 6, 1 },
+		{ "IllWrBEInt", 5, 1 },
+		{ "IllRdBEInt", 4, 1 },
+		{ "IllRdInt", 3, 1 },
+		{ "IllWrInt", 2, 1 },
+		{ "IllTransInt", 1, 1 },
+		{ "RsvdSpaceInt", 0, 1 },
+	{ "CIM_UP_INT_ENABLE", 0x7b38, 0 },
+		{ "Core7AccInt", 22, 1 },
+		{ "Core6AccInt", 21, 1 },
+		{ "Core5AccInt", 20, 1 },
+		{ "Core4AccInt", 19, 1 },
+		{ "Core3AccInt", 18, 1 },
+		{ "Core2AccInt", 17, 1 },
+		{ "Core1AccInt", 16, 1 },
+		{ "SemInt", 8, 1 },
+		{ "RSAInt", 7, 1 },
+		{ "TrngInt", 6, 1 },
+		{ "PeerHaltInt", 5, 1 },
+		{ "MstPlIntEn", 4, 1 },
+		{ "Timer1IntEn", 3, 1 },
+		{ "Timer0IntEn", 2, 1 },
+		{ "PErrNonZero", 1, 1 },
+	{ "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
+		{ "Core7AccInt", 22, 1 },
+		{ "Core6AccInt", 21, 1 },
+		{ "Core5AccInt", 20, 1 },
+		{ "Core4AccInt", 19, 1 },
+		{ "Core3AccInt", 18, 1 },
+		{ "Core2AccInt", 17, 1 },
+		{ "Core1AccInt", 16, 1 },
+		{ "SemInt", 8, 1 },
+		{ "RSAInt", 7, 1 },
+		{ "TrngInt", 6, 1 },
+		{ "PeerHaltInt", 5, 1 },
+		{ "MstPlInt", 4, 1 },
+		{ "Timer1Int", 3, 1 },
+		{ "Timer0Int", 2, 1 },
+		{ "PErrNonZero", 1, 1 },
+		{ "uPAccNonZero", 0, 1 },
+	{ "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
+		{ "ConWrErrInt", 31, 1 },
+		{ "EEPROMWRIntEn", 30, 1 },
+		{ "TimeOutMAIntEn", 29, 1 },
+		{ "TimeOutIntEn", 28, 1 },
+		{ "RspOvrLookupIntEn", 27, 1 },
+		{ "ReqOvrLookupIntEn", 26, 1 },
+		{ "BlkWrPlIntEn", 25, 1 },
+		{ "BlkRdPlIntEn", 24, 1 },
+		{ "SglWrPlIntEn", 23, 1 },
+		{ "SglRdPlIntEn", 22, 1 },
+		{ "BlkWrCtlIntEn", 21, 1 },
+		{ "BlkRdCtlIntEn", 20, 1 },
+		{ "SglWrCtlIntEn", 19, 1 },
+		{ "SglRdCtlIntEn", 18, 1 },
+		{ "BlkWrEEPROMIntEn", 17, 1 },
+		{ "BlkRdEEPROMIntEn", 16, 1 },
+		{ "SglWrEEPROMIntEn", 15, 1 },
+		{ "SglRdEEPROMIntEn", 14, 1 },
+		{ "BlkWrFlashIntEn", 13, 1 },
+		{ "BlkRdFlashIntEn", 12, 1 },
+		{ "SglWrFlashIntEn", 11, 1 },
+		{ "SglRdFlashIntEn", 10, 1 },
+		{ "BlkWrBootIntEn", 9, 1 },
+		{ "BlkRdBootIntEn", 8, 1 },
+		{ "SglWrBootIntEn", 7, 1 },
+		{ "SglRdBootIntEn", 6, 1 },
+		{ "IllWrBEIntEn", 5, 1 },
+		{ "IllRdBEIntEn", 4, 1 },
+		{ "IllRdIntEn", 3, 1 },
+		{ "IllWrIntEn", 2, 1 },
+		{ "IllTransIntEn", 1, 1 },
+		{ "RsvdSpaceIntEn", 0, 1 },
+	{ "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
+		{ "ConWrErrInt", 31, 1 },
+		{ "EEPROMWRInt", 30, 1 },
+		{ "TimeOutMAInt", 29, 1 },
+		{ "TimeOutInt", 28, 1 },
+		{ "RspOvrLookupInt", 27, 1 },
+		{ "ReqOvrLookupInt", 26, 1 },
+		{ "BlkWrPlInt", 25, 1 },
+		{ "BlkRdPlInt", 24, 1 },
+		{ "SglWrPlInt", 23, 1 },
+		{ "SglRdPlInt", 22, 1 },
+		{ "BlkWrCtlInt", 21, 1 },
+		{ "BlkRdCtlInt", 20, 1 },
+		{ "SglWrCtlInt", 19, 1 },
+		{ "SglRdCtlInt", 18, 1 },
+		{ "BlkWrEEPROMInt", 17, 1 },
+		{ "BlkRdEEPROMInt", 16, 1 },
+		{ "SglWrEEPROMInt", 15, 1 },
+		{ "SglRdEEPROMInt", 14, 1 },
+		{ "BlkWrFlashInt", 13, 1 },
+		{ "BlkRdFlashInt", 12, 1 },
+		{ "SglWrFlashInt", 11, 1 },
+		{ "SglRdFlashInt", 10, 1 },
+		{ "BlkWrBootInt", 9, 1 },
+		{ "BlkRdBootInt", 8, 1 },
+		{ "SglWrBootInt", 7, 1 },
+		{ "SglRdBootInt", 6, 1 },
+		{ "IllWrBEInt", 5, 1 },
+		{ "IllRdBEInt", 4, 1 },
+		{ "IllRdInt", 3, 1 },
+		{ "IllWrInt", 2, 1 },
+		{ "IllTransInt", 1, 1 },
+		{ "RsvdSpaceInt", 0, 1 },
+	{ "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
+		{ "MapOffset", 11, 5 },
+		{ "MapSelect", 10, 1 },
+		{ "CoreSelect", 6, 4 },
+		{ "OBQSelect", 5, 1 },
+		{ "IBQSelect", 4, 1 },
+		{ "QueNumSelect", 0, 4 },
+	{ "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
+		{ "Que1KEn", 30, 1 },
+		{ "QueSize", 24, 6 },
+		{ "QueBase", 16, 6 },
+		{ "QueFullThrsh", 0, 9 },
+	{ "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
+		{ "HostBusy", 31, 1 },
+		{ "HostWrite", 30, 1 },
+		{ "HostGrpSel", 28, 2 },
+		{ "HostCoreSel", 24, 4 },
+		{ "HostAddr", 0, 24 },
+	{ "CIM_HOST_ACC_DATA", 0x7b54, 0 },
+	{ "CIM_DEBUG_CFG", 0x7b58, 0 },
+		{ "OR_EN", 20, 1 },
+		{ "USEL", 19, 1 },
+		{ "HI", 18, 1 },
+		{ "SELH", 9, 9 },
+		{ "SELL", 0, 9 },
+	{ "CIM_DEBUG_DATA", 0x7b5c, 0 },
+	{ "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
+		{ "IbqDbgCore", 28, 4 },
+		{ "IbqDbgAddr", 12, 13 },
+		{ "IbqDbgState", 4, 2 },
+		{ "PerrAddrClr", 3, 1 },
+		{ "IbqDbgBusy", 1, 1 },
+		{ "IbqDbgEn", 0, 1 },
+	{ "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
+		{ "ObqDbgCore", 28, 4 },
+		{ "ObqDbgAddr", 12, 13 },
+		{ "ObqDbgState", 4, 2 },
+		{ "ObqDbgBusy", 1, 1 },
+		{ "ObqDbgEn", 0, 1 },
+	{ "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
+	{ "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
+	{ "CIM_DEBUGCFG", 0x7b70, 0 },
+		{ "POLADbgRdPtr", 23, 9 },
+		{ "PILADbgRdPtr", 14, 9 },
+		{ "LAMaskTrig", 13, 1 },
+		{ "LADbgEn", 12, 1 },
+		{ "LAFillOnce", 11, 1 },
+		{ "LAMaskStop", 10, 1 },
+	{ "CIM_DEBUGSTS", 0x7b74, 0 },
+		{ "LAReset", 31, 1 },
+		{ "POLADbgWrPtr", 16, 9 },
+		{ "PILADbgWrPtr", 0, 9 },
+	{ "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
+	{ "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
+	{ "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
+	{ "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
+	{ "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
+	{ "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
+		{ "MEM_ZONE_VA", 4, 28 },
+	{ "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
+		{ "MEM_ZONE_BA", 6, 26 },
+		{ "THREAD_ID", 2, 3 },
+		{ "ZONE_DST", 0, 2 },
+	{ "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
+		{ "MEM_ZONE_LEN", 4, 28 },
+	{ "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
+		{ "Timer1En", 4, 1 },
+		{ "Timer0En", 3, 1 },
+		{ "TimerEn", 1, 1 },
+	{ "CIM_GLB_TIMER", 0x7bf8, 0 },
+	{ "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
+	{ "CIM_TIMER0", 0x7c00, 0 },
+	{ "CIM_TIMER1", 0x7c04, 0 },
+	{ "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
+		{ "DAddrTimeOut", 2, 30 },
+		{ "DAddrTimeOutType", 0, 2 },
+	{ "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
+		{ "DAddrIllegal", 2, 30 },
+		{ "DAddrIllegalType", 0, 2 },
+	{ "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
+	{ "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
+	{ "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
+	{ "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
+	{ "CIM_FPGA_ROM_EFUSE_CMD", 0x7c20, 0 },
+	{ "CIM_FPGA_ROM_EFUSE_DATA", 0x7c24, 0 },
+	{ "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
+	{ "CIM_MA_TIMER_EN", 0x7c2c, 0 },
+		{ "FlashWrPageMore", 5, 1 },
+		{ "FlashWrEnable", 4, 1 },
+		{ "FlashMoreEnable", 3, 1 },
+		{ "wr_resp_enable", 2, 1 },
+		{ "slow_timer_enable", 1, 1 },
+		{ "ma_timer_enable", 0, 1 },
+	{ "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
+	{ "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
+	{ "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 },
+		{ "CIM_ULP_TX_PKT_ERR_CODE", 16, 8 },
+		{ "CIM_PCIE_PKT_ERR_CODE", 8, 8 },
+		{ "CIM_SGE0_PKT_ERR_CODE", 0, 8 },
+	{ "CIM_QUE_PERR_ADDR", 0x7c40, 0 },
+		{ "IbqPerrAddr", 16, 12 },
+		{ "ObqPerrAddr", 0, 12 },
+	{ "CIM_CGEN", 0x7c48, 0 },
+	{ "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 },
+		{ "ulp_obq_size", 8, 2 },
+		{ "tp_ibq_size", 6, 2 },
+		{ "obq_eom_enable", 5, 1 },
+		{ "obq_throuttle_on_eop", 4, 1 },
+		{ "obq_read_ctl_perf_mode_disable", 3, 1 },
+		{ "obq_wait_for_eop_flush_disable", 2, 1 },
+		{ "ibq_rra_dsbl", 1, 1 },
+		{ "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 },
+	{ "CIM_CGEN_GLOBAL", 0x7c50, 0 },
+	{ "CIM_DPSLP_EN", 0x7c54, 0 },
+	{ "CIM_GFT_CMM_CONFIG", 0x7c58, 0 },
+		{ "GlFl", 31, 1 },
+		{ "WrCntIdle", 16, 15 },
+		{ "RdThreshold", 8, 6 },
+		{ "WrThrLevel2", 7, 1 },
+		{ "WrThrLevel1", 6, 1 },
+		{ "WrThrThreshEn", 5, 1 },
+		{ "WrThrThresh", 0, 5 },
+	{ "CIM_GFT_CONFIG", 0x7c5c, 0 },
+		{ "GftMaBase", 16, 16 },
+		{ "GftHashTblSize", 12, 4 },
+		{ "GftTcamPriority", 11, 1 },
+		{ "GftMaThreadId", 8, 3 },
+		{ "GftTcamInit", 7, 1 },
+		{ "GftTcamInitDone", 6, 1 },
+		{ "GftTblModeEn", 0, 1 },
+	{ "CIM_TCAM_BIST_CTRL", 0x7c60, 0 },
+		{ "rst_cb", 31, 1 },
+		{ "cb_start", 0, 28 },
+	{ "CIM_TCAM_BIST_CB_PASS", 0x7c64, 0 },
+	{ "CIM_TCAM_BIST_CB_BUSY", 0x7c68, 0 },
+	{ "CIM_GFT_MASK", 0x7c70, 0 },
+	{ "CIM_GFT_MASK", 0x7c74, 0 },
+	{ "CIM_GFT_MASK", 0x7c78, 0 },
+	{ "CIM_GFT_MASK", 0x7c7c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
+	{ "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
+	{ "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
+		{ "MBWrBusy", 31, 1 },
+	{ "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
+		{ "MBMsgRdyIntEn", 19, 1 },
+	{ "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
+		{ "MBMsgRdyInt", 19, 1 },
+	{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 },
+		{ "MBGeneric", 4, 28 },
+		{ "MBMsgValid", 3, 1 },
+		{ "MBIntReq", 2, 1 },
+		{ "MBOwner", 0, 2 },
+	{ NULL }
+};
+
+struct reg_info t7_tp_regs[] = {
+	{ "TP_IN_CONFIG", 0x7d00, 0 },
+		{ "VLANExtEnPort3", 31, 1 },
+		{ "VLANExtEnPort2", 30, 1 },
+		{ "VLANExtEnPort1", 29, 1 },
+		{ "VLANExtEnPort0", 28, 1 },
+		{ "TcpOptParserDisCh3", 27, 1 },
+		{ "TcpOptParserDisCh2", 26, 1 },
+		{ "TcpOptParserDisCh1", 25, 1 },
+		{ "TcpOptParserDisCh0", 24, 1 },
+		{ "CrcPassPrt3", 23, 1 },
+		{ "CrcPassPrt2", 22, 1 },
+		{ "CrcPassPrt1", 21, 1 },
+		{ "CrcPassPrt0", 20, 1 },
+		{ "VepaMode", 19, 1 },
+		{ "FipUpEn", 18, 1 },
+		{ "FcoeUpEn", 17, 1 },
+		{ "FcoeEnable", 16, 1 },
+		{ "IPv6Enable", 15, 1 },
+		{ "NICMode", 14, 1 },
+		{ "VnTagDefaultVal", 13, 1 },
+		{ "ECheckUDPLen", 12, 1 },
+		{ "EReportUdpHdrLen", 11, 1 },
+		{ "FcoeFPMA", 10, 1 },
+		{ "VnTagEnable", 9, 1 },
+		{ "VnTagEthEnable", 8, 1 },
+		{ "CChecksumCheckIP", 7, 1 },
+		{ "CChecksumCheckUDP", 6, 1 },
+		{ "CChecksumCheckTCP", 5, 1 },
+		{ "CTag", 4, 1 },
+		{ "CXoffOverride", 3, 1 },
+		{ "EthUpEn", 2, 1 },
+		{ "EGreDropEn", 1, 1 },
+		{ "CFastDemuxEn", 0, 1 },
+	{ "TP_OUT_CONFIG", 0x7d04, 0 },
+		{ "PortQfcEn", 28, 4 },
+		{ "EPktDistChn3", 23, 1 },
+		{ "EPktDistChn2", 22, 1 },
+		{ "EPktDistChn1", 21, 1 },
+		{ "EPktDistChn0", 20, 1 },
+		{ "TtlMode", 19, 1 },
+		{ "EQfcDmac", 18, 1 },
+		{ "ELpbkIncMpsStat", 17, 1 },
+		{ "IPIDSplitMode", 16, 1 },
+		{ "ETOEBypCSumNoWait", 15, 1 },
+		{ "ENICCSumNoWait", 14, 1 },
+		{ "CCplAckMode", 13, 1 },
+		{ "RMWHintEnable", 12, 1 },
+		{ "EChecksumInsertTCP", 11, 1 },
+		{ "EChecksumInsertIP", 10, 1 },
+		{ "EVnTagEn", 9, 1 },
+		{ "EV6FlwEn", 8, 1 },
+		{ "EPriority", 7, 1 },
+		{ "EVlanPrio", 6, 1 },
+		{ "CChecksumInsertTCP", 5, 1 },
+		{ "CChecksumInsertIP", 4, 1 },
+		{ "CRxPktEnc", 3, 1 },
+		{ "CCPL", 2, 1 },
+		{ "CRxPktXt", 1, 1 },
+		{ "CEthernet", 0, 1 },
+	{ "TP_GLOBAL_CONFIG", 0x7d08, 0 },
+		{ "RXSACKParse", 31, 1 },
+		{ "RXSACKFwdMode", 29, 2 },
+		{ "SrvrChRssEn", 26, 1 },
+		{ "RXFlowControlDisable", 25, 1 },
+		{ "TXPacingEnable", 24, 1 },
+		{ "LBChnDistEn", 23, 1 },
+		{ "ActiveFilterCounts", 22, 1 },
+		{ "ProtectedMode", 21, 1 },
+		{ "EthTnlLen2x", 20, 1 },
+		{ "EgLBChnDistEn", 19, 1 },
+		{ "FiveTupleLookup", 17, 2 },
+		{ "OfdMpsStats", 16, 1 },
+		{ "DontFragment", 15, 1 },
+		{ "IPIdentSplit", 14, 1 },
+		{ "RssSynSteerEnable", 12, 1 },
+		{ "IssFromCplEnable", 11, 1 },
+		{ "RssLoopbackEnable", 10, 1 },
+		{ "TCAMServerUse", 8, 2 },
+		{ "IPTTL", 0, 8 },
+	{ "TP_DB_CONFIG", 0x7d0c, 0 },
+		{ "DBMaxOpCnt", 24, 8 },
+		{ "CxMaxOpCntDisable", 23, 1 },
+		{ "CxMaxOpCnt", 16, 7 },
+		{ "TxMaxOpCntDisable", 15, 1 },
+		{ "TxMaxOpCnt", 8, 7 },
+		{ "RxMaxOpCntDisable", 7, 1 },
+		{ "RxMaxOpCnt", 0, 7 },
+	{ "TP_CMM_TCB_BASE", 0x7d10, 0 },
+	{ "TP_CMM_MM_BASE", 0x7d14, 0 },
+	{ "TP_CMM_TIMER_BASE", 0x7d18, 0 },
+	{ "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
+		{ "RxPoolSize", 16, 16 },
+		{ "TxPoolSize", 0, 16 },
+	{ "TP_PMM_TX_BASE", 0x7d20, 0 },
+	{ "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
+	{ "TP_PMM_RX_BASE", 0x7d28, 0 },
+	{ "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
+	{ "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
+		{ "PMRxNumChn", 29, 3 },
+		{ "PMRxMaxPage", 0, 21 },
+	{ "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
+	{ "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
+		{ "PMTxNumChn", 29, 3 },
+		{ "PMTxMaxPage", 0, 21 },
+	{ "TP_EXT_CONFIG", 0x7d3c, 0 },
+		{ "TnlErrorIpSecARW", 29, 1 },
+		{ "TnlErrorIpSecICV", 28, 1 },
+		{ "DropErrorIpSecARW", 25, 1 },
+		{ "DropErrorIpSecICV", 24, 1 },
+		{ "MibRdmaRoceEn", 19, 1 },
+		{ "MibRdmaiWarpEn", 18, 1 },
+		{ "BypTxDataAckAllEn", 17, 1 },
+		{ "DataAckExtEn", 16, 1 },
+		{ "MacMatch11Fwd", 11, 1 },
+		{ "UserTmstpEn", 10, 1 },
+		{ "MmgrCacheDis", 9, 1 },
+		{ "TxPktPackOutUdpEn", 8, 1 },
+		{ "IPSecRoCECRCMode", 6, 2 },
+		{ "IPSecIdxLoc", 5, 1 },
+		{ "IPSecIdxCapEn", 4, 1 },
+		{ "IPSecOfEn", 3, 1 },
+		{ "IPSecCfg", 0, 3 },
+	{ "TP_TCP_OPTIONS", 0x7d40, 0 },
+		{ "MTUDefault", 16, 16 },
+		{ "MTUEnable", 10, 1 },
+		{ "SACKTx", 9, 1 },
+		{ "SACKRx", 8, 1 },
+		{ "SACKMode", 4, 2 },
+		{ "WindowScaleMode", 2, 2 },
+		{ "TimestampsMode", 0, 2 },
+	{ "TP_DACK_CONFIG", 0x7d44, 0 },
+		{ "AutoState3", 30, 2 },
+		{ "AutoState2", 28, 2 },
+		{ "AutoState1", 26, 2 },
+		{ "ByteThreshold", 8, 18 },
+		{ "MSSThreshold", 4, 3 },
+		{ "AutoCareful", 2, 1 },
+		{ "AutoEnable", 1, 1 },
+		{ "Mode", 0, 1 },
+	{ "TP_PC_CONFIG", 0x7d48, 0 },
+		{ "EnableFinCheck", 31, 1 },
+		{ "EnableOcspiFull", 30, 1 },
+		{ "EnableFLMErrorDDP", 29, 1 },
+		{ "LockTid", 28, 1 },
+		{ "DisableInvPend", 27, 1 },
+		{ "EnableFilterCount", 26, 1 },
+		{ "RddpCongEn", 25, 1 },
+		{ "EnableOnFlyPDU", 24, 1 },
+		{ "EnableMinRcvWnd", 23, 1 },
+		{ "EnableMaxRcvWnd", 22, 1 },
+		{ "EnableMibVfPld", 21, 1 },
+		{ "TxDeferEnable", 20, 1 },
+		{ "RxCongestionMode", 19, 1 },
+		{ "HearbeatOnceDACK", 18, 1 },
+		{ "HearbeatOnceHeap", 17, 1 },
+		{ "HearbeatDACK", 16, 1 },
+		{ "TxCongestionMode", 15, 1 },
+		{ "AcceptLatestRcvAdv", 14, 1 },
+		{ "DisableSYNData", 13, 1 },
+		{ "DisableWindowPSH", 12, 1 },
+		{ "DisableFINOldData", 11, 1 },
+		{ "EnableFLMError", 10, 1 },
+		{ "EnableOptMtu", 9, 1 },
+		{ "FilterPeerFIN", 8, 1 },
+		{ "EnableFeedbackSend", 7, 1 },
+		{ "EnableRDMAError", 6, 1 },
+		{ "EnableFilterNat", 5, 1 },
+		{ "DisableSepPshFlag", 4, 1 },
+		{ "EnableOfdoVLAN", 3, 1 },
+		{ "DisableTimeWait", 2, 1 },
+		{ "EnableVlanCheck", 1, 1 },
+		{ "TxDataAckPageEnable", 0, 1 },
+	{ "TP_PC_CONFIG2", 0x7d4c, 0 },
+		{ "EnableMtuVfMode", 31, 1 },
+		{ "EnableMibVfMode", 30, 1 },
+		{ "DisableLbkCheck", 29, 1 },
+		{ "EnableUrgDdpOff", 28, 1 },
+		{ "EnableFilterLpbk", 27, 1 },
+		{ "DisableTblMmgr", 26, 1 },
+		{ "CngRecSndNxt", 25, 1 },
+		{ "EnableLbkChn", 24, 1 },
+		{ "EnableLroEcn", 23, 1 },
+		{ "EnablePcmdCheck", 22, 1 },
+		{ "EnableELbkAFull", 21, 1 },
+		{ "EnableCLbkAFull", 20, 1 },
+		{ "EnableOespiFull", 19, 1 },
+		{ "DisableHitCheck", 18, 1 },
+		{ "EnableRssErrCheck", 17, 1 },
+		{ "DisableNewPshFlag", 16, 1 },
+		{ "EnableRddpRcvAdvClr", 15, 1 },
+		{ "EnableFinDdpOff", 14, 1 },
+		{ "EnableArpMiss", 13, 1 },
+		{ "EnableRstPaws", 12, 1 },
+		{ "EnableIPv6RSS", 11, 1 },
+		{ "EnableNonOfdHybRss", 10, 1 },
+		{ "EnableUDP4TupRss", 9, 1 },
+		{ "EnableRxPktTmstpRss", 8, 1 },
+		{ "EnableEPCMDAFull", 7, 1 },
+		{ "EnableCPCMDAFull", 6, 1 },
+		{ "EnableEHdrAFull", 5, 1 },
+		{ "EnableCHdrAFull", 4, 1 },
+		{ "EnableEMacAFull", 3, 1 },
+		{ "EnableNonOfdTidRss", 2, 1 },
+		{ "EnableNonOfdTcbRss", 1, 1 },
+		{ "EnableTnlOfdClosed", 0, 1 },
+	{ "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
+		{ "TimerBackoffIndex3", 24, 8 },
+		{ "TimerBackoffIndex2", 16, 8 },
+		{ "TimerBackoffIndex1", 8, 8 },
+		{ "TimerBackoffIndex0", 0, 8 },
+	{ "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
+		{ "TimerBackoffIndex7", 24, 8 },
+		{ "TimerBackoffIndex6", 16, 8 },
+		{ "TimerBackoffIndex5", 8, 8 },
+		{ "TimerBackoffIndex4", 0, 8 },
+	{ "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
+		{ "TimerBackoffIndex11", 24, 8 },
+		{ "TimerBackoffIndex10", 16, 8 },
+		{ "TimerBackoffIndex9", 8, 8 },
+		{ "TimerBackoffIndex8", 0, 8 },
+	{ "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
+		{ "TimerBackoffIndex15", 24, 8 },
+		{ "TimerBackoffIndex14", 16, 8 },
+		{ "TimerBackoffIndex13", 8, 8 },
+		{ "TimerBackoffIndex12", 0, 8 },
+	{ "TP_PARA_REG0", 0x7d60, 0 },
+		{ "LimTxThresh", 28, 4 },
+		{ "InitCwndIdle", 27, 1 },
+		{ "InitCwnd", 24, 3 },
+		{ "DupAckThresh", 20, 4 },
+		{ "EcnCngFifo", 19, 1 },
+		{ "EcnSynAck", 18, 1 },
+		{ "EcnThresh", 16, 2 },
+		{ "EcnMode", 15, 1 },
+		{ "EcnModeCwr", 14, 1 },
+		{ "SetTimeEnable", 13, 1 },
+		{ "CplErrEnable", 12, 1 },
+		{ "FastTnlCnt", 11, 1 },
+		{ "ForceShove", 10, 1 },
+		{ "TpTcamKey", 9, 1 },
+		{ "SwsMode", 8, 1 },
+		{ "TsmpMode", 6, 2 },
+		{ "ByteCountLimit", 4, 2 },
+		{ "SwsShove", 3, 1 },
+		{ "TblTimer", 2, 1 },
+		{ "RxtPace", 1, 1 },
+		{ "SwsTimer", 0, 1 },
+	{ "TP_PARA_REG1", 0x7d64, 0 },
+		{ "InitRwnd", 16, 16 },
+		{ "InitialSSThresh", 0, 16 },
+	{ "TP_PARA_REG2", 0x7d68, 0 },
+		{ "MaxRxData", 16, 16 },
+		{ "RxCoalesceSize", 0, 16 },
+	{ "TP_PARA_REG3", 0x7d6c, 0 },
+		{ "EnableTnlCngLpbk", 31, 1 },
+		{ "EnableTnlCngFifo", 30, 1 },
+		{ "EnableTnlCngHdr", 29, 1 },
+		{ "EnableTnlCngSge", 28, 1 },
+		{ "RxMacCheck", 27, 1 },
+		{ "RxSynFilter", 26, 1 },
+		{ "CngCtrlECN", 25, 1 },
+		{ "RxDdpOffInit", 24, 1 },
+		{ "TunnelCngDrop3", 23, 1 },
+		{ "TunnelCngDrop2", 22, 1 },
+		{ "TunnelCngDrop1", 21, 1 },
+		{ "TunnelCngDrop0", 20, 1 },
+		{ "TxDataAckIdx", 16, 4 },
+		{ "RxFragEnable", 12, 3 },
+		{ "TxPaceFixedStrict", 11, 1 },
+		{ "TxPaceAutoStrict", 10, 1 },
+		{ "TxPaceFixed", 9, 1 },
+		{ "TxPaceAuto", 8, 1 },
+		{ "RxChnTunnel", 7, 1 },
+		{ "RxUrgTunnel", 6, 1 },
+		{ "RxUrgMode", 5, 1 },
+		{ "TxUrgMode", 4, 1 },
+		{ "CngCtrlMode", 2, 2 },
+		{ "RxCoalesceEnable", 1, 1 },
+		{ "RxCoalescePshEn", 0, 1 },
+	{ "TP_PARA_REG4", 0x7d70, 0 },
+		{ "IdleCwndHighSpeed", 28, 1 },
+		{ "RxmtCwndHighSpeed", 27, 1 },
+		{ "OverdriveHighSpeed", 25, 2 },
+		{ "ByteCountHighSpeed", 24, 1 },
+		{ "IdleCwndNewReno", 20, 1 },
+		{ "RxmtCwndNewReno", 19, 1 },
+		{ "OverdriveNewReno", 17, 2 },
+		{ "ByteCountNewReno", 16, 1 },
+		{ "IdleCwndTahoe", 12, 1 },
+		{ "RxmtCwndTahoe", 11, 1 },
+		{ "OverdriveTahoe", 9, 2 },
+		{ "ByteCountTahoe", 8, 1 },
+		{ "IdleCwndReno", 4, 1 },
+		{ "RxmtCwndReno", 3, 1 },
+		{ "OverdriveReno", 1, 2 },
+		{ "ByteCountReno", 0, 1 },
+	{ "TP_PARA_REG5", 0x7d74, 0 },
+		{ "IndicateSize", 16, 16 },
+		{ "MaxProxySize", 12, 4 },
+		{ "EnableReadPdu", 11, 1 },
+		{ "EnableReadAhead", 10, 1 },
+		{ "EmptyRqEnable", 9, 1 },
+		{ "SchdEnable", 8, 1 },
+		{ "EnableXoffPdu", 7, 1 },
+		{ "EnableFcoeCheck", 6, 1 },
+		{ "EnableFragCheck", 5, 1 },
+		{ "RearmDdpOffset", 4, 1 },
+		{ "ResetDdpOffset", 3, 1 },
+		{ "OnFlyDDPEnable", 2, 1 },
+		{ "EnableRdmaFix", 1, 1 },
+		{ "PushTimerEnable", 0, 1 },
+	{ "TP_PARA_REG6", 0x7d78, 0 },
+		{ "TxPDUSizeAdj", 24, 8 },
+		{ "TxTcamKey", 22, 1 },
+		{ "EnableCByp", 21, 1 },
+		{ "DisablePDUAck", 20, 1 },
+		{ "EnableCSav", 19, 1 },
+		{ "EnableDeferPDU", 18, 1 },
+		{ "EnableFlush", 17, 1 },
+		{ "EnableBytePersist", 16, 1 },
+		{ "DisableTmoCng", 15, 1 },
+		{ "EnableReadAhead", 14, 1 },
+		{ "AllowExeption", 13, 1 },
+		{ "EnableDeferACK", 12, 1 },
+		{ "EnableESnd", 11, 1 },
+		{ "EnableCSnd", 10, 1 },
+		{ "EnablePDUE", 9, 1 },
+		{ "EnablePDUC", 8, 1 },
+		{ "EnableBUFI", 7, 1 },
+		{ "EnableBUFE", 6, 1 },
+		{ "EnableDefer", 5, 1 },
+		{ "EnableClearRxmtOos", 4, 1 },
+		{ "DisablePDUCng", 3, 1 },
+		{ "DisablePDUTimeout", 2, 1 },
+		{ "DisablePDURxmt", 1, 1 },
+		{ "DisablePDUxmt", 0, 1 },
+	{ "TP_PARA_REG7", 0x7d7c, 0 },
+		{ "PMMaxXferLen1", 16, 16 },
+		{ "PMMaxXferLen0", 0, 16 },
+	{ "TP_ENG_CONFIG", 0x7d80, 0 },
+		{ "TableLatencyDone", 28, 4 },
+		{ "TableLatencyStart", 24, 4 },
+		{ "EngineLatencyDelta", 16, 4 },
+		{ "EngineLatencyMmgr", 12, 4 },
+		{ "EngineLatencyWireIp6", 8, 4 },
+		{ "EngineLatencyWire", 4, 4 },
+		{ "EngineLatencyBase", 0, 4 },
+	{ "TP_PARA_REG8", 0x7d84, 0 },
+		{ "EcnAckEct", 2, 1 },
+		{ "EcnFinEct", 1, 1 },
+		{ "EcnSynEct", 0, 1 },
+	{ "TP_PARA_REG9", 0x7d88, 0 },
+		{ "PMMaxXferLen3", 16, 16 },
+		{ "PMMaxXferLen2", 0, 16 },
+	{ "TP_ERR_CONFIG", 0x7d8c, 0 },
+		{ "TnlErrorFPMA", 31, 1 },
+		{ "TnlErrorPing", 30, 1 },
+		{ "TnlErrorCsum", 29, 1 },
+		{ "TnlErrorCsumIP", 28, 1 },
+		{ "TnlErrorOpaque", 27, 1 },
+		{ "TnlErrorIp6Opt", 26, 1 },
+		{ "TnlErrorTcpOpt", 25, 1 },
+		{ "TnlErrorPktLen", 24, 1 },
+		{ "TnlErrorTcpHdrLen", 23, 1 },
+		{ "TnlErrorIpHdrLen", 22, 1 },
+		{ "TnlErrorEthHdrLen", 21, 1 },
+		{ "TnlErrorAttack", 20, 1 },
+		{ "TnlErrorFrag", 19, 1 },
+		{ "TnlErrorIpVer", 18, 1 },
+		{ "TnlErrorMac", 17, 1 },
+		{ "TnlErrorAny", 16, 1 },
+		{ "DropErrorFPMA", 15, 1 },
+		{ "DropErrorPing", 14, 1 },
+		{ "DropErrorCsum", 13, 1 },
+		{ "DropErrorCsumIP", 12, 1 },
+		{ "DropErrorOpaque", 11, 1 },
+		{ "DropErrorIp6Opt", 10, 1 },
+		{ "DropErrorTcpOpt", 9, 1 },
+		{ "DropErrorPktLen", 8, 1 },
+		{ "DropErrorTcpHdrLen", 7, 1 },
+		{ "DropErrorIpHdrLen", 6, 1 },
+		{ "DropErrorEthHdrLen", 5, 1 },
+		{ "DropErrorAttack", 4, 1 },
+		{ "DropErrorFrag", 3, 1 },
+		{ "DropErrorIpVer", 2, 1 },
+		{ "DropErrorMac", 1, 1 },
+		{ "DropErrorAny", 0, 1 },
+	{ "TP_TIMER_RESOLUTION", 0x7d90, 0 },
+		{ "RoceTimerResolution", 24, 8 },
+		{ "TimerResolution", 16, 8 },
+		{ "TimestampResolution", 8, 8 },
+		{ "DelayedACKResolution", 0, 8 },
+	{ "TP_MSL", 0x7d94, 0 },
+	{ "TP_RXT_MIN", 0x7d98, 0 },
+	{ "TP_RXT_MAX", 0x7d9c, 0 },
+	{ "TP_PERS_MIN", 0x7da0, 0 },
+	{ "TP_PERS_MAX", 0x7da4, 0 },
+	{ "TP_KEEP_IDLE", 0x7da8, 0 },
+	{ "TP_KEEP_INTVL", 0x7dac, 0 },
+	{ "TP_INIT_SRTT", 0x7db0, 0 },
+		{ "MaxRtt", 16, 16 },
+		{ "InitSrtt", 0, 16 },
+	{ "TP_DACK_TIMER", 0x7db4, 0 },
+	{ "TP_FINWAIT2_TIMER", 0x7db8, 0 },
+	{ "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
+	{ "TP_SHIFT_CNT", 0x7dc0, 0 },
+		{ "SynShiftMax", 24, 4 },
+		{ "RxtShiftMaxR1", 20, 4 },
+		{ "RxtShiftMaxR2", 16, 4 },
+		{ "PerShiftBackoffMax", 12, 4 },
+		{ "PerShiftMax", 8, 4 },
+		{ "KeepaliveMaxR1", 4, 4 },
+		{ "KeepaliveMaxR2", 0, 4 },
+	{ "TP_TM_CONFIG", 0x7dc4, 0 },
+	{ "TP_TIME_LO", 0x7dc8, 0 },
+	{ "TP_TIME_HI", 0x7dcc, 0 },
+	{ "TP_PORT_MTU_0", 0x7dd0, 0 },
+		{ "Port1MTUValue", 16, 16 },
+		{ "Port0MTUValue", 0, 16 },
+	{ "TP_PORT_MTU_1", 0x7dd4, 0 },
+		{ "Port3MTUValue", 16, 16 },
+		{ "Port2MTUValue", 0, 16 },
+	{ "TP_PACE_TABLE", 0x7dd8, 0 },
+	{ "TP_CCTRL_TABLE", 0x7ddc, 0 },
+		{ "RowIndex", 16, 16 },
+		{ "RowValue", 0, 16 },
+	{ "TP_MTU_TABLE", 0x7de4, 0 },
+		{ "MTUIndex", 24, 8 },
+		{ "MTUWidth", 16, 4 },
+		{ "MTUValue", 0, 14 },
+	{ "TP_ULP_TABLE", 0x7de8, 0 },
+		{ "ULPType7Length", 31, 1 },
+		{ "ULPType7Offset", 28, 3 },
+		{ "ULPType6Length", 27, 1 },
+		{ "ULPType6Offset", 24, 3 },
+		{ "ULPType5Length", 23, 1 },
+		{ "ULPType5Offset", 20, 3 },
+		{ "ULPType4Length", 19, 1 },
+		{ "ULPType4Offset", 16, 3 },
+		{ "ULPType3Length", 15, 1 },
+		{ "ULPType3Offset", 12, 3 },
+		{ "ULPType2Length", 11, 1 },
+		{ "ULPType2Offset", 8, 3 },
+		{ "ULPType1Length", 7, 1 },
+		{ "ULPType1Offset", 4, 3 },
+		{ "ULPType0Length", 3, 1 },
+		{ "ULPType0Offset", 0, 3 },
+	{ "TP_RSS_LKP_TABLE", 0x7dec, 0 },
+		{ "LkpTblQueue1", 10, 10 },
+		{ "LkpTblQueue0", 0, 10 },
+	{ "TP_RSS_CONFIG", 0x7df0, 0 },
+		{ "TNL4tupEnIpv6", 31, 1 },
+		{ "TNL2tupEnIpv6", 30, 1 },
+		{ "TNL4tupEnIpv4", 29, 1 },
+		{ "TNL2tupEnIpv4", 28, 1 },
+		{ "TNLTcpSel", 27, 1 },
+		{ "TNLIp6Sel", 26, 1 },
+		{ "TNLVrtSel", 25, 1 },
+		{ "TNLMapEn", 24, 1 },
+		{ "TNLFcoeMode", 23, 1 },
+		{ "TNLFcoeSid", 22, 1 },
+		{ "TNLFcoeEn", 21, 1 },
+		{ "HashXor", 20, 1 },
+		{ "OFDHashSave", 19, 1 },
+		{ "OFDVrtSel", 18, 1 },
+		{ "OFDMapEn", 17, 1 },
+		{ "OFDLkpEn", 16, 1 },
+		{ "SYN4tupEnIpv6", 15, 1 },
+		{ "SYN2tupEnIpv6", 14, 1 },
+		{ "SYN4tupEnIpv4", 13, 1 },
+		{ "SYN2tupEnIpv4", 12, 1 },
+		{ "SYNIp6Sel", 11, 1 },
+		{ "SYNVrtSel", 10, 1 },
+		{ "SYNMapEn", 9, 1 },
+		{ "SYNLkpEn", 8, 1 },
+		{ "ChannelEnable", 7, 1 },
+		{ "PortEnable", 6, 1 },
+		{ "TNLAllLookup", 5, 1 },
+		{ "VirtEnable", 4, 1 },
+		{ "CongestionEnable", 3, 1 },
+		{ "HashToeplitz", 2, 1 },
+		{ "UdpEnable", 1, 1 },
+		{ "Disable", 0, 1 },
+	{ "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
+		{ "MaskSize", 28, 4 },
+		{ "MaskFilter", 16, 11 },
+		{ "HashAll", 2, 1 },
+		{ "HashEth", 1, 1 },
+		{ "UseWireCh", 0, 1 },
+	{ "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
+		{ "MaskSize", 28, 4 },
+		{ "RRCPLMapEn", 20, 1 },
+		{ "RRCPLQueWidth", 16, 4 },
+		{ "FrmwrQueMask", 12, 4 },
+		{ "RRCPLOpt1SMSelEn", 11, 1 },
+		{ "RRCPLOpt1BQEn", 10, 1 },
+	{ "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
+		{ "MaskSize", 28, 4 },
+		{ "UseWireCh", 0, 1 },
+	{ "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
+		{ "VfPerrEn", 23, 1 },
+		{ "KeyPerrEn", 22, 1 },
+		{ "VfVlanEn", 21, 1 },
+		{ "VfFwEn", 20, 1 },
+		{ "HashDelay", 16, 4 },
+		{ "KeyMode", 6, 2 },
+	{ "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
+		{ "ChnCount3", 31, 1 },
+		{ "ChnCount2", 30, 1 },
+		{ "ChnCount1", 29, 1 },
+		{ "ChnCount0", 28, 1 },
+		{ "ChnUndFlow3", 27, 1 },
+		{ "ChnUndFlow2", 26, 1 },
+		{ "ChnUndFlow1", 25, 1 },
+		{ "ChnUndFlow0", 24, 1 },
+		{ "ChnOvrFlow3", 23, 1 },
+		{ "ChnOvrFlow2", 22, 1 },
+		{ "ChnOvrFlow1", 21, 1 },
+		{ "ChnOvrFlow0", 20, 1 },
+		{ "UpdVld", 19, 1 },
+		{ "Xoff", 18, 1 },
+		{ "UpdChn3", 17, 1 },
+		{ "UpdChn2", 16, 1 },
+		{ "UpdChn1", 15, 1 },
+		{ "UpdChn0", 14, 1 },
+		{ "Queue", 0, 14 },
+	{ "TP_RSS_CONFIG_4CH", 0x7e08, 0 },
+		{ "BaseQIDEn", 1, 1 },
+		{ "200GMode", 0, 1 },
+	{ "TP_RSS_CONFIG_SRAM", 0x7e0c, 0 },
+		{ "SramRdDis", 20, 1 },
+		{ "SramStart", 19, 1 },
+		{ "SramWrite", 18, 1 },
+		{ "SramSel", 16, 2 },
+		{ "SramAddr", 0, 14 },
+	{ "TP_LA_TABLE_0", 0x7e10, 0 },
+		{ "VirtPort1Table", 16, 16 },
+		{ "VirtPort0Table", 0, 16 },
+	{ "TP_LA_TABLE_1", 0x7e14, 0 },
+		{ "VirtPort3Table", 16, 16 },
+		{ "VirtPort2Table", 0, 16 },
+	{ "TP_TM_PIO_ADDR", 0x7e18, 0 },
+	{ "TP_TM_PIO_DATA", 0x7e1c, 0 },
+	{ "TP_RX_MOD_CONFIG_CH3_CH2", 0x7e20, 0 },
+		{ "RxChannelWeight3", 8, 8 },
+		{ "RXChannelWeight2", 0, 8 },
+	{ "TP_MOD_CONFIG", 0x7e24, 0 },
+		{ "RxChannelWeight1", 24, 8 },
+		{ "RXChannelWeight0", 16, 8 },
+		{ "TimerMode", 8, 8 },
+		{ "TxChannelXoffEn", 0, 4 },
+	{ "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
+		{ "RX_MOD_WEIGHT", 24, 8 },
+		{ "TX_MOD_WEIGHT", 16, 8 },
+		{ "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
+	{ "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
+	{ "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
+		{ "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
+	{ "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
+		{ "CH3", 24, 8 },
+		{ "CH2", 16, 8 },
+		{ "CH1", 8, 8 },
+		{ "CH0", 0, 8 },
+	{ "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
+		{ "RX_MOD_RATE_LIMIT_INC", 24, 8 },
+		{ "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
+		{ "TX_MOD_RATE_LIMIT_INC", 8, 8 },
+		{ "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
+	{ "TP_PIO_ADDR", 0x7e40, 0 },
+	{ "TP_PIO_DATA", 0x7e44, 0 },
+	{ "TP_RESET", 0x7e4c, 0 },
+		{ "FlstInitEnable", 1, 1 },
+		{ "TPReset", 0, 1 },
+	{ "TP_MIB_INDEX", 0x7e50, 0 },
+	{ "TP_MIB_DATA", 0x7e54, 0 },
+	{ "TP_SYNC_TIME_HI", 0x7e58, 0 },
+	{ "TP_SYNC_TIME_LO", 0x7e5c, 0 },
+	{ "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
+	{ "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
+	{ "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
+	{ "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
+	{ "TP_INT_ENABLE", 0x7e70, 0 },
+		{ "FlmTxFlstEmpty", 30, 1 },
+		{ "TpCerr", 5, 1 },
+		{ "OtherPerr", 4, 1 },
+		{ "TpeIng1Perr", 3, 1 },
+		{ "TpeIng0Perr", 2, 1 },
+		{ "TpeEgPerr", 1, 1 },
+		{ "TpcPerr", 0, 1 },
+	{ "TP_INT_CAUSE", 0x7e74, 0 },
+		{ "FlmTxFlstEmpty", 30, 1 },
+		{ "TpCerr", 5, 1 },
+		{ "OtherPerr", 4, 1 },
+		{ "TpeIng1Perr", 3, 1 },
+		{ "TpeIng0Perr", 2, 1 },
+		{ "TpeEgPerr", 1, 1 },
+		{ "TpcPerr", 0, 1 },
+	{ "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
+	{ "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
+		{ "FreeRxPageChn", 28, 3 },
+		{ "FreeRxPageCount", 0, 21 },
+	{ "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
+		{ "FreeTxPageChn", 28, 3 },
+		{ "FreeTxPageCount", 0, 21 },
+	{ "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
+	{ "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
+	{ "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
+	{ "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
+	{ "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
+	{ "TP_MOD_POP_CNT", 0x7ea0, 0 },
+	{ "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
+		{ "TimerSeparator", 16, 16 },
+		{ "DisableTimeFreeze", 0, 1 },
+	{ "TP_STAMP_TIME", 0x7ea8, 0 },
+	{ "TP_DEBUG_FLAGS", 0x7eac, 0 },
+		{ "RxTimerCompBuffer", 27, 1 },
+		{ "RxTimerDackFirst", 26, 1 },
+		{ "RxTimerDack", 25, 1 },
+		{ "RxTimerHeartbeat", 24, 1 },
+		{ "RxPawsDrop", 23, 1 },
+		{ "RxUrgDataDrop", 22, 1 },
+		{ "RxFutureData", 21, 1 },
+		{ "RxRcvRxmData", 20, 1 },
+		{ "RxRcvOooDataFin", 19, 1 },
+		{ "RxRcvOooData", 18, 1 },
+		{ "RxRcvWndZero", 17, 1 },
+		{ "RxRcvWndLtMss", 16, 1 },
+		{ "TxDfrFast", 13, 1 },
+		{ "TxRxmMisc", 12, 1 },
+		{ "TxDupAckInc", 11, 1 },
+		{ "TxRxmUrg", 10, 1 },
+		{ "TxRxmFin", 9, 1 },
+		{ "TxRxmSyn", 8, 1 },
+		{ "TxRxmNewReno", 7, 1 },
+		{ "TxRxmFast", 6, 1 },
+		{ "TxRxmTimer", 5, 1 },
+		{ "TxRxmTimerKeepalive", 4, 1 },
+		{ "TxRxmTimerPersist", 3, 1 },
+		{ "TxRcvAdvShrunk", 2, 1 },
+		{ "TxRcvAdvZero", 1, 1 },
+		{ "TxRcvAdvLtMss", 0, 1 },
+	{ "TP_RX_SCHED", 0x7eb0, 0 },
+		{ "CommitReset3", 7, 1 },
+		{ "CommitReset2", 6, 1 },
+		{ "CommitReset1", 5, 1 },
+		{ "CommitReset0", 4, 1 },
+		{ "ForceCong3", 3, 1 },
+		{ "ForceCong2", 2, 1 },
+		{ "ForceCong1", 1, 1 },
+		{ "ForceCong0", 0, 1 },
+	{ "TP_TX_SCHED", 0x7eb4, 0 },
+		{ "CommitReset3", 31, 1 },
+		{ "CommitReset2", 30, 1 },
+		{ "CommitReset1", 29, 1 },
+		{ "CommitReset0", 28, 1 },
+		{ "ForceCong3", 27, 1 },
+		{ "ForceCong2", 26, 1 },
+		{ "ForceCong1", 25, 1 },
+		{ "ForceCong0", 24, 1 },
+		{ "CommitLimit3", 18, 6 },
+		{ "CommitLimit2", 12, 6 },
+		{ "CommitLimit1", 6, 6 },
+		{ "CommitLimit0", 0, 6 },
+	{ "TP_FX_SCHED", 0x7eb8, 0 },
+		{ "TxChnXoff3", 19, 1 },
+		{ "TxChnXoff2", 18, 1 },
+		{ "TxChnXoff1", 17, 1 },
+		{ "TxChnXoff0", 16, 1 },
+		{ "TxModXoff7", 15, 1 },
+		{ "TxModXoff6", 14, 1 },
+		{ "TxModXoff5", 13, 1 },
+		{ "TxModXoff4", 12, 1 },
+		{ "TxModXoff3", 11, 1 },
+		{ "TxModXoff2", 10, 1 },
+		{ "TxModXoff1", 9, 1 },
+		{ "TxModXoff0", 8, 1 },
+		{ "RxChnXoff3", 7, 1 },
+		{ "RxChnXoff2", 6, 1 },
+		{ "RxChnXoff1", 5, 1 },
+		{ "RxChnXoff0", 4, 1 },
+		{ "RxModXoff3", 3, 1 },
+		{ "RxModXoff2", 2, 1 },
+		{ "RxModXoff1", 1, 1 },
+		{ "RxModXoff0", 0, 1 },
+	{ "TP_TX_ORATE", 0x7ebc, 0 },
+		{ "OfdRate3", 24, 8 },
+		{ "OfdRate2", 16, 8 },
+		{ "OfdRate1", 8, 8 },
+		{ "OfdRate0", 0, 8 },
+	{ "TP_IX_SCHED0", 0x7ec0, 0 },
+	{ "TP_IX_SCHED1", 0x7ec4, 0 },
+	{ "TP_IX_SCHED2", 0x7ec8, 0 },
+	{ "TP_IX_SCHED3", 0x7ecc, 0 },
+	{ "TP_TX_TRATE", 0x7ed0, 0 },
+		{ "TnlRate3", 24, 8 },
+		{ "TnlRate2", 16, 8 },
+		{ "TnlRate1", 8, 8 },
+		{ "TnlRate0", 0, 8 },
+	{ "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
+		{ "DbgLaOpcEnable", 24, 8 },
+		{ "DbgLaWhlf", 23, 1 },
+		{ "DbgLaWptr", 16, 7 },
+		{ "DbgLaMode", 14, 2 },
+		{ "DbgLaFatalFreeze", 13, 1 },
+		{ "DbgLaEnable", 12, 1 },
+		{ "DbgLaRptr", 0, 7 },
+	{ "TP_DBG_LA_DATAL", 0x7ed8, 0 },
+	{ "TP_DBG_LA_DATAH", 0x7edc, 0 },
+	{ "TP_DBG_LA_FILTER", 0x7ee0, 0 },
+		{ "FilterTid", 12, 20 },
+		{ "EnTidFilter", 5, 1 },
+		{ "EnOffload", 4, 1 },
+		{ "EnTunnel", 3, 1 },
+		{ "EnI", 2, 1 },
+		{ "EnC", 1, 1 },
+		{ "EnE", 0, 1 },
+	{ "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
+		{ "WriteEnable", 31, 1 },
+		{ "TcamEnable", 10, 1 },
+		{ "BlockSelect", 8, 2 },
+		{ "LineAddress", 1, 7 },
+		{ "RequestDone", 0, 1 },
+	{ "TP_PROTOCOL_DATA0", 0x7eec, 0 },
+	{ "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
+	{ "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
+	{ "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
+	{ "TP_PROTOCOL_DATA4", 0x7efc, 0 },
+	{ "TP_INIC_CTRL0", 0x7f00, 0 },
+	{ "TP_INIC_DBG", 0x7f04, 0 },
+	{ "TP_INIC_PERR_ENABLE", 0x7f08, 0 },
+		{ "inicMac1_err", 16, 6 },
+		{ "inicMac0_err", 0, 6 },
+	{ "TP_INIC_PERR_CAUSE", 0x7f0c, 0 },
+		{ "inicMac1_err", 16, 6 },
+		{ "inicMac0_err", 0, 6 },
+	{ "TP_PARA_REG10", 0x7f20, 0 },
+		{ "Dis39320Fix", 20, 1 },
+		{ "iWARPMaxPduLen", 16, 4 },
+		{ "TlsMaxRxData", 0, 16 },
+	{ "TP_TCAM_BIST_CTRL", 0x7f24, 0 },
+		{ "rst_cb", 31, 1 },
+		{ "cb_start", 0, 28 },
+	{ "TP_TCAM_BIST_CB_PASS", 0x7f28, 0 },
+	{ "TP_TCAM_BIST_CB_BUSY", 0x7f2c, 0 },
+	{ "TP_C_PERR_ENABLE", 0x7f30, 0 },
+		{ "DmxFifoOvfl", 26, 1 },
+		{ "URx2TpcDdpIntf", 25, 1 },
+		{ "TpcDispTokenFifo", 24, 1 },
+		{ "TpcDispCplFifo3", 23, 1 },
+		{ "TpcDispCplFifo2", 22, 1 },
+		{ "TpcDispCplFifo1", 21, 1 },
+		{ "TpcDispCplFifo0", 20, 1 },
+		{ "URxPldIntfCrc3", 19, 1 },
+		{ "URxPldIntfCrc2", 18, 1 },
+		{ "URxPldIntfCrc1", 17, 1 },
+		{ "URxPldIntfCrc0", 16, 1 },
+		{ "DmxDbFifo", 15, 1 },
+		{ "DmxDbSram", 14, 1 },
+		{ "DmxCplFifo", 13, 1 },
+		{ "DmxCplSram", 12, 1 },
+		{ "DmxCsumFifo", 11, 1 },
+		{ "DmxLenFifo", 10, 1 },
+		{ "DmxCheckFifo", 9, 1 },
+		{ "DmxWinFifo", 8, 1 },
+		{ "EgTokenFifo", 7, 1 },
+		{ "EgDataFifo", 6, 1 },
+		{ "Utx2TpcIntf3", 5, 1 },
+		{ "Utx2TpcIntf2", 4, 1 },
+		{ "Utx2TpcIntf1", 3, 1 },
+		{ "Utx2TpcIntf0", 2, 1 },
+		{ "LbkTokenFifo", 1, 1 },
+		{ "LbkDataFifo", 0, 1 },
+	{ "TP_C_PERR_CAUSE", 0x7f34, 0 },
+		{ "DmxFifoOvfl", 26, 1 },
+		{ "URx2TpcDdpIntf", 25, 1 },
+		{ "TpcDispTokenFifo", 24, 1 },
+		{ "TpcDispCplFifo3", 23, 1 },
+		{ "TpcDispCplFifo2", 22, 1 },
+		{ "TpcDispCplFifo1", 21, 1 },
+		{ "TpcDispCplFifo0", 20, 1 },
+		{ "URxPldIntfCrc3", 19, 1 },
+		{ "URxPldIntfCrc2", 18, 1 },
+		{ "URxPldIntfCrc1", 17, 1 },
+		{ "URxPldIntfCrc0", 16, 1 },
+		{ "DmxDbFifo", 15, 1 },
+		{ "DmxDbSram", 14, 1 },
+		{ "DmxCplFifo", 13, 1 },
+		{ "DmxCplSram", 12, 1 },
+		{ "DmxCsumFifo", 11, 1 },
+		{ "DmxLenFifo", 10, 1 },
+		{ "DmxCheckFifo", 9, 1 },
+		{ "DmxWinFifo", 8, 1 },
+		{ "EgTokenFifo", 7, 1 },
+		{ "EgDataFifo", 6, 1 },
+		{ "Utx2TpcIntf3", 5, 1 },
+		{ "Utx2TpcIntf2", 4, 1 },
+		{ "Utx2TpcIntf1", 3, 1 },
+		{ "Utx2TpcIntf0", 2, 1 },
+		{ "LbkTokenFifo", 1, 1 },
+		{ "LbkDataFifo", 0, 1 },
+	{ "TP_E_EG_PERR_ENABLE", 0x7f38, 0 },
+		{ "MpsLpbkTokenFifo", 25, 1 },
+		{ "MpsMacTokenFifo", 24, 1 },
+		{ "DispIpSecFifo3", 23, 1 },
+		{ "DispTcpFifo3", 22, 1 },
+		{ "DispIpFifo3", 21, 1 },
+		{ "DispEthFifo3", 20, 1 },
+		{ "DispGreFifo3", 19, 1 },
+		{ "DispCpl5Fifo3", 18, 1 },
+		{ "DispIpSecFifo2", 17, 1 },
+		{ "DispTcpFifo2", 16, 1 },
+		{ "DispIpFifo2", 15, 1 },
+		{ "DispEthFifo2", 14, 1 },
+		{ "DispGreFifo2", 13, 1 },
+		{ "DispCpl5Fifo2", 12, 1 },
+		{ "DispIpSecFifo1", 11, 1 },
+		{ "DispTcpFifo1", 10, 1 },
+		{ "DispIpFifo1", 9, 1 },
+		{ "DispEthFifo1", 8, 1 },
+		{ "DispGreFifo1", 7, 1 },
+		{ "DispCpl5Fifo1", 6, 1 },
+		{ "DispIpSecFifo0", 5, 1 },
+		{ "DispTcpFifo0", 4, 1 },
+		{ "DispIpFifo0", 3, 1 },
+		{ "DispEthFifo0", 2, 1 },
+		{ "DispGreFifo0", 1, 1 },
+		{ "DispCpl5Fifo0", 0, 1 },
+	{ "TP_E_EG_PERR_CAUSE", 0x7f3c, 0 },
+		{ "MpsLpbkTokenFifo", 25, 1 },
+		{ "MpsMacTokenFifo", 24, 1 },
+		{ "DispIpSecFifo3", 23, 1 },
+		{ "DispTcpFifo3", 22, 1 },
+		{ "DispIpFifo3", 21, 1 },
+		{ "DispEthFifo3", 20, 1 },
+		{ "DispGreFifo3", 19, 1 },
+		{ "DispCpl5Fifo3", 18, 1 },
+		{ "DispIpSecFifo2", 17, 1 },
+		{ "DispTcpFifo2", 16, 1 },
+		{ "DispIpFifo2", 15, 1 },
+		{ "DispEthFifo2", 14, 1 },
+		{ "DispGreFifo2", 13, 1 },
+		{ "DispCpl5Fifo2", 12, 1 },
+		{ "DispIpSecFifo1", 11, 1 },
+		{ "DispTcpFifo1", 10, 1 },
+		{ "DispIpFifo1", 9, 1 },
+		{ "DispEthFifo1", 8, 1 },
+		{ "DispGreFifo1", 7, 1 },
+		{ "DispCpl5Fifo1", 6, 1 },
+		{ "DispIpSecFifo0", 5, 1 },
+		{ "DispTcpFifo0", 4, 1 },
+		{ "DispIpFifo0", 3, 1 },
+		{ "DispEthFifo0", 2, 1 },
+		{ "DispGreFifo0", 1, 1 },
+		{ "DispCpl5Fifo0", 0, 1 },
+	{ "TP_E_IN0_PERR_ENABLE", 0x7f40, 0 },
+		{ "DmxIssFifo", 30, 1 },
+		{ "DmxErrFifo", 29, 1 },
+		{ "DmxAttFifo", 28, 1 },
+		{ "DmxTcpFifo", 27, 1 },
+		{ "DmxMpaFifo", 26, 1 },
+		{ "DmxOptFifo", 25, 1 },
+		{ "IngTokenFifo", 24, 1 },
+		{ "DmxPldChkOvfl1", 21, 1 },
+		{ "DmxPldChkFifo1", 20, 1 },
+		{ "DmxOptFifo1", 19, 1 },
+		{ "DmxMpaFifo1", 18, 1 },
+		{ "DmxDbFifo1", 17, 1 },
+		{ "DmxAttFifo1", 16, 1 },
+		{ "DmxIssFifo1", 15, 1 },
+		{ "DmxTcpFifo1", 14, 1 },
+		{ "DmxErrFifo1", 13, 1 },
+		{ "Mps2TpIntf1", 12, 1 },
+		{ "DmxPldChkOvfl0", 9, 1 },
+		{ "DmxPldChkFifo0", 8, 1 },
+		{ "DmxOptFifo0", 7, 1 },
+		{ "DmxMpaFifo0", 6, 1 },
+		{ "DmxDbFifo0", 5, 1 },
+		{ "DmxAttFifo0", 4, 1 },
+		{ "DmxIssFifo0", 3, 1 },
+		{ "DmxTcpFifo0", 2, 1 },
+		{ "DmxErrFifo0", 1, 1 },
+		{ "Mps2TpIntf0", 0, 1 },
+	{ "TP_E_IN0_PERR_CAUSE", 0x7f44, 0 },
+		{ "DmxIssFifo", 30, 1 },
+		{ "DmxErrFifo", 29, 1 },
+		{ "DmxAttFifo", 28, 1 },
+		{ "DmxTcpFifo", 27, 1 },
+		{ "DmxMpaFifo", 26, 1 },
+		{ "DmxOptFifo", 25, 1 },
+		{ "IngTokenFifo", 24, 1 },
+		{ "DmxPldChkOvfl1", 21, 1 },
+		{ "DmxPldChkFifo1", 20, 1 },
+		{ "DmxOptFifo1", 19, 1 },
+		{ "DmxMpaFifo1", 18, 1 },
+		{ "DmxDbFifo1", 17, 1 },
+		{ "DmxAttFifo1", 16, 1 },
+		{ "DmxIssFifo1", 15, 1 },
+		{ "DmxTcpFifo1", 14, 1 },
+		{ "DmxErrFifo1", 13, 1 },
+		{ "Mps2TpIntf1", 12, 1 },
+		{ "DmxPldChkOvfl0", 9, 1 },
+		{ "DmxPldChkFifo0", 8, 1 },
+		{ "DmxOptFifo0", 7, 1 },
+		{ "DmxMpaFifo0", 6, 1 },
+		{ "DmxDbFifo0", 5, 1 },
+		{ "DmxAttFifo0", 4, 1 },
+		{ "DmxIssFifo0", 3, 1 },
+		{ "DmxTcpFifo0", 2, 1 },
+		{ "DmxErrFifo0", 1, 1 },
+		{ "Mps2TpIntf0", 0, 1 },
+	{ "TP_E_IN1_PERR_ENABLE", 0x7f48, 0 },
+		{ "DmxPldChkOvfl3", 21, 1 },
+		{ "DmxPldChkFifo3", 20, 1 },
+		{ "DmxOptFifo3", 19, 1 },
+		{ "DmxMpaFifo3", 18, 1 },
+		{ "DmxDbFifo3", 17, 1 },
+		{ "DmxAttFifo3", 16, 1 },
+		{ "DmxIssFifo3", 15, 1 },
+		{ "DmxTcpFifo3", 14, 1 },
+		{ "DmxErrFifo3", 13, 1 },
+		{ "Mps2TpIntf3", 12, 1 },
+		{ "DmxPldChkOvfl2", 9, 1 },
+		{ "DmxPldChkFifo2", 8, 1 },
+		{ "DmxOptFifo2", 7, 1 },
+		{ "DmxMpaFifo2", 6, 1 },
+		{ "DmxDbFifo2", 5, 1 },
+		{ "DmxAttFifo2", 4, 1 },
+		{ "DmxIssFifo2", 3, 1 },
+		{ "DmxTcpFifo2", 2, 1 },
+		{ "DmxErrFifo2", 1, 1 },
+		{ "Mps2TpIntf2", 0, 1 },
+	{ "TP_E_IN1_PERR_CAUSE", 0x7f4c, 0 },
+		{ "DmxPldChkOvfl3", 21, 1 },
+		{ "DmxPldChkFifo3", 20, 1 },
+		{ "DmxOptFifo3", 19, 1 },
+		{ "DmxMpaFifo3", 18, 1 },
+		{ "DmxDbFifo3", 17, 1 },
+		{ "DmxAttFifo3", 16, 1 },
+		{ "DmxIssFifo3", 15, 1 },
+		{ "DmxTcpFifo3", 14, 1 },
+		{ "DmxErrFifo3", 13, 1 },
+		{ "Mps2TpIntf3", 12, 1 },
+		{ "DmxPldChkOvfl2", 9, 1 },
+		{ "DmxPldChkFifo2", 8, 1 },
+		{ "DmxOptFifo2", 7, 1 },
+		{ "DmxMpaFifo2", 6, 1 },
+		{ "DmxDbFifo2", 5, 1 },
+		{ "DmxAttFifo2", 4, 1 },
+		{ "DmxIssFifo2", 3, 1 },
+		{ "DmxTcpFifo2", 2, 1 },
+		{ "DmxErrFifo2", 1, 1 },
+		{ "Mps2TpIntf2", 0, 1 },
+	{ "TP_O_PERR_ENABLE", 0x7f50, 0 },
+		{ "DmarbtPerr", 31, 1 },
+		{ "FlmPerrSet", 28, 1 },
+		{ "MmgrCacheDataSram", 24, 1 },
+		{ "MmgrCacheTagFifo", 23, 1 },
+		{ "DbL2tLutPerr", 22, 1 },
+		{ "DbTxTidPerr", 21, 1 },
+		{ "DbExtPerr", 20, 1 },
+		{ "DbOpPerr", 19, 1 },
+		{ "TmCachePerr", 18, 1 },
+		{ "TpProtoSram", 16, 1 },
+		{ "HspSram", 15, 1 },
+		{ "RateGrpSram", 14, 1 },
+		{ "TxFbSeqFifo", 13, 1 },
+		{ "CmDataSram", 12, 1 },
+		{ "CmTagFifo", 11, 1 },
+		{ "RfcOpFifo", 10, 1 },
+		{ "DelInvFifo", 9, 1 },
+		{ "RssCfgSram", 8, 1 },
+		{ "RssKeySram", 7, 1 },
+		{ "RssLkpSram", 6, 1 },
+		{ "SrqSram", 5, 1 },
+		{ "ArpDaSram", 4, 1 },
+		{ "ArpSaSram", 3, 1 },
+		{ "ArpGreSram", 2, 1 },
+		{ "ArpIpsecSram1", 1, 1 },
+		{ "ArpIpsecSram0", 0, 1 },
+	{ "TP_O_PERR_CAUSE", 0x7f54, 0 },
+		{ "DmarbtPerr", 31, 1 },
+		{ "FlmPerrSet", 28, 1 },
+		{ "MmgrCacheDataSram", 24, 1 },
+		{ "MmgrCacheTagFifo", 23, 1 },
+		{ "DbL2tLutPerr", 22, 1 },
+		{ "DbTxTidPerr", 21, 1 },
+		{ "DbExtPerr", 20, 1 },
+		{ "DbOpPerr", 19, 1 },
+		{ "TmCachePerr", 18, 1 },
+		{ "TpProtoSram", 16, 1 },
+		{ "HspSram", 15, 1 },
+		{ "RateGrpSram", 14, 1 },
+		{ "TxFbSeqFifo", 13, 1 },
+		{ "CmDataSram", 12, 1 },
+		{ "CmTagFifo", 11, 1 },
+		{ "RfcOpFifo", 10, 1 },
+		{ "DelInvFifo", 9, 1 },
+		{ "RssCfgSram", 8, 1 },
+		{ "RssKeySram", 7, 1 },
+		{ "RssLkpSram", 6, 1 },
+		{ "SrqSram", 5, 1 },
+		{ "ArpDaSram", 4, 1 },
+		{ "ArpSaSram", 3, 1 },
+		{ "ArpGreSram", 2, 1 },
+		{ "ArpIpsecSram1", 1, 1 },
+		{ "ArpIpsecSram0", 0, 1 },
+	{ "TP_CERR_ENABLE", 0x7f58, 0 },
+		{ "TpcEgDataFifo", 8, 1 },
+		{ "TpcLbkDataFifo", 7, 1 },
+		{ "RssLkpSram", 6, 1 },
+		{ "SrqSram", 5, 1 },
+		{ "ArpDaSram", 4, 1 },
+		{ "ArpSaSram", 3, 1 },
+		{ "ArpGreSram", 2, 1 },
+		{ "ArpIpsecSram1", 1, 1 },
+		{ "ArpIpsecSram0", 0, 1 },
+	{ "TP_CERR_CAUSE", 0x7f5c, 0 },
+		{ "TpcEgDataFifo", 8, 1 },
+		{ "TpcLbkDataFifo", 7, 1 },
+		{ "RssLkpSram", 6, 1 },
+		{ "SrqSram", 5, 1 },
+		{ "ArpDaSram", 4, 1 },
+		{ "ArpSaSram", 3, 1 },
+		{ "ArpGreSram", 2, 1 },
+		{ "ArpIpsecSram1", 1, 1 },
+		{ "ArpIpsecSram0", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_ulp_tx_regs[] = {
+	{ "ULP_TX_CONFIG", 0x8dc0, 0 },
+		{ "LB_LEN_SEL", 28, 1 },
+		{ "Disable_Tpt_Credit_Chk", 27, 1 },
+		{ "ReqSrc", 26, 1 },
+		{ "Err2uP", 25, 1 },
+		{ "SGE_Invalidate_Dis", 24, 1 },
+		{ "RoCE_AckReq_Ctrl", 23, 1 },
+		{ "Mem_Addr_Ctrl", 21, 2 },
+		{ "Tpt_Extension_Mode", 20, 1 },
+		{ "xrc_indication", 19, 1 },
+		{ "lso_1seg_len_upd_en", 18, 1 },
+		{ "PKT_ISGL_ERR_ST_EN", 17, 1 },
+		{ "ULIMIT_EXCLUSIVE_FIX", 16, 1 },
+		{ "ISO_A_FLAG_EN", 15, 1 },
+		{ "IWARP_SEQ_FLIT_DIS", 14, 1 },
+		{ "T10_ISO_FIX_EN", 12, 1 },
+		{ "CPL_FLAGS_UPDATE_EN", 11, 1 },
+		{ "IWARP_SEQ_UPDATE_EN", 10, 1 },
+		{ "SEQ_UPDATE_EN", 9, 1 },
+		{ "ERR_ITT_EN", 8, 1 },
+		{ "atomic_fix_dis", 7, 1 },
+		{ "PHYS_ADDR_RESP_EN", 6, 1 },
+		{ "ENDIANESS_CHANGE", 5, 1 },
+		{ "ERR_RTAG_EN", 4, 1 },
+		{ "TSO_ETHLEN_EN", 3, 1 },
+		{ "emsg_more_info", 2, 1 },
+		{ "LOSDR", 1, 1 },
+		{ "extra_tag_insertion_enable", 0, 1 },
+	{ "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
+		{ "MemSel", 1, 7 },
+		{ "InjectDataErr", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_1", 0x8dc8, 0 },
+		{ "Pbl_bound_err_ch3", 31, 1 },
+		{ "Pbl_bound_err_ch2", 30, 1 },
+		{ "Pbl_bound_err_ch1", 29, 1 },
+		{ "Pbl_bound_err_ch0", 28, 1 },
+		{ "sge2ulp_fifo_perr_set3", 27, 1 },
+		{ "sge2ulp_fifo_perr_set2", 26, 1 },
+		{ "sge2ulp_fifo_perr_set1", 25, 1 },
+		{ "sge2ulp_fifo_perr_set0", 24, 1 },
+		{ "cim2ulp_fifo_perr_set3", 23, 1 },
+		{ "cim2ulp_fifo_perr_set2", 22, 1 },
+		{ "cim2ulp_fifo_perr_set1", 21, 1 },
+		{ "cim2ulp_fifo_perr_set0", 20, 1 },
+		{ "CQE_fifo_perr_set3", 19, 1 },
+		{ "CQE_fifo_perr_set2", 18, 1 },
+		{ "CQE_fifo_perr_set1", 17, 1 },
+		{ "CQE_fifo_perr_set0", 16, 1 },
+		{ "pbl_fifo_perr_set3", 15, 1 },
+		{ "pbl_fifo_perr_set2", 14, 1 },
+		{ "pbl_fifo_perr_set1", 13, 1 },
+		{ "pbl_fifo_perr_set0", 12, 1 },
+		{ "cmd_fifo_perr_set3", 11, 1 },
+		{ "cmd_fifo_perr_set2", 10, 1 },
+		{ "cmd_fifo_perr_set1", 9, 1 },
+		{ "cmd_fifo_perr_set0", 8, 1 },
+		{ "lso_hdr_sram_perr_set3", 7, 1 },
+		{ "lso_hdr_sram_perr_set2", 6, 1 },
+		{ "lso_hdr_sram_perr_set1", 5, 1 },
+		{ "lso_hdr_sram_perr_set0", 4, 1 },
+		{ "tls_dsgl_ParErr3", 3, 1 },
+		{ "tls_dsgl_ParErr2", 2, 1 },
+		{ "tls_dsgl_ParErr1", 1, 1 },
+		{ "tls_dsgl_ParErr0", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_1", 0x8dcc, 0 },
+		{ "Pbl_bound_err_ch3", 31, 1 },
+		{ "Pbl_bound_err_ch2", 30, 1 },
+		{ "Pbl_bound_err_ch1", 29, 1 },
+		{ "Pbl_bound_err_ch0", 28, 1 },
+		{ "sge2ulp_fifo_perr_set3", 27, 1 },
+		{ "sge2ulp_fifo_perr_set2", 26, 1 },
+		{ "sge2ulp_fifo_perr_set1", 25, 1 },
+		{ "sge2ulp_fifo_perr_set0", 24, 1 },
+		{ "cim2ulp_fifo_perr_set3", 23, 1 },
+		{ "cim2ulp_fifo_perr_set2", 22, 1 },
+		{ "cim2ulp_fifo_perr_set1", 21, 1 },
+		{ "cim2ulp_fifo_perr_set0", 20, 1 },
+		{ "CQE_fifo_perr_set3", 19, 1 },
+		{ "CQE_fifo_perr_set2", 18, 1 },
+		{ "CQE_fifo_perr_set1", 17, 1 },
+		{ "CQE_fifo_perr_set0", 16, 1 },
+		{ "pbl_fifo_perr_set3", 15, 1 },
+		{ "pbl_fifo_perr_set2", 14, 1 },
+		{ "pbl_fifo_perr_set1", 13, 1 },
+		{ "pbl_fifo_perr_set0", 12, 1 },
+		{ "cmd_fifo_perr_set3", 11, 1 },
+		{ "cmd_fifo_perr_set2", 10, 1 },
+		{ "cmd_fifo_perr_set1", 9, 1 },
+		{ "cmd_fifo_perr_set0", 8, 1 },
+		{ "lso_hdr_sram_perr_set3", 7, 1 },
+		{ "lso_hdr_sram_perr_set2", 6, 1 },
+		{ "lso_hdr_sram_perr_set1", 5, 1 },
+		{ "lso_hdr_sram_perr_set0", 4, 1 },
+		{ "tls_dsgl_ParErr3", 3, 1 },
+		{ "tls_dsgl_ParErr2", 2, 1 },
+		{ "tls_dsgl_ParErr1", 1, 1 },
+		{ "tls_dsgl_ParErr0", 0, 1 },
+	{ "ULP_TX_PERR_ENABLE_1", 0x8dd0, 0 },
+		{ "sge2ulp_fifo_perr_set3", 27, 1 },
+		{ "sge2ulp_fifo_perr_set2", 26, 1 },
+		{ "sge2ulp_fifo_perr_set1", 25, 1 },
+		{ "sge2ulp_fifo_perr_set0", 24, 1 },
+		{ "cim2ulp_fifo_perr_set3", 23, 1 },
+		{ "cim2ulp_fifo_perr_set2", 22, 1 },
+		{ "cim2ulp_fifo_perr_set1", 21, 1 },
+		{ "cim2ulp_fifo_perr_set0", 20, 1 },
+		{ "CQE_fifo_perr_set3", 19, 1 },
+		{ "CQE_fifo_perr_set2", 18, 1 },
+		{ "CQE_fifo_perr_set1", 17, 1 },
+		{ "CQE_fifo_perr_set0", 16, 1 },
+		{ "pbl_fifo_perr_set3", 15, 1 },
+		{ "pbl_fifo_perr_set2", 14, 1 },
+		{ "pbl_fifo_perr_set1", 13, 1 },
+		{ "pbl_fifo_perr_set0", 12, 1 },
+		{ "cmd_fifo_perr_set3", 11, 1 },
+		{ "cmd_fifo_perr_set2", 10, 1 },
+		{ "cmd_fifo_perr_set1", 9, 1 },
+		{ "cmd_fifo_perr_set0", 8, 1 },
+		{ "lso_hdr_sram_perr_set3", 7, 1 },
+		{ "lso_hdr_sram_perr_set2", 6, 1 },
+		{ "lso_hdr_sram_perr_set1", 5, 1 },
+		{ "lso_hdr_sram_perr_set0", 4, 1 },
+		{ "tls_dsgl_ParErr3", 3, 1 },
+		{ "tls_dsgl_ParErr2", 2, 1 },
+		{ "tls_dsgl_ParErr1", 1, 1 },
+		{ "tls_dsgl_ParErr0", 0, 1 },
+	{ "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
+	{ "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
+	{ "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
+	{ "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
+	{ "ULP_TX_NVME_TCP_TPT_LLIMIT", 0x8fa4, 0 },
+	{ "ULP_TX_NVME_TCP_TPT_ULIMIT", 0x8fa8, 0 },
+	{ "ULP_TX_NVME_TCP_PBL_LLIMIT", 0x8fac, 0 },
+	{ "ULP_TX_NVME_TCP_PBL_ULIMIT", 0x8fb0, 0 },
+	{ "ULP_TX_DBG_CTL", 0x8fb8, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG_L", 16, 1 },
+		{ "SEL_L", 0, 8 },
+	{ "ULP_TX_DBG_DATA", 0x8fbc, 0 },
+	{ "ULP_TX_TLS_CTL", 0x8de4, 0 },
+		{ "TlsPerrEn", 4, 1 },
+		{ "TlsDisableIFuse", 2, 1 },
+		{ "TlsDisableCFuse", 1, 1 },
+		{ "TlsDisable", 0, 1 },
+	{ "ULP_TX_FID_1", 0x8de8, 0 },
+	{ "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
+		{ "Ch3Size1", 24, 8 },
+		{ "Ch2Size1", 16, 8 },
+		{ "Ch1Size1", 8, 8 },
+		{ "Ch0Size1", 0, 8 },
+	{ "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
+		{ "Ch3Size2", 24, 8 },
+		{ "Ch2Size2", 16, 8 },
+		{ "Ch1Size2", 8, 8 },
+		{ "Ch0Size2", 0, 8 },
+	{ "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
+	{ "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
+	{ "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
+	{ "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
+	{ "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
+	{ "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
+	{ "ULP_TX_FC_SOF", 0x8e20, 0 },
+		{ "SOF_FS3", 24, 8 },
+		{ "SOF_FS2", 16, 8 },
+		{ "SOF_3", 8, 8 },
+		{ "SOF_2", 0, 8 },
+	{ "ULP_TX_FC_EOF", 0x8e24, 0 },
+		{ "EOF_LS3", 24, 8 },
+		{ "EOF_LS2", 16, 8 },
+		{ "EOF_3", 8, 8 },
+		{ "EOF_2", 0, 8 },
+	{ "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 },
+	{ "ULP_TX_CGEN", 0x8e2c, 0 },
+		{ "ULP_TX_CGEN_Storage", 8, 4 },
+		{ "ULP_TX_CGEN_RDMA", 4, 4 },
+		{ "ULP_TX_CGEN_Channel", 0, 4 },
+	{ "ULP_TX_MEM_CFG", 0x8e30, 0 },
+		{ "GlobalEnable", 31, 1 },
+		{ "RDREQ_SZ", 3, 3 },
+		{ "WRREQ_SZ", 0, 3 },
+	{ "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 },
+		{ "edma_in_fifo_perr_set3", 31, 1 },
+		{ "edma_in_fifo_perr_set2", 30, 1 },
+		{ "edma_in_fifo_perr_set1", 29, 1 },
+		{ "edma_in_fifo_perr_set0", 28, 1 },
+		{ "align_ctl_fifo_perr_set3", 27, 1 },
+		{ "align_ctl_fifo_perr_set2", 26, 1 },
+		{ "align_ctl_fifo_perr_set1", 25, 1 },
+		{ "align_ctl_fifo_perr_set0", 24, 1 },
+		{ "sge_fifo_perr_set3", 23, 1 },
+		{ "sge_fifo_perr_set2", 22, 1 },
+		{ "sge_fifo_perr_set1", 21, 1 },
+		{ "sge_fifo_perr_set0", 20, 1 },
+		{ "stag_fifo_perr_set3", 19, 1 },
+		{ "stag_fifo_perr_set2", 18, 1 },
+		{ "stag_fifo_perr_set1", 17, 1 },
+		{ "stag_fifo_perr_set0", 16, 1 },
+		{ "map_fifo_perr_set3", 15, 1 },
+		{ "map_fifo_perr_set2", 14, 1 },
+		{ "map_fifo_perr_set1", 13, 1 },
+		{ "map_fifo_perr_set0", 12, 1 },
+		{ "dma_fifo_perr_set3", 11, 1 },
+		{ "dma_fifo_perr_set2", 10, 1 },
+		{ "dma_fifo_perr_set1", 9, 1 },
+		{ "dma_fifo_perr_set0", 8, 1 },
+		{ "fso_hdr_sram_perr_set3", 7, 1 },
+		{ "fso_hdr_sram_perr_set2", 6, 1 },
+		{ "fso_hdr_sram_perr_set1", 5, 1 },
+		{ "fso_hdr_sram_perr_set0", 4, 1 },
+		{ "t10_pi_sram_perr_set3", 3, 1 },
+		{ "t10_pi_sram_perr_set2", 2, 1 },
+		{ "t10_pi_sram_perr_set1", 1, 1 },
+		{ "t10_pi_sram_perr_set0", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_2", 0x8e80, 0 },
+		{ "edma_in_fifo_perr_set3", 31, 1 },
+		{ "edma_in_fifo_perr_set2", 30, 1 },
+		{ "edma_in_fifo_perr_set1", 29, 1 },
+		{ "edma_in_fifo_perr_set0", 28, 1 },
+		{ "align_ctl_fifo_perr_set3", 27, 1 },
+		{ "align_ctl_fifo_perr_set2", 26, 1 },
+		{ "align_ctl_fifo_perr_set1", 25, 1 },
+		{ "align_ctl_fifo_perr_set0", 24, 1 },
+		{ "sge_fifo_perr_set3", 23, 1 },
+		{ "sge_fifo_perr_set2", 22, 1 },
+		{ "sge_fifo_perr_set1", 21, 1 },
+		{ "sge_fifo_perr_set0", 20, 1 },
+		{ "stag_fifo_perr_set3", 19, 1 },
+		{ "stag_fifo_perr_set2", 18, 1 },
+		{ "stag_fifo_perr_set1", 17, 1 },
+		{ "stag_fifo_perr_set0", 16, 1 },
+		{ "map_fifo_perr_set3", 15, 1 },
+		{ "map_fifo_perr_set2", 14, 1 },
+		{ "map_fifo_perr_set1", 13, 1 },
+		{ "map_fifo_perr_set0", 12, 1 },
+		{ "dma_fifo_perr_set3", 11, 1 },
+		{ "dma_fifo_perr_set2", 10, 1 },
+		{ "dma_fifo_perr_set1", 9, 1 },
+		{ "dma_fifo_perr_set0", 8, 1 },
+		{ "fso_hdr_sram_perr_set3", 7, 1 },
+		{ "fso_hdr_sram_perr_set2", 6, 1 },
+		{ "fso_hdr_sram_perr_set1", 5, 1 },
+		{ "fso_hdr_sram_perr_set0", 4, 1 },
+		{ "t10_pi_sram_perr_set3", 3, 1 },
+		{ "t10_pi_sram_perr_set2", 2, 1 },
+		{ "t10_pi_sram_perr_set1", 1, 1 },
+		{ "t10_pi_sram_perr_set0", 0, 1 },
+	{ "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 },
+		{ "edma_in_fifo_perr_set3", 31, 1 },
+		{ "edma_in_fifo_perr_set2", 30, 1 },
+		{ "edma_in_fifo_perr_set1", 29, 1 },
+		{ "edma_in_fifo_perr_set0", 28, 1 },
+		{ "align_ctl_fifo_perr_set3", 27, 1 },
+		{ "align_ctl_fifo_perr_set2", 26, 1 },
+		{ "align_ctl_fifo_perr_set1", 25, 1 },
+		{ "align_ctl_fifo_perr_set0", 24, 1 },
+		{ "sge_fifo_perr_set3", 23, 1 },
+		{ "sge_fifo_perr_set2", 22, 1 },
+		{ "sge_fifo_perr_set1", 21, 1 },
+		{ "sge_fifo_perr_set0", 20, 1 },
+		{ "stag_fifo_perr_set3", 19, 1 },
+		{ "stag_fifo_perr_set2", 18, 1 },
+		{ "stag_fifo_perr_set1", 17, 1 },
+		{ "stag_fifo_perr_set0", 16, 1 },
+		{ "map_fifo_perr_set3", 15, 1 },
+		{ "map_fifo_perr_set2", 14, 1 },
+		{ "map_fifo_perr_set1", 13, 1 },
+		{ "map_fifo_perr_set0", 12, 1 },
+		{ "dma_fifo_perr_set3", 11, 1 },
+		{ "dma_fifo_perr_set2", 10, 1 },
+		{ "dma_fifo_perr_set1", 9, 1 },
+		{ "dma_fifo_perr_set0", 8, 1 },
+		{ "fso_hdr_sram_perr_set3", 7, 1 },
+		{ "fso_hdr_sram_perr_set2", 6, 1 },
+		{ "fso_hdr_sram_perr_set1", 5, 1 },
+		{ "fso_hdr_sram_perr_set0", 4, 1 },
+		{ "t10_pi_sram_perr_set3", 3, 1 },
+		{ "t10_pi_sram_perr_set2", 2, 1 },
+		{ "t10_pi_sram_perr_set1", 1, 1 },
+		{ "t10_pi_sram_perr_set0", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_3", 0x8e88, 0 },
+		{ "gf_sge_fifo_ParErr3", 31, 1 },
+		{ "gf_sge_fifo_ParErr2", 30, 1 },
+		{ "gf_sge_fifo_ParErr1", 29, 1 },
+		{ "gf_sge_fifo_ParErr0", 28, 1 },
+		{ "dedupe_sge_fifo_ParErr3", 27, 1 },
+		{ "dedupe_sge_fifo_ParErr2", 26, 1 },
+		{ "dedupe_sge_fifo_ParErr1", 25, 1 },
+		{ "dedupe_sge_fifo_ParErr0", 24, 1 },
+		{ "gf3_dsgl_fifo_ParErr", 23, 1 },
+		{ "gf2_dsgl_fifo_ParErr", 22, 1 },
+		{ "gf1_dsgl_fifo_ParErr", 21, 1 },
+		{ "gf0_dsgl_fifo_ParErr", 20, 1 },
+		{ "dedupe3_dsgl_fifo_ParErr", 19, 1 },
+		{ "dedupe2_dsgl_fifo_ParErr", 18, 1 },
+		{ "dedupe1_dsgl_fifo_ParErr", 17, 1 },
+		{ "dedupe0_dsgl_fifo_ParErr", 16, 1 },
+		{ "xp10_sge_fifo_ParErr", 15, 1 },
+		{ "dsgl_par_err", 14, 1 },
+		{ "cddip_int", 13, 1 },
+		{ "cceip_int", 12, 1 },
+		{ "tls_sge_fifo_ParErr3", 11, 1 },
+		{ "tls_sge_fifo_ParErr2", 10, 1 },
+		{ "tls_sge_fifo_ParErr1", 9, 1 },
+		{ "tls_sge_fifo_ParErr0", 8, 1 },
+		{ "ulp2smarbt_rsp_perr", 6, 1 },
+		{ "ulptx2ma_rsp_perr", 5, 1 },
+		{ "pcie2ulp_perr3", 4, 1 },
+		{ "pcie2ulp_perr2", 3, 1 },
+		{ "pcie2ulp_perr1", 2, 1 },
+		{ "pcie2ulp_perr0", 1, 1 },
+		{ "cim2ulp_perr", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_3", 0x8e8c, 0 },
+		{ "gf_sge_fifo_ParErr3", 31, 1 },
+		{ "gf_sge_fifo_ParErr2", 30, 1 },
+		{ "gf_sge_fifo_ParErr1", 29, 1 },
+		{ "gf_sge_fifo_ParErr0", 28, 1 },
+		{ "dedupe_sge_fifo_ParErr3", 27, 1 },
+		{ "dedupe_sge_fifo_ParErr2", 26, 1 },
+		{ "dedupe_sge_fifo_ParErr1", 25, 1 },
+		{ "dedupe_sge_fifo_ParErr0", 24, 1 },
+		{ "gf3_dsgl_fifo_ParErr", 23, 1 },
+		{ "gf2_dsgl_fifo_ParErr", 22, 1 },
+		{ "gf1_dsgl_fifo_ParErr", 21, 1 },
+		{ "gf0_dsgl_fifo_ParErr", 20, 1 },
+		{ "dedupe3_dsgl_fifo_ParErr", 19, 1 },
+		{ "dedupe2_dsgl_fifo_ParErr", 18, 1 },
+		{ "dedupe1_dsgl_fifo_ParErr", 17, 1 },
+		{ "dedupe0_dsgl_fifo_ParErr", 16, 1 },
+		{ "xp10_sge_fifo_ParErr", 15, 1 },
+		{ "dsgl_par_err", 14, 1 },
+		{ "cddip_int", 13, 1 },
+		{ "cceip_int", 12, 1 },
+		{ "tls_sge_fifo_ParErr3", 11, 1 },
+		{ "tls_sge_fifo_ParErr2", 10, 1 },
+		{ "tls_sge_fifo_ParErr1", 9, 1 },
+		{ "tls_sge_fifo_ParErr0", 8, 1 },
+		{ "ulp2smarbt_rsp_perr", 6, 1 },
+		{ "ulptx2ma_rsp_perr", 5, 1 },
+		{ "pcie2ulp_perr3", 4, 1 },
+		{ "pcie2ulp_perr2", 3, 1 },
+		{ "pcie2ulp_perr1", 2, 1 },
+		{ "pcie2ulp_perr0", 1, 1 },
+		{ "cim2ulp_perr", 0, 1 },
+	{ "ULP_TX_PERR_ENABLE_3", 0x8e90, 0 },
+		{ "gf_sge_fifo_ParErr3", 31, 1 },
+		{ "gf_sge_fifo_ParErr2", 30, 1 },
+		{ "gf_sge_fifo_ParErr1", 29, 1 },
+		{ "gf_sge_fifo_ParErr0", 28, 1 },
+		{ "dedupe_sge_fifo_ParErr3", 27, 1 },
+		{ "dedupe_sge_fifo_ParErr2", 26, 1 },
+		{ "dedupe_sge_fifo_ParErr1", 25, 1 },
+		{ "dedupe_sge_fifo_ParErr0", 24, 1 },
+		{ "gf3_dsgl_fifo_ParErr", 23, 1 },
+		{ "gf2_dsgl_fifo_ParErr", 22, 1 },
+		{ "gf1_dsgl_fifo_ParErr", 21, 1 },
+		{ "gf0_dsgl_fifo_ParErr", 20, 1 },
+		{ "dedupe3_dsgl_fifo_ParErr", 19, 1 },
+		{ "dedupe2_dsgl_fifo_ParErr", 18, 1 },
+		{ "dedupe1_dsgl_fifo_ParErr", 17, 1 },
+		{ "dedupe0_dsgl_fifo_ParErr", 16, 1 },
+		{ "xp10_sge_fifo_ParErr", 15, 1 },
+		{ "dsgl_par_err", 14, 1 },
+		{ "cddip_int", 13, 1 },
+		{ "cceip_int", 12, 1 },
+		{ "tls_sge_fifo_ParErr3", 11, 1 },
+		{ "tls_sge_fifo_ParErr2", 10, 1 },
+		{ "tls_sge_fifo_ParErr1", 9, 1 },
+		{ "tls_sge_fifo_ParErr0", 8, 1 },
+		{ "ulp2smarbt_rsp_perr", 6, 1 },
+		{ "ulptx2ma_rsp_perr", 5, 1 },
+		{ "pcie2ulp_perr3", 4, 1 },
+		{ "pcie2ulp_perr2", 3, 1 },
+		{ "pcie2ulp_perr1", 2, 1 },
+		{ "pcie2ulp_perr0", 1, 1 },
+		{ "cim2ulp_perr", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_4", 0x8e94, 0 },
+		{ "dma_par_err3", 28, 4 },
+		{ "dma_par_err2", 24, 4 },
+		{ "dma_par_err1", 20, 4 },
+		{ "dma_par_err0", 16, 4 },
+		{ "core_cmd_fifo_lb1", 12, 4 },
+		{ "core_cmd_fifo_lb0", 8, 4 },
+		{ "xp10_2_ulp_perr", 7, 1 },
+		{ "ulp_2_xp10_perr", 6, 1 },
+		{ "cmd_fifo_lb1", 5, 1 },
+		{ "cmd_fifo_lb0", 4, 1 },
+		{ "tf_tp_perr", 3, 1 },
+		{ "tf_sge_perr", 2, 1 },
+		{ "tf_mem_perr", 1, 1 },
+		{ "tf_mp_perr", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_4", 0x8e98, 0 },
+		{ "dma_par_err3", 28, 4 },
+		{ "dma_par_err2", 24, 4 },
+		{ "dma_par_err1", 20, 4 },
+		{ "dma_par_err0", 16, 4 },
+		{ "core_cmd_fifo_lb1", 12, 4 },
+		{ "core_cmd_fifo_lb0", 8, 4 },
+		{ "xp10_2_ulp_perr", 7, 1 },
+		{ "ulp_2_xp10_perr", 6, 1 },
+		{ "cmd_fifo_lb1", 5, 1 },
+		{ "cmd_fifo_lb0", 4, 1 },
+		{ "tf_tp_perr", 3, 1 },
+		{ "tf_sge_perr", 2, 1 },
+		{ "tf_mem_perr", 1, 1 },
+		{ "tf_mp_perr", 0, 1 },
+	{ "ULP_TX_PERR_ENABLE_4", 0x8e9c, 0 },
+		{ "dma_par_err3", 28, 4 },
+		{ "dma_par_err2", 24, 4 },
+		{ "dma_par_err1", 20, 4 },
+		{ "dma_par_err0", 16, 4 },
+		{ "core_cmd_fifo_lb1", 12, 4 },
+		{ "core_cmd_fifo_lb0", 8, 4 },
+		{ "xp10_2_ulp_perr", 7, 1 },
+		{ "ulp_2_xp10_perr", 6, 1 },
+		{ "cmd_fifo_lb1", 5, 1 },
+		{ "cmd_fifo_lb0", 4, 1 },
+		{ "tf_tp_perr", 3, 1 },
+		{ "tf_sge_perr", 2, 1 },
+		{ "tf_mem_perr", 1, 1 },
+		{ "tf_mp_perr", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_5", 0x8ec4, 0 },
+		{ "DeDupe_Perr3", 23, 1 },
+		{ "DeDupe_Perr2", 22, 1 },
+		{ "DeDupe_Perr1", 21, 1 },
+		{ "DeDupe_Perr0", 20, 1 },
+		{ "GF_Perr3", 19, 1 },
+		{ "GF_Perr2", 18, 1 },
+		{ "GF_Perr1", 17, 1 },
+		{ "GF_Perr0", 16, 1 },
+		{ "SGE2ULP_inv_perr", 13, 1 },
+		{ "PL_BusPerr", 12, 1 },
+		{ "TLSTX2ULPTX_Perr3", 11, 1 },
+		{ "TLSTX2ULPTX_Perr2", 10, 1 },
+		{ "TLSTX2ULPTX_Perr1", 9, 1 },
+		{ "TLSTX2ULPTX_Perr0", 8, 1 },
+		{ "xp10_2_ulp_pl_perr", 1, 1 },
+		{ "ulp_2_xp10_pl_perr", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_5", 0x8ec8, 0 },
+		{ "DeDupe_Perr3", 23, 1 },
+		{ "DeDupe_Perr2", 22, 1 },
+		{ "DeDupe_Perr1", 21, 1 },
+		{ "DeDupe_Perr0", 20, 1 },
+		{ "GF_Perr3", 19, 1 },
+		{ "GF_Perr2", 18, 1 },
+		{ "GF_Perr1", 17, 1 },
+		{ "GF_Perr0", 16, 1 },
+		{ "SGE2ULP_inv_perr", 13, 1 },
+		{ "PL_BusPerr", 12, 1 },
+		{ "TLSTX2ULPTX_Perr3", 11, 1 },
+		{ "TLSTX2ULPTX_Perr2", 10, 1 },
+		{ "TLSTX2ULPTX_Perr1", 9, 1 },
+		{ "TLSTX2ULPTX_Perr0", 8, 1 },
+		{ "xp10_2_ulp_pl_perr", 1, 1 },
+		{ "ulp_2_xp10_pl_perr", 0, 1 },
+	{ "ULP_TX_PERR_ENABLE_5", 0x8ecc, 0 },
+		{ "DeDupe_Perr3", 23, 1 },
+		{ "DeDupe_Perr2", 22, 1 },
+		{ "DeDupe_Perr1", 21, 1 },
+		{ "DeDupe_Perr0", 20, 1 },
+		{ "GF_Perr3", 19, 1 },
+		{ "GF_Perr2", 18, 1 },
+		{ "GF_Perr1", 17, 1 },
+		{ "GF_Perr0", 16, 1 },
+		{ "SGE2ULP_inv_perr", 13, 1 },
+		{ "PL_BusPerr", 12, 1 },
+		{ "TLSTX2ULPTX_Perr3", 11, 1 },
+		{ "TLSTX2ULPTX_Perr2", 10, 1 },
+		{ "TLSTX2ULPTX_Perr1", 9, 1 },
+		{ "TLSTX2ULPTX_Perr0", 8, 1 },
+		{ "xp10_2_ulp_pl_perr", 1, 1 },
+		{ "ulp_2_xp10_pl_perr", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_6", 0x8ed0, 0 },
+		{ "DDR_hdr_fifo_perr_set3", 12, 1 },
+		{ "DDR_hdr_fifo_perr_set2", 11, 1 },
+		{ "DDR_hdr_fifo_perr_set1", 10, 1 },
+		{ "DDR_hdr_fifo_perr_set0", 9, 1 },
+		{ "pre_MP_rsp_perr_set3", 8, 1 },
+		{ "pre_MP_rsp_perr_set2", 7, 1 },
+		{ "pre_MP_rsp_perr_set1", 6, 1 },
+		{ "pre_MP_rsp_perr_set0", 5, 1 },
+		{ "pre_CQE_fifo_perr_set3", 4, 1 },
+		{ "pre_CQE_fifo_perr_set2", 3, 1 },
+		{ "pre_CQE_fifo_perr_set1", 2, 1 },
+		{ "pre_CQE_fifo_perr_set0", 1, 1 },
+		{ "rsp_fifo_perr_set", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_6", 0x8ed4, 0 },
+		{ "DDR_hdr_fifo_perr_set3", 12, 1 },
+		{ "DDR_hdr_fifo_perr_set2", 11, 1 },
+		{ "DDR_hdr_fifo_perr_set1", 10, 1 },
+		{ "DDR_hdr_fifo_perr_set0", 9, 1 },
+		{ "pre_MP_rsp_perr_set3", 8, 1 },
+		{ "pre_MP_rsp_perr_set2", 7, 1 },
+		{ "pre_MP_rsp_perr_set1", 6, 1 },
+		{ "pre_MP_rsp_perr_set0", 5, 1 },
+		{ "pre_CQE_fifo_perr_set3", 4, 1 },
+		{ "pre_CQE_fifo_perr_set2", 3, 1 },
+		{ "pre_CQE_fifo_perr_set1", 2, 1 },
+		{ "pre_CQE_fifo_perr_set0", 1, 1 },
+		{ "rsp_fifo_perr_set", 0, 1 },
+	{ "ULP_TX_PERR_ENABLE_6", 0x8ed8, 0 },
+		{ "DDR_hdr_fifo_perr_set3", 12, 1 },
+		{ "DDR_hdr_fifo_perr_set2", 11, 1 },
+		{ "DDR_hdr_fifo_perr_set1", 10, 1 },
+		{ "DDR_hdr_fifo_perr_set0", 9, 1 },
+		{ "pre_MP_rsp_perr_set3", 8, 1 },
+		{ "pre_MP_rsp_perr_set2", 7, 1 },
+		{ "pre_MP_rsp_perr_set1", 6, 1 },
+		{ "pre_MP_rsp_perr_set0", 5, 1 },
+		{ "pre_CQE_fifo_perr_set3", 4, 1 },
+		{ "pre_CQE_fifo_perr_set2", 3, 1 },
+		{ "pre_CQE_fifo_perr_set1", 2, 1 },
+		{ "pre_CQE_fifo_perr_set0", 1, 1 },
+		{ "rsp_fifo_perr_set", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_7", 0x8edc, 0 },
+		{ "tls_sge_fifo_CorErr3", 23, 1 },
+		{ "tls_sge_fifo_CorErr2", 22, 1 },
+		{ "tls_sge_fifo_CorErr1", 21, 1 },
+		{ "tls_sge_fifo_CorErr0", 20, 1 },
+		{ "lso_hdr_sram_cerr_set3", 19, 1 },
+		{ "lso_hdr_sram_cerr_set2", 18, 1 },
+		{ "lso_hdr_sram_cerr_set1", 17, 1 },
+		{ "lso_hdr_sram_cerr_set0", 16, 1 },
+		{ "core_cmd_fifo_cerr_set_ch3_lb1", 15, 1 },
+		{ "core_cmd_fifo_cerr_set_ch2_lb1", 14, 1 },
+		{ "core_cmd_fifo_cerr_set_ch1_lb1", 13, 1 },
+		{ "core_cmd_fifo_cerr_set_ch0_lb1", 12, 1 },
+		{ "core_cmd_fifo_cerr_set_ch3_lb0", 11, 1 },
+		{ "core_cmd_fifo_cerr_set_ch2_lb0", 10, 1 },
+		{ "core_cmd_fifo_cerr_set_ch1_lb0", 9, 1 },
+		{ "core_cmd_fifo_cerr_set_ch0_lb0", 8, 1 },
+		{ "CQE_fifo_cerr_set3", 7, 1 },
+		{ "CQE_fifo_cerr_set2", 6, 1 },
+		{ "CQE_fifo_cerr_set1", 5, 1 },
+		{ "CQE_fifo_cerr_set0", 4, 1 },
+		{ "pre_CQE_fifo_cerr_set3", 3, 1 },
+		{ "pre_CQE_fifo_cerr_set2", 2, 1 },
+		{ "pre_CQE_fifo_cerr_set1", 1, 1 },
+		{ "pre_CQE_fifo_cerr_set0", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_7", 0x8ee0, 0 },
+		{ "tls_sge_fifo_CorErr3", 23, 1 },
+		{ "tls_sge_fifo_CorErr2", 22, 1 },
+		{ "tls_sge_fifo_CorErr1", 21, 1 },
+		{ "tls_sge_fifo_CorErr0", 20, 1 },
+		{ "lso_hdr_sram_cerr_set3", 19, 1 },
+		{ "lso_hdr_sram_cerr_set2", 18, 1 },
+		{ "lso_hdr_sram_cerr_set1", 17, 1 },
+		{ "lso_hdr_sram_cerr_set0", 16, 1 },
+		{ "core_cmd_fifo_cerr_set_ch3_lb1", 15, 1 },
+		{ "core_cmd_fifo_cerr_set_ch2_lb1", 14, 1 },
+		{ "core_cmd_fifo_cerr_set_ch1_lb1", 13, 1 },
+		{ "core_cmd_fifo_cerr_set_ch0_lb1", 12, 1 },
+		{ "core_cmd_fifo_cerr_set_ch3_lb0", 11, 1 },
+		{ "core_cmd_fifo_cerr_set_ch2_lb0", 10, 1 },
+		{ "core_cmd_fifo_cerr_set_ch1_lb0", 9, 1 },
+		{ "core_cmd_fifo_cerr_set_ch0_lb0", 8, 1 },
+		{ "CQE_fifo_cerr_set3", 7, 1 },
+		{ "CQE_fifo_cerr_set2", 6, 1 },
+		{ "CQE_fifo_cerr_set1", 5, 1 },
+		{ "CQE_fifo_cerr_set0", 4, 1 },
+		{ "pre_CQE_fifo_cerr_set3", 3, 1 },
+		{ "pre_CQE_fifo_cerr_set2", 2, 1 },
+		{ "pre_CQE_fifo_cerr_set1", 1, 1 },
+		{ "pre_CQE_fifo_cerr_set0", 0, 1 },
+	{ "ULP_TX_INT_CAUSE_8", 0x8ee4, 0 },
+		{ "mem_rsp_fifo_cerr_set3", 28, 1 },
+		{ "mem_rsp_fifo_cerr_set2", 27, 1 },
+		{ "mem_rsp_fifo_cerr_set1", 26, 1 },
+		{ "mem_rsp_fifo_cerr_set0", 25, 1 },
+		{ "pi_sram_cerr_set3", 24, 1 },
+		{ "pi_sram_cerr_set2", 23, 1 },
+		{ "pi_sram_cerr_set1", 22, 1 },
+		{ "pi_sram_cerr_set0", 21, 1 },
+		{ "pre_MP_rsp_cerr_set3", 20, 1 },
+		{ "pre_MP_rsp_cerr_set2", 19, 1 },
+		{ "pre_MP_rsp_cerr_set1", 18, 1 },
+		{ "pre_MP_rsp_cerr_set0", 17, 1 },
+		{ "DDR_hdr_fifo_cerr_set3", 16, 1 },
+		{ "DDR_hdr_fifo_cerr_set2", 15, 1 },
+		{ "DDR_hdr_fifo_cerr_set1", 14, 1 },
+		{ "DDR_hdr_fifo_cerr_set0", 13, 1 },
+		{ "cmd_fifo_cerr_set3", 12, 1 },
+		{ "cmd_fifo_cerr_set2", 11, 1 },
+		{ "cmd_fifo_cerr_set1", 10, 1 },
+		{ "cmd_fifo_cerr_set0", 9, 1 },
+		{ "gf_sge_fifo_CorErr3", 8, 1 },
+		{ "gf_sge_fifo_CorErr2", 7, 1 },
+		{ "gf_sge_fifo_CorErr1", 6, 1 },
+		{ "gf_sge_fifo_CorErr0", 5, 1 },
+		{ "dedupe_sge_fifo_CorErr3", 4, 1 },
+		{ "dedupe_sge_fifo_CorErr2", 3, 1 },
+		{ "dedupe_sge_fifo_CorErr1", 2, 1 },
+		{ "dedupe_sge_fifo_CorErr0", 1, 1 },
+		{ "rsp_fifo_cerr_set", 0, 1 },
+	{ "ULP_TX_INT_ENABLE_8", 0x8ee8, 0 },
+		{ "mem_rsp_fifo_cerr_set3", 28, 1 },
+		{ "mem_rsp_fifo_cerr_set2", 27, 1 },
+		{ "mem_rsp_fifo_cerr_set1", 26, 1 },
+		{ "mem_rsp_fifo_cerr_set0", 25, 1 },
+		{ "pi_sram_cerr_set3", 24, 1 },
+		{ "pi_sram_cerr_set2", 23, 1 },
+		{ "pi_sram_cerr_set1", 22, 1 },
+		{ "pi_sram_cerr_set0", 21, 1 },
+		{ "pre_MP_rsp_cerr_set3", 20, 1 },
+		{ "pre_MP_rsp_cerr_set2", 19, 1 },
+		{ "pre_MP_rsp_cerr_set1", 18, 1 },
+		{ "pre_MP_rsp_cerr_set0", 17, 1 },
+		{ "DDR_hdr_fifo_cerr_set3", 16, 1 },
+		{ "DDR_hdr_fifo_cerr_set2", 15, 1 },
+		{ "DDR_hdr_fifo_cerr_set1", 14, 1 },
+		{ "DDR_hdr_fifo_cerr_set0", 13, 1 },
+		{ "cmd_fifo_cerr_set3", 12, 1 },
+		{ "cmd_fifo_cerr_set2", 11, 1 },
+		{ "cmd_fifo_cerr_set1", 10, 1 },
+		{ "cmd_fifo_cerr_set0", 9, 1 },
+		{ "gf_sge_fifo_CorErr3", 8, 1 },
+		{ "gf_sge_fifo_CorErr2", 7, 1 },
+		{ "gf_sge_fifo_CorErr1", 6, 1 },
+		{ "gf_sge_fifo_CorErr0", 5, 1 },
+		{ "dedupe_sge_fifo_CorErr3", 4, 1 },
+		{ "dedupe_sge_fifo_CorErr2", 3, 1 },
+		{ "dedupe_sge_fifo_CorErr1", 2, 1 },
+		{ "dedupe_sge_fifo_CorErr0", 1, 1 },
+		{ "rsp_fifo_cerr_set", 0, 1 },
+	{ "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
+		{ "ERR_CH3", 12, 4 },
+		{ "ERR_CH2", 8, 4 },
+		{ "ERR_CH1", 4, 4 },
+		{ "ERR_CH0", 0, 4 },
+	{ "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
+		{ "CLR_DROP", 16, 4 },
+		{ "CLR_CH3", 12, 4 },
+		{ "CLR_CH2", 8, 4 },
+		{ "CLR_CH1", 4, 4 },
+		{ "CLR_CH0", 0, 4 },
+	{ "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
+		{ "SOP_CNT_ULP2TP", 28, 4 },
+		{ "EOP_CNT_ULP2TP", 24, 4 },
+		{ "SOP_CNT_LSO_IN", 20, 4 },
+		{ "EOP_CNT_LSO_IN", 16, 4 },
+		{ "SOP_CNT_ALG_IN", 12, 4 },
+		{ "EOP_CNT_ALG_IN", 8, 4 },
+		{ "SOP_CNT_CIM2ULP", 4, 4 },
+		{ "EOP_CNT_CIM2ULP", 0, 4 },
+	{ "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
+		{ "SOP_CNT_ULP2TP", 28, 4 },
+		{ "EOP_CNT_ULP2TP", 24, 4 },
+		{ "SOP_CNT_LSO_IN", 20, 4 },
+		{ "EOP_CNT_LSO_IN", 16, 4 },
+		{ "SOP_CNT_ALG_IN", 12, 4 },
+		{ "EOP_CNT_ALG_IN", 8, 4 },
+		{ "SOP_CNT_CIM2ULP", 4, 4 },
+		{ "EOP_CNT_CIM2ULP", 0, 4 },
+	{ "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
+		{ "SOP_CNT_ULP2TP", 28, 4 },
+		{ "EOP_CNT_ULP2TP", 24, 4 },
+		{ "SOP_CNT_LSO_IN", 20, 4 },
+		{ "EOP_CNT_LSO_IN", 16, 4 },
+		{ "SOP_CNT_ALG_IN", 12, 4 },
+		{ "EOP_CNT_ALG_IN", 8, 4 },
+		{ "SOP_CNT_CIM2ULP", 4, 4 },
+		{ "EOP_CNT_CIM2ULP", 0, 4 },
+	{ "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
+		{ "SOP_CNT_ULP2TP", 28, 4 },
+		{ "EOP_CNT_ULP2TP", 24, 4 },
+		{ "SOP_CNT_LSO_IN", 20, 4 },
+		{ "EOP_CNT_LSO_IN", 16, 4 },
+		{ "SOP_CNT_ALG_IN", 12, 4 },
+		{ "EOP_CNT_ALG_IN", 8, 4 },
+		{ "SOP_CNT_CIM2ULP", 4, 4 },
+		{ "EOP_CNT_CIM2ULP", 0, 4 },
+	{ "ULP_TX_DROP_CNT", 0x8eb8, 0 },
+		{ "DROP_INVLD_MC_CH3", 28, 4 },
+		{ "DROP_INVLD_MC_CH2", 24, 4 },
+		{ "DROP_INVLD_MC_CH1", 20, 4 },
+		{ "DROP_INVLD_MC_CH0", 16, 4 },
+		{ "DROP_CH3", 12, 4 },
+		{ "DROP_CH2", 8, 4 },
+		{ "DROP_CH1", 4, 4 },
+		{ "DROP_CH0", 0, 4 },
+	{ "ULP_TX_CSU_REVISION", 0x8ebc, 0 },
+	{ "ULP_TX_CPL_TX_DATA_FLAGS_MASK", 0x8f88, 0 },
+		{ "bypass_first", 26, 1 },
+		{ "bypass_middle", 25, 1 },
+		{ "bypass_last", 24, 1 },
+		{ "push_first", 22, 1 },
+		{ "push_middle", 21, 1 },
+		{ "push_last", 20, 1 },
+		{ "save_first", 18, 1 },
+		{ "save_middle", 17, 1 },
+		{ "save_last", 16, 1 },
+		{ "flush_first", 14, 1 },
+		{ "flush_middle", 13, 1 },
+		{ "flush_last", 12, 1 },
+		{ "urgent_first", 10, 1 },
+		{ "urgent_middle", 9, 1 },
+		{ "urgent_last", 8, 1 },
+		{ "more_first", 6, 1 },
+		{ "more_middle", 5, 1 },
+		{ "more_last", 4, 1 },
+		{ "shove_first", 2, 1 },
+		{ "shove_middle", 1, 1 },
+		{ "shove_last", 0, 1 },
+	{ "ULP_TX_ACCELERATOR_CTL", 0x8f90, 0 },
+		{ "Fifo_Threshold", 8, 5 },
+		{ "compression_xp10DisableCFuse", 5, 1 },
+		{ "compression_xp10Disable", 4, 1 },
+		{ "DeDupeDisableCFuse", 3, 1 },
+		{ "DeDupeDisable", 2, 1 },
+		{ "GFDisableCFuse", 1, 1 },
+		{ "GFDisable", 0, 1 },
+	{ "ULP_TX_XP10_IND_ADDR", 0x8f94, 0 },
+		{ "xp10_control", 31, 1 },
+		{ "xp10_addr", 0, 20 },
+	{ "ULP_TX_XP10_IND_DATA", 0x8f98, 0 },
+	{ "ULP_TX_IWARP_PMOF_OPCODES_1", 0x8f9c, 0 },
+		{ "Rdma_Verify_Response", 24, 5 },
+		{ "Rdma_Verify_Request", 16, 5 },
+		{ "Rdma_Flush_Response", 8, 5 },
+		{ "Rdma_Flush_Request", 0, 5 },
+	{ "ULP_TX_IWARP_PMOF_OPCODES_2", 0x8fa0, 0 },
+		{ "Rdma_Send_With_SE_Immediate", 24, 5 },
+		{ "Rdma_Send_With_Immediate", 16, 5 },
+		{ "Rdma_Atomic_Write_Response", 8, 5 },
+		{ "Rdma_Atomic_Write_Request", 0, 5 },
+	{ "ULP_TX_PL2APB_INFO", 0x8ec0, 0 },
+		{ "pl2apb_bridge_hung", 27, 1 },
+		{ "pl2apb_bridge_state", 26, 1 },
+		{ "pl2apb_bridge_hung_type", 25, 1 },
+		{ "pl2apb_bridge_hung_id", 24, 1 },
+		{ "pl2apb_bridge_hung_addr", 0, 20 },
+	{ NULL }
+};
+
+struct reg_info t7_pm_rx_regs[] = {
+	{ "PM_RX_CFG", 0x8fc0, 0 },
+		{ "ch1_output", 27, 5 },
+		{ "ch2_output", 22, 5 },
+		{ "ch3_output", 17, 5 },
+		{ "strobe1", 16, 1 },
+		{ "ch1_input", 11, 5 },
+		{ "ch2_input", 6, 5 },
+		{ "ch3_input", 1, 5 },
+		{ "strobe0", 0, 1 },
+	{ "PM_RX_MODE", 0x8fc4, 0 },
+		{ "cache_hold", 13, 1 },
+		{ "cache_init_done", 12, 1 },
+		{ "cache_depth", 8, 4 },
+		{ "cache_init", 7, 1 },
+		{ "cache_sleep", 6, 1 },
+		{ "cache_bypass", 5, 1 },
+		{ "use_bundle_len", 4, 1 },
+		{ "stat_to_ch", 3, 1 },
+		{ "stat_from_ch", 1, 2 },
+		{ "prefetch_enable", 0, 1 },
+	{ "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
+	{ "PM_RX_STAT_COUNT", 0x8fcc, 0 },
+	{ "PM_RX_DBG_CTRL", 0x8fd0, 0 },
+		{ "OspiWrBusy", 21, 4 },
+		{ "IspiWrBusy", 17, 4 },
+		{ "PMDbgAddr", 0, 17 },
+	{ "PM_RX_DBG_DATA", 0x8fd4, 0 },
+	{ "PM_RX_INT_ENABLE", 0x8fd8, 0 },
+		{ "master_perr", 31, 1 },
+		{ "ospi_overflow3", 30, 1 },
+		{ "ospi_overflow2", 29, 1 },
+		{ "ospi_overflow1", 28, 1 },
+		{ "ospi_overflow0", 27, 1 },
+		{ "ma_intf_sdc_err", 26, 1 },
+		{ "bundle_len_ParErr", 25, 1 },
+		{ "bundle_len_ovfl", 24, 1 },
+		{ "sdc_err", 23, 1 },
+		{ "zero_e_cmd_error", 22, 1 },
+		{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
+		{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
+		{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
+		{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
+		{ "iespi0_Rx_framing_error", 17, 1 },
+		{ "iespi1_Rx_framing_error", 16, 1 },
+		{ "iespi2_Rx_framing_error", 15, 1 },
+		{ "iespi3_Rx_framing_error", 14, 1 },
+		{ "iespi0_Tx_framing_error", 13, 1 },
+		{ "iespi1_Tx_framing_error", 12, 1 },
+		{ "iespi2_Tx_framing_error", 11, 1 },
+		{ "iespi3_Tx_framing_error", 10, 1 },
+		{ "ocspi0_Rx_framing_error", 9, 1 },
+		{ "ocspi1_Rx_framing_error", 8, 1 },
+		{ "ocspi0_Tx_framing_error", 7, 1 },
+		{ "ocspi1_Tx_framing_error", 6, 1 },
+		{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
+		{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
+		{ "ocspi_par_error", 3, 1 },
+		{ "db_options_par_error", 2, 1 },
+		{ "iespi_par_error", 1, 1 },
+		{ "e_pcmd_par_error", 0, 1 },
+	{ "PM_RX_INT_CAUSE", 0x8fdc, 0 },
+		{ "master_perr", 31, 1 },
+		{ "ospi_overflow3", 30, 1 },
+		{ "ospi_overflow2", 29, 1 },
+		{ "ospi_overflow1", 28, 1 },
+		{ "ospi_overflow0", 27, 1 },
+		{ "bundle_len_ovfl", 24, 1 },
+		{ "sdc_err", 23, 1 },
+		{ "zero_e_cmd_error", 22, 1 },
+		{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
+		{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
+		{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
+		{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
+		{ "iespi0_Rx_framing_error", 17, 1 },
+		{ "iespi1_Rx_framing_error", 16, 1 },
+		{ "iespi2_Rx_framing_error", 15, 1 },
+		{ "iespi3_Rx_framing_error", 14, 1 },
+		{ "iespi0_Tx_framing_error", 13, 1 },
+		{ "iespi1_Tx_framing_error", 12, 1 },
+		{ "iespi2_Tx_framing_error", 11, 1 },
+		{ "iespi3_Tx_framing_error", 10, 1 },
+		{ "ocspi0_Rx_framing_error", 9, 1 },
+		{ "ocspi1_Rx_framing_error", 8, 1 },
+		{ "ocspi0_Tx_framing_error", 7, 1 },
+		{ "ocspi1_Tx_framing_error", 6, 1 },
+		{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
+		{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
+		{ "cache_sram_error", 3, 1 },
+		{ "cache_lru_error", 2, 1 },
+		{ "cache_island_error", 1, 1 },
+		{ "cache_ctrl_error", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_pm_tx_regs[] = {
+	{ "PM_TX_CFG", 0x8fe0, 0 },
+		{ "ch1_output", 27, 5 },
+		{ "ch2_output", 22, 5 },
+		{ "ch3_output", 17, 5 },
+		{ "strobe1", 16, 1 },
+		{ "ch1_input", 11, 5 },
+		{ "ch2_input", 6, 5 },
+		{ "ch3_input", 1, 5 },
+		{ "strobe0", 0, 1 },
+	{ "PM_TX_MODE", 0x8fe4, 0 },
+		{ "cong_thresh3", 25, 7 },
+		{ "cong_thresh2", 18, 7 },
+		{ "cong_thresh1", 11, 7 },
+		{ "cong_thresh0", 4, 7 },
+		{ "use_bundle_len", 3, 1 },
+		{ "stat_channel", 1, 2 },
+		{ "prefetch_enable", 0, 1 },
+	{ "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
+	{ "PM_TX_STAT_COUNT", 0x8fec, 0 },
+	{ "PM_TX_DBG_CTRL", 0x8ff0, 0 },
+		{ "OspiWrBusy", 21, 4 },
+		{ "IspiWrBusy", 17, 4 },
+		{ "PMDbgAddr", 0, 17 },
+	{ "PM_TX_DBG_DATA", 0x8ff4, 0 },
+	{ "PM_TX_INT_ENABLE", 0x8ff8, 0 },
+		{ "master_perr", 31, 1 },
+		{ "zero_c_cmd_error", 30, 1 },
+		{ "oespi_cor_err", 29, 1 },
+		{ "icspi_cor_err", 28, 1 },
+		{ "icspi_ovfl", 24, 1 },
+		{ "pcmd_len_ovfl3", 23, 1 },
+		{ "pcmd_len_ovfl2", 22, 1 },
+		{ "pcmd_len_ovfl1", 21, 1 },
+		{ "pcmd_len_ovfl0", 20, 1 },
+		{ "icspi0_fifo2x_Rx_framing_error", 19, 1 },
+		{ "icspi1_fifo2x_Rx_framing_error", 18, 1 },
+		{ "icspi2_fifo2x_Rx_framing_error", 17, 1 },
+		{ "icspi3_fifo2x_Rx_framing_error", 16, 1 },
+		{ "icspi0_Tx_framing_error", 15, 1 },
+		{ "icspi1_Tx_framing_error", 14, 1 },
+		{ "icspi2_Tx_framing_error", 13, 1 },
+		{ "icspi3_Tx_framing_error", 12, 1 },
+		{ "oespi0_Rx_framing_error", 11, 1 },
+		{ "oespi1_Rx_framing_error", 10, 1 },
+		{ "oespi2_Rx_framing_error", 9, 1 },
+		{ "oespi3_Rx_framing_error", 8, 1 },
+		{ "oespi0_Tx_framing_error", 7, 1 },
+		{ "oespi1_Tx_framing_error", 6, 1 },
+		{ "oespi2_Tx_framing_error", 5, 1 },
+		{ "oespi3_Tx_framing_error", 4, 1 },
+		{ "oespi0_ofifo2x_Tx_framing_error", 3, 1 },
+		{ "oespi1_ofifo2x_Tx_framing_error", 2, 1 },
+		{ "oespi2_ofifo2x_Tx_framing_error", 1, 1 },
+		{ "oespi3_ofifo2x_Tx_framing_error", 0, 1 },
+	{ "PM_TX_INT_CAUSE", 0x8ffc, 0 },
+		{ "master_perr", 31, 1 },
+		{ "zero_c_cmd_error", 30, 1 },
+		{ "oespi_cor_err", 29, 1 },
+		{ "icspi_cor_err", 28, 1 },
+		{ "icspi_ovfl", 24, 1 },
+		{ "pcmd_len_ovfl3", 23, 1 },
+		{ "pcmd_len_ovfl2", 22, 1 },
+		{ "pcmd_len_ovfl1", 21, 1 },
+		{ "pcmd_len_ovfl0", 20, 1 },
+		{ "icspi0_fifo2x_Rx_framing_error", 19, 1 },
+		{ "icspi1_fifo2x_Rx_framing_error", 18, 1 },
+		{ "icspi2_fifo2x_Rx_framing_error", 17, 1 },
+		{ "icspi3_fifo2x_Rx_framing_error", 16, 1 },
+		{ "icspi0_Tx_framing_error", 15, 1 },
+		{ "icspi1_Tx_framing_error", 14, 1 },
+		{ "icspi2_Tx_framing_error", 13, 1 },
+		{ "icspi3_Tx_framing_error", 12, 1 },
+		{ "oespi0_Rx_framing_error", 11, 1 },
+		{ "oespi1_Rx_framing_error", 10, 1 },
+		{ "oespi2_Rx_framing_error", 9, 1 },
+		{ "oespi3_Rx_framing_error", 8, 1 },
+		{ "oespi0_Tx_framing_error", 7, 1 },
+		{ "oespi1_Tx_framing_error", 6, 1 },
+		{ "oespi2_Tx_framing_error", 5, 1 },
+		{ "oespi3_Tx_framing_error", 4, 1 },
+		{ "oespi0_ofifo2x_Tx_framing_error", 3, 1 },
+		{ "oespi1_ofifo2x_Tx_framing_error", 2, 1 },
+		{ "oespi2_ofifo2x_Tx_framing_error", 1, 1 },
+		{ "oespi3_ofifo2x_Tx_framing_error", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_mps_regs[] = {
+	{ "MPS_CMN_CTL", 0x9000, 0 },
+		{ "pt1_sel_cfg", 21, 1 },
+		{ "Bug_42938_en", 20, 1 },
+		{ "no_bypass_pause", 19, 1 },
+		{ "bypass_pause", 18, 1 },
+		{ "PBUS_En", 16, 2 },
+		{ "INIC_En", 14, 2 },
+		{ "SBA_En", 12, 2 },
+		{ "BG2TP_MAP_MODE", 11, 1 },
+		{ "LB_Mode", 9, 2 },
+		{ "TX_PORT_STATS_MODE", 8, 1 },
+		{ "T5Mode", 7, 1 },
+		{ "SpeedMode", 5, 2 },
+		{ "LpbkCrdtCtrl", 4, 1 },
+		{ "Detect8023", 3, 1 },
+		{ "VFDirectAccess", 2, 1 },
+		{ "NumPorts", 0, 2 },
+	{ "MPS_INT_ENABLE", 0x9004, 0 },
+		{ "StatIntEnb", 5, 1 },
+		{ "TxIntEnb", 4, 1 },
+		{ "RxIntEnb", 3, 1 },
+		{ "TrcIntEnb", 2, 1 },
+		{ "ClsIntEnb", 1, 1 },
+		{ "PLIntEnb", 0, 1 },
+	{ "MPS_INT_CAUSE", 0x9008, 0 },
+		{ "StatInt", 5, 1 },
+		{ "TxInt", 4, 1 },
+		{ "RxInt", 3, 1 },
+		{ "TrcInt", 2, 1 },
+		{ "ClsInt", 1, 1 },
+		{ "PLInt", 0, 1 },
+	{ "MPS_CGEN_GLOBAL", 0x900c, 0 },
+	{ "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
+	{ "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
+	{ "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
+	{ "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
+	{ "MPS_VF_TX_CTL_159_128", 0x9100, 0 },
+	{ "MPS_VF_TX_CTL_191_160", 0x9104, 0 },
+	{ "MPS_VF_TX_CTL_223_192", 0x9108, 0 },
+	{ "MPS_VF_TX_CTL_255_224", 0x910c, 0 },
+	{ "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
+	{ "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
+	{ "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
+	{ "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
+	{ "MPS_VF_RX_CTL_159_128", 0x9110, 0 },
+	{ "MPS_VF_RX_CTL_191_160", 0x9114, 0 },
+	{ "MPS_VF_RX_CTL_223_192", 0x9118, 0 },
+	{ "MPS_VF_RX_CTL_255_224", 0x911c, 0 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
+	{ "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
+	{ "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
+	{ "MPS_TP_CSIDE_MUX_CTL_P2", 0x9138, 0 },
+	{ "MPS_TP_CSIDE_MUX_CTL_P3", 0x913c, 0 },
+	{ "MPS_WOL_CTL_MODE", 0x9058, 0 },
+	{ "MPS_TOP_SPARE", 0x9074, 0 },
+		{ "TopSpare", 8, 24 },
+		{ "oVlanSelLpbk3", 7, 1 },
+		{ "oVlanSelLpbk2", 6, 1 },
+		{ "oVlanSelLpbk1", 5, 1 },
+		{ "oVlanSelLpbk0", 4, 1 },
+		{ "oVlanSelMac3", 3, 1 },
+		{ "oVlanSelMac2", 2, 1 },
+		{ "oVlanSelMac1", 1, 1 },
+		{ "oVlanSelMac0", 0, 1 },
+	{ "MPS_BUILD_REVISION", 0x9078, 0 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 },
+		{ "Value_1", 16, 16 },
+		{ "Value_0", 0, 16 },
+	{ "MPS_FPGA_BIST_CFG_P0", 0x9120, 0 },
+		{ "AddrMask", 16, 16 },
+		{ "BaseAddr", 0, 16 },
+	{ "MPS_FPGA_BIST_CFG_P1", 0x9124, 0 },
+		{ "AddrMask", 16, 16 },
+		{ "BaseAddr", 0, 16 },
+	{ "MPS_FPGA_BIST_CFG_P2", 0x9128, 0 },
+		{ "AddrMask", 16, 16 },
+		{ "BaseAddr", 0, 16 },
+	{ "MPS_FPGA_BIST_CFG_P3", 0x912c, 0 },
+		{ "AddrMask", 16, 16 },
+		{ "BaseAddr", 0, 16 },
+	{ "MPS_INIC_CTL", 0x9130, 0 },
+		{ "RD_WRN", 16, 1 },
+		{ "ADDR", 0, 16 },
+	{ "MPS_INIC_DATA", 0x9134, 0 },
+	{ "MPS_RED_CTL", 0x9140, 0 },
+		{ "LPBK_SHIFT_0", 28, 4 },
+		{ "LPBK_SHIFT_1", 24, 4 },
+		{ "LPBK_SHIFT_2", 20, 4 },
+		{ "LPBK_SHIFT_3", 16, 4 },
+		{ "MAC_SHIFT_0", 12, 4 },
+		{ "MAC_SHIFT_1", 8, 4 },
+		{ "MAC_SHIFT_2", 4, 4 },
+		{ "MAC_SHIFT_3", 0, 4 },
+	{ "MPS_RED_EN", 0x9144, 0 },
+		{ "LPBK_EN3", 7, 1 },
+		{ "LPBK_EN2", 6, 1 },
+		{ "LPBK_EN1", 5, 1 },
+		{ "LPBK_EN0", 4, 1 },
+		{ "MAC_EN3", 3, 1 },
+		{ "MAC_EN2", 2, 1 },
+		{ "MAC_EN1", 1, 1 },
+		{ "MAC_EN0", 0, 1 },
+	{ "MPS_MAC0_RED_DROP_CNT_H", 0x9148, 0 },
+	{ "MPS_MAC0_RED_DROP_CNT_L", 0x914c, 0 },
+	{ "MPS_MAC1_RED_DROP_CNT_H", 0x9150, 0 },
+	{ "MPS_MAC1_RED_DROP_CNT_L", 0x9154, 0 },
+	{ "MPS_MAC2_RED_DROP_CNT_H", 0x9158, 0 },
+	{ "MPS_MAC2_RED_DROP_CNT_L", 0x915c, 0 },
+	{ "MPS_MAC3_RED_DROP_CNT_H", 0x9160, 0 },
+	{ "MPS_MAC3_RED_DROP_CNT_L", 0x9164, 0 },
+	{ "MPS_LPBK0_RED_DROP_CNT_H", 0x9168, 0 },
+	{ "MPS_LPBK0_RED_DROP_CNT_L", 0x916c, 0 },
+	{ "MPS_LPBK1_RED_DROP_CNT_H", 0x9170, 0 },
+	{ "MPS_LPBK1_RED_DROP_CNT_L", 0x9174, 0 },
+	{ "MPS_LPBK2_RED_DROP_CNT_H", 0x9178, 0 },
+	{ "MPS_LPBK2_RED_DROP_CNT_L", 0x917c, 0 },
+	{ "MPS_LPBK3_RED_DROP_CNT_H", 0x9180, 0 },
+	{ "MPS_LPBK3_RED_DROP_CNT_L", 0x9184, 0 },
+	{ "MPS_MAC_RED_PP_DROP_EN", 0x9188, 0 },
+		{ "MAC3", 24, 8 },
+		{ "MAC2", 16, 8 },
+		{ "MAC1", 8, 8 },
+		{ "MAC0", 0, 8 },
+	{ "MPS_PORT_CTL", 0x30000, 0 },
+		{ "LpbkEn", 31, 1 },
+		{ "TxEn", 30, 1 },
+		{ "RxEn", 29, 1 },
+		{ "PPPEn", 28, 1 },
+		{ "FCSStripEn", 27, 1 },
+		{ "PPPAndPause", 26, 1 },
+		{ "PrioPPPEnMap", 16, 8 },
+	{ "MPS_PORT_PAUSE_CTL", 0x30004, 0 },
+	{ "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 },
+		{ "RegSendOff", 24, 8 },
+		{ "RegSendOn", 16, 8 },
+		{ "SgeSendEn", 8, 8 },
+		{ "RxSendEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 },
+	{ "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 },
+		{ "RegHaltOn", 8, 8 },
+		{ "RxHaltEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 },
+		{ "RegSending", 16, 8 },
+		{ "SgeSending", 8, 8 },
+		{ "RxSending", 0, 8 },
+	{ "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 },
+		{ "RegHalted", 8, 8 },
+		{ "RxHalted", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 },
+	{ "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 },
+		{ "Prty7", 14, 2 },
+		{ "Prty6", 12, 2 },
+		{ "Prty5", 10, 2 },
+		{ "Prty4", 8, 2 },
+		{ "Prty3", 6, 2 },
+		{ "Prty2", 4, 2 },
+		{ "Prty1", 2, 2 },
+		{ "Prty0", 0, 2 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_PRTY_GROUP_MAP", 0x30034, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_TRACE_MAX_CAPTURE_SIZE", 0x30038, 0 },
+		{ "TX2RX", 6, 3 },
+		{ "MAC2MPS", 3, 3 },
+		{ "MPS2MAC", 0, 3 },
+	{ "MPS_PORT_CTL", 0x32000, 0 },
+		{ "LpbkEn", 31, 1 },
+		{ "TxEn", 30, 1 },
+		{ "RxEn", 29, 1 },
+		{ "PPPEn", 28, 1 },
+		{ "FCSStripEn", 27, 1 },
+		{ "PPPAndPause", 26, 1 },
+		{ "PrioPPPEnMap", 16, 8 },
+	{ "MPS_PORT_PAUSE_CTL", 0x32004, 0 },
+	{ "MPS_PORT_TX_PAUSE_CTL", 0x32008, 0 },
+		{ "RegSendOff", 24, 8 },
+		{ "RegSendOn", 16, 8 },
+		{ "SgeSendEn", 8, 8 },
+		{ "RxSendEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_CTL2", 0x3200c, 0 },
+	{ "MPS_PORT_RX_PAUSE_CTL", 0x32010, 0 },
+		{ "RegHaltOn", 8, 8 },
+		{ "RxHaltEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_STATUS", 0x32014, 0 },
+		{ "RegSending", 16, 8 },
+		{ "SgeSending", 8, 8 },
+		{ "RxSending", 0, 8 },
+	{ "MPS_PORT_RX_PAUSE_STATUS", 0x32018, 0 },
+		{ "RegHalted", 8, 8 },
+		{ "RxHalted", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3201c, 0 },
+	{ "MPS_PORT_TX_PAUSE_DEST_H", 0x32020, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x32024, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x32028, 0 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3202c, 0 },
+		{ "Prty7", 14, 2 },
+		{ "Prty6", 12, 2 },
+		{ "Prty5", 10, 2 },
+		{ "Prty4", 8, 2 },
+		{ "Prty3", 6, 2 },
+		{ "Prty2", 4, 2 },
+		{ "Prty1", 2, 2 },
+		{ "Prty0", 0, 2 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x32030, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_PRTY_GROUP_MAP", 0x32034, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_TRACE_MAX_CAPTURE_SIZE", 0x32038, 0 },
+		{ "TX2RX", 6, 3 },
+		{ "MAC2MPS", 3, 3 },
+		{ "MPS2MAC", 0, 3 },
+	{ "MPS_PORT_CTL", 0x34000, 0 },
+		{ "LpbkEn", 31, 1 },
+		{ "TxEn", 30, 1 },
+		{ "RxEn", 29, 1 },
+		{ "PPPEn", 28, 1 },
+		{ "FCSStripEn", 27, 1 },
+		{ "PPPAndPause", 26, 1 },
+		{ "PrioPPPEnMap", 16, 8 },
+	{ "MPS_PORT_PAUSE_CTL", 0x34004, 0 },
+	{ "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 },
+		{ "RegSendOff", 24, 8 },
+		{ "RegSendOn", 16, 8 },
+		{ "SgeSendEn", 8, 8 },
+		{ "RxSendEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 },
+	{ "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 },
+		{ "RegHaltOn", 8, 8 },
+		{ "RxHaltEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 },
+		{ "RegSending", 16, 8 },
+		{ "SgeSending", 8, 8 },
+		{ "RxSending", 0, 8 },
+	{ "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 },
+		{ "RegHalted", 8, 8 },
+		{ "RxHalted", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 },
+	{ "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 },
+		{ "Prty7", 14, 2 },
+		{ "Prty6", 12, 2 },
+		{ "Prty5", 10, 2 },
+		{ "Prty4", 8, 2 },
+		{ "Prty3", 6, 2 },
+		{ "Prty2", 4, 2 },
+		{ "Prty1", 2, 2 },
+		{ "Prty0", 0, 2 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_PRTY_GROUP_MAP", 0x34034, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_TRACE_MAX_CAPTURE_SIZE", 0x34038, 0 },
+		{ "TX2RX", 6, 3 },
+		{ "MAC2MPS", 3, 3 },
+		{ "MPS2MAC", 0, 3 },
+	{ "MPS_PORT_CTL", 0x36000, 0 },
+		{ "LpbkEn", 31, 1 },
+		{ "TxEn", 30, 1 },
+		{ "RxEn", 29, 1 },
+		{ "PPPEn", 28, 1 },
+		{ "FCSStripEn", 27, 1 },
+		{ "PPPAndPause", 26, 1 },
+		{ "PrioPPPEnMap", 16, 8 },
+	{ "MPS_PORT_PAUSE_CTL", 0x36004, 0 },
+	{ "MPS_PORT_TX_PAUSE_CTL", 0x36008, 0 },
+		{ "RegSendOff", 24, 8 },
+		{ "RegSendOn", 16, 8 },
+		{ "SgeSendEn", 8, 8 },
+		{ "RxSendEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_CTL2", 0x3600c, 0 },
+	{ "MPS_PORT_RX_PAUSE_CTL", 0x36010, 0 },
+		{ "RegHaltOn", 8, 8 },
+		{ "RxHaltEn", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_STATUS", 0x36014, 0 },
+		{ "RegSending", 16, 8 },
+		{ "SgeSending", 8, 8 },
+		{ "RxSending", 0, 8 },
+	{ "MPS_PORT_RX_PAUSE_STATUS", 0x36018, 0 },
+		{ "RegHalted", 8, 8 },
+		{ "RxHalted", 0, 8 },
+	{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3601c, 0 },
+	{ "MPS_PORT_TX_PAUSE_DEST_H", 0x36020, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x36024, 0 },
+	{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x36028, 0 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3602c, 0 },
+		{ "Prty7", 14, 2 },
+		{ "Prty6", 12, 2 },
+		{ "Prty5", 10, 2 },
+		{ "Prty4", 8, 2 },
+		{ "Prty3", 6, 2 },
+		{ "Prty2", 4, 2 },
+		{ "Prty1", 2, 2 },
+		{ "Prty0", 0, 2 },
+	{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x36030, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_PRTY_GROUP_MAP", 0x36034, 0 },
+		{ "Prty7", 28, 4 },
+		{ "Prty6", 24, 4 },
+		{ "Prty5", 20, 4 },
+		{ "Prty4", 16, 4 },
+		{ "Prty3", 12, 4 },
+		{ "Prty2", 8, 4 },
+		{ "Prty1", 4, 4 },
+		{ "Prty0", 0, 4 },
+	{ "MPS_PORT_TRACE_MAX_CAPTURE_SIZE", 0x36038, 0 },
+		{ "TX2RX", 6, 3 },
+		{ "MAC2MPS", 3, 3 },
+		{ "MPS2MAC", 0, 3 },
+	{ "MPS_PF_CTL", 0x1e2c0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1e6c0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1eac0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1eec0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1f2c0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1f6c0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1fac0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_PF_CTL", 0x1fec0, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "MPS_RX_CTL", 0x11000, 0 },
+		{ "HASH_TCAM_EN", 19, 1 },
+		{ "SND_ORG_PFVF", 18, 1 },
+		{ "FILT_VLAN_SEL", 17, 1 },
+		{ "CBA_EN", 16, 1 },
+		{ "BLK_SNDR", 12, 4 },
+		{ "CMPRS", 8, 4 },
+		{ "SNF", 0, 8 },
+	{ "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
+		{ "CTL_P3", 12, 4 },
+		{ "CTL_P2", 8, 4 },
+		{ "CTL_P1", 4, 4 },
+		{ "CTL_P0", 0, 4 },
+	{ "MPS_RX_FIFO_0_CTL", 0x11008, 0 },
+	{ "MPS_RX_FIFO_1_CTL", 0x1100c, 0 },
+	{ "MPS_RX_FIFO_2_CTL", 0x11010, 0 },
+	{ "MPS_RX_FIFO_3_CTL", 0x11014, 0 },
+	{ "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
+		{ "EN", 31, 1 },
+		{ "TH", 0, 11 },
+	{ "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
+		{ "EN", 31, 1 },
+		{ "TH", 0, 11 },
+	{ "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
+		{ "EN", 31, 1 },
+		{ "TH", 0, 11 },
+	{ "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
+		{ "EN", 31, 1 },
+		{ "TH", 0, 11 },
+	{ "MPS_RX_OCH_CTL", 0x11058, 0 },
+		{ "DROP_WT", 27, 5 },
+		{ "TRUNC_WT", 22, 5 },
+		{ "DRAIN", 13, 5 },
+		{ "DROP", 8, 5 },
+		{ "STOP", 0, 5 },
+	{ "MPS_RX_LPBK_BP0", 0x1105c, 0 },
+	{ "MPS_RX_LPBK_BP1", 0x11060, 0 },
+	{ "MPS_RX_LPBK_BP2", 0x11064, 0 },
+	{ "MPS_RX_LPBK_BP3", 0x11068, 0 },
+	{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
+	{ "MPS_CTL_STAT", 0x11070, 0 },
+	{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
+		{ "MAC_IN_FIFO_768b", 30, 1 },
+		{ "INT_ERR_INT", 29, 1 },
+		{ "FLOP_PERR", 28, 1 },
+		{ "ATRB", 18, 1 },
+		{ "RPLC_MAP", 13, 5 },
+		{ "TKN_RUNT_DROP_FIFO", 12, 1 },
+		{ "PPM3", 9, 3 },
+		{ "PPM2", 6, 3 },
+		{ "PPM1", 3, 3 },
+		{ "PPM0", 0, 3 },
+	{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
+		{ "INT_ERR_INT", 30, 1 },
+		{ "FLOP_PERR", 28, 1 },
+		{ "ATRB", 18, 1 },
+		{ "RPLC_MAP", 13, 5 },
+		{ "PPM3", 9, 3 },
+		{ "PPM2", 6, 3 },
+		{ "PPM1", 3, 3 },
+		{ "PPM0", 0, 3 },
+	{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
+		{ "INT_ERR_INT", 30, 1 },
+		{ "FLOP_PERR", 28, 1 },
+		{ "ATRB", 18, 1 },
+		{ "RPLC_MAP", 13, 5 },
+		{ "PPM3", 9, 3 },
+		{ "PPM2", 6, 3 },
+		{ "PPM1", 3, 3 },
+		{ "PPM0", 0, 3 },
+	{ "MPS_RX_PERR_INT_CAUSE2", 0x1108c, 0 },
+		{ "crypt2mps_rx_intf_fifo", 28, 4 },
+		{ "inic2mps_tx0_perr", 27, 1 },
+		{ "inic2mps_tx1_perr", 26, 1 },
+		{ "xgmac2mps_rx0_perr", 25, 1 },
+		{ "xgmac2mps_rx1_perr", 24, 1 },
+		{ "mps2crypto_rx_intf_fifo", 20, 4 },
+		{ "RX_PRE_PROC_PERR", 9, 11 },
+	{ "MPS_RX_PERR_INT_ENABLE2", 0x11090, 0 },
+		{ "crypt2mps_rx_intf_fifo", 28, 4 },
+		{ "inic2mps_tx0_perr", 27, 1 },
+		{ "inic2mps_tx1_perr", 26, 1 },
+		{ "xgmac2mps_rx0_perr", 25, 1 },
+		{ "xgmac2mps_rx1_perr", 24, 1 },
+		{ "mps2crypto_rx_intf_fifo", 20, 4 },
+		{ "RX_PRE_PROC_PERR", 9, 11 },
+	{ "MPS_RX_PERR_ENABLE2", 0x11094, 0 },
+		{ "crypt2mps_rx_intf_fifo", 28, 4 },
+		{ "inic2mps_tx0_perr", 27, 1 },
+		{ "inic2mps_tx1_perr", 26, 1 },
+		{ "xgmac2mps_rx0_perr", 25, 1 },
+		{ "xgmac2mps_rx1_perr", 24, 1 },
+		{ "mps2crypto_rx_intf_fifo", 20, 4 },
+		{ "RX_PRE_PROC_PERR", 9, 11 },
+	{ "MPS_RX_PERR_INT_CAUSE3", 0x11310, 0 },
+	{ "MPS_RX_PERR_INT_ENABLE3", 0x11314, 0 },
+	{ "MPS_RX_PERR_ENABLE3", 0x11318, 0 },
+	{ "MPS_RX_PERR_INT_CAUSE4", 0x1131c, 0 },
+		{ "CLS", 20, 6 },
+		{ "rx_pre_proc", 16, 4 },
+		{ "pproc3", 12, 4 },
+		{ "pproc2", 8, 4 },
+		{ "pproc1", 4, 4 },
+		{ "pproc0", 0, 4 },
+	{ "MPS_RX_PERR_INT_ENABLE4", 0x11320, 0 },
+		{ "CLS", 20, 6 },
+		{ "rx_pre_proc", 16, 4 },
+		{ "pproc3", 12, 4 },
+		{ "pproc2", 8, 4 },
+		{ "pproc1", 4, 4 },
+		{ "pproc0", 0, 4 },
+	{ "MPS_RX_PERR_ENABLE4", 0x11324, 0 },
+		{ "CLS", 20, 6 },
+		{ "rx_pre_proc", 16, 4 },
+		{ "pproc3", 12, 4 },
+		{ "pproc2", 8, 4 },
+		{ "pproc1", 4, 4 },
+		{ "pproc0", 0, 4 },
+	{ "MPS_RX_PERR_INT_CAUSE5", 0x11328, 0 },
+		{ "mps2cryp_rx_fifo", 26, 4 },
+		{ "rx_out", 20, 6 },
+		{ "MEM_WRAP", 0, 20 },
+	{ "MPS_RX_PERR_INT_ENABLE5", 0x1132c, 0 },
+		{ "mps2cryp_rx_fifo", 26, 4 },
+		{ "rx_out", 20, 6 },
+		{ "MEM_WRAP", 0, 20 },
+	{ "MPS_RX_PERR_ENABLE5", 0x11330, 0 },
+		{ "mps2cryp_rx_fifo", 26, 4 },
+		{ "rx_out", 20, 6 },
+		{ "MEM_WRAP", 0, 20 },
+	{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MPS_RX_PERR_INT_CAUSE6", 0x11334, 0 },
+	{ "MPS_RX_PERR_INT_ENABLE6", 0x11338, 0 },
+	{ "MPS_RX_PERR_ENABLE6", 0x1133c, 0 },
+	{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
+		{ "MTU_ERR_INT3", 19, 1 },
+		{ "MTU_ERR_INT2", 18, 1 },
+		{ "MTU_ERR_INT1", 17, 1 },
+		{ "MTU_ERR_INT0", 16, 1 },
+		{ "SE_CNT_ERR_INT", 15, 1 },
+		{ "FRM_ERR_INT", 14, 1 },
+		{ "LEN_ERR_INT", 13, 1 },
+		{ "INT_ERR_INT", 8, 5 },
+		{ "PG_TH_INT7", 7, 1 },
+		{ "PG_TH_INT6", 6, 1 },
+		{ "PG_TH_INT5", 5, 1 },
+		{ "PG_TH_INT4", 4, 1 },
+		{ "PG_TH_INT3", 3, 1 },
+		{ "PG_TH_INT2", 2, 1 },
+		{ "PG_TH_INT1", 1, 1 },
+		{ "PG_TH_INT0", 0, 1 },
+	{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
+		{ "MTU_ERR_INT3", 19, 1 },
+		{ "MTU_ERR_INT2", 18, 1 },
+		{ "MTU_ERR_INT1", 17, 1 },
+		{ "MTU_ERR_INT0", 16, 1 },
+		{ "SE_CNT_ERR_INT", 15, 1 },
+		{ "FRM_ERR_INT", 14, 1 },
+		{ "LEN_ERR_INT", 13, 1 },
+		{ "INT_ERR_INT", 8, 5 },
+		{ "PG_TH_INT7", 7, 1 },
+		{ "PG_TH_INT6", 6, 1 },
+		{ "PG_TH_INT5", 5, 1 },
+		{ "PG_TH_INT4", 4, 1 },
+		{ "PG_TH_INT3", 3, 1 },
+		{ "PG_TH_INT2", 2, 1 },
+		{ "PG_TH_INT1", 1, 1 },
+		{ "PG_TH_INT0", 0, 1 },
+	{ "MPS_RX_REPL_CTL", 0x11098, 0 },
+	{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
+		{ "ETYPE", 16, 16 },
+		{ "OPCODE", 0, 16 },
+	{ "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
+		{ "ETYPE", 16, 16 },
+		{ "DA", 0, 16 },
+	{ "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
+	{ "MPS_RX_PT_ARB0", 0x110a8, 0 },
+		{ "LPBK_WT", 16, 14 },
+		{ "MAC_WT", 0, 14 },
+	{ "MPS_RX_PT_ARB1", 0x110ac, 0 },
+		{ "LPBK_WT", 16, 14 },
+		{ "MAC_WT", 0, 14 },
+	{ "MPS_RX_PT_ARB2", 0x11468, 0 },
+		{ "LPBK_WT", 16, 14 },
+		{ "MAC_WT", 0, 14 },
+	{ "MPS_RX_PT_ARB3", 0x1146c, 0 },
+		{ "LPBK_WT", 16, 14 },
+		{ "MAC_WT", 0, 14 },
+	{ "MPS_RX_PT_ARB4", 0x110b0, 0 },
+		{ "LPBK_WT", 16, 14 },
+		{ "MAC_WT", 0, 14 },
+	{ "MPS_PF_OUT_EN", 0x110b4, 0 },
+	{ "MPS_BMC_MTU", 0x110b8, 0 },
+	{ "MPS_BMC_PKT_CNT", 0x110bc, 0 },
+	{ "MPS_BMC_BYTE_CNT", 0x110c0, 0 },
+	{ "MPS_PFVF_ATRB_CTL", 0x110c4, 0 },
+		{ "RD_WRN", 31, 1 },
+		{ "PFVF", 0, 9 },
+	{ "MPS_PFVF_ATRB", 0x110c8, 0 },
+		{ "EXTRACT_DEL_VLAN", 31, 1 },
+		{ "PF", 28, 3 },
+		{ "OFF", 18, 1 },
+		{ "NV_DROP", 17, 1 },
+		{ "MODE", 16, 1 },
+		{ "FULL_FRAME_MODE", 14, 1 },
+		{ "MTU", 0, 14 },
+	{ "MPS_PFVF_ATRB2", 0x120fc, 0 },
+		{ "EXTRACT_DEL_ENCAP", 31, 1 },
+	{ "MPS_PFVF_ATRB_FLTR0", 0x110cc, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR1", 0x110d0, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR2", 0x110d4, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR3", 0x110d8, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR4", 0x110dc, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR5", 0x110e0, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR6", 0x110e4, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR7", 0x110e8, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR8", 0x110ec, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR9", 0x110f0, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR10", 0x110f4, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR11", 0x110f8, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR12", 0x110fc, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR13", 0x11100, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR14", 0x11104, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PFVF_ATRB_FLTR15", 0x11108, 0 },
+		{ "VLAN_EN", 16, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_RPLC_MAP_CTL", 0x1110c, 0 },
+		{ "RD_WRN", 31, 1 },
+		{ "ADDR", 0, 12 },
+	{ "MPS_PF_RPLCT_MAP", 0x11110, 0 },
+	{ "MPS_VF_RPLCT_MAP0", 0x11114, 0 },
+	{ "MPS_VF_RPLCT_MAP1", 0x11118, 0 },
+	{ "MPS_VF_RPLCT_MAP2", 0x1111c, 0 },
+	{ "MPS_VF_RPLCT_MAP3", 0x11120, 0 },
+	{ "MPS_VF_RPLCT_MAP4", 0x11300, 0 },
+	{ "MPS_VF_RPLCT_MAP5", 0x11304, 0 },
+	{ "MPS_VF_RPLCT_MAP6", 0x11308, 0 },
+	{ "MPS_VF_RPLCT_MAP7", 0x1130c, 0 },
+	{ "MPS_PKD_MEM_DATA0", 0x11130, 0 },
+	{ "MPS_PKD_MEM_DATA1", 0x11134, 0 },
+	{ "MPS_PKD_MEM_DATA2", 0x11138, 0 },
+	{ "MPS_PGD_MEM_DATA", 0x1113c, 0 },
+	{ "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
+	{ "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
+	{ "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
+		{ "ST3", 24, 8 },
+		{ "ST2", 16, 8 },
+		{ "ST1", 8, 8 },
+		{ "ST0", 0, 8 },
+	{ "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
+		{ "ST_NCSI", 23, 9 },
+		{ "ST_TP", 0, 23 },
+	{ "MPS_RX_SPARE", 0x11190, 0 },
+	{ "MPS_RX_PTP_ETYPE", 0x11194, 0 },
+		{ "PETYPE2", 16, 16 },
+		{ "PETYPE1", 0, 16 },
+	{ "MPS_RX_PTP_TCP", 0x11198, 0 },
+		{ "PTCPORT2", 16, 16 },
+		{ "PTCPORT1", 0, 16 },
+	{ "MPS_RX_PTP_UDP", 0x1119c, 0 },
+		{ "PUDPORT2", 16, 16 },
+		{ "PUDPORT1", 0, 16 },
+	{ "MPS_RX_PTP_CTL", 0x111a0, 0 },
+		{ "MIN_PTP_SPACE", 24, 7 },
+		{ "PUDP2EN", 20, 4 },
+		{ "PUDP1EN", 16, 4 },
+		{ "PTCP2EN", 12, 4 },
+		{ "PTCP1EN", 8, 4 },
+		{ "PETYPE2EN", 4, 4 },
+		{ "PETYPE1EN", 0, 4 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_0", 0x12104, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_1", 0x12108, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_2", 0x1210c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_3", 0x12110, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_4", 0x12114, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_5", 0x12118, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_6", 0x1211c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_0_7", 0x12120, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_0", 0x12124, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_1", 0x12128, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_2", 0x1212c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_3", 0x12130, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_4", 0x12134, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_5", 0x12138, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_6", 0x1213c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1_7", 0x12140, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_0", 0x12144, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_1", 0x12148, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_2", 0x1214c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_3", 0x12150, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_4", 0x12154, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_5", 0x12158, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_6", 0x1215c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2_7", 0x12160, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_0", 0x12164, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_1", 0x12168, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_2", 0x1216c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_3", 0x12170, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_4", 0x12174, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_5", 0x12178, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_6", 0x1217c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3_7", 0x12180, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_DROP_0_0", 0x12184, 0 },
+	{ "MPS_RX_DROP_0_1", 0x12188, 0 },
+	{ "MPS_RX_DROP_0_2", 0x1218c, 0 },
+	{ "MPS_RX_DROP_0_3", 0x12190, 0 },
+	{ "MPS_RX_DROP_0_4", 0x12194, 0 },
+	{ "MPS_RX_DROP_0_5", 0x12198, 0 },
+	{ "MPS_RX_DROP_0_6", 0x1219c, 0 },
+	{ "MPS_RX_DROP_0_7", 0x121a0, 0 },
+	{ "MPS_RX_DROP_1_0", 0x121a4, 0 },
+	{ "MPS_RX_DROP_1_1", 0x121a8, 0 },
+	{ "MPS_RX_DROP_1_2", 0x121ac, 0 },
+	{ "MPS_RX_DROP_1_3", 0x121b0, 0 },
+	{ "MPS_RX_DROP_1_4", 0x121b4, 0 },
+	{ "MPS_RX_DROP_1_5", 0x121b8, 0 },
+	{ "MPS_RX_DROP_1_6", 0x121bc, 0 },
+	{ "MPS_RX_DROP_1_7", 0x121c0, 0 },
+	{ "MPS_RX_DROP_2_0", 0x121c4, 0 },
+	{ "MPS_RX_DROP_2_1", 0x121c8, 0 },
+	{ "MPS_RX_DROP_2_2", 0x121cc, 0 },
+	{ "MPS_RX_DROP_2_3", 0x121d0, 0 },
+	{ "MPS_RX_DROP_2_4", 0x121d4, 0 },
+	{ "MPS_RX_DROP_2_5", 0x121d8, 0 },
+	{ "MPS_RX_DROP_2_6", 0x121dc, 0 },
+	{ "MPS_RX_DROP_2_7", 0x121e0, 0 },
+	{ "MPS_RX_DROP_3_0", 0x121e4, 0 },
+	{ "MPS_RX_DROP_3_1", 0x121e8, 0 },
+	{ "MPS_RX_DROP_3_2", 0x121ec, 0 },
+	{ "MPS_RX_DROP_3_3", 0x121f0, 0 },
+	{ "MPS_RX_DROP_3_4", 0x121f4, 0 },
+	{ "MPS_RX_DROP_3_5", 0x121f8, 0 },
+	{ "MPS_RX_DROP_3_6", 0x121fc, 0 },
+	{ "MPS_RX_DROP_3_7", 0x12200, 0 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_0", 0x12204, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_1", 0x12208, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_2", 0x1220c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_3", 0x12210, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_4", 0x12214, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_5", 0x12218, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_6", 0x1221c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT0_7", 0x12220, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_0", 0x12224, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_1", 0x12228, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_2", 0x1222c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_3", 0x12230, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_4", 0x12234, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_5", 0x12238, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_6", 0x1223c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1_7", 0x12240, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_0", 0x12244, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_1", 0x12248, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_2", 0x1224c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_3", 0x12250, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_4", 0x12254, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_5", 0x12258, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_6", 0x1225c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2_7", 0x12260, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_0", 0x12264, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_1", 0x12268, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_2", 0x1226c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_3", 0x12270, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_4", 0x12274, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_5", 0x12278, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_6", 0x1227c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3_7", 0x12280, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_PAUSE_GEN_TH_0", 0x12284, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_1", 0x12288, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_2", 0x1228c, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_PAUSE_GEN_TH_3", 0x12290, 0 },
+		{ "TH_HIGH", 16, 16 },
+		{ "TH_LOW", 0, 16 },
+	{ "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 },
+	{ "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 },
+	{ "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 },
+	{ "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 },
+	{ "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 },
+	{ "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 },
+	{ "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 },
+	{ "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 },
+	{ "MPS_RX_CGEN", 0x11204, 0 },
+		{ "MPS_RX_CGEN_NCSI", 12, 1 },
+		{ "MPS_RX_CGEN_OUT", 8, 4 },
+		{ "MPS_RX_CGEN_LPBK_IN", 4, 4 },
+		{ "MPS_RX_CGEN_MAC_IN", 0, 4 },
+	{ "MPS_RX_MAC_BG_PG_CNT0", 0x11208, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT1", 0x1120c, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT2", 0x11210, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_MAC_BG_PG_CNT3", 0x11214, 0 },
+		{ "MAC_USED", 16, 11 },
+		{ "MAC_ALLOC", 0, 11 },
+	{ "MPS_RX_LPBK_BG_PG_CNT0", 0x11218, 0 },
+		{ "LPBK_USED", 16, 11 },
+		{ "LPBK_ALLOC", 0, 11 },
+	{ "MPS_RX_LPBK_BG_PG_CNT1", 0x1121c, 0 },
+		{ "LPBK_USED", 16, 11 },
+		{ "LPBK_ALLOC", 0, 11 },
+	{ "MPS_RX_LPBK_BG_PG_CNT2", 0x11220, 0 },
+		{ "LPBK_USED", 16, 11 },
+		{ "LPBK_ALLOC", 0, 11 },
+	{ "MPS_RX_LPBK_BG_PG_CNT3", 0x11224, 0 },
+		{ "LPBK_USED", 16, 11 },
+		{ "LPBK_ALLOC", 0, 11 },
+	{ "MPS_RX_CONGESTION_THRESHOLD_BG0", 0x11228, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_CONGESTION_THRESHOLD_BG1", 0x1122c, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_CONGESTION_THRESHOLD_BG2", 0x11230, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_CONGESTION_THRESHOLD_BG3", 0x11234, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_LPBK_CONGESTION_THRESHOLD_BG0", 0x122b4, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_LPBK_CONGESTION_THRESHOLD_BG1", 0x122b8, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_LPBK_CONGESTION_THRESHOLD_BG2", 0x122bc, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_LPBK_CONGESTION_THRESHOLD_BG3", 0x122c0, 0 },
+		{ "CONG_EN", 31, 1 },
+		{ "CONG_TH", 0, 20 },
+	{ "MPS_RX_GRE_PROT_TYPE", 0x11238, 0 },
+		{ "NVGRE_EN", 9, 1 },
+		{ "GRE_EN", 8, 1 },
+		{ "GRE", 0, 8 },
+	{ "MPS_RX_VXLAN_TYPE", 0x1123c, 0 },
+		{ "VXLAN_EN", 16, 1 },
+		{ "VXLAN", 0, 16 },
+	{ "MPS_RX_GENEVE_TYPE", 0x11240, 0 },
+		{ "GENEVE_EN", 16, 1 },
+		{ "GENEVE", 0, 16 },
+	{ "MPS_RX_INNER_HDR_IVLAN", 0x11244, 0 },
+		{ "IVLAN_EN", 16, 1 },
+		{ "IVLAN_ETYPE", 0, 16 },
+	{ "MPS_RX_ENCAP_NVGRE", 0x11248, 0 },
+		{ "ETYPE_EN", 16, 1 },
+		{ "ETYPE", 0, 16 },
+	{ "MPS_RX_ENCAP_GENEVE", 0x1124c, 0 },
+		{ "ETYPE_EN", 16, 1 },
+		{ "ETYPE", 0, 16 },
+	{ "MPS_RX_ENCAP_VXLAN", 0x120f0, 0 },
+		{ "ETYPE_EN", 16, 1 },
+		{ "ETYPE", 0, 16 },
+	{ "MPS_RX_INT_VXLAN", 0x120f4, 0 },
+		{ "INT_TYPE_EN", 16, 1 },
+		{ "INT_TYPE", 0, 16 },
+	{ "MPS_RX_INT_GENEVE", 0x120f8, 0 },
+		{ "INT_TYPE_EN", 16, 1 },
+		{ "INT_TYPE", 0, 16 },
+	{ "MPS_RX_TCP", 0x11250, 0 },
+		{ "PROT_TYPE_EN", 8, 1 },
+		{ "PROT_TYPE", 0, 8 },
+	{ "MPS_RX_UDP", 0x11254, 0 },
+		{ "PROT_TYPE_EN", 8, 1 },
+		{ "PROT_TYPE", 0, 8 },
+	{ "MPS_RX_PAUSE", 0x11258, 0 },
+	{ "MPS_RX_LENGTH", 0x1125c, 0 },
+		{ "SAP_VALUE", 16, 16 },
+		{ "LENGTH_ETYPE", 0, 16 },
+	{ "MPS_RX_CTL_ORG", 0x11260, 0 },
+		{ "CTL_VALUE", 24, 8 },
+		{ "ORG_VALUE", 0, 24 },
+	{ "MPS_RX_IPV4", 0x11264, 0 },
+	{ "MPS_RX_IPV6", 0x11268, 0 },
+	{ "MPS_RX_TTL", 0x1126c, 0 },
+		{ "TTL_IPV4", 10, 8 },
+		{ "TTL_IPV6", 2, 8 },
+		{ "TTL_CHK_EN_IPV4", 1, 1 },
+		{ "TTL_CHK_EN_IPV6", 0, 1 },
+	{ "MPS_RX_DEFAULT_VNI", 0x11270, 0 },
+	{ "MPS_RX_PRS_CTL", 0x11274, 0 },
+		{ "CTL_CHK_EN", 28, 1 },
+		{ "ORG_CHK_EN", 27, 1 },
+		{ "SAP_CHK_EN", 26, 1 },
+		{ "VXLAN_FLAG_CHK_EN", 25, 1 },
+		{ "VXLAN_FLAG_MASK", 17, 8 },
+		{ "VXLAN_FLAG", 9, 8 },
+		{ "GRE_VER_CHK_EN", 8, 1 },
+		{ "GRE_VER", 5, 3 },
+		{ "GENEVE_VER_CHK_EN", 4, 1 },
+		{ "GENEVE_VER", 2, 2 },
+		{ "DIP_EN", 1, 1 },
+	{ "MPS_RX_PRS_CTL_2", 0x11278, 0 },
+		{ "IP_EXT_HDR_EN", 5, 1 },
+		{ "EN_UDP_CSUM_CHK", 4, 1 },
+		{ "EN_UDP_LEN_CHK", 3, 1 },
+		{ "EN_IP_CSUM_CHK", 2, 1 },
+		{ "EN_IP_PAYLOAD_LEN_CHK", 1, 1 },
+		{ "IPV6_UDP_CSUM_COMPAT", 0, 1 },
+	{ "MPS_RX_MPS2NCSI_CNT", 0x1127c, 0 },
+	{ "MPS_RX_MAX_TNL_HDR_LEN", 0x11280, 0 },
+		{ "MODE", 9, 1 },
+		{ "LEN", 0, 9 },
+	{ "MPS_RX_PAUSE_DA_H", 0x11284, 0 },
+	{ "MPS_RX_PAUSE_DA_L", 0x11288, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_MAC0", 0x1128c, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_MAC0", 0x11290, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_MAC0", 0x11294, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_MAC0", 0x11298, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_MAC1", 0x1129c, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_MAC1", 0x112a0, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_MAC1", 0x112a4, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_MAC1", 0x112a8, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_MAC2", 0x11408, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_MAC2", 0x1140c, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_MAC2", 0x11410, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_MAC2", 0x11414, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_MAC3", 0x11418, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_MAC3", 0x1141c, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_MAC3", 0x11420, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_MAC3", 0x11424, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_LPBK0", 0x112ac, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_LPBK0", 0x112b0, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_LPBK0", 0x112b4, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK0", 0x112b8, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_LPBK1", 0x112bc, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_LPBK1", 0x112c0, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_LPBK1", 0x112c4, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK1", 0x112c8, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_LPBK2", 0x11428, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_LPBK2", 0x1142c, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_LPBK2", 0x11430, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK2", 0x11434, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_LPBK3", 0x11438, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_LPBK3", 0x1143c, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_LPBK3", 0x11440, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_LPBK3", 0x11444, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_TO_TP0", 0x112cc, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_TO_TP0", 0x112d0, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_TO_TP0", 0x112d4, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP0", 0x112d8, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_TO_TP1", 0x112dc, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_TO_TP1", 0x112e0, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_TO_TP1", 0x112e4, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP1", 0x112e8, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_TO_TP2", 0x11448, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_TO_TP2", 0x1144c, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_TO_TP2", 0x11450, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP2", 0x11454, 0 },
+	{ "MPS_RX_CNT_NVGRE_PKT_TO_TP3", 0x11458, 0 },
+	{ "MPS_RX_CNT_VXLAN_PKT_TO_TP3", 0x1145c, 0 },
+	{ "MPS_RX_CNT_GENEVE_PKT_TO_TP3", 0x11460, 0 },
+	{ "MPS_RX_CNT_TNL_ERR_PKT_TO_TP3", 0x11464, 0 },
+	{ "MPS_RX_ESP", 0x112ec, 0 },
+		{ "PROT_TYPE_EN", 8, 1 },
+		{ "PROT_TYPE", 0, 8 },
+	{ "MPS_EN_LPBK_BLK_SNDR", 0x112f0, 0 },
+		{ "EN_CH3", 3, 1 },
+		{ "EN_CH2", 2, 1 },
+		{ "EN_CH1", 1, 1 },
+		{ "EN_CH0", 0, 1 },
+	{ "MPS_CLS_DROP_DMAC0_L", 0x12070, 0 },
+	{ "MPS_CLS_DROP_DMAC0_H", 0x12074, 0 },
+	{ "MPS_CLS_DROP_DMAC1_L", 0x12078, 0 },
+	{ "MPS_CLS_DROP_DMAC1_H", 0x1207c, 0 },
+	{ "MPS_CLS_DROP_DMAC2_L", 0x12080, 0 },
+	{ "MPS_CLS_DROP_DMAC2_H", 0x12084, 0 },
+	{ "MPS_CLS_DROP_DMAC3_L", 0x12088, 0 },
+	{ "MPS_CLS_DROP_DMAC3_H", 0x1208c, 0 },
+	{ "MPS_CLS_DROP_DMAC4_L", 0x12090, 0 },
+	{ "MPS_CLS_DROP_DMAC4_H", 0x12094, 0 },
+	{ "MPS_CLS_DROP_DMAC5_L", 0x12098, 0 },
+	{ "MPS_CLS_DROP_DMAC5_H", 0x1209c, 0 },
+	{ "MPS_CLS_DROP_DMAC6_L", 0x120a0, 0 },
+	{ "MPS_CLS_DROP_DMAC6_H", 0x120a4, 0 },
+	{ "MPS_CLS_DROP_DMAC7_L", 0x120a8, 0 },
+	{ "MPS_CLS_DROP_DMAC7_H", 0x120ac, 0 },
+	{ "MPS_CLS_DROP_DMAC8_L", 0x120b0, 0 },
+	{ "MPS_CLS_DROP_DMAC8_H", 0x120b4, 0 },
+	{ "MPS_CLS_DROP_DMAC9_L", 0x120b8, 0 },
+	{ "MPS_CLS_DROP_DMAC9_H", 0x120bc, 0 },
+	{ "MPS_CLS_DROP_DMAC10_L", 0x120c0, 0 },
+	{ "MPS_CLS_DROP_DMAC10_H", 0x120c4, 0 },
+	{ "MPS_CLS_DROP_DMAC11_L", 0x120c8, 0 },
+	{ "MPS_CLS_DROP_DMAC11_H", 0x120cc, 0 },
+	{ "MPS_CLS_DROP_DMAC12_L", 0x120d0, 0 },
+	{ "MPS_CLS_DROP_DMAC12_H", 0x120d4, 0 },
+	{ "MPS_CLS_DROP_DMAC13_L", 0x120d8, 0 },
+	{ "MPS_CLS_DROP_DMAC13_H", 0x120dc, 0 },
+	{ "MPS_CLS_DROP_DMAC14_L", 0x120e0, 0 },
+	{ "MPS_CLS_DROP_DMAC14_H", 0x120e4, 0 },
+	{ "MPS_CLS_DROP_DMAC15_L", 0x120e8, 0 },
+	{ "MPS_CLS_DROP_DMAC15_H", 0x120ec, 0 },
+	{ "MPS_RX_TRANS_ENCAP_FLTR_CTL", 0x12100, 0 },
+		{ "TIMEOUT_FLT_CLR_EN", 8, 1 },
+		{ "FLTR_TIMOUT_VAL", 0, 8 },
+	{ "MPS_RX_BG0_IPSEC_CNT", 0x12294, 0 },
+	{ "MPS_RX_BG1_IPSEC_CNT", 0x12298, 0 },
+	{ "MPS_RX_BG2_IPSEC_CNT", 0x1229c, 0 },
+	{ "MPS_RX_BG3_IPSEC_CNT", 0x122a0, 0 },
+	{ "MPS_RX_MEM_FIFO_CONFIG0", 0x122a4, 0 },
+		{ "FIFO_CONFIG2", 16, 16 },
+		{ "FIFO_CONFIG1", 0, 16 },
+	{ "MPS_RX_MEM_FIFO_CONFIG1", 0x122a8, 0 },
+	{ "MPS_LPBK_MEM_FIFO_CONFIG0", 0x122ac, 0 },
+		{ "FIFO_CONFIG2", 16, 16 },
+		{ "FIFO_CONFIG1", 0, 16 },
+	{ "MPS_LPBK_MEM_FIFO_CONFIG1", 0x122b0, 0 },
+	{ "MPS_BG_PAUSE_CTL", 0x122c4, 0 },
+		{ "bg0_pause_en", 3, 1 },
+		{ "bg1_pause_en", 2, 1 },
+		{ "bg2_pause_en", 1, 1 },
+		{ "bg3_pause_en", 0, 1 },
+	{ "MPS_PORT_RX_CTL", 0x30100, 0 },
+		{ "TRANS_ENCAP_EN", 30, 1 },
+		{ "CRYPTO_DUMMY_PKT_CHK_EN", 29, 1 },
+		{ "PASS_HPROM", 28, 1 },
+		{ "PASS_PROM", 27, 1 },
+		{ "ENCAP_ONLY_IF_OUTER_HIT", 26, 1 },
+		{ "HASH_PRIO_SEL_LPBK", 25, 1 },
+		{ "HASH_PRIO_SEL_MAC", 24, 1 },
+		{ "HASH_EN_LPBK", 23, 1 },
+		{ "HASH_EN_MAC", 22, 1 },
+		{ "PTP_FWD_UP", 21, 1 },
+		{ "NO_RPLCT_M", 20, 1 },
+		{ "RPLCT_SEL_L", 18, 2 },
+		{ "FLTR_VLAN_SEL", 17, 1 },
+		{ "PRIO_VLAN_SEL", 16, 1 },
+		{ "CHK_8023_LEN_M", 15, 1 },
+		{ "CHK_8023_LEN_L", 14, 1 },
+		{ "NIV_DROP", 13, 1 },
+		{ "NOV_DROP", 12, 1 },
+		{ "CLS_PRT", 11, 1 },
+		{ "RX_QFC_EN", 10, 1 },
+		{ "QFC_FWD_UP", 9, 1 },
+		{ "PPP_FWD_UP", 8, 1 },
+		{ "PAUSE_FWD_UP", 7, 1 },
+		{ "LPBK_BP", 6, 1 },
+		{ "PASS_NO_MATCH", 5, 1 },
+		{ "IVLAN_EN", 4, 1 },
+		{ "OVLAN_EN3", 3, 1 },
+		{ "OVLAN_EN2", 2, 1 },
+		{ "OVLAN_EN1", 1, 1 },
+		{ "OVLAN_EN0", 0, 1 },
+	{ "MPS_PORT_RX_MTU", 0x30104, 0 },
+	{ "MPS_PORT_RX_PF_MAP", 0x30108, 0 },
+	{ "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 },
+	{ "MPS_PORT_RX_VF_MAP1", 0x30110, 0 },
+	{ "MPS_PORT_RX_VF_MAP2", 0x30114, 0 },
+	{ "MPS_PORT_RX_VF_MAP3", 0x30118, 0 },
+	{ "MPS_PORT_RX_VF_MAP4", 0x30150, 0 },
+	{ "MPS_PORT_RX_VF_MAP5", 0x30154, 0 },
+	{ "MPS_PORT_RX_VF_MAP6", 0x30158, 0 },
+	{ "MPS_PORT_RX_VF_MAP7", 0x3015c, 0 },
+	{ "MPS_PORT_RX_IVLAN", 0x3011c, 0 },
+	{ "MPS_PORT_RX_OVLAN0", 0x30120, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN1", 0x30124, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN2", 0x30128, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN3", 0x3012c, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_RSS_HASH", 0x30130, 0 },
+	{ "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_INT_RSS_HASH", 0x30170, 0 },
+	{ "MPS_PORT_RX_INT_RSS_CONTROL", 0x30174, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_CTL1", 0x30138, 0 },
+		{ "FIXED_PFVF_MAC", 14, 1 },
+		{ "FIXED_PFVF_LPBK", 13, 1 },
+		{ "FIXED_PFVF_LPBK_OV", 12, 1 },
+		{ "FIXED_PF", 9, 3 },
+		{ "FIXED_VF_VLD", 8, 1 },
+		{ "FIXED_VF", 0, 8 },
+	{ "MPS_PORT_RX_SPARE", 0x3013c, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_TS_VLD", 0x30148, 0 },
+	{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3014c, 0 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x30160, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "non_runt_frame", 10, 1 },
+		{ "Inner_VLAN_VLD", 9, 1 },
+		{ "Err_IP_Payload_Len", 8, 1 },
+		{ "Err_UDP_Payload_Len", 7, 1 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x30164, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "Inner_VLAN_VLD", 10, 1 },
+		{ "Err_IP_Payload_Len", 9, 1 },
+		{ "Err_UDP_Payload_Len", 8, 1 },
+	{ "MPS_PORT_RX_REPL_VECT_SEL", 0x30168, 0 },
+		{ "DIS_REPL_VECT_SEL", 4, 1 },
+		{ "REPL_VECT_SEL", 0, 4 },
+	{ "MPS_PORT_MAC_RX_DROP_EN_PP", 0x3016c, 0 },
+	{ "MPS_PORT_RX_CNT_DBG_CTL", 0x30178, 0 },
+	{ "MPS_PORT_RX_CNT_DBG", 0x3017c, 0 },
+	{ "MPS_PORT_RX_CTL", 0x32100, 0 },
+		{ "TRANS_ENCAP_EN", 30, 1 },
+		{ "CRYPTO_DUMMY_PKT_CHK_EN", 29, 1 },
+		{ "PASS_HPROM", 28, 1 },
+		{ "PASS_PROM", 27, 1 },
+		{ "ENCAP_ONLY_IF_OUTER_HIT", 26, 1 },
+		{ "HASH_PRIO_SEL_LPBK", 25, 1 },
+		{ "HASH_PRIO_SEL_MAC", 24, 1 },
+		{ "HASH_EN_LPBK", 23, 1 },
+		{ "HASH_EN_MAC", 22, 1 },
+		{ "PTP_FWD_UP", 21, 1 },
+		{ "NO_RPLCT_M", 20, 1 },
+		{ "RPLCT_SEL_L", 18, 2 },
+		{ "FLTR_VLAN_SEL", 17, 1 },
+		{ "PRIO_VLAN_SEL", 16, 1 },
+		{ "CHK_8023_LEN_M", 15, 1 },
+		{ "CHK_8023_LEN_L", 14, 1 },
+		{ "NIV_DROP", 13, 1 },
+		{ "NOV_DROP", 12, 1 },
+		{ "CLS_PRT", 11, 1 },
+		{ "RX_QFC_EN", 10, 1 },
+		{ "QFC_FWD_UP", 9, 1 },
+		{ "PPP_FWD_UP", 8, 1 },
+		{ "PAUSE_FWD_UP", 7, 1 },
+		{ "LPBK_BP", 6, 1 },
+		{ "PASS_NO_MATCH", 5, 1 },
+		{ "IVLAN_EN", 4, 1 },
+		{ "OVLAN_EN3", 3, 1 },
+		{ "OVLAN_EN2", 2, 1 },
+		{ "OVLAN_EN1", 1, 1 },
+		{ "OVLAN_EN0", 0, 1 },
+	{ "MPS_PORT_RX_MTU", 0x32104, 0 },
+	{ "MPS_PORT_RX_PF_MAP", 0x32108, 0 },
+	{ "MPS_PORT_RX_VF_MAP0", 0x3210c, 0 },
+	{ "MPS_PORT_RX_VF_MAP1", 0x32110, 0 },
+	{ "MPS_PORT_RX_VF_MAP2", 0x32114, 0 },
+	{ "MPS_PORT_RX_VF_MAP3", 0x32118, 0 },
+	{ "MPS_PORT_RX_VF_MAP4", 0x32150, 0 },
+	{ "MPS_PORT_RX_VF_MAP5", 0x32154, 0 },
+	{ "MPS_PORT_RX_VF_MAP6", 0x32158, 0 },
+	{ "MPS_PORT_RX_VF_MAP7", 0x3215c, 0 },
+	{ "MPS_PORT_RX_IVLAN", 0x3211c, 0 },
+	{ "MPS_PORT_RX_OVLAN0", 0x32120, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN1", 0x32124, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN2", 0x32128, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN3", 0x3212c, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_RSS_HASH", 0x32130, 0 },
+	{ "MPS_PORT_RX_RSS_CONTROL", 0x32134, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_INT_RSS_HASH", 0x32170, 0 },
+	{ "MPS_PORT_RX_INT_RSS_CONTROL", 0x32174, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_CTL1", 0x32138, 0 },
+		{ "FIXED_PFVF_MAC", 14, 1 },
+		{ "FIXED_PFVF_LPBK", 13, 1 },
+		{ "FIXED_PFVF_LPBK_OV", 12, 1 },
+		{ "FIXED_PF", 9, 3 },
+		{ "FIXED_VF_VLD", 8, 1 },
+		{ "FIXED_VF", 0, 8 },
+	{ "MPS_PORT_RX_SPARE", 0x3213c, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_HASH", 0x32140, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x32144, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_TS_VLD", 0x32148, 0 },
+	{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3214c, 0 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x32160, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "non_runt_frame", 10, 1 },
+		{ "Inner_VLAN_VLD", 9, 1 },
+		{ "Err_IP_Payload_Len", 8, 1 },
+		{ "Err_UDP_Payload_Len", 7, 1 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x32164, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "Inner_VLAN_VLD", 10, 1 },
+		{ "Err_IP_Payload_Len", 9, 1 },
+		{ "Err_UDP_Payload_Len", 8, 1 },
+	{ "MPS_PORT_RX_REPL_VECT_SEL", 0x32168, 0 },
+		{ "DIS_REPL_VECT_SEL", 4, 1 },
+		{ "REPL_VECT_SEL", 0, 4 },
+	{ "MPS_PORT_MAC_RX_DROP_EN_PP", 0x3216c, 0 },
+	{ "MPS_PORT_RX_CNT_DBG_CTL", 0x32178, 0 },
+	{ "MPS_PORT_RX_CNT_DBG", 0x3217c, 0 },
+	{ "MPS_PORT_RX_CTL", 0x34100, 0 },
+		{ "TRANS_ENCAP_EN", 30, 1 },
+		{ "CRYPTO_DUMMY_PKT_CHK_EN", 29, 1 },
+		{ "PASS_HPROM", 28, 1 },
+		{ "PASS_PROM", 27, 1 },
+		{ "ENCAP_ONLY_IF_OUTER_HIT", 26, 1 },
+		{ "HASH_PRIO_SEL_LPBK", 25, 1 },
+		{ "HASH_PRIO_SEL_MAC", 24, 1 },
+		{ "HASH_EN_LPBK", 23, 1 },
+		{ "HASH_EN_MAC", 22, 1 },
+		{ "PTP_FWD_UP", 21, 1 },
+		{ "NO_RPLCT_M", 20, 1 },
+		{ "RPLCT_SEL_L", 18, 2 },
+		{ "FLTR_VLAN_SEL", 17, 1 },
+		{ "PRIO_VLAN_SEL", 16, 1 },
+		{ "CHK_8023_LEN_M", 15, 1 },
+		{ "CHK_8023_LEN_L", 14, 1 },
+		{ "NIV_DROP", 13, 1 },
+		{ "NOV_DROP", 12, 1 },
+		{ "CLS_PRT", 11, 1 },
+		{ "RX_QFC_EN", 10, 1 },
+		{ "QFC_FWD_UP", 9, 1 },
+		{ "PPP_FWD_UP", 8, 1 },
+		{ "PAUSE_FWD_UP", 7, 1 },
+		{ "LPBK_BP", 6, 1 },
+		{ "PASS_NO_MATCH", 5, 1 },
+		{ "IVLAN_EN", 4, 1 },
+		{ "OVLAN_EN3", 3, 1 },
+		{ "OVLAN_EN2", 2, 1 },
+		{ "OVLAN_EN1", 1, 1 },
+		{ "OVLAN_EN0", 0, 1 },
+	{ "MPS_PORT_RX_MTU", 0x34104, 0 },
+	{ "MPS_PORT_RX_PF_MAP", 0x34108, 0 },
+	{ "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 },
+	{ "MPS_PORT_RX_VF_MAP1", 0x34110, 0 },
+	{ "MPS_PORT_RX_VF_MAP2", 0x34114, 0 },
+	{ "MPS_PORT_RX_VF_MAP3", 0x34118, 0 },
+	{ "MPS_PORT_RX_VF_MAP4", 0x34150, 0 },
+	{ "MPS_PORT_RX_VF_MAP5", 0x34154, 0 },
+	{ "MPS_PORT_RX_VF_MAP6", 0x34158, 0 },
+	{ "MPS_PORT_RX_VF_MAP7", 0x3415c, 0 },
+	{ "MPS_PORT_RX_IVLAN", 0x3411c, 0 },
+	{ "MPS_PORT_RX_OVLAN0", 0x34120, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN1", 0x34124, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN2", 0x34128, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN3", 0x3412c, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_RSS_HASH", 0x34130, 0 },
+	{ "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_INT_RSS_HASH", 0x34170, 0 },
+	{ "MPS_PORT_RX_INT_RSS_CONTROL", 0x34174, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_CTL1", 0x34138, 0 },
+		{ "FIXED_PFVF_MAC", 14, 1 },
+		{ "FIXED_PFVF_LPBK", 13, 1 },
+		{ "FIXED_PFVF_LPBK_OV", 12, 1 },
+		{ "FIXED_PF", 9, 3 },
+		{ "FIXED_VF_VLD", 8, 1 },
+		{ "FIXED_VF", 0, 8 },
+	{ "MPS_PORT_RX_SPARE", 0x3413c, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_TS_VLD", 0x34148, 0 },
+	{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3414c, 0 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x34160, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "non_runt_frame", 10, 1 },
+		{ "Inner_VLAN_VLD", 9, 1 },
+		{ "Err_IP_Payload_Len", 8, 1 },
+		{ "Err_UDP_Payload_Len", 7, 1 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x34164, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "Inner_VLAN_VLD", 10, 1 },
+		{ "Err_IP_Payload_Len", 9, 1 },
+		{ "Err_UDP_Payload_Len", 8, 1 },
+	{ "MPS_PORT_RX_REPL_VECT_SEL", 0x34168, 0 },
+		{ "DIS_REPL_VECT_SEL", 4, 1 },
+		{ "REPL_VECT_SEL", 0, 4 },
+	{ "MPS_PORT_MAC_RX_DROP_EN_PP", 0x3416c, 0 },
+	{ "MPS_PORT_RX_CNT_DBG_CTL", 0x34178, 0 },
+	{ "MPS_PORT_RX_CNT_DBG", 0x3417c, 0 },
+	{ "MPS_PORT_RX_CTL", 0x36100, 0 },
+		{ "TRANS_ENCAP_EN", 30, 1 },
+		{ "CRYPTO_DUMMY_PKT_CHK_EN", 29, 1 },
+		{ "PASS_HPROM", 28, 1 },
+		{ "PASS_PROM", 27, 1 },
+		{ "ENCAP_ONLY_IF_OUTER_HIT", 26, 1 },
+		{ "HASH_PRIO_SEL_LPBK", 25, 1 },
+		{ "HASH_PRIO_SEL_MAC", 24, 1 },
+		{ "HASH_EN_LPBK", 23, 1 },
+		{ "HASH_EN_MAC", 22, 1 },
+		{ "PTP_FWD_UP", 21, 1 },
+		{ "NO_RPLCT_M", 20, 1 },
+		{ "RPLCT_SEL_L", 18, 2 },
+		{ "FLTR_VLAN_SEL", 17, 1 },
+		{ "PRIO_VLAN_SEL", 16, 1 },
+		{ "CHK_8023_LEN_M", 15, 1 },
+		{ "CHK_8023_LEN_L", 14, 1 },
+		{ "NIV_DROP", 13, 1 },
+		{ "NOV_DROP", 12, 1 },
+		{ "CLS_PRT", 11, 1 },
+		{ "RX_QFC_EN", 10, 1 },
+		{ "QFC_FWD_UP", 9, 1 },
+		{ "PPP_FWD_UP", 8, 1 },
+		{ "PAUSE_FWD_UP", 7, 1 },
+		{ "LPBK_BP", 6, 1 },
+		{ "PASS_NO_MATCH", 5, 1 },
+		{ "IVLAN_EN", 4, 1 },
+		{ "OVLAN_EN3", 3, 1 },
+		{ "OVLAN_EN2", 2, 1 },
+		{ "OVLAN_EN1", 1, 1 },
+		{ "OVLAN_EN0", 0, 1 },
+	{ "MPS_PORT_RX_MTU", 0x36104, 0 },
+	{ "MPS_PORT_RX_PF_MAP", 0x36108, 0 },
+	{ "MPS_PORT_RX_VF_MAP0", 0x3610c, 0 },
+	{ "MPS_PORT_RX_VF_MAP1", 0x36110, 0 },
+	{ "MPS_PORT_RX_VF_MAP2", 0x36114, 0 },
+	{ "MPS_PORT_RX_VF_MAP3", 0x36118, 0 },
+	{ "MPS_PORT_RX_VF_MAP4", 0x36150, 0 },
+	{ "MPS_PORT_RX_VF_MAP5", 0x36154, 0 },
+	{ "MPS_PORT_RX_VF_MAP6", 0x36158, 0 },
+	{ "MPS_PORT_RX_VF_MAP7", 0x3615c, 0 },
+	{ "MPS_PORT_RX_IVLAN", 0x3611c, 0 },
+	{ "MPS_PORT_RX_OVLAN0", 0x36120, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN1", 0x36124, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN2", 0x36128, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_OVLAN3", 0x3612c, 0 },
+		{ "OVLAN_MASK", 16, 16 },
+		{ "OVLAN_ETYPE", 0, 16 },
+	{ "MPS_PORT_RX_RSS_HASH", 0x36130, 0 },
+	{ "MPS_PORT_RX_RSS_CONTROL", 0x36134, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_INT_RSS_HASH", 0x36170, 0 },
+	{ "MPS_PORT_RX_INT_RSS_CONTROL", 0x36174, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_CTL1", 0x36138, 0 },
+		{ "FIXED_PFVF_MAC", 14, 1 },
+		{ "FIXED_PFVF_LPBK", 13, 1 },
+		{ "FIXED_PFVF_LPBK_OV", 12, 1 },
+		{ "FIXED_PF", 9, 3 },
+		{ "FIXED_VF_VLD", 8, 1 },
+		{ "FIXED_VF", 0, 8 },
+	{ "MPS_PORT_RX_SPARE", 0x3613c, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_HASH", 0x36140, 0 },
+	{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x36144, 0 },
+		{ "RSS_CTRL", 16, 8 },
+		{ "QUE_NUM", 0, 16 },
+	{ "MPS_PORT_RX_TS_VLD", 0x36148, 0 },
+	{ "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3614c, 0 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x36160, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "non_runt_frame", 10, 1 },
+		{ "Inner_VLAN_VLD", 9, 1 },
+		{ "Err_IP_Payload_Len", 8, 1 },
+		{ "Err_UDP_Payload_Len", 7, 1 },
+	{ "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x36164, 0 },
+		{ "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+		{ "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+		{ "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+		{ "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+		{ "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+		{ "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+		{ "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+		{ "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+		{ "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+		{ "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+		{ "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+		{ "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+		{ "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+		{ "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+		{ "Err_Tnl_Hdr_Len", 11, 1 },
+		{ "Inner_VLAN_VLD", 10, 1 },
+		{ "Err_IP_Payload_Len", 9, 1 },
+		{ "Err_UDP_Payload_Len", 8, 1 },
+	{ "MPS_PORT_RX_REPL_VECT_SEL", 0x36168, 0 },
+		{ "DIS_REPL_VECT_SEL", 4, 1 },
+		{ "REPL_VECT_SEL", 0, 4 },
+	{ "MPS_PORT_MAC_RX_DROP_EN_PP", 0x3616c, 0 },
+	{ "MPS_PORT_RX_CNT_DBG_CTL", 0x36178, 0 },
+	{ "MPS_PORT_RX_CNT_DBG", 0x3617c, 0 },
+	{ "MPS_TX_PRTY_SEL", 0x9400, 0 },
+		{ "Ch4_Prty", 16, 3 },
+		{ "Ch3_Prty", 13, 3 },
+		{ "Ch2_Prty", 10, 3 },
+		{ "Ch1_Prty", 7, 3 },
+		{ "Ch0_Prty", 4, 3 },
+		{ "TP_Source", 2, 2 },
+		{ "NCSI_Source", 0, 2 },
+	{ "MPS_TX_INT_ENABLE", 0x9404, 0 },
+		{ "PortErr", 28, 1 },
+		{ "FRMERR", 27, 1 },
+		{ "SECNTERR", 26, 1 },
+		{ "BUBBLE", 25, 1 },
+		{ "TxTokenFifo", 15, 10 },
+		{ "PERR_TP2MPS_TFIFO", 13, 2 },
+		{ "TxDescFifo", 9, 4 },
+		{ "TxDataFifo", 5, 4 },
+		{ "Ncsi", 4, 1 },
+		{ "TP", 0, 4 },
+	{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
+		{ "PortErr", 28, 1 },
+		{ "FRMERR", 27, 1 },
+		{ "SECNTERR", 26, 1 },
+		{ "BUBBLE", 25, 1 },
+		{ "TxTokenFifo", 15, 10 },
+		{ "PERR_TP2MPS_TFIFO", 13, 2 },
+		{ "TxDescFifo", 9, 4 },
+		{ "TxDataFifo", 5, 4 },
+		{ "Ncsi", 4, 1 },
+		{ "TP", 0, 4 },
+	{ "MPS_TX_NCSI2MPS_CNT", 0x940c, 0 },
+	{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
+		{ "PortErrInt", 28, 1 },
+		{ "FramingErrInt", 27, 1 },
+		{ "SeCntErrInt", 26, 1 },
+		{ "BubbleErrInt", 25, 1 },
+		{ "TxTokenFifo", 15, 10 },
+		{ "PERR_TP2MPS_TFIFO", 13, 2 },
+		{ "TxDescFifo", 9, 4 },
+		{ "TxDataFifo", 5, 4 },
+		{ "Ncsi", 4, 1 },
+		{ "TP", 0, 4 },
+	{ "MPS_TX_PERR_INJECT", 0x9414, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MPS_TX_PORT_ERR", 0x9430, 0 },
+		{ "Lpbkpt3", 7, 1 },
+		{ "Lpbkpt2", 6, 1 },
+		{ "Lpbkpt1", 5, 1 },
+		{ "Lpbkpt0", 4, 1 },
+		{ "pt3", 3, 1 },
+		{ "pt2", 2, 1 },
+		{ "pt1", 1, 1 },
+		{ "pt0", 0, 1 },
+	{ "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
+		{ "BpEn", 1, 1 },
+		{ "DropEn", 0, 1 },
+	{ "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
+		{ "BpEn", 1, 1 },
+		{ "DropEn", 0, 1 },
+	{ "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
+		{ "BpEn", 1, 1 },
+		{ "DropEn", 0, 1 },
+	{ "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
+		{ "BpEn", 1, 1 },
+		{ "DropEn", 0, 1 },
+	{ "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
+	{ "MPS_TX_PAD_CTL", 0x945c, 0 },
+		{ "LpbkPadEnPt3", 7, 1 },
+		{ "LpbkPadEnPt2", 6, 1 },
+		{ "LpbkPadEnPt1", 5, 1 },
+		{ "LpbkPadEnPt0", 4, 1 },
+		{ "MacPadEnPt3", 3, 1 },
+		{ "MacPadEnPt2", 2, 1 },
+		{ "MacPadEnPt1", 1, 1 },
+		{ "MacPadEnPt0", 0, 1 },
+	{ "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 },
+		{ "TP2MPS_Ch3", 24, 8 },
+		{ "TP2MPS_Ch2", 16, 8 },
+		{ "TP2MPS_Ch1", 8, 8 },
+		{ "TP2MPS_Ch0", 0, 8 },
+	{ "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 },
+	{ "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 },
+		{ "PFNOVFDROP", 5, 1 },
+		{ "NCSI_Ch4_CLR", 4, 1 },
+		{ "TP2MPS_Ch3_CLR", 3, 1 },
+		{ "TP2MPS_Ch2_CLR", 2, 1 },
+		{ "TP2MPS_Ch1_CLR", 1, 1 },
+		{ "TP2MPS_Ch0_CLR", 0, 1 },
+	{ "MPS_TX_CGEN", 0x946c, 0 },
+		{ "TxOutLpbk3_CGEN", 31, 1 },
+		{ "TxOutLpbk2_CGEN", 30, 1 },
+		{ "TxOutLpbk1_CGEN", 29, 1 },
+		{ "TxOutLpbk0_CGEN", 28, 1 },
+		{ "TxOutMAC3_CGEN", 27, 1 },
+		{ "TxOutMAC2_CGEN", 26, 1 },
+		{ "TxOutMAC1_CGEN", 25, 1 },
+		{ "TxOutMAC0_CGEN", 24, 1 },
+		{ "TxSchLpbk3_CGEN", 23, 1 },
+		{ "TxSchLpbk2_CGEN", 22, 1 },
+		{ "TxSchLpbk1_CGEN", 21, 1 },
+		{ "TxSchLpbk0_CGEN", 20, 1 },
+		{ "TxSchMAC3_CGEN", 19, 1 },
+		{ "TxSchMAC2_CGEN", 18, 1 },
+		{ "TxSchMAC1_CGEN", 17, 1 },
+		{ "TxSchMAC0_CGEN", 16, 1 },
+		{ "TxInCh4_CGEN", 15, 1 },
+		{ "TxInCh3_CGEN", 14, 1 },
+		{ "TxInCh2_CGEN", 13, 1 },
+		{ "TxInCh1_CGEN", 12, 1 },
+		{ "TxInCh0_CGEN", 11, 1 },
+	{ "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 },
+		{ "TxOutLpbk3_CGEN", 31, 1 },
+		{ "TxOutLpbk2_CGEN", 30, 1 },
+		{ "TxOutLpbk1_CGEN", 29, 1 },
+		{ "TxOutLpbk0_CGEN", 28, 1 },
+		{ "TxOutMAC3_CGEN", 27, 1 },
+		{ "TxOutMAC2_CGEN", 26, 1 },
+		{ "TxOutMAC1_CGEN", 25, 1 },
+		{ "TxOutMAC0_CGEN", 24, 1 },
+		{ "TxSchLpbk3_CGEN", 23, 1 },
+		{ "TxSchLpbk2_CGEN", 22, 1 },
+		{ "TxSchLpbk1_CGEN", 21, 1 },
+		{ "TxSchLpbk0_CGEN", 20, 1 },
+		{ "TxSchMAC3_CGEN", 19, 1 },
+		{ "TxSchMAC2_CGEN", 18, 1 },
+		{ "TxSchMAC1_CGEN", 17, 1 },
+		{ "TxSchMAC0_CGEN", 16, 1 },
+		{ "TxInCh4_CGEN", 15, 1 },
+		{ "TxInCh3_CGEN", 14, 1 },
+		{ "TxInCh2_CGEN", 13, 1 },
+		{ "TxInCh1_CGEN", 12, 1 },
+		{ "TxInCh0_CGEN", 11, 1 },
+	{ "MPS_TX2RX_CH_MAP", 0x9474, 0 },
+		{ "EnableLbk_Ch3", 3, 1 },
+		{ "EnableLbk_Ch2", 2, 1 },
+		{ "EnableLbk_Ch1", 1, 1 },
+		{ "EnableLbk_Ch0", 0, 1 },
+	{ "MPS_TX_DBG_CNT_CTL", 0x9478, 0 },
+	{ "MPS_TX_DBG_CNT", 0x947c, 0 },
+	{ "MPS_TX_INT2_ENABLE", 0x9498, 0 },
+	{ "MPS_TX_INT2_CAUSE", 0x949c, 0 },
+	{ "MPS_TX_PERR2_ENABLE", 0x94a0, 0 },
+	{ "MPS_TX_INT3_ENABLE", 0x94a4, 0 },
+	{ "MPS_TX_INT3_CAUSE", 0x94a8, 0 },
+	{ "MPS_TX_PERR3_ENABLE", 0x94ac, 0 },
+	{ "MPS_TX_INT4_ENABLE", 0x94b0, 0 },
+	{ "MPS_TX_INT4_CAUSE", 0x94b4, 0 },
+	{ "MPS_TX_PERR4_ENABLE", 0x94b8, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1e2e4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1e6e4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1eae4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1eee4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1f2e4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1f6e4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1fae4, 0 },
+	{ "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
+		{ "ProtocolID", 16, 16 },
+		{ "Priority", 13, 3 },
+		{ "CFI", 12, 1 },
+		{ "Tag", 0, 12 },
+	{ "MPS_PF_TX_MAC_DROP_PP", 0x1fee4, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 },
+	{ "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 },
+		{ "OUT_TH", 22, 8 },
+		{ "IN_TH", 14, 8 },
+		{ "FifoTh", 5, 9 },
+		{ "FifoEn", 4, 1 },
+		{ "MaxPktCnt", 0, 4 },
+	{ "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 },
+	{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 },
+		{ "off_pending", 8, 8 },
+		{ "on_pending", 0, 8 },
+	{ "MPS_PORT_TX_MAC_DROP_PP", 0x301d4, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_PP", 0x301d8, 0 },
+	{ "MPS_PORT_TX_MAC_DROP_CNT", 0x301dc, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_CNT", 0x301e0, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x32190, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x32194, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x32198, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3219c, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x321a0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x321a8, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x321ac, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x321b0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x321b4, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x321b8, 0 },
+	{ "MPS_PORT_TX_FIFO_CTL", 0x321c4, 0 },
+		{ "OUT_TH", 22, 8 },
+		{ "IN_TH", 14, 8 },
+		{ "FifoTh", 5, 9 },
+		{ "FifoEn", 4, 1 },
+		{ "MaxPktCnt", 0, 4 },
+	{ "MPS_PORT_FPGA_PAUSE_CTL", 0x321c8, 0 },
+	{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x321d0, 0 },
+		{ "off_pending", 8, 8 },
+		{ "on_pending", 0, 8 },
+	{ "MPS_PORT_TX_MAC_DROP_PP", 0x321d4, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_PP", 0x321d8, 0 },
+	{ "MPS_PORT_TX_MAC_DROP_CNT", 0x321dc, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_CNT", 0x321e0, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 },
+	{ "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 },
+		{ "OUT_TH", 22, 8 },
+		{ "IN_TH", 14, 8 },
+		{ "FifoTh", 5, 9 },
+		{ "FifoEn", 4, 1 },
+		{ "MaxPktCnt", 0, 4 },
+	{ "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 },
+	{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 },
+		{ "off_pending", 8, 8 },
+		{ "on_pending", 0, 8 },
+	{ "MPS_PORT_TX_MAC_DROP_PP", 0x341d4, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_PP", 0x341d8, 0 },
+	{ "MPS_PORT_TX_MAC_DROP_CNT", 0x341dc, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_CNT", 0x341e0, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x36190, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x36194, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x36198, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3619c, 0 },
+	{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x361a0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x361a8, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x361ac, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x361b0, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x361b4, 0 },
+	{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x361b8, 0 },
+	{ "MPS_PORT_TX_FIFO_CTL", 0x361c4, 0 },
+		{ "OUT_TH", 22, 8 },
+		{ "IN_TH", 14, 8 },
+		{ "FifoTh", 5, 9 },
+		{ "FifoEn", 4, 1 },
+		{ "MaxPktCnt", 0, 4 },
+	{ "MPS_PORT_FPGA_PAUSE_CTL", 0x361c8, 0 },
+	{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x361d0, 0 },
+		{ "off_pending", 8, 8 },
+		{ "on_pending", 0, 8 },
+	{ "MPS_PORT_TX_MAC_DROP_PP", 0x361d4, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_PP", 0x361d8, 0 },
+	{ "MPS_PORT_TX_MAC_DROP_CNT", 0x361dc, 0 },
+	{ "MPS_PORT_TX_LPBK_DROP_CNT", 0x361e0, 0 },
+	{ "MPS_TRC_CFG", 0x9800, 0 },
+		{ "TrcMultiRSSFilter", 5, 1 },
+		{ "TrcFifoEmpty", 4, 1 },
+		{ "TrcIgnoreDropInput", 3, 1 },
+		{ "TrcKeepDuplicates", 2, 1 },
+		{ "TrcEn", 1, 1 },
+		{ "TrcMultiFilter", 0, 1 },
+	{ "MPS_TRC_FILTER0_RSS_HASH", 0xa3f0, 0 },
+	{ "MPS_TRC_FILTER0_RSS_CONTROL", 0xa3f4, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER1_RSS_HASH", 0xa3f8, 0 },
+	{ "MPS_TRC_FILTER1_RSS_CONTROL", 0xa3fc, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER2_RSS_HASH", 0xa400, 0 },
+	{ "MPS_TRC_FILTER2_RSS_CONTROL", 0xa404, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER3_RSS_HASH", 0xa408, 0 },
+	{ "MPS_TRC_FILTER3_RSS_CONTROL", 0xa40c, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER4_RSS_HASH", 0xa410, 0 },
+	{ "MPS_TRC_FILTER4_RSS_CONTROL", 0xa414, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER5_RSS_HASH", 0xa418, 0 },
+	{ "MPS_TRC_FILTER5_RSS_CONTROL", 0xa41c, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER6_RSS_HASH", 0xa420, 0 },
+	{ "MPS_TRC_FILTER6_RSS_CONTROL", 0xa424, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_FILTER7_RSS_HASH", 0xa428, 0 },
+	{ "MPS_TRC_FILTER7_RSS_CONTROL", 0xa42c, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_RSS_HASH", 0xa430, 0 },
+	{ "MPS_TRC_RSS_CONTROL", 0xa434, 0 },
+		{ "RssControl", 16, 8 },
+		{ "QueueNumber", 0, 16 },
+	{ "MPS_TRC_VF_OFF_FILTER_0", 0xa438, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_1", 0xa43c, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_2", 0xa440, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_3", 0xa444, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_4", 0xa448, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_5", 0xa44c, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_6", 0xa450, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_VF_OFF_FILTER_7", 0xa454, 0 },
+		{ "TrcMPS2TP_MacOnly", 22, 1 },
+		{ "TrcAllMPS2TP", 21, 1 },
+		{ "TrcAllTP2MPS", 20, 1 },
+		{ "TrcAllVf", 19, 1 },
+		{ "OffEn", 18, 1 },
+		{ "VfFiltEn", 17, 1 },
+		{ "VfFiltMask", 9, 8 },
+		{ "VfFiltValid", 8, 1 },
+		{ "VfFiltData", 0, 8 },
+	{ "MPS_TRC_CGEN", 0xa458, 0 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa460, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa464, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa468, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa46c, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa470, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa474, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa478, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_A", 0xa47c, 0 },
+		{ "TfInsertActLen", 27, 1 },
+		{ "TfInsertTimer", 26, 1 },
+		{ "TfInvertMatch", 25, 1 },
+		{ "TfPktTooLarge", 24, 1 },
+		{ "TfEn", 23, 1 },
+		{ "TfPort", 18, 5 },
+		{ "TfDrop", 17, 1 },
+		{ "TfSopEopErr", 16, 1 },
+		{ "TfLength", 8, 5 },
+		{ "TfOffset", 0, 5 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa480, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa484, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa488, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa48c, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa490, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa494, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa498, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_MATCH_CTL_B", 0xa49c, 0 },
+		{ "TfMinPktSize", 16, 9 },
+		{ "TfCaptureMax", 0, 14 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4a0, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4a4, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4a8, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4ac, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4b0, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4b4, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4b8, 0 },
+	{ "MPS_TRC_FILTER_RUNT_CTL", 0xa4bc, 0 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4c0, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4c4, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4c8, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4cc, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4d0, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4d4, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4d8, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_FILTER_DROP", 0xa4dc, 0 },
+		{ "TfDropInpCount", 16, 16 },
+		{ "TfDropBufferCount", 0, 16 },
+	{ "MPS_TRC_PERR_INJECT", 0x9804, 0 },
+		{ "MemSel", 1, 4 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
+		{ "MiscPerr", 16, 1 },
+		{ "PktFifo", 8, 8 },
+		{ "FiltMem", 0, 8 },
+	{ "MPS_TRC_INT_ENABLE", 0xa4e0, 0 },
+		{ "PLErrEnb", 17, 1 },
+		{ "MiscPerr", 16, 1 },
+		{ "PktFifo", 8, 8 },
+		{ "FiltMem", 0, 8 },
+	{ "MPS_TRC_INT_CAUSE", 0xa4e4, 0 },
+		{ "PLErrEnb", 17, 1 },
+		{ "MiscPerr", 16, 1 },
+		{ "PktFifo", 8, 8 },
+		{ "FiltMem", 0, 8 },
+	{ "MPS_TRC_PERR_ENABLE2", 0xa4f0, 0 },
+		{ "trc_tf_ecc", 24, 8 },
+		{ "mps2mac_conv_trc_cerr", 22, 2 },
+		{ "mps2mac_conv_trc", 18, 4 },
+		{ "TF0_perr_1", 17, 1 },
+		{ "TF1_perr_1", 16, 1 },
+		{ "TF2_perr_1", 15, 1 },
+		{ "TF3_perr_1", 14, 1 },
+		{ "TF4_perr_1", 13, 1 },
+		{ "TF0_perr_0", 12, 1 },
+		{ "TF1_perr_0", 11, 1 },
+		{ "TF2_perr_0", 10, 1 },
+		{ "TF3_perr_0", 9, 1 },
+		{ "TF4_perr_0", 8, 1 },
+		{ "Perr_tf_in_ctl", 0, 8 },
+	{ "MPS_TRC_INT_ENABLE2", 0xa4f4, 0 },
+		{ "trc_tf_ecc", 24, 8 },
+		{ "mps2mac_conv_trc_cerr", 22, 2 },
+		{ "mps2mac_conv_trc", 18, 4 },
+		{ "TF0_perr_1", 17, 1 },
+		{ "TF1_perr_1", 16, 1 },
+		{ "TF2_perr_1", 15, 1 },
+		{ "TF3_perr_1", 14, 1 },
+		{ "TF4_perr_1", 13, 1 },
+		{ "TF0_perr_0", 12, 1 },
+		{ "TF1_perr_0", 11, 1 },
+		{ "TF2_perr_0", 10, 1 },
+		{ "TF3_perr_0", 9, 1 },
+		{ "TF4_perr_0", 8, 1 },
+		{ "Perr_tf_in_ctl", 0, 8 },
+	{ "MPS_TRC_INT_CAUSE2", 0xa4f8, 0 },
+		{ "trc_tf_ecc", 22, 8 },
+		{ "mps2mac_conv_trc", 18, 4 },
+		{ "TF0_perr_1", 17, 1 },
+		{ "TF1_perr_1", 16, 1 },
+		{ "TF2_perr_1", 15, 1 },
+		{ "TF3_perr_1", 14, 1 },
+		{ "TF4_perr_1", 13, 1 },
+		{ "TF0_perr_0", 12, 1 },
+		{ "TF1_perr_0", 11, 1 },
+		{ "TF2_perr_0", 10, 1 },
+		{ "TF3_perr_0", 9, 1 },
+		{ "TF4_perr_0", 8, 1 },
+		{ "Perr_tf_in_ctl", 0, 8 },
+	{ "MPS_TRC_TIMESTAMP_L", 0xa4e8, 0 },
+	{ "MPS_TRC_TIMESTAMP_H", 0xa4ec, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
+	{ "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
+	{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
+	{ "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
+	{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
+	{ "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
+	{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
+	{ "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
+	{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa000, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa004, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa008, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa00c, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa010, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa014, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa018, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa01c, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa020, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa024, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa028, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa02c, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa030, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa034, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa038, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa03c, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa040, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa044, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa048, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa04c, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa050, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa054, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa058, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa05c, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa060, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa064, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa068, 0 },
+	{ "MPS_TRC_FILTER4_MATCH", 0xa06c, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa080, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa084, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa088, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa08c, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa090, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa094, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa098, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa09c, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0a0, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0a4, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0a8, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0ac, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0b0, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0b4, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0b8, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0bc, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0c0, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0c4, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0c8, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0cc, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0d0, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0d4, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0d8, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0dc, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0e0, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0e4, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0e8, 0 },
+	{ "MPS_TRC_FILTER4_DONT_CARE", 0xa0ec, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa100, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa104, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa108, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa10c, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa110, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa114, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa118, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa11c, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa120, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa124, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa128, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa12c, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa130, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa134, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa138, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa13c, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa140, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa144, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa148, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa14c, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa150, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa154, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa158, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa15c, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa160, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa164, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa168, 0 },
+	{ "MPS_TRC_FILTER5_MATCH", 0xa16c, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa180, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa184, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa188, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa18c, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa190, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa194, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa198, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa19c, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1a0, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1a4, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1a8, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1ac, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1b0, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1b4, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1b8, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1bc, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1c0, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1c4, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1c8, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1cc, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1d0, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1d4, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1d8, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1dc, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1e0, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1e4, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1e8, 0 },
+	{ "MPS_TRC_FILTER5_DONT_CARE", 0xa1ec, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa200, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa204, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa208, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa20c, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa210, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa214, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa218, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa21c, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa220, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa224, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa228, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa22c, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa230, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa234, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa238, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa23c, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa240, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa244, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa248, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa24c, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa250, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa254, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa258, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa25c, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa260, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa264, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa268, 0 },
+	{ "MPS_TRC_FILTER6_MATCH", 0xa26c, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa280, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa284, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa288, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa28c, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa290, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa294, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa298, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa29c, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2a0, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2a4, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2a8, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2ac, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2b0, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2b4, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2b8, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2bc, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2c0, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2c4, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2c8, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2cc, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2d0, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2d4, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2d8, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2dc, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2e0, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2e4, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2e8, 0 },
+	{ "MPS_TRC_FILTER6_DONT_CARE", 0xa2ec, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa300, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa304, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa308, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa30c, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa310, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa314, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa318, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa31c, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa320, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa324, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa328, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa32c, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa330, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa334, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa338, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa33c, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa340, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa344, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa348, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa34c, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa350, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa354, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa358, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa35c, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa360, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa364, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa368, 0 },
+	{ "MPS_TRC_FILTER7_MATCH", 0xa36c, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa380, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa384, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa388, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa38c, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa390, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa394, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa398, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa39c, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3a0, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3a4, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3a8, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3ac, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3b0, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3b4, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3b8, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3bc, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3c0, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3c4, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3c8, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3cc, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3d0, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3d4, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3d8, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3dc, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3e0, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3e4, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3e8, 0 },
+	{ "MPS_TRC_FILTER7_DONT_CARE", 0xa3ec, 0 },
+	{ "MPS_STAT_CTL", 0x9600, 0 },
+		{ "StatStopCtrl", 10, 1 },
+		{ "StopStat", 9, 1 },
+		{ "StatWriteCtrl", 8, 1 },
+		{ "CountLbPF", 7, 1 },
+		{ "CountLbVF", 6, 1 },
+		{ "CountPauseMCRx", 5, 1 },
+		{ "CountPauseStatRx", 4, 1 },
+		{ "CountPauseMCTx", 3, 1 },
+		{ "CountPauseStatTx", 2, 1 },
+		{ "CountVFinPF", 1, 1 },
+		{ "LpbkErrStat", 0, 1 },
+	{ "MPS_STAT_INT_ENABLE", 0x9608, 0 },
+	{ "MPS_STAT_INT_CAUSE", 0x960c, 0 },
+	{ "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
+		{ "Rxbg", 27, 2 },
+		{ "Rxpf", 22, 5 },
+		{ "Txpf", 18, 4 },
+		{ "Rxport", 11, 7 },
+		{ "Lbport", 6, 5 },
+		{ "Txport", 0, 6 },
+	{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
+		{ "Rxbg", 27, 2 },
+		{ "Rxpf", 22, 5 },
+		{ "Txpf", 18, 4 },
+		{ "Rxport", 11, 7 },
+		{ "Lbport", 6, 5 },
+		{ "Txport", 0, 6 },
+	{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
+		{ "Rxbg", 27, 2 },
+		{ "Rxpf", 22, 5 },
+		{ "Txpf", 18, 4 },
+		{ "Rxport", 11, 7 },
+		{ "Lbport", 6, 5 },
+		{ "Txport", 0, 6 },
+	{ "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
+		{ "TxCh", 20, 4 },
+		{ "Tx", 12, 8 },
+		{ "Pause", 8, 4 },
+		{ "Drop", 0, 8 },
+	{ "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
+		{ "TxCh", 20, 4 },
+		{ "Tx", 12, 8 },
+		{ "Pause", 8, 4 },
+		{ "Drop", 0, 8 },
+	{ "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
+		{ "TxCh", 20, 4 },
+		{ "Tx", 12, 8 },
+		{ "Pause", 8, 4 },
+		{ "Drop", 0, 8 },
+	{ "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
+		{ "Pause", 20, 4 },
+		{ "Lpbk", 16, 4 },
+		{ "Nq", 8, 8 },
+		{ "PV", 4, 4 },
+		{ "Mac", 0, 4 },
+	{ "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
+		{ "Pause", 20, 4 },
+		{ "Lpbk", 16, 4 },
+		{ "Nq", 8, 8 },
+		{ "PV", 4, 4 },
+		{ "Mac", 0, 4 },
+	{ "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
+		{ "Pause", 20, 4 },
+		{ "Lpbk", 16, 4 },
+		{ "Nq", 8, 8 },
+		{ "PV", 4, 4 },
+		{ "Mac", 0, 4 },
+	{ "MPS_STAT_PERR_INJECT", 0x9634, 0 },
+		{ "MemSel", 1, 7 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
+		{ "SubPrtH", 5, 5 },
+		{ "SubPrtL", 0, 5 },
+	{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
+	{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
+	{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
+	{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
+	{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
+	{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
+	{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
+	{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
+	{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
+	{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
+	{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
+	{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
+	{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
+	{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
+	{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
+	{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
+	{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
+	{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
+	{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
+	{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
+	{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
+	{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
+	{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
+	{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
+	{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
+	{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
+	{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
+	{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
+	{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
+	{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
+	{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
+	{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
+	{ "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
+		{ "Rxvf", 5, 3 },
+		{ "Txvf", 0, 5 },
+	{ "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
+		{ "Rxvf", 5, 3 },
+		{ "Txvf", 0, 5 },
+	{ "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
+		{ "Rxvf", 5, 3 },
+		{ "Txvf", 0, 5 },
+	{ "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
+	{ "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
+		{ "PtLpbk", 8, 4 },
+		{ "PtTx", 4, 4 },
+		{ "PtRx", 0, 4 },
+	{ "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 },
+		{ "PFTx", 8, 8 },
+		{ "PFRx", 0, 8 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_128_159", 0x9710, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_160_191", 0x9714, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_192_223", 0x9718, 0 },
+	{ "MPS_STAT_STOP_UPD_TX_VF_224_255", 0x971c, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_128_159", 0x96f8, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_160_191", 0x96fc, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_192_223", 0x9700, 0 },
+	{ "MPS_STAT_STOP_UPD_RX_VF_224_255", 0x9704, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L", 0x30620, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H", 0x30624, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L", 0x30628, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H", 0x3062c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L", 0x30630, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H", 0x30634, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L", 0x30638, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H", 0x3063c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L", 0x30640, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H", 0x30644, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L", 0x30648, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H", 0x3064c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L", 0x30650, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H", 0x30654, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L", 0x30658, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H", 0x3065c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x32400, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x32404, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x32408, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3240c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x32410, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x32414, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x32418, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3241c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x32420, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x32424, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x32428, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3242c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x32430, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x32434, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x32438, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3243c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x32440, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x32444, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x32448, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3244c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x32450, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x32454, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x32458, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3245c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x32460, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x32464, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x32468, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3246c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x32470, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x32474, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x32478, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3247c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x32480, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x32484, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x32488, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3248c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x32490, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x32494, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x32498, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3249c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x324a0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x324a4, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x324a8, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x324ac, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x324b0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x324b4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x324c0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x324c4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x324c8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x324cc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x324d0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x324d4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x324d8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x324dc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x324e0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x324e4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x324e8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x324ec, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x324f0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x324f4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x324f8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x324fc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x32500, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x32504, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x32508, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3250c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x32510, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x32514, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x32518, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3251c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x32520, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x32524, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x32528, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3252c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x32540, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x32544, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x32548, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3254c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x32550, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x32554, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x32558, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3255c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x32560, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x32564, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x32568, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3256c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x32570, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x32574, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x32578, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3257c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x32580, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x32584, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x32588, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3258c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x32590, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x32594, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x32598, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3259c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x325a0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x325a4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x325a8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x325ac, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x325b0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x325b4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x325b8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x325bc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x325c0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x325c4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x325c8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x325cc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x325d0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x325d4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x325d8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x325dc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x325e0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x325e4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x325e8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x325ec, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x325f0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x325f4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x325f8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x325fc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x32600, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x32604, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x32608, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3260c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x32610, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x32614, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x32618, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3261c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L", 0x32620, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H", 0x32624, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L", 0x32628, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H", 0x3262c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L", 0x32630, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H", 0x32634, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L", 0x32638, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H", 0x3263c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L", 0x32640, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H", 0x32644, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L", 0x32648, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H", 0x3264c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L", 0x32650, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H", 0x32654, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L", 0x32658, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H", 0x3265c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L", 0x34620, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H", 0x34624, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L", 0x34628, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H", 0x3462c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L", 0x34630, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H", 0x34634, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L", 0x34638, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H", 0x3463c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L", 0x34640, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H", 0x34644, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L", 0x34648, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H", 0x3464c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L", 0x34650, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H", 0x34654, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L", 0x34658, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H", 0x3465c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x36400, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x36404, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x36408, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3640c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x36410, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x36414, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x36418, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3641c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x36420, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x36424, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x36428, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3642c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x36430, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x36434, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x36438, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3643c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x36440, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x36444, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x36448, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3644c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x36450, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x36454, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x36458, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3645c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x36460, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x36464, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x36468, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3646c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x36470, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x36474, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x36478, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3647c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x36480, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x36484, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x36488, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3648c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x36490, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x36494, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x36498, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3649c, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x364a0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x364a4, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x364a8, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x364ac, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x364b0, 0 },
+	{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x364b4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x364c0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x364c4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x364c8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x364cc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x364d0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x364d4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x364d8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x364dc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x364e0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x364e4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x364e8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x364ec, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x364f0, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x364f4, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x364f8, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x364fc, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x36500, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x36504, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x36508, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3650c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x36510, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x36514, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x36518, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3651c, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x36520, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x36524, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x36528, 0 },
+	{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3652c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x36540, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x36544, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x36548, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3654c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x36550, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x36554, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x36558, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3655c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x36560, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x36564, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x36568, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3656c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x36570, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x36574, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x36578, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3657c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x36580, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x36584, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x36588, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3658c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x36590, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x36594, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x36598, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3659c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x365a0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x365a4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x365a8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x365ac, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x365b0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x365b4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x365b8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x365bc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x365c0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x365c4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x365c8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x365cc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x365d0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x365d4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x365d8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x365dc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x365e0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x365e4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x365e8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x365ec, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x365f0, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x365f4, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x365f8, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x365fc, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x36600, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x36604, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x36608, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3660c, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x36610, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x36614, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x36618, 0 },
+	{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3661c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L", 0x36620, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H", 0x36624, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L", 0x36628, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H", 0x3662c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L", 0x36630, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H", 0x36634, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L", 0x36638, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H", 0x3663c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L", 0x36640, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H", 0x36644, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L", 0x36648, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H", 0x3664c, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L", 0x36650, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H", 0x36654, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L", 0x36658, 0 },
+	{ "MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H", 0x3665c, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1e380, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1e384, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1e780, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1e784, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1eb80, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1eb84, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1ef80, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1ef84, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1f380, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1f384, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1f780, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1f784, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1fb80, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1fb84, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
+	{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
+	{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
+	{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
+	{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
+	{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
+	{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
+	{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
+	{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
+	{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L", 0x1ff80, 0 },
+	{ "MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H", 0x1ff84, 0 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3020c, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30210, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30214, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30218, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3021c, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30220, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30224, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30228, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
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+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30248, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30254, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x302e4, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x302ec, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x302f0, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
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+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x302f4, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x302f8, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x30300, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32200, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32204, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32208, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3220c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32210, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32214, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32218, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32228, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32270, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32274, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32278, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32280, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3228c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32290, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x32298, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3229c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322a0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322a4, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322a8, 0 },
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+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322ac, 0 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322b0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322b8, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322bc, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322c0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322d0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322d4, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x322d8, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3420c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3421c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34224, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34228, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3422c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34230, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34234, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34238, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3423c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34240, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34244, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34248, 0 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3424c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34250, 0 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34254, 0 },
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+		{ "DisEncap", 22, 1 },
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+		{ "PF", 9, 3 },
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+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34258, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
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+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3425c, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
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+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34260, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
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+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x34264, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36214, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36218, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3621c, 0 },
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+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36220, 0 },
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+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
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+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36224, 0 },
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+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36228, 0 },
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+		{ "DisEncap", 22, 1 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3622c, 0 },
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+		{ "DisEncap", 22, 1 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36230, 0 },
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+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36234, 0 },
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+		{ "DisEncap", 22, 1 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36238, 0 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3623c, 0 },
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+		{ "PF", 9, 3 },
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+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36240, 0 },
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+		{ "DisEncap", 22, 1 },
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+		{ "PF", 9, 3 },
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+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36244, 0 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36248, 0 },
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+		{ "DisEncap", 22, 1 },
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+		{ "VF_Valid", 8, 1 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3624c, 0 },
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+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36250, 0 },
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+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36254, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36258, 0 },
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+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3625c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36260, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36264, 0 },
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+		{ "VF_Valid", 8, 1 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36268, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3626c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3627c, 0 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36280, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36284, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36288, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3628c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36290, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36294, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36298, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x3629c, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362a0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362a4, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362a8, 0 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362ac, 0 },
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+		{ "DisEncap", 22, 1 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362b0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362b4, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362b8, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362bc, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362c8, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362cc, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362d0, 0 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362d4, 0 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362d8, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
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+		{ "PF", 9, 3 },
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+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362dc, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362e0, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362e4, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362e8, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362ec, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362f0, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362f4, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362f8, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x362fc, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_SRAM", 0x36300, 0 },
+		{ "DisEncapOuterRplct", 23, 1 },
+		{ "DisEncap", 22, 1 },
+		{ "Valid", 21, 1 },
+		{ "PortMap", 17, 4 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 },
+		{ "UnicastEnable", 31, 1 },
+	{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 },
+		{ "Enable", 31, 1 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_L", 0x3030c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_H", 0x30310, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_L", 0x30324, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_H", 0x30328, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_L", 0x3032c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_H", 0x30330, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_L", 0x30334, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_H", 0x30338, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_VLAN0", 0x30314, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN1", 0x3033c, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN2", 0x30340, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN3", 0x30344, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_CTL", 0x30318, 0 },
+		{ "SMAC_INDEX_EN", 17, 1 },
+		{ "LPBK_TCAM2_HIT_PRIORITY", 16, 1 },
+		{ "TCAM2_HIT_PRIORITY", 15, 1 },
+		{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+		{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+		{ "LPBK_TCAM_PRIORITY", 12, 1 },
+		{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
+		{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
+		{ "TCAM1_HIT_PRIORITY", 7, 1 },
+		{ "TCAM0_HIT_PRIORITY", 6, 1 },
+		{ "TCAM_PRIORITY", 5, 1 },
+		{ "SMAC_TCAM_SEL", 3, 2 },
+		{ "DMAC_TCAM_SEL", 1, 2 },
+		{ "PF_VLAN_SEL", 0, 1 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3031c, 0 },
+		{ "EthType1", 16, 16 },
+		{ "EthType2", 0, 16 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x30320, 0 },
+		{ "EN1", 1, 1 },
+		{ "EN2", 0, 1 },
+	{ "MPS_PORT_CLS_HASH_CTL", 0x32304, 0 },
+		{ "UnicastEnable", 31, 1 },
+	{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x32308, 0 },
+		{ "Enable", 31, 1 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_L", 0x3230c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_H", 0x32310, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_L", 0x32324, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_H", 0x32328, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_L", 0x3232c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_H", 0x32330, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_L", 0x32334, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_H", 0x32338, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_VLAN0", 0x32314, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN1", 0x3233c, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN2", 0x32340, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN3", 0x32344, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_CTL", 0x32318, 0 },
+		{ "SMAC_INDEX_EN", 17, 1 },
+		{ "LPBK_TCAM2_HIT_PRIORITY", 16, 1 },
+		{ "TCAM2_HIT_PRIORITY", 15, 1 },
+		{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+		{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+		{ "LPBK_TCAM_PRIORITY", 12, 1 },
+		{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
+		{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
+		{ "TCAM1_HIT_PRIORITY", 7, 1 },
+		{ "TCAM0_HIT_PRIORITY", 6, 1 },
+		{ "TCAM_PRIORITY", 5, 1 },
+		{ "SMAC_TCAM_SEL", 3, 2 },
+		{ "DMAC_TCAM_SEL", 1, 2 },
+		{ "PF_VLAN_SEL", 0, 1 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3231c, 0 },
+		{ "EthType1", 16, 16 },
+		{ "EthType2", 0, 16 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x32320, 0 },
+		{ "EN1", 1, 1 },
+		{ "EN2", 0, 1 },
+	{ "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 },
+		{ "UnicastEnable", 31, 1 },
+	{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 },
+		{ "Enable", 31, 1 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_L", 0x3430c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_H", 0x34310, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_L", 0x34324, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_H", 0x34328, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_L", 0x3432c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_H", 0x34330, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_L", 0x34334, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_H", 0x34338, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_VLAN0", 0x34314, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN1", 0x3433c, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN2", 0x34340, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN3", 0x34344, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_CTL", 0x34318, 0 },
+		{ "SMAC_INDEX_EN", 17, 1 },
+		{ "LPBK_TCAM2_HIT_PRIORITY", 16, 1 },
+		{ "TCAM2_HIT_PRIORITY", 15, 1 },
+		{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+		{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+		{ "LPBK_TCAM_PRIORITY", 12, 1 },
+		{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
+		{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
+		{ "TCAM1_HIT_PRIORITY", 7, 1 },
+		{ "TCAM0_HIT_PRIORITY", 6, 1 },
+		{ "TCAM_PRIORITY", 5, 1 },
+		{ "SMAC_TCAM_SEL", 3, 2 },
+		{ "DMAC_TCAM_SEL", 1, 2 },
+		{ "PF_VLAN_SEL", 0, 1 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3431c, 0 },
+		{ "EthType1", 16, 16 },
+		{ "EthType2", 0, 16 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x34320, 0 },
+		{ "EN1", 1, 1 },
+		{ "EN2", 0, 1 },
+	{ "MPS_PORT_CLS_HASH_CTL", 0x36304, 0 },
+		{ "UnicastEnable", 31, 1 },
+	{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x36308, 0 },
+		{ "Enable", 31, 1 },
+		{ "MultiListen", 16, 1 },
+		{ "Priority", 13, 3 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_L", 0x3630c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC0_ADDR_H", 0x36310, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_L", 0x36324, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC1_ADDR_H", 0x36328, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_L", 0x3632c, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC2_ADDR_H", 0x36330, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_L", 0x36334, 0 },
+	{ "MPS_PORT_CLS_BMC_MAC3_ADDR_H", 0x36338, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_PORT_CLS_BMC_VLAN0", 0x36314, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN1", 0x3633c, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN2", 0x36340, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_BMC_VLAN3", 0x36344, 0 },
+		{ "BMC_VLAN_SEL", 13, 1 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_PORT_CLS_CTL", 0x36318, 0 },
+		{ "SMAC_INDEX_EN", 17, 1 },
+		{ "LPBK_TCAM2_HIT_PRIORITY", 16, 1 },
+		{ "TCAM2_HIT_PRIORITY", 15, 1 },
+		{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+		{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+		{ "LPBK_TCAM_PRIORITY", 12, 1 },
+		{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
+		{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
+		{ "TCAM1_HIT_PRIORITY", 7, 1 },
+		{ "TCAM0_HIT_PRIORITY", 6, 1 },
+		{ "TCAM_PRIORITY", 5, 1 },
+		{ "SMAC_TCAM_SEL", 3, 2 },
+		{ "DMAC_TCAM_SEL", 1, 2 },
+		{ "PF_VLAN_SEL", 0, 1 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3631c, 0 },
+		{ "EthType1", 16, 16 },
+		{ "EthType2", 0, 16 },
+	{ "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x36320, 0 },
+		{ "EN1", 1, 1 },
+		{ "EN2", 0, 1 },
+	{ "MPS_CLS_CTL", 0xd000, 0 },
+		{ "VlanClsEn_in", 7, 1 },
+		{ "DisTcamParChk", 6, 1 },
+		{ "VlanLkpEn", 5, 1 },
+		{ "MemWriteFault", 4, 1 },
+		{ "MemWriteWaiting", 3, 1 },
+		{ "CimNoPromiscuous", 2, 1 },
+		{ "HypervisorOnly", 1, 1 },
+		{ "VlanClsEn", 0, 1 },
+	{ "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
+		{ "PlWeight", 16, 5 },
+		{ "CimWeight", 8, 5 },
+		{ "LpbkWeight", 0, 5 },
+	{ "MPS_CLS_NCSI_ETH_TYPE", 0xd008, 0 },
+		{ "EthType1", 16, 16 },
+		{ "EthType2", 0, 16 },
+	{ "MPS_CLS_NCSI_ETH_TYPE_EN", 0xd00c, 0 },
+		{ "EN1", 1, 1 },
+		{ "EN2", 0, 1 },
+	{ "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
+	{ "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
+		{ "MatchAll", 18, 1 },
+		{ "MatchBoth", 17, 1 },
+		{ "Valid", 16, 1 },
+		{ "DA", 0, 16 },
+	{ "MPS_CLS_BMC_VLAN", 0xd018, 0 },
+		{ "Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_TCAM0_MASK_REG0", 0xf040, 0 },
+	{ "MPS_CLS_TCAM0_MASK_REG1", 0xf044, 0 },
+	{ "MPS_CLS_TCAM0_MASK_REG2", 0xf048, 0 },
+	{ "MPS_CLS_TCAM1_MASK_REG0", 0xf04c, 0 },
+	{ "MPS_CLS_TCAM1_MASK_REG1", 0xf050, 0 },
+	{ "MPS_CLS_TCAM1_MASK_REG2", 0xf054, 0 },
+	{ "MPS_CLS_TCAM2_MASK_REG0", 0xf064, 0 },
+	{ "MPS_CLS_TCAM2_MASK_REG1", 0xf068, 0 },
+	{ "MPS_CLS_TCAM2_MASK_REG2", 0xf06c, 0 },
+	{ "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
+		{ "MemSel", 1, 2 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
+		{ "CIM2MPS_Intf_Par", 4, 1 },
+		{ "TCAM_CRC_SRAM", 3, 1 },
+		{ "HashSRAM", 2, 1 },
+		{ "MatchTCAM", 1, 1 },
+		{ "MatchSRAM", 0, 1 },
+	{ "MPS_CLS_INT_ENABLE", 0xd024, 0 },
+		{ "PLErrEnb", 5, 1 },
+		{ "CIM2MPS_Intf_Par", 4, 1 },
+		{ "TCAM_CRC_SRAM", 3, 1 },
+		{ "HashSRAM", 2, 1 },
+		{ "MatchTCAM", 1, 1 },
+		{ "MatchSRAM", 0, 1 },
+	{ "MPS_CLS_INT_CAUSE", 0xd028, 0 },
+		{ "PLErrEnb", 5, 1 },
+		{ "CIM2MPS_Intf_Par", 4, 1 },
+		{ "TCAM_CRC_SRAM", 3, 1 },
+		{ "HashSRAM", 2, 1 },
+		{ "MatchTCAM", 1, 1 },
+		{ "MatchSRAM", 0, 1 },
+	{ "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
+	{ "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
+	{ "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
+		{ "Cls_Spare", 30, 2 },
+		{ "Cls_Priority", 27, 3 },
+		{ "Cls_Replicate", 26, 1 },
+		{ "Cls_Index", 15, 11 },
+		{ "Cls_VF", 7, 8 },
+		{ "Cls_VF_Vld", 6, 1 },
+		{ "Cls_PF", 3, 3 },
+		{ "Cls_Match", 0, 3 },
+	{ "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
+	{ "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
+	{ "MPS_CLS0_MATCH_CNT_TCAM", 0xd100, 0 },
+	{ "MPS_CLS0_MATCH_CNT_HASH", 0xd104, 0 },
+	{ "MPS_CLS0_MATCH_CNT_BCAST", 0xd108, 0 },
+	{ "MPS_CLS0_MATCH_CNT_BMC", 0xd10c, 0 },
+	{ "MPS_CLS0_MATCH_CNT_PROM", 0xd110, 0 },
+	{ "MPS_CLS0_MATCH_CNT_HPROM", 0xd114, 0 },
+	{ "MPS_CLS0_MISS_CNT", 0xd118, 0 },
+	{ "MPS_CLS1_MATCH_CNT_TCAM", 0xd11c, 0 },
+	{ "MPS_CLS1_MATCH_CNT_HASH", 0xd120, 0 },
+	{ "MPS_CLS1_MATCH_CNT_BCAST", 0xd124, 0 },
+	{ "MPS_CLS1_MATCH_CNT_BMC", 0xd128, 0 },
+	{ "MPS_CLS1_MATCH_CNT_PROM", 0xd12c, 0 },
+	{ "MPS_CLS1_MATCH_CNT_HPROM", 0xd130, 0 },
+	{ "MPS_CLS1_MISS_CNT", 0xd134, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd200, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd220, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd240, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd260, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd280, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2a0, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2c0, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2e0, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd204, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd224, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd244, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd264, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd284, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2a4, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2c4, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2e4, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd208, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd228, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd248, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd268, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd288, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2a8, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2c8, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2e8, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd20c, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd22c, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd24c, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd26c, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd28c, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ac, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2cc, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ec, 0 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd210, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd230, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd250, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd270, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd290, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2b0, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2d0, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2f0, 0 },
+		{ "ClsTrcVlanVld", 31, 1 },
+		{ "ClsTrcVlanId", 16, 12 },
+		{ "ClsTrcReqPort", 0, 4 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd214, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd234, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd254, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd274, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd294, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2b4, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2d4, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2f4, 0 },
+		{ "ClsTrcLkpType", 31, 1 },
+		{ "ClsTrcDIPHit", 30, 1 },
+		{ "ClsTrcVNI", 0, 24 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd300, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd304, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd308, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd30c, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd310, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd314, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd318, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_RESULT_TRACE", 0xd31c, 0 },
+		{ "ClsTrcPortNum", 31, 1 },
+		{ "ClsTrcPriority", 28, 3 },
+		{ "ClsTrcMultiListen", 27, 1 },
+		{ "ClsTrcReplicate", 26, 1 },
+		{ "ClsTrcPortMap", 24, 2 },
+		{ "ClsTrcMatch", 23, 1 },
+		{ "ClsTrcIndex", 12, 11 },
+		{ "ClsTrcVF_Vld", 11, 1 },
+		{ "ClsTrcPF", 3, 8 },
+		{ "ClsTrcVF", 0, 3 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
+		{ "VLAN_Mask", 16, 12 },
+		{ "PF", 13, 3 },
+		{ "VLAN_Valid", 12, 1 },
+		{ "VLAN_ID", 0, 12 },
+	{ "MPS_CLS_DIP_ID_TABLE_CTL", 0x12000, 0 },
+		{ "DIP_VLD", 12, 1 },
+		{ "DIP_TYPE", 11, 1 },
+		{ "DIP_WRN", 10, 1 },
+		{ "DIP_SEG", 8, 2 },
+		{ "DIP_TBL_RSVD1", 5, 3 },
+		{ "DIP_TBL_ADDR", 0, 5 },
+	{ "MPS_CLS_DIP_ID_TABLE_DATA", 0x12004, 0 },
+	{ "MPS_RX_HASH_LKP_TABLE", 0x12060, 0 },
+	{ "MPS_RX_HASH_LKP_TABLE", 0x12064, 0 },
+	{ "MPS_RX_HASH_LKP_TABLE", 0x12068, 0 },
+	{ "MPS_RX_HASH_LKP_TABLE", 0x1206c, 0 },
+	{ "MPS_CLS_SRAM_L", 0xe000, 0 },
+		{ "DisEncapOuterRplct", 31, 1 },
+		{ "DisEncap", 30, 1 },
+		{ "MultiListen3", 29, 1 },
+		{ "MultiListen2", 28, 1 },
+		{ "MultiListen1", 27, 1 },
+		{ "MultiListen0", 26, 1 },
+		{ "Priority3", 23, 3 },
+		{ "Priority2", 20, 3 },
+		{ "Priority1", 17, 3 },
+		{ "Priority0", 14, 3 },
+		{ "Valid", 13, 1 },
+		{ "Replicate", 12, 1 },
+		{ "PF", 9, 3 },
+		{ "VF_Valid", 8, 1 },
+		{ "VF", 0, 8 },
+	{ "MPS_CLS_SRAM_H", 0xe004, 0 },
+		{ "SramWRN", 31, 1 },
+		{ "SramSpare", 27, 4 },
+		{ "SramIndex", 16, 11 },
+		{ "MacParity2", 10, 1 },
+		{ "MacParity1", 9, 1 },
+		{ "MacParity0", 8, 1 },
+		{ "MacParityMaskSize", 4, 4 },
+		{ "PortMap", 0, 4 },
+	{ "MPS_CLS_HASH_TCAM_CTL", 0xe008, 0 },
+		{ "CtlCmdType", 15, 1 },
+		{ "CtlXYBitSel", 12, 1 },
+		{ "CtlTcamIndex", 0, 9 },
+	{ "MPS_CLS_HASH_TCAM_DATA", 0xe00c, 0 },
+		{ "LkpType", 24, 1 },
+		{ "VNI", 0, 24 },
+	{ "MPS_CLS_TCAM_DATA0", 0xf000, 0 },
+	{ "MPS_CLS_TCAM_DATA1", 0xf004, 0 },
+		{ "VIDL", 16, 16 },
+		{ "DMACH", 0, 16 },
+	{ "MPS_CLS_TCAM_DATA2_CTL", 0xf008, 0 },
+		{ "CtlCmdType", 31, 1 },
+		{ "CtlReqID", 30, 1 },
+		{ "CtlTcamSel", 26, 2 },
+		{ "CtlTcamIndex", 17, 9 },
+		{ "CtlXYBitSel", 16, 1 },
+		{ "DataPortNum", 12, 4 },
+		{ "DataLkpType", 10, 2 },
+		{ "DataDipHit", 8, 1 },
+		{ "DataVIDH2", 7, 1 },
+		{ "DataVIDH1", 0, 7 },
+	{ "MPS_CLS_TCAM0_RDATA0_REQ_ID0", 0xf010, 0 },
+	{ "MPS_CLS_TCAM0_RDATA1_REQ_ID0", 0xf014, 0 },
+		{ "VIDL", 16, 16 },
+		{ "DMACH", 0, 16 },
+	{ "MPS_CLS_TCAM0_RDATA2_REQ_ID0", 0xf018, 0 },
+		{ "DataPortNum", 12, 4 },
+		{ "DataLkpType", 10, 2 },
+		{ "DataDipHit", 8, 1 },
+		{ "DataVIDH2", 7, 1 },
+		{ "DataVIDH1", 0, 7 },
+	{ "MPS_CLS_TCAM0_RDATA0_REQ_ID1", 0xf01c, 0 },
+	{ "MPS_CLS_TCAM0_RDATA1_REQ_ID1", 0xf020, 0 },
+		{ "VIDL", 16, 16 },
+		{ "DMACH", 0, 16 },
+	{ "MPS_CLS_TCAM0_RDATA2_REQ_ID1", 0xf024, 0 },
+		{ "DataPortNum", 12, 4 },
+		{ "DataLkpType", 10, 2 },
+		{ "DataDipHit", 8, 1 },
+		{ "DataVIDH2", 7, 1 },
+		{ "DataVIDH1", 0, 7 },
+	{ "MPS_CLS_TCAM1_RDATA0_REQ_ID0", 0xf028, 0 },
+	{ "MPS_CLS_TCAM1_RDATA1_REQ_ID0", 0xf02c, 0 },
+		{ "VIDL", 16, 16 },
+		{ "DMACH", 0, 16 },
+	{ "MPS_CLS_TCAM1_RDATA2_REQ_ID0", 0xf030, 0 },
+		{ "DataPortNum", 12, 4 },
+		{ "DataLkpType", 10, 2 },
+		{ "DataDipHit", 8, 1 },
+		{ "DataVIDH2", 7, 1 },
+		{ "DataVIDH1", 0, 7 },
+	{ "MPS_CLS_TCAM1_RDATA0_REQ_ID1", 0xf034, 0 },
+	{ "MPS_CLS_TCAM1_RDATA1_REQ_ID1", 0xf038, 0 },
+		{ "VIDL", 16, 16 },
+		{ "DMACH", 0, 16 },
+	{ "MPS_CLS_TCAM1_RDATA2_REQ_ID1", 0xf03c, 0 },
+		{ "DataPortNum", 12, 4 },
+		{ "DataLkpType", 10, 2 },
+		{ "DataDipHit", 8, 1 },
+		{ "DataVIDH2", 7, 1 },
+		{ "DataVIDH1", 0, 7 },
+	{ "MPS_CLS_TCAM_BIST_CTRL", 0xf058, 0 },
+		{ "rst_cb", 31, 1 },
+		{ "cb_start", 0, 28 },
+	{ "MPS_CLS_TCAM_BIST_CB_PASS", 0xf05c, 0 },
+	{ "MPS_CLS_TCAM_BIST_CB_BUSY", 0xf060, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_cpl_switch_regs[] = {
+	{ "CNTRL", 0x19040, 0 },
+		{ "cpl_pkt_tid", 8, 24 },
+		{ "cim_split_enable", 6, 1 },
+		{ "cim_truncate_enable", 5, 1 },
+		{ "cim_to_up_full_size", 4, 1 },
+		{ "cpu_no_enable", 3, 1 },
+		{ "switch_table_enable", 2, 1 },
+		{ "sge_enable", 1, 1 },
+		{ "cim_enable", 0, 1 },
+	{ "TBL_IDX", 0x19044, 0 },
+	{ "TBL_DATA", 0x19048, 0 },
+	{ "ZERO_ERROR", 0x1904c, 0 },
+		{ "zero_cmd_ch3", 24, 8 },
+		{ "zero_cmd_ch2", 16, 8 },
+		{ "zero_cmd_ch1", 8, 8 },
+		{ "zero_cmd_ch0", 0, 8 },
+	{ "INTR_ENABLE", 0x19050, 0 },
+		{ "perr_cpl_128to128_3", 9, 1 },
+		{ "perr_cpl_128to128_2", 8, 1 },
+		{ "perr_cpl_128to128_1", 7, 1 },
+		{ "perr_cpl_128to128_0", 6, 1 },
+		{ "cim_op_map_perr", 5, 1 },
+		{ "cim_ovfl_error", 4, 1 },
+		{ "tp_framing_error", 3, 1 },
+		{ "sge_framing_error", 2, 1 },
+		{ "cim_framing_error", 1, 1 },
+		{ "zero_switch_error", 0, 1 },
+	{ "INTR_CAUSE", 0x19054, 0 },
+		{ "perr_cpl_128to128_3", 9, 1 },
+		{ "perr_cpl_128to128_2", 8, 1 },
+		{ "perr_cpl_128to128_1", 7, 1 },
+		{ "perr_cpl_128to128_0", 6, 1 },
+		{ "cim_op_map_perr", 5, 1 },
+		{ "cim_ovfl_error", 4, 1 },
+		{ "tp_framing_error", 3, 1 },
+		{ "sge_framing_error", 2, 1 },
+		{ "cim_framing_error", 1, 1 },
+		{ "zero_switch_error", 0, 1 },
+	{ "MAP_TBL_IDX", 0x19058, 0 },
+		{ "cpl_map_tbl_sel", 9, 2 },
+		{ "cim_split_opcode_program", 8, 1 },
+		{ "cpl_map_tbl_idx", 0, 8 },
+	{ "MAP_TBL_DATA", 0x1905c, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_smb_regs[] = {
+	{ "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
+		{ "MacroCntCfg", 12, 5 },
+		{ "MicroCntCfg", 0, 12 },
+	{ "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
+	{ "SMB_MST_CTL_CFG", 0x19068, 0 },
+		{ "MstFifoDbg", 31, 1 },
+		{ "MstFifoDbgClr", 30, 1 },
+		{ "MstRxByteCfg", 12, 6 },
+		{ "MstTxByteCfg", 6, 6 },
+		{ "MstReset", 1, 1 },
+		{ "MstCtlEn", 0, 1 },
+	{ "SMB_MST_CTL_STS", 0x1906c, 0 },
+		{ "MstRxByteCnt", 12, 6 },
+		{ "MstTxByteCnt", 6, 6 },
+		{ "MstBusySts", 0, 1 },
+	{ "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
+	{ "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
+	{ "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
+	{ "SMB_SLV_CTL_CFG", 0x1907c, 0 },
+		{ "SlvFifoDbg", 31, 1 },
+		{ "SlvFifoDbgClr", 30, 1 },
+		{ "SlvCrcOutBitInv", 21, 1 },
+		{ "SlvCrcOutBitRev", 20, 1 },
+		{ "SlvCrcInBitRev", 19, 1 },
+		{ "SlvCrcPreset", 11, 8 },
+		{ "SlvAddrCfg", 4, 7 },
+		{ "SlvAlrtSet", 2, 1 },
+		{ "SlvReset", 1, 1 },
+		{ "SlvCtlEn", 0, 1 },
+	{ "SMB_SLV_CTL_STS", 0x19080, 0 },
+		{ "SlvFifoTxCnt", 12, 6 },
+		{ "SlvFifoCnt", 6, 6 },
+		{ "SlvAlrtSts", 2, 1 },
+		{ "SlvBusySts", 0, 1 },
+	{ "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
+	{ "SMB_INT_ENABLE", 0x1908c, 0 },
+		{ "MstTxFifoParEn", 21, 1 },
+		{ "MstRxFifoParEn", 20, 1 },
+		{ "SlvFifoParEn", 19, 1 },
+		{ "SlvUnExpBusStopEn", 18, 1 },
+		{ "SlvUnExpBusStartEn", 17, 1 },
+		{ "SlvCommandCodeInvEn", 16, 1 },
+		{ "SlvByteCntErrEn", 15, 1 },
+		{ "SlvUnExpAckMstEn", 14, 1 },
+		{ "SlvUnExpNackMstEn", 13, 1 },
+		{ "SlvNoBusStopEn", 12, 1 },
+		{ "SlvNoRepStartEn", 11, 1 },
+		{ "SlvRxAddrIntEn", 10, 1 },
+		{ "SlvRxPecErrIntEn", 9, 1 },
+		{ "SlvPrepToArpIntEn", 8, 1 },
+		{ "SlvTimeOutIntEn", 7, 1 },
+		{ "SlvErrIntEn", 6, 1 },
+		{ "SlvDoneIntEn", 5, 1 },
+		{ "SlvRxRdyIntEn", 4, 1 },
+		{ "MstTimeOutIntEn", 3, 1 },
+		{ "MstNAckIntEn", 2, 1 },
+		{ "MstLostArbIntEn", 1, 1 },
+		{ "MstDoneIntEn", 0, 1 },
+	{ "SMB_INT_CAUSE", 0x19090, 0 },
+		{ "MstTxFifoParInt", 21, 1 },
+		{ "MstRxFifoParInt", 20, 1 },
+		{ "SlvFifoParInt", 19, 1 },
+		{ "SlvUnExpBusStopInt", 18, 1 },
+		{ "SlvUnExpBusStartInt", 17, 1 },
+		{ "SlvCommandCodeInvInt", 16, 1 },
+		{ "SlvByteCntErrInt", 15, 1 },
+		{ "SlvUnExpAckMstInt", 14, 1 },
+		{ "SlvUnExpNackMstInt", 13, 1 },
+		{ "SlvNoBusStopInt", 12, 1 },
+		{ "SlvNoRepStartInt", 11, 1 },
+		{ "SlvRxAddrInt", 10, 1 },
+		{ "SlvRxPecErrInt", 9, 1 },
+		{ "SlvPrepToArpInt", 8, 1 },
+		{ "SlvTimeOutInt", 7, 1 },
+		{ "SlvErrInt", 6, 1 },
+		{ "SlvDoneInt", 5, 1 },
+		{ "SlvRxRdyInt", 4, 1 },
+		{ "MstTimeOutInt", 3, 1 },
+		{ "MstNAckInt", 2, 1 },
+		{ "MstLostArbInt", 1, 1 },
+		{ "MstDoneInt", 0, 1 },
+	{ "SMB_DEBUG_DATA", 0x19094, 0 },
+		{ "DebugDataH", 16, 16 },
+		{ "DebugDataL", 0, 16 },
+	{ "SMB_PERR_EN", 0x19098, 0 },
+		{ "MstTxFifo", 21, 1 },
+		{ "MstRxFifo", 19, 1 },
+		{ "SlvFifo", 18, 1 },
+		{ "MstTxFifoPerrEn", 2, 1 },
+		{ "MstRxFifoPerrEn", 1, 1 },
+		{ "SlvFifoPerrEn", 0, 1 },
+	{ "SMB_PERR_INJ", 0x1909c, 0 },
+		{ "MstTxInjDataErr", 3, 1 },
+		{ "MstRxInjDataErr", 2, 1 },
+		{ "SlvInjDataErr", 1, 1 },
+		{ "FifoInjDataErrEn", 0, 1 },
+	{ "SMB_SLV_ARP_CTL", 0x190a0, 0 },
+		{ "ArpCommandCode", 2, 8 },
+		{ "ArpAddrRes", 1, 1 },
+		{ "ArpAddrVal", 0, 1 },
+	{ "SMB_ARP_UDID0", 0x190a4, 0 },
+	{ "SMB_ARP_UDID1", 0x190a8, 0 },
+		{ "SubsystemVendorID", 16, 16 },
+		{ "SubsystemDeviceID", 0, 16 },
+	{ "SMB_ARP_UDID2", 0x190ac, 0 },
+		{ "DeviceID", 16, 16 },
+		{ "Interface", 0, 16 },
+	{ "SMB_ARP_UDID3", 0x190b0, 0 },
+		{ "DeviceCap", 24, 8 },
+		{ "VersionID", 16, 8 },
+		{ "VendorID", 0, 16 },
+	{ "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
+		{ "AuxAddr0Val", 6, 1 },
+		{ "AuxAddr0", 0, 6 },
+	{ "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
+		{ "AuxAddr1Val", 6, 1 },
+		{ "AuxAddr1", 0, 6 },
+	{ "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
+		{ "AuxAddr2Val", 6, 1 },
+		{ "AuxAddr2", 0, 6 },
+	{ "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
+		{ "AuxAddr3Val", 6, 1 },
+		{ "AuxAddr3", 0, 6 },
+	{ "SMB_COMMAND_CODE0", 0x190c4, 0 },
+	{ "SMB_COMMAND_CODE1", 0x190c8, 0 },
+	{ "SMB_COMMAND_CODE2", 0x190cc, 0 },
+	{ "SMB_COMMAND_CODE3", 0x190d0, 0 },
+	{ "SMB_COMMAND_CODE4", 0x190d4, 0 },
+	{ "SMB_COMMAND_CODE5", 0x190d8, 0 },
+	{ "SMB_COMMAND_CODE6", 0x190dc, 0 },
+	{ "SMB_COMMAND_CODE7", 0x190e0, 0 },
+	{ "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
+		{ "MacroCntClkCfg", 8, 5 },
+		{ "MicroCntClkCfg", 0, 8 },
+	{ "SMB_CTL_STATUS", 0x190e8, 0 },
+		{ "MstBusBusy", 2, 1 },
+		{ "SlvBusBusy", 1, 1 },
+		{ "BusBusy", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_i2cm_regs[] = {
+	{ "I2CM_CFG", 0x190f0, 0 },
+	{ "I2CM_DATA", 0x190f4, 0 },
+	{ "I2CM_OP", 0x190f8, 0 },
+		{ "Busy", 31, 1 },
+		{ "Ack", 30, 1 },
+		{ "Cont", 1, 1 },
+		{ "Op", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_mi_regs[] = {
+	{ "MI_CFG", 0x19100, 0 },
+		{ "T4_St", 14, 1 },
+		{ "ClkDiv", 5, 8 },
+		{ "St", 3, 2 },
+		{ "PreEn", 2, 1 },
+		{ "MDIInv", 1, 1 },
+		{ "MDIO_1P2V_Sel", 0, 1 },
+	{ "MI_ADDR", 0x19104, 0 },
+		{ "PhyAddr", 5, 5 },
+		{ "RegAddr", 0, 5 },
+	{ "MI_DATA", 0x19108, 0 },
+	{ "MI_OP", 0x1910c, 0 },
+		{ "Busy", 31, 1 },
+		{ "St", 3, 2 },
+		{ "Inc", 2, 1 },
+		{ "Op", 0, 2 },
+	{ NULL }
+};
+
+struct reg_info t7_uart_regs[] = {
+	{ "UART_CONFIG", 0x19110, 0 },
+		{ "StopBits", 25, 2 },
+		{ "Parity", 23, 2 },
+		{ "DataBits", 19, 4 },
+		{ "ClkDiv", 0, 18 },
+	{ NULL }
+};
+
+struct reg_info t7_pmu_regs[] = {
+	{ "PMU_PART_CG_PWRMODE", 0x19120, 0 },
+		{ "PL_DIS_PRTY_CHK", 20, 1 },
+		{ "ARM_Part_CGEn", 19, 1 },
+		{ "PDP_Part_CGEn", 18, 1 },
+		{ "TP_Part_CGEn", 17, 1 },
+		{ "EDC0_Part_CGEn", 16, 1 },
+		{ "EDC1_Part_CGEn", 15, 1 },
+		{ "CRYPTO_Part_CGEn", 14, 1 },
+		{ "MA_Part_CGEn", 13, 1 },
+		{ "PCIE_Part_CGEn", 10, 1 },
+		{ "NVME_Part_CGEn", 9, 1 },
+		{ "XP10_Part_CGEn", 8, 1 },
+		{ "GPEX_Part_CGEn", 7, 1 },
+		{ "InitPowerMode", 0, 2 },
+	{ "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
+		{ "GlobalDeepSleepEn", 6, 1 },
+		{ "HWWakeUpEn", 5, 1 },
+		{ "Port3SleepMode", 4, 1 },
+		{ "Port2SleepMode", 3, 1 },
+		{ "Port1SleepMode", 2, 1 },
+		{ "Port0SleepMode", 1, 1 },
+		{ "WakeUp", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_ulp_rx_regs[] = {
+	{ "ULP_RX_CTL", 0x19150, 0 },
+		{ "Iscsi_Page_Size_Chk_Enb", 31, 1 },
+		{ "Rdma_0B_Wr_Opcode_hi", 29, 1 },
+		{ "Rdma_Immediate_Cqe", 28, 1 },
+		{ "Rdma_Atomic_Wr_Rsp_Cqe", 27, 1 },
+		{ "Rdma_Verify_Rsp_Flush", 26, 1 },
+		{ "Rdma_Verify_Rsp_Cqe", 25, 1 },
+		{ "Rdma_Flush_Rsp_Cqe", 24, 1 },
+		{ "Rdma_Atomic_Rsp_Cqe", 23, 1 },
+		{ "Tpt_Extension_Mode", 22, 1 },
+		{ "NVMe_TCP_ddp_val_en", 21, 1 },
+		{ "NVMe_TCP_Remove_Hdr_Crc", 20, 1 },
+		{ "NVMe_TCP_Last_PDU_Check_Enb", 19, 1 },
+		{ "NVMe_TCP_offset_submode", 17, 2 },
+		{ "NVMe_TCP_offset_mode", 16, 1 },
+		{ "qpid_check_disable_for_send", 15, 1 },
+		{ "disable_0B_STAG_ERR", 14, 1 },
+		{ "Rdma_0B_Wr_Opcode_lo", 10, 4 },
+		{ "RDMA_0b_wr_pass", 9, 1 },
+		{ "STAG_RQE", 8, 1 },
+		{ "RDMA_State_En", 7, 1 },
+		{ "Crc1_En", 6, 1 },
+		{ "RDMA_0b_wr_cqe", 5, 1 },
+		{ "PCIE_Atrb_En", 4, 1 },
+		{ "RDMA_permissive_mode", 3, 1 },
+		{ "PagePodME", 2, 1 },
+		{ "IscsiTagTcb", 1, 1 },
+		{ "TddpTagTcb", 0, 1 },
+	{ "ULP_RX_INT_ENABLE", 0x19154, 0 },
+		{ "CERR_PCMD_FIFO_3", 19, 1 },
+		{ "CERR_PCMD_FIFO_2", 18, 1 },
+		{ "CERR_PCMD_FIFO_1", 17, 1 },
+		{ "CERR_PCMD_FIFO_0", 16, 1 },
+		{ "CERR_DATA_FIFO_3", 15, 1 },
+		{ "CERR_DATA_FIFO_2", 14, 1 },
+		{ "CERR_DATA_FIFO_1", 13, 1 },
+		{ "CERR_DATA_FIFO_0", 12, 1 },
+		{ "SE_CNT_MISMATCH_3", 11, 1 },
+		{ "SE_CNT_MISMATCH_2", 10, 1 },
+		{ "SE_CNT_MISMATCH_1", 9, 1 },
+		{ "SE_CNT_MISMATCH_0", 8, 1 },
+		{ "ENABLE_CTX_3", 7, 1 },
+		{ "ENABLE_CTX_2", 6, 1 },
+		{ "ENABLE_CTX_1", 5, 1 },
+		{ "ENABLE_CTX_0", 4, 1 },
+		{ "ENABLE_ALN_SDC_ERR_3", 3, 1 },
+		{ "ENABLE_ALN_SDC_ERR_2", 2, 1 },
+		{ "ENABLE_ALN_SDC_ERR_1", 1, 1 },
+		{ "ENABLE_ALN_SDC_ERR_0", 0, 1 },
+	{ "ULP_RX_INT_CAUSE", 0x19158, 0 },
+		{ "CERR_PCMD_FIFO_3", 19, 1 },
+		{ "CERR_PCMD_FIFO_2", 18, 1 },
+		{ "CERR_PCMD_FIFO_1", 17, 1 },
+		{ "CERR_PCMD_FIFO_0", 16, 1 },
+		{ "CERR_DATA_FIFO_3", 15, 1 },
+		{ "CERR_DATA_FIFO_2", 14, 1 },
+		{ "CERR_DATA_FIFO_1", 13, 1 },
+		{ "CERR_DATA_FIFO_0", 12, 1 },
+		{ "SE_CNT_MISMATCH_3", 11, 1 },
+		{ "SE_CNT_MISMATCH_2", 10, 1 },
+		{ "SE_CNT_MISMATCH_1", 9, 1 },
+		{ "SE_CNT_MISMATCH_0", 8, 1 },
+		{ "ENABLE_CTX_3", 7, 1 },
+		{ "ENABLE_CTX_2", 6, 1 },
+		{ "ENABLE_CTX_1", 5, 1 },
+		{ "ENABLE_CTX_0", 4, 1 },
+		{ "ENABLE_ALN_SDC_ERR_3", 3, 1 },
+		{ "ENABLE_ALN_SDC_ERR_2", 2, 1 },
+		{ "ENABLE_ALN_SDC_ERR_1", 1, 1 },
+		{ "ENABLE_ALN_SDC_ERR_0", 0, 1 },
+	{ "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
+	{ "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
+	{ "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
+		{ "IscsiTagMask", 6, 26 },
+	{ "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
+		{ "Hpz3", 24, 4 },
+		{ "Hpz2", 16, 4 },
+		{ "Hpz1", 8, 4 },
+		{ "Hpz0", 0, 4 },
+	{ "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
+	{ "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
+	{ "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
+		{ "TddpTagMask", 6, 26 },
+	{ "ULP_RX_TDDP_PSZ", 0x19178, 0 },
+		{ "Hpz3", 24, 4 },
+		{ "Hpz2", 16, 4 },
+		{ "Hpz1", 8, 4 },
+		{ "Hpz0", 0, 4 },
+	{ "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
+	{ "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
+	{ "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
+	{ "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
+	{ "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
+	{ "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
+	{ "ULP_RX_CTX_BASE", 0x19194, 0 },
+	{ "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
+		{ "CERR_PCMD_FIFO_3", 19, 1 },
+		{ "CERR_PCMD_FIFO_2", 18, 1 },
+		{ "CERR_PCMD_FIFO_1", 17, 1 },
+		{ "CERR_PCMD_FIFO_0", 16, 1 },
+		{ "CERR_DATA_FIFO_3", 15, 1 },
+		{ "CERR_DATA_FIFO_2", 14, 1 },
+		{ "CERR_DATA_FIFO_1", 13, 1 },
+		{ "CERR_DATA_FIFO_0", 12, 1 },
+		{ "SE_CNT_MISMATCH_3", 11, 1 },
+		{ "SE_CNT_MISMATCH_2", 10, 1 },
+		{ "SE_CNT_MISMATCH_1", 9, 1 },
+		{ "SE_CNT_MISMATCH_0", 8, 1 },
+		{ "ENABLE_CTX_3", 7, 1 },
+		{ "ENABLE_CTX_2", 6, 1 },
+		{ "ENABLE_CTX_1", 5, 1 },
+		{ "ENABLE_CTX_0", 4, 1 },
+		{ "ENABLE_ALN_SDC_ERR_3", 3, 1 },
+		{ "ENABLE_ALN_SDC_ERR_2", 2, 1 },
+		{ "ENABLE_ALN_SDC_ERR_1", 1, 1 },
+		{ "ENABLE_ALN_SDC_ERR_0", 0, 1 },
+	{ "ULP_RX_PERR_INJECT", 0x191a0, 0 },
+		{ "MemSel", 1, 7 },
+		{ "InjectDataErr", 0, 1 },
+	{ "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "ULP_RX_CTX_ACC_CH2", 0x191b4, 0 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "ULP_RX_CTX_ACC_CH3", 0x191b8, 0 },
+		{ "REQ", 21, 1 },
+		{ "WB", 20, 1 },
+		{ "TID", 0, 20 },
+	{ "ULP_RX_CTL2", 0x191bc, 0 },
+		{ "PCMD3Threshold", 24, 8 },
+		{ "PCMD2Threshold", 16, 8 },
+		{ "PCMD1Threshold", 8, 8 },
+		{ "PCMD0Threshold", 0, 8 },
+	{ "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
+		{ "ERR_CH3", 12, 4 },
+		{ "ERR_CH2", 8, 4 },
+		{ "ERR_CH1", 4, 4 },
+		{ "ERR_CH0", 0, 4 },
+	{ "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
+		{ "CLR_CH3", 12, 4 },
+		{ "CLR_CH2", 8, 4 },
+		{ "CLR_CH1", 4, 4 },
+		{ "CLR_CH0", 0, 4 },
+	{ "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
+		{ "SOP_CNT_OUT0", 28, 4 },
+		{ "EOP_CNT_OUT0", 24, 4 },
+		{ "SOP_CNT_AL0", 20, 4 },
+		{ "EOP_CNT_AL0", 16, 4 },
+		{ "SOP_CNT_MR0", 12, 4 },
+		{ "EOP_CNT_MR0", 8, 4 },
+		{ "SOP_CNT_IN0", 4, 4 },
+		{ "EOP_CNT_IN0", 0, 4 },
+	{ "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
+		{ "SOP_CNT_OUT1", 28, 4 },
+		{ "EOP_CNT_OUT1", 24, 4 },
+		{ "SOP_CNT_AL1", 20, 4 },
+		{ "EOP_CNT_AL1", 16, 4 },
+		{ "SOP_CNT_MR1", 12, 4 },
+		{ "EOP_CNT_MR1", 8, 4 },
+		{ "SOP_CNT_IN1", 4, 4 },
+		{ "EOP_CNT_IN1", 0, 4 },
+	{ "ULP_RX_DBG_CTL", 0x191e0, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG_L", 16, 1 },
+		{ "SEL_L", 0, 8 },
+	{ "ULP_RX_DBG_DATA", 0x191e4, 0 },
+	{ "ULP_RX_CQE_GEN_EN", 0x19250, 0 },
+		{ "Termimate_msg", 1, 1 },
+		{ "Terminate_with_err", 0, 1 },
+	{ "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 },
+	{ "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 },
+		{ "Tls_KeySizeConf", 26, 2 },
+		{ "iscsi_dcrc_error_cmp_en", 25, 1 },
+		{ "IscsiTagPI", 24, 1 },
+		{ "ddp_version_1", 22, 2 },
+		{ "ddp_version_0", 20, 2 },
+		{ "rdma_version_1", 18, 2 },
+		{ "rdma_version_0", 16, 2 },
+		{ "pbl_bound_check_w_pglen", 15, 1 },
+		{ "t10_offset_update_en", 13, 1 },
+		{ "ulp_insert_pi", 12, 1 },
+		{ "pdu_dpi", 11, 1 },
+		{ "iscsi_eff_offset_en", 10, 1 },
+		{ "iscsi_all_cmp_mode", 9, 1 },
+		{ "iscsi_enable_hdr_cmd", 8, 1 },
+		{ "iscsi_force_cmp_mode", 7, 1 },
+		{ "pio_rdma_send_rqe", 5, 1 },
+		{ "terminate_status_en", 4, 1 },
+		{ "multiple_pref_enable", 3, 1 },
+		{ "umudp_pbl_pref_enable", 2, 1 },
+		{ "rdma_pbl_pref_en", 1, 1 },
+		{ "sdc_crc_prot_en", 0, 1 },
+	{ "ULP_RX_CH_CGEN", 0x19260, 0 },
+		{ "BYPASS_CGEN", 28, 4 },
+		{ "TDDP_CGEN", 24, 4 },
+		{ "ISCSI_CGEN", 20, 4 },
+		{ "RDMA_CGEN", 16, 4 },
+		{ "CHANNEL_CGEN", 12, 4 },
+		{ "All_DataPath_CGEN", 8, 4 },
+		{ "T10Diff_DataPath_CGEN", 4, 4 },
+		{ "Rdma_DataPath_CGEN", 0, 4 },
+	{ "ULP_RX_CH_CGEN_1", 0x19264, 0 },
+		{ "NVMe_TCP_CGEN", 4, 4 },
+		{ "RoCE_CGEN", 0, 4 },
+	{ "ULP_RX_RFE_DISABLE", 0x19268, 0 },
+	{ "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 },
+	{ "ULP_RX_CGEN_GLOBAL", 0x19280, 0 },
+	{ "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 },
+		{ "clear_ctx_err_cnt3", 7, 1 },
+		{ "clear_ctx_err_cnt2", 6, 1 },
+		{ "clear_ctx_err_cnt1", 5, 1 },
+		{ "clear_ctx_err_cnt0", 4, 1 },
+		{ "skip_ma_req_en3", 3, 1 },
+		{ "skip_ma_req_en2", 2, 1 },
+		{ "skip_ma_req_en1", 1, 1 },
+		{ "skip_ma_req_en0", 0, 1 },
+	{ "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 },
+	{ "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 },
+	{ "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 },
+		{ "Rd_or_Term_msn_check_enable", 2, 1 },
+		{ "atomic_op_msn_check_enable", 1, 1 },
+		{ "send_msn_check_enable", 0, 1 },
+	{ "ULP_RX_SE_CNT_CH2", 0x19294, 0 },
+		{ "SOP_CNT_OUT2", 28, 4 },
+		{ "EOP_CNT_OUT2", 24, 4 },
+		{ "SOP_CNT_AL2", 20, 4 },
+		{ "EOP_CNT_AL2", 16, 4 },
+		{ "SOP_CNT_MR2", 12, 4 },
+		{ "EOP_CNT_MR2", 8, 4 },
+		{ "SOP_CNT_IN2", 4, 4 },
+		{ "EOP_CNT_IN2", 0, 4 },
+	{ "ULP_RX_SE_CNT_CH3", 0x19298, 0 },
+		{ "SOP_CNT_OUT3", 28, 4 },
+		{ "EOP_CNT_OUT3", 24, 4 },
+		{ "SOP_CNT_AL3", 20, 4 },
+		{ "EOP_CNT_AL3", 16, 4 },
+		{ "SOP_CNT_MR3", 12, 4 },
+		{ "EOP_CNT_MR3", 8, 4 },
+		{ "SOP_CNT_IN3", 4, 4 },
+		{ "EOP_CNT_IN3", 0, 4 },
+	{ "ULP_RX_CHNL2_CTX_ERROR_COUNT_PER_TID", 0x1929c, 0 },
+	{ "ULP_RX_CHNL3_CTX_ERROR_COUNT_PER_TID", 0x192a0, 0 },
+	{ "ULP_RX_TLS_PP_LLIMIT", 0x192a4, 0 },
+	{ "ULP_RX_TLS_PP_ULIMIT", 0x192a8, 0 },
+	{ "ULP_RX_TLS_KEY_LLIMIT", 0x192ac, 0 },
+	{ "ULP_RX_TLS_KEY_ULIMIT", 0x192b0, 0 },
+	{ "ULP_RX_TLS_CTL", 0x192bc, 0 },
+		{ "TlsPerrEn", 4, 1 },
+		{ "TlsDisableIFuse", 2, 1 },
+		{ "TlsDisableCFuse", 1, 1 },
+		{ "TlsDisable", 0, 1 },
+	{ "ULP_RX_RRQ_LLIMIT", 0x192c0, 0 },
+	{ "ULP_RX_RRQ_ULIMIT", 0x192c4, 0 },
+	{ "ULP_RX_NVME_TCP_STAG_LLIMIT", 0x192c8, 0 },
+	{ "ULP_RX_NVME_TCP_STAG_ULIMIT", 0x192cc, 0 },
+	{ "ULP_RX_NVME_TCP_RQ_LLIMIT", 0x192d0, 0 },
+	{ "ULP_RX_NVME_TCP_RQ_ULIMIT", 0x192d4, 0 },
+	{ "ULP_RX_NVME_TCP_PBL_LLIMIT", 0x192d8, 0 },
+	{ "ULP_RX_NVME_TCP_PBL_ULIMIT", 0x192dc, 0 },
+	{ "ULP_RX_NVME_TCP_MAX_LENGTH", 0x192e0, 0 },
+		{ "NVMe_TCP_Max_PLEN01", 24, 8 },
+		{ "NVMe_TCP_Max_PLEN23", 16, 8 },
+		{ "NVMe_TCP_Max_Cmd_PDU_Length", 0, 16 },
+	{ "ULP_RX_NVME_TCP_IQE_SIZE", 0x192e4, 0 },
+	{ "ULP_RX_NVME_TCP_NEW_PDU_TYPES", 0x192e8, 0 },
+	{ "ULP_RX_IWARP_PMOF_OPCODES_1", 0x192ec, 0 },
+		{ "Rdma_Verify_Response", 24, 5 },
+		{ "Rdma_Verify_Request", 16, 5 },
+		{ "Rdma_Flush_Response", 8, 5 },
+		{ "Rdma_Flush_Request", 0, 5 },
+	{ "ULP_RX_IWARP_PMOF_OPCODES_2", 0x192f0, 0 },
+		{ "Rdma_Send_With_SE_Immediate", 24, 5 },
+		{ "Rdma_Send_With_Immediate", 16, 5 },
+		{ "Rdma_Atomic_Write_Response", 8, 5 },
+		{ "Rdma_Atomic_Write_Request", 0, 5 },
+	{ "ULP_RX_INT_ENABLE_PCMD", 0x19300, 0 },
+		{ "ENABLE_PCMD_SFIFO_3", 30, 1 },
+		{ "ENABLE_PCMD_FIFO_3", 29, 1 },
+		{ "ENABLE_PCMD_DDP_HINT_3", 28, 1 },
+		{ "ENABLE_PCMD_TPT_3", 27, 1 },
+		{ "ENABLE_PCMD_DDP_3", 26, 1 },
+		{ "ENABLE_PCMD_MPAR_3", 25, 1 },
+		{ "ENABLE_PCMD_MPAC_3", 24, 1 },
+		{ "ENABLE_PCMD_SFIFO_2", 22, 1 },
+		{ "ENABLE_PCMD_FIFO_2", 21, 1 },
+		{ "ENABLE_PCMD_DDP_HINT_2", 20, 1 },
+		{ "ENABLE_PCMD_TPT_2", 19, 1 },
+		{ "ENABLE_PCMD_DDP_2", 18, 1 },
+		{ "ENABLE_PCMD_MPAR_2", 17, 1 },
+		{ "ENABLE_PCMD_MPAC_2", 16, 1 },
+		{ "ENABLE_PCMD_SFIFO_1", 14, 1 },
+		{ "ENABLE_PCMD_FIFO_1", 13, 1 },
+		{ "ENABLE_PCMD_DDP_HINT_1", 12, 1 },
+		{ "ENABLE_PCMD_TPT_1", 11, 1 },
+		{ "ENABLE_PCMD_DDP_1", 10, 1 },
+		{ "ENABLE_PCMD_MPAR_1", 9, 1 },
+		{ "ENABLE_PCMD_MPAC_1", 8, 1 },
+		{ "ENABLE_PCMD_SFIFO_0", 6, 1 },
+		{ "ENABLE_PCMD_FIFO_0", 5, 1 },
+		{ "ENABLE_PCMD_DDP_HINT_0", 4, 1 },
+		{ "ENABLE_PCMD_TPT_0", 3, 1 },
+		{ "ENABLE_PCMD_DDP_0", 2, 1 },
+		{ "ENABLE_PCMD_MPAR_0", 1, 1 },
+		{ "ENABLE_PCMD_MPAC_0", 0, 1 },
+	{ "ULP_RX_INT_CAUSE_PCMD", 0x19304, 0 },
+		{ "CAUSE_PCMD_SFIFO_3", 30, 1 },
+		{ "CAUSE_PCMD_FIFO_3", 29, 1 },
+		{ "CAUSE_PCMD_DDP_HINT_3", 28, 1 },
+		{ "CAUSE_PCMD_TPT_3", 27, 1 },
+		{ "CAUSE_PCMD_DDP_3", 26, 1 },
+		{ "CAUSE_PCMD_MPAR_3", 25, 1 },
+		{ "CAUSE_PCMD_MPAC_3", 24, 1 },
+		{ "CAUSE_PCMD_SFIFO_2", 22, 1 },
+		{ "CAUSE_PCMD_FIFO_2", 21, 1 },
+		{ "CAUSE_PCMD_DDP_HINT_2", 20, 1 },
+		{ "CAUSE_PCMD_TPT_2", 19, 1 },
+		{ "CAUSE_PCMD_DDP_2", 18, 1 },
+		{ "CAUSE_PCMD_MPAR_2", 17, 1 },
+		{ "CAUSE_PCMD_MPAC_2", 16, 1 },
+		{ "CAUSE_PCMD_SFIFO_1", 14, 1 },
+		{ "CAUSE_PCMD_FIFO_1", 13, 1 },
+		{ "CAUSE_PCMD_DDP_HINT_1", 12, 1 },
+		{ "CAUSE_PCMD_TPT_1", 11, 1 },
+		{ "CAUSE_PCMD_DDP_1", 10, 1 },
+		{ "CAUSE_PCMD_MPAR_1", 9, 1 },
+		{ "CAUSE_PCMD_MPAC_1", 8, 1 },
+		{ "CAUSE_PCMD_SFIFO_0", 6, 1 },
+		{ "CAUSE_PCMD_FIFO_0", 5, 1 },
+		{ "CAUSE_PCMD_DDP_HINT_0", 4, 1 },
+		{ "CAUSE_PCMD_TPT_0", 3, 1 },
+		{ "CAUSE_PCMD_DDP_0", 2, 1 },
+		{ "CAUSE_PCMD_MPAR_0", 1, 1 },
+		{ "CAUSE_PCMD_MPAC_0", 0, 1 },
+	{ "ULP_RX_PERR_ENABLE_PCMD", 0x19308, 0 },
+		{ "PERR_ENABLE_PCMD_SFIFO_3", 30, 1 },
+		{ "PERR_ENABLE_PCMD_FIFO_3", 29, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_HINT_3", 28, 1 },
+		{ "PERR_ENABLE_PCMD_TPT_3", 27, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_3", 26, 1 },
+		{ "PERR_ENABLE_PCMD_MPAR_3", 25, 1 },
+		{ "PERR_ENABLE_PCMD_MPAC_3", 24, 1 },
+		{ "PERR_ENABLE_PCMD_SFIFO_2", 22, 1 },
+		{ "PERR_ENABLE_PCMD_FIFO_2", 21, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_HINT_2", 20, 1 },
+		{ "PERR_ENABLE_PCMD_TPT_2", 19, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_2", 18, 1 },
+		{ "PERR_ENABLE_PCMD_MPAR_2", 17, 1 },
+		{ "PERR_ENABLE_PCMD_MPAC_2", 16, 1 },
+		{ "PERR_ENABLE_PCMD_SFIFO_1", 14, 1 },
+		{ "PERR_ENABLE_PCMD_FIFO_1", 13, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_HINT_1", 12, 1 },
+		{ "PERR_ENABLE_PCMD_TPT_1", 11, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_1", 10, 1 },
+		{ "PERR_ENABLE_PCMD_MPAR_1", 9, 1 },
+		{ "PERR_ENABLE_PCMD_MPAC_1", 8, 1 },
+		{ "PERR_ENABLE_PCMD_SFIFO_0", 6, 1 },
+		{ "PERR_ENABLE_PCMD_FIFO_0", 5, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_HINT_0", 4, 1 },
+		{ "PERR_ENABLE_PCMD_TPT_0", 3, 1 },
+		{ "PERR_ENABLE_PCMD_DDP_0", 2, 1 },
+		{ "PERR_ENABLE_PCMD_MPAR_0", 1, 1 },
+		{ "PERR_ENABLE_PCMD_MPAC_0", 0, 1 },
+	{ "ULP_RX_INT_ENABLE_DATA", 0x19310, 0 },
+		{ "ENABLE_DATA_SNOOP_3", 29, 1 },
+		{ "ENABLE_DATA_SFIFO_3", 28, 1 },
+		{ "ENABLE_DATA_FIFO_3", 27, 1 },
+		{ "ENABLE_DATA_DDP_3", 26, 1 },
+		{ "ENABLE_DATA_CTX_3", 25, 1 },
+		{ "ENABLE_DATA_PARSER_3", 24, 1 },
+		{ "ENABLE_DATA_SNOOP_2", 21, 1 },
+		{ "ENABLE_DATA_SFIFO_2", 20, 1 },
+		{ "ENABLE_DATA_FIFO_2", 19, 1 },
+		{ "ENABLE_DATA_DDP_2", 18, 1 },
+		{ "ENABLE_DATA_CTX_2", 17, 1 },
+		{ "ENABLE_DATA_PARSER_2", 16, 1 },
+		{ "ENABLE_DATA_SNOOP_1", 13, 1 },
+		{ "ENABLE_DATA_SFIFO_1", 12, 1 },
+		{ "ENABLE_DATA_FIFO_1", 11, 1 },
+		{ "ENABLE_DATA_DDP_1", 10, 1 },
+		{ "ENABLE_DATA_CTX_1", 9, 1 },
+		{ "ENABLE_DATA_PARSER_1", 8, 1 },
+		{ "ENABLE_DATA_SNOOP_0", 5, 1 },
+		{ "ENABLE_DATA_SFIFO_0", 4, 1 },
+		{ "ENABLE_DATA_FIFO_0", 3, 1 },
+		{ "ENABLE_DATA_DDP_0", 2, 1 },
+		{ "ENABLE_DATA_CTX_0", 1, 1 },
+		{ "ENABLE_DATA_PARSER_0", 0, 1 },
+	{ "ULP_RX_INT_CAUSE_DATA", 0x19314, 0 },
+		{ "CAUSE_DATA_SNOOP_3", 29, 1 },
+		{ "CAUSE_DATA_SFIFO_3", 28, 1 },
+		{ "CAUSE_DATA_FIFO_3", 27, 1 },
+		{ "CAUSE_DATA_DDP_3", 26, 1 },
+		{ "CAUSE_DATA_CTX_3", 25, 1 },
+		{ "CAUSE_DATA_PARSER_3", 24, 1 },
+		{ "CAUSE_DATA_SNOOP_2", 21, 1 },
+		{ "CAUSE_DATA_SFIFO_2", 20, 1 },
+		{ "CAUSE_DATA_FIFO_2", 19, 1 },
+		{ "CAUSE_DATA_DDP_2", 18, 1 },
+		{ "CAUSE_DATA_CTX_2", 17, 1 },
+		{ "CAUSE_DATA_PARSER_2", 16, 1 },
+		{ "CAUSE_DATA_SNOOP_1", 13, 1 },
+		{ "CAUSE_DATA_SFIFO_1", 12, 1 },
+		{ "CAUSE_DATA_FIFO_1", 11, 1 },
+		{ "CAUSE_DATA_DDP_1", 10, 1 },
+		{ "CAUSE_DATA_CTX_1", 9, 1 },
+		{ "CAUSE_DATA_PARSER_1", 8, 1 },
+		{ "CAUSE_DATA_SNOOP_0", 5, 1 },
+		{ "CAUSE_DATA_SFIFO_0", 4, 1 },
+		{ "CAUSE_DATA_FIFO_0", 3, 1 },
+		{ "CAUSE_DATA_DDP_0", 2, 1 },
+		{ "CAUSE_DATA_CTX_0", 1, 1 },
+		{ "CAUSE_DATA_PARSER_0", 0, 1 },
+	{ "ULP_RX_PERR_ENABLE_DATA", 0x19318, 0 },
+		{ "PERR_ENABLE_DATA_SNOOP_3", 29, 1 },
+		{ "PERR_ENABLE_DATA_SFIFO_3", 28, 1 },
+		{ "PERR_ENABLE_DATA_FIFO_3", 27, 1 },
+		{ "PERR_ENABLE_DATA_DDP_3", 26, 1 },
+		{ "PERR_ENABLE_DATA_CTX_3", 25, 1 },
+		{ "PERR_ENABLE_DATA_PARSER_3", 24, 1 },
+		{ "PERR_ENABLE_DATA_SNOOP_2", 21, 1 },
+		{ "PERR_ENABLE_DATA_SFIFO_2", 20, 1 },
+		{ "PERR_ENABLE_DATA_FIFO_2", 19, 1 },
+		{ "PERR_ENABLE_DATA_DDP_2", 18, 1 },
+		{ "PERR_ENABLE_DATA_CTX_2", 17, 1 },
+		{ "PERR_ENABLE_DATA_PARSER_2", 16, 1 },
+		{ "PERR_ENABLE_DATA_SNOOP_1", 13, 1 },
+		{ "PERR_ENABLE_DATA_SFIFO_1", 12, 1 },
+		{ "PERR_ENABLE_DATA_FIFO_1", 11, 1 },
+		{ "PERR_ENABLE_DATA_DDP_1", 10, 1 },
+		{ "PERR_ENABLE_DATA_CTX_1", 9, 1 },
+		{ "PERR_ENABLE_DATA_PARSER_1", 8, 1 },
+		{ "PERR_ENABLE_DATA_SNOOP_0", 5, 1 },
+		{ "PERR_ENABLE_DATA_SFIFO_0", 4, 1 },
+		{ "PERR_ENABLE_DATA_FIFO_0", 3, 1 },
+		{ "PERR_ENABLE_DATA_DDP_0", 2, 1 },
+		{ "PERR_ENABLE_DATA_CTX_0", 1, 1 },
+		{ "PERR_ENABLE_DATA_PARSER_0", 0, 1 },
+	{ "ULP_RX_INT_ENABLE_ARB", 0x19320, 0 },
+		{ "ENABLE_ARB_PBL_PF_3", 27, 1 },
+		{ "ENABLE_ARB_PF_3", 26, 1 },
+		{ "ENABLE_ARB_TPT_PF_3", 25, 1 },
+		{ "ENABLE_ARB_F_3", 24, 1 },
+		{ "ENABLE_ARB_PBL_PF_2", 19, 1 },
+		{ "ENABLE_ARB_PF_2", 18, 1 },
+		{ "ENABLE_ARB_TPT_PF_2", 17, 1 },
+		{ "ENABLE_ARB_F_2", 16, 1 },
+		{ "ENABLE_ARB_PBL_PF_1", 11, 1 },
+		{ "ENABLE_ARB_PF_1", 10, 1 },
+		{ "ENABLE_ARB_TPT_PF_1", 9, 1 },
+		{ "ENABLE_ARB_F_1", 8, 1 },
+		{ "ENABLE_ARB_PBL_PF_0", 3, 1 },
+		{ "ENABLE_ARB_PF_0", 2, 1 },
+		{ "ENABLE_ARB_TPT_PF_0", 1, 1 },
+		{ "ENABLE_ARB_F_0", 0, 1 },
+	{ "ULP_RX_INT_CAUSE_ARB", 0x19324, 0 },
+		{ "CAUSE_ARB_PBL_PF_3", 27, 1 },
+		{ "CAUSE_ARB_PF_3", 26, 1 },
+		{ "CAUSE_ARB_TPT_PF_3", 25, 1 },
+		{ "CAUSE_ARB_F_3", 24, 1 },
+		{ "CAUSE_ARB_PBL_PF_2", 19, 1 },
+		{ "CAUSE_ARB_PF_2", 18, 1 },
+		{ "CAUSE_ARB_TPT_PF_2", 17, 1 },
+		{ "CAUSE_ARB_F_2", 16, 1 },
+		{ "CAUSE_ARB_PBL_PF_1", 11, 1 },
+		{ "CAUSE_ARB_PF_1", 10, 1 },
+		{ "CAUSE_ARB_TPT_PF_1", 9, 1 },
+		{ "CAUSE_ARB_F_1", 8, 1 },
+		{ "CAUSE_ARB_PBL_PF_0", 3, 1 },
+		{ "CAUSE_ARB_PF_0", 2, 1 },
+		{ "CAUSE_ARB_TPT_PF_0", 1, 1 },
+		{ "CAUSE_ARB_F_0", 0, 1 },
+	{ "ULP_RX_PERR_ENABLE_ARB", 0x19328, 0 },
+		{ "PERR_ENABLE_ARB_PBL_PF_3", 27, 1 },
+		{ "PERR_ENABLE_ARB_PF_3", 26, 1 },
+		{ "PERR_ENABLE_ARB_TPT_PF_3", 25, 1 },
+		{ "PERR_ENABLE_ARB_F_3", 24, 1 },
+		{ "PERR_ENABLE_ARB_PBL_PF_2", 19, 1 },
+		{ "PERR_ENABLE_ARB_PF_2", 18, 1 },
+		{ "PERR_ENABLE_ARB_TPT_PF_2", 17, 1 },
+		{ "PERR_ENABLE_ARB_F_2", 16, 1 },
+		{ "PERR_ENABLE_ARB_PBL_PF_1", 11, 1 },
+		{ "PERR_ENABLE_ARB_PF_1", 10, 1 },
+		{ "PERR_ENABLE_ARB_TPT_PF_1", 9, 1 },
+		{ "PERR_ENABLE_ARB_F_1", 8, 1 },
+		{ "PERR_ENABLE_ARB_PBL_PF_0", 3, 1 },
+		{ "PERR_ENABLE_ARB_PF_0", 2, 1 },
+		{ "PERR_ENABLE_ARB_TPT_PF_0", 1, 1 },
+		{ "PERR_ENABLE_ARB_F_0", 0, 1 },
+	{ "ULP_RX_INT_ENABLE_INTERFACE", 0x191c0, 0 },
+		{ "ENABLE_ULPRX2SBT_RspPerr", 31, 1 },
+		{ "ENABLE_ULPRX2MA_RspPerr", 30, 1 },
+		{ "ENABME_Pio_Bus_Perr", 29, 1 },
+		{ "ENABLE_PM2ULP_SnoopData_3", 19, 1 },
+		{ "ENABLE_PM2ULP_SnoopData_2", 18, 1 },
+		{ "ENABLE_PM2ULP_SnoopData_1", 17, 1 },
+		{ "ENABLE_PM2ULP_SnoopData_0", 16, 1 },
+		{ "ENABLE_TLS2ULP_Data_3", 15, 1 },
+		{ "ENABLE_TLS2ULP_Data_2", 14, 1 },
+		{ "ENABLE_TLS2ULP_Data_1", 13, 1 },
+		{ "ENABLE_TLS2ULP_Data_0", 12, 1 },
+		{ "ENABLE_TLS2ULP_PLenData_3", 11, 1 },
+		{ "ENABLE_TLS2ULP_PLenData_2", 10, 1 },
+		{ "ENABLE_TLS2ULP_PLenData_1", 9, 1 },
+		{ "ENABLE_TLS2ULP_PLenData_0", 8, 1 },
+		{ "ENABLE_PM2ULP_DATA_3", 7, 1 },
+		{ "ENABLE_PM2ULP_DATA_2", 6, 1 },
+		{ "ENABLE_PM2ULP_DATA_1", 5, 1 },
+		{ "ENABLE_PM2ULP_DATA_0", 4, 1 },
+		{ "ENABLE_TP2ULP_PCMD_3", 3, 1 },
+		{ "ENABLE_TP2ULP_PCMD_2", 2, 1 },
+		{ "ENABLE_TP2ULP_PCMD_1", 1, 1 },
+		{ "ENABLE_TP2ULP_PCMD_0", 0, 1 },
+	{ "ULP_RX_INT_CAUSE_INTERFACE", 0x191c4, 0 },
+		{ "CAUSE_ULPRX2SBT_RspPerr", 31, 1 },
+		{ "CAUSE_ULPRX2MA_RspPerr", 30, 1 },
+		{ "CAUSE_Pio_Bus_Perr", 29, 1 },
+		{ "CAUSE_PM2ULP_SnoopData_3", 19, 1 },
+		{ "CAUSE_PM2ULP_SnoopData_2", 18, 1 },
+		{ "CAUSE_PM2ULP_SnoopData_1", 17, 1 },
+		{ "CAUSE_PM2ULP_SnoopData_0", 16, 1 },
+		{ "CAUSE_TLS2ULP_Data_3", 15, 1 },
+		{ "CAUSE_TLS2ULP_Data_2", 14, 1 },
+		{ "CAUSE_TLS2ULP_Data_1", 13, 1 },
+		{ "CAUSE_TLS2ULP_Data_0", 12, 1 },
+		{ "CAUSE_TLS2ULP_PLenData_3", 11, 1 },
+		{ "CAUSE_TLS2ULP_PLenData_2", 10, 1 },
+		{ "CAUSE_TLS2ULP_PLenData_1", 9, 1 },
+		{ "CAUSE_TLS2ULP_PLenData_0", 8, 1 },
+		{ "CAUSE_PM2ULP_DATA_3", 7, 1 },
+		{ "CAUSE_PM2ULP_DATA_2", 6, 1 },
+		{ "CAUSE_PM2ULP_DATA_1", 5, 1 },
+		{ "CAUSE_PM2ULP_DATA_0", 4, 1 },
+		{ "CAUSE_TP2ULP_PCMD_3", 3, 1 },
+		{ "CAUSE_TP2ULP_PCMD_2", 2, 1 },
+		{ "CAUSE_TP2ULP_PCMD_1", 1, 1 },
+		{ "CAUSE_TP2ULP_PCMD_0", 0, 1 },
+	{ "ULP_RX_PERR_ENABLE_INTERFACE", 0x191c8, 0 },
+		{ "PERR_ULPRX2SBT_RspPerr", 31, 1 },
+		{ "PERR_ULPRX2MA_RspPerr", 30, 1 },
+		{ "PERR_Pio_Bus_Perr", 29, 1 },
+		{ "PERR_PM2ULP_SnoopData_3", 19, 1 },
+		{ "PERR_PM2ULP_SnoopData_2", 18, 1 },
+		{ "PERR_PM2ULP_SnoopData_1", 17, 1 },
+		{ "PERR_PM2ULP_SnoopData_0", 16, 1 },
+		{ "PERR_TLS2ULP_Data_3", 15, 1 },
+		{ "PERR_TLS2ULP_Data_2", 14, 1 },
+		{ "PERR_TLS2ULP_Data_1", 13, 1 },
+		{ "PERR_TLS2ULP_Data_0", 12, 1 },
+		{ "PERR_TLS2ULP_PLenData_3", 11, 1 },
+		{ "PERR_TLS2ULP_PLenData_2", 10, 1 },
+		{ "PERR_TLS2ULP_PLenData_1", 9, 1 },
+		{ "PERR_TLS2ULP_PLenData_0", 8, 1 },
+		{ "PERR_PM2ULP_DATA_3", 7, 1 },
+		{ "PERR_PM2ULP_DATA_2", 6, 1 },
+		{ "PERR_PM2ULP_DATA_1", 5, 1 },
+		{ "PERR_PM2ULP_DATA_0", 4, 1 },
+		{ "PERR_TP2ULP_PCMD_3", 3, 1 },
+		{ "PERR_TP2ULP_PCMD_2", 2, 1 },
+		{ "PERR_TP2ULP_PCMD_1", 1, 1 },
+		{ "PERR_TP2ULP_PCMD_0", 0, 1 },
+	{ "ULP_RX_CTL1", 0x19330, 0 },
+		{ "iSCSI_Ctl2", 27, 1 },
+		{ "iSCSI_Ctl1", 26, 1 },
+		{ "iSCSI_Ctl0", 25, 1 },
+		{ "NVMe_TCP_Data_Alignment", 16, 9 },
+		{ "NVMe_TCP_Invld_Msg_Dis", 14, 2 },
+		{ "NVMe_TCP_ddp_pdu_chk_type", 13, 1 },
+		{ "T10_Config_Enb", 12, 1 },
+		{ "NVMe_TCP_Colour_Enb", 10, 2 },
+		{ "RoCE_send_rqe", 8, 1 },
+		{ "RDMA_Invld_Msg_Dis", 6, 2 },
+		{ "RoCE_Invld_Msg_Dis", 4, 2 },
+		{ "Mem_Addr_Ctrl", 2, 2 },
+		{ "Enb_32K_PDU", 1, 1 },
+		{ "c2h_success_wo_last_pdu_chk_dis", 0, 1 },
+	{ "ULP_RX_TLS_IND_CMD", 0x19348, 0 },
+	{ "ULP_RX_TLS_IND_DATA", 0x1934c, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_sf_regs[] = {
+	{ "SF_DATA", 0x193f8, 0 },
+	{ "SF_OP", 0x193fc, 0 },
+		{ "Busy", 31, 1 },
+		{ "En32bAddr", 30, 1 },
+		{ "RegDbg_Mode", 10, 1 },
+		{ "RegDbg_Sel", 9, 1 },
+		{ "QuadWrEnable", 8, 1 },
+		{ "Enter4B", 7, 1 },
+		{ "Exit4B", 6, 1 },
+		{ "QuadReadDisable", 5, 1 },
+		{ "Lock", 4, 1 },
+		{ "Cont", 3, 1 },
+		{ "Num_of_bytes", 1, 2 },
+		{ "Op", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_pl_regs[] = {
+	{ "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1e3c8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1e7c8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1ebc8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1efc0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1efc4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1efc8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1f3c8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1f7c8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1fbc8, 0 },
+	{ "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
+		{ "SW", 3, 1 },
+		{ "CIM", 1, 1 },
+		{ "MPS", 0, 1 },
+	{ "PL_PF_CTL", 0x1ffc8, 0 },
+	{ "PL_WHOAMI", 0x19400, 0 },
+		{ "PortxMap", 24, 3 },
+		{ "SourceBus", 16, 2 },
+		{ "SourcePF", 9, 3 },
+		{ "IsVF", 8, 1 },
+		{ "VFID", 0, 8 },
+	{ "PL_PERR_CAUSE", 0x19404, 0 },
+		{ "CRYPTO_KEY", 31, 1 },
+		{ "CRYPTO1", 30, 1 },
+		{ "CRYPTO0", 29, 1 },
+		{ "GCACHE", 28, 1 },
+		{ "ARM", 27, 1 },
+		{ "ULP_TX", 26, 1 },
+		{ "SGE", 25, 1 },
+		{ "HMA", 24, 1 },
+		{ "CPL_SWITCH", 23, 1 },
+		{ "ULP_RX", 22, 1 },
+		{ "PM_RX", 21, 1 },
+		{ "PM_TX", 20, 1 },
+		{ "MA", 19, 1 },
+		{ "TP", 18, 1 },
+		{ "LE", 17, 1 },
+		{ "EDC1", 16, 1 },
+		{ "EDC0", 15, 1 },
+		{ "MC1", 14, 1 },
+		{ "MC0", 13, 1 },
+		{ "PCIE", 12, 1 },
+		{ "UART", 11, 1 },
+		{ "PMU", 10, 1 },
+		{ "MAC", 9, 1 },
+		{ "SMB", 8, 1 },
+		{ "SF", 7, 1 },
+		{ "PL", 6, 1 },
+		{ "NCSI", 5, 1 },
+		{ "MPS", 4, 1 },
+		{ "MI", 3, 1 },
+		{ "DBG", 2, 1 },
+		{ "I2CM", 1, 1 },
+		{ "CIM", 0, 1 },
+	{ "PL_PERR_ENABLE", 0x19408, 0 },
+		{ "CRYPTO_KEY", 31, 1 },
+		{ "CRYPTO1", 30, 1 },
+		{ "CRYPTO0", 29, 1 },
+		{ "GCACHE", 28, 1 },
+		{ "ARM", 27, 1 },
+		{ "ULP_TX", 26, 1 },
+		{ "SGE", 25, 1 },
+		{ "HMA", 24, 1 },
+		{ "CPL_SWITCH", 23, 1 },
+		{ "ULP_RX", 22, 1 },
+		{ "PM_RX", 21, 1 },
+		{ "PM_TX", 20, 1 },
+		{ "MA", 19, 1 },
+		{ "TP", 18, 1 },
+		{ "LE", 17, 1 },
+		{ "EDC1", 16, 1 },
+		{ "EDC0", 15, 1 },
+		{ "MC1", 14, 1 },
+		{ "MC0", 13, 1 },
+		{ "PCIE", 12, 1 },
+		{ "UART", 11, 1 },
+		{ "PMU", 10, 1 },
+		{ "MAC", 9, 1 },
+		{ "SMB", 8, 1 },
+		{ "SF", 7, 1 },
+		{ "PL", 6, 1 },
+		{ "NCSI", 5, 1 },
+		{ "MPS", 4, 1 },
+		{ "MI", 3, 1 },
+		{ "DBG", 2, 1 },
+		{ "I2CM", 1, 1 },
+		{ "CIM", 0, 1 },
+	{ "PL_INT_CAUSE", 0x1940c, 0 },
+		{ "FLR", 31, 1 },
+		{ "SW_CIM", 30, 1 },
+		{ "ULP_TX", 29, 1 },
+		{ "SGE", 28, 1 },
+		{ "HMA", 27, 1 },
+		{ "CPL_SWITCH", 26, 1 },
+		{ "ULP_RX", 25, 1 },
+		{ "PM_RX", 24, 1 },
+		{ "PM_TX", 23, 1 },
+		{ "MA", 22, 1 },
+		{ "TP", 21, 1 },
+		{ "LE", 20, 1 },
+		{ "EDC1", 19, 1 },
+		{ "EDC0", 18, 1 },
+		{ "MC1", 17, 1 },
+		{ "MC0", 16, 1 },
+		{ "PCIE", 15, 1 },
+		{ "UART", 14, 1 },
+		{ "PMU", 13, 1 },
+		{ "MAC3", 12, 1 },
+		{ "MAC2", 11, 1 },
+		{ "MAC1", 10, 1 },
+		{ "MAC0", 9, 1 },
+		{ "SMB", 8, 1 },
+		{ "SF", 7, 1 },
+		{ "PL", 6, 1 },
+		{ "NCSI", 5, 1 },
+		{ "MPS", 4, 1 },
+		{ "MI", 3, 1 },
+		{ "DBG", 2, 1 },
+		{ "I2CM", 1, 1 },
+		{ "CIM", 0, 1 },
+	{ "PL_INT_ENABLE", 0x19410, 0 },
+		{ "FLR", 31, 1 },
+		{ "SW_CIM", 30, 1 },
+		{ "ULP_TX", 29, 1 },
+		{ "SGE", 28, 1 },
+		{ "HMA", 27, 1 },
+		{ "CPL_SWITCH", 26, 1 },
+		{ "ULP_RX", 25, 1 },
+		{ "PM_RX", 24, 1 },
+		{ "PM_TX", 23, 1 },
+		{ "MA", 22, 1 },
+		{ "TP", 21, 1 },
+		{ "LE", 20, 1 },
+		{ "EDC1", 19, 1 },
+		{ "EDC0", 18, 1 },
+		{ "MC1", 17, 1 },
+		{ "MC0", 16, 1 },
+		{ "PCIE", 15, 1 },
+		{ "UART", 14, 1 },
+		{ "PMU", 13, 1 },
+		{ "MAC3", 12, 1 },
+		{ "MAC2", 11, 1 },
+		{ "MAC1", 10, 1 },
+		{ "MAC0", 9, 1 },
+		{ "SMB", 8, 1 },
+		{ "SF", 7, 1 },
+		{ "PL", 6, 1 },
+		{ "NCSI", 5, 1 },
+		{ "MPS", 4, 1 },
+		{ "MI", 3, 1 },
+		{ "DBG", 2, 1 },
+		{ "I2CM", 1, 1 },
+		{ "CIM", 0, 1 },
+	{ "PL_INT_MAP0", 0x19414, 0 },
+		{ "MapNCSI", 16, 9 },
+		{ "MapDefault", 0, 9 },
+	{ "PL_INT_MAP1", 0x19418, 0 },
+		{ "MapMAC1", 16, 9 },
+		{ "MapMAC0", 0, 9 },
+	{ "PL_INT_MAP2", 0x1941c, 0 },
+		{ "MapMAC3", 16, 9 },
+		{ "MapMAC2", 0, 9 },
+	{ "PL_INT_MAP3", 0x19420, 0 },
+		{ "MapMI", 16, 9 },
+		{ "MapSMB", 0, 9 },
+	{ "PL_INT_MAP4", 0x19424, 0 },
+		{ "MapDBG", 16, 9 },
+		{ "MapI2CM", 0, 9 },
+	{ "PL_RST", 0x19428, 0 },
+		{ "AutoPciePause", 4, 1 },
+		{ "FatalPerrEn", 3, 1 },
+		{ "SWIntCIM", 2, 1 },
+		{ "PIORst", 1, 1 },
+		{ "PIORstMode", 0, 1 },
+	{ "PL_PL_INT_CAUSE", 0x19430, 0 },
+		{ "PL_BusPerr", 6, 1 },
+		{ "FatalPerr", 4, 1 },
+		{ "InvalidAccess", 3, 1 },
+		{ "Timeout", 2, 1 },
+		{ "PLErr", 1, 1 },
+	{ "PL_PL_INT_ENABLE", 0x19434, 0 },
+		{ "PL_BusPerr", 6, 1 },
+		{ "FatalPerr", 4, 1 },
+		{ "InvalidAccess", 3, 1 },
+		{ "Timeout", 2, 1 },
+		{ "PLErr", 1, 1 },
+	{ "PL_PL_PERR_ENABLE", 0x19438, 0 },
+		{ "PL_BusPerr", 6, 1 },
+	{ "PL_REV", 0x1943c, 0 },
+		{ "ChipID", 4, 4 },
+		{ "Rev", 0, 4 },
+	{ "PL_PCIE_LINK", 0x19440, 0 },
+		{ "SPEEDMS", 30, 1 },
+		{ "LN0_AESTAT", 27, 3 },
+		{ "LN0_AECMD", 24, 3 },
+		{ "StateCfgInitF", 16, 8 },
+		{ "StateCfgInit", 12, 4 },
+		{ "PHY_STATUS", 10, 1 },
+		{ "SPEED", 8, 2 },
+		{ "PERstTimeout", 7, 1 },
+		{ "LTSSMEnable", 6, 1 },
+		{ "LTSSM", 0, 6 },
+	{ "PL_PCIE_CTL_STAT", 0x19444, 0 },
+		{ "Status", 16, 16 },
+		{ "Control", 0, 16 },
+	{ "PL_SEMAPHORE_CTL", 0x1944c, 0 },
+		{ "LockStatus", 16, 8 },
+		{ "OwnerOverride", 8, 1 },
+		{ "EnablePF", 0, 8 },
+	{ "PL_SEMAPHORE_LOCK", 0x19450, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x19454, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x19458, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x19460, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x19464, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x19468, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
+		{ "Lock", 31, 1 },
+		{ "SourceBus", 3, 2 },
+		{ "SourcePF", 0, 3 },
+	{ "PL_PORTX_MAP", 0x19474, 0 },
+		{ "MAP7", 28, 3 },
+		{ "MAP6", 24, 3 },
+		{ "MAP5", 20, 3 },
+		{ "MAP4", 16, 3 },
+		{ "MAP3", 12, 3 },
+		{ "MAP2", 8, 3 },
+		{ "MAP1", 4, 3 },
+		{ "MAP0", 0, 3 },
+	{ "PL_INT_CAUSE2", 0x19478, 0 },
+		{ "CRYPTO_KEY", 4, 1 },
+		{ "CRYPTO1", 3, 1 },
+		{ "CRYPTO0", 2, 1 },
+		{ "GCACHE", 1, 1 },
+		{ "ARM", 0, 1 },
+	{ "PL_INT_ENABLE2", 0x1947c, 0 },
+		{ "CRYPTO_KEY", 4, 1 },
+		{ "CRYPTO1", 3, 1 },
+		{ "CRYPTO0", 2, 1 },
+		{ "GCACHE", 1, 1 },
+		{ "ARM", 0, 1 },
+	{ "PL_ER_CMD", 0x19488, 0 },
+		{ "ER_ADDR", 2, 30 },
+	{ "PL_ER_DATA", 0x1948c, 0 },
+	{ "PL_VF_SLICE_L", 0x19490, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x19498, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x194a0, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x194a8, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x194b0, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x194b8, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x194c0, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_L", 0x194c8, 0 },
+		{ "LimitAddr", 16, 10 },
+		{ "BaseAddr", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x19494, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x1949c, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x194a4, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x194ac, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x194b4, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x194bc, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x194c4, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_VF_SLICE_H", 0x194cc, 0 },
+		{ "ModIndx", 16, 3 },
+		{ "ModOffset", 0, 10 },
+	{ "PL_TIMEOUT_CTL", 0x194f0, 0 },
+		{ "PerrCapture", 16, 1 },
+		{ "Timeout", 0, 16 },
+	{ "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
+		{ "Addr", 2, 28 },
+	{ "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
+		{ "Valid", 31, 1 },
+		{ "ValidPerr", 30, 1 },
+		{ "Write", 22, 1 },
+		{ "Bus", 20, 2 },
+		{ "PF", 16, 3 },
+		{ "VFID", 0, 9 },
+	{ NULL }
+};
+
+struct reg_info t7_le_regs[] = {
+	{ "LE_DB_ID", 0x19c00, 0 },
+	{ "LE_DB_CONFIG", 0x19c04, 0 },
+		{ "CacheBypass", 28, 1 },
+		{ "CHK_FUL_TUP_ZERO", 27, 1 },
+		{ "PRI_HASH", 26, 1 },
+		{ "EXTN_HASH_IPV4", 25, 1 },
+		{ "PROTOCOLMASKEN", 24, 1 },
+		{ "SRVRSRAMEN", 22, 1 },
+		{ "HASHEN", 20, 1 },
+		{ "ASLIPCOMPEN_IPV4", 18, 1 },
+		{ "BUILD", 16, 1 },
+		{ "IGNR_TUP_ZERO", 9, 1 },
+		{ "IGNR_LIP_ZERO", 8, 1 },
+		{ "CLCAM_INIT_BUSY", 7, 1 },
+		{ "CLCAM_INIT", 6, 1 },
+		{ "MTCAM_INIT_BUSY", 5, 1 },
+		{ "MTCAM_INIT", 4, 1 },
+		{ "REGION_EN", 0, 4 },
+	{ "LE_DB_EXEC_CTRL", 0x19c08, 0 },
+		{ "TPDB_IF_PAUSE_ACK", 10, 1 },
+		{ "TPDB_IF_PAUSE_REQ", 9, 1 },
+		{ "ERRSTOP_EN", 8, 1 },
+		{ "CMDLIMIT", 0, 8 },
+	{ "LE_DB_PS_CTRL", 0x19c0c, 0 },
+		{ "SRAMDEEPSLEEP_STAT", 11, 1 },
+		{ "CLTCAMDEEPSLEEP_STAT", 10, 1 },
+		{ "TCAMDEEPSLEEP_STAT", 9, 1 },
+		{ "SRAMDEEPSLEEP", 8, 1 },
+		{ "CLTCAMDEEPSLEEP", 7, 1 },
+		{ "TCAMDEEPSLEEP", 6, 1 },
+		{ "SRVRAMCLKOFF", 5, 1 },
+		{ "HASHCLKOFF", 4, 1 },
+	{ "LE_DB_ACTIVE_TABLE_START_INDEX", 0x19c10, 0 },
+	{ "LE_DB_NORM_FILT_TABLE_START_INDEX", 0x19c14, 0 },
+	{ "LE_DB_SRVR_START_INDEX", 0x19c18, 0 },
+	{ "LE_DB_HPRI_FILT_TABLE_START_INDEX", 0x19c1c, 0 },
+	{ "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
+	{ "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
+	{ "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 },
+	{ "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 },
+	{ "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
+		{ "RspCnt", 16, 16 },
+		{ "ReqCnt", 0, 16 },
+	{ "LE_HASH_COLLISION", 0x19fc4, 0 },
+	{ "LE_GLOBAL_COLLISION", 0x19fc8, 0 },
+	{ "LE_DB_HASH_CONFIG", 0x19c28, 0 },
+		{ "NUMHASHBKT", 20, 5 },
+		{ "HASHTBLSIZE", 3, 17 },
+	{ "LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES", 0x19c2c, 0 },
+	{ "LE_DB_MAX_NUM_HASH_ENTRIES", 0x19c70, 0 },
+	{ "LE_DB_RSP_CODE_0", 0x19c74, 0 },
+		{ "SUCCESS", 25, 5 },
+		{ "TCAM_ACTV_SUCC", 20, 5 },
+		{ "HASH_ACTV_SUCC", 15, 5 },
+		{ "TCAM_SRVR_HIT", 10, 5 },
+		{ "SRAM_SRVR_HIT", 5, 5 },
+		{ "TCAM_ACTV_HIT", 0, 5 },
+	{ "LE_DB_RSP_CODE_1", 0x19c78, 0 },
+		{ "HASH_ACTV_HIT", 25, 5 },
+		{ "MISS", 20, 5 },
+		{ "NORM_FILT_HIT", 15, 5 },
+		{ "HPRI_FILT_HIT", 10, 5 },
+		{ "ACTV_OPEN_ERR", 5, 5 },
+		{ "ACTV_FULL_ERR", 0, 5 },
+	{ "LE_DB_RSP_CODE_2", 0x19c7c, 0 },
+		{ "SRCH_RGN_HIT", 25, 5 },
+		{ "CLIP_FAIL", 20, 5 },
+		{ "LIP_ZERO_ERR", 15, 5 },
+		{ "UNKNOWN_CMD", 10, 5 },
+		{ "CMD_TID_ERR", 5, 5 },
+		{ "INTERNAL_ERR", 0, 5 },
+	{ "LE_DB_RSP_CODE_3", 0x19c80, 0 },
+		{ "SRAM_SRVR_HIT_ACTF", 25, 5 },
+		{ "TCAM_SRVR_HIT_ACTF", 20, 5 },
+		{ "INVLDRD", 15, 5 },
+		{ "TUPLZERO", 10, 5 },
+	{ "LE_DB_HASH_TBL_BASE_ADDR", 0x19c30, 0 },
+		{ "HASHTBLADDR", 4, 28 },
+	{ "LE_TCAM_SIZE", 0x19c34, 0 },
+		{ "MLL_mask", 2, 1 },
+		{ "SIZE", 0, 2 },
+	{ "LE_DB_INT_ENABLE", 0x19c38, 0 },
+		{ "CacheIntPerr", 31, 1 },
+		{ "CacheSramPerr", 30, 1 },
+		{ "ClipSubErr", 29, 1 },
+		{ "ClCamFifoerr", 28, 1 },
+		{ "HashTblMemCrcErr", 27, 1 },
+		{ "CTcamInvldEnt", 26, 1 },
+		{ "TcamInvldEnt", 25, 1 },
+		{ "TotCntErr", 24, 1 },
+		{ "CmdPrsrIntErr", 23, 1 },
+		{ "CmdTidErr", 22, 1 },
+		{ "ActRgnFull", 21, 1 },
+		{ "ActCntIPv6Tzero", 20, 1 },
+		{ "ActCntIPv4Tzero", 19, 1 },
+		{ "ActCntIPv6zero", 18, 1 },
+		{ "ActCntIPv4zero", 17, 1 },
+		{ "MaifwrIntPerr", 16, 1 },
+		{ "HashTblMemAccErr", 15, 1 },
+		{ "TcamCrcErr", 14, 1 },
+		{ "TcamIntPerr", 13, 1 },
+		{ "VfSramPerr", 12, 1 },
+		{ "SrvSramPerr", 11, 1 },
+		{ "SsramIntPerr", 10, 1 },
+		{ "ClCamIntPerr", 9, 1 },
+		{ "ClCamCrcParErr", 8, 1 },
+		{ "HashTblAccFail", 7, 1 },
+		{ "TcamAccFail", 6, 1 },
+		{ "SrvSramAccFail", 5, 1 },
+		{ "ClipTcamAccFail", 4, 1 },
+		{ "UnknownCmd", 3, 1 },
+		{ "LIP0", 2, 1 },
+		{ "LIPMiss", 1, 1 },
+		{ "PipelineErr", 0, 1 },
+	{ "LE_DB_INT_CAUSE", 0x19c3c, 0 },
+		{ "CacheIntPerr", 31, 1 },
+		{ "CacheSramPerr", 30, 1 },
+		{ "ClipSubErr", 29, 1 },
+		{ "ClCamFifoerr", 28, 1 },
+		{ "HashTblMemCrcErr", 27, 1 },
+		{ "CTcamInvldEnt", 26, 1 },
+		{ "TcamInvldEnt", 25, 1 },
+		{ "TotCntErr", 24, 1 },
+		{ "CmdPrsrIntErr", 23, 1 },
+		{ "CmdTidErr", 22, 1 },
+		{ "ActRgnFull", 21, 1 },
+		{ "ActCntIPv6Tzero", 20, 1 },
+		{ "ActCntIPv4Tzero", 19, 1 },
+		{ "ActCntIPv6zero", 18, 1 },
+		{ "ActCntIPv4zero", 17, 1 },
+		{ "MaifwrIntPerr", 16, 1 },
+		{ "HashTblMemAccErr", 15, 1 },
+		{ "TcamCrcErr", 14, 1 },
+		{ "TcamIntPerr", 13, 1 },
+		{ "VfSramPerr", 12, 1 },
+		{ "SrvSramPerr", 11, 1 },
+		{ "SsramIntPerr", 10, 1 },
+		{ "ClCamIntPerr", 9, 1 },
+		{ "ClCamCrcParErr", 8, 1 },
+		{ "HashTblAccFail", 7, 1 },
+		{ "TcamAccFail", 6, 1 },
+		{ "SrvSramAccFail", 5, 1 },
+		{ "ClipTcamAccFail", 4, 1 },
+		{ "UnknownCmd", 3, 1 },
+		{ "LIP0", 2, 1 },
+		{ "LIPMiss", 1, 1 },
+		{ "PipelineErr", 0, 1 },
+	{ "LE_PERR_ENABLE", 0x19cf8, 0 },
+		{ "CacheIntPerr", 31, 1 },
+		{ "CacheSramPerr", 30, 1 },
+		{ "BkChkPeriod", 22, 8 },
+		{ "TcamBkChkEn", 21, 1 },
+		{ "MaifwrIntPerr", 16, 1 },
+		{ "HashTblMemAccErr", 15, 1 },
+		{ "TcamCrcErr", 14, 1 },
+		{ "TcamIntPerr", 13, 1 },
+		{ "VfSramPerr", 12, 1 },
+		{ "SrvSramPerr", 11, 1 },
+		{ "SsramIntPerr", 10, 1 },
+		{ "ClCamIntPerr", 9, 1 },
+		{ "ClCamCrcParErr", 8, 1 },
+		{ "HashTblAccFail", 7, 1 },
+		{ "TcamAccFail", 6, 1 },
+		{ "SrvSramAccFail", 5, 1 },
+		{ "ClipTcamAccFail", 4, 1 },
+		{ "ClCamFifoerr", 2, 1 },
+		{ "HashTblMemCrcErr", 1, 1 },
+		{ "PipelineErr", 0, 1 },
+	{ "LE_DB_ERR_CMD_TID", 0x19c48, 0 },
+		{ "ERR_CID", 22, 8 },
+		{ "ERR_PROT", 20, 2 },
+		{ "ERR_TID", 0, 20 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c50, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c54, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c58, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c5c, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c60, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c64, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c68, 0 },
+	{ "LE_DB_DBG_MATCH_DATA_MASK", 0x19c6c, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19ca0, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19ca4, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19ca8, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19cac, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19cb0, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19cb4, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19cb8, 0 },
+	{ "LE_DB_DBG_MATCH_DATA", 0x19cbc, 0 },
+	{ "LE_CMM_CONFIG", 0x19cc0, 0 },
+		{ "GlFl", 31, 1 },
+		{ "WrCntIdle", 16, 15 },
+		{ "RdThreshold", 8, 6 },
+		{ "WrThrLevel2", 7, 1 },
+		{ "WrThrLevel1", 6, 1 },
+		{ "WrThrThreshEn", 5, 1 },
+		{ "WrThrThresh", 0, 5 },
+	{ "LE_CACHE_DBG", 0x19cc4, 0 },
+	{ "LE_CACHE_WR_ALL_CNT", 0x19cc8, 0 },
+	{ "LE_CACHE_WR_HIT_CNT", 0x19ccc, 0 },
+	{ "LE_CACHE_RD_ALL_CNT", 0x19cd0, 0 },
+	{ "LE_CACHE_RD_HIT_CNT", 0x19cd4, 0 },
+	{ "LE_CACHE_MC_WR_CNT", 0x19cd8, 0 },
+	{ "LE_CACHE_MC_RD_CNT", 0x19cdc, 0 },
+	{ "LE_DB_DBG_MATCH_CMD_IDX_MASK", 0x19c40, 0 },
+		{ "CMD_CMP_MASK", 20, 5 },
+		{ "TID_CMP_MASK", 0, 20 },
+	{ "LE_DB_DBG_MATCH_CMD_IDX_DATA", 0x19c44, 0 },
+		{ "CMD_CMP", 20, 5 },
+		{ "TID_CMP", 0, 20 },
+	{ "LE_IND_ADDR", 0x19ce8, 0 },
+	{ "LE_IND_DATA", 0x19cec, 0 },
+	{ "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
+		{ "DBGICMDRANGE", 22, 3 },
+		{ "DBGICMDMSKREAD", 21, 1 },
+		{ "DBGICMDSEARCH", 20, 1 },
+		{ "DBGICMDREAD", 19, 1 },
+		{ "DBGICMDLEARN", 18, 1 },
+		{ "DBGICMDWRITE", 17, 1 },
+		{ "DBGICMDIPv6", 16, 1 },
+		{ "DBGICMDBUSY", 3, 1 },
+		{ "DBGICMDSTRT", 2, 1 },
+		{ "DBGICMDMODE", 0, 2 },
+	{ "LE_DB_DBGI_REQ_CMD", 0x19cf4, 0 },
+		{ "DBGICMD", 20, 4 },
+		{ "DBGITID", 0, 20 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d2c, 0 },
+	{ "LE_DB_DBGI_REQ_DATA", 0x19d30, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d7c, 0 },
+	{ "LE_DB_DBGI_REQ_MASK", 0x19d80, 0 },
+	{ "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
+		{ "DBGIRspTid", 12, 20 },
+		{ "DBGIRspMsg", 8, 4 },
+		{ "DBGIRspLearn", 2, 1 },
+		{ "DBGIRspHit", 1, 1 },
+		{ "DBGIRspValid", 0, 1 },
+	{ "LE_DBG_SEL", 0x19d98, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
+	{ "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
+	{ "LE_DB_TCAM_TID_BASE", 0x19df0, 0 },
+	{ "LE_DB_CLCAM_TID_BASE", 0x19df4, 0 },
+	{ "LE_DB_HASH_TID_BASE", 0x19df8, 0 },
+	{ "LE_DB_SSRAM_TID_BASE", 0x19dfc, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
+	{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb0, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb4, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb8, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV4", 0x19ebc, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
+	{ "LE_DB_HASH_MASK_GEN_IPV6", 0x19ee0, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee4, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee8, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19eec, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef0, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef4, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f04, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f08, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f0c, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f10, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f14, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f18, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f1c, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f20, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f24, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f28, 0 },
+	{ "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f2c, 0 },
+	{ "LE_DB_SRVR_SRAM_CONFIG", 0x19f34, 0 },
+		{ "PRI_HFILT", 4, 1 },
+		{ "PRI_SRVR", 3, 1 },
+		{ "PRI_FILT", 2, 1 },
+		{ "SRVRINITBUSY", 1, 1 },
+		{ "SRVRINIT", 0, 1 },
+	{ "LE_DB_SRVR_VF_SRCH_TABLE_CTRL", 0x19f38, 0 },
+		{ "VFLUTBUSY", 10, 1 },
+		{ "VFLUTSTART", 9, 1 },
+		{ "RDWR", 8, 1 },
+		{ "VFINDEX", 0, 8 },
+	{ "LE_DB_SRVR_VF_SRCH_TABLE_DATA", 0x19f3c, 0 },
+		{ "SRCHHADDR", 12, 12 },
+		{ "SRCHLADDR", 0, 12 },
+	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 },
+	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 },
+	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 },
+	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 },
+	{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa4, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa8, 0 },
+	{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fac, 0 },
+	{ "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 },
+	{ "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 },
+	{ "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 },
+	{ "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 },
+	{ "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 },
+	{ "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 },
+	{ "LE_TCAM_BIST_CTRL", 0x19fb0, 0 },
+		{ "rst_cb", 31, 1 },
+		{ "cb_start", 0, 28 },
+	{ "LE_TCAM_BIST_CB_PASS", 0x19fb4, 0 },
+	{ "LE_TCAM_BIST_CB_BUSY", 0x19fbc, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_ncsi_regs[] = {
+	{ "NCSI_PORT_CFGREG", 0x1a000, 0 },
+		{ "WireEn", 28, 4 },
+		{ "strp_crc", 24, 4 },
+		{ "rx_halt", 22, 1 },
+		{ "flush_rx_fifo", 21, 1 },
+		{ "hw_arb_en", 20, 1 },
+		{ "soft_pkg_sel", 19, 1 },
+		{ "err_discard_en", 18, 1 },
+		{ "max_pkt_size", 4, 14 },
+		{ "rx_byte_swap", 3, 1 },
+		{ "tx_byte_swap", 2, 1 },
+		{ "xgmac0_en", 0, 1 },
+	{ "NCSI_RST_CTRL", 0x1a004, 0 },
+		{ "mac_ref_rst", 2, 1 },
+		{ "mac_rx_rst", 1, 1 },
+		{ "mac_tx_rst", 0, 1 },
+	{ "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
+	{ "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
+		{ "CHO_SADDR_EN", 31, 1 },
+		{ "CH0_SADDR_HIGH", 0, 16 },
+	{ "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
+	{ "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
+		{ "CH1_SADDR_EN", 31, 1 },
+		{ "CH1_SADDR_HIGH", 0, 16 },
+	{ "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
+	{ "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
+		{ "CH2_SADDR_EN", 31, 1 },
+		{ "CH2_SADDR_HIGH", 0, 16 },
+	{ "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
+	{ "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
+		{ "CH3_SADDR_EN", 31, 1 },
+		{ "CH3_SADDR_HIGH", 0, 16 },
+	{ "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
+	{ "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
+	{ "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
+	{ "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
+	{ "NCSI_MPS_HDR_LO", 0x1a040, 0 },
+	{ "NCSI_MPS_HDR_HI", 0x1a044, 0 },
+	{ "NCSI_CTL", 0x1a048, 0 },
+		{ "STRIP_OVLAN", 3, 1 },
+		{ "bmc_drop_non_bc", 2, 1 },
+		{ "bmc_rx_fwd_all", 1, 1 },
+		{ "FWD_BMC", 0, 1 },
+	{ "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
+	{ "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
+	{ "NCSI_RX_ERR_CNT", 0x1a054, 0 },
+	{ "NCSI_RX_OF_CNT", 0x1a058, 0 },
+	{ "NCSI_RX_MS_CNT", 0x1a05c, 0 },
+	{ "NCSI_RX_IE_CNT", 0x1a060, 0 },
+	{ "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
+		{ "MPS2CIM_CNT", 16, 9 },
+		{ "MPS2BMC_CNT", 0, 9 },
+	{ "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
+		{ "CIM2MPS_CNT", 16, 9 },
+		{ "CIM2BMC_CNT", 0, 9 },
+	{ "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
+	{ "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
+	{ "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
+	{ "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
+	{ "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
+	{ "NCSI_LA_RDPTR", 0x1a0c0, 0 },
+	{ "NCSI_LA_RDDATA", 0x1a0c4, 0 },
+	{ "NCSI_LA_WRPTR", 0x1a0c8, 0 },
+	{ "NCSI_LA_RESERVED", 0x1a0cc, 0 },
+	{ "NCSI_LA_CTL", 0x1a0d0, 0 },
+	{ "NCSI_INT_ENABLE", 0x1a0d4, 0 },
+		{ "CIM2NC_perr", 9, 1 },
+		{ "CIM_DM_prty_err", 8, 1 },
+		{ "MPS_DM_prty_err", 7, 1 },
+		{ "token", 6, 1 },
+		{ "arb_done", 5, 1 },
+		{ "arb_started", 4, 1 },
+		{ "WOL", 3, 1 },
+		{ "MACInt", 2, 1 },
+		{ "TXFIFO_prty_err", 1, 1 },
+		{ "RXFIFO_prty_err", 0, 1 },
+	{ "NCSI_INT_CAUSE", 0x1a0d8, 0 },
+		{ "CIM2NC_perr", 9, 1 },
+		{ "CIM_DM_prty_err", 8, 1 },
+		{ "MPS_DM_prty_err", 7, 1 },
+		{ "token", 6, 1 },
+		{ "arb_done", 5, 1 },
+		{ "arb_started", 4, 1 },
+		{ "WOL", 3, 1 },
+		{ "MACInt", 2, 1 },
+		{ "TXFIFO_prty_err", 1, 1 },
+		{ "RXFIFO_prty_err", 0, 1 },
+	{ "NCSI_STATUS", 0x1a0dc, 0 },
+		{ "Master", 1, 1 },
+		{ "arb_status", 0, 1 },
+	{ "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
+	{ "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
+	{ "NCSI_PAUSE_WM", 0x1a0ec, 0 },
+		{ "PauseHWM", 16, 11 },
+		{ "PauseLWM", 0, 11 },
+	{ "NCSI_DEBUG", 0x1a0f0, 0 },
+		{ "TxFIFO_empty", 4, 1 },
+		{ "TxFIFO_full", 3, 1 },
+		{ "PKG_ID", 0, 3 },
+	{ "NCSI_PERR_INJECT", 0x1a0f4, 0 },
+		{ "MemSel", 1, 1 },
+		{ "InjectDataErr", 0, 1 },
+	{ "NCSI_PERR_ENABLE", 0x1a0f8, 0 },
+		{ "CIM2NC_perr", 9, 1 },
+		{ "CIM_DM_prty_err", 8, 1 },
+		{ "MPS_DM_prty_err", 7, 1 },
+		{ "TXFIFO_prty_err", 1, 1 },
+		{ "RXFIFO_prty_err", 0, 1 },
+	{ "NCSI_MODE_SEL", 0x1a0fc, 0 },
+	{ "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
+		{ "TxSndZeroPause", 12, 1 },
+		{ "TxSndPause", 11, 1 },
+		{ "TxStop", 10, 1 },
+		{ "TxStart", 9, 1 },
+		{ "BackPress", 8, 1 },
+		{ "StatWrEn", 7, 1 },
+		{ "IncrStat", 6, 1 },
+		{ "ClearStat", 5, 1 },
+		{ "EnMgmtPort", 4, 1 },
+		{ "TxEn", 3, 1 },
+		{ "RxEn", 2, 1 },
+		{ "LoopLocal", 1, 1 },
+		{ "LoopPHY", 0, 1 },
+	{ "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
+		{ "PClkDiv128", 22, 1 },
+		{ "CopyPause", 21, 1 },
+		{ "NonStdPreOK", 20, 1 },
+		{ "NoFCS", 19, 1 },
+		{ "RxEnHalfDup", 18, 1 },
+		{ "NoCopyFCS", 17, 1 },
+		{ "LenChkEn", 16, 1 },
+		{ "RxBufOffset", 14, 2 },
+		{ "PauseEn", 13, 1 },
+		{ "RetryTest", 12, 1 },
+		{ "PClkDiv", 10, 2 },
+		{ "ExtClass", 9, 1 },
+		{ "En1536Frame", 8, 1 },
+		{ "UCastHashEn", 7, 1 },
+		{ "MCastHashEn", 6, 1 },
+		{ "RxBCastDis", 5, 1 },
+		{ "CopyAllFrames", 4, 1 },
+		{ "JumboEn", 3, 1 },
+		{ "SerEn", 2, 1 },
+		{ "FullDuplex", 1, 1 },
+		{ "Speed", 0, 1 },
+	{ "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
+		{ "PHYMgmtStatus", 2, 1 },
+		{ "MDIStatus", 1, 1 },
+		{ "LinkStatus", 0, 1 },
+	{ "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
+		{ "UnderrunErr", 6, 1 },
+		{ "TxComplete", 5, 1 },
+		{ "BufferExhausted", 4, 1 },
+		{ "TxProgress", 3, 1 },
+		{ "RetryLimit", 2, 1 },
+		{ "ColEvent", 1, 1 },
+		{ "UsedBitRead", 0, 1 },
+	{ "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
+		{ "RxBufQPtr", 2, 30 },
+	{ "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
+		{ "TxBufQPtr", 2, 30 },
+	{ "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
+		{ "RxOverrunErr", 2, 1 },
+		{ "FrameRcvd", 1, 1 },
+		{ "NoRxBuf", 0, 1 },
+	{ "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
+		{ "PauseTimeZero", 13, 1 },
+		{ "PauseRcvd", 12, 1 },
+		{ "HRespNotOK", 11, 1 },
+		{ "RxOverrun", 10, 1 },
+		{ "LinkChange", 9, 1 },
+		{ "TxComplete", 7, 1 },
+		{ "TxBufErr", 6, 1 },
+		{ "RetryLimitErr", 5, 1 },
+		{ "TxBufUnderrun", 4, 1 },
+		{ "TxUsedBitRead", 3, 1 },
+		{ "RxUsedBitRead", 2, 1 },
+		{ "RxComplete", 1, 1 },
+		{ "MgmtFrameSent", 0, 1 },
+	{ "NCSI_MACB_INT_EN", 0x1a128, 0 },
+		{ "PauseTimeZero", 13, 1 },
+		{ "PauseRcvd", 12, 1 },
+		{ "HRespNotOK", 11, 1 },
+		{ "RxOverrun", 10, 1 },
+		{ "LinkChange", 9, 1 },
+		{ "TxComplete", 7, 1 },
+		{ "TxBufErr", 6, 1 },
+		{ "RetryLimitErr", 5, 1 },
+		{ "TxBufUnderrun", 4, 1 },
+		{ "TxUsedBitRead", 3, 1 },
+		{ "RxUsedBitRead", 2, 1 },
+		{ "RxComplete", 1, 1 },
+		{ "MgmtFrameSent", 0, 1 },
+	{ "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
+		{ "PauseTimeZero", 13, 1 },
+		{ "PauseRcvd", 12, 1 },
+		{ "HRespNotOK", 11, 1 },
+		{ "RxOverrun", 10, 1 },
+		{ "LinkChange", 9, 1 },
+		{ "TxComplete", 7, 1 },
+		{ "TxBufErr", 6, 1 },
+		{ "RetryLimitErr", 5, 1 },
+		{ "TxBufUnderrun", 4, 1 },
+		{ "TxUsedBitRead", 3, 1 },
+		{ "RxUsedBitRead", 2, 1 },
+		{ "RxComplete", 1, 1 },
+		{ "MgmtFrameSent", 0, 1 },
+	{ "NCSI_MACB_INT_MASK", 0x1a130, 0 },
+		{ "PauseTimeZero", 13, 1 },
+		{ "PauseRcvd", 12, 1 },
+		{ "HRespNotOK", 11, 1 },
+		{ "RxOverrun", 10, 1 },
+		{ "LinkChange", 9, 1 },
+		{ "TxComplete", 7, 1 },
+		{ "TxBufErr", 6, 1 },
+		{ "RetryLimitErr", 5, 1 },
+		{ "TxBufUnderrun", 4, 1 },
+		{ "TxUsedBitRead", 3, 1 },
+		{ "RxUsedBitRead", 2, 1 },
+		{ "RxComplete", 1, 1 },
+		{ "MgmtFrameSent", 0, 1 },
+	{ "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
+	{ "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
+	{ "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
+	{ "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
+	{ "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
+	{ "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
+	{ "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
+	{ "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
+	{ "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
+	{ "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
+	{ "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
+	{ "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
+	{ "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
+	{ "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
+	{ "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
+	{ "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
+	{ "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
+	{ "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
+	{ "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
+	{ "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
+	{ "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
+	{ "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
+	{ "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
+	{ "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
+	{ "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
+	{ "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
+	{ "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
+	{ "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
+	{ "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
+	{ "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
+	{ "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
+	{ "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
+	{ "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
+	{ "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
+	{ "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
+		{ "UserProgInput", 16, 16 },
+		{ "UserProgOutput", 0, 16 },
+	{ "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
+		{ "MCHashEn", 19, 1 },
+		{ "Specific1En", 18, 1 },
+		{ "ARPEn", 17, 1 },
+		{ "MagicPktEn", 16, 1 },
+		{ "ARPIPAddr", 0, 16 },
+	{ "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
+		{ "PartRef", 16, 16 },
+		{ "DesRev", 0, 16 },
+	{ "NCSI_TX_CTRL", 0x1a200, 0 },
+		{ "SendPause", 2, 1 },
+		{ "SendZeroPause", 1, 1 },
+		{ "TxEn", 0, 1 },
+	{ "NCSI_TX_CFG", 0x1a204, 0 },
+		{ "CfgClkSpeed", 2, 3 },
+		{ "StretchMode", 1, 1 },
+		{ "TxPauseEn", 0, 1 },
+	{ "NCSI_TX_PAUSE_QUANTA", 0x1a208, 0 },
+	{ "NCSI_RX_CTRL", 0x1a20c, 0 },
+	{ "NCSI_RX_CFG", 0x1a210, 0 },
+		{ "Con802_3Preamble", 12, 1 },
+		{ "EnNon802_3Preamble", 11, 1 },
+		{ "CopyPreamble", 10, 1 },
+		{ "DisPauseFrames", 9, 1 },
+		{ "En1536BFrames", 8, 1 },
+		{ "EnJumbo", 7, 1 },
+		{ "RmFCS", 6, 1 },
+		{ "DisNonVlan", 5, 1 },
+		{ "EnExtMatch", 4, 1 },
+		{ "EnHashUcast", 3, 1 },
+		{ "EnHashMcast", 2, 1 },
+		{ "DisBCast", 1, 1 },
+		{ "CopyAllFrames", 0, 1 },
+	{ "NCSI_RX_HASH_LOW", 0x1a214, 0 },
+	{ "NCSI_RX_HASH_HIGH", 0x1a218, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_1", 0x1a21c, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_1", 0x1a220, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_2", 0x1a224, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_2", 0x1a228, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_3", 0x1a22c, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_3", 0x1a230, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_4", 0x1a234, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_4", 0x1a238, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_5", 0x1a23c, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_5", 0x1a240, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_6", 0x1a244, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_6", 0x1a248, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_7", 0x1a24c, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_7", 0x1a250, 0 },
+	{ "NCSI_RX_EXACT_MATCH_LOW_8", 0x1a254, 0 },
+	{ "NCSI_RX_EXACT_MATCH_HIGH_8", 0x1a258, 0 },
+	{ "NCSI_RX_TYPE_MATCH_1", 0x1a25c, 0 },
+		{ "EnTypeMatch", 31, 1 },
+		{ "type", 0, 16 },
+	{ "NCSI_RX_TYPE_MATCH_2", 0x1a260, 0 },
+		{ "EnTypeMatch", 31, 1 },
+		{ "type", 0, 16 },
+	{ "NCSI_RX_TYPE_MATCH_3", 0x1a264, 0 },
+		{ "EnTypeMatch", 31, 1 },
+		{ "type", 0, 16 },
+	{ "NCSI_RX_TYPE_MATCH_4", 0x1a268, 0 },
+		{ "EnTypeMatch", 31, 1 },
+		{ "type", 0, 16 },
+	{ "NCSI_INT_STATUS", 0x1a26c, 0 },
+		{ "XGMIIExtInt", 10, 1 },
+		{ "LinkFaultChange", 9, 1 },
+		{ "PhyFrameComplete", 8, 1 },
+		{ "PauseFrameTxmt", 7, 1 },
+		{ "PauseCntrTimeOut", 6, 1 },
+		{ "Non0PauseRcvd", 5, 1 },
+		{ "StatOFlow", 4, 1 },
+		{ "TxErrFIFO", 3, 1 },
+		{ "TxUFlow", 2, 1 },
+		{ "FrameTxmt", 1, 1 },
+		{ "FrameRcvd", 0, 1 },
+	{ "NCSI_XGM_INT_MASK", 0x1a270, 0 },
+		{ "XGMIIExtInt", 10, 1 },
+		{ "LinkFaultChange", 9, 1 },
+		{ "PhyFrameComplete", 8, 1 },
+		{ "PauseFrameTxmt", 7, 1 },
+		{ "PauseCntrTimeOut", 6, 1 },
+		{ "Non0PauseRcvd", 5, 1 },
+		{ "StatOFlow", 4, 1 },
+		{ "TxErrFIFO", 3, 1 },
+		{ "TxUFlow", 2, 1 },
+		{ "FrameTxmt", 1, 1 },
+		{ "FrameRcvd", 0, 1 },
+	{ "NCSI_XGM_INT_ENABLE", 0x1a274, 0 },
+		{ "XGMIIExtInt", 10, 1 },
+		{ "LinkFaultChange", 9, 1 },
+		{ "PhyFrameComplete", 8, 1 },
+		{ "PauseFrameTxmt", 7, 1 },
+		{ "PauseCntrTimeOut", 6, 1 },
+		{ "Non0PauseRcvd", 5, 1 },
+		{ "StatOFlow", 4, 1 },
+		{ "TxErrFIFO", 3, 1 },
+		{ "TxUFlow", 2, 1 },
+		{ "FrameTxmt", 1, 1 },
+		{ "FrameRcvd", 0, 1 },
+	{ "NCSI_XGM_INT_DISABLE", 0x1a278, 0 },
+		{ "XGMIIExtInt", 10, 1 },
+		{ "LinkFaultChange", 9, 1 },
+		{ "PhyFrameComplete", 8, 1 },
+		{ "PauseFrameTxmt", 7, 1 },
+		{ "PauseCntrTimeOut", 6, 1 },
+		{ "Non0PauseRcvd", 5, 1 },
+		{ "StatOFlow", 4, 1 },
+		{ "TxErrFIFO", 3, 1 },
+		{ "TxUFlow", 2, 1 },
+		{ "FrameTxmt", 1, 1 },
+		{ "FrameRcvd", 0, 1 },
+	{ "NCSI_TX_PAUSE_TIMER", 0x1a27c, 0 },
+	{ "NCSI_STAT_CTRL", 0x1a280, 0 },
+		{ "ReadSnpShot", 4, 1 },
+		{ "TakeSnpShot", 3, 1 },
+		{ "ClrStats", 2, 1 },
+		{ "IncrStats", 1, 1 },
+		{ "EnTestModeWr", 0, 1 },
+	{ "NCSI_RXFIFO_CFG", 0x1a284, 0 },
+		{ "RxFIFO_empty", 31, 1 },
+		{ "RxFIFO_full", 30, 1 },
+		{ "RxFIFOPauseHWM", 17, 12 },
+		{ "RxFIFOPauseLWM", 5, 12 },
+		{ "ForcedPause", 4, 1 },
+		{ "ExternLoopback", 3, 1 },
+		{ "RxByteSwap", 2, 1 },
+		{ "RxStrFrwrd", 1, 1 },
+		{ "DisErrFrames", 0, 1 },
+	{ "NCSI_TXFIFO_CFG", 0x1a288, 0 },
+		{ "TxFIFO_empty", 31, 1 },
+		{ "TxFIFO_full", 30, 1 },
+		{ "UnderunFix", 22, 1 },
+		{ "EnDropPkt", 21, 1 },
+		{ "TxIPG", 13, 8 },
+		{ "TxFIFOThresh", 4, 9 },
+		{ "InternLoopback", 3, 1 },
+		{ "TxByteSwap", 2, 1 },
+		{ "DisCRC", 1, 1 },
+		{ "DisPreAmble", 0, 1 },
+	{ "NCSI_SLOW_TIMER", 0x1a28c, 0 },
+		{ "PauseSlowTimerEn", 31, 1 },
+		{ "PauseSlowTimer", 0, 20 },
+	{ "NCSI_PAUSE_TIMER", 0x1a290, 0 },
+	{ "NCSI_XAUI_PCS_TEST", 0x1a294, 0 },
+		{ "TestPattern", 1, 2 },
+		{ "EnTest", 0, 1 },
+	{ "NCSI_RGMII_CTRL", 0x1a298, 0 },
+		{ "PhAlignFIFOThresh", 1, 2 },
+		{ "TxClk90Shift", 0, 1 },
+	{ "NCSI_RGMII_IMP", 0x1a29c, 0 },
+		{ "CalReset", 8, 1 },
+		{ "CalUpdate", 7, 1 },
+		{ "ImpSetUpdate", 6, 1 },
+		{ "RGMIIImpPD", 3, 3 },
+		{ "RGMIIImpPU", 0, 3 },
+	{ "NCSI_RX_MAX_PKT_SIZE", 0x1a2a8, 0 },
+		{ "RxMaxFramerSize", 17, 14 },
+		{ "RxEnErrorGather", 16, 1 },
+		{ "RxEnSingleFlit", 15, 1 },
+		{ "RxEnFramer", 14, 1 },
+		{ "RxMaxPktSize", 0, 14 },
+	{ "NCSI_RESET_CTRL", 0x1a2ac, 0 },
+		{ "XGMAC_STOP_EN", 4, 1 },
+		{ "XG2G_Reset_", 3, 1 },
+		{ "RGMII_Reset_", 2, 1 },
+		{ "PCS_Reset_", 1, 1 },
+		{ "MAC_Reset_", 0, 1 },
+	{ "NCSI_XAUI1G_CTRL", 0x1a2b0, 0 },
+	{ "NCSI_SERDES_LANE_CTRL", 0x1a2b4, 0 },
+		{ "LaneReversal", 8, 1 },
+		{ "TxPolarity", 4, 4 },
+		{ "RxPolarity", 0, 4 },
+	{ "NCSI_PORT_CFG", 0x1a2b8, 0 },
+		{ "SafeSpeedChange", 4, 1 },
+		{ "ClkDivReset_", 3, 1 },
+		{ "PortSpeed", 1, 2 },
+		{ "EnRGMII", 0, 1 },
+	{ "NCSI_EPIO_DATA0", 0x1a2c0, 0 },
+	{ "NCSI_EPIO_DATA1", 0x1a2c4, 0 },
+	{ "NCSI_EPIO_DATA2", 0x1a2c8, 0 },
+	{ "NCSI_EPIO_DATA3", 0x1a2cc, 0 },
+	{ "NCSI_EPIO_OP", 0x1a2d0, 0 },
+		{ "PIO_Ready", 31, 1 },
+		{ "PIO_WrRd", 24, 1 },
+		{ "PIO_Address", 0, 8 },
+	{ "NCSI_XGMAC0_INT_ENABLE", 0x1a2d4, 0 },
+		{ "XAUIPCSDECErr", 24, 1 },
+		{ "RGMIIRxFIFOOverflow", 23, 1 },
+		{ "RGMIIRxFIFOUnderflow", 22, 1 },
+		{ "RxPktSizeError", 21, 1 },
+		{ "WOLPatDetected", 20, 1 },
+		{ "TXFIFO_prty_err", 17, 3 },
+		{ "RXFIFO_prty_err", 14, 3 },
+		{ "TXFIFO_underrun", 13, 1 },
+		{ "RXFIFO_overflow", 12, 1 },
+		{ "SERDESBISTErr", 8, 4 },
+		{ "SERDESLowSigChange", 4, 4 },
+		{ "XAUIPCSCTCErr", 3, 1 },
+		{ "XAUIPCSAlignChange", 2, 1 },
+		{ "RGMIILinkStsChange", 1, 1 },
+		{ "xgm_int", 0, 1 },
+	{ "NCSI_XGMAC0_INT_CAUSE", 0x1a2d8, 0 },
+		{ "XAUIPCSDECErr", 24, 1 },
+		{ "RGMIIRxFIFOOverflow", 23, 1 },
+		{ "RGMIIRxFIFOUnderflow", 22, 1 },
+		{ "RxPktSizeError", 21, 1 },
+		{ "WOLPatDetected", 20, 1 },
+		{ "TXFIFO_prty_err", 17, 3 },
+		{ "RXFIFO_prty_err", 14, 3 },
+		{ "TXFIFO_underrun", 13, 1 },
+		{ "RXFIFO_overflow", 12, 1 },
+		{ "SERDESBISTErr", 8, 4 },
+		{ "SERDESLowSigChange", 4, 4 },
+		{ "XAUIPCSCTCErr", 3, 1 },
+		{ "XAUIPCSAlignChange", 2, 1 },
+		{ "RGMIILinkStsChange", 1, 1 },
+		{ "xgm_int", 0, 1 },
+	{ "NCSI_XAUI_ACT_CTRL", 0x1a2dc, 0 },
+		{ "TxEn", 1, 1 },
+		{ "RxEn", 0, 1 },
+	{ "NCSI_SERDES_CTRL0", 0x1a2e0, 0 },
+		{ "IntSerLPBK3", 27, 1 },
+		{ "IntSerLPBK2", 26, 1 },
+		{ "IntSerLPBK1", 25, 1 },
+		{ "IntSerLPBK0", 24, 1 },
+		{ "Reset3", 23, 1 },
+		{ "Reset2", 22, 1 },
+		{ "Reset1", 21, 1 },
+		{ "Reset0", 20, 1 },
+		{ "Pwrdn3", 19, 1 },
+		{ "Pwrdn2", 18, 1 },
+		{ "Pwrdn1", 17, 1 },
+		{ "Pwrdn0", 16, 1 },
+		{ "ResetPLL23", 15, 1 },
+		{ "ResetPLL01", 14, 1 },
+		{ "PW23", 12, 2 },
+		{ "PW01", 10, 2 },
+		{ "Deq", 6, 4 },
+		{ "Dtx", 2, 4 },
+		{ "LoDrv", 1, 1 },
+		{ "HiDrv", 0, 1 },
+	{ "NCSI_SERDES_CTRL1", 0x1a2e4, 0 },
+		{ "FmOffset3", 19, 5 },
+		{ "FmOffsetEn3", 18, 1 },
+		{ "FmOffset2", 13, 5 },
+		{ "FmOffsetEn2", 12, 1 },
+		{ "FmOffset1", 7, 5 },
+		{ "FmOffsetEn1", 6, 1 },
+		{ "FmOffset0", 1, 5 },
+		{ "FmOffsetEn0", 0, 1 },
+	{ "NCSI_SERDES_CTRL2", 0x1a2e8, 0 },
+		{ "DnIn3", 11, 1 },
+		{ "UpIn3", 10, 1 },
+		{ "RxSlave3", 9, 1 },
+		{ "DnIn2", 8, 1 },
+		{ "UpIn2", 7, 1 },
+		{ "RxSlave2", 6, 1 },
+		{ "DnIn1", 5, 1 },
+		{ "UpIn1", 4, 1 },
+		{ "RxSlave1", 3, 1 },
+		{ "DnIn0", 2, 1 },
+		{ "UpIn0", 1, 1 },
+		{ "RxSlave0", 0, 1 },
+	{ "NCSI_SERDES_CTRL3", 0x1a2ec, 0 },
+		{ "ExtBISTChkErrClr3", 31, 1 },
+		{ "ExtBISTChkEn3", 30, 1 },
+		{ "ExtBISTGenEn3", 29, 1 },
+		{ "ExtBISTPat3", 26, 3 },
+		{ "ExtParReset3", 25, 1 },
+		{ "ExtParLPBK3", 24, 1 },
+		{ "ExtBISTChkErrClr2", 23, 1 },
+		{ "ExtBISTChkEn2", 22, 1 },
+		{ "ExtBISTGenEn2", 21, 1 },
+		{ "ExtBISTPat2", 18, 3 },
+		{ "ExtParReset2", 17, 1 },
+		{ "ExtParLPBK2", 16, 1 },
+		{ "ExtBISTChkErrClr1", 15, 1 },
+		{ "ExtBISTChkEn1", 14, 1 },
+		{ "ExtBISTGenEn1", 13, 1 },
+		{ "ExtBISTPat1", 10, 3 },
+		{ "ExtParReset1", 9, 1 },
+		{ "ExtParLPBK1", 8, 1 },
+		{ "ExtBISTChkErrClr0", 7, 1 },
+		{ "ExtBISTChkEn0", 6, 1 },
+		{ "ExtBISTGenEn0", 5, 1 },
+		{ "ExtBISTPat0", 2, 3 },
+		{ "ExtParReset0", 1, 1 },
+		{ "ExtParLPBK0", 0, 1 },
+	{ "NCSI_SERDES_STAT0", 0x1a2f0, 0 },
+		{ "ExtBISTChkErrCnt0", 4, 24 },
+		{ "ExtBISTChkFmd0", 3, 1 },
+		{ "LowSigForceEn0", 2, 1 },
+		{ "LowSigForceValue0", 1, 1 },
+		{ "LowSig0", 0, 1 },
+	{ "NCSI_SERDES_STAT1", 0x1a2f4, 0 },
+		{ "ExtBISTChkErrCnt1", 4, 24 },
+		{ "ExtBISTChkFmd1", 3, 1 },
+		{ "LowSigForceEn1", 2, 1 },
+		{ "LowSigForceValue1", 1, 1 },
+		{ "LowSig1", 0, 1 },
+	{ "NCSI_SERDES_STAT2", 0x1a2f8, 0 },
+		{ "ExtBISTChkErrCnt2", 4, 24 },
+		{ "ExtBISTChkFmd2", 3, 1 },
+		{ "LowSigForceEn2", 2, 1 },
+		{ "LowSigForceValue2", 1, 1 },
+		{ "LowSig2", 0, 1 },
+	{ "NCSI_SERDES_STAT3", 0x1a2fc, 0 },
+		{ "ExtBISTChkErrCnt3", 4, 24 },
+		{ "ExtBISTChkFmd3", 3, 1 },
+		{ "LowSigForceEn3", 2, 1 },
+		{ "LowSigForceValue3", 1, 1 },
+		{ "LowSig3", 0, 1 },
+	{ "NCSI_STAT_TX_BYTE_LOW", 0x1a300, 0 },
+	{ "NCSI_STAT_TX_BYTE_HIGH", 0x1a304, 0 },
+	{ "NCSI_STAT_TX_FRAME_LOW", 0x1a308, 0 },
+	{ "NCSI_STAT_TX_FRAME_HIGH", 0x1a30c, 0 },
+	{ "NCSI_STAT_TX_BCAST", 0x1a310, 0 },
+	{ "NCSI_STAT_TX_MCAST", 0x1a314, 0 },
+	{ "NCSI_STAT_TX_PAUSE", 0x1a318, 0 },
+	{ "NCSI_STAT_TX_64B_FRAMES", 0x1a31c, 0 },
+	{ "NCSI_STAT_TX_65_127B_FRAMES", 0x1a320, 0 },
+	{ "NCSI_STAT_TX_128_255B_FRAMES", 0x1a324, 0 },
+	{ "NCSI_STAT_TX_256_511B_FRAMES", 0x1a328, 0 },
+	{ "NCSI_STAT_TX_512_1023B_FRAMES", 0x1a32c, 0 },
+	{ "NCSI_STAT_TX_1024_1518B_FRAMES", 0x1a330, 0 },
+	{ "NCSI_STAT_TX_1519_MAXB_FRAMES", 0x1a334, 0 },
+	{ "NCSI_STAT_TX_ERR_FRAMES", 0x1a338, 0 },
+	{ "NCSI_STAT_RX_BYTES_LOW", 0x1a33c, 0 },
+	{ "NCSI_STAT_RX_BYTES_HIGH", 0x1a340, 0 },
+	{ "NCSI_STAT_RX_FRAMES_LOW", 0x1a344, 0 },
+	{ "NCSI_STAT_RX_FRAMES_HIGH", 0x1a348, 0 },
+	{ "NCSI_STAT_RX_BCAST_FRAMES", 0x1a34c, 0 },
+	{ "NCSI_STAT_RX_MCAST_FRAMES", 0x1a350, 0 },
+	{ "NCSI_STAT_RX_PAUSE_FRAMES", 0x1a354, 0 },
+	{ "NCSI_STAT_RX_64B_FRAMES", 0x1a358, 0 },
+	{ "NCSI_STAT_RX_65_127B_FRAMES", 0x1a35c, 0 },
+	{ "NCSI_STAT_RX_128_255B_FRAMES", 0x1a360, 0 },
+	{ "NCSI_STAT_RX_256_511B_FRAMES", 0x1a364, 0 },
+	{ "NCSI_STAT_RX_512_1023B_FRAMES", 0x1a368, 0 },
+	{ "NCSI_STAT_RX_1024_1518B_FRAMES", 0x1a36c, 0 },
+	{ "NCSI_STAT_RX_1519_MAXB_FRAMES", 0x1a370, 0 },
+	{ "NCSI_STAT_RX_SHORT_FRAMES", 0x1a374, 0 },
+	{ "NCSI_STAT_RX_OVERSIZE_FRAMES", 0x1a378, 0 },
+	{ "NCSI_STAT_RX_JABBER_FRAMES", 0x1a37c, 0 },
+	{ "NCSI_STAT_RX_CRC_ERR_FRAMES", 0x1a380, 0 },
+	{ "NCSI_STAT_RX_LENGTH_ERR_FRAMES", 0x1a384, 0 },
+	{ "NCSI_STAT_RX_SYM_CODE_ERR_FRAMES", 0x1a388, 0 },
+	{ "NCSI_XAUI_PCS_ERR", 0x1a398, 0 },
+		{ "PCS_SyncStatus", 5, 4 },
+		{ "PCS_CTCFIFOErr", 1, 4 },
+		{ "PCS_NotAligned", 0, 1 },
+	{ "NCSI_RGMII_STATUS", 0x1a39c, 0 },
+		{ "GMIIDuplex", 3, 1 },
+		{ "GMIISpeed", 1, 2 },
+		{ "GMIILinkStatus", 0, 1 },
+	{ "NCSI_WOL_STATUS", 0x1a3a0, 0 },
+		{ "PatDetected", 31, 1 },
+		{ "MatchedFilter", 0, 3 },
+	{ "NCSI_RX_MAX_PKT_SIZE_ERR_CNT", 0x1a3a4, 0 },
+	{ "NCSI_TX_SPI4_SOP_EOP_CNT", 0x1a3a8, 0 },
+		{ "TxSPI4SopCnt", 16, 16 },
+		{ "TxSPI4EopCnt", 0, 16 },
+	{ "NCSI_RX_SPI4_SOP_EOP_CNT", 0x1a3ac, 0 },
+		{ "RxSPI4SopCnt", 16, 16 },
+		{ "RxSPI4EopCnt", 0, 16 },
+	{ NULL }
+};
+
+struct reg_info t7_mac_t7_regs[] = {
+	{ "MAC_PORT_CFG", 0x30800, 0 },
+		{ "SinkTx", 27, 1 },
+		{ "SinkTxOnLinkDown", 26, 1 },
+		{ "port_map", 21, 3 },
+		{ "Smux_Rx_Loop", 17, 4 },
+		{ "Signal_Det", 15, 1 },
+		{ "cfg_mac_2_mps_full", 13, 1 },
+		{ "mps_full_sel", 12, 1 },
+		{ "SmuxTxSel", 8, 4 },
+		{ "PortSpeed", 4, 4 },
+		{ "Rx_Byte_Swap", 3, 1 },
+		{ "Tx_Byte_Swap", 2, 1 },
+		{ "debug_tx_rx_sel", 1, 1 },
+	{ "MAC_PORT_RESET_CTRL", 0x30804, 0 },
+		{ "EEE_RESET", 30, 1 },
+		{ "PTP_TIMER", 29, 1 },
+		{ "MtipRefReset", 28, 1 },
+		{ "MtipRegReset", 25, 1 },
+		{ "reset_reg_clk_i", 24, 1 },
+		{ "TXIF_Reset", 12, 1 },
+		{ "RXIF_Reset", 11, 1 },
+		{ "AuxExt_Reset", 10, 1 },
+		{ "WOL_Reset", 2, 1 },
+	{ "MAC_PORT_LED_CFG", 0x30808, 0 },
+		{ "Led1_Cfg1", 15, 3 },
+		{ "Led0_Cfg1", 12, 3 },
+		{ "Led1_tlo", 11, 1 },
+		{ "Led1_thi", 10, 1 },
+		{ "Led0_tlo", 9, 1 },
+		{ "Led0_thi", 8, 1 },
+		{ "Led1_Cfg", 5, 3 },
+		{ "Led1_Polarity_Inv", 4, 1 },
+		{ "Led0_Cfg", 1, 3 },
+		{ "Led0_Polarity_Inv", 0, 1 },
+	{ "MAC_PORT_LED_COUNTHI", 0x3080c, 0 },
+	{ "MAC_PORT_LED_COUNTLO", 0x30810, 0 },
+	{ "MAC_PORT_CFG3", 0x30814, 0 },
+		{ "FCSDisCtrl", 25, 1 },
+		{ "SigDetCtrl", 24, 1 },
+		{ "se_clr", 21, 1 },
+	{ "MAC_PORT_CFG2", 0x30818, 0 },
+		{ "InstanceNum", 22, 2 },
+		{ "StopOnPerr", 21, 1 },
+		{ "PatEn", 18, 1 },
+		{ "MagicEn", 17, 1 },
+	{ "MAC_PORT_PKT_COUNT", 0x3081c, 0 },
+		{ "tx_sop_count", 24, 8 },
+		{ "tx_eop_count", 16, 8 },
+		{ "rx_sop_count", 8, 8 },
+		{ "rx_eop_count", 0, 8 },
+	{ "MAC_PORT_MAGIC_MACID_LO", 0x30820, 0 },
+	{ "MAC_PORT_MAGIC_MACID_HI", 0x30824, 0 },
+	{ "MAC_PORT_LINK_STATUS", 0x30828, 0 },
+		{ "egr_se_cnt_Err", 9, 1 },
+		{ "ingr_se_cnt_Err", 8, 1 },
+		{ "hi_ber", 7, 1 },
+		{ "an_done", 6, 1 },
+		{ "align_done", 5, 1 },
+		{ "block_lock", 4, 1 },
+		{ "remflt", 3, 1 },
+		{ "locflt", 2, 1 },
+		{ "linkup", 1, 1 },
+		{ "linkdn", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN_100G", 0x3082c, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x30830, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_ENABLE_100G", 0x30834, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_0", 0x30838, 0 },
+		{ "peer_delay_val", 31, 1 },
+		{ "peer_delay", 1, 30 },
+		{ "mode1s_ena", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_1", 0x3083c, 0 },
+		{ "tx_stop", 25, 1 },
+		{ "mode1s_ena", 24, 1 },
+		{ "tx_ts_id", 12, 12 },
+		{ "tx_li_fault", 11, 1 },
+		{ "xoff_gen", 3, 8 },
+		{ "lpi_txhold", 2, 1 },
+		{ "tx_rem_fault", 1, 1 },
+		{ "tx_loc_fault", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_2", 0x30840, 0 },
+	{ "MAC_PORT_MAC10G100G_STATUS", 0x30844, 0 },
+		{ "reg_lowp", 21, 1 },
+		{ "li_fault", 20, 1 },
+		{ "tx_isidle", 19, 1 },
+		{ "tx_underflow", 18, 1 },
+		{ "tx_empty", 17, 1 },
+		{ "rem_fault", 16, 1 },
+		{ "reg_ts_avail", 15, 1 },
+		{ "phy_txena", 14, 1 },
+		{ "pfc_mode", 13, 1 },
+		{ "pause_on", 5, 8 },
+		{ "mac_pause_en", 4, 1 },
+		{ "mac_enable", 3, 1 },
+		{ "loop_ena", 2, 1 },
+		{ "loc_fault", 1, 1 },
+		{ "ff_rx_empty", 0, 1 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS0", 0x30848, 0 },
+		{ "an_val_an", 15, 1 },
+		{ "an_tr_dis_status_an", 14, 1 },
+		{ "an_status_an", 13, 1 },
+		{ "an_select_an", 8, 5 },
+		{ "an_rs_fec_ena_an", 7, 1 },
+		{ "an_int_an", 6, 1 },
+		{ "an_fec_ena_an", 5, 1 },
+		{ "an_done_an", 4, 1 },
+		{ "an_state", 0, 4 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS1", 0x3084c, 0 },
+	{ "MAC_PORT_EPIO_DATA0", 0x30850, 0 },
+	{ "MAC_PORT_EPIO_DATA1", 0x30854, 0 },
+	{ "MAC_PORT_EPIO_DATA2", 0x30858, 0 },
+	{ "MAC_PORT_EPIO_DATA3", 0x3085c, 0 },
+	{ "MAC_PORT_EPIO_OP", 0x30860, 0 },
+		{ "Busy", 31, 1 },
+		{ "Write", 8, 1 },
+		{ "Address", 0, 8 },
+	{ "MAC_PORT_WOL_STATUS", 0x30864, 0 },
+		{ "MagicDetected", 31, 1 },
+		{ "PatDetected", 30, 1 },
+		{ "ClearMagic", 4, 1 },
+		{ "ClearMatch", 3, 1 },
+		{ "MatchedFilter", 0, 3 },
+	{ "MAC_PORT_INT_EN", 0x30868, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_INT_CAUSE", 0x3086c, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN", 0x30870, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE", 0x30874, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_ENABLE", 0x30878, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INJECT", 0x3087c, 0 },
+		{ "MemSel", 1, 8 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MAC_PORT_RUNT_FRAME", 0x30880, 0 },
+		{ "runtclear", 16, 1 },
+		{ "runt", 0, 16 },
+	{ "MAC_PORT_EEE_STATUS", 0x30884, 0 },
+		{ "eee_tx_10g_state", 10, 2 },
+		{ "eee_rx_10g_state", 8, 2 },
+		{ "pma_rx_refresh", 3, 1 },
+		{ "pma_rx_quiet", 2, 1 },
+		{ "pma_tx_refresh", 1, 1 },
+		{ "pma_tx_quiet", 0, 1 },
+	{ "MAC_PORT_TX_TS_ID", 0x30888, 0 },
+		{ "ts_id_MSB", 3, 1 },
+		{ "ts_id", 0, 3 },
+	{ "MAC_PORT_TX_TS_VAL_LO", 0x3088c, 0 },
+	{ "MAC_PORT_TX_TS_VAL_HI", 0x30890, 0 },
+	{ "MAC_PORT_EEE_CTL", 0x30894, 0 },
+		{ "EEE_CTRL", 2, 30 },
+		{ "TICK_START", 1, 1 },
+		{ "En", 0, 1 },
+	{ "MAC_PORT_EEE_TX_CTL", 0x30898, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_ACTIVE", 3, 1 },
+		{ "LPI_TXHOLD", 2, 1 },
+		{ "LPI_REQ", 1, 1 },
+		{ "EEE_TX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_RX_CTL", 0x3089c, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_IND", 1, 1 },
+		{ "EEE_RX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x308a0, 0 },
+	{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x308a4, 0 },
+	{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x308a8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x308b8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x308bc, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x308c0, 0 },
+	{ "MAC_PORT_EEE_WF_COUNT", 0x308cc, 0 },
+		{ "wake_cnt_clr", 16, 1 },
+		{ "wake_cnt", 0, 16 },
+	{ "MAC_PORT_WOL_EN", 0x308d0, 0 },
+		{ "WOL_enable", 1, 1 },
+		{ "WOL_indicator", 0, 1 },
+	{ "MAC_PORT_INT_TRACE", 0x308d4, 0 },
+	{ "MAC_PORT_TRACE_TS_LO", 0x308d8, 0 },
+	{ "MAC_PORT_TRACE_TS_HI", 0x308dc, 0 },
+	{ "MAC_PORT_MTIP_10G100G_REVISION", 0x30900, 0 },
+		{ "CUSTREV", 16, 16 },
+		{ "VER", 8, 8 },
+		{ "REV", 0, 8 },
+	{ "MAC_PORT_MTIP_10G100G_SCRATCH", 0x30904, 0 },
+	{ "MAC_PORT_MTIP_10G100G_COMMAND_CONFIG", 0x30908, 0 },
+		{ "NO_PREAM", 31, 1 },
+		{ "SHORT_PREAM", 30, 1 },
+		{ "FLT_HDL_DIS", 27, 1 },
+		{ "TX_FIFO_RESET", 26, 1 },
+		{ "REG_LOWP_RXEMPTY", 24, 1 },
+		{ "TX_LOWP_ENA", 23, 1 },
+		{ "TX_FLUSH", 22, 1 },
+		{ "RX_SFD_ANY", 21, 1 },
+		{ "PAUSE_PFC_COMP", 20, 1 },
+		{ "PFC_MODE", 19, 1 },
+		{ "FORCE_SEND_IDLE", 16, 1 },
+		{ "PHY_TXENA", 15, 1 },
+		{ "CNTL_FRM_ENA", 13, 1 },
+		{ "SW_RESET", 12, 1 },
+		{ "TX_PAD_EN", 11, 1 },
+		{ "LOOP_ENA", 10, 1 },
+		{ "TX_ADDR_INS", 9, 1 },
+		{ "PAUSE_IGNORE", 8, 1 },
+		{ "PAUSE_FWD", 7, 1 },
+		{ "CRC_FWD", 6, 1 },
+		{ "PROMIS_EN", 4, 1 },
+		{ "RX_ENAMAC", 1, 1 },
+		{ "TX_ENAMAC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_0", 0x3090c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_1", 0x30910, 0 },
+	{ "MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU", 0x30914, 0 },
+		{ "SET_LEN", 16, 16 },
+		{ "FRM_LEN_SET", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS", 0x3091c, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS", 0x30920, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E", 0x30924, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E", 0x30928, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS", 0x30930, 0 },
+		{ "Clk_divisor", 7, 9 },
+		{ "ENA_CLAUSE", 6, 1 },
+		{ "PREAMBLE_DISABLE", 5, 1 },
+		{ "Hold_time_setting", 2, 3 },
+		{ "MDIO_read_error", 1, 1 },
+		{ "MDIO_Busy", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_COMMAND", 0x30934, 0 },
+		{ "READ_MODE", 15, 1 },
+		{ "POST_INCR_READ", 14, 1 },
+		{ "Port_PHY_Addr", 5, 5 },
+		{ "Device_Reg_Addr", 0, 5 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_DATA", 0x30938, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_REGADDR", 0x3093c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_STATUS", 0x30940, 0 },
+		{ "TX_ISIDLE", 8, 1 },
+		{ "RX_LINT_FAULT", 7, 1 },
+		{ "RX_EMPTY", 6, 1 },
+		{ "TX_EMPTY", 5, 1 },
+		{ "RX_LOWP", 4, 1 },
+		{ "TS_AVAIL", 3, 1 },
+		{ "PHY_LOS", 2, 1 },
+		{ "RX_REM_FAULT", 1, 1 },
+		{ "RX_LOC_FAULT", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH", 0x30944, 0 },
+		{ "IPG_COMP_CNT", 16, 16 },
+		{ "AVG_IPG_LEN", 2, 4 },
+		{ "DSBL_DIC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_CRC_MODE", 0x30948, 0 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA", 0x30954, 0 },
+		{ "CL1_PAUSE_QUANTA", 16, 16 },
+		{ "CL0_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA", 0x30958, 0 },
+		{ "CL3_PAUSE_QUANTA", 16, 16 },
+		{ "CL2_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA", 0x3095c, 0 },
+		{ "CL5_PAUSE_QUANTA", 16, 16 },
+		{ "CL4_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA", 0x30960, 0 },
+		{ "CL7_PAUSE_QUANTA", 16, 16 },
+		{ "CL6_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH", 0x30964, 0 },
+		{ "CL1_QUANTA_THRESH", 16, 16 },
+		{ "CL0_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH", 0x30968, 0 },
+		{ "CL3_QUANTA_THRESH", 16, 16 },
+		{ "CL2_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH", 0x3096c, 0 },
+		{ "CL5_QUANTA_THRESH", 16, 16 },
+		{ "CL4_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH", 0x30970, 0 },
+		{ "CL7_QUANTA_THRESH", 16, 16 },
+		{ "CL6_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS", 0x30974, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TS_TIMESTAMP", 0x3097c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_XIF_MODE", 0x30980, 0 },
+		{ "RX_CNT_MODE", 16, 1 },
+		{ "TS_UPD64_MODE", 12, 1 },
+		{ "TS_BINARY_MODE", 11, 1 },
+		{ "TS_DELAY_MODE", 10, 1 },
+		{ "TS_DELTA_MODE", 9, 1 },
+		{ "TX_MAC_RS_ERR", 8, 1 },
+		{ "RX_PAUSE_BYPASS", 6, 1 },
+		{ "ONE_STEP_ENA", 5, 1 },
+		{ "PAUSETIMERX8", 4, 1 },
+		{ "XGMII_ENA", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_1", 0x30a00, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_1", 0x30a04, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID0", 0x30a08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID1", 0x30a0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SPEED_ABILITY", 0x30a10, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1", 0x30a14, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2", 0x30a18, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_2", 0x30a1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_2", 0x30a20, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID0", 0x30a38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID1", 0x30a3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_EEE_CTRL", 0x30a50, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER", 0x30a58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1", 0x30a80, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2", 0x30a84, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_0", 0x30a88, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_1", 0x30a8c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_2", 0x30a90, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_3", 0x30a94, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_0", 0x30a98, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_1", 0x30a9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_2", 0x30aa0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_3", 0x30aa4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL", 0x30aa8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT", 0x30aac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT", 0x30ab0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT", 0x30ab4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1", 0x30ac8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2", 0x30acc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3", 0x30ad0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4", 0x30ad4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0", 0x30ad8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1", 0x30adc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2", 0x30ae0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3", 0x30ae4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4", 0x30ae8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5", 0x30aec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6", 0x30af0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7", 0x30af4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8", 0x30af8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9", 0x30afc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10", 0x30b00, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11", 0x30b04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12", 0x30b08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13", 0x30b0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14", 0x30b10, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15", 0x30b14, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16", 0x30b18, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17", 0x30b1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18", 0x30b20, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19", 0x30b24, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING", 0x30b28, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING", 0x30b2c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING", 0x30b30, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING", 0x30b34, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING", 0x30b38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING", 0x30b3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING", 0x30b40, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING", 0x30b44, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING", 0x30b48, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING", 0x30b4c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING", 0x30b50, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING", 0x30b54, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING", 0x30b58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING", 0x30b5c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING", 0x30b60, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING", 0x30b64, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING", 0x30b68, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING", 0x30b6c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING", 0x30b70, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING", 0x30b74, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SCRATCH", 0x30b78, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_CORE_REVISION", 0x30b7c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL_INTVL", 0x30b80, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH", 0x30b84, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_0", 0x30b98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_1", 0x30b9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_0", 0x30ba0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_1", 0x30ba4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_0", 0x30ba8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_1", 0x30bac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_0", 0x30bb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_1", 0x30bb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PCS_MODE", 0x30bb8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_0", 0x30c98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_1", 0x30c9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_0", 0x30ca0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_1", 0x30ca4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_0", 0x30ca8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_1", 0x30cac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_0", 0x30cb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_1", 0x30cb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_0", 0x30cb8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_1", 0x30cbc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_0", 0x30cc0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_1", 0x30cc4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_0", 0x30cc8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_1", 0x30ccc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_0", 0x30cd0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_1", 0x30cd4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_0", 0x30cd8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_1", 0x30cdc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_0", 0x30ce0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_1", 0x30ce4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_0", 0x30ce8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_1", 0x30cec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_0", 0x30cf0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_1", 0x30cf4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_0", 0x30cf8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_1", 0x30cfc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_0", 0x30d00, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_1", 0x30d04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_0", 0x30d08, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_1", 0x30d0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_0", 0x30d10, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_1", 0x30d14, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_1", 0x31000, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_1", 0x31004, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID0", 0x31008, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID1", 0x3100c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SPEED_ABILITY", 0x31010, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1", 0x31014, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2", 0x31018, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_2", 0x3101c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_2", 0x31020, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID0", 0x31038, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID1", 0x3103c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_EEE_CTRL", 0x31050, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER", 0x31058, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1", 0x31080, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2", 0x31084, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_0", 0x31088, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_1", 0x3108c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_2", 0x31090, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_3", 0x31094, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_0", 0x31098, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_1", 0x3109c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_2", 0x310a0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_3", 0x310a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL", 0x310a8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT", 0x310ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT", 0x310b0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT", 0x310b4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1", 0x310c8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2", 0x310cc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3", 0x310d0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4", 0x310d4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0", 0x310d8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1", 0x310dc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2", 0x310e0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3", 0x310e4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4", 0x310e8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5", 0x310ec, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6", 0x310f0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7", 0x310f4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8", 0x310f8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9", 0x310fc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10", 0x31100, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11", 0x31104, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12", 0x31108, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13", 0x3110c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14", 0x31110, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15", 0x31114, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16", 0x31118, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17", 0x3111c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18", 0x31120, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19", 0x31124, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING", 0x31128, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING", 0x3112c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING", 0x31130, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING", 0x31134, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING", 0x31138, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING", 0x3113c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING", 0x31140, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING", 0x31144, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING", 0x31148, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING", 0x3114c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING", 0x31150, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING", 0x31154, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING", 0x31158, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING", 0x3115c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING", 0x31160, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING", 0x31164, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING", 0x31168, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING", 0x3116c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING", 0x31170, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING", 0x31174, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SCRATCH", 0x31178, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CORE_REVISION", 0x3117c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL_INTVL", 0x31180, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH", 0x31184, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_0", 0x31198, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_1", 0x3119c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_0", 0x311a0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_1", 0x311a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_0", 0x311a8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_1", 0x311ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_0", 0x311b0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_1", 0x311b4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PCS_MODE", 0x311b8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_CFG", 0x32800, 0 },
+		{ "SinkTx", 27, 1 },
+		{ "SinkTxOnLinkDown", 26, 1 },
+		{ "port_map", 21, 3 },
+		{ "Smux_Rx_Loop", 17, 4 },
+		{ "Signal_Det", 15, 1 },
+		{ "cfg_mac_2_mps_full", 13, 1 },
+		{ "mps_full_sel", 12, 1 },
+		{ "SmuxTxSel", 8, 4 },
+		{ "PortSpeed", 4, 4 },
+		{ "Rx_Byte_Swap", 3, 1 },
+		{ "Tx_Byte_Swap", 2, 1 },
+		{ "debug_tx_rx_sel", 1, 1 },
+	{ "MAC_PORT_RESET_CTRL", 0x32804, 0 },
+		{ "EEE_RESET", 30, 1 },
+		{ "PTP_TIMER", 29, 1 },
+		{ "MtipRefReset", 28, 1 },
+		{ "MtipRegReset", 25, 1 },
+		{ "reset_reg_clk_i", 24, 1 },
+		{ "TXIF_Reset", 12, 1 },
+		{ "RXIF_Reset", 11, 1 },
+		{ "AuxExt_Reset", 10, 1 },
+		{ "WOL_Reset", 2, 1 },
+	{ "MAC_PORT_LED_CFG", 0x32808, 0 },
+		{ "Led1_Cfg1", 15, 3 },
+		{ "Led0_Cfg1", 12, 3 },
+		{ "Led1_tlo", 11, 1 },
+		{ "Led1_thi", 10, 1 },
+		{ "Led0_tlo", 9, 1 },
+		{ "Led0_thi", 8, 1 },
+		{ "Led1_Cfg", 5, 3 },
+		{ "Led1_Polarity_Inv", 4, 1 },
+		{ "Led0_Cfg", 1, 3 },
+		{ "Led0_Polarity_Inv", 0, 1 },
+	{ "MAC_PORT_LED_COUNTHI", 0x3280c, 0 },
+	{ "MAC_PORT_LED_COUNTLO", 0x32810, 0 },
+	{ "MAC_PORT_CFG3", 0x32814, 0 },
+		{ "FCSDisCtrl", 25, 1 },
+		{ "SigDetCtrl", 24, 1 },
+		{ "se_clr", 21, 1 },
+	{ "MAC_PORT_CFG2", 0x32818, 0 },
+		{ "InstanceNum", 22, 2 },
+		{ "StopOnPerr", 21, 1 },
+		{ "PatEn", 18, 1 },
+		{ "MagicEn", 17, 1 },
+	{ "MAC_PORT_PKT_COUNT", 0x3281c, 0 },
+		{ "tx_sop_count", 24, 8 },
+		{ "tx_eop_count", 16, 8 },
+		{ "rx_sop_count", 8, 8 },
+		{ "rx_eop_count", 0, 8 },
+	{ "MAC_PORT_MAGIC_MACID_LO", 0x32820, 0 },
+	{ "MAC_PORT_MAGIC_MACID_HI", 0x32824, 0 },
+	{ "MAC_PORT_LINK_STATUS", 0x32828, 0 },
+		{ "egr_se_cnt_Err", 9, 1 },
+		{ "ingr_se_cnt_Err", 8, 1 },
+		{ "hi_ber", 7, 1 },
+		{ "an_done", 6, 1 },
+		{ "align_done", 5, 1 },
+		{ "block_lock", 4, 1 },
+		{ "remflt", 3, 1 },
+		{ "locflt", 2, 1 },
+		{ "linkup", 1, 1 },
+		{ "linkdn", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN_100G", 0x3282c, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x32830, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_ENABLE_100G", 0x32834, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_0", 0x32838, 0 },
+		{ "peer_delay_val", 31, 1 },
+		{ "peer_delay", 1, 30 },
+		{ "mode1s_ena", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_1", 0x3283c, 0 },
+		{ "tx_stop", 25, 1 },
+		{ "mode1s_ena", 24, 1 },
+		{ "tx_ts_id", 12, 12 },
+		{ "tx_li_fault", 11, 1 },
+		{ "xoff_gen", 3, 8 },
+		{ "lpi_txhold", 2, 1 },
+		{ "tx_rem_fault", 1, 1 },
+		{ "tx_loc_fault", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_2", 0x32840, 0 },
+	{ "MAC_PORT_MAC10G100G_STATUS", 0x32844, 0 },
+		{ "reg_lowp", 21, 1 },
+		{ "li_fault", 20, 1 },
+		{ "tx_isidle", 19, 1 },
+		{ "tx_underflow", 18, 1 },
+		{ "tx_empty", 17, 1 },
+		{ "rem_fault", 16, 1 },
+		{ "reg_ts_avail", 15, 1 },
+		{ "phy_txena", 14, 1 },
+		{ "pfc_mode", 13, 1 },
+		{ "pause_on", 5, 8 },
+		{ "mac_pause_en", 4, 1 },
+		{ "mac_enable", 3, 1 },
+		{ "loop_ena", 2, 1 },
+		{ "loc_fault", 1, 1 },
+		{ "ff_rx_empty", 0, 1 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS0", 0x32848, 0 },
+		{ "an_val_an", 15, 1 },
+		{ "an_tr_dis_status_an", 14, 1 },
+		{ "an_status_an", 13, 1 },
+		{ "an_select_an", 8, 5 },
+		{ "an_rs_fec_ena_an", 7, 1 },
+		{ "an_int_an", 6, 1 },
+		{ "an_fec_ena_an", 5, 1 },
+		{ "an_done_an", 4, 1 },
+		{ "an_state", 0, 4 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS1", 0x3284c, 0 },
+	{ "MAC_PORT_EPIO_DATA0", 0x32850, 0 },
+	{ "MAC_PORT_EPIO_DATA1", 0x32854, 0 },
+	{ "MAC_PORT_EPIO_DATA2", 0x32858, 0 },
+	{ "MAC_PORT_EPIO_DATA3", 0x3285c, 0 },
+	{ "MAC_PORT_EPIO_OP", 0x32860, 0 },
+		{ "Busy", 31, 1 },
+		{ "Write", 8, 1 },
+		{ "Address", 0, 8 },
+	{ "MAC_PORT_WOL_STATUS", 0x32864, 0 },
+		{ "MagicDetected", 31, 1 },
+		{ "PatDetected", 30, 1 },
+		{ "ClearMagic", 4, 1 },
+		{ "ClearMatch", 3, 1 },
+		{ "MatchedFilter", 0, 3 },
+	{ "MAC_PORT_INT_EN", 0x32868, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_INT_CAUSE", 0x3286c, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN", 0x32870, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE", 0x32874, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_ENABLE", 0x32878, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INJECT", 0x3287c, 0 },
+		{ "MemSel", 1, 8 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MAC_PORT_RUNT_FRAME", 0x32880, 0 },
+		{ "runtclear", 16, 1 },
+		{ "runt", 0, 16 },
+	{ "MAC_PORT_EEE_STATUS", 0x32884, 0 },
+		{ "eee_tx_10g_state", 10, 2 },
+		{ "eee_rx_10g_state", 8, 2 },
+		{ "pma_rx_refresh", 3, 1 },
+		{ "pma_rx_quiet", 2, 1 },
+		{ "pma_tx_refresh", 1, 1 },
+		{ "pma_tx_quiet", 0, 1 },
+	{ "MAC_PORT_TX_TS_ID", 0x32888, 0 },
+		{ "ts_id_MSB", 3, 1 },
+		{ "ts_id", 0, 3 },
+	{ "MAC_PORT_TX_TS_VAL_LO", 0x3288c, 0 },
+	{ "MAC_PORT_TX_TS_VAL_HI", 0x32890, 0 },
+	{ "MAC_PORT_EEE_CTL", 0x32894, 0 },
+		{ "EEE_CTRL", 2, 30 },
+		{ "TICK_START", 1, 1 },
+		{ "En", 0, 1 },
+	{ "MAC_PORT_EEE_TX_CTL", 0x32898, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_ACTIVE", 3, 1 },
+		{ "LPI_TXHOLD", 2, 1 },
+		{ "LPI_REQ", 1, 1 },
+		{ "EEE_TX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_RX_CTL", 0x3289c, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_IND", 1, 1 },
+		{ "EEE_RX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x328a0, 0 },
+	{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x328a4, 0 },
+	{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x328a8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x328b8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x328bc, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x328c0, 0 },
+	{ "MAC_PORT_EEE_WF_COUNT", 0x328cc, 0 },
+		{ "wake_cnt_clr", 16, 1 },
+		{ "wake_cnt", 0, 16 },
+	{ "MAC_PORT_WOL_EN", 0x328d0, 0 },
+		{ "WOL_enable", 1, 1 },
+		{ "WOL_indicator", 0, 1 },
+	{ "MAC_PORT_INT_TRACE", 0x328d4, 0 },
+	{ "MAC_PORT_TRACE_TS_LO", 0x328d8, 0 },
+	{ "MAC_PORT_TRACE_TS_HI", 0x328dc, 0 },
+	{ "MAC_PORT_MTIP_10G100G_REVISION", 0x32900, 0 },
+		{ "CUSTREV", 16, 16 },
+		{ "VER", 8, 8 },
+		{ "REV", 0, 8 },
+	{ "MAC_PORT_MTIP_10G100G_SCRATCH", 0x32904, 0 },
+	{ "MAC_PORT_MTIP_10G100G_COMMAND_CONFIG", 0x32908, 0 },
+		{ "NO_PREAM", 31, 1 },
+		{ "SHORT_PREAM", 30, 1 },
+		{ "FLT_HDL_DIS", 27, 1 },
+		{ "TX_FIFO_RESET", 26, 1 },
+		{ "REG_LOWP_RXEMPTY", 24, 1 },
+		{ "TX_LOWP_ENA", 23, 1 },
+		{ "TX_FLUSH", 22, 1 },
+		{ "RX_SFD_ANY", 21, 1 },
+		{ "PAUSE_PFC_COMP", 20, 1 },
+		{ "PFC_MODE", 19, 1 },
+		{ "FORCE_SEND_IDLE", 16, 1 },
+		{ "PHY_TXENA", 15, 1 },
+		{ "CNTL_FRM_ENA", 13, 1 },
+		{ "SW_RESET", 12, 1 },
+		{ "TX_PAD_EN", 11, 1 },
+		{ "LOOP_ENA", 10, 1 },
+		{ "TX_ADDR_INS", 9, 1 },
+		{ "PAUSE_IGNORE", 8, 1 },
+		{ "PAUSE_FWD", 7, 1 },
+		{ "CRC_FWD", 6, 1 },
+		{ "PROMIS_EN", 4, 1 },
+		{ "RX_ENAMAC", 1, 1 },
+		{ "TX_ENAMAC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_0", 0x3290c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_1", 0x32910, 0 },
+	{ "MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU", 0x32914, 0 },
+		{ "SET_LEN", 16, 16 },
+		{ "FRM_LEN_SET", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS", 0x3291c, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS", 0x32920, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E", 0x32924, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E", 0x32928, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS", 0x32930, 0 },
+		{ "Clk_divisor", 7, 9 },
+		{ "ENA_CLAUSE", 6, 1 },
+		{ "PREAMBLE_DISABLE", 5, 1 },
+		{ "Hold_time_setting", 2, 3 },
+		{ "MDIO_read_error", 1, 1 },
+		{ "MDIO_Busy", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_COMMAND", 0x32934, 0 },
+		{ "READ_MODE", 15, 1 },
+		{ "POST_INCR_READ", 14, 1 },
+		{ "Port_PHY_Addr", 5, 5 },
+		{ "Device_Reg_Addr", 0, 5 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_DATA", 0x32938, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_REGADDR", 0x3293c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_STATUS", 0x32940, 0 },
+		{ "TX_ISIDLE", 8, 1 },
+		{ "RX_LINT_FAULT", 7, 1 },
+		{ "RX_EMPTY", 6, 1 },
+		{ "TX_EMPTY", 5, 1 },
+		{ "RX_LOWP", 4, 1 },
+		{ "TS_AVAIL", 3, 1 },
+		{ "PHY_LOS", 2, 1 },
+		{ "RX_REM_FAULT", 1, 1 },
+		{ "RX_LOC_FAULT", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH", 0x32944, 0 },
+		{ "IPG_COMP_CNT", 16, 16 },
+		{ "AVG_IPG_LEN", 2, 4 },
+		{ "DSBL_DIC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_CRC_MODE", 0x32948, 0 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA", 0x32954, 0 },
+		{ "CL1_PAUSE_QUANTA", 16, 16 },
+		{ "CL0_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA", 0x32958, 0 },
+		{ "CL3_PAUSE_QUANTA", 16, 16 },
+		{ "CL2_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA", 0x3295c, 0 },
+		{ "CL5_PAUSE_QUANTA", 16, 16 },
+		{ "CL4_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA", 0x32960, 0 },
+		{ "CL7_PAUSE_QUANTA", 16, 16 },
+		{ "CL6_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH", 0x32964, 0 },
+		{ "CL1_QUANTA_THRESH", 16, 16 },
+		{ "CL0_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH", 0x32968, 0 },
+		{ "CL3_QUANTA_THRESH", 16, 16 },
+		{ "CL2_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH", 0x3296c, 0 },
+		{ "CL5_QUANTA_THRESH", 16, 16 },
+		{ "CL4_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH", 0x32970, 0 },
+		{ "CL7_QUANTA_THRESH", 16, 16 },
+		{ "CL6_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS", 0x32974, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TS_TIMESTAMP", 0x3297c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_XIF_MODE", 0x32980, 0 },
+		{ "RX_CNT_MODE", 16, 1 },
+		{ "TS_UPD64_MODE", 12, 1 },
+		{ "TS_BINARY_MODE", 11, 1 },
+		{ "TS_DELAY_MODE", 10, 1 },
+		{ "TS_DELTA_MODE", 9, 1 },
+		{ "TX_MAC_RS_ERR", 8, 1 },
+		{ "RX_PAUSE_BYPASS", 6, 1 },
+		{ "ONE_STEP_ENA", 5, 1 },
+		{ "PAUSETIMERX8", 4, 1 },
+		{ "XGMII_ENA", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_1", 0x32a00, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_1", 0x32a04, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID0", 0x32a08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID1", 0x32a0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SPEED_ABILITY", 0x32a10, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1", 0x32a14, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2", 0x32a18, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_2", 0x32a1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_2", 0x32a20, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID0", 0x32a38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID1", 0x32a3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_EEE_CTRL", 0x32a50, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER", 0x32a58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1", 0x32a80, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2", 0x32a84, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_0", 0x32a88, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_1", 0x32a8c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_2", 0x32a90, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_3", 0x32a94, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_0", 0x32a98, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_1", 0x32a9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_2", 0x32aa0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_3", 0x32aa4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL", 0x32aa8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT", 0x32aac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT", 0x32ab0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT", 0x32ab4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1", 0x32ac8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2", 0x32acc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3", 0x32ad0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4", 0x32ad4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0", 0x32ad8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1", 0x32adc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2", 0x32ae0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3", 0x32ae4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4", 0x32ae8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5", 0x32aec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6", 0x32af0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7", 0x32af4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8", 0x32af8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9", 0x32afc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10", 0x32b00, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11", 0x32b04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12", 0x32b08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13", 0x32b0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14", 0x32b10, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15", 0x32b14, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16", 0x32b18, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17", 0x32b1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18", 0x32b20, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19", 0x32b24, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING", 0x32b28, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING", 0x32b2c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING", 0x32b30, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING", 0x32b34, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING", 0x32b38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING", 0x32b3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING", 0x32b40, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING", 0x32b44, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING", 0x32b48, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING", 0x32b4c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING", 0x32b50, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING", 0x32b54, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING", 0x32b58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING", 0x32b5c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING", 0x32b60, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING", 0x32b64, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING", 0x32b68, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING", 0x32b6c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING", 0x32b70, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING", 0x32b74, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SCRATCH", 0x32b78, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_CORE_REVISION", 0x32b7c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL_INTVL", 0x32b80, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH", 0x32b84, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_0", 0x32b98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_1", 0x32b9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_0", 0x32ba0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_1", 0x32ba4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_0", 0x32ba8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_1", 0x32bac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_0", 0x32bb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_1", 0x32bb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PCS_MODE", 0x32bb8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_0", 0x32c98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_1", 0x32c9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_0", 0x32ca0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_1", 0x32ca4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_0", 0x32ca8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_1", 0x32cac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_0", 0x32cb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_1", 0x32cb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_0", 0x32cb8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_1", 0x32cbc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_0", 0x32cc0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_1", 0x32cc4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_0", 0x32cc8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_1", 0x32ccc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_0", 0x32cd0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_1", 0x32cd4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_0", 0x32cd8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_1", 0x32cdc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_0", 0x32ce0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_1", 0x32ce4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_0", 0x32ce8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_1", 0x32cec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_0", 0x32cf0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_1", 0x32cf4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_0", 0x32cf8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_1", 0x32cfc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_0", 0x32d00, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_1", 0x32d04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_0", 0x32d08, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_1", 0x32d0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_0", 0x32d10, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_1", 0x32d14, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_1", 0x33000, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_1", 0x33004, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID0", 0x33008, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID1", 0x3300c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SPEED_ABILITY", 0x33010, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1", 0x33014, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2", 0x33018, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_2", 0x3301c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_2", 0x33020, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID0", 0x33038, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID1", 0x3303c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_EEE_CTRL", 0x33050, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER", 0x33058, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1", 0x33080, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2", 0x33084, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_0", 0x33088, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_1", 0x3308c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_2", 0x33090, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_3", 0x33094, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_0", 0x33098, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_1", 0x3309c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_2", 0x330a0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_3", 0x330a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL", 0x330a8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT", 0x330ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT", 0x330b0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT", 0x330b4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1", 0x330c8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2", 0x330cc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3", 0x330d0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4", 0x330d4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0", 0x330d8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1", 0x330dc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2", 0x330e0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3", 0x330e4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4", 0x330e8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5", 0x330ec, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6", 0x330f0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7", 0x330f4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8", 0x330f8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9", 0x330fc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10", 0x33100, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11", 0x33104, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12", 0x33108, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13", 0x3310c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14", 0x33110, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15", 0x33114, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16", 0x33118, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17", 0x3311c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18", 0x33120, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19", 0x33124, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING", 0x33128, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING", 0x3312c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING", 0x33130, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING", 0x33134, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING", 0x33138, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING", 0x3313c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING", 0x33140, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING", 0x33144, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING", 0x33148, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING", 0x3314c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING", 0x33150, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING", 0x33154, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING", 0x33158, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING", 0x3315c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING", 0x33160, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING", 0x33164, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING", 0x33168, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING", 0x3316c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING", 0x33170, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING", 0x33174, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SCRATCH", 0x33178, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CORE_REVISION", 0x3317c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL_INTVL", 0x33180, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH", 0x33184, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_0", 0x33198, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_1", 0x3319c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_0", 0x331a0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_1", 0x331a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_0", 0x331a8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_1", 0x331ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_0", 0x331b0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_1", 0x331b4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PCS_MODE", 0x331b8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_CFG", 0x34800, 0 },
+		{ "SinkTx", 27, 1 },
+		{ "SinkTxOnLinkDown", 26, 1 },
+		{ "port_map", 21, 3 },
+		{ "Smux_Rx_Loop", 17, 4 },
+		{ "Signal_Det", 15, 1 },
+		{ "cfg_mac_2_mps_full", 13, 1 },
+		{ "mps_full_sel", 12, 1 },
+		{ "SmuxTxSel", 8, 4 },
+		{ "PortSpeed", 4, 4 },
+		{ "Rx_Byte_Swap", 3, 1 },
+		{ "Tx_Byte_Swap", 2, 1 },
+		{ "debug_tx_rx_sel", 1, 1 },
+	{ "MAC_PORT_RESET_CTRL", 0x34804, 0 },
+		{ "EEE_RESET", 30, 1 },
+		{ "PTP_TIMER", 29, 1 },
+		{ "MtipRefReset", 28, 1 },
+		{ "MtipRegReset", 25, 1 },
+		{ "reset_reg_clk_i", 24, 1 },
+		{ "TXIF_Reset", 12, 1 },
+		{ "RXIF_Reset", 11, 1 },
+		{ "AuxExt_Reset", 10, 1 },
+		{ "WOL_Reset", 2, 1 },
+	{ "MAC_PORT_LED_CFG", 0x34808, 0 },
+		{ "Led1_Cfg1", 15, 3 },
+		{ "Led0_Cfg1", 12, 3 },
+		{ "Led1_tlo", 11, 1 },
+		{ "Led1_thi", 10, 1 },
+		{ "Led0_tlo", 9, 1 },
+		{ "Led0_thi", 8, 1 },
+		{ "Led1_Cfg", 5, 3 },
+		{ "Led1_Polarity_Inv", 4, 1 },
+		{ "Led0_Cfg", 1, 3 },
+		{ "Led0_Polarity_Inv", 0, 1 },
+	{ "MAC_PORT_LED_COUNTHI", 0x3480c, 0 },
+	{ "MAC_PORT_LED_COUNTLO", 0x34810, 0 },
+	{ "MAC_PORT_CFG3", 0x34814, 0 },
+		{ "FCSDisCtrl", 25, 1 },
+		{ "SigDetCtrl", 24, 1 },
+		{ "se_clr", 21, 1 },
+	{ "MAC_PORT_CFG2", 0x34818, 0 },
+		{ "InstanceNum", 22, 2 },
+		{ "StopOnPerr", 21, 1 },
+		{ "PatEn", 18, 1 },
+		{ "MagicEn", 17, 1 },
+	{ "MAC_PORT_PKT_COUNT", 0x3481c, 0 },
+		{ "tx_sop_count", 24, 8 },
+		{ "tx_eop_count", 16, 8 },
+		{ "rx_sop_count", 8, 8 },
+		{ "rx_eop_count", 0, 8 },
+	{ "MAC_PORT_MAGIC_MACID_LO", 0x34820, 0 },
+	{ "MAC_PORT_MAGIC_MACID_HI", 0x34824, 0 },
+	{ "MAC_PORT_LINK_STATUS", 0x34828, 0 },
+		{ "egr_se_cnt_Err", 9, 1 },
+		{ "ingr_se_cnt_Err", 8, 1 },
+		{ "hi_ber", 7, 1 },
+		{ "an_done", 6, 1 },
+		{ "align_done", 5, 1 },
+		{ "block_lock", 4, 1 },
+		{ "remflt", 3, 1 },
+		{ "locflt", 2, 1 },
+		{ "linkup", 1, 1 },
+		{ "linkdn", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN_100G", 0x3482c, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x34830, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_ENABLE_100G", 0x34834, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_0", 0x34838, 0 },
+		{ "peer_delay_val", 31, 1 },
+		{ "peer_delay", 1, 30 },
+		{ "mode1s_ena", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_1", 0x3483c, 0 },
+		{ "tx_stop", 25, 1 },
+		{ "mode1s_ena", 24, 1 },
+		{ "tx_ts_id", 12, 12 },
+		{ "tx_li_fault", 11, 1 },
+		{ "xoff_gen", 3, 8 },
+		{ "lpi_txhold", 2, 1 },
+		{ "tx_rem_fault", 1, 1 },
+		{ "tx_loc_fault", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_2", 0x34840, 0 },
+	{ "MAC_PORT_MAC10G100G_STATUS", 0x34844, 0 },
+		{ "reg_lowp", 21, 1 },
+		{ "li_fault", 20, 1 },
+		{ "tx_isidle", 19, 1 },
+		{ "tx_underflow", 18, 1 },
+		{ "tx_empty", 17, 1 },
+		{ "rem_fault", 16, 1 },
+		{ "reg_ts_avail", 15, 1 },
+		{ "phy_txena", 14, 1 },
+		{ "pfc_mode", 13, 1 },
+		{ "pause_on", 5, 8 },
+		{ "mac_pause_en", 4, 1 },
+		{ "mac_enable", 3, 1 },
+		{ "loop_ena", 2, 1 },
+		{ "loc_fault", 1, 1 },
+		{ "ff_rx_empty", 0, 1 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS0", 0x34848, 0 },
+		{ "an_val_an", 15, 1 },
+		{ "an_tr_dis_status_an", 14, 1 },
+		{ "an_status_an", 13, 1 },
+		{ "an_select_an", 8, 5 },
+		{ "an_rs_fec_ena_an", 7, 1 },
+		{ "an_int_an", 6, 1 },
+		{ "an_fec_ena_an", 5, 1 },
+		{ "an_done_an", 4, 1 },
+		{ "an_state", 0, 4 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS1", 0x3484c, 0 },
+	{ "MAC_PORT_EPIO_DATA0", 0x34850, 0 },
+	{ "MAC_PORT_EPIO_DATA1", 0x34854, 0 },
+	{ "MAC_PORT_EPIO_DATA2", 0x34858, 0 },
+	{ "MAC_PORT_EPIO_DATA3", 0x3485c, 0 },
+	{ "MAC_PORT_EPIO_OP", 0x34860, 0 },
+		{ "Busy", 31, 1 },
+		{ "Write", 8, 1 },
+		{ "Address", 0, 8 },
+	{ "MAC_PORT_WOL_STATUS", 0x34864, 0 },
+		{ "MagicDetected", 31, 1 },
+		{ "PatDetected", 30, 1 },
+		{ "ClearMagic", 4, 1 },
+		{ "ClearMatch", 3, 1 },
+		{ "MatchedFilter", 0, 3 },
+	{ "MAC_PORT_INT_EN", 0x34868, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_INT_CAUSE", 0x3486c, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN", 0x34870, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE", 0x34874, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_ENABLE", 0x34878, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INJECT", 0x3487c, 0 },
+		{ "MemSel", 1, 8 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MAC_PORT_RUNT_FRAME", 0x34880, 0 },
+		{ "runtclear", 16, 1 },
+		{ "runt", 0, 16 },
+	{ "MAC_PORT_EEE_STATUS", 0x34884, 0 },
+		{ "eee_tx_10g_state", 10, 2 },
+		{ "eee_rx_10g_state", 8, 2 },
+		{ "pma_rx_refresh", 3, 1 },
+		{ "pma_rx_quiet", 2, 1 },
+		{ "pma_tx_refresh", 1, 1 },
+		{ "pma_tx_quiet", 0, 1 },
+	{ "MAC_PORT_TX_TS_ID", 0x34888, 0 },
+		{ "ts_id_MSB", 3, 1 },
+		{ "ts_id", 0, 3 },
+	{ "MAC_PORT_TX_TS_VAL_LO", 0x3488c, 0 },
+	{ "MAC_PORT_TX_TS_VAL_HI", 0x34890, 0 },
+	{ "MAC_PORT_EEE_CTL", 0x34894, 0 },
+		{ "EEE_CTRL", 2, 30 },
+		{ "TICK_START", 1, 1 },
+		{ "En", 0, 1 },
+	{ "MAC_PORT_EEE_TX_CTL", 0x34898, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_ACTIVE", 3, 1 },
+		{ "LPI_TXHOLD", 2, 1 },
+		{ "LPI_REQ", 1, 1 },
+		{ "EEE_TX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_RX_CTL", 0x3489c, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_IND", 1, 1 },
+		{ "EEE_RX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x348a0, 0 },
+	{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x348a4, 0 },
+	{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x348a8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x348b8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x348bc, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x348c0, 0 },
+	{ "MAC_PORT_EEE_WF_COUNT", 0x348cc, 0 },
+		{ "wake_cnt_clr", 16, 1 },
+		{ "wake_cnt", 0, 16 },
+	{ "MAC_PORT_WOL_EN", 0x348d0, 0 },
+		{ "WOL_enable", 1, 1 },
+		{ "WOL_indicator", 0, 1 },
+	{ "MAC_PORT_INT_TRACE", 0x348d4, 0 },
+	{ "MAC_PORT_TRACE_TS_LO", 0x348d8, 0 },
+	{ "MAC_PORT_TRACE_TS_HI", 0x348dc, 0 },
+	{ "MAC_PORT_MTIP_10G100G_REVISION", 0x34900, 0 },
+		{ "CUSTREV", 16, 16 },
+		{ "VER", 8, 8 },
+		{ "REV", 0, 8 },
+	{ "MAC_PORT_MTIP_10G100G_SCRATCH", 0x34904, 0 },
+	{ "MAC_PORT_MTIP_10G100G_COMMAND_CONFIG", 0x34908, 0 },
+		{ "NO_PREAM", 31, 1 },
+		{ "SHORT_PREAM", 30, 1 },
+		{ "FLT_HDL_DIS", 27, 1 },
+		{ "TX_FIFO_RESET", 26, 1 },
+		{ "REG_LOWP_RXEMPTY", 24, 1 },
+		{ "TX_LOWP_ENA", 23, 1 },
+		{ "TX_FLUSH", 22, 1 },
+		{ "RX_SFD_ANY", 21, 1 },
+		{ "PAUSE_PFC_COMP", 20, 1 },
+		{ "PFC_MODE", 19, 1 },
+		{ "FORCE_SEND_IDLE", 16, 1 },
+		{ "PHY_TXENA", 15, 1 },
+		{ "CNTL_FRM_ENA", 13, 1 },
+		{ "SW_RESET", 12, 1 },
+		{ "TX_PAD_EN", 11, 1 },
+		{ "LOOP_ENA", 10, 1 },
+		{ "TX_ADDR_INS", 9, 1 },
+		{ "PAUSE_IGNORE", 8, 1 },
+		{ "PAUSE_FWD", 7, 1 },
+		{ "CRC_FWD", 6, 1 },
+		{ "PROMIS_EN", 4, 1 },
+		{ "RX_ENAMAC", 1, 1 },
+		{ "TX_ENAMAC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_0", 0x3490c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_1", 0x34910, 0 },
+	{ "MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU", 0x34914, 0 },
+		{ "SET_LEN", 16, 16 },
+		{ "FRM_LEN_SET", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS", 0x3491c, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS", 0x34920, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E", 0x34924, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E", 0x34928, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS", 0x34930, 0 },
+		{ "Clk_divisor", 7, 9 },
+		{ "ENA_CLAUSE", 6, 1 },
+		{ "PREAMBLE_DISABLE", 5, 1 },
+		{ "Hold_time_setting", 2, 3 },
+		{ "MDIO_read_error", 1, 1 },
+		{ "MDIO_Busy", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_COMMAND", 0x34934, 0 },
+		{ "READ_MODE", 15, 1 },
+		{ "POST_INCR_READ", 14, 1 },
+		{ "Port_PHY_Addr", 5, 5 },
+		{ "Device_Reg_Addr", 0, 5 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_DATA", 0x34938, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_REGADDR", 0x3493c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_STATUS", 0x34940, 0 },
+		{ "TX_ISIDLE", 8, 1 },
+		{ "RX_LINT_FAULT", 7, 1 },
+		{ "RX_EMPTY", 6, 1 },
+		{ "TX_EMPTY", 5, 1 },
+		{ "RX_LOWP", 4, 1 },
+		{ "TS_AVAIL", 3, 1 },
+		{ "PHY_LOS", 2, 1 },
+		{ "RX_REM_FAULT", 1, 1 },
+		{ "RX_LOC_FAULT", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH", 0x34944, 0 },
+		{ "IPG_COMP_CNT", 16, 16 },
+		{ "AVG_IPG_LEN", 2, 4 },
+		{ "DSBL_DIC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_CRC_MODE", 0x34948, 0 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA", 0x34954, 0 },
+		{ "CL1_PAUSE_QUANTA", 16, 16 },
+		{ "CL0_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA", 0x34958, 0 },
+		{ "CL3_PAUSE_QUANTA", 16, 16 },
+		{ "CL2_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA", 0x3495c, 0 },
+		{ "CL5_PAUSE_QUANTA", 16, 16 },
+		{ "CL4_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA", 0x34960, 0 },
+		{ "CL7_PAUSE_QUANTA", 16, 16 },
+		{ "CL6_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH", 0x34964, 0 },
+		{ "CL1_QUANTA_THRESH", 16, 16 },
+		{ "CL0_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH", 0x34968, 0 },
+		{ "CL3_QUANTA_THRESH", 16, 16 },
+		{ "CL2_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH", 0x3496c, 0 },
+		{ "CL5_QUANTA_THRESH", 16, 16 },
+		{ "CL4_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH", 0x34970, 0 },
+		{ "CL7_QUANTA_THRESH", 16, 16 },
+		{ "CL6_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS", 0x34974, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TS_TIMESTAMP", 0x3497c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_XIF_MODE", 0x34980, 0 },
+		{ "RX_CNT_MODE", 16, 1 },
+		{ "TS_UPD64_MODE", 12, 1 },
+		{ "TS_BINARY_MODE", 11, 1 },
+		{ "TS_DELAY_MODE", 10, 1 },
+		{ "TS_DELTA_MODE", 9, 1 },
+		{ "TX_MAC_RS_ERR", 8, 1 },
+		{ "RX_PAUSE_BYPASS", 6, 1 },
+		{ "ONE_STEP_ENA", 5, 1 },
+		{ "PAUSETIMERX8", 4, 1 },
+		{ "XGMII_ENA", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_1", 0x34a00, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_1", 0x34a04, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID0", 0x34a08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID1", 0x34a0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SPEED_ABILITY", 0x34a10, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1", 0x34a14, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2", 0x34a18, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_2", 0x34a1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_2", 0x34a20, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID0", 0x34a38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID1", 0x34a3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_EEE_CTRL", 0x34a50, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER", 0x34a58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1", 0x34a80, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2", 0x34a84, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_0", 0x34a88, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_1", 0x34a8c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_2", 0x34a90, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_3", 0x34a94, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_0", 0x34a98, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_1", 0x34a9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_2", 0x34aa0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_3", 0x34aa4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL", 0x34aa8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT", 0x34aac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT", 0x34ab0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT", 0x34ab4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1", 0x34ac8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2", 0x34acc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3", 0x34ad0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4", 0x34ad4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0", 0x34ad8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1", 0x34adc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2", 0x34ae0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3", 0x34ae4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4", 0x34ae8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5", 0x34aec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6", 0x34af0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7", 0x34af4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8", 0x34af8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9", 0x34afc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10", 0x34b00, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11", 0x34b04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12", 0x34b08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13", 0x34b0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14", 0x34b10, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15", 0x34b14, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16", 0x34b18, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17", 0x34b1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18", 0x34b20, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19", 0x34b24, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING", 0x34b28, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING", 0x34b2c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING", 0x34b30, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING", 0x34b34, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING", 0x34b38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING", 0x34b3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING", 0x34b40, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING", 0x34b44, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING", 0x34b48, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING", 0x34b4c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING", 0x34b50, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING", 0x34b54, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING", 0x34b58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING", 0x34b5c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING", 0x34b60, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING", 0x34b64, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING", 0x34b68, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING", 0x34b6c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING", 0x34b70, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING", 0x34b74, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SCRATCH", 0x34b78, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_CORE_REVISION", 0x34b7c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL_INTVL", 0x34b80, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH", 0x34b84, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_0", 0x34b98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_1", 0x34b9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_0", 0x34ba0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_1", 0x34ba4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_0", 0x34ba8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_1", 0x34bac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_0", 0x34bb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_1", 0x34bb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PCS_MODE", 0x34bb8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_0", 0x34c98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_1", 0x34c9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_0", 0x34ca0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_1", 0x34ca4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_0", 0x34ca8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_1", 0x34cac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_0", 0x34cb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_1", 0x34cb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_0", 0x34cb8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_1", 0x34cbc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_0", 0x34cc0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_1", 0x34cc4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_0", 0x34cc8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_1", 0x34ccc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_0", 0x34cd0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_1", 0x34cd4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_0", 0x34cd8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_1", 0x34cdc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_0", 0x34ce0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_1", 0x34ce4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_0", 0x34ce8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_1", 0x34cec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_0", 0x34cf0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_1", 0x34cf4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_0", 0x34cf8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_1", 0x34cfc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_0", 0x34d00, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_1", 0x34d04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_0", 0x34d08, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_1", 0x34d0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_0", 0x34d10, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_1", 0x34d14, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_1", 0x35000, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_1", 0x35004, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID0", 0x35008, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID1", 0x3500c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SPEED_ABILITY", 0x35010, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1", 0x35014, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2", 0x35018, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_2", 0x3501c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_2", 0x35020, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID0", 0x35038, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID1", 0x3503c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_EEE_CTRL", 0x35050, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER", 0x35058, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1", 0x35080, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2", 0x35084, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_0", 0x35088, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_1", 0x3508c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_2", 0x35090, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_3", 0x35094, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_0", 0x35098, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_1", 0x3509c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_2", 0x350a0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_3", 0x350a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL", 0x350a8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT", 0x350ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT", 0x350b0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT", 0x350b4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1", 0x350c8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2", 0x350cc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3", 0x350d0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4", 0x350d4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0", 0x350d8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1", 0x350dc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2", 0x350e0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3", 0x350e4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4", 0x350e8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5", 0x350ec, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6", 0x350f0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7", 0x350f4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8", 0x350f8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9", 0x350fc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10", 0x35100, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11", 0x35104, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12", 0x35108, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13", 0x3510c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14", 0x35110, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15", 0x35114, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16", 0x35118, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17", 0x3511c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18", 0x35120, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19", 0x35124, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING", 0x35128, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING", 0x3512c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING", 0x35130, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING", 0x35134, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING", 0x35138, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING", 0x3513c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING", 0x35140, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING", 0x35144, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING", 0x35148, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING", 0x3514c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING", 0x35150, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING", 0x35154, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING", 0x35158, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING", 0x3515c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING", 0x35160, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING", 0x35164, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING", 0x35168, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING", 0x3516c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING", 0x35170, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING", 0x35174, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SCRATCH", 0x35178, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CORE_REVISION", 0x3517c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL_INTVL", 0x35180, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH", 0x35184, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_0", 0x35198, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_1", 0x3519c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_0", 0x351a0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_1", 0x351a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_0", 0x351a8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_1", 0x351ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_0", 0x351b0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_1", 0x351b4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PCS_MODE", 0x351b8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_CFG", 0x36800, 0 },
+		{ "SinkTx", 27, 1 },
+		{ "SinkTxOnLinkDown", 26, 1 },
+		{ "port_map", 21, 3 },
+		{ "Smux_Rx_Loop", 17, 4 },
+		{ "Signal_Det", 15, 1 },
+		{ "cfg_mac_2_mps_full", 13, 1 },
+		{ "mps_full_sel", 12, 1 },
+		{ "SmuxTxSel", 8, 4 },
+		{ "PortSpeed", 4, 4 },
+		{ "Rx_Byte_Swap", 3, 1 },
+		{ "Tx_Byte_Swap", 2, 1 },
+		{ "debug_tx_rx_sel", 1, 1 },
+	{ "MAC_PORT_RESET_CTRL", 0x36804, 0 },
+		{ "EEE_RESET", 30, 1 },
+		{ "PTP_TIMER", 29, 1 },
+		{ "MtipRefReset", 28, 1 },
+		{ "MtipRegReset", 25, 1 },
+		{ "reset_reg_clk_i", 24, 1 },
+		{ "TXIF_Reset", 12, 1 },
+		{ "RXIF_Reset", 11, 1 },
+		{ "AuxExt_Reset", 10, 1 },
+		{ "WOL_Reset", 2, 1 },
+	{ "MAC_PORT_LED_CFG", 0x36808, 0 },
+		{ "Led1_Cfg1", 15, 3 },
+		{ "Led0_Cfg1", 12, 3 },
+		{ "Led1_tlo", 11, 1 },
+		{ "Led1_thi", 10, 1 },
+		{ "Led0_tlo", 9, 1 },
+		{ "Led0_thi", 8, 1 },
+		{ "Led1_Cfg", 5, 3 },
+		{ "Led1_Polarity_Inv", 4, 1 },
+		{ "Led0_Cfg", 1, 3 },
+		{ "Led0_Polarity_Inv", 0, 1 },
+	{ "MAC_PORT_LED_COUNTHI", 0x3680c, 0 },
+	{ "MAC_PORT_LED_COUNTLO", 0x36810, 0 },
+	{ "MAC_PORT_CFG3", 0x36814, 0 },
+		{ "FCSDisCtrl", 25, 1 },
+		{ "SigDetCtrl", 24, 1 },
+		{ "se_clr", 21, 1 },
+	{ "MAC_PORT_CFG2", 0x36818, 0 },
+		{ "InstanceNum", 22, 2 },
+		{ "StopOnPerr", 21, 1 },
+		{ "PatEn", 18, 1 },
+		{ "MagicEn", 17, 1 },
+	{ "MAC_PORT_PKT_COUNT", 0x3681c, 0 },
+		{ "tx_sop_count", 24, 8 },
+		{ "tx_eop_count", 16, 8 },
+		{ "rx_sop_count", 8, 8 },
+		{ "rx_eop_count", 0, 8 },
+	{ "MAC_PORT_MAGIC_MACID_LO", 0x36820, 0 },
+	{ "MAC_PORT_MAGIC_MACID_HI", 0x36824, 0 },
+	{ "MAC_PORT_LINK_STATUS", 0x36828, 0 },
+		{ "egr_se_cnt_Err", 9, 1 },
+		{ "ingr_se_cnt_Err", 8, 1 },
+		{ "hi_ber", 7, 1 },
+		{ "an_done", 6, 1 },
+		{ "align_done", 5, 1 },
+		{ "block_lock", 4, 1 },
+		{ "remflt", 3, 1 },
+		{ "locflt", 2, 1 },
+		{ "linkup", 1, 1 },
+		{ "linkdn", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN_100G", 0x3682c, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE_100G", 0x36830, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_PERR_ENABLE_100G", 0x36834, 0 },
+		{ "Perr_pcsr_fdm_3", 21, 1 },
+		{ "Perr_pcsr_fdm_2", 20, 1 },
+		{ "Perr_pcsr_fdm_1", 19, 1 },
+		{ "Perr_pcsr_fdm_0", 18, 1 },
+		{ "Perr_pcsr_fm_3", 17, 1 },
+		{ "Perr_pcsr_fm_2", 16, 1 },
+		{ "Perr_pcsr_fm_1", 15, 1 },
+		{ "Perr_pcsr_fm_0", 14, 1 },
+		{ "Perr_pcsr_dm_1", 13, 1 },
+		{ "Perr_pcsr_dm_0", 12, 1 },
+		{ "Perr_pcsr_dk_3", 11, 1 },
+		{ "Perr_pcsr_dk_2", 10, 1 },
+		{ "Perr_pcsr_dk_1", 9, 1 },
+		{ "Perr_pcsr_dk_0", 8, 1 },
+		{ "Perr_f91ro_1", 7, 1 },
+		{ "Perr_f91ro_0", 6, 1 },
+		{ "Perr_pcsr_f91dm", 5, 1 },
+		{ "Perr_pcsr_f91ti", 4, 1 },
+		{ "Perr_pcsr_f91to", 3, 1 },
+		{ "Perr_pcsr_f91m", 2, 1 },
+		{ "Perr_pcsr_80_16_1", 1, 1 },
+		{ "Perr_pcsr_80_16_0", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_0", 0x36838, 0 },
+		{ "peer_delay_val", 31, 1 },
+		{ "peer_delay", 1, 30 },
+		{ "mode1s_ena", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_1", 0x3683c, 0 },
+		{ "tx_stop", 25, 1 },
+		{ "mode1s_ena", 24, 1 },
+		{ "tx_ts_id", 12, 12 },
+		{ "tx_li_fault", 11, 1 },
+		{ "xoff_gen", 3, 8 },
+		{ "lpi_txhold", 2, 1 },
+		{ "tx_rem_fault", 1, 1 },
+		{ "tx_loc_fault", 0, 1 },
+	{ "MAC_PORT_MAC10G100G_CONFIG_2", 0x36840, 0 },
+	{ "MAC_PORT_MAC10G100G_STATUS", 0x36844, 0 },
+		{ "reg_lowp", 21, 1 },
+		{ "li_fault", 20, 1 },
+		{ "tx_isidle", 19, 1 },
+		{ "tx_underflow", 18, 1 },
+		{ "tx_empty", 17, 1 },
+		{ "rem_fault", 16, 1 },
+		{ "reg_ts_avail", 15, 1 },
+		{ "phy_txena", 14, 1 },
+		{ "pfc_mode", 13, 1 },
+		{ "pause_on", 5, 8 },
+		{ "mac_pause_en", 4, 1 },
+		{ "mac_enable", 3, 1 },
+		{ "loop_ena", 2, 1 },
+		{ "loc_fault", 1, 1 },
+		{ "ff_rx_empty", 0, 1 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS0", 0x36848, 0 },
+		{ "an_val_an", 15, 1 },
+		{ "an_tr_dis_status_an", 14, 1 },
+		{ "an_status_an", 13, 1 },
+		{ "an_select_an", 8, 5 },
+		{ "an_rs_fec_ena_an", 7, 1 },
+		{ "an_int_an", 6, 1 },
+		{ "an_fec_ena_an", 5, 1 },
+		{ "an_done_an", 4, 1 },
+		{ "an_state", 0, 4 },
+	{ "MAC_PORT_MAC_AN_STATE_STATUS1", 0x3684c, 0 },
+	{ "MAC_PORT_EPIO_DATA0", 0x36850, 0 },
+	{ "MAC_PORT_EPIO_DATA1", 0x36854, 0 },
+	{ "MAC_PORT_EPIO_DATA2", 0x36858, 0 },
+	{ "MAC_PORT_EPIO_DATA3", 0x3685c, 0 },
+	{ "MAC_PORT_EPIO_OP", 0x36860, 0 },
+		{ "Busy", 31, 1 },
+		{ "Write", 8, 1 },
+		{ "Address", 0, 8 },
+	{ "MAC_PORT_WOL_STATUS", 0x36864, 0 },
+		{ "MagicDetected", 31, 1 },
+		{ "PatDetected", 30, 1 },
+		{ "ClearMagic", 4, 1 },
+		{ "ClearMatch", 3, 1 },
+		{ "MatchedFilter", 0, 3 },
+	{ "MAC_PORT_INT_EN", 0x36868, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_INT_CAUSE", 0x3686c, 0 },
+		{ "mps2mac_perr", 31, 1 },
+		{ "pps", 30, 1 },
+		{ "tx_ts_avail", 29, 1 },
+		{ "single_alarm", 28, 1 },
+		{ "periodic_alarm", 27, 1 },
+		{ "PatDetWake", 26, 1 },
+		{ "MagicWake", 25, 1 },
+		{ "SigDetChg", 24, 1 },
+		{ "PCS_Link_Good", 12, 1 },
+		{ "PCS_Link_Fail", 11, 1 },
+		{ "RxFifoOverFlow", 10, 1 },
+		{ "RemoteFault", 7, 1 },
+		{ "LocalFault", 6, 1 },
+		{ "MAC_Link_Down", 5, 1 },
+		{ "MAC_Link_Up", 4, 1 },
+		{ "AutoNeg_Done", 3, 1 },
+		{ "an_page_rcvd", 2, 1 },
+		{ "TxFifo_prty_err", 1, 1 },
+		{ "RxFifo_prty_err", 0, 1 },
+	{ "MAC_PORT_PERR_INT_EN", 0x36870, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INT_CAUSE", 0x36874, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_ENABLE", 0x36878, 0 },
+		{ "Perr_pkt_ram", 31, 1 },
+		{ "Perr_mask_ram", 30, 1 },
+		{ "Perr_crc_ram", 29, 1 },
+	{ "MAC_PORT_PERR_INJECT", 0x3687c, 0 },
+		{ "MemSel", 1, 8 },
+		{ "InjectDataErr", 0, 1 },
+	{ "MAC_PORT_RUNT_FRAME", 0x36880, 0 },
+		{ "runtclear", 16, 1 },
+		{ "runt", 0, 16 },
+	{ "MAC_PORT_EEE_STATUS", 0x36884, 0 },
+		{ "eee_tx_10g_state", 10, 2 },
+		{ "eee_rx_10g_state", 8, 2 },
+		{ "pma_rx_refresh", 3, 1 },
+		{ "pma_rx_quiet", 2, 1 },
+		{ "pma_tx_refresh", 1, 1 },
+		{ "pma_tx_quiet", 0, 1 },
+	{ "MAC_PORT_TX_TS_ID", 0x36888, 0 },
+		{ "ts_id_MSB", 3, 1 },
+		{ "ts_id", 0, 3 },
+	{ "MAC_PORT_TX_TS_VAL_LO", 0x3688c, 0 },
+	{ "MAC_PORT_TX_TS_VAL_HI", 0x36890, 0 },
+	{ "MAC_PORT_EEE_CTL", 0x36894, 0 },
+		{ "EEE_CTRL", 2, 30 },
+		{ "TICK_START", 1, 1 },
+		{ "En", 0, 1 },
+	{ "MAC_PORT_EEE_TX_CTL", 0x36898, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_ACTIVE", 3, 1 },
+		{ "LPI_TXHOLD", 2, 1 },
+		{ "LPI_REQ", 1, 1 },
+		{ "EEE_TX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_RX_CTL", 0x3689c, 0 },
+		{ "WAKE_TIMER", 16, 16 },
+		{ "HSS_TIMER", 5, 4 },
+		{ "HSS_CTL", 4, 1 },
+		{ "LPI_IND", 1, 1 },
+		{ "EEE_RX_RESET", 0, 1 },
+	{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x368a0, 0 },
+	{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x368a4, 0 },
+	{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x368a8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x368b8, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x368bc, 0 },
+	{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x368c0, 0 },
+	{ "MAC_PORT_EEE_WF_COUNT", 0x368cc, 0 },
+		{ "wake_cnt_clr", 16, 1 },
+		{ "wake_cnt", 0, 16 },
+	{ "MAC_PORT_WOL_EN", 0x368d0, 0 },
+		{ "WOL_enable", 1, 1 },
+		{ "WOL_indicator", 0, 1 },
+	{ "MAC_PORT_INT_TRACE", 0x368d4, 0 },
+	{ "MAC_PORT_TRACE_TS_LO", 0x368d8, 0 },
+	{ "MAC_PORT_TRACE_TS_HI", 0x368dc, 0 },
+	{ "MAC_PORT_MTIP_10G100G_REVISION", 0x36900, 0 },
+		{ "CUSTREV", 16, 16 },
+		{ "VER", 8, 8 },
+		{ "REV", 0, 8 },
+	{ "MAC_PORT_MTIP_10G100G_SCRATCH", 0x36904, 0 },
+	{ "MAC_PORT_MTIP_10G100G_COMMAND_CONFIG", 0x36908, 0 },
+		{ "NO_PREAM", 31, 1 },
+		{ "SHORT_PREAM", 30, 1 },
+		{ "FLT_HDL_DIS", 27, 1 },
+		{ "TX_FIFO_RESET", 26, 1 },
+		{ "REG_LOWP_RXEMPTY", 24, 1 },
+		{ "TX_LOWP_ENA", 23, 1 },
+		{ "TX_FLUSH", 22, 1 },
+		{ "RX_SFD_ANY", 21, 1 },
+		{ "PAUSE_PFC_COMP", 20, 1 },
+		{ "PFC_MODE", 19, 1 },
+		{ "FORCE_SEND_IDLE", 16, 1 },
+		{ "PHY_TXENA", 15, 1 },
+		{ "CNTL_FRM_ENA", 13, 1 },
+		{ "SW_RESET", 12, 1 },
+		{ "TX_PAD_EN", 11, 1 },
+		{ "LOOP_ENA", 10, 1 },
+		{ "TX_ADDR_INS", 9, 1 },
+		{ "PAUSE_IGNORE", 8, 1 },
+		{ "PAUSE_FWD", 7, 1 },
+		{ "CRC_FWD", 6, 1 },
+		{ "PROMIS_EN", 4, 1 },
+		{ "RX_ENAMAC", 1, 1 },
+		{ "TX_ENAMAC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_0", 0x3690c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MAC_ADDR_1", 0x36910, 0 },
+	{ "MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU", 0x36914, 0 },
+		{ "SET_LEN", 16, 16 },
+		{ "FRM_LEN_SET", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS", 0x3691c, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS", 0x36920, 0 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E", 0x36924, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E", 0x36928, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS", 0x36930, 0 },
+		{ "Clk_divisor", 7, 9 },
+		{ "ENA_CLAUSE", 6, 1 },
+		{ "PREAMBLE_DISABLE", 5, 1 },
+		{ "Hold_time_setting", 2, 3 },
+		{ "MDIO_read_error", 1, 1 },
+		{ "MDIO_Busy", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_COMMAND", 0x36934, 0 },
+		{ "READ_MODE", 15, 1 },
+		{ "POST_INCR_READ", 14, 1 },
+		{ "Port_PHY_Addr", 5, 5 },
+		{ "Device_Reg_Addr", 0, 5 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_DATA", 0x36938, 0 },
+	{ "MAC_PORT_MTIP_10G100G_MDIO_REGADDR", 0x3693c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_STATUS", 0x36940, 0 },
+		{ "TX_ISIDLE", 8, 1 },
+		{ "RX_LINT_FAULT", 7, 1 },
+		{ "RX_EMPTY", 6, 1 },
+		{ "TX_EMPTY", 5, 1 },
+		{ "RX_LOWP", 4, 1 },
+		{ "TS_AVAIL", 3, 1 },
+		{ "PHY_LOS", 2, 1 },
+		{ "RX_REM_FAULT", 1, 1 },
+		{ "RX_LOC_FAULT", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH", 0x36944, 0 },
+		{ "IPG_COMP_CNT", 16, 16 },
+		{ "AVG_IPG_LEN", 2, 4 },
+		{ "DSBL_DIC", 0, 1 },
+	{ "MAC_PORT_MTIP_10G100G_CRC_MODE", 0x36948, 0 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA", 0x36954, 0 },
+		{ "CL1_PAUSE_QUANTA", 16, 16 },
+		{ "CL0_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA", 0x36958, 0 },
+		{ "CL3_PAUSE_QUANTA", 16, 16 },
+		{ "CL2_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA", 0x3695c, 0 },
+		{ "CL5_PAUSE_QUANTA", 16, 16 },
+		{ "CL4_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA", 0x36960, 0 },
+		{ "CL7_PAUSE_QUANTA", 16, 16 },
+		{ "CL6_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH", 0x36964, 0 },
+		{ "CL1_QUANTA_THRESH", 16, 16 },
+		{ "CL0_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH", 0x36968, 0 },
+		{ "CL3_QUANTA_THRESH", 16, 16 },
+		{ "CL2_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH", 0x3696c, 0 },
+		{ "CL5_QUANTA_THRESH", 16, 16 },
+		{ "CL4_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH", 0x36970, 0 },
+		{ "CL7_QUANTA_THRESH", 16, 16 },
+		{ "CL6_QUANTA_THRESH", 0, 16 },
+	{ "MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS", 0x36974, 0 },
+	{ "MAC_PORT_MTIP_10G100G_TS_TIMESTAMP", 0x3697c, 0 },
+	{ "MAC_PORT_MTIP_10G100G_XIF_MODE", 0x36980, 0 },
+		{ "RX_CNT_MODE", 16, 1 },
+		{ "TS_UPD64_MODE", 12, 1 },
+		{ "TS_BINARY_MODE", 11, 1 },
+		{ "TS_DELAY_MODE", 10, 1 },
+		{ "TS_DELTA_MODE", 9, 1 },
+		{ "TX_MAC_RS_ERR", 8, 1 },
+		{ "RX_PAUSE_BYPASS", 6, 1 },
+		{ "ONE_STEP_ENA", 5, 1 },
+		{ "PAUSETIMERX8", 4, 1 },
+		{ "XGMII_ENA", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_1", 0x36a00, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_1", 0x36a04, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID0", 0x36a08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICE_ID1", 0x36a0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SPEED_ABILITY", 0x36a10, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1", 0x36a14, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2", 0x36a18, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_CONTROL_2", 0x36a1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_STATUS_2", 0x36a20, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID0", 0x36a38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PKG_ID1", 0x36a3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_EEE_CTRL", 0x36a50, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER", 0x36a58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1", 0x36a80, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2", 0x36a84, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_0", 0x36a88, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_1", 0x36a8c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_2", 0x36a90, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_A_3", 0x36a94, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_0", 0x36a98, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_1", 0x36a9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_2", 0x36aa0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SEED_B_3", 0x36aa4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL", 0x36aa8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT", 0x36aac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT", 0x36ab0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT", 0x36ab4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1", 0x36ac8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2", 0x36acc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3", 0x36ad0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4", 0x36ad4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0", 0x36ad8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1", 0x36adc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2", 0x36ae0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3", 0x36ae4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4", 0x36ae8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5", 0x36aec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6", 0x36af0, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7", 0x36af4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8", 0x36af8, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9", 0x36afc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10", 0x36b00, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11", 0x36b04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12", 0x36b08, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13", 0x36b0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14", 0x36b10, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15", 0x36b14, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16", 0x36b18, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17", 0x36b1c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18", 0x36b20, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19", 0x36b24, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING", 0x36b28, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING", 0x36b2c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING", 0x36b30, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING", 0x36b34, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING", 0x36b38, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING", 0x36b3c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING", 0x36b40, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING", 0x36b44, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING", 0x36b48, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING", 0x36b4c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING", 0x36b50, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING", 0x36b54, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING", 0x36b58, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING", 0x36b5c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING", 0x36b60, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING", 0x36b64, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING", 0x36b68, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING", 0x36b6c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING", 0x36b70, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING", 0x36b74, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_SCRATCH", 0x36b78, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_CORE_REVISION", 0x36b7c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL_INTVL", 0x36b80, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH", 0x36b84, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_0", 0x36b98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL0_1", 0x36b9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_0", 0x36ba0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL1_1", 0x36ba4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_0", 0x36ba8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL2_1", 0x36bac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_0", 0x36bb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL3_1", 0x36bb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_PCS_MODE", 0x36bb8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_0", 0x36c98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL4_1", 0x36c9c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_0", 0x36ca0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL5_1", 0x36ca4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_0", 0x36ca8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL6_1", 0x36cac, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_0", 0x36cb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL7_1", 0x36cb4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_0", 0x36cb8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL8_1", 0x36cbc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_0", 0x36cc0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL9_1", 0x36cc4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_0", 0x36cc8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL10_1", 0x36ccc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_0", 0x36cd0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL11_1", 0x36cd4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_0", 0x36cd8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL12_1", 0x36cdc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_0", 0x36ce0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL13_1", 0x36ce4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_0", 0x36ce8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL14_1", 0x36cec, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_0", 0x36cf0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL15_1", 0x36cf4, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_0", 0x36cf8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL16_1", 0x36cfc, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_0", 0x36d00, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL17_1", 0x36d04, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_0", 0x36d08, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL18_1", 0x36d0c, 0 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_0", 0x36d10, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_0_VL19_1", 0x36d14, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_1", 0x37000, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_selection", 13, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection1", 6, 1 },
+		{ "Speed_selection2", 2, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_1", 0x37004, 0 },
+		{ "TX_LPI", 11, 1 },
+		{ "RX_LPI", 10, 1 },
+		{ "TX_LPI_ACTIVE", 9, 1 },
+		{ "RX_LPI_ACTIVE", 8, 1 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+		{ "Low_power_ability", 1, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID0", 0x37008, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICE_ID1", 0x3700c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SPEED_ABILITY", 0x37010, 0 },
+		{ "50G_capable", 5, 1 },
+		{ "25G_capable", 4, 1 },
+		{ "100G_capable", 3, 1 },
+		{ "40G_capable", 2, 1 },
+		{ "10G_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1", 0x37014, 0 },
+		{ "TC_present", 6, 1 },
+		{ "DTE_xS_present", 5, 1 },
+		{ "PHY_xS_present", 4, 1 },
+		{ "PCS_present", 3, 1 },
+		{ "WIS_present", 2, 1 },
+		{ "PMD_PMA_present", 1, 1 },
+		{ "Clause22reg_present", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2", 0x37018, 0 },
+		{ "VSD_2_PRESENT", 15, 1 },
+		{ "VSD_1_PRESENT", 14, 1 },
+		{ "Clause22_ExT_Present", 13, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_CONTROL_2", 0x3701c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_STATUS_2", 0x37020, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+		{ "50GBase_R_capable", 8, 1 },
+		{ "25GBase_R_capable", 7, 1 },
+		{ "100GBase_R_capable", 5, 1 },
+		{ "40GBase_R_capable", 4, 1 },
+		{ "10GBase_T_capable", 3, 1 },
+		{ "10GBase_W_capable", 2, 1 },
+		{ "10GBase_x_capable", 1, 1 },
+		{ "10GBase_R_capable", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID0", 0x37038, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PKG_ID1", 0x3703c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_EEE_CTRL", 0x37050, 0 },
+		{ "50GBase_R_FW", 14, 1 },
+		{ "100GBase_R_DS", 13, 1 },
+		{ "100GBase_R_FW", 12, 1 },
+		{ "25GBase_R_DS", 11, 1 },
+		{ "25GBase_R_FW", 10, 1 },
+		{ "40GBase_R_DS", 9, 1 },
+		{ "40GBase_R_FW", 8, 1 },
+		{ "10GBase_KE_EEE", 6, 1 },
+		{ "Fast_wake", 1, 5 },
+		{ "Deep_Sleep", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER", 0x37058, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1", 0x37080, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+		{ "High_BER", 1, 1 },
+		{ "Block_Lock", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2", 0x37084, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "BER_counter", 8, 6 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_0", 0x37088, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_1", 0x3708c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_2", 0x37090, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_A_3", 0x37094, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_0", 0x37098, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_1", 0x3709c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_2", 0x370a0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SEED_B_3", 0x370a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL", 0x370a8, 0 },
+		{ "Test_pattern_40G", 7, 1 },
+		{ "TX_Test_Pattern_En", 3, 1 },
+		{ "RX_Test_Pattern_En", 2, 1 },
+		{ "Test_Pattern_Select", 1, 1 },
+		{ "Data_Pattern_Select", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT", 0x370ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT", 0x370b0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT", 0x370b4, 0 },
+		{ "Hi_ORDER_CNT_Present", 15, 1 },
+		{ "ERR_BLKS_CNTR", 0, 14 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1", 0x370c8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+		{ "Lane_7_blck_lck", 7, 1 },
+		{ "Lane_6_blck_lck", 6, 1 },
+		{ "Lane_5_blck_lck", 5, 1 },
+		{ "Lane_4_blck_lck", 4, 1 },
+		{ "Lane_3_blck_lck", 3, 1 },
+		{ "Lane_2_blck_lck", 2, 1 },
+		{ "Lane_1_blck_lck", 1, 1 },
+		{ "Lane_0_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2", 0x370cc, 0 },
+		{ "Lane_19_blck_lck", 11, 1 },
+		{ "Lane_18_blck_lck", 10, 1 },
+		{ "Lane_17_blck_lck", 9, 1 },
+		{ "Lane_16_blck_lck", 8, 1 },
+		{ "Lane_15_blck_lck", 7, 1 },
+		{ "Lane_14_blck_lck", 6, 1 },
+		{ "Lane_13_blck_lck", 5, 1 },
+		{ "Lane_12_blck_lck", 4, 1 },
+		{ "Lane_11_blck_lck", 3, 1 },
+		{ "Lane_10_blck_lck", 2, 1 },
+		{ "Lane_9_blck_lck", 1, 1 },
+		{ "Lane_8_blck_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3", 0x370d0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4", 0x370d4, 0 },
+		{ "Lane19_algn_mrkr_lck", 11, 1 },
+		{ "Lane18_algn_mrkr_lck", 10, 1 },
+		{ "Lane17_algn_mrkr_lck", 9, 1 },
+		{ "Lane16_algn_mrkr_lck", 8, 1 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0", 0x370d8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1", 0x370dc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2", 0x370e0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3", 0x370e4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4", 0x370e8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5", 0x370ec, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6", 0x370f0, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7", 0x370f4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8", 0x370f8, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9", 0x370fc, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10", 0x37100, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11", 0x37104, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12", 0x37108, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13", 0x3710c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14", 0x37110, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15", 0x37114, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16", 0x37118, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17", 0x3711c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18", 0x37120, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19", 0x37124, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING", 0x37128, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING", 0x3712c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING", 0x37130, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING", 0x37134, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING", 0x37138, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING", 0x3713c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING", 0x37140, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING", 0x37144, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING", 0x37148, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING", 0x3714c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING", 0x37150, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING", 0x37154, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING", 0x37158, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING", 0x3715c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING", 0x37160, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING", 0x37164, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING", 0x37168, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING", 0x3716c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING", 0x37170, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING", 0x37174, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_SCRATCH", 0x37178, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_CORE_REVISION", 0x3717c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL_INTVL", 0x37180, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH", 0x37184, 0 },
+		{ "lane6_lane7", 12, 4 },
+		{ "lane4_lane5", 8, 4 },
+		{ "lane2_lane3", 4, 4 },
+		{ "lane0_lane1", 0, 4 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_0", 0x37198, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL0_1", 0x3719c, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_0", 0x371a0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL1_1", 0x371a4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_0", 0x371a8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL2_1", 0x371ac, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_0", 0x371b0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_PORT_MTIP_CR4_1_VL3_1", 0x371b4, 0 },
+	{ "MAC_PORT_MTIP_CR4_1_PCS_MODE", 0x371b8, 0 },
+		{ "st_disable_mld", 9, 1 },
+		{ "st_en_clause49", 8, 1 },
+		{ "Hi_ber25", 2, 1 },
+		{ "Disable_mld", 1, 1 },
+		{ "ena_clause49", 0, 1 },
+	{ "MAC_COMMON_CFG_0", 0x38000, 0 },
+		{ "Rx_Polarity_Inv", 24, 8 },
+		{ "Tx_Polarity_Inv", 16, 8 },
+		{ "debug_port_sel", 14, 2 },
+		{ "MAC_septy_ctl", 8, 6 },
+		{ "debug_tx_rx_sel", 7, 1 },
+		{ "MAC_rdy_ctl", 0, 6 },
+	{ "MAC_MTIP_RESET_CTRL_0", 0x38004, 0 },
+		{ "reset_f91_ref_clk_i", 31, 1 },
+		{ "reset_pcs000_ref_clk_i", 30, 1 },
+		{ "reset_ref_clk_i", 29, 1 },
+		{ "reset_sd_rx_clk_i_0", 28, 1 },
+		{ "reset_sd_rx_clk_i_1", 27, 1 },
+		{ "reset_sd_rx_clk_i_2", 26, 1 },
+		{ "reset_sd_rx_clk_i_3", 25, 1 },
+		{ "reset_sd_rx_clk_i_4", 24, 1 },
+		{ "reset_sd_rx_clk_i_5", 23, 1 },
+		{ "reset_sd_rx_clk_i_6", 22, 1 },
+		{ "reset_sd_rx_clk_i_7", 21, 1 },
+		{ "reset_sd_tx_clk_i_0", 20, 1 },
+		{ "reset_sd_tx_clk_i_1", 19, 1 },
+		{ "reset_sd_tx_clk_i_2", 18, 1 },
+		{ "reset_sd_tx_clk_i_3", 17, 1 },
+		{ "reset_sd_tx_clk_i_4", 16, 1 },
+		{ "reset_sd_tx_clk_i_5", 15, 1 },
+		{ "reset_sd_tx_clk_i_6", 14, 1 },
+		{ "reset_sd_tx_clk_i_7", 13, 1 },
+		{ "reset_xpcs_ref_clk_i_0", 12, 1 },
+		{ "reset_xpcs_ref_clk_i_1", 11, 1 },
+		{ "reset_ff_rx_clk_0_i", 9, 1 },
+		{ "reset_ff_tx_clk_0_i", 8, 1 },
+		{ "reset_rxclk_0_i", 7, 1 },
+		{ "reset_txclk_0_i", 6, 1 },
+		{ "reset_ff_rx_clk_1_i", 5, 1 },
+		{ "reset_ff_tx_clk_1_i", 4, 1 },
+		{ "reset_rxclk_1_i", 3, 1 },
+		{ "reset_txclk_1_i", 2, 1 },
+		{ "xgmii_clk_reset_0", 0, 1 },
+	{ "MAC_MTIP_RESET_CTRL_1", 0x38008, 0 },
+		{ "reset_ff_rx_clk_2_i", 31, 1 },
+		{ "reset_ff_tx_clk_2_i", 30, 1 },
+		{ "reset_rxclk_2_i", 29, 1 },
+		{ "reset_txclk_2_i", 28, 1 },
+		{ "reset_ff_rx_clk_3_i", 27, 1 },
+		{ "reset_ff_tx_clk_3_i", 26, 1 },
+		{ "reset_rxclk_3_i", 25, 1 },
+		{ "reset_txclk_3_i", 24, 1 },
+		{ "reset_ff_rx_clk_4_i", 23, 1 },
+		{ "reset_ff_tx_clk_4_i", 22, 1 },
+		{ "reset_rxclk_4_i", 21, 1 },
+		{ "reset_txclk_4_i", 20, 1 },
+		{ "reset_ff_rx_clk_5_i", 19, 1 },
+		{ "reset_ff_tx_clk_5_i", 18, 1 },
+		{ "reset_rxclk_5_i", 17, 1 },
+		{ "reset_txclk_5_i", 16, 1 },
+		{ "reset_sd_rx_clk_an_0_i", 15, 1 },
+		{ "reset_sd_tx_clk_an_0_i", 14, 1 },
+		{ "reset_sd_rx_clk_an_1_i", 13, 1 },
+		{ "reset_sd_tx_clk_an_1_i", 12, 1 },
+		{ "reset_sd_rx_clk_an_2_i", 11, 1 },
+		{ "reset_sd_tx_clk_an_2_i", 10, 1 },
+		{ "reset_sd_rx_clk_an_3_i", 9, 1 },
+		{ "reset_sd_tx_clk_an_3_i", 8, 1 },
+		{ "reset_sd_rx_clk_an_4_i", 7, 1 },
+		{ "reset_sd_tx_clk_an_4_i", 6, 1 },
+		{ "reset_sd_rx_clk_an_5_i", 5, 1 },
+		{ "reset_sd_tx_clk_an_5_i", 4, 1 },
+		{ "reset_sd_rx_clk_an_6_i", 3, 1 },
+		{ "reset_sd_tx_clk_an_6_i", 2, 1 },
+		{ "reset_sd_rx_clk_an_7_i", 1, 1 },
+		{ "reset_sd_tx_clk_an_7_i", 0, 1 },
+	{ "MAC_MTIP_RESET_CTRL_2", 0x3800c, 0 },
+		{ "reset_sgmii_txclk_i_3", 31, 1 },
+		{ "reset_sgmii_rxclk_i_3", 30, 1 },
+		{ "reset_sgmii_txclk_i_2", 29, 1 },
+		{ "reset_sgmii_rxclk_i_2", 28, 1 },
+		{ "reset_sgmii_txclk_i_1", 27, 1 },
+		{ "reset_sgmii_rxclk_i_1", 26, 1 },
+		{ "reset_sgmii_txclk_i_0", 25, 1 },
+		{ "reset_sgmii_rxclk_i_0", 24, 1 },
+		{ "MtipSd7TxRst", 23, 1 },
+		{ "MtipSd6TxRst", 22, 1 },
+		{ "MtipSd5TxRst", 21, 1 },
+		{ "MtipSd4TxRst", 20, 1 },
+		{ "MtipSd3TxRst", 19, 1 },
+		{ "MtipSd2TxRst", 18, 1 },
+		{ "MtipSd1TxRst", 17, 1 },
+		{ "MtipSd0TxRst", 16, 1 },
+		{ "MtipSd7RxRst", 15, 1 },
+		{ "MtipSd6RxRst", 14, 1 },
+		{ "MtipSd5RxRst", 13, 1 },
+		{ "MtipSd4RxRst", 12, 1 },
+		{ "MtipSd3RxRst", 11, 1 },
+		{ "MtipSd2RxRst", 10, 1 },
+		{ "MtipSd1RxRst", 9, 1 },
+		{ "MtipSd0RxRst", 8, 1 },
+		{ "reset_reg_clk_an_0_i", 7, 1 },
+		{ "reset_reg_clk_an_1_i", 6, 1 },
+		{ "reset_reg_clk_an_2_i", 5, 1 },
+		{ "reset_reg_clk_an_3_i", 4, 1 },
+		{ "reset_reg_clk_an_4_i", 3, 1 },
+		{ "reset_reg_clk_an_5_i", 2, 1 },
+		{ "reset_reg_clk_an_6_i", 1, 1 },
+		{ "reset_reg_clk_an_7_i", 0, 1 },
+	{ "MAC_MTIP_CLK_CTRL_0", 0x38010, 0 },
+		{ "f91_ref_clk_i_g", 31, 1 },
+		{ "pcs000_ref_clk_i_g", 30, 1 },
+		{ "ref_clk_i_g", 29, 1 },
+		{ "sd_rx_clk_i_0_g", 28, 1 },
+		{ "sd_rx_clk_i_1_g", 27, 1 },
+		{ "sd_rx_clk_i_2_g", 26, 1 },
+		{ "sd_rx_clk_i_3_g", 25, 1 },
+		{ "sd_rx_clk_i_4_g", 24, 1 },
+		{ "sd_rx_clk_i_5_g", 23, 1 },
+		{ "sd_rx_clk_i_6_g", 22, 1 },
+		{ "sd_rx_clk_i_7_g", 21, 1 },
+		{ "sd_tx_clk_i_0_g", 20, 1 },
+		{ "sd_tx_clk_i_1_g", 19, 1 },
+		{ "sd_tx_clk_i_2_g", 18, 1 },
+		{ "sd_tx_clk_i_3_g", 17, 1 },
+		{ "sd_tx_clk_i_4_g", 16, 1 },
+		{ "sd_tx_clk_i_5_g", 15, 1 },
+		{ "sd_tx_clk_i_6_g", 14, 1 },
+		{ "sd_tx_clk_i_7_g", 13, 1 },
+		{ "xpcs_ref_clk_i_0_g", 12, 1 },
+		{ "xpcs_ref_clk_i_1_g", 11, 1 },
+		{ "reg_clk_i_g", 10, 1 },
+		{ "ff_rx_clk_0_i_g", 9, 1 },
+		{ "ff_tx_clk_0_i_g", 8, 1 },
+		{ "rxclk_0_i_g", 7, 1 },
+		{ "txclk_0_i_g", 6, 1 },
+		{ "ff_rx_clk_1_i_g", 5, 1 },
+		{ "ff_tx_clk_1_i_g", 4, 1 },
+		{ "rxclk_1_i_g", 3, 1 },
+		{ "txclk_1_i_g", 2, 1 },
+	{ "MAC_MTIP_CLK_CTRL_1", 0x38014, 0 },
+		{ "ff_rx_clk_2_i_g", 31, 1 },
+		{ "ff_tx_clk_2_i_g", 30, 1 },
+		{ "rxclk_2_i_g", 29, 1 },
+		{ "txclk_2_i_g", 28, 1 },
+		{ "ff_rx_clk_3_i_g", 27, 1 },
+		{ "ff_tx_clk_3_i_g", 26, 1 },
+		{ "rxclk_3_i_g", 25, 1 },
+		{ "txclk_3_i_g", 24, 1 },
+		{ "ff_rx_clk_4_i_g", 23, 1 },
+		{ "ff_tx_clk_4_i_g", 22, 1 },
+		{ "rxclk_4_i_g", 21, 1 },
+		{ "txclk_4_i_g", 20, 1 },
+		{ "ff_rx_clk_5_i_g", 19, 1 },
+		{ "ff_tx_clk_5_i_g", 18, 1 },
+		{ "rxclk_5_i_g", 17, 1 },
+		{ "txclk_5_i_g", 16, 1 },
+		{ "sd_rx_clk_an_0_i_g", 15, 1 },
+		{ "sd_tx_clk_an_0_i_g", 14, 1 },
+		{ "sd_rx_clk_an_1_i_g", 13, 1 },
+		{ "sd_tx_clk_an_1_i_g", 12, 1 },
+		{ "sd_rx_clk_an_2_i_g", 11, 1 },
+		{ "sd_tx_clk_an_2_i_g", 10, 1 },
+		{ "sd_rx_clk_an_3_i_g", 9, 1 },
+		{ "sd_tx_clk_an_3_i_g", 8, 1 },
+		{ "sd_rx_clk_an_4_i_g", 7, 1 },
+		{ "sd_tx_clk_an_4_i_g", 6, 1 },
+		{ "sd_rx_clk_an_5_i_g", 5, 1 },
+		{ "sd_tx_clk_an_5_i_g", 4, 1 },
+		{ "sd_rx_clk_an_6_i_g", 3, 1 },
+		{ "sd_tx_clk_an_6_i_g", 2, 1 },
+		{ "sd_rx_clk_an_7_i_g", 1, 1 },
+		{ "sd_tx_clk_an_7_i_g", 0, 1 },
+	{ "MAC_MTIP_CLK_CTRL_2", 0x38018, 0 },
+		{ "sd_rx_clk_0_g", 31, 1 },
+		{ "sd_rx_clk_1_g", 30, 1 },
+		{ "sd_rx_clk_2_g", 29, 1 },
+		{ "sd_rx_clk_3_g", 28, 1 },
+		{ "sd_rx_clk_4_g", 27, 1 },
+		{ "sd_rx_clk_5_g", 26, 1 },
+		{ "sd_rx_clk_6_g", 25, 1 },
+		{ "sd_rx_clk_7_g", 24, 1 },
+		{ "sd_tx_clk_0_g", 23, 1 },
+		{ "sd_tx_clk_1_g", 22, 1 },
+		{ "sd_tx_clk_2_g", 21, 1 },
+		{ "sd_tx_clk_3_g", 20, 1 },
+		{ "sd_tx_clk_4_g", 19, 1 },
+		{ "sd_tx_clk_5_g", 18, 1 },
+		{ "sd_tx_clk_6_g", 17, 1 },
+		{ "sd_tx_clk_7_g", 16, 1 },
+		{ "sd_rx_clk_aec_0_g", 15, 1 },
+		{ "sd_rx_clk_aec_1_g", 14, 1 },
+		{ "sd_rx_clk_aec_2_g", 13, 1 },
+		{ "sd_rx_clk_aec_3_g", 12, 1 },
+		{ "sd_rx_clk_aec_4_g", 11, 1 },
+		{ "sd_rx_clk_aec_5_g", 10, 1 },
+		{ "sd_rx_clk_aec_6_g", 9, 1 },
+		{ "sd_rx_clk_aec_7_g", 8, 1 },
+		{ "sd_tx_clk_aec_0_g", 7, 1 },
+		{ "sd_tx_clk_aec_1_g", 6, 1 },
+		{ "sd_tx_clk_aec_2_g", 5, 1 },
+		{ "sd_tx_clk_aec_3_g", 4, 1 },
+		{ "sd_tx_clk_aec_4_g", 3, 1 },
+		{ "sd_tx_clk_aec_5_g", 2, 1 },
+		{ "sd_tx_clk_aec_6_g", 1, 1 },
+		{ "sd_tx_clk_aec_7_g", 0, 1 },
+	{ "MAC_MTIP_CLK_CTRL_3", 0x3801c, 0 },
+		{ "pcs_rx_clk_0_g", 31, 1 },
+		{ "pcs_rx_clk_1_g", 30, 1 },
+		{ "pcs_rx_clk_2_g", 29, 1 },
+		{ "pcs_rx_clk_3_g", 28, 1 },
+		{ "pcs_rx_clk_4_g", 27, 1 },
+		{ "pcs_rx_clk_5_g", 26, 1 },
+		{ "pcs_rx_clk_6_g", 25, 1 },
+		{ "pcs_rx_clk_7_g", 24, 1 },
+		{ "pcs_tx_clk_0_g", 23, 1 },
+		{ "pcs_tx_clk_1_g", 22, 1 },
+		{ "pcs_tx_clk_2_g", 21, 1 },
+		{ "pcs_tx_clk_3_g", 20, 1 },
+		{ "pcs_tx_clk_4_g", 19, 1 },
+		{ "pcs_tx_clk_5_g", 18, 1 },
+		{ "pcs_tx_clk_6_g", 17, 1 },
+		{ "pcs_tx_clk_7_g", 16, 1 },
+		{ "sd_rx_clk_en_0", 15, 1 },
+		{ "sd_rx_clk_en_1", 14, 1 },
+		{ "sd_rx_clk_en_2", 13, 1 },
+		{ "sd_rx_clk_en_3", 12, 1 },
+		{ "sd_rx_clk_en_4", 11, 1 },
+		{ "sd_rx_clk_en_5", 10, 1 },
+		{ "sd_rx_clk_en_6", 9, 1 },
+		{ "sd_rx_clk_en_7", 8, 1 },
+		{ "sd_tx_clk_en_0", 7, 1 },
+		{ "sd_tx_clk_en_1", 6, 1 },
+		{ "sd_tx_clk_en_2", 5, 1 },
+		{ "sd_tx_clk_en_3", 4, 1 },
+		{ "sd_tx_clk_en_4", 3, 1 },
+		{ "sd_tx_clk_en_5", 2, 1 },
+		{ "sd_tx_clk_en_6", 1, 1 },
+		{ "sd_tx_clk_en_7", 0, 1 },
+	{ "MAC_MTIP_CLK_CTRL_4", 0x38020, 0 },
+		{ "sgmii_tx_clk_0_g", 7, 1 },
+		{ "sgmii_tx_clk_1_g", 6, 1 },
+		{ "sgmii_tx_clk_2_g", 5, 1 },
+		{ "sgmii_tx_clk_3_g", 4, 1 },
+		{ "sgmii_rx_clk_0_g", 3, 1 },
+		{ "sgmii_rx_clk_1_g", 2, 1 },
+		{ "sgmii_rx_clk_2_g", 1, 1 },
+		{ "sgmii_rx_clk_3_g", 0, 1 },
+	{ "MAC_PCS_CONFIG_0", 0x38024, 0 },
+		{ "kp_mode_in", 24, 8 },
+		{ "fec91_ena_in", 16, 8 },
+		{ "sd_8x", 8, 8 },
+		{ "sd_n2", 0, 8 },
+	{ "MAC_PCS_CONFIG_1", 0x38028, 0 },
+		{ "fast_1lane_mode", 24, 8 },
+		{ "pacer_10g", 16, 8 },
+		{ "pcs400_ena_in", 14, 2 },
+		{ "mode40_ena_in4", 13, 1 },
+		{ "mode40_ena_in0", 12, 1 },
+		{ "pcs100_ena_in6", 11, 1 },
+		{ "pcs100_ena_in4", 10, 1 },
+		{ "pcs100_ena_in2", 9, 1 },
+		{ "pcs100_ena_in0", 8, 1 },
+		{ "rxlaui_ena_in6", 7, 1 },
+		{ "rxlaui_ena_in4", 6, 1 },
+		{ "rxlaui_ena_in2", 5, 1 },
+		{ "rxlaui_ena_in0", 4, 1 },
+		{ "fec91_lane_in6", 3, 1 },
+		{ "fec91_lane_in4", 2, 1 },
+		{ "fec91_lane_in2", 1, 1 },
+		{ "fec91_lane_in0", 0, 1 },
+	{ "MAC_PCS_CONFIG_2", 0x3802c, 0 },
+		{ "sgpcs_en_3", 29, 1 },
+		{ "sgpcs_en_2", 28, 1 },
+		{ "sgpcs_en_1", 27, 1 },
+		{ "sgpcs_en_0", 26, 1 },
+		{ "cfg_clock_rate", 22, 4 },
+		{ "fec_err_ena", 14, 8 },
+		{ "fec_ena", 6, 8 },
+		{ "pcs001_tx_am_sf", 3, 3 },
+		{ "pcs000_tx_am_sf", 0, 3 },
+	{ "MAC_PCS_STATUS_0", 0x38030, 0 },
+		{ "pcs000_align_lock", 30, 2 },
+		{ "pcs000_hi_ser", 28, 2 },
+		{ "ber_timer_done", 20, 8 },
+		{ "amps_lock", 4, 16 },
+		{ "align_done", 0, 4 },
+	{ "MAC_PCS_STATUS_1", 0x38034, 0 },
+	{ "MAC_PCS_STATUS_2", 0x38038, 0 },
+		{ "rsfec_aligned", 24, 8 },
+		{ "fec_locked", 8, 16 },
+		{ "block_lock", 0, 8 },
+	{ "MAC_PCS_STATUS_3", 0x3803c, 0 },
+		{ "fec_ncerr", 16, 16 },
+		{ "fec_cerr", 0, 16 },
+	{ "MAC_PCS_STATUS_4", 0x38040, 0 },
+		{ "mac1_res_speed", 23, 8 },
+		{ "mac0_res_speed", 14, 8 },
+		{ "pcs400_ena_in_ref", 12, 2 },
+		{ "pcs000_degrade_ser", 10, 2 },
+		{ "p4x_signal_ok", 8, 2 },
+		{ "mode200_ind_ref", 7, 1 },
+		{ "mode200_8x26_ind_ref", 6, 1 },
+		{ "pcs001_rx_am_sf", 3, 3 },
+		{ "pcs000_rx_am_sf", 0, 3 },
+	{ "MAC_PCS_STATUS_5", 0x38044, 0 },
+		{ "mac5_res_speed", 24, 8 },
+		{ "mac4_res_speed", 16, 8 },
+		{ "mac3_res_speed", 8, 8 },
+		{ "mac2_res_speed", 0, 8 },
+	{ "MAC_PCS_STATUS_6", 0x38048, 0 },
+		{ "marker_ins_cnt_100_00", 16, 15 },
+		{ "mac7_res_speed", 8, 8 },
+		{ "mac6_res_speed", 0, 8 },
+	{ "MAC_PCS_STATUS_7", 0x3804c, 0 },
+		{ "pcs000_link_status", 30, 2 },
+		{ "marker_ins_cnt_100_02", 15, 15 },
+		{ "marker_ins_cnt_100_01", 0, 15 },
+	{ "MAC_PCS_STATUS_8", 0x38050, 0 },
+		{ "marker_ins_cnt_25_1", 15, 16 },
+		{ "marker_ins_cnt_100_03", 0, 15 },
+	{ "MAC_PCS_STATUS_9", 0x38054, 0 },
+		{ "marker_ins_cnt_25_5", 16, 16 },
+		{ "marker_ins_cnt_25_3", 0, 16 },
+	{ "MAC_PCS_STATUS_10", 0x38058, 0 },
+		{ "marker_ins_cnt_25_50_2", 16, 16 },
+		{ "marker_ins_cnt_25_50_0", 0, 16 },
+	{ "MAC_PCS_STATUS_11", 0x3805c, 0 },
+		{ "marker_ins_cnt_25_50_6", 16, 16 },
+		{ "marker_ins_cnt_25_50_4", 0, 16 },
+	{ "MAC_PCS_STATUS_12", 0x38060, 0 },
+		{ "link_status", 24, 8 },
+		{ "hi_ber", 16, 8 },
+		{ "marker_ins_cnt_25_7", 0, 16 },
+	{ "MAC_MAC200G400G_0_CONFIG_0", 0x38064, 0 },
+		{ "peer_delay_val", 31, 1 },
+		{ "peer_delay", 1, 30 },
+		{ "mode1s_ena", 0, 1 },
+	{ "MAC_MAC200G400G_0_CONFIG_1", 0x38068, 0 },
+		{ "tx_ts_id", 12, 12 },
+		{ "ff_tx_crc_ovr", 11, 1 },
+		{ "xoff_gen", 3, 8 },
+		{ "tx_smhold", 2, 1 },
+		{ "tx_rem_fault", 1, 1 },
+		{ "tx_loc_fault", 0, 1 },
+	{ "MAC_MAC200G400G_0_CONFIG_2", 0x3806c, 0 },
+	{ "MAC_MAC200G400G_0_CONFIG_3", 0x38070, 0 },
+	{ "MAC_MAC200G400G_0_CONFIG_4", 0x38074, 0 },
+	{ "MAC_MAC200G400G_0_STATUS", 0x38078, 0 },
+		{ "tx_isidle", 19, 1 },
+		{ "tx_underflow", 18, 1 },
+		{ "tx_empty", 17, 1 },
+		{ "rem_fault", 16, 1 },
+		{ "reg_ts_avail", 15, 1 },
+		{ "phy_txena", 14, 1 },
+		{ "pfc_mode", 13, 1 },
+		{ "pause_on", 5, 8 },
+		{ "loop_ena", 4, 1 },
+		{ "loc_fault", 3, 1 },
+		{ "frm_drop", 2, 1 },
+		{ "ff_tx_credit", 1, 1 },
+		{ "ff_rx_empty", 0, 1 },
+	{ "MAC_MAC200G400G_1_CONFIG_0", 0x3807c, 0 },
+		{ "peer_delay_val", 31, 1 },
+		{ "peer_delay", 1, 30 },
+		{ "mode1s_ena", 0, 1 },
+	{ "MAC_MAC200G400G_1_CONFIG_1", 0x38080, 0 },
+		{ "tx_ts_id", 12, 12 },
+		{ "ff_tx_crc_ovr", 11, 1 },
+		{ "xoff_gen", 3, 8 },
+		{ "tx_smhold", 2, 1 },
+		{ "tx_rem_fault", 1, 1 },
+		{ "tx_loc_fault", 0, 1 },
+	{ "MAC_MAC200G400G_1_CONFIG_2", 0x38084, 0 },
+	{ "MAC_MAC200G400G_1_CONFIG_3", 0x38088, 0 },
+	{ "MAC_MAC200G400G_1_CONFIG_4", 0x3808c, 0 },
+	{ "MAC_MAC200G400G_1_STATUS", 0x38090, 0 },
+		{ "tx_isidle", 19, 1 },
+		{ "tx_underflow", 18, 1 },
+		{ "tx_empty", 17, 1 },
+		{ "rem_fault", 16, 1 },
+		{ "reg_ts_avail", 15, 1 },
+		{ "phy_txena", 14, 1 },
+		{ "pfc_mode", 13, 1 },
+		{ "pause_on", 5, 8 },
+		{ "loop_ena", 4, 1 },
+		{ "loc_fault", 3, 1 },
+		{ "frm_drop", 2, 1 },
+		{ "ff_tx_credit", 1, 1 },
+		{ "ff_rx_empty", 0, 1 },
+	{ "MAC_AN_CFG_0", 0x38094, 0 },
+		{ "an_data_ctl", 24, 8 },
+		{ "an_ena", 16, 8 },
+	{ "MAC_AN_CFG_1", 0x38098, 0 },
+		{ "an_dis_timer_an_7", 7, 1 },
+		{ "an_dis_timer_an_6", 6, 1 },
+		{ "an_dis_timer_an_5", 5, 1 },
+		{ "an_dis_timer_an_4", 4, 1 },
+		{ "an_dis_timer_an_3", 3, 1 },
+		{ "an_dis_timer_an_2", 2, 1 },
+		{ "an_dis_timer_an_1", 1, 1 },
+		{ "an_dis_timer_an_0", 0, 1 },
+	{ "MAC_AN_SERDES25G_ENA", 0x3809c, 0 },
+		{ "an_sd25_tx_ena_7", 15, 1 },
+		{ "an_sd25_tx_ena_6", 14, 1 },
+		{ "an_sd25_tx_ena_5", 13, 1 },
+		{ "an_sd25_tx_ena_4", 12, 1 },
+		{ "an_sd25_tx_ena_3", 11, 1 },
+		{ "an_sd25_tx_ena_2", 10, 1 },
+		{ "an_sd25_tx_ena_1", 9, 1 },
+		{ "an_sd25_tx_ena_0", 8, 1 },
+		{ "an_sd25_rx_ena_7", 7, 1 },
+		{ "an_sd25_rx_ena_6", 6, 1 },
+		{ "an_sd25_rx_ena_5", 5, 1 },
+		{ "an_sd25_rx_ena_4", 4, 1 },
+		{ "an_sd25_rx_ena_3", 3, 1 },
+		{ "an_sd25_rx_ena_2", 2, 1 },
+		{ "an_sd25_rx_ena_1", 1, 1 },
+		{ "an_sd25_rx_ena_0", 0, 1 },
+	{ "MAC_PLL_CFG_0", 0x380a0, 0 },
+		{ "USE_RX_CDR_CLK_FOR_TX", 7, 1 },
+		{ "HSSPLLSEL0", 5, 2 },
+		{ "HSSTXDIV2CLK_SEL0", 3, 2 },
+		{ "HSS_Reset0", 2, 1 },
+		{ "APB_RESET0", 1, 1 },
+		{ "HSSCLK32DIV2_RESET0", 0, 1 },
+	{ "MAC_PLL_CFG_1", 0x380a4, 0 },
+		{ "USE_RX_CDR_CLK_FOR_TX", 7, 1 },
+		{ "HSSPLLSEL1", 5, 2 },
+		{ "HSSTXDIV2CLK_SEL1", 3, 2 },
+		{ "HSS_Reset1", 2, 1 },
+		{ "APB_RESET1", 1, 1 },
+		{ "HSSCLK32DIV2_RESET1", 0, 1 },
+	{ "MAC_PLL_CFG_2", 0x380a8, 0 },
+		{ "USE_RX_CDR_CLK_FOR_TX", 7, 1 },
+		{ "HSSPLLSEL2", 5, 2 },
+		{ "HSSTXDIV2CLK_SEL2", 3, 2 },
+		{ "HSS_Reset2", 2, 1 },
+		{ "APB_RESET2", 1, 1 },
+		{ "HSSCLK32DIV2_RESET2", 0, 1 },
+	{ "MAC_PLL_CFG_3", 0x380ac, 0 },
+		{ "USE_RX_CDR_CLK_FOR_TX", 7, 1 },
+		{ "HSSPLLSEL3", 5, 2 },
+		{ "HSSTXDIV2CLK_SEL3", 3, 2 },
+		{ "HSS_Reset3", 2, 1 },
+		{ "APB_RESET3", 1, 1 },
+		{ "HSSCLK32DIV2_RESET3", 0, 1 },
+	{ "MAC_HSS_STATUS", 0x380b0, 0 },
+		{ "tx_lane_pll_sel_3", 30, 2 },
+		{ "tx_lane_pll_sel_2", 28, 2 },
+		{ "tx_lane_pll_sel_1", 26, 2 },
+		{ "tx_lane_pll_sel_0", 24, 2 },
+		{ "HSSPLLLOCKB_HSS3", 7, 1 },
+		{ "HSSPLLLOCKA_HSS3", 6, 1 },
+		{ "HSSPLLLOCKB_HSS2", 5, 1 },
+		{ "HSSPLLLOCKA_HSS2", 4, 1 },
+		{ "HSSPLLLOCKB_HSS1", 3, 1 },
+		{ "HSSPLLLOCKA_HSS1", 2, 1 },
+		{ "HSSPLLLOCKB_HSS0", 1, 1 },
+		{ "HSSPLLLOCKA_HSS0", 0, 1 },
+	{ "MAC_HSS_SIGDET_STATUS", 0x380b4, 0 },
+		{ "HSS3_sigdet", 6, 2 },
+		{ "HSS2_sigdet", 4, 2 },
+		{ "HSS1_sigdet", 2, 2 },
+		{ "HSS0_sigdet", 0, 2 },
+	{ "MAC_FPGA_CFG_0", 0x380b8, 0 },
+	{ "MAC_PMD_STATUS", 0x380bc, 0 },
+	{ "MAC_PMD_AN_CONFIG0", 0x380c0, 0 },
+		{ "AN3_RATE_SELECT", 25, 5 },
+		{ "AN3_STATUS", 24, 1 },
+		{ "AN2_RATE_SELECT", 17, 5 },
+		{ "AN2_STATUS", 16, 1 },
+		{ "AN1_RATE_SELECT", 9, 5 },
+		{ "AN1_STATUS", 8, 1 },
+		{ "AN0_RATE_SELECT", 1, 5 },
+		{ "AN0_STATUS", 0, 1 },
+	{ "MAC_PMD_AN_CONFIG1", 0x380c4, 0 },
+		{ "AN7_RATE_SELECT", 25, 5 },
+		{ "AN7_STATUS", 24, 1 },
+		{ "AN6_RATE_SELECT", 17, 5 },
+		{ "AN6_STATUS", 16, 1 },
+		{ "AN5_RATE_SELECT", 9, 5 },
+		{ "AN5_STATUS", 8, 1 },
+		{ "AN4_RATE_SELECT", 1, 5 },
+		{ "AN4_STATUS", 0, 1 },
+	{ "MAC_INT_EN_CMN", 0x380c8, 0 },
+		{ "HSS3PLL1_LOCK_LOST", 21, 1 },
+		{ "HSS3PLL1_LOCK", 20, 1 },
+		{ "HSS3PLL0_LOCK_LOST", 19, 1 },
+		{ "HSS3PLL0_LOCK", 18, 1 },
+		{ "HSS2PLL1_LOCK_LOST", 17, 1 },
+		{ "HSS2PLL1_LOCK", 16, 1 },
+		{ "HSS2PLL0_LOCK_LOST", 15, 1 },
+		{ "HSS2PLL0_LOCK", 14, 1 },
+		{ "HSS1PLL1_LOCK_LOST", 13, 1 },
+		{ "HSS1PLL1_LOCK", 12, 1 },
+		{ "HSS1PLL0_LOCK_LOST", 11, 1 },
+		{ "HSS1PLL0_LOCK", 10, 1 },
+		{ "HSS0PLL1_LOCK_LOST", 9, 1 },
+		{ "HSS0PLL1_LOCK", 8, 1 },
+		{ "HSS0PLL0_LOCK_LOST", 7, 1 },
+		{ "HSS0PLL0_LOCK", 6, 1 },
+		{ "flock_asserted", 5, 1 },
+		{ "flock_lost", 4, 1 },
+		{ "phase_lock_asserted", 3, 1 },
+		{ "phase_lock_lost", 2, 1 },
+		{ "lock_asserted", 1, 1 },
+		{ "lock_lost", 0, 1 },
+	{ "MAC_INT_CAUSE_CMN", 0x380cc, 0 },
+		{ "HSS3PLL1_LOCK_LOST", 21, 1 },
+		{ "HSS3PLL1_LOCK", 20, 1 },
+		{ "HSS3PLL0_LOCK_LOST", 19, 1 },
+		{ "HSS3PLL0_LOCK", 18, 1 },
+		{ "HSS2PLL1_LOCK_LOST", 17, 1 },
+		{ "HSS2PLL1_LOCK", 16, 1 },
+		{ "HSS2PLL0_LOCK_LOST", 15, 1 },
+		{ "HSS2PLL0_LOCK", 14, 1 },
+		{ "HSS1PLL1_LOCK_LOST", 13, 1 },
+		{ "HSS1PLL1_LOCK", 12, 1 },
+		{ "HSS1PLL0_LOCK_LOST", 11, 1 },
+		{ "HSS1PLL0_LOCK", 10, 1 },
+		{ "HSS0PLL1_LOCK_LOST", 9, 1 },
+		{ "HSS0PLL1_LOCK", 8, 1 },
+		{ "HSS0PLL0_LOCK_LOST", 7, 1 },
+		{ "HSS0PLL0_LOCK", 6, 1 },
+		{ "flock_asserted", 5, 1 },
+		{ "flock_lost", 4, 1 },
+		{ "phase_lock_asserted", 3, 1 },
+		{ "phase_lock_lost", 2, 1 },
+		{ "lock_asserted", 1, 1 },
+		{ "lock_lost", 0, 1 },
+	{ "MAC_PERR_INT_EN_MTIP", 0x380d0, 0 },
+		{ "rx_mac40g", 28, 1 },
+		{ "tx_mac40g", 27, 1 },
+		{ "rx_st_mac40g", 26, 1 },
+		{ "tx_st_mac40g", 25, 1 },
+		{ "tx_mac1g10g", 24, 1 },
+		{ "rx_mac1g10g", 23, 1 },
+		{ "rx_status_mac1g10g", 22, 1 },
+		{ "rx_st_mac1g10g", 21, 1 },
+		{ "tx_st_mac1g10g", 20, 1 },
+		{ "Perr_mac0_tx", 19, 1 },
+		{ "Perr_mac1_tx", 18, 1 },
+		{ "Perr_mac2_tx", 17, 1 },
+		{ "Perr_mac3_tx", 16, 1 },
+		{ "Perr_mac4_tx", 15, 1 },
+		{ "Perr_mac5_tx", 14, 1 },
+		{ "Perr_mac0_rx", 13, 1 },
+		{ "Perr_mac1_rx", 12, 1 },
+		{ "Perr_mac2_rx", 11, 1 },
+		{ "Perr_mac3_rx", 10, 1 },
+		{ "Perr_mac4_rx", 9, 1 },
+		{ "Perr_mac5_rx", 8, 1 },
+		{ "Perr_mac_stat2_rx", 7, 1 },
+		{ "Perr_mac_stat3_rx", 6, 1 },
+		{ "Perr_mac_stat4_rx", 5, 1 },
+		{ "Perr_mac_stat5_rx", 4, 1 },
+		{ "Perr_mac_stat2_tx", 3, 1 },
+		{ "Perr_mac_stat3_tx", 2, 1 },
+		{ "Perr_mac_stat4_tx", 1, 1 },
+		{ "Perr_mac_stat5_tx", 0, 1 },
+	{ "MAC_PERR_INT_CAUSE_MTIP", 0x380d4, 0 },
+		{ "rx_mac40g", 28, 1 },
+		{ "tx_mac40g", 27, 1 },
+		{ "rx_st_mac40g", 26, 1 },
+		{ "tx_st_mac40g", 25, 1 },
+		{ "tx_mac1g10g", 24, 1 },
+		{ "rx_mac1g10g", 23, 1 },
+		{ "rx_status_mac1g10g", 22, 1 },
+		{ "rx_st_mac1g10g", 21, 1 },
+		{ "tx_st_mac1g10g", 20, 1 },
+		{ "Perr_mac0_tx", 19, 1 },
+		{ "Perr_mac1_tx", 18, 1 },
+		{ "Perr_mac2_tx", 17, 1 },
+		{ "Perr_mac3_tx", 16, 1 },
+		{ "Perr_mac4_tx", 15, 1 },
+		{ "Perr_mac5_tx", 14, 1 },
+		{ "Perr_mac0_rx", 13, 1 },
+		{ "Perr_mac1_rx", 12, 1 },
+		{ "Perr_mac2_rx", 11, 1 },
+		{ "Perr_mac3_rx", 10, 1 },
+		{ "Perr_mac4_rx", 9, 1 },
+		{ "Perr_mac5_rx", 8, 1 },
+		{ "Perr_mac_stat_rx", 7, 1 },
+		{ "Perr_mac_stat3_rx", 6, 1 },
+		{ "Perr_mac_stat4_rx", 5, 1 },
+		{ "Perr_mac_stat5_rx", 4, 1 },
+		{ "Perr_mac_stat_tx", 3, 1 },
+		{ "Perr_mac_stat_cap", 2, 1 },
+		{ "Perr_mac_stat4_tx", 1, 1 },
+		{ "Perr_mac_stat5_tx", 0, 1 },
+	{ "MAC_PERR_ENABLE_MTIP", 0x380d8, 0 },
+		{ "rx_mac40g", 28, 1 },
+		{ "tx_mac40g", 27, 1 },
+		{ "rx_st_mac40g", 26, 1 },
+		{ "tx_st_mac40g", 25, 1 },
+		{ "tx_mac1g10g", 24, 1 },
+		{ "rx_mac1g10g", 23, 1 },
+		{ "rx_status_mac1g10g", 22, 1 },
+		{ "rx_st_mac1g10g", 21, 1 },
+		{ "tx_st_mac1g10g", 20, 1 },
+		{ "Perr_mac0_tx", 19, 1 },
+		{ "Perr_mac1_tx", 18, 1 },
+		{ "Perr_mac2_tx", 17, 1 },
+		{ "Perr_mac3_tx", 16, 1 },
+		{ "Perr_mac4_tx", 15, 1 },
+		{ "Perr_mac5_tx", 14, 1 },
+		{ "Perr_mac0_rx", 13, 1 },
+		{ "Perr_mac1_rx", 12, 1 },
+		{ "Perr_mac2_rx", 11, 1 },
+		{ "Perr_mac3_rx", 10, 1 },
+		{ "Perr_mac4_rx", 9, 1 },
+		{ "Perr_mac5_rx", 8, 1 },
+		{ "Perr_mac_stat2_rx", 7, 1 },
+		{ "Perr_mac_stat3_rx", 6, 1 },
+		{ "Perr_mac_stat4_rx", 5, 1 },
+		{ "Perr_mac_stat5_rx", 4, 1 },
+		{ "Perr_mac_stat2_tx", 3, 1 },
+		{ "Perr_mac_stat3_tx", 2, 1 },
+		{ "Perr_mac_stat4_tx", 1, 1 },
+		{ "Perr_mac_stat5_tx", 0, 1 },
+	{ "MAC_PCS_1G_CONFIG_0", 0x380dc, 0 },
+		{ "seq_ena_3", 19, 1 },
+		{ "seq_ena_2", 18, 1 },
+		{ "seq_ena_1", 17, 1 },
+		{ "seq_ena_0", 16, 1 },
+		{ "tx_lane_thresh_3", 12, 4 },
+		{ "tx_lane_thresh_2", 8, 4 },
+		{ "tx_lane_thresh_1", 4, 4 },
+		{ "tx_lane_thresh_0", 0, 4 },
+	{ "MAC_PCS_1G_CONFIG_1", 0x380e0, 0 },
+		{ "tx_lane_ckmult_3", 9, 3 },
+		{ "tx_lane_ckmult_2", 6, 3 },
+		{ "tx_lane_ckmult_1", 3, 3 },
+		{ "tx_lane_ckmult_0", 0, 3 },
+	{ "MAC_PTP_TIMER_RD0_LO", 0x380e4, 0 },
+	{ "MAC_PTP_TIMER_RD0_HI", 0x380e8, 0 },
+	{ "MAC_PTP_TIMER_RD1_LO", 0x380ec, 0 },
+	{ "MAC_PTP_TIMER_RD1_HI", 0x380f0, 0 },
+	{ "MAC_PTP_TIMER_WR_LO", 0x380f4, 0 },
+	{ "MAC_PTP_TIMER_WR_HI", 0x380f8, 0 },
+	{ "MAC_PTP_TIMER_OFFSET_0", 0x380fc, 0 },
+	{ "MAC_PTP_TIMER_OFFSET_1", 0x38100, 0 },
+	{ "MAC_PTP_TIMER_OFFSET_2", 0x38104, 0 },
+	{ "MAC_PTP_SUM_LO", 0x38108, 0 },
+	{ "MAC_PTP_SUM_HI", 0x3810c, 0 },
+	{ "MAC_PTP_TIMER_INCR0", 0x38110, 0 },
+		{ "Y", 16, 16 },
+		{ "X", 0, 16 },
+	{ "MAC_PTP_TIMER_INCR1", 0x38114, 0 },
+		{ "Y_TICK", 16, 16 },
+		{ "X_TICK", 0, 16 },
+	{ "MAC_PTP_DRIFT_ADJUST_COUNT", 0x38118, 0 },
+	{ "MAC_PTP_OFFSET_ADJUST_FINE", 0x3811c, 0 },
+		{ "B", 16, 16 },
+		{ "A", 0, 16 },
+	{ "MAC_PTP_OFFSET_ADJUST_TOTAL", 0x38120, 0 },
+	{ "MAC_PTP_CFG", 0x38124, 0 },
+		{ "ALARM_EN", 21, 1 },
+		{ "ALARM_START", 20, 1 },
+		{ "PPS_EN", 19, 1 },
+		{ "FRZ", 18, 1 },
+		{ "OFFSER_ADJUST_SIGN", 17, 1 },
+		{ "ADD_OFFSET", 16, 1 },
+		{ "CYCLE1", 8, 8 },
+		{ "Q", 0, 8 },
+	{ "MAC_PTP_PPS", 0x38128, 0 },
+	{ "MAC_PTP_SINGLE_ALARM", 0x3812c, 0 },
+	{ "MAC_PTP_PERIODIC_ALARM", 0x38130, 0 },
+	{ "MAC_PTP_STATUS", 0x38134, 0 },
+	{ "MAC_STS_GPIO_SEL", 0x38140, 0 },
+		{ "STSOUTSEL", 1, 1 },
+		{ "STSINSEL", 0, 1 },
+	{ "MAC_CERR_INT_EN_MTIP", 0x38150, 0 },
+		{ "Cerr_mac0_tx", 11, 1 },
+		{ "Cerr_mac1_tx", 10, 1 },
+		{ "Cerr_mac2_tx", 9, 1 },
+		{ "Cerr_mac3_tx", 8, 1 },
+		{ "Cerr_mac4_tx", 7, 1 },
+		{ "Cerr_mac5_tx", 6, 1 },
+		{ "Cerr_mac0_rx", 5, 1 },
+		{ "Cerr_mac1_rx", 4, 1 },
+		{ "Cerr_mac2_rx", 3, 1 },
+		{ "Cerr_mac3_rx", 2, 1 },
+		{ "Cerr_mac4_rx", 1, 1 },
+		{ "Cerr_mac5_rx", 0, 1 },
+	{ "MAC_CERR_INT_CAUSE_MTIP", 0x38154, 0 },
+		{ "Cerr_mac0_tx", 11, 1 },
+		{ "Cerr_mac1_tx", 10, 1 },
+		{ "Cerr_mac2_tx", 9, 1 },
+		{ "Cerr_mac3_tx", 8, 1 },
+		{ "Cerr_mac4_tx", 7, 1 },
+		{ "Cerr_mac5_tx", 6, 1 },
+		{ "Cerr_mac0_rx", 5, 1 },
+		{ "Cerr_mac1_rx", 4, 1 },
+		{ "Cerr_mac2_rx", 3, 1 },
+		{ "Cerr_mac3_rx", 2, 1 },
+		{ "Cerr_mac4_rx", 1, 1 },
+		{ "Cerr_mac5_rx", 0, 1 },
+	{ "MAC_1G_PCS0_STATUS", 0x38160, 0 },
+		{ "sg_loopback", 12, 1 },
+		{ "sg_link_status", 11, 1 },
+		{ "sg_rx_sync", 10, 1 },
+		{ "sg_an_done", 9, 1 },
+		{ "sg_page_recieved", 8, 1 },
+		{ "sg_speed_sel", 6, 2 },
+		{ "sg_half_duplex", 5, 1 },
+		{ "pma_tx_mode_quiet", 4, 1 },
+		{ "tx_lpi_active", 3, 1 },
+		{ "pma_rx_mode_quiet", 2, 1 },
+		{ "rx_lpi_active", 1, 1 },
+		{ "rx_wake_err", 0, 1 },
+	{ "MAC_1G_PCS1_STATUS", 0x38164, 0 },
+		{ "sg_loopback", 12, 1 },
+		{ "sg_link_status", 11, 1 },
+		{ "sg_rx_sync", 10, 1 },
+		{ "sg_an_done", 9, 1 },
+		{ "sg_page_recieved", 8, 1 },
+		{ "sg_speed_sel", 6, 2 },
+		{ "sg_half_duplex", 5, 1 },
+		{ "pma_tx_mode_quiet", 4, 1 },
+		{ "tx_lpi_active", 3, 1 },
+		{ "pma_rx_mode_quiet", 2, 1 },
+		{ "rx_lpi_active", 1, 1 },
+		{ "rx_wake_err", 0, 1 },
+	{ "MAC_1G_PCS2_STATUS", 0x38168, 0 },
+		{ "sg_loopback", 12, 1 },
+		{ "sg_link_status", 11, 1 },
+		{ "sg_rx_sync", 10, 1 },
+		{ "sg_an_done", 9, 1 },
+		{ "sg_page_recieved", 8, 1 },
+		{ "sg_speed_sel", 6, 2 },
+		{ "sg_half_duplex", 5, 1 },
+		{ "pma_tx_mode_quiet", 4, 1 },
+		{ "tx_lpi_active", 3, 1 },
+		{ "pma_rx_mode_quiet", 2, 1 },
+		{ "rx_lpi_active", 1, 1 },
+		{ "rx_wake_err", 0, 1 },
+	{ "MAC_1G_PCS3_STATUS", 0x3816c, 0 },
+		{ "sg_loopback", 12, 1 },
+		{ "sg_link_status", 11, 1 },
+		{ "sg_rx_sync", 10, 1 },
+		{ "sg_an_done", 9, 1 },
+		{ "sg_page_recieved", 8, 1 },
+		{ "sg_speed_sel", 6, 2 },
+		{ "sg_half_duplex", 5, 1 },
+		{ "pma_tx_mode_quiet", 4, 1 },
+		{ "tx_lpi_active", 3, 1 },
+		{ "pma_rx_mode_quiet", 2, 1 },
+		{ "rx_lpi_active", 1, 1 },
+		{ "rx_wake_err", 0, 1 },
+	{ "MAC_PCS_LPI_STATUS_0", 0x38170, 0 },
+	{ "MAC_PCS_LPI_STATUS_1", 0x38174, 0 },
+	{ "MAC_PCS_LPI_STATUS_2", 0x38178, 0 },
+		{ "RX_LPI_MODE", 24, 8 },
+		{ "RX_LPI_STATE", 0, 24 },
+	{ "MAC_PCS_LPI_STATUS_3", 0x3817c, 0 },
+	{ "MAC_TX0_CLK_DIV", 0x38180, 0 },
+	{ "MAC_TX1_CLK_DIV", 0x38184, 0 },
+	{ "MAC_TX2_CLK_DIV", 0x38188, 0 },
+	{ "MAC_TX3_CLK_DIV", 0x3818c, 0 },
+	{ "MAC_TX4_CLK_DIV", 0x38190, 0 },
+	{ "MAC_TX5_CLK_DIV", 0x38194, 0 },
+	{ "MAC_TX6_CLK_DIV", 0x38198, 0 },
+	{ "MAC_TX7_CLK_DIV", 0x3819c, 0 },
+	{ "MAC_RX0_CLK_DIV", 0x381a0, 0 },
+	{ "MAC_RX1_CLK_DIV", 0x381a4, 0 },
+	{ "MAC_RX2_CLK_DIV", 0x381a8, 0 },
+	{ "MAC_RX3_CLK_DIV", 0x381ac, 0 },
+	{ "MAC_RX4_CLK_DIV", 0x381b0, 0 },
+	{ "MAC_RX5_CLK_DIV", 0x381b4, 0 },
+	{ "MAC_RX6_CLK_DIV", 0x381b8, 0 },
+	{ "MAC_RX7_CLK_DIV", 0x381bc, 0 },
+	{ "MAC_SYNC_E_CDR_LANE_SEL", 0x381c0, 0 },
+		{ "CML_MUX_SEL", 11, 1 },
+		{ "CMOS_OUT_EN", 10, 1 },
+		{ "CML_OUT_EN", 9, 1 },
+		{ "LOC_FAULT_PORT_SEL", 6, 2 },
+		{ "TX_CDR_LANE_SEL", 3, 3 },
+		{ "RX_CDR_LANE_SEL", 0, 3 },
+	{ "MAC_DEBUG_PL_IF_1", 0x381c4, 0 },
+	{ "MAC_SIGNAL_DETECT_CTRL", 0x381f0, 0 },
+		{ "Signal_Det_ln7", 15, 1 },
+		{ "Signal_Det_ln6", 14, 1 },
+		{ "Signal_Det_ln5", 13, 1 },
+		{ "Signal_Det_ln4", 12, 1 },
+		{ "Signal_Det_ln3", 11, 1 },
+		{ "Signal_Det_ln2", 10, 1 },
+		{ "Signal_Det_ln1", 9, 1 },
+		{ "Signal_Det_ln0", 8, 1 },
+		{ "SigDetCtrl_ln7", 7, 1 },
+		{ "SigDetCtrl_ln6", 6, 1 },
+		{ "SigDetCtrl_ln5", 5, 1 },
+		{ "SigDetCtrl_ln4", 4, 1 },
+		{ "SigDetCtrl_ln3", 3, 1 },
+		{ "SigDetCtrl_ln2", 2, 1 },
+		{ "SigDetCtrl_ln1", 1, 1 },
+		{ "SigDetCtrl_ln0", 0, 1 },
+	{ "MAC_FPGA_STATUS_FRM_BOARD", 0x381f4, 0 },
+		{ "SFP3_RX_LOS", 15, 1 },
+		{ "SFP3_TX_FAULT", 14, 1 },
+		{ "SFP3_MOD_PRES", 13, 1 },
+		{ "SFP2_RX_LOS", 12, 1 },
+		{ "SFP2_TX_FAULT", 11, 1 },
+		{ "SFP2_MOD_PRES", 10, 1 },
+		{ "SFP1_RX_LOS", 9, 1 },
+		{ "SFP1_TX_FAULT", 8, 1 },
+		{ "SFP1_MOD_PRES", 7, 1 },
+		{ "SFP0_RX_LOS", 6, 1 },
+		{ "SFP0_TX_FAULT", 5, 1 },
+		{ "SFP0_MOD_PRES", 4, 1 },
+		{ "QSFP1_INT_L", 3, 1 },
+		{ "QSFP1_MOD_PRES", 2, 1 },
+		{ "QSFP0_INT_L", 1, 1 },
+		{ "QSFP0_MOD_PRES", 0, 1 },
+	{ "MAC_FPGA_CONTROL_TO_BOARD", 0x381f8, 0 },
+		{ "SBA_EN", 12, 2 },
+		{ "LB_MODE", 10, 2 },
+		{ "SFP3_TX_DISABLE", 9, 1 },
+		{ "SFP2_TX_DISABLE", 8, 1 },
+		{ "SFP1_TX_DISABLE", 7, 1 },
+		{ "SFP0_TX_DISABLE", 6, 1 },
+		{ "QSFP1_LPMODE", 5, 1 },
+		{ "QSFP1_MODSEL_L", 4, 1 },
+		{ "QSFP1_RESET_L", 3, 1 },
+		{ "QSFP0_LPMODE", 2, 1 },
+		{ "QSFP0_MODSEL_L", 1, 1 },
+		{ "QSFP0_RESET_L", 0, 1 },
+	{ "MAC_FPGA_LINK_STATUS", 0x381fc, 0 },
+		{ "port3_fpga_link_up", 3, 1 },
+		{ "port2_fpga_link_up", 2, 1 },
+		{ "port1_fpga_link_up", 1, 1 },
+		{ "port0_fpga_link_up", 0, 1 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_REVISION", 0x38200, 0 },
+		{ "CUSTREV", 16, 16 },
+		{ "VER", 8, 8 },
+		{ "REV", 0, 8 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_SCRATCH", 0x38204, 0 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_COMMAND_CONFIG", 0x38208, 0 },
+		{ "INV_LOOP", 31, 1 },
+		{ "FLT_HDL_DIS", 27, 1 },
+		{ "TX_FIFO_RESET", 26, 1 },
+		{ "TX_FLUSH", 22, 1 },
+		{ "RX_SFD_ANY", 21, 1 },
+		{ "PAUSE_PFC_COMP", 20, 1 },
+		{ "PFC_MODE", 19, 1 },
+		{ "NO_LGTH_CHECK", 17, 1 },
+		{ "SEND_IDLE", 16, 1 },
+		{ "PHY_TXENA", 15, 1 },
+		{ "RX_ERR_DISC", 14, 1 },
+		{ "CMD_FRAME_ENA", 13, 1 },
+		{ "SW_RESET", 12, 1 },
+		{ "TX_PAD_EN", 11, 1 },
+		{ "LOOPBACK_EN", 10, 1 },
+		{ "TX_ADDR_INS", 9, 1 },
+		{ "PAUSE_IGNORE", 8, 1 },
+		{ "PAUSE_FWD", 7, 1 },
+		{ "CRC_FWD", 6, 1 },
+		{ "PAD_EN", 5, 1 },
+		{ "PROMIS_EN", 4, 1 },
+		{ "RX_ENA", 1, 1 },
+		{ "TX_ENA", 0, 1 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_0", 0x3820c, 0 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1", 0x38210, 0 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH", 0x38214, 0 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS", 0x3821c, 0 },
+		{ "AVAIL", 16, 16 },
+		{ "EMPTY", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS", 0x38220, 0 },
+		{ "AVAIL", 16, 16 },
+		{ "EMPTY", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E", 0x38224, 0 },
+		{ "AlmstFull", 16, 16 },
+		{ "AlmstEmpty", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_ALMOST_F_E", 0x38228, 0 },
+		{ "AlmstFull", 16, 16 },
+		{ "AlmstEmpty", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_HASHTABLE_LOAD", 0x3822c, 0 },
+		{ "ENABLE", 8, 1 },
+		{ "ADDR", 0, 6 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_STATUS", 0x38240, 0 },
+		{ "TX_ISIDLE", 8, 1 },
+		{ "RX_EMPTY", 6, 1 },
+		{ "TX_EMPTY", 5, 1 },
+		{ "TS_AVAIL", 3, 1 },
+		{ "PHY_LOS", 2, 1 },
+		{ "RX_REM_FAULT", 1, 1 },
+		{ "RX_LOC_FAULT", 0, 1 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_TX_IPG_LENGTH", 0x38244, 0 },
+		{ "LEN", 19, 13 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA", 0x38254, 0 },
+		{ "CL1_PAUSE_QUANTA", 16, 16 },
+		{ "CL0_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA", 0x38258, 0 },
+		{ "CL3_PAUSE_QUANTA", 16, 16 },
+		{ "CL2_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA", 0x3825c, 0 },
+		{ "CL5_PAUSE_QUANTA", 16, 16 },
+		{ "CL4_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA", 0x38260, 0 },
+		{ "CL7_PAUSE_QUANTA", 16, 16 },
+		{ "CL6_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH", 0x38264, 0 },
+		{ "CL1_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL0_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH", 0x38268, 0 },
+		{ "CL3_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL2_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH", 0x3826c, 0 },
+		{ "CL5_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL4_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH", 0x38270, 0 },
+		{ "CL7_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL6_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_RX_PAUSE_STATUS", 0x38274, 0 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_TS_TIMESTAMP", 0x3827c, 0 },
+	{ "MAC_MTIP_MAC400G_0_MTIP_XIF_MODE", 0x38280, 0 },
+		{ "ONE_STEP_ENA", 5, 1 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_REVISION", 0x38300, 0 },
+		{ "CUSTREV", 16, 16 },
+		{ "VER", 8, 8 },
+		{ "REV", 0, 8 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_SCRATCH", 0x38304, 0 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_COMMAND_CONFIG", 0x38308, 0 },
+		{ "INV_LOOP", 31, 1 },
+		{ "FLT_HDL_DIS", 27, 1 },
+		{ "TX_FIFO_RESET", 26, 1 },
+		{ "TX_FLUSH", 22, 1 },
+		{ "RX_SFD_ANY", 21, 1 },
+		{ "PAUSE_PFC_COMP", 20, 1 },
+		{ "PFC_MODE", 19, 1 },
+		{ "NO_LGTH_CHECK", 17, 1 },
+		{ "SEND_IDLE", 16, 1 },
+		{ "PHY_TXENA", 15, 1 },
+		{ "RX_ERR_DISC", 14, 1 },
+		{ "CMD_FRAME_ENA", 13, 1 },
+		{ "SW_RESET", 12, 1 },
+		{ "TX_PAD_EN", 11, 1 },
+		{ "LOOPBACK_EN", 10, 1 },
+		{ "TX_ADDR_INS", 9, 1 },
+		{ "PAUSE_IGNORE", 8, 1 },
+		{ "PAUSE_FWD", 7, 1 },
+		{ "CRC_FWD", 6, 1 },
+		{ "PAD_EN", 5, 1 },
+		{ "PROMIS_EN", 4, 1 },
+		{ "RX_ENA", 1, 1 },
+		{ "TX_ENA", 0, 1 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_0", 0x3830c, 0 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_1", 0x38310, 0 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_FRM_LENGTH", 0x38314, 0 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_SECTIONS", 0x3831c, 0 },
+		{ "AVAIL", 16, 16 },
+		{ "EMPTY", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_SECTIONS", 0x38320, 0 },
+		{ "AVAIL", 16, 16 },
+		{ "EMPTY", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_ALMOST_F_E", 0x38324, 0 },
+		{ "AlmstFull", 16, 16 },
+		{ "AlmstEmpty", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_ALMOST_F_E", 0x38328, 0 },
+		{ "AlmstFull", 16, 16 },
+		{ "AlmstEmpty", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_HASHTABLE_LOAD", 0x3832c, 0 },
+		{ "ENABLE", 8, 1 },
+		{ "ADDR", 0, 6 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_STATUS", 0x38340, 0 },
+		{ "TX_ISIDLE", 8, 1 },
+		{ "RX_EMPTY", 6, 1 },
+		{ "TX_EMPTY", 5, 1 },
+		{ "TS_AVAIL", 3, 1 },
+		{ "PHY_LOS", 2, 1 },
+		{ "RX_REM_FAULT", 1, 1 },
+		{ "RX_LOC_FAULT", 0, 1 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_TX_IPG_LENGTH", 0x38344, 0 },
+		{ "LEN", 19, 13 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA", 0x38354, 0 },
+		{ "CL1_PAUSE_QUANTA", 16, 16 },
+		{ "CL0_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA", 0x38358, 0 },
+		{ "CL3_PAUSE_QUANTA", 16, 16 },
+		{ "CL2_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA", 0x3835c, 0 },
+		{ "CL5_PAUSE_QUANTA", 16, 16 },
+		{ "CL4_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA", 0x38360, 0 },
+		{ "CL7_PAUSE_QUANTA", 16, 16 },
+		{ "CL6_PAUSE_QUANTA", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH", 0x38364, 0 },
+		{ "CL1_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL0_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH", 0x38368, 0 },
+		{ "CL3_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL2_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH", 0x3836c, 0 },
+		{ "CL5_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL4_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH", 0x38370, 0 },
+		{ "CL7_PAUSE_QUANTA_THRESH", 16, 16 },
+		{ "CL6_PAUSE_QUANTA_THRESH", 0, 16 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_RX_PAUSE_STATUS", 0x38374, 0 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_TS_TIMESTAMP", 0x3837c, 0 },
+	{ "MAC_MTIP_MAC400G_1_MTIP_XIF_MODE", 0x38380, 0 },
+		{ "ONE_STEP_ENA", 5, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_1", 0x38400, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection", 2, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_1", 0x38404, 0 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID0", 0x38408, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID1", 0x3840c, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_SPEED_ABILITY", 0x38410, 0 },
+		{ "400G_capable", 9, 1 },
+		{ "40G_capable", 8, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG1", 0x38414, 0 },
+		{ "Device_Package", 3, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG2", 0x38418, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_2", 0x3841c, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_2", 0x38420, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_3", 0x38424, 0 },
+		{ "Device_present", 2, 14 },
+		{ "400GBase_R", 1, 1 },
+		{ "200GBase_R", 0, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID0", 0x38438, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID1", 0x3843c, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_1", 0x38480, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_2", 0x38484, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_CONTROL", 0x384a8, 0 },
+		{ "Scrambled_ID_TP_EN", 7, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_ERR_CNT", 0x384ac, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_BER_HIGH_ORDER_CNT", 0x384b0, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT", 0x384b4, 0 },
+		{ "High_ORDER", 15, 1 },
+		{ "Error_block_counter", 0, 14 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1", 0x384c8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2", 0x384cc, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3", 0x384d0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4", 0x384d4, 0 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_0_MAPPING", 0x384d8, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_1_MAPPING", 0x384dc, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_2_MAPPING", 0x384e0, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_3_MAPPING", 0x384e4, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_4_MAPPING", 0x384e8, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_5_MAPPING", 0x384ec, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_6_MAPPING", 0x384f0, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_7_MAPPING", 0x384f4, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_8_MAPPING", 0x384f8, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_9_MAPPING", 0x384fc, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_10_MAPPING", 0x38500, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_11_MAPPING", 0x38504, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_12_MAPPING", 0x38508, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_13_MAPPING", 0x3850c, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_14_MAPPING", 0x38510, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_LANE_15_MAPPING", 0x38514, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_SCRATCH", 0x38600, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_CORE_REVISION", 0x38604, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_CL_INTVL", 0x38608, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_TX_LANE_THRESH", 0x3860c, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_TX_CDMII_PACE", 0x3861c, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_AM_0", 0x38620, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_AM_1", 0x38624, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO0", 0x38800, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO1", 0x38804, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO2", 0x38808, 0 },
+	{ "MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO3", 0x3880c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_1", 0x38900, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Low_power", 11, 1 },
+		{ "Speed_selection", 2, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_1", 0x38904, 0 },
+		{ "Fault", 7, 1 },
+		{ "RX_Link_Status", 2, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID0", 0x38908, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID1", 0x3890c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_SPEED_ABILITY", 0x38910, 0 },
+		{ "400G_capable", 9, 1 },
+		{ "40G_capable", 8, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG1", 0x38914, 0 },
+		{ "Device_Package", 3, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG2", 0x38918, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_2", 0x3891c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_2", 0x38920, 0 },
+		{ "Device_present", 14, 2 },
+		{ "Transmit_fault", 11, 1 },
+		{ "Receive_fault", 10, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_3", 0x38924, 0 },
+		{ "Device_present", 2, 14 },
+		{ "400GBase_R", 1, 1 },
+		{ "200GBase_R", 0, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID0", 0x38938, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID1", 0x3893c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_1", 0x38980, 0 },
+		{ "RX_Link_STAT", 12, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_2", 0x38984, 0 },
+		{ "Latched_block_lock", 15, 1 },
+		{ "Latched_high_BER", 14, 1 },
+		{ "Errored_blocks_cntr", 0, 8 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_CONTROL", 0x389a8, 0 },
+		{ "Scrambled_ID_TP_EN", 7, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_ERR_CNT", 0x389ac, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_BER_HIGH_ORDER_CNT", 0x389b0, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT", 0x389b4, 0 },
+		{ "High_ORDER", 15, 1 },
+		{ "Error_block_counter", 0, 14 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1", 0x389c8, 0 },
+		{ "LANE_ALIGN_STAT", 12, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2", 0x389cc, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3", 0x389d0, 0 },
+		{ "Lane7_algn_mrkr_lck", 7, 1 },
+		{ "Lane6_algn_mrkr_lck", 6, 1 },
+		{ "Lane5_algn_mrkr_lck", 5, 1 },
+		{ "Lane4_algn_mrkr_lck", 4, 1 },
+		{ "Lane3_algn_mrkr_lck", 3, 1 },
+		{ "Lane2_algn_mrkr_lck", 2, 1 },
+		{ "Lane1_algn_mrkr_lck", 1, 1 },
+		{ "Lane0_algn_mrkr_lck", 0, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4", 0x389d4, 0 },
+		{ "Lane15_algn_mrkr_lck", 7, 1 },
+		{ "Lane14_algn_mrkr_lck", 6, 1 },
+		{ "Lane13_algn_mrkr_lck", 5, 1 },
+		{ "Lane12_algn_mrkr_lck", 4, 1 },
+		{ "Lane11_algn_mrkr_lck", 3, 1 },
+		{ "Lane10_algn_mrkr_lck", 2, 1 },
+		{ "Lane9_algn_mrkr_lck", 1, 1 },
+		{ "Lane8_algn_mrkr_lck", 0, 1 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_0_MAPPING", 0x389d8, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_1_MAPPING", 0x389dc, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_2_MAPPING", 0x389e0, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_3_MAPPING", 0x389e4, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_4_MAPPING", 0x389e8, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_5_MAPPING", 0x389ec, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_6_MAPPING", 0x389f0, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_7_MAPPING", 0x389f4, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_8_MAPPING", 0x389f8, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_9_MAPPING", 0x389fc, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_10_MAPPING", 0x38a00, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_11_MAPPING", 0x38a04, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_12_MAPPING", 0x38a08, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_13_MAPPING", 0x38a0c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_14_MAPPING", 0x38a10, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_LANE_15_MAPPING", 0x38a14, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_SCRATCH", 0x38b00, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_CORE_REVISION", 0x38b04, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_CL_INTVL", 0x38b08, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_TX_LANE_THRESH", 0x38b0c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_TX_CDMII_PACE", 0x38b1c, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_AM_0", 0x38b20, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_AM_1", 0x38b24, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO0", 0x38d00, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO1", 0x38d04, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO2", 0x38d08, 0 },
+	{ "MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO3", 0x38d0c, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_0", 0x38e00, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_0", 0x38e04, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_0", 0x38e08, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_0", 0x38e0c, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_0", 0x38e10, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_0", 0x38e14, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_0", 0x38e18, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_0", 0x38e1c, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_1", 0x38e20, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_1", 0x38e24, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_1", 0x38e28, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_1", 0x38e2c, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_1", 0x38e30, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_1", 0x38e34, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_1", 0x38e38, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_1", 0x38e3c, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_2", 0x38e40, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_2", 0x38e44, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_2", 0x38e48, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_2", 0x38e4c, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_2", 0x38e50, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_2", 0x38e54, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_2", 0x38e58, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_2", 0x38e5c, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_3", 0x38e60, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_3", 0x38e64, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_3", 0x38e68, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_3", 0x38e6c, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_3", 0x38e70, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_3", 0x38e74, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_3", 0x38e78, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_3", 0x38e7c, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_4", 0x38e80, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_4", 0x38e84, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_4", 0x38e88, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_4", 0x38e8c, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_4", 0x38e90, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_4", 0x38e94, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_4", 0x38e98, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_4", 0x38e9c, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_5", 0x38ea0, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_5", 0x38ea4, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_5", 0x38ea8, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_5", 0x38eac, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_5", 0x38eb0, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_5", 0x38eb4, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_5", 0x38eb8, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_5", 0x38ebc, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_6", 0x38ec0, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_6", 0x38ec4, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_6", 0x38ec8, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_6", 0x38ecc, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_6", 0x38ed0, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_6", 0x38ed4, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_6", 0x38ed8, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_6", 0x38edc, 0 },
+	{ "MAC_MTIP_RS_FEC_CONTROL_0_7", 0x38ee0, 0 },
+		{ "TC_PAD_ALTER", 10, 1 },
+		{ "TC_PAD_VALUE", 9, 1 },
+		{ "KP_ENABLE", 8, 1 },
+		{ "am16_copy_dis", 3, 1 },
+		{ "RS_FEC_Degrade_option_ena", 2, 1 },
+		{ "RS_FEC_Bypass_Error_Indication", 1, 1 },
+		{ "RS_FEC_Bypass_Correction", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_STATUS_0_7", 0x38ee4, 0 },
+		{ "fec_aligned_status", 14, 1 },
+		{ "amp_lock", 8, 4 },
+		{ "rx_am_sf_0", 7, 1 },
+		{ "rx_am_sf_1", 6, 1 },
+		{ "rx_am_sf_2", 5, 1 },
+		{ "RS_FEC_degrade_SER", 4, 1 },
+		{ "RS_FEC_degrade_SER_ability", 3, 1 },
+		{ "RS_FEC_high_SER", 2, 1 },
+		{ "RS_FEC_bypass_error_indication_ability", 1, 1 },
+		{ "RS_FEC_bypass_correction_ability", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_CCW_LO_0_7", 0x38ee8, 0 },
+	{ "MAC_MTIP_RS_FEC_CCW_HI_0_7", 0x38eec, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_LO_0_7", 0x38ef0, 0 },
+	{ "MAC_MTIP_RS_FEC_NCCW_HI_0_7", 0x38ef4, 0 },
+	{ "MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_7", 0x38ef8, 0 },
+	{ "MAC_MTIP_RS_FEC_DEC_THRESH_0_7", 0x38efc, 0 },
+	{ "MAC_MTIP_RS_FEC_HISER_CW", 0x38f00, 0 },
+	{ "MAC_MTIP_RS_FEC_HISER_THRESH", 0x38f04, 0 },
+	{ "MAC_MTIP_RS_FEC_HISER_TIME", 0x38f08, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_SET_CW", 0x38f10, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_SET_CW_HI", 0x38f14, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_SET_THRESH", 0x38f18, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_SET_THRESH_HI", 0x38f1c, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_CLEAR", 0x38f20, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_SET_CLEAR_HI", 0x38f24, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_CLEAR_THRESH", 0x38f28, 0 },
+	{ "MAC_MTIP_RS_DEGRADE_SET_CLEAR_THRESH_HI", 0x38f2c, 0 },
+	{ "MAC_MTIP_RS_VL0_0", 0x38f80, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL0_1", 0x38f84, 0 },
+	{ "MAC_MTIP_RS_VL1_0", 0x38f88, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL1_1", 0x38f8c, 0 },
+	{ "MAC_MTIP_RS_VL2_0", 0x38f90, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL2_1", 0x38f94, 0 },
+	{ "MAC_MTIP_RS_VL3_0", 0x38f98, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL3_1", 0x38f9c, 0 },
+	{ "MAC_MTIP_RS_VL4_0", 0x38fa0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL4_1", 0x38fa4, 0 },
+	{ "MAC_MTIP_RS_VL5_0", 0x38fa8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL5_1", 0x38fac, 0 },
+	{ "MAC_MTIP_RS_VL6_0", 0x38fb0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL6_1", 0x38fb4, 0 },
+	{ "MAC_MTIP_RS_VL7_0", 0x38fb8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL7_1", 0x38fbc, 0 },
+	{ "MAC_MTIP_RS_VL8_0", 0x38fc0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL8_1", 0x38fc4, 0 },
+	{ "MAC_MTIP_RS_VL9_0", 0x38fc8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL9_1", 0x38fcc, 0 },
+	{ "MAC_MTIP_RS_VL10_0", 0x38fd0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL10_1", 0x38fd4, 0 },
+	{ "MAC_MTIP_RS_VL11_0", 0x38fd8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL11_1", 0x38fdc, 0 },
+	{ "MAC_MTIP_RS_VL12_0", 0x38fe0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL12_1", 0x38fe4, 0 },
+	{ "MAC_MTIP_RS_VL13_0", 0x38fe8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL13_1", 0x38fec, 0 },
+	{ "MAC_MTIP_RS_VL14_0", 0x38ff0, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL14_1", 0x38ff4, 0 },
+	{ "MAC_MTIP_RS_VL15_0", 0x38ff8, 0 },
+		{ "M1", 8, 8 },
+		{ "M0", 0, 8 },
+	{ "MAC_MTIP_RS_VL15_1", 0x38ffc, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR0_LO", 0x39000, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR0_HI", 0x39004, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR1_LO", 0x39008, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR1_HI", 0x3900c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR2_LO", 0x39010, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR2_HI", 0x39014, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR3_LO", 0x39018, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR3_HI", 0x3901c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR4_LO", 0x39020, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR4_HI", 0x39024, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR5_LO", 0x39028, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR5_HI", 0x3902c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR6_LO", 0x39030, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR6_HI", 0x39034, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR7_LO", 0x39038, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR7_HI", 0x3903c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR8_LO", 0x39040, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR8_HI", 0x39044, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR9_LO", 0x39048, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR9_HI", 0x3904c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR10_LO", 0x39050, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR10_HI", 0x39054, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR11_LO", 0x39058, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR11_HI", 0x3905c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR12_LO", 0x39060, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR12_HI", 0x39064, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR13_LO", 0x39068, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR13_HI", 0x3906c, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR14_LO", 0x39070, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR14_HI", 0x39074, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR15_LO", 0x39078, 0 },
+	{ "MAC_MTIP_RS_FEC_SYMBLERR15_HI", 0x3907c, 0 },
+	{ "MAC_MTIP_RS_FEC_VENDOR_CONTROL", 0x39080, 0 },
+	{ "MAC_MTIP_RS_FEC_VENDOR_INFO_1", 0x39084, 0 },
+		{ "fec_align_status_lh", 10, 1 },
+		{ "tx_dp_overflow", 9, 1 },
+		{ "rx_dp_overflow", 8, 1 },
+		{ "tx_datapath_restart", 7, 1 },
+		{ "rx_datapath_restart", 6, 1 },
+		{ "marker_check_restart", 5, 1 },
+		{ "fec_align_status_ll", 4, 1 },
+		{ "amps_lock", 0, 1 },
+	{ "MAC_MTIP_RS_FEC_VENDOR_INFO_2", 0x39088, 0 },
+	{ "MAC_MTIP_RS_FEC_VENDOR_REVISION", 0x3908c, 0 },
+	{ "MAC_MTIP_RS_FEC_VENDOR_ALIGN_STATUS", 0x39090, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_0", 0x39100, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_0", 0x39104, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_0", 0x39108, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_0", 0x3910c, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_0", 0x39110, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_0", 0x39114, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_0", 0x39118, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_0", 0x3911c, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_1", 0x39120, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_1", 0x39124, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_1", 0x39128, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_1", 0x3912c, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_1", 0x39130, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_1", 0x39134, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_1", 0x39138, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_1", 0x3913c, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_2", 0x39140, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_2", 0x39144, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_2", 0x39148, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_2", 0x3914c, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_2", 0x39150, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_2", 0x39154, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_2", 0x39158, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_2", 0x3915c, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_3", 0x39160, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_3", 0x39164, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_3", 0x39168, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_3", 0x3916c, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_3", 0x39170, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_3", 0x39174, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_3", 0x39178, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_3", 0x3917c, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_4", 0x39180, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_4", 0x39184, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_4", 0x39188, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_4", 0x3918c, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_4", 0x39190, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_4", 0x39194, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_4", 0x39198, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_4", 0x3919c, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_5", 0x391a0, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_5", 0x391a4, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_5", 0x391a8, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_5", 0x391ac, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_5", 0x391b0, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_5", 0x391b4, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_5", 0x391b8, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_5", 0x391bc, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_6", 0x391c0, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_6", 0x391c4, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_6", 0x391c8, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_6", 0x391cc, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_6", 0x391d0, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_6", 0x391d4, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_6", 0x391d8, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_6", 0x391dc, 0 },
+	{ "MAC_MTIP_FEC74_FEC_ABILITY_7", 0x391e0, 0 },
+		{ "FEC_Error_Indication_Ability", 1, 1 },
+		{ "FEC_Ability", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_CONTROL_7", 0x391e4, 0 },
+		{ "FEC_Enable_Error_Indication", 1, 1 },
+		{ "FEC_Enable", 0, 1 },
+	{ "MAC_MTIP_FEC74_FEC_STATUS_7", 0x391e8, 0 },
+		{ "FEC_Locked_1", 1, 1 },
+		{ "FEC_Locked", 0, 1 },
+	{ "MAC_MTIP_FEC74_VL0_CCW_LO_7", 0x391ec, 0 },
+	{ "MAC_MTIP_FEC74_VL0_NCCW_LO_7", 0x391f0, 0 },
+	{ "MAC_MTIP_FEC74_VL1_CCW_LO_7", 0x391f4, 0 },
+	{ "MAC_MTIP_FEC74_VL1_NCCW_LO_7", 0x391f8, 0 },
+	{ "MAC_MTIP_FEC74_COUNTER_HI_7", 0x391fc, 0 },
+	{ "MAC_BEAN0_CTL", 0x39200, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN0_STATUS", 0x39204, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN0_ABILITY_0", 0x39208, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN0_ABILITY_1", 0x3920c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN0_ABILITY_2", 0x39210, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN0_REM_ABILITY_0", 0x39214, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN0_REM_ABILITY_1", 0x39218, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN0_REM_ABILITY_2", 0x3921c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN0_MS_COUNT", 0x39220, 0 },
+	{ "MAC_BEAN0_XNP_0", 0x39224, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN0_XNP_1", 0x39228, 0 },
+	{ "MAC_BEAN0_XNP_2", 0x3922c, 0 },
+	{ "MAC_LP_BEAN0_XNP_0", 0x39230, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN0_XNP_1", 0x39234, 0 },
+	{ "MAC_LP_BEAN0_XNP_2", 0x39238, 0 },
+	{ "MAC_BEAN0_ETH_STATUS", 0x3923c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN0_ETH_STATUS_2", 0x39240, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN1_CTL", 0x39300, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN1_STATUS", 0x39304, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN1_ABILITY_0", 0x39308, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN1_ABILITY_1", 0x3930c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN1_ABILITY_2", 0x39310, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN1_REM_ABILITY_0", 0x39314, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN1_REM_ABILITY_1", 0x39318, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN1_REM_ABILITY_2", 0x3931c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN1_MS_COUNT", 0x39320, 0 },
+	{ "MAC_BEAN1_XNP_0", 0x39324, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN1_XNP_1", 0x39328, 0 },
+	{ "MAC_BEAN1_XNP_2", 0x3932c, 0 },
+	{ "MAC_LP_BEAN1_XNP_0", 0x39330, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN1_XNP_1", 0x39334, 0 },
+	{ "MAC_LP_BEAN1_XNP_2", 0x39338, 0 },
+	{ "MAC_BEAN1_ETH_STATUS", 0x3933c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN1_ETH_STATUS_2", 0x39340, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN2_CTL", 0x39400, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN2_STATUS", 0x39404, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN2_ABILITY_0", 0x39408, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN2_ABILITY_1", 0x3940c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN2_ABILITY_2", 0x39410, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN2_REM_ABILITY_0", 0x39414, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN2_REM_ABILITY_1", 0x39418, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN2_REM_ABILITY_2", 0x3941c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN2_MS_COUNT", 0x39420, 0 },
+	{ "MAC_BEAN2_XNP_0", 0x39424, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN2_XNP_1", 0x39428, 0 },
+	{ "MAC_BEAN2_XNP_2", 0x3942c, 0 },
+	{ "MAC_LP_BEAN2_XNP_0", 0x39430, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN2_XNP_1", 0x39434, 0 },
+	{ "MAC_LP_BEAN2_XNP_2", 0x39438, 0 },
+	{ "MAC_BEAN2_ETH_STATUS", 0x3943c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN2_ETH_STATUS_2", 0x39440, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN3_CTL", 0x39500, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN3_STATUS", 0x39504, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN3_ABILITY_0", 0x39508, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN3_ABILITY_1", 0x3950c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN3_ABILITY_2", 0x39510, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN3_REM_ABILITY_0", 0x39514, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN3_REM_ABILITY_1", 0x39518, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN3_REM_ABILITY_2", 0x3951c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN3_MS_COUNT", 0x39520, 0 },
+	{ "MAC_BEAN3_XNP_0", 0x39524, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN3_XNP_1", 0x39528, 0 },
+	{ "MAC_BEAN3_XNP_2", 0x3952c, 0 },
+	{ "MAC_LP_BEAN3_XNP_0", 0x39530, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN3_XNP_1", 0x39534, 0 },
+	{ "MAC_LP_BEAN3_XNP_2", 0x39538, 0 },
+	{ "MAC_BEAN3_ETH_STATUS", 0x3953c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN3_ETH_STATUS_2", 0x39540, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN4_CTL", 0x39600, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN4_STATUS", 0x39604, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN4_ABILITY_0", 0x39608, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN4_ABILITY_1", 0x3960c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN4_ABILITY_2", 0x39610, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN4_REM_ABILITY_0", 0x39614, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN4_REM_ABILITY_1", 0x39618, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN4_REM_ABILITY_2", 0x3961c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN4_MS_COUNT", 0x39620, 0 },
+	{ "MAC_BEAN4_XNP_0", 0x39624, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN4_XNP_1", 0x39628, 0 },
+	{ "MAC_BEAN4_XNP_2", 0x3962c, 0 },
+	{ "MAC_LP_BEAN4_XNP_0", 0x39630, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN4_XNP_1", 0x39634, 0 },
+	{ "MAC_LP_BEAN4_XNP_2", 0x39638, 0 },
+	{ "MAC_BEAN4_ETH_STATUS", 0x3963c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN4_ETH_STATUS_2", 0x39640, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN5_CTL", 0x39700, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN5_STATUS", 0x39704, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN5_ABILITY_0", 0x39708, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN5_ABILITY_1", 0x3970c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN5_ABILITY_2", 0x39710, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN5_REM_ABILITY_0", 0x39714, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN5_REM_ABILITY_1", 0x39718, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN5_REM_ABILITY_2", 0x3971c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN5_MS_COUNT", 0x39720, 0 },
+	{ "MAC_BEAN5_XNP_0", 0x39724, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN5_XNP_1", 0x39728, 0 },
+	{ "MAC_BEAN5_XNP_2", 0x3972c, 0 },
+	{ "MAC_LP_BEAN5_XNP_0", 0x39730, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN5_XNP_1", 0x39734, 0 },
+	{ "MAC_LP_BEAN5_XNP_2", 0x39738, 0 },
+	{ "MAC_BEAN5_ETH_STATUS", 0x3973c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN5_ETH_STATUS_2", 0x39740, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN6_CTL", 0x39800, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN6_STATUS", 0x39804, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN6_ABILITY_0", 0x39808, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN6_ABILITY_1", 0x3980c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN6_ABILITY_2", 0x39810, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN6_REM_ABILITY_0", 0x39814, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN6_REM_ABILITY_1", 0x39818, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN6_REM_ABILITY_2", 0x3981c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN6_MS_COUNT", 0x39820, 0 },
+	{ "MAC_BEAN6_XNP_0", 0x39824, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN6_XNP_1", 0x39828, 0 },
+	{ "MAC_BEAN6_XNP_2", 0x3982c, 0 },
+	{ "MAC_LP_BEAN6_XNP_0", 0x39830, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN6_XNP_1", 0x39834, 0 },
+	{ "MAC_LP_BEAN6_XNP_2", 0x39838, 0 },
+	{ "MAC_BEAN6_ETH_STATUS", 0x3983c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN6_ETH_STATUS_2", 0x39840, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_BEAN7_CTL", 0x39900, 0 },
+		{ "AN_RESET", 15, 1 },
+		{ "EXT_NXP_CTRL", 13, 1 },
+		{ "BEAN_EN", 12, 1 },
+		{ "RESTART_BEAN", 9, 1 },
+	{ "MAC_BEAN7_STATUS", 0x39904, 0 },
+		{ "PDF", 9, 1 },
+		{ "EXT_NXP_STATUS", 7, 1 },
+		{ "PAGE_RCVD", 6, 1 },
+		{ "BEAN_COMPLETE", 5, 1 },
+		{ "REM_FAULT_STATUS", 4, 1 },
+		{ "BEAN_ABILITY", 3, 1 },
+		{ "LINK_STATUS", 2, 1 },
+		{ "LP_BEAN_ABILITY", 0, 1 },
+	{ "MAC_BEAN7_ABILITY_0", 0x39908, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN7_ABILITY_1", 0x3990c, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN7_ABILITY_2", 0x39910, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN7_REM_ABILITY_0", 0x39914, 0 },
+		{ "NXP", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "REM_FAULT", 13, 1 },
+		{ "PAUSE_ABILITY", 10, 3 },
+		{ "ECHO_NONCE", 5, 5 },
+		{ "SELECTOR", 0, 5 },
+	{ "MAC_BEAN7_REM_ABILITY_1", 0x39918, 0 },
+		{ "TECH_ABILITY_1", 5, 11 },
+		{ "TX_NONCE", 0, 5 },
+	{ "MAC_BEAN7_REM_ABILITY_2", 0x3991c, 0 },
+		{ "FEC_ABILITY", 12, 4 },
+		{ "TECH_ABILITY_2", 0, 12 },
+	{ "MAC_BEAN7_MS_COUNT", 0x39920, 0 },
+	{ "MAC_BEAN7_XNP_0", 0x39924, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_BEAN7_XNP_1", 0x39928, 0 },
+	{ "MAC_BEAN7_XNP_2", 0x3992c, 0 },
+	{ "MAC_LP_BEAN7_XNP_0", 0x39930, 0 },
+		{ "XNP", 15, 1 },
+		{ "ACKNOWLEDGE", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "ACK2", 12, 1 },
+		{ "TOGGLE", 11, 1 },
+		{ "MU", 0, 11 },
+	{ "MAC_LP_BEAN7_XNP_1", 0x39934, 0 },
+	{ "MAC_LP_BEAN7_XNP_2", 0x39938, 0 },
+	{ "MAC_BEAN7_ETH_STATUS", 0x3993c, 0 },
+		{ "5GKR", 15, 1 },
+		{ "2p5GKX", 14, 1 },
+		{ "25G_KR", 13, 1 },
+		{ "25G_KR_S", 12, 1 },
+		{ "100GCR4", 11, 1 },
+		{ "100GKR4", 10, 1 },
+		{ "100GKP4", 9, 1 },
+		{ "100GCR10", 8, 1 },
+		{ "RS_FEC", 7, 1 },
+		{ "40GCR4", 6, 1 },
+		{ "40GKR4", 5, 1 },
+		{ "FC_FEC", 4, 1 },
+		{ "10GKR", 3, 1 },
+		{ "10GKX4", 2, 1 },
+		{ "1GKX", 1, 1 },
+	{ "MAC_BEAN7_ETH_STATUS_2", 0x39940, 0 },
+		{ "RS_FEC_negotiated", 6, 1 },
+		{ "400GKR4CR4", 5, 1 },
+		{ "200GKR2CR2", 4, 1 },
+		{ "100GKR1CR1", 3, 1 },
+		{ "200GKR4CR4", 2, 1 },
+		{ "100GKR2CR2", 1, 1 },
+		{ "50GKRCR", 0, 1 },
+	{ "MAC_MTIP_ETHERSTATS_DATA_HI", 0x39a00, 0 },
+	{ "MAC_MTIP_ETHERSTATS_STATN_STATUS", 0x39a04, 0 },
+	{ "MAC_MTIP_ETHERSTATS_STATN_CONFIG", 0x39a08, 0 },
+		{ "RESET", 31, 1 },
+		{ "CLEAR_ON_READ", 1, 1 },
+		{ "SATURATE", 0, 1 },
+	{ "MAC_MTIP_ETHERSTATS_STATN_CONTROL", 0x39a0c, 0 },
+		{ "CMD_CLEAR_TX", 31, 1 },
+		{ "CMD_CLEAR_RX", 30, 1 },
+		{ "CLEAR_PRE", 29, 1 },
+		{ "CMD_CAPTURE_TX", 28, 1 },
+		{ "CMD_CAPTURE_RX", 27, 1 },
+		{ "PORTMASK", 0, 8 },
+	{ "MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_LO", 0x39a10, 0 },
+	{ "MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_HI", 0x39a14, 0 },
+	{ "MAC_MTIP_ETHERSTATS_DATA_HI_1", 0x39a1c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_0", 0x39a20, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_1", 0x39a24, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_2", 0x39a28, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_3", 0x39a2c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_4", 0x39a30, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_5", 0x39a34, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_6", 0x39a38, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_7", 0x39a3c, 0 },
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+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_12", 0x39a50, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_13", 0x39a54, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_14", 0x39a58, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_15", 0x39a5c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_16", 0x39a60, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_17", 0x39a64, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_18", 0x39a68, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_19", 0x39a6c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_20", 0x39a70, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_21", 0x39a74, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_22", 0x39a78, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_23", 0x39a7c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_24", 0x39a80, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_25", 0x39a84, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_26", 0x39a88, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_27", 0x39a8c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_28", 0x39a90, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_29", 0x39a94, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_30", 0x39a98, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_31", 0x39a9c, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_32", 0x39aa0, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_33", 0x39aa4, 0 },
+	{ "MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_34", 0x39aa8, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS", 0x39b00, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_OCTETSRECEIVEDOK", 0x39b04, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AALIGNMENTERRORS", 0x39b08, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESRECEIVED", 0x39b0c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AFRAMETOOLONGERRORS", 0x39b10, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AINRANGELENGTHERRORS", 0x39b14, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AFRAMESRECEIVEDOK", 0x39b18, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AFRAMECHECKSEQUENCEERRORS", 0x39b1c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_VLANRECEIVEDOK", 0x39b20, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFINERRORS_RX", 0x39b24, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFINUCASTPKTS_RX", 0x39b28, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFINMULTICASTPKTS_RX", 0x39b2c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFINBROADCASTPKTS_RX", 0x39b30, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSDROPEVENTS_RX", 0x39b34, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_RX", 0x39b38, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSUNDERSIZEPKTS_RX", 0x39b3c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_RX", 0x39b40, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_RX", 0x39b44, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_RX", 0x39b48, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_RX", 0x39b4c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_RX", 0x39b50, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_RX", 0x39b54, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_RX", 0x39b58, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSOVERSIZEPKTS_RX", 0x39b5c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSJABBERS_RX", 0x39b60, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSFRAGMENTS_RX", 0x39b64, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_0_RX", 0x39b68, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_1_RX", 0x39b6c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_2_RX", 0x39b70, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_3_RX", 0x39b74, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_4_RX", 0x39b78, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_5_RX", 0x39b7c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_6_RX", 0x39b80, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_7_RX", 0x39b84, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESRECEIVED_RX", 0x39b88, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS", 0x39b8c, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_OCTETSRECEIVEDOK", 0x39b90, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AALIGNMENTERRORS", 0x39b94, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESRECEIVED", 0x39b98, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AFRAMETOOLONGERRORS", 0x39b9c, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AINRANGELENGTHERRORS", 0x39ba0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AFRAMESRECEIVEDOK", 0x39ba4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AFRAMECHECKSEQUENCEERRORS", 0x39ba8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_VLANRECEIVEDOK", 0x39bac, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFINERRORS_RX", 0x39bb0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFINUCASTPKTS_RX", 0x39bb4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFINMULTICASTPKTS_RX", 0x39bb8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFINBROADCASTPKTS_RX", 0x39bbc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSDROPEVENTS_RX", 0x39bc0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_RX", 0x39bc4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSUNDERSIZEPKTS_RX", 0x39bc8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_RX", 0x39bcc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_RX", 0x39bd0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_RX", 0x39bd4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_RX", 0x39bd8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_RX", 0x39bdc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_RX", 0x39be0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_RX", 0x39be4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSOVERSIZEPKTS_RX", 0x39be8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSJABBERS_RX", 0x39bec, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSFRAGMENTS_RX", 0x39bf0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_0_RX", 0x39bf4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_1_RX", 0x39bf8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_2_RX", 0x39bfc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_3_RX", 0x39c00, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_4_RX", 0x39c04, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_5_RX", 0x39c08, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_6_RX", 0x39c0c, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_7_RX", 0x39c10, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESRECEIVED_RX", 0x39c14, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS", 0x39c18, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_OCTETSRECEIVEDOK", 0x39c1c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AALIGNMENTERRORS", 0x39c20, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESRECEIVED", 0x39c24, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AFRAMETOOLONGERRORS", 0x39c28, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AINRANGELENGTHERRORS", 0x39c2c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AFRAMESRECEIVEDOK", 0x39c30, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AFRAMECHECKSEQUENCEERRORS", 0x39c34, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_VLANRECEIVEDOK", 0x39c38, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFINERRORS_RX", 0x39c3c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFINUCASTPKTS_RX", 0x39c40, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFINMULTICASTPKTS_RX", 0x39c44, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFINBROADCASTPKTS_RX", 0x39c48, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSDROPEVENTS_RX", 0x39c4c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_RX", 0x39c50, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSUNDERSIZEPKTS_RX", 0x39c54, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_RX", 0x39c58, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_RX", 0x39c5c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_RX", 0x39c60, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_RX", 0x39c64, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_RX", 0x39c68, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_RX", 0x39c6c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_RX", 0x39c70, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSOVERSIZEPKTS_RX", 0x39c74, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSJABBERS_RX", 0x39c78, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSFRAGMENTS_RX", 0x39c7c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_0_RX", 0x39c80, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_1_RX", 0x39c84, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_2_RX", 0x39c88, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_3_RX", 0x39c8c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_4_RX", 0x39c90, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_5_RX", 0x39c94, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_6_RX", 0x39c98, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_7_RX", 0x39c9c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESRECEIVED_RX", 0x39ca0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS", 0x39ca4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_OCTETSRECEIVEDOK", 0x39ca8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AALIGNMENTERRORS", 0x39cac, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESRECEIVED", 0x39cb0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AFRAMETOOLONGERRORS", 0x39cb4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AINRANGELENGTHERRORS", 0x39cb8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AFRAMESRECEIVEDOK", 0x39cbc, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AFRAMECHECKSEQUENCEERRORS", 0x39cc0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_VLANRECEIVEDOK", 0x39cc4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFINERRORS_RX", 0x39cc8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFINUCASTPKTS_RX", 0x39ccc, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFINMULTICASTPKTS_RX", 0x39cd0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFINBROADCASTPKTS_RX", 0x39cd4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSDROPEVENTS_RX", 0x39cd8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_RX", 0x39cdc, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSUNDERSIZEPKTS_RX", 0x39ce0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_RX", 0x39ce4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_RX", 0x39ce8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_RX", 0x39cec, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_RX", 0x39cf0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_RX", 0x39cf4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_RX", 0x39cf8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_RX", 0x39cfc, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSOVERSIZEPKTS_RX", 0x39d00, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSJABBERS_RX", 0x39d04, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSFRAGMENTS_RX", 0x39d08, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_0_RX", 0x39d0c, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_1_RX", 0x39d10, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_2_RX", 0x39d14, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_3_RX", 0x39d18, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_4_RX", 0x39d1c, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_5_RX", 0x39d20, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_6_RX", 0x39d24, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_7_RX", 0x39d28, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESRECEIVED_RX", 0x39d2c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS_TX", 0x39d30, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_OCTETSTRANSMITTEDOK_TX", 0x39d34, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESTRANSMITTED_TX", 0x39d38, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AFRAMESTRANSMITTEDOK_TX", 0x39d3c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_VLANTRANSMITTEDOK_TX", 0x39d40, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFOUTERRORS_TX", 0x39d44, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFOUTUCASTPKTS_TX", 0x39d48, 0 },
+	{ "MAC_MTIP_ETHERSTATS0IFOUTMULTICASTPKTS_TX", 0x39d4c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_IFOUTBROADCASTPKTS_TX", 0x39d50, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_TX", 0x39d54, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_TX", 0x39d58, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_TX", 0x39d5c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_TX", 0x39d60, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_TX", 0x39d64, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_TX", 0x39d68, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_TX", 0x39d6c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_0_TX", 0x39d70, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_1_TX", 0x39d74, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_2_TX", 0x39d78, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_3_TX", 0x39d7c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_4_TX", 0x39d80, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_5_TX", 0x39d84, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_6_TX", 0x39d88, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_7_TX", 0x39d8c, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESTRANSMITTED_TX", 0x39d90, 0 },
+	{ "MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_TX", 0x39d94, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS_TX", 0x39d98, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_OCTETSTRANSMITTEDOK_TX", 0x39d9c, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESTRANSMITTED_TX", 0x39da0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AFRAMESTRANSMITTEDOK_TX", 0x39da4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_VLANTRANSMITTEDOK_TX", 0x39da8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFOUTERRORS_TX", 0x39dac, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFOUTUCASTPKTS_TX", 0x39db0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1IFOUTMULTICASTPKTS_TX", 0x39db4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_IFOUTBROADCASTPKTS_TX", 0x39db8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_TX", 0x39dbc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_TX", 0x39dc0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_TX", 0x39dc4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_TX", 0x39dc8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_TX", 0x39dcc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_TX", 0x39dd0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_TX", 0x39dd4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_0_TX", 0x39dd8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_1_TX", 0x39ddc, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_2_TX", 0x39de0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_3_TX", 0x39de4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_4_TX", 0x39de8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_5_TX", 0x39dec, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_6_TX", 0x39df0, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_7_TX", 0x39df4, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESTRANSMITTED_TX", 0x39df8, 0 },
+	{ "MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_TX", 0x39dfc, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS_TX", 0x39e00, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_OCTETSTRANSMITTEDOK_TX", 0x39e04, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESTRANSMITTED_TX", 0x39e08, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AFRAMESTRANSMITTEDOK_TX", 0x39e0c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_VLANTRANSMITTEDOK_TX", 0x39e10, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFOUTERRORS_TX", 0x39e14, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFOUTUCASTPKTS_TX", 0x39e18, 0 },
+	{ "MAC_MTIP_ETHERSTATS2IFOUTMULTICASTPKTS_TX", 0x39e1c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_IFOUTBROADCASTPKTS_TX", 0x39e20, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_TX", 0x39e24, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_TX", 0x39e28, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_TX", 0x39e2c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_TX", 0x39e30, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_TX", 0x39e34, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_TX", 0x39e38, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_TX", 0x39e3c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_0_TX", 0x39e40, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_1_TX", 0x39e44, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_2_TX", 0x39e48, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_3_TX", 0x39e4c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_4_TX", 0x39e50, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_5_TX", 0x39e54, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_6_TX", 0x39e58, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_7_TX", 0x39e5c, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESTRANSMITTED_TX", 0x39e60, 0 },
+	{ "MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_TX", 0x39e64, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS_TX", 0x39e68, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_OCTETSTRANSMITTEDOK_TX", 0x39e6c, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESTRANSMITTED_TX", 0x39e70, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AFRAMESTRANSMITTEDOK_TX", 0x39e74, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_VLANTRANSMITTEDOK_TX", 0x39e78, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFOUTERRORS_TX", 0x39e7c, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFOUTUCASTPKTS_TX", 0x39e80, 0 },
+	{ "MAC_MTIP_ETHERSTATS3IFOUTMULTICASTPKTS_TX", 0x39e84, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_IFOUTBROADCASTPKTS_TX", 0x39e88, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_TX", 0x39e8c, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_TX", 0x39e90, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_TX", 0x39e94, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_TX", 0x39e98, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_TX", 0x39e9c, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_TX", 0x39ea0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_TX", 0x39ea4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_0_TX", 0x39ea8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_1_TX", 0x39eac, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_2_TX", 0x39eb0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_3_TX", 0x39eb4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_4_TX", 0x39eb8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_5_TX", 0x39ebc, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_6_TX", 0x39ec0, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_7_TX", 0x39ec4, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESTRANSMITTED_TX", 0x39ec8, 0 },
+	{ "MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_TX", 0x39ecc, 0 },
+	{ "MAC_IOS_CTRL", 0x3a000, 0 },
+		{ "sub_block_sel", 28, 3 },
+		{ "quad_broadcast_en", 24, 1 },
+		{ "auto_incr", 20, 1 },
+		{ "addr", 0, 19 },
+	{ "MAC_IOS_DATA", 0x3a004, 0 },
+	{ "MAC_IOS_BGR_RST", 0x3a050, 0 },
+	{ "MAC_IOS_BGR_CFG", 0x3a054, 0 },
+	{ "MAC_IOS_QUAD0_CFG", 0x3a058, 0 },
+		{ "quad0_ch3_rstn", 5, 1 },
+		{ "quad0_ch2_rstn", 4, 1 },
+		{ "quad0_ch1_rstn", 3, 1 },
+		{ "quad0_ch0_rstn", 2, 1 },
+		{ "quad0_rstn", 1, 1 },
+		{ "pll0_rstn", 0, 1 },
+	{ "MAC_IOS_QUAD1_CFG", 0x3a05c, 0 },
+		{ "quad1_ch3_rstn", 5, 1 },
+		{ "quad1_ch2_rstn", 4, 1 },
+		{ "quad1_ch1_rstn", 3, 1 },
+		{ "quad1_ch0_rstn", 2, 1 },
+		{ "quad1_rstn", 1, 1 },
+		{ "pll1_rstn", 0, 1 },
+	{ "MAC_IOS_SCRATCHPAD0", 0x3a060, 0 },
+	{ "MAC_IOS_SCRATCHPAD1", 0x3a064, 0 },
+	{ "MAC_IOS_SCRATCHPAD2", 0x3a068, 0 },
+	{ "MAC_IOS_SCRATCHPAD3", 0x3a06c, 0 },
+		{ "data0", 1, 31 },
+		{ "i2c_mode", 0, 1 },
+	{ "MAC_IOS_BGR_DBG_COUNTER", 0x3a070, 0 },
+	{ "MAC_IOS_QUAD0_DBG_COUNTER", 0x3a074, 0 },
+	{ "MAC_IOS_PLL0_DBG_COUNTER", 0x3a078, 0 },
+	{ "MAC_IOS_QUAD1_DBG_COUNTER", 0x3a07c, 0 },
+	{ "MAC_IOS_PLL1_DBG_COUNTER", 0x3a080, 0 },
+	{ "MAC_IOS_DBG_CLK_CFG", 0x3a084, 0 },
+		{ "dbg_clk_mux_gpio", 3, 1 },
+		{ "dbg_clk_mux_sel", 0, 3 },
+	{ "MAC_IOS_INTR_EN_QUAD0", 0x3a090, 0 },
+		{ "Q0_MAILBOX_INT_assert", 24, 1 },
+		{ "Q0_TRAINING_FAILURE_3_assert", 23, 1 },
+		{ "Q0_TRAINING_FAILURE_2_assert", 22, 1 },
+		{ "Q0_TRAINING_FAILURE_1_assert", 21, 1 },
+		{ "Q0_TRAINING_FAILURE_0_assert", 20, 1 },
+		{ "Q0_TRAINING_COMPLETE_3_assert", 19, 1 },
+		{ "Q0_TRAINING_COMPLETE_2_assert", 18, 1 },
+		{ "Q0_TRAINING_COMPLETE_1_assert", 17, 1 },
+		{ "Q0_TRAINING_COMPLETE_0_assert", 16, 1 },
+		{ "Q0_AN_TX_INT_3_assert", 15, 1 },
+		{ "Q0_AN_TX_INT_2_assert", 14, 1 },
+		{ "Q0_AN_TX_INT_1_assert", 13, 1 },
+		{ "Q0_AN_TX_INT_0_assert", 12, 1 },
+		{ "Q0_SIGNAL_DETECT_3_assert", 11, 1 },
+		{ "Q0_SIGNAL_DETECT_2_assert", 10, 1 },
+		{ "Q0_SIGNAL_DETECT_1_assert", 9, 1 },
+		{ "Q0_SIGNAL_DETECT_0_assert", 8, 1 },
+		{ "Q0_CDR_LOL_3_assert", 7, 1 },
+		{ "Q0_CDR_LOL_2_assert", 6, 1 },
+		{ "Q0_CDR_LOL_1_assert", 5, 1 },
+		{ "Q0_CDR_LOL_0_assert", 4, 1 },
+		{ "Q0_LOS_3_assert", 3, 1 },
+		{ "Q0_LOS_2_assert", 2, 1 },
+		{ "Q0_LOS_1_assert", 1, 1 },
+		{ "Q0_LOS_0_assert", 0, 1 },
+	{ "MAC_IOS_INTR_CAUSE_QUAD0", 0x3a094, 0 },
+		{ "Q0_MAILBOX_INT_assert", 24, 1 },
+		{ "Q0_TRAINING_FAILURE_3_assert", 23, 1 },
+		{ "Q0_TRAINING_FAILURE_2_assert", 22, 1 },
+		{ "Q0_TRAINING_FAILURE_1_assert", 21, 1 },
+		{ "Q0_TRAINING_FAILURE_0_assert", 20, 1 },
+		{ "Q0_TRAINING_COMPLETE_3_assert", 19, 1 },
+		{ "Q0_TRAINING_COMPLETE_2_assert", 18, 1 },
+		{ "Q0_TRAINING_COMPLETE_1_assert", 17, 1 },
+		{ "Q0_TRAINING_COMPLETE_0_assert", 16, 1 },
+		{ "Q0_AN_TX_INT_3_assert", 15, 1 },
+		{ "Q0_AN_TX_INT_2_assert", 14, 1 },
+		{ "Q0_AN_TX_INT_1_assert", 13, 1 },
+		{ "Q0_AN_TX_INT_0_assert", 12, 1 },
+		{ "Q0_SIGNAL_DETECT_3_assert", 11, 1 },
+		{ "Q0_SIGNAL_DETECT_2_assert", 10, 1 },
+		{ "Q0_SIGNAL_DETECT_1_assert", 9, 1 },
+		{ "Q0_SIGNAL_DETECT_0_assert", 8, 1 },
+		{ "Q0_CDR_LOL_3_assert", 7, 1 },
+		{ "Q0_CDR_LOL_2_assert", 6, 1 },
+		{ "Q0_CDR_LOL_1_assert", 5, 1 },
+		{ "Q0_CDR_LOL_0_assert", 4, 1 },
+		{ "Q0_LOS_3_assert", 3, 1 },
+		{ "Q0_LOS_2_assert", 2, 1 },
+		{ "Q0_LOS_1_assert", 1, 1 },
+		{ "Q0_LOS_0_assert", 0, 1 },
+	{ "MAC_IOS_INTR_EN_QUAD1", 0x3a098, 0 },
+		{ "Q1_MAILBOX_INT_assert", 24, 1 },
+		{ "Q1_TRAINING_FAILURE_3_assert", 23, 1 },
+		{ "Q1_TRAINING_FAILURE_2_assert", 22, 1 },
+		{ "Q1_TRAINING_FAILURE_1_assert", 21, 1 },
+		{ "Q1_TRAINING_FAILURE_0_assert", 20, 1 },
+		{ "Q1_TRAINING_COMPLETE_3_assert", 19, 1 },
+		{ "Q1_TRAINING_COMPLETE_2_assert", 18, 1 },
+		{ "Q1_TRAINING_COMPLETE_1_assert", 17, 1 },
+		{ "Q1_TRAINING_COMPLETE_0_assert", 16, 1 },
+		{ "Q1_AN_TX_INT_3_assert", 15, 1 },
+		{ "Q1_AN_TX_INT_2_assert", 14, 1 },
+		{ "Q1_AN_TX_INT_1_assert", 13, 1 },
+		{ "Q1_AN_TX_INT_0_assert", 12, 1 },
+		{ "Q1_SIGNAL_DETECT_3_assert", 11, 1 },
+		{ "Q1_SIGNAL_DETECT_2_assert", 10, 1 },
+		{ "Q1_SIGNAL_DETECT_1_assert", 9, 1 },
+		{ "Q1_SIGNAL_DETECT_0_assert", 8, 1 },
+		{ "Q1_CDR_LOL_3_assert", 7, 1 },
+		{ "Q1_CDR_LOL_2_assert", 6, 1 },
+		{ "Q1_CDR_LOL_1_assert", 5, 1 },
+		{ "Q1_CDR_LOL_0_assert", 4, 1 },
+		{ "Q1_LOS_3_assert", 3, 1 },
+		{ "Q1_LOS_2_assert", 2, 1 },
+		{ "Q1_LOS_1_assert", 1, 1 },
+		{ "Q1_LOS_0_assert", 0, 1 },
+	{ "MAC_IOS_INTR_CAUSE_QUAD1", 0x3a09c, 0 },
+		{ "Q1_MAILBOX_INT_assert", 24, 1 },
+		{ "Q1_TRAINING_FAILURE_3_assert", 23, 1 },
+		{ "Q1_TRAINING_FAILURE_2_assert", 22, 1 },
+		{ "Q1_TRAINING_FAILURE_1_assert", 21, 1 },
+		{ "Q1_TRAINING_FAILURE_0_assert", 20, 1 },
+		{ "Q1_TRAINING_COMPLETE_3_assert", 19, 1 },
+		{ "Q1_TRAINING_COMPLETE_2_assert", 18, 1 },
+		{ "Q1_TRAINING_COMPLETE_1_assert", 17, 1 },
+		{ "Q1_TRAINING_COMPLETE_0_assert", 16, 1 },
+		{ "Q1_AN_TX_INT_3_assert", 15, 1 },
+		{ "Q1_AN_TX_INT_2_assert", 14, 1 },
+		{ "Q1_AN_TX_INT_1_assert", 13, 1 },
+		{ "Q1_AN_TX_INT_0_assert", 12, 1 },
+		{ "Q1_SIGNAL_DETECT_3_assert", 11, 1 },
+		{ "Q1_SIGNAL_DETECT_2_assert", 10, 1 },
+		{ "Q1_SIGNAL_DETECT_1_assert", 9, 1 },
+		{ "Q1_SIGNAL_DETECT_0_assert", 8, 1 },
+		{ "Q1_CDR_LOL_3_assert", 7, 1 },
+		{ "Q1_CDR_LOL_2_assert", 6, 1 },
+		{ "Q1_CDR_LOL_1_assert", 5, 1 },
+		{ "Q1_CDR_LOL_0_assert", 4, 1 },
+		{ "Q1_LOS_3_assert", 3, 1 },
+		{ "Q1_LOS_2_assert", 2, 1 },
+		{ "Q1_LOS_1_assert", 1, 1 },
+		{ "Q1_LOS_0_assert", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_0_CONTROL", 0x3e000, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_Sel_1", 13, 1 },
+		{ "Auto_Neg_Ena", 12, 1 },
+		{ "power_down", 11, 1 },
+		{ "isolate", 10, 1 },
+		{ "restart_auto_neg", 9, 1 },
+		{ "duplex_mode", 8, 1 },
+		{ "collision_test", 7, 1 },
+		{ "Speed_Sel_0", 6, 1 },
+	{ "MAC_MTIP_PCS_1G_0_STATUS", 0x3e004, 0 },
+		{ "100Base_T4", 15, 1 },
+		{ "100Base_X_full_duplex", 14, 1 },
+		{ "100Base_X_half_duplex", 13, 1 },
+		{ "10Mbps_full_duplex", 12, 1 },
+		{ "10Mbps_half_duplex", 11, 1 },
+		{ "100Base_T2_half_duplex1", 10, 1 },
+		{ "100Base_T2_half_duplex0", 9, 1 },
+		{ "Extended_status", 8, 1 },
+		{ "Auto_neg_complete", 5, 1 },
+		{ "Remote_fault", 4, 1 },
+		{ "Auto_neg_ability", 3, 1 },
+		{ "Link_status", 2, 1 },
+		{ "Jabber_detect", 1, 1 },
+		{ "extended_capability", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_0", 0x3e008, 0 },
+	{ "MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_1", 0x3e00c, 0 },
+	{ "MAC_MTIP_PCS_1G_0_DEV_ABILITY", 0x3e010, 0 },
+		{ "ACK", 14, 1 },
+		{ "EEE_Clock_Stop_enable", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_0_PARTNER_ABILITY", 0x3e014, 0 },
+		{ "Copper_Link_Status", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "Copper_Duplex_Status", 12, 1 },
+		{ "Copper_Speed", 10, 2 },
+		{ "EEE_Capability", 9, 1 },
+		{ "EEE_Clock_Stop_Capability", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_0_AN_EXPANSION", 0x3e018, 0 },
+		{ "Next_Page_Able", 2, 1 },
+		{ "Page_Receive", 1, 1 },
+	{ "MAC_MTIP_PCS_1G_0_NP_TX", 0x3e01c, 0 },
+	{ "MAC_MTIP_PCS_1G_0_LP_NP_RX", 0x3e020, 0 },
+		{ "NP", 15, 1 },
+		{ "Ack", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "Ack2", 12, 1 },
+		{ "Toggle", 11, 1 },
+		{ "data", 0, 11 },
+	{ "MAC_MTIP_PCS_1G_0_EXTENDED_STATUS", 0x3e03c, 0 },
+	{ "MAC_MTIP_PCS_1G_0_SCRATCH", 0x3e040, 0 },
+	{ "MAC_MTIP_PCS_1G_0_REV", 0x3e044, 0 },
+	{ "MAC_MTIP_PCS_1G_0_LINK_TIMER_0", 0x3e048, 0 },
+	{ "MAC_MTIP_PCS_1G_0_LINK_TIMER_1", 0x3e04c, 0 },
+	{ "MAC_MTIP_PCS_1G_0_IF_MODE", 0x3e050, 0 },
+		{ "SGMII_DUPLEX", 4, 1 },
+		{ "SGMII_SPEED", 2, 2 },
+		{ "USE_SGMII_AN", 1, 1 },
+		{ "SGMII_ENA", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_0_DEC_ERR_CNT", 0x3e054, 0 },
+	{ "MAC_MTIP_PCS_1G_0_VENDOR_CONTROL", 0x3e058, 0 },
+		{ "SGPCS_ENA_ST", 15, 1 },
+		{ "CFG_CLOCK_RATE", 4, 4 },
+		{ "SGPCS_ENA_R", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_0_SD_BIT_SLIP", 0x3e05c, 0 },
+	{ "MAC_MTIP_PCS_1G_1_CONTROL", 0x3e100, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_Sel_1", 13, 1 },
+		{ "Auto_Neg_Ena", 12, 1 },
+		{ "power_down", 11, 1 },
+		{ "isolate", 10, 1 },
+		{ "restart_auto_neg", 9, 1 },
+		{ "duplex_mode", 8, 1 },
+		{ "collision_test", 7, 1 },
+		{ "Speed_Sel_0", 6, 1 },
+	{ "MAC_MTIP_PCS_1G_1_STATUS", 0x3e104, 0 },
+		{ "100Base_T4", 15, 1 },
+		{ "100Base_X_full_duplex", 14, 1 },
+		{ "100Base_X_half_duplex", 13, 1 },
+		{ "10Mbps_full_duplex", 12, 1 },
+		{ "10Mbps_half_duplex", 11, 1 },
+		{ "100Base_T2_half_duplex1", 10, 1 },
+		{ "100Base_T2_half_duplex0", 9, 1 },
+		{ "Extended_status", 8, 1 },
+		{ "Auto_neg_complete", 5, 1 },
+		{ "Remote_fault", 4, 1 },
+		{ "Auto_neg_ability", 3, 1 },
+		{ "Link_status", 2, 1 },
+		{ "Jabber_detect", 1, 1 },
+		{ "extended_capability", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_0", 0x3e108, 0 },
+	{ "MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_1", 0x3e10c, 0 },
+	{ "MAC_MTIP_PCS_1G_1_DEV_ABILITY", 0x3e110, 0 },
+		{ "ACK", 14, 1 },
+		{ "EEE_Clock_Stop_enable", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_1_PARTNER_ABILITY", 0x3e114, 0 },
+		{ "Copper_Link_Status", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "Copper_Duplex_Status", 12, 1 },
+		{ "Copper_Speed", 10, 2 },
+		{ "EEE_Capability", 9, 1 },
+		{ "EEE_Clock_Stop_Capability", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_1_AN_EXPANSION", 0x3e118, 0 },
+		{ "Next_Page_Able", 2, 1 },
+		{ "Page_Receive", 1, 1 },
+	{ "MAC_MTIP_PCS_1G_1_NP_TX", 0x3e11c, 0 },
+	{ "MAC_MTIP_PCS_1G_1_LP_NP_RX", 0x3e120, 0 },
+		{ "NP", 15, 1 },
+		{ "Ack", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "Ack2", 12, 1 },
+		{ "Toggle", 11, 1 },
+		{ "data", 0, 11 },
+	{ "MAC_MTIP_PCS_1G_1_EXTENDED_STATUS", 0x3e13c, 0 },
+	{ "MAC_MTIP_PCS_1G_1_SCRATCH", 0x3e140, 0 },
+	{ "MAC_MTIP_PCS_1G_1_REV", 0x3e144, 0 },
+	{ "MAC_MTIP_PCS_1G_1_LINK_TIMER_0", 0x3e148, 0 },
+	{ "MAC_MTIP_PCS_1G_1_LINK_TIMER_1", 0x3e14c, 0 },
+	{ "MAC_MTIP_PCS_1G_1_IF_MODE", 0x3e150, 0 },
+		{ "SGMII_DUPLEX", 4, 1 },
+		{ "SGMII_SPEED", 2, 2 },
+		{ "USE_SGMII_AN", 1, 1 },
+		{ "SGMII_ENA", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_1_DEC_ERR_CNT", 0x3e154, 0 },
+	{ "MAC_MTIP_PCS_1G_1_VENDOR_CONTROL", 0x3e158, 0 },
+		{ "SGPCS_ENA_ST", 15, 1 },
+		{ "CFG_CLOCK_RATE", 4, 4 },
+		{ "SGPCS_ENA_R", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_1_SD_BIT_SLIP", 0x3e15c, 0 },
+	{ "MAC_MTIP_PCS_1G_2_CONTROL", 0x3e200, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_Sel_1", 13, 1 },
+		{ "Auto_Neg_Ena", 12, 1 },
+		{ "power_down", 11, 1 },
+		{ "isolate", 10, 1 },
+		{ "restart_auto_neg", 9, 1 },
+		{ "duplex_mode", 8, 1 },
+		{ "collision_test", 7, 1 },
+		{ "Speed_Sel_0", 6, 1 },
+	{ "MAC_MTIP_PCS_1G_2_STATUS", 0x3e204, 0 },
+		{ "100Base_T4", 15, 1 },
+		{ "100Base_X_full_duplex", 14, 1 },
+		{ "100Base_X_half_duplex", 13, 1 },
+		{ "10Mbps_full_duplex", 12, 1 },
+		{ "10Mbps_half_duplex", 11, 1 },
+		{ "100Base_T2_half_duplex1", 10, 1 },
+		{ "100Base_T2_half_duplex0", 9, 1 },
+		{ "Extended_status", 8, 1 },
+		{ "Auto_neg_complete", 5, 1 },
+		{ "Remote_fault", 4, 1 },
+		{ "Auto_neg_ability", 3, 1 },
+		{ "Link_status", 2, 1 },
+		{ "Jabber_detect", 1, 1 },
+		{ "extended_capability", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_0", 0x3e208, 0 },
+	{ "MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_1", 0x3e20c, 0 },
+	{ "MAC_MTIP_PCS_1G_2_DEV_ABILITY", 0x3e210, 0 },
+		{ "ACK", 14, 1 },
+		{ "EEE_Clock_Stop_enable", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_2_PARTNER_ABILITY", 0x3e214, 0 },
+		{ "Copper_Link_Status", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "Copper_Duplex_Status", 12, 1 },
+		{ "Copper_Speed", 10, 2 },
+		{ "EEE_Capability", 9, 1 },
+		{ "EEE_Clock_Stop_Capability", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_2_AN_EXPANSION", 0x3e218, 0 },
+		{ "Next_Page_Able", 2, 1 },
+		{ "Page_Receive", 1, 1 },
+	{ "MAC_MTIP_PCS_1G_2_NP_TX", 0x3e21c, 0 },
+	{ "MAC_MTIP_PCS_1G_2_LP_NP_RX", 0x3e220, 0 },
+		{ "NP", 15, 1 },
+		{ "Ack", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "Ack2", 12, 1 },
+		{ "Toggle", 11, 1 },
+		{ "data", 0, 11 },
+	{ "MAC_MTIP_PCS_1G_2_EXTENDED_STATUS", 0x3e23c, 0 },
+	{ "MAC_MTIP_PCS_1G_2_SCRATCH", 0x3e240, 0 },
+	{ "MAC_MTIP_PCS_1G_2_REV", 0x3e244, 0 },
+	{ "MAC_MTIP_PCS_1G_2_LINK_TIMER_0", 0x3e248, 0 },
+	{ "MAC_MTIP_PCS_1G_2_LINK_TIMER_1", 0x3e24c, 0 },
+	{ "MAC_MTIP_PCS_1G_2_IF_MODE", 0x3e250, 0 },
+		{ "SGMII_DUPLEX", 4, 1 },
+		{ "SGMII_SPEED", 2, 2 },
+		{ "USE_SGMII_AN", 1, 1 },
+		{ "SGMII_ENA", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_2_DEC_ERR_CNT", 0x3e254, 0 },
+	{ "MAC_MTIP_PCS_1G_2_VENDOR_CONTROL", 0x3e258, 0 },
+		{ "SGPCS_ENA_ST", 15, 1 },
+		{ "CFG_CLOCK_RATE", 4, 4 },
+		{ "SGPCS_ENA_R", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_2_SD_BIT_SLIP", 0x3e25c, 0 },
+	{ "MAC_MTIP_PCS_1G_3_CONTROL", 0x3e300, 0 },
+		{ "Reset", 15, 1 },
+		{ "Loopback", 14, 1 },
+		{ "Speed_Sel_1", 13, 1 },
+		{ "Auto_Neg_Ena", 12, 1 },
+		{ "power_down", 11, 1 },
+		{ "isolate", 10, 1 },
+		{ "restart_auto_neg", 9, 1 },
+		{ "duplex_mode", 8, 1 },
+		{ "collision_test", 7, 1 },
+		{ "Speed_Sel_0", 6, 1 },
+	{ "MAC_MTIP_PCS_1G_3_STATUS", 0x3e304, 0 },
+		{ "100Base_T4", 15, 1 },
+		{ "100Base_X_full_duplex", 14, 1 },
+		{ "100Base_X_half_duplex", 13, 1 },
+		{ "10Mbps_full_duplex", 12, 1 },
+		{ "10Mbps_half_duplex", 11, 1 },
+		{ "100Base_T2_half_duplex1", 10, 1 },
+		{ "100Base_T2_half_duplex0", 9, 1 },
+		{ "Extended_status", 8, 1 },
+		{ "Auto_neg_complete", 5, 1 },
+		{ "Remote_fault", 4, 1 },
+		{ "Auto_neg_ability", 3, 1 },
+		{ "Link_status", 2, 1 },
+		{ "Jabber_detect", 1, 1 },
+		{ "extended_capability", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_0", 0x3e308, 0 },
+	{ "MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_1", 0x3e30c, 0 },
+	{ "MAC_MTIP_PCS_1G_3_DEV_ABILITY", 0x3e310, 0 },
+		{ "ACK", 14, 1 },
+		{ "EEE_Clock_Stop_enable", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_3_PARTNER_ABILITY", 0x3e314, 0 },
+		{ "Copper_Link_Status", 15, 1 },
+		{ "ACK", 14, 1 },
+		{ "Copper_Duplex_Status", 12, 1 },
+		{ "Copper_Speed", 10, 2 },
+		{ "EEE_Capability", 9, 1 },
+		{ "EEE_Clock_Stop_Capability", 8, 1 },
+	{ "MAC_MTIP_PCS_1G_3_AN_EXPANSION", 0x3e318, 0 },
+		{ "Next_Page_Able", 2, 1 },
+		{ "Page_Receive", 1, 1 },
+	{ "MAC_MTIP_PCS_1G_3_NP_TX", 0x3e31c, 0 },
+	{ "MAC_MTIP_PCS_1G_3_LP_NP_RX", 0x3e320, 0 },
+		{ "NP", 15, 1 },
+		{ "Ack", 14, 1 },
+		{ "MP", 13, 1 },
+		{ "Ack2", 12, 1 },
+		{ "Toggle", 11, 1 },
+		{ "data", 0, 11 },
+	{ "MAC_MTIP_PCS_1G_3_EXTENDED_STATUS", 0x3e33c, 0 },
+	{ "MAC_MTIP_PCS_1G_3_SCRATCH", 0x3e340, 0 },
+	{ "MAC_MTIP_PCS_1G_3_REV", 0x3e344, 0 },
+	{ "MAC_MTIP_PCS_1G_3_LINK_TIMER_0", 0x3e348, 0 },
+	{ "MAC_MTIP_PCS_1G_3_LINK_TIMER_1", 0x3e34c, 0 },
+	{ "MAC_MTIP_PCS_1G_3_IF_MODE", 0x3e350, 0 },
+		{ "SGMII_DUPLEX", 4, 1 },
+		{ "SGMII_SPEED", 2, 2 },
+		{ "USE_SGMII_AN", 1, 1 },
+		{ "SGMII_ENA", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_3_DEC_ERR_CNT", 0x3e354, 0 },
+	{ "MAC_MTIP_PCS_1G_3_VENDOR_CONTROL", 0x3e358, 0 },
+		{ "SGPCS_ENA_ST", 15, 1 },
+		{ "CFG_CLOCK_RATE", 4, 4 },
+		{ "SGPCS_ENA_R", 0, 1 },
+	{ "MAC_MTIP_PCS_1G_3_SD_BIT_SLIP", 0x3e35c, 0 },
+	{ "MAC_DPLL_CTRL_0", 0x3f000, 0 },
+		{ "local_fault_ovrd", 18, 1 },
+		{ "local_fault_hold_en", 17, 1 },
+		{ "DPLL_Rst", 16, 1 },
+		{ "CNTOFFSET", 0, 16 },
+	{ "MAC_DPLL_CTRL_1", 0x3f004, 0 },
+	{ "MAC_DPLL_CTRL_2", 0x3f008, 0 },
+		{ "DIVFFB", 16, 16 },
+		{ "DIVFIN", 0, 16 },
+	{ "MAC_DPLL_CTRL_3", 0x3f00c, 0 },
+		{ "ISHIFT_HOLD", 28, 4 },
+		{ "ISHIFT", 24, 4 },
+		{ "INT_PRESET", 12, 12 },
+		{ "FMI", 4, 8 },
+		{ "DPLL_PROGRAM", 3, 1 },
+		{ "PRESET_EN", 2, 1 },
+		{ "ONTARGETOV", 1, 1 },
+		{ "FDONLY", 0, 1 },
+	{ "MAC_DPLL_CTRL_4", 0x3f010, 0 },
+		{ "FKI", 24, 5 },
+		{ "FRAC_PRESET", 0, 24 },
+	{ "MAC_DPLL_CTRL_5", 0x3f014, 0 },
+		{ "PH_STEP_CNT_HOLD", 24, 5 },
+		{ "CFG_RESET", 23, 1 },
+		{ "PH_STEP_CNT", 16, 5 },
+		{ "OTDLY", 0, 16 },
+	{ "MAC_DPLL_CTRL_6", 0x3f018, 0 },
+		{ "TARGETCNT", 16, 16 },
+		{ "PKP", 8, 5 },
+		{ "PMP", 0, 8 },
+	{ "MAC_DPLL_CTRL_7", 0x3f01c, 0 },
+	{ "MAC_DPLL_STATUS_0", 0x3f020, 0 },
+	{ "MAC_DPLL_STATUS_1", 0x3f024, 0 },
+	{ "MAC_DPLL_STATUS_2", 0x3f028, 0 },
+		{ "INT", 12, 12 },
+		{ "INT_PD_OUT", 0, 12 },
+	{ "MAC_FRAC_N_PLL_CTRL_0", 0x3f02c, 0 },
+		{ "FRAC_N_DSKEWCALCNT", 29, 3 },
+		{ "PLLEN", 28, 1 },
+		{ "BYPASS", 24, 4 },
+		{ "POSTDIV3A", 21, 3 },
+		{ "POSTDIV3B", 18, 3 },
+		{ "POSTDIV2A", 15, 3 },
+		{ "POSTDIV2B", 12, 3 },
+		{ "POSTDIV1A", 9, 3 },
+		{ "POSTDIV1B", 6, 3 },
+		{ "POSTDIV0A", 3, 3 },
+		{ "POSTDIV0B", 0, 3 },
+	{ "MAC_FRAC_N_PLL_CTRL_1", 0x3f030, 0 },
+		{ "FRAC_N_frac_n_fouten", 28, 4 },
+		{ "FRAC_N_DSKEWCALIN", 16, 12 },
+		{ "FRAC_N_REFDIV", 10, 6 },
+		{ "FRAC_N_DSMEN", 9, 1 },
+		{ "FRAC_N_PLLEN", 8, 1 },
+		{ "FRAC_N_DACEN", 7, 1 },
+		{ "FRAC_N_POSTDIV0PRE", 6, 1 },
+		{ "FRAC_N_DSKEWCALBYP", 5, 1 },
+		{ "FRAC_N_DSKEWFASTCAL", 4, 1 },
+		{ "FRAC_N_DSKEWCALEN", 3, 1 },
+		{ "FRAC_N_FREFCMLEN", 2, 1 },
+	{ "MAC_FRAC_N_PLL_STATUS_0", 0x3f034, 0 },
+		{ "DSKEWCALLOCK", 12, 1 },
+		{ "DSKEWCALOUT", 0, 12 },
+	{ "MAC_MTIP_PCS_STATUS_0", 0x3f100, 0 },
+		{ "xlgmii7_tx_tsu", 22, 2 },
+		{ "xlgmii6_tx_tsu", 20, 2 },
+		{ "xlgmii5_tx_tsu", 18, 2 },
+		{ "xlgmii4_tx_tsu", 16, 2 },
+		{ "xlgmii3_tx_tsu", 14, 2 },
+		{ "xlgmii2_tx_tsu", 12, 2 },
+		{ "xlgmii1_tx_tsu", 10, 2 },
+		{ "xlgmii0_tx_tsu", 8, 2 },
+		{ "cgmii3_tx_tsu", 6, 2 },
+		{ "cgmii2_tx_tsu", 4, 2 },
+		{ "cgmii1_tx_tsu", 2, 2 },
+		{ "cgmii0_tx_tsu", 0, 2 },
+	{ "MAC_MTIP_PCS_STATUS_1", 0x3f104, 0 },
+		{ "cdmii1_rx_tsu", 26, 2 },
+		{ "cdmii0_rx_tsu", 24, 2 },
+		{ "xlgmii7_rx_tsu", 22, 2 },
+		{ "xlgmii6_rx_tsu", 20, 2 },
+		{ "xlgmii5_rx_tsu", 18, 2 },
+		{ "xlgmii4_rx_tsu", 16, 2 },
+		{ "xlgmii3_rx_tsu", 14, 2 },
+		{ "xlgmii2_rx_tsu", 12, 2 },
+		{ "xlgmii1_rx_tsu", 10, 2 },
+		{ "xlgmii0_rx_tsu", 8, 2 },
+		{ "cgmii3_rx_tsu", 6, 2 },
+		{ "cgmii2_rx_tsu", 4, 2 },
+		{ "cgmii1_rx_tsu", 2, 2 },
+		{ "cgmii0_rx_tsu", 0, 2 },
+	{ "MAC_MTIP_PCS_STATUS_2", 0x3f108, 0 },
+	{ "MAC_MTIP_PCS_STATUS_3", 0x3f10c, 0 },
+	{ "MAC_MTIP_PCS_STATUS_4", 0x3f110, 0 },
+	{ "MAC_MTIP_PCS_STATUS_5", 0x3f114, 0 },
+	{ "MAC_MTIP_PCS_STATUS_6", 0x3f118, 0 },
+	{ "MAC_MTIP_PCS_STATUS_7", 0x3f11c, 0 },
+	{ "MAC_MTIP_MAC_10G_100G_STATUS_0", 0x3f120, 0 },
+		{ "tsv_xon_stb_2", 24, 8 },
+		{ "tsv_xoff_stb_2", 16, 8 },
+		{ "rsv_xon_stb_2", 8, 8 },
+		{ "rsv_xoff_stb_2", 0, 8 },
+	{ "MAC_MTIP_MAC_10G_100G_STATUS_1", 0x3f124, 0 },
+		{ "tsv_xon_stb_3", 24, 8 },
+		{ "tsv_xoff_stb_3", 16, 8 },
+		{ "rsv_xon_stb_3", 8, 8 },
+		{ "rsv_xoff_stb_3", 0, 8 },
+	{ "MAC_MTIP_MAC_10G_100G_STATUS_2", 0x3f128, 0 },
+		{ "tsv_xon_stb_4", 24, 8 },
+		{ "tsv_xoff_stb_4", 16, 8 },
+		{ "rsv_xon_stb_4", 8, 8 },
+		{ "rsv_xoff_stb_4", 0, 8 },
+	{ "MAC_MTIP_MAC_10G_100G_STATUS_3", 0x3f12c, 0 },
+		{ "tsv_xon_stb_5", 24, 8 },
+		{ "tsv_xoff_stb_5", 16, 8 },
+		{ "rsv_xon_stb_5", 8, 8 },
+		{ "rsv_xoff_stb_5", 0, 8 },
+	{ "MAC_MTIP_MAC_10G_100G_STATUS_4", 0x3f130, 0 },
+		{ "tx_sfd_o_5", 19, 1 },
+		{ "tx_sfd_o_4", 18, 1 },
+		{ "tx_sfd_o_3", 17, 1 },
+		{ "tx_sfd_o_2", 16, 1 },
+		{ "rx_sfd_o_5", 15, 1 },
+		{ "rx_sfd_o_4", 14, 1 },
+		{ "rx_sfd_o_3", 13, 1 },
+		{ "rx_sfd_o_2", 12, 1 },
+		{ "rx_sfd_shift_o_5", 11, 1 },
+		{ "rx_sfd_shift_o_4", 10, 1 },
+		{ "rx_sfd_shift_o_3", 9, 1 },
+		{ "rx_sfd_shift_o_2", 8, 1 },
+		{ "tx_sfd_shift_o_5", 7, 1 },
+		{ "tx_sfd_shift_o_4", 6, 1 },
+		{ "tx_sfd_shift_o_3", 5, 1 },
+		{ "tx_sfd_shift_o_2", 4, 1 },
+		{ "ts_sfd_ena_5", 3, 1 },
+		{ "ts_sfd_ena_4", 2, 1 },
+		{ "ts_sfd_ena_3", 1, 1 },
+		{ "ts_sfd_ena_2", 0, 1 },
+	{ "MAC_STS_CONFIG", 0x3f200, 0 },
+		{ "sts_ena", 30, 1 },
+		{ "n_pps_ena", 29, 1 },
+		{ "sts_reset", 28, 1 },
+		{ "debounce_cnt", 0, 28 },
+	{ "MAC_STS_COUNTER", 0x3f204, 0 },
+	{ "MAC_STS_COUNT_1", 0x3f208, 0 },
+	{ "MAC_STS_COUNT_2", 0x3f20c, 0 },
+	{ "MAC_STS_N_PPS_COUNT_HI", 0x3f210, 0 },
+	{ "MAC_STS_N_PPS_COUNT_LO", 0x3f214, 0 },
+	{ "MAC_STS_N_PPS_COUNTER", 0x3f218, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_crypto_0_regs[] = {
+	{ "TLS_TX_CH_CONFIG", 0x44000, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x44004, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x44008, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4400c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x44010, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x44014, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x44020, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x44024, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x44028, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x44030, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x44100, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x44104, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x44108, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4410c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x44110, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x44114, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x44120, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x44124, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x44128, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x44130, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x44200, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x44204, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x44208, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4420c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x44210, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x44214, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x44220, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x44224, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x44228, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x44230, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x44300, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x44304, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x44308, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4430c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x44310, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x44314, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x44320, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x44324, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x44328, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x44330, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x44400, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x44404, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x44408, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4440c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x44410, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x44414, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x44420, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x44424, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x44428, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x44430, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x44500, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x44504, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x44508, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4450c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x44510, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x44514, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x44520, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x44524, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x44528, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x44530, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_DBG_SELL_DATA", 0x44714, 0 },
+	{ "TLS_TX_DBG_SELH_DATA", 0x44718, 0 },
+	{ "TLS_TX_DBG_SEL_CTRL", 0x44730, 0 },
+	{ "TLS_TX_GLOBAL_CONFIG", 0x447c0, 0 },
+		{ "QUIC_EN", 2, 1 },
+		{ "IPSEC_IDX_UPD_EN", 1, 1 },
+		{ "IPSEC_IDX_CTL", 0, 1 },
+	{ "TLS_TX_CGEN", 0x447f0, 0 },
+	{ "TLS_TX_IND_ADDR", 0x447f8, 0 },
+	{ "TLS_TX_IND_DATA", 0x447fc, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_crypto_1_regs[] = {
+	{ "TLS_TX_CH_CONFIG", 0x45000, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x45004, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x45008, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4500c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x45010, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x45014, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x45020, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x45024, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x45028, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x45030, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x45100, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x45104, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x45108, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4510c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x45110, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x45114, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x45120, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x45124, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x45128, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x45130, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x45200, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x45204, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x45208, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4520c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x45210, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x45214, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x45220, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x45224, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x45228, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x45230, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x45300, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x45304, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x45308, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4530c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x45310, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x45314, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x45320, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x45324, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x45328, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x45330, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x45400, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x45404, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x45408, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4540c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x45410, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x45414, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x45420, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x45424, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x45428, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x45430, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_CH_CONFIG", 0x45500, 0 },
+		{ "SMALL_LEN_THRESH", 16, 16 },
+		{ "CIPH0_CTL_SEL", 12, 3 },
+		{ "CIPHN_CTL_SEL", 9, 3 },
+		{ "MAC_CTL_SEL", 6, 3 },
+		{ "CIPH0_XOR_SEL", 5, 1 },
+		{ "CIPHN_XOR_SEL", 4, 1 },
+		{ "MAC_XOR_SEL", 3, 1 },
+		{ "CIPH0_DP_SEL", 2, 1 },
+		{ "CIPHN_DP_SEL", 1, 1 },
+		{ "MAC_DP_SEL", 0, 1 },
+	{ "TLS_TX_CH_PERR_INJECT", 0x45504, 0 },
+		{ "MemSel", 1, 5 },
+		{ "InjectDataErr", 0, 1 },
+	{ "TLS_TX_CH_INT_ENABLE", 0x45508, 0 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_INT_CAUSE", 0x4550c, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_PERR_ENABLE", 0x45510, 0 },
+		{ "KEX_CERR", 4, 1 },
+		{ "KeyLenErr", 3, 1 },
+		{ "intf1_PERR", 2, 1 },
+		{ "intf0_PERR", 1, 1 },
+		{ "KEX_PERR", 0, 1 },
+	{ "TLS_TX_CH_DEBUG_FLAGS", 0x45514, 0 },
+	{ "TLS_TX_CH_HMACCTRL_CFG", 0x45520, 0 },
+		{ "HMAC_CFG6", 12, 6 },
+		{ "HMAC_CFG5", 6, 6 },
+		{ "HMAC_CFG4", 0, 6 },
+	{ "TLS_TX_CH_ERR_RSP_HDR", 0x45524, 0 },
+	{ "TLS_TX_CH_HANG_TIMEOUT", 0x45528, 0 },
+	{ "TLS_TX_CH_DBG_STEP_CTRL", 0x45530, 0 },
+		{ "DBG_STEP_CTRL", 1, 1 },
+		{ "DBG_STEP_EN", 0, 1 },
+	{ "TLS_TX_DBG_SELL_DATA", 0x45714, 0 },
+	{ "TLS_TX_DBG_SELH_DATA", 0x45718, 0 },
+	{ "TLS_TX_DBG_SEL_CTRL", 0x45730, 0 },
+	{ "TLS_TX_GLOBAL_CONFIG", 0x457c0, 0 },
+		{ "QUIC_EN", 2, 1 },
+		{ "IPSEC_IDX_UPD_EN", 1, 1 },
+		{ "IPSEC_IDX_CTL", 0, 1 },
+	{ "TLS_TX_CGEN", 0x457f0, 0 },
+	{ "TLS_TX_IND_ADDR", 0x457f8, 0 },
+	{ "TLS_TX_IND_DATA", 0x457fc, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_crypto_key_regs[] = {
+	{ "CRYPTO_KEY_CONFIG", 0x46000, 0 },
+		{ "EsnWin", 1, 3 },
+		{ "IngKey96", 0, 1 },
+	{ "CRYPTO_KEY_RST", 0x46004, 0 },
+		{ "Core1Rst", 1, 1 },
+		{ "Core0Rst", 0, 1 },
+	{ "CRYPTO_KEY_INT_ENABLE", 0x46008, 0 },
+		{ "MA_FIFO_PERR", 22, 1 },
+		{ "MA_RSP_PERR", 21, 1 },
+		{ "ING_CACHE_DATA_PERR", 19, 1 },
+		{ "ING_CACHE_TAG_PERR", 18, 1 },
+		{ "LKP_KEY_REQ_PERR", 17, 1 },
+		{ "LKP_CLIP_TCAM_PERR", 16, 1 },
+		{ "LKP_MAIN_TCAM_PERR", 15, 1 },
+		{ "EGR_KEY_REQ_PERR", 14, 1 },
+		{ "EGR_CACHE_DATA_PERR", 13, 1 },
+		{ "EGR_CACHE_TAG_PERR", 12, 1 },
+		{ "CIM_PERR", 11, 1 },
+		{ "MA_INV_RSP_TAG", 10, 1 },
+		{ "ING_KEY_RANGE_ERR", 9, 1 },
+		{ "ING_MFIFO_OVFL", 8, 1 },
+		{ "LKP_REQ_OVFL", 7, 1 },
+		{ "EOK_WAIT_ERR", 6, 1 },
+		{ "EGR_KEY_RANGE_ERR", 5, 1 },
+		{ "EGR_MFIFO_OVFL", 4, 1 },
+		{ "SEQ_WRAP_HP_OVFL", 3, 1 },
+		{ "SEQ_WRAP_LP_OVFL", 2, 1 },
+		{ "EGR_SEQ_WRAP_HP", 1, 1 },
+		{ "EGR_SEQ_WRAP_LP", 0, 1 },
+	{ "CRYPTO_KEY_INT_CAUSE", 0x4600c, 0 },
+		{ "MA_FIFO_PERR", 22, 1 },
+		{ "MA_RSP_PERR", 21, 1 },
+		{ "ING_CACHE_DATA_PERR", 19, 1 },
+		{ "ING_CACHE_TAG_PERR", 18, 1 },
+		{ "LKP_KEY_REQ_PERR", 17, 1 },
+		{ "LKP_CLIP_TCAM_PERR", 16, 1 },
+		{ "LKP_MAIN_TCAM_PERR", 15, 1 },
+		{ "EGR_KEY_REQ_PERR", 14, 1 },
+		{ "EGR_CACHE_DATA_PERR", 13, 1 },
+		{ "EGR_CACHE_TAG_PERR", 12, 1 },
+		{ "CIM_PERR", 11, 1 },
+		{ "MA_INV_RSP_TAG", 10, 1 },
+		{ "ING_KEY_RANGE_ERR", 9, 1 },
+		{ "ING_MFIFO_OVFL", 8, 1 },
+		{ "LKP_REQ_OVFL", 7, 1 },
+		{ "EOK_WAIT_ERR", 6, 1 },
+		{ "EGR_KEY_RANGE_ERR", 5, 1 },
+		{ "EGR_MFIFO_OVFL", 4, 1 },
+		{ "SEQ_WRAP_HP_OVFL", 3, 1 },
+		{ "SEQ_WRAP_LP_OVFL", 2, 1 },
+		{ "EGR_SEQ_WRAP_HP", 1, 1 },
+		{ "EGR_SEQ_WRAP_LP", 0, 1 },
+	{ "CRYPTO_KEY_PERR_ENABLE", 0x46010, 0 },
+		{ "MA_FIFO_PERR", 22, 1 },
+		{ "MA_RSP_PERR", 21, 1 },
+		{ "ING_CACHE_DATA_PERR", 19, 1 },
+		{ "ING_CACHE_TAG_PERR", 18, 1 },
+		{ "LKP_KEY_REQ_PERR", 17, 1 },
+		{ "LKP_CLIP_TCAM_PERR", 16, 1 },
+		{ "LKP_MAIN_TCAM_PERR", 15, 1 },
+		{ "EGR_KEY_REQ_PERR", 14, 1 },
+		{ "EGR_CACHE_DATA_PERR", 13, 1 },
+		{ "EGR_CACHE_TAG_PERR", 12, 1 },
+		{ "CIM_PERR", 11, 1 },
+		{ "MA_INV_RSP_TAG", 10, 1 },
+		{ "ING_KEY_RANGE_ERR", 9, 1 },
+		{ "ING_MFIFO_OVFL", 8, 1 },
+		{ "LKP_REQ_OVFL", 7, 1 },
+		{ "EOK_WAIT_ERR", 6, 1 },
+		{ "EGR_KEY_RANGE_ERR", 5, 1 },
+		{ "EGR_MFIFO_OVFL", 4, 1 },
+		{ "SEQ_WRAP_HP_OVFL", 3, 1 },
+		{ "SEQ_WRAP_LP_OVFL", 2, 1 },
+		{ "EGR_SEQ_WRAP_HP", 1, 1 },
+		{ "EGR_SEQ_WRAP_LP", 0, 1 },
+	{ "CRYPTO_KEY_EGR_SEQ_WRAP_LP_KEY_ID", 0x46018, 0 },
+		{ "KEY_VALID", 31, 1 },
+		{ "KEY_ID", 0, 31 },
+	{ "CRYPTO_KEY_EGR_SEQ_WRAP_HP_KEY_ID", 0x4601c, 0 },
+		{ "KEY_VALID", 31, 1 },
+		{ "KEY_ID", 0, 31 },
+	{ "CRYPTO_KEY_TCAM_DATA0", 0x46020, 0 },
+	{ "CRYPTO_KEY_TCAM_DATA1", 0x46024, 0 },
+	{ "CRYPTO_KEY_TCAM_DATA2", 0x46028, 0 },
+	{ "CRYPTO_KEY_TCAM_DATA3", 0x4602c, 0 },
+	{ "CRYPTO_KEY_TCAM_CTL", 0x46030, 0 },
+		{ "SrchMHit", 21, 1 },
+		{ "Busy", 20, 1 },
+		{ "SrchHit", 19, 1 },
+		{ "IPVersion", 18, 1 },
+		{ "BitSel", 17, 1 },
+		{ "TcamSel", 16, 1 },
+		{ "CmdType", 14, 2 },
+		{ "TcamIndex", 0, 14 },
+	{ "CRYPTO_KEY_TCAM_CONFIG", 0x46034, 0 },
+		{ "CLCAM_INIT_BUSY", 7, 1 },
+		{ "CLCAM_INIT", 6, 1 },
+		{ "MTCAM_INIT_BUSY", 5, 1 },
+		{ "MTCAM_INIT", 4, 1 },
+		{ "CLTCAMDEEPSLEEP_STAT", 3, 1 },
+		{ "TCAMDEEPSLEEP_STAT", 2, 1 },
+		{ "CLTCAMDEEPSLEEP", 1, 1 },
+		{ "TCAMDEEPSLEEP", 0, 1 },
+	{ "CRYPTO_KEY_TX_CMM_CONFIG", 0x46040, 0 },
+		{ "GlFl", 31, 1 },
+		{ "WrCntIdle", 16, 15 },
+		{ "RdThreshold", 8, 6 },
+		{ "WrThrLevel2", 7, 1 },
+		{ "WrThrLevel1", 6, 1 },
+		{ "WrThrThreshEn", 5, 1 },
+		{ "WrThrThresh", 0, 5 },
+	{ "CRYPTO_KEY_TX_TNL_BASE", 0x46044, 0 },
+	{ "CRYPTO_KEY_TX_TRN_BASE", 0x46048, 0 },
+	{ "CRYPTO_KEY_TX_MAX_KEYS", 0x4604c, 0 },
+		{ "TNL_MAX", 16, 16 },
+		{ "TRN_MAX", 0, 16 },
+	{ "CRYPTO_KEY_TX_SEQ_STAT", 0x46050, 0 },
+		{ "ESN", 24, 1 },
+		{ "SeqHi", 20, 4 },
+		{ "KeyID", 0, 20 },
+	{ "CRYPTO_KEY_RX_CMM_CONFIG", 0x46060, 0 },
+		{ "GlFl", 31, 1 },
+		{ "WrCntIdle", 16, 15 },
+		{ "RdThreshold", 8, 6 },
+		{ "WrThrLevel2", 7, 1 },
+		{ "WrThrLevel1", 6, 1 },
+		{ "WrThrThreshEn", 5, 1 },
+		{ "WrThrThresh", 0, 5 },
+	{ "CRYPTO_KEY_RX_BASE", 0x46064, 0 },
+	{ "CRYPTO_KEY_RX_MAX_KEYS", 0x46068, 0 },
+	{ "CRYPTO_KEY_CRYPTO_REVISION", 0x4606c, 0 },
+	{ "CRYPTO_KEY_RX_SEQ_STAT", 0x46070, 0 },
+		{ "ESN", 24, 1 },
+		{ "SeqHi", 20, 4 },
+		{ "KeyID", 0, 20 },
+	{ "CRYPTO_KEY_TCAM_BIST_CTRL", 0x46074, 0 },
+		{ "rst_cb", 31, 1 },
+		{ "cb_start", 0, 28 },
+	{ "CRYPTO_KEY_TCAM_BIST_CB_PASS", 0x46078, 0 },
+	{ "CRYPTO_KEY_TCAM_BIST_CB_BUSY", 0x4607c, 0 },
+	{ "CRYPTO_KEY_DBG_SEL_CTRL", 0x46080, 0 },
+		{ "SEL_OVR_EN", 16, 1 },
+		{ "SELH", 8, 8 },
+		{ "SELL", 0, 8 },
+	{ "CRYPTO_KEY_DBG_SELL_DATA", 0x46084, 0 },
+	{ "CRYPTO_KEY_DBG_SELH_DATA", 0x46088, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_arm_regs[] = {
+	{ "ARM_CPU_POR_RST", 0x47000, 0 },
+		{ "CpuPorRstn3", 3, 1 },
+		{ "CpuPorRstn2", 2, 1 },
+		{ "CpuPorRstn1", 1, 1 },
+		{ "CpuPorRstn0", 0, 1 },
+	{ "ARM_CPU_CORE_RST", 0x47004, 0 },
+		{ "CpuCoreRstn3", 3, 1 },
+		{ "CpuCoreRstn2", 2, 1 },
+		{ "CpuCoreRstn1", 1, 1 },
+		{ "CpuCoreRstn0", 0, 1 },
+	{ "ARM_CPU_WARM_RST_REQ", 0x47008, 0 },
+		{ "CpuWarmRstReq3", 3, 1 },
+		{ "CpuWarmRstReq2", 2, 1 },
+		{ "CpuWarmRstReq1", 1, 1 },
+		{ "CpuWarmRstReq0", 0, 1 },
+	{ "ARM_CPU_L2_RST", 0x4700c, 0 },
+	{ "ARM_CPU_L2_RST_DIS", 0x47010, 0 },
+	{ "ARM_CPU_PRESET_DBG", 0x47014, 0 },
+	{ "ARM_CPU_PERIPH_BASE", 0x47124, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR0", 0x47020, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR1", 0x47024, 0 },
+	{ "ARM_CPU_PMU_EVENT", 0x47028, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR0", 0x47030, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR1", 0x47034, 0 },
+	{ "ARM_CPU_PMU_EVENT", 0x47038, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR0", 0x47040, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR1", 0x47044, 0 },
+	{ "ARM_CPU_PMU_EVENT", 0x47048, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR0", 0x47050, 0 },
+	{ "ARM_CPU_RESET_VECTOR_BASE_ADDR1", 0x47054, 0 },
+	{ "ARM_CPU_PMU_EVENT", 0x47058, 0 },
+	{ "ARM_CPU_DBG_PWR_UP_REQ", 0x47060, 0 },
+		{ "CpuDbgPwrUpReq3", 3, 1 },
+		{ "CpuDbgPwrUpReq2", 2, 1 },
+		{ "CpuDbgPwrUpReq1", 1, 1 },
+		{ "CpuDbgPwrUpReq0", 0, 1 },
+	{ "ARM_CPU_STANDBY_WFE_WFI", 0x47064, 0 },
+		{ "CpuStandbyWfiL2", 8, 1 },
+		{ "CpuStandbyWfi3", 7, 1 },
+		{ "CpuStandbyWfi2", 6, 1 },
+		{ "CpuStandbyWfi1", 5, 1 },
+		{ "CpuStandbyWfi0", 4, 1 },
+		{ "CpuStandbyWfe3", 3, 1 },
+		{ "CpuStandbyWfe2", 2, 1 },
+		{ "CpuStandbyWfe1", 1, 1 },
+		{ "CpuStandbyWfe0", 0, 1 },
+	{ "ARM_CPU_SMPEN", 0x47068, 0 },
+		{ "CpuSmpEn3", 3, 1 },
+		{ "CpuSmpEn2", 2, 1 },
+		{ "CpuSmpEn1", 1, 1 },
+		{ "CpuSmpEn0", 0, 1 },
+	{ "ARM_CPU_QACTIVE", 0x4706c, 0 },
+		{ "CpuQactive3", 3, 1 },
+		{ "CpuQactive2", 2, 1 },
+		{ "CpuQactive1", 1, 1 },
+		{ "CpuQactive0", 0, 1 },
+	{ "ARM_CPU_QREQ", 0x47070, 0 },
+		{ "CpuL2FlushReq", 5, 1 },
+		{ "CpuL2QReqn", 4, 1 },
+		{ "CpuQReq3n", 3, 1 },
+		{ "CpuQReq2n", 2, 1 },
+		{ "CpuQReq1n", 1, 1 },
+		{ "CpuQReq0n", 0, 1 },
+	{ "ARM_CPU_QREQ_STATUS", 0x47074, 0 },
+		{ "CpuL2FlushDone", 10, 1 },
+		{ "CpuL2QDeny", 9, 1 },
+		{ "CpuL2QAcceptn", 8, 1 },
+		{ "CpuQDeny3", 7, 1 },
+		{ "CpuQDeny2", 6, 1 },
+		{ "CpuQDeny1", 5, 1 },
+		{ "CpuQDeny0", 4, 1 },
+		{ "CpuQAccept3n", 3, 1 },
+		{ "CpuQAccept2n", 2, 1 },
+		{ "CpuQAccept1n", 1, 1 },
+		{ "CpuQAccept0n", 0, 1 },
+	{ "ARM_CPU_DBG_EN", 0x47078, 0 },
+		{ "CpuDbgL1RstDisable", 28, 1 },
+		{ "CpuDbgRstReq3", 27, 1 },
+		{ "CpuDbgRstReq2", 26, 1 },
+		{ "CpuDbgRstReq1", 25, 1 },
+		{ "CpuDbgRstReq0", 24, 1 },
+		{ "CpuDbgPwrdUp3", 23, 1 },
+		{ "CpuDbgPwrdUp2", 22, 1 },
+		{ "CpuDbgPwrdUp1", 21, 1 },
+		{ "CpuDbgPwrdUp0", 20, 1 },
+		{ "CpuExtDbgReq3", 19, 1 },
+		{ "CpuExtDbgReq2", 18, 1 },
+		{ "CpuExtDbgReq1", 17, 1 },
+		{ "CpuExtDbgReq0", 16, 1 },
+		{ "CpuSpNidEn3", 15, 1 },
+		{ "CpuSpNidEn2", 14, 1 },
+		{ "CpuSpNidEn1", 13, 1 },
+		{ "CpuSpNidEn0", 12, 1 },
+		{ "CpuSpDbgEn3", 11, 1 },
+		{ "CpuSpDbgEn2", 10, 1 },
+		{ "CpuSpDbgEn1", 9, 1 },
+		{ "CpuSpDbgEn0", 8, 1 },
+		{ "CpuNidEn3", 7, 1 },
+		{ "CpuNidEn2", 6, 1 },
+		{ "CpuNidEn1", 5, 1 },
+		{ "CpuNidEn0", 4, 1 },
+		{ "CpuDbgEn3", 3, 1 },
+		{ "CpuDbgEn2", 2, 1 },
+		{ "CpuDbgEn1", 1, 1 },
+		{ "CpuDbgEn0", 0, 1 },
+	{ "ARM_CPU_DBG_ACK", 0x4707c, 0 },
+		{ "CpuDbgNoPwrDwn3", 11, 1 },
+		{ "CpuDbgNoPwrDwn2", 10, 1 },
+		{ "CpuDbgNoPwrDwn1", 9, 1 },
+		{ "CpuDbgNoPwrDwn0", 8, 1 },
+		{ "CpuDgnRstReq3", 7, 1 },
+		{ "CpuDgnRstReq2", 6, 1 },
+		{ "CpuDgnRstReq1", 5, 1 },
+		{ "CpuDgnRstReq0", 4, 1 },
+		{ "CpuDbgAck3", 3, 1 },
+		{ "CpuDbgAck2", 2, 1 },
+		{ "CpuDbgAck1", 1, 1 },
+		{ "CpuDbgAck0", 0, 1 },
+	{ "ARM_CPU_PMU_SNAPSHOT_REQ", 0x47080, 0 },
+		{ "CpuPmuSnapshotReq3", 3, 1 },
+		{ "CpuPmuSnapshotReq2", 2, 1 },
+		{ "CpuPmuSnapshotReq1", 1, 1 },
+		{ "CpuPmuSnapshotReq0", 0, 1 },
+	{ "ARM_CPU_PMU_SNAPSHOT_ACK", 0x47084, 0 },
+		{ "CpuPmuSnapshotAck3", 3, 1 },
+		{ "CpuPmuSnapshotAck2", 2, 1 },
+		{ "CpuPmuSnapshotAck1", 1, 1 },
+		{ "CpuPmuSnapshotAck0", 0, 1 },
+	{ "ARM_CPU_CFG_END_VINI_TE", 0x4708c, 0 },
+		{ "CpuSysBarDisable", 23, 1 },
+		{ "CpuBroadCacheMain", 22, 1 },
+		{ "CpuBroadOuter", 21, 1 },
+		{ "CpuBroadInner", 20, 1 },
+		{ "CpuCryptoDisable3", 19, 1 },
+		{ "CpuCryptoDisable2", 18, 1 },
+		{ "CpuCryptoDisable1", 17, 1 },
+		{ "CpuCryptoDisable0", 16, 1 },
+		{ "CpuAA64nAA323", 15, 1 },
+		{ "CpuAA64nAA322", 14, 1 },
+		{ "CpuAA64nAA321", 13, 1 },
+		{ "CpuAA64nAA320", 12, 1 },
+		{ "CpuCfgTe3", 11, 1 },
+		{ "CpuCfgTe2", 10, 1 },
+		{ "CpuCfgTe1", 9, 1 },
+		{ "CpuCfgTe0", 8, 1 },
+		{ "CpuViniHi3", 7, 1 },
+		{ "CpuViniHi2", 6, 1 },
+		{ "CpuViniHi1", 5, 1 },
+		{ "CpuViniHi0", 4, 1 },
+		{ "CpuCfgEnd3", 3, 1 },
+		{ "CpuCfgEnd2", 2, 1 },
+		{ "CpuCfgEnd1", 1, 1 },
+		{ "CpuCfgEnd0", 0, 1 },
+	{ "ARM_CPU_CP15_SDISABLE", 0x47090, 0 },
+		{ "CpuCP15SDisable3", 3, 1 },
+		{ "CpuCP15SDisable2", 2, 1 },
+		{ "CpuCP15SDisable1", 1, 1 },
+		{ "CpuCP15SDisable0", 0, 1 },
+	{ "ARM_CPU_CLUSTER_ID_AFF", 0x47094, 0 },
+		{ "CpuClusterIdAff2", 8, 8 },
+		{ "CpuClusterIdAff1", 0, 8 },
+	{ "ARM_CPU_CLK_CFG", 0x47098, 0 },
+		{ "CpuAcInactiveM", 1, 1 },
+		{ "CpuAclkEnM", 0, 1 },
+	{ "ARM_CPU_EVENT_I", 0x47100, 0 },
+	{ "ARM_CPU_EVENT_O", 0x47104, 0 },
+	{ "ARM_CPU_CLR_EXMON_REQ", 0x47108, 0 },
+	{ "ARM_CPU_CLR_EXMON_ACK", 0x4710c, 0 },
+	{ "ARM_UART_MSTR_RXD", 0x47110, 0 },
+	{ "ARM_UART_MSTR_RXC", 0x47114, 0 },
+	{ "ARM_UART_MSTR_TXD", 0x47118, 0 },
+	{ "ARM_UART_MSTR_TXC", 0x4711c, 0 },
+		{ "Int", 1, 1 },
+		{ "uart_mstc_txc", 0, 1 },
+	{ "ARM_UART_SLV_SEL", 0x47120, 0 },
+	{ "ARM_UART_CONFIG", 0x47130, 0 },
+		{ "StopBits", 25, 2 },
+		{ "Parity", 23, 2 },
+		{ "DataBits", 19, 4 },
+		{ "ClkDiv", 0, 18 },
+	{ "ARM_UART_STAT", 0x47134, 0 },
+		{ "Rsv1", 6, 26 },
+		{ "RxFrmErr", 5, 1 },
+		{ "RxParErr", 4, 1 },
+		{ "RxOvrn", 3, 1 },
+		{ "CTL_RxRdy", 2, 1 },
+		{ "TxOvrn", 1, 1 },
+		{ "CTL_TxRdy", 0, 1 },
+	{ "ARM_UART_TX_DATA", 0x47138, 0 },
+	{ "ARM_UART_RX_DATA", 0x4713c, 0 },
+	{ "ARM_UART_DBG0", 0x47140, 0 },
+	{ "ARM_UART_DBG1", 0x47144, 0 },
+	{ "ARM_UART_DBG2", 0x47148, 0 },
+	{ "ARM_UART_DBG3", 0x4714c, 0 },
+	{ "ARM_ARM_CPU_PC0", 0x47150, 0 },
+	{ "ARM_ARM_CPU_PC1", 0x47154, 0 },
+	{ "ARM_ARM_UART_INT_CAUSE", 0x47158, 0 },
+		{ "rx_fifo_not_empty", 1, 1 },
+		{ "tx_fifo_empty", 0, 1 },
+	{ "ARM_ARM_UART_INT_EN", 0x4715c, 0 },
+		{ "rx_fifo_int_not_empty", 1, 1 },
+		{ "tx_fifo_int_empty", 0, 1 },
+	{ "ARM_ARM_UART_GPIO_SEL", 0x47160, 0 },
+		{ "pc_sel", 1, 3 },
+		{ "uart_gpio_sel", 0, 1 },
+	{ "ARM_ARM_SCRATCH_PAD0", 0x47164, 0 },
+	{ "ARM_ARM_SCRATCH_PAD1", 0x47168, 0 },
+	{ "ARM_ARM_SCRATCH_PAD2", 0x4716c, 0 },
+	{ "ARM_DEBUG_INDEX", 0x47450, 0 },
+	{ "ARM_DEBUG_DATA_HIGH", 0x47454, 0 },
+	{ "ARM_DEBUG_DATA_LOW", 0x47458, 0 },
+	{ "ARM_PERR_INT_CAUSE0", 0x47170, 0 },
+		{ "inic_WrData_Fifo_perr", 31, 1 },
+		{ "inic_rData_Fifo_perr", 30, 1 },
+		{ "msi_mem_perr", 29, 1 },
+		{ "arm_db_sram_perr", 27, 2 },
+		{ "emmc_FifoParInt", 26, 1 },
+		{ "icb_ram_perr", 25, 1 },
+		{ "mess2axi4_wrfifo_perr", 24, 1 },
+		{ "rc_wFifo_outperr", 23, 1 },
+		{ "rc_sram_perr", 21, 2 },
+		{ "msi_fifo_par_err", 20, 1 },
+		{ "inic2ma_IntfPerr", 19, 1 },
+		{ "rdataFifo0_perr", 18, 1 },
+		{ "rdataFifo1_perr", 17, 1 },
+		{ "WrDataFifo0_perr", 16, 1 },
+		{ "WrDataFifo1_perr", 15, 1 },
+		{ "wr512dataFifo0_perr", 14, 1 },
+		{ "wr512dataFifo1_perr", 13, 1 },
+		{ "robuff_parerr3", 12, 1 },
+		{ "robuff_parerr2", 11, 1 },
+		{ "robuff_parerr1", 10, 1 },
+		{ "robuff_parerr0", 9, 1 },
+		{ "ma2axi_ReqDataParErr", 8, 1 },
+		{ "ma2axi_ReqCtlParErr", 7, 1 },
+		{ "ma_RspPerr", 6, 1 },
+		{ "pcie2ma_reqCtlParErr", 5, 1 },
+		{ "pcie2ma_reqDataParErr", 4, 1 },
+		{ "inic2ma_reqCtlParErr", 3, 1 },
+		{ "inic2ma_reqDataParErr", 2, 1 },
+		{ "ma_RspUE", 1, 1 },
+		{ "apb2pl_RspDataPerr", 0, 1 },
+	{ "ARM_PERR_INT_ENB0", 0x47174, 0 },
+		{ "inic_WrData_Fifo_perr", 31, 1 },
+		{ "inic_rData_Fifo_perr", 30, 1 },
+		{ "msi_mem_perr", 29, 1 },
+		{ "arm_db_sram_perr", 27, 2 },
+		{ "emmc_FifoParInt", 26, 1 },
+		{ "icb_ram_perr", 25, 1 },
+		{ "mess2axi4_wrfifo_perr", 24, 1 },
+		{ "rc_wFifo_outperr", 23, 1 },
+		{ "rc_sram_perr", 21, 2 },
+		{ "msi_fifo_par_err", 20, 1 },
+		{ "inic2ma_IntfPerr", 19, 1 },
+		{ "rdataFifo0_perr", 18, 1 },
+		{ "rdataFifo1_perr", 17, 1 },
+		{ "WrDataFifo0_perr", 16, 1 },
+		{ "WrDataFifo1_perr", 15, 1 },
+		{ "wr512dataFifo0_perr", 14, 1 },
+		{ "wr512dataFifo1_perr", 13, 1 },
+		{ "robuff_parerr3", 12, 1 },
+		{ "robuff_parerr2", 11, 1 },
+		{ "robuff_parerr1", 10, 1 },
+		{ "robuff_parerr0", 9, 1 },
+		{ "ma2axi_ReqDataParErr", 8, 1 },
+		{ "ma2axi_ReqCtlParErr", 7, 1 },
+		{ "ma_RspPerr", 6, 1 },
+		{ "pcie2ma_reqCtlParErr", 5, 1 },
+		{ "pcie2ma_reqDataParErr", 4, 1 },
+		{ "inic2ma_reqCtlParErr", 3, 1 },
+		{ "inic2ma_reqDataParErr", 2, 1 },
+		{ "ma_RspUE", 1, 1 },
+		{ "apb2pl_RspDataPerr", 0, 1 },
+	{ "ARM_PERR_ENABLE0", 0x4720c, 0 },
+		{ "inic_WrData_Fifo_perr", 31, 1 },
+		{ "inic_rData_Fifo_perr", 30, 1 },
+		{ "msi_mem_perr", 29, 1 },
+		{ "arm_db_sram_perr", 27, 2 },
+		{ "emmc_FifoParInt", 26, 1 },
+		{ "icb_ram_perr", 25, 1 },
+		{ "mess2axi4_wrfifo_perr", 24, 1 },
+		{ "rc_wFifo_outperr", 23, 1 },
+		{ "rc_sram_perr", 21, 2 },
+		{ "msi_fifo_par_err", 20, 1 },
+		{ "inic2ma_IntfPerr", 19, 1 },
+		{ "rdataFifo0_perr", 18, 1 },
+		{ "rdataFifo1_perr", 17, 1 },
+		{ "WrDataFifo0_perr", 16, 1 },
+		{ "WrDataFifo1_perr", 15, 1 },
+		{ "wr512dataFifo0_perr", 14, 1 },
+		{ "wr512dataFifo1_perr", 13, 1 },
+		{ "robuff_parerr3", 12, 1 },
+		{ "robuff_parerr2", 11, 1 },
+		{ "robuff_parerr1", 10, 1 },
+		{ "robuff_parerr0", 9, 1 },
+		{ "ma2axi_ReqDataParErr", 8, 1 },
+		{ "ma2axi_ReqCtlParErr", 7, 1 },
+		{ "ma_RspPerr", 6, 1 },
+		{ "pcie2ma_reqCtlParErr", 5, 1 },
+		{ "pcie2ma_reqDataParErr", 4, 1 },
+		{ "inic2ma_reqCtlParErr", 3, 1 },
+		{ "inic2ma_reqDataParErr", 2, 1 },
+		{ "ma_RspUE", 1, 1 },
+		{ "apb2pl_RspDataPerr", 0, 1 },
+	{ "ARM_PERR_INT_CAUSE1", 0x47430, 0 },
+		{ "arwfifo0_perr", 31, 1 },
+		{ "arwfifo1_perr", 30, 1 },
+		{ "arwidfifo0_perr", 29, 1 },
+		{ "arwidfifo1_perr", 28, 1 },
+		{ "aridfifo0_perr", 27, 1 },
+		{ "aridfifo1_perr", 26, 1 },
+		{ "rrspaddr_fifo0_perr", 25, 1 },
+		{ "rrspaddr_fifo1_perr", 24, 1 },
+		{ "wrstrb_fifo0_perr", 23, 1 },
+		{ "wrstrb_fifo1_perr", 22, 1 },
+		{ "ma2axi_rspDataParErr", 21, 1 },
+		{ "ma2axi_data_par_err", 20, 1 },
+		{ "ma2axi_wr_ord_fifo_parerr", 19, 1 },
+		{ "nvme_db_emu_tracker_fifo_perr", 18, 1 },
+		{ "nvme_db_emu_queue_aw_addr_fifo_perr", 17, 1 },
+		{ "nvme_db_emu_interrupt_offset_fifo_perr", 16, 1 },
+		{ "nvme_db_emu_Id_fifo0_perr", 15, 1 },
+		{ "nvme_db_emu_Id_fifo1_perr", 14, 1 },
+		{ "rc_arwFifo_perr", 13, 1 },
+		{ "rc_aridburstaddrFifo_perr", 12, 1 },
+		{ "rc_cfg_fifo_perr", 11, 1 },
+		{ "rc_rspFifo_perr", 10, 1 },
+		{ "inic_arIDFifo_perr", 9, 1 },
+		{ "inic_arwFifo_perr", 8, 1 },
+		{ "axi2ma_128_rd_addr_size_fifo_perr", 7, 1 },
+		{ "axi2rc_128_rd_addr_size_fifo_perr", 6, 1 },
+		{ "arm_ma_512b_rd_addr_size_fifo0_perr", 5, 1 },
+		{ "arm_ma_512b_rd_addr_size_fifo1_perr", 4, 1 },
+		{ "arm_ma_512b_arb_fifo_perr", 3, 1 },
+		{ "pcie_inic_ma_arb_fifo_perr", 2, 1 },
+		{ "pcie_inic_arb_rspPerr", 1, 1 },
+		{ "ite_cache_perr", 0, 1 },
+	{ "ARM_PERR_INT_ENB1", 0x47434, 0 },
+		{ "arwfifo0_perr", 31, 1 },
+		{ "arwfifo1_perr", 30, 1 },
+		{ "arwidfifo0_perr", 29, 1 },
+		{ "arwidfifo1_perr", 28, 1 },
+		{ "aridfifo0_perr", 27, 1 },
+		{ "aridfifo1_perr", 26, 1 },
+		{ "rrspaddr_fifo0_perr", 25, 1 },
+		{ "rrspaddr_fifo1_perr", 24, 1 },
+		{ "wrstrb_fifo0_perr", 23, 1 },
+		{ "wrstrb_fifo1_perr", 22, 1 },
+		{ "ma2axi_rspDataParErr", 21, 1 },
+		{ "ma2axi_data_par_err", 20, 1 },
+		{ "ma2axi_wr_ord_fifo_parerr", 19, 1 },
+		{ "nvme_db_emu_tracker_fifo_perr", 18, 1 },
+		{ "nvme_db_emu_queue_aw_addr_fifo_perr", 17, 1 },
+		{ "nvme_db_emu_interrupt_offset_fifo_perr", 16, 1 },
+		{ "nvme_db_emu_Id_fifo0_perr", 15, 1 },
+		{ "nvme_db_emu_Id_fifo1_perr", 14, 1 },
+		{ "rc_arwFifo_perr", 13, 1 },
+		{ "rc_aridburstaddrFifo_perr", 12, 1 },
+		{ "rc_cfg_fifo_perr", 11, 1 },
+		{ "rc_rspFifo_perr", 10, 1 },
+		{ "inic_arIDFifo_perr", 9, 1 },
+		{ "inic_arwFifo_perr", 8, 1 },
+		{ "axi2ma_128_rd_addr_size_fifo_perr", 7, 1 },
+		{ "axi2rc_128_rd_addr_size_fifo_perr", 6, 1 },
+		{ "arm_ma_512b_rd_addr_size_fifo0_perr", 5, 1 },
+		{ "arm_ma_512b_rd_addr_size_fifo1_perr", 4, 1 },
+		{ "arm_ma_512b_arb_fifo_perr", 3, 1 },
+		{ "pcie_inic_ma_arb_fifo_perr", 2, 1 },
+		{ "pcie_inic_arb_rspPerr", 1, 1 },
+		{ "ite_cache_perr", 0, 1 },
+	{ "ARM_PERR_ENABLE1", 0x47438, 0 },
+		{ "arwfifo0_perr", 31, 1 },
+		{ "arwfifo1_perr", 30, 1 },
+		{ "arwidfifo0_perr", 29, 1 },
+		{ "arwidfifo1_perr", 28, 1 },
+		{ "aridfifo0_perr", 27, 1 },
+		{ "aridfifo1_perr", 26, 1 },
+		{ "rrspaddr_fifo0_perr", 25, 1 },
+		{ "rrspaddr_fifo1_perr", 24, 1 },
+		{ "wrstrb_fifo0_perr", 23, 1 },
+		{ "wrstrb_fifo1_perr", 22, 1 },
+		{ "ma2axi_rspDataParErr", 21, 1 },
+		{ "ma2axi_data_par_err", 20, 1 },
+		{ "ma2axi_wr_ord_fifo_parerr", 19, 1 },
+		{ "nvme_db_emu_tracker_fifo_perr", 18, 1 },
+		{ "nvme_db_emu_queue_aw_addr_fifo_perr", 17, 1 },
+		{ "nvme_db_emu_interrupt_offset_fifo_perr", 16, 1 },
+		{ "nvme_db_emu_Id_fifo0_perr", 15, 1 },
+		{ "nvme_db_emu_Id_fifo1_perr", 14, 1 },
+		{ "rc_arwFifo_perr", 13, 1 },
+		{ "rc_aridburstaddrFifo_perr", 12, 1 },
+		{ "rc_cfg_fifo_perr", 11, 1 },
+		{ "rc_rspFifo_perr", 10, 1 },
+		{ "inic_arIDFifo_perr", 9, 1 },
+		{ "inic_arwFifo_perr", 8, 1 },
+		{ "axi2ma_128_rd_addr_size_fifo_perr", 7, 1 },
+		{ "axi2rc_128_rd_addr_size_fifo_perr", 6, 1 },
+		{ "arm_ma_512b_rd_addr_size_fifo0_perr", 5, 1 },
+		{ "arm_ma_512b_rd_addr_size_fifo1_perr", 4, 1 },
+		{ "arm_ma_512b_arb_fifo_perr", 3, 1 },
+		{ "pcie_inic_ma_arb_fifo_perr", 2, 1 },
+		{ "pcie_inic_arb_rspPerr", 1, 1 },
+		{ "ite_cache_perr", 0, 1 },
+	{ "ARM_PERR_INT_CAUSE2", 0x4717c, 0 },
+		{ "inic_wstrb_fifo_perr", 31, 1 },
+		{ "inic_bId_fifo_perr", 30, 1 },
+		{ "cc_sram_pka_perr", 29, 1 },
+		{ "cc_sram_sec_perr", 28, 1 },
+		{ "mess2axi4_ParErr", 27, 1 },
+		{ "cci2inic_intf_ParErr", 26, 1 },
+	{ "ARM_PERR_INT_ENB2", 0x47128, 0 },
+		{ "inic_wstrb_fifo_perr", 31, 1 },
+		{ "inic_bId_fifo_perr", 30, 1 },
+		{ "cc_sram_pka_perr", 29, 1 },
+		{ "cc_sram_sec_perr", 28, 1 },
+		{ "mess2axi4_ParErr", 27, 1 },
+		{ "cci2inic_intf_ParErr", 26, 1 },
+	{ "ARM_PERR_ENABLE2", 0x4712c, 0 },
+		{ "inic_wstrb_fifo_perr", 31, 1 },
+		{ "inic_bId_fifo_perr", 30, 1 },
+		{ "cc_sram_pka_perr", 29, 1 },
+		{ "cc_sram_sec_perr", 28, 1 },
+		{ "mess2axi4_ParErr", 27, 1 },
+		{ "cci2inic_intf_ParErr", 26, 1 },
+	{ "ARM_CERR_INT_CAUSE0", 0x471dc, 0 },
+		{ "WrData_Fifo0_cerr", 31, 1 },
+		{ "WrData_Fifo1_cerr", 30, 1 },
+		{ "wr512dataFifo0_cerr", 29, 1 },
+		{ "wr512dataFifo1_cerr", 28, 1 },
+		{ "rdataFifo0_cerr", 27, 1 },
+		{ "rdataFifo1_cerr", 26, 1 },
+		{ "robuff_corerr0", 25, 1 },
+		{ "robuff_corerr1", 24, 1 },
+		{ "robuff_corerr2", 23, 1 },
+		{ "robuff_corerr3", 22, 1 },
+		{ "ma2axi_rspDataCorErr", 21, 1 },
+		{ "rc_sram_cerr", 19, 2 },
+		{ "rc_wFifo_outcerr", 18, 1 },
+		{ "rc_rspFifo_cerr", 17, 1 },
+		{ "msi_mem_cerr", 16, 1 },
+		{ "inic_WrData_Fifo_cerr", 15, 1 },
+		{ "inic_rdataFifo_cerr", 14, 1 },
+		{ "arm_db_sram_cerr", 12, 2 },
+		{ "icb_ram_cerr", 11, 1 },
+		{ "cc_sram_pka_cerr", 10, 1 },
+		{ "cc_sram_sec_cerr", 9, 1 },
+	{ "ARM_CERR_INT_ENB0", 0x471e8, 0 },
+		{ "WrData_Fifo0_cerr", 31, 1 },
+		{ "WrData_Fifo1_cerr", 30, 1 },
+		{ "wr512dataFifo0_cerr", 29, 1 },
+		{ "wr512dataFifo1_cerr", 28, 1 },
+		{ "rdataFifo0_cerr", 27, 1 },
+		{ "rdataFifo1_cerr", 26, 1 },
+		{ "robuff_corerr0", 25, 1 },
+		{ "robuff_corerr1", 24, 1 },
+		{ "robuff_corerr2", 23, 1 },
+		{ "robuff_corerr3", 22, 1 },
+		{ "ma2axi_rspDataCorErr", 21, 1 },
+		{ "rc_sram_cerr", 19, 2 },
+		{ "rc_wFifo_outcerr", 18, 1 },
+		{ "rc_rspFifo_cerr", 17, 1 },
+		{ "msi_mem_cerr", 16, 1 },
+		{ "inic_WrData_Fifo_cerr", 15, 1 },
+		{ "inic_rdataFifo_cerr", 14, 1 },
+		{ "arm_db_sram_cerr", 12, 2 },
+		{ "icb_ram_cerr", 11, 1 },
+		{ "cc_sram_pka_cerr", 10, 1 },
+		{ "cc_sram_sec_cerr", 9, 1 },
+	{ "ARM_ERR_INT_CAUSE0", 0x47444, 0 },
+		{ "strb0_error", 31, 1 },
+		{ "strb1_error", 30, 1 },
+		{ "pcie_inic_ma_arb_inv_rsp_tag", 29, 1 },
+		{ "error0_nocmd_data", 28, 1 },
+		{ "error1_nocmd_data", 27, 1 },
+		{ "inic_strb_error", 26, 1 },
+	{ "ARM_ERR_INT_ENB0", 0x47448, 0 },
+		{ "strb0_error", 31, 1 },
+		{ "strb1_error", 30, 1 },
+		{ "pcie_inic_ma_arb_inv_rsp_tag", 29, 1 },
+		{ "error0_nocmd_data", 28, 1 },
+		{ "error1_nocmd_data", 27, 1 },
+		{ "inic_strb_error", 26, 1 },
+	{ "ARM_PERIPHERAL_INT_CAUSE", 0x4718c, 0 },
+		{ "TIMER_INT", 5, 1 },
+		{ "NVME_INT", 4, 1 },
+		{ "EMMC_WAKEUP_INT", 3, 1 },
+		{ "EMMC_INT", 2, 1 },
+		{ "USB_MC_INT", 1, 1 },
+		{ "USB_DMA_INT", 0, 1 },
+	{ "ARM_PERIPHERAL_INT_ENB", 0x471e4, 0 },
+		{ "TIMER_INT", 5, 1 },
+		{ "NVME_INT", 4, 1 },
+		{ "EMMC_WAKEUP_INT", 3, 1 },
+		{ "EMMC_INT", 2, 1 },
+		{ "USB_MC_INT", 1, 1 },
+		{ "USB_DMA_INT", 0, 1 },
+	{ "ARM_SCRATCH_PAD3", 0x47178, 0 },
+		{ "ECO_43187", 31, 1 },
+		{ "TIMER_SEL", 28, 3 },
+		{ "TIMER", 4, 24 },
+		{ "INT", 0, 2 },
+	{ "ARM_MA2AXI_AW_ATTR", 0x47180, 0 },
+		{ "awLockR1", 29, 1 },
+		{ "awCacheR1", 25, 4 },
+		{ "awProtR1", 21, 4 },
+		{ "awSnoopR1", 18, 3 },
+		{ "awDomainR1", 16, 2 },
+		{ "awLockR0", 13, 1 },
+		{ "awCacheR0", 9, 4 },
+		{ "awProtR0", 5, 4 },
+		{ "awSnoopR0", 2, 3 },
+		{ "awDomainR0", 0, 2 },
+	{ "ARM_MA2AXI_AR_ATTR", 0x47184, 0 },
+		{ "arLockR1", 29, 1 },
+		{ "arCacheR1", 25, 4 },
+		{ "arProtR1", 21, 4 },
+		{ "arSnoopR1", 18, 3 },
+		{ "arDomainR1", 16, 2 },
+		{ "arLockR0", 13, 1 },
+		{ "arCacheR0", 9, 4 },
+		{ "arProtR0", 5, 4 },
+		{ "arSnoopR0", 2, 3 },
+		{ "arDomainR0", 0, 2 },
+	{ "ARM_MA2AXI_SNOOP_RGN", 0x47188, 0 },
+		{ "snoop_end", 16, 16 },
+		{ "snoop_start", 0, 16 },
+	{ "ARM_SCRATCH_PAD4", 0x47190, 0 },
+		{ "pad4", 15, 17 },
+		{ "arm_db_cnt", 0, 15 },
+	{ "ARM_SCRATCH_PAD5", 0x47194, 0 },
+	{ "ARM_SCRATCH_PAD6", 0x47198, 0 },
+	{ "ARM_SCRATCH_PAD7", 0x4719c, 0 },
+	{ "ARM_CPU_DBG_ROM_ADDR0", 0x47200, 0 },
+	{ "ARM_CPU_DBG_ROM_ADDR1", 0x47204, 0 },
+	{ "ARM_CPU_DBG_ROM_ADDR_VALID", 0x47208, 0 },
+	{ "ARM_CPU_DFT_CFG", 0x47220, 0 },
+		{ "CpuMbistReq", 11, 1 },
+		{ "CpuMbistRstn", 10, 1 },
+		{ "CpuDftDftSe", 9, 1 },
+		{ "CpuDftRstDisable", 8, 1 },
+		{ "CpuDftRamDisable", 7, 1 },
+		{ "CpuDftMcpDisable", 6, 1 },
+		{ "CpuDftL2ClkDisable", 5, 1 },
+		{ "CpuDftClkDisable3", 4, 1 },
+		{ "CpuDftClkDisable2", 3, 1 },
+		{ "CpuDftClkDisable1", 2, 1 },
+		{ "CpuDftClkDisable0", 1, 1 },
+		{ "CpuDftClkBypass", 0, 1 },
+	{ "ARM_ADB_PWR_DWN_REQ_N", 0x47230, 0 },
+	{ "ARM_CCI_CFG0", 0x47280, 0 },
+		{ "CciBroadcastcachemaint", 28, 3 },
+		{ "CciStripingGranule", 25, 3 },
+		{ "CciPeriphbase", 0, 25 },
+	{ "ARM_CCI_CFG1", 0x47284, 0 },
+		{ "CciDftRstDisable", 18, 1 },
+		{ "CciSpNiden", 17, 1 },
+		{ "CciNiden", 16, 1 },
+		{ "CciAcchannelN", 11, 5 },
+		{ "CciQosOverride", 6, 5 },
+		{ "CciBufferableOverride", 3, 3 },
+		{ "CciBarrierTerminate", 0, 3 },
+	{ "ARM_CCI_CFG2", 0x47288, 0 },
+		{ "CciAddrmap15", 30, 2 },
+		{ "CciAddrmap14", 28, 2 },
+		{ "CciAddrmap13", 26, 2 },
+		{ "CciAddrmap12", 24, 2 },
+		{ "CciAddrmap11", 22, 2 },
+		{ "CciAddrmap10", 20, 2 },
+		{ "CciAddrmap9", 18, 2 },
+		{ "CciAddrmap8", 16, 2 },
+		{ "CciAddrmap7", 14, 2 },
+		{ "CciAddrmap6", 12, 2 },
+		{ "CciAddrmap5", 10, 2 },
+		{ "CciAddrmap4", 8, 2 },
+		{ "CciAddrmap3", 6, 2 },
+		{ "CciAddrmap2", 4, 2 },
+		{ "CciAddrmap1", 2, 2 },
+		{ "CciAddrmap0", 0, 2 },
+	{ "ARM_CCI_STATUS", 0x4728c, 0 },
+		{ "CciCActive", 6, 1 },
+		{ "CciCsysAck", 5, 1 },
+		{ "CciNEvntCntOverflow", 0, 5 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_CFG", 0x47290, 0 },
+		{ "CciVWreadyvn3M", 20, 1 },
+		{ "CciVAwreadyvn3M", 19, 1 },
+		{ "CciVArreadyvn3M", 18, 1 },
+		{ "CciVWreadyvn2M", 17, 1 },
+		{ "CciVAwreadyvn2M", 16, 1 },
+		{ "CciVArreadyvn2M", 15, 1 },
+		{ "CciVWreadyvn1M", 14, 1 },
+		{ "CciVAwreadyvn1M", 13, 1 },
+		{ "CciVArreadyvn1M", 12, 1 },
+		{ "CciVWreadyvn0M", 11, 1 },
+		{ "CciVAwreadyvn0M", 10, 1 },
+		{ "CciVArreadyvn0M", 9, 1 },
+		{ "CciQvnPreallocwM", 5, 4 },
+		{ "CciQvnPreallocrM", 1, 4 },
+		{ "CciQvnenableM", 0, 1 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_STATUS", 0x47294, 0 },
+		{ "CciVWValidN3M", 31, 1 },
+		{ "CciVAwValidN3M", 30, 1 },
+		{ "CciVAwQosN3M", 29, 1 },
+		{ "CciVArValidN3M", 28, 1 },
+		{ "CciVArQosN3M", 24, 4 },
+		{ "CciVWValidN2M", 23, 1 },
+		{ "CciVAwValidN2M", 22, 1 },
+		{ "CciVAwQosN2M", 21, 1 },
+		{ "CciVArValidN2M", 20, 1 },
+		{ "CciVArQosN2M", 16, 4 },
+		{ "CciVWValidN1M", 15, 1 },
+		{ "CciVAwValidN1M", 14, 1 },
+		{ "CciVAwQosN1M", 13, 1 },
+		{ "CciVArValidN1M", 12, 1 },
+		{ "CciVArQosN1M", 8, 4 },
+		{ "CciVWValidN0M", 7, 1 },
+		{ "CciVAwValidN0M", 6, 1 },
+		{ "CciVAwQosN0M", 5, 1 },
+		{ "CciVArValidN0M", 4, 1 },
+		{ "CciVArQosN0M", 0, 4 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_CFG", 0x47298, 0 },
+		{ "CciVWreadyvn3M", 20, 1 },
+		{ "CciVAwreadyvn3M", 19, 1 },
+		{ "CciVArreadyvn3M", 18, 1 },
+		{ "CciVWreadyvn2M", 17, 1 },
+		{ "CciVAwreadyvn2M", 16, 1 },
+		{ "CciVArreadyvn2M", 15, 1 },
+		{ "CciVWreadyvn1M", 14, 1 },
+		{ "CciVAwreadyvn1M", 13, 1 },
+		{ "CciVArreadyvn1M", 12, 1 },
+		{ "CciVWreadyvn0M", 11, 1 },
+		{ "CciVAwreadyvn0M", 10, 1 },
+		{ "CciVArreadyvn0M", 9, 1 },
+		{ "CciQvnPreallocwM", 5, 4 },
+		{ "CciQvnPreallocrM", 1, 4 },
+		{ "CciQvnenableM", 0, 1 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_STATUS", 0x4729c, 0 },
+		{ "CciVWValidN3M", 31, 1 },
+		{ "CciVAwValidN3M", 30, 1 },
+		{ "CciVAwQosN3M", 29, 1 },
+		{ "CciVArValidN3M", 28, 1 },
+		{ "CciVArQosN3M", 24, 4 },
+		{ "CciVWValidN2M", 23, 1 },
+		{ "CciVAwValidN2M", 22, 1 },
+		{ "CciVAwQosN2M", 21, 1 },
+		{ "CciVArValidN2M", 20, 1 },
+		{ "CciVArQosN2M", 16, 4 },
+		{ "CciVWValidN1M", 15, 1 },
+		{ "CciVAwValidN1M", 14, 1 },
+		{ "CciVAwQosN1M", 13, 1 },
+		{ "CciVArValidN1M", 12, 1 },
+		{ "CciVArQosN1M", 8, 4 },
+		{ "CciVWValidN0M", 7, 1 },
+		{ "CciVAwValidN0M", 6, 1 },
+		{ "CciVAwQosN0M", 5, 1 },
+		{ "CciVArValidN0M", 4, 1 },
+		{ "CciVArQosN0M", 0, 4 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_CFG", 0x472a0, 0 },
+		{ "CciVWreadyvn3M", 20, 1 },
+		{ "CciVAwreadyvn3M", 19, 1 },
+		{ "CciVArreadyvn3M", 18, 1 },
+		{ "CciVWreadyvn2M", 17, 1 },
+		{ "CciVAwreadyvn2M", 16, 1 },
+		{ "CciVArreadyvn2M", 15, 1 },
+		{ "CciVWreadyvn1M", 14, 1 },
+		{ "CciVAwreadyvn1M", 13, 1 },
+		{ "CciVArreadyvn1M", 12, 1 },
+		{ "CciVWreadyvn0M", 11, 1 },
+		{ "CciVAwreadyvn0M", 10, 1 },
+		{ "CciVArreadyvn0M", 9, 1 },
+		{ "CciQvnPreallocwM", 5, 4 },
+		{ "CciQvnPreallocrM", 1, 4 },
+		{ "CciQvnenableM", 0, 1 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_STATUS", 0x472a4, 0 },
+		{ "CciVWValidN3M", 31, 1 },
+		{ "CciVAwValidN3M", 30, 1 },
+		{ "CciVAwQosN3M", 29, 1 },
+		{ "CciVArValidN3M", 28, 1 },
+		{ "CciVArQosN3M", 24, 4 },
+		{ "CciVWValidN2M", 23, 1 },
+		{ "CciVAwValidN2M", 22, 1 },
+		{ "CciVAwQosN2M", 21, 1 },
+		{ "CciVArValidN2M", 20, 1 },
+		{ "CciVArQosN2M", 16, 4 },
+		{ "CciVWValidN1M", 15, 1 },
+		{ "CciVAwValidN1M", 14, 1 },
+		{ "CciVAwQosN1M", 13, 1 },
+		{ "CciVArValidN1M", 12, 1 },
+		{ "CciVArQosN1M", 8, 4 },
+		{ "CciVWValidN0M", 7, 1 },
+		{ "CciVAwValidN0M", 6, 1 },
+		{ "CciVAwQosN0M", 5, 1 },
+		{ "CciVArValidN0M", 4, 1 },
+		{ "CciVArQosN0M", 0, 4 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_CFG", 0x472a8, 0 },
+		{ "CciVWreadyvn3M", 20, 1 },
+		{ "CciVAwreadyvn3M", 19, 1 },
+		{ "CciVArreadyvn3M", 18, 1 },
+		{ "CciVWreadyvn2M", 17, 1 },
+		{ "CciVAwreadyvn2M", 16, 1 },
+		{ "CciVArreadyvn2M", 15, 1 },
+		{ "CciVWreadyvn1M", 14, 1 },
+		{ "CciVAwreadyvn1M", 13, 1 },
+		{ "CciVArreadyvn1M", 12, 1 },
+		{ "CciVWreadyvn0M", 11, 1 },
+		{ "CciVAwreadyvn0M", 10, 1 },
+		{ "CciVArreadyvn0M", 9, 1 },
+		{ "CciQvnPreallocwM", 5, 4 },
+		{ "CciQvnPreallocrM", 1, 4 },
+		{ "CciQvnenableM", 0, 1 },
+	{ "ARM_CCIM_CCI_QVN_MASTER_STATUS", 0x472ac, 0 },
+		{ "CciVWValidN3M", 31, 1 },
+		{ "CciVAwValidN3M", 30, 1 },
+		{ "CciVAwQosN3M", 29, 1 },
+		{ "CciVArValidN3M", 28, 1 },
+		{ "CciVArQosN3M", 24, 4 },
+		{ "CciVWValidN2M", 23, 1 },
+		{ "CciVAwValidN2M", 22, 1 },
+		{ "CciVAwQosN2M", 21, 1 },
+		{ "CciVArValidN2M", 20, 1 },
+		{ "CciVArQosN2M", 16, 4 },
+		{ "CciVWValidN1M", 15, 1 },
+		{ "CciVAwValidN1M", 14, 1 },
+		{ "CciVAwQosN1M", 13, 1 },
+		{ "CciVArValidN1M", 12, 1 },
+		{ "CciVArQosN1M", 8, 4 },
+		{ "CciVWValidN0M", 7, 1 },
+		{ "CciVAwValidN0M", 6, 1 },
+		{ "CciVAwQosN0M", 5, 1 },
+		{ "CciVArValidN0M", 4, 1 },
+		{ "CciVArQosN0M", 0, 4 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_CFG", 0x472d0, 0 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_STATUS", 0x472d4, 0 },
+		{ "CciEvntAwQos", 4, 4 },
+		{ "CciEvntArQos", 0, 4 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_CFG", 0x472d8, 0 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_STATUS", 0x472dc, 0 },
+		{ "CciEvntAwQos", 4, 4 },
+		{ "CciEvntArQos", 0, 4 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_CFG", 0x472e0, 0 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_STATUS", 0x472e4, 0 },
+		{ "CciEvntAwQos", 4, 4 },
+		{ "CciEvntArQos", 0, 4 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_CFG", 0x472e8, 0 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_STATUS", 0x472ec, 0 },
+		{ "CciEvntAwQos", 4, 4 },
+		{ "CciEvntArQos", 0, 4 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_CFG", 0x472f0, 0 },
+	{ "ARM_CCIS_CCI_QVN_SLAVE_STATUS", 0x472f4, 0 },
+		{ "CciEvntAwQos", 4, 4 },
+		{ "CciEvntArQos", 0, 4 },
+	{ "ARM_CCI_EVNTBUS", 0x47300, 0 },
+	{ "ARM_CCI_EVNTBUS", 0x47304, 0 },
+	{ "ARM_CCI_EVNTBUS", 0x47308, 0 },
+	{ "ARM_CCI_EVNTBUS", 0x4730c, 0 },
+	{ "ARM_CCI_EVNTBUS", 0x47310, 0 },
+	{ "ARM_CCI_RST_N", 0x47318, 0 },
+	{ "ARM_CCI_CSYREQ", 0x4731c, 0 },
+	{ "ARM_CCI_TR_DEBUGS0", 0x47320, 0 },
+		{ "CciS0RCnt", 24, 8 },
+		{ "CciS0ArCnt", 16, 8 },
+		{ "CciS0WCnt", 8, 8 },
+		{ "CciS0AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGS1", 0x47324, 0 },
+		{ "CciS1RCnt", 24, 8 },
+		{ "CciS1ArCnt", 16, 8 },
+		{ "CciS1WCnt", 8, 8 },
+		{ "CciS1AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGS2", 0x47328, 0 },
+		{ "CciS2RCnt", 24, 8 },
+		{ "CciS2ArCnt", 16, 8 },
+		{ "CciS2WCnt", 8, 8 },
+		{ "CciS2AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGS3", 0x4732c, 0 },
+		{ "CciS3RCnt", 24, 8 },
+		{ "CciS3ArCnt", 16, 8 },
+		{ "CciS3WCnt", 8, 8 },
+		{ "CciS3AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGS4", 0x47330, 0 },
+		{ "CciS4RCnt", 24, 8 },
+		{ "CciS4ArCnt", 16, 8 },
+		{ "CciS4WCnt", 8, 8 },
+		{ "CciS4AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGS34", 0x47334, 0 },
+		{ "CciS4RspCnt", 24, 8 },
+		{ "CciS4AcCnt", 16, 8 },
+		{ "CciS3RspCnt", 8, 8 },
+		{ "CciS3AcCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGM0", 0x47338, 0 },
+		{ "CciM0RCnt", 24, 8 },
+		{ "CciM0ArCnt", 16, 8 },
+		{ "CciM0WCnt", 8, 8 },
+		{ "CciM0AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGM1", 0x4733c, 0 },
+		{ "CciM1RCnt", 24, 8 },
+		{ "CciM1ArCnt", 16, 8 },
+		{ "CciM1WCnt", 8, 8 },
+		{ "CciM1AwCnt", 0, 8 },
+	{ "ARM_CCI_TR_DEBUGM2", 0x47340, 0 },
+		{ "CciM2RCnt", 24, 8 },
+		{ "CciM2ArCnt", 16, 8 },
+		{ "CciM2WCnt", 8, 8 },
+		{ "CciM2AwCnt", 0, 8 },
+	{ "ARM_MA_TR_DEBUG", 0x47344, 0 },
+		{ "ma1_rd_cnt", 24, 8 },
+		{ "ma1_wr_cnt", 16, 8 },
+		{ "ma0_rd_cnt", 8, 8 },
+		{ "ma0_wr_cnt", 0, 8 },
+	{ "ARM_GP_INT", 0x47348, 0 },
+	{ "ARM_DMA_CFG0", 0x47350, 0 },
+	{ "ARM_DMA_CFG1", 0x47354, 0 },
+		{ "DmaBootPeriphNs", 16, 10 },
+		{ "DmaBootIrqNs", 4, 10 },
+		{ "DmaBootManagerNs", 1, 1 },
+		{ "DmaBootFromPc", 0, 1 },
+	{ "ARM_ARM_CFG0", 0x47380, 0 },
+		{ "MessageBypass_data", 2, 1 },
+		{ "MessageBypass", 1, 1 },
+		{ "PcieBypass", 0, 1 },
+	{ "ARM_ARM_CFG1", 0x47384, 0 },
+	{ "ARM_ARM_CFG1", 0x47388, 0 },
+	{ "ARM_ARM_CFG2", 0x47390, 0 },
+	{ "ARM_ARM_CFG2", 0x47394, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION0", 0x47400, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION1", 0x47404, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION2", 0x47408, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION3", 0x4740c, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION4", 0x47410, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION5", 0x47414, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION6", 0x47418, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION7", 0x4741c, 0 },
+	{ "ARM_PCIE_MA_ADDR_REGION_DST", 0x47440, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA0", 0x47500, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA1", 0x47504, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG0", 0x47508, 0 },
+		{ "WaterMark", 16, 10 },
+		{ "SizeMax", 0, 10 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG1", 0x4750c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG2", 0x47510, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG3", 0x47514, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x47518, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x4751c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA0", 0x47530, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA1", 0x47534, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG0", 0x47538, 0 },
+		{ "WaterMark", 16, 10 },
+		{ "SizeMax", 0, 10 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG1", 0x4753c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG2", 0x47540, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG3", 0x47544, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x47548, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x4754c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA0", 0x47560, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA1", 0x47564, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG0", 0x47568, 0 },
+		{ "WaterMark", 16, 10 },
+		{ "SizeMax", 0, 10 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG1", 0x4756c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG2", 0x47570, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG3", 0x47574, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x47578, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x4757c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA0", 0x47590, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_BA1", 0x47594, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG0", 0x47598, 0 },
+		{ "WaterMark", 16, 10 },
+		{ "SizeMax", 0, 10 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG1", 0x4759c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG2", 0x475a0, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG3", 0x475a4, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x475a8, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG4", 0x475ac, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_0_STATUS", 0x47600, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_1_STATUS", 0x47604, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_2_STATUS", 0x47608, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_3_STATUS", 0x4760c, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_0_ENABLE", 0x47610, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_1_ENABLE", 0x47614, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_2_ENABLE", 0x47618, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_3_ENABLE", 0x4761c, 0 },
+	{ "ARM_APB2MSI_INTERRUPT_PRIORITY_LEVEL", 0x47620, 0 },
+	{ "ARM_APB2MSI_MEM_READ_ADDR", 0x47624, 0 },
+	{ "ARM_MSI_MEMORY_DATA", 0x47628, 0 },
+	{ "ARM_MSI_MEMORY_ADDR", 0x4762c, 0 },
+	{ "ARM_MSG_PCIE_MESSAGE2AXI_CFG5", 0x47630, 0 },
+	{ "ARM_AXI2MA_TIMERCNT", 0x47640, 0 },
+	{ "ARM_AXI2MA_TRTYPE", 0x47644, 0 },
+		{ "ArmMa2Axi1ArTrType", 3, 1 },
+		{ "ArmMa2Axi1AwTrType", 2, 1 },
+		{ "ArmMa2Axi0ArTrType", 1, 1 },
+		{ "ArmMa2Axi0AwTrType", 0, 1 },
+	{ "ARM_AXI2PCIE_VENDOR", 0x47660, 0 },
+		{ "VendorID", 4, 16 },
+		{ "OBFFcode", 0, 4 },
+	{ "ARM_AXI2PCIE_VENMSGHDR_DW3", 0x47664, 0 },
+	{ "ARM_CLUSTER_SEL", 0x47668, 0 },
+	{ "ARM_PWRREQ_PERMIT_ADB", 0x4766c, 0 },
+		{ "pwrq_permit_deny_sar", 1, 1 },
+		{ "pwrqreqns_adb", 0, 1 },
+	{ "ARM_CLK_REQ_ADB", 0x47670, 0 },
+	{ "ARM_WAKEUPM", 0x47674, 0 },
+		{ "dftrstdisablem_adb", 2, 1 },
+		{ "dftrstdisables_adb", 1, 1 },
+		{ "wakeupm_i_adb", 0, 1 },
+	{ "ARM_CC_APB_FILTERING", 0x47678, 0 },
+		{ "cc_dftscanmode", 11, 1 },
+		{ "cc_otp_filtering_disable", 10, 1 },
+		{ "cc_apb_filtering", 0, 10 },
+	{ "ARM_DCU_EN0", 0x4767c, 0 },
+	{ "ARM_DCU_EN1", 0x47680, 0 },
+	{ "ARM_DCU_EN2", 0x47684, 0 },
+	{ "ARM_DCU_EN3", 0x47688, 0 },
+	{ "ARM_DCU_LOCK0", 0x4768c, 0 },
+	{ "ARM_DCU_LOCK1", 0x47690, 0 },
+	{ "ARM_DCU_LOCK2", 0x47694, 0 },
+	{ "ARM_DCU_LOCK3", 0x47698, 0 },
+	{ "ARM_GPPC", 0x4769c, 0 },
+		{ "cc_sec_debug_reset", 24, 1 },
+		{ "cc_dftse", 23, 1 },
+		{ "cc_dftcgen", 22, 1 },
+		{ "cc_dftramhold", 21, 1 },
+		{ "cc_lock_bits", 12, 9 },
+		{ "cc_lcs_is_valid", 11, 1 },
+		{ "cc_lcs", 8, 3 },
+		{ "cc_gppc", 0, 8 },
+	{ "ARM_EMMC", 0x47700, 0 },
+		{ "emmc_card_clk_en", 31, 1 },
+		{ "emmc_led_control", 30, 1 },
+		{ "emmc_uhs1_swvolt_en", 29, 1 },
+		{ "emmc_uhs1_drv_sth", 27, 2 },
+		{ "emmc_sd_vdd1_on", 26, 1 },
+		{ "emmc_sd_vdd1_sel", 23, 3 },
+		{ "emmc_intclk_en", 22, 1 },
+		{ "emmc_card_clk_freq_sel", 12, 10 },
+		{ "emmc_card_clk_gen_sel", 11, 1 },
+		{ "emmc_clk2card_on", 10, 1 },
+		{ "emmc_card_clk_stable", 9, 1 },
+		{ "emmc_int_bclk_stable", 8, 1 },
+		{ "emmc_int_aclk_stable", 7, 1 },
+		{ "emmc_int_tmclk_stable", 6, 1 },
+		{ "emmc_host_reg_vol_stable", 5, 1 },
+		{ "emmc_card_detect_n", 4, 1 },
+		{ "emmc_card_write_prot", 3, 1 },
+		{ "emmc_gp_in", 2, 1 },
+		{ "emmc_test_scan_mode", 1, 1 },
+		{ "emmc_FifoInjDataErr", 0, 1 },
+	{ "ARM_WAKEUPS", 0x47704, 0 },
+	{ "ARM_CLKREQNM_ADB", 0x47708, 0 },
+	{ "ARM_ATOMICDATA0_0", 0x4770c, 0 },
+	{ "ARM_ATOMICDATA0_1", 0x477b0, 0 },
+	{ "ARM_ATOMICDATA1_0", 0x47710, 0 },
+	{ "ARM_ATOMICDATA1_1", 0x477b4, 0 },
+	{ "ARM_TCAM_WRITE_DATA", 0x47744, 0 },
+	{ "ARM_TCAM_WRITE_ADDR", 0x47748, 0 },
+	{ "ARM_TCAM_READ_ADDR", 0x4774c, 0 },
+	{ "ARM_TCAM_CTL", 0x47750, 0 },
+		{ "TcamCbBusy", 6, 1 },
+		{ "TcamCbPass", 5, 1 },
+		{ "TcamCbStart", 4, 1 },
+		{ "TcamRstCb", 3, 1 },
+		{ "tcam_ReqBitPos", 2, 1 },
+		{ "tcam_write", 1, 1 },
+		{ "tcam_enable", 0, 1 },
+	{ "ARM_TCAM_READ_DATA", 0x4775c, 0 },
+	{ "ARM_SRAM1_WRITE_DATA", 0x47760, 0 },
+	{ "ARM_SRAM1_WRITE_ADDR", 0x47764, 0 },
+	{ "ARM_SRAM1_READ_ADDR", 0x47768, 0 },
+	{ "ARM_SRAM1_CTL", 0x4776c, 0 },
+		{ "sram1_write", 1, 1 },
+		{ "sram1_enable", 0, 1 },
+	{ "ARM_SRAM1_READ_DATA", 0x47770, 0 },
+	{ "ARM_SRAM2_WRITE_DATA0", 0x47774, 0 },
+	{ "ARM_SRAM2_WRITE_DATA1", 0x47778, 0 },
+	{ "ARM_SRAM2_WRITE_DATA2", 0x4777c, 0 },
+	{ "ARM_SRAM2_WRITE_DATA3", 0x47210, 0 },
+	{ "ARM_SRAM2_WRITE_ADDR", 0x47780, 0 },
+	{ "ARM_SRAM2_READ_ADDR", 0x47784, 0 },
+	{ "ARM_SRAM2_CTL", 0x47788, 0 },
+		{ "sram2_write", 1, 1 },
+		{ "sram2_enable", 0, 1 },
+	{ "ARM_SRAM2_READ_DATA0", 0x4778c, 0 },
+	{ "ARM_SRAM2_READ_DATA1", 0x47790, 0 },
+	{ "ARM_SRAM2_READ_DATA2", 0x47794, 0 },
+	{ "ARM_SRAM2_READ_DATA3", 0x4721c, 0 },
+	{ "ARM_DBPROC_SRAM_CTL", 0x47798, 0 },
+	{ "ARM_DBPROC_SRAM_READ_ADDR", 0x4779c, 0 },
+	{ "ARM_DBPROC_SRAM_READ_DATA0", 0x477a0, 0 },
+	{ "ARM_DBPROC_SRAM_READ_DATA1", 0x477a4, 0 },
+	{ "ARM_DBPROC_SRAM_READ_DATA2", 0x477a8, 0 },
+	{ "ARM_DBPROC_SRAM_READ_DATA3", 0x477ac, 0 },
+	{ "ARM_DBPROC_CONTROL", 0x4742c, 0 },
+	{ "ARM_SPIDEN", 0x477b8, 0 },
+	{ "ARM_RC_INT_WRITE_DATA", 0x477bc, 0 },
+	{ "ARM_RC_INT_STATUS", 0x4705c, 0 },
+	{ "ARM_DFT_MBI", 0x477c4, 0 },
+		{ "mbistreq", 3, 1 },
+		{ "mbistresetn", 2, 1 },
+		{ "dftramhold", 1, 1 },
+		{ "dftcgen", 0, 1 },
+	{ "ARM_PLM_RID_CFG", 0x4703c, 0 },
+	{ "ARM_PLM_EROM_CFG", 0x47040, 0 },
+	{ "ARM_PL_ARM_HDR_CFG", 0x4704c, 0 },
+	{ "ARM_MBISTACK", 0x477d4, 0 },
+	{ "ARM_MBISTADDR", 0x477d8, 0 },
+	{ "ARM_MBISTREADEN", 0x477dc, 0 },
+	{ "ARM_MBISTWRITEEN", 0x477e0, 0 },
+	{ "ARM_MBISTARRAY", 0x477e4, 0 },
+	{ "ARM_MBISTCFG", 0x477e8, 0 },
+	{ "ARM_MBISTINDATA0", 0x477ec, 0 },
+	{ "ARM_MBISTINDATA1", 0x477f0, 0 },
+	{ "ARM_MBISTOUTDATA1", 0x477f4, 0 },
+	{ "ARM_MBISTOUTDATA0", 0x477f8, 0 },
+	{ "ARM_PL_DMA_AW_OFFSET", 0x47018, 0 },
+	{ "ARM_PL_DMA_AR_OFFSET", 0x4701c, 0 },
+	{ "ARM_DMA_RST", 0x4702c, 0 },
+	{ "ARM_APB_CFG", 0x47224, 0 },
+	{ "ARM_EMMC_BUFS", 0x47228, 0 },
+		{ "emmc_bufs_oen", 2, 2 },
+		{ "emmc_bufs_i", 0, 2 },
+	{ "ARM_SWP_EN", 0x4722c, 0 },
+	{ "ARM_GIC_USER", 0x47238, 0 },
+	{ "ARM_DBPROC_SRAM_TH_CTL", 0x477c8, 0 },
+		{ "dbproc_th_wr_en", 1, 1 },
+		{ "dbproc_th_rd_en", 0, 1 },
+	{ "ARM_DBPROC_SRAM_TH_ADDR", 0x47240, 0 },
+	{ "ARM_DBPROC_SRAM_TH_READ_DATA0", 0x47244, 0 },
+	{ "ARM_DBPROC_SRAM_TH_READ_DATA1", 0x47248, 0 },
+	{ "ARM_DBPROC_SRAM_TH_READ_DATA2", 0x4724c, 0 },
+	{ "ARM_DBPROC_SRAM_TH_READ_DATA3", 0x47250, 0 },
+	{ "ARM_DBPROC_SRAM_TH_WR_DATA0", 0x47254, 0 },
+	{ "ARM_DBPROC_SRAM_TH_WR_DATA1", 0x47258, 0 },
+	{ "ARM_DBPROC_SRAM_TH_WR_DATA2", 0x4725c, 0 },
+	{ "ARM_DBPROC_SRAM_TH_WR_DATA3", 0x47260, 0 },
+	{ "ARM_SWP_EN_2", 0x47264, 0 },
+	{ "ARM_GIC_ERR", 0x47268, 0 },
+		{ "ecc_fatal", 1, 1 },
+		{ "axim_err", 0, 1 },
+	{ "ARM_CPU_STAT", 0x4726c, 0 },
+		{ "cpu_l2_qactive", 12, 1 },
+		{ "wakeupm_o_adb", 11, 1 },
+		{ "pwrqactivem_adb", 10, 1 },
+		{ "clkqactivem_adb", 9, 1 },
+		{ "clkqdenym_adb", 8, 1 },
+		{ "clkqacceptnm_adb", 7, 1 },
+		{ "wakeups_o_adb", 6, 1 },
+		{ "pwrqactives_adb", 5, 1 },
+		{ "clkqactives_adb", 4, 1 },
+		{ "clkqdenys_adb", 3, 1 },
+		{ "clkqacceptns_adb", 2, 1 },
+		{ "pwrqdenys_adb", 1, 1 },
+		{ "pwrqacceptns_adb", 0, 1 },
+	{ "ARM_DEBUG_INT_WRITE_DATA", 0x47270, 0 },
+	{ "ARM_DEBUG_INT_STAT", 0x47274, 0 },
+	{ "ARM_DEBUG_STAT", 0x47278, 0 },
+	{ "ARM_SIZE_STAT", 0x4727c, 0 },
+	{ "ARM_CS_RST", 0x470c0, 0 },
+		{ "atclken", 9, 1 },
+		{ "cxapbicrstn", 8, 1 },
+		{ "csdbgen", 7, 1 },
+		{ "jtagnpotrst", 6, 1 },
+		{ "jtagntrst", 5, 1 },
+		{ "paddr31s0", 4, 1 },
+		{ "cticlken", 3, 1 },
+		{ "pclkendbg", 2, 1 },
+		{ "cpu_niden", 1, 1 },
+		{ "cpu_dbgen", 0, 1 },
+	{ "ARM_CS_ADDRL", 0x470c4, 0 },
+	{ "ARM_CS_ADDRH", 0x470c8, 0 },
+	{ "ARM_CS_DFT_CONTROL", 0x470cc, 0 },
+		{ "dftmbistaddr", 5, 11 },
+		{ "dftmteston", 3, 1 },
+		{ "dftmbistce", 2, 1 },
+		{ "dftmbitwr", 1, 1 },
+		{ "dftse", 0, 1 },
+	{ "ARM_CS_DFT_IN", 0x470d0, 0 },
+	{ "ARM_CS_DFT_OUT", 0x470d4, 0 },
+	{ "ARM_EMMC_CTRL", 0x47088, 0 },
+		{ "EMMC_DATA_P2", 24, 8 },
+		{ "EMMC_DATA_P1", 16, 8 },
+		{ "EMMC_CMD_P2", 15, 1 },
+		{ "EMMC_CMD_P1", 14, 1 },
+		{ "EMMC_RST_P2", 13, 1 },
+		{ "EMMC_RST_P1", 12, 1 },
+		{ "EMMC_GP_IN_P2", 10, 2 },
+		{ "EMMC_GP_IN_P1", 8, 2 },
+		{ "EMMC_CLK_SEL", 0, 8 },
+	{ "ARM_INTERRUPT_GEN", 0x47420, 0 },
+	{ "ARM_INTERRUPT_CLEAR", 0x47424, 0 },
+	{ "ARM_DEBUG_STATUS_0", 0x47428, 0 },
+	{ "ARM_DEBUG_STATUS_1", 0x4743c, 0 },
+	{ "ARM_NVME_DB_EMU_EN", 0x477fc, 0 },
+	{ "ARM_NVME_DB_EMU_INT_CAUSE", 0x4709c, 0 },
+		{ "invalid_bresp", 3, 1 },
+		{ "data_len_of", 2, 1 },
+		{ "invalid_emu_addr", 1, 1 },
+		{ "invalid_axi_addr_cfg", 0, 1 },
+	{ "ARM_NVME_DB_EMU_INT_ENABLE", 0x47740, 0 },
+		{ "invalid_bresp", 3, 1 },
+		{ "data_len_of", 2, 1 },
+		{ "invalid_emu_addr", 1, 1 },
+		{ "invalid_axi_addr_cfg", 0, 1 },
+	{ "ARM_NVME_DB_EMU_INDEX", 0x471a0, 0 },
+	{ "ARM_NVME_DB_EMU_REGION_CTL", 0x471a4, 0 },
+		{ "window_en", 4, 1 },
+		{ "rgn2_int_en", 3, 1 },
+		{ "rgn1_int_en", 2, 1 },
+		{ "queue_en", 1, 1 },
+		{ "rgn0_int_en", 0, 1 },
+	{ "ARM_NVME_DB_EMU_DEVICE_CTL", 0x471a8, 0 },
+		{ "device_size", 8, 4 },
+		{ "rgn1_size", 4, 4 },
+		{ "rgn0_size", 0, 4 },
+	{ "ARM_NVME_DB_EMU_WINDOW_START_ADDR", 0x471b0, 0 },
+	{ "ARM_NVME_DB_EMU_WINDOW_END_ADDR", 0x471b4, 0 },
+	{ "ARM_NVME_DB_EMU_QBASE_ADDR", 0x471b8, 0 },
+	{ "ARM_NVME_DB_EMU_QUEUE_CID", 0x471bc, 0 },
+	{ "ARM_NVME_DB_EMU_QUEUE_CTL", 0x471c0, 0 },
+		{ "int_en", 27, 1 },
+		{ "threshold", 10, 17 },
+		{ "size", 0, 10 },
+	{ "ARM_NVME_DB_EMU_QUEUE_CTL_2", 0x471e0, 0 },
+	{ "ARM_NVME_DB_EMU_MSIX_ADDR_L", 0x471c4, 0 },
+	{ "ARM_NVME_DB_EMU_MSIX_ADDR_H", 0x471c8, 0 },
+	{ "ARM_NVME_DB_EMU_MSIX_OFFSET", 0x471cc, 0 },
+	{ "ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_L", 0x471d0, 0 },
+	{ "ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_H", 0x471d4, 0 },
+	{ "ARM_NVME_DB_EMU_QUEUE_MSIX_OFFSET", 0x471d8, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_mc_t70_regs[] = {
+	{ "MC_IND_ADDR", 0x48000, 0 },
+		{ "autoincr", 30, 2 },
+		{ "addr", 0, 25 },
+	{ "MC_IND_DATA", 0x48004, 0 },
+	{ "MC_DBG_CTL", 0x48018, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG", 16, 1 },
+		{ "SEL", 0, 8 },
+	{ "MC_DBG_DATA", 0x4801c, 0 },
+	{ "MC_P_DDRPHY_RST_CTRL", 0x49300, 0 },
+		{ "PHY_CAL_REQ", 21, 1 },
+		{ "PHY_DRAM_WL", 17, 4 },
+		{ "PHY_CALIB_DONE", 5, 1 },
+		{ "CTL_CAL_REQ", 4, 1 },
+		{ "CTL_CKE", 3, 1 },
+		{ "CTL_RST_N", 2, 1 },
+		{ "DDRIO_ENABLE", 1, 1 },
+		{ "PHY_RST_N", 0, 1 },
+	{ "MC_P_PERFORMANCE_CTRL", 0x49304, 0 },
+		{ "BUF_USE_TH", 12, 3 },
+		{ "MC_IDLE_TH", 8, 4 },
+		{ "RMW_DEFER_EN", 7, 1 },
+		{ "DDR3_BRBC_MODE", 6, 1 },
+		{ "RMW_DWRITE_EN", 5, 1 },
+		{ "RMW_MERGE_EN", 4, 1 },
+		{ "SYNC_PAB_EN", 3, 1 },
+		{ "STALL_CHK_BIT", 2, 1 },
+		{ "DDR3_BRC_MODE", 1, 1 },
+		{ "RMW_PERF_CTRL", 0, 1 },
+	{ "MC_P_ECC_CTRL", 0x49308, 0 },
+		{ "BistECCHBWCtl", 7, 2 },
+		{ "BistTestMode", 6, 1 },
+		{ "rmw_ctl_cfg", 4, 2 },
+		{ "ECC_BYPASS_BIST", 1, 1 },
+		{ "ECC_DISABLE", 0, 1 },
+	{ "MC_P_DDRCTL_INT_ENABLE", 0x4930c, 0 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE", 5, 1 },
+		{ "HIF_RDATA_CRC_ERR_DCH1_ENABLE", 4, 1 },
+		{ "HIF_RDATA_ADDR_ERR_DCH1_ENABLE", 3, 1 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE", 2, 1 },
+		{ "HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE", 1, 1 },
+		{ "HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE", 0, 1 },
+	{ "MC_P_DDRCTL_INT_CAUSE", 0x49310, 0 },
+		{ "WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE", 25, 1 },
+		{ "WR_CRC_ERR_INTR_DCH1_CAUSE", 24, 1 },
+		{ "CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE", 23, 1 },
+		{ "RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE", 22, 1 },
+		{ "DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE", 21, 1 },
+		{ "SWCMD_ERR_INTR_DCH1_CAUSE", 20, 1 },
+		{ "DUCMD_ERR_INTR_DCH1_CAUSE", 19, 1 },
+		{ "LCCMD_ERR_INTR_DCH1_CAUSE", 18, 1 },
+		{ "CTRLUPD_ERR_INTR_DCH1_CAUSE", 17, 1 },
+		{ "RFM_ALERT_INTR_DCH1_CAUSE", 16, 1 },
+		{ "WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE", 15, 1 },
+		{ "WR_CRC_ERR_INTR_DCH0_CAUSE", 14, 1 },
+		{ "CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE", 13, 1 },
+		{ "RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE", 12, 1 },
+		{ "DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE", 11, 1 },
+		{ "SWCMD_ERR_INTR_DCH0_CAUSE", 10, 1 },
+		{ "DUCMD_ERR_INTR_DCH0_CAUSE", 9, 1 },
+		{ "LCCMD_ERR_INTR_DCH0_CAUSE", 8, 1 },
+		{ "CTRLUPD_ERR_INTR_DCH0_CAUSE", 7, 1 },
+		{ "RFM_ALERT_INTR_DCH0_CAUSE", 6, 1 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE", 5, 1 },
+		{ "HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE", 4, 1 },
+		{ "HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE", 3, 1 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE", 2, 1 },
+		{ "HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE", 1, 1 },
+		{ "HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE", 0, 1 },
+	{ "MC_P_PAR_ENABLE", 0x49314, 0 },
+		{ "HIF_WDATA_Q_PARERR_DCH1_ENABLE", 13, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH1_ENABLE", 12, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH0_ENABLE", 11, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH1_ENABLE", 10, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH0_ENABLE", 9, 1 },
+		{ "WDATARAM_PARERR_DCH1_ENABLE", 8, 1 },
+		{ "WDATARAM_PARERR_DCH0_ENABLE", 7, 1 },
+		{ "BIST_ADDR_FIFO_PARERR_ENABLE", 6, 1 },
+		{ "BIST_ERR_ADDR_FIFO_PARERR_ENABLE", 5, 1 },
+		{ "HIF_WDATA_Q_PARERR_DCH0_ENABLE", 4, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH1_ENABLE", 3, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH0_ENABLE", 2, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE", 1, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE", 0, 1 },
+	{ "MC_P_PAR_CAUSE", 0x49318, 0 },
+		{ "HIF_WDATA_Q_PARERR_DCH1_CAUSE", 13, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH1_CAUSE", 12, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH0_CAUSE", 11, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH1_CAUSE", 10, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH0_CAUSE", 9, 1 },
+		{ "WDATARAM_PARERR_DCH1_CAUSE", 8, 1 },
+		{ "WDATARAM_PARERR_DCH0_CAUSE", 7, 1 },
+		{ "BIST_ADDR_FIFO_PARERR_CAUSE", 6, 1 },
+		{ "BIST_ERR_ADDR_FIFO_PARERR_CAUSE", 5, 1 },
+		{ "HIF_WDATA_Q_PARERR_DCH0_CAUSE", 4, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH1_CAUSE", 3, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH0_CAUSE", 2, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE", 1, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE", 0, 1 },
+	{ "MC_P_INT_ENABLE", 0x4931c, 0 },
+		{ "DDRPHY_INT_ENABLE", 4, 1 },
+		{ "DDRCTL_INT_ENABLE", 3, 1 },
+		{ "ECC_CE_INT_ENABLE", 2, 1 },
+		{ "ECC_UE_INT_ENABLE", 1, 1 },
+		{ "PERR_INT_ENABLE", 0, 1 },
+	{ "MC_P_INT_CAUSE", 0x49320, 0 },
+		{ "DDRPHY_INT_CAUSE", 4, 1 },
+		{ "DDRCTL_INT_CAUSE", 3, 1 },
+		{ "ECC_CE_INT_CAUSE", 2, 1 },
+		{ "ECC_UE_INT_CAUSE", 1, 1 },
+		{ "PERR_INT_CAUSE", 0, 1 },
+	{ "MC_P_ECC_UE_INT_ENABLE", 0x49324, 0 },
+	{ "MC_P_ECC_UE_INT_CAUSE", 0x49328, 0 },
+	{ "MC_P_ECC_STATUS", 0x4932c, 0 },
+		{ "ECC_CECNT", 16, 16 },
+		{ "ECC_UECNT", 0, 16 },
+	{ "MC_P_PHY_CTRL", 0x49330, 0 },
+	{ "MC_P_STATIC_CFG_STATUS", 0x49334, 0 },
+		{ "DfiFreqRatio", 27, 1 },
+		{ "STATIC_PP64", 26, 1 },
+		{ "STATIC_PPEN", 25, 1 },
+		{ "STATIC_OOOEN", 24, 1 },
+		{ "STATIC_AWEN", 23, 1 },
+		{ "STATIC_SWLAT", 18, 5 },
+		{ "STATIC_WLAT", 17, 1 },
+		{ "STATIC_ALIGN", 16, 1 },
+		{ "STATIC_SLAT", 11, 5 },
+		{ "STATIC_LAT", 10, 1 },
+		{ "STATIC_MODE", 9, 1 },
+		{ "STATIC_DEN", 6, 3 },
+		{ "STATIC_ORG", 5, 1 },
+		{ "STATIC_RKS", 4, 1 },
+		{ "STATIC_DDR5_HBW_Channel", 3, 1 },
+		{ "STATIC_DDR5_HBW", 2, 1 },
+		{ "STATIC_WIDTH", 1, 1 },
+		{ "STATIC_SLOW", 0, 1 },
+	{ "MC_P_CORE_PCTL_STAT", 0x49338, 0 },
+	{ "MC_P_DEBUG_CNT", 0x4933c, 0 },
+		{ "WDATA_OCNT", 8, 5 },
+		{ "RDATA_OCNT", 0, 5 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49340, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49344, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49348, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x4934c, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49350, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49354, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49358, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x4935c, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49360, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49364, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49368, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x4936c, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49370, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49374, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x49378, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x4937c, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x49380, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x49384, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x49388, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x4938c, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x49390, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x49394, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x49398, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x4939c, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493a0, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493a4, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493a8, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493ac, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493b0, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493b4, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493b8, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x493bc, 0 },
+	{ "MC_CE_ADDR", 0x493c0, 0 },
+	{ "MC_UE_ADDR", 0x493c4, 0 },
+	{ "MC_P_DEEP_SLEEP", 0x493c8, 0 },
+		{ "SleepStatus", 1, 1 },
+		{ "SleepReq", 0, 1 },
+	{ "MC_P_FPGA_BONUS", 0x493cc, 0 },
+	{ "MC_P_DEBUG_CFG", 0x493d0, 0 },
+		{ "DEBUG_OR", 15, 1 },
+		{ "DEBUG_HI", 14, 1 },
+		{ "DEBUG_RPT", 13, 1 },
+		{ "DEBUGPAGE", 10, 3 },
+		{ "DEBUGSELH", 5, 5 },
+		{ "DEBUGSELL", 0, 5 },
+	{ "MC_P_DEBUG_RPT", 0x493d4, 0 },
+	{ "MC_P_PHY_ADR_CK_EN", 0x493d8, 0 },
+	{ "MC_P_WDATARAM_INIT", 0x493dc, 0 },
+		{ "ENABLE_DCH1", 1, 1 },
+		{ "ENABLE_DCH0", 0, 1 },
+	{ "MC_CE_ERR_ECC_DATA0", 0x493e0, 0 },
+	{ "MC_CE_ERR_ECC_DATA1", 0x493e4, 0 },
+	{ "MC_UE_ERR_ECC_DATA0", 0x493e8, 0 },
+	{ "MC_UE_ERR_ECC_DATA1", 0x493ec, 0 },
+	{ "MC_P_RMW_PRIO", 0x493f0, 0 },
+		{ "WR_HI_TH", 24, 8 },
+		{ "WR_MID_TH", 16, 8 },
+		{ "RD_HI_TH", 8, 8 },
+		{ "RD_MID_TH", 0, 8 },
+	{ "MC_P_BIST_CMD", 0x49400, 0 },
+		{ "START_BIST", 31, 1 },
+		{ "FIFO_ERROR_FLAG", 30, 1 },
+		{ "BURST_LEN", 16, 2 },
+		{ "BIST_CMD_GAP", 8, 8 },
+		{ "BIST_OPCODE", 0, 2 },
+	{ "MC_P_BIST_CMD_ADDR", 0x49404, 0 },
+	{ "MC_P_BIST_NUM_BURST", 0x49408, 0 },
+	{ "MC_P_BIST_DATA_PATTERN", 0x4940c, 0 },
+	{ "MC_P_BIST_CRC_SEED", 0x49410, 0 },
+	{ "MC_P_BIST_NUM_ERR", 0x49460, 0 },
+	{ "MC_P_BIST_ERR_ADDR", 0x49464, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49468, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x4946c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49470, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49474, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49478, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x4947c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49480, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49484, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49488, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x4948c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49490, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49494, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x49498, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x4949c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494a0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494a4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494a8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494ac, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494b0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494b4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494b8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494bc, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494c0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494c4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494c8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494cc, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494d0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494d4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494d8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494dc, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494e0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494e4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494e8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494ec, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494f0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x494f4, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_mc_t71_regs[] = {
+	{ "MC_IND_ADDR", 0x58000, 0 },
+		{ "autoincr", 30, 2 },
+		{ "addr", 0, 25 },
+	{ "MC_IND_DATA", 0x58004, 0 },
+	{ "MC_DBG_CTL", 0x58018, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG", 16, 1 },
+		{ "SEL", 0, 8 },
+	{ "MC_DBG_DATA", 0x5801c, 0 },
+	{ "MC_P_DDRPHY_RST_CTRL", 0x59300, 0 },
+		{ "PHY_CAL_REQ", 21, 1 },
+		{ "PHY_DRAM_WL", 17, 4 },
+		{ "PHY_CALIB_DONE", 5, 1 },
+		{ "CTL_CAL_REQ", 4, 1 },
+		{ "CTL_CKE", 3, 1 },
+		{ "CTL_RST_N", 2, 1 },
+		{ "DDRIO_ENABLE", 1, 1 },
+		{ "PHY_RST_N", 0, 1 },
+	{ "MC_P_PERFORMANCE_CTRL", 0x59304, 0 },
+		{ "BUF_USE_TH", 12, 3 },
+		{ "MC_IDLE_TH", 8, 4 },
+		{ "RMW_DEFER_EN", 7, 1 },
+		{ "DDR3_BRBC_MODE", 6, 1 },
+		{ "RMW_DWRITE_EN", 5, 1 },
+		{ "RMW_MERGE_EN", 4, 1 },
+		{ "SYNC_PAB_EN", 3, 1 },
+		{ "STALL_CHK_BIT", 2, 1 },
+		{ "DDR3_BRC_MODE", 1, 1 },
+		{ "RMW_PERF_CTRL", 0, 1 },
+	{ "MC_P_ECC_CTRL", 0x59308, 0 },
+		{ "BistECCHBWCtl", 7, 2 },
+		{ "BistTestMode", 6, 1 },
+		{ "rmw_ctl_cfg", 4, 2 },
+		{ "ECC_BYPASS_BIST", 1, 1 },
+		{ "ECC_DISABLE", 0, 1 },
+	{ "MC_P_DDRCTL_INT_ENABLE", 0x5930c, 0 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE", 5, 1 },
+		{ "HIF_RDATA_CRC_ERR_DCH1_ENABLE", 4, 1 },
+		{ "HIF_RDATA_ADDR_ERR_DCH1_ENABLE", 3, 1 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE", 2, 1 },
+		{ "HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE", 1, 1 },
+		{ "HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE", 0, 1 },
+	{ "MC_P_DDRCTL_INT_CAUSE", 0x59310, 0 },
+		{ "WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE", 25, 1 },
+		{ "WR_CRC_ERR_INTR_DCH1_CAUSE", 24, 1 },
+		{ "CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE", 23, 1 },
+		{ "RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE", 22, 1 },
+		{ "DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE", 21, 1 },
+		{ "SWCMD_ERR_INTR_DCH1_CAUSE", 20, 1 },
+		{ "DUCMD_ERR_INTR_DCH1_CAUSE", 19, 1 },
+		{ "LCCMD_ERR_INTR_DCH1_CAUSE", 18, 1 },
+		{ "CTRLUPD_ERR_INTR_DCH1_CAUSE", 17, 1 },
+		{ "RFM_ALERT_INTR_DCH1_CAUSE", 16, 1 },
+		{ "WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE", 15, 1 },
+		{ "WR_CRC_ERR_INTR_DCH0_CAUSE", 14, 1 },
+		{ "CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE", 13, 1 },
+		{ "RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE", 12, 1 },
+		{ "DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE", 11, 1 },
+		{ "SWCMD_ERR_INTR_DCH0_CAUSE", 10, 1 },
+		{ "DUCMD_ERR_INTR_DCH0_CAUSE", 9, 1 },
+		{ "LCCMD_ERR_INTR_DCH0_CAUSE", 8, 1 },
+		{ "CTRLUPD_ERR_INTR_DCH0_CAUSE", 7, 1 },
+		{ "RFM_ALERT_INTR_DCH0_CAUSE", 6, 1 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE", 5, 1 },
+		{ "HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE", 4, 1 },
+		{ "HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE", 3, 1 },
+		{ "HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE", 2, 1 },
+		{ "HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE", 1, 1 },
+		{ "HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE", 0, 1 },
+	{ "MC_P_PAR_ENABLE", 0x59314, 0 },
+		{ "HIF_WDATA_Q_PARERR_DCH1_ENABLE", 13, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH1_ENABLE", 12, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH0_ENABLE", 11, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH1_ENABLE", 10, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH0_ENABLE", 9, 1 },
+		{ "WDATARAM_PARERR_DCH1_ENABLE", 8, 1 },
+		{ "WDATARAM_PARERR_DCH0_ENABLE", 7, 1 },
+		{ "BIST_ADDR_FIFO_PARERR_ENABLE", 6, 1 },
+		{ "BIST_ERR_ADDR_FIFO_PARERR_ENABLE", 5, 1 },
+		{ "HIF_WDATA_Q_PARERR_DCH0_ENABLE", 4, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH1_ENABLE", 3, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH0_ENABLE", 2, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE", 1, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE", 0, 1 },
+	{ "MC_P_PAR_CAUSE", 0x59318, 0 },
+		{ "HIF_WDATA_Q_PARERR_DCH1_CAUSE", 13, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH1_CAUSE", 12, 1 },
+		{ "DDRCTL_ECC_CE_PAR_DCH0_CAUSE", 11, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH1_CAUSE", 10, 1 },
+		{ "DDRCTL_ECC_UE_PAR_DCH0_CAUSE", 9, 1 },
+		{ "WDATARAM_PARERR_DCH1_CAUSE", 8, 1 },
+		{ "WDATARAM_PARERR_DCH0_CAUSE", 7, 1 },
+		{ "BIST_ADDR_FIFO_PARERR_CAUSE", 6, 1 },
+		{ "BIST_ERR_ADDR_FIFO_PARERR_CAUSE", 5, 1 },
+		{ "HIF_WDATA_Q_PARERR_DCH0_CAUSE", 4, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH1_CAUSE", 3, 1 },
+		{ "HIF_RSPDATA_Q_PARERR_DCH0_CAUSE", 2, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE", 1, 1 },
+		{ "HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE", 0, 1 },
+	{ "MC_P_INT_ENABLE", 0x5931c, 0 },
+		{ "DDRPHY_INT_ENABLE", 4, 1 },
+		{ "DDRCTL_INT_ENABLE", 3, 1 },
+		{ "ECC_CE_INT_ENABLE", 2, 1 },
+		{ "ECC_UE_INT_ENABLE", 1, 1 },
+		{ "PERR_INT_ENABLE", 0, 1 },
+	{ "MC_P_INT_CAUSE", 0x59320, 0 },
+		{ "DDRPHY_INT_CAUSE", 4, 1 },
+		{ "DDRCTL_INT_CAUSE", 3, 1 },
+		{ "ECC_CE_INT_CAUSE", 2, 1 },
+		{ "ECC_UE_INT_CAUSE", 1, 1 },
+		{ "PERR_INT_CAUSE", 0, 1 },
+	{ "MC_P_ECC_UE_INT_ENABLE", 0x59324, 0 },
+	{ "MC_P_ECC_UE_INT_CAUSE", 0x59328, 0 },
+	{ "MC_P_ECC_STATUS", 0x5932c, 0 },
+		{ "ECC_CECNT", 16, 16 },
+		{ "ECC_UECNT", 0, 16 },
+	{ "MC_P_PHY_CTRL", 0x59330, 0 },
+	{ "MC_P_STATIC_CFG_STATUS", 0x59334, 0 },
+		{ "DfiFreqRatio", 27, 1 },
+		{ "STATIC_PP64", 26, 1 },
+		{ "STATIC_PPEN", 25, 1 },
+		{ "STATIC_OOOEN", 24, 1 },
+		{ "STATIC_AWEN", 23, 1 },
+		{ "STATIC_SWLAT", 18, 5 },
+		{ "STATIC_WLAT", 17, 1 },
+		{ "STATIC_ALIGN", 16, 1 },
+		{ "STATIC_SLAT", 11, 5 },
+		{ "STATIC_LAT", 10, 1 },
+		{ "STATIC_MODE", 9, 1 },
+		{ "STATIC_DEN", 6, 3 },
+		{ "STATIC_ORG", 5, 1 },
+		{ "STATIC_RKS", 4, 1 },
+		{ "STATIC_DDR5_HBW_Channel", 3, 1 },
+		{ "STATIC_DDR5_HBW", 2, 1 },
+		{ "STATIC_WIDTH", 1, 1 },
+		{ "STATIC_SLOW", 0, 1 },
+	{ "MC_P_CORE_PCTL_STAT", 0x59338, 0 },
+	{ "MC_P_DEBUG_CNT", 0x5933c, 0 },
+		{ "WDATA_OCNT", 8, 5 },
+		{ "RDATA_OCNT", 0, 5 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59340, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59344, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59348, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x5934c, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59350, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59354, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59358, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x5935c, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59360, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59364, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59368, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x5936c, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59370, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59374, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x59378, 0 },
+	{ "MC_CE_ERR_DATA_RDATA", 0x5937c, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x59380, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x59384, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x59388, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x5938c, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x59390, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x59394, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x59398, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x5939c, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593a0, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593a4, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593a8, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593ac, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593b0, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593b4, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593b8, 0 },
+	{ "MC_UE_ERR_DATA_RDATA", 0x593bc, 0 },
+	{ "MC_CE_ADDR", 0x593c0, 0 },
+	{ "MC_UE_ADDR", 0x593c4, 0 },
+	{ "MC_P_DEEP_SLEEP", 0x593c8, 0 },
+		{ "SleepStatus", 1, 1 },
+		{ "SleepReq", 0, 1 },
+	{ "MC_P_FPGA_BONUS", 0x593cc, 0 },
+	{ "MC_P_DEBUG_CFG", 0x593d0, 0 },
+		{ "DEBUG_OR", 15, 1 },
+		{ "DEBUG_HI", 14, 1 },
+		{ "DEBUG_RPT", 13, 1 },
+		{ "DEBUGPAGE", 10, 3 },
+		{ "DEBUGSELH", 5, 5 },
+		{ "DEBUGSELL", 0, 5 },
+	{ "MC_P_DEBUG_RPT", 0x593d4, 0 },
+	{ "MC_P_PHY_ADR_CK_EN", 0x593d8, 0 },
+	{ "MC_P_WDATARAM_INIT", 0x593dc, 0 },
+		{ "ENABLE_DCH1", 1, 1 },
+		{ "ENABLE_DCH0", 0, 1 },
+	{ "MC_CE_ERR_ECC_DATA0", 0x593e0, 0 },
+	{ "MC_CE_ERR_ECC_DATA1", 0x593e4, 0 },
+	{ "MC_UE_ERR_ECC_DATA0", 0x593e8, 0 },
+	{ "MC_UE_ERR_ECC_DATA1", 0x593ec, 0 },
+	{ "MC_P_RMW_PRIO", 0x593f0, 0 },
+		{ "WR_HI_TH", 24, 8 },
+		{ "WR_MID_TH", 16, 8 },
+		{ "RD_HI_TH", 8, 8 },
+		{ "RD_MID_TH", 0, 8 },
+	{ "MC_P_BIST_CMD", 0x59400, 0 },
+		{ "START_BIST", 31, 1 },
+		{ "FIFO_ERROR_FLAG", 30, 1 },
+		{ "BURST_LEN", 16, 2 },
+		{ "BIST_CMD_GAP", 8, 8 },
+		{ "BIST_OPCODE", 0, 2 },
+	{ "MC_P_BIST_CMD_ADDR", 0x59404, 0 },
+	{ "MC_P_BIST_NUM_BURST", 0x59408, 0 },
+	{ "MC_P_BIST_DATA_PATTERN", 0x5940c, 0 },
+	{ "MC_P_BIST_CRC_SEED", 0x59410, 0 },
+	{ "MC_P_BIST_NUM_ERR", 0x59460, 0 },
+	{ "MC_P_BIST_ERR_ADDR", 0x59464, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59468, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x5946c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59470, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59474, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59478, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x5947c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59480, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59484, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59488, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x5948c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59490, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59494, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x59498, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x5949c, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594a0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594a4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594a8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594ac, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594b0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594b4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594b8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594bc, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594c0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594c4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594c8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594cc, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594d0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594d4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594d8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594dc, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594e0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594e4, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594e8, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594ec, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594f0, 0 },
+	{ "MC_P_BIST_USER_RWEDATA", 0x594f4, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_edc_t60_regs[] = {
+	{ "EDC_H_REF", 0x50000, 0 },
+		{ "SleepStatus", 31, 1 },
+		{ "SleepReq", 30, 1 },
+		{ "PING_PONG", 29, 1 },
+		{ "DramRefEnable", 27, 2 },
+		{ "QDR_ClkPhase", 24, 3 },
+		{ "MaxOpsPerTRC", 21, 3 },
+		{ "NumPipeStages", 19, 2 },
+		{ "EDC_INST_NUM", 18, 1 },
+		{ "ENABLE_PERF", 17, 1 },
+		{ "ECC_BYPASS", 16, 1 },
+		{ "RefFreq", 0, 16 },
+	{ "EDC_H_BIST_CMD", 0x50004, 0 },
+		{ "START_BIST", 31, 1 },
+		{ "BURST_LEN", 16, 2 },
+		{ "BIST_CMD_GAP", 8, 8 },
+		{ "BIST_OPCODE", 0, 2 },
+	{ "EDC_H_BIST_CMD_ADDR", 0x50008, 0 },
+	{ "EDC_H_BIST_CMD_LEN", 0x5000c, 0 },
+	{ "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 },
+	{ "EDC_H_BIST_USER_WDATA0", 0x50014, 0 },
+	{ "EDC_H_BIST_USER_WDATA1", 0x50018, 0 },
+	{ "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 },
+		{ "USER_DATA_MASK", 8, 9 },
+		{ "USER_DATA2", 0, 8 },
+	{ "EDC_H_BIST_NUM_ERR", 0x50020, 0 },
+	{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 },
+	{ "EDC_H_PAR_ENABLE", 0x50070, 0 },
+		{ "ECC_UE_PAR_ENABLE", 2, 1 },
+		{ "ECC_CE_PAR_ENABLE", 1, 1 },
+		{ "PERR_PAR_ENABLE", 0, 1 },
+	{ "EDC_H_INT_ENABLE", 0x50074, 0 },
+		{ "ECC_UE_INT_ENABLE", 2, 1 },
+		{ "ECC_CE_INT_ENABLE", 1, 1 },
+		{ "PERR_INT_ENABLE", 0, 1 },
+	{ "EDC_H_INT_CAUSE", 0x50078, 0 },
+		{ "ECC_UE_INT0_CAUSE", 5, 1 },
+		{ "ECC_CE_INT0_CAUSE", 4, 1 },
+		{ "PERR_INT0_CAUSE", 3, 1 },
+		{ "ECC_UE_INT_CAUSE", 2, 1 },
+		{ "ECC_CE_INT_CAUSE", 1, 1 },
+		{ "PERR_INT_CAUSE", 0, 1 },
+	{ "EDC_H_ECC_STATUS", 0x5007c, 0 },
+		{ "ECC_CECNT", 16, 16 },
+		{ "ECC_UECNT", 0, 16 },
+	{ "EDC_H_ECC_ERR_SEL", 0x50080, 0 },
+	{ "EDC_H_ECC_ERR_ADDR", 0x50084, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 },
+	{ "EDC_H_DBG_MA_CMD_INTF", 0x50300, 0 },
+		{ "MCmdAddr", 12, 20 },
+		{ "MCmdLen", 5, 7 },
+		{ "MCmdNRE", 4, 1 },
+		{ "MCmdNRB", 3, 1 },
+		{ "MCmdWr", 2, 1 },
+		{ "MCmdRdy", 1, 1 },
+		{ "MCmdVld", 0, 1 },
+	{ "EDC_H_DBG_MA_WDATA_INTF", 0x50304, 0 },
+		{ "MWDataVld", 31, 1 },
+		{ "MWDataRdy", 30, 1 },
+		{ "MWData", 0, 30 },
+	{ "EDC_H_DBG_MA_RDATA_INTF", 0x50308, 0 },
+		{ "MRspVld", 31, 1 },
+		{ "MRspRdy", 30, 1 },
+		{ "MRspData", 0, 30 },
+	{ "EDC_H_DBG_BIST_CMD_INTF", 0x5030c, 0 },
+		{ "BCmdAddr", 9, 23 },
+		{ "BCmdLen", 3, 6 },
+		{ "BCmdWr", 2, 1 },
+		{ "BCmdRdy", 1, 1 },
+		{ "BCmdVld", 0, 1 },
+	{ "EDC_H_DBG_BIST_WDATA_INTF", 0x50310, 0 },
+		{ "BWDataVld", 31, 1 },
+		{ "BWDataRdy", 30, 1 },
+		{ "BWData", 0, 30 },
+	{ "EDC_H_DBG_BIST_RDATA_INTF", 0x50314, 0 },
+		{ "BRspVld", 31, 1 },
+		{ "BRspRdy", 30, 1 },
+		{ "BRspData", 0, 30 },
+	{ "EDC_H_DBG_EDRAM_CMD_INTF", 0x50318, 0 },
+		{ "EdramAddr", 16, 16 },
+		{ "EdramDwsn", 8, 8 },
+		{ "EdramCra", 5, 3 },
+		{ "EdramRefEnLo", 4, 1 },
+		{ "Edram1WrEnLo", 3, 1 },
+		{ "Edram1RdEnLo", 2, 1 },
+		{ "Edram0WrEnLo", 1, 1 },
+		{ "Edram0RdEnLo", 0, 1 },
+	{ "EDC_H_DBG_EDRAM_WDATA_INTF", 0x5031c, 0 },
+		{ "EdramWData", 9, 23 },
+		{ "EdramWByteEn", 0, 9 },
+	{ "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50320, 0 },
+	{ "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50324, 0 },
+	{ "EDC_H_DBG_MA_WR_REQ_CNT", 0x50328, 0 },
+	{ "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x5032c, 0 },
+	{ "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50330, 0 },
+	{ "EDC_H_DBG_MA_RD_REQ_CNT", 0x50334, 0 },
+	{ "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50338, 0 },
+	{ "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x5033c, 0 },
+	{ "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50340, 0 },
+	{ "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50344, 0 },
+	{ "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50348, 0 },
+	{ "EDC_H_DBG_BIST_RD_REQ_CNT", 0x5034c, 0 },
+	{ "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50350, 0 },
+	{ "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50354, 0 },
+	{ "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50358, 0 },
+	{ "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x5035c, 0 },
+	{ "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50360, 0 },
+	{ "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50364, 0 },
+	{ "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50368, 0 },
+	{ "EDC_H_DBG_EDRAM1_RMW_CNT", 0x5036c, 0 },
+	{ "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50370, 0 },
+	{ "EDC_H_DBG_FIFO_STATUS", 0x50374, 0 },
+		{ "rdtag_notfull", 17, 1 },
+		{ "rdtag_notempty", 16, 1 },
+		{ "inp_cmdq_notfull_arb", 15, 1 },
+		{ "inp_cmdq_notempty", 14, 1 },
+		{ "inp_wrdq_wrrdy", 13, 1 },
+		{ "inp_wrdq_notempty", 12, 1 },
+		{ "inp_beq_wrrdy_open", 11, 1 },
+		{ "inp_beq_notempty", 10, 1 },
+		{ "rddq_notfull_open", 9, 1 },
+		{ "rddq_rdcnt", 4, 5 },
+		{ "rdsideq_notfull", 3, 1 },
+		{ "rdsideq_notempty", 2, 1 },
+		{ "stg_cmdq_notempty", 1, 1 },
+		{ "stg_wrdq_notempty", 0, 1 },
+	{ "EDC_H_DBG_FSM_STATE", 0x50378, 0 },
+		{ "CmdSplitFsm", 3, 1 },
+		{ "CmdFsm", 0, 3 },
+	{ "EDC_H_DBG_STALL_CYCLES", 0x5037c, 0 },
+		{ "stall_rmw", 19, 1 },
+		{ "stall_edc_cmd", 18, 1 },
+		{ "dead_cycle0", 17, 1 },
+		{ "dead_cycle1", 16, 1 },
+		{ "dead_cycle0_bbi", 15, 1 },
+		{ "dead_cycle1_bbi", 14, 1 },
+		{ "dead_cycle0_max_op", 13, 1 },
+		{ "dead_cycle1_max_op", 12, 1 },
+		{ "dead_cycle0_pre_ref", 11, 1 },
+		{ "dead_cycle1_pre_ref", 10, 1 },
+		{ "dead_cycle0_post_ref", 9, 1 },
+		{ "dead_cycle1_post_ref", 8, 1 },
+		{ "dead_cycle0_rmw", 7, 1 },
+		{ "dead_cycle1_rmw", 6, 1 },
+		{ "dead_cycle0_bbi_rmw", 5, 1 },
+		{ "dead_cycle1_bbi_rmw", 4, 1 },
+		{ "dead_cycle0_pre_ref_rmw", 3, 1 },
+		{ "dead_cycle1_pre_ref_rmw", 2, 1 },
+		{ "dead_cycle0_post_ref_rmw", 1, 1 },
+		{ "dead_cycle1_post_ref_rmw", 0, 1 },
+	{ "EDC_H_DBG_CMD_QUEUE", 0x50380, 0 },
+		{ "ECmdNRE", 31, 1 },
+		{ "ECmdNRB", 30, 1 },
+		{ "ECmdWr", 29, 1 },
+		{ "ECmdLen", 22, 7 },
+		{ "ECmdAddr", 0, 22 },
+	{ "EDC_H_DBG_REFRESH", 0x50384, 0 },
+		{ "RefDone", 12, 1 },
+		{ "RefCntExpr", 11, 1 },
+		{ "RefPtr", 8, 3 },
+		{ "RefCnt", 0, 8 },
+	{ "EDC_H_BIST_CRC_SEED", 0x50400, 0 },
+	{ "EDC_H_PAR_CAUSE", 0x50404, 0 },
+		{ "STG_CMDQ_PARERR_CAUSE", 7, 1 },
+		{ "STG_WRDQ_PARERR_CAUSE", 6, 1 },
+		{ "INP_CMDQ_PARERR_CAUSE", 5, 1 },
+		{ "INP_WRDQ_PARERR_CAUSE", 4, 1 },
+		{ "INP_BEQ_PARERR_CAUSE", 3, 1 },
+		{ "ECC_CE_PAR_ENABLE_CAUSE", 2, 1 },
+		{ "ECC_UE_PAR_ENABLE_CAUSE", 1, 1 },
+		{ "RDDQ_PARERR_CAUSE", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_edc_t61_regs[] = {
+	{ "EDC_H_REF", 0x50800, 0 },
+		{ "SleepStatus", 31, 1 },
+		{ "SleepReq", 30, 1 },
+		{ "PING_PONG", 29, 1 },
+		{ "DramRefEnable", 27, 2 },
+		{ "QDR_ClkPhase", 24, 3 },
+		{ "MaxOpsPerTRC", 21, 3 },
+		{ "NumPipeStages", 19, 2 },
+		{ "EDC_INST_NUM", 18, 1 },
+		{ "ENABLE_PERF", 17, 1 },
+		{ "ECC_BYPASS", 16, 1 },
+		{ "RefFreq", 0, 16 },
+	{ "EDC_H_BIST_CMD", 0x50804, 0 },
+		{ "START_BIST", 31, 1 },
+		{ "BURST_LEN", 16, 2 },
+		{ "BIST_CMD_GAP", 8, 8 },
+		{ "BIST_OPCODE", 0, 2 },
+	{ "EDC_H_BIST_CMD_ADDR", 0x50808, 0 },
+	{ "EDC_H_BIST_CMD_LEN", 0x5080c, 0 },
+	{ "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 },
+	{ "EDC_H_BIST_USER_WDATA0", 0x50814, 0 },
+	{ "EDC_H_BIST_USER_WDATA1", 0x50818, 0 },
+	{ "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 },
+		{ "USER_DATA_MASK", 8, 9 },
+		{ "USER_DATA2", 0, 8 },
+	{ "EDC_H_BIST_NUM_ERR", 0x50820, 0 },
+	{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 },
+	{ "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 },
+	{ "EDC_H_PAR_ENABLE", 0x50870, 0 },
+		{ "ECC_UE_PAR_ENABLE", 2, 1 },
+		{ "ECC_CE_PAR_ENABLE", 1, 1 },
+		{ "PERR_PAR_ENABLE", 0, 1 },
+	{ "EDC_H_INT_ENABLE", 0x50874, 0 },
+		{ "ECC_UE_INT_ENABLE", 2, 1 },
+		{ "ECC_CE_INT_ENABLE", 1, 1 },
+		{ "PERR_INT_ENABLE", 0, 1 },
+	{ "EDC_H_INT_CAUSE", 0x50878, 0 },
+		{ "ECC_UE_INT0_CAUSE", 5, 1 },
+		{ "ECC_CE_INT0_CAUSE", 4, 1 },
+		{ "PERR_INT0_CAUSE", 3, 1 },
+		{ "ECC_UE_INT_CAUSE", 2, 1 },
+		{ "ECC_CE_INT_CAUSE", 1, 1 },
+		{ "PERR_INT_CAUSE", 0, 1 },
+	{ "EDC_H_ECC_STATUS", 0x5087c, 0 },
+		{ "ECC_CECNT", 16, 16 },
+		{ "ECC_UECNT", 0, 16 },
+	{ "EDC_H_ECC_ERR_SEL", 0x50880, 0 },
+	{ "EDC_H_ECC_ERR_ADDR", 0x50884, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 },
+	{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 },
+	{ "EDC_H_DBG_MA_CMD_INTF", 0x50b00, 0 },
+		{ "MCmdAddr", 12, 20 },
+		{ "MCmdLen", 5, 7 },
+		{ "MCmdNRE", 4, 1 },
+		{ "MCmdNRB", 3, 1 },
+		{ "MCmdWr", 2, 1 },
+		{ "MCmdRdy", 1, 1 },
+		{ "MCmdVld", 0, 1 },
+	{ "EDC_H_DBG_MA_WDATA_INTF", 0x50b04, 0 },
+		{ "MWDataVld", 31, 1 },
+		{ "MWDataRdy", 30, 1 },
+		{ "MWData", 0, 30 },
+	{ "EDC_H_DBG_MA_RDATA_INTF", 0x50b08, 0 },
+		{ "MRspVld", 31, 1 },
+		{ "MRspRdy", 30, 1 },
+		{ "MRspData", 0, 30 },
+	{ "EDC_H_DBG_BIST_CMD_INTF", 0x50b0c, 0 },
+		{ "BCmdAddr", 9, 23 },
+		{ "BCmdLen", 3, 6 },
+		{ "BCmdWr", 2, 1 },
+		{ "BCmdRdy", 1, 1 },
+		{ "BCmdVld", 0, 1 },
+	{ "EDC_H_DBG_BIST_WDATA_INTF", 0x50b10, 0 },
+		{ "BWDataVld", 31, 1 },
+		{ "BWDataRdy", 30, 1 },
+		{ "BWData", 0, 30 },
+	{ "EDC_H_DBG_BIST_RDATA_INTF", 0x50b14, 0 },
+		{ "BRspVld", 31, 1 },
+		{ "BRspRdy", 30, 1 },
+		{ "BRspData", 0, 30 },
+	{ "EDC_H_DBG_EDRAM_CMD_INTF", 0x50b18, 0 },
+		{ "EdramAddr", 16, 16 },
+		{ "EdramDwsn", 8, 8 },
+		{ "EdramCra", 5, 3 },
+		{ "EdramRefEnLo", 4, 1 },
+		{ "Edram1WrEnLo", 3, 1 },
+		{ "Edram1RdEnLo", 2, 1 },
+		{ "Edram0WrEnLo", 1, 1 },
+		{ "Edram0RdEnLo", 0, 1 },
+	{ "EDC_H_DBG_EDRAM_WDATA_INTF", 0x50b1c, 0 },
+		{ "EdramWData", 9, 23 },
+		{ "EdramWByteEn", 0, 9 },
+	{ "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50b20, 0 },
+	{ "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50b24, 0 },
+	{ "EDC_H_DBG_MA_WR_REQ_CNT", 0x50b28, 0 },
+	{ "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x50b2c, 0 },
+	{ "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50b30, 0 },
+	{ "EDC_H_DBG_MA_RD_REQ_CNT", 0x50b34, 0 },
+	{ "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50b38, 0 },
+	{ "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x50b3c, 0 },
+	{ "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50b40, 0 },
+	{ "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50b44, 0 },
+	{ "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50b48, 0 },
+	{ "EDC_H_DBG_BIST_RD_REQ_CNT", 0x50b4c, 0 },
+	{ "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50b50, 0 },
+	{ "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50b54, 0 },
+	{ "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50b58, 0 },
+	{ "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x50b5c, 0 },
+	{ "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50b60, 0 },
+	{ "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50b64, 0 },
+	{ "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50b68, 0 },
+	{ "EDC_H_DBG_EDRAM1_RMW_CNT", 0x50b6c, 0 },
+	{ "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50b70, 0 },
+	{ "EDC_H_DBG_FIFO_STATUS", 0x50b74, 0 },
+		{ "rdtag_notfull", 17, 1 },
+		{ "rdtag_notempty", 16, 1 },
+		{ "inp_cmdq_notfull_arb", 15, 1 },
+		{ "inp_cmdq_notempty", 14, 1 },
+		{ "inp_wrdq_wrrdy", 13, 1 },
+		{ "inp_wrdq_notempty", 12, 1 },
+		{ "inp_beq_wrrdy_open", 11, 1 },
+		{ "inp_beq_notempty", 10, 1 },
+		{ "rddq_notfull_open", 9, 1 },
+		{ "rddq_rdcnt", 4, 5 },
+		{ "rdsideq_notfull", 3, 1 },
+		{ "rdsideq_notempty", 2, 1 },
+		{ "stg_cmdq_notempty", 1, 1 },
+		{ "stg_wrdq_notempty", 0, 1 },
+	{ "EDC_H_DBG_FSM_STATE", 0x50b78, 0 },
+		{ "CmdSplitFsm", 3, 1 },
+		{ "CmdFsm", 0, 3 },
+	{ "EDC_H_DBG_STALL_CYCLES", 0x50b7c, 0 },
+		{ "stall_rmw", 19, 1 },
+		{ "stall_edc_cmd", 18, 1 },
+		{ "dead_cycle0", 17, 1 },
+		{ "dead_cycle1", 16, 1 },
+		{ "dead_cycle0_bbi", 15, 1 },
+		{ "dead_cycle1_bbi", 14, 1 },
+		{ "dead_cycle0_max_op", 13, 1 },
+		{ "dead_cycle1_max_op", 12, 1 },
+		{ "dead_cycle0_pre_ref", 11, 1 },
+		{ "dead_cycle1_pre_ref", 10, 1 },
+		{ "dead_cycle0_post_ref", 9, 1 },
+		{ "dead_cycle1_post_ref", 8, 1 },
+		{ "dead_cycle0_rmw", 7, 1 },
+		{ "dead_cycle1_rmw", 6, 1 },
+		{ "dead_cycle0_bbi_rmw", 5, 1 },
+		{ "dead_cycle1_bbi_rmw", 4, 1 },
+		{ "dead_cycle0_pre_ref_rmw", 3, 1 },
+		{ "dead_cycle1_pre_ref_rmw", 2, 1 },
+		{ "dead_cycle0_post_ref_rmw", 1, 1 },
+		{ "dead_cycle1_post_ref_rmw", 0, 1 },
+	{ "EDC_H_DBG_CMD_QUEUE", 0x50b80, 0 },
+		{ "ECmdNRE", 31, 1 },
+		{ "ECmdNRB", 30, 1 },
+		{ "ECmdWr", 29, 1 },
+		{ "ECmdLen", 22, 7 },
+		{ "ECmdAddr", 0, 22 },
+	{ "EDC_H_DBG_REFRESH", 0x50b84, 0 },
+		{ "RefDone", 12, 1 },
+		{ "RefCntExpr", 11, 1 },
+		{ "RefPtr", 8, 3 },
+		{ "RefCnt", 0, 8 },
+	{ "EDC_H_BIST_CRC_SEED", 0x50c00, 0 },
+	{ "EDC_H_PAR_CAUSE", 0x50c04, 0 },
+		{ "STG_CMDQ_PARERR_CAUSE", 7, 1 },
+		{ "STG_WRDQ_PARERR_CAUSE", 6, 1 },
+		{ "INP_CMDQ_PARERR_CAUSE", 5, 1 },
+		{ "INP_WRDQ_PARERR_CAUSE", 4, 1 },
+		{ "INP_BEQ_PARERR_CAUSE", 3, 1 },
+		{ "ECC_CE_PAR_ENABLE_CAUSE", 2, 1 },
+		{ "ECC_UE_PAR_ENABLE_CAUSE", 1, 1 },
+		{ "RDDQ_PARERR_CAUSE", 0, 1 },
+	{ NULL }
+};
+
+struct reg_info t7_hma_t6_regs[] = {
+	{ "HMA_TABLE_ACCESS", 0x51000, 0 },
+		{ "TRIG", 31, 1 },
+		{ "RW", 30, 1 },
+		{ "L_SEL", 0, 4 },
+	{ "HMA_TABLE_LINE0", 0x51004, 0 },
+	{ "HMA_TABLE_LINE1", 0x51008, 0 },
+	{ "HMA_TABLE_LINE1_MSB", 0x51270, 0 },
+	{ "HMA_TABLE_LINE2", 0x5100c, 0 },
+	{ "HMA_TABLE_LINE2_MSB", 0x51274, 0 },
+	{ "HMA_TABLE_LINE3", 0x51010, 0 },
+	{ "HMA_TABLE_LINE4", 0x51014, 0 },
+	{ "HMA_TABLE_LINE5", 0x51018, 0 },
+		{ "FID", 16, 11 },
+		{ "NOS", 15, 1 },
+		{ "RO", 14, 1 },
+		{ "TPH", 12, 2 },
+		{ "TPH_V", 11, 1 },
+		{ "DCA", 0, 11 },
+	{ "HMA_COOKIE", 0x5101c, 0 },
+		{ "C_REQ", 31, 1 },
+		{ "C_FID", 18, 11 },
+		{ "C_VAL", 8, 10 },
+		{ "C_SEL", 0, 4 },
+	{ "HMA_CFG", 0x51020, 0 },
+		{ "OP_MODE", 31, 1 },
+		{ "GK_Enable", 30, 1 },
+		{ "DbgCntRst", 29, 1 },
+	{ "HMA_TLB_ACCESS", 0x51028, 0 },
+		{ "TRIG", 31, 1 },
+		{ "RW", 30, 1 },
+		{ "INV_ALL", 29, 1 },
+		{ "LOCK_ENTRY", 28, 1 },
+		{ "E_SEL", 0, 5 },
+	{ "HMA_TLB_BITS", 0x5102c, 0 },
+		{ "VA", 8, 24 },
+		{ "VALID_E", 4, 1 },
+		{ "LOCK", 3, 1 },
+		{ "USED", 2, 1 },
+		{ "REGION", 0, 2 },
+	{ "HMA_TLB_DESC_0_H", 0x51030, 0 },
+	{ "HMA_TLB_DESC_0_L", 0x51034, 0 },
+	{ "HMA_TLB_DESC_1_H", 0x51038, 0 },
+	{ "HMA_TLB_DESC_1_L", 0x5103c, 0 },
+	{ "HMA_TLB_DESC_2_H", 0x51040, 0 },
+	{ "HMA_TLB_DESC_2_L", 0x51044, 0 },
+	{ "HMA_TLB_DESC_3_H", 0x51048, 0 },
+	{ "HMA_TLB_DESC_3_L", 0x5104c, 0 },
+	{ "HMA_TLB_DESC_4_H", 0x51050, 0 },
+	{ "HMA_TLB_DESC_4_L", 0x51054, 0 },
+	{ "HMA_TLB_DESC_5_H", 0x51058, 0 },
+	{ "HMA_TLB_DESC_5_L", 0x5105c, 0 },
+	{ "HMA_TLB_DESC_6_H", 0x51060, 0 },
+	{ "HMA_TLB_DESC_6_L", 0x51064, 0 },
+	{ "HMA_TLB_DESC_7_H", 0x51068, 0 },
+	{ "HMA_TLB_DESC_7_L", 0x5106c, 0 },
+	{ "HMA_REG0_MIN", 0x51070, 0 },
+		{ "ADDR0_MIN", 8, 24 },
+	{ "HMA_REG0_MAX", 0x51074, 0 },
+		{ "ADDR0_MAX", 8, 24 },
+	{ "HMA_REG0_MASK", 0x51078, 0 },
+		{ "PAGE_SIZE0", 12, 20 },
+	{ "HMA_REG0_BASE_LSB", 0x5107c, 0 },
+	{ "HMA_REG1_MIN", 0x51080, 0 },
+		{ "ADDR1_MIN", 8, 24 },
+	{ "HMA_REG1_MAX", 0x51084, 0 },
+		{ "ADDR1_MAX", 8, 24 },
+	{ "HMA_REG1_MASK", 0x51088, 0 },
+		{ "PAGE_SIZE1", 12, 20 },
+	{ "HMA_REG1_BASE_LSB", 0x5108c, 0 },
+	{ "HMA_REG2_MIN", 0x51090, 0 },
+		{ "ADDR2_MIN", 8, 24 },
+	{ "HMA_REG2_MAX", 0x51094, 0 },
+		{ "ADDR2_MAX", 8, 24 },
+	{ "HMA_REG2_MASK", 0x51098, 0 },
+		{ "PAGE_SIZE2", 12, 20 },
+	{ "HMA_REG2_BASE_LSB", 0x5109c, 0 },
+	{ "HMA_REG3_MIN", 0x510a0, 0 },
+		{ "ADDR3_MIN", 8, 24 },
+	{ "HMA_REG3_MAX", 0x510a4, 0 },
+		{ "ADDR3_MAX", 8, 24 },
+	{ "HMA_REG3_MASK", 0x510a8, 0 },
+		{ "PAGE_SIZE3", 12, 20 },
+	{ "HMA_REG3_BASE_LSB", 0x510ac, 0 },
+	{ "HMA_SW_SYNC", 0x510b0, 0 },
+		{ "ENTER_SYNC", 31, 1 },
+		{ "EXIT_SYNC", 30, 1 },
+	{ "HMA_REG0_BASE_MSB", 0x510b8, 0 },
+	{ "HMA_REG1_BASE_MSB", 0x510bc, 0 },
+	{ "HMA_REG2_BASE_MSB", 0x510c0, 0 },
+	{ "HMA_REG3_BASE_MSB", 0x510c4, 0 },
+	{ "HMA_GC_MODE_SEL", 0x510b4, 0 },
+		{ "MODE_SEL", 8, 2 },
+		{ "FLUSH_REQ", 4, 1 },
+		{ "CLEAR_REQ", 0, 1 },
+	{ "HMA_DBG_CTL", 0x51104, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG", 16, 1 },
+		{ "SEL", 0, 8 },
+	{ "HMA_DBG_DATA", 0x51108, 0 },
+	{ "HMA_PAR_ENABLE", 0x51300, 0 },
+		{ "GK_UF_PAR_ENABLE", 6, 1 },
+		{ "PCIEMST_PAR_ENABLE", 2, 1 },
+		{ "PERR_PAR_ENABLE", 0, 1 },
+	{ "HMA_INT_ENABLE", 0x51304, 0 },
+		{ "GK_UF_INT_ENABLE", 6, 1 },
+		{ "IDTF_INT_ENABLE", 5, 1 },
+		{ "OTF_INT_ENABLE", 4, 1 },
+		{ "RTF_INT_ENABLE", 3, 1 },
+		{ "PCIEMST_INT_ENABLE", 2, 1 },
+		{ "MAMST_INT_ENABLE", 1, 1 },
+		{ "PERR_INT_ENABLE", 0, 1 },
+	{ "HMA_INT_CAUSE", 0x51308, 0 },
+		{ "GK_UF_INT_CAUSE", 6, 1 },
+		{ "IDTF_INT_CAUSE", 5, 1 },
+		{ "OTF_INT_CAUSE", 4, 1 },
+		{ "RTF_INT_CAUSE", 3, 1 },
+		{ "PCIEMST_INT_CAUSE", 2, 1 },
+		{ "MAMST_INT_CAUSE", 1, 1 },
+		{ "PERR_INT_CAUSE", 0, 1 },
+	{ "HMA_MA_MST_ERR", 0x5130c, 0 },
+	{ "HMA_RTF_ERR", 0x51310, 0 },
+	{ "HMA_OTF_ERR", 0x51314, 0 },
+	{ "HMA_IDTF_ERR", 0x51318, 0 },
+	{ "HMA_EXIT_TF", 0x5131c, 0 },
+		{ "TRIG", 31, 1 },
+		{ "RTF", 30, 1 },
+		{ "OTF", 29, 1 },
+		{ "IDTF", 28, 1 },
+	{ "HMA_LOCAL_DEBUG_CFG", 0x51320, 0 },
+		{ "DEBUG_OR", 15, 1 },
+		{ "DEBUG_HI", 14, 1 },
+		{ "DEBUG_RPT", 13, 1 },
+		{ "DEBUGPAGE", 10, 3 },
+		{ "DEBUGSELH", 5, 5 },
+		{ "DEBUGSELL", 0, 5 },
+	{ "HMA_LOCAL_DEBUG_RPT", 0x51324, 0 },
+	{ "HMA_H_BIST_CMD", 0x51200, 0 },
+		{ "START_BIST", 31, 1 },
+		{ "BURST_LEN", 16, 2 },
+		{ "BIST_CMD_GAP", 8, 8 },
+		{ "BIST_OPCODE", 0, 2 },
+	{ "HMA_H_BIST_CMD_ADDR", 0x51204, 0 },
+	{ "HMA_H_BIST_CMD_LEN", 0x51208, 0 },
+	{ "HMA_H_BIST_DATA_PATTERN", 0x5120c, 0 },
+	{ "HMA_H_BIST_USER_WDATA0", 0x51210, 0 },
+	{ "HMA_H_BIST_USER_WDATA1", 0x51214, 0 },
+	{ "HMA_H_BIST_USER_WDATA2", 0x51218, 0 },
+		{ "USER_DATA_MASK", 8, 9 },
+		{ "USER_DATA2", 0, 8 },
+	{ "HMA_H_BIST_NUM_ERR", 0x5121c, 0 },
+	{ "HMA_H_BIST_ERR_FIRST_ADDR", 0x51220, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51224, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51228, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x5122c, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51230, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51234, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51238, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x5123c, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51240, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51244, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51248, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x5124c, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51250, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51254, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51258, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x5125c, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51260, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51264, 0 },
+	{ "HMA_H_BIST_STATUS_RDATA", 0x51268, 0 },
+	{ "HMA_H_BIST_CRC_SEED", 0x5126c, 0 },
+	{ NULL }
+};
+
+struct reg_info t7_gcache_regs[] = {
+	{ "GCACHE_MODE_SEL0", 0x51400, 0 },
+		{ "GC_MA_RSP", 16, 1 },
+		{ "MODE_SEL", 8, 2 },
+		{ "FLUSH_REQ", 4, 1 },
+		{ "CLEAR_REQ", 0, 1 },
+	{ "GCACHE_MEMZONE0_REGION1", 0x51404, 0 },
+		{ "REGION_EN1", 18, 1 },
+		{ "EDC_REGION1", 17, 1 },
+		{ "CACHE_REGION1", 16, 1 },
+		{ "END1", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION2", 0x51408, 0 },
+		{ "REGION_EN2", 18, 1 },
+		{ "EDC_REGION2", 17, 1 },
+		{ "CACHE_REGION2", 16, 1 },
+		{ "END2", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION3", 0x5140c, 0 },
+		{ "REGION_EN3", 18, 1 },
+		{ "EDC_REGION3", 17, 1 },
+		{ "CACHE_REGION3", 16, 1 },
+		{ "END3", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION4", 0x51410, 0 },
+		{ "REGION_EN4", 18, 1 },
+		{ "EDC_REGION4", 17, 1 },
+		{ "CACHE_REGION4", 16, 1 },
+		{ "END4", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION5", 0x51414, 0 },
+		{ "REGION_EN5", 18, 1 },
+		{ "EDC_REGION5", 17, 1 },
+		{ "CACHE_REGION5", 16, 1 },
+		{ "END5", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION6", 0x51418, 0 },
+		{ "REGION_EN6", 18, 1 },
+		{ "EDC_REGION6", 17, 1 },
+		{ "CACHE_REGION6", 16, 1 },
+		{ "END6", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION7", 0x5141c, 0 },
+		{ "REGION_EN7", 18, 1 },
+		{ "EDC_REGION7", 17, 1 },
+		{ "CACHE_REGION7", 16, 1 },
+		{ "END7", 0, 16 },
+	{ "GCACHE_MEMZONE0_REGION8", 0x51420, 0 },
+		{ "REGION_EN8", 18, 1 },
+		{ "EDC_REGION8", 17, 1 },
+		{ "CACHE_REGION8", 16, 1 },
+		{ "END8", 0, 16 },
+	{ "GCACHE_REG0_BASE_MSB", 0x51424, 0 },
+	{ "GCACHE_MEMZONE0_REGION1_MSB", 0x51428, 0 },
+	{ "GCACHE_MEMZONE0_REGION2_MSB", 0x5142c, 0 },
+	{ "GCACHE_MEMZONE0_REGION3_MSB", 0x51430, 0 },
+	{ "GCACHE_MEMZONE0_REGION4_MSB", 0x51434, 0 },
+	{ "GCACHE_MEMZONE0_REGION5_MSB", 0x51438, 0 },
+	{ "GCACHE_MEMZONE0_REGION6_MSB", 0x5143c, 0 },
+	{ "GCACHE_MEMZONE0_REGION7_MSB", 0x51440, 0 },
+	{ "GCACHE_MEMZONE0_REGION8_MSB", 0x51444, 0 },
+	{ "GCACHE_MODE_SEL1", 0x51448, 0 },
+		{ "GC_MA_RSP", 16, 1 },
+		{ "MODE_SEL", 8, 2 },
+		{ "FLUSH_REQ", 4, 1 },
+		{ "CLEAR_REQ", 0, 1 },
+	{ "GCACHE_MEMZONE1_REGION1", 0x5144c, 0 },
+		{ "REGION_EN1", 18, 1 },
+		{ "EDC_REGION1", 17, 1 },
+		{ "CACHE_REGION1", 16, 1 },
+		{ "END1", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION2", 0x51450, 0 },
+		{ "REGION_EN2", 18, 1 },
+		{ "EDC_REGION2", 17, 1 },
+		{ "CACHE_REGION2", 16, 1 },
+		{ "END2", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION3", 0x51454, 0 },
+		{ "REGION_EN3", 18, 1 },
+		{ "EDC_REGION3", 17, 1 },
+		{ "CACHE_REGION3", 16, 1 },
+		{ "END3", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION4", 0x51458, 0 },
+		{ "REGION_EN4", 18, 1 },
+		{ "EDC_REGION4", 17, 1 },
+		{ "CACHE_REGION4", 16, 1 },
+		{ "END4", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION5", 0x5145c, 0 },
+		{ "REGION_EN5", 18, 1 },
+		{ "EDC_REGION5", 17, 1 },
+		{ "CACHE_REGION5", 16, 1 },
+		{ "END5", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION6", 0x51460, 0 },
+		{ "REGION_EN6", 18, 1 },
+		{ "EDC_REGION6", 17, 1 },
+		{ "CACHE_REGION6", 16, 1 },
+		{ "END6", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION7", 0x51464, 0 },
+		{ "REGION_EN7", 18, 1 },
+		{ "EDC_REGION7", 17, 1 },
+		{ "CACHE_REGION7", 16, 1 },
+		{ "END7", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION8", 0x51468, 0 },
+		{ "REGION_EN8", 18, 1 },
+		{ "EDC_REGION8", 17, 1 },
+		{ "CACHE_REGION8", 16, 1 },
+		{ "END8", 0, 16 },
+	{ "GCACHE_MEMZONE1_REGION1_MSB", 0x5146c, 0 },
+	{ "GCACHE_MEMZONE1_REGION2_MSB", 0x51470, 0 },
+	{ "GCACHE_MEMZONE1_REGION3_MSB", 0x51474, 0 },
+	{ "GCACHE_MEMZONE1_REGION4_MSB", 0x51478, 0 },
+	{ "GCACHE_MEMZONE1_REGION5_MSB", 0x5147c, 0 },
+	{ "GCACHE_MEMZONE1_REGION6_MSB", 0x51480, 0 },
+	{ "GCACHE_MEMZONE1_REGION7_MSB", 0x51484, 0 },
+	{ "GCACHE_MEMZONE1_REGION8_MSB", 0x51488, 0 },
+	{ "GCACHE_HMA_MC1_EN", 0x5148c, 0 },
+		{ "MC1_EN", 1, 1 },
+		{ "HMA_EN", 0, 1 },
+	{ "GCACHE_P_BIST_CMD", 0x51490, 0 },
+		{ "START_BIST", 31, 1 },
+		{ "BURST_LEN", 16, 2 },
+		{ "BIST_CMD_GAP", 8, 8 },
+		{ "BIST_OPCODE", 0, 2 },
+	{ "GCACHE_P_BIST_CMD_ADDR", 0x51494, 0 },
+	{ "GCACHE_P_BIST_CMD_LEN", 0x51498, 0 },
+	{ "GCACHE_P_BIST_DATA_PATTERN", 0x5149c, 0 },
+	{ "GCACHE_P_BIST_USER_WDATA0", 0x514a0, 0 },
+	{ "GCACHE_P_BIST_USER_WDATA1", 0x514a4, 0 },
+	{ "GCACHE_P_BIST_USER_WDATA2", 0x514a8, 0 },
+		{ "USER_DATA_MASK", 8, 9 },
+		{ "USER_DATA2", 0, 8 },
+	{ "GCACHE_P_BIST_NUM_ERR", 0x514ac, 0 },
+	{ "GCACHE_P_BIST_ERR_FIRST_ADDR", 0x514b0, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514b4, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514b8, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514bc, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514c0, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514c4, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514c8, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514cc, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514d0, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514d4, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514d8, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514dc, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514e0, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514e4, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514e8, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514ec, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514f0, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514f4, 0 },
+	{ "GCACHE_P_BIST_STATUS_RDATA", 0x514f8, 0 },
+	{ "GCACHE_P_BIST_CRC_SEED", 0x514fc, 0 },
+	{ "GCACHE_CACHE_SIZE", 0x51500, 0 },
+		{ "HMA_2MB", 1, 1 },
+		{ "MC0_2MB", 0, 1 },
+	{ "GCACHE_HINT_MAPPING", 0x51504, 0 },
+		{ "CLIENT_HINT_EN", 16, 15 },
+		{ "HINT_ADDR_SPLIT_EN", 8, 1 },
+		{ "TP_HINT_HMA_MC", 2, 1 },
+		{ "CIM_HINT_HMA_MC", 1, 1 },
+		{ "LE_HINT_HMA_MC", 0, 1 },
+	{ "GCACHE_PERF_EN", 0x51508, 0 },
+		{ "PERF_CLEAR_GC1", 3, 1 },
+		{ "PERF_CLEAR_GC0", 2, 1 },
+		{ "PERF_EN_GC1", 1, 1 },
+		{ "PERF_EN_GC0", 0, 1 },
+	{ "GCACHE_PERF_GC0_RD_HIT", 0x5150c, 0 },
+	{ "GCACHE_PERF_GC1_RD_HIT", 0x51510, 0 },
+	{ "GCACHE_PERF_GC0_WR_HIT", 0x51514, 0 },
+	{ "GCACHE_PERF_GC1_WR_HIT", 0x51518, 0 },
+	{ "GCACHE_PERF_GC0_RD_MISS", 0x5151c, 0 },
+	{ "GCACHE_PERF_GC1_RD_MISS", 0x51520, 0 },
+	{ "GCACHE_PERF_GC0_WR_MISS", 0x51524, 0 },
+	{ "GCACHE_PERF_GC1_WR_MISS", 0x51528, 0 },
+	{ "GCACHE_PERF_GC0_RD_REQ", 0x5152c, 0 },
+	{ "GCACHE_PERF_GC1_RD_REQ", 0x51530, 0 },
+	{ "GCACHE_PERF_GC0_WR_REQ", 0x51534, 0 },
+	{ "GCACHE_PERF_GC1_WR_REQ", 0x51538, 0 },
+	{ "GCACHE_PAR_CAUSE", 0x5153c, 0 },
+		{ "GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE", 27, 1 },
+		{ "GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE", 26, 1 },
+		{ "GC1_WQDATA_FIFO_PERR_PAR_CAUSE", 25, 1 },
+		{ "GC0_WQDATA_FIFO_PERR_PAR_CAUSE", 24, 1 },
+		{ "GC1_RDTAG_QUEUE_PERR_PAR_CAUSE", 23, 1 },
+		{ "GC0_RDTAG_QUEUE_PERR_PAR_CAUSE", 22, 1 },
+		{ "GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE", 21, 1 },
+		{ "GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE", 20, 1 },
+		{ "GC1_RSP_PERR_PAR_CAUSE", 19, 1 },
+		{ "GC0_RSP_PERR_PAR_CAUSE", 18, 1 },
+		{ "GC1_LRU_UERR_PAR_CAUSE", 17, 1 },
+		{ "GC0_LRU_UERR_PAR_CAUSE", 16, 1 },
+		{ "GC1_TAG_UERR_PAR_CAUSE", 15, 1 },
+		{ "GC0_TAG_UERR_PAR_CAUSE", 14, 1 },
+		{ "GC1_LRU_CERR_PAR_CAUSE", 13, 1 },
+		{ "GC0_LRU_CERR_PAR_CAUSE", 12, 1 },
+		{ "GC1_TAG_CERR_PAR_CAUSE", 11, 1 },
+		{ "GC0_TAG_CERR_PAR_CAUSE", 10, 1 },
+		{ "GC1_CE_PAR_CAUSE", 9, 1 },
+		{ "GC0_CE_PAR_CAUSE", 8, 1 },
+		{ "GC1_UE_PAR_CAUSE", 7, 1 },
+		{ "GC0_UE_PAR_CAUSE", 6, 1 },
+		{ "GC1_CMD_PAR_CAUSE", 5, 1 },
+		{ "GC1_DATA_PAR_CAUSE", 4, 1 },
+		{ "GC0_CMD_PAR_CAUSE", 3, 1 },
+		{ "GC0_DATA_PAR_CAUSE", 2, 1 },
+		{ "ILLADDRACCESS1_PAR_CAUSE", 1, 1 },
+		{ "ILLADDRACCESS0_PAR_CAUSE", 0, 1 },
+	{ "GCACHE_PAR_ENABLE", 0x51540, 0 },
+		{ "GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE", 27, 1 },
+		{ "GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE", 26, 1 },
+		{ "GC1_WQDATA_FIFO_PERR_PAR_ENABLE", 25, 1 },
+		{ "GC0_WQDATA_FIFO_PERR_PAR_ENABLE", 24, 1 },
+		{ "GC1_RDTAG_QUEUE_PERR_PAR_ENABLE", 23, 1 },
+		{ "GC0_RDTAG_QUEUE_PERR_PAR_ENABLE", 22, 1 },
+		{ "GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE", 21, 1 },
+		{ "GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE", 20, 1 },
+		{ "GC1_RSP_PERR_PAR_ENABLE", 19, 1 },
+		{ "GC0_RSP_PERR_PAR_ENABLE", 18, 1 },
+		{ "GC1_LRU_UERR_PAR_ENABLE", 17, 1 },
+		{ "GC0_LRU_UERR_PAR_ENABLE", 16, 1 },
+		{ "GC1_TAG_UERR_PAR_ENABLE", 15, 1 },
+		{ "GC0_TAG_UERR_PAR_ENABLE", 14, 1 },
+		{ "GC1_LRU_CERR_PAR_ENABLE", 13, 1 },
+		{ "GC0_LRU_CERR_PAR_ENABLE", 12, 1 },
+		{ "GC1_TAG_CERR_PAR_ENABLE", 11, 1 },
+		{ "GC0_TAG_CERR_PAR_ENABLE", 10, 1 },
+		{ "GC1_CE_PAR_ENABLE", 9, 1 },
+		{ "GC0_CE_PAR_ENABLE", 8, 1 },
+		{ "GC1_UE_PAR_ENABLE", 7, 1 },
+		{ "GC0_UE_PAR_ENABLE", 6, 1 },
+		{ "GC1_CMD_PAR_ENABLE", 5, 1 },
+		{ "GC1_DATA_PAR_ENABLE", 4, 1 },
+		{ "GC0_CMD_PAR_ENABLE", 3, 1 },
+		{ "GC0_DATA_PAR_ENABLE", 2, 1 },
+		{ "ILLADDRACCESS1_PAR_ENABLE", 1, 1 },
+		{ "ILLADDRACCESS0_PAR_ENABLE", 0, 1 },
+	{ "GCACHE_INT_ENABLE", 0x51544, 0 },
+		{ "GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE", 27, 1 },
+		{ "GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE", 26, 1 },
+		{ "GC1_WQDATA_FIFO_PERR_INT_ENABLE", 25, 1 },
+		{ "GC0_WQDATA_FIFO_PERR_INT_ENABLE", 24, 1 },
+		{ "GC1_RDTAG_QUEUE_PERR_INT_ENABLE", 23, 1 },
+		{ "GC0_RDTAG_QUEUE_PERR_INT_ENABLE", 22, 1 },
+		{ "GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE", 21, 1 },
+		{ "GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE", 20, 1 },
+		{ "GC1_RSP_PERR_INT_ENABLE", 19, 1 },
+		{ "GC0_RSP_PERR_INT_ENABLE", 18, 1 },
+		{ "GC1_LRU_UERR_INT_ENABLE", 17, 1 },
+		{ "GC0_LRU_UERR_INT_ENABLE", 16, 1 },
+		{ "GC1_TAG_UERR_INT_ENABLE", 15, 1 },
+		{ "GC0_TAG_UERR_INT_ENABLE", 14, 1 },
+		{ "GC1_LRU_CERR_INT_ENABLE", 13, 1 },
+		{ "GC0_LRU_CERR_INT_ENABLE", 12, 1 },
+		{ "GC1_TAG_CERR_INT_ENABLE", 11, 1 },
+		{ "GC0_TAG_CERR_INT_ENABLE", 10, 1 },
+		{ "GC1_CE_INT_ENABLE", 9, 1 },
+		{ "GC0_CE_INT_ENABLE", 8, 1 },
+		{ "GC1_UE_INT_ENABLE", 7, 1 },
+		{ "GC0_UE_INT_ENABLE", 6, 1 },
+		{ "GC1_CMD_PAR_INT_ENABLE", 5, 1 },
+		{ "GC1_DATA_PAR_INT_ENABLE", 4, 1 },
+		{ "GC0_CMD_PAR_INT_ENABLE", 3, 1 },
+		{ "GC0_DATA_PAR_INT_ENABLE", 2, 1 },
+		{ "ILLADDRACCESS1_INT_ENABLE", 1, 1 },
+		{ "ILLADDRACCESS0_INT_ENABLE", 0, 1 },
+	{ "GCACHE_INT_CAUSE", 0x51548, 0 },
+		{ "GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE", 27, 1 },
+		{ "GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE", 26, 1 },
+		{ "GC1_WQDATA_FIFO_PERR_INT_CAUSE", 25, 1 },
+		{ "GC0_WQDATA_FIFO_PERR_INT_CAUSE", 24, 1 },
+		{ "GC1_RDTAG_QUEUE_PERR_INT_CAUSE", 23, 1 },
+		{ "GC0_RDTAG_QUEUE_PERR_INT_CAUSE", 22, 1 },
+		{ "GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE", 21, 1 },
+		{ "GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE", 20, 1 },
+		{ "GC1_RSP_PERR_INT_CAUSE", 19, 1 },
+		{ "GC0_RSP_PERR_INT_CAUSE", 18, 1 },
+		{ "GC1_LRU_UERR_INT_CAUSE", 17, 1 },
+		{ "GC0_LRU_UERR_INT_CAUSE", 16, 1 },
+		{ "GC1_TAG_UERR_INT_CAUSE", 15, 1 },
+		{ "GC0_TAG_UERR_INT_CAUSE", 14, 1 },
+		{ "GC1_LRU_CERR_INT_CAUSE", 13, 1 },
+		{ "GC0_LRU_CERR_INT_CAUSE", 12, 1 },
+		{ "GC1_TAG_CERR_INT_CAUSE", 11, 1 },
+		{ "GC0_TAG_CERR_INT_CAUSE", 10, 1 },
+		{ "GC1_CE_INT_CAUSE", 9, 1 },
+		{ "GC0_CE_INT_CAUSE", 8, 1 },
+		{ "GC1_UE_INT_CAUSE", 7, 1 },
+		{ "GC0_UE_INT_CAUSE", 6, 1 },
+		{ "GC1_CMD_PAR_INT_CAUSE", 5, 1 },
+		{ "GC1_DATA_PAR_INT_CAUSE", 4, 1 },
+		{ "GC0_CMD_PAR_INT_CAUSE", 3, 1 },
+		{ "GC0_DATA_PAR_INT_CAUSE", 2, 1 },
+		{ "ILLADDRACCESS1_INT_CAUSE", 1, 1 },
+		{ "ILLADDRACCESS0_INT_CAUSE", 0, 1 },
+	{ "GCACHE_DBG_CTL", 0x515f0, 0 },
+		{ "DATAH_SEL", 20, 1 },
+		{ "EN_DBG", 16, 1 },
+		{ "SEL", 0, 8 },
+	{ "GCACHE_DBG_DATA", 0x515f4, 0 },
+	{ "GCACHE_DBG_SEL_CTRL", 0x51550, 0 },
+		{ "SEL_OVR_EN", 31, 1 },
+		{ "DEBUG_HI", 16, 1 },
+		{ "SELH", 8, 8 },
+		{ "SELL", 0, 8 },
+	{ "GCACHE_LOCAL_DEBUG_RPT", 0x51554, 0 },
+	{ "GCACHE_DBG_ILL_ACC", 0x5155c, 0 },
+	{ "GCACHE_DBG_ILL_ADDR0", 0x51560, 0 },
+	{ "GCACHE_DBG_ILL_ADDR1", 0x51564, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_0_32", 0x51568, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_32_32", 0x5156c, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_64_32", 0x51570, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_96_32", 0x51574, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_0_64", 0x51578, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_64_64", 0x5157c, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_0_96", 0x51580, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_32_96", 0x51584, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_0_32", 0x5158c, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_32_32", 0x51590, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_64_32", 0x51594, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_96_32", 0x51598, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_0_64", 0x5159c, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_64_64", 0x515a0, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_0_96", 0x515a4, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_32_96", 0x515a8, 0 },
+	{ "GCACHE_GC0_DBG_ADDR_32_64", 0x515ac, 0 },
+	{ "GCACHE_GC1_DBG_ADDR_32_64", 0x515b0, 0 },
+	{ "GCACHE_PERF_GC0_EVICT", 0x515b4, 0 },
+	{ "GCACHE_PERF_GC1_EVICT", 0x515b8, 0 },
+	{ "GCACHE_PERF_GC0_CE_COUNT", 0x515bc, 0 },
+	{ "GCACHE_PERF_GC1_CE_COUNT", 0x515c0, 0 },
+	{ "GCACHE_PERF_GC0_UE_COUNT", 0x515c4, 0 },
+	{ "GCACHE_PERF_GC1_UE_COUNT", 0x515c8, 0 },
+	{ NULL }
+};
diff --git a/usr.sbin/cxgbetool/tcb_common.c b/usr.sbin/cxgbetool/tcb_common.c
index 53422c994584..803599696423 100644
--- a/usr.sbin/cxgbetool/tcb_common.c
+++ b/usr.sbin/cxgbetool/tcb_common.c
@@ -59,6 +59,15 @@ extern void t6_display_tcb_aux_2(_TCBVAR *tvp,int aux);
 extern void t6_display_tcb_aux_3(_TCBVAR *tvp,int aux);
 extern void t6_display_tcb_aux_4(_TCBVAR *tvp,int aux);
 
+extern _TCBVAR g_tcb_info7[];
+extern _TCBVAR g_scb_info7[];
+extern _TCBVAR g_fcb_info7[];
+extern void t7_display_tcb_aux_0(_TCBVAR *tvp,int aux);
+extern void t7_display_tcb_aux_1(_TCBVAR *tvp,int aux);
+extern void t7_display_tcb_aux_2(_TCBVAR *tvp,int aux);
+extern void t7_display_tcb_aux_3(_TCBVAR *tvp,int aux);
+extern void t7_display_tcb_aux_4(_TCBVAR *tvp,int aux);
+
 /***:-----------------------------------------------------------------------
  ***: globals
  ***:-----------------------------------------------------------------------
@@ -437,7 +446,13 @@ display_tcb_compressed(_TCBVAR *tvp,int aux)
     if      (1==aux) t6_display_tcb_aux_1(tvp,aux);
     else if (2==aux) t6_display_tcb_aux_2(tvp,aux);
     else if (3==aux) t6_display_tcb_aux_3(tvp,aux);
-    else if (4==aux) t6_display_tcb_aux_4(tvp,aux); 
+    else if (4==aux) t6_display_tcb_aux_4(tvp,aux);
+  } else if (g_tN==7) {
+    t7_display_tcb_aux_0(tvp,aux);
+    if      (1==aux) t7_display_tcb_aux_1(tvp,aux);
+    else if (2==aux) t7_display_tcb_aux_2(tvp,aux);
+    else if (3==aux) t7_display_tcb_aux_3(tvp,aux);
+    else if (4==aux) t7_display_tcb_aux_4(tvp,aux);
   }
 }
 
@@ -692,6 +707,11 @@ set_tcb_info(unsigned int tidtype, unsigned int cardtype)
         g_scb_info = g_scb_info6;
         g_fcb_info = g_fcb_info6;
     }
+    else if (7 == g_tN) {
+        g_tcb_info = g_tcb_info7;
+        g_scb_info = g_scb_info7;
+        g_fcb_info = g_fcb_info7;
+    }
 }
 
 void
diff --git a/usr.sbin/cxgbetool/tcbinfot7.c b/usr.sbin/cxgbetool/tcbinfot7.c
new file mode 100644
index 000000000000..93b97bddbda6
--- /dev/null
+++ b/usr.sbin/cxgbetool/tcbinfot7.c
@@ -0,0 +1,1512 @@
+/* Auto-generated file.  Avoid direct editing.     */
+/* Edits will be lost when file regenerated.       */
+/* See tcb_common.c for auto-generation commands.  */
+#include <stdio.h>
+#include "tcb_common.h"
+_TCBVAR g_tcb_info7[]={
+  {"ulp_type"                     , 0,    0,    3, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "ulp_type"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "ULP mode: 0 =toe, 2=iscsi, 4=rdma, 5=ddp, 6=fcoe, 7=user, 8=tls, 9=dtls, remaining values reserved", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"ulp_raw"                      , 0,    4,   11, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "ulp"                          , /* aka */
+   COMP_ULP                       , /* comp */
+   "ULP subtype", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"l2t_ix"                       , 0,   12,   23, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "l2t_ix"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   "Destination MAC address index", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"smac_sel"                     , 0,   24,   31, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "smac_sel"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "Source MAC address index", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_MIGRATING"                 , 0,   32,   32, /* name,aux,lo,hi */
+   "t_flags"                      ,        0,   0, /* faka,flo,fhi */
+   "migrating"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_NON_OFFLOAD"               , 0,   33,   33, /* name,aux,lo,hi */
+   "t_flags"                      ,        1,   1, /* faka,flo,fhi */
+   "non_offload"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_LOCK_TID"                  , 0,   34,   34, /* name,aux,lo,hi */
+   "t_flags"                      ,        2,   2, /* faka,flo,fhi */
+   "lock_tid"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_KEEPALIVE"                 , 0,   35,   35, /* name,aux,lo,hi */
+   "t_flags"                      ,        3,   3, /* faka,flo,fhi */
+   "keepalive"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DACK"                      , 0,   36,   36, /* name,aux,lo,hi */
+   "t_flags"                      ,        4,   4, /* faka,flo,fhi */
+   "dack"                         , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DACK_MSS"                  , 0,   37,   37, /* name,aux,lo,hi */
+   "t_flags"                      ,        5,   5, /* faka,flo,fhi */
+   "dack_mss"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DACK_NOT_ACKED"            , 0,   38,   38, /* name,aux,lo,hi */
+   "t_flags"                      ,        6,   6, /* faka,flo,fhi */
+   "dack_not_acked"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_NAGLE"                     , 0,   39,   39, /* name,aux,lo,hi */
+   "t_flags"                      ,        7,   7, /* faka,flo,fhi */
+   "nagle"                        , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_SSWS_DISABLED"             , 0,   40,   40, /* name,aux,lo,hi */
+   "t_flags"                      ,        8,   8, /* faka,flo,fhi */
+   "ssws_disabled"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RX_FLOW_CONTROL_DDP"       , 0,   41,   41, /* name,aux,lo,hi */
+   "t_flags"                      ,        9,   9, /* faka,flo,fhi */
+   "rx_flow_control_ddp"          , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RX_FLOW_CONTROL_DISABLE"   , 0,   42,   42, /* name,aux,lo,hi */
+   "t_flags"                      ,       10,  10, /* faka,flo,fhi */
+   "rx_flow_control_disable"      , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RESERVED"                  , 0,   43,   43, /* name,aux,lo,hi */
+   "t_flags"                      ,       11,  11, /* faka,flo,fhi */
+   "reserved"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CHANNEL"                   , 0,   44,   45, /* name,aux,lo,hi */
+   "t_flags"                      ,       12,  13, /* faka,flo,fhi */
+   "channel"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CHANNEL_MSB"               , 0,   45,   45, /* name,aux,lo,hi */
+   "t_flags"                      ,       13,  13, /* faka,flo,fhi */
+   "channel_msb"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TX_QUIESCE"                , 0,   46,   46, /* name,aux,lo,hi */
+   "t_flags"                      ,       14,  14, /* faka,flo,fhi */
+   "tx_quiesce"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RX_QUIESCE"                , 0,   47,   47, /* name,aux,lo,hi */
+   "t_flags"                      ,       15,  15, /* faka,flo,fhi */
+   "rx_quiesce"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TX_PACE_AUTO"              , 0,   48,   48, /* name,aux,lo,hi */
+   "t_flags"                      ,       16,  16, /* faka,flo,fhi */
+   "tx_pace_auto"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TX_PACE_FIXED"             , 0,   49,   49, /* name,aux,lo,hi */
+   "t_flags"                      ,       17,  17, /* faka,flo,fhi */
+   "tx_pace_fixed"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TX_QUEUE"                  , 0,   50,   52, /* name,aux,lo,hi */
+   "t_flags"                      ,       18,  20, /* faka,flo,fhi */
+   "tx_queue"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TURBO"                     , 0,   53,   53, /* name,aux,lo,hi */
+   "t_flags"                      ,       21,  21, /* faka,flo,fhi */
+   "turbo"                        , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CCTRL_SEL0"                , 0,   54,   54, /* name,aux,lo,hi */
+   "t_flags"                      ,       22,  22, /* faka,flo,fhi */
+   "cctrl_sel0"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CCTRL_SEL1"                , 0,   55,   55, /* name,aux,lo,hi */
+   "t_flags"                      ,       23,  23, /* faka,flo,fhi */
+   "cctrl_sel1"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CORE_FIN"                  , 0,   56,   56, /* name,aux,lo,hi */
+   "t_flags"                      ,       24,  24, /* faka,flo,fhi */
+   "core_fin"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CORE_URG"                  , 0,   57,   57, /* name,aux,lo,hi */
+   "t_flags"                      ,       25,  25, /* faka,flo,fhi */
+   "core_urg"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CORE_MORE"                 , 0,   58,   58, /* name,aux,lo,hi */
+   "t_flags"                      ,       26,  26, /* faka,flo,fhi */
+   "core_more"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CORE_PUSH"                 , 0,   59,   59, /* name,aux,lo,hi */
+   "t_flags"                      ,       27,  27, /* faka,flo,fhi */
+   "core_push"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CORE_FLUSH"                , 0,   60,   60, /* name,aux,lo,hi */
+   "t_flags"                      ,       28,  28, /* faka,flo,fhi */
+   "core_flush"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RCV_COALESCE_ENABLE"       , 0,   61,   61, /* name,aux,lo,hi */
+   "t_flags"                      ,       29,  29, /* faka,flo,fhi */
+   "rcv_coalesce_enable"          , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RCV_COALESCE_PUSH"         , 0,   62,   62, /* name,aux,lo,hi */
+   "t_flags"                      ,       30,  30, /* faka,flo,fhi */
+   "rcv_coalesce_push"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RCV_COALESCE_LAST_PSH"     , 0,   63,   63, /* name,aux,lo,hi */
+   "t_flags"                      ,       31,  31, /* faka,flo,fhi */
+   "rcv_coalesce_last_psh"        , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RCV_COALESCE_HEARTBEAT"    , 0,   64,   64, /* name,aux,lo,hi */
+   "t_flags"                      ,       32,  32, /* faka,flo,fhi */
+   "rcv_coalesce_heartbeat"       , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RSS_FW"                    , 0,   65,   65, /* name,aux,lo,hi */
+   "t_flags"                      ,       33,  33, /* faka,flo,fhi */
+   "rss_fw"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_ACTIVE_OPEN"               , 0,   66,   66, /* name,aux,lo,hi */
+   "t_flags"                      ,       34,  34, /* faka,flo,fhi */
+   "active_open"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_ASK_MODE"                  , 0,   67,   67, /* name,aux,lo,hi */
+   "t_flags"                      ,       35,  35, /* faka,flo,fhi */
+   "ask_mode"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_MOD_SCHD_REASON0"          , 0,   68,   68, /* name,aux,lo,hi */
+   "t_flags"                      ,       36,  36, /* faka,flo,fhi */
+   "mod_schd_reason0"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_MOD_SCHD_REASON1"          , 0,   69,   69, /* name,aux,lo,hi */
+   "t_flags"                      ,       37,  37, /* faka,flo,fhi */
+   "mod_schd_reason1"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_MOD_SCHD_REASON2"          , 0,   70,   70, /* name,aux,lo,hi */
+   "t_flags"                      ,       38,  38, /* faka,flo,fhi */
+   "mod_schd_reason2"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_MOD_SCHD_TX"               , 0,   71,   71, /* name,aux,lo,hi */
+   "t_flags"                      ,       39,  39, /* faka,flo,fhi */
+   "mod_schd_tx"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_MOD_SCHD_RX"               , 0,   72,   72, /* name,aux,lo,hi */
+   "t_flags"                      ,       40,  40, /* faka,flo,fhi */
+   "mod_schd_rx"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TIMER"                     , 0,   73,   73, /* name,aux,lo,hi */
+   "t_flags"                      ,       41,  41, /* faka,flo,fhi */
+   "timer"                        , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DACK_TIMER"                , 0,   74,   74, /* name,aux,lo,hi */
+   "t_flags"                      ,       42,  42, /* faka,flo,fhi */
+   "dack_timer"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_PEER_FIN"                  , 0,   75,   75, /* name,aux,lo,hi */
+   "t_flags"                      ,       43,  43, /* faka,flo,fhi */
+   "peer_fin"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TX_COMPACT"                , 0,   76,   76, /* name,aux,lo,hi */
+   "t_flags"                      ,       44,  44, /* faka,flo,fhi */
+   "tx_compact"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RX_COMPACT"                , 0,   77,   77, /* name,aux,lo,hi */
+   "t_flags"                      ,       45,  45, /* faka,flo,fhi */
+   "rx_compact"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RDMA_ERROR"                , 0,   78,   78, /* name,aux,lo,hi */
+   "t_flags"                      ,       46,  46, /* faka,flo,fhi */
+   "rdma_error"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RDMA_FLM_ERROR"            , 0,   79,   79, /* name,aux,lo,hi */
+   "t_flags"                      ,       47,  47, /* faka,flo,fhi */
+   "rdma_flm_error"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TX_PDU_OUT"                , 0,   80,   80, /* name,aux,lo,hi */
+   "t_flags"                      ,       48,  48, /* faka,flo,fhi */
+   "tx_pdu_out"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RX_PDU_OUT"                , 0,   81,   81, /* name,aux,lo,hi */
+   "t_flags"                      ,       49,  49, /* faka,flo,fhi */
+   "rx_pdu_out"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DUPACK_COUNT_ODD"          , 0,   82,   82, /* name,aux,lo,hi */
+   "t_flags"                      ,       50,  50, /* faka,flo,fhi */
+   "dupack_count_odd"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_FAST_RECOVERY"             , 0,   83,   83, /* name,aux,lo,hi */
+   "t_flags"                      ,       51,  51, /* faka,flo,fhi */
+   "fast_recovery"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RECV_SCALE"                , 0,   84,   84, /* name,aux,lo,hi */
+   "t_flags"                      ,       52,  52, /* faka,flo,fhi */
+   "recv_scale"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RECV_TSTMP"                , 0,   85,   85, /* name,aux,lo,hi */
+   "t_flags"                      ,       53,  53, /* faka,flo,fhi */
+   "recv_tstmp"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_RECV_SACK"                 , 0,   86,   86, /* name,aux,lo,hi */
+   "t_flags"                      ,       54,  54, /* faka,flo,fhi */
+   "recv_sack"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_PEND_CTL0"                 , 0,   87,   87, /* name,aux,lo,hi */
+   "t_flags"                      ,       55,  55, /* faka,flo,fhi */
+   "pend_ctl0"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_PEND_CTL1"                 , 0,   88,   88, /* name,aux,lo,hi */
+   "t_flags"                      ,       56,  56, /* faka,flo,fhi */
+   "pend_ctl1"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_PEND_CTL2"                 , 0,   89,   89, /* name,aux,lo,hi */
+   "t_flags"                      ,       57,  57, /* faka,flo,fhi */
+   "pend_ctl2"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_IP_VERSION"                , 0,   90,   90, /* name,aux,lo,hi */
+   "t_flags"                      ,       58,  58, /* faka,flo,fhi */
+   "ip_version"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CCTRL_ECN"                 , 0,   91,   91, /* name,aux,lo,hi */
+   "t_flags"                      ,       59,  59, /* faka,flo,fhi */
+   "cctrl_ecn"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CCTRL_ECE"                 , 0,   92,   92, /* name,aux,lo,hi */
+   "t_flags"                      ,       60,  60, /* faka,flo,fhi */
+   "cctrl_ece"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CCTRL_CWR"                 , 0,   93,   93, /* name,aux,lo,hi */
+   "t_flags"                      ,       61,  61, /* faka,flo,fhi */
+   "cctrl_cwr"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CCTRL_RFR"                 , 0,   94,   94, /* name,aux,lo,hi */
+   "t_flags"                      ,       62,  62, /* faka,flo,fhi */
+   "cctrl_rfr"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_CORE_BYPASS"               , 0,   95,   95, /* name,aux,lo,hi */
+   "t_flags"                      ,       63,  63, /* faka,flo,fhi */
+   "core_bypass"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rss_info"                     , 0,   96,  105, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rss_info"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "RSS field", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tos"                          , 0,  106,  111, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tos"                          , /* aka */
+   COMP_NONE                      , /* comp */
+   "TOS field for IP header", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_state"                      , 0,  112,  115, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_state"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "Connection TCP state (see TCP state table)", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"max_rt"                       , 0,  116,  119, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "max_rt"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   "Maximum re-transmissions", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_maxseg"                     , 0,  120,  123, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_maxseg"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "MTU table index", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"snd_scale"                    , 0,  124,  127, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_scale"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   "Scaling for receive window (0-14). Note: this is reverse of common definition.", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rcv_scale"                    , 0,  128,  131, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rcv_scale"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   "Scaling for send window (0-14). Note: this is reverse of common definition.", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_rxtshift"                   , 0,  132,  135, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_rxtshift"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   "Retransmit exponential backoff", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_dupacks"                    , 0,  136,  139, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_dupacks"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   "Number of duplicate ACKs received", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"timestamp_offset"             , 0,  140,  143, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "timestamp_offset"             , /* aka */
+   COMP_NONE                      , /* comp */
+   "Timestamp offset from running clock", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rcv_adv"                      , 0,  144,  159, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rcv_adv"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "Peer advertised window", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"timestamp"                    , 0,  160,  191, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "timestamp"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   "Timer accounting field", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_rtt_ts_recent_age"          , 0,  192,  223, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_rtt_ts_recent_age"          , /* aka */
+   COMP_NONE                      , /* comp */
+   "Round-trip time; timestamps: ts_recent_age", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_rtseq_recent"               , 0,  224,  255, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_rtseq_recent"               , /* aka */
+   COMP_NONE                      , /* comp */
+   "Sequence number being timed t_rtseq; timestamps t_recent", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_srtt"                       , 0,  256,  271, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_srtt"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   "Smoothed round-trip time", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"t_rttvar"                     , 0,  272,  287, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "t_rttvar"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "Variance in round-trip time", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_max"                       , 0,  288,  319, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_max"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   "Highest sequence number in transmit buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"snd_una_raw"                  , 0,  320,  347, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_una"                      , /* aka */
+   COMP_TX_MAX                    , /* comp */
+   "Offset of snd_una from tx_max", /*desc*/
+    "Send unacknowledged", /*akadesc */
+  },
+  {"snd_nxt_raw"                  , 0,  348,  375, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_nxt"                      , /* aka */
+   COMP_TX_MAX                    , /* comp */
+   "Offset of snd_nxt from tx_max", /*desc*/
+    "Send next", /*akadesc */
+  },
+  {"snd_max_raw"                  , 0,  376,  403, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_max"                      , /* aka */
+   COMP_TX_MAX                    , /* comp */
+   "Offset of snd_max from tx_max", /*desc*/
+    "Highest sequence number sent", /*akadesc */
+  },
+  {"snd_rec_raw"                  , 0,  404,  431, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_rec"                      , /* aka */
+   COMP_TX_MAX                    , /* comp */
+   "Offset of NewReno fast recovery end sequence from tx_max", /*desc*/
+    "NewReno fast recovery end sequence number", /*akadesc */
+  },
+  {"snd_cwnd"                     , 0,  432,  459, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_cwnd"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "Congestion-control window", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"snd_ssthresh"                 , 0,  460,  487, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "snd_ssthresh"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   "Slow Start threshold", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_hdr_ptr_raw"               , 0,  488,  504, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_hdr_ptr"                   , /* aka */
+   COMP_PTR                       , /* comp */
+   "Page pointer for first byte in send buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_last_ptr_raw"              , 0,  505,  521, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_last_ptr"                  , /* aka */
+   COMP_PTR                       , /* comp */
+   "Page pointer for last byte in send buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rcv_nxt"                      , 0,  522,  553, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rcv_nxt"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "TCP receive next", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rcv_wnd"                      , 0,  554,  581, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rcv_wnd"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "Receive credits (advertised to peer in receive window)", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_hdr_offset"                , 0,  582,  609, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_hdr_offset"                , /* aka */
+   COMP_NONE                      , /* comp */
+   "Receive in-order buffered data", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"ts_last_ack_sent_raw"         , 0,  610,  637, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "ts_last_ack_sent"             , /* aka */
+   COMP_RCV_NXT                   , /* comp */
+   "Offset of highest sequence acked from rcv_nxt", /*desc*/
+    "Highest sequence number acked", /*akadesc */
+  },
+  {"rx_frag0_start_idx_raw"       , 0,  638,  665, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag0_start_idx"           , /* aka */
+   COMP_RCV_NXT                   , /* comp */
+   "Offset of receive fragment 0 start sequence from rcv_nxt", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag1_start_idx_offset"    , 0,  666,  693, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag1_start_idx_offset"    , /* aka */
+   COMP_RCV_NXT                   , /* comp */
+   "Offset of receive fragment 1 start sequence from rcv_nxt", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag0_len"                 , 0,  694,  721, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag0_len"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   "Receive re-order fragment 0 length", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag1_len"                 , 0,  722,  749, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag1_len"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   "Receive re-order fragment 1 length", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"pdu_len"                      , 0,  750,  765, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "pdu_len"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "Receive recovered PDU length", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_ptr_raw"                   , 0,  766,  782, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ptr"                       , /* aka */
+   COMP_PTR                       , /* comp */
+   "Page pointer for in-order receive buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag1_ptr_raw"             , 0,  783,  799, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag1_ptr"                 , /* aka */
+   COMP_PTR                       , /* comp */
+   "Page pointer for out-of-order receive buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"main_slush"                   , 0,  800,  831, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "main_slush"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   "Reserved", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"aux1_slush0"                  , 1,  832,  846, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "aux1_slush0"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   "Reserved", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag2_start_idx_offset_raw", 1,  847,  874, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag2_start_idx_offset"    , /* aka */
+   COMP_RCV_NXT                   , /* comp */
+   "Offset of receive fragment 2 start sequence from rcv_nxt", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag2_ptr_raw"             , 1,  875,  891, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag2_ptr"                 , /* aka */
+   COMP_PTR                       , /* comp */
+   "Page pointer for out-of-order receive buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag2_len_raw"             , 1,  892,  919, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag2_len"                 , /* aka */
+   COMP_LEN                       , /* comp */
+   "Receive re-order fragment 2 length", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag3_ptr_raw"             , 1,  920,  936, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag3_ptr"                 , /* aka */
+   COMP_PTR                       , /* comp */
+   "Page pointer for out-of-order receive buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag3_len_raw"             , 1,  937,  964, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag3_len"                 , /* aka */
+   COMP_LEN                       , /* comp */
+   "Receive re-order fragment 3 length", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_frag3_start_idx_offset_raw", 1,  965,  992, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_frag3_start_idx_offset"    , /* aka */
+   COMP_RCV_NXT                   , /* comp */
+   "Offset of receive fragment 3 start sequence from rcv_nxt", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"pdu_hdr_len"                  , 1,  993, 1000, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "pdu_hdr_len"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   "Receive recovered PDU header length", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"aux1_slush1"                  , 1, 1001, 1019, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "aux1_slush1"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   "Reserved", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"ulp_ext"                      , 1, 1020, 1023, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "ulp_ext"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "Extension of ulp_raw for PI configuration", /*desc*/
+    NULL, /*akadesc */
+  },
+
+  {"irs_ulp"                      , 2,  832,  840, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "irs_ulp"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "IRS modulo marker_interval when enterring iWARP mode", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"iss_ulp"                      , 2,  841,  849, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "iss_ulp"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   "ISS modulo marker_interval when entering iWARP mode", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_pdu_len"                   , 2,  850,  863, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_pdu_len"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   "Length of Tx FPDU", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"cq_idx_sq"                    , 2,  864,  879, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "cq_idx_sq"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   "CQ index of CQ for SQ", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"cq_idx_rq"                    , 2,  880,  895, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "cq_idx_rq"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   "CQ index of CQ for RQ", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"qp_id"                        , 2,  896,  911, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "qp_id"                        , /* aka */
+   COMP_NONE                      , /* comp */
+   "QP index", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"pd_id"                        , 2,  912,  927, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "pd_id"                        , /* aka */
+   COMP_NONE                      , /* comp */
+   "PD index", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"STAG"                         , 2,  928,  959, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "stag"                         , /* aka */
+   COMP_NONE                      , /* comp */
+   "PDU response STAG", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rq_start"                     , 2,  960,  985, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rq_start"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "DW aligned starting addres of RQ", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rq_MSN"                       , 2,  986,  998, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rq_msn"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   "Current MSN (modulo 8K, further check in ULP_RX)", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rq_max_offset"                , 2,  999, 1002, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rq_max_offset"                , /* aka */
+   COMP_NONE                      , /* comp */
+   "Log size RQ (the size in hardware is rounded up to a power of 2)", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rq_write_ptr"                 , 2, 1003, 1015, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rq_write_ptr"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   "Host RQ write pointer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"RDMAP_opcode"                 , 2, 1016, 1019, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rdmap_opcode"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   "Current FPDU command", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"ord_L_bit_vld"                , 2, 1020, 1020, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "ord_l_bit_vld"                , /* aka */
+   COMP_NONE                      , /* comp */
+   "Current FPDU has L-bit set", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_flush"                     , 2, 1021, 1021, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_flush"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   "1 = flush CPL_TX_DATA", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_oos_rxmt"                  , 2, 1022, 1022, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_oos_rxmt"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   "Retransmit is out of FPDU sync", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"tx_oos_txmt"                  , 2, 1023, 1023, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "tx_oos_txmt"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   "Transmit is out of FPDU sync, or disable aligned transmission", /*desc*/
+    NULL, /*akadesc */
+  },
+
+  {"rx_ddp_buf0_offset"           , 3,  832,  855, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ddp_buf0_offset"           , /* aka */
+   COMP_NONE                      , /* comp */
+   "Current offset into DDP buffer 0", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_ddp_buf0_len"              , 3,  856,  879, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ddp_buf0_len"              , /* aka */
+   COMP_NONE                      , /* comp */
+   "Length of DDP buffer 0", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_INDICATE_OUT"          , 3,  880,  880, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        0,   0, /* faka,flo,fhi */
+   "ddp_indicate_out"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_ACTIVE_BUF"            , 3,  881,  881, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        1,   1, /* faka,flo,fhi */
+   "ddp_active_buf"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_OFF"                   , 3,  882,  882, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        2,   2, /* faka,flo,fhi */
+   "ddp_off"                      , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_WAIT_FRAG"             , 3,  883,  883, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        3,   3, /* faka,flo,fhi */
+   "ddp_wait_frag"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF_INF"               , 3,  884,  884, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        4,   4, /* faka,flo,fhi */
+   "ddp_buf_inf"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_RX2TX"                 , 3,  885,  885, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        5,   5, /* faka,flo,fhi */
+   "ddp_rx2tx"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_INDICATE_FLL"          , 3,  886,  886, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        6,   6, /* faka,flo,fhi */
+   "ddp_indicate_fll"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_MAIN_UNUSED"           , 3,  887,  887, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        7,   7, /* faka,flo,fhi */
+   "ddp_main_unused"              , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_TLS_KEY_MODE"              , 3,  887,  887, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        7,   7, /* faka,flo,fhi */
+   "tls_key_mode"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF0_VALID"            , 3,  888,  888, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        8,   8, /* faka,flo,fhi */
+   "ddp_buf0_valid"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF0_INDICATE"         , 3,  889,  889, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,        9,   9, /* faka,flo,fhi */
+   "ddp_buf0_indicate"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF0_FLUSH"            , 3,  890,  890, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       10,  10, /* faka,flo,fhi */
+   "ddp_buf0_flush"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_PSHF_ENABLE_0"         , 3,  891,  891, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       11,  11, /* faka,flo,fhi */
+   "ddp_pshf_enable_0"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_PUSH_DISABLE_0"        , 3,  892,  892, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       12,  12, /* faka,flo,fhi */
+   "ddp_push_disable_0"           , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_PSH_NO_INVALIDATE0"    , 3,  893,  893, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       13,  13, /* faka,flo,fhi */
+   "ddp_psh_no_invalidate0"       , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF0_UNUSED"           , 3,  894,  895, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       14,  15, /* faka,flo,fhi */
+   "ddp_buf0_unused"              , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF1_VALID"            , 3,  896,  896, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       16,  16, /* faka,flo,fhi */
+   "ddp_buf1_valid"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF1_INDICATE"         , 3,  897,  897, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       17,  17, /* faka,flo,fhi */
+   "ddp_buf1_indicate"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF1_FLUSH"            , 3,  898,  898, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       18,  18, /* faka,flo,fhi */
+   "ddp_buf1_flush"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_PSHF_ENABLE_1"         , 3,  899,  899, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       19,  19, /* faka,flo,fhi */
+   "ddp_pshf_enable_1"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_PUSH_DISABLE_1"        , 3,  900,  900, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       20,  20, /* faka,flo,fhi */
+   "ddp_push_disable_1"           , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_PSH_NO_INVALIDATE1"    , 3,  901,  901, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       21,  21, /* faka,flo,fhi */
+   "ddp_psh_no_invalidate1"       , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"TF_DDP_BUF1_UNUSED"           , 3,  902,  903, /* name,aux,lo,hi */
+   "rx_ddp_flags"                 ,       22,  23, /* faka,flo,fhi */
+   "ddp_buf1_unused"              , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_ddp_buf1_offset"           , 3,  904,  927, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ddp_buf1_offset"           , /* aka */
+   COMP_NONE                      , /* comp */
+   "Current offset into DDP buffer 1", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_ddp_buf1_len"              , 3,  928,  951, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ddp_buf1_len"              , /* aka */
+   COMP_NONE                      , /* comp */
+   "Length of DDP buffer 1", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"aux3_slush"                   , 3,  952,  959, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "aux3_slush"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   "Reserved", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_ddp_buf0_tag"              , 3,  960,  991, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ddp_buf0_tag"              , /* aka */
+   COMP_NONE                      , /* comp */
+   "Tag for DDP buffer 0", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_ddp_buf1_tag"              , 3,  992, 1023, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_ddp_buf1_tag"              , /* aka */
+   COMP_NONE                      , /* comp */
+   "Tag for DDP buffer 1", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_tls_buf_offset"            , 4,  832,  855, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_tls_buf_offset"            , /* aka */
+   COMP_NONE                      , /* comp */
+   "Current offset into DDP buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_tls_buf_len"               , 4,  856,  879, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_tls_buf_len"               , /* aka */
+   COMP_NONE                      , /* comp */
+   "Length of DDP buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_tls_flags"                 , 4,  880,  895, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_tls_flags"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   "DDP control flags", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_tls_seq"                   , 4,  896,  959, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_tls_seq"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   "TLS/SSL sequence number", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_tls_buf_tag"               , 4,  960,  991, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_tls_buf_tag"               , /* aka */
+   COMP_NONE                      , /* comp */
+   "Tag for DDP buffer", /*desc*/
+    NULL, /*akadesc */
+  },
+  {"rx_tls_key_tag"               , 4,  992, 1023, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "rx_tls_key_tag"               , /* aka */
+   COMP_NONE                      , /* comp */
+   "Tag for TLS crypto state", /*desc*/
+    NULL, /*akadesc */
+  },
+  {NULL,0,0,0,  NULL,0,0, NULL, 0, NULL, NULL}, /*terminator*/
+};
+
+/* ====================================================== */
+_TCBVAR g_scb_info7[]={
+  {"OPT_1_RSS_INFO"               , 0,    0,   11, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_1_RSS_INFO"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_1_LISTEN_INTERFACE"       , 0,   12,   19, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_1_LISTEN_INTERFACE"       , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_1_LISTEN_FILTER"          , 0,   20,   20, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_1_LISTEN_FILTER"          , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_1_SYN_DEFENSE"            , 0,   21,   21, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_1_SYN_DEFENSE"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_1_CONNECTION_POLICY"      , 0,   22,   23, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_1_CONNECTION_POLICY"      , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_1_FLT_INFO"               , 0,   24,   63, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_1_FLT_INFO"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_ACCEPT_MODE"            , 0,   64,   65, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_ACCEPT_MODE"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_CHANNEL"                , 0,   66,   67, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_CHANNEL"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_NO_CONGESTION_CONTROL"  , 0,   68,   68, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_NO_CONGESTION_CONTROL"  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_DELAYED_ACK"            , 0,   69,   69, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_DELAYED_ACK"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_INJECT_TIMER"           , 0,   70,   70, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_INJECT_TIMER"           , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_NON_OFFLOAD"            , 0,   71,   71, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_NON_OFFLOAD"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_ULP_MODE"               , 0,   72,   75, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_ULP_MODE"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_MAX_RCV_BUFFER"         , 0,   76,   85, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_MAX_RCV_BUFFER"         , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_TOS"                    , 0,   86,   91, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_TOS"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_SM_SEL"                 , 0,   92,   99, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_SM_SEL"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_L2T_IX"                 , 0,  100,  111, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_L2T_IX"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_TCAM_BYPASS"            , 0,  112,  112, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_TCAM_BYPASS"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_NAGLE"                  , 0,  113,  113, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_NAGLE"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_WSF"                    , 0,  114,  117, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_WSF"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_KEEPALIVE"              , 0,  118,  118, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_KEEPALIVE"              , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_CONN_MAXRT"             , 0,  119,  122, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_CONN_MAXRT"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_MAXRT_OVERRIDE"         , 0,  123,  123, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_MAXRT_OVERRIDE"         , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"OPT_0_MAX_SEG"                , 0,  124,  127, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "OPT_0_MAX_SEG"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"scb_slush"                    , 0,  128, 1023, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "scb_slush"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {NULL,0,0,0,  NULL,0,0, NULL, 0, NULL, NULL}, /*terminator*/
+};
+
+/* ====================================================== */
+_TCBVAR g_fcb_info7[]={
+  {"filter"                       , 0,   33,   33, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "filter"                       , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Drop_Encapsulation_Headers"   , 0,   35,   35, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Drop_Encapsulation_Headers"   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Report_TID"                   , 0,   53,   53, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Report_TID"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Drop"                         , 0,   54,   54, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Drop"                         , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Direct_Steer"                 , 0,   55,   55, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Direct_Steer"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Mask_Hash"                    , 0,   48,   48, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Mask_Hash"                    , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Direct_Steer_Hash"            , 0,   49,   49, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Direct_Steer_Hash"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Loopback"                     , 0,   91,   91, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Loopback"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Loopback_TX_Channel"          , 0,   44,   45, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Loopback_TX_Channel"          , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Loopback_TX_Loopback"         , 0,   85,   85, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Loopback_TX_Loopback"         , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Swap_MAC_addresses"           , 0,   86,   86, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Swap_MAC_addresses"           , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Rewrite_DMAC"                 , 0,   92,   92, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Rewrite_DMAC"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Rewrite_SMAC"                 , 0,   93,   93, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Rewrite_SMAC"                 , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Insert_VLAN"                  , 0,   94,   94, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Insert_VLAN"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Remove_VLAN"                  , 0,   39,   39, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Remove_VLAN"                  , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"NAT_Mode"                     , 0,   50,   52, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "NAT_Mode"                     , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"NAT_seq_check"                , 0,   42,   42, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "NAT_seq_check"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"NAT_flag_check"               , 0,   84,   84, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "NAT_flag_check"               , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Count_Hits"                   , 0,   36,   36, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Count_Hits"                   , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Hit_frame_cnt"                , 0,  160,  191, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Hit_frame_cnt"                , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Hit_byte_cnt_high"            , 0,  224,  255, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Hit_byte_cnt_high"            , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {"Hit_byte_cnt_low"             , 0,  192,  223, /* name,aux,lo,hi */
+   NULL                           ,        0,   0, /* faka,flo,fhi */
+   "Hit_byte_cnt_low"             , /* aka */
+   COMP_NONE                      , /* comp */
+   NULL, /*desc*/
+    NULL, /*akadesc */
+  },
+  {NULL,0,0,0,  NULL,0,0, NULL, 0, NULL, NULL}, /*terminator*/
+};
+
diff --git a/usr.sbin/cxgbetool/tcbshowt7.c b/usr.sbin/cxgbetool/tcbshowt7.c
new file mode 100644
index 000000000000..a3397960b26b
--- /dev/null
+++ b/usr.sbin/cxgbetool/tcbshowt7.c
@@ -0,0 +1,412 @@
+/* Auto-generated file.  Avoid direct editing.     */
+/* Edits will be lost when file regenerated.       */
+/* See tcb_common.c for auto-generation commands.  */
+#include <stdio.h>
+#include "tcb_common.h"
+
+void t7_display_tcb_aux_0 (_TCBVAR *tvp, int aux)
+{
+
+
+
+
+
+
+  
+  PR("STATE:\n");
+  PR("  %-12s (%-2u), %s, lock_tid %u, rss_fw %u\n",
+	      spr_tcp_state(val("t_state")), 
+	      val("t_state"),
+	      spr_ip_version(val("ip_version")),
+	      val("lock_tid"),
+	      val("rss_fw")
+	     );
+  PR("  l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n",
+	      val("l2t_ix"),
+	      val("smac_sel"),
+	      val("tos")
+	      );
+  PR("  maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n",
+	      val("t_maxseg"),   val("recv_scale"),
+	      val("recv_tstmp"), val("recv_sack"));
+
+
+  PR("TIMERS:\n"); /* **************************************** */
+  PR("  timer    %u,  dack_timer      %u\n", 
+	   val("timer"), val("dack_timer"));
+  PR("  mod_schd: tx: %u, rx: %u, reason 0x%1x\n", 
+	      val("mod_schd_tx"), 
+	      val("mod_schd_rx"),
+	      ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
+	       val("mod_schd_reason0"))
+	      );
+
+
+  PR("  max_rt   %-2u, rxtshift        %u, keepalive   %u\n", 
+	   val("max_rt"),  val("t_rxtshift"), 
+	   val("keepalive"));
+  PR("  timestamp_offset 0x%x,  timestamp 0x%x\n",
+	   val("timestamp_offset"),val("timestamp"));
+
+
+  PR("  t_rtt_ts_recent_age %u  t_rttseq_recent %u\n", 
+	   val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
+  PR("  t_srtt %u, t_rttvar %u\n",
+	   val("t_srtt"),val("t_rttvar"));
+
+
+
+
+
+
+  PR("TRANSMIT BUFFER:\n");   /* *************************** */
+  PR("  snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n",
+	      val("snd_una"),val("snd_nxt"),
+	      val("snd_max"),val("tx_max"));
+  PR("  core_fin %u, tx_hdr_offset %u\n",  
+	      val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
+	     );
+  if (val("recv_scale") && !val("active_open")) {
+    PR("  rcv_adv    %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n",
+		val("rcv_adv"), val("rcv_scale"), 
+		val("rcv_adv") << val("rcv_scale"), 
+		val("recv_scale"), val("rcv_scale"), val("active_open"));
+  } else {
+    PR("  rcv_adv    %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n",
+		val("rcv_adv"), val("rcv_scale"), 
+		val("recv_scale"), val("active_open"));
+  }
+  
+  PR("  snd_cwnd   %-5u  snd_ssthresh %u  snd_rec %u\n",
+	      val("snd_cwnd")    , val("snd_ssthresh"), val("snd_rec")
+	     );
+
+
+
+
+  PR("  cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n",
+	      spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
+	      val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
+	      val("cctrl_rfr"));
+  PR("  t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n",
+	      val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
+  PR("  core_more    %u, core_urg,       %u  core_push   %u,",
+	      val("core_more"),val("core_urg"),val("core_push"));
+  PR("  core_flush %u\n",val("core_flush"));
+  PR("  nagle        %u, ssws_disable    %u, turbo       %u,",
+	      val("nagle"), val("ssws_disabled"), val("turbo"));
+  PR("  tx_pdu_out %u\n",val("tx_pdu_out"));
+  PR("  tx_pace_auto %u, tx_pace_fixed   %u, tx_queue    %u",
+	      val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
+
+
+  PR("   tx_quiesce %u\n",val("tx_quiesce"));
+  PR("  channel   %u, channel_msb   %u\n",
+	      val("channel"),
+	      val("channel_msb")
+	      );
+
+
+
+
+  PR("  tx_hdr_ptr   0x%-6x   tx_last_ptr 0x%-6x  tx_compact %u\n", 
+	      val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
+
+
+
+
+  PR("RECEIVE BUFFER:\n");  /* *************************** */
+  PR("  last_ack_sent %-10u                      rx_compact %u\n", 
+	      val("ts_last_ack_sent"),val("rx_compact"));
+  PR("  rcv_nxt       %-10u  hdr_off %-10u\n",
+	      val("rcv_nxt"), val("rx_hdr_offset"));
+  PR("  frag0_idx     %-10u  length  %-10u  frag0_ptr  0x%-8x\n", 
+	      val("rx_frag0_start_idx"),
+	      val("rx_frag0_len"),
+	      val("rx_ptr"));
+  PR("  frag1_idx     %-10u  length  %-10u  ", 
+	      val("rx_frag1_start_idx_offset"),
+	      val("rx_frag1_len"));
+
+
+
+
+  if (val("ulp_type")!=4 && val("ulp_type")!=7) { /* RDMA has FRAG1 idx && len, but no ptr?  Should I not display frag1 at all? */
+    PR("frag1_ptr  0x%-8x\n",val("rx_frag1_ptr"));
+  } else {
+    PR("\n");
+  }
+	      
+  
+  if (val("ulp_type") != 9 && val("ulp_type")!=8 && val("ulp_type") !=6 && 
+      val("ulp_type") != 5 && val("ulp_type") !=4 && val("ulp_type") !=7) {
+    PR("  frag2_idx     %-10u  length  %-10u  frag2_ptr  0x%-8x\n", 
+		val("rx_frag2_start_idx_offset"),
+		val("rx_frag2_len"),
+		val("rx_frag2_ptr"));
+    PR("  frag3_idx     %-10u  length  %-10u  frag3_ptr  0x%-8x\n", 
+		val("rx_frag3_start_idx_offset"),
+		val("rx_frag3_len"),
+		val("rx_frag3_ptr"));
+  }
+
+
+
+
+
+
+  PR("  peer_fin %u,   rx_pdu_out %u, pdu_len %u\n",
+	      val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
+
+
+
+
+  if (val("recv_scale")) {
+    PR("  rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n",
+		val("rcv_wnd"), val("snd_scale"), 
+		val("rcv_wnd") >> val("snd_scale"), 
+		val("recv_scale"));
+  } else {
+    PR("  rcv_wnd %u.  (snd_scale %u, recv_scaleflag = %u)\n",
+		val("rcv_wnd"), val("snd_scale"), 
+		val("recv_scale"));
+  }
+
+
+
+
+ PR("  dack_mss   %u dack       %u,  dack_not_acked: %u\n", 
+	      val("dack_mss"),val("dack"),val("dack_not_acked"));
+  PR("  rcv_coal   %u rcv_co_psh %u rcv_co_last_psh  %u heart %u\n",
+	      val("rcv_coalesce_enable"),
+	      val("rcv_coalesce_push"),
+	      val("rcv_coalesce_last_psh"),
+	      val("rcv_coalesce_heartbeat"));
+  
+  PR("  rx_quiesce %u rx_flow_ctrl_dis %u,",
+	      val("rx_quiesce"),
+	      val("rx_flow_control_disable"));
+  PR("  rx_flow_ctrl_ddp %u\n",
+	      val("rx_flow_control_ddp"));
+
+
+  PR("MISCELANEOUS:\n");  /* *************************** */
+  PR("  pend_ctl: 0x%1x, core_bypass: 0x%x,  main_slush: 0x%x\n",
+	      ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) | 
+	       val("pend_ctl0")),
+	      val("core_bypass"),val("main_slush"));
+  PR("  Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n",
+	      val("migrating"), 
+	      val("ask_mode"), val("non_offload"), val("rss_info"));
+  PR("  ULP: ulp_type %u (%s), ulp_raw %u",
+	      val("ulp_type"), spr_ulp_type(val("ulp_type")),
+	      val("ulp_raw"));
+
+
+  if (aux==1) {
+    PR(",  ulp_ext %u",val("ulp_ext"));
+  }
+  PR("\n");
+
+
+
+
+  PR("  RDMA: error   %u, flm_err %u\n", 
+	      val("rdma_error"), val("rdma_flm_error"));
+
+
+}
+void t7_display_tcb_aux_1 (_TCBVAR *tvp, int aux)
+{
+
+
+  
+  PR("    aux1_slush0: 0x%x aux1_slush1 0x%x\n",
+	      val("aux1_slush0"), val("aux1_slush1"));
+  PR("    pdu_hdr_len %u\n",val("pdu_hdr_len"));
+  
+
+
+}
+void t7_display_tcb_aux_2 (_TCBVAR *tvp, int aux)
+{
+
+
+
+
+  PR("    qp_id %u, pd_id %u, stag %u\n",
+	       val("qp_id"), val("pd_id"),val("stag"));
+  PR("    irs_ulp %u, iss_ulp %u\n",
+	      val("irs_ulp"),val("iss_ulp"));
+  PR("    tx_pdu_len %u\n",
+	      val("tx_pdu_len"));
+  PR("    cq_idx_sq %u, cq_idx_rq %u\n",
+	      val("cq_idx_sq"),val("cq_idx_rq"));
+  PR("    rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n",
+	      val("rq_start"),val("rq_msn"),val("rq_max_offset"),
+	      val("rq_write_ptr"));
+  PR("    L_valid %u, rdmap opcode %u\n",
+	      val("ord_l_bit_vld"),val("rdmap_opcode"));
+  PR("    tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n",
+	      val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
+
+
+
+
+}
+void t7_display_tcb_aux_3 (_TCBVAR *tvp, int aux)
+{
+
+
+
+
+
+
+  PR("  aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x\n",
+	      val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"));
+
+
+  PR("  ind_full: %u, tls_key_mode: %u\n",
+	      val("ddp_indicate_fll"),val("tls_key_mode"));
+
+
+  PR("  DDP: DDPOFF  ActBuf  IndOut  WaitFrag  Rx2Tx  BufInf\n");
+  PR("         %u       %u       %u        %u        %u      %u\n",
+	      val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
+	      val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
+	     );
+
+
+  PR("        Ind  PshfEn PushDis Flush NoInvalidate\n");
+  PR("   Buf0: %u      %u       %u    %u       %u\n",
+	      val("ddp_buf0_indicate"),
+	      val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
+	      val("ddp_buf0_flush"),  val("ddp_psh_no_invalidate0")
+	       );
+  PR("   Buf1: %u      %u       %u    %u       %u\n",
+	      val("ddp_buf1_indicate"),
+	      val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
+	      val("ddp_buf1_flush"),  val("ddp_psh_no_invalidate1")
+	       );
+
+
+
+
+
+
+
+
+
+
+  PR("        Valid  Offset   Length    Tag\n");
+  PR("   Buf0:  %u    0x%6.6x 0x%6.6x  0x%8.8x",
+	      val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"), 
+	      val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag") 
+
+
+	       );
+  if      (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
+    PR("   (Active)\n");
+  } else {
+    PR(" (Inactive)\n");
+  }
+
+
+  PR("   Buf1:  %u    0x%6.6x 0x%6.6x  0x%8.8x",
+	      val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"), 
+	      val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag") 
+
+
+	       );
+
+
+  if      (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
+    PR("   (Active)\n");
+  } else {
+    PR(" (Inactive)\n");
+  }
+
+
+
+
+
+
+  if    (1==val("ddp_off")) {
+    PR("   DDP is off (which also disables indicate)\n");
+  } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
+    PR("   Data being DDP'ed to buf 0, ");
+    PR("which has %u - %u = %u bytes of space left\n",
+		val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
+		val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
+	       );
+    if (1==val("ddp_buf1_valid")) {
+      PR("   And buf1, which is also valid, has %u - %u = %u bytes of space left\n",
+		  val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
+		  val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
+		 );
+    }
+  } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
+    PR("   Data being DDP'ed to buf 1, ");
+    PR("which has %u - %u = %u bytes of space left\n",
+		val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
+		val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
+	       );
+    if (1==val("ddp_buf0_valid")) {
+      PR("   And buf0, which is also valid, has %u - %u = %u bytes of space left\n",
+		  val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
+		  val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
+		 );
+    }
+  } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
+    PR("   !!! Invalid DDP buf 1 valid, but buf 0 active.\n");
+  } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
+    PR("   !!! Invalid DDP buf 0 valid, but buf 1 active.\n");
+  } else {
+    PR("   DDP is enabled, but no buffers are active && valid.\n");
+
+
+
+
+    if (0==val("ddp_indicate_out")) {
+      if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
+	PR("   0 length Indicate buffers ");
+	if (0==val("rx_hdr_offset")) {
+	  PR("will cause new data to be held in PMRX.\n");	
+	} else {
+	  PR("is causing %u bytes to be held in PMRX\n",
+		      val("rx_hdr_offset"));
+	}
+      } else {
+	PR("   Data being indicated to host\n");	  
+      }
+    } else if (1==val("ddp_indicate_out")) {
+      PR("   Indicate is off, which ");
+      if (0==val("rx_hdr_offset")) {
+	PR("will cause new data to be held in PMRX.\n");	
+      } else {
+	PR("is causing %u bytes to be held in PMRX\n",
+		    val("rx_hdr_offset"));
+      }	
+    }
+  }
+
+
+
+
+}
+void t7_display_tcb_aux_4 (_TCBVAR *tvp, int aux)
+{
+
+
+  
+  PR("TLS:  offset: 0x%6.6x, len:0x%6.6x, flags: 0x%4.4x\n",
+	      val("rx_tls_buf_offset"),val("rx_tls_buf_len"),
+	      val("rx_tls_flags"));
+  PR("      seq: 0x%llx \n",val64("rx_tls_seq")); 
+  PR("      tag: 0x%8.8x, key:0x%8.8x\n",
+	      val("rx_tls_buf_tag"),val("rx_tls_key_tag"));
+
+
+
+
+}
diff --git a/usr.sbin/inetd/inetd.8 b/usr.sbin/inetd/inetd.8
index 86feb0ba466e..d2a4331bb79c 100644
--- a/usr.sbin/inetd/inetd.8
+++ b/usr.sbin/inetd/inetd.8
@@ -25,7 +25,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd September 29, 2022
+.Dd September 25, 2025
 .Dt INETD 8
 .Os
 .Sh NAME
@@ -949,7 +949,7 @@ database.
 .Xr bootpd 8 ,
 .Xr comsat 8 ,
 .Xr fingerd 8 ,
-.Xr ftpd 8 ,
+.Xr ftpd 8 Pq Pa ports/ftp/freebsd-ftpd ,
 .Xr imapd 8 Pq Pa ports/mail/courier-imap ,
 .Xr nmbd 8 Pq Pa ports/net/samba412 ,
 .Xr rlogind 8 ,
diff --git a/usr.sbin/inetd/inetd.conf b/usr.sbin/inetd/inetd.conf
index a8359ea793f5..e25a77d3ca9c 100644
--- a/usr.sbin/inetd/inetd.conf
+++ b/usr.sbin/inetd/inetd.conf
@@ -5,8 +5,8 @@
 # To disable a service, comment it out by prefixing the line with '#'.
 # To enable a service, remove the '#' at the beginning of the line.
 #
-#ftp	stream	tcp	nowait	root	/usr/libexec/ftpd	ftpd -l
-#ftp	stream	tcp6	nowait	root	/usr/libexec/ftpd	ftpd -l
+#ftp	stream	tcp	nowait	root	/usr/local/libexec/ftpd	ftpd -l
+#ftp	stream	tcp6	nowait	root	/usr/local/libexec/ftpd	ftpd -l
 #ssh	stream	tcp	nowait	root	/usr/sbin/sshd		sshd -i
 #ssh	stream	tcp6	nowait	root	/usr/sbin/sshd		sshd -i
 #telnet	stream	tcp	nowait	root	/usr/local/libexec/telnetd	telnetd
diff --git a/usr.sbin/iovctl/iovctl.8 b/usr.sbin/iovctl/iovctl.8
index 5c7b01c249a0..2574503e5ae7 100644
--- a/usr.sbin/iovctl/iovctl.8
+++ b/usr.sbin/iovctl/iovctl.8
@@ -95,7 +95,7 @@ and
 options, this file will only be used to specify the name of the PF device.
 .Pp
 See
-.Xr iovctl.conf
+.Xr iovctl.conf 5
 for a description of the config file format and documentation of the
 configuration parameters that apply to all PF drivers.
 See the PF driver manual page for configuration parameters specific to
diff --git a/usr.sbin/mixer/Makefile b/usr.sbin/mixer/Makefile
index 9e96c2f2d2e8..6c75e65d2a9b 100644
--- a/usr.sbin/mixer/Makefile
+++ b/usr.sbin/mixer/Makefile
@@ -1,5 +1,7 @@
 .include <src.opts.mk>
 
+PACKAGE=	sound
+
 PROG=		mixer
 SRCS=		${PROG}.c
 MAN=		${PROG}.8
diff --git a/usr.sbin/newsyslog/newsyslog.conf.d/Makefile b/usr.sbin/newsyslog/newsyslog.conf.d/Makefile
index 8ef3af253a50..81bec81ece6e 100644
--- a/usr.sbin/newsyslog/newsyslog.conf.d/Makefile
+++ b/usr.sbin/newsyslog/newsyslog.conf.d/Makefile
@@ -6,13 +6,6 @@ CONFSDIR=	/etc/newsyslog.conf.d
 CONFGROUPS=	CONFS
 CONFS=
 
-.if ${MK_FTP} != "no"
-CONFGROUPS+=	FTP
-FTP+=		ftp.conf
-FTPPACKAGE=	ftpd
-FTPDIR=		/etc/newsyslog.conf.d
-.endif
-
 .if ${MK_LPR} != "no"
 CONFGROUPS+=	LP
 LP+=		lpr.conf
diff --git a/usr.sbin/sndctl/Makefile b/usr.sbin/sndctl/Makefile
index c1830413f931..d6697bb88fd5 100644
--- a/usr.sbin/sndctl/Makefile
+++ b/usr.sbin/sndctl/Makefile
@@ -1,5 +1,7 @@
 .include <src.opts.mk>
 
+PACKAGE=	sound
+
 PROG=		sndctl
 SRCS=		${PROG}.c
 MAN=		${PROG}.8
diff --git a/usr.sbin/syslogd/Makefile b/usr.sbin/syslogd/Makefile
index 7b202c69f7f9..45df62a4a6ec 100644
--- a/usr.sbin/syslogd/Makefile
+++ b/usr.sbin/syslogd/Makefile
@@ -29,12 +29,6 @@ CFLAGS+= -DINET6
 
 SYSLOGD_D=
 SYSLOGD_DDIR=	/etc/syslog.d
-.if ${MK_FTP} != "no"
-CONFGROUPS+=	FTP
-FTP+=		ftp.conf
-FTPDIR=		/etc/syslog.d
-FTPPACKAGE=	ftpd
-.endif
 
 .if ${MK_LPR} != "no"
 CONFGROUPS+=	LP
diff --git a/usr.sbin/trim/trim.8 b/usr.sbin/trim/trim.8
index a4874c54c183..eef369703715 100644
--- a/usr.sbin/trim/trim.8
+++ b/usr.sbin/trim/trim.8
@@ -23,7 +23,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.Dd July 20, 2025
+.Dd October 1, 2025
 .Dt TRIM 8
 .Os
 .Sh NAME
@@ -48,9 +48,16 @@
 The
 .Nm
 utility erases specified region of the device.
-It is mostly relevant for storage that implement trim (like flash based,
+It is mostly relevant for a storage that implements trim (like flash based,
 or thinly provisioned storage).
 .Sy All erased data is lost.
+Alternatively, refer to the
+.Xr fsck_ffs 8
+command having a flag
+.Fl E
+to trim populated UFS, and to the
+.Xr zpool-trim 8
+command to trim existing ZFS pool.
 .Pp
 The following options are available:
 .Bl -tag -width indent
@@ -156,7 +163,9 @@ is special device file not supporting DIOCGMEDIASIZE
 .Xr sysexits 3 ,
 .Xr ada 4 ,
 .Xr da 4 ,
-.Xr nda 4
+.Xr nda 4 ,
+.Xr fsck_ffs 8 ,
+.Xr zpool-trim 8
 .Sh HISTORY
 The
 .Nm
diff --git a/usr.sbin/virtual_oss/Makefile b/usr.sbin/virtual_oss/Makefile
index bf73041377b3..6c497ad71d46 100644
--- a/usr.sbin/virtual_oss/Makefile
+++ b/usr.sbin/virtual_oss/Makefile
@@ -1,8 +1,9 @@
 .include <src.opts.mk>
 
-SUBDIR+= virtual_bt_speaker \
-	 virtual_oss_cmd \
+SUBDIR+= virtual_oss_cmd \
 	 virtual_oss
 
+SUBDIR.${MK_BLUETOOTH}+= virtual_bt_speaker
+
 .include "Makefile.inc"
 .include <bsd.subdir.mk>
diff --git a/usr.sbin/virtual_oss/Makefile.inc b/usr.sbin/virtual_oss/Makefile.inc
index 01b5f23410c8..d2b0d74fa8c4 100644
--- a/usr.sbin/virtual_oss/Makefile.inc
+++ b/usr.sbin/virtual_oss/Makefile.inc
@@ -1 +1,3 @@
+PACKAGE?=	sound
+
 .include "../Makefile.inc"
diff --git a/usr.sbin/virtual_oss/virtual_bt_speaker/Makefile b/usr.sbin/virtual_oss/virtual_bt_speaker/Makefile
index 5e4553e7a298..0f5fb2b4eb99 100644
--- a/usr.sbin/virtual_oss/virtual_bt_speaker/Makefile
+++ b/usr.sbin/virtual_oss/virtual_bt_speaker/Makefile
@@ -6,6 +6,6 @@ SRCS=		bt_speaker.c
 CFLAGS+= 	-I${SRCTOP}/usr.sbin/virtual_oss/virtual_oss \
 		-I${SRCTOP}/lib/virtual_oss/bt
 
-LDFLAGS+= 	-L${LIBDIR} -lm -lbluetooth -lsdp
+LDFLAGS+= 	-lm -lbluetooth -lsdp
 
 .include <bsd.prog.mk>
diff --git a/usr.sbin/virtual_oss/virtual_oss/httpd.c b/usr.sbin/virtual_oss/virtual_oss/httpd.c
index c05d5839e96b..dc5d6036f39d 100644
--- a/usr.sbin/virtual_oss/virtual_oss/httpd.c
+++ b/usr.sbin/virtual_oss/virtual_oss/httpd.c
@@ -147,8 +147,9 @@ done:
 }
 
 static uint16_t
-voss_ipv4_csum(const uint16_t *ptr, size_t count)
+voss_ipv4_csum(const void *vptr, size_t count)
 {
+	const uint16_t *ptr = vptr;
 	uint32_t sum = 0;
 
 	while (count--)
@@ -161,9 +162,11 @@ voss_ipv4_csum(const uint16_t *ptr, size_t count)
 }
 
 static uint16_t
-voss_udp_csum(uint32_t sum, const uint16_t *hdr, size_t count,
+voss_udp_csum(uint32_t sum, const void *vhdr, size_t count,
     const uint16_t *ptr, size_t length)
 {
+	const uint16_t *hdr = vhdr;
+
 	while (count--)
 		sum += *hdr++;
 
@@ -233,8 +236,7 @@ voss_httpd_send_rtp_sub(vclient_t *pvc, int fd, void *ptr, size_t len, uint32_t
 	pvc->profile->http.rtp_seqnum++;
 	pvc->profile->http.rtp_ts += len / (2 * pvc->channels);
 
-	if (writev(fd, iov, 2) < 0)
-		;
+	(void)writev(fd, iov, 2);
 }
 
 static void
@@ -483,7 +485,7 @@ voss_httpd_handle_connection(vclient_t *pvc, int fd, const struct sockaddr_in *s
 		} else if (page < 0 && strstr(line, "GET /stream.m3u") == line) {
 			page = 2;
 		} else if (strstr(line, "Range: bytes=") == line &&
-		    sscanf(line, "Range: bytes=%zu-%zu", &r_start, &r_end) >= 1) {
+		    sscanf(line, "Range: bytes=%ju-%ju", &r_start, &r_end) >= 1) {
 			is_partial = true;
 		}
 	}
diff --git a/usr.sbin/virtual_oss/virtual_oss/int.h b/usr.sbin/virtual_oss/virtual_oss/int.h
index 4fea69f1a11f..b3cc573ba8a9 100644
--- a/usr.sbin/virtual_oss/virtual_oss/int.h
+++ b/usr.sbin/virtual_oss/virtual_oss/int.h
@@ -54,20 +54,24 @@ extern pthread_cond_t atomic_cv;
 	(AFMT_U8 | AFMT_S8)
 
 #define	VMAX_CHAN 64
-#define	VMAX_STRING 64	/* characters */
+/*
+ * XXX 32 - strlen("/dev") to not exceed OSS_DEVNODE_SIZE in soundcard.h. Also
+ * silences GCC warnings.
+ */
+#define	VMAX_STRING 27
 
 #define	VTYPE_OSS_DAT 0
 #define	VTYPE_WAV_HDR 1
 #define	VTYPE_WAV_DAT 2
 
 #define	VPREFERRED_SNE_AFMT \
-  (AFMT_S8 | AFMT_S16_NE | AFMT_S24_NE | AFMT_S32_NE | AFMT_F32_NE)
+  (AFMT_S8 | AFMT_S16_NE | AFMT_S24_NE | AFMT_S32_NE)
 #define	VPREFERRED_UNE_AFMT \
   (AFMT_U8 | AFMT_U16_NE | AFMT_U24_NE | AFMT_U32_NE)
 #define	VPREFERRED_SLE_AFMT \
-  (AFMT_S8 | AFMT_S16_LE | AFMT_S24_LE | AFMT_S32_LE | AFMT_F32_LE)
+  (AFMT_S8 | AFMT_S16_LE | AFMT_S24_LE | AFMT_S32_LE)
 #define	VPREFERRED_SBE_AFMT \
-  (AFMT_S8 | AFMT_S16_BE | AFMT_S24_BE | AFMT_S32_BE | AFMT_F32_BE)
+  (AFMT_S8 | AFMT_S16_BE | AFMT_S24_BE | AFMT_S32_BE)
 #define	VPREFERRED_ULE_AFMT \
   (AFMT_U8 | AFMT_U16_LE | AFMT_U24_LE | AFMT_U32_LE)
 #define	VPREFERRED_UBE_AFMT \
diff --git a/usr.sbin/virtual_oss/virtual_oss/main.c b/usr.sbin/virtual_oss/virtual_oss/main.c
index 760747e90091..3f7fb84ce4c6 100644
--- a/usr.sbin/virtual_oss/virtual_oss/main.c
+++ b/usr.sbin/virtual_oss/virtual_oss/main.c
@@ -1185,7 +1185,7 @@ vclient_ioctl_oss(struct cuse_dev *pdev, int fflags __unused,
 		strlcpy(data.audioinfo.name, pvc->profile->oss_name,
 		    sizeof(data.audioinfo.name));
 		snprintf(data.audioinfo.devnode, sizeof(data.audioinfo.devnode),
-		    _PATH_DEV "%s", pvc->profile->oss_name);
+		    "/dev/%s", pvc->profile->oss_name);
 		data.audioinfo.caps = DSP_CAP_INPUT | DSP_CAP_OUTPUT;
 		data.audioinfo.iformats = VSUPPORTED_AFMT;
 		data.audioinfo.oformats = VSUPPORTED_AFMT;
@@ -2275,7 +2275,7 @@ parse_options(int narg, char **pparg, int is_main)
 			if (voss_ctl_device[0])
 				return ("-t parameter may only be used once");
 
-			strncpy(voss_ctl_device, optarg, sizeof(voss_ctl_device));
+			strlcpy(voss_ctl_device, optarg, sizeof(voss_ctl_device));
 			break;
 		case 'm':
 			ptr = optarg;
@@ -2529,7 +2529,7 @@ main(int argc, char **argv)
 {
 	const char *ptrerr;
 	struct sigaction sa;
-	struct cuse_dev *pdev;
+	struct cuse_dev *pdev = NULL;
 
 	TAILQ_INIT(&virtual_profile_client_head);
 	TAILQ_INIT(&virtual_profile_loopback_head);
diff --git a/usr.sbin/wlanstats/Makefile b/usr.sbin/wlanstat/Makefile
index 574a9c27137f..ec1fc3206267 100644
--- a/usr.sbin/wlanstats/Makefile
+++ b/usr.sbin/wlanstat/Makefile
@@ -1,13 +1,13 @@
 .include <bsd.compiler.mk>
 
-PROG=	wlanstats
-MAN=	wlanstats.8
+PROG=	wlanstat
+MAN=	wlanstat.8
 
 CFLAGS=	-I${SRCTOP}/lib/libbsdstat
 LIBADD=	bsdstat
 
 SRCS=	main.c \
-	wlanstats.c
+	wlanstat.c
 
 CFLAGS.clang+= -fbracket-depth=512 -Wno-cast-align
 
diff --git a/usr.sbin/wlanstats/main.c b/usr.sbin/wlanstat/main.c
index 85d10ad9012a..fba0b01a07d0 100644
--- a/usr.sbin/wlanstats/main.c
+++ b/usr.sbin/wlanstat/main.c
@@ -28,7 +28,7 @@
  */
 
 /*
- * wlanstats [-i interface]
+ * wlanstat [-i interface]
  * (default interface is wlan0).
  */
 
@@ -45,7 +45,7 @@
 #include <strings.h>
 #include <unistd.h>
 
-#include "wlanstats.h"
+#include "wlanstat.h"
 
 static struct {
 	const char *tag;
@@ -158,7 +158,7 @@ static void
 usage(void)
 {
 
-	printf("wlanstats: [-h] [-i ifname] [-l] [-m station_MAC_address] [-o fmt] [interval]\n");
+	printf("wlanstat: [-h] [-i ifname] [-l] [-m station_MAC_address] [-o fmt] [interval]\n");
 }
 
 int
@@ -176,7 +176,7 @@ main(int argc, char *argv[])
 	ifname = getenv("WLAN");
 	if (ifname == NULL)
 		ifname = "wlan0";
-	wf = wlanstats_new(ifname, getfmt("default"));
+	wf = wlanstat_new(ifname, getfmt("default"));
 #if 0
 	while ((c = getopt(argc, argv, "ahi:lm:o:")) != -1) {
 #else
diff --git a/usr.sbin/wlanstats/wlanstats.8 b/usr.sbin/wlanstat/wlanstat.8
index a8127726dd61..6e3df1ef3e5e 100644
--- a/usr.sbin/wlanstats/wlanstats.8
+++ b/usr.sbin/wlanstat/wlanstat.8
@@ -7,10 +7,10 @@
 .\" SPDX-License-Identifier: BSD-2-Clause
 .\"
 .Dd March 14, 2025
-.Dt WLANSTATS 8
+.Dt WLANSTAT 8
 .Os
 .Sh NAME
-.Nm wlanstats
+.Nm wlanstat
 .Nd query 802.11 wireless network statistics
 .Sh SYNOPSIS
 .Nm
diff --git a/usr.sbin/wlanstats/wlanstats.c b/usr.sbin/wlanstat/wlanstat.c
index 83f5010341a9..468c4848004d 100644
--- a/usr.sbin/wlanstats/wlanstats.c
+++ b/usr.sbin/wlanstat/wlanstat.c
@@ -52,7 +52,7 @@
 
 #include "../../sys/net80211/ieee80211_ioctl.h"
 
-#include "wlanstats.h"
+#include "wlanstat.h"
 
 #ifndef IEEE80211_ADDR_COPY
 #define	IEEE80211_ADDR_COPY(dst, src)	memcpy(dst, src, IEEE80211_ADDR_LEN)
@@ -61,7 +61,7 @@
 
 #define	AFTER(prev)	((prev)+1)
 
-static const struct fmt wlanstats[] = {
+static const struct fmt wlanstat[] = {
 #define	S_RX_BADVERSION		0
 	{ 5,  "rx_badversion",	"bvers",	"rx frame with bad version" },
 #define	S_RX_TOOSHORT		AFTER(S_RX_BADVERSION)
@@ -1032,14 +1032,14 @@ wlan_get_totstat(struct bsdstat *sf, int s, char b[], size_t bs)
 BSDSTAT_DEFINE_BOUNCE(wlanstatfoo)
 
 struct wlanstatfoo *
-wlanstats_new(const char *ifname, const char *fmtstring)
+wlanstat_new(const char *ifname, const char *fmtstring)
 {
 	struct wlanstatfoo_p *wf;
 
 	wf = calloc(1, sizeof(struct wlanstatfoo_p));
 	if (wf != NULL) {
-		bsdstat_init(&wf->base.base, "wlanstats", wlanstats,
-		    nitems(wlanstats));
+		bsdstat_init(&wf->base.base, "wlanstat", wlanstat,
+		    nitems(wlanstat));
 		/* override base methods */
 		wf->base.base.collect_cur = wlan_collect_cur;
 		wf->base.base.collect_tot = wlan_collect_tot;
diff --git a/usr.sbin/wlanstats/wlanstats.h b/usr.sbin/wlanstat/wlanstat.h
index 8ab3c0558fd6..ed0150e11809 100644
--- a/usr.sbin/wlanstats/wlanstats.h
+++ b/usr.sbin/wlanstat/wlanstat.h
@@ -27,8 +27,8 @@
  * THE POSSIBILITY OF SUCH DAMAGES.
  */
 
-#ifndef _WLANSTATS_H_
-#define	_WLANSTATS_H_
+#ifndef _WLANSTAT_H_
+#define	_WLANSTAT_H_
 
 #include "bsdstat.h"
 
@@ -50,5 +50,5 @@ struct wlanstatfoo {
 	void (*setstamac)(struct wlanstatfoo *, const uint8_t mac[]);
 };
 
-struct wlanstatfoo *wlanstats_new(const char *ifname, const char *fmtstring);
-#endif /* _WLANSTATS_H_ */
+struct wlanstatfoo *wlanstat_new(const char *ifname, const char *fmtstring);
+#endif /* _WLANSTAT_H_ */
diff --git a/usr.sbin/ypserv/Makefile b/usr.sbin/ypserv/Makefile
index ba7eb1f86267..b4e59b719692 100644
--- a/usr.sbin/ypserv/Makefile
+++ b/usr.sbin/ypserv/Makefile
@@ -41,7 +41,10 @@ FILESNAME= Makefile.dist
 FILESDIR= /var/yp
 SCRIPTS= ypinit.sh
 
-.if !exists(${DESTDIR}${FILESDIR}/Makefile)
+# If NO_ROOT is defined, we are doing a stage install and always need to
+# install the symlink, otherwise, don't overwrite the user's existing
+# symlink.
+.if defined(NO_ROOT) || !exists(${DESTDIR}${FILESDIR}/Makefile)
 SYMLINKS= ${FILESNAME} ${FILESDIR}/Makefile
 .endif