diff options
36 files changed, 81 insertions, 81 deletions
diff --git a/sys/dev/ae/if_ae.c b/sys/dev/ae/if_ae.c index d3156070d0f2..eb9260d66932 100644 --- a/sys/dev/ae/if_ae.c +++ b/sys/dev/ae/if_ae.c @@ -341,7 +341,7 @@ ae_attach(device_t dev) ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); IFQ_SET_READY(&ifp->if_snd); - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { ifp->if_capabilities |= IFCAP_WOL_MAGIC; sc->flags |= AE_FLAG_PMG; } @@ -929,7 +929,7 @@ ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) val &= ~AE_SPICTL_VPD_EN; AE_WRITE_4(sc, AE_SPICTL_REG, val); } - error = pci_find_extcap(sc->dev, PCIY_VPD, vpdc); + error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); return (error); } @@ -1383,7 +1383,7 @@ ae_pm_init(ae_softc_t *sc) /* * Configure PME. */ - pci_find_extcap(sc->dev, PCIY_PMG, &pmc); + pci_find_cap(sc->dev, PCIY_PMG, &pmc); pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); if ((ifp->if_capenable & IFCAP_WOL) != 0) diff --git a/sys/dev/age/if_age.c b/sys/dev/age/if_age.c index e08607a050dc..d57a51d01046 100644 --- a/sys/dev/age/if_age.c +++ b/sys/dev/age/if_age.c @@ -346,7 +346,7 @@ age_get_macaddr(struct age_softc *sc) CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); } - if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { + if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { /* * PCI VPD capability found, let TWSI reload EEPROM. * This will set ethernet address of controller. @@ -563,7 +563,7 @@ age_attach(device_t dev) /* Get DMA parameters from PCIe device control register. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->age_flags |= AGE_FLAG_PCIE; burst = pci_read_config(dev, i + 0x08, 2); /* Max read request size. */ @@ -610,7 +610,7 @@ age_attach(device_t dev) IFQ_SET_READY(&ifp->if_snd); ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { sc->age_flags |= AGE_FLAG_PMCAP; ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; } @@ -1329,7 +1329,7 @@ age_setwol(struct age_softc *sc) AGE_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) { + if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { CSR_WRITE_4(sc, AGE_WOL_CFG, 0); /* * No PME capability, PHY power down. diff --git a/sys/dev/agp/agp.c b/sys/dev/agp/agp.c index 09e284884700..6e5aa358b24e 100644 --- a/sys/dev/agp/agp.c +++ b/sys/dev/agp/agp.c @@ -98,7 +98,7 @@ agp_find_caps(device_t dev) int capreg; - if (pci_find_extcap(dev, PCIY_AGP, &capreg) != 0) + if (pci_find_cap(dev, PCIY_AGP, &capreg) != 0) capreg = 0; return (capreg); } diff --git a/sys/dev/aic7xxx/aic79xx_pci.c b/sys/dev/aic7xxx/aic79xx_pci.c index 1e3bbed392f1..2f02cc678352 100644 --- a/sys/dev/aic7xxx/aic79xx_pci.c +++ b/sys/dev/aic7xxx/aic79xx_pci.c @@ -353,7 +353,7 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) * Find the PCI-X cap pointer. If we don't find it, * pcix_ptr will be 0. */ - pci_find_extcap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); + pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { ahd->chip |= AHD_PCI; diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c index 25625c43caf2..7bad91b50349 100644 --- a/sys/dev/alc/if_alc.c +++ b/sys/dev/alc/if_alc.c @@ -783,7 +783,7 @@ alc_attach(device_t dev) sc->alc_dma_rd_burst = 0; sc->alc_dma_wr_burst = 0; sc->alc_rcb = DMA_CFG_RCB_64; - if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); @@ -963,7 +963,7 @@ alc_attach(device_t dev) IFQ_SET_READY(&ifp->if_snd); ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; - if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) { + if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; sc->alc_flags |= ALC_FLAG_PM; sc->alc_pmcap = base; diff --git a/sys/dev/ale/if_ale.c b/sys/dev/ale/if_ale.c index dac0351f9306..e4272df25659 100644 --- a/sys/dev/ale/if_ale.c +++ b/sys/dev/ale/if_ale.c @@ -330,7 +330,7 @@ ale_get_macaddr(struct ale_softc *sc) CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); } - if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { + if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { /* * PCI VPD capability found, let TWSI reload EEPROM. * This will set ethernet address of controller. @@ -544,7 +544,7 @@ ale_attach(device_t dev) } /* Get DMA parameters from PCIe device control register. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->ale_flags |= ALE_FLAG_PCIE; burst = pci_read_config(dev, i + 0x08, 2); /* Max read request size. */ @@ -591,7 +591,7 @@ ale_attach(device_t dev) IFQ_SET_READY(&ifp->if_snd); ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { sc->ale_flags |= ALE_FLAG_PMCAP; ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; } @@ -1469,7 +1469,7 @@ ale_setwol(struct ale_softc *sc) ALE_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { + if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { /* Disable WOL. */ CSR_WRITE_4(sc, ALE_WOL_CFG, 0); reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); @@ -1548,7 +1548,7 @@ ale_resume(device_t dev) sc = device_get_softc(dev); ALE_LOCK(sc); - if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); diff --git a/sys/dev/bce/if_bce.c b/sys/dev/bce/if_bce.c index 49d3689ae933..7d0e47e5e827 100644 --- a/sys/dev/bce/if_bce.c +++ b/sys/dev/bce/if_bce.c @@ -801,13 +801,13 @@ bce_probe_pci_caps(device_t dev, struct bce_softc *sc) DBENTER(BCE_VERBOSE_LOAD); /* Check if PCI-X capability is enabled. */ - if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { + if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { if (reg != 0) sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; } /* Check if PCIe capability is enabled. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { if (reg != 0) { u16 link_status = pci_read_config(dev, reg + 0x12, 2); DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " @@ -820,13 +820,13 @@ bce_probe_pci_caps(device_t dev, struct bce_softc *sc) } /* Check if MSI capability is enabled. */ - if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { + if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { if (reg != 0) sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; } /* Check if MSI-X capability is enabled. */ - if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { + if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { if (reg != 0) sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; } diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c index e5318c22d6e4..b1fc3824ff77 100644 --- a/sys/dev/bge/if_bge.c +++ b/sys/dev/bge/if_bge.c @@ -2883,7 +2883,7 @@ bge_attach(device_t dev) /* * Check if this is a PCI-X or PCI Express device. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { /* * Found a PCI Express capabilities register, this * must be a PCI Express device. @@ -2897,7 +2897,7 @@ bge_attach(device_t dev) * Check if the device is in PCI-X Mode. * (This bit is not valid on PCI Express controllers.) */ - if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) + if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) sc->bge_pcixcap = reg; if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & BGE_PCISTATE_PCI_BUSMODE) == 0) @@ -2917,7 +2917,7 @@ bge_attach(device_t dev) * normal operation. */ rid = 0; - if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { + if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { sc->bge_msicap = reg; if (bge_can_use_msi(sc)) { msicount = pci_msi_count(dev); diff --git a/sys/dev/bwn/if_bwn.c b/sys/dev/bwn/if_bwn.c index e43f413b0826..a79ec113b967 100644 --- a/sys/dev/bwn/if_bwn.c +++ b/sys/dev/bwn/if_bwn.c @@ -979,7 +979,7 @@ bwn_attach(device_t dev) /* * setup PCI resources and interrupt. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { msic = pci_msi_count(dev); if (bootverbose) device_printf(sc->sc_dev, "MSI count : %d\n", msic); diff --git a/sys/dev/bxe/if_bxe.c b/sys/dev/bxe/if_bxe.c index 2d81933096aa..f3e5e1619f88 100644 --- a/sys/dev/bxe/if_bxe.c +++ b/sys/dev/bxe/if_bxe.c @@ -1568,7 +1568,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc) DBENTER(BXE_EXTREME_LOAD); /* Check if PCI Power Management capability is enabled. */ - if (pci_find_extcap(dev, PCIY_PMG, ®) == 0) { + if (pci_find_cap(dev, PCIY_PMG, ®) == 0) { if (reg != 0) { DBPRINT(sc, BXE_EXTREME_LOAD, "%s(): Found PM capability at 0x%04X\n", @@ -1578,7 +1578,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc) } /* Check if PCIe capability is enabled. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { if (reg != 0) { link_status = pci_read_config(dev, reg + 0x12, 2); @@ -1612,7 +1612,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc) /* Check if MSI capability is enabled. */ - if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { + if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { if (reg != 0) { DBPRINT(sc, BXE_EXTREME_LOAD, "%s(): Found MSI capability at 0x%04X\n", @@ -1622,7 +1622,7 @@ bxe_probe_pci_caps(struct bxe_softc *sc) } /* Check if MSI-X capability is enabled. */ - if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { + if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { if (reg != 0) { DBPRINT(sc, BXE_EXTREME_LOAD, "%s(): Found MSI-X capability at 0x%04X\n", diff --git a/sys/dev/cxgb/cxgb_main.c b/sys/dev/cxgb/cxgb_main.c index f094846b3fc6..be65f02d9165 100644 --- a/sys/dev/cxgb/cxgb_main.c +++ b/sys/dev/cxgb/cxgb_main.c @@ -458,7 +458,7 @@ cxgb_controller_attach(device_t dev) ai = cxgb_get_adapter_info(dev); /* find the PCIe link width and set max read request to 4KB*/ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { uint16_t lnk; lnk = pci_read_config(dev, reg + PCIR_EXPRESS_LINK_STA, 2); diff --git a/sys/dev/drm/drm_agpsupport.c b/sys/dev/drm/drm_agpsupport.c index cb98ec118a5d..6a7ebcf5e9ef 100644 --- a/sys/dev/drm/drm_agpsupport.c +++ b/sys/dev/drm/drm_agpsupport.c @@ -51,7 +51,7 @@ drm_device_find_capability(struct drm_device *dev, int cap) { #if __FreeBSD_version >= 602102 - return (pci_find_extcap(dev->device, cap, NULL) == 0); + return (pci_find_cap(dev->device, cap, NULL) == 0); #else /* Code taken from agp.c. IWBNI that was a public interface. */ u_int32_t status; diff --git a/sys/dev/e1000/e1000_osdep.c b/sys/dev/e1000/e1000_osdep.c index d5eccc4e12cf..75a7b79a4c4c 100644 --- a/sys/dev/e1000/e1000_osdep.c +++ b/sys/dev/e1000/e1000_osdep.c @@ -75,7 +75,7 @@ e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) device_t dev = ((struct e1000_osdep *)hw->back)->dev; u32 offset; - pci_find_extcap(dev, PCIY_EXPRESS, &offset); + pci_find_cap(dev, PCIY_EXPRESS, &offset); *value = pci_read_config(dev, offset + reg, 2); return (E1000_SUCCESS); } @@ -89,7 +89,7 @@ e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) device_t dev = ((struct e1000_osdep *)hw->back)->dev; u32 offset; - pci_find_extcap(dev, PCIY_EXPRESS, &offset); + pci_find_cap(dev, PCIY_EXPRESS, &offset); pci_write_config(dev, offset + reg, *value, 2); return (E1000_SUCCESS); } diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index cbf0bbb42eaa..c119144d001f 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -4756,7 +4756,7 @@ em_enable_wakeup(device_t dev) u32 pmc, ctrl, ctrl_ext, rctl; u16 status; - if ((pci_find_extcap(dev, PCIY_PMG, &pmc) != 0)) + if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) return; /* Advertise the wakeup capability */ @@ -4924,7 +4924,7 @@ em_disable_aspm(struct adapter *adapter) default: return; } - if (pci_find_extcap(dev, PCIY_EXPRESS, &base) != 0) + if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) return; reg = base + PCIR_EXPRESS_LINK_CAP; link_cap = pci_read_config(dev, reg, 2); diff --git a/sys/dev/e1000/if_lem.c b/sys/dev/e1000/if_lem.c index 7f10909b79c6..d4bd1b6a3a02 100644 --- a/sys/dev/e1000/if_lem.c +++ b/sys/dev/e1000/if_lem.c @@ -3939,7 +3939,7 @@ lem_enable_wakeup(device_t dev) u32 pmc, ctrl, ctrl_ext, rctl; u16 status; - if ((pci_find_extcap(dev, PCIY_PMG, &pmc) != 0)) + if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) return; /* Advertise the wakeup capability */ diff --git a/sys/dev/et/if_et.c b/sys/dev/et/if_et.c index 326309eb51a6..d337efde845e 100644 --- a/sys/dev/et/if_et.c +++ b/sys/dev/et/if_et.c @@ -275,7 +275,7 @@ et_attach(device_t dev) } msic = 0; - if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { sc->sc_expcap = cap; sc->sc_flags |= ET_FLAG_PCIE; msic = pci_msi_count(dev); diff --git a/sys/dev/fxp/if_fxp.c b/sys/dev/fxp/if_fxp.c index 7fd1b8cdb37f..fc22a967ed3d 100644 --- a/sys/dev/fxp/if_fxp.c +++ b/sys/dev/fxp/if_fxp.c @@ -521,7 +521,7 @@ fxp_attach(device_t dev) sc->revision != FXP_REV_82559S_A) { fxp_read_eeprom(sc, &data, 10, 1); if ((data & 0x20) != 0 && - pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) + pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) sc->flags |= FXP_FLAG_WOLCAP; } @@ -1054,7 +1054,7 @@ fxp_suspend(device_t dev) FXP_LOCK(sc); ifp = sc->ifp; - if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { @@ -1088,7 +1088,7 @@ fxp_resume(device_t dev) FXP_LOCK(sc); - if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { sc->flags &= ~FXP_FLAG_WOL; pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); /* Disable PME and clear PME status. */ diff --git a/sys/dev/iwn/if_iwn.c b/sys/dev/iwn/if_iwn.c index 72cf4150dc40..03674c3cba16 100644 --- a/sys/dev/iwn/if_iwn.c +++ b/sys/dev/iwn/if_iwn.c @@ -429,7 +429,7 @@ iwn_attach(device_t dev) * Get the offset of the PCI Express Capability Structure in PCI * Configuration Space. */ - error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); + error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); if (error != 0) { device_printf(dev, "PCIe capability structure not found!\n"); return error; diff --git a/sys/dev/ixgbe/ixv.c b/sys/dev/ixgbe/ixv.c index 6f3ad166f8c9..f9f910a109d3 100644 --- a/sys/dev/ixgbe/ixv.c +++ b/sys/dev/ixgbe/ixv.c @@ -1627,7 +1627,7 @@ ixv_allocate_msix(struct adapter *adapter) */ if (adapter->hw.mac.type == ixgbe_mac_82599_vf) { int msix_ctrl; - pci_find_extcap(dev, PCIY_MSIX, &rid); + pci_find_cap(dev, PCIY_MSIX, &rid); rid += PCIR_MSIX_CTRL; msix_ctrl = pci_read_config(dev, rid, 2); msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; diff --git a/sys/dev/jme/if_jme.c b/sys/dev/jme/if_jme.c index 0fd5b8cb3e32..6fc328e108e2 100644 --- a/sys/dev/jme/if_jme.c +++ b/sys/dev/jme/if_jme.c @@ -778,7 +778,7 @@ jme_attach(device_t dev) sc->jme_phyaddr = 0; /* Set max allowable DMA size. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->jme_flags |= JME_FLAG_PCIE; burst = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); if (bootverbose) { @@ -827,7 +827,7 @@ jme_attach(device_t dev) /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { sc->jme_flags |= JME_FLAG_PMCAP; ifp->if_capabilities |= IFCAP_WOL_MAGIC; } @@ -1591,7 +1591,7 @@ jme_setwol(struct jme_softc *sc) JME_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { + if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { /* Remove Tx MAC/offload clock to save more power. */ if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & @@ -1663,7 +1663,7 @@ jme_resume(device_t dev) sc = device_get_softc(dev); JME_LOCK(sc); - if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { + if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); /* Disable PME clear PME status. */ diff --git a/sys/dev/malo/if_malo_pci.c b/sys/dev/malo/if_malo_pci.c index c996658e53fb..9c2027b924c1 100644 --- a/sys/dev/malo/if_malo_pci.c +++ b/sys/dev/malo/if_malo_pci.c @@ -175,7 +175,7 @@ malo_pci_attach(device_t dev) */ sc->malo_invalid = 1; - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { msic = pci_msi_count(dev); if (bootverbose) device_printf(dev, "MSI count : %d\n", msic); diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index 7aa3fa5fde12..bc89d958acb4 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -1759,10 +1759,10 @@ mskc_attach(device_t dev) } /* Check bus type. */ - if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { sc->msk_bustype = MSK_PEX_BUS; sc->msk_expcap = reg; - } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { + } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { sc->msk_bustype = MSK_PCIX_BUS; sc->msk_pcixcap = reg; } else diff --git a/sys/dev/mxge/if_mxge.c b/sys/dev/mxge/if_mxge.c index 4a49c5abd9f5..6e6d6499700f 100644 --- a/sys/dev/mxge/if_mxge.c +++ b/sys/dev/mxge/if_mxge.c @@ -553,7 +553,7 @@ mxge_firmware_probe(mxge_softc_t *sc) * Verify the max read request size was set to 4KB * before trying the test with 4KB. */ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { pectl = pci_read_config(dev, reg + 0x8, 2); if ((pectl & (5 << 12)) != (5 << 12)) { device_printf(dev, "Max Read Req. size != 4k (0x%x\n", @@ -3731,7 +3731,7 @@ mxge_setup_cfg_space(mxge_softc_t *sc) uint16_t cmd, lnk, pectl; /* find the PCIe link width and set max read request to 4KB*/ - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { lnk = pci_read_config(dev, reg + 0x12, 2); sc->link_width = (lnk >> 4) & 0x3f; @@ -3760,7 +3760,7 @@ mxge_read_reboot(mxge_softc_t *sc) uint32_t vs; /* find the vendor specific offset */ - if (pci_find_extcap(dev, PCIY_VENDOR, &vs) != 0) { + if (pci_find_cap(dev, PCIY_VENDOR, &vs) != 0) { device_printf(sc->dev, "could not find vendor specific offset\n"); return (uint32_t)-1; diff --git a/sys/dev/nfe/if_nfe.c b/sys/dev/nfe/if_nfe.c index a79e43f2acb4..094fe03f7a75 100644 --- a/sys/dev/nfe/if_nfe.c +++ b/sys/dev/nfe/if_nfe.c @@ -363,7 +363,7 @@ nfe_attach(device_t dev) return (ENXIO); } - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { uint16_t v, width; v = pci_read_config(dev, reg + 0x08, 2); @@ -596,7 +596,7 @@ nfe_attach(device_t dev) IFCAP_VLAN_HWTSO; } - if (pci_find_extcap(dev, PCIY_PMG, ®) == 0) + if (pci_find_cap(dev, PCIY_PMG, ®) == 0) ifp->if_capabilities |= IFCAP_WOL_MAGIC; ifp->if_capenable = ifp->if_capabilities; @@ -3354,7 +3354,7 @@ nfe_set_wol(struct nfe_softc *sc) NFE_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) + if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) return; ifp = sc->nfe_ifp; if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) diff --git a/sys/dev/nge/if_nge.c b/sys/dev/nge/if_nge.c index aef2269921b8..ef92ff50d90d 100644 --- a/sys/dev/nge/if_nge.c +++ b/sys/dev/nge/if_nge.c @@ -1061,7 +1061,7 @@ nge_attach(device_t dev) * supply(3VAUX) to drive PME such that checking PCI power * management capability is necessary. */ - if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &i) == 0) + if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0) ifp->if_capabilities |= IFCAP_WOL; ifp->if_capenable = ifp->if_capabilities; @@ -2689,7 +2689,7 @@ nge_wol(struct nge_softc *sc) NGE_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &pmc) != 0) + if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0) return; ifp = sc->nge_ifp; @@ -2776,7 +2776,7 @@ nge_resume(device_t dev) NGE_LOCK(sc); ifp = sc->nge_ifp; - if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2); diff --git a/sys/dev/pci/hostb_pci.c b/sys/dev/pci/hostb_pci.c index ca1b2f61542a..2e1d61144f6a 100644 --- a/sys/dev/pci/hostb_pci.c +++ b/sys/dev/pci/hostb_pci.c @@ -78,7 +78,7 @@ pci_hostb_attach(device_t dev) * If AGP capabilities are present on this device, then create * an AGP child. */ - if (pci_find_extcap(dev, PCIY_AGP, NULL) == 0) + if (pci_find_cap(dev, PCIY_AGP, NULL) == 0) device_add_child(dev, "agp", -1); bus_generic_attach(dev); return (0); diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c index 2d9d4d7b12e1..37dd62fa6177 100644 --- a/sys/dev/re/if_re.c +++ b/sys/dev/re/if_re.c @@ -1237,7 +1237,7 @@ re_attach(device_t dev) msic = pci_msi_count(dev); msixc = pci_msix_count(dev); - if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) sc->rl_flags |= RL_FLAG_PCIE; if (bootverbose) { device_printf(dev, "MSI count : %d\n", msic); @@ -1561,7 +1561,7 @@ re_attach(device_t dev) if (ifp->if_capabilities & IFCAP_HWCSUM) ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; /* Enable WOL if PM is supported. */ - if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) + if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) ifp->if_capabilities |= IFCAP_WOL; ifp->if_capenable = ifp->if_capabilities; /* @@ -3565,7 +3565,7 @@ re_setwol(struct rl_softc *sc) RL_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) + if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) return; ifp = sc->rl_ifp; @@ -3633,7 +3633,7 @@ re_clrwol(struct rl_softc *sc) RL_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) + if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) return; /* Enable config register write. */ diff --git a/sys/dev/siba/siba_core.c b/sys/dev/siba/siba_core.c index 979ac1406a65..2b1a84f6eca0 100644 --- a/sys/dev/siba/siba_core.c +++ b/sys/dev/siba/siba_core.c @@ -362,7 +362,7 @@ siba_scan(struct siba_softc *siba) case SIBA_DEVID_PCI: case SIBA_DEVID_PCIE: n_pci++; - error = pci_find_extcap(siba->siba_dev, PCIY_EXPRESS, + error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS, &base); is_pcie = (error == 0) ? 1 : 0; diff --git a/sys/dev/sis/if_sis.c b/sys/dev/sis/if_sis.c index feef0bf460e9..39bd58439f7a 100644 --- a/sys/dev/sis/if_sis.c +++ b/sys/dev/sis/if_sis.c @@ -1192,7 +1192,7 @@ sis_attach(device_t dev) ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; IFQ_SET_READY(&ifp->if_snd); - if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { if (sc->sis_type == SIS_TYPE_83815) ifp->if_capabilities |= IFCAP_WOL; else @@ -2472,7 +2472,7 @@ sis_wol(struct sis_softc *sc) /* Enable silent RX mode. */ SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); } else { - if (pci_find_extcap(sc->sis_dev, PCIY_PMG, &pmc) != 0) + if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) return; val = 0; if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) diff --git a/sys/dev/ste/if_ste.c b/sys/dev/ste/if_ste.c index e201d4260055..3074538bf2c5 100644 --- a/sys/dev/ste/if_ste.c +++ b/sys/dev/ste/if_ste.c @@ -1176,7 +1176,7 @@ ste_attach(device_t dev) */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_MTU; - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) ifp->if_capabilities |= IFCAP_WOL_MAGIC; ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING @@ -2157,7 +2157,7 @@ ste_resume(device_t dev) sc = device_get_softc(dev); STE_LOCK(sc); - if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); @@ -2261,7 +2261,7 @@ ste_setwol(struct ste_softc *sc) STE_LOCK_ASSERT(sc); - if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { + if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { /* Disable WOL. */ CSR_READ_1(sc, STE_WAKE_EVENT); CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); diff --git a/sys/dev/txp/if_txp.c b/sys/dev/txp/if_txp.c index 52d5c5f8546e..e51489f54899 100644 --- a/sys/dev/txp/if_txp.c +++ b/sys/dev/txp/if_txp.c @@ -423,7 +423,7 @@ txp_attach(device_t dev) * advertise the whole capability anyway. */ ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM; - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) ifp->if_capabilities |= IFCAP_WOL_MAGIC; /* Enable all capabilities. */ ifp->if_capenable = ifp->if_capabilities; @@ -1153,7 +1153,7 @@ txp_suspend(device_t dev) WRITE_REG(sc, TXP_IER, TXP_INTR_NONE); WRITE_REG(sc, TXP_IMR, TXP_INTR_ALL); txp_sleep(sc, sc->sc_ifp->if_capenable); - if (pci_find_extcap(sc->sc_dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->sc_dev, PCIY_PMG, &pmc) == 0) { /* Request PME. */ pmstat = pci_read_config(sc->sc_dev, pmc + PCIR_POWER_STATUS, 2); @@ -1178,7 +1178,7 @@ txp_resume(device_t dev) sc = device_get_softc(dev); TXP_LOCK(sc); - if (pci_find_extcap(sc->sc_dev, PCIY_PMG, &pmc) == 0) { + if (pci_find_cap(sc->sc_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->sc_dev, pmc + PCIR_POWER_STATUS, 2); diff --git a/sys/dev/vge/if_vge.c b/sys/dev/vge/if_vge.c index 20a0df4b242a..4549bb08bca9 100644 --- a/sys/dev/vge/if_vge.c +++ b/sys/dev/vge/if_vge.c @@ -1004,12 +1004,12 @@ vge_attach(device_t dev) goto fail; } - if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { + if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { sc->vge_flags |= VGE_FLAG_PCIE; sc->vge_expcap = cap; } else sc->vge_flags |= VGE_FLAG_JUMBO; - if (pci_find_extcap(dev, PCIY_PMG, &cap) == 0) { + if (pci_find_cap(dev, PCIY_PMG, &cap) == 0) { sc->vge_flags |= VGE_FLAG_PMCAP; sc->vge_pmcap = cap; } diff --git a/sys/dev/vr/if_vr.c b/sys/dev/vr/if_vr.c index 49555757b77a..4dabdc3df325 100644 --- a/sys/dev/vr/if_vr.c +++ b/sys/dev/vr/if_vr.c @@ -696,7 +696,7 @@ vr_attach(device_t dev) } if (sc->vr_revid >= REV_ID_VT6102_A && - pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) + pci_find_cap(dev, PCIY_PMG, &pmc) == 0) ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; /* Rhine supports oversized VLAN frame. */ @@ -711,7 +711,7 @@ vr_attach(device_t dev) * shuts down. Be sure to kick it in the head to wake it * up again. */ - if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) + if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); /* @@ -2494,7 +2494,7 @@ vr_setwol(struct vr_softc *sc) VR_LOCK_ASSERT(sc); if (sc->vr_revid < REV_ID_VT6102_A || - pci_find_extcap(sc->vr_dev, PCIY_PMG, &pmc) != 0) + pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) return; ifp = sc->vr_ifp; diff --git a/sys/dev/xl/if_xl.c b/sys/dev/xl/if_xl.c index 43005e66967e..1db6ece71f98 100644 --- a/sys/dev/xl/if_xl.c +++ b/sys/dev/xl/if_xl.c @@ -1407,7 +1407,7 @@ xl_attach(device_t dev) /* Check availability of WOL. */ if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && - pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) { + pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { sc->xl_pmcap = pmcap; sc->xl_flags |= XL_FLAG_WOL; sinfo2 = 0; diff --git a/sys/ofed/include/linux/pci.h b/sys/ofed/include/linux/pci.h index e4fb5f54ff1a..f9828ef3a282 100644 --- a/sys/ofed/include/linux/pci.h +++ b/sys/ofed/include/linux/pci.h @@ -299,7 +299,7 @@ pci_find_capability(struct pci_dev *pdev, int capid) { int reg; - if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) + if (pci_find_cap(pdev->dev.bsddev, capid, ®)) return (0); return (reg); } diff --git a/sys/pci/if_rl.c b/sys/pci/if_rl.c index f2170099cbc9..85250eb21ebb 100644 --- a/sys/pci/if_rl.c +++ b/sys/pci/if_rl.c @@ -939,7 +939,7 @@ rl_attach(device_t dev) ifp->if_capabilities = IFCAP_VLAN_MTU; /* Check WOL for RTL8139B or newer controllers. */ if (sc->rl_type == RL_8139 && - pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { + pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; switch (hwrev) { case RL_HWREV_8139B: @@ -2122,7 +2122,7 @@ rl_resume(device_t dev) RL_LOCK(sc); if ((ifp->if_capabilities & IFCAP_WOL) != 0 && - pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { + pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); @@ -2187,7 +2187,7 @@ rl_setwol(struct rl_softc *sc) ifp = sc->rl_ifp; if ((ifp->if_capabilities & IFCAP_WOL) == 0) return; - if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) + if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) return; /* Enable config register write. */ |