diff options
25 files changed, 11354 insertions, 11044 deletions
diff --git a/sys/dev/aic7xxx/93cx6.c b/sys/dev/aic7xxx/93cx6.c deleted file mode 100644 index 62a4aeefa9c1..000000000000 --- a/sys/dev/aic7xxx/93cx6.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Interface for the 93C66/56/46/26/06 serial eeprom parts. - * - * Copyright (c) 1995, 1996 Daniel M. Eischen - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice immediately at the beginning of the file, without modification, - * this list of conditions, and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Absolutely no warranty of function or purpose is made by the author - * Daniel M. Eischen. - * 4. Modifications may be freely made to this file if the above conditions - * are met. - * - * $FreeBSD$ - */ - -/* - * The instruction set of the 93C66/56/46/26/06 chips are as follows: - * - * Start OP * - * Function Bit Code Address** Data Description - * ------------------------------------------------------------------- - * READ 1 10 A5 - A0 Reads data stored in memory, - * starting at specified address - * EWEN 1 00 11XXXX Write enable must preceed - * all programming modes - * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0 - * WRITE 1 01 A5 - A0 D15 - D0 Writes register - * ERAL 1 00 10XXXX Erase all registers - * WRAL 1 00 01XXXX D15 - D0 Writes to all registers - * EWDS 1 00 00XXXX Disables all programming - * instructions - * *Note: A value of X for address is a don't care condition. - * **Note: There are 8 address bits for the 93C56/66 chips unlike - * the 93C46/26/06 chips which have 6 address bits. - * - * The 93C46 has a four wire interface: clock, chip select, data in, and - * data out. In order to perform one of the above functions, you need - * to enable the chip select for a clock period (typically a minimum of - * 1 usec, with the clock high and low a minimum of 750 and 250 nsec - * respectively). While the chip select remains high, you can clock in - * the instructions (above) starting with the start bit, followed by the - * OP code, Address, and Data (if needed). For the READ instruction, the - * requested 16-bit register contents is read from the data out line but - * is preceded by an initial zero (leading 0, followed by 16-bits, MSB - * first). The clock cycling from low to high initiates the next data - * bit to be sent from the chip. - * - */ - -#include "opt_aic7xxx.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <machine/bus_memio.h> -#include <machine/bus_pio.h> -#include <machine/bus.h> -#include <dev/aic7xxx/93cx6.h> - -/* - * Right now, we only have to read the SEEPROM. But we make it easier to - * add other 93Cx6 functions. - */ -static struct seeprom_cmd { - unsigned char len; - unsigned char bits[3]; -} seeprom_read = {3, {1, 1, 0}}; - -/* - * Wait for the SEERDY to go high; about 800 ns. - */ -#define CLOCK_PULSE(sd, rdy) \ - while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \ - ; /* Do nothing */ \ - } \ - (void)SEEPROM_INB(sd); /* Clear clock */ - -/* - * Read the serial EEPROM and returns 1 if successful and 0 if - * not successful. - */ -int -read_seeprom(sd, buf, start_addr, count) - struct seeprom_descriptor *sd; - uint16_t *buf; - bus_size_t start_addr; - bus_size_t count; -{ - int i = 0; - u_int k = 0; - uint16_t v; - uint8_t temp; - - /* - * Read the requested registers of the seeprom. The loop - * will range from 0 to count-1. - */ - for (k = start_addr; k < count + start_addr; k++) { - /* Send chip select for one clock cycle. */ - temp = sd->sd_MS ^ sd->sd_CS; - SEEPROM_OUTB(sd, temp ^ sd->sd_CK); - CLOCK_PULSE(sd, sd->sd_RDY); - - /* - * Now we're ready to send the read command followed by the - * address of the 16-bit register we want to read. - */ - for (i = 0; i < seeprom_read.len; i++) { - if (seeprom_read.bits[i] != 0) - temp ^= sd->sd_DO; - SEEPROM_OUTB(sd, temp); - CLOCK_PULSE(sd, sd->sd_RDY); - SEEPROM_OUTB(sd, temp ^ sd->sd_CK); - CLOCK_PULSE(sd, sd->sd_RDY); - if (seeprom_read.bits[i] != 0) - temp ^= sd->sd_DO; - } - /* Send the 6 or 8 bit address (MSB first, LSB last). */ - for (i = (sd->sd_chip - 1); i >= 0; i--) { - if ((k & (1 << i)) != 0) - temp ^= sd->sd_DO; - SEEPROM_OUTB(sd, temp); - CLOCK_PULSE(sd, sd->sd_RDY); - SEEPROM_OUTB(sd, temp ^ sd->sd_CK); - CLOCK_PULSE(sd, sd->sd_RDY); - if ((k & (1 << i)) != 0) - temp ^= sd->sd_DO; - } - - /* - * Now read the 16 bit register. An initial 0 precedes the - * register contents which begins with bit 15 (MSB) and ends - * with bit 0 (LSB). The initial 0 will be shifted off the - * top of our word as we let the loop run from 0 to 16. - */ - v = 0; - for (i = 16; i >= 0; i--) { - SEEPROM_OUTB(sd, temp); - CLOCK_PULSE(sd, sd->sd_RDY); - v <<= 1; - if (SEEPROM_DATA_INB(sd) & sd->sd_DI) - v |= 1; - SEEPROM_OUTB(sd, temp ^ sd->sd_CK); - CLOCK_PULSE(sd, sd->sd_RDY); - } - - buf[k - start_addr] = v; - - /* Reset the chip select for the next command cycle. */ - temp = sd->sd_MS; - SEEPROM_OUTB(sd, temp); - CLOCK_PULSE(sd, sd->sd_RDY); - SEEPROM_OUTB(sd, temp ^ sd->sd_CK); - CLOCK_PULSE(sd, sd->sd_RDY); - SEEPROM_OUTB(sd, temp); - CLOCK_PULSE(sd, sd->sd_RDY); - } -#ifdef AHC_DUMP_EEPROM - printf("\nSerial EEPROM:\n\t"); - for (k = 0; k < count; k = k + 1) { - if (((k % 8) == 0) && (k != 0)) { - printf ("\n\t"); - } - printf (" 0x%x", buf[k]); - } - printf ("\n"); -#endif - return (1); -} diff --git a/sys/dev/aic7xxx/93cx6.h b/sys/dev/aic7xxx/93cx6.h deleted file mode 100644 index 8fd7bb9be1ed..000000000000 --- a/sys/dev/aic7xxx/93cx6.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Interface to the 93C46 serial EEPROM that is used to store BIOS - * settings for the aic7xxx based adaptec SCSI controllers. It can - * also be used for 93C26 and 93C06 serial EEPROMS. - * - * Copyright (c) 1994, 1995 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include <sys/param.h> -#if !defined(__NetBSD__) -#include <sys/systm.h> -#endif - -#ifdef _KERNEL - -typedef enum { - C46 = 6, - C56_66 = 8 -} seeprom_chip_t; - -struct seeprom_descriptor { - bus_space_tag_t sd_tag; - bus_space_handle_t sd_bsh; - bus_size_t sd_control_offset; - bus_size_t sd_status_offset; - bus_size_t sd_dataout_offset; - seeprom_chip_t sd_chip; - uint16_t sd_MS; - uint16_t sd_RDY; - uint16_t sd_CS; - uint16_t sd_CK; - uint16_t sd_DO; - uint16_t sd_DI; -}; - -/* - * This function will read count 16-bit words from the serial EEPROM and - * return their value in buf. The port address of the aic7xxx serial EEPROM - * control register is passed in as offset. The following parameters are - * also passed in: - * - * CS - Chip select - * CK - Clock - * DO - Data out - * DI - Data in - * RDY - SEEPROM ready - * MS - Memory port mode select - * - * A failed read attempt returns 0, and a successful read returns 1. - */ - -#define SEEPROM_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset) -#define SEEPROM_OUTB(sd, value) \ - bus_space_write_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset, value) -#define SEEPROM_STATUS_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_status_offset) -#define SEEPROM_DATA_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_dataout_offset) - -int read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, - bus_size_t start_addr, bus_size_t count); - -#endif /* _KERNEL */ diff --git a/sys/dev/aic7xxx/Makefile b/sys/dev/aic7xxx/Makefile deleted file mode 100644 index c5575a8e7e88..000000000000 --- a/sys/dev/aic7xxx/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# $FreeBSD$ - -PROG= aicasm - -CSRCS= aicasm.c aicasm_symbol.c -GENSRCS= aicasm_gram.c aicasm_scan.c - -GENHDRS= y.tab.h - -SRCS= ${GENSRCS} ${CSRCS} -CLEANFILES+= ${GENSRCS} ${GENHDRS} y.output -DPADD+= ${LIBL} -LDADD+= -ll - -# Correct path for kernel builds -# Don't rely on the kernel's .depend file -.ifdef MAKESRCPATH -.PATH: ${MAKESRCPATH} -DEPENDFILE= -.endif - -CFLAGS+= -nostdinc -I${.CURDIR}/../.. -I. -I/usr/include -NOMAN= noman - -.ifdef DEBUG -CFLAGS+= -DDEBUG -g -YFLAGS+= -t -LFLAGS+= -d -.endif - -.include <bsd.prog.mk> diff --git a/sys/dev/aic7xxx/ahc_eisa.c b/sys/dev/aic7xxx/ahc_eisa.c index 1e0e16ad8a7c..9e0e3f007e74 100644 --- a/sys/dev/aic7xxx/ahc_eisa.c +++ b/sys/dev/aic7xxx/ahc_eisa.c @@ -1,8 +1,8 @@ /* - * Product specific probe and attach routines for: - * 27/284X and aic7770 motherboard SCSI controllers + * FreeBSD, EISA product support functions + * * - * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 2000 Justin T. Gibbs. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,92 +26,60 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $Id$ + * * $FreeBSD$ */ -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/bus.h> - -#include <machine/bus_pio.h> -#include <machine/bus.h> -#include <machine/resource.h> -#include <sys/rman.h> +#include <dev/aic7xxx/aic7xxx_freebsd.h> #include <dev/eisa/eisaconf.h> -#include <cam/cam.h> -#include <cam/cam_ccb.h> -#include <cam/cam_sim.h> -#include <cam/cam_xpt_sim.h> -#include <cam/scsi/scsi_all.h> - -#include <dev/aic7xxx/aic7xxx.h> -#include <dev/aic7xxx/93cx6.h> - -#include <aic7xxx_reg.h> - -#define EISA_DEVICE_ID_ADAPTEC_AIC7770 0x04907770 -#define EISA_DEVICE_ID_ADAPTEC_274x 0x04907771 -#define EISA_DEVICE_ID_ADAPTEC_284xB 0x04907756 /* BIOS enabled */ -#define EISA_DEVICE_ID_ADAPTEC_284x 0x04907757 /* BIOS disabled*/ - -#define AHC_EISA_SLOT_OFFSET 0xc00 -#define AHC_EISA_IOSIZE 0x100 -#define INTDEF 0x5cul /* Interrupt Definition Register */ - -static void aha2840_load_seeprom(struct ahc_softc *ahc); - -static const char *aic7770_match(eisa_id_t type); - -static const char* -aic7770_match(eisa_id_t type) -{ - switch (type) { - case EISA_DEVICE_ID_ADAPTEC_AIC7770: - return ("Adaptec aic7770 SCSI host adapter"); - break; - case EISA_DEVICE_ID_ADAPTEC_274x: - return ("Adaptec 274X SCSI host adapter"); - break; - case EISA_DEVICE_ID_ADAPTEC_284xB: - case EISA_DEVICE_ID_ADAPTEC_284x: - return ("Adaptec 284X SCSI host adapter"); - break; - default: - break; - } - return (NULL); -} - static int aic7770_probe(device_t dev) { - const char *desc; + struct aic7770_identity *entry; + struct resource *regs; uint32_t iobase; - uint32_t irq; - uint8_t intdef; - uint8_t hcntrl; - int shared; - - desc = aic7770_match(eisa_get_id(dev)); - if (!desc) + bus_space_handle_t bsh; + bus_space_tag_t tag; + u_int irq; + u_int intdef; + u_int hcntrl; + int shared; + int rid; + int error; + + entry = aic7770_find_device(eisa_get_id(dev)); + if (entry == NULL) return (ENXIO); - device_set_desc(dev, desc); + device_set_desc(dev, entry->name); iobase = (eisa_get_slot(dev) * EISA_SLOT_SIZE) + AHC_EISA_SLOT_OFFSET; - /* Pause the card preseving the IRQ type */ - hcntrl = inb(iobase + HCNTRL) & IRQMS; + eisa_add_iospace(dev, iobase, AHC_EISA_IOSIZE, RESVADDR_NONE); + + regs = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, + 0, ~0, 1, RF_ACTIVE); + if (regs == NULL) { + device_printf(dev, "Unable to map I/O space?!\n"); + return ENOMEM; + } - outb(iobase + HCNTRL, hcntrl | PAUSE); + tag = rman_get_bustag(regs); + bsh = rman_get_bushandle(regs); + error = 0; - eisa_add_iospace(dev, iobase, AHC_EISA_IOSIZE, RESVADDR_NONE); - intdef = inb(INTDEF + iobase); - shared = (intdef & 0x80) ? EISA_TRIGGER_EDGE : EISA_TRIGGER_LEVEL; - irq = intdef & 0xf; + /* Pause the card preseving the IRQ type */ + hcntrl = bus_space_read_1(tag, bsh, HCNTRL) & IRQMS; + bus_space_write_1(tag, bsh, HCNTRL, hcntrl | PAUSE); + while ((bus_space_read_1(tag, bsh, HCNTRL) & PAUSE) == 0) + ; + + /* Make sure we have a valid interrupt vector */ + intdef = bus_space_read_1(tag, bsh, INTDEF); + shared = (intdef & EDGE_TRIG) ? EISA_TRIGGER_EDGE : EISA_TRIGGER_LEVEL; + irq = intdef & VECTOR; switch (irq) { case 9: case 10: @@ -119,342 +87,107 @@ aic7770_probe(device_t dev) case 12: case 14: case 15: - break; + break; default: - printf("aic7770 at slot %d: illegal " - "irq setting %d\n", eisa_get_slot(dev), - intdef); - irq = 0; - break; + printf("aic7770 at slot %d: illegal irq setting %d\n", + eisa_get_slot(dev), intdef); + error = ENXIO; } - if (irq == 0) - return ENXIO; - eisa_add_intr(dev, irq, shared); + if (error == 0) + eisa_add_intr(dev, irq, shared); - return 0; + bus_release_resource(dev, SYS_RES_IOPORT, rid, regs); + return (error); } static int aic7770_attach(device_t dev) { - struct ahc_probe_config probe_config; - bus_dma_tag_t parent_dmat; - struct ahc_softc *ahc; - struct resource *io; - int error, rid; + struct aic7770_identity *entry; + struct ahc_softc *ahc; + char *name; + int error; - rid = 0; - io = NULL; - ahc = NULL; - ahc_init_probe_config(&probe_config); - switch (eisa_get_id(dev)) { - case EISA_DEVICE_ID_ADAPTEC_274x: - case EISA_DEVICE_ID_ADAPTEC_AIC7770: - probe_config.chip = AHC_AIC7770|AHC_EISA; - break; - case EISA_DEVICE_ID_ADAPTEC_284xB: - case EISA_DEVICE_ID_ADAPTEC_284x: - probe_config.chip = AHC_AIC7770|AHC_VL; - break; - default: - printf("aic7770_attach: Unknown device type!\n"); - goto bad; - } + entry = aic7770_find_device(eisa_get_id(dev)); + if (entry == NULL) + return (ENXIO); - probe_config.description = aic7770_match(eisa_get_id(dev)); - probe_config.channel = 'A'; - probe_config.channel_b = 'B'; - probe_config.features = AHC_AIC7770_FE; - probe_config.bugs |= AHC_TMODE_WIDEODD_BUG; - probe_config.flags |= AHC_PAGESCBS; - /* XXX Should be a child of the EISA bus dma tag */ + /* + * Allocate a softc for this card and + * set it up for attachment by our + * common detect routine. + */ + name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT); + if (name == NULL) + return (ENOMEM); + strcpy(name, device_get_nameunit(dev)); + ahc = ahc_alloc(NULL, name); + if (ahc == NULL) + return (ENOMEM); + + /* Allocate a dmatag for our SCB DMA maps */ + /* XXX Should be a child of the PCI bus dma tag */ error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL, - /*maxsize*/MAXBSIZE, - /*nsegments*/AHC_NSEG, + /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, /*maxsegsz*/AHC_MAXTRANSFER_SIZE, - /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); + /*flags*/BUS_DMA_ALLOCNOW, + &ahc->parent_dmat); if (error != 0) { printf("ahc_eisa_attach: Could not allocate DMA tag " "- error %d\n", error); - goto bad; - } - - io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, - 0, ~0, 1, RF_ACTIVE); - if (!io) { - device_printf(dev, "No I/O space?!\n"); - return ENOMEM; - } - - if (!(ahc = ahc_alloc(dev, io, SYS_RES_IOPORT, rid, - parent_dmat, &probe_config, NULL))) - goto bad; - - io = NULL; - - if (ahc_reset(ahc) != 0) { - goto bad; - } - - /* - * The IRQMS bit enables level sensitive interrupts. Only allow - * IRQ sharing if it's set. - */ - rid = 0; - ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, - 0, ~0, 1, RF_ACTIVE); - if (ahc->irq == NULL) { - device_printf(dev, "Can't allocate interrupt\n"); - goto bad; - } - ahc->irq_res_type = SYS_RES_IRQ; - - /* - * Tell the user what type of interrupts we're using. - * usefull for debugging irq problems - */ - if (bootverbose) { - printf("%s: Using %s Interrupts\n", - ahc_name(ahc), - ahc->pause & IRQMS ? - "Level Sensitive" : "Edge Triggered"); - } - - /* - * Now that we know we own the resources we need, do the - * card initialization. - * - * First, the aic7770 card specific setup. - */ - switch (probe_config.chip & (AHC_EISA|AHC_VL)) { - case AHC_EISA: - { - u_int biosctrl; - u_int scsiconf; - u_int scsiconf1; -#if DEBUG - int i; -#endif - - biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL); - scsiconf = ahc_inb(ahc, SCSICONF); - scsiconf1 = ahc_inb(ahc, SCSICONF + 1); - -#if DEBUG - for (i = TARG_SCSIRATE; i <= HA_274_BIOSCTRL; i+=8) { - printf("0x%x, 0x%x, 0x%x, 0x%x, " - "0x%x, 0x%x, 0x%x, 0x%x\n", - ahc_inb(ahc, i), - ahc_inb(ahc, i+1), - ahc_inb(ahc, i+2), - ahc_inb(ahc, i+3), - ahc_inb(ahc, i+4), - ahc_inb(ahc, i+5), - ahc_inb(ahc, i+6), - ahc_inb(ahc, i+7)); - } -#endif - - /* Get the primary channel information */ - if ((biosctrl & CHANNEL_B_PRIMARY) != 0) - ahc->flags |= AHC_CHANNEL_B_PRIMARY; - - if ((biosctrl & BIOSMODE) == BIOSDISABLED) { - ahc->flags |= AHC_USEDEFAULTS; - } else { - if ((ahc->features & AHC_WIDE) != 0) { - ahc->our_id = scsiconf1 & HWSCSIID; - if (scsiconf & TERM_ENB) - ahc->flags |= AHC_TERM_ENB_A; - } else { - ahc->our_id = scsiconf & HSCSIID; - ahc->our_id_b = scsiconf1 & HSCSIID; - if (scsiconf & TERM_ENB) - ahc->flags |= AHC_TERM_ENB_A; - if (scsiconf1 & TERM_ENB) - ahc->flags |= AHC_TERM_ENB_B; - } - } - /* - * We have no way to tell, so assume extended - * translation is enabled. - */ - ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B; - break; - } - case AHC_VL: - { - aha2840_load_seeprom(ahc); - break; - } - default: - break; - } - - /* - * See if we have a Rev E or higher aic7770. Anything below a - * Rev E will have a R/O autoflush disable configuration bit. - */ - { - char *id_string; - uint8_t sblkctl; - uint8_t sblkctl_orig; - - sblkctl_orig = ahc_inb(ahc, SBLKCTL); - sblkctl = sblkctl_orig ^ AUTOFLUSHDIS; - ahc_outb(ahc, SBLKCTL, sblkctl); - sblkctl = ahc_inb(ahc, SBLKCTL); - if (sblkctl != sblkctl_orig) { - id_string = "aic7770 >= Rev E, "; - /* - * Ensure autoflush is enabled - */ - sblkctl &= ~AUTOFLUSHDIS; - ahc_outb(ahc, SBLKCTL, sblkctl); - - } else - id_string = "aic7770 <= Rev C, "; - - printf("%s: %s", ahc_name(ahc), id_string); - } - - /* Setup the FIFO threshold and the bus off time */ - { - uint8_t hostconf = ahc_inb(ahc, HOSTCONF); - ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH); - ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF); + ahc_free(ahc); + return (ENOMEM); } - - /* - * Generic aic7xxx initialization. - */ - if (ahc_init(ahc)) { - /* - * The board's IRQ line is not yet enabled so it's safe - * to release the irq. - */ - goto bad; + ahc->dev_softc = dev; + error = aic7770_config(ahc, entry); + if (error != 0) { + ahc_free(ahc); + return (error); } - /* - * Enable the board's BUS drivers - */ - ahc_outb(ahc, BCTL, ENABLE); - - /* Attach sub-devices - always succeeds */ ahc_attach(ahc); - - return 0; - - bad: - if (ahc != NULL) - ahc_free(ahc); - - if (io != NULL) - bus_release_resource(dev, SYS_RES_IOPORT, 0, io); - - return -1; + return (0); } -/* - * Read the 284x SEEPROM. - */ -static void -aha2840_load_seeprom(struct ahc_softc *ahc) +int +aic7770_map_registers(struct ahc_softc *ahc) { - struct seeprom_descriptor sd; - struct seeprom_config sc; - uint16_t checksum = 0; - uint8_t scsi_conf; - int have_seeprom; + struct resource *regs; + int rid; - sd.sd_tag = ahc->tag; - sd.sd_bsh = ahc->bsh; - sd.sd_control_offset = SEECTL_2840; - sd.sd_status_offset = STATUS_2840; - sd.sd_dataout_offset = STATUS_2840; - sd.sd_chip = C46; - sd.sd_MS = 0; - sd.sd_RDY = EEPROM_TF; - sd.sd_CS = CS_2840; - sd.sd_CK = CK_2840; - sd.sd_DO = DO_2840; - sd.sd_DI = DI_2840; - - if (bootverbose) - printf("%s: Reading SEEPROM...", ahc_name(ahc)); - have_seeprom = read_seeprom(&sd, - (uint16_t *)&sc, - /*start_addr*/0, - sizeof(sc)/2); - - if (have_seeprom) { - /* Check checksum */ - int i; - int maxaddr = (sizeof(sc)/2) - 1; - uint16_t *scarray = (uint16_t *)≻ - - for (i = 0; i < maxaddr; i++) - checksum = checksum + scarray[i]; - if (checksum != sc.checksum) { - if(bootverbose) - printf ("checksum error\n"); - have_seeprom = 0; - } else if (bootverbose) { - printf("done.\n"); - } + regs = bus_alloc_resource(ahc->dev_softc, SYS_RES_IOPORT, + &rid, 0, ~0, 1, RF_ACTIVE); + if (regs == NULL) { + device_printf(ahc->dev_softc, "Unable to map I/O space?!\n"); + return ENOMEM; } + ahc->platform_data->regs_res_type = SYS_RES_IOPORT; + ahc->platform_data->regs_res_id = rid, + ahc->platform_data->regs = regs; + ahc->tag = rman_get_bustag(regs); + ahc->bsh = rman_get_bushandle(regs); + return (0); +} - if (!have_seeprom) { - if (bootverbose) - printf("%s: No SEEPROM available\n", ahc_name(ahc)); - ahc->flags |= AHC_USEDEFAULTS; - } else { - /* - * Put the data we've collected down into SRAM - * where ahc_init will find it. - */ - int i; - int max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8; - uint16_t discenable; - - discenable = 0; - for (i = 0; i < max_targ; i++){ - uint8_t target_settings; - target_settings = (sc.device_flags[i] & CFXFER) << 4; - if (sc.device_flags[i] & CFSYNCH) - target_settings |= SOFS; - if (sc.device_flags[i] & CFWIDEB) - target_settings |= WIDEXFER; - if (sc.device_flags[i] & CFDISC) - discenable |= (0x01 << i); - ahc_outb(ahc, TARG_SCSIRATE + i, target_settings); - } - ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); - ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); - - ahc->our_id = sc.brtime_id & CFSCSIID; - - scsi_conf = (ahc->our_id & 0x7); - if (sc.adapter_control & CFSPARITY) - scsi_conf |= ENSPCHK; - if (sc.adapter_control & CFRESETB) - scsi_conf |= RESET_SCSI; - - if (sc.bios_control & CF284XEXTEND) - ahc->flags |= AHC_EXTENDED_TRANS_A; - /* Set SCSICONF info */ - ahc_outb(ahc, SCSICONF, scsi_conf); - - if (sc.adapter_control & CF284XSTERM) - ahc->flags |= AHC_TERM_ENB_A; - } +int +aic7770_map_int(struct ahc_softc *ahc) +{ + int zero; + + zero = 0; + ahc->platform_data->irq = + bus_alloc_resource(ahc->dev_softc, SYS_RES_IRQ, &zero, + 0, ~0, 1, RF_ACTIVE); + if (ahc->platform_data->irq == NULL) + return (ENOMEM); + ahc->platform_data->irq_res_type = SYS_RES_IRQ; + return (0); } static device_method_t ahc_eisa_methods[] = { diff --git a/sys/dev/aic7xxx/ahc_pci.c b/sys/dev/aic7xxx/ahc_pci.c index 5ca35fcad43c..3bb1a40338f6 100644 --- a/sys/dev/aic7xxx/ahc_pci.c +++ b/sys/dev/aic7xxx/ahc_pci.c @@ -1,7 +1,5 @@ /* - * Product specific probe and attach routines for: - * 3940, 2940, aic7895, aic7890, aic7880, - * aic7870, aic7860 and aic7850 SCSI controllers + * FreeBSD, PCI product support functions * * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs * All rights reserved. @@ -30,568 +28,19 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $Id$ + * * $FreeBSD$ */ -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/bus.h> - -#include <pci/pcireg.h> -#include <pci/pcivar.h> - -#include <machine/bus_memio.h> -#include <machine/bus_pio.h> -#include <machine/bus.h> -#include <machine/resource.h> -#include <machine/clock.h> -#include <sys/rman.h> - -#include <cam/cam.h> -#include <cam/cam_ccb.h> -#include <cam/cam_sim.h> -#include <cam/cam_xpt_sim.h> - -#include <cam/scsi/scsi_all.h> - -#include <dev/aic7xxx/aic7xxx.h> -#include <dev/aic7xxx/93cx6.h> - -#include <aic7xxx_reg.h> - -#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ -#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ - -static __inline uint64_t -ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) -{ - uint64_t id; - - id = subvendor - | (subdevice << 16) - | ((uint64_t)vendor << 32) - | ((uint64_t)device << 48); - - return (id); -} - -#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull -#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull -#define ID_AIC7850 0x5078900400000000ull -#define ID_AHA_2910_15_20_30C 0x5078900478509004ull -#define ID_AIC7855 0x5578900400000000ull -#define ID_AIC7859 0x3860900400000000ull -#define ID_AHA_2930CU 0x3860900438699004ull -#define ID_AIC7860 0x6078900400000000ull -#define ID_AIC7860C 0x6078900478609004ull -#define ID_AHA_2940AU_0 0x6178900400000000ull -#define ID_AHA_2940AU_1 0x6178900478619004ull -#define ID_AHA_2940AU_CN 0x2178900478219004ull -#define ID_AHA_2930C_VAR 0x6038900438689004ull +#include <dev/aic7xxx/aic7xxx_freebsd.h> -#define ID_AIC7870 0x7078900400000000ull -#define ID_AHA_2940 0x7178900400000000ull -#define ID_AHA_3940 0x7278900400000000ull -#define ID_AHA_398X 0x7378900400000000ull -#define ID_AHA_2944 0x7478900400000000ull -#define ID_AHA_3944 0x7578900400000000ull -#define ID_AHA_4944 0x7678900400000000ull - -#define ID_AIC7880 0x8078900400000000ull -#define ID_AIC7880_B 0x8078900478809004ull -#define ID_AHA_2940U 0x8178900400000000ull -#define ID_AHA_3940U 0x8278900400000000ull -#define ID_AHA_2944U 0x8478900400000000ull -#define ID_AHA_3944U 0x8578900400000000ull -#define ID_AHA_398XU 0x8378900400000000ull -#define ID_AHA_4944U 0x8678900400000000ull -#define ID_AHA_2940UB 0x8178900478819004ull -#define ID_AHA_2930U 0x8878900478889004ull -#define ID_AHA_2940U_PRO 0x8778900478879004ull -#define ID_AHA_2940U_CN 0x0078900478009004ull - -#define ID_AIC7895 0x7895900478959004ull -#define ID_AIC7895_RAID_PORT 0x7893900478939004ull -#define ID_AHA_2940U_DUAL 0x7895900478919004ull -#define ID_AHA_3940AU 0x7895900478929004ull -#define ID_AHA_3944AU 0x7895900478949004ull - -#define ID_AIC7890 0x001F9005000F9005ull -#define ID_AAA_131U2 0x0013900500039005ull -#define ID_AHA_2930U2 0x0011900501819005ull -#define ID_AHA_2940U2B 0x00109005A1009005ull -#define ID_AHA_2940U2_OEM 0x0010900521809005ull -#define ID_AHA_2940U2 0x00109005A1809005ull -#define ID_AHA_2950U2B 0x00109005E1009005ull - -#define ID_AIC7892 0x008F9005FFFF9005ull -#define ID_AHA_29160 0x00809005E2A09005ull -#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull -#define ID_AHA_29160N 0x0080900562A09005ull -#define ID_AHA_29160B 0x00809005E2209005ull -#define ID_AHA_19160B 0x0081900562A19005ull - -#define ID_AIC7896 0x005F9005FFFF9005ull -#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull -#define ID_AHA_3950U2B_1 0x00509005F5009005ull -#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull -#define ID_AHA_3950U2D_1 0x00519005B5009005ull - -#define ID_AIC7899 0x00CF9005FFFF9005ull -#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ -#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull - -#define ID_AIC7810 0x1078900400000000ull -#define ID_AIC7815 0x7815900400000000ull - -typedef int (ahc_device_setup_t)(device_t, struct ahc_probe_config *); - -static ahc_device_setup_t ahc_aic7850_setup; -static ahc_device_setup_t ahc_aic7855_setup; -static ahc_device_setup_t ahc_aic7859_setup; -static ahc_device_setup_t ahc_aic7860_setup; -static ahc_device_setup_t ahc_aic7870_setup; -static ahc_device_setup_t ahc_aha394X_setup; -static ahc_device_setup_t ahc_aha494X_setup; -static ahc_device_setup_t ahc_aha398X_setup; -static ahc_device_setup_t ahc_aic7880_setup; -static ahc_device_setup_t ahc_2940Pro_setup; -static ahc_device_setup_t ahc_aha394XU_setup; -static ahc_device_setup_t ahc_aha398XU_setup; -static ahc_device_setup_t ahc_aic7890_setup; -static ahc_device_setup_t ahc_aic7892_setup; -static ahc_device_setup_t ahc_aic7895_setup; -static ahc_device_setup_t ahc_aic7896_setup; -static ahc_device_setup_t ahc_aic7899_setup; -static ahc_device_setup_t ahc_raid_setup; -static ahc_device_setup_t ahc_aha394XX_setup; -static ahc_device_setup_t ahc_aha494XX_setup; -static ahc_device_setup_t ahc_aha398XX_setup; - -struct ahc_pci_identity { - uint64_t full_id; - uint64_t id_mask; - char *name; - ahc_device_setup_t *setup; -}; - -struct ahc_pci_identity ahc_pci_ident_table [] = -{ - /* aic7850 based controllers */ - { - ID_AHA_2910_15_20_30C, - ID_ALL_MASK, - "Adaptec 2910/15/20/30C SCSI adapter", - ahc_aic7850_setup - }, - /* aic7859 based controllers */ - { - ID_AHA_2930CU, - ID_ALL_MASK, - "Adaptec 2930CU SCSI adapter", - ahc_aic7859_setup - }, - /* aic7860 based controllers */ - { - ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2940A Ultra SCSI adapter", - ahc_aic7860_setup - }, - { - ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2940A/CN Ultra SCSI adapter", - ahc_aic7860_setup - }, - { - ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2930C SCSI adapter (VAR)", - ahc_aic7860_setup - }, - /* aic7870 based controllers */ - { - ID_AHA_2940, - ID_ALL_MASK, - "Adaptec 2940 SCSI adapter", - ahc_aic7870_setup - }, - { - ID_AHA_3940, - ID_ALL_MASK, - "Adaptec 3940 SCSI adapter", - ahc_aha394X_setup - }, - { - ID_AHA_398X, - ID_ALL_MASK, - "Adaptec 398X SCSI RAID adapter", - ahc_aha398X_setup - }, - { - ID_AHA_2944, - ID_ALL_MASK, - "Adaptec 2944 SCSI adapter", - ahc_aic7870_setup - }, - { - ID_AHA_3944, - ID_ALL_MASK, - "Adaptec 3944 SCSI adapter", - ahc_aha394X_setup - }, - { - ID_AHA_4944, - ID_ALL_MASK, - "Adaptec 4944 SCSI adapter", - ahc_aha494X_setup - }, - /* aic7880 based controllers */ - { - ID_AHA_2940U & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2940 Ultra SCSI adapter", - ahc_aic7880_setup - }, - { - ID_AHA_3940U & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 3940 Ultra SCSI adapter", - ahc_aha394XU_setup - }, - { - ID_AHA_2944U & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2944 Ultra SCSI adapter", - ahc_aic7880_setup - }, - { - ID_AHA_3944U & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 3944 Ultra SCSI adapter", - ahc_aha394XU_setup - }, - { - ID_AHA_398XU & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 398X Ultra SCSI RAID adapter", - ahc_aha398XU_setup - }, - { - /* - * XXX Don't know the slot numbers - * so we can't identify channels - */ - ID_AHA_4944U & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 4944 Ultra SCSI adapter", - ahc_aic7880_setup - }, - { - ID_AHA_2930U & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2930 Ultra SCSI adapter", - ahc_aic7880_setup - }, - { - ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2940 Pro Ultra SCSI adapter", - ahc_2940Pro_setup - }, - { - ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec 2940/CN Ultra SCSI adapter", - ahc_aic7880_setup - }, - /* aic7890 based controllers */ - { - ID_AHA_2930U2, - ID_ALL_MASK, - "Adaptec 2930 Ultra2 SCSI adapter", - ahc_aic7890_setup - }, - { - ID_AHA_2940U2B, - ID_ALL_MASK, - "Adaptec 2940B Ultra2 SCSI adapter", - ahc_aic7890_setup - }, - { - ID_AHA_2940U2_OEM, - ID_ALL_MASK, - "Adaptec 2940 Ultra2 SCSI adapter (OEM)", - ahc_aic7890_setup - }, - { - ID_AHA_2940U2, - ID_ALL_MASK, - "Adaptec 2940 Ultra2 SCSI adapter", - ahc_aic7890_setup - }, - { - ID_AHA_2950U2B, - ID_ALL_MASK, - "Adaptec 2950 Ultra2 SCSI adapter", - ahc_aic7890_setup - }, - { - ID_AAA_131U2, - ID_ALL_MASK, - "Adaptec AAA-131 Ultra2 RAID adapter", - ahc_aic7890_setup - }, - /* aic7892 based controllers */ - { - ID_AHA_29160, - ID_ALL_MASK, - "Adaptec 29160 Ultra160 SCSI adapter", - ahc_aic7892_setup - }, - { - ID_AHA_29160_CPQ, - ID_ALL_MASK, - "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", - ahc_aic7892_setup - }, - { - ID_AHA_29160N, - ID_ALL_MASK, - "Adaptec 29160N Ultra160 SCSI adapter", - ahc_aic7892_setup - }, - { - ID_AHA_29160B, - ID_ALL_MASK, - "Adaptec 29160B Ultra160 SCSI adapter", - ahc_aic7892_setup - }, - { - ID_AHA_19160B, - ID_ALL_MASK, - "Adaptec 19160B Ultra160 SCSI adapter", - ahc_aic7892_setup - }, - /* aic7895 based controllers */ - { - ID_AHA_2940U_DUAL, - ID_ALL_MASK, - "Adaptec 2940/DUAL Ultra SCSI adapter", - ahc_aic7895_setup - }, - { - ID_AHA_3940AU, - ID_ALL_MASK, - "Adaptec 3940A Ultra SCSI adapter", - ahc_aic7895_setup - }, - { - ID_AHA_3944AU, - ID_ALL_MASK, - "Adaptec 3944A Ultra SCSI adapter", - ahc_aic7895_setup - }, - /* aic7896/97 based controllers */ - { - ID_AHA_3950U2B_0, - ID_ALL_MASK, - "Adaptec 3950B Ultra2 SCSI adapter", - ahc_aic7896_setup - }, - { - ID_AHA_3950U2B_1, - ID_ALL_MASK, - "Adaptec 3950B Ultra2 SCSI adapter", - ahc_aic7896_setup - }, - { - ID_AHA_3950U2D_0, - ID_ALL_MASK, - "Adaptec 3950D Ultra2 SCSI adapter", - ahc_aic7896_setup - }, - { - ID_AHA_3950U2D_1, - ID_ALL_MASK, - "Adaptec 3950D Ultra2 SCSI adapter", - ahc_aic7896_setup - }, - /* aic7899 based controllers */ - { - ID_AHA_3960D, - ID_ALL_MASK, - "Adaptec 3960D Ultra160 SCSI adapter", - ahc_aic7899_setup - }, - { - ID_AHA_3960D_CPQ, - ID_ALL_MASK, - "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", - ahc_aic7899_setup - }, - /* Generic chip probes for devices we don't know 'exactly' */ - { - ID_AIC7850 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7850 SCSI adapter", - ahc_aic7850_setup - }, - { - ID_AIC7855 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7855 SCSI adapter", - ahc_aic7855_setup - }, - { - ID_AIC7859 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7859 SCSI adapter", - ahc_aic7859_setup - }, - { - ID_AIC7860 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7860 SCSI adapter", - ahc_aic7860_setup - }, - { - ID_AIC7870 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7870 SCSI adapter", - ahc_aic7870_setup - }, - { - ID_AIC7880 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7880 Ultra SCSI adapter", - ahc_aic7880_setup - }, - { - ID_AIC7890 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7890/91 Ultra2 SCSI adapter", - ahc_aic7890_setup - }, - { - ID_AIC7892 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7892 Ultra160 SCSI adapter", - ahc_aic7892_setup - }, - { - ID_AIC7895 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7895 Ultra SCSI adapter", - ahc_aic7895_setup - }, - { - ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", - ahc_aic7895_setup - }, - { - ID_AIC7896 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7896/97 Ultra2 SCSI adapter", - ahc_aic7896_setup - }, - { - ID_AIC7899 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7899 Ultra160 SCSI adapter", - ahc_aic7899_setup - }, - { - ID_AIC7810 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7810 RAID memory controller", - ahc_raid_setup - }, - { - ID_AIC7815 & ID_DEV_VENDOR_MASK, - ID_DEV_VENDOR_MASK, - "Adaptec aic7815 RAID memory controller", - ahc_raid_setup - } -}; - -static const int ahc_num_pci_devs = - sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); - -#define AHC_394X_SLOT_CHANNEL_A 4 -#define AHC_394X_SLOT_CHANNEL_B 5 - -#define AHC_398X_SLOT_CHANNEL_A 4 -#define AHC_398X_SLOT_CHANNEL_B 8 -#define AHC_398X_SLOT_CHANNEL_C 12 - -#define AHC_494X_SLOT_CHANNEL_A 4 -#define AHC_494X_SLOT_CHANNEL_B 5 -#define AHC_494X_SLOT_CHANNEL_C 6 -#define AHC_494X_SLOT_CHANNEL_D 7 - -#define DEVCONFIG 0x40 -#define SCBSIZE32 0x00010000ul /* aic789X only */ -#define MPORTMODE 0x00000400ul /* aic7870 only */ -#define RAMPSM 0x00000200ul /* aic7870 only */ -#define VOLSENSE 0x00000100ul -#define SCBRAMSEL 0x00000080ul -#define MRDCEN 0x00000040ul -#define EXTSCBTIME 0x00000020ul /* aic7870 only */ -#define EXTSCBPEN 0x00000010ul /* aic7870 only */ -#define BERREN 0x00000008ul -#define DACEN 0x00000004ul -#define STPWLEVEL 0x00000002ul -#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ - -#define CSIZE_LATTIME 0x0c -#define CACHESIZE 0x0000003ful /* only 5 bits */ -#define LATTIME 0x0000ff00ul - -static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); -static int ahc_ext_scbram_present(struct ahc_softc *ahc); -static void ahc_scbram_config(struct ahc_softc *ahc, int enable, - int pcheck, int fast, int large); -static void ahc_probe_ext_scbram(struct ahc_softc *ahc); -static int verify_cksum(struct seeprom_config *sc); -static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); -static void configure_termination(struct ahc_softc *ahc, - struct seeprom_descriptor *sd, - u_int adapter_control, - u_int *sxfrctl1); - -static void ahc_new_term_detect(struct ahc_softc *ahc, - int *enableSEC_low, - int *enableSEC_high, - int *enablePRI_low, - int *enablePRI_high, - int *eeprom_present); -static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, - int *internal68_present, - int *externalcable_present, - int *eeprom_present); -static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, - int *externalcable_present, - int *eeprom_present); -static int acquire_seeprom(struct ahc_softc *ahc, - struct seeprom_descriptor *sd); -static void release_seeprom(struct seeprom_descriptor *sd); -static void write_brdctl(struct ahc_softc *ahc, uint8_t value); -static uint8_t read_brdctl(struct ahc_softc *ahc); - -static struct ahc_softc *first_398X; +#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ +#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ static int ahc_pci_probe(device_t dev); static int ahc_pci_attach(device_t dev); -/* Exported for use in the ahc_intr routine */ -void ahc_pci_intr(struct ahc_softc *ahc); - static device_method_t ahc_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ahc_pci_probe), @@ -609,30 +58,10 @@ static devclass_t ahc_devclass; DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); -static struct ahc_pci_identity * -ahc_find_pci_device(device_t dev) -{ - uint64_t full_id; - struct ahc_pci_identity *entry; - u_int i; - - full_id = ahc_compose_id(pci_get_device(dev), - pci_get_vendor(dev), - pci_get_subdevice(dev), - pci_get_subvendor(dev)); - - for (i = 0; i < ahc_num_pci_devs; i++) { - entry = &ahc_pci_ident_table[i]; - if (entry->full_id == (full_id & entry->id_mask)) - return (entry); - } - return (NULL); -} - static int ahc_pci_probe(device_t dev) { - struct ahc_pci_identity *entry; + struct ahc_pci_identity *entry; entry = ahc_find_pci_device(dev); if (entry != NULL) { @@ -645,61 +74,27 @@ ahc_pci_probe(device_t dev) static int ahc_pci_attach(device_t dev) { - struct ahc_probe_config probe_config; - bus_dma_tag_t parent_dmat; - struct ahc_pci_identity *entry; - struct resource *regs; - struct ahc_softc *ahc; - struct scb_data *shared_scb_data; - u_int command; - int regs_type; - int regs_id; - u_int our_id = 0; - u_int sxfrctl1; - u_int scsiseq; - u_int dscommand0; - int error; - int zero; - uint8_t sblkctl; + struct ahc_pci_identity *entry; + struct ahc_softc *ahc; + char *name; + int error; - shared_scb_data = NULL; - command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); entry = ahc_find_pci_device(dev); if (entry == NULL) return (ENXIO); - ahc_init_probe_config(&probe_config); - error = entry->setup(dev, &probe_config); - probe_config.chip |= AHC_PCI; - probe_config.description = entry->name; - if (error != 0) - return (error); - regs = NULL; - regs_type = 0; - regs_id = 0; -#ifdef AHC_ALLOW_MEMIO - if ((command & PCIM_CMD_MEMEN) != 0) { - regs_type = SYS_RES_MEMORY; - regs_id = AHC_PCI_MEMADDR; - regs = bus_alloc_resource(dev, regs_type, - ®s_id, 0, ~0, 1, RF_ACTIVE); - } -#endif - if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { - regs_type = SYS_RES_IOPORT; - regs_id = AHC_PCI_IOADDR; - regs = bus_alloc_resource(dev, regs_type, - ®s_id, 0, ~0, 1, RF_ACTIVE); - } - - if (regs == NULL) { - device_printf(dev, "can't allocate register resources\n"); + /* + * Allocate a softc for this card and + * set it up for attachment by our + * common detect routine. + */ + name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT); + if (name == NULL) + return (ENOMEM); + strcpy(name, device_get_nameunit(dev)); + ahc = ahc_alloc(NULL, name); + if (ahc == NULL) return (ENOMEM); - } - - /* Ensure busmastering is enabled */ - command |= PCIM_CMD_BUSMASTEREN; - pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); /* Allocate a dmatag for our SCB DMA maps */ /* XXX Should be a child of the PCI bus dma tag */ @@ -710,1301 +105,95 @@ ahc_pci_attach(device_t dev) /*filter*/NULL, /*filterarg*/NULL, /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, /*maxsegsz*/AHC_MAXTRANSFER_SIZE, - /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); + /*flags*/BUS_DMA_ALLOCNOW, + &ahc->parent_dmat); if (error != 0) { printf("ahc_pci_attach: Could not allocate DMA tag " "- error %d\n", error); - return (ENOMEM); - } - - /* On all PCI adapters, we allow SCB paging */ - probe_config.flags |= AHC_PAGESCBS; - if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, - &probe_config, shared_scb_data)) == NULL) - return (ENOMEM); - - /* Store our PCI bus information for use in our PCI error handler */ - ahc->device = dev; - - /* Remeber how the card was setup in case there is no SEEPROM */ - pause_sequencer(ahc); - if ((ahc->features & AHC_ULTRA2) != 0) - our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; - else - our_id = ahc_inb(ahc, SCSIID) & OID; - sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; - scsiseq = ahc_inb(ahc, SCSISEQ); - - if (ahc_reset(ahc) != 0) { - /* Failed */ - ahc_free(ahc); - return (ENXIO); - } - - if ((ahc->features & AHC_DT) != 0) { - u_int sfunct; - - /* Perform ALT-Mode Setup */ - sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; - ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); - ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); - /* Send CRC info in target mode every 4K */ - ahc_outb(ahc, TARGCRCCNT, 0); - ahc_outb(ahc, TARGCRCCNT + 1, 0x10); - ahc_outb(ahc, SFUNCT, sfunct); - - /* Normal mode setup */ - ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN - |TARGCRCENDEN|TARGCRCCNTEN); - } - zero = 0; - ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, - 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); - if (ahc->irq == NULL) { ahc_free(ahc); return (ENOMEM); } - - ahc->irq_res_type = SYS_RES_IRQ; - - dscommand0 = ahc_inb(ahc, DSCOMMAND0); - dscommand0 |= MPARCKEN; - if ((ahc->features & AHC_ULTRA2) != 0) { - - /* - * DPARCKEN doesn't work correctly on - * some MBs so don't use it. - */ - dscommand0 &= ~DPARCKEN; - /* - * We default to using 32byte SCBs - * and using cacheline streaming. - * If external SCB ram is detected, - * we'll switch to using 64 byte SCBs. - */ - dscommand0 |= CACHETHEN|USCBSIZE32; - } - /* - * Handle chips that must have cache line - * streaming (dis/en)abled. - */ - if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) - dscommand0 |= CACHETHEN; - - if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) - dscommand0 &= ~CACHETHEN; - - ahc_outb(ahc, DSCOMMAND0, dscommand0); - - /* See if we have a SEEPROM and perform auto-term */ - check_extport(ahc, &sxfrctl1); - - /* - * Take the LED out of diagnostic mode - */ - sblkctl = ahc_inb(ahc, SBLKCTL); - ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); - - /* - * I don't know where this is set in the SEEPROM or by the - * BIOS, so we default to 100% on Ultra or slower controllers - * and 75% on ULTRA2 controllers. - */ - if ((ahc->features & AHC_ULTRA2) != 0) { - ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); - } else { - ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); - } - - if (ahc->flags & AHC_USEDEFAULTS) { - /* - * PCI Adapter default setup - * Should only be used if the adapter does not have - * an SEEPROM. - */ - /* See if someone else set us up already */ - if (scsiseq != 0) { - printf("%s: Using left over BIOS settings\n", - ahc_name(ahc)); - ahc->flags &= ~AHC_USEDEFAULTS; - } else { - /* - * Assume only one connector and always turn - * on termination. - */ - our_id = 0x07; - sxfrctl1 = STPWEN; - } - ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); - - ahc->our_id = our_id; - } - - /* - * Take a look to see if we have external SRAM. - * We currently do not attempt to use SRAM that is - * shared among multiple controllers. - */ - ahc_probe_ext_scbram(ahc); - - printf("%s: %s ", ahc_name(ahc), - ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); - - /* - * Record our termination setting for the - * generic initialization routine. - */ - if ((sxfrctl1 & STPWEN) != 0) - ahc->flags |= AHC_TERM_ENB_A; - - if (ahc_init(ahc)) { + ahc->dev_softc = dev; + error = ahc_pci_config(ahc, entry); + if (error != 0) { ahc_free(ahc); - return (ENOMEM); - } - - /* XXX Crude hack - fix sometime */ - if (ahc->flags & AHC_SHARED_SRAM) { - /* Only set this once we've successfully probed */ - if (shared_scb_data == NULL) - first_398X = ahc; + return (error); } ahc_attach(ahc); return (0); } -/* - * Test for the presense of external sram in an - * "unshared" configuration. - */ -static int -ahc_ext_scbram_present(struct ahc_softc *ahc) -{ - int ramps; - int single_user; - uint32_t devconfig; - - devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); - single_user = (devconfig & MPORTMODE) != 0; - - if ((ahc->features & AHC_ULTRA2) != 0) - ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; - else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) - ramps = (devconfig & RAMPSM) != 0; - else - ramps = 0; - - if (ramps && single_user) - return (1); - return (0); -} - -/* - * Enable external scbram. - */ -static void -ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, - int fast, int large) -{ - uint32_t devconfig; - - if (ahc->features & AHC_MULTI_FUNC) { - /* - * Set the SCB Base addr (highest address bit) - * depending on which channel we are. - */ - ahc_outb(ahc, SCBBADDR, pci_get_function(ahc->device)); - } - - devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); - if ((ahc->features & AHC_ULTRA2) != 0) { - u_int dscommand0; - - dscommand0 = ahc_inb(ahc, DSCOMMAND0); - if (enable) - dscommand0 &= ~INTSCBRAMSEL; - else - dscommand0 |= INTSCBRAMSEL; - if (large) - dscommand0 |= USCBSIZE32; - else - dscommand0 &= ~USCBSIZE32; - ahc_outb(ahc, DSCOMMAND0, dscommand0); - } else { - if (fast) - devconfig &= ~EXTSCBTIME; - else - devconfig |= EXTSCBTIME; - if (enable) - devconfig &= ~SCBRAMSEL; - else - devconfig |= SCBRAMSEL; - if (large) - devconfig &= ~SCBSIZE32; - else - devconfig |= SCBSIZE32; - } - if (pcheck) - devconfig |= EXTSCBPEN; - else - devconfig &= ~EXTSCBPEN; - - pci_write_config(ahc->device, DEVCONFIG, devconfig, /*bytes*/4); -} - -/* - * Take a look to see if we have external SRAM. - * We currently do not attempt to use SRAM that is - * shared among multiple controllers. - */ -static void -ahc_probe_ext_scbram(struct ahc_softc *ahc) -{ - int num_scbs; - int test_num_scbs; - int enable; - int pcheck; - int fast; - int large; - - enable = FALSE; - pcheck = FALSE; - fast = FALSE; - large = FALSE; - num_scbs = 0; - - if (ahc_ext_scbram_present(ahc) == 0) - return; - - /* - * Probe for the best parameters to use. - */ - ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); - num_scbs = ahc_probe_scbs(ahc); - if (num_scbs == 0) { - /* The SRAM wasn't really present. */ - goto done; - } - enable = TRUE; - - /* - * Clear any outstanding parity error - * and ensure that parity error reporting - * is enabled. - */ - ahc_outb(ahc, SEQCTL, 0); - ahc_outb(ahc, CLRINT, CLRPARERR); - ahc_outb(ahc, CLRINT, CLRBRKADRINT); - - /* Now see if we can do parity */ - ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); - num_scbs = ahc_probe_scbs(ahc); - if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 - || (ahc_inb(ahc, ERROR) & MPARERR) == 0) - pcheck = TRUE; - - /* Clear any resulting parity error */ - ahc_outb(ahc, CLRINT, CLRPARERR); - ahc_outb(ahc, CLRINT, CLRBRKADRINT); - - /* Now see if we can do fast timing */ - ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); - test_num_scbs = ahc_probe_scbs(ahc); - if (test_num_scbs == num_scbs - && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 - || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) - fast = TRUE; - - /* - * See if we can use large SCBs and still maintain - * the same overall count of SCBs. - */ - if ((ahc->features & AHC_LARGE_SCBS) != 0) { - ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); - test_num_scbs = ahc_probe_scbs(ahc); - if (test_num_scbs >= num_scbs) { - large = TRUE; - num_scbs = test_num_scbs; - } - if (num_scbs >= 64) - /* - * We have enough space to move the "busy targets - * table" into SCB space and make it qualify all - * the way to the lun level. - */ - ahc->flags |= AHC_SCB_BTT; - } -done: - /* - * Disable parity error reporting until we - * can load instruction ram. - */ - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); - /* Clear any latched parity error */ - ahc_outb(ahc, CLRINT, CLRPARERR); - ahc_outb(ahc, CLRINT, CLRBRKADRINT); - if (bootverbose && enable) { - printf("%s: External SRAM, %s access%s\n", - ahc_name(ahc), fast ? "fast" : "slow", - pcheck ? ", parity checking enabled" : ""); - - } - ahc_scbram_config(ahc, enable, pcheck, fast, large); -} - -static int -verify_cksum(struct seeprom_config *sc) -{ - int i; - int maxaddr; - uint32_t checksum; - uint16_t *scarray; - - maxaddr = (sizeof(*sc)/2) - 1; - checksum = 0; - scarray = (uint16_t *)sc; - - for (i = 0; i < maxaddr; i++) - checksum = checksum + scarray[i]; - if (checksum == 0 - || (checksum & 0xFFFF) != sc->checksum) { - return (0); - } else { - return(1); - } -} - -/* - * Check the external port logic for a serial eeprom - * and termination/cable detection contrls. - */ -static void -check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) -{ - struct seeprom_descriptor sd; - struct seeprom_config sc; - u_int scsi_conf; - u_int adapter_control; - int have_seeprom; - int have_autoterm; - - sd.sd_tag = ahc->tag; - sd.sd_bsh = ahc->bsh; - sd.sd_control_offset = SEECTL; - sd.sd_status_offset = SEECTL; - sd.sd_dataout_offset = SEECTL; - - /* - * For some multi-channel devices, the c46 is simply too - * small to work. For the other controller types, we can - * get our information from either SEEPROM type. Set the - * type to start our probe with accordingly. - */ - if (ahc->flags & AHC_LARGE_SEEPROM) - sd.sd_chip = C56_66; - else - sd.sd_chip = C46; - - sd.sd_MS = SEEMS; - sd.sd_RDY = SEERDY; - sd.sd_CS = SEECS; - sd.sd_CK = SEECK; - sd.sd_DO = SEEDO; - sd.sd_DI = SEEDI; - - have_seeprom = acquire_seeprom(ahc, &sd); - if (have_seeprom) { - - if (bootverbose) - printf("%s: Reading SEEPROM...", ahc_name(ahc)); - - for (;;) { - bus_size_t start_addr; - - start_addr = 32 * (ahc->channel - 'A'); - - have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, - start_addr, sizeof(sc)/2); - - if (have_seeprom) - have_seeprom = verify_cksum(&sc); - - if (have_seeprom != 0 || sd.sd_chip == C56_66) { - if (bootverbose) { - if (have_seeprom == 0) - printf ("checksum error\n"); - else - printf ("done.\n"); - } - break; - } - sd.sd_chip = C56_66; - } - } - -#if 0 - /* - * This code causes a machine with an aic7880 chipset - * to reboot spontaneously. Whatever it's supposed to do, - * it's doing it wrong. -wpaul - */ - if (!have_seeprom) { - /* - * Pull scratch ram settings and treat them as - * if they are the contents of an seeprom if - * the 'ADPT' signature is found in SCB2. - */ - ahc_outb(ahc, SCBPTR, 2); - if (ahc_inb(ahc, SCB_CONTROL) == 'A' - && ahc_inb(ahc, SCB_CONTROL + 1) == 'D' - && ahc_inb(ahc, SCB_CONTROL + 2) == 'P' - && ahc_inb(ahc, SCB_CONTROL + 3) == 'T') { - uint8_t *sc_bytes; - int i; - - printf("Got Here!\n"); - sc_bytes = (uint8_t *)≻ - for (i = 0; i < 64; i++) - sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); - /* Byte 0x1c is stored in byte 4 of SCB2 */ - sc_bytes[0x1c] = ahc_inb(ahc, SCB_CONTROL + 4); - have_seeprom = verify_cksum(&sc); - if (have_seeprom) - printf("And it even worked!\n"); - } - } -#endif - - if (!have_seeprom) { - if (bootverbose) - printf("%s: No SEEPROM available.\n", ahc_name(ahc)); - ahc->flags |= AHC_USEDEFAULTS; - } else { - /* - * Put the data we've collected down into SRAM - * where ahc_init will find it. - */ - int i; - int max_targ = sc.max_targets & CFMAXTARG; - uint16_t discenable; - uint16_t ultraenb; - - discenable = 0; - ultraenb = 0; - if ((sc.adapter_control & CFULTRAEN) != 0) { - /* - * Determine if this adapter has a "newstyle" - * SEEPROM format. - */ - for (i = 0; i < max_targ; i++) { - if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ - ahc->flags |= AHC_NEWEEPROM_FMT; - break; - } - } - } - - for (i = 0; i < max_targ; i++) { - u_int scsirate; - uint16_t target_mask; - - target_mask = 0x01 << i; - if (sc.device_flags[i] & CFDISC) - discenable |= target_mask; - if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { - if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) - ultraenb |= target_mask; - } else if ((sc.adapter_control & CFULTRAEN) != 0) { - ultraenb |= target_mask; - } - if ((sc.device_flags[i] & CFXFER) == 0x04 - && (ultraenb & target_mask) != 0) { - /* Treat 10MHz as a non-ultra speed */ - sc.device_flags[i] &= ~CFXFER; - ultraenb &= ~target_mask; - } - if ((ahc->features & AHC_ULTRA2) != 0) { - u_int offset; - - if (sc.device_flags[i] & CFSYNCH) - offset = MAX_OFFSET_ULTRA2; - else - offset = 0; - ahc_outb(ahc, TARG_OFFSET + i, offset); - - /* - * The ultra enable bits contain the - * high bit of the ultra2 sync rate - * field. - */ - scsirate = (sc.device_flags[i] & CFXFER) - | ((ultraenb & target_mask) - ? 0x8 : 0x0); - if (sc.device_flags[i] & CFWIDEB) - scsirate |= WIDEXFER; - } else { - scsirate = (sc.device_flags[i] & CFXFER) << 4; - if (sc.device_flags[i] & CFSYNCH) - scsirate |= SOFS; - if (sc.device_flags[i] & CFWIDEB) - scsirate |= WIDEXFER; - } - ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); - } - ahc->our_id = sc.brtime_id & CFSCSIID; - - scsi_conf = (ahc->our_id & 0x7); - if (sc.adapter_control & CFSPARITY) - scsi_conf |= ENSPCHK; - if (sc.adapter_control & CFRESETB) - scsi_conf |= RESET_SCSI; - - if (sc.bios_control & CFEXTEND) - ahc->flags |= AHC_EXTENDED_TRANS_A; - if (ahc->features & AHC_ULTRA - && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { - /* Should we enable Ultra mode? */ - if (!(sc.adapter_control & CFULTRAEN)) - /* Treat us as a non-ultra card */ - ultraenb = 0; - } - - if (sc.signature == CFSIGNATURE) { - uint32_t devconfig; - - /* Honor the STPWLEVEL settings */ - devconfig = pci_read_config(ahc->device, DEVCONFIG, - /*bytes*/4); - devconfig &= ~STPWLEVEL; - if ((sc.bios_control & CFSTPWLEVEL) != 0) - devconfig |= STPWLEVEL; - pci_write_config(ahc->device, DEVCONFIG, - devconfig, /*bytes*/4); - } - /* Set SCSICONF info */ - ahc_outb(ahc, SCSICONF, scsi_conf); - ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); - ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); - ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); - ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); - } - - /* - * Cards that have the external logic necessary to talk to - * a SEEPROM, are almost certain to have the remaining logic - * necessary for auto-termination control. This assumption - * hasn't failed yet... - */ - have_autoterm = have_seeprom; - if (have_seeprom) - adapter_control = sc.adapter_control; - else - adapter_control = CFAUTOTERM; - - /* - * Some low-cost chips have SEEPROM and auto-term control built - * in, instead of using a GAL. They can tell us directly - * if the termination logic is enabled. - */ - if ((ahc->features & AHC_SPIOCAP) != 0) { - if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) - have_autoterm = TRUE; - else - have_autoterm = FALSE; - } - - if (have_autoterm) - configure_termination(ahc, &sd, adapter_control, sxfrctl1); - - release_seeprom(&sd); -} - -static void -configure_termination(struct ahc_softc *ahc, - struct seeprom_descriptor *sd, - u_int adapter_control, - u_int *sxfrctl1) +int +ahc_pci_map_registers(struct ahc_softc *ahc) { - uint8_t brddat; - - brddat = 0; - - /* - * Update the settings in sxfrctl1 to match the - * termination settings - */ - *sxfrctl1 = 0; - - /* - * SEECS must be on for the GALS to latch - * the data properly. Be sure to leave MS - * on or we will release the seeprom. - */ - SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); - if ((adapter_control & CFAUTOTERM) != 0 - || (ahc->features & AHC_NEW_TERMCTL) != 0) { - int internal50_present; - int internal68_present; - int externalcable_present; - int eeprom_present; - int enableSEC_low; - int enableSEC_high; - int enablePRI_low; - int enablePRI_high; - - enableSEC_low = 0; - enableSEC_high = 0; - enablePRI_low = 0; - enablePRI_high = 0; - if ((ahc->features & AHC_NEW_TERMCTL) != 0) { - ahc_new_term_detect(ahc, &enableSEC_low, - &enableSEC_high, - &enablePRI_low, - &enablePRI_high, - &eeprom_present); - if ((adapter_control & CFSEAUTOTERM) == 0) { - if (bootverbose) - printf("%s: Manual SE Termination\n", - ahc_name(ahc)); - enableSEC_low = (adapter_control & CFSELOWTERM); - enableSEC_high = - (adapter_control & CFSEHIGHTERM); - } - if ((adapter_control & CFAUTOTERM) == 0) { - if (bootverbose) - printf("%s: Manual LVD Termination\n", - ahc_name(ahc)); - enablePRI_low = (adapter_control & CFSTERM); - enablePRI_high = (adapter_control & CFWSTERM); - } - /* Make the table calculations below happy */ - internal50_present = 0; - internal68_present = 1; - externalcable_present = 1; - } else if ((ahc->features & AHC_SPIOCAP) != 0) { - aic785X_cable_detect(ahc, &internal50_present, - &externalcable_present, - &eeprom_present); - } else { - aic787X_cable_detect(ahc, &internal50_present, - &internal68_present, - &externalcable_present, - &eeprom_present); - } + struct resource *regs; + u_int command; + int regs_type; + int regs_id; - if ((ahc->features & AHC_WIDE) == 0) - internal68_present = 0; - - if (bootverbose) { - if ((ahc->features & AHC_ULTRA2) == 0) { - printf("%s: internal 50 cable %s present, " - "internal 68 cable %s present\n", - ahc_name(ahc), - internal50_present ? "is":"not", - internal68_present ? "is":"not"); - - printf("%s: external cable %s present\n", - ahc_name(ahc), - externalcable_present ? "is":"not"); - } - printf("%s: BIOS eeprom %s present\n", - ahc_name(ahc), eeprom_present ? "is" : "not"); - } + command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); + regs = NULL; + regs_type = 0; + regs_id = 0; + if ((command & PCIM_CMD_MEMEN) != 0) { + regs_type = SYS_RES_MEMORY; + regs_id = AHC_PCI_MEMADDR; + regs = bus_alloc_resource(ahc->dev_softc, regs_type, + ®s_id, 0, ~0, 1, RF_ACTIVE); + if (regs != NULL) { + ahc->tag = rman_get_bustag(regs); + ahc->bsh = rman_get_bushandle(regs); - if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { /* - * The 50 pin connector is a separate bus, - * so force it to always be terminated. - * In the future, perform current sensing - * to determine if we are in the middle of - * a properly terminated bus. + * Do a quick test to see if memory mapped + * I/O is functioning correctly. */ - internal50_present = 0; - } - - /* - * Now set the termination based on what - * we found. - * Flash Enable = BRDDAT7 - * Secondary High Term Enable = BRDDAT6 - * Secondary Low Term Enable = BRDDAT5 (7890) - * Primary High Term Enable = BRDDAT4 (7890) - */ - if ((ahc->features & AHC_ULTRA2) == 0 - && (internal50_present != 0) - && (internal68_present != 0) - && (externalcable_present != 0)) { - printf("%s: Illegal cable configuration!!. " - "Only two connectors on the " - "adapter may be used at a " - "time!\n", ahc_name(ahc)); - } - - if ((ahc->features & AHC_WIDE) != 0 - && ((externalcable_present == 0) - || (internal68_present == 0) - || (enableSEC_high != 0))) { - brddat |= BRDDAT6; - if (bootverbose) { - if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) - printf("%s: 68 pin termination " - "Enabled\n", ahc_name(ahc)); - else - printf("%s: %sHigh byte termination " - "Enabled\n", ahc_name(ahc), - enableSEC_high ? "Secondary " - : ""); - } - } - - if (((internal50_present ? 1 : 0) - + (internal68_present ? 1 : 0) - + (externalcable_present ? 1 : 0)) <= 1 - || (enableSEC_low != 0)) { - if ((ahc->features & AHC_ULTRA2) != 0) - brddat |= BRDDAT5; - else - *sxfrctl1 |= STPWEN; - if (bootverbose) { - if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) - printf("%s: 50 pin termination " - "Enabled\n", ahc_name(ahc)); - else - printf("%s: %sLow byte termination " - "Enabled\n", ahc_name(ahc), - enableSEC_low ? "Secondary " - : ""); + if (ahc_inb(ahc, HCNTRL) == 0xFF) { + device_printf(ahc->dev_softc, + "PCI Device %d:%d:%d failed memory " + "mapped test. Using PIO.\n", + ahc_get_pci_bus(ahc->dev_softc), + ahc_get_pci_slot(ahc->dev_softc), + ahc_get_pci_function(ahc->dev_softc)); + bus_release_resource(ahc->dev_softc, regs_type, + regs_id, regs); + regs = NULL; } } - - if (enablePRI_low != 0) { - *sxfrctl1 |= STPWEN; - if (bootverbose) - printf("%s: Primary Low Byte termination " - "Enabled\n", ahc_name(ahc)); - } - - /* - * Setup STPWEN before setting up the rest of - * the termination per the tech note on the U160 cards. - */ - ahc_outb(ahc, SXFRCTL1, *sxfrctl1); - - if (enablePRI_high != 0) { - brddat |= BRDDAT4; - if (bootverbose) - printf("%s: Primary High Byte " - "termination Enabled\n", - ahc_name(ahc)); - } - - write_brdctl(ahc, brddat); - - } else { - if ((adapter_control & CFSTERM) != 0) { - *sxfrctl1 |= STPWEN; - - if (bootverbose) - printf("%s: %sLow byte termination Enabled\n", - ahc_name(ahc), - (ahc->features & AHC_ULTRA2) ? "Primary " - : ""); - } - - if ((adapter_control & CFWSTERM) != 0) { - brddat |= BRDDAT6; - if (bootverbose) - printf("%s: %sHigh byte termination Enabled\n", - ahc_name(ahc), - (ahc->features & AHC_ULTRA2) - ? "Secondary " : ""); - } - - /* - * Setup STPWEN before setting up the rest of - * the termination per the tech note on the U160 cards. - */ - ahc_outb(ahc, SXFRCTL1, *sxfrctl1); - - write_brdctl(ahc, brddat); - } - SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ -} - -static void -ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, - int *enableSEC_high, int *enablePRI_low, - int *enablePRI_high, int *eeprom_present) -{ - uint8_t brdctl; - - /* - * BRDDAT7 = Eeprom - * BRDDAT6 = Enable Secondary High Byte termination - * BRDDAT5 = Enable Secondary Low Byte termination - * BRDDAT4 = Enable Primary high byte termination - * BRDDAT3 = Enable Primary low byte termination - */ - brdctl = read_brdctl(ahc); - *eeprom_present = brdctl & BRDDAT7; - *enableSEC_high = (brdctl & BRDDAT6); - *enableSEC_low = (brdctl & BRDDAT5); - *enablePRI_high = (brdctl & BRDDAT4); - *enablePRI_low = (brdctl & BRDDAT3); -} - -static void -aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, - int *internal68_present, int *externalcable_present, - int *eeprom_present) -{ - uint8_t brdctl; - - /* - * First read the status of our cables. - * Set the rom bank to 0 since the - * bank setting serves as a multiplexor - * for the cable detection logic. - * BRDDAT5 controls the bank switch. - */ - write_brdctl(ahc, 0); - - /* - * Now read the state of the internal - * connectors. BRDDAT6 is INT50 and - * BRDDAT7 is INT68. - */ - brdctl = read_brdctl(ahc); - *internal50_present = !(brdctl & BRDDAT6); - *internal68_present = !(brdctl & BRDDAT7); - - /* - * Set the rom bank to 1 and determine - * the other signals. - */ - write_brdctl(ahc, BRDDAT5); - - /* - * Now read the state of the external - * connectors. BRDDAT6 is EXT68 and - * BRDDAT7 is EPROMPS. - */ - brdctl = read_brdctl(ahc); - *externalcable_present = !(brdctl & BRDDAT6); - *eeprom_present = brdctl & BRDDAT7; -} - -static void -aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, - int *externalcable_present, int *eeprom_present) -{ - uint8_t brdctl; - - ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); - ahc_outb(ahc, BRDCTL, 0); - brdctl = ahc_inb(ahc, BRDCTL); - *internal50_present = !(brdctl & BRDDAT5); - *externalcable_present = !(brdctl & BRDDAT6); - - *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; -} - -static int -acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) -{ - int wait; - - if ((ahc->features & AHC_SPIOCAP) != 0 - && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) - return (0); - - /* - * Request access of the memory port. When access is - * granted, SEERDY will go high. We use a 1 second - * timeout which should be near 1 second more than - * is needed. Reason: after the chip reset, there - * should be no contention. - */ - SEEPROM_OUTB(sd, sd->sd_MS); - wait = 1000; /* 1 second timeout in msec */ - while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { - DELAY(1000); /* delay 1 msec */ } - if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { - SEEPROM_OUTB(sd, 0); - return (0); - } - return(1); -} - -static void -release_seeprom(struct seeprom_descriptor *sd) -{ - /* Release access to the memory port and the serial EEPROM. */ - SEEPROM_OUTB(sd, 0); -} - -static void -write_brdctl(struct ahc_softc *ahc, uint8_t value) -{ - uint8_t brdctl; - - if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { - brdctl = BRDSTB; - if (ahc->channel == 'B') - brdctl |= BRDCS; - } else if ((ahc->features & AHC_ULTRA2) != 0) { - brdctl = 0; - } else { - brdctl = BRDSTB|BRDCS; - } - ahc_outb(ahc, BRDCTL, brdctl); - DELAY(20); - brdctl |= value; - ahc_outb(ahc, BRDCTL, brdctl); - DELAY(20); - if ((ahc->features & AHC_ULTRA2) != 0) - brdctl |= BRDSTB_ULTRA2; - else - brdctl &= ~BRDSTB; - ahc_outb(ahc, BRDCTL, brdctl); - DELAY(20); - if ((ahc->features & AHC_ULTRA2) != 0) - brdctl = 0; - else - brdctl &= ~BRDCS; - ahc_outb(ahc, BRDCTL, brdctl); -} - -static uint8_t -read_brdctl(ahc) - struct ahc_softc *ahc; -{ - uint8_t brdctl; - uint8_t value; - - if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { - brdctl = BRDRW; - if (ahc->channel == 'B') - brdctl |= BRDCS; - } else if ((ahc->features & AHC_ULTRA2) != 0) { - brdctl = BRDRW_ULTRA2; - } else { - brdctl = BRDRW|BRDCS; - } - ahc_outb(ahc, BRDCTL, brdctl); - DELAY(20); - value = ahc_inb(ahc, BRDCTL); - ahc_outb(ahc, BRDCTL, 0); - return (value); -} - -#define DPE 0x80 -#define SSE 0x40 -#define RMA 0x20 -#define RTA 0x10 -#define STA 0x08 -#define DPR 0x01 - -void -ahc_pci_intr(struct ahc_softc *ahc) -{ - uint8_t status1; - - status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); - - if (status1 & DPE) { - printf("%s: Data Parity Error Detected during address " - "or write data phase\n", ahc_name(ahc)); - } - if (status1 & SSE) { - printf("%s: Signal System Error Detected\n", ahc_name(ahc)); - } - if (status1 & RMA) { - printf("%s: Received a Master Abort\n", ahc_name(ahc)); - } - if (status1 & RTA) { - printf("%s: Received a Target Abort\n", ahc_name(ahc)); - } - if (status1 & STA) { - printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); - } - if (status1 & DPR) { - printf("%s: Data Parity Error has been reported via PERR#\n", - ahc_name(ahc)); - } - if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { - printf("%s: Latched PCIERR interrupt with " - "no status bits set\n", ahc_name(ahc)); - } - pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); - - if (status1 & (DPR|RMA|RTA)) { - ahc_outb(ahc, CLRINT, CLRPARERR); + if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { + regs_type = SYS_RES_IOPORT; + regs_id = AHC_PCI_IOADDR; + regs = bus_alloc_resource(ahc->dev_softc, regs_type, + ®s_id, 0, ~0, 1, RF_ACTIVE); + ahc->tag = rman_get_bustag(regs); + ahc->bsh = rman_get_bushandle(regs); } -} - -static int -ahc_aic7850_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7850; - probe_config->features = AHC_AIC7850_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - return (0); -} - -static int -ahc_aic7855_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7855; - probe_config->features = AHC_AIC7855_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - return (0); -} - -static int -ahc_aic7859_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7859; - probe_config->features = AHC_AIC7859_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - return (0); -} - -static int -ahc_aic7860_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7860; - probe_config->features = AHC_AIC7860_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - return (0); -} - -static int -ahc_aic7870_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7870; - probe_config->features = AHC_AIC7870_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - return (0); -} - -static int -ahc_aha394X_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - int error; - - error = ahc_aic7870_setup(dev, probe_config); - if (error == 0) - error = ahc_aha394XX_setup(dev, probe_config); - return (error); -} - -static int -ahc_aha398X_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - int error; - - error = ahc_aic7870_setup(dev, probe_config); - if (error == 0) - error = ahc_aha398XX_setup(dev, probe_config); - return (error); -} - -static int -ahc_aha494X_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - int error; - - error = ahc_aic7870_setup(dev, probe_config); - if (error == 0) - error = ahc_aha494XX_setup(dev, probe_config); - return (error); -} - -static int -ahc_aic7880_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7880; - probe_config->features = AHC_AIC7880_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - return (0); -} - -static int -ahc_2940Pro_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - int error; - - probe_config->flags |= AHC_INT50_SPEEDFLEX; - error = ahc_aic7880_setup(dev, probe_config); - return (0); -} - -static int -ahc_aha394XU_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - int error; - - error = ahc_aic7880_setup(dev, probe_config); - if (error == 0) - error = ahc_aha394XX_setup(dev, probe_config); - return (error); -} - -static int -ahc_aha398XU_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - int error; - - error = ahc_aic7880_setup(dev, probe_config); - if (error == 0) - error = ahc_aha398XX_setup(dev, probe_config); - return (error); -} - -static int -ahc_aic7890_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7890; - probe_config->features = AHC_AIC7890_FE; - probe_config->flags |= AHC_NEWEEPROM_FMT; - if (pci_get_revid(dev) == 0) - probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; - return (0); -} - -static int -ahc_aic7892_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = 'A'; - probe_config->chip = AHC_AIC7892; - probe_config->features = AHC_AIC7892_FE; - probe_config->flags |= AHC_NEWEEPROM_FMT; - return (0); -} - -static int -ahc_aic7895_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - uint32_t devconfig; - - probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; - probe_config->chip = AHC_AIC7895; - /* The 'C' revision of the aic7895 has a few additional features */ - if (pci_get_revid(dev) >= 4) - probe_config->features = AHC_AIC7895C_FE; - else - probe_config->features = AHC_AIC7895_FE; - probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; - probe_config->flags |= AHC_NEWEEPROM_FMT; - devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); - devconfig |= SCBSIZE32; - pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); - return (0); -} - -static int -ahc_aic7896_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; - probe_config->chip = AHC_AIC7896; - probe_config->features = AHC_AIC7896_FE; - probe_config->flags |= AHC_NEWEEPROM_FMT; - probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; - return (0); -} - -static int -ahc_aic7899_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; - probe_config->chip = AHC_AIC7899; - probe_config->features = AHC_AIC7899_FE; - probe_config->flags |= AHC_NEWEEPROM_FMT; - return (0); -} - -static int -ahc_raid_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - printf("RAID functionality unsupported\n"); - return (ENXIO); -} - -static int -ahc_aha394XX_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - switch (pci_get_slot(dev)) { - case AHC_394X_SLOT_CHANNEL_A: - probe_config->channel = 'A'; - break; - case AHC_394X_SLOT_CHANNEL_B: - probe_config->channel = 'B'; - break; - default: - printf("adapter at unexpected slot %d\n" - "unable to map to a channel\n", - pci_get_slot(dev)); - probe_config->channel = 'A'; + ahc->platform_data->regs_res_type = regs_type; + ahc->platform_data->regs_res_id = regs_id; + ahc->platform_data->regs = regs; + + if (regs == NULL) { + device_printf(ahc->dev_softc, + "can't allocate register resources\n"); + return (ENOMEM); } return (0); } -static int -ahc_aha398XX_setup(device_t dev, struct ahc_probe_config *probe_config) +int +ahc_pci_map_int(struct ahc_softc *ahc) { - switch (pci_get_slot(dev)) { - case AHC_398X_SLOT_CHANNEL_A: - probe_config->channel = 'A'; - break; - case AHC_398X_SLOT_CHANNEL_B: - probe_config->channel = 'B'; - break; - case AHC_398X_SLOT_CHANNEL_C: - probe_config->channel = 'C'; - break; - default: - printf("adapter at unexpected slot %d\n" - "unable to map to a channel\n", - pci_get_slot(dev)); - probe_config->channel = 'A'; - break; - } - probe_config->flags |= AHC_LARGE_SEEPROM; - return (0); -} + int zero; -static int -ahc_aha494XX_setup(device_t dev, struct ahc_probe_config *probe_config) -{ - switch (pci_get_slot(dev)) { - case AHC_494X_SLOT_CHANNEL_A: - probe_config->channel = 'A'; - break; - case AHC_494X_SLOT_CHANNEL_B: - probe_config->channel = 'B'; - break; - case AHC_494X_SLOT_CHANNEL_C: - probe_config->channel = 'C'; - break; - case AHC_494X_SLOT_CHANNEL_D: - probe_config->channel = 'D'; - break; - default: - printf("adapter at unexpected slot %d\n" - "unable to map to a channel\n", - pci_get_slot(dev)); - probe_config->channel = 'A'; - } - probe_config->flags |= AHC_LARGE_SEEPROM; + zero = 0; + ahc->platform_data->irq = + bus_alloc_resource(ahc->dev_softc, SYS_RES_IRQ, &zero, + 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); + if (ahc->platform_data->irq == NULL) + return (ENOMEM); + ahc->platform_data->irq_res_type = SYS_RES_IRQ; return (0); } diff --git a/sys/dev/aic7xxx/aic7770.c b/sys/dev/aic7xxx/aic7770.c new file mode 100644 index 000000000000..bcfa0f68a1ad --- /dev/null +++ b/sys/dev/aic7xxx/aic7770.c @@ -0,0 +1,319 @@ +/* + * Product specific probe and attach routines for: + * 27/284X and aic7770 motherboard SCSI controllers + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 2000 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#ifdef __linux__ +#include "aic7xxx_linux.h" +#include "aic7xxx_inline.h" +#include "aic7xxx_93cx6.h" +#endif + +#ifdef __FreeBSD__ +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> +#include <dev/aic7xxx/aic7xxx_93cx6.h> +#endif + +#define ID_AIC7770 0x04907770 +#define ID_AHA_274x 0x04907771 +#define ID_AHA_284xB 0x04907756 /* BIOS enabled */ +#define ID_AHA_284x 0x04907757 /* BIOS disabled*/ + +static void aha2840_load_seeprom(struct ahc_softc *ahc); +static ahc_device_setup_t ahc_aic7770_VL_setup; +static ahc_device_setup_t ahc_aic7770_EISA_setup;; +static ahc_device_setup_t ahc_aic7770_setup; + + +struct aic7770_identity aic7770_ident_table [] = +{ + { + ID_AHA_274x, + 0xFFFFFFFF, + "Adaptec 274X SCSI adapter", + ahc_aic7770_EISA_setup + }, + { + ID_AHA_284xB, + 0xFFFFFFFE, + "Adaptec 284X SCSI adapter", + ahc_aic7770_VL_setup + }, + /* Generic chip probes for devices we don't know 'exactly' */ + { + ID_AIC7770, + 0xFFFFFFFF, + "Adaptec aic7770 SCSI adapter", + ahc_aic7770_EISA_setup + } +}; +const int ahc_num_aic7770_devs = NUM_ELEMENTS(aic7770_ident_table); + +struct aic7770_identity * +aic7770_find_device(uint32_t id) +{ + struct aic7770_identity *entry; + int i; + + for (i = 0; i < ahc_num_aic7770_devs; i++) { + entry = &aic7770_ident_table[i]; + if (entry->full_id == (id & entry->id_mask)) + return (entry); + } + return (NULL); +} + +int +aic7770_config(struct ahc_softc *ahc, struct aic7770_identity *entry) +{ + struct ahc_probe_config probe_config; + int error; + u_int hostconf; + + ahc_init_probe_config(&probe_config); + error = entry->setup(ahc->dev_softc, &probe_config); + if (error != 0) + return (error); + + error = aic7770_map_registers(ahc); + if (error != 0) + return (error); + + probe_config.description = entry->name; + error = ahc_softc_init(ahc, &probe_config); + + error = aic7770_map_int(ahc); + if (error != 0) + return (error); + + error = ahc_reset(ahc); + if (error != 0) + return (error); + + switch (probe_config.chip & (AHC_EISA|AHC_VL)) { + case AHC_EISA: + { + u_int biosctrl; + u_int scsiconf; + u_int scsiconf1; + + biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL); + scsiconf = ahc_inb(ahc, SCSICONF); + scsiconf1 = ahc_inb(ahc, SCSICONF + 1); + + /* Get the primary channel information */ + if ((biosctrl & CHANNEL_B_PRIMARY) != 0) + ahc->flags |= AHC_CHANNEL_B_PRIMARY; + + if ((biosctrl & BIOSMODE) == BIOSDISABLED) { + ahc->flags |= AHC_USEDEFAULTS; + } else { + if ((ahc->features & AHC_WIDE) != 0) { + ahc->our_id = scsiconf1 & HWSCSIID; + if (scsiconf & TERM_ENB) + ahc->flags |= AHC_TERM_ENB_A; + } else { + ahc->our_id = scsiconf & HSCSIID; + ahc->our_id_b = scsiconf1 & HSCSIID; + if (scsiconf & TERM_ENB) + ahc->flags |= AHC_TERM_ENB_A; + if (scsiconf1 & TERM_ENB) + ahc->flags |= AHC_TERM_ENB_B; + } + } + /* + * We have no way to tell, so assume extended + * translation is enabled. + */ + ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B; + break; + } + case AHC_VL: + { + aha2840_load_seeprom(ahc); + break; + } + default: + break; + } + + /* + * Ensure autoflush is enabled + */ + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS); + + /* Setup the FIFO threshold and the bus off time */ + hostconf = ahc_inb(ahc, HOSTCONF); + ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH); + ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF); + + /* + * Generic aic7xxx initialization. + */ + error = ahc_init(ahc); + if (error != 0) + return (error); + + /* + * Enable the board's BUS drivers + */ + ahc_outb(ahc, BCTL, ENABLE); + + return (0); +} + +/* + * Read the 284x SEEPROM. + */ +static void +aha2840_load_seeprom(struct ahc_softc *ahc) +{ + struct seeprom_descriptor sd; + struct seeprom_config sc; + uint16_t checksum = 0; + uint8_t scsi_conf; + int have_seeprom; + + sd.sd_ahc = ahc; + sd.sd_control_offset = SEECTL_2840; + sd.sd_status_offset = STATUS_2840; + sd.sd_dataout_offset = STATUS_2840; + sd.sd_chip = C46; + sd.sd_MS = 0; + sd.sd_RDY = EEPROM_TF; + sd.sd_CS = CS_2840; + sd.sd_CK = CK_2840; + sd.sd_DO = DO_2840; + sd.sd_DI = DI_2840; + + if (bootverbose) + printf("%s: Reading SEEPROM...", ahc_name(ahc)); + have_seeprom = read_seeprom(&sd, + (uint16_t *)&sc, + /*start_addr*/0, + sizeof(sc)/2); + + if (have_seeprom) { + /* Check checksum */ + int i; + int maxaddr = (sizeof(sc)/2) - 1; + uint16_t *scarray = (uint16_t *)≻ + + for (i = 0; i < maxaddr; i++) + checksum = checksum + scarray[i]; + if (checksum != sc.checksum) { + if(bootverbose) + printf ("checksum error\n"); + have_seeprom = 0; + } else if (bootverbose) { + printf("done.\n"); + } + } + + if (!have_seeprom) { + if (bootverbose) + printf("%s: No SEEPROM available\n", ahc_name(ahc)); + ahc->flags |= AHC_USEDEFAULTS; + } else { + /* + * Put the data we've collected down into SRAM + * where ahc_init will find it. + */ + int i; + int max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8; + uint16_t discenable; + + discenable = 0; + for (i = 0; i < max_targ; i++){ + uint8_t target_settings; + target_settings = (sc.device_flags[i] & CFXFER) << 4; + if (sc.device_flags[i] & CFSYNCH) + target_settings |= SOFS; + if (sc.device_flags[i] & CFWIDEB) + target_settings |= WIDEXFER; + if (sc.device_flags[i] & CFDISC) + discenable |= (0x01 << i); + ahc_outb(ahc, TARG_SCSIRATE + i, target_settings); + } + ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); + ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); + + ahc->our_id = sc.brtime_id & CFSCSIID; + + scsi_conf = (ahc->our_id & 0x7); + if (sc.adapter_control & CFSPARITY) + scsi_conf |= ENSPCHK; + if (sc.adapter_control & CFRESETB) + scsi_conf |= RESET_SCSI; + + if (sc.bios_control & CF284XEXTEND) + ahc->flags |= AHC_EXTENDED_TRANS_A; + /* Set SCSICONF info */ + ahc_outb(ahc, SCSICONF, scsi_conf); + + if (sc.adapter_control & CF284XSTERM) + ahc->flags |= AHC_TERM_ENB_A; + } +} + +static int +ahc_aic7770_VL_setup(ahc_dev_softc_t dev, struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7770_setup(dev, probe_config); + probe_config->chip |= AHC_VL; + return (error); +} + +static int +ahc_aic7770_EISA_setup(ahc_dev_softc_t dev, + struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7770_setup(dev, probe_config); + probe_config->chip |= AHC_EISA; + return (error); +} + +static int +ahc_aic7770_setup(ahc_dev_softc_t dev, struct ahc_probe_config *probe_config) +{ + probe_config->channel = 'A'; + probe_config->channel_b = 'B'; + probe_config->chip = AHC_AIC7770; + probe_config->features = AHC_AIC7770_FE; + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; + probe_config->flags |= AHC_PAGESCBS; + return (0); +} diff --git a/sys/dev/aic7xxx/aic7xxx.c b/sys/dev/aic7xxx/aic7xxx.c index e861c3db5971..a3155f6de2d4 100644 --- a/sys/dev/aic7xxx/aic7xxx.c +++ b/sys/dev/aic7xxx/aic7xxx.c @@ -1,9 +1,5 @@ /* - * Generic driver for the aic7xxx based adaptec SCSI controllers - * Product specific probe and attach routines can be found in: - * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers - * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, - * aic7880, aic7870, aic7860, and aic7850 controllers + * Core routines and tables shareable across OS platforms. * * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. * All rights reserved. @@ -32,153 +28,27 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD$ - */ -/* - * A few notes on features of the driver. - * - * SCB paging takes advantage of the fact that devices stay disconnected - * from the bus a relatively long time and that while they're disconnected, - * having the SCBs for these transactions down on the host adapter is of - * little use. Instead of leaving this idle SCB down on the card we copy - * it back up into kernel memory and reuse the SCB slot on the card to - * schedule another transaction. This can be a real payoff when doing random - * I/O to tagged queueing devices since there are more transactions active at - * once for the device to sort for optimal seek reduction. The algorithm goes - * like this... - * - * The sequencer maintains two lists of its hardware SCBs. The first is the - * singly linked free list which tracks all SCBs that are not currently in - * use. The second is the doubly linked disconnected list which holds the - * SCBs of transactions that are in the disconnected state sorted most - * recently disconnected first. When the kernel queues a transaction to - * the card, a hardware SCB to "house" this transaction is retrieved from - * either of these two lists. If the SCB came from the disconnected list, - * a check is made to see if any data transfer or SCB linking (more on linking - * in a bit) information has been changed since it was copied from the host - * and if so, DMAs the SCB back up before it can be used. Once a hardware - * SCB has been obtained, the SCB is DMAed from the host. Before any work - * can begin on this SCB, the sequencer must ensure that either the SCB is - * for a tagged transaction or the target is not already working on another - * non-tagged transaction. If a conflict arises in the non-tagged case, the - * sequencer finds the SCB for the active transactions and sets the SCB_LINKED - * field in that SCB to this next SCB to execute. To facilitate finding - * active non-tagged SCBs, the last four bytes of up to the first four hardware - * SCBs serve as a storage area for the currently active SCB ID for each - * target. - * - * When a device reconnects, a search is made of the hardware SCBs to find - * the SCB for this transaction. If the search fails, a hardware SCB is - * pulled from either the free or disconnected SCB list and the proper - * SCB is DMAed from the host. If the MK_MESSAGE control bit is set - * in the control byte of the SCB while it was disconnected, the sequencer - * will assert ATN and attempt to issue a message to the host. - * - * When a command completes, a check for non-zero status and residuals is - * made. If either of these conditions exists, the SCB is DMAed back up to - * the host so that it can interpret this information. Additionally, in the - * case of bad status, the sequencer generates a special interrupt and pauses - * itself. This allows the host to setup a request sense command if it - * chooses for this target synchronously with the error so that sense - * information isn't lost. + * $Id$ * + * $FreeBSD$ */ -#include <opt_aic7xxx.h> - -#include <pci.h> -#include <stddef.h> /* For offsetof */ - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/malloc.h> -#include <sys/eventhandler.h> -#include <sys/proc.h> - -#include <cam/cam.h> -#include <cam/cam_ccb.h> -#include <cam/cam_sim.h> -#include <cam/cam_xpt_sim.h> -#include <cam/cam_debug.h> - -#include <cam/scsi/scsi_all.h> -#include <cam/scsi/scsi_message.h> - -#if NPCI > 0 -#include <machine/bus_memio.h> +#ifdef __linux__ +#include "aic7xxx_linux.h" +#include "aic7xxx_inline.h" +#include "aicasm/aicasm_insformat.h" #endif -#include <machine/bus_pio.h> -#include <machine/bus.h> -#include <machine/clock.h> -#include <machine/endian.h> -#include <sys/rman.h> - -#include <vm/vm.h> -#include <vm/vm_param.h> -#include <vm/pmap.h> - -#include <dev/aic7xxx/aic7xxx.h> -#include <dev/aic7xxx/aicasm_insformat.h> -#include <aic7xxx_reg.h> -#include <aic7xxx_seq.h> - -#include <sys/kernel.h> - -#ifndef AHC_TMODE_ENABLE -#define AHC_TMODE_ENABLE 0 +#ifdef __FreeBSD__ +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> +#include <dev/aic7xxx/aicasm/aicasm_insformat.h> #endif -#define MAX(a,b) (((a) > (b)) ? (a) : (b)) -#define MIN(a,b) (((a) < (b)) ? (a) : (b)) -#define ALL_CHANNELS '\0' -#define ALL_TARGETS_MASK 0xFFFF -#define INITIATOR_WILDCARD (~0) - -#define SIM_IS_SCSIBUS_B(ahc, sim) \ - ((sim) == ahc->sim_b) -#define SIM_CHANNEL(ahc, sim) \ - (((sim) == ahc->sim_b) ? 'B' : 'A') -#define SIM_SCSI_ID(ahc, sim) \ - (((sim) == ahc->sim_b) ? ahc->our_id_b : ahc->our_id) -#define SIM_PATH(ahc, sim) \ - (((sim) == ahc->sim_b) ? ahc->path_b : ahc->path) -#define SCSIID_TARGET(ahc, scsiid) \ - (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ - >> TID_SHIFT) -#define SCSIID_OUR_ID(scsiid) \ - ((scsiid) & OID) -#define SCSIID_CHANNEL(ahc, scsiid) \ - ((((ahc)->features & AHC_TWIN) != 0) \ - ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ - : 'A') -#define SCB_IS_SCSIBUS_B(ahc, scb) \ - (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') -#define SCB_GET_OUR_ID(scb) \ - SCSIID_OUR_ID((scb)->hscb->scsiid) -#define SCB_GET_TARGET(ahc, scb) \ - SCSIID_TARGET((ahc), (scb)->hscb->scsiid) -#define SCB_GET_CHANNEL(ahc, scb) \ - SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) -#define SCB_GET_LUN(scb) \ - ((scb)->hscb->lun) -#define SCB_GET_TARGET_OFFSET(ahc, scb) \ - (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) -#define SCB_GET_TARGET_MASK(ahc, scb) \ - (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) -#define TCL_TARGET_OFFSET(tcl) \ - ((((tcl) >> 4) & TID) >> 4) -#define TCL_LUN(tcl) \ - (tcl & (AHC_NUM_LUNS - 1)) -#define BUILD_TCL(scsiid, lun) \ - ((lun) | (((scsiid) & TID) << 4)) -#define BUILD_SCSIID(ahc, sim, target_id, our_id) \ - ((((target_id) << TID_SHIFT) & TID) | (our_id) \ - | (SIM_IS_SCSIBUS_B(ahc, sim) ? TWIN_CHNLB : 0)) - -#define ccb_scb_ptr spriv_ptr0 -#define ccb_ahc_ptr spriv_ptr1 +/****************************** Softc Data ************************************/ +struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); +/***************************** Lookup Tables **********************************/ char *ahc_chip_names[] = { "NONE", @@ -190,263 +60,173 @@ char *ahc_chip_names[] = "aic7870", "aic7880", "aic7895", + "aic7895C", "aic7890/91", "aic7896/97", "aic7892", "aic7899" }; +const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); -typedef enum { - ROLE_UNKNOWN, - ROLE_INITIATOR, - ROLE_TARGET -} role_t; - -struct ahc_devinfo { - int our_scsiid; - int target_offset; - uint16_t target_mask; - uint8_t target; - uint8_t lun; - char channel; - role_t role; /* - * Only guaranteed to be correct if not - * in the busfree state. - */ +struct hard_error_entry hard_error[] = { + { ILLHADDR, "Illegal Host Access" }, + { ILLSADDR, "Illegal Sequencer Address referrenced" }, + { ILLOPCODE, "Illegal Opcode in sequencer program" }, + { SQPARERR, "Sequencer Parity Error" }, + { DPARERR, "Data-path Parity Error" }, + { MPARERR, "Scratch or SCB Memory Parity Error" }, + { PCIERRSTAT, "PCI Error detected" }, + { CIOPARERR, "CIOBUS Parity Error" }, }; +const u_int num_errors = NUM_ELEMENTS(hard_error); -typedef enum { - SEARCH_COMPLETE, - SEARCH_COUNT, - SEARCH_REMOVE -} ahc_search_action; - -#ifdef AHC_DEBUG -static int ahc_debug = AHC_DEBUG; -#endif - -#if NPCI > 0 -void ahc_pci_intr(struct ahc_softc *ahc); -#endif +struct phase_table_entry phase_table[] = +{ + { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, + { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, + { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, + { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, + { P_COMMAND, MSG_NOOP, "in Command phase" }, + { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, + { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, + { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, + { P_BUSFREE, MSG_NOOP, "while idle" }, + { 0, MSG_NOOP, "in unknown phase" } +}; -static int ahcinitscbdata(struct ahc_softc *ahc); -static void ahcfiniscbdata(struct ahc_softc *ahc); +/* + * In most cases we only wish to itterate over real phases, so + * exclude the last element from the count. + */ +const u_int num_phases = NUM_ELEMENTS(phase_table) - 1; -static bus_dmamap_callback_t ahcdmamapcb; +/* + * Valid SCSIRATE values. (p. 3-17) + * Provides a mapping of tranfer periods in ns to the proper value to + * stick in the scsixfer reg. + */ +struct ahc_syncrate ahc_syncrates[] = +{ + /* ultra2 fast/ultra period rate */ + { 0x42, 0x000, 9, "80.0" }, + { 0x03, 0x000, 10, "40.0" }, + { 0x04, 0x000, 11, "33.0" }, + { 0x05, 0x100, 12, "20.0" }, + { 0x06, 0x110, 15, "16.0" }, + { 0x07, 0x120, 18, "13.4" }, + { 0x08, 0x000, 25, "10.0" }, + { 0x19, 0x010, 31, "8.0" }, + { 0x1a, 0x020, 37, "6.67" }, + { 0x1b, 0x030, 43, "5.7" }, + { 0x1c, 0x040, 50, "5.0" }, + { 0x00, 0x050, 56, "4.4" }, + { 0x00, 0x060, 62, "4.0" }, + { 0x00, 0x070, 68, "3.6" }, + { 0x00, 0x000, 0, NULL } +}; -#if UNUSED -static void ahc_dump_targcmd(struct target_cmd *cmd); -#endif -static void ahc_shutdown(void *arg, int howto); -static cam_status - ahc_find_tmode_devs(struct ahc_softc *ahc, - struct cam_sim *sim, union ccb *ccb, - struct tmode_tstate **tstate, - struct tmode_lstate **lstate, - int notfound_failure); -static void ahc_action(struct cam_sim *sim, union ccb *ccb); -static void ahc_async(void *callback_arg, uint32_t code, - struct cam_path *path, void *arg); -static void ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, - int nsegments, int error); -static void ahc_poll(struct cam_sim *sim); -static void ahc_setup_data(struct ahc_softc *ahc, - struct ccb_scsiio *csio, struct scb *scb); -static void ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path); -static void ahcallocscbs(struct ahc_softc *ahc); -#if UNUSED -static void ahc_scb_devinfo(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct scb *scb); -#endif -static void ahc_fetch_devinfo(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -static void ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, - u_int target, u_int lun, char channel, - role_t role); -static u_int ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev); -static void ahc_done(struct ahc_softc *ahc, struct scb *scbp); -static struct tmode_tstate * - ahc_alloc_tstate(struct ahc_softc *ahc, - u_int scsi_id, char channel); -static void ahc_free_tstate(struct ahc_softc *ahc, - u_int scsi_id, char channel, int force); -static void ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, - union ccb *ccb); -static void ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask); -static int ahc_handle_target_cmd(struct ahc_softc *ahc, - struct target_cmd *cmd); -static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); -static void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat); -static void ahc_build_transfer_msg(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct scb *scb); -static void ahc_setup_target_msgin(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -static int ahc_handle_msg_reject(struct ahc_softc *ahc, +/* Our Sequencer Program */ +#include "aic7xxx_seq.h" + +/**************************** Function Declarations ***************************/ +static struct tmode_tstate* + ahc_alloc_tstate(struct ahc_softc *ahc, + u_int scsi_id, char channel); +static void ahc_free_tstate(struct ahc_softc *ahc, + u_int scsi_id, char channel, int force); +static struct ahc_syncrate* + ahc_devlimited_syncrate(struct ahc_softc *ahc, + u_int *period, + u_int *ppr_options); +static void ahc_update_target_msg_request(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct ahc_initiator_tinfo *tinfo, + int force, int paused); +static void ahc_update_pending_syncrates(struct ahc_softc *ahc); +static void ahc_fetch_devinfo(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_scb_devinfo(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct scb *scb); +static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct scb *scb); +static void ahc_build_transfer_msg(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_construct_sdtr(struct ahc_softc *ahc, + u_int period, u_int offset); +static void ahc_construct_wdtr(struct ahc_softc *ahc, + u_int bus_width); +static void ahc_construct_ppr(struct ahc_softc *ahc, + u_int period, u_int offset, + u_int bus_width, u_int ppr_options); +static void ahc_clear_msg_state(struct ahc_softc *ahc); +static void ahc_handle_message_phase(struct ahc_softc *ahc); +static int ahc_sent_msg(struct ahc_softc *ahc, + u_int msgtype, int full); +static int ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo); -static void ahc_clear_msg_state(struct ahc_softc *ahc); -static void ahc_handle_message_phase(struct ahc_softc *ahc, - struct cam_path *path); -static int ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full); -typedef enum { - MSGLOOP_IN_PROG, - MSGLOOP_MSGCOMPLETE, - MSGLOOP_TERMINATED -} msg_loop_stat; -static int ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, - struct ahc_devinfo *devinfo); -static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo); -static void ahc_handle_devreset(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - cam_status status, ac_code acode, - char *message, - int verbose_level); +static int ahc_handle_msg_reject(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +static void ahc_handle_devreset(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + cam_status status, char *message, + int verbose_level); + +static bus_dmamap_callback_t ahc_dmamap_cb; +static int ahc_init_scbdata(struct ahc_softc *ahc); +static void ahc_fini_scbdata(struct ahc_softc *ahc); + +static void ahc_busy_tcl(struct ahc_softc *ahc, + u_int tcl, u_int busyid); +static int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, + int target, char channel, int lun, + u_int tag, role_t role); + +static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, + u_int prev, u_int scbptr); +static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); +static u_int ahc_rem_wscb(struct ahc_softc *ahc, + u_int scbpos, u_int prev); +static int ahc_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status); +static void ahc_reset_current_bus(struct ahc_softc *ahc); +static void ahc_calc_residual(struct scb *scb); #ifdef AHC_DUMP_SEQ -static void ahc_dumpseq(struct ahc_softc *ahc); +static void ahc_dumpseq(struct ahc_softc *ahc); #endif -static void ahc_loadseq(struct ahc_softc *ahc); -static int ahc_check_patch(struct ahc_softc *ahc, - struct patch **start_patch, - u_int start_instr, u_int *skip_addr); -static void ahc_download_instr(struct ahc_softc *ahc, - u_int instrptr, uint8_t *dconsts); -static int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, - int target, char channel, int lun, u_int tag, - role_t role); -#ifdef AHC_DEBUG -static void ahc_print_scb(struct scb *scb); +static void ahc_loadseq(struct ahc_softc *ahc); +static int ahc_check_patch(struct ahc_softc *ahc, + struct patch **start_patch, + u_int start_instr, u_int *skip_addr); +static void ahc_download_instr(struct ahc_softc *ahc, + u_int instrptr, uint8_t *dconsts); +#ifdef AHC_TARGET_MODE +static void ahc_queue_lstate_event(struct ahc_softc *ahc, + struct tmode_lstate *lstate, + u_int initiator_id, + u_int event_type, + u_int event_arg); +static void ahc_update_scsiid(struct ahc_softc *ahc, + u_int targid_mask); +static int ahc_handle_target_cmd(struct ahc_softc *ahc, + struct target_cmd *cmd); #endif -static int ahc_search_qinfifo(struct ahc_softc *ahc, int target, - char channel, int lun, u_int tag, - role_t role, uint32_t status, - ahc_search_action action); -static void ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, - union ccb *ccb); -static int ahc_reset_channel(struct ahc_softc *ahc, char channel, - int initiate_reset); -static int ahc_abort_scbs(struct ahc_softc *ahc, int target, - char channel, int lun, u_int tag, role_t role, - uint32_t status); -static int ahc_search_disc_list(struct ahc_softc *ahc, int target, - char channel, int lun, u_int tag, - int stop_on_first, int remove, - int save_state); -static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, - u_int prev, u_int scbptr); -static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); -static void ahc_clear_intstat(struct ahc_softc *ahc); -static void ahc_reset_current_bus(struct ahc_softc *ahc); -static struct ahc_syncrate * - ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period, - u_int *ppr_options); -static struct ahc_syncrate * - ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, - u_int *ppr_options, u_int maxsync); -static u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate, - u_int maxsync); -static void ahc_validate_offset(struct ahc_softc *ahc, - struct ahc_syncrate *syncrate, - u_int *offset, int wide); -static void ahc_validate_width(struct ahc_softc *ahc, u_int *bus_width); -static void ahc_update_target_msg_request(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct ahc_initiator_tinfo *tinfo, - int force, int paused); -static int ahc_create_path(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct cam_path **path); -static void ahc_set_syncrate(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct cam_path *path, - struct ahc_syncrate *syncrate, - u_int period, u_int offset, - u_int ppr_options, u_int type, - int paused); -static void ahc_set_width(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct cam_path *path, u_int width, u_int type, - int paused); -static void ahc_set_tags(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - int enable); -static void ahc_construct_sdtr(struct ahc_softc *ahc, - u_int period, u_int offset); - -static void ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width); -static void ahc_construct_ppr(struct ahc_softc *ahc, u_int period, - u_int offset, u_int bus_width, - u_int ppr_options); - -static __inline int ahc_check_residual(struct scb *scb); -static void ahc_calc_residual(struct scb *scb); - -static void ahc_update_pending_syncrates(struct ahc_softc *ahc); - -static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); - -static timeout_t - ahc_timeout; -static void ahc_queue_lstate_event(struct ahc_softc *ahc, - struct tmode_lstate *lstate, - u_int initiator_id, u_int event_type, - u_int event_arg); -static void ahc_send_lstate_events(struct ahc_softc *ahc, - struct tmode_lstate *lstate); -static void restart_sequencer(struct ahc_softc *ahc); -static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, - u_int tcl, int unbusy); - -static __inline void ahc_freeze_ccb(union ccb* ccb); -static __inline cam_status ahc_ccb_status(union ccb* ccb); -static __inline void ahcsetccbstatus(union ccb* ccb, - cam_status status); -static void ahc_run_untagged_queues(struct ahc_softc *); -static void ahc_run_untagged_queue(struct ahc_softc *, - struct scb_tailq *); -static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); -static void ahc_run_qoutfifo(struct ahc_softc *ahc); - -static __inline struct ahc_initiator_tinfo * - ahc_fetch_transinfo(struct ahc_softc *ahc, - char channel, - u_int our_id, u_int target, - struct tmode_tstate **tstate); -static __inline struct ahc_dma_seg * - ahc_sg_bus_to_virt(struct scb *scb, - uint32_t sg_busaddr); -static __inline uint32_t - ahc_sg_virt_to_bus(struct scb *scb, - struct ahc_dma_seg *sg); -static __inline void ahc_queue_scb(struct ahc_softc *ahc, - struct scb *scb); -static void ahcfreescb(struct ahc_softc *ahc, struct scb *scb); -static __inline struct scb *ahcgetscb(struct ahc_softc *ahc); -static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc); -static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc); - -static __inline uint32_t -ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) -{ - return (ahc->scb_data->hscb_busaddr - + (sizeof(struct hardware_scb) * index)); -} - -#define AHC_BUSRESET_DELAY 250 /* Reset delay in us */ - +/************************* Sequencer Execution Control ************************/ /* * Restart the sequencer program from address zero */ -static void +void restart_sequencer(struct ahc_softc *ahc) { u_int i; pause_sequencer(ahc); + /* XXX Use critical code sections.... */ /* * Everytime we restart the sequencer, there * is the possiblitity that we have restarted @@ -466,213 +246,46 @@ restart_sequencer(struct ahc_softc *ahc) ahc_add_curscb_to_free_list(ahc); } } + ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ + ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ + ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); + /* Always allow reselection */ + ahc_outb(ahc, SCSISEQ, + ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); + if ((ahc->features & AHC_CMD_CHAN) != 0) { + /* Ensure that no DMA operations are in progress */ + ahc_outb(ahc, CCSGCTL, 0); + ahc_outb(ahc, CCSCBCTL, 0); + } + ahc_outb(ahc, MWI_RESIDUAL, 0); ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); unpause_sequencer(ahc); } -static u_int -ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) -{ - u_int scbid; - u_int target_offset; - - if ((ahc->features & AHC_SCB_BTT) != 0) { - u_int saved_scbptr; - - saved_scbptr = ahc_inb(ahc, SCBPTR); - ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); - scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); - if (unbusy) - ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), - SCB_LIST_NULL); - ahc_outb(ahc, SCBPTR, saved_scbptr); - } else { - target_offset = TCL_TARGET_OFFSET(tcl); - scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); - if (unbusy) - ahc_outb(ahc, BUSY_TARGETS + target_offset, - SCB_LIST_NULL); - } - - return (scbid); -} - -static __inline int -ahc_check_residual(struct scb *scb) -{ - struct status_pkt *sp; - - sp = &scb->hscb->shared_data.status; - if ((scb->hscb->sgptr & SG_RESID_VALID) != 0) - return (1); - return (0); -} - -static __inline void -ahc_freeze_ccb(union ccb* ccb) -{ - if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { - ccb->ccb_h.status |= CAM_DEV_QFRZN; - xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); - } -} - -static __inline cam_status -ahc_ccb_status(union ccb* ccb) -{ - return (ccb->ccb_h.status & CAM_STATUS_MASK); -} - -static __inline void -ahcsetccbstatus(union ccb* ccb, cam_status status) -{ - ccb->ccb_h.status &= ~CAM_STATUS_MASK; - ccb->ccb_h.status |= status; -} - -static __inline struct ahc_initiator_tinfo * -ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, - u_int remote_id, struct tmode_tstate **tstate) -{ - /* - * Transfer data structures are stored from the perspective - * of the target role. Since the parameters for a connection - * in the initiator role to a given target are the same as - * when the roles are reversed, we pretend we are the target. - */ - if (channel == 'B') - our_id += 8; - *tstate = ahc->enabled_targets[our_id]; - return (&(*tstate)->transinfo[remote_id]); -} - -static __inline struct ahc_dma_seg * -ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) -{ - int sg_index; - - sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg); - /* sg_list_phys points to entry 1, not 0 */ - sg_index++; - - return (&scb->sg_list[sg_index]); -} - -static __inline uint32_t -ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg) -{ - int sg_index; - - /* sg_list_phys points to entry 1, not 0 */ - sg_index = sg - &scb->sg_list[1]; - - return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list))); -} - -static __inline void -ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb) -{ - ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; - if ((ahc->features & AHC_QUEUE_REGS) != 0) { - ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); - } else { - pause_sequencer(ahc); - ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); - unpause_sequencer(ahc); - } -} - -static __inline void -ahc_freeze_untagged_queues(struct ahc_softc *ahc) -{ - if ((ahc->features & AHC_SCB_BTT) == 0) - ahc->untagged_queue_lock++; -} - -static __inline void -ahc_release_untagged_queues(struct ahc_softc *ahc) -{ - if ((ahc->features & AHC_SCB_BTT) == 0) { - ahc->untagged_queue_lock--; - if (ahc->untagged_queue_lock == 0) - ahc_run_untagged_queues(ahc); - } -} - -static void -ahc_run_untagged_queues(struct ahc_softc *ahc) -{ - int i; - - for (i = 0; i < 16; i++) - ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); -} - -static void -ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) -{ - struct scb *scb; - - if (ahc->untagged_queue_lock != 0) - return; - - if ((scb = TAILQ_FIRST(queue)) != NULL - && (scb->flags & SCB_ACTIVE) == 0) { - scb->flags |= SCB_ACTIVE; - ahc_queue_scb(ahc, scb); - } -} - -static void -ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) -{ - struct target_cmd *cmd; - - while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { - - /* - * Only advance through the queue if we - * have the resources to process the command. - */ - if (ahc_handle_target_cmd(ahc, cmd) != 0) - break; - - ahc->tqinfifonext++; - cmd->cmd_valid = 0; - - /* - * Lazily update our position in the target mode incomming - * command queue as seen by the sequencer. - */ - if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { - if ((ahc->features & AHC_HS_MAILBOX) != 0) { - u_int hs_mailbox; - - hs_mailbox = ahc_inb(ahc, HS_MAILBOX); - hs_mailbox &= ~HOST_TQINPOS; - hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; - ahc_outb(ahc, HS_MAILBOX, hs_mailbox); - } else { - if (!paused) - pause_sequencer(ahc); - ahc_outb(ahc, KERNEL_TQINPOS, - ahc->tqinfifonext & HOST_TQINPOS); - if (!paused) - unpause_sequencer(ahc); - } - } - } -} - -static void +/************************* Input/Output Queues ********************************/ +void ahc_run_qoutfifo(struct ahc_softc *ahc) { struct scb *scb; u_int scb_index; while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { + scb_index = ahc->qoutfifo[ahc->qoutfifonext]; - ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; + if ((ahc->qoutfifonext & 0x03) == 0x03) { + u_int modnext; + + /* + * Clear 32bits of QOUTFIFO at a time + * so that we don't clobber an incomming + * byte DMA to the array on architectures + * that only support 32bit load and store + * operations. + */ + modnext = ahc->qoutfifonext & ~0x3; + *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; + } + ahc->qoutfifonext++; scb = &ahc->scb_data->scbarray[scb_index]; if (scb_index >= ahc->scb_data->numscbs @@ -691,1736 +304,61 @@ ahc_run_qoutfifo(struct ahc_softc *ahc) if (ahc_check_residual(scb) != 0) ahc_calc_residual(scb); else - scb->ccb->csio.resid = 0; + ahc_set_residual(scb, 0); ahc_done(ahc, scb); } } - -/* - * Return an SCB resource to the free list. - */ -static void -ahcfreescb(struct ahc_softc *ahc, struct scb *scb) -{ - struct hardware_scb *hscb; - int opri; - - hscb = scb->hscb; - - opri = splcam(); - - if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 - && (scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { - scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; - ahc->flags &= ~AHC_RESOURCE_SHORTAGE; - } - - /* Clean up for the next user */ - scb->flags = SCB_FREE; - hscb->control = 0; - - SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle); - splx(opri); -} - -/* - * Get a free scb. If there are none, see if we can allocate a new SCB. - */ -static __inline struct scb * -ahcgetscb(struct ahc_softc *ahc) -{ - struct scb *scbp; - int opri; - - opri = splcam(); - if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { - SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); - } else { - ahcallocscbs(ahc); - scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); - if (scbp != NULL) - SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); - } - - splx(opri); - - return (scbp); -} - -char * -ahc_name(struct ahc_softc *ahc) -{ - static char name[10]; - - snprintf(name, sizeof(name), "ahc%d", ahc->unit); - return (name); -} - -#ifdef AHC_DEBUG -static void -ahc_print_scb(struct scb *scb) -{ - int i; - - struct hardware_scb *hscb = scb->hscb; - - printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", - scb, - hscb->control, - hscb->scsiid, - hscb->lun, - hscb->cdb_len); - i = 0; - printf("Shared Data: %#02x %#02x %#02x %#02x\n", - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++]); - printf(" %#02x %#02x %#02x %#02x\n", - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++]); - printf(" %#02x %#02x %#02x %#02x\n", - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++], - hscb->shared_data.cdb[i++]); - printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", - hscb->dataptr, - hscb->datacnt, - hscb->sgptr, - hscb->tag); - if (scb->sg_count > 0) { - for (i = 0; i < scb->sg_count; i++) { - printf("sg[%d] - Addr 0x%x : Length %d\n", - i, - scb->sg_list[i].addr, - scb->sg_list[i].len); - } - } -} -#endif - -static struct { - uint8_t errno; - char *errmesg; -} hard_error[] = { - { ILLHADDR, "Illegal Host Access" }, - { ILLSADDR, "Illegal Sequencer Address referrenced" }, - { ILLOPCODE, "Illegal Opcode in sequencer program" }, - { SQPARERR, "Sequencer Parity Error" }, - { DPARERR, "Data-path Parity Error" }, - { MPARERR, "Scratch or SCB Memory Parity Error" }, - { PCIERRSTAT, "PCI Error detected" }, - { CIOPARERR, "CIOBUS Parity Error" }, -}; -static const int num_errors = sizeof(hard_error)/sizeof(hard_error[0]); - -static struct { - uint8_t phase; - uint8_t mesg_out; /* Message response to parity errors */ - char *phasemsg; -} phase_table[] = { - { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, - { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, - { P_COMMAND, MSG_NOOP, "in Command phase" }, - { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, - { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, - { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, - { P_BUSFREE, MSG_NOOP, "while idle" }, - { 0, MSG_NOOP, "in unknown phase" } -}; -static const u_int num_phases = - (sizeof(phase_table)/sizeof(phase_table[0])) - 1; - -/* - * Valid SCSIRATE values. (p. 3-17) - * Provides a mapping of tranfer periods in ns to the proper value to - * stick in the scsiscfr reg to use that transfer rate. - */ -#define AHC_SYNCRATE_DT 0 -#define AHC_SYNCRATE_ULTRA2 1 -#define AHC_SYNCRATE_ULTRA 3 -#define AHC_SYNCRATE_FAST 6 -static struct ahc_syncrate ahc_syncrates[] = { - /* ultra2 fast/ultra period rate */ - { 0x42, 0x000, 9, "80.0" }, - { 0x03, 0x000, 10, "40.0" }, - { 0x04, 0x000, 11, "33.0" }, - { 0x05, 0x100, 12, "20.0" }, - { 0x06, 0x110, 15, "16.0" }, - { 0x07, 0x120, 18, "13.4" }, - { 0x08, 0x000, 25, "10.0" }, - { 0x19, 0x010, 31, "8.0" }, - { 0x1a, 0x020, 37, "6.67" }, - { 0x1b, 0x030, 43, "5.7" }, - { 0x1c, 0x040, 50, "5.0" }, - { 0x00, 0x050, 56, "4.4" }, - { 0x00, 0x060, 62, "4.0" }, - { 0x00, 0x070, 68, "3.6" }, - { 0x00, 0x000, 0, NULL } -}; - -void -ahc_init_probe_config(struct ahc_probe_config *probe_config) -{ - probe_config->description = NULL; - probe_config->channel = 'A'; - probe_config->channel_b = 'B'; - probe_config->chip = AHC_NONE; - probe_config->features = AHC_FENONE; - probe_config->bugs = AHC_BUGNONE; - probe_config->flags = AHC_FNONE; -} - -/* - * Allocate a controller structure for a new device and initialize it. - */ -struct ahc_softc * -ahc_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id, - bus_dma_tag_t parent_dmat, struct ahc_probe_config *config, - struct scb_data *scb_data) -{ - /* - * find unit and check we have that many defined - */ - struct ahc_softc *ahc; - size_t alloc_size; - int i; - - /* - * Allocate a storage area for us. - */ - if (scb_data == NULL) - /* - * We are not sharing SCB space with another controller - * so allocate our own SCB data space. - */ - alloc_size = sizeof(struct full_ahc_softc); - else - alloc_size = sizeof(struct ahc_softc); - ahc = malloc(alloc_size, M_DEVBUF, M_NOWAIT); - if (!ahc) { - device_printf(dev, "cannot malloc softc!\n"); - return NULL; - } - bzero(ahc, alloc_size); - LIST_INIT(&ahc->pending_ccbs); - ahc->device = dev; - ahc->unit = device_get_unit(dev); - ahc->regs_res_type = regs_type; - ahc->regs_res_id = regs_id; - ahc->regs = regs; - ahc->tag = rman_get_bustag(regs); - ahc->bsh = rman_get_bushandle(regs); - ahc->parent_dmat = parent_dmat; - ahc->chip = config->chip; - ahc->features = config->features; - ahc->bugs = config->bugs; - ahc->flags = config->flags; - ahc->channel = config->channel; - for (i = 0; i < 16; i++) - TAILQ_INIT(&ahc->untagged_queues[i]); - - if (scb_data == NULL) { - struct full_ahc_softc* full_softc = (struct full_ahc_softc*)ahc; - ahc->scb_data = &full_softc->scb_data_storage; - } else - ahc->scb_data = scb_data; - - ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; - /* The IRQMS bit is only valid on VL and EISA chips */ - if ((ahc->chip & AHC_PCI) != 0) - ahc->unpause &= ~IRQMS; - ahc->pause = ahc->unpause | PAUSE; - return (ahc); -} - void -ahc_free(ahc) - struct ahc_softc *ahc; -{ - ahcfiniscbdata(ahc); - switch (ahc->init_level) { - case 3: - bus_dmamap_unload(ahc->shared_data_dmat, - ahc->shared_data_dmamap); - case 2: - bus_dmamem_free(ahc->shared_data_dmat, ahc->qoutfifo, - ahc->shared_data_dmamap); - bus_dmamap_destroy(ahc->shared_data_dmat, - ahc->shared_data_dmamap); - case 1: - bus_dma_tag_destroy(ahc->buffer_dmat); - break; - } - - if (ahc->regs != NULL) - bus_release_resource(ahc->device, ahc->regs_res_type, - ahc->regs_res_id, ahc->regs); - if (ahc->irq != NULL) - bus_release_resource(ahc->device, ahc->irq_res_type, - 0, ahc->irq); - - free(ahc, M_DEVBUF); - return; -} - -static int -ahcinitscbdata(struct ahc_softc *ahc) +ahc_run_untagged_queues(struct ahc_softc *ahc) { - struct scb_data *scb_data; int i; - scb_data = ahc->scb_data; - SLIST_INIT(&scb_data->free_scbs); - SLIST_INIT(&scb_data->sg_maps); - - /* Allocate SCB resources */ - scb_data->scbarray = - (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, - M_DEVBUF, M_NOWAIT); - if (scb_data->scbarray == NULL) - return (ENOMEM); - bzero(scb_data->scbarray, sizeof(struct scb) * AHC_SCB_MAX); - - /* Determine the number of hardware SCBs and initialize them */ - - scb_data->maxhscbs = ahc_probe_scbs(ahc); - /* SCB 0 heads the free list */ - ahc_outb(ahc, FREE_SCBH, 0); - for (i = 0; i < ahc->scb_data->maxhscbs; i++) { - ahc_outb(ahc, SCBPTR, i); - - /* Clear the control byte. */ - ahc_outb(ahc, SCB_CONTROL, 0); - - /* Set the next pointer */ - ahc_outb(ahc, SCB_NEXT, i+1); - - /* Make the tag number invalid */ - ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); - } - - /* Make sure that the last SCB terminates the free list */ - ahc_outb(ahc, SCBPTR, i-1); - ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); - - /* Ensure we clear the 0 SCB's control byte. */ - ahc_outb(ahc, SCBPTR, 0); - ahc_outb(ahc, SCB_CONTROL, 0); - - scb_data->maxhscbs = i; - - if (ahc->scb_data->maxhscbs == 0) - panic("%s: No SCB space found", ahc_name(ahc)); - - /* - * Create our DMA tags. These tags define the kinds of device - * accessible memory allocations and memory mappings we will - * need to perform during normal operation. - * - * Unless we need to further restrict the allocation, we rely - * on the restrictions of the parent dmat, hence the common - * use of MAXADDR and MAXSIZE. - */ - - /* DMA tag for our hardware scb structures */ - if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0, - /*lowaddr*/BUS_SPACE_MAXADDR, - /*highaddr*/BUS_SPACE_MAXADDR, - /*filter*/NULL, /*filterarg*/NULL, - AHC_SCB_MAX * sizeof(struct hardware_scb), - /*nsegments*/1, - /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, - /*flags*/0, &scb_data->hscb_dmat) != 0) { - goto error_exit; - } - - scb_data->init_level++; - - /* Allocation for our ccbs */ - if (bus_dmamem_alloc(scb_data->hscb_dmat, (void **)&scb_data->hscbs, - BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { - goto error_exit; - } - - scb_data->init_level++; - - /* And permanently map them */ - bus_dmamap_load(scb_data->hscb_dmat, scb_data->hscb_dmamap, - scb_data->hscbs, - AHC_SCB_MAX * sizeof(struct hardware_scb), - ahcdmamapcb, &scb_data->hscb_busaddr, /*flags*/0); - - scb_data->init_level++; - - /* DMA tag for our sense buffers */ - if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0, - /*lowaddr*/BUS_SPACE_MAXADDR, - /*highaddr*/BUS_SPACE_MAXADDR, - /*filter*/NULL, /*filterarg*/NULL, - AHC_SCB_MAX * sizeof(struct scsi_sense_data), - /*nsegments*/1, - /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, - /*flags*/0, &scb_data->sense_dmat) != 0) { - goto error_exit; - } - - scb_data->init_level++; - - /* Allocate them */ - if (bus_dmamem_alloc(scb_data->sense_dmat, (void **)&scb_data->sense, - BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { - goto error_exit; - } - - scb_data->init_level++; - - /* And permanently map them */ - bus_dmamap_load(scb_data->sense_dmat, scb_data->sense_dmamap, - scb_data->sense, - AHC_SCB_MAX * sizeof(struct scsi_sense_data), - ahcdmamapcb, &scb_data->sense_busaddr, /*flags*/0); - - scb_data->init_level++; - - /* DMA tag for our S/G structures. We allocate in page sized chunks */ - if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0, - /*lowaddr*/BUS_SPACE_MAXADDR, - /*highaddr*/BUS_SPACE_MAXADDR, - /*filter*/NULL, /*filterarg*/NULL, - PAGE_SIZE, /*nsegments*/1, - /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, - /*flags*/0, &scb_data->sg_dmat) != 0) { - goto error_exit; - } - - scb_data->init_level++; - - /* Perform initial CCB allocation */ - bzero(scb_data->hscbs, AHC_SCB_MAX * sizeof(struct hardware_scb)); - ahcallocscbs(ahc); - - if (scb_data->numscbs == 0) { - printf("%s: ahc_init_scb_data - " - "Unable to allocate initial scbs\n", - ahc_name(ahc)); - goto error_exit; - } - - /* - * Note that we were successfull - */ - return 0; - -error_exit: - - return ENOMEM; -} - -static void -ahcfiniscbdata(struct ahc_softc *ahc) -{ - struct scb_data *scb_data; - - scb_data = ahc->scb_data; - - switch (scb_data->init_level) { - default: - case 7: - { - struct sg_map_node *sg_map; - - while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { - SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); - bus_dmamap_unload(scb_data->sg_dmat, - sg_map->sg_dmamap); - bus_dmamem_free(scb_data->sg_dmat, sg_map->sg_vaddr, - sg_map->sg_dmamap); - free(sg_map, M_DEVBUF); - } - bus_dma_tag_destroy(scb_data->sg_dmat); - } - case 6: - bus_dmamap_unload(scb_data->sense_dmat, - scb_data->sense_dmamap); - case 5: - bus_dmamem_free(scb_data->sense_dmat, scb_data->sense, - scb_data->sense_dmamap); - bus_dmamap_destroy(scb_data->sense_dmat, - scb_data->sense_dmamap); - case 4: - bus_dma_tag_destroy(scb_data->sense_dmat); - case 3: - bus_dmamap_unload(scb_data->hscb_dmat, scb_data->hscb_dmamap); - case 2: - bus_dmamem_free(scb_data->hscb_dmat, scb_data->hscbs, - scb_data->hscb_dmamap); - bus_dmamap_destroy(scb_data->hscb_dmat, scb_data->hscb_dmamap); - case 1: - bus_dma_tag_destroy(scb_data->hscb_dmat); - break; - } - if (scb_data->scbarray != NULL) - free(scb_data->scbarray, M_DEVBUF); -} - -static void -ahcdmamapcb(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - bus_addr_t *baddr; - - baddr = (bus_addr_t *)arg; - *baddr = segs->ds_addr; -} - -int -ahc_reset(struct ahc_softc *ahc) -{ - u_int sblkctl; - u_int sxfrctl1; - int wait; - -#ifdef AHC_DUMP_SEQ - if (ahc->init_level == 0) - ahc_dumpseq(ahc); -#endif - - /* Cache STPWEN. It is cleared by a chip reset */ - pause_sequencer(ahc); - sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; - ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); - /* - * Ensure that the reset has finished - */ - wait = 1000; - do { - DELAY(1000); - } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); - - if (wait == 0) { - printf("%s: WARNING - Failed chip reset! " - "Trying to initialize anyway.\n", ahc_name(ahc)); - } - ahc_outb(ahc, HCNTRL, ahc->pause); - /* - * Reload sxfrctl1 with the cached value of STPWEN - * to minimize the amount of time our terminators - * are disabled. If a BIOS has initialized the chip, - * then sxfrctl1 will have the correct value. If - * not, STPWEN will be false (the value after a POST) - * and this action will be harmless. - * - * We must always initialize STPWEN to 1 before we - * restore the saved value. STPWEN is initialized - * to a tri-state condition which is only be cleared - * by turning it on. - */ - ahc_outb(ahc, SXFRCTL1, sxfrctl1|STPWEN); - ahc_outb(ahc, SXFRCTL1, sxfrctl1); - - /* Determine channel configuration */ - sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); - /* No Twin Channel PCI cards */ - if ((ahc->chip & AHC_PCI) != 0) - sblkctl &= ~SELBUSB; - switch (sblkctl) { - case 0: - /* Single Narrow Channel */ - break; - case 2: - /* Wide Channel */ - ahc->features |= AHC_WIDE; - break; - case 8: - /* Twin Channel */ - ahc->features |= AHC_TWIN; - break; - default: - printf(" Unsupported adapter type. Ignoring\n"); - return(-1); - } - - return (0); -} - -/* - * Called when we have an active connection to a target on the bus, - * this function finds the nearest syncrate to the input period limited - * by the capabilities of the bus connectivity of the target. - */ -static struct ahc_syncrate * -ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period, - u_int *ppr_options) { - u_int maxsync; - - if ((ahc->features & AHC_ULTRA2) != 0) { - if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 - && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { - maxsync = AHC_SYNCRATE_DT; - } else { - maxsync = AHC_SYNCRATE_ULTRA; - /* Can't do DT on an SE bus */ - *ppr_options &= ~MSG_EXT_PPR_DT_REQ; - } - } else if ((ahc->features & AHC_ULTRA) != 0) { - maxsync = AHC_SYNCRATE_ULTRA; - } else { - maxsync = AHC_SYNCRATE_FAST; - } - return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); -} - -/* - * Look up the valid period to SCSIRATE conversion in our table. - * Return the period and offset that should be sent to the target - * if this was the beginning of an SDTR. - */ -static struct ahc_syncrate * -ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, - u_int *ppr_options, u_int maxsync) -{ - struct ahc_syncrate *syncrate; - - if ((ahc->features & AHC_DT) == 0) - *ppr_options &= ~MSG_EXT_PPR_DT_REQ; - - for (syncrate = &ahc_syncrates[maxsync]; - syncrate->rate != NULL; - syncrate++) { - - /* - * The Ultra2 table doesn't go as low - * as for the Fast/Ultra cards. - */ - if ((ahc->features & AHC_ULTRA2) != 0 - && (syncrate->sxfr_u2 == 0)) - break; - - /* Skip any DT entries if DT is not available */ - if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 - && (syncrate->sxfr_u2 & DT_SXFR) != 0) - continue; - - if (*period <= syncrate->period) { - /* - * When responding to a target that requests - * sync, the requested rate may fall between - * two rates that we can output, but still be - * a rate that we can receive. Because of this, - * we want to respond to the target with - * the same rate that it sent to us even - * if the period we use to send data to it - * is lower. Only lower the response period - * if we must. - */ - if (syncrate == &ahc_syncrates[maxsync]) - *period = syncrate->period; - - /* - * At some speeds, we only support - * ST transfers. - */ - if ((syncrate->sxfr_u2 & ST_SXFR) != 0) - *ppr_options &= ~MSG_EXT_PPR_DT_REQ; - break; - } - } - - if ((*period == 0) - || (syncrate->rate == NULL) - || ((ahc->features & AHC_ULTRA2) != 0 - && (syncrate->sxfr_u2 == 0))) { - /* Use asynchronous transfers. */ - *period = 0; - syncrate = NULL; - *ppr_options &= ~MSG_EXT_PPR_DT_REQ; - } - return (syncrate); -} - -static u_int -ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) -{ - struct ahc_syncrate *syncrate; - - if ((ahc->features & AHC_ULTRA2) != 0) - scsirate &= SXFR_ULTRA2; - else - scsirate &= SXFR; - - syncrate = &ahc_syncrates[maxsync]; - while (syncrate->rate != NULL) { - - if ((ahc->features & AHC_ULTRA2) != 0) { - if (syncrate->sxfr_u2 == 0) - break; - else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) - return (syncrate->period); - } else if (scsirate == (syncrate->sxfr & SXFR)) { - return (syncrate->period); - } - syncrate++; - } - return (0); /* async */ -} - -static void -ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, - u_int *offset, int wide) -{ - u_int maxoffset; - - /* Limit offset to what we can do */ - if (syncrate == NULL) { - maxoffset = 0; - } else if ((ahc->features & AHC_ULTRA2) != 0) { - maxoffset = MAX_OFFSET_ULTRA2; - } else { - if (wide) - maxoffset = MAX_OFFSET_16BIT; - else - maxoffset = MAX_OFFSET_8BIT; - } - *offset = MIN(*offset, maxoffset); -} - - -static void -ahc_validate_width(struct ahc_softc *ahc, u_int *bus_width) -{ - switch (*bus_width) { - default: - if (ahc->features & AHC_WIDE) { - /* Respond Wide */ - *bus_width = MSG_EXT_WDTR_BUS_16_BIT; - break; - } - /* FALLTHROUGH */ - case MSG_EXT_WDTR_BUS_8_BIT: - bus_width = MSG_EXT_WDTR_BUS_8_BIT; - break; - } -} - -static void -ahc_update_target_msg_request(struct ahc_softc *ahc, - struct ahc_devinfo *devinfo, - struct ahc_initiator_tinfo *tinfo, - int force, int paused) -{ - u_int targ_msg_req_orig; - - targ_msg_req_orig = ahc->targ_msg_req; - if (tinfo->current.period != tinfo->goal.period - || tinfo->current.width != tinfo->goal.width - || tinfo->current.offset != tinfo->goal.offset - || (force - && (tinfo->goal.period != 0 - || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) - ahc->targ_msg_req |= devinfo->target_mask; - else - ahc->targ_msg_req &= ~devinfo->target_mask; - - if (ahc->targ_msg_req != targ_msg_req_orig) { - /* Update the message request bit for this target */ - if (!paused) - pause_sequencer(ahc); - - ahc_outb(ahc, TARGET_MSG_REQUEST, - ahc->targ_msg_req & 0xFF); - ahc_outb(ahc, TARGET_MSG_REQUEST + 1, - (ahc->targ_msg_req >> 8) & 0xFF); - - if (!paused) - unpause_sequencer(ahc); - } -} - -static int -ahc_create_path(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, - struct cam_path **path) -{ - path_id_t path_id; - - if (devinfo->channel == 'B') - path_id = cam_sim_path(ahc->sim_b); - else - path_id = cam_sim_path(ahc->sim); - - return (xpt_create_path(path, /*periph*/NULL, - path_id, devinfo->target, - devinfo->lun)); -} - -static void -ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, - struct cam_path *path, struct ahc_syncrate *syncrate, - u_int period, u_int offset, u_int ppr_options, - u_int type, int paused) -{ - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int old_period; - u_int old_offset; - int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; - - if (syncrate == NULL) { - period = 0; - offset = 0; - } - - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, - devinfo->target, &tstate); - old_period = tinfo->current.period; - old_offset = tinfo->current.offset; - - if ((type & AHC_TRANS_CUR) != 0 - && (old_period != period || old_offset != offset)) { - struct cam_path *path2; - u_int scsirate; - - scsirate = tinfo->scsirate; - if ((ahc->features & AHC_ULTRA2) != 0) { - - scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); - if (syncrate != NULL) { - scsirate |= syncrate->sxfr_u2; - if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) - scsirate |= ENABLE_CRC; - else - scsirate |= SINGLE_EDGE; - } - if (active) - ahc_outb(ahc, SCSIOFFSET, offset); - } else { - - scsirate &= ~(SXFR|SOFS); - /* - * Ensure Ultra mode is set properly for - * this target. - */ - tstate->ultraenb &= ~devinfo->target_mask; - if (syncrate != NULL) { - if (syncrate->sxfr & ULTRA_SXFR) { - tstate->ultraenb |= - devinfo->target_mask; - } - scsirate |= syncrate->sxfr & SXFR; - scsirate |= offset & SOFS; - } - if (active) { - u_int sxfrctl0; - - sxfrctl0 = ahc_inb(ahc, SXFRCTL0); - sxfrctl0 &= ~FAST20; - if (tstate->ultraenb & devinfo->target_mask) - sxfrctl0 |= FAST20; - ahc_outb(ahc, SXFRCTL0, sxfrctl0); - } - } - if (active) - ahc_outb(ahc, SCSIRATE, scsirate); - - tinfo->scsirate = scsirate; - tinfo->current.period = period; - tinfo->current.offset = offset; - tinfo->current.ppr_options = ppr_options; - - /* Update the syncrates in any pending scbs */ - ahc_update_pending_syncrates(ahc); - - /* - * If possible, tell the SCSI layer about the - * new transfer parameters. - */ - /* If possible, update the XPT's notion of our transfer rate */ - path2 = NULL; - if (path == NULL) { - int error; - - error = ahc_create_path(ahc, devinfo, &path2); - if (error == CAM_REQ_CMP) - path = path2; - else - path2 = NULL; - } - - if (path != NULL) { - struct ccb_trans_settings neg; - - neg.flags = CCB_TRANS_CURRENT_SETTINGS; - neg.sync_period = period; - neg.sync_offset = offset; - neg.valid = CCB_TRANS_SYNC_RATE_VALID - | CCB_TRANS_SYNC_OFFSET_VALID; - xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); - xpt_async(AC_TRANSFER_NEG, path, &neg); - } - - if (path2 != NULL) - xpt_free_path(path2); - - if (bootverbose) { - if (offset != 0) { - printf("%s: target %d synchronous at %sMHz%s, " - "offset = 0x%x\n", ahc_name(ahc), - devinfo->target, syncrate->rate, - (ppr_options & MSG_EXT_PPR_DT_REQ) - ? " DT" : "", offset); - } else { - printf("%s: target %d using " - "asynchronous transfers\n", - ahc_name(ahc), devinfo->target); - } - } - } - - if ((type & AHC_TRANS_GOAL) != 0) { - tinfo->goal.period = period; - tinfo->goal.offset = offset; - tinfo->goal.ppr_options = ppr_options; - } - - if ((type & AHC_TRANS_USER) != 0) { - tinfo->user.period = period; - tinfo->user.offset = offset; - tinfo->user.ppr_options = ppr_options; - } - - ahc_update_target_msg_request(ahc, devinfo, tinfo, - /*force*/FALSE, - paused); -} - -static void -ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, - struct cam_path *path, u_int width, u_int type, int paused) -{ - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int oldwidth; - int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; - - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, - devinfo->target, &tstate); - oldwidth = tinfo->current.width; - - if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { - struct cam_path *path2; - u_int scsirate; - - scsirate = tinfo->scsirate; - scsirate &= ~WIDEXFER; - if (width == MSG_EXT_WDTR_BUS_16_BIT) - scsirate |= WIDEXFER; - - tinfo->scsirate = scsirate; - - if (active) - ahc_outb(ahc, SCSIRATE, scsirate); - - tinfo->current.width = width; - - /* If possible, update the XPT's notion of our transfer rate */ - path2 = NULL; - if (path == NULL) { - int error; - - error = ahc_create_path(ahc, devinfo, &path2); - if (error == CAM_REQ_CMP) - path = path2; - else - path2 = NULL; - } - - if (path != NULL) { - struct ccb_trans_settings neg; - - neg.flags = CCB_TRANS_CURRENT_SETTINGS; - neg.bus_width = width; - neg.valid = CCB_TRANS_BUS_WIDTH_VALID; - xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); - xpt_async(AC_TRANSFER_NEG, path, &neg); - } - - if (path2 != NULL) - xpt_free_path(path2); - - if (bootverbose) { - printf("%s: target %d using %dbit transfers\n", - ahc_name(ahc), devinfo->target, - 8 * (0x01 << width)); - } - } - if ((type & AHC_TRANS_GOAL) != 0) - tinfo->goal.width = width; - if ((type & AHC_TRANS_USER) != 0) - tinfo->user.width = width; - - ahc_update_target_msg_request(ahc, devinfo, tinfo, - /*force*/FALSE, paused); -} - -static void -ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) -{ - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, - devinfo->target, &tstate); - - if (enable) - tstate->tagenable |= devinfo->target_mask; - else - tstate->tagenable &= ~devinfo->target_mask; -} - -/* - * Attach all the sub-devices we can find - */ -int -ahc_attach(struct ahc_softc *ahc) -{ - struct ccb_setasync csa; - struct cam_devq *devq; - int bus_id; - int bus_id2; - struct cam_sim *sim; - struct cam_sim *sim2; - struct cam_path *path; - struct cam_path *path2; - int count; - int s; - int error; - - count = 0; - sim = NULL; - sim2 = NULL; - - s = splcam(); - /* Hook up our interrupt handler */ - if ((error = bus_setup_intr(ahc->device, ahc->irq, INTR_TYPE_CAM, - ahc_intr, ahc, &ahc->ih)) != 0) { - device_printf(ahc->device, "bus_setup_intr() failed: %d\n", - error); - goto fail; - } - - /* - * Attach secondary channel first if the user has - * declared it the primary channel. - */ - if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { - bus_id = 1; - bus_id2 = 0; - } else { - bus_id = 0; - bus_id2 = 1; - } - - /* - * Create the device queue for our SIM(s). - */ - devq = cam_simq_alloc(AHC_SCB_MAX); - if (devq == NULL) - goto fail; - - /* - * Construct our first channel SIM entry - */ - sim = cam_sim_alloc(ahc_action, ahc_poll, "ahc", ahc, ahc->unit, - 1, AHC_SCB_MAX, devq); - if (sim == NULL) { - cam_simq_free(devq); - goto fail; - } - - if (xpt_bus_register(sim, bus_id) != CAM_SUCCESS) { - cam_sim_free(sim, /*free_devq*/TRUE); - sim = NULL; - goto fail; - } - - if (xpt_create_path(&path, /*periph*/NULL, - cam_sim_path(sim), CAM_TARGET_WILDCARD, - CAM_LUN_WILDCARD) != CAM_REQ_CMP) { - xpt_bus_deregister(cam_sim_path(sim)); - cam_sim_free(sim, /*free_devq*/TRUE); - sim = NULL; - goto fail; - } - - xpt_setup_ccb(&csa.ccb_h, path, /*priority*/5); - csa.ccb_h.func_code = XPT_SASYNC_CB; - csa.event_enable = AC_LOST_DEVICE; - csa.callback = ahc_async; - csa.callback_arg = sim; - xpt_action((union ccb *)&csa); - count++; - - if (ahc->features & AHC_TWIN) { - sim2 = cam_sim_alloc(ahc_action, ahc_poll, "ahc", - ahc, ahc->unit, 1, - AHC_SCB_MAX, devq); - - if (sim2 == NULL) { - printf("ahc_attach: Unable to attach second " - "bus due to resource shortage"); - goto fail; - } - - if (xpt_bus_register(sim2, bus_id2) != CAM_SUCCESS) { - printf("ahc_attach: Unable to attach second " - "bus due to resource shortage"); - /* - * We do not want to destroy the device queue - * because the first bus is using it. - */ - cam_sim_free(sim2, /*free_devq*/FALSE); - goto fail; - } - - if (xpt_create_path(&path2, /*periph*/NULL, - cam_sim_path(sim2), - CAM_TARGET_WILDCARD, - CAM_LUN_WILDCARD) != CAM_REQ_CMP) { - xpt_bus_deregister(cam_sim_path(sim2)); - cam_sim_free(sim2, /*free_devq*/FALSE); - sim2 = NULL; - goto fail; - } - xpt_setup_ccb(&csa.ccb_h, path2, /*priority*/5); - csa.ccb_h.func_code = XPT_SASYNC_CB; - csa.event_enable = AC_LOST_DEVICE; - csa.callback = ahc_async; - csa.callback_arg = sim2; - xpt_action((union ccb *)&csa); - count++; - } - -fail: - if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { - ahc->sim_b = sim; - ahc->path_b = path; - ahc->sim = sim2; - ahc->path = path2; - } else { - ahc->sim = sim; - ahc->path = path; - ahc->sim_b = sim2; - ahc->path_b = path2; - } - splx(s); - return (count); -} - -#if UNUSED -static void -ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, - struct scb *scb) -{ - role_t role; - int our_id; - - if (scb->ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { - our_id = scb->ccb->ccb_h.target_id; - role = ROLE_TARGET; - } else { - our_id = SCB_GET_CHANNEL(scb) == 'B' ? ahc->our_id_b : ahc->our_id; - role = ROLE_INITIATOR; - } - ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), - SCB_GET_LUN(scb), SCB_GET_CHANNEL(scb), role); -} -#endif - -static void -ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) -{ - u_int saved_scsiid; - role_t role; - int our_id; - - if (ahc_inb(ahc, SSTAT0) & TARGET) - role = ROLE_TARGET; - else - role = ROLE_INITIATOR; - - if (role == ROLE_TARGET - && (ahc->features & AHC_MULTI_TID) != 0 - && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { - /* We were selected, so pull our id from TARGIDIN */ - our_id = ahc_inb(ahc, TARGIDIN) & OID; - } else if ((ahc->features & AHC_ULTRA2) != 0) - our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; - else - our_id = ahc_inb(ahc, SCSIID) & OID; - - saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); - ahc_compile_devinfo(devinfo, - our_id, - SCSIID_TARGET(ahc, saved_scsiid), - ahc_inb(ahc, SAVED_LUN), - SCSIID_CHANNEL(ahc, saved_scsiid), - role); -} - -static void -ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, - u_int lun, char channel, role_t role) -{ - devinfo->our_scsiid = our_id; - devinfo->target = target; - devinfo->lun = lun; - devinfo->target_offset = target; - devinfo->channel = channel; - devinfo->role = role; - if (channel == 'B') - devinfo->target_offset += 8; - devinfo->target_mask = (0x01 << devinfo->target_offset); + for (i = 0; i < 16; i++) + ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); } -/* - * Catch an interrupt from the adapter - */ void -ahc_intr(void *arg) -{ - struct ahc_softc *ahc; - u_int intstat; - - ahc = (struct ahc_softc *)arg; - - intstat = ahc_inb(ahc, INTSTAT); - - /* - * Any interrupts to process? - */ -#if NPCI > 0 - if ((intstat & INT_PEND) == 0) { - if ((ahc->chip & AHC_PCI) != 0 - && (ahc->unsolicited_ints > 500)) { - if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) - ahc_pci_intr(ahc); - ahc->unsolicited_ints = 0; - } else { - ahc->unsolicited_ints++; - } - return; - } else { - ahc->unsolicited_ints = 0; - } -#else - if ((intstat & INT_PEND) == 0) - return; -#endif - - if (intstat & CMDCMPLT) { - ahc_outb(ahc, CLRINT, CLRCMDINT); - ahc_run_qoutfifo(ahc); - if ((ahc->flags & AHC_TARGETMODE) != 0) - ahc_run_tqinfifo(ahc, /*paused*/FALSE); - } - if (intstat & BRKADRINT) { - /* - * We upset the sequencer :-( - * Lookup the error message - */ - int i, error, num_errors; - - error = ahc_inb(ahc, ERROR); - num_errors = sizeof(hard_error)/sizeof(hard_error[0]); - for (i = 0; error != 1 && i < num_errors; i++) - error >>= 1; - panic("%s: brkadrint, %s at seqaddr = 0x%x\n", - ahc_name(ahc), hard_error[i].errmesg, - ahc_inb(ahc, SEQADDR0) | - (ahc_inb(ahc, SEQADDR1) << 8)); - - /* Tell everyone that this HBA is no longer availible */ - ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, - CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, - CAM_NO_HBA); - } - - if ((intstat & (SEQINT|SCSIINT)) != 0) - ahc_pause_bug_fix(ahc); - - if ((intstat & SEQINT) != 0) - ahc_handle_seqint(ahc, intstat); - - if ((intstat & SCSIINT) != 0) - ahc_handle_scsiint(ahc, intstat); -} - -static struct tmode_tstate * -ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) -{ - struct tmode_tstate *master_tstate; - struct tmode_tstate *tstate; - int i, s; - - master_tstate = ahc->enabled_targets[ahc->our_id]; - if (channel == 'B') { - scsi_id += 8; - master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; - } - if (ahc->enabled_targets[scsi_id] != NULL - && ahc->enabled_targets[scsi_id] != master_tstate) - panic("%s: ahc_alloc_tstate - Target already allocated", - ahc_name(ahc)); - tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); - if (tstate == NULL) - return (NULL); - - /* - * If we have allocated a master tstate, copy user settings from - * the master tstate (taken from SRAM or the EEPROM) for this - * channel, but reset our current and goal settings to async/narrow - * until an initiator talks to us. - */ - if (master_tstate != NULL) { - bcopy(master_tstate, tstate, sizeof(*tstate)); - bzero(tstate->enabled_luns, sizeof(tstate->enabled_luns)); - tstate->ultraenb = 0; - for (i = 0; i < 16; i++) { - bzero(&tstate->transinfo[i].current, - sizeof(tstate->transinfo[i].current)); - bzero(&tstate->transinfo[i].goal, - sizeof(tstate->transinfo[i].goal)); - } - } else - bzero(tstate, sizeof(*tstate)); - s = splcam(); - ahc->enabled_targets[scsi_id] = tstate; - splx(s); - return (tstate); -} - -static void -ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) -{ - struct tmode_tstate *tstate; - - /* Don't clean up the entry for our initiator role */ - if ((ahc->flags & AHC_INITIATORMODE) != 0 - && ((channel == 'B' && scsi_id == ahc->our_id_b) - || (channel == 'A' && scsi_id == ahc->our_id)) - && force == FALSE) - return; - - if (channel == 'B') - scsi_id += 8; - tstate = ahc->enabled_targets[scsi_id]; - if (tstate != NULL) - free(tstate, M_DEVBUF); - ahc->enabled_targets[scsi_id] = NULL; -} - -static void -ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) +ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) { - struct tmode_tstate *tstate; - struct tmode_lstate *lstate; - struct ccb_en_lun *cel; - cam_status status; - u_int target; - u_int lun; - u_int target_mask; - char channel; - int s; - - status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, - /* notfound_failure*/FALSE); + struct scb *scb; - if (status != CAM_REQ_CMP) { - ccb->ccb_h.status = status; + if (ahc->untagged_queue_lock != 0) return; - } - - cel = &ccb->cel; - target = ccb->ccb_h.target_id; - lun = ccb->ccb_h.target_lun; - channel = SIM_CHANNEL(ahc, sim); - target_mask = 0x01 << target; - if (channel == 'B') - target_mask <<= 8; - - if (cel->enable != 0) { - u_int scsiseq; - - /* Are we already enabled?? */ - if (lstate != NULL) { - xpt_print_path(ccb->ccb_h.path); - printf("Lun already enabled\n"); - ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; - return; - } - if (cel->grp6_len != 0 - || cel->grp7_len != 0) { - /* - * Don't (yet?) support vendor - * specific commands. - */ - ccb->ccb_h.status = CAM_REQ_INVALID; - printf("Non-zero Group Codes\n"); - return; - } - - /* - * Seems to be okay. - * Setup our data structures. - */ - if (target != CAM_TARGET_WILDCARD && tstate == NULL) { - tstate = ahc_alloc_tstate(ahc, target, channel); - if (tstate == NULL) { - xpt_print_path(ccb->ccb_h.path); - printf("Couldn't allocate tstate\n"); - ccb->ccb_h.status = CAM_RESRC_UNAVAIL; - return; - } - } - lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); - if (lstate == NULL) { - xpt_print_path(ccb->ccb_h.path); - printf("Couldn't allocate lstate\n"); - ccb->ccb_h.status = CAM_RESRC_UNAVAIL; - return; - } - bzero(lstate, sizeof(*lstate)); - status = xpt_create_path(&lstate->path, /*periph*/NULL, - xpt_path_path_id(ccb->ccb_h.path), - xpt_path_target_id(ccb->ccb_h.path), - xpt_path_lun_id(ccb->ccb_h.path)); - if (status != CAM_REQ_CMP) { - free(lstate, M_DEVBUF); - xpt_print_path(ccb->ccb_h.path); - printf("Couldn't allocate path\n"); - ccb->ccb_h.status = CAM_RESRC_UNAVAIL; - return; - } - SLIST_INIT(&lstate->accept_tios); - SLIST_INIT(&lstate->immed_notifies); - s = splcam(); - pause_sequencer(ahc); - if (target != CAM_TARGET_WILDCARD) { - tstate->enabled_luns[lun] = lstate; - ahc->enabled_luns++; - - if ((ahc->features & AHC_MULTI_TID) != 0) { - u_int targid_mask; - - targid_mask = ahc_inb(ahc, TARGID) - | (ahc_inb(ahc, TARGID + 1) << 8); - - targid_mask |= target_mask; - ahc_outb(ahc, TARGID, targid_mask); - ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); - - ahc_update_scsiid(ahc, targid_mask); - } else { - u_int our_id; - char channel; - - channel = SIM_CHANNEL(ahc, sim); - our_id = SIM_SCSI_ID(ahc, sim); - - /* - * This can only happen if selections - * are not enabled - */ - if (target != our_id) { - u_int sblkctl; - char cur_channel; - int swap; - - sblkctl = ahc_inb(ahc, SBLKCTL); - cur_channel = (sblkctl & SELBUSB) - ? 'B' : 'A'; - if ((ahc->features & AHC_TWIN) == 0) - cur_channel = 'A'; - swap = cur_channel != channel; - if (channel == 'A') - ahc->our_id = target; - else - ahc->our_id_b = target; - - if (swap) - ahc_outb(ahc, SBLKCTL, - sblkctl ^ SELBUSB); - - ahc_outb(ahc, SCSIID, target); - - if (swap) - ahc_outb(ahc, SBLKCTL, sblkctl); - } - } - } else - ahc->black_hole = lstate; - /* Allow select-in operations */ - if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { - scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); - scsiseq |= ENSELI; - ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); - scsiseq = ahc_inb(ahc, SCSISEQ); - scsiseq |= ENSELI; - ahc_outb(ahc, SCSISEQ, scsiseq); - } - unpause_sequencer(ahc); - splx(s); - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_print_path(ccb->ccb_h.path); - printf("Lun now enabled for target mode\n"); - } else { - struct ccb_hdr *elm; - int i, empty; - - if (lstate == NULL) { - ccb->ccb_h.status = CAM_LUN_INVALID; - return; - } - - s = splcam(); - ccb->ccb_h.status = CAM_REQ_CMP; - LIST_FOREACH(elm, &ahc->pending_ccbs, sim_links.le) { - if (elm->func_code == XPT_CONT_TARGET_IO - && !xpt_path_comp(elm->path, ccb->ccb_h.path)){ - printf("CTIO pending\n"); - ccb->ccb_h.status = CAM_REQ_INVALID; - splx(s); - return; - } - } - - if (SLIST_FIRST(&lstate->accept_tios) != NULL) { - printf("ATIOs pending\n"); - ccb->ccb_h.status = CAM_REQ_INVALID; - } - - if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { - printf("INOTs pending\n"); - ccb->ccb_h.status = CAM_REQ_INVALID; - } - - if (ccb->ccb_h.status != CAM_REQ_CMP) { - splx(s); - return; - } - - xpt_print_path(ccb->ccb_h.path); - printf("Target mode disabled\n"); - xpt_free_path(lstate->path); - free(lstate, M_DEVBUF); - - pause_sequencer(ahc); - /* Can we clean up the target too? */ - if (target != CAM_TARGET_WILDCARD) { - tstate->enabled_luns[lun] = NULL; - ahc->enabled_luns--; - for (empty = 1, i = 0; i < 8; i++) - if (tstate->enabled_luns[i] != NULL) { - empty = 0; - break; - } - - if (empty) { - ahc_free_tstate(ahc, target, channel, - /*force*/FALSE); - if (ahc->features & AHC_MULTI_TID) { - u_int targid_mask; - - targid_mask = ahc_inb(ahc, TARGID) - | (ahc_inb(ahc, TARGID + 1) - << 8); - - targid_mask &= ~target_mask; - ahc_outb(ahc, TARGID, targid_mask); - ahc_outb(ahc, TARGID+1, - (targid_mask >> 8)); - ahc_update_scsiid(ahc, targid_mask); - } - } - } else { - - ahc->black_hole = NULL; - - /* - * We can't allow selections without - * our black hole device. - */ - empty = TRUE; - } - if (ahc->enabled_luns == 0) { - /* Disallow select-in */ - u_int scsiseq; - - scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); - scsiseq &= ~ENSELI; - ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); - scsiseq = ahc_inb(ahc, SCSISEQ); - scsiseq &= ~ENSELI; - ahc_outb(ahc, SCSISEQ, scsiseq); - } - unpause_sequencer(ahc); - splx(s); - } -} - -static void -ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) -{ - u_int scsiid_mask; - u_int scsiid; - - if ((ahc->features & AHC_MULTI_TID) == 0) - panic("ahc_update_scsiid called on non-multitid unit\n"); - - /* - * Since we will rely on the the TARGID mask - * for selection enables, ensure that OID - * in SCSIID is not set to some other ID - * that we don't want to allow selections on. - */ - if ((ahc->features & AHC_ULTRA2) != 0) - scsiid = ahc_inb(ahc, SCSIID_ULTRA2); - else - scsiid = ahc_inb(ahc, SCSIID); - scsiid_mask = 0x1 << (scsiid & OID); - if ((targid_mask & scsiid_mask) == 0) { - u_int our_id; - - /* ffs counts from 1 */ - our_id = ffs(targid_mask); - if (our_id == 0) - our_id = ahc->our_id; - else - our_id--; - scsiid &= TID; - scsiid |= our_id; + if ((scb = TAILQ_FIRST(queue)) != NULL + && (scb->flags & SCB_ACTIVE) == 0) { + scb->flags |= SCB_ACTIVE; + ahc_queue_scb(ahc, scb); } - if ((ahc->features & AHC_ULTRA2) != 0) - ahc_outb(ahc, SCSIID_ULTRA2, scsiid); - else - ahc_outb(ahc, SCSIID, scsiid); } -static int -ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) +/************************* Interrupt Handling *********************************/ +void +ahc_handle_brkadrint(struct ahc_softc *ahc) { - struct tmode_tstate *tstate; - struct tmode_lstate *lstate; - struct ccb_accept_tio *atio; - uint8_t *byte; - int initiator; - int target; - int lun; - - initiator = SCSIID_TARGET(ahc, cmd->scsiid); - target = SCSIID_OUR_ID(cmd->scsiid); - lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); - - byte = cmd->bytes; - tstate = ahc->enabled_targets[target]; - lstate = NULL; - if (tstate != NULL) - lstate = tstate->enabled_luns[lun]; - /* - * Commands for disabled luns go to the black hole driver. + * We upset the sequencer :-( + * Lookup the error message */ - if (lstate == NULL) - lstate = ahc->black_hole; - - atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); - if (atio == NULL) { - ahc->flags |= AHC_TQINFIFO_BLOCKED; - /* - * Wait for more ATIOs from the peripheral driver for this lun. - */ - return (1); - } else - ahc->flags &= ~AHC_TQINFIFO_BLOCKED; -#if 0 - printf("Incoming command from %d for %d:%d%s\n", - initiator, target, lun, - lstate == ahc->black_hole ? "(Black Holed)" : ""); -#endif - SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); - - if (lstate == ahc->black_hole) { - /* Fill in the wildcards */ - atio->ccb_h.target_id = target; - atio->ccb_h.target_lun = lun; - } - - /* - * Package it up and send it off to - * whomever has this lun enabled. - */ - atio->sense_len = 0; - atio->init_id = initiator; - if (byte[0] != 0xFF) { - /* Tag was included */ - atio->tag_action = *byte++; - atio->tag_id = *byte++; - atio->ccb_h.flags = CAM_TAG_ACTION_VALID; - } else { - atio->ccb_h.flags = 0; - } - byte++; - - /* Okay. Now determine the cdb size based on the command code */ - switch (*byte >> CMD_GROUP_CODE_SHIFT) { - case 0: - atio->cdb_len = 6; - break; - case 1: - case 2: - atio->cdb_len = 10; - break; - case 4: - atio->cdb_len = 16; - break; - case 5: - atio->cdb_len = 12; - break; - case 3: - default: - /* Only copy the opcode. */ - atio->cdb_len = 1; - printf("Reserved or VU command code type encountered\n"); - break; - } - bcopy(byte, atio->cdb_io.cdb_bytes, atio->cdb_len); - - atio->ccb_h.status |= CAM_CDB_RECVD; - - if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { - /* - * We weren't allowed to disconnect. - * We're hanging on the bus until a - * continue target I/O comes in response - * to this accept tio. - */ -#if 0 - printf("Received Immediate Command %d:%d:%d - %p\n", - initiator, target, lun, ahc->pending_device); -#endif - ahc->pending_device = lstate; - ahc_freeze_ccb((union ccb *)atio); - atio->ccb_h.flags |= CAM_DIS_DISCONNECT; - } - xpt_done((union ccb*)atio); - return (0); + int i, error, num_errors; + + error = ahc_inb(ahc, ERROR); + num_errors = sizeof(hard_error)/sizeof(hard_error[0]); + for (i = 0; error != 1 && i < num_errors; i++) + error >>= 1; + panic("%s: brkadrint, %s at seqaddr = 0x%x\n", + ahc_name(ahc), hard_error[i].errmesg, + ahc_inb(ahc, SEQADDR0) | + (ahc_inb(ahc, SEQADDR1) << 8)); + + /* Tell everyone that this HBA is no longer availible */ + ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, + CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, + CAM_NO_HBA); } -static void +void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) { struct scb *scb; @@ -2440,7 +378,6 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) { u_int scb_index; struct hardware_scb *hscb; - struct ccb_scsiio *csio; /* * The sequencer will notify us when a command * has an error that would be of interest to @@ -2478,16 +415,15 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) * complete. */ scb->flags &= ~SCB_SENSE; - ahcsetccbstatus(scb->ccb, CAM_AUTOSENSE_FAIL); + ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); break; } - ahcsetccbstatus(scb->ccb, CAM_SCSI_STATUS_ERROR); + ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); /* Freeze the queue until the client sees the error. */ - ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); - ahc_freeze_ccb(scb->ccb); - csio = &scb->ccb->csio; - csio->scsi_status = hscb->shared_data.status.scsi_status; - switch (csio->scsi_status) { + ahc_freeze_devq(ahc, scb); + ahc_freeze_scb(scb); + ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); + switch (hscb->shared_data.status.scsi_status) { case SCSI_STATUS_OK: printf("%s: Interrupted for staus of 0???\n", ahc_name(ahc)); @@ -2496,12 +432,13 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) case SCSI_STATUS_CHECK_COND: #ifdef AHC_DEBUG if (ahc_debug & AHC_SHOWSENSE) { - xpt_print_path(csio->ccb_h.path); + ahc_print_path(ahc, scb); printf("SCB %d: requests Check Status\n", scb->hscb->tag); } #endif - if ((csio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { + + if (ahc_perform_autosense(scb)) { struct ahc_dma_seg *sg; struct scsi_sense *sc; struct ahc_initiator_tinfo *targ_info; @@ -2524,18 +461,16 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) if (ahc_check_residual(scb)) ahc_calc_residual(scb); else - scb->ccb->csio.resid = 0; - + ahc_set_residual(scb, 0); #ifdef AHC_DEBUG if (ahc_debug & AHC_SHOWSENSE) { - xpt_print_path(csio->ccb_h.path); + ahc_print_path(ahc, scb); printf("Sending Sense\n"); } #endif sg->addr = ahc->scb_data->sense_busaddr + (hscb->tag*sizeof(struct scsi_sense_data)); - sg->len = MIN(sizeof(struct scsi_sense_data), - csio->sense_len); + sg->len = ahc_get_sense_bufsize(ahc, scb); sg->len |= AHC_DMA_LAST_SEG; sc->opcode = REQUEST_SENSE; @@ -2563,8 +498,8 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) * errors will be reported before any data * phases occur. */ - if (scb->ccb->csio.resid - == scb->ccb->csio.dxfer_len) { + if (ahc_get_residual(scb) + == ahc_get_transfer_length(scb)) { ahc_update_target_msg_request(ahc, &devinfo, targ_info, @@ -2579,14 +514,16 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) scb->flags |= SCB_SENSE; ahc_outb(ahc, RETURN_1, SEND_SENSE); +#ifdef __FreeBSD__ /* * Ensure we have enough time to actually * retrieve the sense. */ untimeout(ahc_timeout, (caddr_t)scb, - scb->ccb->ccb_h.timeout_ch); - scb->ccb->ccb_h.timeout_ch = + scb->io_ctx->ccb_h.timeout_ch); + scb->io_ctx->ccb_h.timeout_ch = timeout(ahc_timeout, (caddr_t)scb, 5 * hz); +#endif } break; default: @@ -2724,14 +661,16 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; ahc->msgin_index = 0; - } else + } +#if AHC_TARGET_MODE + else /* XXX Ever executed??? */ ahc_setup_target_msgin(ahc, &devinfo); +#endif } } - /* Pass a NULL path so that handlers generate their own */ - ahc_handle_message_phase(ahc, /*path*/NULL); + ahc_handle_message_phase(ahc); break; } case PERR_DETECTED: @@ -2783,15 +722,15 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) if (lastphase == phase_table[i].phase) break; } - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); printf("data overrun detected %s." " Tag == 0x%x.\n", phase_table[i].phasemsg, scb->hscb->tag); - xpt_print_path(scb->ccb->ccb_h.path); - printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", + ahc_print_path(ahc, scb); + printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", - scb->ccb->csio.dxfer_len, scb->sg_count); + ahc_get_transfer_length(scb), scb->sg_count); if (scb->sg_count > 0) { for (i = 0; i < scb->sg_count; i++) { printf("sg[%d] - Addr 0x%x : Length %d\n", @@ -2804,105 +743,17 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) * Set this and it will take effect when the * target does a command complete. */ - ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); - ahcsetccbstatus(scb->ccb, CAM_DATA_RUN_ERR); - ahc_freeze_ccb(scb->ccb); + ahc_freeze_devq(ahc, scb); + ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); + ahc_freeze_scb(scb); break; } case TRACEPOINT: { - printf("SAVED_SCSIID %x, SAVED_LUN %x, SCBPTR %x\n", - ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), - ahc_inb(ahc, SCBPTR)); -#if 0 - printf("%s: SCB_DATAPTR = %x, SCB_DATACNT = %x\n", - ahc_name(ahc), - ahc_inb(ahc, SCB_DATAPTR) - | (ahc_inb(ahc, SCB_DATAPTR + 1) << 8) - | (ahc_inb(ahc, SCB_DATAPTR + 2) << 16) - | (ahc_inb(ahc, SCB_DATAPTR + 3) << 24), - ahc_inb(ahc, SCB_DATACNT) - | (ahc_inb(ahc, SCB_DATACNT + 1) << 8) - | (ahc_inb(ahc, SCB_DATACNT + 2) << 16) - | (ahc_inb(ahc, SCB_DATACNT + 3) << 24)); - printf("SCSIRATE = %x\n", ahc_inb(ahc, SCSIRATE)); - printf("SG_CACHEPTR = %x\n", ahc_inb(ahc, SINDEX)); - printf("DFCNTRL = %x, DFSTATUS = %x\n", - ahc_inb(ahc, DFCNTRL), - ahc_inb(ahc, DFSTATUS)); - if ((ahc->features & AHC_CMD_CHAN) != 0) { - printf("CCHADDR = 0x%x\n", - ahc_inb(ahc, CCHADDR) - | (ahc_inb(ahc, CCHADDR + 1) << 8) - | (ahc_inb(ahc, CCHADDR + 2) << 16) - | (ahc_inb(ahc, CCHADDR + 3) << 24)); - } else { - printf("HADDR = 0x%x\n", - ahc_inb(ahc, HADDR) - | (ahc_inb(ahc, HADDR + 1) << 8) - | (ahc_inb(ahc, HADDR + 2) << 16) - | (ahc_inb(ahc, HADDR + 3) << 24)); - } - -#endif break; } case TRACEPOINT2: { - printf("SINDEX = %x\n", ahc_inb(ahc, SINDEX)); - printf("SCSIRATE = %x\n", ahc_inb(ahc, SCSIRATE)); -#if 0 - printf("SCB_RESIDUAL_SGPTR = %x, SCB_RESIDUAL_DATACNT = %x\n", - ahc_inb(ahc, SCB_RESIDUAL_SGPTR) - | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) - | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) - | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24), - ahc_inb(ahc, SCB_RESIDUAL_DATACNT) - | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) - | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) - | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 3) << 24)); - printf("DATA_COUNT_ODD = %x\n", ahc_inb(ahc, DATA_COUNT_ODD)); - printf("SINDEX = %x\n", ahc_inb(ahc, SINDEX)); - printf("SCB_SGPTR %x, SCB_RESIDUAL_SGPTR %x\n", - ahc_inb(ahc, SCB_SGPTR), - ahc_inb(ahc, SCB_RESIDUAL_SGPTR)); - printf("SAVED_SCSIID %x, SAVED_LUN %d, " - "DISCONNECTED_SCBH %d\n", - ahc_inb(ahc, SAVED_SCSIID), - ahc_inb(ahc, SAVED_LUN), - ahc_inb(ahc, DISCONNECTED_SCBH)); - int i; - - if (ahc->unit != 1) - break; - for (i = 0; i < 32;) { - printf("0x%x 0x%x 0x%x 0x%x\n", - ahc_inb(ahc, SCB_CONTROL + i), - ahc_inb(ahc, SCB_CONTROL + i + 1), - ahc_inb(ahc, SCB_CONTROL + i + 2), - ahc_inb(ahc, SCB_CONTROL + i + 3)); - i += 4; - } -#endif -#if 0 - printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); - printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); - printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); - printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", - ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); - printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); - printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", - ahc_inb(ahc, CCHADDR) - | (ahc_inb(ahc, CCHADDR+1) << 8) - | (ahc_inb(ahc, CCHADDR+2) << 16) - | (ahc_inb(ahc, CCHADDR+3) << 24), - ahc_inb(ahc, CCHCNT) - | (ahc_inb(ahc, CCHCNT+1) << 8) - | (ahc_inb(ahc, CCHCNT+2) << 16), - ahc_inb(ahc, SCBPTR)); - printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); - printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); -#endif break; } default: @@ -2911,7 +762,6 @@ ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) intstat, ahc_inb(ahc, SCSISIGI)); break; } - unpause: /* * The sequencer is paused immediately on @@ -2921,7 +771,7 @@ unpause: unpause_sequencer(ahc); } -static void +void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) { u_int scb_index; @@ -2980,10 +830,13 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) u_int curphase; u_int errorphase; u_int lastphase; + u_int scsirate; u_int i; + u_int sstat2; lastphase = ahc_inb(ahc, LASTPHASE); curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; + sstat2 = ahc_inb(ahc, SSTAT2); ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); /* * For all phases save DATA, the sequencer won't @@ -2997,7 +850,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) * curphase and lastphase. */ if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 - || curphase == P_DATAIN) + || curphase == P_DATAIN || curphase == P_DATAIN_DT) errorphase = curphase; else errorphase = lastphase; @@ -3008,17 +861,30 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) } mesg_out = phase_table[i].mesg_out; if (scb != NULL) - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); else printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); - + scsirate = ahc_inb(ahc, SCSIRATE); printf("parity error detected %s. " "SEQADDR(0x%x) SCSIRATE(0x%x)\n", phase_table[i].phasemsg, ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), - ahc_inb(ahc, SCSIRATE)); + scsirate); + + if ((ahc->features & AHC_DT) != 0) { + + if ((sstat2 & CRCVALERR) != 0) + printf("\tCRC Value Mismatch\n"); + if ((sstat2 & CRCENDERR) != 0) + printf("\tNo terminal CRC packet recevied\n"); + if ((sstat2 & CRCREQERR) != 0) + printf("\tIllegal CRC packet request\n"); + if ((sstat2 & DUAL_EDGE_ERR) != 0) + printf("\tUnexpected %sDT Data Phase\n", + (scsirate & SINGLE_EDGE) ? "" : "non-"); + } /* * We've set the hardware to assert ATN if we @@ -3064,7 +930,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) tag = scb->hscb->tag; /* FALLTRHOUGH */ case MSG_ABORT: - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); printf("SCB %d - Abort %s Completed.\n", scb->hscb->tag, tag == SCB_LIST_NULL ? "" : "Tag"); @@ -3077,28 +943,29 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) case MSG_BUS_DEV_RESET: { struct ahc_devinfo devinfo; - +#ifdef __FreeBSD__ /* * Don't mark the user's request for this BDR * as completing with CAM_BDR_SENT. CAM3 * specifies CAM_REQ_CMP. */ if (scb != NULL - && scb->ccb->ccb_h.func_code == XPT_RESET_DEV + && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV && ahc_match_scb(ahc, scb, target, channel, - saved_lun, + CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_INITIATOR)) { - ahcsetccbstatus(scb->ccb, CAM_REQ_CMP); + ahc_set_transaction_status(scb, CAM_REQ_CMP); } +#endif ahc_compile_devinfo(&devinfo, initiator_role_id, target, - saved_lun, + CAM_LUN_WILDCARD, channel, ROLE_INITIATOR); ahc_handle_devreset(ahc, &devinfo, - CAM_BDR_SENT, AC_SENT_BDR, + CAM_BDR_SENT, "Bus Device Reset", /*verbose_level*/0); printerror = 0; @@ -3122,7 +989,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) SCB_GET_LUN(scb), tag, ROLE_INITIATOR, CAM_UNEXP_BUSFREE); - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); } else { /* * We had not fully identified this connection, @@ -3163,8 +1030,8 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) "valid during SELTO scb(%d, %d)\n", ahc_name(ahc), scbptr, scb_index); } else { - ahcsetccbstatus(scb->ccb, CAM_SEL_TIMEOUT); - ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); + ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); + ahc_freeze_devq(ahc, scb); } /* Stop the selection */ ahc_outb(ahc, SCSISEQ, 0); @@ -3187,7 +1054,7 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) ahc_outb(ahc, CLRINT, CLRSCSIINT); restart_sequencer(ahc); } else { - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); printf("Unknown SCSIINT. Status = 0x%x\n", status); ahc_outb(ahc, CLRSINT1, status); ahc_outb(ahc, CLRINT, CLRSCSIINT); @@ -3195,69 +1062,698 @@ ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) } } -static void -ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) + +/* + * Clear any pending interrupt status. + */ +void +ahc_clear_intstat(struct ahc_softc *ahc) +{ + /* Clear any interrupt conditions this may have caused */ + ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); + ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI + |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| + CLRREQINIT); + ahc_outb(ahc, CLRINT, CLRSCSIINT); +} + +/**************************** Debugging Routines ******************************/ +void +ahc_print_scb(struct scb *scb) +{ + int i; + + struct hardware_scb *hscb = scb->hscb; + + printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", + scb, + hscb->control, + hscb->scsiid, + hscb->lun, + hscb->cdb_len); + i = 0; + printf("Shared Data: %#02x %#02x %#02x %#02x\n", + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++]); + printf(" %#02x %#02x %#02x %#02x\n", + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++]); + printf(" %#02x %#02x %#02x %#02x\n", + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++], + hscb->shared_data.cdb[i++]); + printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", + hscb->dataptr, + hscb->datacnt, + hscb->sgptr, + hscb->tag); + if (scb->sg_count > 0) { + for (i = 0; i < scb->sg_count; i++) { + printf("sg[%d] - Addr 0x%x : Length %d\n", + i, + scb->sg_list[i].addr, + scb->sg_list[i].len); + } + } +} + +/************************* Transfer Negotiation *******************************/ +/* + * Allocate per target mode instance (ID we respond to as a target) + * transfer negotiation data structures. + */ +static struct tmode_tstate * +ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) { + struct tmode_tstate *master_tstate; + struct tmode_tstate *tstate; + int i; + + master_tstate = ahc->enabled_targets[ahc->our_id]; + if (channel == 'B') { + scsi_id += 8; + master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; + } + if (ahc->enabled_targets[scsi_id] != NULL + && ahc->enabled_targets[scsi_id] != master_tstate) + panic("%s: ahc_alloc_tstate - Target already allocated", + ahc_name(ahc)); + tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); + if (tstate == NULL) + return (NULL); + /* - * We need to initiate transfer negotiations. - * If our current and goal settings are identical, - * we want to renegotiate due to a check condition. + * If we have allocated a master tstate, copy user settings from + * the master tstate (taken from SRAM or the EEPROM) for this + * channel, but reset our current and goal settings to async/narrow + * until an initiator talks to us. */ + if (master_tstate != NULL) { + memcpy(tstate, master_tstate, sizeof(*tstate)); + memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); + tstate->ultraenb = 0; + for (i = 0; i < 16; i++) { + memset(&tstate->transinfo[i].current, 0, + sizeof(tstate->transinfo[i].current)); + memset(&tstate->transinfo[i].goal, 0, + sizeof(tstate->transinfo[i].goal)); + } + } else + memset(tstate, 0, sizeof(*tstate)); + ahc->enabled_targets[scsi_id] = tstate; + return (tstate); +} + +/* + * Free per target mode instance (ID we respond to as a target) + * transfer negotiation data structures. + */ +static void +ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) +{ + struct tmode_tstate *tstate; + + /* Don't clean up the entry for our initiator role */ + if ((ahc->flags & AHC_INITIATORMODE) != 0 + && ((channel == 'B' && scsi_id == ahc->our_id_b) + || (channel == 'A' && scsi_id == ahc->our_id)) + && force == FALSE) + return; + + if (channel == 'B') + scsi_id += 8; + tstate = ahc->enabled_targets[scsi_id]; + if (tstate != NULL) + free(tstate, M_DEVBUF); + ahc->enabled_targets[scsi_id] = NULL; +} + +/* + * Called when we have an active connection to a target on the bus, + * this function finds the nearest syncrate to the input period limited + * by the capabilities of the bus connectivity of the target. + */ +struct ahc_syncrate * +ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period, + u_int *ppr_options) { + u_int maxsync; + + if ((ahc->features & AHC_ULTRA2) != 0) { + if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 + && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { + maxsync = AHC_SYNCRATE_DT; + } else { + maxsync = AHC_SYNCRATE_ULTRA; + /* Can't do DT on an SE bus */ + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + } + } else if ((ahc->features & AHC_ULTRA) != 0) { + maxsync = AHC_SYNCRATE_ULTRA; + } else { + maxsync = AHC_SYNCRATE_FAST; + } + return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); +} + +/* + * Look up the valid period to SCSIRATE conversion in our table. + * Return the period and offset that should be sent to the target + * if this was the beginning of an SDTR. + */ +struct ahc_syncrate * +ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, + u_int *ppr_options, u_int maxsync) +{ + struct ahc_syncrate *syncrate; + + if ((ahc->features & AHC_DT) == 0) + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + + for (syncrate = &ahc_syncrates[maxsync]; + syncrate->rate != NULL; + syncrate++) { + + /* + * The Ultra2 table doesn't go as low + * as for the Fast/Ultra cards. + */ + if ((ahc->features & AHC_ULTRA2) != 0 + && (syncrate->sxfr_u2 == 0)) + break; + + /* Skip any DT entries if DT is not available */ + if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 + && (syncrate->sxfr_u2 & DT_SXFR) != 0) + continue; + + if (*period <= syncrate->period) { + /* + * When responding to a target that requests + * sync, the requested rate may fall between + * two rates that we can output, but still be + * a rate that we can receive. Because of this, + * we want to respond to the target with + * the same rate that it sent to us even + * if the period we use to send data to it + * is lower. Only lower the response period + * if we must. + */ + if (syncrate == &ahc_syncrates[maxsync]) + *period = syncrate->period; + + /* + * At some speeds, we only support + * ST transfers. + */ + if ((syncrate->sxfr_u2 & ST_SXFR) != 0) + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + break; + } + } + + if ((*period == 0) + || (syncrate->rate == NULL) + || ((ahc->features & AHC_ULTRA2) != 0 + && (syncrate->sxfr_u2 == 0))) { + /* Use asynchronous transfers. */ + *period = 0; + syncrate = NULL; + *ppr_options &= ~MSG_EXT_PPR_DT_REQ; + } + return (syncrate); +} + +/* + * Convert from an entry in our syncrate table to the SCSI equivalent + * sync "period" factor. + */ +u_int +ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) +{ + struct ahc_syncrate *syncrate; + + if ((ahc->features & AHC_ULTRA2) != 0) + scsirate &= SXFR_ULTRA2; + else + scsirate &= SXFR; + + syncrate = &ahc_syncrates[maxsync]; + while (syncrate->rate != NULL) { + + if ((ahc->features & AHC_ULTRA2) != 0) { + if (syncrate->sxfr_u2 == 0) + break; + else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) + return (syncrate->period); + } else if (scsirate == (syncrate->sxfr & SXFR)) { + return (syncrate->period); + } + syncrate++; + } + return (0); /* async */ +} + +/* + * Truncate the given synchronous offset to a value the + * current adapter type and syncrate are capable of. + */ +void +ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, + u_int *offset, int wide) +{ + u_int maxoffset; + + /* Limit offset to what we can do */ + if (syncrate == NULL) { + maxoffset = 0; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + maxoffset = MAX_OFFSET_ULTRA2; + } else { + if (wide) + maxoffset = MAX_OFFSET_16BIT; + else + maxoffset = MAX_OFFSET_8BIT; + } + *offset = MIN(*offset, maxoffset); +} + +/* + * Truncate the given transfer width parameter to a value the + * current adapter type is capable of. + */ +void +ahc_validate_width(struct ahc_softc *ahc, u_int *bus_width) +{ + switch (*bus_width) { + default: + if (ahc->features & AHC_WIDE) { + /* Respond Wide */ + *bus_width = MSG_EXT_WDTR_BUS_16_BIT; + break; + } + /* FALLTHROUGH */ + case MSG_EXT_WDTR_BUS_8_BIT: + bus_width = MSG_EXT_WDTR_BUS_8_BIT; + break; + } +} + +/* + * Update the bitmask of targets for which the controller should + * negotiate with at the next convenient oportunity. This currently + * means the next time we send the initial identify messages for + * a new transaction. + */ +static void +ahc_update_target_msg_request(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct ahc_initiator_tinfo *tinfo, + int force, int paused) +{ + u_int targ_msg_req_orig; + + targ_msg_req_orig = ahc->targ_msg_req; + if (tinfo->current.period != tinfo->goal.period + || tinfo->current.width != tinfo->goal.width + || tinfo->current.offset != tinfo->goal.offset + || (force + && (tinfo->goal.period != 0 + || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) + ahc->targ_msg_req |= devinfo->target_mask; + else + ahc->targ_msg_req &= ~devinfo->target_mask; + + if (ahc->targ_msg_req != targ_msg_req_orig) { + /* Update the message request bit for this target */ + if (!paused) + pause_sequencer(ahc); + + ahc_outb(ahc, TARGET_MSG_REQUEST, + ahc->targ_msg_req & 0xFF); + ahc_outb(ahc, TARGET_MSG_REQUEST + 1, + (ahc->targ_msg_req >> 8) & 0xFF); + + if (!paused) + unpause_sequencer(ahc); + } +} + +/* + * Update the user/goal/current tables of synchronous negotiation + * parameters as well as, in the case of a current or active update, + * any data structures on the host controller. In the case of an + * active update, the specified target is currently talking to us on + * the bus, so the transfer parameter update must take effect + * immediately. + */ +void +ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct ahc_syncrate *syncrate, u_int period, + u_int offset, u_int ppr_options, u_int type, int paused) +{ struct ahc_initiator_tinfo *tinfo; struct tmode_tstate *tstate; - struct ahc_syncrate *rate; - int dowide; - int dosync; - int doppr; - int use_ppr; - u_int period; - u_int ppr_options; - u_int offset; + u_int old_period; + u_int old_offset; + int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; + + if (syncrate == NULL) { + period = 0; + offset = 0; + } tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, devinfo->target, &tstate); - dowide = tinfo->current.width != tinfo->goal.width; - dosync = tinfo->current.period != tinfo->goal.period; - doppr = tinfo->current.ppr_options != tinfo->goal.ppr_options; + old_period = tinfo->current.period; + old_offset = tinfo->current.offset; - if (!dowide && !dosync && !doppr) { - dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; - dosync = tinfo->goal.period != 0; - doppr = tinfo->goal.ppr_options != 0; + if ((type & AHC_TRANS_CUR) != 0 + && (old_period != period || old_offset != offset)) { + u_int scsirate; + + scsirate = tinfo->scsirate; + if ((ahc->features & AHC_ULTRA2) != 0) { + + scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); + if (syncrate != NULL) { + scsirate |= syncrate->sxfr_u2; + if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) + scsirate |= ENABLE_CRC; + else + scsirate |= SINGLE_EDGE; + } + } else { + + scsirate &= ~(SXFR|SOFS); + /* + * Ensure Ultra mode is set properly for + * this target. + */ + tstate->ultraenb &= ~devinfo->target_mask; + if (syncrate != NULL) { + if (syncrate->sxfr & ULTRA_SXFR) { + tstate->ultraenb |= + devinfo->target_mask; + } + scsirate |= syncrate->sxfr & SXFR; + scsirate |= offset & SOFS; + } + if (active) { + u_int sxfrctl0; + + sxfrctl0 = ahc_inb(ahc, SXFRCTL0); + sxfrctl0 &= ~FAST20; + if (tstate->ultraenb & devinfo->target_mask) + sxfrctl0 |= FAST20; + ahc_outb(ahc, SXFRCTL0, sxfrctl0); + } + } + if (active) { + ahc_outb(ahc, SCSIRATE, scsirate); + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SCSIOFFSET, offset); + } + + tinfo->scsirate = scsirate; + tinfo->current.period = period; + tinfo->current.offset = offset; + tinfo->current.ppr_options = ppr_options; + + /* Update the syncrates in any pending scbs */ + ahc_update_pending_syncrates(ahc); + + ahc_send_async(ahc, devinfo, AC_TRANSFER_NEG); + if (bootverbose) { + if (offset != 0) { + printf("%s: target %d synchronous at %sMHz%s, " + "offset = 0x%x\n", ahc_name(ahc), + devinfo->target, syncrate->rate, + (ppr_options & MSG_EXT_PPR_DT_REQ) + ? " DT" : "", offset); + } else { + printf("%s: target %d using " + "asynchronous transfers\n", + ahc_name(ahc), devinfo->target); + } + } } - if (!dowide && !dosync && !doppr) { - panic("ahc_intr: AWAITING_MSG for negotiation, " - "but no negotiation needed\n"); + if ((type & AHC_TRANS_GOAL) != 0) { + tinfo->goal.period = period; + tinfo->goal.offset = offset; + tinfo->goal.ppr_options = ppr_options; } - use_ppr = (tinfo->current.transport_version >= 3) || doppr; - if (use_ppr) { - ahc_construct_ppr(ahc, tinfo->goal.period, tinfo->goal.offset, - tinfo->goal.width, tinfo->goal.ppr_options); - } else if (dowide) { - ahc_construct_wdtr(ahc, tinfo->goal.width); - } else if (dosync) { + if ((type & AHC_TRANS_USER) != 0) { + tinfo->user.period = period; + tinfo->user.offset = offset; + tinfo->user.ppr_options = ppr_options; + } - period = tinfo->goal.period; - ppr_options = 0; - rate = ahc_devlimited_syncrate(ahc, &period, &ppr_options); - offset = tinfo->goal.offset; - ahc_validate_offset(ahc, rate, &offset, - tinfo->current.width); - ahc_construct_sdtr(ahc, period, offset); + ahc_update_target_msg_request(ahc, devinfo, tinfo, + /*force*/FALSE, + paused); +} + +/* + * Update the user/goal/current tables of wide negotiation + * parameters as well as, in the case of a current or active update, + * any data structures on the host controller. In the case of an + * active update, the specified target is currently talking to us on + * the bus, so the transfer parameter update must take effect + * immediately. + */ +void +ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + u_int width, u_int type, int paused) +{ + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + u_int oldwidth; + int active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; + + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, + devinfo->target, &tstate); + oldwidth = tinfo->current.width; + + if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { + u_int scsirate; + + scsirate = tinfo->scsirate; + scsirate &= ~WIDEXFER; + if (width == MSG_EXT_WDTR_BUS_16_BIT) + scsirate |= WIDEXFER; + + tinfo->scsirate = scsirate; + + if (active) + ahc_outb(ahc, SCSIRATE, scsirate); + + tinfo->current.width = width; + + ahc_send_async(ahc, devinfo, AC_TRANSFER_NEG); + if (bootverbose) { + printf("%s: target %d using %dbit transfers\n", + ahc_name(ahc), devinfo->target, + 8 * (0x01 << width)); + } + } + if ((type & AHC_TRANS_GOAL) != 0) + tinfo->goal.width = width; + if ((type & AHC_TRANS_USER) != 0) + tinfo->user.width = width; + + ahc_update_target_msg_request(ahc, devinfo, tinfo, + /*force*/FALSE, paused); +} + +/* + * Update the current state of tagged queuing for a given target. + */ +void +ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) +{ + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t orig_tagenable; + + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, + devinfo->target, &tstate); + + orig_tagenable = tstate->tagenable; + if (enable) + tstate->tagenable |= devinfo->target_mask; + else + tstate->tagenable &= ~devinfo->target_mask; + + if (orig_tagenable != tstate->tagenable) { + ahc_platform_set_tags(ahc, devinfo, enable); + ahc_send_async(ahc, devinfo, AC_TRANSFER_NEG); } + } +/* + * When the transfer settings for a connection change, update any + * in-transit SCBs to contain the new data so the hardware will + * be set correctly during future (re)selections. + */ +static void +ahc_update_pending_syncrates(struct ahc_softc *ahc) +{ + struct scb *pending_scb; + int pending_scb_count; + int i; + u_int saved_scbptr; + + /* + * Traverse the pending SCB list and ensure that all of the + * SCBs there have the proper settings. + */ + pending_scb = LIST_FIRST(&ahc->pending_scbs); + pending_scb_count = 0; + while (pending_scb != NULL) { + struct ahc_devinfo devinfo; + struct hardware_scb *pending_hscb; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + + ahc_scb_devinfo(ahc, &devinfo, pending_scb); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + pending_hscb = pending_scb->hscb; + pending_hscb->control &= ~ULTRAENB; + if ((tstate->ultraenb & devinfo.target_mask) != 0) + pending_hscb->control |= ULTRAENB; + pending_hscb->scsirate = tinfo->scsirate; + pending_hscb->scsioffset = tinfo->current.offset; + pending_scb_count++; + pending_scb = LIST_NEXT(pending_scb, pending_links); + } + + if (pending_scb_count == 0) + return; + + saved_scbptr = ahc_inb(ahc, SCBPTR); + /* Ensure that the hscbs down on the card match the new information */ + for (i = 0; i < ahc->scb_data->maxhscbs; i++) { + u_int scb_tag; + + ahc_outb(ahc, SCBPTR, i); + scb_tag = ahc_inb(ahc, SCB_TAG); + if (scb_tag != SCB_LIST_NULL) { + struct ahc_devinfo devinfo; + struct scb *pending_scb; + struct hardware_scb *pending_hscb; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + u_int control; + + pending_scb = &ahc->scb_data->scbarray[scb_tag]; + if (pending_scb->flags == SCB_FREE) + continue; + pending_hscb = pending_scb->hscb; + ahc_scb_devinfo(ahc, &devinfo, pending_scb); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + control = ahc_inb(ahc, SCB_CONTROL); + control &= ~ULTRAENB; + if ((tstate->ultraenb & devinfo.target_mask) != 0) + control |= ULTRAENB; + ahc_outb(ahc, SCB_CONTROL, control); + ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); + ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); + } + } + ahc_outb(ahc, SCBPTR, saved_scbptr); +} + +/**************************** Pathing Information *****************************/ +static void +ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) +{ + u_int saved_scsiid; + role_t role; + int our_id; + + if (ahc_inb(ahc, SSTAT0) & TARGET) + role = ROLE_TARGET; + else + role = ROLE_INITIATOR; + + if (role == ROLE_TARGET + && (ahc->features & AHC_MULTI_TID) != 0 + && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { + /* We were selected, so pull our id from TARGIDIN */ + our_id = ahc_inb(ahc, TARGIDIN) & OID; + } else if ((ahc->features & AHC_ULTRA2) != 0) + our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; + else + our_id = ahc_inb(ahc, SCSIID) & OID; + + saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); + ahc_compile_devinfo(devinfo, + our_id, + SCSIID_TARGET(ahc, saved_scsiid), + ahc_inb(ahc, SAVED_LUN), + SCSIID_CHANNEL(ahc, saved_scsiid), + role); +} + +void +ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, + u_int lun, char channel, role_t role) +{ + devinfo->our_scsiid = our_id; + devinfo->target = target; + devinfo->lun = lun; + devinfo->target_offset = target; + devinfo->channel = channel; + devinfo->role = role; + if (channel == 'B') + devinfo->target_offset += 8; + devinfo->target_mask = (0x01 << devinfo->target_offset); +} + +static void +ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct scb *scb) +{ + role_t role; + int our_id; + + our_id = SCSIID_OUR_ID(scb->hscb->scsiid); + role = ROLE_INITIATOR; + if ((scb->hscb->control & TARGET_SCB) != 0) + role = ROLE_TARGET; + ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), + SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); +} + + +/************************ Message Phase Processing ****************************/ +/* + * When an initiator transaction with the MK_MESSAGE flag either reconnects + * or enters the initial message out phase, we are interrupted. Fill our + * outgoing message buffer with the appropriate message and beging handing + * the message phase(s) manually. + */ static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, struct scb *scb) { - /* + /* * To facilitate adding multiple messages together, * each routine should increment the index and len * variables instead of setting them explicitly. - */ + */ ahc->msgout_index = 0; ahc->msgout_len = 0; @@ -3273,7 +1769,7 @@ ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, if ((scb->hscb->control & TAG_ENB) != 0) { ahc->msgout_buf[ahc->msgout_index++] = - scb->ccb->csio.tag_action; + scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; ahc->msgout_len += 2; } @@ -3282,7 +1778,7 @@ ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, if (scb->flags & SCB_DEVICE_RESET) { ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; ahc->msgout_len++; - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); printf("Bus Device Reset Message Sent\n"); } else if ((scb->flags & SCB_ABORT) != 0) { if ((scb->hscb->control & TAG_ENB) != 0) @@ -3290,7 +1786,7 @@ ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, else ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; ahc->msgout_len++; - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); printf("Abort Message Sent\n"); } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0 || (scb->flags & SCB_NEGOTIATE) != 0) { @@ -3313,139 +1809,115 @@ ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, ahc->msgout_index = 0; ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; } - +/* + * Build an appropriate transfer negotiation message for the + * currently active target. + */ static void -ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) -{ - /* - * To facilitate adding multiple messages together, - * each routine should increment the index and len - * variables instead of setting them explicitly. - */ - ahc->msgout_index = 0; - ahc->msgout_len = 0; - - if ((ahc->targ_msg_req & devinfo->target_mask) != 0) - ahc_build_transfer_msg(ahc, devinfo); - else - panic("ahc_intr: AWAITING target message with no message"); - - ahc->msgout_index = 0; - ahc->msg_type = MSG_TYPE_TARGET_MSGIN; -} - -static int -ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) +ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) { /* - * What we care about here is if we had an - * outstanding SDTR or WDTR message for this - * target. If we did, this is a signal that - * the target is refusing negotiation. + * We need to initiate transfer negotiations. + * If our current and goal settings are identical, + * we want to renegotiate due to a check condition. */ - struct scb *scb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int scb_index; - u_int last_msg; - int response = 0; - - scb_index = ahc_inb(ahc, SCB_TAG); - scb = &ahc->scb_data->scbarray[scb_index]; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + struct ahc_syncrate *rate; + int dowide; + int dosync; + int doppr; + int use_ppr; + u_int period; + u_int ppr_options; + u_int offset; - tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, - devinfo->our_scsiid, + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, devinfo->target, &tstate); - /* Might be necessary */ - last_msg = ahc_inb(ahc, LAST_MSG); + dowide = tinfo->current.width != tinfo->goal.width; + dosync = tinfo->current.period != tinfo->goal.period; + doppr = tinfo->current.ppr_options != tinfo->goal.ppr_options; - if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { + if (!dowide && !dosync && !doppr) { + dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; + dosync = tinfo->goal.period != 0; + doppr = tinfo->goal.ppr_options != 0; + } - /* note 8bit xfers */ - printf("%s:%c:%d: refuses WIDE negotiation. Using " - "8bit transfers\n", ahc_name(ahc), - devinfo->channel, devinfo->target); - ahc_set_width(ahc, devinfo, scb->ccb->ccb_h.path, - MSG_EXT_WDTR_BUS_8_BIT, - AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE); - /* - * No need to clear the sync rate. If the target - * did not accept the command, our syncrate is - * unaffected. If the target started the negotiation, - * but rejected our response, we already cleared the - * sync rate before sending our WDTR. - */ - if (tinfo->goal.period) { - u_int period; - u_int ppr_options; + if (!dowide && !dosync && !doppr) { + panic("ahc_intr: AWAITING_MSG for negotiation, " + "but no negotiation needed\n"); + } - /* Start the sync negotiation */ - period = tinfo->goal.period; - ppr_options = 0; - ahc_devlimited_syncrate(ahc, &period, &ppr_options); - ahc->msgout_index = 0; - ahc->msgout_len = 0; - ahc_construct_sdtr(ahc, period, tinfo->goal.offset); - ahc->msgout_index = 0; - response = 1; - } - } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { - /* note asynch xfers and clear flag */ - ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, - /*syncrate*/NULL, /*period*/0, - /*offset*/0, /*ppr_options*/0, - AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE); - printf("%s:%c:%d: refuses synchronous negotiation. " - "Using asynchronous transfers\n", - ahc_name(ahc), - devinfo->channel, devinfo->target); - } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { - struct ccb_trans_settings neg; + use_ppr = (tinfo->current.transport_version >= 3) || doppr; + if (use_ppr) { + ahc_construct_ppr(ahc, tinfo->goal.period, tinfo->goal.offset, + tinfo->goal.width, tinfo->goal.ppr_options); + } else if (dowide) { + ahc_construct_wdtr(ahc, tinfo->goal.width); + } else if (dosync) { - printf("%s:%c:%d: refuses tagged commands. Performing " - "non-tagged I/O\n", ahc_name(ahc), - devinfo->channel, devinfo->target); - - ahc_set_tags(ahc, devinfo, FALSE); - neg.flags = CCB_TRANS_CURRENT_SETTINGS; - neg.valid = CCB_TRANS_TQ_VALID; - xpt_setup_ccb(&neg.ccb_h, scb->ccb->ccb_h.path, /*priority*/1); - xpt_async(AC_TRANSFER_NEG, scb->ccb->ccb_h.path, &neg); + period = tinfo->goal.period; + ppr_options = 0; + rate = ahc_devlimited_syncrate(ahc, &period, &ppr_options); + offset = tinfo->goal.offset; + ahc_validate_offset(ahc, rate, &offset, + tinfo->current.width); + ahc_construct_sdtr(ahc, period, offset); + } +} - /* - * Resend the identify for this CCB as the target - * may believe that the selection is invalid otherwise. - */ - ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) - & ~MSG_SIMPLE_Q_TAG); - scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; - scb->ccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; - ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); - ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); +/* + * Build an synchronous negotiateion message in our message + * buffer based on the input parameters. + */ +static void +ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) +{ + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; + ahc->msgout_buf[ahc->msgout_index++] = period; + ahc->msgout_buf[ahc->msgout_index++] = offset; + ahc->msgout_len += 5; +} - /* - * Requeue all tagged commands for this target - * currently in our posession so they can be - * converted to untagged commands. - */ - ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), - SCB_GET_CHANNEL(ahc, scb), - SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, - ROLE_INITIATOR, CAM_REQUEUE_REQ, - SEARCH_COMPLETE); - } else { - /* - * Otherwise, we ignore it. - */ - printf("%s:%c:%d: Message reject for %x -- ignored\n", - ahc_name(ahc), devinfo->channel, devinfo->target, - last_msg); - } - return (response); +/* + * Build a wide negotiateion message in our message + * buffer based on the input parameters. + */ +static void +ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) +{ + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; + ahc->msgout_buf[ahc->msgout_index++] = bus_width; + ahc->msgout_len += 4; } +/* + * Build a parallel protocol request message in our message + * buffer based on the input parameters. + */ +static void +ahc_construct_ppr(struct ahc_softc *ahc, u_int period, u_int offset, + u_int bus_width, u_int ppr_options) +{ + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; + ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; + ahc->msgout_buf[ahc->msgout_index++] = period; + ahc->msgout_buf[ahc->msgout_index++] = 0; + ahc->msgout_buf[ahc->msgout_index++] = offset; + ahc->msgout_buf[ahc->msgout_index++] = bus_width; + ahc->msgout_buf[ahc->msgout_index++] = ppr_options; + ahc->msgout_len += 8; +} + +/* + * Clear any active message state. + */ static void ahc_clear_msg_state(struct ahc_softc *ahc) { @@ -3455,8 +1927,11 @@ ahc_clear_msg_state(struct ahc_softc *ahc) ahc_outb(ahc, MSG_OUT, MSG_NOOP); } +/* + * Manual message loop handler. + */ static void -ahc_handle_message_phase(struct ahc_softc *ahc, struct cam_path *path) +ahc_handle_message_phase(struct ahc_softc *ahc) { struct ahc_devinfo devinfo; u_int bus_phase; @@ -3551,7 +2026,7 @@ reswitch: /* Pull the byte in without acking it */ ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); - message_done = ahc_parse_msg(ahc, path, &devinfo); + message_done = ahc_parse_msg(ahc, &devinfo); if (message_done) { /* @@ -3647,7 +2122,7 @@ reswitch: */ ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); - msgdone = ahc_parse_msg(ahc, path, &devinfo); + msgdone = ahc_parse_msg(ahc, &devinfo); if (msgdone == MSGLOOP_TERMINATED) { /* * The message is *really* done in that it caused @@ -3704,9 +2179,9 @@ reswitch: /* * See if we sent a particular extended message to the target. - * If "full" is true, the target saw the full message. - * If "full" is false, the target saw at least the first - * byte of the message. + * If "full" is true, return true only if the target saw the full + * message. If "full" is false, return true if the target saw at + * least the first byte of the message. */ static int ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) @@ -3746,9 +2221,11 @@ ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) return (found); } +/* + * Wait for a complete incomming message, parse it, and respond accordingly. + */ static int -ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, - struct ahc_devinfo *devinfo) +ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) { struct ahc_initiator_tinfo *tinfo; struct tmode_tstate *tstate; @@ -3818,7 +2295,7 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, &ppr_options); ahc_validate_offset(ahc, syncrate, &offset, targ_scsirate & WIDEXFER); - ahc_set_syncrate(ahc, devinfo, path, + ahc_set_syncrate(ahc, devinfo, syncrate, period, offset, ppr_options, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, @@ -3904,12 +2381,11 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, response = TRUE; sending_reply = TRUE; } - ahc_set_width(ahc, devinfo, path, bus_width, + ahc_set_width(ahc, devinfo, bus_width, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, /*paused*/TRUE); - /* After a wide message, we are async */ - ahc_set_syncrate(ahc, devinfo, path, + ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, /*offset*/0, /*ppr_options*/0, AHC_TRANS_ACTIVE, /*paused*/TRUE); @@ -4011,14 +2487,14 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, printf("Target Initated PPR detected!\n"); response = TRUE; } - ahc_set_syncrate(ahc, devinfo, path, + ahc_set_width(ahc, devinfo, bus_width, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + ahc_set_syncrate(ahc, devinfo, syncrate, period, offset, ppr_options, AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, /*paused*/TRUE); - ahc_set_width(ahc, devinfo, path, bus_width, - AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, - /*paused*/TRUE); break; } default: @@ -4030,7 +2506,7 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, } case MSG_BUS_DEV_RESET: ahc_handle_devreset(ahc, devinfo, - CAM_BDR_SENT, AC_SENT_BDR, + CAM_BDR_SENT, "Bus Device Reset Received", /*verbose_level*/0); restart_sequencer(ahc); @@ -4039,6 +2515,7 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, case MSG_ABORT_TAG: case MSG_ABORT: case MSG_CLEAR_QUEUE: +#ifdef AHC_TARGET_MODE /* Target mode messages */ if (devinfo->role != ROLE_TARGET) { reject = TRUE; @@ -4066,6 +2543,7 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, } done = MSGLOOP_MSGCOMPLETE; break; +#endif case MSG_TERM_IO_PROC: default: reject = TRUE; @@ -4090,6 +2568,130 @@ ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, return (done); } +/* + * Process a message reject message. + */ +static int +ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) +{ + /* + * What we care about here is if we had an + * outstanding SDTR or WDTR message for this + * target. If we did, this is a signal that + * the target is refusing negotiation. + */ + struct scb *scb; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + u_int scb_index; + u_int last_msg; + int response = 0; + + scb_index = ahc_inb(ahc, SCB_TAG); + scb = &ahc->scb_data->scbarray[scb_index]; + + tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, + devinfo->our_scsiid, + devinfo->target, &tstate); + /* Might be necessary */ + last_msg = ahc_inb(ahc, LAST_MSG); + + if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { + + /* note 8bit xfers */ + printf("%s:%c:%d: refuses WIDE negotiation. Using " + "8bit transfers\n", ahc_name(ahc), + devinfo->channel, devinfo->target); + ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + /* + * No need to clear the sync rate. If the target + * did not accept the command, our syncrate is + * unaffected. If the target started the negotiation, + * but rejected our response, we already cleared the + * sync rate before sending our WDTR. + */ + if (tinfo->goal.period) { + u_int period; + u_int ppr_options; + + /* Start the sync negotiation */ + period = tinfo->goal.period; + ppr_options = 0; + ahc_devlimited_syncrate(ahc, &period, &ppr_options); + ahc->msgout_index = 0; + ahc->msgout_len = 0; + ahc_construct_sdtr(ahc, period, tinfo->goal.offset); + ahc->msgout_index = 0; + response = 1; + } + } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { + /* note asynch xfers and clear flag */ + ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, + /*offset*/0, /*ppr_options*/0, + AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, + /*paused*/TRUE); + printf("%s:%c:%d: refuses synchronous negotiation. " + "Using asynchronous transfers\n", + ahc_name(ahc), + devinfo->channel, devinfo->target); + } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { + + printf("%s:%c:%d: refuses tagged commands. Performing " + "non-tagged I/O\n", ahc_name(ahc), + devinfo->channel, devinfo->target); + ahc_set_tags(ahc, devinfo, FALSE); + + /* + * Resend the identify for this CCB as the target + * may believe that the selection is invalid otherwise. + */ + ahc_outb(ahc, SCB_CONTROL, + ahc_inb(ahc, SCB_CONTROL) & ~MSG_SIMPLE_Q_TAG); + scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; + ahc_set_transaction_tag(scb, /*enabled*/FALSE, + /*type*/MSG_SIMPLE_Q_TAG); + ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); + ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); + + /* + * This transaction is now at the head of + * the untagged queue for this target. + */ + if ((ahc->features & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + + untagged_q = &(ahc->untagged_queues[devinfo->target]); + TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); + } + ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), + scb->hscb->tag); + + /* + * Requeue all tagged commands for this target + * currently in our posession so they can be + * converted to untagged commands. + */ + ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), + SCB_GET_CHANNEL(ahc, scb), + SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, + ROLE_INITIATOR, CAM_REQUEUE_REQ, + SEARCH_COMPLETE); + } else { + /* + * Otherwise, we ignore it. + */ + printf("%s:%c:%d: Message reject for %x -- ignored\n", + ahc_name(ahc), devinfo->channel, devinfo->target, + last_msg); + } + return (response); +} + +/* + * Process an ingnore wide residue message. + */ static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) { @@ -4098,8 +2700,12 @@ ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) scb_index = ahc_inb(ahc, SCB_TAG); scb = &ahc->scb_data->scbarray[scb_index]; + /* + * XXX Actually check data direction in the sequencer? + * Perhaps add datadir to some spare bits in the hscb? + */ if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 - || (scb->ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_IN) { + || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { /* * Ignore the message if we haven't * seen an appropriate data phase yet. @@ -4199,25 +2805,26 @@ ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) } } +/* + * Handle the effects of issuing a bus device reset message. + */ static void ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, - cam_status status, ac_code acode, char *message, - int verbose_level) + cam_status status, char *message, int verbose_level) { - struct cam_path *path; - int found; - int error; +#ifdef AHC_TARGET_MODE struct tmode_tstate* tstate; u_int lun; - - error = ahc_create_path(ahc, devinfo, &path); +#endif + int found; found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, status); +#ifdef AHC_TARGET_MODE /* - * Send an immediate notify ccb to all target more peripheral + * Send an immediate notify ccb to all target mord peripheral * drivers affected by this action. */ tstate = ahc->enabled_targets[devinfo->our_scsiid]; @@ -4234,23 +2841,18 @@ ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, ahc_send_lstate_events(ahc, lstate); } } +#endif /* * Go back to async/narrow transfers and renegotiate. - * ahc_set_width and ahc_set_syncrate can cope with NULL - * paths. */ - ahc_set_width(ahc, devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, + ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, AHC_TRANS_CUR, /*paused*/TRUE); - ahc_set_syncrate(ahc, devinfo, path, /*syncrate*/NULL, + ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, /*offset*/0, /*ppr_options*/0, AHC_TRANS_CUR, /*paused*/TRUE); - if (error == CAM_REQ_CMP && acode != 0) - xpt_async(AC_SENT_BDR, path, NULL); - - if (error == CAM_REQ_CMP) - xpt_free_path(path); + ahc_send_async(ahc, devinfo, AC_SENT_BDR); if (message != NULL && (verbose_level <= bootverbose)) @@ -4258,119 +2860,297 @@ ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, message, devinfo->channel, devinfo->target, found); } +#ifdef AHC_TARGET_MODE +void +ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) +{ + /* + * To facilitate adding multiple messages together, + * each routine should increment the index and len + * variables instead of setting them explicitly. + */ + ahc->msgout_index = 0; + ahc->msgout_len = 0; + + if ((ahc->targ_msg_req & devinfo->target_mask) != 0) + ahc_build_transfer_msg(ahc, devinfo); + else + panic("ahc_intr: AWAITING target message with no message"); + + ahc->msgout_index = 0; + ahc->msg_type = MSG_TYPE_TARGET_MSGIN; +} +#endif +/**************************** Initialization **********************************/ /* - * We have an scb which has been processed by the - * adaptor, now we look to see how the operation - * went. + * Allocate a controller structure for a new device + * and perform initial initializion. */ -static void -ahc_done(struct ahc_softc *ahc, struct scb *scb) +struct ahc_softc * +ahc_alloc(void *platform_arg, char *name) { - union ccb *ccb; + struct ahc_softc *ahc; + int i; - CAM_DEBUG(scb->ccb->ccb_h.path, CAM_DEBUG_TRACE, - ("ahc_done - scb %d\n", scb->hscb->tag)); + ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); + if (!ahc) { + printf("aic7xxx: cannot malloc softc!\n"); + free(name, M_DEVBUF); + return NULL; + } + memset(ahc, 0, sizeof(*ahc)); + LIST_INIT(&ahc->pending_scbs); + /* We don't know or unit number until the OSM sets it */ + ahc->name = name; + for (i = 0; i < 16; i++) + TAILQ_INIT(&ahc->untagged_queues[i]); + if (ahc_platform_alloc(ahc, platform_arg) != 0) { + ahc_free(ahc); + ahc = NULL; + } + return (ahc); +} - ccb = scb->ccb; - LIST_REMOVE(&ccb->ccb_h, sim_links.le); - if (ccb->ccb_h.func_code == XPT_SCSI_IO - && ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0 - || ccb->csio.tag_action == CAM_TAG_ACTION_NONE) - && (ahc->features & AHC_SCB_BTT) == 0) { - struct scb_tailq *untagged_q; +int +ahc_softc_init(struct ahc_softc *ahc, struct ahc_probe_config *config) +{ - untagged_q = &ahc->untagged_queues[ccb->ccb_h.target_id]; - TAILQ_REMOVE(untagged_q, scb, links.tqe); - ahc_run_untagged_queue(ahc, untagged_q); + ahc->chip = config->chip; + ahc->features = config->features; + ahc->bugs = config->bugs; + ahc->flags = config->flags; + ahc->channel = config->channel; + ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; + ahc->description = config->description; + /* The IRQMS bit is only valid on VL and EISA chips */ + if ((ahc->chip & AHC_PCI) != 0) + ahc->unpause &= ~IRQMS; + ahc->pause = ahc->unpause | PAUSE; + /* XXX The shared scb data stuff should be depricated */ + if (ahc->scb_data == NULL) { + ahc->scb_data = malloc(sizeof(*ahc->scb_data), + M_DEVBUF, M_NOWAIT); + if (ahc->scb_data == NULL) + return (ENOMEM); + memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); } - untimeout(ahc_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch); + return (0); +} - if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { - bus_dmasync_op_t op; +void +ahc_softc_insert(struct ahc_softc *ahc) +{ + struct ahc_softc *list_ahc; - if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) - op = BUS_DMASYNC_POSTREAD; - else - op = BUS_DMASYNC_POSTWRITE; - bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op); - bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); +#ifdef AHC_SUPPORT_PCI + /* + * Second Function PCI devices need to inherit some + * settings from function 0. We assume that function 0 + * will always be found prior to function 1. + */ + if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI + && ahc_get_pci_function(ahc->dev_softc) == 1) { + TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { + ahc_dev_softc_t list_pci; + ahc_dev_softc_t pci; + + list_pci = list_ahc->dev_softc; + pci = ahc->dev_softc; + if (ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci) + && ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) + && ahc_get_pci_function(list_pci) == 0) { + ahc->flags &= ~AHC_BIOS_ENABLED; + ahc->flags |= + list_ahc->flags & AHC_BIOS_ENABLED; + ahc->flags &= ~AHC_CHANNEL_B_PRIMARY; + ahc->flags |= + list_ahc->flags & AHC_CHANNEL_B_PRIMARY; + break; + } + } } +#endif - if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { - if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) - ccb->ccb_h.status |= CAM_REQ_CMP; - ccb->ccb_h.status &= ~CAM_SIM_QUEUED; - ahcfreescb(ahc, scb); - xpt_done(ccb); - return; + /* + * Insertion sort into our list of softcs. + */ + list_ahc = TAILQ_FIRST(&ahc_tailq); + while (list_ahc != NULL + && ahc_softc_comp(list_ahc, ahc) <= 0) + list_ahc = TAILQ_NEXT(list_ahc, links); + if (list_ahc != NULL) + TAILQ_INSERT_BEFORE(list_ahc, ahc, links); + else + TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); + ahc->init_level++; +} + +void +ahc_set_unit(struct ahc_softc *ahc, int unit) +{ + ahc->unit = unit; +} + +void +ahc_set_name(struct ahc_softc *ahc, char *name) +{ + if (ahc->name != NULL) + free(ahc->name, M_DEVBUF); + ahc->name = name; +} + +void +ahc_free(struct ahc_softc *ahc) +{ + ahc_fini_scbdata(ahc); + switch (ahc->init_level) { + case 4: + ahc_shutdown(ahc); + TAILQ_REMOVE(&ahc_tailq, ahc, links); + /* FALLTHROUGH */ + case 3: + ahc_dmamap_unload(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap); + /* FALLTHROUGH */ + case 2: + ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, + ahc->shared_data_dmamap); + ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, + ahc->shared_data_dmamap); + /* FALLTHROUGH */ + case 1: +#ifndef __linux__ + ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); +#endif + break; } + ahc_platform_free(ahc); +#if XXX + for () { + ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, + char channel, int force); + } +#endif + if (ahc->name != NULL) + free(ahc->name, M_DEVBUF); + free(ahc, M_DEVBUF); + return; +} + +void +ahc_shutdown(void *arg) +{ + struct ahc_softc *ahc; + int i; + + ahc = (struct ahc_softc *)arg; + + /* This will reset most registers to 0, but not all */ + ahc_reset(ahc); + ahc_outb(ahc, SCSISEQ, 0); + ahc_outb(ahc, SXFRCTL0, 0); + ahc_outb(ahc, DSPCISTATUS, 0); + + for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) + ahc_outb(ahc, i, 0); +} + +/* + * Reset the controller and record some information about it + * that is only availabel just after a reset. + */ +int +ahc_reset(struct ahc_softc *ahc) +{ + u_int sblkctl; + u_int sxfrctl1_a, sxfrctl1_b; + int wait; + /* - * If the recovery SCB completes, we have to be - * out of our timeout. + * Preserve the value of the SXFRCTL1 register for all channels. + * It contains settings that affect termination and we don't want + * to disturb the integrity of the bus. */ - if ((scb->flags & SCB_RECOVERY_SCB) != 0) { - - struct ccb_hdr *ccbh; + pause_sequencer(ahc); + sxfrctl1_b = 0; + if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { + u_int sblkctl; /* - * We were able to complete the command successfully, - * so reinstate the timeouts for all other pending - * commands. + * Save channel B's settings in case this chip + * is setup for TWIN channel operation. */ - ccbh = ahc->pending_ccbs.lh_first; - while (ccbh != NULL) { - struct scb *pending_scb; - - pending_scb = (struct scb *)ccbh->ccb_scb_ptr; - ccbh->timeout_ch = - timeout(ahc_timeout, pending_scb, - (ccbh->timeout * hz)/1000); - ccbh = LIST_NEXT(ccbh, sim_links.le); - } + sblkctl = ahc_inb(ahc, SBLKCTL); + ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); + sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); + ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); + } + sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); - /* - * Ensure that we didn't put a second instance of this - * SCB into the QINFIFO. - */ - ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), - SCB_GET_CHANNEL(ahc, scb), - SCB_GET_LUN(scb), scb->hscb->tag, - ROLE_INITIATOR, /*status*/0, - SEARCH_REMOVE); - if (ahc_ccb_status(ccb) == CAM_BDR_SENT - || ahc_ccb_status(ccb) == CAM_REQ_ABORTED) - ahcsetccbstatus(ccb, CAM_CMD_TIMEOUT); - xpt_print_path(ccb->ccb_h.path); - printf("no longer in timeout, status = %x\n", - ccb->ccb_h.status); + ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); + + /* + * Ensure that the reset has finished + */ + wait = 1000; + do { + ahc_delay(1000); + } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); + + if (wait == 0) { + printf("%s: WARNING - Failed chip reset! " + "Trying to initialize anyway.\n", ahc_name(ahc)); + ahc_outb(ahc, HCNTRL, ahc->pause); } - /* Don't clobber any existing error state */ - if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) { - ccb->ccb_h.status |= CAM_REQ_CMP; - } else if ((scb->flags & SCB_SENSE) != 0) { - /* - * We performed autosense retrieval. - * - * bzero the sense data before having - * the drive fill it. The SCSI spec mandates - * that any untransfered data should be - * assumed to be zero. Complete the 'bounce' - * of sense information through buffers accessible - * via bus-space by copying it into the clients - * csio. - */ - bzero(&ccb->csio.sense_data, sizeof(ccb->csio.sense_data)); - bcopy(&ahc->scb_data->sense[scb->hscb->tag], - &ccb->csio.sense_data, - scb->sg_list->len & AHC_SG_LEN_MASK); - scb->ccb->ccb_h.status |= CAM_AUTOSNS_VALID; - } - ccb->ccb_h.status &= ~CAM_SIM_QUEUED; - ahcfreescb(ahc, scb); - xpt_done(ccb); + /* Determine channel configuration */ + sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); + /* No Twin Channel PCI cards */ + if ((ahc->chip & AHC_PCI) != 0) + sblkctl &= ~SELBUSB; + switch (sblkctl) { + case 0: + /* Single Narrow Channel */ + break; + case 2: + /* Wide Channel */ + ahc->features |= AHC_WIDE; + break; + case 8: + /* Twin Channel */ + ahc->features |= AHC_TWIN; + break; + default: + printf(" Unsupported adapter type. Ignoring\n"); + return(-1); + } + + /* + * Reload sxfrctl1. + * + * We must always initialize STPWEN to 1 before we + * restore the saved values. STPWEN is initialized + * to a tri-state condition which can only be cleared + * by turning it on. + */ + if ((ahc->features & AHC_TWIN) != 0) { + u_int sblkctl; + + sblkctl = ahc_inb(ahc, SBLKCTL); + ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); + ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); + ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); + } + ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); + +#ifdef AHC_DUMP_SEQ + if (ahc->init_level == 0) + ahc_dumpseq(ahc); +#endif + + return (0); } /* @@ -4382,31 +3162,368 @@ ahc_probe_scbs(struct ahc_softc *ahc) { for (i = 0; i < AHC_SCB_MAX; i++) { ahc_outb(ahc, SCBPTR, i); - ahc_outb(ahc, SCB_CONTROL, i); - if (ahc_inb(ahc, SCB_CONTROL) != i) + ahc_outb(ahc, SCB_BASE, i); + if (ahc_inb(ahc, SCB_BASE) != i) break; ahc_outb(ahc, SCBPTR, 0); - if (ahc_inb(ahc, SCB_CONTROL) != 0) + if (ahc_inb(ahc, SCB_BASE) != 0) break; } return (i); } +void +ahc_init_probe_config(struct ahc_probe_config *probe_config) +{ + probe_config->description = NULL; + probe_config->channel = 'A'; + probe_config->channel_b = 'B'; + probe_config->chip = AHC_NONE; + probe_config->features = AHC_FENONE; + probe_config->bugs = AHC_BUGNONE; + probe_config->flags = AHC_FNONE; +} + +static void +ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + bus_addr_t *baddr; + + baddr = (bus_addr_t *)arg; + *baddr = segs->ds_addr; +} + +static int +ahc_init_scbdata(struct ahc_softc *ahc) +{ + struct scb_data *scb_data; + int i; + + scb_data = ahc->scb_data; + SLIST_INIT(&scb_data->free_scbs); + SLIST_INIT(&scb_data->sg_maps); + + /* Allocate SCB resources */ + scb_data->scbarray = + (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, + M_DEVBUF, M_NOWAIT); + if (scb_data->scbarray == NULL) + return (ENOMEM); + memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX); + + /* Determine the number of hardware SCBs and initialize them */ + + scb_data->maxhscbs = ahc_probe_scbs(ahc); + /* SCB 0 heads the free list */ + ahc_outb(ahc, FREE_SCBH, 0); + for (i = 0; i < ahc->scb_data->maxhscbs; i++) { + ahc_outb(ahc, SCBPTR, i); + + /* Clear the control byte. */ + ahc_outb(ahc, SCB_CONTROL, 0); + + /* Set the next pointer */ + ahc_outb(ahc, SCB_NEXT, i+1); + + /* Make the tag number invalid */ + ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); + } + + /* Make sure that the last SCB terminates the free list */ + ahc_outb(ahc, SCBPTR, i-1); + ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); + + /* Ensure we clear the 0 SCB's control byte. */ + ahc_outb(ahc, SCBPTR, 0); + ahc_outb(ahc, SCB_CONTROL, 0); + + scb_data->maxhscbs = i; + + if (ahc->scb_data->maxhscbs == 0) + panic("%s: No SCB space found", ahc_name(ahc)); + + /* + * Create our DMA tags. These tags define the kinds of device + * accessible memory allocations and memory mappings we will + * need to perform during normal operation. + * + * Unless we need to further restrict the allocation, we rely + * on the restrictions of the parent dmat, hence the common + * use of MAXADDR and MAXSIZE. + */ + + /* DMA tag for our hardware scb structures */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + AHC_SCB_MAX * sizeof(struct hardware_scb), + /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &scb_data->hscb_dmat) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* Allocation for our ccbs */ + if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, + (void **)&scb_data->hscbs, + BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* And permanently map them */ + ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, + scb_data->hscbs, + AHC_SCB_MAX * sizeof(struct hardware_scb), + ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); + + scb_data->init_level++; + + /* DMA tag for our sense buffers */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + AHC_SCB_MAX * sizeof(struct scsi_sense_data), + /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &scb_data->sense_dmat) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* Allocate them */ + if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, + (void **)&scb_data->sense, + BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* And permanently map them */ + ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, + scb_data->sense, + AHC_SCB_MAX * sizeof(struct scsi_sense_data), + ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); + + scb_data->init_level++; + + /* DMA tag for our S/G structures. We allocate in page sized chunks */ + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, + /*highaddr*/BUS_SPACE_MAXADDR, + /*filter*/NULL, /*filterarg*/NULL, + PAGE_SIZE, /*nsegments*/1, + /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, + /*flags*/0, &scb_data->sg_dmat) != 0) { + goto error_exit; + } + + scb_data->init_level++; + + /* Perform initial CCB allocation */ + memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); + ahc_alloc_scbs(ahc); + + if (scb_data->numscbs == 0) { + printf("%s: ahc_init_scbdata - " + "Unable to allocate initial scbs\n", + ahc_name(ahc)); + goto error_exit; + } + + /* + * Note that we were successfull + */ + return (0); + +error_exit: + + return (ENOMEM); +} + +static void +ahc_fini_scbdata(struct ahc_softc *ahc) +{ + struct scb_data *scb_data; + + scb_data = ahc->scb_data; + + switch (scb_data->init_level) { + default: + case 7: + { + struct sg_map_node *sg_map; + + while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { + SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); + ahc_dmamap_unload(ahc, scb_data->sg_dmat, + sg_map->sg_dmamap); + ahc_dmamem_free(ahc, scb_data->sg_dmat, + sg_map->sg_vaddr, + sg_map->sg_dmamap); + free(sg_map, M_DEVBUF); + } + ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); + } + case 6: + ahc_dmamap_unload(ahc, scb_data->sense_dmat, + scb_data->sense_dmamap); + case 5: + ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, + scb_data->sense_dmamap); + ahc_dmamap_destroy(ahc, scb_data->sense_dmat, + scb_data->sense_dmamap); + case 4: + ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); + case 3: + ahc_dmamap_unload(ahc, scb_data->hscb_dmat, + scb_data->hscb_dmamap); + case 2: + ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, + scb_data->hscb_dmamap); + ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, + scb_data->hscb_dmamap); + case 1: + ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); + break; + } + if (scb_data->scbarray != NULL) + free(scb_data->scbarray, M_DEVBUF); +} + +void +ahc_alloc_scbs(struct ahc_softc *ahc) +{ + struct scb_data *scb_data; + struct scb *next_scb; + struct sg_map_node *sg_map; + bus_addr_t physaddr; + struct ahc_dma_seg *segs; + int newcount; + int i; + + scb_data = ahc->scb_data; + if (scb_data->numscbs >= AHC_SCB_MAX) + /* Can't allocate any more */ + return; + + next_scb = &scb_data->scbarray[scb_data->numscbs]; + + sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); + + if (sg_map == NULL) + return; + + /* Allocate S/G space for the next batch of SCBS */ + if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, + (void **)&sg_map->sg_vaddr, + BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { + free(sg_map, M_DEVBUF); + return; + } + + SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); + + ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, + sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, + &sg_map->sg_physaddr, /*flags*/0); + + segs = sg_map->sg_vaddr; + physaddr = sg_map->sg_physaddr; + + newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); + for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { + struct scb_platform_data *pdata; +#ifndef __linux__ + int error; +#endif + pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), + M_DEVBUF, M_NOWAIT); + if (pdata == NULL) + break; + next_scb->platform_data = pdata; + next_scb->sg_list = segs; + /* + * The sequencer always starts with the second entry. + * The first entry is embedded in the scb. + */ + next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); + next_scb->flags = SCB_FREE; +#ifndef __linux__ + error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, + &next_scb->dmamap); + if (error != 0) + break; +#endif + next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; + next_scb->hscb->tag = ahc->scb_data->numscbs; + next_scb->cdb32_busaddr = + ahc_hscb_busaddr(ahc, next_scb->hscb->tag) + + offsetof(struct hardware_scb, cdb32); + SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, + next_scb, links.sle); + segs += AHC_NSEG; + physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); + next_scb++; + ahc->scb_data->numscbs++; + } +} + +void +ahc_controller_info(struct ahc_softc *ahc, char *buf) +{ + int len; + + len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); + buf += len; + if ((ahc->features & AHC_TWIN) != 0) + len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " + "B SCSI Id=%d, primary %c, ", + ahc->our_id, ahc->our_id_b, + ahc->flags & AHC_CHANNEL_B_PRIMARY ? 'B': 'A'); + else { + const char *type; + + if ((ahc->features & AHC_WIDE) != 0) { + type = "Wide"; + } else { + type = "Single"; + } + len = sprintf(buf, "%s Channel %c, SCSI Id=%d, ", + type, ahc->channel, ahc->our_id); + } + buf += len; + + if (ahc->flags & AHC_PAGESCBS) + len = sprintf(buf, "%d/%d SCBs", + ahc->scb_data->maxhscbs, AHC_SCB_MAX); + else + len = sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); + buf += len; +} + /* * Start the board, ready for normal operation */ int ahc_init(struct ahc_softc *ahc) { - int max_targ = 15; - int i; - int term; - u_int scsi_conf; - u_int scsiseq_template; - u_int ultraenb; - u_int discenable; - u_int tagenable; - size_t driver_data_size; + int max_targ; + int i; + int term; + u_int scsi_conf; + u_int scsiseq_template; + u_int ultraenb; + u_int discenable; + u_int tagenable; + size_t driver_data_size; uint32_t physaddr; #ifdef AHC_PRINT_SRAM @@ -4427,6 +3544,7 @@ ahc_init(struct ahc_softc *ahc) } printf ("\n"); #endif + max_targ = 15; /* * Assume we have a board at this stage and it has been reset. @@ -4439,12 +3557,7 @@ ahc_init(struct ahc_softc *ahc) */ ahc->flags |= AHC_INITIATORMODE; - /* - * XXX Would be better to use a per device flag, but PCI and EISA - * devices don't have them yet. - */ - if ((AHC_TMODE_ENABLE & (0x01 << ahc->unit)) != 0) { - ahc->flags |= AHC_TARGETMODE; + if ((ahc->flags & AHC_TARGETMODE) != 0) { /* * Although we have space for both the initiator and * target roles on ULTRA2 chips, we currently disable @@ -4457,9 +3570,10 @@ ahc_init(struct ahc_softc *ahc) ahc->flags &= ~AHC_INITIATORMODE; } +#ifndef __linux__ /* DMA tag for mapping buffers into device visible space. */ - if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0, - /*lowaddr*/BUS_SPACE_MAXADDR, + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL, /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, @@ -4468,6 +3582,7 @@ ahc_init(struct ahc_softc *ahc) &ahc->buffer_dmat) != 0) { return (ENOMEM); } +#endif ahc->init_level++; @@ -4476,7 +3591,7 @@ ahc_init(struct ahc_softc *ahc) * the card's sequencer must be able to access. For initiator * roles, we need to allocate space for the the qinfifo and qoutfifo. * The qinfifo and qoutfifo are composed of 256 1 byte elements. - * When providing for the target mode role, we additionally must + * When providing for the target mode role, we must additionally * provide space for the incoming target command fifo and an extra * byte to deal with a dma bug in some chip versions. */ @@ -4484,8 +3599,8 @@ ahc_init(struct ahc_softc *ahc) if ((ahc->flags & AHC_TARGETMODE) != 0) driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) + /*DMA WideOdd Bug Buffer*/1; - if (bus_dma_tag_create(ahc->parent_dmat, /*alignment*/1, /*boundary*/0, - /*lowaddr*/BUS_SPACE_MAXADDR, + if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, + /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL, driver_data_size, @@ -4498,7 +3613,7 @@ ahc_init(struct ahc_softc *ahc) ahc->init_level++; /* Allocation of driver data */ - if (bus_dmamem_alloc(ahc->shared_data_dmat, + if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, (void **)&ahc->qoutfifo, BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { return (ENOMEM); @@ -4506,9 +3621,9 @@ ahc_init(struct ahc_softc *ahc) ahc->init_level++; - /* And permanently map it in */ - bus_dmamap_load(ahc->shared_data_dmat, ahc->shared_data_dmamap, - ahc->qoutfifo, driver_data_size, ahcdmamapcb, + /* And permanently map it in */ + ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, + ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, &ahc->shared_data_busaddr, /*flags*/0); if ((ahc->flags & AHC_TARGETMODE) != 0) { @@ -4530,7 +3645,7 @@ ahc_init(struct ahc_softc *ahc) /* Allocate SCB data now that buffer_dmat is initialized */ if (ahc->scb_data->maxhscbs == 0) - if (ahcinitscbdata(ahc) != 0) + if (ahc_init_scbdata(ahc) != 0) return (ENOMEM); /* @@ -4550,26 +3665,14 @@ ahc_init(struct ahc_softc *ahc) "Failing attach\n", ahc_name(ahc)); return (-1); } - printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", - ahc->our_id, ahc->our_id_b, - ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); - } else { - if ((ahc->features & AHC_WIDE) != 0) { - printf("Wide "); - } else { - printf("Single "); - } - printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); } ahc_outb(ahc, SEQ_FLAGS, 0); if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { ahc->flags |= AHC_PAGESCBS; - printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, AHC_SCB_MAX); } else { ahc->flags &= ~AHC_PAGESCBS; - printf("%d SCBs\n", ahc->scb_data->maxhscbs); } #ifdef AHC_DEBUG @@ -4577,7 +3680,7 @@ ahc_init(struct ahc_softc *ahc) printf("%s: hardware scb %d bytes; kernel scb %d bytes; " "ahc_dma %d bytes\n", ahc_name(ahc), - sizeof(struct hardware_scb), + sizeof(struct hardware_scb), sizeof(struct scb), sizeof(struct ahc_dma_seg)); } @@ -4590,11 +3693,9 @@ ahc_init(struct ahc_softc *ahc) * The device is gated to channel B after a chip reset, * so set those values first */ + ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; - if ((ahc->features & AHC_ULTRA2) != 0) - ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); - else - ahc_outb(ahc, SCSIID, ahc->our_id_b); + ahc_outb(ahc, SCSIID, ahc->our_id_b); scsi_conf = ahc_inb(ahc, SCSICONF + 1); ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) |term|ENSTIMER|ACTNEGEN); @@ -4669,7 +3770,7 @@ ahc_init(struct ahc_softc *ahc) tinfo = ahc_fetch_transinfo(ahc, channel, our_id, target_id, &tstate); /* Default to async narrow across the board */ - bzero(tinfo, sizeof(*tinfo)); + memset(tinfo, 0, sizeof(*tinfo)); if (ahc->flags & AHC_USEDEFAULTS) { if ((ahc->features & AHC_WIDE) != 0) tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; @@ -4847,20 +3948,16 @@ ahc_init(struct ahc_softc *ahc) /* * Load the Sequencer program and Enable the adapter * in "fast" mode. - */ + */ if (bootverbose) printf("%s: Downloading Sequencer Program...", ahc_name(ahc)); ahc_loadseq(ahc); - /* We have to wait until after any system dumps... */ - EVENTHANDLER_REGISTER(shutdown_final, ahc_shutdown, - ahc, SHUTDOWN_PRI_DEFAULT); - if ((ahc->features & AHC_ULTRA2) != 0) { int wait; - + /* * Wait for up to 500ms for our transceivers * to settle. If the adapter does not have @@ -4872,1510 +3969,130 @@ ahc_init(struct ahc_softc *ahc) for (wait = 5000; (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; wait--) - DELAY(100); + ahc_delay(100); unpause_sequencer(ahc); } - return (0); } -static cam_status -ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, - struct tmode_tstate **tstate, struct tmode_lstate **lstate, - int notfound_failure) -{ - u_int our_id; - - /* - * If we are not configured for target mode, someone - * is really confused to be sending this to us. - */ - if ((ahc->flags & AHC_TARGETMODE) == 0) - return (CAM_REQ_INVALID); - - /* Range check target and lun */ - - /* - * Handle the 'black hole' device that sucks up - * requests to unattached luns on enabled targets. - */ - if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD - && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { - *tstate = NULL; - *lstate = ahc->black_hole; - } else { - u_int max_id; - - if (cam_sim_bus(sim) == 0) - our_id = ahc->our_id; - else - our_id = ahc->our_id_b; - - max_id = (ahc->features & AHC_WIDE) ? 15 : 7; - if (ccb->ccb_h.target_id > max_id) - return (CAM_TID_INVALID); - - if (ccb->ccb_h.target_lun > 7) - return (CAM_LUN_INVALID); - - if (ccb->ccb_h.target_id != our_id) { - if ((ahc->features & AHC_MULTI_TID) != 0) { - /* - * Only allow additional targets if - * the initiator role is disabled. - * The hardware cannot handle a re-select-in - * on the initiator id during a re-select-out - * on a different target id. - */ - if ((ahc->flags & AHC_INITIATORMODE) != 0) - return (CAM_TID_INVALID); - } else { - /* - * Only allow our target id to change - * if the initiator role is not configured - * and there are no enabled luns which - * are attached to the currently registered - * scsi id. - */ - if ((ahc->flags & AHC_INITIATORMODE) != 0 - || ahc->enabled_luns > 0) - return (CAM_TID_INVALID); - } - } - - *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; - *lstate = NULL; - if (*tstate != NULL) - *lstate = - (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; - } - - if (notfound_failure != 0 && *lstate == NULL) - return (CAM_PATH_INVALID); - - return (CAM_REQ_CMP); -} - -static void -ahc_action(struct cam_sim *sim, union ccb *ccb) +/************************** Busy Target Table *********************************/ +/* + * Return the untagged transaction id for a given target/channel lun. + * Optionally, clear the entry. + */ +u_int +ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) { - struct ahc_softc *ahc; - struct tmode_lstate *lstate; - u_int target_id; - u_int our_id; - int s; - - CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahc_action\n")); - - ahc = (struct ahc_softc *)cam_sim_softc(sim); - - target_id = ccb->ccb_h.target_id; - our_id = SIM_SCSI_ID(ahc, sim); - - switch (ccb->ccb_h.func_code) { - /* Common cases first */ - case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ - case XPT_CONT_TARGET_IO:/* Continue Host Target I/O Connection*/ - { - struct tmode_tstate *tstate; - cam_status status; - - status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, - &lstate, TRUE); - - if (status != CAM_REQ_CMP) { - if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { - /* Response from the black hole device */ - tstate = NULL; - lstate = ahc->black_hole; - } else { - ccb->ccb_h.status = status; - xpt_done(ccb); - break; - } - } - if (ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) { - int s; - - s = splcam(); - SLIST_INSERT_HEAD(&lstate->accept_tios, &ccb->ccb_h, - sim_links.sle); - ccb->ccb_h.status = CAM_REQ_INPROG; - if ((ahc->flags & AHC_TQINFIFO_BLOCKED) != 0) - ahc_run_tqinfifo(ahc, /*paused*/FALSE); - splx(s); - break; - } - - /* - * The target_id represents the target we attempt to - * select. In target mode, this is the initiator of - * the original command. - */ - our_id = target_id; - target_id = ccb->csio.init_id; - /* FALLTHROUGH */ - } - case XPT_SCSI_IO: /* Execute the requested I/O operation */ - case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ - { - struct scb *scb; - struct hardware_scb *hscb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - uint16_t mask; - - /* - * get an scb to use. - */ - if ((scb = ahcgetscb(ahc)) == NULL) { - int s; - - s = splcam(); - ahc->flags |= AHC_RESOURCE_SHORTAGE; - splx(s); - xpt_freeze_simq(ahc->sim, /*count*/1); - ahcsetccbstatus(ccb, CAM_REQUEUE_REQ); - xpt_done(ccb); - return; - } - - hscb = scb->hscb; - - CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_SUBTRACE, - ("start scb(%p)\n", scb)); - scb->ccb = ccb; - /* - * So we can find the SCB when an abort is requested - */ - ccb->ccb_h.ccb_scb_ptr = scb; - ccb->ccb_h.ccb_ahc_ptr = ahc; - - /* - * Put all the arguments for the xfer in the scb - */ - hscb->control = 0; - hscb->scsiid = BUILD_SCSIID(ahc, sim, target_id, our_id); - hscb->lun = ccb->ccb_h.target_lun; - mask = SCB_GET_TARGET_MASK(ahc, scb); - tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, sim), our_id, - target_id, &tstate); - - hscb->scsirate = tinfo->scsirate; - hscb->scsioffset = tinfo->current.offset; - if ((tstate->ultraenb & mask) != 0) - hscb->control |= ULTRAENB; - - if ((tstate->discenable & mask) != 0 - && (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0) - hscb->control |= DISCENB; - - if ((ccb->ccb_h.flags & CAM_NEGOTIATE) != 0 - && (tinfo->current.width != 0 || tinfo->current.period != 0)) { - scb->flags |= SCB_NEGOTIATE; - hscb->control |= MK_MESSAGE; - } - - if (ccb->ccb_h.func_code == XPT_RESET_DEV) { - hscb->cdb_len = 0; - scb->flags |= SCB_DEVICE_RESET; - hscb->control |= MK_MESSAGE; - ahc_execute_scb(scb, NULL, 0, 0); - } else { - if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { - struct target_data *tdata; - - tdata = &hscb->shared_data.tdata; - if (ahc->pending_device == lstate) { - scb->flags |= SCB_TARGET_IMMEDIATE; - ahc->pending_device = NULL; - } - hscb->control |= TARGET_SCB; - tdata->target_phases = IDENTIFY_SEEN; - if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { - tdata->target_phases |= SPHASE_PENDING; - tdata->scsi_status = - ccb->csio.scsi_status; - } - tdata->initiator_tag = ccb->csio.tag_id; - } - if (ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) - hscb->control |= ccb->csio.tag_action; - - ahc_setup_data(ahc, &ccb->csio, scb); - } - break; - } - case XPT_NOTIFY_ACK: - case XPT_IMMED_NOTIFY: - { - struct tmode_tstate *tstate; - struct tmode_lstate *lstate; - cam_status status; - - status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, - &lstate, TRUE); - - if (status != CAM_REQ_CMP) { - ccb->ccb_h.status = status; - xpt_done(ccb); - break; - } - SLIST_INSERT_HEAD(&lstate->immed_notifies, &ccb->ccb_h, - sim_links.sle); - ccb->ccb_h.status = CAM_REQ_INPROG; - ahc_send_lstate_events(ahc, lstate); - break; - } - case XPT_EN_LUN: /* Enable LUN as a target */ - ahc_handle_en_lun(ahc, sim, ccb); - xpt_done(ccb); - break; - case XPT_ABORT: /* Abort the specified CCB */ - { - ahc_abort_ccb(ahc, sim, ccb); - break; - } - case XPT_SET_TRAN_SETTINGS: - { - struct ahc_devinfo devinfo; - struct ccb_trans_settings *cts; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - uint16_t *discenable; - uint16_t *tagenable; - u_int update_type; - int s; - - cts = &ccb->cts; - ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), - cts->ccb_h.target_id, - cts->ccb_h.target_lun, - SIM_CHANNEL(ahc, sim), - ROLE_UNKNOWN); - tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, - devinfo.our_scsiid, - devinfo.target, &tstate); - update_type = 0; - if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { - update_type |= AHC_TRANS_GOAL; - discenable = &tstate->discenable; - tagenable = &tstate->tagenable; - } else if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { - update_type |= AHC_TRANS_USER; - discenable = &ahc->user_discenable; - tagenable = &ahc->user_tagenable; - } else { - ccb->ccb_h.status = CAM_REQ_INVALID; - xpt_done(ccb); - break; - } - - s = splcam(); - - if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { - if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) - *discenable |= devinfo.target_mask; - else - *discenable &= ~devinfo.target_mask; - } - - if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { - if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) - *tagenable |= devinfo.target_mask; - else - *tagenable &= ~devinfo.target_mask; - } - - if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { - ahc_validate_width(ahc, &cts->bus_width); - ahc_set_width(ahc, &devinfo, cts->ccb_h.path, - cts->bus_width, update_type, - /*paused*/FALSE); - } - - if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0) { - if (update_type == AHC_TRANS_USER) - cts->sync_offset = tinfo->user.offset; - else - cts->sync_offset = tinfo->goal.offset; - } - - if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0) { - if (update_type == AHC_TRANS_USER) - cts->sync_period = tinfo->user.period; - else - cts->sync_period = tinfo->goal.period; - } - - if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) - || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { - struct ahc_syncrate *syncrate; - u_int ppr_options; - u_int maxsync; - - if ((ahc->features & AHC_ULTRA2) != 0) - maxsync = AHC_SYNCRATE_DT; - else if ((ahc->features & AHC_ULTRA) != 0) - maxsync = AHC_SYNCRATE_ULTRA; - else - maxsync = AHC_SYNCRATE_FAST; - - ppr_options = 0; - if (cts->sync_period <= 9) - ppr_options = MSG_EXT_PPR_DT_REQ; - - syncrate = ahc_find_syncrate(ahc, &cts->sync_period, - &ppr_options, - maxsync); - ahc_validate_offset(ahc, syncrate, &cts->sync_offset, - MSG_EXT_WDTR_BUS_8_BIT); - - /* We use a period of 0 to represent async */ - if (cts->sync_offset == 0) { - cts->sync_period = 0; - ppr_options = 0; - } - - if (ppr_options == MSG_EXT_PPR_DT_REQ - && tinfo->user.transport_version >= 3) { - tinfo->goal.transport_version = - tinfo->user.transport_version; - tinfo->current.transport_version = - tinfo->user.transport_version; - } - - ahc_set_syncrate(ahc, &devinfo, cts->ccb_h.path, - syncrate, cts->sync_period, - cts->sync_offset, ppr_options, - update_type, /*paused*/FALSE); - } - - splx(s); - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - case XPT_GET_TRAN_SETTINGS: - /* Get default/user set transfer settings for the target */ - { - struct ahc_devinfo devinfo; - struct ccb_trans_settings *cts; - struct ahc_initiator_tinfo *targ_info; - struct tmode_tstate *tstate; - struct ahc_transinfo *tinfo; - int s; - - cts = &ccb->cts; - ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), - cts->ccb_h.target_id, - cts->ccb_h.target_lun, - SIM_CHANNEL(ahc, sim), - ROLE_UNKNOWN); - targ_info = ahc_fetch_transinfo(ahc, devinfo.channel, - devinfo.our_scsiid, - devinfo.target, &tstate); - - if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) - tinfo = &targ_info->current; - else - tinfo = &targ_info->user; - - s = splcam(); - - cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); - if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { - if ((ahc->user_discenable & devinfo.target_mask) != 0) - cts->flags |= CCB_TRANS_DISC_ENB; - - if ((ahc->user_tagenable & devinfo.target_mask) != 0) - cts->flags |= CCB_TRANS_TAG_ENB; - } else { - if ((tstate->discenable & devinfo.target_mask) != 0) - cts->flags |= CCB_TRANS_DISC_ENB; - - if ((tstate->tagenable & devinfo.target_mask) != 0) - cts->flags |= CCB_TRANS_TAG_ENB; - } - cts->sync_period = tinfo->period; - cts->sync_offset = tinfo->offset; - cts->bus_width = tinfo->width; - - splx(s); - - cts->valid = CCB_TRANS_SYNC_RATE_VALID - | CCB_TRANS_SYNC_OFFSET_VALID - | CCB_TRANS_BUS_WIDTH_VALID - | CCB_TRANS_DISC_VALID - | CCB_TRANS_TQ_VALID; + u_int scbid; + u_int target_offset; - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - case XPT_CALC_GEOMETRY: - { - struct ccb_calc_geometry *ccg; - uint32_t size_mb; - uint32_t secs_per_cylinder; - int extended; - - ccg = &ccb->ccg; - size_mb = ccg->volume_size - / ((1024L * 1024L) / ccg->block_size); - extended = SIM_IS_SCSIBUS_B(ahc, sim) - ? ahc->flags & AHC_EXTENDED_TRANS_B - : ahc->flags & AHC_EXTENDED_TRANS_A; - - if (size_mb > 1024 && extended) { - ccg->heads = 255; - ccg->secs_per_track = 63; - } else { - ccg->heads = 64; - ccg->secs_per_track = 32; - } - secs_per_cylinder = ccg->heads * ccg->secs_per_track; - ccg->cylinders = ccg->volume_size / secs_per_cylinder; - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - case XPT_RESET_BUS: /* Reset the specified SCSI bus */ - { - int found; - - s = splcam(); - found = ahc_reset_channel(ahc, SIM_CHANNEL(ahc, sim), - /*initiate reset*/TRUE); - splx(s); - if (bootverbose) { - xpt_print_path(SIM_PATH(ahc, sim)); - printf("SCSI bus reset delivered. " - "%d SCBs aborted.\n", found); - } - ccb->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - case XPT_TERM_IO: /* Terminate the I/O process */ - /* XXX Implement */ - ccb->ccb_h.status = CAM_REQ_INVALID; - xpt_done(ccb); - break; - case XPT_PATH_INQ: /* Path routing inquiry */ - { - struct ccb_pathinq *cpi = &ccb->cpi; + if ((ahc->features & AHC_SCB_BTT) != 0) { + u_int saved_scbptr; - cpi->version_num = 1; /* XXX??? */ - cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; - if ((ahc->features & AHC_WIDE) != 0) - cpi->hba_inquiry |= PI_WIDE_16; - if ((ahc->flags & AHC_TARGETMODE) != 0) { - cpi->target_sprt = PIT_PROCESSOR - | PIT_DISCONNECT - | PIT_TERM_IO; - } else { - cpi->target_sprt = 0; - } - cpi->hba_misc = (ahc->flags & AHC_INITIATORMODE) - ? 0 : PIM_NOINITIATOR; - cpi->hba_eng_cnt = 0; - cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; - cpi->max_lun = 64; - if (SIM_IS_SCSIBUS_B(ahc, sim)) { - cpi->initiator_id = ahc->our_id_b; - if ((ahc->flags & AHC_RESET_BUS_B) == 0) - cpi->hba_misc |= PIM_NOBUSRESET; - } else { - cpi->initiator_id = ahc->our_id; - if ((ahc->flags & AHC_RESET_BUS_A) == 0) - cpi->hba_misc |= PIM_NOBUSRESET; - } - cpi->bus_id = cam_sim_bus(sim); - cpi->base_transfer_speed = 3300; - strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); - strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN); - strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); - cpi->unit_number = cam_sim_unit(sim); - cpi->ccb_h.status = CAM_REQ_CMP; - xpt_done(ccb); - break; - } - default: - ccb->ccb_h.status = CAM_REQ_INVALID; - xpt_done(ccb); - break; + saved_scbptr = ahc_inb(ahc, SCBPTR); + ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); + scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); + if (unbusy) + ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), + SCB_LIST_NULL); + ahc_outb(ahc, SCBPTR, saved_scbptr); + } else { + target_offset = TCL_TARGET_OFFSET(tcl); + scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); + if (unbusy) + ahc_outb(ahc, BUSY_TARGETS + target_offset, + SCB_LIST_NULL); } -} - -static void -ahc_async(void *callback_arg, uint32_t code, struct cam_path *path, void *arg) -{ - struct ahc_softc *ahc; - struct cam_sim *sim; - - sim = (struct cam_sim *)callback_arg; - ahc = (struct ahc_softc *)cam_sim_softc(sim); - switch (code) { - case AC_LOST_DEVICE: - { - struct ahc_devinfo devinfo; - int s; - ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), - xpt_path_target_id(path), - xpt_path_lun_id(path), - SIM_CHANNEL(ahc, sim), - ROLE_UNKNOWN); - - /* - * Revert to async/narrow transfers - * for the next device. - */ - s = splcam(); - ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, - AHC_TRANS_GOAL|AHC_TRANS_CUR, - /*paused*/FALSE); - ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, - /*period*/0, /*offset*/0, /*ppr_options*/0, - AHC_TRANS_GOAL|AHC_TRANS_CUR, - /*paused*/FALSE); - splx(s); - break; - } - default: - break; - } + return (scbid); } -static void -ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments, - int error) +void +ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) { - struct scb *scb; - union ccb *ccb; - struct ahc_softc *ahc; - int s; - - scb = (struct scb *)arg; - ccb = scb->ccb; - ahc = (struct ahc_softc *)ccb->ccb_h.ccb_ahc_ptr; - - if (error != 0) { - if (error == EFBIG) - ahcsetccbstatus(scb->ccb, CAM_REQ_TOO_BIG); - else - ahcsetccbstatus(scb->ccb, CAM_REQ_CMP_ERR); - if (nsegments != 0) - bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); - ahcfreescb(ahc, scb); - xpt_done(ccb); - return; - } - if (nsegments != 0) { - struct ahc_dma_seg *sg; - bus_dma_segment_t *end_seg; - bus_dmasync_op_t op; - - end_seg = dm_segs + nsegments; + u_int target_offset; - /* Copy the segments into our SG list */ - sg = scb->sg_list; - while (dm_segs < end_seg) { - sg->addr = dm_segs->ds_addr; -/* XXX Add in the 5th byte of the address later. */ - sg->len = dm_segs->ds_len; - sg++; - dm_segs++; - } + if ((ahc->features & AHC_SCB_BTT) != 0) { + u_int saved_scbptr; - /* - * Note where to find the SG entries in bus space. - * We also set the full residual flag which the - * sequencer will clear as soon as a data transfer - * occurs. - */ - scb->hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; - - if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) - op = BUS_DMASYNC_PREREAD; - else - op = BUS_DMASYNC_PREWRITE; - - bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op); - - if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { - struct target_data *tdata; - - tdata = &scb->hscb->shared_data.tdata; - tdata->target_phases |= DPHASE_PENDING; - if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) - tdata->data_phase = P_DATAOUT; - else - tdata->data_phase = P_DATAIN; - - /* - * If the transfer is of an odd length and in the - * "in" direction (scsi->HostBus), then it may - * trigger a bug in the 'WideODD' feature of - * non-Ultra2 chips. Force the total data-length - * to be even by adding an extra, 1 byte, SG, - * element. We do this even if we are not currently - * negotiated wide as negotiation could occur before - * this command is executed. - */ - if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0 - && (ccb->csio.dxfer_len & 0x1) != 0 - && (ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { - - nsegments++; - if (nsegments > AHC_NSEG) { - - ahcsetccbstatus(scb->ccb, - CAM_REQ_TOO_BIG); - bus_dmamap_unload(ahc->buffer_dmat, - scb->dmamap); - ahcfreescb(ahc, scb); - xpt_done(ccb); - return; - } - sg->addr = ahc->dma_bug_buf; - sg->len = 1; - sg++; - } - } - sg--; - sg->len |= AHC_DMA_LAST_SEG; - - /* Copy the first SG into the "current" data pointer area */ - scb->hscb->dataptr = scb->sg_list->addr; - scb->hscb->datacnt = scb->sg_list->len; - } else { - scb->hscb->sgptr = SG_LIST_NULL; - scb->hscb->dataptr = 0; - scb->hscb->datacnt = 0; - } - - scb->sg_count = nsegments; - - s = splcam(); - - /* - * Last time we need to check if this SCB needs to - * be aborted. - */ - if (ahc_ccb_status(ccb) != CAM_REQ_INPROG) { - if (nsegments != 0) - bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); - ahcfreescb(ahc, scb); - xpt_done(ccb); - splx(s); - return; - } - - LIST_INSERT_HEAD(&ahc->pending_ccbs, &ccb->ccb_h, - sim_links.le); - - ccb->ccb_h.status |= CAM_SIM_QUEUED; - - if (ccb->ccb_h.timeout != CAM_TIME_INFINITY) { - if (ccb->ccb_h.timeout == CAM_TIME_DEFAULT) - ccb->ccb_h.timeout = 5 * 1000; - ccb->ccb_h.timeout_ch = - timeout(ahc_timeout, (caddr_t)scb, - (ccb->ccb_h.timeout * hz) / 1000); - } - - /* - * We only allow one untagged transaction - * per target in the initiator role unless - * we are storing a full busy target *lun* - * table in SCB space. - */ - if ((scb->hscb->control & (TARGET_SCB|TAG_ENB)) == 0 - && (ahc->features & AHC_SCB_BTT) == 0) { - struct scb_tailq *untagged_q; - - untagged_q = &(ahc->untagged_queues[ccb->ccb_h.target_id]); - TAILQ_INSERT_TAIL(untagged_q, scb, links.tqe); - if (TAILQ_FIRST(untagged_q) != scb) { - splx(s); - return; - } - } - scb->flags |= SCB_ACTIVE; - - if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { -#if 0 - printf("Continueing Immediate Command %d:%d\n", - ccb->ccb_h.target_id, ccb->ccb_h.target_lun); -#endif - pause_sequencer(ahc); - if ((ahc->flags & AHC_PAGESCBS) == 0) - ahc_outb(ahc, SCBPTR, scb->hscb->tag); - ahc_outb(ahc, SCB_TAG, scb->hscb->tag); - ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); - unpause_sequencer(ahc); + saved_scbptr = ahc_inb(ahc, SCBPTR); + ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); + ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); + ahc_outb(ahc, SCBPTR, saved_scbptr); } else { - ahc_queue_scb(ahc, scb); + target_offset = TCL_TARGET_OFFSET(tcl); + ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); } - - splx(s); -} - -static void -ahc_poll(struct cam_sim *sim) -{ - ahc_intr(cam_sim_softc(sim)); } -static void -ahc_setup_data(struct ahc_softc *ahc, struct ccb_scsiio *csio, - struct scb *scb) +/************************** SCB and SCB queue management **********************/ +int +ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, + char channel, int lun, u_int tag, role_t role) { - struct hardware_scb *hscb; - struct ccb_hdr *ccb_h; - - hscb = scb->hscb; - ccb_h = &csio->ccb_h; - - if (ccb_h->func_code == XPT_SCSI_IO) { - hscb->cdb_len = csio->cdb_len; - if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { - - if (hscb->cdb_len > sizeof(hscb->cdb32) - || (ccb_h->flags & CAM_CDB_PHYS) != 0) { - ahcsetccbstatus(scb->ccb, CAM_REQ_INVALID); - xpt_done(scb->ccb); - ahcfreescb(ahc, scb); - return; - } - if (hscb->cdb_len > 12) { - memcpy(hscb->cdb32, - csio->cdb_io.cdb_ptr, - hscb->cdb_len); - if ((ahc->flags & AHC_CMD_CHAN) == 0) { - hscb->shared_data.cdb_ptr = - scb->cdb32_busaddr; - } - } else { - memcpy(hscb->shared_data.cdb, - csio->cdb_io.cdb_ptr, - hscb->cdb_len); - } - } else { - if (hscb->cdb_len > 12) { - memcpy(hscb->cdb32, csio->cdb_io.cdb_bytes, - hscb->cdb_len); - if ((ahc->flags & AHC_CMD_CHAN) == 0) { - hscb->shared_data.cdb_ptr = - scb->cdb32_busaddr; - } - } else { - memcpy(hscb->shared_data.cdb, - csio->cdb_io.cdb_bytes, - hscb->cdb_len); - } - } - } - - /* Only use S/G if there is a transfer */ - if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { - if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { - /* We've been given a pointer to a single buffer */ - if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { - int s; - int error; - - s = splsoftvm(); - error = bus_dmamap_load(ahc->buffer_dmat, - scb->dmamap, - csio->data_ptr, - csio->dxfer_len, - ahc_execute_scb, - scb, /*flags*/0); - if (error == EINPROGRESS) { - /* - * So as to maintain ordering, - * freeze the controller queue - * until our mapping is - * returned. - */ - xpt_freeze_simq(ahc->sim, - /*count*/1); - scb->ccb->ccb_h.status |= - CAM_RELEASE_SIMQ; - } - splx(s); - } else { - struct bus_dma_segment seg; - - /* Pointer to physical buffer */ - if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE) - panic("ahc_setup_data - Transfer size " - "larger than can device max"); - - seg.ds_addr = (intptr_t)csio->data_ptr; - seg.ds_len = csio->dxfer_len; - ahc_execute_scb(scb, &seg, 1, 0); - } - } else { - struct bus_dma_segment *segs; - - if ((ccb_h->flags & CAM_DATA_PHYS) != 0) - panic("ahc_setup_data - Physical segment " - "pointers unsupported"); + int targ = SCB_GET_TARGET(ahc, scb); + char chan = SCB_GET_CHANNEL(ahc, scb); + int slun = SCB_GET_LUN(scb); + int match; - if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) - panic("ahc_setup_data - Virtual segment " - "addresses unsupported"); + match = ((chan == channel) || (channel == ALL_CHANNELS)); + if (match != 0) + match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); + if (match != 0) + match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); + if (match != 0) { +#if AHC_TARGET_MODE + int group; - /* Just use the segments provided */ - segs = (struct bus_dma_segment *)csio->data_ptr; - ahc_execute_scb(scb, segs, csio->sglist_cnt, 0); + group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); + if (role == ROLE_INITIATOR) { + match = (group == XPT_FC_GROUP_COMMON) + && ((tag == scb->hscb->tag) + || (tag == SCB_LIST_NULL)); + } else if (role == ROLE_TARGET) { + match = (group == XPT_FC_GROUP_TMODE) + && ((tag == scb->io_ctx->csio.tag_id) + || (tag == SCB_LIST_NULL)); } - } else { - ahc_execute_scb(scb, NULL, 0, 0); +#else /* !AHC_TARGET_MODE */ + match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); +#endif /* AHC_TARGET_MODE */ } + + return match; } -static void -ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path) +void +ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) { int target; char channel; int lun; - target = xpt_path_target_id(path); - lun = xpt_path_lun_id(path); - channel = xpt_path_sim(path)->bus_id == 0 ? 'A' : 'B'; + target = SCB_GET_TARGET(ahc, scb); + lun = SCB_GET_LUN(scb); + channel = SCB_GET_CHANNEL(ahc, scb); ahc_search_qinfifo(ahc, target, channel, lun, /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, CAM_REQUEUE_REQ, SEARCH_COMPLETE); -} - -static void -ahcallocscbs(struct ahc_softc *ahc) -{ - struct scb_data *scb_data; - struct scb *next_scb; - struct sg_map_node *sg_map; - bus_addr_t physaddr; - struct ahc_dma_seg *segs; - int newcount; - int i; - - scb_data = ahc->scb_data; - if (scb_data->numscbs >= AHC_SCB_MAX) - /* Can't allocate any more */ - return; - next_scb = &scb_data->scbarray[scb_data->numscbs]; - - sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); - - if (sg_map == NULL) - return; - - /* Allocate S/G space for the next batch of SCBS */ - if (bus_dmamem_alloc(scb_data->sg_dmat, (void **)&sg_map->sg_vaddr, - BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { - free(sg_map, M_DEVBUF); - return; - } - - SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); - - bus_dmamap_load(scb_data->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr, - PAGE_SIZE, ahcdmamapcb, &sg_map->sg_physaddr, - /*flags*/0); - - segs = sg_map->sg_vaddr; - physaddr = sg_map->sg_physaddr; - - newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); - for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { - int error; - - next_scb->sg_list = segs; - /* - * The sequencer always starts with the second entry. - * The first entry is embedded in the scb. - */ - next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); - next_scb->flags = SCB_FREE; - error = bus_dmamap_create(ahc->buffer_dmat, /*flags*/0, - &next_scb->dmamap); - if (error != 0) - break; - next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; - next_scb->hscb->tag = ahc->scb_data->numscbs; - next_scb->cdb32_busaddr = - ahc_hscb_busaddr(ahc, next_scb->hscb->tag) - + offsetof(struct hardware_scb, cdb32); - SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, - next_scb, links.sle); - segs += AHC_NSEG; - physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); - next_scb++; - ahc->scb_data->numscbs++; - } + ahc_platform_freeze_devq(ahc, scb); } -#ifdef AHC_DUMP_SEQ -static void -ahc_dumpseq(struct ahc_softc* ahc) -{ - int i; - int max_prog; - - if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) - max_prog = 448; - else if ((ahc->features & AHC_ULTRA2) != 0) - max_prog = 768; - else - max_prog = 512; - - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); - ahc_outb(ahc, SEQADDR0, 0); - ahc_outb(ahc, SEQADDR1, 0); - for (i = 0; i < max_prog; i++) { - uint8_t ins_bytes[4]; - - ahc_insb(ahc, SEQRAM, ins_bytes, 4); - printf("0x%08x\n", ins_bytes[0] << 24 - | ins_bytes[1] << 16 - | ins_bytes[2] << 8 - | ins_bytes[3]); - } -} -#endif - -static void -ahc_loadseq(struct ahc_softc *ahc) -{ - struct patch *cur_patch; - u_int i; - int downloaded; - u_int skip_addr; - uint8_t download_consts[2]; - - /* Setup downloadable constant table */ - download_consts[QOUTFIFO_OFFSET] = 0; - if (ahc->targetcmds != NULL) - download_consts[QOUTFIFO_OFFSET] += 32; - download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; - - cur_patch = patches; - downloaded = 0; - skip_addr = 0; - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); - ahc_outb(ahc, SEQADDR0, 0); - ahc_outb(ahc, SEQADDR1, 0); - - for (i = 0; i < sizeof(seqprog)/4; i++) { - if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { - /* - * Don't download this instruction as it - * is in a patch that was removed. - */ - continue; - } - ahc_download_instr(ahc, i, download_consts); - downloaded++; - } - ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); - restart_sequencer(ahc); - - if (bootverbose) - printf(" %d instructions downloaded\n", downloaded); -} - -static int -ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, - u_int start_instr, u_int *skip_addr) -{ - struct patch *cur_patch; - struct patch *last_patch; - u_int num_patches; - - num_patches = sizeof(patches)/sizeof(struct patch); - last_patch = &patches[num_patches]; - cur_patch = *start_patch; - - while (cur_patch < last_patch && start_instr == cur_patch->begin) { - - if (cur_patch->patch_func(ahc) == 0) { - - /* Start rejecting code */ - *skip_addr = start_instr + cur_patch->skip_instr; - cur_patch += cur_patch->skip_patch; - } else { - /* Accepted this patch. Advance to the next - * one and wait for our intruction pointer to - * hit this point. - */ - cur_patch++; - } - } - - *start_patch = cur_patch; - if (start_instr < *skip_addr) - /* Still skipping */ - return (0); - - return (1); -} - -static void -ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) -{ - union ins_formats instr; - struct ins_format1 *fmt1_ins; - struct ins_format3 *fmt3_ins; - u_int opcode; - - /* Structure copy */ - instr = *(union ins_formats*)&seqprog[instrptr * 4]; - -#if BYTE_ORDER == BIG_ENDIAN - opcode = instr.format.bytes[0]; - instr.format.bytes[0] = instr.format.bytes[3]; - instr.format.bytes[3] = opcode; - opcode = instr.format.bytes[1]; - instr.format.bytes[1] = instr.format.bytes[2]; - instr.format.bytes[2] = opcode; -#endif - - fmt1_ins = &instr.format1; - fmt3_ins = NULL; - - /* Pull the opcode */ - opcode = instr.format1.opcode; - switch (opcode) { - case AIC_OP_JMP: - case AIC_OP_JC: - case AIC_OP_JNC: - case AIC_OP_CALL: - case AIC_OP_JNE: - case AIC_OP_JNZ: - case AIC_OP_JE: - case AIC_OP_JZ: - { - struct patch *cur_patch; - int address_offset; - u_int address; - u_int skip_addr; - u_int i; - - fmt3_ins = &instr.format3; - address_offset = 0; - address = fmt3_ins->address; - cur_patch = patches; - skip_addr = 0; - - for (i = 0; i < address;) { - - ahc_check_patch(ahc, &cur_patch, i, &skip_addr); - - if (skip_addr > i) { - int end_addr; - - end_addr = MIN(address, skip_addr); - address_offset += end_addr - i; - i = skip_addr; - } else { - i++; - } - } - address -= address_offset; - fmt3_ins->address = address; - /* FALLTHROUGH */ - } - case AIC_OP_OR: - case AIC_OP_AND: - case AIC_OP_XOR: - case AIC_OP_ADD: - case AIC_OP_ADC: - case AIC_OP_BMOV: - if (fmt1_ins->parity != 0) { - fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; - } - fmt1_ins->parity = 0; - /* FALLTHROUGH */ - case AIC_OP_ROL: - if ((ahc->features & AHC_ULTRA2) != 0) { - int i, count; - - /* Calculate odd parity for the instruction */ - for (i = 0, count = 0; i < 31; i++) { - uint32_t mask; - - mask = 0x01 << i; - if ((instr.integer & mask) != 0) - count++; - } - if ((count & 0x01) == 0) - instr.format1.parity = 1; - } else { - /* Compress the instruction for older sequencers */ - if (fmt3_ins != NULL) { - instr.integer = - fmt3_ins->immediate - | (fmt3_ins->source << 8) - | (fmt3_ins->address << 16) - | (fmt3_ins->opcode << 25); - } else { - instr.integer = - fmt1_ins->immediate - | (fmt1_ins->source << 8) - | (fmt1_ins->destination << 16) - | (fmt1_ins->ret << 24) - | (fmt1_ins->opcode << 25); - } - } -#if BYTE_ORDER == BIG_ENDIAN - opcode = instr.format.bytes[0]; - instr.format.bytes[0] = instr.format.bytes[3]; - instr.format.bytes[3] = opcode; - opcode = instr.format.bytes[1]; - instr.format.bytes[1] = instr.format.bytes[2]; - instr.format.bytes[2] = opcode; -#endif - ahc_outsb(ahc, SEQRAM, instr.bytes, 4); - break; - default: - panic("Unknown opcode encountered in seq program"); - break; - } -} - -static void -ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) { - - if ((scb->flags & SCB_RECOVERY_SCB) == 0) { - struct ccb_hdr *ccbh; - - scb->flags |= SCB_RECOVERY_SCB; - - /* - * Take all queued, but not sent SCBs out of the equation. - * Also ensure that no new CCBs are queued to us while we - * try to fix this problem. - */ - if ((scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { - xpt_freeze_simq(ahc->sim, /*count*/1); - scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; - } - - /* - * Go through all of our pending SCBs and remove - * any scheduled timeouts for them. We will reschedule - * them after we've successfully fixed this problem. - */ - ccbh = ahc->pending_ccbs.lh_first; - while (ccbh != NULL) { - struct scb *pending_scb; - - pending_scb = (struct scb *)ccbh->ccb_scb_ptr; - untimeout(ahc_timeout, pending_scb, ccbh->timeout_ch); - ccbh = ccbh->sim_links.le.le_next; - } - } -} - -static void -ahc_timeout(void *arg) -{ - struct scb *scb; - struct ahc_softc *ahc; - int s, found; - u_int last_phase; - int target; - int lun; - int i; - char channel; - - scb = (struct scb *)arg; - ahc = (struct ahc_softc *)scb->ccb->ccb_h.ccb_ahc_ptr; - - s = splcam(); - - /* - * Ensure that the card doesn't do anything - * behind our back. Also make sure that we - * didn't "just" miss an interrupt that would - * affect this timeout. - */ - do { - ahc_intr(ahc); - pause_sequencer(ahc); - } while (ahc_inb(ahc, INTSTAT) & INT_PEND); - - xpt_print_path(scb->ccb->ccb_h.path); - if ((scb->flags & SCB_ACTIVE) == 0) { - /* Previous timeout took care of me already */ - printf("Timedout SCB %d handled by another timeout\n", - scb->hscb->tag); - unpause_sequencer(ahc); - splx(s); - return; - } - - target = SCB_GET_TARGET(ahc, scb); - channel = SCB_GET_CHANNEL(ahc, scb); - lun = SCB_GET_LUN(scb); - - printf("SCB 0x%x - timed out ", scb->hscb->tag); - /* - * Take a snapshot of the bus state and print out - * some information so we can track down driver bugs. - */ - last_phase = ahc_inb(ahc, LASTPHASE); - - for (i = 0; i < num_phases; i++) { - if (last_phase == phase_table[i].phase) - break; - } - printf("%s", phase_table[i].phasemsg); - - printf(", SEQADDR == 0x%x\n", - ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); - -#if 0 - printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); - printf("SSTAT3 == 0x%x\n", ahc_inb(ahc, SSTAT3)); - printf("SCSIPHASE == 0x%x\n", ahc_inb(ahc, SCSIPHASE)); - printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); - printf("SCSIOFFSET == 0x%x\n", ahc_inb(ahc, SCSIOFFSET)); - printf("SEQ_FLAGS == 0x%x\n", ahc_inb(ahc, SEQ_FLAGS)); - printf("SCB_DATAPTR == 0x%x\n", ahc_inb(ahc, SCB_DATAPTR) - | ahc_inb(ahc, SCB_DATAPTR + 1) << 8 - | ahc_inb(ahc, SCB_DATAPTR + 2) << 16 - | ahc_inb(ahc, SCB_DATAPTR + 3) << 24); - printf("SCB_DATACNT == 0x%x\n", ahc_inb(ahc, SCB_DATACNT) - | ahc_inb(ahc, SCB_DATACNT + 1) << 8 - | ahc_inb(ahc, SCB_DATACNT + 2) << 16); - printf("SCB_SGCOUNT == 0x%x\n", ahc_inb(ahc, SCB_SGCOUNT)); - printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); - printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); - printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); - printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); - printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); - if (scb->sg_count > 0) { - for (i = 0; i < scb->sg_count; i++) { - printf("sg[%d] - Addr 0x%x : Length %d\n", - i, - scb->sg_list[i].addr, - scb->sg_list[i].len); - } - } -#endif - if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { - /* - * Been down this road before. - * Do a full bus reset. - */ -bus_reset: - ahcsetccbstatus(scb->ccb, CAM_CMD_TIMEOUT); - found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); - printf("%s: Issued Channel %c Bus Reset. " - "%d SCBs aborted\n", ahc_name(ahc), channel, found); - } else { - /* - * If we are a target, transition to bus free and report - * the timeout. - * - * The target/initiator that is holding up the bus may not - * be the same as the one that triggered this timeout - * (different commands have different timeout lengths). - * If the bus is idle and we are actiing as the initiator - * for this request, queue a BDR message to the timed out - * target. Otherwise, if the timed out transaction is - * active: - * Initiator transaction: - * Stuff the message buffer with a BDR message and assert - * ATN in the hopes that the target will let go of the bus - * and go to the mesgout phase. If this fails, we'll - * get another timeout 2 seconds later which will attempt - * a bus reset. - * - * Target transaction: - * Transition to BUS FREE and report the error. - * It's good to be the target! - */ - u_int active_scb_index; - - active_scb_index = ahc_inb(ahc, SCB_TAG); - - if (last_phase != P_BUSFREE - && (active_scb_index < ahc->scb_data->numscbs)) { - struct scb *active_scb; - - /* - * If the active SCB is not from our device, - * assume that another device is hogging the bus - * and wait for it's timeout to expire before - * taking additional action. - */ - active_scb = &ahc->scb_data->scbarray[active_scb_index]; - if (active_scb->hscb->scsiid != scb->hscb->scsiid - || active_scb->hscb->lun != scb->hscb->lun) { - struct ccb_hdr *ccbh; - u_int newtimeout; - - xpt_print_path(scb->ccb->ccb_h.path); - printf("Other SCB Timeout%s", - (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 - ? " again\n" : "\n"); - scb->flags |= SCB_OTHERTCL_TIMEOUT; - newtimeout = MAX(active_scb->ccb->ccb_h.timeout, - scb->ccb->ccb_h.timeout); - ccbh = &scb->ccb->ccb_h; - scb->ccb->ccb_h.timeout_ch = - timeout(ahc_timeout, scb, - (newtimeout * hz) / 1000); - splx(s); - return; - } - - /* It's us */ - if ((scb->hscb->control & TARGET_SCB) != 0) { - - /* - * Send back any queued up transactions - * and properly record the error condition. - */ - ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); - ahcsetccbstatus(scb->ccb, CAM_CMD_TIMEOUT); - ahc_freeze_ccb(scb->ccb); - ahc_done(ahc, scb); - - /* Will clear us from the bus */ - restart_sequencer(ahc); - return; - } - - ahc_set_recoveryscb(ahc, active_scb); - ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); - ahc_outb(ahc, SCSISIGO, last_phase|ATNO); - xpt_print_path(active_scb->ccb->ccb_h.path); - printf("BDR message in message buffer\n"); - active_scb->flags |= SCB_DEVICE_RESET; - active_scb->ccb->ccb_h.timeout_ch = - timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); - unpause_sequencer(ahc); - } else { - int disconnected; - - /* XXX Shouldn't panic. Just punt instead */ - if ((scb->hscb->control & TARGET_SCB) != 0) - panic("Timed-out target SCB but bus idle"); - - if (last_phase != P_BUSFREE - && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { - /* XXX What happened to the SCB? */ - /* Hung target selection. Goto busfree */ - printf("%s: Hung target selection\n", - ahc_name(ahc)); - restart_sequencer(ahc); - return; - } - - if (ahc_search_qinfifo(ahc, target, channel, lun, - scb->hscb->tag, ROLE_INITIATOR, - /*status*/0, SEARCH_COUNT) > 0) { - disconnected = FALSE; - } else { - disconnected = TRUE; - } - - if (disconnected) { - u_int active_scb; - - ahc_set_recoveryscb(ahc, scb); - /* - * Simply set the MK_MESSAGE control bit. - */ - scb->hscb->control |= MK_MESSAGE; - scb->flags |= SCB_QUEUED_MSG - | SCB_DEVICE_RESET; - - /* - * Mark the cached copy of this SCB in the - * disconnected list too, so that a reconnect - * at this point causes a BDR or abort. - */ - active_scb = ahc_inb(ahc, SCBPTR); - if (ahc_search_disc_list(ahc, target, - channel, lun, - scb->hscb->tag, - /*stop_on_first*/TRUE, - /*remove*/FALSE, - /*save_state*/FALSE)) { - u_int scb_control; - - scb_control = ahc_inb(ahc, SCB_CONTROL); - scb_control |= MK_MESSAGE; - ahc_outb(ahc, SCB_CONTROL, scb_control); - } - ahc_outb(ahc, SCBPTR, active_scb); - - /* - * Actually re-queue this SCB in case we can - * select the device before it reconnects. - * Clear out any entries in the QINFIFO first - * so we are the next SCB for this target - * to run. - */ - ahc_search_qinfifo(ahc, - SCB_GET_TARGET(ahc, scb), - channel, SCB_GET_LUN(scb), - SCB_LIST_NULL, - ROLE_INITIATOR, - CAM_REQUEUE_REQ, - SEARCH_COMPLETE); - xpt_print_path(scb->ccb->ccb_h.path); - printf("Queuing a BDR SCB\n"); - ahc->qinfifo[ahc->qinfifonext++] = - scb->hscb->tag; - if ((ahc->features & AHC_QUEUE_REGS) != 0) { - ahc_outb(ahc, HNSCB_QOFF, - ahc->qinfifonext); - } else { - ahc_outb(ahc, KERNEL_QINPOS, - ahc->qinfifonext); - } - scb->ccb->ccb_h.timeout_ch = - timeout(ahc_timeout, (caddr_t)scb, 2 * hz); - unpause_sequencer(ahc); - } else { - /* Go "immediatly" to the bus reset */ - /* This shouldn't happen */ - ahc_set_recoveryscb(ahc, scb); - xpt_print_path(scb->ccb->ccb_h.path); - printf("SCB %d: Immediate reset. " - "Flags = 0x%x\n", scb->hscb->tag, - scb->flags); - goto bus_reset; - } - } - } - splx(s); -} - -static int +int ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, int lun, u_int tag, role_t role, uint32_t status, ahc_search_action action) { - struct scb *scbp; + struct scb *scb; uint8_t qinpos; uint8_t qintail; uint8_t next, prev; uint8_t curscbptr; - int found; + int found; + int maxtarget; + int i; qinpos = ahc_inb(ahc, QINPOS); qintail = ahc->qinfifonext; @@ -6396,28 +4113,36 @@ ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, ahc->qinfifonext = qinpos; while (qinpos != qintail) { - scbp = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; - if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { + scb = &ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; + if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { /* * We found an scb that needs to be acted on. */ found++; switch (action) { case SEARCH_COMPLETE: - if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) - ahcsetccbstatus(scbp->ccb, status); - ahc_freeze_ccb(scbp->ccb); - ahc_done(ahc, scbp); + { + cam_status ostat; + + ostat = ahc_get_transaction_status(scb); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scb, + status); + ahc_freeze_scb(scb); + if ((scb->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB in qinfifo\n"); + ahc_done(ahc, scb); break; + } case SEARCH_COUNT: ahc->qinfifo[ahc->qinfifonext++] = - scbp->hscb->tag; + scb->hscb->tag; break; case SEARCH_REMOVE: break; } } else { - ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; + ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; } qinpos++; } @@ -6445,28 +4170,36 @@ ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, "SCB index == %d, yet numscbs == %d.", scb_index, ahc->scb_data->numscbs); } - scbp = &ahc->scb_data->scbarray[scb_index]; - if (ahc_match_scb(ahc, scbp, target, channel, + scb = &ahc->scb_data->scbarray[scb_index]; + if (ahc_match_scb(ahc, scb, target, channel, lun, SCB_LIST_NULL, role)) { /* * We found an scb that needs to be acted on. */ found++; switch (action) { - case SEARCH_REMOVE: - next = ahc_rem_wscb(ahc, next, prev); - break; case SEARCH_COMPLETE: + { + cam_status ostat; + next = ahc_rem_wscb(ahc, next, prev); - if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) - ahcsetccbstatus(scbp->ccb, status); - ahc_freeze_ccb(scbp->ccb); - ahc_done(ahc, scbp); + ostat = ahc_get_transaction_status(scb); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scb, + status); + ahc_freeze_scb(scb); + if ((scb->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB in Waiting List\n"); + ahc_done(ahc, scb); break; + } case SEARCH_COUNT: prev = next; next = ahc_inb(ahc, SCB_NEXT); break; + case SEARCH_REMOVE: + next = ahc_rem_wscb(ahc, next, prev); + break; } } else { @@ -6476,221 +4209,85 @@ ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, } ahc_outb(ahc, SCBPTR, curscbptr); - if (action == SEARCH_COMPLETE) - ahc_release_untagged_queues(ahc); - return (found); -} - - -static void -ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) -{ - union ccb *abort_ccb; - - abort_ccb = ccb->cab.abort_ccb; - switch (abort_ccb->ccb_h.func_code) { - case XPT_ACCEPT_TARGET_IO: - case XPT_IMMED_NOTIFY: - case XPT_CONT_TARGET_IO: - { - struct tmode_tstate *tstate; - struct tmode_lstate *lstate; - struct ccb_hdr_slist *list; - cam_status status; - - status = ahc_find_tmode_devs(ahc, sim, abort_ccb, &tstate, - &lstate, TRUE); - - if (status != CAM_REQ_CMP) { - ccb->ccb_h.status = status; - break; - } - - if (abort_ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) - list = &lstate->accept_tios; - else if (abort_ccb->ccb_h.func_code == XPT_IMMED_NOTIFY) - list = &lstate->immed_notifies; - else - list = NULL; - - if (list != NULL) { - struct ccb_hdr *curelm; - int found; - - curelm = SLIST_FIRST(list); - found = 0; - if (curelm == &abort_ccb->ccb_h) { - found = 1; - SLIST_REMOVE_HEAD(list, sim_links.sle); - } else { - while(curelm != NULL) { - struct ccb_hdr *nextelm; - - nextelm = - SLIST_NEXT(curelm, sim_links.sle); - - if (nextelm == &abort_ccb->ccb_h) { - found = 1; - SLIST_NEXT(curelm, - sim_links.sle) = - SLIST_NEXT(nextelm, - sim_links.sle); - break; - } - curelm = nextelm; - } - } - - if (found) { - abort_ccb->ccb_h.status = CAM_REQ_ABORTED; - xpt_done(abort_ccb); - ccb->ccb_h.status = CAM_REQ_CMP; - } else { - printf("Not found\n"); - ccb->ccb_h.status = CAM_PATH_INVALID; - } - break; - } - /* FALLTHROUGH */ - } - case XPT_SCSI_IO: - /* XXX Fully implement the hard ones */ - ccb->ccb_h.status = CAM_UA_ABORT; - break; - default: - ccb->ccb_h.status = CAM_REQ_INVALID; - break; - } - xpt_done(ccb); -} - -/* - * Abort all SCBs that match the given description (target/channel/lun/tag), - * setting their status to the passed in status if the status has not already - * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer - * is paused before it is called. - */ -static int -ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, - int lun, u_int tag, role_t role, uint32_t status) -{ - struct scb *scbp; - u_int active_scb; - int i; - int maxtarget; - int found; - - /* - * Don't attempt to run any queued untagged transactions - * until we are done with the abort process. - */ - ahc_freeze_untagged_queues(ahc); - - /* restore this when we're done */ - active_scb = ahc_inb(ahc, SCBPTR); - - found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, - role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); - /* - * Clean out the busy target table for any untagged commands. + * And lastly, the untagged holding queues. */ i = 0; - maxtarget = 16; - if (target != CAM_TARGET_WILDCARD) { - i = target; - maxtarget = target + 1; - } - - for (;i < maxtarget; i++) { - u_int scbid; + if ((ahc->flags & AHC_SCB_BTT) == 0) { - scbid = ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, 0), - /*unbusy*/FALSE); - scbp = &ahc->scb_data->scbarray[scbid]; - if (scbid < ahc->scb_data->numscbs - && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { - u_int minlun; - u_int maxlun; - - if (lun == CAM_LUN_WILDCARD) { + maxtarget = 16; + if (target != CAM_TARGET_WILDCARD) { - /* - * Unless we are using an SCB based - * busy targets table, there is only - * one table entry for all luns of - * a target. - */ - minlun = 0; - maxlun = 1; - if ((ahc->flags & AHC_SCB_BTT) != 0) - maxlun = AHC_NUM_LUNS; - } else { - minlun = lun; - maxlun = lun + 1; - } - while (minlun < maxlun) { - ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, - minlun), /*unbusy*/TRUE); - minlun++; - } + i = target; + if (channel == 'B') + i += 8; + maxtarget = i + 1; } + } else { + maxtarget = 0; } - /* - * Go through the disconnected list and remove any entries we - * have queued for completion, 0'ing their control byte too. - * We save the active SCB and restore it ourselves, so there - * is no reason for this search to restore it too. - */ - ahc_search_disc_list(ahc, target, channel, lun, tag, - /*stop_on_first*/FALSE, /*remove*/TRUE, - /*save_state*/FALSE); + for (; i < maxtarget; i++) { + struct scb_tailq *untagged_q; + struct scb *next_scb; - /* - * Go through the hardware SCB array looking for commands that - * were active but not on any list. - */ - for(i = 0; i < ahc->scb_data->maxhscbs; i++) { - u_int scbid; + untagged_q = &(ahc->untagged_queues[i]); + next_scb = TAILQ_FIRST(untagged_q); + while (next_scb != NULL) { - ahc_outb(ahc, SCBPTR, i); - scbid = ahc_inb(ahc, SCB_TAG); - scbp = &ahc->scb_data->scbarray[scbid]; - if (scbid < ahc->scb_data->numscbs - && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) - ahc_add_curscb_to_free_list(ahc); - } + scb = next_scb; + next_scb = TAILQ_NEXT(scb, links.tqe); - /* - * Go through the pending CCB list and look for - * commands for this target that are still active. - * These are other tagged commands that were - * disconnected when the reset occured. - */ - { - struct ccb_hdr *ccb_h; - - ccb_h = ahc->pending_ccbs.lh_first; - while (ccb_h != NULL) { - scbp = (struct scb *)ccb_h->ccb_scb_ptr; - ccb_h = ccb_h->sim_links.le.le_next; - if (ahc_match_scb(ahc, scbp, target, channel, - lun, tag, role)) { - if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) - ahcsetccbstatus(scbp->ccb, status); - ahc_freeze_ccb(scbp->ccb); - ahc_done(ahc, scbp); + /* + * The head of the list may be the currently + * active untagged command for a device. + * We're only searching for commands that + * have not been started. A transaction + * marked active but still in the qinfifo + * is removed by the qinfifo scanning code + * above. + */ + if ((scb->flags & SCB_ACTIVE) != 0) + continue; + + if (ahc_match_scb(ahc, scb, target, channel, + lun, SCB_LIST_NULL, role)) { + /* + * We found an scb that needs to be acted on. + */ found++; + switch (action) { + case SEARCH_COMPLETE: + { + cam_status ostat; + + ostat = ahc_get_transaction_status(scb); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scb, + status); + ahc_freeze_scb(scb); + if ((scb->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB in untaggedQ\n"); + ahc_done(ahc, scb); + break; + } + case SEARCH_REMOVE: + TAILQ_REMOVE(untagged_q, scb, + links.tqe); + break; + case SEARCH_COUNT: + break; + } } } } - ahc_outb(ahc, SCBPTR, active_scb); - ahc_release_untagged_queues(ahc); - return found; + + if (action == SEARCH_COMPLETE) + ahc_release_untagged_queues(ahc); + return (found); } -static int +int ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, int lun, u_int tag, int stop_on_first, int remove, int save_state) @@ -6751,6 +4348,10 @@ ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, return (count); } +/* + * Remove an SCB from the on chip list of disconnected transactions. + * This is empty/unused if we are not performing SCB paging. + */ static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) { @@ -6772,10 +4373,18 @@ ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) return (next); } +/* + * Add the SCB as selected by SCBPTR onto the on chip list of + * free hardware SCBs. This list is empty/unused if we are not + * performing SCB paging. + */ static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc) { - /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ + /* + * Invalidate the tag so that our abort + * routines don't think it's active. + */ ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); @@ -6830,15 +4439,135 @@ ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) return next; } -static void -ahc_clear_intstat(struct ahc_softc *ahc) +/******************************** Error Handling ******************************/ +/* + * Abort all SCBs that match the given description (target/channel/lun/tag), + * setting their status to the passed in status if the status has not already + * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer + * is paused before it is called. + */ +int +ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, + int lun, u_int tag, role_t role, uint32_t status) { - /* Clear any interrupt conditions this may have caused */ - ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); - ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI - |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| - CLRREQINIT); - ahc_outb(ahc, CLRINT, CLRSCSIINT); + struct scb *scbp; + struct scb *scbp_next; + u_int active_scb; + int i; + int maxtarget; + int found; + + /* + * Don't attempt to run any queued untagged transactions + * until we are done with the abort process. + */ + ahc_freeze_untagged_queues(ahc); + + /* restore this when we're done */ + active_scb = ahc_inb(ahc, SCBPTR); + + found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, + role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); + + /* + * Clean out the busy target table for any untagged commands. + */ + i = 0; + maxtarget = 16; + if (target != CAM_TARGET_WILDCARD) { + i = target; + if (channel == 'B') + i += 8; + maxtarget = i + 1; + } + + for (;i < maxtarget; i++) { + u_int scbid; + + scbid = ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, 0), + /*unbusy*/FALSE); + scbp = &ahc->scb_data->scbarray[scbid]; + if (scbid < ahc->scb_data->numscbs + && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { + u_int minlun; + u_int maxlun; + + if (lun == CAM_LUN_WILDCARD) { + + /* + * Unless we are using an SCB based + * busy targets table, there is only + * one table entry for all luns of + * a target. + */ + minlun = 0; + maxlun = 1; + if ((ahc->flags & AHC_SCB_BTT) != 0) + maxlun = AHC_NUM_LUNS; + } else { + minlun = lun; + maxlun = lun + 1; + } + while (minlun < maxlun) { + ahc_index_busy_tcl(ahc, BUILD_TCL(i << 4, + minlun), /*unbusy*/TRUE); + minlun++; + } + } + } + + /* + * Go through the disconnected list and remove any entries we + * have queued for completion, 0'ing their control byte too. + * We save the active SCB and restore it ourselves, so there + * is no reason for this search to restore it too. + */ + ahc_search_disc_list(ahc, target, channel, lun, tag, + /*stop_on_first*/FALSE, /*remove*/TRUE, + /*save_state*/FALSE); + + /* + * Go through the hardware SCB array looking for commands that + * were active but not on any list. + */ + for(i = 0; i < ahc->scb_data->maxhscbs; i++) { + u_int scbid; + + ahc_outb(ahc, SCBPTR, i); + scbid = ahc_inb(ahc, SCB_TAG); + scbp = &ahc->scb_data->scbarray[scbid]; + if (scbid < ahc->scb_data->numscbs + && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) + ahc_add_curscb_to_free_list(ahc); + } + + /* + * Go through the pending CCB list and look for + * commands for this target that are still active. + * These are other tagged commands that were + * disconnected when the reset occured. + */ + scbp_next = LIST_FIRST(&ahc->pending_scbs); + while (scbp_next != NULL) { + scbp = scbp_next; + scbp_next = LIST_NEXT(scbp, pending_links); + if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { + cam_status ostat; + + ostat = ahc_get_transaction_status(scbp); + if (ostat == CAM_REQ_INPROG) + ahc_set_transaction_status(scbp, status); + ahc_freeze_scb(scbp); + if ((scbp->flags & SCB_ACTIVE) == 0) + printf("Inactive SCB on pending list\n"); + ahc_done(ahc, scbp); + found++; + } + } + ahc_outb(ahc, SCBPTR, active_scb); + ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); + ahc_release_untagged_queues(ahc); + return found; } static void @@ -6849,7 +4578,7 @@ ahc_reset_current_bus(struct ahc_softc *ahc) ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); scsiseq = ahc_inb(ahc, SCSISEQ); ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); - DELAY(AHC_BUSRESET_DELAY); + ahc_delay(AHC_BUSRESET_DELAY); /* Turn off the bus reset */ ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); @@ -6859,19 +4588,23 @@ ahc_reset_current_bus(struct ahc_softc *ahc) ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); } -static int +int ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) { - struct cam_path *path; + struct ahc_devinfo devinfo; u_int initiator, target, max_scsiid; u_int sblkctl; - u_int our_id; int found; int restart_needed; char cur_channel; ahc->pending_device = NULL; + ahc_compile_devinfo(&devinfo, + CAM_TARGET_WILDCARD, + CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD, + channel, ROLE_UNKNOWN); pause_sequencer(ahc); /* @@ -6880,9 +4613,11 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) * before the reset occurred. */ ahc_run_qoutfifo(ahc); +#if AHC_TARGET_MODE if ((ahc->flags & AHC_TARGETMODE) != 0) { ahc_run_tqinfifo(ahc, /*paused*/TRUE); } +#endif /* * Reset the bus if we are initiating this reset @@ -6921,6 +4656,8 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) * a race in the sequencer that could cause corruption * of our Q pointers by starting over from index 1. */ + *((uint32_t *)(&ahc->qoutfifo[ahc->qoutfifonext & ~0x3])) + = 0xFFFFFFFF; ahc->qoutfifonext = 0; if ((ahc->features & AHC_QUEUE_REGS) != 0) ahc_outb(ahc, SDSCB_QOFF, 0); @@ -6948,16 +4685,10 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); - if (channel == 'B') { - path = ahc->path_b; - our_id = ahc->our_id_b; - } else { - path = ahc->path; - our_id = ahc->our_id; - } max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; +#ifdef AHC_TARGET_MODE /* * Send an immediate notify ccb to all target more peripheral * drivers affected by this action. @@ -6981,9 +4712,9 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) ahc_send_lstate_events(ahc, lstate); } } - +#endif /* Notify the XPT that a bus reset occurred */ - xpt_async(AC_BUS_RESET, path, NULL); + ahc_send_async(ahc, &devinfo, AC_BUS_RESET); /* * Revert to async/narrow transfers until we renegotiate. @@ -6998,13 +4729,12 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) ahc_compile_devinfo(&devinfo, target, initiator, CAM_LUN_WILDCARD, channel, ROLE_UNKNOWN); - ahc_set_width(ahc, &devinfo, path, - MSG_EXT_WDTR_BUS_8_BIT, + ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, AHC_TRANS_CUR, /*paused*/TRUE); - ahc_set_syncrate(ahc, &devinfo, path, - /*syncrate*/NULL, /*period*/0, - /*offset*/0, /*ppr_options*/0, - AHC_TRANS_CUR, /*paused*/TRUE); + ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, + /*period*/0, /*offset*/0, + /*ppr_options*/0, AHC_TRANS_CUR, + /*paused*/TRUE); } } @@ -7015,74 +4745,11 @@ ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) return found; } -static int -ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, - char channel, int lun, u_int tag, role_t role) -{ - int targ = SCB_GET_TARGET(ahc, scb); - char chan = SCB_GET_CHANNEL(ahc, scb); - int slun = SCB_GET_LUN(scb); - int match; - - match = ((chan == channel) || (channel == ALL_CHANNELS)); - if (match != 0) - match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); - if (match != 0) - match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); - if (match != 0) { - int group; - - group = XPT_FC_GROUP(scb->ccb->ccb_h.func_code); - if (role == ROLE_INITIATOR) { - match = (group == XPT_FC_GROUP_COMMON) - && ((tag == scb->hscb->tag) - || (tag == SCB_LIST_NULL)); - } else if (role == ROLE_TARGET) { - match = (group == XPT_FC_GROUP_TMODE) - && ((tag == scb->ccb->csio.tag_id) - || (tag == SCB_LIST_NULL)); - } - } - - return match; -} - -static void -ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) -{ - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; - ahc->msgout_buf[ahc->msgout_index++] = period; - ahc->msgout_buf[ahc->msgout_index++] = offset; - ahc->msgout_len += 5; -} - -static void -ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) -{ - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; - ahc->msgout_buf[ahc->msgout_index++] = bus_width; - ahc->msgout_len += 4; -} - -static void -ahc_construct_ppr(struct ahc_softc *ahc, u_int period, u_int offset, - u_int bus_width, u_int ppr_options) -{ - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; - ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; - ahc->msgout_buf[ahc->msgout_index++] = period; - ahc->msgout_buf[ahc->msgout_index++] = 0; - ahc->msgout_buf[ahc->msgout_index++] = offset; - ahc->msgout_buf[ahc->msgout_index++] = bus_width; - ahc->msgout_buf[ahc->msgout_index++] = ppr_options; - ahc->msgout_len += 8; -} +/***************************** Residual Processing ****************************/ +/* + * Calculate the residual for a just completed SCB. + */ static void ahc_calc_residual(struct scb *scb) { @@ -7117,15 +4784,15 @@ ahc_calc_residual(struct scb *scb) return; spkt = &hscb->shared_data.status; - if ((hscb->sgptr & SG_FULL_RESID) != 0) + if ((hscb->sgptr & SG_FULL_RESID) != 0) { /* Case 3 */ - resid = scb->ccb->csio.dxfer_len; - else if ((spkt->residual_sg_ptr & SG_LIST_NULL) != 0) + resid = ahc_get_transfer_length(scb); + } else if ((spkt->residual_sg_ptr & SG_LIST_NULL) != 0) { /* Case 4 */ return; - else if ((spkt->residual_sg_ptr & ~SG_PTR_MASK) != 0) + } else if ((spkt->residual_sg_ptr & ~SG_PTR_MASK) != 0) { panic("Bogus resid sgptr value 0x%x\n", spkt->residual_sg_ptr); - else { + } else { struct ahc_dma_seg *sg; /* @@ -7149,200 +4816,21 @@ ahc_calc_residual(struct scb *scb) resid += sg->len & AHC_SG_LEN_MASK; } } - if ((scb->flags & SCB_SENSE) == 0) { - - scb->ccb->csio.resid = resid; - } else { - - scb->ccb->csio.sense_resid = resid; - } + if ((scb->flags & SCB_SENSE) == 0) + ahc_set_residual(scb, resid); + else + ahc_set_sense_residual(scb, resid); #ifdef AHC_DEBUG if (ahc_debug & AHC_SHOWMISC) { - xpt_print_path(scb->ccb->ccb_h.path); + ahc_print_path(ahc, scb); printf("Handled Residual of %d bytes\n", resid); } #endif } -static void -ahc_update_pending_syncrates(struct ahc_softc *ahc) -{ - struct ccb_hdr *ccbh; - int pending_ccb_count; - int i; - u_int saved_scbptr; - - /* - * Traverse the pending SCB list and ensure that all of the - * SCBs there have the proper settings. - */ - ccbh = LIST_FIRST(&ahc->pending_ccbs); - pending_ccb_count = 0; - while (ccbh != NULL) { - struct ahc_devinfo devinfo; - union ccb *ccb; - struct scb *pending_scb; - struct hardware_scb *pending_hscb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int our_id, remote_id; - - ccb = (union ccb*)ccbh; - pending_scb = (struct scb *)ccbh->ccb_scb_ptr; - pending_hscb = pending_scb->hscb; - if (ccbh->func_code == XPT_CONT_TARGET_IO) { - our_id = ccb->ccb_h.target_id; - remote_id = ccb->ctio.init_id; - } else { - our_id = SCB_IS_SCSIBUS_B(ahc, pending_scb) - ? ahc->our_id_b : ahc->our_id; - remote_id = ccb->ccb_h.target_id; - } - ahc_compile_devinfo(&devinfo, our_id, remote_id, - SCB_GET_LUN(pending_scb), - SCB_GET_CHANNEL(ahc, pending_scb), - ROLE_UNKNOWN); - tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, - our_id, remote_id, &tstate); - pending_hscb->control &= ~ULTRAENB; - if ((tstate->ultraenb & devinfo.target_mask) != 0) - pending_hscb->control |= ULTRAENB; - pending_hscb->scsirate = tinfo->scsirate; - pending_hscb->scsioffset = tinfo->current.offset; - pending_ccb_count++; - ccbh = LIST_NEXT(ccbh, sim_links.le); - } - - if (pending_ccb_count == 0) - return; - - saved_scbptr = ahc_inb(ahc, SCBPTR); - /* Ensure that the hscbs down on the card match the new information */ - for (i = 0; i < ahc->scb_data->maxhscbs; i++) { - u_int scb_tag; - - ahc_outb(ahc, SCBPTR, i); - scb_tag = ahc_inb(ahc, SCB_TAG); - if (scb_tag != SCB_LIST_NULL) { - struct ahc_devinfo devinfo; - union ccb *ccb; - struct scb *pending_scb; - struct hardware_scb *pending_hscb; - struct ahc_initiator_tinfo *tinfo; - struct tmode_tstate *tstate; - u_int our_id, remote_id; - u_int control; - - pending_scb = &ahc->scb_data->scbarray[scb_tag]; - if (pending_scb->flags == SCB_FREE) - continue; - pending_hscb = pending_scb->hscb; - ccb = pending_scb->ccb; - if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { - our_id = ccb->ccb_h.target_id; - remote_id = ccb->ctio.init_id; - } else { - our_id = SCB_IS_SCSIBUS_B(ahc, pending_scb) - ? ahc->our_id_b : ahc->our_id; - remote_id = ccb->ccb_h.target_id; - } - ahc_compile_devinfo(&devinfo, our_id, remote_id, - SCB_GET_LUN(pending_scb), - SCB_GET_CHANNEL(ahc, pending_scb), - ROLE_UNKNOWN); - tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, - our_id, remote_id, &tstate); - control = ahc_inb(ahc, SCB_CONTROL); - control &= ~ULTRAENB; - if ((tstate->ultraenb & devinfo.target_mask) != 0) - control |= ULTRAENB; - ahc_outb(ahc, SCB_CONTROL, control); - ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); - ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); - } - } - ahc_outb(ahc, SCBPTR, saved_scbptr); -} - -#if UNUSED -static void -ahc_dump_targcmd(struct target_cmd *cmd) -{ - uint8_t *byte; - uint8_t *last_byte; - int i; - - byte = &cmd->initiator_channel; - /* Debugging info for received commands */ - last_byte = &cmd[1].initiator_channel; - - i = 0; - while (byte < last_byte) { - if (i == 0) - printf("\t"); - printf("%#x", *byte++); - i++; - if (i == 8) { - printf("\n"); - i = 0; - } else { - printf(", "); - } - } -} -#endif - -static void -ahc_shutdown(void *arg, int howto) -{ - struct ahc_softc *ahc; - int i; - u_int sxfrctl1_a, sxfrctl1_b; - - ahc = (struct ahc_softc *)arg; - - pause_sequencer(ahc); - - /* - * Preserve the value of the SXFRCTL1 register for all channels. - * It contains settings that affect termination and we don't want - * to disturb the integrity of the bus during shutdown in case - * we are in a multi-initiator setup. - */ - sxfrctl1_b = 0; - if ((ahc->features & AHC_TWIN) != 0) { - u_int sblkctl; - - sblkctl = ahc_inb(ahc, SBLKCTL); - ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); - sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); - ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); - } - - sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); - - /* This will reset most registers to 0, but not all */ - ahc_reset(ahc); - - if ((ahc->features & AHC_TWIN) != 0) { - u_int sblkctl; - - sblkctl = ahc_inb(ahc, SBLKCTL); - ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); - ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); - ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); - } - ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); - - ahc_outb(ahc, SCSISEQ, 0); - ahc_outb(ahc, SXFRCTL0, 0); - ahc_outb(ahc, DSPCISTATUS, 0); - - for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) - ahc_outb(ahc, i, 0); -} - +/******************************* Target Mode **********************************/ +#ifdef AHC_TARGET_MODE /* * Add a target mode event to this lun's queue */ @@ -7397,7 +4885,7 @@ ahc_queue_lstate_event(struct ahc_softc *ahc, struct tmode_lstate *lstate, * Send any target mode events queued up waiting * for immediate notify resources. */ -static void +void ahc_send_lstate_events(struct ahc_softc *ahc, struct tmode_lstate *lstate) { struct ccb_hdr *ccbh; @@ -7428,3 +4916,872 @@ ahc_send_lstate_events(struct ahc_softc *ahc, struct tmode_lstate *lstate) lstate->event_r_idx = 0; } } +#endif + +/******************** Sequencer Program Patching/Download *********************/ + +#ifdef AHC_DUMP_SEQ +void +ahc_dumpseq(struct ahc_softc* ahc) +{ + int i; + int max_prog; + + if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) + max_prog = 448; + else if ((ahc->features & AHC_ULTRA2) != 0) + max_prog = 768; + else + max_prog = 512; + + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); + ahc_outb(ahc, SEQADDR0, 0); + ahc_outb(ahc, SEQADDR1, 0); + for (i = 0; i < max_prog; i++) { + uint8_t ins_bytes[4]; + + ahc_insb(ahc, SEQRAM, ins_bytes, 4); + printf("0x%08x\n", ins_bytes[0] << 24 + | ins_bytes[1] << 16 + | ins_bytes[2] << 8 + | ins_bytes[3]); + } +} +#endif + +static void +ahc_loadseq(struct ahc_softc *ahc) +{ + struct patch *cur_patch; + u_int i; + int downloaded; + u_int skip_addr; + uint8_t download_consts[4]; + + /* Setup downloadable constant table */ + download_consts[QOUTFIFO_OFFSET] = 0; + if (ahc->targetcmds != NULL) + download_consts[QOUTFIFO_OFFSET] += 32; + download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; + download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; + download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); + + cur_patch = patches; + downloaded = 0; + skip_addr = 0; + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); + ahc_outb(ahc, SEQADDR0, 0); + ahc_outb(ahc, SEQADDR1, 0); + + for (i = 0; i < sizeof(seqprog)/4; i++) { + if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { + /* + * Don't download this instruction as it + * is in a patch that was removed. + */ + continue; + } + ahc_download_instr(ahc, i, download_consts); + downloaded++; + } + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); + restart_sequencer(ahc); + + if (bootverbose) + printf(" %d instructions downloaded\n", downloaded); +} + +static int +ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, + u_int start_instr, u_int *skip_addr) +{ + struct patch *cur_patch; + struct patch *last_patch; + u_int num_patches; + + num_patches = sizeof(patches)/sizeof(struct patch); + last_patch = &patches[num_patches]; + cur_patch = *start_patch; + + while (cur_patch < last_patch && start_instr == cur_patch->begin) { + + if (cur_patch->patch_func(ahc) == 0) { + + /* Start rejecting code */ + *skip_addr = start_instr + cur_patch->skip_instr; + cur_patch += cur_patch->skip_patch; + } else { + /* Accepted this patch. Advance to the next + * one and wait for our intruction pointer to + * hit this point. + */ + cur_patch++; + } + } + + *start_patch = cur_patch; + if (start_instr < *skip_addr) + /* Still skipping */ + return (0); + + return (1); +} + +static void +ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) +{ + union ins_formats instr; + struct ins_format1 *fmt1_ins; + struct ins_format3 *fmt3_ins; + u_int opcode; + + /* Structure copy */ + instr = *(union ins_formats*)&seqprog[instrptr * 4]; + +#if BYTE_ORDER == BIG_ENDIAN + opcode = instr.format.bytes[0]; + instr.format.bytes[0] = instr.format.bytes[3]; + instr.format.bytes[3] = opcode; + opcode = instr.format.bytes[1]; + instr.format.bytes[1] = instr.format.bytes[2]; + instr.format.bytes[2] = opcode; +#endif + + fmt1_ins = &instr.format1; + fmt3_ins = NULL; + + /* Pull the opcode */ + opcode = instr.format1.opcode; + switch (opcode) { + case AIC_OP_JMP: + case AIC_OP_JC: + case AIC_OP_JNC: + case AIC_OP_CALL: + case AIC_OP_JNE: + case AIC_OP_JNZ: + case AIC_OP_JE: + case AIC_OP_JZ: + { + struct patch *cur_patch; + int address_offset; + u_int address; + u_int skip_addr; + u_int i; + + fmt3_ins = &instr.format3; + address_offset = 0; + address = fmt3_ins->address; + cur_patch = patches; + skip_addr = 0; + + for (i = 0; i < address;) { + + ahc_check_patch(ahc, &cur_patch, i, &skip_addr); + + if (skip_addr > i) { + int end_addr; + + end_addr = MIN(address, skip_addr); + address_offset += end_addr - i; + i = skip_addr; + } else { + i++; + } + } + address -= address_offset; + fmt3_ins->address = address; + /* FALLTHROUGH */ + } + case AIC_OP_OR: + case AIC_OP_AND: + case AIC_OP_XOR: + case AIC_OP_ADD: + case AIC_OP_ADC: + case AIC_OP_BMOV: + if (fmt1_ins->parity != 0) { + fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; + } + fmt1_ins->parity = 0; + /* FALLTHROUGH */ + case AIC_OP_ROL: + if ((ahc->features & AHC_ULTRA2) != 0) { + int i, count; + + /* Calculate odd parity for the instruction */ + for (i = 0, count = 0; i < 31; i++) { + uint32_t mask; + + mask = 0x01 << i; + if ((instr.integer & mask) != 0) + count++; + } + if ((count & 0x01) == 0) + instr.format1.parity = 1; + } else { + /* Compress the instruction for older sequencers */ + if (fmt3_ins != NULL) { + instr.integer = + fmt3_ins->immediate + | (fmt3_ins->source << 8) + | (fmt3_ins->address << 16) + | (fmt3_ins->opcode << 25); + } else { + instr.integer = + fmt1_ins->immediate + | (fmt1_ins->source << 8) + | (fmt1_ins->destination << 16) + | (fmt1_ins->ret << 24) + | (fmt1_ins->opcode << 25); + } + } +#if BYTE_ORDER == BIG_ENDIAN + opcode = instr.format.bytes[0]; + instr.format.bytes[0] = instr.format.bytes[3]; + instr.format.bytes[3] = opcode; + opcode = instr.format.bytes[1]; + instr.format.bytes[1] = instr.format.bytes[2]; + instr.format.bytes[2] = opcode; +#endif + ahc_outsb(ahc, SEQRAM, instr.bytes, 4); + break; + default: + panic("Unknown opcode encountered in seq program"); + break; + } +} + +void +ahc_dump_card_state(struct ahc_softc *ahc) +{ + struct scb *scb; + struct scb_tailq *untagged_q; + int target; + int maxtarget; + int i; + uint8_t qinpos; + uint8_t qintail; + uint8_t qoutpos; + uint8_t scb_index; + uint8_t saved_scbptr; + + saved_scbptr = ahc_inb(ahc, SCBPTR); + + printf("SCB count = %d\n", ahc->scb_data->numscbs); + /* QINFIFO */ + printf("QINFIFO entries: "); + qinpos = ahc_inb(ahc, QINPOS); + qintail = ahc->qinfifonext; + while (qinpos != qintail) { + printf("%d ", ahc->qinfifo[qinpos]); + qinpos++; + } + printf("\n"); + + printf("Waiting Queue entries: "); + scb_index = ahc_inb(ahc, WAITING_SCBH); + i = 0; + while (scb_index != SCB_LIST_NULL && i++ < 256) { + ahc_outb(ahc, SCBPTR, scb_index); + printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); + scb_index = ahc_inb(ahc, SCB_NEXT); + } + printf("\n"); + + printf("Disconnected Queue entries: "); + scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); + i = 0; + while (scb_index != SCB_LIST_NULL && i++ < 256) { + ahc_outb(ahc, SCBPTR, scb_index); + printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); + scb_index = ahc_inb(ahc, SCB_NEXT); + } + printf("\n"); + + printf("QOUTFIFO entries: "); + qoutpos = ahc->qoutfifonext; + i = 0; + while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { + printf("%d ", ahc->qoutfifo[qoutpos]); + qoutpos++; + } + printf("\n"); + + printf("Sequencer Free SCB List: "); + scb_index = ahc_inb(ahc, FREE_SCBH); + i = 0; + while (scb_index != SCB_LIST_NULL && i++ < 256) { + ahc_outb(ahc, SCBPTR, scb_index); + printf("%d ", scb_index); + scb_index = ahc_inb(ahc, SCB_NEXT); + } + printf("\n"); + + printf("Pending list: "); + i = 0; + LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { + if (i++ > 256) + break; + printf("%d ", scb->hscb->tag); + } + printf("\n"); + + printf("Kernel Free SCB list: "); + i = 0; + SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { + if (i++ > 256) + break; + printf("%d ", scb->hscb->tag); + } + printf("\n"); + + maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; + for (target = 0; target <= maxtarget; target++) { + untagged_q = &ahc->untagged_queues[0]; + if (TAILQ_FIRST(untagged_q) == NULL) + continue; + printf("Untagged Q(%d): ", target); + i = 0; + TAILQ_FOREACH(scb, untagged_q, links.tqe) { + if (i++ > 256) + break; + printf("%d ", scb->hscb->tag); + } + printf("\n"); + } + + ahc_platform_dump_card_state(ahc); + ahc_outb(ahc, SCBPTR, saved_scbptr); +} + +/************************* Target Mode ****************************************/ +#ifdef AHC_TARGET_MODE +cam_status +ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, + struct tmode_tstate **tstate, struct tmode_lstate **lstate, + int notfound_failure) +{ + u_int our_id; + + /* + * If we are not configured for target mode, someone + * is really confused to be sending this to us. + */ + if ((ahc->flags & AHC_TARGETMODE) == 0) + return (CAM_REQ_INVALID); + + /* Range check target and lun */ + + /* + * Handle the 'black hole' device that sucks up + * requests to unattached luns on enabled targets. + */ + if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD + && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { + *tstate = NULL; + *lstate = ahc->black_hole; + } else { + u_int max_id; + + if (cam_sim_bus(sim) == 0) + our_id = ahc->our_id; + else + our_id = ahc->our_id_b; + + max_id = (ahc->features & AHC_WIDE) ? 15 : 7; + if (ccb->ccb_h.target_id > max_id) + return (CAM_TID_INVALID); + + if (ccb->ccb_h.target_lun > 7) + return (CAM_LUN_INVALID); + + if (ccb->ccb_h.target_id != our_id) { + if ((ahc->features & AHC_MULTI_TID) != 0) { + /* + * Only allow additional targets if + * the initiator role is disabled. + * The hardware cannot handle a re-select-in + * on the initiator id during a re-select-out + * on a different target id. + */ + if ((ahc->flags & AHC_INITIATORMODE) != 0) + return (CAM_TID_INVALID); + } else { + /* + * Only allow our target id to change + * if the initiator role is not configured + * and there are no enabled luns which + * are attached to the currently registered + * scsi id. + */ + if ((ahc->flags & AHC_INITIATORMODE) != 0 + || ahc->enabled_luns > 0) + return (CAM_TID_INVALID); + } + } + + *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; + *lstate = NULL; + if (*tstate != NULL) + *lstate = + (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; + } + + if (notfound_failure != 0 && *lstate == NULL) + return (CAM_PATH_INVALID); + + return (CAM_REQ_CMP); +} + +void +ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) +{ + struct tmode_tstate *tstate; + struct tmode_lstate *lstate; + struct ccb_en_lun *cel; + cam_status status; + u_int target; + u_int lun; + u_int target_mask; + u_long s; + char channel; + + status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, + /* notfound_failure*/FALSE); + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; + return; + } + + cel = &ccb->cel; + target = ccb->ccb_h.target_id; + lun = ccb->ccb_h.target_lun; + channel = SIM_CHANNEL(ahc, sim); + target_mask = 0x01 << target; + if (channel == 'B') + target_mask <<= 8; + + if (cel->enable != 0) { + u_int scsiseq; + + /* Are we already enabled?? */ + if (lstate != NULL) { + xpt_print_path(ccb->ccb_h.path); + printf("Lun already enabled\n"); + ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; + return; + } + + if (cel->grp6_len != 0 + || cel->grp7_len != 0) { + /* + * Don't (yet?) support vendor + * specific commands. + */ + ccb->ccb_h.status = CAM_REQ_INVALID; + printf("Non-zero Group Codes\n"); + return; + } + + /* + * Seems to be okay. + * Setup our data structures. + */ + if (target != CAM_TARGET_WILDCARD && tstate == NULL) { + tstate = ahc_alloc_tstate(ahc, target, channel); + if (tstate == NULL) { + xpt_print_path(ccb->ccb_h.path); + printf("Couldn't allocate tstate\n"); + ccb->ccb_h.status = CAM_RESRC_UNAVAIL; + return; + } + } + lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); + if (lstate == NULL) { + xpt_print_path(ccb->ccb_h.path); + printf("Couldn't allocate lstate\n"); + ccb->ccb_h.status = CAM_RESRC_UNAVAIL; + return; + } + memset(lstate, 0, sizeof(*lstate)); + status = xpt_create_path(&lstate->path, /*periph*/NULL, + xpt_path_path_id(ccb->ccb_h.path), + xpt_path_target_id(ccb->ccb_h.path), + xpt_path_lun_id(ccb->ccb_h.path)); + if (status != CAM_REQ_CMP) { + free(lstate, M_DEVBUF); + xpt_print_path(ccb->ccb_h.path); + printf("Couldn't allocate path\n"); + ccb->ccb_h.status = CAM_RESRC_UNAVAIL; + return; + } + SLIST_INIT(&lstate->accept_tios); + SLIST_INIT(&lstate->immed_notifies); + ahc_lock(ahc, &s); + pause_sequencer(ahc); + if (target != CAM_TARGET_WILDCARD) { + tstate->enabled_luns[lun] = lstate; + ahc->enabled_luns++; + + if ((ahc->features & AHC_MULTI_TID) != 0) { + u_int targid_mask; + + targid_mask = ahc_inb(ahc, TARGID) + | (ahc_inb(ahc, TARGID + 1) << 8); + + targid_mask |= target_mask; + ahc_outb(ahc, TARGID, targid_mask); + ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); + + ahc_update_scsiid(ahc, targid_mask); + } else { + u_int our_id; + char channel; + + channel = SIM_CHANNEL(ahc, sim); + our_id = SIM_SCSI_ID(ahc, sim); + + /* + * This can only happen if selections + * are not enabled + */ + if (target != our_id) { + u_int sblkctl; + char cur_channel; + int swap; + + sblkctl = ahc_inb(ahc, SBLKCTL); + cur_channel = (sblkctl & SELBUSB) + ? 'B' : 'A'; + if ((ahc->features & AHC_TWIN) == 0) + cur_channel = 'A'; + swap = cur_channel != channel; + if (channel == 'A') + ahc->our_id = target; + else + ahc->our_id_b = target; + + if (swap) + ahc_outb(ahc, SBLKCTL, + sblkctl ^ SELBUSB); + + ahc_outb(ahc, SCSIID, target); + + if (swap) + ahc_outb(ahc, SBLKCTL, sblkctl); + } + } + } else + ahc->black_hole = lstate; + /* Allow select-in operations */ + if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { + scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); + scsiseq |= ENSELI; + ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); + scsiseq = ahc_inb(ahc, SCSISEQ); + scsiseq |= ENSELI; + ahc_outb(ahc, SCSISEQ, scsiseq); + } + unpause_sequencer(ahc); + ahc_unlock(ahc, &s); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_print_path(ccb->ccb_h.path); + printf("Lun now enabled for target mode\n"); + } else { + struct scb *scb; + int i, empty; + + if (lstate == NULL) { + ccb->ccb_h.status = CAM_LUN_INVALID; + return; + } + + ahc_lock(ahc, &s); + + ccb->ccb_h.status = CAM_REQ_CMP; + LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { + struct ccb_hdr *ccbh; + + ccbh = &scb->io_ctx->ccb_h; + if (ccbh->func_code == XPT_CONT_TARGET_IO + && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ + printf("CTIO pending\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + ahc_unlock(ahc, &s); + return; + } + } + + if (SLIST_FIRST(&lstate->accept_tios) != NULL) { + printf("ATIOs pending\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + } + + if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { + printf("INOTs pending\n"); + ccb->ccb_h.status = CAM_REQ_INVALID; + } + + if (ccb->ccb_h.status != CAM_REQ_CMP) { + ahc_unlock(ahc, &s); + return; + } + + xpt_print_path(ccb->ccb_h.path); + printf("Target mode disabled\n"); + xpt_free_path(lstate->path); + free(lstate, M_DEVBUF); + + pause_sequencer(ahc); + /* Can we clean up the target too? */ + if (target != CAM_TARGET_WILDCARD) { + tstate->enabled_luns[lun] = NULL; + ahc->enabled_luns--; + for (empty = 1, i = 0; i < 8; i++) + if (tstate->enabled_luns[i] != NULL) { + empty = 0; + break; + } + + if (empty) { + ahc_free_tstate(ahc, target, channel, + /*force*/FALSE); + if (ahc->features & AHC_MULTI_TID) { + u_int targid_mask; + + targid_mask = ahc_inb(ahc, TARGID) + | (ahc_inb(ahc, TARGID + 1) + << 8); + + targid_mask &= ~target_mask; + ahc_outb(ahc, TARGID, targid_mask); + ahc_outb(ahc, TARGID+1, + (targid_mask >> 8)); + ahc_update_scsiid(ahc, targid_mask); + } + } + } else { + + ahc->black_hole = NULL; + + /* + * We can't allow selections without + * our black hole device. + */ + empty = TRUE; + } + if (ahc->enabled_luns == 0) { + /* Disallow select-in */ + u_int scsiseq; + + scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); + scsiseq &= ~ENSELI; + ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); + scsiseq = ahc_inb(ahc, SCSISEQ); + scsiseq &= ~ENSELI; + ahc_outb(ahc, SCSISEQ, scsiseq); + } + unpause_sequencer(ahc); + ahc_unlock(ahc, &s); + } +} + +static void +ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) +{ + u_int scsiid_mask; + u_int scsiid; + + if ((ahc->features & AHC_MULTI_TID) == 0) + panic("ahc_update_scsiid called on non-multitid unit\n"); + + /* + * Since we will rely on the the TARGID mask + * for selection enables, ensure that OID + * in SCSIID is not set to some other ID + * that we don't want to allow selections on. + */ + if ((ahc->features & AHC_ULTRA2) != 0) + scsiid = ahc_inb(ahc, SCSIID_ULTRA2); + else + scsiid = ahc_inb(ahc, SCSIID); + scsiid_mask = 0x1 << (scsiid & OID); + if ((targid_mask & scsiid_mask) == 0) { + u_int our_id; + + /* ffs counts from 1 */ + our_id = ffs(targid_mask); + if (our_id == 0) + our_id = ahc->our_id; + else + our_id--; + scsiid &= TID; + scsiid |= our_id; + } + if ((ahc->features & AHC_ULTRA2) != 0) + ahc_outb(ahc, SCSIID_ULTRA2, scsiid); + else + ahc_outb(ahc, SCSIID, scsiid); +} + +void +ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) +{ + struct target_cmd *cmd; + + /* + * If the card supports auto-access pause, + * we can access the card directly regardless + * of whether it is paused or not. + */ + if ((ahc->features & AHC_AUTOPAUSE) != 0) + paused = TRUE; + + while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { + + /* + * Only advance through the queue if we + * have the resources to process the command. + */ + if (ahc_handle_target_cmd(ahc, cmd) != 0) + break; + + ahc->tqinfifonext++; + cmd->cmd_valid = 0; + + /* + * Lazily update our position in the target mode incomming + * command queue as seen by the sequencer. + */ + if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { + if ((ahc->features & AHC_HS_MAILBOX) != 0) { + u_int hs_mailbox; + + hs_mailbox = ahc_inb(ahc, HS_MAILBOX); + hs_mailbox &= ~HOST_TQINPOS; + hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; + ahc_outb(ahc, HS_MAILBOX, hs_mailbox); + } else { + if (!paused) + pause_sequencer(ahc); + ahc_outb(ahc, KERNEL_TQINPOS, + ahc->tqinfifonext & HOST_TQINPOS); + if (!paused) + unpause_sequencer(ahc); + } + } + } +} + +static int +ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) +{ + struct tmode_tstate *tstate; + struct tmode_lstate *lstate; + struct ccb_accept_tio *atio; + uint8_t *byte; + int initiator; + int target; + int lun; + + initiator = SCSIID_TARGET(ahc, cmd->scsiid); + target = SCSIID_OUR_ID(cmd->scsiid); + lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); + + byte = cmd->bytes; + tstate = ahc->enabled_targets[target]; + lstate = NULL; + if (tstate != NULL) + lstate = tstate->enabled_luns[lun]; + + /* + * Commands for disabled luns go to the black hole driver. + */ + if (lstate == NULL) + lstate = ahc->black_hole; + + atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); + if (atio == NULL) { + ahc->flags |= AHC_TQINFIFO_BLOCKED; + /* + * Wait for more ATIOs from the peripheral driver for this lun. + */ + return (1); + } else + ahc->flags &= ~AHC_TQINFIFO_BLOCKED; +#if 0 + printf("Incoming command from %d for %d:%d%s\n", + initiator, target, lun, + lstate == ahc->black_hole ? "(Black Holed)" : ""); +#endif + SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); + + if (lstate == ahc->black_hole) { + /* Fill in the wildcards */ + atio->ccb_h.target_id = target; + atio->ccb_h.target_lun = lun; + } + + /* + * Package it up and send it off to + * whomever has this lun enabled. + */ + atio->sense_len = 0; + atio->init_id = initiator; + if (byte[0] != 0xFF) { + /* Tag was included */ + atio->tag_action = *byte++; + atio->tag_id = *byte++; + atio->ccb_h.flags = CAM_TAG_ACTION_VALID; + } else { + atio->ccb_h.flags = 0; + } + byte++; + + /* Okay. Now determine the cdb size based on the command code */ + switch (*byte >> CMD_GROUP_CODE_SHIFT) { + case 0: + atio->cdb_len = 6; + break; + case 1: + case 2: + atio->cdb_len = 10; + break; + case 4: + atio->cdb_len = 16; + break; + case 5: + atio->cdb_len = 12; + break; + case 3: + default: + /* Only copy the opcode. */ + atio->cdb_len = 1; + printf("Reserved or VU command code type encountered\n"); + break; + } + + memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); + + atio->ccb_h.status |= CAM_CDB_RECVD; + + if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { + /* + * We weren't allowed to disconnect. + * We're hanging on the bus until a + * continue target I/O comes in response + * to this accept tio. + */ +#if 0 + printf("Received Immediate Command %d:%d:%d - %p\n", + initiator, target, lun, ahc->pending_device); +#endif + ahc->pending_device = lstate; + ahc_freeze_ccb((union ccb *)atio); + atio->ccb_h.flags |= CAM_DIS_DISCONNECT; + } + xpt_done((union ccb*)atio); + return (0); +} + +#endif diff --git a/sys/dev/aic7xxx/aic7xxx.h b/sys/dev/aic7xxx/aic7xxx.h index c146a5b3a7e8..09d71cb697ab 100644 --- a/sys/dev/aic7xxx/aic7xxx.h +++ b/sys/dev/aic7xxx/aic7xxx.h @@ -1,7 +1,5 @@ /* - * Interface to the generic driver for the aic7xxx based adaptec - * SCSI controllers. This is used to implement product specific - * probe and attach routines. + * Core definitions and data structures shareable across OS platforms. * * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. * All rights reserved. @@ -30,17 +28,22 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $Id$ + * * $FreeBSD$ */ #ifndef _AIC7XXX_H_ #define _AIC7XXX_H_ -#include "opt_aic7xxx.h" /* for config options */ +/* Register Definitions */ #include "aic7xxx_reg.h" -#include <sys/bus.h> /* For device_t */ +/************************* Forward Declarations *******************************/ +struct ahc_platform_data; +struct scb_platform_data; +/****************************** Useful Macros *********************************/ #ifndef MAX #define MAX(a,b) (((a) > (b)) ? (a) : (b)) #endif @@ -49,6 +52,50 @@ #define MIN(a,b) (((a) < (b)) ? (a) : (b)) #endif +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) + +#define ALL_CHANNELS '\0' +#define ALL_TARGETS_MASK 0xFFFF +#define INITIATOR_WILDCARD (~0) + +#define SCSIID_TARGET(ahc, scsiid) \ + (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ + >> TID_SHIFT) +#define SCSIID_OUR_ID(scsiid) \ + ((scsiid) & OID) +#define SCSIID_CHANNEL(ahc, scsiid) \ + ((((ahc)->features & AHC_TWIN) != 0) \ + ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ + : 'A') +#define SCB_IS_SCSIBUS_B(ahc, scb) \ + (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') +#define SCB_GET_OUR_ID(scb) \ + SCSIID_OUR_ID((scb)->hscb->scsiid) +#define SCB_GET_TARGET(ahc, scb) \ + SCSIID_TARGET((ahc), (scb)->hscb->scsiid) +#define SCB_GET_CHANNEL(ahc, scb) \ + SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) +#define SCB_GET_LUN(scb) \ + ((scb)->hscb->lun) +#define SCB_GET_TARGET_OFFSET(ahc, scb) \ + (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) +#define SCB_GET_TARGET_MASK(ahc, scb) \ + (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) +#define TCL_TARGET_OFFSET(tcl) \ + ((((tcl) >> 4) & TID) >> 4) +#define TCL_LUN(tcl) \ + (tcl & (AHC_NUM_LUNS - 1)) +#define BUILD_TCL(scsiid, lun) \ + ((lun) | (((scsiid) & TID) << 4)) + +/**************************** Driver Constants ********************************/ /* * The maximum number of supported targets. */ @@ -56,9 +103,12 @@ /* * The maximum number of supported luns. - * The identify message supports up to 64 luns in SPI3. + * Although the identify message only supports 64 luns in SPI3, you + * can have 2^64 luns when information unit transfers are enabled. + * The max we can do sanely given the 8bit nature of the RISC engine + * on these chips is 256. */ -#define AHC_NUM_LUNS 64 +#define AHC_NUM_LUNS 256 /* * The maximum transfer per S/G segment. @@ -66,51 +116,30 @@ #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ /* - * The number of dma segments supported. The sequencer can handle any number - * of physically contiguous S/G entrys. To reduce the driver's memory - * consumption, we limit the number supported to be sufficient to handle - * the largest mapping supported by the kernel, MAXPHYS. Assuming the - * transfer is as fragmented as possible and unaligned, this turns out to - * be the number of paged sized transfers in MAXPHYS plus an extra element - * to handle any unaligned residual. The sequencer fetches SG elements - * in 128 byte chucks, so make the number per-transaction a nice multiple - * of 16 (8 byte S/G elements). - */ -/* XXX Worth the space??? */ -#define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16)) - -#define AHC_SCB_MAX 255 /* - * Up to 255 SCBs on some types of aic7xxx - * based boards. The aic7870 have 16 internal - * SCBs, but external SRAM bumps this to 255. - * The aic7770 family have only 4, and the - * aic7850 has only 3. - */ - -#define AHC_TMODE_CMDS 256 /* - * Ring Buffer of incoming target commands. - * We allocate 256 to simplify the logic - * in the sequencer by using the natural - * wrap point of an 8bit counter. - */ + * The maximum number of concurrent transactions supported per driver instance. + * Sequencer Control Blocks (SCBs) store per-transaction information. Although + * the space for SCBs on the host adapter varies by model, the driver will + * page the SCBs between host and controller memory as needed. We are limited + * to 255 because of the 8bit nature of the RISC engine and the need to + * reserve the value of 255 as a "No Transaction" value. + */ +#define AHC_SCB_MAX 255 /* - * The aic7xxx chips only support a 24bit length. We use the top - * byte of the length to store additional address bits as well - * as an indicator if this is the last SG segment in a transfer. - * This gives us an addressable range of 512GB on machines with - * 64bit PCI or with chips that can support dual address cycles - * on 32bit PCI busses. + * Ring Buffer of incoming target commands. + * We allocate 256 to simplify the logic in the sequencer + * by using the natural wrap point of an 8bit counter. */ -struct ahc_dma_seg { - uint32_t addr; - uint32_t len; -#define AHC_DMA_LAST_SEG 0x80000000 -#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 -#define AHC_SG_LEN_MASK 0x00FFFFFF -}; +#define AHC_TMODE_CMDS 256 + +/* Reset line assertion time in us */ +#define AHC_BUSRESET_DELAY 250 -/* The chip order is from least sophisticated to most sophisticated */ +/******************* Chip Characteristics/Operating Settings *****************/ +/* + * Chip Type + * The chip order is from least sophisticated to most sophisticated. + */ typedef enum { AHC_NONE = 0x0000, AHC_CHIPID_MASK = 0x00FF, @@ -122,53 +151,59 @@ typedef enum { AHC_AIC7870 = 0x0006, AHC_AIC7880 = 0x0007, AHC_AIC7895 = 0x0008, - AHC_AIC7890 = 0x0009, - AHC_AIC7896 = 0x000a, - AHC_AIC7892 = 0x000b, - AHC_AIC7899 = 0x000c, + AHC_AIC7895C = 0x0009, + AHC_AIC7890 = 0x000a, + AHC_AIC7896 = 0x000b, + AHC_AIC7892 = 0x000c, + AHC_AIC7899 = 0x000d, AHC_VL = 0x0100, /* Bus type VL */ AHC_EISA = 0x0200, /* Bus type EISA */ AHC_PCI = 0x0400, /* Bus type PCI */ AHC_BUS_MASK = 0x0F00 } ahc_chip; -extern char *ahc_chip_names[]; - +/* + * Features available in each chip type. + */ typedef enum { - AHC_FENONE = 0x0000, - AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ - AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ - AHC_WIDE = 0x0004, /* Wide Channel */ - AHC_TWIN = 0x0008, /* Twin Channel */ - AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ - AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ - AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ - AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ - AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ - AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ - AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ - AHC_DT = 0x0800, /* Double Transition transfers */ - AHC_NEW_TERMCTL = 0x1000, - AHC_MULTI_FUNC = 0x2000, /* Multi-Function Twin Channel Device */ - AHC_LARGE_SCBS = 0x4000, /* 64byte SCBs */ + AHC_FENONE = 0x00000, + AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ + AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ + AHC_WIDE = 0x00004, /* Wide Channel */ + AHC_TWIN = 0x00008, /* Twin Channel */ + AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ + AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ + AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ + AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ + AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ + AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ + AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ + AHC_DT = 0x00800, /* Double Transition transfers */ + AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ + AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ + AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ + AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ + AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ AHC_AIC7770_FE = AHC_FENONE, - AHC_AIC7850_FE = AHC_SPIOCAP, + AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE, AHC_AIC7855_FE = AHC_AIC7850_FE, - AHC_AIC7859_FE = AHC_AIC7850_FE|AHC_ULTRA, - AHC_AIC7860_FE = AHC_AIC7859_FE, + AHC_AIC7860_FE = AHC_AIC7850_FE|AHC_ULTRA, AHC_AIC7870_FE = AHC_FENONE, AHC_AIC7880_FE = AHC_ULTRA, AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX |AHC_NEW_TERMCTL|AHC_LARGE_SCBS, - AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT, - AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM + AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, + AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC } ahc_feature; +/* + * Bugs in the silicon that we work around in software. + */ typedef enum { AHC_BUGNONE = 0x00, /* @@ -184,17 +219,38 @@ typedef enum { */ AHC_AUTOFLUSH_BUG = 0x02, /* - * On the aic7890/91 Rev 0 chips, cacheline - * streaming does not work. + * On many chips, cacheline streaming does not work. */ AHC_CACHETHEN_BUG = 0x04, /* * On the aic7896/97 chips, cacheline * streaming must be enabled. */ - AHC_CACHETHEN_DIS_BUG = 0x08 + AHC_CACHETHEN_DIS_BUG = 0x08, + /* + * PCI 2.1 Retry failure on non-empty data fifo. + */ + AHC_PCI_2_1_RETRY_BUG = 0x10, + /* + * Controller does not handle cacheline residuals + * properly on S/G segments if PCI MWI instructions + * are allowed. + */ + AHC_PCI_MWI_BUG = 0x20, + /* + * An SCB upload using the SCB channel's + * auto array entry copy feature may + * corrupt data. This appears to only + * occur on 66MHz systems. + */ + AHC_SCBCHAN_UPLOAD_BUG = 0x40 } ahc_bug; +/* + * Configuration specific settings. + * The driver determines these settings by probing the + * chip/controller's configuration. + */ typedef enum { AHC_FNONE = 0x000, AHC_PAGESCBS = 0x001,/* Enable SCB paging */ @@ -232,13 +288,17 @@ typedef enum { * Internal 50pin connector * sits behind an aic3860 */ - AHC_SCB_BTT = 0x40000 /* + AHC_SCB_BTT = 0x40000,/* * The busy targets table is * stored in SCB space rather * than SRAM. */ + AHC_BIOS_ENABLED = 0x80000 } ahc_flag; +/* + * Controller Information composed at probe time. + */ struct ahc_probe_config { const char *description; char channel; @@ -249,25 +309,7 @@ struct ahc_probe_config { ahc_flag flags; }; -typedef enum { - SCB_FREE = 0x0000, - SCB_OTHERTCL_TIMEOUT = 0x0002,/* - * Another device was active - * during the first timeout for - * this SCB so we gave ourselves - * an additional timeout period - * in case it was hogging the - * bus. - */ - SCB_DEVICE_RESET = 0x0004, - SCB_SENSE = 0x0008, - SCB_RECOVERY_SCB = 0x0040, - SCB_NEGOTIATE = 0x0080, - SCB_ABORT = 0x1000, - SCB_QUEUED_MSG = 0x2000, - SCB_ACTIVE = 0x4000, - SCB_TARGET_IMMEDIATE = 0x8000 -} scb_flag; +/************************* Hardware SCB Definition ***************************/ /* * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB @@ -277,7 +319,7 @@ typedef enum { * To minimize space utilization, a portion of the hardware scb stores * different data during different portions of a SCSI transaction. * As initialized by the host driver for the initiator role, this area - * contains the SCSI cdb (or pointer to the cdb) to be executed. After + * contains the SCSI cdb (or a pointer to the cdb) to be executed. After * the cdb has been presented to the target, this area serves to store * residual transfer information and the SCSI status byte. * For the target role, the contents of this area do not change, but @@ -285,28 +327,35 @@ typedef enum { * struct target_data for details. */ +/* + * Status information embedded in the shared poriton of + * an SCB after passing the cdb to the target. The kernel + * driver will only read this data for transactions that + * complete abnormally (non-zero status byte). + */ struct status_pkt { - uint32_t residual_datacnt; - uint32_t residual_sg_ptr; - uint8_t scsi_status; + uint32_t residual_datacnt; /* Residual in the current S/G seg */ + uint32_t residual_sg_ptr; /* The next S/G for this transfer */ + uint8_t scsi_status; /* Standard SCSI status byte */ }; +/* + * Target mode version of the shared data SCB segment. + */ struct target_data { - uint8_t target_phases; - uint8_t data_phase; - uint8_t scsi_status; - uint8_t initiator_tag; + uint8_t target_phases; /* Bitmap of phases to execute */ + uint8_t data_phase; /* Data-In or Data-Out */ + uint8_t scsi_status; /* SCSI status to give to initiator */ + uint8_t initiator_tag; /* Initiator's transaction tag */ }; struct hardware_scb { -/*0*/ uint8_t control; -/*1*/ uint8_t scsiid; /* what to load in the SCSIID register */ -/*2*/ uint8_t lun; -/*3*/ uint8_t cdb_len; -/*4*/ union { +/*0*/ union { /* - * 12 bytes of cdb information only - * used on chips with 32byte SCBs. + * If the cdb is 12 bytes or less, we embed it directly + * in the SCB. For longer cdbs, we embed the address + * of the cdb payload as seen by the chip and a DMA + * is used to pull it in. */ uint8_t cdb[12]; uint32_t cdb_ptr; @@ -314,22 +363,25 @@ struct hardware_scb { struct target_data tdata; } shared_data; /* - * A word about residuals. The scb is presented to the sequencer with - * the dataptr and datacnt fields initialized to the contents of the - * first S/G element to transfer. The sgptr field is initialized to - * the bus address for the S/G element that follows the first in the - * in core S/G array or'ed with the SG_FULL_RESID flag. Sgptr may point - * to an invalid S/G entry for this transfer. If no transfer is to occur, - * sgptr is set to SG_LIST_NULL. The SG_FULL_RESID flag insures that - * the residual will be correctly noted even if no data transfers occur. - * Once the data phase is entered, the residual sgptr and datacnt are - * loaded from the sgptr and the datacnt fields. After each S/G element's - * dataptr and length are loaded into the hardware, the residual sgptr - * is advanced. After each S/G element is expired, its datacnt field - * is checked to see if the LAST_SEG flag is set. If so, SG_LIST_NULL - * is set in the residual sg ptr and the transfer is considered complete. - * If the sequencer determines that three is a residual in the tranfer, - * it will set the SG_RESID_VALID flag in sgptr and dma the scb back into + * A word about residuals. + * The scb is presented to the sequencer with the dataptr and datacnt + * fields initialized to the contents of the first S/G element to + * transfer. The sgptr field is initialized to the bus address for + * the S/G element that follows the first in the in core S/G array + * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid + * S/G entry for this transfer (single S/G element transfer with the + * first elements address and length preloaded in the dataptr/datacnt + * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. + * The SG_FULL_RESID flag ensures that the residual will be correctly + * noted even if no data transfers occur. Once the data phase is entered, + * the residual sgptr and datacnt are loaded from the sgptr and the + * datacnt fields. After each S/G element's dataptr and length are + * loaded into the hardware, the residual sgptr is advanced. After + * each S/G element is expired, its datacnt field is checked to see + * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the + * residual sg ptr and the transfer is considered complete. If the + * sequencer determines that there is a residual in the tranfer, it + * will set the SG_RESID_VALID flag in sgptr and dma the scb back into * host memory. To sumarize: * * Sequencer: @@ -347,58 +399,165 @@ struct hardware_scb { * and so may point beyond the last valid sg entry for the * transfer. */ -/*16*/ uint32_t dataptr; -/*20*/ uint32_t datacnt; /* - * The highest address byte is - * really the 5th. byte in the - * dataptr. +/*12*/ uint32_t dataptr; +/*16*/ uint32_t datacnt; /* + * Byte 3 (numbered from 0) of + * the datacnt is really the + * 4th byte in that data address. */ -/*24*/ uint32_t sgptr; +/*20*/ uint32_t sgptr; #define SG_PTR_MASK 0xFFFFFFF8 -/*28*/ uint8_t tag; /* Index into our kernel SCB array. +/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ +/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ +/*26*/ uint8_t lun; +/*27*/ uint8_t tag; /* + * Index into our kernel SCB array. * Also used as the tag for tagged I/O */ +/*28*/ uint8_t cdb_len; /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ -/*31*/ uint8_t next; /* Used for threading SCBs in the +/*31*/ uint8_t next; /* + * Used for threading SCBs in the * "Waiting for Selection" and * "Disconnected SCB" lists down * in the sequencer. */ /*32*/ uint8_t cdb32[32]; /* - * CDB storage for controllers - * supporting 64 byte SCBs. + * CDB storage for cdbs of size + * 13->32. We store them here + * because hardware scbs are + * allocated from DMA safe + * memory so we are guaranteed + * the controller can access + * this data. */ }; +/************************ Kernel SCB Definitions ******************************/ +/* + * Some fields of the SCB are OS dependent. Here we collect the + * definitions for elements that all OS platforms need to include + * in there SCB definition. + */ + +/* + * Definition of a scatter/gather element as transfered to the controller. + * The aic7xxx chips only support a 24bit length. We use the top byte of + * the length to store additional address bits and a flag to indicate + * that a given segment terminates the transfer. This gives us an + * addressable range of 512GB on machines with 64bit PCI or with chips + * that can support dual address cycles on 32bit PCI busses. + */ +struct ahc_dma_seg { + uint32_t addr; + uint32_t len; +#define AHC_DMA_LAST_SEG 0x80000000 +#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 +#define AHC_SG_LEN_MASK 0x00FFFFFF +}; + +/* + * The current state of this SCB. + */ +typedef enum { + SCB_FREE = 0x0000, + SCB_OTHERTCL_TIMEOUT = 0x0002,/* + * Another device was active + * during the first timeout for + * this SCB so we gave ourselves + * an additional timeout period + * in case it was hogging the + * bus. + */ + SCB_DEVICE_RESET = 0x0004, + SCB_SENSE = 0x0008, + SCB_RECOVERY_SCB = 0x0040, + SCB_NEGOTIATE = 0x0080, + SCB_ABORT = 0x1000, + SCB_QUEUED_MSG = 0x2000, + SCB_ACTIVE = 0x4000, + SCB_TARGET_IMMEDIATE = 0x8000 +} scb_flag; + struct scb { - struct hardware_scb *hscb; + struct hardware_scb *hscb; union { - SLIST_ENTRY(scb) sle; - TAILQ_ENTRY(scb) tqe; + SLIST_ENTRY(scb) sle; + TAILQ_ENTRY(scb) tqe; } links; - union ccb *ccb; /* the ccb for this cmd */ - scb_flag flags; - bus_dmamap_t dmamap; - struct ahc_dma_seg *sg_list; - bus_addr_t sg_list_phys; - bus_addr_t cdb32_busaddr; - u_int sg_count;/* How full ahc_dma_seg is */ + LIST_ENTRY(scb) pending_links; + ahc_io_ctx_t io_ctx; + scb_flag flags; +#ifndef __linux__ + bus_dmamap_t dmamap; +#endif + struct scb_platform_data *platform_data; + struct ahc_dma_seg *sg_list; + bus_addr_t sg_list_phys; + bus_addr_t cdb32_busaddr; + u_int sg_count;/* How full ahc_dma_seg is */ +}; + +struct sg_map_node { + bus_dmamap_t sg_dmamap; + bus_addr_t sg_physaddr; + struct ahc_dma_seg* sg_vaddr; + SLIST_ENTRY(sg_map_node) links; +}; + +struct scb_data { + struct hardware_scb *hscbs; /* Array of hardware SCBs */ + struct scb *scbarray; /* Array of kernel SCBs */ + SLIST_HEAD(, scb) free_scbs; /* + * Pool of SCBs ready to be assigned + * commands to execute. + */ + struct scsi_sense_data *sense; /* Per SCB sense data */ + + /* + * "Bus" addresses of our data structures. + */ + bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ + bus_dmamap_t hscb_dmamap; + bus_addr_t hscb_busaddr; + bus_dma_tag_t sense_dmat; + bus_dmamap_t sense_dmamap; + bus_addr_t sense_busaddr; + bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ + SLIST_HEAD(, sg_map_node) sg_maps; + uint8_t numscbs; + uint8_t maxhscbs; /* Number of SCBs on the card */ + uint8_t init_level; /* + * How far we've initialized + * this structure. + */ }; +/************************ Target Mode Definitions *****************************/ + /* * Connection desciptor for select-in requests in target mode. - * The first byte is the connecting target, followed by identify - * message and optional tag information, terminated by 0xFF. The - * remainder is the command to execute. The cmd_valid byte is on - * an 8 byte boundary to simplify setting it on aic7880 hardware - * which only has limited direct access to the DMA FIFO. */ struct target_cmd { - uint8_t scsiid; + uint8_t scsiid; /* Our ID and the initiator's ID */ uint8_t identify; /* Identify message */ - uint8_t bytes[22]; - uint8_t cmd_valid; + uint8_t bytes[22]; /* + * Bytes contains any additional message + * bytes terminated by 0xFF. The remainder + * is the cdb to execute. + */ + uint8_t cmd_valid; /* + * When a command is complete, the firmware + * will set cmd_valid to all bits set. + * After the host has seen the command, + * the bits are cleared. This allows us + * to just peek at host memory to determine + * if more work is complete. cmd_valid is on + * an 8 byte boundary to simplify setting + * it on aic7880 hardware which only has + * limited direct access to the DMA FIFO. + */ uint8_t pad[7]; }; @@ -415,9 +574,13 @@ struct ahc_tmode_event { }; /* - * Per lun target mode state including accept TIO CCB - * and immediate notify CCB pools. + * Per enabled lun target mode state. + * As this state is directly influenced by the host OS'es target mode + * environment, we let the OS module define it. Forward declare the + * structure here so we can store arrays of them, etc. in OS neutral + * data structures. */ +#ifdef AHC_TARGET_MODE struct tmode_lstate { struct cam_path *path; struct ccb_hdr_slist accept_tios; @@ -426,36 +589,46 @@ struct tmode_lstate { uint8_t event_r_idx; uint8_t event_w_idx; }; +#else +struct tmode_lstate; +#endif +/******************** Transfer Negotiation Datastructures *********************/ #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ -#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ +#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ +/* + * Transfer Negotiation Information. + */ struct ahc_transinfo { - uint8_t protocol_version; - uint8_t transport_version; - uint8_t width; - uint8_t period; - uint8_t offset; - uint8_t ppr_options; + uint8_t protocol_version; /* SCSI Revision level */ + uint8_t transport_version; /* SPI Revision level */ + uint8_t width; /* Bus width */ + uint8_t period; /* Sync rate factor */ + uint8_t offset; /* Sync offset */ + uint8_t ppr_options; /* Parallel Protocol Request options */ }; +/* + * Per-initiator current, goal and user transfer negotiation information. */ struct ahc_initiator_tinfo { - uint8_t scsirate; + uint8_t scsirate; /* Computed value for SCSIRATE reg */ struct ahc_transinfo current; struct ahc_transinfo goal; struct ahc_transinfo user; }; /* - * Per target mode enabled target state. Esentially just an array of - * pointers to lun target state as well as sync/wide negotiation information - * for each initiator<->target mapping (including the mapping for when we - * are the initiator). + * Per enabled target ID state. + * Pointers to lun target state as well as sync/wide negotiation information + * for each initiator<->target mapping. For the initiator role we pretend + * that we are the target and the targets are the initiators since the + * negotiation is the same regardless of role. */ struct tmode_tstate { - struct tmode_lstate* enabled_luns[64]; + struct tmode_lstate* enabled_luns[64]; /* NULL == disabled */ struct ahc_initiator_tinfo transinfo[16]; /* @@ -467,12 +640,65 @@ struct tmode_tstate { }; /* - * Define the format of the aic7XXX SEEPROM registers (16 bits). + * Data structure for our table of allowed synchronous transfer rates. + */ +struct ahc_syncrate { + u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ + u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ +#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ +#define ST_SXFR 0x010 /* Rate Single Transition Only */ +#define DT_SXFR 0x040 /* Rate Double Transition Only */ + uint8_t period; /* Period to send to SCSI target */ + char *rate; +}; + +/* + * The synchronouse transfer rate table. + */ +extern struct ahc_syncrate ahc_syncrates[]; + +/* + * Indexes into our table of syncronous transfer rates. */ +#define AHC_SYNCRATE_DT 0 +#define AHC_SYNCRATE_ULTRA2 1 +#define AHC_SYNCRATE_ULTRA 3 +#define AHC_SYNCRATE_FAST 6 + +/***************************** Lookup Tables **********************************/ +/* + * Textual descriptions of the different chips indexed by chip type. + */ +extern char *ahc_chip_names[]; +extern const u_int num_chip_names; + +/* + * Hardware error codes. + */ +struct hard_error_entry { + uint8_t errno; + char *errmesg; +}; +extern struct hard_error_entry hard_error[]; +extern const u_int num_errors; + +/* + * Phase -> name and message out response + * to parity errors in each phase table. + */ +struct phase_table_entry { + uint8_t phase; + uint8_t mesg_out; /* Message response to parity errors */ + char *phasemsg; +}; +extern struct phase_table_entry phase_table[]; +extern const u_int num_phases; + +/************************** Serial EEPROM Format ******************************/ struct seeprom_config { /* - * SCSI ID Configuration Flags + * Per SCSI ID Configuration Flags */ uint16_t device_flags[16]; /* words 0-15 */ #define CFXFER 0x0007 /* synchronous transfer rate */ @@ -525,7 +751,7 @@ struct seeprom_config { #define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ /* - * Bus Release, Host Adapter ID + * Bus Release Time, Host Adapter ID */ uint16_t brtime_id; /* word 18 */ #define CFSCSIID 0x000f /* host adapter SCSI ID */ @@ -545,17 +771,7 @@ struct seeprom_config { uint16_t checksum; /* word 31 */ }; -struct ahc_syncrate { - u_int sxfr_u2; - u_int sxfr; - /* Rates in Ultra mode have bit 8 of sxfr set */ -#define ULTRA_SXFR 0x100 -#define ST_SXFR 0x010 /* Rate Single Transition Only */ -#define DT_SXFR 0x040 /* Rate Double Transition Only */ - uint8_t period; /* Period to send to SCSI target */ - char *rate; -}; - +/**************************** Message Buffer *********************************/ typedef enum { MSG_TYPE_NONE = 0x00, MSG_TYPE_INITIATOR_MSGOUT = 0x01, @@ -564,53 +780,27 @@ typedef enum { MSG_TYPE_TARGET_MSGIN = 0x04 } ahc_msg_type; -struct sg_map_node { - bus_dmamap_t sg_dmamap; - bus_addr_t sg_physaddr; - struct ahc_dma_seg* sg_vaddr; - SLIST_ENTRY(sg_map_node) links; -}; - -struct scb_data { - struct hardware_scb *hscbs; /* Array of hardware SCBs */ - struct scb *scbarray; /* Array of kernel SCBs */ - SLIST_HEAD(, scb) free_scbs; /* - * Pool of SCBs ready to be assigned - * commands to execute. - */ - struct scsi_sense_data *sense; /* Per SCB sense data */ - - /* - * "Bus" addresses of our data structures. - */ - bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ - bus_dmamap_t hscb_dmamap; - bus_addr_t hscb_busaddr; - bus_dma_tag_t sense_dmat; - bus_dmamap_t sense_dmamap; - bus_addr_t sense_busaddr; - bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ - SLIST_HEAD(, sg_map_node) sg_maps; - uint8_t numscbs; - uint8_t maxhscbs; /* Number of SCBs on the card */ - uint8_t init_level; /* - * How far we've initialized - * this structure. - */ -}; +typedef enum { + MSGLOOP_IN_PROG, + MSGLOOP_MSGCOMPLETE, + MSGLOOP_TERMINATED +} msg_loop_stat; +/*********************** Software Configuration Structure *********************/ TAILQ_HEAD(scb_tailq, scb); struct ahc_softc { - bus_space_tag_t tag; - bus_space_handle_t bsh; - bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ - struct scb_data *scb_data; + bus_space_tag_t tag; + bus_space_handle_t bsh; +#ifndef __linux__ + bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ +#endif + struct scb_data *scb_data; /* - * CCBs that have been sent to the controller + * SCBs that have been sent to the controller */ - LIST_HEAD(, ccb_hdr) pending_ccbs; + LIST_HEAD(, scb) pending_scbs; /* * Counting lock for deferring the release of additional @@ -618,7 +808,7 @@ struct ahc_softc { * the lock is decremented to 0, all queues in the * untagged_queues array are run. */ - u_int untagged_queue_lock; + u_int untagged_queue_lock; /* * Per-target queue of untagged-transactions. The @@ -627,7 +817,17 @@ struct ahc_softc { * target. The driver only allows a single untagged * transaction per target. */ - struct scb_tailq untagged_queues[16]; + struct scb_tailq untagged_queues[16]; + + /* + * Platform specific data. + */ + struct ahc_platform_data *platform_data; + + /* + * Platform specific device information. + */ + ahc_dev_softc_t dev_softc; /* * Target mode related state kept on a per enabled lun basis. @@ -635,193 +835,263 @@ struct ahc_softc { * As an initiator, we keep one target entry for our initiator * ID to store our sync/wide transfer settings. */ - struct tmode_tstate* enabled_targets[16]; + struct tmode_tstate* enabled_targets[16]; /* * The black hole device responsible for handling requests for * disabled luns on enabled targets. */ - struct tmode_lstate* black_hole; + struct tmode_lstate* black_hole; /* * Device instance currently on the bus awaiting a continue TIO * for a command that was not given the disconnect priveledge. */ - struct tmode_lstate* pending_device; + struct tmode_lstate* pending_device; /* * Card characteristics */ - ahc_chip chip; - ahc_feature features; - ahc_bug bugs; - ahc_flag flags; + ahc_chip chip; + ahc_feature features; + ahc_bug bugs; + ahc_flag flags; /* Values to store in the SEQCTL register for pause and unpause */ - uint8_t unpause; - uint8_t pause; + uint8_t unpause; + uint8_t pause; /* Command Queues */ - uint8_t qoutfifonext; - uint8_t qinfifonext; - uint8_t *qoutfifo; - uint8_t *qinfifo; - - /* - * Hooks into the XPT. - */ - struct cam_sim *sim; - struct cam_sim *sim_b; - struct cam_path *path; - struct cam_path *path_b; + uint8_t qoutfifonext; + uint8_t qinfifonext; + uint8_t *qoutfifo; + uint8_t *qinfifo; - int unit; + /* Links for chaining softcs */ + TAILQ_ENTRY(ahc_softc) links; /* Channel Names ('A', 'B', etc.) */ - char channel; - char channel_b; + char channel; + char channel_b; /* Initiator Bus ID */ - uint8_t our_id; - uint8_t our_id_b; + uint8_t our_id; + uint8_t our_id_b; /* Targets that need negotiation messages */ - uint16_t targ_msg_req; + uint16_t targ_msg_req; /* - * PCI error detection and data for running the - * PCI error interrupt handler. + * PCI error detection. */ - int unsolicited_ints; - device_t device; + int unsolicited_ints; /* * Target incoming command FIFO. */ - struct target_cmd *targetcmds; - uint8_t tqinfifonext; + struct target_cmd *targetcmds; + uint8_t tqinfifonext; /* * Incoming and outgoing message handling. */ - uint8_t send_msg_perror; - ahc_msg_type msg_type; - uint8_t msgout_buf[8]; /* Message we are sending */ - uint8_t msgin_buf[8]; /* Message we are receiving */ - u_int msgout_len; /* Length of message to send */ - u_int msgout_index; /* Current index in msgout */ - u_int msgin_index; /* Current index in msgin */ - - int regs_res_type; - int regs_res_id; - int irq_res_type; - struct resource *regs; - struct resource *irq; - void *ih; - bus_dma_tag_t parent_dmat; - bus_dma_tag_t shared_data_dmat; - bus_dmamap_t shared_data_dmamap; - bus_addr_t shared_data_busaddr; - bus_addr_t dma_bug_buf; + uint8_t send_msg_perror; + ahc_msg_type msg_type; + uint8_t msgout_buf[8];/* Message we are sending */ + uint8_t msgin_buf[8]; /* Message we are receiving */ + u_int msgout_len; /* Length of message to send */ + u_int msgout_index; /* Current index in msgout */ + u_int msgin_index; /* Current index in msgin */ - /* Number of enabled target mode device on this card */ - u_int enabled_luns; + /* + * Mapping information for data structures shared + * between the sequencer and kernel. + */ + bus_dma_tag_t parent_dmat; + bus_dma_tag_t shared_data_dmat; + bus_dmamap_t shared_data_dmamap; + bus_addr_t shared_data_busaddr; - /* Initialization level of this data structure */ - u_int init_level; + /* + * Bus address of the one byte buffer used to + * work-around a DMA bug for chips <= aic7880 + * in target mode. + */ + bus_addr_t dma_bug_buf; - uint16_t user_discenable;/* Disconnection allowed */ - uint16_t user_tagenable;/* Tagged Queuing allowed */ -}; + /* Number of enabled target mode device on this card */ + u_int enabled_luns; -struct full_ahc_softc { - struct ahc_softc softc; - struct scb_data scb_data_storage; -}; + /* Initialization level of this data structure */ + u_int init_level; -/* #define AHC_DEBUG */ -#ifdef AHC_DEBUG -/* Different debugging levels used when AHC_DEBUG is defined */ -#define AHC_SHOWMISC 0x0001 -#define AHC_SHOWCMDS 0x0002 -#define AHC_SHOWSCBS 0x0004 -#define AHC_SHOWABORTS 0x0008 -#define AHC_SHOWSENSE 0x0010 -#define AHC_SHOWSCBCNT 0x0020 - -extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ -#endif + /* PCI cacheline size. */ + u_int pci_cachesize; -#define ahc_inb(ahc, port) \ - bus_space_read_1((ahc)->tag, (ahc)->bsh, port) - -#define ahc_outb(ahc, port, value) \ - bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) - -#define ahc_outsb(ahc, port, valp, count) \ - bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) - -#define ahc_insb(ahc, port, valp, count) \ - bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) - -char *ahc_name(struct ahc_softc *ahc); - -void ahc_init_probe_config(struct ahc_probe_config *config); -struct ahc_softc* - ahc_alloc(device_t dev, struct resource *regs, int regs_type, - int regs_id, bus_dma_tag_t parent_dmat, - struct ahc_probe_config *config, struct scb_data *scb_data); -int ahc_reset(struct ahc_softc *ahc); -void ahc_free(struct ahc_softc *); -int ahc_probe_scbs(struct ahc_softc *); -int ahc_init(struct ahc_softc *); -int ahc_attach(struct ahc_softc *); -void ahc_intr(void *arg); -static __inline int sequencer_paused(struct ahc_softc *ahc); -static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); -static __inline void pause_sequencer(struct ahc_softc *ahc); -static __inline void unpause_sequencer(struct ahc_softc *ahc); - -static __inline void -ahc_pause_bug_fix(struct ahc_softc *ahc) -{ - /* - * Clear the CIOBUS stretch signal by reading a register that will - * set this signal and deassert it. Without this workaround, if - * the chip is paused, by an interrupt or manual pause, while - * accessing scb ram, then accesses to certain registers will hang - * the system (infinite pci retries). - */ - if ((ahc->features & AHC_ULTRA2) != 0) - (void)ahc_inb(ahc, CCSCBCTL); -} + /* Per-Unit descriptive information */ + const char *description; + char *name; + int unit; -static __inline int -sequencer_paused(struct ahc_softc *ahc) -{ - return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); -} + uint16_t user_discenable;/* Disconnection allowed */ + uint16_t user_tagenable;/* Tagged Queuing allowed */ +}; -static __inline void -pause_sequencer(struct ahc_softc *ahc) -{ - ahc_outb(ahc, HCNTRL, ahc->pause); +TAILQ_HEAD(ahc_softc_tailq, ahc_softc); +extern struct ahc_softc_tailq ahc_tailq; - /* - * Since the sequencer can disable pausing in a critical section, we - * must loop until it actually stops. - */ - while (sequencer_paused(ahc) == 0) - ; +/************************ Active Device Information ***************************/ +typedef enum { + ROLE_UNKNOWN, + ROLE_INITIATOR, + ROLE_TARGET +} role_t; + +struct ahc_devinfo { + int our_scsiid; + int target_offset; + uint16_t target_mask; + u_int target; + u_int lun; + char channel; + role_t role; /* + * Only guaranteed to be correct if not + * in the busfree state. + */ +}; - ahc_pause_bug_fix(ahc); -} +/****************************** PCI Structures ********************************/ +typedef int (ahc_device_setup_t)(ahc_dev_softc_t, + struct ahc_probe_config *); -static __inline void -unpause_sequencer(struct ahc_softc *ahc) -{ - if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) - ahc_outb(ahc, HCNTRL, ahc->unpause); -} +struct ahc_pci_identity { + uint64_t full_id; + uint64_t id_mask; + char *name; + ahc_device_setup_t *setup; +}; +extern struct ahc_pci_identity ahc_pci_ident_table []; +extern const int ahc_num_pci_devs; + +/***************************** VL/EISA Declarations ***************************/ +struct aic7770_identity { + uint32_t full_id; + uint32_t id_mask; + char *name; + ahc_device_setup_t *setup; +}; +extern struct aic7770_identity aic7770_ident_table []; +extern const int ahc_num_aic7770_devs; + +#define AHC_EISA_SLOT_OFFSET 0xc00 +#define AHC_EISA_IOSIZE 0x100 + +/*************************** Function Declarations ****************************/ +/******************************************************************************/ + +/***************************** PCI Front End *********************************/ +struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); +int ahc_pci_config(struct ahc_softc *, + struct ahc_pci_identity *); + +/*************************** EISA/VL Front End ********************************/ +struct aic7770_identity *aic7770_find_device(uint32_t); +int aic7770_config(struct ahc_softc *ahc, + struct aic7770_identity *); + +/************************** SCB and SCB queue management **********************/ +int ahc_probe_scbs(struct ahc_softc *); +void ahc_run_untagged_queues(struct ahc_softc *ahc); +void ahc_run_untagged_queue(struct ahc_softc *ahc, + struct scb_tailq *queue); + +/****************************** Initialization ********************************/ +void ahc_init_probe_config(struct ahc_probe_config *); +struct ahc_softc *ahc_alloc(void *platform_arg, char *name); +int ahc_softc_init(struct ahc_softc *, + struct ahc_probe_config*); +void ahc_controller_info(struct ahc_softc *ahc, char *buf); +int ahc_init(struct ahc_softc *ahc); +void ahc_softc_insert(struct ahc_softc *); +void ahc_set_unit(struct ahc_softc *, int); +void ahc_set_name(struct ahc_softc *, char *); +void ahc_alloc_scbs(struct ahc_softc *ahc); +void ahc_free(struct ahc_softc *ahc); +int ahc_reset(struct ahc_softc *ahc); +void ahc_shutdown(void *arg); + +/*************************** Interrupt Services *******************************/ +void ahc_pci_intr(struct ahc_softc *ahc); +void ahc_clear_intstat(struct ahc_softc *ahc); +void ahc_run_qoutfifo(struct ahc_softc *ahc); +#ifdef AHC_TARGET_MODE +void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); +#endif +void ahc_handle_brkadrint(struct ahc_softc *ahc); +void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); +void ahc_handle_scsiint(struct ahc_softc *ahc, + u_int intstat); -#endif /* _AIC7XXX_H_ */ +/***************************** Error Recovery *********************************/ +typedef enum { + SEARCH_COMPLETE, + SEARCH_COUNT, + SEARCH_REMOVE +} ahc_search_action; +int ahc_search_qinfifo(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status, + ahc_search_action action); +int ahc_search_disc_list(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + int stop_on_first, int remove, + int save_state); +void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); +int ahc_reset_channel(struct ahc_softc *ahc, char channel, + int initiate_reset); +void restart_sequencer(struct ahc_softc *ahc); +/*************************** Utility Functions ********************************/ +void ahc_compile_devinfo(struct ahc_devinfo *devinfo, + u_int our_id, u_int target, + u_int lun, char channel, + role_t role); +/************************** Transfer Negotiation ******************************/ +struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, + u_int *ppr_options, u_int maxsync); +u_int ahc_find_period(struct ahc_softc *ahc, + u_int scsirate, u_int maxsync); +void ahc_validate_offset(struct ahc_softc *ahc, + struct ahc_syncrate *syncrate, + u_int *offset, int wide); +void ahc_validate_width(struct ahc_softc *ahc, + u_int *bus_width); +void ahc_set_width(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + u_int width, u_int type, int paused); +void ahc_set_syncrate(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct ahc_syncrate *syncrate, + u_int period, u_int offset, + u_int ppr_options, + u_int type, int paused); +void ahc_set_tags(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, int enable); + +/**************************** Target Mode *************************************/ +#ifdef AHC_TARGET_MODE +void ahc_send_lstate_events(struct ahc_softc *, + struct tmode_lstate *); +void ahc_handle_en_lun(struct ahc_softc *ahc, + struct cam_sim *sim, union ccb *ccb); +cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, + struct cam_sim *sim, union ccb *ccb, + struct tmode_tstate **tstate, + struct tmode_lstate **lstate, + int notfound_failure); +void ahc_setup_target_msgin(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo); +#endif +/******************************* Debug ***************************************/ +void ahc_print_scb(struct scb *scb); +void ahc_dump_card_state(struct ahc_softc *ahc); +#endif /* _AIC7XXX_H_ */ diff --git a/sys/dev/aic7xxx/aic7xxx.reg b/sys/dev/aic7xxx/aic7xxx.reg index 8e1fd1b9b4cf..b3c19835d02b 100644 --- a/sys/dev/aic7xxx/aic7xxx.reg +++ b/sys/dev/aic7xxx/aic7xxx.reg @@ -28,6 +28,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $Id$ + * * $FreeBSD$ */ diff --git a/sys/dev/aic7xxx/aic7xxx.seq b/sys/dev/aic7xxx/aic7xxx.seq index 0103104eee06..b5e50f5b4ea8 100644 --- a/sys/dev/aic7xxx/aic7xxx.seq +++ b/sys/dev/aic7xxx/aic7xxx.seq @@ -28,6 +28,8 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $Id$ + * * $FreeBSD$ */ @@ -52,18 +54,6 @@ * automatically consume the entries. */ -reset: - clr SCSISIGO; /* De-assert BSY */ - mvi MSG_OUT, MSG_NOOP; /* No message to send */ - and SXFRCTL1, ~BITBUCKET; - /* Always allow reselection */ - and SCSISEQ, ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ_TEMPLATE; - if ((ahc->features & AHC_CMD_CHAN) != 0) { - /* Ensure that no DMA operations are in progress */ - clr CCSGCTL; - clr CCSCBCTL; - } - poll_for_work: call clear_target_state; and SXFRCTL0, ~SPIOEN; @@ -82,7 +72,7 @@ poll_for_work_loop: */ xor SBLKCTL,SELBUSB; /* Toggle to the other bus */ test SSTAT0, SELDO|SELDI jnz selection; - test SCSISEQ, ENSELO jnz poll_for_work_loop; + xor SBLKCTL,SELBUSB; /* Toggle back */ } cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting; test_queue: @@ -119,7 +109,6 @@ dma_queued_scb: */ mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET; mov RETURN_2 call dma_scb; - start_scb: /* * Place us on the waiting list in case our selection @@ -133,7 +122,7 @@ start_waiting: */ mov SCBPTR, WAITING_SCBH; call start_selection; - jmp poll_for_work; + jmp poll_for_work_loop; start_selection: if ((ahc->features & AHC_TWIN) != 0) { @@ -708,6 +697,40 @@ idle_sg_avail: ret; } +if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { +/* + * Calculate the trailing portion of this S/G segment that cannot + * be transferred using memory write and invalidate PCI transactions. + * XXX Can we optimize this for PCI writes only??? + */ +calc_mwi_residual: + /* + * If the ending address is on a cacheline boundary, + * there is no need for an extra segment. + */ + mov A, HCNT[0]; + add A, A, HADDR[0]; + and A, CACHESIZE_MASK; + test A, 0xFF jz return; + + /* + * If the transfer is less than a cachline, + * there is no need for an extra segment. + */ + test HCNT[1], 0xFF jnz calc_mwi_residual_final; + test HCNT[2], 0xFF jnz calc_mwi_residual_final; + add NONE, INVERTED_CACHESIZE_MASK, HCNT[0]; + jnc return; + +calc_mwi_residual_final: + mov MWI_RESIDUAL, A; + not A; + inc A; + add HCNT[0], A; + adc HCNT[1], -1; + adc HCNT[2], -1 ret; +} + /* * If we re-enter the data phase after going through another phase, the * STCNT may have been cleared, so restore it from the residual field. @@ -767,8 +790,11 @@ p_data: mvi DINDEX, SCB_RESIDUAL_DATACNT + 3; mvi SCB_DATACNT + 3 call bcopy_5; } + if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { + call calc_mwi_residual; + } and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID; - and DATA_COUNT_ODD, 0x1, SCB_DATACNT[0]; + and DATA_COUNT_ODD, 0x1, HCNT[0]; if ((ahc->features & AHC_ULTRA2) == 0) { if ((ahc->features & AHC_CMD_CHAN) != 0) { @@ -792,7 +818,7 @@ data_phase_loop: and DMAPARAMS, ~(HDMAEN|SDMAEN); if ((ahc->features & AHC_ULTRA2) != 0) { bmov HCNT, ALLONES, 3; - or SXFRCTL0, CLRCHN; /* Ensure FIFO empty */ + or SXFRCTL0, CLRCHN|CLRSTCNT;/* Ensure FIFO empty */ } else if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov STCNT, ALLONES, 3; } else { @@ -907,6 +933,10 @@ sgptr_fixup_done: clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */ } else { /* If we are the last SG block, tell the hardware. */ + if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 + && ahc->pci_cachesize != 0) { + test MWI_RESIDUAL, 0xFF jnz dma_mid_sg; + } test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg; if ((ahc->flags & AHC_TARGETMODE) != 0) { test SSTAT0, TARGET jz dma_last_sg; @@ -952,13 +982,15 @@ dma_dmadone: and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN); dma_halt: /* - * Some revisions of the aic7880 have a problem where, if the + * Some revisions of the aic78XX have a problem where, if the * data fifo is full, but the PCI input latch is not empty, * HDMAEN cannot be cleared. The fix used here is to drain * the prefetched but unused data from the data fifo until * there is space for the input latch to drain. */ - mov NONE, DFDAT; + if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { + mov NONE, DFDAT; + } test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt; /* See if we have completed this last segment */ @@ -969,6 +1001,26 @@ dma_halt: /* * Advance the scatter-gather pointers if needed */ + if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 + && ahc->pci_cachesize != 0) { + test MWI_RESIDUAL, 0xFF jz no_mwi_resid; + /* + * Reload HADDR from SHADDR and setup the + * count to be the size of our residual. + */ + if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov HADDR, SHADDR, 4; + mov HCNT, MWI_RESIDUAL; + bmov HCNT[1], ALLZEROS, 2; + } else { + mvi DINDEX, HADDR; + mvi SHADDR call bcopy_4; + mov MWI_RESIDUAL call set_hcnt; + } + clr MWI_RESIDUAL; + jmp sg_load_done; +no_mwi_resid: + } test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load; or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL; jmp data_phase_finish; @@ -985,8 +1037,8 @@ sg_load: call idle_loop; test CCSGCTL, CCSGEN jnz . - 1; bmov HADDR, CCSGRAM, 7; - bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1; - bmov STCNT, HCNT, 3; + test CCSGRAM, SG_LAST_SEG jz . + 2; + or SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG; } else { mvi DINDEX, HADDR; mvi SCB_RESIDUAL_SGPTR call bcopy_4; @@ -997,18 +1049,29 @@ sg_load: call dma_finish; - mvi HADDR call dfdat_in_7; + mvi DINDEX, HADDR; + call dfdat_in_7; mov SCB_RESIDUAL_DATACNT[3], DFDAT; - call set_stcnt_from_hcnt; } - /* Track odd'ness */ - test HCNT[0], 0x1 jz . + 2; - xor DATA_COUNT_ODD, 0x1; + if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 + && ahc->pci_cachesize != 0) { + call calc_mwi_residual; + } /* Point to the new next sg in memory */ call sg_advance; +sg_load_done: + if ((ahc->features & AHC_CMD_CHAN) != 0) { + bmov STCNT, HCNT, 3; + } else { + call set_stcnt_from_hcnt; + } + /* Track odd'ness */ + test HCNT[0], 0x1 jz . + 2; + xor DATA_COUNT_ODD, 0x1; + if ((ahc->flags & AHC_TARGETMODE) != 0) { test SSTAT0, TARGET jnz data_phase_loop; } @@ -1055,12 +1118,30 @@ data_phase_done: /* Kill off any pending prefetch */ clr CCSGCTL; test CCSGCTL, CCSGEN jnz .; + } + if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 + && ahc->pci_cachesize != 0) { + if ((ahc->features & AHC_CMD_CHAN) != 0) { + test MWI_RESIDUAL, 0xFF jz bmov_resid; + } + mov A, MWI_RESIDUAL; + add SCB_RESIDUAL_DATACNT[0], A, STCNT[0]; + clr A; + adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1]; + adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2]; + clr MWI_RESIDUAL; + if ((ahc->features & AHC_CMD_CHAN) != 0) { + jmp . + 2; +bmov_resid: + bmov SCB_RESIDUAL_DATACNT, STCNT, 3; + } + } else if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov SCB_RESIDUAL_DATACNT, STCNT, 3; } else { - mov SCB_RESIDUAL_DATACNT[0],STCNT[0]; - mov SCB_RESIDUAL_DATACNT[1],STCNT[1]; - mov SCB_RESIDUAL_DATACNT[2],STCNT[2]; + mov SCB_RESIDUAL_DATACNT[0], STCNT[0]; + mov SCB_RESIDUAL_DATACNT[1], STCNT[1]; + mov SCB_RESIDUAL_DATACNT[2], STCNT[2]; } /* @@ -1108,7 +1189,7 @@ p_command: clr STCNT[2]; } add NONE, -13, SCB_CDB_LEN; - mvi SCB_CDB_STORE jnc p_command_embedded; + mvi SCB_CDB_STORE jnc p_command_embedded; p_command_from_host: if ((ahc->features & AHC_ULTRA2) != 0) { bmov HADDR[0], SCB_CDB_PTR, 4; @@ -1116,7 +1197,7 @@ p_command_from_host: } else { if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov HADDR[0], SCB_CDB_PTR, 4; - bmov HCNT[0], STCNT[0], 3; + bmov HCNT, STCNT, 3; } else { mvi DINDEX, HADDR; mvi SCB_CDB_PTR call bcopy_5; @@ -1135,15 +1216,29 @@ p_command_embedded: clr HADDR[0]; if ((ahc->features & AHC_ULTRA2) != 0) { mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); - } else { - mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); - } - if ((ahc->features & AHC_CMD_CHAN) != 0) { bmov DFDAT, SCB_CDB_STORE, 12; - if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { + } else if ((ahc->features & AHC_CMD_CHAN) != 0) { + if ((ahc->features & AHC_SCB_BTT) != 0) { + /* + * On the 7895 the data FIFO will + * get corrupted if you try to dump + * data from external SCB memory into + * the FIFO while it is enabled. So, + * fill the fifo and then enable SCSI + * transfers. + */ + mvi DFCNTRL, (DIRECTION|FIFORESET); + } else { + mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); + } + bmov DFDAT, SCB_CDB_STORE, 12; + if ((ahc->features & AHC_SCB_BTT) != 0) { + mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); + } else { or DFCNTRL, FIFOFLUSH; } } else { + mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); call copy_to_fifo_6; call copy_to_fifo_6; or DFCNTRL, FIFOFLUSH; @@ -1437,11 +1532,11 @@ mesgin_rdptrs: * upon return. SCBPTR may be modified by this action. */ index_busy_target: + shr SINDEX, 4; if ((ahc->features & AHC_SCB_BTT) != 0) { mov SCBPTR, SAVED_LUN; add SINDEX, SCB_64_BTT; } else { - shr SINDEX, 4; add SINDEX, BUSY_TARGETS; } mov DINDEX, SINDEX ret; @@ -1629,6 +1724,7 @@ assert: * preceding SCB in the disconnected list which can be used to speed up * removal of the found SCB from the disconnected list. */ +if ((ahc->flags & AHC_PAGESCBS) != 0) { findSCB: mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */ mov A, SINDEX; /* Tag passed in SINDEX */ @@ -1654,6 +1750,7 @@ findSCB_notFound: /* Jump instead of call as we want to return anyway */ test SCB_CONTROL, DISCONNECTED jnz add_scb_to_disc_list; jmp add_scb_to_free_list; +} /* * This routine expects SINDEX to contain the index of the SCB to be @@ -1822,17 +1919,27 @@ dma_scb: mvi HSCB_ADDR call set_64byte_addr; mov CCSCBPTR, SCBPTR; test DMAPARAMS, DIRECTION jz dma_scb_tohost; - mvi CCHCNT, SCB_64BYTE_SIZE; + if ((ahc->features & AHC_SCB_BTT) != 0) { + mvi CCHCNT, SCB_DOWNLOAD_SIZE_64; + } else { + mvi CCHCNT, SCB_DOWNLOAD_SIZE; + } mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET; cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .; jmp dma_scb_finish; dma_scb_tohost: - mvi CCHCNT, SCB_32BYTE_SIZE; - if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { + mvi CCHCNT, SCB_UPLOAD_SIZE; + if ((ahc->features & AHC_ULTRA2) == 0) { mvi CCSCBCTL, CCSCBRESET; - bmov CCSCBRAM, SCB_CONTROL, SCB_32BYTE_SIZE; + bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE; or CCSCBCTL, CCSCBEN|CCSCBRESET; test CCSCBCTL, CCSCBDONE jz .; + } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) { + mvi CCSCBCTL, CCARREN|CCSCBRESET; + cmp CCSCBCTL, ARRDONE|CCARREN jne .; + mvi CCHCNT, SCB_UPLOAD_SIZE; + mvi CCSCBCTL, CCSCBEN|CCSCBRESET; + cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .; } else { mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET; cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .; @@ -1844,39 +1951,90 @@ dma_scb_finish: } else { mvi DINDEX, HADDR; mvi HSCB_ADDR call set_64byte_addr; - mvi SCB_32BYTE_SIZE call set_hcnt; + mvi SCB_DOWNLOAD_SIZE call set_hcnt; mov DFCNTRL, DMAPARAMS; test DMAPARAMS, DIRECTION jnz dma_scb_fromhost; /* Fill it with the SCB data */ copy_scb_tofifo: - mvi SINDEX, SCB_CONTROL; - add A, SCB_32BYTE_SIZE, SINDEX; + mvi SINDEX, SCB_BASE; + add A, SCB_DOWNLOAD_SIZE, SINDEX; copy_scb_tofifo_loop: - call copy_to_fifo_6; + call copy_to_fifo_8; cmp SINDEX, A jne copy_scb_tofifo_loop; or DFCNTRL, HDMAEN|FIFOFLUSH; + jmp dma_finish; dma_scb_fromhost: - call dma_finish; - /* If we were putting the SCB, we are done */ - test DMAPARAMS, DIRECTION jz return; - mvi SCB_CONTROL call dfdat_in_7; - call dfdat_in_7_continued; - call dfdat_in_7_continued; - call dfdat_in_7_continued; - jmp dfdat_in_2_continued; + mvi DINDEX, SCB_BASE; + if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) { + /* + * The PCI module will only issue a PCI + * retry if the data FIFO is empty. If the + * host disconnects in the middle of a + * transfer, we must empty the fifo of all + * available data to force the chip to + * continue the transfer. This does not + * happen for SCSI transfers as the SCSI module + * will drain the FIFO as data is made available. + * When the hang occurs, we know that at least + * 8 bytes are in the FIFO because the PCI + * module has an 8 byte input latch that only + * dumps to the FIFO when HCNT == 0 or the + * latch is full. + */ + mvi A, -24; + /* Wait for some data to arrive. */ +dma_scb_hang_fifo: + test DFSTATUS, FIFOEMP jnz dma_scb_hang_fifo; +dma_scb_hang_wait: + test DFSTATUS, MREQPEND jnz dma_scb_hang_wait; + test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; + test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; + test DFSTATUS, HDONE jnz dma_scb_hang_dma_done; + /* + * The PCI no longer intends to perform a PCI + * transaction and HDONE has not come true. + * We are hung. Drain the fifo. + */ +dma_scb_hang_empty_fifo: + call dfdat_in_8; + add A, 8; + add SINDEX, A, HCNT; + /* + * The result will be <= 0 (carry set) if at + * least 8 bytes of data have been placed + * into the fifo. + */ + jc dma_scb_hang_empty_fifo; + jmp dma_scb_hang_fifo; +dma_scb_hang_dma_done: + and DFCNTRL, ~HDMAEN; + test DFCNTRL, HDMAEN jnz .; + call dfdat_in_8; + add A, 8; + cmp A, 8 jne . - 2; + } else { + call dma_finish; + /* If we were putting the SCB, we are done */ + call dfdat_in_8; + call dfdat_in_8; + call dfdat_in_8; + } +dfdat_in_8: + mov DINDIR,DFDAT; dfdat_in_7: - mov DINDEX,SINDEX; -dfdat_in_7_continued: mov DINDIR,DFDAT; mov DINDIR,DFDAT; mov DINDIR,DFDAT; mov DINDIR,DFDAT; mov DINDIR,DFDAT; -dfdat_in_2_continued: +dfdat_in_2: mov DINDIR,DFDAT; mov DINDIR,DFDAT ret; } +copy_to_fifo_8: + mov DFDAT,SINDIR; + mov DFDAT,SINDIR; copy_to_fifo_6: mov DFDAT,SINDIR; copy_to_fifo_5: @@ -1923,7 +2081,6 @@ unlink_disc_scb: dequeue_free_scb: mov SCBPTR, FREE_SCBH; mov FREE_SCBH, SCB_NEXT ret; -} add_scb_to_disc_list: /* @@ -1933,5 +2090,6 @@ add_scb_to_disc_list: */ mov SCB_NEXT, DISCONNECTED_SCBH; mov DISCONNECTED_SCBH, SCBPTR ret; +} return: ret; diff --git a/sys/dev/aic7xxx/aic7xxx_93cx6.c b/sys/dev/aic7xxx/aic7xxx_93cx6.c index 62a4aeefa9c1..c5fc7f863ffa 100644 --- a/sys/dev/aic7xxx/aic7xxx_93cx6.c +++ b/sys/dev/aic7xxx/aic7xxx_93cx6.c @@ -8,15 +8,27 @@ * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright - * notice immediately at the beginning of the file, without modification, - * this list of conditions, and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Absolutely no warranty of function or purpose is made by the author - * Daniel M. Eischen. - * 4. Modifications may be freely made to this file if the above conditions - * are met. + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ * * $FreeBSD$ */ @@ -55,22 +67,25 @@ * */ -#include "opt_aic7xxx.h" +#ifdef __linux__ +#include "aic7xxx_linux.h" +#include "aic7xxx_inline.h" +#include "aic7xxx_93cx6.h" +#endif -#include <sys/param.h> -#include <sys/systm.h> -#include <machine/bus_memio.h> -#include <machine/bus_pio.h> -#include <machine/bus.h> -#include <dev/aic7xxx/93cx6.h> +#ifdef __FreeBSD__ +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> +#include <dev/aic7xxx/aic7xxx_93cx6.h> +#endif /* * Right now, we only have to read the SEEPROM. But we make it easier to * add other 93Cx6 functions. */ static struct seeprom_cmd { - unsigned char len; - unsigned char bits[3]; + uint8_t len; + uint8_t bits[3]; } seeprom_read = {3, {1, 1, 0}}; /* @@ -90,8 +105,8 @@ int read_seeprom(sd, buf, start_addr, count) struct seeprom_descriptor *sd; uint16_t *buf; - bus_size_t start_addr; - bus_size_t count; + u_int start_addr; + u_int count; { int i = 0; u_int k = 0; @@ -174,3 +189,25 @@ read_seeprom(sd, buf, start_addr, count) #endif return (1); } + +int +verify_cksum(struct seeprom_config *sc) +{ + int i; + int maxaddr; + uint32_t checksum; + uint16_t *scarray; + + maxaddr = (sizeof(*sc)/2) - 1; + checksum = 0; + scarray = (uint16_t *)sc; + + for (i = 0; i < maxaddr; i++) + checksum = checksum + scarray[i]; + if (checksum == 0 + || (checksum & 0xFFFF) != sc->checksum) { + return (0); + } else { + return(1); + } +} diff --git a/sys/dev/aic7xxx/aic7xxx_93cx6.h b/sys/dev/aic7xxx/aic7xxx_93cx6.h index 8fd7bb9be1ed..2fe0661ed5c7 100644 --- a/sys/dev/aic7xxx/aic7xxx_93cx6.h +++ b/sys/dev/aic7xxx/aic7xxx_93cx6.h @@ -1,9 +1,9 @@ /* - * Interface to the 93C46 serial EEPROM that is used to store BIOS + * Interface to the 93C46/56 serial EEPROM that is used to store BIOS * settings for the aic7xxx based adaptec SCSI controllers. It can * also be used for 93C26 and 93C06 serial EEPROMS. * - * Copyright (c) 1994, 1995 Justin T. Gibbs. + * Copyright (c) 1994, 1995, 2000 Justin T. Gibbs. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,15 +30,12 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * + * $Id$ + * * $FreeBSD$ */ - -#include <sys/param.h> -#if !defined(__NetBSD__) -#include <sys/systm.h> -#endif - -#ifdef _KERNEL +#ifndef _AIC7XXX_93CX6_H_ +#define _AIC7XXX_93CX6_H_ typedef enum { C46 = 6, @@ -46,11 +43,10 @@ typedef enum { } seeprom_chip_t; struct seeprom_descriptor { - bus_space_tag_t sd_tag; - bus_space_handle_t sd_bsh; - bus_size_t sd_control_offset; - bus_size_t sd_status_offset; - bus_size_t sd_dataout_offset; + struct ahc_softc *sd_ahc; + u_int sd_control_offset; + u_int sd_status_offset; + u_int sd_dataout_offset; seeprom_chip_t sd_chip; uint16_t sd_MS; uint16_t sd_RDY; @@ -77,15 +73,20 @@ struct seeprom_descriptor { */ #define SEEPROM_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset) -#define SEEPROM_OUTB(sd, value) \ - bus_space_write_1(sd->sd_tag, sd->sd_bsh, sd->sd_control_offset, value) + ahc_inb(sd->sd_ahc, sd->sd_control_offset) +#define SEEPROM_OUTB(sd, value) \ +do { \ + ahc_outb(sd->sd_ahc, sd->sd_control_offset, value); \ + ahc_flush_device_writes(sd->sd_ahc); \ +} while(0) + #define SEEPROM_STATUS_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_status_offset) + ahc_inb(sd->sd_ahc, sd->sd_status_offset) #define SEEPROM_DATA_INB(sd) \ - bus_space_read_1(sd->sd_tag, sd->sd_bsh, sd->sd_dataout_offset) + ahc_inb(sd->sd_ahc, sd->sd_dataout_offset) int read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, - bus_size_t start_addr, bus_size_t count); + u_int start_addr, u_int count); +int verify_cksum(struct seeprom_config *sc); -#endif /* _KERNEL */ +#endif /* _AIC7XXX_93CX6_H_ */ diff --git a/sys/dev/aic7xxx/aic7xxx_freebsd.c b/sys/dev/aic7xxx/aic7xxx_freebsd.c new file mode 100644 index 000000000000..c9c8f5a2fefd --- /dev/null +++ b/sys/dev/aic7xxx/aic7xxx_freebsd.c @@ -0,0 +1,1823 @@ +/* + * Bus independent FreeBSD shim for the aic7xxx based adaptec SCSI controllers + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> + +#include <sys/eventhandler.h> + +#ifndef AHC_TMODE_ENABLE +#define AHC_TMODE_ENABLE 0 +#endif + +#define ccb_scb_ptr spriv_ptr0 +#define ccb_ahc_ptr spriv_ptr1 + +#ifdef AHC_DEBUG +static int ahc_debug = AHC_DEBUG; +#endif + +static void ahc_freebsd_intr(void *arg); + +#if UNUSED +static void ahc_dump_targcmd(struct target_cmd *cmd); +#endif +static void ahc_action(struct cam_sim *sim, union ccb *ccb); +static void ahc_get_tran_settings(struct ahc_softc *ahc, + int our_id, char channel, + struct ccb_trans_settings *cts); +static void ahc_async(void *callback_arg, uint32_t code, + struct cam_path *path, void *arg); +static void ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, + int nsegments, int error); +static void ahc_poll(struct cam_sim *sim); +static void ahc_setup_data(struct ahc_softc *ahc, struct cam_sim *sim, + struct ccb_scsiio *csio, struct scb *scb); +static void ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, + union ccb *ccb); +static int ahc_create_path(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct cam_path **path); + +static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); + +static int +ahc_create_path(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct cam_path **path) +{ + path_id_t path_id; + + if (devinfo->channel == 'B') + path_id = cam_sim_path(ahc->platform_data->sim_b); + else + path_id = cam_sim_path(ahc->platform_data->sim); + + return (xpt_create_path(path, /*periph*/NULL, + path_id, devinfo->target, + devinfo->lun)); +} + +/* + * Attach all the sub-devices we can find + */ +int +ahc_attach(struct ahc_softc *ahc) +{ + char ahc_info[256]; + struct ccb_setasync csa; + struct cam_devq *devq; + int bus_id; + int bus_id2; + struct cam_sim *sim; + struct cam_sim *sim2; + struct cam_path *path; + struct cam_path *path2; + long s; + int count; + int error; + + count = 0; + sim = NULL; + sim2 = NULL; + + ahc_controller_info(ahc, ahc_info); + printf("%s\n", ahc_info); + ahc_lock(ahc, &s); + /* Hook up our interrupt handler */ + if ((error = bus_setup_intr(ahc->dev_softc, ahc->platform_data->irq, + INTR_TYPE_CAM, ahc_freebsd_intr, ahc, + &ahc->platform_data->ih)) != 0) { + device_printf(ahc->dev_softc, "bus_setup_intr() failed: %d\n", + error); + goto fail; + } + + /* + * Attach secondary channel first if the user has + * declared it the primary channel. + */ + if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { + bus_id = 1; + bus_id2 = 0; + } else { + bus_id = 0; + bus_id2 = 1; + } + + /* + * Create the device queue for our SIM(s). + */ + devq = cam_simq_alloc(AHC_SCB_MAX); + if (devq == NULL) + goto fail; + + /* + * Construct our first channel SIM entry + */ + sim = cam_sim_alloc(ahc_action, ahc_poll, "ahc", ahc, ahc->unit, + 1, AHC_SCB_MAX, devq); + if (sim == NULL) { + cam_simq_free(devq); + goto fail; + } + + if (xpt_bus_register(sim, bus_id) != CAM_SUCCESS) { + cam_sim_free(sim, /*free_devq*/TRUE); + sim = NULL; + goto fail; + } + + if (xpt_create_path(&path, /*periph*/NULL, + cam_sim_path(sim), CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD) != CAM_REQ_CMP) { + xpt_bus_deregister(cam_sim_path(sim)); + cam_sim_free(sim, /*free_devq*/TRUE); + sim = NULL; + goto fail; + } + + xpt_setup_ccb(&csa.ccb_h, path, /*priority*/5); + csa.ccb_h.func_code = XPT_SASYNC_CB; + csa.event_enable = AC_LOST_DEVICE; + csa.callback = ahc_async; + csa.callback_arg = sim; + xpt_action((union ccb *)&csa); + count++; + + if (ahc->features & AHC_TWIN) { + sim2 = cam_sim_alloc(ahc_action, ahc_poll, "ahc", + ahc, ahc->unit, 1, + AHC_SCB_MAX, devq); + + if (sim2 == NULL) { + printf("ahc_attach: Unable to attach second " + "bus due to resource shortage"); + goto fail; + } + + if (xpt_bus_register(sim2, bus_id2) != CAM_SUCCESS) { + printf("ahc_attach: Unable to attach second " + "bus due to resource shortage"); + /* + * We do not want to destroy the device queue + * because the first bus is using it. + */ + cam_sim_free(sim2, /*free_devq*/FALSE); + goto fail; + } + + if (xpt_create_path(&path2, /*periph*/NULL, + cam_sim_path(sim2), + CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD) != CAM_REQ_CMP) { + xpt_bus_deregister(cam_sim_path(sim2)); + cam_sim_free(sim2, /*free_devq*/FALSE); + sim2 = NULL; + goto fail; + } + xpt_setup_ccb(&csa.ccb_h, path2, /*priority*/5); + csa.ccb_h.func_code = XPT_SASYNC_CB; + csa.event_enable = AC_LOST_DEVICE; + csa.callback = ahc_async; + csa.callback_arg = sim2; + xpt_action((union ccb *)&csa); + count++; + } + +fail: + if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { + ahc->platform_data->sim_b = sim; + ahc->platform_data->path_b = path; + ahc->platform_data->sim = sim2; + ahc->platform_data->path = path2; + } else { + ahc->platform_data->sim = sim; + ahc->platform_data->path = path; + ahc->platform_data->sim_b = sim2; + ahc->platform_data->path_b = path2; + } + ahc_unlock(ahc, &s); + + if (count != 0) + /* We have to wait until after any system dumps... */ + EVENTHANDLER_REGISTER(shutdown_final, ahc_shutdown, + ahc, SHUTDOWN_PRI_DEFAULT); + + return (count); +} + +/* + * Catch an interrupt from the adapter + */ +void +ahc_freebsd_intr(void *arg) +{ + struct ahc_softc *ahc; + + ahc = (struct ahc_softc *)arg; + ahc_intr(ahc); +} + +/* + * We have an scb which has been processed by the + * adaptor, now we look to see how the operation + * went. + */ +void +ahc_done(struct ahc_softc *ahc, struct scb *scb) +{ + union ccb *ccb; + + CAM_DEBUG(scb->io_ctx->ccb_h.path, CAM_DEBUG_TRACE, + ("ahc_done - scb %d\n", scb->hscb->tag)); + + ccb = scb->io_ctx; + LIST_REMOVE(scb, pending_links); + if (ccb->ccb_h.func_code == XPT_SCSI_IO + && ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0 + || ccb->csio.tag_action == CAM_TAG_ACTION_NONE) + && (ahc->features & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + + untagged_q = &ahc->untagged_queues[ccb->ccb_h.target_id]; + TAILQ_REMOVE(untagged_q, scb, links.tqe); + ahc_run_untagged_queue(ahc, untagged_q); + } + + untimeout(ahc_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch); + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { + bus_dmasync_op_t op; + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + op = BUS_DMASYNC_POSTREAD; + else + op = BUS_DMASYNC_POSTWRITE; + bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op); + bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); + } + + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + if (ahc_get_transaction_status(scb) == CAM_REQ_INPROG) + ccb->ccb_h.status |= CAM_REQ_CMP; + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ahc_free_scb(ahc, scb); + xpt_done(ccb); + return; + } + + /* + * If the recovery SCB completes, we have to be + * out of our timeout. + */ + if ((scb->flags & SCB_RECOVERY_SCB) != 0) { + struct scb *list_scb; + + /* + * We were able to complete the command successfully, + * so reinstate the timeouts for all other pending + * commands. + */ + LIST_FOREACH(list_scb, &ahc->pending_scbs, pending_links) { + union ccb *ccb; + + ccb = list_scb->io_ctx; + ccb->ccb_h.timeout_ch = + timeout(ahc_timeout, list_scb, + (ccb->ccb_h.timeout * hz)/1000); + } + + /* + * Ensure that we didn't put a second instance of this + * SCB into the QINFIFO. + */ + ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), + SCB_GET_CHANNEL(ahc, scb), + SCB_GET_LUN(scb), scb->hscb->tag, + ROLE_INITIATOR, /*status*/0, + SEARCH_REMOVE); + if (ahc_get_transaction_status(scb) == CAM_BDR_SENT + || ahc_get_transaction_status(scb) == CAM_REQ_ABORTED) + ahc_set_transaction_status(scb, CAM_CMD_TIMEOUT); + ahc_print_path(ahc, scb); + printf("no longer in timeout, status = %x\n", + ccb->ccb_h.status); + } + + /* Don't clobber any existing error state */ + if (ahc_get_transaction_status(scb) == CAM_REQ_INPROG) { + ccb->ccb_h.status |= CAM_REQ_CMP; + } else if ((scb->flags & SCB_SENSE) != 0) { + /* + * We performed autosense retrieval. + * + * Zero any sense not transferred by the + * device. The SCSI spec mandates that any + * untransfered data should be assumed to be + * zero. Complete the 'bounce' of sense information + * through buffers accessible via bus-space by + * copying it into the clients csio. + */ + memset(&ccb->csio.sense_data, 0, sizeof(ccb->csio.sense_data)); + memcpy(&ccb->csio.sense_data, + &ahc->scb_data->sense[scb->hscb->tag], + (scb->sg_list->len & AHC_SG_LEN_MASK) + - ccb->csio.sense_resid); + scb->io_ctx->ccb_h.status |= CAM_AUTOSNS_VALID; + } + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ahc_free_scb(ahc, scb); + xpt_done(ccb); +} + +static void +ahc_action(struct cam_sim *sim, union ccb *ccb) +{ + struct ahc_softc *ahc; + struct tmode_lstate *lstate; + u_int target_id; + u_int our_id; + long s; + + CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahc_action\n")); + + ahc = (struct ahc_softc *)cam_sim_softc(sim); + + target_id = ccb->ccb_h.target_id; + our_id = SIM_SCSI_ID(ahc, sim); + + switch (ccb->ccb_h.func_code) { + /* Common cases first */ + case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ + case XPT_CONT_TARGET_IO:/* Continue Host Target I/O Connection*/ + { + struct tmode_tstate *tstate; + cam_status status; + + status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, + &lstate, TRUE); + + if (status != CAM_REQ_CMP) { + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + /* Response from the black hole device */ + tstate = NULL; + lstate = ahc->black_hole; + } else { + ccb->ccb_h.status = status; + xpt_done(ccb); + break; + } + } + if (ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) { + + ahc_lock(ahc, &s); + SLIST_INSERT_HEAD(&lstate->accept_tios, &ccb->ccb_h, + sim_links.sle); + ccb->ccb_h.status = CAM_REQ_INPROG; + if ((ahc->flags & AHC_TQINFIFO_BLOCKED) != 0) + ahc_run_tqinfifo(ahc, /*paused*/FALSE); + ahc_unlock(ahc, &s); + break; + } + + /* + * The target_id represents the target we attempt to + * select. In target mode, this is the initiator of + * the original command. + */ + our_id = target_id; + target_id = ccb->csio.init_id; + /* FALLTHROUGH */ + } + case XPT_SCSI_IO: /* Execute the requested I/O operation */ + case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ + { + struct scb *scb; + struct hardware_scb *hscb; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t mask; + + /* + * get an scb to use. + */ + if ((scb = ahc_get_scb(ahc)) == NULL) { + + ahc_lock(ahc, &s); + ahc->flags |= AHC_RESOURCE_SHORTAGE; + ahc_unlock(ahc, &s); + xpt_freeze_simq(sim, /*count*/1); + ahc_set_transaction_status(scb, CAM_REQUEUE_REQ); + xpt_done(ccb); + return; + } + + hscb = scb->hscb; + + CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_SUBTRACE, + ("start scb(%p)\n", scb)); + scb->io_ctx = ccb; + /* + * So we can find the SCB when an abort is requested + */ + ccb->ccb_h.ccb_scb_ptr = scb; + ccb->ccb_h.ccb_ahc_ptr = ahc; + + /* + * Put all the arguments for the xfer in the scb + */ + hscb->control = 0; + hscb->scsiid = BUILD_SCSIID(ahc, sim, target_id, our_id); + hscb->lun = ccb->ccb_h.target_lun; + mask = SCB_GET_TARGET_MASK(ahc, scb); + tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, sim), our_id, + target_id, &tstate); + + hscb->scsirate = tinfo->scsirate; + hscb->scsioffset = tinfo->current.offset; + if ((tstate->ultraenb & mask) != 0) + hscb->control |= ULTRAENB; + + if ((tstate->discenable & mask) != 0 + && (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0) + hscb->control |= DISCENB; + + if ((ccb->ccb_h.flags & CAM_NEGOTIATE) != 0 + && (tinfo->current.width != 0 || tinfo->current.period != 0)) { + scb->flags |= SCB_NEGOTIATE; + hscb->control |= MK_MESSAGE; + } + + if (ccb->ccb_h.func_code == XPT_RESET_DEV) { + hscb->cdb_len = 0; + scb->flags |= SCB_DEVICE_RESET; + hscb->control |= MK_MESSAGE; + ahc_execute_scb(scb, NULL, 0, 0); + } else { + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + struct target_data *tdata; + + tdata = &hscb->shared_data.tdata; + if (ahc->pending_device == lstate) { + scb->flags |= SCB_TARGET_IMMEDIATE; + ahc->pending_device = NULL; + } + hscb->control |= TARGET_SCB; + tdata->target_phases = IDENTIFY_SEEN; + if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { + tdata->target_phases |= SPHASE_PENDING; + tdata->scsi_status = + ccb->csio.scsi_status; + } + tdata->initiator_tag = ccb->csio.tag_id; + } + if (ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) + hscb->control |= ccb->csio.tag_action; + + ahc_setup_data(ahc, sim, &ccb->csio, scb); + } + break; + } + case XPT_NOTIFY_ACK: + case XPT_IMMED_NOTIFY: + { + struct tmode_tstate *tstate; + struct tmode_lstate *lstate; + cam_status status; + + status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, + &lstate, TRUE); + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; + xpt_done(ccb); + break; + } + SLIST_INSERT_HEAD(&lstate->immed_notifies, &ccb->ccb_h, + sim_links.sle); + ccb->ccb_h.status = CAM_REQ_INPROG; + ahc_send_lstate_events(ahc, lstate); + break; + } + case XPT_EN_LUN: /* Enable LUN as a target */ + ahc_handle_en_lun(ahc, sim, ccb); + xpt_done(ccb); + break; + case XPT_ABORT: /* Abort the specified CCB */ + { + ahc_abort_ccb(ahc, sim, ccb); + break; + } + case XPT_SET_TRAN_SETTINGS: + { +#ifdef AHC_NEW_TRAN_SETTINGS + struct ahc_devinfo devinfo; + struct ccb_trans_settings *cts; + struct ccb_trans_settings_scsi *scsi; + struct ccb_trans_settings_spi *spi; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t *discenable; + uint16_t *tagenable; + u_int update_type; + + cts = &ccb->cts; + scsi = &cts->proto_specific.scsi; + spi = &cts->xport_specific.spi; + ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + SIM_CHANNEL(ahc, sim), + ROLE_UNKNOWN); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + update_type = 0; + if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { + update_type |= AHC_TRANS_GOAL; + discenable = &tstate->discenable; + tagenable = &tstate->tagenable; + tinfo->current.protocol_version = + cts->protocol_version; + tinfo->current.transport_version = + cts->transport_version; + tinfo->goal.protocol_version = + cts->protocol_version; + tinfo->goal.transport_version = + cts->transport_version; + } else if (cts->type == CTS_TYPE_USER_SETTINGS) { + update_type |= AHC_TRANS_USER; + discenable = &ahc->user_discenable; + tagenable = &ahc->user_tagenable; + tinfo->user.protocol_version = + cts->protocol_version; + tinfo->user.transport_version = + cts->transport_version; + } else { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + + ahc_lock(ahc, &s); + + if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { + if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) + *discenable |= devinfo.target_mask; + else + *discenable &= ~devinfo.target_mask; + } + + if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { + if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) + *tagenable |= devinfo.target_mask; + else + *tagenable &= ~devinfo.target_mask; + } + + if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) { + ahc_validate_width(ahc, &spi->bus_width); + ahc_set_width(ahc, &devinfo, spi->bus_width, + update_type, /*paused*/FALSE); + } + + if ((spi->valid & CTS_SPI_VALID_PPR_OPTIONS) == 0) { + if (update_type == AHC_TRANS_USER) + spi->ppr_options = tinfo->user.ppr_options; + else + spi->ppr_options = tinfo->goal.ppr_options; + } + + if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) { + if (update_type == AHC_TRANS_USER) + spi->sync_offset = tinfo->user.offset; + else + spi->sync_offset = tinfo->goal.offset; + } + + if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) { + if (update_type == AHC_TRANS_USER) + spi->sync_period = tinfo->user.period; + else + spi->sync_period = tinfo->goal.period; + } + + if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) + || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) { + struct ahc_syncrate *syncrate; + u_int maxsync; + + if ((ahc->features & AHC_ULTRA2) != 0) + maxsync = AHC_SYNCRATE_DT; + else if ((ahc->features & AHC_ULTRA) != 0) + maxsync = AHC_SYNCRATE_ULTRA; + else + maxsync = AHC_SYNCRATE_FAST; + + syncrate = ahc_find_syncrate(ahc, &spi->sync_period, + &spi->ppr_options, + maxsync); + ahc_validate_offset(ahc, syncrate, &spi->sync_offset, + spi->bus_width); + + /* We use a period of 0 to represent async */ + if (spi->sync_offset == 0) { + spi->sync_period = 0; + spi->ppr_options = 0; + } + + ahc_set_syncrate(ahc, &devinfo, syncrate, + spi->sync_period, spi->sync_offset, + spi->ppr_options, update_type, + /*paused*/FALSE); + } + ahc_unlock(ahc, &s); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); +#else + struct ahc_devinfo devinfo; + struct ccb_trans_settings *cts; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t *discenable; + uint16_t *tagenable; + u_int update_type; + long s; + + cts = &ccb->cts; + ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + SIM_CHANNEL(ahc, sim), + ROLE_UNKNOWN); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + update_type = 0; + if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { + update_type |= AHC_TRANS_GOAL; + discenable = &tstate->discenable; + tagenable = &tstate->tagenable; + } else if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { + update_type |= AHC_TRANS_USER; + discenable = &ahc->user_discenable; + tagenable = &ahc->user_tagenable; + } else { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + + ahc_lock(ahc, &s); + + if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { + if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) + *discenable |= devinfo.target_mask; + else + *discenable &= ~devinfo.target_mask; + } + + if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { + if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) + *tagenable |= devinfo.target_mask; + else + *tagenable &= ~devinfo.target_mask; + } + + if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { + ahc_validate_width(ahc, &cts->bus_width); + ahc_set_width(ahc, &devinfo, cts->bus_width, + update_type, /*paused*/FALSE); + } + + if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0) { + if (update_type == AHC_TRANS_USER) + cts->sync_offset = tinfo->user.offset; + else + cts->sync_offset = tinfo->goal.offset; + } + + if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0) { + if (update_type == AHC_TRANS_USER) + cts->sync_period = tinfo->user.period; + else + cts->sync_period = tinfo->goal.period; + } + + if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) + || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { + struct ahc_syncrate *syncrate; + u_int ppr_options; + u_int maxsync; + + if ((ahc->features & AHC_ULTRA2) != 0) + maxsync = AHC_SYNCRATE_DT; + else if ((ahc->features & AHC_ULTRA) != 0) + maxsync = AHC_SYNCRATE_ULTRA; + else + maxsync = AHC_SYNCRATE_FAST; + + ppr_options = 0; + if (cts->sync_period <= 9) + ppr_options = MSG_EXT_PPR_DT_REQ; + + syncrate = ahc_find_syncrate(ahc, &cts->sync_period, + &ppr_options, + maxsync); + ahc_validate_offset(ahc, syncrate, &cts->sync_offset, + MSG_EXT_WDTR_BUS_8_BIT); + + /* We use a period of 0 to represent async */ + if (cts->sync_offset == 0) { + cts->sync_period = 0; + ppr_options = 0; + } + + if (ppr_options == MSG_EXT_PPR_DT_REQ + && tinfo->user.transport_version >= 3) { + tinfo->goal.transport_version = + tinfo->user.transport_version; + tinfo->current.transport_version = + tinfo->user.transport_version; + } + + ahc_set_syncrate(ahc, &devinfo, syncrate, + cts->sync_period, cts->sync_offset, + ppr_options, update_type, + /*paused*/FALSE); + } + ahc_unlock(ahc, &s); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); +#endif + break; + } + case XPT_GET_TRAN_SETTINGS: + /* Get default/user set transfer settings for the target */ + { + + ahc_lock(ahc, &s); + ahc_get_tran_settings(ahc, SIM_SCSI_ID(ahc, sim), + SIM_CHANNEL(ahc, sim), &ccb->cts); + ahc_unlock(ahc, &s); + xpt_done(ccb); + break; + } + case XPT_CALC_GEOMETRY: + { + struct ccb_calc_geometry *ccg; + uint32_t size_mb; + uint32_t secs_per_cylinder; + int extended; + + ccg = &ccb->ccg; + size_mb = ccg->volume_size + / ((1024L * 1024L) / ccg->block_size); + extended = SIM_IS_SCSIBUS_B(ahc, sim) + ? ahc->flags & AHC_EXTENDED_TRANS_B + : ahc->flags & AHC_EXTENDED_TRANS_A; + + if (size_mb > 1024 && extended) { + ccg->heads = 255; + ccg->secs_per_track = 63; + } else { + ccg->heads = 64; + ccg->secs_per_track = 32; + } + secs_per_cylinder = ccg->heads * ccg->secs_per_track; + ccg->cylinders = ccg->volume_size / secs_per_cylinder; + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + case XPT_RESET_BUS: /* Reset the specified SCSI bus */ + { + int found; + + ahc_lock(ahc, &s); + found = ahc_reset_channel(ahc, SIM_CHANNEL(ahc, sim), + /*initiate reset*/TRUE); + ahc_unlock(ahc, &s); + if (bootverbose) { + xpt_print_path(SIM_PATH(ahc, sim)); + printf("SCSI bus reset delivered. " + "%d SCBs aborted.\n", found); + } + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + case XPT_TERM_IO: /* Terminate the I/O process */ + /* XXX Implement */ + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + case XPT_PATH_INQ: /* Path routing inquiry */ + { + struct ccb_pathinq *cpi = &ccb->cpi; + + cpi->version_num = 1; /* XXX??? */ + cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; + if ((ahc->features & AHC_WIDE) != 0) + cpi->hba_inquiry |= PI_WIDE_16; + if ((ahc->flags & AHC_TARGETMODE) != 0) { + cpi->target_sprt = PIT_PROCESSOR + | PIT_DISCONNECT + | PIT_TERM_IO; + } else { + cpi->target_sprt = 0; + } + cpi->hba_misc = (ahc->flags & AHC_INITIATORMODE) + ? 0 : PIM_NOINITIATOR; + cpi->hba_eng_cnt = 0; + cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; + cpi->max_lun = 64; + if (SIM_IS_SCSIBUS_B(ahc, sim)) { + cpi->initiator_id = ahc->our_id_b; + if ((ahc->flags & AHC_RESET_BUS_B) == 0) + cpi->hba_misc |= PIM_NOBUSRESET; + } else { + cpi->initiator_id = ahc->our_id; + if ((ahc->flags & AHC_RESET_BUS_A) == 0) + cpi->hba_misc |= PIM_NOBUSRESET; + } + cpi->bus_id = cam_sim_bus(sim); + cpi->base_transfer_speed = 3300; + strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); + strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN); + strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); + cpi->unit_number = cam_sim_unit(sim); +#ifdef AHC_NEW_TRAN_SETTINGS + cpi->protocol = PROTO_SCSI; + cpi->protocol_version = SCSI_REV_2; + cpi->transport = XPORT_SPI; + cpi->transport_version = 2; + cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; + if ((ahc->features & AHC_DT) != 0) { + cpi->transport_version = 3; + cpi->xport_specific.spi.ppr_options = + SID_SPI_CLOCK_DT_ST; + } +#endif + cpi->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + default: + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } +} + +static void +ahc_get_tran_settings(struct ahc_softc *ahc, int our_id, char channel, + struct ccb_trans_settings *cts) +{ +#ifdef AHC_NEW_TRAN_SETTINGS + struct ahc_devinfo devinfo; + struct ccb_trans_settings_scsi *scsi; + struct ccb_trans_settings_spi *spi; + struct ahc_initiator_tinfo *targ_info; + struct tmode_tstate *tstate; + struct ahc_transinfo *tinfo; + + scsi = &cts->proto_specific.scsi; + spi = &cts->xport_specific.spi; + ahc_compile_devinfo(&devinfo, our_id, + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + channel, ROLE_UNKNOWN); + targ_info = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + + if (cts->type == CTS_TYPE_CURRENT_SETTINGS) + tinfo = &targ_info->current; + else + tinfo = &targ_info->user; + + scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; + spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; + if (cts->type == CTS_TYPE_USER_SETTINGS) { + if ((ahc->user_discenable & devinfo.target_mask) != 0) + spi->flags |= CTS_SPI_FLAGS_DISC_ENB; + + if ((ahc->user_tagenable & devinfo.target_mask) != 0) + scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; + } else { + if ((tstate->discenable & devinfo.target_mask) != 0) + spi->flags |= CTS_SPI_FLAGS_DISC_ENB; + + if ((tstate->tagenable & devinfo.target_mask) != 0) + scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; + } + cts->protocol_version = tinfo->protocol_version; + cts->transport_version = tinfo->transport_version; + + spi->sync_period = tinfo->period; + spi->sync_offset = tinfo->offset; + spi->bus_width = tinfo->width; + spi->ppr_options = tinfo->ppr_options; + + cts->protocol = PROTO_SCSI; + cts->transport = XPORT_SPI; + scsi->valid = CTS_SCSI_VALID_TQ; + spi->valid = CTS_SPI_VALID_SYNC_RATE + | CTS_SPI_VALID_SYNC_OFFSET + | CTS_SPI_VALID_BUS_WIDTH + | CTS_SPI_VALID_DISC + | CTS_SPI_VALID_PPR_OPTIONS; + + cts->ccb_h.status = CAM_REQ_CMP; +#else + struct ahc_devinfo devinfo; + struct ahc_initiator_tinfo *targ_info; + struct tmode_tstate *tstate; + struct ahc_transinfo *tinfo; + long s; + + ahc_compile_devinfo(&devinfo, our_id, + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + channel, ROLE_UNKNOWN); + targ_info = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + + if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) + tinfo = &targ_info->current; + else + tinfo = &targ_info->user; + + ahc_lock(ahc, &s); + + cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); + if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { + if ((ahc->user_discenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_DISC_ENB; + + if ((ahc->user_tagenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_TAG_ENB; + } else { + if ((tstate->discenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_DISC_ENB; + + if ((tstate->tagenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_TAG_ENB; + } + cts->sync_period = tinfo->period; + cts->sync_offset = tinfo->offset; + cts->bus_width = tinfo->width; + + ahc_unlock(ahc, &s); + + cts->valid = CCB_TRANS_SYNC_RATE_VALID + | CCB_TRANS_SYNC_OFFSET_VALID + | CCB_TRANS_BUS_WIDTH_VALID + | CCB_TRANS_DISC_VALID + | CCB_TRANS_TQ_VALID; + + cts->ccb_h.status = CAM_REQ_CMP; +#endif +} + +static void +ahc_async(void *callback_arg, uint32_t code, struct cam_path *path, void *arg) +{ + struct ahc_softc *ahc; + struct cam_sim *sim; + + sim = (struct cam_sim *)callback_arg; + ahc = (struct ahc_softc *)cam_sim_softc(sim); + switch (code) { + case AC_LOST_DEVICE: + { + struct ahc_devinfo devinfo; + long s; + + ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), + xpt_path_target_id(path), + xpt_path_lun_id(path), + SIM_CHANNEL(ahc, sim), + ROLE_UNKNOWN); + + /* + * Revert to async/narrow transfers + * for the next device. + */ + ahc_lock(ahc, &s); + ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, + AHC_TRANS_GOAL|AHC_TRANS_CUR, /*paused*/FALSE); + ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, + /*period*/0, /*offset*/0, /*ppr_options*/0, + AHC_TRANS_GOAL|AHC_TRANS_CUR, + /*paused*/FALSE); + ahc_unlock(ahc, &s); + break; + } + default: + break; + } +} + +static void +ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments, + int error) +{ + struct scb *scb; + union ccb *ccb; + struct ahc_softc *ahc; + long s; + + scb = (struct scb *)arg; + ccb = scb->io_ctx; + ahc = (struct ahc_softc *)ccb->ccb_h.ccb_ahc_ptr; + + if (error != 0) { + if (error == EFBIG) + ahc_set_transaction_status(scb, CAM_REQ_TOO_BIG); + else + ahc_set_transaction_status(scb, CAM_REQ_CMP_ERR); + if (nsegments != 0) + bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); + ahc_free_scb(ahc, scb); + xpt_done(ccb); + return; + } + if (nsegments != 0) { + struct ahc_dma_seg *sg; + bus_dma_segment_t *end_seg; + bus_dmasync_op_t op; + + end_seg = dm_segs + nsegments; + + /* Copy the segments into our SG list */ + sg = scb->sg_list; + while (dm_segs < end_seg) { + sg->addr = dm_segs->ds_addr; +/* XXX Add in the 5th byte of the address later. */ + sg->len = dm_segs->ds_len; + sg++; + dm_segs++; + } + + /* + * Note where to find the SG entries in bus space. + * We also set the full residual flag which the + * sequencer will clear as soon as a data transfer + * occurs. + */ + scb->hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + op = BUS_DMASYNC_PREREAD; + else + op = BUS_DMASYNC_PREWRITE; + + bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op); + + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + struct target_data *tdata; + + tdata = &scb->hscb->shared_data.tdata; + tdata->target_phases |= DPHASE_PENDING; + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + tdata->data_phase = P_DATAOUT; + else + tdata->data_phase = P_DATAIN; + + /* + * If the transfer is of an odd length and in the + * "in" direction (scsi->HostBus), then it may + * trigger a bug in the 'WideODD' feature of + * non-Ultra2 chips. Force the total data-length + * to be even by adding an extra, 1 byte, SG, + * element. We do this even if we are not currently + * negotiated wide as negotiation could occur before + * this command is executed. + */ + if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0 + && (ccb->csio.dxfer_len & 0x1) != 0 + && (ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { + + nsegments++; + if (nsegments > AHC_NSEG) { + + ahc_set_transaction_status(scb, + CAM_REQ_TOO_BIG); + bus_dmamap_unload(ahc->buffer_dmat, + scb->dmamap); + ahc_free_scb(ahc, scb); + xpt_done(ccb); + return; + } + sg->addr = ahc->dma_bug_buf; + sg->len = 1; + sg++; + } + } + sg--; + sg->len |= AHC_DMA_LAST_SEG; + + /* Copy the first SG into the "current" data pointer area */ + scb->hscb->dataptr = scb->sg_list->addr; + scb->hscb->datacnt = scb->sg_list->len; + } else { + scb->hscb->sgptr = SG_LIST_NULL; + scb->hscb->dataptr = 0; + scb->hscb->datacnt = 0; + } + + scb->sg_count = nsegments; + + ahc_lock(ahc, &s); + + /* + * Last time we need to check if this SCB needs to + * be aborted. + */ + if (ahc_get_transaction_status(scb) != CAM_REQ_INPROG) { + if (nsegments != 0) + bus_dmamap_unload(ahc->buffer_dmat, + scb->dmamap); + ahc_free_scb(ahc, scb); + xpt_done(ccb); + ahc_unlock(ahc, &s); + return; + } + + LIST_INSERT_HEAD(&ahc->pending_scbs, scb, pending_links); + + ccb->ccb_h.status |= CAM_SIM_QUEUED; + + if (ccb->ccb_h.timeout != CAM_TIME_INFINITY) { + if (ccb->ccb_h.timeout == CAM_TIME_DEFAULT) + ccb->ccb_h.timeout = 5 * 1000; + ccb->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)scb, + (ccb->ccb_h.timeout * hz) / 1000); + } + + /* + * We only allow one untagged transaction + * per target in the initiator role unless + * we are storing a full busy target *lun* + * table in SCB space. + */ + if ((scb->hscb->control & (TARGET_SCB|TAG_ENB)) == 0 + && (ahc->features & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + + untagged_q = &(ahc->untagged_queues[ccb->ccb_h.target_id]); + TAILQ_INSERT_TAIL(untagged_q, scb, links.tqe); + if (TAILQ_FIRST(untagged_q) != scb) { + ahc_unlock(ahc, &s); + return; + } + } + scb->flags |= SCB_ACTIVE; + + if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { + pause_sequencer(ahc); + if ((ahc->flags & AHC_PAGESCBS) == 0) + ahc_outb(ahc, SCBPTR, scb->hscb->tag); + ahc_outb(ahc, SCB_TAG, scb->hscb->tag); + ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); + unpause_sequencer(ahc); + } else { + ahc_queue_scb(ahc, scb); + } + + ahc_unlock(ahc, &s); +} + +static void +ahc_poll(struct cam_sim *sim) +{ + ahc_intr(cam_sim_softc(sim)); +} + +static void +ahc_setup_data(struct ahc_softc *ahc, struct cam_sim *sim, + struct ccb_scsiio *csio, struct scb *scb) +{ + struct hardware_scb *hscb; + struct ccb_hdr *ccb_h; + + hscb = scb->hscb; + ccb_h = &csio->ccb_h; + + if (ccb_h->func_code == XPT_SCSI_IO) { + hscb->cdb_len = csio->cdb_len; + if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { + + if (hscb->cdb_len > sizeof(hscb->cdb32) + || (ccb_h->flags & CAM_CDB_PHYS) != 0) { + ahc_set_transaction_status(scb, + CAM_REQ_INVALID); + xpt_done(scb->io_ctx); + ahc_free_scb(ahc, scb); + return; + } + if (hscb->cdb_len > 12) { + memcpy(hscb->cdb32, + csio->cdb_io.cdb_ptr, + hscb->cdb_len); + hscb->shared_data.cdb_ptr = scb->cdb32_busaddr; + } else { + memcpy(hscb->shared_data.cdb, + csio->cdb_io.cdb_ptr, + hscb->cdb_len); + } + } else { + if (hscb->cdb_len > 12) { + memcpy(hscb->cdb32, csio->cdb_io.cdb_bytes, + hscb->cdb_len); + hscb->shared_data.cdb_ptr = scb->cdb32_busaddr; + } else { + memcpy(hscb->shared_data.cdb, + csio->cdb_io.cdb_bytes, + hscb->cdb_len); + } + } + } + + /* Only use S/G if there is a transfer */ + if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { + if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { + /* We've been given a pointer to a single buffer */ + if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { + int s; + int error; + + s = splsoftvm(); + error = bus_dmamap_load(ahc->buffer_dmat, + scb->dmamap, + csio->data_ptr, + csio->dxfer_len, + ahc_execute_scb, + scb, /*flags*/0); + if (error == EINPROGRESS) { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + xpt_freeze_simq(sim, + /*count*/1); + scb->io_ctx->ccb_h.status |= + CAM_RELEASE_SIMQ; + } + splx(s); + } else { + struct bus_dma_segment seg; + + /* Pointer to physical buffer */ + if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE) + panic("ahc_setup_data - Transfer size " + "larger than can device max"); + + seg.ds_addr = (bus_addr_t)csio->data_ptr; + seg.ds_len = csio->dxfer_len; + ahc_execute_scb(scb, &seg, 1, 0); + } + } else { + struct bus_dma_segment *segs; + + if ((ccb_h->flags & CAM_DATA_PHYS) != 0) + panic("ahc_setup_data - Physical segment " + "pointers unsupported"); + + if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) + panic("ahc_setup_data - Virtual segment " + "addresses unsupported"); + + /* Just use the segments provided */ + segs = (struct bus_dma_segment *)csio->data_ptr; + ahc_execute_scb(scb, segs, csio->sglist_cnt, 0); + } + } else { + ahc_execute_scb(scb, NULL, 0, 0); + } +} + +static void +ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) { + + if ((scb->flags & SCB_RECOVERY_SCB) == 0) { + struct scb *list_scb; + + scb->flags |= SCB_RECOVERY_SCB; + + /* + * Take all queued, but not sent SCBs out of the equation. + * Also ensure that no new CCBs are queued to us while we + * try to fix this problem. + */ + if ((scb->io_ctx->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { + xpt_freeze_simq(SCB_GET_SIM(ahc, scb), /*count*/1); + scb->io_ctx->ccb_h.status |= CAM_RELEASE_SIMQ; + } + + /* + * Go through all of our pending SCBs and remove + * any scheduled timeouts for them. We will reschedule + * them after we've successfully fixed this problem. + */ + LIST_FOREACH(list_scb, &ahc->pending_scbs, pending_links) { + union ccb *ccb; + + ccb = list_scb->io_ctx; + untimeout(ahc_timeout, list_scb, ccb->ccb_h.timeout_ch); + } + } +} + +void +ahc_timeout(void *arg) +{ + struct scb *scb; + struct ahc_softc *ahc; + long s; + int found; + u_int last_phase; + int target; + int lun; + int i; + char channel; + + scb = (struct scb *)arg; + ahc = (struct ahc_softc *)scb->io_ctx->ccb_h.ccb_ahc_ptr; + + ahc_lock(ahc, &s); + + /* + * Ensure that the card doesn't do anything + * behind our back. Also make sure that we + * didn't "just" miss an interrupt that would + * affect this timeout. + */ + do { + ahc_intr(ahc); + pause_sequencer(ahc); + } while (ahc_inb(ahc, INTSTAT) & INT_PEND); + + ahc_print_path(ahc, scb); + if ((scb->flags & SCB_ACTIVE) == 0) { + /* Previous timeout took care of me already */ + printf("Timedout SCB %d handled by another timeout\n", + scb->hscb->tag); + unpause_sequencer(ahc); + ahc_unlock(ahc, &s); + return; + } + + target = SCB_GET_TARGET(ahc, scb); + channel = SCB_GET_CHANNEL(ahc, scb); + lun = SCB_GET_LUN(scb); + + printf("SCB 0x%x - timed out ", scb->hscb->tag); + /* + * Take a snapshot of the bus state and print out + * some information so we can track down driver bugs. + */ + last_phase = ahc_inb(ahc, LASTPHASE); + + for (i = 0; i < num_phases; i++) { + if (last_phase == phase_table[i].phase) + break; + } + printf("%s", phase_table[i].phasemsg); + + printf(", SEQADDR == 0x%x\n", + ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); + + if (scb->sg_count > 0) { + for (i = 0; i < scb->sg_count; i++) { + printf("sg[%d] - Addr 0x%x : Length %d\n", + i, + scb->sg_list[i].addr, + scb->sg_list[i].len); + } + } + if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { + /* + * Been down this road before. + * Do a full bus reset. + */ +bus_reset: + ahc_set_transaction_status(scb, CAM_CMD_TIMEOUT); + found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); + printf("%s: Issued Channel %c Bus Reset. " + "%d SCBs aborted\n", ahc_name(ahc), channel, found); + } else { + /* + * If we are a target, transition to bus free and report + * the timeout. + * + * The target/initiator that is holding up the bus may not + * be the same as the one that triggered this timeout + * (different commands have different timeout lengths). + * If the bus is idle and we are actiing as the initiator + * for this request, queue a BDR message to the timed out + * target. Otherwise, if the timed out transaction is + * active: + * Initiator transaction: + * Stuff the message buffer with a BDR message and assert + * ATN in the hopes that the target will let go of the bus + * and go to the mesgout phase. If this fails, we'll + * get another timeout 2 seconds later which will attempt + * a bus reset. + * + * Target transaction: + * Transition to BUS FREE and report the error. + * It's good to be the target! + */ + u_int active_scb_index; + + active_scb_index = ahc_inb(ahc, SCB_TAG); + + if (last_phase != P_BUSFREE + && (active_scb_index < ahc->scb_data->numscbs)) { + struct scb *active_scb; + + /* + * If the active SCB is not from our device, + * assume that another device is hogging the bus + * and wait for it's timeout to expire before + * taking additional action. + */ + active_scb = &ahc->scb_data->scbarray[active_scb_index]; + if (active_scb->hscb->scsiid != scb->hscb->scsiid + || active_scb->hscb->lun != scb->hscb->lun) { + struct ccb_hdr *ccbh; + u_int newtimeout; + + ahc_print_path(ahc, scb); + printf("Other SCB Timeout%s", + (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 + ? " again\n" : "\n"); + scb->flags |= SCB_OTHERTCL_TIMEOUT; + newtimeout = + MAX(active_scb->io_ctx->ccb_h.timeout, + scb->io_ctx->ccb_h.timeout); + ccbh = &scb->io_ctx->ccb_h; + scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, scb, + (newtimeout * hz) / 1000); + ahc_unlock(ahc, &s); + return; + } + + /* It's us */ + if ((scb->hscb->control & TARGET_SCB) != 0) { + + /* + * Send back any queued up transactions + * and properly record the error condition. + */ + ahc_freeze_devq(ahc, scb); + ahc_set_transaction_status(scb, + CAM_CMD_TIMEOUT); + ahc_freeze_scb(scb); + ahc_done(ahc, scb); + + /* Will clear us from the bus */ + restart_sequencer(ahc); + return; + } + + ahc_set_recoveryscb(ahc, active_scb); + ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); + ahc_outb(ahc, SCSISIGO, last_phase|ATNO); + ahc_print_path(ahc, active_scb); + printf("BDR message in message buffer\n"); + active_scb->flags |= SCB_DEVICE_RESET; + active_scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); + unpause_sequencer(ahc); + } else { + int disconnected; + + /* XXX Shouldn't panic. Just punt instead */ + if ((scb->hscb->control & TARGET_SCB) != 0) + panic("Timed-out target SCB but bus idle"); + + if (last_phase != P_BUSFREE + && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { + /* XXX What happened to the SCB? */ + /* Hung target selection. Goto busfree */ + printf("%s: Hung target selection\n", + ahc_name(ahc)); + restart_sequencer(ahc); + return; + } + + if (ahc_search_qinfifo(ahc, target, channel, lun, + scb->hscb->tag, ROLE_INITIATOR, + /*status*/0, SEARCH_COUNT) > 0) { + disconnected = FALSE; + } else { + disconnected = TRUE; + } + + if (disconnected) { + u_int active_scb; + + ahc_set_recoveryscb(ahc, scb); + /* + * Simply set the MK_MESSAGE control bit. + */ + scb->hscb->control |= MK_MESSAGE; + scb->flags |= SCB_QUEUED_MSG + | SCB_DEVICE_RESET; + + /* + * Mark the cached copy of this SCB in the + * disconnected list too, so that a reconnect + * at this point causes a BDR or abort. + */ + active_scb = ahc_inb(ahc, SCBPTR); + if (ahc_search_disc_list(ahc, target, + channel, lun, + scb->hscb->tag, + /*stop_on_first*/TRUE, + /*remove*/FALSE, + /*save_state*/FALSE)) { + u_int scb_control; + + scb_control = ahc_inb(ahc, SCB_CONTROL); + scb_control |= MK_MESSAGE; + ahc_outb(ahc, SCB_CONTROL, scb_control); + } + ahc_outb(ahc, SCBPTR, active_scb); + + /* + * Actually re-queue this SCB in case we can + * select the device before it reconnects. + * Clear out any entries in the QINFIFO first + * so we are the next SCB for this target + * to run. + */ + ahc_search_qinfifo(ahc, + SCB_GET_TARGET(ahc, scb), + channel, SCB_GET_LUN(scb), + SCB_LIST_NULL, + ROLE_INITIATOR, + CAM_REQUEUE_REQ, + SEARCH_COMPLETE); + ahc_print_path(ahc, scb); + printf("Queuing a BDR SCB\n"); + ahc->qinfifo[ahc->qinfifonext++] = + scb->hscb->tag; + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + ahc_outb(ahc, HNSCB_QOFF, + ahc->qinfifonext); + } else { + ahc_outb(ahc, KERNEL_QINPOS, + ahc->qinfifonext); + } + scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)scb, 2 * hz); + unpause_sequencer(ahc); + } else { + /* Go "immediatly" to the bus reset */ + /* This shouldn't happen */ + ahc_set_recoveryscb(ahc, scb); + ahc_print_path(ahc, scb); + printf("SCB %d: Immediate reset. " + "Flags = 0x%x\n", scb->hscb->tag, + scb->flags); + goto bus_reset; + } + } + } + ahc_unlock(ahc, &s); +} + +static void +ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) +{ + union ccb *abort_ccb; + + abort_ccb = ccb->cab.abort_ccb; + switch (abort_ccb->ccb_h.func_code) { + case XPT_ACCEPT_TARGET_IO: + case XPT_IMMED_NOTIFY: + case XPT_CONT_TARGET_IO: + { + struct tmode_tstate *tstate; + struct tmode_lstate *lstate; + struct ccb_hdr_slist *list; + cam_status status; + + status = ahc_find_tmode_devs(ahc, sim, abort_ccb, &tstate, + &lstate, TRUE); + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; + break; + } + + if (abort_ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) + list = &lstate->accept_tios; + else if (abort_ccb->ccb_h.func_code == XPT_IMMED_NOTIFY) + list = &lstate->immed_notifies; + else + list = NULL; + + if (list != NULL) { + struct ccb_hdr *curelm; + int found; + + curelm = SLIST_FIRST(list); + found = 0; + if (curelm == &abort_ccb->ccb_h) { + found = 1; + SLIST_REMOVE_HEAD(list, sim_links.sle); + } else { + while(curelm != NULL) { + struct ccb_hdr *nextelm; + + nextelm = + SLIST_NEXT(curelm, sim_links.sle); + + if (nextelm == &abort_ccb->ccb_h) { + found = 1; + SLIST_NEXT(curelm, + sim_links.sle) = + SLIST_NEXT(nextelm, + sim_links.sle); + break; + } + curelm = nextelm; + } + } + + if (found) { + abort_ccb->ccb_h.status = CAM_REQ_ABORTED; + xpt_done(abort_ccb); + ccb->ccb_h.status = CAM_REQ_CMP; + } else { + printf("Not found\n"); + ccb->ccb_h.status = CAM_PATH_INVALID; + } + break; + } + /* FALLTHROUGH */ + } + case XPT_SCSI_IO: + /* XXX Fully implement the hard ones */ + ccb->ccb_h.status = CAM_UA_ABORT; + break; + default: + ccb->ccb_h.status = CAM_REQ_INVALID; + break; + } + xpt_done(ccb); +} + +void +ahc_send_async(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, ac_code code) +{ + struct ahc_devinfo mod_devinfo; + struct ccb_trans_settings cts; + struct cam_path *path; + void *arg; + int error; + + mod_devinfo = *devinfo; + mod_devinfo.lun = CAM_LUN_WILDCARD; + arg = NULL; + error = ahc_create_path(ahc, &mod_devinfo, &path); + + if (error != CAM_REQ_CMP) + return; + + switch (code) { + case AC_TRANSFER_NEG: +#ifdef AHC_NEW_TRAN_SETTINGS + cts.type = CTS_TYPE_CURRENT_SETTINGS; +#else + cts.flags = CCB_TRANS_CURRENT_SETTINGS; +#endif + cts.ccb_h.path = path; + cts.ccb_h.target_id = devinfo->target; + cts.ccb_h.target_lun = devinfo->lun; + ahc_get_tran_settings(ahc, devinfo->our_scsiid, + devinfo->channel, &cts); + arg = &cts; + break; + case AC_SENT_BDR: + case AC_BUS_RESET: + break; + default: + panic("ahc_send_async: Unexpected async event"); + } + xpt_async(code, path, arg); +} + +void +ahc_platform_set_tags(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, int enable) +{ +} + +int +ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg) +{ + ahc->platform_data = + malloc(sizeof(struct ahc_platform_data), M_DEVBUF, M_NOWAIT); + if (ahc->platform_data == NULL) + return (ENOMEM); + memset(ahc->platform_data, 0, sizeof(struct ahc_platform_data)); + return (0); +} + +void +ahc_platform_free(struct ahc_softc *ahc) +{ + if (ahc->platform_data != NULL) { + if (ahc->platform_data->regs != NULL) + bus_release_resource(ahc->dev_softc, + ahc->platform_data->regs_res_type, + ahc->platform_data->regs_res_id, + ahc->platform_data->regs); + + if (ahc->platform_data->irq != NULL) + bus_release_resource(ahc->dev_softc, + ahc->platform_data->irq_res_type, + 0, ahc->platform_data->irq); + + free(ahc->platform_data, M_DEVBUF); + } +} + +int +ahc_softc_comp(struct ahc_softc *lahc, struct ahc_softc *rahc) +{ + /* We don't sort softcs under FreeBSD so report equal always */ + return (0); +} + +#if UNUSED +static void +ahc_dump_targcmd(struct target_cmd *cmd) +{ + uint8_t *byte; + uint8_t *last_byte; + int i; + + byte = &cmd->initiator_channel; + /* Debugging info for received commands */ + last_byte = &cmd[1].initiator_channel; + + i = 0; + while (byte < last_byte) { + if (i == 0) + printf("\t"); + printf("%#x", *byte++); + i++; + if (i == 8) { + printf("\n"); + i = 0; + } else { + printf(", "); + } + } +} +#endif diff --git a/sys/dev/aic7xxx/aic7xxx_freebsd.h b/sys/dev/aic7xxx/aic7xxx_freebsd.h new file mode 100644 index 000000000000..eefc09ed6f0e --- /dev/null +++ b/sys/dev/aic7xxx/aic7xxx_freebsd.h @@ -0,0 +1,451 @@ +/* + * FreeBSD platform specific driver option settings, data structures, + * function declarations and includes. + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#ifndef _AIC7XXX_FREEBSD_H_ +#define _AIC7XXX_FREEBSD_H_ + +#include <opt_aic7xxx.h> /* for config options */ +#include <pci.h> /* for NPCI */ + +#include <stddef.h> /* For offsetof */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> /* For device_t */ +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/queue.h> + +#if NPCI > 0 +#define AHC_SUPPORT_PCI 1 +#include <machine/bus_memio.h> +#endif +#include <machine/bus_pio.h> +#include <machine/bus.h> +#include <machine/clock.h> +#include <machine/resource.h> + +#include <sys/rman.h> + +#if NPCI > 0 +#include <pci/pcireg.h> +#include <pci/pcivar.h> +#endif + +#include <cam/cam.h> +#include <cam/cam_ccb.h> +#include <cam/cam_debug.h> +#include <cam/cam_sim.h> +#include <cam/cam_xpt_sim.h> + +#include <cam/scsi/scsi_all.h> +#include <cam/scsi/scsi_message.h> + +/****************************** Platform Macros *******************************/ +#define SIM_IS_SCSIBUS_B(ahc, sim) \ + ((sim) == ahc->platform_data->sim_b) +#define SIM_CHANNEL(ahc, sim) \ + (((sim) == ahc->platform_data->sim_b) ? 'B' : 'A') +#define SIM_SCSI_ID(ahc, sim) \ + (((sim) == ahc->platform_data->sim_b) ? ahc->our_id_b : ahc->our_id) +#define SIM_PATH(ahc, sim) \ + (((sim) == ahc->platform_data->sim_b) ? ahc->platform_data->path_b \ + : ahc->platform_data->path) +#define BUILD_SCSIID(ahc, sim, target_id, our_id) \ + ((((target_id) << TID_SHIFT) & TID) | (our_id) \ + | (SIM_IS_SCSIBUS_B(ahc, sim) ? TWIN_CHNLB : 0)) + +#define SCB_GET_SIM(ahc, scb) \ + (SCB_GET_CHANNEL(ahc, scb) == 'A' ? (ahc)->platform_data->sim \ + : (ahc)->platform_data->sim_b) + +/************************* Forward Declarations *******************************/ +typedef device_t ahc_dev_softc_t; +typedef union ccb *ahc_io_ctx_t; + +/***************************** Bus Space/DMA **********************************/ +#define ahc_dma_tag_create(ahc, parent_tag, alignment, boundary, \ + lowaddr, highaddr, filter, filterarg, \ + maxsize, nsegments, maxsegsz, flags, \ + dma_tagp) \ + bus_dma_tag_create(parent_tag, alignment, boundary, \ + lowaddr, highaddr, filter, filterarg, \ + maxsize, nsegments, maxsegsz, flags, \ + dma_tagp) + +#define ahc_dma_tag_destroy(ahc, tag) \ + bus_dma_tag_destroy(tag) + +#define ahc_dmamem_alloc(ahc, dmat, vaddr, flags, mapp) \ + bus_dmamem_alloc(dmat, vaddr, flags, mapp) + +#define ahc_dmamem_free(ahc, dmat, vaddr, map) \ + bus_dmamem_free(dmat, vaddr, map) + +#define ahc_dmamap_create(ahc, tag, flags, mapp) \ + bus_dmamap_create(tag, flags, mapp) + +#define ahc_dmamap_destroy(ahc, tag, map) \ + bus_dmamap_destroy(tag, map) + +#define ahc_dmamap_load(ahc, dmat, map, addr, buflen, callback, \ + callback_arg, flags) \ + bus_dmamap_load(dmat, map, addr, buflen, callback, callback_arg, flags) + +#define ahc_dmamap_unload(ahc, tag, map) \ + bus_dmamap_unload(tag, map) + +#define ahc_dmamap_sync(ahc, dma_tag, dmamap, op) \ + bus_dmamap_sync(dma_tag_dmamap, op) + +/************************ Tunable Driver Parameters **************************/ +/* + * The number of dma segments supported. The sequencer can handle any number + * of physically contiguous S/G entrys. To reduce the driver's memory + * consumption, we limit the number supported to be sufficient to handle + * the largest mapping supported by the kernel, MAXPHYS. Assuming the + * transfer is as fragmented as possible and unaligned, this turns out to + * be the number of paged sized transfers in MAXPHYS plus an extra element + * to handle any unaligned residual. The sequencer fetches SG elements + * in 128 byte chucks, so make the number per-transaction a nice multiple + * of 16 (8 byte S/G elements). + */ +/* XXX Worth the space??? */ +#define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16)) + +/* This driver supports target mode */ +#define AHC_TARGET_MODE 1 + +/************************** Softc/SCB Platform Data ***************************/ +struct ahc_platform_data { + /* + * Hooks into the XPT. + */ + struct cam_sim *sim; + struct cam_sim *sim_b; + struct cam_path *path; + struct cam_path *path_b; + + int regs_res_type; + int regs_res_id; + int irq_res_type; + struct resource *regs; + struct resource *irq; + void *ih; +}; + +struct scb_platform_data { +}; + +/***************************** Core Includes **********************************/ +#include <dev/aic7xxx/aic7xxx.h> + +/*************************** Device Access ************************************/ +#define ahc_inb(ahc, port) \ + bus_space_read_1((ahc)->tag, (ahc)->bsh, port) + +#define ahc_outb(ahc, port, value) \ + bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) + +#define ahc_outsb(ahc, port, valp, count) \ + bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) + +#define ahc_insb(ahc, port, valp, count) \ + bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) + +static __inline void ahc_flush_device_writes(struct ahc_softc *); + +static __inline void +ahc_flush_device_writes(struct ahc_softc *ahc) +{ + /* XXX Is this sufficient for all architectures??? */ + ahc_inb(ahc, INTSTAT); +} + +/**************************** Locking Primitives ******************************/ +/* Lock protecting internal data structures */ +static __inline void ahc_lockinit(struct ahc_softc *); +static __inline void ahc_lock(struct ahc_softc *, unsigned long *flags); +static __inline void ahc_unlock(struct ahc_softc *, unsigned long *flags); + +/* Lock held during command compeletion to the upper layer */ +static __inline void ahc_done_lockinit(struct ahc_softc *); +static __inline void ahc_done_lock(struct ahc_softc *, unsigned long *flags); +static __inline void ahc_done_unlock(struct ahc_softc *, unsigned long *flags); + +static __inline void +ahc_lockinit(struct ahc_softc *ahc) +{ +} + +static __inline void +ahc_lock(struct ahc_softc *ahc, unsigned long *flags) +{ + *flags = splcam(); +} + +static __inline void +ahc_unlock(struct ahc_softc *ahc, unsigned long *flags) +{ + splx(*flags); +} + +/* Lock held during command compeletion to the upper layer */ +static __inline void +ahc_done_lockinit(struct ahc_softc *ahc) +{ +} + +static __inline void +ahc_done_lock(struct ahc_softc *ahc, unsigned long *flags) +{ +} + +static __inline void +ahc_done_unlock(struct ahc_softc *ahc, unsigned long *flags) +{ +} + +/****************************** OS Primitives *********************************/ +#define ahc_delay DELAY + +/************************** Transaction Operations ****************************/ +static __inline void ahc_set_transaction_status(struct scb *, uint32_t); +static __inline void ahc_set_scsi_status(struct scb *, uint32_t); +static __inline uint32_t ahc_get_transaction_status(struct scb *); +static __inline uint32_t ahc_get_scsi_status(struct scb *); +static __inline void ahc_set_transaction_tag(struct scb *, int, u_int); +static __inline u_long ahc_get_transfer_length(struct scb *); +static __inline int ahc_get_transfer_dir(struct scb *); +static __inline void ahc_set_residual(struct scb *, u_long); +static __inline void ahc_set_sense_residual(struct scb *, u_long); +static __inline u_long ahc_get_residual(struct scb *); +static __inline int ahc_perform_autosense(struct scb *); +static __inline uint32_t ahc_get_sense_bufsize(struct ahc_softc*, struct scb*); +static __inline void ahc_freeze_ccb(union ccb *ccb); +static __inline void ahc_freeze_scb(struct scb *scb); +static __inline void ahc_platform_freeze_devq(struct ahc_softc *, struct scb *); +static __inline int ahc_platform_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status); + +static __inline +void ahc_set_transaction_status(struct scb *scb, uint32_t status) +{ + scb->io_ctx->ccb_h.status &= ~CAM_STATUS_MASK; + scb->io_ctx->ccb_h.status |= status; +} + +static __inline +void ahc_set_scsi_status(struct scb *scb, uint32_t status) +{ + scb->io_ctx->csio.scsi_status = status; +} + +static __inline +uint32_t ahc_get_transaction_status(struct scb *scb) +{ + return (scb->io_ctx->ccb_h.status & CAM_STATUS_MASK); +} + +static __inline +uint32_t ahc_get_scsi_status(struct scb *scb) +{ + return (scb->io_ctx->csio.scsi_status); +} + +static __inline +void ahc_set_transaction_tag(struct scb *scb, int enabled, u_int type) +{ + scb->io_ctx->csio.tag_action = type; + if (enabled) + scb->io_ctx->ccb_h.flags |= CAM_TAG_ACTION_VALID; + else + scb->io_ctx->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; +} + +static __inline +u_long ahc_get_transfer_length(struct scb *scb) +{ + return (scb->io_ctx->csio.dxfer_len); +} + +static __inline +int ahc_get_transfer_dir(struct scb *scb) +{ + return (scb->io_ctx->ccb_h.flags & CAM_DIR_MASK); +} + +static __inline +void ahc_set_residual(struct scb *scb, u_long resid) +{ + scb->io_ctx->csio.resid = resid; +} + +static __inline +void ahc_set_sense_residual(struct scb *scb, u_long resid) +{ + scb->io_ctx->csio.sense_resid = resid; +} + +static __inline +u_long ahc_get_residual(struct scb *scb) +{ + return (scb->io_ctx->csio.resid); +} + +static __inline +int ahc_perform_autosense(struct scb *scb) +{ + return (!(scb->io_ctx->ccb_h.flags & CAM_DIS_AUTOSENSE)); +} + +static __inline uint32_t +ahc_get_sense_bufsize(struct ahc_softc *ahc, struct scb *scb) +{ + return (sizeof(struct scsi_sense_data)); +} + +static __inline void +ahc_freeze_ccb(union ccb *ccb) +{ + if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { + ccb->ccb_h.status |= CAM_DEV_QFRZN; + xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); + } +} + +static __inline void +ahc_freeze_scb(struct scb *scb) +{ + ahc_freeze_ccb(scb->io_ctx); +} + +static __inline void +ahc_platform_freeze_devq(struct ahc_softc *ahc, struct scb *scb) +{ + /* Nothing to do here for FreeBSD */ +} + +static __inline int +ahc_platform_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status) +{ + /* Nothing to do here for FreeBSD */ + return (0); +} + +/********************************** PCI ***************************************/ +#ifdef AHC_SUPPORT_PCI +static __inline uint32_t ahc_pci_read_config(ahc_dev_softc_t pci, + int reg, int width); +static __inline void ahc_pci_write_config(ahc_dev_softc_t pci, + int reg, uint32_t value, + int width); +static __inline int ahc_get_pci_function(ahc_dev_softc_t); +static __inline int ahc_get_pci_slot(ahc_dev_softc_t); +static __inline int ahc_get_pci_bus(ahc_dev_softc_t); + +int ahc_pci_map_registers(struct ahc_softc *ahc); +int ahc_pci_map_int(struct ahc_softc *ahc); + +static __inline uint32_t +ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width) +{ + return (pci_read_config(pci, reg, width)); +} + +static __inline void +ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width) +{ + pci_write_config(pci, reg, value, width); +} + +static __inline int +ahc_get_pci_function(ahc_dev_softc_t pci) +{ + return (pci_get_function(pci)); +} + +static __inline int +ahc_get_pci_slot(ahc_dev_softc_t pci) +{ + return (pci_get_slot(pci)); +} + +static __inline int +ahc_get_pci_bus(ahc_dev_softc_t pci) +{ + return (pci_get_bus(pci)); +} +#endif +/******************************** VL/EISA *************************************/ +int aic7770_map_registers(struct ahc_softc *ahc); +int aic7770_map_int(struct ahc_softc *ahc); + +/********************************* Debug **************************************/ +static __inline void ahc_print_path(struct ahc_softc *, struct scb *); +static __inline void ahc_platform_dump_card_state(struct ahc_softc *ahc); + +static __inline void +ahc_print_path(struct ahc_softc *ahc, struct scb *scb) +{ + xpt_print_path(scb->io_ctx->ccb_h.path); +} + +static __inline void +ahc_platform_dump_card_state(struct ahc_softc *ahc) +{ + /* Nothing to do here for FreeBSD */ +} +/**************************** Transfer Settings *******************************/ +void ahc_notify_xfer_settings_change(struct ahc_softc *, + struct ahc_devinfo *); +void ahc_platform_set_tags(struct ahc_softc *, struct ahc_devinfo *, + int /*enable*/); + +/***************************** Initialization *********************************/ +int ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg); +void ahc_platform_free(struct ahc_softc *ahc); +int ahc_attach(struct ahc_softc *); +int ahc_softc_comp(struct ahc_softc *lahc, struct ahc_softc *rahc); + +/************************ Misc Function Declarations **************************/ +timeout_t ahc_timeout; +void ahc_done(struct ahc_softc *ahc, struct scb *scb); +void ahc_send_async(struct ahc_softc *, struct ahc_devinfo *, ac_code); +#endif /* _AIC7XXX_FREEBSD_H_ */ diff --git a/sys/dev/aic7xxx/aic7xxx_inline.h b/sys/dev/aic7xxx/aic7xxx_inline.h new file mode 100644 index 000000000000..4bd8c13abd35 --- /dev/null +++ b/sys/dev/aic7xxx/aic7xxx_inline.h @@ -0,0 +1,366 @@ +/* + * Inline routines shareable across OS platforms. + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#ifndef _AIC7XXX_INLINE_H_ +#define _AIC7XXX_INLINE_H_ + +/************************* Sequencer Execution Control ************************/ +static __inline int sequencer_paused(struct ahc_softc *ahc); +static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); +static __inline void pause_sequencer(struct ahc_softc *ahc); +static __inline void unpause_sequencer(struct ahc_softc *ahc); + +/* + * Work around any chip bugs related to halting sequencer execution. + * On Ultra2 controllers, we must clear the CIOBUS stretch signal by + * reading a register that will set this signal and deassert it. + * Without this workaround, if the chip is paused, by an interrupt or + * manual pause while accessing scb ram, accesses to certain registers + * will hang the system (infinite pci retries). + */ +static __inline void +ahc_pause_bug_fix(struct ahc_softc *ahc) +{ + if ((ahc->features & AHC_ULTRA2) != 0) + (void)ahc_inb(ahc, CCSCBCTL); +} + +/* + * Determine whether the sequencer has halted code execution. + * Returns non-zero status if the sequencer is stopped. + */ +static __inline int +sequencer_paused(struct ahc_softc *ahc) +{ + return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); +} + +/* + * Request that the sequencer stop and wait, indefinitely, for it + * to stop. The sequencer will only acknowledge that it is paused + * once it has reached an instruction boundary and PAUSEDIS is + * cleared in the SEQCTL register. The sequencer may use PAUSEDIS + * for critical sections. + */ +static __inline void +pause_sequencer(struct ahc_softc *ahc) +{ + ahc_outb(ahc, HCNTRL, ahc->pause); + + /* + * Since the sequencer can disable pausing in a critical section, we + * must loop until it actually stops. + */ + while (sequencer_paused(ahc) == 0) + ; + + ahc_pause_bug_fix(ahc); +} + +/* + * Allow the sequencer to continue program execution. + * We check here to ensure that no additional interrupt + * sources that would cause the sequencer to halt have been + * asserted. If, for example, a SCSI bus reset is detected + * while we are fielding a different, pausing, interrupt type, + * we don't want to release the sequencer before going back + * into our interrupt handler and dealing with this new + * condition. + */ +static __inline void +unpause_sequencer(struct ahc_softc *ahc) +{ + if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) + ahc_outb(ahc, HCNTRL, ahc->unpause); +} + +/*********************** Untagged Transaction Routines ************************/ +u_int ahc_index_busy_tcl(struct ahc_softc *ahc, + u_int tcl, int unbusy); +static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc); +static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc); + +/* + * Block our completion routine from starting the next untagged + * transaction for this target or target lun. + */ +static __inline void +ahc_freeze_untagged_queues(struct ahc_softc *ahc) +{ + if ((ahc->features & AHC_SCB_BTT) == 0) + ahc->untagged_queue_lock++; +} + +/* + * Allow the next untagged transaction for this target or target lun + * to be executed. We use a counting semaphore to allow the lock + * to be acquired recursively. Once the count drops to zero, the + * transaction queues will be run. + */ +static __inline void +ahc_release_untagged_queues(struct ahc_softc *ahc) +{ + if ((ahc->features & AHC_SCB_BTT) == 0) { + ahc->untagged_queue_lock--; + if (ahc->untagged_queue_lock == 0) + ahc_run_untagged_queues(ahc); + } +} + +/************************** Memory mapping routines ***************************/ +static __inline struct ahc_dma_seg * + ahc_sg_bus_to_virt(struct scb *scb, + uint32_t sg_busaddr); +static __inline uint32_t + ahc_sg_virt_to_bus(struct scb *scb, + struct ahc_dma_seg *sg); +static __inline uint32_t + ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index); + +static __inline struct ahc_dma_seg * +ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) +{ + int sg_index; + + sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg); + /* sg_list_phys points to entry 1, not 0 */ + sg_index++; + + return (&scb->sg_list[sg_index]); +} + +static __inline uint32_t +ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg) +{ + int sg_index; + + /* sg_list_phys points to entry 1, not 0 */ + sg_index = sg - &scb->sg_list[1]; + + return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list))); +} + +static __inline uint32_t +ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) +{ + return (ahc->scb_data->hscb_busaddr + + (sizeof(struct hardware_scb) * index)); +} + +/******************************** Debugging ***********************************/ +static __inline char *ahc_name(struct ahc_softc *ahc); + +static __inline char * +ahc_name(struct ahc_softc *ahc) +{ + return (ahc->name); +} + +/*********************** Miscelaneous Support Functions ***********************/ + +static __inline int ahc_check_residual(struct scb *scb); +static __inline struct ahc_initiator_tinfo * + ahc_fetch_transinfo(struct ahc_softc *ahc, + char channel, u_int our_id, + u_int remote_id, + struct tmode_tstate **tstate); +static __inline struct scb* + ahc_get_scb(struct ahc_softc *ahc); +static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); +static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb); + +/* + * Determine whether the sequencer reported a residual + * for this SCB/transaction. + */ +static __inline int +ahc_check_residual(struct scb *scb) +{ + struct status_pkt *sp; + + sp = &scb->hscb->shared_data.status; + if ((scb->hscb->sgptr & SG_RESID_VALID) != 0) + return (1); + return (0); +} + +/* + * Return pointers to the transfer negotiation information + * for the specified our_id/remote_id pair. + */ +static __inline struct ahc_initiator_tinfo * +ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, + u_int remote_id, struct tmode_tstate **tstate) +{ + /* + * Transfer data structures are stored from the perspective + * of the target role. Since the parameters for a connection + * in the initiator role to a given target are the same as + * when the roles are reversed, we pretend we are the target. + */ + if (channel == 'B') + our_id += 8; + *tstate = ahc->enabled_targets[our_id]; + return (&(*tstate)->transinfo[remote_id]); +} + +/* + * Get a free scb. If there are none, see if we can allocate a new SCB. + */ +static __inline struct scb * +ahc_get_scb(struct ahc_softc *ahc) +{ + struct scb *scbp; + + if ((scbp = SLIST_FIRST(&ahc->scb_data->free_scbs))) { + SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); + } else { + ahc_alloc_scbs(ahc); + scbp = SLIST_FIRST(&ahc->scb_data->free_scbs); + if (scbp != NULL) + SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); + } + + return (scbp); +} + +/* + * Return an SCB resource to the free list. + */ +static __inline void +ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) +{ + struct hardware_scb *hscb; + + hscb = scb->hscb; +#if 0 + /* What do we do to generically handle driver resource shortages??? */ + if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 + && (scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { + scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; + ahc->flags &= ~AHC_RESOURCE_SHORTAGE; + } +#endif + /* Clean up for the next user */ + scb->flags = SCB_FREE; + hscb->control = 0; + + SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle); +} + +/* + * Tell the sequencer about a new transaction to execute. + */ +static __inline void +ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb) +{ + ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); + } else { + if ((ahc->features & AHC_AUTOPAUSE) == 0) + pause_sequencer(ahc); + ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); + if ((ahc->features & AHC_AUTOPAUSE) == 0) + unpause_sequencer(ahc); + } +} + +/************************** Interrupt Processing ******************************/ +static __inline void ahc_intr(struct ahc_softc *ahc); + +/* + * Catch an interrupt from the adapter + */ +static __inline void +ahc_intr(struct ahc_softc *ahc) +{ + u_int intstat; + + intstat = ahc_inb(ahc, INTSTAT); + + /* + * Any interrupts to process? + */ +#if AHC_PCI_CONFIG > 0 + if ((intstat & INT_PEND) == 0) { + if ((ahc->chip & AHC_PCI) != 0 + && (ahc->unsolicited_ints > 500)) { + if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) + ahc_pci_intr(ahc); + ahc->unsolicited_ints = 0; + } else { + ahc->unsolicited_ints++; + } + return; + } else { + ahc->unsolicited_ints = 0; + } +#else + if ((intstat & INT_PEND) == 0) + return; +#endif + + if (intstat & CMDCMPLT) { + ahc_outb(ahc, CLRINT, CLRCMDINT); + /* + * Ensure that the chip sees that we've cleared + * this interrupt before we walk the output fifo. + * Otherwise, we may, due to posted bus writes, + * clear the interrupt after we finish the scan, + * and after the sequencer has added new entries + * and asserted the interrupt again. + */ + ahc_flush_device_writes(ahc); + ahc_run_qoutfifo(ahc); +#ifdef AHC_TARGET_MODE + if ((ahc->flags & AHC_TARGETMODE) != 0) + ahc_run_tqinfifo(ahc, /*paused*/FALSE); +#endif + } + if (intstat & BRKADRINT) + ahc_handle_brkadrint(ahc); + + if ((intstat & (SEQINT|SCSIINT)) != 0) + ahc_pause_bug_fix(ahc); + + if ((intstat & SEQINT) != 0) + ahc_handle_seqint(ahc, intstat); + + if ((intstat & SCSIINT) != 0) + ahc_handle_scsiint(ahc, intstat); +} + +#endif /* _AIC7XXX_INLINE_H_ */ diff --git a/sys/dev/aic7xxx/aic7xxx_osm.c b/sys/dev/aic7xxx/aic7xxx_osm.c new file mode 100644 index 000000000000..c9c8f5a2fefd --- /dev/null +++ b/sys/dev/aic7xxx/aic7xxx_osm.c @@ -0,0 +1,1823 @@ +/* + * Bus independent FreeBSD shim for the aic7xxx based adaptec SCSI controllers + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> + +#include <sys/eventhandler.h> + +#ifndef AHC_TMODE_ENABLE +#define AHC_TMODE_ENABLE 0 +#endif + +#define ccb_scb_ptr spriv_ptr0 +#define ccb_ahc_ptr spriv_ptr1 + +#ifdef AHC_DEBUG +static int ahc_debug = AHC_DEBUG; +#endif + +static void ahc_freebsd_intr(void *arg); + +#if UNUSED +static void ahc_dump_targcmd(struct target_cmd *cmd); +#endif +static void ahc_action(struct cam_sim *sim, union ccb *ccb); +static void ahc_get_tran_settings(struct ahc_softc *ahc, + int our_id, char channel, + struct ccb_trans_settings *cts); +static void ahc_async(void *callback_arg, uint32_t code, + struct cam_path *path, void *arg); +static void ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, + int nsegments, int error); +static void ahc_poll(struct cam_sim *sim); +static void ahc_setup_data(struct ahc_softc *ahc, struct cam_sim *sim, + struct ccb_scsiio *csio, struct scb *scb); +static void ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, + union ccb *ccb); +static int ahc_create_path(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, + struct cam_path **path); + +static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); + +static int +ahc_create_path(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, + struct cam_path **path) +{ + path_id_t path_id; + + if (devinfo->channel == 'B') + path_id = cam_sim_path(ahc->platform_data->sim_b); + else + path_id = cam_sim_path(ahc->platform_data->sim); + + return (xpt_create_path(path, /*periph*/NULL, + path_id, devinfo->target, + devinfo->lun)); +} + +/* + * Attach all the sub-devices we can find + */ +int +ahc_attach(struct ahc_softc *ahc) +{ + char ahc_info[256]; + struct ccb_setasync csa; + struct cam_devq *devq; + int bus_id; + int bus_id2; + struct cam_sim *sim; + struct cam_sim *sim2; + struct cam_path *path; + struct cam_path *path2; + long s; + int count; + int error; + + count = 0; + sim = NULL; + sim2 = NULL; + + ahc_controller_info(ahc, ahc_info); + printf("%s\n", ahc_info); + ahc_lock(ahc, &s); + /* Hook up our interrupt handler */ + if ((error = bus_setup_intr(ahc->dev_softc, ahc->platform_data->irq, + INTR_TYPE_CAM, ahc_freebsd_intr, ahc, + &ahc->platform_data->ih)) != 0) { + device_printf(ahc->dev_softc, "bus_setup_intr() failed: %d\n", + error); + goto fail; + } + + /* + * Attach secondary channel first if the user has + * declared it the primary channel. + */ + if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { + bus_id = 1; + bus_id2 = 0; + } else { + bus_id = 0; + bus_id2 = 1; + } + + /* + * Create the device queue for our SIM(s). + */ + devq = cam_simq_alloc(AHC_SCB_MAX); + if (devq == NULL) + goto fail; + + /* + * Construct our first channel SIM entry + */ + sim = cam_sim_alloc(ahc_action, ahc_poll, "ahc", ahc, ahc->unit, + 1, AHC_SCB_MAX, devq); + if (sim == NULL) { + cam_simq_free(devq); + goto fail; + } + + if (xpt_bus_register(sim, bus_id) != CAM_SUCCESS) { + cam_sim_free(sim, /*free_devq*/TRUE); + sim = NULL; + goto fail; + } + + if (xpt_create_path(&path, /*periph*/NULL, + cam_sim_path(sim), CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD) != CAM_REQ_CMP) { + xpt_bus_deregister(cam_sim_path(sim)); + cam_sim_free(sim, /*free_devq*/TRUE); + sim = NULL; + goto fail; + } + + xpt_setup_ccb(&csa.ccb_h, path, /*priority*/5); + csa.ccb_h.func_code = XPT_SASYNC_CB; + csa.event_enable = AC_LOST_DEVICE; + csa.callback = ahc_async; + csa.callback_arg = sim; + xpt_action((union ccb *)&csa); + count++; + + if (ahc->features & AHC_TWIN) { + sim2 = cam_sim_alloc(ahc_action, ahc_poll, "ahc", + ahc, ahc->unit, 1, + AHC_SCB_MAX, devq); + + if (sim2 == NULL) { + printf("ahc_attach: Unable to attach second " + "bus due to resource shortage"); + goto fail; + } + + if (xpt_bus_register(sim2, bus_id2) != CAM_SUCCESS) { + printf("ahc_attach: Unable to attach second " + "bus due to resource shortage"); + /* + * We do not want to destroy the device queue + * because the first bus is using it. + */ + cam_sim_free(sim2, /*free_devq*/FALSE); + goto fail; + } + + if (xpt_create_path(&path2, /*periph*/NULL, + cam_sim_path(sim2), + CAM_TARGET_WILDCARD, + CAM_LUN_WILDCARD) != CAM_REQ_CMP) { + xpt_bus_deregister(cam_sim_path(sim2)); + cam_sim_free(sim2, /*free_devq*/FALSE); + sim2 = NULL; + goto fail; + } + xpt_setup_ccb(&csa.ccb_h, path2, /*priority*/5); + csa.ccb_h.func_code = XPT_SASYNC_CB; + csa.event_enable = AC_LOST_DEVICE; + csa.callback = ahc_async; + csa.callback_arg = sim2; + xpt_action((union ccb *)&csa); + count++; + } + +fail: + if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { + ahc->platform_data->sim_b = sim; + ahc->platform_data->path_b = path; + ahc->platform_data->sim = sim2; + ahc->platform_data->path = path2; + } else { + ahc->platform_data->sim = sim; + ahc->platform_data->path = path; + ahc->platform_data->sim_b = sim2; + ahc->platform_data->path_b = path2; + } + ahc_unlock(ahc, &s); + + if (count != 0) + /* We have to wait until after any system dumps... */ + EVENTHANDLER_REGISTER(shutdown_final, ahc_shutdown, + ahc, SHUTDOWN_PRI_DEFAULT); + + return (count); +} + +/* + * Catch an interrupt from the adapter + */ +void +ahc_freebsd_intr(void *arg) +{ + struct ahc_softc *ahc; + + ahc = (struct ahc_softc *)arg; + ahc_intr(ahc); +} + +/* + * We have an scb which has been processed by the + * adaptor, now we look to see how the operation + * went. + */ +void +ahc_done(struct ahc_softc *ahc, struct scb *scb) +{ + union ccb *ccb; + + CAM_DEBUG(scb->io_ctx->ccb_h.path, CAM_DEBUG_TRACE, + ("ahc_done - scb %d\n", scb->hscb->tag)); + + ccb = scb->io_ctx; + LIST_REMOVE(scb, pending_links); + if (ccb->ccb_h.func_code == XPT_SCSI_IO + && ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0 + || ccb->csio.tag_action == CAM_TAG_ACTION_NONE) + && (ahc->features & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + + untagged_q = &ahc->untagged_queues[ccb->ccb_h.target_id]; + TAILQ_REMOVE(untagged_q, scb, links.tqe); + ahc_run_untagged_queue(ahc, untagged_q); + } + + untimeout(ahc_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch); + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { + bus_dmasync_op_t op; + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + op = BUS_DMASYNC_POSTREAD; + else + op = BUS_DMASYNC_POSTWRITE; + bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op); + bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); + } + + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + if (ahc_get_transaction_status(scb) == CAM_REQ_INPROG) + ccb->ccb_h.status |= CAM_REQ_CMP; + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ahc_free_scb(ahc, scb); + xpt_done(ccb); + return; + } + + /* + * If the recovery SCB completes, we have to be + * out of our timeout. + */ + if ((scb->flags & SCB_RECOVERY_SCB) != 0) { + struct scb *list_scb; + + /* + * We were able to complete the command successfully, + * so reinstate the timeouts for all other pending + * commands. + */ + LIST_FOREACH(list_scb, &ahc->pending_scbs, pending_links) { + union ccb *ccb; + + ccb = list_scb->io_ctx; + ccb->ccb_h.timeout_ch = + timeout(ahc_timeout, list_scb, + (ccb->ccb_h.timeout * hz)/1000); + } + + /* + * Ensure that we didn't put a second instance of this + * SCB into the QINFIFO. + */ + ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), + SCB_GET_CHANNEL(ahc, scb), + SCB_GET_LUN(scb), scb->hscb->tag, + ROLE_INITIATOR, /*status*/0, + SEARCH_REMOVE); + if (ahc_get_transaction_status(scb) == CAM_BDR_SENT + || ahc_get_transaction_status(scb) == CAM_REQ_ABORTED) + ahc_set_transaction_status(scb, CAM_CMD_TIMEOUT); + ahc_print_path(ahc, scb); + printf("no longer in timeout, status = %x\n", + ccb->ccb_h.status); + } + + /* Don't clobber any existing error state */ + if (ahc_get_transaction_status(scb) == CAM_REQ_INPROG) { + ccb->ccb_h.status |= CAM_REQ_CMP; + } else if ((scb->flags & SCB_SENSE) != 0) { + /* + * We performed autosense retrieval. + * + * Zero any sense not transferred by the + * device. The SCSI spec mandates that any + * untransfered data should be assumed to be + * zero. Complete the 'bounce' of sense information + * through buffers accessible via bus-space by + * copying it into the clients csio. + */ + memset(&ccb->csio.sense_data, 0, sizeof(ccb->csio.sense_data)); + memcpy(&ccb->csio.sense_data, + &ahc->scb_data->sense[scb->hscb->tag], + (scb->sg_list->len & AHC_SG_LEN_MASK) + - ccb->csio.sense_resid); + scb->io_ctx->ccb_h.status |= CAM_AUTOSNS_VALID; + } + ccb->ccb_h.status &= ~CAM_SIM_QUEUED; + ahc_free_scb(ahc, scb); + xpt_done(ccb); +} + +static void +ahc_action(struct cam_sim *sim, union ccb *ccb) +{ + struct ahc_softc *ahc; + struct tmode_lstate *lstate; + u_int target_id; + u_int our_id; + long s; + + CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahc_action\n")); + + ahc = (struct ahc_softc *)cam_sim_softc(sim); + + target_id = ccb->ccb_h.target_id; + our_id = SIM_SCSI_ID(ahc, sim); + + switch (ccb->ccb_h.func_code) { + /* Common cases first */ + case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ + case XPT_CONT_TARGET_IO:/* Continue Host Target I/O Connection*/ + { + struct tmode_tstate *tstate; + cam_status status; + + status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, + &lstate, TRUE); + + if (status != CAM_REQ_CMP) { + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + /* Response from the black hole device */ + tstate = NULL; + lstate = ahc->black_hole; + } else { + ccb->ccb_h.status = status; + xpt_done(ccb); + break; + } + } + if (ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) { + + ahc_lock(ahc, &s); + SLIST_INSERT_HEAD(&lstate->accept_tios, &ccb->ccb_h, + sim_links.sle); + ccb->ccb_h.status = CAM_REQ_INPROG; + if ((ahc->flags & AHC_TQINFIFO_BLOCKED) != 0) + ahc_run_tqinfifo(ahc, /*paused*/FALSE); + ahc_unlock(ahc, &s); + break; + } + + /* + * The target_id represents the target we attempt to + * select. In target mode, this is the initiator of + * the original command. + */ + our_id = target_id; + target_id = ccb->csio.init_id; + /* FALLTHROUGH */ + } + case XPT_SCSI_IO: /* Execute the requested I/O operation */ + case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ + { + struct scb *scb; + struct hardware_scb *hscb; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t mask; + + /* + * get an scb to use. + */ + if ((scb = ahc_get_scb(ahc)) == NULL) { + + ahc_lock(ahc, &s); + ahc->flags |= AHC_RESOURCE_SHORTAGE; + ahc_unlock(ahc, &s); + xpt_freeze_simq(sim, /*count*/1); + ahc_set_transaction_status(scb, CAM_REQUEUE_REQ); + xpt_done(ccb); + return; + } + + hscb = scb->hscb; + + CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_SUBTRACE, + ("start scb(%p)\n", scb)); + scb->io_ctx = ccb; + /* + * So we can find the SCB when an abort is requested + */ + ccb->ccb_h.ccb_scb_ptr = scb; + ccb->ccb_h.ccb_ahc_ptr = ahc; + + /* + * Put all the arguments for the xfer in the scb + */ + hscb->control = 0; + hscb->scsiid = BUILD_SCSIID(ahc, sim, target_id, our_id); + hscb->lun = ccb->ccb_h.target_lun; + mask = SCB_GET_TARGET_MASK(ahc, scb); + tinfo = ahc_fetch_transinfo(ahc, SIM_CHANNEL(ahc, sim), our_id, + target_id, &tstate); + + hscb->scsirate = tinfo->scsirate; + hscb->scsioffset = tinfo->current.offset; + if ((tstate->ultraenb & mask) != 0) + hscb->control |= ULTRAENB; + + if ((tstate->discenable & mask) != 0 + && (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0) + hscb->control |= DISCENB; + + if ((ccb->ccb_h.flags & CAM_NEGOTIATE) != 0 + && (tinfo->current.width != 0 || tinfo->current.period != 0)) { + scb->flags |= SCB_NEGOTIATE; + hscb->control |= MK_MESSAGE; + } + + if (ccb->ccb_h.func_code == XPT_RESET_DEV) { + hscb->cdb_len = 0; + scb->flags |= SCB_DEVICE_RESET; + hscb->control |= MK_MESSAGE; + ahc_execute_scb(scb, NULL, 0, 0); + } else { + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + struct target_data *tdata; + + tdata = &hscb->shared_data.tdata; + if (ahc->pending_device == lstate) { + scb->flags |= SCB_TARGET_IMMEDIATE; + ahc->pending_device = NULL; + } + hscb->control |= TARGET_SCB; + tdata->target_phases = IDENTIFY_SEEN; + if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { + tdata->target_phases |= SPHASE_PENDING; + tdata->scsi_status = + ccb->csio.scsi_status; + } + tdata->initiator_tag = ccb->csio.tag_id; + } + if (ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) + hscb->control |= ccb->csio.tag_action; + + ahc_setup_data(ahc, sim, &ccb->csio, scb); + } + break; + } + case XPT_NOTIFY_ACK: + case XPT_IMMED_NOTIFY: + { + struct tmode_tstate *tstate; + struct tmode_lstate *lstate; + cam_status status; + + status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, + &lstate, TRUE); + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; + xpt_done(ccb); + break; + } + SLIST_INSERT_HEAD(&lstate->immed_notifies, &ccb->ccb_h, + sim_links.sle); + ccb->ccb_h.status = CAM_REQ_INPROG; + ahc_send_lstate_events(ahc, lstate); + break; + } + case XPT_EN_LUN: /* Enable LUN as a target */ + ahc_handle_en_lun(ahc, sim, ccb); + xpt_done(ccb); + break; + case XPT_ABORT: /* Abort the specified CCB */ + { + ahc_abort_ccb(ahc, sim, ccb); + break; + } + case XPT_SET_TRAN_SETTINGS: + { +#ifdef AHC_NEW_TRAN_SETTINGS + struct ahc_devinfo devinfo; + struct ccb_trans_settings *cts; + struct ccb_trans_settings_scsi *scsi; + struct ccb_trans_settings_spi *spi; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t *discenable; + uint16_t *tagenable; + u_int update_type; + + cts = &ccb->cts; + scsi = &cts->proto_specific.scsi; + spi = &cts->xport_specific.spi; + ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + SIM_CHANNEL(ahc, sim), + ROLE_UNKNOWN); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + update_type = 0; + if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { + update_type |= AHC_TRANS_GOAL; + discenable = &tstate->discenable; + tagenable = &tstate->tagenable; + tinfo->current.protocol_version = + cts->protocol_version; + tinfo->current.transport_version = + cts->transport_version; + tinfo->goal.protocol_version = + cts->protocol_version; + tinfo->goal.transport_version = + cts->transport_version; + } else if (cts->type == CTS_TYPE_USER_SETTINGS) { + update_type |= AHC_TRANS_USER; + discenable = &ahc->user_discenable; + tagenable = &ahc->user_tagenable; + tinfo->user.protocol_version = + cts->protocol_version; + tinfo->user.transport_version = + cts->transport_version; + } else { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + + ahc_lock(ahc, &s); + + if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { + if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) + *discenable |= devinfo.target_mask; + else + *discenable &= ~devinfo.target_mask; + } + + if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { + if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) + *tagenable |= devinfo.target_mask; + else + *tagenable &= ~devinfo.target_mask; + } + + if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) { + ahc_validate_width(ahc, &spi->bus_width); + ahc_set_width(ahc, &devinfo, spi->bus_width, + update_type, /*paused*/FALSE); + } + + if ((spi->valid & CTS_SPI_VALID_PPR_OPTIONS) == 0) { + if (update_type == AHC_TRANS_USER) + spi->ppr_options = tinfo->user.ppr_options; + else + spi->ppr_options = tinfo->goal.ppr_options; + } + + if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) == 0) { + if (update_type == AHC_TRANS_USER) + spi->sync_offset = tinfo->user.offset; + else + spi->sync_offset = tinfo->goal.offset; + } + + if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) == 0) { + if (update_type == AHC_TRANS_USER) + spi->sync_period = tinfo->user.period; + else + spi->sync_period = tinfo->goal.period; + } + + if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) + || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) { + struct ahc_syncrate *syncrate; + u_int maxsync; + + if ((ahc->features & AHC_ULTRA2) != 0) + maxsync = AHC_SYNCRATE_DT; + else if ((ahc->features & AHC_ULTRA) != 0) + maxsync = AHC_SYNCRATE_ULTRA; + else + maxsync = AHC_SYNCRATE_FAST; + + syncrate = ahc_find_syncrate(ahc, &spi->sync_period, + &spi->ppr_options, + maxsync); + ahc_validate_offset(ahc, syncrate, &spi->sync_offset, + spi->bus_width); + + /* We use a period of 0 to represent async */ + if (spi->sync_offset == 0) { + spi->sync_period = 0; + spi->ppr_options = 0; + } + + ahc_set_syncrate(ahc, &devinfo, syncrate, + spi->sync_period, spi->sync_offset, + spi->ppr_options, update_type, + /*paused*/FALSE); + } + ahc_unlock(ahc, &s); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); +#else + struct ahc_devinfo devinfo; + struct ccb_trans_settings *cts; + struct ahc_initiator_tinfo *tinfo; + struct tmode_tstate *tstate; + uint16_t *discenable; + uint16_t *tagenable; + u_int update_type; + long s; + + cts = &ccb->cts; + ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + SIM_CHANNEL(ahc, sim), + ROLE_UNKNOWN); + tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + update_type = 0; + if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { + update_type |= AHC_TRANS_GOAL; + discenable = &tstate->discenable; + tagenable = &tstate->tagenable; + } else if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { + update_type |= AHC_TRANS_USER; + discenable = &ahc->user_discenable; + tagenable = &ahc->user_tagenable; + } else { + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } + + ahc_lock(ahc, &s); + + if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { + if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) + *discenable |= devinfo.target_mask; + else + *discenable &= ~devinfo.target_mask; + } + + if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { + if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) + *tagenable |= devinfo.target_mask; + else + *tagenable &= ~devinfo.target_mask; + } + + if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { + ahc_validate_width(ahc, &cts->bus_width); + ahc_set_width(ahc, &devinfo, cts->bus_width, + update_type, /*paused*/FALSE); + } + + if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0) { + if (update_type == AHC_TRANS_USER) + cts->sync_offset = tinfo->user.offset; + else + cts->sync_offset = tinfo->goal.offset; + } + + if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0) { + if (update_type == AHC_TRANS_USER) + cts->sync_period = tinfo->user.period; + else + cts->sync_period = tinfo->goal.period; + } + + if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) + || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { + struct ahc_syncrate *syncrate; + u_int ppr_options; + u_int maxsync; + + if ((ahc->features & AHC_ULTRA2) != 0) + maxsync = AHC_SYNCRATE_DT; + else if ((ahc->features & AHC_ULTRA) != 0) + maxsync = AHC_SYNCRATE_ULTRA; + else + maxsync = AHC_SYNCRATE_FAST; + + ppr_options = 0; + if (cts->sync_period <= 9) + ppr_options = MSG_EXT_PPR_DT_REQ; + + syncrate = ahc_find_syncrate(ahc, &cts->sync_period, + &ppr_options, + maxsync); + ahc_validate_offset(ahc, syncrate, &cts->sync_offset, + MSG_EXT_WDTR_BUS_8_BIT); + + /* We use a period of 0 to represent async */ + if (cts->sync_offset == 0) { + cts->sync_period = 0; + ppr_options = 0; + } + + if (ppr_options == MSG_EXT_PPR_DT_REQ + && tinfo->user.transport_version >= 3) { + tinfo->goal.transport_version = + tinfo->user.transport_version; + tinfo->current.transport_version = + tinfo->user.transport_version; + } + + ahc_set_syncrate(ahc, &devinfo, syncrate, + cts->sync_period, cts->sync_offset, + ppr_options, update_type, + /*paused*/FALSE); + } + ahc_unlock(ahc, &s); + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); +#endif + break; + } + case XPT_GET_TRAN_SETTINGS: + /* Get default/user set transfer settings for the target */ + { + + ahc_lock(ahc, &s); + ahc_get_tran_settings(ahc, SIM_SCSI_ID(ahc, sim), + SIM_CHANNEL(ahc, sim), &ccb->cts); + ahc_unlock(ahc, &s); + xpt_done(ccb); + break; + } + case XPT_CALC_GEOMETRY: + { + struct ccb_calc_geometry *ccg; + uint32_t size_mb; + uint32_t secs_per_cylinder; + int extended; + + ccg = &ccb->ccg; + size_mb = ccg->volume_size + / ((1024L * 1024L) / ccg->block_size); + extended = SIM_IS_SCSIBUS_B(ahc, sim) + ? ahc->flags & AHC_EXTENDED_TRANS_B + : ahc->flags & AHC_EXTENDED_TRANS_A; + + if (size_mb > 1024 && extended) { + ccg->heads = 255; + ccg->secs_per_track = 63; + } else { + ccg->heads = 64; + ccg->secs_per_track = 32; + } + secs_per_cylinder = ccg->heads * ccg->secs_per_track; + ccg->cylinders = ccg->volume_size / secs_per_cylinder; + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + case XPT_RESET_BUS: /* Reset the specified SCSI bus */ + { + int found; + + ahc_lock(ahc, &s); + found = ahc_reset_channel(ahc, SIM_CHANNEL(ahc, sim), + /*initiate reset*/TRUE); + ahc_unlock(ahc, &s); + if (bootverbose) { + xpt_print_path(SIM_PATH(ahc, sim)); + printf("SCSI bus reset delivered. " + "%d SCBs aborted.\n", found); + } + ccb->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + case XPT_TERM_IO: /* Terminate the I/O process */ + /* XXX Implement */ + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + case XPT_PATH_INQ: /* Path routing inquiry */ + { + struct ccb_pathinq *cpi = &ccb->cpi; + + cpi->version_num = 1; /* XXX??? */ + cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; + if ((ahc->features & AHC_WIDE) != 0) + cpi->hba_inquiry |= PI_WIDE_16; + if ((ahc->flags & AHC_TARGETMODE) != 0) { + cpi->target_sprt = PIT_PROCESSOR + | PIT_DISCONNECT + | PIT_TERM_IO; + } else { + cpi->target_sprt = 0; + } + cpi->hba_misc = (ahc->flags & AHC_INITIATORMODE) + ? 0 : PIM_NOINITIATOR; + cpi->hba_eng_cnt = 0; + cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; + cpi->max_lun = 64; + if (SIM_IS_SCSIBUS_B(ahc, sim)) { + cpi->initiator_id = ahc->our_id_b; + if ((ahc->flags & AHC_RESET_BUS_B) == 0) + cpi->hba_misc |= PIM_NOBUSRESET; + } else { + cpi->initiator_id = ahc->our_id; + if ((ahc->flags & AHC_RESET_BUS_A) == 0) + cpi->hba_misc |= PIM_NOBUSRESET; + } + cpi->bus_id = cam_sim_bus(sim); + cpi->base_transfer_speed = 3300; + strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); + strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN); + strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); + cpi->unit_number = cam_sim_unit(sim); +#ifdef AHC_NEW_TRAN_SETTINGS + cpi->protocol = PROTO_SCSI; + cpi->protocol_version = SCSI_REV_2; + cpi->transport = XPORT_SPI; + cpi->transport_version = 2; + cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; + if ((ahc->features & AHC_DT) != 0) { + cpi->transport_version = 3; + cpi->xport_specific.spi.ppr_options = + SID_SPI_CLOCK_DT_ST; + } +#endif + cpi->ccb_h.status = CAM_REQ_CMP; + xpt_done(ccb); + break; + } + default: + ccb->ccb_h.status = CAM_REQ_INVALID; + xpt_done(ccb); + break; + } +} + +static void +ahc_get_tran_settings(struct ahc_softc *ahc, int our_id, char channel, + struct ccb_trans_settings *cts) +{ +#ifdef AHC_NEW_TRAN_SETTINGS + struct ahc_devinfo devinfo; + struct ccb_trans_settings_scsi *scsi; + struct ccb_trans_settings_spi *spi; + struct ahc_initiator_tinfo *targ_info; + struct tmode_tstate *tstate; + struct ahc_transinfo *tinfo; + + scsi = &cts->proto_specific.scsi; + spi = &cts->xport_specific.spi; + ahc_compile_devinfo(&devinfo, our_id, + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + channel, ROLE_UNKNOWN); + targ_info = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + + if (cts->type == CTS_TYPE_CURRENT_SETTINGS) + tinfo = &targ_info->current; + else + tinfo = &targ_info->user; + + scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; + spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; + if (cts->type == CTS_TYPE_USER_SETTINGS) { + if ((ahc->user_discenable & devinfo.target_mask) != 0) + spi->flags |= CTS_SPI_FLAGS_DISC_ENB; + + if ((ahc->user_tagenable & devinfo.target_mask) != 0) + scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; + } else { + if ((tstate->discenable & devinfo.target_mask) != 0) + spi->flags |= CTS_SPI_FLAGS_DISC_ENB; + + if ((tstate->tagenable & devinfo.target_mask) != 0) + scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; + } + cts->protocol_version = tinfo->protocol_version; + cts->transport_version = tinfo->transport_version; + + spi->sync_period = tinfo->period; + spi->sync_offset = tinfo->offset; + spi->bus_width = tinfo->width; + spi->ppr_options = tinfo->ppr_options; + + cts->protocol = PROTO_SCSI; + cts->transport = XPORT_SPI; + scsi->valid = CTS_SCSI_VALID_TQ; + spi->valid = CTS_SPI_VALID_SYNC_RATE + | CTS_SPI_VALID_SYNC_OFFSET + | CTS_SPI_VALID_BUS_WIDTH + | CTS_SPI_VALID_DISC + | CTS_SPI_VALID_PPR_OPTIONS; + + cts->ccb_h.status = CAM_REQ_CMP; +#else + struct ahc_devinfo devinfo; + struct ahc_initiator_tinfo *targ_info; + struct tmode_tstate *tstate; + struct ahc_transinfo *tinfo; + long s; + + ahc_compile_devinfo(&devinfo, our_id, + cts->ccb_h.target_id, + cts->ccb_h.target_lun, + channel, ROLE_UNKNOWN); + targ_info = ahc_fetch_transinfo(ahc, devinfo.channel, + devinfo.our_scsiid, + devinfo.target, &tstate); + + if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) + tinfo = &targ_info->current; + else + tinfo = &targ_info->user; + + ahc_lock(ahc, &s); + + cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); + if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { + if ((ahc->user_discenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_DISC_ENB; + + if ((ahc->user_tagenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_TAG_ENB; + } else { + if ((tstate->discenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_DISC_ENB; + + if ((tstate->tagenable & devinfo.target_mask) != 0) + cts->flags |= CCB_TRANS_TAG_ENB; + } + cts->sync_period = tinfo->period; + cts->sync_offset = tinfo->offset; + cts->bus_width = tinfo->width; + + ahc_unlock(ahc, &s); + + cts->valid = CCB_TRANS_SYNC_RATE_VALID + | CCB_TRANS_SYNC_OFFSET_VALID + | CCB_TRANS_BUS_WIDTH_VALID + | CCB_TRANS_DISC_VALID + | CCB_TRANS_TQ_VALID; + + cts->ccb_h.status = CAM_REQ_CMP; +#endif +} + +static void +ahc_async(void *callback_arg, uint32_t code, struct cam_path *path, void *arg) +{ + struct ahc_softc *ahc; + struct cam_sim *sim; + + sim = (struct cam_sim *)callback_arg; + ahc = (struct ahc_softc *)cam_sim_softc(sim); + switch (code) { + case AC_LOST_DEVICE: + { + struct ahc_devinfo devinfo; + long s; + + ahc_compile_devinfo(&devinfo, SIM_SCSI_ID(ahc, sim), + xpt_path_target_id(path), + xpt_path_lun_id(path), + SIM_CHANNEL(ahc, sim), + ROLE_UNKNOWN); + + /* + * Revert to async/narrow transfers + * for the next device. + */ + ahc_lock(ahc, &s); + ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, + AHC_TRANS_GOAL|AHC_TRANS_CUR, /*paused*/FALSE); + ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, + /*period*/0, /*offset*/0, /*ppr_options*/0, + AHC_TRANS_GOAL|AHC_TRANS_CUR, + /*paused*/FALSE); + ahc_unlock(ahc, &s); + break; + } + default: + break; + } +} + +static void +ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments, + int error) +{ + struct scb *scb; + union ccb *ccb; + struct ahc_softc *ahc; + long s; + + scb = (struct scb *)arg; + ccb = scb->io_ctx; + ahc = (struct ahc_softc *)ccb->ccb_h.ccb_ahc_ptr; + + if (error != 0) { + if (error == EFBIG) + ahc_set_transaction_status(scb, CAM_REQ_TOO_BIG); + else + ahc_set_transaction_status(scb, CAM_REQ_CMP_ERR); + if (nsegments != 0) + bus_dmamap_unload(ahc->buffer_dmat, scb->dmamap); + ahc_free_scb(ahc, scb); + xpt_done(ccb); + return; + } + if (nsegments != 0) { + struct ahc_dma_seg *sg; + bus_dma_segment_t *end_seg; + bus_dmasync_op_t op; + + end_seg = dm_segs + nsegments; + + /* Copy the segments into our SG list */ + sg = scb->sg_list; + while (dm_segs < end_seg) { + sg->addr = dm_segs->ds_addr; +/* XXX Add in the 5th byte of the address later. */ + sg->len = dm_segs->ds_len; + sg++; + dm_segs++; + } + + /* + * Note where to find the SG entries in bus space. + * We also set the full residual flag which the + * sequencer will clear as soon as a data transfer + * occurs. + */ + scb->hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; + + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) + op = BUS_DMASYNC_PREREAD; + else + op = BUS_DMASYNC_PREWRITE; + + bus_dmamap_sync(ahc->buffer_dmat, scb->dmamap, op); + + if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { + struct target_data *tdata; + + tdata = &scb->hscb->shared_data.tdata; + tdata->target_phases |= DPHASE_PENDING; + if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) + tdata->data_phase = P_DATAOUT; + else + tdata->data_phase = P_DATAIN; + + /* + * If the transfer is of an odd length and in the + * "in" direction (scsi->HostBus), then it may + * trigger a bug in the 'WideODD' feature of + * non-Ultra2 chips. Force the total data-length + * to be even by adding an extra, 1 byte, SG, + * element. We do this even if we are not currently + * negotiated wide as negotiation could occur before + * this command is executed. + */ + if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0 + && (ccb->csio.dxfer_len & 0x1) != 0 + && (ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { + + nsegments++; + if (nsegments > AHC_NSEG) { + + ahc_set_transaction_status(scb, + CAM_REQ_TOO_BIG); + bus_dmamap_unload(ahc->buffer_dmat, + scb->dmamap); + ahc_free_scb(ahc, scb); + xpt_done(ccb); + return; + } + sg->addr = ahc->dma_bug_buf; + sg->len = 1; + sg++; + } + } + sg--; + sg->len |= AHC_DMA_LAST_SEG; + + /* Copy the first SG into the "current" data pointer area */ + scb->hscb->dataptr = scb->sg_list->addr; + scb->hscb->datacnt = scb->sg_list->len; + } else { + scb->hscb->sgptr = SG_LIST_NULL; + scb->hscb->dataptr = 0; + scb->hscb->datacnt = 0; + } + + scb->sg_count = nsegments; + + ahc_lock(ahc, &s); + + /* + * Last time we need to check if this SCB needs to + * be aborted. + */ + if (ahc_get_transaction_status(scb) != CAM_REQ_INPROG) { + if (nsegments != 0) + bus_dmamap_unload(ahc->buffer_dmat, + scb->dmamap); + ahc_free_scb(ahc, scb); + xpt_done(ccb); + ahc_unlock(ahc, &s); + return; + } + + LIST_INSERT_HEAD(&ahc->pending_scbs, scb, pending_links); + + ccb->ccb_h.status |= CAM_SIM_QUEUED; + + if (ccb->ccb_h.timeout != CAM_TIME_INFINITY) { + if (ccb->ccb_h.timeout == CAM_TIME_DEFAULT) + ccb->ccb_h.timeout = 5 * 1000; + ccb->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)scb, + (ccb->ccb_h.timeout * hz) / 1000); + } + + /* + * We only allow one untagged transaction + * per target in the initiator role unless + * we are storing a full busy target *lun* + * table in SCB space. + */ + if ((scb->hscb->control & (TARGET_SCB|TAG_ENB)) == 0 + && (ahc->features & AHC_SCB_BTT) == 0) { + struct scb_tailq *untagged_q; + + untagged_q = &(ahc->untagged_queues[ccb->ccb_h.target_id]); + TAILQ_INSERT_TAIL(untagged_q, scb, links.tqe); + if (TAILQ_FIRST(untagged_q) != scb) { + ahc_unlock(ahc, &s); + return; + } + } + scb->flags |= SCB_ACTIVE; + + if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { + pause_sequencer(ahc); + if ((ahc->flags & AHC_PAGESCBS) == 0) + ahc_outb(ahc, SCBPTR, scb->hscb->tag); + ahc_outb(ahc, SCB_TAG, scb->hscb->tag); + ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); + unpause_sequencer(ahc); + } else { + ahc_queue_scb(ahc, scb); + } + + ahc_unlock(ahc, &s); +} + +static void +ahc_poll(struct cam_sim *sim) +{ + ahc_intr(cam_sim_softc(sim)); +} + +static void +ahc_setup_data(struct ahc_softc *ahc, struct cam_sim *sim, + struct ccb_scsiio *csio, struct scb *scb) +{ + struct hardware_scb *hscb; + struct ccb_hdr *ccb_h; + + hscb = scb->hscb; + ccb_h = &csio->ccb_h; + + if (ccb_h->func_code == XPT_SCSI_IO) { + hscb->cdb_len = csio->cdb_len; + if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { + + if (hscb->cdb_len > sizeof(hscb->cdb32) + || (ccb_h->flags & CAM_CDB_PHYS) != 0) { + ahc_set_transaction_status(scb, + CAM_REQ_INVALID); + xpt_done(scb->io_ctx); + ahc_free_scb(ahc, scb); + return; + } + if (hscb->cdb_len > 12) { + memcpy(hscb->cdb32, + csio->cdb_io.cdb_ptr, + hscb->cdb_len); + hscb->shared_data.cdb_ptr = scb->cdb32_busaddr; + } else { + memcpy(hscb->shared_data.cdb, + csio->cdb_io.cdb_ptr, + hscb->cdb_len); + } + } else { + if (hscb->cdb_len > 12) { + memcpy(hscb->cdb32, csio->cdb_io.cdb_bytes, + hscb->cdb_len); + hscb->shared_data.cdb_ptr = scb->cdb32_busaddr; + } else { + memcpy(hscb->shared_data.cdb, + csio->cdb_io.cdb_bytes, + hscb->cdb_len); + } + } + } + + /* Only use S/G if there is a transfer */ + if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { + if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { + /* We've been given a pointer to a single buffer */ + if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { + int s; + int error; + + s = splsoftvm(); + error = bus_dmamap_load(ahc->buffer_dmat, + scb->dmamap, + csio->data_ptr, + csio->dxfer_len, + ahc_execute_scb, + scb, /*flags*/0); + if (error == EINPROGRESS) { + /* + * So as to maintain ordering, + * freeze the controller queue + * until our mapping is + * returned. + */ + xpt_freeze_simq(sim, + /*count*/1); + scb->io_ctx->ccb_h.status |= + CAM_RELEASE_SIMQ; + } + splx(s); + } else { + struct bus_dma_segment seg; + + /* Pointer to physical buffer */ + if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE) + panic("ahc_setup_data - Transfer size " + "larger than can device max"); + + seg.ds_addr = (bus_addr_t)csio->data_ptr; + seg.ds_len = csio->dxfer_len; + ahc_execute_scb(scb, &seg, 1, 0); + } + } else { + struct bus_dma_segment *segs; + + if ((ccb_h->flags & CAM_DATA_PHYS) != 0) + panic("ahc_setup_data - Physical segment " + "pointers unsupported"); + + if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) + panic("ahc_setup_data - Virtual segment " + "addresses unsupported"); + + /* Just use the segments provided */ + segs = (struct bus_dma_segment *)csio->data_ptr; + ahc_execute_scb(scb, segs, csio->sglist_cnt, 0); + } + } else { + ahc_execute_scb(scb, NULL, 0, 0); + } +} + +static void +ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) { + + if ((scb->flags & SCB_RECOVERY_SCB) == 0) { + struct scb *list_scb; + + scb->flags |= SCB_RECOVERY_SCB; + + /* + * Take all queued, but not sent SCBs out of the equation. + * Also ensure that no new CCBs are queued to us while we + * try to fix this problem. + */ + if ((scb->io_ctx->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { + xpt_freeze_simq(SCB_GET_SIM(ahc, scb), /*count*/1); + scb->io_ctx->ccb_h.status |= CAM_RELEASE_SIMQ; + } + + /* + * Go through all of our pending SCBs and remove + * any scheduled timeouts for them. We will reschedule + * them after we've successfully fixed this problem. + */ + LIST_FOREACH(list_scb, &ahc->pending_scbs, pending_links) { + union ccb *ccb; + + ccb = list_scb->io_ctx; + untimeout(ahc_timeout, list_scb, ccb->ccb_h.timeout_ch); + } + } +} + +void +ahc_timeout(void *arg) +{ + struct scb *scb; + struct ahc_softc *ahc; + long s; + int found; + u_int last_phase; + int target; + int lun; + int i; + char channel; + + scb = (struct scb *)arg; + ahc = (struct ahc_softc *)scb->io_ctx->ccb_h.ccb_ahc_ptr; + + ahc_lock(ahc, &s); + + /* + * Ensure that the card doesn't do anything + * behind our back. Also make sure that we + * didn't "just" miss an interrupt that would + * affect this timeout. + */ + do { + ahc_intr(ahc); + pause_sequencer(ahc); + } while (ahc_inb(ahc, INTSTAT) & INT_PEND); + + ahc_print_path(ahc, scb); + if ((scb->flags & SCB_ACTIVE) == 0) { + /* Previous timeout took care of me already */ + printf("Timedout SCB %d handled by another timeout\n", + scb->hscb->tag); + unpause_sequencer(ahc); + ahc_unlock(ahc, &s); + return; + } + + target = SCB_GET_TARGET(ahc, scb); + channel = SCB_GET_CHANNEL(ahc, scb); + lun = SCB_GET_LUN(scb); + + printf("SCB 0x%x - timed out ", scb->hscb->tag); + /* + * Take a snapshot of the bus state and print out + * some information so we can track down driver bugs. + */ + last_phase = ahc_inb(ahc, LASTPHASE); + + for (i = 0; i < num_phases; i++) { + if (last_phase == phase_table[i].phase) + break; + } + printf("%s", phase_table[i].phasemsg); + + printf(", SEQADDR == 0x%x\n", + ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); + + if (scb->sg_count > 0) { + for (i = 0; i < scb->sg_count; i++) { + printf("sg[%d] - Addr 0x%x : Length %d\n", + i, + scb->sg_list[i].addr, + scb->sg_list[i].len); + } + } + if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { + /* + * Been down this road before. + * Do a full bus reset. + */ +bus_reset: + ahc_set_transaction_status(scb, CAM_CMD_TIMEOUT); + found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); + printf("%s: Issued Channel %c Bus Reset. " + "%d SCBs aborted\n", ahc_name(ahc), channel, found); + } else { + /* + * If we are a target, transition to bus free and report + * the timeout. + * + * The target/initiator that is holding up the bus may not + * be the same as the one that triggered this timeout + * (different commands have different timeout lengths). + * If the bus is idle and we are actiing as the initiator + * for this request, queue a BDR message to the timed out + * target. Otherwise, if the timed out transaction is + * active: + * Initiator transaction: + * Stuff the message buffer with a BDR message and assert + * ATN in the hopes that the target will let go of the bus + * and go to the mesgout phase. If this fails, we'll + * get another timeout 2 seconds later which will attempt + * a bus reset. + * + * Target transaction: + * Transition to BUS FREE and report the error. + * It's good to be the target! + */ + u_int active_scb_index; + + active_scb_index = ahc_inb(ahc, SCB_TAG); + + if (last_phase != P_BUSFREE + && (active_scb_index < ahc->scb_data->numscbs)) { + struct scb *active_scb; + + /* + * If the active SCB is not from our device, + * assume that another device is hogging the bus + * and wait for it's timeout to expire before + * taking additional action. + */ + active_scb = &ahc->scb_data->scbarray[active_scb_index]; + if (active_scb->hscb->scsiid != scb->hscb->scsiid + || active_scb->hscb->lun != scb->hscb->lun) { + struct ccb_hdr *ccbh; + u_int newtimeout; + + ahc_print_path(ahc, scb); + printf("Other SCB Timeout%s", + (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 + ? " again\n" : "\n"); + scb->flags |= SCB_OTHERTCL_TIMEOUT; + newtimeout = + MAX(active_scb->io_ctx->ccb_h.timeout, + scb->io_ctx->ccb_h.timeout); + ccbh = &scb->io_ctx->ccb_h; + scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, scb, + (newtimeout * hz) / 1000); + ahc_unlock(ahc, &s); + return; + } + + /* It's us */ + if ((scb->hscb->control & TARGET_SCB) != 0) { + + /* + * Send back any queued up transactions + * and properly record the error condition. + */ + ahc_freeze_devq(ahc, scb); + ahc_set_transaction_status(scb, + CAM_CMD_TIMEOUT); + ahc_freeze_scb(scb); + ahc_done(ahc, scb); + + /* Will clear us from the bus */ + restart_sequencer(ahc); + return; + } + + ahc_set_recoveryscb(ahc, active_scb); + ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); + ahc_outb(ahc, SCSISIGO, last_phase|ATNO); + ahc_print_path(ahc, active_scb); + printf("BDR message in message buffer\n"); + active_scb->flags |= SCB_DEVICE_RESET; + active_scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); + unpause_sequencer(ahc); + } else { + int disconnected; + + /* XXX Shouldn't panic. Just punt instead */ + if ((scb->hscb->control & TARGET_SCB) != 0) + panic("Timed-out target SCB but bus idle"); + + if (last_phase != P_BUSFREE + && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { + /* XXX What happened to the SCB? */ + /* Hung target selection. Goto busfree */ + printf("%s: Hung target selection\n", + ahc_name(ahc)); + restart_sequencer(ahc); + return; + } + + if (ahc_search_qinfifo(ahc, target, channel, lun, + scb->hscb->tag, ROLE_INITIATOR, + /*status*/0, SEARCH_COUNT) > 0) { + disconnected = FALSE; + } else { + disconnected = TRUE; + } + + if (disconnected) { + u_int active_scb; + + ahc_set_recoveryscb(ahc, scb); + /* + * Simply set the MK_MESSAGE control bit. + */ + scb->hscb->control |= MK_MESSAGE; + scb->flags |= SCB_QUEUED_MSG + | SCB_DEVICE_RESET; + + /* + * Mark the cached copy of this SCB in the + * disconnected list too, so that a reconnect + * at this point causes a BDR or abort. + */ + active_scb = ahc_inb(ahc, SCBPTR); + if (ahc_search_disc_list(ahc, target, + channel, lun, + scb->hscb->tag, + /*stop_on_first*/TRUE, + /*remove*/FALSE, + /*save_state*/FALSE)) { + u_int scb_control; + + scb_control = ahc_inb(ahc, SCB_CONTROL); + scb_control |= MK_MESSAGE; + ahc_outb(ahc, SCB_CONTROL, scb_control); + } + ahc_outb(ahc, SCBPTR, active_scb); + + /* + * Actually re-queue this SCB in case we can + * select the device before it reconnects. + * Clear out any entries in the QINFIFO first + * so we are the next SCB for this target + * to run. + */ + ahc_search_qinfifo(ahc, + SCB_GET_TARGET(ahc, scb), + channel, SCB_GET_LUN(scb), + SCB_LIST_NULL, + ROLE_INITIATOR, + CAM_REQUEUE_REQ, + SEARCH_COMPLETE); + ahc_print_path(ahc, scb); + printf("Queuing a BDR SCB\n"); + ahc->qinfifo[ahc->qinfifonext++] = + scb->hscb->tag; + if ((ahc->features & AHC_QUEUE_REGS) != 0) { + ahc_outb(ahc, HNSCB_QOFF, + ahc->qinfifonext); + } else { + ahc_outb(ahc, KERNEL_QINPOS, + ahc->qinfifonext); + } + scb->io_ctx->ccb_h.timeout_ch = + timeout(ahc_timeout, (caddr_t)scb, 2 * hz); + unpause_sequencer(ahc); + } else { + /* Go "immediatly" to the bus reset */ + /* This shouldn't happen */ + ahc_set_recoveryscb(ahc, scb); + ahc_print_path(ahc, scb); + printf("SCB %d: Immediate reset. " + "Flags = 0x%x\n", scb->hscb->tag, + scb->flags); + goto bus_reset; + } + } + } + ahc_unlock(ahc, &s); +} + +static void +ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) +{ + union ccb *abort_ccb; + + abort_ccb = ccb->cab.abort_ccb; + switch (abort_ccb->ccb_h.func_code) { + case XPT_ACCEPT_TARGET_IO: + case XPT_IMMED_NOTIFY: + case XPT_CONT_TARGET_IO: + { + struct tmode_tstate *tstate; + struct tmode_lstate *lstate; + struct ccb_hdr_slist *list; + cam_status status; + + status = ahc_find_tmode_devs(ahc, sim, abort_ccb, &tstate, + &lstate, TRUE); + + if (status != CAM_REQ_CMP) { + ccb->ccb_h.status = status; + break; + } + + if (abort_ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) + list = &lstate->accept_tios; + else if (abort_ccb->ccb_h.func_code == XPT_IMMED_NOTIFY) + list = &lstate->immed_notifies; + else + list = NULL; + + if (list != NULL) { + struct ccb_hdr *curelm; + int found; + + curelm = SLIST_FIRST(list); + found = 0; + if (curelm == &abort_ccb->ccb_h) { + found = 1; + SLIST_REMOVE_HEAD(list, sim_links.sle); + } else { + while(curelm != NULL) { + struct ccb_hdr *nextelm; + + nextelm = + SLIST_NEXT(curelm, sim_links.sle); + + if (nextelm == &abort_ccb->ccb_h) { + found = 1; + SLIST_NEXT(curelm, + sim_links.sle) = + SLIST_NEXT(nextelm, + sim_links.sle); + break; + } + curelm = nextelm; + } + } + + if (found) { + abort_ccb->ccb_h.status = CAM_REQ_ABORTED; + xpt_done(abort_ccb); + ccb->ccb_h.status = CAM_REQ_CMP; + } else { + printf("Not found\n"); + ccb->ccb_h.status = CAM_PATH_INVALID; + } + break; + } + /* FALLTHROUGH */ + } + case XPT_SCSI_IO: + /* XXX Fully implement the hard ones */ + ccb->ccb_h.status = CAM_UA_ABORT; + break; + default: + ccb->ccb_h.status = CAM_REQ_INVALID; + break; + } + xpt_done(ccb); +} + +void +ahc_send_async(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, ac_code code) +{ + struct ahc_devinfo mod_devinfo; + struct ccb_trans_settings cts; + struct cam_path *path; + void *arg; + int error; + + mod_devinfo = *devinfo; + mod_devinfo.lun = CAM_LUN_WILDCARD; + arg = NULL; + error = ahc_create_path(ahc, &mod_devinfo, &path); + + if (error != CAM_REQ_CMP) + return; + + switch (code) { + case AC_TRANSFER_NEG: +#ifdef AHC_NEW_TRAN_SETTINGS + cts.type = CTS_TYPE_CURRENT_SETTINGS; +#else + cts.flags = CCB_TRANS_CURRENT_SETTINGS; +#endif + cts.ccb_h.path = path; + cts.ccb_h.target_id = devinfo->target; + cts.ccb_h.target_lun = devinfo->lun; + ahc_get_tran_settings(ahc, devinfo->our_scsiid, + devinfo->channel, &cts); + arg = &cts; + break; + case AC_SENT_BDR: + case AC_BUS_RESET: + break; + default: + panic("ahc_send_async: Unexpected async event"); + } + xpt_async(code, path, arg); +} + +void +ahc_platform_set_tags(struct ahc_softc *ahc, + struct ahc_devinfo *devinfo, int enable) +{ +} + +int +ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg) +{ + ahc->platform_data = + malloc(sizeof(struct ahc_platform_data), M_DEVBUF, M_NOWAIT); + if (ahc->platform_data == NULL) + return (ENOMEM); + memset(ahc->platform_data, 0, sizeof(struct ahc_platform_data)); + return (0); +} + +void +ahc_platform_free(struct ahc_softc *ahc) +{ + if (ahc->platform_data != NULL) { + if (ahc->platform_data->regs != NULL) + bus_release_resource(ahc->dev_softc, + ahc->platform_data->regs_res_type, + ahc->platform_data->regs_res_id, + ahc->platform_data->regs); + + if (ahc->platform_data->irq != NULL) + bus_release_resource(ahc->dev_softc, + ahc->platform_data->irq_res_type, + 0, ahc->platform_data->irq); + + free(ahc->platform_data, M_DEVBUF); + } +} + +int +ahc_softc_comp(struct ahc_softc *lahc, struct ahc_softc *rahc) +{ + /* We don't sort softcs under FreeBSD so report equal always */ + return (0); +} + +#if UNUSED +static void +ahc_dump_targcmd(struct target_cmd *cmd) +{ + uint8_t *byte; + uint8_t *last_byte; + int i; + + byte = &cmd->initiator_channel; + /* Debugging info for received commands */ + last_byte = &cmd[1].initiator_channel; + + i = 0; + while (byte < last_byte) { + if (i == 0) + printf("\t"); + printf("%#x", *byte++); + i++; + if (i == 8) { + printf("\n"); + i = 0; + } else { + printf(", "); + } + } +} +#endif diff --git a/sys/dev/aic7xxx/aic7xxx_osm.h b/sys/dev/aic7xxx/aic7xxx_osm.h new file mode 100644 index 000000000000..eefc09ed6f0e --- /dev/null +++ b/sys/dev/aic7xxx/aic7xxx_osm.h @@ -0,0 +1,451 @@ +/* + * FreeBSD platform specific driver option settings, data structures, + * function declarations and includes. + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#ifndef _AIC7XXX_FREEBSD_H_ +#define _AIC7XXX_FREEBSD_H_ + +#include <opt_aic7xxx.h> /* for config options */ +#include <pci.h> /* for NPCI */ + +#include <stddef.h> /* For offsetof */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> /* For device_t */ +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/queue.h> + +#if NPCI > 0 +#define AHC_SUPPORT_PCI 1 +#include <machine/bus_memio.h> +#endif +#include <machine/bus_pio.h> +#include <machine/bus.h> +#include <machine/clock.h> +#include <machine/resource.h> + +#include <sys/rman.h> + +#if NPCI > 0 +#include <pci/pcireg.h> +#include <pci/pcivar.h> +#endif + +#include <cam/cam.h> +#include <cam/cam_ccb.h> +#include <cam/cam_debug.h> +#include <cam/cam_sim.h> +#include <cam/cam_xpt_sim.h> + +#include <cam/scsi/scsi_all.h> +#include <cam/scsi/scsi_message.h> + +/****************************** Platform Macros *******************************/ +#define SIM_IS_SCSIBUS_B(ahc, sim) \ + ((sim) == ahc->platform_data->sim_b) +#define SIM_CHANNEL(ahc, sim) \ + (((sim) == ahc->platform_data->sim_b) ? 'B' : 'A') +#define SIM_SCSI_ID(ahc, sim) \ + (((sim) == ahc->platform_data->sim_b) ? ahc->our_id_b : ahc->our_id) +#define SIM_PATH(ahc, sim) \ + (((sim) == ahc->platform_data->sim_b) ? ahc->platform_data->path_b \ + : ahc->platform_data->path) +#define BUILD_SCSIID(ahc, sim, target_id, our_id) \ + ((((target_id) << TID_SHIFT) & TID) | (our_id) \ + | (SIM_IS_SCSIBUS_B(ahc, sim) ? TWIN_CHNLB : 0)) + +#define SCB_GET_SIM(ahc, scb) \ + (SCB_GET_CHANNEL(ahc, scb) == 'A' ? (ahc)->platform_data->sim \ + : (ahc)->platform_data->sim_b) + +/************************* Forward Declarations *******************************/ +typedef device_t ahc_dev_softc_t; +typedef union ccb *ahc_io_ctx_t; + +/***************************** Bus Space/DMA **********************************/ +#define ahc_dma_tag_create(ahc, parent_tag, alignment, boundary, \ + lowaddr, highaddr, filter, filterarg, \ + maxsize, nsegments, maxsegsz, flags, \ + dma_tagp) \ + bus_dma_tag_create(parent_tag, alignment, boundary, \ + lowaddr, highaddr, filter, filterarg, \ + maxsize, nsegments, maxsegsz, flags, \ + dma_tagp) + +#define ahc_dma_tag_destroy(ahc, tag) \ + bus_dma_tag_destroy(tag) + +#define ahc_dmamem_alloc(ahc, dmat, vaddr, flags, mapp) \ + bus_dmamem_alloc(dmat, vaddr, flags, mapp) + +#define ahc_dmamem_free(ahc, dmat, vaddr, map) \ + bus_dmamem_free(dmat, vaddr, map) + +#define ahc_dmamap_create(ahc, tag, flags, mapp) \ + bus_dmamap_create(tag, flags, mapp) + +#define ahc_dmamap_destroy(ahc, tag, map) \ + bus_dmamap_destroy(tag, map) + +#define ahc_dmamap_load(ahc, dmat, map, addr, buflen, callback, \ + callback_arg, flags) \ + bus_dmamap_load(dmat, map, addr, buflen, callback, callback_arg, flags) + +#define ahc_dmamap_unload(ahc, tag, map) \ + bus_dmamap_unload(tag, map) + +#define ahc_dmamap_sync(ahc, dma_tag, dmamap, op) \ + bus_dmamap_sync(dma_tag_dmamap, op) + +/************************ Tunable Driver Parameters **************************/ +/* + * The number of dma segments supported. The sequencer can handle any number + * of physically contiguous S/G entrys. To reduce the driver's memory + * consumption, we limit the number supported to be sufficient to handle + * the largest mapping supported by the kernel, MAXPHYS. Assuming the + * transfer is as fragmented as possible and unaligned, this turns out to + * be the number of paged sized transfers in MAXPHYS plus an extra element + * to handle any unaligned residual. The sequencer fetches SG elements + * in 128 byte chucks, so make the number per-transaction a nice multiple + * of 16 (8 byte S/G elements). + */ +/* XXX Worth the space??? */ +#define AHC_NSEG (roundup(btoc(MAXPHYS) + 1, 16)) + +/* This driver supports target mode */ +#define AHC_TARGET_MODE 1 + +/************************** Softc/SCB Platform Data ***************************/ +struct ahc_platform_data { + /* + * Hooks into the XPT. + */ + struct cam_sim *sim; + struct cam_sim *sim_b; + struct cam_path *path; + struct cam_path *path_b; + + int regs_res_type; + int regs_res_id; + int irq_res_type; + struct resource *regs; + struct resource *irq; + void *ih; +}; + +struct scb_platform_data { +}; + +/***************************** Core Includes **********************************/ +#include <dev/aic7xxx/aic7xxx.h> + +/*************************** Device Access ************************************/ +#define ahc_inb(ahc, port) \ + bus_space_read_1((ahc)->tag, (ahc)->bsh, port) + +#define ahc_outb(ahc, port, value) \ + bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) + +#define ahc_outsb(ahc, port, valp, count) \ + bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) + +#define ahc_insb(ahc, port, valp, count) \ + bus_space_read_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) + +static __inline void ahc_flush_device_writes(struct ahc_softc *); + +static __inline void +ahc_flush_device_writes(struct ahc_softc *ahc) +{ + /* XXX Is this sufficient for all architectures??? */ + ahc_inb(ahc, INTSTAT); +} + +/**************************** Locking Primitives ******************************/ +/* Lock protecting internal data structures */ +static __inline void ahc_lockinit(struct ahc_softc *); +static __inline void ahc_lock(struct ahc_softc *, unsigned long *flags); +static __inline void ahc_unlock(struct ahc_softc *, unsigned long *flags); + +/* Lock held during command compeletion to the upper layer */ +static __inline void ahc_done_lockinit(struct ahc_softc *); +static __inline void ahc_done_lock(struct ahc_softc *, unsigned long *flags); +static __inline void ahc_done_unlock(struct ahc_softc *, unsigned long *flags); + +static __inline void +ahc_lockinit(struct ahc_softc *ahc) +{ +} + +static __inline void +ahc_lock(struct ahc_softc *ahc, unsigned long *flags) +{ + *flags = splcam(); +} + +static __inline void +ahc_unlock(struct ahc_softc *ahc, unsigned long *flags) +{ + splx(*flags); +} + +/* Lock held during command compeletion to the upper layer */ +static __inline void +ahc_done_lockinit(struct ahc_softc *ahc) +{ +} + +static __inline void +ahc_done_lock(struct ahc_softc *ahc, unsigned long *flags) +{ +} + +static __inline void +ahc_done_unlock(struct ahc_softc *ahc, unsigned long *flags) +{ +} + +/****************************** OS Primitives *********************************/ +#define ahc_delay DELAY + +/************************** Transaction Operations ****************************/ +static __inline void ahc_set_transaction_status(struct scb *, uint32_t); +static __inline void ahc_set_scsi_status(struct scb *, uint32_t); +static __inline uint32_t ahc_get_transaction_status(struct scb *); +static __inline uint32_t ahc_get_scsi_status(struct scb *); +static __inline void ahc_set_transaction_tag(struct scb *, int, u_int); +static __inline u_long ahc_get_transfer_length(struct scb *); +static __inline int ahc_get_transfer_dir(struct scb *); +static __inline void ahc_set_residual(struct scb *, u_long); +static __inline void ahc_set_sense_residual(struct scb *, u_long); +static __inline u_long ahc_get_residual(struct scb *); +static __inline int ahc_perform_autosense(struct scb *); +static __inline uint32_t ahc_get_sense_bufsize(struct ahc_softc*, struct scb*); +static __inline void ahc_freeze_ccb(union ccb *ccb); +static __inline void ahc_freeze_scb(struct scb *scb); +static __inline void ahc_platform_freeze_devq(struct ahc_softc *, struct scb *); +static __inline int ahc_platform_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status); + +static __inline +void ahc_set_transaction_status(struct scb *scb, uint32_t status) +{ + scb->io_ctx->ccb_h.status &= ~CAM_STATUS_MASK; + scb->io_ctx->ccb_h.status |= status; +} + +static __inline +void ahc_set_scsi_status(struct scb *scb, uint32_t status) +{ + scb->io_ctx->csio.scsi_status = status; +} + +static __inline +uint32_t ahc_get_transaction_status(struct scb *scb) +{ + return (scb->io_ctx->ccb_h.status & CAM_STATUS_MASK); +} + +static __inline +uint32_t ahc_get_scsi_status(struct scb *scb) +{ + return (scb->io_ctx->csio.scsi_status); +} + +static __inline +void ahc_set_transaction_tag(struct scb *scb, int enabled, u_int type) +{ + scb->io_ctx->csio.tag_action = type; + if (enabled) + scb->io_ctx->ccb_h.flags |= CAM_TAG_ACTION_VALID; + else + scb->io_ctx->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; +} + +static __inline +u_long ahc_get_transfer_length(struct scb *scb) +{ + return (scb->io_ctx->csio.dxfer_len); +} + +static __inline +int ahc_get_transfer_dir(struct scb *scb) +{ + return (scb->io_ctx->ccb_h.flags & CAM_DIR_MASK); +} + +static __inline +void ahc_set_residual(struct scb *scb, u_long resid) +{ + scb->io_ctx->csio.resid = resid; +} + +static __inline +void ahc_set_sense_residual(struct scb *scb, u_long resid) +{ + scb->io_ctx->csio.sense_resid = resid; +} + +static __inline +u_long ahc_get_residual(struct scb *scb) +{ + return (scb->io_ctx->csio.resid); +} + +static __inline +int ahc_perform_autosense(struct scb *scb) +{ + return (!(scb->io_ctx->ccb_h.flags & CAM_DIS_AUTOSENSE)); +} + +static __inline uint32_t +ahc_get_sense_bufsize(struct ahc_softc *ahc, struct scb *scb) +{ + return (sizeof(struct scsi_sense_data)); +} + +static __inline void +ahc_freeze_ccb(union ccb *ccb) +{ + if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { + ccb->ccb_h.status |= CAM_DEV_QFRZN; + xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); + } +} + +static __inline void +ahc_freeze_scb(struct scb *scb) +{ + ahc_freeze_ccb(scb->io_ctx); +} + +static __inline void +ahc_platform_freeze_devq(struct ahc_softc *ahc, struct scb *scb) +{ + /* Nothing to do here for FreeBSD */ +} + +static __inline int +ahc_platform_abort_scbs(struct ahc_softc *ahc, int target, + char channel, int lun, u_int tag, + role_t role, uint32_t status) +{ + /* Nothing to do here for FreeBSD */ + return (0); +} + +/********************************** PCI ***************************************/ +#ifdef AHC_SUPPORT_PCI +static __inline uint32_t ahc_pci_read_config(ahc_dev_softc_t pci, + int reg, int width); +static __inline void ahc_pci_write_config(ahc_dev_softc_t pci, + int reg, uint32_t value, + int width); +static __inline int ahc_get_pci_function(ahc_dev_softc_t); +static __inline int ahc_get_pci_slot(ahc_dev_softc_t); +static __inline int ahc_get_pci_bus(ahc_dev_softc_t); + +int ahc_pci_map_registers(struct ahc_softc *ahc); +int ahc_pci_map_int(struct ahc_softc *ahc); + +static __inline uint32_t +ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width) +{ + return (pci_read_config(pci, reg, width)); +} + +static __inline void +ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width) +{ + pci_write_config(pci, reg, value, width); +} + +static __inline int +ahc_get_pci_function(ahc_dev_softc_t pci) +{ + return (pci_get_function(pci)); +} + +static __inline int +ahc_get_pci_slot(ahc_dev_softc_t pci) +{ + return (pci_get_slot(pci)); +} + +static __inline int +ahc_get_pci_bus(ahc_dev_softc_t pci) +{ + return (pci_get_bus(pci)); +} +#endif +/******************************** VL/EISA *************************************/ +int aic7770_map_registers(struct ahc_softc *ahc); +int aic7770_map_int(struct ahc_softc *ahc); + +/********************************* Debug **************************************/ +static __inline void ahc_print_path(struct ahc_softc *, struct scb *); +static __inline void ahc_platform_dump_card_state(struct ahc_softc *ahc); + +static __inline void +ahc_print_path(struct ahc_softc *ahc, struct scb *scb) +{ + xpt_print_path(scb->io_ctx->ccb_h.path); +} + +static __inline void +ahc_platform_dump_card_state(struct ahc_softc *ahc) +{ + /* Nothing to do here for FreeBSD */ +} +/**************************** Transfer Settings *******************************/ +void ahc_notify_xfer_settings_change(struct ahc_softc *, + struct ahc_devinfo *); +void ahc_platform_set_tags(struct ahc_softc *, struct ahc_devinfo *, + int /*enable*/); + +/***************************** Initialization *********************************/ +int ahc_platform_alloc(struct ahc_softc *ahc, void *platform_arg); +void ahc_platform_free(struct ahc_softc *ahc); +int ahc_attach(struct ahc_softc *); +int ahc_softc_comp(struct ahc_softc *lahc, struct ahc_softc *rahc); + +/************************ Misc Function Declarations **************************/ +timeout_t ahc_timeout; +void ahc_done(struct ahc_softc *ahc, struct scb *scb); +void ahc_send_async(struct ahc_softc *, struct ahc_devinfo *, ac_code); +#endif /* _AIC7XXX_FREEBSD_H_ */ diff --git a/sys/dev/aic7xxx/aic7xxx_pci.c b/sys/dev/aic7xxx/aic7xxx_pci.c new file mode 100644 index 000000000000..96ff260c3191 --- /dev/null +++ b/sys/dev/aic7xxx/aic7xxx_pci.c @@ -0,0 +1,1921 @@ +/* + * Product specific probe and attach routines for: + * 3940, 2940, aic7895, aic7890, aic7880, + * aic7870, aic7860 and aic7850 SCSI controllers + * + * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + * + * $FreeBSD$ + */ + +#ifdef __linux__ +#include "aic7xxx_linux.h" +#include "aic7xxx_inline.h" +#include "aic7xxx_93cx6.h" +#endif + +#ifdef __FreeBSD__ +#include <dev/aic7xxx/aic7xxx_freebsd.h> +#include <dev/aic7xxx/aic7xxx_inline.h> +#include <dev/aic7xxx/aic7xxx_93cx6.h> +#endif + +#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ +#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ + +static __inline uint64_t +ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) +{ + uint64_t id; + + id = subvendor + | (subdevice << 16) + | ((uint64_t)vendor << 32) + | ((uint64_t)device << 48); + + return (id); +} + +#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull +#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull +#define ID_AIC7850 0x5078900400000000ull +#define ID_AHA_2910_15_20_30C 0x5078900478509004ull +#define ID_AIC7855 0x5578900400000000ull +#define ID_AIC7859 0x3860900400000000ull +#define ID_AHA_2930CU 0x3860900438699004ull +#define ID_AIC7860 0x6078900400000000ull +#define ID_AIC7860C 0x6078900478609004ull +#define ID_AHA_1480A 0x6075900400000000ull +#define ID_AHA_2940AU_0 0x6178900400000000ull +#define ID_AHA_2940AU_1 0x6178900478619004ull +#define ID_AHA_2940AU_CN 0x2178900478219004ull +#define ID_AHA_2930C_VAR 0x6038900438689004ull + +#define ID_AIC7870 0x7078900400000000ull +#define ID_AHA_2940 0x7178900400000000ull +#define ID_AHA_3940 0x7278900400000000ull +#define ID_AHA_398X 0x7378900400000000ull +#define ID_AHA_2944 0x7478900400000000ull +#define ID_AHA_3944 0x7578900400000000ull +#define ID_AHA_4944 0x7678900400000000ull + +#define ID_AIC7880 0x8078900400000000ull +#define ID_AIC7880_B 0x8078900478809004ull +#define ID_AHA_2940U 0x8178900400000000ull +#define ID_AHA_3940U 0x8278900400000000ull +#define ID_AHA_2944U 0x8478900400000000ull +#define ID_AHA_3944U 0x8578900400000000ull +#define ID_AHA_398XU 0x8378900400000000ull +#define ID_AHA_4944U 0x8678900400000000ull +#define ID_AHA_2940UB 0x8178900478819004ull +#define ID_AHA_2930U 0x8878900478889004ull +#define ID_AHA_2940U_PRO 0x8778900478879004ull +#define ID_AHA_2940U_CN 0x0078900478009004ull + +#define ID_AIC7895 0x7895900478959004ull +#define ID_AIC7895_RAID_PORT 0x7893900478939004ull +#define ID_AHA_2940U_DUAL 0x7895900478919004ull +#define ID_AHA_3940AU 0x7895900478929004ull +#define ID_AHA_3944AU 0x7895900478949004ull + +#define ID_AIC7890 0x001F9005000F9005ull +#define ID_AAA_131U2 0x0013900500039005ull +#define ID_AHA_2930U2 0x0011900501819005ull +#define ID_AHA_2940U2B 0x00109005A1009005ull +#define ID_AHA_2940U2_OEM 0x0010900521809005ull +#define ID_AHA_2940U2 0x00109005A1809005ull +#define ID_AHA_2950U2B 0x00109005E1009005ull + +#define ID_AIC7892 0x008F9005FFFF9005ull +#define ID_AHA_29160 0x00809005E2A09005ull +#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull +#define ID_AHA_29160N 0x0080900562A09005ull +#define ID_AHA_29160B 0x00809005E2209005ull +#define ID_AHA_19160B 0x0081900562A19005ull + +#define ID_AIC7896 0x005F9005FFFF9005ull +#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull +#define ID_AHA_3950U2B_1 0x00509005F5009005ull +#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull +#define ID_AHA_3950U2D_1 0x00519005B5009005ull + +#define ID_AIC7899 0x00CF9005FFFF9005ull +#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ +#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull + +#define ID_AIC7810 0x1078900400000000ull +#define ID_AIC7815 0x7815900400000000ull + +static ahc_device_setup_t ahc_aic7850_setup; +static ahc_device_setup_t ahc_aic7855_setup; +static ahc_device_setup_t ahc_aic7860_setup; +static ahc_device_setup_t ahc_aic7870_setup; +static ahc_device_setup_t ahc_aha394X_setup; +static ahc_device_setup_t ahc_aha494X_setup; +static ahc_device_setup_t ahc_aha398X_setup; +static ahc_device_setup_t ahc_aic7880_setup; +static ahc_device_setup_t ahc_2940Pro_setup; +static ahc_device_setup_t ahc_aha394XU_setup; +static ahc_device_setup_t ahc_aha398XU_setup; +static ahc_device_setup_t ahc_aic7890_setup; +static ahc_device_setup_t ahc_aic7892_setup; +static ahc_device_setup_t ahc_aic7895_setup; +static ahc_device_setup_t ahc_aic7896_setup; +static ahc_device_setup_t ahc_aic7899_setup; +static ahc_device_setup_t ahc_raid_setup; +static ahc_device_setup_t ahc_aha394XX_setup; +static ahc_device_setup_t ahc_aha494XX_setup; +static ahc_device_setup_t ahc_aha398XX_setup; + +struct ahc_pci_identity ahc_pci_ident_table [] = +{ + /* aic7850 based controllers */ + { + ID_AHA_2910_15_20_30C, + ID_ALL_MASK, + "Adaptec 2910/15/20/30C SCSI adapter", + ahc_aic7850_setup + }, + /* aic7860 based controllers */ + { + ID_AHA_2930CU, + ID_ALL_MASK, + "Adaptec 2930CU SCSI adapter", + ahc_aic7860_setup + }, + { + ID_AHA_1480A & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 1480A Ultra SCSI adapter", + ahc_aic7860_setup + }, + { + ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2940A Ultra SCSI adapter", + ahc_aic7860_setup + }, + { + ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2940A/CN Ultra SCSI adapter", + ahc_aic7860_setup + }, + { + ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2930C SCSI adapter (VAR)", + ahc_aic7860_setup + }, + /* aic7870 based controllers */ + { + ID_AHA_2940, + ID_ALL_MASK, + "Adaptec 2940 SCSI adapter", + ahc_aic7870_setup + }, + { + ID_AHA_3940, + ID_ALL_MASK, + "Adaptec 3940 SCSI adapter", + ahc_aha394X_setup + }, + { + ID_AHA_398X, + ID_ALL_MASK, + "Adaptec 398X SCSI RAID adapter", + ahc_aha398X_setup + }, + { + ID_AHA_2944, + ID_ALL_MASK, + "Adaptec 2944 SCSI adapter", + ahc_aic7870_setup + }, + { + ID_AHA_3944, + ID_ALL_MASK, + "Adaptec 3944 SCSI adapter", + ahc_aha394X_setup + }, + { + ID_AHA_4944, + ID_ALL_MASK, + "Adaptec 4944 SCSI adapter", + ahc_aha494X_setup + }, + /* aic7880 based controllers */ + { + ID_AHA_2940U & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2940 Ultra SCSI adapter", + ahc_aic7880_setup + }, + { + ID_AHA_3940U & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 3940 Ultra SCSI adapter", + ahc_aha394XU_setup + }, + { + ID_AHA_2944U & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2944 Ultra SCSI adapter", + ahc_aic7880_setup + }, + { + ID_AHA_3944U & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 3944 Ultra SCSI adapter", + ahc_aha394XU_setup + }, + { + ID_AHA_398XU & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 398X Ultra SCSI RAID adapter", + ahc_aha398XU_setup + }, + { + /* + * XXX Don't know the slot numbers + * so we can't identify channels + */ + ID_AHA_4944U & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 4944 Ultra SCSI adapter", + ahc_aic7880_setup + }, + { + ID_AHA_2930U & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2930 Ultra SCSI adapter", + ahc_aic7880_setup + }, + { + ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2940 Pro Ultra SCSI adapter", + ahc_2940Pro_setup + }, + { + ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec 2940/CN Ultra SCSI adapter", + ahc_aic7880_setup + }, + /* aic7890 based controllers */ + { + ID_AHA_2930U2, + ID_ALL_MASK, + "Adaptec 2930 Ultra2 SCSI adapter", + ahc_aic7890_setup + }, + { + ID_AHA_2940U2B, + ID_ALL_MASK, + "Adaptec 2940B Ultra2 SCSI adapter", + ahc_aic7890_setup + }, + { + ID_AHA_2940U2_OEM, + ID_ALL_MASK, + "Adaptec 2940 Ultra2 SCSI adapter (OEM)", + ahc_aic7890_setup + }, + { + ID_AHA_2940U2, + ID_ALL_MASK, + "Adaptec 2940 Ultra2 SCSI adapter", + ahc_aic7890_setup + }, + { + ID_AHA_2950U2B, + ID_ALL_MASK, + "Adaptec 2950 Ultra2 SCSI adapter", + ahc_aic7890_setup + }, + { + ID_AAA_131U2, + ID_ALL_MASK, + "Adaptec AAA-131 Ultra2 RAID adapter", + ahc_aic7890_setup + }, + /* aic7892 based controllers */ + { + ID_AHA_29160, + ID_ALL_MASK, + "Adaptec 29160 Ultra160 SCSI adapter", + ahc_aic7892_setup + }, + { + ID_AHA_29160_CPQ, + ID_ALL_MASK, + "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", + ahc_aic7892_setup + }, + { + ID_AHA_29160N, + ID_ALL_MASK, + "Adaptec 29160N Ultra160 SCSI adapter", + ahc_aic7892_setup + }, + { + ID_AHA_29160B, + ID_ALL_MASK, + "Adaptec 29160B Ultra160 SCSI adapter", + ahc_aic7892_setup + }, + { + ID_AHA_19160B, + ID_ALL_MASK, + "Adaptec 19160B Ultra160 SCSI adapter", + ahc_aic7892_setup + }, + /* aic7895 based controllers */ + { + ID_AHA_2940U_DUAL, + ID_ALL_MASK, + "Adaptec 2940/DUAL Ultra SCSI adapter", + ahc_aic7895_setup + }, + { + ID_AHA_3940AU, + ID_ALL_MASK, + "Adaptec 3940A Ultra SCSI adapter", + ahc_aic7895_setup + }, + { + ID_AHA_3944AU, + ID_ALL_MASK, + "Adaptec 3944A Ultra SCSI adapter", + ahc_aic7895_setup + }, + /* aic7896/97 based controllers */ + { + ID_AHA_3950U2B_0, + ID_ALL_MASK, + "Adaptec 3950B Ultra2 SCSI adapter", + ahc_aic7896_setup + }, + { + ID_AHA_3950U2B_1, + ID_ALL_MASK, + "Adaptec 3950B Ultra2 SCSI adapter", + ahc_aic7896_setup + }, + { + ID_AHA_3950U2D_0, + ID_ALL_MASK, + "Adaptec 3950D Ultra2 SCSI adapter", + ahc_aic7896_setup + }, + { + ID_AHA_3950U2D_1, + ID_ALL_MASK, + "Adaptec 3950D Ultra2 SCSI adapter", + ahc_aic7896_setup + }, + /* aic7899 based controllers */ + { + ID_AHA_3960D, + ID_ALL_MASK, + "Adaptec 3960D Ultra160 SCSI adapter", + ahc_aic7899_setup + }, + { + ID_AHA_3960D_CPQ, + ID_ALL_MASK, + "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", + ahc_aic7899_setup + }, + /* Generic chip probes for devices we don't know 'exactly' */ + { + ID_AIC7850 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7850 SCSI adapter", + ahc_aic7850_setup + }, + { + ID_AIC7855 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7855 SCSI adapter", + ahc_aic7855_setup + }, + { + ID_AIC7859 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7859 Ultra SCSI adapter", + ahc_aic7860_setup + }, + { + ID_AIC7860 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7860 SCSI adapter", + ahc_aic7860_setup + }, + { + ID_AIC7870 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7870 SCSI adapter", + ahc_aic7870_setup + }, + { + ID_AIC7880 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7880 Ultra SCSI adapter", + ahc_aic7880_setup + }, + { + ID_AIC7890 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7890/91 Ultra2 SCSI adapter", + ahc_aic7890_setup + }, + { + ID_AIC7892 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7892 Ultra160 SCSI adapter", + ahc_aic7892_setup + }, + { + ID_AIC7895 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7895 Ultra SCSI adapter", + ahc_aic7895_setup + }, + { + ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", + ahc_aic7895_setup + }, + { + ID_AIC7896 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7896/97 Ultra2 SCSI adapter", + ahc_aic7896_setup + }, + { + ID_AIC7899 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7899 Ultra160 SCSI adapter", + ahc_aic7899_setup + }, + { + ID_AIC7810 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7810 RAID memory controller", + ahc_raid_setup + }, + { + ID_AIC7815 & ID_DEV_VENDOR_MASK, + ID_DEV_VENDOR_MASK, + "Adaptec aic7815 RAID memory controller", + ahc_raid_setup + } +}; + +const int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); + +#define AHC_394X_SLOT_CHANNEL_A 4 +#define AHC_394X_SLOT_CHANNEL_B 5 + +#define AHC_398X_SLOT_CHANNEL_A 4 +#define AHC_398X_SLOT_CHANNEL_B 8 +#define AHC_398X_SLOT_CHANNEL_C 12 + +#define AHC_494X_SLOT_CHANNEL_A 4 +#define AHC_494X_SLOT_CHANNEL_B 5 +#define AHC_494X_SLOT_CHANNEL_C 6 +#define AHC_494X_SLOT_CHANNEL_D 7 + +#define DEVCONFIG 0x40 +#define SCBSIZE32 0x00010000ul /* aic789X only */ +#define MPORTMODE 0x00000400ul /* aic7870 only */ +#define RAMPSM 0x00000200ul /* aic7870 only */ +#define VOLSENSE 0x00000100ul +#define SCBRAMSEL 0x00000080ul +#define MRDCEN 0x00000040ul +#define EXTSCBTIME 0x00000020ul /* aic7870 only */ +#define EXTSCBPEN 0x00000010ul /* aic7870 only */ +#define BERREN 0x00000008ul +#define DACEN 0x00000004ul +#define STPWLEVEL 0x00000002ul +#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ + +#define CSIZE_LATTIME 0x0c +#define CACHESIZE 0x0000003ful /* only 5 bits */ +#define LATTIME 0x0000ff00ul + +static int ahc_ext_scbram_present(struct ahc_softc *ahc); +static void ahc_scbram_config(struct ahc_softc *ahc, int enable, + int pcheck, int fast, int large); +static void ahc_probe_ext_scbram(struct ahc_softc *ahc); +static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); +static void configure_termination(struct ahc_softc *ahc, + struct seeprom_descriptor *sd, + u_int adapter_control, + u_int *sxfrctl1); + +static void ahc_new_term_detect(struct ahc_softc *ahc, + int *enableSEC_low, + int *enableSEC_high, + int *enablePRI_low, + int *enablePRI_high, + int *eeprom_present); +static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, + int *internal68_present, + int *externalcable_present, + int *eeprom_present); +static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, + int *externalcable_present, + int *eeprom_present); +static int acquire_seeprom(struct ahc_softc *ahc, + struct seeprom_descriptor *sd); +static void release_seeprom(struct seeprom_descriptor *sd); +static void write_brdctl(struct ahc_softc *ahc, uint8_t value); +static uint8_t read_brdctl(struct ahc_softc *ahc); + +struct ahc_pci_identity * +ahc_find_pci_device(ahc_dev_softc_t pci) +{ + uint64_t full_id; + uint16_t device; + uint16_t vendor; + uint16_t subdevice; + uint16_t subvendor; + struct ahc_pci_identity *entry; + u_int i; + + vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); + device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); + subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); + subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); + full_id = ahc_compose_id(device, + vendor, + subdevice, + subvendor); + + for (i = 0; i < ahc_num_pci_devs; i++) { + entry = &ahc_pci_ident_table[i]; + if (entry->full_id == (full_id & entry->id_mask)) + return (entry); + } + return (NULL); +} + +int +ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) +{ + struct ahc_probe_config probe_config; + struct scb_data *shared_scb_data; + u_int command; + u_int our_id = 0; + u_int sxfrctl1; + u_int scsiseq; + u_int dscommand0; + int error; + uint8_t sblkctl; + + shared_scb_data = NULL; + ahc_init_probe_config(&probe_config); + error = entry->setup(ahc->dev_softc, &probe_config); + if (error != 0) + return (error); + probe_config.chip |= AHC_PCI; + probe_config.description = entry->name; + + error = ahc_pci_map_registers(ahc); + if (error != 0) + return (error); + + /* Ensure busmastering is enabled */ + command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); + command |= PCIM_CMD_BUSMASTEREN; + ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); + + /* On all PCI adapters, we allow SCB paging */ + probe_config.flags |= AHC_PAGESCBS; + + error = ahc_softc_init(ahc, &probe_config); + if (error != 0) + return (error); + + /* Remeber how the card was setup in case there is no SEEPROM */ + pause_sequencer(ahc); + if ((ahc->features & AHC_ULTRA2) != 0) + our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; + else + our_id = ahc_inb(ahc, SCSIID) & OID; + sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; + scsiseq = ahc_inb(ahc, SCSISEQ); + + error = ahc_reset(ahc); + if (error != 0) + return (ENXIO); + + if ((ahc->features & AHC_DT) != 0) { + u_int sfunct; + + /* Perform ALT-Mode Setup */ + sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; + ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); + ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); + /* Send CRC info in target mode every 4K */ + ahc_outb(ahc, TARGCRCCNT, 0); + ahc_outb(ahc, TARGCRCCNT + 1, 0x10); + ahc_outb(ahc, SFUNCT, sfunct); + + /* Normal mode setup */ + ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN + |TARGCRCENDEN|TARGCRCCNTEN); + } + + error = ahc_pci_map_int(ahc); + if (error != 0) + return (error); + dscommand0 = ahc_inb(ahc, DSCOMMAND0); + dscommand0 |= MPARCKEN; + if ((ahc->features & AHC_ULTRA2) != 0) { + + /* + * DPARCKEN doesn't work correctly on + * some MBs so don't use it. + */ + dscommand0 &= ~DPARCKEN; + dscommand0 |= CACHETHEN; + } + + /* + * Handle chips that must have cache line + * streaming (dis/en)abled. + */ + if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) + dscommand0 |= CACHETHEN; + + if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) + dscommand0 &= ~CACHETHEN; + + ahc_outb(ahc, DSCOMMAND0, dscommand0); + + ahc->pci_cachesize = + ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, + /*bytes*/1) & CACHESIZE; + ahc->pci_cachesize *= 4; + + /* See if we have a SEEPROM and perform auto-term */ + check_extport(ahc, &sxfrctl1); + + /* + * Take the LED out of diagnostic mode + */ + sblkctl = ahc_inb(ahc, SBLKCTL); + ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); + + /* + * I don't know where this is set in the SEEPROM or by the + * BIOS, so we default to 100% on Ultra or slower controllers + * and 75% on ULTRA2 controllers. + */ + if ((ahc->features & AHC_ULTRA2) != 0) { + ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); + } else { + ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); + } + + if (ahc->flags & AHC_USEDEFAULTS) { + /* + * PCI Adapter default setup + * Should only be used if the adapter does not have + * a SEEPROM. + */ + /* See if someone else set us up already */ + if (scsiseq != 0) { + printf("%s: Using left over BIOS settings\n", + ahc_name(ahc)); + ahc->flags &= ~AHC_USEDEFAULTS; + } else { + /* + * Assume only one connector and always turn + * on termination. + */ + our_id = 0x07; + sxfrctl1 = STPWEN; + } + ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); + + ahc->our_id = our_id; + } + + /* + * Take a look to see if we have external SRAM. + * We currently do not attempt to use SRAM that is + * shared among multiple controllers. + */ + ahc_probe_ext_scbram(ahc); + + /* + * Record our termination setting for the + * generic initialization routine. + */ + if ((sxfrctl1 & STPWEN) != 0) + ahc->flags |= AHC_TERM_ENB_A; + + /* Core initialization */ + error = ahc_init(ahc); + if (error != 0) + return (error); + + /* + * Link this softc in with all other ahc instances. + */ + ahc_softc_insert(ahc); + + return (0); +} + +/* + * Test for the presense of external sram in an + * "unshared" configuration. + */ +static int +ahc_ext_scbram_present(struct ahc_softc *ahc) +{ + int ramps; + int single_user; + uint32_t devconfig; + + devconfig = ahc_pci_read_config(ahc->dev_softc, + DEVCONFIG, /*bytes*/4); + single_user = (devconfig & MPORTMODE) != 0; + + if ((ahc->features & AHC_ULTRA2) != 0) + ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; + else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) + ramps = (devconfig & RAMPSM) != 0; + else + ramps = 0; + + if (ramps && single_user) + return (1); + return (0); +} + +/* + * Enable external scbram. + */ +static void +ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, + int fast, int large) +{ + uint32_t devconfig; + + if (ahc->features & AHC_MULTI_FUNC) { + /* + * Set the SCB Base addr (highest address bit) + * depending on which channel we are. + */ + ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); + } + + devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); + if ((ahc->features & AHC_ULTRA2) != 0) { + u_int dscommand0; + + dscommand0 = ahc_inb(ahc, DSCOMMAND0); + if (enable) + dscommand0 &= ~INTSCBRAMSEL; + else + dscommand0 |= INTSCBRAMSEL; + if (large) + dscommand0 &= ~USCBSIZE32; + else + dscommand0 |= USCBSIZE32; + ahc_outb(ahc, DSCOMMAND0, dscommand0); + } else { + if (fast) + devconfig &= ~EXTSCBTIME; + else + devconfig |= EXTSCBTIME; + if (enable) + devconfig &= ~SCBRAMSEL; + else + devconfig |= SCBRAMSEL; + if (large) + devconfig &= ~SCBSIZE32; + else + devconfig |= SCBSIZE32; + } + if (pcheck) + devconfig |= EXTSCBPEN; + else + devconfig &= ~EXTSCBPEN; + + ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); +} + +/* + * Take a look to see if we have external SRAM. + * We currently do not attempt to use SRAM that is + * shared among multiple controllers. + */ +static void +ahc_probe_ext_scbram(struct ahc_softc *ahc) +{ + int num_scbs; + int test_num_scbs; + int enable; + int pcheck; + int fast; + int large; + + enable = FALSE; + pcheck = FALSE; + fast = FALSE; + large = FALSE; + num_scbs = 0; + + if (ahc_ext_scbram_present(ahc) == 0) + goto done; + + /* + * Probe for the best parameters to use. + */ + ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); + num_scbs = ahc_probe_scbs(ahc); + if (num_scbs == 0) { + /* The SRAM wasn't really present. */ + goto done; + } + enable = TRUE; + + /* + * Clear any outstanding parity error + * and ensure that parity error reporting + * is enabled. + */ + ahc_outb(ahc, SEQCTL, 0); + ahc_outb(ahc, CLRINT, CLRPARERR); + ahc_outb(ahc, CLRINT, CLRBRKADRINT); + + /* Now see if we can do parity */ + ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); + num_scbs = ahc_probe_scbs(ahc); + if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 + || (ahc_inb(ahc, ERROR) & MPARERR) == 0) + pcheck = TRUE; + + /* Clear any resulting parity error */ + ahc_outb(ahc, CLRINT, CLRPARERR); + ahc_outb(ahc, CLRINT, CLRBRKADRINT); + + /* Now see if we can do fast timing */ + ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); + test_num_scbs = ahc_probe_scbs(ahc); + if (test_num_scbs == num_scbs + && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 + || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) + fast = TRUE; + + /* + * See if we can use large SCBs and still maintain + * the same overall count of SCBs. + */ + if ((ahc->features & AHC_LARGE_SCBS) != 0) { + ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); + test_num_scbs = ahc_probe_scbs(ahc); + if (test_num_scbs >= num_scbs) { + large = TRUE; + num_scbs = test_num_scbs; + if (num_scbs >= 64) { + /* + * We have enough space to move the + * "busy targets table" into SCB space + * and make it qualify all the way to the + * lun level. + */ + ahc->flags |= AHC_SCB_BTT; + } + } + } +done: + /* + * Disable parity error reporting until we + * can load instruction ram. + */ + ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); + /* Clear any latched parity error */ + ahc_outb(ahc, CLRINT, CLRPARERR); + ahc_outb(ahc, CLRINT, CLRBRKADRINT); + if (bootverbose && enable) { + printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", + ahc_name(ahc), fast ? "fast" : "slow", + pcheck ? ", parity checking enabled" : "", + large ? 64 : 32); + } + ahc_scbram_config(ahc, enable, pcheck, fast, large); +} + +/* + * Check the external port logic for a serial eeprom + * and termination/cable detection contrls. + */ +static void +check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) +{ + struct seeprom_descriptor sd; + struct seeprom_config sc; + u_int scsi_conf; + u_int adapter_control; + int have_seeprom; + int have_autoterm; + + sd.sd_ahc = ahc; + sd.sd_control_offset = SEECTL; + sd.sd_status_offset = SEECTL; + sd.sd_dataout_offset = SEECTL; + + /* + * For some multi-channel devices, the c46 is simply too + * small to work. For the other controller types, we can + * get our information from either SEEPROM type. Set the + * type to start our probe with accordingly. + */ + if (ahc->flags & AHC_LARGE_SEEPROM) + sd.sd_chip = C56_66; + else + sd.sd_chip = C46; + + sd.sd_MS = SEEMS; + sd.sd_RDY = SEERDY; + sd.sd_CS = SEECS; + sd.sd_CK = SEECK; + sd.sd_DO = SEEDO; + sd.sd_DI = SEEDI; + + have_seeprom = acquire_seeprom(ahc, &sd); + if (have_seeprom) { + + if (bootverbose) + printf("%s: Reading SEEPROM...", ahc_name(ahc)); + + for (;;) { + u_int start_addr; + + start_addr = 32 * (ahc->channel - 'A'); + + have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, + start_addr, sizeof(sc)/2); + + if (have_seeprom) + have_seeprom = verify_cksum(&sc); + + if (have_seeprom != 0 || sd.sd_chip == C56_66) { + if (bootverbose) { + if (have_seeprom == 0) + printf ("checksum error\n"); + else + printf ("done.\n"); + } + break; + } + sd.sd_chip = C56_66; + } + } + +#if 0 + if (!have_seeprom) { + /* + * Pull scratch ram settings and treat them as + * if they are the contents of an seeprom if + * the 'ADPT' signature is found in SCB2. + */ + ahc_outb(ahc, SCBPTR, 2); + if (ahc_inb(ahc, SCB_BASE) == 'A' + && ahc_inb(ahc, SCB_BASE + 1) == 'D' + && ahc_inb(ahc, SCB_BASE + 2) == 'P' + && ahc_inb(ahc, SCB_BASE + 3) == 'T') { + uint8_t *sc_bytes; + int i; + + sc_bytes = (uint8_t *)≻ + for (i = 0; i < 64; i++) + sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); + /* Byte 0x1c is stored in byte 4 of SCB2 */ + sc_bytes[0x1c] = ahc_inb(ahc, SCB_BASE + 4); + have_seeprom = verify_cksum(&sc); + } + } +#endif + + if (!have_seeprom) { + if (bootverbose) + printf("%s: No SEEPROM available.\n", ahc_name(ahc)); + ahc->flags |= AHC_USEDEFAULTS; + } else { + /* + * Put the data we've collected down into SRAM + * where ahc_init will find it. + */ + int i; + int max_targ = sc.max_targets & CFMAXTARG; + uint16_t discenable; + uint16_t ultraenb; + + discenable = 0; + ultraenb = 0; + if ((sc.adapter_control & CFULTRAEN) != 0) { + /* + * Determine if this adapter has a "newstyle" + * SEEPROM format. + */ + for (i = 0; i < max_targ; i++) { + if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ + ahc->flags |= AHC_NEWEEPROM_FMT; + break; + } + } + } + + for (i = 0; i < max_targ; i++) { + u_int scsirate; + uint16_t target_mask; + + target_mask = 0x01 << i; + if (sc.device_flags[i] & CFDISC) + discenable |= target_mask; + if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { + if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) + ultraenb |= target_mask; + } else if ((sc.adapter_control & CFULTRAEN) != 0) { + ultraenb |= target_mask; + } + if ((sc.device_flags[i] & CFXFER) == 0x04 + && (ultraenb & target_mask) != 0) { + /* Treat 10MHz as a non-ultra speed */ + sc.device_flags[i] &= ~CFXFER; + ultraenb &= ~target_mask; + } + if ((ahc->features & AHC_ULTRA2) != 0) { + u_int offset; + + if (sc.device_flags[i] & CFSYNCH) + offset = MAX_OFFSET_ULTRA2; + else + offset = 0; + ahc_outb(ahc, TARG_OFFSET + i, offset); + + /* + * The ultra enable bits contain the + * high bit of the ultra2 sync rate + * field. + */ + scsirate = (sc.device_flags[i] & CFXFER) + | ((ultraenb & target_mask) + ? 0x8 : 0x0); + if (sc.device_flags[i] & CFWIDEB) + scsirate |= WIDEXFER; + } else { + scsirate = (sc.device_flags[i] & CFXFER) << 4; + if (sc.device_flags[i] & CFSYNCH) + scsirate |= SOFS; + if (sc.device_flags[i] & CFWIDEB) + scsirate |= WIDEXFER; + } + ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); + } + ahc->our_id = sc.brtime_id & CFSCSIID; + + scsi_conf = (ahc->our_id & 0x7); + if (sc.adapter_control & CFSPARITY) + scsi_conf |= ENSPCHK; + if (sc.adapter_control & CFRESETB) + scsi_conf |= RESET_SCSI; + + if (sc.bios_control & CFEXTEND) + ahc->flags |= AHC_EXTENDED_TRANS_A; + if (ahc->features & AHC_ULTRA + && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { + /* Should we enable Ultra mode? */ + if (!(sc.adapter_control & CFULTRAEN)) + /* Treat us as a non-ultra card */ + ultraenb = 0; + } + + if (sc.signature == CFSIGNATURE) { + uint32_t devconfig; + + /* Honor the STPWLEVEL settings */ + devconfig = ahc_pci_read_config(ahc->dev_softc, + DEVCONFIG, /*bytes*/4); + devconfig &= ~STPWLEVEL; + if ((sc.bios_control & CFSTPWLEVEL) != 0) + devconfig |= STPWLEVEL; + ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, + devconfig, /*bytes*/4); + } + /* Set SCSICONF info */ + ahc_outb(ahc, SCSICONF, scsi_conf); + ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); + ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); + ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); + ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); + } + + /* + * Cards that have the external logic necessary to talk to + * a SEEPROM, are almost certain to have the remaining logic + * necessary for auto-termination control. This assumption + * hasn't failed yet... + */ + have_autoterm = have_seeprom; + if (have_seeprom) + adapter_control = sc.adapter_control; + else + adapter_control = CFAUTOTERM; + + /* + * Some low-cost chips have SEEPROM and auto-term control built + * in, instead of using a GAL. They can tell us directly + * if the termination logic is enabled. + */ + if ((ahc->features & AHC_SPIOCAP) != 0) { + if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) + have_autoterm = TRUE; + else + have_autoterm = FALSE; + } + + if (have_autoterm) + configure_termination(ahc, &sd, adapter_control, sxfrctl1); + + release_seeprom(&sd); +} + +static void +configure_termination(struct ahc_softc *ahc, + struct seeprom_descriptor *sd, + u_int adapter_control, + u_int *sxfrctl1) +{ + uint8_t brddat; + + brddat = 0; + + /* + * Update the settings in sxfrctl1 to match the + * termination settings + */ + *sxfrctl1 = 0; + + /* + * SEECS must be on for the GALS to latch + * the data properly. Be sure to leave MS + * on or we will release the seeprom. + */ + SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); + if ((adapter_control & CFAUTOTERM) != 0 + || (ahc->features & AHC_NEW_TERMCTL) != 0) { + int internal50_present; + int internal68_present; + int externalcable_present; + int eeprom_present; + int enableSEC_low; + int enableSEC_high; + int enablePRI_low; + int enablePRI_high; + + enableSEC_low = 0; + enableSEC_high = 0; + enablePRI_low = 0; + enablePRI_high = 0; + if ((ahc->features & AHC_NEW_TERMCTL) != 0) { + ahc_new_term_detect(ahc, &enableSEC_low, + &enableSEC_high, + &enablePRI_low, + &enablePRI_high, + &eeprom_present); + if ((adapter_control & CFSEAUTOTERM) == 0) { + if (bootverbose) + printf("%s: Manual SE Termination\n", + ahc_name(ahc)); + enableSEC_low = (adapter_control & CFSELOWTERM); + enableSEC_high = + (adapter_control & CFSEHIGHTERM); + } + if ((adapter_control & CFAUTOTERM) == 0) { + if (bootverbose) + printf("%s: Manual LVD Termination\n", + ahc_name(ahc)); + enablePRI_low = (adapter_control & CFSTERM); + enablePRI_high = (adapter_control & CFWSTERM); + } + /* Make the table calculations below happy */ + internal50_present = 0; + internal68_present = 1; + externalcable_present = 1; + } else if ((ahc->features & AHC_SPIOCAP) != 0) { + aic785X_cable_detect(ahc, &internal50_present, + &externalcable_present, + &eeprom_present); + } else { + aic787X_cable_detect(ahc, &internal50_present, + &internal68_present, + &externalcable_present, + &eeprom_present); + } + + if ((ahc->features & AHC_WIDE) == 0) + internal68_present = 0; + + if (bootverbose) { + if ((ahc->features & AHC_ULTRA2) == 0) { + printf("%s: internal 50 cable %s present, " + "internal 68 cable %s present\n", + ahc_name(ahc), + internal50_present ? "is":"not", + internal68_present ? "is":"not"); + + printf("%s: external cable %s present\n", + ahc_name(ahc), + externalcable_present ? "is":"not"); + } + printf("%s: BIOS eeprom %s present\n", + ahc_name(ahc), eeprom_present ? "is" : "not"); + } + + if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { + /* + * The 50 pin connector is a separate bus, + * so force it to always be terminated. + * In the future, perform current sensing + * to determine if we are in the middle of + * a properly terminated bus. + */ + internal50_present = 0; + } + + /* + * Now set the termination based on what + * we found. + * Flash Enable = BRDDAT7 + * Secondary High Term Enable = BRDDAT6 + * Secondary Low Term Enable = BRDDAT5 (7890) + * Primary High Term Enable = BRDDAT4 (7890) + */ + if ((ahc->features & AHC_ULTRA2) == 0 + && (internal50_present != 0) + && (internal68_present != 0) + && (externalcable_present != 0)) { + printf("%s: Illegal cable configuration!!. " + "Only two connectors on the " + "adapter may be used at a " + "time!\n", ahc_name(ahc)); + } + + if ((ahc->features & AHC_WIDE) != 0 + && ((externalcable_present == 0) + || (internal68_present == 0) + || (enableSEC_high != 0))) { + brddat |= BRDDAT6; + if (bootverbose) { + if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) + printf("%s: 68 pin termination " + "Enabled\n", ahc_name(ahc)); + else + printf("%s: %sHigh byte termination " + "Enabled\n", ahc_name(ahc), + enableSEC_high ? "Secondary " + : ""); + } + } + + if (((internal50_present ? 1 : 0) + + (internal68_present ? 1 : 0) + + (externalcable_present ? 1 : 0)) <= 1 + || (enableSEC_low != 0)) { + if ((ahc->features & AHC_ULTRA2) != 0) + brddat |= BRDDAT5; + else + *sxfrctl1 |= STPWEN; + if (bootverbose) { + if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) + printf("%s: 50 pin termination " + "Enabled\n", ahc_name(ahc)); + else + printf("%s: %sLow byte termination " + "Enabled\n", ahc_name(ahc), + enableSEC_low ? "Secondary " + : ""); + } + } + + if (enablePRI_low != 0) { + *sxfrctl1 |= STPWEN; + if (bootverbose) + printf("%s: Primary Low Byte termination " + "Enabled\n", ahc_name(ahc)); + } + + /* + * Setup STPWEN before setting up the rest of + * the termination per the tech note on the U160 cards. + */ + ahc_outb(ahc, SXFRCTL1, *sxfrctl1); + + if (enablePRI_high != 0) { + brddat |= BRDDAT4; + if (bootverbose) + printf("%s: Primary High Byte " + "termination Enabled\n", + ahc_name(ahc)); + } + + write_brdctl(ahc, brddat); + + } else { + if ((adapter_control & CFSTERM) != 0) { + *sxfrctl1 |= STPWEN; + + if (bootverbose) + printf("%s: %sLow byte termination Enabled\n", + ahc_name(ahc), + (ahc->features & AHC_ULTRA2) ? "Primary " + : ""); + } + + if ((adapter_control & CFWSTERM) != 0) { + brddat |= BRDDAT6; + if (bootverbose) + printf("%s: %sHigh byte termination Enabled\n", + ahc_name(ahc), + (ahc->features & AHC_ULTRA2) + ? "Secondary " : ""); + } + + /* + * Setup STPWEN before setting up the rest of + * the termination per the tech note on the U160 cards. + */ + ahc_outb(ahc, SXFRCTL1, *sxfrctl1); + + write_brdctl(ahc, brddat); + } + SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ +} + +static void +ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, + int *enableSEC_high, int *enablePRI_low, + int *enablePRI_high, int *eeprom_present) +{ + uint8_t brdctl; + + /* + * BRDDAT7 = Eeprom + * BRDDAT6 = Enable Secondary High Byte termination + * BRDDAT5 = Enable Secondary Low Byte termination + * BRDDAT4 = Enable Primary high byte termination + * BRDDAT3 = Enable Primary low byte termination + */ + brdctl = read_brdctl(ahc); + *eeprom_present = brdctl & BRDDAT7; + *enableSEC_high = (brdctl & BRDDAT6); + *enableSEC_low = (brdctl & BRDDAT5); + *enablePRI_high = (brdctl & BRDDAT4); + *enablePRI_low = (brdctl & BRDDAT3); +} + +static void +aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, + int *internal68_present, int *externalcable_present, + int *eeprom_present) +{ + uint8_t brdctl; + + /* + * First read the status of our cables. + * Set the rom bank to 0 since the + * bank setting serves as a multiplexor + * for the cable detection logic. + * BRDDAT5 controls the bank switch. + */ + write_brdctl(ahc, 0); + + /* + * Now read the state of the internal + * connectors. BRDDAT6 is INT50 and + * BRDDAT7 is INT68. + */ + brdctl = read_brdctl(ahc); + *internal50_present = !(brdctl & BRDDAT6); + *internal68_present = !(brdctl & BRDDAT7); + + /* + * Set the rom bank to 1 and determine + * the other signals. + */ + write_brdctl(ahc, BRDDAT5); + + /* + * Now read the state of the external + * connectors. BRDDAT6 is EXT68 and + * BRDDAT7 is EPROMPS. + */ + brdctl = read_brdctl(ahc); + *externalcable_present = !(brdctl & BRDDAT6); + *eeprom_present = brdctl & BRDDAT7; +} + +static void +aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, + int *externalcable_present, int *eeprom_present) +{ + uint8_t brdctl; + + ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); + ahc_outb(ahc, BRDCTL, 0); + brdctl = ahc_inb(ahc, BRDCTL); + *internal50_present = !(brdctl & BRDDAT5); + *externalcable_present = !(brdctl & BRDDAT6); + + *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; +} + +static int +acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) +{ + int wait; + + if ((ahc->features & AHC_SPIOCAP) != 0 + && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) + return (0); + + /* + * Request access of the memory port. When access is + * granted, SEERDY will go high. We use a 1 second + * timeout which should be near 1 second more than + * is needed. Reason: after the chip reset, there + * should be no contention. + */ + SEEPROM_OUTB(sd, sd->sd_MS); + wait = 1000; /* 1 second timeout in msec */ + while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { + ahc_delay(1000); /* delay 1 msec */ + } + if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { + SEEPROM_OUTB(sd, 0); + return (0); + } + return(1); +} + +static void +release_seeprom(struct seeprom_descriptor *sd) +{ + /* Release access to the memory port and the serial EEPROM. */ + SEEPROM_OUTB(sd, 0); +} + +static void +write_brdctl(struct ahc_softc *ahc, uint8_t value) +{ + uint8_t brdctl; + + if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { + brdctl = BRDSTB; + if (ahc->channel == 'B') + brdctl |= BRDCS; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + brdctl = 0; + } else { + brdctl = BRDSTB|BRDCS; + } + ahc_outb(ahc, BRDCTL, brdctl); + ahc_delay(20); + brdctl |= value; + ahc_outb(ahc, BRDCTL, brdctl); + ahc_delay(20); + if ((ahc->features & AHC_ULTRA2) != 0) + brdctl |= BRDSTB_ULTRA2; + else + brdctl &= ~BRDSTB; + ahc_outb(ahc, BRDCTL, brdctl); + ahc_delay(20); + if ((ahc->features & AHC_ULTRA2) != 0) + brdctl = 0; + else + brdctl &= ~BRDCS; + ahc_outb(ahc, BRDCTL, brdctl); +} + +static uint8_t +read_brdctl(ahc) + struct ahc_softc *ahc; +{ + uint8_t brdctl; + uint8_t value; + + if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { + brdctl = BRDRW; + if (ahc->channel == 'B') + brdctl |= BRDCS; + } else if ((ahc->features & AHC_ULTRA2) != 0) { + brdctl = BRDRW_ULTRA2; + } else { + brdctl = BRDRW|BRDCS; + } + ahc_outb(ahc, BRDCTL, brdctl); + ahc_delay(20); + value = ahc_inb(ahc, BRDCTL); + ahc_outb(ahc, BRDCTL, 0); + return (value); +} + +#define DPE 0x80 +#define SSE 0x40 +#define RMA 0x20 +#define RTA 0x10 +#define STA 0x08 +#define DPR 0x01 + +void +ahc_pci_intr(struct ahc_softc *ahc) +{ + uint8_t status1; + + status1 = ahc_pci_read_config(ahc->dev_softc, + PCIR_STATUS + 1, /*bytes*/1); + + if (status1 & (DPE|SSE|RMA|RTA|STA|DPR)) { + printf("%s: PCI Interrupt at seqaddr = 0x%x\n", + ahc_name(ahc), + ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); + } + if (status1 & DPE) { + printf("%s: Data Parity Error Detected during address " + "or write data phase\n", ahc_name(ahc)); + } + if (status1 & SSE) { + printf("%s: Signal System Error Detected\n", ahc_name(ahc)); + } + if (status1 & RMA) { + printf("%s: Received a Master Abort\n", ahc_name(ahc)); + } + if (status1 & RTA) { + printf("%s: Received a Target Abort\n", ahc_name(ahc)); + } + if (status1 & STA) { + printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); + } + if (status1 & DPR) { + printf("%s: Data Parity Error has been reported via PERR#\n", + ahc_name(ahc)); + } + if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { + printf("%s: Latched PCIERR interrupt with " + "no status bits set\n", ahc_name(ahc)); + } + ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, + status1, /*bytes*/1); + + if (status1 & (DPR|RMA|RTA)) { + ahc_outb(ahc, CLRINT, CLRPARERR); + } +} + +static int +ahc_aic7850_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7850; + probe_config->features = AHC_AIC7850_FE; + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG + | AHC_PCI_MWI_BUG; + return (0); +} + +static int +ahc_aic7855_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7855; + probe_config->features = AHC_AIC7855_FE; + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG + | AHC_PCI_MWI_BUG; + return (0); +} + +static int +ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + uint8_t rev; + + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7860; + probe_config->features = AHC_AIC7860_FE; + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG + | AHC_PCI_MWI_BUG; + rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); + if (rev >= 1) + probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; + return (0); +} + +static int +ahc_aic7870_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7870; + probe_config->features = AHC_AIC7870_FE; + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG + | AHC_PCI_MWI_BUG; + return (0); +} + +static int +ahc_aha394X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7870_setup(pci, probe_config); + if (error == 0) + error = ahc_aha394XX_setup(pci, probe_config); + return (error); +} + +static int +ahc_aha398X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7870_setup(pci, probe_config); + if (error == 0) + error = ahc_aha398XX_setup(pci, probe_config); + return (error); +} + +static int +ahc_aha494X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7870_setup(pci, probe_config); + if (error == 0) + error = ahc_aha494XX_setup(pci, probe_config); + return (error); +} + +static int +ahc_aic7880_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + uint8_t rev; + + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7880; + probe_config->features = AHC_AIC7880_FE; + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; + rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); + if (rev >= 1) { + probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; + } else { + probe_config->bugs |= AHC_CACHETHEN_BUG; + } + return (0); +} + +static int +ahc_2940Pro_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + int error; + + probe_config->flags |= AHC_INT50_SPEEDFLEX; + error = ahc_aic7880_setup(pci, probe_config); + return (0); +} + +static int +ahc_aha394XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7880_setup(pci, probe_config); + if (error == 0) + error = ahc_aha394XX_setup(pci, probe_config); + return (error); +} + +static int +ahc_aha398XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + int error; + + error = ahc_aic7880_setup(pci, probe_config); + if (error == 0) + error = ahc_aha398XX_setup(pci, probe_config); + return (error); +} + +static int +ahc_aic7890_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + uint8_t rev; + + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7890; + probe_config->features = AHC_AIC7890_FE; + probe_config->flags |= AHC_NEWEEPROM_FMT; + rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); + if (rev == 0) + probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; + return (0); +} + +static int +ahc_aic7892_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + probe_config->channel = 'A'; + probe_config->chip = AHC_AIC7892; + probe_config->features = AHC_AIC7892_FE; + probe_config->flags |= AHC_NEWEEPROM_FMT; + probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; + return (0); +} + +static int +ahc_aic7895_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + uint8_t rev; + + probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; + /* + * The 'C' revision of the aic7895 has a few additional features. + */ + rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); + if (rev >= 4) { + probe_config->chip = AHC_AIC7895C; + probe_config->features = AHC_AIC7895C_FE; + } else { + u_int command; + + probe_config->chip = AHC_AIC7895; + probe_config->features = AHC_AIC7895_FE; + + /* + * The BIOS disables the use of MWI transactions + * since it does not have the MWI bug work around + * we have. Disabling MWI reduces performance, so + * turn it on again. + */ + command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); + command |= PCIM_CMD_MWRICEN; + ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); + probe_config->bugs |= AHC_PCI_MWI_BUG; + } + /* + * XXX Does CACHETHEN really not work??? What about PCI retry? + * on C level chips. Need to test, but for now, play it safe. + */ + probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG + | AHC_CACHETHEN_BUG; + +#if 0 + uint32_t devconfig; + + /* + * Cachesize must also be zero due to stray DAC + * problem when sitting behind some bridges. + */ + ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); + devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); + devconfig |= MRDCEN; + ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); +#endif + probe_config->flags |= AHC_NEWEEPROM_FMT; + return (0); +} + +static int +ahc_aic7896_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; + probe_config->chip = AHC_AIC7896; + probe_config->features = AHC_AIC7896_FE; + probe_config->flags |= AHC_NEWEEPROM_FMT; + probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; + return (0); +} + +static int +ahc_aic7899_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; + probe_config->chip = AHC_AIC7899; + probe_config->features = AHC_AIC7899_FE; + probe_config->flags |= AHC_NEWEEPROM_FMT; + probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; + return (0); +} + +static int +ahc_raid_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + printf("RAID functionality unsupported\n"); + return (ENXIO); +} + +static int +ahc_aha394XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + switch (ahc_get_pci_slot(pci)) { + case AHC_394X_SLOT_CHANNEL_A: + probe_config->channel = 'A'; + break; + case AHC_394X_SLOT_CHANNEL_B: + probe_config->channel = 'B'; + break; + default: + printf("adapter at unexpected slot %d\n" + "unable to map to a channel\n", + ahc_get_pci_slot(pci)); + probe_config->channel = 'A'; + } + return (0); +} + +static int +ahc_aha398XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + switch (ahc_get_pci_slot(pci)) { + case AHC_398X_SLOT_CHANNEL_A: + probe_config->channel = 'A'; + break; + case AHC_398X_SLOT_CHANNEL_B: + probe_config->channel = 'B'; + break; + case AHC_398X_SLOT_CHANNEL_C: + probe_config->channel = 'C'; + break; + default: + printf("adapter at unexpected slot %d\n" + "unable to map to a channel\n", + ahc_get_pci_slot(pci)); + probe_config->channel = 'A'; + break; + } + probe_config->flags |= AHC_LARGE_SEEPROM; + return (0); +} + +static int +ahc_aha494XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) +{ + switch (ahc_get_pci_slot(pci)) { + case AHC_494X_SLOT_CHANNEL_A: + probe_config->channel = 'A'; + break; + case AHC_494X_SLOT_CHANNEL_B: + probe_config->channel = 'B'; + break; + case AHC_494X_SLOT_CHANNEL_C: + probe_config->channel = 'C'; + break; + case AHC_494X_SLOT_CHANNEL_D: + probe_config->channel = 'D'; + break; + default: + printf("adapter at unexpected slot %d\n" + "unable to map to a channel\n", + ahc_get_pci_slot(pci)); + probe_config->channel = 'A'; + } + probe_config->flags |= AHC_LARGE_SEEPROM; + return (0); +} diff --git a/sys/dev/aic7xxx/aicasm.c b/sys/dev/aic7xxx/aicasm.c deleted file mode 100644 index 374e86c79ca2..000000000000 --- a/sys/dev/aic7xxx/aicasm.c +++ /dev/null @@ -1,736 +0,0 @@ -/* - * Aic7xxx SCSI host adapter firmware asssembler - * - * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification, immediately at the beginning of the file. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ -#include <sys/types.h> -#include <sys/mman.h> - -#include <ctype.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <sysexits.h> -#include <unistd.h> - -#include "aicasm.h" -#include "aicasm_symbol.h" -#include "aicasm_insformat.h" - -typedef struct patch { - STAILQ_ENTRY(patch) links; - int patch_func; - u_int begin; - u_int skip_instr; - u_int skip_patch; -} patch_t; - -STAILQ_HEAD(patch_list, patch) patches; - -static void usage(void); -static void back_patch(void); -static void output_code(void); -static void output_listing(char *ifilename); -static void dump_scope(scope_t *scope); -static void emit_patch(scope_t *scope, int patch); -static int check_patch(patch_t **start_patch, int start_instr, - int *skip_addr, int *func_vals); - -struct path_list search_path; -int includes_search_curdir; -char *appname; -FILE *ofile; -char *ofilename; -char *regfilename; -FILE *regfile; -char *listfilename; -FILE *listfile; - -static STAILQ_HEAD(,instruction) seq_program; -struct scope_list scope_stack; -symlist_t patch_functions; - -#if DEBUG -extern int yy_flex_debug; -extern int yydebug; -#endif -extern FILE *yyin; -extern int yyparse __P((void)); - -int -main(argc, argv) - int argc; - char *argv[]; -{ - extern char *optarg; - extern int optind; - int ch; - int retval; - char *inputfilename; - scope_t *sentinal; - - STAILQ_INIT(&patches); - SLIST_INIT(&search_path); - STAILQ_INIT(&seq_program); - SLIST_INIT(&scope_stack); - - /* Set Sentinal scope node */ - sentinal = scope_alloc(); - sentinal->type = SCOPE_ROOT; - - includes_search_curdir = 1; - appname = *argv; - regfile = NULL; - listfile = NULL; -#if DEBUG - yy_flex_debug = 0; - yydebug = 0; -#endif - while ((ch = getopt(argc, argv, "d:l:n:o:r:I:O:")) != -1) { - switch(ch) { - case 'd': -#if DEBUG - if (strcmp(optarg, "s") == 0) { - yy_flex_debug = 1; - } else if (strcmp(optarg, "p") == 0) { - yydebug = 1; - } else { - fprintf(stderr, "%s: -d Requires either an " - "'s' or 'p' argument\n", appname); - usage(); - } -#else - stop("-d: Assembler not built with debugging " - "information", EX_SOFTWARE); -#endif - break; - case 'l': - /* Create a program listing */ - if ((listfile = fopen(optarg, "w")) == NULL) { - perror(optarg); - stop(NULL, EX_CANTCREAT); - } - listfilename = optarg; - break; - case 'n': - /* Don't complain about the -nostdinc directrive */ - if (strcmp(optarg, "ostdinc")) { - fprintf(stderr, "%s: Unknown option -%c%s\n", - appname, ch, optarg); - usage(); - /* NOTREACHED */ - } - break; - case 'o': - if ((ofile = fopen(optarg, "w")) == NULL) { - perror(optarg); - stop(NULL, EX_CANTCREAT); - } - ofilename = optarg; - break; - case 'r': - if ((regfile = fopen(optarg, "w")) == NULL) { - perror(optarg); - stop(NULL, EX_CANTCREAT); - } - regfilename = optarg; - break; - case 'I': - { - path_entry_t include_dir; - - if (strcmp(optarg, "-") == 0) { - if (includes_search_curdir == 0) { - fprintf(stderr, "%s: Warning - '-I-' " - "specified multiple " - "times\n", appname); - } - includes_search_curdir = 0; - for (include_dir = search_path.slh_first; - include_dir != NULL; - include_dir = include_dir->links.sle_next) - /* - * All entries before a '-I-' only - * apply to includes specified with - * quotes instead of "<>". - */ - include_dir->quoted_includes_only = 1; - } else { - include_dir = - (path_entry_t)malloc(sizeof(*include_dir)); - if (include_dir == NULL) { - perror(optarg); - stop(NULL, EX_OSERR); - } - include_dir->directory = strdup(optarg); - if (include_dir->directory == NULL) { - perror(optarg); - stop(NULL, EX_OSERR); - } - include_dir->quoted_includes_only = 0; - SLIST_INSERT_HEAD(&search_path, include_dir, - links); - } - break; - } - case '?': - default: - usage(); - /* NOTREACHED */ - } - } - argc -= optind; - argv += optind; - - if (argc != 1) { - fprintf(stderr, "%s: No input file specifiled\n", appname); - usage(); - /* NOTREACHED */ - } - - symtable_open(); - inputfilename = *argv; - include_file(*argv, SOURCE_FILE); - retval = yyparse(); - if (retval == 0) { - if (SLIST_FIRST(&scope_stack) == NULL - || SLIST_FIRST(&scope_stack)->type != SCOPE_ROOT) { - stop("Unterminated conditional expression", - EX_DATAERR); - /* NOTREACHED */ - } - - /* Process outmost scope */ - process_scope(SLIST_FIRST(&scope_stack)); - /* - * Decend the tree of scopes and insert/emit - * patches as appropriate. We perform a depth first - * tranversal, recursively handling each scope. - */ - /* start at the root scope */ - dump_scope(SLIST_FIRST(&scope_stack)); - - /* Patch up forward jump addresses */ - back_patch(); - - if (ofile != NULL) - output_code(); - if (regfile != NULL) { - symtable_dump(regfile); - } - if (listfile != NULL) - output_listing(inputfilename); - } - - stop(NULL, 0); - /* NOTREACHED */ - return (0); -} - -static void -usage() -{ - - (void)fprintf(stderr, -"usage: %-16s [-nostdinc] [-I-] [-I directory] [-o output_file] - [-r register_output_file] [-l program_list_file] - input_file\n", - appname); - exit(EX_USAGE); -} - -static void -back_patch() -{ - struct instruction *cur_instr; - - for(cur_instr = seq_program.stqh_first; - cur_instr != NULL; - cur_instr = cur_instr->links.stqe_next) { - if (cur_instr->patch_label != NULL) { - struct ins_format3 *f3_instr; - u_int address; - - if (cur_instr->patch_label->type != LABEL) { - char buf[255]; - - snprintf(buf, sizeof(buf), - "Undefined label %s", - cur_instr->patch_label->name); - stop(buf, EX_DATAERR); - /* NOTREACHED */ - } - f3_instr = &cur_instr->format.format3; - address = f3_instr->address; - address += cur_instr->patch_label->info.linfo->address; - f3_instr->address = address; - } - } -} - -static void -output_code() -{ - struct instruction *cur_instr; - patch_t *cur_patch; - symbol_node_t *cur_node; - int instrcount; - - instrcount = 0; - fprintf(ofile, -"/* - * DO NOT EDIT - This file is automatically generated. - */\n"); - - fprintf(ofile, "static uint8_t seqprog[] = {\n"); - for(cur_instr = seq_program.stqh_first; - cur_instr != NULL; - cur_instr = cur_instr->links.stqe_next) { - - fprintf(ofile, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", -#if BYTE_ORDER == LITTLE_ENDIAN - cur_instr->format.bytes[0], - cur_instr->format.bytes[1], - cur_instr->format.bytes[2], - cur_instr->format.bytes[3]); -#else - cur_instr->format.bytes[3], - cur_instr->format.bytes[2], - cur_instr->format.bytes[1], - cur_instr->format.bytes[0]); -#endif - instrcount++; - } - fprintf(ofile, "};\n\n"); - - /* - * Output patch information. Patch functions first. - */ - for(cur_node = SLIST_FIRST(&patch_functions); - cur_node != NULL; - cur_node = SLIST_NEXT(cur_node,links)) { - fprintf(ofile, -"static int ahc_patch%d_func(struct ahc_softc *ahc); - -static int -ahc_patch%d_func(struct ahc_softc *ahc) -{ - return (%s); -}\n\n", - cur_node->symbol->info.condinfo->func_num, - cur_node->symbol->info.condinfo->func_num, - cur_node->symbol->name); - } - - fprintf(ofile, -"typedef int patch_func_t __P((struct ahc_softc *)); -struct patch { - patch_func_t *patch_func; - uint32_t begin :10, - skip_instr :10, - skip_patch :12; -} patches[] = {\n"); - - for(cur_patch = STAILQ_FIRST(&patches); - cur_patch != NULL; - cur_patch = STAILQ_NEXT(cur_patch,links)) { - fprintf(ofile, "\t{ ahc_patch%d_func, %d, %d, %d },\n", - cur_patch->patch_func, cur_patch->begin, - cur_patch->skip_instr, cur_patch->skip_patch); - } - - fprintf(ofile, "\n};\n"); - - fprintf(stderr, "%s: %d instructions used\n", appname, instrcount); -} - -static void -dump_scope(scope_t *scope) -{ - scope_t *cur_scope; - - /* - * Emit the first patch for this scope - */ - emit_patch(scope, 0); - - /* - * Dump each scope within this one. - */ - cur_scope = TAILQ_FIRST(&scope->inner_scope); - - while (cur_scope != NULL) { - - dump_scope(cur_scope); - - cur_scope = TAILQ_NEXT(cur_scope, scope_links); - } - - /* - * Emit the second, closing, patch for this scope - */ - emit_patch(scope, 1); -} - -void -emit_patch(scope_t *scope, int patch) -{ - patch_info_t *pinfo; - patch_t *new_patch; - - pinfo = &scope->patches[patch]; - - if (pinfo->skip_instr == 0) - /* No-Op patch */ - return; - - new_patch = (patch_t *)malloc(sizeof(*new_patch)); - - if (new_patch == NULL) - stop("Could not malloc patch structure", EX_OSERR); - - memset(new_patch, 0, sizeof(*new_patch)); - - if (patch == 0) { - new_patch->patch_func = scope->func_num; - new_patch->begin = scope->begin_addr; - } else { - new_patch->patch_func = 0; - new_patch->begin = scope->end_addr; - } - new_patch->skip_instr = pinfo->skip_instr; - new_patch->skip_patch = pinfo->skip_patch; - STAILQ_INSERT_TAIL(&patches, new_patch, links); -} - -void -output_listing(char *ifilename) -{ - char buf[1024]; - FILE *ifile; - struct instruction *cur_instr; - patch_t *cur_patch; - symbol_node_t *cur_func; - int *func_values; - int instrcount; - int instrptr; - int line; - int func_count; - int skip_addr; - - instrcount = 0; - instrptr = 0; - line = 1; - skip_addr = 0; - if ((ifile = fopen(ifilename, "r")) == NULL) { - perror(ifilename); - stop(NULL, EX_DATAERR); - } - - /* - * Determine which options to apply to this listing. - */ - for (func_count = 0, cur_func = SLIST_FIRST(&patch_functions); - cur_func != NULL; - cur_func = SLIST_NEXT(cur_func, links)) - func_count++; - - if (func_count != 0) { - func_values = (int *)malloc(func_count * sizeof(int)); - - if (func_values == NULL) - stop("Could not malloc", EX_OSERR); - - func_values[0] = 0; /* FALSE func */ - func_count--; - - /* - * Ask the user to fill in the return values for - * the rest of the functions. - */ - - - for (cur_func = SLIST_FIRST(&patch_functions); - cur_func != NULL && SLIST_NEXT(cur_func, links) != NULL; - cur_func = SLIST_NEXT(cur_func, links), func_count--) { - int input; - - fprintf(stdout, "\n(%s)\n", cur_func->symbol->name); - fprintf(stdout, - "Enter the return value for " - "this expression[T/F]:"); - - while (1) { - - input = getchar(); - input = toupper(input); - - if (input == 'T') { - func_values[func_count] = 1; - break; - } else if (input == 'F') { - func_values[func_count] = 0; - break; - } - } - if (isatty(fileno(stdin)) == 0) - putchar(input); - } - fprintf(stdout, "\nThanks!\n"); - } - - /* Now output the listing */ - cur_patch = STAILQ_FIRST(&patches); - for(cur_instr = STAILQ_FIRST(&seq_program); - cur_instr != NULL; - cur_instr = STAILQ_NEXT(cur_instr, links), instrcount++) { - - if (check_patch(&cur_patch, instrcount, - &skip_addr, func_values) == 0) { - /* Don't count this instruction as it is in a patch - * that was removed. - */ - continue; - } - - while (line < cur_instr->srcline) { - fgets(buf, sizeof(buf), ifile); - fprintf(listfile, "\t\t%s", buf); - line++; - } - fprintf(listfile, "%03x %02x%02x%02x%02x", instrptr, -#if BYTE_ORDER == LITTLE_ENDIAN - cur_instr->format.bytes[0], - cur_instr->format.bytes[1], - cur_instr->format.bytes[2], - cur_instr->format.bytes[3]); -#else - cur_instr->format.bytes[3], - cur_instr->format.bytes[2], - cur_instr->format.bytes[1], - cur_instr->format.bytes[0]); -#endif - fgets(buf, sizeof(buf), ifile); - fprintf(listfile, "\t%s", buf); - line++; - instrptr++; - } - /* Dump the remainder of the file */ - while(fgets(buf, sizeof(buf), ifile) != NULL) - fprintf(listfile, "\t\t%s", buf); - - fclose(ifile); -} - -static int -check_patch(patch_t **start_patch, int start_instr, - int *skip_addr, int *func_vals) -{ - patch_t *cur_patch; - - cur_patch = *start_patch; - - while (cur_patch != NULL && start_instr == cur_patch->begin) { - if (func_vals[cur_patch->patch_func] == 0) { - int skip; - - /* Start rejecting code */ - *skip_addr = start_instr + cur_patch->skip_instr; - for (skip = cur_patch->skip_patch; - skip > 0 && cur_patch != NULL; - skip--) - cur_patch = STAILQ_NEXT(cur_patch, links); - } else { - /* Accepted this patch. Advance to the next - * one and wait for our intruction pointer to - * hit this point. - */ - cur_patch = STAILQ_NEXT(cur_patch, links); - } - } - - *start_patch = cur_patch; - if (start_instr < *skip_addr) - /* Still skipping */ - return (0); - - return (1); -} - -/* - * Print out error information if appropriate, and clean up before - * terminating the program. - */ -void -stop(string, err_code) - const char *string; - int err_code; -{ - if (string != NULL) { - fprintf(stderr, "%s: ", appname); - if (yyfilename != NULL) { - fprintf(stderr, "Stopped at file %s, line %d - ", - yyfilename, yylineno); - } - fprintf(stderr, "%s\n", string); - } - - if (ofile != NULL) { - fclose(ofile); - if (err_code != 0) { - fprintf(stderr, "%s: Removing %s due to error\n", - appname, ofilename); - unlink(ofilename); - } - } - - if (regfile != NULL) { - fclose(regfile); - if (err_code != 0) { - fprintf(stderr, "%s: Removing %s due to error\n", - appname, regfilename); - unlink(regfilename); - } - } - - if (listfile != NULL) { - fclose(listfile); - if (err_code != 0) { - fprintf(stderr, "%s: Removing %s due to error\n", - appname, listfilename); - unlink(listfilename); - } - } - - symlist_free(&patch_functions); - symtable_close(); - - exit(err_code); -} - -struct instruction * -seq_alloc() -{ - struct instruction *new_instr; - - new_instr = (struct instruction *)malloc(sizeof(struct instruction)); - if (new_instr == NULL) - stop("Unable to malloc instruction object", EX_SOFTWARE); - memset(new_instr, 0, sizeof(*new_instr)); - STAILQ_INSERT_TAIL(&seq_program, new_instr, links); - new_instr->srcline = yylineno; - return new_instr; -} - -scope_t * -scope_alloc() -{ - scope_t *new_scope; - - new_scope = (scope_t *)malloc(sizeof(scope_t)); - if (new_scope == NULL) - stop("Unable to malloc scope object", EX_SOFTWARE); - memset(new_scope, 0, sizeof(*new_scope)); - TAILQ_INIT(&new_scope->inner_scope); - - if (SLIST_FIRST(&scope_stack) != NULL) { - TAILQ_INSERT_TAIL(&SLIST_FIRST(&scope_stack)->inner_scope, - new_scope, scope_links); - } - /* This patch is now the current scope */ - SLIST_INSERT_HEAD(&scope_stack, new_scope, scope_stack_links); - return new_scope; -} - -void -process_scope(scope_t *scope) -{ - /* - * We are "leaving" this scope. We should now have - * enough information to process the lists of scopes - * we encapsulate. - */ - scope_t *cur_scope; - u_int skip_patch_count; - u_int skip_instr_count; - - cur_scope = TAILQ_LAST(&scope->inner_scope, scope_tailq); - skip_patch_count = 0; - skip_instr_count = 0; - while (cur_scope != NULL) { - u_int patch0_patch_skip; - - patch0_patch_skip = 0; - switch (cur_scope->type) { - case SCOPE_IF: - case SCOPE_ELSE_IF: - if (skip_instr_count != 0) { - /* Create a tail patch */ - patch0_patch_skip++; - cur_scope->patches[1].skip_patch = - skip_patch_count + 1; - cur_scope->patches[1].skip_instr = - skip_instr_count; - } - - /* Count Head patch */ - patch0_patch_skip++; - - /* Count any patches contained in our inner scope */ - patch0_patch_skip += cur_scope->inner_scope_patches; - - cur_scope->patches[0].skip_patch = patch0_patch_skip; - cur_scope->patches[0].skip_instr = - cur_scope->end_addr - cur_scope->begin_addr; - - skip_instr_count += cur_scope->patches[0].skip_instr; - - skip_patch_count += patch0_patch_skip; - if (cur_scope->type == SCOPE_IF) { - scope->inner_scope_patches += skip_patch_count; - skip_patch_count = 0; - skip_instr_count = 0; - } - break; - case SCOPE_ELSE: - /* Count any patches contained in our innter scope */ - skip_patch_count += cur_scope->inner_scope_patches; - - skip_instr_count += cur_scope->end_addr - - cur_scope->begin_addr; - break; - case SCOPE_ROOT: - stop("Unexpected scope type encountered", EX_SOFTWARE); - /* NOTREACHED */ - } - - cur_scope = TAILQ_PREV(cur_scope, scope_tailq, scope_links); - } -} diff --git a/sys/dev/aic7xxx/aicasm.h b/sys/dev/aic7xxx/aicasm.h deleted file mode 100644 index 9faecd0f4f02..000000000000 --- a/sys/dev/aic7xxx/aicasm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Assembler for the sequencer program downloaded to Aic7xxx SCSI host adapters - * - * Copyright (c) 1997 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include <sys/queue.h> - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -typedef struct path_entry { - char *directory; - int quoted_includes_only; - SLIST_ENTRY(path_entry) links; -} *path_entry_t; - -typedef enum { - QUOTED_INCLUDE, - BRACKETED_INCLUDE, - SOURCE_FILE -} include_type; - -SLIST_HEAD(path_list, path_entry); - -extern struct path_list search_path; -extern struct scope_list scope_stack; -extern struct symlist patch_functions; -extern int includes_search_curdir; /* False if we've seen -I- */ -extern char *appname; -extern int yylineno; -extern char *yyfilename; - -void stop(const char *errstring, int err_code); -void include_file(char *file_name, include_type type); -struct instruction *seq_alloc(void); -struct scope *scope_alloc(void); -void process_scope(struct scope *); diff --git a/sys/dev/aic7xxx/aicasm_gram.y b/sys/dev/aic7xxx/aicasm_gram.y deleted file mode 100644 index 5731f674bcdf..000000000000 --- a/sys/dev/aic7xxx/aicasm_gram.y +++ /dev/null @@ -1,1438 +0,0 @@ -%{ -/* - * Parser for the Aic7xxx SCSI Host adapter sequencer assembler. - * - * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <sysexits.h> - -#include <sys/types.h> -#include <sys/queue.h> - -#include "aicasm.h" -#include "aicasm_symbol.h" -#include "aicasm_insformat.h" - -int yylineno; -char *yyfilename; -static symbol_t *cur_symbol; -static symtype cur_symtype; -static symbol_t *accumulator; -static symbol_ref_t allones; -static symbol_ref_t allzeros; -static symbol_ref_t none; -static symbol_ref_t sindex; -static int instruction_ptr; -static int sram_or_scb_offset; -static int download_constant_count; - -static void process_bitmask __P((int mask_type, symbol_t *sym, int mask)); -static void initialize_symbol __P((symbol_t *symbol)); -static void process_register __P((symbol_t **p_symbol)); -static void format_1_instr __P((int opcode, symbol_ref_t *dest, - expression_t *immed, symbol_ref_t *src, - int ret)); -static void format_2_instr __P((int opcode, symbol_ref_t *dest, - expression_t *places, symbol_ref_t *src, - int ret)); -static void format_3_instr __P((int opcode, symbol_ref_t *src, - expression_t *immed, symbol_ref_t *address)); -static void test_readable_symbol __P((symbol_t *symbol)); -static void test_writable_symbol __P((symbol_t *symbol)); -static void type_check __P((symbol_t *symbol, expression_t *expression, - int and_op)); -static void make_expression __P((expression_t *immed, int value)); -static void add_conditional __P((symbol_t *symbol)); -static int is_download_const __P((expression_t *immed)); - -#define YYDEBUG 1 -#define SRAM_SYMNAME "SRAM_BASE" -#define SCB_SYMNAME "SCB_BASE" -%} - -%union { - int value; - char *str; - symbol_t *sym; - symbol_ref_t sym_ref; - expression_t expression; -} - -%token T_REGISTER - -%token <value> T_CONST - -%token T_DOWNLOAD - -%token T_SCB - -%token T_SRAM - -%token T_ALIAS - -%token T_SIZE - -%token <value> T_ADDRESS - -%token T_ACCESS_MODE - -%token <value> T_MODE - -%token T_BIT - -%token T_MASK - -%token <value> T_NUMBER - -%token <str> T_PATH - -%token <sym> T_CEXPR - -%token T_EOF T_INCLUDE - -%token <value> T_SHR T_SHL T_ROR T_ROL - -%token <value> T_MVI T_MOV T_CLR T_BMOV - -%token <value> T_JMP T_JC T_JNC T_JE T_JNE T_JNZ T_JZ T_CALL - -%token <value> T_ADD T_ADC - -%token <value> T_INC T_DEC - -%token <value> T_STC T_CLC - -%token <value> T_CMP T_NOT T_XOR - -%token <value> T_TEST T_AND - -%token <value> T_OR - -%token T_RET - -%token T_NOP - -%token T_ACCUM T_ALLONES T_ALLZEROS T_NONE T_SINDEX - -%token T_A - -%token <sym> T_SYMBOL - -%token T_NL - -%token T_IF T_ELSE T_ELSE_IF T_ENDIF - -%type <sym_ref> reg_symbol address destination source opt_source - -%type <expression> expression immediate immediate_or_a - -%type <value> ret f1_opcode f2_opcode jmp_jc_jnc_call jz_jnz je_jne - -%type <value> numerical_value - -%left '|' -%left '&' -%left '+' '-' -%right '~' -%nonassoc UMINUS -%% - -program: - include -| program include -| register -| program register -| constant -| program constant -| scratch_ram -| program scratch_ram -| scb -| program scb -| label -| program label -| conditional -| program conditional -| code -| program code -; - -include: - T_INCLUDE '<' T_PATH '>' - { include_file($3, BRACKETED_INCLUDE); } -| T_INCLUDE '"' T_PATH '"' - { include_file($3, QUOTED_INCLUDE); } -; - -register: - T_REGISTER { cur_symtype = REGISTER; } reg_definition -; - -reg_definition: - T_SYMBOL '{' - { - if ($1->type != UNINITIALIZED) { - stop("Register multiply defined", EX_DATAERR); - /* NOTREACHED */ - } - cur_symbol = $1; - cur_symbol->type = cur_symtype; - initialize_symbol(cur_symbol); - } - reg_attribute_list - '}' - { - /* - * Default to allowing everything in for registers - * with no bit or mask definitions. - */ - if (cur_symbol->info.rinfo->valid_bitmask == 0) - cur_symbol->info.rinfo->valid_bitmask = 0xFF; - - if (cur_symbol->info.rinfo->size == 0) - cur_symbol->info.rinfo->size = 1; - - /* - * This might be useful for registers too. - */ - if (cur_symbol->type != REGISTER) { - if (cur_symbol->info.rinfo->address == 0) - cur_symbol->info.rinfo->address = - sram_or_scb_offset; - sram_or_scb_offset += - cur_symbol->info.rinfo->size; - } - cur_symbol = NULL; - } -; - -reg_attribute_list: - reg_attribute -| reg_attribute_list reg_attribute -; - -reg_attribute: - reg_address -| size -| access_mode -| bit_defn -| mask_defn -| alias -| accumulator -| allones -| allzeros -| none -| sindex -; - -reg_address: - T_ADDRESS T_NUMBER - { - cur_symbol->info.rinfo->address = $2; - } -; - -size: - T_SIZE T_NUMBER - { - cur_symbol->info.rinfo->size = $2; - } -; - -access_mode: - T_ACCESS_MODE T_MODE - { - cur_symbol->info.rinfo->mode = $2; - } -; - -bit_defn: - T_BIT T_SYMBOL T_NUMBER - { - process_bitmask(BIT, $2, $3); - } -; - -mask_defn: - T_MASK T_SYMBOL expression - { - process_bitmask(MASK, $2, $3.value); - } -; - -alias: - T_ALIAS T_SYMBOL - { - if ($2->type != UNINITIALIZED) { - stop("Re-definition of register alias", - EX_DATAERR); - /* NOTREACHED */ - } - $2->type = ALIAS; - initialize_symbol($2); - $2->info.ainfo->parent = cur_symbol; - } -; - -accumulator: - T_ACCUM - { - if (accumulator != NULL) { - stop("Only one accumulator definition allowed", - EX_DATAERR); - /* NOTREACHED */ - } - accumulator = cur_symbol; - } -; - -allones: - T_ALLONES - { - if (allones.symbol != NULL) { - stop("Only one definition of allones allowed", - EX_DATAERR); - /* NOTREACHED */ - } - allones.symbol = cur_symbol; - } -; - -allzeros: - T_ALLZEROS - { - if (allzeros.symbol != NULL) { - stop("Only one definition of allzeros allowed", - EX_DATAERR); - /* NOTREACHED */ - } - allzeros.symbol = cur_symbol; - } -; - -none: - T_NONE - { - if (none.symbol != NULL) { - stop("Only one definition of none allowed", - EX_DATAERR); - /* NOTREACHED */ - } - none.symbol = cur_symbol; - } -; - -sindex: - T_SINDEX - { - if (sindex.symbol != NULL) { - stop("Only one definition of sindex allowed", - EX_DATAERR); - /* NOTREACHED */ - } - sindex.symbol = cur_symbol; - } -; - -expression: - expression '|' expression - { - $$.value = $1.value | $3.value; - symlist_merge(&$$.referenced_syms, - &$1.referenced_syms, - &$3.referenced_syms); - } -| expression '&' expression - { - $$.value = $1.value & $3.value; - symlist_merge(&$$.referenced_syms, - &$1.referenced_syms, - &$3.referenced_syms); - } -| expression '+' expression - { - $$.value = $1.value + $3.value; - symlist_merge(&$$.referenced_syms, - &$1.referenced_syms, - &$3.referenced_syms); - } -| expression '-' expression - { - $$.value = $1.value - $3.value; - symlist_merge(&($$.referenced_syms), - &($1.referenced_syms), - &($3.referenced_syms)); - } -| '(' expression ')' - { - $$ = $2; - } -| '~' expression - { - $$ = $2; - $$.value = (~$$.value) & 0xFF; - } -| '-' expression %prec UMINUS - { - $$ = $2; - $$.value = -$$.value; - } -| T_NUMBER - { - $$.value = $1; - SLIST_INIT(&$$.referenced_syms); - } -| T_SYMBOL - { - symbol_t *symbol; - - symbol = $1; - switch (symbol->type) { - case ALIAS: - symbol = $1->info.ainfo->parent; - case REGISTER: - case SCBLOC: - case SRAMLOC: - $$.value = symbol->info.rinfo->address; - break; - case MASK: - case BIT: - $$.value = symbol->info.minfo->mask; - break; - case DOWNLOAD_CONST: - case CONST: - $$.value = symbol->info.cinfo->value; - break; - case UNINITIALIZED: - default: - { - char buf[255]; - - snprintf(buf, sizeof(buf), - "Undefined symbol %s referenced", - symbol->name); - stop(buf, EX_DATAERR); - /* NOTREACHED */ - break; - } - } - SLIST_INIT(&$$.referenced_syms); - symlist_add(&$$.referenced_syms, symbol, SYMLIST_INSERT_HEAD); - } -; - -constant: - T_CONST T_SYMBOL numerical_value - { - if ($2->type != UNINITIALIZED) { - stop("Re-definition of symbol as a constant", - EX_DATAERR); - /* NOTREACHED */ - } - $2->type = CONST; - initialize_symbol($2); - $2->info.cinfo->value = $3; - $2->info.cinfo->define = $1; - } -| T_CONST T_SYMBOL T_DOWNLOAD - { - if ($1) { - stop("Invalid downloaded constant declaration", - EX_DATAERR); - /* NOTREACHED */ - } - if ($2->type != UNINITIALIZED) { - stop("Re-definition of symbol as a downloaded constant", - EX_DATAERR); - /* NOTREACHED */ - } - $2->type = DOWNLOAD_CONST; - initialize_symbol($2); - $2->info.cinfo->value = download_constant_count++; - $2->info.cinfo->define = FALSE; - } -; - -numerical_value: - T_NUMBER - { - $$ = $1; - } -| '-' T_NUMBER - { - $$ = -$2; - } -; - -scratch_ram: - T_SRAM '{' - { - cur_symbol = symtable_get(SRAM_SYMNAME); - cur_symtype = SRAMLOC; - if (cur_symbol->type != UNINITIALIZED) { - stop("Only one SRAM definition allowed", - EX_DATAERR); - /* NOTREACHED */ - } - cur_symbol->type = SRAMLOC; - initialize_symbol(cur_symbol); - } - reg_address - { - sram_or_scb_offset = cur_symbol->info.rinfo->address; - } - scb_or_sram_reg_list - '}' - { - cur_symbol = NULL; - } -; - -scb: - T_SCB '{' - { - cur_symbol = symtable_get(SCB_SYMNAME); - cur_symtype = SCBLOC; - if (cur_symbol->type != UNINITIALIZED) { - stop("Only one SRAM definition allowed", - EX_SOFTWARE); - /* NOTREACHED */ - } - cur_symbol->type = SCBLOC; - initialize_symbol(cur_symbol); - } - reg_address - { - sram_or_scb_offset = cur_symbol->info.rinfo->address; - } - scb_or_sram_reg_list - '}' - { - cur_symbol = NULL; - } -; - -scb_or_sram_reg_list: - reg_definition -| scb_or_sram_reg_list reg_definition -; - -reg_symbol: - T_SYMBOL - { - process_register(&$1); - $$.symbol = $1; - $$.offset = 0; - } -| T_SYMBOL '[' T_SYMBOL ']' - { - process_register(&$1); - if ($3->type != CONST) { - stop("register offset must be a constant", EX_DATAERR); - /* NOTREACHED */ - } - if (($3->info.cinfo->value + 1) > $1->info.rinfo->size) { - stop("Accessing offset beyond range of register", - EX_DATAERR); - /* NOTREACHED */ - } - $$.symbol = $1; - $$.offset = $3->info.cinfo->value; - } -| T_SYMBOL '[' T_NUMBER ']' - { - process_register(&$1); - if (($3 + 1) > $1->info.rinfo->size) { - stop("Accessing offset beyond range of register", - EX_DATAERR); - /* NOTREACHED */ - } - $$.symbol = $1; - $$.offset = $3; - } -| T_A - { - if (accumulator == NULL) { - stop("No accumulator has been defined", EX_DATAERR); - /* NOTREACHED */ - } - $$.symbol = accumulator; - $$.offset = 0; - } -; - -destination: - reg_symbol - { - test_writable_symbol($1.symbol); - $$ = $1; - } -; - -immediate: - expression - { $$ = $1; } -; - -immediate_or_a: - expression - { - $$ = $1; - } -| T_A - { - SLIST_INIT(&$$.referenced_syms); - $$.value = 0; - } -; - -source: - reg_symbol - { - test_readable_symbol($1.symbol); - $$ = $1; - } -; - -opt_source: - { - $$.symbol = NULL; - $$.offset = 0; - } -| ',' source - { $$ = $2; } -; - -ret: - { $$ = 0; } -| T_RET - { $$ = 1; } -; - -label: - T_SYMBOL ':' - { - if ($1->type != UNINITIALIZED) { - stop("Program label multiply defined", EX_DATAERR); - /* NOTREACHED */ - } - $1->type = LABEL; - initialize_symbol($1); - $1->info.linfo->address = instruction_ptr; - } -; - -address: - T_SYMBOL - { - $$.symbol = $1; - $$.offset = 0; - } -| T_SYMBOL '+' T_NUMBER - { - $$.symbol = $1; - $$.offset = $3; - } -| T_SYMBOL '-' T_NUMBER - { - $$.symbol = $1; - $$.offset = -$3; - } -| '.' - { - $$.symbol = NULL; - $$.offset = 0; - } -| '.' '+' T_NUMBER - { - $$.symbol = NULL; - $$.offset = $3; - } -| '.' '-' T_NUMBER - { - $$.symbol = NULL; - $$.offset = -$3; - } -; - -conditional: - T_IF T_CEXPR '{' - { - scope_t *new_scope; - - add_conditional($2); - new_scope = scope_alloc(); - new_scope->type = SCOPE_IF; - new_scope->begin_addr = instruction_ptr; - new_scope->func_num = $2->info.condinfo->func_num; - } -| T_ELSE T_IF T_CEXPR '{' - { - scope_t *new_scope; - scope_t *scope_context; - scope_t *last_scope; - - /* - * Ensure that the previous scope is either an - * if or and else if. - */ - scope_context = SLIST_FIRST(&scope_stack); - last_scope = TAILQ_LAST(&scope_context->inner_scope, - scope_tailq); - if (last_scope == NULL - || last_scope->type == T_ELSE) { - - stop("'else if' without leading 'if'", EX_DATAERR); - /* NOTREACHED */ - } - add_conditional($3); - new_scope = scope_alloc(); - new_scope->type = SCOPE_ELSE_IF; - new_scope->begin_addr = instruction_ptr; - new_scope->func_num = $3->info.condinfo->func_num; - } -| T_ELSE '{' - { - scope_t *new_scope; - scope_t *scope_context; - scope_t *last_scope; - - /* - * Ensure that the previous scope is either an - * if or and else if. - */ - scope_context = SLIST_FIRST(&scope_stack); - last_scope = TAILQ_LAST(&scope_context->inner_scope, - scope_tailq); - if (last_scope == NULL - || last_scope->type == SCOPE_ELSE) { - - stop("'else' without leading 'if'", EX_DATAERR); - /* NOTREACHED */ - } - new_scope = scope_alloc(); - new_scope->type = SCOPE_ELSE; - new_scope->begin_addr = instruction_ptr; - } -; - -conditional: - '}' - { - scope_t *scope_context; - scope_t *last_scope; - - scope_context = SLIST_FIRST(&scope_stack); - if (scope_context->type == SCOPE_ROOT) { - stop("Unexpected '}' encountered", EX_DATAERR); - /* NOTREACHED */ - } - - scope_context->end_addr = instruction_ptr; - - /* Pop the scope */ - SLIST_REMOVE_HEAD(&scope_stack, scope_stack_links); - - process_scope(scope_context); - - if (SLIST_FIRST(&scope_stack) == NULL) { - stop("Unexpected '}' encountered", EX_DATAERR); - /* NOTREACHED */ - } - } -; - -f1_opcode: - T_AND { $$ = AIC_OP_AND; } -| T_XOR { $$ = AIC_OP_XOR; } -| T_ADD { $$ = AIC_OP_ADD; } -| T_ADC { $$ = AIC_OP_ADC; } -; - -code: - f1_opcode destination ',' immediate_or_a opt_source ret ';' - { - format_1_instr($1, &$2, &$4, &$5, $6); - } -; - -code: - T_OR reg_symbol ',' immediate_or_a opt_source ret ';' - { - format_1_instr(AIC_OP_OR, &$2, &$4, &$5, $6); - } -; - -code: - T_INC destination opt_source ret ';' - { - expression_t immed; - - make_expression(&immed, 1); - format_1_instr(AIC_OP_ADD, &$2, &immed, &$3, $4); - } -; - -code: - T_DEC destination opt_source ret ';' - { - expression_t immed; - - make_expression(&immed, -1); - format_1_instr(AIC_OP_ADD, &$2, &immed, &$3, $4); - } -; - -code: - T_CLC ret ';' - { - expression_t immed; - - make_expression(&immed, -1); - format_1_instr(AIC_OP_ADD, &none, &immed, &allzeros, $2); - } -| T_CLC T_MVI destination ',' immediate_or_a ret ';' - { - format_1_instr(AIC_OP_ADD, &$3, &$5, &allzeros, $6); - } -; - -code: - T_STC ret ';' - { - expression_t immed; - - make_expression(&immed, 1); - format_1_instr(AIC_OP_ADD, &none, &immed, &allones, $2); - } -| T_STC destination ret ';' - { - expression_t immed; - - make_expression(&immed, 1); - format_1_instr(AIC_OP_ADD, &$2, &immed, &allones, $3); - } -; - -code: - T_BMOV destination ',' source ',' immediate_or_a ret ';' - { - format_1_instr(AIC_OP_BMOV, &$2, &$6, &$4, $7); - } -; - -code: - T_MOV destination ',' source ret ';' - { - expression_t immed; - - make_expression(&immed, 0xff); - format_1_instr(AIC_OP_AND, &$2, &immed, &$4, $5); - } -; - -code: - T_MVI destination ',' immediate_or_a ret ';' - { - format_1_instr(AIC_OP_OR, &$2, &$4, &allzeros, $5); - } -; - -code: - T_NOT destination opt_source ret ';' - { - expression_t immed; - - make_expression(&immed, 0xff); - format_1_instr(AIC_OP_XOR, &$2, &immed, &$3, $4); - } -; - -code: - T_CLR destination ret ';' - { - expression_t immed; - - make_expression(&immed, 0xff); - format_1_instr(AIC_OP_AND, &$2, &immed, &allzeros, $3); - } -; - -code: - T_NOP ret ';' - { - expression_t immed; - - make_expression(&immed, 0xff); - format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, $2); - } -; - -code: - T_RET ';' - { - expression_t immed; - - make_expression(&immed, 0xff); - format_1_instr(AIC_OP_AND, &none, &immed, &allzeros, TRUE); - } -; - - /* - * This grammer differs from the one in the aic7xxx - * reference manual since the grammer listed there is - * ambiguous and causes a shift/reduce conflict. - * It also seems more logical as the "immediate" - * argument is listed as the second arg like the - * other formats. - */ - -f2_opcode: - T_SHL { $$ = AIC_OP_SHL; } -| T_SHR { $$ = AIC_OP_SHR; } -| T_ROL { $$ = AIC_OP_ROL; } -| T_ROR { $$ = AIC_OP_ROR; } -; - -code: - f2_opcode destination ',' expression opt_source ret ';' - { - format_2_instr($1, &$2, &$4, &$5, $6); - } -; - -jmp_jc_jnc_call: - T_JMP { $$ = AIC_OP_JMP; } -| T_JC { $$ = AIC_OP_JC; } -| T_JNC { $$ = AIC_OP_JNC; } -| T_CALL { $$ = AIC_OP_CALL; } -; - -jz_jnz: - T_JZ { $$ = AIC_OP_JZ; } -| T_JNZ { $$ = AIC_OP_JNZ; } -; - -je_jne: - T_JE { $$ = AIC_OP_JE; } -| T_JNE { $$ = AIC_OP_JNE; } -; - -code: - jmp_jc_jnc_call address ';' - { - expression_t immed; - - make_expression(&immed, 0); - format_3_instr($1, &sindex, &immed, &$2); - } -; - -code: - T_OR reg_symbol ',' immediate jmp_jc_jnc_call address ';' - { - format_3_instr($5, &$2, &$4, &$6); - } -; - -code: - T_TEST source ',' immediate_or_a jz_jnz address ';' - { - format_3_instr($5, &$2, &$4, &$6); - } -; - -code: - T_CMP source ',' immediate_or_a je_jne address ';' - { - format_3_instr($5, &$2, &$4, &$6); - } -; - -code: - T_MOV source jmp_jc_jnc_call address ';' - { - expression_t immed; - - make_expression(&immed, 0); - format_3_instr($3, &$2, &immed, &$4); - } -; - -code: - T_MVI immediate jmp_jc_jnc_call address ';' - { - format_3_instr($3, &allzeros, &$2, &$4); - } -; - -%% - -static void -process_bitmask(mask_type, sym, mask) - int mask_type; - symbol_t *sym; - int mask; -{ - /* - * Add the current register to its - * symbol list, if it already exists, - * warn if we are setting it to a - * different value, or in the bit to - * the "allowed bits" of this register. - */ - if (sym->type == UNINITIALIZED) { - sym->type = mask_type; - initialize_symbol(sym); - if (mask_type == BIT) { - if (mask == 0) { - stop("Bitmask with no bits set", EX_DATAERR); - /* NOTREACHED */ - } - if ((mask & ~(0x01 << (ffs(mask) - 1))) != 0) { - stop("Bitmask with more than one bit set", - EX_DATAERR); - /* NOTREACHED */ - } - } - sym->info.minfo->mask = mask; - } else if (sym->type != mask_type) { - stop("Bit definition mirrors a definition of the same " - " name, but a different type", EX_DATAERR); - /* NOTREACHED */ - } else if (mask != sym->info.minfo->mask) { - stop("Bitmask redefined with a conflicting value", EX_DATAERR); - /* NOTREACHED */ - } - /* Fail if this symbol is already listed */ - if (symlist_search(&(sym->info.minfo->symrefs), - cur_symbol->name) != NULL) { - stop("Bitmask defined multiple times for register", EX_DATAERR); - /* NOTREACHED */ - } - symlist_add(&(sym->info.minfo->symrefs), cur_symbol, - SYMLIST_INSERT_HEAD); - cur_symbol->info.rinfo->valid_bitmask |= mask; - cur_symbol->info.rinfo->typecheck_masks = TRUE; -} - -static void -initialize_symbol(symbol) - symbol_t *symbol; -{ - switch (symbol->type) { - case UNINITIALIZED: - stop("Call to initialize_symbol with type field unset", - EX_SOFTWARE); - /* NOTREACHED */ - break; - case REGISTER: - case SRAMLOC: - case SCBLOC: - symbol->info.rinfo = - (struct reg_info *)malloc(sizeof(struct reg_info)); - if (symbol->info.rinfo == NULL) { - stop("Can't create register info", EX_SOFTWARE); - /* NOTREACHED */ - } - memset(symbol->info.rinfo, 0, - sizeof(struct reg_info)); - break; - case ALIAS: - symbol->info.ainfo = - (struct alias_info *)malloc(sizeof(struct alias_info)); - if (symbol->info.ainfo == NULL) { - stop("Can't create alias info", EX_SOFTWARE); - /* NOTREACHED */ - } - memset(symbol->info.ainfo, 0, - sizeof(struct alias_info)); - break; - case MASK: - case BIT: - symbol->info.minfo = - (struct mask_info *)malloc(sizeof(struct mask_info)); - if (symbol->info.minfo == NULL) { - stop("Can't create bitmask info", EX_SOFTWARE); - /* NOTREACHED */ - } - memset(symbol->info.minfo, 0, sizeof(struct mask_info)); - SLIST_INIT(&(symbol->info.minfo->symrefs)); - break; - case CONST: - case DOWNLOAD_CONST: - symbol->info.cinfo = - (struct const_info *)malloc(sizeof(struct const_info)); - if (symbol->info.cinfo == NULL) { - stop("Can't create alias info", EX_SOFTWARE); - /* NOTREACHED */ - } - memset(symbol->info.cinfo, 0, - sizeof(struct const_info)); - break; - case LABEL: - symbol->info.linfo = - (struct label_info *)malloc(sizeof(struct label_info)); - if (symbol->info.linfo == NULL) { - stop("Can't create label info", EX_SOFTWARE); - /* NOTREACHED */ - } - memset(symbol->info.linfo, 0, - sizeof(struct label_info)); - break; - case CONDITIONAL: - symbol->info.condinfo = - (struct cond_info *)malloc(sizeof(struct cond_info)); - if (symbol->info.condinfo == NULL) { - stop("Can't create conditional info", EX_SOFTWARE); - /* NOTREACHED */ - } - memset(symbol->info.condinfo, 0, - sizeof(struct cond_info)); - break; - default: - stop("Call to initialize_symbol with invalid symbol type", - EX_SOFTWARE); - /* NOTREACHED */ - break; - } -} - -static void -process_register(p_symbol) - symbol_t **p_symbol; -{ - char buf[255]; - symbol_t *symbol = *p_symbol; - - if (symbol->type == UNINITIALIZED) { - snprintf(buf, sizeof(buf), "Undefined register %s", - symbol->name); - stop(buf, EX_DATAERR); - /* NOTREACHED */ - } else if (symbol->type == ALIAS) { - *p_symbol = symbol->info.ainfo->parent; - } else if ((symbol->type != REGISTER) - && (symbol->type != SCBLOC) - && (symbol->type != SRAMLOC)) { - snprintf(buf, sizeof(buf), - "Specified symbol %s is not a register", - symbol->name); - stop(buf, EX_DATAERR); - } -} - -static void -format_1_instr(opcode, dest, immed, src, ret) - int opcode; - symbol_ref_t *dest; - expression_t *immed; - symbol_ref_t *src; - int ret; -{ - struct instruction *instr; - struct ins_format1 *f1_instr; - - if (src->symbol == NULL) - src = dest; - - /* Test register permissions */ - test_writable_symbol(dest->symbol); - test_readable_symbol(src->symbol); - - /* Ensure that immediate makes sense for this destination */ - type_check(dest->symbol, immed, opcode); - - /* Allocate sequencer space for the instruction and fill it out */ - instr = seq_alloc(); - f1_instr = &instr->format.format1; - f1_instr->ret = ret ? 1 : 0; - f1_instr->opcode = opcode; - f1_instr->destination = dest->symbol->info.rinfo->address - + dest->offset; - f1_instr->source = src->symbol->info.rinfo->address - + src->offset; - f1_instr->immediate = immed->value; - - if (is_download_const(immed)) - f1_instr->parity = 1; - - symlist_free(&immed->referenced_syms); - instruction_ptr++; -} - -static void -format_2_instr(opcode, dest, places, src, ret) - int opcode; - symbol_ref_t *dest; - expression_t *places; - symbol_ref_t *src; - int ret; -{ - struct instruction *instr; - struct ins_format2 *f2_instr; - uint8_t shift_control; - - if (src->symbol == NULL) - src = dest; - - /* Test register permissions */ - test_writable_symbol(dest->symbol); - test_readable_symbol(src->symbol); - - /* Allocate sequencer space for the instruction and fill it out */ - instr = seq_alloc(); - f2_instr = &instr->format.format2; - f2_instr->ret = ret ? 1 : 0; - f2_instr->opcode = AIC_OP_ROL; - f2_instr->destination = dest->symbol->info.rinfo->address - + dest->offset; - f2_instr->source = src->symbol->info.rinfo->address - + src->offset; - if (places->value > 8 || places->value <= 0) { - stop("illegal shift value", EX_DATAERR); - /* NOTREACHED */ - } - switch (opcode) { - case AIC_OP_SHL: - if (places->value == 8) - shift_control = 0xf0; - else - shift_control = (places->value << 4) | places->value; - break; - case AIC_OP_SHR: - if (places->value == 8) { - shift_control = 0xf8; - } else { - shift_control = (places->value << 4) - | (8 - places->value) - | 0x08; - } - break; - case AIC_OP_ROL: - shift_control = places->value & 0x7; - break; - case AIC_OP_ROR: - shift_control = (8 - places->value) | 0x08; - break; - default: - shift_control = 0; /* Quiet Compiler */ - stop("Invalid shift operation specified", EX_SOFTWARE); - /* NOTREACHED */ - break; - }; - f2_instr->shift_control = shift_control; - symlist_free(&places->referenced_syms); - instruction_ptr++; -} - -static void -format_3_instr(opcode, src, immed, address) - int opcode; - symbol_ref_t *src; - expression_t *immed; - symbol_ref_t *address; -{ - struct instruction *instr; - struct ins_format3 *f3_instr; - int addr; - - /* Test register permissions */ - test_readable_symbol(src->symbol); - - /* Ensure that immediate makes sense for this source */ - type_check(src->symbol, immed, opcode); - - /* Allocate sequencer space for the instruction and fill it out */ - instr = seq_alloc(); - f3_instr = &instr->format.format3; - if (address->symbol == NULL) { - /* 'dot' referrence. Use the current instruction pointer */ - addr = instruction_ptr + address->offset; - } else if (address->symbol->type == UNINITIALIZED) { - /* forward reference */ - addr = address->offset; - instr->patch_label = address->symbol; - } else - addr = address->symbol->info.linfo->address + address->offset; - f3_instr->opcode = opcode; - f3_instr->address = addr; - f3_instr->source = src->symbol->info.rinfo->address - + src->offset; - f3_instr->immediate = immed->value; - - if (is_download_const(immed)) - f3_instr->parity = 1; - - symlist_free(&immed->referenced_syms); - instruction_ptr++; -} - -static void -test_readable_symbol(symbol) - symbol_t *symbol; -{ - if (symbol->info.rinfo->mode == WO) { - stop("Write Only register specified as source", - EX_DATAERR); - /* NOTREACHED */ - } -} - -static void -test_writable_symbol(symbol) - symbol_t *symbol; -{ - if (symbol->info.rinfo->mode == RO) { - stop("Read Only register specified as destination", - EX_DATAERR); - /* NOTREACHED */ - } -} - -static void -type_check(symbol, expression, opcode) - symbol_t *symbol; - expression_t *expression; - int opcode; -{ - symbol_node_t *node; - int and_op; - char buf[255]; - - and_op = FALSE; - if (opcode == AIC_OP_AND || opcode == AIC_OP_JNZ || AIC_OP_JZ) - and_op = TRUE; - - /* - * Make sure that we aren't attempting to write something - * that hasn't been defined. If this is an and operation, - * this is a mask, so "undefined" bits are okay. - */ - if (and_op == FALSE - && (expression->value & ~symbol->info.rinfo->valid_bitmask) != 0) { - snprintf(buf, sizeof(buf), - "Invalid bit(s) 0x%x in immediate written to %s", - expression->value & ~symbol->info.rinfo->valid_bitmask, - symbol->name); - stop(buf, EX_DATAERR); - /* NOTREACHED */ - } - - /* - * Now make sure that all of the symbols referenced by the - * expression are defined for this register. - */ - if(symbol->info.rinfo->typecheck_masks != FALSE) { - for(node = expression->referenced_syms.slh_first; - node != NULL; - node = node->links.sle_next) { - if ((node->symbol->type == MASK - || node->symbol->type == BIT) - && symlist_search(&node->symbol->info.minfo->symrefs, - symbol->name) == NULL) { - snprintf(buf, sizeof(buf), - "Invalid bit or mask %s " - "for register %s", - node->symbol->name, symbol->name); - stop(buf, EX_DATAERR); - /* NOTREACHED */ - } - } - } -} - -static void -make_expression(immed, value) - expression_t *immed; - int value; -{ - SLIST_INIT(&immed->referenced_syms); - immed->value = value & 0xff; -} - -static void -add_conditional(symbol) - symbol_t *symbol; -{ - static int numfuncs; - - if (numfuncs == 0) { - /* add a special conditional, "0" */ - symbol_t *false_func; - - false_func = symtable_get("0"); - if (false_func->type != UNINITIALIZED) { - stop("Conditional expression '0' " - "conflicts with a symbol", EX_DATAERR); - /* NOTREACHED */ - } - false_func->type = CONDITIONAL; - initialize_symbol(false_func); - false_func->info.condinfo->func_num = numfuncs++; - symlist_add(&patch_functions, false_func, SYMLIST_INSERT_HEAD); - } - - /* This condition has occurred before */ - if (symbol->type == CONDITIONAL) - return; - - if (symbol->type != UNINITIALIZED) { - stop("Conditional expression conflicts with a symbol", - EX_DATAERR); - /* NOTREACHED */ - } - - symbol->type = CONDITIONAL; - initialize_symbol(symbol); - symbol->info.condinfo->func_num = numfuncs++; - symlist_add(&patch_functions, symbol, SYMLIST_INSERT_HEAD); -} - -void -yyerror(string) - const char *string; -{ - stop(string, EX_DATAERR); -} - -static int -is_download_const(immed) - expression_t *immed; -{ - if ((immed->referenced_syms.slh_first != NULL) - && (immed->referenced_syms.slh_first->symbol->type == DOWNLOAD_CONST)) - return (TRUE); - - return (FALSE); -} diff --git a/sys/dev/aic7xxx/aicasm_insformat.h b/sys/dev/aic7xxx/aicasm_insformat.h deleted file mode 100644 index 64667472b0ae..000000000000 --- a/sys/dev/aic7xxx/aicasm_insformat.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Instruction formats for the sequencer program downloaded to - * Aic7xxx SCSI host adapters - * - * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include <machine/endian.h> - -struct ins_format1 { -#if BYTE_ORDER == LITTLE_ENDIAN - uint32_t immediate : 8, - source : 9, - destination : 9, - ret : 1, - opcode : 4, - parity : 1; -#else - uint32_t parity : 1, - opcode : 4, - ret : 1, - destination : 9, - source : 9, - immediate : 8; -#endif -}; - -struct ins_format2 { -#if BYTE_ORDER == LITTLE_ENDIAN - uint32_t shift_control : 8, - source : 9, - destination : 9, - ret : 1, - opcode : 4, - parity : 1; -#else - uint32_t parity : 1, - opcode : 4, - ret : 1, - destination : 9, - source : 9, - shift_control : 8; -#endif -}; - -struct ins_format3 { -#if BYTE_ORDER == LITTLE_ENDIAN - uint32_t immediate : 8, - source : 9, - address : 10, - opcode : 4, - parity : 1; -#else - uint32_t parity : 1, - opcode : 4, - address : 10, - source : 9, - immediate : 8; -#endif -}; - -union ins_formats { - struct ins_format1 format1; - struct ins_format2 format2; - struct ins_format3 format3; - uint8_t bytes[4]; - uint32_t integer; -}; -struct instruction { - union ins_formats format; - u_int srcline; - struct symbol *patch_label; - STAILQ_ENTRY(instruction) links; -}; - -#define AIC_OP_OR 0x0 -#define AIC_OP_AND 0x1 -#define AIC_OP_XOR 0x2 -#define AIC_OP_ADD 0x3 -#define AIC_OP_ADC 0x4 -#define AIC_OP_ROL 0x5 -#define AIC_OP_BMOV 0x6 - -#define AIC_OP_JMP 0x8 -#define AIC_OP_JC 0x9 -#define AIC_OP_JNC 0xa -#define AIC_OP_CALL 0xb -#define AIC_OP_JNE 0xc -#define AIC_OP_JNZ 0xd -#define AIC_OP_JE 0xe -#define AIC_OP_JZ 0xf - -/* Pseudo Ops */ -#define AIC_OP_SHL 0x10 -#define AIC_OP_SHR 0x20 -#define AIC_OP_ROR 0x30 diff --git a/sys/dev/aic7xxx/aicasm_scan.l b/sys/dev/aic7xxx/aicasm_scan.l deleted file mode 100644 index 48170d68154d..000000000000 --- a/sys/dev/aic7xxx/aicasm_scan.l +++ /dev/null @@ -1,287 +0,0 @@ -%{ -/* - * Lexical Analyzer for the Aic7xxx SCSI Host adapter sequencer assembler. - * - * Copyright (c) 1997, 1998 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include <sys/types.h> - -#include <limits.h> -#include <stdio.h> -#include <string.h> -#include <sysexits.h> -#include <sys/queue.h> - -#include "aicasm.h" -#include "aicasm_symbol.h" -#include "y.tab.h" - -#define MAX_STR_CONST 256 -char string_buf[MAX_STR_CONST]; -char *string_buf_ptr; -int parren_count; -%} - -PATH [-/A-Za-z0-9_.]*[./][-/A-Za-z0-9_.]* -WORD [A-Za-z_][-A-Za-z_0-9]* -SPACE [ \t]+ - -%x COMMENT -%x CEXPR -%x INCLUDE - -%% -\n { ++yylineno; } -"/*" { BEGIN COMMENT; /* Enter comment eating state */ } -<COMMENT>"/*" { fprintf(stderr, "Warning! Comment within comment."); } -<COMMENT>\n { ++yylineno; } -<COMMENT>[^*/\n]* ; -<COMMENT>"*"+[^*/\n]* ; -<COMMENT>"/"+[^*/\n]* ; -<COMMENT>"*"+"/" { BEGIN INITIAL; } -if[ \t]*\( { - string_buf_ptr = string_buf; - parren_count = 1; - BEGIN CEXPR; - return T_IF; - } -<CEXPR>\( { *string_buf_ptr++ = '('; parren_count++; } -<CEXPR>\) { - parren_count--; - if (parren_count == 0) { - /* All done */ - BEGIN INITIAL; - *string_buf_ptr = '\0'; - yylval.sym = symtable_get(string_buf); - return T_CEXPR; - } else { - *string_buf_ptr++ = ')'; - } - } -<CEXPR>\n { ++yylineno; } -<CEXPR>[^()\n]+ { - char *yptr = yytext; - - while (*yptr != '\0') - *string_buf_ptr++ = *yptr++; - } - -{SPACE} ; - - /* Register/SCB/SRAM definition keywords */ -register { return T_REGISTER; } -const { yylval.value = FALSE; return T_CONST; } -download { return T_DOWNLOAD; } -address { return T_ADDRESS; } -access_mode { return T_ACCESS_MODE; } -RW|RO|WO { - if (strcmp(yytext, "RW") == 0) - yylval.value = RW; - else if (strcmp(yytext, "RO") == 0) - yylval.value = RO; - else - yylval.value = WO; - return T_MODE; - } -bit { return T_BIT; } -mask { return T_MASK; } -alias { return T_ALIAS; } -size { return T_SIZE; } -scb { return T_SCB; } -scratch_ram { return T_SRAM; } -accumulator { return T_ACCUM; } -allones { return T_ALLONES; } -allzeros { return T_ALLZEROS; } -none { return T_NONE; } -sindex { return T_SINDEX; } -A { return T_A; } - - /* Opcodes */ -shl { return T_SHL; } -shr { return T_SHR; } -ror { return T_ROR; } -rol { return T_ROL; } -mvi { return T_MVI; } -mov { return T_MOV; } -clr { return T_CLR; } -jmp { return T_JMP; } -jc { return T_JC; } -jnc { return T_JNC; } -je { return T_JE; } -jne { return T_JNE; } -jz { return T_JZ; } -jnz { return T_JNZ; } -call { return T_CALL; } -add { return T_ADD; } -adc { return T_ADC; } -bmov { return T_BMOV; } -inc { return T_INC; } -dec { return T_DEC; } -stc { return T_STC; } -clc { return T_CLC; } -cmp { return T_CMP; } -not { return T_NOT; } -xor { return T_XOR; } -test { return T_TEST;} -and { return T_AND; } -or { return T_OR; } -ret { return T_RET; } -nop { return T_NOP; } -else { return T_ELSE; } - - /* Allowed Symbols */ -[-+,:()~|&."{};<>[\]!] { return yytext[0]; } - - /* Number processing */ -0[0-7]* { - yylval.value = strtol(yytext, NULL, 8); - return T_NUMBER; - } - -0[xX][0-9a-fA-F]+ { - yylval.value = strtoul(yytext + 2, NULL, 16); - return T_NUMBER; - } - -[1-9][0-9]* { - yylval.value = strtol(yytext, NULL, 10); - return T_NUMBER; - } - - /* Include Files */ -#include { return T_INCLUDE; BEGIN INCLUDE;} -<INCLUDE>[<>\"] { return yytext[0]; } -<INCLUDE>{PATH} { yylval.str = strdup(yytext); return T_PATH; } -<INCLUDE>; { BEGIN INITIAL; return yytext[0]; } -<INCLUDE>. { stop("Invalid include line", EX_DATAERR); } - - /* For parsing C include files with #define foo */ -#define { yylval.value = TRUE; return T_CONST; } - /* Throw away macros */ -#define[^\n]*[()]+[^\n]* ; -{PATH} { yylval.str = strdup(yytext); return T_PATH; } - -{WORD} { yylval.sym = symtable_get(yytext); return T_SYMBOL; } - -. { - char buf[255]; - - snprintf(buf, sizeof(buf), "Invalid character " - "'%c'", yytext[0]); - stop(buf, EX_DATAERR); - } -%% - -typedef struct include { - YY_BUFFER_STATE buffer; - int lineno; - char *filename; - SLIST_ENTRY(include) links; -}include_t; - -SLIST_HEAD(, include) include_stack; - -void -include_file(file_name, type) - char *file_name; - include_type type; -{ - FILE *newfile; - include_t *include; - - newfile = NULL; - /* Try the current directory first */ - if (includes_search_curdir != 0 || type == SOURCE_FILE) - newfile = fopen(file_name, "r"); - - if (newfile == NULL && type != SOURCE_FILE) { - path_entry_t include_dir; - for (include_dir = search_path.slh_first; - include_dir != NULL; - include_dir = include_dir->links.sle_next) { - char fullname[PATH_MAX]; - - if ((include_dir->quoted_includes_only == TRUE) - && (type != QUOTED_INCLUDE)) - continue; - - snprintf(fullname, sizeof(fullname), - "%s/%s", include_dir->directory, file_name); - - if ((newfile = fopen(fullname, "r")) != NULL) - break; - } - } - - if (newfile == NULL) { - perror(file_name); - stop("Unable to open input file", EX_SOFTWARE); - /* NOTREACHED */ - } - - if (type != SOURCE_FILE) { - include = (include_t *)malloc(sizeof(include_t)); - if (include == NULL) { - stop("Unable to allocate include stack entry", - EX_SOFTWARE); - /* NOTREACHED */ - } - include->buffer = YY_CURRENT_BUFFER; - include->lineno = yylineno; - include->filename = yyfilename; - SLIST_INSERT_HEAD(&include_stack, include, links); - } - yy_switch_to_buffer(yy_create_buffer(newfile, YY_BUF_SIZE)); - yylineno = 1; - yyfilename = strdup(file_name); -} - -int -yywrap() -{ - include_t *include; - - yy_delete_buffer(YY_CURRENT_BUFFER); - (void)fclose(yyin); - if (yyfilename != NULL) - free(yyfilename); - yyfilename = NULL; - include = include_stack.slh_first; - if (include != NULL) { - yy_switch_to_buffer(include->buffer); - yylineno = include->lineno; - yyfilename = include->filename; - SLIST_REMOVE_HEAD(&include_stack, links); - free(include); - return (0); - } - return (1); -} diff --git a/sys/dev/aic7xxx/aicasm_symbol.c b/sys/dev/aic7xxx/aicasm_symbol.c deleted file mode 100644 index 43440ea4f40f..000000000000 --- a/sys/dev/aic7xxx/aicasm_symbol.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Aic7xxx SCSI host adapter firmware asssembler symbol table implementation - * - * Copyright (c) 1997 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - - -#include <sys/types.h> - -#include <db.h> -#include <fcntl.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <sysexits.h> - -#include "aicasm_symbol.h" -#include "aicasm.h" - -static DB *symtable; - -symbol_t * -symbol_create(name) - char *name; -{ - symbol_t *new_symbol; - - new_symbol = (symbol_t *)malloc(sizeof(symbol_t)); - if (new_symbol == NULL) { - perror("Unable to create new symbol"); - exit(EX_SOFTWARE); - } - memset(new_symbol, 0, sizeof(*new_symbol)); - new_symbol->name = strdup(name); - new_symbol->type = UNINITIALIZED; - return (new_symbol); -} - -void -symbol_delete(symbol) - symbol_t *symbol; -{ - if (symtable != NULL) { - DBT key; - - key.data = symbol->name; - key.size = strlen(symbol->name); - symtable->del(symtable, &key, /*flags*/0); - } - switch(symbol->type) { - case SCBLOC: - case SRAMLOC: - case REGISTER: - if (symbol->info.rinfo != NULL) - free(symbol->info.rinfo); - break; - case ALIAS: - if (symbol->info.ainfo != NULL) - free(symbol->info.ainfo); - break; - case MASK: - case BIT: - if (symbol->info.minfo != NULL) { - symlist_free(&symbol->info.minfo->symrefs); - free(symbol->info.minfo); - } - break; - case DOWNLOAD_CONST: - case CONST: - if (symbol->info.cinfo != NULL) - free(symbol->info.cinfo); - break; - case LABEL: - if (symbol->info.linfo != NULL) - free(symbol->info.linfo); - break; - case UNINITIALIZED: - default: - break; - } - free(symbol->name); - free(symbol); -} - -void -symtable_open() -{ - symtable = dbopen(/*filename*/NULL, - O_CREAT | O_NONBLOCK | O_RDWR, /*mode*/0, DB_HASH, - /*openinfo*/NULL); - - if (symtable == NULL) { - perror("Symbol table creation failed"); - exit(EX_SOFTWARE); - /* NOTREACHED */ - } -} - -void -symtable_close() -{ - if (symtable != NULL) { - DBT key; - DBT data; - - while (symtable->seq(symtable, &key, &data, R_FIRST) == 0) { - symbol_t *stored_ptr; - - memcpy(&stored_ptr, data.data, sizeof(stored_ptr)); - symbol_delete(stored_ptr); - } - symtable->close(symtable); - } -} - -/* - * The semantics of get is to return an uninitialized symbol entry - * if a lookup fails. - */ -symbol_t * -symtable_get(name) - char *name; -{ - symbol_t *stored_ptr; - DBT key; - DBT data; - int retval; - - key.data = (void *)name; - key.size = strlen(name); - - if ((retval = symtable->get(symtable, &key, &data, /*flags*/0)) != 0) { - if (retval == -1) { - perror("Symbol table get operation failed"); - exit(EX_SOFTWARE); - /* NOTREACHED */ - } else if (retval == 1) { - /* Symbol wasn't found, so create a new one */ - symbol_t *new_symbol; - - new_symbol = symbol_create(name); - data.data = &new_symbol; - data.size = sizeof(new_symbol); - if (symtable->put(symtable, &key, &data, - /*flags*/0) !=0) { - perror("Symtable put failed"); - exit(EX_SOFTWARE); - } - return (new_symbol); - } else { - perror("Unexpected return value from db get routine"); - exit(EX_SOFTWARE); - /* NOTREACHED */ - } - } - memcpy(&stored_ptr, data.data, sizeof(stored_ptr)); - return (stored_ptr); -} - -symbol_node_t * -symlist_search(symlist, symname) - symlist_t *symlist; - char *symname; -{ - symbol_node_t *curnode; - - curnode = symlist->slh_first; - while(curnode != NULL) { - if (strcmp(symname, curnode->symbol->name) == 0) - break; - curnode = curnode->links.sle_next; - } - return (curnode); -} - -void -symlist_add(symlist, symbol, how) - symlist_t *symlist; - symbol_t *symbol; - int how; -{ - symbol_node_t *newnode; - - newnode = (symbol_node_t *)malloc(sizeof(symbol_node_t)); - if (newnode == NULL) { - stop("symlist_add: Unable to malloc symbol_node", EX_SOFTWARE); - /* NOTREACHED */ - } - newnode->symbol = symbol; - if (how == SYMLIST_SORT) { - symbol_node_t *curnode; - int mask; - - mask = FALSE; - switch(symbol->type) { - case REGISTER: - case SCBLOC: - case SRAMLOC: - break; - case BIT: - case MASK: - mask = TRUE; - break; - default: - stop("symlist_add: Invalid symbol type for sorting", - EX_SOFTWARE); - /* NOTREACHED */ - } - - curnode = symlist->slh_first; - if (curnode == NULL - || (mask && (curnode->symbol->info.minfo->mask > - newnode->symbol->info.minfo->mask)) - || (!mask && (curnode->symbol->info.rinfo->address > - newnode->symbol->info.rinfo->address))) { - SLIST_INSERT_HEAD(symlist, newnode, links); - return; - } - - while (1) { - if (curnode->links.sle_next == NULL) { - SLIST_INSERT_AFTER(curnode, newnode, - links); - break; - } else { - symbol_t *cursymbol; - - cursymbol = curnode->links.sle_next->symbol; - if ((mask && (cursymbol->info.minfo->mask > - symbol->info.minfo->mask)) - || (!mask &&(cursymbol->info.rinfo->address > - symbol->info.rinfo->address))){ - SLIST_INSERT_AFTER(curnode, newnode, - links); - break; - } - } - curnode = curnode->links.sle_next; - } - } else { - SLIST_INSERT_HEAD(symlist, newnode, links); - } -} - -void -symlist_free(symlist) - symlist_t *symlist; -{ - symbol_node_t *node1, *node2; - - node1 = symlist->slh_first; - while (node1 != NULL) { - node2 = node1->links.sle_next; - free(node1); - node1 = node2; - } - SLIST_INIT(symlist); -} - -void -symlist_merge(symlist_dest, symlist_src1, symlist_src2) - symlist_t *symlist_dest; - symlist_t *symlist_src1; - symlist_t *symlist_src2; -{ - symbol_node_t *node; - - *symlist_dest = *symlist_src1; - while((node = symlist_src2->slh_first) != NULL) { - SLIST_REMOVE_HEAD(symlist_src2, links); - SLIST_INSERT_HEAD(symlist_dest, node, links); - } - - /* These are now empty */ - SLIST_INIT(symlist_src1); - SLIST_INIT(symlist_src2); -} - -void -symtable_dump(ofile) - FILE *ofile; -{ - /* - * Sort the registers by address with a simple insertion sort. - * Put bitmasks next to the first register that defines them. - * Put constants at the end. - */ - symlist_t registers; - symlist_t masks; - symlist_t constants; - symlist_t download_constants; - symlist_t aliases; - - SLIST_INIT(®isters); - SLIST_INIT(&masks); - SLIST_INIT(&constants); - SLIST_INIT(&download_constants); - SLIST_INIT(&aliases); - - if (symtable != NULL) { - DBT key; - DBT data; - int flag = R_FIRST; - - while (symtable->seq(symtable, &key, &data, flag) == 0) { - symbol_t *cursym; - - memcpy(&cursym, data.data, sizeof(cursym)); - switch(cursym->type) { - case REGISTER: - case SCBLOC: - case SRAMLOC: - symlist_add(®isters, cursym, SYMLIST_SORT); - break; - case MASK: - case BIT: - symlist_add(&masks, cursym, SYMLIST_SORT); - break; - case CONST: - if (cursym->info.cinfo->define == FALSE) { - symlist_add(&constants, cursym, - SYMLIST_INSERT_HEAD); - } - break; - case DOWNLOAD_CONST: - symlist_add(&download_constants, cursym, - SYMLIST_INSERT_HEAD); - break; - case ALIAS: - symlist_add(&aliases, cursym, - SYMLIST_INSERT_HEAD); - break; - default: - break; - } - flag = R_NEXT; - } - - /* Put in the masks and bits */ - while (masks.slh_first != NULL) { - symbol_node_t *curnode; - symbol_node_t *regnode; - char *regname; - - curnode = masks.slh_first; - SLIST_REMOVE_HEAD(&masks, links); - - regnode = - curnode->symbol->info.minfo->symrefs.slh_first; - regname = regnode->symbol->name; - regnode = symlist_search(®isters, regname); - SLIST_INSERT_AFTER(regnode, curnode, links); - } - - /* Add the aliases */ - while (aliases.slh_first != NULL) { - symbol_node_t *curnode; - symbol_node_t *regnode; - char *regname; - - curnode = aliases.slh_first; - SLIST_REMOVE_HEAD(&aliases, links); - - regname = curnode->symbol->info.ainfo->parent->name; - regnode = symlist_search(®isters, regname); - SLIST_INSERT_AFTER(regnode, curnode, links); - } - - /* Output what we have */ - fprintf(ofile, -"/* - * DO NOT EDIT - This file is automatically generated. - */\n"); - while (registers.slh_first != NULL) { - symbol_node_t *curnode; - uint8_t value; - char *tab_str; - char *tab_str2; - - curnode = registers.slh_first; - SLIST_REMOVE_HEAD(®isters, links); - switch(curnode->symbol->type) { - case REGISTER: - case SCBLOC: - case SRAMLOC: - fprintf(ofile, "\n"); - value = curnode->symbol->info.rinfo->address; - tab_str = "\t"; - tab_str2 = "\t\t"; - break; - case ALIAS: - { - symbol_t *parent; - - parent = curnode->symbol->info.ainfo->parent; - value = parent->info.rinfo->address; - tab_str = "\t"; - tab_str2 = "\t\t"; - break; - } - case MASK: - case BIT: - value = curnode->symbol->info.minfo->mask; - tab_str = "\t\t"; - tab_str2 = "\t"; - break; - default: - value = 0; /* Quiet compiler */ - tab_str = NULL; - tab_str2 = NULL; - stop("symtable_dump: Invalid symbol type " - "encountered", EX_SOFTWARE); - break; - } - fprintf(ofile, "#define%s%-16s%s0x%02x\n", - tab_str, curnode->symbol->name, tab_str2, - value); - free(curnode); - } - fprintf(ofile, "\n\n"); - - while (constants.slh_first != NULL) { - symbol_node_t *curnode; - - curnode = constants.slh_first; - SLIST_REMOVE_HEAD(&constants, links); - fprintf(ofile, "#define\t%-8s\t0x%02x\n", - curnode->symbol->name, - curnode->symbol->info.cinfo->value); - free(curnode); - } - - - fprintf(ofile, "\n\n/* Downloaded Constant Definitions */\n"); - - while (download_constants.slh_first != NULL) { - symbol_node_t *curnode; - - curnode = download_constants.slh_first; - SLIST_REMOVE_HEAD(&download_constants, links); - fprintf(ofile, "#define\t%-8s\t0x%02x\n", - curnode->symbol->name, - curnode->symbol->info.cinfo->value); - free(curnode); - } - } -} - diff --git a/sys/dev/aic7xxx/aicasm_symbol.h b/sys/dev/aic7xxx/aicasm_symbol.h deleted file mode 100644 index 37f5e7f66664..000000000000 --- a/sys/dev/aic7xxx/aicasm_symbol.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Aic7xxx SCSI host adapter firmware asssembler symbol table definitions - * - * Copyright (c) 1997 Justin T. Gibbs. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU Public License ("GPL"). - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include <sys/queue.h> - -typedef enum { - UNINITIALIZED, - REGISTER, - ALIAS, - SCBLOC, - SRAMLOC, - MASK, - BIT, - CONST, - DOWNLOAD_CONST, - LABEL, - CONDITIONAL -}symtype; - -typedef enum { - RO = 0x01, - WO = 0x02, - RW = 0x03 -}amode_t; - -struct reg_info { - uint8_t address; - int size; - amode_t mode; - uint8_t valid_bitmask; - int typecheck_masks; -}; - -typedef SLIST_HEAD(symlist, symbol_node) symlist_t; - -struct mask_info { - symlist_t symrefs; - uint8_t mask; -}; - -struct const_info { - uint8_t value; - int define; -}; - -struct alias_info { - struct symbol *parent; -}; - -struct label_info { - int address; -}; - -struct cond_info { - int func_num; -}; - -typedef struct expression_info { - symlist_t referenced_syms; - int value; -} expression_t; - -typedef struct symbol { - char *name; - symtype type; - union { - struct reg_info *rinfo; - struct mask_info *minfo; - struct const_info *cinfo; - struct alias_info *ainfo; - struct label_info *linfo; - struct cond_info *condinfo; - }info; -} symbol_t; - -typedef struct symbol_ref { - symbol_t *symbol; - int offset; -} symbol_ref_t; - -typedef struct symbol_node { - SLIST_ENTRY(symbol_node) links; - symbol_t *symbol; -}symbol_node_t; - -typedef enum { - SCOPE_ROOT, - SCOPE_IF, - SCOPE_ELSE_IF, - SCOPE_ELSE -} scope_type; - -typedef struct patch_info { - int skip_patch; - int skip_instr; -} patch_info_t; - -typedef struct scope { - SLIST_ENTRY(scope) scope_stack_links; - TAILQ_ENTRY(scope) scope_links; - TAILQ_HEAD(, scope) inner_scope; - scope_type type; - int inner_scope_patches; - int begin_addr; - int end_addr; - patch_info_t patches[2]; - int func_num; -} scope_t; - -SLIST_HEAD(scope_list, scope); -TAILQ_HEAD(scope_tailq, scope); - -void symbol_delete __P((symbol_t *symbol)); - -void symtable_open __P((void)); - -void symtable_close __P((void)); - -symbol_t * - symtable_get __P((char *name)); - -symbol_node_t * - symlist_search __P((symlist_t *symlist, char *symname)); - -void - symlist_add __P((symlist_t *symlist, symbol_t *symbol, int how)); -#define SYMLIST_INSERT_HEAD 0x00 -#define SYMLIST_SORT 0x01 - -void symlist_free __P((symlist_t *symlist)); - -void symlist_merge __P((symlist_t *symlist_dest, symlist_t *symlist_src1, - symlist_t *symlist_src2)); -void symtable_dump __P((FILE *ofile)); |