diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 43 |
1 files changed, 29 insertions, 14 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 676f6f0a2a8c..847b9a672891 100644 --- a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -109,19 +109,19 @@ public: bool AllowModify) const override; /// Remove the branching code at the end of the specific MBB. - /// This is only invoked in cases where AnalyzeBranch returns success. It + /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions that were removed. unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; /// Insert branch code into the end of the specified MachineBasicBlock. /// The operands to this method are the same as those - /// returned by AnalyzeBranch. This is only invoked in cases where - /// AnalyzeBranch returns success. It returns the number of instructions + /// returned by analyzeBranch. This is only invoked in cases where + /// analyzeBranch returns success. It returns the number of instructions /// inserted. /// /// It is also invoked by tail merging to add unconditional branches in - /// cases where AnalyzeBranch doesn't apply because there was no original + /// cases where analyzeBranch doesn't apply because there was no original /// branch to analyze. At least this much must be implemented, else tail /// merging needs to be disabled. unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, @@ -182,7 +182,7 @@ public: /// is true, the register operand is the last use and must be marked kill. void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; @@ -191,7 +191,7 @@ public: /// machine basic block before the specified machine instruction. void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; @@ -204,10 +204,11 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; /// Get the base register and byte offset of a load/store instr. - bool getMemOperandWithOffset(const MachineInstr &LdSt, - const MachineOperand *&BaseOp, - int64_t &Offset, - const TargetRegisterInfo *TRI) const override; + bool getMemOperandsWithOffsetWidth( + const MachineInstr &LdSt, + SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, + bool &OffsetIsScalable, unsigned &Width, + const TargetRegisterInfo *TRI) const override; /// Reverses the branch condition of the specified condition list, /// returning false on success and true if it cannot be reversed. @@ -268,8 +269,8 @@ public: /// in SrcReg and SrcReg2 if having two register operands, and the value it /// compares against in CmpValue. Return true if the comparison instruction /// can be analyzed. - bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, - unsigned &SrcReg2, int &Mask, int &Value) const override; + bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int &Mask, int &Value) const override; /// Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via @@ -341,10 +342,10 @@ public: MachineBasicBlock *TargetBB, SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; - bool isBaseImmOffset(const MachineInstr &MI) const; bool isAbsoluteSet(const MachineInstr &MI) const; bool isAccumulator(const MachineInstr &MI) const; bool isAddrModeWithOffset(const MachineInstr &MI) const; + bool isBaseImmOffset(const MachineInstr &MI) const; bool isComplex(const MachineInstr &MI) const; bool isCompoundBranchInstr(const MachineInstr &MI) const; bool isConstExtended(const MachineInstr &MI) const; @@ -387,6 +388,8 @@ public: bool isPredicated(unsigned Opcode) const; bool isPredicateLate(unsigned Opcode) const; bool isPredictedTaken(unsigned Opcode) const; + bool isPureSlot0(const MachineInstr &MI) const; + bool isRestrictNoSlot1Store(const MachineInstr &MI) const; bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const; bool isSignExtendingLoad(const MachineInstr &MI) const; bool isSolo(const MachineInstr &MI) const; @@ -435,6 +438,7 @@ public: getCompoundCandidateGroup(const MachineInstr &MI) const; unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const; + int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const; int getCondOpcode(int Opc, bool sense) const; int getDotCurOp(const MachineInstr &MI) const; int getNonDotCurOp(const MachineInstr &MI) const; @@ -461,7 +465,7 @@ public: short getRegForm(const MachineInstr &MI) const; unsigned getSize(const MachineInstr &MI) const; uint64_t getType(const MachineInstr &MI) const; - unsigned getUnits(const MachineInstr &MI) const; + InstrStage::FuncUnits getUnits(const MachineInstr &MI) const; MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const; @@ -480,6 +484,17 @@ public: void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const; bool getBundleNoShuf(const MachineInstr &MIB) const; + + // When TinyCore with Duplexes is enabled, this function is used to translate + // tiny-instructions to big-instructions and vice versa to get the slot + // consumption. + void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, + bool ToBigInstrs) const; + void translateInstrsForDup(MachineFunction &MF, + bool ToBigInstrs = true) const; + void translateInstrsForDup(MachineBasicBlock::instr_iterator MII, + bool ToBigInstrs) const; + // Addressing mode relations. short changeAddrMode_abs_io(short Opc) const; short changeAddrMode_io_abs(short Opc) const; |