diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h index 3905a18895de..c17e51f44651 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h @@ -21,6 +21,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineMemOperand.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/TargetLowering.h" @@ -28,12 +29,9 @@ #include "llvm/IR/CallingConv.h" #include "llvm/IR/InlineAsm.h" #include "llvm/IR/Type.h" -#include "llvm/Support/MachineValueType.h" #include "llvm/Target/TargetMachine.h" #include <algorithm> -#include <cassert> #include <deque> -#include <string> #include <utility> #include <vector> @@ -99,6 +97,9 @@ class TargetRegisterClass; // Floating Point Compare FPCmp, + // Floating point Abs + FAbs, + // Floating point select FSELECT, @@ -157,7 +158,7 @@ class TargetRegisterClass; Ins, CIns, - // EXTR.W instrinsic nodes. + // EXTR.W intrinsic nodes. EXTP, EXTPDP, EXTR_S_H, @@ -280,8 +281,9 @@ class TargetRegisterClass; EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override; - bool isCheapToSpeculateCttz() const override; - bool isCheapToSpeculateCtlz() const override; + bool isCheapToSpeculateCttz(Type *Ty) const override; + bool isCheapToSpeculateCtlz(Type *Ty) const override; + bool hasBitTest(SDValue X, SDValue Y) const override; bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override; @@ -520,7 +522,7 @@ class TargetRegisterClass; unsigned Flag) const; // Lower Operand helpers - SDValue LowerCallResult(SDValue Chain, SDValue InFlag, + SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, @@ -540,6 +542,10 @@ class TargetRegisterClass; SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, + bool HasExtractInsert) const; + SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, + bool HasExtractInsert) const; SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; @@ -633,19 +639,18 @@ class TargetRegisterClass; /// vector. If it is invalid, don't add anything to Ops. If hasMemory is /// true it means one of the asm constraint of the inline asm instruction /// being processed is 'm'. - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const override; - unsigned + InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override { if (ConstraintCode == "o") - return InlineAsm::Constraint_o; + return InlineAsm::ConstraintCode::o; if (ConstraintCode == "R") - return InlineAsm::Constraint_R; + return InlineAsm::ConstraintCode::R; if (ConstraintCode == "ZC") - return InlineAsm::Constraint_ZC; + return InlineAsm::ConstraintCode::ZC; return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); } |