diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.h | 60 |
1 files changed, 46 insertions, 14 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.h b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.h index 48c5ce730933..58b7ec89f875 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -63,11 +63,11 @@ enum NodeType : unsigned { CLZW, CTZW, // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V - // instructions, but the same operand order as fshl/fshr intrinsics. + // instructions. Operand order is rs1, rs3, rs2/shamt. FSR, FSL, - // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, - // but the same operand order as fshl/fshr intrinsics. + // RV64IB funnel shifts, with the semantics of the named RISC-V instructions. + // Operand order is rs1, rs3, rs2/shamt. FSRW, FSLW, // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as @@ -86,14 +86,16 @@ enum NodeType : unsigned { FMV_X_ANYEXTW_RV64, // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of - // range inputs. These are used for FP_TO_S/UINT_SAT lowering. - FCVT_X_RTZ, - FCVT_XU_RTZ, + // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode + // is passed as a TargetConstant operand using the RISCVFPRndMode enum. + FCVT_X, + FCVT_XU, // FP to 32 bit int conversions for RV64. These are used to keep track of the // result being sign extended to 64 bit. These saturate out of range inputs. - // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. - FCVT_W_RTZ_RV64, - FCVT_WU_RTZ_RV64, + // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode + // is passed as a TargetConstant operand using the RISCVFPRndMode enum. + FCVT_W_RV64, + FCVT_WU_RV64, // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target // (returns (Lo, Hi)). It takes a chain operand. READ_CYCLE_WIDE, @@ -118,6 +120,13 @@ enum NodeType : unsigned { BCOMPRESSW, BDECOMPRESS, BDECOMPRESSW, + // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2 + // into the value in rs1. The upper bits of rs2 control the length of the bit + // field and target position. The layout of rs2 is chosen in a way that makes + // it possible to construct rs2 easily using pack[h] instructions and/or + // andi/lui. + BFP, + BFPW, // Vector Extension // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand // for the VL value to be used for the operation. @@ -236,6 +245,7 @@ enum NodeType : unsigned { // Widening instructions VWMUL_VL, VWMULU_VL, + VWADDU_VL, // Vector compare producing a mask. Fourth operand is input mask. Fifth // operand is VL. @@ -243,6 +253,10 @@ enum NodeType : unsigned { // Vector select with an additional VL operand. This operation is unmasked. VSELECT_VL, + // Vector select with operand #2 (the value when the condition is false) tied + // to the destination and an additional VL operand. This operation is + // unmasked. + VP_MERGE_VL, // Mask binary operators. VMAND_VL, @@ -284,8 +298,8 @@ enum NodeType : unsigned { // FP to 32 bit int conversions for RV64. These are used to keep track of the // result being sign extended to 64 bit. These saturate out of range inputs. - STRICT_FCVT_W_RTZ_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE, - STRICT_FCVT_WU_RTZ_RV64, + STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE, + STRICT_FCVT_WU_RV64, // Memory opcodes start here. VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, @@ -462,6 +476,8 @@ public: SelectionDAG &DAG) const override; SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const override; + template <class NodeTy> + SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override { @@ -524,6 +540,16 @@ public: bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; + SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, + SmallVectorImpl<SDNode *> &Created) const override; + + unsigned getJumpTableEncoding() const override; + + const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, + const MachineBasicBlock *MBB, + unsigned uid, + MCContext &Ctx) const override; + private: /// RISCVCCAssignFn - This target-specific function extends the default /// CCValAssign with additional information used to lower RISC-V calling @@ -544,9 +570,6 @@ private: bool IsRet, CallLoweringInfo *CLI, RISCVCCAssignFn Fn) const; - template <class NodeTy> - SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; - SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const; SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; @@ -652,6 +675,15 @@ namespace RISCVVIntrinsicsTable { struct RISCVVIntrinsicInfo { unsigned IntrinsicID; uint8_t SplatOperand; + uint8_t VLOperand; + bool hasSplatOperand() const { + // 0xF is not valid. See NoSplatOperand in IntrinsicsRISCV.td. + return SplatOperand != 0xF; + } + bool hasVLOperand() const { + // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td. + return VLOperand != 0x1F; + } }; using namespace RISCV; |