diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp | 42 |
1 files changed, 7 insertions, 35 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index 6fe1fd2b5c5a..db2ad05b4cdf 100644 --- a/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -76,8 +76,10 @@ void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB, CopyOpcode = WebAssembly::COPY_F64; else if (RC == &WebAssembly::V128RegClass) CopyOpcode = WebAssembly::COPY_V128; - else if (RC == &WebAssembly::EXNREFRegClass) - CopyOpcode = WebAssembly::COPY_EXNREF; + else if (RC == &WebAssembly::FUNCREFRegClass) + CopyOpcode = WebAssembly::COPY_FUNCREF; + else if (RC == &WebAssembly::EXTERNREFRegClass) + CopyOpcode = WebAssembly::COPY_EXTERNREF; else llvm_unreachable("Unexpected register class"); @@ -139,14 +141,6 @@ bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, else FBB = MI.getOperand(0).getMBB(); break; - case WebAssembly::BR_ON_EXN: - if (HaveCond) - return true; - Cond.push_back(MachineOperand::CreateImm(true)); - Cond.push_back(MI.getOperand(2)); - TBB = MI.getOperand(0).getMBB(); - HaveCond = true; - break; } if (MI.isBarrier()) break; @@ -192,24 +186,10 @@ unsigned WebAssemblyInstrInfo::insertBranch( assert(Cond.size() == 2 && "Expected a flag and a successor block"); - MachineFunction &MF = *MBB.getParent(); - auto &MRI = MF.getRegInfo(); - bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) == - &WebAssembly::EXNREFRegClass; - - if (Cond[0].getImm()) { - if (IsBrOnExn) { - const char *CPPExnSymbol = MF.createExternalSymbolName("__cpp_exception"); - BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN)) - .addMBB(TBB) - .addExternalSymbol(CPPExnSymbol) - .add(Cond[1]); - } else - BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); - } else { - assert(!IsBrOnExn && "br_on_exn does not have a reversed condition"); + if (Cond[0].getImm()) + BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); + else BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]); - } if (!FBB) return 1; @@ -220,14 +200,6 @@ unsigned WebAssemblyInstrInfo::insertBranch( bool WebAssemblyInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 2 && "Expected a flag and a condition expression"); - - // br_on_exn's condition cannot be reversed - MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent(); - auto &MRI = MF.getRegInfo(); - if (Cond[1].isReg() && - MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass) - return true; - Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm()); return false; } |