diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.h')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.h | 62 |
1 files changed, 35 insertions, 27 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 9530d9f2aa0d..66b6883c955b 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -43,7 +43,7 @@ public: /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr *MI, + unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// If the specified machine instruction is a direct @@ -51,7 +51,7 @@ public: /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr *MI, + unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// Analyze the branching code at the end of MBB, returning @@ -79,10 +79,10 @@ public: /// If AllowModify is true, then this routine is allowed to modify the basic /// block (e.g. delete instructions after the unconditional branch). /// - bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl<MachineOperand> &Cond, - bool AllowModify) const override; + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, + bool AllowModify) const override; /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where AnalyzeBranch returns success. It @@ -101,7 +101,7 @@ public: /// merging needs to be disabled. unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, - DebugLoc DL) const override; + const DebugLoc &DL) const override; /// Return true if it's profitable to predicate /// instructions with accumulated instruction latency of "NumCycles" @@ -141,9 +141,8 @@ public: /// The source and destination registers may overlap, which may require a /// careful implementation when multiple copy instructions are required for /// large registers. See for example the ARM target. - void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, + void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override; /// Store the specified register of the given register class to the specified @@ -171,7 +170,7 @@ public: /// into real instructions. The target can edit MI in place, or it can insert /// new instructions and erase MI. The function should return true if /// anything was changed. - bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; + bool expandPostRAPseudo(MachineInstr &MI) const override; /// Reverses the branch condition of the specified condition list, /// returning false on success and true if it cannot be reversed. @@ -183,11 +182,11 @@ public: MachineBasicBlock::iterator MI) const override; /// Returns true if the instruction is already predicated. - bool isPredicated(const MachineInstr *MI) const override; + bool isPredicated(const MachineInstr &MI) const override; /// Convert the instruction into a predicated instruction. /// It returns true if the operation was successful. - bool PredicateInstruction(MachineInstr *MI, + bool PredicateInstruction(MachineInstr &MI, ArrayRef<MachineOperand> Cond) const override; /// Returns true if the first specified predicate @@ -198,17 +197,17 @@ public: /// If the specified instruction defines any predicate /// or condition code register(s) used for predication, returns true as well /// as the definition predicate(s) by reference. - bool DefinesPredicate(MachineInstr *MI, + bool DefinesPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred) const override; /// Return true if the specified instruction can be predicated. /// By default, this returns true for every instruction with a /// PredicateOperand. - bool isPredicable(MachineInstr *MI) const override; + bool isPredicable(MachineInstr &MI) const override; /// Test if the given instruction should be considered a scheduling boundary. /// This primarily includes labels and terminators. - bool isSchedulingBoundary(const MachineInstr *MI, + bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override; @@ -227,15 +226,14 @@ public: /// in SrcReg and SrcReg2 if having two register operands, and the value it /// compares against in CmpValue. Return true if the comparison instruction /// can be analyzed. - bool analyzeCompare(const MachineInstr *MI, - unsigned &SrcReg, unsigned &SrcReg2, - int &Mask, int &Value) const override; + bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, + unsigned &SrcReg2, int &Mask, int &Value) const override; /// Compute the instruction latency of a given instruction. /// If the instruction has higher cost when predicated, it's returned via /// PredCost. unsigned getInstrLatency(const InstrItineraryData *ItinData, - const MachineInstr *MI, + const MachineInstr &MI, unsigned *PredCost = 0) const override; /// Create machine specific model for scheduling. @@ -246,10 +244,9 @@ public: // to tell, even without aliasing information, that two MIs access different // memory addresses. This function returns true if two MIs access different // memory addresses and false otherwise. - bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, - AliasAnalysis *AA = nullptr) - const override; - + bool + areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, + AliasAnalysis *AA = nullptr) const override; /// HexagonInstrInfo specifics. /// @@ -301,20 +298,24 @@ public: bool isNewValueStore(unsigned Opcode) const; bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const; bool isPostIncrement(const MachineInstr* MI) const; - bool isPredicatedNew(const MachineInstr *MI) const; + bool isPredicatedNew(const MachineInstr &MI) const; bool isPredicatedNew(unsigned Opcode) const; - bool isPredicatedTrue(const MachineInstr *MI) const; + bool isPredicatedTrue(const MachineInstr &MI) const; bool isPredicatedTrue(unsigned Opcode) const; bool isPredicated(unsigned Opcode) const; bool isPredicateLate(unsigned Opcode) const; bool isPredictedTaken(unsigned Opcode) const; bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const; + bool isSignExtendingLoad(const MachineInstr &MI) const; bool isSolo(const MachineInstr* MI) const; bool isSpillPredRegOp(const MachineInstr *MI) const; + bool isTailCall(const MachineInstr *MI) const; bool isTC1(const MachineInstr *MI) const; bool isTC2(const MachineInstr *MI) const; bool isTC2Early(const MachineInstr *MI) const; bool isTC4x(const MachineInstr *MI) const; + bool isToBeScheduledASAP(const MachineInstr *MI1, + const MachineInstr *MI2) const; bool isV60VectorInstruction(const MachineInstr *MI) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; @@ -322,8 +323,10 @@ public: bool isVecALU(const MachineInstr *MI) const; bool isVecUsableNextPacket(const MachineInstr *ProdMI, const MachineInstr *ConsMI) const; + bool isZeroExtendingLoad(const MachineInstr &MI) const; - + bool addLatencyToSchedule(const MachineInstr *MI1, + const MachineInstr *MI2) const; bool canExecuteInBundle(const MachineInstr *First, const MachineInstr *Second) const; bool hasEHLabel(const MachineBasicBlock *B) const; @@ -341,11 +344,15 @@ public: bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; + short getAbsoluteForm(const MachineInstr *MI) const; unsigned getAddrMode(const MachineInstr* MI) const; unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset, unsigned &AccessSize) const; bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos, unsigned &OffsetPos) const; + short getBaseWithLongOffset(short Opcode) const; + short getBaseWithLongOffset(const MachineInstr *MI) const; + short getBaseWithRegOffset(const MachineInstr *MI) const; SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const; unsigned getCExtOpNum(const MachineInstr *MI) const; HexagonII::CompoundGroup @@ -395,6 +402,7 @@ public: bool reversePredSense(MachineInstr* MI) const; unsigned reversePrediction(unsigned Opcode) const; bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const; + short xformRegToImmOffset(const MachineInstr *MI) const; }; } |