diff options
Diffstat (limited to 'lib/libpmc/pmu-events/arch/test/test_soc')
5 files changed, 117 insertions, 0 deletions
diff --git a/lib/libpmc/pmu-events/arch/test/test_soc/cpu/branch.json b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/branch.json new file mode 100644 index 000000000000..93ddfd8053ca --- /dev/null +++ b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/branch.json @@ -0,0 +1,12 @@ +[ + { + "EventName": "bp_l1_btb_correct", + "EventCode": "0x8a", + "BriefDescription": "L1 BTB Correction." + }, + { + "EventName": "bp_l2_btb_correct", + "EventCode": "0x8b", + "BriefDescription": "L2 BTB Correction." + } +] diff --git a/lib/libpmc/pmu-events/arch/test/test_soc/cpu/cache.json b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/cache.json new file mode 100644 index 000000000000..036d0efdb2bb --- /dev/null +++ b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/cache.json @@ -0,0 +1,5 @@ +[ + { + "ArchStdEvent": "L3_CACHE_RD" + } +]
\ No newline at end of file diff --git a/lib/libpmc/pmu-events/arch/test/test_soc/cpu/other.json b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/other.json new file mode 100644 index 000000000000..7d53d7ecd723 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/other.json @@ -0,0 +1,26 @@ +[ + { + "EventCode": "0x6", + "Counter": "0,1", + "UMask": "0x80", + "EventName": "SEGMENT_REG_LOADS.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Number of segment register loads." + }, + { + "EventCode": "0x9", + "Counter": "0,1", + "UMask": "0x20", + "EventName": "DISPATCH_BLOCKED.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason" + }, + { + "EventCode": "0x3A", + "Counter": "0,1", + "UMask": "0x0", + "EventName": "EIST_TRANS", + "SampleAfterValue": "200000", + "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions" + } +]
\ No newline at end of file diff --git a/lib/libpmc/pmu-events/arch/test/test_soc/cpu/uncore.json b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/uncore.json new file mode 100644 index 000000000000..41bac1c6a008 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/test/test_soc/cpu/uncore.json @@ -0,0 +1,58 @@ +[ + { + "EventCode": "0x02", + "EventName": "uncore_hisi_ddrc.flux_wcmd", + "BriefDescription": "DDRC write commands", + "PublicDescription": "DDRC write commands", + "Unit": "hisi_sccl,ddrc" + }, + { + "Unit": "CBO", + "EventCode": "0x22", + "UMask": "0x81", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "Counter": "0,1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0" + }, + { + "Unit": "CBO", + "EventCode": "0xE0", + "UMask": "0x00", + "EventName": "event-hyphen", + "BriefDescription": "UNC_CBO_HYPHEN", + "PublicDescription": "UNC_CBO_HYPHEN" + }, + { + "Unit": "CBO", + "EventCode": "0xC0", + "UMask": "0x00", + "EventName": "event-two-hyph", + "BriefDescription": "UNC_CBO_TWO_HYPH", + "PublicDescription": "UNC_CBO_TWO_HYPH" + }, + { + "EventCode": "0x7", + "EventName": "uncore_hisi_l3c.rd_hit_cpipe", + "BriefDescription": "Total read hits", + "PublicDescription": "Total read hits", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x12", + "EventName": "uncore_imc_free_running.cache_miss", + "BriefDescription": "Total cache misses", + "PublicDescription": "Total cache misses", + "Unit": "imc_free_running" + }, + { + "EventCode": "0x34", + "EventName": "uncore_imc.cache_hits", + "BriefDescription": "Total cache hits", + "PublicDescription": "Total cache hits", + "Unit": "imc" + } +] diff --git a/lib/libpmc/pmu-events/arch/test/test_soc/sys/uncore.json b/lib/libpmc/pmu-events/arch/test/test_soc/sys/uncore.json new file mode 100644 index 000000000000..c7e7528db315 --- /dev/null +++ b/lib/libpmc/pmu-events/arch/test/test_soc/sys/uncore.json @@ -0,0 +1,16 @@ +[ + { + "BriefDescription": "ddr write-cycles event", + "EventCode": "0x2b", + "EventName": "sys_ddr_pmu.write_cycles", + "Unit": "sys_ddr_pmu", + "Compat": "v8" + }, + { + "BriefDescription": "ccn read-cycles event", + "ConfigCode": "0x2c", + "EventName": "sys_ccn_pmu.read_cycles", + "Unit": "sys_ccn_pmu", + "Compat": "0x01" + } +] |