diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.h | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 1f198a92c0fa..1cd7f1b29e07 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -147,6 +147,7 @@ private: SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const; + SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const; SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const; SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; @@ -211,12 +212,16 @@ private: unsigned getFusedOpcode(const SelectionDAG &DAG, const SDNode *N0, const SDNode *N1) const; SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N, + DAGCombinerInfo &DCI) const; + SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const; + SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; @@ -310,9 +315,9 @@ public: SmallVectorImpl<SDValue> &Ops, SelectionDAG &DAG) const override; - bool getAddrModeArguments(IntrinsicInst * /*I*/, - SmallVectorImpl<Value*> &/*Ops*/, - Type *&/*AccessTy*/) const override; + bool getAddrModeArguments(const IntrinsicInst *I, + SmallVectorImpl<Value *> &Ops, + Type *&AccessTy) const override; bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const; bool isLegalGlobalAddressingMode(const AddrMode &AM) const; @@ -346,7 +351,6 @@ public: EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override; - bool isMemOpUniform(const SDNode *N) const; bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; static bool isNonGlobalAddrSpace(unsigned AS); @@ -361,6 +365,7 @@ public: bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override; + bool isExtractVecEltCheap(EVT VT, unsigned Index) const override; bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; @@ -387,7 +392,7 @@ public: bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, - LLVMContext &Context) const override; + LLVMContext &Context, const Type *RetTy) const override; SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, @@ -420,7 +425,6 @@ public: SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const override; - SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; @@ -456,6 +460,7 @@ public: EVT VT) const override; bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, const LLT Ty) const override; + bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; @@ -463,7 +468,6 @@ public: SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const override; @@ -536,6 +540,8 @@ public: const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const override; + bool isProfitableToHoist(Instruction *I) const override; + bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN = false, @@ -545,7 +551,10 @@ public: AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; + + void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const; void emitExpandAtomicRMW(AtomicRMWInst *AI) const override; + void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override; LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; |