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Diffstat (limited to 'secure/lib/libcrypto/man/man3/OPENSSL_ppccap.3')
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diff --git a/secure/lib/libcrypto/man/man3/OPENSSL_ppccap.3 b/secure/lib/libcrypto/man/man3/OPENSSL_ppccap.3 new file mode 100644 index 000000000000..b5734163a026 --- /dev/null +++ b/secure/lib/libcrypto/man/man3/OPENSSL_ppccap.3 @@ -0,0 +1,206 @@ +.\" -*- mode: troff; coding: utf-8 -*- +.\" Automatically generated by Pod::Man v6.0.2 (Pod::Simple 3.45) +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. +.ie n \{\ +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds C` +. ds C' +'br\} +.\" +.\" Escape single quotes in literal strings from groff's Unicode transform. +.ie \n(.g .ds Aq \(aq +.el .ds Aq ' +.\" +.\" If the F register is >0, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX +.. +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{\ +. if \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. if !\nF==2 \{\ +. nr % 0 +. nr F 2 +. \} +. \} +.\} +.rr rF +.\" +.\" Required to disable full justification in groff 1.23.0. +.if n .ds AD l +.\" ======================================================================== +.\" +.IX Title "OPENSSL_PPCCAP 3ossl" +.TH OPENSSL_PPCCAP 3ossl 2026-04-07 3.5.6 OpenSSL +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.if n .ad l +.nh +.SH NAME +OPENSSL_ppccap \- the PowerPC processor capabilities vector +.SH SYNOPSIS +.IX Header "SYNOPSIS" +.Vb 1 +\& env OPENSSL_ppccap=... <application> +.Ve +.SH DESCRIPTION +.IX Header "DESCRIPTION" +libcrypto supports PowerPC instruction set extensions. These extensions are +represented by bits in the PowerPC capabilities vector. When libcrypto +initializes, it stores the results returned by PowerPC CPU capabilities detection +logic in the PowerPC capabilities vector. The CPU capabilities detection methods +are OS\-dependent and use a combination of information gathered by the kernel +during boot and probe functions that attempt to execute instructions and trap +illegal instruction signals with a signal handler. +.PP +To override the set of extensions available to an application, you can set the +\&\fBOPENSSL_ppccap\fR environment variable before you start the application. The +environment variable is assigned a numerical value that denotes the bits in +the PowerPC capabilities vector. The ppc_arch.h header file states that, "Flags\*(Aq +usage can appear ambiguous, because they are set rather to reflect OpenSSL +performance preferences than actual processor capabilities." +.PP +Multiple extensions are enabled by logically OR\-ing the values that represent the +desired extensions. +.PP +\&\fBNotes\fR: Enabling an extension on a CPU that does not support the extension +will result in a SIGILL crash. On AIX, all vector instructions can be disabled +with the schedo \-ro allow_vmx=0 command. DO NOT USE THIS COMMAND to disable +vector instructions in the OS when it is running on a CPU level that supports the +instructions without also disabling them in libcrpto via the OPENSSL_ppccap +environment variable or the application will crash with a SIGILL. +.PP +Currently, the following extensions are defined: +.IP 0x01 4 +.IX Item "0x01" +Name: \fBPPC_FPU64\fR +.Sp +This flag is obsolete. +.IP 0x02 4 +.IX Item "0x02" +Name: \fBPPC_ALTIVEC\fR +.Sp +Meaning: Use AltiVec (aka VMX) instructions. In some but not all cases, this +capability gates the use of later ISA vector instructions. The associated probe +instruction is vor (vector logical or). +.Sp +Effect: Enables use of vector instructions but does not enable extensions added +at specific ISA levels. However, disabling this capability disables a subset of +vector extensions added at specific ISA levels even if they are otherwise +enabled. +.IP 0x04 4 +.IX Item "0x04" +Name: \fBPPC_CRYPTO207\fR +.Sp +Meaning: Use instructions added in ISA level 2.07. The associated probe +instruction instruction is vcipher (vector AES cipher round). +.Sp +Effect: Enables AES, SHA\-2 sigma, and other ISA 2.07 instructions for AES, SHA\-2, +GHASH, and Poly1305. +.IP 0x08 4 +.IX Item "0x08" +Name: \fBPPC_FPU\fR +.Sp +Meaning: Use FPU instructions. The associated probe instruction is fmr (floating +move register). +.Sp +Effect: Enables Poly1305 FPU implementation. The PPC_CRYPTO207 capability +overrides this effect. +.IP 0x10 4 +.IX Item "0x10" +Name: \fBPPC_MADD300\fR +.Sp +Meaning: Use instructions added in ISA level 3.00. The associated probe +instruction is maddhdu (multiply\-add high doubleword unsigned). +.Sp +Effect: Enables use of the polynomial multiply and other ISA 3.00 instructions +for AES\-GCM, P\-384, and P\-521. +.IP 0x20 4 +.IX Item "0x20" +Name: \fBPPC_MFTB\fR +.Sp +Meaning: Use the mftb (move from time base) instruction. The associated probe +instruction is mftb. +.Sp +Effect: Enables use of the mftb instruction to sample the lower 32 bits of the +CPU time base register in order to acquire entropy. Considered obsolete. The +PPC_MFSPR268 capability overrides this capability. +.IP 0x40 4 +.IX Item "0x40" +Name: \fBPPC_MFSPR268\fR +.Sp +Meaning: Use the mfspr (move from special purpose register) instruction to +read SPR 268. The associated probe instruction is mfspr 268. +.Sp +Effect: Enables use of the mfspr instruction to sample the lower 32 bits of the +CPU time base register from SPR 268, the TBL (time base lower) register, in order +to acquire entropy. +.IP 0x80 4 +.IX Item "0x80" +Name: \fBPPC_BRD31\fR +.Sp +Meaning: Use instructions added in ISA level 3.1. The associated probe instruction +is brd (byte\-reverse doubleword). +.Sp +Effect: Enables use of ISA 3.1 instructions in ChaCha20. +.SH "RETURN VALUES" +.IX Header "RETURN VALUES" +Not available. +.SH EXAMPLES +.IX Header "EXAMPLES" +Check currently detected capabilities: +.PP +.Vb 2 +\& $ openssl info \-cpusettings +\& OPENSSL_ppccap=0x2E +.Ve +.PP +The detected capabilities in the above example indicate that PPC_MFTB, PPC_FPU, +PPC_CRYPTO207, PPC_MFSPR268, and PPC_ALTIVEC are enabled. +.PP +Disable all instruction set extensions: +.PP +.Vb 1 +\& OPENSSL_ppccap=0x00 +.Ve +.PP +Enable base AltiVec extensions: +.PP +.Vb 1 +\& OPENSSL_ppccap=0x02 +.Ve +.SH COPYRIGHT +.IX Header "COPYRIGHT" +Copyright 2025 The OpenSSL Project Authors. All Rights Reserved. +.PP +Licensed under the Apache License 2.0 (the "License"). You may not use +this file except in compliance with the License. You can obtain a copy +in the file LICENSE in the source distribution or at +<https://www.openssl.org/source/license.html>. |