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+.\" -*- mode: troff; coding: utf-8 -*-
+.\" Automatically generated by Pod::Man v6.0.2 (Pod::Simple 3.45)
+.\"
+.\" Standard preamble:
+.\" ========================================================================
+.de Sp \" Vertical space (when we can't use .PP)
+.if t .sp .5v
+.if n .sp
+..
+.de Vb \" Begin verbatim text
+.ft CW
+.nf
+.ne \\$1
+..
+.de Ve \" End verbatim text
+.ft R
+.fi
+..
+.\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>.
+.ie n \{\
+. ds C` ""
+. ds C' ""
+'br\}
+.el\{\
+. ds C`
+. ds C'
+'br\}
+.\"
+.\" Escape single quotes in literal strings from groff's Unicode transform.
+.ie \n(.g .ds Aq \(aq
+.el .ds Aq '
+.\"
+.\" If the F register is >0, we'll generate index entries on stderr for
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
+.\" entries marked with X<> in POD. Of course, you'll have to process the
+.\" output yourself in some meaningful fashion.
+.\"
+.\" Avoid warning from groff about undefined register 'F'.
+.de IX
+..
+.nr rF 0
+.if \n(.g .if rF .nr rF 1
+.if (\n(rF:(\n(.g==0)) \{\
+. if \nF \{\
+. de IX
+. tm Index:\\$1\t\\n%\t"\\$2"
+..
+. if !\nF==2 \{\
+. nr % 0
+. nr F 2
+. \}
+. \}
+.\}
+.rr rF
+.\"
+.\" Required to disable full justification in groff 1.23.0.
+.if n .ds AD l
+.\" ========================================================================
+.\"
+.IX Title "OPENSSL_RISCVCAP 3ossl"
+.TH OPENSSL_RISCVCAP 3ossl 2026-04-07 3.5.6 OpenSSL
+.\" For nroff, turn off justification. Always turn off hyphenation; it makes
+.\" way too many mistakes in technical documents.
+.if n .ad l
+.nh
+.SH NAME
+OPENSSL_riscvcap \- the RISC\-V processor capabilities vector
+.SH SYNOPSIS
+.IX Header "SYNOPSIS"
+.Vb 1
+\& env OPENSSL_riscvcap=... <application>
+.Ve
+.SH DESCRIPTION
+.IX Header "DESCRIPTION"
+libcrypto supports RISC\-V instruction set extensions. These
+extensions are denoted by individual extension names in the capabilities
+vector. For Linux platform, when libcrypto is initialized, the results
+returned by the RISC\-V Hardware Probing syscall (hwprobe) are stored
+in the vector. Otherwise all capabilities are disabled.
+.PP
+To override the set of instructions available to an application, you can
+set the \fBOPENSSL_riscvcap\fR environment variable before you start the
+application.
+.PP
+The environment variable is similar to the RISC\-V ISA string defined in the
+RISC\-V Instruction Set Manual. It is case insensitive. Though due to the limit
+of the environment variable parser inside libcrypto, an extension must be
+prefixed with an underscore to make it recognizable. This also applies to the
+Vector extension.
+.PP
+.Vb 1
+\& OPENSSL_riscvcap="rv64gc_v_zba_zbb_zbs..."
+.Ve
+.PP
+Note that extension implication is currently not implemented.
+For example, when "rv64gc_b" is provided as the environment variable,
+zba/zbb/zbs would not be implied in the capability vector.
+.PP
+Currently only these extensions are recognized:
+.IP ZBA 4
+.IX Item "ZBA"
+Address Generation
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.5
+.IP ZBB 4
+.IX Item "ZBB"
+Basic bit\-manipulation
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.5
+.IP ZBC 4
+.IX Item "ZBC"
+Carry\-less multiplication
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZBS 4
+.IX Item "ZBS"
+Single\-bit instructions
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.5
+.IP ZBKB 4
+.IX Item "ZBKB"
+Bit\-manipulation for Cryptography
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZBKC 4
+.IX Item "ZBKC"
+Carry\-less multiplication for Cryptography
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZBKX 4
+.IX Item "ZBKX"
+Crossbar permutations
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZKND 4
+.IX Item "ZKND"
+NIST Suite: AES Decryption
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZKNE 4
+.IX Item "ZKNE"
+NIST Suite: AES Encryption
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZKNH 4
+.IX Item "ZKNH"
+NIST Suite: Hash Function Instructions
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZKSED 4
+.IX Item "ZKSED"
+ShangMi Suite: SM4 Block Cipher Instructions
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZKSH 4
+.IX Item "ZKSH"
+ShangMi Suite: SM3 Hash Function Instructions
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZKR 4
+.IX Item "ZKR"
+Entropy Source Extension
+.IP ZKT 4
+.IX Item "ZKT"
+Data Independent Execution Latency
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP V 4
+.IX Item "V"
+Vector Extension for Application Processors
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.5
+.IP ZVBB 4
+.IX Item "ZVBB"
+Vector Basic Bit\-manipulation
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVBC 4
+.IX Item "ZVBC"
+Vector Carryless Multiplication
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKB 4
+.IX Item "ZVKB"
+Vector Cryptography Bit\-manipulation
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKG 4
+.IX Item "ZVKG"
+Vector GCM/GMAC
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKNED 4
+.IX Item "ZVKNED"
+NIST Suite: Vector AES Block Cipher
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKNHA 4
+.IX Item "ZVKNHA"
+NIST Suite: Vector SHA\-2 Secure Hash
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKNHB 4
+.IX Item "ZVKNHB"
+NIST Suite: Vector SHA\-2 Secure Hash
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKSED 4
+.IX Item "ZVKSED"
+ShangMi Suite: SM4 Block Cipher
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.IP ZVKSH 4
+.IX Item "ZVKSH"
+ShangMi Suite: SM3 Secure Hash
+.Sp
+Could be detected using hwprobe for Linux kernel >= 6.8
+.SH "RETURN VALUES"
+.IX Header "RETURN VALUES"
+Not available.
+.SH EXAMPLES
+.IX Header "EXAMPLES"
+Check currently detected capabilities
+.PP
+.Vb 2
+\& $ openssl info \-cpusettings
+\& OPENSSL_riscvcap=RV64GC_ZBA_ZBB_ZBC_ZBS_V vlen:256
+.Ve
+.PP
+Note: The first word in the displayed capabilities is the RISC\-V base
+architecture value, which is derived from the compiler configuration.
+It is therefore not overridable by the environment variable.
+When the V extension is given the riscv_vlen value is always displayed,
+there is no way to override the riscv_vlen by the environment variable.
+.PP
+Disables all instruction set extensions:
+.PP
+.Vb 1
+\& export OPENSSL_riscvcap="rv64gc"
+.Ve
+.PP
+Only enable the vector extension:
+.PP
+.Vb 1
+\& export OPENSSL_riscvcap="rv64gc_v"
+.Ve
+.SH COPYRIGHT
+.IX Header "COPYRIGHT"
+Copyright 2024 The OpenSSL Project Authors. All Rights Reserved.
+.PP
+Licensed under the Apache License 2.0 (the "License"). You may not use
+this file except in compliance with the License. You can obtain a copy
+in the file LICENSE in the source distribution or at
+<https://www.openssl.org/source/license.html>.