12 files changed, 0 insertions, 1783 deletions
diff --git a/sys/arm/altera/socfpga/files.socfpga b/sys/arm/altera/socfpga/files.socfpga
deleted file mode 100644
index 56c1d16f1f46..000000000000
--- a/sys/arm/altera/socfpga/files.socfpga
+++ /dev/null
@@ -1,20 +0,0 @@
-# $FreeBSD$
-
-arm/altera/socfpga/socfpga_common.c		standard
-arm/altera/socfpga/socfpga_machdep.c		standard
-arm/altera/socfpga/socfpga_manager.c		standard
-arm/altera/socfpga/socfpga_rstmgr.c		standard
-arm/altera/socfpga/socfpga_mp.c			optional smp
-
-dev/mmc/host/dwmmc.c				optional dwmmc
-dev/mmc/host/dwmmc_altera.c			optional dwmmc
-
-# Arria 10
-arm/altera/socfpga/socfpga_a10_manager.c	standard
-
-# BERI specific
-dev/beri/beri_ring.c				optional beri_ring
-dev/beri/beri_mem.c				optional beri_mem
-dev/beri/virtio/virtio.c			optional beri_vtblk | vtbe
-dev/beri/virtio/virtio_block.c			optional beri_vtblk
-dev/beri/virtio/network/if_vtbe.c		optional vtbe
diff --git a/sys/arm/altera/socfpga/socfpga_a10_manager.c b/sys/arm/altera/socfpga/socfpga_a10_manager.c
deleted file mode 100644
index 1038b8252c7c..000000000000
--- a/sys/arm/altera/socfpga/socfpga_a10_manager.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/*-
- * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Intel Arria 10 FPGA Manager.
- * Chapter 4, Arria 10 Hard Processor System Technical Reference Manual.
- * Chapter A, FPGA Reconfiguration.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <sys/timeet.h>
-#include <sys/timetc.h>
-#include <sys/conf.h>
-#include <sys/uio.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/intr.h>
-
-#include <arm/altera/socfpga/socfpga_common.h>
-
-#define	FPGAMGR_DCLKCNT			0x8	/* DCLK Count Register */
-#define	FPGAMGR_DCLKSTAT		0xC	/* DCLK Status Register */
-#define	FPGAMGR_GPO			0x10	/* General-Purpose Output Register */
-#define	FPGAMGR_GPI			0x14	/* General-Purpose Input Register */
-#define	FPGAMGR_MISCI			0x18	/* Miscellaneous Input Register */
-#define	IMGCFG_CTRL_00			0x70
-#define	 S2F_CONDONE_OE			(1 << 24)
-#define	 S2F_NSTATUS_OE			(1 << 16)
-#define	 CTRL_00_NCONFIG		(1 << 8)
-#define	 CTRL_00_NENABLE_CONDONE	(1 << 2)
-#define	 CTRL_00_NENABLE_NSTATUS	(1 << 1)
-#define	 CTRL_00_NENABLE_NCONFIG	(1 << 0)
-#define	IMGCFG_CTRL_01			0x74
-#define	 CTRL_01_S2F_NCE		(1 << 24)
-#define	 CTRL_01_S2F_PR_REQUEST		(1 << 16)
-#define	 CTRL_01_S2F_NENABLE_CONFIG	(1 << 0)
-#define	IMGCFG_CTRL_02			0x78
-#define	 CTRL_02_CDRATIO_S		16
-#define	 CTRL_02_CDRATIO_M		(0x3 << CTRL_02_CDRATIO_S)
-#define	 CTRL_02_CFGWIDTH_16		(0 << 24)
-#define	 CTRL_02_CFGWIDTH_32		(1 << 24)
-#define	 CTRL_02_EN_CFG_DATA		(1 << 8)
-#define	 CTRL_02_EN_CFG_CTRL		(1 << 0)
-#define	IMGCFG_STAT			0x80
-#define	 F2S_PR_ERROR			(1 << 11)
-#define	 F2S_PR_DONE			(1 << 10)
-#define	 F2S_PR_READY			(1 << 9)
-#define	 F2S_MSEL_S			16
-#define	 F2S_MSEL_M			(0x7 << F2S_MSEL_S)
-#define	 MSEL_PASSIVE_FAST		0
-#define	 MSEL_PASSIVE_SLOW		1
-#define	 F2S_NCONFIG_PIN		(1 << 12)
-#define	 F2S_CONDONE_OE			(1 << 7)
-#define	 F2S_NSTATUS_PIN		(1 << 4)
-#define	 F2S_CONDONE_PIN		(1 << 6)
-#define	 F2S_USERMODE			(1 << 2)
-
-struct fpgamgr_a10_softc {
-	struct resource		*res[2];
-	bus_space_tag_t		bst_data;
-	bus_space_handle_t	bsh_data;
-	struct cdev		*mgr_cdev;
-	device_t		dev;
-};
-
-static struct resource_spec fpgamgr_a10_spec[] = {
-	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
-	{ SYS_RES_MEMORY,	1,	RF_ACTIVE },
-	{ -1, 0 }
-};
-
-static int
-fpga_wait_dclk_pulses(struct fpgamgr_a10_softc *sc, int npulses)
-{
-	int tout;
-
-	/* Clear done bit, if any */
-	if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
-		WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
-
-	/* Request DCLK pulses */
-	WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
-
-	/* Wait finish */
-	tout = 1000;
-	while (tout > 0) {
-		if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
-			WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
-			break;
-		}
-		tout--;
-		DELAY(10);
-	}
-	if (tout == 0) {
-		device_printf(sc->dev,
-		    "Error: dclkpulses wait timeout\n");
-		return (1);
-	}
-
-	return (0);
-}
-
-static int
-fpga_open(struct cdev *dev, int flags __unused,
-    int fmt __unused, struct thread *td __unused)
-{
-	struct fpgamgr_a10_softc *sc;
-	int tout;
-	int msel;
-	int reg;
-
-	sc = dev->si_drv1;
-
-	/* Step 1 */
-	reg = READ4(sc, IMGCFG_STAT);
-	if ((reg & F2S_USERMODE) == 0) {
-		device_printf(sc->dev, "Error: invalid mode\n");
-		return (ENXIO);
-	};
-
-	/* Step 2 */
-	reg = READ4(sc, IMGCFG_STAT);
-	msel = (reg & F2S_MSEL_M) >> F2S_MSEL_S;
-	if ((msel != MSEL_PASSIVE_FAST) && \
-	    (msel != MSEL_PASSIVE_SLOW)) {
-		device_printf(sc->dev,
-		    "Error: invalid msel %d\n", msel);
-		return (ENXIO);
-	};
-
-	/*
-	 * Step 3.
-	 * TODO: add support for compressed, encrypted images.
-	 */
-	reg = READ4(sc, IMGCFG_CTRL_02);
-	reg &= ~(CTRL_02_CDRATIO_M);
-	WRITE4(sc, IMGCFG_CTRL_02, reg);
-
-	reg = READ4(sc, IMGCFG_CTRL_02);
-	reg &= ~CTRL_02_CFGWIDTH_32;
-	WRITE4(sc, IMGCFG_CTRL_02, reg);
-
-	/* Step 4. a */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg &= ~CTRL_01_S2F_PR_REQUEST;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	reg = READ4(sc, IMGCFG_CTRL_00);
-	reg |= CTRL_00_NCONFIG;
-	WRITE4(sc, IMGCFG_CTRL_00, reg);
-
-	/* b */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg &= ~CTRL_01_S2F_NCE;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	/* c */
-	reg = READ4(sc, IMGCFG_CTRL_02);
-	reg |= CTRL_02_EN_CFG_CTRL;
-	WRITE4(sc, IMGCFG_CTRL_02, reg);
-
-	/* d */
-	reg = READ4(sc, IMGCFG_CTRL_00);
-	reg &= ~S2F_CONDONE_OE;
-	reg &= ~S2F_NSTATUS_OE;
-	reg |= CTRL_00_NCONFIG;
-	reg |= CTRL_00_NENABLE_NSTATUS;
-	reg |= CTRL_00_NENABLE_CONDONE;
-	reg &= ~CTRL_00_NENABLE_NCONFIG;
-	WRITE4(sc, IMGCFG_CTRL_00, reg);
-
-	/* Step 5 */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg &= ~CTRL_01_S2F_NENABLE_CONFIG;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	/* Step 6 */
-	fpga_wait_dclk_pulses(sc, 0x100);
-
-	/* Step 7. a */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg |= CTRL_01_S2F_PR_REQUEST;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	/* b, c */
-	fpga_wait_dclk_pulses(sc, 0x7ff);
-
-	/* Step 8 */
-	tout = 10;
-	while (tout--) {
-		reg = READ4(sc, IMGCFG_STAT);
-		if (reg & F2S_PR_ERROR) {
-			device_printf(sc->dev,
-			    "Error: PR failed on open.\n");
-			return (ENXIO);
-		}
-		if (reg & F2S_PR_READY) {
-			break;
-		}
-	}
-	if (tout == 0) {
-		device_printf(sc->dev,
-		    "Error: Timeout waiting PR ready bit.\n");
-		return (ENXIO);
-	}
-
-	return (0);
-}
-
-static int
-fpga_close(struct cdev *dev, int flags __unused,
-    int fmt __unused, struct thread *td __unused)
-{
-	struct fpgamgr_a10_softc *sc;
-	int tout;
-	int reg;
-
-	sc = dev->si_drv1;
-
-	/* Step 10 */
-	tout = 10;
-	while (tout--) {
-		reg = READ4(sc, IMGCFG_STAT);
-		if (reg & F2S_PR_ERROR) {
-			device_printf(sc->dev,
-			    "Error: PR failed.\n");
-			return (ENXIO);
-		}
-		if (reg & F2S_PR_DONE) {
-			break;
-		}
-	}
-
-	/* Step 11 */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg &= ~CTRL_01_S2F_PR_REQUEST;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	/* Step 12, 13 */
-	fpga_wait_dclk_pulses(sc, 0x100);
-
-	/* Step 14 */
-	reg = READ4(sc, IMGCFG_CTRL_02);
-	reg &= ~CTRL_02_EN_CFG_CTRL;
-	WRITE4(sc, IMGCFG_CTRL_02, reg);
-
-	/* Step 15 */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg |= CTRL_01_S2F_NCE;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	/* Step 16 */
-	reg = READ4(sc, IMGCFG_CTRL_01);
-	reg |= CTRL_01_S2F_NENABLE_CONFIG;
-	WRITE4(sc, IMGCFG_CTRL_01, reg);
-
-	/* Step 17 */
-	reg = READ4(sc, IMGCFG_STAT);
-	if ((reg & F2S_USERMODE) == 0) {
-		device_printf(sc->dev,
-		    "Error: invalid mode\n");
-		return (ENXIO);
-	};
-
-	if ((reg & F2S_CONDONE_PIN) == 0) {
-		device_printf(sc->dev,
-		    "Error: configuration not done\n");
-		return (ENXIO);
-	};
-
-	if ((reg & F2S_NSTATUS_PIN) == 0) {
-		device_printf(sc->dev,
-		    "Error: nstatus pin\n");
-		return (ENXIO);
-	};
-
-	return (0);
-}
-
-static int
-fpga_write(struct cdev *dev, struct uio *uio, int ioflag)
-{
-	struct fpgamgr_a10_softc *sc;
-	uint32_t buffer;
-
-	sc = dev->si_drv1;
-
-	/*
-	 * Step 9.
-	 * Device supports 4-byte writes only.
-	 */
-
-	while (uio->uio_resid >= 4) {
-		uiomove(&buffer, 4, uio);
-		bus_space_write_4(sc->bst_data, sc->bsh_data,
-		    0x0, buffer);
-	}
-
-	switch (uio->uio_resid) {
-	case 3:
-		uiomove(&buffer, 3, uio);
-		buffer &= 0xffffff;
-		bus_space_write_4(sc->bst_data, sc->bsh_data,
-		    0x0, buffer);
-		break;
-	case 2:
-		uiomove(&buffer, 2, uio);
-		buffer &= 0xffff;
-		bus_space_write_4(sc->bst_data, sc->bsh_data,
-		    0x0, buffer);
-		break;
-	case 1:
-		uiomove(&buffer, 1, uio);
-		buffer &= 0xff;
-		bus_space_write_4(sc->bst_data, sc->bsh_data,
-		    0x0, buffer);
-		break;
-	default:
-		break;
-	};
-
-	return (0);
-}
-
-static int
-fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags,
-    struct thread *td)
-{
-
-	return (0);
-}
-
-static struct cdevsw fpga_cdevsw = {
-	.d_version =	D_VERSION,
-	.d_open =	fpga_open,
-	.d_close =	fpga_close,
-	.d_write =	fpga_write,
-	.d_ioctl =	fpga_ioctl,
-	.d_name =	"FPGA Manager",
-};
-
-static int
-fpgamgr_a10_probe(device_t dev)
-{
-
-	if (!ofw_bus_status_okay(dev))
-		return (ENXIO);
-
-	if (!ofw_bus_is_compatible(dev, "altr,socfpga-a10-fpga-mgr"))
-		return (ENXIO);
-
-	device_set_desc(dev, "Arria 10 FPGA Manager");
-
-	return (BUS_PROBE_DEFAULT);
-}
-
-static int
-fpgamgr_a10_attach(device_t dev)
-{
-	struct fpgamgr_a10_softc *sc;
-
-	sc = device_get_softc(dev);
-	sc->dev = dev;
-
-	if (bus_alloc_resources(dev, fpgamgr_a10_spec, sc->res)) {
-		device_printf(dev, "Could not allocate resources.\n");
-		return (ENXIO);
-	}
-
-	/* Memory interface */
-	sc->bst_data = rman_get_bustag(sc->res[1]);
-	sc->bsh_data = rman_get_bushandle(sc->res[1]);
-
-	sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
-	    0600, "fpga%d", device_get_unit(sc->dev));
-
-	if (sc->mgr_cdev == NULL) {
-		device_printf(dev, "Failed to create character device.\n");
-		return (ENXIO);
-	}
-
-	sc->mgr_cdev->si_drv1 = sc;
-
-	return (0);
-}
-
-static device_method_t fpgamgr_a10_methods[] = {
-	DEVMETHOD(device_probe,		fpgamgr_a10_probe),
-	DEVMETHOD(device_attach,	fpgamgr_a10_attach),
-	{ 0, 0 }
-};
-
-static driver_t fpgamgr_a10_driver = {
-	"fpgamgr_a10",
-	fpgamgr_a10_methods,
-	sizeof(struct fpgamgr_a10_softc),
-};
-
-DRIVER_MODULE(fpgamgr_a10, simplebus, fpgamgr_a10_driver, 0, 0);
diff --git a/sys/arm/altera/socfpga/socfpga_common.c b/sys/arm/altera/socfpga/socfpga_common.c
deleted file mode 100644
index 2d466275ff16..000000000000
--- a/sys/arm/altera/socfpga/socfpga_common.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*-
- * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-
-#include <dev/ofw/openfirm.h>
-
-#include <machine/bus.h>
-#include <machine/fdt.h>
-
-#include <arm/altera/socfpga/socfpga_rstmgr.h>
diff --git a/sys/arm/altera/socfpga/socfpga_common.h b/sys/arm/altera/socfpga/socfpga_common.h
deleted file mode 100644
index 2b4e97bbb462..000000000000
--- a/sys/arm/altera/socfpga/socfpga_common.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*-
- * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#define	READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg)
-#define	READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg)
-#define	READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg)
-#define	WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val)
-#define	WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val)
-#define	WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val)
diff --git a/sys/arm/altera/socfpga/socfpga_l3regs.h b/sys/arm/altera/socfpga/socfpga_l3regs.h
deleted file mode 100644
index b4ef6f6d980d..000000000000
--- a/sys/arm/altera/socfpga/socfpga_l3regs.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*-
- * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#define	L3REGS_REMAP		0x0	/* Remap */
-#define	 REMAP_LWHPS2FPGA	(1 << 4)
-#define	 REMAP_HPS2FPGA		(1 << 3)
-#define	 REMAP_MPUZERO		(1 << 0)
-#define	L3REGS_L4MAIN		0x8	/* L4 main peripherals security */
-#define	L3REGS_L4SP		0xC	/* L4 SP Peripherals Security */
-#define	L3REGS_L4MP		0x10	/* L4 MP Peripherals Security */
-#define	L3REGS_L4OSC1		0x14	/* L4 OSC1 Peripherals Security */
-#define	L3REGS_L4SPIM		0x18	/* L4 SPIM Peripherals Security */
-#define	L3REGS_STM		0x1C	/* STM Peripheral Security */
-#define	L3REGS_LWHPS2FPGAREGS	0x20	/* LWHPS2FPGA AXI Bridge Security */
-#define	L3REGS_USB1		0x28	/* USB1 Peripheral Security */
-#define	L3REGS_NANDDATA		0x2C	/* NAND Flash Controller Data Sec */
-#define	L3REGS_USB0		0x80	/* USB0 Peripheral Security */
-#define	L3REGS_NANDREGS		0x84	/* NAND Flash Controller Security */
-#define	L3REGS_QSPIDATA		0x88	/* QSPI Flash Controller Data Sec */
-#define	L3REGS_FPGAMGRDATA	0x8C	/* FPGA Manager Data Peripheral Sec */
-#define	L3REGS_HPS2FPGAREGS	0x90	/* HPS2FPGA AXI Bridge Perip. Sec */
-#define	L3REGS_ACP		0x94	/* MPU ACP Peripheral Security */
-#define	L3REGS_ROM		0x98	/* ROM Peripheral Security */
-#define	L3REGS_OCRAM		0x9C	/* On-chip RAM Peripheral Security */
-#define	L3REGS_SDRDATA		0xA0	/* SDRAM Data Peripheral Security */
diff --git a/sys/arm/altera/socfpga/socfpga_machdep.c b/sys/arm/altera/socfpga/socfpga_machdep.c
deleted file mode 100644
index 4a0d9ecca294..000000000000
--- a/sys/arm/altera/socfpga/socfpga_machdep.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*-
- * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include "opt_platform.h"
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/devmap.h>
-
-#include <vm/vm.h>
-
-#include <dev/ofw/openfirm.h>
-
-#include <machine/armreg.h>
-#include <machine/bus.h>
-#include <machine/fdt.h>
-#include <machine/machdep.h>
-#include <machine/platform.h>
-#include <machine/platformvar.h>
-
-#include <arm/altera/socfpga/socfpga_mp.h>
-#include <arm/altera/socfpga/socfpga_rstmgr.h>
-
-#include "platform_if.h"
-
-#if defined(SOC_ALTERA_CYCLONE5)
-static int
-socfpga_devmap_init(platform_t plat)
-{
-
-	/* UART */
-	devmap_add_entry(0xffc00000, 0x100000);
-
-	/*
-	 * USB OTG
-	 *
-	 * We use static device map for USB due to some bug in the Altera
-	 * which throws Translation Fault (P) exception on high load.
-	 * It might be caused due to some power save options being turned
-	 * on or something else.
-	 */
-	devmap_add_entry(0xffb00000, 0x100000);
-
-	/* dwmmc */
-	devmap_add_entry(0xff700000, 0x100000);
-
-	/* scu */
-	devmap_add_entry(0xfff00000, 0x100000);
-
-	/* FPGA memory window, 256MB */
-	devmap_add_entry(0xd0000000, 0x10000000);
-
-	return (0);
-}
-#endif
-
-#if defined(SOC_ALTERA_ARRIA10)
-static int
-socfpga_a10_devmap_init(platform_t plat)
-{
-
-	/* UART */
-	devmap_add_entry(0xffc00000, 0x100000);
-
-	/* USB OTG */
-	devmap_add_entry(0xffb00000, 0x100000);
-
-	/* dwmmc */
-	devmap_add_entry(0xff800000, 0x100000);
-
-	/* scu */
-	devmap_add_entry(0xfff00000, 0x100000);
-
-	return (0);
-}
-#endif
-
-static void
-_socfpga_cpu_reset(bus_size_t reg)
-{
-	uint32_t paddr;
-	bus_addr_t vaddr;
-	phandle_t node;
-
-	if (rstmgr_warmreset(reg) == 0)
-		goto end;
-
-	node = OF_finddevice("/soc/rstmgr");
-	if (node == -1)
-		goto end;
-
-	if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
-		if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) {
-			bus_space_write_4(fdtbus_bs_tag, vaddr,
-			    reg, CTRL_SWWARMRSTREQ);
-		}
-	}
-
-end:
-	while (1);
-}
-
-#if defined(SOC_ALTERA_CYCLONE5)
-static void
-socfpga_cpu_reset(platform_t plat)
-{
-
-	_socfpga_cpu_reset(RSTMGR_CTRL);
-}
-#endif
-
-#if defined(SOC_ALTERA_ARRIA10)
-static void
-socfpga_a10_cpu_reset(platform_t plat)
-{
-
-	_socfpga_cpu_reset(RSTMGR_A10_CTRL);
-}
-#endif
-
-#if defined(SOC_ALTERA_CYCLONE5)
-static platform_method_t socfpga_methods[] = {
-	PLATFORMMETHOD(platform_devmap_init,	socfpga_devmap_init),
-	PLATFORMMETHOD(platform_cpu_reset,	socfpga_cpu_reset),
-#ifdef SMP
-	PLATFORMMETHOD(platform_mp_setmaxid,	socfpga_mp_setmaxid),
-	PLATFORMMETHOD(platform_mp_start_ap,	socfpga_mp_start_ap),
-#endif
-	PLATFORMMETHOD_END,
-};
-FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
-#endif
-
-#if defined(SOC_ALTERA_ARRIA10)
-static platform_method_t socfpga_a10_methods[] = {
-	PLATFORMMETHOD(platform_devmap_init,	socfpga_a10_devmap_init),
-	PLATFORMMETHOD(platform_cpu_reset,	socfpga_a10_cpu_reset),
-#ifdef SMP
-	PLATFORMMETHOD(platform_mp_setmaxid,	socfpga_mp_setmaxid),
-	PLATFORMMETHOD(platform_mp_start_ap,	socfpga_a10_mp_start_ap),
-#endif
-	PLATFORMMETHOD_END,
-};
-FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);
-#endif
diff --git a/sys/arm/altera/socfpga/socfpga_manager.c b/sys/arm/altera/socfpga/socfpga_manager.c
deleted file mode 100644
index 95a0d1321237..000000000000
--- a/sys/arm/altera/socfpga/socfpga_manager.c
+++ /dev/null
@@ -1,429 +0,0 @@
-/*-
- * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Altera FPGA Manager.
- * Chapter 4, Cyclone V Device Handbook (CV-5V2 2014.07.22)
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <sys/timeet.h>
-#include <sys/timetc.h>
-#include <sys/conf.h>
-#include <sys/uio.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/intr.h>
-
-#include <arm/altera/socfpga/socfpga_common.h>
-
-/* FPGA Manager Module Registers */
-#define	FPGAMGR_STAT		0x0	/* Status Register */
-#define	 STAT_MSEL_MASK		0x1f
-#define	 STAT_MSEL_SHIFT	3
-#define	 STAT_MODE_SHIFT	0
-#define	 STAT_MODE_MASK		0x7
-#define	FPGAMGR_CTRL		0x4	/* Control Register */
-#define	 CTRL_AXICFGEN		(1 << 8)
-#define	 CTRL_CDRATIO_MASK	0x3
-#define	 CTRL_CDRATIO_SHIFT	6
-#define	 CTRL_CFGWDTH_MASK	1
-#define	 CTRL_CFGWDTH_SHIFT	9
-#define	 CTRL_NCONFIGPULL	(1 << 2)
-#define	 CTRL_NCE		(1 << 1)
-#define	 CTRL_EN		(1 << 0)
-#define	FPGAMGR_DCLKCNT		0x8	/* DCLK Count Register */
-#define	FPGAMGR_DCLKSTAT	0xC	/* DCLK Status Register */
-#define	FPGAMGR_GPO		0x10	/* General-Purpose Output Register */
-#define	FPGAMGR_GPI		0x14	/* General-Purpose Input Register */
-#define	FPGAMGR_MISCI		0x18	/* Miscellaneous Input Register */
-
-/* Configuration Monitor (MON) Registers */
-#define	GPIO_INTEN		0x830	/* Interrupt Enable Register */
-#define	GPIO_INTMASK		0x834	/* Interrupt Mask Register */
-#define	GPIO_INTTYPE_LEVEL	0x838	/* Interrupt Level Register */
-#define	GPIO_INT_POLARITY	0x83C	/* Interrupt Polarity Register */
-#define	GPIO_INTSTATUS		0x840	/* Interrupt Status Register */
-#define	GPIO_RAW_INTSTATUS	0x844	/* Raw Interrupt Status Register */
-#define	GPIO_PORTA_EOI		0x84C	/* Clear Interrupt Register */
-#define	 PORTA_EOI_NS		(1 << 0)
-#define	GPIO_EXT_PORTA		0x850	/* External Port A Register */
-#define	 EXT_PORTA_CDP		(1 << 10) /* Configuration done */
-#define	GPIO_LS_SYNC		0x860	/* Synchronization Level Register */
-#define	GPIO_VER_ID_CODE	0x86C	/* GPIO Version Register */
-#define	GPIO_CONFIG_REG2	0x870	/* Configuration Register 2 */
-#define	GPIO_CONFIG_REG1	0x874	/* Configuration Register 1 */
-
-#define	MSEL_PP16_FAST_NOAES_NODC	0x0
-#define	MSEL_PP16_FAST_AES_NODC		0x1
-#define	MSEL_PP16_FAST_AESOPT_DC	0x2
-#define	MSEL_PP16_SLOW_NOAES_NODC	0x4
-#define	MSEL_PP16_SLOW_AES_NODC		0x5
-#define	MSEL_PP16_SLOW_AESOPT_DC	0x6
-#define	MSEL_PP32_FAST_NOAES_NODC	0x8
-#define	MSEL_PP32_FAST_AES_NODC		0x9
-#define	MSEL_PP32_FAST_AESOPT_DC	0xa
-#define	MSEL_PP32_SLOW_NOAES_NODC	0xc
-#define	MSEL_PP32_SLOW_AES_NODC		0xd
-#define	MSEL_PP32_SLOW_AESOPT_DC	0xe
-
-#define	CFGWDTH_16	0
-#define	CFGWDTH_32	1
-
-#define	CDRATIO_1	0
-#define	CDRATIO_2	1
-#define	CDRATIO_4	2
-#define	CDRATIO_8	3
-
-#define	FPGAMGR_MODE_POWEROFF	0x0
-#define	FPGAMGR_MODE_RESET	0x1
-#define	FPGAMGR_MODE_CONFIG	0x2
-#define	FPGAMGR_MODE_INIT	0x3
-#define	FPGAMGR_MODE_USER	0x4
-
-struct cfgmgr_mode {
-	int msel;
-	int cfgwdth;
-	int cdratio;
-};
-
-static struct cfgmgr_mode cfgmgr_modes[] = {
-	{ MSEL_PP16_FAST_NOAES_NODC, CFGWDTH_16, CDRATIO_1 },
-	{ MSEL_PP16_FAST_AES_NODC,   CFGWDTH_16, CDRATIO_2 },
-	{ MSEL_PP16_FAST_AESOPT_DC,  CFGWDTH_16, CDRATIO_4 },
-	{ MSEL_PP16_SLOW_NOAES_NODC, CFGWDTH_16, CDRATIO_1 },
-	{ MSEL_PP16_SLOW_AES_NODC,   CFGWDTH_16, CDRATIO_2 },
-	{ MSEL_PP16_SLOW_AESOPT_DC,  CFGWDTH_16, CDRATIO_4 },
-	{ MSEL_PP32_FAST_NOAES_NODC, CFGWDTH_32, CDRATIO_1 },
-	{ MSEL_PP32_FAST_AES_NODC,   CFGWDTH_32, CDRATIO_4 },
-	{ MSEL_PP32_FAST_AESOPT_DC,  CFGWDTH_32, CDRATIO_8 },
-	{ MSEL_PP32_SLOW_NOAES_NODC, CFGWDTH_32, CDRATIO_1 },
-	{ MSEL_PP32_SLOW_AES_NODC,   CFGWDTH_32, CDRATIO_4 },
-	{ MSEL_PP32_SLOW_AESOPT_DC,  CFGWDTH_32, CDRATIO_8 },
-	{ -1, -1, -1 },
-};
-
-struct fpgamgr_softc {
-	struct resource		*res[3];
-	bus_space_tag_t		bst_data;
-	bus_space_handle_t	bsh_data;
-	struct cdev		*mgr_cdev;
-	device_t		dev;
-};
-
-static struct resource_spec fpgamgr_spec[] = {
-	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
-	{ SYS_RES_MEMORY,	1,	RF_ACTIVE },
-	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
-	{ -1, 0 }
-};
-
-static int
-fpgamgr_state_get(struct fpgamgr_softc *sc)
-{
-	int reg;
-
-	reg = READ4(sc, FPGAMGR_STAT);
-	reg >>= STAT_MODE_SHIFT;
-	reg &= STAT_MODE_MASK;
-
-	return reg;
-}
-
-static int
-fpgamgr_state_wait(struct fpgamgr_softc *sc, int state)
-{
-	int tout;
-
-	tout = 1000;
-	while (tout > 0) {
-		if (fpgamgr_state_get(sc) == state)
-			break;
-		tout--;
-		DELAY(10);
-	}
-	if (tout == 0) {
-		return (1);
-	}
-
-	return (0);
-}
-
-static int
-fpga_open(struct cdev *dev, int flags __unused,
-    int fmt __unused, struct thread *td __unused)
-{
-	struct fpgamgr_softc *sc;
-	struct cfgmgr_mode *mode;
-	int msel;
-	int reg;
-	int i;
-
-	sc = dev->si_drv1;
-
-	msel = READ4(sc, FPGAMGR_STAT);
-	msel >>= STAT_MSEL_SHIFT;
-	msel &= STAT_MSEL_MASK;
-
-	mode = NULL;
-	for (i = 0; cfgmgr_modes[i].msel != -1; i++) {
-		if (msel == cfgmgr_modes[i].msel) {
-			mode = &cfgmgr_modes[i];
-			break;
-		}
-	}
-	if (mode == NULL) {
-		device_printf(sc->dev, "Can't configure: unknown mode\n");
-		return (ENXIO);
-	}
-
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg &= ~(CTRL_CDRATIO_MASK << CTRL_CDRATIO_SHIFT);
-	reg |= (mode->cdratio << CTRL_CDRATIO_SHIFT);
-	reg &= ~(CTRL_CFGWDTH_MASK << CTRL_CFGWDTH_SHIFT);
-	reg |= (mode->cfgwdth << CTRL_CFGWDTH_SHIFT);
-	reg &= ~(CTRL_NCE);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	/* Enable configuration */
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg |= (CTRL_EN);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	/* Reset FPGA */
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg |= (CTRL_NCONFIGPULL);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	/* Wait reset state */
-	if (fpgamgr_state_wait(sc, FPGAMGR_MODE_RESET)) {
-		device_printf(sc->dev, "Can't get RESET state\n");
-		return (ENXIO);
-	}
-
-	/* Release from reset */
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg &= ~(CTRL_NCONFIGPULL);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	if (fpgamgr_state_wait(sc, FPGAMGR_MODE_CONFIG)) {
-		device_printf(sc->dev, "Can't get CONFIG state\n");
-		return (ENXIO);
-	}
-
-	/* Clear nSTATUS edge interrupt */
-	WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS);
-
-	/* Enter configuration state */
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg |= (CTRL_AXICFGEN);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	return (0);
-}
-
-static int
-fpga_wait_dclk_pulses(struct fpgamgr_softc *sc, int npulses)
-{
-	int tout;
-
-	/* Clear done bit, if any */
-	if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
-		WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
-
-	/* Request DCLK pulses */
-	WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
-
-	/* Wait finish */
-	tout = 1000;
-	while (tout > 0) {
-		if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
-			WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
-			break;
-		}
-		tout--;
-		DELAY(10);
-	}
-	if (tout == 0) {
-		return (1);
-	}
-
-	return (0);
-}
-
-static int
-fpga_close(struct cdev *dev, int flags __unused,
-    int fmt __unused, struct thread *td __unused)
-{
-	struct fpgamgr_softc *sc;
-	int reg;
-
-	sc = dev->si_drv1;
-
-	reg = READ4(sc, GPIO_EXT_PORTA);
-	if ((reg & EXT_PORTA_CDP) == 0) {
-		device_printf(sc->dev, "Err: configuration failed\n");
-		return (ENXIO);
-	}
-
-	/* Exit configuration state */
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg &= ~(CTRL_AXICFGEN);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	/* Wait dclk pulses */
-	if (fpga_wait_dclk_pulses(sc, 4)) {
-		device_printf(sc->dev, "Can't proceed 4 dclk pulses\n");
-		return (ENXIO);
-	}
-
-	if (fpgamgr_state_wait(sc, FPGAMGR_MODE_USER)) {
-		device_printf(sc->dev, "Can't get USER mode\n");
-		return (ENXIO);
-	}
-
-	/* Disable configuration */
-	reg = READ4(sc, FPGAMGR_CTRL);
-	reg &= ~(CTRL_EN);
-	WRITE4(sc, FPGAMGR_CTRL, reg);
-
-	return (0);
-}
-
-static int
-fpga_write(struct cdev *dev, struct uio *uio, int ioflag)
-{
-	struct fpgamgr_softc *sc;
-	int buffer;
-
-	sc = dev->si_drv1;
-
-	/*
-	 * Device supports 4-byte copy only.
-	 * TODO: add padding for <4 bytes.
-	 */
-
-	while (uio->uio_resid > 0) {
-		uiomove(&buffer, 4, uio);
-		bus_space_write_4(sc->bst_data, sc->bsh_data,
-		    0x0, buffer);
-	}
-
-	return (0);
-}
-
-static int
-fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags,
-    struct thread *td)
-{
-
-	return (0);
-}
-
-static struct cdevsw fpga_cdevsw = {
-	.d_version =	D_VERSION,
-	.d_open =	fpga_open,
-	.d_close =	fpga_close,
-	.d_write =	fpga_write,
-	.d_ioctl =	fpga_ioctl,
-	.d_name =	"FPGA Manager",
-};
-
-static int
-fpgamgr_probe(device_t dev)
-{
-
-	if (!ofw_bus_status_okay(dev))
-		return (ENXIO);
-
-	if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr"))
-		return (ENXIO);
-
-	device_set_desc(dev, "FPGA Manager");
-	return (BUS_PROBE_DEFAULT);
-}
-
-static int
-fpgamgr_attach(device_t dev)
-{
-	struct fpgamgr_softc *sc;
-
-	sc = device_get_softc(dev);
-	sc->dev = dev;
-
-	if (bus_alloc_resources(dev, fpgamgr_spec, sc->res)) {
-		device_printf(dev, "could not allocate resources\n");
-		return (ENXIO);
-	}
-
-	/* Memory interface */
-	sc->bst_data = rman_get_bustag(sc->res[1]);
-	sc->bsh_data = rman_get_bushandle(sc->res[1]);
-
-	sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
-	    0600, "fpga%d", device_get_unit(sc->dev));
-
-	if (sc->mgr_cdev == NULL) {
-		device_printf(dev, "Failed to create character device.\n");
-		return (ENXIO);
-	}
-
-	sc->mgr_cdev->si_drv1 = sc;
-
-	return (0);
-}
-
-static device_method_t fpgamgr_methods[] = {
-	DEVMETHOD(device_probe,		fpgamgr_probe),
-	DEVMETHOD(device_attach,	fpgamgr_attach),
-	{ 0, 0 }
-};
-
-static driver_t fpgamgr_driver = {
-	"fpgamgr",
-	fpgamgr_methods,
-	sizeof(struct fpgamgr_softc),
-};
-
-DRIVER_MODULE(fpgamgr, simplebus, fpgamgr_driver, 0, 0);
diff --git a/sys/arm/altera/socfpga/socfpga_mp.c b/sys/arm/altera/socfpga/socfpga_mp.c
deleted file mode 100644
index 2b3a6dfe61c7..000000000000
--- a/sys/arm/altera/socfpga/socfpga_mp.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*-
- * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include "opt_platform.h"
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/smp.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-
-#include <machine/cpu.h>
-#include <machine/smp.h>
-#include <machine/fdt.h>
-#include <machine/intr.h>
-#include <machine/platformvar.h>
-
-#include <arm/altera/socfpga/socfpga_mp.h>
-#include <arm/altera/socfpga/socfpga_rstmgr.h>
-
-#define	SCU_PHYSBASE			0xFFFEC000
-#define	SCU_PHYSBASE_A10		0xFFFFC000
-#define	SCU_SIZE			0x100
-
-#define	SCU_CONTROL_REG			0x00
-#define	 SCU_CONTROL_ENABLE		(1 << 0)
-#define	SCU_CONFIG_REG			0x04
-#define	 SCU_CONFIG_REG_NCPU_MASK	0x03
-#define	SCU_CPUPOWER_REG		0x08
-#define	SCU_INV_TAGS_REG		0x0c
-#define	SCU_DIAG_CONTROL		0x30
-#define	 SCU_DIAG_DISABLE_MIGBIT	(1 << 0)
-#define	SCU_FILTER_START_REG		0x40
-#define	SCU_FILTER_END_REG		0x44
-#define	SCU_SECURE_ACCESS_REG		0x50
-#define	SCU_NONSECURE_ACCESS_REG	0x54
-
-#define	RSTMGR_PHYSBASE			0xFFD05000
-#define	RSTMGR_SIZE			0x100
-
-#define	RAM_PHYSBASE			0x0
-#define	RAM_SIZE			0x1000
-
-#define	SOCFPGA_ARRIA10			1
-#define	SOCFPGA_CYCLONE5		2
-
-extern char	*mpentry_addr;
-static void	socfpga_trampoline(void);
-
-static void
-socfpga_trampoline(void)
-{
-
-	__asm __volatile(
-			"ldr pc, 1f\n"
-			".globl mpentry_addr\n"
-			"mpentry_addr:\n"
-			"1: .space 4\n");
-}
-
-void
-socfpga_mp_setmaxid(platform_t plat)
-{
-	int hwcpu, ncpu;
-
-	/* If we've already set this don't bother to do it again. */
-	if (mp_ncpus != 0)
-		return;
-
-	hwcpu = 2;
-
-	ncpu = hwcpu;
-	TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
-	if (ncpu < 1 || ncpu > hwcpu)
-		ncpu = hwcpu;
-
-	mp_ncpus = ncpu;
-	mp_maxid = ncpu - 1;
-}
-
-static void
-_socfpga_mp_start_ap(uint32_t platid)
-{
-	bus_space_handle_t scu, rst, ram;
-	int reg;
-
-	switch (platid) {
-#if defined(SOC_ALTERA_ARRIA10)
-	case SOCFPGA_ARRIA10:
-		if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
-		    SCU_SIZE, 0, &scu) != 0)
-			panic("Couldn't map the SCU\n");
-		break;
-#endif
-#if defined(SOC_ALTERA_CYCLONE5)
-	case SOCFPGA_CYCLONE5:
-		if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
-		    SCU_SIZE, 0, &scu) != 0)
-			panic("Couldn't map the SCU\n");
-		break;
-#endif
-	default:
-		panic("Unknown platform id %d\n", platid);
-	}
-
-	if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
-					RSTMGR_SIZE, 0, &rst) != 0)
-		panic("Couldn't map the reset manager (RSTMGR)\n");
-	if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
-					RAM_SIZE, 0, &ram) != 0)
-		panic("Couldn't map the first physram page\n");
-
-	/* Invalidate SCU cache tags */
-	bus_space_write_4(fdtbus_bs_tag, scu,
-		SCU_INV_TAGS_REG, 0x0000ffff);
-
-	/*
-	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
-	 * Setting the "disable-migratory bit" in the undocumented SCU
-	 * Diagnostic Control Register helps work around the problem.
-	 */
-	reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
-	reg |= (SCU_DIAG_DISABLE_MIGBIT);
-	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
-
-	/* Put CPU1 to reset state */
-	switch (platid) {
-#if defined(SOC_ALTERA_ARRIA10)
-	case SOCFPGA_ARRIA10:
-		bus_space_write_4(fdtbus_bs_tag, rst,
-		    RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
-		break;
-#endif
-#if defined(SOC_ALTERA_CYCLONE5)
-	case SOCFPGA_CYCLONE5:
-		bus_space_write_4(fdtbus_bs_tag, rst,
-		    RSTMGR_MPUMODRST, MPUMODRST_CPU1);
-		break;
-#endif
-	default:
-		panic("Unknown platform id %d\n", platid);
-	}
-
-	/* Enable the SCU, then clean the cache on this core */
-	reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
-	reg |= (SCU_CONTROL_ENABLE);
-	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
-
-	/* Set up trampoline code */
-	mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
-	bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
-	    (uint32_t *)&socfpga_trampoline, 8);
-
-	dcache_wbinv_poc_all();
-
-	/* Put CPU1 out from reset */
-	switch (platid) {
-#if defined(SOC_ALTERA_ARRIA10)
-	case SOCFPGA_ARRIA10:
-		bus_space_write_4(fdtbus_bs_tag, rst,
-		    RSTMGR_A10_MPUMODRST, 0);
-		break;
-#endif
-#if defined(SOC_ALTERA_CYCLONE5)
-	case SOCFPGA_CYCLONE5:
-		bus_space_write_4(fdtbus_bs_tag, rst,
-		    RSTMGR_MPUMODRST, 0);
-		break;
-#endif
-	default:
-		panic("Unknown platform id %d\n", platid);
-	}
-
-	dsb();
-	sev();
-
-	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
-	bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
-	bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
-}
-
-#if defined(SOC_ALTERA_ARRIA10)
-void
-socfpga_a10_mp_start_ap(platform_t plat)
-{
-
-	_socfpga_mp_start_ap(SOCFPGA_ARRIA10);
-}
-#endif
-
-#if defined(SOC_ALTERA_CYCLONE5)
-void
-socfpga_mp_start_ap(platform_t plat)
-{
-
-	_socfpga_mp_start_ap(SOCFPGA_CYCLONE5);
-}
-#endif
diff --git a/sys/arm/altera/socfpga/socfpga_mp.h b/sys/arm/altera/socfpga/socfpga_mp.h
deleted file mode 100644
index bf3014d4983d..000000000000
--- a/sys/arm/altera/socfpga/socfpga_mp.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*-
- * Copyright (c) 2017 Andrew Turner <andrew@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _SOCFPGA_MP_H_
-#define	_SOCFPGA_MP_H_
-
-void socfpga_mp_setmaxid(platform_t);
-void socfpga_mp_start_ap(platform_t);
-void socfpga_a10_mp_start_ap(platform_t);
-
-#endif /* _SOCFPGA_MP_H_ */
diff --git a/sys/arm/altera/socfpga/socfpga_rstmgr.c b/sys/arm/altera/socfpga/socfpga_rstmgr.c
deleted file mode 100644
index 7633fcdccae1..000000000000
--- a/sys/arm/altera/socfpga/socfpga_rstmgr.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*-
- * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * SOCFPGA Reset Manager.
- * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22)
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <sys/timeet.h>
-#include <sys/timetc.h>
-#include <sys/sysctl.h>
-
-#include <dev/ofw/openfirm.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include <machine/bus.h>
-#include <machine/fdt.h>
-#include <machine/cpu.h>
-#include <machine/intr.h>
-
-#include <arm/altera/socfpga/socfpga_common.h>
-#include <arm/altera/socfpga/socfpga_rstmgr.h>
-#include <arm/altera/socfpga/socfpga_l3regs.h>
-
-struct rstmgr_softc {
-	struct resource		*res[1];
-	bus_space_tag_t		bst;
-	bus_space_handle_t	bsh;
-	device_t		dev;
-};
-
-struct rstmgr_softc *rstmgr_sc;
-
-static struct resource_spec rstmgr_spec[] = {
-	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
-	{ -1, 0 }
-};
-
-enum {
-	RSTMGR_SYSCTL_FPGA2HPS,
-	RSTMGR_SYSCTL_LWHPS2FPGA,
-	RSTMGR_SYSCTL_HPS2FPGA
-};
-
-static int
-l3remap(struct rstmgr_softc *sc, int remap, int enable)
-{
-	uint32_t paddr;
-	bus_addr_t vaddr;
-	phandle_t node;
-	int reg;
-
-	/*
-	 * Control whether bridge is visible to L3 masters or not.
-	 * Register is write-only.
-	 */
-
-	reg = REMAP_MPUZERO;
-	if (enable)
-		reg |= (remap);
-	else
-		reg &= ~(remap);
-
-	node = OF_finddevice("l3regs");
-	if (node == -1) {
-		device_printf(sc->dev, "Can't find l3regs node\n");
-		return (1);
-	}
-
-	if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
-		if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) {
-			bus_space_write_4(fdtbus_bs_tag, vaddr,
-			    L3REGS_REMAP, reg);
-			return (0);
-		}
-	}
-
-	return (1);
-}
-
-static int
-rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
-{
-	struct rstmgr_softc *sc;
-	int enable;
-	int remap;
-	int err;
-	int reg;
-	int bit;
-
-	sc = arg1;
-
-	switch (arg2) {
-	case RSTMGR_SYSCTL_FPGA2HPS:
-		bit = BRGMODRST_FPGA2HPS;
-		remap = 0;
-		break;
-	case RSTMGR_SYSCTL_LWHPS2FPGA:
-		bit = BRGMODRST_LWHPS2FPGA;
-		remap = REMAP_LWHPS2FPGA;
-		break;
-	case RSTMGR_SYSCTL_HPS2FPGA:
-		bit = BRGMODRST_HPS2FPGA;
-		remap = REMAP_HPS2FPGA;
-		break;
-	default:
-		return (1);
-	}
-
-	reg = READ4(sc, RSTMGR_BRGMODRST);
-	enable = reg & bit ? 0 : 1;
-
-	err = sysctl_handle_int(oidp, &enable, 0, req);
-	if (err || !req->newptr)
-		return (err);
-
-	if (enable == 1)
-		reg &= ~(bit);
-	else if (enable == 0)
-		reg |= (bit);
-	else
-		return (EINVAL);
-
-	WRITE4(sc, RSTMGR_BRGMODRST, reg);
-	l3remap(sc, remap, enable);
-
-	return (0);
-}
-
-int
-rstmgr_warmreset(uint32_t reg)
-{
-	struct rstmgr_softc *sc;
-
-	sc = rstmgr_sc;
-	if (sc == NULL)
-		return (1);
-
-	/* Request warm reset */
-	WRITE4(sc, reg, CTRL_SWWARMRSTREQ);
-
-	return (0);
-}
-
-static int
-rstmgr_add_sysctl(struct rstmgr_softc *sc)
-{
-	struct sysctl_oid_list *children;
-	struct sysctl_ctx_list *ctx;
-
-	ctx = device_get_sysctl_ctx(sc->dev);
-	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
-
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps",
-	    CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
-	    sc, RSTMGR_SYSCTL_FPGA2HPS,
-	    rstmgr_sysctl, "I", "Enable fpga2hps bridge");
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga",
-	    CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
-	    sc, RSTMGR_SYSCTL_LWHPS2FPGA,
-	    rstmgr_sysctl, "I", "Enable lwhps2fpga bridge");
-	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga",
-	    CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
-	    sc, RSTMGR_SYSCTL_HPS2FPGA,
-	    rstmgr_sysctl, "I", "Enable hps2fpga bridge");
-
-	return (0);
-}
-
-static int
-rstmgr_probe(device_t dev)
-{
-
-	if (!ofw_bus_status_okay(dev))
-		return (ENXIO);
-
-	if (!ofw_bus_is_compatible(dev, "altr,rst-mgr"))
-		return (ENXIO);
-
-	device_set_desc(dev, "Reset Manager");
-
-	return (BUS_PROBE_DEFAULT);
-}
-
-static int
-rstmgr_attach(device_t dev)
-{
-	struct rstmgr_softc *sc;
-
-	sc = device_get_softc(dev);
-	sc->dev = dev;
-
-	if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) {
-		device_printf(dev, "could not allocate resources\n");
-		return (ENXIO);
-	}
-
-	/* Memory interface */
-	sc->bst = rman_get_bustag(sc->res[0]);
-	sc->bsh = rman_get_bushandle(sc->res[0]);
-
-	rstmgr_sc = sc;
-	rstmgr_add_sysctl(sc);
-
-	return (0);
-}
-
-static device_method_t rstmgr_methods[] = {
-	DEVMETHOD(device_probe,		rstmgr_probe),
-	DEVMETHOD(device_attach,	rstmgr_attach),
-	{ 0, 0 }
-};
-
-static driver_t rstmgr_driver = {
-	"rstmgr",
-	rstmgr_methods,
-	sizeof(struct rstmgr_softc),
-};
-
-DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, 0, 0);
diff --git a/sys/arm/altera/socfpga/socfpga_rstmgr.h b/sys/arm/altera/socfpga/socfpga_rstmgr.h
deleted file mode 100644
index 1980bcf393f6..000000000000
--- a/sys/arm/altera/socfpga/socfpga_rstmgr.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*-
- * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
- * All rights reserved.
- *
- * This software was developed by SRI International and the University of
- * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
- * ("CTSRD"), as part of the DARPA CRASH research programme.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#define	RSTMGR_STAT		0x0	/* Status */
-#define	RSTMGR_CTRL		0x4	/* Control */
-#define	 CTRL_SWWARMRSTREQ	(1 << 1) /* Trigger warm reset */
-#define	RSTMGR_COUNTS		0x8	/* Reset Cycles Count */
-#define	RSTMGR_MPUMODRST	0x10	/* MPU Module Reset */
-#define	 MPUMODRST_CPU1			(1 << 1)
-#define	RSTMGR_PERMODRST	0x14	/* Peripheral Module Reset */
-#define	RSTMGR_PER2MODRST	0x18	/* Peripheral 2 Module Reset */
-#define	RSTMGR_BRGMODRST	0x1C	/* Bridge Module Reset */
-#define	 BRGMODRST_FPGA2HPS	(1 << 2)
-#define	 BRGMODRST_LWHPS2FPGA	(1 << 1)
-#define	 BRGMODRST_HPS2FPGA	(1 << 0)
-#define	RSTMGR_MISCMODRST	0x20	/* Miscellaneous Module Reset */
-
-#define	RSTMGR_A10_CTRL		0xC	/* Control */
-#define	RSTMGR_A10_MPUMODRST	0x20	/* MPU Module Reset */
-
-int rstmgr_warmreset(uint32_t reg);
diff --git a/sys/arm/altera/socfpga/std.socfpga b/sys/arm/altera/socfpga/std.socfpga
deleted file mode 100644
index dc5cf704640b..000000000000
--- a/sys/arm/altera/socfpga/std.socfpga
+++ /dev/null
@@ -1,7 +0,0 @@
-# $FreeBSD$
-
-cpu		CPU_CORTEXA
-machine		arm armv7
-makeoptions	CONF_CFLAGS="-march=armv7a"
-
-files		"../altera/socfpga/files.socfpga"