diff options
Diffstat (limited to 'sys/arm/xscale/i8134x')
22 files changed, 0 insertions, 4170 deletions
diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c deleted file mode 100644 index 93687efd7e13..000000000000 --- a/sys/arm/xscale/i8134x/crb_machdep.c +++ /dev/null @@ -1,333 +0,0 @@ -/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994-1998 Mark Brinicombe. - * Copyright (c) 1994 Brini. - * All rights reserved. - * - * This code is derived from software written for Brini by Mark Brinicombe - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Brini. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RiscBSD kernel project - * - * machdep.c - * - * Machine dependent functions for kernel setup - * - * This file needs a lot of work. - * - * Created : 17/09/94 - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include "opt_kstack_pages.h" - -#define _ARM32_BUS_DMA_PRIVATE -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/sysproto.h> -#include <sys/signalvar.h> -#include <sys/imgact.h> -#include <sys/kernel.h> -#include <sys/ktr.h> -#include <sys/linker.h> -#include <sys/lock.h> -#include <sys/malloc.h> -#include <sys/mutex.h> -#include <sys/pcpu.h> -#include <sys/proc.h> -#include <sys/ptrace.h> -#include <sys/cons.h> -#include <sys/bio.h> -#include <sys/bus.h> -#include <sys/buf.h> -#include <sys/exec.h> -#include <sys/kdb.h> -#include <sys/msgbuf.h> -#include <sys/devmap.h> -#include <machine/reg.h> -#include <machine/cpu.h> - -#include <vm/vm.h> -#include <vm/pmap.h> -#include <vm/vm_object.h> -#include <vm/vm_page.h> -#include <vm/vm_map.h> -#include <machine/vmparam.h> -#include <machine/pcb.h> -#include <machine/undefined.h> -#include <machine/machdep.h> -#include <machine/metadata.h> -#include <machine/armreg.h> -#include <machine/bus.h> -#include <machine/physmem.h> -#include <sys/reboot.h> - - -#include <arm/xscale/i8134x/i80321var.h> /* For i80321_calibrate_delay() */ - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/i81342var.h> -#include <arm/xscale/i8134x/obiovar.h> - - -#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ -#define KERNEL_PT_IOPXS 1 -#define KERNEL_PT_BEFOREKERN 2 -#define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */ -#define KERNEL_PT_AFKERNEL_NUM 9 - -/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ -#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) - -struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; - -/* Physical and virtual addresses for some global pages */ - -struct pv_addr systempage; -struct pv_addr msgbufpv; -struct pv_addr irqstack; -struct pv_addr undstack; -struct pv_addr abtstack; -struct pv_addr kernelstack; - -/* Static device mappings. */ -static const struct devmap_entry iq81342_devmap[] = { - { - IOP34X_VADDR, - IOP34X_HWADDR, - IOP34X_SIZE, - }, - { - /* - * Cheat and map a whole section, this will bring - * both PCI-X and PCI-E outbound I/O - */ - rounddown2(IOP34X_PCIX_OIOBAR_VADDR, 0x100000), - rounddown2(IOP34X_PCIX_OIOBAR, 0x100000), - 0x100000, - }, - { - IOP34X_PCE1_VADDR, - IOP34X_PCE1, - IOP34X_PCE1_SIZE, - }, - { - 0, - 0, - 0, - } -}; - -#define SDRAM_START 0x00000000 - -extern vm_offset_t xscale_cache_clean_addr; - -void * -initarm(struct arm_boot_params *abp) -{ - struct pv_addr kernel_l1pt; - struct pv_addr dpcpu; - int loop, i; - u_int l1pagetable; - vm_offset_t freemempos; - vm_offset_t freemem_pt; - vm_offset_t afterkern; - vm_offset_t freemem_after; - vm_offset_t lastaddr; - uint32_t memsize, memstart; - - lastaddr = parse_boot_param(abp); - arm_physmem_kernaddr = abp->abp_physaddr; - set_cpufuncs(); - pcpu_init(pcpup, 0, sizeof(struct pcpu)); - PCPU_SET(curthread, &thread0); - - /* Do basic tuning, hz etc */ - init_param1(); - - freemempos = 0x00200000; - /* Define a macro to simplify memory allocation */ -#define valloc_pages(var, np) \ - alloc_pages((var).pv_pa, (np)); \ - (var).pv_va = (var).pv_pa + 0xc0000000; - -#define alloc_pages(var, np) \ - freemempos -= (np * PAGE_SIZE); \ - (var) = freemempos; \ - memset((char *)(var), 0, ((np) * PAGE_SIZE)); - - while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) - freemempos -= PAGE_SIZE; - valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); - for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { - if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { - valloc_pages(kernel_pt_table[loop], - L2_TABLE_SIZE / PAGE_SIZE); - } else { - kernel_pt_table[loop].pv_pa = freemempos + - (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * - L2_TABLE_SIZE_REAL; - kernel_pt_table[loop].pv_va = - kernel_pt_table[loop].pv_pa + 0xc0000000; - } - } - freemem_pt = freemempos; - freemempos = 0x00100000; - /* - * Allocate a page for the system page mapped to V0x00000000 - * This page will just contain the system vectors and can be - * shared by all processes. - */ - valloc_pages(systempage, 1); - - /* Allocate dynamic per-cpu area. */ - valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); - dpcpu_init((void *)dpcpu.pv_va, 0); - - /* Allocate stacks for all modes */ - valloc_pages(irqstack, IRQ_STACK_SIZE); - valloc_pages(abtstack, ABT_STACK_SIZE); - valloc_pages(undstack, UND_STACK_SIZE); - valloc_pages(kernelstack, kstack_pages); - valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); - /* - * Now we start construction of the L1 page table - * We start by mapping the L2 page tables into the L1. - * This means that we can replace L1 mappings later on if necessary - */ - l1pagetable = kernel_l1pt.pv_va; - - /* Map the L2 pages tables in the L1 page table */ - pmap_link_l2pt(l1pagetable, rounddown2(ARM_VECTORS_HIGH, 0x00100000), - &kernel_pt_table[KERNEL_PT_SYS]); - pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - - pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000, - 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - - pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000, - rounddown2(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE, L1_S_SIZE), - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - freemem_after = rounddown2((int)lastaddr + PAGE_SIZE, PAGE_SIZE); - afterkern = round_page(rounddown2((vm_offset_t)lastaddr + L1_S_SIZE, L1_S_SIZE)); - for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { - pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, - &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); - } - - - /* Map the vector page. */ - pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - devmap_bootstrap(l1pagetable, iq81342_devmap); - /* - * Give the XScale global cache clean code an appropriately - * sized chunk of unmapped VA space starting at 0xff000000 - * (our device mappings end before this address). - */ - xscale_cache_clean_addr = 0xff000000U; - - cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - cpu_setttb(kernel_l1pt.pv_pa); - cpu_tlb_flushID(); - cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); - /* - * Pages were allocated during the secondary bootstrap for the - * stacks for different CPU modes. - * We must now set the r13 registers in the different CPU modes to - * point to these stacks. - * Since the ARM stacks use STMFD etc. we must set r13 to the top end - * of the stack memory. - */ - - set_stackptrs(0); - - /* - * We must now clean the cache again.... - * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in cpu_setttb() - * but since we are boot strapping the addresses used for the read - * may have just been remapped and thus the cache could be out - * of sync. A re-clean after the switch will cure this. - * After booting there are no gross relocations of the kernel thus - * this problem will not occur after initarm(). - */ - cpu_idcache_wbinv_all(); - cpu_setup(); - - i80321_calibrate_delay(); - i81342_sdram_bounds(arm_base_bs_tag, IOP34X_VADDR, &memstart, &memsize); - physmem = memsize / PAGE_SIZE; - cninit(); - /* Set stack for exception handlers */ - - undefined_init(); - - init_proc0(kernelstack.pv_va); - - arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); - - pmap_curmaxkvaddr = afterkern + PAGE_SIZE; - - vm_max_kernel_address = 0xe0000000; - pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); - msgbufp = (void*)msgbufpv.pv_va; - msgbufinit(msgbufp, msgbufsize); - mutex_init(); - - /* - * Add the physical ram we have available. - * - * Exclude the kernel (and all the things we allocated which immediately - * follow the kernel) from the VM allocation pool but not from crash - * dumps. virtual_avail is a global variable which tracks the kva we've - * "allocated" while setting up pmaps. - * - * Prepare the list of physical memory available to the vm subsystem. - */ - arm_physmem_hardware_region(SDRAM_START, memsize); - arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr - - freemem_pt, EXFLAG_NOALLOC); - arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 - - freemempos, EXFLAG_NOALLOC); - arm_physmem_exclude_region(abp->abp_physaddr, - virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); - arm_physmem_init_kernel_globals(); - - init_param2(physmem); - kdb_init(); - return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - - sizeof(struct pcb))); -} diff --git a/sys/arm/xscale/i8134x/files.crb b/sys/arm/xscale/i8134x/files.crb deleted file mode 100644 index 25398af60f95..000000000000 --- a/sys/arm/xscale/i8134x/files.crb +++ /dev/null @@ -1,3 +0,0 @@ -# $FreeBSD$ -arm/xscale/i8134x/crb_machdep.c standard -arm/xscale/i8134x/iq81342_7seg.c optional 7seg diff --git a/sys/arm/xscale/i8134x/files.i81342 b/sys/arm/xscale/i8134x/files.i81342 deleted file mode 100644 index 63c715cb4be7..000000000000 --- a/sys/arm/xscale/i8134x/files.i81342 +++ /dev/null @@ -1,12 +0,0 @@ -# $FreeBSD$ -arm/arm/bus_space_base.c standard -arm/xscale/i8134x/i80321_timer.c standard -arm/xscale/i8134x/i80321_wdog.c optional iopwdog -arm/xscale/i8134x/i81342.c standard -arm/xscale/i8134x/i81342_mcu.c standard -arm/xscale/i8134x/i81342_pci.c optional pci -arm/xscale/i8134x/i81342_space.c standard -arm/xscale/i8134x/obio.c standard -arm/xscale/i8134x/uart_bus_i81342.c optional uart -arm/xscale/i8134x/uart_cpu_i81342.c optional uart -dev/uart/uart_dev_ns8250.c optional uart diff --git a/sys/arm/xscale/i8134x/i80321_timer.c b/sys/arm/xscale/i8134x/i80321_timer.c deleted file mode 100644 index 5dc650568c0a..000000000000 --- a/sys/arm/xscale/i8134x/i80321_timer.c +++ /dev/null @@ -1,486 +0,0 @@ -/* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */ - -/*- - * Copyright (c) 2001, 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Timer/clock support for the Intel i80321 I/O processor. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/time.h> -#include <sys/bus.h> -#include <sys/resource.h> -#include <sys/rman.h> -#include <sys/timetc.h> - -#include <machine/armreg.h> -#include <machine/bus.h> -#include <machine/cpu.h> -#include <machine/frame.h> -#include <machine/resource.h> -#include <machine/intr.h> -#include <arm/xscale/i8134x/i80321reg.h> -#include <arm/xscale/i8134x/i80321var.h> - -#ifdef CPU_XSCALE_81342 -#define ICU_INT_TIMER0 (8) /* XXX: Can't include i81342reg.h because - definitions overrides the ones from i80321reg.h - */ -#endif -#include "opt_timer.h" - -void (*i80321_hardclock_hook)(void) = NULL; -struct i80321_timer_softc { - device_t dev; -} timer_softc; - - -static unsigned i80321_timer_get_timecount(struct timecounter *tc); - - -static uint32_t counts_per_hz; - -#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342) -static uint32_t offset; -static uint32_t last = -1; -#endif - -static int ticked = 0; - -#ifndef COUNTS_PER_SEC -#define COUNTS_PER_SEC 200000000 /* 200MHz */ -#endif - -#define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000) - -static struct timecounter i80321_timer_timecounter = { - i80321_timer_get_timecount, /* get_timecount */ - NULL, /* no poll_pps */ - ~0u, /* counter_mask */ -#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342) - COUNTS_PER_SEC, -#else - COUNTS_PER_SEC * 3, /* frequency */ -#endif - "i80321 timer", /* name */ - 1000 /* quality */ -}; - -static int -i80321_timer_probe(device_t dev) -{ - - device_set_desc(dev, "i80321 timer"); - return (0); -} - -static int -i80321_timer_attach(device_t dev) -{ - timer_softc.dev = dev; - - return (0); -} - -static device_method_t i80321_timer_methods[] = { - DEVMETHOD(device_probe, i80321_timer_probe), - DEVMETHOD(device_attach, i80321_timer_attach), - {0, 0}, -}; - -static driver_t i80321_timer_driver = { - "itimer", - i80321_timer_methods, - sizeof(struct i80321_timer_softc), -}; -static devclass_t i80321_timer_devclass; - -DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0); - -int clockhandler(void *); - - -static __inline uint32_t -tmr1_read(void) -{ - uint32_t rv; - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mrc p6, 0, %0, c1, c9, 0" -#else - __asm __volatile("mrc p6, 0, %0, c1, c1, 0" -#endif - : "=r" (rv)); - return (rv); -} - -static __inline void -tmr1_write(uint32_t val) -{ - - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c1, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c1, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline uint32_t -tcr1_read(void) -{ - uint32_t rv; - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mrc p6, 0, %0, c3, c9, 0" -#else - __asm __volatile("mrc p6, 0, %0, c3, c1, 0" -#endif - : "=r" (rv)); - return (rv); -} -static __inline void -tcr1_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c3, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c3, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline void -trr1_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c5, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c5, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline uint32_t -tmr0_read(void) -{ - uint32_t rv; - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mrc p6, 0, %0, c0, c9, 0" -#else - __asm __volatile("mrc p6, 0, %0, c0, c1, 0" -#endif - : "=r" (rv)); - return (rv); -} - -static __inline void -tmr0_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c0, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c0, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline uint32_t -tcr0_read(void) -{ - uint32_t rv; - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mrc p6, 0, %0, c2, c9, 0" -#else - __asm __volatile("mrc p6, 0, %0, c2, c1, 0" -#endif - : "=r" (rv)); - return (rv); -} -static __inline void -tcr0_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c2, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c2, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline void -trr0_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c4, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c4, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline void -tisr_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c6, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c6, c1, 0" -#endif - : - : "r" (val)); -} - -static __inline uint32_t -tisr_read(void) -{ - int ret; - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mrc p6, 0, %0, c6, c9, 0" : "=r" (ret)); -#else - __asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret)); -#endif - return (ret); -} - -static unsigned -i80321_timer_get_timecount(struct timecounter *tc) -{ -#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342) - uint32_t cur = tcr0_read(); - - if (cur > last && last != -1) { - offset += counts_per_hz; - if (ticked > 0) - ticked--; - } - if (ticked) { - offset += ticked * counts_per_hz; - ticked = 0; - } - return (counts_per_hz - cur + offset); -#else - uint32_t ret; - - __asm __volatile("mrc p14, 0, %0, c1, c0, 0\n" - : "=r" (ret)); - return (ret); -#endif -} - -/* - * i80321_calibrate_delay: - * - * Calibrate the delay loop. - */ -void -i80321_calibrate_delay(void) -{ - - /* - * Just use hz=100 for now -- we'll adjust it, if necessary, - * in cpu_initclocks(). - */ - counts_per_hz = COUNTS_PER_SEC / 100; - - tmr0_write(0); /* stop timer */ - tisr_write(TISR_TMR0); /* clear interrupt */ - trr0_write(counts_per_hz); /* reload value */ - tcr0_write(counts_per_hz); /* current value */ - - tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); -} - -/* - * cpu_initclocks: - * - * Initialize the clock and get them going. - */ -void -cpu_initclocks(void) -{ - u_int oldirqstate; - struct resource *irq; - int rid = 0; - void *ihl; - device_t dev = timer_softc.dev; - - if (hz < 50 || COUNTS_PER_SEC % hz) { - printf("Cannot get %d Hz clock; using 100 Hz\n", hz); - hz = 100; - } - tick = 1000000 / hz; /* number of microseconds between interrupts */ - - /* - * We only have one timer available; stathz and profhz are - * always left as 0 (the upper-layer clock code deals with - * this situation). - */ - if (stathz != 0) - printf("Cannot get %d Hz statclock\n", stathz); - stathz = 0; - - if (profhz != 0) - printf("Cannot get %d Hz profclock\n", profhz); - profhz = 0; - - /* Report the clock frequency. */ - - oldirqstate = disable_interrupts(PSR_I); - - irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, -#ifdef CPU_XSCALE_81342 - ICU_INT_TIMER0, ICU_INT_TIMER0, -#else - ICU_INT_TMR0, ICU_INT_TMR0, -#endif - 1, RF_ACTIVE); - if (!irq) - panic("Unable to setup the clock irq handler.\n"); - else - bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL, - NULL, &ihl); - tmr0_write(0); /* stop timer */ - tisr_write(TISR_TMR0); /* clear interrupt */ - - counts_per_hz = COUNTS_PER_SEC / hz; - - trr0_write(counts_per_hz); /* reload value */ - tcr0_write(counts_per_hz); /* current value */ - tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); - - tc_init(&i80321_timer_timecounter); - restore_interrupts(oldirqstate); - rid = 0; -#if !defined(XSCALE_DISABLE_CCNT) && !defined(CPU_XSCALE_81342) - /* Enable the clock count register. */ - __asm __volatile("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (rid)); - rid &= ~(1 << 3); - rid |= (1 << 2) | 1; - __asm __volatile("mcr p14, 0, %0, c0, c0, 0\n" - : : "r" (rid)); -#endif -} - - -/* - * DELAY: - * - * Delay for at least N microseconds. - */ -void -DELAY(int n) -{ - uint32_t cur, last, delta, usecs; - - TSENTER(); - /* - * This works by polling the timer and counting the - * number of microseconds that go by. - */ - last = tcr0_read(); - delta = usecs = 0; - - while (n > usecs) { - cur = tcr0_read(); - - /* Check to see if the timer has wrapped around. */ - if (last < cur) - delta += (last + (counts_per_hz - cur)); - else - delta += (last - cur); - - last = cur; - - if (delta >= COUNTS_PER_USEC) { - usecs += delta / COUNTS_PER_USEC; - delta %= COUNTS_PER_USEC; - } - } - TSEXIT(); -} - -/* - * clockhandler: - * - * Handle the hardclock interrupt. - */ -int -clockhandler(void *arg) -{ - struct trapframe *frame = arg; - - ticked++; - tisr_write(TISR_TMR0); - hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); - - if (i80321_hardclock_hook != NULL) - (*i80321_hardclock_hook)(); - return (FILTER_HANDLED); -} - -void -cpu_startprofclock(void) -{ -} - -void -cpu_stopprofclock(void) -{ - -} diff --git a/sys/arm/xscale/i8134x/i80321_wdog.c b/sys/arm/xscale/i8134x/i80321_wdog.c deleted file mode 100644 index 72f0fd8511af..000000000000 --- a/sys/arm/xscale/i8134x/i80321_wdog.c +++ /dev/null @@ -1,153 +0,0 @@ -/* $NetBSD: i80321_wdog.c,v 1.6 2003/07/15 00:24:54 lukem Exp $ */ - -/*- - * Copyright (c) 2005 Olivier Houchard - * Copyright (c) 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Watchdog timer support for the Intel i80321 I/O processor. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/watchdog.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> - -#include <machine/bus.h> -#include <machine/machdep.h> - -#include <arm/xscale/i8134x/i80321reg.h> -#include <arm/xscale/i8134x/i80321var.h> - - -struct iopwdog_softc { - device_t dev; - int armed; - int wdog_period; -}; - -static __inline void -wdtcr_write(uint32_t val) -{ - -#ifdef CPU_XSCALE_81342 - __asm __volatile("mcr p6, 0, %0, c7, c9, 0" -#else - __asm __volatile("mcr p6, 0, %0, c7, c1, 0" -#endif - : - : "r" (val)); -} - -static void -iopwdog_tickle(void *arg) -{ - struct iopwdog_softc *sc = arg; - - if (!sc->armed) - return; - wdtcr_write(WDTCR_ENABLE1); - wdtcr_write(WDTCR_ENABLE2); -} - -static int -iopwdog_probe(device_t dev) -{ - struct iopwdog_softc *sc = device_get_softc(dev); - char buf[128]; - - /* - * XXX Should compute the period based on processor speed. - * For a 600MHz XScale core, the wdog must be tickled approx. - * every 7 seconds. - */ - - sc->wdog_period = 7; - sprintf(buf, "i80321 Watchdog, must be tickled every %d seconds", - sc->wdog_period); - device_set_desc_copy(dev, buf); - - return (0); -} - -static void -iopwdog_watchdog_fn(void *private, u_int cmd, int *error) -{ - struct iopwdog_softc *sc = private; - - cmd &= WD_INTERVAL; - if (cmd > 0 && cmd <= 63 - && (uint64_t)1<<cmd <= (uint64_t)sc->wdog_period * 1000000000) { - /* Valid value -> Enable watchdog */ - iopwdog_tickle(sc); - sc->armed = 1; - *error = 0; - } else { - /* Can't disable this watchdog! */ - if (sc->armed) - *error = EOPNOTSUPP; - } -} - -static int -iopwdog_attach(device_t dev) -{ - struct iopwdog_softc *sc = device_get_softc(dev); - - sc->dev = dev; - sc->armed = 0; - EVENTHANDLER_REGISTER(watchdog_list, iopwdog_watchdog_fn, sc, 0); - return (0); -} - -static device_method_t iopwdog_methods[] = { - DEVMETHOD(device_probe, iopwdog_probe), - DEVMETHOD(device_attach, iopwdog_attach), - {0, 0}, -}; - -static driver_t iopwdog_driver = { - "iopwdog", - iopwdog_methods, - sizeof(struct iopwdog_softc), -}; -static devclass_t iopwdog_devclass; - -DRIVER_MODULE(iopwdog, iq, iopwdog_driver, iopwdog_devclass, 0, 0); diff --git a/sys/arm/xscale/i8134x/i80321reg.h b/sys/arm/xscale/i8134x/i80321reg.h deleted file mode 100644 index b6dd4fea14da..000000000000 --- a/sys/arm/xscale/i8134x/i80321reg.h +++ /dev/null @@ -1,455 +0,0 @@ -/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */ - -/*- - * Copyright (c) 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _ARM_XSCALE_I80321REG_H_ -#define _ARM_XSCALE_I80321REG_H_ - -/* - * Register definitions for the Intel 80321 (``Verde'') I/O processor, - * based on the XScale core. - */ - -/* - * Base i80321 memory map: - * - * 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window - * 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows - * 0x9002.0000 - 0xffff.dfff External Memory - * 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers - * 0xffff.e900 - 0xffff.ffff Reserved - */ - -#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL -#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL - -#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL -#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL - -#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL -#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL - -#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL - -#define VERDE_EXTMEM_BASE 0x90020000UL - -#define VERDE_PMMR_BASE 0xffffe000UL -#define VERDE_PMMR_SIZE 0x00001700UL - -/* - * Peripheral Memory Mapped Registers. Defined as offsets - * from the VERDE_PMMR_BASE. - */ -#define VERDE_ATU_BASE 0x0100 -#define VERDE_ATU_SIZE 0x0100 - -#define VERDE_MU_BASE 0x0300 -#define VERDE_MU_SIZE 0x0100 - -#define VERDE_DMA_BASE 0x0400 -#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) -#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) -#define VERDE_DMA_SIZE 0x0100 -#define VERDE_DMA_CHSIZE 0x0040 - -#define VERDE_MCU_BASE 0x0500 -#define VERDE_MCU_SIZE 0x0100 - -#define VERDE_PBIU_BASE 0x0680 -#define VERDE_PBIU_SIZE 0x0080 - -#define VERDE_I2C_BASE 0x1680 -#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) -#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) -#define VERDE_I2C_SIZE 0x0080 -#define VERDE_I2C_CHSIZE 0x0020 - -/* - * Address Translation Unit - */ - /* 0x00 - 0x38 -- PCI configuration space header */ -#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ -#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ -#define ATU_ERLR 0x48 /* Expansion ROM Limit */ -#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ -#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ -#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ -#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ -#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ -#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ -#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ -#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ -#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ -#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ -#define ATU_ATUCR 0x80 /* ATU Configuration */ -#define ATU_PCSR 0x84 /* PCI Configuration and Status */ -#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ -#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ -#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ -#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ -#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ -#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ -#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ -#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ -#define ATU_MSI_PORT 0xb4 /* MSI port */ -#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ -#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ -#define ATU_PCI_X_NEXT 0xe1 /* (1) */ -#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ -#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ - -#define ATUCR_DRC_ALIAS (1U << 19) -#define ATUCR_DAU2GXEN (1U << 18) -#define ATUCR_P_SERR_MA (1U << 16) -#define ATUCR_DTS (1U << 15) -#define ATUCR_P_SERR_DIE (1U << 9) -#define ATUCR_DAE (1U << 8) -#define ATUCR_BIST_IE (1U << 3) -#define ATUCR_OUT_EN (1U << 1) - -#define PCSR_DAAAPE (1U << 18) -#define PCSR_PCI_X_CAP (3U << 16) -#define PCSR_PCI_X_CAP_BORING (0 << 16) -#define PCSR_PCI_X_CAP_66 (1U << 16) -#define PCSR_PCI_X_CAP_100 (2U << 16) -#define PCSR_PCI_X_CAP_133 (3U << 16) -#define PCSR_OTQB (1U << 15) -#define PCSR_IRTQB (1U << 14) -#define PCSR_DTV (1U << 12) -#define PCSR_BUS66 (1U << 10) -#define PCSR_BUS64 (1U << 8) -#define PCSR_RIB (1U << 5) -#define PCSR_RPB (1U << 4) -#define PCSR_CCR (1U << 2) -#define PCSR_CPR (1U << 1) - -#define ATUISR_IMW1BU (1U << 14) -#define ATUISR_ISCEM (1U << 13) -#define ATUISR_RSCEM (1U << 12) -#define ATUISR_PST (1U << 11) -#define ATUISR_P_SERR_ASRT (1U << 10) -#define ATUISR_DPE (1U << 9) -#define ATUISR_BIST (1U << 8) -#define ATUISR_IBMA (1U << 7) -#define ATUISR_P_SERR_DET (1U << 4) -#define ATUISR_PMA (1U << 3) -#define ATUISR_PTAM (1U << 2) -#define ATUISR_PTAT (1U << 1) -#define ATUISR_PMPE (1U << 0) - -#define ATUIMR_IMW1BU (1U << 11) -#define ATUIMR_ISCEM (1U << 10) -#define ATUIMR_RSCEM (1U << 9) -#define ATUIMR_PST (1U << 8) -#define ATUIMR_DPE (1U << 7) -#define ATUIMR_P_SERR_ASRT (1U << 6) -#define ATUIMR_PMA (1U << 5) -#define ATUIMR_PTAM (1U << 4) -#define ATUIMR_PTAT (1U << 3) -#define ATUIMR_PMPE (1U << 2) -#define ATUIMR_IE_SERR_EN (1U << 1) -#define ATUIMR_ECC_TAE (1U << 0) - -#define PCIXCMD_MOST_1 (0 << 4) -#define PCIXCMD_MOST_2 (1 << 4) -#define PCIXCMD_MOST_3 (2 << 4) -#define PCIXCMD_MOST_4 (3 << 4) -#define PCIXCMD_MOST_8 (4 << 4) -#define PCIXCMD_MOST_12 (5 << 4) -#define PCIXCMD_MOST_16 (6 << 4) -#define PCIXCMD_MOST_32 (7 << 4) -#define PCIXCMD_MOST_MASK (7 << 4) -#define PCIXCMD_MMRBC_512 (0 << 2) -#define PCIXCMD_MMRBC_1024 (1 << 2) -#define PCIXCMD_MMRBC_2048 (2 << 2) -#define PCIXCMD_MMRBC_4096 (3 << 2) -#define PCIXCMD_MMRBC_MASK (3 << 2) -#define PCIXCMD_ERO (1U << 1) -#define PCIXCMD_DPERE (1U << 0) - -#define PCIXSR_RSCEM (1U << 29) -#define PCIXSR_DMCRS_MASK (7 << 26) -#define PCIXSR_DMOST_MASK (7 << 23) -#define PCIXSR_COMPLEX (1U << 20) -#define PCIXSR_USC (1U << 19) -#define PCIXSR_SCD (1U << 18) -#define PCIXSR_133_CAP (1U << 17) -#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ -#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) -#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) -#define PCIXSR_FUNCNO(x) ((x) & 0x7) - -/* - * Memory Controller Unit - */ -#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ -#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ -#define MCU_SDBR 0x08 /* SDRAM Base Register */ -#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ -#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ -#define MCU_ECCR 0x34 /* ECC Control Register */ -#define MCU_ELOG0 0x38 /* ECC Log 0 */ -#define MCU_ELOG1 0x3c /* ECC Log 1 */ -#define MCU_ECAR0 0x40 /* ECC address 0 */ -#define MCU_ECAR1 0x44 /* ECC address 1 */ -#define MCU_ECTST 0x48 /* ECC test register */ -#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ -#define MCU_RFR 0x50 /* Refresh Frequency Register */ -#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ -#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ -#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ -#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ -#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ -#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ -#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ -#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ -#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ -#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ -#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ -#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ -#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ -#define MCU_REDR 0x88 /* Rx Enable Delay Register */ - -#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ -#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ - -#define SBRx_TECH (1U << 31) -#define SBRx_BOUND 0x0000003f - -#define ECCR_SBERE (1U << 0) -#define ECCR_MBERE (1U << 1) -#define ECCR_SBECE (1U << 2) -#define ECCR_ECCEN (1U << 3) - -#define ELOGx_SYNDROME 0x000000ff -#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ -#define ELOGx_RW (1U << 12) /* 1 = write error */ - /* - * Dev ID Func Requester - * 2 0 XScale core - * 2 1 ATU - * 13 0 DMA channel 0 - * 13 1 DMA channel 1 - * 26 0 ATU - */ -#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) -#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) - -#define MCISR_ECC_ERR0 (1U << 0) -#define MCISR_ECC_ERR1 (1U << 1) -#define MCISR_ECC_ERRN (1U << 2) - -/* - * Timers - * - * The i80321 timer registers are available in both memory-mapped - * and coprocessor spaces. Most of the registers are read-only - * if memory-mapped, so we access them via coprocessor space. - * - * TMR0 cp6 c0,1 0xffffe7e0 - * TMR1 cp6 c1,1 0xffffe7e4 - * TCR0 cp6 c2,1 0xffffe7e8 - * TCR1 cp6 c3,1 0xffffe7ec - * TRR0 cp6 c4,1 0xffffe7f0 - * TRR1 cp6 c5,1 0xffffe7f4 - * TISR cp6 c6,1 0xffffe7f8 - * WDTCR cp6 c7,1 0xffffe7fc - */ - -#define TMRx_TC (1U << 0) -#define TMRx_ENABLE (1U << 1) -#define TMRx_RELOAD (1U << 2) -#define TMRx_CSEL_CORE (0 << 4) -#define TMRx_CSEL_CORE_div4 (1 << 4) -#define TMRx_CSEL_CORE_div8 (2 << 4) -#define TMRx_CSEL_CORE_div16 (3 << 4) - -#define TISR_TMR0 (1U << 0) -#define TISR_TMR1 (1U << 1) - -#define WDTCR_ENABLE1 0x1e1e1e1e -#define WDTCR_ENABLE2 0xe1e1e1e1 - -/* - * Interrupt Controller Unit. - * - * INTCTL cp6 c0,0 0xffffe7d0 - * INTSTR cp6 c4,0 0xffffe7d4 - * IINTSRC cp6 c8,0 0xffffe7d8 - * FINTSRC cp6 c9,0 0xffffe7dc - * PIRSR 0xffffe1ec - */ - -#define ICU_PIRSR 0x01ec -#define ICU_GPOE 0x07c4 -#define ICU_GPID 0x07c8 -#define ICU_GPOD 0x07cc - -/* - * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE - * INTERRUPTS. See i80321_icu.c - */ -#define ICU_INT_HPI 31 /* high priority interrupt */ -#define ICU_INT_XINT0 27 /* external interrupts */ -#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) -#define ICU_INT_bit26 26 - -/* CPU_XSCALE_80321 */ -#define ICU_INT_SSP 25 /* SSP serial port */ - -#define ICU_INT_MUE 24 /* msg unit error */ - -/* CPU_XSCALE_80321 */ -#define ICU_INT_AAUE 23 /* AAU error */ - -#define ICU_INT_bit22 22 -#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ -#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ -#define ICU_INT_MCUE 19 /* memory controller error */ -#define ICU_INT_ATUE 18 /* ATU error */ -#define ICU_INT_BIUE 17 /* bus interface unit error */ -#define ICU_INT_PMU 16 /* XScale PMU */ -#define ICU_INT_PPM 15 /* peripheral PMU */ -#define ICU_INT_BIST 14 /* ATU Start BIST */ -#define ICU_INT_MU 13 /* messaging unit */ -#define ICU_INT_I2C1 12 /* i2c unit 1 */ -#define ICU_INT_I2C0 11 /* i2c unit 0 */ -#define ICU_INT_TMR1 10 /* timer 1 */ -#define ICU_INT_TMR0 9 /* timer 0 */ -#define ICU_INT_CPPM 8 /* core processor PMU */ - -/* CPU_XSCALE_80321 */ -#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ -#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ - -#define ICU_INT_bit5 5 -#define ICU_INT_bit4 4 -#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ -#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ -#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ -#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ - -/* CPU_XSCALE_80321 */ -#define ICU_INT_HWMASK (0xffffffff & \ - ~((1 << ICU_INT_bit26) | \ - (1 << ICU_INT_bit22) | \ - (1 << ICU_INT_bit5) | \ - (1 << ICU_INT_bit4))) - -/* - * Peripheral Bus Interface Unit - */ - -#define PBIU_PBCR 0x00 /* PBIU Control Register */ -#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ -#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ -#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ -#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ -#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ -#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ -#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ -#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ -#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ -#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ -#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ -#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ -#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ -#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ -#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ -#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ - -#define PBIU_PBCR_PBIEN (1 << 0) -#define PBIU_PBCR_PBI100 (1 << 1) -#define PBIU_PBCR_PBI66 (2 << 1) -#define PBIU_PBCR_PBI33 (3 << 1) -#define PBIU_PBCR_PBBEN (1 << 3) - -#define PBIU_PBARx_WIDTH8 (0 << 0) -#define PBIU_PBARx_WIDTH16 (1 << 0) -#define PBIU_PBARx_WIDTH32 (2 << 0) -#define PBIU_PBARx_ADWAIT4 (0 << 2) -#define PBIU_PBARx_ADWAIT8 (1 << 2) -#define PBIU_PBARx_ADWAIT12 (2 << 2) -#define PBIU_PBARx_ADWAIT16 (3 << 2) -#define PBIU_PBARx_ADWAIT20 (4 << 2) -#define PBIU_PBARx_RCWAIT1 (0 << 6) -#define PBIU_PBARx_RCWAIT4 (1 << 6) -#define PBIU_PBARx_RCWAIT8 (2 << 6) -#define PBIU_PBARx_RCWAIT12 (3 << 6) -#define PBIU_PBARx_RCWAIT16 (4 << 6) -#define PBIU_PBARx_RCWAIT20 (5 << 6) -#define PBIU_PBARx_FWE (1 << 9) -#define PBIU_BASE_MASK 0xfffff000U - -#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) - -/* - * Messaging Unit - */ -#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ -#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ -#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ -#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ -#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ -#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ -#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ -#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ -#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ -#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ -#define MU_MUCR 0x0050 /* MU Configuration Register */ -#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ -#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ -#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ -#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ -#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ -#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ -#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ -#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ -#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ -#define MU_IAR 0x0080 /* MU Index Address Register */ - -#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ -#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ -#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ -#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ -#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ -#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ -#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ - -#endif /* _ARM_XSCALE_I80321REG_H_ */ diff --git a/sys/arm/xscale/i8134x/i80321var.h b/sys/arm/xscale/i8134x/i80321var.h deleted file mode 100644 index 0fead2577a2e..000000000000 --- a/sys/arm/xscale/i8134x/i80321var.h +++ /dev/null @@ -1,137 +0,0 @@ -/* $NetBSD: i80321var.h,v 1.8 2003/10/06 16:06:06 thorpej Exp $ */ - -/*- - * Copyright (c) 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _ARM_XSCALE_I80321VAR_H_ -#define _ARM_XSCALE_I80321VAR_H_ - -#include <sys/queue.h> -#include <dev/pci/pcivar.h> -#include <sys/rman.h> - -extern struct bus_space i80321_bs_tag; - -struct i80321_softc { - device_t dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_sh; - /* Handles for the various subregions. */ - bus_space_handle_t sc_atu_sh; - bus_space_handle_t sc_mcu_sh; - int sc_is_host; - - /* - * We expect the board-specific front-end to have already mapped - * the PCI I/O space .. it is only 64K, and I/O mappings tend to - * be smaller than a page size, so it's generally more efficient - * to map them all into virtual space in one fell swoop. - */ - vm_offset_t sc_iow_vaddr; /* I/O window vaddr */ - - /* - * Variables that define the Inbound windows. The base address of - * 0-2 are configured by a host via BARs. The xlate variable - * defines the start of the local address space that it maps to. - * The size variable defines the byte size. - * - * The first 3 windows are for incoming PCI memory read/write - * cycles from a host. The 4th window, not configured by the - * host (as it outside the normal BAR range) is the inbound - * window for PCI devices controlled by the i80321. - */ - struct { - uint32_t iwin_base_hi; - uint32_t iwin_base_lo; - uint32_t iwin_xlate; - uint32_t iwin_size; - } sc_iwin[4]; - - /* - * Variables that define the Outbound windows. - */ - struct { - uint32_t owin_xlate_lo; - uint32_t owin_xlate_hi; - } sc_owin[2]; - - /* - * This is the PCI address that the Outbound I/O - * window maps to. - */ - uint32_t sc_ioout_xlate; - - /* Bus space, DMA, and PCI tags for the PCI bus (private devices). */ - struct bus_space sc_pci_iot; - struct bus_space sc_pci_memt; - - /* GPIO state */ - uint8_t sc_gpio_dir; /* GPIO pin direction (1 == output) */ - uint8_t sc_gpio_val; /* GPIO output pin value */ - struct rman sc_irq_rman; - -}; - - -struct i80321_pci_softc { - device_t sc_dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_atu_sh; - bus_space_tag_t sc_pciio; - bus_space_tag_t sc_pcimem; - int sc_busno; - struct rman sc_mem_rman; - struct rman sc_io_rman; - struct rman sc_irq_rman; - uint32_t sc_mem; - uint32_t sc_io; -}; - -void i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t, - vm_paddr_t *, vm_size_t *); - -void i80321_attach(struct i80321_softc *); -void i80321_calibrate_delay(void); - -void i80321_bs_init(bus_space_tag_t, void *); -void i80321_io_bs_init(bus_space_tag_t, void *); -void i80321_mem_bs_init(bus_space_tag_t, void *); -extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin); - - -#endif /* _ARM_XSCALE_I80321VAR_H_ */ diff --git a/sys/arm/xscale/i8134x/i81342.c b/sys/arm/xscale/i8134x/i81342.c deleted file mode 100644 index ace6004cf9c0..000000000000 --- a/sys/arm/xscale/i8134x/i81342.c +++ /dev/null @@ -1,468 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> - -#define _ARM32_BUS_DMA_PRIVATE -#include <machine/armreg.h> -#include <machine/bus.h> -#include <machine/intr.h> - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/i81342var.h> - -#define WDTCR_ENABLE1 0x1e1e1e1e -#define WDTCR_ENABLE2 0xe1e1e1e1 - -static volatile int intr_enabled0; -static volatile int intr_enabled1; -static volatile int intr_enabled2; -static volatile int intr_enabled3; - -struct bus_space i81342_bs_tag; - -/* Read the interrupt pending register */ - -static __inline -uint32_t intpnd0_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c0, c3, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intpnd1_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c1, c3, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intpnd2_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c2, c3, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intpnd3_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c3, c3, 0" - : "=r" (ret)); - return (ret); -} - -/* Read the interrupt control register */ -/* 0 masked, 1 unmasked */ -static __inline -uint32_t intctl0_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c0, c4, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intctl1_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c1, c4, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intctl2_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c2, c4, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intctl3_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c3, c4, 0" - : "=r" (ret)); - return (ret); -} - -/* Write the interrupt control register */ - -static __inline -void intctl0_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c0, c4, 0" - : : "r" (val)); -} - -static __inline -void intctl1_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c1, c4, 0" - : : "r" (val)); -} - -static __inline -void intctl2_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c2, c4, 0" - : : "r" (val)); -} - -static __inline -void intctl3_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c3, c4, 0" - : : "r" (val)); -} - -/* Read the interrupt steering register */ -/* 0 IRQ 1 FIQ */ -static __inline -uint32_t intstr0_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c0, c5, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intstr1_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c1, c5, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intstr2_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c2, c5, 0" - : "=r" (ret)); - return (ret); -} - -static __inline -uint32_t intstr3_read(void) -{ - uint32_t ret; - - __asm __volatile("mrc p6, 0, %0, c3, c5, 0" - : "=r" (ret)); - return (ret); -} - -/* Write the interrupt steering register */ - -static __inline -void intstr0_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c0, c5, 0" - : : "r" (val)); -} - -static __inline -void intstr1_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c1, c5, 0" - : : "r" (val)); -} - -static __inline -void intstr2_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c2, c5, 0" - : : "r" (val)); -} - -static __inline -void intstr3_write(uint32_t val) -{ - - __asm __volatile("mcr p6, 0, %0, c3, c5, 0" - : : "r" (val)); -} - -void -cpu_reset(void) -{ - - disable_interrupts(PSR_I); - /* XXX: Use the watchdog to reset for now */ - __asm __volatile("mcr p6, 0, %0, c8, c9, 0\n" - "mcr p6, 0, %1, c7, c9, 0\n" - "mcr p6, 0, %2, c7, c9, 0\n" - : : "r" (1), "r" (WDTCR_ENABLE1), "r" (WDTCR_ENABLE2)); - while (1); -} - -void -arm_mask_irq(uintptr_t nb) -{ - - if (nb < 32) { - intr_enabled0 &= ~(1 << nb); - intctl0_write(intr_enabled0); - } else if (nb < 64) { - intr_enabled1 &= ~(1 << (nb - 32)); - intctl1_write(intr_enabled1); - } else if (nb < 96) { - intr_enabled2 &= ~(1 << (nb - 64)); - intctl2_write(intr_enabled2); - } else { - intr_enabled3 &= ~(1 << (nb - 96)); - intctl3_write(intr_enabled3); - } -} - -void -arm_unmask_irq(uintptr_t nb) -{ - if (nb < 32) { - intr_enabled0 |= (1 << nb); - intctl0_write(intr_enabled0); - } else if (nb < 64) { - intr_enabled1 |= (1 << (nb - 32)); - intctl1_write(intr_enabled1); - } else if (nb < 96) { - intr_enabled2 |= (1 << (nb - 64)); - intctl2_write(intr_enabled2); - } else { - intr_enabled3 |= (1 << (nb - 96)); - intctl3_write(intr_enabled3); - } -} - -int -arm_get_next_irq(int last __unused) -{ - uint32_t val; - val = intpnd0_read() & intr_enabled0; - if (val) - return (ffs(val) - 1); - val = intpnd1_read() & intr_enabled1; - if (val) - return (32 + ffs(val) - 1); - val = intpnd2_read() & intr_enabled2; - if (val) - return (64 + ffs(val) - 1); - val = intpnd3_read() & intr_enabled3; - if (val) - return (96 + ffs(val) - 1); - return (-1); -} - -int -bus_dma_get_range_nb(void) -{ - return (0); -} - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - return (NULL); -} - -static int -i81342_probe(device_t dev) -{ - unsigned int freq; - - freq = *(volatile unsigned int *)(IOP34X_VADDR + IOP34X_PFR); - - switch (freq & IOP34X_FREQ_MASK) { - case IOP34X_FREQ_600: - device_set_desc(dev, "Intel 81342 600MHz"); - break; - case IOP34X_FREQ_667: - device_set_desc(dev, "Intel 81342 667MHz"); - break; - case IOP34X_FREQ_800: - device_set_desc(dev, "Intel 81342 800MHz"); - break; - case IOP34X_FREQ_833: - device_set_desc(dev, "Intel 81342 833MHz"); - break; - case IOP34X_FREQ_1000: - device_set_desc(dev, "Intel 81342 1000MHz"); - break; - case IOP34X_FREQ_1200: - device_set_desc(dev, "Intel 81342 1200MHz"); - break; - default: - device_set_desc(dev, "Intel 81342 unknown frequency"); - break; - } - return (0); -} - -static void -i81342_identify(driver_t *driver, device_t parent) -{ - - BUS_ADD_CHILD(parent, 0, "iq", 0); -} - -static int -i81342_attach(device_t dev) -{ - struct i81342_softc *sc = device_get_softc(dev); - uint32_t esstrsr; - - i81342_bs_init(&i81342_bs_tag, sc); - sc->sc_st = &i81342_bs_tag; - sc->sc_sh = IOP34X_VADDR; - esstrsr = bus_space_read_4(sc->sc_st, sc->sc_sh, IOP34X_ESSTSR0); - sc->sc_atux_sh = IOP34X_ATUX_ADDR(esstrsr) - IOP34X_HWADDR + - IOP34X_VADDR; - sc->sc_atue_sh = IOP34X_ATUE_ADDR(esstrsr) - IOP34X_HWADDR + - IOP34X_VADDR; - /* Disable all interrupts. */ - intctl0_write(0); - intctl1_write(0); - intctl2_write(0); - intctl3_write(0); - /* Defaults to IRQ */ - intstr0_write(0); - intstr1_write(0); - intstr2_write(0); - intstr3_write(0); - sc->sc_irq_rman.rm_type = RMAN_ARRAY; - sc->sc_irq_rman.rm_descr = "i81342 IRQs"; - if (rman_init(&sc->sc_irq_rman) != 0 || - rman_manage_region(&sc->sc_irq_rman, 0, 127) != 0) - panic("i81342_attach: failed to set up IRQ rman"); - - device_add_child(dev, "obio", 0); - device_add_child(dev, "itimer", 0); - device_add_child(dev, "iopwdog", 0); - device_add_child(dev, "pcib", 0); - device_add_child(dev, "pcib", 1); - device_add_child(dev, "iqseg", 0); - bus_generic_probe(dev); - bus_generic_attach(dev); - return (0); -} - -static struct resource * -i81342_alloc_resource(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct i81342_softc *sc = device_get_softc(dev); - struct resource *rv; - - if (type == SYS_RES_IRQ) { - rv = rman_reserve_resource(&sc->sc_irq_rman, - start, end, count, flags, child); - if (rv != NULL) - rman_set_rid(rv, *rid); - return (rv); - } - - return (NULL); -} - -static int -i81342_setup_intr(device_t dev, device_t child, struct resource *ires, - int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, - void **cookiep) -{ - int error; - - error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, - filt, intr, arg, cookiep); - if (error) - return (error); - return (0); -} - -static int -i81342_teardown_intr(device_t dev, device_t child, struct resource *res, - void *cookie) -{ - return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); -} - -static device_method_t i81342_methods[] = { - DEVMETHOD(device_probe, i81342_probe), - DEVMETHOD(device_attach, i81342_attach), - DEVMETHOD(device_identify, i81342_identify), - DEVMETHOD(bus_alloc_resource, i81342_alloc_resource), - DEVMETHOD(bus_setup_intr, i81342_setup_intr), - DEVMETHOD(bus_teardown_intr, i81342_teardown_intr), - {0, 0}, -}; - -static driver_t i81342_driver = { - "iq", - i81342_methods, - sizeof(struct i81342_softc), -}; -static devclass_t i81342_devclass; - -DRIVER_MODULE(iq, nexus, i81342_driver, i81342_devclass, 0, 0); diff --git a/sys/arm/xscale/i8134x/i81342_mcu.c b/sys/arm/xscale/i8134x/i81342_mcu.c deleted file mode 100644 index a144774233ff..000000000000 --- a/sys/arm/xscale/i8134x/i81342_mcu.c +++ /dev/null @@ -1,58 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> - -#include <machine/bus.h> -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/i81342var.h> - -void -i81342_sdram_bounds(bus_space_tag_t bt, bus_space_handle_t bh, - vm_paddr_t *start, vm_size_t *size) -{ - uint32_t reg; - int bank_nb; - - reg = bus_space_read_4(bt, bh, SMC_SDBR); - *start = (reg & SMC_SDBR_BASEADDR_MASK); - reg = bus_space_read_4(bt, bh, SMC_SBSR); - if (reg & SMC_SBSR_BANK_NB) - bank_nb = 1; - else - bank_nb = 2; - - *size = (reg & SMC_SBSR_BANK_SZ_MASK) * bank_nb; -} diff --git a/sys/arm/xscale/i8134x/i81342_pci.c b/sys/arm/xscale/i8134x/i81342_pci.c deleted file mode 100644 index fc348ef1da67..000000000000 --- a/sys/arm/xscale/i8134x/i81342_pci.c +++ /dev/null @@ -1,547 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/types.h> -#include <sys/rman.h> - -#include <machine/bus.h> -#include <machine/cpu.h> -#include <machine/pcb.h> -#include <vm/vm.h> -#include <vm/pmap.h> -#include <vm/vm_extern.h> - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/i81342var.h> - -#include <dev/pci/pcivar.h> -#include <dev/pci/pcib_private.h> -#include "pcib_if.h" - -#include <dev/pci/pcireg.h> - -static pcib_read_config_t i81342_pci_read_config; -static pcib_write_config_t i81342_pci_write_config; - -static int -i81342_pci_probe(device_t dev) -{ - struct i81342_pci_softc *sc; - - sc = device_get_softc(dev); - if (device_get_unit(dev) == 0) { - device_set_desc(dev, "i81342 PCI-X bus"); - sc->sc_is_atux = 1; - } else { - device_set_desc(dev, "i81342 PCIe bus"); - sc->sc_is_atux = 0; - } - return (0); -} - -#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 -#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 - -static int -i81342_pci_attach(device_t dev) -{ - struct i81342_softc *parent_sc; - struct i81342_pci_softc *sc; - uint32_t memsize, memstart; - uint32_t reg; - int func; - uint32_t busno; - - sc = device_get_softc(dev); - parent_sc = device_get_softc(device_get_parent(dev)); - sc->sc_atu_sh = sc->sc_is_atux ? parent_sc->sc_atux_sh : - parent_sc->sc_atue_sh; - sc->sc_st = parent_sc->sc_st; - if (bus_space_read_4(sc->sc_st, parent_sc->sc_sh, IOP34X_ESSTSR0) - & IOP34X_INT_SEL_PCIX) { - if (sc->sc_is_atux) - func = 5; - else - func = 0; - } else { - if (sc->sc_is_atux) - func = 0; - else - func = 5; - } - i81342_io_bs_init(&sc->sc_pciio, sc); - i81342_mem_bs_init(&sc->sc_pcimem, sc); - i81342_sdram_bounds(sc->sc_st, IOP34X_VADDR, &memstart, &memsize); - if (sc->sc_is_atux) { - reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR); - if (reg & ATUX_P_RSTOUT) { - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR, - reg &~ ATUX_P_RSTOUT); - DELAY(200); - } - } - /* Setup the Inbound windows. */ - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR0, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR0, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 0); - - /* Set the mapping Physical address <=> PCI address */ - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR1, - memstart | PCI_MAPREG_MEM_PREFETCHABLE_MASK | - PCI_MAPREG_MEM_TYPE_64BIT); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR1, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1, - rounddown2(~(0xfff), memsize)); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR1, memstart); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUTVR1, 0); - - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR2, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR2, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 0); - - /* Setup the Outbound IO Bar */ - if (sc->sc_is_atux) - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR, - (IOP34X_PCIX_OIOBAR >> 4) | func); - else - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR, - (IOP34X_PCIE_OIOBAR >> 4) | func); - - /* Setup the Outbound windows */ - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR0, 0); - if (sc->sc_is_atux) - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1, - (IOP34X_PCIX_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) | - ATU_OUMBAR_EN); - else - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1, - (IOP34X_PCIE_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) | - ATU_OUMBAR_EN); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMWTVR1, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR2, 0); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR3, 0); - - /* Enable the outbound windows. */ - reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_CR); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_CR, - reg | ATU_CR_OUT_EN); - - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, - bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK); - /* - * Enable bus mastering, memory access, SERR, and parity - * checking on the ATU. - */ - if (sc->sc_is_atux) { - busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); - busno = PCIXSR_BUSNO(busno); - } else { - busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR); - busno = PCIE_BUSNO(busno); - } - reg = bus_space_read_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD); - reg |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN | - PCIM_CMD_SERRESPEN; - bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD, reg); - sc->sc_busno = busno; - /* Initialize memory and i/o rmans. */ - sc->sc_io_rman.rm_type = RMAN_ARRAY; - sc->sc_io_rman.rm_descr = "I81342 PCI I/O Ports"; - if (rman_init(&sc->sc_io_rman) != 0 || - rman_manage_region(&sc->sc_io_rman, - sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR : - IOP34X_PCIE_OIOBAR_VADDR, - (sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR : - IOP34X_PCIE_OIOBAR_VADDR) + IOP34X_OIOBAR_SIZE) != 0) { - panic("i81342_pci_probe: failed to set up I/O rman"); - } - sc->sc_mem_rman.rm_type = RMAN_ARRAY; - sc->sc_mem_rman.rm_descr = "I81342 PCI Memory"; - if (rman_init(&sc->sc_mem_rman) != 0 || - rman_manage_region(&sc->sc_mem_rman, - 0, 0xffffffff) != 0) { - panic("i81342_pci_attach: failed to set up memory rman"); - } - sc->sc_irq_rman.rm_type = RMAN_ARRAY; - sc->sc_irq_rman.rm_descr = "i81342 PCI IRQs"; - if (sc->sc_is_atux) { - if (rman_init(&sc->sc_irq_rman) != 0 || - rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0, - ICU_INT_XINT3) != 0) - panic("i83142_pci_attach: failed to set up IRQ rman"); - } else { - if (rman_init(&sc->sc_irq_rman) != 0 || - rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA, - ICU_INT_ATUE_MD) != 0) - panic("i81342_pci_attach: failed to set up IRQ rman"); - - } - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, - bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK); - device_add_child(dev, "pci", -1); - return (bus_generic_attach(dev)); -} - -static int -i81342_pci_maxslots(device_t dev) -{ - - return (PCI_SLOTMAX); -} - -static void -i81342_pci_conf_setup(struct i81342_pci_softc *sc, int bus, int slot, int func, - int reg, uint32_t *addr) -{ - uint32_t busno; - - if (sc->sc_is_atux) { - busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); - busno = PCIXSR_BUSNO(busno); - } else { - busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR); - busno = PCIE_BUSNO(busno); - } - bus &= 0xff; - slot &= 0x1f; - func &= 0x7; - if (sc->sc_is_atux) { - if (busno == bus) - *addr = (1 << (slot + 16)) | (slot << 11) | - (func << 8) | reg; - else - *addr = (bus << 16) | (slot << 11) | (func << 11) | - reg | 1; - } else { - *addr = (bus << 24) | (slot << 19) | (func << 16) | reg; - if (bus != busno) - *addr |= 1; - } -} - -static u_int32_t -i81342_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, - u_int reg, int bytes) -{ - struct i81342_pci_softc *sc = device_get_softc(dev); - uint32_t addr; - uint32_t ret = 0; - uint32_t isr; - int err = 0; - vm_offset_t va; - - i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ? - ATUX_OCCAR : ATUE_OCCAR, addr); - if (sc->sc_is_atux) - va = sc->sc_atu_sh + ATUX_OCCDR; - else - va = sc->sc_atu_sh + ATUE_OCCDR; - switch (bytes) { - case 1: - err = badaddr_read((void*)(va + (reg & 3)), 1, &ret); - break; - case 2: - err = badaddr_read((void*)(va + (reg & 3)), 2, &ret); - break; - case 4: - err = badaddr_read((void *)(va) , 4, &ret); - break; - default: - printf("i81342_read_config: invalid size %d\n", bytes); - ret = -1; - } - if (err) { - isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR); - if (sc->sc_is_atux) - isr &= ATUX_ISR_ERRMSK; - else - isr &= ATUE_ISR_ERRMSK; - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, isr); - ret = -1; - } - - return (ret); -} - -static void -i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, - u_int reg, u_int32_t data, int bytes) -{ - struct i81342_pci_softc *sc = device_get_softc(dev); - uint32_t addr; - vm_offset_t va; - - i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr); - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ? - ATUX_OCCAR : ATUE_OCCAR, addr); - va = sc->sc_is_atux ? ATUX_OCCDR : ATUE_OCCDR; - switch (bytes) { - case 1: - bus_space_write_1(sc->sc_st, sc->sc_atu_sh, va + (reg & 3) - , data); - break; - case 2: - bus_space_write_2(sc->sc_st, sc->sc_atu_sh, va + (reg & 3) - , data); - break; - case 4: - bus_space_write_4(sc->sc_st, sc->sc_atu_sh, va, data); - break; - default: - printf("i81342_pci_write_config: Invalid size : %d\n", bytes); - } - - -} - -static struct resource * -i81342_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct i81342_pci_softc *sc = device_get_softc(bus); - struct resource *rv; - struct rman *rm; - bus_space_tag_t bt = NULL; - bus_space_handle_t bh = 0; - - switch (type) { - case SYS_RES_IRQ: - rm = &sc->sc_irq_rman; - break; - case SYS_RES_MEMORY: - rm = &sc->sc_mem_rman; - bt = &sc->sc_pcimem; - bh = 0; - break; - case SYS_RES_IOPORT: - rm = &sc->sc_io_rman; - bt = &sc->sc_pciio; - bh = sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR : - IOP34X_PCIE_OIOBAR_VADDR; - start += bh; - end += bh; - break; - default: - return (NULL); - } - - rv = rman_reserve_resource(rm, start, end, count, flags, child); - if (rv == NULL) - return (NULL); - rman_set_rid(rv, *rid); - if (type != SYS_RES_IRQ) { - if (type == SYS_RES_MEMORY) - bh += (rman_get_start(rv)); - rman_set_bustag(rv, bt); - rman_set_bushandle(rv, bh); - if (flags & RF_ACTIVE) { - if (bus_activate_resource(child, type, *rid, rv)) { - rman_release_resource(rv); - return (NULL); - } - } - } - return (rv); - - - return (NULL); -} - -static int -i81342_pci_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - bus_space_handle_t p; - int error; - - if (type == SYS_RES_MEMORY) { - error = bus_space_map(rman_get_bustag(r), - rman_get_bushandle(r), rman_get_size(r), 0, &p); - if (error) - return (error); - rman_set_bushandle(r, p); - - } - return (rman_activate_resource(r)); -} - -static int -i81342_pci_setup_intr(device_t dev, device_t child, struct resource *ires, - int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, - void **cookiep) -{ - - return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, - filt, intr, arg, cookiep)); -} - - - -static int -i81342_pci_teardown_intr(device_t dev, device_t child, struct resource *res, - void *cookie) -{ - return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); -} - -static int -i81342_pci_route_interrupt(device_t pcib, device_t dev, int pin) -{ - struct i81342_pci_softc *sc; - int device; - - device = pci_get_slot(dev); - sc = device_get_softc(pcib); - /* XXX: Is board specific */ - if (sc->sc_is_atux) { - /* PCI-X */ - switch(device) { - case 1: - switch (pin) { - case 1: - return (ICU_INT_XINT1); - case 2: - return (ICU_INT_XINT2); - case 3: - return (ICU_INT_XINT3); - case 4: - return (ICU_INT_XINT0); - default: - break; - } - case 2: - switch (pin) { - case 1: - return (ICU_INT_XINT2); - case 2: - return (ICU_INT_XINT3); - case 3: - return (ICU_INT_XINT2); - case 4: - return (ICU_INT_XINT3); - default: - break; - } - } - - } else { - switch (pin) { - case 1: - return (ICU_INT_ATUE_MA); - case 2: - return (ICU_INT_ATUE_MB); - case 3: - return (ICU_INT_ATUE_MC); - case 4: - return (ICU_INT_ATUE_MD); - default: - break; - } - } - printf("Warning: couldn't map %s IRQ for device %d pin %d\n", - sc->sc_is_atux ? "PCI-X" : "PCIe", device, pin); - return (-1); -} - -static int -i81342_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) -{ - struct i81342_pci_softc *sc = device_get_softc(dev); - switch (which) { - case PCIB_IVAR_DOMAIN: - *result = 0; - return (0); - case PCIB_IVAR_BUS: - *result = sc->sc_busno; - return (0); - - } - return (ENOENT); -} - -static int -i81342_write_ivar(device_t dev, device_t child, int which, uintptr_t result) -{ - struct i81342_pci_softc * sc = device_get_softc(dev); - - switch (which) { - case PCIB_IVAR_DOMAIN: - return (EINVAL); - case PCIB_IVAR_BUS: - sc->sc_busno = result; - return (0); - } - return (ENOENT); -} - -static device_method_t i81342_pci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, i81342_pci_probe), - DEVMETHOD(device_attach, i81342_pci_attach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* Bus interface */ - DEVMETHOD(bus_read_ivar, i81342_read_ivar), - DEVMETHOD(bus_write_ivar, i81342_write_ivar), - DEVMETHOD(bus_alloc_resource, i81342_pci_alloc_resource), - DEVMETHOD(bus_release_resource, bus_generic_release_resource), - DEVMETHOD(bus_activate_resource, i81342_pci_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_setup_intr, i81342_pci_setup_intr), - DEVMETHOD(bus_teardown_intr, i81342_pci_teardown_intr), - - /* pcib interface */ - DEVMETHOD(pcib_maxslots, i81342_pci_maxslots), - DEVMETHOD(pcib_read_config, i81342_pci_read_config), - DEVMETHOD(pcib_write_config, i81342_pci_write_config), - DEVMETHOD(pcib_route_interrupt, i81342_pci_route_interrupt), - DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), - - DEVMETHOD_END -}; - -static driver_t i81342_pci_driver = { - "pcib", - i81342_pci_methods, - sizeof(struct i81342_pci_softc), -}; - -static devclass_t i81342_pci_devclass; - -DRIVER_MODULE(ipci, iq, i81342_pci_driver, i81342_pci_devclass, 0, 0); diff --git a/sys/arm/xscale/i8134x/i81342_space.c b/sys/arm/xscale/i8134x/i81342_space.c deleted file mode 100644 index ed27675e4a0f..000000000000 --- a/sys/arm/xscale/i8134x/i81342_space.c +++ /dev/null @@ -1,234 +0,0 @@ -/* $NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2001, 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * bus_space functions for i81342 I/O Processor. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/malloc.h> - -#include <machine/pcb.h> - -#include <vm/vm.h> -#include <vm/vm_kern.h> -#include <vm/pmap.h> -#include <vm/vm_page.h> -#include <vm/vm_extern.h> - -#include <machine/bus.h> - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/i81342var.h> - -/* Prototypes for all the bus_space structure functions */ -bs_protos(i81342); -bs_protos(i81342_io); -bs_protos(i81342_mem); - -void -i81342_bs_init(bus_space_tag_t bs, void *cookie) -{ - - *bs = *arm_base_bs_tag; - bs->bs_privdata = cookie; -} - -void -i81342_io_bs_init(bus_space_tag_t bs, void *cookie) -{ - - *bs = *arm_base_bs_tag; - bs->bs_privdata = cookie; - - bs->bs_map = i81342_io_bs_map; - bs->bs_unmap = i81342_io_bs_unmap; - bs->bs_alloc = i81342_io_bs_alloc; - bs->bs_free = i81342_io_bs_free; - -} - -void -i81342_mem_bs_init(bus_space_tag_t bs, void *cookie) -{ - - *bs = *arm_base_bs_tag; - bs->bs_privdata = cookie; - - bs->bs_map = i81342_mem_bs_map; - bs->bs_unmap = i81342_mem_bs_unmap; - bs->bs_alloc = i81342_mem_bs_alloc; - bs->bs_free = i81342_mem_bs_free; - -} - -/* *** Routines shared by i81342, PCI IO, and PCI MEM. *** */ - -int -i81342_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, - bus_size_t size, bus_space_handle_t *nbshp) -{ - - *nbshp = bsh + offset; - return (0); -} - -void -i81342_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, - bus_size_t len, int flags) -{ - - /* Nothing to do. */ -} - -/* *** Routines for PCI IO. *** */ - -int -i81342_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, - bus_space_handle_t *bshp) -{ - - *bshp = bpa; - return (0); -} - -void -i81342_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) -{ - - /* Nothing to do. */ -} - -int -i81342_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, - bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, - bus_addr_t *bpap, bus_space_handle_t *bshp) -{ - - panic("i81342_io_bs_alloc(): not implemented"); -} - -void -i81342_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) -{ - - panic("i81342_io_bs_free(): not implemented"); -} - - -/* *** Routines for PCI MEM. *** */ -extern int badaddr_read(void *, int, void *); -static vm_offset_t allocable = 0xe1000000; -int -i81342_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, - bus_space_handle_t *bshp) -{ - struct i81342_pci_softc *sc = (struct i81342_pci_softc *)tag->bs_privdata; - struct i81342_pci_map *tmp; - vm_offset_t addr, endaddr; - vm_paddr_t paddr; - - /* Lookup to see if we already have a mapping at this address. */ - tmp = sc->sc_pci_mappings; - while (tmp) { - if (tmp->paddr <= bpa && tmp->paddr + tmp->size > - bpa + size) { - *bshp = bpa - tmp->paddr + tmp->vaddr; - return (0); - } - tmp = tmp->next; - } - addr = allocable; - endaddr = rounddown2(addr + size, 0x1000000) + 0x1000000; - if (endaddr >= IOP34X_VADDR) - panic("PCI virtual memory exhausted"); - allocable = endaddr; - tmp = malloc(sizeof(*tmp), M_DEVBUF, M_WAITOK); - tmp->next = NULL; - paddr = rounddown2(bpa, 0x100000); - tmp->paddr = paddr; - tmp->vaddr = addr; - tmp->size = 0; - while (addr < endaddr) { - pmap_kenter_supersection(addr, paddr + (sc->sc_is_atux ? - IOP34X_PCIX_OMBAR : IOP34X_PCIE_OMBAR), 0); - addr += 0x1000000; - paddr += 0x1000000; - tmp->size += 0x1000000; - } - tmp->next = sc->sc_pci_mappings; - sc->sc_pci_mappings = tmp; - *bshp = bpa - tmp->paddr + tmp->vaddr; - return (0); -} - -void -i81342_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) -{ -#if 0 - vm_offset_t va, endva; - - va = trunc_page((vm_offset_t)h); - endva = va + round_page(size); - - /* Free the kernel virtual mapping. */ - kva_free(va, endva - va); -#endif -} - -int -i81342_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, - bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, - bus_addr_t *bpap, bus_space_handle_t *bshp) -{ - - panic("i81342_mem_bs_alloc(): not implemented"); -} - -void -i81342_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) -{ - - panic("i81342_mem_bs_free(): not implemented"); -} diff --git a/sys/arm/xscale/i8134x/i81342reg.h b/sys/arm/xscale/i8134x/i81342reg.h deleted file mode 100644 index 07bec22ef89c..000000000000 --- a/sys/arm/xscale/i8134x/i81342reg.h +++ /dev/null @@ -1,350 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $FreeBSD$ */ - -#ifndef I83142_REG_H_ -#define I83142_REG_H_ -/* Physical Memory Map */ -/* - * 0x000000000 - 0x07FFFFFFF SDRAM - * 0x090100000 - 0x0901FFFFF ATUe Outbound IO Window - * 0x0F0000000 - 0x0F1FFFFFF Flash - * 0x0F2000000 - 0x0F20FFFFF PCE1 - * 0x0F3000000 - 0x0FFCFFFFF Compact Flash - * 0x0FFD00000 - 0x0FFDFFFFF MMR - * 0x0FFFB0000 - 0x0FFFBFFFF ATU-X Outbound I/O Window - * 0x0FFFD0000 - 0x0FFFDFFFF ATUe Outbound I/O Window - * 0x100000000 - 0x1FFFFFFFF ATU-X outbound Memory Translation Window - * 0x2FF000000 - 0x2FFFFFFFF ATUe Outbound Memory Translation Window - */ - -#define IOP34X_VADDR 0xf0000000 -#define IOP34X_HWADDR 0xffd00000 -#define IOP34X_SIZE 0x100000 - -#define IOP34X_ADMA0_OFFSET 0x00080000 -#define IOP34X_ADMA1_OFFSET 0x00080200 -#define IOP34X_ADMA2_OFFSET 0x00080400 -#define IOP34X_ADMA_SIZE 0x200 - - -/* ADMA Registers */ -#define IOP34X_ADMA_CCR 0x0000 /* Channel Control Register */ -#define IOP34X_ADMA_CSR 0x0004 /* Channel Status Register */ -#define IOP34X_ADMA_DAR 0x0008 /* Descriptor Address Register */ -#define IOP34X_ADMA_IPCR 0x0018 /* Internal Interface Parity Ctrl Reg */ -#define IOP34X_ADMA_NDAR 0x0024 /* Next Descriptor Register */ -#define IOP34X_ADMA_DCR 0x0028 /* Descriptor Control Register */ - -#define IOP34X_ADMA_IE (1 << 0) /* Interrupt enable */ -#define IOP34X_ADMA_TR (1 << 1) /* Transfert Direction */ -/* - * Source Destination - * 00 Host I/O Interface Local Memory - * 01 Local Memory Host I/O Interface - * 10 Internal Bus Local Memory - * 11 Local Memory Internal Bus - */ -#define IOP34X_ADMA_SS (1 << 3) /* Source selection */ -/* 0000: Data Transfer / CRC / Memory Block Fill */ -#define IOP34X_ADMA_ZRBCE (1 << 7) /* Zero Result Buffer Check Enable */ -#define IOP34X_ADMA_MBFE (1 << 8) /* Memory Block Fill Enable */ -#define IOP34X_ADMA_CGE (1 << 9) /* CRC Generation enable */ -#define IOP34X_ADMA_CTD (1 << 10) /* CRC Transfer disable */ -#define IOP34X_ADMA_CSFD (1 << 11) /* CRC Seed fetch disable */ -#define IOP34X_ADMA_SWBE (1 << 12) /* Status write back enable */ -#define IOP34X_ADMA_ESE (1 << 13) /* Endian swap enable */ -#define IOP34X_ADMA_PQUTE (1 << 16) /* P+Q Update Transfer Enable */ -#define IOP34X_ADMA_DXE (1 << 17) /* Dual XOR Enable */ -#define IOP34X_ADMA_PQTE (1 << 18) /* P+Q Transfer Enable */ -#define IOP34X_ADMA_PTD (1 << 19) /* P Transfer Disable */ -#define IOP34X_ADMA_ROE (1 << 30) /* Relaxed Ordering Enable */ -#define IOP34X_ADMA_NSE (1U << 31) /* No Snoop Enable */ - -#define IOP34X_PBBAR0 0x81588 /* PBI Base Address Register 0 */ -#define IOP34X_PBBAR0_ADDRMASK 0xfffff000 -#define IOP34X_PBBAR1 0x81590 -#define IOP34X_PCE1 0xF2000000 -#define IOP34X_PCE1_SIZE 0x00100000 -#define IOP34X_PCE1_VADDR 0xF1000000 -#define IOP34X_ESSTSR0 0x82188 -#define IOP34X_CONTROLLER_ONLY (1 << 14) -#define IOP34X_INT_SEL_PCIX (1 << 15) -#define IOP34X_PFR 0x82180 /* Processor Frequency Register */ -#define IOP34X_FREQ_MASK ((1 << 16) | (1 << 17) | (1 << 18)) -#define IOP34X_FREQ_600 (0) -#define IOP34X_FREQ_667 (1 << 16) -#define IOP34X_FREQ_800 (1 << 17) -#define IOP34X_FREQ_833 ((1 << 17) | (1 << 16)) -#define IOP34X_FREQ_1000 (1 << 18) -#define IOP34X_FREQ_1200 ((1 << 16) | (1 << 18)) - -#define IOP34X_UART0_VADDR IOP34X_VADDR + 0x82300 -#define IOP34X_UART0_HWADDR IOP34X_HWADDR + 0x82300 -#define IOP34X_UART1_VADDR IOP34X_VADDR + 0x82340 -#define IOP34X_UART1_HWADDR IOP34X_HWADDR + 0x82340 -#define IOP34X_PBI_HWADDR 0xffd81580 - -/* SDRAM Memory Controller */ -#define SMC_SDBR 0x8180c /* Base Register */ -#define SMC_SDBR_BASEADDR (1 << 27) -#define SMC_SDBR_BASEADDR_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \ - | (1U << 31)) -#define SMC_SDUBR 0x81810 /* Upper Base Register */ -#define SMC_SBSR 0x81814 /* SDRAM Bank Size Register */ -#define SMC_SBSR_BANK_NB (1 << 2) /* Number of DDR Banks - 0 => 2 Banks - 1 => 1 Bank - */ -#define SMC_SBSR_BANK_SZ (1 << 27) /* SDRAM Bank Size : - 0x00000 Empty - 0x00001 128MB - 0x00010 256MB - 0x00100 512MB - 0x01000 1GB - */ -#define SMC_SBSR_BANK_SZ_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \ - | (1U << 31)) - - -/* Two possible addresses for ATUe depending on configuration. */ -#define IOP34X_ATUE_ADDR(esstrsr) ((((esstrsr) & (IOP34X_CONTROLLER_ONLY | \ - IOP34X_INT_SEL_PCIX)) == (IOP34X_CONTROLLER_ONLY | IOP34X_INT_SEL_PCIX)) ? \ - 0xffdc8000 : 0xffdcd000) - -/* Three possible addresses for ATU-X depending on configuration. */ -#define IOP34X_ATUX_ADDR(esstrsr) (!((esstrsr) & IOP34X_CONTROLLER_ONLY) ? \ - 0xffdcc000 : !((esstrsr) & IOP34X_INT_SEL_PCIX) ? 0xffdc8000 : 0xffdcd000) - -#define IOP34X_OIOBAR_SIZE 0x10000 -#define IOP34X_PCIX_OIOBAR 0xfffb0000 -#define IOP34X_PCIX_OIOBAR_VADDR 0xf01b0000 -#define IOP34X_PCIX_OMBAR 0x100000000 -#define IOP34X_PCIE_OIOBAR 0xfffd0000 -#define IOP34X_PCIE_OIOBAR_VADDR 0xf01d0000 -#define IOP34X_PCIE_OMBAR 0x200000000 - -/* ATU Registers */ -/* Common for ATU-X and ATUe */ -#define ATU_VID 0x0000 /* ATU Vendor ID */ -#define ATU_DID 0x0002 /* ATU Device ID */ -#define ATU_CMD 0x0004 /* ATU Command Register */ -#define ATU_SR 0x0006 /* ATU Status Register */ -#define ATU_RID 0x0008 /* ATU Revision ID */ -#define ATU_CCR 0x0009 /* ATU Class Code */ -#define ATU_CLSR 0x000c /* ATU Cacheline Size */ -#define ATU_LT 0x000d /* ATU Latency Timer */ -#define ATU_HTR 0x000e /* ATU Header Type */ -#define ATU_BISTR 0x000f /* ATU BIST Register */ -#define ATU_IABAR0 0x0010 /* Inbound ATU Base Address register 0 */ -#define ATU_IAUBAR0 0x0014 /* Inbound ATU Upper Base Address Register 0 */ -#define ATU_IABAR1 0x0018 /* Inbound ATU Base Address Register 1 */ -#define ATU_IAUBAR1 0x001c /* Inbound ATU Upper Base Address Register 1 */ -#define ATU_IABAR2 0x0020 /* Inbound ATU Base Address Register 2 */ -#define ATU_IAUBAR2 0x0024 /* Inbound ATU Upper Base Address Register 2 */ -#define ATU_VSIR 0x002c /* ATU Subsystem Vendor ID Register */ -#define ATU_SIR 0x002e /* ATU Subsystem ID Register */ -#define ATU_ERBAR 0x0030 /* Expansion ROM Base Address Register */ -#define ATU_CAPPTR 0x0034 /* ATU Capabilities Pointer Register */ -#define ATU_ILR 0x003c /* ATU Interrupt Line Register */ -#define ATU_IPR 0x003d /* ATU Interrupt Pin Register */ -#define ATU_MGNT 0x003e /* ATU Minimum Grand Register */ -#define ATU_MLAT 0x003f /* ATU Maximum Latency Register */ -#define ATU_IALR0 0x0040 /* Inbound ATU Limit Register 0 */ -#define ATU_IATVR0 0x0044 /* Inbound ATU Translate Value Register 0 */ -#define ATU_IAUTVR0 0x0048 /* Inbound ATU Upper Translate Value Register 0*/ -#define ATU_IALR1 0x004c /* Inbound ATU Limit Register 1 */ -#define ATU_IATVR1 0x0050 /* Inbound ATU Translate Value Register 1 */ -#define ATU_IAUTVR1 0x0054 /* Inbound ATU Upper Translate Value Register 1*/ -#define ATU_IALR2 0x0058 /* Inbound ATU Limit Register 2 */ -#define ATU_IATVR2 0x005c /* Inbound ATU Translate Value Register 2 */ -#define ATU_IAUTVR2 0x0060 /* Inbound ATU Upper Translate Value Register 2*/ -#define ATU_ERLR 0x0064 /* Expansion ROM Limit Register */ -#define ATU_ERTVR 0x0068 /* Expansion ROM Translator Value Register */ -#define ATU_ERUTVR 0x006c /* Expansion ROM Upper Translate Value Register*/ -#define ATU_CR 0x0070 /* ATU Configuration Register */ -#define ATU_CR_OUT_EN (1 << 1) -#define ATU_PCSR 0x0074 /* PCI Configuration and Status Register */ -#define PCIE_BUSNO(x) ((x & 0xff000000) >> 24) -#define ATUX_CORE_RST ((1 << 30) | (1U << 31)) /* Core Processor Reset */ -#define ATUX_P_RSTOUT (1 << 21) /* Central Resource PCI Bus Reset */ -#define ATUE_CORE_RST ((1 << 9) | (1 << 8)) /* Core Processor Reset */ -#define ATU_ISR 0x0078 /* ATU Interrupt Status Register */ -#define ATUX_ISR_PIE (1 << 18) /* PCI Interface error */ -#define ATUX_ISR_IBPR (1 << 16) /* Internal Bus Parity Error */ -#define ATUX_ISR_DCE (1 << 14) /* Detected Correctable error */ -#define ATUX_ISR_ISCE (1 << 13) /* Initiated Split Completion Error Msg */ -#define ATUX_ISR_RSCE (1 << 12) /* Received Split Completion Error Msg */ -#define ATUX_ISR_DPE (1 << 9) /* Detected Parity Error */ -#define ATUX_ISR_IBMA (1 << 7) /* Internal Bus Master Abort */ -#define ATUX_ISR_PMA (1 << 3) /* PCI Master Abort */ -#define ATUX_ISR_PTAM (1 << 2) /* PCI Target Abort (Master) */ -#define ATUX_ISR_PTAT (1 << 1) /* PCI Target Abort (Target) */ -#define ATUX_ISR_PMPE (1 << 0) /* PCI Master Parity Error */ -#define ATUX_ISR_ERRMSK (ATUX_ISR_PIE | ATUX_ISR_IBPR | ATUX_ISR_DCE | \ - ATUX_ISR_ISCE | ATUX_ISR_RSCE | ATUX_ISR_DPE | ATUX_ISR_IBMA | ATUX_ISR_PMA\ - | ATUX_ISR_PTAM | ATUX_ISR_PTAT | ATUX_ISR_PMPE) -#define ATUE_ISR_HON (1 << 13) /* Halt on Error Interrupt */ -#define ATUE_ISR_RSE (1 << 12) /* Root System Error Message */ -#define ATUE_ISR_REM (1 << 11) /* Root Error Message */ -#define ATUE_ISR_PIE (1 << 10) /* PCI Interface error */ -#define ATUE_ISR_CEM (1 << 9) /* Correctable Error Message */ -#define ATUE_ISR_UEM (1 << 8) /* Uncorrectable error message */ -#define ATUE_ISR_CRS (1 << 7) /* Received Configuration Retry Status */ -#define ATUE_ISR_IBMA (1 << 5) /* Internal Bus Master Abort */ -#define ATUE_ISR_DPE (1 << 4) /* Detected Parity Error Interrupt */ -#define ATUE_ISR_MAI (1 << 3) /* Received Master Abort Interrupt */ -#define ATUE_ISR_STAI (1 << 2) /* Signaled Target Abort Interrupt */ -#define ATUE_ISR_TAI (1 << 1) /* Received Target Abort Interrupt */ -#define ATUE_ISR_MDPE (1 << 0) /* Master Data Parity Error Interrupt */ -#define ATUE_ISR_ERRMSK (ATUE_ISR_HON | ATUE_ISR_RSE | ATUE_ISR_REM | \ - ATUE_ISR_PIE | ATUE_ISR_CEM | ATUE_ISR_UEM | ATUE_ISR_CRS | ATUE_ISR_IBMA |\ - ATUE_ISR_DPE | ATUE_ISR_MAI | ATUE_ISR_STAI | ATUE_ISR_TAI | ATUE_ISR_MDPE) -#define ATU_IMR 0x007c /* ATU Interrupt Mask Register */ -/* 0x0080 - 0x008f reserved */ -#define ATU_VPDCID 0x0090 /* VPD Capability Identifier Register */ -#define ATU_VPDNIP 0x0091 /* VPD Next Item Pointer Register */ -#define ATU_VPDAR 0x0092 /* VPD Address Register */ -#define ATU_VPDDR 0x0094 /* VPD Data Register */ -#define ATU_PMCID 0x0098 /* PM Capability Identifier Register */ -#define ATU_PMNIPR 0x0099 /* PM Next Item Pointer Register */ -#define ATU_PMCR 0x009a /* ATU Power Management Capabilities Register */ -#define ATU_PMCSR 0x009c /* ATU Power Management Control/Status Register*/ -#define ATU_MSICIR 0x00a0 /* MSI Capability Identifier Register */ -#define ATU_MSINIPR 0x00a1 /* MSI Next Item Pointer Register */ -#define ATU_MCR 0x00a2 /* Message Control Register */ -#define ATU_MAR 0x00a4 /* Message Address Register */ -#define ATU_MUAR 0x00a8 /* Message Upper Address Register */ -#define ATU_MDR 0x00ac /* Message Data Register */ -#define ATU_PCIXSR 0x00d4 /* PCI-X Status Register */ -#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) -#define ATU_IABAR3 0x0200 /* Inbound ATU Base Address Register 3 */ -#define ATU_IAUBAR3 0x0204 /* Inbound ATU Upper Base Address Register 3 */ -#define ATU_IALR3 0x0208 /* Inbound ATU Limit Register 3 */ -#define ATU_ITVR3 0x020c /* Inbound ATU Upper Translate Value Reg 3 */ -#define ATU_OIOBAR 0x0300 /* Outbound I/O Base Address Register */ -#define ATU_OIOWTVR 0x0304 /* Outbound I/O Window Translate Value Reg */ -#define ATU_OUMBAR0 0x0308 /* Outbound Upper Memory Window base addr reg 0*/ -#define ATU_OUMBAR_FUNC (28) -#define ATU_OUMBAR_EN (1U << 31) -#define ATU_OUMWTVR0 0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */ -#define ATU_OUMBAR1 0x0310 /* Outbound Upper Memory Window base addr reg1*/ -#define ATU_OUMWTVR1 0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */ -#define ATU_OUMBAR2 0x0318 /* Outbound Upper Memory Window base addr reg2*/ -#define ATU_OUMWTVR2 0x031c /* Outbount Upper 32bit Memory Window Translate Value Register 2 */ -#define ATU_OUMBAR3 0x0320 /* Outbound Upper Memory Window base addr reg3*/ -#define ATU_OUMWTVR3 0x0324 /* Outbound Upper 32bit Memory Window Translate Value Register 3 */ - -/* ATU-X specific */ -#define ATUX_OCCAR 0x0330 /* Outbound Configuration Cycle Address Reg */ -#define ATUX_OCCDR 0x0334 /* Outbound Configuration Cycle Data Reg */ -#define ATUX_OCCFN 0x0338 /* Outbound Configuration Cycle Function Number*/ -/* ATUe specific */ -#define ATUE_OCCAR 0x032c /* Outbound Configuration Cycle Address Reg */ -#define ATUE_OCCDR 0x0330 /* Outbound Configuration Cycle Data Reg */ -#define ATUE_OCCFN 0x0334 /* Outbound Configuration Cycle Function Number*/ -/* Interrupts */ - -/* IINTRSRC0 */ -#define ICU_INT_ADMA0_EOT (0) /* ADMA 0 End of transfer */ -#define ICU_INT_ADMA0_EOC (1) /* ADMA 0 End of Chain */ -#define ICU_INT_ADMA1_EOT (2) /* ADMA 1 End of transfer */ -#define ICU_INT_ADMA1_EOC (3) /* ADMA 1 End of chain */ -#define ICU_INT_ADMA2_EOT (4) /* ADMA 2 End of transfer */ -#define ICU_INT_ADMA2_EOC (5) /* ADMA 2 end of chain */ -#define ICU_INT_WDOG (6) /* Watchdog timer */ -/* 7 Reserved */ -#define ICU_INT_TIMER0 (8) /* Timer 0 */ -#define ICU_INT_TIMER1 (9) /* Timer 1 */ -#define ICU_INT_I2C0 (10) /* I2C bus interface 0 */ -#define ICU_INT_I2C1 (11) /* I2C bus interface 1 */ -#define ICU_INT_MU (12) /* Message Unit */ -#define ICU_INT_MU_IPQ (13) /* Message unit inbound post queue */ -#define ICU_INT_ATUE_IM (14) /* ATU-E inbound message */ -#define ICU_INT_ATU_BIST (15) /* ATU/Start BIST */ -#define ICU_INT_PMC (16) /* PMC */ -#define ICU_INT_PMU (17) /* PMU */ -#define ICU_INT_PC (18) /* Processor cache */ -/* 19-23 Reserved */ -#define ICU_INT_XINT0 (24) -#define ICU_INT_XINT1 (25) -#define ICU_INT_XINT2 (26) -#define ICU_INT_XINT3 (27) -#define ICU_INT_XINT4 (28) -#define ICU_INT_XINT5 (29) -#define ICU_INT_XINT6 (30) -#define ICU_INT_XINT7 (31) -/* IINTSRC1 */ -#define ICU_INT_XINT8 (32) -#define ICU_INT_XINT9 (33) -#define ICU_INT_XINT10 (34) -#define ICU_INT_XINT11 (35) -#define ICU_INT_XINT12 (36) -#define ICU_INT_XINT13 (37) -#define ICU_INT_XINT14 (38) -#define ICU_INT_XINT15 (39) -/* 40-50 reserved */ -#define ICU_INT_UART0 (51) /* UART 0 */ -#define ICU_INT_UART1 (52) /* UART 1 */ -#define ICU_INT_PBIUE (53) /* Peripheral bus interface unit error */ -#define ICU_INT_ATUCRW (54) /* ATU Configuration register write */ -#define ICU_INT_ATUE (55) /* ATU error */ -#define ICU_INT_MCUE (56) /* Memory controller unit error */ -#define ICU_INT_ADMA0E (57) /* ADMA Channel 0 error */ -#define ICU_INT_ADMA1E (58) /* ADMA Channel 1 error */ -#define ICU_INT_ADMA2E (59) /* ADMA Channel 2 error */ -/* 60-61 reserved */ -#define ICU_INT_MUE (62) /* Messaging Unit Error */ -/* 63 reserved */ - -/* IINTSRC2 */ -#define ICU_INT_IP (64) /* Inter-processor */ -/* 65-93 reserved */ -#define ICU_INT_SIBBE (94) /* South internal bus bridge error */ -/* 95 reserved */ - -/* IINTSRC3 */ -#define ICU_INT_I2C2 (96) /* I2C bus interface 2 */ -#define ICU_INT_ATUE_BIST (97) /* ATU-E/Start BIST */ -#define ICU_INT_ATUE_CRW (98) /* ATU-E Configuration register write */ -#define ICU_INT_ATUEE (99) /* ATU-E Error */ -#define ICU_INT_IMU (100) /* IMU */ -/* 101-106 reserved */ -#define ICU_INT_ATUE_MA (107) /* ATUE Interrupt message A */ -#define ICU_INT_ATUE_MB (108) /* ATUE Interrupt message B */ -#define ICU_INT_ATUE_MC (109) /* ATUE Interrupt message C */ -#define ICU_INT_ATUE_MD (110) /* ATUE Interrupt message D */ -#define ICU_INT_MU_MSIX_TW (111) /* MU MSI-X Table write */ -/* 112 reserved */ -#define ICU_INT_IMSI (113) /* Inbound MSI */ -/* 114-126 reserved */ -#define ICU_INT_HPI (127) /* HPI */ - - -#endif /* I81342_REG_H_ */ diff --git a/sys/arm/xscale/i8134x/i81342var.h b/sys/arm/xscale/i8134x/i81342var.h deleted file mode 100644 index 92574964610e..000000000000 --- a/sys/arm/xscale/i8134x/i81342var.h +++ /dev/null @@ -1,72 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $FreeBSD$ */ -#ifndef I81342VAR_H_ -#define I81342VAR_H_ - -#include <sys/rman.h> - -struct i81342_softc { - device_t dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_sh; - bus_space_handle_t sc_atux_sh; - bus_space_handle_t sc_atue_sh; - bus_space_tag_t sc_pciio; - bus_space_tag_t sc_pcimem; - struct rman sc_irq_rman; -}; - -struct i81342_pci_map { - vm_offset_t vaddr; - vm_paddr_t paddr; - vm_size_t size; - struct i81342_pci_map *next; -}; - -struct i81342_pci_softc { - device_t sc_dev; - bus_space_tag_t sc_st; - bus_space_handle_t sc_atu_sh; - struct bus_space sc_pciio; - struct bus_space sc_pcimem; - struct rman sc_mem_rman; - struct rman sc_io_rman; - struct rman sc_irq_rman; - char sc_is_atux; - int sc_busno; - struct i81342_pci_map *sc_pci_mappings; -}; - -void i81342_bs_init(bus_space_tag_t, void *); -void i81342_io_bs_init(bus_space_tag_t, void *); -void i81342_mem_bs_init(bus_space_tag_t, void *); -void i81342_sdram_bounds(bus_space_tag_t, bus_space_handle_t, vm_paddr_t *, - vm_size_t *); -#endif /*I81342VAR_H_ */ diff --git a/sys/arm/xscale/i8134x/iq81342_7seg.c b/sys/arm/xscale/i8134x/iq81342_7seg.c deleted file mode 100644 index 7264d1c9e656..000000000000 --- a/sys/arm/xscale/i8134x/iq81342_7seg.c +++ /dev/null @@ -1,393 +0,0 @@ -/* $NetBSD: iq31244_7seg.c,v 1.2 2003/07/15 00:25:01 lukem Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Support for the 7-segment display on the Intel IQ81342. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/bus.h> -#include <sys/sysctl.h> - -#include <machine/bus.h> - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/iq81342reg.h> -#include <arm/xscale/i8134x/iq81342var.h> - -#define WRITE(x, v) *((__volatile uint8_t *) (x)) = (v) - -static int snakestate; - -/* - * The 7-segment display looks like so: - * - * A - * +-----+ - * | | - * F | | B - * | G | - * +-----+ - * | | - * E | | C - * | D | - * +-----+ o DP - * - * Setting a bit clears the corresponding segment on the - * display. - */ -#define SEG_A (1 << 1) -#define SEG_B (1 << 2) -#define SEG_C (1 << 3) -#define SEG_D (1 << 4) -#define SEG_E (1 << 5) -#define SEG_F (1 << 6) -#define SEG_G (1 << 7) -#define SEG_DP (1 << 0) - -static const uint8_t digitmap[] = { -/* +#####+ - * # # - * # # - * # # - * +-----+ - * # # - * # # - * # # - * +#####+ - */ - (unsigned char)~SEG_G, - -/* +-----+ - * | # - * | # - * | # - * +-----+ - * | # - * | # - * | # - * +-----+ - */ - SEG_B|SEG_C, - -/* +#####+ - * | # - * | # - * | # - * +#####+ - * # | - * # | - * # | - * +#####+ - */ - ~(SEG_C|SEG_F), - -/* +#####+ - * | # - * | # - * | # - * +#####+ - * | # - * | # - * | # - * +#####+ - */ - ~(SEG_E|SEG_F), - -/* +-----+ - * # # - * # # - * # # - * +#####+ - * | # - * | # - * | # - * +-----+ - */ - ~(SEG_A|SEG_D|SEG_E), - -/* +#####+ - * # | - * # | - * # | - * +#####+ - * | # - * | # - * | # - * +#####+ - */ - ~(SEG_B|SEG_E), - -/* +#####+ - * # | - * # | - * # | - * +#####+ - * # # - * # # - * # # - * +#####+ - */ - ~(SEG_B), - -/* +#####+ - * | # - * | # - * | # - * +-----+ - * | # - * | # - * | # - * +-----+ - */ - ~(SEG_D|SEG_E|SEG_F), - -/* +#####+ - * # # - * # # - * # # - * +#####+ - * # # - * # # - * # # - * +#####+ - */ - ~0, - -/* +#####+ - * # # - * # # - * # # - * +#####+ - * | # - * | # - * | # - * +-----+ - */ - ~(SEG_D|SEG_E), -}; - -static uint8_t -iq81342_7seg_xlate(char c) -{ - uint8_t rv; - - if (c >= '0' && c <= '9') - rv = digitmap[c - '0']; - else if (c == '.') - rv = (uint8_t) ~SEG_DP; - else - rv = 0xff; - - return (rv); -} - -void -iq81342_7seg(char a, char b) -{ - uint8_t msb, lsb; - - msb = iq81342_7seg_xlate(a); - lsb = iq81342_7seg_xlate(b); - - snakestate = 0; - - WRITE(IQ8134X_7SEG_MSB, msb); - WRITE(IQ8134X_7SEG_LSB, lsb); -} - -static const uint8_t snakemap[][2] = { - -/* +#####+ +#####+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - */ - { SEG_A, SEG_A }, - -/* +-----+ +-----+ - * # | | # - * # | | # - * # | | # - * +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - */ - { SEG_F, SEG_B }, - -/* +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +#####+ +#####+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - */ - { SEG_G, SEG_G }, - -/* +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - * | # # | - * | # # | - * | # # | - * +-----+ +-----+ - */ - { SEG_C, SEG_E }, - -/* +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +#####+ +#####+ - */ - { SEG_D, SEG_D }, - -/* +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - * # | | # - * # | | # - * # | | # - * +-----+ +-----+ - */ - { SEG_E, SEG_C }, - -/* +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +#####+ +#####+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - */ - { SEG_G, SEG_G }, - -/* +-----+ +-----+ - * | # # | - * | # # | - * | # # | - * +-----+ +-----+ - * | | | | - * | | | | - * | | | | - * +-----+ +-----+ - */ - { SEG_B, SEG_F }, -}; - -static SYSCTL_NODE(_hw, OID_AUTO, sevenseg, CTLFLAG_RD, 0, "7 seg"); -static int freq = 20; -SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0, - "7 Seg update frequency"); -static void -iq81342_7seg_snake(void) -{ - static int snakefreq; - int cur = snakestate; - - snakefreq++; - if ((snakefreq % freq)) - return; - WRITE(IQ8134X_7SEG_MSB, snakemap[cur][0]); - WRITE(IQ8134X_7SEG_LSB, snakemap[cur][1]); - - snakestate = (cur + 1) & 7; -} - -struct iq81342_7seg_softc { - device_t dev; -}; - -static int -iq81342_7seg_probe(device_t dev) -{ - - device_set_desc(dev, "IQ81342 7seg"); - return (0); -} - -extern void (*i80321_hardclock_hook)(void); -static int -iq81342_7seg_attach(device_t dev) -{ - - i80321_hardclock_hook = iq81342_7seg_snake; - return (0); -} - -static device_method_t iq81342_7seg_methods[] = { - DEVMETHOD(device_probe, iq81342_7seg_probe), - DEVMETHOD(device_attach, iq81342_7seg_attach), - {0, 0}, -}; - -static driver_t iq81342_7seg_driver = { - "iqseg", - iq81342_7seg_methods, - sizeof(struct iq81342_7seg_softc), -}; -static devclass_t iq81342_7seg_devclass; - -DRIVER_MODULE(iqseg, iq, iq81342_7seg_driver, iq81342_7seg_devclass, 0, 0); diff --git a/sys/arm/xscale/i8134x/iq81342reg.h b/sys/arm/xscale/i8134x/iq81342reg.h deleted file mode 100644 index da1e67b83f21..000000000000 --- a/sys/arm/xscale/i8134x/iq81342reg.h +++ /dev/null @@ -1,35 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $FreeBSD$ */ - -#ifndef _IQ81342REG_H_ -#define _IQ81342REG_H_ -#define IQ8134X_7SEG_MSB IOP34X_PCE1_VADDR + 0x40000 -#define IQ8134X_7SEG_LSB IOP34X_PCE1_VADDR + 0x50000 -#endif /* _IQ81342REG_H_ */ diff --git a/sys/arm/xscale/i8134x/iq81342var.h b/sys/arm/xscale/i8134x/iq81342var.h deleted file mode 100644 index 8c89a0f82ef7..000000000000 --- a/sys/arm/xscale/i8134x/iq81342var.h +++ /dev/null @@ -1,34 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Olivier Houchard - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* $FreeBSD$ */ - -#ifndef _IQ81342VAR_H_ -#define _IQ81342VAR_H_ -void iq81342_7seg(char, char); -#endif /* _I8Q1342VAR_H_ */ diff --git a/sys/arm/xscale/i8134x/obio.c b/sys/arm/xscale/i8134x/obio.c deleted file mode 100644 index f81b02795a77..000000000000 --- a/sys/arm/xscale/i8134x/obio.c +++ /dev/null @@ -1,168 +0,0 @@ -/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * On-board device autoconfiguration support for Intel IQ80321 - * evaluation boards. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <sys/rman.h> -#include <sys/malloc.h> - -#include <machine/bus.h> - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/obiovar.h> - -static int -obio_probe(device_t dev) -{ - return (0); -} - -static int -obio_attach(device_t dev) -{ - struct obio_softc *sc = device_get_softc(dev); - - sc->oba_st = arm_base_bs_tag; - sc->oba_rman.rm_type = RMAN_ARRAY; - sc->oba_rman.rm_descr = "OBIO I/O"; - if (rman_init(&sc->oba_rman) != 0 || - rman_manage_region(&sc->oba_rman, - IOP34X_UART0_VADDR, IOP34X_UART1_VADDR + 0x40) != 0) - panic("obio_attach: failed to set up I/O rman"); - sc->oba_irq_rman.rm_type = RMAN_ARRAY; - sc->oba_irq_rman.rm_descr = "OBIO IRQ"; - if (rman_init(&sc->oba_irq_rman) != 0 || - rman_manage_region(&sc->oba_irq_rman, ICU_INT_UART0, ICU_INT_UART1) != 0) - panic("obio_attach: failed to set up IRQ rman"); - device_add_child(dev, "uart", 0); - device_add_child(dev, "uart", 1); - bus_generic_probe(dev); - bus_generic_attach(dev); - return (0); -} - -static struct resource * -obio_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct resource *rv; - struct rman *rm; - bus_space_tag_t bt = NULL; - bus_space_handle_t bh = 0; - struct obio_softc *sc = device_get_softc(bus); - int unit = device_get_unit(child); - - switch (type) { - case SYS_RES_IRQ: - rm = &sc->oba_irq_rman; - if (unit == 0) - start = end = ICU_INT_UART0; - else - start = end = ICU_INT_UART1; - break; - case SYS_RES_MEMORY: - return (NULL); - case SYS_RES_IOPORT: - rm = &sc->oba_rman; - bt = sc->oba_st; - if (unit == 0) { - bh = IOP34X_UART0_VADDR; - start = bh; - end = IOP34X_UART1_VADDR; - } else { - bh = IOP34X_UART1_VADDR; - start = bh; - end = start + 0x40; - } - break; - default: - return (NULL); - } - - - rv = rman_reserve_resource(rm, start, end, count, flags, child); - if (rv == NULL) - return (NULL); - if (type == SYS_RES_IRQ) - return (rv); - rman_set_rid(rv, *rid); - rman_set_bustag(rv, bt); - rman_set_bushandle(rv, bh); - - return (rv); - -} - -static int -obio_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - return (0); -} -static device_method_t obio_methods[] = { - DEVMETHOD(device_probe, obio_probe), - DEVMETHOD(device_attach, obio_attach), - - DEVMETHOD(bus_alloc_resource, obio_alloc_resource), - DEVMETHOD(bus_activate_resource, obio_activate_resource), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - {0, 0}, -}; - -static driver_t obio_driver = { - "obio", - obio_methods, - sizeof(struct obio_softc), -}; -static devclass_t obio_devclass; - -DRIVER_MODULE(obio, iq, obio_driver, obio_devclass, 0, 0); diff --git a/sys/arm/xscale/i8134x/obiovar.h b/sys/arm/xscale/i8134x/obiovar.h deleted file mode 100644 index fe773df10c82..000000000000 --- a/sys/arm/xscale/i8134x/obiovar.h +++ /dev/null @@ -1,56 +0,0 @@ -/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _IQ81342_OBIOVAR_H_ -#define _IQ81342_OBIOVAR_H_ - -#include <sys/rman.h> - -struct obio_softc { - bus_space_tag_t oba_st; /* bus space tag */ - int oba_irq; /* XINT interrupt bit # */ - struct rman oba_rman; - struct rman oba_irq_rman; - -}; - -#endif /* _IQ80321_OBIOVAR_H_ */ diff --git a/sys/arm/xscale/i8134x/std.crb b/sys/arm/xscale/i8134x/std.crb deleted file mode 100644 index fe80ffb1c02e..000000000000 --- a/sys/arm/xscale/i8134x/std.crb +++ /dev/null @@ -1,6 +0,0 @@ -#CRB board configuration -#$FreeBSD$ -include "../xscale/i8134x/std.i81342" -files "../xscale/i8134x/files.crb" -makeoptions KERNPHYSADDR=0x00200000 -makeoptions KERNVIRTADDR=0xc0200000 diff --git a/sys/arm/xscale/i8134x/std.i81342 b/sys/arm/xscale/i8134x/std.i81342 deleted file mode 100644 index a9ad3f92a3c8..000000000000 --- a/sys/arm/xscale/i8134x/std.i81342 +++ /dev/null @@ -1,6 +0,0 @@ -#XScale i81342 generic configuration -#$FreeBSD$ -files "../xscale/i8134x/files.i81342" -include "../xscale/std.xscale" -cpu CPU_XSCALE_81342 -machine arm diff --git a/sys/arm/xscale/i8134x/uart_bus_i81342.c b/sys/arm/xscale/i8134x/uart_bus_i81342.c deleted file mode 100644 index c1b39f7db55d..000000000000 --- a/sys/arm/xscale/i8134x/uart_bus_i81342.c +++ /dev/null @@ -1,94 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2004 Olivier Houchard. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/conf.h> -#include <sys/kernel.h> -#include <sys/module.h> -#include <machine/bus.h> -#include <sys/rman.h> -#include <machine/resource.h> - -#include <dev/pci/pcivar.h> - -#include <dev/uart/uart.h> -#include <dev/uart/uart_bus.h> -#include <dev/uart/uart_cpu.h> - -#include <dev/ic/ns16550.h> - -#include "uart_if.h" - -static int uart_i81342_probe(device_t dev); - -static device_method_t uart_i81342_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_i81342_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_i81342_driver = { - uart_driver_name, - uart_i81342_methods, - sizeof(struct uart_softc), -}; - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; -static int -uart_i81342_probe(device_t dev) -{ - struct uart_softc *sc; - int err; - - sc = device_get_softc(dev); - sc->sc_class = &uart_ns8250_class; - if (device_get_unit(dev) == 0) { - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - } - sc->sc_rres = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, - &sc->sc_rrid, uart_getrange(sc->sc_class), RF_ACTIVE); - - sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); - sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); - bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, REG_IER << 2, - 0x40 | 0x10); - bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); - - err = uart_bus_probe(dev, 2, 0, 33334000, 0, device_get_unit(dev)); - sc->sc_rxfifosz = sc->sc_txfifosz = 1; - return (err); -} - - -DRIVER_MODULE(uart, obio, uart_i81342_driver, uart_devclass, 0, 0); diff --git a/sys/arm/xscale/i8134x/uart_cpu_i81342.c b/sys/arm/xscale/i8134x/uart_cpu_i81342.c deleted file mode 100644 index 59bd47602186..000000000000 --- a/sys/arm/xscale/i8134x/uart_cpu_i81342.c +++ /dev/null @@ -1,70 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <sys/cdefs.h> -__FBSDID("$FreeBSD$"); - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/bus.h> -#include <sys/cons.h> -#include <machine/bus.h> - -#include <dev/uart/uart.h> -#include <dev/uart/uart_cpu.h> - -#include <arm/xscale/i8134x/i81342reg.h> -#include <arm/xscale/i8134x/obiovar.h> - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - - di->ops = uart_getops(&uart_ns8250_class); - di->bas.chan = 0; - di->bas.bst = arm_base_bs_tag; - di->bas.regshft = 2; - di->bas.rclk = 33334000; - di->baudrate = 115200; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - uart_bus_space_io = arm_base_bs_tag; - uart_bus_space_mem = NULL; - di->bas.bsh = IOP34X_UART0_VADDR; - return (0); -} |