diff options
Diffstat (limited to 'sys/contrib/dev/acpica/common/dmtbinfo1.c')
| -rw-r--r-- | sys/contrib/dev/acpica/common/dmtbinfo1.c | 575 |
1 files changed, 569 insertions, 6 deletions
diff --git a/sys/contrib/dev/acpica/common/dmtbinfo1.c b/sys/contrib/dev/acpica/common/dmtbinfo1.c index 8ce79320db3b..49c0f6f2a31c 100644 --- a/sys/contrib/dev/acpica/common/dmtbinfo1.c +++ b/sys/contrib/dev/acpica/common/dmtbinfo1.c @@ -8,7 +8,7 @@ * * 1. Copyright Notice * - * Some or all of this work - Copyright (c) 1999 - 2022, Intel Corp. + * Some or all of this work - Copyright (c) 1999 - 2025, Intel Corp. * All rights reserved. * * 2. License @@ -287,6 +287,16 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorError[] = ACPI_DMT_TERMINATOR }; +/* 3: Vendor Defined V2 */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorV2Error[] = +{ + {ACPI_DMT_UINT64, ACPI_AEST3A_OFFSET (AcpiHid), "ACPI HID", 0}, + {ACPI_DMT_UINT32, ACPI_AEST3A_OFFSET (AcpiUid), "ACPI UID", 0}, + {ACPI_DMT_BUF16, ACPI_AEST3A_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, + ACPI_DMT_TERMINATOR +}; + /* 4: Gic Error */ ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = @@ -296,6 +306,31 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = ACPI_DMT_TERMINATOR }; +/* 5: PCIe Error */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestPCIeError[] = +{ + {ACPI_DMT_UINT32, ACPI_AEST5_OFFSET (IortNodeReference), "Iort Node Reference", 0}, + ACPI_DMT_TERMINATOR +}; + +/* 6: Proxy Error */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestProxyError[] = +{ + {ACPI_DMT_UINT64, ACPI_AEST6_OFFSET (NodeAddress), "Proxy Node Address", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Common AEST structures for subtables */ + +#define ACPI_DM_AEST_INTERFACE_COMMON(a) \ + {ACPI_DMT_UINT32, ACPI_AEST0D##a##_OFFSET (Common.ErrorNodeDevice), "Arm Error Node Device", 0},\ + {ACPI_DMT_UINT32, ACPI_AEST0D##a##_OFFSET (Common.ProcessorAffinity), "Processor Affinity", 0}, \ + {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.ErrorGroupRegisterBase), "Err-Group Register Addr", 0}, \ + {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.FaultInjectRegisterBase), "Err-Inject Register Addr", 0}, \ + {ACPI_DMT_UINT64, ACPI_AEST0D##a##_OFFSET (Common.InterruptConfigRegisterBase), "IRQ-Config Register Addr", 0}, + /* AestXface: Node Interface Structure */ ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = @@ -314,6 +349,60 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = ACPI_DMT_TERMINATOR }; +/* AestXface: Node Interface Structure V2 Header */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestXfaceHeader[] = +{ + {ACPI_DMT_AEST_XFACE, ACPI_AEST0DH_OFFSET (Type), "Interface Type", 0}, + {ACPI_DMT_UINT8, ACPI_AEST0DH_OFFSET (GroupFormat), "Group Format", 0}, + {ACPI_DMT_UINT16, ACPI_AEST0DH_OFFSET (Reserved[0]), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (Flags), "Flags (decoded below)", 0}, + {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, + {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, + {ACPI_DMT_FLAG2, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Error Node Device Valid", 0}, + {ACPI_DMT_FLAG3, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Affinity Type", 0}, + {ACPI_DMT_FLAG4, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Error group Address Valid", 0}, + {ACPI_DMT_FLAG5, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Fault Injection Address Valid", 0}, + {ACPI_DMT_FLAG7, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Interrupt Config Address valid", 0}, + {ACPI_DMT_UINT64, ACPI_AEST0DH_OFFSET (Address), "Address", 0}, + {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, + {ACPI_DMT_UINT32, ACPI_AEST0DH_OFFSET (ErrorRecordCount), "Error Record Count", 0}, + ACPI_DMT_TERMINATOR +}; + +/* AestXface: Node Interface Structure V2 4K Group Format */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface4k[] = +{ + {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, + {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, + {ACPI_DMT_UINT64, ACPI_AEST0D4_OFFSET (AddressingMode), "Addressing Mode", 0}, + ACPI_DM_AEST_INTERFACE_COMMON(4) + ACPI_DMT_TERMINATOR +}; + +/* AestXface: Node Interface Structure V2 16K Group Format */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface16k[] = +{ + {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (ErrorRecordImplemented[0]),"Error Record Implemented", 0}, + {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (ErrorStatusReporting[0]), "Error Status Reporting", 0}, + {ACPI_DMT_BUF32, ACPI_AEST0D16_OFFSET (AddressingMode[0]), "Addressing Mode", 0}, + ACPI_DM_AEST_INTERFACE_COMMON(16) + ACPI_DMT_TERMINATOR +}; + +/* AestXface: Node Interface Structure V2 64K Group Format */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface64k[] = +{ + {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (ErrorRecordImplemented[0]),"Error Record Implemented", 0}, + {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (ErrorStatusReporting[0]), "Error Status Reporting", 0}, + {ACPI_DMT_BUF112, ACPI_AEST0D64_OFFSET (AddressingMode[0]), "Addressing Mode", 0}, + ACPI_DM_AEST_INTERFACE_COMMON(64) + ACPI_DMT_TERMINATOR +}; + /* AestXrupt: Node Interrupt Structure */ ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = @@ -329,6 +418,20 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = }; +/* AestXrupt: Node Interrupt Structure V2 */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAestXruptV2[] = +{ + {ACPI_DMT_AEST_XRUPT, ACPI_AEST0EA_OFFSET (Type), "Interrupt Type", 0}, + {ACPI_DMT_UINT16, ACPI_AEST0EA_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT8, ACPI_AEST0EA_OFFSET (Flags), "Flags (decoded below)", 0}, + {ACPI_DMT_FLAG0, ACPI_AEST0EA_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, + {ACPI_DMT_UINT32, ACPI_AEST0EA_OFFSET (Gsiv), "Gsiv", 0}, + {ACPI_DMT_UINT32, ACPI_AEST0EA_OFFSET (Reserved1[0]), "Reserved", 0}, + ACPI_DMT_TERMINATOR +}; + + /******************************************************************************* * * ASF - Alert Standard Format table (Signature "ASF!") @@ -435,6 +538,57 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = /******************************************************************************* * + * ASPT - AMD Secure Processor table (Signature "ASPT") + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoAspt[] = +{ + {ACPI_DMT_UINT32, ACPI_ASPT_OFFSET(NumEntries), "Number of Subtables", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Common Subtable header (one per Subtable) */ +ACPI_DMTABLE_INFO AcpiDmTableInfoAsptHdr[] = +{ + {ACPI_DMT_ASPT, ACPI_ASPTH_OFFSET(Type), "Type", 0}, + {ACPI_DMT_UINT16, ACPI_ASPTH_OFFSET(Length), "Length", 0}, + ACPI_DMT_TERMINATOR +}; + +/* 0: ASPT Global Registers */ +ACPI_DMTABLE_INFO AcpiDmTableInfoAspt0[] = +{ + {ACPI_DMT_UINT32, ACPI_ASPT0_OFFSET(Reserved), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(FeatureRegAddr), "Feature Register Address", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqEnRegAddr), "Interrupt Enable Register Address", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqStRegAddr), "Interrupt Status Register Address", 0}, + ACPI_DMT_TERMINATOR +}; + +/* 1: ASPT SEV Mailbox Registers */ +ACPI_DMTABLE_INFO AcpiDmTableInfoAspt1[] = +{ + {ACPI_DMT_UINT8, ACPI_ASPT1_OFFSET(MboxIrqId), "Mailbox Interrupt ID", 0}, + {ACPI_DMT_UINT24, ACPI_ASPT1_OFFSET(Reserved[0]), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufLoRegAddr), "CmdBufAddr_Lo Register Address", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufHiRegAddr), "CmdBufAddr_Hi Register Address", 0}, + ACPI_DMT_TERMINATOR +}; + +/* 2: ASPT ACPI Maiblox Registers */ +ACPI_DMTABLE_INFO AcpiDmTableInfoAspt2[] = +{ + {ACPI_DMT_UINT32, ACPI_ASPT2_OFFSET(Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[0]), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[1]), "Reserved", 0}, + ACPI_DMT_TERMINATOR +}; + +/******************************************************************************* + * * BDAT - BIOS Data ACPI Table * ******************************************************************************/ @@ -494,6 +648,116 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = ACPI_DMT_TERMINATOR }; +/******************************************************************************* + * + * CDAT - Coherent Device Attribute Table + * + ******************************************************************************/ + + /* Table header (not ACPI-compliant) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdatTableHdr[] = +{ + {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Length), "CDAT Table Length", DT_LENGTH}, + {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Revision), "Revision", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Checksum), "Checksum", 0}, + {ACPI_DMT_UINT48, ACPI_CDAT_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Sequence), "Sequence", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Common subtable header */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdatHeader[] = +{ + {ACPI_DMT_CDAT, ACPI_CDATH_OFFSET (Type), "Subtable Type", 0}, + {ACPI_DMT_UINT8, ACPI_CDATH_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT16, ACPI_CDATH_OFFSET (Length), "Length", DT_LENGTH}, + ACPI_DMT_TERMINATOR +}; + +/* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdat0[] = +{ + {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (DsmadHandle), "DSMAD Handle", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT0_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaBaseAddress), "DPA Base Address", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaLength), "DPA Length", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdat1[] = +{ + {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Handle), "Handle", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (DataType), "Data Type", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[0]), "Entry0", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[1]), "Entry1", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[2]), "Entry2", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Reserved2), "Reserved", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdat2[] = +{ + {ACPI_DMT_UINT8, ACPI_CDAT2_OFFSET (DsmasHandle), "DSMAS Handle", 0}, + {ACPI_DMT_UINT24, ACPI_CDAT2_OFFSET (Reserved[3]), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT2_OFFSET (SideCacheSize), "Side Cache Size", 0}, + {ACPI_DMT_UINT32, ACPI_CDAT2_OFFSET (CacheAttributes), "Cache Attributes", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Subtable 3: Device Scoped Initiator Structure (DSIS) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdat3[] = +{ + {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Handle), "Handle", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT3_OFFSET (Reserved), "Reserved", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdat4[] = +{ + {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (DsmasHandle), "DSMAS Handle", 0}, + {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (MemoryType), "Memory Type", 0}, + {ACPI_DMT_UINT16, ACPI_CDAT4_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (DpaOffset), "DPA Offset", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (RangeLength), "DPA Range Length", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdat5[] = +{ + {ACPI_DMT_UINT8, ACPI_CDAT5_OFFSET (DataType), "Data Type", 0}, + {ACPI_DMT_UINT24, ACPI_CDAT5_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_CDAT5_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, + ACPI_DMT_TERMINATOR +}; + +/* Switch Scoped Latency and Bandwidth Entry (SSLBE) (For subtable 5 above) */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCdatEntries[] = +{ + {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortxId), "Port X Id", 0}, + {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortyId), "Port Y Id", 0}, + {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (LatencyOrBandwidth), "Latency or Bandwidth", 0}, + {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (Reserved), "Reserved", 0}, + ACPI_DMT_TERMINATOR +}; + /******************************************************************************* * @@ -528,7 +792,7 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1[] = {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Reserved1), "Reserved", 0}, {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (BaseHpa), "Window base address", 0}, {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (WindowSize), "Window size", 0}, - {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveWays), "Interleave Members (2^n)", 0}, + {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveWays), "Interleave Members", 0}, {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveArithmetic), "Interleave Arithmetic", 0}, {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Reserved2), "Reserved", 0}, {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Granularity), "Granularity", 0}, @@ -544,6 +808,23 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1_te[] = ACPI_DMT_TERMINATOR }; +/* 2: CXL XOR Interleave Math Structure */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoCedt2[] = +{ + {ACPI_DMT_UINT16, ACPI_CEDT2_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT8, ACPI_CEDT2_OFFSET (Hbig), "Interleave Granularity", 0}, + {ACPI_DMT_UINT8, ACPI_CEDT2_OFFSET (NrXormaps), "Xormap List Count", 0}, + {ACPI_DMT_UINT64, ACPI_CEDT2_OFFSET (XormapList), "First Xormap", 0}, + ACPI_DMT_TERMINATOR +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoCedt2_te[] = +{ + {ACPI_DMT_UINT64, ACPI_CEDT2_TE_OFFSET (Xormap), "Next Xormap", 0}, + ACPI_DMT_TERMINATOR +}; + /******************************************************************************* * * CPEP - Corrected Platform Error Polling table @@ -730,7 +1011,8 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = { {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, - {ACPI_DMT_UINT16, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, ACPI_DMT_TERMINATOR @@ -743,7 +1025,8 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = { {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, - {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Size), "Size (decoded below)", 0}, + {ACPI_DMT_FLAGS4_0, ACPI_DMAR0_FLAG_OFFSET (Size,0), "Size (pages, log2)", 0}, {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, ACPI_DMT_TERMINATOR @@ -790,7 +1073,7 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = ACPI_DMT_TERMINATOR }; -/* 5: Hardware Unit Definition */ +/* 5: SoC Integrated Address Translation Cache */ ACPI_DMTABLE_INFO AcpiDmTableInfoDmar5[] = { @@ -800,6 +1083,16 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoDmar5[] = ACPI_DMT_TERMINATOR }; +/* 6: SoC Integrated Device Property */ + +ACPI_DMTABLE_INFO AcpiDmTableInfoDmar6[] = +{ + {ACPI_DMT_UINT16, ACPI_DMAR6_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT16, ACPI_DMAR6_OFFSET (Segment), "PCI Segment Number", 0}, + ACPI_DMT_TERMINATOR +}; + + /******************************************************************************* * * DRTM - Dynamic Root of Trust for Measurement table @@ -909,6 +1202,276 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = /******************************************************************************* * + * ERDT - Enhanced Resource Director Technology table + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdt[] = +{ + {ACPI_DMT_UINT32, ACPI_ERDT_OFFSET (MaxClos), "Maximum supported CLOSID", 0}, + {ACPI_DMT_BUF24, ACPI_ERDT_OFFSET (Reserved), "Reserved", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * ERDT - Common Subtable Header + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtHdr[] = +{ + {ACPI_DMT_ERDT, ACPI_ERDT_HDR_OFFSET (Type), "Type", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_HDR_OFFSET (Length), "Length", DT_LENGTH}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - ERDT Resource Management Domain Description subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtRmdd[] = +{ + {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, + {ACPI_DMT_FLAG0, ACPI_ERDT_RMDD_FLAG_OFFSET (Flags,0), "L3 Domain", 0}, + {ACPI_DMT_FLAG1, ACPI_ERDT_RMDD_FLAG_OFFSET (Flags,0), "I/O L3 Domain", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (IO_l3_Slices), "I/O L3 Slices", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_RMDD_OFFSET (IO_l3_Sets), "I/O L3 Sets", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_RMDD_OFFSET (IO_l3_Ways), "I/O L3 Ways", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_RMDD_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (DomainId), "Domain ID", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_RMDD_OFFSET (MaxRmid), "Maximum supported RMID", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_RMDD_OFFSET (CregBase), "Control Register Base Address", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_RMDD_OFFSET (CregSize), "Control Register Base Size", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - CACD CPU Agent Collection Description subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCacd[] = +{ + {ACPI_DMT_UINT16, ACPI_ERDT_CACD_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CACD_OFFSET (DomainId), "Domain ID", 0}, + ACPI_DMT_TERMINATOR +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCacdX2apic[] = +{ + {ACPI_DMT_UINT32, 0, "X2ApicID", DT_OPTIONAL}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - DACD Device Agent Collection Description subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacd[] = +{ + {ACPI_DMT_UINT16, ACPI_ERDT_DACD_OFFSET (Reserved), "Reserved", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_DACD_OFFSET (DomainId), "Domain ID", 0}, + ACPI_DMT_TERMINATOR +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacdScope[] = +{ + {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Header.Type), "PCIType", DT_OPTIONAL}, + {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Header.Length), "Length", DT_OPTIONAL}, + {ACPI_DMT_UINT16, ACPI_ERDT_DACD_PATH_OFFSET (Segment), "Segment", DT_OPTIONAL}, + {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (Reserved), "Reserved", DT_OPTIONAL}, + {ACPI_DMT_UINT8, ACPI_ERDT_DACD_PATH_OFFSET (StartBus), "StartBus", DT_OPTIONAL}, + ACPI_DMT_TERMINATOR +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtDacdPath[] = +{ + {ACPI_DMT_UINT8, 0, "Path", DT_OPTIONAL}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - Cache Monitoring Registers for CPU Agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCmrc[] = +{ + {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_CMRC_OFFSET (IndexFn), "Register Index Function", 0}, + {ACPI_DMT_BUF11, ACPI_ERDT_CMRC_OFFSET (Reserved2), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_CMRC_OFFSET (CmtRegBase), "CMT Register Base Address", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CMRC_OFFSET (CmtRegSize), "CMT Register Size", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CMRC_OFFSET (ClumpSize), "Clump Size", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CMRC_OFFSET (ClumpStride), "Clump Stride", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_CMRC_OFFSET (UpScale), "Upscale factor", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - Memory-bandwidth Monitoring Registers for CPU agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMmrc[] = +{ + {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_MMRC_OFFSET (IndexFn), "Register Index Function", 0}, + {ACPI_DMT_BUF11, ACPI_ERDT_MMRC_OFFSET (Reserved2), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_MMRC_OFFSET (RegBase), "MBM Register Base Address", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (RegSize), "MBM Register Size", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_MMRC_OFFSET (CounterWidth), "MBM Counter Width", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_MMRC_OFFSET (UpScale), "Upscale factor", 0}, + {ACPI_DMT_UINT56, ACPI_ERDT_MMRC_OFFSET (Reserved3), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (CorrFactorListLen), "Corr Factor List Length", 0}, + ACPI_DMT_TERMINATOR +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMmrcCorrFactor[] = +{ + {ACPI_DMT_UINT32, 0, "CorrFactor", DT_OPTIONAL}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - Memory-bandwidth Allocation Registers for CPU agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtMarc[] = +{ + {ACPI_DMT_UINT16, ACPI_ERDT_MARC_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_MARC_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_MARC_OFFSET (IndexFn), "Register Index Function", 0}, + {ACPI_DMT_UINT56, ACPI_ERDT_MARC_OFFSET (Reserved2), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseOpt), "MBA Register Opt Base Address", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseMin), "MBA Register Min Base Address", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_MARC_OFFSET (RegBaseMax), "MBA Register Max Base Address", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_MARC_OFFSET (MbaRegSize), "MBA Register Size", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_MARC_OFFSET (MbaCtrlRange), "MBA Control Range", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - Cache Allocation Registers for CPU Agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCarc[] = +{ + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - Cache Monitoring Registers for Device Agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCmrd[] = +{ + {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_CMRD_OFFSET (IndexFn), "Register Index Function", 0}, + {ACPI_DMT_BUF11, ACPI_ERDT_CMRD_OFFSET (Reserved2), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_CMRD_OFFSET (RegBase), "CMRD Register Base Address", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (RegSize), "CMRD Register Size", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CMRD_OFFSET (CmtRegOff), "Register Offset", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CMRD_OFFSET (CmtClumpSize), "Clump Size", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_CMRD_OFFSET (UpScale), "Upscale factor", 0}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - O Bandwidth Monitoring Registers for Device Agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbrd[] = +{ + {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_IBRD_OFFSET (IndexFn), "Register Index Function", 0}, + {ACPI_DMT_BUF11, ACPI_ERDT_IBRD_OFFSET (Reserved2), "Reserved", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_IBRD_OFFSET (RegBase), "IBRD Register Base Address", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (RegSize), "IBRD Register Size", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (TotalBwOffset), "TotalBw Offset", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (IOMissBwOffset), "IO Miss Offset", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (TotalBwClump), "TotalBw Clump", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_IBRD_OFFSET (IOMissBwClump), "IO Miss Clump", 0}, + {ACPI_DMT_UINT56, ACPI_ERDT_IBRD_OFFSET (Reserved3), "Reserved", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_IBRD_OFFSET (CounterWidth), "Counter Width", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_IBRD_OFFSET (UpScale), "Upscale factor", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (CorrFactorListLen), "Corr Factor List Length", 0}, + ACPI_DMT_TERMINATOR +}; + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbrdCorrFactor[] = +{ + {ACPI_DMT_UINT32, 0, "CorrFactor", DT_OPTIONAL}, + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - O bandwidth Allocation Registers for Device Agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtIbad[] = +{ + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * + * RMDD - Cache Allocation Registers for Device Agents subtable + * + ******************************************************************************/ + +ACPI_DMTABLE_INFO AcpiDmTableInfoErdtCard[] = +{ + {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (Reserved1), "Reserved", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (Flags), "Flags", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (ContentionMask), "ContentionMask", 0}, + {ACPI_DMT_UINT8, ACPI_ERDT_CARD_OFFSET (IndexFn), "Register Index Function", 0}, + {ACPI_DMT_UINT56, ACPI_ERDT_CARD_OFFSET (Reserved2), "Register Index Function", 0}, + {ACPI_DMT_UINT64, ACPI_ERDT_CARD_OFFSET (RegBase), "CARD Register Base Address", 0}, + {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (RegSize), "CARD Register Size", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CARD_OFFSET (CatRegOffset), "CARD Register Offset", 0}, + {ACPI_DMT_UINT16, ACPI_ERDT_CARD_OFFSET (CatRegBlockSize), "CARD Register Block Size", 0}, + + ACPI_DMT_TERMINATOR +}; + + +/******************************************************************************* + * * ERST - Error Record Serialization table * ******************************************************************************/ @@ -1387,7 +1950,7 @@ ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, - {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (Reserved2), "Reserved2", 0}, + {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (AddressMode), "Address Mode", 0}, {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, ACPI_DMT_TERMINATOR }; |