diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml')
| -rw-r--r-- | sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml b/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml index 926c503bed1f..f261445bf341 100644 --- a/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml +++ b/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,19 +4,23 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation - and control of clock signals for the IP modules, generation and control of resets, - and control over booting, low power consumption and power supply domains. + On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles + generation and control of clock signals for the IP modules, generation and + control of resets, and control over booting, low power consumption and power + supply domains. properties: compatible: - const: renesas,r9a09g057-cpg + enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g056-cpg # RZ/V2N + - renesas,r9a09g057-cpg # RZ/V2H reg: maxItems: 1 @@ -37,7 +41,7 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/renesas,r9a09g057-cpg.h>, + <dt-bindings/clock/renesas,r9a09g0*-cpg.h>, - For module clocks, the two clock specifier cells must be "CPG_MOD" and a module number. The module number is calculated as the CLKON register offset index multiplied by 16, plus the actual bit in the register |