diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/clock')
172 files changed, 6331 insertions, 265 deletions
diff --git a/sys/contrib/device-tree/Bindings/clock/actions,owl-cmu.yaml b/sys/contrib/device-tree/Bindings/clock/actions,owl-cmu.yaml new file mode 100644 index 000000000000..28396441bc98 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/actions,owl-cmu.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi Owl Clock Management Unit (CMU) + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: | + The Actions Semi Owl Clock Management Unit generates and supplies clock + to various controllers within the SoC. + + See also: + include/dt-bindings/clock/actions,s500-cmu.h + include/dt-bindings/clock/actions,s700-cmu.h + include/dt-bindings/clock/actions,s900-cmu.h + +properties: + compatible: + enum: + - actions,s500-cmu + - actions,s700-cmu + - actions,s900-cmu + + reg: + maxItems: 1 + + clocks: + items: + - description: Host oscillator source + - description: Internal low frequency oscillator source + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0xe0160000 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/adi,axi-clkgen.yaml b/sys/contrib/device-tree/Bindings/clock/adi,axi-clkgen.yaml index 5e942bccf277..2b2041818a0a 100644 --- a/sys/contrib/device-tree/Bindings/clock/adi,axi-clkgen.yaml +++ b/sys/contrib/device-tree/Bindings/clock/adi,axi-clkgen.yaml @@ -26,9 +26,21 @@ properties: description: Specifies the reference clock(s) from which the output frequency is derived. This must either reference one clock if only the first clock - input is connected or two if both clock inputs are connected. - minItems: 1 - maxItems: 2 + input is connected or two if both clock inputs are connected. The last + clock is the AXI bus clock that needs to be enabled so we can access the + core registers. + minItems: 2 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: clkin1 + - const: s_axi_aclk + - items: + - const: clkin1 + - const: clkin2 + - const: s_axi_aclk '#clock-cells': const: 0 @@ -40,6 +52,7 @@ required: - compatible - reg - clocks + - clock-names - '#clock-cells' additionalProperties: false @@ -50,5 +63,6 @@ examples: compatible = "adi,axi-clkgen-2.00.a"; #clock-cells = <0>; reg = <0xff000000 0x1000>; - clocks = <&osc 1>; + clocks = <&osc 1>, <&clkc 15>; + clock-names = "clkin1", "s_axi_aclk"; }; diff --git a/sys/contrib/device-tree/Bindings/clock/airoha,en7523-scu.yaml b/sys/contrib/device-tree/Bindings/clock/airoha,en7523-scu.yaml index 84353fd09428..fe2c5c1baf43 100644 --- a/sys/contrib/device-tree/Bindings/clock/airoha,en7523-scu.yaml +++ b/sys/contrib/device-tree/Bindings/clock/airoha,en7523-scu.yaml @@ -34,8 +34,10 @@ properties: - airoha,en7581-scu reg: - minItems: 2 - maxItems: 4 + items: + - description: scu base address + - description: misc scu base address + minItems: 1 "#clock-cells": description: @@ -60,9 +62,7 @@ allOf: then: properties: reg: - items: - - description: scu base address - - description: misc scu base address + minItems: 2 '#reset-cells': false @@ -73,11 +73,7 @@ allOf: then: properties: reg: - items: - - description: scu base address - - description: misc scu base address - - description: reset base address - - description: pb scu base address + maxItems: 1 additionalProperties: false @@ -96,12 +92,9 @@ examples: #address-cells = <2>; #size-cells = <2>; - scuclk: clock-controller@1fa20000 { + scuclk: clock-controller@1fb00000 { compatible = "airoha,en7581-scu"; - reg = <0x0 0x1fa20000 0x0 0x400>, - <0x0 0x1fb00000 0x0 0x90>, - <0x0 0x1fb00830 0x0 0x8>, - <0x0 0x1fbe3400 0x0 0xfc>; + reg = <0x0 0x1fb00000 0x0 0x970>; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/sys/contrib/device-tree/Bindings/clock/allwinner,sun55i-a523-ccu.yaml b/sys/contrib/device-tree/Bindings/clock/allwinner,sun55i-a523-ccu.yaml new file mode 100644 index 000000000000..f5f62e9a10a1 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Clock Control Unit + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-r-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 5 + + clock-names: + minItems: 4 + maxItems: 5 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Peripherals PLL + - description: Audio PLL + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-periph + - const: pll-audio + +additionalProperties: false + +examples: + - | + clock-controller@2001000 { + compatible = "allwinner,sun55i-a523-ccu"; + reg = <0x02001000 0x1000>; + clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>; + clock-names = "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/sys/contrib/device-tree/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 70369bd633e4..7fcd55d468d4 100644 --- a/sys/contrib/device-tree/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/sys/contrib/device-tree/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -25,6 +25,7 @@ properties: - const: allwinner,sun50i-a64-de2-clk - const: allwinner,sun50i-h5-de2-clk - const: allwinner,sun50i-h6-de3-clk + - const: allwinner,sun50i-h616-de33-clk - items: - const: allwinner,sun8i-r40-de2-clk - const: allwinner,sun8i-h3-de2-clk diff --git a/sys/contrib/device-tree/Bindings/clock/alphascale,asm9260-clock-controller.yaml b/sys/contrib/device-tree/Bindings/clock/alphascale,asm9260-clock-controller.yaml new file mode 100644 index 000000000000..1caad419ce9d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/alphascale,asm9260-clock-controller.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Alphascale Clock Controller + +maintainers: + - Oleksij Rempel <linux@rempel-privat.de> + +description: | + The ACC (Alphascale Clock Controller) is responsible for choosing proper + clock source, setting dividers and clock gates. + + Simple one-cell clock specifier format is used, where the only cell is used + as an index of the clock inside the provider. + It is encouraged to use dt-binding for clock index definitions. SoC specific + dt-binding should be included to the device tree descriptor. For example + Alphascale ASM9260: + + #include <dt-bindings/clock/alphascale,asm9260.h> + + This binding contains two types of clock providers: + + _AHB_ - AHB gate; + _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider. + + All clock specific details can be found in the SoC documentation. + +properties: + compatible: + const: alphascale,asm9260-clock-controller + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/amlogic,meson8-clkc.yaml b/sys/contrib/device-tree/Bindings/clock/amlogic,meson8-clkc.yaml new file mode 100644 index 000000000000..ab73d4654171 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/amlogic,meson8-clkc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson8-clkc + - amlogic,meson8b-clkc + - items: + - const: amlogic,meson8m2-clkc + - const: amlogic,meson8-clkc + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + items: + - const: xtal + - const: ddr_pll + - const: clk_32k + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#reset-cells' + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/apm,xgene-device-clock.yaml b/sys/contrib/device-tree/Bindings/clock/apm,xgene-device-clock.yaml new file mode 100644 index 000000000000..b27bcb2a9ee0 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/apm,xgene-device-clock.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC device clocks + +maintainers: + - Khuong Dinh <khuong@os.amperecomputing.com> + +properties: + compatible: + const: apm,xgene-device-clock + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + items: + - enum: [ csr-reg, div-reg ] + - const: div-reg + minItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + + clock-output-names: + maxItems: 1 + + clock-names: + maxItems: 1 + + csr-offset: + description: Offset to the CSR reset register + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + csr-mask: + description: CSR reset mask bit + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0xf + + enable-offset: + description: Offset to the enable register + $ref: /schemas/types.yaml#/definitions/uint32 + default: 8 + + enable-mask: + description: CSR enable mask bit + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0xf + + divider-offset: + description: Offset to the divider register + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + divider-width: + description: Width of the divider register + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + divider-shift: + description: Bit shift of the divider register + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-output-names + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/apm,xgene-socpll-clock.yaml b/sys/contrib/device-tree/Bindings/clock/apm,xgene-socpll-clock.yaml new file mode 100644 index 000000000000..bdd4a6b92bbd --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/apm,xgene-socpll-clock.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks + +maintainers: + - Khuong Dinh <khuong@os.amperecomputing.com> + +properties: + compatible: + items: + - enum: + - apm,xgene-pcppll-clock + - apm,xgene-pcppll-v2-clock + - apm,xgene-pmd-clock + - apm,xgene-socpll-clock + - apm,xgene-socpll-v2-clock + + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ csr-reg, div-reg ] + - const: div-reg + minItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: [ pcppll, socpll ] + + "#clock-cells": + const: 1 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-output-names + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/atmel,at91rm9200-pmc.yaml b/sys/contrib/device-tree/Bindings/clock/atmel,at91rm9200-pmc.yaml index c9eb60776b4d..e803a1fc3681 100644 --- a/sys/contrib/device-tree/Bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/atmel,at91rm9200-pmc.yaml @@ -34,6 +34,8 @@ properties: - enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g45-pmc - atmel,at91sam9n12-pmc - atmel,at91sam9rl-pmc @@ -43,6 +45,7 @@ properties: - atmel,sama5d4-pmc - microchip,sam9x60-pmc - microchip,sam9x7-pmc + - microchip,sama7d65-pmc - microchip,sama7g5-pmc - const: syscon @@ -90,6 +93,7 @@ allOf: enum: - microchip,sam9x60-pmc - microchip,sam9x7-pmc + - microchip,sama7d65-pmc - microchip,sama7g5-pmc then: properties: @@ -109,6 +113,8 @@ allOf: enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g20-pmc then: properties: diff --git a/sys/contrib/device-tree/Bindings/clock/atmel,at91sam9x5-sckc.yaml b/sys/contrib/device-tree/Bindings/clock/atmel,at91sam9x5-sckc.yaml index c2283cd07f05..d4cf8ae2961e 100644 --- a/sys/contrib/device-tree/Bindings/clock/atmel,at91sam9x5-sckc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -20,6 +20,7 @@ properties: - items: - enum: - microchip,sam9x7-sckc + - microchip,sama7d65-sckc - microchip,sama7g5-sckc - const: microchip,sam9x60-sckc diff --git a/sys/contrib/device-tree/Bindings/clock/axis,artpec6-clkctrl.yaml b/sys/contrib/device-tree/Bindings/clock/axis,artpec6-clkctrl.yaml new file mode 100644 index 000000000000..a78269369df8 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/axis,artpec6-clkctrl.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/axis,artpec6-clkctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-6 clock controller + +maintainers: + - Lars Persson <lars.persson@axis.com> + +properties: + compatible: + const: axis,artpec6-clkctrl + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + minItems: 1 + items: + - description: external 50 MHz oscillator. + - description: optional audio reference clock. + - description: fractional audio clock divider 0. + - description: fractional audio clock divider 1. + + clock-names: + minItems: 1 + items: + - const: sys_refclk + - const: i2s_refclk + - const: frac_clk0 + - const: frac_clk1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller@f8000000 { + compatible = "axis,artpec6-clkctrl"; + reg = <0xf8000000 0x48>; + #clock-cells = <1>; + clocks = <&ext_clk>; + clock-names = "sys_refclk"; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/brcm,bcm2835-aux-clock.yaml b/sys/contrib/device-tree/Bindings/clock/brcm,bcm2835-aux-clock.yaml new file mode 100644 index 000000000000..0f4050ffa41c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/brcm,bcm2835-aux-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm2835-aux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 auxiliary peripheral clock + +maintainers: + - Stefan Wahren <wahrenst@gmx.net> + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> + +description: + The auxiliary peripherals (UART, SPI1, and SPI2) have a small register + area controlling clock gating to the peripherals, and providing an IRQ + status register. + +properties: + compatible: + const: brcm,bcm2835-aux + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/bcm2835.h> + clock@7e215000 { + compatible = "brcm,bcm2835-aux"; + reg = <0x7e215000 0x8>; + #clock-cells = <1>; + clocks = <&clocks BCM2835_CLOCK_VPU>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/brcm,bcm2835-cprman.yaml b/sys/contrib/device-tree/Bindings/clock/brcm,bcm2835-cprman.yaml new file mode 100644 index 000000000000..b0cf76c74bc7 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/brcm,bcm2835-cprman.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm2835-cprman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 CPRMAN clocks + +maintainers: + - Stefan Wahren <wahrenst@gmx.net> + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> + +description: + The CPRMAN clock controller generates clocks in the audio power domain of the + BCM2835. There is a level of PLLs deriving from an external oscillator, a + level of PLL dividers that produce channels off of the few PLLs, and a level + of mostly-generic clock generators sourcing from the PLL channels. Most other + hardware components source from the clock generators, but a few (like the ARM + or HDMI) will source from the PLL dividers directly. + +properties: + compatible: + enum: + - brcm,bcm2711-cprman + - brcm,bcm2835-cprman + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + items: + - description: External oscillator clock. + - description: DSI0 byte clock. + - description: DSI0 DDR2 clock. + - description: DSI0 DDR clock. + - description: DSI1 byte clock. + - description: DSI1 DDR2 clock. + - description: DSI1 DDR clock. + +additionalProperties: false + +required: + - compatible + - '#clock-cells' + - reg + - clocks + +examples: + - | + clock-controller@7e101000 { + compatible = "brcm,bcm2835-cprman"; + reg = <0x7e101000 0x2000>; + #clock-cells = <1>; + clocks = <&clk_osc>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/brcm,bcm53573-ilp.yaml b/sys/contrib/device-tree/Bindings/clock/brcm,bcm53573-ilp.yaml new file mode 100644 index 000000000000..cd291f428a8d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/brcm,bcm53573-ilp.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm53573-ilp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM53573 ILP clock + +maintainers: + - Rafał Miłecki <rafal@milecki.pl> + +description: > + ILP clock (sometimes referred as "slow clock") on Broadcom BCM53573 devices + using Cortex-A7 CPU. + + ILP's rate has to be calculated on runtime and it depends on ALP clock which + has to be referenced. + + This clock is part of PMU (Power Management Unit), a Broadcom device handling + power-related aspects. Its node must be sub-node of the PMU device. + +properties: + compatible: + items: + - const: brcm,bcm53573-ilp + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + clock-output-names: + items: + - const: ilp + +additionalProperties: false + +examples: + - | + ilp { + compatible = "brcm,bcm53573-ilp"; + clocks = <&alp>; + #clock-cells = <0>; + clock-output-names = "ilp"; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/brcm,bcm63xx-clocks.yaml b/sys/contrib/device-tree/Bindings/clock/brcm,bcm63xx-clocks.yaml new file mode 100644 index 000000000000..56909ea499a2 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/brcm,bcm63xx-clocks.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm63xx-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS based BCM63XX SoCs Gated Clock Controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +properties: + compatible: + enum: + - brcm,bcm3368-clocks + - brcm,bcm6318-clocks + - brcm,bcm6318-ubus-clocks + - brcm,bcm6328-clocks + - brcm,bcm6358-clocks + - brcm,bcm6362-clocks + - brcm,bcm6368-clocks + - brcm,bcm63268-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000004 { + compatible = "brcm,bcm6328-clocks"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/cirrus,ep7209-clk.yaml b/sys/contrib/device-tree/Bindings/clock/cirrus,ep7209-clk.yaml new file mode 100644 index 000000000000..fbd0d50d46a8 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/cirrus,ep7209-clk.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cirrus,ep7209-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CLPS711X Clock Controller + +maintainers: + - Alexander Shiyan <shc_work@mail.ru> + +description: + See include/dt-bindings/clock/clps711x-clock.h for the full list of CLPS711X + clock IDs. + +properties: + compatible: + items: + - const: cirrus,ep7312-clk + - const: cirrus,ep7209-clk + + reg: + maxItems: 1 + + startup-frequency: + description: Factory set CPU startup frequency in HZ. + $ref: /schemas/types.yaml#/definitions/uint32 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - startup-frequency + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@80000000 { + compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk"; + reg = <0x80000000 0xc000>; + #clock-cells = <1>; + startup-frequency = <73728000>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/fsl,vf610-ccm.yaml b/sys/contrib/device-tree/Bindings/clock/fsl,vf610-ccm.yaml new file mode 100644 index 000000000000..29ae5be51acf --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/fsl,vf610-ccm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,vf610-ccm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock for Freescale Vybrid VF610 SOC + +description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h + for the full list of VF610 clock IDs + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,vf610-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: external crystal oscillator 32KHz, recommended + - description: external crystal oscillator 24MHz, recommended + - description: audio + - description: enet + minItems: 2 + + clock-names: + items: + - const: sxosc + - const: fxosc + - const: enet_ext + - const: audio_ext + minItems: 2 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + clock-controller@4006b000 { + compatible = "fsl,vf610-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; + clocks = <&sxosc>, <&fxosc>; + clock-names = "sxosc", "fxosc"; + }; + diff --git a/sys/contrib/device-tree/Bindings/clock/gated-fixed-clock.yaml b/sys/contrib/device-tree/Bindings/clock/gated-fixed-clock.yaml new file mode 100644 index 000000000000..d3e0faf3c64d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/gated-fixed-clock.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gated Fixed clock + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + const: gated-fixed-clock + + "#clock-cells": + const: 0 + + clock-frequency: true + + clock-output-names: + maxItems: 1 + + enable-gpios: + description: + Contains a single GPIO specifier for the GPIO that enables and disables + the oscillator. + maxItems: 1 + + vdd-supply: + description: handle of the regulator that provides the supply voltage + +required: + - compatible + - "#clock-cells" + - clock-frequency + - vdd-supply + +additionalProperties: false + +examples: + - | + clock-1000000000 { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + vdd-supply = <®_vdd>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/img,pistachio-clk.yaml b/sys/contrib/device-tree/Bindings/clock/img,pistachio-clk.yaml new file mode 100644 index 000000000000..e70feee8e894 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/img,pistachio-clk.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination Technologies Pistachio SoC clock controllers + +maintainers: + - Andrew Bresticker <abrestic@chromium.org> + +description: | + Pistachio has four clock controllers (core clock, peripheral clock, peripheral + general control, and top general control) which are instantiated individually + from the device-tree. + + Core clock controller: + + The core clock controller generates clocks for the CPU, RPU (WiFi + BT + co-processor), audio, and several peripherals. + + Peripheral clock controller: + + The peripheral clock controller generates clocks for the DDR, ROM, and other + peripherals. The peripheral system clock ("periph_sys") generated by the core + clock controller is the input clock to the peripheral clock controller. + + Peripheral general control: + + The peripheral general control block generates system interface clocks and + resets for various peripherals. It also contains miscellaneous peripheral + control registers. + + Top-level general control: + + The top-level general control block contains miscellaneous control registers + and gates for the external clocks "audio_clk_in" and "enet_clk_in". + +properties: + compatible: + items: + - enum: + - img,pistachio-clk + - img,pistachio-clk-periph + - img,pistachio-cr-periph + - img,pistachio-cr-top + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: img,pistachio-clk + then: + properties: + clocks: + items: + - description: External 52Mhz oscillator + - description: Alternate audio reference clock + - description: Alternate ethernet PHY clock + + clock-names: + items: + - const: xtal + - const: audio_refclk_ext_gate + - const: ext_enet_in_gate + + - if: + properties: + compatible: + contains: + const: img,pistachio-clk-periph + then: + properties: + clocks: + items: + - description: Peripheral system clock + + clock-names: + items: + - const: periph_sys_core + + - if: + properties: + compatible: + contains: + const: img,pistachio-cr-periph + then: + properties: + clocks: + items: + - description: System interface clock + + clock-names: + items: + - const: sys + + - if: + properties: + compatible: + contains: + const: img,pistachio-cr-top + then: + properties: + clocks: + items: + - description: External audio reference clock + - description: External ethernet PHY clock + + clock-names: + items: + - const: audio_clk_in + - const: enet_clk_in + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/imx8m-clock.yaml b/sys/contrib/device-tree/Bindings/clock/imx8m-clock.yaml index c643d4a81478..4fec55832702 100644 --- a/sys/contrib/device-tree/Bindings/clock/imx8m-clock.yaml +++ b/sys/contrib/device-tree/Bindings/clock/imx8m-clock.yaml @@ -43,6 +43,13 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h for the full list of i.MX8M clock IDs. + fsl,operating-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [nominal, overdrive] + description: + The operating mode of the SoC. This affects the maximum clock rates that + can safely be configured by the clock controller. + required: - compatible - reg @@ -109,6 +116,7 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,operating-mode = "nominal"; }; - | diff --git a/sys/contrib/device-tree/Bindings/clock/imx8mp-audiomix.yaml b/sys/contrib/device-tree/Bindings/clock/imx8mp-audiomix.yaml index 6588a17a7d9a..0272c9527037 100644 --- a/sys/contrib/device-tree/Bindings/clock/imx8mp-audiomix.yaml +++ b/sys/contrib/device-tree/Bindings/clock/imx8mp-audiomix.yaml @@ -24,8 +24,8 @@ properties: maxItems: 1 clocks: - minItems: 7 - maxItems: 7 + minItems: 8 + maxItems: 8 clock-names: items: @@ -36,6 +36,7 @@ properties: - const: sai5 - const: sai6 - const: sai7 + - const: axi '#clock-cells': const: 1 @@ -72,10 +73,11 @@ examples: <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; }; diff --git a/sys/contrib/device-tree/Bindings/clock/imx93-clock.yaml b/sys/contrib/device-tree/Bindings/clock/imx93-clock.yaml index ccb53c6b96c1..98c0800732ef 100644 --- a/sys/contrib/device-tree/Bindings/clock/imx93-clock.yaml +++ b/sys/contrib/device-tree/Bindings/clock/imx93-clock.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - fsl,imx91-ccm - fsl,imx93-ccm reg: diff --git a/sys/contrib/device-tree/Bindings/clock/lsi,axm5516-clks.yaml b/sys/contrib/device-tree/Bindings/clock/lsi,axm5516-clks.yaml new file mode 100644 index 000000000000..7a792dbeffb3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/lsi,axm5516-clks.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2025 LSI +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/lsi,axm5516-clks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LSI AXM5516 Clock Controller + +maintainers: + - Anders Berg <anders.berg@lsi.com> + +description: + See <dt-bindings/clock/lsi,axxia-clock.h> for the list of supported clock IDs. + +properties: + compatible: + const: lsi,axm5516-clks + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <1>; + clock-controller@2010020000 { + compatible = "lsi,axm5516-clks"; + #clock-cells = <1>; + reg = <0x20 0x10020000 0x20000>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/lsi,nspire-cx-clock.yaml b/sys/contrib/device-tree/Bindings/clock/lsi,nspire-cx-clock.yaml new file mode 100644 index 000000000000..52c217d210d0 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/lsi,nspire-cx-clock.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/lsi,nspire-cx-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE Clocks + +maintainers: + - Daniel Tang <dt.tangr@gmail.com> + +properties: + compatible: + enum: + - lsi,nspire-cx-ahb-divider + - lsi,nspire-classic-ahb-divider + - lsi,nspire-cx-clock + - lsi,nspire-classic-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + +additionalProperties: false + +required: + - compatible + - reg diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,armada-370-corediv-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,armada-370-corediv-clock.yaml new file mode 100644 index 000000000000..9d766558cdb9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,armada-370-corediv-clock.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/marvell,armada-370-corediv-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MVEBU Core Divider Clock + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + oneOf: + - enum: + - marvell,armada-370-corediv-clock + - marvell,armada-375-corediv-clock + - marvell,armada-380-corediv-clock + - marvell,mv98dx3236-corediv-clock + - items: + - const: marvell,armada-390-corediv-clock + - const: marvell,armada-380-corediv-clock + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + clock-controller@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; + #clock-cells = <1>; + clocks = <&pll>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,armada-3700-periph-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,armada-3700-periph-clock.yaml new file mode 100644 index 000000000000..87e8e4ca111a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,armada-3700-periph-clock.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 37xx SoCs Peripheral Clocks + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +description: > + Marvell Armada 37xx SoCs provide peripheral clocks which are used as clock + source for the peripheral of the SoC. + + There are two different blocks associated to north bridge and south bridge. + + The following is a list of provided IDs for Armada 3700 North bridge clocks: + + ID Clock name Description + ----------------------------------- + 0 mmc MMC controller + 1 sata_host Sata Host + 2 sec_at Security AT + 3 sac_dap Security DAP + 4 tsecm Security Engine + 5 setm_tmx Serial Embedded Trace Module + 6 avs Adaptive Voltage Scaling + 7 sqf SPI + 8 pwm PWM + 9 i2c_2 I2C 2 + 10 i2c_1 I2C 1 + 11 ddr_phy DDR PHY + 12 ddr_fclk DDR F clock + 13 trace Trace + 14 counter Counter + 15 eip97 EIP 97 + 16 cpu CPU + + The following is a list of provided IDs for Armada 3700 South bridge clocks: + + ID Clock name Description + ----------------------------------- + 0 gbe-50 50 MHz parent clock for Gigabit Ethernet + 1 gbe-core parent clock for Gigabit Ethernet core + 2 gbe-125 125 MHz parent clock for Gigabit Ethernet + 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 + 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 + 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 + 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0 + 7 gbe1-core Gigabit Ethernet core port 1 + 8 gbe0-core Gigabit Ethernet core port 0 + 9 gbe-bm Gigabit Ethernet Buffer Manager + 10 sdio SDIO + 11 usb32-sub2-sys USB 2 clock + 12 usb32-ss-sys USB 3 clock + 13 pcie PCIe controller + +properties: + compatible: + oneOf: + - const: marvell,armada-3700-periph-clock-sb + - items: + - const: marvell,armada-3700-periph-clock-nb + - const: syscon + reg: + maxItems: 1 + + clocks: + items: + - description: TBG-A P clock and specifier + - description: TBG-B P clock and specifier + - description: TBG-A S clock and specifier + - description: TBG-B S clock and specifier + - description: Xtal clock and specifier + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13000{ + compatible = "marvell,armada-3700-periph-clock-sb"; + reg = <0x13000 0x1000>; + clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,armada-3700-tbg-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,armada-3700-tbg-clock.yaml new file mode 100644 index 000000000000..7fd1d758f794 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,armada-3700-tbg-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,armada-3700-tbg-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 3700 Time Base Generator Clock + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +description: > + Marvell Armada 37xx SoCs provide Time Base Generator clocks which are used as + parent clocks for the peripheral clocks. + + The TBG clock consumer should specify the desired clock by having the clock ID + in its "clocks" phandle cell. + + The following is a list of provided IDs and clock names on Armada 3700: + + 0 = TBG A P + 1 = TBG B P + 2 = TBG A S + 3 = TBG B S + +properties: + compatible: + const: marvell,armada-3700-tbg-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13200 { + compatible = "marvell,armada-3700-tbg-clock"; + reg = <0x13200 0x1000>; + clocks = <&xtalclk>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,armada-xp-cpu-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,armada-xp-cpu-clock.yaml new file mode 100644 index 000000000000..f2ac6741da9a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,armada-xp-cpu-clock.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$schema: http://devicetree.org/meta-schemas/core.yaml# +$id: http://devicetree.org/schemas/clock/marvell,armada-xp-cpu-clock.yaml# + +title: Marvell EBU CPU Clock + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + compatible: + enum: + - marvell,armada-xp-cpu-clock + - marvell,mv98dx3236-cpu-clock + + reg: + items: + - description: Clock complex registers + - description: PMU DFS registers + + '#clock-cells': + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + clock-controller@d0018700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clock"; + reg = <0xd0018700 0xa0>, <0x1c054 0x10>; + clocks = <&coreclk 1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,berlin2-clk.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,berlin2-clk.yaml new file mode 100644 index 000000000000..8d48a2c7e381 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,berlin2-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Berlin Clock Controller + +maintainers: + - Jisheng Zhang <jszhang@kernel.org> + +description: + Clock related registers are spread among the chip control registers. Berlin + clock node should be a sub-node of the chip controller node. Marvell Berlin2 + (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor + differences in features and register layout. + +properties: + compatible: + enum: + - marvell,berlin2-clk + - marvell,berlin2q-clk + + '#clock-cells': + const: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - enum: + - refclk + - video_ext0 + +required: + - compatible + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "marvell,berlin2q-clk"; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,dove-divider-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,dove-divider-clock.yaml new file mode 100644 index 000000000000..7a8e0e281b63 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,dove-divider-clock.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Dove PLL Divider Clock + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +description: > + Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide + high speed clocks for a number of peripherals. These dividers are part of the + PMU, and thus this node should be a child of the PMU node. + + The following clocks are provided: + + ID Clock + ------------- + 0 AXI bus clock + 1 GPU clock + 2 VMeta clock + 3 LCD clock + +properties: + compatible: + const: marvell,dove-divider-clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@64 { + compatible = "marvell,dove-divider-clock"; + reg = <0x0064 0x8>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,mvebu-core-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,mvebu-core-clock.yaml new file mode 100644 index 000000000000..215bcd9080c3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,mvebu-core-clock.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MVEBU SoC core clock + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +description: > + Marvell MVEBU SoCs usually allow to determine core clock frequencies by + reading the Sample-At-Reset (SAR) register. The core clock consumer should + specify the desired clock by having the clock ID in its "clocks" phandle cell. + + The following is a list of provided IDs and clock names on Armada 370/XP: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = nbclk (L2 Cache clock) + 3 = hclk (DRAM control clock) + 4 = dramclk (DDR clock) + + The following is a list of provided IDs and clock names on Armada 375: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = l2clk (L2 Cache clock) + 3 = ddrclk (DDR clock) + + The following is a list of provided IDs and clock names on Armada 380/385: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = l2clk (L2 Cache clock) + 3 = ddrclk (DDR clock) + + The following is a list of provided IDs and clock names on Armada 39x: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = nbclk (Coherent Fabric clock) + 3 = hclk (SDRAM Controller Internal Clock) + 4 = dclk (SDRAM Interface Clock) + 5 = refclk (Reference Clock) + + The following is a list of provided IDs and clock names on 98dx3236: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = ddrclk (DDR clock) + 3 = mpll (MPLL Clock) + + The following is a list of provided IDs and clock names on Kirkwood and Dove: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU0 clock) + 2 = l2clk (L2 Cache clock derived from CPU0 clock) + 3 = ddrclk (DDR controller clock derived from CPU0 clock) + + The following is a list of provided IDs and clock names on Orion5x: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU0 clock) + 2 = ddrclk (DDR controller clock derived from CPU0 clock) + +properties: + compatible: + enum: + - marvell,armada-370-core-clock + - marvell,armada-375-core-clock + - marvell,armada-380-core-clock + - marvell,armada-390-core-clock + - marvell,armada-xp-core-clock + - marvell,dove-core-clock + - marvell,kirkwood-core-clock + - marvell,mv88f5181-core-clock + - marvell,mv88f5182-core-clock + - marvell,mv88f5281-core-clock + - marvell,mv88f6180-core-clock + - marvell,mv88f6183-core-clock + - marvell,mv98dx1135-core-clock + - marvell,mv98dx3236-core-clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-output-names: + description: Overwrite default clock output names. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/marvell,pxa1908.yaml b/sys/contrib/device-tree/Bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..4e78933232b6 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović <duje.mihanovic@skole.hr> + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>. + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/marvell-armada-370-gating-clock.yaml b/sys/contrib/device-tree/Bindings/clock/marvell-armada-370-gating-clock.yaml new file mode 100644 index 000000000000..0475360d2b6a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/marvell-armada-370-gating-clock.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/clock/marvell-armada-370-gating-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell EBU SoC gating-clock + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +description: > + Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some peripheral + clocks to be gated to save some power. The clock ID is directly mapped to the + corresponding clock gating control bit in HW to ease manual clock lookup in + datasheet. + + The following is a list of provided IDs for Armada 370: + + ID Clock Peripheral + ----------------------------------- + 0 Audio AC97 Cntrl + 1 pex0_en PCIe 0 Clock out + 2 pex1_en PCIe 1 Clock out + 3 ge1 Gigabit Ethernet 1 + 4 ge0 Gigabit Ethernet 0 + 5 pex0 PCIe Cntrl 0 + 9 pex1 PCIe Cntrl 1 + 15 sata0 SATA Host 0 + 17 sdio SDHCI Host + 23 crypto CESA (crypto engine) + 25 tdm Time Division Mplx + 28 ddr DDR Cntrl + 30 sata1 SATA Host 0 + + The following is a list of provided IDs for Armada 375: + + ID Clock Peripheral + ----------------------------------- + 2 mu Management Unit + 3 pp Packet Processor + 4 ptp PTP + 5 pex0 PCIe 0 Clock out + 6 pex1 PCIe 1 Clock out + 8 audio Audio Cntrl + 11 nd_clk Nand Flash Cntrl + 14 sata0_link SATA 0 Link + 15 sata0_core SATA 0 Core + 16 usb3 USB3 Host + 17 sdio SDHCI Host + 18 usb USB Host + 19 gop Gigabit Ethernet MAC + 20 sata1_link SATA 1 Link + 21 sata1_core SATA 1 Core + 22 xor0 XOR DMA 0 + 23 xor1 XOR DMA 0 + 24 copro Coprocessor + 25 tdm Time Division Mplx + 28 crypto0_enc Cryptographic Unit Port 0 Encryption + 29 crypto0_core Cryptographic Unit Port 0 Core + 30 crypto1_enc Cryptographic Unit Port 1 Encryption + 31 crypto1_core Cryptographic Unit Port 1 Core + + The following is a list of provided IDs for Armada 380/385: + + ID Clock Peripheral + ----------------------------------- + 0 audio Audio + 2 ge2 Gigabit Ethernet 2 + 3 ge1 Gigabit Ethernet 1 + 4 ge0 Gigabit Ethernet 0 + 5 pex1 PCIe 1 + 6 pex2 PCIe 2 + 7 pex3 PCIe 3 + 8 pex0 PCIe 0 + 9 usb3h0 USB3 Host 0 + 10 usb3h1 USB3 Host 1 + 11 usb3d USB3 Device + 13 bm Buffer Management + 14 crypto0z Cryptographic 0 Z + 15 sata0 SATA 0 + 16 crypto1z Cryptographic 1 Z + 17 sdio SDIO + 18 usb2 USB 2 + 21 crypto1 Cryptographic 1 + 22 xor0 XOR 0 + 23 crypto0 Cryptographic 0 + 25 tdm Time Division Multiplexing + 28 xor1 XOR 1 + 30 sata1 SATA 1 + + The following is a list of provided IDs for Armada 39x: + + ID Clock Peripheral + ----------------------------------- + 5 pex1 PCIe 1 + 6 pex2 PCIe 2 + 7 pex3 PCIe 3 + 8 pex0 PCIe 0 + 9 usb3h0 USB3 Host 0 + 10 usb3h1 USB3 Host 1 + 15 sata0 SATA 0 + 17 sdio SDIO + 22 xor0 XOR 0 + 28 xor1 XOR 1 + + The following is a list of provided IDs for Armada XP: + + ID Clock Peripheral + ----------------------------------- + 0 audio Audio Cntrl + 1 ge3 Gigabit Ethernet 3 + 2 ge2 Gigabit Ethernet 2 + 3 ge1 Gigabit Ethernet 1 + 4 ge0 Gigabit Ethernet 0 + 5 pex0 PCIe Cntrl 0 + 6 pex1 PCIe Cntrl 1 + 7 pex2 PCIe Cntrl 2 + 8 pex3 PCIe Cntrl 3 + 13 bp + 14 sata0lnk + 15 sata0 SATA Host 0 + 16 lcd LCD Cntrl + 17 sdio SDHCI Host + 18 usb0 USB Host 0 + 19 usb1 USB Host 1 + 20 usb2 USB Host 2 + 22 xor0 XOR DMA 0 + 23 crypto CESA engine + 25 tdm Time Division Mplx + 28 xor1 XOR DMA 1 + 29 sata1lnk + 30 sata1 SATA Host 1 + + The following is a list of provided IDs for 98dx3236: + + ID Clock Peripheral + ----------------------------------- + 3 ge1 Gigabit Ethernet 1 + 4 ge0 Gigabit Ethernet 0 + 5 pex0 PCIe Cntrl 0 + 17 sdio SDHCI Host + 18 usb0 USB Host 0 + 22 xor0 XOR DMA 0 + + The following is a list of provided IDs for Dove: + + ID Clock Peripheral + ----------------------------------- + 0 usb0 USB Host 0 + 1 usb1 USB Host 1 + 2 ge Gigabit Ethernet + 3 sata SATA Host + 4 pex0 PCIe Cntrl 0 + 5 pex1 PCIe Cntrl 1 + 8 sdio0 SDHCI Host 0 + 9 sdio1 SDHCI Host 1 + 10 nand NAND Cntrl + 11 camera Camera Cntrl + 12 i2s0 I2S Cntrl 0 + 13 i2s1 I2S Cntrl 1 + 15 crypto CESA engine + 21 ac97 AC97 Cntrl + 22 pdma Peripheral DMA + 23 xor0 XOR DMA 0 + 24 xor1 XOR DMA 1 + 30 gephy Gigabit Ethernet PHY + Note: gephy(30) is implemented as a parent clock of ge(2) + + The following is a list of provided IDs for Kirkwood: + + ID Clock Peripheral + ----------------------------------- + 0 ge0 Gigabit Ethernet 0 + 2 pex0 PCIe Cntrl 0 + 3 usb0 USB Host 0 + 4 sdio SDIO Cntrl + 5 tsu Transp. Stream Unit + 6 dunit SDRAM Cntrl + 7 runit Runit + 8 xor0 XOR DMA 0 + 9 audio I2S Cntrl 0 + 14 sata0 SATA Host 0 + 15 sata1 SATA Host 1 + 16 xor1 XOR DMA 1 + 17 crypto CESA engine + 18 pex1 PCIe Cntrl 1 + 19 ge1 Gigabit Ethernet 1 + 20 tdm Time Division Mplx + +properties: + compatible: + enum: + - marvell,armada-370-gating-clock + - marvell,armada-375-gating-clock + - marvell,armada-380-gating-clock + - marvell,armada-390-gating-clock + - marvell,armada-xp-gating-clock + - marvell,mv98dx3236-gating-clock + - marvell,dove-gating-clock + - marvell,kirkwood-gating-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + /* default parent clock is tclk */ + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/maxim,max9485.yaml b/sys/contrib/device-tree/Bindings/clock/maxim,max9485.yaml new file mode 100644 index 000000000000..f9d8941c7235 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/maxim,max9485.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/maxim,max9485.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX9485 Programmable Audio Clock Generator + +maintainers: + - Daniel Mack <daniel@zonque.org> + +description: > + Maxim MAX9485 Programmable Audio Clock Generator exposes 4 clocks in total: + + - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz + - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete + frequencies + - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT + + MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set + requests. + +properties: + compatible: + const: maxim,max9485 + + reg: + maxItems: 1 + + clocks: + description: Input clock. Must provide 27 MHz + maxItems: 1 + + clock-names: + items: + - const: xclk + + '#clock-cells': + const: 1 + + reset-gpios: + description: > + GPIO descriptor connected to the #RESET input pin + + vdd-supply: + description: A regulator node for Vdd + + clock-output-names: + description: Name of output clocks, as defined in common clock bindings + items: + - const: mclkout + - const: clkout + - const: clkout1 + - const: clkout2 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@63 { + compatible = "maxim,max9485"; + reg = <0x63>; + #clock-cells = <1>; + clock-names = "xclk"; + clocks = <&xo_27mhz>; + reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + vdd-supply = <®_3v3>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,apmixedsys.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,apmixedsys.yaml index db5f48e4dd15..591a9e862c7d 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,apmixedsys.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,apmixedsys.yaml @@ -12,7 +12,8 @@ maintainers: description: The Mediatek apmixedsys controller provides PLLs to the system. - The clock values can be found in <dt-bindings/clock/mt*-clk.h>. + The clock values can be found in <dt-bindings/clock/mt*-clk.h> + and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>. properties: compatible: @@ -34,6 +35,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixed - mediatek,mt6795-apmixedsys diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,infracfg.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,infracfg.yaml index 252c46d316ee..d1d30700d9b0 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,infracfg.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,infracfg.yaml @@ -11,9 +11,10 @@ maintainers: description: The Mediatek infracfg controller provides various clocks and reset outputs - to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>, - and reset values in <dt-bindings/reset/mt*-reset.h> and - <dt-bindings/reset/mt*-resets.h>. + to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h> + and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in + <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and + <dt-bindings/reset/mediatek,mt*-infracfg.h>. properties: compatible: @@ -22,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6795-infracfg - mediatek,mt6779-infracfg_ao diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,mt8188-clock.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,mt8188-clock.yaml index 860570320545..5403242545ab 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,mt8188-clock.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,mt8188-clock.yaml @@ -52,11 +52,35 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + + then: + required: + - '#reset-cells' + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,mtmips-sysc.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,mtmips-sysc.yaml index ba7ffc5b16a0..56bbd69b16d9 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,mtmips-sysc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,mtmips-sysc.yaml @@ -18,27 +18,38 @@ description: | These SoCs have an XTAL from where the cpu clock is provided as well as derived clocks for the bus and the peripherals. + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>. + properties: compatible: - items: - - enum: - - ralink,mt7620-sysc - - ralink,mt7628-sysc - - ralink,mt7688-sysc - - ralink,rt2880-sysc - - ralink,rt3050-sysc - - ralink,rt3052-sysc - - ralink,rt3352-sysc - - ralink,rt3883-sysc - - ralink,rt5350-sysc - - const: syscon + oneOf: + - items: + - enum: + - ralink,mt7620-sysc + - ralink,mt7688-sysc + - ralink,rt2880-sysc + - ralink,rt3050-sysc + - ralink,rt3052-sysc + - ralink,rt3352-sysc + - ralink,rt3883-sysc + - ralink,rt5350-sysc + - const: syscon + - items: + - const: ralink,mt7628-sysc + - const: ralink,mt7688-sysc + - const: syscon reg: maxItems: 1 '#clock-cells': description: - The first cell indicates the clock number. + The first cell indicates the clock number, see [1] for available + clocks. const: 1 '#reset-cells': @@ -56,6 +67,8 @@ additionalProperties: false examples: - | + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> + syscon@0 { compatible = "ralink,rt5350-sysc", "syscon"; reg = <0x0 0x100>; diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,pericfg.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,pericfg.yaml index 2f06baecfd23..b98cf45efe2f 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,pericfg.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt6795-pericfg - mediatek,mt7622-pericfg diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,syscon.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,syscon.yaml index 10483e26878f..a86a64893c67 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,syscon.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,syscon.yaml @@ -28,6 +28,10 @@ properties: - mediatek,mt2712-mfgcfg - mediatek,mt2712-vdecsys - mediatek,mt2712-vencsys + - mediatek,mt6735-imgsys + - mediatek,mt6735-mfgcfg + - mediatek,mt6735-vdecsys + - mediatek,mt6735-vencsys - mediatek,mt6765-camsys - mediatek,mt6765-imgsys - mediatek,mt6765-mipi0a diff --git a/sys/contrib/device-tree/Bindings/clock/mediatek,topckgen.yaml b/sys/contrib/device-tree/Bindings/clock/mediatek,topckgen.yaml index bdf3b55bd56f..c080fb0a1618 100644 --- a/sys/contrib/device-tree/Bindings/clock/mediatek,topckgen.yaml +++ b/sys/contrib/device-tree/Bindings/clock/mediatek,topckgen.yaml @@ -12,7 +12,8 @@ maintainers: description: The Mediatek topckgen controller provides various clocks to the system. - The clock values can be found in <dt-bindings/clock/mt*-clk.h>. + The clock values can be found in <dt-bindings/clock/mt*-clk.h> and + <dt-bindings/clock/mediatek,mt*-topckgen.h>. properties: compatible: @@ -31,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen - mediatek,mt6795-topckgen diff --git a/sys/contrib/device-tree/Bindings/clock/microchip,lan966x-gck.yaml b/sys/contrib/device-tree/Bindings/clock/microchip,lan966x-gck.yaml index df2bec188706..16106e8b637f 100644 --- a/sys/contrib/device-tree/Bindings/clock/microchip,lan966x-gck.yaml +++ b/sys/contrib/device-tree/Bindings/clock/microchip,lan966x-gck.yaml @@ -16,7 +16,18 @@ description: | properties: compatible: - const: microchip,lan966x-gck + oneOf: + - enum: + - microchip,lan966x-gck + - microchip,lan9691-gck + - items: + - enum: + - microchip,lan9698-gck + - microchip,lan9696-gck + - microchip,lan9694-gck + - microchip,lan9693-gck + - microchip,lan9692-gck + - const: microchip,lan9691-gck reg: minItems: 1 diff --git a/sys/contrib/device-tree/Bindings/clock/microchip,pic32mzda-clk.yaml b/sys/contrib/device-tree/Bindings/clock/microchip,pic32mzda-clk.yaml new file mode 100644 index 000000000000..a14a838140f1 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/microchip,pic32mzda-clk.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,pic32mzda-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32MZDA Clock Controller + +maintainers: + - Purna Chandra Mandal <purna.mandal@microchip.com> + +description: + Microchip clock controller consists of a few oscillators, PLL, multiplexer + and divider modules. + +properties: + compatible: + const: microchip,pic32mzda-clk + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + microchip,pic32mzda-sosc: + description: Presence of secondary oscillator. + type: boolean + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1f801200 { + compatible = "microchip,pic32mzda-clk"; + reg = <0x1f801200 0x200>; + #clock-cells = <1>; + /* optional */ + microchip,pic32mzda-sosc; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/moxa,moxart-clock.yaml b/sys/contrib/device-tree/Bindings/clock/moxa,moxart-clock.yaml new file mode 100644 index 000000000000..bcf7cc240eba --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/moxa,moxart-clock.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/moxa,moxart-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MOXA ART Clock Controllers + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + MOXA ART SoCs allow to determine PLL output and APB frequencies by reading + registers holding multiplier and divisor information. + +properties: + compatible: + enum: + - moxa,moxart-apb-clock + - moxa,moxart-pll-clock + + "#clock-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-output-names: true + +additionalProperties: false + +required: + - compatible + - "#clock-cells" + - reg diff --git a/sys/contrib/device-tree/Bindings/clock/nuvoton,npcm750-clk.yaml b/sys/contrib/device-tree/Bindings/clock/nuvoton,npcm750-clk.yaml new file mode 100644 index 000000000000..694dac68619c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/nuvoton,npcm750-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,npcm750-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM7XX Clock Controller + +maintainers: + - Tali Perry <tali.perry1@gmail.com> + +description: > + Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which + generates and supplies clocks to all modules within the BMC. + + External clocks: + + There are six fixed clocks that are generated outside the BMC. All clocks are of + a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and + clk_sysbypck are inputs to the clock controller. + clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the + network. They are set on the device tree, but not used by the clock module. The + network devices use them directly. + + All available clocks are defined as preprocessor macros in: + dt-bindings/clock/nuvoton,npcm7xx-clock.h + and can be reused as DT sources. + +properties: + compatible: + const: nuvoton,npcm750-clk + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-names: + items: + - const: refclk + - const: sysbypck + - const: mcbypck + + clocks: + items: + - description: refclk + - description: sysbypck + - description: mcbypck + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/nxp,imx95-blk-ctl.yaml b/sys/contrib/device-tree/Bindings/clock/nxp,imx95-blk-ctl.yaml index 5dc360b2ea4b..27403b4c52d6 100644 --- a/sys/contrib/device-tree/Bindings/clock/nxp,imx95-blk-ctl.yaml +++ b/sys/contrib/device-tree/Bindings/clock/nxp,imx95-blk-ctl.yaml @@ -13,9 +13,12 @@ properties: compatible: items: - enum: - - nxp,imx95-lvds-csr - - nxp,imx95-display-csr + - nxp,imx94-display-csr + - nxp,imx94-lvds-csr - nxp,imx95-camera-csr + - nxp,imx95-display-csr + - nxp,imx95-hsio-blk-ctl + - nxp,imx95-lvds-csr - nxp,imx95-netcmix-blk-ctrl - nxp,imx95-vpu-csr - const: syscon diff --git a/sys/contrib/device-tree/Bindings/clock/nxp,lpc1850-ccu.yaml b/sys/contrib/device-tree/Bindings/clock/nxp,lpc1850-ccu.yaml new file mode 100644 index 000000000000..5459038cc954 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/nxp,lpc1850-ccu.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nxp,lpc1850-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC1850 Clock Control Unit (CCU) + +description: + Each CGU base clock has several clock branches which can be turned on + or off independently by the Clock Control Units CCU1 or CCU2. The + branch clocks are distributed between CCU1 and CCU2. + + Above text taken from NXP LPC1850 User Manual + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: nxp,lpc1850-ccu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 8 + + clock-names: + minItems: 1 + maxItems: 8 + items: + enum: + - base_usb0_clk + - base_periph_clk + - base_usb1_clk + - base_cpu_clk + - base_spifi_clk + - base_spi_clk + - base_apb1_clk + - base_apb3_clk + - base_adchs_clk + - base_sdio_clk + - base_ssp0_clk + - base_ssp1_clk + - base_uart0_clk + - base_uart1_clk + - base_uart2_clk + - base_uart3_clk + - base_audio_clk + description: + Which branch clocks that are available on the CCU depends on the + specific LPC part. Check the user manual for your specific part. + + A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h. + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/lpc18xx-cgu.h> + + clock-controller@40051000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40051000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, + <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, + <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, + <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; + clock-names = "base_apb3_clk", "base_apb1_clk", + "base_spifi_clk", "base_cpu_clk", + "base_periph_clk", "base_usb0_clk", + "base_usb1_clk", "base_spi_clk"; + }; + + - | + #include <dt-bindings/clock/lpc18xx-cgu.h> + + clock-controller@40052000 { + compatible = "nxp,lpc1850-ccu"; + reg = <0x40052000 0x1000>; + #clock-cells = <1>; + clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, + <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, + <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, + <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; + clock-names = "base_audio_clk", "base_uart3_clk", + "base_uart2_clk", "base_uart1_clk", + "base_uart0_clk", "base_ssp1_clk", + "base_ssp0_clk", "base_sdio_clk"; + }; + diff --git a/sys/contrib/device-tree/Bindings/clock/nxp,lpc1850-cgu.yaml b/sys/contrib/device-tree/Bindings/clock/nxp,lpc1850-cgu.yaml new file mode 100644 index 000000000000..ed178c7df00c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/nxp,lpc1850-cgu.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC1850 Clock Generation Unit (CGU) + +description: > + The CGU generates multiple independent clocks for the core and the + peripheral blocks of the LPC18xx. Each independent clock is called + a base clock and itself is one of the inputs to the two Clock + Control Units (CCUs) which control the branch clocks to the + individual peripherals. + + The CGU selects the inputs to the clock generators from multiple + clock sources, controls the clock generation, and routes the outputs + of the clock generators through the clock source bus to the output + stages. Each output stage provides an independent clock source and + corresponds to one of the base clocks for the LPC18xx. + + Above text taken from NXP LPC1850 User Manual. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: nxp,lpc1850-cgu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: | + Which base clocks that are available on the CGU depends on the + specific LPC part. Base clocks are numbered from 0 to 27. + + Number: Name: Description: + 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT + 1 BASE_USB0_CLK Base clock for USB0 + 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem, + SPI, and SGPIO + 3 BASE_USB1_CLK Base clock for USB1 + 4 BASE_CPU_CLK System base clock for ARM Cortex-M core + and APB peripheral blocks #0 and #2 + 5 BASE_SPIFI_CLK Base clock for SPIFI + 6 BASE_SPI_CLK Base clock for SPI + 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock + 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock + 9 BASE_APB1_CLK Base clock for APB peripheral block # 1 + 10 BASE_APB3_CLK Base clock for APB peripheral block # 3 + 11 BASE_LCD_CLK Base clock for LCD + 12 BASE_ADCHS_CLK Base clock for ADCHS + 13 BASE_SDIO_CLK Base clock for SD/MMC + 14 BASE_SSP0_CLK Base clock for SSP0 + 15 BASE_SSP1_CLK Base clock for SSP1 + 16 BASE_UART0_CLK Base clock for UART0 + 17 BASE_UART1_CLK Base clock for UART1 + 18 BASE_UART2_CLK Base clock for UART2 + 19 BASE_UART3_CLK Base clock for UART3 + 20 BASE_OUT_CLK Base clock for CLKOUT pin + 24-21 - Reserved + 25 BASE_AUDIO_CLK Base clock for audio system (I2S) + 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output + 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output + + BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx. + BASE_ADCHS_CLK is only available on LPC4370. + + clocks: + maxItems: 5 + + clock-indices: + minItems: 1 + maxItems: 28 + + clock-output-names: + minItems: 1 + maxItems: 28 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@40050000 { + compatible = "nxp,lpc1850-cgu"; + reg = <0x40050000 0x1000>; + #clock-cells = <1>; + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + }; + diff --git a/sys/contrib/device-tree/Bindings/clock/qca,ath79-pll.yaml b/sys/contrib/device-tree/Bindings/clock/qca,ath79-pll.yaml new file mode 100644 index 000000000000..69863e8a4648 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qca,ath79-pll.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros ATH79 PLL controller + +maintainers: + - Alban Bedel <albeu@free.fr> + - Antony Pavlov <antonynpavlov@gmail.com> + +description: > + The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. + +properties: + compatible: + oneOf: + - items: + - const: qca,ar9132-pll + - const: qca,ar9130-pll + - items: + - enum: + - qca,ar7100-pll + - qca,ar7240-pll + - qca,ar9130-pll + - qca,ar9330-pll + - qca,ar9340-pll + - qca,qca9530-pll + - qca,qca9550-pll + - qca,qca9560-pll + + reg: + maxItems: 1 + + clock-names: + items: + - const: ref + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + + clock-output-names: + items: + - const: cpu + - const: ddr + - const: ahb + +required: + - compatible + - reg + - clock-names + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@18050000 { + compatible = "qca,ar9132-pll", "qca,ar9130-pll"; + reg = <0x18050000 0x20>; + clock-names = "ref"; + clocks = <&extosc>; + #clock-cells = <1>; + clock-output-names = "cpu", "ddr", "ahb"; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,camcc-sm8250.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,camcc-sm8250.yaml index 3fd3dc1069fb..5c3ff37ec0d7 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,camcc-sm8250.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,camcc-sm8250.yaml @@ -13,7 +13,7 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8250. - See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h + See also: include/dt-bindings/clock/qcom,camcc-sm8250.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6125.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6125.yaml index 0a3ef7fd03fa..ef2b1e204430 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6125.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6125.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks and power domains on SM6125. - See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h + See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6350.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6350.yaml index 46403b98411f..a602e882e964 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6350.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6350.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM6350. - See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h + See also: include/dt-bindings/clock/qcom,dispcc-sm6350.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq4019.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq4019.yaml index 012048921f92..c91039dc100e 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq4019.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq4019.yaml @@ -15,7 +15,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on IPQ4019. - See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h + See also: include/dt-bindings/clock/qcom,gcc-ipq4019.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq8074.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq8074.yaml index 38b9e4283900..00d7df75b3d6 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq8074.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq8074.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on IPQ8074. - See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h + See also: include/dt-bindings/clock/qcom,gcc-ipq8074.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml index cd49704dcb95..92195091a919 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8976. - See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h + See also: include/dt-bindings/clock/qcom,gcc-msm8976.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8994.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8994.yaml index 10afe984e2fb..93bcd61461e7 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8994.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8994.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8994 and MSM8992. - See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h + See also: include/dt-bindings/clock/qcom,gcc-msm8994.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8996.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8996.yaml index 013fd074a8d5..64796f45f294 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8996.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8996.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module which provides the clocks, resets and power domains on MSM8996. - See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h + See also: include/dt-bindings/clock/qcom,gcc-msm8996.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8998.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8998.yaml index abae658c0ed9..d882f2b6620e 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8998.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8998.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8998. - See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h + See also: include/dt-bindings/clock/qcom,gcc-msm8998.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcm2290.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcm2290.yaml index 38c4c8c61b3a..b9194fa11e47 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcm2290.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcm2290.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on QCM2290. - See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h + See also: include/dt-bindings/clock/qcom,gcc-qcm2290.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcs404.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcs404.yaml index 94755465c1fb..6b35a3c080a2 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcs404.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcs404.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on QCS404. - See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h + See also: include/dt-bindings/clock/qcom,gcc-qcs404.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7180.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7180.yaml index 1847bbeaa9d1..e30d1df3eeb5 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7180.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7180.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SC7180. - See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h + See also: include/dt-bindings/clock/qcom,gcc-sc7180.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7280.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7280.yaml index 4e4f68b9f6d2..5ddaf27bb1f4 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7280.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7280.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SC7280. - See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h + See also: include/dt-bindings/clock/qcom,gcc-sc7280.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8180x.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8180x.yaml index b4784ecaf58d..82c2ef39934d 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8180x.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8180x.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SC8180x. - See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h + See also: include/dt-bindings/clock/qcom,gcc-sc8180x.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8280xp.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8280xp.yaml index 5cfde8a4de4e..c1eeccef66b4 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8280xp.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc8280xp.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SC8280xp. - See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h + See also: include/dt-bindings/clock/qcom,gcc-sc8280xp.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdm845.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdm845.yaml index ef0a20456e8a..a7523a414341 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdm845.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdm845.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SDM670 and SDM845 - See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h + See also: include/dt-bindings/clock/qcom,gcc-sdm845.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx55.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx55.yaml index 30819f3d85c6..320e4f5b2b18 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx55.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx55.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SDX55 - See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h + See also: include/dt-bindings/clock/qcom,gcc-sdx55.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx65.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx65.yaml index 915449228668..9242e6e19139 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx65.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdx65.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SDX65 - See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h + See also: include/dt-bindings/clock/qcom,gcc-sdx65.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6115.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6115.yaml index ecb69c707f09..c926630907c5 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6115.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6115.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM4250/6115. - See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h + See also: include/dt-bindings/clock/qcom,gcc-sm6115.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6125.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6125.yaml index 1fe68e07a2b2..5bd422e94a38 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6125.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6125.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM6125. - See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h + See also: include/dt-bindings/clock/qcom,gcc-sm6125.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6350.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6350.yaml index 78e232fa95dc..819e855eaf9a 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6350.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm6350.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM6350. - See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h + See also: include/dt-bindings/clock/qcom,gcc-sm6350.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8150.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8150.yaml index 1dcf97c0c064..5f3f69fe9ddb 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8150.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8150.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8150. - See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h + See also: include/dt-bindings/clock/qcom,gcc-sm8150.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8250.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8250.yaml index 979ff0a8bf68..f4cd5a509c60 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8250.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8250.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8250. - See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h + See also: include/dt-bindings/clock/qcom,gcc-sm8250.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8350.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8350.yaml index 594e87f5ba09..97ffae3b5522 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8350.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8350.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8350. - See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h + See also: include/dt-bindings/clock/qcom,gcc-sm8350.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml index d848361beeb3..3169ac05e1d8 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml @@ -13,11 +13,13 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8450 - See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h + See also: include/dt-bindings/clock/qcom,gcc-sm8450.h properties: compatible: - const: qcom,gcc-sm8450 + enum: + - qcom,gcc-sm8450 + - qcom,sm8475-gcc clocks: items: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml index 0858fd635282..4cdff6161bf0 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml @@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller maintainers: - Taniya Das <quic_tdas@quicinc.com> + - Imran Shaik <quic_imrashai@quicinc.com> description: | Qualcomm graphics clock control module provides the clocks, resets and power @@ -23,10 +24,12 @@ description: | include/dt-bindings/clock/qcom,gpucc-sm8150.h include/dt-bindings/clock/qcom,gpucc-sm8250.h include/dt-bindings/clock/qcom,gpucc-sm8350.h + include/dt-bindings/clock/qcom,qcs8300-gpucc.h properties: compatible: enum: + - qcom,qcs8300-gpucc - qcom,sdm845-gpucc - qcom,sa8775p-gpucc - qcom,sc7180-gpucc diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,ipq5332-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,ipq5332-gcc.yaml index 9193de681de2..1230183fc0a9 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,ipq5332-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,ipq5332-gcc.yaml @@ -4,31 +4,35 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on IPQ5332 +title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424 maintainers: - Bjorn Andersson <andersson@kernel.org> description: | Qualcomm global clock control module provides the clocks, resets and power - domains on IPQ5332. + domains on IPQ5332 and IPQ5424. - See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h - -allOf: - - $ref: qcom,gcc.yaml# + See also: + include/dt-bindings/clock/qcom,gcc-ipq5332.h + include/dt-bindings/clock/qcom,gcc-ipq5424.h properties: compatible: - const: qcom,ipq5332-gcc + enum: + - qcom,ipq5332-gcc + - qcom,ipq5424-gcc clocks: + minItems: 5 items: - description: Board XO clock source - description: Sleep clock source - description: PCIE 2lane PHY pipe clock source - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - description: USB PCIE wrapper pipe clock source + - description: PCIE 2-lane PHY2 pipe clock source + - description: PCIE 2-lane PHY3 pipe clock source '#power-domain-cells': false '#interconnect-cells': @@ -38,6 +42,29 @@ required: - compatible - clocks +allOf: + - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,ipq5332-gcc + then: + properties: + clocks: + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: qcom,ipq5424-gcc + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + unevaluatedProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-cmn-pll.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-cmn-pll.yaml new file mode 100644 index 000000000000..817d51135fbf --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CMN PLL Clock Controller on IPQ SoC + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Luo Jie <quic_luoj@quicinc.com> + +description: + The CMN (or common) PLL clock controller expects a reference + input clock. This reference clock is from the on-board Wi-Fi. + The CMN PLL supplies a number of fixed rate output clocks to + the devices providing networking functions and to GCC. These + networking hardware include PPE (packet process engine), PCS + and the externally connected switch or PHY devices. The CMN + PLL block also outputs fixed rate clocks to GCC. The PLL's + primary function is to enable fixed rate output clocks for + networking hardware functions used with the IPQ SoC. + +properties: + compatible: + enum: + - qcom,ipq5018-cmn-pll + - qcom,ipq5424-cmn-pll + - qcom,ipq9574-cmn-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: The reference clock. The supported clock rates include + 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. + - description: The AHB clock + - description: The SYS clock + description: + The reference clock is the source clock of CMN PLL, which is from the + Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL + clock registers. + + clock-names: + items: + - const: ref + - const: ahb + - const: sys + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-nsscc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-nsscc.yaml new file mode 100644 index 000000000000..17252b6ea3be --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-nsscc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Anusha Rao <quic_anusha@quicinc.com> + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq9574-nsscc.h + +properties: + compatible: + const: qcom,ipq9574-nsscc + + clocks: + items: + - description: Board XO source + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: GCC GPLL0 OUT AUX clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Uniphy2 NSS Rx clock source + - description: Uniphy2 NSS Tx clock source + - description: GCC NSSCC clock source + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + #include <dt-bindings/clock/qcom,ipq-cmn-pll.h> + clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&uniphy 4>, + <&uniphy 5>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss_1200", + "ppe_353", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,krait-cc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..d6a019371fcf --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Clock Controller + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: Parent clock phandle for hfpll0 + - description: Parent clock phandle for hfpll1 + - description: Parent clock phandle for acpu0_aux + - description: Parent clock phandle for acpu1_aux + - description: Parent clock phandle for qsb + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + +required: + - compatible + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,milos-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,milos-camcc.yaml new file mode 100644 index 000000000000..f63149ecf3e1 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,milos-camcc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on Milos + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on Milos. + + See also: include/dt-bindings/clock/qcom,milos-camcc.h + +properties: + compatible: + const: qcom,milos-camcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Camera AHB clock from GCC + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,milos-gcc.h> + clock-controller@adb0000 { + compatible = "qcom,milos-camcc"; + reg = <0x0adb0000 0x40000>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,milos-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,milos-dispcc.yaml new file mode 100644 index 000000000000..94908804756b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,milos-dispcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on Milos + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on Milos. + + See also: include/dt-bindings/clock/qcom,milos-dispcc.h + +properties: + compatible: + const: qcom,milos-dispcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Display's AHB clock + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,milos-gcc.h> + #include <dt-bindings/phy/phy-qcom-qmp.h> + clock-controller@af00000 { + compatible = "qcom,milos-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,milos-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,milos-gcc.yaml new file mode 100644 index 000000000000..cf244c155f9a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,milos-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Milos + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on Milos. + + See also: include/dt-bindings/clock/qcom,milos-gcc.h + +properties: + compatible: + const: qcom,milos-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,milos-gcc"; + reg = <0x00100000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,milos-videocc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,milos-videocc.yaml new file mode 100644 index 000000000000..14c31efe1308 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,milos-videocc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on Milos + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Milos. + + See also: include/dt-bindings/clock/qcom,milos-videocc.h + +properties: + compatible: + const: qcom,milos-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: Video AHB clock from GCC + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,milos-gcc.h> + clock-controller@aaf0000 { + compatible = "qcom,milos-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,mmcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,mmcc.yaml index aa35a40648ba..53ceec9673a8 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,mmcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,mmcc.yaml @@ -38,36 +38,16 @@ properties: minItems: 7 maxItems: 13 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding - vdd-gfx-supply: description: Regulator supply for the GPU_GX GDSC required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false - allOf: + - $ref: qcom,gcc.yaml# - if: properties: compatible: @@ -78,6 +58,7 @@ allOf: then: properties: clocks: + minItems: 8 items: - description: Board PXO source - description: PLL 3 clock @@ -87,8 +68,10 @@ allOf: - description: DSI phy instance 2 dsi clock - description: DSI phy instance 2 byte clock - description: HDMI phy PLL clock + - description: LVDS PLL clock clock-names: + minItems: 8 items: - const: pxo - const: pll3 @@ -98,6 +81,7 @@ allOf: - const: dsi2pll - const: dsi2pllbyte - const: hdmipll + - const: lvdspll - if: properties: @@ -347,6 +331,8 @@ allOf: - const: dp_link_2x_clk_divsel_five - const: dp_vco_divided_clk_src_mux +unevaluatedProperties: false + examples: # Example for MMCC for MSM8960: - | diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,msm8998-gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,msm8998-gpucc.yaml index b9b218ef9b68..374de7a6f8d9 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,msm8998-gpucc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,msm8998-gpucc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm graphics clock control module provides the clocks, resets and power domains on MSM8998. - See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h + See also: include/dt-bindings/clock/qcom,gpucc-msm8998.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qcm2290-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qcm2290-dispcc.yaml index 243be4f76db3..4a533b45eec2 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,qcm2290-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qcm2290-dispcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on qcm2290. - See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h + See also: include/dt-bindings/clock/qcom,dispcc-qcm2290.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-dispcc.yaml new file mode 100644 index 000000000000..d566f19beb0d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-dispcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on QCS615. + + See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h + +properties: + compatible: + const: qcom,qcs615-dispcc + + clocks: + items: + - description: Board XO source + - description: GPLL0 clock source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Display port PLL link clock + - description: Display port PLL VCO DIV clock + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,qcs615-gcc.h> + clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dp_phy 0>, + <&mdss_dp_vco 0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-gcc.yaml new file mode 100644 index 000000000000..4a828e102d25 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-gcc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on QCS615. + + See also: include/dt-bindings/clock/qcom,qcs615-gcc.h + +properties: + compatible: + const: qcom,qcs615-gcc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,qcs615-gcc"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-gpucc.yaml new file mode 100644 index 000000000000..5f7d83d1a7be --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-gpucc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h + +properties: + compatible: + const: qcom,qcs615-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 GPUCC div branch source + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,qcs615-gcc.h> + + clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0x5090000 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-videocc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-videocc.yaml new file mode 100644 index 000000000000..f51b69de1047 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qcs615-videocc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm video clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-videocc.h + +properties: + compatible: + const: qcom,qcs615-videocc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,qcs615-gcc.h> + + clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0xab00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qcs8300-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qcs8300-gcc.yaml new file mode 100644 index 000000000000..081bc452081f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qcs8300-gcc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + - Imran Shaik <quic_imrashai@quicinc.com> + +description: | + Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and + power domains on QCS8300 + + See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h + +properties: + compatible: + const: qcom,qcs8300-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: PCIE Phy Auxiliary clock source + - description: First EMAC controller reference clock + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,qcs8300-gcc"; + reg = <0x00100000 0xc7018>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&pcie_phy_aux_clk>, + <&rxc0_ref_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-ecpricc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-ecpricc.yaml index fd21df0e7697..3038307ff2c5 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-ecpricc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-ecpricc.yaml @@ -14,7 +14,7 @@ description: | Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control module which supports the clocks, resets on QDU1000 and QRU1000 - See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h + See also: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml index 86befef02650..2c5a9ef4fe4d 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module which supports the clocks, resets and power domains on QDU1000 and QRU1000 - See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h + See also: include/dt-bindings/clock/qcom,qdu1000-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,rpmcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,rpmcc.yaml index 02fcffe93f1a..90cd3feab5fa 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,rpmcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,rpmcc.yaml @@ -33,6 +33,8 @@ properties: - qcom,rpmcc-msm8916 - qcom,rpmcc-msm8917 - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8937 + - qcom,rpmcc-msm8940 - qcom,rpmcc-msm8953 - qcom,rpmcc-msm8974 - qcom,rpmcc-msm8976 @@ -42,6 +44,7 @@ properties: - qcom,rpmcc-msm8998 - qcom,rpmcc-qcm2290 - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 @@ -110,6 +113,8 @@ allOf: - qcom,rpmcc-msm8916 - qcom,rpmcc-msm8917 - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8937 + - qcom,rpmcc-msm8940 - qcom,rpmcc-msm8953 - qcom,rpmcc-msm8974 - qcom,rpmcc-msm8976 @@ -119,6 +124,7 @@ allOf: - qcom,rpmcc-msm8998 - qcom,rpmcc-qcm2290 - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,rpmhcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,rpmhcc.yaml index ca857942ed6c..a4414ba0b287 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,rpmhcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,rpmhcc.yaml @@ -17,8 +17,11 @@ description: | properties: compatible: enum: + - qcom,milos-rpmh-clk + - qcom,qcs615-rpmh-clk - qcom,qdu1000-rpmh-clk - qcom,sa8775p-rpmh-clk + - qcom,sar2130p-rpmh-clk - qcom,sc7180-rpmh-clk - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk @@ -36,6 +39,7 @@ properties: - qcom,sm8450-rpmh-clk - qcom,sm8550-rpmh-clk - qcom,sm8650-rpmh-clk + - qcom,sm8750-rpmh-clk - qcom,x1e80100-rpmh-clk clocks: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-camcc.yaml new file mode 100644 index 000000000000..f42ccb6627a3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-camcc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + - Imran Shaik <quic_imrashai@quicinc.com> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SA8775p. + + See also: + include/dt-bindings/clock/qcom,qcs8300-camcc.h + include/dt-bindings/clock/qcom,sa8775p-camcc.h + include/dt-bindings/clock/qcom,sc8280xp-camcc.h + +properties: + compatible: + enum: + - qcom,qcs8300-camcc + - qcom,sa8775p-camcc + - qcom,sc8280xp-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: MMCX power domain + + required-opps: + description: + OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,sc8280xp-camcc + then: + required: + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + clock-controller@ade0000 { + compatible = "qcom,sa8775p-camcc"; + reg = <0x0ade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-dispcc.yaml new file mode 100644 index 000000000000..ce61755e62d4 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-dispcc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SA8775P. + + See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h + +properties: + compatible: + enum: + - qcom,sa8775p-dispcc0 + - qcom,sa8775p-dispcc1 + + clocks: + items: + - description: GCC AHB clock source + - description: Board XO source + - description: Board XO_AO source + - description: Sleep clock source + - description: Link clock from DP0 PHY + - description: VCO DIV clock from DP0 PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Byte clock from DSI0 PHY + - description: Pixel clock from DSI0 PHY + - description: Byte clock from DSI1 PHY + - description: Pixel clock from DSI1 PHY + + power-domains: + maxItems: 1 + description: MMCX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + clock-controller@af00000 { + compatible = "qcom,sa8775p-dispcc0"; + reg = <0x0af00000 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&dp_phy0 0>, + <&dp_phy0 1>, + <&dp_phy1 2>, + <&dp_phy1 3>, + <&dsi_phy0 0>, + <&dsi_phy0 1>, + <&dsi_phy1 2>, + <&dsi_phy1 3>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-gcc.yaml index addbd323fa6d..c641aac8c451 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-gcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on sa8775p. - See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h + See also: include/dt-bindings/clock/qcom,sa8775p-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-videocc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-videocc.yaml new file mode 100644 index 000000000000..07e5d811d816 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sa8775p-videocc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SA8775P. + + See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h + +properties: + compatible: + enum: + - qcom,qcs8300-videocc + - qcom,sa8775p-videocc + + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep Clock source + + power-domains: + maxItems: 1 + description: MMCX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + videocc: clock-controller@abf0000 { + compatible = "qcom,sa8775p-videocc"; + reg = <0x0abf0000 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SA8775P_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sar2130p-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sar2130p-gcc.yaml new file mode 100644 index 000000000000..9a430bbd872a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sar2130p-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on sar2130p + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on sar2130p. + + See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h + +properties: + compatible: + const: qcom,sar2130p-gcc + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: PCIe 0 pipe clock + - description: PCIe 1 pipe clock + - description: Primary USB3 PHY wrapper pipe clock + + protected-clocks: + maxItems: 240 + + power-domains: + maxItems: 1 + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + gcc: clock-controller@100000 { + compatible = "qcom,sar2130p-gcc"; + reg = <0x100000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&usb_0_ssphy>; + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-camcc.yaml index c7fe6400ea13..98ee9be84794 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-camcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SC7180. - See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h + See also: include/dt-bindings/clock/qcom,camcc-sc7180.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-dispcc.yaml index 0d8ea44d8141..f147d06ad2ef 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-dispcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SC7180. - See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h + See also: include/dt-bindings/clock/qcom,dispcc-sc7180.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-lpasscorecc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-lpasscorecc.yaml index fdfb389083c1..ad360debef7c 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-lpasscorecc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7180-lpasscorecc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm LPASS core clock control module provides the clocks and power domains on SC7180. - See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h + See also: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-camcc.yaml index dcef8de3a905..2f28be58e82e 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-camcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SC7280. - See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h + See also: include/dt-bindings/clock/qcom,camcc-sc7280.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml index 23177661be40..95b1e4f48c4f 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SC7280. - See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h + See also: include/dt-bindings/clock/qcom,dispcc-sc7280.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscc.yaml index f44c5c130d2d..a90961d8656c 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm LPASS core clock control module provides the clocks and power domains on SC7280. - See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h + See also: include/dt-bindings/clock/qcom,lpass-sc7280.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscorecc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscorecc.yaml index deee5423d66e..99ab9106009f 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -18,25 +18,32 @@ description: | include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h properties: - clocks: true - - clock-names: true - - reg: true - compatible: enum: + - qcom,qcm6490-lpassaudiocc - qcom,sc7280-lpassaoncc - qcom,sc7280-lpassaudiocc - qcom,sc7280-lpasscorecc - qcom,sc7280-lpasshm - power-domains: - maxItems: 1 + reg: + minItems: 1 + maxItems: 2 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 '#clock-cells': const: 1 + power-domains: + maxItems: 1 + '#power-domain-cells': const: 1 @@ -57,14 +64,14 @@ required: - '#clock-cells' - '#power-domain-cells' -additionalProperties: false - allOf: - if: properties: compatible: contains: - const: qcom,sc7280-lpassaudiocc + enum: + - qcom,qcm6490-lpassaudiocc + - qcom,sc7280-lpassaudiocc then: properties: @@ -125,6 +132,9 @@ allOf: reg: maxItems: 1 + +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmh.h> diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sc8180x-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sc8180x-camcc.yaml new file mode 100644 index 000000000000..477ee687520e --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sc8180x-camcc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8180x-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SC8180X + +maintainers: + - Satya Priya Kakitapalli <quic_skakitap@quicinc.com> + +description: | + Qualcomm camera clock control module provides the clocks, resets and + power domains on SC8180X. + + See also: include/dt-bindings/clock/qcom,sc8180x-camcc.h + +properties: + compatible: + const: qcom,sc8180x-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: + A phandle and PM domain specifier for the MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc8180x.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@ad00000 { + compatible = "qcom,sc8180x-camcc"; + reg = <0x0ad00000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + power-domains = <&rpmhpd SC8180X_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-camcc.yaml index 810b852ae371..6214e41eec1f 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-camcc.yaml @@ -13,14 +13,18 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SDM845. - See also:: include/dt-bindings/clock/qcom,camcc-sm845.h + See also: include/dt-bindings/clock/qcom,camcc-sm845.h allOf: - $ref: qcom,gcc.yaml# properties: compatible: - const: qcom,sdm845-camcc + oneOf: + - items: + - const: qcom,sdm670-camcc + - const: qcom,sdm845-camcc + - const: qcom,sdm845-camcc clocks: items: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml index 220f4004f7fd..854c391c8307 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SDM845. - See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h + See also: include/dt-bindings/clock/qcom,dispcc-sdm845.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-lpasscc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-lpasscc.yaml index a96fd837c70a..f9feb7049b21 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-lpasscc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-lpasscc.yaml @@ -12,7 +12,7 @@ maintainers: description: | Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller. - See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h + See also: include/dt-bindings/clock/qcom,lpass-sdm845.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sdx75-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sdx75-gcc.yaml index 567182aba300..29a0b29bcb81 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sdx75-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sdx75-gcc.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SDX75 - See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h + See also: include/dt-bindings/clock/qcom,sdx75-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-camcc.yaml index f54ce865880d..70f025b26736 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-camcc.yaml @@ -14,38 +14,26 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM4450 - See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h + See also: include/dt-bindings/clock/qcom,sm4450-camcc.h properties: compatible: const: qcom,sm4450-camcc - reg: - maxItems: 1 - clocks: items: - description: Board XO source - description: Camera AHB clock source from GCC - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-dispcc.yaml index 2aa05353eff1..d977788bdc8a 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-dispcc.yaml @@ -14,15 +14,12 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM4450 - See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h + See also: include/dt-bindings/clock/qcom,sm4450-dispcc.h properties: compatible: const: qcom,sm4450-dispcc - reg: - maxItems: 1 - clocks: items: - description: Board XO source @@ -32,24 +29,15 @@ properties: - description: Byte clock from DSI PHY0 - description: Pixel clock from DSI PHY0 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-gcc.yaml index 0ac92d7871e1..9cfe859bacc9 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm4450-gcc.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM4450 - See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h + See also: include/dt-bindings/clock/qcom,sm4450-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-dispcc.yaml index 00be36683eb5..b31424306f49 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-dispcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks and power domains on SM6115. - See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h + See also: include/dt-bindings/clock/qcom,sm6115-dispcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-gpucc.yaml index 4ff17a91344b..104ba10ca573 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-gpucc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-gpucc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm graphics clock control module provides clocks, resets and power domains on Qualcomm SoCs. - See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + See also: include/dt-bindings/clock/qcom,sm6115-gpucc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-lpasscc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-lpasscc.yaml new file mode 100644 index 000000000000..8cbab3fbb660 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-lpasscc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SM6115 + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm LPASS core and audio clock controllers provide audio-related resets + on SM6115 and its derivatives. + + See also:: + include/dt-bindings/clock/qcom,sm6115-lpasscc.h + +properties: + compatible: + enum: + - qcom,sm6115-lpassaudiocc + - qcom,sm6115-lpasscc + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + lpass_audiocc: clock-controller@a6a9000 { + compatible = "qcom,sm6115-lpassaudiocc"; + reg = <0x0a6a9000 0x1000>; + #reset-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6125-gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6125-gpucc.yaml index 10a9c96a97b6..12d6f0cdbcd8 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6125-gpucc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6125-gpucc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm graphics clock control module provides clocks and power domains on Qualcomm SoCs. - See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + See also: include/dt-bindings/clock/qcom,sm6125-gpucc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6350-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6350-camcc.yaml index c03b30f64f35..e31cd4300f7d 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6350-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6350-camcc.yaml @@ -8,16 +8,21 @@ title: Qualcomm Camera Clock & Reset Controller on SM6350 maintainers: - Konrad Dybcio <konradybcio@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> description: | Qualcomm camera clock control module provides the clocks, resets and power - domains on SM6350. + domains on SM6350 and QCS615 SoC. - See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h + See also: + include/dt-bindings/clock/qcom,qcs615-camcc.h + include/dt-bindings/clock/qcom,sm6350-camcc.h properties: compatible: - const: qcom,sm6350-camcc + enum: + - qcom,qcs615-camcc + - qcom,sm6350-camcc clocks: items: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-dispcc.yaml index 3cd422a645fd..519ea76cb052 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-dispcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM6375. - See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h + See also: include/dt-bindings/clock/qcom,dispcc-sm6375.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gcc.yaml index de4e9066eeb8..66dfa72fa975 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM6375 - See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h + See also: include/dt-bindings/clock/qcom,sm6375-gcc.h allOf: - $ref: qcom,gcc.yaml# diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gpucc.yaml index d9dd479c17bd..3aad6b5bb1c5 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gpucc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gpucc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm graphics clock control module provides clocks, resets and power domains on Qualcomm SoCs. - See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + See also: include/dt-bindings/clock/qcom,sm6375-gpucc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-camcc.yaml index 7be4b10c430c..b96091c28c5a 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-camcc.yaml @@ -15,7 +15,7 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM7150. - See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h + See also: include/dt-bindings/clock/qcom,sm7150-camcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-dispcc.yaml index b8d6e1d05ce2..13ab3359b592 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-dispcc.yaml @@ -15,7 +15,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM7150. - See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h + See also: include/dt-bindings/clock/qcom,sm7150-dispcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-gcc.yaml index 4d7bbbf4ce8a..3878808f811e 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-gcc.yaml @@ -15,7 +15,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM7150 - See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h + See also: include/dt-bindings/clock/qcom,sm7150-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-videocc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-videocc.yaml index 037ffc71e70e..9f7928730386 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-videocc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm7150-videocc.yaml @@ -15,7 +15,7 @@ description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM7150. - See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h + See also: include/dt-bindings/clock/qcom,videocc-sm7150.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8150-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8150-camcc.yaml index 5e9f62d7866c..a55e30a4975e 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8150-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8150-camcc.yaml @@ -13,15 +13,12 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8150. - See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h + See also: include/dt-bindings/clock/qcom,sm8150-camcc.h properties: compatible: const: qcom,sm8150-camcc - reg: - maxItems: 1 - clocks: items: - description: Board XO source @@ -37,26 +34,17 @@ properties: description: A phandle to an OPP node describing required MMCX performance point. - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - required: - compatible - - reg - clocks - power-domains - required-opps - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml index 26afbbe65511..c1e06f39431e 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml @@ -15,20 +15,17 @@ description: | domains on SM8450. See also: - include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h - include/dt-bindings/clock/qcom,x1e80100-camcc.h properties: compatible: enum: - - qcom,sc8280xp-camcc - qcom,sm8450-camcc + - qcom,sm8475-camcc - qcom,sm8550-camcc - qcom,sm8650-camcc - - qcom,x1e80100-camcc clocks: items: @@ -38,14 +35,18 @@ properties: - description: Sleep clock source power-domains: - maxItems: 1 description: - A phandle and PM domain specifier for the MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + OPP nodes that describe required performance points on power domains + items: + - description: MMCX performance point + - description: MXC performance point reg: maxItems: 1 @@ -65,7 +66,6 @@ allOf: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc - - qcom,x1e80100-camcc then: required: - required-opps @@ -84,8 +84,10 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-dispcc.yaml index 4794c53793a8..bd131a1ff165 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-dispcc.yaml @@ -13,12 +13,13 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h + See also: include/dt-bindings/clock/qcom,sm8450-dispcc.h properties: compatible: enum: - qcom,sm8450-dispcc + - qcom,sm8475-dispcc clocks: minItems: 3 diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml index 2d2c59aa8c6b..44380f6f8136 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml @@ -14,6 +14,8 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,milos-gpucc.h + include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -24,11 +26,15 @@ description: | properties: compatible: enum: + - qcom,milos-gpucc + - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc + - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc - qcom,x1e80100-gpucc + - qcom,x1p42100-gpucc clocks: items: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml index 9829ba28fe0e..fcd2727dae46 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml @@ -22,8 +22,10 @@ properties: compatible: enum: - qcom,sm8450-videocc + - qcom,sm8475-videocc - qcom,sm8550-videocc - qcom,sm8650-videocc + - qcom,x1e80100-videocc clocks: items: @@ -31,14 +33,18 @@ properties: - description: Video AHB clock from GCC power-domains: - maxItems: 1 description: - MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + OPP nodes that describe required performance points on power domains + items: + - description: MMCX performance point + - description: MXC performance point required: - compatible @@ -71,8 +77,10 @@ examples: reg = <0x0aaf0000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml index c17035a180db..30e4b4631575 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml @@ -12,18 +12,21 @@ maintainers: description: | Qualcomm display clock control module provides the clocks, resets and power - domains on SM8550. + domains on SM8550, SM8650, SM8750 and few other platforms. See also: - include/dt-bindings/clock/qcom,sm8550-dispcc.h - include/dt-bindings/clock/qcom,sm8650-dispcc.h + - include/dt-bindings/clock/qcom,sm8750-dispcc.h - include/dt-bindings/clock/qcom,x1e80100-dispcc.h properties: compatible: enum: + - qcom,sar2130p-dispcc - qcom,sm8550-dispcc - qcom,sm8650-dispcc + - qcom,sm8750-dispcc - qcom,x1e80100-dispcc clocks: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-gcc.yaml index d83b64dcce4f..c4e9b9bb63f5 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-gcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8550 - See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h + See also: include/dt-bindings/clock/qcom,sm8550-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-tcsr.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-tcsr.yaml index 48fdd562d743..2ed7d59722fc 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-tcsr.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8550-tcsr.yaml @@ -16,13 +16,17 @@ description: | See also: - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h + - include/dt-bindings/clock/qcom,sm8750-tcsr.h properties: compatible: items: - enum: + - qcom,milos-tcsr + - qcom,sar2130p-tcsr - qcom,sm8550-tcsr - qcom,sm8650-tcsr + - qcom,sm8750-tcsr - qcom,x1e80100-tcsr - const: syscon diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8650-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8650-gcc.yaml index 976f29cce809..c7143e2abc80 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,sm8650-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8650-gcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8650 - See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h + See also: include/dt-bindings/clock/qcom,sm8650-gcc.h properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,sm8750-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,sm8750-gcc.yaml new file mode 100644 index 000000000000..aab7039fd28d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,sm8750-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM8750 + +maintainers: + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM8750 + + See also: include/dt-bindings/clock/qcom,sm8750-gcc.h + +properties: + compatible: + const: qcom,sm8750-gcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,sm8750-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml index 340c7e5cf980..5f7738d6835c 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sm6350-videocc.h include/dt-bindings/clock/qcom,videocc-sc7180.h include/dt-bindings/clock/qcom,videocc-sc7280.h include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -26,6 +27,7 @@ properties: - qcom,sc7180-videocc - qcom,sc7280-videocc - qcom,sdm845-videocc + - qcom,sm6350-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc @@ -91,6 +93,24 @@ allOf: properties: compatible: enum: + - qcom,sm6350-videocc + then: + properties: + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Sleep Clock source + clock-names: + items: + - const: iface + - const: bi_tcxo + - const: sleep_clk + + - if: + properties: + compatible: + enum: - qcom,sm8150-videocc then: properties: diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-camcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-camcc.yaml new file mode 100644 index 000000000000..938a2f1ff3fc --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-camcc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on x1e80100 + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on x1e80100. + + See also: + include/dt-bindings/clock/qcom,x1e80100-camcc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,x1e80100-camcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + items: + - description: A phandle to the MXC power-domain + - description: A phandle to the MMCX power-domain + + required-opps: + items: + - description: A phandle to an OPP node describing MXC performance points + - description: A phandle to an OPP node describing MMCX performance points + +required: + - compatible + - clocks + - power-domains + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,x1e80100-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-gcc.yaml b/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-gcc.yaml index 5951a60ab081..68dde0720c71 100644 --- a/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-gcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/qcom,x1e80100-gcc.yaml @@ -13,11 +13,15 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on X1E80100 - See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h + See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h properties: compatible: - const: qcom,x1e80100-gcc + oneOf: + - items: + - const: qcom,x1p42100-gcc + - const: qcom,x1e80100-gcc + - const: qcom,x1e80100-gcc clocks: items: diff --git a/sys/contrib/device-tree/Bindings/clock/raspberrypi,rp1-clocks.yaml b/sys/contrib/device-tree/Bindings/clock/raspberrypi,rp1-clocks.yaml new file mode 100644 index 000000000000..cc4491f7ee5f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/raspberrypi,rp1-clocks.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi RP1 clock generator + +maintainers: + - A. della Porta <andrea.porta@suse.com> + +description: | + The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO, + VIDEO), and each PLL output can be programmed through dividers to generate + the clocks to drive the sub-peripherals embedded inside the chipset. + + Link to datasheet: + https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf + +properties: + compatible: + const: raspberrypi,rp1-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The available clocks are defined in + include/dt-bindings/clock/raspberrypi,rp1-clocks.h. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/raspberrypi,rp1-clocks.h> + + rp1 { + #address-cells = <2>; + #size-cells = <2>; + + clocks@c040018000 { + compatible = "raspberrypi,rp1-clocks"; + reg = <0xc0 0x40018000 0x0 0x10038>; + #clock-cells = <1>; + clocks = <&clk_rp1_xosc>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/renesas,5p35023.yaml b/sys/contrib/device-tree/Bindings/clock/renesas,5p35023.yaml index 42b6f80613f3..162d38035188 100644 --- a/sys/contrib/device-tree/Bindings/clock/renesas,5p35023.yaml +++ b/sys/contrib/device-tree/Bindings/clock/renesas,5p35023.yaml @@ -31,6 +31,7 @@ description: | properties: compatible: enum: + - renesas,5l35023 - renesas,5p35023 reg: diff --git a/sys/contrib/device-tree/Bindings/clock/renesas,cpg-mssr.yaml b/sys/contrib/device-tree/Bindings/clock/renesas,cpg-mssr.yaml index 77ce3615c65a..bc2fd3761328 100644 --- a/sys/contrib/device-tree/Bindings/clock/renesas,cpg-mssr.yaml +++ b/sys/contrib/device-tree/Bindings/clock/renesas,cpg-mssr.yaml @@ -52,9 +52,16 @@ properties: - renesas,r8a779f0-cpg-mssr # R-Car S4-8 - renesas,r8a779g0-cpg-mssr # R-Car V4H - renesas,r8a779h0-cpg-mssr # R-Car V4M + - renesas,r9a09g077-cpg-mssr # RZ/T2H + - renesas,r9a09g087-cpg-mssr # RZ/N2H reg: - maxItems: 1 + minItems: 1 + items: + - description: base address of register block 0 + - description: base address of register block 1 + description: base addresses of clock controller. Some controllers + (like r9a09g077) use two blocks instead of a single one. clocks: minItems: 1 @@ -92,16 +99,6 @@ properties: the datasheet. const: 1 -if: - not: - properties: - compatible: - items: - enum: - - renesas,r7s9210-cpg-mssr -then: - required: - - '#reset-cells' required: - compatible @@ -111,6 +108,36 @@ required: - '#clock-cells' - '#power-domain-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-cpg-mssr + - renesas,r9a09g087-cpg-mssr + then: + properties: + reg: + minItems: 2 + clock-names: + items: + - const: extal + else: + properties: + reg: + maxItems: 1 + - if: + not: + properties: + compatible: + items: + enum: + - renesas,r7s9210-cpg-mssr + then: + required: + - '#reset-cells' + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/clock/renesas,r9a08g045-vbattb.yaml b/sys/contrib/device-tree/Bindings/clock/renesas,r9a08g045-vbattb.yaml new file mode 100644 index 000000000000..3707e4118949 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/renesas,r9a08g045-vbattb.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Battery Backup Function (VBATTB) + +description: + Renesas VBATTB is an always on powered module (backed by battery) which + controls the RTC clock (VBATTCLK), tamper detection logic and a small + general usage memory (128B). + +maintainers: + - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> + +properties: + compatible: + const: renesas,r9a08g045-vbattb + + reg: + maxItems: 1 + + interrupts: + items: + - description: tamper detector interrupt + + clocks: + items: + - description: VBATTB module clock + - description: RTC input clock (crystal or external clock device) + + clock-names: + items: + - const: bclk + - const: rtx + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + + quartz-load-femtofarads: + description: load capacitance of the on board crystal + enum: [ 4000, 7000, 9000, 12500 ] + default: 4000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a08g045-cpg.h> + #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + clock-controller@1005c000 { + compatible = "renesas,r9a08g045-vbattb"; + reg = <0x1005c000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; + clock-names = "bclk", "rtx"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + #clock-cells = <1>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + quartz-load-femtofarads = <12500>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/renesas,rzg2l-cpg.yaml b/sys/contrib/device-tree/Bindings/clock/renesas,rzg2l-cpg.yaml index 0440f23da059..8c18616e5c4d 100644 --- a/sys/contrib/device-tree/Bindings/clock/renesas,rzg2l-cpg.yaml +++ b/sys/contrib/device-tree/Bindings/clock/renesas,rzg2l-cpg.yaml @@ -57,8 +57,7 @@ properties: can be power-managed through Module Standby should refer to the CPG device node in their "power-domains" property, as documented by the generic PM Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml. - The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could - be used to reference individual CPG power domains. + const: 0 '#reset-cells': description: @@ -77,21 +76,6 @@ required: additionalProperties: false -allOf: - - if: - properties: - compatible: - contains: - const: renesas,r9a08g045-cpg - then: - properties: - '#power-domain-cells': - const: 1 - else: - properties: - '#power-domain-cells': - const: 0 - examples: - | cpg: clock-controller@11010000 { diff --git a/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml b/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml index 926c503bed1f..f261445bf341 100644 --- a/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml +++ b/sys/contrib/device-tree/Bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,19 +4,23 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation - and control of clock signals for the IP modules, generation and control of resets, - and control over booting, low power consumption and power supply domains. + On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles + generation and control of clock signals for the IP modules, generation and + control of resets, and control over booting, low power consumption and power + supply domains. properties: compatible: - const: renesas,r9a09g057-cpg + enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g056-cpg # RZ/V2N + - renesas,r9a09g057-cpg # RZ/V2H reg: maxItems: 1 @@ -37,7 +41,7 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/renesas,r9a09g057-cpg.h>, + <dt-bindings/clock/renesas,r9a09g0*-cpg.h>, - For module clocks, the two clock specifier cells must be "CPG_MOD" and a module number. The module number is calculated as the CLKON register offset index multiplied by 16, plus the actual bit in the register diff --git a/sys/contrib/device-tree/Bindings/clock/rockchip,rk3328-cru.yaml b/sys/contrib/device-tree/Bindings/clock/rockchip,rk3328-cru.yaml new file mode 100644 index 000000000000..f079c7a2559b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/rockchip,rk3328-cru.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3328 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3328 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required, + - "clkin_i2s" - external I2S clock - optional, + - "gmac_clkin" - external GMAC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + - "hdmi_phy" - output clock of the hdmi phy pll - optional + +properties: + compatible: + enum: + - rockchip,rk3328-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru"; + reg = <0xff440000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/rockchip,rk3528-cru.yaml b/sys/contrib/device-tree/Bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 000000000000..5a3ec902351c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi <ziyao@disroot.org> + +description: | + The RK3528 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to specify + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + const: rockchip,rk3528-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + - description: > + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. + + clock-names: + items: + - const: xin24m + - const: gmac0 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0xff4a0000 0x30000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/rockchip,rk3562-cru.yaml b/sys/contrib/device-tree/Bindings/clock/rockchip,rk3562-cru.yaml new file mode 100644 index 000000000000..36a353f5c42a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/rockchip,rk3562-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3562 Clock and Reset Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RK3562 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + +properties: + compatible: + const: rockchip,rk3562-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0xff100000 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/samsung,exynos2200-cmu.yaml b/sys/contrib/device-tree/Bindings/clock/samsung,exynos2200-cmu.yaml new file mode 100644 index 000000000000..89433e6d3518 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/samsung,exynos2200-cmu.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos2200 SoC clock controller + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Exynos2200 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clocks in that root tree + are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be + defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header. + +properties: + compatible: + enum: + - samsung,exynos2200-cmu-alive + - samsung,exynos2200-cmu-cmgp + - samsung,exynos2200-cmu-hsi0 + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + - samsung,exynos2200-cmu-peris + - samsung,exynos2200-cmu-top + - samsung,exynos2200-cmu-ufs + - samsung,exynos2200-cmu-vts + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-alive + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_ALIVE NOC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_CMGP NOC clock (from CMU_TOP) + - description: CMU_CMGP PERI clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: peri + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI0 NOC clock (from CMU_TOP) + - description: CMU_HSI0 DPGTC clock (from CMU_TOP) + - description: CMU_HSI0 DPOSC clock (from CMU_TOP) + - description: CMU_HSI0 USB32DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: noc + - const: dpgtc + - const: dposc + - const: usb + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_PERICn NOC clock (from CMU_TOP) + - description: CMU_PERICn IP0 clock (from CMU_TOP) + - description: CMU_PERICn IP1 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ip0 + - const: ip1 + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (25.6 MHz) + - description: CMU_PERIS NOC clock (from CMU_TOP) + - description: CMU_PERIS GIC clock (from CMU_TOP) + + clock-names: + items: + - const: tcxo_div3 + - const: noc + - const: gic + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-ufs + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_UFS NOC clock (from CMU_TOP) + - description: CMU_UFS MMC clock (from CMU_TOP) + - description: CMU_UFS UFS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: mmc + - const: ufs + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-vts + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_VTS DMIC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dmic + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos2200-cmu.h> + + cmu_vts: clock-controller@15300000 { + compatible = "samsung,exynos2200-cmu-vts"; + reg = <0x15300000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_VTS_DMIC>; + clock-names = "oscclk", "dmic"; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/samsung,exynos7870-cmu.yaml b/sys/contrib/device-tree/Bindings/clock/samsung,exynos7870-cmu.yaml new file mode 100644 index 000000000000..3c58712f12b9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/samsung,exynos7870-cmu.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7870 SoC clock controller + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + Exynos7870 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + include/dt-bindings/clock/samsung,exynos7870-cmu.h header. + +properties: + compatible: + enum: + - samsung,exynos7870-cmu-mif + - samsung,exynos7870-cmu-dispaud + - samsung,exynos7870-cmu-fsys + - samsung,exynos7870-cmu-g3d + - samsung,exynos7870-cmu-isp + - samsung,exynos7870-cmu-mfcmscl + - samsung,exynos7870-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mif + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-dispaud + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_DISPAUD bus clock (from CMU_MIF) + - description: DECON external clock (from CMU_MIF) + - description: DECON vertical clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: decon_eclk + - const: decon_vclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-fsys + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_MIF) + - description: USB20DRD clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-g3d + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D switch clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-isp + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: ISP camera clock (from CMU_MIF) + - description: ISP clock (from CMU_MIF) + - description: ISP VRA clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: cam + - const: isp + - const: vra + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mfcmscl + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: MSCL clock (from CMU_MIF) + - description: MFC clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: mfc + - const: mscl + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-peri + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_MIF) + - description: SPI0 clock (from CMU_MIF) + - description: SPI1 clock (from CMU_MIF) + - description: SPI2 clock (from CMU_MIF) + - description: SPI3 clock (from CMU_MIF) + - description: SPI4 clock (from CMU_MIF) + - description: UART0 clock (from CMU_MIF) + - description: UART1 clock (from CMU_MIF) + - description: UART2 clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: spi0 + - const: spi1 + - const: spi2 + - const: spi3 + - const: spi4 + - const: uart0 + - const: uart1 + - const: uart2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos7870-cmu.h> + + cmu_peri: clock-controller@101f0000 { + compatible = "samsung,exynos7870-cmu-peri"; + reg = <0x101f0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", + "spi3", "spi4", "uart0", "uart1", "uart2"; + clocks = <&oscclk>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/samsung,exynos8895-clock.yaml b/sys/contrib/device-tree/Bindings/clock/samsung,exynos8895-clock.yaml new file mode 100644 index 000000000000..111de33ce00b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/samsung,exynos8895-clock.yaml @@ -0,0 +1,239 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos8895 SoC clock controller + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Exynos8895 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos8895.h' header. + +properties: + compatible: + enum: + - samsung,exynos8895-cmu-fsys0 + - samsung,exynos8895-cmu-fsys1 + - samsung,exynos8895-cmu-peric0 + - samsung,exynos8895-cmu-peric1 + - samsung,exynos8895-cmu-peris + - samsung,exynos8895-cmu-top + + clocks: + minItems: 1 + maxItems: 16 + + clock-names: + minItems: 1 + maxItems: 16 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos8895-cmu-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS0 BUS clock (from CMU_TOP) + - description: CMU_FSYS0 DPGTC clock (from CMU_TOP) + - description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP) + - description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP) + - description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: dpgtc + - const: mmc + - const: ufs + - const: usbdrd30 + + - if: + properties: + compatible: + contains: + const: samsung,exynos8895-cmu-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS1 BUS clock (from CMU_TOP) + - description: CMU_FSYS1 PCIE clock (from CMU_TOP) + - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP) + - description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: pcie + - const: ufs + - const: mmc + + - if: + properties: + compatible: + contains: + const: samsung,exynos8895-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC0 BUS clock (from CMU_TOP) + - description: CMU_PERIC0 UART_DBG clock (from CMU_TOP) + - description: CMU_PERIC0 USI00 clock (from CMU_TOP) + - description: CMU_PERIC0 USI01 clock (from CMU_TOP) + - description: CMU_PERIC0 USI02 clock (from CMU_TOP) + - description: CMU_PERIC0 USI03 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: uart + - const: usi0 + - const: usi1 + - const: usi2 + - const: usi3 + + - if: + properties: + compatible: + contains: + const: samsung,exynos8895-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC1 BUS clock (from CMU_TOP) + - description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP) + - description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP) + - description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP) + - description: CMU_PERIC1 UART_BT clock (from CMU_TOP) + - description: CMU_PERIC1 USI04 clock (from CMU_TOP) + - description: CMU_PERIC1 USI05 clock (from CMU_TOP) + - description: CMU_PERIC1 USI06 clock (from CMU_TOP) + - description: CMU_PERIC1 USI07 clock (from CMU_TOP) + - description: CMU_PERIC1 USI08 clock (from CMU_TOP) + - description: CMU_PERIC1 USI09 clock (from CMU_TOP) + - description: CMU_PERIC1 USI10 clock (from CMU_TOP) + - description: CMU_PERIC1 USI11 clock (from CMU_TOP) + - description: CMU_PERIC1 USI12 clock (from CMU_TOP) + - description: CMU_PERIC1 USI13 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: speedy + - const: cam0 + - const: cam1 + - const: uart + - const: usi4 + - const: usi5 + - const: usi6 + - const: usi7 + - const: usi8 + - const: usi9 + - const: usi10 + - const: usi11 + - const: usi12 + - const: usi13 + + - if: + properties: + compatible: + contains: + const: samsung,exynos8895-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS BUS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos8895-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos8895.h> + + cmu_fsys1: clock-controller@11400000 { + compatible = "samsung,exynos8895-cmu-fsys1"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>, + <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/samsung,exynos990-clock.yaml b/sys/contrib/device-tree/Bindings/clock/samsung,exynos990-clock.yaml new file mode 100644 index 000000000000..c15cc1752b02 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/samsung,exynos990-clock.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos990 SoC clock controller + +maintainers: + - Igor Belwon <igor.belwon@mentallysanemainliners.org> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Exynos990 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos990.h' header. + +properties: + compatible: + enum: + - samsung,exynos990-cmu-hsi0 + - samsung,exynos990-cmu-peris + - samsung,exynos990-cmu-top + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos990-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_HSI0 BUS clock (from CMU_TOP) + - description: CMU_HSI0 USB31DRD clock (from CMU_TOP) + - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP) + - description: CMU_HSI0 DPGTC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: usb31drd + - const: usbdp_debug + - const: dpgtc + + - if: + properties: + compatible: + contains: + const: samsung,exynos990-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS BUS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos990-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos990.h> + + cmu_hsi0: clock-controller@10a00000 { + compatible = "samsung,exynos990-cmu-hsi0"; + reg = <0x10a00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, + <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>, + <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>; + clock-names = "oscclk", + "bus", + "usb31drd", + "usbdp_debug", + "dpgtc"; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/samsung,exynosautov920-clock.yaml b/sys/contrib/device-tree/Bindings/clock/samsung,exynosautov920-clock.yaml index 3330b2727474..72f59db73f76 100644 --- a/sys/contrib/device-tree/Bindings/clock/samsung,exynosautov920-clock.yaml +++ b/sys/contrib/device-tree/Bindings/clock/samsung,exynosautov920-clock.yaml @@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller maintainers: - Sunyeal Hong <sunyeal.hong@samsung.com> + - Shin Son <shin.son@samsung.com> - Chanwoo Choi <cw00.choi@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> - Sylwester Nawrocki <s.nawrocki@samsung.com> @@ -31,20 +32,24 @@ description: | properties: compatible: enum: - - samsung,exynosautov920-cmu-top - - samsung,exynosautov920-cmu-peric0 - - samsung,exynosautov920-cmu-peric1 - - samsung,exynosautov920-cmu-misc + - samsung,exynosautov920-cmu-cpucl0 + - samsung,exynosautov920-cmu-cpucl1 + - samsung,exynosautov920-cmu-cpucl2 - samsung,exynosautov920-cmu-hsi0 - samsung,exynosautov920-cmu-hsi1 + - samsung,exynosautov920-cmu-hsi2 + - samsung,exynosautov920-cmu-misc + - samsung,exynosautov920-cmu-peric0 + - samsung,exynosautov920-cmu-peric1 + - samsung,exynosautov920-cmu-top clocks: minItems: 1 - maxItems: 4 + maxItems: 5 clock-names: minItems: 1 - maxItems: 4 + maxItems: 5 "#clock-cells": const: 1 @@ -74,6 +79,71 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP) + - description: CMU_CPUCL0 DBG clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + - const: dbg + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 @@ -132,6 +202,30 @@ allOf: - const: usbdrd - const: mmc_card + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-hsi2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_HSI2 NOC clock (from CMU_TOP) + - description: CMU_HSI2 NOC UFS clock (from CMU_TOP) + - description: CMU_HSI2 UFS EMBD clock (from CMU_TOP) + - description: CMU_HSI2 ETHERNET clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ufs + - const: embd + - const: ethernet + required: - compatible - "#clock-cells" diff --git a/sys/contrib/device-tree/Bindings/clock/sophgo,cv1800-clk.yaml b/sys/contrib/device-tree/Bindings/clock/sophgo,cv1800-clk.yaml index 59ef41adb539..379ce3e9e391 100644 --- a/sys/contrib/device-tree/Bindings/clock/sophgo,cv1800-clk.yaml +++ b/sys/contrib/device-tree/Bindings/clock/sophgo,cv1800-clk.yaml @@ -11,10 +11,18 @@ maintainers: properties: compatible: - enum: - - sophgo,cv1800-clk - - sophgo,cv1810-clk - - sophgo,sg2000-clk + oneOf: + - enum: + - sophgo,cv1800b-clk + - sophgo,cv1812h-clk + - sophgo,sg2000-clk + - items: + - const: sophgo,sg2002-clk + - const: sophgo,sg2000-clk + - const: sophgo,cv1800-clk + deprecated: true + - const: sophgo,cv1810-clk + deprecated: true reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/clock/sophgo,sg2044-clk.yaml b/sys/contrib/device-tree/Bindings/clock/sophgo,sg2044-clk.yaml new file mode 100644 index 000000000000..272e58bdb62c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/sophgo,sg2044-clk.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 Clock Controller + +maintainers: + - Inochi Amaoto <inochiama@gmail.com> + +description: | + The Sophgo SG2044 clock controller requires an external oscillator + as input clock. + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/sophgo,sg2044-clk.h + +properties: + compatible: + const: sophgo,sg2044-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: fpll0 + - description: fpll1 + - description: fpll2 + - description: dpll0 + - description: dpll1 + - description: dpll2 + - description: dpll3 + - description: dpll4 + - description: dpll5 + - description: dpll6 + - description: dpll7 + - description: mpll0 + - description: mpll1 + - description: mpll2 + - description: mpll3 + - description: mpll4 + - description: mpll5 + + clock-names: + items: + - const: fpll0 + - const: fpll1 + - const: fpll2 + - const: dpll0 + - const: dpll1 + - const: dpll2 + - const: dpll3 + - const: dpll4 + - const: dpll5 + - const: dpll6 + - const: dpll7 + - const: mpll0 + - const: mpll1 + - const: mpll2 + - const: mpll3 + - const: mpll4 + - const: mpll5 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sophgo,sg2044-pll.h> + + clock-controller@50002000 { + compatible = "sophgo,sg2044-clk"; + reg = <0x50002000 0x1000>; + #clock-cells = <1>; + clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>, + <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>, + <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>, + <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>, + <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>, + <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>, + <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>, + <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>, + <&syscon CLK_MPLL5>; + clock-names = "fpll0", "fpll1", "fpll2", "dpll0", + "dpll1", "dpll2", "dpll3", "dpll4", + "dpll5", "dpll6", "dpll7", "mpll0", + "mpll1", "mpll2", "mpll3", "mpll4", + "mpll5"; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/spacemit,k1-pll.yaml b/sys/contrib/device-tree/Bindings/clock/spacemit,k1-pll.yaml new file mode 100644 index 000000000000..06bafd68c00a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/spacemit,k1-pll.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PLL + +maintainers: + - Haylen Chu <heylenay@4d2.org> + +properties: + compatible: + const: spacemit,k1-pll + + reg: + maxItems: 1 + + clocks: + description: External 24MHz oscillator + + spacemit,mpmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL + lock status. + + "#clock-cells": + const: 1 + description: + See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices. + +required: + - compatible + - reg + - clocks + - spacemit,mpmu + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@d4090000 { + compatible = "spacemit,k1-pll"; + reg = <0xd4090000 0x1000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&sysctl_mpmu>; + #clock-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/st,stm32-rcc.yaml b/sys/contrib/device-tree/Bindings/clock/st,stm32-rcc.yaml new file mode 100644 index 000000000000..f83a6120d65a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/st,stm32-rcc.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Reset Clock Controller + +maintainers: + - Dario Binacchi <dario.binacchi@amarulasolutions.com> + +description: | + The RCC IP is both a reset and a clock controller. + The reset phandle argument is the bit number within the RCC registers bank, + starting from RCC base address. + +properties: + compatible: + oneOf: + - items: + - enum: + - st,stm32f42xx-rcc + - st,stm32f746-rcc + - st,stm32h743-rcc + - const: st,stm32-rcc + - items: + - enum: + - st,stm32f469-rcc + - const: st,stm32f42xx-rcc + - const: st,stm32-rcc + - items: + - enum: + - st,stm32f769-rcc + - const: st,stm32f746-rcc + - const: st,stm32-rcc + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + '#clock-cells': + enum: [1, 2] + + clocks: + minItems: 2 + maxItems: 3 + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system configuration controller. It can be used to control the + power domain circuitry. + + st,ssc-modfreq-hz: + description: + The modulation frequency for main PLL (in Hz) + + st,ssc-moddepth-permyriad: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The modulation rate for main PLL (in permyriad, i.e. 0.01%) + minimum: 25 + maximum: 200 + + st,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/string + description: + The modulation techniques for main PLL. + items: + enum: + - center-spread + - down-spread + +required: + - compatible + - reg + - '#reset-cells' + - '#clock-cells' + - clocks + - st,syscfg + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32h743-rcc + then: + properties: + '#clock-cells': + const: 1 + description: | + The clock index for the specified type. + clocks: + items: + - description: high speed external (HSE) clock input + - description: low speed external (LSE) clock input + - description: Inter-IC sound (I2S) clock input + st,ssc-modfreq-hz: false + st,ssc-moddepth-permyriad: false + st,ssc-modmethod: false + + else: + properties: + '#clock-cells': + const: 2 + description: | + - The first cell is the clock type, possible values are 0 for + gated clocks and 1 otherwise. + - The second cell is the clock index for the specified type. + clocks: + items: + - description: high speed external (HSE) clock input + - description: Inter-IC sound (I2S) clock input + +additionalProperties: false + +examples: + # Reset and Clock Control Module node: + - | + clock-controller@40023800 { + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + #clock-cells = <2>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; + st,ssc-modfreq-hz = <10000>; + st,ssc-moddepth-permyriad = <200>; + st,ssc-modmethod = "center-spread"; + }; + - | + clock-controller@58024400 { + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/clock/st,stm32mp1-rcc.yaml b/sys/contrib/device-tree/Bindings/clock/st,stm32mp1-rcc.yaml index 9b3aaae546cb..e72f46e79b90 100644 --- a/sys/contrib/device-tree/Bindings/clock/st,stm32mp1-rcc.yaml +++ b/sys/contrib/device-tree/Bindings/clock/st,stm32mp1-rcc.yaml @@ -21,7 +21,7 @@ description: | ================= All available clocks are defined as preprocessor macros in - dt-bindings/clock/stm32mp1-clks.h header and can be used in device + include/dt-bindings/clock/stm32mp1-clks.h header and can be used in device tree sources. Specifying softreset control of devices @@ -40,8 +40,8 @@ description: | = 0x180 / 4 * 32 + 0 = 3072 The list of valid indices for STM32MP1 is available in: - include/dt-bindings/reset-controller/stm32mp1-resets.h - include/dt-bindings/reset-controller/stm32mp13-resets.h + include/dt-bindings/reset/stm32mp1-resets.h + include/dt-bindings/reset/stm32mp13-resets.h This file implements defines like: #define LTDC_R 3072 diff --git a/sys/contrib/device-tree/Bindings/clock/thead,th1520-clk-ap.yaml b/sys/contrib/device-tree/Bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3..9d058c00ab3d 100644 --- a/sys/contrib/device-tree/Bindings/clock/thead,th1520-clk-ap.yaml +++ b/sys/contrib/device-tree/Bindings/clock/thead,th1520-clk-ap.yaml @@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller description: | The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures + the clock gates for the HDMI, MIPI and the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -20,14 +21,24 @@ maintainers: properties: compatible: - const: thead,th1520-clk-ap + enum: + - thead,th1520-clk-ap + - thead,th1520-clk-vo reg: maxItems: 1 clocks: items: - - description: main oscillator (24MHz) + - description: | + One input clock: + - For "thead,th1520-clk-ap": the clock input must be the 24 MHz + main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL + (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with + a maximum FOUTVCO of 2376 MHz. "#clock-cells": const: 1 diff --git a/sys/contrib/device-tree/Bindings/clock/ti,clkctrl.yaml b/sys/contrib/device-tree/Bindings/clock/ti,clkctrl.yaml new file mode 100644 index 000000000000..49787550ce45 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti,clkctrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments clkctrl clock + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Andreas Kemnade <andreas@kemnade.info> + +description: | + Texas Instruments SoCs can have a clkctrl clock controller for each + interconnect target module. The clkctrl clock controller manages functional + and interface clocks for each module. Each clkctrl controller can also + gate one or more optional functional clocks for a module, and can have one + or more clock muxes. There is a clkctrl clock controller typically for each + interconnect target module on omap4 and later variants. + + The clock consumers can specify the index of the clkctrl clock using + the hardware offset from the clkctrl instance register space. The optional + clocks can be specified by clkctrl hardware offset and the index of the + optional clock. + +properties: + compatible: + enum: + - ti,clkctrl + - ti,clkctrl-l4-cfg + - ti,clkctrl-l4-per + - ti,clkctrl-l4-secure + - ti,clkctrl-l4-wkup + + "#clock-cells": + const: 2 + + clock-output-names: + maxItems: 1 + + reg: + minItems: 1 + maxItems: 8 # arbitrary, should be enough + +required: + - compatible + - "#clock-cells" + - clock-output-names + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + + clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; + reg = <0x20 0x1b0>; + #clock-cells = <2>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/ti/composite.txt b/sys/contrib/device-tree/Bindings/clock/ti/composite.txt index 6f7e1331b546..238e6f7d74f8 100644 --- a/sys/contrib/device-tree/Bindings/clock/ti/composite.txt +++ b/sys/contrib/device-tree/Bindings/clock/ti/composite.txt @@ -16,8 +16,8 @@ merged to this clock. The component clocks shall be of one of the "ti,*composite*-clock" types. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/mux.txt -[3] Documentation/devicetree/bindings/clock/ti/divider.txt +[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml +[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml [4] Documentation/devicetree/bindings/clock/ti/gate.txt Required properties: diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,autoidle.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,autoidle.yaml new file mode 100644 index 000000000000..ed1bf182b64d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,autoidle.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,autoidle.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI autoidle clock + +maintainers: + - Tero Kristo <kristo@kernel.org> + - Sukrut Bellary <sbellary@baylibre.com> + +description: + Some clocks in TI SoC support the autoidle feature. These properties are + applicable only if the clock supports autoidle feature. It assumes a register + mapped clock which can be put to idle automatically by hardware based on + usage and configuration bit setting. Autoidle clock is never an individual + clock, it is always a derivative of some basic clock like a gate, divider, or + fixed-factor. + +properties: + ti,autoidle-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + bit shift of the autoidle enable bit for the clock + maximum: 31 + default: 0 + + ti,invert-autoidle-bit: + type: boolean + description: + autoidle is enabled by setting the bit to 0 + +additionalProperties: true diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,composite-clock.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,composite-clock.yaml new file mode 100644 index 000000000000..31a6794852c7 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,composite-clock.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments composite clock + +maintainers: + - Tero Kristo <kristo@kernel.org> + +description: | + *Deprecated design pattern: one node per clock* + + This binding assumes a register-mapped composite clock with multiple + different sub-types: + + a multiplexer clock with multiple input clock signals or parents, one + of which can be selected as output, this behaves exactly as [1]. + + an adjustable clock rate divider, this behaves exactly as [2]. + + a gating function which can be used to enable and disable the output + clock, this behaves exactly as [3]. + + The binding must provide a list of the component clocks that shall be + merged to this clock. The component clocks shall be of one of the + "ti,*composite*-clock" types. + + [1] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml + [2] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml + [3] Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml + +properties: + compatible: + const: ti,composite-clock + + "#clock-cells": + const: 0 + + clocks: true + + clock-output-names: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + usb_l4_gate_ick: clock-controller@a10 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + reg = <0x0a10>; + }; + + usb_l4_div_ick: clock-controller@a40 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + reg = <0x0a40>; + ti,index-starts-at-one; + }; + }; + + clock-controller { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,divider-clock.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,divider-clock.yaml new file mode 100644 index 000000000000..6729fcb839d2 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,divider-clock.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments divider clock + +maintainers: + - Tero Kristo <kristo@kernel.org> + +description: | + This clock It assumes a register-mapped adjustable clock rate divider + that does not gate and has only one input clock or parent. By default the + value programmed into the register is one less than the actual divisor value. + E.g: + + register value actual divisor value + 0 1 + 1 2 + 2 3 + + This assumption may be modified by the following optional properties: + + ti,index-starts-at-one - valid divisor values start at 1, not the default + of 0. E.g: + register value actual divisor value + 1 1 + 2 2 + 3 3 + + ti,index-power-of-two - valid divisor values are powers of two. E.g: + register value actual divisor value + 0 1 + 1 2 + 2 4 + + Additionally an array of valid dividers may be supplied like so: + + ti,dividers = <4>, <8>, <0>, <16>; + + Which will map the resulting values to a divisor table by their index: + register value actual divisor value + 0 4 + 1 8 + 2 <invalid divisor, skipped> + 3 16 + + Any zero value in this array means the corresponding bit-value is invalid + and must not be used. + + The binding must also provide the register to control the divider and + unless the divider array is provided, min and max dividers. Optionally + the number of bits to shift that mask, if necessary. If the shift value + is missing it is the same as supplying a zero shift. + + This binding can also optionally provide support to the hardware autoidle + feature. + +allOf: + - $ref: ti,autoidle.yaml# + +properties: + compatible: + enum: + - ti,divider-clock + - ti,composite-divider-clock + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,dividers: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + array of integers defining divisors + + ti,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + number of bits to shift the divider value + maximum: 31 + default: 0 + + ti,min-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + min divisor for dividing the input clock rate, only + needed if the first divisor is offset from the default value (1) + minimum: 1 + default: 1 + + ti,max-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max divisor for dividing the input clock rate, only needed + if ti,dividers is not defined. + + ti,index-starts-at-one: + type: boolean + description: + valid divisor programming starts at 1, not zero, + only valid if ti,dividers is not defined + + ti,index-power-of-two: + type: boolean + description: + valid divisor programming must be a power of two, + only valid if ti,dividers is not defined. + + ti,set-rate-parent: + type: boolean + description: + clk_set_rate is propagated to parent | + + ti,latch-bit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + latch the divider value to HW, only needed if the register + compatible access requires this. As an example dra76x DPLL_GMAC + H14 divider implements such behavior. + +dependentSchemas: + ti,dividers: + properties: + ti,min-div: false + ti,max-div: false + ti,index-power-of-two: false + ti,index-starts-at-one: false + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + reg = <0x190>; + ti,index-starts-at-one; + }; + + clock-controller@528 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&abe_clk>; + ti,bit-shift = <24>; + reg = <0x528>; + ti,max-div = <2>; + }; + + clock-controller@a40 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + reg = <0x0a40>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,fixed-factor-clock.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,fixed-factor-clock.yaml new file mode 100644 index 000000000000..7a63b0992976 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,fixed-factor-clock.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,fixed-factor-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI fixed factor rate clock sources + +maintainers: + - Tero Kristo <kristo@kernel.org> + - Sukrut Bellary <sbellary@baylibre.com> + +description: + This consists of a divider and a multiplier used to generate a fixed rate + clock. This also uses the autoidle support from TI autoidle clock. + +allOf: + - $ref: ti,autoidle.yaml# + +properties: + compatible: + const: ti,fixed-factor-clock + + "#clock-cells": + const: 0 + + reg: + maxItems: 1 + + ti,clock-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Fixed divider + minimum: 1 + + ti,clock-mult: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Fixed multiplier + minimum: 1 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + ti,set-rate-parent: + description: + Propagate to parent clock + type: boolean + +required: + - compatible + - clocks + - "#clock-cells" + - ti,clock-mult + - ti,clock-div + +unevaluatedProperties: false + +examples: + - | + bus{ + #address-cells = <1>; + #size-cells = <0>; + + clock@1b4 { + compatible = "ti,fixed-factor-clock"; + reg = <0x1b4>; + clocks = <&dpll_usb_ck>; + #clock-cells = <0>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + ti,invert-autoidle-bit; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,gate-clock.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,gate-clock.yaml new file mode 100644 index 000000000000..eaa727ab0d7f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,gate-clock.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments gate clock + +maintainers: + - Tero Kristo <kristo@kernel.org> + +description: | + *Deprecated design pattern: one node per clock* + + This clock is quite much similar to the basic gate-clock [1], however, + it supports a number of additional features. If no register + is provided for this clock, the code assumes that a clockdomain + will be controlled instead and the corresponding hw-ops for + that is used. + + [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml + [2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt + +properties: + compatible: + enum: + - ti,gate-clock # basic gate clock + - ti,wait-gate-clock # gate clock which waits until clock is + # active before returning from clk_enable() + - ti,dss-gate-clock # gate clock with DSS specific hardware + # handling + - ti,am35xx-gate-clock # gate clock with AM35xx specific hardware + # handling + - ti,clkdm-gate-clock # clockdomain gate clock, which derives its + # functional clock directly from a + # clockdomain, see [2] how to map + # clockdomains properly + - ti,hsdiv-gate-clock # gate clock with OMAP36xx specific hardware + # handling, required for a hardware errata + - ti,composite-gate-clock # composite gate clock, to be part of + # composite clock + - ti,composite-no-wait-gate-clock # composite gate clock that does not + # wait for clock to be active before + # returning from clk_enable() + "#clock-cells": + const: 0 + + clocks: true + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of bits to shift the bit-mask + maximum: 31 + default: 0 + + ti,set-bit-to-disable: + type: boolean + description: + Inverts default gate programming. Setting the bit + gates the clock and clearing the bit ungates the clock. + + ti,set-rate-parent: + type: boolean + description: + clk_set_rate is propagated to parent clock, + +if: + properties: + compatible: + contains: + const: ti,clkdm-gate-clock +then: + properties: + reg: false + required: + - compatible + - "#clock-cells" + - clocks +else: + required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@a00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <25>; + }; + + clock-controller@d00 { + compatible = "ti,hsdiv-gate-clock"; + reg = <0x0d00>; + #clock-cells = <0>; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + ti,set-bit-to-disable; + }; + }; + + - | + clock-controller { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clocks = <&emu_src_mux_ck>; + }; + diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,interface-clock.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,interface-clock.yaml new file mode 100644 index 000000000000..1eaf95d88e0b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,interface-clock.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interface clock. + +maintainers: + - Tero Kristo <kristo@kernel.org> + +description: | + This clock is quite much similar to the basic gate-clock[1], however, + it supports a number of additional features, including + companion clock finding (match corresponding functional gate + clock) and hardware autoidle enable / disable. + + [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml + +properties: + compatible: + enum: + - ti,omap3-interface-clock # basic OMAP3 interface clock + - ti,omap3-no-wait-interface-clock # interface clock which has no hardware + # capability for waiting clock to be ready + - ti,omap3-hsotgusb-interface-clock # interface clock with USB specific HW handling + - ti,omap3-dss-interface-clock # interface clock with DSS specific HW handling + - ti,omap3-ssi-interface-clock # interface clock with SSI specific HW handling + - ti,am35xx-interface-clock # interface clock with AM35xx specific HW handling + - ti,omap2430-interface-clock # interface clock with OMAP2430 specific HW handling + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,bit-shift: + description: + bit shift for the bit enabling/disabling the clock + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 31 + +required: + - compatible + - clocks + - '#clock-cells' + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + aes1_ick: clock-controller@3 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <3>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/ti/ti,mux-clock.yaml b/sys/contrib/device-tree/Bindings/clock/ti/ti,mux-clock.yaml new file mode 100644 index 000000000000..485b6aae85d4 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/ti/ti,mux-clock.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments mux clock + +maintainers: + - Tero Kristo <kristo@kernel.org> + +description: | + This clock assumes a register-mapped multiplexer with multiple inpt clock + signals or parents, one of which can be selected as output. This clock does + not gate or adjust the parent rate via a divider or multiplier. + + By default the "clocks" property lists the parents in the same order + as they are programmed into the register. E.g: + + clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; + + Results in programming the register as follows: + + register value selected parent clock + 0 foo_clock + 1 bar_clock + 2 baz_clock + + Some clock controller IPs do not allow a value of zero to be programmed + into the register, instead indexing begins at 1. The optional property + "index-starts-at-one" modified the scheme as follows: + + register value selected clock parent + 1 foo_clock + 2 bar_clock + 3 baz_clock + + The binding must provide the register to control the mux. Optionally + the number of bits to shift the control field in the register can be + supplied. If the shift value is missing it is the same as supplying + a zero shift. + +properties: + compatible: + enum: + - ti,mux-clock + - ti,composite-mux-clock + + "#clock-cells": + const: 0 + + clocks: true + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of bits to shift the bit-mask + maximum: 31 + default: 0 + + ti,index-starts-at-one: + type: boolean + description: + Valid input select programming starts at 1, not zero + + ti,set-rate-parent: + type: boolean + description: + clk_set_rate is propagated to parent clock, + not supported by the composite-mux-clock subtype. + + ti,latch-bit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Latch the mux value to HW, only needed if the register + access requires this. As an example, dra7x DPLL_GMAC H14 muxing + implements such behavior. + maximum: 31 + +if: + properties: + compatible: + contains: + const: ti,composite-mux-clock +then: + properties: + ti,set-rate-parent: false + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@110 { + compatible = "ti,mux-clock"; + reg = <0x0110>; + #clock-cells = <0>; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>; + ti,index-starts-at-one; + ti,set-rate-parent; + }; + + clock-controller@120 { + compatible = "ti,composite-mux-clock"; + reg = <0x0120>; + #clock-cells = <0>; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/clock/xlnx,clocking-wizard.yaml b/sys/contrib/device-tree/Bindings/clock/xlnx,clocking-wizard.yaml index 9d5324dc1027..b44a76a958f4 100644 --- a/sys/contrib/device-tree/Bindings/clock/xlnx,clocking-wizard.yaml +++ b/sys/contrib/device-tree/Bindings/clock/xlnx,clocking-wizard.yaml @@ -39,6 +39,11 @@ properties: - const: clk_in1 - const: s_axi_aclk + xlnx,static-config: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicate whether the core has been configured without support for dynamic + runtime reconfguration of the clocking primitive MMCM/PLL. xlnx,speed-grade: $ref: /schemas/types.yaml#/definitions/uint32 @@ -70,6 +75,7 @@ examples: compatible = "xlnx,clocking-wizard"; reg = <0xb0000000 0x10000>; #clock-cells = <1>; + xlnx,static-config; xlnx,speed-grade = <1>; xlnx,nr-outputs = <6>; clock-names = "clk_in1", "s_axi_aclk"; diff --git a/sys/contrib/device-tree/Bindings/clock/xlnx,vcu.yaml b/sys/contrib/device-tree/Bindings/clock/xlnx,vcu.yaml new file mode 100644 index 000000000000..19dc923e2ee9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/clock/xlnx,vcu.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: LogicoreIP designed compatible with Xilinx ZYNQ family. + +maintainers: + - Rohit Visavalia <rohit.visavalia@amd.com> + +description: + LogicoreIP design to provide the isolation between processing system + and programmable logic. Also provides the list of register set to configure + the frequency. + +properties: + compatible: + items: + - enum: + - xlnx,vcu + - xlnx,vcu-logicoreip-1.0 + + reg: + maxItems: 1 + + clocks: + items: + - description: pll ref clocksource + - description: aclk + + clock-names: + items: + - const: pll_ref + - const: aclk + + reset-gpios: + maxItems: 1 + +required: + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + fpga { + #address-cells = <2>; + #size-cells = <2>; + xlnx_vcu: vcu@a0040000 { + compatible = "xlnx,vcu-logicoreip-1.0"; + reg = <0x0 0xa0040000 0x0 0x1000>; + reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>; + clocks = <&si570_1>, <&clkc 71>; + clock-names = "pll_ref", "aclk"; + }; + }; |