diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/dma')
42 files changed, 1757 insertions, 90 deletions
diff --git a/sys/contrib/device-tree/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/sys/contrib/device-tree/Bindings/dma/allwinner,sun50i-a64-dma.yaml index ec2d7a789ffe..0f2501f72cca 100644 --- a/sys/contrib/device-tree/Bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -28,6 +28,9 @@ properties: - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma + - items: + - const: allwinner,sun50i-h616-dma + - const: allwinner,sun50i-a100-dma reg: maxItems: 1 @@ -59,10 +62,11 @@ required: if: properties: compatible: - enum: - - allwinner,sun20i-d1-dma - - allwinner,sun50i-a100-dma - - allwinner,sun50i-h6-dma + contains: + enum: + - allwinner,sun20i-d1-dma + - allwinner,sun50i-a100-dma + - allwinner,sun50i-h6-dma then: properties: diff --git a/sys/contrib/device-tree/Bindings/dma/atmel-xdma.txt b/sys/contrib/device-tree/Bindings/dma/atmel-xdma.txt index 510b7f25ba24..76d649b3a25d 100644 --- a/sys/contrib/device-tree/Bindings/dma/atmel-xdma.txt +++ b/sys/contrib/device-tree/Bindings/dma/atmel-xdma.txt @@ -3,7 +3,8 @@ * XDMA Controller Required properties: - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or - "microchip,sama7g5-dma". + "microchip,sama7g5-dma" or + "microchip,sam9x7-dma", "atmel,sama5d4-dma". - reg: Should contain DMA registers location and length. - interrupts: Should contain DMA interrupt. - #dma-cells: Must be <1>, used to represent the number of integer cells in diff --git a/sys/contrib/device-tree/Bindings/dma/brcm,bcm2835-dma.yaml b/sys/contrib/device-tree/Bindings/dma/brcm,bcm2835-dma.yaml new file mode 100644 index 000000000000..c9b9a5490826 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/brcm,bcm2835-dma.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835 DMA controller + +maintainers: + - Nicolas Saenz Julienne <nsaenz@kernel.org> + +description: + The BCM2835 DMA controller has 16 channels in total. Only the lower + 13 channels have an associated IRQ. Some arbitrary channels are used by the + VideoCore firmware (1,3,6,7 in the current firmware version). The channels + 0, 2 and 3 have special functionality and should not be used by the driver. + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: brcm,bcm2835-dma + + reg: + maxItems: 1 + + interrupts: + description: + Should contain the DMA interrupts associated to the DMA channels in + ascending order. + minItems: 1 + maxItems: 16 + + interrupt-names: + minItems: 1 + maxItems: 16 + + '#dma-cells': + description: The single cell represents the DREQ number. + const: 1 + + brcm,dma-channel-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask of available DMA channels in ascending order that are + not reserved by firmware and are available to the + kernel. i.e. first channel corresponds to LSB. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - brcm,dma-channel-mask + +examples: + - | + dma-controller@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16>, + <1 17>, + <1 18>, + <1 19>, + <1 20>, + <1 21>, + <1 22>, + <1 23>, + <1 24>, + <1 25>, + <1 26>, + /* dma channel 11-14 share one irq */ + <1 27>, + <1 27>, + <1 27>, + <1 27>, + /* unused shared irq for all channels */ + <1 28>; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5", + "dma6", + "dma7", + "dma8", + "dma9", + "dma10", + "dma11", + "dma12", + "dma13", + "dma14", + "dma-shared-all"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x7f35>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/dma/cirrus,ep9301-dma-m2m.yaml b/sys/contrib/device-tree/Bindings/dma/cirrus,ep9301-dma-m2m.yaml new file mode 100644 index 000000000000..871b76ddf90f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/cirrus,ep9301-dma-m2m.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic ep93xx SoC DMA controller + +maintainers: + - Alexander Sverdlin <alexander.sverdlin@gmail.com> + - Nikita Shubin <nikita.shubin@maquefel.me> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-dma-m2m + - items: + - enum: + - cirrus,ep9302-dma-m2m + - cirrus,ep9307-dma-m2m + - cirrus,ep9312-dma-m2m + - cirrus,ep9315-dma-m2m + - const: cirrus,ep9301-dma-m2m + + reg: + items: + - description: m2m0 channel registers + - description: m2m1 channel registers + + clocks: + items: + - description: m2m0 channel gate clock + - description: m2m1 channel gate clock + + clock-names: + items: + - const: m2m0 + - const: m2m1 + + interrupts: + items: + - description: m2m0 channel interrupt + - description: m2m1 channel interrupt + + '#dma-cells': + const: 2 + description: | + The first cell is the unique device channel number as indicated by this + table for ep93xx: + + 10: SPI controller + 11: IDE controller + + The second cell is the DMA direction line number: + + 1: Memory to device + 2: Device to memory + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/cirrus,ep9301-syscon.h> + dma-controller@80000100 { + compatible = "cirrus,ep9301-dma-m2m"; + reg = <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks = <&syscon EP93XX_CLK_M2M0>, + <&syscon EP93XX_CLK_M2M1>; + clock-names = "m2m0", "m2m1"; + interrupt-parent = <&vic0>; + interrupts = <17>, <18>; + #dma-cells = <2>; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/cirrus,ep9301-dma-m2p.yaml b/sys/contrib/device-tree/Bindings/dma/cirrus,ep9301-dma-m2p.yaml new file mode 100644 index 000000000000..d14c31553543 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/cirrus,ep9301-dma-m2p.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic ep93xx SoC M2P DMA controller + +maintainers: + - Alexander Sverdlin <alexander.sverdlin@gmail.com> + - Nikita Shubin <nikita.shubin@maquefel.me> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-dma-m2p + - items: + - enum: + - cirrus,ep9302-dma-m2p + - cirrus,ep9307-dma-m2p + - cirrus,ep9312-dma-m2p + - cirrus,ep9315-dma-m2p + - const: cirrus,ep9301-dma-m2p + + reg: + items: + - description: m2p0 channel registers + - description: m2p1 channel registers + - description: m2p2 channel registers + - description: m2p3 channel registers + - description: m2p4 channel registers + - description: m2p5 channel registers + - description: m2p6 channel registers + - description: m2p7 channel registers + - description: m2p8 channel registers + - description: m2p9 channel registers + + clocks: + items: + - description: m2p0 channel gate clock + - description: m2p1 channel gate clock + - description: m2p2 channel gate clock + - description: m2p3 channel gate clock + - description: m2p4 channel gate clock + - description: m2p5 channel gate clock + - description: m2p6 channel gate clock + - description: m2p7 channel gate clock + - description: m2p8 channel gate clock + - description: m2p9 channel gate clock + + clock-names: + items: + - const: m2p0 + - const: m2p1 + - const: m2p2 + - const: m2p3 + - const: m2p4 + - const: m2p5 + - const: m2p6 + - const: m2p7 + - const: m2p8 + - const: m2p9 + + interrupts: + items: + - description: m2p0 channel interrupt + - description: m2p1 channel interrupt + - description: m2p2 channel interrupt + - description: m2p3 channel interrupt + - description: m2p4 channel interrupt + - description: m2p5 channel interrupt + - description: m2p6 channel interrupt + - description: m2p7 channel interrupt + - description: m2p8 channel interrupt + - description: m2p9 channel interrupt + + '#dma-cells': + const: 2 + description: | + The first cell is the unique device channel number as indicated by this + table for ep93xx: + + 0: I2S channel 1 + 1: I2S channel 2 (unused) + 2: AC97 channel 1 (unused) + 3: AC97 channel 2 (unused) + 4: AC97 channel 3 (unused) + 5: I2S channel 3 (unused) + 6: UART1 (unused) + 7: UART2 (unused) + 8: UART3 (unused) + 9: IRDA (unused) + + The second cell is the DMA direction line number: + + 1: Memory to device + 2: Device to memory + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/cirrus,ep9301-syscon.h> + dma-controller@80000000 { + compatible = "cirrus,ep9301-dma-m2p"; + reg = <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks = <&syscon EP93XX_CLK_M2P0>, + <&syscon EP93XX_CLK_M2P1>, + <&syscon EP93XX_CLK_M2P2>, + <&syscon EP93XX_CLK_M2P3>, + <&syscon EP93XX_CLK_M2P4>, + <&syscon EP93XX_CLK_M2P5>, + <&syscon EP93XX_CLK_M2P6>, + <&syscon EP93XX_CLK_M2P7>, + <&syscon EP93XX_CLK_M2P8>, + <&syscon EP93XX_CLK_M2P9>; + clock-names = "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + interrupt-parent = <&vic0>; + interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + #dma-cells = <2>; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/dma-controller.yaml b/sys/contrib/device-tree/Bindings/dma/dma-controller.yaml index 04d150d4d15d..e6afca558c2d 100644 --- a/sys/contrib/device-tree/Bindings/dma/dma-controller.yaml +++ b/sys/contrib/device-tree/Bindings/dma/dma-controller.yaml @@ -19,19 +19,4 @@ properties: additionalProperties: true -examples: - - | - dma: dma-controller@48000000 { - compatible = "ti,omap-sdma"; - reg = <0x48000000 0x1000>; - interrupts = <0 12 0x4>, - <0 13 0x4>, - <0 14 0x4>, - <0 15 0x4>; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - dma-channel-mask = <0xfffe>; - }; - ... diff --git a/sys/contrib/device-tree/Bindings/dma/dma-router.yaml b/sys/contrib/device-tree/Bindings/dma/dma-router.yaml index 346fe0fa4460..5ad2febc581e 100644 --- a/sys/contrib/device-tree/Bindings/dma/dma-router.yaml +++ b/sys/contrib/device-tree/Bindings/dma/dma-router.yaml @@ -40,15 +40,4 @@ required: additionalProperties: true -examples: - - | - sdma_xbar: dma-router@4a002b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0x4a002b78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; - }; - ... diff --git a/sys/contrib/device-tree/Bindings/dma/fsl,edma.yaml b/sys/contrib/device-tree/Bindings/dma/fsl,edma.yaml index 5fd8fc604261..d54140f18d34 100644 --- a/sys/contrib/device-tree/Bindings/dma/fsl,edma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/fsl,edma.yaml @@ -21,33 +21,61 @@ properties: - enum: - fsl,vf610-edma - fsl,imx7ulp-edma + - fsl,imx8qm-edma + - fsl,imx8ulp-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 + - fsl,imx95-edma5 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma reg: - minItems: 2 + minItems: 1 maxItems: 3 interrupts: - minItems: 2 - maxItems: 17 + minItems: 1 + maxItems: 64 interrupt-names: - minItems: 2 - maxItems: 17 + minItems: 1 + maxItems: 64 "#dma-cells": - const: 2 + description: | + Specifies the number of cells needed to encode an DMA channel. + + Encode for cells number 2: + cell 0: index of dma channel mux instance. + cell 1: peripheral dma request id. + + Encode for cells number 3: + cell 0: peripheral dma request id. + cell 1: dma channel priority. + cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h + enum: + - 2 + - 3 dma-channels: - const: 32 + minimum: 1 + maximum: 64 clocks: - maxItems: 2 + minItems: 1 + maxItems: 33 clock-names: - maxItems: 2 + minItems: 1 + maxItems: 33 + + power-domains: + description: + The number of power domains matches the number of channels, arranged + in ascending order according to their associated DMA channels. + minItems: 1 + maxItems: 64 big-endian: description: | @@ -60,7 +88,6 @@ required: - compatible - reg - interrupts - - clocks - dma-channels allOf: @@ -69,21 +96,53 @@ allOf: properties: compatible: contains: + enum: + - fsl,imx8qm-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 + - fsl,imx95-edma5 + then: + properties: + "#dma-cells": + const: 3 + # It is not necessary to write the interrupt name for each channel. + # instead, you can simply maintain the sequential IRQ numbers as + # defined for the DMA channels. + interrupt-names: false + clock-names: + items: + - const: dma + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: const: fsl,vf610-edma then: properties: + clocks: + minItems: 2 + maxItems: 2 clock-names: items: - const: dmamux0 - const: dmamux1 interrupts: + minItems: 2 maxItems: 2 interrupt-names: items: - const: edma-tx - const: edma-err reg: + minItems: 2 maxItems: 3 + "#dma-cells": + const: 2 + dma-channels: + const: 32 - if: properties: @@ -92,14 +151,75 @@ allOf: const: fsl,imx7ulp-edma then: properties: + clock: + minItems: 2 + maxItems: 2 clock-names: items: - const: dma - const: dmamux0 interrupts: + minItems: 2 maxItems: 17 reg: + minItems: 2 maxItems: 2 + "#dma-cells": + const: 2 + dma-channels: + const: 32 + + - if: + properties: + compatible: + contains: + const: fsl,imx8ulp-edma + then: + properties: + clocks: + minItems: 33 + clock-names: + minItems: 33 + items: + oneOf: + - const: dma + - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$" + + interrupt-names: false + interrupts: + minItems: 32 + "#dma-cells": + const: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,vf610-edma + - fsl,imx7ulp-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 + - fsl,imx95-edma5 + - fsl,imx8ulp-edma + - fsl,ls1028a-edma + then: + required: + - clocks + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-adma + - fsl,imx8qm-edma + then: + required: + - power-domains + else: + properties: + power-domains: false unevaluatedProperties: false @@ -153,3 +273,30 @@ examples: clock-names = "dma", "dmamux0"; clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + dma-controller@5a9f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a9f0000 0x90000>; + #dma-cells = <3>; + dma-channels = <8>; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/fsl,imx-dma.yaml b/sys/contrib/device-tree/Bindings/dma/fsl,imx-dma.yaml new file mode 100644 index 000000000000..75957f9fb58b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/fsl,imx-dma.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,imx-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Direct Memory Access (DMA) Controller for i.MX + +maintainers: + - Animesh Agarwal <animeshagarwal28@gmail.com> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx1-dma + - fsl,imx21-dma + - fsl,imx27-dma + + reg: + maxItems: 1 + + interrupts: + items: + - description: DMA complete interrupt + - description: DMA Error interrupt + minItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: ahb + + "#dma-cells": + const: 1 + + dma-channels: + const: 16 + + dma-requests: + description: Number of DMA requests supported. + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx27-clock.h> + + dma-controller@10001000 { + compatible = "fsl,imx27-dma"; + reg = <0x10001000 0x1000>; + interrupts = <32 33>; + #dma-cells = <1>; + dma-channels = <16>; + clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, <&clks IMX27_CLK_DMA_AHB_GATE>; + clock-names = "ipg", "ahb"; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/fsl,imx-sdma.yaml b/sys/contrib/device-tree/Bindings/dma/fsl,imx-sdma.yaml index b95dd8db5a30..738b25b88b37 100644 --- a/sys/contrib/device-tree/Bindings/dma/fsl,imx-sdma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/fsl,imx-sdma.yaml @@ -92,7 +92,9 @@ properties: description: needs firmware more than ver 2 - Shared ASRC: 23 - SAI: 24 - - HDMI Audio: 25 + - Multi SAI: 25 + - HDMI Audio: 26 + - I2C: 27 The third cell: transfer priority ID enum: diff --git a/sys/contrib/device-tree/Bindings/dma/fsl,mxs-dma.yaml b/sys/contrib/device-tree/Bindings/dma/fsl,mxs-dma.yaml index add9c77e8b52..a17cf2360dd4 100644 --- a/sys/contrib/device-tree/Bindings/dma/fsl,mxs-dma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/fsl,mxs-dma.yaml @@ -11,6 +11,17 @@ maintainers: allOf: - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-dma-apbh + then: + required: + - power-domains + else: + properties: + power-domains: false properties: compatible: @@ -20,6 +31,7 @@ properties: - fsl,imx6q-dma-apbh - fsl,imx6sx-dma-apbh - fsl,imx7d-dma-apbh + - fsl,imx8qxp-dma-apbh - const: fsl,imx28-dma-apbh - enum: - fsl,imx23-dma-apbh @@ -42,6 +54,9 @@ properties: dma-channels: enum: [4, 8, 16] + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/dma/fsl-qdma.yaml b/sys/contrib/device-tree/Bindings/dma/fsl-qdma.yaml new file mode 100644 index 000000000000..9401b1f6300d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/fsl-qdma.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl-qdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Layerscape SoC qDMA Controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - const: fsl,ls1021a-qdma + - items: + - enum: + - fsl,ls1028a-qdma + - fsl,ls1043a-qdma + - fsl,ls1046a-qdma + - const: fsl,ls1021a-qdma + + reg: + items: + - description: Controller regs + - description: Status regs + - description: Block regs + + interrupts: + minItems: 2 + maxItems: 5 + + interrupt-names: + minItems: 2 + items: + - const: qdma-error + - const: qdma-queue0 + - const: qdma-queue1 + - const: qdma-queue2 + - const: qdma-queue3 + + dma-channels: + minimum: 1 + maximum: 64 + + fsl,dma-queues: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Should contain number of queues supported. + minimum: 1 + maximum: 4 + + block-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: the virtual block number + + block-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: the offset of different virtual block + + status-sizes: + $ref: /schemas/types.yaml#/definitions/uint32 + description: status queue size of per virtual block + + queue-sizes: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + command queue size of per virtual block, the size number + based on queues + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - fsl,dma-queues + - block-number + - block-offset + - status-sizes + - queue-sizes + +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1028a-qdma + - fsl,ls1043a-qdma + - fsl,ls1046a-qdma + then: + properties: + interrupts: + minItems: 5 + interrupt-names: + minItems: 5 + else: + properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x8388000 0x1000>, /* Controller regs */ + <0x8389000 0x1000>, /* Status regs */ + <0x838a000 0x2000>; /* Block regs */ + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1"; + #dma-cells = <1>; + dma-channels = <8>; + block-number = <2>; + block-offset = <0x1000>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + fsl,dma-queues = <2>; + }; + diff --git a/sys/contrib/device-tree/Bindings/dma/ingenic,dma.yaml b/sys/contrib/device-tree/Bindings/dma/ingenic,dma.yaml index 37400496e086..d9cca3006e73 100644 --- a/sys/contrib/device-tree/Bindings/dma/ingenic,dma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/ingenic,dma.yaml @@ -68,7 +68,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: > Bitmask of channels to reserve for devices that need a specific - channel. These channels will only be assigned when explicitely + channel. These channels will only be assigned when explicitly requested by a client. The primary use for this is channels 0 and 1, which can be configured to have special behaviour for NAND/BCH when using programmable firmware. diff --git a/sys/contrib/device-tree/Bindings/dma/loongson,ls1b-apbdma.yaml b/sys/contrib/device-tree/Bindings/dma/loongson,ls1b-apbdma.yaml new file mode 100644 index 000000000000..4c7d2fb7b292 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/loongson,ls1b-apbdma.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 APB DMA Controller + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +description: + Loongson-1 APB DMA controller provides 3 independent channels for + peripherals such as NAND, audio playback and capture. + +properties: + compatible: + oneOf: + - const: loongson,ls1b-apbdma + - items: + - enum: + - loongson,ls1a-apbdma + - loongson,ls1c-apbdma + - const: loongson,ls1b-apbdma + + reg: + maxItems: 1 + + interrupts: + items: + - description: NAND interrupt + - description: Audio playback interrupt + - description: Audio capture interrupt + + interrupt-names: + items: + - const: ch0 + - const: ch1 + - const: ch2 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - '#dma-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + dma-controller@1fd01160 { + compatible = "loongson,ls1b-apbdma"; + reg = <0x1fd01160 0x4>; + interrupt-parent = <&intc0>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>, + <14 IRQ_TYPE_EDGE_RISING>, + <15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ch0", "ch1", "ch2"; + #dma-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/loongson,ls2x-apbdma.yaml b/sys/contrib/device-tree/Bindings/dma/loongson,ls2x-apbdma.yaml new file mode 100644 index 000000000000..6a1b49a49a64 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/loongson,ls2x-apbdma.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/loongson,ls2x-apbdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS2X APB DMA controller + +description: + The Loongson LS2X APB DMA controller is used for transferring data + between system memory and the peripherals on the APB bus. + +maintainers: + - Binbin Zhou <zhoubinbin@loongson.cn> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls2k1000-apbdma + - items: + - const: loongson,ls2k0500-apbdma + - const: loongson,ls2k1000-apbdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - '#dma-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/loongson,ls2k-clk.h> + + dma-controller@1fe00c00 { + compatible = "loongson,ls2k1000-apbdma"; + reg = <0x1fe00c00 0x8>; + interrupt-parent = <&liointc1>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LOONGSON2_APB_CLK>; + #dma-cells = <1>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/dma/marvell,mmp-dma.yaml b/sys/contrib/device-tree/Bindings/dma/marvell,mmp-dma.yaml new file mode 100644 index 000000000000..d447d5207be0 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/marvell,mmp-dma.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP DMA controller + +maintainers: + - Duje Mihanović <duje.mihanovic@skole.hr> + +description: + Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio. + +properties: + compatible: + enum: + - marvell,pdma-1.0 + - marvell,adma-1.0 + - marvell,pxa910-squ + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt lines for the controller, may be shared or one per DMA channel + minItems: 1 + + asram: + description: + A phandle to the SRAM pool + $ref: /schemas/types.yaml#/definitions/phandle + + '#dma-channels': + deprecated: true + + '#dma-requests': + deprecated: true + +required: + - compatible + - reg + - interrupts + - '#dma-cells' + +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - marvell,pdma-1.0 + then: + properties: + asram: false + else: + required: + - asram + +unevaluatedProperties: false + +examples: + - | + dma-controller@d4000000 { + compatible = "marvell,pdma-1.0"; + reg = <0xd4000000 0x10000>; + interrupts = <47>; + #dma-cells = <2>; + dma-channels = <16>; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/marvell,xor-v2.yaml b/sys/contrib/device-tree/Bindings/dma/marvell,xor-v2.yaml new file mode 100644 index 000000000000..646b4e779d8a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/marvell,xor-v2.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell XOR v2 engines + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + +properties: + compatible: + oneOf: + - const: marvell,xor-v2 + - items: + - enum: + - marvell,armada-7k-xor + - const: marvell,xor-v2 + + reg: + items: + - description: DMA registers + - description: global registers + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: reg + + msi-parent: + description: + Phandle to the MSI-capable interrupt controller used for + interrupts. + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - msi-parent + - dma-coherent + +additionalProperties: false + +examples: + - | + xor0@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; + clocks = <&ap_clk 0>, <&ap_clk 1>; + clock-names = "core", "reg"; + msi-parent = <&gic_v2m0>; + dma-coherent; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/mediatek,mt7622-hsdma.yaml b/sys/contrib/device-tree/Bindings/dma/mediatek,mt7622-hsdma.yaml new file mode 100644 index 000000000000..3f1e120e40a3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/mediatek,mt7622-hsdma.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek High-Speed DMA Controller + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-hsdma + - mediatek,mt7623-hsdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: hsdma + + power-domains: + maxItems: 1 + + "#dma-cells": + description: Channel number + const: 1 + +required: + - reg + - interrupts + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt2701-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt2701-power.h> + + dma-controller@1b007000 { + compatible = "mediatek,mt7623-hsdma"; + reg = <0x1b007000 0x1000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; + clocks = <ðsys CLK_ETHSYS_HSDMA>; + clock-names = "hsdma"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + #dma-cells = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/dma/nvidia,tegra20-apbdma.txt b/sys/contrib/device-tree/Bindings/dma/nvidia,tegra20-apbdma.txt index c6908e7c42cc..447fb44e7abe 100644 --- a/sys/contrib/device-tree/Bindings/dma/nvidia,tegra20-apbdma.txt +++ b/sys/contrib/device-tree/Bindings/dma/nvidia,tegra20-apbdma.txt @@ -2,7 +2,7 @@ Required properties: - compatible: Should be "nvidia,<chip>-apbdma" -- reg: Should contain DMA registers location and length. This shuld include +- reg: Should contain DMA registers location and length. This should include all of the per-channel registers. - interrupts: Should contain all of the per-channel DMA interrupts. - clocks: Must contain one entry, for the module clock. diff --git a/sys/contrib/device-tree/Bindings/dma/nvidia,tegra210-adma.yaml b/sys/contrib/device-tree/Bindings/dma/nvidia,tegra210-adma.yaml index 4003dbe94940..877147e95ecc 100644 --- a/sys/contrib/device-tree/Bindings/dma/nvidia,tegra210-adma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/nvidia,tegra210-adma.yaml @@ -53,6 +53,9 @@ properties: ADMA_CHn_CTRL register. const: 1 + dma-channel-mask: + maxItems: 1 + required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/dma/nxp,lpc3220-dmamux.yaml b/sys/contrib/device-tree/Bindings/dma/nxp,lpc3220-dmamux.yaml new file mode 100644 index 000000000000..32f208744154 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/nxp,lpc3220-dmamux.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nxp,lpc3220-dmamux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DMA multiplexer for LPC32XX SoC (DMA request router) + +maintainers: + - J.M.B. Downing <jonathan.downing@nautel.com> + - Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> + +allOf: + - $ref: dma-router.yaml# + +properties: + compatible: + const: nxp,lpc3220-dmamux + + reg: + maxItems: 1 + + dma-masters: + description: phandle to a dma node compatible with arm,pl080 + maxItems: 1 + + "#dma-cells": + const: 3 + description: | + First two cells same as for device pointed in dma-masters. + Third cell represents mux value for the request. + +required: + - compatible + - reg + - dma-masters + +additionalProperties: false + +examples: + - | + dma-router@7c { + compatible = "nxp,lpc3220-dmamux"; + reg = <0x7c 0x8>; + dma-masters = <&dma>; + #dma-cells = <3>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/dma/qcom,bam-dma.yaml b/sys/contrib/device-tree/Bindings/dma/qcom,bam-dma.yaml index f1ddcf672261..3ad0d9b1fbc5 100644 --- a/sys/contrib/device-tree/Bindings/dma/qcom,bam-dma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/qcom,bam-dma.yaml @@ -15,13 +15,19 @@ allOf: properties: compatible: - enum: - # APQ8064, IPQ8064 and MSM8960 - - qcom,bam-v1.3.0 - # MSM8974, APQ8074 and APQ8084 - - qcom,bam-v1.4.0 - # MSM8916 and SDM845 - - qcom,bam-v1.7.0 + oneOf: + - enum: + # APQ8064, IPQ8064 and MSM8960 + - qcom,bam-v1.3.0 + # MSM8974, APQ8074 and APQ8084 + - qcom,bam-v1.4.0 + # MSM8916, SDM630 + - qcom,bam-v1.7.0 + - items: + - enum: + # SDM845, SM6115, SM8150, SM8250 and QCM2290 + - qcom,bam-v1.7.4 + - const: qcom,bam-v1.7.0 clocks: maxItems: 1 @@ -38,7 +44,7 @@ properties: iommus: minItems: 1 - maxItems: 4 + maxItems: 6 num-channels: $ref: /schemas/types.yaml#/definitions/uint32 @@ -48,7 +54,7 @@ properties: qcom,controlled-remotely: type: boolean description: - Indicates that the bam is controlled by remote proccessor i.e. execution + Indicates that the bam is controlled by remote processor i.e. execution environment. qcom,ee: @@ -81,6 +87,15 @@ required: - qcom,ee - reg +anyOf: + - required: + - qcom,powered-remotely + - required: + - qcom,controlled-remotely + - required: + - clocks + - clock-names + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/dma/qcom,gpi.yaml b/sys/contrib/device-tree/Bindings/dma/qcom,gpi.yaml index f61145c91b6d..4df4e61895d2 100644 --- a/sys/contrib/device-tree/Bindings/dma/qcom,gpi.yaml +++ b/sys/contrib/device-tree/Bindings/dma/qcom,gpi.yaml @@ -27,11 +27,14 @@ properties: - qcom,qcm2290-gpi-dma - qcom,qdu1000-gpi-dma - qcom,sc7280-gpi-dma + - qcom,sdx75-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - qcom,sm8550-gpi-dma + - qcom,sm8650-gpi-dma + - qcom,x1e80100-gpi-dma - const: qcom,sm6350-gpi-dma - items: - enum: @@ -69,6 +72,8 @@ properties: dma-channel-mask: maxItems: 1 + dma-coherent: true + required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/dma/renesas,rcar-dmac.yaml b/sys/contrib/device-tree/Bindings/dma/renesas,rcar-dmac.yaml index 03aa067b1229..04fc4a99a7cb 100644 --- a/sys/contrib/device-tree/Bindings/dma/renesas,rcar-dmac.yaml +++ b/sys/contrib/device-tree/Bindings/dma/renesas,rcar-dmac.yaml @@ -46,6 +46,7 @@ properties: - renesas,dmac-r8a779a0 # R-Car V3U - renesas,dmac-r8a779f0 # R-Car S4-8 - renesas,dmac-r8a779g0 # R-Car V4H + - renesas,dmac-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-dmac # R-Car Gen4 reg: true diff --git a/sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml b/sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml index c284abc6784a..ca24cf48769f 100644 --- a/sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml +++ b/sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml @@ -16,9 +16,10 @@ properties: compatible: items: - enum: - - renesas,r9a07g043-dmac # RZ/G2UL + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five - renesas,r9a07g044-dmac # RZ/G2{L,LC} - renesas,r9a07g054-dmac # RZ/V2L + - renesas,r9a08g045-dmac # RZ/G3S - const: renesas,rz-dmac reg: diff --git a/sys/contrib/device-tree/Bindings/dma/sifive,fu540-c000-pdma.yaml b/sys/contrib/device-tree/Bindings/dma/sifive,fu540-c000-pdma.yaml index a1af0b906365..3b22183a1a37 100644 --- a/sys/contrib/device-tree/Bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/sifive,fu540-c000-pdma.yaml @@ -29,6 +29,7 @@ properties: compatible: items: - enum: + - microchip,mpfs-pdma - sifive,fu540-c000-pdma - const: sifive,pdma0 description: diff --git a/sys/contrib/device-tree/Bindings/dma/snps,dma-spear1340.yaml b/sys/contrib/device-tree/Bindings/dma/snps,dma-spear1340.yaml index 5da8291a7de0..c21a4f073f6c 100644 --- a/sys/contrib/device-tree/Bindings/dma/snps,dma-spear1340.yaml +++ b/sys/contrib/device-tree/Bindings/dma/snps,dma-spear1340.yaml @@ -93,10 +93,10 @@ properties: data-width: $ref: /schemas/types.yaml#/definitions/uint32-array description: Data bus width per each DMA master in bytes. + minItems: 1 + maxItems: 4 items: - maxItems: 4 - items: - enum: [4, 8, 16, 32] + enum: [4, 8, 16, 32] data_width: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -106,28 +106,28 @@ properties: deprecated. It' usage is discouraged in favor of data-width one. Moreover the property incorrectly permits to define data-bus width of 8 and 16 bits, which is impossible in accordance with DW DMAC IP-core data book. + minItems: 1 + maxItems: 4 items: - maxItems: 4 - items: - enum: - - 0 # 8 bits - - 1 # 16 bits - - 2 # 32 bits - - 3 # 64 bits - - 4 # 128 bits - - 5 # 256 bits - default: 0 + enum: + - 0 # 8 bits + - 1 # 16 bits + - 2 # 32 bits + - 3 # 64 bits + - 4 # 128 bits + - 5 # 256 bits + default: 0 multi-block: $ref: /schemas/types.yaml#/definitions/uint32-array description: | LLP-based multi-block transfer supported by hardware per each DMA channel. + minItems: 1 + maxItems: 8 items: - maxItems: 8 - items: - enum: [0, 1] - default: 1 + enum: [0, 1] + default: 1 snps,max-burst-len: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -138,11 +138,11 @@ properties: will be from 1 to max-burst-len words. It's an array property with one cell per channel in the units determined by the value set in the CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width). + minItems: 1 + maxItems: 8 items: - maxItems: 8 - items: - enum: [4, 8, 16, 32, 64, 128, 256] - default: 256 + enum: [4, 8, 16, 32, 64, 128, 256] + default: 256 snps,dma-protection-control: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/sys/contrib/device-tree/Bindings/dma/snps,dw-axi-dmac.yaml b/sys/contrib/device-tree/Bindings/dma/snps,dw-axi-dmac.yaml index 363cf8bd150d..525f5f3932f5 100644 --- a/sys/contrib/device-tree/Bindings/dma/snps,dw-axi-dmac.yaml +++ b/sys/contrib/device-tree/Bindings/dma/snps,dw-axi-dmac.yaml @@ -21,6 +21,7 @@ properties: - snps,axi-dma-1.01a - intel,kmb-axi-dma - starfive,jh7110-axi-dma + - starfive,jh8100-axi-dma reg: minItems: 1 diff --git a/sys/contrib/device-tree/Bindings/dma/sprd,sc9860-dma.yaml b/sys/contrib/device-tree/Bindings/dma/sprd,sc9860-dma.yaml new file mode 100644 index 000000000000..94647219c021 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/sprd,sc9860-dma.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 DMA controller + +description: | + There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP + DMA controller, it can or do not request the IRQ, which will save + system power without resuming system by DMA interrupts if AGCP DMA + does not request the IRQ. + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + compatible: + const: sprd,sc9860-dma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: DMA enable clock + - description: optional ashb_eb clock, only for the AGCP DMA controller + + clock-names: + minItems: 1 + items: + - const: enable + - const: ashb_eb + + '#dma-cells': + const: 1 + + dma-channels: + const: 32 + + '#dma-channels': + const: 32 + deprecated: true + +required: + - compatible + - reg + - clocks + - clock-names + - '#dma-cells' + - dma-channels + +allOf: + - $ref: dma-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/sprd,sc9860-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + /* AP DMA controller */ + dma-controller@20100000 { + compatible = "sprd,sc9860-dma"; + reg = <0x20100000 0x4000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apahb_gate CLK_DMA_EB>; + clock-names = "enable"; + #dma-cells = <1>; + dma-channels = <32>; + }; + + /* AGCP DMA controller */ + dma-controller@41580000 { + compatible = "sprd,sc9860-dma"; + reg = <0x41580000 0x4000>; + clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, + <&agcp_gate CLK_AGCP_AP_ASHB_EB>; + clock-names = "enable", "ashb_eb"; + #dma-cells = <1>; + dma-channels = <32>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/dma/st,stm32-dma.yaml b/sys/contrib/device-tree/Bindings/dma/st,stm32-dma.yaml index 329847ef096a..ff935a0068ec 100644 --- a/sys/contrib/device-tree/Bindings/dma/st,stm32-dma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/st,stm32-dma.yaml @@ -82,6 +82,10 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/dma/st,stm32-dmamux.yaml b/sys/contrib/device-tree/Bindings/dma/st,stm32-dmamux.yaml index e722fbcd8a5f..ddf82bf1e71a 100644 --- a/sys/contrib/device-tree/Bindings/dma/st,stm32-dmamux.yaml +++ b/sys/contrib/device-tree/Bindings/dma/st,stm32-dmamux.yaml @@ -28,6 +28,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/dma/stericsson,dma40.yaml b/sys/contrib/device-tree/Bindings/dma/stericsson,dma40.yaml index 1e5752b19a49..7b94d24d5ef4 100644 --- a/sys/contrib/device-tree/Bindings/dma/stericsson,dma40.yaml +++ b/sys/contrib/device-tree/Bindings/dma/stericsson,dma40.yaml @@ -148,7 +148,7 @@ properties: memcpy-channels: $ref: /schemas/types.yaml#/definitions/uint32-array description: Array of u32 elements indicating which channels on the DMA - engine are elegible for memcpy transfers + engine are eligible for memcpy transfers required: - "#dma-cells" diff --git a/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dma.yaml b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dma.yaml new file mode 100644 index 000000000000..11a289f1d505 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dma.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DMA Controller + +description: | + The STM32 DMA is a general-purpose direct memory access controller capable of + supporting 8 independent DMA channels. Each channel can have up to 8 requests. + DMA clients connected to the STM32 DMA controller must use the format + described in the dma.txt file, using a four-cell specifier for each + channel: a phandle to the DMA controller plus the following four integer cells: + 1. The channel id + 2. The request line number + 3. A 32bit mask specifying the DMA channel configuration which are device + dependent: + -bit 9: Peripheral Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 10: Memory Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 15: Peripheral Increment Offset Size + 0x0: offset size is linked to the peripheral bus width + 0x1: offset size is fixed to 4 (32-bit alignment) + -bit 16-17: Priority level + 0x0: low + 0x1: medium + 0x2: high + 0x3: very high + 4. A 32bit bitfield value specifying DMA features which are device dependent: + -bit 0-1: DMA FIFO threshold selection + 0x0: 1/4 full FIFO + 0x1: 1/2 full FIFO + 0x2: 3/4 full FIFO + 0x3: full FIFO + -bit 2: DMA direct mode + 0x0: FIFO mode with threshold selectable with bit 0-1 + 0x1: Direct mode: each DMA request immediately initiates a transfer + from/to the memory, FIFO is bypassed. + -bit 4: alternative DMA request/acknowledge protocol + 0x0: Use standard DMA ACK management, where ACK signal is maintained + up to the removal of request and transfer completion + 0x1: Use alternative DMA ACK management, where ACK de-assertion does + not wait for the de-assertion of the REQuest, ACK is only managed + by transfer completion. This must only be used on channels + managing transfers for STM32 USART/UART. + + +maintainers: + - Amelie Delaunay <amelie.delaunay@foss.st.com> + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + "#dma-cells": + const: 4 + + compatible: + const: st,stm32-dma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 8 + description: Should contain all of the per-channel DMA + interrupts in ascending order with respect to the + DMA channel index. + + resets: + maxItems: 1 + + st,mem2mem: + $ref: /schemas/types.yaml#/definitions/flag + description: if defined, it indicates that the controller + supports memory-to-memory transfer + + access-controllers: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&clk_hclk>; + #dma-cells = <4>; + st,mem2mem; + resets = <&rcc 150>; + dma-requests = <8>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dma3.yaml b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dma3.yaml new file mode 100644 index 000000000000..7fdc44b2e646 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dma3.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DMA3 Controller + +description: | + The STM32 DMA3 is a direct memory access controller with different features + depending on its hardware configuration. + It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High + Performance). + Its hardware configuration registers allow to dynamically expose its features. + + GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA. + GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA. + + Bindings are generic for these 3 STM32 DMA3 configurations. + + DMA clients connected to the STM32 DMA3 controller must use the format + described in "#dma-cells" property description below, using a three-cell + specifier for each channel. + +maintainers: + - Amelie Delaunay <amelie.delaunay@foss.st.com> + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: st,stm32mp25-dma3 + + reg: + maxItems: 1 + + interrupts: + minItems: 4 + maxItems: 16 + description: + Should contain all of the per-channel DMA interrupts in ascending order + with respect to the DMA channel index. + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#dma-cells": + const: 3 + description: | + Specifies the number of cells needed to provide DMA controller specific + information. + The first cell is the request line number. + The second cell is a 32-bit mask specifying the DMA channel requirements: + -bit 0-1: The priority level + 0x0: low priority, low weight + 0x1: low priority, mid weight + 0x2: low priority, high weight + 0x3: high priority + -bit 4-7: The FIFO requirement for queuing source/destination transfers + 0x0: no FIFO requirement/any channel can fit + 0x2: FIFO of 8 bytes (2^2+1) + 0x4: FIFO of 32 bytes (2^4+1) + 0x6: FIFO of 128 bytes (2^6+1) + 0x7: FIFO of 256 bytes (2^7+1) + The third cell is a 32-bit mask specifying the DMA transfer requirements: + -bit 0: The source incrementing burst + 0x0: fixed burst + 0x1: contiguously incremented burst + -bit 1: The source allocated port + 0x0: port 0 is allocated to the source transfer + 0x1: port 1 is allocated to the source transfer + -bit 4: The destination incrementing burst + 0x0: fixed burst + 0x1: contiguously incremented burst + -bit 5: The destination allocated port + 0x0: port 0 is allocated to the destination transfer + 0x1: port 1 is allocated to the destination transfer + -bit 8: The type of hardware request + 0x0: burst + 0x1: block + -bit 9: The control mode + 0x0: DMA controller control mode + 0x1: peripheral control mode + -bit 12-13: The transfer complete event mode + 0x0: at block level, transfer complete event is generated at the end + of a block + 0x2: at LLI level, the transfer complete event is generated at the end + of the LLI transfer + including the update of the LLI if any + 0x3: at channel level, the transfer complete event is generated at the + end of the last LLI + +required: + - compatible + - reg + - interrupts + - clocks + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/st,stm32mp25-rcc.h> + dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_HPDMA1>; + #dma-cells = <3>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dmamux.yaml b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dmamux.yaml new file mode 100644 index 000000000000..f26c914a3a9a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-dmamux.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dmamux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DMA MUX (DMA request router) + +maintainers: + - Amelie Delaunay <amelie.delaunay@foss.st.com> + +allOf: + - $ref: /schemas/dma/dma-router.yaml# + +properties: + "#dma-cells": + const: 3 + + compatible: + const: st,stm32h7-dmamux + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + access-controllers: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - dma-masters + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x3c>; + #dma-cells = <3>; + dma-requests = <128>; + dma-channels = <16>; + dma-masters = <&dma1>, <&dma2>; + clocks = <&timer_clk>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-mdma.yaml b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-mdma.yaml new file mode 100644 index 000000000000..45fe91db11db --- /dev/null +++ b/sys/contrib/device-tree/Bindings/dma/stm32/st,stm32-mdma.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 MDMA Controller + +description: | + The STM32 MDMA is a general-purpose direct memory access controller capable of + supporting 64 independent DMA channels with 256 HW requests. + DMA clients connected to the STM32 MDMA controller must use the format + described in the dma.txt file, using a five-cell specifier for each channel: + a phandle to the MDMA controller plus the following five integer cells: + 1. The request line number + 2. The priority level + 0x0: Low + 0x1: Medium + 0x2: High + 0x3: Very high + 3. A 32bit mask specifying the DMA channel configuration + -bit 0-1: Source increment mode + 0x0: Source address pointer is fixed + 0x2: Source address pointer is incremented after each data transfer + 0x3: Source address pointer is decremented after each data transfer + -bit 2-3: Destination increment mode + 0x0: Destination address pointer is fixed + 0x2: Destination address pointer is incremented after each data transfer + 0x3: Destination address pointer is decremented after each data transfer + -bit 8-9: Source increment offset size + 0x0: byte (8bit) + 0x1: half-word (16bit) + 0x2: word (32bit) + 0x3: double-word (64bit) + -bit 10-11: Destination increment offset size + 0x0: byte (8bit) + 0x1: half-word (16bit) + 0x2: word (32bit) + 0x3: double-word (64bit) + -bit 25-18: The number of bytes to be transferred in a single transfer + (min = 1 byte, max = 128 bytes) + -bit 29:28: Trigger Mode + 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) + 0x1: Each MDMA request triggers a block transfer (max 64K bytes) + 0x2: Each MDMA request triggers a repeated block transfer + 0x3: Each MDMA request triggers a linked list transfer + 4. A 32bit value specifying the register to be used to acknowledge the request + if no HW ack signal is used by the MDMA client + 5. A 32bit mask specifying the value to be written to acknowledge the request + if no HW ack signal is used by the MDMA client + +maintainers: + - Amelie Delaunay <amelie.delaunay@foss.st.com> + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + "#dma-cells": + const: 5 + + compatible: + const: st,stm32h7-mdma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + st,ahb-addr-masks: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Array of u32 mask to list memory devices addressed via AHB bus. + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + dma-controller@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&timer_clk>; + resets = <&rcc 992>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + st,ahb-addr-masks = <0x20000000>, <0x00000000>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/dma/ti-dma-crossbar.txt b/sys/contrib/device-tree/Bindings/dma/ti-dma-crossbar.txt index 47e477cce6d2..1f9831540c97 100644 --- a/sys/contrib/device-tree/Bindings/dma/ti-dma-crossbar.txt +++ b/sys/contrib/device-tree/Bindings/dma/ti-dma-crossbar.txt @@ -20,7 +20,7 @@ Optional properties: memcpy channels in eDMA. Notes: -When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request +When requesting channel via ti,dra7-dma-crossbar, the DMA client must request the DMA event number as crossbar ID (input to the DMA crossbar). For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients: diff --git a/sys/contrib/device-tree/Bindings/dma/ti/k3-bcdma.yaml b/sys/contrib/device-tree/Bindings/dma/ti/k3-bcdma.yaml index 4ca300a42a99..27b8e1636560 100644 --- a/sys/contrib/device-tree/Bindings/dma/ti/k3-bcdma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/ti/k3-bcdma.yaml @@ -37,11 +37,11 @@ properties: reg: minItems: 3 - maxItems: 5 + maxItems: 9 reg-names: minItems: 3 - maxItems: 5 + maxItems: 9 "#dma-cells": const: 3 @@ -141,7 +141,10 @@ allOf: ti,sci-rm-range-tchan: false reg: - maxItems: 3 + items: + - description: BCDMA Control /Status Registers region + - description: RX Channel Realtime Registers region + - description: Ring Realtime Registers region reg-names: items: @@ -161,14 +164,29 @@ allOf: properties: reg: minItems: 5 + items: + - description: BCDMA Control /Status Registers region + - description: Block Copy Channel Realtime Registers region + - description: RX Channel Realtime Registers region + - description: TX Channel Realtime Registers region + - description: Ring Realtime Registers region + - description: Ring Configuration Registers region + - description: TX Channel Configuration Registers region + - description: RX Channel Configuration Registers region + - description: Block Copy Channel Configuration Registers region reg-names: + minItems: 5 items: - const: gcfg - const: bchanrt - const: rchanrt - const: tchanrt - const: ringrt + - const: ring + - const: tchan + - const: rchan + - const: bchan required: - ti,sci-rm-range-bchan @@ -184,7 +202,11 @@ allOf: ti,sci-rm-range-bchan: false reg: - maxItems: 4 + items: + - description: BCDMA Control /Status Registers region + - description: RX Channel Realtime Registers region + - description: TX Channel Realtime Registers region + - description: Ring Realtime Registers region reg-names: items: @@ -220,8 +242,13 @@ examples: <0x0 0x4c000000 0x0 0x20000>, <0x0 0x4a820000 0x0 0x20000>, <0x0 0x4aa40000 0x0 0x20000>, - <0x0 0x4bc00000 0x0 0x100000>; - reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + <0x0 0x4bc00000 0x0 0x100000>, + <0x0 0x48600000 0x0 0x8000>, + <0x0 0x484a4000 0x0 0x2000>, + <0x0 0x484c2000 0x0 0x2000>, + <0x0 0x48420000 0x0 0x2000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "bchan"; msi-parent = <&inta_main_dmss>; #dma-cells = <3>; diff --git a/sys/contrib/device-tree/Bindings/dma/ti/k3-pktdma.yaml b/sys/contrib/device-tree/Bindings/dma/ti/k3-pktdma.yaml index a69f62f854d8..11e064c02994 100644 --- a/sys/contrib/device-tree/Bindings/dma/ti/k3-pktdma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/ti/k3-pktdma.yaml @@ -45,14 +45,28 @@ properties: The second cell is the ASEL value for the channel reg: - maxItems: 4 + minItems: 4 + items: + - description: Packet DMA Control /Status Registers region + - description: RX Channel Realtime Registers region + - description: TX Channel Realtime Registers region + - description: Ring Realtime Registers region + - description: Ring Configuration Registers region + - description: TX Configuration Registers region + - description: RX Configuration Registers region + - description: RX Flow Configuration Registers region reg-names: + minItems: 4 items: - const: gcfg - const: rchanrt - const: tchanrt - const: ringrt + - const: ring + - const: tchan + - const: rchan + - const: rflow msi-parent: true @@ -136,8 +150,14 @@ examples: reg = <0x0 0x485c0000 0x0 0x100>, <0x0 0x4a800000 0x0 0x20000>, <0x0 0x4aa00000 0x0 0x40000>, - <0x0 0x4b800000 0x0 0x400000>; - reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + <0x0 0x4b800000 0x0 0x400000>, + <0x0 0x485e0000 0x0 0x20000>, + <0x0 0x484a0000 0x0 0x4000>, + <0x0 0x484c0000 0x0 0x2000>, + <0x0 0x48430000 0x0 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", + "ring", "tchan", "rchan", "rflow"; + msi-parent = <&inta_main_dmss>; #dma-cells = <2>; diff --git a/sys/contrib/device-tree/Bindings/dma/ti/k3-udma.yaml b/sys/contrib/device-tree/Bindings/dma/ti/k3-udma.yaml index 22f6c5e2f7f4..b18cf2bfdb5b 100644 --- a/sys/contrib/device-tree/Bindings/dma/ti/k3-udma.yaml +++ b/sys/contrib/device-tree/Bindings/dma/ti/k3-udma.yaml @@ -69,13 +69,24 @@ properties: - ti,j721e-navss-mcu-udmap reg: - maxItems: 3 + minItems: 3 + items: + - description: UDMA-P Control /Status Registers region + - description: RX Channel Realtime Registers region + - description: TX Channel Realtime Registers region + - description: TX Configuration Registers region + - description: RX Configuration Registers region + - description: RX Flow Configuration Registers region reg-names: + minItems: 3 items: - const: gcfg - const: rchanrt - const: tchanrt + - const: tchan + - const: rchan + - const: rflow msi-parent: true @@ -158,8 +169,11 @@ examples: compatible = "ti,am654-navss-main-udmap"; reg = <0x0 0x31150000 0x0 0x100>, <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x35000000 0x0 0x100000>, + <0x0 0x30b00000 0x0 0x20000>, + <0x0 0x30c00000 0x0 0x8000>, + <0x0 0x30d00000 0x0 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow"; #dma-cells = <1>; ti,ringacc = <&ringacc>; diff --git a/sys/contrib/device-tree/Bindings/dma/xilinx/xilinx_dma.txt b/sys/contrib/device-tree/Bindings/dma/xilinx/xilinx_dma.txt index d1700a5c36bf..590d1948f202 100644 --- a/sys/contrib/device-tree/Bindings/dma/xilinx/xilinx_dma.txt +++ b/sys/contrib/device-tree/Bindings/dma/xilinx/xilinx_dma.txt @@ -49,6 +49,12 @@ Optional properties for AXI DMA and MCDMA: register as configured in h/w. Takes values {8...26}. If the property is missing or invalid then the default value 23 is used. This is the maximum value that is supported by all IP versions. + +Optional properties for AXI DMA: +- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. +- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from + 0-255. Setting this value to zero disables the delay timer interrupt. + 1 timeout interval = 125 * clock period of SG clock. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: diff --git a/sys/contrib/device-tree/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/sys/contrib/device-tree/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index 23ada8f87526..ac3198953b8e 100644 --- a/sys/contrib/device-tree/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/sys/contrib/device-tree/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -13,6 +13,8 @@ description: | maintainers: - Michael Tretter <m.tretter@pengutronix.de> + - Harini Katakam <harini.katakam@amd.com> + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> allOf: - $ref: ../dma-controller.yaml# @@ -22,7 +24,9 @@ properties: const: 1 compatible: - const: xlnx,zynqmp-dma-1.0 + enum: + - amd,versal2-dma-1.0 + - xlnx,zynqmp-dma-1.0 reg: description: memory map for gdma/adma module access @@ -65,6 +69,7 @@ required: - interrupts - clocks - clock-names + - xlnx,bus-width additionalProperties: false |