diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/gpio/fairchild,74hc595.yaml')
| -rw-r--r-- | sys/contrib/device-tree/Bindings/gpio/fairchild,74hc595.yaml | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/sys/contrib/device-tree/Bindings/gpio/fairchild,74hc595.yaml b/sys/contrib/device-tree/Bindings/gpio/fairchild,74hc595.yaml index e8bc9f018edb..ab35bcf98101 100644 --- a/sys/contrib/device-tree/Bindings/gpio/fairchild,74hc595.yaml +++ b/sys/contrib/device-tree/Bindings/gpio/fairchild,74hc595.yaml @@ -6,6 +6,23 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic 8-bit shift register +description: | + NOTE: These chips nominally don't have a chip select pin. They do however + have a rising-edge triggered latch clock (or storage register clock) pin, + which behaves like an active-low chip select. + + After the bits are shifted into the shift register, CS# is driven high, which + the 74HC595 sees as a rising edge on the latch clock that results in a + transfer of the bits from the shift register to the storage register and thus + to the output pins. + _ _ _ _ + shift clock ____| |_| |_..._| |_| |_________ + + latch clock * trigger + ___ ________ + chip select# |___________________| + + maintainers: - Maxime Ripard <mripard@kernel.org> @@ -54,15 +71,15 @@ unevaluatedProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - - gpio5: gpio5@0 { - compatible = "fairchild,74hc595"; - reg = <0>; - gpio-controller; - #gpio-cells = <2>; - registers-number = <4>; - spi-max-frequency = <100000>; - }; + #address-cells = <1>; + #size-cells = <0>; + + gpio5@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; }; |