diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/media')
113 files changed, 6528 insertions, 429 deletions
diff --git a/sys/contrib/device-tree/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml b/sys/contrib/device-tree/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml index a4f06bbdfe49..8ba5177ac631 100644 --- a/sys/contrib/device-tree/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml +++ b/sys/contrib/device-tree/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml# diff --git a/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-csi.yaml b/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-csi.yaml index b3d6db922693..1aa5775ba2bc 100644 --- a/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-csi.yaml @@ -110,7 +110,7 @@ examples: reg = <0x01cb4000 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI>; clock-names = "bus", "mod", diff --git a/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-isp.yaml b/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-isp.yaml index a61a76bb611c..3ea4a4290f23 100644 --- a/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-isp.yaml +++ b/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-isp.yaml @@ -79,7 +79,7 @@ examples: reg = <0x01cb8000 0x1000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI>; clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; diff --git a/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml index 54e15ab8a7f5..627b28e94354 100644 --- a/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +++ b/sys/contrib/device-tree/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml @@ -103,7 +103,7 @@ examples: reg = <0x01cb1000 0x1000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>; + <&ccu CLK_CSI_SCLK>; clock-names = "bus", "mod"; resets = <&ccu RST_BUS_CSI>; diff --git a/sys/contrib/device-tree/Bindings/media/amlogic,c3-isp.yaml b/sys/contrib/device-tree/Bindings/media/amlogic,c3-isp.yaml new file mode 100644 index 000000000000..123bf462f098 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/amlogic,c3-isp.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-isp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 Image Signal Processing Unit + +maintainers: + - Keke Li <keke.li@amlogic.com> + +description: + Amlogic ISP is the RAW image processing module + and supports three channels image output. + +properties: + compatible: + enum: + - amlogic,c3-isp + + reg: + maxItems: 1 + + reg-names: + items: + - const: isp + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: isp0 + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: input port node. + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + #include <dt-bindings/power/amlogic,c3-pwrc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp: isp@ff000000 { + compatible = "amlogic,c3-isp"; + reg = <0x0 0xff000000 0x0 0xf000>; + reg-names = "isp"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>; + + port { + c3_isp_in: endpoint { + remote-endpoint = <&c3_adap_out>; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/amlogic,c3-mipi-adapter.yaml b/sys/contrib/device-tree/Bindings/media/amlogic,c3-mipi-adapter.yaml new file mode 100644 index 000000000000..ba43bc6709a0 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/amlogic,c3-mipi-adapter.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-mipi-adapter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 MIPI adapter receiver + +maintainers: + - Keke Li <keke.li@amlogic.com> + +description: + MIPI adapter is used to convert the MIPI CSI-2 data + into an ISP supported data format. + +properties: + compatible: + enum: + - amlogic,c3-mipi-adapter + + reg: + maxItems: 3 + + reg-names: + items: + - const: top + - const: fd + - const: rd + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: isp0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: input port node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: output port node. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + #include <dt-bindings/power/amlogic,c3-pwrc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + adap: adap@ff010000 { + compatible = "amlogic,c3-mipi-adapter"; + reg = <0x0 0xff010000 0x0 0x100>, + <0x0 0xff01b000 0x0 0x100>, + <0x0 0xff01d000 0x0 0x200>; + reg-names = "top", "fd", "rd"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_adap_in: endpoint { + remote-endpoint = <&c3_mipi_csi_out>; + }; + }; + + port@1 { + reg = <1>; + c3_adap_out: endpoint { + remote-endpoint = <&c3_isp_in>; + }; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/amlogic,c3-mipi-csi2.yaml b/sys/contrib/device-tree/Bindings/media/amlogic,c3-mipi-csi2.yaml new file mode 100644 index 000000000000..b0129beab0c3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/amlogic,c3-mipi-csi2.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/amlogic,c3-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 MIPI CSI-2 receiver + +maintainers: + - Keke Li <keke.li@amlogic.com> + +description: + MIPI CSI-2 receiver contains CSI-2 RX PHY and host controller. + It receives the MIPI data from the image sensor and sends MIPI data + to MIPI adapter. + +properties: + compatible: + enum: + - amlogic,c3-mipi-csi2 + + reg: + maxItems: 3 + + reg-names: + items: + - const: aphy + - const: dphy + - const: host + + power-domains: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vapb + - const: phy0 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port node, connected to sensor. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: output port node + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h> + #include <dt-bindings/power/amlogic,c3-pwrc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi: csi@ff018000 { + compatible = "amlogic,c3-mipi-csi2"; + reg = <0x0 0xff018000 0x0 0x400>, + <0x0 0xff019000 0x0 0x300>, + <0x0 0xff01a000 0x0 0x100>; + reg-names = "aphy", "dphy", "host"; + power-domains = <&pwrc PWRC_C3_MIPI_ISP_WRAP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + clock-names = "vapb", "phy0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + assigned-clock-rates = <0>, <200000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_mipi_csi_in: endpoint { + remote-endpoint = <&imx290_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + c3_mipi_csi_out: endpoint { + remote-endpoint = <&c3_adap_in>; + }; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/amlogic,meson-ir-tx.yaml b/sys/contrib/device-tree/Bindings/media/amlogic,meson-ir-tx.yaml index 377acce93423..6da8a6aded23 100644 --- a/sys/contrib/device-tree/Bindings/media/amlogic,meson-ir-tx.yaml +++ b/sys/contrib/device-tree/Bindings/media/amlogic,meson-ir-tx.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml# diff --git a/sys/contrib/device-tree/Bindings/media/amphion,vpu.yaml b/sys/contrib/device-tree/Bindings/media/amphion,vpu.yaml index 9801de3ed84e..5a920d9e78c7 100644 --- a/sys/contrib/device-tree/Bindings/media/amphion,vpu.yaml +++ b/sys/contrib/device-tree/Bindings/media/amphion,vpu.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/amphion,vpu.yaml# diff --git a/sys/contrib/device-tree/Bindings/media/aspeed,video-engine.yaml b/sys/contrib/device-tree/Bindings/media/aspeed,video-engine.yaml new file mode 100644 index 000000000000..682bba20778c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/aspeed,video-engine.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/aspeed,video-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED Video Engine + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The Video Engine (VE) embedded in the ASPEED SOCs can be configured to + capture and compress video data from digital or analog sources. + +properties: + compatible: + enum: + - aspeed,ast2400-video-engine + - aspeed,ast2500-video-engine + - aspeed,ast2600-video-engine + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vclk + - const: eclk + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + description: | + Phandle to the reserved memory nodes to be associated with the + VE. VE will acquires memory space for 3 purposes: + 1. JPEG header + 2. Compressed result + 3. Temporary transformed image data + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/cdns,csi2rx.yaml b/sys/contrib/device-tree/Bindings/media/cdns,csi2rx.yaml index 2008a47c0580..6ed9a5621064 100644 --- a/sys/contrib/device-tree/Bindings/media/cdns,csi2rx.yaml +++ b/sys/contrib/device-tree/Bindings/media/cdns,csi2rx.yaml @@ -24,6 +24,14 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: error_irq + - const: irq + clocks: items: - description: CSI2Rx system clock diff --git a/sys/contrib/device-tree/Bindings/media/cec/nvidia,tegra114-cec.yaml b/sys/contrib/device-tree/Bindings/media/cec/nvidia,tegra114-cec.yaml index a6b73498bc21..4b46aa755ccd 100644 --- a/sys/contrib/device-tree/Bindings/media/cec/nvidia,tegra114-cec.yaml +++ b/sys/contrib/device-tree/Bindings/media/cec/nvidia,tegra114-cec.yaml @@ -14,10 +14,16 @@ allOf: properties: compatible: - enum: - - nvidia,tegra114-cec - - nvidia,tegra124-cec - - nvidia,tegra210-cec + oneOf: + - enum: + - nvidia,tegra114-cec + - nvidia,tegra124-cec + - nvidia,tegra210-cec + - items: + - enum: + - nvidia,tegra186-cec + - nvidia,tegra194-cec + - const: nvidia,tegra210-cec clocks: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/fsl,imx-capture-subsystem.yaml b/sys/contrib/device-tree/Bindings/media/fsl,imx-capture-subsystem.yaml new file mode 100644 index 000000000000..25e65a344a0a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/fsl,imx-capture-subsystem.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx-capture-subsystem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Media Video Device + +description: + This is the media controller node for video capture support. It is a + virtual device that lists the camera serial interface nodes that the + media device will control + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx-capture-subsystem + + ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles pointing to camera + sensor interface ports of IPU devices. + +required: + - compatible + +additionalProperties: false + +examples: + - | + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu1_csi0>, <&ipu1_csi1>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/fsl,imx6-mipi-csi2.yaml b/sys/contrib/device-tree/Bindings/media/fsl,imx6-mipi-csi2.yaml new file mode 100644 index 000000000000..65255f576f26 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/fsl,imx6-mipi-csi2.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6-mipi-csi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPI CSI-2 Receiver core in the i.MX SoC + +description: + This is the device node for the MIPI CSI-2 Receiver core in the i.MX + SoC. This is a Synopsys Designware MIPI CSI-2 host controller core + combined with a D-PHY core mixed into the same register block. In + addition this device consists of an i.MX-specific "CSI2IPU gasket" + glue logic, also controlled from the same register block. The CSI2IPU + gasket demultiplexes the four virtual channel streams from the host + controller's 32-bit output image bus onto four 16-bit parallel busses + to the i.MX IPU CSIs. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx6-mipi-csi2 + + reg: + maxItems: 1 + + clocks: + items: + - description: hsi_tx (the D-PHY clock) + - description: video_27m (D-PHY PLL reference clock) + - description: eim_podf; + + clock-names: + items: + - const: dphy + - const: ref + - const: pix + + interrupts: + items: + - description: CSI-2 ERR1 irq + - description: CSI-2 ERR2 irq + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port node, single endpoint describing the CSI-2 transmitter. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + const: 0 + + data-lanes: + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + +patternProperties: + '^port@[1-4]$': + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + ports 1 through 4 are output ports connecting with parallel bus sink + endpoint nodes and correspond to the four MIPI CSI-2 virtual channel + outputs. + + properties: + endpoint@0: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + endpoint@1: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + + mipi@21dc000 { + compatible = "fsl,imx6-mipi-csi2"; + reg = <0x021dc000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, + <&clks IMX6QDL_CLK_VIDEO_27M>, + <&clks IMX6QDL_CLK_EIM_PODF>; + clock-names = "dphy", "ref", "pix"; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/fsl,imx6q-vdoa.yaml b/sys/contrib/device-tree/Bindings/media/fsl,imx6q-vdoa.yaml new file mode 100644 index 000000000000..511ac0d67a7f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/fsl,imx6q-vdoa.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6q-vdoa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Video Data Order Adapter + +description: + The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose + is to reorder video data from the macroblock tiled order produced by the CODA + 960 VPU to the conventional raster-scan order for scanout. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: "fsl,imx6q-vdoa" + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx6qdl-clock.h> + + vdoa@21e4000 { + compatible = "fsl,imx6q-vdoa"; + reg = <0x021e4000 0x4000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_VDOA>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/fsl,imx6ull-pxp.yaml b/sys/contrib/device-tree/Bindings/media/fsl,imx6ull-pxp.yaml index 84a5e894ace4..3f47744459aa 100644 --- a/sys/contrib/device-tree/Bindings/media/fsl,imx6ull-pxp.yaml +++ b/sys/contrib/device-tree/Bindings/media/fsl,imx6ull-pxp.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml# diff --git a/sys/contrib/device-tree/Bindings/media/fsl,imx8qm-isi.yaml b/sys/contrib/device-tree/Bindings/media/fsl,imx8qm-isi.yaml new file mode 100644 index 000000000000..93f527e223af --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/fsl,imx8qm-isi.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8QM Image Sensing Interface + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Image Sensing Interface (ISI) combines image processing pipelines with + DMA engines to process and capture frames originating from a variety of + sources. The inputs to the ISI go through Pixel Link interfaces, and their + number and nature is SoC-dependent. They cover both capture interfaces (MIPI + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. + +properties: + compatible: + enum: + - fsl,imx8qm-isi + + reg: + maxItems: 1 + + clocks: + maxItems: 8 + + clock-names: + items: + - const: per0 + - const: per1 + - const: per2 + - const: per3 + - const: per4 + - const: per5 + - const: per6 + - const: per7 + + interrupts: + maxItems: 8 + + power-domains: + maxItems: 8 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI CSI-2 RX 0 + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI CSI-2 RX 1 + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI RX + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx8-clock.h> + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + image-controller@58100000 { + compatible = "fsl,imx8qm-isi"; + reg = <0x58100000 0x80000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, + <&pdma1_lpcg IMX_LPCG_CLK_0>, + <&pdma2_lpcg IMX_LPCG_CLK_0>, + <&pdma3_lpcg IMX_LPCG_CLK_0>, + <&pdma4_lpcg IMX_LPCG_CLK_0>, + <&pdma5_lpcg IMX_LPCG_CLK_0>, + <&pdma6_lpcg IMX_LPCG_CLK_0>, + <&pdma7_lpcg IMX_LPCG_CLK_0>; + clock-names = "per0", "per1", "per2", "per3", + "per4", "per5", "per6", "per7"; + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>, + <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>, + <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>, + <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&mipi_csi0_out>; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/fsl,imx8qxp-isi.yaml b/sys/contrib/device-tree/Bindings/media/fsl,imx8qxp-isi.yaml new file mode 100644 index 000000000000..bb41996bd2e3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/fsl,imx8qxp-isi.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8QXP Image Sensing Interface + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Image Sensing Interface (ISI) combines image processing pipelines with + DMA engines to process and capture frames originating from a variety of + sources. The inputs to the ISI go through Pixel Link interfaces, and their + number and nature is SoC-dependent. They cover both capture interfaces (MIPI + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. + +properties: + compatible: + enum: + - fsl,imx8qxp-isi + + reg: + maxItems: 1 + + clocks: + maxItems: 6 + + clock-names: + items: + - const: per0 + - const: per1 + - const: per2 + - const: per3 + - const: per4 + - const: per5 + + interrupts: + maxItems: 6 + + power-domains: + maxItems: 6 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MIPI CSI-2 RX 0 + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: CSI-2 Parallel RX + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx8-clock.h> + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + image-controller@58100000 { + compatible = "fsl,imx8qxp-isi"; + reg = <0x58100000 0x60000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, + <&pdma1_lpcg IMX_LPCG_CLK_0>, + <&pdma2_lpcg IMX_LPCG_CLK_0>, + <&pdma3_lpcg IMX_LPCG_CLK_0>, + <&pdma4_lpcg IMX_LPCG_CLK_0>, + <&pdma5_lpcg IMX_LPCG_CLK_0>; + clock-names = "per0", "per1", "per2", "per3", "per4", "per5"; + power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>, + <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>, + <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&mipi_csi0_out>; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adi,ad5820.yaml b/sys/contrib/device-tree/Bindings/media/i2c/adi,ad5820.yaml new file mode 100644 index 000000000000..0c8f24f692ca --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/adi,ad5820.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,ad5820.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5820 autofocus coil + +maintainers: + - Pavel Machek <pavel@ucw.cz> + +description: + The AD5820 is a current sink driver designed for precise control of + voice coil motors (VCMs) in camera autofocus systems. + +properties: + compatible: + enum: + - adi,ad5820 + - adi,ad5821 + - adi,ad5823 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + description: + GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is active low, + a high level on the pin enables the device. + + VANA-supply: + description: supply of voltage for VANA pin + +required: + - compatible + - reg + - VANA-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + coil@c { + compatible = "adi,ad5820"; + reg = <0x0c>; + + enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>; + VANA-supply = <&vaux4>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adi,adp1653.txt b/sys/contrib/device-tree/Bindings/media/i2c/adi,adp1653.txt new file mode 100644 index 000000000000..4cce0de40ee9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/adi,adp1653.txt @@ -0,0 +1,38 @@ +* Analog Devices ADP1653 flash LED driver + +Required Properties: + + - compatible: Must contain "adi,adp1653" + + - reg: I2C slave address + + - enable-gpios: Specifier of the GPIO connected to EN pin + +There are two LED outputs available - flash and indicator. One LED is +represented by one child node, nodes need to be named "flash" and "indicator". + +Required properties of the LED child node: +- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + +Required properties of the flash LED child node: + +- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt +- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt +- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt + +Example: + + adp1653: led-controller@30 { + compatible = "adi,adp1653"; + reg = <0x30>; + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ + + flash { + flash-timeout-us = <500000>; + flash-max-microamp = <320000>; + led-max-microamp = <50000>; + }; + indicator { + led-max-microamp = <17500>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7180.yaml b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7180.yaml new file mode 100644 index 000000000000..dee8ce7cb7ba --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7180.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,adv7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV7180 analog video decoder family + +maintainers: + - Lars-Peter Clausen <lars@metafoo.de> + +description: + The adv7180 family devices are used to capture analog video to different + digital interfaces like MIPI CSI-2 or parallel video. + +properties: + compatible: + items: + - enum: + - adi,adv7180 + - adi,adv7180cp + - adi,adv7180st + - adi,adv7182 + - adi,adv7280 + - adi,adv7280-m + - adi,adv7281 + - adi,adv7281-m + - adi,adv7281-ma + - adi,adv7282 + - adi,adv7282-m + + reg: + maxItems: 1 + + powerdown-gpios: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + adv,force-bt656-4: + deprecated: true + description: + Indicates that the output is a BT.656-4 compatible stream. + type: boolean + + adi,force-bt656-4: + description: + Indicates that the output is a BT.656-4 compatible stream. + type: boolean + + interrupts: + items: + - description: The GPIO connected to the INTRQ pin. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + ports: true + +additionalProperties: false + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + enum: + - adi,adv7180 + - adi,adv7182 + - adi,adv7280 + - adi,adv7280-m + - adi,adv7281 + - adi,adv7281-m + - adi,adv7281-ma + - adi,adv7282 + - adi,adv7282-m + then: + required: + - port + + - if: + properties: + compatible: + contains: + const: adi,adv7180cp + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + patternProperties: + "^port@[0-2]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + required: + - port@3 + + required: + - ports + + - if: + properties: + compatible: + contains: + const: adi,adv7180st + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + required: + - port@6 + + required: + - ports + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; + + }; + + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + remote-endpoint = <&vin4_in>; + }; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7343.txt b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7343.txt new file mode 100644 index 000000000000..5653bc2428b8 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7343.txt @@ -0,0 +1,48 @@ +* Analog Devices adv7343 video encoder + +The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP +package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite +(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard +definition (SD), enhanced definition (ED), or high definition (HD) video +formats. + +Required Properties : +- compatible: Must be "adi,adv7343" + +Optional Properties : +- adi,power-mode-sleep-mode: on enable the current consumption is reduced to + micro ampere level. All DACs and the internal PLL + circuit are disabled. +- adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows + internal PLL 1 circuit to be powered down and the + oversampling to be switched off. +- ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6, + 0 = OFF and 1 = ON, Default value when this + property is not specified is <0 0 0 0 0 0>. +- ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF + and 1 = ON, Default value when this property is + not specified is <0 0>. + +Example: + +i2c0@1c22000 { + ... + ... + + adv7343@2a { + compatible = "adi,adv7343"; + reg = <0x2a>; + + port { + adv7343_1: endpoint { + adi,power-mode-sleep-mode; + adi,power-mode-pll-ctrl; + /* Use DAC1..3, DAC6 */ + adi,dac-enable = <1 1 1 0 0 1>; + /* Use SD DAC output 1 */ + adi,sd-dac-enable = <1 0>; + }; + }; + }; + ... +}; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adi,adv748x.yaml b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv748x.yaml new file mode 100644 index 000000000000..254987350321 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv748x.yaml @@ -0,0 +1,212 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,adv748x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV748X video decoder with HDMI receiver + +maintainers: + - Kieran Bingham <kieran.bingham@ideasonboard.com> + - Niklas Söderlund <niklas.soderlund@ragnatech.se> + +description: + The ADV7481 and ADV7482 are multi format video decoders with an integrated + HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB + from three input sources HDMI, analog and TTL. + +properties: + compatible: + items: + - enum: + - adi,adv7481 + - adi,adv7482 + + reg: + minItems: 1 + maxItems: 12 + description: + The ADV748x has up to twelve 256-byte maps that can be accessed via the + main I2C ports. Each map has it own I2C address and acts as a standard + slave device on the I2C bus. The main address is mandatory, others are + optional and remain at default values if not specified. + + reg-names: + minItems: 1 + items: + - const: main + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] + + interrupts: true + + interrupt-names: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + "^port@[0-7]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port nodes for analog inputs AIN[0-7]. + + properties: + port@8: + $ref: /schemas/graph.yaml#/properties/port + description: Input port node for HDMI. + + port@9: + $ref: /schemas/graph.yaml#/properties/port + description: Input port node for TTL. + + port@a: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output port node, single endpoint describing the CSI-2 transmitter TXA. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@b: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output port node, single endpoint describing the CSI-2 transmitter TXB. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + maxItems: 1 + + required: + - clock-lanes + - data-lanes + +allOf: + - if: + properties: + compatible: + contains: + const: adi,adv7481 + then: + properties: + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + maxItems: 3 + items: + enum: [ intrq1, intrq2, intrq3 ] + else: + properties: + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: [ intrq1, intrq2 ] + +additionalProperties: false + +required: + - compatible + - reg + - ports + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb"; + + interrupt-parent = <&gpio6>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>, <31 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_in>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + + port@b { + reg = <11>; + + adv7482_txb: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&csi20_in>; + }; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7604.yaml b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7604.yaml new file mode 100644 index 000000000000..6c403003cdda --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/adi,adv7604.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/adi,adv7604.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver + +maintainers: + - Hans Verkuil <hverkuil-cisco@xs4all.nl> + +description: + The ADV7604 and ADV7610/11/12 are multiformat video decoders with + an integrated HDMI receiver. The ADV7604 has four multiplexed HDMI inputs + and one analog input, and the ADV7610/11 have one HDMI input and no analog + input. The ADV7612 is similar to the ADV7610/11 but has 2 HDMI inputs. + + These device tree bindings support the ADV7610/11/12 only at the moment. + +properties: + compatible: + items: + - enum: + - adi,adv7610 + - adi,adv7611 + - adi,adv7612 + + reg: + minItems: 1 + maxItems: 13 + + reg-names: + minItems: 1 + items: + - const: main + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ] + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + hpd-gpios: + minItems: 1 + description: + References to the GPIOs that control the HDMI hot-plug detection pins, + one per HDMI input. The active flag indicates the GPIO level that + enables hot-plug detection. + + default-input: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Select which input is selected after reset. + + ports: true + +required: + - compatible + - reg + - ports + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: adi,adv7611 + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + required: + - port@1 + + - if: + properties: + compatible: + contains: + const: adi,adv7612 + then: + properties: + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Output port + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/properties/port + description: Input port + + required: + - port@2 + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_receiver@4c { + compatible = "adi,adv7611"; + /* + * The edid page will be accessible @ 0x66 on the I2C bus. All + * other maps will retain their default addresses. + */ + reg = <0x4c>, <0x66>; + reg-names = "main", "edid"; + + reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>; + hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + hdmi_in: endpoint { + remote-endpoint = <&ccdc_in>; + }; + }; + }; + + + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/adv7180.yaml b/sys/contrib/device-tree/Bindings/media/i2c/adv7180.yaml index c8d887eee3bb..9ee1483775f6 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/adv7180.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/adv7180.yaml @@ -39,10 +39,20 @@ properties: maxItems: 1 adv,force-bt656-4: + deprecated: true description: Indicates that the output is a BT.656-4 compatible stream. type: boolean + adi,force-bt656-4: + description: + Indicates that the output is a BT.656-4 compatible stream. + type: boolean + + interrupts: + items: + - description: The GPIO connected to the INTRQ pin. + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false diff --git a/sys/contrib/device-tree/Bindings/media/i2c/aptina,mt9v032.txt b/sys/contrib/device-tree/Bindings/media/i2c/aptina,mt9v032.txt new file mode 100644 index 000000000000..100f0ae43269 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/aptina,mt9v032.txt @@ -0,0 +1,41 @@ +* Aptina 1/3-Inch WVGA CMOS Digital Image Sensor + +The Aptina MT9V032 is a 1/3-inch CMOS active pixel digital image sensor with +an active array size of 752H x 480V. It is programmable through a simple +two-wire serial interface. + +Required Properties: + +- compatible: value should be either one among the following + (a) "aptina,mt9v022" for MT9V022 color sensor + (b) "aptina,mt9v022m" for MT9V022 monochrome sensor + (c) "aptina,mt9v024" for MT9V024 color sensor + (d) "aptina,mt9v024m" for MT9V024 monochrome sensor + (e) "aptina,mt9v032" for MT9V032 color sensor + (f) "aptina,mt9v032m" for MT9V032 monochrome sensor + (g) "aptina,mt9v034" for MT9V034 color sensor + (h) "aptina,mt9v034m" for MT9V034 monochrome sensor + +Optional Properties: + +- link-frequencies: List of allowed link frequencies in Hz. Each frequency is + expressed as a 64-bit big-endian integer. +- reset-gpios: GPIO handle which is connected to the reset pin of the chip. +- standby-gpios: GPIO handle which is connected to the standby pin of the chip. + +For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + mt9v032@5c { + compatible = "aptina,mt9v032"; + reg = <0x5c>; + + port { + mt9v032_out: endpoint { + link-frequencies = /bits/ 64 + <13000000 26600000 27000000>; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/hynix,hi846.yaml b/sys/contrib/device-tree/Bindings/media/i2c/hynix,hi846.yaml index 60f19e1152b3..1a57f2aa1982 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/hynix,hi846.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/hynix,hi846.yaml @@ -28,12 +28,6 @@ properties: items: - description: Reference to the mclk clock. - assigned-clocks: - maxItems: 1 - - assigned-clock-rates: - maxItems: 1 - reset-gpios: description: Reference to the GPIO connected to the RESETB pin. Active low. maxItems: 1 @@ -82,8 +76,6 @@ required: - compatible - reg - clocks - - assigned-clocks - - assigned-clock-rates - vddio-supply - vdda-supply - vddd-supply @@ -105,8 +97,6 @@ examples: pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi1>; clocks = <&clk 0>; - assigned-clocks = <&clk 0>; - assigned-clock-rates = <25000000>; vdda-supply = <®_camera_vdda>; vddd-supply = <®_camera_vddd>; vddio-supply = <®_camera_vddio>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/maxim,max2175.txt b/sys/contrib/device-tree/Bindings/media/i2c/maxim,max2175.txt new file mode 100644 index 000000000000..02b4e9cd7b1b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/maxim,max2175.txt @@ -0,0 +1,59 @@ +Maxim Integrated MAX2175 RF to Bits tuner +----------------------------------------- + +The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with +RF to Bits® front-end designed for software-defined radio solutions. + +Required properties: +-------------------- +- compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner. +- clocks: clock specifier. +- port: child port node corresponding to the I2S output, in accordance with + the video interface bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The port + node must contain at least one endpoint. + +Optional properties: +-------------------- +- maxim,master : phandle to the master tuner if it is a slave. This + is used to define two tuners in diversity mode + (1 master, 1 slave). By default each tuner is an + individual master. +- maxim,refout-load : load capacitance value (in picofarads) on reference + output drive level. The possible load values are: + 0 (default - refout disabled) + 10 + 20 + 30 + 40 + 60 + 70 +- maxim,am-hiz-filter : empty property indicates the AM Hi-Z filter is used + in this hardware for AM antenna input. + +Example: +-------- + +Board specific DTS file + +/* Fixed XTAL clock node */ +maxim_xtal: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <36864000>; +}; + +/* A tuner device instance under i2c bus */ +max2175_0: tuner@60 { + compatible = "maxim,max2175"; + reg = <0x60>; + clocks = <&maxim_xtal>; + maxim,refout-load = <10>; + + port { + max2175_0_ep: endpoint { + remote-endpoint = <&slave_rx_device>; + }; + }; + +}; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/maxim,max96712.yaml b/sys/contrib/device-tree/Bindings/media/i2c/maxim,max96712.yaml index 6c72e77b927c..26f85151afbd 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/maxim,max96712.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/maxim,max96712.yaml @@ -25,7 +25,10 @@ description: | properties: compatible: - const: maxim,max96712 + items: + - enum: + - maxim,max96712 + - maxim,max96724 reg: description: I2C device address diff --git a/sys/contrib/device-tree/Bindings/media/i2c/micron,mt9m111.txt b/sys/contrib/device-tree/Bindings/media/i2c/micron,mt9m111.txt new file mode 100644 index 000000000000..d0bed6fa901a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/micron,mt9m111.txt @@ -0,0 +1,37 @@ +Micron 1.3Mp CMOS Digital Image Sensor + +The Micron MT9M111 is a CMOS active pixel digital image sensor with an active +array size of 1280H x 1024V. It is programmable through a simple two-wire serial +interface. + +Required Properties: +- compatible: value should be "micron,mt9m111" +- clocks: reference to the master clock. +- clock-names: shall be "mclk". + +The device node must contain one 'port' child node with one 'endpoint' child +sub-node for its digital output video port, in accordance with the video +interface bindings defined in: +Documentation/devicetree/bindings/media/video-interfaces.txt + +Optional endpoint properties: +- pclk-sample: For information see ../video-interfaces.txt. The value is set to + 0 if it isn't specified. + +Example: + + i2c_master { + mt9m111@5d { + compatible = "micron,mt9m111"; + reg = <0x5d>; + clocks = <&mclk>; + clock-names = "mclk"; + + port { + mt9m111_1: endpoint { + remote-endpoint = <&pxa_camera>; + pclk-sample = <1>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/mipi-ccs.yaml b/sys/contrib/device-tree/Bindings/media/i2c/mipi-ccs.yaml index f8ace8cbccdb..bc664a016396 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/mipi-ccs.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/mipi-ccs.yaml @@ -23,6 +23,9 @@ description: More detailed documentation can be found in Documentation/devicetree/bindings/media/video-interfaces.txt . +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + properties: compatible: oneOf: @@ -58,16 +61,10 @@ properties: documentation. maxItems: 1 - flash-leds: - description: Flash LED phandles. See ../video-interfaces.txt for details. - - lens-focus: - description: Lens focus controller phandles. See ../video-interfaces.txt - for details. + flash-leds: true + lens-focus: true rotation: - description: Rotation of the sensor. See ../video-interfaces.txt for - details. enum: [ 0, 180 ] port: diff --git a/sys/contrib/device-tree/Bindings/media/i2c/nxp,tda1997x.txt b/sys/contrib/device-tree/Bindings/media/i2c/nxp,tda1997x.txt new file mode 100644 index 000000000000..e76167999d76 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/nxp,tda1997x.txt @@ -0,0 +1,178 @@ +Device-Tree bindings for the NXP TDA1997x HDMI receiver + +The TDA19971/73 are HDMI video receivers. + +The TDA19971 Video port output pins can be used as follows: + - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4] + - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4] + - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4] + - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2] + - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0] + - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles) + - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles) + - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) + +The TDA19973 Video port output pins can be used as follows: + - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0] + - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0] + - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0] + - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) + +The Video port output pins are mapped via 4-bit 'pin groups' allowing +for a variety of connection possibilities including swapping pin order within +pin groups. The video_portcfg device-tree property consists of register mapping +pairs which map a chip-specific VP output register to a 4-bit pin group. If +the pin group needs to be bit-swapped you can use the *_S pin-group defines. + +Required Properties: + - compatible : + - "nxp,tda19971" for the TDA19971 + - "nxp,tda19973" for the TDA19973 + - reg : I2C slave address + - interrupts : The interrupt number + - DOVDD-supply : Digital I/O supply + - DVDD-supply : Digital Core supply + - AVDD-supply : Analog supply + - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups. + +Optional Properties: + - nxp,audout-format : DAI bus format: "i2s" or "spdif". + - nxp,audout-width : width of audio output data bus (1-4). + - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used). + - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec + mclk. + +The port node shall contain one endpoint child node for its digital +output video port, in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Optional Endpoint Properties: + The following three properties are defined in video-interfaces.txt and + are valid for the output parallel bus endpoint: + - hsync-active: Horizontal synchronization polarity. Defaults to active high. + - vsync-active: Vertical synchronization polarity. Defaults to active high. + - data-active: Data polarity. Defaults to active high. + +Examples: + - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422 + 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same pixclk cycle. + */ + nxp,vidout-portcfg = + /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; + - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 + 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same pixclk cycle. + */ + nxp,vidout-portcfg = + /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; + - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 + 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over + * 2 pixclk cycles. + */ + nxp,vidout-portcfg = + /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >, + /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >, + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m001.txt b/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m001.txt new file mode 100644 index 000000000000..c920552b03ef --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m001.txt @@ -0,0 +1,38 @@ +MT9M001: 1/2-Inch Megapixel Digital Image Sensor + +The MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital +image sensor. It is programmable through I2C interface. + +Required Properties: + +- compatible: shall be "onnn,mt9m001". +- clocks: reference to the master clock into sensor + +Optional Properties: + +- reset-gpios: GPIO handle which is connected to the reset pin of the chip. + Active low. +- standby-gpios: GPIO handle which is connected to the standby pin of the chip. + Active high. + +The device node must contain one 'port' child node with one 'endpoint' child +sub-node for its digital output video port, in accordance with the video +interface bindings defined in: +Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + + &i2c1 { + camera-sensor@5d { + compatible = "onnn,mt9m001"; + reg = <0x5d>; + reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + standby-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + clocks = <&camera_clk>; + port { + mt9m001_out: endpoint { + remote-endpoint = <&vcap_in>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m114.yaml b/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m114.yaml index f6b87892068a..a89f740214f7 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m114.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/onnn,mt9m114.yaml @@ -70,6 +70,15 @@ properties: - bus-type - link-frequencies + slew-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Slew rate ot the output pads DOUT[7:0], LINE_VALID, FRAME_VALID and + PIXCLK. Higher values imply steeper voltage-flanks on the pads. + minimum: 0 + maximum: 7 + default: 7 + required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov02e10.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov02e10.yaml new file mode 100644 index 000000000000..03d476bcf805 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov02e10.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov02e10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV02E10 CMOS Sensor + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: | + The Omnivision OV02E10 and OV02C10 sensors are 2 megapixel, CMOS image sensors which support: + - Automatic black level calibration (ABLC) + - Programmable controls for frame rate, mirror and flip, binning, cropping + and windowing + - OVO2C10 + - 10 bit RAW Bayer 1920x1080 60 fps 2-lane @ 800 Mbps/lane + - 10 bit RAW Bayer 1920x1080 60 fps 1-lane @ 1500 Mbps/lane + - 10 bit RAW Bayer 1280x720 60 fps cropped 1-lane @ 960 Mbps/lane + - 10 bit RGB/BW 640x480 60 fps bin2 or skip2 1-lane @ 800 Mbps/lane + - 10 bit RGB/BW 480x270 60 fps bin4 or skip4 1-lane @ 800 Mbps/lane + - OV02E10 + - 10 bit RAW Bayer 1920x1088 60 fps 2-lane @ 720 Mbps/lane + - 10 bit RAW Bayer 1280x1080 60 fps 2-lane @ 720 Mbps/lane + - 10 bit Quad Bayer 960x540 60 fps 2-lane 360 Mbps/lane + - 8 bit Quad Bayer 480x270 1/3/5/10 fps sub2 288 Mbps/lane + - 8 bit Quad Bayer 232x132 1/3/5/10 fps sub4 144 Mbps/lane + - Dynamic defect pixel cancellation + - Standard SCCB command interface + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - ovti,ov02c10 + - ovti,ov02e10 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + avdd-supply: + description: Analogue circuit voltage supply. + + dovdd-supply: + description: I/O circuit voltage supply. + + dvdd-supply: + description: Digital circuit voltage supply. + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + additionalProperties: false + + properties: + data-lanes: + items: + - const: 1 + - const: 2 + link-frequencies: true + remote-endpoint: true + + required: + - data-lanes + - link-frequencies + - remote-endpoint + +required: + - compatible + - reg + - clocks + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov02e10: camera@10 { + compatible = "ovti,ov02e10"; + reg = <0x10>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov02e10_clk>; + + assigned-clocks = <&ov02e10_clk>; + assigned-clock-parents = <&ov02e10_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02e10_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + + ov02c10: camera@36 { + compatible = "ovti,ov02c10"; + reg = <0x36>; + + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov02c10_clk>; + + assigned-clocks = <&ov02c10_clk>; + assigned-clock-parents = <&ov02c10_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov02c10_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov08x40.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov08x40.yaml new file mode 100644 index 000000000000..552efdf8934f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov08x40.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2024 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov08x40.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV08X40 CMOS Sensor + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: | + The Omnivision OV08X40 is a 9.2 megapixel, CMOS image sensor which supports: + - Automatic black level calibration (ABLC) + - Programmable controls for frame rate, mirror and flip, binning, cropping + and windowing + - Output formats 10-bit 4C RGB RAW, 10-bit Bayer RAW + - 4-lane MIPI D-PHY TX @ 1 Gbps per lane + - 2-lane MPIP D-PHY TX @ 2 Gbps per lane + - Dynamic defect pixel cancellation + - Standard SCCB command interface + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,ov08x40 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + avdd-supply: + description: Analogue circuit voltage supply. + + dovdd-supply: + description: I/O circuit voltage supply. + + dvdd-supply: + description: Digital circuit voltage supply. + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + additionalProperties: false + + properties: + data-lanes: + oneOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + link-frequencies: true + remote-endpoint: true + + required: + - data-lanes + - link-frequencies + - remote-endpoint + +required: + - compatible + - reg + - clocks + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov08x40: camera@36 { + compatible = "ovti,ov08x40"; + reg = <0x36>; + + reset-gpios = <&tlmm 111 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_rgb_defaultt>; + + clocks = <&ov08x40_clk>; + + assigned-clocks = <&ov08x40_clk>; + assigned-clock-parents = <&ov08x40_clk_parent>; + assigned-clock-rates = <19200000>; + + avdd-supply = <&vreg_l7b_2p8>; + dvdd-supply = <&vreg_l7b_1p8>; + dovdd-supply = <&vreg_l3m_1p8>; + + port { + ov08x40_ep: endpoint { + remote-endpoint = <&csiphy4_ep>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <400000000>; + }; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov2640.txt b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov2640.txt new file mode 100644 index 000000000000..989ce6cb6ac3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov2640.txt @@ -0,0 +1,41 @@ +* Omnivision OV2640 CMOS sensor + +The Omnivision OV2640 sensor supports multiple resolutions output, such as +CIF, SVGA, UXGA. It also can support the YUV422/420, RGB565/555 or raw RGB +output formats. + +Required Properties: +- compatible: should be "ovti,ov2640" +- clocks: reference to the xvclk input clock. +- clock-names: should be "xvclk". + +Optional Properties: +- resetb-gpios: reference to the GPIO connected to the resetb pin, if any. +- pwdn-gpios: reference to the GPIO connected to the pwdn pin, if any. + +The device node must contain one 'port' child node for its digital output +video port, in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + i2c1: i2c@f0018000 { + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 11 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xvclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov2659.txt b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov2659.txt new file mode 100644 index 000000000000..92989a619f29 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov2659.txt @@ -0,0 +1,47 @@ +* OV2659 1/5-Inch 2Mp SOC Camera + +The Omnivision OV2659 is a 1/5-inch SOC camera, with an active array size of +1632H x 1212V. It is programmable through a SCCB. The OV2659 sensor supports +multiple resolutions output, such as UXGA, SVGA, 720p. It also can support +YUV422, RGB565/555 or raw RGB output formats. + +Required Properties: +- compatible: Must be "ovti,ov2659" +- reg: I2C slave address +- clocks: reference to the xvclk input clock. +- clock-names: should be "xvclk". +- link-frequencies: target pixel clock frequency. + +Optional Properties: +- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. + Active high with internal pull down resistor. +- reset-gpios: reference to the GPIO connected to the resetb pin, if any. + Active low with internal pull up resistor. + +For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + i2c0@1c22000 { + ... + ... + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&clk_ov2659 0>; + clock-names = "xvclk"; + + powerdown-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + port { + ov2659_0: endpoint { + remote-endpoint = <&vpfe_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; + ... + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov5648.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov5648.yaml index 1f497679168c..8028c8b107c4 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov5648.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov5648.yaml @@ -20,12 +20,6 @@ properties: items: - description: XVCLK Clock - assigned-clocks: - maxItems: 1 - - assigned-clock-rates: - maxItems: 1 - dvdd-supply: description: Digital Domain Power Supply @@ -68,8 +62,6 @@ required: - compatible - reg - clocks - - assigned-clocks - - assigned-clock-rates - dvdd-supply - dovdd-supply - port @@ -93,9 +85,6 @@ examples: avdd-supply = <&ov5648_avdd>; dovdd-supply = <&ov5648_dovdd>; clocks = <&ov5648_xvclk 0>; - assigned-clocks = <&ov5648_xvclk 0>; - assigned-clock-rates = <24000000>; - ov5648_out: port { ov5648_out_mipi_csi2: endpoint { diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov7670.txt b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov7670.txt new file mode 100644 index 000000000000..2c972a56f3cb --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov7670.txt @@ -0,0 +1,55 @@ +* Omnivision OV7670 CMOS sensor + +The Omnivision OV7670 sensor supports multiple resolutions output, such as +CIF, SVGA, UXGA. It also can support the YUV422/420, RGB565/555 or raw RGB +output formats. + +Required Properties: +- compatible: should be "ovti,ov7670" +- clocks: reference to the xclk input clock. +- clock-names: should be "xclk". + +Required Endpoint Properties: +- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. +- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. + +Optional Properties: +- reset-gpios: reference to the GPIO connected to the resetb pin, if any. + Active is low. +- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. + Active is high. +- ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output + signal during horizontal blankings. + +The device node must contain one 'port' child node with one 'endpoint' child +sub-node for its digital output video port, in accordance with the video +interface bindings defined in: +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + i2c1: i2c@f0018000 { + ov7670: camera@21 { + compatible = "ovti,ov7670"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + reset-gpios = <&pioE 11 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; + + ov7670,pclk-hb-disable; + + port { + ov7670_0: endpoint { + hsync-active = <0>; + vsync-active = <0>; + + remote-endpoint = <&isi_0>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov7740.txt b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov7740.txt new file mode 100644 index 000000000000..af781c3a5f0e --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov7740.txt @@ -0,0 +1,47 @@ +* Omnivision OV7740 CMOS image sensor + +The Omnivision OV7740 image sensor supports multiple output image +size, such as VGA, and QVGA, CIF and any size smaller. It also +supports the RAW RGB and YUV output formats. + +The common video interfaces bindings (see video-interfaces.txt) should +be used to specify link to the image data receiver. The OV7740 device +node should contain one 'port' child node with an 'endpoint' subnode. + +Required Properties: +- compatible: "ovti,ov7740". +- reg: I2C slave address of the sensor. +- clocks: Reference to the xvclk input clock. +- clock-names: "xvclk". + +Optional Properties: +- reset-gpios: Rreference to the GPIO connected to the reset_b pin, + if any. Active low with pull-ip resistor. +- powerdown-gpios: Reference to the GPIO connected to the pwdn pin, + if any. Active high with pull-down resistor. + +Endpoint node mandatory properties: +- remote-endpoint: A phandle to the bus receiver's endpoint node. + +Example: + + i2c1: i2c@fc028000 { + ov7740: camera@21 { + compatible = "ovti,ov7740"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sensor_power &pinctrl_sensor_reset>; + clocks = <&isc>; + clock-names = "xvclk"; + assigned-clocks = <&isc>; + assigned-clock-rates = <24000000>; + reset-gpios = <&pioA 43 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&pioA 44 GPIO_ACTIVE_HIGH>; + + port { + ov7740_0: endpoint { + remote-endpoint = <&isc_0>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8858.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8858.yaml index a65f921ec0fd..491f2931e6bc 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8858.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8858.yaml @@ -15,6 +15,8 @@ description: | controlled through an I2C-compatible SCCB bus. The sensor transmits images on a MIPI CSI-2 output interface with up to 4 data lanes. +$ref: /schemas/media/video-interface-devices.yaml# + properties: compatible: const: ovti,ov8858 @@ -69,7 +71,7 @@ required: - clocks - port -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8865.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8865.yaml index 8a70e23ba6ab..320b9aacbb8b 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8865.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov8865.yaml @@ -20,12 +20,6 @@ properties: items: - description: EXTCLK Clock - assigned-clocks: - maxItems: 1 - - assigned-clock-rates: - maxItems: 1 - dvdd-supply: description: Digital Domain Power Supply @@ -68,8 +62,6 @@ required: - compatible - reg - clocks - - assigned-clocks - - assigned-clock-rates - dvdd-supply - avdd-supply - dovdd-supply @@ -94,8 +86,6 @@ examples: pinctrl-0 = <&csi_mclk_pin>; clocks = <&ccu CLK_CSI_MCLK>; - assigned-clocks = <&ccu CLK_CSI_MCLK>; - assigned-clock-rates = <24000000>; avdd-supply = <®_ov8865_avdd>; dovdd-supply = <®_ov8865_dovdd>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9282.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9282.yaml index 79a7658f6d05..401c8613f840 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9282.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9282.yaml @@ -27,10 +27,6 @@ properties: description: I2C address maxItems: 1 - assigned-clocks: true - assigned-clock-parents: true - assigned-clock-rates: true - clocks: description: Clock frequency from 6 to 27MHz maxItems: 1 @@ -87,10 +83,6 @@ examples: reg = <0x60>; clocks = <&ov9282_clk>; - assigned-clocks = <&ov9282_clk>; - assigned-clock-parents = <&ov9282_clk_parent>; - assigned-clock-rates = <24000000>; - port { ov9282: endpoint { remote-endpoint = <&cam>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9650.txt b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9650.txt new file mode 100644 index 000000000000..506dfc52872a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ovti,ov9650.txt @@ -0,0 +1,36 @@ +* Omnivision OV9650/OV9652 CMOS sensor + +Required Properties: +- compatible: shall be one of + "ovti,ov9650" + "ovti,ov9652" +- clocks: reference to the xvclk input clock. + +Optional Properties: +- reset-gpios: reference to the GPIO connected to the resetb pin, if any. + Active is high. +- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. + Active is high. + +The device node shall contain one 'port' child node with one child 'endpoint' +subnode for its digital output video port, in accordance with the video +interface bindings defined in Documentation/devicetree/bindings/media/ +video-interfaces.txt. + +Example: + +&i2c0 { + ov9650: camera@30 { + compatible = "ovti,ov9650"; + reg = <0x30>; + reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_HIGH>; + clocks = <&xclk>; + + port { + ov9650_0: endpoint { + remote-endpoint = <&vcap1_in0>; + }; + }; + }; +}; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx214.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx214.yaml index 0162eec8ca99..aea99ebf8e9e 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx214.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx214.yaml @@ -33,20 +33,21 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz. + deprecated: true enable-gpios: description: GPIO descriptor for the enable pin. maxItems: 1 - vdddo-supply: - description: Chip digital IO regulator (1.8V). - vdda-supply: description: Chip analog regulator (2.7V). vddd-supply: description: Chip digital core regulator (1.12V). + vdddo-supply: + description: Chip digital IO regulator (1.8V). + flash-leds: true lens-focus: true @@ -84,11 +85,10 @@ required: - compatible - reg - clocks - - clock-frequency - enable-gpios - - vdddo-supply - vdda-supply - vddd-supply + - vdddo-supply - port unevaluatedProperties: false @@ -104,22 +104,25 @@ examples: camera-sensor@1a { compatible = "sony,imx214"; reg = <0x1a>; - vdddo-supply = <&pm8994_lvs1>; - vddd-supply = <&camera_vddd_1v12>; + + clocks = <&camera_clk>; + assigned-clocks = <&camera_clk>; + assigned-clock-rates = <24000000>; + + enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + vdda-supply = <&pm8994_l17>; + vddd-supply = <&camera_vddd_1v12>; + vdddo-supply = <&pm8994_lvs1>; + lens-focus = <&ad5820>; - enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; - clocks = <&camera_clk>; - clock-frequency = <24000000>; port { imx214_ep: endpoint { data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <480000000>; + link-frequencies = /bits/ 64 <600000000>; remote-endpoint = <&csiphy0_ep>; }; }; }; }; - -... diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx219.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx219.yaml new file mode 100644 index 000000000000..38c3759bcd9f --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx219.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx219.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor + +maintainers: + - Dave Stevenson <dave.stevenson@raspberrypi.com> + +description: |- + The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor + with an active array size of 3280H x 2464V. It is programmable through + I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet. + Image data is sent through MIPI CSI-2, which is configured as either 2 or + 4 data lanes. + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: sony,imx219 + + reg: + description: I2C device address + maxItems: 1 + + clocks: + maxItems: 1 + + VDIG-supply: + description: + Digital I/O voltage supply, 1.8 volts + + VANA-supply: + description: + Analog voltage supply, 2.8 volts + + VDDL-supply: + description: + Digital core voltage supply, 1.2 volts + + reset-gpios: + maxItems: 1 + description: |- + Reference to the GPIO connected to the xclr pin, if any. + Must be released (set high) after all supplies are applied. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: |- + The sensor supports either two-lane, or four-lane operation. + If this property is omitted four-lane operation is assumed. + For two-lane operation the property must be set to <1 2>. + items: + - const: 1 + - const: 2 + + clock-noncontinuous: true + link-frequencies: true + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - VANA-supply + - VDIG-supply + - VDDL-supply + - port + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + VANA-supply = <&imx219_vana>; /* 2.8v */ + VDIG-supply = <&imx219_vdig>; /* 1.8v */ + VDDL-supply = <&imx219_vddl>; /* 1.2v */ + + port { + imx219_0: endpoint { + remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx258.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx258.yaml index c978abc0cdb3..421b935b52bc 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx258.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx258.yaml @@ -18,16 +18,14 @@ description: |- The camera module does not expose the model through registers, so the exact model needs to be specified. +$ref: /schemas/media/video-interface-devices.yaml# + properties: compatible: enum: - sony,imx258 - sony,imx258-pdaf - assigned-clocks: true - assigned-clock-parents: true - assigned-clock-rates: true - clocks: description: Clock frequency from 6 to 27 MHz. @@ -85,7 +83,7 @@ required: - reg - port -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -125,9 +123,6 @@ examples: reg = <0x6c>; clocks = <&imx258_clk>; - assigned-clocks = <&imx258_clk>; - assigned-clock-rates = <19200000>; - port { endpoint { remote-endpoint = <&csi1_ep>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx290.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx290.yaml index bf05ca48601a..990acf89af8f 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx290.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx290.yaml @@ -33,6 +33,8 @@ properties: - sony,imx290lqr # Colour - sony,imx290llr # Monochrome - sony,imx327lqr # Colour + - sony,imx462lqr # Colour + - sony,imx462llr # Monochrome - const: sony,imx290 deprecated: true @@ -134,7 +136,7 @@ examples: port { imx290_ep: endpoint { data-lanes = <1 2 3 4>; - link-frequencies = /bits/ 64 <445500000>; + link-frequencies = /bits/ 64 <222750000 148500000>; remote-endpoint = <&csiphy0_ep>; }; }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx334.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx334.yaml index bce57b22f7b6..3842e5130463 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx334.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx334.yaml @@ -24,10 +24,6 @@ properties: description: I2C address maxItems: 1 - assigned-clocks: true - assigned-clock-parents: true - assigned-clock-rates: true - clocks: description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz maxItems: 1 @@ -74,10 +70,6 @@ examples: reg = <0x1a>; clocks = <&imx334_clk>; - assigned-clocks = <&imx334_clk>; - assigned-clock-parents = <&imx334_clk_parent>; - assigned-clock-rates = <24000000>; - port { imx334: endpoint { remote-endpoint = <&cam>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx335.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx335.yaml index 77bf3a4ee89d..80f879b6bd01 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx335.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx335.yaml @@ -24,10 +24,6 @@ properties: description: I2C address maxItems: 1 - assigned-clocks: true - assigned-clock-parents: true - assigned-clock-rates: true - clocks: description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz maxItems: 1 @@ -86,10 +82,6 @@ examples: reg = <0x1a>; clocks = <&imx335_clk>; - assigned-clocks = <&imx335_clk>; - assigned-clock-parents = <&imx335_clk_parent>; - assigned-clock-rates = <24000000>; - avdd-supply = <&camera_vdda_2v9>; ovdd-supply = <&camera_vddo_1v8>; dvdd-supply = <&camera_vddd_1v2>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx412.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx412.yaml index d9b7815650fd..5447ab0768a6 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx412.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx412.yaml @@ -26,10 +26,6 @@ properties: description: I2C address maxItems: 1 - assigned-clocks: true - assigned-clock-parents: true - assigned-clock-rates: true - clocks: description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz maxItems: 1 @@ -86,10 +82,6 @@ examples: reg = <0x1a>; clocks = <&imx412_clk>; - assigned-clocks = <&imx412_clk>; - assigned-clock-parents = <&imx412_clk_parent>; - assigned-clock-rates = <24000000>; - port { imx412: endpoint { remote-endpoint = <&cam>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx415.yaml b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx415.yaml index 34962c5c7006..7c11e871dca6 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/sony,imx415.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/sony,imx415.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sony IMX415 CMOS Image Sensor maintainers: - - Michael Riesch <michael.riesch@wolfvision.net> + - Michael Riesch <michael.riesch@collabora.com> description: |- The Sony IMX415 is a diagonal 6.4 mm (Type 1/2.8) CMOS active pixel type diff --git a/sys/contrib/device-tree/Bindings/media/i2c/st,st-mipid02.yaml b/sys/contrib/device-tree/Bindings/media/i2c/st,st-mipid02.yaml index b68141264c0e..4d40e75b4e1e 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/st,st-mipid02.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/st,st-mipid02.yaml @@ -71,7 +71,7 @@ properties: description: Any lane can be inverted or not. minItems: 1 - maxItems: 2 + maxItems: 3 required: - data-lanes diff --git a/sys/contrib/device-tree/Bindings/media/i2c/st,vd55g1.yaml b/sys/contrib/device-tree/Bindings/media/i2c/st,vd55g1.yaml new file mode 100644 index 000000000000..3c071e6fbea6 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/st,vd55g1.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025 STMicroelectronics SA. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,vd55g1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics VD55G1 Global Shutter Image Sensor + +maintainers: + - Benjamin Mugnier <benjamin.mugnier@foss.st.com> + - Sylvain Petinot <sylvain.petinot@foss.st.com> + +description: |- + The STMicroelectronics VD55G1 is a global shutter image sensor with an active + array size of 804H x 704V. It is programmable through I2C interface. The I2C + address is fixed to 0x10. + + Image data is sent through MIPI CSI-2, which is configured as only 1 data + lane. The sensor provides 4 GPIOS that can be used for external LED signal + (synchronized with sensor integration periods). + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: st,vd55g1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcore-supply: + description: Digital core power supply (1.15V) + + vddio-supply: + description: Digital IO power supply (1.8V) + + vana-supply: + description: Analog power supply (2.8V) + + reset-gpios: + description: Sensor reset active low GPIO (XSHUTDOWN) + maxItems: 1 + + st,leds: + description: + List sensor's GPIOs used to control strobe light sources during exposure + time. The numbers identify the sensor pin on which the illumination + system is connected. GPIOs are active-high. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 3 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + items: + - const: 1 + + link-frequencies: + maxItems: 1 + items: + minimum: 125000000 + maximum: 600000000 + + lane-polarities: + minItems: 1 + maxItems: 2 + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - vcore-supply + - vddio-supply + - vana-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@10 { + compatible = "st,vd55g1"; + reg = <0x10>; + + clocks = <&camera_clk_12M>; + + vcore-supply = <&camera_vcore_v1v15>; + vddio-supply = <&camera_vddio_v1v8>; + vana-supply = <&camera_vana_v2v8>; + + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + st,leds = <2>; + + orientation = <2>; + rotation = <0>; + + port { + endpoint { + data-lanes = <1>; + link-frequencies = /bits/ 64 <600000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/st,vd56g3.yaml b/sys/contrib/device-tree/Bindings/media/i2c/st,vd56g3.yaml new file mode 100644 index 000000000000..c6673b8539db --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/st,vd56g3.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2024 STMicroelectronics SA. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,vd56g3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics VD56G3 Global Shutter Image Sensor + +maintainers: + - Benjamin Mugnier <benjamin.mugnier@foss.st.com> + - Sylvain Petinot <sylvain.petinot@foss.st.com> + +description: |- + The STMicroelectronics VD56G3 is a 1.5 M pixel global shutter image sensor + with an active array size of 1124 x 1364 (portrait orientation). It is + programmable through I2C, the address is fixed to 0x10. The sensor output is + available via CSI-2, which is configured as either 1 or 2 data lanes. The + sensor provides 8 GPIOS that can be used for external LED signal + (synchronized with sensor integration periods) + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - st,vd56g3 + - st,vd66gy + description: + Two variants are availables; VD56G3 is a monochrome sensor while VD66GY + is a colour variant. + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcore-supply: + description: Digital core power supply (1.15V) + + vddio-supply: + description: Digital IO power supply (1.8V) + + vana-supply: + description: Analog power supply (2.8V) + + reset-gpios: + description: Sensor reset active low GPIO (XSHUTDOWN) + maxItems: 1 + + st,leds: + description: + List sensor's GPIOs used to control strobe light sources during exposure + time. The numbers identify the sensor pin on which the illumination system + is connected. GPIOs are active-high. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 2 + items: + enum: [1, 2] + + link-frequencies: + maxItems: 1 + items: + enum: [402000000, 750000000] + + lane-polarities: + minItems: 1 + maxItems: 3 + description: Any lane can be inverted or not. + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - vcore-supply + - vddio-supply + - vana-supply + - reset-gpios + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@10 { + compatible = "st,vd56g3"; + reg = <0x10>; + + clocks = <&camera_clk_12M>; + + vcore-supply = <&camera_vcore_v1v15>; + vddio-supply = <&camera_vddio_v1v8>; + vana-supply = <&camera_vana_v2v8>; + + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + st,leds = <6>; + + orientation = <2>; + rotation = <0>; + + port { + endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <402000000>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/thine,thp7312.yaml b/sys/contrib/device-tree/Bindings/media/i2c/thine,thp7312.yaml index 535acf2b88a9..bc339a7374b2 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/thine,thp7312.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/thine,thp7312.yaml @@ -135,8 +135,7 @@ properties: data-lanes: $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes - items: - maxItems: 4 + maxItems: 4 description: This property is for lane reordering between the THP7312 and the imaging sensor that it is connected to. diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub953.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub953.yaml index 2030366994d1..2e129bf573b7 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub953.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub953.yaml @@ -38,6 +38,13 @@ properties: '#clock-cells': const: 0 + reg: + maxItems: 1 + description: + The strap I2C address of the serializer. Can be used by the deserializer + to communicate over back-channel when the forward-channel is not yet + active. + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -81,51 +88,57 @@ examples: - | #include <dt-bindings/gpio/gpio.h> - serializer { - compatible = "ti,ds90ub953-q1"; + link { + #address-cells = <1>; + #size-cells = <0>; + + serializer@18 { + compatible = "ti,ds90ub953-q1"; + reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; + gpio-controller; + #gpio-cells = <2>; - #clock-cells = <0>; + #clock-cells = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; - ub953_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&sensor_out>; + port@0 { + reg = <0>; + ub953_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; }; - }; - port@1 { - reg = <1>; - endpoint { - remote-endpoint = <&deser_fpd_in>; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&deser_fpd_in>; + }; }; }; - }; - i2c { - #address-cells = <1>; - #size-cells = <0>; + i2c { + #address-cells = <1>; + #size-cells = <0>; - sensor@1a { - compatible = "sony,imx274"; - reg = <0x1a>; + sensor@1a { + compatible = "sony,imx274"; + reg = <0x1a>; - reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; + reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>; - clocks = <&serializer>; - clock-names = "inck"; + clocks = <&serializer>; + clock-names = "inck"; - port { - sensor_out: endpoint { - remote-endpoint = <&ub953_in>; + port { + sensor_out: endpoint { + remote-endpoint = <&ub953_in>; + }; }; }; }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub960.yaml b/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub960.yaml index 0b71e6f911a8..4dcbd2b039a5 100644 --- a/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub960.yaml +++ b/sys/contrib/device-tree/Bindings/media/i2c/ti,ds90ub960.yaml @@ -68,6 +68,12 @@ properties: description: The link number maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + i2c-alias: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -107,7 +113,8 @@ properties: maximum: 14 description: Manual EQ level - serializer: + patternProperties: + '^serializer(@[0-9a-f]+)*$': type: object description: FPD-Link Serializer node @@ -115,7 +122,6 @@ properties: - reg - i2c-alias - ti,rx-mode - - serializer ports: $ref: /schemas/graph.yaml#/properties/ports @@ -309,13 +315,17 @@ examples: /* Link 0 has DS90UB953 serializer and IMX274 sensor */ link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; i2c-alias = <0x44>; ti,rx-mode = <3>; - serializer1: serializer { + serializer1: serializer@30 { compatible = "ti,ds90ub953-q1"; + reg = <0x30>; gpio-controller; #gpio-cells = <2>; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ti,ths8200.txt b/sys/contrib/device-tree/Bindings/media/i2c/ti,ths8200.txt new file mode 100644 index 000000000000..285f6ae7dfa9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ti,ths8200.txt @@ -0,0 +1,19 @@ +* Texas Instruments THS8200 video encoder + +The ths8200 device is a digital to analog converter used in DVD players, video +recorders, set-top boxes. + +Required Properties : +- compatible : value must be "ti,ths8200" + +Example: + + i2c0@1c22000 { + ... + ... + ths8200@5c { + compatible = "ti,ths8200"; + reg = <0x5c>; + }; + ... + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp514x.txt b/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp514x.txt new file mode 100644 index 000000000000..46752cc71f2e --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp514x.txt @@ -0,0 +1,44 @@ +* Texas Instruments TVP514x video decoder + +The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip +digital video decoder that digitizes and decodes all popular baseband analog +video formats into digital video component. The tvp514x decoder supports analog- +to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D +conversion and decoding of NTSC, PAL and SECAM composite and S-video into +component YCbCr. + +Required Properties : +- compatible : value should be either one among the following + (a) "ti,tvp5146" for tvp5146 decoder. + (b) "ti,tvp5146m2" for tvp5146m2 decoder. + (c) "ti,tvp5147" for tvp5147 decoder. + (d) "ti,tvp5147m1" for tvp5147m1 decoder. + +- hsync-active: HSYNC Polarity configuration for endpoint. + +- vsync-active: VSYNC Polarity configuration for endpoint. + +- pclk-sample: Clock polarity of the endpoint. + +For further reading on port node refer to Documentation/devicetree/bindings/ +media/video-interfaces.txt. + +Example: + + i2c0@1c22000 { + ... + ... + tvp514x@5c { + compatible = "ti,tvp5146"; + reg = <0x5c>; + + port { + tvp514x_1: endpoint { + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; + ... + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp5150.txt b/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp5150.txt new file mode 100644 index 000000000000..94b908ace53c --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp5150.txt @@ -0,0 +1,157 @@ +* Texas Instruments TVP5150 and TVP5151 video decoders + +The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL +(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV +with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats. + +Required Properties: +==================== +- compatible: Value must be "ti,tvp5150". +- reg: I2C slave address. + +Optional Properties: +==================== +- pdn-gpios: Phandle for the GPIO connected to the PDN pin, if any. +- reset-gpios: Phandle for the GPIO connected to the RESETB pin, if any. + +The device node must contain one 'port' child node per device physical input +and output port, in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes +are numbered as follows + + Name Type Port + -------------------------------------- + AIP1A sink 0 + AIP1B sink 1 + Y-OUT src 2 + +The device node must contain at least one sink port and the src port. Each input +port must be linked to an endpoint defined in [1]. The port/connector layout is +as follows + +tvp-5150 port@0 (AIP1A) + endpoint@0 -----------> Comp0-Con port + endpoint@1 ------+----> Svideo-Con port +tvp-5150 port@1 (AIP1B) | + endpoint@1 ------+ + endpoint@0 -----------> Comp1-Con port +tvp-5150 port@2 + endpoint (video bitstream output at YOUT[0-7] parallel bus) + +Required Endpoint Properties for parallel synchronization on output port: +========================================================================= + +- hsync-active: Active state of the HSYNC signal. Must be <1> (HIGH). +- vsync-active: Active state of the VSYNC signal. Must be <1> (HIGH). +- field-even-active: Field signal level during the even field data + transmission. Must be <0>. + +Note: Do not specify any of these properties if you want to use the embedded + BT.656 synchronization. + +Optional Connector Properties: +============================== + +- sdtv-standards: Set the possible signals to which the hardware tries to lock + instead of using the autodetection mechanism. Please look at + [1] for more information. + +[1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml. + +Example - three input sources: +#include <dt-bindings/display/sdtv-standards.h> + +comp_connector_0 { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = <SDTV_STD_PAL_M>; /* limit to pal-m signals */ + + port { + composite0_to_tvp5150: endpoint { + remote-endpoint = <&tvp5150_to_composite0>; + }; + }; +}; + +comp_connector_1 { + compatible = "composite-video-connector"; + label = "Composite1"; + sdtv-standards = <SDTV_STD_NTSC_M>; /* limit to ntsc-m signals */ + + port { + composite1_to_tvp5150: endpoint { + remote-endpoint = <&tvp5150_to_composite1>; + }; + }; +}; + +svideo_connector { + compatible = "svideo-connector"; + label = "S-Video"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + svideo_luma_to_tvp5150: endpoint@0 { + reg = <0>; + remote-endpoint = <&tvp5150_to_svideo_luma>; + }; + + svideo_chroma_to_tvp5150: endpoint@1 { + reg = <1>; + remote-endpoint = <&tvp5150_to_svideo_chroma>; + }; + }; +}; + +&i2c2 { + tvp5150@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tvp5150_to_composite0: endpoint@0 { + reg = <0>; + remote-endpoint = <&composite0_to_tvp5150>; + }; + + tvp5150_to_svideo_luma: endpoint@1 { + reg = <1>; + remote-endpoint = <&svideo_luma_to_tvp5150>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tvp5150_to_composite1: endpoint@0 { + reg = <0>; + remote-endpoint = <&composite1_to_tvp5150>; + }; + + tvp5150_to_svideo_chroma: endpoint@1 { + reg = <1>; + remote-endpoint = <&svideo_chroma_to_tvp5150>; + }; + }; + + port@2 { + reg = <2>; + + tvp5150_1: endpoint { + remote-endpoint = <&ccdc_ep>; + }; + }; + }; +}; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp7002.txt b/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp7002.txt new file mode 100644 index 000000000000..5f28b5d9abcc --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/ti,tvp7002.txt @@ -0,0 +1,53 @@ +* Texas Instruments TV7002 video decoder + +The TVP7002 device supports digitizing of video and graphics signal in RGB and +YPbPr color space. + +Required Properties : +- compatible : Must be "ti,tvp7002" + +Optional Properties: +- hsync-active: HSYNC Polarity configuration for the bus. Default value when + this property is not specified is <0>. + +- vsync-active: VSYNC Polarity configuration for the bus. Default value when + this property is not specified is <0>. + +- pclk-sample: Clock polarity of the bus. Default value when this property is + not specified is <0>. + +- sync-on-green-active: Active state of Sync-on-green signal property of the + endpoint. + 0 = Normal Operation (Active Low, Default) + 1 = Inverted operation + +- field-even-active: Active-high Field ID output polarity control of the bus. + Under normal operation, the field ID output is set to logic 1 for an odd field + (field 1) and set to logic 0 for an even field (field 0). + 0 = Normal Operation (Active Low, Default) + 1 = FID output polarity inverted + +For further reading of port node refer Documentation/devicetree/bindings/media/ +video-interfaces.txt. + +Example: + + i2c0@1c22000 { + ... + ... + tvp7002@5c { + compatible = "ti,tvp7002"; + reg = <0x5c>; + + port { + tvp7002_1: endpoint { + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + sync-on-green-active = <1>; + field-even-active = <0>; + }; + }; + }; + ... + }; diff --git a/sys/contrib/device-tree/Bindings/media/i2c/toshiba,tc358743.txt b/sys/contrib/device-tree/Bindings/media/i2c/toshiba,tc358743.txt new file mode 100644 index 000000000000..59102edcf01e --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/i2c/toshiba,tc358743.txt @@ -0,0 +1,48 @@ +* Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge + +The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts +a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C. + +Required Properties: + +- compatible: value should be "toshiba,tc358743" +- clocks, clock-names: should contain a phandle link to the reference clock + source, the clock input is named "refclk". + +Optional Properties: + +- reset-gpios: gpio phandle GPIO connected to the reset pin +- interrupts: GPIO connected to the interrupt pin +- data-lanes: should be <1 2 3 4> for four-lane operation, + or <1 2> for two-lane operation +- clock-lanes: should be <0> +- clock-noncontinuous: Presence of this boolean property decides whether the + MIPI CSI-2 clock is continuous or non-continuous. +- link-frequencies: List of allowed link frequencies in Hz. Each frequency is + expressed as a 64-bit big-endian integer. The frequency + is half of the bps per lane due to DDR transmission. + +For further information on the MIPI CSI-2 endpoint node properties, see +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + tc358743@f { + compatible = "toshiba,tc358743"; + reg = <0x0f>; + clocks = <&hdmi_osc>; + clock-names = "refclk"; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + port { + tc358743_out: endpoint { + remote-endpoint = <&mipi_csi2_in>; + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <297000000>; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-fg.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-fg.yaml index 03f31b009085..40fda59fa8a8 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-fg.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-fg.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-fg + oneOf: + - enum: + - mediatek,mt8195-mdp3-fg + - items: + - const: mediatek,mt8188-mdp3-fg + - const: mediatek,mt8195-mdp3-fg reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-hdr.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-hdr.yaml index d4609bba6578..d9f926c20220 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-hdr.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-hdr.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-hdr + oneOf: + - enum: + - mediatek,mt8195-mdp3-hdr + - items: + - const: mediatek,mt8188-mdp3-hdr + - const: mediatek,mt8195-mdp3-hdr reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-rsz.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-rsz.yaml index f5676bec4326..8124c39d73e9 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-rsz.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-rsz.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-rsz - items: - enum: + - mediatek,mt8188-mdp3-rsz - mediatek,mt8195-mdp3-rsz - const: mediatek,mt8183-mdp3-rsz diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-stitch.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-stitch.yaml index d815bea29154..1d8e7e202c42 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-stitch.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-stitch.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-stitch + oneOf: + - enum: + - mediatek,mt8195-mdp3-stitch + - items: + - const: mediatek,mt8188-mdp3-stitch + - const: mediatek,mt8195-mdp3-stitch reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tcc.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tcc.yaml index 14ea556d4f82..6cff7c073ce4 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tcc.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tcc.yaml @@ -17,8 +17,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tcc + oneOf: + - enum: + - mediatek,mt8195-mdp3-tcc + - items: + - const: mediatek,mt8188-mdp3-tcc + - const: mediatek,mt8195-mdp3-tcc reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tdshp.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tdshp.yaml index 8ab7f2d8e148..cdfa27324738 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tdshp.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-tdshp.yaml @@ -16,8 +16,12 @@ description: properties: compatible: - enum: - - mediatek,mt8195-mdp3-tdshp + oneOf: + - enum: + - mediatek,mt8195-mdp3-tdshp + - items: + - const: mediatek,mt8188-mdp3-tdshp + - const: mediatek,mt8195-mdp3-tdshp reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-wrot.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-wrot.yaml index 53a679338402..b6269f4f9fd6 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-wrot.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,mdp3-wrot.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8183-mdp3-wrot - items: - enum: + - mediatek,mt8188-mdp3-wrot - mediatek,mt8195-mdp3-wrot - const: mediatek,mt8183-mdp3-wrot diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-decoder.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-decoder.yaml index b401c67e3ba0..d726d141a434 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-decoder.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-decoder.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml# diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml index b45743d0a9ec..ebc615584f92 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml# @@ -42,10 +41,6 @@ properties: minItems: 1 maxItems: 5 - assigned-clocks: true - - assigned-clock-parents: true - iommus: minItems: 1 maxItems: 32 @@ -79,8 +74,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents allOf: - if: diff --git a/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-subdev-decoder.yaml b/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-subdev-decoder.yaml index a500a585c692..bf8082d87ac0 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -1,56 +1,73 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek Video Decode Accelerator With Multi Hardware +title: MediaTek Video Decode Accelerator With Multi Hardware maintainers: - Yunfei Dong <yunfei.dong@mediatek.com> description: | - Mediatek Video Decode is the video decode hardware present in Mediatek - SoCs which supports high resolution decoding functionalities. Required - parent and child device node. - - About the Decoder Hardware Block Diagram, please check below: - - +------------------------------------------------+-------------------------------------+ - | | | - | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | - | || || | || | - +------------||-------------||-------------------+---------------------||--------------+ - || lat || | core workqueue <parent> - -------------||-------------||-------------------|---------------------||--------------- - ||<------------||----------------HW index---------------->|| <child> - \/ \/ \/ - +-------------------------------------------------------------+ - | enable/disable | - | clk power irq iommu | - | (lat/lat soc/core0/core1) | - +-------------------------------------------------------------+ - - As above, there are parent and child devices, child mean each hardware. The child device - controls the information of each hardware independent which include clk/power/irq. - - There are two workqueues in parent device: lat workqueue and core workqueue. They are used - to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer, - then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode - done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, - writing the result to output buffer, disable hardware when core decode done. These two - hardwares will decode each frame cyclically. - - For the smi common may not the same for each hardware, can't combine all hardware in one node, - or leading to iommu fault when access dram data. - - Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195 - platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and - clock when lat start to work, don't have interrupt. - - mt8195: lat soc HW + lat HW + core HW - mt8192: lat HW + core HW + MediaTek Video Decode Accelerator is the video decoding hardware present in + MediaTek SoCs that supports high-resolution decoding functionalities. + It consists of parent and child nodes. + + The decoder hardware block diagram is shown below: + + +------------------------------------------------+------------------------------+ + | | | + | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer | + | || || | || | + +--------------||-----------||-------------------+-------||---------------------+ + LAT Workqueue | Core Workqueue <parent> + ---------------||-----------||-------------------|-------||---------------------- + ||<----------||---------HW index--------->|| <child> + \/ \/ \/ + +-------------------------------------------------------------+ + | enable/disable | + | clk power irq iommu | + | (lat/lat-soc/core0/core1) | + +-------------------------------------------------------------+ + + The child nodes represent the individual hardware blocks within the decoding + pipeline, such as LAT-SoC, LAT and Core. + Each child node is responsible for managing the dedicated resources of the + hardware, such as clocks, power domains, interrupts and IOMMUs. + + The parent node is a central point of control for the child nodes. + It identifies the specific video decoding pipeline architecture used by the + SoC, manages the shared resources like workqueues and platform data, and + handles V4L2 API calls on behalf of the underlying hardware. + + The parent utilizes two workqueues to manage the decoding process. + 1. LAT Workqueue, for LAT-SoC and LAT decoder: + Its workers take input bitstream and LAT buffer, enable the hardware for + decoding tasks, write the result to LAT buffer, and disable the hardware + after the LAT decoding is done. + 2. Core Workqueue, for Core decoder: + Its workers take LAT buffer and output buffer, enable the hardware for + decoding tasks, write the result to output buffer, and disable the hardware + after the Core decoding is done. + + These hardware decode each frame cyclically. + + The hardware might be associated with different SMI-common devices. + To prevent IOMMU faults during DRAM access in such cases, each hardware with + the unique SMI-common device must be placed under a separate parent node in + the device tree. + + LAT-SoC refers to another hardware block that connected to additional LARB + (local arbiter) ports, such as RDMA and UFO. + It requires independent power and clock control to work with LAT decoder, and + it doesn't have a dedicated interrupt. + + The used video decoding pipeline architecture across various Mediatek SoC: + MT8195: LAT-SoC + LAT + Core + MT8192: LAT + Core + MT8188: LAT + Core + MT8186: Core properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-decoder.yaml b/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-decoder.yaml index cfabf360f278..a4aacd3eb189 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-decoder.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-decoder.yaml @@ -44,7 +44,8 @@ properties: maxItems: 1 iommus: - maxItems: 2 + minItems: 2 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-encoder.yaml b/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-encoder.yaml index 83c020a673d6..5b15f8977f67 100644 --- a/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-encoder.yaml +++ b/sys/contrib/device-tree/Bindings/media/mediatek-jpeg-encoder.yaml @@ -39,7 +39,7 @@ properties: iommus: minItems: 2 - maxItems: 4 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/sys/contrib/device-tree/Bindings/media/microchip,sama5d4-vdec.yaml b/sys/contrib/device-tree/Bindings/media/microchip,sama5d4-vdec.yaml index 59b805ca47c5..ede086d55add 100644 --- a/sys/contrib/device-tree/Bindings/media/microchip,sama5d4-vdec.yaml +++ b/sys/contrib/device-tree/Bindings/media/microchip,sama5d4-vdec.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml# @@ -36,12 +35,12 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/at91.h> - #include <dt-bindings/interrupt-controller/irq.h> - - vdec0: vdec@300000 { - compatible = "microchip,sama5d4-vdec"; - reg = <0x00300000 0x100000>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - }; + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/interrupt-controller/irq.h> + + vdec@300000 { + compatible = "microchip,sama5d4-vdec"; + reg = <0x00300000 0x100000>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/nxp,imx8-isi.yaml b/sys/contrib/device-tree/Bindings/media/nxp,imx8-isi.yaml index 4d5348d456a1..f43b91984f01 100644 --- a/sys/contrib/device-tree/Bindings/media/nxp,imx8-isi.yaml +++ b/sys/contrib/device-tree/Bindings/media/nxp,imx8-isi.yaml @@ -21,6 +21,7 @@ properties: enum: - fsl,imx8mn-isi - fsl,imx8mp-isi + - fsl,imx8ulp-isi - fsl,imx93-isi reg: @@ -75,6 +76,7 @@ allOf: contains: enum: - fsl,imx8mn-isi + - fsl,imx8ulp-isi - fsl,imx93-isi then: properties: diff --git a/sys/contrib/device-tree/Bindings/media/nxp,imx8-jpeg.yaml b/sys/contrib/device-tree/Bindings/media/nxp,imx8-jpeg.yaml index 2be30c5fdc83..4cba42ba7cf7 100644 --- a/sys/contrib/device-tree/Bindings/media/nxp,imx8-jpeg.yaml +++ b/sys/contrib/device-tree/Bindings/media/nxp,imx8-jpeg.yaml @@ -22,10 +22,14 @@ properties: - nxp,imx8qxp-jpgdec - nxp,imx8qxp-jpgenc - items: - - const: nxp,imx8qm-jpgdec + - enum: + - nxp,imx8qm-jpgdec + - nxp,imx95-jpgdec - const: nxp,imx8qxp-jpgdec - items: - - const: nxp,imx8qm-jpgenc + - enum: + - nxp,imx8qm-jpgenc + - nxp,imx95-jpgenc - const: nxp,imx8qxp-jpgenc reg: @@ -48,7 +52,7 @@ properties: description: List of phandle and PM domain specifier as documented in Documentation/devicetree/bindings/power/power_domain.txt - minItems: 2 # Wrapper and 1 slot + minItems: 1 # Wrapper and all slots maxItems: 5 # Wrapper and 4 slots required: @@ -58,6 +62,24 @@ required: - interrupts - power-domains +allOf: + - if: + properties: + compatible: + contains: + enum: + - nxp,imx95-jpgenc + - nxp,imx95-jpgdec + then: + properties: + power-domains: + maxItems: 1 + else: + properties: + power-domains: + minItems: 2 # Wrapper and 1 slot + + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-mipi-csi2.yaml b/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-mipi-csi2.yaml index 2a14e3b0e004..3389bab266a9 100644 --- a/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-mipi-csi2.yaml +++ b/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-mipi-csi2.yaml @@ -16,11 +16,19 @@ description: |- properties: compatible: - enum: - - fsl,imx8mq-mipi-csi2 + oneOf: + - enum: + - fsl,imx8mq-mipi-csi2 + - fsl,imx8qxp-mipi-csi2 + - items: + - const: fsl,imx8qm-mipi-csi2 + - const: fsl,imx8qxp-mipi-csi2 reg: - maxItems: 1 + items: + - description: MIPI CSI-2 RX host controller register. + - description: MIPI CSI-2 control and status register (csr). + minItems: 1 clocks: items: @@ -46,6 +54,7 @@ properties: - description: CORE_RESET reset register bit definition - description: PHY_REF_RESET reset register bit definition - description: ESC_RESET reset register bit definition + minItems: 1 fsl,mipi-phy-gpr: description: | @@ -113,9 +122,30 @@ required: - clock-names - power-domains - resets - - fsl,mipi-phy-gpr - ports +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-mipi-csi2 + then: + properties: + reg: + minItems: 2 + resets: + maxItems: 1 + else: + properties: + reg: + maxItems: 1 + resets: + minItems: 3 + required: + - fsl,mipi-phy-gpr + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-vpu.yaml b/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-vpu.yaml index 3d58f02b0c5d..19528262810a 100644 --- a/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-vpu.yaml +++ b/sys/contrib/device-tree/Bindings/media/nxp,imx8mq-vpu.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml# @@ -44,26 +43,26 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/imx8mq-clock.h> - #include <dt-bindings/power/imx8mq-power.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx8mq-clock.h> + #include <dt-bindings/power/imx8mq-power.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> - vpu_g1: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu-g1"; - reg = <0x38300000 0x10000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; - }; + video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; - | - #include <dt-bindings/clock/imx8mq-clock.h> - #include <dt-bindings/power/imx8mq-power.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx8mq-clock.h> + #include <dt-bindings/power/imx8mq-power.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> - vpu_g2: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu-g2"; - reg = <0x38310000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; - }; + video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,msm8916-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,msm8916-camss.yaml index 9cc0a968a401..7c8e0a905d89 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,msm8916-camss.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,msm8916-camss.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml# @@ -94,6 +93,10 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -113,6 +116,10 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/sys/contrib/device-tree/Bindings/media/qcom,msm8916-venus.yaml b/sys/contrib/device-tree/Bindings/media/qcom,msm8916-venus.yaml index 9410f13ca97c..da140c2e3d3f 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,msm8916-venus.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,msm8916-venus.yaml @@ -45,6 +45,7 @@ properties: required: - compatible + deprecated: true additionalProperties: false video-encoder: @@ -57,13 +58,12 @@ properties: required: - compatible + deprecated: true additionalProperties: false required: - compatible - iommus - - video-decoder - - video-encoder unevaluatedProperties: false @@ -83,12 +83,4 @@ examples: power-domains = <&gcc VENUS_GDSC>; iommus = <&apps_iommu 5>; memory-region = <&venus_mem>; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,msm8953-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,msm8953-camss.yaml new file mode 100644 index 000000000000..6d776b0ca711 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/qcom,msm8953-camss.yaml @@ -0,0 +1,337 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,msm8953-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8953 Camera Subsystem (CAMSS) + +maintainers: + - Barnabas Czeman <barnabas.czeman@mainlining.org> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,msm8953-camss + + clocks: + minItems: 30 + maxItems: 30 + + clock-names: + items: + - const: ahb + - const: csi0 + - const: csi0_ahb + - const: csi0_phy + - const: csi0_pix + - const: csi0_rdi + - const: csi1 + - const: csi1_ahb + - const: csi1_phy + - const: csi1_pix + - const: csi1_rdi + - const: csi2 + - const: csi2_ahb + - const: csi2_phy + - const: csi2_pix + - const: csi2_rdi + - const: csi_vfe0 + - const: csi_vfe1 + - const: csiphy0_timer + - const: csiphy1_timer + - const: csiphy2_timer + - const: ispif_ahb + - const: micro_ahb + - const: top_ahb + - const: vfe0 + - const: vfe0_ahb + - const: vfe0_axi + - const: vfe1 + - const: vfe1_ahb + - const: vfe1_axi + + interrupts: + minItems: 9 + maxItems: 9 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: ispif + - const: vfe0 + - const: vfe1 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller. + - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: vfe0 + - const: vfe1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: + An array of physical data lanes indexes. + Position of an entry determines the logical + lane number, while the value of an entry + indicates physical lane index. Lane swapping + is supported. Physical lane indexes; + 0, 2, 3, 4. + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + reg: + minItems: 13 + maxItems: 13 + + reg-names: + items: + - const: csi_clk_mux + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy0_clk_mux + - const: csiphy1 + - const: csiphy1_clk_mux + - const: csiphy2 + - const: csiphy2_clk_mux + - const: ispif + - const: vfe0 + - const: vfe1 + + vdda-supply: + description: + Definition of the regulator used as analog power supply. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + - vdda-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,gcc-msm8953.h> + + camss: camss@1b00020 { + compatible = "qcom,msm8953-camss"; + + reg = <0x1b00020 0x10>, + <0x1b30000 0x100>, + <0x1b30400 0x100>, + <0x1b30800 0x100>, + <0x1b34000 0x1000>, + <0x1b00030 0x4>, + <0x1b35000 0x1000>, + <0x1b00038 0x4>, + <0x1b36000 0x1000>, + <0x1b00040 0x4>, + <0x1b31000 0x500>, + <0x1b10000 0x1000>, + <0x1b14000 0x1000>; + reg-names = "csi_clk_mux", + "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csiphy2", + "csiphy2_clk_mux", + "ispif", + "vfe0", + "vfe1"; + + clocks = <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE0_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_AXI_CLK>, + <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AHB_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>; + clock-names = "ahb", + "csi0", + "csi0_ahb", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1", + "csi1_ahb", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2", + "csi2_ahb", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi_vfe0", + "csi_vfe1", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "ispif_ahb", + "micro_ahb", + "top_ahb", + "vfe0", + "vfe0_ahb", + "vfe0_axi", + "vfe1", + "vfe1_ahb", + "vfe1_axi"; + + interrupts = <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "ispif", + "vfe0", + "vfe1"; + + iommus = <&apps_iommu 0x14>; + + power-domains = <&gcc VFE0_GDSC>, + <&gcc VFE1_GDSC>; + power-domain-names = "vfe0", "vfe1"; + + vdda-supply = <®_2v8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,msm8996-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,msm8996-camss.yaml index 5cb0e337ea6e..a2025952fe95 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,msm8996-camss.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,msm8996-camss.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml# @@ -116,6 +115,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -135,6 +139,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -154,6 +163,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -173,6 +187,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sc7180-venus.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sc7180-venus.yaml index 5cec1d077cda..bfd8b1ad4731 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sc7180-venus.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sc7180-venus.yaml @@ -18,7 +18,12 @@ allOf: properties: compatible: - const: qcom,sc7180-venus + oneOf: + - items: + - enum: + - qcom,qcs615-venus + - const: qcom,sc7180-venus + - const: qcom,sc7180-venus power-domains: minItems: 2 @@ -70,6 +75,7 @@ properties: required: - compatible + deprecated: true additionalProperties: false video-encoder: @@ -82,14 +88,13 @@ properties: required: - compatible + deprecated: true additionalProperties: false required: - compatible - power-domain-names - iommus - - video-decoder - - video-encoder unevaluatedProperties: false @@ -114,12 +119,4 @@ examples: "vcodec0_core", "vcodec0_bus"; iommus = <&apps_smmu 0x0c00 0x60>; memory-region = <&venus_mem>; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sc7280-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sc7280-camss.yaml new file mode 100644 index 000000000000..ee35e3bc97ff --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/qcom,sc7280-camss.yaml @@ -0,0 +1,425 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 CAMSS ISP + +maintainers: + - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com> + - Hariram Purushothaman <hariramp@quicinc.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sc7280-camss + + reg: + maxItems: 15 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 33 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: icp_ahb + - const: vfe0 + - const: vfe0_axi + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe1 + - const: vfe1_axi + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe2 + - const: vfe2_axi + - const: vfe2_cphy_rx + - const: vfe2_csid + - const: vfe_lite0 + - const: vfe_lite0_cphy_rx + - const: vfe_lite0_csid + - const: vfe_lite1 + - const: vfe_lite1_cphy_rx + - const: vfe_lite1_csid + + interrupts: + maxItems: 15 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 4. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,camcc-sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb3000 { + compatible = "qcom,sc7280-camss"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0accf000 0x0 0x1000>, + <0x0 0x0ace0000 0x0 0x2000>, + <0x0 0x0ace2000 0x0 0x2000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0accb000 0x0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2", + "vfe2_axi", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x800 0x4e0>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sc7280-venus.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sc7280-venus.yaml index 10c334e6b3dc..413c5b4ee650 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sc7280-venus.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sc7280-venus.yaml @@ -68,6 +68,7 @@ properties: required: - compatible + deprecated: true additionalProperties: false video-encoder: @@ -80,14 +81,13 @@ properties: required: - compatible + deprecated: true additionalProperties: false required: - compatible - power-domain-names - iommus - - video-decoder - - video-encoder unevaluatedProperties: false @@ -125,14 +125,6 @@ examples: memory-region = <&video_mem>; - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - video-firmware { iommus = <&apps_smmu 0x21a2 0x0>; }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sc8280xp-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sc8280xp-camss.yaml index c0bc31709873..d195f1bfb23d 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sc8280xp-camss.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sc8280xp-camss.yaml @@ -143,6 +143,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -166,6 +171,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -189,6 +199,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -212,6 +227,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -328,26 +348,26 @@ examples: vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; - interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csid1_lite", "vfe_lite1", diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sdm660-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sdm660-camss.yaml index 584106e275f6..6e6ad8390e44 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sdm660-camss.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sdm660-camss.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml# @@ -122,6 +121,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -141,6 +145,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -160,6 +169,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -179,6 +193,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sdm670-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sdm670-camss.yaml new file mode 100644 index 000000000000..35c40fe22376 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/qcom,sdm670-camss.yaml @@ -0,0 +1,318 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Camera Subsystem (CAMSS) + +maintainers: + - Richard Acayan <mailingradian@gmail.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sdm670-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + interrupts: + maxItems: 9 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + clocks: + maxItems: 22 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csi0 + - const: csi1 + - const: csi2 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: soc_ahb + - const: vfe0 + - const: vfe0_axi + - const: vfe0_cphy_rx + - const: vfe1 + - const: vfe1_axi + - const: vfe1_cphy_rx + - const: vfe_lite + - const: vfe_lite_cphy_rx + + iommus: + maxItems: 4 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,camcc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb3000 { + compatible = "qcom,sdm670-camss"; + + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_l8a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&front_sensor_ep>; + }; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sdm845-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sdm845-camss.yaml index ec4380a0a03f..82bf4689d330 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sdm845-camss.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sdm845-camss.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml# @@ -109,6 +108,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -128,6 +132,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -147,6 +156,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -166,6 +180,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - data-lanes @@ -296,16 +315,16 @@ examples: "vfe_lite_cphy_rx", "vfe_lite_src"; - interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csid0", "csid1", diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sdm845-venus-v2.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sdm845-venus-v2.yaml index 6228fd2b3246..c839cb1ebc09 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sdm845-venus-v2.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sdm845-venus-v2.yaml @@ -70,6 +70,7 @@ properties: required: - compatible + deprecated: true additionalProperties: false video-core1: @@ -82,14 +83,13 @@ properties: required: - compatible + deprecated: true additionalProperties: false required: - compatible - power-domain-names - iommus - - video-core0 - - video-core1 unevaluatedProperties: false @@ -119,12 +119,4 @@ examples: iommus = <&apps_smmu 0x10a0 0x8>, <&apps_smmu 0x10b0 0x0>; memory-region = <&venus_mem>; - - video-core0 { - compatible = "venus-decoder"; - }; - - video-core1 { - compatible = "venus-encoder"; - }; }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sm8250-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sm8250-camss.yaml index fa5073c0fd1e..ebf68ff4ab96 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sm8250-camss.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sm8250-camss.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml# @@ -129,6 +128,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -152,6 +156,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -175,6 +184,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -198,6 +212,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -221,6 +240,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -244,6 +268,11 @@ properties: minItems: 1 maxItems: 4 + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + required: - clock-lanes - data-lanes @@ -329,20 +358,20 @@ examples: vdda-phy-supply = <&vreg_l5a_0p88>; vdda-pll-supply = <&vreg_l9a_1p2>; - interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy0", "csiphy1", "csiphy2", diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sm8250-venus.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sm8250-venus.yaml index f66033ae8b59..da54493220c9 100644 --- a/sys/contrib/device-tree/Bindings/media/qcom,sm8250-venus.yaml +++ b/sys/contrib/device-tree/Bindings/media/qcom,sm8250-venus.yaml @@ -73,6 +73,7 @@ properties: required: - compatible + deprecated: true additionalProperties: false video-encoder: @@ -85,6 +86,7 @@ properties: required: - compatible + deprecated: true additionalProperties: false required: @@ -95,8 +97,6 @@ required: - iommus - resets - reset-names - - video-decoder - - video-encoder unevaluatedProperties: false @@ -132,12 +132,4 @@ examples: resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, <&videocc VIDEO_CC_MVS0C_CLK_ARES>; reset-names = "bus", "core"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sm8550-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sm8550-camss.yaml new file mode 100644 index 000000000000..cd34f14916b4 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/qcom,sm8550-camss.yaml @@ -0,0 +1,597 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Camera Subsystem (CAMSS) + +maintainers: + - Depeng Shao <quic_depengs@quicinc.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8550-camss + + reg: + maxItems: 19 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 36 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_ife_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy6 + - const: csiphy6_timer + - const: csiphy7 + - const: csiphy7_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0_mnoc + + iommus: + maxItems: 1 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI4. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@6: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI6. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@7: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI7. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8550-camcc.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb7000 { + compatible = "qcom,sm8550-camss"; + + reg = <0 0x0acb7000 0 0xd00>, + <0 0x0acb9000 0 0xd00>, + <0 0x0acbb000 0 0xd00>, + <0 0x0acca000 0 0xa00>, + <0 0x0acce000 0 0xa00>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0acf0000 0 0x2000>, + <0 0x0acf2000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accb000 0 0x1800>, + <0 0x0accf000 0 0x1800>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY6_CLK>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY7_CLK>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_ife_lite", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy6", + "csiphy6_timer", + "csiphy7", + "csiphy7_timer", + "csiphy_rx", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csiphy_ep0: endpoint@0 { + reg = <0>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/qcom,sm8550-iris.yaml b/sys/contrib/device-tree/Bindings/media/qcom,sm8550-iris.yaml new file mode 100644 index 000000000000..c79bf2101812 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/qcom,sm8550-iris.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm iris video encode and decode accelerators + +maintainers: + - Vikash Garodia <quic_vgarodia@quicinc.com> + - Dikshita Agarwal <quic_dikshita@quicinc.com> + +description: + The iris video processing unit is a video encode and decode accelerator + present on Qualcomm platforms. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,sa8775p-iris + - const: qcom,sm8550-iris + - enum: + - qcom,qcs8300-iris + - qcom,sm8550-iris + - qcom,sm8650-iris + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + resets: + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + items: + - const: bus + - const: xo + - const: core + + iommus: + maxItems: 2 + + dma-coherent: true + + operating-points-v2: true + + opp-table: + type: object + +required: + - compatible + - power-domain-names + - interconnects + - interconnect-names + - resets + - reset-names + - iommus + - dma-coherent + +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,sm8450-videocc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + video-codec@aa00000 { + compatible = "qcom,sm8550-iris"; + reg = <0x0aa00000 0xf0000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", "core", "vcodec0_core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", "video-mem"; + + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "bus"; + + iommus = <&apps_smmu 0x1940 0x0000>, + <&apps_smmu 0x1947 0x0000>; + dma-coherent; + + operating-points-v2 = <&iris_opp_table>; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; +... diff --git a/sys/contrib/device-tree/Bindings/media/qcom,x1e80100-camss.yaml b/sys/contrib/device-tree/Bindings/media/qcom,x1e80100-camss.yaml new file mode 100644 index 000000000000..b075341caafc --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/qcom,x1e80100-camss.yaml @@ -0,0 +1,367 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Camera Subsystem (CAMSS) + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,x1e80100-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 29 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe_lite + - const: cphy_rx_clk_src + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 13 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 8 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdd-csiphy-0p8-supply: + description: + Phandle to a 0.8V regulator supply to a PHY. + + vdd-csiphy-1p2-supply: + description: + Phandle to 1.8V regulator supply to a PHY. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdd-csiphy-0p8-supply + - vdd-csiphy-1p2-supply + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,x1e80100-gcc.h> + #include <dt-bindings/clock/qcom,x1e80100-camcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: isp@acb7000 { + compatible = "qcom,x1e80100-camss"; + + reg = <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0x4000>, + <0 0x0ac71000 0 0x4000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x1800 0x60>, + <&apps_smmu 0x1860 0x60>, + <&apps_smmu 0x18e0 0x00>, + <&apps_smmu 0x1980 0x20>, + <&apps_smmu 0x1900 0x00>, + <&apps_smmu 0x19a0 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "top"; + + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy_ep0: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/raspberrypi,rp1-cfe.yaml b/sys/contrib/device-tree/Bindings/media/raspberrypi,rp1-cfe.yaml new file mode 100644 index 000000000000..eba5394719b9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/raspberrypi,rp1-cfe.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/raspberrypi,rp1-cfe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raspberry Pi PiSP Camera Front End + +maintainers: + - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> + +description: | + The Raspberry Pi PiSP Camera Front End is a module in Raspberrypi 5's RP1 I/O + controller, that contains: + - MIPI D-PHY + - MIPI CSI-2 receiver + - Simple image processor (called PiSP Front End, or FE) + + The FE documentation is available at: + https://datasheets.raspberrypi.com/camera/raspberry-pi-image-signal-processor-specification.pdf + + The PHY and CSI-2 receiver part have no public documentation. + +properties: + compatible: + items: + - const: raspberrypi,rp1-cfe + + reg: + items: + - description: CSI-2 registers + - description: D-PHY registers + - description: MIPI CFG (a simple top-level mux) registers + - description: FE registers + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + description: CSI-2 RX Port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + rp1 { + #address-cells = <2>; + #size-cells = <2>; + + csi@110000 { + compatible = "raspberrypi,rp1-cfe"; + reg = <0xc0 0x40110000 0x0 0x100>, + <0xc0 0x40114000 0x0 0x100>, + <0xc0 0x40120000 0x0 0x100>, + <0xc0 0x40124000 0x0 0x1000>; + + interrupts = <42>; + + clocks = <&rp1_clocks>; + + port { + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; + }; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/media/renesas,csi2.yaml b/sys/contrib/device-tree/Bindings/media/renesas,csi2.yaml index 977ab188d654..80b77875874d 100644 --- a/sys/contrib/device-tree/Bindings/media/renesas,csi2.yaml +++ b/sys/contrib/device-tree/Bindings/media/renesas,csi2.yaml @@ -32,6 +32,7 @@ properties: - renesas,r8a77990-csi2 # R-Car E3 - renesas,r8a779a0-csi2 # R-Car V3U - renesas,r8a779g0-csi2 # R-Car V4H + - renesas,r8a779h0-csi2 # R-Car V4M reg: maxItems: 1 diff --git a/sys/contrib/device-tree/Bindings/media/renesas,fcp.yaml b/sys/contrib/device-tree/Bindings/media/renesas,fcp.yaml index f94dacd96278..cf92dfe69637 100644 --- a/sys/contrib/device-tree/Bindings/media/renesas,fcp.yaml +++ b/sys/contrib/device-tree/Bindings/media/renesas,fcp.yaml @@ -30,14 +30,25 @@ properties: - renesas,r9a07g043u-fcpvd # RZ/G2UL - renesas,r9a07g044-fcpvd # RZ/G2{L,LC} - renesas,r9a07g054-fcpvd # RZ/V2L + - renesas,r9a09g056-fcpvd # RZ/V2N + - renesas,r9a09g057-fcpvd # RZ/V2H(P) - const: renesas,fcpv # Generic FCP for VSP fallback reg: maxItems: 1 - clocks: true + clocks: + minItems: 1 + items: + - description: Main clock + - description: Register access clock + - description: Video clock - clock-names: true + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk iommus: maxItems: 1 @@ -66,18 +77,11 @@ allOf: - renesas,r9a07g043u-fcpvd - renesas,r9a07g044-fcpvd - renesas,r9a07g054-fcpvd + - renesas,r9a09g057-fcpvd then: properties: clocks: - items: - - description: Main clock - - description: Register access clock - - description: Video clock - clock-names: - items: - - const: aclk - - const: pclk - - const: vclk + minItems: 3 required: - clock-names else: diff --git a/sys/contrib/device-tree/Bindings/media/renesas,isp.yaml b/sys/contrib/device-tree/Bindings/media/renesas,isp.yaml index 33650a1ea034..d25e020f5e5e 100644 --- a/sys/contrib/device-tree/Bindings/media/renesas,isp.yaml +++ b/sys/contrib/device-tree/Bindings/media/renesas,isp.yaml @@ -22,20 +22,58 @@ properties: - enum: - renesas,r8a779a0-isp # V3U - renesas,r8a779g0-isp # V4H + - renesas,r8a779h0-isp # V4M + - const: renesas,rcar-gen4-isp # Generic R-Car Gen4 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: cs + - const: core interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: cs + - const: core clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: cs + - const: core power-domains: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: cs + - const: core + + renesas,vspx: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the companion VSPX responsible for the Streaming Bridge + functionality. The Streaming Bridge is responsible for feeding image + and configuration data to the ISP when operating in memory-to-memory + mode. ports: $ref: /schemas/graph.yaml#/properties/ports @@ -101,10 +139,14 @@ properties: required: - compatible - reg + - reg-names - interrupts + - interrupt-names - clocks + - clock-names - power-domains - resets + - reset-names - ports additionalProperties: false @@ -116,12 +158,19 @@ examples: #include <dt-bindings/power/r8a779a0-sysc.h> isp1: isp@fed20000 { - compatible = "renesas,r8a779a0-isp"; - reg = <0xfed20000 0x10000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 613>; + compatible = "renesas,r8a779a0-isp", "renesas,rcar-gen4-isp"; + reg = <0xfed20000 0x10000>, <0xfee00000 0x100000>; + reg-names = "cs", "core"; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cs", "core"; + clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>; + clock-names = "cs", "core"; power-domains = <&sysc R8A779A0_PD_A3ISP01>; - resets = <&cpg 613>; + resets = <&cpg 613>, <&cpg 17>; + reset-names = "cs", "core"; + + renesas,vspx = <&vspx1>; ports { #address-cells = <1>; diff --git a/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-cru.yaml b/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-cru.yaml index bc1245127025..47e18690fa57 100644 --- a/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-cru.yaml +++ b/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-cru.yaml @@ -17,24 +17,43 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-cru # RZ/G2UL - - renesas,r9a07g044-cru # RZ/G2{L,LC} - - renesas,r9a07g054-cru # RZ/V2L - - const: renesas,rzg2l-cru + oneOf: + - items: + - enum: + - renesas,r9a07g043-cru # RZ/G2UL + - renesas,r9a07g044-cru # RZ/G2{L,LC} + - renesas,r9a07g054-cru # RZ/V2L + - const: renesas,rzg2l-cru + - const: renesas,r9a09g047-cru # RZ/G3E reg: maxItems: 1 interrupts: - maxItems: 3 + oneOf: + - items: + - description: CRU Interrupt for image_conv + - description: CRU Interrupt for image_conv_err + - description: CRU AXI master error interrupt + - items: + - description: CRU Interrupt for image_conv + - description: CRU AXI master error interrupt + - description: CRU Video Data AXI Master Address 0 Write End interrupt + - description: CRU Statistics data AXI master addr 0 write end interrupt + - description: CRU Video statistics data AXI master addr 0 write end interrupt interrupt-names: - items: - - const: image_conv - - const: image_conv_err - - const: axi_mst_err + oneOf: + - items: + - const: image_conv + - const: image_conv_err + - const: axi_mst_err + - items: + - const: image_conv + - const: axi_mst_err + - const: vd_addr_wend + - const: sd_addr_wend + - const: vsd_addr_wend clocks: items: @@ -109,6 +128,10 @@ allOf: - renesas,r9a07g054-cru then: properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 ports: required: - port@0 @@ -122,10 +145,30 @@ allOf: - renesas,r9a07g043-cru then: properties: + interrupts: + maxItems: 3 + interrupt-names: + maxItems: 3 ports: properties: port@0: false + required: + - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-cru + then: + properties: + interrupts: + minItems: 5 + interrupt-names: + minItems: 5 + ports: + properties: + port@0: false required: - port@1 diff --git a/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-csi2.yaml b/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-csi2.yaml index 7faa12fecd5b..c5c511c9f0db 100644 --- a/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-csi2.yaml +++ b/sys/contrib/device-tree/Bindings/media/renesas,rzg2l-csi2.yaml @@ -17,12 +17,17 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-csi2 # RZ/G2UL - - renesas,r9a07g044-csi2 # RZ/G2{L,LC} - - renesas,r9a07g054-csi2 # RZ/V2L - - const: renesas,rzg2l-csi2 + oneOf: + - items: + - enum: + - renesas,r9a07g043-csi2 # RZ/G2UL + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} + - renesas,r9a07g054-csi2 # RZ/V2L + - const: renesas,rzg2l-csi2 + - items: + - const: renesas,r9a09g047-csi2 # RZ/G3E + - const: renesas,r9a09g057-csi2 + - const: renesas,r9a09g057-csi2 # RZ/V2H(P) reg: maxItems: 1 @@ -31,16 +36,24 @@ properties: maxItems: 1 clocks: - items: - - description: Internal clock for connecting CRU and MIPI - - description: CRU Main clock - - description: CRU Register access clock + oneOf: + - items: + - description: Internal clock for connecting CRU and MIPI + - description: CRU Main clock + - description: CRU Register access clock + - items: + - description: CRU Main clock + - description: CRU Register access clock clock-names: - items: - - const: system - - const: video - - const: apb + oneOf: + - items: + - const: system + - const: video + - const: apb + - items: + - const: video + - const: apb power-domains: maxItems: 1 @@ -48,7 +61,7 @@ properties: resets: items: - description: CRU_PRESETN reset terminal - - description: CRU_CMN_RSTB reset terminal + - description: D-PHY reset (CRU_CMN_RSTB or CRU_n_S_RESETN) reset-names: items: @@ -101,6 +114,25 @@ required: - reset-names - ports +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-csi2 + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/media/renesas,vsp1.yaml b/sys/contrib/device-tree/Bindings/media/renesas,vsp1.yaml index 1a03e67462a4..07a97dd87a5b 100644 --- a/sys/contrib/device-tree/Bindings/media/renesas,vsp1.yaml +++ b/sys/contrib/device-tree/Bindings/media/renesas,vsp1.yaml @@ -25,6 +25,8 @@ properties: - enum: - renesas,r9a07g043u-vsp2 # RZ/G2UL - renesas,r9a07g054-vsp2 # RZ/V2L + - renesas,r9a09g056-vsp2 # RZ/V2N + - renesas,r9a09g057-vsp2 # RZ/V2H(P) - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback reg: @@ -33,8 +35,18 @@ properties: interrupts: maxItems: 1 - clocks: true - clock-names: true + clocks: + minItems: 1 + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk power-domains: maxItems: 1 @@ -78,15 +90,7 @@ allOf: then: properties: clocks: - items: - - description: Main clock - - description: Register access clock - - description: Video clock - clock-names: - items: - - const: aclk - - const: pclk - - const: vclk + minItems: 3 required: - clock-names else: diff --git a/sys/contrib/device-tree/Bindings/media/rockchip,rk3568-vepu.yaml b/sys/contrib/device-tree/Bindings/media/rockchip,rk3568-vepu.yaml index 947ad699cc5e..d246f5d38427 100644 --- a/sys/contrib/device-tree/Bindings/media/rockchip,rk3568-vepu.yaml +++ b/sys/contrib/device-tree/Bindings/media/rockchip,rk3568-vepu.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml# diff --git a/sys/contrib/device-tree/Bindings/media/rockchip,vdec.yaml b/sys/contrib/device-tree/Bindings/media/rockchip,vdec.yaml index 08b02ec16755..96b6c8938768 100644 --- a/sys/contrib/device-tree/Bindings/media/rockchip,vdec.yaml +++ b/sys/contrib/device-tree/Bindings/media/rockchip,vdec.yaml @@ -10,13 +10,15 @@ maintainers: - Heiko Stuebner <heiko@sntech.de> description: |- - The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264, - HEVC an VP9 streams. + Rockchip SoCs have variants of the same stateless Video Decoder that can + decodes H.264, HEVC, VP9 and AV1 streams, depending on the variant. properties: compatible: oneOf: - const: rockchip,rk3399-vdec + - const: rockchip,rk3576-vdec + - const: rockchip,rk3588-vdec - items: - enum: - rockchip,rk3228-vdec @@ -24,35 +26,72 @@ properties: - const: rockchip,rk3399-vdec reg: - maxItems: 1 + minItems: 1 + items: + - description: The function configuration registers base + - description: The link table configuration registers base + - description: The cache configuration registers base + + reg-names: + items: + - const: function + - const: link + - const: cache interrupts: maxItems: 1 clocks: + minItems: 4 items: - description: The Video Decoder AXI interface clock - description: The Video Decoder AHB interface clock - description: The Video Decoded CABAC clock - description: The Video Decoder core clock + - description: The Video decoder HEVC CABAC clock clock-names: + minItems: 4 items: - const: axi - const: ahb - const: cabac - const: core + - const: hevc_cabac assigned-clocks: true assigned-clock-rates: true + resets: + items: + - description: The Video Decoder AXI interface reset + - description: The Video Decoder AHB interface reset + - description: The Video Decoded CABAC reset + - description: The Video Decoder core reset + - description: The Video decoder HEVC CABAC reset + + reset-names: + items: + - const: axi + - const: ahb + - const: cabac + - const: core + - const: hevc_cabac + power-domains: maxItems: 1 iommus: maxItems: 1 + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to a reserved on-chip SRAM regions. + Some SoCs, like rk3588 provide on-chip SRAM to store temporary + buffers during decoding. + required: - compatible - reg @@ -61,6 +100,41 @@ required: - clock-names - power-domains +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-vdec + - rockchip,rk3588-vdec + then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + clocks: + minItems: 5 + clock-names: + minItems: 5 + resets: + minItems: 5 + reset-names: + minItems: 5 + else: + properties: + reg: + maxItems: 1 + reg-names: false + clocks: + maxItems: 4 + clock-names: + maxItems: 4 + resets: false + reset-names: false + sram: false + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/media/rockchip-vpu.yaml b/sys/contrib/device-tree/Bindings/media/rockchip-vpu.yaml index 719aeb2dc593..8c2501634080 100644 --- a/sys/contrib/device-tree/Bindings/media/rockchip-vpu.yaml +++ b/sys/contrib/device-tree/Bindings/media/rockchip-vpu.yaml @@ -1,5 +1,4 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - %YAML 1.2 --- $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml# @@ -92,18 +91,18 @@ additionalProperties: false examples: - | - #include <dt-bindings/clock/rk3288-cru.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/power/rk3288-power.h> - - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0xff9a0000 0x800>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3288_PD_VIDEO>; - iommus = <&vpu_mmu>; - }; + #include <dt-bindings/clock/rk3288-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/rk3288-power.h> + + video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; + reg = <0xff9a0000 0x800>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3288_PD_VIDEO>; + iommus = <&vpu_mmu>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/snps,dw-hdmi-rx.yaml b/sys/contrib/device-tree/Bindings/media/snps,dw-hdmi-rx.yaml new file mode 100644 index 000000000000..510e94e9ca3a --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/snps,dw-hdmi-rx.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Device Tree bindings for Synopsys DesignWare HDMI RX Controller + +--- +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI RX Controller + +maintainers: + - Shreeya Patel <shreeya.patel@collabora.com> + +description: + Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs + allowing devices to receive and decode high-resolution video streams + from external sources like media players, cameras, laptops, etc. + +properties: + compatible: + items: + - const: rockchip,rk3588-hdmirx-ctrler + - const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: cec + - const: hdmi + - const: dma + + clocks: + maxItems: 7 + + clock-names: + items: + - const: aclk + - const: audio + - const: cr_para + - const: pclk + - const: ref + - const: hclk_s_hdmirx + - const: hclk_vo1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: axi + - const: apb + - const: ref + - const: biu + + memory-region: + maxItems: 1 + + hpd-gpios: + description: GPIO specifier for HPD. + maxItems: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the general register file + containing HDMIRX PHY status bits. + + rockchip,vo1-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the Video Output GRF register + to enable EDID transfer through SDAIN and SCLIN. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - pinctrl-0 + - hpd-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/rk3588-power.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + hdmi_receiver: hdmi-receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0xfdee0000 0x6000>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + memory-region = <&hdmi_receiver_cma>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>; + pinctrl-names = "default"; + hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + }; diff --git a/sys/contrib/device-tree/Bindings/media/st,stm32-dcmipp.yaml b/sys/contrib/device-tree/Bindings/media/st,stm32-dcmipp.yaml index 87731f3ce7bd..7b03a77adbce 100644 --- a/sys/contrib/device-tree/Bindings/media/st,stm32-dcmipp.yaml +++ b/sys/contrib/device-tree/Bindings/media/st,stm32-dcmipp.yaml @@ -12,7 +12,9 @@ maintainers: properties: compatible: - const: st,stm32mp13-dcmipp + enum: + - st,stm32mp13-dcmipp + - st,stm32mp25-dcmipp reg: maxItems: 1 @@ -21,11 +23,24 @@ properties: maxItems: 1 clocks: - maxItems: 1 + items: + - description: bus clock + - description: csi clock + minItems: 1 + + clock-names: + items: + - const: kclk + - const: mclk + minItems: 1 resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false @@ -39,7 +54,7 @@ properties: properties: bus-type: - enum: [5, 6] + enum: [4, 5, 6] default: 5 bus-width: @@ -50,9 +65,6 @@ properties: hsync-active: true vsync-active: true - required: - - pclk-sample - required: - compatible - reg @@ -61,6 +73,35 @@ required: - resets - port +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dcmipp + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + port: + properties: + endpoint: + properties: + bus-type: + enum: [5, 6] + else: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + additionalProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/media/st,stm32mp25-csi.yaml b/sys/contrib/device-tree/Bindings/media/st,stm32mp25-csi.yaml new file mode 100644 index 000000000000..e9fa3cfea5d2 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/media/st,stm32mp25-csi.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 CSI controller + +description: + The STM32 CSI controller, coupled with a D-PHY allows connecting a CSI-2 + based camera to the DCMIPP camera pipeline. + +maintainers: + - Alain Volmat <alain.volmat@foss.st.com> + +properties: + compatible: + enum: + - st,stm32mp25-csi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: pclk + - const: txesc + - const: csi2phy + + resets: + maxItems: 1 + + vdd-supply: + description: Digital core power supply (0.91V) + + vdda18-supply: + description: System analog power supply (1.8V) + + access-controllers: + minItems: 1 + maxItems: 2 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port node + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + items: + - const: 1 + - const: 2 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/st,stm32mp25-rcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/media/video-interfaces.h> + #include <dt-bindings/reset/st,stm32mp25-rcc.h> + csi@48020000 { + compatible = "st,stm32mp25-csi"; + reg = <0x48020000 0x2000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CSI_R>; + clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>; + clock-names = "pclk", "txesc", "csi2phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&imx335_ep>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dcmipp_0>; + }; + }; + }; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/media/ti,j721e-csi2rx-shim.yaml b/sys/contrib/device-tree/Bindings/media/ti,j721e-csi2rx-shim.yaml index f762fdc05e4d..b9f033f2f3ce 100644 --- a/sys/contrib/device-tree/Bindings/media/ti,j721e-csi2rx-shim.yaml +++ b/sys/contrib/device-tree/Bindings/media/ti,j721e-csi2rx-shim.yaml @@ -13,7 +13,7 @@ description: | CSI_RX_IF section. maintainers: - - Jai Luthra <j-luthra@ti.com> + - Jai Luthra <jai.luthra@linux.dev> properties: compatible: diff --git a/sys/contrib/device-tree/Bindings/media/video-interfaces.yaml b/sys/contrib/device-tree/Bindings/media/video-interfaces.yaml index 26e3e7d7c67b..038e85b45bef 100644 --- a/sys/contrib/device-tree/Bindings/media/video-interfaces.yaml +++ b/sys/contrib/device-tree/Bindings/media/video-interfaces.yaml @@ -210,6 +210,27 @@ properties: lane-polarities property is omitted, the value must be interpreted as 0 (normal). This property is valid for serial busses only. + line-orders: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + enum: + - 0 # ABC + - 1 # ACB + - 2 # BAC + - 3 # BCA + - 4 # CAB + - 5 # CBA + description: + An array of line orders of the CSI-2 C-PHY data lanes. The order of the + lanes are the same as in data-lanes property. Valid values are 0-5 as + defined in the MIPI Discovery and Configuration (DisCo) Specification for + Imaging. The length of the array must be the same length as the + data-lanes property. If the line-orders property is omitted, the value + shall be interpreted as 0 (ABC). This property is valid for CSI-2 C-PHY + busses only. + strobe: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 0, 1 ] |