diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/riscv/cpus.yaml')
| -rw-r--r-- | sys/contrib/device-tree/Bindings/riscv/cpus.yaml | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/sys/contrib/device-tree/Bindings/riscv/cpus.yaml b/sys/contrib/device-tree/Bindings/riscv/cpus.yaml index 8edc8261241a..1a0cf0702a45 100644 --- a/sys/contrib/device-tree/Bindings/riscv/cpus.yaml +++ b/sys/contrib/device-tree/Bindings/riscv/cpus.yaml @@ -26,6 +26,18 @@ description: | allOf: - $ref: /schemas/cpu.yaml# - $ref: extensions.yaml + - if: + not: + properties: + compatible: + contains: + enum: + - thead,c906 + - thead,c910 + - thead,c920 + then: + properties: + thead,vlenb: false properties: compatible: @@ -33,6 +45,7 @@ properties: - items: - enum: - amd,mbv32 + - amd,mbv64 - andestech,ax45mp - canaan,k210 - sifive,bullet0 @@ -46,6 +59,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x60 - thead,c906 - thead,c908 - thead,c910 @@ -95,6 +109,13 @@ properties: description: The blocksize in bytes for the Zicboz cache operations. + thead,vlenb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + VLEN/8, the vector register length in bytes. This property is required on + thead systems where the vector register length is not identical on all harts, or + the vlenb CSR is not available. + # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false |