diff options
Diffstat (limited to 'sys/contrib/device-tree/Bindings/watchdog')
44 files changed, 1951 insertions, 139 deletions
diff --git a/sys/contrib/device-tree/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 9aa3c313c49f..274519fc24fd 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -4,10 +4,10 @@ $id: http://devicetree.org/schemas/watchdog/allwinner,sun4i-a10-wdt.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Watchdog Device Tree Bindings +title: Allwinner A10 Watchdog allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -24,16 +24,23 @@ properties: - allwinner,sun50i-a100-wdt - allwinner,sun50i-h6-wdt - allwinner,sun50i-h616-wdt + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset + - allwinner,suniv-f1c100s-wdt - const: allwinner,sun6i-a31-wdt + - const: allwinner,sun20i-d1-wdt - items: - - const: allwinner,suniv-f1c100s-wdt - - const: allwinner,sun4i-a10-wdt + - const: allwinner,sun20i-d1-wdt-reset + - const: allwinner,sun20i-d1-wdt reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: 32 KHz input clock + - description: secondary clock source interrupts: maxItems: 1 @@ -44,6 +51,36 @@ required: - clocks - interrupts +if: + properties: + compatible: + contains: + enum: + - allwinner,sun20i-d1-wdt + - allwinner,sun20i-d1-wdt-reset + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset + +then: + properties: + clocks: + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input + + clock-names: + items: + - const: hosc + - const: losc + + required: + - clock-names + +else: + properties: + clocks: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/watchdog/alphascale,asm9260-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/alphascale,asm9260-wdt.yaml new file mode 100644 index 000000000000..fea84f5b7e6d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/alphascale,asm9260-wdt.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/alphascale,asm9260-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Alphascale asm9260 Watchdog timer + +allOf: + - $ref: watchdog.yaml# + +maintainers: + - Oleksij Rempel <linux@rempel-privat.de> + +properties: + compatible: + const: alphascale,asm9260-wdt + + reg: + maxItems: 1 + + clocks: + items: + - description: source clock, used for tick counter + - description: ahb gate + + clock-names: + items: + - const: mod + - const: ahb + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: wdt_rst + + alphascale,mode: + description: | + Specifies the reset mode of operation. If set to sw, then reset is handled + via interrupt request, if set to debug, then it does nothing and logs. + $ref: /schemas/types.yaml#/definitions/string + enum: [hw, sw, debug] + default: hw + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/alphascale,asm9260.h> + watchdog0: watchdog@80048000 { + compatible = "alphascale,asm9260-wdt"; + reg = <0x80048000 0x10>; + clocks = <&acc CLKID_SYS_WDT>, <&acc CLKID_AHB_WDT>; + clock-names = "mod", "ahb"; + interrupts = <55>; + timeout-sec = <30>; + alphascale,mode = "hw"; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml index c7459cf70e30..f5cc7aa1b93b 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml @@ -2,13 +2,13 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Meson GXBB SoCs Watchdog timer maintainers: - - Neil Armstrong <narmstrong@baylibre.com> + - Neil Armstrong <neil.armstrong@linaro.org> allOf: - $ref: watchdog.yaml# @@ -36,7 +36,7 @@ unevaluatedProperties: false examples: - | watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x98d0 0x10>; - clocks = <&xtal>; + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x98d0 0x10>; + clocks = <&xtal>; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson6-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson6-wdt.yaml new file mode 100644 index 000000000000..84732cb58ec4 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/amlogic,meson6-wdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/amlogic,meson6-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson6 SoCs Watchdog timer + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson6-wdt + - amlogic,meson8-wdt + - amlogic,meson8b-wdt + - items: + - const: amlogic,meson8m2-wdt + - const: amlogic,meson8b-wdt + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + wdt: watchdog@c1109900 { + compatible = "amlogic,meson6-wdt"; + reg = <0xc1109900 0x8>; + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <10>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/apple,wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/apple,wdt.yaml new file mode 100644 index 000000000000..929681127df0 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/apple,wdt.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Watchdog + +allOf: + - $ref: watchdog.yaml# + +maintainers: + - Sven Peter <sven@svenpeter.dev> + +properties: + compatible: + items: + - enum: + - apple,t8103-wdt + - apple,t8112-wdt + - apple,t6000-wdt + - const: apple,wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/apple-aic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + wdt: watchdog@50000000 { + compatible = "apple,t8103-wdt", "apple,wdt"; + reg = <0x50000000 0x4000>; + clocks = <&clk>; + interrupts = <AIC_IRQ 123 IRQ_TYPE_LEVEL_HIGH>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/arm,sbsa-gwdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/arm,sbsa-gwdt.yaml new file mode 100644 index 000000000000..aa804f96acba --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/arm,sbsa-gwdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/arm,sbsa-gwdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SBSA (Server Base System Architecture) Generic Watchdog + +maintainers: + - Fu Wei <fu.wei@linaro.org> + +description: | + The SBSA Generic Watchdog Timer is used to force a reset of the system after + two stages of timeout have elapsed. A detailed definition of the watchdog + timer can be found in the ARM document: ARM-DEN-0029 - Server Base System + Architecture (SBSA) + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: arm,sbsa-gwdt + + reg: + items: + - description: Watchdog control frame + - description: Refresh frame + + interrupts: + description: The Watchdog Signal 0 (WS0) SPI (Shared Peripheral Interrupt) + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + watchdog@2a440000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x2a440000 0x1000>, + <0x2a450000 0x1000>; + interrupts = <0 27 4>; + timeout-sec = <30>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/arm,sp805.yaml b/sys/contrib/device-tree/Bindings/watchdog/arm,sp805.yaml index a69cac8ec208..7aea255b301b 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/arm,sp805.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/arm,sp805.yaml @@ -43,7 +43,6 @@ properties: Clocks driving the watchdog timer hardware. The first clock is used for the actual watchdog counter. The second clock drives the register interface. - minItems: 2 maxItems: 2 clock-names: diff --git a/sys/contrib/device-tree/Bindings/watchdog/arm,twd-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/arm,twd-wdt.yaml new file mode 100644 index 000000000000..9646ac72051e --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/arm,twd-wdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Timer-Watchdog Watchdog + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core + Timer-Watchdog (aka TWD), which provides both a per-cpu local timer + and watchdog. + + The TWD is usually attached to a GIC to deliver its two per-processor + interrupts. + +properties: + compatible: + enum: + - arm,cortex-a9-twd-wdt + - arm,cortex-a5-twd-wdt + - arm,arm11mp-twd-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@2c000620 { + compatible = "arm,arm11mp-twd-wdt"; + reg = <0x2c000620 0x20>; + interrupts = <GIC_PPI 14 0xf01>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/arm-smc-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/arm-smc-wdt.yaml index e3a1d79574e2..b5573852ef5a 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/arm-smc-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/arm-smc-wdt.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Secure Monitor Call based watchdog allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# maintainers: - Julius Werner <jwerner@chromium.org> @@ -16,6 +16,7 @@ properties: compatible: enum: - arm,smc-wdt + arm,smc-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | @@ -30,9 +31,9 @@ unevaluatedProperties: false examples: - | watchdog { - compatible = "arm,smc-wdt"; - arm,smc-id = <0x82003D06>; - timeout-sec = <15>; + compatible = "arm,smc-wdt"; + arm,smc-id = <0x82003D06>; + timeout-sec = <15>; }; ... diff --git a/sys/contrib/device-tree/Bindings/watchdog/atmel,at91sam9-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/atmel,at91sam9-wdt.yaml new file mode 100644 index 000000000000..ad27bc518670 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/atmel,at91sam9-wdt.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Watchdog Timers + +maintainers: + - Eugen Hristev <eugen.hristev@microchip.com> + +properties: + compatible: + const: atmel,at91sam9260-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + atmel,max-heartbeat-sec: + description: + Should contain the maximum heartbeat value in seconds. This value + should be less or equal to 16. It is used to compute the WDV field. + maximum: 16 + + atmel,min-heartbeat-sec: + description: + Should contain the minimum heartbeat value in seconds. This value + must be smaller than the max-heartbeat-sec value. It is used to + compute the WDD field. + maximum: 16 + + atmel,watchdog-type: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be hardware or software. + oneOf: + - description: + Hardware watchdog uses the at91 watchdog reset. + const: hardware + - description: | + Software watchdog uses the watchdog interrupt + to trigger a software reset. + const: software + default: hardware + + atmel,reset-type: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be proc or all. This is valid only when using hardware watchdog. + oneOf: + - description: + Assert peripherals and processor reset signals. + const: all + - description: + Assert the processor reset signal. + const: proc + default: all + + atmel,disable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Should be present if you want to stop the watchdog. + + atmel,idle-halt: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Should be present if you want to stop the watchdog when + entering idle state. + CAUTION: This property should be used with care, it actually makes the + watchdog not counting when the CPU is in idle state, therefore the + watchdog reset time depends on mean CPU usage and will not reset at all + if the CPU stops working while it is in idle state, which is probably + not what you want. + + atmel,dbg-halt: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Should be present if you want to stop the watchdog when + entering debug state. + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: watchdog.yaml# + - if: + properties: + atmel,reset-type: + enum: + - all + - proc + then: + properties: + atmel,watchdog-type: + const: hardware + +dependencies: + atmel,reset-type: ['atmel,watchdog-type'] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + timeout-sec = <15>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + atmel,idle-halt; + atmel,max-heartbeat-sec = <16>; + atmel,min-heartbeat-sec = <0>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/atmel,sama5d4-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/atmel,sama5d4-wdt.yaml new file mode 100644 index 000000000000..816f85ee2c77 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/atmel,sama5d4-wdt.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller + +maintainers: + - Eugen Hristev <eugen.hristev@microchip.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - atmel,sama5d4-wdt + - microchip,sam9x60-wdt + - microchip,sama7g5-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + atmel,watchdog-type: + $ref: /schemas/types.yaml#/definitions/string + description: should be hardware or software. + oneOf: + - description: + Enable watchdog fault reset. A watchdog fault triggers + watchdog reset. + const: hardware + - description: + Enable watchdog fault interrupt. A watchdog fault asserts + watchdog interrupt. + const: software + default: hardware + + atmel,idle-halt: + $ref: /schemas/types.yaml#/definitions/flag + description: | + present if you want to stop the watchdog when the CPU is in idle state. + CAUTION: This property should be used with care, it actually makes the + watchdog not counting when the CPU is in idle state, therefore the + watchdog reset time depends on mean CPU usage and will not reset at all + if the CPU stop working while it is in idle state, which is probably + not what you want. + + atmel,dbg-halt: + $ref: /schemas/types.yaml#/definitions/flag + description: | + present if you want to stop the watchdog when the CPU is in debug state. + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + watchdog@fc068640 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xfc068640 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>; + timeout-sec = <10>; + atmel,watchdog-type = "hardware"; + atmel,dbg-halt; + atmel,idle-halt; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/brcm,bcm7038-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/brcm,bcm7038-wdt.yaml new file mode 100644 index 000000000000..526ff908d134 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/brcm,bcm7038-wdt.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/brcm,bcm7038-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM63xx and BCM7038 watchdog timer + +allOf: + - $ref: watchdog.yaml# + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + - Justin Chen <justinpopo6@gmail.com> + - Rafał Miłecki <rafal@milecki.pl> + +properties: + compatible: + enum: + - brcm,bcm6345-wdt + - brcm,bcm7038-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: > + The clock running the watchdog. If no clock is found the driver will + default to 27000000 Hz. + +unevaluatedProperties: false + +required: + - reg + +examples: + - | + watchdog@f040a7e8 { + compatible = "brcm,bcm7038-wdt"; + reg = <0xf040a7e8 0x16>; + clocks = <&upg_fixed>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/brcm,kona-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/brcm,kona-wdt.yaml new file mode 100644 index 000000000000..3d4403b41cbe --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/brcm,kona-wdt.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/brcm,kona-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Kona Family Watchdog Timer + +description: | + This watchdog timer is used in the following Broadcom SoCs: + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + items: + - const: brcm,bcm11351-wdt + - const: brcm,kona-wdt + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@35002f40 { + compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; + reg = <0x35002f40 0x6c>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/cdns,wdt-r1p2.yaml b/sys/contrib/device-tree/Bindings/watchdog/cdns,wdt-r1p2.yaml new file mode 100644 index 000000000000..3c17c5883bce --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/cdns,wdt-r1p2.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence watchdog timer controller + +maintainers: + - Neeli Srinivas <srinivas.neeli@amd.com> + +description: + The cadence watchdog timer is used to detect and recover from + system malfunctions. This watchdog contains 24 bit counter and + a programmable reset period. The timeout period varies from 1 ms + to 30 seconds while using a 100Mhz clock. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - cdns,wdt-r1p2 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-on-timeout: + type: boolean + description: | + If this property exists, then a reset is done when watchdog + times out. + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@f8005000 { + compatible = "cdns,wdt-r1p2"; + reg = <0xf8005000 0x1000>; + clocks = <&clkc 45>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>; + reset-on-timeout; + timeout-sec = <10>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/da9062-wdt.txt b/sys/contrib/device-tree/Bindings/watchdog/da9062-wdt.txt index 950e4fba8dbc..354314d854ef 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/da9062-wdt.txt +++ b/sys/contrib/device-tree/Bindings/watchdog/da9062-wdt.txt @@ -10,6 +10,12 @@ Optional properties: - dlg,use-sw-pm: Add this property to disable the watchdog during suspend. Only use this option if you can't use the watchdog automatic suspend function during a suspend (see register CONTROL_B). +- dlg,wdt-sd: Set what happens on watchdog timeout. If this bit is set the + watchdog timeout triggers SHUTDOWN, if cleared the watchdog triggers + POWERDOWN. Can be 0 or 1. Only use this option if you want to change the + default chip's OTP setting for WATCHDOG_SD bit. If this property is NOT + set the WATCHDOG_SD bit and on timeout watchdog behavior will match the + chip's OTP settings. Example: DA9062 diff --git a/sys/contrib/device-tree/Bindings/watchdog/faraday,ftwdt010.yaml b/sys/contrib/device-tree/Bindings/watchdog/faraday,ftwdt010.yaml new file mode 100644 index 000000000000..726dc872ad02 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/faraday,ftwdt010.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/faraday,ftwdt010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTWDT010 watchdog + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + - Corentin Labbe <clabbe@baylibre.com> + +description: | + This is an IP part from Faraday Technology found in the Gemini + SoCs and others. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - const: faraday,ftwdt010 + - items: + - enum: + - cortina,gemini-watchdog + - moxa,moxart-watchdog + - const: faraday,ftwdt010 + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: PCLK + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + watchdog@41000000 { + compatible = "faraday,ftwdt010"; + reg = <0x41000000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + timeout-sec = <5>; + }; + - | + watchdog: watchdog@98500000 { + compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; + reg = <0x98500000 0x10>; + clocks = <&clk_apb>; + clock-names = "PCLK"; + }; +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/fsl,scu-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/fsl,scu-wdt.yaml new file mode 100644 index 000000000000..47701248cd8d --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/fsl,scu-wdt.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/fsl,scu-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Watchdog Based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + items: + - const: fsl,imx8qxp-sc-wdt + - const: fsl,imx-sc-wdt + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/fsl-imx-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/fsl-imx-wdt.yaml index fb7695515be1..181f0cc5b5bd 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/fsl-imx-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/fsl-imx-wdt.yaml @@ -9,9 +9,6 @@ title: Freescale i.MX Watchdog Timer (WDT) Controller maintainers: - Anson Huang <Anson.Huang@nxp.com> -allOf: - - $ref: "watchdog.yaml#" - properties: compatible: oneOf: @@ -55,11 +52,45 @@ properties: If present, the watchdog device is configured to assert its external reset (WDOG_B) instead of issuing a software reset. + fsl,suspend-in-wait: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, the watchdog device is suspended in WAIT mode + (Suspend-to-Idle). Only supported on certain devices. + required: - compatible - interrupts - reg +allOf: + - $ref: watchdog.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx25-wdt + - fsl,imx35-wdt + - fsl,imx50-wdt + - fsl,imx51-wdt + - fsl,imx53-wdt + - fsl,imx6q-wdt + - fsl,imx6sl-wdt + - fsl,imx6sll-wdt + - fsl,imx6sx-wdt + - fsl,imx6ul-wdt + - fsl,imx7d-wdt + - fsl,imx8mm-wdt + - fsl,imx8mn-wdt + - fsl,imx8mp-wdt + - fsl,imx8mq-wdt + - fsl,vf610-wdt + then: + properties: + fsl,suspend-in-wait: false + unevaluatedProperties: false examples: diff --git a/sys/contrib/device-tree/Bindings/watchdog/fsl-imx7ulp-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/fsl-imx7ulp-wdt.yaml index 51d6d482bbc2..4b7ed1355701 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/fsl-imx7ulp-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -10,12 +10,16 @@ maintainers: - Anson Huang <Anson.Huang@nxp.com> allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# properties: compatible: - enum: - - fsl,imx7ulp-wdt + oneOf: + - const: fsl,imx7ulp-wdt + - items: + - const: fsl,imx8ulp-wdt + - const: fsl,imx7ulp-wdt + - const: fsl,imx93-wdt reg: maxItems: 1 @@ -26,21 +30,13 @@ properties: clocks: maxItems: 1 - assigned-clocks: - maxItems: 1 - - assigned-clocks-parents: - maxItems: 1 - - timeout-sec: true - required: - compatible - interrupts - reg - clocks -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -53,7 +49,7 @@ examples: interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc2 IMX7ULP_CLK_WDG1>; assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/gpio-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/gpio-wdt.yaml new file mode 100644 index 000000000000..155dc7965e9b --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/gpio-wdt.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/gpio-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO controlled watchdog + +maintainers: + - Robert Marko <robert.marko@sartura.hr> + +properties: + compatible: + const: linux,wdt-gpio + + gpios: + maxItems: 1 + description: GPIO connected to the WDT reset pin + + hw_algo: + $ref: /schemas/types.yaml#/definitions/string + description: Algorithm used by the driver + oneOf: + - description: + Either a high-to-low or a low-to-high transition clears the WDT counter. + The watchdog timer is disabled when GPIO is left floating or connected + to a three-state buffer. + const: toggle + - description: + Low or high level starts counting WDT timeout, the opposite level + disables the WDT. + Active level is determined by the GPIO flags. + const: level + + hw_margin_ms: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Maximum time to reset watchdog circuit (in milliseconds) + minimum: 2 + maximum: 65535 + + always-running: + type: boolean + description: + If the watchdog timer cannot be disabled, add this flag to have the driver + keep toggling the signal without a client. + It will only cease to toggle the signal when the device is open and the + timeout elapsed. + +required: + - compatible + - gpios + - hw_algo + - hw_margin_ms + +unevaluatedProperties: false diff --git a/sys/contrib/device-tree/Bindings/watchdog/linux,wdt-gpio.yaml b/sys/contrib/device-tree/Bindings/watchdog/linux,wdt-gpio.yaml new file mode 100644 index 000000000000..499f1b7e03f9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/linux,wdt-gpio.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO-controlled Watchdog + +maintainers: + - Guenter Roeck <linux@roeck-us.net> + - Robert Marko <robert.marko@sartura.hr> + +properties: + compatible: + const: linux,wdt-gpio + + gpios: + description: gpio connection to WDT reset pin + maxItems: 1 + + hw_algo: + description: The algorithm used by the driver. + oneOf: + - description: + Either a high-to-low or a low-to-high transition clears the WDT counter. + The watchdog timer is disabled when GPIO is left floating or connected + to a three-state buffer. + const: toggle + - description: + Low or high level starts counting WDT timeout, the opposite level + disables the WDT. + Active level is determined by the GPIO flags. + const: level + + hw_margin_ms: + description: Maximum time to reset watchdog circuit (milliseconds). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 65535 + + always-running: + type: boolean + description: + If the watchdog timer cannot be disabled, add this flag to have the driver + keep toggling the signal without a client. + It will only cease to toggle the signal when the device is open and the + timeout elapsed. + +required: + - compatible + - gpios + - hw_algo + - hw_margin_ms + +allOf: + - $ref: watchdog.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + watchdog { + compatible = "linux,wdt-gpio"; + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + hw_algo = "toggle"; + hw_margin_ms = <1600>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/loongson,ls1x-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/loongson,ls1x-wdt.yaml new file mode 100644 index 000000000000..81690d4b62a6 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/loongson,ls1x-wdt.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/loongson,ls1x-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-1 Watchdog Timer + +maintainers: + - Keguang Zhang <keguang.zhang@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - loongson,ls1b-wdt + - loongson,ls1c-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/loongson,ls1x-clk.h> + watchdog: watchdog@1fe5c060 { + compatible = "loongson,ls1b-wdt"; + reg = <0x1fe5c060 0xc>; + + clocks = <&clkc LS1X_CLKID_APB>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/maxim,max63xx.yaml b/sys/contrib/device-tree/Bindings/watchdog/maxim,max63xx.yaml new file mode 100644 index 000000000000..1a6490c43d89 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/maxim,max63xx.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/maxim,max63xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim 63xx Watchdog Timers + +allOf: + - $ref: watchdog.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + +maintainers: + - Marc Zyngier <maz@kernel.org> + - Linus Walleij <linus.walleij@linaro.org> + +properties: + compatible: + enum: + - maxim,max6369 + - maxim,max6370 + - maxim,max6371 + - maxim,max6372 + - maxim,max6373 + - maxim,max6374 + + reg: + description: This is a 1-byte memory-mapped address + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + wdt: watchdog@50000000 { + compatible = "maxim,max6369"; + reg = <0x50000000 0x1>; + timeout-sec = <10>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/mediatek,mt7621-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/mediatek,mt7621-wdt.yaml new file mode 100644 index 000000000000..18160869c378 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/mediatek,mt7621-wdt.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink Watchdog Timers + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: mediatek,mt7621-wdt + + reg: + maxItems: 1 + + mediatek,sysctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to system controller 'sysc' syscon node which + controls system registers + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + watchdog@100 { + compatible = "mediatek,mt7621-wdt"; + reg = <0x100 0x100>; + mediatek,sysctl = <&sysc>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/mediatek,mtk-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/mediatek,mtk-wdt.yaml new file mode 100644 index 000000000000..cc502838bc39 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/mediatek,mtk-wdt.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoCs Watchdog timer + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + The watchdog supports a pre-timeout interrupt that fires + timeout-sec/2 before the expiry. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-wdt + - mediatek,mt6589-wdt + - mediatek,mt6735-wdt + - mediatek,mt6795-wdt + - mediatek,mt7986-wdt + - mediatek,mt8183-wdt + - mediatek,mt8186-wdt + - mediatek,mt8188-wdt + - mediatek,mt8192-wdt + - mediatek,mt8195-wdt + - items: + - enum: + - mediatek,mt2701-wdt + - mediatek,mt6582-wdt + - mediatek,mt6797-wdt + - mediatek,mt7622-wdt + - mediatek,mt7623-wdt + - mediatek,mt7629-wdt + - mediatek,mt8173-wdt + - mediatek,mt8365-wdt + - mediatek,mt8516-wdt + - const: mediatek,mt6589-wdt + + reg: + maxItems: 1 + + interrupts: + items: + - description: Watchdog pre-timeout (bark) interrupt + + mediatek,disable-extrst: + description: Disable sending output reset signal + type: boolean + + mediatek,reset-by-toprgu: + description: The Top Reset Generation Unit (TOPRGU) generates reset signals + and distributes them to each IP. If present, the watchdog timer will be + reset by TOPRGU once system resets. + type: boolean + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt"; + reg = <0 0x10007000 0 0x100>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; + mediatek,disable-extrst; + timeout-sec = <10>; + #reset-cells = <1>; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/mstar,msc313e-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/mstar,msc313e-wdt.yaml new file mode 100644 index 000000000000..33794711c594 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/mstar,msc313e-wdt.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/mstar,msc313e-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar Watchdog + +maintainers: + - Daniel Palmer <daniel@0x0f.com> + - Romain Perier <romain.perier@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - mstar,msc313e-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@6000 { + compatible = "mstar,msc313e-wdt"; + reg = <0x6000 0x1f>; + clocks = <&xtal_div2>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/mtk-wdt.txt b/sys/contrib/device-tree/Bindings/watchdog/mtk-wdt.txt index e36ba60de829..762c62e428ef 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/mtk-wdt.txt +++ b/sys/contrib/device-tree/Bindings/watchdog/mtk-wdt.txt @@ -1,22 +1,31 @@ Mediatek SoCs Watchdog timer +The watchdog supports a pre-timeout interrupt that fires timeout-sec/2 +before the expiry. + Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 "mediatek,mt2712-wdt": for MT2712 + "mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 + "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986 "mediatek,mt8183-wdt": for MT8183 + "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 + "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195 - reg : Specifies base physical address and size of the registers. Optional properties: +- mediatek,disable-extrst: disable send output reset signal +- interrupts: Watchdog pre-timeout (bark) interrupt. - timeout-sec: contains the watchdog timeout in seconds. - #reset-cells: Should be 1. @@ -25,7 +34,9 @@ Example: watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; + mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; + interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; timeout-sec = <10>; #reset-cells = <1>; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/nuvoton,npcm-wdt.txt b/sys/contrib/device-tree/Bindings/watchdog/nuvoton,npcm-wdt.txt index 9059f54dc023..866a958b8a2b 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/nuvoton,npcm-wdt.txt +++ b/sys/contrib/device-tree/Bindings/watchdog/nuvoton,npcm-wdt.txt @@ -6,7 +6,8 @@ expiry. Required properties: - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or - "nuvoton,wpcm450-wdt" for WPCM450 (Hermon). + "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or + "nuvoton,npcm845-wdt" for NPCM845 (Arbel). - reg : Offset and length of the register set for the device. - interrupts : Contain the timer interrupt with flags for falling edge. diff --git a/sys/contrib/device-tree/Bindings/watchdog/qcom,pm8916-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/qcom,pm8916-wdt.yaml new file mode 100644 index 000000000000..568eb8480fc3 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/qcom,pm8916-wdt.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/qcom,pm8916-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PM8916 watchdog timer controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: qcom,pm8916-wdt + + interrupts: + maxItems: 1 + +required: + - compatible + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/spmi/spmi.h> + + pmic@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + watchdog { + compatible = "qcom,pm8916-wdt"; + interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; + timeout-sec = <60>; + }; + }; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/qcom-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/qcom-wdt.yaml index b8e4118945a0..6d0fe6abd06a 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/qcom-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/qcom-wdt.yaml @@ -9,24 +9,46 @@ title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer maintainers: - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> -allOf: - - $ref: watchdog.yaml# - properties: + $nodename: + pattern: "^(watchdog|timer)@[0-9a-f]+$" + compatible: - enum: - - qcom,apss-wdt-qcs404 - - qcom,apss-wdt-sc7180 - - qcom,apss-wdt-sdm845 - - qcom,apss-wdt-sdx55 - - qcom,apss-wdt-sm8150 - - qcom,kpss-timer - - qcom,kpss-wdt - - qcom,kpss-wdt-apq8064 - - qcom,kpss-wdt-ipq4019 - - qcom,kpss-wdt-ipq8064 - - qcom,kpss-wdt-msm8960 - - qcom,scss-timer + oneOf: + - items: + - enum: + - qcom,kpss-wdt-ipq4019 + - qcom,apss-wdt-ipq5332 + - qcom,apss-wdt-ipq9574 + - qcom,apss-wdt-msm8994 + - qcom,apss-wdt-qcm2290 + - qcom,apss-wdt-qcs404 + - qcom,apss-wdt-sa8775p + - qcom,apss-wdt-sc7180 + - qcom,apss-wdt-sc7280 + - qcom,apss-wdt-sc8180x + - qcom,apss-wdt-sc8280xp + - qcom,apss-wdt-sdm845 + - qcom,apss-wdt-sdx55 + - qcom,apss-wdt-sdx65 + - qcom,apss-wdt-sm6115 + - qcom,apss-wdt-sm6350 + - qcom,apss-wdt-sm8150 + - qcom,apss-wdt-sm8250 + - const: qcom,kpss-wdt + - const: qcom,kpss-wdt + deprecated: true + - items: + - const: qcom,scss-timer + - const: qcom,msm-timer + - items: + - enum: + - qcom,kpss-wdt-apq8064 + - qcom,kpss-wdt-ipq8064 + - qcom,kpss-wdt-mdm9615 + - qcom,kpss-wdt-msm8960 + - const: qcom,kpss-timer + - const: qcom,msm-timer reg: maxItems: 1 @@ -34,18 +56,87 @@ properties: clocks: maxItems: 1 + clock-names: + items: + - const: sleep + + clock-frequency: + description: + The frequency of the general purpose timer in Hz. + + cpu-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Per-CPU offset used when the timer is accessed without the CPU remapping + facilities. The offset is cpu-offset + (0x10000 * cpu-nr). + + interrupts: + minItems: 1 + maxItems: 5 + required: - compatible - reg - clocks +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + const: qcom,kpss-wdt + then: + properties: + clock-frequency: false + cpu-offset: false + interrupts: + minItems: 1 + items: + - description: Bark + - description: Bite + + else: + properties: + interrupts: + minItems: 3 + items: + - description: Debug + - description: First general purpose timer + - description: Second general purpose timer + - description: First watchdog + - description: Second watchdog + required: + - clock-frequency + unevaluatedProperties: false examples: - | - watchdog@208a038 { - compatible = "qcom,kpss-wdt-ipq8064"; - reg = <0x0208a038 0x40>; - clocks = <&sleep_clk>; - timeout-sec = <10>; + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; + reg = <0x17c10000 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + timeout-sec = <10>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@200a000 { + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/ralink,rt2880-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/ralink,rt2880-wdt.yaml new file mode 100644 index 000000000000..51e00de947e9 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/ralink,rt2880-wdt.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/ralink,rt2880-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink Watchdog Timers + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: ralink,rt2880-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@100 { + compatible = "ralink,rt2880-wdt"; + reg = <0x120 0x10>; + clocks = <&clkref>; + resets = <&rstctrl 8>; + interrupt-parent = <&intc>; + interrupts = <1>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/realtek,otto-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/realtek,otto-wdt.yaml new file mode 100644 index 000000000000..1f5390a67cdb --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/realtek,otto-wdt.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Otto watchdog timer + +maintainers: + - Sander Vanheule <sander@svanheule.net> + +description: | + The timer has two timeout phases. Both phases have a maximum duration of 32 + prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The + minimum duration of each phase is one tick. Each phase can trigger an + interrupt, although the phase 2 interrupt will occur with the system reset. + - Phase 1: During this phase, the WDT can be pinged to reset the timeout. + - Phase 2: Starts after phase 1 has timed out, and only serves to give the + system some time to clean up, or notify others that it's going to reset. + During this phase, pinging the WDT has no effect, and a reset is + unavoidable, unless the WDT is disabled. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - realtek,rtl8380-wdt + - realtek,rtl8390-wdt + - realtek,rtl9300-wdt + - realtek,rtl9310-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: interrupt specifier for pretimeout + - description: interrupt specifier for timeout + + interrupt-names: + items: + - const: phase1 + - const: phase2 + + realtek,reset-mode: + $ref: /schemas/types.yaml#/definitions/string + description: | + Specify how the system is reset after a timeout. Defaults to "cpu" if + left unspecified. + oneOf: + - description: Reset the entire chip + const: soc + - description: | + Reset the CPU and IPsec engine, but leave other peripherals untouched + const: cpu + - description: | + Reset the execution pointer, but don't actually reset any hardware + const: software + +required: + - compatible + - reg + - clocks + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + watchdog: watchdog@3150 { + compatible = "realtek,rtl8380-wdt"; + reg = <0x3150 0xc>; + + realtek,reset-mode = "soc"; + + clocks = <&lxbus_clock>; + timeout-sec = <20>; + + interrupt-parent = <&rtlintc>; + interrupt-names = "phase1", "phase2"; + interrupts = <19>, <18>; + }; + +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/renesas,wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/renesas,wdt.yaml index ab66d3f0c476..951a7d54135a 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/renesas,wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/renesas,wdt.yaml @@ -10,9 +10,6 @@ maintainers: - Wolfram Sang <wsa+renesas@sang-engineering.com> - Geert Uytterhoeven <geert+renesas@glider.be> -allOf: - - $ref: "watchdog.yaml#" - properties: compatible: oneOf: @@ -24,6 +21,23 @@ properties: - items: - enum: + - renesas,r9a06g032-wdt # RZ/N1D + - const: renesas,rzn1-wdt # RZ/N1 + + - items: + - enum: + - renesas,r9a07g043-wdt # RZ/G2UL and RZ/Five + - renesas,r9a07g044-wdt # RZ/G2{L,LC} + - renesas,r9a07g054-wdt # RZ/V2L + - const: renesas,rzg2l-wdt + + - items: + - enum: + - renesas,r9a09g011-wdt # RZ/V2M + - const: renesas,rzv2m-wdt # RZ/V2M + + - items: + - enum: - renesas,r8a7742-wdt # RZ/G1H - renesas,r8a7743-wdt # RZ/G1M - renesas,r8a7744-wdt # RZ/G1N @@ -50,17 +64,41 @@ properties: - renesas,r8a77980-wdt # R-Car V3H - renesas,r8a77990-wdt # R-Car E3 - renesas,r8a77995-wdt # R-Car D3 - - renesas,r8a779a0-wdt # R-Car V3U - const: renesas,rcar-gen3-wdt # R-Car Gen3 and RZ/G2 + - items: + - enum: + - renesas,r8a779a0-wdt # R-Car V3U + - renesas,r8a779f0-wdt # R-Car S4-8 + - renesas,r8a779g0-wdt # R-Car V4H + - const: renesas,rcar-gen4-wdt # R-Car Gen4 + reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + items: + - description: Timeout + - description: Parity error + + interrupt-names: + minItems: 1 + items: + - const: wdt + - const: perrout clocks: - maxItems: 1 + minItems: 1 + items: + - description: Register access clock + - description: Main clock + + clock-names: + minItems: 1 + items: + - const: pclk + - const: oscclk power-domains: maxItems: 1 @@ -73,19 +111,63 @@ properties: required: - compatible - reg + - interrupts - clocks -if: - not: - properties: - compatible: - contains: - enum: - - renesas,rza-wdt -then: - required: - - power-domains - - resets +allOf: + - $ref: watchdog.yaml# + + - if: + not: + properties: + compatible: + contains: + enum: + - renesas,rza-wdt + - renesas,rzn1-wdt + then: + required: + - power-domains + - resets + + - if: + properties: + compatible: + contains: + enum: + - renesas,rzg2l-wdt + - renesas,rzv2m-wdt + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - renesas,rzg2l-wdt + then: + properties: + interrupts: + minItems: 2 + interrupt-names: + minItems: 2 + required: + - interrupt-names + else: + properties: + interrupts: + maxItems: 1 additionalProperties: false @@ -93,11 +175,13 @@ examples: - | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> #include <dt-bindings/power/r8a7795-sysc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> wdt0: watchdog@e6020000 { - compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; - reg = <0xe6020000 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 402>; - timeout-sec = <60>; + compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; + reg = <0xe6020000 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 402>; + timeout-sec = <60>; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/samsung-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/samsung-wdt.yaml index 76cb9586ee00..8fb6656ba0c2 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/samsung-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/samsung-wdt.yaml @@ -22,25 +22,33 @@ properties: - samsung,exynos5250-wdt # for Exynos5250 - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 + - samsung,exynos850-wdt # for Exynos850 + - samsung,exynosautov9-wdt # for Exynosautov9 reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - items: - - const: watchdog + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 + samsung,cluster-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Index of CPU cluster on which watchdog is running (in case of Exynos850) + samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: - Phandle to the PMU system controller node (in case of Exynos5250 - and Exynos5420). + Phandle to the PMU system controller node (in case of Exynos5250, + Exynos5420, Exynos7 and Exynos850). required: - compatible @@ -58,9 +66,42 @@ allOf: enum: - samsung,exynos5250-wdt - samsung,exynos5420-wdt + - samsung,exynos7-wdt + - samsung,exynos850-wdt + - samsung,exynosautov9-wdt then: required: - samsung,syscon-phandle + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-wdt + - samsung,exynosautov9-wdt + then: + properties: + clocks: + items: + - description: Bus clock, used for register interface + - description: Source clock (driving watchdog counter) + clock-names: + items: + - const: watchdog + - const: watchdog_src + samsung,cluster-index: + enum: [0, 1] + required: + - samsung,cluster-index + else: + properties: + clocks: + items: + - description: Bus clock, which is also a source clock + clock-names: + items: + - const: watchdog + samsung,cluster-index: false unevaluatedProperties: false diff --git a/sys/contrib/device-tree/Bindings/watchdog/snps,dw-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/snps,dw-wdt.yaml index b58596b1831d..76eceeddd150 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/snps,dw-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/snps,dw-wdt.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Watchdog Timer allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# maintainers: - Jamie Iles <jamie@jamieiles.com> @@ -20,6 +20,7 @@ properties: - enum: - rockchip,px30-wdt - rockchip,rk3066-wdt + - rockchip,rk3128-wdt - rockchip,rk3188-wdt - rockchip,rk3228-wdt - rockchip,rk3288-wdt @@ -27,6 +28,8 @@ properties: - rockchip,rk3328-wdt - rockchip,rk3368-wdt - rockchip,rk3399-wdt + - rockchip,rk3568-wdt + - rockchip,rk3588-wdt - rockchip,rv1108-wdt - const: snps,dw-wdt @@ -80,25 +83,25 @@ required: examples: - | watchdog@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&per_base_clk>; - resets = <&wdt_rst>; + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&per_base_clk>; + resets = <&wdt_rst>; }; - | watchdog@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&per_base_clk>; - clock-names = "tclk"; - snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF - 0x000007FF 0x0000FFFF 0x0001FFFF - 0x0003FFFF 0x0007FFFF 0x000FFFFF - 0x001FFFFF 0x003FFFFF 0x007FFFFF - 0x00FFFFFF 0x01FFFFFF 0x03FFFFFF - 0x07FFFFFF>; + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&per_base_clk>; + clock-names = "tclk"; + snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF + 0x000007FF 0x0000FFFF 0x0001FFFF + 0x0003FFFF 0x0007FFFF 0x000FFFFF + 0x001FFFFF 0x003FFFFF 0x007FFFFF + 0x00FFFFFF 0x01FFFFFF 0x03FFFFFF + 0x07FFFFFF>; }; ... diff --git a/sys/contrib/device-tree/Bindings/watchdog/socionext,uniphier-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/socionext,uniphier-wdt.yaml index a059d16cb4f2..ba0709314360 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/socionext,uniphier-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/socionext,uniphier-wdt.yaml @@ -10,7 +10,7 @@ maintainers: - Keiji Hayashibara <hayashibara.keiji@socionext.com> allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# properties: compatible: @@ -19,18 +19,12 @@ properties: required: - compatible -additionalProperties: false +unevaluatedProperties: false examples: - | // The UniPhier watchdog should be a subnode of a "syscon" compatible node. - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; + watchdog { + compatible = "socionext,uniphier-wdt"; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/st,stm32-iwdg.yaml b/sys/contrib/device-tree/Bindings/watchdog/st,stm32-iwdg.yaml index 3f1ba1d6c6b5..6b13bfc11e11 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/st,stm32-iwdg.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/st,stm32-iwdg.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/watchdog/st,stm32-iwdg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings +title: STMicroelectronics STM32 Independent WatchDoG (IWDG) maintainers: - - Yannick Fertre <yannick.fertre@st.com> - - Christophe Roullier <christophe.roullier@st.com> + - Yannick Fertre <yannick.fertre@foss.st.com> + - Christophe Roullier <christophe.roullier@foss.st.com> allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# properties: compatible: @@ -27,7 +27,6 @@ properties: - description: Low speed clock - description: Optional peripheral clock minItems: 1 - maxItems: 2 clock-names: items: @@ -49,11 +48,11 @@ examples: - | #include <dt-bindings/clock/stm32mp1-clks.h> watchdog@5a002000 { - compatible = "st,stm32mp1-iwdg"; - reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; - clock-names = "pclk", "lsi"; - timeout-sec = <32>; + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + timeout-sec = <32>; }; ... diff --git a/sys/contrib/device-tree/Bindings/watchdog/starfive,jh7100-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/starfive,jh7100-wdt.yaml new file mode 100644 index 000000000000..68f3f6fd08a6 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/starfive,jh7100-wdt.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Watchdog for JH7100 and JH7110 SoC + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + - Samin Guo <samin.guo@starfivetech.com> + +description: + The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog + has only one timeout phase and reboots. And JH7110 watchdog has two + timeout phases. At the first phase, the signal of watchdog interrupt + output(WDOGINT) will rise when counter is 0. The counter will reload + the timeout value. And then, if counter decreases to 0 again and WDOGINT + isn't cleared, the watchdog will reset the system unless the watchdog + reset is disabled. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-wdt + - starfive,jh7110-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: Core clock + + clock-names: + items: + - const: apb + - const: core + + resets: + items: + - description: APB reset + - description: Core reset + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x12480000 0x10000>; + clocks = <&clk 171>, + <&clk 172>; + clock-names = "apb", "core"; + resets = <&rst 99>, + <&rst 100>; + }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/sunplus,sp7021-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/sunplus,sp7021-wdt.yaml new file mode 100644 index 000000000000..d90271013191 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/sunplus,sp7021-wdt.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/sunplus,sp7021-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoCs Watchdog + +maintainers: + - XianTao Hu <xt.hu@cqplus1.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: sunplus,sp7021-wdt + + reg: + items: + - description: watchdog registers regions + - description: miscellaneous control registers regions + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + watchdog: watchdog@9c000630 { + compatible = "sunplus,sp7021-wdt"; + reg = <0x9c000630 0x08>, <0x9c000274 0x04>; + clocks = <&clkc 0x24>; + resets = <&rstc 0x14>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/ti,rti-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/ti,rti-wdt.yaml index 054584d7543a..fc553211e42d 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/ti,rti-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/ti,rti-wdt.yaml @@ -18,7 +18,7 @@ description: to directly reset the SoC. allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# properties: compatible: @@ -34,12 +34,6 @@ properties: power-domains: maxItems: 1 - assigned-clocks: - maxItems: 1 - - assigned-clocks-parents: - maxItems: 1 - required: - compatible - reg diff --git a/sys/contrib/device-tree/Bindings/watchdog/toshiba,visconti-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/toshiba,visconti-wdt.yaml index 690e19ce4b87..51d03d5b08ad 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/toshiba,visconti-wdt.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/toshiba,visconti-wdt.yaml @@ -24,31 +24,25 @@ properties: clocks: maxItems: 1 - timeout-sec: true - required: - compatible - reg - clocks -additionalProperties: false +unevaluatedProperties: false examples: - | + #include <dt-bindings/clock/toshiba,tmpv770x.h> + soc { #address-cells = <2>; #size-cells = <2>; - wdt_clk: wdt-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - watchdog@28330000 { + wdt: watchdog@28330000 { compatible = "toshiba,visconti-wdt"; reg = <0 0x28330000 0 0x1000>; - clocks = <&wdt_clk>; timeout-sec = <20>; + clocks = <&pismu TMPV770X_CLK_WDTCLK>; }; }; diff --git a/sys/contrib/device-tree/Bindings/watchdog/watchdog.yaml b/sys/contrib/device-tree/Bindings/watchdog/watchdog.yaml index e3dfb02f0ca5..f0a584af1223 100644 --- a/sys/contrib/device-tree/Bindings/watchdog/watchdog.yaml +++ b/sys/contrib/device-tree/Bindings/watchdog/watchdog.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/watchdog/watchdog.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Watchdog Generic Bindings +title: Watchdog Common Properties maintainers: - Guenter Roeck <linux@roeck-us.net> @@ -14,9 +14,14 @@ description: | This document describes generic bindings which can be used to describe watchdog devices in a device tree. +select: + properties: + $nodename: + pattern: "^watchdog(@.*|-([0-9]|[1-9][0-9]+))?$" + properties: $nodename: - pattern: "^watchdog(@.*|-[0-9a-f])?$" + pattern: "^(timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$" timeout-sec: description: diff --git a/sys/contrib/device-tree/Bindings/watchdog/xlnx,versal-wwdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/xlnx,versal-wwdt.yaml new file mode 100644 index 000000000000..14b069599740 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/xlnx,versal-wwdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal window watchdog timer controller + +maintainers: + - Neeli Srinivas <srinivas.neeli@amd.com> + +description: + Versal watchdog intellectual property uses window watchdog mode. + Window watchdog timer(WWDT) contains closed(first) and open(second) + window with 32 bit width. Write to the watchdog timer within + predefined window periods of time. This means a period that is not + too soon and a period that is not too late. The WWDT has to be + restarted within the open window time. If software tries to restart + WWDT outside of the open window time period, it generates a reset. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - xlnx,versal-wwdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + watchdog@fd4d0000 { + compatible = "xlnx,versal-wwdt"; + reg = <0xfd4d0000 0x10000>; + clocks = <&clock25>; + timeout-sec = <30>; + }; +... diff --git a/sys/contrib/device-tree/Bindings/watchdog/xlnx,xps-timebase-wdt.yaml b/sys/contrib/device-tree/Bindings/watchdog/xlnx,xps-timebase-wdt.yaml new file mode 100644 index 000000000000..dc1ff39d05a0 --- /dev/null +++ b/sys/contrib/device-tree/Bindings/watchdog/xlnx,xps-timebase-wdt.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI/PLB softcore and window Watchdog Timer + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + - Srinivas Neeli <srinivas.neeli@amd.com> + +description: + The Timebase watchdog timer(WDT) is a free-running 32 bit counter. + WDT uses a dual-expiration architecture. After one expiration of + the timeout interval, an interrupt is generated and the WDT state + bit is set to one in the status register. If the state bit is not + cleared (by writing a one to the state bit) before the next + expiration of the timeout interval, a WDT reset is generated. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - xlnx,xps-timebase-wdt-1.01.a + - xlnx,xps-timebase-wdt-1.00.a + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Frequency of clock in Hz + + xlnx,wdt-interval: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Watchdog timeout interval + minimum: 8 + maximum: 32 + + xlnx,wdt-enable-once: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: If watchdog is configured as enable once, + then the watchdog cannot be disabled after + it has been enabled. + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@40100000 { + compatible = "xlnx,xps-timebase-wdt-1.00.a"; + reg = <0x40100000 0x1000>; + clock-frequency = <50000000>; + clocks = <&clkc 15>; + xlnx,wdt-enable-once = <0x0>; + xlnx,wdt-interval = <0x1b>; + }; +... |