diff options
Diffstat (limited to 'sys/dev/cxgbe/common/t4_regs.h')
| -rw-r--r-- | sys/dev/cxgbe/common/t4_regs.h | 27273 |
1 files changed, 25727 insertions, 1546 deletions
diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h index e3b2a29b2ea9..8f500ec0fbdd 100644 --- a/sys/dev/cxgbe/common/t4_regs.h +++ b/sys/dev/cxgbe/common/t4_regs.h @@ -1,8 +1,7 @@ /*- * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2013, 2016 Chelsio Communications, Inc. - * All rights reserved. + * Copyright (c) 2013, 2016, 2025 Chelsio Communications. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -28,10 +27,11 @@ */ /* This file is automatically generated --- changes will be lost */ -/* Generation Date : Wed Jan 27 10:57:51 IST 2016 */ -/* Directory name: t4_reg.txt, Changeset: */ -/* Directory name: t5_reg.txt, Changeset: 6936:7f6342b03d61 */ -/* Directory name: t6_reg.txt, Changeset: 4191:ce3ccd95c109 */ +/* Generation Date : Thu Sep 11 05:25:56 PM IST 2025 */ +/* Directory name: t4_reg.txt, Date: Not specified */ +/* Directory name: t5_reg.txt, Changeset: 6945:54ba4ba7ee8b */ +/* Directory name: t6_reg.txt, Changeset: 4277:9c165d0f4899 */ +/* Directory name: t7_reg.txt, Changeset: 5945:1487219ecb20 */ #define MYPF_BASE 0x1b000 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) @@ -285,9 +285,6 @@ #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) -#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) -#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) - #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) #define NUM_PCIE_PF_INT_INSTANCES 8 @@ -459,9 +456,6 @@ #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11 -#define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4) -#define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11 - #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4) #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8 @@ -501,12 +495,175 @@ #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4) #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256 +#define T7_MYPORT_BASE 0x2e000 +#define T7_MYPORT_REG(reg_addr) (T7_MYPORT_BASE + (reg_addr)) + +#define T7_PORT0_BASE 0x30000 +#define T7_PORT0_REG(reg_addr) (T7_PORT0_BASE + (reg_addr)) + +#define T7_PORT1_BASE 0x32000 +#define T7_PORT1_REG(reg_addr) (T7_PORT1_BASE + (reg_addr)) + +#define T7_PORT2_BASE 0x34000 +#define T7_PORT2_REG(reg_addr) (T7_PORT2_BASE + (reg_addr)) + +#define T7_PORT3_BASE 0x36000 +#define T7_PORT3_REG(reg_addr) (T7_PORT3_BASE + (reg_addr)) + +#define T7_PORT_STRIDE 0x2000 +#define T7_PORT_BASE(idx) (T7_PORT0_BASE + (idx) * T7_PORT_STRIDE) +#define T7_PORT_REG(idx, reg) (T7_PORT_BASE(idx) + (reg)) + +#define PCIE_MEM_ACCESS_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_MEM_ACCESS_T7_INSTANCES 16 + +#define PCIE_T7_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T7_CMD_INSTANCES 1 + +#define PCIE_T5_ARM_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_ARM_INSTANCES 1 + +#define PCIE_JBOF_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_JBOF_INSTANCES 16 + +#define PCIE_EMUADRRMAP_REG(reg_addr, idx) ((reg_addr) + (idx) * 32) +#define NUM_PCIE_EMUADRRMAP_INSTANCES 3 + +#define CIM_GFT_MASK(idx) (A_CIM_GFT_MASK + (idx) * 4) +#define NUM_CIM_GFT_MASK_INSTANCES 4 + +#define T7_MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_T7_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4) +#define NUM_T7_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 8 + +#define T7_MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_T7_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4) +#define NUM_T7_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 8 + +#define T7_MPS_TRC_FILTER_RUNT_CTL(idx) (A_T7_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4) +#define NUM_T7_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 8 + +#define T7_MPS_TRC_FILTER_DROP(idx) (A_T7_MPS_TRC_FILTER_DROP + (idx) * 4) +#define NUM_T7_MPS_TRC_FILTER_DROP_INSTANCES 8 + +#define MPS_TRC_FILTER4_MATCH(idx) (A_MPS_TRC_FILTER4_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER4_MATCH_INSTANCES 28 + +#define MPS_TRC_FILTER4_DONT_CARE(idx) (A_MPS_TRC_FILTER4_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER4_DONT_CARE_INSTANCES 28 + +#define MPS_TRC_FILTER5_MATCH(idx) (A_MPS_TRC_FILTER5_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER5_MATCH_INSTANCES 28 + +#define MPS_TRC_FILTER5_DONT_CARE(idx) (A_MPS_TRC_FILTER5_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER5_DONT_CARE_INSTANCES 28 + +#define MPS_TRC_FILTER6_MATCH(idx) (A_MPS_TRC_FILTER6_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER6_MATCH_INSTANCES 28 + +#define MPS_TRC_FILTER6_DONT_CARE(idx) (A_MPS_TRC_FILTER6_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER6_DONT_CARE_INSTANCES 28 + +#define MPS_TRC_FILTER7_MATCH(idx) (A_MPS_TRC_FILTER7_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER7_MATCH_INSTANCES 28 + +#define MPS_TRC_FILTER7_DONT_CARE(idx) (A_MPS_TRC_FILTER7_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER7_DONT_CARE_INSTANCES 28 + +#define LE_DB_DBGI_REQ_DATA_T7(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4) +#define NUM_LE_DB_DBGI_REQ_DATA_T7_INSTANCES 13 + +#define LE_DB_DBGI_REQ_MASK_T7(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) +#define NUM_LE_DB_DBGI_REQ_MASK_T7_INSTANCES 13 + +#define LE_DB_ACTIVE_MASK_IPV6_T7(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4) +#define NUM_LE_DB_ACTIVE_MASK_IPV6_T7_INSTANCES 8 + +#define LE_HASH_MASK_GEN_IPV4T7(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV4T7_INSTANCES 8 + +#define T7_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T7_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4) +#define NUM_T7_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8 + +#define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T7(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T7_INSTANCES 8 + +#define TLS_TX_CH_REG(reg_addr, idx) ((reg_addr) + (idx) * 256) +#define NUM_TLS_TX_CH_INSTANCES 6 + +#define TLS_TX_CH_IND_REG(reg_addr, idx) ((reg_addr) + (idx) * 256) +#define NUM_TLS_TX_CH_IND_INSTANCES 6 + +#define ARM_CPU_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_ARM_CPU_INSTANCES 4 + +#define ARM_CCIM_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_ARM_CCIM_INSTANCES 4 + +#define ARM_CCIS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_ARM_CCIS_INSTANCES 5 + +#define ARM_CCI_EVNTBUS(idx) (A_ARM_CCI_EVNTBUS + (idx) * 4) +#define NUM_ARM_CCI_EVNTBUS_INSTANCES 5 + +#define ARM_ARM_CFG1(idx) (A_ARM_ARM_CFG1 + (idx) * 4) +#define NUM_ARM_ARM_CFG1_INSTANCES 2 + +#define ARM_ARM_CFG2(idx) (A_ARM_ARM_CFG2 + (idx) * 4) +#define NUM_ARM_ARM_CFG2_INSTANCES 2 + +#define ARM_MSG_REG(reg_addr, idx) ((reg_addr) + (idx) * 48) +#define NUM_ARM_MSG_INSTANCES 4 + +#define ARM_MSG_PCIE_MESSAGE2AXI_CFG4(idx) (A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 + (idx) * 4) +#define NUM_ARM_MSG_PCIE_MESSAGE2AXI_CFG4_INSTANCES 2 + +#define MC_CE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_CE_ERR_DATA_T7_INSTANCES 16 + +#define MC_UE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_UE_ERR_DATA_T7_INSTANCES 16 + +#define MC_P_BIST_USER_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_P_BIST_USER_INSTANCES 36 + +#define HMA_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_HMA_H_BIST_STATUS_INSTANCES 18 + +#define GCACHE_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_GCACHE_P_BIST_STATUS_INSTANCES 18 + +#define CIM_CTL_MAILBOX_VF_STATUS_T7(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4) +#define NUM_CIM_CTL_MAILBOX_VF_STATUS_T7_INSTANCES 8 + +#define CIM_CTL_MAILBOX_VFN_CTL_T7(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4) +#define NUM_CIM_CTL_MAILBOX_VFN_CTL_T7_INSTANCES 256 + +#define CIM_CTL_TID_MAP_EN(idx) (A_CIM_CTL_TID_MAP_EN + (idx) * 4) +#define NUM_CIM_CTL_TID_MAP_EN_INSTANCES 8 + +#define CIM_CTL_TID_MAP_CORE(idx) (A_CIM_CTL_TID_MAP_CORE + (idx) * 4) +#define NUM_CIM_CTL_TID_MAP_CORE_INSTANCES 8 + +#define CIM_CTL_CRYPTO_KEY_DATA(idx) (A_CIM_CTL_CRYPTO_KEY_DATA + (idx) * 4) +#define NUM_CIM_CTL_CRYPTO_KEY_DATA_INSTANCES 17 + +#define CIM_CTL_FLOWID_OP_VALID(idx) (A_CIM_CTL_FLOWID_OP_VALID + (idx) * 4) +#define NUM_CIM_CTL_FLOWID_OP_VALID_INSTANCES 8 + +#define CIM_CTL_SLV_REG(reg_addr, idx) ((reg_addr) + (idx) * 1024) +#define NUM_CIM_CTL_SLV_INSTANCES 7 + #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx) +#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) +#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) + +#define MC_T7_STRIDE (MC_T71_BASE_ADDR - MC_T70_BASE_ADDR) +#define MC_T7_REG(reg, idx) (reg + MC_T7_STRIDE * idx) + /* registers for module SGE */ #define SGE_BASE_ADDR 0x1000 @@ -637,6 +794,24 @@ #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) #define F_GLOBALENABLE V_GLOBALENABLE(1U) +#define S_NUMOFFID 19 +#define M_NUMOFFID 0x7U +#define V_NUMOFFID(x) ((x) << S_NUMOFFID) +#define G_NUMOFFID(x) (((x) >> S_NUMOFFID) & M_NUMOFFID) + +#define S_INGHINTENABLE2 16 +#define V_INGHINTENABLE2(x) ((x) << S_INGHINTENABLE2) +#define F_INGHINTENABLE2 V_INGHINTENABLE2(1U) + +#define S_INGHINTENABLE3 3 +#define V_INGHINTENABLE3(x) ((x) << S_INGHINTENABLE3) +#define F_INGHINTENABLE3 V_INGHINTENABLE3(1U) + +#define S_TF_MODE 1 +#define M_TF_MODE 0x3U +#define V_TF_MODE(x) ((x) << S_TF_MODE) +#define G_TF_MODE(x) (((x) >> S_TF_MODE) & M_TF_MODE) + #define A_SGE_HOST_PAGE_SIZE 0x100c #define S_HOSTPAGESIZEPF7 28 @@ -792,6 +967,16 @@ #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE) #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE) +#define S_WR_SENDPATH_ERROR_OPCODE 16 +#define M_WR_SENDPATH_ERROR_OPCODE 0xffU +#define V_WR_SENDPATH_ERROR_OPCODE(x) ((x) << S_WR_SENDPATH_ERROR_OPCODE) +#define G_WR_SENDPATH_ERROR_OPCODE(x) (((x) >> S_WR_SENDPATH_ERROR_OPCODE) & M_WR_SENDPATH_ERROR_OPCODE) + +#define S_WR_SENDPATH_OPCODE 8 +#define M_WR_SENDPATH_OPCODE 0xffU +#define V_WR_SENDPATH_OPCODE(x) ((x) << S_WR_SENDPATH_OPCODE) +#define G_WR_SENDPATH_OPCODE(x) (((x) >> S_WR_SENDPATH_OPCODE) & M_WR_SENDPATH_OPCODE) + #define A_SGE_PERR_INJECT 0x1020 #define S_MEMSEL 1 @@ -941,6 +1126,22 @@ #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ) #define F_PERR_PC_REQ V_PERR_PC_REQ(1U) +#define S_PERR_HEADERSPLIT_FIFO3 28 +#define V_PERR_HEADERSPLIT_FIFO3(x) ((x) << S_PERR_HEADERSPLIT_FIFO3) +#define F_PERR_HEADERSPLIT_FIFO3 V_PERR_HEADERSPLIT_FIFO3(1U) + +#define S_PERR_HEADERSPLIT_FIFO2 27 +#define V_PERR_HEADERSPLIT_FIFO2(x) ((x) << S_PERR_HEADERSPLIT_FIFO2) +#define F_PERR_HEADERSPLIT_FIFO2 V_PERR_HEADERSPLIT_FIFO2(1U) + +#define S_PERR_PAYLOAD_FIFO3 26 +#define V_PERR_PAYLOAD_FIFO3(x) ((x) << S_PERR_PAYLOAD_FIFO3) +#define F_PERR_PAYLOAD_FIFO3 V_PERR_PAYLOAD_FIFO3(1U) + +#define S_PERR_PAYLOAD_FIFO2 25 +#define V_PERR_PAYLOAD_FIFO2(x) ((x) << S_PERR_PAYLOAD_FIFO2) +#define F_PERR_PAYLOAD_FIFO2 V_PERR_PAYLOAD_FIFO2(1U) + #define A_SGE_INT_ENABLE1 0x1028 #define A_SGE_PERR_ENABLE1 0x102c #define A_SGE_INT_CAUSE2 0x1030 @@ -1105,6 +1306,22 @@ #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO) #define F_PERR_DB_FIFO V_PERR_DB_FIFO(1U) +#define S_TF_FIFO_PERR 24 +#define V_TF_FIFO_PERR(x) ((x) << S_TF_FIFO_PERR) +#define F_TF_FIFO_PERR V_TF_FIFO_PERR(1U) + +#define S_PERR_ISW_IDMA3_FIFO 15 +#define V_PERR_ISW_IDMA3_FIFO(x) ((x) << S_PERR_ISW_IDMA3_FIFO) +#define F_PERR_ISW_IDMA3_FIFO V_PERR_ISW_IDMA3_FIFO(1U) + +#define S_PERR_ISW_IDMA2_FIFO 13 +#define V_PERR_ISW_IDMA2_FIFO(x) ((x) << S_PERR_ISW_IDMA2_FIFO) +#define F_PERR_ISW_IDMA2_FIFO V_PERR_ISW_IDMA2_FIFO(1U) + +#define S_SGE_IPP_FIFO_PERR 5 +#define V_SGE_IPP_FIFO_PERR(x) ((x) << S_SGE_IPP_FIFO_PERR) +#define F_SGE_IPP_FIFO_PERR V_SGE_IPP_FIFO_PERR(1U) + #define A_SGE_INT_ENABLE2 0x1034 #define A_SGE_PERR_ENABLE2 0x1038 #define A_SGE_INT_CAUSE3 0x103c @@ -1259,110 +1476,20 @@ #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) #define A_SGE_FL_BUFFER_SIZE1 0x1048 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE2 0x104c - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE3 0x1050 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE4 0x1054 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE5 0x1058 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE6 0x105c - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE7 0x1060 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE8 0x1064 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE9 0x1068 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE10 0x106c - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE11 0x1070 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE12 0x1074 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE13 0x1078 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE14 0x107c - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_FL_BUFFER_SIZE15 0x1080 - -#define S_T6_SIZE 4 -#define M_T6_SIZE 0xfffffU -#define V_T6_SIZE(x) ((x) << S_T6_SIZE) -#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE) - #define A_SGE_DBQ_CTXT_BADDR 0x1084 #define S_BASEADDR 3 @@ -1426,6 +1553,10 @@ #define V_NULLPTREN(x) ((x) << S_NULLPTREN) #define F_NULLPTREN V_NULLPTREN(1U) +#define S_HDRSTARTFLQ4K 1 +#define V_HDRSTARTFLQ4K(x) ((x) << S_HDRSTARTFLQ4K) +#define F_HDRSTARTFLQ4K V_HDRSTARTFLQ4K(1U) + #define A_SGE_CONM_CTRL 0x1094 #define S_EGRTHRESHOLD 8 @@ -2243,6 +2374,34 @@ #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0) #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U) +#define S_PERR_POINTER_HDR_FIFO3 10 +#define V_PERR_POINTER_HDR_FIFO3(x) ((x) << S_PERR_POINTER_HDR_FIFO3) +#define F_PERR_POINTER_HDR_FIFO3 V_PERR_POINTER_HDR_FIFO3(1U) + +#define S_PERR_POINTER_HDR_FIFO2 9 +#define V_PERR_POINTER_HDR_FIFO2(x) ((x) << S_PERR_POINTER_HDR_FIFO2) +#define F_PERR_POINTER_HDR_FIFO2 V_PERR_POINTER_HDR_FIFO2(1U) + +#define S_PERR_POINTER_DATA_FIFO3 8 +#define V_PERR_POINTER_DATA_FIFO3(x) ((x) << S_PERR_POINTER_DATA_FIFO3) +#define F_PERR_POINTER_DATA_FIFO3 V_PERR_POINTER_DATA_FIFO3(1U) + +#define S_PERR_POINTER_DATA_FIFO2 7 +#define V_PERR_POINTER_DATA_FIFO2(x) ((x) << S_PERR_POINTER_DATA_FIFO2) +#define F_PERR_POINTER_DATA_FIFO2 V_PERR_POINTER_DATA_FIFO2(1U) + +#define S_PERR_IDMA2IMSG_FIFO3 3 +#define V_PERR_IDMA2IMSG_FIFO3(x) ((x) << S_PERR_IDMA2IMSG_FIFO3) +#define F_PERR_IDMA2IMSG_FIFO3 V_PERR_IDMA2IMSG_FIFO3(1U) + +#define S_PERR_IDMA2IMSG_FIFO2 2 +#define V_PERR_IDMA2IMSG_FIFO2(x) ((x) << S_PERR_IDMA2IMSG_FIFO2) +#define F_PERR_IDMA2IMSG_FIFO2 V_PERR_IDMA2IMSG_FIFO2(1U) + +#define S_PERR_HINT_DELAY_FIFO 0 +#define V_PERR_HINT_DELAY_FIFO(x) ((x) << S_PERR_HINT_DELAY_FIFO) +#define F_PERR_HINT_DELAY_FIFO V_PERR_HINT_DELAY_FIFO(1U) + #define A_SGE_INT_ENABLE5 0x1110 #define A_SGE_PERR_ENABLE5 0x1114 #define A_SGE_DBFIFO_STATUS2 0x1118 @@ -2359,6 +2518,46 @@ #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI) #define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U) +#define S_HINT_SGE_SEL 31 +#define V_HINT_SGE_SEL(x) ((x) << S_HINT_SGE_SEL) +#define F_HINT_SGE_SEL V_HINT_SGE_SEL(1U) + +#define S_HINT_SEL 30 +#define V_HINT_SEL(x) ((x) << S_HINT_SEL) +#define F_HINT_SEL V_HINT_SEL(1U) + +#define S_HINT_DISABLE 29 +#define V_HINT_DISABLE(x) ((x) << S_HINT_DISABLE) +#define F_HINT_DISABLE V_HINT_DISABLE(1U) + +#define S_RXCPLMODE_ISCSI 28 +#define V_RXCPLMODE_ISCSI(x) ((x) << S_RXCPLMODE_ISCSI) +#define F_RXCPLMODE_ISCSI V_RXCPLMODE_ISCSI(1U) + +#define S_RXCPLMODE_NVMT 27 +#define V_RXCPLMODE_NVMT(x) ((x) << S_RXCPLMODE_NVMT) +#define F_RXCPLMODE_NVMT V_RXCPLMODE_NVMT(1U) + +#define S_WRE_REPLAY_INORDER 26 +#define V_WRE_REPLAY_INORDER(x) ((x) << S_WRE_REPLAY_INORDER) +#define F_WRE_REPLAY_INORDER V_WRE_REPLAY_INORDER(1U) + +#define S_ETH2XEN 25 +#define V_ETH2XEN(x) ((x) << S_ETH2XEN) +#define F_ETH2XEN V_ETH2XEN(1U) + +#define S_ARMDBENDDIS 24 +#define V_ARMDBENDDIS(x) ((x) << S_ARMDBENDDIS) +#define F_ARMDBENDDIS V_ARMDBENDDIS(1U) + +#define S_PACKPADT7 23 +#define V_PACKPADT7(x) ((x) << S_PACKPADT7) +#define F_PACKPADT7 V_PACKPADT7(1U) + +#define S_WRE_UPFLCREDIT 22 +#define V_WRE_UPFLCREDIT(x) ((x) << S_WRE_UPFLCREDIT) +#define F_WRE_UPFLCREDIT V_WRE_UPFLCREDIT(1U) + #define A_SGE_DEEP_SLEEP 0x1128 #define S_IDMA1_SLEEP_STATUS 11 @@ -2493,6 +2692,42 @@ #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ) #define F_FATAL_DEQ V_FATAL_DEQ(1U) +#define S_FATAL_DEQ0_DRDY 29 +#define M_FATAL_DEQ0_DRDY 0x7U +#define V_FATAL_DEQ0_DRDY(x) ((x) << S_FATAL_DEQ0_DRDY) +#define G_FATAL_DEQ0_DRDY(x) (((x) >> S_FATAL_DEQ0_DRDY) & M_FATAL_DEQ0_DRDY) + +#define S_FATAL_OUT0_DRDY 26 +#define M_FATAL_OUT0_DRDY 0x7U +#define V_FATAL_OUT0_DRDY(x) ((x) << S_FATAL_OUT0_DRDY) +#define G_FATAL_OUT0_DRDY(x) (((x) >> S_FATAL_OUT0_DRDY) & M_FATAL_OUT0_DRDY) + +#define S_IMSG_DBG3_STUCK 25 +#define V_IMSG_DBG3_STUCK(x) ((x) << S_IMSG_DBG3_STUCK) +#define F_IMSG_DBG3_STUCK V_IMSG_DBG3_STUCK(1U) + +#define S_IMSG_DBG2_STUCK 24 +#define V_IMSG_DBG2_STUCK(x) ((x) << S_IMSG_DBG2_STUCK) +#define F_IMSG_DBG2_STUCK V_IMSG_DBG2_STUCK(1U) + +#define S_IMSG_DBG1_STUCK 23 +#define V_IMSG_DBG1_STUCK(x) ((x) << S_IMSG_DBG1_STUCK) +#define F_IMSG_DBG1_STUCK V_IMSG_DBG1_STUCK(1U) + +#define S_IMSG_DBG0_STUCK 22 +#define V_IMSG_DBG0_STUCK(x) ((x) << S_IMSG_DBG0_STUCK) +#define F_IMSG_DBG0_STUCK V_IMSG_DBG0_STUCK(1U) + +#define S_FATAL_DEQ1_DRDY 3 +#define M_FATAL_DEQ1_DRDY 0x3U +#define V_FATAL_DEQ1_DRDY(x) ((x) << S_FATAL_DEQ1_DRDY) +#define G_FATAL_DEQ1_DRDY(x) (((x) >> S_FATAL_DEQ1_DRDY) & M_FATAL_DEQ1_DRDY) + +#define S_FATAL_OUT1_DRDY 1 +#define M_FATAL_OUT1_DRDY 0x3U +#define V_FATAL_OUT1_DRDY(x) ((x) << S_FATAL_OUT1_DRDY) +#define G_FATAL_OUT1_DRDY(x) (((x) >> S_FATAL_OUT1_DRDY) & M_FATAL_OUT1_DRDY) + #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c #define S_THROTTLE_THRESHOLD_FL 16 @@ -2612,6 +2847,55 @@ #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0) #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0) +#define A_SGE_TBUF_CONTROL0 0x114c +#define A_SGE_TBUF_CONTROL1 0x1150 + +#define S_DBPTBUFRSV3 9 +#define M_DBPTBUFRSV3 0x1ffU +#define V_DBPTBUFRSV3(x) ((x) << S_DBPTBUFRSV3) +#define G_DBPTBUFRSV3(x) (((x) >> S_DBPTBUFRSV3) & M_DBPTBUFRSV3) + +#define S_DBPTBUFRSV2 0 +#define M_DBPTBUFRSV2 0x1ffU +#define V_DBPTBUFRSV2(x) ((x) << S_DBPTBUFRSV2) +#define G_DBPTBUFRSV2(x) (((x) >> S_DBPTBUFRSV2) & M_DBPTBUFRSV2) + +#define A_SGE_TBUF_CONTROL2 0x1154 + +#define S_DBPTBUFRSV5 9 +#define M_DBPTBUFRSV5 0x1ffU +#define V_DBPTBUFRSV5(x) ((x) << S_DBPTBUFRSV5) +#define G_DBPTBUFRSV5(x) (((x) >> S_DBPTBUFRSV5) & M_DBPTBUFRSV5) + +#define S_DBPTBUFRSV4 0 +#define M_DBPTBUFRSV4 0x1ffU +#define V_DBPTBUFRSV4(x) ((x) << S_DBPTBUFRSV4) +#define G_DBPTBUFRSV4(x) (((x) >> S_DBPTBUFRSV4) & M_DBPTBUFRSV4) + +#define A_SGE_TBUF_CONTROL3 0x1158 + +#define S_DBPTBUFRSV7 9 +#define M_DBPTBUFRSV7 0x1ffU +#define V_DBPTBUFRSV7(x) ((x) << S_DBPTBUFRSV7) +#define G_DBPTBUFRSV7(x) (((x) >> S_DBPTBUFRSV7) & M_DBPTBUFRSV7) + +#define S_DBPTBUFRSV6 0 +#define M_DBPTBUFRSV6 0x1ffU +#define V_DBPTBUFRSV6(x) ((x) << S_DBPTBUFRSV6) +#define G_DBPTBUFRSV6(x) (((x) >> S_DBPTBUFRSV6) & M_DBPTBUFRSV6) + +#define A_SGE_TBUF_CONTROL4 0x115c + +#define S_DBPTBUFRSV9 9 +#define M_DBPTBUFRSV9 0x1ffU +#define V_DBPTBUFRSV9(x) ((x) << S_DBPTBUFRSV9) +#define G_DBPTBUFRSV9(x) (((x) >> S_DBPTBUFRSV9) & M_DBPTBUFRSV9) + +#define S_DBPTBUFRSV8 0 +#define M_DBPTBUFRSV8 0x1ffU +#define V_DBPTBUFRSV8(x) ((x) << S_DBPTBUFRSV8) +#define G_DBPTBUFRSV8(x) (((x) >> S_DBPTBUFRSV8) & M_DBPTBUFRSV8) + #define A_SGE_PC0_REQ_BIST_CMD 0x1180 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184 #define A_SGE_PC1_REQ_BIST_CMD 0x1190 @@ -2620,6 +2904,113 @@ #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4 +#define A_SGE_DBQ_TIMER_THRESH0 0x11b8 + +#define S_TXTIMETH3 24 +#define M_TXTIMETH3 0x3fU +#define V_TXTIMETH3(x) ((x) << S_TXTIMETH3) +#define G_TXTIMETH3(x) (((x) >> S_TXTIMETH3) & M_TXTIMETH3) + +#define S_TXTIMETH2 16 +#define M_TXTIMETH2 0x3fU +#define V_TXTIMETH2(x) ((x) << S_TXTIMETH2) +#define G_TXTIMETH2(x) (((x) >> S_TXTIMETH2) & M_TXTIMETH2) + +#define S_TXTIMETH1 8 +#define M_TXTIMETH1 0x3fU +#define V_TXTIMETH1(x) ((x) << S_TXTIMETH1) +#define G_TXTIMETH1(x) (((x) >> S_TXTIMETH1) & M_TXTIMETH1) + +#define S_TXTIMETH0 0 +#define M_TXTIMETH0 0x3fU +#define V_TXTIMETH0(x) ((x) << S_TXTIMETH0) +#define G_TXTIMETH0(x) (((x) >> S_TXTIMETH0) & M_TXTIMETH0) + +#define A_SGE_DBQ_TIMER_THRESH1 0x11bc + +#define S_TXTIMETH7 24 +#define M_TXTIMETH7 0x3fU +#define V_TXTIMETH7(x) ((x) << S_TXTIMETH7) +#define G_TXTIMETH7(x) (((x) >> S_TXTIMETH7) & M_TXTIMETH7) + +#define S_TXTIMETH6 16 +#define M_TXTIMETH6 0x3fU +#define V_TXTIMETH6(x) ((x) << S_TXTIMETH6) +#define G_TXTIMETH6(x) (((x) >> S_TXTIMETH6) & M_TXTIMETH6) + +#define S_TXTIMETH5 8 +#define M_TXTIMETH5 0x3fU +#define V_TXTIMETH5(x) ((x) << S_TXTIMETH5) +#define G_TXTIMETH5(x) (((x) >> S_TXTIMETH5) & M_TXTIMETH5) + +#define S_TXTIMETH4 0 +#define M_TXTIMETH4 0x3fU +#define V_TXTIMETH4(x) ((x) << S_TXTIMETH4) +#define G_TXTIMETH4(x) (((x) >> S_TXTIMETH4) & M_TXTIMETH4) + +#define A_SGE_DBQ_TIMER_CONFIG 0x11c0 + +#define S_DBQ_TIMER_OP 0 +#define M_DBQ_TIMER_OP 0xffU +#define V_DBQ_TIMER_OP(x) ((x) << S_DBQ_TIMER_OP) +#define G_DBQ_TIMER_OP(x) (((x) >> S_DBQ_TIMER_OP) & M_DBQ_TIMER_OP) + +#define A_SGE_DBQ_TIMER_DBG 0x11c4 + +#define S_DBQ_TIMER_CMD 31 +#define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD) +#define F_DBQ_TIMER_CMD V_DBQ_TIMER_CMD(1U) + +#define S_DBQ_TIMER_INDEX 24 +#define M_DBQ_TIMER_INDEX 0x3fU +#define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX) +#define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX) + +#define S_DBQ_TIMER_QCNT 0 +#define M_DBQ_TIMER_QCNT 0x1ffffU +#define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT) +#define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT) + +#define A_SGE_INT_CAUSE8 0x11c8 + +#define S_TRACE_RXPERR 8 +#define V_TRACE_RXPERR(x) ((x) << S_TRACE_RXPERR) +#define F_TRACE_RXPERR V_TRACE_RXPERR(1U) + +#define S_U3_RXPERR 7 +#define V_U3_RXPERR(x) ((x) << S_U3_RXPERR) +#define F_U3_RXPERR V_U3_RXPERR(1U) + +#define S_U2_RXPERR 6 +#define V_U2_RXPERR(x) ((x) << S_U2_RXPERR) +#define F_U2_RXPERR V_U2_RXPERR(1U) + +#define S_U1_RXPERR 5 +#define V_U1_RXPERR(x) ((x) << S_U1_RXPERR) +#define F_U1_RXPERR V_U1_RXPERR(1U) + +#define S_U0_RXPERR 4 +#define V_U0_RXPERR(x) ((x) << S_U0_RXPERR) +#define F_U0_RXPERR V_U0_RXPERR(1U) + +#define S_T3_RXPERR 3 +#define V_T3_RXPERR(x) ((x) << S_T3_RXPERR) +#define F_T3_RXPERR V_T3_RXPERR(1U) + +#define S_T2_RXPERR 2 +#define V_T2_RXPERR(x) ((x) << S_T2_RXPERR) +#define F_T2_RXPERR V_T2_RXPERR(1U) + +#define S_T1_RXPERR 1 +#define V_T1_RXPERR(x) ((x) << S_T1_RXPERR) +#define F_T1_RXPERR V_T1_RXPERR(1U) + +#define S_T0_RXPERR 0 +#define V_T0_RXPERR(x) ((x) << S_T0_RXPERR) +#define F_T0_RXPERR V_T0_RXPERR(1U) + +#define A_SGE_INT_ENABLE8 0x11cc +#define A_SGE_PERR_ENABLE8 0x11d0 #define A_SGE_CTXT_CMD 0x11fc #define S_BUSY 31 @@ -2648,6 +3039,17 @@ #define A_SGE_CTXT_DATA4 0x1210 #define A_SGE_CTXT_DATA5 0x1214 #define A_SGE_CTXT_DATA6 0x1218 + +#define S_DATA_UNUSED 7 +#define M_DATA_UNUSED 0x1ffffffU +#define V_DATA_UNUSED(x) ((x) << S_DATA_UNUSED) +#define G_DATA_UNUSED(x) (((x) >> S_DATA_UNUSED) & M_DATA_UNUSED) + +#define S_DATA6 0 +#define M_DATA6 0x7fU +#define V_DATA6(x) ((x) << S_DATA6) +#define G_DATA6(x) (((x) >> S_DATA6) & M_DATA6) + #define A_SGE_CTXT_DATA7 0x121c #define A_SGE_CTXT_MASK0 0x1220 #define A_SGE_CTXT_MASK1 0x1224 @@ -2656,6 +3058,17 @@ #define A_SGE_CTXT_MASK4 0x1230 #define A_SGE_CTXT_MASK5 0x1234 #define A_SGE_CTXT_MASK6 0x1238 + +#define S_MASK_UNUSED 7 +#define M_MASK_UNUSED 0x1ffffffU +#define V_MASK_UNUSED(x) ((x) << S_MASK_UNUSED) +#define G_MASK_UNUSED(x) (((x) >> S_MASK_UNUSED) & M_MASK_UNUSED) + +#define S_MASK 0 +#define M_MASK 0x7fU +#define V_MASK(x) ((x) << S_MASK) +#define G_MASK(x) (((x) >> S_MASK) & M_MASK) + #define A_SGE_CTXT_MASK7 0x123c #define A_SGE_QBASE_MAP0 0x1240 @@ -2674,6 +3087,10 @@ #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE) #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE) +#define S_DESTINATION 31 +#define V_DESTINATION(x) ((x) << S_DESTINATION) +#define F_DESTINATION V_DESTINATION(1U) + #define A_SGE_QBASE_MAP1 0x1244 #define S_EGRESS0_BASE 0 @@ -2719,6 +3136,10 @@ #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH) #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH) +#define S_CONENMIDDLE 7 +#define V_CONENMIDDLE(x) ((x) << S_CONENMIDDLE) +#define F_CONENMIDDLE V_CONENMIDDLE(1U) + #define A_SGE_DEBUG_CONM 0x1258 #define S_MPS_CH_CNG 16 @@ -2745,6 +3166,16 @@ #define V_LAST_QID(x) ((x) << S_LAST_QID) #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID) +#define S_CH_CNG 16 +#define M_CH_CNG 0xffffU +#define V_CH_CNG(x) ((x) << S_CH_CNG) +#define G_CH_CNG(x) (((x) >> S_CH_CNG) & M_CH_CNG) + +#define S_CH_SEL 14 +#define M_CH_SEL 0x3U +#define V_CH_SEL(x) ((x) << S_CH_SEL) +#define G_CH_SEL(x) (((x) >> S_CH_SEL) & M_CH_SEL) + #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c #define S_IMSG_GTS_SEL 18 @@ -2766,6 +3197,7 @@ #define A_SGE_DBG_BAR2_PKT_CNT 0x126c #define A_SGE_DBG_DB_PKT_CNT 0x1270 #define A_SGE_DBG_GTS_PKT_CNT 0x1274 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_16 0x1278 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280 #define S_CIM_WM 24 @@ -3965,6 +4397,352 @@ #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET) #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET) +#define A_SGE_DEBUG_DATA_HIGH_INDEX_17 0x1340 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_18 0x1344 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_19 0x1348 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_20 0x134c +#define A_SGE_DEBUG_DATA_HIGH_INDEX_21 0x1350 +#define A_SGE_DEBUG_DATA_LOW_INDEX_16 0x1354 +#define A_SGE_DEBUG_DATA_LOW_INDEX_17 0x1358 +#define A_SGE_DEBUG_DATA_LOW_INDEX_18 0x135c +#define A_SGE_INT_CAUSE7 0x1360 + +#define S_HINT_FIFO_FULL 25 +#define V_HINT_FIFO_FULL(x) ((x) << S_HINT_FIFO_FULL) +#define F_HINT_FIFO_FULL V_HINT_FIFO_FULL(1U) + +#define S_CERR_HINT_DELAY_FIFO 24 +#define V_CERR_HINT_DELAY_FIFO(x) ((x) << S_CERR_HINT_DELAY_FIFO) +#define F_CERR_HINT_DELAY_FIFO V_CERR_HINT_DELAY_FIFO(1U) + +#define S_COAL_TIMER_FIFO_PERR 23 +#define V_COAL_TIMER_FIFO_PERR(x) ((x) << S_COAL_TIMER_FIFO_PERR) +#define F_COAL_TIMER_FIFO_PERR V_COAL_TIMER_FIFO_PERR(1U) + +#define S_CMP_FIFO_PERR 22 +#define V_CMP_FIFO_PERR(x) ((x) << S_CMP_FIFO_PERR) +#define F_CMP_FIFO_PERR V_CMP_FIFO_PERR(1U) + +#define S_SGE_IPP_FIFO_CERR 21 +#define V_SGE_IPP_FIFO_CERR(x) ((x) << S_SGE_IPP_FIFO_CERR) +#define F_SGE_IPP_FIFO_CERR V_SGE_IPP_FIFO_CERR(1U) + +#define S_CERR_ING_CTXT_CACHE 20 +#define V_CERR_ING_CTXT_CACHE(x) ((x) << S_CERR_ING_CTXT_CACHE) +#define F_CERR_ING_CTXT_CACHE V_CERR_ING_CTXT_CACHE(1U) + +#define S_IMSG_CNTX_PERR 19 +#define V_IMSG_CNTX_PERR(x) ((x) << S_IMSG_CNTX_PERR) +#define F_IMSG_CNTX_PERR V_IMSG_CNTX_PERR(1U) + +#define S_PD_FIFO_PERR 18 +#define V_PD_FIFO_PERR(x) ((x) << S_PD_FIFO_PERR) +#define F_PD_FIFO_PERR V_PD_FIFO_PERR(1U) + +#define S_IMSG_512_FIFO_PERR 17 +#define V_IMSG_512_FIFO_PERR(x) ((x) << S_IMSG_512_FIFO_PERR) +#define F_IMSG_512_FIFO_PERR V_IMSG_512_FIFO_PERR(1U) + +#define S_CPLSW_FIFO_PERR 16 +#define V_CPLSW_FIFO_PERR(x) ((x) << S_CPLSW_FIFO_PERR) +#define F_CPLSW_FIFO_PERR V_CPLSW_FIFO_PERR(1U) + +#define S_IMSG_FIFO_PERR 15 +#define V_IMSG_FIFO_PERR(x) ((x) << S_IMSG_FIFO_PERR) +#define F_IMSG_FIFO_PERR V_IMSG_FIFO_PERR(1U) + +#define S_CERR_ITP_EVR 14 +#define V_CERR_ITP_EVR(x) ((x) << S_CERR_ITP_EVR) +#define F_CERR_ITP_EVR V_CERR_ITP_EVR(1U) + +#define S_CERR_CONM_SRAM 13 +#define V_CERR_CONM_SRAM(x) ((x) << S_CERR_CONM_SRAM) +#define F_CERR_CONM_SRAM V_CERR_CONM_SRAM(1U) + +#define S_CERR_EGR_CTXT_CACHE 12 +#define V_CERR_EGR_CTXT_CACHE(x) ((x) << S_CERR_EGR_CTXT_CACHE) +#define F_CERR_EGR_CTXT_CACHE V_CERR_EGR_CTXT_CACHE(1U) + +#define S_CERR_FLM_CNTXMEM 11 +#define V_CERR_FLM_CNTXMEM(x) ((x) << S_CERR_FLM_CNTXMEM) +#define F_CERR_FLM_CNTXMEM V_CERR_FLM_CNTXMEM(1U) + +#define S_CERR_FUNC_QBASE 10 +#define V_CERR_FUNC_QBASE(x) ((x) << S_CERR_FUNC_QBASE) +#define F_CERR_FUNC_QBASE V_CERR_FUNC_QBASE(1U) + +#define S_IMSG_CNTX_CERR 9 +#define V_IMSG_CNTX_CERR(x) ((x) << S_IMSG_CNTX_CERR) +#define F_IMSG_CNTX_CERR V_IMSG_CNTX_CERR(1U) + +#define S_PD_FIFO_CERR 8 +#define V_PD_FIFO_CERR(x) ((x) << S_PD_FIFO_CERR) +#define F_PD_FIFO_CERR V_PD_FIFO_CERR(1U) + +#define S_IMSG_512_FIFO_CERR 7 +#define V_IMSG_512_FIFO_CERR(x) ((x) << S_IMSG_512_FIFO_CERR) +#define F_IMSG_512_FIFO_CERR V_IMSG_512_FIFO_CERR(1U) + +#define S_CPLSW_FIFO_CERR 6 +#define V_CPLSW_FIFO_CERR(x) ((x) << S_CPLSW_FIFO_CERR) +#define F_CPLSW_FIFO_CERR V_CPLSW_FIFO_CERR(1U) + +#define S_IMSG_FIFO_CERR 5 +#define V_IMSG_FIFO_CERR(x) ((x) << S_IMSG_FIFO_CERR) +#define F_IMSG_FIFO_CERR V_IMSG_FIFO_CERR(1U) + +#define S_CERR_HEADERSPLIT_FIFO3 4 +#define V_CERR_HEADERSPLIT_FIFO3(x) ((x) << S_CERR_HEADERSPLIT_FIFO3) +#define F_CERR_HEADERSPLIT_FIFO3 V_CERR_HEADERSPLIT_FIFO3(1U) + +#define S_CERR_HEADERSPLIT_FIFO2 3 +#define V_CERR_HEADERSPLIT_FIFO2(x) ((x) << S_CERR_HEADERSPLIT_FIFO2) +#define F_CERR_HEADERSPLIT_FIFO2 V_CERR_HEADERSPLIT_FIFO2(1U) + +#define S_CERR_HEADERSPLIT_FIFO1 2 +#define V_CERR_HEADERSPLIT_FIFO1(x) ((x) << S_CERR_HEADERSPLIT_FIFO1) +#define F_CERR_HEADERSPLIT_FIFO1 V_CERR_HEADERSPLIT_FIFO1(1U) + +#define S_CERR_HEADERSPLIT_FIFO0 1 +#define V_CERR_HEADERSPLIT_FIFO0(x) ((x) << S_CERR_HEADERSPLIT_FIFO0) +#define F_CERR_HEADERSPLIT_FIFO0 V_CERR_HEADERSPLIT_FIFO0(1U) + +#define S_CERR_FLM_L1CACHE 0 +#define V_CERR_FLM_L1CACHE(x) ((x) << S_CERR_FLM_L1CACHE) +#define F_CERR_FLM_L1CACHE V_CERR_FLM_L1CACHE(1U) + +#define A_SGE_INT_ENABLE7 0x1364 +#define A_SGE_PERR_ENABLE7 0x1368 +#define A_SGE_ING_COMP_COAL_CFG 0x1700 + +#define S_USE_PTP_TIMER 27 +#define V_USE_PTP_TIMER(x) ((x) << S_USE_PTP_TIMER) +#define F_USE_PTP_TIMER V_USE_PTP_TIMER(1U) + +#define S_IMSG_SET_OFLOW_ALL_ENTRIES_43060 26 +#define V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(x) ((x) << S_IMSG_SET_OFLOW_ALL_ENTRIES_43060) +#define F_IMSG_SET_OFLOW_ALL_ENTRIES_43060 V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(1U) + +#define S_IMSG_STUCK_INDIRECT_QUEUE_42907 25 +#define V_IMSG_STUCK_INDIRECT_QUEUE_42907(x) ((x) << S_IMSG_STUCK_INDIRECT_QUEUE_42907) +#define F_IMSG_STUCK_INDIRECT_QUEUE_42907 V_IMSG_STUCK_INDIRECT_QUEUE_42907(1U) + +#define S_COMP_COAL_PIDX_INCR 24 +#define V_COMP_COAL_PIDX_INCR(x) ((x) << S_COMP_COAL_PIDX_INCR) +#define F_COMP_COAL_PIDX_INCR V_COMP_COAL_PIDX_INCR(1U) + +#define S_COMP_COAL_TIMER_CNT 16 +#define M_COMP_COAL_TIMER_CNT 0xffU +#define V_COMP_COAL_TIMER_CNT(x) ((x) << S_COMP_COAL_TIMER_CNT) +#define G_COMP_COAL_TIMER_CNT(x) (((x) >> S_COMP_COAL_TIMER_CNT) & M_COMP_COAL_TIMER_CNT) + +#define S_COMP_COAL_CNTR_TH 8 +#define M_COMP_COAL_CNTR_TH 0xffU +#define V_COMP_COAL_CNTR_TH(x) ((x) << S_COMP_COAL_CNTR_TH) +#define G_COMP_COAL_CNTR_TH(x) (((x) >> S_COMP_COAL_CNTR_TH) & M_COMP_COAL_CNTR_TH) + +#define S_COMP_COAL_OPCODE 0 +#define M_COMP_COAL_OPCODE 0xffU +#define V_COMP_COAL_OPCODE(x) ((x) << S_COMP_COAL_OPCODE) +#define G_COMP_COAL_OPCODE(x) (((x) >> S_COMP_COAL_OPCODE) & M_COMP_COAL_OPCODE) + +#define A_SGE_ING_IMSG_DBG 0x1704 + +#define S_STUCK_CTR_TH 1 +#define M_STUCK_CTR_TH 0xffU +#define V_STUCK_CTR_TH(x) ((x) << S_STUCK_CTR_TH) +#define G_STUCK_CTR_TH(x) (((x) >> S_STUCK_CTR_TH) & M_STUCK_CTR_TH) + +#define S_STUCK_INT_EN 0 +#define V_STUCK_INT_EN(x) ((x) << S_STUCK_INT_EN) +#define F_STUCK_INT_EN V_STUCK_INT_EN(1U) + +#define A_SGE_ING_IMSG_RSP0_DBG 0x1708 + +#define S_IDMA1_QID 16 +#define M_IDMA1_QID 0xffffU +#define V_IDMA1_QID(x) ((x) << S_IDMA1_QID) +#define G_IDMA1_QID(x) (((x) >> S_IDMA1_QID) & M_IDMA1_QID) + +#define S_IDMA0_QID 0 +#define M_IDMA0_QID 0xffffU +#define V_IDMA0_QID(x) ((x) << S_IDMA0_QID) +#define G_IDMA0_QID(x) (((x) >> S_IDMA0_QID) & M_IDMA0_QID) + +#define A_SGE_ING_IMSG_RSP1_DBG 0x170c + +#define S_IDMA3_QID 16 +#define M_IDMA3_QID 0xffffU +#define V_IDMA3_QID(x) ((x) << S_IDMA3_QID) +#define G_IDMA3_QID(x) (((x) >> S_IDMA3_QID) & M_IDMA3_QID) + +#define S_IDMA2_QID 0 +#define M_IDMA2_QID 0xffffU +#define V_IDMA2_QID(x) ((x) << S_IDMA2_QID) +#define G_IDMA2_QID(x) (((x) >> S_IDMA2_QID) & M_IDMA2_QID) + +#define A_SGE_LB_MODE 0x1710 + +#define S_LB_MODE 0 +#define M_LB_MODE 0x3U +#define V_LB_MODE(x) ((x) << S_LB_MODE) +#define G_LB_MODE(x) (((x) >> S_LB_MODE) & M_LB_MODE) + +#define A_SGE_IMSG_QUESCENT 0x1714 + +#define S_IMSG_QUESCENT 0 +#define V_IMSG_QUESCENT(x) ((x) << S_IMSG_QUESCENT) +#define F_IMSG_QUESCENT V_IMSG_QUESCENT(1U) + +#define A_SGE_LA_CTRL 0x1718 + +#define S_LA_GLOBAL_EN 8 +#define V_LA_GLOBAL_EN(x) ((x) << S_LA_GLOBAL_EN) +#define F_LA_GLOBAL_EN V_LA_GLOBAL_EN(1U) + +#define S_PTP_TIMESTAMP_SEL 7 +#define V_PTP_TIMESTAMP_SEL(x) ((x) << S_PTP_TIMESTAMP_SEL) +#define F_PTP_TIMESTAMP_SEL V_PTP_TIMESTAMP_SEL(1U) + +#define S_CIM2SGE_ID_CHK_VLD 6 +#define V_CIM2SGE_ID_CHK_VLD(x) ((x) << S_CIM2SGE_ID_CHK_VLD) +#define F_CIM2SGE_ID_CHK_VLD V_CIM2SGE_ID_CHK_VLD(1U) + +#define S_CPLSW_ID_CHK_VLD 5 +#define V_CPLSW_ID_CHK_VLD(x) ((x) << S_CPLSW_ID_CHK_VLD) +#define F_CPLSW_ID_CHK_VLD V_CPLSW_ID_CHK_VLD(1U) + +#define S_FLM_ID_CHK_VLD 4 +#define V_FLM_ID_CHK_VLD(x) ((x) << S_FLM_ID_CHK_VLD) +#define F_FLM_ID_CHK_VLD V_FLM_ID_CHK_VLD(1U) + +#define S_IQ_DBP_ID_CHK_VLD 3 +#define V_IQ_DBP_ID_CHK_VLD(x) ((x) << S_IQ_DBP_ID_CHK_VLD) +#define F_IQ_DBP_ID_CHK_VLD V_IQ_DBP_ID_CHK_VLD(1U) + +#define S_UP_OBQ_ID_CHK_VLD 2 +#define V_UP_OBQ_ID_CHK_VLD(x) ((x) << S_UP_OBQ_ID_CHK_VLD) +#define F_UP_OBQ_ID_CHK_VLD V_UP_OBQ_ID_CHK_VLD(1U) + +#define S_CIM_ID_CHK_VLD 1 +#define V_CIM_ID_CHK_VLD(x) ((x) << S_CIM_ID_CHK_VLD) +#define F_CIM_ID_CHK_VLD V_CIM_ID_CHK_VLD(1U) + +#define S_DBP_ID_CHK_VLD 0 +#define V_DBP_ID_CHK_VLD(x) ((x) << S_DBP_ID_CHK_VLD) +#define F_DBP_ID_CHK_VLD V_DBP_ID_CHK_VLD(1U) + +#define A_SGE_LA_CTRL_EQID_LOW 0x171c + +#define S_EQ_ID_CHK_LOW 0 +#define M_EQ_ID_CHK_LOW 0x1ffffU +#define V_EQ_ID_CHK_LOW(x) ((x) << S_EQ_ID_CHK_LOW) +#define G_EQ_ID_CHK_LOW(x) (((x) >> S_EQ_ID_CHK_LOW) & M_EQ_ID_CHK_LOW) + +#define A_SGE_LA_CTRL_EQID_HIGH 0x1720 + +#define S_EQ_ID_CHK_HIGH 0 +#define M_EQ_ID_CHK_HIGH 0x1ffffU +#define V_EQ_ID_CHK_HIGH(x) ((x) << S_EQ_ID_CHK_HIGH) +#define G_EQ_ID_CHK_HIGH(x) (((x) >> S_EQ_ID_CHK_HIGH) & M_EQ_ID_CHK_HIGH) + +#define A_SGE_LA_CTRL_IQID 0x1724 + +#define S_IQ_ID_CHK_HIGH 16 +#define M_IQ_ID_CHK_HIGH 0xffffU +#define V_IQ_ID_CHK_HIGH(x) ((x) << S_IQ_ID_CHK_HIGH) +#define G_IQ_ID_CHK_HIGH(x) (((x) >> S_IQ_ID_CHK_HIGH) & M_IQ_ID_CHK_HIGH) + +#define S_IQ_ID_CHK_LOW 0 +#define M_IQ_ID_CHK_LOW 0xffffU +#define V_IQ_ID_CHK_LOW(x) ((x) << S_IQ_ID_CHK_LOW) +#define G_IQ_ID_CHK_LOW(x) (((x) >> S_IQ_ID_CHK_LOW) & M_IQ_ID_CHK_LOW) + +#define A_SGE_LA_CTRL_TID_LOW 0x1728 + +#define S_TID_CHK_LOW 0 +#define M_TID_CHK_LOW 0xffffffU +#define V_TID_CHK_LOW(x) ((x) << S_TID_CHK_LOW) +#define G_TID_CHK_LOW(x) (((x) >> S_TID_CHK_LOW) & M_TID_CHK_LOW) + +#define A_SGE_LA_CTRL_TID_HIGH 0x172c + +#define S_TID_CHK_HIGH 0 +#define M_TID_CHK_HIGH 0xffffffU +#define V_TID_CHK_HIGH(x) ((x) << S_TID_CHK_HIGH) +#define G_TID_CHK_HIGH(x) (((x) >> S_TID_CHK_HIGH) & M_TID_CHK_HIGH) + +#define A_SGE_CFG_TP_ERR 0x173c + +#define S_TP_ERR_STATUS_CH3 30 +#define M_TP_ERR_STATUS_CH3 0x3U +#define V_TP_ERR_STATUS_CH3(x) ((x) << S_TP_ERR_STATUS_CH3) +#define G_TP_ERR_STATUS_CH3(x) (((x) >> S_TP_ERR_STATUS_CH3) & M_TP_ERR_STATUS_CH3) + +#define S_TP_ERR_STATUS_CH2 28 +#define M_TP_ERR_STATUS_CH2 0x3U +#define V_TP_ERR_STATUS_CH2(x) ((x) << S_TP_ERR_STATUS_CH2) +#define G_TP_ERR_STATUS_CH2(x) (((x) >> S_TP_ERR_STATUS_CH2) & M_TP_ERR_STATUS_CH2) + +#define S_TP_ERR_STATUS_CH1 26 +#define M_TP_ERR_STATUS_CH1 0x3U +#define V_TP_ERR_STATUS_CH1(x) ((x) << S_TP_ERR_STATUS_CH1) +#define G_TP_ERR_STATUS_CH1(x) (((x) >> S_TP_ERR_STATUS_CH1) & M_TP_ERR_STATUS_CH1) + +#define S_TP_ERR_STATUS_CH0 24 +#define M_TP_ERR_STATUS_CH0 0x3U +#define V_TP_ERR_STATUS_CH0(x) ((x) << S_TP_ERR_STATUS_CH0) +#define G_TP_ERR_STATUS_CH0(x) (((x) >> S_TP_ERR_STATUS_CH0) & M_TP_ERR_STATUS_CH0) + +#define S_CPL0_SIZE 16 +#define M_CPL0_SIZE 0xffU +#define V_CPL0_SIZE(x) ((x) << S_CPL0_SIZE) +#define G_CPL0_SIZE(x) (((x) >> S_CPL0_SIZE) & M_CPL0_SIZE) + +#define S_CPL1_SIZE 8 +#define M_CPL1_SIZE 0xffU +#define V_CPL1_SIZE(x) ((x) << S_CPL1_SIZE) +#define G_CPL1_SIZE(x) (((x) >> S_CPL1_SIZE) & M_CPL1_SIZE) + +#define S_SIZE_LATCH_CLR 3 +#define V_SIZE_LATCH_CLR(x) ((x) << S_SIZE_LATCH_CLR) +#define F_SIZE_LATCH_CLR V_SIZE_LATCH_CLR(1U) + +#define S_EXT_LATCH_CLR 2 +#define V_EXT_LATCH_CLR(x) ((x) << S_EXT_LATCH_CLR) +#define F_EXT_LATCH_CLR V_EXT_LATCH_CLR(1U) + +#define S_EXT_CHANGE_42875 1 +#define V_EXT_CHANGE_42875(x) ((x) << S_EXT_CHANGE_42875) +#define F_EXT_CHANGE_42875 V_EXT_CHANGE_42875(1U) + +#define S_SIZE_CHANGE_42913 0 +#define V_SIZE_CHANGE_42913(x) ((x) << S_SIZE_CHANGE_42913) +#define F_SIZE_CHANGE_42913 V_SIZE_CHANGE_42913(1U) + +#define A_SGE_CHNL0_CTX_ERROR_COUNT_PER_TID 0x1740 +#define A_SGE_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1744 +#define A_SGE_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1748 +#define A_SGE_CHNL3_CTX_ERROR_COUNT_PER_TID 0x174c +#define A_SGE_CTX_ACC_CH0 0x1750 + +#define S_RDMA_INV_HANDLING 24 +#define M_RDMA_INV_HANDLING 0x3U +#define V_RDMA_INV_HANDLING(x) ((x) << S_RDMA_INV_HANDLING) +#define G_RDMA_INV_HANDLING(x) (((x) >> S_RDMA_INV_HANDLING) & M_RDMA_INV_HANDLING) + +#define S_T7_TERMINATE_STATUS_EN 23 +#define V_T7_TERMINATE_STATUS_EN(x) ((x) << S_T7_TERMINATE_STATUS_EN) +#define F_T7_TERMINATE_STATUS_EN V_T7_TERMINATE_STATUS_EN(1U) + +#define S_T7_DISABLE 22 +#define V_T7_DISABLE(x) ((x) << S_T7_DISABLE) +#define F_T7_DISABLE V_T7_DISABLE(1U) + +#define A_SGE_CTX_ACC_CH1 0x1754 +#define A_SGE_CTX_ACC_CH2 0x1758 +#define A_SGE_CTX_ACC_CH3 0x175c +#define A_SGE_CTX_BASE 0x1760 #define A_SGE_LA_RDPTR_0 0x1800 #define A_SGE_LA_RDDATA_0 0x1804 #define A_SGE_LA_WRPTR_0 0x1808 @@ -4296,6 +5074,11 @@ #define A_PCIE_INT_CAUSE 0x3004 #define A_PCIE_PERR_ENABLE 0x3008 + +#define S_TGTTAGQCLIENT1PERR 29 +#define V_TGTTAGQCLIENT1PERR(x) ((x) << S_TGTTAGQCLIENT1PERR) +#define F_TGTTAGQCLIENT1PERR V_TGTTAGQCLIENT1PERR(1U) + #define A_PCIE_PERR_INJECT 0x300c #define S_IDE 0 @@ -4582,10 +5365,6 @@ #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE) #define F_LINKREQRSTPCIECRSTMODE V_LINKREQRSTPCIECRSTMODE(1U) -#define S_T6_PIOSTOPEN 31 -#define V_T6_PIOSTOPEN(x) ((x) << S_T6_PIOSTOPEN) -#define F_T6_PIOSTOPEN V_T6_PIOSTOPEN(1U) - #define A_PCIE_DMA_CTRL 0x3018 #define S_LITTLEENDIAN 7 @@ -4618,6 +5397,14 @@ #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG) #define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG) +#define S_REG_VDM_ONLY 17 +#define V_REG_VDM_ONLY(x) ((x) << S_REG_VDM_ONLY) +#define F_REG_VDM_ONLY V_REG_VDM_ONLY(1U) + +#define S_MULT_REQID_SUP 16 +#define V_MULT_REQID_SUP(x) ((x) << S_MULT_REQID_SUP) +#define F_MULT_REQID_SUP V_MULT_REQID_SUP(1U) + #define A_PCIE_DMA_CFG 0x301c #define S_MAXPYLDSIZE 28 @@ -4668,6 +5455,10 @@ #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY) #define F_DMADCASTFIRSTONLY V_DMADCASTFIRSTONLY(1U) +#define S_ARMDCASTFIRSTONLY 7 +#define V_ARMDCASTFIRSTONLY(x) ((x) << S_ARMDCASTFIRSTONLY) +#define F_ARMDCASTFIRSTONLY V_ARMDCASTFIRSTONLY(1U) + #define A_PCIE_DMA_STAT 0x3020 #define S_STATEREQ 28 @@ -4748,7 +5539,157 @@ #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER) #define A_PCIE_CFG7 0x302c +#define A_PCIE_INT_ENABLE_EXT 0x3030 + +#define S_TCAMRSPERR 31 +#define V_TCAMRSPERR(x) ((x) << S_TCAMRSPERR) +#define F_TCAMRSPERR V_TCAMRSPERR(1U) + +#define S_IPFORMQPERR 30 +#define V_IPFORMQPERR(x) ((x) << S_IPFORMQPERR) +#define F_IPFORMQPERR V_IPFORMQPERR(1U) + +#define S_IPFORMQCERR 29 +#define V_IPFORMQCERR(x) ((x) << S_IPFORMQCERR) +#define F_IPFORMQCERR V_IPFORMQCERR(1U) + +#define S_TRGT1GRPCERR 28 +#define V_TRGT1GRPCERR(x) ((x) << S_TRGT1GRPCERR) +#define F_TRGT1GRPCERR V_TRGT1GRPCERR(1U) + +#define S_IPSOTCERR 27 +#define V_IPSOTCERR(x) ((x) << S_IPSOTCERR) +#define F_IPSOTCERR V_IPSOTCERR(1U) + +#define S_IPRETRYCERR 26 +#define V_IPRETRYCERR(x) ((x) << S_IPRETRYCERR) +#define F_IPRETRYCERR V_IPRETRYCERR(1U) + +#define S_IPRXDATAGRPCERR 25 +#define V_IPRXDATAGRPCERR(x) ((x) << S_IPRXDATAGRPCERR) +#define F_IPRXDATAGRPCERR V_IPRXDATAGRPCERR(1U) + +#define S_IPRXHDRGRPCERR 24 +#define V_IPRXHDRGRPCERR(x) ((x) << S_IPRXHDRGRPCERR) +#define F_IPRXHDRGRPCERR V_IPRXHDRGRPCERR(1U) + +#define S_A0ARBRSPORDFIFOPERR 19 +#define V_A0ARBRSPORDFIFOPERR(x) ((x) << S_A0ARBRSPORDFIFOPERR) +#define F_A0ARBRSPORDFIFOPERR V_A0ARBRSPORDFIFOPERR(1U) + +#define S_HRSPCERR 18 +#define V_HRSPCERR(x) ((x) << S_HRSPCERR) +#define F_HRSPCERR V_HRSPCERR(1U) + +#define S_HREQRDCERR 17 +#define V_HREQRDCERR(x) ((x) << S_HREQRDCERR) +#define F_HREQRDCERR V_HREQRDCERR(1U) + +#define S_HREQWRCERR 16 +#define V_HREQWRCERR(x) ((x) << S_HREQWRCERR) +#define F_HREQWRCERR V_HREQWRCERR(1U) + +#define S_DRSPCERR 15 +#define V_DRSPCERR(x) ((x) << S_DRSPCERR) +#define F_DRSPCERR V_DRSPCERR(1U) + +#define S_DREQRDCERR 14 +#define V_DREQRDCERR(x) ((x) << S_DREQRDCERR) +#define F_DREQRDCERR V_DREQRDCERR(1U) + +#define S_DREQWRCERR 13 +#define V_DREQWRCERR(x) ((x) << S_DREQWRCERR) +#define F_DREQWRCERR V_DREQWRCERR(1U) + +#define S_CRSPCERR 12 +#define V_CRSPCERR(x) ((x) << S_CRSPCERR) +#define F_CRSPCERR V_CRSPCERR(1U) + +#define S_ARSPPERR 11 +#define V_ARSPPERR(x) ((x) << S_ARSPPERR) +#define F_ARSPPERR V_ARSPPERR(1U) + +#define S_AREQRDPERR 10 +#define V_AREQRDPERR(x) ((x) << S_AREQRDPERR) +#define F_AREQRDPERR V_AREQRDPERR(1U) + +#define S_AREQWRPERR 9 +#define V_AREQWRPERR(x) ((x) << S_AREQWRPERR) +#define F_AREQWRPERR V_AREQWRPERR(1U) + +#define S_PIOREQGRPCERR 8 +#define V_PIOREQGRPCERR(x) ((x) << S_PIOREQGRPCERR) +#define F_PIOREQGRPCERR V_PIOREQGRPCERR(1U) + +#define S_ARSPCERR 7 +#define V_ARSPCERR(x) ((x) << S_ARSPCERR) +#define F_ARSPCERR V_ARSPCERR(1U) + +#define S_AREQRDCERR 6 +#define V_AREQRDCERR(x) ((x) << S_AREQRDCERR) +#define F_AREQRDCERR V_AREQRDCERR(1U) + +#define S_AREQWRCERR 5 +#define V_AREQWRCERR(x) ((x) << S_AREQWRCERR) +#define F_AREQWRCERR V_AREQWRCERR(1U) + +#define S_MARSPPERR 4 +#define V_MARSPPERR(x) ((x) << S_MARSPPERR) +#define F_MARSPPERR V_MARSPPERR(1U) + +#define S_INICMAWDATAORDPERR 3 +#define V_INICMAWDATAORDPERR(x) ((x) << S_INICMAWDATAORDPERR) +#define F_INICMAWDATAORDPERR V_INICMAWDATAORDPERR(1U) + +#define S_EMUPERR 2 +#define V_EMUPERR(x) ((x) << S_EMUPERR) +#define F_EMUPERR V_EMUPERR(1U) + +#define S_ERRSPPERR 1 +#define V_ERRSPPERR(x) ((x) << S_ERRSPPERR) +#define F_ERRSPPERR V_ERRSPPERR(1U) + +#define S_MSTGRPCERR 0 +#define V_MSTGRPCERR(x) ((x) << S_MSTGRPCERR) +#define F_MSTGRPCERR V_MSTGRPCERR(1U) + +#define A_PCIE_INT_ENABLE_X8 0x3034 + +#define S_X8TGTGRPPERR 23 +#define V_X8TGTGRPPERR(x) ((x) << S_X8TGTGRPPERR) +#define F_X8TGTGRPPERR V_X8TGTGRPPERR(1U) + +#define S_X8IPSOTPERR 22 +#define V_X8IPSOTPERR(x) ((x) << S_X8IPSOTPERR) +#define F_X8IPSOTPERR V_X8IPSOTPERR(1U) + +#define S_X8IPRETRYPERR 21 +#define V_X8IPRETRYPERR(x) ((x) << S_X8IPRETRYPERR) +#define F_X8IPRETRYPERR V_X8IPRETRYPERR(1U) + +#define S_X8IPRXDATAGRPPERR 20 +#define V_X8IPRXDATAGRPPERR(x) ((x) << S_X8IPRXDATAGRPPERR) +#define F_X8IPRXDATAGRPPERR V_X8IPRXDATAGRPPERR(1U) + +#define S_X8IPRXHDRGRPPERR 19 +#define V_X8IPRXHDRGRPPERR(x) ((x) << S_X8IPRXHDRGRPPERR) +#define F_X8IPRXHDRGRPPERR V_X8IPRXHDRGRPPERR(1U) + +#define S_X8IPCORECERR 3 +#define V_X8IPCORECERR(x) ((x) << S_X8IPCORECERR) +#define F_X8IPCORECERR V_X8IPCORECERR(1U) + +#define S_X8MSTGRPPERR 2 +#define V_X8MSTGRPPERR(x) ((x) << S_X8MSTGRPPERR) +#define F_X8MSTGRPPERR V_X8MSTGRPPERR(1U) + +#define S_X8MSTGRPCERR 1 +#define V_X8MSTGRPCERR(x) ((x) << S_X8MSTGRPCERR) +#define F_X8MSTGRPCERR V_X8MSTGRPCERR(1U) + +#define A_PCIE_INT_CAUSE_EXT 0x3038 #define A_PCIE_CMD_CTRL 0x303c +#define A_PCIE_INT_CAUSE_X8 0x303c #define A_PCIE_CMD_CFG 0x3040 #define S_MAXRSPCNT 16 @@ -4761,6 +5702,40 @@ #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT) #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT) +#define A_PCIE_PERR_ENABLE_EXT 0x3040 + +#define S_T7_ARSPPERR 18 +#define V_T7_ARSPPERR(x) ((x) << S_T7_ARSPPERR) +#define F_T7_ARSPPERR V_T7_ARSPPERR(1U) + +#define S_T7_AREQRDPERR 17 +#define V_T7_AREQRDPERR(x) ((x) << S_T7_AREQRDPERR) +#define F_T7_AREQRDPERR V_T7_AREQRDPERR(1U) + +#define S_T7_AREQWRPERR 16 +#define V_T7_AREQWRPERR(x) ((x) << S_T7_AREQWRPERR) +#define F_T7_AREQWRPERR V_T7_AREQWRPERR(1U) + +#define S_T7_A0ARBRSPORDFIFOPERR 15 +#define V_T7_A0ARBRSPORDFIFOPERR(x) ((x) << S_T7_A0ARBRSPORDFIFOPERR) +#define F_T7_A0ARBRSPORDFIFOPERR V_T7_A0ARBRSPORDFIFOPERR(1U) + +#define S_T7_MARSPPERR 14 +#define V_T7_MARSPPERR(x) ((x) << S_T7_MARSPPERR) +#define F_T7_MARSPPERR V_T7_MARSPPERR(1U) + +#define S_T7_INICMAWDATAORDPERR 13 +#define V_T7_INICMAWDATAORDPERR(x) ((x) << S_T7_INICMAWDATAORDPERR) +#define F_T7_INICMAWDATAORDPERR V_T7_INICMAWDATAORDPERR(1U) + +#define S_T7_EMUPERR 12 +#define V_T7_EMUPERR(x) ((x) << S_T7_EMUPERR) +#define F_T7_EMUPERR V_T7_EMUPERR(1U) + +#define S_T7_ERRSPPERR 11 +#define V_T7_ERRSPPERR(x) ((x) << S_T7_ERRSPPERR) +#define F_T7_ERRSPPERR V_T7_ERRSPPERR(1U) + #define A_PCIE_CMD_STAT 0x3044 #define S_RSPCNT 16 @@ -4773,6 +5748,32 @@ #define V_REQCNT(x) ((x) << S_REQCNT) #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT) +#define A_PCIE_PERR_ENABLE_X8 0x3044 + +#define S_T7_X8TGTGRPPERR 28 +#define V_T7_X8TGTGRPPERR(x) ((x) << S_T7_X8TGTGRPPERR) +#define F_T7_X8TGTGRPPERR V_T7_X8TGTGRPPERR(1U) + +#define S_T7_X8IPSOTPERR 27 +#define V_T7_X8IPSOTPERR(x) ((x) << S_T7_X8IPSOTPERR) +#define F_T7_X8IPSOTPERR V_T7_X8IPSOTPERR(1U) + +#define S_T7_X8IPRETRYPERR 26 +#define V_T7_X8IPRETRYPERR(x) ((x) << S_T7_X8IPRETRYPERR) +#define F_T7_X8IPRETRYPERR V_T7_X8IPRETRYPERR(1U) + +#define S_T7_X8IPRXDATAGRPPERR 25 +#define V_T7_X8IPRXDATAGRPPERR(x) ((x) << S_T7_X8IPRXDATAGRPPERR) +#define F_T7_X8IPRXDATAGRPPERR V_T7_X8IPRXDATAGRPPERR(1U) + +#define S_T7_X8IPRXHDRGRPPERR 24 +#define V_T7_X8IPRXHDRGRPPERR(x) ((x) << S_T7_X8IPRXHDRGRPPERR) +#define F_T7_X8IPRXHDRGRPPERR V_T7_X8IPRXHDRGRPPERR(1U) + +#define S_T7_X8MSTGRPPERR 0 +#define V_T7_X8MSTGRPPERR(x) ((x) << S_T7_X8MSTGRPPERR) +#define F_T7_X8MSTGRPPERR V_T7_X8MSTGRPPERR(1U) + #define A_PCIE_HMA_CTRL 0x3050 #define S_IPLTSSM 12 @@ -4889,9 +5890,9 @@ #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE) #define F_T6_ENABLE V_T6_ENABLE(1U) -#define S_T6_AI 30 -#define V_T6_AI(x) ((x) << S_T6_AI) -#define F_T6_AI V_T6_AI(1U) +#define S_T6_1_AI 30 +#define V_T6_1_AI(x) ((x) << S_T6_1_AI) +#define F_T6_1_AI V_T6_1_AI(1U) #define S_T6_CS2 29 #define V_T6_CS2(x) ((x) << S_T6_CS2) @@ -4936,6 +5937,7 @@ #define V_MEMOFST(x) ((x) << S_MEMOFST) #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST) +#define A_T7_PCIE_MAILBOX_BASE_WIN 0x30a4 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8 #define S_MBOXPCIEOFST 6 @@ -4953,7 +5955,21 @@ #define V_MBOXWIN(x) ((x) << S_MBOXWIN) #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN) +#define A_PCIE_MAILBOX_OFFSET0 0x30a8 + +#define S_MEMOFST0 3 +#define M_MEMOFST0 0x1fffffffU +#define V_MEMOFST0(x) ((x) << S_MEMOFST0) +#define G_MEMOFST0(x) (((x) >> S_MEMOFST0) & M_MEMOFST0) + #define A_PCIE_MAILBOX_OFFSET 0x30ac +#define A_PCIE_MAILBOX_OFFSET1 0x30ac + +#define S_MEMOFST1 0 +#define M_MEMOFST1 0xfU +#define V_MEMOFST1(x) ((x) << S_MEMOFST1) +#define G_MEMOFST1(x) (((x) >> S_MEMOFST1) & M_MEMOFST1) + #define A_PCIE_MA_CTRL 0x30b0 #define S_MA_TAGFREE 29 @@ -5098,6 +6114,11 @@ #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3) #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3) +#define S_T7_STATIC_SPARE3 0 +#define M_T7_STATIC_SPARE3 0x7fffU +#define V_T7_STATIC_SPARE3(x) ((x) << S_T7_STATIC_SPARE3) +#define G_T7_STATIC_SPARE3(x) (((x) >> S_T7_STATIC_SPARE3) & M_T7_STATIC_SPARE3) + #define A_PCIE_DBG_INDIR_REQ 0x30ec #define S_DBGENABLE 31 @@ -5173,6 +6194,17 @@ #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM) #define A_PCIE_PF_INT_CFG 0x3140 + +#define S_T7_VECNUM 12 +#define M_T7_VECNUM 0x7ffU +#define V_T7_VECNUM(x) ((x) << S_T7_VECNUM) +#define G_T7_VECNUM(x) (((x) >> S_T7_VECNUM) & M_T7_VECNUM) + +#define S_T7_VECBASE 0 +#define M_T7_VECBASE 0xfffU +#define V_T7_VECBASE(x) ((x) << S_T7_VECBASE) +#define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE) + #define A_PCIE_PF_INT_CFG2 0x3144 #define A_PCIE_VF_INT_CFG 0x3180 #define A_PCIE_VF_INT_CFG2 0x3184 @@ -5198,6 +6230,20 @@ #define A_PCIE_VF_MSIX_EN_1 0x35c4 #define A_PCIE_VF_MSIX_EN_2 0x35c8 #define A_PCIE_VF_MSIX_EN_3 0x35cc +#define A_PCIE_FID_PASID 0x35e0 +#define A_PCIE_FID_VFID_CTL 0x35e4 + +#define S_T7_WRITE 0 +#define V_T7_WRITE(x) ((x) << S_T7_WRITE) +#define F_T7_WRITE V_T7_WRITE(1U) + +#define A_T7_PCIE_FID_VFID_SEL 0x35e8 + +#define S_T7_ADDR 2 +#define M_T7_ADDR 0x1fffU +#define V_T7_ADDR(x) ((x) << S_T7_ADDR) +#define G_T7_ADDR(x) (((x) >> S_T7_ADDR) & M_T7_ADDR) + #define A_PCIE_FID_VFID_SEL 0x35ec #define S_FID_VFID_SEL_SELECT 0 @@ -5205,6 +6251,17 @@ #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT) #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT) +#define A_T7_PCIE_FID_VFID 0x35ec + +#define S_FID_VFID_NVMEGROUPEN 29 +#define V_FID_VFID_NVMEGROUPEN(x) ((x) << S_FID_VFID_NVMEGROUPEN) +#define F_FID_VFID_NVMEGROUPEN V_FID_VFID_NVMEGROUPEN(1U) + +#define S_FID_VFID_GROUPSEL 25 +#define M_FID_VFID_GROUPSEL 0xfU +#define V_FID_VFID_GROUPSEL(x) ((x) << S_FID_VFID_GROUPSEL) +#define G_FID_VFID_GROUPSEL(x) (((x) >> S_FID_VFID_GROUPSEL) & M_FID_VFID_GROUPSEL) + #define A_PCIE_FID_VFID 0x3600 #define S_FID_VFID_SELECT 30 @@ -5264,6 +6321,227 @@ #define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF) #define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF) +#define A_PCIE_JBOF_NVME_HIGH_DW_START_ADDR 0x3600 +#define A_PCIE_JBOF_NVME_LOW_DW_START_ADDR 0x3604 +#define A_PCIE_JBOF_NVME_LENGTH 0x3608 + +#define S_NVMEDISABLE 31 +#define V_NVMEDISABLE(x) ((x) << S_NVMEDISABLE) +#define F_NVMEDISABLE V_NVMEDISABLE(1U) + +#define S_NVMELENGTH 0 +#define M_NVMELENGTH 0x3fffffffU +#define V_NVMELENGTH(x) ((x) << S_NVMELENGTH) +#define G_NVMELENGTH(x) (((x) >> S_NVMELENGTH) & M_NVMELENGTH) + +#define A_PCIE_JBOF_NVME_GROUP 0x360c + +#define S_NVMEGROUPSEL 0 +#define M_NVMEGROUPSEL 0xfU +#define V_NVMEGROUPSEL(x) ((x) << S_NVMEGROUPSEL) +#define G_NVMEGROUPSEL(x) (((x) >> S_NVMEGROUPSEL) & M_NVMEGROUPSEL) + +#define A_T7_PCIE_MEM_ACCESS_BASE_WIN 0x3700 +#define A_PCIE_MEM_ACCESS_BASE_WIN1 0x3704 + +#define S_PCIEOFST1 0 +#define M_PCIEOFST1 0xffU +#define V_PCIEOFST1(x) ((x) << S_PCIEOFST1) +#define G_PCIEOFST1(x) (((x) >> S_PCIEOFST1) & M_PCIEOFST1) + +#define A_PCIE_MEM_ACCESS_OFFSET0 0x3708 +#define A_PCIE_MEM_ACCESS_OFFSET1 0x370c +#define A_PCIE_PTM_EP_EXT_STROBE 0x3804 + +#define S_PTM_AUTO_UPDATE 1 +#define V_PTM_AUTO_UPDATE(x) ((x) << S_PTM_AUTO_UPDATE) +#define F_PTM_AUTO_UPDATE V_PTM_AUTO_UPDATE(1U) + +#define S_PTM_EXT_STROBE 0 +#define V_PTM_EXT_STROBE(x) ((x) << S_PTM_EXT_STROBE) +#define F_PTM_EXT_STROBE V_PTM_EXT_STROBE(1U) + +#define A_PCIE_PTM_EP_EXT_TIME0 0x3808 +#define A_PCIE_PTM_EP_EXT_TIME1 0x380c +#define A_PCIE_PTM_MAN_UPD_PULSE 0x3810 + +#define S_PTM_MAN_UPD_PULSE 0 +#define V_PTM_MAN_UPD_PULSE(x) ((x) << S_PTM_MAN_UPD_PULSE) +#define F_PTM_MAN_UPD_PULSE V_PTM_MAN_UPD_PULSE(1U) + +#define A_PCIE_SWAP_DATA_B2L_X16 0x3814 +#define A_PCIE_PCIE_RC_RST 0x3818 + +#define S_PERST 0 +#define V_PERST(x) ((x) << S_PERST) +#define F_PERST V_PERST(1U) + +#define A_PCIE_PCIE_LN_CLKSEL 0x3880 + +#define S_DS8_SEL 30 +#define M_DS8_SEL 0x3U +#define V_DS8_SEL(x) ((x) << S_DS8_SEL) +#define G_DS8_SEL(x) (((x) >> S_DS8_SEL) & M_DS8_SEL) + +#define S_DS7_SEL 28 +#define M_DS7_SEL 0x3U +#define V_DS7_SEL(x) ((x) << S_DS7_SEL) +#define G_DS7_SEL(x) (((x) >> S_DS7_SEL) & M_DS7_SEL) + +#define S_DS6_SEL 26 +#define M_DS6_SEL 0x3U +#define V_DS6_SEL(x) ((x) << S_DS6_SEL) +#define G_DS6_SEL(x) (((x) >> S_DS6_SEL) & M_DS6_SEL) + +#define S_DS5_SEL 24 +#define M_DS5_SEL 0x3U +#define V_DS5_SEL(x) ((x) << S_DS5_SEL) +#define G_DS5_SEL(x) (((x) >> S_DS5_SEL) & M_DS5_SEL) + +#define S_DS4_SEL 22 +#define M_DS4_SEL 0x3U +#define V_DS4_SEL(x) ((x) << S_DS4_SEL) +#define G_DS4_SEL(x) (((x) >> S_DS4_SEL) & M_DS4_SEL) + +#define S_DS3_SEL 20 +#define M_DS3_SEL 0x3U +#define V_DS3_SEL(x) ((x) << S_DS3_SEL) +#define G_DS3_SEL(x) (((x) >> S_DS3_SEL) & M_DS3_SEL) + +#define S_DS2_SEL 18 +#define M_DS2_SEL 0x3U +#define V_DS2_SEL(x) ((x) << S_DS2_SEL) +#define G_DS2_SEL(x) (((x) >> S_DS2_SEL) & M_DS2_SEL) + +#define S_DS1_SEL 16 +#define M_DS1_SEL 0x3U +#define V_DS1_SEL(x) ((x) << S_DS1_SEL) +#define G_DS1_SEL(x) (((x) >> S_DS1_SEL) & M_DS1_SEL) + +#define S_LN14_SEL 14 +#define M_LN14_SEL 0x3U +#define V_LN14_SEL(x) ((x) << S_LN14_SEL) +#define G_LN14_SEL(x) (((x) >> S_LN14_SEL) & M_LN14_SEL) + +#define S_LN12_SEL 12 +#define M_LN12_SEL 0x3U +#define V_LN12_SEL(x) ((x) << S_LN12_SEL) +#define G_LN12_SEL(x) (((x) >> S_LN12_SEL) & M_LN12_SEL) + +#define S_LN10_SEL 10 +#define M_LN10_SEL 0x3U +#define V_LN10_SEL(x) ((x) << S_LN10_SEL) +#define G_LN10_SEL(x) (((x) >> S_LN10_SEL) & M_LN10_SEL) + +#define S_LN8_SEL 8 +#define M_LN8_SEL 0x3U +#define V_LN8_SEL(x) ((x) << S_LN8_SEL) +#define G_LN8_SEL(x) (((x) >> S_LN8_SEL) & M_LN8_SEL) + +#define S_LN6_SEL 6 +#define M_LN6_SEL 0x3U +#define V_LN6_SEL(x) ((x) << S_LN6_SEL) +#define G_LN6_SEL(x) (((x) >> S_LN6_SEL) & M_LN6_SEL) + +#define S_LN4_SEL 4 +#define M_LN4_SEL 0x3U +#define V_LN4_SEL(x) ((x) << S_LN4_SEL) +#define G_LN4_SEL(x) (((x) >> S_LN4_SEL) & M_LN4_SEL) + +#define S_LN2_SEL 2 +#define M_LN2_SEL 0x3U +#define V_LN2_SEL(x) ((x) << S_LN2_SEL) +#define G_LN2_SEL(x) (((x) >> S_LN2_SEL) & M_LN2_SEL) + +#define S_LN0_SEL 0 +#define M_LN0_SEL 0x3U +#define V_LN0_SEL(x) ((x) << S_LN0_SEL) +#define G_LN0_SEL(x) (((x) >> S_LN0_SEL) & M_LN0_SEL) + +#define A_PCIE_PCIE_MSIX_EN 0x3884 + +#define S_MSIX_ENABLE 0 +#define M_MSIX_ENABLE 0xffU +#define V_MSIX_ENABLE(x) ((x) << S_MSIX_ENABLE) +#define G_MSIX_ENABLE(x) (((x) >> S_MSIX_ENABLE) & M_MSIX_ENABLE) + +#define A_PCIE_LFSR_WRCTRL 0x3888 + +#define S_WR_LFSR_CMP_DATA 16 +#define M_WR_LFSR_CMP_DATA 0xffffU +#define V_WR_LFSR_CMP_DATA(x) ((x) << S_WR_LFSR_CMP_DATA) +#define G_WR_LFSR_CMP_DATA(x) (((x) >> S_WR_LFSR_CMP_DATA) & M_WR_LFSR_CMP_DATA) + +#define S_WR_LFSR_RSVD 2 +#define M_WR_LFSR_RSVD 0x3fffU +#define V_WR_LFSR_RSVD(x) ((x) << S_WR_LFSR_RSVD) +#define G_WR_LFSR_RSVD(x) (((x) >> S_WR_LFSR_RSVD) & M_WR_LFSR_RSVD) + +#define S_WR_LFSR_EN 1 +#define V_WR_LFSR_EN(x) ((x) << S_WR_LFSR_EN) +#define F_WR_LFSR_EN V_WR_LFSR_EN(1U) + +#define S_WR_LFSR_START 0 +#define V_WR_LFSR_START(x) ((x) << S_WR_LFSR_START) +#define F_WR_LFSR_START V_WR_LFSR_START(1U) + +#define A_PCIE_LFSR_RDCTRL 0x388c + +#define S_CMD_LFSR_CMP_DATA 24 +#define M_CMD_LFSR_CMP_DATA 0xffU +#define V_CMD_LFSR_CMP_DATA(x) ((x) << S_CMD_LFSR_CMP_DATA) +#define G_CMD_LFSR_CMP_DATA(x) (((x) >> S_CMD_LFSR_CMP_DATA) & M_CMD_LFSR_CMP_DATA) + +#define S_RD_LFSR_CMD_DATA 16 +#define M_RD_LFSR_CMD_DATA 0xffU +#define V_RD_LFSR_CMD_DATA(x) ((x) << S_RD_LFSR_CMD_DATA) +#define G_RD_LFSR_CMD_DATA(x) (((x) >> S_RD_LFSR_CMD_DATA) & M_RD_LFSR_CMD_DATA) + +#define S_RD_LFSR_RSVD 10 +#define M_RD_LFSR_RSVD 0x3fU +#define V_RD_LFSR_RSVD(x) ((x) << S_RD_LFSR_RSVD) +#define G_RD_LFSR_RSVD(x) (((x) >> S_RD_LFSR_RSVD) & M_RD_LFSR_RSVD) + +#define S_RD3_LFSR_EN 9 +#define V_RD3_LFSR_EN(x) ((x) << S_RD3_LFSR_EN) +#define F_RD3_LFSR_EN V_RD3_LFSR_EN(1U) + +#define S_RD3_LFSR_START 8 +#define V_RD3_LFSR_START(x) ((x) << S_RD3_LFSR_START) +#define F_RD3_LFSR_START V_RD3_LFSR_START(1U) + +#define S_RD2_LFSR_EN 7 +#define V_RD2_LFSR_EN(x) ((x) << S_RD2_LFSR_EN) +#define F_RD2_LFSR_EN V_RD2_LFSR_EN(1U) + +#define S_RD2_LFSR_START 6 +#define V_RD2_LFSR_START(x) ((x) << S_RD2_LFSR_START) +#define F_RD2_LFSR_START V_RD2_LFSR_START(1U) + +#define S_RD1_LFSR_EN 5 +#define V_RD1_LFSR_EN(x) ((x) << S_RD1_LFSR_EN) +#define F_RD1_LFSR_EN V_RD1_LFSR_EN(1U) + +#define S_RD1_LFSR_START 4 +#define V_RD1_LFSR_START(x) ((x) << S_RD1_LFSR_START) +#define F_RD1_LFSR_START V_RD1_LFSR_START(1U) + +#define S_RD0_LFSR_EN 3 +#define V_RD0_LFSR_EN(x) ((x) << S_RD0_LFSR_EN) +#define F_RD0_LFSR_EN V_RD0_LFSR_EN(1U) + +#define S_RD0_LFSR_START 2 +#define V_RD0_LFSR_START(x) ((x) << S_RD0_LFSR_START) +#define F_RD0_LFSR_START V_RD0_LFSR_START(1U) + +#define S_CMD_LFSR_EN 1 +#define V_CMD_LFSR_EN(x) ((x) << S_CMD_LFSR_EN) +#define F_CMD_LFSR_EN V_CMD_LFSR_EN(1U) + +#define S_CMD_LFSR_START 0 +#define V_CMD_LFSR_START(x) ((x) << S_CMD_LFSR_START) +#define F_CMD_LFSR_START V_CMD_LFSR_START(1U) + #define A_PCIE_FID 0x3900 #define S_PAD 11 @@ -5280,6 +6558,309 @@ #define V_FUNC(x) ((x) << S_FUNC) #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC) +#define A_PCIE_EMU_ADDR 0x3900 + +#define S_EMU_ADDR 0 +#define M_EMU_ADDR 0x1ffU +#define V_EMU_ADDR(x) ((x) << S_EMU_ADDR) +#define G_EMU_ADDR(x) (((x) >> S_EMU_ADDR) & M_EMU_ADDR) + +#define A_PCIE_EMU_CFG 0x3904 + +#define S_EMUENABLE 16 +#define V_EMUENABLE(x) ((x) << S_EMUENABLE) +#define F_EMUENABLE V_EMUENABLE(1U) + +#define S_EMUTYPE 14 +#define M_EMUTYPE 0x3U +#define V_EMUTYPE(x) ((x) << S_EMUTYPE) +#define G_EMUTYPE(x) (((x) >> S_EMUTYPE) & M_EMUTYPE) + +#define S_BAR0TARGET 12 +#define M_BAR0TARGET 0x3U +#define V_BAR0TARGET(x) ((x) << S_BAR0TARGET) +#define G_BAR0TARGET(x) (((x) >> S_BAR0TARGET) & M_BAR0TARGET) + +#define S_BAR2TARGET 10 +#define M_BAR2TARGET 0x3U +#define V_BAR2TARGET(x) ((x) << S_BAR2TARGET) +#define G_BAR2TARGET(x) (((x) >> S_BAR2TARGET) & M_BAR2TARGET) + +#define S_BAR4TARGET 8 +#define M_BAR4TARGET 0x3U +#define V_BAR4TARGET(x) ((x) << S_BAR4TARGET) +#define G_BAR4TARGET(x) (((x) >> S_BAR4TARGET) & M_BAR4TARGET) + +#define S_RELEATIVEEMUID 0 +#define M_RELEATIVEEMUID 0xffU +#define V_RELEATIVEEMUID(x) ((x) << S_RELEATIVEEMUID) +#define G_RELEATIVEEMUID(x) (((x) >> S_RELEATIVEEMUID) & M_RELEATIVEEMUID) + +#define A_PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0 0x3910 + +#define S_T7_MEMOFST0 0 +#define M_T7_MEMOFST0 0xfffffffU +#define V_T7_MEMOFST0(x) ((x) << S_T7_MEMOFST0) +#define G_T7_MEMOFST0(x) (((x) >> S_T7_MEMOFST0) & M_T7_MEMOFST0) + +#define A_PCIE_EMUADRRMAP_MEM_CFG0_BAR0 0x3914 + +#define S_SIZE0 0 +#define M_SIZE0 0x1fU +#define V_SIZE0(x) ((x) << S_SIZE0) +#define G_SIZE0(x) (((x) >> S_SIZE0) & M_SIZE0) + +#define A_PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0 0x3918 + +#define S_T7_MEMOFST1 0 +#define M_T7_MEMOFST1 0xfffffffU +#define V_T7_MEMOFST1(x) ((x) << S_T7_MEMOFST1) +#define G_T7_MEMOFST1(x) (((x) >> S_T7_MEMOFST1) & M_T7_MEMOFST1) + +#define A_PCIE_EMUADRRMAP_MEM_CFG1_BAR0 0x391c + +#define S_SIZE1 0 +#define M_SIZE1 0x1fU +#define V_SIZE1(x) ((x) << S_SIZE1) +#define G_SIZE1(x) (((x) >> S_SIZE1) & M_SIZE1) + +#define A_PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0 0x3920 + +#define S_MEMOFST2 0 +#define M_MEMOFST2 0xfffffffU +#define V_MEMOFST2(x) ((x) << S_MEMOFST2) +#define G_MEMOFST2(x) (((x) >> S_MEMOFST2) & M_MEMOFST2) + +#define A_PCIE_EMUADRRMAP_MEM_CFG2_BAR0 0x3924 + +#define S_SIZE2 0 +#define M_SIZE2 0x1fU +#define V_SIZE2(x) ((x) << S_SIZE2) +#define G_SIZE2(x) (((x) >> S_SIZE2) & M_SIZE2) + +#define A_PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0 0x3928 + +#define S_MEMOFST3 0 +#define M_MEMOFST3 0xfffffffU +#define V_MEMOFST3(x) ((x) << S_MEMOFST3) +#define G_MEMOFST3(x) (((x) >> S_MEMOFST3) & M_MEMOFST3) + +#define A_PCIE_EMUADRRMAP_MEM_CFG3_BAR0 0x392c + +#define S_SIZE3 0 +#define M_SIZE3 0x1fU +#define V_SIZE3(x) ((x) << S_SIZE3) +#define G_SIZE3(x) (((x) >> S_SIZE3) & M_SIZE3) + +#define A_PCIE_TCAM_DATA 0x3970 +#define A_PCIE_TCAM_CTL 0x3974 + +#define S_TCAMADDR 8 +#define M_TCAMADDR 0x3ffU +#define V_TCAMADDR(x) ((x) << S_TCAMADDR) +#define G_TCAMADDR(x) (((x) >> S_TCAMADDR) & M_TCAMADDR) + +#define S_CAMEN 0 +#define V_CAMEN(x) ((x) << S_CAMEN) +#define F_CAMEN V_CAMEN(1U) + +#define A_PCIE_TCAM_DBG 0x3978 + +#define S_CBPASS 24 +#define V_CBPASS(x) ((x) << S_CBPASS) +#define F_CBPASS V_CBPASS(1U) + +#define S_CBBUSY 20 +#define V_CBBUSY(x) ((x) << S_CBBUSY) +#define F_CBBUSY V_CBBUSY(1U) + +#define S_CBSTART 17 +#define V_CBSTART(x) ((x) << S_CBSTART) +#define F_CBSTART V_CBSTART(1U) + +#define S_RSTCB 16 +#define V_RSTCB(x) ((x) << S_RSTCB) +#define F_RSTCB V_RSTCB(1U) + +#define S_TCAM_DBG_DATA 0 +#define M_TCAM_DBG_DATA 0xffffU +#define V_TCAM_DBG_DATA(x) ((x) << S_TCAM_DBG_DATA) +#define G_TCAM_DBG_DATA(x) (((x) >> S_TCAM_DBG_DATA) & M_TCAM_DBG_DATA) + +#define A_PCIE_TEST_CTRL0 0x3980 +#define A_PCIE_TEST_CTRL1 0x3984 +#define A_PCIE_TEST_CTRL2 0x3988 +#define A_PCIE_TEST_CTRL3 0x398c +#define A_PCIE_TEST_STS0 0x3990 +#define A_PCIE_TEST_STS1 0x3994 +#define A_PCIE_TEST_STS2 0x3998 +#define A_PCIE_TEST_STS3 0x399c +#define A_PCIE_X8_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x4700 +#define A_PCIE_X8_CORE_VENDOR_SPECIFIC_DLLP 0x4704 +#define A_PCIE_X8_CORE_PORT_FORCE_LINK 0x4708 +#define A_PCIE_X8_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x470c +#define A_PCIE_X8_CORE_PORT_LINK_CONTROL 0x4710 +#define A_PCIE_X8_CORE_LANE_SKEW 0x4714 +#define A_PCIE_X8_CORE_SYMBOL_NUMBER 0x4718 +#define A_PCIE_X8_CORE_SYMBOL_TIMER_FILTER_MASK1 0x471c +#define A_PCIE_X8_CORE_FILTER_MASK2 0x4720 +#define A_PCIE_X8_CORE_DEBUG_0 0x4728 +#define A_PCIE_X8_CORE_DEBUG_1 0x472c +#define A_PCIE_X8_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x4730 +#define A_PCIE_X8_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x4734 +#define A_PCIE_X8_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x4738 +#define A_PCIE_X8_CORE_QUEUE_STATUS 0x473c +#define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_1 0x4740 +#define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_2 0x4744 +#define A_PCIE_X8_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x4748 +#define A_PCIE_X8_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x474c +#define A_PCIE_X8_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x4750 +#define A_PCIE_X8_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x4754 +#define A_PCIE_X8_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x4758 +#define A_PCIE_X8_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x475c +#define A_PCIE_X8_CORE_LINK_WIDTH_SPEED_CHANGE 0x480c +#define A_PCIE_X8_CORE_PHY_STATUS 0x4810 +#define A_PCIE_X8_CORE_PHY_CONTROL 0x4814 +#define A_PCIE_X8_CORE_GEN3_CONTROL 0x4890 +#define A_PCIE_X8_CORE_GEN3_EQ_FS_LF 0x4894 +#define A_PCIE_X8_CORE_GEN3_EQ_PRESET_COEFF 0x4898 +#define A_PCIE_X8_CORE_GEN3_EQ_PRESET_INDEX 0x489c +#define A_PCIE_X8_CORE_GEN3_EQ_STATUS 0x48a4 +#define A_PCIE_X8_CORE_GEN3_EQ_CONTROL 0x48a8 +#define A_PCIE_X8_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x48ac +#define A_PCIE_X8_CORE_PIPE_CONTROL 0x48b8 +#define A_PCIE_X8_CORE_DBI_RO_WE 0x48bc +#define A_PCIE_X8_CFG_SPACE_REQ 0x48c0 +#define A_PCIE_X8_CFG_SPACE_DATA 0x48c4 +#define A_PCIE_X8_CFG_MPS_MRS 0x4900 + +#define S_MRS 3 +#define M_MRS 0x7U +#define V_MRS(x) ((x) << S_MRS) +#define G_MRS(x) (((x) >> S_MRS) & M_MRS) + +#define S_T7_MPS 0 +#define M_T7_MPS 0x7U +#define V_T7_MPS(x) ((x) << S_T7_MPS) +#define G_T7_MPS(x) (((x) >> S_T7_MPS) & M_T7_MPS) + +#define A_PCIE_X8_CFG_ATTRIBUTES 0x4904 + +#define S_T7_DCAEN 2 +#define V_T7_DCAEN(x) ((x) << S_T7_DCAEN) +#define F_T7_DCAEN V_T7_DCAEN(1U) + +#define S_DCASTFITTRAONLEN 1 +#define V_DCASTFITTRAONLEN(x) ((x) << S_DCASTFITTRAONLEN) +#define F_DCASTFITTRAONLEN V_DCASTFITTRAONLEN(1U) + +#define S_REQCTLDYNSTCLKEN 0 +#define V_REQCTLDYNSTCLKEN(x) ((x) << S_REQCTLDYNSTCLKEN) +#define F_REQCTLDYNSTCLKEN V_REQCTLDYNSTCLKEN(1U) + +#define A_PCIE_X8_CFG_LTSSM 0x4908 + +#define S_APP_LTSSM_ENABLE 0 +#define V_APP_LTSSM_ENABLE(x) ((x) << S_APP_LTSSM_ENABLE) +#define F_APP_LTSSM_ENABLE V_APP_LTSSM_ENABLE(1U) + +#define A_PCIE_ARM_REQUESTER_ID_X8 0x490c + +#define S_A1_RSVD1 24 +#define M_A1_RSVD1 0xffU +#define V_A1_RSVD1(x) ((x) << S_A1_RSVD1) +#define G_A1_RSVD1(x) (((x) >> S_A1_RSVD1) & M_A1_RSVD1) + +#define S_A1_PRIMBUSNUMBER 16 +#define M_A1_PRIMBUSNUMBER 0xffU +#define V_A1_PRIMBUSNUMBER(x) ((x) << S_A1_PRIMBUSNUMBER) +#define G_A1_PRIMBUSNUMBER(x) (((x) >> S_A1_PRIMBUSNUMBER) & M_A1_PRIMBUSNUMBER) + +#define S_A1_REQUESTERID 0 +#define M_A1_REQUESTERID 0xffffU +#define V_A1_REQUESTERID(x) ((x) << S_A1_REQUESTERID) +#define G_A1_REQUESTERID(x) (((x) >> S_A1_REQUESTERID) & M_A1_REQUESTERID) + +#define A_PCIE_SWAP_DATA_B2L_X8 0x4910 + +#define S_CFGRD_SWAP_EN 1 +#define V_CFGRD_SWAP_EN(x) ((x) << S_CFGRD_SWAP_EN) +#define F_CFGRD_SWAP_EN V_CFGRD_SWAP_EN(1U) + +#define S_CFGWR_SWAP_EN 0 +#define V_CFGWR_SWAP_EN(x) ((x) << S_CFGWR_SWAP_EN) +#define F_CFGWR_SWAP_EN V_CFGWR_SWAP_EN(1U) + +#define A_PCIE_PDEBUG_DATA0_X8 0x4914 +#define A_PCIE_PDEBUG_DATA1_X8 0x4918 +#define A_PCIE_PDEBUG_DATA2_X8 0x491c +#define A_PCIE_PDEBUG_CTRL_X8 0x4920 +#define A_PCIE_PDEBUG_DATA_X8 0x4924 +#define A_PCIE_SPARE_REGISTER_SPACES_X8 0x4ffc +#define A_PCIE_PIPE_LANE0_REG0 0x5500 +#define A_PCIE_PIPE_LANE0_REG1 0x5504 +#define A_PCIE_PIPE_LANE0_REG2 0x5508 +#define A_PCIE_PIPE_LANE0_REG3 0x550c +#define A_PCIE_PIPE_LANE1_REG0 0x5510 +#define A_PCIE_PIPE_LANE1_REG1 0x5514 +#define A_PCIE_PIPE_LANE1_REG2 0x5518 +#define A_PCIE_PIPE_LANE1_REG3 0x551c +#define A_PCIE_PIPE_LANE2_REG0 0x5520 +#define A_PCIE_PIPE_LANE2_REG1 0x5524 +#define A_PCIE_PIPE_LANE2_REG2 0x5528 +#define A_PCIE_PIPE_LANE2_REG3 0x552c +#define A_PCIE_PIPE_LANE3_REG0 0x5530 +#define A_PCIE_PIPE_LANE3_REG1 0x5534 +#define A_PCIE_PIPE_LANE3_REG2 0x5538 +#define A_PCIE_PIPE_LANE3_REG3 0x553c +#define A_PCIE_PIPE_LANE4_REG0 0x5540 +#define A_PCIE_PIPE_LANE4_REG1 0x5544 +#define A_PCIE_PIPE_LANE4_REG2 0x5548 +#define A_PCIE_PIPE_LANE4_REG3 0x554c +#define A_PCIE_PIPE_LANE5_REG0 0x5550 +#define A_PCIE_PIPE_LANE5_REG1 0x5554 +#define A_PCIE_PIPE_LANE5_REG2 0x5558 +#define A_PCIE_PIPE_LANE5_REG3 0x555c +#define A_PCIE_PIPE_LANE6_REG0 0x5560 +#define A_PCIE_PIPE_LANE6_REG1 0x5564 +#define A_PCIE_PIPE_LANE6_REG2 0x5568 +#define A_PCIE_PIPE_LANE6_REG3 0x556c +#define A_PCIE_PIPE_LANE7_REG0 0x5570 +#define A_PCIE_PIPE_LANE7_REG1 0x5574 +#define A_PCIE_PIPE_LANE7_REG2 0x5578 +#define A_PCIE_PIPE_LANE7_REG3 0x557c +#define A_PCIE_PIPE_LANE8_REG0 0x5580 +#define A_PCIE_PIPE_LANE8_REG1 0x5584 +#define A_PCIE_PIPE_LANE8_REG2 0x5588 +#define A_PCIE_PIPE_LANE8_REG3 0x558c +#define A_PCIE_PIPE_LANE9_REG0 0x5590 +#define A_PCIE_PIPE_LANE9_REG1 0x5594 +#define A_PCIE_PIPE_LANE9_REG2 0x5598 +#define A_PCIE_PIPE_LANE9_REG3 0x559c +#define A_PCIE_PIPE_LANE10_REG0 0x55a0 +#define A_PCIE_PIPE_LANE10_REG1 0x55a4 +#define A_PCIE_PIPE_LANE10_REG2 0x55a8 +#define A_PCIE_PIPE_LANE10_REG3 0x55ac +#define A_PCIE_PIPE_LANE11_REG0 0x55b0 +#define A_PCIE_PIPE_LANE11_REG1 0x55b4 +#define A_PCIE_PIPE_LANE11_REG2 0x55b8 +#define A_PCIE_PIPE_LANE11_REG3 0x55bc +#define A_PCIE_PIPE_LANE12_REG0 0x55c0 +#define A_PCIE_PIPE_LANE12_REG1 0x55c4 +#define A_PCIE_PIPE_LANE12_REG2 0x55c8 +#define A_PCIE_PIPE_LANE12_REG3 0x55cc +#define A_PCIE_PIPE_LANE13_REG0 0x55d0 +#define A_PCIE_PIPE_LANE13_REG1 0x55d4 +#define A_PCIE_PIPE_LANE13_REG2 0x55d8 +#define A_PCIE_PIPE_LANE13_REG3 0x55dc +#define A_PCIE_PIPE_LANE14_REG0 0x55e0 +#define A_PCIE_PIPE_LANE14_REG1 0x55e4 +#define A_PCIE_PIPE_LANE14_REG2 0x55e8 +#define A_PCIE_PIPE_LANE14_REG3 0x55ec +#define A_PCIE_PIPE_LANE15_REG0 0x55f0 +#define A_PCIE_PIPE_LANE15_REG1 0x55f4 +#define A_PCIE_PIPE_LANE15_REG2 0x55f8 +#define A_PCIE_PIPE_LANE15_REG3 0x55fc #define A_PCIE_COOKIE_STAT 0x5600 #define S_COOKIEB 16 @@ -5346,6 +6927,30 @@ #define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE) #define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE) +#define A_T7_PCIE_VC0_CDTS0 0x56c4 + +#define S_T7_CPLD0 16 +#define M_T7_CPLD0 0xffffU +#define V_T7_CPLD0(x) ((x) << S_T7_CPLD0) +#define G_T7_CPLD0(x) (((x) >> S_T7_CPLD0) & M_T7_CPLD0) + +#define S_T7_CPLH0 0 +#define M_T7_CPLH0 0xfffU +#define V_T7_CPLH0(x) ((x) << S_T7_CPLH0) +#define G_T7_CPLH0(x) (((x) >> S_T7_CPLH0) & M_T7_CPLH0) + +#define A_T7_PCIE_VC0_CDTS1 0x56c8 + +#define S_T7_PD0 16 +#define M_T7_PD0 0xffffU +#define V_T7_PD0(x) ((x) << S_T7_PD0) +#define G_T7_PD0(x) (((x) >> S_T7_PD0) & M_T7_PD0) + +#define S_T7_PH0 0 +#define M_T7_PH0 0xfffU +#define V_T7_PH0(x) ((x) << S_T7_PH0) +#define G_T7_PH0(x) (((x) >> S_T7_PH0) & M_T7_PH0) + #define A_PCIE_VC0_CDTS0 0x56cc #define S_CPLD0 20 @@ -5363,6 +6968,18 @@ #define V_PD0(x) ((x) << S_PD0) #define G_PD0(x) (((x) >> S_PD0) & M_PD0) +#define A_PCIE_VC0_CDTS2 0x56cc + +#define S_T7_NPD0 16 +#define M_T7_NPD0 0xffffU +#define V_T7_NPD0(x) ((x) << S_T7_NPD0) +#define G_T7_NPD0(x) (((x) >> S_T7_NPD0) & M_T7_NPD0) + +#define S_T7_NPH0 0 +#define M_T7_NPH0 0xfffU +#define V_T7_NPH0(x) ((x) << S_T7_NPH0) +#define G_T7_NPH0(x) (((x) >> S_T7_NPH0) & M_T7_NPH0) + #define A_PCIE_VC0_CDTS1 0x56d0 #define S_CPLH0 20 @@ -5380,6 +6997,7 @@ #define V_NPD0(x) ((x) << S_NPD0) #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0) +#define A_T7_PCIE_VC1_CDTS0 0x56d0 #define A_PCIE_VC1_CDTS0 0x56d4 #define S_CPLD1 20 @@ -5397,6 +7015,7 @@ #define V_PD1(x) ((x) << S_PD1) #define G_PD1(x) (((x) >> S_PD1) & M_PD1) +#define A_T7_PCIE_VC1_CDTS1 0x56d4 #define A_PCIE_VC1_CDTS1 0x56d8 #define S_CPLH1 20 @@ -5414,6 +7033,7 @@ #define V_NPD1(x) ((x) << S_NPD1) #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1) +#define A_PCIE_VC1_CDTS2 0x56d8 #define A_PCIE_FLR_PF_STATUS 0x56dc #define A_PCIE_FLR_VF0_STATUS 0x56e0 #define A_PCIE_FLR_VF1_STATUS 0x56e4 @@ -5916,6 +7536,11 @@ #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER) #define F_DISABLE_SCRAMBLER V_DISABLE_SCRAMBLER(1U) +#define S_RATE_SHADOW_SEL 24 +#define M_RATE_SHADOW_SEL 0x3U +#define V_RATE_SHADOW_SEL(x) ((x) << S_RATE_SHADOW_SEL) +#define G_RATE_SHADOW_SEL(x) (((x) >> S_RATE_SHADOW_SEL) & M_RATE_SHADOW_SEL) + #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894 #define S_FULL_SWING 6 @@ -6347,6 +7972,35 @@ #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT) #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT) +#define S_DMA_COOKIECNT 24 +#define M_DMA_COOKIECNT 0xfU +#define V_DMA_COOKIECNT(x) ((x) << S_DMA_COOKIECNT) +#define G_DMA_COOKIECNT(x) (((x) >> S_DMA_COOKIECNT) & M_DMA_COOKIECNT) + +#define S_DMA_RDSEQNUMUPDCNT 20 +#define M_DMA_RDSEQNUMUPDCNT 0xfU +#define V_DMA_RDSEQNUMUPDCNT(x) ((x) << S_DMA_RDSEQNUMUPDCNT) +#define G_DMA_RDSEQNUMUPDCNT(x) (((x) >> S_DMA_RDSEQNUMUPDCNT) & M_DMA_RDSEQNUMUPDCNT) + +#define S_DMA_SIREQCNT 16 +#define M_DMA_SIREQCNT 0xfU +#define V_DMA_SIREQCNT(x) ((x) << S_DMA_SIREQCNT) +#define G_DMA_SIREQCNT(x) (((x) >> S_DMA_SIREQCNT) & M_DMA_SIREQCNT) + +#define S_DMA_WREOPMATCHSOP 12 +#define V_DMA_WREOPMATCHSOP(x) ((x) << S_DMA_WREOPMATCHSOP) +#define F_DMA_WREOPMATCHSOP V_DMA_WREOPMATCHSOP(1U) + +#define S_DMA_WRSOPCNT 8 +#define M_DMA_WRSOPCNT 0xfU +#define V_DMA_WRSOPCNT(x) ((x) << S_DMA_WRSOPCNT) +#define G_DMA_WRSOPCNT(x) (((x) >> S_DMA_WRSOPCNT) & M_DMA_WRSOPCNT) + +#define S_DMA_RDSOPCNT 0 +#define M_DMA_RDSOPCNT 0xffU +#define V_DMA_RDSOPCNT(x) ((x) << S_DMA_RDSOPCNT) +#define G_DMA_RDSOPCNT(x) (((x) >> S_DMA_RDSOPCNT) & M_DMA_RDSOPCNT) + #define A_PCIE_T5_DMA_STAT3 0x594c #define S_ATMREQSOPCNT 24 @@ -6372,6 +8026,29 @@ #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT) #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT) +#define S_DMA_ATMREQSOPCNT 24 +#define M_DMA_ATMREQSOPCNT 0xffU +#define V_DMA_ATMREQSOPCNT(x) ((x) << S_DMA_ATMREQSOPCNT) +#define G_DMA_ATMREQSOPCNT(x) (((x) >> S_DMA_ATMREQSOPCNT) & M_DMA_ATMREQSOPCNT) + +#define S_DMA_ATMEOPMATCHSOP 17 +#define V_DMA_ATMEOPMATCHSOP(x) ((x) << S_DMA_ATMEOPMATCHSOP) +#define F_DMA_ATMEOPMATCHSOP V_DMA_ATMEOPMATCHSOP(1U) + +#define S_DMA_RSPEOPMATCHSOP 16 +#define V_DMA_RSPEOPMATCHSOP(x) ((x) << S_DMA_RSPEOPMATCHSOP) +#define F_DMA_RSPEOPMATCHSOP V_DMA_RSPEOPMATCHSOP(1U) + +#define S_DMA_RSPERRCNT 8 +#define M_DMA_RSPERRCNT 0xffU +#define V_DMA_RSPERRCNT(x) ((x) << S_DMA_RSPERRCNT) +#define G_DMA_RSPERRCNT(x) (((x) >> S_DMA_RSPERRCNT) & M_DMA_RSPERRCNT) + +#define S_DMA_RSPSOPCNT 0 +#define M_DMA_RSPSOPCNT 0xffU +#define V_DMA_RSPSOPCNT(x) ((x) << S_DMA_RSPSOPCNT) +#define G_DMA_RSPSOPCNT(x) (((x) >> S_DMA_RSPSOPCNT) & M_DMA_RSPSOPCNT) + #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960 #define S_OP0H 24 @@ -6507,11 +8184,6 @@ #define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL) #define F_T6_USECMDPOOL V_T6_USECMDPOOL(1U) -#define S_T6_MINTAG 0 -#define M_T6_MINTAG 0xffU -#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG) -#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG) - #define A_PCIE_T5_CMD_STAT 0x5984 #define S_T5_STAT_RSPCNT 20 @@ -6558,6 +8230,21 @@ #define A_PCIE_T5_CMD_STAT2 0x5988 #define A_PCIE_T5_CMD_STAT3 0x598c + +#define S_CMD_RSPEOPMATCHSOP 16 +#define V_CMD_RSPEOPMATCHSOP(x) ((x) << S_CMD_RSPEOPMATCHSOP) +#define F_CMD_RSPEOPMATCHSOP V_CMD_RSPEOPMATCHSOP(1U) + +#define S_CMD_RSPERRCNT 8 +#define M_CMD_RSPERRCNT 0xffU +#define V_CMD_RSPERRCNT(x) ((x) << S_CMD_RSPERRCNT) +#define G_CMD_RSPERRCNT(x) (((x) >> S_CMD_RSPERRCNT) & M_CMD_RSPERRCNT) + +#define S_CMD_RSPSOPCNT 0 +#define M_CMD_RSPSOPCNT 0xffU +#define V_CMD_RSPSOPCNT(x) ((x) << S_CMD_RSPSOPCNT) +#define G_CMD_RSPSOPCNT(x) (((x) >> S_CMD_RSPSOPCNT) & M_CMD_RSPSOPCNT) + #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990 #define S_OC0T 24 @@ -6868,14 +8555,14 @@ #define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT) #define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT) -#define S_T6_SEQCHKDIS 8 -#define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS) -#define F_T6_SEQCHKDIS V_T6_SEQCHKDIS(1U) +#define S_T5_HMA_SEQCHKDIS 8 +#define V_T5_HMA_SEQCHKDIS(x) ((x) << S_T5_HMA_SEQCHKDIS) +#define F_T5_HMA_SEQCHKDIS V_T5_HMA_SEQCHKDIS(1U) -#define S_T6_MINTAG 0 -#define M_T6_MINTAG 0xffU -#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG) -#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG) +#define S_T5_MINTAG 0 +#define M_T5_MINTAG 0xffU +#define V_T5_MINTAG(x) ((x) << S_T5_MINTAG) +#define G_T5_MINTAG(x) (((x) >> S_T5_MINTAG) & M_T5_MINTAG) #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4 @@ -6992,6 +8679,31 @@ #define F_CRSI V_CRSI(1U) #define A_PCIE_T5_HMA_STAT2 0x59b8 + +#define S_HMA_COOKIECNT 24 +#define M_HMA_COOKIECNT 0xfU +#define V_HMA_COOKIECNT(x) ((x) << S_HMA_COOKIECNT) +#define G_HMA_COOKIECNT(x) (((x) >> S_HMA_COOKIECNT) & M_HMA_COOKIECNT) + +#define S_HMA_RDSEQNUMUPDCNT 20 +#define M_HMA_RDSEQNUMUPDCNT 0xfU +#define V_HMA_RDSEQNUMUPDCNT(x) ((x) << S_HMA_RDSEQNUMUPDCNT) +#define G_HMA_RDSEQNUMUPDCNT(x) (((x) >> S_HMA_RDSEQNUMUPDCNT) & M_HMA_RDSEQNUMUPDCNT) + +#define S_HMA_WREOPMATCHSOP 12 +#define V_HMA_WREOPMATCHSOP(x) ((x) << S_HMA_WREOPMATCHSOP) +#define F_HMA_WREOPMATCHSOP V_HMA_WREOPMATCHSOP(1U) + +#define S_HMA_WRSOPCNT 8 +#define M_HMA_WRSOPCNT 0xfU +#define V_HMA_WRSOPCNT(x) ((x) << S_HMA_WRSOPCNT) +#define G_HMA_WRSOPCNT(x) (((x) >> S_HMA_WRSOPCNT) & M_HMA_WRSOPCNT) + +#define S_HMA_RDSOPCNT 0 +#define M_HMA_RDSOPCNT 0xffU +#define V_HMA_RDSOPCNT(x) ((x) << S_HMA_RDSOPCNT) +#define G_HMA_RDSOPCNT(x) (((x) >> S_HMA_RDSOPCNT) & M_HMA_RDSOPCNT) + #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc #define S_PTOM 31 @@ -7035,6 +8747,21 @@ #define F_PMC7 V_PMC7(1U) #define A_PCIE_T5_HMA_STAT3 0x59bc + +#define S_HMA_RSPEOPMATCHSOP 16 +#define V_HMA_RSPEOPMATCHSOP(x) ((x) << S_HMA_RSPEOPMATCHSOP) +#define F_HMA_RSPEOPMATCHSOP V_HMA_RSPEOPMATCHSOP(1U) + +#define S_HMA_RSPERRCNT 8 +#define M_HMA_RSPERRCNT 0xffU +#define V_HMA_RSPERRCNT(x) ((x) << S_HMA_RSPERRCNT) +#define G_HMA_RSPERRCNT(x) (((x) >> S_HMA_RSPERRCNT) & M_HMA_RSPERRCNT) + +#define S_HMA_RSPSOPCNT 0 +#define M_HMA_RSPSOPCNT 0xffU +#define V_HMA_RSPSOPCNT(x) ((x) << S_HMA_RSPSOPCNT) +#define G_HMA_RSPSOPCNT(x) (((x) >> S_HMA_RSPSOPCNT) & M_HMA_RSPSOPCNT) + #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0 #define S_PTOS 31 @@ -7187,6 +8914,14 @@ #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ) #define F_STI_SLEEPREQ V_STI_SLEEPREQ(1U) +#define S_ARM_STATIC_CGEN 28 +#define V_ARM_STATIC_CGEN(x) ((x) << S_ARM_STATIC_CGEN) +#define F_ARM_STATIC_CGEN V_ARM_STATIC_CGEN(1U) + +#define S_ARM_DYNAMIC_CGEN 27 +#define V_ARM_DYNAMIC_CGEN(x) ((x) << S_ARM_DYNAMIC_CGEN) +#define F_ARM_DYNAMIC_CGEN V_ARM_DYNAMIC_CGEN(1U) + #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4 #define S_PTOI 31 @@ -7521,6 +9256,14 @@ #define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR) #define F_PIOCPL_VDMTXDATAPERR V_PIOCPL_VDMTXDATAPERR(1U) +#define S_TGT1_MEM_PERR 28 +#define V_TGT1_MEM_PERR(x) ((x) << S_TGT1_MEM_PERR) +#define F_TGT1_MEM_PERR V_TGT1_MEM_PERR(1U) + +#define S_TGT2_MEM_PERR 27 +#define V_TGT2_MEM_PERR(x) ((x) << S_TGT2_MEM_PERR) +#define F_TGT2_MEM_PERR V_TGT2_MEM_PERR(1U) + #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4 @@ -7622,6 +9365,16 @@ #define V_T6_REQVFID(x) ((x) << S_T6_REQVFID) #define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID) +#define S_LOGADDR10B 9 +#define M_LOGADDR10B 0x3ffU +#define V_LOGADDR10B(x) ((x) << S_LOGADDR10B) +#define G_LOGADDR10B(x) (((x) >> S_LOGADDR10B) & M_LOGADDR10B) + +#define S_LOGREQVFID 0 +#define M_LOGREQVFID 0x1ffU +#define V_LOGREQVFID(x) ((x) << S_LOGREQVFID) +#define G_LOGREQVFID(x) (((x) >> S_LOGREQVFID) & M_LOGREQVFID) + #define A_PCIE_CHANGESET 0x59fc #define A_PCIE_REVISION 0x5a00 #define A_PCIE_PDEBUG_INDEX 0x5a04 @@ -7646,6 +9399,16 @@ #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL) #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL) +#define S_T7_1_PDEBUGSELH 16 +#define M_T7_1_PDEBUGSELH 0xffU +#define V_T7_1_PDEBUGSELH(x) ((x) << S_T7_1_PDEBUGSELH) +#define G_T7_1_PDEBUGSELH(x) (((x) >> S_T7_1_PDEBUGSELH) & M_T7_1_PDEBUGSELH) + +#define S_T7_1_PDEBUGSELL 0 +#define M_T7_1_PDEBUGSELL 0xffU +#define V_T7_1_PDEBUGSELL(x) ((x) << S_T7_1_PDEBUGSELL) +#define G_T7_1_PDEBUGSELL(x) (((x) >> S_T7_1_PDEBUGSELL) & M_T7_1_PDEBUGSELL) + #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c #define A_PCIE_CDEBUG_INDEX 0x5a10 @@ -8468,6 +10231,21 @@ #define A_PCIE_PHY_INDIR_DATA 0x5bf4 #define A_PCIE_STATIC_SPARE1 0x5bf8 #define A_PCIE_STATIC_SPARE2 0x5bfc + +#define S_X8_SW_EN 30 +#define V_X8_SW_EN(x) ((x) << S_X8_SW_EN) +#define F_X8_SW_EN V_X8_SW_EN(1U) + +#define S_SWITCHCFG 28 +#define M_SWITCHCFG 0x3U +#define V_SWITCHCFG(x) ((x) << S_SWITCHCFG) +#define G_SWITCHCFG(x) (((x) >> S_SWITCHCFG) & M_SWITCHCFG) + +#define S_STATIC_SPARE2 0 +#define M_STATIC_SPARE2 0xfffffffU +#define V_STATIC_SPARE2(x) ((x) << S_STATIC_SPARE2) +#define G_STATIC_SPARE2(x) (((x) >> S_STATIC_SPARE2) & M_STATIC_SPARE2) + #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10 #define S_KDB_PF_LEN 24 @@ -8872,9 +10650,13 @@ #define A_PCIE_FLR_VF6_STATUS 0x5e78 #define A_PCIE_FLR_VF7_STATUS 0x5e7c #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80 +#define A_T7_PCIE_BUS_MST_STAT_4 0x5e80 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84 +#define A_T7_PCIE_BUS_MST_STAT_5 0x5e84 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88 +#define A_T7_PCIE_BUS_MST_STAT_6 0x5e88 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c +#define A_T7_PCIE_BUS_MST_STAT_7 0x5e8c #define A_PCIE_BUS_MST_STAT_8 0x5e90 #define S_BUSMST_263_256 0 @@ -8895,9 +10677,13 @@ #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT) #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0 +#define A_T7_PCIE_RSP_ERR_STAT_4 0x5ea0 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4 +#define A_T7_PCIE_RSP_ERR_STAT_5 0x5ea4 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8 +#define A_T7_PCIE_RSP_ERR_STAT_6 0x5ea8 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac +#define A_T7_PCIE_RSP_ERR_STAT_7 0x5eac #define A_PCIE_RSP_ERR_STAT_8 0x5eb0 #define S_RSPERR_263_256 0 @@ -9025,6 +10811,1028 @@ #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00 +#define A_PCIE_PHY_PGM_LOAD_CTRL 0x5f04 + +#define S_HSS_PMLD_ACC_EN 31 +#define V_HSS_PMLD_ACC_EN(x) ((x) << S_HSS_PMLD_ACC_EN) +#define F_HSS_PMLD_ACC_EN V_HSS_PMLD_ACC_EN(1U) + +#define S_HSS_PMRDWR_ADDR 0 +#define M_HSS_PMRDWR_ADDR 0x3ffffU +#define V_HSS_PMRDWR_ADDR(x) ((x) << S_HSS_PMRDWR_ADDR) +#define G_HSS_PMRDWR_ADDR(x) (((x) >> S_HSS_PMRDWR_ADDR) & M_HSS_PMRDWR_ADDR) + +#define A_PCIE_PHY_PGM_LOAD_DATA 0x5f08 +#define A_PCIE_HSS_CFG 0x5f0c + +#define S_HSS_PCS_AGGREGATION_MODE 30 +#define M_HSS_PCS_AGGREGATION_MODE 0x3U +#define V_HSS_PCS_AGGREGATION_MODE(x) ((x) << S_HSS_PCS_AGGREGATION_MODE) +#define G_HSS_PCS_AGGREGATION_MODE(x) (((x) >> S_HSS_PCS_AGGREGATION_MODE) & M_HSS_PCS_AGGREGATION_MODE) + +#define S_HSS_PCS_FURCATE_MODE 28 +#define M_HSS_PCS_FURCATE_MODE 0x3U +#define V_HSS_PCS_FURCATE_MODE(x) ((x) << S_HSS_PCS_FURCATE_MODE) +#define G_HSS_PCS_FURCATE_MODE(x) (((x) >> S_HSS_PCS_FURCATE_MODE) & M_HSS_PCS_FURCATE_MODE) + +#define S_HSS_PCS_PCLK_ON_IN_P2 27 +#define V_HSS_PCS_PCLK_ON_IN_P2(x) ((x) << S_HSS_PCS_PCLK_ON_IN_P2) +#define F_HSS_PCS_PCLK_ON_IN_P2 V_HSS_PCS_PCLK_ON_IN_P2(1U) + +#define S_HSS0_PHY_CTRL_REFCLK 17 +#define M_HSS0_PHY_CTRL_REFCLK 0x1fU +#define V_HSS0_PHY_CTRL_REFCLK(x) ((x) << S_HSS0_PHY_CTRL_REFCLK) +#define G_HSS0_PHY_CTRL_REFCLK(x) (((x) >> S_HSS0_PHY_CTRL_REFCLK) & M_HSS0_PHY_CTRL_REFCLK) + +#define S_HSS1_PHY_CTRL_REFCLK 12 +#define M_HSS1_PHY_CTRL_REFCLK 0x1fU +#define V_HSS1_PHY_CTRL_REFCLK(x) ((x) << S_HSS1_PHY_CTRL_REFCLK) +#define G_HSS1_PHY_CTRL_REFCLK(x) (((x) >> S_HSS1_PHY_CTRL_REFCLK) & M_HSS1_PHY_CTRL_REFCLK) + +#define S_HSS0_PHY_REXT_MASTER 11 +#define V_HSS0_PHY_REXT_MASTER(x) ((x) << S_HSS0_PHY_REXT_MASTER) +#define F_HSS0_PHY_REXT_MASTER V_HSS0_PHY_REXT_MASTER(1U) + +#define S_HSS1_PHY_REXT_MASTER 10 +#define V_HSS1_PHY_REXT_MASTER(x) ((x) << S_HSS1_PHY_REXT_MASTER) +#define F_HSS1_PHY_REXT_MASTER V_HSS1_PHY_REXT_MASTER(1U) + +#define S_HSS0_PHY_CTRL_VDDA_SEL 9 +#define V_HSS0_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDA_SEL) +#define F_HSS0_PHY_CTRL_VDDA_SEL V_HSS0_PHY_CTRL_VDDA_SEL(1U) + +#define S_HSS0_PHY_CTRL_VDDHA_SEL 8 +#define V_HSS0_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDHA_SEL) +#define F_HSS0_PHY_CTRL_VDDHA_SEL V_HSS0_PHY_CTRL_VDDHA_SEL(1U) + +#define S_HSS1_PHY_CTRL_VDDA_SEL 7 +#define V_HSS1_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDA_SEL) +#define F_HSS1_PHY_CTRL_VDDA_SEL V_HSS1_PHY_CTRL_VDDA_SEL(1U) + +#define S_HSS1_PHY_CTRL_VDDHA_SEL 6 +#define V_HSS1_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDHA_SEL) +#define F_HSS1_PHY_CTRL_VDDHA_SEL V_HSS1_PHY_CTRL_VDDHA_SEL(1U) + +#define S_HSS1_CPU_MEMPSACK 5 +#define V_HSS1_CPU_MEMPSACK(x) ((x) << S_HSS1_CPU_MEMPSACK) +#define F_HSS1_CPU_MEMPSACK V_HSS1_CPU_MEMPSACK(1U) + +#define S_HSS0_CPU_MEMPSACK 3 +#define V_HSS0_CPU_MEMPSACK(x) ((x) << S_HSS0_CPU_MEMPSACK) +#define F_HSS0_CPU_MEMPSACK V_HSS0_CPU_MEMPSACK(1U) + +#define S_HSS1_CPU_MEMACK 4 +#define V_HSS1_CPU_MEMACK(x) ((x) << S_HSS1_CPU_MEMACK) +#define F_HSS1_CPU_MEMACK V_HSS1_CPU_MEMACK(1U) + +#define S_HSS0_CPU_MEMACK 2 +#define V_HSS0_CPU_MEMACK(x) ((x) << S_HSS0_CPU_MEMACK) +#define F_HSS0_CPU_MEMACK V_HSS0_CPU_MEMACK(1U) + +#define S_HSS_PM_IS_ROM 1 +#define V_HSS_PM_IS_ROM(x) ((x) << S_HSS_PM_IS_ROM) +#define F_HSS_PM_IS_ROM V_HSS_PM_IS_ROM(1U) + +#define A_PCIE_HSS_RST 0x5f10 + +#define S_HSS_RST_CTRL_BY_FW 31 +#define V_HSS_RST_CTRL_BY_FW(x) ((x) << S_HSS_RST_CTRL_BY_FW) +#define F_HSS_RST_CTRL_BY_FW V_HSS_RST_CTRL_BY_FW(1U) + +#define S_HSS_PIPE0_RESET_N 30 +#define V_HSS_PIPE0_RESET_N(x) ((x) << S_HSS_PIPE0_RESET_N) +#define F_HSS_PIPE0_RESET_N V_HSS_PIPE0_RESET_N(1U) + +#define S_HSS0_POR_N 29 +#define V_HSS0_POR_N(x) ((x) << S_HSS0_POR_N) +#define F_HSS0_POR_N V_HSS0_POR_N(1U) + +#define S_HSS1_POR_N 28 +#define V_HSS1_POR_N(x) ((x) << S_HSS1_POR_N) +#define F_HSS1_POR_N V_HSS1_POR_N(1U) + +#define S_HSS0_CPU_RESET 27 +#define V_HSS0_CPU_RESET(x) ((x) << S_HSS0_CPU_RESET) +#define F_HSS0_CPU_RESET V_HSS0_CPU_RESET(1U) + +#define S_HSS1_CPU_RESET 26 +#define V_HSS1_CPU_RESET(x) ((x) << S_HSS1_CPU_RESET) +#define F_HSS1_CPU_RESET V_HSS1_CPU_RESET(1U) + +#define S_HSS_PCS_POR_N 25 +#define V_HSS_PCS_POR_N(x) ((x) << S_HSS_PCS_POR_N) +#define F_HSS_PCS_POR_N V_HSS_PCS_POR_N(1U) + +#define S_SW_CRST_ 24 +#define V_SW_CRST_(x) ((x) << S_SW_CRST_) +#define F_SW_CRST_ V_SW_CRST_(1U) + +#define S_SW_PCIECRST_ 23 +#define V_SW_PCIECRST_(x) ((x) << S_SW_PCIECRST_) +#define F_SW_PCIECRST_ V_SW_PCIECRST_(1U) + +#define S_SW_PCIEPIPERST_ 22 +#define V_SW_PCIEPIPERST_(x) ((x) << S_SW_PCIEPIPERST_) +#define F_SW_PCIEPIPERST_ V_SW_PCIEPIPERST_(1U) + +#define S_SW_PCIEPHYRST_ 21 +#define V_SW_PCIEPHYRST_(x) ((x) << S_SW_PCIEPHYRST_) +#define F_SW_PCIEPHYRST_ V_SW_PCIEPHYRST_(1U) + +#define S_HSS1_ERR_O 3 +#define V_HSS1_ERR_O(x) ((x) << S_HSS1_ERR_O) +#define F_HSS1_ERR_O V_HSS1_ERR_O(1U) + +#define S_HSS0_ERR_O 2 +#define V_HSS0_ERR_O(x) ((x) << S_HSS0_ERR_O) +#define F_HSS0_ERR_O V_HSS0_ERR_O(1U) + +#define S_HSS1_PLL_LOCK 1 +#define V_HSS1_PLL_LOCK(x) ((x) << S_HSS1_PLL_LOCK) +#define F_HSS1_PLL_LOCK V_HSS1_PLL_LOCK(1U) + +#define S_HSS0_PLL_LOCK 0 +#define V_HSS0_PLL_LOCK(x) ((x) << S_HSS0_PLL_LOCK) +#define F_HSS0_PLL_LOCK V_HSS0_PLL_LOCK(1U) + +#define A_PCIE_T5_ARM_CFG 0x5f20 + +#define S_T5_ARM_MAXREQCNT 20 +#define M_T5_ARM_MAXREQCNT 0x7fU +#define V_T5_ARM_MAXREQCNT(x) ((x) << S_T5_ARM_MAXREQCNT) +#define G_T5_ARM_MAXREQCNT(x) (((x) >> S_T5_ARM_MAXREQCNT) & M_T5_ARM_MAXREQCNT) + +#define S_T5_ARM_MAXRDREQSIZE 17 +#define M_T5_ARM_MAXRDREQSIZE 0x7U +#define V_T5_ARM_MAXRDREQSIZE(x) ((x) << S_T5_ARM_MAXRDREQSIZE) +#define G_T5_ARM_MAXRDREQSIZE(x) (((x) >> S_T5_ARM_MAXRDREQSIZE) & M_T5_ARM_MAXRDREQSIZE) + +#define S_T5_ARM_MAXRSPCNT 9 +#define M_T5_ARM_MAXRSPCNT 0xffU +#define V_T5_ARM_MAXRSPCNT(x) ((x) << S_T5_ARM_MAXRSPCNT) +#define G_T5_ARM_MAXRSPCNT(x) (((x) >> S_T5_ARM_MAXRSPCNT) & M_T5_ARM_MAXRSPCNT) + +#define A_PCIE_T5_ARM_STAT 0x5f24 + +#define S_ARM_RESPCNT 20 +#define M_ARM_RESPCNT 0x1ffU +#define V_ARM_RESPCNT(x) ((x) << S_ARM_RESPCNT) +#define G_ARM_RESPCNT(x) (((x) >> S_ARM_RESPCNT) & M_ARM_RESPCNT) + +#define S_ARM_RDREQCNT 12 +#define M_ARM_RDREQCNT 0x3fU +#define V_ARM_RDREQCNT(x) ((x) << S_ARM_RDREQCNT) +#define G_ARM_RDREQCNT(x) (((x) >> S_ARM_RDREQCNT) & M_ARM_RDREQCNT) + +#define S_ARM_WRREQCNT 0 +#define M_ARM_WRREQCNT 0x1ffU +#define V_ARM_WRREQCNT(x) ((x) << S_ARM_WRREQCNT) +#define G_ARM_WRREQCNT(x) (((x) >> S_ARM_WRREQCNT) & M_ARM_WRREQCNT) + +#define A_PCIE_T5_ARM_STAT2 0x5f28 + +#define S_ARM_COOKIECNT 24 +#define M_ARM_COOKIECNT 0xfU +#define V_ARM_COOKIECNT(x) ((x) << S_ARM_COOKIECNT) +#define G_ARM_COOKIECNT(x) (((x) >> S_ARM_COOKIECNT) & M_ARM_COOKIECNT) + +#define S_ARM_RDSEQNUMUPDCNT 20 +#define M_ARM_RDSEQNUMUPDCNT 0xfU +#define V_ARM_RDSEQNUMUPDCNT(x) ((x) << S_ARM_RDSEQNUMUPDCNT) +#define G_ARM_RDSEQNUMUPDCNT(x) (((x) >> S_ARM_RDSEQNUMUPDCNT) & M_ARM_RDSEQNUMUPDCNT) + +#define S_ARM_SIREQCNT 16 +#define M_ARM_SIREQCNT 0xfU +#define V_ARM_SIREQCNT(x) ((x) << S_ARM_SIREQCNT) +#define G_ARM_SIREQCNT(x) (((x) >> S_ARM_SIREQCNT) & M_ARM_SIREQCNT) + +#define S_ARM_WREOPMATCHSOP 12 +#define V_ARM_WREOPMATCHSOP(x) ((x) << S_ARM_WREOPMATCHSOP) +#define F_ARM_WREOPMATCHSOP V_ARM_WREOPMATCHSOP(1U) + +#define S_ARM_WRSOPCNT 8 +#define M_ARM_WRSOPCNT 0xfU +#define V_ARM_WRSOPCNT(x) ((x) << S_ARM_WRSOPCNT) +#define G_ARM_WRSOPCNT(x) (((x) >> S_ARM_WRSOPCNT) & M_ARM_WRSOPCNT) + +#define S_ARM_RDSOPCNT 0 +#define M_ARM_RDSOPCNT 0xffU +#define V_ARM_RDSOPCNT(x) ((x) << S_ARM_RDSOPCNT) +#define G_ARM_RDSOPCNT(x) (((x) >> S_ARM_RDSOPCNT) & M_ARM_RDSOPCNT) + +#define A_PCIE_T5_ARM_STAT3 0x5f2c + +#define S_ARM_ATMREQSOPCNT 24 +#define M_ARM_ATMREQSOPCNT 0xffU +#define V_ARM_ATMREQSOPCNT(x) ((x) << S_ARM_ATMREQSOPCNT) +#define G_ARM_ATMREQSOPCNT(x) (((x) >> S_ARM_ATMREQSOPCNT) & M_ARM_ATMREQSOPCNT) + +#define S_ARM_ATMEOPMATCHSOP 17 +#define V_ARM_ATMEOPMATCHSOP(x) ((x) << S_ARM_ATMEOPMATCHSOP) +#define F_ARM_ATMEOPMATCHSOP V_ARM_ATMEOPMATCHSOP(1U) + +#define S_ARM_RSPEOPMATCHSOP 16 +#define V_ARM_RSPEOPMATCHSOP(x) ((x) << S_ARM_RSPEOPMATCHSOP) +#define F_ARM_RSPEOPMATCHSOP V_ARM_RSPEOPMATCHSOP(1U) + +#define S_ARM_RSPERRCNT 8 +#define M_ARM_RSPERRCNT 0xffU +#define V_ARM_RSPERRCNT(x) ((x) << S_ARM_RSPERRCNT) +#define G_ARM_RSPERRCNT(x) (((x) >> S_ARM_RSPERRCNT) & M_ARM_RSPERRCNT) + +#define S_ARM_RSPSOPCNT 0 +#define M_ARM_RSPSOPCNT 0xffU +#define V_ARM_RSPSOPCNT(x) ((x) << S_ARM_RSPSOPCNT) +#define G_ARM_RSPSOPCNT(x) (((x) >> S_ARM_RSPSOPCNT) & M_ARM_RSPSOPCNT) + +#define A_PCIE_ARM_REQUESTER_ID 0x5f30 + +#define S_A0_RSVD1 24 +#define M_A0_RSVD1 0xffU +#define V_A0_RSVD1(x) ((x) << S_A0_RSVD1) +#define G_A0_RSVD1(x) (((x) >> S_A0_RSVD1) & M_A0_RSVD1) + +#define S_A0_PRIMBUSNUMBER 16 +#define M_A0_PRIMBUSNUMBER 0xffU +#define V_A0_PRIMBUSNUMBER(x) ((x) << S_A0_PRIMBUSNUMBER) +#define G_A0_PRIMBUSNUMBER(x) (((x) >> S_A0_PRIMBUSNUMBER) & M_A0_PRIMBUSNUMBER) + +#define S_A0_REQUESTERID 0 +#define M_A0_REQUESTERID 0xffffU +#define V_A0_REQUESTERID(x) ((x) << S_A0_REQUESTERID) +#define G_A0_REQUESTERID(x) (((x) >> S_A0_REQUESTERID) & M_A0_REQUESTERID) + +#define A_PCIE_SWITCH_CFG_SPACE_REQ0 0x5f34 + +#define S_REQ0ENABLE 31 +#define V_REQ0ENABLE(x) ((x) << S_REQ0ENABLE) +#define F_REQ0ENABLE V_REQ0ENABLE(1U) + +#define S_RDREQ0TYPE 19 +#define V_RDREQ0TYPE(x) ((x) << S_RDREQ0TYPE) +#define F_RDREQ0TYPE V_RDREQ0TYPE(1U) + +#define S_BYTEENABLE0 15 +#define M_BYTEENABLE0 0xfU +#define V_BYTEENABLE0(x) ((x) << S_BYTEENABLE0) +#define G_BYTEENABLE0(x) (((x) >> S_BYTEENABLE0) & M_BYTEENABLE0) + +#define S_REGADDR0 0 +#define M_REGADDR0 0x7fffU +#define V_REGADDR0(x) ((x) << S_REGADDR0) +#define G_REGADDR0(x) (((x) >> S_REGADDR0) & M_REGADDR0) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA0 0x5f38 +#define A_PCIE_SWITCH_CFG_SPACE_REQ1 0x5f3c + +#define S_REQ1ENABLE 31 +#define V_REQ1ENABLE(x) ((x) << S_REQ1ENABLE) +#define F_REQ1ENABLE V_REQ1ENABLE(1U) + +#define S_RDREQ1TYPE 26 +#define M_RDREQ1TYPE 0xfU +#define V_RDREQ1TYPE(x) ((x) << S_RDREQ1TYPE) +#define G_RDREQ1TYPE(x) (((x) >> S_RDREQ1TYPE) & M_RDREQ1TYPE) + +#define S_BYTEENABLE1 15 +#define M_BYTEENABLE1 0x7ffU +#define V_BYTEENABLE1(x) ((x) << S_BYTEENABLE1) +#define G_BYTEENABLE1(x) (((x) >> S_BYTEENABLE1) & M_BYTEENABLE1) + +#define S_REGADDR1 0 +#define M_REGADDR1 0x7fffU +#define V_REGADDR1(x) ((x) << S_REGADDR1) +#define G_REGADDR1(x) (((x) >> S_REGADDR1) & M_REGADDR1) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA1 0x5f40 +#define A_PCIE_SWITCH_CFG_SPACE_REQ2 0x5f44 + +#define S_REQ2ENABLE 31 +#define V_REQ2ENABLE(x) ((x) << S_REQ2ENABLE) +#define F_REQ2ENABLE V_REQ2ENABLE(1U) + +#define S_RDREQ2TYPE 26 +#define M_RDREQ2TYPE 0xfU +#define V_RDREQ2TYPE(x) ((x) << S_RDREQ2TYPE) +#define G_RDREQ2TYPE(x) (((x) >> S_RDREQ2TYPE) & M_RDREQ2TYPE) + +#define S_BYTEENABLE2 15 +#define M_BYTEENABLE2 0x7ffU +#define V_BYTEENABLE2(x) ((x) << S_BYTEENABLE2) +#define G_BYTEENABLE2(x) (((x) >> S_BYTEENABLE2) & M_BYTEENABLE2) + +#define S_REGADDR2 0 +#define M_REGADDR2 0x7fffU +#define V_REGADDR2(x) ((x) << S_REGADDR2) +#define G_REGADDR2(x) (((x) >> S_REGADDR2) & M_REGADDR2) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA2 0x5f48 +#define A_PCIE_SWITCH_CFG_SPACE_REQ3 0x5f4c + +#define S_REQ3ENABLE 31 +#define V_REQ3ENABLE(x) ((x) << S_REQ3ENABLE) +#define F_REQ3ENABLE V_REQ3ENABLE(1U) + +#define S_RDREQ3TYPE 26 +#define M_RDREQ3TYPE 0xfU +#define V_RDREQ3TYPE(x) ((x) << S_RDREQ3TYPE) +#define G_RDREQ3TYPE(x) (((x) >> S_RDREQ3TYPE) & M_RDREQ3TYPE) + +#define S_BYTEENABLE3 15 +#define M_BYTEENABLE3 0x7ffU +#define V_BYTEENABLE3(x) ((x) << S_BYTEENABLE3) +#define G_BYTEENABLE3(x) (((x) >> S_BYTEENABLE3) & M_BYTEENABLE3) + +#define S_REGADDR3 0 +#define M_REGADDR3 0x7fffU +#define V_REGADDR3(x) ((x) << S_REGADDR3) +#define G_REGADDR3(x) (((x) >> S_REGADDR3) & M_REGADDR3) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA3 0x5f50 +#define A_PCIE_SWITCH_CFG_SPACE_REQ4 0x5f54 + +#define S_REQ4ENABLE 31 +#define V_REQ4ENABLE(x) ((x) << S_REQ4ENABLE) +#define F_REQ4ENABLE V_REQ4ENABLE(1U) + +#define S_RDREQ4TYPE 26 +#define M_RDREQ4TYPE 0xfU +#define V_RDREQ4TYPE(x) ((x) << S_RDREQ4TYPE) +#define G_RDREQ4TYPE(x) (((x) >> S_RDREQ4TYPE) & M_RDREQ4TYPE) + +#define S_BYTEENABLE4 15 +#define M_BYTEENABLE4 0x7ffU +#define V_BYTEENABLE4(x) ((x) << S_BYTEENABLE4) +#define G_BYTEENABLE4(x) (((x) >> S_BYTEENABLE4) & M_BYTEENABLE4) + +#define S_REGADDR4 0 +#define M_REGADDR4 0x7fffU +#define V_REGADDR4(x) ((x) << S_REGADDR4) +#define G_REGADDR4(x) (((x) >> S_REGADDR4) & M_REGADDR4) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA4 0x5f58 +#define A_PCIE_SWITCH_CFG_SPACE_REQ5 0x5f5c + +#define S_REQ5ENABLE 31 +#define V_REQ5ENABLE(x) ((x) << S_REQ5ENABLE) +#define F_REQ5ENABLE V_REQ5ENABLE(1U) + +#define S_RDREQ5TYPE 26 +#define M_RDREQ5TYPE 0xfU +#define V_RDREQ5TYPE(x) ((x) << S_RDREQ5TYPE) +#define G_RDREQ5TYPE(x) (((x) >> S_RDREQ5TYPE) & M_RDREQ5TYPE) + +#define S_BYTEENABLE5 15 +#define M_BYTEENABLE5 0x7ffU +#define V_BYTEENABLE5(x) ((x) << S_BYTEENABLE5) +#define G_BYTEENABLE5(x) (((x) >> S_BYTEENABLE5) & M_BYTEENABLE5) + +#define S_REGADDR5 0 +#define M_REGADDR5 0x7fffU +#define V_REGADDR5(x) ((x) << S_REGADDR5) +#define G_REGADDR5(x) (((x) >> S_REGADDR5) & M_REGADDR5) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA5 0x5f60 +#define A_PCIE_SWITCH_CFG_SPACE_REQ6 0x5f64 + +#define S_REQ6ENABLE 31 +#define V_REQ6ENABLE(x) ((x) << S_REQ6ENABLE) +#define F_REQ6ENABLE V_REQ6ENABLE(1U) + +#define S_RDREQ6TYPE 26 +#define M_RDREQ6TYPE 0xfU +#define V_RDREQ6TYPE(x) ((x) << S_RDREQ6TYPE) +#define G_RDREQ6TYPE(x) (((x) >> S_RDREQ6TYPE) & M_RDREQ6TYPE) + +#define S_BYTEENABLE6 15 +#define M_BYTEENABLE6 0x7ffU +#define V_BYTEENABLE6(x) ((x) << S_BYTEENABLE6) +#define G_BYTEENABLE6(x) (((x) >> S_BYTEENABLE6) & M_BYTEENABLE6) + +#define S_REGADDR6 0 +#define M_REGADDR6 0x7fffU +#define V_REGADDR6(x) ((x) << S_REGADDR6) +#define G_REGADDR6(x) (((x) >> S_REGADDR6) & M_REGADDR6) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA6 0x5f68 +#define A_PCIE_SWITCH_CFG_SPACE_REQ7 0x5f6c + +#define S_REQ7ENABLE 31 +#define V_REQ7ENABLE(x) ((x) << S_REQ7ENABLE) +#define F_REQ7ENABLE V_REQ7ENABLE(1U) + +#define S_RDREQ7TYPE 26 +#define M_RDREQ7TYPE 0xfU +#define V_RDREQ7TYPE(x) ((x) << S_RDREQ7TYPE) +#define G_RDREQ7TYPE(x) (((x) >> S_RDREQ7TYPE) & M_RDREQ7TYPE) + +#define S_BYTEENABLE7 15 +#define M_BYTEENABLE7 0x7ffU +#define V_BYTEENABLE7(x) ((x) << S_BYTEENABLE7) +#define G_BYTEENABLE7(x) (((x) >> S_BYTEENABLE7) & M_BYTEENABLE7) + +#define S_REGADDR7 0 +#define M_REGADDR7 0x7fffU +#define V_REGADDR7(x) ((x) << S_REGADDR7) +#define G_REGADDR7(x) (((x) >> S_REGADDR7) & M_REGADDR7) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA7 0x5f70 +#define A_PCIE_SWITCH_CFG_SPACE_REQ8 0x5f74 + +#define S_REQ8ENABLE 31 +#define V_REQ8ENABLE(x) ((x) << S_REQ8ENABLE) +#define F_REQ8ENABLE V_REQ8ENABLE(1U) + +#define S_RDREQ8TYPE 26 +#define M_RDREQ8TYPE 0xfU +#define V_RDREQ8TYPE(x) ((x) << S_RDREQ8TYPE) +#define G_RDREQ8TYPE(x) (((x) >> S_RDREQ8TYPE) & M_RDREQ8TYPE) + +#define S_BYTEENABLE8 15 +#define M_BYTEENABLE8 0x7ffU +#define V_BYTEENABLE8(x) ((x) << S_BYTEENABLE8) +#define G_BYTEENABLE8(x) (((x) >> S_BYTEENABLE8) & M_BYTEENABLE8) + +#define S_REGADDR8 0 +#define M_REGADDR8 0x7fffU +#define V_REGADDR8(x) ((x) << S_REGADDR8) +#define G_REGADDR8(x) (((x) >> S_REGADDR8) & M_REGADDR8) + +#define A_PCIE_SWITCH_CFG_SPACE_DATA8 0x5f78 +#define A_PCIE_SNPS_G5_PHY_CR_REQ 0x5f7c + +#define S_REGSEL 31 +#define V_REGSEL(x) ((x) << S_REGSEL) +#define F_REGSEL V_REGSEL(1U) + +#define S_RDENABLE 30 +#define V_RDENABLE(x) ((x) << S_RDENABLE) +#define F_RDENABLE V_RDENABLE(1U) + +#define S_WRENABLE 29 +#define V_WRENABLE(x) ((x) << S_WRENABLE) +#define F_WRENABLE V_WRENABLE(1U) + +#define S_AUTOINCRVAL 21 +#define M_AUTOINCRVAL 0x3U +#define V_AUTOINCRVAL(x) ((x) << S_AUTOINCRVAL) +#define G_AUTOINCRVAL(x) (((x) >> S_AUTOINCRVAL) & M_AUTOINCRVAL) + +#define S_AUTOINCR 20 +#define V_AUTOINCR(x) ((x) << S_AUTOINCR) +#define F_AUTOINCR V_AUTOINCR(1U) + +#define S_PHYSEL 16 +#define M_PHYSEL 0xfU +#define V_PHYSEL(x) ((x) << S_PHYSEL) +#define G_PHYSEL(x) (((x) >> S_PHYSEL) & M_PHYSEL) + +#define S_T7_REGADDR 0 +#define M_T7_REGADDR 0xffffU +#define V_T7_REGADDR(x) ((x) << S_T7_REGADDR) +#define G_T7_REGADDR(x) (((x) >> S_T7_REGADDR) & M_T7_REGADDR) + +#define A_PCIE_SNPS_G5_PHY_CR_DATA 0x5f80 +#define A_PCIE_SNPS_G5_PHY_SRAM_CFG 0x5f84 + +#define S_PHY3_SRAM_BOOTLOAD_BYPASS 27 +#define V_PHY3_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY3_SRAM_BOOTLOAD_BYPASS) +#define F_PHY3_SRAM_BOOTLOAD_BYPASS V_PHY3_SRAM_BOOTLOAD_BYPASS(1U) + +#define S_PHY3_SRAM_BYPASS 26 +#define V_PHY3_SRAM_BYPASS(x) ((x) << S_PHY3_SRAM_BYPASS) +#define F_PHY3_SRAM_BYPASS V_PHY3_SRAM_BYPASS(1U) + +#define S_PHY3_SRAM_ECC_EN 25 +#define V_PHY3_SRAM_ECC_EN(x) ((x) << S_PHY3_SRAM_ECC_EN) +#define F_PHY3_SRAM_ECC_EN V_PHY3_SRAM_ECC_EN(1U) + +#define S_PHY3_SRAM_EXT_LD_DONE 24 +#define V_PHY3_SRAM_EXT_LD_DONE(x) ((x) << S_PHY3_SRAM_EXT_LD_DONE) +#define F_PHY3_SRAM_EXT_LD_DONE V_PHY3_SRAM_EXT_LD_DONE(1U) + +#define S_PHY2_SRAM_BOOTLOAD_BYPASS 19 +#define V_PHY2_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY2_SRAM_BOOTLOAD_BYPASS) +#define F_PHY2_SRAM_BOOTLOAD_BYPASS V_PHY2_SRAM_BOOTLOAD_BYPASS(1U) + +#define S_PHY2_SRAM_BYPASS 18 +#define V_PHY2_SRAM_BYPASS(x) ((x) << S_PHY2_SRAM_BYPASS) +#define F_PHY2_SRAM_BYPASS V_PHY2_SRAM_BYPASS(1U) + +#define S_PHY2_SRAM_ECC_EN 17 +#define V_PHY2_SRAM_ECC_EN(x) ((x) << S_PHY2_SRAM_ECC_EN) +#define F_PHY2_SRAM_ECC_EN V_PHY2_SRAM_ECC_EN(1U) + +#define S_PHY2_SRAM_EXT_LD_DONE 16 +#define V_PHY2_SRAM_EXT_LD_DONE(x) ((x) << S_PHY2_SRAM_EXT_LD_DONE) +#define F_PHY2_SRAM_EXT_LD_DONE V_PHY2_SRAM_EXT_LD_DONE(1U) + +#define S_PHY1_SRAM_BOOTLOAD_BYPASS 11 +#define V_PHY1_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY1_SRAM_BOOTLOAD_BYPASS) +#define F_PHY1_SRAM_BOOTLOAD_BYPASS V_PHY1_SRAM_BOOTLOAD_BYPASS(1U) + +#define S_PHY1_SRAM_BYPASS 10 +#define V_PHY1_SRAM_BYPASS(x) ((x) << S_PHY1_SRAM_BYPASS) +#define F_PHY1_SRAM_BYPASS V_PHY1_SRAM_BYPASS(1U) + +#define S_PHY1_SRAM_ECC_EN 9 +#define V_PHY1_SRAM_ECC_EN(x) ((x) << S_PHY1_SRAM_ECC_EN) +#define F_PHY1_SRAM_ECC_EN V_PHY1_SRAM_ECC_EN(1U) + +#define S_PHY1_SRAM_EXT_LD_DONE 8 +#define V_PHY1_SRAM_EXT_LD_DONE(x) ((x) << S_PHY1_SRAM_EXT_LD_DONE) +#define F_PHY1_SRAM_EXT_LD_DONE V_PHY1_SRAM_EXT_LD_DONE(1U) + +#define S_PHY_CR_PARA_SEL 4 +#define M_PHY_CR_PARA_SEL 0xfU +#define V_PHY_CR_PARA_SEL(x) ((x) << S_PHY_CR_PARA_SEL) +#define G_PHY_CR_PARA_SEL(x) (((x) >> S_PHY_CR_PARA_SEL) & M_PHY_CR_PARA_SEL) + +#define S_PHY0_SRAM_BOOTLOAD_BYPASS 3 +#define V_PHY0_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY0_SRAM_BOOTLOAD_BYPASS) +#define F_PHY0_SRAM_BOOTLOAD_BYPASS V_PHY0_SRAM_BOOTLOAD_BYPASS(1U) + +#define S_PHY0_SRAM_BYPASS 2 +#define V_PHY0_SRAM_BYPASS(x) ((x) << S_PHY0_SRAM_BYPASS) +#define F_PHY0_SRAM_BYPASS V_PHY0_SRAM_BYPASS(1U) + +#define S_PHY0_SRAM_ECC_EN 1 +#define V_PHY0_SRAM_ECC_EN(x) ((x) << S_PHY0_SRAM_ECC_EN) +#define F_PHY0_SRAM_ECC_EN V_PHY0_SRAM_ECC_EN(1U) + +#define S_PHY0_SRAM_EXT_LD_DONE 0 +#define V_PHY0_SRAM_EXT_LD_DONE(x) ((x) << S_PHY0_SRAM_EXT_LD_DONE) +#define F_PHY0_SRAM_EXT_LD_DONE V_PHY0_SRAM_EXT_LD_DONE(1U) + +#define A_PCIE_SNPS_G5_PHY_SRAM_STS 0x5f88 + +#define S_PHY3_SRAM_INIT_DONE 3 +#define V_PHY3_SRAM_INIT_DONE(x) ((x) << S_PHY3_SRAM_INIT_DONE) +#define F_PHY3_SRAM_INIT_DONE V_PHY3_SRAM_INIT_DONE(1U) + +#define S_PHY2_SRAM_INIT_DONE 2 +#define V_PHY2_SRAM_INIT_DONE(x) ((x) << S_PHY2_SRAM_INIT_DONE) +#define F_PHY2_SRAM_INIT_DONE V_PHY2_SRAM_INIT_DONE(1U) + +#define S_PHY1_SRAM_INIT_DONE 1 +#define V_PHY1_SRAM_INIT_DONE(x) ((x) << S_PHY1_SRAM_INIT_DONE) +#define F_PHY1_SRAM_INIT_DONE V_PHY1_SRAM_INIT_DONE(1U) + +#define S_PHY0_SRAM_INIT_DONE 0 +#define V_PHY0_SRAM_INIT_DONE(x) ((x) << S_PHY0_SRAM_INIT_DONE) +#define F_PHY0_SRAM_INIT_DONE V_PHY0_SRAM_INIT_DONE(1U) + +#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_TO_3 0x5f90 +#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_DATA 0x5f94 +#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_1_DATA 0x5f98 +#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_2_DATA 0x5f9c +#define A_PCIE_SNPS_G5_PHY_CTRL_PHY_3_DATA 0x5fa0 +#define A_PCIE_SNPS_G5_PHY_DEFAULTS 0x5fa4 +#define A_PCIE_SNPS_G5_PHY_0_VALUES 0x5fa8 + +#define S_RX_TERM_OFFSET 28 +#define V_RX_TERM_OFFSET(x) ((x) << S_RX_TERM_OFFSET) +#define F_RX_TERM_OFFSET V_RX_TERM_OFFSET(1U) + +#define S_REFB_RAW_CLK_DIV2_EN 27 +#define V_REFB_RAW_CLK_DIV2_EN(x) ((x) << S_REFB_RAW_CLK_DIV2_EN) +#define F_REFB_RAW_CLK_DIV2_EN V_REFB_RAW_CLK_DIV2_EN(1U) + +#define S_REFB_RANGE 23 +#define M_REFB_RANGE 0xfU +#define V_REFB_RANGE(x) ((x) << S_REFB_RANGE) +#define G_REFB_RANGE(x) (((x) >> S_REFB_RANGE) & M_REFB_RANGE) + +#define S_REFB_LANE_CLK_EN 22 +#define V_REFB_LANE_CLK_EN(x) ((x) << S_REFB_LANE_CLK_EN) +#define F_REFB_LANE_CLK_EN V_REFB_LANE_CLK_EN(1U) + +#define S_REFB_CLK_DIV2_EN 21 +#define V_REFB_CLK_DIV2_EN(x) ((x) << S_REFB_CLK_DIV2_EN) +#define F_REFB_CLK_DIV2_EN V_REFB_CLK_DIV2_EN(1U) + +#define S_REFA_RAW_CLK_DIV2_EN 20 +#define V_REFA_RAW_CLK_DIV2_EN(x) ((x) << S_REFA_RAW_CLK_DIV2_EN) +#define F_REFA_RAW_CLK_DIV2_EN V_REFA_RAW_CLK_DIV2_EN(1U) + +#define S_REFA_RANGE 16 +#define M_REFA_RANGE 0xfU +#define V_REFA_RANGE(x) ((x) << S_REFA_RANGE) +#define G_REFA_RANGE(x) (((x) >> S_REFA_RANGE) & M_REFA_RANGE) + +#define S_REFA_LANE_CLK_EN 15 +#define V_REFA_LANE_CLK_EN(x) ((x) << S_REFA_LANE_CLK_EN) +#define F_REFA_LANE_CLK_EN V_REFA_LANE_CLK_EN(1U) + +#define S_REFA_CLK_DIV2_EN 14 +#define V_REFA_CLK_DIV2_EN(x) ((x) << S_REFA_CLK_DIV2_EN) +#define F_REFA_CLK_DIV2_EN V_REFA_CLK_DIV2_EN(1U) + +#define S_NOMINAL_VPH_SEL 10 +#define M_NOMINAL_VPH_SEL 0x3U +#define V_NOMINAL_VPH_SEL(x) ((x) << S_NOMINAL_VPH_SEL) +#define G_NOMINAL_VPH_SEL(x) (((x) >> S_NOMINAL_VPH_SEL) & M_NOMINAL_VPH_SEL) + +#define S_NOMINAL_VP_SEL 8 +#define M_NOMINAL_VP_SEL 0x3U +#define V_NOMINAL_VP_SEL(x) ((x) << S_NOMINAL_VP_SEL) +#define G_NOMINAL_VP_SEL(x) (((x) >> S_NOMINAL_VP_SEL) & M_NOMINAL_VP_SEL) + +#define S_MPLLB_WORD_CLK_EN 7 +#define V_MPLLB_WORD_CLK_EN(x) ((x) << S_MPLLB_WORD_CLK_EN) +#define F_MPLLB_WORD_CLK_EN V_MPLLB_WORD_CLK_EN(1U) + +#define S_MPLLB_SSC_EN 6 +#define V_MPLLB_SSC_EN(x) ((x) << S_MPLLB_SSC_EN) +#define F_MPLLB_SSC_EN V_MPLLB_SSC_EN(1U) + +#define S_MPLLB_SHORT_LOCK_EN 5 +#define V_MPLLB_SHORT_LOCK_EN(x) ((x) << S_MPLLB_SHORT_LOCK_EN) +#define F_MPLLB_SHORT_LOCK_EN V_MPLLB_SHORT_LOCK_EN(1U) + +#define S_MPLLB_FORCE_EN 4 +#define V_MPLLB_FORCE_EN(x) ((x) << S_MPLLB_FORCE_EN) +#define F_MPLLB_FORCE_EN V_MPLLB_FORCE_EN(1U) + +#define S_MPLLA_WORD_CLK_EN 3 +#define V_MPLLA_WORD_CLK_EN(x) ((x) << S_MPLLA_WORD_CLK_EN) +#define F_MPLLA_WORD_CLK_EN V_MPLLA_WORD_CLK_EN(1U) + +#define S_MPLLA_SSC_EN 2 +#define V_MPLLA_SSC_EN(x) ((x) << S_MPLLA_SSC_EN) +#define F_MPLLA_SSC_EN V_MPLLA_SSC_EN(1U) + +#define S_MPLLA_SHORT_LOCK_EN 1 +#define V_MPLLA_SHORT_LOCK_EN(x) ((x) << S_MPLLA_SHORT_LOCK_EN) +#define F_MPLLA_SHORT_LOCK_EN V_MPLLA_SHORT_LOCK_EN(1U) + +#define S_MPLLA_FORCE_EN 0 +#define V_MPLLA_FORCE_EN(x) ((x) << S_MPLLA_FORCE_EN) +#define F_MPLLA_FORCE_EN V_MPLLA_FORCE_EN(1U) + +#define A_PCIE_SNPS_G5_PHY_1_VALUES 0x5fac + +#define S_REF_ALT1_CLK_M 13 +#define V_REF_ALT1_CLK_M(x) ((x) << S_REF_ALT1_CLK_M) +#define F_REF_ALT1_CLK_M V_REF_ALT1_CLK_M(1U) + +#define S_REF_ALT1_CLK_P 12 +#define V_REF_ALT1_CLK_P(x) ((x) << S_REF_ALT1_CLK_P) +#define F_REF_ALT1_CLK_P V_REF_ALT1_CLK_P(1U) + +#define A_PCIE_SNPS_G5_PHY_2_VALUES 0x5fb0 +#define A_PCIE_SNPS_G5_PHY_3_VALUES 0x5fb4 +#define A_PCIE_SNPS_G5_PHY_0_RX_LANEPLL_BYPASS_MODE 0x5fb8 + +#define S_T7_LANE3 15 +#define M_T7_LANE3 0x1fU +#define V_T7_LANE3(x) ((x) << S_T7_LANE3) +#define G_T7_LANE3(x) (((x) >> S_T7_LANE3) & M_T7_LANE3) + +#define S_T7_LANE2 10 +#define M_T7_LANE2 0x1fU +#define V_T7_LANE2(x) ((x) << S_T7_LANE2) +#define G_T7_LANE2(x) (((x) >> S_T7_LANE2) & M_T7_LANE2) + +#define S_T7_LANE1 5 +#define M_T7_LANE1 0x1fU +#define V_T7_LANE1(x) ((x) << S_T7_LANE1) +#define G_T7_LANE1(x) (((x) >> S_T7_LANE1) & M_T7_LANE1) + +#define S_T7_LANE0 0 +#define M_T7_LANE0 0x1fU +#define V_T7_LANE0(x) ((x) << S_T7_LANE0) +#define G_T7_LANE0(x) (((x) >> S_T7_LANE0) & M_T7_LANE0) + +#define A_PCIE_SNPS_G5_PHY_1_RX_LANEPLL_BYPASS_MODE 0x5fbc +#define A_PCIE_SNPS_G5_PHY_2_RX_LANEPLL_BYPASS_MODE 0x5fc0 +#define A_PCIE_SNPS_G5_PHY_3_RX_LANEPLL_BYPASS_MODE 0x5fc4 +#define A_PCIE_SNPS_G5_PHY_0_1_RX_LANEPLL_SRC_SEL 0x5fc8 + +#define S_LANE7_LANEPLL_SRC_SEL 28 +#define M_LANE7_LANEPLL_SRC_SEL 0xfU +#define V_LANE7_LANEPLL_SRC_SEL(x) ((x) << S_LANE7_LANEPLL_SRC_SEL) +#define G_LANE7_LANEPLL_SRC_SEL(x) (((x) >> S_LANE7_LANEPLL_SRC_SEL) & M_LANE7_LANEPLL_SRC_SEL) + +#define S_LANE6_LANEPLL_SRC_SEL 24 +#define M_LANE6_LANEPLL_SRC_SEL 0xfU +#define V_LANE6_LANEPLL_SRC_SEL(x) ((x) << S_LANE6_LANEPLL_SRC_SEL) +#define G_LANE6_LANEPLL_SRC_SEL(x) (((x) >> S_LANE6_LANEPLL_SRC_SEL) & M_LANE6_LANEPLL_SRC_SEL) + +#define S_LANE5_LANEPLL_SRC_SEL 20 +#define M_LANE5_LANEPLL_SRC_SEL 0xfU +#define V_LANE5_LANEPLL_SRC_SEL(x) ((x) << S_LANE5_LANEPLL_SRC_SEL) +#define G_LANE5_LANEPLL_SRC_SEL(x) (((x) >> S_LANE5_LANEPLL_SRC_SEL) & M_LANE5_LANEPLL_SRC_SEL) + +#define S_LANE4_LANEPLL_SRC_SEL 16 +#define M_LANE4_LANEPLL_SRC_SEL 0xfU +#define V_LANE4_LANEPLL_SRC_SEL(x) ((x) << S_LANE4_LANEPLL_SRC_SEL) +#define G_LANE4_LANEPLL_SRC_SEL(x) (((x) >> S_LANE4_LANEPLL_SRC_SEL) & M_LANE4_LANEPLL_SRC_SEL) + +#define S_LANE3_LANEPLL_SRC_SEL 12 +#define M_LANE3_LANEPLL_SRC_SEL 0xfU +#define V_LANE3_LANEPLL_SRC_SEL(x) ((x) << S_LANE3_LANEPLL_SRC_SEL) +#define G_LANE3_LANEPLL_SRC_SEL(x) (((x) >> S_LANE3_LANEPLL_SRC_SEL) & M_LANE3_LANEPLL_SRC_SEL) + +#define S_LANE2_LANEPLL_SRC_SEL 8 +#define M_LANE2_LANEPLL_SRC_SEL 0xfU +#define V_LANE2_LANEPLL_SRC_SEL(x) ((x) << S_LANE2_LANEPLL_SRC_SEL) +#define G_LANE2_LANEPLL_SRC_SEL(x) (((x) >> S_LANE2_LANEPLL_SRC_SEL) & M_LANE2_LANEPLL_SRC_SEL) + +#define S_LANE1_LANEPLL_SRC_SEL 4 +#define M_LANE1_LANEPLL_SRC_SEL 0xfU +#define V_LANE1_LANEPLL_SRC_SEL(x) ((x) << S_LANE1_LANEPLL_SRC_SEL) +#define G_LANE1_LANEPLL_SRC_SEL(x) (((x) >> S_LANE1_LANEPLL_SRC_SEL) & M_LANE1_LANEPLL_SRC_SEL) + +#define S_LANE0_LANEPLL_SRC_SEL 0 +#define M_LANE0_LANEPLL_SRC_SEL 0xfU +#define V_LANE0_LANEPLL_SRC_SEL(x) ((x) << S_LANE0_LANEPLL_SRC_SEL) +#define G_LANE0_LANEPLL_SRC_SEL(x) (((x) >> S_LANE0_LANEPLL_SRC_SEL) & M_LANE0_LANEPLL_SRC_SEL) + +#define A_PCIE_SNPS_G5_PHY_2_3_RX_LANEPLL_SRC_SEL 0x5fcc +#define A_PCIE_SNPS_G5_PHY_RX_DECERR 0x5fd0 + +#define S_LANE15_REC_OVRD_8B10B_DECERR 30 +#define M_LANE15_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE15_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE15_REC_OVRD_8B10B_DECERR) +#define G_LANE15_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE15_REC_OVRD_8B10B_DECERR) & M_LANE15_REC_OVRD_8B10B_DECERR) + +#define S_LANE14_REC_OVRD_8B10B_DECERR 28 +#define M_LANE14_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE14_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE14_REC_OVRD_8B10B_DECERR) +#define G_LANE14_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE14_REC_OVRD_8B10B_DECERR) & M_LANE14_REC_OVRD_8B10B_DECERR) + +#define S_LANE13_REC_OVRD_8B10B_DECERR 26 +#define M_LANE13_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE13_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE13_REC_OVRD_8B10B_DECERR) +#define G_LANE13_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE13_REC_OVRD_8B10B_DECERR) & M_LANE13_REC_OVRD_8B10B_DECERR) + +#define S_LANE12_REC_OVRD_8B10B_DECERR 24 +#define M_LANE12_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE12_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE12_REC_OVRD_8B10B_DECERR) +#define G_LANE12_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE12_REC_OVRD_8B10B_DECERR) & M_LANE12_REC_OVRD_8B10B_DECERR) + +#define S_LANE11_REC_OVRD_8B10B_DECERR 22 +#define M_LANE11_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE11_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE11_REC_OVRD_8B10B_DECERR) +#define G_LANE11_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE11_REC_OVRD_8B10B_DECERR) & M_LANE11_REC_OVRD_8B10B_DECERR) + +#define S_LANE10_REC_OVRD_8B10B_DECERR 20 +#define M_LANE10_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE10_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE10_REC_OVRD_8B10B_DECERR) +#define G_LANE10_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE10_REC_OVRD_8B10B_DECERR) & M_LANE10_REC_OVRD_8B10B_DECERR) + +#define S_LANE9_REC_OVRD_8B10B_DECERR 18 +#define M_LANE9_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE9_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE9_REC_OVRD_8B10B_DECERR) +#define G_LANE9_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE9_REC_OVRD_8B10B_DECERR) & M_LANE9_REC_OVRD_8B10B_DECERR) + +#define S_LANE8_REC_OVRD_8B10B_DECERR 16 +#define M_LANE8_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE8_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE8_REC_OVRD_8B10B_DECERR) +#define G_LANE8_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE8_REC_OVRD_8B10B_DECERR) & M_LANE8_REC_OVRD_8B10B_DECERR) + +#define S_LANE7_REC_OVRD_8B10B_DECERR 14 +#define M_LANE7_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE7_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE7_REC_OVRD_8B10B_DECERR) +#define G_LANE7_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE7_REC_OVRD_8B10B_DECERR) & M_LANE7_REC_OVRD_8B10B_DECERR) + +#define S_LANE6_REC_OVRD_8B10B_DECERR 12 +#define M_LANE6_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE6_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE6_REC_OVRD_8B10B_DECERR) +#define G_LANE6_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE6_REC_OVRD_8B10B_DECERR) & M_LANE6_REC_OVRD_8B10B_DECERR) + +#define S_LANE5_REC_OVRD_8B10B_DECERR 10 +#define M_LANE5_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE5_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE5_REC_OVRD_8B10B_DECERR) +#define G_LANE5_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE5_REC_OVRD_8B10B_DECERR) & M_LANE5_REC_OVRD_8B10B_DECERR) + +#define S_LANE4_REC_OVRD_8B10B_DECERR 8 +#define M_LANE4_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE4_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE4_REC_OVRD_8B10B_DECERR) +#define G_LANE4_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE4_REC_OVRD_8B10B_DECERR) & M_LANE4_REC_OVRD_8B10B_DECERR) + +#define S_LANE3_REC_OVRD_8B10B_DECERR 6 +#define M_LANE3_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE3_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE3_REC_OVRD_8B10B_DECERR) +#define G_LANE3_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE3_REC_OVRD_8B10B_DECERR) & M_LANE3_REC_OVRD_8B10B_DECERR) + +#define S_LANE2_REC_OVRD_8B10B_DECERR 4 +#define M_LANE2_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE2_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE2_REC_OVRD_8B10B_DECERR) +#define G_LANE2_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE2_REC_OVRD_8B10B_DECERR) & M_LANE2_REC_OVRD_8B10B_DECERR) + +#define S_LANE1_REC_OVRD_8B10B_DECERR 2 +#define M_LANE1_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE1_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE1_REC_OVRD_8B10B_DECERR) +#define G_LANE1_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE1_REC_OVRD_8B10B_DECERR) & M_LANE1_REC_OVRD_8B10B_DECERR) + +#define S_LANE0_REC_OVRD_8B10B_DECERR 0 +#define M_LANE0_REC_OVRD_8B10B_DECERR 0x3U +#define V_LANE0_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE0_REC_OVRD_8B10B_DECERR) +#define G_LANE0_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE0_REC_OVRD_8B10B_DECERR) & M_LANE0_REC_OVRD_8B10B_DECERR) + +#define A_PCIE_SNPS_G5_PHY_TX2RX_LOOPBK_REC_OVRD_EN 0x5fd4 + +#define S_LANE15_REC_OVRD_EN 31 +#define V_LANE15_REC_OVRD_EN(x) ((x) << S_LANE15_REC_OVRD_EN) +#define F_LANE15_REC_OVRD_EN V_LANE15_REC_OVRD_EN(1U) + +#define S_LANE14_REC_OVRD_EN 30 +#define V_LANE14_REC_OVRD_EN(x) ((x) << S_LANE14_REC_OVRD_EN) +#define F_LANE14_REC_OVRD_EN V_LANE14_REC_OVRD_EN(1U) + +#define S_LANE13_REC_OVRD_EN 29 +#define V_LANE13_REC_OVRD_EN(x) ((x) << S_LANE13_REC_OVRD_EN) +#define F_LANE13_REC_OVRD_EN V_LANE13_REC_OVRD_EN(1U) + +#define S_LANE11_REC_OVRD_EN 27 +#define V_LANE11_REC_OVRD_EN(x) ((x) << S_LANE11_REC_OVRD_EN) +#define F_LANE11_REC_OVRD_EN V_LANE11_REC_OVRD_EN(1U) + +#define S_LANE12_REC_OVRD_EN 28 +#define V_LANE12_REC_OVRD_EN(x) ((x) << S_LANE12_REC_OVRD_EN) +#define F_LANE12_REC_OVRD_EN V_LANE12_REC_OVRD_EN(1U) + +#define S_LANE10_REC_OVRD_EN 26 +#define V_LANE10_REC_OVRD_EN(x) ((x) << S_LANE10_REC_OVRD_EN) +#define F_LANE10_REC_OVRD_EN V_LANE10_REC_OVRD_EN(1U) + +#define S_LANE9_REC_OVRD_EN 25 +#define V_LANE9_REC_OVRD_EN(x) ((x) << S_LANE9_REC_OVRD_EN) +#define F_LANE9_REC_OVRD_EN V_LANE9_REC_OVRD_EN(1U) + +#define S_LANE8_REC_OVRD_EN 24 +#define V_LANE8_REC_OVRD_EN(x) ((x) << S_LANE8_REC_OVRD_EN) +#define F_LANE8_REC_OVRD_EN V_LANE8_REC_OVRD_EN(1U) + +#define S_LANE7_REC_OVRD_EN 23 +#define V_LANE7_REC_OVRD_EN(x) ((x) << S_LANE7_REC_OVRD_EN) +#define F_LANE7_REC_OVRD_EN V_LANE7_REC_OVRD_EN(1U) + +#define S_LANE6_REC_OVRD_EN 22 +#define V_LANE6_REC_OVRD_EN(x) ((x) << S_LANE6_REC_OVRD_EN) +#define F_LANE6_REC_OVRD_EN V_LANE6_REC_OVRD_EN(1U) + +#define S_LANE5_REC_OVRD_EN 21 +#define V_LANE5_REC_OVRD_EN(x) ((x) << S_LANE5_REC_OVRD_EN) +#define F_LANE5_REC_OVRD_EN V_LANE5_REC_OVRD_EN(1U) + +#define S_LANE4_REC_OVRD_EN 20 +#define V_LANE4_REC_OVRD_EN(x) ((x) << S_LANE4_REC_OVRD_EN) +#define F_LANE4_REC_OVRD_EN V_LANE4_REC_OVRD_EN(1U) + +#define S_LANE3_REC_OVRD_EN 19 +#define V_LANE3_REC_OVRD_EN(x) ((x) << S_LANE3_REC_OVRD_EN) +#define F_LANE3_REC_OVRD_EN V_LANE3_REC_OVRD_EN(1U) + +#define S_LANE2_REC_OVRD_EN 18 +#define V_LANE2_REC_OVRD_EN(x) ((x) << S_LANE2_REC_OVRD_EN) +#define F_LANE2_REC_OVRD_EN V_LANE2_REC_OVRD_EN(1U) + +#define S_LANE1_REC_OVRD_EN 17 +#define V_LANE1_REC_OVRD_EN(x) ((x) << S_LANE1_REC_OVRD_EN) +#define F_LANE1_REC_OVRD_EN V_LANE1_REC_OVRD_EN(1U) + +#define S_LANE0_REC_OVRD_EN 16 +#define V_LANE0_REC_OVRD_EN(x) ((x) << S_LANE0_REC_OVRD_EN) +#define F_LANE0_REC_OVRD_EN V_LANE0_REC_OVRD_EN(1U) + +#define S_LANE15_TX2RX_LOOPBK 15 +#define V_LANE15_TX2RX_LOOPBK(x) ((x) << S_LANE15_TX2RX_LOOPBK) +#define F_LANE15_TX2RX_LOOPBK V_LANE15_TX2RX_LOOPBK(1U) + +#define S_LANE14_TX2RX_LOOPBK 14 +#define V_LANE14_TX2RX_LOOPBK(x) ((x) << S_LANE14_TX2RX_LOOPBK) +#define F_LANE14_TX2RX_LOOPBK V_LANE14_TX2RX_LOOPBK(1U) + +#define S_LANE13_TX2RX_LOOPBK 13 +#define V_LANE13_TX2RX_LOOPBK(x) ((x) << S_LANE13_TX2RX_LOOPBK) +#define F_LANE13_TX2RX_LOOPBK V_LANE13_TX2RX_LOOPBK(1U) + +#define S_LANE12_TX2RX_LOOPBK 12 +#define V_LANE12_TX2RX_LOOPBK(x) ((x) << S_LANE12_TX2RX_LOOPBK) +#define F_LANE12_TX2RX_LOOPBK V_LANE12_TX2RX_LOOPBK(1U) + +#define S_LANE11_TX2RX_LOOPBK 11 +#define V_LANE11_TX2RX_LOOPBK(x) ((x) << S_LANE11_TX2RX_LOOPBK) +#define F_LANE11_TX2RX_LOOPBK V_LANE11_TX2RX_LOOPBK(1U) + +#define S_LANE10_TX2RX_LOOPBK 10 +#define V_LANE10_TX2RX_LOOPBK(x) ((x) << S_LANE10_TX2RX_LOOPBK) +#define F_LANE10_TX2RX_LOOPBK V_LANE10_TX2RX_LOOPBK(1U) + +#define S_LANE9_TX2RX_LOOPBK 9 +#define V_LANE9_TX2RX_LOOPBK(x) ((x) << S_LANE9_TX2RX_LOOPBK) +#define F_LANE9_TX2RX_LOOPBK V_LANE9_TX2RX_LOOPBK(1U) + +#define S_LANE8_TX2RX_LOOPBK 8 +#define V_LANE8_TX2RX_LOOPBK(x) ((x) << S_LANE8_TX2RX_LOOPBK) +#define F_LANE8_TX2RX_LOOPBK V_LANE8_TX2RX_LOOPBK(1U) + +#define S_LANE7_TX2RX_LOOPBK 7 +#define V_LANE7_TX2RX_LOOPBK(x) ((x) << S_LANE7_TX2RX_LOOPBK) +#define F_LANE7_TX2RX_LOOPBK V_LANE7_TX2RX_LOOPBK(1U) + +#define S_LANE6_TX2RX_LOOPBK 6 +#define V_LANE6_TX2RX_LOOPBK(x) ((x) << S_LANE6_TX2RX_LOOPBK) +#define F_LANE6_TX2RX_LOOPBK V_LANE6_TX2RX_LOOPBK(1U) + +#define S_LANE5_TX2RX_LOOPBK 5 +#define V_LANE5_TX2RX_LOOPBK(x) ((x) << S_LANE5_TX2RX_LOOPBK) +#define F_LANE5_TX2RX_LOOPBK V_LANE5_TX2RX_LOOPBK(1U) + +#define S_LANE4_TX2RX_LOOPBK 4 +#define V_LANE4_TX2RX_LOOPBK(x) ((x) << S_LANE4_TX2RX_LOOPBK) +#define F_LANE4_TX2RX_LOOPBK V_LANE4_TX2RX_LOOPBK(1U) + +#define S_LANE3_TX2RX_LOOPBK 3 +#define V_LANE3_TX2RX_LOOPBK(x) ((x) << S_LANE3_TX2RX_LOOPBK) +#define F_LANE3_TX2RX_LOOPBK V_LANE3_TX2RX_LOOPBK(1U) + +#define S_LANE2_TX2RX_LOOPBK 2 +#define V_LANE2_TX2RX_LOOPBK(x) ((x) << S_LANE2_TX2RX_LOOPBK) +#define F_LANE2_TX2RX_LOOPBK V_LANE2_TX2RX_LOOPBK(1U) + +#define S_LANE1_TX2RX_LOOPBK 1 +#define V_LANE1_TX2RX_LOOPBK(x) ((x) << S_LANE1_TX2RX_LOOPBK) +#define F_LANE1_TX2RX_LOOPBK V_LANE1_TX2RX_LOOPBK(1U) + +#define S_LANE0_TX2RX_LOOPBK 0 +#define V_LANE0_TX2RX_LOOPBK(x) ((x) << S_LANE0_TX2RX_LOOPBK) +#define F_LANE0_TX2RX_LOOPBK V_LANE0_TX2RX_LOOPBK(1U) + +#define A_PCIE_PHY_TX_DISABLE_UPCS_PIPE_CONFIG 0x5fd8 + +#define S_UPCS_PIPE_CONFIG 16 +#define M_UPCS_PIPE_CONFIG 0xffffU +#define V_UPCS_PIPE_CONFIG(x) ((x) << S_UPCS_PIPE_CONFIG) +#define G_UPCS_PIPE_CONFIG(x) (((x) >> S_UPCS_PIPE_CONFIG) & M_UPCS_PIPE_CONFIG) + +#define S_TX15_DISABLE 15 +#define V_TX15_DISABLE(x) ((x) << S_TX15_DISABLE) +#define F_TX15_DISABLE V_TX15_DISABLE(1U) + +#define S_TX14_DISABLE 14 +#define V_TX14_DISABLE(x) ((x) << S_TX14_DISABLE) +#define F_TX14_DISABLE V_TX14_DISABLE(1U) + +#define S_TX13_DISABLE 13 +#define V_TX13_DISABLE(x) ((x) << S_TX13_DISABLE) +#define F_TX13_DISABLE V_TX13_DISABLE(1U) + +#define S_TX12_DISABLE 12 +#define V_TX12_DISABLE(x) ((x) << S_TX12_DISABLE) +#define F_TX12_DISABLE V_TX12_DISABLE(1U) + +#define S_TX11_DISABLE 11 +#define V_TX11_DISABLE(x) ((x) << S_TX11_DISABLE) +#define F_TX11_DISABLE V_TX11_DISABLE(1U) + +#define S_TX10_DISABLE 10 +#define V_TX10_DISABLE(x) ((x) << S_TX10_DISABLE) +#define F_TX10_DISABLE V_TX10_DISABLE(1U) + +#define S_TX9_DISABLE 9 +#define V_TX9_DISABLE(x) ((x) << S_TX9_DISABLE) +#define F_TX9_DISABLE V_TX9_DISABLE(1U) + +#define S_TX8_DISABLE 8 +#define V_TX8_DISABLE(x) ((x) << S_TX8_DISABLE) +#define F_TX8_DISABLE V_TX8_DISABLE(1U) + +#define S_TX7_DISABLE 7 +#define V_TX7_DISABLE(x) ((x) << S_TX7_DISABLE) +#define F_TX7_DISABLE V_TX7_DISABLE(1U) + +#define S_TX6_DISABLE 6 +#define V_TX6_DISABLE(x) ((x) << S_TX6_DISABLE) +#define F_TX6_DISABLE V_TX6_DISABLE(1U) + +#define S_TX5_DISABLE 5 +#define V_TX5_DISABLE(x) ((x) << S_TX5_DISABLE) +#define F_TX5_DISABLE V_TX5_DISABLE(1U) + +#define S_TX4_DISABLE 4 +#define V_TX4_DISABLE(x) ((x) << S_TX4_DISABLE) +#define F_TX4_DISABLE V_TX4_DISABLE(1U) + +#define S_TX3_DISABLE 3 +#define V_TX3_DISABLE(x) ((x) << S_TX3_DISABLE) +#define F_TX3_DISABLE V_TX3_DISABLE(1U) + +#define S_TX2_DISABLE 2 +#define V_TX2_DISABLE(x) ((x) << S_TX2_DISABLE) +#define F_TX2_DISABLE V_TX2_DISABLE(1U) + +#define S_TX1_DISABLE 1 +#define V_TX1_DISABLE(x) ((x) << S_TX1_DISABLE) +#define F_TX1_DISABLE V_TX1_DISABLE(1U) + +#define S_TX0_DISABLE 0 +#define V_TX0_DISABLE(x) ((x) << S_TX0_DISABLE) +#define F_TX0_DISABLE V_TX0_DISABLE(1U) + #define A_PCIE_PDEBUG_REG_0X0 0x0 #define A_PCIE_PDEBUG_REG_0X1 0x1 #define A_PCIE_PDEBUG_REG_0X2 0x2 @@ -11668,6 +14476,40 @@ #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) +#define A_DBG_GPIO_OUT 0x6010 + +#define S_GPIO23_OUT_VAL 23 +#define V_GPIO23_OUT_VAL(x) ((x) << S_GPIO23_OUT_VAL) +#define F_GPIO23_OUT_VAL V_GPIO23_OUT_VAL(1U) + +#define S_GPIO22_OUT_VAL 22 +#define V_GPIO22_OUT_VAL(x) ((x) << S_GPIO22_OUT_VAL) +#define F_GPIO22_OUT_VAL V_GPIO22_OUT_VAL(1U) + +#define S_GPIO21_OUT_VAL 21 +#define V_GPIO21_OUT_VAL(x) ((x) << S_GPIO21_OUT_VAL) +#define F_GPIO21_OUT_VAL V_GPIO21_OUT_VAL(1U) + +#define S_GPIO20_OUT_VAL 20 +#define V_GPIO20_OUT_VAL(x) ((x) << S_GPIO20_OUT_VAL) +#define F_GPIO20_OUT_VAL V_GPIO20_OUT_VAL(1U) + +#define S_T7_GPIO19_OUT_VAL 19 +#define V_T7_GPIO19_OUT_VAL(x) ((x) << S_T7_GPIO19_OUT_VAL) +#define F_T7_GPIO19_OUT_VAL V_T7_GPIO19_OUT_VAL(1U) + +#define S_T7_GPIO18_OUT_VAL 18 +#define V_T7_GPIO18_OUT_VAL(x) ((x) << S_T7_GPIO18_OUT_VAL) +#define F_T7_GPIO18_OUT_VAL V_T7_GPIO18_OUT_VAL(1U) + +#define S_T7_GPIO17_OUT_VAL 17 +#define V_T7_GPIO17_OUT_VAL(x) ((x) << S_T7_GPIO17_OUT_VAL) +#define F_T7_GPIO17_OUT_VAL V_T7_GPIO17_OUT_VAL(1U) + +#define S_T7_GPIO16_OUT_VAL 16 +#define V_T7_GPIO16_OUT_VAL(x) ((x) << S_T7_GPIO16_OUT_VAL) +#define F_T7_GPIO16_OUT_VAL V_T7_GPIO16_OUT_VAL(1U) + #define A_DBG_GPIO_IN 0x6014 #define S_GPIO15_CHG_DET 31 @@ -11798,6 +14640,38 @@ #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN) #define F_GPIO0_IN V_GPIO0_IN(1U) +#define S_GPIO23_IN 23 +#define V_GPIO23_IN(x) ((x) << S_GPIO23_IN) +#define F_GPIO23_IN V_GPIO23_IN(1U) + +#define S_GPIO22_IN 22 +#define V_GPIO22_IN(x) ((x) << S_GPIO22_IN) +#define F_GPIO22_IN V_GPIO22_IN(1U) + +#define S_GPIO21_IN 21 +#define V_GPIO21_IN(x) ((x) << S_GPIO21_IN) +#define F_GPIO21_IN V_GPIO21_IN(1U) + +#define S_GPIO20_IN 20 +#define V_GPIO20_IN(x) ((x) << S_GPIO20_IN) +#define F_GPIO20_IN V_GPIO20_IN(1U) + +#define S_T7_GPIO19_IN 19 +#define V_T7_GPIO19_IN(x) ((x) << S_T7_GPIO19_IN) +#define F_T7_GPIO19_IN V_T7_GPIO19_IN(1U) + +#define S_T7_GPIO18_IN 18 +#define V_T7_GPIO18_IN(x) ((x) << S_T7_GPIO18_IN) +#define F_T7_GPIO18_IN V_T7_GPIO18_IN(1U) + +#define S_T7_GPIO17_IN 17 +#define V_T7_GPIO17_IN(x) ((x) << S_T7_GPIO17_IN) +#define F_T7_GPIO17_IN V_T7_GPIO17_IN(1U) + +#define S_T7_GPIO16_IN 16 +#define V_T7_GPIO16_IN(x) ((x) << S_T7_GPIO16_IN) +#define F_T7_GPIO16_IN V_T7_GPIO16_IN(1U) + #define A_DBG_INT_ENABLE 0x6018 #define S_IBM_FDL_FAIL_INT_ENBL 25 @@ -11920,6 +14794,58 @@ #define V_GPIO16(x) ((x) << S_GPIO16) #define F_GPIO16 V_GPIO16(1U) +#define S_USBFIFOPARERR 12 +#define V_USBFIFOPARERR(x) ((x) << S_USBFIFOPARERR) +#define F_USBFIFOPARERR V_USBFIFOPARERR(1U) + +#define S_T7_IBM_FDL_FAIL_INT_ENBL 11 +#define V_T7_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_T7_IBM_FDL_FAIL_INT_ENBL) +#define F_T7_IBM_FDL_FAIL_INT_ENBL V_T7_IBM_FDL_FAIL_INT_ENBL(1U) + +#define S_T7_PLL_LOCK_LOST_INT_ENBL 10 +#define V_T7_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_T7_PLL_LOCK_LOST_INT_ENBL) +#define F_T7_PLL_LOCK_LOST_INT_ENBL V_T7_PLL_LOCK_LOST_INT_ENBL(1U) + +#define S_M1_LOCK 9 +#define V_M1_LOCK(x) ((x) << S_M1_LOCK) +#define F_M1_LOCK V_M1_LOCK(1U) + +#define S_T7_PCIE_LOCK 8 +#define V_T7_PCIE_LOCK(x) ((x) << S_T7_PCIE_LOCK) +#define F_T7_PCIE_LOCK V_T7_PCIE_LOCK(1U) + +#define S_T7_U_LOCK 7 +#define V_T7_U_LOCK(x) ((x) << S_T7_U_LOCK) +#define F_T7_U_LOCK V_T7_U_LOCK(1U) + +#define S_MAC_LOCK 6 +#define V_MAC_LOCK(x) ((x) << S_MAC_LOCK) +#define F_MAC_LOCK V_MAC_LOCK(1U) + +#define S_ARM_LOCK 5 +#define V_ARM_LOCK(x) ((x) << S_ARM_LOCK) +#define F_ARM_LOCK V_ARM_LOCK(1U) + +#define S_M0_LOCK 4 +#define V_M0_LOCK(x) ((x) << S_M0_LOCK) +#define F_M0_LOCK V_M0_LOCK(1U) + +#define S_XGPBUS_LOCK 3 +#define V_XGPBUS_LOCK(x) ((x) << S_XGPBUS_LOCK) +#define F_XGPBUS_LOCK V_XGPBUS_LOCK(1U) + +#define S_XGPHY_LOCK 2 +#define V_XGPHY_LOCK(x) ((x) << S_XGPHY_LOCK) +#define F_XGPHY_LOCK V_XGPHY_LOCK(1U) + +#define S_USB_LOCK 1 +#define V_USB_LOCK(x) ((x) << S_USB_LOCK) +#define F_USB_LOCK V_USB_LOCK(1U) + +#define S_T7_C_LOCK 0 +#define V_T7_C_LOCK(x) ((x) << S_T7_C_LOCK) +#define F_T7_C_LOCK V_T7_C_LOCK(1U) + #define A_DBG_INT_CAUSE 0x601c #define S_IBM_FDL_FAIL_INT_CAUSE 25 @@ -11938,6 +14864,14 @@ #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE) #define F_PLL_LOCK_LOST_INT_CAUSE V_PLL_LOCK_LOST_INT_CAUSE(1U) +#define S_T7_IBM_FDL_FAIL_INT_CAUSE 11 +#define V_T7_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_T7_IBM_FDL_FAIL_INT_CAUSE) +#define F_T7_IBM_FDL_FAIL_INT_CAUSE V_T7_IBM_FDL_FAIL_INT_CAUSE(1U) + +#define S_T7_PLL_LOCK_LOST_INT_CAUSE 10 +#define V_T7_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_T7_PLL_LOCK_LOST_INT_CAUSE) +#define F_T7_PLL_LOCK_LOST_INT_CAUSE V_T7_PLL_LOCK_LOST_INT_CAUSE(1U) + #define A_DBG_DBG0_RST_VALUE 0x6020 #define S_DEBUGDATA 0 @@ -11977,6 +14911,10 @@ #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN) #define F_C_OCLK_EN V_C_OCLK_EN(1U) +#define S_INIC_MODE_EN 0 +#define V_INIC_MODE_EN(x) ((x) << S_INIC_MODE_EN) +#define F_INIC_MODE_EN V_INIC_MODE_EN(1U) + #define A_DBG_PLL_LOCK 0x602c #define S_PLL_P_LOCK 20 @@ -12003,6 +14941,38 @@ #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK) #define F_PLL_C_LOCK V_PLL_C_LOCK(1U) +#define S_T7_PLL_M_LOCK 9 +#define V_T7_PLL_M_LOCK(x) ((x) << S_T7_PLL_M_LOCK) +#define F_T7_PLL_M_LOCK V_T7_PLL_M_LOCK(1U) + +#define S_PLL_PCIE_LOCK 8 +#define V_PLL_PCIE_LOCK(x) ((x) << S_PLL_PCIE_LOCK) +#define F_PLL_PCIE_LOCK V_PLL_PCIE_LOCK(1U) + +#define S_T7_PLL_U_LOCK 7 +#define V_T7_PLL_U_LOCK(x) ((x) << S_T7_PLL_U_LOCK) +#define F_T7_PLL_U_LOCK V_T7_PLL_U_LOCK(1U) + +#define S_PLL_MAC_LOCK 6 +#define V_PLL_MAC_LOCK(x) ((x) << S_PLL_MAC_LOCK) +#define F_PLL_MAC_LOCK V_PLL_MAC_LOCK(1U) + +#define S_PLL_ARM_LOCK 5 +#define V_PLL_ARM_LOCK(x) ((x) << S_PLL_ARM_LOCK) +#define F_PLL_ARM_LOCK V_PLL_ARM_LOCK(1U) + +#define S_PLL_XGPBUS_LOCK 3 +#define V_PLL_XGPBUS_LOCK(x) ((x) << S_PLL_XGPBUS_LOCK) +#define F_PLL_XGPBUS_LOCK V_PLL_XGPBUS_LOCK(1U) + +#define S_PLL_XGPHY_LOCK 2 +#define V_PLL_XGPHY_LOCK(x) ((x) << S_PLL_XGPHY_LOCK) +#define F_PLL_XGPHY_LOCK V_PLL_XGPHY_LOCK(1U) + +#define S_PLL_USB_LOCK 1 +#define V_PLL_USB_LOCK(x) ((x) << S_PLL_USB_LOCK) +#define F_PLL_USB_LOCK V_PLL_USB_LOCK(1U) + #define A_DBG_GPIO_ACT_LOW 0x6030 #define S_P_LOCK_ACT_LOW 21 @@ -12109,6 +15079,48 @@ #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW) #define F_GPIO16_ACT_LOW V_GPIO16_ACT_LOW(1U) +#define A_DBG_PLL_LOCK_ACT_LOW 0x6030 + +#define S_M1_LOCK_ACT_LOW 9 +#define V_M1_LOCK_ACT_LOW(x) ((x) << S_M1_LOCK_ACT_LOW) +#define F_M1_LOCK_ACT_LOW V_M1_LOCK_ACT_LOW(1U) + +#define S_PCIE_LOCK_ACT_LOW 8 +#define V_PCIE_LOCK_ACT_LOW(x) ((x) << S_PCIE_LOCK_ACT_LOW) +#define F_PCIE_LOCK_ACT_LOW V_PCIE_LOCK_ACT_LOW(1U) + +#define S_T7_U_LOCK_ACT_LOW 7 +#define V_T7_U_LOCK_ACT_LOW(x) ((x) << S_T7_U_LOCK_ACT_LOW) +#define F_T7_U_LOCK_ACT_LOW V_T7_U_LOCK_ACT_LOW(1U) + +#define S_MAC_LOCK_ACT_LOW 6 +#define V_MAC_LOCK_ACT_LOW(x) ((x) << S_MAC_LOCK_ACT_LOW) +#define F_MAC_LOCK_ACT_LOW V_MAC_LOCK_ACT_LOW(1U) + +#define S_ARM_LOCK_ACT_LOW 5 +#define V_ARM_LOCK_ACT_LOW(x) ((x) << S_ARM_LOCK_ACT_LOW) +#define F_ARM_LOCK_ACT_LOW V_ARM_LOCK_ACT_LOW(1U) + +#define S_M0_LOCK_ACT_LOW 4 +#define V_M0_LOCK_ACT_LOW(x) ((x) << S_M0_LOCK_ACT_LOW) +#define F_M0_LOCK_ACT_LOW V_M0_LOCK_ACT_LOW(1U) + +#define S_XGPBUS_LOCK_ACT_LOW 3 +#define V_XGPBUS_LOCK_ACT_LOW(x) ((x) << S_XGPBUS_LOCK_ACT_LOW) +#define F_XGPBUS_LOCK_ACT_LOW V_XGPBUS_LOCK_ACT_LOW(1U) + +#define S_XGPHY_LOCK_ACT_LOW 2 +#define V_XGPHY_LOCK_ACT_LOW(x) ((x) << S_XGPHY_LOCK_ACT_LOW) +#define F_XGPHY_LOCK_ACT_LOW V_XGPHY_LOCK_ACT_LOW(1U) + +#define S_USB_LOCK_ACT_LOW 1 +#define V_USB_LOCK_ACT_LOW(x) ((x) << S_USB_LOCK_ACT_LOW) +#define F_USB_LOCK_ACT_LOW V_USB_LOCK_ACT_LOW(1U) + +#define S_T7_C_LOCK_ACT_LOW 0 +#define V_T7_C_LOCK_ACT_LOW(x) ((x) << S_T7_C_LOCK_ACT_LOW) +#define F_T7_C_LOCK_ACT_LOW V_T7_C_LOCK_ACT_LOW(1U) + #define A_DBG_EFUSE_BYTE0_3 0x6034 #define A_DBG_EFUSE_BYTE4_7 0x6038 #define A_DBG_EFUSE_BYTE8_11 0x603c @@ -12140,6 +15152,32 @@ #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE) #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE) +#define A_T7_DBG_STATIC_U_PLL_CONF1 0x6044 + +#define S_STATIC_U_PLL_RANGE 22 +#define M_STATIC_U_PLL_RANGE 0x7U +#define V_STATIC_U_PLL_RANGE(x) ((x) << S_STATIC_U_PLL_RANGE) +#define G_STATIC_U_PLL_RANGE(x) (((x) >> S_STATIC_U_PLL_RANGE) & M_STATIC_U_PLL_RANGE) + +#define S_STATIC_U_PLL_DIVQ 17 +#define M_STATIC_U_PLL_DIVQ 0x1fU +#define V_STATIC_U_PLL_DIVQ(x) ((x) << S_STATIC_U_PLL_DIVQ) +#define G_STATIC_U_PLL_DIVQ(x) (((x) >> S_STATIC_U_PLL_DIVQ) & M_STATIC_U_PLL_DIVQ) + +#define S_STATIC_U_PLL_DIVFI 8 +#define M_STATIC_U_PLL_DIVFI 0x1ffU +#define V_STATIC_U_PLL_DIVFI(x) ((x) << S_STATIC_U_PLL_DIVFI) +#define G_STATIC_U_PLL_DIVFI(x) (((x) >> S_STATIC_U_PLL_DIVFI) & M_STATIC_U_PLL_DIVFI) + +#define S_STATIC_U_PLL_DIVR 2 +#define M_STATIC_U_PLL_DIVR 0x3fU +#define V_STATIC_U_PLL_DIVR(x) ((x) << S_STATIC_U_PLL_DIVR) +#define G_STATIC_U_PLL_DIVR(x) (((x) >> S_STATIC_U_PLL_DIVR) & M_STATIC_U_PLL_DIVR) + +#define S_T7_1_STATIC_U_PLL_BYPASS 1 +#define V_T7_1_STATIC_U_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_U_PLL_BYPASS) +#define F_T7_1_STATIC_U_PLL_BYPASS V_T7_1_STATIC_U_PLL_BYPASS(1U) + #define A_DBG_STATIC_C_PLL_CONF 0x6048 #define S_STATIC_C_PLL_MULT 23 @@ -12167,6 +15205,26 @@ #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE) #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE) +#define A_T7_DBG_STATIC_U_PLL_CONF2 0x6048 + +#define S_STATIC_U_PLL_SSMF 5 +#define M_STATIC_U_PLL_SSMF 0xfU +#define V_STATIC_U_PLL_SSMF(x) ((x) << S_STATIC_U_PLL_SSMF) +#define G_STATIC_U_PLL_SSMF(x) (((x) >> S_STATIC_U_PLL_SSMF) & M_STATIC_U_PLL_SSMF) + +#define S_STATIC_U_PLL_SSMD 2 +#define M_STATIC_U_PLL_SSMD 0x7U +#define V_STATIC_U_PLL_SSMD(x) ((x) << S_STATIC_U_PLL_SSMD) +#define G_STATIC_U_PLL_SSMD(x) (((x) >> S_STATIC_U_PLL_SSMD) & M_STATIC_U_PLL_SSMD) + +#define S_STATIC_U_PLL_SSDS 1 +#define V_STATIC_U_PLL_SSDS(x) ((x) << S_STATIC_U_PLL_SSDS) +#define F_STATIC_U_PLL_SSDS V_STATIC_U_PLL_SSDS(1U) + +#define S_STATIC_U_PLL_SSE 0 +#define V_STATIC_U_PLL_SSE(x) ((x) << S_STATIC_U_PLL_SSE) +#define F_STATIC_U_PLL_SSE V_STATIC_U_PLL_SSE(1U) + #define A_DBG_STATIC_M_PLL_CONF 0x604c #define S_STATIC_M_PLL_MULT 23 @@ -12194,6 +15252,32 @@ #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE) #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE) +#define A_T7_DBG_STATIC_C_PLL_CONF1 0x604c + +#define S_STATIC_C_PLL_RANGE 22 +#define M_STATIC_C_PLL_RANGE 0x7U +#define V_STATIC_C_PLL_RANGE(x) ((x) << S_STATIC_C_PLL_RANGE) +#define G_STATIC_C_PLL_RANGE(x) (((x) >> S_STATIC_C_PLL_RANGE) & M_STATIC_C_PLL_RANGE) + +#define S_STATIC_C_PLL_DIVQ 17 +#define M_STATIC_C_PLL_DIVQ 0x1fU +#define V_STATIC_C_PLL_DIVQ(x) ((x) << S_STATIC_C_PLL_DIVQ) +#define G_STATIC_C_PLL_DIVQ(x) (((x) >> S_STATIC_C_PLL_DIVQ) & M_STATIC_C_PLL_DIVQ) + +#define S_STATIC_C_PLL_DIVFI 8 +#define M_STATIC_C_PLL_DIVFI 0x1ffU +#define V_STATIC_C_PLL_DIVFI(x) ((x) << S_STATIC_C_PLL_DIVFI) +#define G_STATIC_C_PLL_DIVFI(x) (((x) >> S_STATIC_C_PLL_DIVFI) & M_STATIC_C_PLL_DIVFI) + +#define S_STATIC_C_PLL_DIVR 2 +#define M_STATIC_C_PLL_DIVR 0x3fU +#define V_STATIC_C_PLL_DIVR(x) ((x) << S_STATIC_C_PLL_DIVR) +#define G_STATIC_C_PLL_DIVR(x) (((x) >> S_STATIC_C_PLL_DIVR) & M_STATIC_C_PLL_DIVR) + +#define S_T7_1_STATIC_C_PLL_BYPASS 1 +#define V_T7_1_STATIC_C_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_C_PLL_BYPASS) +#define F_T7_1_STATIC_C_PLL_BYPASS V_T7_1_STATIC_C_PLL_BYPASS(1U) + #define A_DBG_STATIC_KX_PLL_CONF 0x6050 #define S_STATIC_KX_PLL_C 21 @@ -12226,6 +15310,26 @@ #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P) #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P) +#define A_T7_DBG_STATIC_C_PLL_CONF2 0x6050 + +#define S_STATIC_C_PLL_SSMF 5 +#define M_STATIC_C_PLL_SSMF 0xfU +#define V_STATIC_C_PLL_SSMF(x) ((x) << S_STATIC_C_PLL_SSMF) +#define G_STATIC_C_PLL_SSMF(x) (((x) >> S_STATIC_C_PLL_SSMF) & M_STATIC_C_PLL_SSMF) + +#define S_STATIC_C_PLL_SSMD 2 +#define M_STATIC_C_PLL_SSMD 0x7U +#define V_STATIC_C_PLL_SSMD(x) ((x) << S_STATIC_C_PLL_SSMD) +#define G_STATIC_C_PLL_SSMD(x) (((x) >> S_STATIC_C_PLL_SSMD) & M_STATIC_C_PLL_SSMD) + +#define S_STATIC_C_PLL_SSDS 1 +#define V_STATIC_C_PLL_SSDS(x) ((x) << S_STATIC_C_PLL_SSDS) +#define F_STATIC_C_PLL_SSDS V_STATIC_C_PLL_SSDS(1U) + +#define S_STATIC_C_PLL_SSE 0 +#define V_STATIC_C_PLL_SSE(x) ((x) << S_STATIC_C_PLL_SSE) +#define F_STATIC_C_PLL_SSE V_STATIC_C_PLL_SSE(1U) + #define A_DBG_STATIC_KR_PLL_CONF 0x6054 #define S_STATIC_KR_PLL_C 21 @@ -12258,6 +15362,38 @@ #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P) #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P) +#define A_DBG_STATIC_PLL_DFS_CONF 0x6054 + +#define S_STATIC_U_DFS_ACK 23 +#define V_STATIC_U_DFS_ACK(x) ((x) << S_STATIC_U_DFS_ACK) +#define F_STATIC_U_DFS_ACK V_STATIC_U_DFS_ACK(1U) + +#define S_STATIC_C_DFS_ACK 22 +#define V_STATIC_C_DFS_ACK(x) ((x) << S_STATIC_C_DFS_ACK) +#define F_STATIC_C_DFS_ACK V_STATIC_C_DFS_ACK(1U) + +#define S_STATIC_U_DFS_DIVFI 13 +#define M_STATIC_U_DFS_DIVFI 0x1ffU +#define V_STATIC_U_DFS_DIVFI(x) ((x) << S_STATIC_U_DFS_DIVFI) +#define G_STATIC_U_DFS_DIVFI(x) (((x) >> S_STATIC_U_DFS_DIVFI) & M_STATIC_U_DFS_DIVFI) + +#define S_STATIC_U_DFS_NEWDIV 12 +#define V_STATIC_U_DFS_NEWDIV(x) ((x) << S_STATIC_U_DFS_NEWDIV) +#define F_STATIC_U_DFS_NEWDIV V_STATIC_U_DFS_NEWDIV(1U) + +#define S_T7_STATIC_U_DFS_ENABLE 11 +#define V_T7_STATIC_U_DFS_ENABLE(x) ((x) << S_T7_STATIC_U_DFS_ENABLE) +#define F_T7_STATIC_U_DFS_ENABLE V_T7_STATIC_U_DFS_ENABLE(1U) + +#define S_STATIC_C_DFS_DIVFI 2 +#define M_STATIC_C_DFS_DIVFI 0x1ffU +#define V_STATIC_C_DFS_DIVFI(x) ((x) << S_STATIC_C_DFS_DIVFI) +#define G_STATIC_C_DFS_DIVFI(x) (((x) >> S_STATIC_C_DFS_DIVFI) & M_STATIC_C_DFS_DIVFI) + +#define S_STATIC_C_DFS_NEWDIV 1 +#define V_STATIC_C_DFS_NEWDIV(x) ((x) << S_STATIC_C_DFS_NEWDIV) +#define F_STATIC_C_DFS_NEWDIV V_STATIC_C_DFS_NEWDIV(1U) + #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058 #define S_STATIC_M_PLL_RESET 30 @@ -12343,6 +15479,14 @@ #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL) #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL) +#define S_T7_STATIC_LVDS_CLKOUT_EN 21 +#define V_T7_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_T7_STATIC_LVDS_CLKOUT_EN) +#define F_T7_STATIC_LVDS_CLKOUT_EN V_T7_STATIC_LVDS_CLKOUT_EN(1U) + +#define S_T7_EXPHYCLK_SEL_EN 16 +#define V_T7_EXPHYCLK_SEL_EN(x) ((x) << S_T7_EXPHYCLK_SEL_EN) +#define F_T7_EXPHYCLK_SEL_EN V_T7_EXPHYCLK_SEL_EN(1U) + #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c #define S_M_OCLK_MUXSEL 12 @@ -12467,16 +15611,6 @@ #define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0) #define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0) -#define S_T6_RD_ADDR1 11 -#define M_T6_RD_ADDR1 0x1ffU -#define V_T6_RD_ADDR1(x) ((x) << S_T6_RD_ADDR1) -#define G_T6_RD_ADDR1(x) (((x) >> S_T6_RD_ADDR1) & M_T6_RD_ADDR1) - -#define S_T6_RD_ADDR0 2 -#define M_T6_RD_ADDR0 0x1ffU -#define V_T6_RD_ADDR0(x) ((x) << S_T6_RD_ADDR0) -#define G_T6_RD_ADDR0(x) (((x) >> S_T6_RD_ADDR0) & M_T6_RD_ADDR0) - #define A_DBG_TRACE_WRADDR 0x6090 #define S_WR_POINTER_ADDR1 16 @@ -12499,16 +15633,6 @@ #define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0) #define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0) -#define S_T6_WR_POINTER_ADDR1 16 -#define M_T6_WR_POINTER_ADDR1 0x1ffU -#define V_T6_WR_POINTER_ADDR1(x) ((x) << S_T6_WR_POINTER_ADDR1) -#define G_T6_WR_POINTER_ADDR1(x) (((x) >> S_T6_WR_POINTER_ADDR1) & M_T6_WR_POINTER_ADDR1) - -#define S_T6_WR_POINTER_ADDR0 0 -#define M_T6_WR_POINTER_ADDR0 0x1ffU -#define V_T6_WR_POINTER_ADDR0(x) ((x) << S_T6_WR_POINTER_ADDR0) -#define G_T6_WR_POINTER_ADDR0(x) (((x) >> S_T6_WR_POINTER_ADDR0) & M_T6_WR_POINTER_ADDR0) - #define A_DBG_TRACE0_DATA_OUT 0x6094 #define A_DBG_TRACE1_DATA_OUT 0x6098 #define A_DBG_FUSE_SENSE_DONE 0x609c @@ -12575,7 +15699,52 @@ #define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST) #define F_T6_TVSENSE_RST V_T6_TVSENSE_RST(1U) +#define A_DBG_PVT_EN1 0x60a8 + +#define S_PVT_TRIMO 18 +#define M_PVT_TRIMO 0x3fU +#define V_PVT_TRIMO(x) ((x) << S_PVT_TRIMO) +#define G_PVT_TRIMO(x) (((x) >> S_PVT_TRIMO) & M_PVT_TRIMO) + +#define S_PVT_TRIMG 13 +#define M_PVT_TRIMG 0x1fU +#define V_PVT_TRIMG(x) ((x) << S_PVT_TRIMG) +#define G_PVT_TRIMG(x) (((x) >> S_PVT_TRIMG) & M_PVT_TRIMG) + +#define S_PVT_VSAMPLE 12 +#define V_PVT_VSAMPLE(x) ((x) << S_PVT_VSAMPLE) +#define F_PVT_VSAMPLE V_PVT_VSAMPLE(1U) + +#define S_PVT_PSAMPLE 10 +#define M_PVT_PSAMPLE 0x3U +#define V_PVT_PSAMPLE(x) ((x) << S_PVT_PSAMPLE) +#define G_PVT_PSAMPLE(x) (((x) >> S_PVT_PSAMPLE) & M_PVT_PSAMPLE) + +#define S_PVT_ENA 9 +#define V_PVT_ENA(x) ((x) << S_PVT_ENA) +#define F_PVT_ENA V_PVT_ENA(1U) + +#define S_PVT_RESET 8 +#define V_PVT_RESET(x) ((x) << S_PVT_RESET) +#define F_PVT_RESET V_PVT_RESET(1U) + +#define S_PVT_DIV 0 +#define M_PVT_DIV 0xffU +#define V_PVT_DIV(x) ((x) << S_PVT_DIV) +#define G_PVT_DIV(x) (((x) >> S_PVT_DIV) & M_PVT_DIV) + #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac +#define A_DBG_PVT_EN2 0x60ac + +#define S_PVT_DATA_OUT 1 +#define M_PVT_DATA_OUT 0x3ffU +#define V_PVT_DATA_OUT(x) ((x) << S_PVT_DATA_OUT) +#define G_PVT_DATA_OUT(x) (((x) >> S_PVT_DATA_OUT) & M_PVT_DATA_OUT) + +#define S_PVT_DATA_VALID 0 +#define V_PVT_DATA_VALID(x) ((x) << S_PVT_DATA_VALID) +#define F_PVT_DATA_VALID V_PVT_DATA_VALID(1U) + #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4 @@ -12638,6 +15807,36 @@ #define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE) #define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE) +#define A_DBG_STATIC_M0_PLL_CONF1 0x60b8 + +#define S_STATIC_M0_PLL_RANGE 22 +#define M_STATIC_M0_PLL_RANGE 0x7U +#define V_STATIC_M0_PLL_RANGE(x) ((x) << S_STATIC_M0_PLL_RANGE) +#define G_STATIC_M0_PLL_RANGE(x) (((x) >> S_STATIC_M0_PLL_RANGE) & M_STATIC_M0_PLL_RANGE) + +#define S_STATIC_M0_PLL_DIVQ 17 +#define M_STATIC_M0_PLL_DIVQ 0x1fU +#define V_STATIC_M0_PLL_DIVQ(x) ((x) << S_STATIC_M0_PLL_DIVQ) +#define G_STATIC_M0_PLL_DIVQ(x) (((x) >> S_STATIC_M0_PLL_DIVQ) & M_STATIC_M0_PLL_DIVQ) + +#define S_STATIC_M0_PLL_DIVFI 8 +#define M_STATIC_M0_PLL_DIVFI 0x1ffU +#define V_STATIC_M0_PLL_DIVFI(x) ((x) << S_STATIC_M0_PLL_DIVFI) +#define G_STATIC_M0_PLL_DIVFI(x) (((x) >> S_STATIC_M0_PLL_DIVFI) & M_STATIC_M0_PLL_DIVFI) + +#define S_STATIC_M0_PLL_DIVR 2 +#define M_STATIC_M0_PLL_DIVR 0x3fU +#define V_STATIC_M0_PLL_DIVR(x) ((x) << S_STATIC_M0_PLL_DIVR) +#define G_STATIC_M0_PLL_DIVR(x) (((x) >> S_STATIC_M0_PLL_DIVR) & M_STATIC_M0_PLL_DIVR) + +#define S_STATIC_M0_PLL_BYPASS 1 +#define V_STATIC_M0_PLL_BYPASS(x) ((x) << S_STATIC_M0_PLL_BYPASS) +#define F_STATIC_M0_PLL_BYPASS V_STATIC_M0_PLL_BYPASS(1U) + +#define S_STATIC_M0_PLL_RESET 0 +#define V_STATIC_M0_PLL_RESET(x) ((x) << S_STATIC_M0_PLL_RESET) +#define F_STATIC_M0_PLL_RESET V_STATIC_M0_PLL_RESET(1U) + #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc #define S_T5_STATIC_M_PLL_DCO_BYPASS 23 @@ -12715,6 +15914,50 @@ #define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE) #define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE) +#define A_DBG_STATIC_M0_PLL_CONF2 0x60bc + +#define S_T7_STATIC_SWMC1RST_ 14 +#define V_T7_STATIC_SWMC1RST_(x) ((x) << S_T7_STATIC_SWMC1RST_) +#define F_T7_STATIC_SWMC1RST_ V_T7_STATIC_SWMC1RST_(1U) + +#define S_T7_STATIC_SWMC1CFGRST_ 13 +#define V_T7_STATIC_SWMC1CFGRST_(x) ((x) << S_T7_STATIC_SWMC1CFGRST_) +#define F_T7_STATIC_SWMC1CFGRST_ V_T7_STATIC_SWMC1CFGRST_(1U) + +#define S_T7_STATIC_PHY0RECRST_ 12 +#define V_T7_STATIC_PHY0RECRST_(x) ((x) << S_T7_STATIC_PHY0RECRST_) +#define F_T7_STATIC_PHY0RECRST_ V_T7_STATIC_PHY0RECRST_(1U) + +#define S_T7_STATIC_PHY1RECRST_ 11 +#define V_T7_STATIC_PHY1RECRST_(x) ((x) << S_T7_STATIC_PHY1RECRST_) +#define F_T7_STATIC_PHY1RECRST_ V_T7_STATIC_PHY1RECRST_(1U) + +#define S_T7_STATIC_SWMC0RST_ 10 +#define V_T7_STATIC_SWMC0RST_(x) ((x) << S_T7_STATIC_SWMC0RST_) +#define F_T7_STATIC_SWMC0RST_ V_T7_STATIC_SWMC0RST_(1U) + +#define S_T7_STATIC_SWMC0CFGRST_ 9 +#define V_T7_STATIC_SWMC0CFGRST_(x) ((x) << S_T7_STATIC_SWMC0CFGRST_) +#define F_T7_STATIC_SWMC0CFGRST_ V_T7_STATIC_SWMC0CFGRST_(1U) + +#define S_STATIC_M0_PLL_SSMF 5 +#define M_STATIC_M0_PLL_SSMF 0xfU +#define V_STATIC_M0_PLL_SSMF(x) ((x) << S_STATIC_M0_PLL_SSMF) +#define G_STATIC_M0_PLL_SSMF(x) (((x) >> S_STATIC_M0_PLL_SSMF) & M_STATIC_M0_PLL_SSMF) + +#define S_STATIC_M0_PLL_SSMD 2 +#define M_STATIC_M0_PLL_SSMD 0x7U +#define V_STATIC_M0_PLL_SSMD(x) ((x) << S_STATIC_M0_PLL_SSMD) +#define G_STATIC_M0_PLL_SSMD(x) (((x) >> S_STATIC_M0_PLL_SSMD) & M_STATIC_M0_PLL_SSMD) + +#define S_STATIC_M0_PLL_SSDS 1 +#define V_STATIC_M0_PLL_SSDS(x) ((x) << S_STATIC_M0_PLL_SSDS) +#define F_STATIC_M0_PLL_SSDS V_STATIC_M0_PLL_SSDS(1U) + +#define S_STATIC_M0_PLL_SSE 0 +#define V_STATIC_M0_PLL_SSE(x) ((x) << S_STATIC_M0_PLL_SSE) +#define F_STATIC_M0_PLL_SSE V_STATIC_M0_PLL_SSE(1U) + #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0 #define S_T5_STATIC_M_PLL_MULTPRE 30 @@ -12778,8 +16021,58 @@ #define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA) #define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA) +#define A_DBG_STATIC_MAC_PLL_CONF1 0x60c0 + +#define S_STATIC_MAC_PLL_RANGE 22 +#define M_STATIC_MAC_PLL_RANGE 0x7U +#define V_STATIC_MAC_PLL_RANGE(x) ((x) << S_STATIC_MAC_PLL_RANGE) +#define G_STATIC_MAC_PLL_RANGE(x) (((x) >> S_STATIC_MAC_PLL_RANGE) & M_STATIC_MAC_PLL_RANGE) + +#define S_STATIC_MAC_PLL_DIVQ 17 +#define M_STATIC_MAC_PLL_DIVQ 0x1fU +#define V_STATIC_MAC_PLL_DIVQ(x) ((x) << S_STATIC_MAC_PLL_DIVQ) +#define G_STATIC_MAC_PLL_DIVQ(x) (((x) >> S_STATIC_MAC_PLL_DIVQ) & M_STATIC_MAC_PLL_DIVQ) + +#define S_STATIC_MAC_PLL_DIVFI 8 +#define M_STATIC_MAC_PLL_DIVFI 0x1ffU +#define V_STATIC_MAC_PLL_DIVFI(x) ((x) << S_STATIC_MAC_PLL_DIVFI) +#define G_STATIC_MAC_PLL_DIVFI(x) (((x) >> S_STATIC_MAC_PLL_DIVFI) & M_STATIC_MAC_PLL_DIVFI) + +#define S_STATIC_MAC_PLL_DIVR 2 +#define M_STATIC_MAC_PLL_DIVR 0x3fU +#define V_STATIC_MAC_PLL_DIVR(x) ((x) << S_STATIC_MAC_PLL_DIVR) +#define G_STATIC_MAC_PLL_DIVR(x) (((x) >> S_STATIC_MAC_PLL_DIVR) & M_STATIC_MAC_PLL_DIVR) + +#define S_STATIC_MAC_PLL_BYPASS 1 +#define V_STATIC_MAC_PLL_BYPASS(x) ((x) << S_STATIC_MAC_PLL_BYPASS) +#define F_STATIC_MAC_PLL_BYPASS V_STATIC_MAC_PLL_BYPASS(1U) + +#define S_STATIC_MAC_PLL_RESET 0 +#define V_STATIC_MAC_PLL_RESET(x) ((x) << S_STATIC_MAC_PLL_RESET) +#define F_STATIC_MAC_PLL_RESET V_STATIC_MAC_PLL_RESET(1U) + #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4 +#define A_DBG_STATIC_MAC_PLL_CONF2 0x60c4 + +#define S_STATIC_MAC_PLL_SSMF 5 +#define M_STATIC_MAC_PLL_SSMF 0xfU +#define V_STATIC_MAC_PLL_SSMF(x) ((x) << S_STATIC_MAC_PLL_SSMF) +#define G_STATIC_MAC_PLL_SSMF(x) (((x) >> S_STATIC_MAC_PLL_SSMF) & M_STATIC_MAC_PLL_SSMF) + +#define S_STATIC_MAC_PLL_SSMD 2 +#define M_STATIC_MAC_PLL_SSMD 0x7U +#define V_STATIC_MAC_PLL_SSMD(x) ((x) << S_STATIC_MAC_PLL_SSMD) +#define G_STATIC_MAC_PLL_SSMD(x) (((x) >> S_STATIC_MAC_PLL_SSMD) & M_STATIC_MAC_PLL_SSMD) + +#define S_STATIC_MAC_PLL_SSDS 1 +#define V_STATIC_MAC_PLL_SSDS(x) ((x) << S_STATIC_MAC_PLL_SSDS) +#define F_STATIC_MAC_PLL_SSDS V_STATIC_MAC_PLL_SSDS(1U) + +#define S_STATIC_MAC_PLL_SSE 0 +#define V_STATIC_MAC_PLL_SSE(x) ((x) << S_STATIC_MAC_PLL_SSE) +#define F_STATIC_MAC_PLL_SSE V_STATIC_MAC_PLL_SSE(1U) + #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8 #define S_T5_STATIC_M_PLL_VCVTUNE 24 @@ -12835,6 +16128,36 @@ #define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT) #define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT) +#define A_DBG_STATIC_ARM_PLL_CONF1 0x60c8 + +#define S_STATIC_ARM_PLL_RANGE 22 +#define M_STATIC_ARM_PLL_RANGE 0x7U +#define V_STATIC_ARM_PLL_RANGE(x) ((x) << S_STATIC_ARM_PLL_RANGE) +#define G_STATIC_ARM_PLL_RANGE(x) (((x) >> S_STATIC_ARM_PLL_RANGE) & M_STATIC_ARM_PLL_RANGE) + +#define S_STATIC_ARM_PLL_DIVQ 17 +#define M_STATIC_ARM_PLL_DIVQ 0x1fU +#define V_STATIC_ARM_PLL_DIVQ(x) ((x) << S_STATIC_ARM_PLL_DIVQ) +#define G_STATIC_ARM_PLL_DIVQ(x) (((x) >> S_STATIC_ARM_PLL_DIVQ) & M_STATIC_ARM_PLL_DIVQ) + +#define S_STATIC_ARM_PLL_DIVFI 8 +#define M_STATIC_ARM_PLL_DIVFI 0x1ffU +#define V_STATIC_ARM_PLL_DIVFI(x) ((x) << S_STATIC_ARM_PLL_DIVFI) +#define G_STATIC_ARM_PLL_DIVFI(x) (((x) >> S_STATIC_ARM_PLL_DIVFI) & M_STATIC_ARM_PLL_DIVFI) + +#define S_STATIC_ARM_PLL_DIVR 2 +#define M_STATIC_ARM_PLL_DIVR 0x3fU +#define V_STATIC_ARM_PLL_DIVR(x) ((x) << S_STATIC_ARM_PLL_DIVR) +#define G_STATIC_ARM_PLL_DIVR(x) (((x) >> S_STATIC_ARM_PLL_DIVR) & M_STATIC_ARM_PLL_DIVR) + +#define S_STATIC_ARM_PLL_BYPASS 1 +#define V_STATIC_ARM_PLL_BYPASS(x) ((x) << S_STATIC_ARM_PLL_BYPASS) +#define F_STATIC_ARM_PLL_BYPASS V_STATIC_ARM_PLL_BYPASS(1U) + +#define S_STATIC_ARM_PLL_RESET 0 +#define V_STATIC_ARM_PLL_RESET(x) ((x) << S_STATIC_ARM_PLL_RESET) +#define F_STATIC_ARM_PLL_RESET V_STATIC_ARM_PLL_RESET(1U) + #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc #define S_T5_STATIC_PHY0RECRST_ 5 @@ -12913,6 +16236,26 @@ #define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_) #define F_STATIC_SWMC1CFGRST_ V_STATIC_SWMC1CFGRST_(1U) +#define A_DBG_STATIC_ARM_PLL_CONF2 0x60cc + +#define S_STATIC_ARM_PLL_SSMF 5 +#define M_STATIC_ARM_PLL_SSMF 0xfU +#define V_STATIC_ARM_PLL_SSMF(x) ((x) << S_STATIC_ARM_PLL_SSMF) +#define G_STATIC_ARM_PLL_SSMF(x) (((x) >> S_STATIC_ARM_PLL_SSMF) & M_STATIC_ARM_PLL_SSMF) + +#define S_STATIC_ARM_PLL_SSMD 2 +#define M_STATIC_ARM_PLL_SSMD 0x7U +#define V_STATIC_ARM_PLL_SSMD(x) ((x) << S_STATIC_ARM_PLL_SSMD) +#define G_STATIC_ARM_PLL_SSMD(x) (((x) >> S_STATIC_ARM_PLL_SSMD) & M_STATIC_ARM_PLL_SSMD) + +#define S_STATIC_ARM_PLL_SSDS 1 +#define V_STATIC_ARM_PLL_SSDS(x) ((x) << S_STATIC_ARM_PLL_SSDS) +#define F_STATIC_ARM_PLL_SSDS V_STATIC_ARM_PLL_SSDS(1U) + +#define S_STATIC_ARM_PLL_SSE 0 +#define V_STATIC_ARM_PLL_SSE(x) ((x) << S_STATIC_ARM_PLL_SSE) +#define F_STATIC_ARM_PLL_SSE V_STATIC_ARM_PLL_SSE(1U) + #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0 #define S_T5_STATIC_C_PLL_MULTFRAC 8 @@ -12937,6 +16280,36 @@ #define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE) #define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE) +#define A_DBG_STATIC_USB_PLL_CONF1 0x60d0 + +#define S_STATIC_USB_PLL_RANGE 22 +#define M_STATIC_USB_PLL_RANGE 0x7U +#define V_STATIC_USB_PLL_RANGE(x) ((x) << S_STATIC_USB_PLL_RANGE) +#define G_STATIC_USB_PLL_RANGE(x) (((x) >> S_STATIC_USB_PLL_RANGE) & M_STATIC_USB_PLL_RANGE) + +#define S_STATIC_USB_PLL_DIVQ 17 +#define M_STATIC_USB_PLL_DIVQ 0x1fU +#define V_STATIC_USB_PLL_DIVQ(x) ((x) << S_STATIC_USB_PLL_DIVQ) +#define G_STATIC_USB_PLL_DIVQ(x) (((x) >> S_STATIC_USB_PLL_DIVQ) & M_STATIC_USB_PLL_DIVQ) + +#define S_STATIC_USB_PLL_DIVFI 8 +#define M_STATIC_USB_PLL_DIVFI 0x1ffU +#define V_STATIC_USB_PLL_DIVFI(x) ((x) << S_STATIC_USB_PLL_DIVFI) +#define G_STATIC_USB_PLL_DIVFI(x) (((x) >> S_STATIC_USB_PLL_DIVFI) & M_STATIC_USB_PLL_DIVFI) + +#define S_STATIC_USB_PLL_DIVR 2 +#define M_STATIC_USB_PLL_DIVR 0x3fU +#define V_STATIC_USB_PLL_DIVR(x) ((x) << S_STATIC_USB_PLL_DIVR) +#define G_STATIC_USB_PLL_DIVR(x) (((x) >> S_STATIC_USB_PLL_DIVR) & M_STATIC_USB_PLL_DIVR) + +#define S_STATIC_USB_PLL_BYPASS 1 +#define V_STATIC_USB_PLL_BYPASS(x) ((x) << S_STATIC_USB_PLL_BYPASS) +#define F_STATIC_USB_PLL_BYPASS V_STATIC_USB_PLL_BYPASS(1U) + +#define S_STATIC_USB_PLL_RESET 0 +#define V_STATIC_USB_PLL_RESET(x) ((x) << S_STATIC_USB_PLL_RESET) +#define F_STATIC_USB_PLL_RESET V_STATIC_USB_PLL_RESET(1U) + #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4 #define S_T5_STATIC_C_PLL_DCO_BYPASS 23 @@ -13019,6 +16392,26 @@ #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE) #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE) +#define A_DBG_STATIC_USB_PLL_CONF2 0x60d4 + +#define S_STATIC_USB_PLL_SSMF 5 +#define M_STATIC_USB_PLL_SSMF 0xfU +#define V_STATIC_USB_PLL_SSMF(x) ((x) << S_STATIC_USB_PLL_SSMF) +#define G_STATIC_USB_PLL_SSMF(x) (((x) >> S_STATIC_USB_PLL_SSMF) & M_STATIC_USB_PLL_SSMF) + +#define S_STATIC_USB_PLL_SSMD 2 +#define M_STATIC_USB_PLL_SSMD 0x7U +#define V_STATIC_USB_PLL_SSMD(x) ((x) << S_STATIC_USB_PLL_SSMD) +#define G_STATIC_USB_PLL_SSMD(x) (((x) >> S_STATIC_USB_PLL_SSMD) & M_STATIC_USB_PLL_SSMD) + +#define S_STATIC_USB_PLL_SSDS 1 +#define V_STATIC_USB_PLL_SSDS(x) ((x) << S_STATIC_USB_PLL_SSDS) +#define F_STATIC_USB_PLL_SSDS V_STATIC_USB_PLL_SSDS(1U) + +#define S_STATIC_USB_PLL_SSE 0 +#define V_STATIC_USB_PLL_SSE(x) ((x) << S_STATIC_USB_PLL_SSE) +#define F_STATIC_USB_PLL_SSE V_STATIC_USB_PLL_SSE(1U) + #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8 #define S_T5_STATIC_C_PLL_MULTPRE 30 @@ -13082,8 +16475,58 @@ #define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA) #define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA) +#define A_DBG_STATIC_XGPHY_PLL_CONF1 0x60d8 + +#define S_STATIC_XGPHY_PLL_RANGE 22 +#define M_STATIC_XGPHY_PLL_RANGE 0x7U +#define V_STATIC_XGPHY_PLL_RANGE(x) ((x) << S_STATIC_XGPHY_PLL_RANGE) +#define G_STATIC_XGPHY_PLL_RANGE(x) (((x) >> S_STATIC_XGPHY_PLL_RANGE) & M_STATIC_XGPHY_PLL_RANGE) + +#define S_STATIC_XGPHY_PLL_DIVQ 17 +#define M_STATIC_XGPHY_PLL_DIVQ 0x1fU +#define V_STATIC_XGPHY_PLL_DIVQ(x) ((x) << S_STATIC_XGPHY_PLL_DIVQ) +#define G_STATIC_XGPHY_PLL_DIVQ(x) (((x) >> S_STATIC_XGPHY_PLL_DIVQ) & M_STATIC_XGPHY_PLL_DIVQ) + +#define S_STATIC_XGPHY_PLL_DIVFI 8 +#define M_STATIC_XGPHY_PLL_DIVFI 0x1ffU +#define V_STATIC_XGPHY_PLL_DIVFI(x) ((x) << S_STATIC_XGPHY_PLL_DIVFI) +#define G_STATIC_XGPHY_PLL_DIVFI(x) (((x) >> S_STATIC_XGPHY_PLL_DIVFI) & M_STATIC_XGPHY_PLL_DIVFI) + +#define S_STATIC_XGPHY_PLL_DIVR 2 +#define M_STATIC_XGPHY_PLL_DIVR 0x3fU +#define V_STATIC_XGPHY_PLL_DIVR(x) ((x) << S_STATIC_XGPHY_PLL_DIVR) +#define G_STATIC_XGPHY_PLL_DIVR(x) (((x) >> S_STATIC_XGPHY_PLL_DIVR) & M_STATIC_XGPHY_PLL_DIVR) + +#define S_STATIC_XGPHY_PLL_BYPASS 1 +#define V_STATIC_XGPHY_PLL_BYPASS(x) ((x) << S_STATIC_XGPHY_PLL_BYPASS) +#define F_STATIC_XGPHY_PLL_BYPASS V_STATIC_XGPHY_PLL_BYPASS(1U) + +#define S_STATIC_XGPHY_PLL_RESET 0 +#define V_STATIC_XGPHY_PLL_RESET(x) ((x) << S_STATIC_XGPHY_PLL_RESET) +#define F_STATIC_XGPHY_PLL_RESET V_STATIC_XGPHY_PLL_RESET(1U) + #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc #define A_DBG_STATIC_C_PLL_CONF4 0x60dc +#define A_DBG_STATIC_XGPHY_PLL_CONF2 0x60dc + +#define S_STATIC_XGPHY_PLL_SSMF 5 +#define M_STATIC_XGPHY_PLL_SSMF 0xfU +#define V_STATIC_XGPHY_PLL_SSMF(x) ((x) << S_STATIC_XGPHY_PLL_SSMF) +#define G_STATIC_XGPHY_PLL_SSMF(x) (((x) >> S_STATIC_XGPHY_PLL_SSMF) & M_STATIC_XGPHY_PLL_SSMF) + +#define S_STATIC_XGPHY_PLL_SSMD 2 +#define M_STATIC_XGPHY_PLL_SSMD 0x7U +#define V_STATIC_XGPHY_PLL_SSMD(x) ((x) << S_STATIC_XGPHY_PLL_SSMD) +#define G_STATIC_XGPHY_PLL_SSMD(x) (((x) >> S_STATIC_XGPHY_PLL_SSMD) & M_STATIC_XGPHY_PLL_SSMD) + +#define S_STATIC_XGPHY_PLL_SSDS 1 +#define V_STATIC_XGPHY_PLL_SSDS(x) ((x) << S_STATIC_XGPHY_PLL_SSDS) +#define F_STATIC_XGPHY_PLL_SSDS V_STATIC_XGPHY_PLL_SSDS(1U) + +#define S_STATIC_XGPHY_PLL_SSE 0 +#define V_STATIC_XGPHY_PLL_SSE(x) ((x) << S_STATIC_XGPHY_PLL_SSE) +#define F_STATIC_XGPHY_PLL_SSE V_STATIC_XGPHY_PLL_SSE(1U) + #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0 #define S_T5_STATIC_C_PLL_VCVTUNE 22 @@ -13140,6 +16583,40 @@ #define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT) #define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT) +#define A_DBG_STATIC_XGPBUS_PLL_CONF1 0x60e0 + +#define S_STATIC_XGPBUS_SWRST_ 25 +#define V_STATIC_XGPBUS_SWRST_(x) ((x) << S_STATIC_XGPBUS_SWRST_) +#define F_STATIC_XGPBUS_SWRST_ V_STATIC_XGPBUS_SWRST_(1U) + +#define S_STATIC_XGPBUS_PLL_RANGE 22 +#define M_STATIC_XGPBUS_PLL_RANGE 0x7U +#define V_STATIC_XGPBUS_PLL_RANGE(x) ((x) << S_STATIC_XGPBUS_PLL_RANGE) +#define G_STATIC_XGPBUS_PLL_RANGE(x) (((x) >> S_STATIC_XGPBUS_PLL_RANGE) & M_STATIC_XGPBUS_PLL_RANGE) + +#define S_STATIC_XGPBUS_PLL_DIVQ 17 +#define M_STATIC_XGPBUS_PLL_DIVQ 0x1fU +#define V_STATIC_XGPBUS_PLL_DIVQ(x) ((x) << S_STATIC_XGPBUS_PLL_DIVQ) +#define G_STATIC_XGPBUS_PLL_DIVQ(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVQ) & M_STATIC_XGPBUS_PLL_DIVQ) + +#define S_STATIC_XGPBUS_PLL_DIVFI 8 +#define M_STATIC_XGPBUS_PLL_DIVFI 0x1ffU +#define V_STATIC_XGPBUS_PLL_DIVFI(x) ((x) << S_STATIC_XGPBUS_PLL_DIVFI) +#define G_STATIC_XGPBUS_PLL_DIVFI(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVFI) & M_STATIC_XGPBUS_PLL_DIVFI) + +#define S_STATIC_XGPBUS_PLL_DIVR 2 +#define M_STATIC_XGPBUS_PLL_DIVR 0x3fU +#define V_STATIC_XGPBUS_PLL_DIVR(x) ((x) << S_STATIC_XGPBUS_PLL_DIVR) +#define G_STATIC_XGPBUS_PLL_DIVR(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVR) & M_STATIC_XGPBUS_PLL_DIVR) + +#define S_STATIC_XGPBUS_PLL_BYPASS 1 +#define V_STATIC_XGPBUS_PLL_BYPASS(x) ((x) << S_STATIC_XGPBUS_PLL_BYPASS) +#define F_STATIC_XGPBUS_PLL_BYPASS V_STATIC_XGPBUS_PLL_BYPASS(1U) + +#define S_STATIC_XGPBUS_PLL_RESET 0 +#define V_STATIC_XGPBUS_PLL_RESET(x) ((x) << S_STATIC_XGPBUS_PLL_RESET) +#define F_STATIC_XGPBUS_PLL_RESET V_STATIC_XGPBUS_PLL_RESET(1U) + #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4 #define S_T5_STATIC_U_PLL_MULTFRAC 8 @@ -13164,6 +16641,26 @@ #define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE) #define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE) +#define A_DBG_STATIC_XGPBUS_PLL_CONF2 0x60e4 + +#define S_STATIC_XGPBUS_PLL_SSMF 5 +#define M_STATIC_XGPBUS_PLL_SSMF 0xfU +#define V_STATIC_XGPBUS_PLL_SSMF(x) ((x) << S_STATIC_XGPBUS_PLL_SSMF) +#define G_STATIC_XGPBUS_PLL_SSMF(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMF) & M_STATIC_XGPBUS_PLL_SSMF) + +#define S_STATIC_XGPBUS_PLL_SSMD 2 +#define M_STATIC_XGPBUS_PLL_SSMD 0x7U +#define V_STATIC_XGPBUS_PLL_SSMD(x) ((x) << S_STATIC_XGPBUS_PLL_SSMD) +#define G_STATIC_XGPBUS_PLL_SSMD(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMD) & M_STATIC_XGPBUS_PLL_SSMD) + +#define S_STATIC_XGPBUS_PLL_SSDS 1 +#define V_STATIC_XGPBUS_PLL_SSDS(x) ((x) << S_STATIC_XGPBUS_PLL_SSDS) +#define F_STATIC_XGPBUS_PLL_SSDS V_STATIC_XGPBUS_PLL_SSDS(1U) + +#define S_STATIC_XGPBUS_PLL_SSE 0 +#define V_STATIC_XGPBUS_PLL_SSE(x) ((x) << S_STATIC_XGPBUS_PLL_SSE) +#define F_STATIC_XGPBUS_PLL_SSE V_STATIC_XGPBUS_PLL_SSE(1U) + #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8 #define S_T5_STATIC_U_PLL_DCO_BYPASS 23 @@ -13246,6 +16743,36 @@ #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE) #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE) +#define A_DBG_STATIC_M1_PLL_CONF1 0x60e8 + +#define S_STATIC_M1_PLL_RANGE 22 +#define M_STATIC_M1_PLL_RANGE 0x7U +#define V_STATIC_M1_PLL_RANGE(x) ((x) << S_STATIC_M1_PLL_RANGE) +#define G_STATIC_M1_PLL_RANGE(x) (((x) >> S_STATIC_M1_PLL_RANGE) & M_STATIC_M1_PLL_RANGE) + +#define S_STATIC_M1_PLL_DIVQ 17 +#define M_STATIC_M1_PLL_DIVQ 0x1fU +#define V_STATIC_M1_PLL_DIVQ(x) ((x) << S_STATIC_M1_PLL_DIVQ) +#define G_STATIC_M1_PLL_DIVQ(x) (((x) >> S_STATIC_M1_PLL_DIVQ) & M_STATIC_M1_PLL_DIVQ) + +#define S_STATIC_M1_PLL_DIVFI 8 +#define M_STATIC_M1_PLL_DIVFI 0x1ffU +#define V_STATIC_M1_PLL_DIVFI(x) ((x) << S_STATIC_M1_PLL_DIVFI) +#define G_STATIC_M1_PLL_DIVFI(x) (((x) >> S_STATIC_M1_PLL_DIVFI) & M_STATIC_M1_PLL_DIVFI) + +#define S_STATIC_M1_PLL_DIVR 2 +#define M_STATIC_M1_PLL_DIVR 0x3fU +#define V_STATIC_M1_PLL_DIVR(x) ((x) << S_STATIC_M1_PLL_DIVR) +#define G_STATIC_M1_PLL_DIVR(x) (((x) >> S_STATIC_M1_PLL_DIVR) & M_STATIC_M1_PLL_DIVR) + +#define S_STATIC_M1_PLL_BYPASS 1 +#define V_STATIC_M1_PLL_BYPASS(x) ((x) << S_STATIC_M1_PLL_BYPASS) +#define F_STATIC_M1_PLL_BYPASS V_STATIC_M1_PLL_BYPASS(1U) + +#define S_STATIC_M1_PLL_RESET 0 +#define V_STATIC_M1_PLL_RESET(x) ((x) << S_STATIC_M1_PLL_RESET) +#define F_STATIC_M1_PLL_RESET V_STATIC_M1_PLL_RESET(1U) + #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec #define S_T5_STATIC_U_PLL_MULTPRE 30 @@ -13309,6 +16836,26 @@ #define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA) #define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA) +#define A_DBG_STATIC_M1_PLL_CONF2 0x60ec + +#define S_STATIC_M1_PLL_SSMF 5 +#define M_STATIC_M1_PLL_SSMF 0xfU +#define V_STATIC_M1_PLL_SSMF(x) ((x) << S_STATIC_M1_PLL_SSMF) +#define G_STATIC_M1_PLL_SSMF(x) (((x) >> S_STATIC_M1_PLL_SSMF) & M_STATIC_M1_PLL_SSMF) + +#define S_STATIC_M1_PLL_SSMD 2 +#define M_STATIC_M1_PLL_SSMD 0x7U +#define V_STATIC_M1_PLL_SSMD(x) ((x) << S_STATIC_M1_PLL_SSMD) +#define G_STATIC_M1_PLL_SSMD(x) (((x) >> S_STATIC_M1_PLL_SSMD) & M_STATIC_M1_PLL_SSMD) + +#define S_STATIC_M1_PLL_SSDS 1 +#define V_STATIC_M1_PLL_SSDS(x) ((x) << S_STATIC_M1_PLL_SSDS) +#define F_STATIC_M1_PLL_SSDS V_STATIC_M1_PLL_SSDS(1U) + +#define S_STATIC_M1_PLL_SSE 0 +#define V_STATIC_M1_PLL_SSE(x) ((x) << S_STATIC_M1_PLL_SSE) +#define F_STATIC_M1_PLL_SSE V_STATIC_M1_PLL_SSE(1U) + #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4 @@ -13557,6 +17104,104 @@ #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL) #define F_GPIO19_OUT_VAL V_GPIO19_OUT_VAL(1U) +#define A_DBG_GPIO_OEN 0x6100 + +#define S_GPIO23_OEN 23 +#define V_GPIO23_OEN(x) ((x) << S_GPIO23_OEN) +#define F_GPIO23_OEN V_GPIO23_OEN(1U) + +#define S_GPIO22_OEN 22 +#define V_GPIO22_OEN(x) ((x) << S_GPIO22_OEN) +#define F_GPIO22_OEN V_GPIO22_OEN(1U) + +#define S_GPIO21_OEN 21 +#define V_GPIO21_OEN(x) ((x) << S_GPIO21_OEN) +#define F_GPIO21_OEN V_GPIO21_OEN(1U) + +#define S_GPIO20_OEN 20 +#define V_GPIO20_OEN(x) ((x) << S_GPIO20_OEN) +#define F_GPIO20_OEN V_GPIO20_OEN(1U) + +#define S_T7_GPIO19_OEN 19 +#define V_T7_GPIO19_OEN(x) ((x) << S_T7_GPIO19_OEN) +#define F_T7_GPIO19_OEN V_T7_GPIO19_OEN(1U) + +#define S_T7_GPIO18_OEN 18 +#define V_T7_GPIO18_OEN(x) ((x) << S_T7_GPIO18_OEN) +#define F_T7_GPIO18_OEN V_T7_GPIO18_OEN(1U) + +#define S_T7_GPIO17_OEN 17 +#define V_T7_GPIO17_OEN(x) ((x) << S_T7_GPIO17_OEN) +#define F_T7_GPIO17_OEN V_T7_GPIO17_OEN(1U) + +#define S_T7_GPIO16_OEN 16 +#define V_T7_GPIO16_OEN(x) ((x) << S_T7_GPIO16_OEN) +#define F_T7_GPIO16_OEN V_T7_GPIO16_OEN(1U) + +#define S_T7_GPIO15_OEN 15 +#define V_T7_GPIO15_OEN(x) ((x) << S_T7_GPIO15_OEN) +#define F_T7_GPIO15_OEN V_T7_GPIO15_OEN(1U) + +#define S_T7_GPIO14_OEN 14 +#define V_T7_GPIO14_OEN(x) ((x) << S_T7_GPIO14_OEN) +#define F_T7_GPIO14_OEN V_T7_GPIO14_OEN(1U) + +#define S_T7_GPIO13_OEN 13 +#define V_T7_GPIO13_OEN(x) ((x) << S_T7_GPIO13_OEN) +#define F_T7_GPIO13_OEN V_T7_GPIO13_OEN(1U) + +#define S_T7_GPIO12_OEN 12 +#define V_T7_GPIO12_OEN(x) ((x) << S_T7_GPIO12_OEN) +#define F_T7_GPIO12_OEN V_T7_GPIO12_OEN(1U) + +#define S_T7_GPIO11_OEN 11 +#define V_T7_GPIO11_OEN(x) ((x) << S_T7_GPIO11_OEN) +#define F_T7_GPIO11_OEN V_T7_GPIO11_OEN(1U) + +#define S_T7_GPIO10_OEN 10 +#define V_T7_GPIO10_OEN(x) ((x) << S_T7_GPIO10_OEN) +#define F_T7_GPIO10_OEN V_T7_GPIO10_OEN(1U) + +#define S_T7_GPIO9_OEN 9 +#define V_T7_GPIO9_OEN(x) ((x) << S_T7_GPIO9_OEN) +#define F_T7_GPIO9_OEN V_T7_GPIO9_OEN(1U) + +#define S_T7_GPIO8_OEN 8 +#define V_T7_GPIO8_OEN(x) ((x) << S_T7_GPIO8_OEN) +#define F_T7_GPIO8_OEN V_T7_GPIO8_OEN(1U) + +#define S_T7_GPIO7_OEN 7 +#define V_T7_GPIO7_OEN(x) ((x) << S_T7_GPIO7_OEN) +#define F_T7_GPIO7_OEN V_T7_GPIO7_OEN(1U) + +#define S_T7_GPIO6_OEN 6 +#define V_T7_GPIO6_OEN(x) ((x) << S_T7_GPIO6_OEN) +#define F_T7_GPIO6_OEN V_T7_GPIO6_OEN(1U) + +#define S_T7_GPIO5_OEN 5 +#define V_T7_GPIO5_OEN(x) ((x) << S_T7_GPIO5_OEN) +#define F_T7_GPIO5_OEN V_T7_GPIO5_OEN(1U) + +#define S_T7_GPIO4_OEN 4 +#define V_T7_GPIO4_OEN(x) ((x) << S_T7_GPIO4_OEN) +#define F_T7_GPIO4_OEN V_T7_GPIO4_OEN(1U) + +#define S_T7_GPIO3_OEN 3 +#define V_T7_GPIO3_OEN(x) ((x) << S_T7_GPIO3_OEN) +#define F_T7_GPIO3_OEN V_T7_GPIO3_OEN(1U) + +#define S_T7_GPIO2_OEN 2 +#define V_T7_GPIO2_OEN(x) ((x) << S_T7_GPIO2_OEN) +#define F_T7_GPIO2_OEN V_T7_GPIO2_OEN(1U) + +#define S_T7_GPIO1_OEN 1 +#define V_T7_GPIO1_OEN(x) ((x) << S_T7_GPIO1_OEN) +#define F_T7_GPIO1_OEN V_T7_GPIO1_OEN(1U) + +#define S_T7_GPIO0_OEN 0 +#define V_T7_GPIO0_OEN(x) ((x) << S_T7_GPIO0_OEN) +#define F_T7_GPIO0_OEN V_T7_GPIO0_OEN(1U) + #define A_DBG_PVT_REG_UPDATE_CTL 0x6104 #define S_FAST_UPDATE 8 @@ -13605,6 +17250,104 @@ #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN) #define F_GPIO16_IN V_GPIO16_IN(1U) +#define A_DBG_GPIO_CHG_DET 0x6104 + +#define S_GPIO23_CHG_DET 23 +#define V_GPIO23_CHG_DET(x) ((x) << S_GPIO23_CHG_DET) +#define F_GPIO23_CHG_DET V_GPIO23_CHG_DET(1U) + +#define S_GPIO22_CHG_DET 22 +#define V_GPIO22_CHG_DET(x) ((x) << S_GPIO22_CHG_DET) +#define F_GPIO22_CHG_DET V_GPIO22_CHG_DET(1U) + +#define S_GPIO21_CHG_DET 21 +#define V_GPIO21_CHG_DET(x) ((x) << S_GPIO21_CHG_DET) +#define F_GPIO21_CHG_DET V_GPIO21_CHG_DET(1U) + +#define S_GPIO20_CHG_DET 20 +#define V_GPIO20_CHG_DET(x) ((x) << S_GPIO20_CHG_DET) +#define F_GPIO20_CHG_DET V_GPIO20_CHG_DET(1U) + +#define S_T7_GPIO19_CHG_DET 19 +#define V_T7_GPIO19_CHG_DET(x) ((x) << S_T7_GPIO19_CHG_DET) +#define F_T7_GPIO19_CHG_DET V_T7_GPIO19_CHG_DET(1U) + +#define S_T7_GPIO18_CHG_DET 18 +#define V_T7_GPIO18_CHG_DET(x) ((x) << S_T7_GPIO18_CHG_DET) +#define F_T7_GPIO18_CHG_DET V_T7_GPIO18_CHG_DET(1U) + +#define S_T7_GPIO17_CHG_DET 17 +#define V_T7_GPIO17_CHG_DET(x) ((x) << S_T7_GPIO17_CHG_DET) +#define F_T7_GPIO17_CHG_DET V_T7_GPIO17_CHG_DET(1U) + +#define S_T7_GPIO16_CHG_DET 16 +#define V_T7_GPIO16_CHG_DET(x) ((x) << S_T7_GPIO16_CHG_DET) +#define F_T7_GPIO16_CHG_DET V_T7_GPIO16_CHG_DET(1U) + +#define S_T7_GPIO15_CHG_DET 15 +#define V_T7_GPIO15_CHG_DET(x) ((x) << S_T7_GPIO15_CHG_DET) +#define F_T7_GPIO15_CHG_DET V_T7_GPIO15_CHG_DET(1U) + +#define S_T7_GPIO14_CHG_DET 14 +#define V_T7_GPIO14_CHG_DET(x) ((x) << S_T7_GPIO14_CHG_DET) +#define F_T7_GPIO14_CHG_DET V_T7_GPIO14_CHG_DET(1U) + +#define S_T7_GPIO13_CHG_DET 13 +#define V_T7_GPIO13_CHG_DET(x) ((x) << S_T7_GPIO13_CHG_DET) +#define F_T7_GPIO13_CHG_DET V_T7_GPIO13_CHG_DET(1U) + +#define S_T7_GPIO12_CHG_DET 12 +#define V_T7_GPIO12_CHG_DET(x) ((x) << S_T7_GPIO12_CHG_DET) +#define F_T7_GPIO12_CHG_DET V_T7_GPIO12_CHG_DET(1U) + +#define S_T7_GPIO11_CHG_DET 11 +#define V_T7_GPIO11_CHG_DET(x) ((x) << S_T7_GPIO11_CHG_DET) +#define F_T7_GPIO11_CHG_DET V_T7_GPIO11_CHG_DET(1U) + +#define S_T7_GPIO10_CHG_DET 10 +#define V_T7_GPIO10_CHG_DET(x) ((x) << S_T7_GPIO10_CHG_DET) +#define F_T7_GPIO10_CHG_DET V_T7_GPIO10_CHG_DET(1U) + +#define S_T7_GPIO9_CHG_DET 9 +#define V_T7_GPIO9_CHG_DET(x) ((x) << S_T7_GPIO9_CHG_DET) +#define F_T7_GPIO9_CHG_DET V_T7_GPIO9_CHG_DET(1U) + +#define S_T7_GPIO8_CHG_DET 8 +#define V_T7_GPIO8_CHG_DET(x) ((x) << S_T7_GPIO8_CHG_DET) +#define F_T7_GPIO8_CHG_DET V_T7_GPIO8_CHG_DET(1U) + +#define S_T7_GPIO7_CHG_DET 7 +#define V_T7_GPIO7_CHG_DET(x) ((x) << S_T7_GPIO7_CHG_DET) +#define F_T7_GPIO7_CHG_DET V_T7_GPIO7_CHG_DET(1U) + +#define S_T7_GPIO6_CHG_DET 6 +#define V_T7_GPIO6_CHG_DET(x) ((x) << S_T7_GPIO6_CHG_DET) +#define F_T7_GPIO6_CHG_DET V_T7_GPIO6_CHG_DET(1U) + +#define S_T7_GPIO5_CHG_DET 5 +#define V_T7_GPIO5_CHG_DET(x) ((x) << S_T7_GPIO5_CHG_DET) +#define F_T7_GPIO5_CHG_DET V_T7_GPIO5_CHG_DET(1U) + +#define S_T7_GPIO4_CHG_DET 4 +#define V_T7_GPIO4_CHG_DET(x) ((x) << S_T7_GPIO4_CHG_DET) +#define F_T7_GPIO4_CHG_DET V_T7_GPIO4_CHG_DET(1U) + +#define S_T7_GPIO3_CHG_DET 3 +#define V_T7_GPIO3_CHG_DET(x) ((x) << S_T7_GPIO3_CHG_DET) +#define F_T7_GPIO3_CHG_DET V_T7_GPIO3_CHG_DET(1U) + +#define S_T7_GPIO2_CHG_DET 2 +#define V_T7_GPIO2_CHG_DET(x) ((x) << S_T7_GPIO2_CHG_DET) +#define F_T7_GPIO2_CHG_DET V_T7_GPIO2_CHG_DET(1U) + +#define S_T7_GPIO1_CHG_DET 1 +#define V_T7_GPIO1_CHG_DET(x) ((x) << S_T7_GPIO1_CHG_DET) +#define F_T7_GPIO1_CHG_DET V_T7_GPIO1_CHG_DET(1U) + +#define S_T7_GPIO0_CHG_DET 0 +#define V_T7_GPIO0_CHG_DET(x) ((x) << S_T7_GPIO0_CHG_DET) +#define F_T7_GPIO0_CHG_DET V_T7_GPIO0_CHG_DET(1U) + #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108 #define S_LAST_MEASUREMENT_SELECT 8 @@ -13964,6 +17707,22 @@ #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN) #define F_GPIO0_PE_EN V_GPIO0_PE_EN(1U) +#define S_GPIO23_PE_EN 23 +#define V_GPIO23_PE_EN(x) ((x) << S_GPIO23_PE_EN) +#define F_GPIO23_PE_EN V_GPIO23_PE_EN(1U) + +#define S_GPIO22_PE_EN 22 +#define V_GPIO22_PE_EN(x) ((x) << S_GPIO22_PE_EN) +#define F_GPIO22_PE_EN V_GPIO22_PE_EN(1U) + +#define S_GPIO21_PE_EN 21 +#define V_GPIO21_PE_EN(x) ((x) << S_GPIO21_PE_EN) +#define F_GPIO21_PE_EN V_GPIO21_PE_EN(1U) + +#define S_GPIO20_PE_EN 20 +#define V_GPIO20_PE_EN(x) ((x) << S_GPIO20_PE_EN) +#define F_GPIO20_PE_EN V_GPIO20_PE_EN(1U) + #define A_DBG_PVT_REG_THRESHOLD 0x611c #define S_PVT_CALIBRATION_DONE 8 @@ -14084,6 +17843,22 @@ #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN) #define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U) +#define S_GPIO23_PS_EN 23 +#define V_GPIO23_PS_EN(x) ((x) << S_GPIO23_PS_EN) +#define F_GPIO23_PS_EN V_GPIO23_PS_EN(1U) + +#define S_GPIO22_PS_EN 22 +#define V_GPIO22_PS_EN(x) ((x) << S_GPIO22_PS_EN) +#define F_GPIO22_PS_EN V_GPIO22_PS_EN(1U) + +#define S_GPIO21_PS_EN 21 +#define V_GPIO21_PS_EN(x) ((x) << S_GPIO21_PS_EN) +#define F_GPIO21_PS_EN V_GPIO21_PS_EN(1U) + +#define S_GPIO20_PS_EN 20 +#define V_GPIO20_PS_EN(x) ((x) << S_GPIO20_PS_EN) +#define F_GPIO20_PS_EN V_GPIO20_PS_EN(1U) + #define A_DBG_PVT_REG_IN_TERMP 0x6120 #define S_REG_IN_TERMP_B 4 @@ -14254,6 +18029,17 @@ #define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE) #define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE) +#define A_DBG_STATIC_PLL_LOCK_WAIT_CONF 0x6150 + +#define S_STATIC_WAIT_LOCK 24 +#define V_STATIC_WAIT_LOCK(x) ((x) << S_STATIC_WAIT_LOCK) +#define F_STATIC_WAIT_LOCK V_STATIC_WAIT_LOCK(1U) + +#define S_STATIC_LOCK_WAIT_TIME 0 +#define M_STATIC_LOCK_WAIT_TIME 0xffffffU +#define V_STATIC_LOCK_WAIT_TIME(x) ((x) << S_STATIC_LOCK_WAIT_TIME) +#define G_STATIC_LOCK_WAIT_TIME(x) (((x) >> S_STATIC_LOCK_WAIT_TIME) & M_STATIC_LOCK_WAIT_TIME) + #define A_DBG_STATIC_C_PLL_CONF6 0x6154 #define S_STATIC_C_PLL_VREGTUNE 0 @@ -14303,13 +18089,274 @@ #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180 +#define A_DBG_GPIO_INT_ENABLE 0x6180 + +#define S_GPIO23 23 +#define V_GPIO23(x) ((x) << S_GPIO23) +#define F_GPIO23 V_GPIO23(1U) + +#define S_GPIO22 22 +#define V_GPIO22(x) ((x) << S_GPIO22) +#define F_GPIO22 V_GPIO22(1U) + +#define S_GPIO21 21 +#define V_GPIO21(x) ((x) << S_GPIO21) +#define F_GPIO21 V_GPIO21(1U) + +#define S_GPIO20 20 +#define V_GPIO20(x) ((x) << S_GPIO20) +#define F_GPIO20 V_GPIO20(1U) + +#define S_T7_GPIO19 19 +#define V_T7_GPIO19(x) ((x) << S_T7_GPIO19) +#define F_T7_GPIO19 V_T7_GPIO19(1U) + +#define S_T7_GPIO18 18 +#define V_T7_GPIO18(x) ((x) << S_T7_GPIO18) +#define F_T7_GPIO18 V_T7_GPIO18(1U) + +#define S_T7_GPIO17 17 +#define V_T7_GPIO17(x) ((x) << S_T7_GPIO17) +#define F_T7_GPIO17 V_T7_GPIO17(1U) + +#define S_T7_GPIO16 16 +#define V_T7_GPIO16(x) ((x) << S_T7_GPIO16) +#define F_T7_GPIO16 V_T7_GPIO16(1U) + #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184 +#define A_DBG_GPIO_INT_CAUSE 0x6184 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188 +#define A_T7_DBG_GPIO_ACT_LOW 0x6188 + +#define S_GPIO23_ACT_LOW 23 +#define V_GPIO23_ACT_LOW(x) ((x) << S_GPIO23_ACT_LOW) +#define F_GPIO23_ACT_LOW V_GPIO23_ACT_LOW(1U) + +#define S_GPIO22_ACT_LOW 22 +#define V_GPIO22_ACT_LOW(x) ((x) << S_GPIO22_ACT_LOW) +#define F_GPIO22_ACT_LOW V_GPIO22_ACT_LOW(1U) + +#define S_GPIO21_ACT_LOW 21 +#define V_GPIO21_ACT_LOW(x) ((x) << S_GPIO21_ACT_LOW) +#define F_GPIO21_ACT_LOW V_GPIO21_ACT_LOW(1U) + +#define S_GPIO20_ACT_LOW 20 +#define V_GPIO20_ACT_LOW(x) ((x) << S_GPIO20_ACT_LOW) +#define F_GPIO20_ACT_LOW V_GPIO20_ACT_LOW(1U) + +#define S_T7_GPIO19_ACT_LOW 19 +#define V_T7_GPIO19_ACT_LOW(x) ((x) << S_T7_GPIO19_ACT_LOW) +#define F_T7_GPIO19_ACT_LOW V_T7_GPIO19_ACT_LOW(1U) + +#define S_T7_GPIO18_ACT_LOW 18 +#define V_T7_GPIO18_ACT_LOW(x) ((x) << S_T7_GPIO18_ACT_LOW) +#define F_T7_GPIO18_ACT_LOW V_T7_GPIO18_ACT_LOW(1U) + +#define S_T7_GPIO17_ACT_LOW 17 +#define V_T7_GPIO17_ACT_LOW(x) ((x) << S_T7_GPIO17_ACT_LOW) +#define F_T7_GPIO17_ACT_LOW V_T7_GPIO17_ACT_LOW(1U) + +#define S_T7_GPIO16_ACT_LOW 16 +#define V_T7_GPIO16_ACT_LOW(x) ((x) << S_T7_GPIO16_ACT_LOW) +#define F_T7_GPIO16_ACT_LOW V_T7_GPIO16_ACT_LOW(1U) + #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c +#define A_DBG_DDR_CAL 0x618c + +#define S_CAL_ENDC 9 +#define V_CAL_ENDC(x) ((x) << S_CAL_ENDC) +#define F_CAL_ENDC V_CAL_ENDC(1U) + +#define S_CAL_MODE 8 +#define V_CAL_MODE(x) ((x) << S_CAL_MODE) +#define F_CAL_MODE V_CAL_MODE(1U) + +#define S_CAL_REFSEL 7 +#define V_CAL_REFSEL(x) ((x) << S_CAL_REFSEL) +#define F_CAL_REFSEL V_CAL_REFSEL(1U) + +#define S_PD 6 +#define V_PD(x) ((x) << S_PD) +#define F_PD V_PD(1U) + +#define S_CAL_RST 5 +#define V_CAL_RST(x) ((x) << S_CAL_RST) +#define F_CAL_RST V_CAL_RST(1U) + +#define S_CAL_READ 4 +#define V_CAL_READ(x) ((x) << S_CAL_READ) +#define F_CAL_READ V_CAL_READ(1U) + +#define S_CAL_SC 3 +#define V_CAL_SC(x) ((x) << S_CAL_SC) +#define F_CAL_SC V_CAL_SC(1U) + +#define S_CAL_LC 2 +#define V_CAL_LC(x) ((x) << S_CAL_LC) +#define F_CAL_LC V_CAL_LC(1U) + +#define S_CAL_CCAL 1 +#define V_CAL_CCAL(x) ((x) << S_CAL_CCAL) +#define F_CAL_CCAL V_CAL_CCAL(1U) + +#define S_CAL_RES 0 +#define V_CAL_RES(x) ((x) << S_CAL_RES) +#define F_CAL_RES V_CAL_RES(1U) + #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190 +#define A_DBG_EFUSE_CTL_0 0x6190 + +#define S_EFUSE_CSB 31 +#define V_EFUSE_CSB(x) ((x) << S_EFUSE_CSB) +#define F_EFUSE_CSB V_EFUSE_CSB(1U) + +#define S_EFUSE_STROBE 30 +#define V_EFUSE_STROBE(x) ((x) << S_EFUSE_STROBE) +#define F_EFUSE_STROBE V_EFUSE_STROBE(1U) + +#define S_EFUSE_LOAD 29 +#define V_EFUSE_LOAD(x) ((x) << S_EFUSE_LOAD) +#define F_EFUSE_LOAD V_EFUSE_LOAD(1U) + +#define S_EFUSE_PGENB 28 +#define V_EFUSE_PGENB(x) ((x) << S_EFUSE_PGENB) +#define F_EFUSE_PGENB V_EFUSE_PGENB(1U) + +#define S_EFUSE_PS 27 +#define V_EFUSE_PS(x) ((x) << S_EFUSE_PS) +#define F_EFUSE_PS V_EFUSE_PS(1U) + +#define S_EFUSE_MR 26 +#define V_EFUSE_MR(x) ((x) << S_EFUSE_MR) +#define F_EFUSE_MR V_EFUSE_MR(1U) + +#define S_EFUSE_PD 25 +#define V_EFUSE_PD(x) ((x) << S_EFUSE_PD) +#define F_EFUSE_PD V_EFUSE_PD(1U) + +#define S_EFUSE_RWL 24 +#define V_EFUSE_RWL(x) ((x) << S_EFUSE_RWL) +#define F_EFUSE_RWL V_EFUSE_RWL(1U) + +#define S_EFUSE_RSB 23 +#define V_EFUSE_RSB(x) ((x) << S_EFUSE_RSB) +#define F_EFUSE_RSB V_EFUSE_RSB(1U) + +#define S_EFUSE_TRCS 22 +#define V_EFUSE_TRCS(x) ((x) << S_EFUSE_TRCS) +#define F_EFUSE_TRCS V_EFUSE_TRCS(1U) + +#define S_EFUSE_AT 20 +#define M_EFUSE_AT 0x3U +#define V_EFUSE_AT(x) ((x) << S_EFUSE_AT) +#define G_EFUSE_AT(x) (((x) >> S_EFUSE_AT) & M_EFUSE_AT) + +#define S_EFUSE_RD_STATE 16 +#define M_EFUSE_RD_STATE 0xfU +#define V_EFUSE_RD_STATE(x) ((x) << S_EFUSE_RD_STATE) +#define G_EFUSE_RD_STATE(x) (((x) >> S_EFUSE_RD_STATE) & M_EFUSE_RD_STATE) + +#define S_EFUSE_BUSY 15 +#define V_EFUSE_BUSY(x) ((x) << S_EFUSE_BUSY) +#define F_EFUSE_BUSY V_EFUSE_BUSY(1U) + +#define S_EFUSE_WR_RD 13 +#define M_EFUSE_WR_RD 0x3U +#define V_EFUSE_WR_RD(x) ((x) << S_EFUSE_WR_RD) +#define G_EFUSE_WR_RD(x) (((x) >> S_EFUSE_WR_RD) & M_EFUSE_WR_RD) + +#define S_EFUSE_A 0 +#define M_EFUSE_A 0x7ffU +#define V_EFUSE_A(x) ((x) << S_EFUSE_A) +#define G_EFUSE_A(x) (((x) >> S_EFUSE_A) & M_EFUSE_A) + #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194 +#define A_DBG_EFUSE_CTL_1 0x6194 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198 +#define A_DBG_EFUSE_RD_CTL 0x6198 + +#define S_EFUSE_RD_ID 6 +#define M_EFUSE_RD_ID 0x3U +#define V_EFUSE_RD_ID(x) ((x) << S_EFUSE_RD_ID) +#define G_EFUSE_RD_ID(x) (((x) >> S_EFUSE_RD_ID) & M_EFUSE_RD_ID) + +#define S_EFUSE_RD_ADDR 0 +#define M_EFUSE_RD_ADDR 0x3fU +#define V_EFUSE_RD_ADDR(x) ((x) << S_EFUSE_RD_ADDR) +#define G_EFUSE_RD_ADDR(x) (((x) >> S_EFUSE_RD_ADDR) & M_EFUSE_RD_ADDR) + #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c +#define A_DBG_EFUSE_RD_DATA 0x619c +#define A_DBG_EFUSE_TIME_0 0x61a0 + +#define S_EFUSE_TIME_1 16 +#define M_EFUSE_TIME_1 0xffffU +#define V_EFUSE_TIME_1(x) ((x) << S_EFUSE_TIME_1) +#define G_EFUSE_TIME_1(x) (((x) >> S_EFUSE_TIME_1) & M_EFUSE_TIME_1) + +#define S_EFUSE_TIME_0 0 +#define M_EFUSE_TIME_0 0xffffU +#define V_EFUSE_TIME_0(x) ((x) << S_EFUSE_TIME_0) +#define G_EFUSE_TIME_0(x) (((x) >> S_EFUSE_TIME_0) & M_EFUSE_TIME_0) + +#define A_DBG_EFUSE_TIME_1 0x61a4 + +#define S_EFUSE_TIME_3 16 +#define M_EFUSE_TIME_3 0xffffU +#define V_EFUSE_TIME_3(x) ((x) << S_EFUSE_TIME_3) +#define G_EFUSE_TIME_3(x) (((x) >> S_EFUSE_TIME_3) & M_EFUSE_TIME_3) + +#define S_EFUSE_TIME_2 0 +#define M_EFUSE_TIME_2 0xffffU +#define V_EFUSE_TIME_2(x) ((x) << S_EFUSE_TIME_2) +#define G_EFUSE_TIME_2(x) (((x) >> S_EFUSE_TIME_2) & M_EFUSE_TIME_2) + +#define A_DBG_EFUSE_TIME_2 0x61a8 + +#define S_EFUSE_TIME_5 16 +#define M_EFUSE_TIME_5 0xffffU +#define V_EFUSE_TIME_5(x) ((x) << S_EFUSE_TIME_5) +#define G_EFUSE_TIME_5(x) (((x) >> S_EFUSE_TIME_5) & M_EFUSE_TIME_5) + +#define S_EFUSE_TIME_4 0 +#define M_EFUSE_TIME_4 0xffffU +#define V_EFUSE_TIME_4(x) ((x) << S_EFUSE_TIME_4) +#define G_EFUSE_TIME_4(x) (((x) >> S_EFUSE_TIME_4) & M_EFUSE_TIME_4) + +#define A_DBG_EFUSE_TIME_3 0x61ac + +#define S_EFUSE_TIME_7 16 +#define M_EFUSE_TIME_7 0xffffU +#define V_EFUSE_TIME_7(x) ((x) << S_EFUSE_TIME_7) +#define G_EFUSE_TIME_7(x) (((x) >> S_EFUSE_TIME_7) & M_EFUSE_TIME_7) + +#define S_EFUSE_TIME_6 0 +#define M_EFUSE_TIME_6 0xffffU +#define V_EFUSE_TIME_6(x) ((x) << S_EFUSE_TIME_6) +#define G_EFUSE_TIME_6(x) (((x) >> S_EFUSE_TIME_6) & M_EFUSE_TIME_6) + +#define A_DBG_VREF_CTL 0x61b0 + +#define S_VREF_SEL_1 15 +#define V_VREF_SEL_1(x) ((x) << S_VREF_SEL_1) +#define F_VREF_SEL_1 V_VREF_SEL_1(1U) + +#define S_VREF_R_1 8 +#define M_VREF_R_1 0x7fU +#define V_VREF_R_1(x) ((x) << S_VREF_R_1) +#define G_VREF_R_1(x) (((x) >> S_VREF_R_1) & M_VREF_R_1) + +#define S_VREF_SEL_0 7 +#define V_VREF_SEL_0(x) ((x) << S_VREF_SEL_0) +#define F_VREF_SEL_0 V_VREF_SEL_0(1U) + +#define S_VREF_R_0 0 +#define M_VREF_R_0 0x7fU +#define V_VREF_R_0(x) ((x) << S_VREF_R_0) +#define G_VREF_R_0(x) (((x) >> S_VREF_R_0) & M_VREF_R_0) + +#define A_DBG_FPGA_EFUSE_CTL 0x61b4 +#define A_DBG_FPGA_EFUSE_DATA 0x61b8 /* registers for module MC */ #define MC_BASE_ADDR 0x6200 @@ -16048,31 +20095,91 @@ #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN) #define F_THRESHOLD0_EN V_THRESHOLD0_EN(1U) +#define A_MA_CLIENT0_PR_THRESHOLD 0x7700 + +#define S_T7_THRESHOLD1_EN 31 +#define V_T7_THRESHOLD1_EN(x) ((x) << S_T7_THRESHOLD1_EN) +#define F_T7_THRESHOLD1_EN V_T7_THRESHOLD1_EN(1U) + +#define S_T7_THRESHOLD1 16 +#define M_T7_THRESHOLD1 0x7fffU +#define V_T7_THRESHOLD1(x) ((x) << S_T7_THRESHOLD1) +#define G_T7_THRESHOLD1(x) (((x) >> S_T7_THRESHOLD1) & M_T7_THRESHOLD1) + +#define S_T7_THRESHOLD0_EN 15 +#define V_T7_THRESHOLD0_EN(x) ((x) << S_T7_THRESHOLD0_EN) +#define F_T7_THRESHOLD0_EN V_T7_THRESHOLD0_EN(1U) + +#define S_T7_THRESHOLD0 0 +#define M_T7_THRESHOLD0 0x7fffU +#define V_T7_THRESHOLD0(x) ((x) << S_T7_THRESHOLD0) +#define G_T7_THRESHOLD0(x) (((x) >> S_T7_THRESHOLD0) & M_T7_THRESHOLD0) + #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704 +#define A_MA_CLIENT0_CR_THRESHOLD 0x7704 + +#define S_CREDITSHAPER_EN 31 +#define V_CREDITSHAPER_EN(x) ((x) << S_CREDITSHAPER_EN) +#define F_CREDITSHAPER_EN V_CREDITSHAPER_EN(1U) + +#define S_CREDIT_MAX 16 +#define M_CREDIT_MAX 0xfffU +#define V_CREDIT_MAX(x) ((x) << S_CREDIT_MAX) +#define G_CREDIT_MAX(x) (((x) >> S_CREDIT_MAX) & M_CREDIT_MAX) + +#define S_CREDIT_VAL 0 +#define M_CREDIT_VAL 0xfffU +#define V_CREDIT_VAL(x) ((x) << S_CREDIT_VAL) +#define G_CREDIT_VAL(x) (((x) >> S_CREDIT_VAL) & M_CREDIT_VAL) + #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708 +#define A_MA_CLIENT1_PR_THRESHOLD 0x7708 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c +#define A_MA_CLIENT1_CR_THRESHOLD 0x770c #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710 +#define A_MA_CLIENT2_PR_THRESHOLD 0x7710 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714 +#define A_MA_CLIENT2_CR_THRESHOLD 0x7714 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718 +#define A_MA_CLIENT3_PR_THRESHOLD 0x7718 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c +#define A_MA_CLIENT3_CR_THRESHOLD 0x771c #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720 +#define A_MA_CLIENT4_PR_THRESHOLD 0x7720 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724 +#define A_MA_CLIENT4_CR_THRESHOLD 0x7724 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728 +#define A_MA_CLIENT5_PR_THRESHOLD 0x7728 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c +#define A_MA_CLIENT5_CR_THRESHOLD 0x772c #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730 +#define A_MA_CLIENT6_PR_THRESHOLD 0x7730 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734 +#define A_MA_CLIENT6_CR_THRESHOLD 0x7734 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738 +#define A_MA_CLIENT7_PR_THRESHOLD 0x7738 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c +#define A_MA_CLIENT7_CR_THRESHOLD 0x773c #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740 +#define A_MA_CLIENT8_PR_THRESHOLD 0x7740 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744 +#define A_MA_CLIENT8_CR_THRESHOLD 0x7744 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748 +#define A_MA_CLIENT9_PR_THRESHOLD 0x7748 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c +#define A_MA_CLIENT9_CR_THRESHOLD 0x774c #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750 +#define A_MA_CLIENT10_PR_THRESHOLD 0x7750 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754 +#define A_MA_CLIENT10_CR_THRESHOLD 0x7754 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758 +#define A_MA_CLIENT11_PR_THRESHOLD 0x7758 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c +#define A_MA_CLIENT11_CR_THRESHOLD 0x775c #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760 +#define A_MA_CLIENT12_PR_THRESHOLD 0x7760 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764 +#define A_MA_CLIENT12_CR_THRESHOLD 0x7764 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768 #define S_DBG_READ_DATA_CNT 24 @@ -16103,10 +20210,359 @@ #define A_MA_TP_TH1_DEBUG_CNT 0x7780 #define A_MA_LE_DEBUG_CNT 0x7784 #define A_MA_CIM_DEBUG_CNT 0x7788 +#define A_MA_CIM_TH0_DEBUG_CNT 0x7788 #define A_MA_PCIE_DEBUG_CNT 0x778c #define A_MA_PMTX_DEBUG_CNT 0x7790 #define A_MA_PMRX_DEBUG_CNT 0x7794 #define A_MA_HMA_DEBUG_CNT 0x7798 +#define A_MA_COR_ERROR_ENABLE1 0x779c + +#define S_ARB4_COR_WRQUEUE_ERROR_EN 9 +#define V_ARB4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR_EN) +#define F_ARB4_COR_WRQUEUE_ERROR_EN V_ARB4_COR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB3_COR_WRQUEUE_ERROR_EN 8 +#define V_ARB3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR_EN) +#define F_ARB3_COR_WRQUEUE_ERROR_EN V_ARB3_COR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB2_COR_WRQUEUE_ERROR_EN 7 +#define V_ARB2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR_EN) +#define F_ARB2_COR_WRQUEUE_ERROR_EN V_ARB2_COR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB1_COR_WRQUEUE_ERROR_EN 6 +#define V_ARB1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR_EN) +#define F_ARB1_COR_WRQUEUE_ERROR_EN V_ARB1_COR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB0_COR_WRQUEUE_ERROR_EN 5 +#define V_ARB0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR_EN) +#define F_ARB0_COR_WRQUEUE_ERROR_EN V_ARB0_COR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB4_COR_RDQUEUE_ERROR_EN 4 +#define V_ARB4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR_EN) +#define F_ARB4_COR_RDQUEUE_ERROR_EN V_ARB4_COR_RDQUEUE_ERROR_EN(1U) + +#define S_ARB3_COR_RDQUEUE_ERROR_EN 3 +#define V_ARB3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR_EN) +#define F_ARB3_COR_RDQUEUE_ERROR_EN V_ARB3_COR_RDQUEUE_ERROR_EN(1U) + +#define S_ARB2_COR_RDQUEUE_ERROR_EN 2 +#define V_ARB2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR_EN) +#define F_ARB2_COR_RDQUEUE_ERROR_EN V_ARB2_COR_RDQUEUE_ERROR_EN(1U) + +#define S_ARB1_COR_RDQUEUE_ERROR_EN 1 +#define V_ARB1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR_EN) +#define F_ARB1_COR_RDQUEUE_ERROR_EN V_ARB1_COR_RDQUEUE_ERROR_EN(1U) + +#define S_ARB0_COR_RDQUEUE_ERROR_EN 0 +#define V_ARB0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR_EN) +#define F_ARB0_COR_RDQUEUE_ERROR_EN V_ARB0_COR_RDQUEUE_ERROR_EN(1U) + +#define A_MA_COR_ERROR_STATUS1 0x77a0 + +#define S_ARB4_COR_WRQUEUE_ERROR 9 +#define V_ARB4_COR_WRQUEUE_ERROR(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR) +#define F_ARB4_COR_WRQUEUE_ERROR V_ARB4_COR_WRQUEUE_ERROR(1U) + +#define S_ARB3_COR_WRQUEUE_ERROR 8 +#define V_ARB3_COR_WRQUEUE_ERROR(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR) +#define F_ARB3_COR_WRQUEUE_ERROR V_ARB3_COR_WRQUEUE_ERROR(1U) + +#define S_ARB2_COR_WRQUEUE_ERROR 7 +#define V_ARB2_COR_WRQUEUE_ERROR(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR) +#define F_ARB2_COR_WRQUEUE_ERROR V_ARB2_COR_WRQUEUE_ERROR(1U) + +#define S_ARB1_COR_WRQUEUE_ERROR 6 +#define V_ARB1_COR_WRQUEUE_ERROR(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR) +#define F_ARB1_COR_WRQUEUE_ERROR V_ARB1_COR_WRQUEUE_ERROR(1U) + +#define S_ARB0_COR_WRQUEUE_ERROR 5 +#define V_ARB0_COR_WRQUEUE_ERROR(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR) +#define F_ARB0_COR_WRQUEUE_ERROR V_ARB0_COR_WRQUEUE_ERROR(1U) + +#define S_ARB4_COR_RDQUEUE_ERROR 4 +#define V_ARB4_COR_RDQUEUE_ERROR(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR) +#define F_ARB4_COR_RDQUEUE_ERROR V_ARB4_COR_RDQUEUE_ERROR(1U) + +#define S_ARB3_COR_RDQUEUE_ERROR 3 +#define V_ARB3_COR_RDQUEUE_ERROR(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR) +#define F_ARB3_COR_RDQUEUE_ERROR V_ARB3_COR_RDQUEUE_ERROR(1U) + +#define S_ARB2_COR_RDQUEUE_ERROR 2 +#define V_ARB2_COR_RDQUEUE_ERROR(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR) +#define F_ARB2_COR_RDQUEUE_ERROR V_ARB2_COR_RDQUEUE_ERROR(1U) + +#define S_ARB1_COR_RDQUEUE_ERROR 1 +#define V_ARB1_COR_RDQUEUE_ERROR(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR) +#define F_ARB1_COR_RDQUEUE_ERROR V_ARB1_COR_RDQUEUE_ERROR(1U) + +#define S_ARB0_COR_RDQUEUE_ERROR 0 +#define V_ARB0_COR_RDQUEUE_ERROR(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR) +#define F_ARB0_COR_RDQUEUE_ERROR V_ARB0_COR_RDQUEUE_ERROR(1U) + +#define A_MA_DBG_CTL 0x77a4 + +#define S_DATAH_SEL 20 +#define V_DATAH_SEL(x) ((x) << S_DATAH_SEL) +#define F_DATAH_SEL V_DATAH_SEL(1U) + +#define S_EN_DBG 16 +#define V_EN_DBG(x) ((x) << S_EN_DBG) +#define F_EN_DBG V_EN_DBG(1U) + +#define S_T7_SEL 0 +#define M_T7_SEL 0xffU +#define V_T7_SEL(x) ((x) << S_T7_SEL) +#define G_T7_SEL(x) (((x) >> S_T7_SEL) & M_T7_SEL) + +#define A_MA_DBG_DATA 0x77a8 +#define A_MA_COR_ERROR_ENABLE2 0x77b0 + +#define S_CL14_COR_WRQUEUE_ERROR_EN 14 +#define V_CL14_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_WRQUEUE_ERROR_EN) +#define F_CL14_COR_WRQUEUE_ERROR_EN V_CL14_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL13_COR_WRQUEUE_ERROR_EN 13 +#define V_CL13_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_WRQUEUE_ERROR_EN) +#define F_CL13_COR_WRQUEUE_ERROR_EN V_CL13_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL12_COR_WRQUEUE_ERROR_EN 12 +#define V_CL12_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_WRQUEUE_ERROR_EN) +#define F_CL12_COR_WRQUEUE_ERROR_EN V_CL12_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL11_COR_WRQUEUE_ERROR_EN 11 +#define V_CL11_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_WRQUEUE_ERROR_EN) +#define F_CL11_COR_WRQUEUE_ERROR_EN V_CL11_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL10_COR_WRQUEUE_ERROR_EN 10 +#define V_CL10_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_WRQUEUE_ERROR_EN) +#define F_CL10_COR_WRQUEUE_ERROR_EN V_CL10_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL9_COR_WRQUEUE_ERROR_EN 9 +#define V_CL9_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_WRQUEUE_ERROR_EN) +#define F_CL9_COR_WRQUEUE_ERROR_EN V_CL9_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL8_COR_WRQUEUE_ERROR_EN 8 +#define V_CL8_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_WRQUEUE_ERROR_EN) +#define F_CL8_COR_WRQUEUE_ERROR_EN V_CL8_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL7_COR_WRQUEUE_ERROR_EN 7 +#define V_CL7_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_WRQUEUE_ERROR_EN) +#define F_CL7_COR_WRQUEUE_ERROR_EN V_CL7_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL6_COR_WRQUEUE_ERROR_EN 6 +#define V_CL6_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_WRQUEUE_ERROR_EN) +#define F_CL6_COR_WRQUEUE_ERROR_EN V_CL6_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL5_COR_WRQUEUE_ERROR_EN 5 +#define V_CL5_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_WRQUEUE_ERROR_EN) +#define F_CL5_COR_WRQUEUE_ERROR_EN V_CL5_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL4_COR_WRQUEUE_ERROR_EN 4 +#define V_CL4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_WRQUEUE_ERROR_EN) +#define F_CL4_COR_WRQUEUE_ERROR_EN V_CL4_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL3_COR_WRQUEUE_ERROR_EN 3 +#define V_CL3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_WRQUEUE_ERROR_EN) +#define F_CL3_COR_WRQUEUE_ERROR_EN V_CL3_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL2_COR_WRQUEUE_ERROR_EN 2 +#define V_CL2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_WRQUEUE_ERROR_EN) +#define F_CL2_COR_WRQUEUE_ERROR_EN V_CL2_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL1_COR_WRQUEUE_ERROR_EN 1 +#define V_CL1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_WRQUEUE_ERROR_EN) +#define F_CL1_COR_WRQUEUE_ERROR_EN V_CL1_COR_WRQUEUE_ERROR_EN(1U) + +#define S_CL0_COR_WRQUEUE_ERROR_EN 0 +#define V_CL0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_WRQUEUE_ERROR_EN) +#define F_CL0_COR_WRQUEUE_ERROR_EN V_CL0_COR_WRQUEUE_ERROR_EN(1U) + +#define A_MA_COR_ERROR_STATUS2 0x77b4 + +#define S_CL14_COR_WRQUEUE_ERROR 14 +#define V_CL14_COR_WRQUEUE_ERROR(x) ((x) << S_CL14_COR_WRQUEUE_ERROR) +#define F_CL14_COR_WRQUEUE_ERROR V_CL14_COR_WRQUEUE_ERROR(1U) + +#define S_CL13_COR_WRQUEUE_ERROR 13 +#define V_CL13_COR_WRQUEUE_ERROR(x) ((x) << S_CL13_COR_WRQUEUE_ERROR) +#define F_CL13_COR_WRQUEUE_ERROR V_CL13_COR_WRQUEUE_ERROR(1U) + +#define S_CL12_COR_WRQUEUE_ERROR 12 +#define V_CL12_COR_WRQUEUE_ERROR(x) ((x) << S_CL12_COR_WRQUEUE_ERROR) +#define F_CL12_COR_WRQUEUE_ERROR V_CL12_COR_WRQUEUE_ERROR(1U) + +#define S_CL11_COR_WRQUEUE_ERROR 11 +#define V_CL11_COR_WRQUEUE_ERROR(x) ((x) << S_CL11_COR_WRQUEUE_ERROR) +#define F_CL11_COR_WRQUEUE_ERROR V_CL11_COR_WRQUEUE_ERROR(1U) + +#define S_CL10_COR_WRQUEUE_ERROR 10 +#define V_CL10_COR_WRQUEUE_ERROR(x) ((x) << S_CL10_COR_WRQUEUE_ERROR) +#define F_CL10_COR_WRQUEUE_ERROR V_CL10_COR_WRQUEUE_ERROR(1U) + +#define S_CL9_COR_WRQUEUE_ERROR 9 +#define V_CL9_COR_WRQUEUE_ERROR(x) ((x) << S_CL9_COR_WRQUEUE_ERROR) +#define F_CL9_COR_WRQUEUE_ERROR V_CL9_COR_WRQUEUE_ERROR(1U) + +#define S_CL8_COR_WRQUEUE_ERROR 8 +#define V_CL8_COR_WRQUEUE_ERROR(x) ((x) << S_CL8_COR_WRQUEUE_ERROR) +#define F_CL8_COR_WRQUEUE_ERROR V_CL8_COR_WRQUEUE_ERROR(1U) + +#define S_CL7_COR_WRQUEUE_ERROR 7 +#define V_CL7_COR_WRQUEUE_ERROR(x) ((x) << S_CL7_COR_WRQUEUE_ERROR) +#define F_CL7_COR_WRQUEUE_ERROR V_CL7_COR_WRQUEUE_ERROR(1U) + +#define S_CL6_COR_WRQUEUE_ERROR 6 +#define V_CL6_COR_WRQUEUE_ERROR(x) ((x) << S_CL6_COR_WRQUEUE_ERROR) +#define F_CL6_COR_WRQUEUE_ERROR V_CL6_COR_WRQUEUE_ERROR(1U) + +#define S_CL5_COR_WRQUEUE_ERROR 5 +#define V_CL5_COR_WRQUEUE_ERROR(x) ((x) << S_CL5_COR_WRQUEUE_ERROR) +#define F_CL5_COR_WRQUEUE_ERROR V_CL5_COR_WRQUEUE_ERROR(1U) + +#define S_CL4_COR_WRQUEUE_ERROR 4 +#define V_CL4_COR_WRQUEUE_ERROR(x) ((x) << S_CL4_COR_WRQUEUE_ERROR) +#define F_CL4_COR_WRQUEUE_ERROR V_CL4_COR_WRQUEUE_ERROR(1U) + +#define S_CL3_COR_WRQUEUE_ERROR 3 +#define V_CL3_COR_WRQUEUE_ERROR(x) ((x) << S_CL3_COR_WRQUEUE_ERROR) +#define F_CL3_COR_WRQUEUE_ERROR V_CL3_COR_WRQUEUE_ERROR(1U) + +#define S_CL2_COR_WRQUEUE_ERROR 2 +#define V_CL2_COR_WRQUEUE_ERROR(x) ((x) << S_CL2_COR_WRQUEUE_ERROR) +#define F_CL2_COR_WRQUEUE_ERROR V_CL2_COR_WRQUEUE_ERROR(1U) + +#define S_CL1_COR_WRQUEUE_ERROR 1 +#define V_CL1_COR_WRQUEUE_ERROR(x) ((x) << S_CL1_COR_WRQUEUE_ERROR) +#define F_CL1_COR_WRQUEUE_ERROR V_CL1_COR_WRQUEUE_ERROR(1U) + +#define S_CL0_COR_WRQUEUE_ERROR 0 +#define V_CL0_COR_WRQUEUE_ERROR(x) ((x) << S_CL0_COR_WRQUEUE_ERROR) +#define F_CL0_COR_WRQUEUE_ERROR V_CL0_COR_WRQUEUE_ERROR(1U) + +#define A_MA_COR_ERROR_ENABLE3 0x77b8 + +#define S_CL14_COR_RDQUEUE_ERROR_EN 14 +#define V_CL14_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_RDQUEUE_ERROR_EN) +#define F_CL14_COR_RDQUEUE_ERROR_EN V_CL14_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL13_COR_RDQUEUE_ERROR_EN 13 +#define V_CL13_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_RDQUEUE_ERROR_EN) +#define F_CL13_COR_RDQUEUE_ERROR_EN V_CL13_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL12_COR_RDQUEUE_ERROR_EN 12 +#define V_CL12_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_RDQUEUE_ERROR_EN) +#define F_CL12_COR_RDQUEUE_ERROR_EN V_CL12_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL11_COR_RDQUEUE_ERROR_EN 11 +#define V_CL11_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_RDQUEUE_ERROR_EN) +#define F_CL11_COR_RDQUEUE_ERROR_EN V_CL11_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL10_COR_RDQUEUE_ERROR_EN 10 +#define V_CL10_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_RDQUEUE_ERROR_EN) +#define F_CL10_COR_RDQUEUE_ERROR_EN V_CL10_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL9_COR_RDQUEUE_ERROR_EN 9 +#define V_CL9_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_RDQUEUE_ERROR_EN) +#define F_CL9_COR_RDQUEUE_ERROR_EN V_CL9_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL8_COR_RDQUEUE_ERROR_EN 8 +#define V_CL8_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_RDQUEUE_ERROR_EN) +#define F_CL8_COR_RDQUEUE_ERROR_EN V_CL8_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL7_COR_RDQUEUE_ERROR_EN 7 +#define V_CL7_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_RDQUEUE_ERROR_EN) +#define F_CL7_COR_RDQUEUE_ERROR_EN V_CL7_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL6_COR_RDQUEUE_ERROR_EN 6 +#define V_CL6_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_RDQUEUE_ERROR_EN) +#define F_CL6_COR_RDQUEUE_ERROR_EN V_CL6_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL5_COR_RDQUEUE_ERROR_EN 5 +#define V_CL5_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_RDQUEUE_ERROR_EN) +#define F_CL5_COR_RDQUEUE_ERROR_EN V_CL5_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL4_COR_RDQUEUE_ERROR_EN 4 +#define V_CL4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_RDQUEUE_ERROR_EN) +#define F_CL4_COR_RDQUEUE_ERROR_EN V_CL4_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL3_COR_RDQUEUE_ERROR_EN 3 +#define V_CL3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_RDQUEUE_ERROR_EN) +#define F_CL3_COR_RDQUEUE_ERROR_EN V_CL3_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL2_COR_RDQUEUE_ERROR_EN 2 +#define V_CL2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_RDQUEUE_ERROR_EN) +#define F_CL2_COR_RDQUEUE_ERROR_EN V_CL2_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL1_COR_RDQUEUE_ERROR_EN 1 +#define V_CL1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_RDQUEUE_ERROR_EN) +#define F_CL1_COR_RDQUEUE_ERROR_EN V_CL1_COR_RDQUEUE_ERROR_EN(1U) + +#define S_CL0_COR_RDQUEUE_ERROR_EN 0 +#define V_CL0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_RDQUEUE_ERROR_EN) +#define F_CL0_COR_RDQUEUE_ERROR_EN V_CL0_COR_RDQUEUE_ERROR_EN(1U) + +#define A_MA_COR_ERROR_STATUS3 0x77bc + +#define S_CL14_COR_RDQUEUE_ERROR 14 +#define V_CL14_COR_RDQUEUE_ERROR(x) ((x) << S_CL14_COR_RDQUEUE_ERROR) +#define F_CL14_COR_RDQUEUE_ERROR V_CL14_COR_RDQUEUE_ERROR(1U) + +#define S_CL13_COR_RDQUEUE_ERROR 13 +#define V_CL13_COR_RDQUEUE_ERROR(x) ((x) << S_CL13_COR_RDQUEUE_ERROR) +#define F_CL13_COR_RDQUEUE_ERROR V_CL13_COR_RDQUEUE_ERROR(1U) + +#define S_CL12_COR_RDQUEUE_ERROR 12 +#define V_CL12_COR_RDQUEUE_ERROR(x) ((x) << S_CL12_COR_RDQUEUE_ERROR) +#define F_CL12_COR_RDQUEUE_ERROR V_CL12_COR_RDQUEUE_ERROR(1U) + +#define S_CL11_COR_RDQUEUE_ERROR 11 +#define V_CL11_COR_RDQUEUE_ERROR(x) ((x) << S_CL11_COR_RDQUEUE_ERROR) +#define F_CL11_COR_RDQUEUE_ERROR V_CL11_COR_RDQUEUE_ERROR(1U) + +#define S_CL10_COR_RDQUEUE_ERROR 10 +#define V_CL10_COR_RDQUEUE_ERROR(x) ((x) << S_CL10_COR_RDQUEUE_ERROR) +#define F_CL10_COR_RDQUEUE_ERROR V_CL10_COR_RDQUEUE_ERROR(1U) + +#define S_CL9_COR_RDQUEUE_ERROR 9 +#define V_CL9_COR_RDQUEUE_ERROR(x) ((x) << S_CL9_COR_RDQUEUE_ERROR) +#define F_CL9_COR_RDQUEUE_ERROR V_CL9_COR_RDQUEUE_ERROR(1U) + +#define S_CL8_COR_RDQUEUE_ERROR 8 +#define V_CL8_COR_RDQUEUE_ERROR(x) ((x) << S_CL8_COR_RDQUEUE_ERROR) +#define F_CL8_COR_RDQUEUE_ERROR V_CL8_COR_RDQUEUE_ERROR(1U) + +#define S_CL7_COR_RDQUEUE_ERROR 7 +#define V_CL7_COR_RDQUEUE_ERROR(x) ((x) << S_CL7_COR_RDQUEUE_ERROR) +#define F_CL7_COR_RDQUEUE_ERROR V_CL7_COR_RDQUEUE_ERROR(1U) + +#define S_CL6_COR_RDQUEUE_ERROR 6 +#define V_CL6_COR_RDQUEUE_ERROR(x) ((x) << S_CL6_COR_RDQUEUE_ERROR) +#define F_CL6_COR_RDQUEUE_ERROR V_CL6_COR_RDQUEUE_ERROR(1U) + +#define S_CL5_COR_RDQUEUE_ERROR 5 +#define V_CL5_COR_RDQUEUE_ERROR(x) ((x) << S_CL5_COR_RDQUEUE_ERROR) +#define F_CL5_COR_RDQUEUE_ERROR V_CL5_COR_RDQUEUE_ERROR(1U) + +#define S_CL4_COR_RDQUEUE_ERROR 4 +#define V_CL4_COR_RDQUEUE_ERROR(x) ((x) << S_CL4_COR_RDQUEUE_ERROR) +#define F_CL4_COR_RDQUEUE_ERROR V_CL4_COR_RDQUEUE_ERROR(1U) + +#define S_CL3_COR_RDQUEUE_ERROR 3 +#define V_CL3_COR_RDQUEUE_ERROR(x) ((x) << S_CL3_COR_RDQUEUE_ERROR) +#define F_CL3_COR_RDQUEUE_ERROR V_CL3_COR_RDQUEUE_ERROR(1U) + +#define S_CL2_COR_RDQUEUE_ERROR 2 +#define V_CL2_COR_RDQUEUE_ERROR(x) ((x) << S_CL2_COR_RDQUEUE_ERROR) +#define F_CL2_COR_RDQUEUE_ERROR V_CL2_COR_RDQUEUE_ERROR(1U) + +#define S_CL1_COR_RDQUEUE_ERROR 1 +#define V_CL1_COR_RDQUEUE_ERROR(x) ((x) << S_CL1_COR_RDQUEUE_ERROR) +#define F_CL1_COR_RDQUEUE_ERROR V_CL1_COR_RDQUEUE_ERROR(1U) + +#define S_CL0_COR_RDQUEUE_ERROR 0 +#define V_CL0_COR_RDQUEUE_ERROR(x) ((x) << S_CL0_COR_RDQUEUE_ERROR) +#define F_CL0_COR_RDQUEUE_ERROR V_CL0_COR_RDQUEUE_ERROR(1U) + #define A_MA_EDRAM0_BAR 0x77c0 #define S_EDRAM0_BASE 16 @@ -16119,6 +20575,16 @@ #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE) #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE) +#define S_T7_EDRAM0_BASE 16 +#define M_T7_EDRAM0_BASE 0xffffU +#define V_T7_EDRAM0_BASE(x) ((x) << S_T7_EDRAM0_BASE) +#define G_T7_EDRAM0_BASE(x) (((x) >> S_T7_EDRAM0_BASE) & M_T7_EDRAM0_BASE) + +#define S_T7_EDRAM0_SIZE 0 +#define M_T7_EDRAM0_SIZE 0xffffU +#define V_T7_EDRAM0_SIZE(x) ((x) << S_T7_EDRAM0_SIZE) +#define G_T7_EDRAM0_SIZE(x) (((x) >> S_T7_EDRAM0_SIZE) & M_T7_EDRAM0_SIZE) + #define A_MA_EDRAM1_BAR 0x77c4 #define S_EDRAM1_BASE 16 @@ -16131,6 +20597,16 @@ #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE) #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE) +#define S_T7_EDRAM1_BASE 16 +#define M_T7_EDRAM1_BASE 0xffffU +#define V_T7_EDRAM1_BASE(x) ((x) << S_T7_EDRAM1_BASE) +#define G_T7_EDRAM1_BASE(x) (((x) >> S_T7_EDRAM1_BASE) & M_T7_EDRAM1_BASE) + +#define S_T7_EDRAM1_SIZE 0 +#define M_T7_EDRAM1_SIZE 0xffffU +#define V_T7_EDRAM1_SIZE(x) ((x) << S_T7_EDRAM1_SIZE) +#define G_T7_EDRAM1_SIZE(x) (((x) >> S_T7_EDRAM1_SIZE) & M_T7_EDRAM1_SIZE) + #define A_MA_EXT_MEMORY_BAR 0x77c8 #define S_EXT_MEM_BASE 16 @@ -16155,6 +20631,16 @@ #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE) #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE) +#define S_T7_EXT_MEM0_BASE 16 +#define M_T7_EXT_MEM0_BASE 0xffffU +#define V_T7_EXT_MEM0_BASE(x) ((x) << S_T7_EXT_MEM0_BASE) +#define G_T7_EXT_MEM0_BASE(x) (((x) >> S_T7_EXT_MEM0_BASE) & M_T7_EXT_MEM0_BASE) + +#define S_T7_EXT_MEM0_SIZE 0 +#define M_T7_EXT_MEM0_SIZE 0xffffU +#define V_T7_EXT_MEM0_SIZE(x) ((x) << S_T7_EXT_MEM0_SIZE) +#define G_T7_EXT_MEM0_SIZE(x) (((x) >> S_T7_EXT_MEM0_SIZE) & M_T7_EXT_MEM0_SIZE) + #define A_MA_HOST_MEMORY_BAR 0x77cc #define S_HMA_BASE 16 @@ -16167,6 +20653,16 @@ #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE) #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE) +#define S_HMATARGETBASE 16 +#define M_HMATARGETBASE 0xffffU +#define V_HMATARGETBASE(x) ((x) << S_HMATARGETBASE) +#define G_HMATARGETBASE(x) (((x) >> S_HMATARGETBASE) & M_HMATARGETBASE) + +#define S_T7_HMA_SIZE 0 +#define M_T7_HMA_SIZE 0xffffU +#define V_T7_HMA_SIZE(x) ((x) << S_T7_HMA_SIZE) +#define G_T7_HMA_SIZE(x) (((x) >> S_T7_HMA_SIZE) & M_T7_HMA_SIZE) + #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0 #define S_BRC_MODE 2 @@ -16290,6 +20786,14 @@ #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT) #define F_MC_SPLIT V_MC_SPLIT(1U) +#define S_EDC512 8 +#define V_EDC512(x) ((x) << S_EDC512) +#define F_EDC512 V_EDC512(1U) + +#define S_MC_SPLIT_BOUNDARY 7 +#define V_MC_SPLIT_BOUNDARY(x) ((x) << S_MC_SPLIT_BOUNDARY) +#define F_MC_SPLIT_BOUNDARY V_MC_SPLIT_BOUNDARY(1U) + #define A_MA_INT_ENABLE 0x77dc #define S_MEM_PERR_INT_ENABLE 1 @@ -16475,6 +20979,55 @@ #define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U) #define A_MA_PARITY_ERROR_ENABLE1 0x77f0 + +#define S_T7_ARB4_PAR_WRQUEUE_ERROR_EN 11 +#define V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR_EN) +#define F_T7_ARB4_PAR_WRQUEUE_ERROR_EN V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_ARB3_PAR_WRQUEUE_ERROR_EN 10 +#define V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR_EN) +#define F_T7_ARB3_PAR_WRQUEUE_ERROR_EN V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_ARB2_PAR_WRQUEUE_ERROR_EN 9 +#define V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR_EN) +#define F_T7_ARB2_PAR_WRQUEUE_ERROR_EN V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_ARB1_PAR_WRQUEUE_ERROR_EN 8 +#define V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR_EN) +#define F_T7_ARB1_PAR_WRQUEUE_ERROR_EN V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_ARB0_PAR_WRQUEUE_ERROR_EN 7 +#define V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR_EN) +#define F_T7_ARB0_PAR_WRQUEUE_ERROR_EN V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_ARB4_PAR_RDQUEUE_ERROR_EN 6 +#define V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR_EN) +#define F_T7_ARB4_PAR_RDQUEUE_ERROR_EN V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_T7_ARB3_PAR_RDQUEUE_ERROR_EN 5 +#define V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR_EN) +#define F_T7_ARB3_PAR_RDQUEUE_ERROR_EN V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_T7_ARB2_PAR_RDQUEUE_ERROR_EN 4 +#define V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR_EN) +#define F_T7_ARB2_PAR_RDQUEUE_ERROR_EN V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_T7_ARB1_PAR_RDQUEUE_ERROR_EN 3 +#define V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR_EN) +#define F_T7_ARB1_PAR_RDQUEUE_ERROR_EN V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_T7_ARB0_PAR_RDQUEUE_ERROR_EN 2 +#define V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR_EN) +#define F_T7_ARB0_PAR_RDQUEUE_ERROR_EN V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_T7_TP_DMARBT_PAR_ERROR_EN 1 +#define V_T7_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR_EN) +#define F_T7_TP_DMARBT_PAR_ERROR_EN V_T7_TP_DMARBT_PAR_ERROR_EN(1U) + +#define S_T7_LOGIC_FIFO_PAR_ERROR_EN 0 +#define V_T7_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR_EN) +#define F_T7_LOGIC_FIFO_PAR_ERROR_EN V_T7_LOGIC_FIFO_PAR_ERROR_EN(1U) + #define A_MA_PARITY_ERROR_STATUS 0x77f4 #define S_TP_DMARBT_PAR_ERROR 31 @@ -16606,6 +21159,55 @@ #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U) #define A_MA_PARITY_ERROR_STATUS1 0x77f4 + +#define S_T7_ARB4_PAR_WRQUEUE_ERROR 11 +#define V_T7_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR) +#define F_T7_ARB4_PAR_WRQUEUE_ERROR V_T7_ARB4_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_ARB3_PAR_WRQUEUE_ERROR 10 +#define V_T7_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR) +#define F_T7_ARB3_PAR_WRQUEUE_ERROR V_T7_ARB3_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_ARB2_PAR_WRQUEUE_ERROR 9 +#define V_T7_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR) +#define F_T7_ARB2_PAR_WRQUEUE_ERROR V_T7_ARB2_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_ARB1_PAR_WRQUEUE_ERROR 8 +#define V_T7_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR) +#define F_T7_ARB1_PAR_WRQUEUE_ERROR V_T7_ARB1_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_ARB0_PAR_WRQUEUE_ERROR 7 +#define V_T7_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR) +#define F_T7_ARB0_PAR_WRQUEUE_ERROR V_T7_ARB0_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_ARB4_PAR_RDQUEUE_ERROR 6 +#define V_T7_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR) +#define F_T7_ARB4_PAR_RDQUEUE_ERROR V_T7_ARB4_PAR_RDQUEUE_ERROR(1U) + +#define S_T7_ARB3_PAR_RDQUEUE_ERROR 5 +#define V_T7_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR) +#define F_T7_ARB3_PAR_RDQUEUE_ERROR V_T7_ARB3_PAR_RDQUEUE_ERROR(1U) + +#define S_T7_ARB2_PAR_RDQUEUE_ERROR 4 +#define V_T7_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR) +#define F_T7_ARB2_PAR_RDQUEUE_ERROR V_T7_ARB2_PAR_RDQUEUE_ERROR(1U) + +#define S_T7_ARB1_PAR_RDQUEUE_ERROR 3 +#define V_T7_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR) +#define F_T7_ARB1_PAR_RDQUEUE_ERROR V_T7_ARB1_PAR_RDQUEUE_ERROR(1U) + +#define S_T7_ARB0_PAR_RDQUEUE_ERROR 2 +#define V_T7_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR) +#define F_T7_ARB0_PAR_RDQUEUE_ERROR V_T7_ARB0_PAR_RDQUEUE_ERROR(1U) + +#define S_T7_TP_DMARBT_PAR_ERROR 1 +#define V_T7_TP_DMARBT_PAR_ERROR(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR) +#define F_T7_TP_DMARBT_PAR_ERROR V_T7_TP_DMARBT_PAR_ERROR(1U) + +#define S_T7_LOGIC_FIFO_PAR_ERROR 0 +#define V_T7_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR) +#define F_T7_LOGIC_FIFO_PAR_ERROR V_T7_LOGIC_FIFO_PAR_ERROR(1U) + #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8 #define S_BONUS_REG 6 @@ -16653,6 +21255,66 @@ #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN) #define F_ARB4_PAR_RDQUEUE_ERROR_EN V_ARB4_PAR_RDQUEUE_ERROR_EN(1U) +#define S_CL14_PAR_WRQUEUE_ERROR_EN 14 +#define V_CL14_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR_EN) +#define F_CL14_PAR_WRQUEUE_ERROR_EN V_CL14_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_CL13_PAR_WRQUEUE_ERROR_EN 13 +#define V_CL13_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR_EN) +#define F_CL13_PAR_WRQUEUE_ERROR_EN V_CL13_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_CL12_PAR_WRQUEUE_ERROR_EN 12 +#define V_CL12_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR_EN) +#define F_CL12_PAR_WRQUEUE_ERROR_EN V_CL12_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_CL11_PAR_WRQUEUE_ERROR_EN 11 +#define V_CL11_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR_EN) +#define F_CL11_PAR_WRQUEUE_ERROR_EN V_CL11_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL10_PAR_WRQUEUE_ERROR_EN 10 +#define V_T7_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL10_PAR_WRQUEUE_ERROR_EN V_T7_CL10_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL9_PAR_WRQUEUE_ERROR_EN 9 +#define V_T7_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL9_PAR_WRQUEUE_ERROR_EN V_T7_CL9_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL8_PAR_WRQUEUE_ERROR_EN 8 +#define V_T7_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL8_PAR_WRQUEUE_ERROR_EN V_T7_CL8_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL7_PAR_WRQUEUE_ERROR_EN 7 +#define V_T7_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL7_PAR_WRQUEUE_ERROR_EN V_T7_CL7_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL6_PAR_WRQUEUE_ERROR_EN 6 +#define V_T7_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL6_PAR_WRQUEUE_ERROR_EN V_T7_CL6_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL5_PAR_WRQUEUE_ERROR_EN 5 +#define V_T7_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL5_PAR_WRQUEUE_ERROR_EN V_T7_CL5_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL4_PAR_WRQUEUE_ERROR_EN 4 +#define V_T7_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL4_PAR_WRQUEUE_ERROR_EN V_T7_CL4_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL3_PAR_WRQUEUE_ERROR_EN 3 +#define V_T7_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL3_PAR_WRQUEUE_ERROR_EN V_T7_CL3_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL2_PAR_WRQUEUE_ERROR_EN 2 +#define V_T7_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL2_PAR_WRQUEUE_ERROR_EN V_T7_CL2_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL1_PAR_WRQUEUE_ERROR_EN 1 +#define V_T7_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL1_PAR_WRQUEUE_ERROR_EN V_T7_CL1_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_T7_CL0_PAR_WRQUEUE_ERROR_EN 0 +#define V_T7_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR_EN) +#define F_T7_CL0_PAR_WRQUEUE_ERROR_EN V_T7_CL0_PAR_WRQUEUE_ERROR_EN(1U) + #define A_MA_PARITY_ERROR_STATUS2 0x7804 #define S_ARB4_PAR_WRQUEUE_ERROR 1 @@ -16663,6 +21325,66 @@ #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR) #define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U) +#define S_CL14_PAR_WRQUEUE_ERROR 14 +#define V_CL14_PAR_WRQUEUE_ERROR(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR) +#define F_CL14_PAR_WRQUEUE_ERROR V_CL14_PAR_WRQUEUE_ERROR(1U) + +#define S_CL13_PAR_WRQUEUE_ERROR 13 +#define V_CL13_PAR_WRQUEUE_ERROR(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR) +#define F_CL13_PAR_WRQUEUE_ERROR V_CL13_PAR_WRQUEUE_ERROR(1U) + +#define S_CL12_PAR_WRQUEUE_ERROR 12 +#define V_CL12_PAR_WRQUEUE_ERROR(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR) +#define F_CL12_PAR_WRQUEUE_ERROR V_CL12_PAR_WRQUEUE_ERROR(1U) + +#define S_CL11_PAR_WRQUEUE_ERROR 11 +#define V_CL11_PAR_WRQUEUE_ERROR(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR) +#define F_CL11_PAR_WRQUEUE_ERROR V_CL11_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL10_PAR_WRQUEUE_ERROR 10 +#define V_T7_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR) +#define F_T7_CL10_PAR_WRQUEUE_ERROR V_T7_CL10_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL9_PAR_WRQUEUE_ERROR 9 +#define V_T7_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR) +#define F_T7_CL9_PAR_WRQUEUE_ERROR V_T7_CL9_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL8_PAR_WRQUEUE_ERROR 8 +#define V_T7_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR) +#define F_T7_CL8_PAR_WRQUEUE_ERROR V_T7_CL8_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL7_PAR_WRQUEUE_ERROR 7 +#define V_T7_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR) +#define F_T7_CL7_PAR_WRQUEUE_ERROR V_T7_CL7_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL6_PAR_WRQUEUE_ERROR 6 +#define V_T7_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR) +#define F_T7_CL6_PAR_WRQUEUE_ERROR V_T7_CL6_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL5_PAR_WRQUEUE_ERROR 5 +#define V_T7_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR) +#define F_T7_CL5_PAR_WRQUEUE_ERROR V_T7_CL5_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL4_PAR_WRQUEUE_ERROR 4 +#define V_T7_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR) +#define F_T7_CL4_PAR_WRQUEUE_ERROR V_T7_CL4_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL3_PAR_WRQUEUE_ERROR 3 +#define V_T7_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR) +#define F_T7_CL3_PAR_WRQUEUE_ERROR V_T7_CL3_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL2_PAR_WRQUEUE_ERROR 2 +#define V_T7_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR) +#define F_T7_CL2_PAR_WRQUEUE_ERROR V_T7_CL2_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL1_PAR_WRQUEUE_ERROR 1 +#define V_T7_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR) +#define F_T7_CL1_PAR_WRQUEUE_ERROR V_T7_CL1_PAR_WRQUEUE_ERROR(1U) + +#define S_T7_CL0_PAR_WRQUEUE_ERROR 0 +#define V_T7_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR) +#define F_T7_CL0_PAR_WRQUEUE_ERROR V_T7_CL0_PAR_WRQUEUE_ERROR(1U) + #define A_MA_EXT_MEMORY1_BAR 0x7808 #define S_EXT_MEM1_BASE 16 @@ -16675,6 +21397,16 @@ #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE) #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE) +#define S_T7_EXT_MEM1_BASE 16 +#define M_T7_EXT_MEM1_BASE 0xffffU +#define V_T7_EXT_MEM1_BASE(x) ((x) << S_T7_EXT_MEM1_BASE) +#define G_T7_EXT_MEM1_BASE(x) (((x) >> S_T7_EXT_MEM1_BASE) & M_T7_EXT_MEM1_BASE) + +#define S_T7_EXT_MEM1_SIZE 0 +#define M_T7_EXT_MEM1_SIZE 0xffffU +#define V_T7_EXT_MEM1_SIZE(x) ((x) << S_T7_EXT_MEM1_SIZE) +#define G_T7_EXT_MEM1_SIZE(x) (((x) >> S_T7_EXT_MEM1_SIZE) & M_T7_EXT_MEM1_SIZE) + #define A_MA_PMTX_THROTTLE 0x780c #define S_FL_ENABLE 31 @@ -16696,6 +21428,7 @@ #define A_MA_TP_TH1_WRDATA_CNT 0x782c #define A_MA_LE_WRDATA_CNT 0x7830 #define A_MA_CIM_WRDATA_CNT 0x7834 +#define A_MA_CIM_TH0_WRDATA_CNT 0x7834 #define A_MA_PCIE_WRDATA_CNT 0x7838 #define A_MA_PMTX_WRDATA_CNT 0x783c #define A_MA_PMRX_WRDATA_CNT 0x7840 @@ -16709,6 +21442,7 @@ #define A_MA_TP_TH1_RDDATA_CNT 0x7860 #define A_MA_LE_RDDATA_CNT 0x7864 #define A_MA_CIM_RDDATA_CNT 0x7868 +#define A_MA_CIM_TH0_RDDATA_CNT 0x7868 #define A_MA_PCIE_RDDATA_CNT 0x786c #define A_MA_PMTX_RDDATA_CNT 0x7870 #define A_MA_PMRX_RDDATA_CNT 0x7874 @@ -16733,7 +21467,43 @@ #define F_DDR_MODE V_DDR_MODE(1U) #define A_MA_EDRAM1_WRDATA_CNT1 0x7884 +#define A_MA_PARITY_ERROR_ENABLE3 0x7884 + +#define S_CL14_PAR_RDQUEUE_ERROR_EN 14 +#define V_CL14_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR_EN) +#define F_CL14_PAR_RDQUEUE_ERROR_EN V_CL14_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_CL13_PAR_RDQUEUE_ERROR_EN 13 +#define V_CL13_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR_EN) +#define F_CL13_PAR_RDQUEUE_ERROR_EN V_CL13_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_CL12_PAR_RDQUEUE_ERROR_EN 12 +#define V_CL12_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR_EN) +#define F_CL12_PAR_RDQUEUE_ERROR_EN V_CL12_PAR_RDQUEUE_ERROR_EN(1U) + +#define S_CL11_PAR_RDQUEUE_ERROR_EN 11 +#define V_CL11_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR_EN) +#define F_CL11_PAR_RDQUEUE_ERROR_EN V_CL11_PAR_RDQUEUE_ERROR_EN(1U) + #define A_MA_EDRAM1_WRDATA_CNT0 0x7888 +#define A_MA_PARITY_ERROR_STATUS3 0x7888 + +#define S_CL14_PAR_RDQUEUE_ERROR 14 +#define V_CL14_PAR_RDQUEUE_ERROR(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR) +#define F_CL14_PAR_RDQUEUE_ERROR V_CL14_PAR_RDQUEUE_ERROR(1U) + +#define S_CL13_PAR_RDQUEUE_ERROR 13 +#define V_CL13_PAR_RDQUEUE_ERROR(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR) +#define F_CL13_PAR_RDQUEUE_ERROR V_CL13_PAR_RDQUEUE_ERROR(1U) + +#define S_CL12_PAR_RDQUEUE_ERROR 12 +#define V_CL12_PAR_RDQUEUE_ERROR(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR) +#define F_CL12_PAR_RDQUEUE_ERROR V_CL12_PAR_RDQUEUE_ERROR(1U) + +#define S_CL11_PAR_RDQUEUE_ERROR 11 +#define V_CL11_PAR_RDQUEUE_ERROR(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR) +#define F_CL11_PAR_RDQUEUE_ERROR V_CL11_PAR_RDQUEUE_ERROR(1U) + #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894 @@ -16915,6 +21685,30 @@ #define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE) #define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE) +#define S_T7_FUTURE_CEXPANSION_WTE 31 +#define V_T7_FUTURE_CEXPANSION_WTE(x) ((x) << S_T7_FUTURE_CEXPANSION_WTE) +#define F_T7_FUTURE_CEXPANSION_WTE V_T7_FUTURE_CEXPANSION_WTE(1U) + +#define S_CL14_WR_CMD_TO_EN 30 +#define V_CL14_WR_CMD_TO_EN(x) ((x) << S_CL14_WR_CMD_TO_EN) +#define F_CL14_WR_CMD_TO_EN V_CL14_WR_CMD_TO_EN(1U) + +#define S_CL13_WR_CMD_TO_EN 29 +#define V_CL13_WR_CMD_TO_EN(x) ((x) << S_CL13_WR_CMD_TO_EN) +#define F_CL13_WR_CMD_TO_EN V_CL13_WR_CMD_TO_EN(1U) + +#define S_T7_FUTURE_DEXPANSION_WTE 15 +#define V_T7_FUTURE_DEXPANSION_WTE(x) ((x) << S_T7_FUTURE_DEXPANSION_WTE) +#define F_T7_FUTURE_DEXPANSION_WTE V_T7_FUTURE_DEXPANSION_WTE(1U) + +#define S_CL14_WR_DATA_TO_EN 14 +#define V_CL14_WR_DATA_TO_EN(x) ((x) << S_CL14_WR_DATA_TO_EN) +#define F_CL14_WR_DATA_TO_EN V_CL14_WR_DATA_TO_EN(1U) + +#define S_CL13_WR_DATA_TO_EN 13 +#define V_CL13_WR_DATA_TO_EN(x) ((x) << S_CL13_WR_DATA_TO_EN) +#define F_CL13_WR_DATA_TO_EN V_CL13_WR_DATA_TO_EN(1U) + #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8 #define S_CL12_WR_CMD_TO_ERROR 28 @@ -17031,6 +21825,30 @@ #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS) #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS) +#define S_T7_FUTURE_CEXPANSION_WTS 31 +#define V_T7_FUTURE_CEXPANSION_WTS(x) ((x) << S_T7_FUTURE_CEXPANSION_WTS) +#define F_T7_FUTURE_CEXPANSION_WTS V_T7_FUTURE_CEXPANSION_WTS(1U) + +#define S_CL14_WR_CMD_TO_ERROR 30 +#define V_CL14_WR_CMD_TO_ERROR(x) ((x) << S_CL14_WR_CMD_TO_ERROR) +#define F_CL14_WR_CMD_TO_ERROR V_CL14_WR_CMD_TO_ERROR(1U) + +#define S_CL13_WR_CMD_TO_ERROR 29 +#define V_CL13_WR_CMD_TO_ERROR(x) ((x) << S_CL13_WR_CMD_TO_ERROR) +#define F_CL13_WR_CMD_TO_ERROR V_CL13_WR_CMD_TO_ERROR(1U) + +#define S_T7_FUTURE_DEXPANSION_WTS 15 +#define V_T7_FUTURE_DEXPANSION_WTS(x) ((x) << S_T7_FUTURE_DEXPANSION_WTS) +#define F_T7_FUTURE_DEXPANSION_WTS V_T7_FUTURE_DEXPANSION_WTS(1U) + +#define S_CL14_WR_DATA_TO_ERROR 14 +#define V_CL14_WR_DATA_TO_ERROR(x) ((x) << S_CL14_WR_DATA_TO_ERROR) +#define F_CL14_WR_DATA_TO_ERROR V_CL14_WR_DATA_TO_ERROR(1U) + +#define S_CL13_WR_DATA_TO_ERROR 13 +#define V_CL13_WR_DATA_TO_ERROR(x) ((x) << S_CL13_WR_DATA_TO_ERROR) +#define F_CL13_WR_DATA_TO_ERROR V_CL13_WR_DATA_TO_ERROR(1U) + #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc #define S_CL12_RD_CMD_TO_EN 28 @@ -17147,6 +21965,30 @@ #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE) #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE) +#define S_T7_FUTURE_CEXPANSION_RTE 31 +#define V_T7_FUTURE_CEXPANSION_RTE(x) ((x) << S_T7_FUTURE_CEXPANSION_RTE) +#define F_T7_FUTURE_CEXPANSION_RTE V_T7_FUTURE_CEXPANSION_RTE(1U) + +#define S_CL14_RD_CMD_TO_EN 30 +#define V_CL14_RD_CMD_TO_EN(x) ((x) << S_CL14_RD_CMD_TO_EN) +#define F_CL14_RD_CMD_TO_EN V_CL14_RD_CMD_TO_EN(1U) + +#define S_CL13_RD_CMD_TO_EN 29 +#define V_CL13_RD_CMD_TO_EN(x) ((x) << S_CL13_RD_CMD_TO_EN) +#define F_CL13_RD_CMD_TO_EN V_CL13_RD_CMD_TO_EN(1U) + +#define S_T7_FUTURE_DEXPANSION_RTE 15 +#define V_T7_FUTURE_DEXPANSION_RTE(x) ((x) << S_T7_FUTURE_DEXPANSION_RTE) +#define F_T7_FUTURE_DEXPANSION_RTE V_T7_FUTURE_DEXPANSION_RTE(1U) + +#define S_CL14_RD_DATA_TO_EN 14 +#define V_CL14_RD_DATA_TO_EN(x) ((x) << S_CL14_RD_DATA_TO_EN) +#define F_CL14_RD_DATA_TO_EN V_CL14_RD_DATA_TO_EN(1U) + +#define S_CL13_RD_DATA_TO_EN 13 +#define V_CL13_RD_DATA_TO_EN(x) ((x) << S_CL13_RD_DATA_TO_EN) +#define F_CL13_RD_DATA_TO_EN V_CL13_RD_DATA_TO_EN(1U) + #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0 #define S_CL12_RD_CMD_TO_ERROR 28 @@ -17263,6 +22105,27 @@ #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS) #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS) +#define S_T7_FUTURE_CEXPANSION_RTS 31 +#define V_T7_FUTURE_CEXPANSION_RTS(x) ((x) << S_T7_FUTURE_CEXPANSION_RTS) +#define F_T7_FUTURE_CEXPANSION_RTS V_T7_FUTURE_CEXPANSION_RTS(1U) + +#define S_CL14_RD_CMD_TO_ERROR 30 +#define V_CL14_RD_CMD_TO_ERROR(x) ((x) << S_CL14_RD_CMD_TO_ERROR) +#define F_CL14_RD_CMD_TO_ERROR V_CL14_RD_CMD_TO_ERROR(1U) + +#define S_CL13_RD_CMD_TO_ERROR 29 +#define V_CL13_RD_CMD_TO_ERROR(x) ((x) << S_CL13_RD_CMD_TO_ERROR) +#define F_CL13_RD_CMD_TO_ERROR V_CL13_RD_CMD_TO_ERROR(1U) + +#define S_T7_FUTURE_DEXPANSION_RTS 14 +#define M_T7_FUTURE_DEXPANSION_RTS 0x3U +#define V_T7_FUTURE_DEXPANSION_RTS(x) ((x) << S_T7_FUTURE_DEXPANSION_RTS) +#define G_T7_FUTURE_DEXPANSION_RTS(x) (((x) >> S_T7_FUTURE_DEXPANSION_RTS) & M_T7_FUTURE_DEXPANSION_RTS) + +#define S_CL13_RD_DATA_TO_ERROR 13 +#define V_CL13_RD_DATA_TO_ERROR(x) ((x) << S_CL13_RD_DATA_TO_ERROR) +#define F_CL13_RD_DATA_TO_ERROR V_CL13_RD_DATA_TO_ERROR(1U) + #define A_MA_BKP_CNT_SEL 0x78e4 #define S_BKP_CNT_TYPE 30 @@ -17361,12 +22224,16 @@ #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE) #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE) -#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4 +#define S_T7_FUTURE_DEXPANSION_IPE 14 +#define M_T7_FUTURE_DEXPANSION_IPE 0x3ffffU +#define V_T7_FUTURE_DEXPANSION_IPE(x) ((x) << S_T7_FUTURE_DEXPANSION_IPE) +#define G_T7_FUTURE_DEXPANSION_IPE(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPE) & M_T7_FUTURE_DEXPANSION_IPE) -#define S_T5_FUTURE_DEXPANSION 13 -#define M_T5_FUTURE_DEXPANSION 0x7ffffU -#define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION) -#define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION) +#define S_CL13_IF_PAR_EN 13 +#define V_CL13_IF_PAR_EN(x) ((x) << S_CL13_IF_PAR_EN) +#define F_CL13_IF_PAR_EN V_CL13_IF_PAR_EN(1U) + +#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4 #define S_CL12_IF_PAR_ERROR 12 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR) @@ -17425,6 +22292,15 @@ #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS) #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS) +#define S_T7_FUTURE_DEXPANSION_IPS 14 +#define M_T7_FUTURE_DEXPANSION_IPS 0x3ffffU +#define V_T7_FUTURE_DEXPANSION_IPS(x) ((x) << S_T7_FUTURE_DEXPANSION_IPS) +#define G_T7_FUTURE_DEXPANSION_IPS(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPS) & M_T7_FUTURE_DEXPANSION_IPS) + +#define S_CL13_IF_PAR_ERROR 13 +#define V_CL13_IF_PAR_ERROR(x) ((x) << S_CL13_IF_PAR_ERROR) +#define F_CL13_IF_PAR_ERROR V_CL13_IF_PAR_ERROR(1U) + #define A_MA_LOCAL_DEBUG_CFG 0x78f8 #define S_DEBUG_OR 15 @@ -17445,6 +22321,131 @@ #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE) #define A_MA_LOCAL_DEBUG_RPT 0x78fc +#define A_MA_CLIENT13_PR_THRESHOLD 0x7900 +#define A_MA_CLIENT13_CR_THRESHOLD 0x7904 +#define A_MA_CRYPTO_DEBUG_CNT 0x7908 +#define A_MA_CRYPTO_WRDATA_CNT 0x790c +#define A_MA_CRYPTO_RDDATA_CNT 0x7910 +#define A_MA_LOCAL_DEBUG_PERF_CFG 0x7914 +#define A_MA_LOCAL_DEBUG_PERF_RPT 0x7918 +#define A_MA_PCIE_THROTTLE 0x791c +#define A_MA_CLIENT14_PR_THRESHOLD 0x7920 +#define A_MA_CLIENT14_CR_THRESHOLD 0x7924 +#define A_MA_CIM_TH1_DEBUG_CNT 0x7928 +#define A_MA_CIM_TH1_WRDATA_CNT 0x792c +#define A_MA_CIM_TH1_RDDATA_CNT 0x7930 +#define A_MA_CIM_THREAD1_MAPPER 0x7934 + +#define S_CIM_THREAD1_EN 0 +#define M_CIM_THREAD1_EN 0xffU +#define V_CIM_THREAD1_EN(x) ((x) << S_CIM_THREAD1_EN) +#define G_CIM_THREAD1_EN(x) (((x) >> S_CIM_THREAD1_EN) & M_CIM_THREAD1_EN) + +#define A_MA_PIO_CI_SGE_TH0_BASE 0x7938 + +#define S_SGE_TH0_BASE 0 +#define M_SGE_TH0_BASE 0xffffU +#define V_SGE_TH0_BASE(x) ((x) << S_SGE_TH0_BASE) +#define G_SGE_TH0_BASE(x) (((x) >> S_SGE_TH0_BASE) & M_SGE_TH0_BASE) + +#define A_MA_PIO_CI_SGE_TH1_BASE 0x793c + +#define S_SGE_TH1_BASE 0 +#define M_SGE_TH1_BASE 0xffffU +#define V_SGE_TH1_BASE(x) ((x) << S_SGE_TH1_BASE) +#define G_SGE_TH1_BASE(x) (((x) >> S_SGE_TH1_BASE) & M_SGE_TH1_BASE) + +#define A_MA_PIO_CI_ULPTX_BASE 0x7940 + +#define S_ULPTX_BASE 0 +#define M_ULPTX_BASE 0xffffU +#define V_ULPTX_BASE(x) ((x) << S_ULPTX_BASE) +#define G_ULPTX_BASE(x) (((x) >> S_ULPTX_BASE) & M_ULPTX_BASE) + +#define A_MA_PIO_CI_ULPRX_BASE 0x7944 + +#define S_ULPRX_BASE 0 +#define M_ULPRX_BASE 0xffffU +#define V_ULPRX_BASE(x) ((x) << S_ULPRX_BASE) +#define G_ULPRX_BASE(x) (((x) >> S_ULPRX_BASE) & M_ULPRX_BASE) + +#define A_MA_PIO_CI_ULPTXRX_BASE 0x7948 + +#define S_ULPTXRX_BASE 0 +#define M_ULPTXRX_BASE 0xffffU +#define V_ULPTXRX_BASE(x) ((x) << S_ULPTXRX_BASE) +#define G_ULPTXRX_BASE(x) (((x) >> S_ULPTXRX_BASE) & M_ULPTXRX_BASE) + +#define A_MA_PIO_CI_TP_TH0_BASE 0x794c + +#define S_TP_TH0_BASE 0 +#define M_TP_TH0_BASE 0xffffU +#define V_TP_TH0_BASE(x) ((x) << S_TP_TH0_BASE) +#define G_TP_TH0_BASE(x) (((x) >> S_TP_TH0_BASE) & M_TP_TH0_BASE) + +#define A_MA_PIO_CI_TP_TH1_BASE 0x7950 + +#define S_TP_TH1_BASE 0 +#define M_TP_TH1_BASE 0xffffU +#define V_TP_TH1_BASE(x) ((x) << S_TP_TH1_BASE) +#define G_TP_TH1_BASE(x) (((x) >> S_TP_TH1_BASE) & M_TP_TH1_BASE) + +#define A_MA_PIO_CI_LE_BASE 0x7954 + +#define S_LE_BASE 0 +#define M_LE_BASE 0xffffU +#define V_LE_BASE(x) ((x) << S_LE_BASE) +#define G_LE_BASE(x) (((x) >> S_LE_BASE) & M_LE_BASE) + +#define A_MA_PIO_CI_CIM_TH0_BASE 0x7958 + +#define S_CIM_TH0_BASE 0 +#define M_CIM_TH0_BASE 0xffffU +#define V_CIM_TH0_BASE(x) ((x) << S_CIM_TH0_BASE) +#define G_CIM_TH0_BASE(x) (((x) >> S_CIM_TH0_BASE) & M_CIM_TH0_BASE) + +#define A_MA_PIO_CI_PCIE_BASE 0x795c + +#define S_PCIE_BASE 0 +#define M_PCIE_BASE 0xffffU +#define V_PCIE_BASE(x) ((x) << S_PCIE_BASE) +#define G_PCIE_BASE(x) (((x) >> S_PCIE_BASE) & M_PCIE_BASE) + +#define A_MA_PIO_CI_PMTX_BASE 0x7960 + +#define S_PMTX_BASE 0 +#define M_PMTX_BASE 0xffffU +#define V_PMTX_BASE(x) ((x) << S_PMTX_BASE) +#define G_PMTX_BASE(x) (((x) >> S_PMTX_BASE) & M_PMTX_BASE) + +#define A_MA_PIO_CI_PMRX_BASE 0x7964 + +#define S_PMRX_BASE 0 +#define M_PMRX_BASE 0xffffU +#define V_PMRX_BASE(x) ((x) << S_PMRX_BASE) +#define G_PMRX_BASE(x) (((x) >> S_PMRX_BASE) & M_PMRX_BASE) + +#define A_MA_PIO_CI_HMA_BASE 0x7968 + +#define S_HMACLIENTBASE 0 +#define M_HMACLIENTBASE 0xffffU +#define V_HMACLIENTBASE(x) ((x) << S_HMACLIENTBASE) +#define G_HMACLIENTBASE(x) (((x) >> S_HMACLIENTBASE) & M_HMACLIENTBASE) + +#define A_MA_PIO_CI_CRYPTO_BASE 0x796c + +#define S_CRYPTO_BASE 0 +#define M_CRYPTO_BASE 0xffffU +#define V_CRYPTO_BASE(x) ((x) << S_CRYPTO_BASE) +#define G_CRYPTO_BASE(x) (((x) >> S_CRYPTO_BASE) & M_CRYPTO_BASE) + +#define A_MA_PIO_CI_CIM_TH1_BASE 0x7970 + +#define S_CIM_TH1_BASE 0 +#define M_CIM_TH1_BASE 0xffffU +#define V_CIM_TH1_BASE(x) ((x) << S_CIM_TH1_BASE) +#define G_CIM_TH1_BASE(x) (((x) >> S_CIM_TH1_BASE) & M_CIM_TH1_BASE) + #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000 #define S_CMDVLD0 31 @@ -20418,6 +25419,124 @@ #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE) #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE) +#define A_T7_CIM_PERR_ENABLE 0x7b08 + +#define S_T7_MA_CIM_INTFPERR 31 +#define V_T7_MA_CIM_INTFPERR(x) ((x) << S_T7_MA_CIM_INTFPERR) +#define F_T7_MA_CIM_INTFPERR V_T7_MA_CIM_INTFPERR(1U) + +#define S_T7_MBHOSTPARERR 30 +#define V_T7_MBHOSTPARERR(x) ((x) << S_T7_MBHOSTPARERR) +#define F_T7_MBHOSTPARERR V_T7_MBHOSTPARERR(1U) + +#define S_MAARBINVRSPTAG 29 +#define V_MAARBINVRSPTAG(x) ((x) << S_MAARBINVRSPTAG) +#define F_MAARBINVRSPTAG V_MAARBINVRSPTAG(1U) + +#define S_MAARBFIFOPARERR 28 +#define V_MAARBFIFOPARERR(x) ((x) << S_MAARBFIFOPARERR) +#define F_MAARBFIFOPARERR V_MAARBFIFOPARERR(1U) + +#define S_SEMSRAMPARERR 27 +#define V_SEMSRAMPARERR(x) ((x) << S_SEMSRAMPARERR) +#define F_SEMSRAMPARERR V_SEMSRAMPARERR(1U) + +#define S_RSACPARERR 26 +#define V_RSACPARERR(x) ((x) << S_RSACPARERR) +#define F_RSACPARERR V_RSACPARERR(1U) + +#define S_RSADPARERR 25 +#define V_RSADPARERR(x) ((x) << S_RSADPARERR) +#define F_RSADPARERR V_RSADPARERR(1U) + +#define S_T7_PLCIM_MSTRSPDATAPARERR 24 +#define V_T7_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_T7_PLCIM_MSTRSPDATAPARERR) +#define F_T7_PLCIM_MSTRSPDATAPARERR V_T7_PLCIM_MSTRSPDATAPARERR(1U) + +#define S_T7_PCIE2CIMINTFPARERR 23 +#define V_T7_PCIE2CIMINTFPARERR(x) ((x) << S_T7_PCIE2CIMINTFPARERR) +#define F_T7_PCIE2CIMINTFPARERR V_T7_PCIE2CIMINTFPARERR(1U) + +#define S_T7_NCSI2CIMINTFPARERR 22 +#define V_T7_NCSI2CIMINTFPARERR(x) ((x) << S_T7_NCSI2CIMINTFPARERR) +#define F_T7_NCSI2CIMINTFPARERR V_T7_NCSI2CIMINTFPARERR(1U) + +#define S_T7_SGE2CIMINTFPARERR 21 +#define V_T7_SGE2CIMINTFPARERR(x) ((x) << S_T7_SGE2CIMINTFPARERR) +#define F_T7_SGE2CIMINTFPARERR V_T7_SGE2CIMINTFPARERR(1U) + +#define S_T7_ULP2CIMINTFPARERR 20 +#define V_T7_ULP2CIMINTFPARERR(x) ((x) << S_T7_ULP2CIMINTFPARERR) +#define F_T7_ULP2CIMINTFPARERR V_T7_ULP2CIMINTFPARERR(1U) + +#define S_T7_TP2CIMINTFPARERR 19 +#define V_T7_TP2CIMINTFPARERR(x) ((x) << S_T7_TP2CIMINTFPARERR) +#define F_T7_TP2CIMINTFPARERR V_T7_TP2CIMINTFPARERR(1U) + +#define S_CORE7PARERR 18 +#define V_CORE7PARERR(x) ((x) << S_CORE7PARERR) +#define F_CORE7PARERR V_CORE7PARERR(1U) + +#define S_CORE6PARERR 17 +#define V_CORE6PARERR(x) ((x) << S_CORE6PARERR) +#define F_CORE6PARERR V_CORE6PARERR(1U) + +#define S_CORE5PARERR 16 +#define V_CORE5PARERR(x) ((x) << S_CORE5PARERR) +#define F_CORE5PARERR V_CORE5PARERR(1U) + +#define S_CORE4PARERR 15 +#define V_CORE4PARERR(x) ((x) << S_CORE4PARERR) +#define F_CORE4PARERR V_CORE4PARERR(1U) + +#define S_CORE3PARERR 14 +#define V_CORE3PARERR(x) ((x) << S_CORE3PARERR) +#define F_CORE3PARERR V_CORE3PARERR(1U) + +#define S_CORE2PARERR 13 +#define V_CORE2PARERR(x) ((x) << S_CORE2PARERR) +#define F_CORE2PARERR V_CORE2PARERR(1U) + +#define S_CORE1PARERR 12 +#define V_CORE1PARERR(x) ((x) << S_CORE1PARERR) +#define F_CORE1PARERR V_CORE1PARERR(1U) + +#define S_GFTPARERR 10 +#define V_GFTPARERR(x) ((x) << S_GFTPARERR) +#define F_GFTPARERR V_GFTPARERR(1U) + +#define S_MPSRSPDATAPARERR 9 +#define V_MPSRSPDATAPARERR(x) ((x) << S_MPSRSPDATAPARERR) +#define F_MPSRSPDATAPARERR V_MPSRSPDATAPARERR(1U) + +#define S_ER_RSPDATAPARERR 8 +#define V_ER_RSPDATAPARERR(x) ((x) << S_ER_RSPDATAPARERR) +#define F_ER_RSPDATAPARERR V_ER_RSPDATAPARERR(1U) + +#define S_FLOWFIFOPARERR 7 +#define V_FLOWFIFOPARERR(x) ((x) << S_FLOWFIFOPARERR) +#define F_FLOWFIFOPARERR V_FLOWFIFOPARERR(1U) + +#define S_OBQSRAMPARERR 6 +#define V_OBQSRAMPARERR(x) ((x) << S_OBQSRAMPARERR) +#define F_OBQSRAMPARERR V_OBQSRAMPARERR(1U) + +#define S_TIEQOUTPARERR 3 +#define V_TIEQOUTPARERR(x) ((x) << S_TIEQOUTPARERR) +#define F_TIEQOUTPARERR V_TIEQOUTPARERR(1U) + +#define S_TIEQINPARERR 2 +#define V_TIEQINPARERR(x) ((x) << S_TIEQINPARERR) +#define F_TIEQINPARERR V_TIEQINPARERR(1U) + +#define S_PIFRSPPARERR 1 +#define V_PIFRSPPARERR(x) ((x) << S_PIFRSPPARERR) +#define F_PIFRSPPARERR V_PIFRSPPARERR(1U) + +#define S_PIFREQPARERR 0 +#define V_PIFREQPARERR(x) ((x) << S_PIFREQPARERR) +#define F_PIFREQPARERR V_PIFREQPARERR(1U) + #define A_CIM_EEPROM_BASE_ADDR 0x7b0c #define S_EEPROMBASEADDR 6 @@ -20425,6 +25544,7 @@ #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR) #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR) +#define A_CIM_PERR_CAUSE 0x7b0c #define A_CIM_EEPROM_ADDR_SIZE 0x7b10 #define S_EEPROMADDRSIZE 4 @@ -20593,6 +25713,38 @@ #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR) #define F_IBQPCIEPARERR V_IBQPCIEPARERR(1U) +#define S_CORE7ACCINT 22 +#define V_CORE7ACCINT(x) ((x) << S_CORE7ACCINT) +#define F_CORE7ACCINT V_CORE7ACCINT(1U) + +#define S_CORE6ACCINT 21 +#define V_CORE6ACCINT(x) ((x) << S_CORE6ACCINT) +#define F_CORE6ACCINT V_CORE6ACCINT(1U) + +#define S_CORE5ACCINT 20 +#define V_CORE5ACCINT(x) ((x) << S_CORE5ACCINT) +#define F_CORE5ACCINT V_CORE5ACCINT(1U) + +#define S_CORE4ACCINT 19 +#define V_CORE4ACCINT(x) ((x) << S_CORE4ACCINT) +#define F_CORE4ACCINT V_CORE4ACCINT(1U) + +#define S_CORE3ACCINT 18 +#define V_CORE3ACCINT(x) ((x) << S_CORE3ACCINT) +#define F_CORE3ACCINT V_CORE3ACCINT(1U) + +#define S_CORE2ACCINT 17 +#define V_CORE2ACCINT(x) ((x) << S_CORE2ACCINT) +#define F_CORE2ACCINT V_CORE2ACCINT(1U) + +#define S_CORE1ACCINT 16 +#define V_CORE1ACCINT(x) ((x) << S_CORE1ACCINT) +#define F_CORE1ACCINT V_CORE1ACCINT(1U) + +#define S_PERRNONZERO 1 +#define V_PERRNONZERO(x) ((x) << S_PERRNONZERO) +#define F_PERRNONZERO V_PERRNONZERO(1U) + #define A_CIM_HOST_INT_CAUSE 0x7b2c #define S_TIEQOUTPARERRINT 20 @@ -20745,6 +25897,10 @@ #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN) #define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U) +#define S_CONWRERRINTEN 31 +#define V_CONWRERRINTEN(x) ((x) << S_CONWRERRINTEN) +#define F_CONWRERRINTEN V_CONWRERRINTEN(1U) + #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34 #define S_EEPROMWRINT 30 @@ -20871,12 +26027,32 @@ #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) #define F_RSVDSPACEINT V_RSVDSPACEINT(1U) +#define S_CONWRERRINT 31 +#define V_CONWRERRINT(x) ((x) << S_CONWRERRINT) +#define F_CONWRERRINT V_CONWRERRINT(1U) + #define A_CIM_UP_INT_ENABLE 0x7b38 #define S_MSTPLINTEN 4 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN) #define F_MSTPLINTEN V_MSTPLINTEN(1U) +#define S_SEMINT 8 +#define V_SEMINT(x) ((x) << S_SEMINT) +#define F_SEMINT V_SEMINT(1U) + +#define S_RSAINT 7 +#define V_RSAINT(x) ((x) << S_RSAINT) +#define F_RSAINT V_RSAINT(1U) + +#define S_TRNGINT 6 +#define V_TRNGINT(x) ((x) << S_TRNGINT) +#define F_TRNGINT V_TRNGINT(1U) + +#define S_PEERHALTINT 5 +#define V_PEERHALTINT(x) ((x) << S_PEERHALTINT) +#define F_PEERHALTINT V_PEERHALTINT(1U) + #define A_CIM_UP_INT_CAUSE 0x7b3c #define S_MSTPLINT 4 @@ -20900,6 +26076,33 @@ #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT) #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT) +#define S_MAPOFFSET 11 +#define M_MAPOFFSET 0x1fU +#define V_MAPOFFSET(x) ((x) << S_MAPOFFSET) +#define G_MAPOFFSET(x) (((x) >> S_MAPOFFSET) & M_MAPOFFSET) + +#define S_MAPSELECT 10 +#define V_MAPSELECT(x) ((x) << S_MAPSELECT) +#define F_MAPSELECT V_MAPSELECT(1U) + +#define S_CORESELECT 6 +#define M_CORESELECT 0xfU +#define V_CORESELECT(x) ((x) << S_CORESELECT) +#define G_CORESELECT(x) (((x) >> S_CORESELECT) & M_CORESELECT) + +#define S_T7_OBQSELECT 5 +#define V_T7_OBQSELECT(x) ((x) << S_T7_OBQSELECT) +#define F_T7_OBQSELECT V_T7_OBQSELECT(1U) + +#define S_T7_IBQSELECT 4 +#define V_T7_IBQSELECT(x) ((x) << S_T7_IBQSELECT) +#define F_T7_IBQSELECT V_T7_IBQSELECT(1U) + +#define S_T7_QUENUMSELECT 0 +#define M_T7_QUENUMSELECT 0xfU +#define V_T7_QUENUMSELECT(x) ((x) << S_T7_QUENUMSELECT) +#define G_T7_QUENUMSELECT(x) (((x) >> S_T7_QUENUMSELECT) & M_T7_QUENUMSELECT) + #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c #define S_CIMQSIZE 24 @@ -20940,6 +26143,29 @@ #define V_HOSTADDR(x) ((x) << S_HOSTADDR) #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR) +#define S_T7_HOSTBUSY 31 +#define V_T7_HOSTBUSY(x) ((x) << S_T7_HOSTBUSY) +#define F_T7_HOSTBUSY V_T7_HOSTBUSY(1U) + +#define S_T7_HOSTWRITE 30 +#define V_T7_HOSTWRITE(x) ((x) << S_T7_HOSTWRITE) +#define F_T7_HOSTWRITE V_T7_HOSTWRITE(1U) + +#define S_HOSTGRPSEL 28 +#define M_HOSTGRPSEL 0x3U +#define V_HOSTGRPSEL(x) ((x) << S_HOSTGRPSEL) +#define G_HOSTGRPSEL(x) (((x) >> S_HOSTGRPSEL) & M_HOSTGRPSEL) + +#define S_HOSTCORESEL 24 +#define M_HOSTCORESEL 0xfU +#define V_HOSTCORESEL(x) ((x) << S_HOSTCORESEL) +#define G_HOSTCORESEL(x) (((x) >> S_HOSTCORESEL) & M_HOSTCORESEL) + +#define S_T7_HOSTADDR 0 +#define M_T7_HOSTADDR 0xffffffU +#define V_T7_HOSTADDR(x) ((x) << S_T7_HOSTADDR) +#define G_T7_HOSTADDR(x) (((x) >> S_T7_HOSTADDR) & M_T7_HOSTADDR) + #define A_CIM_HOST_ACC_DATA 0x7b54 #define A_CIM_CDEBUGDATA 0x7b58 @@ -20953,6 +26179,31 @@ #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL) #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL) +#define A_CIM_DEBUG_CFG 0x7b58 + +#define S_OR_EN 20 +#define V_OR_EN(x) ((x) << S_OR_EN) +#define F_OR_EN V_OR_EN(1U) + +#define S_USEL 19 +#define V_USEL(x) ((x) << S_USEL) +#define F_USEL V_USEL(1U) + +#define S_HI 18 +#define V_HI(x) ((x) << S_HI) +#define F_HI V_HI(1U) + +#define S_SELH 9 +#define M_SELH 0x1ffU +#define V_SELH(x) ((x) << S_SELH) +#define G_SELH(x) (((x) >> S_SELH) & M_SELH) + +#define S_SELL 0 +#define M_SELL 0x1ffU +#define V_SELL(x) ((x) << S_SELL) +#define G_SELL(x) (((x) >> S_SELL) & M_SELL) + +#define A_CIM_DEBUG_DATA 0x7b5c #define A_CIM_IBQ_DBG_CFG 0x7b60 #define S_IBQDBGADDR 16 @@ -20972,6 +26223,25 @@ #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) #define F_IBQDBGEN V_IBQDBGEN(1U) +#define S_IBQDBGCORE 28 +#define M_IBQDBGCORE 0xfU +#define V_IBQDBGCORE(x) ((x) << S_IBQDBGCORE) +#define G_IBQDBGCORE(x) (((x) >> S_IBQDBGCORE) & M_IBQDBGCORE) + +#define S_T7_IBQDBGADDR 12 +#define M_T7_IBQDBGADDR 0x1fffU +#define V_T7_IBQDBGADDR(x) ((x) << S_T7_IBQDBGADDR) +#define G_T7_IBQDBGADDR(x) (((x) >> S_T7_IBQDBGADDR) & M_T7_IBQDBGADDR) + +#define S_IBQDBGSTATE 4 +#define M_IBQDBGSTATE 0x3U +#define V_IBQDBGSTATE(x) ((x) << S_IBQDBGSTATE) +#define G_IBQDBGSTATE(x) (((x) >> S_IBQDBGSTATE) & M_IBQDBGSTATE) + +#define S_PERRADDRCLR 3 +#define V_PERRADDRCLR(x) ((x) << S_PERRADDRCLR) +#define F_PERRADDRCLR V_PERRADDRCLR(1U) + #define A_CIM_OBQ_DBG_CFG 0x7b64 #define S_OBQDBGADDR 16 @@ -20991,6 +26261,21 @@ #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN) #define F_OBQDBGEN V_OBQDBGEN(1U) +#define S_OBQDBGCORE 28 +#define M_OBQDBGCORE 0xfU +#define V_OBQDBGCORE(x) ((x) << S_OBQDBGCORE) +#define G_OBQDBGCORE(x) (((x) >> S_OBQDBGCORE) & M_OBQDBGCORE) + +#define S_T7_OBQDBGADDR 12 +#define M_T7_OBQDBGADDR 0x1fffU +#define V_T7_OBQDBGADDR(x) ((x) << S_T7_OBQDBGADDR) +#define G_T7_OBQDBGADDR(x) (((x) >> S_T7_OBQDBGADDR) & M_T7_OBQDBGADDR) + +#define S_OBQDBGSTATE 4 +#define M_OBQDBGSTATE 0x3U +#define V_OBQDBGSTATE(x) ((x) << S_OBQDBGSTATE) +#define G_OBQDBGSTATE(x) (((x) >> S_OBQDBGSTATE) & M_OBQDBGSTATE) + #define A_CIM_IBQ_DBG_DATA 0x7b68 #define A_CIM_OBQ_DBG_DATA 0x7b6c #define A_CIM_DEBUGCFG 0x7b70 @@ -21075,6 +26360,11 @@ #define V_ZONE_DST(x) ((x) << S_ZONE_DST) #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST) +#define S_THREAD_ID 2 +#define M_THREAD_ID 0x7U +#define V_THREAD_ID(x) ((x) << S_THREAD_ID) +#define G_THREAD_ID(x) (((x) >> S_THREAD_ID) & M_THREAD_ID) + #define A_CIM_MEM_ZONE0_LEN 0x7b98 #define S_MEM_ZONE_LEN 4 @@ -21207,6 +26497,7 @@ #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK) #define A_CIM_PERR_INJECT 0x7c20 +#define A_CIM_FPGA_ROM_EFUSE_CMD 0x7c20 #define A_CIM_PERR_ENABLE 0x7c24 #define S_PERREN 0 @@ -21224,6 +26515,7 @@ #define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN) #define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN) +#define A_CIM_FPGA_ROM_EFUSE_DATA 0x7c24 #define A_CIM_EEPROM_BUSY_BIT 0x7c28 #define S_EEPROMBUSY 0 @@ -21240,6 +26532,22 @@ #define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE) #define F_SLOW_TIMER_ENABLE V_SLOW_TIMER_ENABLE(1U) +#define S_FLASHWRPAGEMORE 5 +#define V_FLASHWRPAGEMORE(x) ((x) << S_FLASHWRPAGEMORE) +#define F_FLASHWRPAGEMORE V_FLASHWRPAGEMORE(1U) + +#define S_FLASHWRENABLE 4 +#define V_FLASHWRENABLE(x) ((x) << S_FLASHWRENABLE) +#define F_FLASHWRENABLE V_FLASHWRENABLE(1U) + +#define S_FLASHMOREENABLE 3 +#define V_FLASHMOREENABLE(x) ((x) << S_FLASHMOREENABLE) +#define F_FLASHMOREENABLE V_FLASHMOREENABLE(1U) + +#define S_WR_RESP_ENABLE 2 +#define V_WR_RESP_ENABLE(x) ((x) << S_WR_RESP_ENABLE) +#define F_WR_RESP_ENABLE V_WR_RESP_ENABLE(1U) + #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30 #define S_UP_PO_SINGLE_OUTSTANDING 0 @@ -21271,6 +26579,18 @@ #define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE) #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40 +#define A_CIM_QUE_PERR_ADDR 0x7c40 + +#define S_IBQPERRADDR 16 +#define M_IBQPERRADDR 0xfffU +#define V_IBQPERRADDR(x) ((x) << S_IBQPERRADDR) +#define G_IBQPERRADDR(x) (((x) >> S_IBQPERRADDR) & M_IBQPERRADDR) + +#define S_OBQPERRADDR 0 +#define M_OBQPERRADDR 0xfffU +#define V_OBQPERRADDR(x) ((x) << S_OBQPERRADDR) +#define G_OBQPERRADDR(x) (((x) >> S_OBQPERRADDR) & M_OBQPERRADDR) + #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44 #define S_PIO_UP_MST_CFG_SEL 0 @@ -21309,6 +26629,20 @@ #define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE) #define F_PCIE_OBQ_IF_DISABLE V_PCIE_OBQ_IF_DISABLE(1U) +#define S_ULP_OBQ_SIZE 8 +#define M_ULP_OBQ_SIZE 0x3U +#define V_ULP_OBQ_SIZE(x) ((x) << S_ULP_OBQ_SIZE) +#define G_ULP_OBQ_SIZE(x) (((x) >> S_ULP_OBQ_SIZE) & M_ULP_OBQ_SIZE) + +#define S_TP_IBQ_SIZE 6 +#define M_TP_IBQ_SIZE 0x3U +#define V_TP_IBQ_SIZE(x) ((x) << S_TP_IBQ_SIZE) +#define G_TP_IBQ_SIZE(x) (((x) >> S_TP_IBQ_SIZE) & M_TP_IBQ_SIZE) + +#define S_OBQ_EOM_ENABLE 5 +#define V_OBQ_EOM_ENABLE(x) ((x) << S_OBQ_EOM_ENABLE) +#define F_OBQ_EOM_ENABLE V_OBQ_EOM_ENABLE(1U) + #define A_CIM_CGEN_GLOBAL 0x7c50 #define S_CGEN_GLOBAL 0 @@ -21321,6 +26655,77 @@ #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN) #define F_PIFDBGLA_DPSLP_EN V_PIFDBGLA_DPSLP_EN(1U) +#define A_CIM_GFT_CMM_CONFIG 0x7c58 + +#define S_GLFL 31 +#define V_GLFL(x) ((x) << S_GLFL) +#define F_GLFL V_GLFL(1U) + +#define S_T7_WRCNTIDLE 16 +#define M_T7_WRCNTIDLE 0x7fffU +#define V_T7_WRCNTIDLE(x) ((x) << S_T7_WRCNTIDLE) +#define G_T7_WRCNTIDLE(x) (((x) >> S_T7_WRCNTIDLE) & M_T7_WRCNTIDLE) + +#define A_CIM_GFT_CONFIG 0x7c5c + +#define S_GFTMABASE 16 +#define M_GFTMABASE 0xffffU +#define V_GFTMABASE(x) ((x) << S_GFTMABASE) +#define G_GFTMABASE(x) (((x) >> S_GFTMABASE) & M_GFTMABASE) + +#define S_GFTHASHTBLSIZE 12 +#define M_GFTHASHTBLSIZE 0xfU +#define V_GFTHASHTBLSIZE(x) ((x) << S_GFTHASHTBLSIZE) +#define G_GFTHASHTBLSIZE(x) (((x) >> S_GFTHASHTBLSIZE) & M_GFTHASHTBLSIZE) + +#define S_GFTTCAMPRIORITY 11 +#define V_GFTTCAMPRIORITY(x) ((x) << S_GFTTCAMPRIORITY) +#define F_GFTTCAMPRIORITY V_GFTTCAMPRIORITY(1U) + +#define S_GFTMATHREADID 8 +#define M_GFTMATHREADID 0x7U +#define V_GFTMATHREADID(x) ((x) << S_GFTMATHREADID) +#define G_GFTMATHREADID(x) (((x) >> S_GFTMATHREADID) & M_GFTMATHREADID) + +#define S_GFTTCAMINIT 7 +#define V_GFTTCAMINIT(x) ((x) << S_GFTTCAMINIT) +#define F_GFTTCAMINIT V_GFTTCAMINIT(1U) + +#define S_GFTTCAMINITDONE 6 +#define V_GFTTCAMINITDONE(x) ((x) << S_GFTTCAMINITDONE) +#define F_GFTTCAMINITDONE V_GFTTCAMINITDONE(1U) + +#define S_GFTTBLMODEEN 0 +#define V_GFTTBLMODEEN(x) ((x) << S_GFTTBLMODEEN) +#define F_GFTTBLMODEEN V_GFTTBLMODEEN(1U) + +#define A_CIM_TCAM_BIST_CTRL 0x7c60 + +#define S_RST_CB 31 +#define V_RST_CB(x) ((x) << S_RST_CB) +#define F_RST_CB V_RST_CB(1U) + +#define S_CB_START 0 +#define M_CB_START 0xfffffffU +#define V_CB_START(x) ((x) << S_CB_START) +#define G_CB_START(x) (((x) >> S_CB_START) & M_CB_START) + +#define A_CIM_TCAM_BIST_CB_PASS 0x7c64 + +#define S_CB_PASS 0 +#define M_CB_PASS 0xfffffffU +#define V_CB_PASS(x) ((x) << S_CB_PASS) +#define G_CB_PASS(x) (((x) >> S_CB_PASS) & M_CB_PASS) + +#define A_CIM_TCAM_BIST_CB_BUSY 0x7c68 + +#define S_CB_BUSY 0 +#define M_CB_BUSY 0xfffffffU +#define V_CB_BUSY(x) ((x) << S_CB_BUSY) +#define G_CB_BUSY(x) (((x) >> S_CB_BUSY) & M_CB_BUSY) + +#define A_CIM_GFT_MASK 0x7c70 + /* registers for module TP */ #define TP_BASE_ADDR 0x7d00 @@ -21613,6 +27018,14 @@ #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT) #define F_CRXPKTXT V_CRXPKTXT(1U) +#define S_ETOEBYPCSUMNOWAIT 15 +#define V_ETOEBYPCSUMNOWAIT(x) ((x) << S_ETOEBYPCSUMNOWAIT) +#define F_ETOEBYPCSUMNOWAIT V_ETOEBYPCSUMNOWAIT(1U) + +#define S_ENICCSUMNOWAIT 14 +#define V_ENICCSUMNOWAIT(x) ((x) << S_ENICCSUMNOWAIT) +#define F_ENICCSUMNOWAIT V_ENICCSUMNOWAIT(1U) + #define A_TP_GLOBAL_CONFIG 0x7d08 #define S_SYNCOOKIEPARAMS 26 @@ -21703,6 +27116,31 @@ #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS) #define F_ACTIVEFILTERCOUNTS V_ACTIVEFILTERCOUNTS(1U) +#define S_RXSACKPARSE 31 +#define V_RXSACKPARSE(x) ((x) << S_RXSACKPARSE) +#define F_RXSACKPARSE V_RXSACKPARSE(1U) + +#define S_RXSACKFWDMODE 29 +#define M_RXSACKFWDMODE 0x3U +#define V_RXSACKFWDMODE(x) ((x) << S_RXSACKFWDMODE) +#define G_RXSACKFWDMODE(x) (((x) >> S_RXSACKFWDMODE) & M_RXSACKFWDMODE) + +#define S_SRVRCHRSSEN 26 +#define V_SRVRCHRSSEN(x) ((x) << S_SRVRCHRSSEN) +#define F_SRVRCHRSSEN V_SRVRCHRSSEN(1U) + +#define S_LBCHNDISTEN 23 +#define V_LBCHNDISTEN(x) ((x) << S_LBCHNDISTEN) +#define F_LBCHNDISTEN V_LBCHNDISTEN(1U) + +#define S_ETHTNLLEN2X 20 +#define V_ETHTNLLEN2X(x) ((x) << S_ETHTNLLEN2X) +#define F_ETHTNLLEN2X V_ETHTNLLEN2X(1U) + +#define S_EGLBCHNDISTEN 19 +#define V_EGLBCHNDISTEN(x) ((x) << S_EGLBCHNDISTEN) +#define F_EGLBCHNDISTEN V_EGLBCHNDISTEN(1U) + #define A_TP_DB_CONFIG 0x7d0c #define S_DBMAXOPCNT 24 @@ -21767,6 +27205,11 @@ #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE) #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE) +#define S_T7_PMRXNUMCHN 29 +#define M_T7_PMRXNUMCHN 0x7U +#define V_T7_PMRXNUMCHN(x) ((x) << S_T7_PMRXNUMCHN) +#define G_T7_PMRXNUMCHN(x) (((x) >> S_T7_PMRXNUMCHN) & M_T7_PMRXNUMCHN) + #define A_TP_PMM_TX_PAGE_SIZE 0x7d34 #define A_TP_PMM_TX_MAX_PAGE 0x7d38 @@ -21780,6 +27223,83 @@ #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE) #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE) +#define S_T7_PMTXNUMCHN 29 +#define M_T7_PMTXNUMCHN 0x7U +#define V_T7_PMTXNUMCHN(x) ((x) << S_T7_PMTXNUMCHN) +#define G_T7_PMTXNUMCHN(x) (((x) >> S_T7_PMTXNUMCHN) & M_T7_PMTXNUMCHN) + +#define A_TP_EXT_CONFIG 0x7d3c + +#define S_TNLERRORIPSECARW 29 +#define V_TNLERRORIPSECARW(x) ((x) << S_TNLERRORIPSECARW) +#define F_TNLERRORIPSECARW V_TNLERRORIPSECARW(1U) + +#define S_TNLERRORIPSECICV 28 +#define V_TNLERRORIPSECICV(x) ((x) << S_TNLERRORIPSECICV) +#define F_TNLERRORIPSECICV V_TNLERRORIPSECICV(1U) + +#define S_DROPERRORIPSECARW 25 +#define V_DROPERRORIPSECARW(x) ((x) << S_DROPERRORIPSECARW) +#define F_DROPERRORIPSECARW V_DROPERRORIPSECARW(1U) + +#define S_DROPERRORIPSECICV 24 +#define V_DROPERRORIPSECICV(x) ((x) << S_DROPERRORIPSECICV) +#define F_DROPERRORIPSECICV V_DROPERRORIPSECICV(1U) + +#define S_MIBRDMAROCEEN 19 +#define V_MIBRDMAROCEEN(x) ((x) << S_MIBRDMAROCEEN) +#define F_MIBRDMAROCEEN V_MIBRDMAROCEEN(1U) + +#define S_MIBRDMAIWARPEN 18 +#define V_MIBRDMAIWARPEN(x) ((x) << S_MIBRDMAIWARPEN) +#define F_MIBRDMAIWARPEN V_MIBRDMAIWARPEN(1U) + +#define S_BYPTXDATAACKALLEN 17 +#define V_BYPTXDATAACKALLEN(x) ((x) << S_BYPTXDATAACKALLEN) +#define F_BYPTXDATAACKALLEN V_BYPTXDATAACKALLEN(1U) + +#define S_DATAACKEXTEN 16 +#define V_DATAACKEXTEN(x) ((x) << S_DATAACKEXTEN) +#define F_DATAACKEXTEN V_DATAACKEXTEN(1U) + +#define S_MACMATCH11FWD 11 +#define V_MACMATCH11FWD(x) ((x) << S_MACMATCH11FWD) +#define F_MACMATCH11FWD V_MACMATCH11FWD(1U) + +#define S_USERTMSTPEN 10 +#define V_USERTMSTPEN(x) ((x) << S_USERTMSTPEN) +#define F_USERTMSTPEN V_USERTMSTPEN(1U) + +#define S_MMGRCACHEDIS 9 +#define V_MMGRCACHEDIS(x) ((x) << S_MMGRCACHEDIS) +#define F_MMGRCACHEDIS V_MMGRCACHEDIS(1U) + +#define S_TXPKTPACKOUTUDPEN 8 +#define V_TXPKTPACKOUTUDPEN(x) ((x) << S_TXPKTPACKOUTUDPEN) +#define F_TXPKTPACKOUTUDPEN V_TXPKTPACKOUTUDPEN(1U) + +#define S_IPSECROCECRCMODE 6 +#define M_IPSECROCECRCMODE 0x3U +#define V_IPSECROCECRCMODE(x) ((x) << S_IPSECROCECRCMODE) +#define G_IPSECROCECRCMODE(x) (((x) >> S_IPSECROCECRCMODE) & M_IPSECROCECRCMODE) + +#define S_IPSECIDXLOC 5 +#define V_IPSECIDXLOC(x) ((x) << S_IPSECIDXLOC) +#define F_IPSECIDXLOC V_IPSECIDXLOC(1U) + +#define S_IPSECIDXCAPEN 4 +#define V_IPSECIDXCAPEN(x) ((x) << S_IPSECIDXCAPEN) +#define F_IPSECIDXCAPEN V_IPSECIDXCAPEN(1U) + +#define S_IPSECOFEN 3 +#define V_IPSECOFEN(x) ((x) << S_IPSECOFEN) +#define F_IPSECOFEN V_IPSECOFEN(1U) + +#define S_IPSECCFG 0 +#define M_IPSECCFG 0x7U +#define V_IPSECCFG(x) ((x) << S_IPSECCFG) +#define G_IPSECCFG(x) (((x) >> S_IPSECCFG) & M_IPSECCFG) + #define A_TP_TCP_OPTIONS 0x7d40 #define S_MTUDEFAULT 16 @@ -22615,10 +28135,6 @@ #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ) #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ) -#define S_ENABLECBYP 21 -#define V_ENABLECBYP(x) ((x) << S_ENABLECBYP) -#define F_ENABLECBYP V_ENABLECBYP(1U) - #define S_LIMITEDTRANSMIT 20 #define M_LIMITEDTRANSMIT 0xfU #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT) @@ -22779,6 +28295,18 @@ #define V_ECNSYNECT(x) ((x) << S_ECNSYNECT) #define F_ECNSYNECT V_ECNSYNECT(1U) +#define A_TP_PARA_REG9 0x7d88 + +#define S_PMMAXXFERLEN3 16 +#define M_PMMAXXFERLEN3 0xffffU +#define V_PMMAXXFERLEN3(x) ((x) << S_PMMAXXFERLEN3) +#define G_PMMAXXFERLEN3(x) (((x) >> S_PMMAXXFERLEN3) & M_PMMAXXFERLEN3) + +#define S_PMMAXXFERLEN2 0 +#define M_PMMAXXFERLEN2 0xffffU +#define V_PMMAXXFERLEN2(x) ((x) << S_PMMAXXFERLEN2) +#define G_PMMAXXFERLEN2(x) (((x) >> S_PMMAXXFERLEN2) & M_PMMAXXFERLEN2) + #define A_TP_ERR_CONFIG 0x7d8c #define S_TNLERRORPING 30 @@ -22926,6 +28454,11 @@ #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION) +#define S_ROCETIMERRESOLUTION 24 +#define M_ROCETIMERRESOLUTION 0xffU +#define V_ROCETIMERRESOLUTION(x) ((x) << S_ROCETIMERRESOLUTION) +#define G_ROCETIMERRESOLUTION(x) (((x) >> S_ROCETIMERRESOLUTION) & M_ROCETIMERRESOLUTION) + #define A_TP_MSL 0x7d94 #define S_MSL 0 @@ -23423,6 +28956,14 @@ #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK) #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK) +#define S_RRCPLOPT1SMSELEN 11 +#define V_RRCPLOPT1SMSELEN(x) ((x) << S_RRCPLOPT1SMSELEN) +#define F_RRCPLOPT1SMSELEN V_RRCPLOPT1SMSELEN(1U) + +#define S_RRCPLOPT1BQEN 10 +#define V_RRCPLOPT1BQEN(x) ((x) << S_RRCPLOPT1BQEN) +#define F_RRCPLOPT1BQEN V_RRCPLOPT1BQEN(1U) + #define A_TP_RSS_CONFIG_SYN 0x7dfc #define A_TP_RSS_CONFIG_VRT 0x7e00 @@ -23595,6 +29136,69 @@ #define V_QUEUE(x) ((x) << S_QUEUE) #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE) +#define S_T7_UPDVLD 19 +#define V_T7_UPDVLD(x) ((x) << S_T7_UPDVLD) +#define F_T7_UPDVLD V_T7_UPDVLD(1U) + +#define S_T7_XOFF 18 +#define V_T7_XOFF(x) ((x) << S_T7_XOFF) +#define F_T7_XOFF V_T7_XOFF(1U) + +#define S_T7_UPDCHN3 17 +#define V_T7_UPDCHN3(x) ((x) << S_T7_UPDCHN3) +#define F_T7_UPDCHN3 V_T7_UPDCHN3(1U) + +#define S_T7_UPDCHN2 16 +#define V_T7_UPDCHN2(x) ((x) << S_T7_UPDCHN2) +#define F_T7_UPDCHN2 V_T7_UPDCHN2(1U) + +#define S_T7_UPDCHN1 15 +#define V_T7_UPDCHN1(x) ((x) << S_T7_UPDCHN1) +#define F_T7_UPDCHN1 V_T7_UPDCHN1(1U) + +#define S_T7_UPDCHN0 14 +#define V_T7_UPDCHN0(x) ((x) << S_T7_UPDCHN0) +#define F_T7_UPDCHN0 V_T7_UPDCHN0(1U) + +#define S_T7_QUEUE 0 +#define M_T7_QUEUE 0x3fffU +#define V_T7_QUEUE(x) ((x) << S_T7_QUEUE) +#define G_T7_QUEUE(x) (((x) >> S_T7_QUEUE) & M_T7_QUEUE) + +#define A_TP_RSS_CONFIG_4CH 0x7e08 + +#define S_BASEQIDEN 1 +#define V_BASEQIDEN(x) ((x) << S_BASEQIDEN) +#define F_BASEQIDEN V_BASEQIDEN(1U) + +#define S_200GMODE 0 +#define V_200GMODE(x) ((x) << S_200GMODE) +#define F_200GMODE V_200GMODE(1U) + +#define A_TP_RSS_CONFIG_SRAM 0x7e0c + +#define S_SRAMRDDIS 20 +#define V_SRAMRDDIS(x) ((x) << S_SRAMRDDIS) +#define F_SRAMRDDIS V_SRAMRDDIS(1U) + +#define S_SRAMSTART 19 +#define V_SRAMSTART(x) ((x) << S_SRAMSTART) +#define F_SRAMSTART V_SRAMSTART(1U) + +#define S_SRAMWRITE 18 +#define V_SRAMWRITE(x) ((x) << S_SRAMWRITE) +#define F_SRAMWRITE V_SRAMWRITE(1U) + +#define S_SRAMSEL 16 +#define M_SRAMSEL 0x3U +#define V_SRAMSEL(x) ((x) << S_SRAMSEL) +#define G_SRAMSEL(x) (((x) >> S_SRAMSEL) & M_SRAMSEL) + +#define S_SRAMADDR 0 +#define M_SRAMADDR 0x3fffU +#define V_SRAMADDR(x) ((x) << S_SRAMADDR) +#define G_SRAMADDR(x) (((x) >> S_SRAMADDR) & M_SRAMADDR) + #define A_TP_LA_TABLE_0 0x7e10 #define S_VIRTPORT1TABLE 16 @@ -23621,6 +29225,18 @@ #define A_TP_TM_PIO_ADDR 0x7e18 #define A_TP_TM_PIO_DATA 0x7e1c +#define A_TP_RX_MOD_CONFIG_CH3_CH2 0x7e20 + +#define S_RXCHANNELWEIGHT3 8 +#define M_RXCHANNELWEIGHT3 0xffU +#define V_RXCHANNELWEIGHT3(x) ((x) << S_RXCHANNELWEIGHT3) +#define G_RXCHANNELWEIGHT3(x) (((x) >> S_RXCHANNELWEIGHT3) & M_RXCHANNELWEIGHT3) + +#define S_RXCHANNELWEIGHT2 0 +#define M_RXCHANNELWEIGHT2 0xffU +#define V_RXCHANNELWEIGHT2(x) ((x) << S_RXCHANNELWEIGHT2) +#define G_RXCHANNELWEIGHT2(x) (((x) >> S_RXCHANNELWEIGHT2) & M_RXCHANNELWEIGHT2) + #define A_TP_MOD_CONFIG 0x7e24 #define S_RXCHANNELWEIGHT1 24 @@ -23887,6 +29503,30 @@ #define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR) #define F_SRQTABLEPERR V_SRQTABLEPERR(1U) +#define S_TPCERR 5 +#define V_TPCERR(x) ((x) << S_TPCERR) +#define F_TPCERR V_TPCERR(1U) + +#define S_OTHERPERR 4 +#define V_OTHERPERR(x) ((x) << S_OTHERPERR) +#define F_OTHERPERR V_OTHERPERR(1U) + +#define S_TPEING1PERR 3 +#define V_TPEING1PERR(x) ((x) << S_TPEING1PERR) +#define F_TPEING1PERR V_TPEING1PERR(1U) + +#define S_TPEING0PERR 2 +#define V_TPEING0PERR(x) ((x) << S_TPEING0PERR) +#define F_TPEING0PERR V_TPEING0PERR(1U) + +#define S_TPEEGPERR 1 +#define V_TPEEGPERR(x) ((x) << S_TPEEGPERR) +#define F_TPEEGPERR V_TPEEGPERR(1U) + +#define S_TPCPERR 0 +#define V_TPCPERR(x) ((x) << S_TPCPERR) +#define F_TPCPERR V_TPCPERR(1U) + #define A_TP_INT_CAUSE 0x7e74 #define A_TP_PER_ENABLE 0x7e78 #define A_TP_FLM_FREE_PS_CNT 0x7e80 @@ -23907,6 +29547,11 @@ #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT) #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT) +#define S_T7_FREERXPAGECHN 28 +#define M_T7_FREERXPAGECHN 0x7U +#define V_T7_FREERXPAGECHN(x) ((x) << S_T7_FREERXPAGECHN) +#define G_T7_FREERXPAGECHN(x) (((x) >> S_T7_FREERXPAGECHN) & M_T7_FREERXPAGECHN) + #define A_TP_FLM_FREE_TX_CNT 0x7e88 #define S_FREETXPAGECHN 28 @@ -23919,6 +29564,11 @@ #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT) #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT) +#define S_T7_FREETXPAGECHN 28 +#define M_T7_FREETXPAGECHN 0x7U +#define V_T7_FREETXPAGECHN(x) ((x) << S_T7_FREETXPAGECHN) +#define G_T7_FREETXPAGECHN(x) (((x) >> S_T7_FREETXPAGECHN) & M_T7_FREETXPAGECHN) + #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c #define A_TP_TM_HEAP_POP_CNT 0x7e90 #define A_TP_TM_DACK_PUSH_CNT 0x7e94 @@ -24111,6 +29761,38 @@ #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0) #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0) +#define S_RXCOMMITRESET3 7 +#define V_RXCOMMITRESET3(x) ((x) << S_RXCOMMITRESET3) +#define F_RXCOMMITRESET3 V_RXCOMMITRESET3(1U) + +#define S_RXCOMMITRESET2 6 +#define V_RXCOMMITRESET2(x) ((x) << S_RXCOMMITRESET2) +#define F_RXCOMMITRESET2 V_RXCOMMITRESET2(1U) + +#define S_T7_RXCOMMITRESET1 5 +#define V_T7_RXCOMMITRESET1(x) ((x) << S_T7_RXCOMMITRESET1) +#define F_T7_RXCOMMITRESET1 V_T7_RXCOMMITRESET1(1U) + +#define S_T7_RXCOMMITRESET0 4 +#define V_T7_RXCOMMITRESET0(x) ((x) << S_T7_RXCOMMITRESET0) +#define F_T7_RXCOMMITRESET0 V_T7_RXCOMMITRESET0(1U) + +#define S_RXFORCECONG3 3 +#define V_RXFORCECONG3(x) ((x) << S_RXFORCECONG3) +#define F_RXFORCECONG3 V_RXFORCECONG3(1U) + +#define S_RXFORCECONG2 2 +#define V_RXFORCECONG2(x) ((x) << S_RXFORCECONG2) +#define F_RXFORCECONG2 V_RXFORCECONG2(1U) + +#define S_T7_RXFORCECONG1 1 +#define V_T7_RXFORCECONG1(x) ((x) << S_T7_RXFORCECONG1) +#define F_T7_RXFORCECONG1 V_T7_RXFORCECONG1(1U) + +#define S_T7_RXFORCECONG0 0 +#define V_T7_RXFORCECONG0(x) ((x) << S_T7_RXFORCECONG0) +#define F_T7_RXFORCECONG0 V_T7_RXFORCECONG0(1U) + #define A_TP_TX_SCHED 0x7eb4 #define S_COMMITRESET3 31 @@ -24229,6 +29911,14 @@ #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0) #define F_RXMODXOFF0 V_RXMODXOFF0(1U) +#define S_RXMODXOFF3 3 +#define V_RXMODXOFF3(x) ((x) << S_RXMODXOFF3) +#define F_RXMODXOFF3 V_RXMODXOFF3(1U) + +#define S_RXMODXOFF2 2 +#define V_RXMODXOFF2(x) ((x) << S_RXMODXOFF2) +#define F_RXMODXOFF2 V_RXMODXOFF2(1U) + #define A_TP_TX_ORATE 0x7ebc #define S_OFDRATE3 24 @@ -24313,6 +30003,37 @@ #define A_TP_DBG_LA_DATAL 0x7ed8 #define A_TP_DBG_LA_DATAH 0x7edc +#define A_TP_DBG_LA_FILTER 0x7ee0 + +#define S_FILTERTID 12 +#define M_FILTERTID 0xfffffU +#define V_FILTERTID(x) ((x) << S_FILTERTID) +#define G_FILTERTID(x) (((x) >> S_FILTERTID) & M_FILTERTID) + +#define S_ENTIDFILTER 5 +#define V_ENTIDFILTER(x) ((x) << S_ENTIDFILTER) +#define F_ENTIDFILTER V_ENTIDFILTER(1U) + +#define S_ENOFFLOAD 4 +#define V_ENOFFLOAD(x) ((x) << S_ENOFFLOAD) +#define F_ENOFFLOAD V_ENOFFLOAD(1U) + +#define S_ENTUNNEL 3 +#define V_ENTUNNEL(x) ((x) << S_ENTUNNEL) +#define F_ENTUNNEL V_ENTUNNEL(1U) + +#define S_ENI 2 +#define V_ENI(x) ((x) << S_ENI) +#define F_ENI V_ENI(1U) + +#define S_ENC 1 +#define V_ENC(x) ((x) << S_ENC) +#define F_ENC V_ENC(1U) + +#define S_ENE 0 +#define V_ENE(x) ((x) << S_ENE) +#define F_ENE V_ENE(1U) + #define A_TP_PROTOCOL_CNTRL 0x7ee8 #define S_WRITEENABLE 31 @@ -24348,6 +30069,546 @@ #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD) #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD) +#define A_TP_INIC_CTRL0 0x7f00 +#define A_TP_INIC_DBG 0x7f04 +#define A_TP_INIC_PERR_ENABLE 0x7f08 + +#define S_INICMAC1_ERR 16 +#define M_INICMAC1_ERR 0x3fU +#define V_INICMAC1_ERR(x) ((x) << S_INICMAC1_ERR) +#define G_INICMAC1_ERR(x) (((x) >> S_INICMAC1_ERR) & M_INICMAC1_ERR) + +#define S_INICMAC0_ERR 0 +#define M_INICMAC0_ERR 0x3fU +#define V_INICMAC0_ERR(x) ((x) << S_INICMAC0_ERR) +#define G_INICMAC0_ERR(x) (((x) >> S_INICMAC0_ERR) & M_INICMAC0_ERR) + +#define A_TP_INIC_PERR_CAUSE 0x7f0c +#define A_TP_PARA_REG10 0x7f20 + +#define S_DIS39320FIX 20 +#define V_DIS39320FIX(x) ((x) << S_DIS39320FIX) +#define F_DIS39320FIX V_DIS39320FIX(1U) + +#define S_IWARPMAXPDULEN 16 +#define M_IWARPMAXPDULEN 0xfU +#define V_IWARPMAXPDULEN(x) ((x) << S_IWARPMAXPDULEN) +#define G_IWARPMAXPDULEN(x) (((x) >> S_IWARPMAXPDULEN) & M_IWARPMAXPDULEN) + +#define S_TLSMAXRXDATA 0 +#define M_TLSMAXRXDATA 0xffffU +#define V_TLSMAXRXDATA(x) ((x) << S_TLSMAXRXDATA) +#define G_TLSMAXRXDATA(x) (((x) >> S_TLSMAXRXDATA) & M_TLSMAXRXDATA) + +#define A_TP_TCAM_BIST_CTRL 0x7f24 +#define A_TP_TCAM_BIST_CB_PASS 0x7f28 +#define A_TP_TCAM_BIST_CB_BUSY 0x7f2c +#define A_TP_C_PERR_ENABLE 0x7f30 + +#define S_DMXFIFOOVFL 26 +#define V_DMXFIFOOVFL(x) ((x) << S_DMXFIFOOVFL) +#define F_DMXFIFOOVFL V_DMXFIFOOVFL(1U) + +#define S_URX2TPCDDPINTF 25 +#define V_URX2TPCDDPINTF(x) ((x) << S_URX2TPCDDPINTF) +#define F_URX2TPCDDPINTF V_URX2TPCDDPINTF(1U) + +#define S_TPCDISPTOKENFIFO 24 +#define V_TPCDISPTOKENFIFO(x) ((x) << S_TPCDISPTOKENFIFO) +#define F_TPCDISPTOKENFIFO V_TPCDISPTOKENFIFO(1U) + +#define S_TPCDISPCPLFIFO3 23 +#define V_TPCDISPCPLFIFO3(x) ((x) << S_TPCDISPCPLFIFO3) +#define F_TPCDISPCPLFIFO3 V_TPCDISPCPLFIFO3(1U) + +#define S_TPCDISPCPLFIFO2 22 +#define V_TPCDISPCPLFIFO2(x) ((x) << S_TPCDISPCPLFIFO2) +#define F_TPCDISPCPLFIFO2 V_TPCDISPCPLFIFO2(1U) + +#define S_TPCDISPCPLFIFO1 21 +#define V_TPCDISPCPLFIFO1(x) ((x) << S_TPCDISPCPLFIFO1) +#define F_TPCDISPCPLFIFO1 V_TPCDISPCPLFIFO1(1U) + +#define S_TPCDISPCPLFIFO0 20 +#define V_TPCDISPCPLFIFO0(x) ((x) << S_TPCDISPCPLFIFO0) +#define F_TPCDISPCPLFIFO0 V_TPCDISPCPLFIFO0(1U) + +#define S_URXPLDINTFCRC3 19 +#define V_URXPLDINTFCRC3(x) ((x) << S_URXPLDINTFCRC3) +#define F_URXPLDINTFCRC3 V_URXPLDINTFCRC3(1U) + +#define S_URXPLDINTFCRC2 18 +#define V_URXPLDINTFCRC2(x) ((x) << S_URXPLDINTFCRC2) +#define F_URXPLDINTFCRC2 V_URXPLDINTFCRC2(1U) + +#define S_URXPLDINTFCRC1 17 +#define V_URXPLDINTFCRC1(x) ((x) << S_URXPLDINTFCRC1) +#define F_URXPLDINTFCRC1 V_URXPLDINTFCRC1(1U) + +#define S_URXPLDINTFCRC0 16 +#define V_URXPLDINTFCRC0(x) ((x) << S_URXPLDINTFCRC0) +#define F_URXPLDINTFCRC0 V_URXPLDINTFCRC0(1U) + +#define S_DMXDBFIFO 15 +#define V_DMXDBFIFO(x) ((x) << S_DMXDBFIFO) +#define F_DMXDBFIFO V_DMXDBFIFO(1U) + +#define S_DMXDBSRAM 14 +#define V_DMXDBSRAM(x) ((x) << S_DMXDBSRAM) +#define F_DMXDBSRAM V_DMXDBSRAM(1U) + +#define S_DMXCPLFIFO 13 +#define V_DMXCPLFIFO(x) ((x) << S_DMXCPLFIFO) +#define F_DMXCPLFIFO V_DMXCPLFIFO(1U) + +#define S_DMXCPLSRAM 12 +#define V_DMXCPLSRAM(x) ((x) << S_DMXCPLSRAM) +#define F_DMXCPLSRAM V_DMXCPLSRAM(1U) + +#define S_DMXCSUMFIFO 11 +#define V_DMXCSUMFIFO(x) ((x) << S_DMXCSUMFIFO) +#define F_DMXCSUMFIFO V_DMXCSUMFIFO(1U) + +#define S_DMXLENFIFO 10 +#define V_DMXLENFIFO(x) ((x) << S_DMXLENFIFO) +#define F_DMXLENFIFO V_DMXLENFIFO(1U) + +#define S_DMXCHECKFIFO 9 +#define V_DMXCHECKFIFO(x) ((x) << S_DMXCHECKFIFO) +#define F_DMXCHECKFIFO V_DMXCHECKFIFO(1U) + +#define S_DMXWINFIFO 8 +#define V_DMXWINFIFO(x) ((x) << S_DMXWINFIFO) +#define F_DMXWINFIFO V_DMXWINFIFO(1U) + +#define S_EGTOKENFIFO 7 +#define V_EGTOKENFIFO(x) ((x) << S_EGTOKENFIFO) +#define F_EGTOKENFIFO V_EGTOKENFIFO(1U) + +#define S_EGDATAFIFO 6 +#define V_EGDATAFIFO(x) ((x) << S_EGDATAFIFO) +#define F_EGDATAFIFO V_EGDATAFIFO(1U) + +#define S_UTX2TPCINTF3 5 +#define V_UTX2TPCINTF3(x) ((x) << S_UTX2TPCINTF3) +#define F_UTX2TPCINTF3 V_UTX2TPCINTF3(1U) + +#define S_UTX2TPCINTF2 4 +#define V_UTX2TPCINTF2(x) ((x) << S_UTX2TPCINTF2) +#define F_UTX2TPCINTF2 V_UTX2TPCINTF2(1U) + +#define S_UTX2TPCINTF1 3 +#define V_UTX2TPCINTF1(x) ((x) << S_UTX2TPCINTF1) +#define F_UTX2TPCINTF1 V_UTX2TPCINTF1(1U) + +#define S_UTX2TPCINTF0 2 +#define V_UTX2TPCINTF0(x) ((x) << S_UTX2TPCINTF0) +#define F_UTX2TPCINTF0 V_UTX2TPCINTF0(1U) + +#define S_LBKTOKENFIFO 1 +#define V_LBKTOKENFIFO(x) ((x) << S_LBKTOKENFIFO) +#define F_LBKTOKENFIFO V_LBKTOKENFIFO(1U) + +#define S_LBKDATAFIFO 0 +#define V_LBKDATAFIFO(x) ((x) << S_LBKDATAFIFO) +#define F_LBKDATAFIFO V_LBKDATAFIFO(1U) + +#define A_TP_C_PERR_CAUSE 0x7f34 +#define A_TP_E_EG_PERR_ENABLE 0x7f38 + +#define S_MPSLPBKTOKENFIFO 25 +#define V_MPSLPBKTOKENFIFO(x) ((x) << S_MPSLPBKTOKENFIFO) +#define F_MPSLPBKTOKENFIFO V_MPSLPBKTOKENFIFO(1U) + +#define S_MPSMACTOKENFIFO 24 +#define V_MPSMACTOKENFIFO(x) ((x) << S_MPSMACTOKENFIFO) +#define F_MPSMACTOKENFIFO V_MPSMACTOKENFIFO(1U) + +#define S_DISPIPSECFIFO3 23 +#define V_DISPIPSECFIFO3(x) ((x) << S_DISPIPSECFIFO3) +#define F_DISPIPSECFIFO3 V_DISPIPSECFIFO3(1U) + +#define S_DISPTCPFIFO3 22 +#define V_DISPTCPFIFO3(x) ((x) << S_DISPTCPFIFO3) +#define F_DISPTCPFIFO3 V_DISPTCPFIFO3(1U) + +#define S_DISPIPFIFO3 21 +#define V_DISPIPFIFO3(x) ((x) << S_DISPIPFIFO3) +#define F_DISPIPFIFO3 V_DISPIPFIFO3(1U) + +#define S_DISPETHFIFO3 20 +#define V_DISPETHFIFO3(x) ((x) << S_DISPETHFIFO3) +#define F_DISPETHFIFO3 V_DISPETHFIFO3(1U) + +#define S_DISPGREFIFO3 19 +#define V_DISPGREFIFO3(x) ((x) << S_DISPGREFIFO3) +#define F_DISPGREFIFO3 V_DISPGREFIFO3(1U) + +#define S_DISPCPL5FIFO3 18 +#define V_DISPCPL5FIFO3(x) ((x) << S_DISPCPL5FIFO3) +#define F_DISPCPL5FIFO3 V_DISPCPL5FIFO3(1U) + +#define S_DISPIPSECFIFO2 17 +#define V_DISPIPSECFIFO2(x) ((x) << S_DISPIPSECFIFO2) +#define F_DISPIPSECFIFO2 V_DISPIPSECFIFO2(1U) + +#define S_DISPTCPFIFO2 16 +#define V_DISPTCPFIFO2(x) ((x) << S_DISPTCPFIFO2) +#define F_DISPTCPFIFO2 V_DISPTCPFIFO2(1U) + +#define S_DISPIPFIFO2 15 +#define V_DISPIPFIFO2(x) ((x) << S_DISPIPFIFO2) +#define F_DISPIPFIFO2 V_DISPIPFIFO2(1U) + +#define S_DISPETHFIFO2 14 +#define V_DISPETHFIFO2(x) ((x) << S_DISPETHFIFO2) +#define F_DISPETHFIFO2 V_DISPETHFIFO2(1U) + +#define S_DISPGREFIFO2 13 +#define V_DISPGREFIFO2(x) ((x) << S_DISPGREFIFO2) +#define F_DISPGREFIFO2 V_DISPGREFIFO2(1U) + +#define S_DISPCPL5FIFO2 12 +#define V_DISPCPL5FIFO2(x) ((x) << S_DISPCPL5FIFO2) +#define F_DISPCPL5FIFO2 V_DISPCPL5FIFO2(1U) + +#define S_DISPIPSECFIFO1 11 +#define V_DISPIPSECFIFO1(x) ((x) << S_DISPIPSECFIFO1) +#define F_DISPIPSECFIFO1 V_DISPIPSECFIFO1(1U) + +#define S_DISPTCPFIFO1 10 +#define V_DISPTCPFIFO1(x) ((x) << S_DISPTCPFIFO1) +#define F_DISPTCPFIFO1 V_DISPTCPFIFO1(1U) + +#define S_DISPIPFIFO1 9 +#define V_DISPIPFIFO1(x) ((x) << S_DISPIPFIFO1) +#define F_DISPIPFIFO1 V_DISPIPFIFO1(1U) + +#define S_DISPETHFIFO1 8 +#define V_DISPETHFIFO1(x) ((x) << S_DISPETHFIFO1) +#define F_DISPETHFIFO1 V_DISPETHFIFO1(1U) + +#define S_DISPGREFIFO1 7 +#define V_DISPGREFIFO1(x) ((x) << S_DISPGREFIFO1) +#define F_DISPGREFIFO1 V_DISPGREFIFO1(1U) + +#define S_DISPCPL5FIFO1 6 +#define V_DISPCPL5FIFO1(x) ((x) << S_DISPCPL5FIFO1) +#define F_DISPCPL5FIFO1 V_DISPCPL5FIFO1(1U) + +#define S_DISPIPSECFIFO0 5 +#define V_DISPIPSECFIFO0(x) ((x) << S_DISPIPSECFIFO0) +#define F_DISPIPSECFIFO0 V_DISPIPSECFIFO0(1U) + +#define S_DISPTCPFIFO0 4 +#define V_DISPTCPFIFO0(x) ((x) << S_DISPTCPFIFO0) +#define F_DISPTCPFIFO0 V_DISPTCPFIFO0(1U) + +#define S_DISPIPFIFO0 3 +#define V_DISPIPFIFO0(x) ((x) << S_DISPIPFIFO0) +#define F_DISPIPFIFO0 V_DISPIPFIFO0(1U) + +#define S_DISPETHFIFO0 2 +#define V_DISPETHFIFO0(x) ((x) << S_DISPETHFIFO0) +#define F_DISPETHFIFO0 V_DISPETHFIFO0(1U) + +#define S_DISPGREFIFO0 1 +#define V_DISPGREFIFO0(x) ((x) << S_DISPGREFIFO0) +#define F_DISPGREFIFO0 V_DISPGREFIFO0(1U) + +#define S_DISPCPL5FIFO0 0 +#define V_DISPCPL5FIFO0(x) ((x) << S_DISPCPL5FIFO0) +#define F_DISPCPL5FIFO0 V_DISPCPL5FIFO0(1U) + +#define A_TP_E_EG_PERR_CAUSE 0x7f3c +#define A_TP_E_IN0_PERR_ENABLE 0x7f40 + +#define S_DMXISSFIFO 30 +#define V_DMXISSFIFO(x) ((x) << S_DMXISSFIFO) +#define F_DMXISSFIFO V_DMXISSFIFO(1U) + +#define S_DMXERRFIFO 29 +#define V_DMXERRFIFO(x) ((x) << S_DMXERRFIFO) +#define F_DMXERRFIFO V_DMXERRFIFO(1U) + +#define S_DMXATTFIFO 28 +#define V_DMXATTFIFO(x) ((x) << S_DMXATTFIFO) +#define F_DMXATTFIFO V_DMXATTFIFO(1U) + +#define S_DMXTCPFIFO 27 +#define V_DMXTCPFIFO(x) ((x) << S_DMXTCPFIFO) +#define F_DMXTCPFIFO V_DMXTCPFIFO(1U) + +#define S_DMXMPAFIFO 26 +#define V_DMXMPAFIFO(x) ((x) << S_DMXMPAFIFO) +#define F_DMXMPAFIFO V_DMXMPAFIFO(1U) + +#define S_DMXOPTFIFO 25 +#define V_DMXOPTFIFO(x) ((x) << S_DMXOPTFIFO) +#define F_DMXOPTFIFO V_DMXOPTFIFO(1U) + +#define S_INGTOKENFIFO 24 +#define V_INGTOKENFIFO(x) ((x) << S_INGTOKENFIFO) +#define F_INGTOKENFIFO V_INGTOKENFIFO(1U) + +#define S_DMXPLDCHKOVFL1 21 +#define V_DMXPLDCHKOVFL1(x) ((x) << S_DMXPLDCHKOVFL1) +#define F_DMXPLDCHKOVFL1 V_DMXPLDCHKOVFL1(1U) + +#define S_DMXPLDCHKFIFO1 20 +#define V_DMXPLDCHKFIFO1(x) ((x) << S_DMXPLDCHKFIFO1) +#define F_DMXPLDCHKFIFO1 V_DMXPLDCHKFIFO1(1U) + +#define S_DMXOPTFIFO1 19 +#define V_DMXOPTFIFO1(x) ((x) << S_DMXOPTFIFO1) +#define F_DMXOPTFIFO1 V_DMXOPTFIFO1(1U) + +#define S_DMXMPAFIFO1 18 +#define V_DMXMPAFIFO1(x) ((x) << S_DMXMPAFIFO1) +#define F_DMXMPAFIFO1 V_DMXMPAFIFO1(1U) + +#define S_DMXDBFIFO1 17 +#define V_DMXDBFIFO1(x) ((x) << S_DMXDBFIFO1) +#define F_DMXDBFIFO1 V_DMXDBFIFO1(1U) + +#define S_DMXATTFIFO1 16 +#define V_DMXATTFIFO1(x) ((x) << S_DMXATTFIFO1) +#define F_DMXATTFIFO1 V_DMXATTFIFO1(1U) + +#define S_DMXISSFIFO1 15 +#define V_DMXISSFIFO1(x) ((x) << S_DMXISSFIFO1) +#define F_DMXISSFIFO1 V_DMXISSFIFO1(1U) + +#define S_DMXTCPFIFO1 14 +#define V_DMXTCPFIFO1(x) ((x) << S_DMXTCPFIFO1) +#define F_DMXTCPFIFO1 V_DMXTCPFIFO1(1U) + +#define S_DMXERRFIFO1 13 +#define V_DMXERRFIFO1(x) ((x) << S_DMXERRFIFO1) +#define F_DMXERRFIFO1 V_DMXERRFIFO1(1U) + +#define S_MPS2TPINTF1 12 +#define V_MPS2TPINTF1(x) ((x) << S_MPS2TPINTF1) +#define F_MPS2TPINTF1 V_MPS2TPINTF1(1U) + +#define S_DMXPLDCHKOVFL0 9 +#define V_DMXPLDCHKOVFL0(x) ((x) << S_DMXPLDCHKOVFL0) +#define F_DMXPLDCHKOVFL0 V_DMXPLDCHKOVFL0(1U) + +#define S_DMXPLDCHKFIFO0 8 +#define V_DMXPLDCHKFIFO0(x) ((x) << S_DMXPLDCHKFIFO0) +#define F_DMXPLDCHKFIFO0 V_DMXPLDCHKFIFO0(1U) + +#define S_DMXOPTFIFO0 7 +#define V_DMXOPTFIFO0(x) ((x) << S_DMXOPTFIFO0) +#define F_DMXOPTFIFO0 V_DMXOPTFIFO0(1U) + +#define S_DMXMPAFIFO0 6 +#define V_DMXMPAFIFO0(x) ((x) << S_DMXMPAFIFO0) +#define F_DMXMPAFIFO0 V_DMXMPAFIFO0(1U) + +#define S_DMXDBFIFO0 5 +#define V_DMXDBFIFO0(x) ((x) << S_DMXDBFIFO0) +#define F_DMXDBFIFO0 V_DMXDBFIFO0(1U) + +#define S_DMXATTFIFO0 4 +#define V_DMXATTFIFO0(x) ((x) << S_DMXATTFIFO0) +#define F_DMXATTFIFO0 V_DMXATTFIFO0(1U) + +#define S_DMXISSFIFO0 3 +#define V_DMXISSFIFO0(x) ((x) << S_DMXISSFIFO0) +#define F_DMXISSFIFO0 V_DMXISSFIFO0(1U) + +#define S_DMXTCPFIFO0 2 +#define V_DMXTCPFIFO0(x) ((x) << S_DMXTCPFIFO0) +#define F_DMXTCPFIFO0 V_DMXTCPFIFO0(1U) + +#define S_DMXERRFIFO0 1 +#define V_DMXERRFIFO0(x) ((x) << S_DMXERRFIFO0) +#define F_DMXERRFIFO0 V_DMXERRFIFO0(1U) + +#define S_MPS2TPINTF0 0 +#define V_MPS2TPINTF0(x) ((x) << S_MPS2TPINTF0) +#define F_MPS2TPINTF0 V_MPS2TPINTF0(1U) + +#define A_TP_E_IN0_PERR_CAUSE 0x7f44 +#define A_TP_E_IN1_PERR_ENABLE 0x7f48 + +#define S_DMXPLDCHKOVFL3 21 +#define V_DMXPLDCHKOVFL3(x) ((x) << S_DMXPLDCHKOVFL3) +#define F_DMXPLDCHKOVFL3 V_DMXPLDCHKOVFL3(1U) + +#define S_DMXPLDCHKFIFO3 20 +#define V_DMXPLDCHKFIFO3(x) ((x) << S_DMXPLDCHKFIFO3) +#define F_DMXPLDCHKFIFO3 V_DMXPLDCHKFIFO3(1U) + +#define S_DMXOPTFIFO3 19 +#define V_DMXOPTFIFO3(x) ((x) << S_DMXOPTFIFO3) +#define F_DMXOPTFIFO3 V_DMXOPTFIFO3(1U) + +#define S_DMXMPAFIFO3 18 +#define V_DMXMPAFIFO3(x) ((x) << S_DMXMPAFIFO3) +#define F_DMXMPAFIFO3 V_DMXMPAFIFO3(1U) + +#define S_DMXDBFIFO3 17 +#define V_DMXDBFIFO3(x) ((x) << S_DMXDBFIFO3) +#define F_DMXDBFIFO3 V_DMXDBFIFO3(1U) + +#define S_DMXATTFIFO3 16 +#define V_DMXATTFIFO3(x) ((x) << S_DMXATTFIFO3) +#define F_DMXATTFIFO3 V_DMXATTFIFO3(1U) + +#define S_DMXISSFIFO3 15 +#define V_DMXISSFIFO3(x) ((x) << S_DMXISSFIFO3) +#define F_DMXISSFIFO3 V_DMXISSFIFO3(1U) + +#define S_DMXTCPFIFO3 14 +#define V_DMXTCPFIFO3(x) ((x) << S_DMXTCPFIFO3) +#define F_DMXTCPFIFO3 V_DMXTCPFIFO3(1U) + +#define S_DMXERRFIFO3 13 +#define V_DMXERRFIFO3(x) ((x) << S_DMXERRFIFO3) +#define F_DMXERRFIFO3 V_DMXERRFIFO3(1U) + +#define S_MPS2TPINTF3 12 +#define V_MPS2TPINTF3(x) ((x) << S_MPS2TPINTF3) +#define F_MPS2TPINTF3 V_MPS2TPINTF3(1U) + +#define S_DMXPLDCHKOVFL2 9 +#define V_DMXPLDCHKOVFL2(x) ((x) << S_DMXPLDCHKOVFL2) +#define F_DMXPLDCHKOVFL2 V_DMXPLDCHKOVFL2(1U) + +#define S_DMXPLDCHKFIFO2 8 +#define V_DMXPLDCHKFIFO2(x) ((x) << S_DMXPLDCHKFIFO2) +#define F_DMXPLDCHKFIFO2 V_DMXPLDCHKFIFO2(1U) + +#define S_DMXOPTFIFO2 7 +#define V_DMXOPTFIFO2(x) ((x) << S_DMXOPTFIFO2) +#define F_DMXOPTFIFO2 V_DMXOPTFIFO2(1U) + +#define S_DMXMPAFIFO2 6 +#define V_DMXMPAFIFO2(x) ((x) << S_DMXMPAFIFO2) +#define F_DMXMPAFIFO2 V_DMXMPAFIFO2(1U) + +#define S_DMXDBFIFO2 5 +#define V_DMXDBFIFO2(x) ((x) << S_DMXDBFIFO2) +#define F_DMXDBFIFO2 V_DMXDBFIFO2(1U) + +#define S_DMXATTFIFO2 4 +#define V_DMXATTFIFO2(x) ((x) << S_DMXATTFIFO2) +#define F_DMXATTFIFO2 V_DMXATTFIFO2(1U) + +#define S_DMXISSFIFO2 3 +#define V_DMXISSFIFO2(x) ((x) << S_DMXISSFIFO2) +#define F_DMXISSFIFO2 V_DMXISSFIFO2(1U) + +#define S_DMXTCPFIFO2 2 +#define V_DMXTCPFIFO2(x) ((x) << S_DMXTCPFIFO2) +#define F_DMXTCPFIFO2 V_DMXTCPFIFO2(1U) + +#define S_DMXERRFIFO2 1 +#define V_DMXERRFIFO2(x) ((x) << S_DMXERRFIFO2) +#define F_DMXERRFIFO2 V_DMXERRFIFO2(1U) + +#define S_MPS2TPINTF2 0 +#define V_MPS2TPINTF2(x) ((x) << S_MPS2TPINTF2) +#define F_MPS2TPINTF2 V_MPS2TPINTF2(1U) + +#define A_TP_E_IN1_PERR_CAUSE 0x7f4c +#define A_TP_O_PERR_ENABLE 0x7f50 + +#define S_DMARBTPERR 31 +#define V_DMARBTPERR(x) ((x) << S_DMARBTPERR) +#define F_DMARBTPERR V_DMARBTPERR(1U) + +#define S_MMGRCACHEDATASRAM 24 +#define V_MMGRCACHEDATASRAM(x) ((x) << S_MMGRCACHEDATASRAM) +#define F_MMGRCACHEDATASRAM V_MMGRCACHEDATASRAM(1U) + +#define S_MMGRCACHETAGFIFO 23 +#define V_MMGRCACHETAGFIFO(x) ((x) << S_MMGRCACHETAGFIFO) +#define F_MMGRCACHETAGFIFO V_MMGRCACHETAGFIFO(1U) + +#define S_TPPROTOSRAM 16 +#define V_TPPROTOSRAM(x) ((x) << S_TPPROTOSRAM) +#define F_TPPROTOSRAM V_TPPROTOSRAM(1U) + +#define S_HSPSRAM 15 +#define V_HSPSRAM(x) ((x) << S_HSPSRAM) +#define F_HSPSRAM V_HSPSRAM(1U) + +#define S_RATEGRPSRAM 14 +#define V_RATEGRPSRAM(x) ((x) << S_RATEGRPSRAM) +#define F_RATEGRPSRAM V_RATEGRPSRAM(1U) + +#define S_TXFBSEQFIFO 13 +#define V_TXFBSEQFIFO(x) ((x) << S_TXFBSEQFIFO) +#define F_TXFBSEQFIFO V_TXFBSEQFIFO(1U) + +#define S_CMDATASRAM 12 +#define V_CMDATASRAM(x) ((x) << S_CMDATASRAM) +#define F_CMDATASRAM V_CMDATASRAM(1U) + +#define S_CMTAGFIFO 11 +#define V_CMTAGFIFO(x) ((x) << S_CMTAGFIFO) +#define F_CMTAGFIFO V_CMTAGFIFO(1U) + +#define S_RFCOPFIFO 10 +#define V_RFCOPFIFO(x) ((x) << S_RFCOPFIFO) +#define F_RFCOPFIFO V_RFCOPFIFO(1U) + +#define S_DELINVFIFO 9 +#define V_DELINVFIFO(x) ((x) << S_DELINVFIFO) +#define F_DELINVFIFO V_DELINVFIFO(1U) + +#define S_RSSCFGSRAM 8 +#define V_RSSCFGSRAM(x) ((x) << S_RSSCFGSRAM) +#define F_RSSCFGSRAM V_RSSCFGSRAM(1U) + +#define S_RSSKEYSRAM 7 +#define V_RSSKEYSRAM(x) ((x) << S_RSSKEYSRAM) +#define F_RSSKEYSRAM V_RSSKEYSRAM(1U) + +#define S_RSSLKPSRAM 6 +#define V_RSSLKPSRAM(x) ((x) << S_RSSLKPSRAM) +#define F_RSSLKPSRAM V_RSSLKPSRAM(1U) + +#define S_SRQSRAM 5 +#define V_SRQSRAM(x) ((x) << S_SRQSRAM) +#define F_SRQSRAM V_SRQSRAM(1U) + +#define S_ARPDASRAM 4 +#define V_ARPDASRAM(x) ((x) << S_ARPDASRAM) +#define F_ARPDASRAM V_ARPDASRAM(1U) + +#define S_ARPSASRAM 3 +#define V_ARPSASRAM(x) ((x) << S_ARPSASRAM) +#define F_ARPSASRAM V_ARPSASRAM(1U) + +#define S_ARPGRESRAM 2 +#define V_ARPGRESRAM(x) ((x) << S_ARPGRESRAM) +#define F_ARPGRESRAM V_ARPGRESRAM(1U) + +#define S_ARPIPSECSRAM1 1 +#define V_ARPIPSECSRAM1(x) ((x) << S_ARPIPSECSRAM1) +#define F_ARPIPSECSRAM1 V_ARPIPSECSRAM1(1U) + +#define S_ARPIPSECSRAM0 0 +#define V_ARPIPSECSRAM0(x) ((x) << S_ARPIPSECSRAM0) +#define F_ARPIPSECSRAM0 V_ARPIPSECSRAM0(1U) + +#define A_TP_O_PERR_CAUSE 0x7f54 +#define A_TP_CERR_ENABLE 0x7f58 + +#define S_TPCEGDATAFIFO 8 +#define V_TPCEGDATAFIFO(x) ((x) << S_TPCEGDATAFIFO) +#define F_TPCEGDATAFIFO V_TPCEGDATAFIFO(1U) + +#define S_TPCLBKDATAFIFO 7 +#define V_TPCLBKDATAFIFO(x) ((x) << S_TPCLBKDATAFIFO) +#define F_TPCLBKDATAFIFO V_TPCLBKDATAFIFO(1U) + +#define A_TP_CERR_CAUSE 0x7f5c #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0 #define S_TXTIMERSEPQ7 16 @@ -24520,6 +30781,137 @@ #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb +#define A_TP_RX_MOD_Q3_Q2_TIMER_SEPARATOR 0xc + +#define S_RXTIMERSEPQ3 16 +#define M_RXTIMERSEPQ3 0xffffU +#define V_RXTIMERSEPQ3(x) ((x) << S_RXTIMERSEPQ3) +#define G_RXTIMERSEPQ3(x) (((x) >> S_RXTIMERSEPQ3) & M_RXTIMERSEPQ3) + +#define S_RXTIMERSEPQ2 0 +#define M_RXTIMERSEPQ2 0xffffU +#define V_RXTIMERSEPQ2(x) ((x) << S_RXTIMERSEPQ2) +#define G_RXTIMERSEPQ2(x) (((x) >> S_RXTIMERSEPQ2) & M_RXTIMERSEPQ2) + +#define A_TP_RX_MOD_Q3_Q2_RATE_LIMIT 0xd + +#define S_RXRATEINCQ3 24 +#define M_RXRATEINCQ3 0xffU +#define V_RXRATEINCQ3(x) ((x) << S_RXRATEINCQ3) +#define G_RXRATEINCQ3(x) (((x) >> S_RXRATEINCQ3) & M_RXRATEINCQ3) + +#define S_RXRATETCKQ3 16 +#define M_RXRATETCKQ3 0xffU +#define V_RXRATETCKQ3(x) ((x) << S_RXRATETCKQ3) +#define G_RXRATETCKQ3(x) (((x) >> S_RXRATETCKQ3) & M_RXRATETCKQ3) + +#define S_RXRATEINCQ2 8 +#define M_RXRATEINCQ2 0xffU +#define V_RXRATEINCQ2(x) ((x) << S_RXRATEINCQ2) +#define G_RXRATEINCQ2(x) (((x) >> S_RXRATEINCQ2) & M_RXRATEINCQ2) + +#define S_RXRATETCKQ2 0 +#define M_RXRATETCKQ2 0xffU +#define V_RXRATETCKQ2(x) ((x) << S_RXRATETCKQ2) +#define G_RXRATETCKQ2(x) (((x) >> S_RXRATETCKQ2) & M_RXRATETCKQ2) + +#define A_TP_RX_LPBK_CONG 0x1c +#define A_TP_RX_SCHED_MOD 0x1d + +#define S_T7_ENABLELPBKFULL1 28 +#define M_T7_ENABLELPBKFULL1 0xfU +#define V_T7_ENABLELPBKFULL1(x) ((x) << S_T7_ENABLELPBKFULL1) +#define G_T7_ENABLELPBKFULL1(x) (((x) >> S_T7_ENABLELPBKFULL1) & M_T7_ENABLELPBKFULL1) + +#define S_T7_ENABLEFIFOFULL1 24 +#define M_T7_ENABLEFIFOFULL1 0xfU +#define V_T7_ENABLEFIFOFULL1(x) ((x) << S_T7_ENABLEFIFOFULL1) +#define G_T7_ENABLEFIFOFULL1(x) (((x) >> S_T7_ENABLEFIFOFULL1) & M_T7_ENABLEFIFOFULL1) + +#define S_T7_ENABLEPCMDFULL1 20 +#define M_T7_ENABLEPCMDFULL1 0xfU +#define V_T7_ENABLEPCMDFULL1(x) ((x) << S_T7_ENABLEPCMDFULL1) +#define G_T7_ENABLEPCMDFULL1(x) (((x) >> S_T7_ENABLEPCMDFULL1) & M_T7_ENABLEPCMDFULL1) + +#define S_T7_ENABLEHDRFULL1 16 +#define M_T7_ENABLEHDRFULL1 0xfU +#define V_T7_ENABLEHDRFULL1(x) ((x) << S_T7_ENABLEHDRFULL1) +#define G_T7_ENABLEHDRFULL1(x) (((x) >> S_T7_ENABLEHDRFULL1) & M_T7_ENABLEHDRFULL1) + +#define S_T7_ENABLELPBKFULL0 12 +#define M_T7_ENABLELPBKFULL0 0xfU +#define V_T7_ENABLELPBKFULL0(x) ((x) << S_T7_ENABLELPBKFULL0) +#define G_T7_ENABLELPBKFULL0(x) (((x) >> S_T7_ENABLELPBKFULL0) & M_T7_ENABLELPBKFULL0) + +#define S_T7_ENABLEFIFOFULL0 8 +#define M_T7_ENABLEFIFOFULL0 0xfU +#define V_T7_ENABLEFIFOFULL0(x) ((x) << S_T7_ENABLEFIFOFULL0) +#define G_T7_ENABLEFIFOFULL0(x) (((x) >> S_T7_ENABLEFIFOFULL0) & M_T7_ENABLEFIFOFULL0) + +#define S_T7_ENABLEPCMDFULL0 4 +#define M_T7_ENABLEPCMDFULL0 0xfU +#define V_T7_ENABLEPCMDFULL0(x) ((x) << S_T7_ENABLEPCMDFULL0) +#define G_T7_ENABLEPCMDFULL0(x) (((x) >> S_T7_ENABLEPCMDFULL0) & M_T7_ENABLEPCMDFULL0) + +#define S_T7_ENABLEHDRFULL0 0 +#define M_T7_ENABLEHDRFULL0 0xfU +#define V_T7_ENABLEHDRFULL0(x) ((x) << S_T7_ENABLEHDRFULL0) +#define G_T7_ENABLEHDRFULL0(x) (((x) >> S_T7_ENABLEHDRFULL0) & M_T7_ENABLEHDRFULL0) + +#define A_TP_RX_SCHED_MOD_CH3_CH2 0x1e + +#define S_ENABLELPBKFULL3 28 +#define M_ENABLELPBKFULL3 0xfU +#define V_ENABLELPBKFULL3(x) ((x) << S_ENABLELPBKFULL3) +#define G_ENABLELPBKFULL3(x) (((x) >> S_ENABLELPBKFULL3) & M_ENABLELPBKFULL3) + +#define S_ENABLEFIFOFULL3 24 +#define M_ENABLEFIFOFULL3 0xfU +#define V_ENABLEFIFOFULL3(x) ((x) << S_ENABLEFIFOFULL3) +#define G_ENABLEFIFOFULL3(x) (((x) >> S_ENABLEFIFOFULL3) & M_ENABLEFIFOFULL3) + +#define S_ENABLEPCMDFULL3 20 +#define M_ENABLEPCMDFULL3 0xfU +#define V_ENABLEPCMDFULL3(x) ((x) << S_ENABLEPCMDFULL3) +#define G_ENABLEPCMDFULL3(x) (((x) >> S_ENABLEPCMDFULL3) & M_ENABLEPCMDFULL3) + +#define S_ENABLEHDRFULL3 16 +#define M_ENABLEHDRFULL3 0xfU +#define V_ENABLEHDRFULL3(x) ((x) << S_ENABLEHDRFULL3) +#define G_ENABLEHDRFULL3(x) (((x) >> S_ENABLEHDRFULL3) & M_ENABLEHDRFULL3) + +#define S_ENABLELPBKFULL2 12 +#define M_ENABLELPBKFULL2 0xfU +#define V_ENABLELPBKFULL2(x) ((x) << S_ENABLELPBKFULL2) +#define G_ENABLELPBKFULL2(x) (((x) >> S_ENABLELPBKFULL2) & M_ENABLELPBKFULL2) + +#define S_ENABLEFIFOFULL2 8 +#define M_ENABLEFIFOFULL2 0xfU +#define V_ENABLEFIFOFULL2(x) ((x) << S_ENABLEFIFOFULL2) +#define G_ENABLEFIFOFULL2(x) (((x) >> S_ENABLEFIFOFULL2) & M_ENABLEFIFOFULL2) + +#define S_ENABLEPCMDFULL2 4 +#define M_ENABLEPCMDFULL2 0xfU +#define V_ENABLEPCMDFULL2(x) ((x) << S_ENABLEPCMDFULL2) +#define G_ENABLEPCMDFULL2(x) (((x) >> S_ENABLEPCMDFULL2) & M_ENABLEPCMDFULL2) + +#define S_ENABLEHDRFULL2 0 +#define M_ENABLEHDRFULL2 0xfU +#define V_ENABLEHDRFULL2(x) ((x) << S_ENABLEHDRFULL2) +#define G_ENABLEHDRFULL2(x) (((x) >> S_ENABLEHDRFULL2) & M_ENABLEHDRFULL2) + +#define A_TP_RX_SCHED_MAP_CH3_CH2 0x1f + +#define S_T7_RXMAPCHANNEL3 16 +#define M_T7_RXMAPCHANNEL3 0xffffU +#define V_T7_RXMAPCHANNEL3(x) ((x) << S_T7_RXMAPCHANNEL3) +#define G_T7_RXMAPCHANNEL3(x) (((x) >> S_T7_RXMAPCHANNEL3) & M_T7_RXMAPCHANNEL3) + +#define S_T7_RXMAPCHANNEL2 0 +#define M_T7_RXMAPCHANNEL2 0xffffU +#define V_T7_RXMAPCHANNEL2(x) ((x) << S_T7_RXMAPCHANNEL2) +#define G_T7_RXMAPCHANNEL2(x) (((x) >> S_T7_RXMAPCHANNEL2) & M_T7_RXMAPCHANNEL2) + #define A_TP_RX_SCHED_MAP 0x20 #define S_RXMAPCHANNEL3 24 @@ -24542,6 +30934,16 @@ #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0) #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0) +#define S_T7_RXMAPCHANNEL1 16 +#define M_T7_RXMAPCHANNEL1 0xffffU +#define V_T7_RXMAPCHANNEL1(x) ((x) << S_T7_RXMAPCHANNEL1) +#define G_T7_RXMAPCHANNEL1(x) (((x) >> S_T7_RXMAPCHANNEL1) & M_T7_RXMAPCHANNEL1) + +#define S_T7_RXMAPCHANNEL0 0 +#define M_T7_RXMAPCHANNEL0 0xffffU +#define V_T7_RXMAPCHANNEL0(x) ((x) << S_T7_RXMAPCHANNEL0) +#define G_T7_RXMAPCHANNEL0(x) (((x) >> S_T7_RXMAPCHANNEL0) & M_T7_RXMAPCHANNEL0) + #define A_TP_RX_SCHED_SGE 0x21 #define S_RXSGEMOD1 12 @@ -24570,6 +30972,16 @@ #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0) #define F_RXSGECHANNEL0 V_RXSGECHANNEL0(1U) +#define S_RXSGEMOD3 20 +#define M_RXSGEMOD3 0xfU +#define V_RXSGEMOD3(x) ((x) << S_RXSGEMOD3) +#define G_RXSGEMOD3(x) (((x) >> S_RXSGEMOD3) & M_RXSGEMOD3) + +#define S_RXSGEMOD2 16 +#define M_RXSGEMOD2 0xfU +#define V_RXSGEMOD2(x) ((x) << S_RXSGEMOD2) +#define G_RXSGEMOD2(x) (((x) >> S_RXSGEMOD2) & M_RXSGEMOD2) + #define A_TP_TX_SCHED_MAP 0x22 #define S_TXMAPCHANNEL3 12 @@ -24600,6 +31012,14 @@ #define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0) #define F_TXLPKCHANNEL0 V_TXLPKCHANNEL0(1U) +#define S_TXLPKCHANNEL3 19 +#define V_TXLPKCHANNEL3(x) ((x) << S_TXLPKCHANNEL3) +#define F_TXLPKCHANNEL3 V_TXLPKCHANNEL3(1U) + +#define S_TXLPKCHANNEL2 18 +#define V_TXLPKCHANNEL2(x) ((x) << S_TXLPKCHANNEL2) +#define F_TXLPKCHANNEL2 V_TXLPKCHANNEL2(1U) + #define A_TP_TX_SCHED_HDR 0x23 #define S_TXMAPHDRCHANNEL7 28 @@ -24827,6 +31247,69 @@ #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0) #define F_RXMAPE2CCHANNEL0 V_RXMAPE2CCHANNEL0(1U) +#define S_T7_LB_MODE 30 +#define M_T7_LB_MODE 0x3U +#define V_T7_LB_MODE(x) ((x) << S_T7_LB_MODE) +#define G_T7_LB_MODE(x) (((x) >> S_T7_LB_MODE) & M_T7_LB_MODE) + +#define S_ING_LB_MODE 28 +#define M_ING_LB_MODE 0x3U +#define V_ING_LB_MODE(x) ((x) << S_ING_LB_MODE) +#define G_ING_LB_MODE(x) (((x) >> S_ING_LB_MODE) & M_ING_LB_MODE) + +#define S_RXC_LB_MODE 26 +#define M_RXC_LB_MODE 0x3U +#define V_RXC_LB_MODE(x) ((x) << S_RXC_LB_MODE) +#define G_RXC_LB_MODE(x) (((x) >> S_RXC_LB_MODE) & M_RXC_LB_MODE) + +#define S_SINGLERXCHANNEL 25 +#define V_SINGLERXCHANNEL(x) ((x) << S_SINGLERXCHANNEL) +#define F_SINGLERXCHANNEL V_SINGLERXCHANNEL(1U) + +#define S_RXCHANNELCHECK 24 +#define V_RXCHANNELCHECK(x) ((x) << S_RXCHANNELCHECK) +#define F_RXCHANNELCHECK V_RXCHANNELCHECK(1U) + +#define S_T7_RXMAPC2CCHANNEL3 21 +#define M_T7_RXMAPC2CCHANNEL3 0x7U +#define V_T7_RXMAPC2CCHANNEL3(x) ((x) << S_T7_RXMAPC2CCHANNEL3) +#define G_T7_RXMAPC2CCHANNEL3(x) (((x) >> S_T7_RXMAPC2CCHANNEL3) & M_T7_RXMAPC2CCHANNEL3) + +#define S_T7_RXMAPC2CCHANNEL2 18 +#define M_T7_RXMAPC2CCHANNEL2 0x7U +#define V_T7_RXMAPC2CCHANNEL2(x) ((x) << S_T7_RXMAPC2CCHANNEL2) +#define G_T7_RXMAPC2CCHANNEL2(x) (((x) >> S_T7_RXMAPC2CCHANNEL2) & M_T7_RXMAPC2CCHANNEL2) + +#define S_T7_RXMAPC2CCHANNEL1 15 +#define M_T7_RXMAPC2CCHANNEL1 0x7U +#define V_T7_RXMAPC2CCHANNEL1(x) ((x) << S_T7_RXMAPC2CCHANNEL1) +#define G_T7_RXMAPC2CCHANNEL1(x) (((x) >> S_T7_RXMAPC2CCHANNEL1) & M_T7_RXMAPC2CCHANNEL1) + +#define S_T7_RXMAPC2CCHANNEL0 12 +#define M_T7_RXMAPC2CCHANNEL0 0x7U +#define V_T7_RXMAPC2CCHANNEL0(x) ((x) << S_T7_RXMAPC2CCHANNEL0) +#define G_T7_RXMAPC2CCHANNEL0(x) (((x) >> S_T7_RXMAPC2CCHANNEL0) & M_T7_RXMAPC2CCHANNEL0) + +#define S_T7_RXMAPE2CCHANNEL3 9 +#define M_T7_RXMAPE2CCHANNEL3 0x7U +#define V_T7_RXMAPE2CCHANNEL3(x) ((x) << S_T7_RXMAPE2CCHANNEL3) +#define G_T7_RXMAPE2CCHANNEL3(x) (((x) >> S_T7_RXMAPE2CCHANNEL3) & M_T7_RXMAPE2CCHANNEL3) + +#define S_T7_RXMAPE2CCHANNEL2 6 +#define M_T7_RXMAPE2CCHANNEL2 0x7U +#define V_T7_RXMAPE2CCHANNEL2(x) ((x) << S_T7_RXMAPE2CCHANNEL2) +#define G_T7_RXMAPE2CCHANNEL2(x) (((x) >> S_T7_RXMAPE2CCHANNEL2) & M_T7_RXMAPE2CCHANNEL2) + +#define S_T7_RXMAPE2CCHANNEL1 3 +#define M_T7_RXMAPE2CCHANNEL1 0x7U +#define V_T7_RXMAPE2CCHANNEL1(x) ((x) << S_T7_RXMAPE2CCHANNEL1) +#define G_T7_RXMAPE2CCHANNEL1(x) (((x) >> S_T7_RXMAPE2CCHANNEL1) & M_T7_RXMAPE2CCHANNEL1) + +#define S_T7_RXMAPE2CCHANNEL0 0 +#define M_T7_RXMAPE2CCHANNEL0 0x7U +#define V_T7_RXMAPE2CCHANNEL0(x) ((x) << S_T7_RXMAPE2CCHANNEL0) +#define G_T7_RXMAPE2CCHANNEL0(x) (((x) >> S_T7_RXMAPE2CCHANNEL0) & M_T7_RXMAPE2CCHANNEL0) + #define A_TP_RX_LPBK 0x28 #define A_TP_TX_LPBK 0x29 #define A_TP_TX_SCHED_PPP 0x2a @@ -24873,6 +31356,55 @@ #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L) #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L) +#define A_TP_RX_SCHED_FIFO_CH3_CH2 0x2c + +#define S_COMMITLIMIT3H 24 +#define M_COMMITLIMIT3H 0xffU +#define V_COMMITLIMIT3H(x) ((x) << S_COMMITLIMIT3H) +#define G_COMMITLIMIT3H(x) (((x) >> S_COMMITLIMIT3H) & M_COMMITLIMIT3H) + +#define S_COMMITLIMIT3L 16 +#define M_COMMITLIMIT3L 0xffU +#define V_COMMITLIMIT3L(x) ((x) << S_COMMITLIMIT3L) +#define G_COMMITLIMIT3L(x) (((x) >> S_COMMITLIMIT3L) & M_COMMITLIMIT3L) + +#define S_COMMITLIMIT2H 8 +#define M_COMMITLIMIT2H 0xffU +#define V_COMMITLIMIT2H(x) ((x) << S_COMMITLIMIT2H) +#define G_COMMITLIMIT2H(x) (((x) >> S_COMMITLIMIT2H) & M_COMMITLIMIT2H) + +#define S_COMMITLIMIT2L 0 +#define M_COMMITLIMIT2L 0xffU +#define V_COMMITLIMIT2L(x) ((x) << S_COMMITLIMIT2L) +#define G_COMMITLIMIT2L(x) (((x) >> S_COMMITLIMIT2L) & M_COMMITLIMIT2L) + +#define A_TP_CHANNEL_MAP_LPBK 0x2d + +#define S_T7_RXMAPCHANNELELN 12 +#define M_T7_RXMAPCHANNELELN 0xfU +#define V_T7_RXMAPCHANNELELN(x) ((x) << S_T7_RXMAPCHANNELELN) +#define G_T7_RXMAPCHANNELELN(x) (((x) >> S_T7_RXMAPCHANNELELN) & M_T7_RXMAPCHANNELELN) + +#define S_T7_RXMAPE2LCHANNEL3 9 +#define M_T7_RXMAPE2LCHANNEL3 0x7U +#define V_T7_RXMAPE2LCHANNEL3(x) ((x) << S_T7_RXMAPE2LCHANNEL3) +#define G_T7_RXMAPE2LCHANNEL3(x) (((x) >> S_T7_RXMAPE2LCHANNEL3) & M_T7_RXMAPE2LCHANNEL3) + +#define S_T7_RXMAPE2LCHANNEL2 6 +#define M_T7_RXMAPE2LCHANNEL2 0x7U +#define V_T7_RXMAPE2LCHANNEL2(x) ((x) << S_T7_RXMAPE2LCHANNEL2) +#define G_T7_RXMAPE2LCHANNEL2(x) (((x) >> S_T7_RXMAPE2LCHANNEL2) & M_T7_RXMAPE2LCHANNEL2) + +#define S_T7_RXMAPE2LCHANNEL1 3 +#define M_T7_RXMAPE2LCHANNEL1 0x7U +#define V_T7_RXMAPE2LCHANNEL1(x) ((x) << S_T7_RXMAPE2LCHANNEL1) +#define G_T7_RXMAPE2LCHANNEL1(x) (((x) >> S_T7_RXMAPE2LCHANNEL1) & M_T7_RXMAPE2LCHANNEL1) + +#define S_T7_RXMAPE2LCHANNEL0 0 +#define M_T7_RXMAPE2LCHANNEL0 0x7U +#define V_T7_RXMAPE2LCHANNEL0(x) ((x) << S_T7_RXMAPE2LCHANNEL0) +#define G_T7_RXMAPE2LCHANNEL0(x) (((x) >> S_T7_RXMAPE2LCHANNEL0) & M_T7_RXMAPE2LCHANNEL0) + #define A_TP_IPMI_CFG1 0x2e #define S_VLANENABLE 31 @@ -24966,47 +31498,12 @@ #define F_T6_CHNENABLE V_T6_CHNENABLE(1U) #define A_TP_RSS_PF1_CONFIG 0x31 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF2_CONFIG 0x32 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF3_CONFIG 0x33 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF4_CONFIG 0x34 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF5_CONFIG 0x35 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF6_CONFIG 0x36 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF7_CONFIG 0x37 - -#define S_T6_CHNENABLE 29 -#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE) -#define F_T6_CHNENABLE V_T6_CHNENABLE(1U) - #define A_TP_RSS_PF_MAP 0x38 #define S_LKPIDXSIZE 24 @@ -25097,6 +31594,22 @@ #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE) #define A_TP_RSS_VFL_CONFIG 0x3a + +#define S_BASEQID 16 +#define M_BASEQID 0xfffU +#define V_BASEQID(x) ((x) << S_BASEQID) +#define G_BASEQID(x) (((x) >> S_BASEQID) & M_BASEQID) + +#define S_MAXRRQID 8 +#define M_MAXRRQID 0xffU +#define V_MAXRRQID(x) ((x) << S_MAXRRQID) +#define G_MAXRRQID(x) (((x) >> S_MAXRRQID) & M_MAXRRQID) + +#define S_RRCOUNTER 0 +#define M_RRCOUNTER 0xffU +#define V_RRCOUNTER(x) ((x) << S_RRCOUNTER) +#define G_RRCOUNTER(x) (((x) >> S_RRCOUNTER) & M_RRCOUNTER) + #define A_TP_RSS_VFH_CONFIG 0x3b #define S_ENABLEUDPHASH 31 @@ -25150,6 +31663,10 @@ #define V_KEYINDEX(x) ((x) << S_KEYINDEX) #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX) +#define S_ROUNDROBINEN 3 +#define V_ROUNDROBINEN(x) ((x) << S_ROUNDROBINEN) +#define F_ROUNDROBINEN V_ROUNDROBINEN(1U) + #define A_TP_RSS_SECRET_KEY0 0x40 #define A_TP_RSS_SECRET_KEY1 0x41 #define A_TP_RSS_SECRET_KEY2 0x42 @@ -25283,6 +31800,36 @@ #define V_SHAREDXRC(x) ((x) << S_SHAREDXRC) #define F_SHAREDXRC V_SHAREDXRC(1U) +#define S_VERIFYRSPOP 25 +#define M_VERIFYRSPOP 0x1fU +#define V_VERIFYRSPOP(x) ((x) << S_VERIFYRSPOP) +#define G_VERIFYRSPOP(x) (((x) >> S_VERIFYRSPOP) & M_VERIFYRSPOP) + +#define S_VERIFYREQOP 20 +#define M_VERIFYREQOP 0x1fU +#define V_VERIFYREQOP(x) ((x) << S_VERIFYREQOP) +#define G_VERIFYREQOP(x) (((x) >> S_VERIFYREQOP) & M_VERIFYREQOP) + +#define S_AWRITERSPOP 15 +#define M_AWRITERSPOP 0x1fU +#define V_AWRITERSPOP(x) ((x) << S_AWRITERSPOP) +#define G_AWRITERSPOP(x) (((x) >> S_AWRITERSPOP) & M_AWRITERSPOP) + +#define S_AWRITEREQOP 10 +#define M_AWRITEREQOP 0x1fU +#define V_AWRITEREQOP(x) ((x) << S_AWRITEREQOP) +#define G_AWRITEREQOP(x) (((x) >> S_AWRITEREQOP) & M_AWRITEREQOP) + +#define S_FLUSHRSPOP 5 +#define M_FLUSHRSPOP 0x1fU +#define V_FLUSHRSPOP(x) ((x) << S_FLUSHRSPOP) +#define G_FLUSHRSPOP(x) (((x) >> S_FLUSHRSPOP) & M_FLUSHRSPOP) + +#define S_FLUSHREQOP 0 +#define M_FLUSHREQOP 0x1fU +#define V_FLUSHREQOP(x) ((x) << S_FLUSHREQOP) +#define G_FLUSHREQOP(x) (((x) >> S_FLUSHREQOP) & M_FLUSHREQOP) + #define A_TP_FRAG_CONFIG 0x56 #define S_TLSMODE 16 @@ -25330,6 +31877,21 @@ #define V_PASSMODE(x) ((x) << S_PASSMODE) #define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE) +#define S_NVMTMODE 22 +#define M_NVMTMODE 0x3U +#define V_NVMTMODE(x) ((x) << S_NVMTMODE) +#define G_NVMTMODE(x) (((x) >> S_NVMTMODE) & M_NVMTMODE) + +#define S_ROCEMODE 20 +#define M_ROCEMODE 0x3U +#define V_ROCEMODE(x) ((x) << S_ROCEMODE) +#define G_ROCEMODE(x) (((x) >> S_ROCEMODE) & M_ROCEMODE) + +#define S_DTLSMODE 18 +#define M_DTLSMODE 0x3U +#define V_DTLSMODE(x) ((x) << S_DTLSMODE) +#define G_DTLSMODE(x) (((x) >> S_DTLSMODE) & M_DTLSMODE) + #define A_TP_CMM_CONFIG 0x57 #define S_WRCNTIDLE 16 @@ -25383,6 +31945,7 @@ #define V_GRETYPE(x) ((x) << S_GRETYPE) #define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE) +#define A_TP_MMGR_CMM_CONFIG 0x5a #define A_TP_DBG_CLEAR 0x60 #define A_TP_DBG_CORE_HDR0 0x61 @@ -25843,14 +32406,6 @@ #define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY) #define F_T5_EPCMDBUSY V_T5_EPCMDBUSY(1U) -#define S_T6_ETXBUSY 1 -#define V_T6_ETXBUSY(x) ((x) << S_T6_ETXBUSY) -#define F_T6_ETXBUSY V_T6_ETXBUSY(1U) - -#define S_T6_EPCMDBUSY 0 -#define V_T6_EPCMDBUSY(x) ((x) << S_T6_EPCMDBUSY) -#define F_T6_EPCMDBUSY V_T6_EPCMDBUSY(1U) - #define A_TP_DBG_ENG_RES1 0x67 #define S_RXCPLSRDY 31 @@ -26114,16 +32669,6 @@ #define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG) #define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG) -#define S_T6_RXFIFOCNG 20 -#define M_T6_RXFIFOCNG 0xfU -#define V_T6_RXFIFOCNG(x) ((x) << S_T6_RXFIFOCNG) -#define G_T6_RXFIFOCNG(x) (((x) >> S_T6_RXFIFOCNG) & M_T6_RXFIFOCNG) - -#define S_T6_RXPCMDCNG 14 -#define M_T6_RXPCMDCNG 0x3U -#define V_T6_RXPCMDCNG(x) ((x) << S_T6_RXPCMDCNG) -#define G_T6_RXPCMDCNG(x) (((x) >> S_T6_RXPCMDCNG) & M_T6_RXPCMDCNG) - #define A_TP_DBG_ERROR_CNT 0x6c #define A_TP_DBG_CORE_CPL 0x6d @@ -26191,6 +32736,244 @@ #define A_TP_DBG_CACHE_RD_HIT 0x73 #define A_TP_DBG_CACHE_MC_REQ 0x74 #define A_TP_DBG_CACHE_MC_RSP 0x75 +#define A_TP_RSS_PF0_CONFIG_CH3_CH2 0x80 + +#define S_PFMAPALWAYS 22 +#define V_PFMAPALWAYS(x) ((x) << S_PFMAPALWAYS) +#define F_PFMAPALWAYS V_PFMAPALWAYS(1U) + +#define S_PFROUNDROBINEN 21 +#define V_PFROUNDROBINEN(x) ((x) << S_PFROUNDROBINEN) +#define F_PFROUNDROBINEN V_PFROUNDROBINEN(1U) + +#define S_FOURCHNEN 20 +#define V_FOURCHNEN(x) ((x) << S_FOURCHNEN) +#define F_FOURCHNEN V_FOURCHNEN(1U) + +#define S_CH3DEFAULTQUEUE 10 +#define M_CH3DEFAULTQUEUE 0x3ffU +#define V_CH3DEFAULTQUEUE(x) ((x) << S_CH3DEFAULTQUEUE) +#define G_CH3DEFAULTQUEUE(x) (((x) >> S_CH3DEFAULTQUEUE) & M_CH3DEFAULTQUEUE) + +#define S_CH2DEFAULTQUEUE 0 +#define M_CH2DEFAULTQUEUE 0x3ffU +#define V_CH2DEFAULTQUEUE(x) ((x) << S_CH2DEFAULTQUEUE) +#define G_CH2DEFAULTQUEUE(x) (((x) >> S_CH2DEFAULTQUEUE) & M_CH2DEFAULTQUEUE) + +#define A_TP_RSS_PF1_CONFIG_CH3_CH2 0x81 +#define A_TP_RSS_PF2_CONFIG_CH3_CH2 0x82 +#define A_TP_RSS_PF3_CONFIG_CH3_CH2 0x83 +#define A_TP_RSS_PF4_CONFIG_CH3_CH2 0x84 +#define A_TP_RSS_PF5_CONFIG_CH3_CH2 0x85 +#define A_TP_RSS_PF6_CONFIG_CH3_CH2 0x86 +#define A_TP_RSS_PF7_CONFIG_CH3_CH2 0x87 +#define A_TP_RSS_PF0_EXT_CONFIG 0x88 +#define A_TP_RSS_PF1_EXT_CONFIG 0x89 +#define A_TP_RSS_PF2_EXT_CONFIG 0x8a +#define A_TP_RSS_PF3_EXT_CONFIG 0x8b +#define A_TP_RSS_PF4_EXT_CONFIG 0x8c +#define A_TP_RSS_PF5_EXT_CONFIG 0x8d +#define A_TP_RSS_PF6_EXT_CONFIG 0x8e +#define A_TP_RSS_PF7_EXT_CONFIG 0x8f +#define A_TP_ROCE_CONFIG 0x90 + +#define S_IGNAETHMSB 24 +#define V_IGNAETHMSB(x) ((x) << S_IGNAETHMSB) +#define F_IGNAETHMSB V_IGNAETHMSB(1U) + +#define S_XDIDMMCTL 23 +#define V_XDIDMMCTL(x) ((x) << S_XDIDMMCTL) +#define F_XDIDMMCTL V_XDIDMMCTL(1U) + +#define S_WRRETHDBGFWDEN 22 +#define V_WRRETHDBGFWDEN(x) ((x) << S_WRRETHDBGFWDEN) +#define F_WRRETHDBGFWDEN V_WRRETHDBGFWDEN(1U) + +#define S_ACKINTGENCTRL 20 +#define M_ACKINTGENCTRL 0x3U +#define V_ACKINTGENCTRL(x) ((x) << S_ACKINTGENCTRL) +#define G_ACKINTGENCTRL(x) (((x) >> S_ACKINTGENCTRL) & M_ACKINTGENCTRL) + +#define S_ATOMICALIGNCHKEN 19 +#define V_ATOMICALIGNCHKEN(x) ((x) << S_ATOMICALIGNCHKEN) +#define F_ATOMICALIGNCHKEN V_ATOMICALIGNCHKEN(1U) + +#define S_RDRETHLENCHKEN 18 +#define V_RDRETHLENCHKEN(x) ((x) << S_RDRETHLENCHKEN) +#define F_RDRETHLENCHKEN V_RDRETHLENCHKEN(1U) + +#define S_WRTOTALLENCHKEN 17 +#define V_WRTOTALLENCHKEN(x) ((x) << S_WRTOTALLENCHKEN) +#define F_WRTOTALLENCHKEN V_WRTOTALLENCHKEN(1U) + +#define S_WRRETHLENCHKEN 16 +#define V_WRRETHLENCHKEN(x) ((x) << S_WRRETHLENCHKEN) +#define F_WRRETHLENCHKEN V_WRRETHLENCHKEN(1U) + +#define S_TNLERRORUDPLEN 11 +#define V_TNLERRORUDPLEN(x) ((x) << S_TNLERRORUDPLEN) +#define F_TNLERRORUDPLEN V_TNLERRORUDPLEN(1U) + +#define S_TNLERRORPKEY 10 +#define V_TNLERRORPKEY(x) ((x) << S_TNLERRORPKEY) +#define F_TNLERRORPKEY V_TNLERRORPKEY(1U) + +#define S_TNLERROROPCODE 9 +#define V_TNLERROROPCODE(x) ((x) << S_TNLERROROPCODE) +#define F_TNLERROROPCODE V_TNLERROROPCODE(1U) + +#define S_TNLERRORTVER 8 +#define V_TNLERRORTVER(x) ((x) << S_TNLERRORTVER) +#define F_TNLERRORTVER V_TNLERRORTVER(1U) + +#define S_DROPERRORUDPLEN 3 +#define V_DROPERRORUDPLEN(x) ((x) << S_DROPERRORUDPLEN) +#define F_DROPERRORUDPLEN V_DROPERRORUDPLEN(1U) + +#define S_DROPERRORPKEY 2 +#define V_DROPERRORPKEY(x) ((x) << S_DROPERRORPKEY) +#define F_DROPERRORPKEY V_DROPERRORPKEY(1U) + +#define S_DROPERROROPCODE 1 +#define V_DROPERROROPCODE(x) ((x) << S_DROPERROROPCODE) +#define F_DROPERROROPCODE V_DROPERROROPCODE(1U) + +#define S_DROPERRORTVER 0 +#define V_DROPERRORTVER(x) ((x) << S_DROPERRORTVER) +#define F_DROPERRORTVER V_DROPERRORTVER(1U) + +#define A_TP_NVMT_CONFIG 0x91 + +#define S_PDACHKEN 2 +#define V_PDACHKEN(x) ((x) << S_PDACHKEN) +#define F_PDACHKEN V_PDACHKEN(1U) + +#define S_FORCERQNONDDP 1 +#define V_FORCERQNONDDP(x) ((x) << S_FORCERQNONDDP) +#define F_FORCERQNONDDP V_FORCERQNONDDP(1U) + +#define S_STRIPHCRC 0 +#define V_STRIPHCRC(x) ((x) << S_STRIPHCRC) +#define F_STRIPHCRC V_STRIPHCRC(1U) + +#define A_TP_NVMT_MAXHDR 0x92 + +#define S_MAXHDR3 24 +#define M_MAXHDR3 0xffU +#define V_MAXHDR3(x) ((x) << S_MAXHDR3) +#define G_MAXHDR3(x) (((x) >> S_MAXHDR3) & M_MAXHDR3) + +#define S_MAXHDR2 16 +#define M_MAXHDR2 0xffU +#define V_MAXHDR2(x) ((x) << S_MAXHDR2) +#define G_MAXHDR2(x) (((x) >> S_MAXHDR2) & M_MAXHDR2) + +#define S_MAXHDR1 8 +#define M_MAXHDR1 0xffU +#define V_MAXHDR1(x) ((x) << S_MAXHDR1) +#define G_MAXHDR1(x) (((x) >> S_MAXHDR1) & M_MAXHDR1) + +#define S_MAXHDR0 0 +#define M_MAXHDR0 0xffU +#define V_MAXHDR0(x) ((x) << S_MAXHDR0) +#define G_MAXHDR0(x) (((x) >> S_MAXHDR0) & M_MAXHDR0) + +#define A_TP_NVMT_PDORSVD 0x93 + +#define S_PDORSVD3 24 +#define M_PDORSVD3 0xffU +#define V_PDORSVD3(x) ((x) << S_PDORSVD3) +#define G_PDORSVD3(x) (((x) >> S_PDORSVD3) & M_PDORSVD3) + +#define S_PDORSVD2 16 +#define M_PDORSVD2 0xffU +#define V_PDORSVD2(x) ((x) << S_PDORSVD2) +#define G_PDORSVD2(x) (((x) >> S_PDORSVD2) & M_PDORSVD2) + +#define S_PDORSVD1 8 +#define M_PDORSVD1 0xffU +#define V_PDORSVD1(x) ((x) << S_PDORSVD1) +#define G_PDORSVD1(x) (((x) >> S_PDORSVD1) & M_PDORSVD1) + +#define S_PDORSVD0 0 +#define M_PDORSVD0 0xffU +#define V_PDORSVD0(x) ((x) << S_PDORSVD0) +#define G_PDORSVD0(x) (((x) >> S_PDORSVD0) & M_PDORSVD0) + +#define A_TP_RDMA_CONFIG 0x94 + +#define S_SRQLIMITEN 20 +#define V_SRQLIMITEN(x) ((x) << S_SRQLIMITEN) +#define F_SRQLIMITEN V_SRQLIMITEN(1U) + +#define S_SNDIMMSEOP 15 +#define M_SNDIMMSEOP 0x1fU +#define V_SNDIMMSEOP(x) ((x) << S_SNDIMMSEOP) +#define G_SNDIMMSEOP(x) (((x) >> S_SNDIMMSEOP) & M_SNDIMMSEOP) + +#define S_SNDIMMOP 10 +#define M_SNDIMMOP 0x1fU +#define V_SNDIMMOP(x) ((x) << S_SNDIMMOP) +#define G_SNDIMMOP(x) (((x) >> S_SNDIMMOP) & M_SNDIMMOP) + +#define S_IWARPXRCIDCHKEN 4 +#define V_IWARPXRCIDCHKEN(x) ((x) << S_IWARPXRCIDCHKEN) +#define F_IWARPXRCIDCHKEN V_IWARPXRCIDCHKEN(1U) + +#define S_IWARPEXTOPEN 3 +#define V_IWARPEXTOPEN(x) ((x) << S_IWARPEXTOPEN) +#define F_IWARPEXTOPEN V_IWARPEXTOPEN(1U) + +#define S_XRCIMPLTYPE 1 +#define V_XRCIMPLTYPE(x) ((x) << S_XRCIMPLTYPE) +#define F_XRCIMPLTYPE V_XRCIMPLTYPE(1U) + +#define S_XRCEN 0 +#define V_XRCEN(x) ((x) << S_XRCEN) +#define F_XRCEN V_XRCEN(1U) + +#define A_TP_ROCE_RRQ_BASE 0x95 +#define A_TP_FILTER_RATE_CFG 0x96 + +#define S_GRP_CFG_RD 30 +#define V_GRP_CFG_RD(x) ((x) << S_GRP_CFG_RD) +#define F_GRP_CFG_RD V_GRP_CFG_RD(1U) + +#define S_GRP_CFG_INIT 29 +#define V_GRP_CFG_INIT(x) ((x) << S_GRP_CFG_INIT) +#define F_GRP_CFG_INIT V_GRP_CFG_INIT(1U) + +#define S_GRP_CFG_RST 28 +#define V_GRP_CFG_RST(x) ((x) << S_GRP_CFG_RST) +#define F_GRP_CFG_RST V_GRP_CFG_RST(1U) + +#define S_GRP_CFG_SEL 16 +#define M_GRP_CFG_SEL 0xfffU +#define V_GRP_CFG_SEL(x) ((x) << S_GRP_CFG_SEL) +#define G_GRP_CFG_SEL(x) (((x) >> S_GRP_CFG_SEL) & M_GRP_CFG_SEL) + +#define S_US_TIMER_TICK 0 +#define M_US_TIMER_TICK 0xffffU +#define V_US_TIMER_TICK(x) ((x) << S_US_TIMER_TICK) +#define G_US_TIMER_TICK(x) (((x) >> S_US_TIMER_TICK) & M_US_TIMER_TICK) + +#define A_TP_TLS_CONFIG 0x99 + +#define S_QUIESCETYPE1 24 +#define M_QUIESCETYPE1 0xffU +#define V_QUIESCETYPE1(x) ((x) << S_QUIESCETYPE1) +#define G_QUIESCETYPE1(x) (((x) >> S_QUIESCETYPE1) & M_QUIESCETYPE1) + +#define S_QUIESCETYPE2 16 +#define M_QUIESCETYPE2 0xffU +#define V_QUIESCETYPE2(x) ((x) << S_QUIESCETYPE2) +#define G_QUIESCETYPE2(x) (((x) >> S_QUIESCETYPE2) & M_QUIESCETYPE2) + +#define S_QUIESCETYPE3 8 +#define M_QUIESCETYPE3 0xffU +#define V_QUIESCETYPE3(x) ((x) << S_QUIESCETYPE3) +#define G_QUIESCETYPE3(x) (((x) >> S_QUIESCETYPE3) & M_QUIESCETYPE3) + #define A_TP_T5_TX_DROP_CNT_CH0 0x120 #define A_TP_T5_TX_DROP_CNT_CH1 0x121 #define A_TP_TX_DROP_CNT_CH2 0x122 @@ -26682,10 +33465,6 @@ #define A_TP_DBG_ESIDE_DISP1 0x137 -#define S_T6_ESTATIC4 12 -#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4) -#define F_T6_ESTATIC4 V_T6_ESTATIC4(1U) - #define S_TXFULL_ESIDE1 0 #define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1) #define F_TXFULL_ESIDE1 V_TXFULL_ESIDE1(1U) @@ -26719,20 +33498,12 @@ #define A_TP_DBG_ESIDE_DISP2 0x13a -#define S_T6_ESTATIC4 12 -#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4) -#define F_T6_ESTATIC4 V_T6_ESTATIC4(1U) - #define S_TXFULL_ESIDE2 0 #define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2) #define F_TXFULL_ESIDE2 V_TXFULL_ESIDE2(1U) #define A_TP_DBG_ESIDE_DISP3 0x13b -#define S_T6_ESTATIC4 12 -#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4) -#define F_T6_ESTATIC4 V_T6_ESTATIC4(1U) - #define S_TXFULL_ESIDE3 0 #define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3) #define F_TXFULL_ESIDE3 V_TXFULL_ESIDE3(1U) @@ -26836,6 +33607,94 @@ #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM) #define F_SRVRSRAM V_SRVRSRAM(1U) +#define S_T7_FILTERMODE 31 +#define V_T7_FILTERMODE(x) ((x) << S_T7_FILTERMODE) +#define F_T7_FILTERMODE V_T7_FILTERMODE(1U) + +#define S_T7_FCOEMASK 30 +#define V_T7_FCOEMASK(x) ((x) << S_T7_FCOEMASK) +#define F_T7_FCOEMASK V_T7_FCOEMASK(1U) + +#define S_T7_SRVRSRAM 29 +#define V_T7_SRVRSRAM(x) ((x) << S_T7_SRVRSRAM) +#define F_T7_SRVRSRAM V_T7_SRVRSRAM(1U) + +#define S_ROCEUDFORCEIPV6 28 +#define V_ROCEUDFORCEIPV6(x) ((x) << S_ROCEUDFORCEIPV6) +#define F_ROCEUDFORCEIPV6 V_ROCEUDFORCEIPV6(1U) + +#define S_TCPFLAGS8 27 +#define V_TCPFLAGS8(x) ((x) << S_TCPFLAGS8) +#define F_TCPFLAGS8 V_TCPFLAGS8(1U) + +#define S_MACMATCH11 26 +#define V_MACMATCH11(x) ((x) << S_MACMATCH11) +#define F_MACMATCH11 V_MACMATCH11(1U) + +#define S_SMACMATCH10 25 +#define V_SMACMATCH10(x) ((x) << S_SMACMATCH10) +#define F_SMACMATCH10 V_SMACMATCH10(1U) + +#define S_SMACMATCH 14 +#define V_SMACMATCH(x) ((x) << S_SMACMATCH) +#define F_SMACMATCH V_SMACMATCH(1U) + +#define S_TCPFLAGS 13 +#define V_TCPFLAGS(x) ((x) << S_TCPFLAGS) +#define F_TCPFLAGS V_TCPFLAGS(1U) + +#define S_SYNONLY 12 +#define V_SYNONLY(x) ((x) << S_SYNONLY) +#define F_SYNONLY V_SYNONLY(1U) + +#define S_ROCE 11 +#define V_ROCE(x) ((x) << S_ROCE) +#define F_ROCE V_ROCE(1U) + +#define S_T7_FRAGMENTATION 10 +#define V_T7_FRAGMENTATION(x) ((x) << S_T7_FRAGMENTATION) +#define F_T7_FRAGMENTATION V_T7_FRAGMENTATION(1U) + +#define S_T7_MPSHITTYPE 9 +#define V_T7_MPSHITTYPE(x) ((x) << S_T7_MPSHITTYPE) +#define F_T7_MPSHITTYPE V_T7_MPSHITTYPE(1U) + +#define S_T7_MACMATCH 8 +#define V_T7_MACMATCH(x) ((x) << S_T7_MACMATCH) +#define F_T7_MACMATCH V_T7_MACMATCH(1U) + +#define S_T7_ETHERTYPE 7 +#define V_T7_ETHERTYPE(x) ((x) << S_T7_ETHERTYPE) +#define F_T7_ETHERTYPE V_T7_ETHERTYPE(1U) + +#define S_T7_PROTOCOL 6 +#define V_T7_PROTOCOL(x) ((x) << S_T7_PROTOCOL) +#define F_T7_PROTOCOL V_T7_PROTOCOL(1U) + +#define S_T7_TOS 5 +#define V_T7_TOS(x) ((x) << S_T7_TOS) +#define F_T7_TOS V_T7_TOS(1U) + +#define S_T7_VLAN 4 +#define V_T7_VLAN(x) ((x) << S_T7_VLAN) +#define F_T7_VLAN V_T7_VLAN(1U) + +#define S_T7_VNIC_ID 3 +#define V_T7_VNIC_ID(x) ((x) << S_T7_VNIC_ID) +#define F_T7_VNIC_ID V_T7_VNIC_ID(1U) + +#define S_T7_PORT 2 +#define V_T7_PORT(x) ((x) << S_T7_PORT) +#define F_T7_PORT V_T7_PORT(1U) + +#define S_T7_FCOE 1 +#define V_T7_FCOE(x) ((x) << S_T7_FCOE) +#define F_T7_FCOE V_T7_FCOE(1U) + +#define S_IPSECIDX 0 +#define V_IPSECIDX(x) ((x) << S_IPSECIDX) +#define F_IPSECIDX V_IPSECIDX(1U) + #define A_TP_INGRESS_CONFIG 0x141 #define S_OPAQUE_TYPE 16 @@ -26888,6 +33747,14 @@ #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX) #define F_USE_ENC_IDX V_USE_ENC_IDX(1U) +#define S_USE_MPS_ECN 15 +#define V_USE_MPS_ECN(x) ((x) << S_USE_MPS_ECN) +#define F_USE_MPS_ECN V_USE_MPS_ECN(1U) + +#define S_USE_MPS_CONG 14 +#define V_USE_MPS_CONG(x) ((x) << S_USE_MPS_CONG) +#define F_USE_MPS_CONG V_USE_MPS_CONG(1U) + #define A_TP_TX_DROP_CFG_CH2 0x142 #define A_TP_TX_DROP_CFG_CH3 0x143 #define A_TP_EGRESS_CONFIG 0x145 @@ -27490,6 +34357,51 @@ #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT) #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT) +#define S_IPSECTUNETHTRANSEN 29 +#define V_IPSECTUNETHTRANSEN(x) ((x) << S_IPSECTUNETHTRANSEN) +#define F_IPSECTUNETHTRANSEN V_IPSECTUNETHTRANSEN(1U) + +#define S_ROCEV2ZEROUDP6CSUM 28 +#define V_ROCEV2ZEROUDP6CSUM(x) ((x) << S_ROCEV2ZEROUDP6CSUM) +#define F_ROCEV2ZEROUDP6CSUM V_ROCEV2ZEROUDP6CSUM(1U) + +#define S_ROCEV2PROCEN 27 +#define V_ROCEV2PROCEN(x) ((x) << S_ROCEV2PROCEN) +#define F_ROCEV2PROCEN V_ROCEV2PROCEN(1U) + +#define A_TP_ESIDE_ROCE_PORT12 0x161 + +#define S_ROCEV2UDPPORT2 16 +#define M_ROCEV2UDPPORT2 0xffffU +#define V_ROCEV2UDPPORT2(x) ((x) << S_ROCEV2UDPPORT2) +#define G_ROCEV2UDPPORT2(x) (((x) >> S_ROCEV2UDPPORT2) & M_ROCEV2UDPPORT2) + +#define S_ROCEV2UDPPORT1 0 +#define M_ROCEV2UDPPORT1 0xffffU +#define V_ROCEV2UDPPORT1(x) ((x) << S_ROCEV2UDPPORT1) +#define G_ROCEV2UDPPORT1(x) (((x) >> S_ROCEV2UDPPORT1) & M_ROCEV2UDPPORT1) + +#define A_TP_ESIDE_ROCE_PORT34 0x162 + +#define S_ROCEV2UDPPORT4 16 +#define M_ROCEV2UDPPORT4 0xffffU +#define V_ROCEV2UDPPORT4(x) ((x) << S_ROCEV2UDPPORT4) +#define G_ROCEV2UDPPORT4(x) (((x) >> S_ROCEV2UDPPORT4) & M_ROCEV2UDPPORT4) + +#define S_ROCEV2UDPPORT3 0 +#define M_ROCEV2UDPPORT3 0xffffU +#define V_ROCEV2UDPPORT3(x) ((x) << S_ROCEV2UDPPORT3) +#define G_ROCEV2UDPPORT3(x) (((x) >> S_ROCEV2UDPPORT3) & M_ROCEV2UDPPORT3) + +#define A_TP_ESIDE_CONFIG1 0x163 + +#define S_ROCEV2CRCIGN 0 +#define M_ROCEV2CRCIGN 0xfU +#define V_ROCEV2CRCIGN(x) ((x) << S_ROCEV2CRCIGN) +#define G_ROCEV2CRCIGN(x) (((x) >> S_ROCEV2CRCIGN) & M_ROCEV2CRCIGN) + +#define A_TP_ESIDE_DEBUG_CFG 0x16c +#define A_TP_ESIDE_DEBUG_DATA 0x16d #define A_TP_DBG_CSIDE_RX0 0x230 #define S_CRXSOPCNT 28 @@ -27962,56 +34874,7 @@ #define V_TXFULL2X(x) ((x) << S_TXFULL2X) #define F_TXFULL2X V_TXFULL2X(1U) -#define S_T6_TXFULL 31 -#define V_T6_TXFULL(x) ((x) << S_T6_TXFULL) -#define F_T6_TXFULL V_T6_TXFULL(1U) - -#define S_T6_PLD_RXZEROP_SRDY 25 -#define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY) -#define F_T6_PLD_RXZEROP_SRDY V_T6_PLD_RXZEROP_SRDY(1U) - -#define S_T6_DDP_SRDY 22 -#define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY) -#define F_T6_DDP_SRDY V_T6_DDP_SRDY(1U) - -#define S_T6_DDP_DRDY 21 -#define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY) -#define F_T6_DDP_DRDY V_T6_DDP_DRDY(1U) - #define A_TP_DBG_CSIDE_DISP1 0x23b - -#define S_T5_TXFULL 31 -#define V_T5_TXFULL(x) ((x) << S_T5_TXFULL) -#define F_T5_TXFULL V_T5_TXFULL(1U) - -#define S_T5_PLD_RXZEROP_SRDY 25 -#define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY) -#define F_T5_PLD_RXZEROP_SRDY V_T5_PLD_RXZEROP_SRDY(1U) - -#define S_T5_DDP_SRDY 22 -#define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY) -#define F_T5_DDP_SRDY V_T5_DDP_SRDY(1U) - -#define S_T5_DDP_DRDY 21 -#define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY) -#define F_T5_DDP_DRDY V_T5_DDP_DRDY(1U) - -#define S_T6_TXFULL 31 -#define V_T6_TXFULL(x) ((x) << S_T6_TXFULL) -#define F_T6_TXFULL V_T6_TXFULL(1U) - -#define S_T6_PLD_RXZEROP_SRDY 25 -#define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY) -#define F_T6_PLD_RXZEROP_SRDY V_T6_PLD_RXZEROP_SRDY(1U) - -#define S_T6_DDP_SRDY 22 -#define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY) -#define F_T6_DDP_SRDY V_T6_DDP_SRDY(1U) - -#define S_T6_DDP_DRDY 21 -#define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY) -#define F_T6_DDP_DRDY V_T6_DDP_DRDY(1U) - #define A_TP_DBG_CSIDE_DDP0 0x23c #define S_DDPMSGLATEST7 28 @@ -28222,6 +35085,59 @@ #define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE) #define F_ISCSICMDMODE V_ISCSICMDMODE(1U) +#define S_NVMTOPUPDEN 30 +#define V_NVMTOPUPDEN(x) ((x) << S_NVMTOPUPDEN) +#define F_NVMTOPUPDEN V_NVMTOPUPDEN(1U) + +#define S_NOPDIS 29 +#define V_NOPDIS(x) ((x) << S_NOPDIS) +#define F_NOPDIS V_NOPDIS(1U) + +#define S_IWARPINVREQEN 27 +#define V_IWARPINVREQEN(x) ((x) << S_IWARPINVREQEN) +#define F_IWARPINVREQEN V_IWARPINVREQEN(1U) + +#define S_ROCEINVREQEN 26 +#define V_ROCEINVREQEN(x) ((x) << S_ROCEINVREQEN) +#define F_ROCEINVREQEN V_ROCEINVREQEN(1U) + +#define S_ROCESRQFWEN 25 +#define V_ROCESRQFWEN(x) ((x) << S_ROCESRQFWEN) +#define F_ROCESRQFWEN V_ROCESRQFWEN(1U) + +#define S_T7_WRITEZEROOP 20 +#define M_T7_WRITEZEROOP 0x1fU +#define V_T7_WRITEZEROOP(x) ((x) << S_T7_WRITEZEROOP) +#define G_T7_WRITEZEROOP(x) (((x) >> S_T7_WRITEZEROOP) & M_T7_WRITEZEROOP) + +#define S_IWARPEXTMODE 9 +#define V_IWARPEXTMODE(x) ((x) << S_IWARPEXTMODE) +#define F_IWARPEXTMODE V_IWARPEXTMODE(1U) + +#define S_IWARPINVFWEN 8 +#define V_IWARPINVFWEN(x) ((x) << S_IWARPINVFWEN) +#define F_IWARPINVFWEN V_IWARPINVFWEN(1U) + +#define S_IWARPSRQFWEN 7 +#define V_IWARPSRQFWEN(x) ((x) << S_IWARPSRQFWEN) +#define F_IWARPSRQFWEN V_IWARPSRQFWEN(1U) + +#define S_T7_STARTSKIPPLD 3 +#define V_T7_STARTSKIPPLD(x) ((x) << S_T7_STARTSKIPPLD) +#define F_T7_STARTSKIPPLD V_T7_STARTSKIPPLD(1U) + +#define S_NVMTFLIMMEN 2 +#define V_NVMTFLIMMEN(x) ((x) << S_NVMTFLIMMEN) +#define F_NVMTFLIMMEN V_NVMTFLIMMEN(1U) + +#define S_NVMTOPCTRLEN 1 +#define V_NVMTOPCTRLEN(x) ((x) << S_NVMTOPCTRLEN) +#define F_NVMTOPCTRLEN V_NVMTOPCTRLEN(1U) + +#define S_T7_WRITEZEROEN 0 +#define V_T7_WRITEZEROEN(x) ((x) << S_T7_WRITEZEROEN) +#define F_T7_WRITEZEROEN V_T7_WRITEZEROEN(1U) + #define A_TP_CSPI_POWER 0x243 #define S_GATECHNTX3 11 @@ -28256,6 +35172,26 @@ #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN) #define F_SLEEPREQUTRN V_SLEEPREQUTRN(1U) +#define S_GATECHNRX3 7 +#define V_GATECHNRX3(x) ((x) << S_GATECHNRX3) +#define F_GATECHNRX3 V_GATECHNRX3(1U) + +#define S_GATECHNRX2 6 +#define V_GATECHNRX2(x) ((x) << S_GATECHNRX2) +#define F_GATECHNRX2 V_GATECHNRX2(1U) + +#define S_T7_GATECHNRX1 5 +#define V_T7_GATECHNRX1(x) ((x) << S_T7_GATECHNRX1) +#define F_T7_GATECHNRX1 V_T7_GATECHNRX1(1U) + +#define S_T7_GATECHNRX0 4 +#define V_T7_GATECHNRX0(x) ((x) << S_T7_GATECHNRX0) +#define F_T7_GATECHNRX0 V_T7_GATECHNRX0(1U) + +#define S_T7_SLEEPRDYUTRN 3 +#define V_T7_SLEEPRDYUTRN(x) ((x) << S_T7_SLEEPRDYUTRN) +#define F_T7_SLEEPRDYUTRN V_T7_SLEEPRDYUTRN(1U) + #define A_TP_TRC_CONFIG 0x244 #define S_TRCRR 1 @@ -28266,6 +35202,19 @@ #define V_TRCCH(x) ((x) << S_TRCCH) #define F_TRCCH V_TRCCH(1U) +#define S_DEBUGPG 3 +#define V_DEBUGPG(x) ((x) << S_DEBUGPG) +#define F_DEBUGPG V_DEBUGPG(1U) + +#define S_T7_TRCRR 2 +#define V_T7_TRCRR(x) ((x) << S_T7_TRCRR) +#define F_T7_TRCRR V_T7_TRCRR(1U) + +#define S_T7_TRCCH 0 +#define M_T7_TRCCH 0x3U +#define V_T7_TRCCH(x) ((x) << S_T7_TRCCH) +#define G_T7_TRCCH(x) (((x) >> S_T7_TRCCH) & M_T7_TRCCH) + #define A_TP_TAG_CONFIG 0x245 #define S_ETAGTYPE 16 @@ -28379,26 +35328,6 @@ #define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0) #define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0) -#define S_T6_CPRSSTATE3 24 -#define M_T6_CPRSSTATE3 0xfU -#define V_T6_CPRSSTATE3(x) ((x) << S_T6_CPRSSTATE3) -#define G_T6_CPRSSTATE3(x) (((x) >> S_T6_CPRSSTATE3) & M_T6_CPRSSTATE3) - -#define S_T6_CPRSSTATE2 16 -#define M_T6_CPRSSTATE2 0xfU -#define V_T6_CPRSSTATE2(x) ((x) << S_T6_CPRSSTATE2) -#define G_T6_CPRSSTATE2(x) (((x) >> S_T6_CPRSSTATE2) & M_T6_CPRSSTATE2) - -#define S_T6_CPRSSTATE1 8 -#define M_T6_CPRSSTATE1 0xfU -#define V_T6_CPRSSTATE1(x) ((x) << S_T6_CPRSSTATE1) -#define G_T6_CPRSSTATE1(x) (((x) >> S_T6_CPRSSTATE1) & M_T6_CPRSSTATE1) - -#define S_T6_CPRSSTATE0 0 -#define M_T6_CPRSSTATE0 0xfU -#define V_T6_CPRSSTATE0(x) ((x) << S_T6_CPRSSTATE0) -#define G_T6_CPRSSTATE0(x) (((x) >> S_T6_CPRSSTATE0) & M_T6_CPRSSTATE0) - #define A_TP_DBG_CSIDE_DEMUX 0x247 #define S_CALLDONE 28 @@ -28630,6 +35559,62 @@ #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250 +#define A_TP_CHDR_CONFIG1 0x259 + +#define S_CH3HIGH 24 +#define M_CH3HIGH 0xffU +#define V_CH3HIGH(x) ((x) << S_CH3HIGH) +#define G_CH3HIGH(x) (((x) >> S_CH3HIGH) & M_CH3HIGH) + +#define S_CH3LOW 16 +#define M_CH3LOW 0xffU +#define V_CH3LOW(x) ((x) << S_CH3LOW) +#define G_CH3LOW(x) (((x) >> S_CH3LOW) & M_CH3LOW) + +#define S_CH2HIGH 8 +#define M_CH2HIGH 0xffU +#define V_CH2HIGH(x) ((x) << S_CH2HIGH) +#define G_CH2HIGH(x) (((x) >> S_CH2HIGH) & M_CH2HIGH) + +#define S_CH2LOW 0 +#define M_CH2LOW 0xffU +#define V_CH2LOW(x) ((x) << S_CH2LOW) +#define G_CH2LOW(x) (((x) >> S_CH2LOW) & M_CH2LOW) + +#define A_TP_CDSP_RDMA_CONFIG 0x260 +#define A_TP_NVMT_OP_CTRL 0x268 + +#define S_DEFOPCTRL 30 +#define M_DEFOPCTRL 0x3U +#define V_DEFOPCTRL(x) ((x) << S_DEFOPCTRL) +#define G_DEFOPCTRL(x) (((x) >> S_DEFOPCTRL) & M_DEFOPCTRL) + +#define S_NVMTOPCTRL 0 +#define M_NVMTOPCTRL 0x3fffffffU +#define V_NVMTOPCTRL(x) ((x) << S_NVMTOPCTRL) +#define G_NVMTOPCTRL(x) (((x) >> S_NVMTOPCTRL) & M_NVMTOPCTRL) + +#define A_TP_CSIDE_DEBUG_CFG 0x26c + +#define S_T7_OR_EN 13 +#define V_T7_OR_EN(x) ((x) << S_T7_OR_EN) +#define F_T7_OR_EN V_T7_OR_EN(1U) + +#define S_T7_HI 12 +#define V_T7_HI(x) ((x) << S_T7_HI) +#define F_T7_HI V_T7_HI(1U) + +#define S_T7_SELH 6 +#define M_T7_SELH 0x3fU +#define V_T7_SELH(x) ((x) << S_T7_SELH) +#define G_T7_SELH(x) (((x) >> S_T7_SELH) & M_T7_SELH) + +#define S_T7_SELL 0 +#define M_T7_SELL 0x3fU +#define V_T7_SELL(x) ((x) << S_T7_SELL) +#define G_T7_SELL(x) (((x) >> S_T7_SELL) & M_T7_SELL) + +#define A_TP_CSIDE_DEBUG_DATA 0x26d #define A_TP_FIFO_CONFIG 0x8c0 #define S_CH1_OUTPUT 27 @@ -28771,6 +35756,174 @@ #define A_TP_MIB_TNL_ERR_1 0x71 #define A_TP_MIB_TNL_ERR_2 0x72 #define A_TP_MIB_TNL_ERR_3 0x73 +#define A_TP_MIB_RDMA_IN_PKT_0 0x80 +#define A_TP_MIB_RDMA_IN_PKT_1 0x81 +#define A_TP_MIB_RDMA_IN_PKT_2 0x82 +#define A_TP_MIB_RDMA_IN_PKT_3 0x83 +#define A_TP_MIB_RDMA_IN_BYTE_HI_0 0x84 +#define A_TP_MIB_RDMA_IN_BYTE_LO_0 0x85 +#define A_TP_MIB_RDMA_IN_BYTE_HI_1 0x86 +#define A_TP_MIB_RDMA_IN_BYTE_LO_1 0x87 +#define A_TP_MIB_RDMA_IN_BYTE_HI_2 0x88 +#define A_TP_MIB_RDMA_IN_BYTE_LO_2 0x89 +#define A_TP_MIB_RDMA_IN_BYTE_HI_3 0x8a +#define A_TP_MIB_RDMA_IN_BYTE_LO_3 0x8b +#define A_TP_MIB_RDMA_OUT_PKT_0 0x90 +#define A_TP_MIB_RDMA_OUT_PKT_1 0x91 +#define A_TP_MIB_RDMA_OUT_PKT_2 0x92 +#define A_TP_MIB_RDMA_OUT_PKT_3 0x93 +#define A_TP_MIB_RDMA_OUT_BYTE_HI_0 0x94 +#define A_TP_MIB_RDMA_OUT_BYTE_LO_0 0x95 +#define A_TP_MIB_RDMA_OUT_BYTE_HI_1 0x96 +#define A_TP_MIB_RDMA_OUT_BYTE_LO_1 0x97 +#define A_TP_MIB_RDMA_OUT_BYTE_HI_2 0x98 +#define A_TP_MIB_RDMA_OUT_BYTE_LO_2 0x99 +#define A_TP_MIB_RDMA_OUT_BYTE_HI_3 0x9a +#define A_TP_MIB_RDMA_OUT_BYTE_LO_3 0x9b +#define A_TP_MIB_ISCSI_IN_PKT_0 0xa0 +#define A_TP_MIB_ISCSI_IN_PKT_1 0xa1 +#define A_TP_MIB_ISCSI_IN_PKT_2 0xa2 +#define A_TP_MIB_ISCSI_IN_PKT_3 0xa3 +#define A_TP_MIB_ISCSI_IN_BYTE_HI_0 0xa4 +#define A_TP_MIB_ISCSI_IN_BYTE_LO_0 0xa5 +#define A_TP_MIB_ISCSI_IN_BYTE_HI_1 0xa6 +#define A_TP_MIB_ISCSI_IN_BYTE_LO_1 0xa7 +#define A_TP_MIB_ISCSI_IN_BYTE_HI_2 0xa8 +#define A_TP_MIB_ISCSI_IN_BYTE_LO_2 0xa9 +#define A_TP_MIB_ISCSI_IN_BYTE_HI_3 0xaa +#define A_TP_MIB_ISCSI_IN_BYTE_LO_3 0xab +#define A_TP_MIB_ISCSI_OUT_PKT_0 0xb0 +#define A_TP_MIB_ISCSI_OUT_PKT_1 0xb1 +#define A_TP_MIB_ISCSI_OUT_PKT_2 0xb2 +#define A_TP_MIB_ISCSI_OUT_PKT_3 0xb3 +#define A_TP_MIB_ISCSI_OUT_BYTE_HI_0 0xb4 +#define A_TP_MIB_ISCSI_OUT_BYTE_LO_0 0xb5 +#define A_TP_MIB_ISCSI_OUT_BYTE_HI_1 0xb6 +#define A_TP_MIB_ISCSI_OUT_BYTE_LO_1 0xb7 +#define A_TP_MIB_ISCSI_OUT_BYTE_HI_2 0xb8 +#define A_TP_MIB_ISCSI_OUT_BYTE_LO_2 0xb9 +#define A_TP_MIB_ISCSI_OUT_BYTE_HI_3 0xba +#define A_TP_MIB_ISCSI_OUT_BYTE_LO_3 0xbb +#define A_TP_MIB_NVMT_IN_PKT_0 0xc0 +#define A_TP_MIB_NVMT_IN_PKT_1 0xc1 +#define A_TP_MIB_NVMT_IN_PKT_2 0xc2 +#define A_TP_MIB_NVMT_IN_PKT_3 0xc3 +#define A_TP_MIB_NVMT_IN_BYTE_HI_0 0xc4 +#define A_TP_MIB_NVMT_IN_BYTE_LO_0 0xc5 +#define A_TP_MIB_NVMT_IN_BYTE_HI_1 0xc6 +#define A_TP_MIB_NVMT_IN_BYTE_LO_1 0xc7 +#define A_TP_MIB_NVMT_IN_BYTE_HI_2 0xc8 +#define A_TP_MIB_NVMT_IN_BYTE_LO_2 0xc9 +#define A_TP_MIB_NVMT_IN_BYTE_HI_3 0xca +#define A_TP_MIB_NVMT_IN_BYTE_LO_3 0xcb +#define A_TP_MIB_NVMT_OUT_PKT_0 0xd0 +#define A_TP_MIB_NVMT_OUT_PKT_1 0xd1 +#define A_TP_MIB_NVMT_OUT_PKT_2 0xd2 +#define A_TP_MIB_NVMT_OUT_PKT_3 0xd3 +#define A_TP_MIB_NVMT_OUT_BYTE_HI_0 0xd4 +#define A_TP_MIB_NVMT_OUT_BYTE_LO_0 0xd5 +#define A_TP_MIB_NVMT_OUT_BYTE_HI_1 0xd6 +#define A_TP_MIB_NVMT_OUT_BYTE_LO_1 0xd7 +#define A_TP_MIB_NVMT_OUT_BYTE_HI_2 0xd8 +#define A_TP_MIB_NVMT_OUT_BYTE_LO_2 0xd9 +#define A_TP_MIB_NVMT_OUT_BYTE_HI_3 0xda +#define A_TP_MIB_NVMT_OUT_BYTE_LO_3 0xdb +#define A_TP_MIB_TLS_IN_PKT_0 0xe0 +#define A_TP_MIB_TLS_IN_PKT_1 0xe1 +#define A_TP_MIB_TLS_IN_PKT_2 0xe2 +#define A_TP_MIB_TLS_IN_PKT_3 0xe3 +#define A_TP_MIB_TLS_IN_BYTE_HI_0 0xe4 +#define A_TP_MIB_TLS_IN_BYTE_LO_0 0xe5 +#define A_TP_MIB_TLS_IN_BYTE_HI_1 0xe6 +#define A_TP_MIB_TLS_IN_BYTE_LO_1 0xe7 +#define A_TP_MIB_TLS_IN_BYTE_HI_2 0xe8 +#define A_TP_MIB_TLS_IN_BYTE_LO_2 0xe9 +#define A_TP_MIB_TLS_IN_BYTE_HI_3 0xea +#define A_TP_MIB_TLS_IN_BYTE_LO_3 0xeb +#define A_TP_MIB_TLS_OUT_PKT_0 0xf0 +#define A_TP_MIB_TLS_OUT_PKT_1 0xf1 +#define A_TP_MIB_TLS_OUT_PKT_2 0xf2 +#define A_TP_MIB_TLS_OUT_PKT_3 0xf3 +#define A_TP_MIB_TLS_OUT_BYTE_HI_0 0xf4 +#define A_TP_MIB_TLS_OUT_BYTE_LO_0 0xf5 +#define A_TP_MIB_TLS_OUT_BYTE_HI_1 0xf6 +#define A_TP_MIB_TLS_OUT_BYTE_LO_1 0xf7 +#define A_TP_MIB_TLS_OUT_BYTE_HI_2 0xf8 +#define A_TP_MIB_TLS_OUT_BYTE_LO_2 0xf9 +#define A_TP_MIB_TLS_OUT_BYTE_HI_3 0xfa +#define A_TP_MIB_TLS_OUT_BYTE_LO_3 0xfb +#define A_TP_MIB_ROCE_IN_PKT_0 0x100 +#define A_TP_MIB_ROCE_IN_PKT_1 0x101 +#define A_TP_MIB_ROCE_IN_PKT_2 0x102 +#define A_TP_MIB_ROCE_IN_PKT_3 0x103 +#define A_TP_MIB_ROCE_IN_BYTE_HI_0 0x104 +#define A_TP_MIB_ROCE_IN_BYTE_LO_0 0x105 +#define A_TP_MIB_ROCE_IN_BYTE_HI_1 0x106 +#define A_TP_MIB_ROCE_IN_BYTE_LO_1 0x107 +#define A_TP_MIB_ROCE_IN_BYTE_HI_2 0x108 +#define A_TP_MIB_ROCE_IN_BYTE_LO_2 0x109 +#define A_TP_MIB_ROCE_IN_BYTE_HI_3 0x10a +#define A_TP_MIB_ROCE_IN_BYTE_LO_3 0x10b +#define A_TP_MIB_ROCE_OUT_PKT_0 0x110 +#define A_TP_MIB_ROCE_OUT_PKT_1 0x111 +#define A_TP_MIB_ROCE_OUT_PKT_2 0x112 +#define A_TP_MIB_ROCE_OUT_PKT_3 0x113 +#define A_TP_MIB_ROCE_OUT_BYTE_HI_0 0x114 +#define A_TP_MIB_ROCE_OUT_BYTE_LO_0 0x115 +#define A_TP_MIB_ROCE_OUT_BYTE_HI_1 0x116 +#define A_TP_MIB_ROCE_OUT_BYTE_LO_1 0x117 +#define A_TP_MIB_ROCE_OUT_BYTE_HI_2 0x118 +#define A_TP_MIB_ROCE_OUT_BYTE_LO_2 0x119 +#define A_TP_MIB_ROCE_OUT_BYTE_HI_3 0x11a +#define A_TP_MIB_ROCE_OUT_BYTE_LO_3 0x11b +#define A_TP_MIB_IPSEC_TNL_IN_PKT_0 0x120 +#define A_TP_MIB_IPSEC_TNL_IN_PKT_1 0x121 +#define A_TP_MIB_IPSEC_TNL_IN_PKT_2 0x122 +#define A_TP_MIB_IPSEC_TNL_IN_PKT_3 0x123 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_0 0x124 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_0 0x125 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_1 0x126 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_1 0x127 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_2 0x128 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_2 0x129 +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_3 0x12a +#define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_3 0x12b +#define A_TP_MIB_IPSEC_TNL_OUT_PKT_0 0x130 +#define A_TP_MIB_IPSEC_TNL_OUT_PKT_1 0x131 +#define A_TP_MIB_IPSEC_TNL_OUT_PKT_2 0x132 +#define A_TP_MIB_IPSEC_TNL_OUT_PKT_3 0x133 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_0 0x134 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_0 0x135 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_1 0x136 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_1 0x137 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_2 0x138 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_2 0x139 +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_3 0x13a +#define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_3 0x13b +#define A_TP_MIB_IPSEC_OFD_IN_PKT_0 0x140 +#define A_TP_MIB_IPSEC_OFD_IN_PKT_1 0x141 +#define A_TP_MIB_IPSEC_OFD_IN_PKT_2 0x142 +#define A_TP_MIB_IPSEC_OFD_IN_PKT_3 0x143 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_0 0x144 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_0 0x145 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_1 0x146 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_1 0x147 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_2 0x148 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_2 0x149 +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_3 0x14a +#define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_3 0x14b +#define A_TP_MIB_IPSEC_OFD_OUT_PKT_0 0x150 +#define A_TP_MIB_IPSEC_OFD_OUT_PKT_1 0x151 +#define A_TP_MIB_IPSEC_OFD_OUT_PKT_2 0x152 +#define A_TP_MIB_IPSEC_OFD_OUT_PKT_3 0x153 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_0 0x154 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_0 0x155 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_1 0x156 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_1 0x157 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_2 0x158 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_2 0x159 +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_3 0x15a +#define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_3 0x15b /* registers for module ULP_TX */ #define ULP_TX_BASE_ADDR 0x8dc0 @@ -28853,7 +36006,58 @@ #define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS) #define F_ATOMIC_FIX_DIS V_ATOMIC_FIX_DIS(1U) +#define S_LB_LEN_SEL 28 +#define V_LB_LEN_SEL(x) ((x) << S_LB_LEN_SEL) +#define F_LB_LEN_SEL V_LB_LEN_SEL(1U) + +#define S_DISABLE_TPT_CREDIT_CHK 27 +#define V_DISABLE_TPT_CREDIT_CHK(x) ((x) << S_DISABLE_TPT_CREDIT_CHK) +#define F_DISABLE_TPT_CREDIT_CHK V_DISABLE_TPT_CREDIT_CHK(1U) + +#define S_REQSRC 26 +#define V_REQSRC(x) ((x) << S_REQSRC) +#define F_REQSRC V_REQSRC(1U) + +#define S_ERR2UP 25 +#define V_ERR2UP(x) ((x) << S_ERR2UP) +#define F_ERR2UP V_ERR2UP(1U) + +#define S_SGE_INVALIDATE_DIS 24 +#define V_SGE_INVALIDATE_DIS(x) ((x) << S_SGE_INVALIDATE_DIS) +#define F_SGE_INVALIDATE_DIS V_SGE_INVALIDATE_DIS(1U) + +#define S_ROCE_ACKREQ_CTRL 23 +#define V_ROCE_ACKREQ_CTRL(x) ((x) << S_ROCE_ACKREQ_CTRL) +#define F_ROCE_ACKREQ_CTRL V_ROCE_ACKREQ_CTRL(1U) + +#define S_MEM_ADDR_CTRL 21 +#define M_MEM_ADDR_CTRL 0x3U +#define V_MEM_ADDR_CTRL(x) ((x) << S_MEM_ADDR_CTRL) +#define G_MEM_ADDR_CTRL(x) (((x) >> S_MEM_ADDR_CTRL) & M_MEM_ADDR_CTRL) + +#define S_TPT_EXTENSION_MODE 20 +#define V_TPT_EXTENSION_MODE(x) ((x) << S_TPT_EXTENSION_MODE) +#define F_TPT_EXTENSION_MODE V_TPT_EXTENSION_MODE(1U) + +#define S_XRC_INDICATION 19 +#define V_XRC_INDICATION(x) ((x) << S_XRC_INDICATION) +#define F_XRC_INDICATION V_XRC_INDICATION(1U) + +#define S_LSO_1SEG_LEN_UPD_EN 18 +#define V_LSO_1SEG_LEN_UPD_EN(x) ((x) << S_LSO_1SEG_LEN_UPD_EN) +#define F_LSO_1SEG_LEN_UPD_EN V_LSO_1SEG_LEN_UPD_EN(1U) + +#define S_PKT_ISGL_ERR_ST_EN 17 +#define V_PKT_ISGL_ERR_ST_EN(x) ((x) << S_PKT_ISGL_ERR_ST_EN) +#define F_PKT_ISGL_ERR_ST_EN V_PKT_ISGL_ERR_ST_EN(1U) + #define A_ULP_TX_PERR_INJECT 0x8dc4 + +#define S_T7_1_MEMSEL 1 +#define M_T7_1_MEMSEL 0x7fU +#define V_T7_1_MEMSEL(x) ((x) << S_T7_1_MEMSEL) +#define G_T7_1_MEMSEL(x) (((x) >> S_T7_1_MEMSEL) & M_T7_1_MEMSEL) + #define A_ULP_TX_INT_ENABLE 0x8dc8 #define S_PBL_BOUND_ERR_CH3 31 @@ -28984,8 +36188,28 @@ #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0) #define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U) +#define A_ULP_TX_INT_ENABLE_1 0x8dc8 + +#define S_TLS_DSGL_PARERR3 3 +#define V_TLS_DSGL_PARERR3(x) ((x) << S_TLS_DSGL_PARERR3) +#define F_TLS_DSGL_PARERR3 V_TLS_DSGL_PARERR3(1U) + +#define S_TLS_DSGL_PARERR2 2 +#define V_TLS_DSGL_PARERR2(x) ((x) << S_TLS_DSGL_PARERR2) +#define F_TLS_DSGL_PARERR2 V_TLS_DSGL_PARERR2(1U) + +#define S_TLS_DSGL_PARERR1 1 +#define V_TLS_DSGL_PARERR1(x) ((x) << S_TLS_DSGL_PARERR1) +#define F_TLS_DSGL_PARERR1 V_TLS_DSGL_PARERR1(1U) + +#define S_TLS_DSGL_PARERR0 0 +#define V_TLS_DSGL_PARERR0(x) ((x) << S_TLS_DSGL_PARERR0) +#define F_TLS_DSGL_PARERR0 V_TLS_DSGL_PARERR0(1U) + #define A_ULP_TX_INT_CAUSE 0x8dcc +#define A_ULP_TX_INT_CAUSE_1 0x8dcc #define A_ULP_TX_PERR_ENABLE 0x8dd0 +#define A_ULP_TX_PERR_ENABLE_1 0x8dd0 #define A_ULP_TX_TPT_LLIMIT 0x8dd4 #define A_ULP_TX_TPT_ULIMIT 0x8dd8 #define A_ULP_TX_PBL_LLIMIT 0x8ddc @@ -29014,6 +36238,13 @@ #define F_TLSDISABLE V_TLSDISABLE(1U) #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8 +#define A_ULP_TX_FID_1 0x8de8 + +#define S_FID_1 0 +#define M_FID_1 0x7ffU +#define V_FID_1(x) ((x) << S_FID_1) +#define G_FID_1(x) (((x) >> S_FID_1) & M_FID_1) + #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4 @@ -29166,6 +36397,15 @@ #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ) #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ) +#define S_T7_GLOBALENABLE 31 +#define V_T7_GLOBALENABLE(x) ((x) << S_T7_GLOBALENABLE) +#define F_T7_GLOBALENABLE V_T7_GLOBALENABLE(1U) + +#define S_RDREQ_SZ 3 +#define M_RDREQ_SZ 0x7U +#define V_RDREQ_SZ(x) ((x) << S_RDREQ_SZ) +#define G_RDREQ_SZ(x) (((x) >> S_RDREQ_SZ) & M_RDREQ_SZ) + #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34 #define A_ULP_TX_PERR_INJECT_2 0x8e34 @@ -29385,6 +36625,200 @@ #define A_ULP_TX_INT_CAUSE_2 0x8e80 #define A_ULP_TX_PERR_ENABLE_2 0x8e84 +#define A_ULP_TX_INT_ENABLE_3 0x8e88 + +#define S_GF_SGE_FIFO_PARERR3 31 +#define V_GF_SGE_FIFO_PARERR3(x) ((x) << S_GF_SGE_FIFO_PARERR3) +#define F_GF_SGE_FIFO_PARERR3 V_GF_SGE_FIFO_PARERR3(1U) + +#define S_GF_SGE_FIFO_PARERR2 30 +#define V_GF_SGE_FIFO_PARERR2(x) ((x) << S_GF_SGE_FIFO_PARERR2) +#define F_GF_SGE_FIFO_PARERR2 V_GF_SGE_FIFO_PARERR2(1U) + +#define S_GF_SGE_FIFO_PARERR1 29 +#define V_GF_SGE_FIFO_PARERR1(x) ((x) << S_GF_SGE_FIFO_PARERR1) +#define F_GF_SGE_FIFO_PARERR1 V_GF_SGE_FIFO_PARERR1(1U) + +#define S_GF_SGE_FIFO_PARERR0 28 +#define V_GF_SGE_FIFO_PARERR0(x) ((x) << S_GF_SGE_FIFO_PARERR0) +#define F_GF_SGE_FIFO_PARERR0 V_GF_SGE_FIFO_PARERR0(1U) + +#define S_DEDUPE_SGE_FIFO_PARERR3 27 +#define V_DEDUPE_SGE_FIFO_PARERR3(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR3) +#define F_DEDUPE_SGE_FIFO_PARERR3 V_DEDUPE_SGE_FIFO_PARERR3(1U) + +#define S_DEDUPE_SGE_FIFO_PARERR2 26 +#define V_DEDUPE_SGE_FIFO_PARERR2(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR2) +#define F_DEDUPE_SGE_FIFO_PARERR2 V_DEDUPE_SGE_FIFO_PARERR2(1U) + +#define S_DEDUPE_SGE_FIFO_PARERR1 25 +#define V_DEDUPE_SGE_FIFO_PARERR1(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR1) +#define F_DEDUPE_SGE_FIFO_PARERR1 V_DEDUPE_SGE_FIFO_PARERR1(1U) + +#define S_DEDUPE_SGE_FIFO_PARERR0 24 +#define V_DEDUPE_SGE_FIFO_PARERR0(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR0) +#define F_DEDUPE_SGE_FIFO_PARERR0 V_DEDUPE_SGE_FIFO_PARERR0(1U) + +#define S_GF3_DSGL_FIFO_PARERR 23 +#define V_GF3_DSGL_FIFO_PARERR(x) ((x) << S_GF3_DSGL_FIFO_PARERR) +#define F_GF3_DSGL_FIFO_PARERR V_GF3_DSGL_FIFO_PARERR(1U) + +#define S_GF2_DSGL_FIFO_PARERR 22 +#define V_GF2_DSGL_FIFO_PARERR(x) ((x) << S_GF2_DSGL_FIFO_PARERR) +#define F_GF2_DSGL_FIFO_PARERR V_GF2_DSGL_FIFO_PARERR(1U) + +#define S_GF1_DSGL_FIFO_PARERR 21 +#define V_GF1_DSGL_FIFO_PARERR(x) ((x) << S_GF1_DSGL_FIFO_PARERR) +#define F_GF1_DSGL_FIFO_PARERR V_GF1_DSGL_FIFO_PARERR(1U) + +#define S_GF0_DSGL_FIFO_PARERR 20 +#define V_GF0_DSGL_FIFO_PARERR(x) ((x) << S_GF0_DSGL_FIFO_PARERR) +#define F_GF0_DSGL_FIFO_PARERR V_GF0_DSGL_FIFO_PARERR(1U) + +#define S_DEDUPE3_DSGL_FIFO_PARERR 19 +#define V_DEDUPE3_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE3_DSGL_FIFO_PARERR) +#define F_DEDUPE3_DSGL_FIFO_PARERR V_DEDUPE3_DSGL_FIFO_PARERR(1U) + +#define S_DEDUPE2_DSGL_FIFO_PARERR 18 +#define V_DEDUPE2_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE2_DSGL_FIFO_PARERR) +#define F_DEDUPE2_DSGL_FIFO_PARERR V_DEDUPE2_DSGL_FIFO_PARERR(1U) + +#define S_DEDUPE1_DSGL_FIFO_PARERR 17 +#define V_DEDUPE1_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE1_DSGL_FIFO_PARERR) +#define F_DEDUPE1_DSGL_FIFO_PARERR V_DEDUPE1_DSGL_FIFO_PARERR(1U) + +#define S_DEDUPE0_DSGL_FIFO_PARERR 16 +#define V_DEDUPE0_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE0_DSGL_FIFO_PARERR) +#define F_DEDUPE0_DSGL_FIFO_PARERR V_DEDUPE0_DSGL_FIFO_PARERR(1U) + +#define S_XP10_SGE_FIFO_PARERR 15 +#define V_XP10_SGE_FIFO_PARERR(x) ((x) << S_XP10_SGE_FIFO_PARERR) +#define F_XP10_SGE_FIFO_PARERR V_XP10_SGE_FIFO_PARERR(1U) + +#define S_DSGL_PAR_ERR 14 +#define V_DSGL_PAR_ERR(x) ((x) << S_DSGL_PAR_ERR) +#define F_DSGL_PAR_ERR V_DSGL_PAR_ERR(1U) + +#define S_CDDIP_INT 13 +#define V_CDDIP_INT(x) ((x) << S_CDDIP_INT) +#define F_CDDIP_INT V_CDDIP_INT(1U) + +#define S_CCEIP_INT 12 +#define V_CCEIP_INT(x) ((x) << S_CCEIP_INT) +#define F_CCEIP_INT V_CCEIP_INT(1U) + +#define S_TLS_SGE_FIFO_PARERR3 11 +#define V_TLS_SGE_FIFO_PARERR3(x) ((x) << S_TLS_SGE_FIFO_PARERR3) +#define F_TLS_SGE_FIFO_PARERR3 V_TLS_SGE_FIFO_PARERR3(1U) + +#define S_TLS_SGE_FIFO_PARERR2 10 +#define V_TLS_SGE_FIFO_PARERR2(x) ((x) << S_TLS_SGE_FIFO_PARERR2) +#define F_TLS_SGE_FIFO_PARERR2 V_TLS_SGE_FIFO_PARERR2(1U) + +#define S_TLS_SGE_FIFO_PARERR1 9 +#define V_TLS_SGE_FIFO_PARERR1(x) ((x) << S_TLS_SGE_FIFO_PARERR1) +#define F_TLS_SGE_FIFO_PARERR1 V_TLS_SGE_FIFO_PARERR1(1U) + +#define S_TLS_SGE_FIFO_PARERR0 8 +#define V_TLS_SGE_FIFO_PARERR0(x) ((x) << S_TLS_SGE_FIFO_PARERR0) +#define F_TLS_SGE_FIFO_PARERR0 V_TLS_SGE_FIFO_PARERR0(1U) + +#define S_ULP2SMARBT_RSP_PERR 6 +#define V_ULP2SMARBT_RSP_PERR(x) ((x) << S_ULP2SMARBT_RSP_PERR) +#define F_ULP2SMARBT_RSP_PERR V_ULP2SMARBT_RSP_PERR(1U) + +#define S_ULPTX2MA_RSP_PERR 5 +#define V_ULPTX2MA_RSP_PERR(x) ((x) << S_ULPTX2MA_RSP_PERR) +#define F_ULPTX2MA_RSP_PERR V_ULPTX2MA_RSP_PERR(1U) + +#define S_PCIE2ULP_PERR3 4 +#define V_PCIE2ULP_PERR3(x) ((x) << S_PCIE2ULP_PERR3) +#define F_PCIE2ULP_PERR3 V_PCIE2ULP_PERR3(1U) + +#define S_PCIE2ULP_PERR2 3 +#define V_PCIE2ULP_PERR2(x) ((x) << S_PCIE2ULP_PERR2) +#define F_PCIE2ULP_PERR2 V_PCIE2ULP_PERR2(1U) + +#define S_PCIE2ULP_PERR1 2 +#define V_PCIE2ULP_PERR1(x) ((x) << S_PCIE2ULP_PERR1) +#define F_PCIE2ULP_PERR1 V_PCIE2ULP_PERR1(1U) + +#define S_PCIE2ULP_PERR0 1 +#define V_PCIE2ULP_PERR0(x) ((x) << S_PCIE2ULP_PERR0) +#define F_PCIE2ULP_PERR0 V_PCIE2ULP_PERR0(1U) + +#define S_CIM2ULP_PERR 0 +#define V_CIM2ULP_PERR(x) ((x) << S_CIM2ULP_PERR) +#define F_CIM2ULP_PERR V_CIM2ULP_PERR(1U) + +#define A_ULP_TX_INT_CAUSE_3 0x8e8c +#define A_ULP_TX_PERR_ENABLE_3 0x8e90 +#define A_ULP_TX_INT_ENABLE_4 0x8e94 + +#define S_DMA_PAR_ERR3 28 +#define M_DMA_PAR_ERR3 0xfU +#define V_DMA_PAR_ERR3(x) ((x) << S_DMA_PAR_ERR3) +#define G_DMA_PAR_ERR3(x) (((x) >> S_DMA_PAR_ERR3) & M_DMA_PAR_ERR3) + +#define S_DMA_PAR_ERR2 24 +#define M_DMA_PAR_ERR2 0xfU +#define V_DMA_PAR_ERR2(x) ((x) << S_DMA_PAR_ERR2) +#define G_DMA_PAR_ERR2(x) (((x) >> S_DMA_PAR_ERR2) & M_DMA_PAR_ERR2) + +#define S_DMA_PAR_ERR1 20 +#define M_DMA_PAR_ERR1 0xfU +#define V_DMA_PAR_ERR1(x) ((x) << S_DMA_PAR_ERR1) +#define G_DMA_PAR_ERR1(x) (((x) >> S_DMA_PAR_ERR1) & M_DMA_PAR_ERR1) + +#define S_DMA_PAR_ERR0 16 +#define M_DMA_PAR_ERR0 0xfU +#define V_DMA_PAR_ERR0(x) ((x) << S_DMA_PAR_ERR0) +#define G_DMA_PAR_ERR0(x) (((x) >> S_DMA_PAR_ERR0) & M_DMA_PAR_ERR0) + +#define S_CORE_CMD_FIFO_LB1 12 +#define M_CORE_CMD_FIFO_LB1 0xfU +#define V_CORE_CMD_FIFO_LB1(x) ((x) << S_CORE_CMD_FIFO_LB1) +#define G_CORE_CMD_FIFO_LB1(x) (((x) >> S_CORE_CMD_FIFO_LB1) & M_CORE_CMD_FIFO_LB1) + +#define S_CORE_CMD_FIFO_LB0 8 +#define M_CORE_CMD_FIFO_LB0 0xfU +#define V_CORE_CMD_FIFO_LB0(x) ((x) << S_CORE_CMD_FIFO_LB0) +#define G_CORE_CMD_FIFO_LB0(x) (((x) >> S_CORE_CMD_FIFO_LB0) & M_CORE_CMD_FIFO_LB0) + +#define S_XP10_2_ULP_PERR 7 +#define V_XP10_2_ULP_PERR(x) ((x) << S_XP10_2_ULP_PERR) +#define F_XP10_2_ULP_PERR V_XP10_2_ULP_PERR(1U) + +#define S_ULP_2_XP10_PERR 6 +#define V_ULP_2_XP10_PERR(x) ((x) << S_ULP_2_XP10_PERR) +#define F_ULP_2_XP10_PERR V_ULP_2_XP10_PERR(1U) + +#define S_CMD_FIFO_LB1 5 +#define V_CMD_FIFO_LB1(x) ((x) << S_CMD_FIFO_LB1) +#define F_CMD_FIFO_LB1 V_CMD_FIFO_LB1(1U) + +#define S_CMD_FIFO_LB0 4 +#define V_CMD_FIFO_LB0(x) ((x) << S_CMD_FIFO_LB0) +#define F_CMD_FIFO_LB0 V_CMD_FIFO_LB0(1U) + +#define S_TF_TP_PERR 3 +#define V_TF_TP_PERR(x) ((x) << S_TF_TP_PERR) +#define F_TF_TP_PERR V_TF_TP_PERR(1U) + +#define S_TF_SGE_PERR 2 +#define V_TF_SGE_PERR(x) ((x) << S_TF_SGE_PERR) +#define F_TF_SGE_PERR V_TF_SGE_PERR(1U) + +#define S_TF_MEM_PERR 1 +#define V_TF_MEM_PERR(x) ((x) << S_TF_MEM_PERR) +#define F_TF_MEM_PERR V_TF_MEM_PERR(1U) + +#define S_TF_MP_PERR 0 +#define V_TF_MP_PERR(x) ((x) << S_TF_MP_PERR) +#define F_TF_MP_PERR V_TF_MP_PERR(1U) + +#define A_ULP_TX_INT_CAUSE_4 0x8e98 +#define A_ULP_TX_PERR_ENABLE_4 0x8e9c #define A_ULP_TX_SE_CNT_ERR 0x8ea0 #define S_ERR_CH3 12 @@ -29531,16 +36965,381 @@ #define A_ULP_TX_CSU_REVISION 0x8ebc #define A_ULP_TX_LA_RDPTR_0 0x8ec0 +#define A_ULP_TX_PL2APB_INFO 0x8ec0 + +#define S_PL2APB_BRIDGE_HUNG 27 +#define V_PL2APB_BRIDGE_HUNG(x) ((x) << S_PL2APB_BRIDGE_HUNG) +#define F_PL2APB_BRIDGE_HUNG V_PL2APB_BRIDGE_HUNG(1U) + +#define S_PL2APB_BRIDGE_STATE 26 +#define V_PL2APB_BRIDGE_STATE(x) ((x) << S_PL2APB_BRIDGE_STATE) +#define F_PL2APB_BRIDGE_STATE V_PL2APB_BRIDGE_STATE(1U) + +#define S_PL2APB_BRIDGE_HUNG_TYPE 25 +#define V_PL2APB_BRIDGE_HUNG_TYPE(x) ((x) << S_PL2APB_BRIDGE_HUNG_TYPE) +#define F_PL2APB_BRIDGE_HUNG_TYPE V_PL2APB_BRIDGE_HUNG_TYPE(1U) + +#define S_PL2APB_BRIDGE_HUNG_ID 24 +#define V_PL2APB_BRIDGE_HUNG_ID(x) ((x) << S_PL2APB_BRIDGE_HUNG_ID) +#define F_PL2APB_BRIDGE_HUNG_ID V_PL2APB_BRIDGE_HUNG_ID(1U) + +#define S_PL2APB_BRIDGE_HUNG_ADDR 0 +#define M_PL2APB_BRIDGE_HUNG_ADDR 0xfffffU +#define V_PL2APB_BRIDGE_HUNG_ADDR(x) ((x) << S_PL2APB_BRIDGE_HUNG_ADDR) +#define G_PL2APB_BRIDGE_HUNG_ADDR(x) (((x) >> S_PL2APB_BRIDGE_HUNG_ADDR) & M_PL2APB_BRIDGE_HUNG_ADDR) + #define A_ULP_TX_LA_RDDATA_0 0x8ec4 +#define A_ULP_TX_INT_ENABLE_5 0x8ec4 + +#define S_DEDUPE_PERR3 23 +#define V_DEDUPE_PERR3(x) ((x) << S_DEDUPE_PERR3) +#define F_DEDUPE_PERR3 V_DEDUPE_PERR3(1U) + +#define S_DEDUPE_PERR2 22 +#define V_DEDUPE_PERR2(x) ((x) << S_DEDUPE_PERR2) +#define F_DEDUPE_PERR2 V_DEDUPE_PERR2(1U) + +#define S_DEDUPE_PERR1 21 +#define V_DEDUPE_PERR1(x) ((x) << S_DEDUPE_PERR1) +#define F_DEDUPE_PERR1 V_DEDUPE_PERR1(1U) + +#define S_DEDUPE_PERR0 20 +#define V_DEDUPE_PERR0(x) ((x) << S_DEDUPE_PERR0) +#define F_DEDUPE_PERR0 V_DEDUPE_PERR0(1U) + +#define S_GF_PERR3 19 +#define V_GF_PERR3(x) ((x) << S_GF_PERR3) +#define F_GF_PERR3 V_GF_PERR3(1U) + +#define S_GF_PERR2 18 +#define V_GF_PERR2(x) ((x) << S_GF_PERR2) +#define F_GF_PERR2 V_GF_PERR2(1U) + +#define S_GF_PERR1 17 +#define V_GF_PERR1(x) ((x) << S_GF_PERR1) +#define F_GF_PERR1 V_GF_PERR1(1U) + +#define S_GF_PERR0 16 +#define V_GF_PERR0(x) ((x) << S_GF_PERR0) +#define F_GF_PERR0 V_GF_PERR0(1U) + +#define S_SGE2ULP_INV_PERR 13 +#define V_SGE2ULP_INV_PERR(x) ((x) << S_SGE2ULP_INV_PERR) +#define F_SGE2ULP_INV_PERR V_SGE2ULP_INV_PERR(1U) + +#define S_T7_PL_BUSPERR 12 +#define V_T7_PL_BUSPERR(x) ((x) << S_T7_PL_BUSPERR) +#define F_T7_PL_BUSPERR V_T7_PL_BUSPERR(1U) + +#define S_TLSTX2ULPTX_PERR3 11 +#define V_TLSTX2ULPTX_PERR3(x) ((x) << S_TLSTX2ULPTX_PERR3) +#define F_TLSTX2ULPTX_PERR3 V_TLSTX2ULPTX_PERR3(1U) + +#define S_TLSTX2ULPTX_PERR2 10 +#define V_TLSTX2ULPTX_PERR2(x) ((x) << S_TLSTX2ULPTX_PERR2) +#define F_TLSTX2ULPTX_PERR2 V_TLSTX2ULPTX_PERR2(1U) + +#define S_TLSTX2ULPTX_PERR1 9 +#define V_TLSTX2ULPTX_PERR1(x) ((x) << S_TLSTX2ULPTX_PERR1) +#define F_TLSTX2ULPTX_PERR1 V_TLSTX2ULPTX_PERR1(1U) + +#define S_TLSTX2ULPTX_PERR0 8 +#define V_TLSTX2ULPTX_PERR0(x) ((x) << S_TLSTX2ULPTX_PERR0) +#define F_TLSTX2ULPTX_PERR0 V_TLSTX2ULPTX_PERR0(1U) + +#define S_XP10_2_ULP_PL_PERR 1 +#define V_XP10_2_ULP_PL_PERR(x) ((x) << S_XP10_2_ULP_PL_PERR) +#define F_XP10_2_ULP_PL_PERR V_XP10_2_ULP_PL_PERR(1U) + +#define S_ULP_2_XP10_PL_PERR 0 +#define V_ULP_2_XP10_PL_PERR(x) ((x) << S_ULP_2_XP10_PL_PERR) +#define F_ULP_2_XP10_PL_PERR V_ULP_2_XP10_PL_PERR(1U) + #define A_ULP_TX_LA_WRPTR_0 0x8ec8 +#define A_ULP_TX_INT_CAUSE_5 0x8ec8 #define A_ULP_TX_LA_RESERVED_0 0x8ecc +#define A_ULP_TX_PERR_ENABLE_5 0x8ecc #define A_ULP_TX_LA_RDPTR_1 0x8ed0 +#define A_ULP_TX_INT_CAUSE_6 0x8ed0 + +#define S_DDR_HDR_FIFO_PERR_SET3 12 +#define V_DDR_HDR_FIFO_PERR_SET3(x) ((x) << S_DDR_HDR_FIFO_PERR_SET3) +#define F_DDR_HDR_FIFO_PERR_SET3 V_DDR_HDR_FIFO_PERR_SET3(1U) + +#define S_DDR_HDR_FIFO_PERR_SET2 11 +#define V_DDR_HDR_FIFO_PERR_SET2(x) ((x) << S_DDR_HDR_FIFO_PERR_SET2) +#define F_DDR_HDR_FIFO_PERR_SET2 V_DDR_HDR_FIFO_PERR_SET2(1U) + +#define S_DDR_HDR_FIFO_PERR_SET1 10 +#define V_DDR_HDR_FIFO_PERR_SET1(x) ((x) << S_DDR_HDR_FIFO_PERR_SET1) +#define F_DDR_HDR_FIFO_PERR_SET1 V_DDR_HDR_FIFO_PERR_SET1(1U) + +#define S_DDR_HDR_FIFO_PERR_SET0 9 +#define V_DDR_HDR_FIFO_PERR_SET0(x) ((x) << S_DDR_HDR_FIFO_PERR_SET0) +#define F_DDR_HDR_FIFO_PERR_SET0 V_DDR_HDR_FIFO_PERR_SET0(1U) + +#define S_PRE_MP_RSP_PERR_SET3 8 +#define V_PRE_MP_RSP_PERR_SET3(x) ((x) << S_PRE_MP_RSP_PERR_SET3) +#define F_PRE_MP_RSP_PERR_SET3 V_PRE_MP_RSP_PERR_SET3(1U) + +#define S_PRE_MP_RSP_PERR_SET2 7 +#define V_PRE_MP_RSP_PERR_SET2(x) ((x) << S_PRE_MP_RSP_PERR_SET2) +#define F_PRE_MP_RSP_PERR_SET2 V_PRE_MP_RSP_PERR_SET2(1U) + +#define S_PRE_MP_RSP_PERR_SET1 6 +#define V_PRE_MP_RSP_PERR_SET1(x) ((x) << S_PRE_MP_RSP_PERR_SET1) +#define F_PRE_MP_RSP_PERR_SET1 V_PRE_MP_RSP_PERR_SET1(1U) + +#define S_PRE_MP_RSP_PERR_SET0 5 +#define V_PRE_MP_RSP_PERR_SET0(x) ((x) << S_PRE_MP_RSP_PERR_SET0) +#define F_PRE_MP_RSP_PERR_SET0 V_PRE_MP_RSP_PERR_SET0(1U) + +#define S_PRE_CQE_FIFO_PERR_SET3 4 +#define V_PRE_CQE_FIFO_PERR_SET3(x) ((x) << S_PRE_CQE_FIFO_PERR_SET3) +#define F_PRE_CQE_FIFO_PERR_SET3 V_PRE_CQE_FIFO_PERR_SET3(1U) + +#define S_PRE_CQE_FIFO_PERR_SET2 3 +#define V_PRE_CQE_FIFO_PERR_SET2(x) ((x) << S_PRE_CQE_FIFO_PERR_SET2) +#define F_PRE_CQE_FIFO_PERR_SET2 V_PRE_CQE_FIFO_PERR_SET2(1U) + +#define S_PRE_CQE_FIFO_PERR_SET1 2 +#define V_PRE_CQE_FIFO_PERR_SET1(x) ((x) << S_PRE_CQE_FIFO_PERR_SET1) +#define F_PRE_CQE_FIFO_PERR_SET1 V_PRE_CQE_FIFO_PERR_SET1(1U) + +#define S_PRE_CQE_FIFO_PERR_SET0 1 +#define V_PRE_CQE_FIFO_PERR_SET0(x) ((x) << S_PRE_CQE_FIFO_PERR_SET0) +#define F_PRE_CQE_FIFO_PERR_SET0 V_PRE_CQE_FIFO_PERR_SET0(1U) + +#define S_RSP_FIFO_PERR_SET 0 +#define V_RSP_FIFO_PERR_SET(x) ((x) << S_RSP_FIFO_PERR_SET) +#define F_RSP_FIFO_PERR_SET V_RSP_FIFO_PERR_SET(1U) + #define A_ULP_TX_LA_RDDATA_1 0x8ed4 +#define A_ULP_TX_INT_ENABLE_6 0x8ed4 #define A_ULP_TX_LA_WRPTR_1 0x8ed8 +#define A_ULP_TX_PERR_ENABLE_6 0x8ed8 #define A_ULP_TX_LA_RESERVED_1 0x8edc +#define A_ULP_TX_INT_CAUSE_7 0x8edc + +#define S_TLS_SGE_FIFO_CORERR3 23 +#define V_TLS_SGE_FIFO_CORERR3(x) ((x) << S_TLS_SGE_FIFO_CORERR3) +#define F_TLS_SGE_FIFO_CORERR3 V_TLS_SGE_FIFO_CORERR3(1U) + +#define S_TLS_SGE_FIFO_CORERR2 22 +#define V_TLS_SGE_FIFO_CORERR2(x) ((x) << S_TLS_SGE_FIFO_CORERR2) +#define F_TLS_SGE_FIFO_CORERR2 V_TLS_SGE_FIFO_CORERR2(1U) + +#define S_TLS_SGE_FIFO_CORERR1 21 +#define V_TLS_SGE_FIFO_CORERR1(x) ((x) << S_TLS_SGE_FIFO_CORERR1) +#define F_TLS_SGE_FIFO_CORERR1 V_TLS_SGE_FIFO_CORERR1(1U) + +#define S_TLS_SGE_FIFO_CORERR0 20 +#define V_TLS_SGE_FIFO_CORERR0(x) ((x) << S_TLS_SGE_FIFO_CORERR0) +#define F_TLS_SGE_FIFO_CORERR0 V_TLS_SGE_FIFO_CORERR0(1U) + +#define S_LSO_HDR_SRAM_CERR_SET3 19 +#define V_LSO_HDR_SRAM_CERR_SET3(x) ((x) << S_LSO_HDR_SRAM_CERR_SET3) +#define F_LSO_HDR_SRAM_CERR_SET3 V_LSO_HDR_SRAM_CERR_SET3(1U) + +#define S_LSO_HDR_SRAM_CERR_SET2 18 +#define V_LSO_HDR_SRAM_CERR_SET2(x) ((x) << S_LSO_HDR_SRAM_CERR_SET2) +#define F_LSO_HDR_SRAM_CERR_SET2 V_LSO_HDR_SRAM_CERR_SET2(1U) + +#define S_LSO_HDR_SRAM_CERR_SET1 17 +#define V_LSO_HDR_SRAM_CERR_SET1(x) ((x) << S_LSO_HDR_SRAM_CERR_SET1) +#define F_LSO_HDR_SRAM_CERR_SET1 V_LSO_HDR_SRAM_CERR_SET1(1U) + +#define S_LSO_HDR_SRAM_CERR_SET0 16 +#define V_LSO_HDR_SRAM_CERR_SET0(x) ((x) << S_LSO_HDR_SRAM_CERR_SET0) +#define F_LSO_HDR_SRAM_CERR_SET0 V_LSO_HDR_SRAM_CERR_SET0(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH3_LB1 15 +#define V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB1) +#define F_CORE_CMD_FIFO_CERR_SET_CH3_LB1 V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH2_LB1 14 +#define V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB1) +#define F_CORE_CMD_FIFO_CERR_SET_CH2_LB1 V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH1_LB1 13 +#define V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB1) +#define F_CORE_CMD_FIFO_CERR_SET_CH1_LB1 V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH0_LB1 12 +#define V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB1) +#define F_CORE_CMD_FIFO_CERR_SET_CH0_LB1 V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH3_LB0 11 +#define V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB0) +#define F_CORE_CMD_FIFO_CERR_SET_CH3_LB0 V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH2_LB0 10 +#define V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB0) +#define F_CORE_CMD_FIFO_CERR_SET_CH2_LB0 V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH1_LB0 9 +#define V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB0) +#define F_CORE_CMD_FIFO_CERR_SET_CH1_LB0 V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(1U) + +#define S_CORE_CMD_FIFO_CERR_SET_CH0_LB0 8 +#define V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB0) +#define F_CORE_CMD_FIFO_CERR_SET_CH0_LB0 V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(1U) + +#define S_CQE_FIFO_CERR_SET3 7 +#define V_CQE_FIFO_CERR_SET3(x) ((x) << S_CQE_FIFO_CERR_SET3) +#define F_CQE_FIFO_CERR_SET3 V_CQE_FIFO_CERR_SET3(1U) + +#define S_CQE_FIFO_CERR_SET2 6 +#define V_CQE_FIFO_CERR_SET2(x) ((x) << S_CQE_FIFO_CERR_SET2) +#define F_CQE_FIFO_CERR_SET2 V_CQE_FIFO_CERR_SET2(1U) + +#define S_CQE_FIFO_CERR_SET1 5 +#define V_CQE_FIFO_CERR_SET1(x) ((x) << S_CQE_FIFO_CERR_SET1) +#define F_CQE_FIFO_CERR_SET1 V_CQE_FIFO_CERR_SET1(1U) + +#define S_CQE_FIFO_CERR_SET0 4 +#define V_CQE_FIFO_CERR_SET0(x) ((x) << S_CQE_FIFO_CERR_SET0) +#define F_CQE_FIFO_CERR_SET0 V_CQE_FIFO_CERR_SET0(1U) + +#define S_PRE_CQE_FIFO_CERR_SET3 3 +#define V_PRE_CQE_FIFO_CERR_SET3(x) ((x) << S_PRE_CQE_FIFO_CERR_SET3) +#define F_PRE_CQE_FIFO_CERR_SET3 V_PRE_CQE_FIFO_CERR_SET3(1U) + +#define S_PRE_CQE_FIFO_CERR_SET2 2 +#define V_PRE_CQE_FIFO_CERR_SET2(x) ((x) << S_PRE_CQE_FIFO_CERR_SET2) +#define F_PRE_CQE_FIFO_CERR_SET2 V_PRE_CQE_FIFO_CERR_SET2(1U) + +#define S_PRE_CQE_FIFO_CERR_SET1 1 +#define V_PRE_CQE_FIFO_CERR_SET1(x) ((x) << S_PRE_CQE_FIFO_CERR_SET1) +#define F_PRE_CQE_FIFO_CERR_SET1 V_PRE_CQE_FIFO_CERR_SET1(1U) + +#define S_PRE_CQE_FIFO_CERR_SET0 0 +#define V_PRE_CQE_FIFO_CERR_SET0(x) ((x) << S_PRE_CQE_FIFO_CERR_SET0) +#define F_PRE_CQE_FIFO_CERR_SET0 V_PRE_CQE_FIFO_CERR_SET0(1U) + #define A_ULP_TX_LA_RDPTR_2 0x8ee0 +#define A_ULP_TX_INT_ENABLE_7 0x8ee0 #define A_ULP_TX_LA_RDDATA_2 0x8ee4 +#define A_ULP_TX_INT_CAUSE_8 0x8ee4 + +#define S_MEM_RSP_FIFO_CERR_SET3 28 +#define V_MEM_RSP_FIFO_CERR_SET3(x) ((x) << S_MEM_RSP_FIFO_CERR_SET3) +#define F_MEM_RSP_FIFO_CERR_SET3 V_MEM_RSP_FIFO_CERR_SET3(1U) + +#define S_MEM_RSP_FIFO_CERR_SET2 27 +#define V_MEM_RSP_FIFO_CERR_SET2(x) ((x) << S_MEM_RSP_FIFO_CERR_SET2) +#define F_MEM_RSP_FIFO_CERR_SET2 V_MEM_RSP_FIFO_CERR_SET2(1U) + +#define S_MEM_RSP_FIFO_CERR_SET1 26 +#define V_MEM_RSP_FIFO_CERR_SET1(x) ((x) << S_MEM_RSP_FIFO_CERR_SET1) +#define F_MEM_RSP_FIFO_CERR_SET1 V_MEM_RSP_FIFO_CERR_SET1(1U) + +#define S_MEM_RSP_FIFO_CERR_SET0 25 +#define V_MEM_RSP_FIFO_CERR_SET0(x) ((x) << S_MEM_RSP_FIFO_CERR_SET0) +#define F_MEM_RSP_FIFO_CERR_SET0 V_MEM_RSP_FIFO_CERR_SET0(1U) + +#define S_PI_SRAM_CERR_SET3 24 +#define V_PI_SRAM_CERR_SET3(x) ((x) << S_PI_SRAM_CERR_SET3) +#define F_PI_SRAM_CERR_SET3 V_PI_SRAM_CERR_SET3(1U) + +#define S_PI_SRAM_CERR_SET2 23 +#define V_PI_SRAM_CERR_SET2(x) ((x) << S_PI_SRAM_CERR_SET2) +#define F_PI_SRAM_CERR_SET2 V_PI_SRAM_CERR_SET2(1U) + +#define S_PI_SRAM_CERR_SET1 22 +#define V_PI_SRAM_CERR_SET1(x) ((x) << S_PI_SRAM_CERR_SET1) +#define F_PI_SRAM_CERR_SET1 V_PI_SRAM_CERR_SET1(1U) + +#define S_PI_SRAM_CERR_SET0 21 +#define V_PI_SRAM_CERR_SET0(x) ((x) << S_PI_SRAM_CERR_SET0) +#define F_PI_SRAM_CERR_SET0 V_PI_SRAM_CERR_SET0(1U) + +#define S_PRE_MP_RSP_CERR_SET3 20 +#define V_PRE_MP_RSP_CERR_SET3(x) ((x) << S_PRE_MP_RSP_CERR_SET3) +#define F_PRE_MP_RSP_CERR_SET3 V_PRE_MP_RSP_CERR_SET3(1U) + +#define S_PRE_MP_RSP_CERR_SET2 19 +#define V_PRE_MP_RSP_CERR_SET2(x) ((x) << S_PRE_MP_RSP_CERR_SET2) +#define F_PRE_MP_RSP_CERR_SET2 V_PRE_MP_RSP_CERR_SET2(1U) + +#define S_PRE_MP_RSP_CERR_SET1 18 +#define V_PRE_MP_RSP_CERR_SET1(x) ((x) << S_PRE_MP_RSP_CERR_SET1) +#define F_PRE_MP_RSP_CERR_SET1 V_PRE_MP_RSP_CERR_SET1(1U) + +#define S_PRE_MP_RSP_CERR_SET0 17 +#define V_PRE_MP_RSP_CERR_SET0(x) ((x) << S_PRE_MP_RSP_CERR_SET0) +#define F_PRE_MP_RSP_CERR_SET0 V_PRE_MP_RSP_CERR_SET0(1U) + +#define S_DDR_HDR_FIFO_CERR_SET3 16 +#define V_DDR_HDR_FIFO_CERR_SET3(x) ((x) << S_DDR_HDR_FIFO_CERR_SET3) +#define F_DDR_HDR_FIFO_CERR_SET3 V_DDR_HDR_FIFO_CERR_SET3(1U) + +#define S_DDR_HDR_FIFO_CERR_SET2 15 +#define V_DDR_HDR_FIFO_CERR_SET2(x) ((x) << S_DDR_HDR_FIFO_CERR_SET2) +#define F_DDR_HDR_FIFO_CERR_SET2 V_DDR_HDR_FIFO_CERR_SET2(1U) + +#define S_DDR_HDR_FIFO_CERR_SET1 14 +#define V_DDR_HDR_FIFO_CERR_SET1(x) ((x) << S_DDR_HDR_FIFO_CERR_SET1) +#define F_DDR_HDR_FIFO_CERR_SET1 V_DDR_HDR_FIFO_CERR_SET1(1U) + +#define S_DDR_HDR_FIFO_CERR_SET0 13 +#define V_DDR_HDR_FIFO_CERR_SET0(x) ((x) << S_DDR_HDR_FIFO_CERR_SET0) +#define F_DDR_HDR_FIFO_CERR_SET0 V_DDR_HDR_FIFO_CERR_SET0(1U) + +#define S_CMD_FIFO_CERR_SET3 12 +#define V_CMD_FIFO_CERR_SET3(x) ((x) << S_CMD_FIFO_CERR_SET3) +#define F_CMD_FIFO_CERR_SET3 V_CMD_FIFO_CERR_SET3(1U) + +#define S_CMD_FIFO_CERR_SET2 11 +#define V_CMD_FIFO_CERR_SET2(x) ((x) << S_CMD_FIFO_CERR_SET2) +#define F_CMD_FIFO_CERR_SET2 V_CMD_FIFO_CERR_SET2(1U) + +#define S_CMD_FIFO_CERR_SET1 10 +#define V_CMD_FIFO_CERR_SET1(x) ((x) << S_CMD_FIFO_CERR_SET1) +#define F_CMD_FIFO_CERR_SET1 V_CMD_FIFO_CERR_SET1(1U) + +#define S_CMD_FIFO_CERR_SET0 9 +#define V_CMD_FIFO_CERR_SET0(x) ((x) << S_CMD_FIFO_CERR_SET0) +#define F_CMD_FIFO_CERR_SET0 V_CMD_FIFO_CERR_SET0(1U) + +#define S_GF_SGE_FIFO_CORERR3 8 +#define V_GF_SGE_FIFO_CORERR3(x) ((x) << S_GF_SGE_FIFO_CORERR3) +#define F_GF_SGE_FIFO_CORERR3 V_GF_SGE_FIFO_CORERR3(1U) + +#define S_GF_SGE_FIFO_CORERR2 7 +#define V_GF_SGE_FIFO_CORERR2(x) ((x) << S_GF_SGE_FIFO_CORERR2) +#define F_GF_SGE_FIFO_CORERR2 V_GF_SGE_FIFO_CORERR2(1U) + +#define S_GF_SGE_FIFO_CORERR1 6 +#define V_GF_SGE_FIFO_CORERR1(x) ((x) << S_GF_SGE_FIFO_CORERR1) +#define F_GF_SGE_FIFO_CORERR1 V_GF_SGE_FIFO_CORERR1(1U) + +#define S_GF_SGE_FIFO_CORERR0 5 +#define V_GF_SGE_FIFO_CORERR0(x) ((x) << S_GF_SGE_FIFO_CORERR0) +#define F_GF_SGE_FIFO_CORERR0 V_GF_SGE_FIFO_CORERR0(1U) + +#define S_DEDUPE_SGE_FIFO_CORERR3 4 +#define V_DEDUPE_SGE_FIFO_CORERR3(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR3) +#define F_DEDUPE_SGE_FIFO_CORERR3 V_DEDUPE_SGE_FIFO_CORERR3(1U) + +#define S_DEDUPE_SGE_FIFO_CORERR2 3 +#define V_DEDUPE_SGE_FIFO_CORERR2(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR2) +#define F_DEDUPE_SGE_FIFO_CORERR2 V_DEDUPE_SGE_FIFO_CORERR2(1U) + +#define S_DEDUPE_SGE_FIFO_CORERR1 2 +#define V_DEDUPE_SGE_FIFO_CORERR1(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR1) +#define F_DEDUPE_SGE_FIFO_CORERR1 V_DEDUPE_SGE_FIFO_CORERR1(1U) + +#define S_DEDUPE_SGE_FIFO_CORERR0 1 +#define V_DEDUPE_SGE_FIFO_CORERR0(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR0) +#define F_DEDUPE_SGE_FIFO_CORERR0 V_DEDUPE_SGE_FIFO_CORERR0(1U) + +#define S_RSP_FIFO_CERR_SET 0 +#define V_RSP_FIFO_CERR_SET(x) ((x) << S_RSP_FIFO_CERR_SET) +#define F_RSP_FIFO_CERR_SET V_RSP_FIFO_CERR_SET(1U) + #define A_ULP_TX_LA_WRPTR_2 0x8ee8 +#define A_ULP_TX_INT_ENABLE_8 0x8ee8 #define A_ULP_TX_LA_RESERVED_2 0x8eec #define A_ULP_TX_LA_RDPTR_3 0x8ef0 #define A_ULP_TX_LA_RDDATA_3 0x8ef4 @@ -29671,6 +37470,97 @@ #define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST) #define F_SHOVE_LAST V_SHOVE_LAST(1U) +#define A_ULP_TX_ACCELERATOR_CTL 0x8f90 + +#define S_FIFO_THRESHOLD 8 +#define M_FIFO_THRESHOLD 0x1fU +#define V_FIFO_THRESHOLD(x) ((x) << S_FIFO_THRESHOLD) +#define G_FIFO_THRESHOLD(x) (((x) >> S_FIFO_THRESHOLD) & M_FIFO_THRESHOLD) + +#define S_COMPRESSION_XP10DISABLECFUSE 5 +#define V_COMPRESSION_XP10DISABLECFUSE(x) ((x) << S_COMPRESSION_XP10DISABLECFUSE) +#define F_COMPRESSION_XP10DISABLECFUSE V_COMPRESSION_XP10DISABLECFUSE(1U) + +#define S_COMPRESSION_XP10DISABLE 4 +#define V_COMPRESSION_XP10DISABLE(x) ((x) << S_COMPRESSION_XP10DISABLE) +#define F_COMPRESSION_XP10DISABLE V_COMPRESSION_XP10DISABLE(1U) + +#define S_DEDUPEDISABLECFUSE 3 +#define V_DEDUPEDISABLECFUSE(x) ((x) << S_DEDUPEDISABLECFUSE) +#define F_DEDUPEDISABLECFUSE V_DEDUPEDISABLECFUSE(1U) + +#define S_DEDUPEDISABLE 2 +#define V_DEDUPEDISABLE(x) ((x) << S_DEDUPEDISABLE) +#define F_DEDUPEDISABLE V_DEDUPEDISABLE(1U) + +#define S_GFDISABLECFUSE 1 +#define V_GFDISABLECFUSE(x) ((x) << S_GFDISABLECFUSE) +#define F_GFDISABLECFUSE V_GFDISABLECFUSE(1U) + +#define S_GFDISABLE 0 +#define V_GFDISABLE(x) ((x) << S_GFDISABLE) +#define F_GFDISABLE V_GFDISABLE(1U) + +#define A_ULP_TX_XP10_IND_ADDR 0x8f94 + +#define S_XP10_CONTROL 31 +#define V_XP10_CONTROL(x) ((x) << S_XP10_CONTROL) +#define F_XP10_CONTROL V_XP10_CONTROL(1U) + +#define S_XP10_ADDR 0 +#define M_XP10_ADDR 0xfffffU +#define V_XP10_ADDR(x) ((x) << S_XP10_ADDR) +#define G_XP10_ADDR(x) (((x) >> S_XP10_ADDR) & M_XP10_ADDR) + +#define A_ULP_TX_XP10_IND_DATA 0x8f98 +#define A_ULP_TX_IWARP_PMOF_OPCODES_1 0x8f9c + +#define S_RDMA_VERIFY_RESPONSE 24 +#define M_RDMA_VERIFY_RESPONSE 0x1fU +#define V_RDMA_VERIFY_RESPONSE(x) ((x) << S_RDMA_VERIFY_RESPONSE) +#define G_RDMA_VERIFY_RESPONSE(x) (((x) >> S_RDMA_VERIFY_RESPONSE) & M_RDMA_VERIFY_RESPONSE) + +#define S_RDMA_VERIFY_REQUEST 16 +#define M_RDMA_VERIFY_REQUEST 0x1fU +#define V_RDMA_VERIFY_REQUEST(x) ((x) << S_RDMA_VERIFY_REQUEST) +#define G_RDMA_VERIFY_REQUEST(x) (((x) >> S_RDMA_VERIFY_REQUEST) & M_RDMA_VERIFY_REQUEST) + +#define S_RDMA_FLUSH_RESPONSE 8 +#define M_RDMA_FLUSH_RESPONSE 0x1fU +#define V_RDMA_FLUSH_RESPONSE(x) ((x) << S_RDMA_FLUSH_RESPONSE) +#define G_RDMA_FLUSH_RESPONSE(x) (((x) >> S_RDMA_FLUSH_RESPONSE) & M_RDMA_FLUSH_RESPONSE) + +#define S_RDMA_FLUSH_REQUEST 0 +#define M_RDMA_FLUSH_REQUEST 0x1fU +#define V_RDMA_FLUSH_REQUEST(x) ((x) << S_RDMA_FLUSH_REQUEST) +#define G_RDMA_FLUSH_REQUEST(x) (((x) >> S_RDMA_FLUSH_REQUEST) & M_RDMA_FLUSH_REQUEST) + +#define A_ULP_TX_IWARP_PMOF_OPCODES_2 0x8fa0 + +#define S_RDMA_SEND_WITH_SE_IMMEDIATE 24 +#define M_RDMA_SEND_WITH_SE_IMMEDIATE 0x1fU +#define V_RDMA_SEND_WITH_SE_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_SE_IMMEDIATE) +#define G_RDMA_SEND_WITH_SE_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_SE_IMMEDIATE) & M_RDMA_SEND_WITH_SE_IMMEDIATE) + +#define S_RDMA_SEND_WITH_IMMEDIATE 16 +#define M_RDMA_SEND_WITH_IMMEDIATE 0x1fU +#define V_RDMA_SEND_WITH_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_IMMEDIATE) +#define G_RDMA_SEND_WITH_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_IMMEDIATE) & M_RDMA_SEND_WITH_IMMEDIATE) + +#define S_RDMA_ATOMIC_WRITE_RESPONSE 8 +#define M_RDMA_ATOMIC_WRITE_RESPONSE 0x1fU +#define V_RDMA_ATOMIC_WRITE_RESPONSE(x) ((x) << S_RDMA_ATOMIC_WRITE_RESPONSE) +#define G_RDMA_ATOMIC_WRITE_RESPONSE(x) (((x) >> S_RDMA_ATOMIC_WRITE_RESPONSE) & M_RDMA_ATOMIC_WRITE_RESPONSE) + +#define S_RDMA_ATOMIC_WRITE_REQUEST 0 +#define M_RDMA_ATOMIC_WRITE_REQUEST 0x1fU +#define V_RDMA_ATOMIC_WRITE_REQUEST(x) ((x) << S_RDMA_ATOMIC_WRITE_REQUEST) +#define G_RDMA_ATOMIC_WRITE_REQUEST(x) (((x) >> S_RDMA_ATOMIC_WRITE_REQUEST) & M_RDMA_ATOMIC_WRITE_REQUEST) + +#define A_ULP_TX_NVME_TCP_TPT_LLIMIT 0x8fa4 +#define A_ULP_TX_NVME_TCP_TPT_ULIMIT 0x8fa8 +#define A_ULP_TX_NVME_TCP_PBL_LLIMIT 0x8fac +#define A_ULP_TX_NVME_TCP_PBL_ULIMIT 0x8fb0 #define A_ULP_TX_TLS_IND_CMD 0x8fb8 #define S_TLS_TX_REG_OFF_ADDR 0 @@ -29678,7 +37568,48 @@ #define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR) #define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR) +#define A_ULP_TX_DBG_CTL 0x8fb8 #define A_ULP_TX_TLS_IND_DATA 0x8fbc +#define A_ULP_TX_DBG_DATA 0x8fbc +#define A_ULP_TX_TLS_CH0_PERR_CAUSE 0xc + +#define S_GLUE_PERR 3 +#define V_GLUE_PERR(x) ((x) << S_GLUE_PERR) +#define F_GLUE_PERR V_GLUE_PERR(1U) + +#define S_DSGL_PERR 2 +#define V_DSGL_PERR(x) ((x) << S_DSGL_PERR) +#define F_DSGL_PERR V_DSGL_PERR(1U) + +#define S_SGE_PERR 1 +#define V_SGE_PERR(x) ((x) << S_SGE_PERR) +#define F_SGE_PERR V_SGE_PERR(1U) + +#define S_KEX_PERR 0 +#define V_KEX_PERR(x) ((x) << S_KEX_PERR) +#define F_KEX_PERR V_KEX_PERR(1U) + +#define A_ULP_TX_TLS_CH0_PERR_ENABLE 0x10 +#define A_ULP_TX_TLS_CH0_HMACCTRL_CFG 0x20 + +#define S_HMAC_CFG6 12 +#define M_HMAC_CFG6 0x3fU +#define V_HMAC_CFG6(x) ((x) << S_HMAC_CFG6) +#define G_HMAC_CFG6(x) (((x) >> S_HMAC_CFG6) & M_HMAC_CFG6) + +#define S_HMAC_CFG5 6 +#define M_HMAC_CFG5 0x3fU +#define V_HMAC_CFG5(x) ((x) << S_HMAC_CFG5) +#define G_HMAC_CFG5(x) (((x) >> S_HMAC_CFG5) & M_HMAC_CFG5) + +#define S_HMAC_CFG4 0 +#define M_HMAC_CFG4 0x3fU +#define V_HMAC_CFG4(x) ((x) << S_HMAC_CFG4) +#define G_HMAC_CFG4(x) (((x) >> S_HMAC_CFG4) & M_HMAC_CFG4) + +#define A_ULP_TX_TLS_CH1_PERR_CAUSE 0x4c +#define A_ULP_TX_TLS_CH1_PERR_ENABLE 0x50 +#define A_ULP_TX_TLS_CH1_HMACCTRL_CFG 0x60 /* registers for module PM_RX */ #define PM_RX_BASE_ADDR 0x8fc0 @@ -29703,6 +37634,31 @@ #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE) #define F_PREFETCH_ENABLE V_PREFETCH_ENABLE(1U) +#define S_CACHE_HOLD 13 +#define V_CACHE_HOLD(x) ((x) << S_CACHE_HOLD) +#define F_CACHE_HOLD V_CACHE_HOLD(1U) + +#define S_CACHE_INIT_DONE 12 +#define V_CACHE_INIT_DONE(x) ((x) << S_CACHE_INIT_DONE) +#define F_CACHE_INIT_DONE V_CACHE_INIT_DONE(1U) + +#define S_CACHE_DEPTH 8 +#define M_CACHE_DEPTH 0xfU +#define V_CACHE_DEPTH(x) ((x) << S_CACHE_DEPTH) +#define G_CACHE_DEPTH(x) (((x) >> S_CACHE_DEPTH) & M_CACHE_DEPTH) + +#define S_CACHE_INIT 7 +#define V_CACHE_INIT(x) ((x) << S_CACHE_INIT) +#define F_CACHE_INIT V_CACHE_INIT(1U) + +#define S_CACHE_SLEEP 6 +#define V_CACHE_SLEEP(x) ((x) << S_CACHE_SLEEP) +#define F_CACHE_SLEEP V_CACHE_SLEEP(1U) + +#define S_CACHE_BYPASS 5 +#define V_CACHE_BYPASS(x) ((x) << S_CACHE_BYPASS) +#define F_CACHE_BYPASS V_CACHE_BYPASS(1U) + #define A_PM_RX_STAT_CONFIG 0x8fc8 #define A_PM_RX_STAT_COUNT 0x8fcc #define A_PM_RX_STAT_LSB 0x8fd0 @@ -29723,6 +37679,11 @@ #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR) #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR) +#define S_T7_OSPIWRBUSY_T5 21 +#define M_T7_OSPIWRBUSY_T5 0xfU +#define V_T7_OSPIWRBUSY_T5(x) ((x) << S_T7_OSPIWRBUSY_T5) +#define G_T7_OSPIWRBUSY_T5(x) (((x) >> S_T7_OSPIWRBUSY_T5) & M_T7_OSPIWRBUSY_T5) + #define A_PM_RX_STAT_MSB 0x8fd4 #define A_PM_RX_DBG_DATA 0x8fd4 #define A_PM_RX_INT_ENABLE 0x8fd8 @@ -29843,7 +37804,36 @@ #define V_SDC_ERR(x) ((x) << S_SDC_ERR) #define F_SDC_ERR V_SDC_ERR(1U) +#define S_MASTER_PERR 31 +#define V_MASTER_PERR(x) ((x) << S_MASTER_PERR) +#define F_MASTER_PERR V_MASTER_PERR(1U) + +#define S_T7_OSPI_OVERFLOW3 30 +#define V_T7_OSPI_OVERFLOW3(x) ((x) << S_T7_OSPI_OVERFLOW3) +#define F_T7_OSPI_OVERFLOW3 V_T7_OSPI_OVERFLOW3(1U) + +#define S_T7_OSPI_OVERFLOW2 29 +#define V_T7_OSPI_OVERFLOW2(x) ((x) << S_T7_OSPI_OVERFLOW2) +#define F_T7_OSPI_OVERFLOW2 V_T7_OSPI_OVERFLOW2(1U) + #define A_PM_RX_INT_CAUSE 0x8fdc + +#define S_CACHE_SRAM_ERROR 3 +#define V_CACHE_SRAM_ERROR(x) ((x) << S_CACHE_SRAM_ERROR) +#define F_CACHE_SRAM_ERROR V_CACHE_SRAM_ERROR(1U) + +#define S_CACHE_LRU_ERROR 2 +#define V_CACHE_LRU_ERROR(x) ((x) << S_CACHE_LRU_ERROR) +#define F_CACHE_LRU_ERROR V_CACHE_LRU_ERROR(1U) + +#define S_CACHE_ISLAND_ERROR 1 +#define V_CACHE_ISLAND_ERROR(x) ((x) << S_CACHE_ISLAND_ERROR) +#define F_CACHE_ISLAND_ERROR V_CACHE_ISLAND_ERROR(1U) + +#define S_CACHE_CTRL_ERROR 0 +#define V_CACHE_CTRL_ERROR(x) ((x) << S_CACHE_CTRL_ERROR) +#define F_CACHE_CTRL_ERROR V_CACHE_CTRL_ERROR(1U) + #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002 @@ -29959,12 +37949,25 @@ #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT) #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT) +#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT0 0x1001c #define A_PM_RX_FEATURE_EN 0x1001d #define S_PIO_CH_DEFICIT_CTL_EN_RX 0 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX) #define F_PIO_CH_DEFICIT_CTL_EN_RX V_PIO_CH_DEFICIT_CTL_EN_RX(1U) +#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT1 0x1001d + +#define S_CHNL3_MAX_DEFICIT_CNT 16 +#define M_CHNL3_MAX_DEFICIT_CNT 0xffffU +#define V_CHNL3_MAX_DEFICIT_CNT(x) ((x) << S_CHNL3_MAX_DEFICIT_CNT) +#define G_CHNL3_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL3_MAX_DEFICIT_CNT) & M_CHNL3_MAX_DEFICIT_CNT) + +#define S_CHNL2_MAX_DEFICIT_CNT 0 +#define M_CHNL2_MAX_DEFICIT_CNT 0xffffU +#define V_CHNL2_MAX_DEFICIT_CNT(x) ((x) << S_CHNL2_MAX_DEFICIT_CNT) +#define G_CHNL2_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL2_MAX_DEFICIT_CNT) & M_CHNL2_MAX_DEFICIT_CNT) + #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e #define S_CH0_OSPI_DEFICIT_THRSHLD 0 @@ -30245,16 +38248,6 @@ #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL) #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL) -#define S_T6_RX_PCMD_DRDY 26 -#define M_T6_RX_PCMD_DRDY 0x3U -#define V_T6_RX_PCMD_DRDY(x) ((x) << S_T6_RX_PCMD_DRDY) -#define G_T6_RX_PCMD_DRDY(x) (((x) >> S_T6_RX_PCMD_DRDY) & M_T6_RX_PCMD_DRDY) - -#define S_T6_RX_PCMD_SRDY 24 -#define M_T6_RX_PCMD_SRDY 0x3U -#define V_T6_RX_PCMD_SRDY(x) ((x) << S_T6_RX_PCMD_SRDY) -#define G_T6_RX_PCMD_SRDY(x) (((x) >> S_T6_RX_PCMD_SRDY) & M_T6_RX_PCMD_SRDY) - #define A_PM_RX_DBG_STAT6 0x10027 #define S_RX_M_INTRNL_FIFO_CNT 4 @@ -30434,6 +38427,179 @@ #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0) #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0) +#define A_PM_RX_INT_CAUSE_MASK_HALT_2 0x10049 +#define A_PM_RX_INT_ENABLE_2 0x10060 + +#define S_CACHE_SRAM_ODD_CERR 12 +#define V_CACHE_SRAM_ODD_CERR(x) ((x) << S_CACHE_SRAM_ODD_CERR) +#define F_CACHE_SRAM_ODD_CERR V_CACHE_SRAM_ODD_CERR(1U) + +#define S_CACHE_SRAM_EVEN_CERR 11 +#define V_CACHE_SRAM_EVEN_CERR(x) ((x) << S_CACHE_SRAM_EVEN_CERR) +#define F_CACHE_SRAM_EVEN_CERR V_CACHE_SRAM_EVEN_CERR(1U) + +#define S_CACHE_LRU_LEFT_CERR 10 +#define V_CACHE_LRU_LEFT_CERR(x) ((x) << S_CACHE_LRU_LEFT_CERR) +#define F_CACHE_LRU_LEFT_CERR V_CACHE_LRU_LEFT_CERR(1U) + +#define S_CACHE_LRU_RIGHT_CERR 9 +#define V_CACHE_LRU_RIGHT_CERR(x) ((x) << S_CACHE_LRU_RIGHT_CERR) +#define F_CACHE_LRU_RIGHT_CERR V_CACHE_LRU_RIGHT_CERR(1U) + +#define S_CACHE_ISLAND_CERR 8 +#define V_CACHE_ISLAND_CERR(x) ((x) << S_CACHE_ISLAND_CERR) +#define F_CACHE_ISLAND_CERR V_CACHE_ISLAND_CERR(1U) + +#define S_OCSPI_CERR 7 +#define V_OCSPI_CERR(x) ((x) << S_OCSPI_CERR) +#define F_OCSPI_CERR V_OCSPI_CERR(1U) + +#define S_IESPI_CERR 6 +#define V_IESPI_CERR(x) ((x) << S_IESPI_CERR) +#define F_IESPI_CERR V_IESPI_CERR(1U) + +#define S_OCSPI2_RX_FRAMING_ERROR 5 +#define V_OCSPI2_RX_FRAMING_ERROR(x) ((x) << S_OCSPI2_RX_FRAMING_ERROR) +#define F_OCSPI2_RX_FRAMING_ERROR V_OCSPI2_RX_FRAMING_ERROR(1U) + +#define S_OCSPI3_RX_FRAMING_ERROR 4 +#define V_OCSPI3_RX_FRAMING_ERROR(x) ((x) << S_OCSPI3_RX_FRAMING_ERROR) +#define F_OCSPI3_RX_FRAMING_ERROR V_OCSPI3_RX_FRAMING_ERROR(1U) + +#define S_OCSPI2_TX_FRAMING_ERROR 3 +#define V_OCSPI2_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_TX_FRAMING_ERROR) +#define F_OCSPI2_TX_FRAMING_ERROR V_OCSPI2_TX_FRAMING_ERROR(1U) + +#define S_OCSPI3_TX_FRAMING_ERROR 2 +#define V_OCSPI3_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_TX_FRAMING_ERROR) +#define F_OCSPI3_TX_FRAMING_ERROR V_OCSPI3_TX_FRAMING_ERROR(1U) + +#define S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR 1 +#define V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR) +#define F_OCSPI2_OFIFO2X_TX_FRAMING_ERROR V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(1U) + +#define S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR 0 +#define V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR) +#define F_OCSPI3_OFIFO2X_TX_FRAMING_ERROR V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(1U) + +#define A_PM_RX_INT_CAUSE_2 0x10061 +#define A_PM_RX_PERR_ENABLE 0x10062 + +#define S_T7_SDC_ERR 31 +#define V_T7_SDC_ERR(x) ((x) << S_T7_SDC_ERR) +#define F_T7_SDC_ERR V_T7_SDC_ERR(1U) + +#define S_T7_MA_INTF_SDC_ERR 30 +#define V_T7_MA_INTF_SDC_ERR(x) ((x) << S_T7_MA_INTF_SDC_ERR) +#define F_T7_MA_INTF_SDC_ERR V_T7_MA_INTF_SDC_ERR(1U) + +#define S_E_PCMD_PERR 21 +#define V_E_PCMD_PERR(x) ((x) << S_E_PCMD_PERR) +#define F_E_PCMD_PERR V_E_PCMD_PERR(1U) + +#define S_CACHE_RSP_DFIFO_PERR 20 +#define V_CACHE_RSP_DFIFO_PERR(x) ((x) << S_CACHE_RSP_DFIFO_PERR) +#define F_CACHE_RSP_DFIFO_PERR V_CACHE_RSP_DFIFO_PERR(1U) + +#define S_CACHE_SRAM_ODD_PERR 19 +#define V_CACHE_SRAM_ODD_PERR(x) ((x) << S_CACHE_SRAM_ODD_PERR) +#define F_CACHE_SRAM_ODD_PERR V_CACHE_SRAM_ODD_PERR(1U) + +#define S_CACHE_SRAM_EVEN_PERR 18 +#define V_CACHE_SRAM_EVEN_PERR(x) ((x) << S_CACHE_SRAM_EVEN_PERR) +#define F_CACHE_SRAM_EVEN_PERR V_CACHE_SRAM_EVEN_PERR(1U) + +#define S_CACHE_RSVD_PERR 17 +#define V_CACHE_RSVD_PERR(x) ((x) << S_CACHE_RSVD_PERR) +#define F_CACHE_RSVD_PERR V_CACHE_RSVD_PERR(1U) + +#define S_CACHE_LRU_LEFT_PERR 16 +#define V_CACHE_LRU_LEFT_PERR(x) ((x) << S_CACHE_LRU_LEFT_PERR) +#define F_CACHE_LRU_LEFT_PERR V_CACHE_LRU_LEFT_PERR(1U) + +#define S_CACHE_LRU_RIGHT_PERR 15 +#define V_CACHE_LRU_RIGHT_PERR(x) ((x) << S_CACHE_LRU_RIGHT_PERR) +#define F_CACHE_LRU_RIGHT_PERR V_CACHE_LRU_RIGHT_PERR(1U) + +#define S_CACHE_RSP_CMD_PERR 14 +#define V_CACHE_RSP_CMD_PERR(x) ((x) << S_CACHE_RSP_CMD_PERR) +#define F_CACHE_RSP_CMD_PERR V_CACHE_RSP_CMD_PERR(1U) + +#define S_CACHE_SRAM_CMD_PERR 13 +#define V_CACHE_SRAM_CMD_PERR(x) ((x) << S_CACHE_SRAM_CMD_PERR) +#define F_CACHE_SRAM_CMD_PERR V_CACHE_SRAM_CMD_PERR(1U) + +#define S_CACHE_MA_CMD_PERR 12 +#define V_CACHE_MA_CMD_PERR(x) ((x) << S_CACHE_MA_CMD_PERR) +#define F_CACHE_MA_CMD_PERR V_CACHE_MA_CMD_PERR(1U) + +#define S_CACHE_TCAM_PERR 11 +#define V_CACHE_TCAM_PERR(x) ((x) << S_CACHE_TCAM_PERR) +#define F_CACHE_TCAM_PERR V_CACHE_TCAM_PERR(1U) + +#define S_CACHE_ISLAND_PERR 10 +#define V_CACHE_ISLAND_PERR(x) ((x) << S_CACHE_ISLAND_PERR) +#define F_CACHE_ISLAND_PERR V_CACHE_ISLAND_PERR(1U) + +#define S_MC_WCNT_FIFO_PERR 9 +#define V_MC_WCNT_FIFO_PERR(x) ((x) << S_MC_WCNT_FIFO_PERR) +#define F_MC_WCNT_FIFO_PERR V_MC_WCNT_FIFO_PERR(1U) + +#define S_MC_WDATA_FIFO_PERR 8 +#define V_MC_WDATA_FIFO_PERR(x) ((x) << S_MC_WDATA_FIFO_PERR) +#define F_MC_WDATA_FIFO_PERR V_MC_WDATA_FIFO_PERR(1U) + +#define S_MC_RCNT_FIFO_PERR 7 +#define V_MC_RCNT_FIFO_PERR(x) ((x) << S_MC_RCNT_FIFO_PERR) +#define F_MC_RCNT_FIFO_PERR V_MC_RCNT_FIFO_PERR(1U) + +#define S_MC_RDATA_FIFO_PERR 6 +#define V_MC_RDATA_FIFO_PERR(x) ((x) << S_MC_RDATA_FIFO_PERR) +#define F_MC_RDATA_FIFO_PERR V_MC_RDATA_FIFO_PERR(1U) + +#define S_TOKEN_FIFO_PERR 5 +#define V_TOKEN_FIFO_PERR(x) ((x) << S_TOKEN_FIFO_PERR) +#define F_TOKEN_FIFO_PERR V_TOKEN_FIFO_PERR(1U) + +#define S_T7_BUNDLE_LEN_PARERR 4 +#define V_T7_BUNDLE_LEN_PARERR(x) ((x) << S_T7_BUNDLE_LEN_PARERR) +#define F_T7_BUNDLE_LEN_PARERR V_T7_BUNDLE_LEN_PARERR(1U) + +#define A_PM_RX_PERR_CAUSE 0x10063 +#define A_PM_RX_EXT_CFIFO_CONFIG0 0x10070 + +#define S_CH1_PTR_MAX 17 +#define M_CH1_PTR_MAX 0x7fffU +#define V_CH1_PTR_MAX(x) ((x) << S_CH1_PTR_MAX) +#define G_CH1_PTR_MAX(x) (((x) >> S_CH1_PTR_MAX) & M_CH1_PTR_MAX) + +#define S_CH0_PTR_MAX 1 +#define M_CH0_PTR_MAX 0x7fffU +#define V_CH0_PTR_MAX(x) ((x) << S_CH0_PTR_MAX) +#define G_CH0_PTR_MAX(x) (((x) >> S_CH0_PTR_MAX) & M_CH0_PTR_MAX) + +#define S_STROBE 0 +#define V_STROBE(x) ((x) << S_STROBE) +#define F_STROBE V_STROBE(1U) + +#define A_PM_RX_EXT_CFIFO_CONFIG1 0x10071 + +#define S_CH2_PTR_MAX 1 +#define M_CH2_PTR_MAX 0x7fffU +#define V_CH2_PTR_MAX(x) ((x) << S_CH2_PTR_MAX) +#define G_CH2_PTR_MAX(x) (((x) >> S_CH2_PTR_MAX) & M_CH2_PTR_MAX) + +#define A_PM_RX_EXT_EFIFO_CONFIG0 0x10072 +#define A_PM_RX_EXT_EFIFO_CONFIG1 0x10073 +#define A_T7_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x10074 +#define A_T7_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x10075 +#define A_PM_RX_CH2_OSPI_DEFICIT_THRSHLD 0x10076 +#define A_PM_RX_CH3_OSPI_DEFICIT_THRSHLD 0x10077 +#define A_T7_PM_RX_FEATURE_EN 0x10078 +#define A_PM_RX_TCAM_BIST_CTRL 0x10080 +#define A_PM_RX_TCAM_BIST_CB_PASS 0x10081 +#define A_PM_RX_TCAM_BIST_CB_BUSY 0x10082 + /* registers for module PM_TX */ #define PM_TX_BASE_ADDR 0x8fe0 @@ -30613,6 +38779,118 @@ #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR) #define F_C_PCMD_PAR_ERROR V_C_PCMD_PAR_ERROR(1U) +#define S_T7_ZERO_C_CMD_ERROR 30 +#define V_T7_ZERO_C_CMD_ERROR(x) ((x) << S_T7_ZERO_C_CMD_ERROR) +#define F_T7_ZERO_C_CMD_ERROR V_T7_ZERO_C_CMD_ERROR(1U) + +#define S_OESPI_COR_ERR 29 +#define V_OESPI_COR_ERR(x) ((x) << S_OESPI_COR_ERR) +#define F_OESPI_COR_ERR V_OESPI_COR_ERR(1U) + +#define S_ICSPI_COR_ERR 28 +#define V_ICSPI_COR_ERR(x) ((x) << S_ICSPI_COR_ERR) +#define F_ICSPI_COR_ERR V_ICSPI_COR_ERR(1U) + +#define S_ICSPI_OVFL 24 +#define V_ICSPI_OVFL(x) ((x) << S_ICSPI_OVFL) +#define F_ICSPI_OVFL V_ICSPI_OVFL(1U) + +#define S_PCMD_LEN_OVFL3 23 +#define V_PCMD_LEN_OVFL3(x) ((x) << S_PCMD_LEN_OVFL3) +#define F_PCMD_LEN_OVFL3 V_PCMD_LEN_OVFL3(1U) + +#define S_T7_PCMD_LEN_OVFL2 22 +#define V_T7_PCMD_LEN_OVFL2(x) ((x) << S_T7_PCMD_LEN_OVFL2) +#define F_T7_PCMD_LEN_OVFL2 V_T7_PCMD_LEN_OVFL2(1U) + +#define S_T7_PCMD_LEN_OVFL1 21 +#define V_T7_PCMD_LEN_OVFL1(x) ((x) << S_T7_PCMD_LEN_OVFL1) +#define F_T7_PCMD_LEN_OVFL1 V_T7_PCMD_LEN_OVFL1(1U) + +#define S_T7_PCMD_LEN_OVFL0 20 +#define V_T7_PCMD_LEN_OVFL0(x) ((x) << S_T7_PCMD_LEN_OVFL0) +#define F_T7_PCMD_LEN_OVFL0 V_T7_PCMD_LEN_OVFL0(1U) + +#define S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR 19 +#define V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR) +#define F_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR 18 +#define V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR) +#define F_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR 17 +#define V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR) +#define F_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR 16 +#define V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR) +#define F_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI0_TX_FRAMING_ERROR 15 +#define V_T7_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_TX_FRAMING_ERROR) +#define F_T7_ICSPI0_TX_FRAMING_ERROR V_T7_ICSPI0_TX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI1_TX_FRAMING_ERROR 14 +#define V_T7_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_TX_FRAMING_ERROR) +#define F_T7_ICSPI1_TX_FRAMING_ERROR V_T7_ICSPI1_TX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI2_TX_FRAMING_ERROR 13 +#define V_T7_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_TX_FRAMING_ERROR) +#define F_T7_ICSPI2_TX_FRAMING_ERROR V_T7_ICSPI2_TX_FRAMING_ERROR(1U) + +#define S_T7_ICSPI3_TX_FRAMING_ERROR 12 +#define V_T7_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_TX_FRAMING_ERROR) +#define F_T7_ICSPI3_TX_FRAMING_ERROR V_T7_ICSPI3_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI0_RX_FRAMING_ERROR 11 +#define V_T7_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_RX_FRAMING_ERROR) +#define F_T7_OESPI0_RX_FRAMING_ERROR V_T7_OESPI0_RX_FRAMING_ERROR(1U) + +#define S_T7_OESPI1_RX_FRAMING_ERROR 10 +#define V_T7_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_RX_FRAMING_ERROR) +#define F_T7_OESPI1_RX_FRAMING_ERROR V_T7_OESPI1_RX_FRAMING_ERROR(1U) + +#define S_T7_OESPI2_RX_FRAMING_ERROR 9 +#define V_T7_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_RX_FRAMING_ERROR) +#define F_T7_OESPI2_RX_FRAMING_ERROR V_T7_OESPI2_RX_FRAMING_ERROR(1U) + +#define S_T7_OESPI3_RX_FRAMING_ERROR 8 +#define V_T7_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_RX_FRAMING_ERROR) +#define F_T7_OESPI3_RX_FRAMING_ERROR V_T7_OESPI3_RX_FRAMING_ERROR(1U) + +#define S_T7_OESPI0_TX_FRAMING_ERROR 7 +#define V_T7_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_TX_FRAMING_ERROR) +#define F_T7_OESPI0_TX_FRAMING_ERROR V_T7_OESPI0_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI1_TX_FRAMING_ERROR 6 +#define V_T7_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_TX_FRAMING_ERROR) +#define F_T7_OESPI1_TX_FRAMING_ERROR V_T7_OESPI1_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI2_TX_FRAMING_ERROR 5 +#define V_T7_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_TX_FRAMING_ERROR) +#define F_T7_OESPI2_TX_FRAMING_ERROR V_T7_OESPI2_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI3_TX_FRAMING_ERROR 4 +#define V_T7_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_TX_FRAMING_ERROR) +#define F_T7_OESPI3_TX_FRAMING_ERROR V_T7_OESPI3_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR 3 +#define V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR) +#define F_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR 2 +#define V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR) +#define F_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR 1 +#define V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR) +#define F_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U) + +#define S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR 0 +#define V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR) +#define F_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U) + #define A_PM_TX_INT_CAUSE 0x8ffc #define S_ZERO_C_CMD_ERROR 28 @@ -30624,23 +38902,51 @@ #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U) #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000 +#define A_T7_PM_TX_DBG_STAT_MSB 0x10000 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001 +#define A_T7_PM_TX_DBG_STAT_LSB 0x10001 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002 +#define A_T7_PM_TX_DBG_RSVD_FLIT_CNT 0x10002 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003 +#define A_T7_PM_TX_SDC_EN 0x10003 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004 +#define A_T7_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x10004 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005 +#define A_T7_PM_TX_INOUT_FIFO_DBG_WR 0x10005 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006 +#define A_T7_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10006 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007 +#define A_T7_PM_TX_FEATURE_EN 0x10007 + +#define S_IN_AFULL_TH 5 +#define M_IN_AFULL_TH 0x3U +#define V_IN_AFULL_TH(x) ((x) << S_IN_AFULL_TH) +#define G_IN_AFULL_TH(x) (((x) >> S_IN_AFULL_TH) & M_IN_AFULL_TH) + +#define S_PIO_FROM_CH_EN 4 +#define V_PIO_FROM_CH_EN(x) ((x) << S_PIO_FROM_CH_EN) +#define F_PIO_FROM_CH_EN V_PIO_FROM_CH_EN(1U) + #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008 +#define A_T7_PM_TX_T5_PM_TX_INT_ENABLE 0x10008 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009 +#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10009 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a +#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x1000a #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b +#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x1000b #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c +#define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x1000c #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d +#define A_T7_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x1000d #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e +#define A_T7_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x1000e #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f +#define A_T7_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x1000f #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010 +#define A_T7_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x10010 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011 +#define A_T7_PM_TX_INT_CAUSE_MASK_HALT 0x10011 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014 @@ -30722,6 +39028,48 @@ #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028 +#define A_PM_TX_PERR_ENABLE 0x10028 + +#define S_T7_1_OSPI_OVERFLOW3 23 +#define V_T7_1_OSPI_OVERFLOW3(x) ((x) << S_T7_1_OSPI_OVERFLOW3) +#define F_T7_1_OSPI_OVERFLOW3 V_T7_1_OSPI_OVERFLOW3(1U) + +#define S_T7_1_OSPI_OVERFLOW2 22 +#define V_T7_1_OSPI_OVERFLOW2(x) ((x) << S_T7_1_OSPI_OVERFLOW2) +#define F_T7_1_OSPI_OVERFLOW2 V_T7_1_OSPI_OVERFLOW2(1U) + +#define S_T7_1_OSPI_OVERFLOW1 21 +#define V_T7_1_OSPI_OVERFLOW1(x) ((x) << S_T7_1_OSPI_OVERFLOW1) +#define F_T7_1_OSPI_OVERFLOW1 V_T7_1_OSPI_OVERFLOW1(1U) + +#define S_T7_1_OSPI_OVERFLOW0 20 +#define V_T7_1_OSPI_OVERFLOW0(x) ((x) << S_T7_1_OSPI_OVERFLOW0) +#define F_T7_1_OSPI_OVERFLOW0 V_T7_1_OSPI_OVERFLOW0(1U) + +#define S_T7_BUNDLE_LEN_OVFL_EN 18 +#define V_T7_BUNDLE_LEN_OVFL_EN(x) ((x) << S_T7_BUNDLE_LEN_OVFL_EN) +#define F_T7_BUNDLE_LEN_OVFL_EN V_T7_BUNDLE_LEN_OVFL_EN(1U) + +#define S_T7_M_INTFPERREN 17 +#define V_T7_M_INTFPERREN(x) ((x) << S_T7_M_INTFPERREN) +#define F_T7_M_INTFPERREN V_T7_M_INTFPERREN(1U) + +#define S_T7_1_SDC_ERR 16 +#define V_T7_1_SDC_ERR(x) ((x) << S_T7_1_SDC_ERR) +#define F_T7_1_SDC_ERR V_T7_1_SDC_ERR(1U) + +#define S_TOKEN_PAR_ERROR 5 +#define V_TOKEN_PAR_ERROR(x) ((x) << S_TOKEN_PAR_ERROR) +#define F_TOKEN_PAR_ERROR V_TOKEN_PAR_ERROR(1U) + +#define S_BUNDLE_LEN_PAR_ERROR 4 +#define V_BUNDLE_LEN_PAR_ERROR(x) ((x) << S_BUNDLE_LEN_PAR_ERROR) +#define F_BUNDLE_LEN_PAR_ERROR V_BUNDLE_LEN_PAR_ERROR(1U) + +#define S_C_PCMD_TOKEN_PAR_ERROR 0 +#define V_C_PCMD_TOKEN_PAR_ERROR(x) ((x) << S_C_PCMD_TOKEN_PAR_ERROR) +#define F_C_PCMD_TOKEN_PAR_ERROR V_C_PCMD_TOKEN_PAR_ERROR(1U) + #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029 #define S_CH2_OSPI_DEFICIT_THRSHLD 0 @@ -30729,6 +39077,7 @@ #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD) #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD) +#define A_PM_TX_PERR_CAUSE 0x10029 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a #define S_CH3_OSPI_DEFICIT_THRSHLD 0 @@ -31462,6 +39811,7 @@ #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR) #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24 +#define A_MPS_VF_TX_MAC_DROP_PP 0x24 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c @@ -31547,6 +39897,24 @@ #define V_TXPRTY0(x) ((x) << S_TXPRTY0) #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0) +#define A_MPS_PORT_PRTY_GROUP_MAP 0x34 +#define A_MPS_PORT_TRACE_MAX_CAPTURE_SIZE 0x38 + +#define S_TX2RX 6 +#define M_TX2RX 0x7U +#define V_TX2RX(x) ((x) << S_TX2RX) +#define G_TX2RX(x) (((x) >> S_TX2RX) & M_TX2RX) + +#define S_MAC2MPS 3 +#define M_MAC2MPS 0x7U +#define V_MAC2MPS(x) ((x) << S_MAC2MPS) +#define G_MAC2MPS(x) (((x) >> S_MAC2MPS) & M_MAC2MPS) + +#define S_MPS2MAC 0 +#define M_MPS2MAC 0x7U +#define V_MPS2MAC(x) ((x) << S_MPS2MAC) +#define G_MPS2MAC(x) (((x) >> S_MPS2MAC) & M_MPS2MAC) + #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88 @@ -31578,7 +39946,9 @@ #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8 +#define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_L 0xf8 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc +#define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_H 0xfc #define A_MPS_PORT_RX_CTL 0x100 #define S_NO_RPLCT_M 20 @@ -31682,6 +40052,26 @@ #define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC) #define F_HASH_EN_MAC V_HASH_EN_MAC(1U) +#define S_TRANS_ENCAP_EN 30 +#define V_TRANS_ENCAP_EN(x) ((x) << S_TRANS_ENCAP_EN) +#define F_TRANS_ENCAP_EN V_TRANS_ENCAP_EN(1U) + +#define S_CRYPTO_DUMMY_PKT_CHK_EN 29 +#define V_CRYPTO_DUMMY_PKT_CHK_EN(x) ((x) << S_CRYPTO_DUMMY_PKT_CHK_EN) +#define F_CRYPTO_DUMMY_PKT_CHK_EN V_CRYPTO_DUMMY_PKT_CHK_EN(1U) + +#define S_PASS_HPROM 28 +#define V_PASS_HPROM(x) ((x) << S_PASS_HPROM) +#define F_PASS_HPROM V_PASS_HPROM(1U) + +#define S_PASS_PROM 27 +#define V_PASS_PROM(x) ((x) << S_PASS_PROM) +#define F_PASS_PROM V_PASS_PROM(1U) + +#define S_ENCAP_ONLY_IF_OUTER_HIT 26 +#define V_ENCAP_ONLY_IF_OUTER_HIT(x) ((x) << S_ENCAP_ONLY_IF_OUTER_HIT) +#define F_ENCAP_ONLY_IF_OUTER_HIT V_ENCAP_ONLY_IF_OUTER_HIT(1U) + #define A_MPS_PORT_RX_MTU 0x104 #define A_MPS_PORT_RX_PF_MAP 0x108 #define A_MPS_PORT_RX_VF_MAP0 0x10c @@ -31924,6 +40314,23 @@ #define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL) #define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL) +#define A_MPS_PORT_MAC_RX_DROP_EN_PP 0x16c + +#define S_PRIO 0 +#define M_PRIO 0xffU +#define V_PRIO(x) ((x) << S_PRIO) +#define G_PRIO(x) (((x) >> S_PRIO) & M_PRIO) + +#define A_MPS_PORT_RX_INT_RSS_HASH 0x170 +#define A_MPS_PORT_RX_INT_RSS_CONTROL 0x174 +#define A_MPS_PORT_RX_CNT_DBG_CTL 0x178 + +#define S_DBG_TYPE 0 +#define M_DBG_TYPE 0x1fU +#define V_DBG_TYPE(x) ((x) << S_DBG_TYPE) +#define G_DBG_TYPE(x) (((x) >> S_DBG_TYPE) & M_DBG_TYPE) + +#define A_MPS_PORT_RX_CNT_DBG 0x17c #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190 #define S_CREDIT 0 @@ -31984,6 +40391,10 @@ #define V_ON_PENDING(x) ((x) << S_ON_PENDING) #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING) +#define A_MPS_PORT_TX_MAC_DROP_PP 0x1d4 +#define A_MPS_PORT_TX_LPBK_DROP_PP 0x1d8 +#define A_MPS_PORT_TX_MAC_DROP_CNT 0x1dc +#define A_MPS_PORT_TX_LPBK_DROP_CNT 0x1e0 #define A_MPS_PORT_CLS_HASH_SRAM 0x200 #define S_VALID 20 @@ -32097,6 +40508,13 @@ #define V_TAG(x) ((x) << S_TAG) #define G_TAG(x) (((x) >> S_TAG) & M_TAG) +#define A_MPS_PF_TX_MAC_DROP_PP 0x2e4 + +#define S_T7_DROPEN 0 +#define M_T7_DROPEN 0xffU +#define V_T7_DROPEN(x) ((x) << S_T7_DROPEN) +#define G_T7_DROPEN(x) (((x) >> S_T7_DROPEN) & M_T7_DROPEN) + #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304 #define A_MPS_PORT_CLS_HASH_CTL 0x304 @@ -32112,35 +40530,9 @@ #define V_PROMISCEN(x) ((x) << S_PROMISCEN) #define F_PROMISCEN V_PROMISCEN(1U) -#define S_T6_MULTILISTEN 16 -#define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN) -#define F_T6_MULTILISTEN V_T6_MULTILISTEN(1U) - -#define S_T6_PRIORITY 13 -#define M_T6_PRIORITY 0x7U -#define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY) -#define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY) - -#define S_T6_REPLICATE 12 -#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE) -#define F_T6_REPLICATE V_T6_REPLICATE(1U) - -#define S_T6_PF 9 -#define M_T6_PF 0x7U -#define V_T6_PF(x) ((x) << S_T6_PF) -#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF) - -#define S_T6_VF_VALID 8 -#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID) -#define F_T6_VF_VALID V_T6_VF_VALID(1U) - -#define S_T6_VF 0 -#define M_T6_VF 0xffU -#define V_T6_VF(x) ((x) << S_T6_VF) -#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF) - #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c +#define A_MPS_PORT_CLS_BMC_MAC0_ADDR_L 0x30c #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310 @@ -32156,6 +40548,7 @@ #define V_MATCHALL(x) ((x) << S_MATCHALL) #define F_MATCHALL V_MATCHALL(1U) +#define A_MPS_PORT_CLS_BMC_MAC0_ADDR_H 0x310 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314 #define A_MPS_PORT_CLS_BMC_VLAN 0x314 @@ -32167,6 +40560,7 @@ #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD) #define F_VLAN_VLD V_VLAN_VLD(1U) +#define A_MPS_PORT_CLS_BMC_VLAN0 0x314 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318 #define A_MPS_PORT_CLS_CTL 0x318 @@ -32218,6 +40612,18 @@ #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL) #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL) +#define S_SMAC_INDEX_EN 17 +#define V_SMAC_INDEX_EN(x) ((x) << S_SMAC_INDEX_EN) +#define F_SMAC_INDEX_EN V_SMAC_INDEX_EN(1U) + +#define S_LPBK_TCAM2_HIT_PRIORITY 16 +#define V_LPBK_TCAM2_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM2_HIT_PRIORITY) +#define F_LPBK_TCAM2_HIT_PRIORITY V_LPBK_TCAM2_HIT_PRIORITY(1U) + +#define S_TCAM2_HIT_PRIORITY 15 +#define V_TCAM2_HIT_PRIORITY(x) ((x) << S_TCAM2_HIT_PRIORITY) +#define F_TCAM2_HIT_PRIORITY V_TCAM2_HIT_PRIORITY(1U) + #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c @@ -32238,14 +40644,23 @@ #define F_EN2 V_EN2(1U) #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324 +#define A_MPS_PORT_CLS_BMC_MAC1_ADDR_L 0x324 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328 +#define A_MPS_PORT_CLS_BMC_MAC1_ADDR_H 0x328 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c +#define A_MPS_PORT_CLS_BMC_MAC2_ADDR_L 0x32c #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330 +#define A_MPS_PORT_CLS_BMC_MAC2_ADDR_H 0x330 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334 +#define A_MPS_PORT_CLS_BMC_MAC3_ADDR_L 0x334 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338 +#define A_MPS_PORT_CLS_BMC_MAC3_ADDR_H 0x338 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c +#define A_MPS_PORT_CLS_BMC_VLAN1 0x33c #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340 +#define A_MPS_PORT_CLS_BMC_VLAN2 0x340 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344 +#define A_MPS_PORT_CLS_BMC_VLAN3 0x344 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350 @@ -32261,7 +40676,9 @@ #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380 +#define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L 0x380 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384 +#define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H 0x384 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 @@ -32393,6 +40810,22 @@ #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c +#define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L 0x620 +#define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H 0x624 +#define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L 0x628 +#define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H 0x62c +#define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L 0x630 +#define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H 0x634 +#define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L 0x638 +#define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H 0x63c +#define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L 0x640 +#define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H 0x644 +#define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L 0x648 +#define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H 0x64c +#define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L 0x650 +#define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H 0x654 +#define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L 0x658 +#define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H 0x65c #define A_MPS_CMN_CTL 0x9000 #define S_DETECT8023 3 @@ -32425,6 +40858,46 @@ #define V_SPEEDMODE(x) ((x) << S_SPEEDMODE) #define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE) +#define S_PT1_SEL_CFG 21 +#define V_PT1_SEL_CFG(x) ((x) << S_PT1_SEL_CFG) +#define F_PT1_SEL_CFG V_PT1_SEL_CFG(1U) + +#define S_BUG_42938_EN 20 +#define V_BUG_42938_EN(x) ((x) << S_BUG_42938_EN) +#define F_BUG_42938_EN V_BUG_42938_EN(1U) + +#define S_NO_BYPASS_PAUSE 19 +#define V_NO_BYPASS_PAUSE(x) ((x) << S_NO_BYPASS_PAUSE) +#define F_NO_BYPASS_PAUSE V_NO_BYPASS_PAUSE(1U) + +#define S_BYPASS_PAUSE 18 +#define V_BYPASS_PAUSE(x) ((x) << S_BYPASS_PAUSE) +#define F_BYPASS_PAUSE V_BYPASS_PAUSE(1U) + +#define S_PBUS_EN 16 +#define M_PBUS_EN 0x3U +#define V_PBUS_EN(x) ((x) << S_PBUS_EN) +#define G_PBUS_EN(x) (((x) >> S_PBUS_EN) & M_PBUS_EN) + +#define S_INIC_EN 14 +#define M_INIC_EN 0x3U +#define V_INIC_EN(x) ((x) << S_INIC_EN) +#define G_INIC_EN(x) (((x) >> S_INIC_EN) & M_INIC_EN) + +#define S_SBA_EN 12 +#define M_SBA_EN 0x3U +#define V_SBA_EN(x) ((x) << S_SBA_EN) +#define G_SBA_EN(x) (((x) >> S_SBA_EN) & M_SBA_EN) + +#define S_BG2TP_MAP_MODE 11 +#define V_BG2TP_MAP_MODE(x) ((x) << S_BG2TP_MAP_MODE) +#define F_BG2TP_MAP_MODE V_BG2TP_MAP_MODE(1U) + +#define S_MPS_LB_MODE 9 +#define M_MPS_LB_MODE 0x3U +#define V_MPS_LB_MODE(x) ((x) << S_MPS_LB_MODE) +#define G_MPS_LB_MODE(x) (((x) >> S_MPS_LB_MODE) & M_MPS_LB_MODE) + #define A_MPS_INT_ENABLE 0x9004 #define S_STATINTENB 5 @@ -32618,6 +41091,17 @@ #define A_MPS_T5_BUILD_REVISION 0x9078 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c + +#define S_VALUE_1 16 +#define M_VALUE_1 0xffffU +#define V_VALUE_1(x) ((x) << S_VALUE_1) +#define G_VALUE_1(x) (((x) >> S_VALUE_1) & M_VALUE_1) + +#define S_VALUE_0 0 +#define M_VALUE_0 0xffffU +#define V_VALUE_0(x) ((x) << S_VALUE_0) +#define G_VALUE_0(x) (((x) >> S_VALUE_0) & M_VALUE_0) + #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088 @@ -32671,11 +41155,130 @@ #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR) #define A_MPS_FPGA_BIST_CFG_P1 0x9124 - -#define S_T6_BASEADDR 0 -#define M_T6_BASEADDR 0xffffU -#define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR) -#define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR) +#define A_MPS_FPGA_BIST_CFG_P2 0x9128 +#define A_MPS_FPGA_BIST_CFG_P3 0x912c +#define A_MPS_INIC_CTL 0x9130 + +#define S_T7_RD_WRN 16 +#define V_T7_RD_WRN(x) ((x) << S_T7_RD_WRN) +#define F_T7_RD_WRN V_T7_RD_WRN(1U) + +#define A_MPS_INIC_DATA 0x9134 +#define A_MPS_TP_CSIDE_MUX_CTL_P2 0x9138 +#define A_MPS_TP_CSIDE_MUX_CTL_P3 0x913c +#define A_MPS_RED_CTL 0x9140 + +#define S_LPBK_SHIFT_0 28 +#define M_LPBK_SHIFT_0 0xfU +#define V_LPBK_SHIFT_0(x) ((x) << S_LPBK_SHIFT_0) +#define G_LPBK_SHIFT_0(x) (((x) >> S_LPBK_SHIFT_0) & M_LPBK_SHIFT_0) + +#define S_LPBK_SHIFT_1 24 +#define M_LPBK_SHIFT_1 0xfU +#define V_LPBK_SHIFT_1(x) ((x) << S_LPBK_SHIFT_1) +#define G_LPBK_SHIFT_1(x) (((x) >> S_LPBK_SHIFT_1) & M_LPBK_SHIFT_1) + +#define S_LPBK_SHIFT_2 20 +#define M_LPBK_SHIFT_2 0xfU +#define V_LPBK_SHIFT_2(x) ((x) << S_LPBK_SHIFT_2) +#define G_LPBK_SHIFT_2(x) (((x) >> S_LPBK_SHIFT_2) & M_LPBK_SHIFT_2) + +#define S_LPBK_SHIFT_3 16 +#define M_LPBK_SHIFT_3 0xfU +#define V_LPBK_SHIFT_3(x) ((x) << S_LPBK_SHIFT_3) +#define G_LPBK_SHIFT_3(x) (((x) >> S_LPBK_SHIFT_3) & M_LPBK_SHIFT_3) + +#define S_MAC_SHIFT_0 12 +#define M_MAC_SHIFT_0 0xfU +#define V_MAC_SHIFT_0(x) ((x) << S_MAC_SHIFT_0) +#define G_MAC_SHIFT_0(x) (((x) >> S_MAC_SHIFT_0) & M_MAC_SHIFT_0) + +#define S_MAC_SHIFT_1 8 +#define M_MAC_SHIFT_1 0xfU +#define V_MAC_SHIFT_1(x) ((x) << S_MAC_SHIFT_1) +#define G_MAC_SHIFT_1(x) (((x) >> S_MAC_SHIFT_1) & M_MAC_SHIFT_1) + +#define S_MAC_SHIFT_2 4 +#define M_MAC_SHIFT_2 0xfU +#define V_MAC_SHIFT_2(x) ((x) << S_MAC_SHIFT_2) +#define G_MAC_SHIFT_2(x) (((x) >> S_MAC_SHIFT_2) & M_MAC_SHIFT_2) + +#define S_MAC_SHIFT_3 0 +#define M_MAC_SHIFT_3 0xfU +#define V_MAC_SHIFT_3(x) ((x) << S_MAC_SHIFT_3) +#define G_MAC_SHIFT_3(x) (((x) >> S_MAC_SHIFT_3) & M_MAC_SHIFT_3) + +#define A_MPS_RED_EN 0x9144 + +#define S_LPBK_EN3 7 +#define V_LPBK_EN3(x) ((x) << S_LPBK_EN3) +#define F_LPBK_EN3 V_LPBK_EN3(1U) + +#define S_LPBK_EN2 6 +#define V_LPBK_EN2(x) ((x) << S_LPBK_EN2) +#define F_LPBK_EN2 V_LPBK_EN2(1U) + +#define S_LPBK_EN1 5 +#define V_LPBK_EN1(x) ((x) << S_LPBK_EN1) +#define F_LPBK_EN1 V_LPBK_EN1(1U) + +#define S_LPBK_EN0 4 +#define V_LPBK_EN0(x) ((x) << S_LPBK_EN0) +#define F_LPBK_EN0 V_LPBK_EN0(1U) + +#define S_MAC_EN3 3 +#define V_MAC_EN3(x) ((x) << S_MAC_EN3) +#define F_MAC_EN3 V_MAC_EN3(1U) + +#define S_MAC_EN2 2 +#define V_MAC_EN2(x) ((x) << S_MAC_EN2) +#define F_MAC_EN2 V_MAC_EN2(1U) + +#define S_MAC_EN1 1 +#define V_MAC_EN1(x) ((x) << S_MAC_EN1) +#define F_MAC_EN1 V_MAC_EN1(1U) + +#define S_MAC_EN0 0 +#define V_MAC_EN0(x) ((x) << S_MAC_EN0) +#define F_MAC_EN0 V_MAC_EN0(1U) + +#define A_MPS_MAC0_RED_DROP_CNT_H 0x9148 +#define A_MPS_MAC0_RED_DROP_CNT_L 0x914c +#define A_MPS_MAC1_RED_DROP_CNT_H 0x9150 +#define A_MPS_MAC1_RED_DROP_CNT_L 0x9154 +#define A_MPS_MAC2_RED_DROP_CNT_H 0x9158 +#define A_MPS_MAC2_RED_DROP_CNT_L 0x915c +#define A_MPS_MAC3_RED_DROP_CNT_H 0x9160 +#define A_MPS_MAC3_RED_DROP_CNT_L 0x9164 +#define A_MPS_LPBK0_RED_DROP_CNT_H 0x9168 +#define A_MPS_LPBK0_RED_DROP_CNT_L 0x916c +#define A_MPS_LPBK1_RED_DROP_CNT_H 0x9170 +#define A_MPS_LPBK1_RED_DROP_CNT_L 0x9174 +#define A_MPS_LPBK2_RED_DROP_CNT_H 0x9178 +#define A_MPS_LPBK2_RED_DROP_CNT_L 0x917c +#define A_MPS_LPBK3_RED_DROP_CNT_H 0x9180 +#define A_MPS_LPBK3_RED_DROP_CNT_L 0x9184 +#define A_MPS_MAC_RED_PP_DROP_EN 0x9188 + +#define S_T7_MAC3 24 +#define M_T7_MAC3 0xffU +#define V_T7_MAC3(x) ((x) << S_T7_MAC3) +#define G_T7_MAC3(x) (((x) >> S_T7_MAC3) & M_T7_MAC3) + +#define S_T7_MAC2 16 +#define M_T7_MAC2 0xffU +#define V_T7_MAC2(x) ((x) << S_T7_MAC2) +#define G_T7_MAC2(x) (((x) >> S_T7_MAC2) & M_T7_MAC2) + +#define S_T7_MAC1 8 +#define M_T7_MAC1 0xffU +#define V_T7_MAC1(x) ((x) << S_T7_MAC1) +#define G_T7_MAC1(x) (((x) >> S_T7_MAC1) & M_T7_MAC1) + +#define S_T7_MAC0 0 +#define M_T7_MAC0 0xffU +#define V_T7_MAC0(x) ((x) << S_T7_MAC0) +#define G_T7_MAC0(x) (((x) >> S_T7_MAC0) & M_T7_MAC0) #define A_MPS_TX_PRTY_SEL 0x9400 @@ -32714,6 +41317,26 @@ #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE) #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE) +#define S_T7_CH4_PRTY 16 +#define M_T7_CH4_PRTY 0x7U +#define V_T7_CH4_PRTY(x) ((x) << S_T7_CH4_PRTY) +#define G_T7_CH4_PRTY(x) (((x) >> S_T7_CH4_PRTY) & M_T7_CH4_PRTY) + +#define S_T7_CH3_PRTY 13 +#define M_T7_CH3_PRTY 0x7U +#define V_T7_CH3_PRTY(x) ((x) << S_T7_CH3_PRTY) +#define G_T7_CH3_PRTY(x) (((x) >> S_T7_CH3_PRTY) & M_T7_CH3_PRTY) + +#define S_T7_CH2_PRTY 10 +#define M_T7_CH2_PRTY 0x7U +#define V_T7_CH2_PRTY(x) ((x) << S_T7_CH2_PRTY) +#define G_T7_CH2_PRTY(x) (((x) >> S_T7_CH2_PRTY) & M_T7_CH2_PRTY) + +#define S_T7_CH1_PRTY 7 +#define M_T7_CH1_PRTY 0x7U +#define V_T7_CH1_PRTY(x) ((x) << S_T7_CH1_PRTY) +#define G_T7_CH1_PRTY(x) (((x) >> S_T7_CH1_PRTY) & M_T7_CH1_PRTY) + #define A_MPS_TX_INT_ENABLE 0x9404 #define S_PORTERR 16 @@ -32751,9 +41374,52 @@ #define V_TPFIFO(x) ((x) << S_TPFIFO) #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO) +#define S_T7_PORTERR 28 +#define V_T7_PORTERR(x) ((x) << S_T7_PORTERR) +#define F_T7_PORTERR V_T7_PORTERR(1U) + +#define S_T7_FRMERR 27 +#define V_T7_FRMERR(x) ((x) << S_T7_FRMERR) +#define F_T7_FRMERR V_T7_FRMERR(1U) + +#define S_T7_SECNTERR 26 +#define V_T7_SECNTERR(x) ((x) << S_T7_SECNTERR) +#define F_T7_SECNTERR V_T7_SECNTERR(1U) + +#define S_T7_BUBBLE 25 +#define V_T7_BUBBLE(x) ((x) << S_T7_BUBBLE) +#define F_T7_BUBBLE V_T7_BUBBLE(1U) + +#define S_TXTOKENFIFO 15 +#define M_TXTOKENFIFO 0x3ffU +#define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO) +#define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO) + +#define S_PERR_TP2MPS_TFIFO 13 +#define M_PERR_TP2MPS_TFIFO 0x3U +#define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO) +#define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO) + #define A_MPS_TX_INT_CAUSE 0x9408 #define A_MPS_TX_NCSI2MPS_CNT 0x940c #define A_MPS_TX_PERR_ENABLE 0x9410 + +#define S_PORTERRINT 28 +#define V_PORTERRINT(x) ((x) << S_PORTERRINT) +#define F_PORTERRINT V_PORTERRINT(1U) + +#define S_FRAMINGERRINT 27 +#define V_FRAMINGERRINT(x) ((x) << S_FRAMINGERRINT) +#define F_FRAMINGERRINT V_FRAMINGERRINT(1U) + +#define S_SECNTERRINT 26 +#define V_SECNTERRINT(x) ((x) << S_SECNTERRINT) +#define F_SECNTERRINT V_SECNTERRINT(1U) + +#define S_BUBBLEERRINT 25 +#define V_BUBBLEERRINT(x) ((x) << S_BUBBLEERRINT) +#define F_BUBBLEERRINT V_BUBBLEERRINT(1U) + #define A_MPS_TX_PERR_INJECT 0x9414 #define S_MPSTXMEMSEL 1 @@ -33481,6 +42147,41 @@ #define F_TXINCH0_CGEN V_TXINCH0_CGEN(1U) #define A_MPS_TX_CGEN_DYNAMIC 0x9470 +#define A_MPS_TX2RX_CH_MAP 0x9474 + +#define S_ENABLELBK_CH3 3 +#define V_ENABLELBK_CH3(x) ((x) << S_ENABLELBK_CH3) +#define F_ENABLELBK_CH3 V_ENABLELBK_CH3(1U) + +#define S_ENABLELBK_CH2 2 +#define V_ENABLELBK_CH2(x) ((x) << S_ENABLELBK_CH2) +#define F_ENABLELBK_CH2 V_ENABLELBK_CH2(1U) + +#define S_ENABLELBK_CH1 1 +#define V_ENABLELBK_CH1(x) ((x) << S_ENABLELBK_CH1) +#define F_ENABLELBK_CH1 V_ENABLELBK_CH1(1U) + +#define S_ENABLELBK_CH0 0 +#define V_ENABLELBK_CH0(x) ((x) << S_ENABLELBK_CH0) +#define F_ENABLELBK_CH0 V_ENABLELBK_CH0(1U) + +#define A_MPS_TX_DBG_CNT_CTL 0x9478 + +#define S_DBG_CNT_CTL 0 +#define M_DBG_CNT_CTL 0xffU +#define V_DBG_CNT_CTL(x) ((x) << S_DBG_CNT_CTL) +#define G_DBG_CNT_CTL(x) (((x) >> S_DBG_CNT_CTL) & M_DBG_CNT_CTL) + +#define A_MPS_TX_DBG_CNT 0x947c +#define A_MPS_TX_INT2_ENABLE 0x9498 +#define A_MPS_TX_INT2_CAUSE 0x949c +#define A_MPS_TX_PERR2_ENABLE 0x94a0 +#define A_MPS_TX_INT3_ENABLE 0x94a4 +#define A_MPS_TX_INT3_CAUSE 0x94a8 +#define A_MPS_TX_PERR3_ENABLE 0x94ac +#define A_MPS_TX_INT4_ENABLE 0x94b0 +#define A_MPS_TX_INT4_CAUSE 0x94b4 +#define A_MPS_TX_PERR4_ENABLE 0x94b8 #define A_MPS_STAT_CTL 0x9600 #define S_COUNTVFINPF 1 @@ -33810,6 +42511,7 @@ #define A_MPS_TRC_RSS_HASH 0x9804 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804 +#define A_T7_MPS_TRC_PERR_INJECT 0x9804 #define A_MPS_TRC_RSS_CONTROL 0x9808 #define S_RSSCONTROL 16 @@ -33939,6 +42641,20 @@ #define V_FILTMEM(x) ((x) << S_FILTMEM) #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM) +#define S_T7_MISCPERR 16 +#define V_T7_MISCPERR(x) ((x) << S_T7_MISCPERR) +#define F_T7_MISCPERR V_T7_MISCPERR(1U) + +#define S_T7_PKTFIFO 8 +#define M_T7_PKTFIFO 0xffU +#define V_T7_PKTFIFO(x) ((x) << S_T7_PKTFIFO) +#define G_T7_PKTFIFO(x) (((x) >> S_T7_PKTFIFO) & M_T7_PKTFIFO) + +#define S_T7_FILTMEM 0 +#define M_T7_FILTMEM 0xffU +#define V_T7_FILTMEM(x) ((x) << S_T7_FILTMEM) +#define G_T7_FILTMEM(x) (((x) >> S_T7_FILTMEM) & M_T7_FILTMEM) + #define A_MPS_TRC_INT_ENABLE 0x9858 #define S_TRCPLERRENB 9 @@ -33961,6 +42677,7 @@ #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000 +#define A_MPS_TRC_FILTER4_MATCH 0xa000 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004 #define A_MPS_T5_TRC_RSS_HASH 0xa008 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c @@ -34043,125 +42760,8 @@ #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA) #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014 - -#define S_T6_TRCMPS2TP_MACONLY 22 -#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY) -#define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U) - -#define S_T6_TRCALLMPS2TP 21 -#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP) -#define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U) - -#define S_T6_TRCALLTP2MPS 20 -#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS) -#define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U) - -#define S_T6_TRCALLVF 19 -#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF) -#define F_T6_TRCALLVF V_T6_TRCALLVF(1U) - -#define S_T6_TRC_OFLD_EN 18 -#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN) -#define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U) - -#define S_T6_VFFILTEN 17 -#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN) -#define F_T6_VFFILTEN V_T6_VFFILTEN(1U) - -#define S_T6_VFFILTMASK 9 -#define M_T6_VFFILTMASK 0xffU -#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK) -#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK) - -#define S_T6_VFFILTVALID 8 -#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID) -#define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U) - -#define S_T6_VFFILTDATA 0 -#define M_T6_VFFILTDATA 0xffU -#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA) -#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA) - #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018 - -#define S_T6_TRCMPS2TP_MACONLY 22 -#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY) -#define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U) - -#define S_T6_TRCALLMPS2TP 21 -#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP) -#define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U) - -#define S_T6_TRCALLTP2MPS 20 -#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS) -#define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U) - -#define S_T6_TRCALLVF 19 -#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF) -#define F_T6_TRCALLVF V_T6_TRCALLVF(1U) - -#define S_T6_TRC_OFLD_EN 18 -#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN) -#define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U) - -#define S_T6_VFFILTEN 17 -#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN) -#define F_T6_VFFILTEN V_T6_VFFILTEN(1U) - -#define S_T6_VFFILTMASK 9 -#define M_T6_VFFILTMASK 0xffU -#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK) -#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK) - -#define S_T6_VFFILTVALID 8 -#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID) -#define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U) - -#define S_T6_VFFILTDATA 0 -#define M_T6_VFFILTDATA 0xffU -#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA) -#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA) - #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c - -#define S_T6_TRCMPS2TP_MACONLY 22 -#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY) -#define F_T6_TRCMPS2TP_MACONLY V_T6_TRCMPS2TP_MACONLY(1U) - -#define S_T6_TRCALLMPS2TP 21 -#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP) -#define F_T6_TRCALLMPS2TP V_T6_TRCALLMPS2TP(1U) - -#define S_T6_TRCALLTP2MPS 20 -#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS) -#define F_T6_TRCALLTP2MPS V_T6_TRCALLTP2MPS(1U) - -#define S_T6_TRCALLVF 19 -#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF) -#define F_T6_TRCALLVF V_T6_TRCALLVF(1U) - -#define S_T6_TRC_OFLD_EN 18 -#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN) -#define F_T6_TRC_OFLD_EN V_T6_TRC_OFLD_EN(1U) - -#define S_T6_VFFILTEN 17 -#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN) -#define F_T6_VFFILTEN V_T6_VFFILTEN(1U) - -#define S_T6_VFFILTMASK 9 -#define M_T6_VFFILTMASK 0xffU -#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK) -#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK) - -#define S_T6_VFFILTVALID 8 -#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID) -#define F_T6_VFFILTVALID V_T6_VFFILTVALID(1U) - -#define S_T6_VFFILTDATA 0 -#define M_T6_VFFILTDATA 0xffU -#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA) -#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA) - #define A_MPS_TRC_CGEN 0xa020 #define S_MPSTRCCGEN 0 @@ -34169,6 +42769,129 @@ #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN) #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN) +#define A_MPS_TRC_FILTER4_DONT_CARE 0xa080 +#define A_MPS_TRC_FILTER5_MATCH 0xa100 +#define A_MPS_TRC_FILTER5_DONT_CARE 0xa180 +#define A_MPS_TRC_FILTER6_MATCH 0xa200 +#define A_MPS_TRC_FILTER6_DONT_CARE 0xa280 +#define A_MPS_TRC_FILTER7_MATCH 0xa300 +#define A_MPS_TRC_FILTER7_DONT_CARE 0xa380 +#define A_T7_MPS_TRC_FILTER0_RSS_HASH 0xa3f0 +#define A_T7_MPS_TRC_FILTER0_RSS_CONTROL 0xa3f4 +#define A_T7_MPS_TRC_FILTER1_RSS_HASH 0xa3f8 +#define A_T7_MPS_TRC_FILTER1_RSS_CONTROL 0xa3fc +#define A_T7_MPS_TRC_FILTER2_RSS_HASH 0xa400 +#define A_T7_MPS_TRC_FILTER2_RSS_CONTROL 0xa404 +#define A_T7_MPS_TRC_FILTER3_RSS_HASH 0xa408 +#define A_T7_MPS_TRC_FILTER3_RSS_CONTROL 0xa40c +#define A_MPS_TRC_FILTER4_RSS_HASH 0xa410 +#define A_MPS_TRC_FILTER4_RSS_CONTROL 0xa414 +#define A_MPS_TRC_FILTER5_RSS_HASH 0xa418 +#define A_MPS_TRC_FILTER5_RSS_CONTROL 0xa41c +#define A_MPS_TRC_FILTER6_RSS_HASH 0xa420 +#define A_MPS_TRC_FILTER6_RSS_CONTROL 0xa424 +#define A_MPS_TRC_FILTER7_RSS_HASH 0xa428 +#define A_MPS_TRC_FILTER7_RSS_CONTROL 0xa42c +#define A_T7_MPS_T5_TRC_RSS_HASH 0xa430 +#define A_T7_MPS_T5_TRC_RSS_CONTROL 0xa434 +#define A_T7_MPS_TRC_VF_OFF_FILTER_0 0xa438 +#define A_T7_MPS_TRC_VF_OFF_FILTER_1 0xa43c +#define A_T7_MPS_TRC_VF_OFF_FILTER_2 0xa440 +#define A_T7_MPS_TRC_VF_OFF_FILTER_3 0xa444 +#define A_MPS_TRC_VF_OFF_FILTER_4 0xa448 +#define A_MPS_TRC_VF_OFF_FILTER_5 0xa44c +#define A_MPS_TRC_VF_OFF_FILTER_6 0xa450 +#define A_MPS_TRC_VF_OFF_FILTER_7 0xa454 +#define A_T7_MPS_TRC_CGEN 0xa458 + +#define S_T7_MPSTRCCGEN 0 +#define M_T7_MPSTRCCGEN 0xffU +#define V_T7_MPSTRCCGEN(x) ((x) << S_T7_MPSTRCCGEN) +#define G_T7_MPSTRCCGEN(x) (((x) >> S_T7_MPSTRCCGEN) & M_T7_MPSTRCCGEN) + +#define A_T7_MPS_TRC_FILTER_MATCH_CTL_A 0xa460 +#define A_T7_MPS_TRC_FILTER_MATCH_CTL_B 0xa480 +#define A_T7_MPS_TRC_FILTER_RUNT_CTL 0xa4a0 +#define A_T7_MPS_TRC_FILTER_DROP 0xa4c0 +#define A_T7_MPS_TRC_INT_ENABLE 0xa4e0 + +#define S_T7_TRCPLERRENB 17 +#define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB) +#define F_T7_TRCPLERRENB V_T7_TRCPLERRENB(1U) + +#define A_T7_MPS_TRC_INT_CAUSE 0xa4e4 +#define A_T7_MPS_TRC_TIMESTAMP_L 0xa4e8 +#define A_T7_MPS_TRC_TIMESTAMP_H 0xa4ec +#define A_MPS_TRC_PERR_ENABLE2 0xa4f0 + +#define S_TRC_TF_ECC 24 +#define M_TRC_TF_ECC 0xffU +#define V_TRC_TF_ECC(x) ((x) << S_TRC_TF_ECC) +#define G_TRC_TF_ECC(x) (((x) >> S_TRC_TF_ECC) & M_TRC_TF_ECC) + +#define S_MPS2MAC_CONV_TRC_CERR 22 +#define M_MPS2MAC_CONV_TRC_CERR 0x3U +#define V_MPS2MAC_CONV_TRC_CERR(x) ((x) << S_MPS2MAC_CONV_TRC_CERR) +#define G_MPS2MAC_CONV_TRC_CERR(x) (((x) >> S_MPS2MAC_CONV_TRC_CERR) & M_MPS2MAC_CONV_TRC_CERR) + +#define S_MPS2MAC_CONV_TRC 18 +#define M_MPS2MAC_CONV_TRC 0xfU +#define V_MPS2MAC_CONV_TRC(x) ((x) << S_MPS2MAC_CONV_TRC) +#define G_MPS2MAC_CONV_TRC(x) (((x) >> S_MPS2MAC_CONV_TRC) & M_MPS2MAC_CONV_TRC) + +#define S_TF0_PERR_1 17 +#define V_TF0_PERR_1(x) ((x) << S_TF0_PERR_1) +#define F_TF0_PERR_1 V_TF0_PERR_1(1U) + +#define S_TF1_PERR_1 16 +#define V_TF1_PERR_1(x) ((x) << S_TF1_PERR_1) +#define F_TF1_PERR_1 V_TF1_PERR_1(1U) + +#define S_TF2_PERR_1 15 +#define V_TF2_PERR_1(x) ((x) << S_TF2_PERR_1) +#define F_TF2_PERR_1 V_TF2_PERR_1(1U) + +#define S_TF3_PERR_1 14 +#define V_TF3_PERR_1(x) ((x) << S_TF3_PERR_1) +#define F_TF3_PERR_1 V_TF3_PERR_1(1U) + +#define S_TF4_PERR_1 13 +#define V_TF4_PERR_1(x) ((x) << S_TF4_PERR_1) +#define F_TF4_PERR_1 V_TF4_PERR_1(1U) + +#define S_TF0_PERR_0 12 +#define V_TF0_PERR_0(x) ((x) << S_TF0_PERR_0) +#define F_TF0_PERR_0 V_TF0_PERR_0(1U) + +#define S_TF1_PERR_0 11 +#define V_TF1_PERR_0(x) ((x) << S_TF1_PERR_0) +#define F_TF1_PERR_0 V_TF1_PERR_0(1U) + +#define S_TF2_PERR_0 10 +#define V_TF2_PERR_0(x) ((x) << S_TF2_PERR_0) +#define F_TF2_PERR_0 V_TF2_PERR_0(1U) + +#define S_TF3_PERR_0 9 +#define V_TF3_PERR_0(x) ((x) << S_TF3_PERR_0) +#define F_TF3_PERR_0 V_TF3_PERR_0(1U) + +#define S_TF4_PERR_0 8 +#define V_TF4_PERR_0(x) ((x) << S_TF4_PERR_0) +#define F_TF4_PERR_0 V_TF4_PERR_0(1U) + +#define S_PERR_TF_IN_CTL 0 +#define M_PERR_TF_IN_CTL 0xffU +#define V_PERR_TF_IN_CTL(x) ((x) << S_PERR_TF_IN_CTL) +#define G_PERR_TF_IN_CTL(x) (((x) >> S_PERR_TF_IN_CTL) & M_PERR_TF_IN_CTL) + +#define A_MPS_TRC_INT_ENABLE2 0xa4f4 +#define A_MPS_TRC_INT_CAUSE2 0xa4f8 + +#define S_T7_TRC_TF_ECC 22 +#define M_T7_TRC_TF_ECC 0xffU +#define V_T7_TRC_TF_ECC(x) ((x) << S_T7_TRC_TF_ECC) +#define G_T7_TRC_TF_ECC(x) (((x) >> S_T7_TRC_TF_ECC) & M_T7_TRC_TF_ECC) + #define A_MPS_CLS_CTL 0xd000 #define S_MEMWRITEFAULT 4 @@ -34246,12 +42969,24 @@ #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM) #define F_MATCHSRAM V_MATCHSRAM(1U) +#define S_CIM2MPS_INTF_PAR 4 +#define V_CIM2MPS_INTF_PAR(x) ((x) << S_CIM2MPS_INTF_PAR) +#define F_CIM2MPS_INTF_PAR V_CIM2MPS_INTF_PAR(1U) + +#define S_TCAM_CRC_SRAM 3 +#define V_TCAM_CRC_SRAM(x) ((x) << S_TCAM_CRC_SRAM) +#define F_TCAM_CRC_SRAM V_TCAM_CRC_SRAM(1U) + #define A_MPS_CLS_INT_ENABLE 0xd024 #define S_PLERRENB 3 #define V_PLERRENB(x) ((x) << S_PLERRENB) #define F_PLERRENB V_PLERRENB(1U) +#define S_T7_PLERRENB 5 +#define V_T7_PLERRENB(x) ((x) << S_T7_PLERRENB) +#define F_T7_PLERRENB V_T7_PLERRENB(1U) + #define A_MPS_CLS_INT_CAUSE 0xd028 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c #define A_MPS_CLS_PL_TEST_DATA_H 0xd030 @@ -34314,6 +43049,25 @@ #define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF) #define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF) +#define S_T7_CLS_SPARE 30 +#define M_T7_CLS_SPARE 0x3U +#define V_T7_CLS_SPARE(x) ((x) << S_T7_CLS_SPARE) +#define G_T7_CLS_SPARE(x) (((x) >> S_T7_CLS_SPARE) & M_T7_CLS_SPARE) + +#define S_T7_1_CLS_PRIORITY 27 +#define M_T7_1_CLS_PRIORITY 0x7U +#define V_T7_1_CLS_PRIORITY(x) ((x) << S_T7_1_CLS_PRIORITY) +#define G_T7_1_CLS_PRIORITY(x) (((x) >> S_T7_1_CLS_PRIORITY) & M_T7_1_CLS_PRIORITY) + +#define S_T7_1_CLS_REPLICATE 26 +#define V_T7_1_CLS_REPLICATE(x) ((x) << S_T7_1_CLS_REPLICATE) +#define F_T7_1_CLS_REPLICATE V_T7_1_CLS_REPLICATE(1U) + +#define S_T7_1_CLS_INDEX 15 +#define M_T7_1_CLS_INDEX 0x7ffU +#define V_T7_1_CLS_INDEX(x) ((x) << S_T7_1_CLS_INDEX) +#define G_T7_1_CLS_INDEX(x) (((x) >> S_T7_1_CLS_INDEX) & M_T7_1_CLS_INDEX) + #define A_MPS_CLS_PL_TEST_CTL 0xd038 #define S_PLTESTCTL 0 @@ -34327,12 +43081,26 @@ #define F_PRTBMCCTL V_PRTBMCCTL(1U) #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100 +#define A_MPS_CLS0_MATCH_CNT_TCAM 0xd100 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104 +#define A_MPS_CLS0_MATCH_CNT_HASH 0xd104 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108 +#define A_MPS_CLS0_MATCH_CNT_BCAST 0xd108 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c +#define A_MPS_CLS0_MATCH_CNT_BMC 0xd10c #define A_MPS_CLS_MATCH_CNT_PROM 0xd110 +#define A_MPS_CLS0_MATCH_CNT_PROM 0xd110 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114 +#define A_MPS_CLS0_MATCH_CNT_HPROM 0xd114 #define A_MPS_CLS_MISS_CNT 0xd118 +#define A_MPS_CLS0_MISS_CNT 0xd118 +#define A_MPS_CLS1_MATCH_CNT_TCAM 0xd11c +#define A_MPS_CLS1_MATCH_CNT_HASH 0xd120 +#define A_MPS_CLS1_MATCH_CNT_BCAST 0xd124 +#define A_MPS_CLS1_MATCH_CNT_BMC 0xd128 +#define A_MPS_CLS1_MATCH_CNT_PROM 0xd12c +#define A_MPS_CLS1_MATCH_CNT_HPROM 0xd130 +#define A_MPS_CLS1_MISS_CNT 0xd134 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204 @@ -34428,6 +43196,15 @@ #define V_CLSTRCVF(x) ((x) << S_CLSTRCVF) #define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF) +#define S_T7_CLSTRCMATCH 23 +#define V_T7_CLSTRCMATCH(x) ((x) << S_T7_CLSTRCMATCH) +#define F_T7_CLSTRCMATCH V_T7_CLSTRCMATCH(1U) + +#define S_T7_CLSTRCINDEX 12 +#define M_T7_CLSTRCINDEX 0x7ffU +#define V_T7_CLSTRCINDEX(x) ((x) << S_T7_CLSTRCINDEX) +#define G_T7_CLSTRCINDEX(x) (((x) >> S_T7_CLSTRCINDEX) & M_T7_CLSTRCINDEX) + #define A_MPS_CLS_VLAN_TABLE 0xdfc0 #define S_VLAN_MASK 16 @@ -34536,24 +43313,6 @@ #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD) #define F_T6_SRAM_VLD V_T6_SRAM_VLD(1U) -#define S_T6_REPLICATE 12 -#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE) -#define F_T6_REPLICATE V_T6_REPLICATE(1U) - -#define S_T6_PF 9 -#define M_T6_PF 0x7U -#define V_T6_PF(x) ((x) << S_T6_PF) -#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF) - -#define S_T6_VF_VALID 8 -#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID) -#define F_T6_VF_VALID V_T6_VF_VALID(1U) - -#define S_T6_VF 0 -#define M_T6_VF 0xffU -#define V_T6_VF(x) ((x) << S_T6_VF) -#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF) - #define A_MPS_CLS_SRAM_H 0xe004 #define S_MACPARITY1 9 @@ -34580,6 +43339,41 @@ #define V_MACPARITY2(x) ((x) << S_MACPARITY2) #define F_MACPARITY2 V_MACPARITY2(1U) +#define S_SRAMWRN 31 +#define V_SRAMWRN(x) ((x) << S_SRAMWRN) +#define F_SRAMWRN V_SRAMWRN(1U) + +#define S_SRAMSPARE 27 +#define M_SRAMSPARE 0xfU +#define V_SRAMSPARE(x) ((x) << S_SRAMSPARE) +#define G_SRAMSPARE(x) (((x) >> S_SRAMSPARE) & M_SRAMSPARE) + +#define S_SRAMINDEX 16 +#define M_SRAMINDEX 0x7ffU +#define V_SRAMINDEX(x) ((x) << S_SRAMINDEX) +#define G_SRAMINDEX(x) (((x) >> S_SRAMINDEX) & M_SRAMINDEX) + +#define A_MPS_CLS_HASH_TCAM_CTL 0xe008 + +#define S_T7_CTLCMDTYPE 15 +#define V_T7_CTLCMDTYPE(x) ((x) << S_T7_CTLCMDTYPE) +#define F_T7_CTLCMDTYPE V_T7_CTLCMDTYPE(1U) + +#define S_T7_CTLXYBITSEL 12 +#define V_T7_CTLXYBITSEL(x) ((x) << S_T7_CTLXYBITSEL) +#define F_T7_CTLXYBITSEL V_T7_CTLXYBITSEL(1U) + +#define S_T7_CTLTCAMINDEX 0 +#define M_T7_CTLTCAMINDEX 0x1ffU +#define V_T7_CTLTCAMINDEX(x) ((x) << S_T7_CTLTCAMINDEX) +#define G_T7_CTLTCAMINDEX(x) (((x) >> S_T7_CTLTCAMINDEX) & M_T7_CTLTCAMINDEX) + +#define A_MPS_CLS_HASH_TCAM_DATA 0xe00c + +#define S_LKPTYPE 24 +#define V_LKPTYPE(x) ((x) << S_LKPTYPE) +#define F_LKPTYPE V_LKPTYPE(1U) + #define A_MPS_CLS_TCAM_Y_L 0xf000 #define A_MPS_CLS_TCAM_DATA0 0xf000 #define A_MPS_CLS_TCAM_Y_H 0xf004 @@ -34648,6 +43442,16 @@ #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1) #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1) +#define S_T7_CTLTCAMSEL 26 +#define M_T7_CTLTCAMSEL 0x3U +#define V_T7_CTLTCAMSEL(x) ((x) << S_T7_CTLTCAMSEL) +#define G_T7_CTLTCAMSEL(x) (((x) >> S_T7_CTLTCAMSEL) & M_T7_CTLTCAMSEL) + +#define S_T7_1_CTLTCAMINDEX 17 +#define M_T7_1_CTLTCAMINDEX 0x1ffU +#define V_T7_1_CTLTCAMINDEX(x) ((x) << S_T7_1_CTLTCAMINDEX) +#define G_T7_1_CTLTCAMINDEX(x) (((x) >> S_T7_1_CTLTCAMINDEX) & M_T7_1_CTLTCAMINDEX) + #define A_MPS_CLS_TCAM_X_H 0xf00c #define S_TCAMXH 0 @@ -34656,11 +43460,47 @@ #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH) #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010 +#define A_MPS_CLS_TCAM0_RDATA0_REQ_ID0 0xf010 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014 +#define A_MPS_CLS_TCAM0_RDATA1_REQ_ID0 0xf014 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018 +#define A_MPS_CLS_TCAM0_RDATA2_REQ_ID0 0xf018 +#define A_MPS_CLS_TCAM0_RDATA0_REQ_ID1 0xf01c #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020 +#define A_MPS_CLS_TCAM0_RDATA1_REQ_ID1 0xf020 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024 +#define A_MPS_CLS_TCAM0_RDATA2_REQ_ID1 0xf024 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028 +#define A_MPS_CLS_TCAM1_RDATA0_REQ_ID0 0xf028 +#define A_MPS_CLS_TCAM1_RDATA1_REQ_ID0 0xf02c +#define A_MPS_CLS_TCAM1_RDATA2_REQ_ID0 0xf030 +#define A_MPS_CLS_TCAM1_RDATA0_REQ_ID1 0xf034 +#define A_MPS_CLS_TCAM1_RDATA1_REQ_ID1 0xf038 +#define A_MPS_CLS_TCAM1_RDATA2_REQ_ID1 0xf03c +#define A_MPS_CLS_TCAM0_MASK_REG0 0xf040 +#define A_MPS_CLS_TCAM0_MASK_REG1 0xf044 +#define A_MPS_CLS_TCAM0_MASK_REG2 0xf048 + +#define S_MASK_0_2 0 +#define M_MASK_0_2 0xffffU +#define V_MASK_0_2(x) ((x) << S_MASK_0_2) +#define G_MASK_0_2(x) (((x) >> S_MASK_0_2) & M_MASK_0_2) + +#define A_MPS_CLS_TCAM1_MASK_REG0 0xf04c +#define A_MPS_CLS_TCAM1_MASK_REG1 0xf050 +#define A_MPS_CLS_TCAM1_MASK_REG2 0xf054 + +#define S_MASK_1_2 0 +#define M_MASK_1_2 0xffffU +#define V_MASK_1_2(x) ((x) << S_MASK_1_2) +#define G_MASK_1_2(x) (((x) >> S_MASK_1_2) & M_MASK_1_2) + +#define A_MPS_CLS_TCAM_BIST_CTRL 0xf058 +#define A_MPS_CLS_TCAM_BIST_CB_PASS 0xf05c +#define A_MPS_CLS_TCAM_BIST_CB_BUSY 0xf060 +#define A_MPS_CLS_TCAM2_MASK_REG0 0xf064 +#define A_MPS_CLS_TCAM2_MASK_REG1 0xf068 +#define A_MPS_CLS_TCAM2_MASK_REG2 0xf06c #define A_MPS_RX_CTL 0x11000 #define S_FILT_VLAN_SEL 17 @@ -34686,6 +43526,14 @@ #define V_SNF(x) ((x) << S_SNF) #define G_SNF(x) (((x) >> S_SNF) & M_SNF) +#define S_HASH_TCAM_EN 19 +#define V_HASH_TCAM_EN(x) ((x) << S_HASH_TCAM_EN) +#define F_HASH_TCAM_EN V_HASH_TCAM_EN(1U) + +#define S_SND_ORG_PFVF 18 +#define V_SND_ORG_PFVF(x) ((x) << S_SND_ORG_PFVF) +#define F_SND_ORG_PFVF V_SND_ORG_PFVF(1U) + #define A_MPS_RX_PORT_MUX_CTL 0x11004 #define S_CTL_P3 12 @@ -34877,6 +43725,11 @@ #define V_THRESH(x) ((x) << S_THRESH) #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH) +#define S_T7_THRESH 0 +#define M_T7_THRESH 0xfffU +#define V_T7_THRESH(x) ((x) << S_T7_THRESH) +#define G_T7_THRESH(x) (((x) >> S_T7_THRESH) & M_T7_THRESH) + #define A_MPS_RX_LPBK_BP1 0x11060 #define A_MPS_RX_LPBK_BP2 0x11064 #define A_MPS_RX_LPBK_BP3 0x11068 @@ -34888,6 +43741,12 @@ #define G_GAP(x) (((x) >> S_GAP) & M_GAP) #define A_MPS_RX_CHMN_CNT 0x11070 +#define A_MPS_CTL_STAT 0x11070 + +#define S_T7_CTL 0 +#define V_T7_CTL(x) ((x) << S_T7_CTL) +#define F_T7_CTL V_T7_CTL(1U) + #define A_MPS_RX_PERR_INT_CAUSE 0x11074 #define S_FF 23 @@ -34990,18 +43849,54 @@ #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT) #define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U) -#define A_MPS_RX_PERR_INT_ENABLE 0x11078 +#define S_MAC_IN_FIFO_768B 30 +#define V_MAC_IN_FIFO_768B(x) ((x) << S_MAC_IN_FIFO_768B) +#define F_MAC_IN_FIFO_768B V_MAC_IN_FIFO_768B(1U) -#define S_T6_INT_ERR_INT 24 -#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT) -#define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U) +#define S_T7_1_INT_ERR_INT 29 +#define V_T7_1_INT_ERR_INT(x) ((x) << S_T7_1_INT_ERR_INT) +#define F_T7_1_INT_ERR_INT V_T7_1_INT_ERR_INT(1U) -#define A_MPS_RX_PERR_ENABLE 0x1107c +#define S_FLOP_PERR 28 +#define V_FLOP_PERR(x) ((x) << S_FLOP_PERR) +#define F_FLOP_PERR V_FLOP_PERR(1U) -#define S_T6_INT_ERR_INT 24 -#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT) -#define F_T6_INT_ERR_INT V_T6_INT_ERR_INT(1U) +#define S_RPLC_MAP 13 +#define M_RPLC_MAP 0x1fU +#define V_RPLC_MAP(x) ((x) << S_RPLC_MAP) +#define G_RPLC_MAP(x) (((x) >> S_RPLC_MAP) & M_RPLC_MAP) + +#define S_TKN_RUNT_DROP_FIFO 12 +#define V_TKN_RUNT_DROP_FIFO(x) ((x) << S_TKN_RUNT_DROP_FIFO) +#define F_TKN_RUNT_DROP_FIFO V_TKN_RUNT_DROP_FIFO(1U) + +#define S_T7_PPM3 9 +#define M_T7_PPM3 0x7U +#define V_T7_PPM3(x) ((x) << S_T7_PPM3) +#define G_T7_PPM3(x) (((x) >> S_T7_PPM3) & M_T7_PPM3) +#define S_T7_PPM2 6 +#define M_T7_PPM2 0x7U +#define V_T7_PPM2(x) ((x) << S_T7_PPM2) +#define G_T7_PPM2(x) (((x) >> S_T7_PPM2) & M_T7_PPM2) + +#define S_T7_PPM1 3 +#define M_T7_PPM1 0x7U +#define V_T7_PPM1(x) ((x) << S_T7_PPM1) +#define G_T7_PPM1(x) (((x) >> S_T7_PPM1) & M_T7_PPM1) + +#define S_T7_PPM0 0 +#define M_T7_PPM0 0x7U +#define V_T7_PPM0(x) ((x) << S_T7_PPM0) +#define G_T7_PPM0(x) (((x) >> S_T7_PPM0) & M_T7_PPM0) + +#define A_MPS_RX_PERR_INT_ENABLE 0x11078 + +#define S_T7_2_INT_ERR_INT 30 +#define V_T7_2_INT_ERR_INT(x) ((x) << S_T7_2_INT_ERR_INT) +#define F_T7_2_INT_ERR_INT V_T7_2_INT_ERR_INT(1U) + +#define A_MPS_RX_PERR_ENABLE 0x1107c #define A_MPS_RX_PERR_INJECT 0x11080 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084 @@ -35083,8 +43978,43 @@ #define V_TH_LOW(x) ((x) << S_TH_LOW) #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW) +#define A_MPS_RX_PERR_INT_CAUSE2 0x1108c + +#define S_CRYPT2MPS_RX_INTF_FIFO 28 +#define M_CRYPT2MPS_RX_INTF_FIFO 0xfU +#define V_CRYPT2MPS_RX_INTF_FIFO(x) ((x) << S_CRYPT2MPS_RX_INTF_FIFO) +#define G_CRYPT2MPS_RX_INTF_FIFO(x) (((x) >> S_CRYPT2MPS_RX_INTF_FIFO) & M_CRYPT2MPS_RX_INTF_FIFO) + +#define S_INIC2MPS_TX0_PERR 27 +#define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR) +#define F_INIC2MPS_TX0_PERR V_INIC2MPS_TX0_PERR(1U) + +#define S_INIC2MPS_TX1_PERR 26 +#define V_INIC2MPS_TX1_PERR(x) ((x) << S_INIC2MPS_TX1_PERR) +#define F_INIC2MPS_TX1_PERR V_INIC2MPS_TX1_PERR(1U) + +#define S_XGMAC2MPS_RX0_PERR 25 +#define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR) +#define F_XGMAC2MPS_RX0_PERR V_XGMAC2MPS_RX0_PERR(1U) + +#define S_XGMAC2MPS_RX1_PERR 24 +#define V_XGMAC2MPS_RX1_PERR(x) ((x) << S_XGMAC2MPS_RX1_PERR) +#define F_XGMAC2MPS_RX1_PERR V_XGMAC2MPS_RX1_PERR(1U) + +#define S_MPS2CRYPTO_RX_INTF_FIFO 20 +#define M_MPS2CRYPTO_RX_INTF_FIFO 0xfU +#define V_MPS2CRYPTO_RX_INTF_FIFO(x) ((x) << S_MPS2CRYPTO_RX_INTF_FIFO) +#define G_MPS2CRYPTO_RX_INTF_FIFO(x) (((x) >> S_MPS2CRYPTO_RX_INTF_FIFO) & M_MPS2CRYPTO_RX_INTF_FIFO) + +#define S_RX_PRE_PROC_PERR 9 +#define M_RX_PRE_PROC_PERR 0x7ffU +#define V_RX_PRE_PROC_PERR(x) ((x) << S_RX_PRE_PROC_PERR) +#define G_RX_PRE_PROC_PERR(x) (((x) >> S_RX_PRE_PROC_PERR) & M_RX_PRE_PROC_PERR) + #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090 +#define A_MPS_RX_PERR_INT_ENABLE2 0x11090 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094 +#define A_MPS_RX_PERR_ENABLE2 0x11094 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098 #define A_MPS_RX_REPL_CTL 0x11098 @@ -35126,10 +44056,13 @@ #define A_MPS_RX_PT_ARB1 0x110ac #define A_MPS_RX_PT_ARB2 0x110b0 +#define A_T7_MPS_RX_PT_ARB4 0x110b0 #define A_MPS_RX_PT_ARB3 0x110b4 #define A_T6_MPS_PF_OUT_EN 0x110b4 +#define A_T7_MPS_PF_OUT_EN 0x110b4 #define A_MPS_RX_PT_ARB4 0x110b8 #define A_T6_MPS_BMC_MTU 0x110b8 +#define A_T7_MPS_BMC_MTU 0x110b8 #define A_MPS_PF_OUT_EN 0x110bc #define S_OUTEN 0 @@ -35138,6 +44071,7 @@ #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN) #define A_T6_MPS_BMC_PKT_CNT 0x110bc +#define A_T7_MPS_BMC_PKT_CNT 0x110bc #define A_MPS_BMC_MTU 0x110c0 #define S_MTU 0 @@ -35146,6 +44080,7 @@ #define G_MTU(x) (((x) >> S_MTU) & M_MTU) #define A_T6_MPS_BMC_BYTE_CNT 0x110c0 +#define A_T7_MPS_BMC_BYTE_CNT 0x110c0 #define A_MPS_BMC_PKT_CNT 0x110c4 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4 @@ -35154,6 +44089,7 @@ #define V_T6_PFVF(x) ((x) << S_T6_PFVF) #define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF) +#define A_T7_MPS_PFVF_ATRB_CTL 0x110c4 #define A_MPS_BMC_BYTE_CNT 0x110c8 #define A_T6_MPS_PFVF_ATRB 0x110c8 @@ -35161,6 +44097,12 @@ #define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE) #define F_FULL_FRAME_MODE V_FULL_FRAME_MODE(1U) +#define A_T7_MPS_PFVF_ATRB 0x110c8 + +#define S_EXTRACT_DEL_VLAN 31 +#define V_EXTRACT_DEL_VLAN(x) ((x) << S_EXTRACT_DEL_VLAN) +#define F_EXTRACT_DEL_VLAN V_EXTRACT_DEL_VLAN(1U) + #define A_MPS_PFVF_ATRB_CTL 0x110cc #define S_RD_WRN 31 @@ -35173,6 +44115,7 @@ #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF) #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc +#define A_T7_MPS_PFVF_ATRB_FLTR0 0x110cc #define A_MPS_PFVF_ATRB 0x110d0 #define S_ATTR_PF 28 @@ -35193,6 +44136,7 @@ #define F_ATTR_MODE V_ATTR_MODE(1U) #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0 +#define A_T7_MPS_PFVF_ATRB_FLTR1 0x110d0 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4 #define S_VLAN_EN 16 @@ -35205,36 +44149,58 @@ #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID) #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4 +#define A_T7_MPS_PFVF_ATRB_FLTR2 0x110d4 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8 +#define A_T7_MPS_PFVF_ATRB_FLTR3 0x110d8 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc +#define A_T7_MPS_PFVF_ATRB_FLTR4 0x110dc #define A_MPS_PFVF_ATRB_FLTR3 0x110e0 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0 +#define A_T7_MPS_PFVF_ATRB_FLTR5 0x110e0 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4 +#define A_T7_MPS_PFVF_ATRB_FLTR6 0x110e4 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8 +#define A_T7_MPS_PFVF_ATRB_FLTR7 0x110e8 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec +#define A_T7_MPS_PFVF_ATRB_FLTR8 0x110ec #define A_MPS_PFVF_ATRB_FLTR7 0x110f0 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0 +#define A_T7_MPS_PFVF_ATRB_FLTR9 0x110f0 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4 +#define A_T7_MPS_PFVF_ATRB_FLTR10 0x110f4 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8 +#define A_T7_MPS_PFVF_ATRB_FLTR11 0x110f8 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc +#define A_T7_MPS_PFVF_ATRB_FLTR12 0x110fc #define A_MPS_PFVF_ATRB_FLTR11 0x11100 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100 +#define A_T7_MPS_PFVF_ATRB_FLTR13 0x11100 #define A_MPS_PFVF_ATRB_FLTR12 0x11104 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104 +#define A_T7_MPS_PFVF_ATRB_FLTR14 0x11104 #define A_MPS_PFVF_ATRB_FLTR13 0x11108 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108 +#define A_T7_MPS_PFVF_ATRB_FLTR15 0x11108 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c #define A_T6_MPS_RPLC_MAP_CTL 0x1110c +#define A_T7_MPS_RPLC_MAP_CTL 0x1110c + +#define S_T7_RPLC_MAP_ADDR 0 +#define M_T7_RPLC_MAP_ADDR 0xfffU +#define V_T7_RPLC_MAP_ADDR(x) ((x) << S_T7_RPLC_MAP_ADDR) +#define G_T7_RPLC_MAP_ADDR(x) (((x) >> S_T7_RPLC_MAP_ADDR) & M_T7_RPLC_MAP_ADDR) + #define A_MPS_PFVF_ATRB_FLTR15 0x11110 #define A_T6_MPS_PF_RPLCT_MAP 0x11110 +#define A_T7_MPS_PF_RPLCT_MAP 0x11110 #define A_MPS_RPLC_MAP_CTL 0x11114 #define S_RPLC_MAP_ADDR 0 @@ -35243,6 +44209,7 @@ #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR) #define A_T6_MPS_VF_RPLCT_MAP0 0x11114 +#define A_T7_MPS_VF_RPLCT_MAP0 0x11114 #define A_MPS_PF_RPLCT_MAP 0x11118 #define S_PF_EN 0 @@ -35251,10 +44218,13 @@ #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN) #define A_T6_MPS_VF_RPLCT_MAP1 0x11118 +#define A_T7_MPS_VF_RPLCT_MAP1 0x11118 #define A_MPS_VF_RPLCT_MAP0 0x1111c #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c +#define A_T7_MPS_VF_RPLCT_MAP2 0x1111c #define A_MPS_VF_RPLCT_MAP1 0x11120 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120 +#define A_T7_MPS_VF_RPLCT_MAP3 0x11120 #define A_MPS_VF_RPLCT_MAP2 0x11124 #define A_MPS_VF_RPLCT_MAP3 0x11128 #define A_MPS_MEM_DBG_CTL 0x1112c @@ -35629,9 +44599,13 @@ #define V_CONG_TH(x) ((x) << S_CONG_TH) #define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH) +#define A_MPS_RX_LPBK_BG_PG_CNT2 0x11220 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224 +#define A_MPS_RX_LPBK_BG_PG_CNT3 0x11224 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228 +#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11228 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c +#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG1 0x1122c #define A_MPS_RX_GRE_PROT_TYPE 0x11230 #define S_NVGRE_EN 9 @@ -35647,6 +44621,7 @@ #define V_GRE(x) ((x) << S_GRE) #define G_GRE(x) (((x) >> S_GRE) & M_GRE) +#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11230 #define A_MPS_RX_VXLAN_TYPE 0x11234 #define S_VXLAN_EN 16 @@ -35658,6 +44633,7 @@ #define V_VXLAN(x) ((x) << S_VXLAN) #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN) +#define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG3 0x11234 #define A_MPS_RX_GENEVE_TYPE 0x11238 #define S_GENEVE_EN 16 @@ -35669,12 +44645,14 @@ #define V_GENEVE(x) ((x) << S_GENEVE) #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE) +#define A_T7_MPS_RX_GRE_PROT_TYPE 0x11238 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c #define S_T6_IVLAN_EN 16 #define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN) #define F_T6_IVLAN_EN V_T6_IVLAN_EN(1U) +#define A_T7_MPS_RX_VXLAN_TYPE 0x1123c #define A_MPS_RX_ENCAP_NVGRE 0x11240 #define S_ETYPE_EN 16 @@ -35686,13 +44664,9 @@ #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE) #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE) +#define A_T7_MPS_RX_GENEVE_TYPE 0x11240 #define A_MPS_RX_ENCAP_GENEVE 0x11244 - -#define S_T6_ETYPE 0 -#define M_T6_ETYPE 0xffffU -#define V_T6_ETYPE(x) ((x) << S_T6_ETYPE) -#define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE) - +#define A_T7_MPS_RX_INNER_HDR_IVLAN 0x11244 #define A_MPS_RX_TCP 0x11248 #define S_PROT_TYPE_EN 8 @@ -35704,8 +44678,11 @@ #define V_PROT_TYPE(x) ((x) << S_PROT_TYPE) #define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE) +#define A_T7_MPS_RX_ENCAP_NVGRE 0x11248 #define A_MPS_RX_UDP 0x1124c +#define A_T7_MPS_RX_ENCAP_GENEVE 0x1124c #define A_MPS_RX_PAUSE 0x11250 +#define A_T7_MPS_RX_TCP 0x11250 #define A_MPS_RX_LENGTH 0x11254 #define S_SAP_VALUE 16 @@ -35718,6 +44695,7 @@ #define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE) #define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE) +#define A_T7_MPS_RX_UDP 0x11254 #define A_MPS_RX_CTL_ORG 0x11258 #define S_CTL_VALUE 24 @@ -35730,6 +44708,7 @@ #define V_ORG_VALUE(x) ((x) << S_ORG_VALUE) #define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE) +#define A_T7_MPS_RX_PAUSE 0x11258 #define A_MPS_RX_IPV4 0x1125c #define S_ETYPE_IPV4 0 @@ -35737,6 +44716,7 @@ #define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4) #define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4) +#define A_T7_MPS_RX_LENGTH 0x1125c #define A_MPS_RX_IPV6 0x11260 #define S_ETYPE_IPV6 0 @@ -35744,6 +44724,7 @@ #define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6) #define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6) +#define A_T7_MPS_RX_CTL_ORG 0x11260 #define A_MPS_RX_TTL 0x11264 #define S_TTL_IPV4 10 @@ -35764,6 +44745,7 @@ #define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6) #define F_TTL_CHK_EN_IPV6 V_TTL_CHK_EN_IPV6(1U) +#define A_T7_MPS_RX_IPV4 0x11264 #define A_MPS_RX_DEFAULT_VNI 0x11268 #define S_VNI 0 @@ -35771,6 +44753,7 @@ #define V_VNI(x) ((x) << S_VNI) #define G_VNI(x) (((x) >> S_VNI) & M_VNI) +#define A_T7_MPS_RX_IPV6 0x11268 #define A_MPS_RX_PRS_CTL 0x1126c #define S_CTL_CHK_EN 28 @@ -35821,6 +44804,7 @@ #define V_DIP_EN(x) ((x) << S_DIP_EN) #define F_DIP_EN V_DIP_EN(1U) +#define A_T7_MPS_RX_TTL 0x1126c #define A_MPS_RX_PRS_CTL_2 0x11270 #define S_EN_UDP_CSUM_CHK 4 @@ -35843,7 +44827,9 @@ #define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT) #define F_T6_IPV6_UDP_CSUM_COMPAT V_T6_IPV6_UDP_CSUM_COMPAT(1U) +#define A_T7_MPS_RX_DEFAULT_VNI 0x11270 #define A_MPS_RX_MPS2NCSI_CNT 0x11274 +#define A_T7_MPS_RX_PRS_CTL 0x11274 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278 #define S_T6_LEN 0 @@ -35851,38 +44837,222 @@ #define V_T6_LEN(x) ((x) << S_T6_LEN) #define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN) +#define A_T7_MPS_RX_PRS_CTL_2 0x11278 + +#define S_IP_EXT_HDR_EN 5 +#define V_IP_EXT_HDR_EN(x) ((x) << S_IP_EXT_HDR_EN) +#define F_IP_EXT_HDR_EN V_IP_EXT_HDR_EN(1U) + #define A_MPS_RX_PAUSE_DA_H 0x1127c +#define A_T7_MPS_RX_MPS2NCSI_CNT 0x1127c #define A_MPS_RX_PAUSE_DA_L 0x11280 +#define A_T7_MPS_RX_MAX_TNL_HDR_LEN 0x11280 + +#define S_MPS_TNL_HDR_LEN_MODE 9 +#define V_MPS_TNL_HDR_LEN_MODE(x) ((x) << S_MPS_TNL_HDR_LEN_MODE) +#define F_MPS_TNL_HDR_LEN_MODE V_MPS_TNL_HDR_LEN_MODE(1U) + +#define S_MPS_MAX_TNL_HDR_LEN 0 +#define M_MPS_MAX_TNL_HDR_LEN 0x1ffU +#define V_MPS_MAX_TNL_HDR_LEN(x) ((x) << S_MPS_MAX_TNL_HDR_LEN) +#define G_MPS_MAX_TNL_HDR_LEN(x) (((x) >> S_MPS_MAX_TNL_HDR_LEN) & M_MPS_MAX_TNL_HDR_LEN) + #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284 +#define A_T7_MPS_RX_PAUSE_DA_H 0x11284 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288 +#define A_T7_MPS_RX_PAUSE_DA_L 0x11288 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c +#define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC0 0x1128c #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290 +#define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11290 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294 +#define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC0 0x11294 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298 +#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11298 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c +#define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC1 0x1129c #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0 +#define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC1 0x112a0 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4 +#define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC1 0x112a4 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8 +#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a8 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac +#define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112ac #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0 +#define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112b0 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4 +#define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112b4 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8 +#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b8 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc +#define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112bc #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0 +#define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112c0 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4 +#define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112c4 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8 +#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c8 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc +#define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112cc #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0 +#define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112d0 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4 +#define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112d4 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8 +#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d8 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc +#define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112dc #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0 +#define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112e0 +#define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112e4 +#define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e8 +#define A_MPS_RX_ESP 0x112ec +#define A_MPS_EN_LPBK_BLK_SNDR 0x112f0 + +#define S_EN_CH3 3 +#define V_EN_CH3(x) ((x) << S_EN_CH3) +#define F_EN_CH3 V_EN_CH3(1U) + +#define S_EN_CH2 2 +#define V_EN_CH2(x) ((x) << S_EN_CH2) +#define F_EN_CH2 V_EN_CH2(1U) + +#define S_EN_CH1 1 +#define V_EN_CH1(x) ((x) << S_EN_CH1) +#define F_EN_CH1 V_EN_CH1(1U) + +#define S_EN_CH0 0 +#define V_EN_CH0(x) ((x) << S_EN_CH0) +#define F_EN_CH0 V_EN_CH0(1U) + #define A_MPS_VF_RPLCT_MAP4 0x11300 #define A_MPS_VF_RPLCT_MAP5 0x11304 #define A_MPS_VF_RPLCT_MAP6 0x11308 #define A_MPS_VF_RPLCT_MAP7 0x1130c +#define A_MPS_RX_PERR_INT_CAUSE3 0x11310 +#define A_MPS_RX_PERR_INT_ENABLE3 0x11314 +#define A_MPS_RX_PERR_ENABLE3 0x11318 +#define A_MPS_RX_PERR_INT_CAUSE4 0x1131c + +#define S_CLS 20 +#define M_CLS 0x3fU +#define V_CLS(x) ((x) << S_CLS) +#define G_CLS(x) (((x) >> S_CLS) & M_CLS) + +#define S_RX_PRE_PROC 16 +#define M_RX_PRE_PROC 0xfU +#define V_RX_PRE_PROC(x) ((x) << S_RX_PRE_PROC) +#define G_RX_PRE_PROC(x) (((x) >> S_RX_PRE_PROC) & M_RX_PRE_PROC) + +#define S_PPROC3 12 +#define M_PPROC3 0xfU +#define V_PPROC3(x) ((x) << S_PPROC3) +#define G_PPROC3(x) (((x) >> S_PPROC3) & M_PPROC3) + +#define S_PPROC2 8 +#define M_PPROC2 0xfU +#define V_PPROC2(x) ((x) << S_PPROC2) +#define G_PPROC2(x) (((x) >> S_PPROC2) & M_PPROC2) + +#define S_PPROC1 4 +#define M_PPROC1 0xfU +#define V_PPROC1(x) ((x) << S_PPROC1) +#define G_PPROC1(x) (((x) >> S_PPROC1) & M_PPROC1) + +#define S_PPROC0 0 +#define M_PPROC0 0xfU +#define V_PPROC0(x) ((x) << S_PPROC0) +#define G_PPROC0(x) (((x) >> S_PPROC0) & M_PPROC0) + +#define A_MPS_RX_PERR_INT_ENABLE4 0x11320 +#define A_MPS_RX_PERR_ENABLE4 0x11324 +#define A_MPS_RX_PERR_INT_CAUSE5 0x11328 + +#define S_MPS2CRYP_RX_FIFO 26 +#define M_MPS2CRYP_RX_FIFO 0xfU +#define V_MPS2CRYP_RX_FIFO(x) ((x) << S_MPS2CRYP_RX_FIFO) +#define G_MPS2CRYP_RX_FIFO(x) (((x) >> S_MPS2CRYP_RX_FIFO) & M_MPS2CRYP_RX_FIFO) + +#define S_RX_OUT 20 +#define M_RX_OUT 0x3fU +#define V_RX_OUT(x) ((x) << S_RX_OUT) +#define G_RX_OUT(x) (((x) >> S_RX_OUT) & M_RX_OUT) + +#define S_MEM_WRAP 0 +#define M_MEM_WRAP 0xfffffU +#define V_MEM_WRAP(x) ((x) << S_MEM_WRAP) +#define G_MEM_WRAP(x) (((x) >> S_MEM_WRAP) & M_MEM_WRAP) + +#define A_MPS_RX_PERR_INT_ENABLE5 0x1132c +#define A_MPS_RX_PERR_ENABLE5 0x11330 +#define A_MPS_RX_PERR_INT_CAUSE6 0x11334 + +#define S_MPS_RX_MEM_WRAP 0 +#define M_MPS_RX_MEM_WRAP 0x1ffffffU +#define V_MPS_RX_MEM_WRAP(x) ((x) << S_MPS_RX_MEM_WRAP) +#define G_MPS_RX_MEM_WRAP(x) (((x) >> S_MPS_RX_MEM_WRAP) & M_MPS_RX_MEM_WRAP) + +#define A_MPS_RX_PERR_INT_ENABLE6 0x11338 +#define A_MPS_RX_PERR_ENABLE6 0x1133c +#define A_MPS_RX_CNT_NVGRE_PKT_MAC2 0x11408 +#define A_MPS_RX_CNT_VXLAN_PKT_MAC2 0x1140c +#define A_MPS_RX_CNT_GENEVE_PKT_MAC2 0x11410 +#define A_MPS_RX_CNT_TNL_ERR_PKT_MAC2 0x11414 +#define A_MPS_RX_CNT_NVGRE_PKT_MAC3 0x11418 +#define A_MPS_RX_CNT_VXLAN_PKT_MAC3 0x1141c +#define A_MPS_RX_CNT_GENEVE_PKT_MAC3 0x11420 +#define A_MPS_RX_CNT_TNL_ERR_PKT_MAC3 0x11424 +#define A_MPS_RX_CNT_NVGRE_PKT_LPBK2 0x11428 +#define A_MPS_RX_CNT_VXLAN_PKT_LPBK2 0x1142c +#define A_MPS_RX_CNT_GENEVE_PKT_LPBK2 0x11430 +#define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK2 0x11434 +#define A_MPS_RX_CNT_NVGRE_PKT_LPBK3 0x11438 +#define A_MPS_RX_CNT_VXLAN_PKT_LPBK3 0x1143c +#define A_MPS_RX_CNT_GENEVE_PKT_LPBK3 0x11440 +#define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK3 0x11444 +#define A_MPS_RX_CNT_NVGRE_PKT_TO_TP2 0x11448 +#define A_MPS_RX_CNT_VXLAN_PKT_TO_TP2 0x1144c +#define A_MPS_RX_CNT_GENEVE_PKT_TO_TP2 0x11450 +#define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP2 0x11454 +#define A_MPS_RX_CNT_NVGRE_PKT_TO_TP3 0x11458 +#define A_MPS_RX_CNT_VXLAN_PKT_TO_TP3 0x1145c +#define A_MPS_RX_CNT_GENEVE_PKT_TO_TP3 0x11460 +#define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP3 0x11464 +#define A_T7_MPS_RX_PT_ARB2 0x11468 +#define A_T7_MPS_RX_PT_ARB3 0x1146c #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000 +#define A_MPS_CLS_DIP_ID_TABLE_CTL 0x12000 + +#define S_DIP_VLD 12 +#define V_DIP_VLD(x) ((x) << S_DIP_VLD) +#define F_DIP_VLD V_DIP_VLD(1U) + +#define S_DIP_TYPE 11 +#define V_DIP_TYPE(x) ((x) << S_DIP_TYPE) +#define F_DIP_TYPE V_DIP_TYPE(1U) + +#define S_DIP_WRN 10 +#define V_DIP_WRN(x) ((x) << S_DIP_WRN) +#define F_DIP_WRN V_DIP_WRN(1U) + +#define S_DIP_SEG 8 +#define M_DIP_SEG 0x3U +#define V_DIP_SEG(x) ((x) << S_DIP_SEG) +#define G_DIP_SEG(x) (((x) >> S_DIP_SEG) & M_DIP_SEG) + +#define S_DIP_TBL_RSVD1 5 +#define M_DIP_TBL_RSVD1 0x7U +#define V_DIP_TBL_RSVD1(x) ((x) << S_DIP_TBL_RSVD1) +#define G_DIP_TBL_RSVD1(x) (((x) >> S_DIP_TBL_RSVD1) & M_DIP_TBL_RSVD1) + +#define S_DIP_TBL_ADDR 0 +#define M_DIP_TBL_ADDR 0x1fU +#define V_DIP_TBL_ADDR(x) ((x) << S_DIP_TBL_ADDR) +#define G_DIP_TBL_ADDR(x) (((x) >> S_DIP_TBL_ADDR) & M_DIP_TBL_ADDR) + #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004 +#define A_MPS_CLS_DIP_ID_TABLE_DATA 0x12004 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028 @@ -35892,6 +45062,226 @@ #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c #define A_MPS_RX_HASH_LKP_TABLE 0x12060 +#define A_MPS_CLS_DROP_DMAC0_L 0x12070 +#define A_MPS_CLS_DROP_DMAC0_H 0x12074 + +#define S_DMAC 0 +#define M_DMAC 0xffffU +#define V_DMAC(x) ((x) << S_DMAC) +#define G_DMAC(x) (((x) >> S_DMAC) & M_DMAC) + +#define A_MPS_CLS_DROP_DMAC1_L 0x12078 +#define A_MPS_CLS_DROP_DMAC1_H 0x1207c +#define A_MPS_CLS_DROP_DMAC2_L 0x12080 +#define A_MPS_CLS_DROP_DMAC2_H 0x12084 +#define A_MPS_CLS_DROP_DMAC3_L 0x12088 +#define A_MPS_CLS_DROP_DMAC3_H 0x1208c +#define A_MPS_CLS_DROP_DMAC4_L 0x12090 +#define A_MPS_CLS_DROP_DMAC4_H 0x12094 +#define A_MPS_CLS_DROP_DMAC5_L 0x12098 +#define A_MPS_CLS_DROP_DMAC5_H 0x1209c +#define A_MPS_CLS_DROP_DMAC6_L 0x120a0 +#define A_MPS_CLS_DROP_DMAC6_H 0x120a4 +#define A_MPS_CLS_DROP_DMAC7_L 0x120a8 +#define A_MPS_CLS_DROP_DMAC7_H 0x120ac +#define A_MPS_CLS_DROP_DMAC8_L 0x120b0 +#define A_MPS_CLS_DROP_DMAC8_H 0x120b4 +#define A_MPS_CLS_DROP_DMAC9_L 0x120b8 +#define A_MPS_CLS_DROP_DMAC9_H 0x120bc +#define A_MPS_CLS_DROP_DMAC10_L 0x120c0 +#define A_MPS_CLS_DROP_DMAC10_H 0x120c4 +#define A_MPS_CLS_DROP_DMAC11_L 0x120c8 +#define A_MPS_CLS_DROP_DMAC11_H 0x120cc +#define A_MPS_CLS_DROP_DMAC12_L 0x120d0 +#define A_MPS_CLS_DROP_DMAC12_H 0x120d4 +#define A_MPS_CLS_DROP_DMAC13_L 0x120d8 +#define A_MPS_CLS_DROP_DMAC13_H 0x120dc +#define A_MPS_CLS_DROP_DMAC14_L 0x120e0 +#define A_MPS_CLS_DROP_DMAC14_H 0x120e4 +#define A_MPS_CLS_DROP_DMAC15_L 0x120e8 +#define A_MPS_CLS_DROP_DMAC15_H 0x120ec +#define A_MPS_RX_ENCAP_VXLAN 0x120f0 +#define A_MPS_RX_INT_VXLAN 0x120f4 + +#define S_INT_TYPE_EN 16 +#define V_INT_TYPE_EN(x) ((x) << S_INT_TYPE_EN) +#define F_INT_TYPE_EN V_INT_TYPE_EN(1U) + +#define S_INT_TYPE 0 +#define M_INT_TYPE 0xffffU +#define V_INT_TYPE(x) ((x) << S_INT_TYPE) +#define G_INT_TYPE(x) (((x) >> S_INT_TYPE) & M_INT_TYPE) + +#define A_MPS_RX_INT_GENEVE 0x120f8 +#define A_MPS_PFVF_ATRB2 0x120fc + +#define S_EXTRACT_DEL_ENCAP 31 +#define V_EXTRACT_DEL_ENCAP(x) ((x) << S_EXTRACT_DEL_ENCAP) +#define F_EXTRACT_DEL_ENCAP V_EXTRACT_DEL_ENCAP(1U) + +#define A_MPS_RX_TRANS_ENCAP_FLTR_CTL 0x12100 + +#define S_TIMEOUT_FLT_CLR_EN 8 +#define V_TIMEOUT_FLT_CLR_EN(x) ((x) << S_TIMEOUT_FLT_CLR_EN) +#define F_TIMEOUT_FLT_CLR_EN V_TIMEOUT_FLT_CLR_EN(1U) + +#define S_FLTR_TIMOUT_VAL 0 +#define M_FLTR_TIMOUT_VAL 0xffU +#define V_FLTR_TIMOUT_VAL(x) ((x) << S_FLTR_TIMOUT_VAL) +#define G_FLTR_TIMOUT_VAL(x) (((x) >> S_FLTR_TIMOUT_VAL) & M_FLTR_TIMOUT_VAL) + +#define A_T7_MPS_RX_PAUSE_GEN_TH_0_0 0x12104 +#define A_T7_MPS_RX_PAUSE_GEN_TH_0_1 0x12108 +#define A_T7_MPS_RX_PAUSE_GEN_TH_0_2 0x1210c +#define A_T7_MPS_RX_PAUSE_GEN_TH_0_3 0x12110 +#define A_MPS_RX_PAUSE_GEN_TH_0_4 0x12114 +#define A_MPS_RX_PAUSE_GEN_TH_0_5 0x12118 +#define A_MPS_RX_PAUSE_GEN_TH_0_6 0x1211c +#define A_MPS_RX_PAUSE_GEN_TH_0_7 0x12120 +#define A_T7_MPS_RX_PAUSE_GEN_TH_1_0 0x12124 +#define A_T7_MPS_RX_PAUSE_GEN_TH_1_1 0x12128 +#define A_T7_MPS_RX_PAUSE_GEN_TH_1_2 0x1212c +#define A_T7_MPS_RX_PAUSE_GEN_TH_1_3 0x12130 +#define A_MPS_RX_PAUSE_GEN_TH_1_4 0x12134 +#define A_MPS_RX_PAUSE_GEN_TH_1_5 0x12138 +#define A_MPS_RX_PAUSE_GEN_TH_1_6 0x1213c +#define A_MPS_RX_PAUSE_GEN_TH_1_7 0x12140 +#define A_T7_MPS_RX_PAUSE_GEN_TH_2_0 0x12144 +#define A_T7_MPS_RX_PAUSE_GEN_TH_2_1 0x12148 +#define A_T7_MPS_RX_PAUSE_GEN_TH_2_2 0x1214c +#define A_T7_MPS_RX_PAUSE_GEN_TH_2_3 0x12150 +#define A_MPS_RX_PAUSE_GEN_TH_2_4 0x12154 +#define A_MPS_RX_PAUSE_GEN_TH_2_5 0x12158 +#define A_MPS_RX_PAUSE_GEN_TH_2_6 0x1215c +#define A_MPS_RX_PAUSE_GEN_TH_2_7 0x12160 +#define A_T7_MPS_RX_PAUSE_GEN_TH_3_0 0x12164 +#define A_T7_MPS_RX_PAUSE_GEN_TH_3_1 0x12168 +#define A_T7_MPS_RX_PAUSE_GEN_TH_3_2 0x1216c +#define A_T7_MPS_RX_PAUSE_GEN_TH_3_3 0x12170 +#define A_MPS_RX_PAUSE_GEN_TH_3_4 0x12174 +#define A_MPS_RX_PAUSE_GEN_TH_3_5 0x12178 +#define A_MPS_RX_PAUSE_GEN_TH_3_6 0x1217c +#define A_MPS_RX_PAUSE_GEN_TH_3_7 0x12180 +#define A_MPS_RX_DROP_0_0 0x12184 + +#define S_DROP_TH 0 +#define M_DROP_TH 0xffffU +#define V_DROP_TH(x) ((x) << S_DROP_TH) +#define G_DROP_TH(x) (((x) >> S_DROP_TH) & M_DROP_TH) + +#define A_MPS_RX_DROP_0_1 0x12188 +#define A_MPS_RX_DROP_0_2 0x1218c +#define A_MPS_RX_DROP_0_3 0x12190 +#define A_MPS_RX_DROP_0_4 0x12194 +#define A_MPS_RX_DROP_0_5 0x12198 +#define A_MPS_RX_DROP_0_6 0x1219c +#define A_MPS_RX_DROP_0_7 0x121a0 +#define A_MPS_RX_DROP_1_0 0x121a4 +#define A_MPS_RX_DROP_1_1 0x121a8 +#define A_MPS_RX_DROP_1_2 0x121ac +#define A_MPS_RX_DROP_1_3 0x121b0 +#define A_MPS_RX_DROP_1_4 0x121b4 +#define A_MPS_RX_DROP_1_5 0x121b8 +#define A_MPS_RX_DROP_1_6 0x121bc +#define A_MPS_RX_DROP_1_7 0x121c0 +#define A_MPS_RX_DROP_2_0 0x121c4 +#define A_MPS_RX_DROP_2_1 0x121c8 +#define A_MPS_RX_DROP_2_2 0x121cc +#define A_MPS_RX_DROP_2_3 0x121d0 +#define A_MPS_RX_DROP_2_4 0x121d4 +#define A_MPS_RX_DROP_2_5 0x121d8 +#define A_MPS_RX_DROP_2_6 0x121dc +#define A_MPS_RX_DROP_2_7 0x121e0 +#define A_MPS_RX_DROP_3_0 0x121e4 +#define A_MPS_RX_DROP_3_1 0x121e8 +#define A_MPS_RX_DROP_3_2 0x121ec +#define A_MPS_RX_DROP_3_3 0x121f0 +#define A_MPS_RX_DROP_3_4 0x121f4 +#define A_MPS_RX_DROP_3_5 0x121f8 +#define A_MPS_RX_DROP_3_6 0x121fc +#define A_MPS_RX_DROP_3_7 0x12200 +#define A_MPS_RX_MAC_BG_PG_CNT0_0 0x12204 +#define A_MPS_RX_MAC_BG_PG_CNT0_1 0x12208 +#define A_MPS_RX_MAC_BG_PG_CNT0_2 0x1220c +#define A_MPS_RX_MAC_BG_PG_CNT0_3 0x12210 +#define A_MPS_RX_MAC_BG_PG_CNT0_4 0x12214 +#define A_MPS_RX_MAC_BG_PG_CNT0_5 0x12218 +#define A_MPS_RX_MAC_BG_PG_CNT0_6 0x1221c +#define A_MPS_RX_MAC_BG_PG_CNT0_7 0x12220 +#define A_MPS_RX_MAC_BG_PG_CNT1_0 0x12224 +#define A_MPS_RX_MAC_BG_PG_CNT1_1 0x12228 +#define A_MPS_RX_MAC_BG_PG_CNT1_2 0x1222c +#define A_MPS_RX_MAC_BG_PG_CNT1_3 0x12230 +#define A_MPS_RX_MAC_BG_PG_CNT1_4 0x12234 +#define A_MPS_RX_MAC_BG_PG_CNT1_5 0x12238 +#define A_MPS_RX_MAC_BG_PG_CNT1_6 0x1223c +#define A_MPS_RX_MAC_BG_PG_CNT1_7 0x12240 +#define A_MPS_RX_MAC_BG_PG_CNT2_0 0x12244 +#define A_MPS_RX_MAC_BG_PG_CNT2_1 0x12248 +#define A_MPS_RX_MAC_BG_PG_CNT2_2 0x1224c +#define A_MPS_RX_MAC_BG_PG_CNT2_3 0x12250 +#define A_MPS_RX_MAC_BG_PG_CNT2_4 0x12254 +#define A_MPS_RX_MAC_BG_PG_CNT2_5 0x12258 +#define A_MPS_RX_MAC_BG_PG_CNT2_6 0x1225c +#define A_MPS_RX_MAC_BG_PG_CNT2_7 0x12260 +#define A_MPS_RX_MAC_BG_PG_CNT3_0 0x12264 +#define A_MPS_RX_MAC_BG_PG_CNT3_1 0x12268 +#define A_MPS_RX_MAC_BG_PG_CNT3_2 0x1226c +#define A_MPS_RX_MAC_BG_PG_CNT3_3 0x12270 +#define A_MPS_RX_MAC_BG_PG_CNT3_4 0x12274 +#define A_MPS_RX_MAC_BG_PG_CNT3_5 0x12278 +#define A_MPS_RX_MAC_BG_PG_CNT3_6 0x1227c +#define A_MPS_RX_MAC_BG_PG_CNT3_7 0x12280 +#define A_T7_MPS_RX_PAUSE_GEN_TH_0 0x12284 +#define A_T7_MPS_RX_PAUSE_GEN_TH_1 0x12288 +#define A_T7_MPS_RX_PAUSE_GEN_TH_2 0x1228c +#define A_T7_MPS_RX_PAUSE_GEN_TH_3 0x12290 +#define A_MPS_RX_BG0_IPSEC_CNT 0x12294 +#define A_MPS_RX_BG1_IPSEC_CNT 0x12298 +#define A_MPS_RX_BG2_IPSEC_CNT 0x1229c +#define A_MPS_RX_BG3_IPSEC_CNT 0x122a0 +#define A_MPS_RX_MEM_FIFO_CONFIG0 0x122a4 + +#define S_FIFO_CONFIG2 16 +#define M_FIFO_CONFIG2 0xffffU +#define V_FIFO_CONFIG2(x) ((x) << S_FIFO_CONFIG2) +#define G_FIFO_CONFIG2(x) (((x) >> S_FIFO_CONFIG2) & M_FIFO_CONFIG2) + +#define S_FIFO_CONFIG1 0 +#define M_FIFO_CONFIG1 0xffffU +#define V_FIFO_CONFIG1(x) ((x) << S_FIFO_CONFIG1) +#define G_FIFO_CONFIG1(x) (((x) >> S_FIFO_CONFIG1) & M_FIFO_CONFIG1) + +#define A_MPS_RX_MEM_FIFO_CONFIG1 0x122a8 + +#define S_FIFO_CONFIG3 0 +#define M_FIFO_CONFIG3 0xffffU +#define V_FIFO_CONFIG3(x) ((x) << S_FIFO_CONFIG3) +#define G_FIFO_CONFIG3(x) (((x) >> S_FIFO_CONFIG3) & M_FIFO_CONFIG3) + +#define A_MPS_LPBK_MEM_FIFO_CONFIG0 0x122ac +#define A_MPS_LPBK_MEM_FIFO_CONFIG1 0x122b0 +#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG0 0x122b4 +#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG1 0x122b8 +#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG2 0x122bc +#define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG3 0x122c0 +#define A_MPS_BG_PAUSE_CTL 0x122c4 + +#define S_BG0_PAUSE_EN 3 +#define V_BG0_PAUSE_EN(x) ((x) << S_BG0_PAUSE_EN) +#define F_BG0_PAUSE_EN V_BG0_PAUSE_EN(1U) + +#define S_BG1_PAUSE_EN 2 +#define V_BG1_PAUSE_EN(x) ((x) << S_BG1_PAUSE_EN) +#define F_BG1_PAUSE_EN V_BG1_PAUSE_EN(1U) + +#define S_BG2_PAUSE_EN 1 +#define V_BG2_PAUSE_EN(x) ((x) << S_BG2_PAUSE_EN) +#define F_BG2_PAUSE_EN V_BG2_PAUSE_EN(1U) + +#define S_BG3_PAUSE_EN 0 +#define V_BG3_PAUSE_EN(x) ((x) << S_BG3_PAUSE_EN) +#define F_BG3_PAUSE_EN V_BG3_PAUSE_EN(1U) /* registers for module CPL_SWITCH */ #define CPL_SWITCH_BASE_ADDR 0x19040 @@ -35931,6 +45321,7 @@ #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE) #define F_CIM_SPLIT_ENABLE V_CIM_SPLIT_ENABLE(1U) +#define A_CNTRL 0x19040 #define A_CPL_SWITCH_TBL_IDX 0x19044 #define S_SWITCH_TBL_IDX 0 @@ -35938,7 +45329,9 @@ #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX) #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX) +#define A_TBL_IDX 0x19044 #define A_CPL_SWITCH_TBL_DATA 0x19048 +#define A_TBL_DATA 0x19048 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c #define S_ZERO_CMD_CH1 8 @@ -35951,6 +45344,18 @@ #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0) #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0) +#define A_ZERO_ERROR 0x1904c + +#define S_ZERO_CMD_CH3 24 +#define M_ZERO_CMD_CH3 0xffU +#define V_ZERO_CMD_CH3(x) ((x) << S_ZERO_CMD_CH3) +#define G_ZERO_CMD_CH3(x) (((x) >> S_ZERO_CMD_CH3) & M_ZERO_CMD_CH3) + +#define S_ZERO_CMD_CH2 16 +#define M_ZERO_CMD_CH2 0xffU +#define V_ZERO_CMD_CH2(x) ((x) << S_ZERO_CMD_CH2) +#define G_ZERO_CMD_CH2(x) (((x) >> S_ZERO_CMD_CH2) & M_ZERO_CMD_CH2) + #define A_CPL_INTR_ENABLE 0x19050 #define S_CIM_OP_MAP_PERR 5 @@ -35985,7 +45390,18 @@ #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0) #define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U) +#define A_INTR_ENABLE 0x19050 + +#define S_PERR_CPL_128TO128_3 9 +#define V_PERR_CPL_128TO128_3(x) ((x) << S_PERR_CPL_128TO128_3) +#define F_PERR_CPL_128TO128_3 V_PERR_CPL_128TO128_3(1U) + +#define S_PERR_CPL_128TO128_2 8 +#define V_PERR_CPL_128TO128_2(x) ((x) << S_PERR_CPL_128TO128_2) +#define F_PERR_CPL_128TO128_2 V_PERR_CPL_128TO128_2(1U) + #define A_CPL_INTR_CAUSE 0x19054 +#define A_INTR_CAUSE 0x19054 #define A_CPL_MAP_TBL_IDX 0x19058 #define S_MAP_TBL_IDX 0 @@ -35997,6 +45413,13 @@ #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM) #define F_CIM_SPLIT_OPCODE_PROGRAM V_CIM_SPLIT_OPCODE_PROGRAM(1U) +#define A_MAP_TBL_IDX 0x19058 + +#define S_CPL_MAP_TBL_SEL 9 +#define M_CPL_MAP_TBL_SEL 0x3U +#define V_CPL_MAP_TBL_SEL(x) ((x) << S_CPL_MAP_TBL_SEL) +#define G_CPL_MAP_TBL_SEL(x) (((x) >> S_CPL_MAP_TBL_SEL) & M_CPL_MAP_TBL_SEL) + #define A_CPL_MAP_TBL_DATA 0x1905c #define S_MAP_TBL_DATA 0 @@ -36004,6 +45427,8 @@ #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA) #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA) +#define A_MAP_TBL_DATA 0x1905c + /* registers for module SMB */ #define SMB_BASE_ADDR 0x19060 @@ -36019,6 +45444,16 @@ #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG) #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG) +#define S_T7_MACROCNTCFG 12 +#define M_T7_MACROCNTCFG 0x1fU +#define V_T7_MACROCNTCFG(x) ((x) << S_T7_MACROCNTCFG) +#define G_T7_MACROCNTCFG(x) (((x) >> S_T7_MACROCNTCFG) & M_T7_MACROCNTCFG) + +#define S_T7_MICROCNTCFG 0 +#define M_T7_MICROCNTCFG 0xfffU +#define V_T7_MICROCNTCFG(x) ((x) << S_T7_MICROCNTCFG) +#define G_T7_MICROCNTCFG(x) (((x) >> S_T7_MICROCNTCFG) & M_T7_MICROCNTCFG) + #define A_SMB_MST_TIMEOUT_CFG 0x19064 #define S_MSTTIMEOUTCFG 0 @@ -36685,6 +46120,26 @@ #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV) #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV) +#define S_T7_STOPBITS 25 +#define M_T7_STOPBITS 0x3U +#define V_T7_STOPBITS(x) ((x) << S_T7_STOPBITS) +#define G_T7_STOPBITS(x) (((x) >> S_T7_STOPBITS) & M_T7_STOPBITS) + +#define S_T7_PARITY 23 +#define M_T7_PARITY 0x3U +#define V_T7_PARITY(x) ((x) << S_T7_PARITY) +#define G_T7_PARITY(x) (((x) >> S_T7_PARITY) & M_T7_PARITY) + +#define S_T7_DATABITS 19 +#define M_T7_DATABITS 0xfU +#define V_T7_DATABITS(x) ((x) << S_T7_DATABITS) +#define G_T7_DATABITS(x) (((x) >> S_T7_DATABITS) & M_T7_DATABITS) + +#define S_T7_UART_CLKDIV 0 +#define M_T7_UART_CLKDIV 0x3ffffU +#define V_T7_UART_CLKDIV(x) ((x) << S_T7_UART_CLKDIV) +#define G_T7_UART_CLKDIV(x) (((x) >> S_T7_UART_CLKDIV) & M_T7_UART_CLKDIV) + /* registers for module PMU */ #define PMU_BASE_ADDR 0x19120 @@ -36767,6 +46222,26 @@ #define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK) #define F_PL_DIS_PRTY_CHK V_PL_DIS_PRTY_CHK(1U) +#define S_ARM_PART_CGEN 19 +#define V_ARM_PART_CGEN(x) ((x) << S_ARM_PART_CGEN) +#define F_ARM_PART_CGEN V_ARM_PART_CGEN(1U) + +#define S_CRYPTO_PART_CGEN 14 +#define V_CRYPTO_PART_CGEN(x) ((x) << S_CRYPTO_PART_CGEN) +#define F_CRYPTO_PART_CGEN V_CRYPTO_PART_CGEN(1U) + +#define S_NVME_PART_CGEN 9 +#define V_NVME_PART_CGEN(x) ((x) << S_NVME_PART_CGEN) +#define F_NVME_PART_CGEN V_NVME_PART_CGEN(1U) + +#define S_XP10_PART_CGEN 8 +#define V_XP10_PART_CGEN(x) ((x) << S_XP10_PART_CGEN) +#define F_XP10_PART_CGEN V_XP10_PART_CGEN(1U) + +#define S_GPEX_PART_CGEN 7 +#define V_GPEX_PART_CGEN(x) ((x) << S_GPEX_PART_CGEN) +#define F_GPEX_PART_CGEN V_GPEX_PART_CGEN(1U) + #define A_PMU_SLEEPMODE_WAKEUP 0x19124 #define S_HWWAKEUPEN 5 @@ -36861,6 +46336,72 @@ #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) #define F_TDDPTAGTCB V_TDDPTAGTCB(1U) +#define S_ISCSI_PAGE_SIZE_CHK_ENB 31 +#define V_ISCSI_PAGE_SIZE_CHK_ENB(x) ((x) << S_ISCSI_PAGE_SIZE_CHK_ENB) +#define F_ISCSI_PAGE_SIZE_CHK_ENB V_ISCSI_PAGE_SIZE_CHK_ENB(1U) + +#define S_RDMA_0B_WR_OPCODE_HI 29 +#define V_RDMA_0B_WR_OPCODE_HI(x) ((x) << S_RDMA_0B_WR_OPCODE_HI) +#define F_RDMA_0B_WR_OPCODE_HI V_RDMA_0B_WR_OPCODE_HI(1U) + +#define S_RDMA_IMMEDIATE_CQE 28 +#define V_RDMA_IMMEDIATE_CQE(x) ((x) << S_RDMA_IMMEDIATE_CQE) +#define F_RDMA_IMMEDIATE_CQE V_RDMA_IMMEDIATE_CQE(1U) + +#define S_RDMA_ATOMIC_WR_RSP_CQE 27 +#define V_RDMA_ATOMIC_WR_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_WR_RSP_CQE) +#define F_RDMA_ATOMIC_WR_RSP_CQE V_RDMA_ATOMIC_WR_RSP_CQE(1U) + +#define S_RDMA_VERIFY_RSP_FLUSH 26 +#define V_RDMA_VERIFY_RSP_FLUSH(x) ((x) << S_RDMA_VERIFY_RSP_FLUSH) +#define F_RDMA_VERIFY_RSP_FLUSH V_RDMA_VERIFY_RSP_FLUSH(1U) + +#define S_RDMA_VERIFY_RSP_CQE 25 +#define V_RDMA_VERIFY_RSP_CQE(x) ((x) << S_RDMA_VERIFY_RSP_CQE) +#define F_RDMA_VERIFY_RSP_CQE V_RDMA_VERIFY_RSP_CQE(1U) + +#define S_RDMA_FLUSH_RSP_CQE 24 +#define V_RDMA_FLUSH_RSP_CQE(x) ((x) << S_RDMA_FLUSH_RSP_CQE) +#define F_RDMA_FLUSH_RSP_CQE V_RDMA_FLUSH_RSP_CQE(1U) + +#define S_RDMA_ATOMIC_RSP_CQE 23 +#define V_RDMA_ATOMIC_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_RSP_CQE) +#define F_RDMA_ATOMIC_RSP_CQE V_RDMA_ATOMIC_RSP_CQE(1U) + +#define S_T7_TPT_EXTENSION_MODE 22 +#define V_T7_TPT_EXTENSION_MODE(x) ((x) << S_T7_TPT_EXTENSION_MODE) +#define F_T7_TPT_EXTENSION_MODE V_T7_TPT_EXTENSION_MODE(1U) + +#define S_NVME_TCP_DDP_VAL_EN 21 +#define V_NVME_TCP_DDP_VAL_EN(x) ((x) << S_NVME_TCP_DDP_VAL_EN) +#define F_NVME_TCP_DDP_VAL_EN V_NVME_TCP_DDP_VAL_EN(1U) + +#define S_NVME_TCP_REMOVE_HDR_CRC 20 +#define V_NVME_TCP_REMOVE_HDR_CRC(x) ((x) << S_NVME_TCP_REMOVE_HDR_CRC) +#define F_NVME_TCP_REMOVE_HDR_CRC V_NVME_TCP_REMOVE_HDR_CRC(1U) + +#define S_NVME_TCP_LAST_PDU_CHECK_ENB 19 +#define V_NVME_TCP_LAST_PDU_CHECK_ENB(x) ((x) << S_NVME_TCP_LAST_PDU_CHECK_ENB) +#define F_NVME_TCP_LAST_PDU_CHECK_ENB V_NVME_TCP_LAST_PDU_CHECK_ENB(1U) + +#define S_NVME_TCP_OFFSET_SUBMODE 17 +#define M_NVME_TCP_OFFSET_SUBMODE 0x3U +#define V_NVME_TCP_OFFSET_SUBMODE(x) ((x) << S_NVME_TCP_OFFSET_SUBMODE) +#define G_NVME_TCP_OFFSET_SUBMODE(x) (((x) >> S_NVME_TCP_OFFSET_SUBMODE) & M_NVME_TCP_OFFSET_SUBMODE) + +#define S_NVME_TCP_OFFSET_MODE 16 +#define V_NVME_TCP_OFFSET_MODE(x) ((x) << S_NVME_TCP_OFFSET_MODE) +#define F_NVME_TCP_OFFSET_MODE V_NVME_TCP_OFFSET_MODE(1U) + +#define S_QPID_CHECK_DISABLE_FOR_SEND 15 +#define V_QPID_CHECK_DISABLE_FOR_SEND(x) ((x) << S_QPID_CHECK_DISABLE_FOR_SEND) +#define F_QPID_CHECK_DISABLE_FOR_SEND V_QPID_CHECK_DISABLE_FOR_SEND(1U) + +#define S_RDMA_0B_WR_OPCODE_LO 10 +#define M_RDMA_0B_WR_OPCODE_LO 0xfU +#define V_RDMA_0B_WR_OPCODE_LO(x) ((x) << S_RDMA_0B_WR_OPCODE_LO) +#define G_RDMA_0B_WR_OPCODE_LO(x) (((x) >> S_RDMA_0B_WR_OPCODE_LO) & M_RDMA_0B_WR_OPCODE_LO) + #define A_ULP_RX_INT_ENABLE 0x19154 #define S_ENABLE_CTX_1 24 @@ -36971,6 +46512,86 @@ #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0) #define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U) +#define S_CERR_PCMD_FIFO_3 19 +#define V_CERR_PCMD_FIFO_3(x) ((x) << S_CERR_PCMD_FIFO_3) +#define F_CERR_PCMD_FIFO_3 V_CERR_PCMD_FIFO_3(1U) + +#define S_CERR_PCMD_FIFO_2 18 +#define V_CERR_PCMD_FIFO_2(x) ((x) << S_CERR_PCMD_FIFO_2) +#define F_CERR_PCMD_FIFO_2 V_CERR_PCMD_FIFO_2(1U) + +#define S_CERR_PCMD_FIFO_1 17 +#define V_CERR_PCMD_FIFO_1(x) ((x) << S_CERR_PCMD_FIFO_1) +#define F_CERR_PCMD_FIFO_1 V_CERR_PCMD_FIFO_1(1U) + +#define S_CERR_PCMD_FIFO_0 16 +#define V_CERR_PCMD_FIFO_0(x) ((x) << S_CERR_PCMD_FIFO_0) +#define F_CERR_PCMD_FIFO_0 V_CERR_PCMD_FIFO_0(1U) + +#define S_CERR_DATA_FIFO_3 15 +#define V_CERR_DATA_FIFO_3(x) ((x) << S_CERR_DATA_FIFO_3) +#define F_CERR_DATA_FIFO_3 V_CERR_DATA_FIFO_3(1U) + +#define S_CERR_DATA_FIFO_2 14 +#define V_CERR_DATA_FIFO_2(x) ((x) << S_CERR_DATA_FIFO_2) +#define F_CERR_DATA_FIFO_2 V_CERR_DATA_FIFO_2(1U) + +#define S_CERR_DATA_FIFO_1 13 +#define V_CERR_DATA_FIFO_1(x) ((x) << S_CERR_DATA_FIFO_1) +#define F_CERR_DATA_FIFO_1 V_CERR_DATA_FIFO_1(1U) + +#define S_CERR_DATA_FIFO_0 12 +#define V_CERR_DATA_FIFO_0(x) ((x) << S_CERR_DATA_FIFO_0) +#define F_CERR_DATA_FIFO_0 V_CERR_DATA_FIFO_0(1U) + +#define S_SE_CNT_MISMATCH_3 11 +#define V_SE_CNT_MISMATCH_3(x) ((x) << S_SE_CNT_MISMATCH_3) +#define F_SE_CNT_MISMATCH_3 V_SE_CNT_MISMATCH_3(1U) + +#define S_SE_CNT_MISMATCH_2 10 +#define V_SE_CNT_MISMATCH_2(x) ((x) << S_SE_CNT_MISMATCH_2) +#define F_SE_CNT_MISMATCH_2 V_SE_CNT_MISMATCH_2(1U) + +#define S_T7_SE_CNT_MISMATCH_1 9 +#define V_T7_SE_CNT_MISMATCH_1(x) ((x) << S_T7_SE_CNT_MISMATCH_1) +#define F_T7_SE_CNT_MISMATCH_1 V_T7_SE_CNT_MISMATCH_1(1U) + +#define S_T7_SE_CNT_MISMATCH_0 8 +#define V_T7_SE_CNT_MISMATCH_0(x) ((x) << S_T7_SE_CNT_MISMATCH_0) +#define F_T7_SE_CNT_MISMATCH_0 V_T7_SE_CNT_MISMATCH_0(1U) + +#define S_ENABLE_CTX_3 7 +#define V_ENABLE_CTX_3(x) ((x) << S_ENABLE_CTX_3) +#define F_ENABLE_CTX_3 V_ENABLE_CTX_3(1U) + +#define S_ENABLE_CTX_2 6 +#define V_ENABLE_CTX_2(x) ((x) << S_ENABLE_CTX_2) +#define F_ENABLE_CTX_2 V_ENABLE_CTX_2(1U) + +#define S_T7_ENABLE_CTX_1 5 +#define V_T7_ENABLE_CTX_1(x) ((x) << S_T7_ENABLE_CTX_1) +#define F_T7_ENABLE_CTX_1 V_T7_ENABLE_CTX_1(1U) + +#define S_T7_ENABLE_CTX_0 4 +#define V_T7_ENABLE_CTX_0(x) ((x) << S_T7_ENABLE_CTX_0) +#define F_T7_ENABLE_CTX_0 V_T7_ENABLE_CTX_0(1U) + +#define S_ENABLE_ALN_SDC_ERR_3 3 +#define V_ENABLE_ALN_SDC_ERR_3(x) ((x) << S_ENABLE_ALN_SDC_ERR_3) +#define F_ENABLE_ALN_SDC_ERR_3 V_ENABLE_ALN_SDC_ERR_3(1U) + +#define S_ENABLE_ALN_SDC_ERR_2 2 +#define V_ENABLE_ALN_SDC_ERR_2(x) ((x) << S_ENABLE_ALN_SDC_ERR_2) +#define F_ENABLE_ALN_SDC_ERR_2 V_ENABLE_ALN_SDC_ERR_2(1U) + +#define S_T7_ENABLE_ALN_SDC_ERR_1 1 +#define V_T7_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_1) +#define F_T7_ENABLE_ALN_SDC_ERR_1 V_T7_ENABLE_ALN_SDC_ERR_1(1U) + +#define S_T7_ENABLE_ALN_SDC_ERR_0 0 +#define V_T7_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_0) +#define F_T7_ENABLE_ALN_SDC_ERR_0 V_T7_ENABLE_ALN_SDC_ERR_0(1U) + #define A_ULP_RX_INT_CAUSE 0x19158 #define S_CAUSE_CTX_1 24 @@ -37282,6 +46903,312 @@ #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID) #define A_ULP_RX_CTX_ACC_CH1 0x191b0 +#define A_ULP_RX_CTX_ACC_CH2 0x191b4 +#define A_ULP_RX_CTX_ACC_CH3 0x191b8 +#define A_ULP_RX_CTL2 0x191bc + +#define S_PCMD3THRESHOLD 24 +#define M_PCMD3THRESHOLD 0xffU +#define V_PCMD3THRESHOLD(x) ((x) << S_PCMD3THRESHOLD) +#define G_PCMD3THRESHOLD(x) (((x) >> S_PCMD3THRESHOLD) & M_PCMD3THRESHOLD) + +#define S_PCMD2THRESHOLD 16 +#define M_PCMD2THRESHOLD 0xffU +#define V_PCMD2THRESHOLD(x) ((x) << S_PCMD2THRESHOLD) +#define G_PCMD2THRESHOLD(x) (((x) >> S_PCMD2THRESHOLD) & M_PCMD2THRESHOLD) + +#define S_T7_PCMD1THRESHOLD 8 +#define M_T7_PCMD1THRESHOLD 0xffU +#define V_T7_PCMD1THRESHOLD(x) ((x) << S_T7_PCMD1THRESHOLD) +#define G_T7_PCMD1THRESHOLD(x) (((x) >> S_T7_PCMD1THRESHOLD) & M_T7_PCMD1THRESHOLD) + +#define S_T7_PCMD0THRESHOLD 0 +#define M_T7_PCMD0THRESHOLD 0xffU +#define V_T7_PCMD0THRESHOLD(x) ((x) << S_T7_PCMD0THRESHOLD) +#define G_T7_PCMD0THRESHOLD(x) (((x) >> S_T7_PCMD0THRESHOLD) & M_T7_PCMD0THRESHOLD) + +#define A_ULP_RX_INT_ENABLE_INTERFACE 0x191c0 + +#define S_ENABLE_ULPRX2SBT_RSPPERR 31 +#define V_ENABLE_ULPRX2SBT_RSPPERR(x) ((x) << S_ENABLE_ULPRX2SBT_RSPPERR) +#define F_ENABLE_ULPRX2SBT_RSPPERR V_ENABLE_ULPRX2SBT_RSPPERR(1U) + +#define S_ENABLE_ULPRX2MA_RSPPERR 30 +#define V_ENABLE_ULPRX2MA_RSPPERR(x) ((x) << S_ENABLE_ULPRX2MA_RSPPERR) +#define F_ENABLE_ULPRX2MA_RSPPERR V_ENABLE_ULPRX2MA_RSPPERR(1U) + +#define S_ENABME_PIO_BUS_PERR 29 +#define V_ENABME_PIO_BUS_PERR(x) ((x) << S_ENABME_PIO_BUS_PERR) +#define F_ENABME_PIO_BUS_PERR V_ENABME_PIO_BUS_PERR(1U) + +#define S_ENABLE_PM2ULP_SNOOPDATA_3 19 +#define V_ENABLE_PM2ULP_SNOOPDATA_3(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_3) +#define F_ENABLE_PM2ULP_SNOOPDATA_3 V_ENABLE_PM2ULP_SNOOPDATA_3(1U) + +#define S_ENABLE_PM2ULP_SNOOPDATA_2 18 +#define V_ENABLE_PM2ULP_SNOOPDATA_2(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_2) +#define F_ENABLE_PM2ULP_SNOOPDATA_2 V_ENABLE_PM2ULP_SNOOPDATA_2(1U) + +#define S_ENABLE_PM2ULP_SNOOPDATA_1 17 +#define V_ENABLE_PM2ULP_SNOOPDATA_1(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_1) +#define F_ENABLE_PM2ULP_SNOOPDATA_1 V_ENABLE_PM2ULP_SNOOPDATA_1(1U) + +#define S_ENABLE_PM2ULP_SNOOPDATA_0 16 +#define V_ENABLE_PM2ULP_SNOOPDATA_0(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_0) +#define F_ENABLE_PM2ULP_SNOOPDATA_0 V_ENABLE_PM2ULP_SNOOPDATA_0(1U) + +#define S_ENABLE_TLS2ULP_DATA_3 15 +#define V_ENABLE_TLS2ULP_DATA_3(x) ((x) << S_ENABLE_TLS2ULP_DATA_3) +#define F_ENABLE_TLS2ULP_DATA_3 V_ENABLE_TLS2ULP_DATA_3(1U) + +#define S_ENABLE_TLS2ULP_DATA_2 14 +#define V_ENABLE_TLS2ULP_DATA_2(x) ((x) << S_ENABLE_TLS2ULP_DATA_2) +#define F_ENABLE_TLS2ULP_DATA_2 V_ENABLE_TLS2ULP_DATA_2(1U) + +#define S_ENABLE_TLS2ULP_DATA_1 13 +#define V_ENABLE_TLS2ULP_DATA_1(x) ((x) << S_ENABLE_TLS2ULP_DATA_1) +#define F_ENABLE_TLS2ULP_DATA_1 V_ENABLE_TLS2ULP_DATA_1(1U) + +#define S_ENABLE_TLS2ULP_DATA_0 12 +#define V_ENABLE_TLS2ULP_DATA_0(x) ((x) << S_ENABLE_TLS2ULP_DATA_0) +#define F_ENABLE_TLS2ULP_DATA_0 V_ENABLE_TLS2ULP_DATA_0(1U) + +#define S_ENABLE_TLS2ULP_PLENDATA_3 11 +#define V_ENABLE_TLS2ULP_PLENDATA_3(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_3) +#define F_ENABLE_TLS2ULP_PLENDATA_3 V_ENABLE_TLS2ULP_PLENDATA_3(1U) + +#define S_ENABLE_TLS2ULP_PLENDATA_2 10 +#define V_ENABLE_TLS2ULP_PLENDATA_2(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_2) +#define F_ENABLE_TLS2ULP_PLENDATA_2 V_ENABLE_TLS2ULP_PLENDATA_2(1U) + +#define S_ENABLE_TLS2ULP_PLENDATA_1 9 +#define V_ENABLE_TLS2ULP_PLENDATA_1(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_1) +#define F_ENABLE_TLS2ULP_PLENDATA_1 V_ENABLE_TLS2ULP_PLENDATA_1(1U) + +#define S_ENABLE_TLS2ULP_PLENDATA_0 8 +#define V_ENABLE_TLS2ULP_PLENDATA_0(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_0) +#define F_ENABLE_TLS2ULP_PLENDATA_0 V_ENABLE_TLS2ULP_PLENDATA_0(1U) + +#define S_ENABLE_PM2ULP_DATA_3 7 +#define V_ENABLE_PM2ULP_DATA_3(x) ((x) << S_ENABLE_PM2ULP_DATA_3) +#define F_ENABLE_PM2ULP_DATA_3 V_ENABLE_PM2ULP_DATA_3(1U) + +#define S_ENABLE_PM2ULP_DATA_2 6 +#define V_ENABLE_PM2ULP_DATA_2(x) ((x) << S_ENABLE_PM2ULP_DATA_2) +#define F_ENABLE_PM2ULP_DATA_2 V_ENABLE_PM2ULP_DATA_2(1U) + +#define S_ENABLE_PM2ULP_DATA_1 5 +#define V_ENABLE_PM2ULP_DATA_1(x) ((x) << S_ENABLE_PM2ULP_DATA_1) +#define F_ENABLE_PM2ULP_DATA_1 V_ENABLE_PM2ULP_DATA_1(1U) + +#define S_ENABLE_PM2ULP_DATA_0 4 +#define V_ENABLE_PM2ULP_DATA_0(x) ((x) << S_ENABLE_PM2ULP_DATA_0) +#define F_ENABLE_PM2ULP_DATA_0 V_ENABLE_PM2ULP_DATA_0(1U) + +#define S_ENABLE_TP2ULP_PCMD_3 3 +#define V_ENABLE_TP2ULP_PCMD_3(x) ((x) << S_ENABLE_TP2ULP_PCMD_3) +#define F_ENABLE_TP2ULP_PCMD_3 V_ENABLE_TP2ULP_PCMD_3(1U) + +#define S_ENABLE_TP2ULP_PCMD_2 2 +#define V_ENABLE_TP2ULP_PCMD_2(x) ((x) << S_ENABLE_TP2ULP_PCMD_2) +#define F_ENABLE_TP2ULP_PCMD_2 V_ENABLE_TP2ULP_PCMD_2(1U) + +#define S_ENABLE_TP2ULP_PCMD_1 1 +#define V_ENABLE_TP2ULP_PCMD_1(x) ((x) << S_ENABLE_TP2ULP_PCMD_1) +#define F_ENABLE_TP2ULP_PCMD_1 V_ENABLE_TP2ULP_PCMD_1(1U) + +#define S_ENABLE_TP2ULP_PCMD_0 0 +#define V_ENABLE_TP2ULP_PCMD_0(x) ((x) << S_ENABLE_TP2ULP_PCMD_0) +#define F_ENABLE_TP2ULP_PCMD_0 V_ENABLE_TP2ULP_PCMD_0(1U) + +#define A_ULP_RX_INT_CAUSE_INTERFACE 0x191c4 + +#define S_CAUSE_ULPRX2SBT_RSPPERR 31 +#define V_CAUSE_ULPRX2SBT_RSPPERR(x) ((x) << S_CAUSE_ULPRX2SBT_RSPPERR) +#define F_CAUSE_ULPRX2SBT_RSPPERR V_CAUSE_ULPRX2SBT_RSPPERR(1U) + +#define S_CAUSE_ULPRX2MA_RSPPERR 30 +#define V_CAUSE_ULPRX2MA_RSPPERR(x) ((x) << S_CAUSE_ULPRX2MA_RSPPERR) +#define F_CAUSE_ULPRX2MA_RSPPERR V_CAUSE_ULPRX2MA_RSPPERR(1U) + +#define S_CAUSE_PIO_BUS_PERR 29 +#define V_CAUSE_PIO_BUS_PERR(x) ((x) << S_CAUSE_PIO_BUS_PERR) +#define F_CAUSE_PIO_BUS_PERR V_CAUSE_PIO_BUS_PERR(1U) + +#define S_CAUSE_PM2ULP_SNOOPDATA_3 19 +#define V_CAUSE_PM2ULP_SNOOPDATA_3(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_3) +#define F_CAUSE_PM2ULP_SNOOPDATA_3 V_CAUSE_PM2ULP_SNOOPDATA_3(1U) + +#define S_CAUSE_PM2ULP_SNOOPDATA_2 18 +#define V_CAUSE_PM2ULP_SNOOPDATA_2(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_2) +#define F_CAUSE_PM2ULP_SNOOPDATA_2 V_CAUSE_PM2ULP_SNOOPDATA_2(1U) + +#define S_CAUSE_PM2ULP_SNOOPDATA_1 17 +#define V_CAUSE_PM2ULP_SNOOPDATA_1(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_1) +#define F_CAUSE_PM2ULP_SNOOPDATA_1 V_CAUSE_PM2ULP_SNOOPDATA_1(1U) + +#define S_CAUSE_PM2ULP_SNOOPDATA_0 16 +#define V_CAUSE_PM2ULP_SNOOPDATA_0(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_0) +#define F_CAUSE_PM2ULP_SNOOPDATA_0 V_CAUSE_PM2ULP_SNOOPDATA_0(1U) + +#define S_CAUSE_TLS2ULP_DATA_3 15 +#define V_CAUSE_TLS2ULP_DATA_3(x) ((x) << S_CAUSE_TLS2ULP_DATA_3) +#define F_CAUSE_TLS2ULP_DATA_3 V_CAUSE_TLS2ULP_DATA_3(1U) + +#define S_CAUSE_TLS2ULP_DATA_2 14 +#define V_CAUSE_TLS2ULP_DATA_2(x) ((x) << S_CAUSE_TLS2ULP_DATA_2) +#define F_CAUSE_TLS2ULP_DATA_2 V_CAUSE_TLS2ULP_DATA_2(1U) + +#define S_CAUSE_TLS2ULP_DATA_1 13 +#define V_CAUSE_TLS2ULP_DATA_1(x) ((x) << S_CAUSE_TLS2ULP_DATA_1) +#define F_CAUSE_TLS2ULP_DATA_1 V_CAUSE_TLS2ULP_DATA_1(1U) + +#define S_CAUSE_TLS2ULP_DATA_0 12 +#define V_CAUSE_TLS2ULP_DATA_0(x) ((x) << S_CAUSE_TLS2ULP_DATA_0) +#define F_CAUSE_TLS2ULP_DATA_0 V_CAUSE_TLS2ULP_DATA_0(1U) + +#define S_CAUSE_TLS2ULP_PLENDATA_3 11 +#define V_CAUSE_TLS2ULP_PLENDATA_3(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_3) +#define F_CAUSE_TLS2ULP_PLENDATA_3 V_CAUSE_TLS2ULP_PLENDATA_3(1U) + +#define S_CAUSE_TLS2ULP_PLENDATA_2 10 +#define V_CAUSE_TLS2ULP_PLENDATA_2(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_2) +#define F_CAUSE_TLS2ULP_PLENDATA_2 V_CAUSE_TLS2ULP_PLENDATA_2(1U) + +#define S_CAUSE_TLS2ULP_PLENDATA_1 9 +#define V_CAUSE_TLS2ULP_PLENDATA_1(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_1) +#define F_CAUSE_TLS2ULP_PLENDATA_1 V_CAUSE_TLS2ULP_PLENDATA_1(1U) + +#define S_CAUSE_TLS2ULP_PLENDATA_0 8 +#define V_CAUSE_TLS2ULP_PLENDATA_0(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_0) +#define F_CAUSE_TLS2ULP_PLENDATA_0 V_CAUSE_TLS2ULP_PLENDATA_0(1U) + +#define S_CAUSE_PM2ULP_DATA_3 7 +#define V_CAUSE_PM2ULP_DATA_3(x) ((x) << S_CAUSE_PM2ULP_DATA_3) +#define F_CAUSE_PM2ULP_DATA_3 V_CAUSE_PM2ULP_DATA_3(1U) + +#define S_CAUSE_PM2ULP_DATA_2 6 +#define V_CAUSE_PM2ULP_DATA_2(x) ((x) << S_CAUSE_PM2ULP_DATA_2) +#define F_CAUSE_PM2ULP_DATA_2 V_CAUSE_PM2ULP_DATA_2(1U) + +#define S_CAUSE_PM2ULP_DATA_1 5 +#define V_CAUSE_PM2ULP_DATA_1(x) ((x) << S_CAUSE_PM2ULP_DATA_1) +#define F_CAUSE_PM2ULP_DATA_1 V_CAUSE_PM2ULP_DATA_1(1U) + +#define S_CAUSE_PM2ULP_DATA_0 4 +#define V_CAUSE_PM2ULP_DATA_0(x) ((x) << S_CAUSE_PM2ULP_DATA_0) +#define F_CAUSE_PM2ULP_DATA_0 V_CAUSE_PM2ULP_DATA_0(1U) + +#define S_CAUSE_TP2ULP_PCMD_3 3 +#define V_CAUSE_TP2ULP_PCMD_3(x) ((x) << S_CAUSE_TP2ULP_PCMD_3) +#define F_CAUSE_TP2ULP_PCMD_3 V_CAUSE_TP2ULP_PCMD_3(1U) + +#define S_CAUSE_TP2ULP_PCMD_2 2 +#define V_CAUSE_TP2ULP_PCMD_2(x) ((x) << S_CAUSE_TP2ULP_PCMD_2) +#define F_CAUSE_TP2ULP_PCMD_2 V_CAUSE_TP2ULP_PCMD_2(1U) + +#define S_CAUSE_TP2ULP_PCMD_1 1 +#define V_CAUSE_TP2ULP_PCMD_1(x) ((x) << S_CAUSE_TP2ULP_PCMD_1) +#define F_CAUSE_TP2ULP_PCMD_1 V_CAUSE_TP2ULP_PCMD_1(1U) + +#define S_CAUSE_TP2ULP_PCMD_0 0 +#define V_CAUSE_TP2ULP_PCMD_0(x) ((x) << S_CAUSE_TP2ULP_PCMD_0) +#define F_CAUSE_TP2ULP_PCMD_0 V_CAUSE_TP2ULP_PCMD_0(1U) + +#define A_ULP_RX_PERR_ENABLE_INTERFACE 0x191c8 + +#define S_PERR_ULPRX2SBT_RSPPERR 31 +#define V_PERR_ULPRX2SBT_RSPPERR(x) ((x) << S_PERR_ULPRX2SBT_RSPPERR) +#define F_PERR_ULPRX2SBT_RSPPERR V_PERR_ULPRX2SBT_RSPPERR(1U) + +#define S_PERR_ULPRX2MA_RSPPERR 30 +#define V_PERR_ULPRX2MA_RSPPERR(x) ((x) << S_PERR_ULPRX2MA_RSPPERR) +#define F_PERR_ULPRX2MA_RSPPERR V_PERR_ULPRX2MA_RSPPERR(1U) + +#define S_PERR_PIO_BUS_PERR 29 +#define V_PERR_PIO_BUS_PERR(x) ((x) << S_PERR_PIO_BUS_PERR) +#define F_PERR_PIO_BUS_PERR V_PERR_PIO_BUS_PERR(1U) + +#define S_PERR_PM2ULP_SNOOPDATA_3 19 +#define V_PERR_PM2ULP_SNOOPDATA_3(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_3) +#define F_PERR_PM2ULP_SNOOPDATA_3 V_PERR_PM2ULP_SNOOPDATA_3(1U) + +#define S_PERR_PM2ULP_SNOOPDATA_2 18 +#define V_PERR_PM2ULP_SNOOPDATA_2(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_2) +#define F_PERR_PM2ULP_SNOOPDATA_2 V_PERR_PM2ULP_SNOOPDATA_2(1U) + +#define S_PERR_PM2ULP_SNOOPDATA_1 17 +#define V_PERR_PM2ULP_SNOOPDATA_1(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_1) +#define F_PERR_PM2ULP_SNOOPDATA_1 V_PERR_PM2ULP_SNOOPDATA_1(1U) + +#define S_PERR_PM2ULP_SNOOPDATA_0 16 +#define V_PERR_PM2ULP_SNOOPDATA_0(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_0) +#define F_PERR_PM2ULP_SNOOPDATA_0 V_PERR_PM2ULP_SNOOPDATA_0(1U) + +#define S_PERR_TLS2ULP_DATA_3 15 +#define V_PERR_TLS2ULP_DATA_3(x) ((x) << S_PERR_TLS2ULP_DATA_3) +#define F_PERR_TLS2ULP_DATA_3 V_PERR_TLS2ULP_DATA_3(1U) + +#define S_PERR_TLS2ULP_DATA_2 14 +#define V_PERR_TLS2ULP_DATA_2(x) ((x) << S_PERR_TLS2ULP_DATA_2) +#define F_PERR_TLS2ULP_DATA_2 V_PERR_TLS2ULP_DATA_2(1U) + +#define S_PERR_TLS2ULP_DATA_1 13 +#define V_PERR_TLS2ULP_DATA_1(x) ((x) << S_PERR_TLS2ULP_DATA_1) +#define F_PERR_TLS2ULP_DATA_1 V_PERR_TLS2ULP_DATA_1(1U) + +#define S_PERR_TLS2ULP_DATA_0 12 +#define V_PERR_TLS2ULP_DATA_0(x) ((x) << S_PERR_TLS2ULP_DATA_0) +#define F_PERR_TLS2ULP_DATA_0 V_PERR_TLS2ULP_DATA_0(1U) + +#define S_PERR_TLS2ULP_PLENDATA_3 11 +#define V_PERR_TLS2ULP_PLENDATA_3(x) ((x) << S_PERR_TLS2ULP_PLENDATA_3) +#define F_PERR_TLS2ULP_PLENDATA_3 V_PERR_TLS2ULP_PLENDATA_3(1U) + +#define S_PERR_TLS2ULP_PLENDATA_2 10 +#define V_PERR_TLS2ULP_PLENDATA_2(x) ((x) << S_PERR_TLS2ULP_PLENDATA_2) +#define F_PERR_TLS2ULP_PLENDATA_2 V_PERR_TLS2ULP_PLENDATA_2(1U) + +#define S_PERR_TLS2ULP_PLENDATA_1 9 +#define V_PERR_TLS2ULP_PLENDATA_1(x) ((x) << S_PERR_TLS2ULP_PLENDATA_1) +#define F_PERR_TLS2ULP_PLENDATA_1 V_PERR_TLS2ULP_PLENDATA_1(1U) + +#define S_PERR_TLS2ULP_PLENDATA_0 8 +#define V_PERR_TLS2ULP_PLENDATA_0(x) ((x) << S_PERR_TLS2ULP_PLENDATA_0) +#define F_PERR_TLS2ULP_PLENDATA_0 V_PERR_TLS2ULP_PLENDATA_0(1U) + +#define S_PERR_PM2ULP_DATA_3 7 +#define V_PERR_PM2ULP_DATA_3(x) ((x) << S_PERR_PM2ULP_DATA_3) +#define F_PERR_PM2ULP_DATA_3 V_PERR_PM2ULP_DATA_3(1U) + +#define S_PERR_PM2ULP_DATA_2 6 +#define V_PERR_PM2ULP_DATA_2(x) ((x) << S_PERR_PM2ULP_DATA_2) +#define F_PERR_PM2ULP_DATA_2 V_PERR_PM2ULP_DATA_2(1U) + +#define S_PERR_PM2ULP_DATA_1 5 +#define V_PERR_PM2ULP_DATA_1(x) ((x) << S_PERR_PM2ULP_DATA_1) +#define F_PERR_PM2ULP_DATA_1 V_PERR_PM2ULP_DATA_1(1U) + +#define S_PERR_PM2ULP_DATA_0 4 +#define V_PERR_PM2ULP_DATA_0(x) ((x) << S_PERR_PM2ULP_DATA_0) +#define F_PERR_PM2ULP_DATA_0 V_PERR_PM2ULP_DATA_0(1U) + +#define S_PERR_TP2ULP_PCMD_3 3 +#define V_PERR_TP2ULP_PCMD_3(x) ((x) << S_PERR_TP2ULP_PCMD_3) +#define F_PERR_TP2ULP_PCMD_3 V_PERR_TP2ULP_PCMD_3(1U) + +#define S_PERR_TP2ULP_PCMD_2 2 +#define V_PERR_TP2ULP_PCMD_2(x) ((x) << S_PERR_TP2ULP_PCMD_2) +#define F_PERR_TP2ULP_PCMD_2 V_PERR_TP2ULP_PCMD_2(1U) + +#define S_PERR_TP2ULP_PCMD_1 1 +#define V_PERR_TP2ULP_PCMD_1(x) ((x) << S_PERR_TP2ULP_PCMD_1) +#define F_PERR_TP2ULP_PCMD_1 V_PERR_TP2ULP_PCMD_1(1U) + +#define S_PERR_TP2ULP_PCMD_0 0 +#define V_PERR_TP2ULP_PCMD_0(x) ((x) << S_PERR_TP2ULP_PCMD_0) +#define F_PERR_TP2ULP_PCMD_0 V_PERR_TP2ULP_PCMD_0(1U) + #define A_ULP_RX_SE_CNT_ERR 0x191d0 #define A_ULP_RX_SE_CNT_CLR 0x191d4 @@ -37295,6 +47222,26 @@ #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1) #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1) +#define S_CLRCHAN3 12 +#define M_CLRCHAN3 0xfU +#define V_CLRCHAN3(x) ((x) << S_CLRCHAN3) +#define G_CLRCHAN3(x) (((x) >> S_CLRCHAN3) & M_CLRCHAN3) + +#define S_CLRCHAN2 8 +#define M_CLRCHAN2 0xfU +#define V_CLRCHAN2(x) ((x) << S_CLRCHAN2) +#define G_CLRCHAN2(x) (((x) >> S_CLRCHAN2) & M_CLRCHAN2) + +#define S_T7_CLRCHAN1 4 +#define M_T7_CLRCHAN1 0xfU +#define V_T7_CLRCHAN1(x) ((x) << S_T7_CLRCHAN1) +#define G_T7_CLRCHAN1(x) (((x) >> S_T7_CLRCHAN1) & M_T7_CLRCHAN1) + +#define S_T7_CLRCHAN0 0 +#define M_T7_CLRCHAN0 0xfU +#define V_T7_CLRCHAN0(x) ((x) << S_T7_CLRCHAN0) +#define G_T7_CLRCHAN0(x) (((x) >> S_T7_CLRCHAN0) & M_T7_CLRCHAN0) + #define A_ULP_RX_SE_CNT_CH0 0x191d8 #define S_SOP_CNT_OUT0 28 @@ -37400,6 +47347,7 @@ #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L) #define A_ULP_RX_DBG_DATAH 0x191e4 +#define A_ULP_RX_DBG_DATA 0x191e4 #define A_ULP_RX_DBG_DATAL 0x191e8 #define A_ULP_RX_LA_CHNL 0x19238 @@ -37581,6 +47529,11 @@ #define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE) #define F_PIO_RDMA_SEND_RQE V_PIO_RDMA_SEND_RQE(1U) +#define S_TLS_KEYSIZECONF 26 +#define M_TLS_KEYSIZECONF 0x3U +#define V_TLS_KEYSIZECONF(x) ((x) << S_TLS_KEYSIZECONF) +#define G_TLS_KEYSIZECONF(x) (((x) >> S_TLS_KEYSIZECONF) & M_TLS_KEYSIZECONF) + #define A_ULP_RX_CH0_CGEN 0x19260 #define S_BYPASS_CGEN 7 @@ -37615,7 +47568,61 @@ #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN) #define F_RDMA_DATAPATH_CGEN V_RDMA_DATAPATH_CGEN(1U) +#define A_ULP_RX_CH_CGEN 0x19260 + +#define S_T7_BYPASS_CGEN 28 +#define M_T7_BYPASS_CGEN 0xfU +#define V_T7_BYPASS_CGEN(x) ((x) << S_T7_BYPASS_CGEN) +#define G_T7_BYPASS_CGEN(x) (((x) >> S_T7_BYPASS_CGEN) & M_T7_BYPASS_CGEN) + +#define S_T7_TDDP_CGEN 24 +#define M_T7_TDDP_CGEN 0xfU +#define V_T7_TDDP_CGEN(x) ((x) << S_T7_TDDP_CGEN) +#define G_T7_TDDP_CGEN(x) (((x) >> S_T7_TDDP_CGEN) & M_T7_TDDP_CGEN) + +#define S_T7_ISCSI_CGEN 20 +#define M_T7_ISCSI_CGEN 0xfU +#define V_T7_ISCSI_CGEN(x) ((x) << S_T7_ISCSI_CGEN) +#define G_T7_ISCSI_CGEN(x) (((x) >> S_T7_ISCSI_CGEN) & M_T7_ISCSI_CGEN) + +#define S_T7_RDMA_CGEN 16 +#define M_T7_RDMA_CGEN 0xfU +#define V_T7_RDMA_CGEN(x) ((x) << S_T7_RDMA_CGEN) +#define G_T7_RDMA_CGEN(x) (((x) >> S_T7_RDMA_CGEN) & M_T7_RDMA_CGEN) + +#define S_T7_CHANNEL_CGEN 12 +#define M_T7_CHANNEL_CGEN 0xfU +#define V_T7_CHANNEL_CGEN(x) ((x) << S_T7_CHANNEL_CGEN) +#define G_T7_CHANNEL_CGEN(x) (((x) >> S_T7_CHANNEL_CGEN) & M_T7_CHANNEL_CGEN) + +#define S_T7_ALL_DATAPATH_CGEN 8 +#define M_T7_ALL_DATAPATH_CGEN 0xfU +#define V_T7_ALL_DATAPATH_CGEN(x) ((x) << S_T7_ALL_DATAPATH_CGEN) +#define G_T7_ALL_DATAPATH_CGEN(x) (((x) >> S_T7_ALL_DATAPATH_CGEN) & M_T7_ALL_DATAPATH_CGEN) + +#define S_T7_T10DIFF_DATAPATH_CGEN 4 +#define M_T7_T10DIFF_DATAPATH_CGEN 0xfU +#define V_T7_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T7_T10DIFF_DATAPATH_CGEN) +#define G_T7_T10DIFF_DATAPATH_CGEN(x) (((x) >> S_T7_T10DIFF_DATAPATH_CGEN) & M_T7_T10DIFF_DATAPATH_CGEN) + +#define S_T7_RDMA_DATAPATH_CGEN 0 +#define M_T7_RDMA_DATAPATH_CGEN 0xfU +#define V_T7_RDMA_DATAPATH_CGEN(x) ((x) << S_T7_RDMA_DATAPATH_CGEN) +#define G_T7_RDMA_DATAPATH_CGEN(x) (((x) >> S_T7_RDMA_DATAPATH_CGEN) & M_T7_RDMA_DATAPATH_CGEN) + #define A_ULP_RX_CH1_CGEN 0x19264 +#define A_ULP_RX_CH_CGEN_1 0x19264 + +#define S_NVME_TCP_CGEN 4 +#define M_NVME_TCP_CGEN 0xfU +#define V_NVME_TCP_CGEN(x) ((x) << S_NVME_TCP_CGEN) +#define G_NVME_TCP_CGEN(x) (((x) >> S_NVME_TCP_CGEN) & M_NVME_TCP_CGEN) + +#define S_ROCE_CGEN 0 +#define M_ROCE_CGEN 0xfU +#define V_ROCE_CGEN(x) ((x) << S_ROCE_CGEN) +#define G_ROCE_CGEN(x) (((x) >> S_ROCE_CGEN) & M_ROCE_CGEN) + #define A_ULP_RX_RFE_DISABLE 0x19268 #define S_RQE_LIM_CHECK_RFE_DISABLE 0 @@ -37742,6 +47749,30 @@ #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0) #define F_SKIP_MA_REQ_EN0 V_SKIP_MA_REQ_EN0(1U) +#define S_CLEAR_CTX_ERR_CNT3 7 +#define V_CLEAR_CTX_ERR_CNT3(x) ((x) << S_CLEAR_CTX_ERR_CNT3) +#define F_CLEAR_CTX_ERR_CNT3 V_CLEAR_CTX_ERR_CNT3(1U) + +#define S_CLEAR_CTX_ERR_CNT2 6 +#define V_CLEAR_CTX_ERR_CNT2(x) ((x) << S_CLEAR_CTX_ERR_CNT2) +#define F_CLEAR_CTX_ERR_CNT2 V_CLEAR_CTX_ERR_CNT2(1U) + +#define S_T7_CLEAR_CTX_ERR_CNT1 5 +#define V_T7_CLEAR_CTX_ERR_CNT1(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT1) +#define F_T7_CLEAR_CTX_ERR_CNT1 V_T7_CLEAR_CTX_ERR_CNT1(1U) + +#define S_T7_CLEAR_CTX_ERR_CNT0 4 +#define V_T7_CLEAR_CTX_ERR_CNT0(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT0) +#define F_T7_CLEAR_CTX_ERR_CNT0 V_T7_CLEAR_CTX_ERR_CNT0(1U) + +#define S_SKIP_MA_REQ_EN3 3 +#define V_SKIP_MA_REQ_EN3(x) ((x) << S_SKIP_MA_REQ_EN3) +#define F_SKIP_MA_REQ_EN3 V_SKIP_MA_REQ_EN3(1U) + +#define S_SKIP_MA_REQ_EN2 2 +#define V_SKIP_MA_REQ_EN2(x) ((x) << S_SKIP_MA_REQ_EN2) +#define F_SKIP_MA_REQ_EN2 V_SKIP_MA_REQ_EN2(1U) + #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290 @@ -37758,6 +47789,92 @@ #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE) #define F_SEND_MSN_CHECK_ENABLE V_SEND_MSN_CHECK_ENABLE(1U) +#define A_ULP_RX_SE_CNT_CH2 0x19294 + +#define S_SOP_CNT_OUT2 28 +#define M_SOP_CNT_OUT2 0xfU +#define V_SOP_CNT_OUT2(x) ((x) << S_SOP_CNT_OUT2) +#define G_SOP_CNT_OUT2(x) (((x) >> S_SOP_CNT_OUT2) & M_SOP_CNT_OUT2) + +#define S_EOP_CNT_OUT2 24 +#define M_EOP_CNT_OUT2 0xfU +#define V_EOP_CNT_OUT2(x) ((x) << S_EOP_CNT_OUT2) +#define G_EOP_CNT_OUT2(x) (((x) >> S_EOP_CNT_OUT2) & M_EOP_CNT_OUT2) + +#define S_SOP_CNT_AL2 20 +#define M_SOP_CNT_AL2 0xfU +#define V_SOP_CNT_AL2(x) ((x) << S_SOP_CNT_AL2) +#define G_SOP_CNT_AL2(x) (((x) >> S_SOP_CNT_AL2) & M_SOP_CNT_AL2) + +#define S_EOP_CNT_AL2 16 +#define M_EOP_CNT_AL2 0xfU +#define V_EOP_CNT_AL2(x) ((x) << S_EOP_CNT_AL2) +#define G_EOP_CNT_AL2(x) (((x) >> S_EOP_CNT_AL2) & M_EOP_CNT_AL2) + +#define S_SOP_CNT_MR2 12 +#define M_SOP_CNT_MR2 0xfU +#define V_SOP_CNT_MR2(x) ((x) << S_SOP_CNT_MR2) +#define G_SOP_CNT_MR2(x) (((x) >> S_SOP_CNT_MR2) & M_SOP_CNT_MR2) + +#define S_EOP_CNT_MR2 8 +#define M_EOP_CNT_MR2 0xfU +#define V_EOP_CNT_MR2(x) ((x) << S_EOP_CNT_MR2) +#define G_EOP_CNT_MR2(x) (((x) >> S_EOP_CNT_MR2) & M_EOP_CNT_MR2) + +#define S_SOP_CNT_IN2 4 +#define M_SOP_CNT_IN2 0xfU +#define V_SOP_CNT_IN2(x) ((x) << S_SOP_CNT_IN2) +#define G_SOP_CNT_IN2(x) (((x) >> S_SOP_CNT_IN2) & M_SOP_CNT_IN2) + +#define S_EOP_CNT_IN2 0 +#define M_EOP_CNT_IN2 0xfU +#define V_EOP_CNT_IN2(x) ((x) << S_EOP_CNT_IN2) +#define G_EOP_CNT_IN2(x) (((x) >> S_EOP_CNT_IN2) & M_EOP_CNT_IN2) + +#define A_ULP_RX_SE_CNT_CH3 0x19298 + +#define S_SOP_CNT_OUT3 28 +#define M_SOP_CNT_OUT3 0xfU +#define V_SOP_CNT_OUT3(x) ((x) << S_SOP_CNT_OUT3) +#define G_SOP_CNT_OUT3(x) (((x) >> S_SOP_CNT_OUT3) & M_SOP_CNT_OUT3) + +#define S_EOP_CNT_OUT3 24 +#define M_EOP_CNT_OUT3 0xfU +#define V_EOP_CNT_OUT3(x) ((x) << S_EOP_CNT_OUT3) +#define G_EOP_CNT_OUT3(x) (((x) >> S_EOP_CNT_OUT3) & M_EOP_CNT_OUT3) + +#define S_SOP_CNT_AL3 20 +#define M_SOP_CNT_AL3 0xfU +#define V_SOP_CNT_AL3(x) ((x) << S_SOP_CNT_AL3) +#define G_SOP_CNT_AL3(x) (((x) >> S_SOP_CNT_AL3) & M_SOP_CNT_AL3) + +#define S_EOP_CNT_AL3 16 +#define M_EOP_CNT_AL3 0xfU +#define V_EOP_CNT_AL3(x) ((x) << S_EOP_CNT_AL3) +#define G_EOP_CNT_AL3(x) (((x) >> S_EOP_CNT_AL3) & M_EOP_CNT_AL3) + +#define S_SOP_CNT_MR3 12 +#define M_SOP_CNT_MR3 0xfU +#define V_SOP_CNT_MR3(x) ((x) << S_SOP_CNT_MR3) +#define G_SOP_CNT_MR3(x) (((x) >> S_SOP_CNT_MR3) & M_SOP_CNT_MR3) + +#define S_EOP_CNT_MR3 8 +#define M_EOP_CNT_MR3 0xfU +#define V_EOP_CNT_MR3(x) ((x) << S_EOP_CNT_MR3) +#define G_EOP_CNT_MR3(x) (((x) >> S_EOP_CNT_MR3) & M_EOP_CNT_MR3) + +#define S_SOP_CNT_IN3 4 +#define M_SOP_CNT_IN3 0xfU +#define V_SOP_CNT_IN3(x) ((x) << S_SOP_CNT_IN3) +#define G_SOP_CNT_IN3(x) (((x) >> S_SOP_CNT_IN3) & M_SOP_CNT_IN3) + +#define S_EOP_CNT_IN3 0 +#define M_EOP_CNT_IN3 0xfU +#define V_EOP_CNT_IN3(x) ((x) << S_EOP_CNT_IN3) +#define G_EOP_CNT_IN3(x) (((x) >> S_EOP_CNT_IN3) & M_EOP_CNT_IN3) + +#define A_ULP_RX_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1929c +#define A_ULP_RX_CHNL3_CTX_ERROR_COUNT_PER_TID 0x192a0 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4 #define S_TLSPPLLIMIT 6 @@ -37787,6 +47904,933 @@ #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT) #define A_ULP_RX_TLS_CTL 0x192bc +#define A_ULP_RX_RRQ_LLIMIT 0x192c0 +#define A_ULP_RX_RRQ_ULIMIT 0x192c4 +#define A_ULP_RX_NVME_TCP_STAG_LLIMIT 0x192c8 +#define A_ULP_RX_NVME_TCP_STAG_ULIMIT 0x192cc +#define A_ULP_RX_NVME_TCP_RQ_LLIMIT 0x192d0 +#define A_ULP_RX_NVME_TCP_RQ_ULIMIT 0x192d4 +#define A_ULP_RX_NVME_TCP_PBL_LLIMIT 0x192d8 +#define A_ULP_RX_NVME_TCP_PBL_ULIMIT 0x192dc +#define A_ULP_RX_NVME_TCP_MAX_LENGTH 0x192e0 + +#define S_NVME_TCP_MAX_PLEN01 24 +#define M_NVME_TCP_MAX_PLEN01 0xffU +#define V_NVME_TCP_MAX_PLEN01(x) ((x) << S_NVME_TCP_MAX_PLEN01) +#define G_NVME_TCP_MAX_PLEN01(x) (((x) >> S_NVME_TCP_MAX_PLEN01) & M_NVME_TCP_MAX_PLEN01) + +#define S_NVME_TCP_MAX_PLEN23 16 +#define M_NVME_TCP_MAX_PLEN23 0xffU +#define V_NVME_TCP_MAX_PLEN23(x) ((x) << S_NVME_TCP_MAX_PLEN23) +#define G_NVME_TCP_MAX_PLEN23(x) (((x) >> S_NVME_TCP_MAX_PLEN23) & M_NVME_TCP_MAX_PLEN23) + +#define S_NVME_TCP_MAX_CMD_PDU_LENGTH 0 +#define M_NVME_TCP_MAX_CMD_PDU_LENGTH 0xffffU +#define V_NVME_TCP_MAX_CMD_PDU_LENGTH(x) ((x) << S_NVME_TCP_MAX_CMD_PDU_LENGTH) +#define G_NVME_TCP_MAX_CMD_PDU_LENGTH(x) (((x) >> S_NVME_TCP_MAX_CMD_PDU_LENGTH) & M_NVME_TCP_MAX_CMD_PDU_LENGTH) + +#define A_ULP_RX_NVME_TCP_IQE_SIZE 0x192e4 +#define A_ULP_RX_NVME_TCP_NEW_PDU_TYPES 0x192e8 +#define A_ULP_RX_IWARP_PMOF_OPCODES_1 0x192ec +#define A_ULP_RX_IWARP_PMOF_OPCODES_2 0x192f0 +#define A_ULP_RX_INT_ENABLE_PCMD 0x19300 + +#define S_ENABLE_PCMD_SFIFO_3 30 +#define V_ENABLE_PCMD_SFIFO_3(x) ((x) << S_ENABLE_PCMD_SFIFO_3) +#define F_ENABLE_PCMD_SFIFO_3 V_ENABLE_PCMD_SFIFO_3(1U) + +#define S_ENABLE_PCMD_FIFO_3 29 +#define V_ENABLE_PCMD_FIFO_3(x) ((x) << S_ENABLE_PCMD_FIFO_3) +#define F_ENABLE_PCMD_FIFO_3 V_ENABLE_PCMD_FIFO_3(1U) + +#define S_ENABLE_PCMD_DDP_HINT_3 28 +#define V_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_ENABLE_PCMD_DDP_HINT_3) +#define F_ENABLE_PCMD_DDP_HINT_3 V_ENABLE_PCMD_DDP_HINT_3(1U) + +#define S_ENABLE_PCMD_TPT_3 27 +#define V_ENABLE_PCMD_TPT_3(x) ((x) << S_ENABLE_PCMD_TPT_3) +#define F_ENABLE_PCMD_TPT_3 V_ENABLE_PCMD_TPT_3(1U) + +#define S_ENABLE_PCMD_DDP_3 26 +#define V_ENABLE_PCMD_DDP_3(x) ((x) << S_ENABLE_PCMD_DDP_3) +#define F_ENABLE_PCMD_DDP_3 V_ENABLE_PCMD_DDP_3(1U) + +#define S_ENABLE_PCMD_MPAR_3 25 +#define V_ENABLE_PCMD_MPAR_3(x) ((x) << S_ENABLE_PCMD_MPAR_3) +#define F_ENABLE_PCMD_MPAR_3 V_ENABLE_PCMD_MPAR_3(1U) + +#define S_ENABLE_PCMD_MPAC_3 24 +#define V_ENABLE_PCMD_MPAC_3(x) ((x) << S_ENABLE_PCMD_MPAC_3) +#define F_ENABLE_PCMD_MPAC_3 V_ENABLE_PCMD_MPAC_3(1U) + +#define S_ENABLE_PCMD_SFIFO_2 22 +#define V_ENABLE_PCMD_SFIFO_2(x) ((x) << S_ENABLE_PCMD_SFIFO_2) +#define F_ENABLE_PCMD_SFIFO_2 V_ENABLE_PCMD_SFIFO_2(1U) + +#define S_ENABLE_PCMD_FIFO_2 21 +#define V_ENABLE_PCMD_FIFO_2(x) ((x) << S_ENABLE_PCMD_FIFO_2) +#define F_ENABLE_PCMD_FIFO_2 V_ENABLE_PCMD_FIFO_2(1U) + +#define S_ENABLE_PCMD_DDP_HINT_2 20 +#define V_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_ENABLE_PCMD_DDP_HINT_2) +#define F_ENABLE_PCMD_DDP_HINT_2 V_ENABLE_PCMD_DDP_HINT_2(1U) + +#define S_ENABLE_PCMD_TPT_2 19 +#define V_ENABLE_PCMD_TPT_2(x) ((x) << S_ENABLE_PCMD_TPT_2) +#define F_ENABLE_PCMD_TPT_2 V_ENABLE_PCMD_TPT_2(1U) + +#define S_ENABLE_PCMD_DDP_2 18 +#define V_ENABLE_PCMD_DDP_2(x) ((x) << S_ENABLE_PCMD_DDP_2) +#define F_ENABLE_PCMD_DDP_2 V_ENABLE_PCMD_DDP_2(1U) + +#define S_ENABLE_PCMD_MPAR_2 17 +#define V_ENABLE_PCMD_MPAR_2(x) ((x) << S_ENABLE_PCMD_MPAR_2) +#define F_ENABLE_PCMD_MPAR_2 V_ENABLE_PCMD_MPAR_2(1U) + +#define S_ENABLE_PCMD_MPAC_2 16 +#define V_ENABLE_PCMD_MPAC_2(x) ((x) << S_ENABLE_PCMD_MPAC_2) +#define F_ENABLE_PCMD_MPAC_2 V_ENABLE_PCMD_MPAC_2(1U) + +#define S_ENABLE_PCMD_SFIFO_1 14 +#define V_ENABLE_PCMD_SFIFO_1(x) ((x) << S_ENABLE_PCMD_SFIFO_1) +#define F_ENABLE_PCMD_SFIFO_1 V_ENABLE_PCMD_SFIFO_1(1U) + +#define S_ENABLE_PCMD_FIFO_1 13 +#define V_ENABLE_PCMD_FIFO_1(x) ((x) << S_ENABLE_PCMD_FIFO_1) +#define F_ENABLE_PCMD_FIFO_1 V_ENABLE_PCMD_FIFO_1(1U) + +#define S_ENABLE_PCMD_DDP_HINT_1 12 +#define V_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_ENABLE_PCMD_DDP_HINT_1) +#define F_ENABLE_PCMD_DDP_HINT_1 V_ENABLE_PCMD_DDP_HINT_1(1U) + +#define S_ENABLE_PCMD_TPT_1 11 +#define V_ENABLE_PCMD_TPT_1(x) ((x) << S_ENABLE_PCMD_TPT_1) +#define F_ENABLE_PCMD_TPT_1 V_ENABLE_PCMD_TPT_1(1U) + +#define S_ENABLE_PCMD_DDP_1 10 +#define V_ENABLE_PCMD_DDP_1(x) ((x) << S_ENABLE_PCMD_DDP_1) +#define F_ENABLE_PCMD_DDP_1 V_ENABLE_PCMD_DDP_1(1U) + +#define S_ENABLE_PCMD_MPAR_1 9 +#define V_ENABLE_PCMD_MPAR_1(x) ((x) << S_ENABLE_PCMD_MPAR_1) +#define F_ENABLE_PCMD_MPAR_1 V_ENABLE_PCMD_MPAR_1(1U) + +#define S_ENABLE_PCMD_MPAC_1 8 +#define V_ENABLE_PCMD_MPAC_1(x) ((x) << S_ENABLE_PCMD_MPAC_1) +#define F_ENABLE_PCMD_MPAC_1 V_ENABLE_PCMD_MPAC_1(1U) + +#define S_ENABLE_PCMD_SFIFO_0 6 +#define V_ENABLE_PCMD_SFIFO_0(x) ((x) << S_ENABLE_PCMD_SFIFO_0) +#define F_ENABLE_PCMD_SFIFO_0 V_ENABLE_PCMD_SFIFO_0(1U) + +#define S_ENABLE_PCMD_FIFO_0 5 +#define V_ENABLE_PCMD_FIFO_0(x) ((x) << S_ENABLE_PCMD_FIFO_0) +#define F_ENABLE_PCMD_FIFO_0 V_ENABLE_PCMD_FIFO_0(1U) + +#define S_ENABLE_PCMD_DDP_HINT_0 4 +#define V_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_ENABLE_PCMD_DDP_HINT_0) +#define F_ENABLE_PCMD_DDP_HINT_0 V_ENABLE_PCMD_DDP_HINT_0(1U) + +#define S_ENABLE_PCMD_TPT_0 3 +#define V_ENABLE_PCMD_TPT_0(x) ((x) << S_ENABLE_PCMD_TPT_0) +#define F_ENABLE_PCMD_TPT_0 V_ENABLE_PCMD_TPT_0(1U) + +#define S_ENABLE_PCMD_DDP_0 2 +#define V_ENABLE_PCMD_DDP_0(x) ((x) << S_ENABLE_PCMD_DDP_0) +#define F_ENABLE_PCMD_DDP_0 V_ENABLE_PCMD_DDP_0(1U) + +#define S_ENABLE_PCMD_MPAR_0 1 +#define V_ENABLE_PCMD_MPAR_0(x) ((x) << S_ENABLE_PCMD_MPAR_0) +#define F_ENABLE_PCMD_MPAR_0 V_ENABLE_PCMD_MPAR_0(1U) + +#define S_ENABLE_PCMD_MPAC_0 0 +#define V_ENABLE_PCMD_MPAC_0(x) ((x) << S_ENABLE_PCMD_MPAC_0) +#define F_ENABLE_PCMD_MPAC_0 V_ENABLE_PCMD_MPAC_0(1U) + +#define A_ULP_RX_INT_CAUSE_PCMD 0x19304 + +#define S_CAUSE_PCMD_SFIFO_3 30 +#define V_CAUSE_PCMD_SFIFO_3(x) ((x) << S_CAUSE_PCMD_SFIFO_3) +#define F_CAUSE_PCMD_SFIFO_3 V_CAUSE_PCMD_SFIFO_3(1U) + +#define S_CAUSE_PCMD_FIFO_3 29 +#define V_CAUSE_PCMD_FIFO_3(x) ((x) << S_CAUSE_PCMD_FIFO_3) +#define F_CAUSE_PCMD_FIFO_3 V_CAUSE_PCMD_FIFO_3(1U) + +#define S_CAUSE_PCMD_DDP_HINT_3 28 +#define V_CAUSE_PCMD_DDP_HINT_3(x) ((x) << S_CAUSE_PCMD_DDP_HINT_3) +#define F_CAUSE_PCMD_DDP_HINT_3 V_CAUSE_PCMD_DDP_HINT_3(1U) + +#define S_CAUSE_PCMD_TPT_3 27 +#define V_CAUSE_PCMD_TPT_3(x) ((x) << S_CAUSE_PCMD_TPT_3) +#define F_CAUSE_PCMD_TPT_3 V_CAUSE_PCMD_TPT_3(1U) + +#define S_CAUSE_PCMD_DDP_3 26 +#define V_CAUSE_PCMD_DDP_3(x) ((x) << S_CAUSE_PCMD_DDP_3) +#define F_CAUSE_PCMD_DDP_3 V_CAUSE_PCMD_DDP_3(1U) + +#define S_CAUSE_PCMD_MPAR_3 25 +#define V_CAUSE_PCMD_MPAR_3(x) ((x) << S_CAUSE_PCMD_MPAR_3) +#define F_CAUSE_PCMD_MPAR_3 V_CAUSE_PCMD_MPAR_3(1U) + +#define S_CAUSE_PCMD_MPAC_3 24 +#define V_CAUSE_PCMD_MPAC_3(x) ((x) << S_CAUSE_PCMD_MPAC_3) +#define F_CAUSE_PCMD_MPAC_3 V_CAUSE_PCMD_MPAC_3(1U) + +#define S_CAUSE_PCMD_SFIFO_2 22 +#define V_CAUSE_PCMD_SFIFO_2(x) ((x) << S_CAUSE_PCMD_SFIFO_2) +#define F_CAUSE_PCMD_SFIFO_2 V_CAUSE_PCMD_SFIFO_2(1U) + +#define S_CAUSE_PCMD_FIFO_2 21 +#define V_CAUSE_PCMD_FIFO_2(x) ((x) << S_CAUSE_PCMD_FIFO_2) +#define F_CAUSE_PCMD_FIFO_2 V_CAUSE_PCMD_FIFO_2(1U) + +#define S_CAUSE_PCMD_DDP_HINT_2 20 +#define V_CAUSE_PCMD_DDP_HINT_2(x) ((x) << S_CAUSE_PCMD_DDP_HINT_2) +#define F_CAUSE_PCMD_DDP_HINT_2 V_CAUSE_PCMD_DDP_HINT_2(1U) + +#define S_CAUSE_PCMD_TPT_2 19 +#define V_CAUSE_PCMD_TPT_2(x) ((x) << S_CAUSE_PCMD_TPT_2) +#define F_CAUSE_PCMD_TPT_2 V_CAUSE_PCMD_TPT_2(1U) + +#define S_CAUSE_PCMD_DDP_2 18 +#define V_CAUSE_PCMD_DDP_2(x) ((x) << S_CAUSE_PCMD_DDP_2) +#define F_CAUSE_PCMD_DDP_2 V_CAUSE_PCMD_DDP_2(1U) + +#define S_CAUSE_PCMD_MPAR_2 17 +#define V_CAUSE_PCMD_MPAR_2(x) ((x) << S_CAUSE_PCMD_MPAR_2) +#define F_CAUSE_PCMD_MPAR_2 V_CAUSE_PCMD_MPAR_2(1U) + +#define S_CAUSE_PCMD_MPAC_2 16 +#define V_CAUSE_PCMD_MPAC_2(x) ((x) << S_CAUSE_PCMD_MPAC_2) +#define F_CAUSE_PCMD_MPAC_2 V_CAUSE_PCMD_MPAC_2(1U) + +#define S_CAUSE_PCMD_SFIFO_1 14 +#define V_CAUSE_PCMD_SFIFO_1(x) ((x) << S_CAUSE_PCMD_SFIFO_1) +#define F_CAUSE_PCMD_SFIFO_1 V_CAUSE_PCMD_SFIFO_1(1U) + +#define S_CAUSE_PCMD_FIFO_1 13 +#define V_CAUSE_PCMD_FIFO_1(x) ((x) << S_CAUSE_PCMD_FIFO_1) +#define F_CAUSE_PCMD_FIFO_1 V_CAUSE_PCMD_FIFO_1(1U) + +#define S_CAUSE_PCMD_DDP_HINT_1 12 +#define V_CAUSE_PCMD_DDP_HINT_1(x) ((x) << S_CAUSE_PCMD_DDP_HINT_1) +#define F_CAUSE_PCMD_DDP_HINT_1 V_CAUSE_PCMD_DDP_HINT_1(1U) + +#define S_CAUSE_PCMD_TPT_1 11 +#define V_CAUSE_PCMD_TPT_1(x) ((x) << S_CAUSE_PCMD_TPT_1) +#define F_CAUSE_PCMD_TPT_1 V_CAUSE_PCMD_TPT_1(1U) + +#define S_CAUSE_PCMD_DDP_1 10 +#define V_CAUSE_PCMD_DDP_1(x) ((x) << S_CAUSE_PCMD_DDP_1) +#define F_CAUSE_PCMD_DDP_1 V_CAUSE_PCMD_DDP_1(1U) + +#define S_CAUSE_PCMD_MPAR_1 9 +#define V_CAUSE_PCMD_MPAR_1(x) ((x) << S_CAUSE_PCMD_MPAR_1) +#define F_CAUSE_PCMD_MPAR_1 V_CAUSE_PCMD_MPAR_1(1U) + +#define S_CAUSE_PCMD_MPAC_1 8 +#define V_CAUSE_PCMD_MPAC_1(x) ((x) << S_CAUSE_PCMD_MPAC_1) +#define F_CAUSE_PCMD_MPAC_1 V_CAUSE_PCMD_MPAC_1(1U) + +#define S_CAUSE_PCMD_SFIFO_0 6 +#define V_CAUSE_PCMD_SFIFO_0(x) ((x) << S_CAUSE_PCMD_SFIFO_0) +#define F_CAUSE_PCMD_SFIFO_0 V_CAUSE_PCMD_SFIFO_0(1U) + +#define S_CAUSE_PCMD_FIFO_0 5 +#define V_CAUSE_PCMD_FIFO_0(x) ((x) << S_CAUSE_PCMD_FIFO_0) +#define F_CAUSE_PCMD_FIFO_0 V_CAUSE_PCMD_FIFO_0(1U) + +#define S_CAUSE_PCMD_DDP_HINT_0 4 +#define V_CAUSE_PCMD_DDP_HINT_0(x) ((x) << S_CAUSE_PCMD_DDP_HINT_0) +#define F_CAUSE_PCMD_DDP_HINT_0 V_CAUSE_PCMD_DDP_HINT_0(1U) + +#define S_CAUSE_PCMD_TPT_0 3 +#define V_CAUSE_PCMD_TPT_0(x) ((x) << S_CAUSE_PCMD_TPT_0) +#define F_CAUSE_PCMD_TPT_0 V_CAUSE_PCMD_TPT_0(1U) + +#define S_CAUSE_PCMD_DDP_0 2 +#define V_CAUSE_PCMD_DDP_0(x) ((x) << S_CAUSE_PCMD_DDP_0) +#define F_CAUSE_PCMD_DDP_0 V_CAUSE_PCMD_DDP_0(1U) + +#define S_CAUSE_PCMD_MPAR_0 1 +#define V_CAUSE_PCMD_MPAR_0(x) ((x) << S_CAUSE_PCMD_MPAR_0) +#define F_CAUSE_PCMD_MPAR_0 V_CAUSE_PCMD_MPAR_0(1U) + +#define S_CAUSE_PCMD_MPAC_0 0 +#define V_CAUSE_PCMD_MPAC_0(x) ((x) << S_CAUSE_PCMD_MPAC_0) +#define F_CAUSE_PCMD_MPAC_0 V_CAUSE_PCMD_MPAC_0(1U) + +#define A_ULP_RX_PERR_ENABLE_PCMD 0x19308 + +#define S_PERR_ENABLE_PCMD_SFIFO_3 30 +#define V_PERR_ENABLE_PCMD_SFIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_3) +#define F_PERR_ENABLE_PCMD_SFIFO_3 V_PERR_ENABLE_PCMD_SFIFO_3(1U) + +#define S_PERR_ENABLE_PCMD_FIFO_3 29 +#define V_PERR_ENABLE_PCMD_FIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_3) +#define F_PERR_ENABLE_PCMD_FIFO_3 V_PERR_ENABLE_PCMD_FIFO_3(1U) + +#define S_PERR_ENABLE_PCMD_DDP_HINT_3 28 +#define V_PERR_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_3) +#define F_PERR_ENABLE_PCMD_DDP_HINT_3 V_PERR_ENABLE_PCMD_DDP_HINT_3(1U) + +#define S_PERR_ENABLE_PCMD_TPT_3 27 +#define V_PERR_ENABLE_PCMD_TPT_3(x) ((x) << S_PERR_ENABLE_PCMD_TPT_3) +#define F_PERR_ENABLE_PCMD_TPT_3 V_PERR_ENABLE_PCMD_TPT_3(1U) + +#define S_PERR_ENABLE_PCMD_DDP_3 26 +#define V_PERR_ENABLE_PCMD_DDP_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_3) +#define F_PERR_ENABLE_PCMD_DDP_3 V_PERR_ENABLE_PCMD_DDP_3(1U) + +#define S_PERR_ENABLE_PCMD_MPAR_3 25 +#define V_PERR_ENABLE_PCMD_MPAR_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_3) +#define F_PERR_ENABLE_PCMD_MPAR_3 V_PERR_ENABLE_PCMD_MPAR_3(1U) + +#define S_PERR_ENABLE_PCMD_MPAC_3 24 +#define V_PERR_ENABLE_PCMD_MPAC_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_3) +#define F_PERR_ENABLE_PCMD_MPAC_3 V_PERR_ENABLE_PCMD_MPAC_3(1U) + +#define S_PERR_ENABLE_PCMD_SFIFO_2 22 +#define V_PERR_ENABLE_PCMD_SFIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_2) +#define F_PERR_ENABLE_PCMD_SFIFO_2 V_PERR_ENABLE_PCMD_SFIFO_2(1U) + +#define S_PERR_ENABLE_PCMD_FIFO_2 21 +#define V_PERR_ENABLE_PCMD_FIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_2) +#define F_PERR_ENABLE_PCMD_FIFO_2 V_PERR_ENABLE_PCMD_FIFO_2(1U) + +#define S_PERR_ENABLE_PCMD_DDP_HINT_2 20 +#define V_PERR_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_2) +#define F_PERR_ENABLE_PCMD_DDP_HINT_2 V_PERR_ENABLE_PCMD_DDP_HINT_2(1U) + +#define S_PERR_ENABLE_PCMD_TPT_2 19 +#define V_PERR_ENABLE_PCMD_TPT_2(x) ((x) << S_PERR_ENABLE_PCMD_TPT_2) +#define F_PERR_ENABLE_PCMD_TPT_2 V_PERR_ENABLE_PCMD_TPT_2(1U) + +#define S_PERR_ENABLE_PCMD_DDP_2 18 +#define V_PERR_ENABLE_PCMD_DDP_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_2) +#define F_PERR_ENABLE_PCMD_DDP_2 V_PERR_ENABLE_PCMD_DDP_2(1U) + +#define S_PERR_ENABLE_PCMD_MPAR_2 17 +#define V_PERR_ENABLE_PCMD_MPAR_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_2) +#define F_PERR_ENABLE_PCMD_MPAR_2 V_PERR_ENABLE_PCMD_MPAR_2(1U) + +#define S_PERR_ENABLE_PCMD_MPAC_2 16 +#define V_PERR_ENABLE_PCMD_MPAC_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_2) +#define F_PERR_ENABLE_PCMD_MPAC_2 V_PERR_ENABLE_PCMD_MPAC_2(1U) + +#define S_PERR_ENABLE_PCMD_SFIFO_1 14 +#define V_PERR_ENABLE_PCMD_SFIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_1) +#define F_PERR_ENABLE_PCMD_SFIFO_1 V_PERR_ENABLE_PCMD_SFIFO_1(1U) + +#define S_PERR_ENABLE_PCMD_FIFO_1 13 +#define V_PERR_ENABLE_PCMD_FIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_1) +#define F_PERR_ENABLE_PCMD_FIFO_1 V_PERR_ENABLE_PCMD_FIFO_1(1U) + +#define S_PERR_ENABLE_PCMD_DDP_HINT_1 12 +#define V_PERR_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_1) +#define F_PERR_ENABLE_PCMD_DDP_HINT_1 V_PERR_ENABLE_PCMD_DDP_HINT_1(1U) + +#define S_PERR_ENABLE_PCMD_TPT_1 11 +#define V_PERR_ENABLE_PCMD_TPT_1(x) ((x) << S_PERR_ENABLE_PCMD_TPT_1) +#define F_PERR_ENABLE_PCMD_TPT_1 V_PERR_ENABLE_PCMD_TPT_1(1U) + +#define S_PERR_ENABLE_PCMD_DDP_1 10 +#define V_PERR_ENABLE_PCMD_DDP_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_1) +#define F_PERR_ENABLE_PCMD_DDP_1 V_PERR_ENABLE_PCMD_DDP_1(1U) + +#define S_PERR_ENABLE_PCMD_MPAR_1 9 +#define V_PERR_ENABLE_PCMD_MPAR_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_1) +#define F_PERR_ENABLE_PCMD_MPAR_1 V_PERR_ENABLE_PCMD_MPAR_1(1U) + +#define S_PERR_ENABLE_PCMD_MPAC_1 8 +#define V_PERR_ENABLE_PCMD_MPAC_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_1) +#define F_PERR_ENABLE_PCMD_MPAC_1 V_PERR_ENABLE_PCMD_MPAC_1(1U) + +#define S_PERR_ENABLE_PCMD_SFIFO_0 6 +#define V_PERR_ENABLE_PCMD_SFIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_0) +#define F_PERR_ENABLE_PCMD_SFIFO_0 V_PERR_ENABLE_PCMD_SFIFO_0(1U) + +#define S_PERR_ENABLE_PCMD_FIFO_0 5 +#define V_PERR_ENABLE_PCMD_FIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_0) +#define F_PERR_ENABLE_PCMD_FIFO_0 V_PERR_ENABLE_PCMD_FIFO_0(1U) + +#define S_PERR_ENABLE_PCMD_DDP_HINT_0 4 +#define V_PERR_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_0) +#define F_PERR_ENABLE_PCMD_DDP_HINT_0 V_PERR_ENABLE_PCMD_DDP_HINT_0(1U) + +#define S_PERR_ENABLE_PCMD_TPT_0 3 +#define V_PERR_ENABLE_PCMD_TPT_0(x) ((x) << S_PERR_ENABLE_PCMD_TPT_0) +#define F_PERR_ENABLE_PCMD_TPT_0 V_PERR_ENABLE_PCMD_TPT_0(1U) + +#define S_PERR_ENABLE_PCMD_DDP_0 2 +#define V_PERR_ENABLE_PCMD_DDP_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_0) +#define F_PERR_ENABLE_PCMD_DDP_0 V_PERR_ENABLE_PCMD_DDP_0(1U) + +#define S_PERR_ENABLE_PCMD_MPAR_0 1 +#define V_PERR_ENABLE_PCMD_MPAR_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_0) +#define F_PERR_ENABLE_PCMD_MPAR_0 V_PERR_ENABLE_PCMD_MPAR_0(1U) + +#define S_PERR_ENABLE_PCMD_MPAC_0 0 +#define V_PERR_ENABLE_PCMD_MPAC_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_0) +#define F_PERR_ENABLE_PCMD_MPAC_0 V_PERR_ENABLE_PCMD_MPAC_0(1U) + +#define A_ULP_RX_INT_ENABLE_DATA 0x19310 + +#define S_ENABLE_DATA_SNOOP_3 29 +#define V_ENABLE_DATA_SNOOP_3(x) ((x) << S_ENABLE_DATA_SNOOP_3) +#define F_ENABLE_DATA_SNOOP_3 V_ENABLE_DATA_SNOOP_3(1U) + +#define S_ENABLE_DATA_SFIFO_3 28 +#define V_ENABLE_DATA_SFIFO_3(x) ((x) << S_ENABLE_DATA_SFIFO_3) +#define F_ENABLE_DATA_SFIFO_3 V_ENABLE_DATA_SFIFO_3(1U) + +#define S_ENABLE_DATA_FIFO_3 27 +#define V_ENABLE_DATA_FIFO_3(x) ((x) << S_ENABLE_DATA_FIFO_3) +#define F_ENABLE_DATA_FIFO_3 V_ENABLE_DATA_FIFO_3(1U) + +#define S_ENABLE_DATA_DDP_3 26 +#define V_ENABLE_DATA_DDP_3(x) ((x) << S_ENABLE_DATA_DDP_3) +#define F_ENABLE_DATA_DDP_3 V_ENABLE_DATA_DDP_3(1U) + +#define S_ENABLE_DATA_CTX_3 25 +#define V_ENABLE_DATA_CTX_3(x) ((x) << S_ENABLE_DATA_CTX_3) +#define F_ENABLE_DATA_CTX_3 V_ENABLE_DATA_CTX_3(1U) + +#define S_ENABLE_DATA_PARSER_3 24 +#define V_ENABLE_DATA_PARSER_3(x) ((x) << S_ENABLE_DATA_PARSER_3) +#define F_ENABLE_DATA_PARSER_3 V_ENABLE_DATA_PARSER_3(1U) + +#define S_ENABLE_DATA_SNOOP_2 21 +#define V_ENABLE_DATA_SNOOP_2(x) ((x) << S_ENABLE_DATA_SNOOP_2) +#define F_ENABLE_DATA_SNOOP_2 V_ENABLE_DATA_SNOOP_2(1U) + +#define S_ENABLE_DATA_SFIFO_2 20 +#define V_ENABLE_DATA_SFIFO_2(x) ((x) << S_ENABLE_DATA_SFIFO_2) +#define F_ENABLE_DATA_SFIFO_2 V_ENABLE_DATA_SFIFO_2(1U) + +#define S_ENABLE_DATA_FIFO_2 19 +#define V_ENABLE_DATA_FIFO_2(x) ((x) << S_ENABLE_DATA_FIFO_2) +#define F_ENABLE_DATA_FIFO_2 V_ENABLE_DATA_FIFO_2(1U) + +#define S_ENABLE_DATA_DDP_2 18 +#define V_ENABLE_DATA_DDP_2(x) ((x) << S_ENABLE_DATA_DDP_2) +#define F_ENABLE_DATA_DDP_2 V_ENABLE_DATA_DDP_2(1U) + +#define S_ENABLE_DATA_CTX_2 17 +#define V_ENABLE_DATA_CTX_2(x) ((x) << S_ENABLE_DATA_CTX_2) +#define F_ENABLE_DATA_CTX_2 V_ENABLE_DATA_CTX_2(1U) + +#define S_ENABLE_DATA_PARSER_2 16 +#define V_ENABLE_DATA_PARSER_2(x) ((x) << S_ENABLE_DATA_PARSER_2) +#define F_ENABLE_DATA_PARSER_2 V_ENABLE_DATA_PARSER_2(1U) + +#define S_ENABLE_DATA_SNOOP_1 13 +#define V_ENABLE_DATA_SNOOP_1(x) ((x) << S_ENABLE_DATA_SNOOP_1) +#define F_ENABLE_DATA_SNOOP_1 V_ENABLE_DATA_SNOOP_1(1U) + +#define S_ENABLE_DATA_SFIFO_1 12 +#define V_ENABLE_DATA_SFIFO_1(x) ((x) << S_ENABLE_DATA_SFIFO_1) +#define F_ENABLE_DATA_SFIFO_1 V_ENABLE_DATA_SFIFO_1(1U) + +#define S_ENABLE_DATA_FIFO_1 11 +#define V_ENABLE_DATA_FIFO_1(x) ((x) << S_ENABLE_DATA_FIFO_1) +#define F_ENABLE_DATA_FIFO_1 V_ENABLE_DATA_FIFO_1(1U) + +#define S_ENABLE_DATA_DDP_1 10 +#define V_ENABLE_DATA_DDP_1(x) ((x) << S_ENABLE_DATA_DDP_1) +#define F_ENABLE_DATA_DDP_1 V_ENABLE_DATA_DDP_1(1U) + +#define S_ENABLE_DATA_CTX_1 9 +#define V_ENABLE_DATA_CTX_1(x) ((x) << S_ENABLE_DATA_CTX_1) +#define F_ENABLE_DATA_CTX_1 V_ENABLE_DATA_CTX_1(1U) + +#define S_ENABLE_DATA_PARSER_1 8 +#define V_ENABLE_DATA_PARSER_1(x) ((x) << S_ENABLE_DATA_PARSER_1) +#define F_ENABLE_DATA_PARSER_1 V_ENABLE_DATA_PARSER_1(1U) + +#define S_ENABLE_DATA_SNOOP_0 5 +#define V_ENABLE_DATA_SNOOP_0(x) ((x) << S_ENABLE_DATA_SNOOP_0) +#define F_ENABLE_DATA_SNOOP_0 V_ENABLE_DATA_SNOOP_0(1U) + +#define S_ENABLE_DATA_SFIFO_0 4 +#define V_ENABLE_DATA_SFIFO_0(x) ((x) << S_ENABLE_DATA_SFIFO_0) +#define F_ENABLE_DATA_SFIFO_0 V_ENABLE_DATA_SFIFO_0(1U) + +#define S_ENABLE_DATA_FIFO_0 3 +#define V_ENABLE_DATA_FIFO_0(x) ((x) << S_ENABLE_DATA_FIFO_0) +#define F_ENABLE_DATA_FIFO_0 V_ENABLE_DATA_FIFO_0(1U) + +#define S_ENABLE_DATA_DDP_0 2 +#define V_ENABLE_DATA_DDP_0(x) ((x) << S_ENABLE_DATA_DDP_0) +#define F_ENABLE_DATA_DDP_0 V_ENABLE_DATA_DDP_0(1U) + +#define S_ENABLE_DATA_CTX_0 1 +#define V_ENABLE_DATA_CTX_0(x) ((x) << S_ENABLE_DATA_CTX_0) +#define F_ENABLE_DATA_CTX_0 V_ENABLE_DATA_CTX_0(1U) + +#define S_ENABLE_DATA_PARSER_0 0 +#define V_ENABLE_DATA_PARSER_0(x) ((x) << S_ENABLE_DATA_PARSER_0) +#define F_ENABLE_DATA_PARSER_0 V_ENABLE_DATA_PARSER_0(1U) + +#define A_ULP_RX_INT_CAUSE_DATA 0x19314 + +#define S_CAUSE_DATA_SNOOP_3 29 +#define V_CAUSE_DATA_SNOOP_3(x) ((x) << S_CAUSE_DATA_SNOOP_3) +#define F_CAUSE_DATA_SNOOP_3 V_CAUSE_DATA_SNOOP_3(1U) + +#define S_CAUSE_DATA_SFIFO_3 28 +#define V_CAUSE_DATA_SFIFO_3(x) ((x) << S_CAUSE_DATA_SFIFO_3) +#define F_CAUSE_DATA_SFIFO_3 V_CAUSE_DATA_SFIFO_3(1U) + +#define S_CAUSE_DATA_FIFO_3 27 +#define V_CAUSE_DATA_FIFO_3(x) ((x) << S_CAUSE_DATA_FIFO_3) +#define F_CAUSE_DATA_FIFO_3 V_CAUSE_DATA_FIFO_3(1U) + +#define S_CAUSE_DATA_DDP_3 26 +#define V_CAUSE_DATA_DDP_3(x) ((x) << S_CAUSE_DATA_DDP_3) +#define F_CAUSE_DATA_DDP_3 V_CAUSE_DATA_DDP_3(1U) + +#define S_CAUSE_DATA_CTX_3 25 +#define V_CAUSE_DATA_CTX_3(x) ((x) << S_CAUSE_DATA_CTX_3) +#define F_CAUSE_DATA_CTX_3 V_CAUSE_DATA_CTX_3(1U) + +#define S_CAUSE_DATA_PARSER_3 24 +#define V_CAUSE_DATA_PARSER_3(x) ((x) << S_CAUSE_DATA_PARSER_3) +#define F_CAUSE_DATA_PARSER_3 V_CAUSE_DATA_PARSER_3(1U) + +#define S_CAUSE_DATA_SNOOP_2 21 +#define V_CAUSE_DATA_SNOOP_2(x) ((x) << S_CAUSE_DATA_SNOOP_2) +#define F_CAUSE_DATA_SNOOP_2 V_CAUSE_DATA_SNOOP_2(1U) + +#define S_CAUSE_DATA_SFIFO_2 20 +#define V_CAUSE_DATA_SFIFO_2(x) ((x) << S_CAUSE_DATA_SFIFO_2) +#define F_CAUSE_DATA_SFIFO_2 V_CAUSE_DATA_SFIFO_2(1U) + +#define S_CAUSE_DATA_FIFO_2 19 +#define V_CAUSE_DATA_FIFO_2(x) ((x) << S_CAUSE_DATA_FIFO_2) +#define F_CAUSE_DATA_FIFO_2 V_CAUSE_DATA_FIFO_2(1U) + +#define S_CAUSE_DATA_DDP_2 18 +#define V_CAUSE_DATA_DDP_2(x) ((x) << S_CAUSE_DATA_DDP_2) +#define F_CAUSE_DATA_DDP_2 V_CAUSE_DATA_DDP_2(1U) + +#define S_CAUSE_DATA_CTX_2 17 +#define V_CAUSE_DATA_CTX_2(x) ((x) << S_CAUSE_DATA_CTX_2) +#define F_CAUSE_DATA_CTX_2 V_CAUSE_DATA_CTX_2(1U) + +#define S_CAUSE_DATA_PARSER_2 16 +#define V_CAUSE_DATA_PARSER_2(x) ((x) << S_CAUSE_DATA_PARSER_2) +#define F_CAUSE_DATA_PARSER_2 V_CAUSE_DATA_PARSER_2(1U) + +#define S_CAUSE_DATA_SNOOP_1 13 +#define V_CAUSE_DATA_SNOOP_1(x) ((x) << S_CAUSE_DATA_SNOOP_1) +#define F_CAUSE_DATA_SNOOP_1 V_CAUSE_DATA_SNOOP_1(1U) + +#define S_CAUSE_DATA_SFIFO_1 12 +#define V_CAUSE_DATA_SFIFO_1(x) ((x) << S_CAUSE_DATA_SFIFO_1) +#define F_CAUSE_DATA_SFIFO_1 V_CAUSE_DATA_SFIFO_1(1U) + +#define S_CAUSE_DATA_FIFO_1 11 +#define V_CAUSE_DATA_FIFO_1(x) ((x) << S_CAUSE_DATA_FIFO_1) +#define F_CAUSE_DATA_FIFO_1 V_CAUSE_DATA_FIFO_1(1U) + +#define S_CAUSE_DATA_DDP_1 10 +#define V_CAUSE_DATA_DDP_1(x) ((x) << S_CAUSE_DATA_DDP_1) +#define F_CAUSE_DATA_DDP_1 V_CAUSE_DATA_DDP_1(1U) + +#define S_CAUSE_DATA_CTX_1 9 +#define V_CAUSE_DATA_CTX_1(x) ((x) << S_CAUSE_DATA_CTX_1) +#define F_CAUSE_DATA_CTX_1 V_CAUSE_DATA_CTX_1(1U) + +#define S_CAUSE_DATA_PARSER_1 8 +#define V_CAUSE_DATA_PARSER_1(x) ((x) << S_CAUSE_DATA_PARSER_1) +#define F_CAUSE_DATA_PARSER_1 V_CAUSE_DATA_PARSER_1(1U) + +#define S_CAUSE_DATA_SNOOP_0 5 +#define V_CAUSE_DATA_SNOOP_0(x) ((x) << S_CAUSE_DATA_SNOOP_0) +#define F_CAUSE_DATA_SNOOP_0 V_CAUSE_DATA_SNOOP_0(1U) + +#define S_CAUSE_DATA_SFIFO_0 4 +#define V_CAUSE_DATA_SFIFO_0(x) ((x) << S_CAUSE_DATA_SFIFO_0) +#define F_CAUSE_DATA_SFIFO_0 V_CAUSE_DATA_SFIFO_0(1U) + +#define S_CAUSE_DATA_FIFO_0 3 +#define V_CAUSE_DATA_FIFO_0(x) ((x) << S_CAUSE_DATA_FIFO_0) +#define F_CAUSE_DATA_FIFO_0 V_CAUSE_DATA_FIFO_0(1U) + +#define S_CAUSE_DATA_DDP_0 2 +#define V_CAUSE_DATA_DDP_0(x) ((x) << S_CAUSE_DATA_DDP_0) +#define F_CAUSE_DATA_DDP_0 V_CAUSE_DATA_DDP_0(1U) + +#define S_CAUSE_DATA_CTX_0 1 +#define V_CAUSE_DATA_CTX_0(x) ((x) << S_CAUSE_DATA_CTX_0) +#define F_CAUSE_DATA_CTX_0 V_CAUSE_DATA_CTX_0(1U) + +#define S_CAUSE_DATA_PARSER_0 0 +#define V_CAUSE_DATA_PARSER_0(x) ((x) << S_CAUSE_DATA_PARSER_0) +#define F_CAUSE_DATA_PARSER_0 V_CAUSE_DATA_PARSER_0(1U) + +#define A_ULP_RX_PERR_ENABLE_DATA 0x19318 + +#define S_PERR_ENABLE_DATA_SNOOP_3 29 +#define V_PERR_ENABLE_DATA_SNOOP_3(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_3) +#define F_PERR_ENABLE_DATA_SNOOP_3 V_PERR_ENABLE_DATA_SNOOP_3(1U) + +#define S_PERR_ENABLE_DATA_SFIFO_3 28 +#define V_PERR_ENABLE_DATA_SFIFO_3(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_3) +#define F_PERR_ENABLE_DATA_SFIFO_3 V_PERR_ENABLE_DATA_SFIFO_3(1U) + +#define S_PERR_ENABLE_DATA_FIFO_3 27 +#define V_PERR_ENABLE_DATA_FIFO_3(x) ((x) << S_PERR_ENABLE_DATA_FIFO_3) +#define F_PERR_ENABLE_DATA_FIFO_3 V_PERR_ENABLE_DATA_FIFO_3(1U) + +#define S_PERR_ENABLE_DATA_DDP_3 26 +#define V_PERR_ENABLE_DATA_DDP_3(x) ((x) << S_PERR_ENABLE_DATA_DDP_3) +#define F_PERR_ENABLE_DATA_DDP_3 V_PERR_ENABLE_DATA_DDP_3(1U) + +#define S_PERR_ENABLE_DATA_CTX_3 25 +#define V_PERR_ENABLE_DATA_CTX_3(x) ((x) << S_PERR_ENABLE_DATA_CTX_3) +#define F_PERR_ENABLE_DATA_CTX_3 V_PERR_ENABLE_DATA_CTX_3(1U) + +#define S_PERR_ENABLE_DATA_PARSER_3 24 +#define V_PERR_ENABLE_DATA_PARSER_3(x) ((x) << S_PERR_ENABLE_DATA_PARSER_3) +#define F_PERR_ENABLE_DATA_PARSER_3 V_PERR_ENABLE_DATA_PARSER_3(1U) + +#define S_PERR_ENABLE_DATA_SNOOP_2 21 +#define V_PERR_ENABLE_DATA_SNOOP_2(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_2) +#define F_PERR_ENABLE_DATA_SNOOP_2 V_PERR_ENABLE_DATA_SNOOP_2(1U) + +#define S_PERR_ENABLE_DATA_SFIFO_2 20 +#define V_PERR_ENABLE_DATA_SFIFO_2(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_2) +#define F_PERR_ENABLE_DATA_SFIFO_2 V_PERR_ENABLE_DATA_SFIFO_2(1U) + +#define S_PERR_ENABLE_DATA_FIFO_2 19 +#define V_PERR_ENABLE_DATA_FIFO_2(x) ((x) << S_PERR_ENABLE_DATA_FIFO_2) +#define F_PERR_ENABLE_DATA_FIFO_2 V_PERR_ENABLE_DATA_FIFO_2(1U) + +#define S_PERR_ENABLE_DATA_DDP_2 18 +#define V_PERR_ENABLE_DATA_DDP_2(x) ((x) << S_PERR_ENABLE_DATA_DDP_2) +#define F_PERR_ENABLE_DATA_DDP_2 V_PERR_ENABLE_DATA_DDP_2(1U) + +#define S_PERR_ENABLE_DATA_CTX_2 17 +#define V_PERR_ENABLE_DATA_CTX_2(x) ((x) << S_PERR_ENABLE_DATA_CTX_2) +#define F_PERR_ENABLE_DATA_CTX_2 V_PERR_ENABLE_DATA_CTX_2(1U) + +#define S_PERR_ENABLE_DATA_PARSER_2 16 +#define V_PERR_ENABLE_DATA_PARSER_2(x) ((x) << S_PERR_ENABLE_DATA_PARSER_2) +#define F_PERR_ENABLE_DATA_PARSER_2 V_PERR_ENABLE_DATA_PARSER_2(1U) + +#define S_PERR_ENABLE_DATA_SNOOP_1 13 +#define V_PERR_ENABLE_DATA_SNOOP_1(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_1) +#define F_PERR_ENABLE_DATA_SNOOP_1 V_PERR_ENABLE_DATA_SNOOP_1(1U) + +#define S_PERR_ENABLE_DATA_SFIFO_1 12 +#define V_PERR_ENABLE_DATA_SFIFO_1(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_1) +#define F_PERR_ENABLE_DATA_SFIFO_1 V_PERR_ENABLE_DATA_SFIFO_1(1U) + +#define S_PERR_ENABLE_DATA_FIFO_1 11 +#define V_PERR_ENABLE_DATA_FIFO_1(x) ((x) << S_PERR_ENABLE_DATA_FIFO_1) +#define F_PERR_ENABLE_DATA_FIFO_1 V_PERR_ENABLE_DATA_FIFO_1(1U) + +#define S_PERR_ENABLE_DATA_DDP_1 10 +#define V_PERR_ENABLE_DATA_DDP_1(x) ((x) << S_PERR_ENABLE_DATA_DDP_1) +#define F_PERR_ENABLE_DATA_DDP_1 V_PERR_ENABLE_DATA_DDP_1(1U) + +#define S_PERR_ENABLE_DATA_CTX_1 9 +#define V_PERR_ENABLE_DATA_CTX_1(x) ((x) << S_PERR_ENABLE_DATA_CTX_1) +#define F_PERR_ENABLE_DATA_CTX_1 V_PERR_ENABLE_DATA_CTX_1(1U) + +#define S_PERR_ENABLE_DATA_PARSER_1 8 +#define V_PERR_ENABLE_DATA_PARSER_1(x) ((x) << S_PERR_ENABLE_DATA_PARSER_1) +#define F_PERR_ENABLE_DATA_PARSER_1 V_PERR_ENABLE_DATA_PARSER_1(1U) + +#define S_PERR_ENABLE_DATA_SNOOP_0 5 +#define V_PERR_ENABLE_DATA_SNOOP_0(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_0) +#define F_PERR_ENABLE_DATA_SNOOP_0 V_PERR_ENABLE_DATA_SNOOP_0(1U) + +#define S_PERR_ENABLE_DATA_SFIFO_0 4 +#define V_PERR_ENABLE_DATA_SFIFO_0(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_0) +#define F_PERR_ENABLE_DATA_SFIFO_0 V_PERR_ENABLE_DATA_SFIFO_0(1U) + +#define S_PERR_ENABLE_DATA_FIFO_0 3 +#define V_PERR_ENABLE_DATA_FIFO_0(x) ((x) << S_PERR_ENABLE_DATA_FIFO_0) +#define F_PERR_ENABLE_DATA_FIFO_0 V_PERR_ENABLE_DATA_FIFO_0(1U) + +#define S_PERR_ENABLE_DATA_DDP_0 2 +#define V_PERR_ENABLE_DATA_DDP_0(x) ((x) << S_PERR_ENABLE_DATA_DDP_0) +#define F_PERR_ENABLE_DATA_DDP_0 V_PERR_ENABLE_DATA_DDP_0(1U) + +#define S_PERR_ENABLE_DATA_CTX_0 1 +#define V_PERR_ENABLE_DATA_CTX_0(x) ((x) << S_PERR_ENABLE_DATA_CTX_0) +#define F_PERR_ENABLE_DATA_CTX_0 V_PERR_ENABLE_DATA_CTX_0(1U) + +#define S_PERR_ENABLE_DATA_PARSER_0 0 +#define V_PERR_ENABLE_DATA_PARSER_0(x) ((x) << S_PERR_ENABLE_DATA_PARSER_0) +#define F_PERR_ENABLE_DATA_PARSER_0 V_PERR_ENABLE_DATA_PARSER_0(1U) + +#define A_ULP_RX_INT_ENABLE_ARB 0x19320 + +#define S_ENABLE_ARB_PBL_PF_3 27 +#define V_ENABLE_ARB_PBL_PF_3(x) ((x) << S_ENABLE_ARB_PBL_PF_3) +#define F_ENABLE_ARB_PBL_PF_3 V_ENABLE_ARB_PBL_PF_3(1U) + +#define S_ENABLE_ARB_PF_3 26 +#define V_ENABLE_ARB_PF_3(x) ((x) << S_ENABLE_ARB_PF_3) +#define F_ENABLE_ARB_PF_3 V_ENABLE_ARB_PF_3(1U) + +#define S_ENABLE_ARB_TPT_PF_3 25 +#define V_ENABLE_ARB_TPT_PF_3(x) ((x) << S_ENABLE_ARB_TPT_PF_3) +#define F_ENABLE_ARB_TPT_PF_3 V_ENABLE_ARB_TPT_PF_3(1U) + +#define S_ENABLE_ARB_F_3 24 +#define V_ENABLE_ARB_F_3(x) ((x) << S_ENABLE_ARB_F_3) +#define F_ENABLE_ARB_F_3 V_ENABLE_ARB_F_3(1U) + +#define S_ENABLE_ARB_PBL_PF_2 19 +#define V_ENABLE_ARB_PBL_PF_2(x) ((x) << S_ENABLE_ARB_PBL_PF_2) +#define F_ENABLE_ARB_PBL_PF_2 V_ENABLE_ARB_PBL_PF_2(1U) + +#define S_ENABLE_ARB_PF_2 18 +#define V_ENABLE_ARB_PF_2(x) ((x) << S_ENABLE_ARB_PF_2) +#define F_ENABLE_ARB_PF_2 V_ENABLE_ARB_PF_2(1U) + +#define S_ENABLE_ARB_TPT_PF_2 17 +#define V_ENABLE_ARB_TPT_PF_2(x) ((x) << S_ENABLE_ARB_TPT_PF_2) +#define F_ENABLE_ARB_TPT_PF_2 V_ENABLE_ARB_TPT_PF_2(1U) + +#define S_ENABLE_ARB_F_2 16 +#define V_ENABLE_ARB_F_2(x) ((x) << S_ENABLE_ARB_F_2) +#define F_ENABLE_ARB_F_2 V_ENABLE_ARB_F_2(1U) + +#define S_ENABLE_ARB_PBL_PF_1 11 +#define V_ENABLE_ARB_PBL_PF_1(x) ((x) << S_ENABLE_ARB_PBL_PF_1) +#define F_ENABLE_ARB_PBL_PF_1 V_ENABLE_ARB_PBL_PF_1(1U) + +#define S_ENABLE_ARB_PF_1 10 +#define V_ENABLE_ARB_PF_1(x) ((x) << S_ENABLE_ARB_PF_1) +#define F_ENABLE_ARB_PF_1 V_ENABLE_ARB_PF_1(1U) + +#define S_ENABLE_ARB_TPT_PF_1 9 +#define V_ENABLE_ARB_TPT_PF_1(x) ((x) << S_ENABLE_ARB_TPT_PF_1) +#define F_ENABLE_ARB_TPT_PF_1 V_ENABLE_ARB_TPT_PF_1(1U) + +#define S_ENABLE_ARB_F_1 8 +#define V_ENABLE_ARB_F_1(x) ((x) << S_ENABLE_ARB_F_1) +#define F_ENABLE_ARB_F_1 V_ENABLE_ARB_F_1(1U) + +#define S_ENABLE_ARB_PBL_PF_0 3 +#define V_ENABLE_ARB_PBL_PF_0(x) ((x) << S_ENABLE_ARB_PBL_PF_0) +#define F_ENABLE_ARB_PBL_PF_0 V_ENABLE_ARB_PBL_PF_0(1U) + +#define S_ENABLE_ARB_PF_0 2 +#define V_ENABLE_ARB_PF_0(x) ((x) << S_ENABLE_ARB_PF_0) +#define F_ENABLE_ARB_PF_0 V_ENABLE_ARB_PF_0(1U) + +#define S_ENABLE_ARB_TPT_PF_0 1 +#define V_ENABLE_ARB_TPT_PF_0(x) ((x) << S_ENABLE_ARB_TPT_PF_0) +#define F_ENABLE_ARB_TPT_PF_0 V_ENABLE_ARB_TPT_PF_0(1U) + +#define S_ENABLE_ARB_F_0 0 +#define V_ENABLE_ARB_F_0(x) ((x) << S_ENABLE_ARB_F_0) +#define F_ENABLE_ARB_F_0 V_ENABLE_ARB_F_0(1U) + +#define A_ULP_RX_INT_CAUSE_ARB 0x19324 + +#define S_CAUSE_ARB_PBL_PF_3 27 +#define V_CAUSE_ARB_PBL_PF_3(x) ((x) << S_CAUSE_ARB_PBL_PF_3) +#define F_CAUSE_ARB_PBL_PF_3 V_CAUSE_ARB_PBL_PF_3(1U) + +#define S_CAUSE_ARB_PF_3 26 +#define V_CAUSE_ARB_PF_3(x) ((x) << S_CAUSE_ARB_PF_3) +#define F_CAUSE_ARB_PF_3 V_CAUSE_ARB_PF_3(1U) + +#define S_CAUSE_ARB_TPT_PF_3 25 +#define V_CAUSE_ARB_TPT_PF_3(x) ((x) << S_CAUSE_ARB_TPT_PF_3) +#define F_CAUSE_ARB_TPT_PF_3 V_CAUSE_ARB_TPT_PF_3(1U) + +#define S_CAUSE_ARB_F_3 24 +#define V_CAUSE_ARB_F_3(x) ((x) << S_CAUSE_ARB_F_3) +#define F_CAUSE_ARB_F_3 V_CAUSE_ARB_F_3(1U) + +#define S_CAUSE_ARB_PBL_PF_2 19 +#define V_CAUSE_ARB_PBL_PF_2(x) ((x) << S_CAUSE_ARB_PBL_PF_2) +#define F_CAUSE_ARB_PBL_PF_2 V_CAUSE_ARB_PBL_PF_2(1U) + +#define S_CAUSE_ARB_PF_2 18 +#define V_CAUSE_ARB_PF_2(x) ((x) << S_CAUSE_ARB_PF_2) +#define F_CAUSE_ARB_PF_2 V_CAUSE_ARB_PF_2(1U) + +#define S_CAUSE_ARB_TPT_PF_2 17 +#define V_CAUSE_ARB_TPT_PF_2(x) ((x) << S_CAUSE_ARB_TPT_PF_2) +#define F_CAUSE_ARB_TPT_PF_2 V_CAUSE_ARB_TPT_PF_2(1U) + +#define S_CAUSE_ARB_F_2 16 +#define V_CAUSE_ARB_F_2(x) ((x) << S_CAUSE_ARB_F_2) +#define F_CAUSE_ARB_F_2 V_CAUSE_ARB_F_2(1U) + +#define S_CAUSE_ARB_PBL_PF_1 11 +#define V_CAUSE_ARB_PBL_PF_1(x) ((x) << S_CAUSE_ARB_PBL_PF_1) +#define F_CAUSE_ARB_PBL_PF_1 V_CAUSE_ARB_PBL_PF_1(1U) + +#define S_CAUSE_ARB_PF_1 10 +#define V_CAUSE_ARB_PF_1(x) ((x) << S_CAUSE_ARB_PF_1) +#define F_CAUSE_ARB_PF_1 V_CAUSE_ARB_PF_1(1U) + +#define S_CAUSE_ARB_TPT_PF_1 9 +#define V_CAUSE_ARB_TPT_PF_1(x) ((x) << S_CAUSE_ARB_TPT_PF_1) +#define F_CAUSE_ARB_TPT_PF_1 V_CAUSE_ARB_TPT_PF_1(1U) + +#define S_CAUSE_ARB_F_1 8 +#define V_CAUSE_ARB_F_1(x) ((x) << S_CAUSE_ARB_F_1) +#define F_CAUSE_ARB_F_1 V_CAUSE_ARB_F_1(1U) + +#define S_CAUSE_ARB_PBL_PF_0 3 +#define V_CAUSE_ARB_PBL_PF_0(x) ((x) << S_CAUSE_ARB_PBL_PF_0) +#define F_CAUSE_ARB_PBL_PF_0 V_CAUSE_ARB_PBL_PF_0(1U) + +#define S_CAUSE_ARB_PF_0 2 +#define V_CAUSE_ARB_PF_0(x) ((x) << S_CAUSE_ARB_PF_0) +#define F_CAUSE_ARB_PF_0 V_CAUSE_ARB_PF_0(1U) + +#define S_CAUSE_ARB_TPT_PF_0 1 +#define V_CAUSE_ARB_TPT_PF_0(x) ((x) << S_CAUSE_ARB_TPT_PF_0) +#define F_CAUSE_ARB_TPT_PF_0 V_CAUSE_ARB_TPT_PF_0(1U) + +#define S_CAUSE_ARB_F_0 0 +#define V_CAUSE_ARB_F_0(x) ((x) << S_CAUSE_ARB_F_0) +#define F_CAUSE_ARB_F_0 V_CAUSE_ARB_F_0(1U) + +#define A_ULP_RX_PERR_ENABLE_ARB 0x19328 + +#define S_PERR_ENABLE_ARB_PBL_PF_3 27 +#define V_PERR_ENABLE_ARB_PBL_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_3) +#define F_PERR_ENABLE_ARB_PBL_PF_3 V_PERR_ENABLE_ARB_PBL_PF_3(1U) + +#define S_PERR_ENABLE_ARB_PF_3 26 +#define V_PERR_ENABLE_ARB_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PF_3) +#define F_PERR_ENABLE_ARB_PF_3 V_PERR_ENABLE_ARB_PF_3(1U) + +#define S_PERR_ENABLE_ARB_TPT_PF_3 25 +#define V_PERR_ENABLE_ARB_TPT_PF_3(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_3) +#define F_PERR_ENABLE_ARB_TPT_PF_3 V_PERR_ENABLE_ARB_TPT_PF_3(1U) + +#define S_PERR_ENABLE_ARB_F_3 24 +#define V_PERR_ENABLE_ARB_F_3(x) ((x) << S_PERR_ENABLE_ARB_F_3) +#define F_PERR_ENABLE_ARB_F_3 V_PERR_ENABLE_ARB_F_3(1U) + +#define S_PERR_ENABLE_ARB_PBL_PF_2 19 +#define V_PERR_ENABLE_ARB_PBL_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_2) +#define F_PERR_ENABLE_ARB_PBL_PF_2 V_PERR_ENABLE_ARB_PBL_PF_2(1U) + +#define S_PERR_ENABLE_ARB_PF_2 18 +#define V_PERR_ENABLE_ARB_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PF_2) +#define F_PERR_ENABLE_ARB_PF_2 V_PERR_ENABLE_ARB_PF_2(1U) + +#define S_PERR_ENABLE_ARB_TPT_PF_2 17 +#define V_PERR_ENABLE_ARB_TPT_PF_2(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_2) +#define F_PERR_ENABLE_ARB_TPT_PF_2 V_PERR_ENABLE_ARB_TPT_PF_2(1U) + +#define S_PERR_ENABLE_ARB_F_2 16 +#define V_PERR_ENABLE_ARB_F_2(x) ((x) << S_PERR_ENABLE_ARB_F_2) +#define F_PERR_ENABLE_ARB_F_2 V_PERR_ENABLE_ARB_F_2(1U) + +#define S_PERR_ENABLE_ARB_PBL_PF_1 11 +#define V_PERR_ENABLE_ARB_PBL_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_1) +#define F_PERR_ENABLE_ARB_PBL_PF_1 V_PERR_ENABLE_ARB_PBL_PF_1(1U) + +#define S_PERR_ENABLE_ARB_PF_1 10 +#define V_PERR_ENABLE_ARB_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PF_1) +#define F_PERR_ENABLE_ARB_PF_1 V_PERR_ENABLE_ARB_PF_1(1U) + +#define S_PERR_ENABLE_ARB_TPT_PF_1 9 +#define V_PERR_ENABLE_ARB_TPT_PF_1(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_1) +#define F_PERR_ENABLE_ARB_TPT_PF_1 V_PERR_ENABLE_ARB_TPT_PF_1(1U) + +#define S_PERR_ENABLE_ARB_F_1 8 +#define V_PERR_ENABLE_ARB_F_1(x) ((x) << S_PERR_ENABLE_ARB_F_1) +#define F_PERR_ENABLE_ARB_F_1 V_PERR_ENABLE_ARB_F_1(1U) + +#define S_PERR_ENABLE_ARB_PBL_PF_0 3 +#define V_PERR_ENABLE_ARB_PBL_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_0) +#define F_PERR_ENABLE_ARB_PBL_PF_0 V_PERR_ENABLE_ARB_PBL_PF_0(1U) + +#define S_PERR_ENABLE_ARB_PF_0 2 +#define V_PERR_ENABLE_ARB_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PF_0) +#define F_PERR_ENABLE_ARB_PF_0 V_PERR_ENABLE_ARB_PF_0(1U) + +#define S_PERR_ENABLE_ARB_TPT_PF_0 1 +#define V_PERR_ENABLE_ARB_TPT_PF_0(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_0) +#define F_PERR_ENABLE_ARB_TPT_PF_0 V_PERR_ENABLE_ARB_TPT_PF_0(1U) + +#define S_PERR_ENABLE_ARB_F_0 0 +#define V_PERR_ENABLE_ARB_F_0(x) ((x) << S_PERR_ENABLE_ARB_F_0) +#define F_PERR_ENABLE_ARB_F_0 V_PERR_ENABLE_ARB_F_0(1U) + +#define A_ULP_RX_CTL1 0x19330 + +#define S_ISCSI_CTL2 27 +#define V_ISCSI_CTL2(x) ((x) << S_ISCSI_CTL2) +#define F_ISCSI_CTL2 V_ISCSI_CTL2(1U) + +#define S_ISCSI_CTL1 26 +#define V_ISCSI_CTL1(x) ((x) << S_ISCSI_CTL1) +#define F_ISCSI_CTL1 V_ISCSI_CTL1(1U) + +#define S_ISCSI_CTL0 25 +#define V_ISCSI_CTL0(x) ((x) << S_ISCSI_CTL0) +#define F_ISCSI_CTL0 V_ISCSI_CTL0(1U) + +#define S_NVME_TCP_DATA_ALIGNMENT 16 +#define M_NVME_TCP_DATA_ALIGNMENT 0x1ffU +#define V_NVME_TCP_DATA_ALIGNMENT(x) ((x) << S_NVME_TCP_DATA_ALIGNMENT) +#define G_NVME_TCP_DATA_ALIGNMENT(x) (((x) >> S_NVME_TCP_DATA_ALIGNMENT) & M_NVME_TCP_DATA_ALIGNMENT) + +#define S_NVME_TCP_INVLD_MSG_DIS 14 +#define M_NVME_TCP_INVLD_MSG_DIS 0x3U +#define V_NVME_TCP_INVLD_MSG_DIS(x) ((x) << S_NVME_TCP_INVLD_MSG_DIS) +#define G_NVME_TCP_INVLD_MSG_DIS(x) (((x) >> S_NVME_TCP_INVLD_MSG_DIS) & M_NVME_TCP_INVLD_MSG_DIS) + +#define S_NVME_TCP_DDP_PDU_CHK_TYPE 13 +#define V_NVME_TCP_DDP_PDU_CHK_TYPE(x) ((x) << S_NVME_TCP_DDP_PDU_CHK_TYPE) +#define F_NVME_TCP_DDP_PDU_CHK_TYPE V_NVME_TCP_DDP_PDU_CHK_TYPE(1U) + +#define S_T10_CONFIG_ENB 12 +#define V_T10_CONFIG_ENB(x) ((x) << S_T10_CONFIG_ENB) +#define F_T10_CONFIG_ENB V_T10_CONFIG_ENB(1U) + +#define S_NVME_TCP_COLOUR_ENB 10 +#define M_NVME_TCP_COLOUR_ENB 0x3U +#define V_NVME_TCP_COLOUR_ENB(x) ((x) << S_NVME_TCP_COLOUR_ENB) +#define G_NVME_TCP_COLOUR_ENB(x) (((x) >> S_NVME_TCP_COLOUR_ENB) & M_NVME_TCP_COLOUR_ENB) + +#define S_ROCE_SEND_RQE 8 +#define V_ROCE_SEND_RQE(x) ((x) << S_ROCE_SEND_RQE) +#define F_ROCE_SEND_RQE V_ROCE_SEND_RQE(1U) + +#define S_RDMA_INVLD_MSG_DIS 6 +#define M_RDMA_INVLD_MSG_DIS 0x3U +#define V_RDMA_INVLD_MSG_DIS(x) ((x) << S_RDMA_INVLD_MSG_DIS) +#define G_RDMA_INVLD_MSG_DIS(x) (((x) >> S_RDMA_INVLD_MSG_DIS) & M_RDMA_INVLD_MSG_DIS) + +#define S_ROCE_INVLD_MSG_DIS 4 +#define M_ROCE_INVLD_MSG_DIS 0x3U +#define V_ROCE_INVLD_MSG_DIS(x) ((x) << S_ROCE_INVLD_MSG_DIS) +#define G_ROCE_INVLD_MSG_DIS(x) (((x) >> S_ROCE_INVLD_MSG_DIS) & M_ROCE_INVLD_MSG_DIS) + +#define S_T7_MEM_ADDR_CTRL 2 +#define M_T7_MEM_ADDR_CTRL 0x3U +#define V_T7_MEM_ADDR_CTRL(x) ((x) << S_T7_MEM_ADDR_CTRL) +#define G_T7_MEM_ADDR_CTRL(x) (((x) >> S_T7_MEM_ADDR_CTRL) & M_T7_MEM_ADDR_CTRL) + +#define S_ENB_32K_PDU 1 +#define V_ENB_32K_PDU(x) ((x) << S_ENB_32K_PDU) +#define F_ENB_32K_PDU V_ENB_32K_PDU(1U) + +#define S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS 0 +#define V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(x) ((x) << S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS) +#define F_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(1U) + #define A_ULP_RX_TLS_IND_CMD 0x19348 #define S_TLS_RX_REG_OFF_ADDR 0 @@ -37795,6 +48839,8 @@ #define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR) #define A_ULP_RX_TLS_IND_DATA 0x1934c +#define A_ULP_RX_TLS_CH0_HMACCTRL_CFG 0x20 +#define A_ULP_RX_TLS_CH1_HMACCTRL_CFG 0x60 /* registers for module SF */ #define SF_BASE_ADDR 0x193f8 @@ -37815,6 +48861,39 @@ #define V_BYTECNT(x) ((x) << S_BYTECNT) #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) +#define S_EN32BADDR 30 +#define V_EN32BADDR(x) ((x) << S_EN32BADDR) +#define F_EN32BADDR V_EN32BADDR(1U) + +#define S_NUM_OF_BYTES 1 +#define M_NUM_OF_BYTES 0x3U +#define V_NUM_OF_BYTES(x) ((x) << S_NUM_OF_BYTES) +#define G_NUM_OF_BYTES(x) (((x) >> S_NUM_OF_BYTES) & M_NUM_OF_BYTES) + +#define S_QUADREADDISABLE 5 +#define V_QUADREADDISABLE(x) ((x) << S_QUADREADDISABLE) +#define F_QUADREADDISABLE V_QUADREADDISABLE(1U) + +#define S_EXIT4B 6 +#define V_EXIT4B(x) ((x) << S_EXIT4B) +#define F_EXIT4B V_EXIT4B(1U) + +#define S_ENTER4B 7 +#define V_ENTER4B(x) ((x) << S_ENTER4B) +#define F_ENTER4B V_ENTER4B(1U) + +#define S_QUADWRENABLE 8 +#define V_QUADWRENABLE(x) ((x) << S_QUADWRENABLE) +#define F_QUADWRENABLE V_QUADWRENABLE(1U) + +#define S_REGDBG_SEL 9 +#define V_REGDBG_SEL(x) ((x) << S_REGDBG_SEL) +#define F_REGDBG_SEL V_REGDBG_SEL(1U) + +#define S_REGDBG_MODE 10 +#define V_REGDBG_MODE(x) ((x) << S_REGDBG_MODE) +#define F_REGDBG_MODE V_REGDBG_MODE(1U) + /* registers for module PL */ #define PL_BASE_ADDR 0x19400 @@ -37892,21 +48971,6 @@ #define F_SWINT V_SWINT(1U) #define A_PL_WHOAMI 0x19400 - -#define S_T6_SOURCEPF 9 -#define M_T6_SOURCEPF 0x7U -#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF) -#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF) - -#define S_T6_ISVF 8 -#define V_T6_ISVF(x) ((x) << S_T6_ISVF) -#define F_T6_ISVF V_T6_ISVF(1U) - -#define S_T6_VFID 0 -#define M_T6_VFID 0xffU -#define V_T6_VFID(x) ((x) << S_T6_VFID) -#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID) - #define A_PL_PERR_CAUSE 0x19404 #define S_UART 28 @@ -38037,6 +49101,134 @@ #define V_ANYMAC(x) ((x) << S_ANYMAC) #define F_ANYMAC V_ANYMAC(1U) +#define S_T7_PL_PERR_CRYPTO_KEY 31 +#define V_T7_PL_PERR_CRYPTO_KEY(x) ((x) << S_T7_PL_PERR_CRYPTO_KEY) +#define F_T7_PL_PERR_CRYPTO_KEY V_T7_PL_PERR_CRYPTO_KEY(1U) + +#define S_T7_PL_PERR_CRYPTO1 30 +#define V_T7_PL_PERR_CRYPTO1(x) ((x) << S_T7_PL_PERR_CRYPTO1) +#define F_T7_PL_PERR_CRYPTO1 V_T7_PL_PERR_CRYPTO1(1U) + +#define S_T7_PL_PERR_CRYPTO0 29 +#define V_T7_PL_PERR_CRYPTO0(x) ((x) << S_T7_PL_PERR_CRYPTO0) +#define F_T7_PL_PERR_CRYPTO0 V_T7_PL_PERR_CRYPTO0(1U) + +#define S_T7_PL_PERR_GCACHE 28 +#define V_T7_PL_PERR_GCACHE(x) ((x) << S_T7_PL_PERR_GCACHE) +#define F_T7_PL_PERR_GCACHE V_T7_PL_PERR_GCACHE(1U) + +#define S_T7_PL_PERR_ARM 27 +#define V_T7_PL_PERR_ARM(x) ((x) << S_T7_PL_PERR_ARM) +#define F_T7_PL_PERR_ARM V_T7_PL_PERR_ARM(1U) + +#define S_T7_PL_PERR_ULP_TX 26 +#define V_T7_PL_PERR_ULP_TX(x) ((x) << S_T7_PL_PERR_ULP_TX) +#define F_T7_PL_PERR_ULP_TX V_T7_PL_PERR_ULP_TX(1U) + +#define S_T7_PL_PERR_SGE 25 +#define V_T7_PL_PERR_SGE(x) ((x) << S_T7_PL_PERR_SGE) +#define F_T7_PL_PERR_SGE V_T7_PL_PERR_SGE(1U) + +#define S_T7_PL_PERR_HMA 24 +#define V_T7_PL_PERR_HMA(x) ((x) << S_T7_PL_PERR_HMA) +#define F_T7_PL_PERR_HMA V_T7_PL_PERR_HMA(1U) + +#define S_T7_PL_PERR_CPL_SWITCH 23 +#define V_T7_PL_PERR_CPL_SWITCH(x) ((x) << S_T7_PL_PERR_CPL_SWITCH) +#define F_T7_PL_PERR_CPL_SWITCH V_T7_PL_PERR_CPL_SWITCH(1U) + +#define S_T7_PL_PERR_ULP_RX 22 +#define V_T7_PL_PERR_ULP_RX(x) ((x) << S_T7_PL_PERR_ULP_RX) +#define F_T7_PL_PERR_ULP_RX V_T7_PL_PERR_ULP_RX(1U) + +#define S_T7_PL_PERR_PM_RX 21 +#define V_T7_PL_PERR_PM_RX(x) ((x) << S_T7_PL_PERR_PM_RX) +#define F_T7_PL_PERR_PM_RX V_T7_PL_PERR_PM_RX(1U) + +#define S_T7_PL_PERR_PM_TX 20 +#define V_T7_PL_PERR_PM_TX(x) ((x) << S_T7_PL_PERR_PM_TX) +#define F_T7_PL_PERR_PM_TX V_T7_PL_PERR_PM_TX(1U) + +#define S_T7_PL_PERR_MA 19 +#define V_T7_PL_PERR_MA(x) ((x) << S_T7_PL_PERR_MA) +#define F_T7_PL_PERR_MA V_T7_PL_PERR_MA(1U) + +#define S_T7_PL_PERR_TP 18 +#define V_T7_PL_PERR_TP(x) ((x) << S_T7_PL_PERR_TP) +#define F_T7_PL_PERR_TP V_T7_PL_PERR_TP(1U) + +#define S_T7_PL_PERR_LE 17 +#define V_T7_PL_PERR_LE(x) ((x) << S_T7_PL_PERR_LE) +#define F_T7_PL_PERR_LE V_T7_PL_PERR_LE(1U) + +#define S_T7_PL_PERR_EDC1 16 +#define V_T7_PL_PERR_EDC1(x) ((x) << S_T7_PL_PERR_EDC1) +#define F_T7_PL_PERR_EDC1 V_T7_PL_PERR_EDC1(1U) + +#define S_T7_PL_PERR_EDC0 15 +#define V_T7_PL_PERR_EDC0(x) ((x) << S_T7_PL_PERR_EDC0) +#define F_T7_PL_PERR_EDC0 V_T7_PL_PERR_EDC0(1U) + +#define S_T7_PL_PERR_MC1 14 +#define V_T7_PL_PERR_MC1(x) ((x) << S_T7_PL_PERR_MC1) +#define F_T7_PL_PERR_MC1 V_T7_PL_PERR_MC1(1U) + +#define S_T7_PL_PERR_MC0 13 +#define V_T7_PL_PERR_MC0(x) ((x) << S_T7_PL_PERR_MC0) +#define F_T7_PL_PERR_MC0 V_T7_PL_PERR_MC0(1U) + +#define S_T7_PL_PERR_PCIE 12 +#define V_T7_PL_PERR_PCIE(x) ((x) << S_T7_PL_PERR_PCIE) +#define F_T7_PL_PERR_PCIE V_T7_PL_PERR_PCIE(1U) + +#define S_T7_PL_PERR_UART 11 +#define V_T7_PL_PERR_UART(x) ((x) << S_T7_PL_PERR_UART) +#define F_T7_PL_PERR_UART V_T7_PL_PERR_UART(1U) + +#define S_T7_PL_PERR_PMU 10 +#define V_T7_PL_PERR_PMU(x) ((x) << S_T7_PL_PERR_PMU) +#define F_T7_PL_PERR_PMU V_T7_PL_PERR_PMU(1U) + +#define S_T7_PL_PERR_MAC 9 +#define V_T7_PL_PERR_MAC(x) ((x) << S_T7_PL_PERR_MAC) +#define F_T7_PL_PERR_MAC V_T7_PL_PERR_MAC(1U) + +#define S_T7_PL_PERR_SMB 8 +#define V_T7_PL_PERR_SMB(x) ((x) << S_T7_PL_PERR_SMB) +#define F_T7_PL_PERR_SMB V_T7_PL_PERR_SMB(1U) + +#define S_T7_PL_PERR_SF 7 +#define V_T7_PL_PERR_SF(x) ((x) << S_T7_PL_PERR_SF) +#define F_T7_PL_PERR_SF V_T7_PL_PERR_SF(1U) + +#define S_T7_PL_PERR_PL 6 +#define V_T7_PL_PERR_PL(x) ((x) << S_T7_PL_PERR_PL) +#define F_T7_PL_PERR_PL V_T7_PL_PERR_PL(1U) + +#define S_T7_PL_PERR_NCSI 5 +#define V_T7_PL_PERR_NCSI(x) ((x) << S_T7_PL_PERR_NCSI) +#define F_T7_PL_PERR_NCSI V_T7_PL_PERR_NCSI(1U) + +#define S_T7_PL_PERR_MPS 4 +#define V_T7_PL_PERR_MPS(x) ((x) << S_T7_PL_PERR_MPS) +#define F_T7_PL_PERR_MPS V_T7_PL_PERR_MPS(1U) + +#define S_T7_PL_PERR_MI 3 +#define V_T7_PL_PERR_MI(x) ((x) << S_T7_PL_PERR_MI) +#define F_T7_PL_PERR_MI V_T7_PL_PERR_MI(1U) + +#define S_T7_PL_PERR_DBG 2 +#define V_T7_PL_PERR_DBG(x) ((x) << S_T7_PL_PERR_DBG) +#define F_T7_PL_PERR_DBG V_T7_PL_PERR_DBG(1U) + +#define S_T7_PL_PERR_I2CM 1 +#define V_T7_PL_PERR_I2CM(x) ((x) << S_T7_PL_PERR_I2CM) +#define F_T7_PL_PERR_I2CM V_T7_PL_PERR_I2CM(1U) + +#define S_T7_PL_PERR_CIM 0 +#define V_T7_PL_PERR_CIM(x) ((x) << S_T7_PL_PERR_CIM) +#define F_T7_PL_PERR_CIM V_T7_PL_PERR_CIM(1U) + #define A_PL_PERR_ENABLE 0x19408 #define A_PL_INT_CAUSE 0x1940c @@ -38064,6 +49256,78 @@ #define V_MAC0(x) ((x) << S_MAC0) #define F_MAC0 V_MAC0(1U) +#define S_T7_FLR 31 +#define V_T7_FLR(x) ((x) << S_T7_FLR) +#define F_T7_FLR V_T7_FLR(1U) + +#define S_T7_SW_CIM 30 +#define V_T7_SW_CIM(x) ((x) << S_T7_SW_CIM) +#define F_T7_SW_CIM V_T7_SW_CIM(1U) + +#define S_T7_ULP_TX 29 +#define V_T7_ULP_TX(x) ((x) << S_T7_ULP_TX) +#define F_T7_ULP_TX V_T7_ULP_TX(1U) + +#define S_T7_SGE 28 +#define V_T7_SGE(x) ((x) << S_T7_SGE) +#define F_T7_SGE V_T7_SGE(1U) + +#define S_T7_HMA 27 +#define V_T7_HMA(x) ((x) << S_T7_HMA) +#define F_T7_HMA V_T7_HMA(1U) + +#define S_T7_CPL_SWITCH 26 +#define V_T7_CPL_SWITCH(x) ((x) << S_T7_CPL_SWITCH) +#define F_T7_CPL_SWITCH V_T7_CPL_SWITCH(1U) + +#define S_T7_ULP_RX 25 +#define V_T7_ULP_RX(x) ((x) << S_T7_ULP_RX) +#define F_T7_ULP_RX V_T7_ULP_RX(1U) + +#define S_T7_PM_RX 24 +#define V_T7_PM_RX(x) ((x) << S_T7_PM_RX) +#define F_T7_PM_RX V_T7_PM_RX(1U) + +#define S_T7_PM_TX 23 +#define V_T7_PM_TX(x) ((x) << S_T7_PM_TX) +#define F_T7_PM_TX V_T7_PM_TX(1U) + +#define S_T7_MA 22 +#define V_T7_MA(x) ((x) << S_T7_MA) +#define F_T7_MA V_T7_MA(1U) + +#define S_T7_TP 21 +#define V_T7_TP(x) ((x) << S_T7_TP) +#define F_T7_TP V_T7_TP(1U) + +#define S_T7_LE 20 +#define V_T7_LE(x) ((x) << S_T7_LE) +#define F_T7_LE V_T7_LE(1U) + +#define S_T7_EDC1 19 +#define V_T7_EDC1(x) ((x) << S_T7_EDC1) +#define F_T7_EDC1 V_T7_EDC1(1U) + +#define S_T7_EDC0 18 +#define V_T7_EDC0(x) ((x) << S_T7_EDC0) +#define F_T7_EDC0 V_T7_EDC0(1U) + +#define S_T7_MC1 17 +#define V_T7_MC1(x) ((x) << S_T7_MC1) +#define F_T7_MC1 V_T7_MC1(1U) + +#define S_T7_MC0 16 +#define V_T7_MC0(x) ((x) << S_T7_MC0) +#define F_T7_MC0 V_T7_MC0(1U) + +#define S_T7_PCIE 15 +#define V_T7_PCIE(x) ((x) << S_T7_PCIE) +#define F_T7_PCIE V_T7_PCIE(1U) + +#define S_T7_UART 14 +#define V_T7_UART(x) ((x) << S_T7_UART) +#define F_T7_UART V_T7_UART(1U) + #define A_PL_INT_ENABLE 0x19410 #define A_PL_INT_MAP0 0x19414 @@ -38262,15 +49526,10 @@ #define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD) #define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD) -#define S_T6_STATECFGINITF 16 -#define M_T6_STATECFGINITF 0xffU -#define V_T6_STATECFGINITF(x) ((x) << S_T6_STATECFGINITF) -#define G_T6_STATECFGINITF(x) (((x) >> S_T6_STATECFGINITF) & M_T6_STATECFGINITF) - -#define S_T6_STATECFGINIT 12 -#define M_T6_STATECFGINIT 0xfU -#define V_T6_STATECFGINIT(x) ((x) << S_T6_STATECFGINIT) -#define G_T6_STATECFGINIT(x) (((x) >> S_T6_STATECFGINIT) & M_T6_STATECFGINIT) +#define S_T6_1_STATECFGINITF 16 +#define M_T6_1_STATECFGINITF 0xffU +#define V_T6_1_STATECFGINITF(x) ((x) << S_T6_1_STATECFGINITF) +#define G_T6_1_STATECFGINITF(x) (((x) >> S_T6_1_STATECFGINITF) & M_T6_1_STATECFGINITF) #define S_PHY_STATUS 10 #define V_PHY_STATUS(x) ((x) << S_PHY_STATUS) @@ -38285,9 +49544,9 @@ #define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL) #define F_PERSTTIMEOUT_PL V_PERSTTIMEOUT_PL(1U) -#define S_T6_LTSSMENABLE 6 -#define V_T6_LTSSMENABLE(x) ((x) << S_T6_LTSSMENABLE) -#define F_T6_LTSSMENABLE V_T6_LTSSMENABLE(1U) +#define S_SPEEDMS 30 +#define V_SPEEDMS(x) ((x) << S_SPEEDMS) +#define F_SPEEDMS V_SPEEDMS(1U) #define A_PL_PCIE_CTL_STAT 0x19444 @@ -38382,6 +49641,37 @@ #define V_MAP0(x) ((x) << S_MAP0) #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0) +#define A_PL_INT_CAUSE2 0x19478 + +#define S_CRYPTO_KEY 4 +#define V_CRYPTO_KEY(x) ((x) << S_CRYPTO_KEY) +#define F_CRYPTO_KEY V_CRYPTO_KEY(1U) + +#define S_CRYPTO1 3 +#define V_CRYPTO1(x) ((x) << S_CRYPTO1) +#define F_CRYPTO1 V_CRYPTO1(1U) + +#define S_CRYPTO0 2 +#define V_CRYPTO0(x) ((x) << S_CRYPTO0) +#define F_CRYPTO0 V_CRYPTO0(1U) + +#define S_GCACHE 1 +#define V_GCACHE(x) ((x) << S_GCACHE) +#define F_GCACHE V_GCACHE(1U) + +#define S_ARM 0 +#define V_ARM(x) ((x) << S_ARM) +#define F_ARM V_ARM(1U) + +#define A_PL_INT_ENABLE2 0x1947c +#define A_PL_ER_CMD 0x19488 + +#define S_ER_ADDR 2 +#define M_ER_ADDR 0x3fffffffU +#define V_ER_ADDR(x) ((x) << S_ER_ADDR) +#define G_ER_ADDR(x) (((x) >> S_ER_ADDR) & M_ER_ADDR) + +#define A_PL_ER_DATA 0x1948c #define A_PL_VF_SLICE_L 0x19490 #define S_LIMITADDR 16 @@ -38638,6 +49928,10 @@ #define V_REGION_EN(x) ((x) << S_REGION_EN) #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN) +#define S_CACHEBYPASS 28 +#define V_CACHEBYPASS(x) ((x) << S_CACHEBYPASS) +#define F_CACHEBYPASS V_CACHEBYPASS(1U) + #define A_LE_MISC 0x19c08 #define S_CMPUNVAIL 0 @@ -38830,6 +50124,10 @@ #define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE) #define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE) +#define S_MLL_MASK 2 +#define V_MLL_MASK(x) ((x) << S_MLL_MASK) +#define F_MLL_MASK V_MLL_MASK(1U) + #define A_LE_DB_INT_ENABLE 0x19c38 #define S_MSGSEL 27 @@ -39045,40 +50343,15 @@ #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR) #define F_PIPELINEERR V_PIPELINEERR(1U) -#define A_LE_DB_INT_CAUSE 0x19c3c - -#define S_T6_ACTRGNFULL 21 -#define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL) -#define F_T6_ACTRGNFULL V_T6_ACTRGNFULL(1U) +#define S_CACHEINTPERR 31 +#define V_CACHEINTPERR(x) ((x) << S_CACHEINTPERR) +#define F_CACHEINTPERR V_CACHEINTPERR(1U) -#define S_T6_ACTCNTIPV6TZERO 20 -#define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO) -#define F_T6_ACTCNTIPV6TZERO V_T6_ACTCNTIPV6TZERO(1U) - -#define S_T6_ACTCNTIPV4TZERO 19 -#define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO) -#define F_T6_ACTCNTIPV4TZERO V_T6_ACTCNTIPV4TZERO(1U) - -#define S_T6_ACTCNTIPV6ZERO 18 -#define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO) -#define F_T6_ACTCNTIPV6ZERO V_T6_ACTCNTIPV6ZERO(1U) - -#define S_T6_ACTCNTIPV4ZERO 17 -#define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO) -#define F_T6_ACTCNTIPV4ZERO V_T6_ACTCNTIPV4ZERO(1U) - -#define S_T6_UNKNOWNCMD 3 -#define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD) -#define F_T6_UNKNOWNCMD V_T6_UNKNOWNCMD(1U) - -#define S_T6_LIP0 2 -#define V_T6_LIP0(x) ((x) << S_T6_LIP0) -#define F_T6_LIP0 V_T6_LIP0(1U) - -#define S_T6_LIPMISS 1 -#define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS) -#define F_T6_LIPMISS V_T6_LIPMISS(1U) +#define S_CACHESRAMPERR 30 +#define V_CACHESRAMPERR(x) ((x) << S_CACHESRAMPERR) +#define F_CACHESRAMPERR V_CACHESRAMPERR(1U) +#define A_LE_DB_INT_CAUSE 0x19c3c #define A_LE_DB_INT_TID 0x19c40 #define S_INTTID 0 @@ -39287,6 +50560,14 @@ #define A_LE_DB_MASK_IPV6 0x19ca0 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0 +#define A_LE_CMM_CONFIG 0x19cc0 +#define A_LE_CACHE_DBG 0x19cc4 +#define A_LE_CACHE_WR_ALL_CNT 0x19cc8 +#define A_LE_CACHE_WR_HIT_CNT 0x19ccc +#define A_LE_CACHE_RD_ALL_CNT 0x19cd0 +#define A_LE_CACHE_RD_HIT_CNT 0x19cd4 +#define A_LE_CACHE_MC_WR_CNT 0x19cd8 +#define A_LE_CACHE_MC_RD_CNT 0x19cdc #define A_LE_DB_REQ_RSP_CNT 0x19ce4 #define S_T4_RSPCNT 16 @@ -39309,6 +50590,14 @@ #define V_REQCNTLE(x) ((x) << S_REQCNTLE) #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE) +#define A_LE_IND_ADDR 0x19ce8 + +#define S_T7_1_ADDR 0 +#define M_T7_1_ADDR 0xffU +#define V_T7_1_ADDR(x) ((x) << S_T7_1_ADDR) +#define G_T7_1_ADDR(x) (((x) >> S_T7_1_ADDR) & M_T7_1_ADDR) + +#define A_LE_IND_DATA 0x19cec #define A_LE_DB_DBGI_CONFIG 0x19cf0 #define S_DBGICMDPERR 31 @@ -39436,6 +50725,11 @@ #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR) #define F_T6_HASHTBLMEMCRCERR V_T6_HASHTBLMEMCRCERR(1U) +#define S_T7_BKCHKPERIOD 22 +#define M_T7_BKCHKPERIOD 0xffU +#define V_T7_BKCHKPERIOD(x) ((x) << S_T7_BKCHKPERIOD) +#define G_T7_BKCHKPERIOD(x) (((x) >> S_T7_BKCHKPERIOD) & M_T7_BKCHKPERIOD) + #define A_LE_SPARE 0x19cfc #define A_LE_DB_DBGI_REQ_DATA 0x19d00 #define A_LE_DB_DBGI_REQ_MASK 0x19d50 @@ -39551,6 +50845,7 @@ #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE) #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE) +#define A_T7_LE_DB_HASH_TID_BASE 0x19df8 #define A_LE_PERR_INJECT 0x19dfc #define S_LEMEMSEL 1 @@ -39573,6 +50868,7 @@ #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4 +#define A_T7_LE_HASH_MASK_GEN_IPV6T5 0x19ec4 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4 @@ -39677,6 +50973,9 @@ #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4 +#define A_LE_TCAM_BIST_CTRL 0x19fb0 +#define A_LE_TCAM_BIST_CB_PASS 0x19fb4 +#define A_LE_TCAM_BIST_CB_BUSY 0x19fbc #define A_LE_HASH_COLLISION 0x19fc4 #define A_LE_GLOBAL_COLLISION 0x19fc8 #define A_LE_FULL_CNT_COLLISION 0x19fcc @@ -39686,6 +50985,38 @@ #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4 +#define A_LE_TCAM_NEG_CTRL0 0x0 +#define A_LE_TCAM_NEG_CTRL1 0x1 +#define A_LE_TCAM_NEG_CTRL2 0x2 +#define A_LE_TCAM_NEG_CTRL3 0x3 +#define A_LE_TCAM_NEG_CTRL4 0x4 +#define A_LE_TCAM_NEG_CTRL5 0x5 +#define A_LE_TCAM_NEG_CTRL6 0x6 +#define A_LE_TCAM_NEG_CTRL7 0x7 +#define A_LE_TCAM_NEG_CTRL8 0x8 +#define A_LE_TCAM_NEG_CTRL9 0x9 +#define A_LE_TCAM_NEG_CTRL10 0xa +#define A_LE_TCAM_NEG_CTRL11 0xb +#define A_LE_TCAM_NEG_CTRL12 0xc +#define A_LE_TCAM_NEG_CTRL13 0xd +#define A_LE_TCAM_NEG_CTRL14 0xe +#define A_LE_TCAM_NEG_CTRL15 0xf +#define A_LE_TCAM_NEG_CTRL16 0x10 +#define A_LE_TCAM_NEG_CTRL17 0x11 +#define A_LE_TCAM_NEG_CTRL18 0x12 +#define A_LE_TCAM_NEG_CTRL19 0x13 +#define A_LE_TCAM_NEG_CTRL20 0x14 +#define A_LE_TCAM_NEG_CTRL21 0x15 +#define A_LE_TCAM_NEG_CTRL22 0x16 +#define A_LE_TCAM_NEG_CTRL23 0x17 +#define A_LE_TCAM_NEG_CTRL24 0x18 +#define A_LE_TCAM_NEG_CTRL25 0x19 +#define A_LE_TCAM_NEG_CTRL26 0x1a +#define A_LE_TCAM_NEG_CTRL27 0x1b +#define A_LE_TCAM_NEG_CTRL28 0x1c +#define A_LE_TCAM_NEG_CTRL29 0x1d +#define A_LE_TCAM_NEG_CTRL30 0x1e +#define A_LE_TCAM_NEG_CTRL31 0x1f /* registers for module NCSI */ #define NCSI_BASE_ADDR 0x1a000 @@ -39735,6 +51066,10 @@ #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP) #define F_TX_BYTE_SWAP V_TX_BYTE_SWAP(1U) +#define S_XGMAC0_EN 0 +#define V_XGMAC0_EN(x) ((x) << S_XGMAC0_EN) +#define F_XGMAC0_EN V_XGMAC0_EN(1U) + #define A_NCSI_RST_CTRL 0x1a004 #define S_MAC_REF_RST 2 @@ -39991,6 +51326,10 @@ #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) #define F_RXFIFO_PRTY_ERR V_RXFIFO_PRTY_ERR(1U) +#define S_CIM2NC_PERR 9 +#define V_CIM2NC_PERR(x) ((x) << S_CIM2NC_PERR) +#define F_CIM2NC_PERR V_CIM2NC_PERR(1U) + #define A_NCSI_INT_CAUSE 0x1a0d8 #define A_NCSI_STATUS 0x1a0dc @@ -40048,6 +51387,12 @@ #define F_MCSIMELSEL V_MCSIMELSEL(1U) #define A_NCSI_PERR_ENABLE 0x1a0f8 +#define A_NCSI_MODE_SEL 0x1a0fc + +#define S_XGMAC_MODE 0 +#define V_XGMAC_MODE(x) ((x) << S_XGMAC_MODE) +#define F_XGMAC_MODE V_XGMAC_MODE(1U) + #define A_NCSI_MACB_NETWORK_CTRL 0x1a100 #define S_TXSNDZEROPAUSE 12 @@ -40550,6 +51895,832 @@ #define V_DESREV(x) ((x) << S_DESREV) #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV) +#define A_NCSI_TX_CTRL 0x1a200 + +#define S_T7_TXEN 0 +#define V_T7_TXEN(x) ((x) << S_T7_TXEN) +#define F_T7_TXEN V_T7_TXEN(1U) + +#define A_NCSI_TX_CFG 0x1a204 +#define A_NCSI_TX_PAUSE_QUANTA 0x1a208 +#define A_NCSI_RX_CTRL 0x1a20c +#define A_NCSI_RX_CFG 0x1a210 +#define A_NCSI_RX_HASH_LOW 0x1a214 +#define A_NCSI_RX_HASH_HIGH 0x1a218 +#define A_NCSI_RX_EXACT_MATCH_LOW_1 0x1a21c +#define A_NCSI_RX_EXACT_MATCH_HIGH_1 0x1a220 +#define A_NCSI_RX_EXACT_MATCH_LOW_2 0x1a224 +#define A_NCSI_RX_EXACT_MATCH_HIGH_2 0x1a228 +#define A_NCSI_RX_EXACT_MATCH_LOW_3 0x1a22c +#define A_NCSI_RX_EXACT_MATCH_HIGH_3 0x1a230 +#define A_NCSI_RX_EXACT_MATCH_LOW_4 0x1a234 +#define A_NCSI_RX_EXACT_MATCH_HIGH_4 0x1a238 +#define A_NCSI_RX_EXACT_MATCH_LOW_5 0x1a23c +#define A_NCSI_RX_EXACT_MATCH_HIGH_5 0x1a240 +#define A_NCSI_RX_EXACT_MATCH_LOW_6 0x1a244 +#define A_NCSI_RX_EXACT_MATCH_HIGH_6 0x1a248 +#define A_NCSI_RX_EXACT_MATCH_LOW_7 0x1a24c +#define A_NCSI_RX_EXACT_MATCH_HIGH_7 0x1a250 +#define A_NCSI_RX_EXACT_MATCH_LOW_8 0x1a254 +#define A_NCSI_RX_EXACT_MATCH_HIGH_8 0x1a258 +#define A_NCSI_RX_TYPE_MATCH_1 0x1a25c +#define A_NCSI_RX_TYPE_MATCH_2 0x1a260 +#define A_NCSI_RX_TYPE_MATCH_3 0x1a264 +#define A_NCSI_RX_TYPE_MATCH_4 0x1a268 +#define A_NCSI_INT_STATUS 0x1a26c +#define A_NCSI_XGM_INT_MASK 0x1a270 +#define A_NCSI_XGM_INT_ENABLE 0x1a274 +#define A_NCSI_XGM_INT_DISABLE 0x1a278 +#define A_NCSI_TX_PAUSE_TIMER 0x1a27c +#define A_NCSI_STAT_CTRL 0x1a280 +#define A_NCSI_RXFIFO_CFG 0x1a284 + +#define S_RXFIFO_EMPTY 31 +#define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY) +#define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U) + +#define S_RXFIFO_FULL 30 +#define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL) +#define F_RXFIFO_FULL V_RXFIFO_FULL(1U) + +#define S_RXFIFOPAUSEHWM 17 +#define M_RXFIFOPAUSEHWM 0xfffU +#define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) +#define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) + +#define S_RXFIFOPAUSELWM 5 +#define M_RXFIFOPAUSELWM 0xfffU +#define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) +#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) + +#define S_FORCEDPAUSE 4 +#define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE) +#define F_FORCEDPAUSE V_FORCEDPAUSE(1U) + +#define S_EXTERNLOOPBACK 3 +#define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK) +#define F_EXTERNLOOPBACK V_EXTERNLOOPBACK(1U) + +#define S_RXBYTESWAP 2 +#define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP) +#define F_RXBYTESWAP V_RXBYTESWAP(1U) + +#define S_RXSTRFRWRD 1 +#define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD) +#define F_RXSTRFRWRD V_RXSTRFRWRD(1U) + +#define S_DISERRFRAMES 0 +#define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) +#define F_DISERRFRAMES V_DISERRFRAMES(1U) + +#define A_NCSI_TXFIFO_CFG 0x1a288 + +#define S_T7_TXFIFO_EMPTY 31 +#define V_T7_TXFIFO_EMPTY(x) ((x) << S_T7_TXFIFO_EMPTY) +#define F_T7_TXFIFO_EMPTY V_T7_TXFIFO_EMPTY(1U) + +#define S_T7_TXFIFO_FULL 30 +#define V_T7_TXFIFO_FULL(x) ((x) << S_T7_TXFIFO_FULL) +#define F_T7_TXFIFO_FULL V_T7_TXFIFO_FULL(1U) + +#define S_UNDERUNFIX 22 +#define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX) +#define F_UNDERUNFIX V_UNDERUNFIX(1U) + +#define S_ENDROPPKT 21 +#define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) +#define F_ENDROPPKT V_ENDROPPKT(1U) + +#define S_TXIPG 13 +#define M_TXIPG 0xffU +#define V_TXIPG(x) ((x) << S_TXIPG) +#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) + +#define S_TXFIFOTHRESH 4 +#define M_TXFIFOTHRESH 0x1ffU +#define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) +#define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH) + +#define S_INTERNLOOPBACK 3 +#define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK) +#define F_INTERNLOOPBACK V_INTERNLOOPBACK(1U) + +#define S_TXBYTESWAP 2 +#define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP) +#define F_TXBYTESWAP V_TXBYTESWAP(1U) + +#define S_DISCRC 1 +#define V_DISCRC(x) ((x) << S_DISCRC) +#define F_DISCRC V_DISCRC(1U) + +#define S_DISPREAMBLE 0 +#define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE) +#define F_DISPREAMBLE V_DISPREAMBLE(1U) + +#define A_NCSI_SLOW_TIMER 0x1a28c + +#define S_PAUSESLOWTIMEREN 31 +#define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN) +#define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U) + +#define S_PAUSESLOWTIMER 0 +#define M_PAUSESLOWTIMER 0xfffffU +#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) +#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) + +#define A_NCSI_PAUSE_TIMER 0x1a290 + +#define S_PAUSETIMER 0 +#define M_PAUSETIMER 0xfffffU +#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) +#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) + +#define A_NCSI_XAUI_PCS_TEST 0x1a294 + +#define S_TESTPATTERN 1 +#define M_TESTPATTERN 0x3U +#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) +#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) + +#define S_ENTEST 0 +#define V_ENTEST(x) ((x) << S_ENTEST) +#define F_ENTEST V_ENTEST(1U) + +#define A_NCSI_RGMII_CTRL 0x1a298 + +#define S_PHALIGNFIFOTHRESH 1 +#define M_PHALIGNFIFOTHRESH 0x3U +#define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH) +#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) + +#define S_TXCLK90SHIFT 0 +#define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT) +#define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U) + +#define A_NCSI_RGMII_IMP 0x1a29c + +#define S_CALRESET 8 +#define V_CALRESET(x) ((x) << S_CALRESET) +#define F_CALRESET V_CALRESET(1U) + +#define S_CALUPDATE 7 +#define V_CALUPDATE(x) ((x) << S_CALUPDATE) +#define F_CALUPDATE V_CALUPDATE(1U) + +#define S_IMPSETUPDATE 6 +#define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE) +#define F_IMPSETUPDATE V_IMPSETUPDATE(1U) + +#define S_RGMIIIMPPD 3 +#define M_RGMIIIMPPD 0x7U +#define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) +#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) + +#define S_RGMIIIMPPU 0 +#define M_RGMIIIMPPU 0x7U +#define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) +#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) + +#define A_NCSI_RX_MAX_PKT_SIZE 0x1a2a8 + +#define S_RXMAXFRAMERSIZE 17 +#define M_RXMAXFRAMERSIZE 0x3fffU +#define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE) +#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) + +#define S_RXENERRORGATHER 16 +#define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER) +#define F_RXENERRORGATHER V_RXENERRORGATHER(1U) + +#define S_RXENSINGLEFLIT 15 +#define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT) +#define F_RXENSINGLEFLIT V_RXENSINGLEFLIT(1U) + +#define S_RXENFRAMER 14 +#define V_RXENFRAMER(x) ((x) << S_RXENFRAMER) +#define F_RXENFRAMER V_RXENFRAMER(1U) + +#define S_RXMAXPKTSIZE 0 +#define M_RXMAXPKTSIZE 0x3fffU +#define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) +#define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) + +#define A_NCSI_RESET_CTRL 0x1a2ac + +#define S_XGMAC_STOP_EN 4 +#define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN) +#define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U) + +#define S_XG2G_RESET_ 3 +#define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) +#define F_XG2G_RESET_ V_XG2G_RESET_(1U) + +#define S_RGMII_RESET_ 2 +#define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) +#define F_RGMII_RESET_ V_RGMII_RESET_(1U) + +#define S_PCS_RESET_ 1 +#define V_PCS_RESET_(x) ((x) << S_PCS_RESET_) +#define F_PCS_RESET_ V_PCS_RESET_(1U) + +#define S_MAC_RESET_ 0 +#define V_MAC_RESET_(x) ((x) << S_MAC_RESET_) +#define F_MAC_RESET_ V_MAC_RESET_(1U) + +#define A_NCSI_XAUI1G_CTRL 0x1a2b0 + +#define S_XAUI1GLINKID 0 +#define M_XAUI1GLINKID 0x3U +#define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID) +#define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID) + +#define A_NCSI_SERDES_LANE_CTRL 0x1a2b4 + +#define S_LANEREVERSAL 8 +#define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL) +#define F_LANEREVERSAL V_LANEREVERSAL(1U) + +#define S_TXPOLARITY 4 +#define M_TXPOLARITY 0xfU +#define V_TXPOLARITY(x) ((x) << S_TXPOLARITY) +#define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY) + +#define S_RXPOLARITY 0 +#define M_RXPOLARITY 0xfU +#define V_RXPOLARITY(x) ((x) << S_RXPOLARITY) +#define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY) + +#define A_NCSI_PORT_CFG 0x1a2b8 + +#define S_NCSI_SAFESPEEDCHANGE 4 +#define V_NCSI_SAFESPEEDCHANGE(x) ((x) << S_NCSI_SAFESPEEDCHANGE) +#define F_NCSI_SAFESPEEDCHANGE V_NCSI_SAFESPEEDCHANGE(1U) + +#define S_NCSI_CLKDIVRESET_ 3 +#define V_NCSI_CLKDIVRESET_(x) ((x) << S_NCSI_CLKDIVRESET_) +#define F_NCSI_CLKDIVRESET_ V_NCSI_CLKDIVRESET_(1U) + +#define S_NCSI_PORTSPEED 1 +#define M_NCSI_PORTSPEED 0x3U +#define V_NCSI_PORTSPEED(x) ((x) << S_NCSI_PORTSPEED) +#define G_NCSI_PORTSPEED(x) (((x) >> S_NCSI_PORTSPEED) & M_NCSI_PORTSPEED) + +#define S_NCSI_ENRGMII 0 +#define V_NCSI_ENRGMII(x) ((x) << S_NCSI_ENRGMII) +#define F_NCSI_ENRGMII V_NCSI_ENRGMII(1U) + +#define A_NCSI_EPIO_DATA0 0x1a2c0 +#define A_NCSI_EPIO_DATA1 0x1a2c4 +#define A_NCSI_EPIO_DATA2 0x1a2c8 +#define A_NCSI_EPIO_DATA3 0x1a2cc +#define A_NCSI_EPIO_OP 0x1a2d0 + +#define S_PIO_READY 31 +#define V_PIO_READY(x) ((x) << S_PIO_READY) +#define F_PIO_READY V_PIO_READY(1U) + +#define S_PIO_WRRD 24 +#define V_PIO_WRRD(x) ((x) << S_PIO_WRRD) +#define F_PIO_WRRD V_PIO_WRRD(1U) + +#define S_PIO_ADDRESS 0 +#define M_PIO_ADDRESS 0xffU +#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) +#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) + +#define A_NCSI_XGMAC0_INT_ENABLE 0x1a2d4 + +#define S_XAUIPCSDECERR 24 +#define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR) +#define F_XAUIPCSDECERR V_XAUIPCSDECERR(1U) + +#define S_RGMIIRXFIFOOVERFLOW 23 +#define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW) +#define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U) + +#define S_RGMIIRXFIFOUNDERFLOW 22 +#define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW) +#define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U) + +#define S_RXPKTSIZEERROR 21 +#define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR) +#define F_RXPKTSIZEERROR V_RXPKTSIZEERROR(1U) + +#define S_WOLPATDETECTED 20 +#define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED) +#define F_WOLPATDETECTED V_WOLPATDETECTED(1U) + +#define S_T7_TXFIFO_PRTY_ERR 17 +#define M_T7_TXFIFO_PRTY_ERR 0x7U +#define V_T7_TXFIFO_PRTY_ERR(x) ((x) << S_T7_TXFIFO_PRTY_ERR) +#define G_T7_TXFIFO_PRTY_ERR(x) (((x) >> S_T7_TXFIFO_PRTY_ERR) & M_T7_TXFIFO_PRTY_ERR) + +#define S_T7_RXFIFO_PRTY_ERR 14 +#define M_T7_RXFIFO_PRTY_ERR 0x7U +#define V_T7_RXFIFO_PRTY_ERR(x) ((x) << S_T7_RXFIFO_PRTY_ERR) +#define G_T7_RXFIFO_PRTY_ERR(x) (((x) >> S_T7_RXFIFO_PRTY_ERR) & M_T7_RXFIFO_PRTY_ERR) + +#define S_TXFIFO_UNDERRUN 13 +#define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) +#define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) + +#define S_RXFIFO_OVERFLOW 12 +#define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) +#define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) + +#define S_SERDESBISTERR 8 +#define M_SERDESBISTERR 0xfU +#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) +#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) + +#define S_SERDESLOWSIGCHANGE 4 +#define M_SERDESLOWSIGCHANGE 0xfU +#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) +#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) + +#define S_XAUIPCSCTCERR 3 +#define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) +#define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) + +#define S_XAUIPCSALIGNCHANGE 2 +#define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) +#define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) + +#define S_RGMIILINKSTSCHANGE 1 +#define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE) +#define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U) + +#define S_T7_XGM_INT 0 +#define V_T7_XGM_INT(x) ((x) << S_T7_XGM_INT) +#define F_T7_XGM_INT V_T7_XGM_INT(1U) + +#define A_NCSI_XGMAC0_INT_CAUSE 0x1a2d8 +#define A_NCSI_XAUI_ACT_CTRL 0x1a2dc +#define A_NCSI_SERDES_CTRL0 0x1a2e0 + +#define S_INTSERLPBK3 27 +#define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3) +#define F_INTSERLPBK3 V_INTSERLPBK3(1U) + +#define S_INTSERLPBK2 26 +#define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2) +#define F_INTSERLPBK2 V_INTSERLPBK2(1U) + +#define S_INTSERLPBK1 25 +#define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1) +#define F_INTSERLPBK1 V_INTSERLPBK1(1U) + +#define S_INTSERLPBK0 24 +#define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0) +#define F_INTSERLPBK0 V_INTSERLPBK0(1U) + +#define S_RESET3 23 +#define V_RESET3(x) ((x) << S_RESET3) +#define F_RESET3 V_RESET3(1U) + +#define S_RESET2 22 +#define V_RESET2(x) ((x) << S_RESET2) +#define F_RESET2 V_RESET2(1U) + +#define S_RESET1 21 +#define V_RESET1(x) ((x) << S_RESET1) +#define F_RESET1 V_RESET1(1U) + +#define S_RESET0 20 +#define V_RESET0(x) ((x) << S_RESET0) +#define F_RESET0 V_RESET0(1U) + +#define S_PWRDN3 19 +#define V_PWRDN3(x) ((x) << S_PWRDN3) +#define F_PWRDN3 V_PWRDN3(1U) + +#define S_PWRDN2 18 +#define V_PWRDN2(x) ((x) << S_PWRDN2) +#define F_PWRDN2 V_PWRDN2(1U) + +#define S_PWRDN1 17 +#define V_PWRDN1(x) ((x) << S_PWRDN1) +#define F_PWRDN1 V_PWRDN1(1U) + +#define S_PWRDN0 16 +#define V_PWRDN0(x) ((x) << S_PWRDN0) +#define F_PWRDN0 V_PWRDN0(1U) + +#define S_RESETPLL23 15 +#define V_RESETPLL23(x) ((x) << S_RESETPLL23) +#define F_RESETPLL23 V_RESETPLL23(1U) + +#define S_RESETPLL01 14 +#define V_RESETPLL01(x) ((x) << S_RESETPLL01) +#define F_RESETPLL01 V_RESETPLL01(1U) + +#define S_PW23 12 +#define M_PW23 0x3U +#define V_PW23(x) ((x) << S_PW23) +#define G_PW23(x) (((x) >> S_PW23) & M_PW23) + +#define S_PW01 10 +#define M_PW01 0x3U +#define V_PW01(x) ((x) << S_PW01) +#define G_PW01(x) (((x) >> S_PW01) & M_PW01) + +#define S_DEQ 6 +#define M_DEQ 0xfU +#define V_DEQ(x) ((x) << S_DEQ) +#define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ) + +#define S_DTX 2 +#define M_DTX 0xfU +#define V_DTX(x) ((x) << S_DTX) +#define G_DTX(x) (((x) >> S_DTX) & M_DTX) + +#define S_LODRV 1 +#define V_LODRV(x) ((x) << S_LODRV) +#define F_LODRV V_LODRV(1U) + +#define S_HIDRV 0 +#define V_HIDRV(x) ((x) << S_HIDRV) +#define F_HIDRV V_HIDRV(1U) + +#define A_NCSI_SERDES_CTRL1 0x1a2e4 + +#define S_FMOFFSET3 19 +#define M_FMOFFSET3 0x1fU +#define V_FMOFFSET3(x) ((x) << S_FMOFFSET3) +#define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3) + +#define S_FMOFFSETEN3 18 +#define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3) +#define F_FMOFFSETEN3 V_FMOFFSETEN3(1U) + +#define S_FMOFFSET2 13 +#define M_FMOFFSET2 0x1fU +#define V_FMOFFSET2(x) ((x) << S_FMOFFSET2) +#define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2) + +#define S_FMOFFSETEN2 12 +#define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2) +#define F_FMOFFSETEN2 V_FMOFFSETEN2(1U) + +#define S_FMOFFSET1 7 +#define M_FMOFFSET1 0x1fU +#define V_FMOFFSET1(x) ((x) << S_FMOFFSET1) +#define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1) + +#define S_FMOFFSETEN1 6 +#define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1) +#define F_FMOFFSETEN1 V_FMOFFSETEN1(1U) + +#define S_FMOFFSET0 1 +#define M_FMOFFSET0 0x1fU +#define V_FMOFFSET0(x) ((x) << S_FMOFFSET0) +#define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0) + +#define S_FMOFFSETEN0 0 +#define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0) +#define F_FMOFFSETEN0 V_FMOFFSETEN0(1U) + +#define A_NCSI_SERDES_CTRL2 0x1a2e8 + +#define S_DNIN3 11 +#define V_DNIN3(x) ((x) << S_DNIN3) +#define F_DNIN3 V_DNIN3(1U) + +#define S_UPIN3 10 +#define V_UPIN3(x) ((x) << S_UPIN3) +#define F_UPIN3 V_UPIN3(1U) + +#define S_RXSLAVE3 9 +#define V_RXSLAVE3(x) ((x) << S_RXSLAVE3) +#define F_RXSLAVE3 V_RXSLAVE3(1U) + +#define S_DNIN2 8 +#define V_DNIN2(x) ((x) << S_DNIN2) +#define F_DNIN2 V_DNIN2(1U) + +#define S_UPIN2 7 +#define V_UPIN2(x) ((x) << S_UPIN2) +#define F_UPIN2 V_UPIN2(1U) + +#define S_RXSLAVE2 6 +#define V_RXSLAVE2(x) ((x) << S_RXSLAVE2) +#define F_RXSLAVE2 V_RXSLAVE2(1U) + +#define S_DNIN1 5 +#define V_DNIN1(x) ((x) << S_DNIN1) +#define F_DNIN1 V_DNIN1(1U) + +#define S_UPIN1 4 +#define V_UPIN1(x) ((x) << S_UPIN1) +#define F_UPIN1 V_UPIN1(1U) + +#define S_RXSLAVE1 3 +#define V_RXSLAVE1(x) ((x) << S_RXSLAVE1) +#define F_RXSLAVE1 V_RXSLAVE1(1U) + +#define S_DNIN0 2 +#define V_DNIN0(x) ((x) << S_DNIN0) +#define F_DNIN0 V_DNIN0(1U) + +#define S_UPIN0 1 +#define V_UPIN0(x) ((x) << S_UPIN0) +#define F_UPIN0 V_UPIN0(1U) + +#define S_RXSLAVE0 0 +#define V_RXSLAVE0(x) ((x) << S_RXSLAVE0) +#define F_RXSLAVE0 V_RXSLAVE0(1U) + +#define A_NCSI_SERDES_CTRL3 0x1a2ec + +#define S_EXTBISTCHKERRCLR3 31 +#define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3) +#define F_EXTBISTCHKERRCLR3 V_EXTBISTCHKERRCLR3(1U) + +#define S_EXTBISTCHKEN3 30 +#define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3) +#define F_EXTBISTCHKEN3 V_EXTBISTCHKEN3(1U) + +#define S_EXTBISTGENEN3 29 +#define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3) +#define F_EXTBISTGENEN3 V_EXTBISTGENEN3(1U) + +#define S_EXTBISTPAT3 26 +#define M_EXTBISTPAT3 0x7U +#define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3) +#define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3) + +#define S_EXTPARRESET3 25 +#define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3) +#define F_EXTPARRESET3 V_EXTPARRESET3(1U) + +#define S_EXTPARLPBK3 24 +#define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3) +#define F_EXTPARLPBK3 V_EXTPARLPBK3(1U) + +#define S_EXTBISTCHKERRCLR2 23 +#define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2) +#define F_EXTBISTCHKERRCLR2 V_EXTBISTCHKERRCLR2(1U) + +#define S_EXTBISTCHKEN2 22 +#define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2) +#define F_EXTBISTCHKEN2 V_EXTBISTCHKEN2(1U) + +#define S_EXTBISTGENEN2 21 +#define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2) +#define F_EXTBISTGENEN2 V_EXTBISTGENEN2(1U) + +#define S_EXTBISTPAT2 18 +#define M_EXTBISTPAT2 0x7U +#define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2) +#define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2) + +#define S_EXTPARRESET2 17 +#define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2) +#define F_EXTPARRESET2 V_EXTPARRESET2(1U) + +#define S_EXTPARLPBK2 16 +#define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2) +#define F_EXTPARLPBK2 V_EXTPARLPBK2(1U) + +#define S_EXTBISTCHKERRCLR1 15 +#define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1) +#define F_EXTBISTCHKERRCLR1 V_EXTBISTCHKERRCLR1(1U) + +#define S_EXTBISTCHKEN1 14 +#define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1) +#define F_EXTBISTCHKEN1 V_EXTBISTCHKEN1(1U) + +#define S_EXTBISTGENEN1 13 +#define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1) +#define F_EXTBISTGENEN1 V_EXTBISTGENEN1(1U) + +#define S_EXTBISTPAT1 10 +#define M_EXTBISTPAT1 0x7U +#define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1) +#define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1) + +#define S_EXTPARRESET1 9 +#define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1) +#define F_EXTPARRESET1 V_EXTPARRESET1(1U) + +#define S_EXTPARLPBK1 8 +#define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1) +#define F_EXTPARLPBK1 V_EXTPARLPBK1(1U) + +#define S_EXTBISTCHKERRCLR0 7 +#define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0) +#define F_EXTBISTCHKERRCLR0 V_EXTBISTCHKERRCLR0(1U) + +#define S_EXTBISTCHKEN0 6 +#define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0) +#define F_EXTBISTCHKEN0 V_EXTBISTCHKEN0(1U) + +#define S_EXTBISTGENEN0 5 +#define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0) +#define F_EXTBISTGENEN0 V_EXTBISTGENEN0(1U) + +#define S_EXTBISTPAT0 2 +#define M_EXTBISTPAT0 0x7U +#define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0) +#define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0) + +#define S_EXTPARRESET0 1 +#define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0) +#define F_EXTPARRESET0 V_EXTPARRESET0(1U) + +#define S_EXTPARLPBK0 0 +#define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0) +#define F_EXTPARLPBK0 V_EXTPARLPBK0(1U) + +#define A_NCSI_SERDES_STAT0 0x1a2f0 + +#define S_EXTBISTCHKERRCNT0 4 +#define M_EXTBISTCHKERRCNT0 0xffffffU +#define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0) +#define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0) + +#define S_EXTBISTCHKFMD0 3 +#define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0) +#define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U) + +#define S_LOWSIGFORCEEN0 2 +#define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0) +#define F_LOWSIGFORCEEN0 V_LOWSIGFORCEEN0(1U) + +#define S_LOWSIGFORCEVALUE0 1 +#define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0) +#define F_LOWSIGFORCEVALUE0 V_LOWSIGFORCEVALUE0(1U) + +#define S_LOWSIG0 0 +#define V_LOWSIG0(x) ((x) << S_LOWSIG0) +#define F_LOWSIG0 V_LOWSIG0(1U) + +#define A_NCSI_SERDES_STAT1 0x1a2f4 + +#define S_EXTBISTCHKERRCNT1 4 +#define M_EXTBISTCHKERRCNT1 0xffffffU +#define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1) +#define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1) + +#define S_EXTBISTCHKFMD1 3 +#define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1) +#define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U) + +#define S_LOWSIGFORCEEN1 2 +#define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1) +#define F_LOWSIGFORCEEN1 V_LOWSIGFORCEEN1(1U) + +#define S_LOWSIGFORCEVALUE1 1 +#define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1) +#define F_LOWSIGFORCEVALUE1 V_LOWSIGFORCEVALUE1(1U) + +#define S_LOWSIG1 0 +#define V_LOWSIG1(x) ((x) << S_LOWSIG1) +#define F_LOWSIG1 V_LOWSIG1(1U) + +#define A_NCSI_SERDES_STAT2 0x1a2f8 + +#define S_EXTBISTCHKERRCNT2 4 +#define M_EXTBISTCHKERRCNT2 0xffffffU +#define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2) +#define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2) + +#define S_EXTBISTCHKFMD2 3 +#define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2) +#define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U) + +#define S_LOWSIGFORCEEN2 2 +#define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2) +#define F_LOWSIGFORCEEN2 V_LOWSIGFORCEEN2(1U) + +#define S_LOWSIGFORCEVALUE2 1 +#define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2) +#define F_LOWSIGFORCEVALUE2 V_LOWSIGFORCEVALUE2(1U) + +#define S_LOWSIG2 0 +#define V_LOWSIG2(x) ((x) << S_LOWSIG2) +#define F_LOWSIG2 V_LOWSIG2(1U) + +#define A_NCSI_SERDES_STAT3 0x1a2fc + +#define S_EXTBISTCHKERRCNT3 4 +#define M_EXTBISTCHKERRCNT3 0xffffffU +#define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3) +#define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3) + +#define S_EXTBISTCHKFMD3 3 +#define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3) +#define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U) + +#define S_LOWSIGFORCEEN3 2 +#define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3) +#define F_LOWSIGFORCEEN3 V_LOWSIGFORCEEN3(1U) + +#define S_LOWSIGFORCEVALUE3 1 +#define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3) +#define F_LOWSIGFORCEVALUE3 V_LOWSIGFORCEVALUE3(1U) + +#define S_LOWSIG3 0 +#define V_LOWSIG3(x) ((x) << S_LOWSIG3) +#define F_LOWSIG3 V_LOWSIG3(1U) + +#define A_NCSI_STAT_TX_BYTE_LOW 0x1a300 +#define A_NCSI_STAT_TX_BYTE_HIGH 0x1a304 +#define A_NCSI_STAT_TX_FRAME_LOW 0x1a308 +#define A_NCSI_STAT_TX_FRAME_HIGH 0x1a30c +#define A_NCSI_STAT_TX_BCAST 0x1a310 +#define A_NCSI_STAT_TX_MCAST 0x1a314 +#define A_NCSI_STAT_TX_PAUSE 0x1a318 +#define A_NCSI_STAT_TX_64B_FRAMES 0x1a31c +#define A_NCSI_STAT_TX_65_127B_FRAMES 0x1a320 +#define A_NCSI_STAT_TX_128_255B_FRAMES 0x1a324 +#define A_NCSI_STAT_TX_256_511B_FRAMES 0x1a328 +#define A_NCSI_STAT_TX_512_1023B_FRAMES 0x1a32c +#define A_NCSI_STAT_TX_1024_1518B_FRAMES 0x1a330 +#define A_NCSI_STAT_TX_1519_MAXB_FRAMES 0x1a334 +#define A_NCSI_STAT_TX_ERR_FRAMES 0x1a338 +#define A_NCSI_STAT_RX_BYTES_LOW 0x1a33c +#define A_NCSI_STAT_RX_BYTES_HIGH 0x1a340 +#define A_NCSI_STAT_RX_FRAMES_LOW 0x1a344 +#define A_NCSI_STAT_RX_FRAMES_HIGH 0x1a348 +#define A_NCSI_STAT_RX_BCAST_FRAMES 0x1a34c +#define A_NCSI_STAT_RX_MCAST_FRAMES 0x1a350 +#define A_NCSI_STAT_RX_PAUSE_FRAMES 0x1a354 +#define A_NCSI_STAT_RX_64B_FRAMES 0x1a358 +#define A_NCSI_STAT_RX_65_127B_FRAMES 0x1a35c +#define A_NCSI_STAT_RX_128_255B_FRAMES 0x1a360 +#define A_NCSI_STAT_RX_256_511B_FRAMES 0x1a364 +#define A_NCSI_STAT_RX_512_1023B_FRAMES 0x1a368 +#define A_NCSI_STAT_RX_1024_1518B_FRAMES 0x1a36c +#define A_NCSI_STAT_RX_1519_MAXB_FRAMES 0x1a370 +#define A_NCSI_STAT_RX_SHORT_FRAMES 0x1a374 +#define A_NCSI_STAT_RX_OVERSIZE_FRAMES 0x1a378 +#define A_NCSI_STAT_RX_JABBER_FRAMES 0x1a37c +#define A_NCSI_STAT_RX_CRC_ERR_FRAMES 0x1a380 +#define A_NCSI_STAT_RX_LENGTH_ERR_FRAMES 0x1a384 +#define A_NCSI_STAT_RX_SYM_CODE_ERR_FRAMES 0x1a388 +#define A_NCSI_XAUI_PCS_ERR 0x1a398 + +#define S_PCS_SYNCSTATUS 5 +#define M_PCS_SYNCSTATUS 0xfU +#define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS) +#define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS) + +#define S_PCS_CTCFIFOERR 1 +#define M_PCS_CTCFIFOERR 0xfU +#define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR) +#define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR) + +#define S_PCS_NOTALIGNED 0 +#define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED) +#define F_PCS_NOTALIGNED V_PCS_NOTALIGNED(1U) + +#define A_NCSI_RGMII_STATUS 0x1a39c + +#define S_GMIIDUPLEX 3 +#define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX) +#define F_GMIIDUPLEX V_GMIIDUPLEX(1U) + +#define S_GMIISPEED 1 +#define M_GMIISPEED 0x3U +#define V_GMIISPEED(x) ((x) << S_GMIISPEED) +#define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED) + +#define S_GMIILINKSTATUS 0 +#define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS) +#define F_GMIILINKSTATUS V_GMIILINKSTATUS(1U) + +#define A_NCSI_WOL_STATUS 0x1a3a0 + +#define S_T7_PATDETECTED 31 +#define V_T7_PATDETECTED(x) ((x) << S_T7_PATDETECTED) +#define F_T7_PATDETECTED V_T7_PATDETECTED(1U) + +#define A_NCSI_RX_MAX_PKT_SIZE_ERR_CNT 0x1a3a4 +#define A_NCSI_TX_SPI4_SOP_EOP_CNT 0x1a3a8 + +#define S_TXSPI4SOPCNT 16 +#define M_TXSPI4SOPCNT 0xffffU +#define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT) +#define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT) + +#define S_TXSPI4EOPCNT 0 +#define M_TXSPI4EOPCNT 0xffffU +#define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT) +#define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT) + +#define A_NCSI_RX_SPI4_SOP_EOP_CNT 0x1a3ac + +#define S_RXSPI4SOPCNT 16 +#define M_RXSPI4SOPCNT 0xffffU +#define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT) +#define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT) + +#define S_RXSPI4EOPCNT 0 +#define M_RXSPI4EOPCNT 0xffffU +#define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT) +#define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT) + /* registers for module XGMAC */ #define XGMAC_BASE_ADDR 0x0 @@ -44054,6 +56225,16 @@ #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY) #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY) +#define S_T7_IBQGEN1 10 +#define M_T7_IBQGEN1 0x3fU +#define V_T7_IBQGEN1(x) ((x) << S_T7_IBQGEN1) +#define G_T7_IBQGEN1(x) (((x) >> S_T7_IBQGEN1) & M_T7_IBQGEN1) + +#define S_T7_IBQEMPTY 0 +#define M_T7_IBQEMPTY 0x3ffU +#define V_T7_IBQEMPTY(x) ((x) << S_T7_IBQEMPTY) +#define G_T7_IBQEMPTY(x) (((x) >> S_T7_IBQEMPTY) & M_T7_IBQEMPTY) + #define A_UP_OBQ_GEN 0xc #define S_OBQGEN 6 @@ -44076,6 +56257,16 @@ #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL) #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL) +#define S_T7_T5_OBQGEN 16 +#define M_T7_T5_OBQGEN 0xffffU +#define V_T7_T5_OBQGEN(x) ((x) << S_T7_T5_OBQGEN) +#define G_T7_T5_OBQGEN(x) (((x) >> S_T7_T5_OBQGEN) & M_T7_T5_OBQGEN) + +#define S_T7_T5_OBQFULL 0 +#define M_T7_T5_OBQFULL 0xffffU +#define V_T7_T5_OBQFULL(x) ((x) << S_T7_T5_OBQFULL) +#define G_T7_T5_OBQFULL(x) (((x) >> S_T7_T5_OBQFULL) & M_T7_T5_OBQFULL) + #define A_UP_IBQ_0_RDADDR 0x10 #define S_QUEID 13 @@ -44088,6 +56279,13 @@ #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR) #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR) +#define A_UP_IBQ_GEN_IPC 0x10 + +#define S_IPCEMPTY 0 +#define M_IPCEMPTY 0x7fU +#define V_IPCEMPTY(x) ((x) << S_IPCEMPTY) +#define G_IPCEMPTY(x) (((x) >> S_IPCEMPTY) & M_IPCEMPTY) + #define A_UP_IBQ_0_WRADDR 0x14 #define S_IBQWRADDR 0 @@ -44160,10 +56358,15 @@ #define A_UP_OBQ_0_STATUS 0x78 #define A_UP_OBQ_0_PKTCNT 0x7c #define A_UP_OBQ_1_RDADDR 0x80 +#define A_UP_NXT_FLOWADDR0 0x80 #define A_UP_OBQ_1_WRADDR 0x84 +#define A_UP_NXT_FLOWADDR1 0x84 #define A_UP_OBQ_1_STATUS 0x88 +#define A_UP_NXT_FLOWADDR2 0x88 #define A_UP_OBQ_1_PKTCNT 0x8c +#define A_UP_NXT_FLOWADDR3 0x8c #define A_UP_OBQ_2_RDADDR 0x90 +#define A_UP_DFT_FLOWADDR 0x90 #define A_UP_OBQ_2_WRADDR 0x94 #define A_UP_OBQ_2_STATUS 0x98 #define A_UP_OBQ_2_PKTCNT 0x9c @@ -44176,9 +56379,33 @@ #define A_UP_OBQ_4_STATUS 0xb8 #define A_UP_OBQ_4_PKTCNT 0xbc #define A_UP_OBQ_5_RDADDR 0xc0 +#define A_UP_MAX_SEQ_NUM 0xc0 #define A_UP_OBQ_5_WRADDR 0xc4 +#define A_UP_UNACK_SEQ_NUM 0xc4 #define A_UP_OBQ_5_STATUS 0xc8 +#define A_UP_SEARCH_SEQ_NUM 0xc8 #define A_UP_OBQ_5_PKTCNT 0xcc +#define A_UP_SEQ_SEARCH_CTRL 0xcc + +#define S_FIFO_SIZE 29 +#define M_FIFO_SIZE 0x7U +#define V_FIFO_SIZE(x) ((x) << S_FIFO_SIZE) +#define G_FIFO_SIZE(x) (((x) >> S_FIFO_SIZE) & M_FIFO_SIZE) + +#define S_ROCE_MODE 28 +#define V_ROCE_MODE(x) ((x) << S_ROCE_MODE) +#define F_ROCE_MODE V_ROCE_MODE(1U) + +#define S_SEQ_WR_PTR 16 +#define M_SEQ_WR_PTR 0xfffU +#define V_SEQ_WR_PTR(x) ((x) << S_SEQ_WR_PTR) +#define G_SEQ_WR_PTR(x) (((x) >> S_SEQ_WR_PTR) & M_SEQ_WR_PTR) + +#define S_SEQ_RD_PTR 0 +#define M_SEQ_RD_PTR 0xfffU +#define V_SEQ_RD_PTR(x) ((x) << S_SEQ_RD_PTR) +#define G_SEQ_RD_PTR(x) (((x) >> S_SEQ_RD_PTR) & M_SEQ_RD_PTR) + #define A_UP_IBQ_0_CONFIG 0xd0 #define S_QUESIZE 26 @@ -44203,6 +56430,25 @@ #define V_QUE1KEN(x) ((x) << S_QUE1KEN) #define F_QUE1KEN V_QUE1KEN(1U) +#define A_UP_SEQ_SEARCH_RES0 0xd0 + +#define S_INV_SEQ 18 +#define V_INV_SEQ(x) ((x) << S_INV_SEQ) +#define F_INV_SEQ V_INV_SEQ(1U) + +#define S_DUP_SEQ 17 +#define V_DUP_SEQ(x) ((x) << S_DUP_SEQ) +#define F_DUP_SEQ V_DUP_SEQ(1U) + +#define S_MATCH_VLD 16 +#define V_MATCH_VLD(x) ((x) << S_MATCH_VLD) +#define F_MATCH_VLD V_MATCH_VLD(1U) + +#define S_MATCH_INDEX 0 +#define M_MATCH_INDEX 0xffffU +#define V_MATCH_INDEX(x) ((x) << S_MATCH_INDEX) +#define G_MATCH_INDEX(x) (((x) >> S_MATCH_INDEX) & M_MATCH_INDEX) + #define A_UP_IBQ_0_REALADDR 0xd4 #define S_QUERDADDRWRAP 31 @@ -44218,6 +56464,7 @@ #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR) #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR) +#define A_UP_SEQ_SEARCH_RES1 0xd4 #define A_UP_IBQ_1_CONFIG 0xd8 #define A_UP_IBQ_1_REALADDR 0xdc #define A_UP_IBQ_2_CONFIG 0xe0 @@ -44229,14 +56476,34 @@ #define A_UP_IBQ_5_CONFIG 0xf8 #define A_UP_IBQ_5_REALADDR 0xfc #define A_UP_OBQ_0_CONFIG 0x100 +#define A_UP_PEER_HALT_STAT0 0x100 + +#define S_HALTINFO 1 +#define M_HALTINFO 0x7fffffffU +#define V_HALTINFO(x) ((x) << S_HALTINFO) +#define G_HALTINFO(x) (((x) >> S_HALTINFO) & M_HALTINFO) + #define A_UP_OBQ_0_REALADDR 0x104 +#define A_UP_PEER_HALT_STAT1 0x104 #define A_UP_OBQ_1_CONFIG 0x108 +#define A_UP_PEER_HALT_STAT2 0x108 #define A_UP_OBQ_1_REALADDR 0x10c +#define A_UP_PEER_HALT_STAT3 0x10c #define A_UP_OBQ_2_CONFIG 0x110 +#define A_UP_PEER_HALT_STAT4 0x110 #define A_UP_OBQ_2_REALADDR 0x114 +#define A_UP_PEER_HALT_STAT5 0x114 #define A_UP_OBQ_3_CONFIG 0x118 +#define A_UP_PEER_HALT_STAT6 0x118 #define A_UP_OBQ_3_REALADDR 0x11c +#define A_UP_PEER_HALT_STAT7 0x11c #define A_UP_OBQ_4_CONFIG 0x120 +#define A_UP_PEER_HALT_CTL 0x120 + +#define S_HALTREQ 0 +#define V_HALTREQ(x) ((x) << S_HALTREQ) +#define F_HALTREQ V_HALTREQ(1U) + #define A_UP_OBQ_4_REALADDR 0x124 #define A_UP_OBQ_5_CONFIG 0x128 #define A_UP_OBQ_5_REALADDR 0x12c @@ -44516,6 +56783,204 @@ #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc +#define A_T7_UP_IBQ_0_SHADOW_RDADDR 0x400 +#define A_T7_UP_IBQ_0_SHADOW_WRADDR 0x404 +#define A_T7_UP_IBQ_0_SHADOW_STATUS 0x408 + +#define S_T7_QUEREMFLITS 0 +#define M_T7_QUEREMFLITS 0xfffU +#define V_T7_QUEREMFLITS(x) ((x) << S_T7_QUEREMFLITS) +#define G_T7_QUEREMFLITS(x) (((x) >> S_T7_QUEREMFLITS) & M_T7_QUEREMFLITS) + +#define A_T7_UP_IBQ_0_SHADOW_PKTCNT 0x40c +#define A_T7_UP_IBQ_1_SHADOW_RDADDR 0x410 +#define A_T7_UP_IBQ_1_SHADOW_WRADDR 0x414 +#define A_T7_UP_IBQ_1_SHADOW_STATUS 0x418 +#define A_T7_UP_IBQ_1_SHADOW_PKTCNT 0x41c +#define A_T7_UP_IBQ_2_SHADOW_RDADDR 0x420 +#define A_T7_UP_IBQ_2_SHADOW_WRADDR 0x424 +#define A_T7_UP_IBQ_2_SHADOW_STATUS 0x428 +#define A_T7_UP_IBQ_2_SHADOW_PKTCNT 0x42c +#define A_T7_UP_IBQ_3_SHADOW_RDADDR 0x430 +#define A_T7_UP_IBQ_3_SHADOW_WRADDR 0x434 +#define A_T7_UP_IBQ_3_SHADOW_STATUS 0x438 +#define A_T7_UP_IBQ_3_SHADOW_PKTCNT 0x43c +#define A_T7_UP_IBQ_4_SHADOW_RDADDR 0x440 +#define A_T7_UP_IBQ_4_SHADOW_WRADDR 0x444 +#define A_T7_UP_IBQ_4_SHADOW_STATUS 0x448 +#define A_T7_UP_IBQ_4_SHADOW_PKTCNT 0x44c +#define A_T7_UP_IBQ_5_SHADOW_RDADDR 0x450 +#define A_T7_UP_IBQ_5_SHADOW_WRADDR 0x454 +#define A_T7_UP_IBQ_5_SHADOW_STATUS 0x458 +#define A_T7_UP_IBQ_5_SHADOW_PKTCNT 0x45c +#define A_UP_IBQ_6_SHADOW_RDADDR 0x460 +#define A_UP_IBQ_6_SHADOW_WRADDR 0x464 +#define A_UP_IBQ_6_SHADOW_STATUS 0x468 +#define A_UP_IBQ_6_SHADOW_PKTCNT 0x46c +#define A_UP_IBQ_7_SHADOW_RDADDR 0x470 +#define A_UP_IBQ_7_SHADOW_WRADDR 0x474 +#define A_UP_IBQ_7_SHADOW_STATUS 0x478 +#define A_UP_IBQ_7_SHADOW_PKTCNT 0x47c +#define A_UP_IBQ_8_SHADOW_RDADDR 0x480 +#define A_UP_IBQ_8_SHADOW_WRADDR 0x484 +#define A_UP_IBQ_8_SHADOW_STATUS 0x488 +#define A_UP_IBQ_8_SHADOW_PKTCNT 0x48c +#define A_UP_IBQ_9_SHADOW_RDADDR 0x490 +#define A_UP_IBQ_9_SHADOW_WRADDR 0x494 +#define A_UP_IBQ_9_SHADOW_STATUS 0x498 +#define A_UP_IBQ_9_SHADOW_PKTCNT 0x49c +#define A_UP_IBQ_10_SHADOW_RDADDR 0x4a0 +#define A_UP_IBQ_10_SHADOW_WRADDR 0x4a4 +#define A_UP_IBQ_10_SHADOW_STATUS 0x4a8 +#define A_UP_IBQ_10_SHADOW_PKTCNT 0x4ac +#define A_UP_IBQ_11_SHADOW_RDADDR 0x4b0 +#define A_UP_IBQ_11_SHADOW_WRADDR 0x4b4 +#define A_UP_IBQ_11_SHADOW_STATUS 0x4b8 +#define A_UP_IBQ_11_SHADOW_PKTCNT 0x4bc +#define A_UP_IBQ_12_SHADOW_RDADDR 0x4c0 +#define A_UP_IBQ_12_SHADOW_WRADDR 0x4c4 +#define A_UP_IBQ_12_SHADOW_STATUS 0x4c8 +#define A_UP_IBQ_12_SHADOW_PKTCNT 0x4cc +#define A_UP_IBQ_13_SHADOW_RDADDR 0x4d0 +#define A_UP_IBQ_13_SHADOW_WRADDR 0x4d4 +#define A_UP_IBQ_13_SHADOW_STATUS 0x4d8 +#define A_UP_IBQ_13_SHADOW_PKTCNT 0x4dc +#define A_UP_IBQ_14_SHADOW_RDADDR 0x4e0 +#define A_UP_IBQ_14_SHADOW_WRADDR 0x4e4 +#define A_UP_IBQ_14_SHADOW_STATUS 0x4e8 +#define A_UP_IBQ_14_SHADOW_PKTCNT 0x4ec +#define A_UP_IBQ_15_SHADOW_RDADDR 0x4f0 +#define A_UP_IBQ_15_SHADOW_WRADDR 0x4f4 +#define A_UP_IBQ_15_SHADOW_STATUS 0x4f8 +#define A_UP_IBQ_15_SHADOW_PKTCNT 0x4fc +#define A_T7_UP_IBQ_0_SHADOW_CONFIG 0x500 +#define A_T7_UP_IBQ_0_SHADOW_REALADDR 0x504 +#define A_T7_UP_IBQ_1_SHADOW_CONFIG 0x510 +#define A_T7_UP_IBQ_1_SHADOW_REALADDR 0x514 +#define A_T7_UP_IBQ_2_SHADOW_CONFIG 0x520 +#define A_T7_UP_IBQ_2_SHADOW_REALADDR 0x524 +#define A_T7_UP_IBQ_3_SHADOW_CONFIG 0x530 +#define A_T7_UP_IBQ_3_SHADOW_REALADDR 0x534 +#define A_T7_UP_IBQ_4_SHADOW_CONFIG 0x540 +#define A_T7_UP_IBQ_4_SHADOW_REALADDR 0x544 +#define A_T7_UP_IBQ_5_SHADOW_CONFIG 0x550 +#define A_T7_UP_IBQ_5_SHADOW_REALADDR 0x554 +#define A_UP_IBQ_6_SHADOW_CONFIG 0x560 +#define A_UP_IBQ_6_SHADOW_REALADDR 0x564 +#define A_UP_IBQ_7_SHADOW_CONFIG 0x570 +#define A_UP_IBQ_7_SHADOW_REALADDR 0x574 +#define A_UP_IBQ_8_SHADOW_CONFIG 0x580 +#define A_UP_IBQ_8_SHADOW_REALADDR 0x584 +#define A_UP_IBQ_9_SHADOW_CONFIG 0x590 +#define A_UP_IBQ_9_SHADOW_REALADDR 0x594 +#define A_UP_IBQ_10_SHADOW_CONFIG 0x5a0 +#define A_UP_IBQ_10_SHADOW_REALADDR 0x5a4 +#define A_UP_IBQ_11_SHADOW_CONFIG 0x5b0 +#define A_UP_IBQ_11_SHADOW_REALADDR 0x5b4 +#define A_UP_IBQ_12_SHADOW_CONFIG 0x5c0 +#define A_UP_IBQ_12_SHADOW_REALADDR 0x5c4 +#define A_UP_IBQ_13_SHADOW_CONFIG 0x5d0 +#define A_UP_IBQ_13_SHADOW_REALADDR 0x5d4 +#define A_UP_IBQ_14_SHADOW_CONFIG 0x5e0 +#define A_UP_IBQ_14_SHADOW_REALADDR 0x5e4 +#define A_UP_IBQ_15_SHADOW_CONFIG 0x5f0 +#define A_UP_IBQ_15_SHADOW_REALADDR 0x5f4 +#define A_T7_UP_OBQ_0_SHADOW_RDADDR 0x600 +#define A_T7_UP_OBQ_0_SHADOW_WRADDR 0x604 +#define A_T7_UP_OBQ_0_SHADOW_STATUS 0x608 +#define A_T7_UP_OBQ_0_SHADOW_PKTCNT 0x60c +#define A_T7_UP_OBQ_1_SHADOW_RDADDR 0x610 +#define A_T7_UP_OBQ_1_SHADOW_WRADDR 0x614 +#define A_T7_UP_OBQ_1_SHADOW_STATUS 0x618 +#define A_T7_UP_OBQ_1_SHADOW_PKTCNT 0x61c +#define A_T7_UP_OBQ_2_SHADOW_RDADDR 0x620 +#define A_T7_UP_OBQ_2_SHADOW_WRADDR 0x624 +#define A_T7_UP_OBQ_2_SHADOW_STATUS 0x628 +#define A_T7_UP_OBQ_2_SHADOW_PKTCNT 0x62c +#define A_T7_UP_OBQ_3_SHADOW_RDADDR 0x630 +#define A_T7_UP_OBQ_3_SHADOW_WRADDR 0x634 +#define A_T7_UP_OBQ_3_SHADOW_STATUS 0x638 +#define A_T7_UP_OBQ_3_SHADOW_PKTCNT 0x63c +#define A_T7_UP_OBQ_4_SHADOW_RDADDR 0x640 +#define A_T7_UP_OBQ_4_SHADOW_WRADDR 0x644 +#define A_T7_UP_OBQ_4_SHADOW_STATUS 0x648 +#define A_T7_UP_OBQ_4_SHADOW_PKTCNT 0x64c +#define A_T7_UP_OBQ_5_SHADOW_RDADDR 0x650 +#define A_T7_UP_OBQ_5_SHADOW_WRADDR 0x654 +#define A_T7_UP_OBQ_5_SHADOW_STATUS 0x658 +#define A_T7_UP_OBQ_5_SHADOW_PKTCNT 0x65c +#define A_T7_UP_OBQ_6_SHADOW_RDADDR 0x660 +#define A_T7_UP_OBQ_6_SHADOW_WRADDR 0x664 +#define A_T7_UP_OBQ_6_SHADOW_STATUS 0x668 +#define A_T7_UP_OBQ_6_SHADOW_PKTCNT 0x66c +#define A_T7_UP_OBQ_7_SHADOW_RDADDR 0x670 +#define A_T7_UP_OBQ_7_SHADOW_WRADDR 0x674 +#define A_T7_UP_OBQ_7_SHADOW_STATUS 0x678 +#define A_T7_UP_OBQ_7_SHADOW_PKTCNT 0x67c +#define A_UP_OBQ_8_SHADOW_RDADDR 0x680 +#define A_UP_OBQ_8_SHADOW_WRADDR 0x684 +#define A_UP_OBQ_8_SHADOW_STATUS 0x688 +#define A_UP_OBQ_8_SHADOW_PKTCNT 0x68c +#define A_UP_OBQ_9_SHADOW_RDADDR 0x690 +#define A_UP_OBQ_9_SHADOW_WRADDR 0x694 +#define A_UP_OBQ_9_SHADOW_STATUS 0x698 +#define A_UP_OBQ_9_SHADOW_PKTCNT 0x69c +#define A_UP_OBQ_10_SHADOW_RDADDR 0x6a0 +#define A_UP_OBQ_10_SHADOW_WRADDR 0x6a4 +#define A_UP_OBQ_10_SHADOW_STATUS 0x6a8 +#define A_UP_OBQ_10_SHADOW_PKTCNT 0x6ac +#define A_UP_OBQ_11_SHADOW_RDADDR 0x6b0 +#define A_UP_OBQ_11_SHADOW_WRADDR 0x6b4 +#define A_UP_OBQ_11_SHADOW_STATUS 0x6b8 +#define A_UP_OBQ_11_SHADOW_PKTCNT 0x6bc +#define A_UP_OBQ_12_SHADOW_RDADDR 0x6c0 +#define A_UP_OBQ_12_SHADOW_WRADDR 0x6c4 +#define A_UP_OBQ_12_SHADOW_STATUS 0x6c8 +#define A_UP_OBQ_12_SHADOW_PKTCNT 0x6cc +#define A_UP_OBQ_13_SHADOW_RDADDR 0x6d0 +#define A_UP_OBQ_13_SHADOW_WRADDR 0x6d4 +#define A_UP_OBQ_13_SHADOW_STATUS 0x6d8 +#define A_UP_OBQ_13_SHADOW_PKTCNT 0x6dc +#define A_UP_OBQ_14_SHADOW_RDADDR 0x6e0 +#define A_UP_OBQ_14_SHADOW_WRADDR 0x6e4 +#define A_UP_OBQ_14_SHADOW_STATUS 0x6e8 +#define A_UP_OBQ_14_SHADOW_PKTCNT 0x6ec +#define A_UP_OBQ_15_SHADOW_RDADDR 0x6f0 +#define A_UP_OBQ_15_SHADOW_WRADDR 0x6f4 +#define A_UP_OBQ_15_SHADOW_STATUS 0x6f8 +#define A_UP_OBQ_15_SHADOW_PKTCNT 0x6fc +#define A_T7_UP_OBQ_0_SHADOW_CONFIG 0x700 +#define A_T7_UP_OBQ_0_SHADOW_REALADDR 0x704 +#define A_T7_UP_OBQ_1_SHADOW_CONFIG 0x710 +#define A_T7_UP_OBQ_1_SHADOW_REALADDR 0x714 +#define A_T7_UP_OBQ_2_SHADOW_CONFIG 0x720 +#define A_T7_UP_OBQ_2_SHADOW_REALADDR 0x724 +#define A_T7_UP_OBQ_3_SHADOW_CONFIG 0x730 +#define A_T7_UP_OBQ_3_SHADOW_REALADDR 0x734 +#define A_T7_UP_OBQ_4_SHADOW_CONFIG 0x740 +#define A_T7_UP_OBQ_4_SHADOW_REALADDR 0x744 +#define A_T7_UP_OBQ_5_SHADOW_CONFIG 0x750 +#define A_T7_UP_OBQ_5_SHADOW_REALADDR 0x754 +#define A_T7_UP_OBQ_6_SHADOW_CONFIG 0x760 +#define A_T7_UP_OBQ_6_SHADOW_REALADDR 0x764 +#define A_T7_UP_OBQ_7_SHADOW_CONFIG 0x770 +#define A_T7_UP_OBQ_7_SHADOW_REALADDR 0x774 +#define A_UP_OBQ_8_SHADOW_CONFIG 0x780 +#define A_UP_OBQ_8_SHADOW_REALADDR 0x784 +#define A_UP_OBQ_9_SHADOW_CONFIG 0x790 +#define A_UP_OBQ_9_SHADOW_REALADDR 0x794 +#define A_UP_OBQ_10_SHADOW_CONFIG 0x7a0 +#define A_UP_OBQ_10_SHADOW_REALADDR 0x7a4 +#define A_UP_OBQ_11_SHADOW_CONFIG 0x7b0 +#define A_UP_OBQ_11_SHADOW_REALADDR 0x7b4 +#define A_UP_OBQ_12_SHADOW_CONFIG 0x7c0 +#define A_UP_OBQ_12_SHADOW_REALADDR 0x7c4 +#define A_UP_OBQ_13_SHADOW_CONFIG 0x7d0 +#define A_UP_OBQ_13_SHADOW_REALADDR 0x7d4 +#define A_UP_OBQ_14_SHADOW_CONFIG 0x7e0 +#define A_UP_OBQ_14_SHADOW_REALADDR 0x7e4 +#define A_UP_OBQ_15_SHADOW_CONFIG 0x7f0 +#define A_UP_OBQ_15_SHADOW_REALADDR 0x7f4 /* registers for module CIM_CTL */ #define CIM_CTL_BASE_ADDR 0x0 @@ -44579,17 +57044,63 @@ #define A_CIM_CTL_STATIC_PREFADDR10 0x38 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c #define A_CIM_CTL_STATIC_PREFADDR12 0x40 +#define A_CIM_CTL_SEM_CFG 0x40 + +#define S_SEMINIT 31 +#define V_SEMINIT(x) ((x) << S_SEMINIT) +#define F_SEMINIT V_SEMINIT(1U) + +#define S_NUMSEM 0 +#define M_NUMSEM 0x3ffffU +#define V_NUMSEM(x) ((x) << S_NUMSEM) +#define G_NUMSEM(x) (((x) >> S_NUMSEM) & M_NUMSEM) + #define A_CIM_CTL_STATIC_PREFADDR13 0x44 +#define A_CIM_CTL_SEM_MA_CFG 0x44 + +#define S_SEMMABASE 4 +#define M_SEMMABASE 0xfffffffU +#define V_SEMMABASE(x) ((x) << S_SEMMABASE) +#define G_SEMMABASE(x) (((x) >> S_SEMMABASE) & M_SEMMABASE) + +#define S_SEMMATHREADID 0 +#define M_SEMMATHREADID 0x7U +#define V_SEMMATHREADID(x) ((x) << S_SEMMATHREADID) +#define G_SEMMATHREADID(x) (((x) >> S_SEMMATHREADID) & M_SEMMATHREADID) + #define A_CIM_CTL_STATIC_PREFADDR14 0x48 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50 +#define A_CIM_CTL_LOCK_CFG 0x50 + +#define S_NUMLOCK 0 +#define M_NUMLOCK 0x3ffffU +#define V_NUMLOCK(x) ((x) << S_NUMLOCK) +#define G_NUMLOCK(x) (((x) >> S_NUMLOCK) & M_NUMLOCK) + #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54 +#define A_CIM_CTL_LOCK_MA_CFG 0x54 + +#define S_LOCKMABASE 4 +#define M_LOCKMABASE 0xfffffffU +#define V_LOCKMABASE(x) ((x) << S_LOCKMABASE) +#define G_LOCKMABASE(x) (((x) >> S_LOCKMABASE) & M_LOCKMABASE) + +#define S_LOCKMATHREADID 0 +#define M_LOCKMATHREADID 0x7U +#define V_LOCKMATHREADID(x) ((x) << S_LOCKMATHREADID) +#define G_LOCKMATHREADID(x) (((x) >> S_LOCKMATHREADID) & M_LOCKMATHREADID) + #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60 +#define A_CIM_CTL_RSA_INT 0x60 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64 +#define A_CIM_CTL_RSA_BUSY 0x64 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68 +#define A_CIM_CTL_RSA_CPERR 0x68 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c +#define A_CIM_CTL_RSA_DPERR 0x6c #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78 @@ -44650,6 +57161,66 @@ #define A_CIM_CTL_GEN_TIMER3 0xd0 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100 +#define A_CIM_CTL_TID_MAP_EN 0x500 +#define A_CIM_CTL_TID_MAP_CORE 0x520 +#define A_CIM_CTL_TID_MAP_CONFIG 0x540 + +#define S_TIDDEFCORE 4 +#define M_TIDDEFCORE 0xfU +#define V_TIDDEFCORE(x) ((x) << S_TIDDEFCORE) +#define G_TIDDEFCORE(x) (((x) >> S_TIDDEFCORE) & M_TIDDEFCORE) + +#define S_TIDVECBASE 0 +#define M_TIDVECBASE 0x7U +#define V_TIDVECBASE(x) ((x) << S_TIDVECBASE) +#define G_TIDVECBASE(x) (((x) >> S_TIDVECBASE) & M_TIDVECBASE) + +#define A_CIM_CTL_CRYPTO_KEY_DATA 0x600 +#define A_CIM_CTL_SECURE_CONFIG 0x6f8 +#define A_CIM_CTL_CRYPTO_KEY_CTRL 0x6fc + +#define S_CRYPTOKEYDATAREGNUM 8 +#define M_CRYPTOKEYDATAREGNUM 0xffU +#define V_CRYPTOKEYDATAREGNUM(x) ((x) << S_CRYPTOKEYDATAREGNUM) +#define G_CRYPTOKEYDATAREGNUM(x) (((x) >> S_CRYPTOKEYDATAREGNUM) & M_CRYPTOKEYDATAREGNUM) + +#define S_CRYPTOKEYSTARTBUSY 0 +#define V_CRYPTOKEYSTARTBUSY(x) ((x) << S_CRYPTOKEYSTARTBUSY) +#define F_CRYPTOKEYSTARTBUSY V_CRYPTOKEYSTARTBUSY(1U) + +#define A_CIM_CTL_FLOWID_OP_VALID 0x700 +#define A_CIM_CTL_FLOWID_CTL 0x720 + +#define S_FLOWBASEADDR 8 +#define M_FLOWBASEADDR 0xffffffU +#define V_FLOWBASEADDR(x) ((x) << S_FLOWBASEADDR) +#define G_FLOWBASEADDR(x) (((x) >> S_FLOWBASEADDR) & M_FLOWBASEADDR) + +#define S_SEQSRCHALIGNCFG 4 +#define M_SEQSRCHALIGNCFG 0x3U +#define V_SEQSRCHALIGNCFG(x) ((x) << S_SEQSRCHALIGNCFG) +#define G_SEQSRCHALIGNCFG(x) (((x) >> S_SEQSRCHALIGNCFG) & M_SEQSRCHALIGNCFG) + +#define S_FLOWADDRSIZE 1 +#define M_FLOWADDRSIZE 0x3U +#define V_FLOWADDRSIZE(x) ((x) << S_FLOWADDRSIZE) +#define G_FLOWADDRSIZE(x) (((x) >> S_FLOWADDRSIZE) & M_FLOWADDRSIZE) + +#define S_FLOWIDEN 0 +#define V_FLOWIDEN(x) ((x) << S_FLOWIDEN) +#define F_FLOWIDEN V_FLOWIDEN(1U) + +#define A_CIM_CTL_FLOWID_MAX 0x724 + +#define S_MAXFLOWID 0 +#define M_MAXFLOWID 0xffffffU +#define V_MAXFLOWID(x) ((x) << S_MAXFLOWID) +#define G_MAXFLOWID(x) (((x) >> S_MAXFLOWID) & M_MAXFLOWID) + +#define A_CIM_CTL_FLOWID_HINT0 0x728 +#define A_CIM_CTL_EFUSE_CTRL 0x780 +#define A_CIM_CTL_EFUSE_QOUT 0x784 +#define A_CIM_CTL_EFUSE_RFOUT 0x788 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900 #define S_TSCHNLEN 31 @@ -45001,14 +57572,19 @@ #define A_CIM_CTL_TSCH_TICK3 0xd8c #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90 +#define A_T7_CIM_CTL_MAILBOX_PF0_CTL 0xd90 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94 +#define A_T7_CIM_CTL_MAILBOX_PF1_CTL 0xd94 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98 +#define A_T7_CIM_CTL_MAILBOX_PF2_CTL 0xd98 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c +#define A_T7_CIM_CTL_MAILBOX_PF3_CTL 0xd9c #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0 +#define A_T7_CIM_CTL_MAILBOX_PF4_CTL 0xda0 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4 #define S_PF7_OWNER_PL 15 @@ -45076,6 +57652,7 @@ #define F_PF0_OWNER_UP V_PF0_OWNER_UP(1U) #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4 +#define A_T7_CIM_CTL_MAILBOX_PF5_CTL 0xda4 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8 #define S_T5_CTLRID 0 @@ -45084,15 +57661,13 @@ #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID) #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8 +#define A_T7_CIM_CTL_MAILBOX_PF6_CTL 0xda8 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac +#define A_T7_CIM_CTL_MAILBOX_PF7_CTL 0xdac #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0 +#define A_T7_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4 - -#define S_T6_UPRID 0 -#define M_T6_UPRID 0x1ffU -#define V_T6_UPRID(x) ((x) << S_T6_UPRID) -#define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID) - +#define A_T7_CIM_CTL_PIO_MST_CONFIG 0xdb4 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08 @@ -45119,6 +57694,64 @@ #define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT) #define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT) +#define A_CIM_CTL_BREAK 0xf00 + +#define S_XOCDMODE 8 +#define M_XOCDMODE 0xffU +#define V_XOCDMODE(x) ((x) << S_XOCDMODE) +#define G_XOCDMODE(x) (((x) >> S_XOCDMODE) & M_XOCDMODE) + +#define S_BREAKIN_CONTROL 0 +#define M_BREAKIN_CONTROL 0xffU +#define V_BREAKIN_CONTROL(x) ((x) << S_BREAKIN_CONTROL) +#define G_BREAKIN_CONTROL(x) (((x) >> S_BREAKIN_CONTROL) & M_BREAKIN_CONTROL) + +#define A_CIM_CTL_SLV_BOOT_CFG 0x4000 + +#define S_T7_UPGEN 3 +#define M_T7_UPGEN 0x1fU +#define V_T7_UPGEN(x) ((x) << S_T7_UPGEN) +#define G_T7_UPGEN(x) (((x) >> S_T7_UPGEN) & M_T7_UPGEN) + +#define S_UPCLKEN 2 +#define V_UPCLKEN(x) ((x) << S_UPCLKEN) +#define F_UPCLKEN V_UPCLKEN(1U) + +#define A_CIM_CTL_SLV_BOOT_LEN 0x4004 +#define A_CIM_CTL_SLV_ACC_INT_ENABLE 0x4008 +#define A_CIM_CTL_SLV_ACC_INT_CAUSE 0x400c +#define A_CIM_CTL_SLV_INT_ENABLE 0x4010 +#define A_CIM_CTL_SLV_INT_CAUSE 0x4014 +#define A_CIM_CTL_SLV_PERR_ENABLE 0x4018 +#define A_CIM_CTL_SLV_PERR_CAUSE 0x401c +#define A_CIM_CTL_SLV_ADDR_TIMEOUT 0x4028 +#define A_CIM_CTL_SLV_ADDR_ILLEGAL 0x402c +#define A_CIM_CTL_SLV_PIO_MST_CONFIG 0x4030 +#define A_CIM_CTL_SLV_MEM_ZONE0_VA 0x4040 +#define A_CIM_CTL_SLV_MEM_ZONE0_BA 0x4044 +#define A_CIM_CTL_SLV_MEM_ZONE0_LEN 0x4048 +#define A_CIM_CTL_SLV_MEM_ZONE1_VA 0x404c +#define A_CIM_CTL_SLV_MEM_ZONE1_BA 0x4050 +#define A_CIM_CTL_SLV_MEM_ZONE1_LEN 0x4054 +#define A_CIM_CTL_SLV_MEM_ZONE2_VA 0x4058 +#define A_CIM_CTL_SLV_MEM_ZONE2_BA 0x405c +#define A_CIM_CTL_SLV_MEM_ZONE2_LEN 0x4060 +#define A_CIM_CTL_SLV_MEM_ZONE3_VA 0x4064 +#define A_CIM_CTL_SLV_MEM_ZONE3_BA 0x4068 +#define A_CIM_CTL_SLV_MEM_ZONE3_LEN 0x406c +#define A_CIM_CTL_SLV_MEM_ZONE4_VA 0x4070 +#define A_CIM_CTL_SLV_MEM_ZONE4_BA 0x4074 +#define A_CIM_CTL_SLV_MEM_ZONE4_LEN 0x4078 +#define A_CIM_CTL_SLV_MEM_ZONE5_VA 0x407c +#define A_CIM_CTL_SLV_MEM_ZONE5_BA 0x4080 +#define A_CIM_CTL_SLV_MEM_ZONE5_LEN 0x4084 +#define A_CIM_CTL_SLV_MEM_ZONE6_VA 0x4088 +#define A_CIM_CTL_SLV_MEM_ZONE6_BA 0x408c +#define A_CIM_CTL_SLV_MEM_ZONE6_LEN 0x4090 +#define A_CIM_CTL_SLV_MEM_ZONE7_VA 0x4094 +#define A_CIM_CTL_SLV_MEM_ZONE7_BA 0x4098 +#define A_CIM_CTL_SLV_MEM_ZONE7_LEN 0x409c + /* registers for module MAC */ #define MAC_BASE_ADDR 0x0 @@ -46613,33 +59246,7 @@ #define F_PERR_TX_PCS1G V_PERR_TX_PCS1G(1U) #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4 - -#define S_T6_PERR_PKT_RAM 31 -#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM) -#define F_T6_PERR_PKT_RAM V_T6_PERR_PKT_RAM(1U) - -#define S_T6_PERR_MASK_RAM 30 -#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM) -#define F_T6_PERR_MASK_RAM V_T6_PERR_MASK_RAM(1U) - -#define S_T6_PERR_CRC_RAM 29 -#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM) -#define F_T6_PERR_CRC_RAM V_T6_PERR_CRC_RAM(1U) - #define A_MAC_PORT_PERR_ENABLE 0x8e8 - -#define S_T6_PERR_PKT_RAM 31 -#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM) -#define F_T6_PERR_PKT_RAM V_T6_PERR_PKT_RAM(1U) - -#define S_T6_PERR_MASK_RAM 30 -#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM) -#define F_T6_PERR_MASK_RAM V_T6_PERR_MASK_RAM(1U) - -#define S_T6_PERR_CRC_RAM 29 -#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM) -#define F_T6_PERR_CRC_RAM V_T6_PERR_CRC_RAM(1U) - #define A_MAC_PORT_PERR_INJECT 0x8ec #define S_MEMSEL_PERR 1 @@ -47304,10 +59911,12 @@ #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4 +#if 0 #define S_B 16 -#define CXGBE_M_B 0xffffU +#define M_B 0xffffU #define V_B(x) ((x) << S_B) -#define G_B(x) (((x) >> S_B) & CXGBE_M_B) +#define G_B(x) (((x) >> S_B) & M_B) +#endif #define S_A 0 #define M_A 0xffffU @@ -48454,10 +61063,6 @@ #define V_LOW_POWER(x) ((x) << S_LOW_POWER) #define F_LOW_POWER V_LOW_POWER(1U) -#define S_T6_SPEED_SEL1 6 -#define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1) -#define F_T6_SPEED_SEL1 V_T6_SPEED_SEL1(1U) - #define S_SPEED_SEL2 2 #define M_SPEED_SEL2 0xfU #define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2) @@ -49016,7 +61621,7 @@ #define S_VLANTAG 0 #define CXGBE_M_VLANTAG 0xffffU #define V_VLANTAG(x) ((x) << S_VLANTAG) -#define G_VLANTAG(x) (((x) >> S_VLANTAG) & CXGBE_M_VLANTAG) +#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG) #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08 @@ -51279,75 +63884,24 @@ #define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM) #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20 - -#define S_T6_INIT_METH 12 -#define M_T6_INIT_METH 0xfU -#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH) -#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH) - #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c #define A_MAC_PORT_AET_STATUS_1 0x2b30 - -#define S_T6_NEU_STATE 4 -#define M_T6_NEU_STATE 0xfU -#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE) -#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE) - -#define S_T6_CTRL_STATE 0 -#define M_T6_CTRL_STATE 0xfU -#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE) -#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE) - #define A_MAC_PORT_AET_STATUS_21 0x2b34 #define A_MAC_PORT_AET_LIMITS1 0x2b38 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40 - -#define S_T6_INIT_METH 12 -#define M_T6_INIT_METH 0xfU -#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH) -#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH) - #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c #define A_MAC_PORT_AET_STATUS_2 0x2b50 - -#define S_T6_NEU_STATE 4 -#define M_T6_NEU_STATE 0xfU -#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE) -#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE) - -#define S_T6_CTRL_STATE 0 -#define M_T6_CTRL_STATE 0xfU -#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE) -#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE) - #define A_MAC_PORT_AET_STATUS_22 0x2b54 #define A_MAC_PORT_AET_LIMITS2 0x2b58 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60 - -#define S_T6_INIT_METH 12 -#define M_T6_INIT_METH 0xfU -#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH) -#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH) - #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c #define A_MAC_PORT_AET_STATUS_3 0x2b70 - -#define S_T6_NEU_STATE 4 -#define M_T6_NEU_STATE 0xfU -#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE) -#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE) - -#define S_T6_CTRL_STATE 0 -#define M_T6_CTRL_STATE 0xfU -#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE) -#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE) - #define A_MAC_PORT_AET_STATUS_23 0x2b74 #define A_MAC_PORT_AET_LIMITS3 0x2b78 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00 @@ -52384,103 +64938,21 @@ #define F_BSOUTP V_BSOUTP(1U) #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100 - -#define S_T6_T5_TX_RXLOOP 5 -#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP) -#define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U) - -#define S_T6_T5_TX_BWSEL 2 -#define M_T6_T5_TX_BWSEL 0x3U -#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL) -#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104 - -#define S_T6_ERROR 9 -#define V_T6_ERROR(x) ((x) << S_T6_ERROR) -#define F_T6_ERROR V_T6_ERROR(1U) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118 - -#define S_T6_CALSSTN 8 -#define M_T6_CALSSTN 0x3fU -#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN) -#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN) - -#define S_T6_CALSSTP 0 -#define M_T6_CALSSTP 0x3fU -#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP) -#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c - -#define S_T6_DRTOL 2 -#define M_T6_DRTOL 0x7U -#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL) -#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120 - -#define S_T6_NXTT0 0 -#define M_T6_NXTT0 0x3fU -#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0) -#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128 - -#define S_T6_NXTT2 0 -#define M_T6_NXTT2 0x3fU -#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2) -#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134 - -#define S_T6_NXTPOL 0 -#define M_T6_NXTPOL 0xfU -#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL) -#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138 - -#define S_T6_C0UPDT 6 -#define M_T6_C0UPDT 0x3U -#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT) -#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT) - -#define S_T6_C2UPDT 2 -#define M_T6_C2UPDT 0x3U -#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT) -#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT) - -#define S_T6_C1UPDT 0 -#define M_T6_C1UPDT 0x3U -#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT) -#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c - -#define S_T6_C0STAT 6 -#define M_T6_C0STAT 0x3U -#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT) -#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT) - -#define S_T6_C2STAT 2 -#define M_T6_C2STAT 0x3U -#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT) -#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT) - -#define S_T6_C1STAT 0 -#define M_T6_C1STAT 0x3U -#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT) -#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144 @@ -52503,12 +64975,6 @@ #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c - -#define S_T6_XADDR 1 -#define M_T6_XADDR 0x1fU -#define V_T6_XADDR(x) ((x) << S_T6_XADDR) -#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188 @@ -52521,21 +64987,6 @@ #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0 -#define S_T6_DCCTIMEEN 13 -#define M_T6_DCCTIMEEN 0x3U -#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN) -#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN) - -#define S_T6_DCCLOCK 11 -#define M_T6_DCCLOCK 0x3U -#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK) -#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK) - -#define S_T6_DCCOFFSET 8 -#define M_T6_DCCOFFSET 0x7U -#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET) -#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET) - #define S_TX_LINKB_DCCSTEP_CTL 6 #define M_TX_LINKB_DCCSTEP_CTL 0x3U #define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL) @@ -52553,20 +65004,9 @@ #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0 - -#define S_T6_SDOVRD 0 -#define M_T6_SDOVRD 0xffffU -#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD) -#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc - -#define S_T6_SDOVRDEN 15 -#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN) -#define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U) - #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200 #define S_T5_RX_LINKEN 15 @@ -54442,56 +66882,15 @@ #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c - -#define S_T6_TMSCAL 8 -#define M_T6_TMSCAL 0x3U -#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL) -#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL) - -#define S_T6_APADJ 7 -#define V_T6_APADJ(x) ((x) << S_T6_APADJ) -#define F_T6_APADJ V_T6_APADJ(1U) - -#define S_T6_RSEL 6 -#define V_T6_RSEL(x) ((x) << S_T6_RSEL) -#define F_T6_RSEL V_T6_RSEL(1U) - -#define S_T6_PHOFFS 0 -#define M_T6_PHOFFS 0x3fU -#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS) -#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS) - #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320 - -#define S_T6_SPIFMT 8 -#define M_T6_SPIFMT 0xfU -#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT) -#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT) - #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c - -#define S_T6_WRAPSEL 15 -#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL) -#define F_T6_WRAPSEL V_T6_WRAPSEL(1U) - -#define S_T6_PEAK 9 -#define M_T6_PEAK 0x1fU -#define V_T6_PEAK(x) ((x) << S_T6_PEAK) -#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK) - #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330 - -#define S_T6_T5VGAIN 0 -#define M_T6_T5VGAIN 0x7fU -#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN) -#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN) - #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338 @@ -54515,12 +66914,6 @@ #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374 - -#define S_T6_ODEC 0 -#define M_T6_ODEC 0xfU -#define V_T6_ODEC(x) ((x) << S_T6_ODEC) -#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC) - #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378 #define S_RX_LINKB_ACCCMP_RIS 11 @@ -54550,20 +66943,6 @@ #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac - -#define S_T6_EMMD 3 -#define M_T6_EMMD 0x3U -#define V_T6_EMMD(x) ((x) << S_T6_EMMD) -#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD) - -#define S_T6_EMBRDY 2 -#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY) -#define F_T6_EMBRDY V_T6_EMBRDY(1U) - -#define S_T6_EMBUMP 1 -#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP) -#define F_T6_EMBUMP V_T6_EMBUMP(1U) - #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8 @@ -54611,103 +66990,21 @@ #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400 - -#define S_T6_T5_TX_RXLOOP 5 -#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP) -#define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U) - -#define S_T6_T5_TX_BWSEL 2 -#define M_T6_T5_TX_BWSEL 0x3U -#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL) -#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404 - -#define S_T6_ERROR 9 -#define V_T6_ERROR(x) ((x) << S_T6_ERROR) -#define F_T6_ERROR V_T6_ERROR(1U) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418 - -#define S_T6_CALSSTN 8 -#define M_T6_CALSSTN 0x3fU -#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN) -#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN) - -#define S_T6_CALSSTP 0 -#define M_T6_CALSSTP 0x3fU -#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP) -#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c - -#define S_T6_DRTOL 2 -#define M_T6_DRTOL 0x7U -#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL) -#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420 - -#define S_T6_NXTT0 0 -#define M_T6_NXTT0 0x3fU -#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0) -#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428 - -#define S_T6_NXTT2 0 -#define M_T6_NXTT2 0x3fU -#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2) -#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434 - -#define S_T6_NXTPOL 0 -#define M_T6_NXTPOL 0xfU -#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL) -#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438 - -#define S_T6_C0UPDT 6 -#define M_T6_C0UPDT 0x3U -#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT) -#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT) - -#define S_T6_C2UPDT 2 -#define M_T6_C2UPDT 0x3U -#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT) -#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT) - -#define S_T6_C1UPDT 0 -#define M_T6_C1UPDT 0x3U -#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT) -#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c - -#define S_T6_C0STAT 6 -#define M_T6_C0STAT 0x3U -#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT) -#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT) - -#define S_T6_C2STAT 2 -#define M_T6_C2STAT 0x3U -#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT) -#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT) - -#define S_T6_C1STAT 0 -#define M_T6_C1STAT 0x3U -#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT) -#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444 @@ -54730,12 +67027,6 @@ #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c - -#define S_T6_XADDR 1 -#define M_T6_XADDR 0x1fU -#define V_T6_XADDR(x) ((x) << S_T6_XADDR) -#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488 @@ -54748,21 +67039,6 @@ #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0 -#define S_T6_DCCTIMEEN 13 -#define M_T6_DCCTIMEEN 0x3U -#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN) -#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN) - -#define S_T6_DCCLOCK 11 -#define M_T6_DCCLOCK 0x3U -#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK) -#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK) - -#define S_T6_DCCOFFSET 8 -#define M_T6_DCCOFFSET 0x7U -#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET) -#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET) - #define S_TX_LINKC_DCCSTEP_CTL 6 #define M_TX_LINKC_DCCSTEP_CTL 0x3U #define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL) @@ -54780,118 +67056,25 @@ #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0 - -#define S_T6_SDOVRD 0 -#define M_T6_SDOVRD 0xffffU -#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD) -#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc - -#define S_T6_SDOVRDEN 15 -#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN) -#define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500 - -#define S_T6_T5_TX_RXLOOP 5 -#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP) -#define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U) - -#define S_T6_T5_TX_BWSEL 2 -#define M_T6_T5_TX_BWSEL 0x3U -#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL) -#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504 - -#define S_T6_ERROR 9 -#define V_T6_ERROR(x) ((x) << S_T6_ERROR) -#define F_T6_ERROR V_T6_ERROR(1U) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518 - -#define S_T6_CALSSTN 8 -#define M_T6_CALSSTN 0x3fU -#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN) -#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN) - -#define S_T6_CALSSTP 0 -#define M_T6_CALSSTP 0x3fU -#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP) -#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c - -#define S_T6_DRTOL 2 -#define M_T6_DRTOL 0x7U -#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL) -#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520 - -#define S_T6_NXTT0 0 -#define M_T6_NXTT0 0x3fU -#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0) -#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528 - -#define S_T6_NXTT2 0 -#define M_T6_NXTT2 0x3fU -#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2) -#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534 - -#define S_T6_NXTPOL 0 -#define M_T6_NXTPOL 0xfU -#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL) -#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538 - -#define S_T6_C0UPDT 6 -#define M_T6_C0UPDT 0x3U -#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT) -#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT) - -#define S_T6_C2UPDT 2 -#define M_T6_C2UPDT 0x3U -#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT) -#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT) - -#define S_T6_C1UPDT 0 -#define M_T6_C1UPDT 0x3U -#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT) -#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c - -#define S_T6_C0STAT 6 -#define M_T6_C0STAT 0x3U -#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT) -#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT) - -#define S_T6_C2STAT 2 -#define M_T6_C2STAT 0x3U -#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT) -#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT) - -#define S_T6_C1STAT 0 -#define M_T6_C1STAT 0x3U -#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT) -#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544 @@ -54914,12 +67097,6 @@ #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c - -#define S_T6_XADDR 1 -#define M_T6_XADDR 0x1fU -#define V_T6_XADDR(x) ((x) << S_T6_XADDR) -#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588 @@ -54932,21 +67109,6 @@ #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0 -#define S_T6_DCCTIMEEN 13 -#define M_T6_DCCTIMEEN 0x3U -#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN) -#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN) - -#define S_T6_DCCLOCK 11 -#define M_T6_DCCLOCK 0x3U -#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK) -#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK) - -#define S_T6_DCCOFFSET 8 -#define M_T6_DCCOFFSET 0x7U -#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET) -#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET) - #define S_TX_LINKD_DCCSTEP_CTL 6 #define M_TX_LINKD_DCCSTEP_CTL 0x3U #define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL) @@ -54964,74 +67126,22 @@ #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0 - -#define S_T6_SDOVRD 0 -#define M_T6_SDOVRD 0xffffU -#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD) -#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc - -#define S_T6_SDOVRDEN 15 -#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN) -#define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U) - #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c - -#define S_T6_TMSCAL 8 -#define M_T6_TMSCAL 0x3U -#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL) -#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL) - -#define S_T6_APADJ 7 -#define V_T6_APADJ(x) ((x) << S_T6_APADJ) -#define F_T6_APADJ V_T6_APADJ(1U) - -#define S_T6_RSEL 6 -#define V_T6_RSEL(x) ((x) << S_T6_RSEL) -#define F_T6_RSEL V_T6_RSEL(1U) - -#define S_T6_PHOFFS 0 -#define M_T6_PHOFFS 0x3fU -#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS) -#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS) - #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620 - -#define S_T6_SPIFMT 8 -#define M_T6_SPIFMT 0xfU -#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT) -#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT) - #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c - -#define S_T6_WRAPSEL 15 -#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL) -#define F_T6_WRAPSEL V_T6_WRAPSEL(1U) - -#define S_T6_PEAK 9 -#define M_T6_PEAK 0x1fU -#define V_T6_PEAK(x) ((x) << S_T6_PEAK) -#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK) - #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630 - -#define S_T6_T5VGAIN 0 -#define M_T6_T5VGAIN 0x7fU -#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN) -#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN) - #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638 @@ -55055,12 +67165,6 @@ #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674 - -#define S_T6_ODEC 0 -#define M_T6_ODEC 0xfU -#define V_T6_ODEC(x) ((x) << S_T6_ODEC) -#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC) - #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678 #define S_RX_LINKC_ACCCMP_RIS 11 @@ -55090,20 +67194,6 @@ #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac - -#define S_T6_EMMD 3 -#define M_T6_EMMD 0x3U -#define V_T6_EMMD(x) ((x) << S_T6_EMMD) -#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD) - -#define S_T6_EMBRDY 2 -#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY) -#define F_T6_EMBRDY V_T6_EMBRDY(1U) - -#define S_T6_EMBUMP 1 -#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP) -#define F_T6_EMBUMP V_T6_EMBUMP(1U) - #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8 @@ -55154,56 +67244,15 @@ #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c - -#define S_T6_TMSCAL 8 -#define M_T6_TMSCAL 0x3U -#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL) -#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL) - -#define S_T6_APADJ 7 -#define V_T6_APADJ(x) ((x) << S_T6_APADJ) -#define F_T6_APADJ V_T6_APADJ(1U) - -#define S_T6_RSEL 6 -#define V_T6_RSEL(x) ((x) << S_T6_RSEL) -#define F_T6_RSEL V_T6_RSEL(1U) - -#define S_T6_PHOFFS 0 -#define M_T6_PHOFFS 0x3fU -#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS) -#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS) - #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720 - -#define S_T6_SPIFMT 8 -#define M_T6_SPIFMT 0xfU -#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT) -#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT) - #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c - -#define S_T6_WRAPSEL 15 -#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL) -#define F_T6_WRAPSEL V_T6_WRAPSEL(1U) - -#define S_T6_PEAK 9 -#define M_T6_PEAK 0x1fU -#define V_T6_PEAK(x) ((x) << S_T6_PEAK) -#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK) - #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730 - -#define S_T6_T5VGAIN 0 -#define M_T6_T5VGAIN 0x7fU -#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN) -#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN) - #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738 @@ -55227,12 +67276,6 @@ #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774 - -#define S_T6_ODEC 0 -#define M_T6_ODEC 0xfU -#define V_T6_ODEC(x) ((x) << S_T6_ODEC) -#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC) - #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778 #define S_RX_LINKD_ACCCMP_RIS 11 @@ -55262,20 +67305,6 @@ #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac - -#define S_T6_EMMD 3 -#define M_T6_EMMD 0x3U -#define V_T6_EMMD(x) ((x) << S_T6_EMMD) -#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD) - -#define S_T6_EMBRDY 2 -#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY) -#define F_T6_EMBRDY V_T6_EMBRDY(1U) - -#define S_T6_EMBUMP 1 -#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP) -#define F_T6_EMBUMP V_T6_EMBUMP(1U) - #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8 @@ -55597,103 +67626,21 @@ #define F_MACROTEST V_MACROTEST(1U) #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900 - -#define S_T6_T5_TX_RXLOOP 5 -#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP) -#define F_T6_T5_TX_RXLOOP V_T6_T5_TX_RXLOOP(1U) - -#define S_T6_T5_TX_BWSEL 2 -#define M_T6_T5_TX_BWSEL 0x3U -#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL) -#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904 - -#define S_T6_ERROR 9 -#define V_T6_ERROR(x) ((x) << S_T6_ERROR) -#define F_T6_ERROR V_T6_ERROR(1U) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918 - -#define S_T6_CALSSTN 8 -#define M_T6_CALSSTN 0x3fU -#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN) -#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN) - -#define S_T6_CALSSTP 0 -#define M_T6_CALSSTP 0x3fU -#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP) -#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c - -#define S_T6_DRTOL 2 -#define M_T6_DRTOL 0x7U -#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL) -#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920 - -#define S_T6_NXTT0 0 -#define M_T6_NXTT0 0x3fU -#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0) -#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928 - -#define S_T6_NXTT2 0 -#define M_T6_NXTT2 0x3fU -#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2) -#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934 - -#define S_T6_NXTPOL 0 -#define M_T6_NXTPOL 0xfU -#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL) -#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938 - -#define S_T6_C0UPDT 6 -#define M_T6_C0UPDT 0x3U -#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT) -#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT) - -#define S_T6_C2UPDT 2 -#define M_T6_C2UPDT 0x3U -#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT) -#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT) - -#define S_T6_C1UPDT 0 -#define M_T6_C1UPDT 0x3U -#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT) -#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c - -#define S_T6_C0STAT 6 -#define M_T6_C0STAT 0x3U -#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT) -#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT) - -#define S_T6_C2STAT 2 -#define M_T6_C2STAT 0x3U -#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT) -#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT) - -#define S_T6_C1STAT 0 -#define M_T6_C1STAT 0x3U -#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT) -#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944 @@ -55716,12 +67663,6 @@ #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c - -#define S_T6_XADDR 1 -#define M_T6_XADDR 0x1fU -#define V_T6_XADDR(x) ((x) << S_T6_XADDR) -#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988 @@ -55734,21 +67675,6 @@ #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0 -#define S_T6_DCCTIMEEN 13 -#define M_T6_DCCTIMEEN 0x3U -#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN) -#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN) - -#define S_T6_DCCLOCK 11 -#define M_T6_DCCLOCK 0x3U -#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK) -#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK) - -#define S_T6_DCCOFFSET 8 -#define M_T6_DCCOFFSET 0x7U -#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET) -#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET) - #define S_TX_LINK_BCST_DCCSTEP_CTL 6 #define M_TX_LINK_BCST_DCCSTEP_CTL 0x3U #define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL) @@ -55766,74 +67692,22 @@ #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0 - -#define S_T6_SDOVRD 0 -#define M_T6_SDOVRD 0xffffU -#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD) -#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc - -#define S_T6_SDOVRDEN 15 -#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN) -#define F_T6_SDOVRDEN V_T6_SDOVRDEN(1U) - #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c - -#define S_T6_TMSCAL 8 -#define M_T6_TMSCAL 0x3U -#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL) -#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL) - -#define S_T6_APADJ 7 -#define V_T6_APADJ(x) ((x) << S_T6_APADJ) -#define F_T6_APADJ V_T6_APADJ(1U) - -#define S_T6_RSEL 6 -#define V_T6_RSEL(x) ((x) << S_T6_RSEL) -#define F_T6_RSEL V_T6_RSEL(1U) - -#define S_T6_PHOFFS 0 -#define M_T6_PHOFFS 0x3fU -#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS) -#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS) - #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20 - -#define S_T6_SPIFMT 8 -#define M_T6_SPIFMT 0xfU -#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT) -#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT) - #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c - -#define S_T6_WRAPSEL 15 -#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL) -#define F_T6_WRAPSEL V_T6_WRAPSEL(1U) - -#define S_T6_PEAK 9 -#define M_T6_PEAK 0x1fU -#define V_T6_PEAK(x) ((x) << S_T6_PEAK) -#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK) - #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30 - -#define S_T6_T5VGAIN 0 -#define M_T6_T5VGAIN 0x7fU -#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN) -#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN) - #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38 @@ -55857,12 +67731,6 @@ #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74 - -#define S_T6_ODEC 0 -#define M_T6_ODEC 0xfU -#define V_T6_ODEC(x) ((x) << S_T6_ODEC) -#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC) - #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78 #define S_RX_LINK_BCST_ACCCMP_RIS 11 @@ -55892,20 +67760,6 @@ #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac - -#define S_T6_EMMD 3 -#define M_T6_EMMD 0x3U -#define V_T6_EMMD(x) ((x) << S_T6_EMMD) -#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD) - -#define S_T6_EMBRDY 2 -#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY) -#define F_T6_EMBRDY V_T6_EMBRDY(1U) - -#define S_T6_EMBUMP 1 -#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP) -#define F_T6_EMBUMP V_T6_EMBUMP(1U) - #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8 @@ -56304,17 +68158,6 @@ #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10 - -#define S_T6_C0MAX 8 -#define M_T6_C0MAX 0x7fU -#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX) -#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX) - -#define S_T6_C0MIN 0 -#define M_T6_C0MIN 0x7fU -#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN) -#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 @@ -56323,17 +68166,6 @@ #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30 - -#define S_T6_C2MAX 8 -#define M_T6_C2MAX 0x7fU -#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX) -#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX) - -#define S_T6_C2MIN 0 -#define M_T6_C2MIN 0x7fU -#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN) -#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN) - #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 @@ -56349,17 +68181,6 @@ #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10 - -#define S_T6_C0MAX 8 -#define M_T6_C0MAX 0x7fU -#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX) -#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX) - -#define S_T6_C0MIN 0 -#define M_T6_C0MIN 0x7fU -#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN) -#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 @@ -56368,17 +68189,6 @@ #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30 - -#define S_T6_C2MAX 8 -#define M_T6_C2MAX 0x7fU -#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX) -#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX) - -#define S_T6_C2MIN 0 -#define M_T6_C2MIN 0x7fU -#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN) -#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN) - #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 @@ -56394,17 +68204,6 @@ #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10 - -#define S_T6_C0MAX 8 -#define M_T6_C0MAX 0x7fU -#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX) -#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX) - -#define S_T6_C0MIN 0 -#define M_T6_C0MIN 0x7fU -#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN) -#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 @@ -56413,17 +68212,6 @@ #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30 - -#define S_T6_C2MAX 8 -#define M_T6_C2MAX 0x7fU -#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX) -#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX) - -#define S_T6_C2MIN 0 -#define M_T6_C2MIN 0x7fU -#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN) -#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN) - #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 @@ -56439,17 +68227,6 @@ #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10 - -#define S_T6_C0MAX 8 -#define M_T6_C0MAX 0x7fU -#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX) -#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX) - -#define S_T6_C0MIN 0 -#define M_T6_C0MIN 0x7fU -#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN) -#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 @@ -56458,17 +68235,6 @@ #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30 - -#define S_T6_C2MAX 8 -#define M_T6_C2MAX 0x7fU -#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX) -#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX) - -#define S_T6_C2MIN 0 -#define M_T6_C2MIN 0x7fU -#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN) -#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN) - #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 @@ -56639,17 +68405,6 @@ #define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN) #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04 - -#define S_T6_H1OSN 13 -#define M_T6_H1OSN 0x7U -#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN) -#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN) - -#define S_T6_H1OMAG 8 -#define M_T6_H1OMAG 0x1fU -#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG) -#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG) - #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10 @@ -56668,17 +68423,6 @@ #define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN) #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04 - -#define S_T6_H1OSN 13 -#define M_T6_H1OSN 0x7U -#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN) -#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN) - -#define S_T6_H1OMAG 8 -#define M_T6_H1OMAG 0x1fU -#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG) -#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG) - #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10 @@ -56697,17 +68441,6 @@ #define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN) #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04 - -#define S_T6_H1OSN 13 -#define M_T6_H1OSN 0x7U -#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN) -#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN) - -#define S_T6_H1OMAG 8 -#define M_T6_H1OMAG 0x1fU -#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG) -#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG) - #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10 @@ -56726,17 +68459,6 @@ #define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN) #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204 - -#define S_T6_H1OSN 13 -#define M_T6_H1OSN 0x7U -#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN) -#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN) - -#define S_T6_H1OMAG 8 -#define M_T6_H1OMAG 0x1fU -#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG) -#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG) - #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210 @@ -57294,69 +69016,21 @@ #define G_BANK(x) (((x) >> S_BANK) & M_BANK) #define A_MC_LMC_INITSEQ1 0x40148 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD1 0x4014c #define A_MC_LMC_INITSEQ2 0x40150 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD2 0x40154 #define A_MC_LMC_INITSEQ3 0x40158 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD3 0x4015c #define A_MC_LMC_INITSEQ4 0x40160 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD4 0x40164 #define A_MC_LMC_INITSEQ5 0x40168 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD5 0x4016c #define A_MC_LMC_INITSEQ6 0x40170 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD6 0x40174 #define A_MC_LMC_INITSEQ7 0x40178 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD7 0x4017c #define A_MC_UPCTL_ECCCFG 0x40180 #define A_MC_LMC_INITSEQ8 0x40180 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_UPCTL_ECCTST 0x40184 #define S_ECC_TEST_MASK0 0 @@ -57367,61 +69041,19 @@ #define A_MC_LMC_CMD8 0x40184 #define A_MC_UPCTL_ECCCLR 0x40188 #define A_MC_LMC_INITSEQ9 0x40188 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_UPCTL_ECCLOG 0x4018c #define A_MC_LMC_CMD9 0x4018c #define A_MC_LMC_INITSEQ10 0x40190 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD10 0x40194 #define A_MC_LMC_INITSEQ11 0x40198 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD11 0x4019c #define A_MC_LMC_INITSEQ12 0x401a0 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD12 0x401a4 #define A_MC_LMC_INITSEQ13 0x401a8 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD13 0x401ac #define A_MC_LMC_INITSEQ14 0x401b0 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD14 0x401b4 #define A_MC_LMC_INITSEQ15 0x401b8 - -#define S_T6_RANK 0 -#define M_T6_RANK 0xfU -#define V_T6_RANK(x) ((x) << S_T6_RANK) -#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK) - #define A_MC_LMC_CMD15 0x401bc #define A_MC_UPCTL_DTUWACTL 0x40200 @@ -61990,6 +73622,11 @@ #define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES) #define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES) +#define S_DRAMREFENABLE 27 +#define M_DRAMREFENABLE 0x3U +#define V_DRAMREFENABLE(x) ((x) << S_DRAMREFENABLE) +#define G_DRAMREFENABLE(x) (((x) >> S_DRAMREFENABLE) & M_DRAMREFENABLE) + #define A_EDC_H_DBG_MA_CMD_INTF 0x50300 #define S_MCMDADDR 12 @@ -62372,12 +74009,51 @@ #define V_REFCNT(x) ((x) << S_REFCNT) #define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT) +#define A_EDC_H_PAR_CAUSE 0x50404 + +#define S_STG_CMDQ_PARERR_CAUSE 7 +#define V_STG_CMDQ_PARERR_CAUSE(x) ((x) << S_STG_CMDQ_PARERR_CAUSE) +#define F_STG_CMDQ_PARERR_CAUSE V_STG_CMDQ_PARERR_CAUSE(1U) + +#define S_STG_WRDQ_PARERR_CAUSE 6 +#define V_STG_WRDQ_PARERR_CAUSE(x) ((x) << S_STG_WRDQ_PARERR_CAUSE) +#define F_STG_WRDQ_PARERR_CAUSE V_STG_WRDQ_PARERR_CAUSE(1U) + +#define S_INP_CMDQ_PARERR_CAUSE 5 +#define V_INP_CMDQ_PARERR_CAUSE(x) ((x) << S_INP_CMDQ_PARERR_CAUSE) +#define F_INP_CMDQ_PARERR_CAUSE V_INP_CMDQ_PARERR_CAUSE(1U) + +#define S_INP_WRDQ_PARERR_CAUSE 4 +#define V_INP_WRDQ_PARERR_CAUSE(x) ((x) << S_INP_WRDQ_PARERR_CAUSE) +#define F_INP_WRDQ_PARERR_CAUSE V_INP_WRDQ_PARERR_CAUSE(1U) + +#define S_INP_BEQ_PARERR_CAUSE 3 +#define V_INP_BEQ_PARERR_CAUSE(x) ((x) << S_INP_BEQ_PARERR_CAUSE) +#define F_INP_BEQ_PARERR_CAUSE V_INP_BEQ_PARERR_CAUSE(1U) + +#define S_ECC_CE_PAR_ENABLE_CAUSE 2 +#define V_ECC_CE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_CE_PAR_ENABLE_CAUSE) +#define F_ECC_CE_PAR_ENABLE_CAUSE V_ECC_CE_PAR_ENABLE_CAUSE(1U) + +#define S_ECC_UE_PAR_ENABLE_CAUSE 1 +#define V_ECC_UE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_UE_PAR_ENABLE_CAUSE) +#define F_ECC_UE_PAR_ENABLE_CAUSE V_ECC_UE_PAR_ENABLE_CAUSE(1U) + +#define S_RDDQ_PARERR_CAUSE 0 +#define V_RDDQ_PARERR_CAUSE(x) ((x) << S_RDDQ_PARERR_CAUSE) +#define F_RDDQ_PARERR_CAUSE V_RDDQ_PARERR_CAUSE(1U) + /* registers for module EDC_T61 */ #define EDC_T61_BASE_ADDR 0x50800 /* registers for module HMA_T6 */ #define HMA_T6_BASE_ADDR 0x51000 +#define S_T7_CLIENT_EN 0 +#define M_T7_CLIENT_EN 0x7fffU +#define V_T7_CLIENT_EN(x) ((x) << S_T7_CLIENT_EN) +#define G_T7_CLIENT_EN(x) (((x) >> S_T7_CLIENT_EN) & M_T7_CLIENT_EN) + #define S_TPH 12 #define M_TPH 0x3U #define V_TPH(x) ((x) << S_TPH) @@ -62398,6 +74074,14 @@ #define V_OP_MODE(x) ((x) << S_OP_MODE) #define F_OP_MODE V_OP_MODE(1U) +#define S_GK_ENABLE 30 +#define V_GK_ENABLE(x) ((x) << S_GK_ENABLE) +#define F_GK_ENABLE V_GK_ENABLE(1U) + +#define S_DBGCNTRST 29 +#define V_DBGCNTRST(x) ((x) << S_DBGCNTRST) +#define F_DBGCNTRST V_DBGCNTRST(1U) + #define A_HMA_TLB_ACCESS 0x51028 #define S_INV_ALL 29 @@ -62437,6 +74121,11 @@ #define V_REGION(x) ((x) << S_REGION) #define G_REGION(x) (((x) >> S_REGION) & M_REGION) +#define S_T7_VA 8 +#define M_T7_VA 0xffffffU +#define V_T7_VA(x) ((x) << S_T7_VA) +#define G_T7_VA(x) (((x) >> S_T7_VA) & M_T7_VA) + #define A_HMA_TLB_DESC_0_H 0x51030 #define A_HMA_TLB_DESC_0_L 0x51034 #define A_HMA_TLB_DESC_1_H 0x51038 @@ -62460,6 +74149,11 @@ #define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN) #define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN) +#define S_REG0MINADDR0MIN 8 +#define M_REG0MINADDR0MIN 0xffffffU +#define V_REG0MINADDR0MIN(x) ((x) << S_REG0MINADDR0MIN) +#define G_REG0MINADDR0MIN(x) (((x) >> S_REG0MINADDR0MIN) & M_REG0MINADDR0MIN) + #define A_HMA_REG0_MAX 0x51074 #define S_ADDR0_MAX 12 @@ -62467,6 +74161,11 @@ #define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX) #define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX) +#define S_REG0MAXADDR0MAX 8 +#define M_REG0MAXADDR0MAX 0xffffffU +#define V_REG0MAXADDR0MAX(x) ((x) << S_REG0MAXADDR0MAX) +#define G_REG0MAXADDR0MAX(x) (((x) >> S_REG0MAXADDR0MAX) & M_REG0MAXADDR0MAX) + #define A_HMA_REG0_MASK 0x51078 #define S_PAGE_SIZE0 12 @@ -62475,6 +74174,7 @@ #define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0) #define A_HMA_REG0_BASE 0x5107c +#define A_HMA_REG0_BASE_LSB 0x5107c #define A_HMA_REG1_MIN 0x51080 #define S_ADDR1_MIN 12 @@ -62482,6 +74182,11 @@ #define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN) #define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN) +#define S_REG1MINADDR1MIN 8 +#define M_REG1MINADDR1MIN 0xffffffU +#define V_REG1MINADDR1MIN(x) ((x) << S_REG1MINADDR1MIN) +#define G_REG1MINADDR1MIN(x) (((x) >> S_REG1MINADDR1MIN) & M_REG1MINADDR1MIN) + #define A_HMA_REG1_MAX 0x51084 #define S_ADDR1_MAX 12 @@ -62489,6 +74194,11 @@ #define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX) #define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX) +#define S_REG1MAXADDR1MAX 8 +#define M_REG1MAXADDR1MAX 0xffffffU +#define V_REG1MAXADDR1MAX(x) ((x) << S_REG1MAXADDR1MAX) +#define G_REG1MAXADDR1MAX(x) (((x) >> S_REG1MAXADDR1MAX) & M_REG1MAXADDR1MAX) + #define A_HMA_REG1_MASK 0x51088 #define S_PAGE_SIZE1 12 @@ -62497,6 +74207,7 @@ #define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1) #define A_HMA_REG1_BASE 0x5108c +#define A_HMA_REG1_BASE_LSB 0x5108c #define A_HMA_REG2_MIN 0x51090 #define S_ADDR2_MIN 12 @@ -62504,6 +74215,11 @@ #define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN) #define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN) +#define S_REG2MINADDR2MIN 8 +#define M_REG2MINADDR2MIN 0xffffffU +#define V_REG2MINADDR2MIN(x) ((x) << S_REG2MINADDR2MIN) +#define G_REG2MINADDR2MIN(x) (((x) >> S_REG2MINADDR2MIN) & M_REG2MINADDR2MIN) + #define A_HMA_REG2_MAX 0x51094 #define S_ADDR2_MAX 12 @@ -62511,6 +74227,11 @@ #define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX) #define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX) +#define S_REG2MAXADDR2MAX 8 +#define M_REG2MAXADDR2MAX 0xffffffU +#define V_REG2MAXADDR2MAX(x) ((x) << S_REG2MAXADDR2MAX) +#define G_REG2MAXADDR2MAX(x) (((x) >> S_REG2MAXADDR2MAX) & M_REG2MAXADDR2MAX) + #define A_HMA_REG2_MASK 0x51098 #define S_PAGE_SIZE2 12 @@ -62519,6 +74240,7 @@ #define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2) #define A_HMA_REG2_BASE 0x5109c +#define A_HMA_REG2_BASE_LSB 0x5109c #define A_HMA_REG3_MIN 0x510a0 #define S_ADDR3_MIN 12 @@ -62526,6 +74248,11 @@ #define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN) #define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN) +#define S_REG3MINADDR3MIN 8 +#define M_REG3MINADDR3MIN 0xffffffU +#define V_REG3MINADDR3MIN(x) ((x) << S_REG3MINADDR3MIN) +#define G_REG3MINADDR3MIN(x) (((x) >> S_REG3MINADDR3MIN) & M_REG3MINADDR3MIN) + #define A_HMA_REG3_MAX 0x510a4 #define S_ADDR3_MAX 12 @@ -62533,6 +74260,11 @@ #define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX) #define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX) +#define S_REG3MAXADDR3MAX 8 +#define M_REG3MAXADDR3MAX 0xffffffU +#define V_REG3MAXADDR3MAX(x) ((x) << S_REG3MAXADDR3MAX) +#define G_REG3MAXADDR3MAX(x) (((x) >> S_REG3MAXADDR3MAX) & M_REG3MAXADDR3MAX) + #define A_HMA_REG3_MASK 0x510a8 #define S_PAGE_SIZE3 12 @@ -62541,6 +74273,7 @@ #define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3) #define A_HMA_REG3_BASE 0x510ac +#define A_HMA_REG3_BASE_LSB 0x510ac #define A_HMA_SW_SYNC 0x510b0 #define S_ENTER_SYNC 31 @@ -62551,6 +74284,84 @@ #define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC) #define F_EXIT_SYNC V_EXIT_SYNC(1U) +#define A_HMA_GC_MODE_SEL 0x510b4 + +#define S_MODE_SEL 8 +#define M_MODE_SEL 0x3U +#define V_MODE_SEL(x) ((x) << S_MODE_SEL) +#define G_MODE_SEL(x) (((x) >> S_MODE_SEL) & M_MODE_SEL) + +#define S_FLUSH_REQ 4 +#define V_FLUSH_REQ(x) ((x) << S_FLUSH_REQ) +#define F_FLUSH_REQ V_FLUSH_REQ(1U) + +#define S_CLEAR_REQ 0 +#define V_CLEAR_REQ(x) ((x) << S_CLEAR_REQ) +#define F_CLEAR_REQ V_CLEAR_REQ(1U) + +#define A_HMA_REG0_BASE_MSB 0x510b8 + +#define S_BASE0_MSB 0 +#define M_BASE0_MSB 0xfU +#define V_BASE0_MSB(x) ((x) << S_BASE0_MSB) +#define G_BASE0_MSB(x) (((x) >> S_BASE0_MSB) & M_BASE0_MSB) + +#define A_HMA_REG1_BASE_MSB 0x510bc + +#define S_BASE1_MSB 0 +#define M_BASE1_MSB 0xfU +#define V_BASE1_MSB(x) ((x) << S_BASE1_MSB) +#define G_BASE1_MSB(x) (((x) >> S_BASE1_MSB) & M_BASE1_MSB) + +#define A_HMA_REG2_BASE_MSB 0x510c0 + +#define S_BASE2_MSB 0 +#define M_BASE2_MSB 0xfU +#define V_BASE2_MSB(x) ((x) << S_BASE2_MSB) +#define G_BASE2_MSB(x) (((x) >> S_BASE2_MSB) & M_BASE2_MSB) + +#define A_HMA_REG3_BASE_MSB 0x510c4 + +#define S_BASE3_MSB 0 +#define M_BASE3_MSB 0xfU +#define V_BASE3_MSB(x) ((x) << S_BASE3_MSB) +#define G_BASE3_MSB(x) (((x) >> S_BASE3_MSB) & M_BASE3_MSB) + +#define A_HMA_DBG_CTL 0x51104 +#define A_HMA_DBG_DATA 0x51108 +#define A_HMA_H_BIST_CMD 0x51200 +#define A_HMA_H_BIST_CMD_ADDR 0x51204 +#define A_HMA_H_BIST_CMD_LEN 0x51208 +#define A_HMA_H_BIST_DATA_PATTERN 0x5120c +#define A_HMA_H_BIST_USER_WDATA0 0x51210 +#define A_HMA_H_BIST_USER_WDATA1 0x51214 +#define A_HMA_H_BIST_USER_WDATA2 0x51218 +#define A_HMA_H_BIST_NUM_ERR 0x5121c +#define A_HMA_H_BIST_ERR_FIRST_ADDR 0x51220 +#define A_HMA_H_BIST_STATUS_RDATA 0x51224 +#define A_HMA_H_BIST_CRC_SEED 0x5126c +#define A_HMA_TABLE_LINE1_MSB 0x51270 + +#define S_STARTA 0 +#define M_STARTA 0xfU +#define V_STARTA(x) ((x) << S_STARTA) +#define G_STARTA(x) (((x) >> S_STARTA) & M_STARTA) + +#define A_HMA_TABLE_LINE2_MSB 0x51274 + +#define S_ENDA 0 +#define M_ENDA 0xfU +#define V_ENDA(x) ((x) << S_ENDA) +#define G_ENDA(x) (((x) >> S_ENDA) & M_ENDA) + +#define S_GK_UF_PAR_ENABLE 6 +#define V_GK_UF_PAR_ENABLE(x) ((x) << S_GK_UF_PAR_ENABLE) +#define F_GK_UF_PAR_ENABLE V_GK_UF_PAR_ENABLE(1U) + +#define S_PCIEMST_PAR_ENABLE 2 +#define V_PCIEMST_PAR_ENABLE(x) ((x) << S_PCIEMST_PAR_ENABLE) +#define F_PCIEMST_PAR_ENABLE V_PCIEMST_PAR_ENABLE(1U) + #define S_IDTF_INT_ENABLE 5 #define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE) #define F_IDTF_INT_ENABLE V_IDTF_INT_ENABLE(1U) @@ -62571,6 +74382,10 @@ #define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE) #define F_MAMST_INT_ENABLE V_MAMST_INT_ENABLE(1U) +#define S_GK_UF_INT_ENABLE 6 +#define V_GK_UF_INT_ENABLE(x) ((x) << S_GK_UF_INT_ENABLE) +#define F_GK_UF_INT_ENABLE V_GK_UF_INT_ENABLE(1U) + #define S_IDTF_INT_CAUSE 5 #define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE) #define F_IDTF_INT_CAUSE V_IDTF_INT_CAUSE(1U) @@ -62591,6 +74406,10 @@ #define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE) #define F_MAMST_INT_CAUSE V_MAMST_INT_CAUSE(1U) +#define S_GK_UF_INT_CAUSE 6 +#define V_GK_UF_INT_CAUSE(x) ((x) << S_GK_UF_INT_CAUSE) +#define F_GK_UF_INT_CAUSE V_GK_UF_INT_CAUSE(1U) + #define A_HMA_MA_MST_ERR 0x5130c #define A_HMA_RTF_ERR 0x51310 #define A_HMA_OTF_ERR 0x51314 @@ -62904,3 +74723,12365 @@ #define M_RD_EOP_CNT 0xffU #define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT) #define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT) + +#define S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT 16 +#define M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT 0xffU +#define V_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT) +#define G_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT) + +#define S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT 8 +#define M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT 0xffU +#define V_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT) +#define G_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT) + +#define S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT 0 +#define M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT 0xffU +#define V_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT) +#define G_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT) + +/* registers for module MAC_T7 */ +#define MAC_T7_BASE_ADDR 0x38000 + +#define S_T7_PORT_MAP 21 +#define M_T7_PORT_MAP 0x7U +#define V_T7_PORT_MAP(x) ((x) << S_T7_PORT_MAP) +#define G_T7_PORT_MAP(x) (((x) >> S_T7_PORT_MAP) & M_T7_PORT_MAP) + +#define S_T7_SMUX_RX_LOOP 17 +#define M_T7_SMUX_RX_LOOP 0xfU +#define V_T7_SMUX_RX_LOOP(x) ((x) << S_T7_SMUX_RX_LOOP) +#define G_T7_SMUX_RX_LOOP(x) (((x) >> S_T7_SMUX_RX_LOOP) & M_T7_SMUX_RX_LOOP) + +#define S_T7_SIGNAL_DET 15 +#define V_T7_SIGNAL_DET(x) ((x) << S_T7_SIGNAL_DET) +#define F_T7_SIGNAL_DET V_T7_SIGNAL_DET(1U) + +#define S_CFG_MAC_2_MPS_FULL 13 +#define V_CFG_MAC_2_MPS_FULL(x) ((x) << S_CFG_MAC_2_MPS_FULL) +#define F_CFG_MAC_2_MPS_FULL V_CFG_MAC_2_MPS_FULL(1U) + +#define S_MPS_FULL_SEL 12 +#define V_MPS_FULL_SEL(x) ((x) << S_MPS_FULL_SEL) +#define F_MPS_FULL_SEL V_MPS_FULL_SEL(1U) + +#define S_T7_SMUXTXSEL 8 +#define M_T7_SMUXTXSEL 0xfU +#define V_T7_SMUXTXSEL(x) ((x) << S_T7_SMUXTXSEL) +#define G_T7_SMUXTXSEL(x) (((x) >> S_T7_SMUXTXSEL) & M_T7_SMUXTXSEL) + +#define S_T7_PORTSPEED 4 +#define M_T7_PORTSPEED 0xfU +#define V_T7_PORTSPEED(x) ((x) << S_T7_PORTSPEED) +#define G_T7_PORTSPEED(x) (((x) >> S_T7_PORTSPEED) & M_T7_PORTSPEED) + +#define S_MTIP_REG_RESET 25 +#define V_MTIP_REG_RESET(x) ((x) << S_MTIP_REG_RESET) +#define F_MTIP_REG_RESET V_MTIP_REG_RESET(1U) + +#define S_RESET_REG_CLK_I 24 +#define V_RESET_REG_CLK_I(x) ((x) << S_RESET_REG_CLK_I) +#define F_RESET_REG_CLK_I V_RESET_REG_CLK_I(1U) + +#define S_T7_LED1_CFG1 15 +#define M_T7_LED1_CFG1 0x7U +#define V_T7_LED1_CFG1(x) ((x) << S_T7_LED1_CFG1) +#define G_T7_LED1_CFG1(x) (((x) >> S_T7_LED1_CFG1) & M_T7_LED1_CFG1) + +#define S_T7_LED0_CFG1 12 +#define M_T7_LED0_CFG1 0x7U +#define V_T7_LED0_CFG1(x) ((x) << S_T7_LED0_CFG1) +#define G_T7_LED0_CFG1(x) (((x) >> S_T7_LED0_CFG1) & M_T7_LED0_CFG1) + +#define A_T7_MAC_PORT_MAGIC_MACID_LO 0x820 +#define A_T7_MAC_PORT_MAGIC_MACID_HI 0x824 +#define A_T7_MAC_PORT_LINK_STATUS 0x828 + +#define S_EGR_SE_CNT_ERR 9 +#define V_EGR_SE_CNT_ERR(x) ((x) << S_EGR_SE_CNT_ERR) +#define F_EGR_SE_CNT_ERR V_EGR_SE_CNT_ERR(1U) + +#define S_INGR_SE_CNT_ERR 8 +#define V_INGR_SE_CNT_ERR(x) ((x) << S_INGR_SE_CNT_ERR) +#define F_INGR_SE_CNT_ERR V_INGR_SE_CNT_ERR(1U) + +#define A_T7_MAC_PORT_PERR_INT_EN_100G 0x82c + +#define S_PERR_PCSR_FDM_3 21 +#define V_PERR_PCSR_FDM_3(x) ((x) << S_PERR_PCSR_FDM_3) +#define F_PERR_PCSR_FDM_3 V_PERR_PCSR_FDM_3(1U) + +#define S_PERR_PCSR_FDM_2 20 +#define V_PERR_PCSR_FDM_2(x) ((x) << S_PERR_PCSR_FDM_2) +#define F_PERR_PCSR_FDM_2 V_PERR_PCSR_FDM_2(1U) + +#define S_PERR_PCSR_FDM_1 19 +#define V_PERR_PCSR_FDM_1(x) ((x) << S_PERR_PCSR_FDM_1) +#define F_PERR_PCSR_FDM_1 V_PERR_PCSR_FDM_1(1U) + +#define S_PERR_PCSR_FDM_0 18 +#define V_PERR_PCSR_FDM_0(x) ((x) << S_PERR_PCSR_FDM_0) +#define F_PERR_PCSR_FDM_0 V_PERR_PCSR_FDM_0(1U) + +#define S_PERR_PCSR_FM_3 17 +#define V_PERR_PCSR_FM_3(x) ((x) << S_PERR_PCSR_FM_3) +#define F_PERR_PCSR_FM_3 V_PERR_PCSR_FM_3(1U) + +#define S_PERR_PCSR_FM_2 16 +#define V_PERR_PCSR_FM_2(x) ((x) << S_PERR_PCSR_FM_2) +#define F_PERR_PCSR_FM_2 V_PERR_PCSR_FM_2(1U) + +#define S_PERR_PCSR_FM_1 15 +#define V_PERR_PCSR_FM_1(x) ((x) << S_PERR_PCSR_FM_1) +#define F_PERR_PCSR_FM_1 V_PERR_PCSR_FM_1(1U) + +#define S_PERR_PCSR_FM_0 14 +#define V_PERR_PCSR_FM_0(x) ((x) << S_PERR_PCSR_FM_0) +#define F_PERR_PCSR_FM_0 V_PERR_PCSR_FM_0(1U) + +#define S_PERR_PCSR_DM_1 13 +#define V_PERR_PCSR_DM_1(x) ((x) << S_PERR_PCSR_DM_1) +#define F_PERR_PCSR_DM_1 V_PERR_PCSR_DM_1(1U) + +#define S_PERR_PCSR_DM_0 12 +#define V_PERR_PCSR_DM_0(x) ((x) << S_PERR_PCSR_DM_0) +#define F_PERR_PCSR_DM_0 V_PERR_PCSR_DM_0(1U) + +#define S_PERR_PCSR_DK_3 11 +#define V_PERR_PCSR_DK_3(x) ((x) << S_PERR_PCSR_DK_3) +#define F_PERR_PCSR_DK_3 V_PERR_PCSR_DK_3(1U) + +#define S_PERR_PCSR_DK_2 10 +#define V_PERR_PCSR_DK_2(x) ((x) << S_PERR_PCSR_DK_2) +#define F_PERR_PCSR_DK_2 V_PERR_PCSR_DK_2(1U) + +#define S_PERR_PCSR_DK_1 9 +#define V_PERR_PCSR_DK_1(x) ((x) << S_PERR_PCSR_DK_1) +#define F_PERR_PCSR_DK_1 V_PERR_PCSR_DK_1(1U) + +#define S_PERR_PCSR_DK_0 8 +#define V_PERR_PCSR_DK_0(x) ((x) << S_PERR_PCSR_DK_0) +#define F_PERR_PCSR_DK_0 V_PERR_PCSR_DK_0(1U) + +#define S_PERR_F91RO_1 7 +#define V_PERR_F91RO_1(x) ((x) << S_PERR_F91RO_1) +#define F_PERR_F91RO_1 V_PERR_F91RO_1(1U) + +#define S_PERR_F91RO_0 6 +#define V_PERR_F91RO_0(x) ((x) << S_PERR_F91RO_0) +#define F_PERR_F91RO_0 V_PERR_F91RO_0(1U) + +#define S_PERR_PCSR_F91DM 5 +#define V_PERR_PCSR_F91DM(x) ((x) << S_PERR_PCSR_F91DM) +#define F_PERR_PCSR_F91DM V_PERR_PCSR_F91DM(1U) + +#define S_PERR_PCSR_F91TI 4 +#define V_PERR_PCSR_F91TI(x) ((x) << S_PERR_PCSR_F91TI) +#define F_PERR_PCSR_F91TI V_PERR_PCSR_F91TI(1U) + +#define S_PERR_PCSR_F91TO 3 +#define V_PERR_PCSR_F91TO(x) ((x) << S_PERR_PCSR_F91TO) +#define F_PERR_PCSR_F91TO V_PERR_PCSR_F91TO(1U) + +#define S_PERR_PCSR_F91M 2 +#define V_PERR_PCSR_F91M(x) ((x) << S_PERR_PCSR_F91M) +#define F_PERR_PCSR_F91M V_PERR_PCSR_F91M(1U) + +#define S_PERR_PCSR_80_16_1 1 +#define V_PERR_PCSR_80_16_1(x) ((x) << S_PERR_PCSR_80_16_1) +#define F_PERR_PCSR_80_16_1 V_PERR_PCSR_80_16_1(1U) + +#define S_PERR_PCSR_80_16_0 0 +#define V_PERR_PCSR_80_16_0(x) ((x) << S_PERR_PCSR_80_16_0) +#define F_PERR_PCSR_80_16_0 V_PERR_PCSR_80_16_0(1U) + +#define A_T7_MAC_PORT_PERR_INT_CAUSE_100G 0x830 +#define A_T7_MAC_PORT_PERR_ENABLE_100G 0x834 +#define A_MAC_PORT_MAC10G100G_CONFIG_0 0x838 + +#define S_PEER_DELAY_VAL 31 +#define V_PEER_DELAY_VAL(x) ((x) << S_PEER_DELAY_VAL) +#define F_PEER_DELAY_VAL V_PEER_DELAY_VAL(1U) + +#define S_PEER_DELAY 1 +#define M_PEER_DELAY 0x3fffffffU +#define V_PEER_DELAY(x) ((x) << S_PEER_DELAY) +#define G_PEER_DELAY(x) (((x) >> S_PEER_DELAY) & M_PEER_DELAY) + +#define S_MODE1S_ENA 0 +#define V_MODE1S_ENA(x) ((x) << S_MODE1S_ENA) +#define F_MODE1S_ENA V_MODE1S_ENA(1U) + +#define A_MAC_PORT_MAC10G100G_CONFIG_1 0x83c + +#define S_TX_STOP 25 +#define V_TX_STOP(x) ((x) << S_TX_STOP) +#define F_TX_STOP V_TX_STOP(1U) + +#define S_T7_MODE1S_ENA 24 +#define V_T7_MODE1S_ENA(x) ((x) << S_T7_MODE1S_ENA) +#define F_T7_MODE1S_ENA V_T7_MODE1S_ENA(1U) + +#define S_TX_TS_ID 12 +#define M_TX_TS_ID 0xfffU +#define V_TX_TS_ID(x) ((x) << S_TX_TS_ID) +#define G_TX_TS_ID(x) (((x) >> S_TX_TS_ID) & M_TX_TS_ID) + +#define S_T7_TX_LI_FAULT 11 +#define V_T7_TX_LI_FAULT(x) ((x) << S_T7_TX_LI_FAULT) +#define F_T7_TX_LI_FAULT V_T7_TX_LI_FAULT(1U) + +#define S_XOFF_GEN 3 +#define M_XOFF_GEN 0xffU +#define V_XOFF_GEN(x) ((x) << S_XOFF_GEN) +#define G_XOFF_GEN(x) (((x) >> S_XOFF_GEN) & M_XOFF_GEN) + +#define S_TX_REM_FAULT 1 +#define V_TX_REM_FAULT(x) ((x) << S_TX_REM_FAULT) +#define F_TX_REM_FAULT V_TX_REM_FAULT(1U) + +#define S_TX_LOC_FAULT 0 +#define V_TX_LOC_FAULT(x) ((x) << S_TX_LOC_FAULT) +#define F_TX_LOC_FAULT V_TX_LOC_FAULT(1U) + +#define A_MAC_PORT_MAC10G100G_CONFIG_2 0x840 + +#define S_FF_TX_RX_TS_NS 0 +#define M_FF_TX_RX_TS_NS 0x3fffffffU +#define V_FF_TX_RX_TS_NS(x) ((x) << S_FF_TX_RX_TS_NS) +#define G_FF_TX_RX_TS_NS(x) (((x) >> S_FF_TX_RX_TS_NS) & M_FF_TX_RX_TS_NS) + +#define A_MAC_PORT_MAC10G100G_STATUS 0x844 + +#define S_REG_LOWP 21 +#define V_REG_LOWP(x) ((x) << S_REG_LOWP) +#define F_REG_LOWP V_REG_LOWP(1U) + +#define S_LI_FAULT 20 +#define V_LI_FAULT(x) ((x) << S_LI_FAULT) +#define F_LI_FAULT V_LI_FAULT(1U) + +#define S_TX_ISIDLE 19 +#define V_TX_ISIDLE(x) ((x) << S_TX_ISIDLE) +#define F_TX_ISIDLE V_TX_ISIDLE(1U) + +#define S_TX_UNDERFLOW 18 +#define V_TX_UNDERFLOW(x) ((x) << S_TX_UNDERFLOW) +#define F_TX_UNDERFLOW V_TX_UNDERFLOW(1U) + +#define S_T7_TX_EMPTY 17 +#define V_T7_TX_EMPTY(x) ((x) << S_T7_TX_EMPTY) +#define F_T7_TX_EMPTY V_T7_TX_EMPTY(1U) + +#define S_T7_1_REM_FAULT 16 +#define V_T7_1_REM_FAULT(x) ((x) << S_T7_1_REM_FAULT) +#define F_T7_1_REM_FAULT V_T7_1_REM_FAULT(1U) + +#define S_REG_TS_AVAIL 15 +#define V_REG_TS_AVAIL(x) ((x) << S_REG_TS_AVAIL) +#define F_REG_TS_AVAIL V_REG_TS_AVAIL(1U) + +#define S_T7_PHY_TXENA 14 +#define V_T7_PHY_TXENA(x) ((x) << S_T7_PHY_TXENA) +#define F_T7_PHY_TXENA V_T7_PHY_TXENA(1U) + +#define S_T7_PFC_MODE 13 +#define V_T7_PFC_MODE(x) ((x) << S_T7_PFC_MODE) +#define F_T7_PFC_MODE V_T7_PFC_MODE(1U) + +#define S_PAUSE_ON 5 +#define M_PAUSE_ON 0xffU +#define V_PAUSE_ON(x) ((x) << S_PAUSE_ON) +#define G_PAUSE_ON(x) (((x) >> S_PAUSE_ON) & M_PAUSE_ON) + +#define S_MAC_PAUSE_EN 4 +#define V_MAC_PAUSE_EN(x) ((x) << S_MAC_PAUSE_EN) +#define F_MAC_PAUSE_EN V_MAC_PAUSE_EN(1U) + +#define S_MAC_ENABLE 3 +#define V_MAC_ENABLE(x) ((x) << S_MAC_ENABLE) +#define F_MAC_ENABLE V_MAC_ENABLE(1U) + +#define S_LOOP_ENA 2 +#define V_LOOP_ENA(x) ((x) << S_LOOP_ENA) +#define F_LOOP_ENA V_LOOP_ENA(1U) + +#define S_LOC_FAULT 1 +#define V_LOC_FAULT(x) ((x) << S_LOC_FAULT) +#define F_LOC_FAULT V_LOC_FAULT(1U) + +#define S_FF_RX_EMPTY 0 +#define V_FF_RX_EMPTY(x) ((x) << S_FF_RX_EMPTY) +#define F_FF_RX_EMPTY V_FF_RX_EMPTY(1U) + +#define A_MAC_PORT_MAC_AN_STATE_STATUS0 0x848 + +#define S_AN_VAL_AN 15 +#define V_AN_VAL_AN(x) ((x) << S_AN_VAL_AN) +#define F_AN_VAL_AN V_AN_VAL_AN(1U) + +#define S_AN_TR_DIS_STATUS_AN 14 +#define V_AN_TR_DIS_STATUS_AN(x) ((x) << S_AN_TR_DIS_STATUS_AN) +#define F_AN_TR_DIS_STATUS_AN V_AN_TR_DIS_STATUS_AN(1U) + +#define S_AN_STATUS_AN 13 +#define V_AN_STATUS_AN(x) ((x) << S_AN_STATUS_AN) +#define F_AN_STATUS_AN V_AN_STATUS_AN(1U) + +#define S_AN_SELECT_AN 8 +#define M_AN_SELECT_AN 0x1fU +#define V_AN_SELECT_AN(x) ((x) << S_AN_SELECT_AN) +#define G_AN_SELECT_AN(x) (((x) >> S_AN_SELECT_AN) & M_AN_SELECT_AN) + +#define S_AN_RS_FEC_ENA_AN 7 +#define V_AN_RS_FEC_ENA_AN(x) ((x) << S_AN_RS_FEC_ENA_AN) +#define F_AN_RS_FEC_ENA_AN V_AN_RS_FEC_ENA_AN(1U) + +#define S_AN_INT_AN 6 +#define V_AN_INT_AN(x) ((x) << S_AN_INT_AN) +#define F_AN_INT_AN V_AN_INT_AN(1U) + +#define S_AN_FEC_ENA_AN 5 +#define V_AN_FEC_ENA_AN(x) ((x) << S_AN_FEC_ENA_AN) +#define F_AN_FEC_ENA_AN V_AN_FEC_ENA_AN(1U) + +#define S_AN_DONE_AN 4 +#define V_AN_DONE_AN(x) ((x) << S_AN_DONE_AN) +#define F_AN_DONE_AN V_AN_DONE_AN(1U) + +#define S_AN_STATE 0 +#define M_AN_STATE 0xfU +#define V_AN_STATE(x) ((x) << S_AN_STATE) +#define G_AN_STATE(x) (((x) >> S_AN_STATE) & M_AN_STATE) + +#define A_MAC_PORT_MAC_AN_STATE_STATUS1 0x84c +#define A_T7_MAC_PORT_EPIO_DATA0 0x850 +#define A_T7_MAC_PORT_EPIO_DATA1 0x854 +#define A_T7_MAC_PORT_EPIO_DATA2 0x858 +#define A_T7_MAC_PORT_EPIO_DATA3 0x85c +#define A_T7_MAC_PORT_EPIO_OP 0x860 +#define A_T7_MAC_PORT_WOL_STATUS 0x864 +#define A_T7_MAC_PORT_INT_EN 0x868 + +#define S_MAC2MPS_PERR 31 +#define V_MAC2MPS_PERR(x) ((x) << S_MAC2MPS_PERR) +#define F_MAC2MPS_PERR V_MAC2MPS_PERR(1U) + +#define S_MAC_PPS_INT_EN 30 +#define V_MAC_PPS_INT_EN(x) ((x) << S_MAC_PPS_INT_EN) +#define F_MAC_PPS_INT_EN V_MAC_PPS_INT_EN(1U) + +#define S_MAC_TX_TS_AVAIL_INT_EN 29 +#define V_MAC_TX_TS_AVAIL_INT_EN(x) ((x) << S_MAC_TX_TS_AVAIL_INT_EN) +#define F_MAC_TX_TS_AVAIL_INT_EN V_MAC_TX_TS_AVAIL_INT_EN(1U) + +#define S_MAC_SINGLE_ALARM_INT_EN 28 +#define V_MAC_SINGLE_ALARM_INT_EN(x) ((x) << S_MAC_SINGLE_ALARM_INT_EN) +#define F_MAC_SINGLE_ALARM_INT_EN V_MAC_SINGLE_ALARM_INT_EN(1U) + +#define S_MAC_PERIODIC_ALARM_INT_EN 27 +#define V_MAC_PERIODIC_ALARM_INT_EN(x) ((x) << S_MAC_PERIODIC_ALARM_INT_EN) +#define F_MAC_PERIODIC_ALARM_INT_EN V_MAC_PERIODIC_ALARM_INT_EN(1U) + +#define S_MAC_PATDETWAKE_INT_EN 26 +#define V_MAC_PATDETWAKE_INT_EN(x) ((x) << S_MAC_PATDETWAKE_INT_EN) +#define F_MAC_PATDETWAKE_INT_EN V_MAC_PATDETWAKE_INT_EN(1U) + +#define S_MAC_MAGIC_WAKE_INT_EN 25 +#define V_MAC_MAGIC_WAKE_INT_EN(x) ((x) << S_MAC_MAGIC_WAKE_INT_EN) +#define F_MAC_MAGIC_WAKE_INT_EN V_MAC_MAGIC_WAKE_INT_EN(1U) + +#define S_MAC_SIGDETCHG_INT_EN 24 +#define V_MAC_SIGDETCHG_INT_EN(x) ((x) << S_MAC_SIGDETCHG_INT_EN) +#define F_MAC_SIGDETCHG_INT_EN V_MAC_SIGDETCHG_INT_EN(1U) + +#define S_MAC_PCS_LINK_GOOD_EN 12 +#define V_MAC_PCS_LINK_GOOD_EN(x) ((x) << S_MAC_PCS_LINK_GOOD_EN) +#define F_MAC_PCS_LINK_GOOD_EN V_MAC_PCS_LINK_GOOD_EN(1U) + +#define S_MAC_PCS_LINK_FAIL_EN 11 +#define V_MAC_PCS_LINK_FAIL_EN(x) ((x) << S_MAC_PCS_LINK_FAIL_EN) +#define F_MAC_PCS_LINK_FAIL_EN V_MAC_PCS_LINK_FAIL_EN(1U) + +#define S_MAC_OVRFLOW_INT_EN 10 +#define V_MAC_OVRFLOW_INT_EN(x) ((x) << S_MAC_OVRFLOW_INT_EN) +#define F_MAC_OVRFLOW_INT_EN V_MAC_OVRFLOW_INT_EN(1U) + +#define S_MAC_REM_FAULT_INT_EN 7 +#define V_MAC_REM_FAULT_INT_EN(x) ((x) << S_MAC_REM_FAULT_INT_EN) +#define F_MAC_REM_FAULT_INT_EN V_MAC_REM_FAULT_INT_EN(1U) + +#define S_MAC_LOC_FAULT_INT_EN 6 +#define V_MAC_LOC_FAULT_INT_EN(x) ((x) << S_MAC_LOC_FAULT_INT_EN) +#define F_MAC_LOC_FAULT_INT_EN V_MAC_LOC_FAULT_INT_EN(1U) + +#define S_MAC_LINK_DOWN_INT_EN 5 +#define V_MAC_LINK_DOWN_INT_EN(x) ((x) << S_MAC_LINK_DOWN_INT_EN) +#define F_MAC_LINK_DOWN_INT_EN V_MAC_LINK_DOWN_INT_EN(1U) + +#define S_MAC_LINK_UP_INT_EN 4 +#define V_MAC_LINK_UP_INT_EN(x) ((x) << S_MAC_LINK_UP_INT_EN) +#define F_MAC_LINK_UP_INT_EN V_MAC_LINK_UP_INT_EN(1U) + +#define S_MAC_AN_DONE_INT_EN 3 +#define V_MAC_AN_DONE_INT_EN(x) ((x) << S_MAC_AN_DONE_INT_EN) +#define F_MAC_AN_DONE_INT_EN V_MAC_AN_DONE_INT_EN(1U) + +#define S_MAC_AN_PGRD_INT_EN 2 +#define V_MAC_AN_PGRD_INT_EN(x) ((x) << S_MAC_AN_PGRD_INT_EN) +#define F_MAC_AN_PGRD_INT_EN V_MAC_AN_PGRD_INT_EN(1U) + +#define S_MAC_TXFIFO_ERR_INT_EN 1 +#define V_MAC_TXFIFO_ERR_INT_EN(x) ((x) << S_MAC_TXFIFO_ERR_INT_EN) +#define F_MAC_TXFIFO_ERR_INT_EN V_MAC_TXFIFO_ERR_INT_EN(1U) + +#define S_MAC_RXFIFO_ERR_INT_EN 0 +#define V_MAC_RXFIFO_ERR_INT_EN(x) ((x) << S_MAC_RXFIFO_ERR_INT_EN) +#define F_MAC_RXFIFO_ERR_INT_EN V_MAC_RXFIFO_ERR_INT_EN(1U) + +#define A_T7_MAC_PORT_INT_CAUSE 0x86c + +#define S_MAC2MPS_PERR_CAUSE 31 +#define V_MAC2MPS_PERR_CAUSE(x) ((x) << S_MAC2MPS_PERR_CAUSE) +#define F_MAC2MPS_PERR_CAUSE V_MAC2MPS_PERR_CAUSE(1U) + +#define S_MAC_PPS_INT_CAUSE 30 +#define V_MAC_PPS_INT_CAUSE(x) ((x) << S_MAC_PPS_INT_CAUSE) +#define F_MAC_PPS_INT_CAUSE V_MAC_PPS_INT_CAUSE(1U) + +#define S_MAC_TX_TS_AVAIL_INT_CAUSE 29 +#define V_MAC_TX_TS_AVAIL_INT_CAUSE(x) ((x) << S_MAC_TX_TS_AVAIL_INT_CAUSE) +#define F_MAC_TX_TS_AVAIL_INT_CAUSE V_MAC_TX_TS_AVAIL_INT_CAUSE(1U) + +#define S_MAC_SINGLE_ALARM_INT_CAUSE 28 +#define V_MAC_SINGLE_ALARM_INT_CAUSE(x) ((x) << S_MAC_SINGLE_ALARM_INT_CAUSE) +#define F_MAC_SINGLE_ALARM_INT_CAUSE V_MAC_SINGLE_ALARM_INT_CAUSE(1U) + +#define S_MAC_PERIODIC_ALARM_INT_CAUSE 27 +#define V_MAC_PERIODIC_ALARM_INT_CAUSE(x) ((x) << S_MAC_PERIODIC_ALARM_INT_CAUSE) +#define F_MAC_PERIODIC_ALARM_INT_CAUSE V_MAC_PERIODIC_ALARM_INT_CAUSE(1U) + +#define S_MAC_PATDETWAKE_INT_CAUSE 26 +#define V_MAC_PATDETWAKE_INT_CAUSE(x) ((x) << S_MAC_PATDETWAKE_INT_CAUSE) +#define F_MAC_PATDETWAKE_INT_CAUSE V_MAC_PATDETWAKE_INT_CAUSE(1U) + +#define S_MAC_MAGIC_WAKE_INT_CAUSE 25 +#define V_MAC_MAGIC_WAKE_INT_CAUSE(x) ((x) << S_MAC_MAGIC_WAKE_INT_CAUSE) +#define F_MAC_MAGIC_WAKE_INT_CAUSE V_MAC_MAGIC_WAKE_INT_CAUSE(1U) + +#define S_MAC_SIGDETCHG_INT_CAUSE 24 +#define V_MAC_SIGDETCHG_INT_CAUSE(x) ((x) << S_MAC_SIGDETCHG_INT_CAUSE) +#define F_MAC_SIGDETCHG_INT_CAUSE V_MAC_SIGDETCHG_INT_CAUSE(1U) + +#define S_MAC_PCS_LINK_GOOD_CAUSE 12 +#define V_MAC_PCS_LINK_GOOD_CAUSE(x) ((x) << S_MAC_PCS_LINK_GOOD_CAUSE) +#define F_MAC_PCS_LINK_GOOD_CAUSE V_MAC_PCS_LINK_GOOD_CAUSE(1U) + +#define S_MAC_PCS_LINK_FAIL_CAUSE 11 +#define V_MAC_PCS_LINK_FAIL_CAUSE(x) ((x) << S_MAC_PCS_LINK_FAIL_CAUSE) +#define F_MAC_PCS_LINK_FAIL_CAUSE V_MAC_PCS_LINK_FAIL_CAUSE(1U) + +#define S_MAC_OVRFLOW_INT_CAUSE 10 +#define V_MAC_OVRFLOW_INT_CAUSE(x) ((x) << S_MAC_OVRFLOW_INT_CAUSE) +#define F_MAC_OVRFLOW_INT_CAUSE V_MAC_OVRFLOW_INT_CAUSE(1U) + +#define S_MAC_REM_FAULT_INT_CAUSE 7 +#define V_MAC_REM_FAULT_INT_CAUSE(x) ((x) << S_MAC_REM_FAULT_INT_CAUSE) +#define F_MAC_REM_FAULT_INT_CAUSE V_MAC_REM_FAULT_INT_CAUSE(1U) + +#define S_MAC_LOC_FAULT_INT_CAUSE 6 +#define V_MAC_LOC_FAULT_INT_CAUSE(x) ((x) << S_MAC_LOC_FAULT_INT_CAUSE) +#define F_MAC_LOC_FAULT_INT_CAUSE V_MAC_LOC_FAULT_INT_CAUSE(1U) + +#define S_MAC_LINK_DOWN_INT_CAUSE 5 +#define V_MAC_LINK_DOWN_INT_CAUSE(x) ((x) << S_MAC_LINK_DOWN_INT_CAUSE) +#define F_MAC_LINK_DOWN_INT_CAUSE V_MAC_LINK_DOWN_INT_CAUSE(1U) + +#define S_MAC_LINK_UP_INT_CAUSE 4 +#define V_MAC_LINK_UP_INT_CAUSE(x) ((x) << S_MAC_LINK_UP_INT_CAUSE) +#define F_MAC_LINK_UP_INT_CAUSE V_MAC_LINK_UP_INT_CAUSE(1U) + +#define S_MAC_AN_DONE_INT_CAUSE 3 +#define V_MAC_AN_DONE_INT_CAUSE(x) ((x) << S_MAC_AN_DONE_INT_CAUSE) +#define F_MAC_AN_DONE_INT_CAUSE V_MAC_AN_DONE_INT_CAUSE(1U) + +#define S_MAC_AN_PGRD_INT_CAUSE 2 +#define V_MAC_AN_PGRD_INT_CAUSE(x) ((x) << S_MAC_AN_PGRD_INT_CAUSE) +#define F_MAC_AN_PGRD_INT_CAUSE V_MAC_AN_PGRD_INT_CAUSE(1U) + +#define S_MAC_TXFIFO_ERR_INT_CAUSE 1 +#define V_MAC_TXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_TXFIFO_ERR_INT_CAUSE) +#define F_MAC_TXFIFO_ERR_INT_CAUSE V_MAC_TXFIFO_ERR_INT_CAUSE(1U) + +#define S_MAC_RXFIFO_ERR_INT_CAUSE 0 +#define V_MAC_RXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_RXFIFO_ERR_INT_CAUSE) +#define F_MAC_RXFIFO_ERR_INT_CAUSE V_MAC_RXFIFO_ERR_INT_CAUSE(1U) + +#define A_T7_MAC_PORT_PERR_INT_EN 0x870 +#define A_T7_MAC_PORT_PERR_INT_CAUSE 0x874 +#define A_T7_MAC_PORT_PERR_ENABLE 0x878 +#define A_T7_MAC_PORT_PERR_INJECT 0x87c + +#define S_T7_MEMSEL_PERR 1 +#define M_T7_MEMSEL_PERR 0xffU +#define V_T7_MEMSEL_PERR(x) ((x) << S_T7_MEMSEL_PERR) +#define G_T7_MEMSEL_PERR(x) (((x) >> S_T7_MEMSEL_PERR) & M_T7_MEMSEL_PERR) + +#define A_T7_MAC_PORT_RUNT_FRAME 0x880 +#define A_T7_MAC_PORT_EEE_STATUS 0x884 +#define A_T7_MAC_PORT_TX_TS_ID 0x888 + +#define S_TS_ID_MSB 3 +#define V_TS_ID_MSB(x) ((x) << S_TS_ID_MSB) +#define F_TS_ID_MSB V_TS_ID_MSB(1U) + +#define A_T7_MAC_PORT_TX_TS_VAL_LO 0x88c +#define A_T7_MAC_PORT_TX_TS_VAL_HI 0x890 +#define A_T7_MAC_PORT_EEE_CTL 0x894 +#define A_T7_MAC_PORT_EEE_TX_CTL 0x898 +#define A_T7_MAC_PORT_EEE_RX_CTL 0x89c +#define A_T7_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x8a0 +#define A_T7_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x8a4 +#define A_T7_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x8a8 +#define A_T7_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x8b8 +#define A_T7_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x8bc +#define A_T7_MAC_PORT_EEE_RX_10G_WF_TIMER 0x8c0 +#define A_T7_MAC_PORT_EEE_WF_COUNT 0x8cc +#define A_MAC_PORT_WOL_EN 0x8d0 + +#define S_WOL_ENABLE 1 +#define V_WOL_ENABLE(x) ((x) << S_WOL_ENABLE) +#define F_WOL_ENABLE V_WOL_ENABLE(1U) + +#define S_WOL_INDICATOR 0 +#define V_WOL_INDICATOR(x) ((x) << S_WOL_INDICATOR) +#define F_WOL_INDICATOR V_WOL_INDICATOR(1U) + +#define A_MAC_PORT_INT_TRACE 0x8d4 + +#define S_INTERRUPT 0 +#define M_INTERRUPT 0x7fffffffU +#define V_INTERRUPT(x) ((x) << S_INTERRUPT) +#define G_INTERRUPT(x) (((x) >> S_INTERRUPT) & M_INTERRUPT) + +#define A_MAC_PORT_TRACE_TS_LO 0x8d8 +#define A_MAC_PORT_TRACE_TS_HI 0x8dc +#define A_MAC_PORT_MTIP_10G100G_REVISION 0x900 + +#define S_VER_10G100G 8 +#define M_VER_10G100G 0xffU +#define V_VER_10G100G(x) ((x) << S_VER_10G100G) +#define G_VER_10G100G(x) (((x) >> S_VER_10G100G) & M_VER_10G100G) + +#define S_REV_10G100G 0 +#define M_REV_10G100G 0xffU +#define V_REV_10G100G(x) ((x) << S_REV_10G100G) +#define G_REV_10G100G(x) (((x) >> S_REV_10G100G) & M_REV_10G100G) + +#define A_MAC_PORT_MTIP_10G100G_SCRATCH 0x904 +#define A_MAC_PORT_MTIP_10G100G_COMMAND_CONFIG 0x908 + +#define S_NO_PREAM 31 +#define V_NO_PREAM(x) ((x) << S_NO_PREAM) +#define F_NO_PREAM V_NO_PREAM(1U) + +#define S_SHORT_PREAM 30 +#define V_SHORT_PREAM(x) ((x) << S_SHORT_PREAM) +#define F_SHORT_PREAM V_SHORT_PREAM(1U) + +#define S_FLT_HDL_DIS 27 +#define V_FLT_HDL_DIS(x) ((x) << S_FLT_HDL_DIS) +#define F_FLT_HDL_DIS V_FLT_HDL_DIS(1U) + +#define S_TX_FIFO_RESET 26 +#define V_TX_FIFO_RESET(x) ((x) << S_TX_FIFO_RESET) +#define F_TX_FIFO_RESET V_TX_FIFO_RESET(1U) + +#define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_0 0x90c +#define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_1 0x910 +#define A_MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU 0x914 +#define A_MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS 0x91c + +#define S_RX10G100G_EMPTY 16 +#define M_RX10G100G_EMPTY 0xffffU +#define V_RX10G100G_EMPTY(x) ((x) << S_RX10G100G_EMPTY) +#define G_RX10G100G_EMPTY(x) (((x) >> S_RX10G100G_EMPTY) & M_RX10G100G_EMPTY) + +#define S_RX10G100G_AVAIL 0 +#define M_RX10G100G_AVAIL 0xffffU +#define V_RX10G100G_AVAIL(x) ((x) << S_RX10G100G_AVAIL) +#define G_RX10G100G_AVAIL(x) (((x) >> S_RX10G100G_AVAIL) & M_RX10G100G_AVAIL) + +#define A_MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS 0x920 + +#define S_TX10G100G_EMPTY 16 +#define M_TX10G100G_EMPTY 0xffffU +#define V_TX10G100G_EMPTY(x) ((x) << S_TX10G100G_EMPTY) +#define G_TX10G100G_EMPTY(x) (((x) >> S_TX10G100G_EMPTY) & M_TX10G100G_EMPTY) + +#define S_TX10G100G_AVAIL 0 +#define M_TX10G100G_AVAIL 0xffffU +#define V_TX10G100G_AVAIL(x) ((x) << S_TX10G100G_AVAIL) +#define G_TX10G100G_AVAIL(x) (((x) >> S_TX10G100G_AVAIL) & M_TX10G100G_AVAIL) + +#define A_MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E 0x924 +#define A_MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E 0x928 +#define A_MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS 0x930 +#define A_MAC_PORT_MTIP_10G100G_MDIO_COMMAND 0x934 +#define A_MAC_PORT_MTIP_10G100G_MDIO_DATA 0x938 +#define A_MAC_PORT_MTIP_10G100G_MDIO_REGADDR 0x93c +#define A_MAC_PORT_MTIP_10G100G_STATUS 0x940 + +#define S_T7_TX_ISIDLE 8 +#define V_T7_TX_ISIDLE(x) ((x) << S_T7_TX_ISIDLE) +#define F_T7_TX_ISIDLE V_T7_TX_ISIDLE(1U) + +#define A_MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH 0x944 + +#define S_IPG_COMP_CNT 16 +#define M_IPG_COMP_CNT 0xffffU +#define V_IPG_COMP_CNT(x) ((x) << S_IPG_COMP_CNT) +#define G_IPG_COMP_CNT(x) (((x) >> S_IPG_COMP_CNT) & M_IPG_COMP_CNT) + +#define S_AVG_IPG_LEN 2 +#define M_AVG_IPG_LEN 0xfU +#define V_AVG_IPG_LEN(x) ((x) << S_AVG_IPG_LEN) +#define G_AVG_IPG_LEN(x) (((x) >> S_AVG_IPG_LEN) & M_AVG_IPG_LEN) + +#define S_DSBL_DIC 0 +#define V_DSBL_DIC(x) ((x) << S_DSBL_DIC) +#define F_DSBL_DIC V_DSBL_DIC(1U) + +#define A_MAC_PORT_MTIP_10G100G_CRC_MODE 0x948 +#define A_MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA 0x954 +#define A_MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA 0x958 +#define A_MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA 0x95c +#define A_MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA 0x960 +#define A_MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH 0x964 +#define A_MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH 0x968 +#define A_MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH 0x96c +#define A_MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH 0x970 +#define A_MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS 0x974 +#define A_MAC_PORT_MTIP_10G100G_TS_TIMESTAMP 0x97c +#define A_MAC_PORT_MTIP_10G100G_XIF_MODE 0x980 + +#define S_RX_CNT_MODE 16 +#define V_RX_CNT_MODE(x) ((x) << S_RX_CNT_MODE) +#define F_RX_CNT_MODE V_RX_CNT_MODE(1U) + +#define S_TS_UPD64_MODE 12 +#define V_TS_UPD64_MODE(x) ((x) << S_TS_UPD64_MODE) +#define F_TS_UPD64_MODE V_TS_UPD64_MODE(1U) + +#define S_TS_BINARY_MODE 11 +#define V_TS_BINARY_MODE(x) ((x) << S_TS_BINARY_MODE) +#define F_TS_BINARY_MODE V_TS_BINARY_MODE(1U) + +#define S_TS_DELAY_MODE 10 +#define V_TS_DELAY_MODE(x) ((x) << S_TS_DELAY_MODE) +#define F_TS_DELAY_MODE V_TS_DELAY_MODE(1U) + +#define S_TS_DELTA_MODE 9 +#define V_TS_DELTA_MODE(x) ((x) << S_TS_DELTA_MODE) +#define F_TS_DELTA_MODE V_TS_DELTA_MODE(1U) + +#define S_TX_MAC_RS_ERR 8 +#define V_TX_MAC_RS_ERR(x) ((x) << S_TX_MAC_RS_ERR) +#define F_TX_MAC_RS_ERR V_TX_MAC_RS_ERR(1U) + +#define S_RX_PAUSE_BYPASS 6 +#define V_RX_PAUSE_BYPASS(x) ((x) << S_RX_PAUSE_BYPASS) +#define F_RX_PAUSE_BYPASS V_RX_PAUSE_BYPASS(1U) + +#define S_ONE_STEP_ENA 5 +#define V_ONE_STEP_ENA(x) ((x) << S_ONE_STEP_ENA) +#define F_ONE_STEP_ENA V_ONE_STEP_ENA(1U) + +#define S_PAUSETIMERX8 4 +#define V_PAUSETIMERX8(x) ((x) << S_PAUSETIMERX8) +#define F_PAUSETIMERX8 V_PAUSETIMERX8(1U) + +#define S_XGMII_ENA 0 +#define V_XGMII_ENA(x) ((x) << S_XGMII_ENA) +#define F_XGMII_ENA V_XGMII_ENA(1U) + +#define A_MAC_PORT_MTIP_CR4_0_CONTROL_1 0xa00 +#define A_MAC_PORT_MTIP_CR4_0_STATUS_1 0xa04 + +#define S_CR4_0_RX_LINK_STATUS 2 +#define V_CR4_0_RX_LINK_STATUS(x) ((x) << S_CR4_0_RX_LINK_STATUS) +#define F_CR4_0_RX_LINK_STATUS V_CR4_0_RX_LINK_STATUS(1U) + +#define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID0 0xa08 + +#define S_CR4_0_DEVICE_ID0 0 +#define M_CR4_0_DEVICE_ID0 0xffffU +#define V_CR4_0_DEVICE_ID0(x) ((x) << S_CR4_0_DEVICE_ID0) +#define G_CR4_0_DEVICE_ID0(x) (((x) >> S_CR4_0_DEVICE_ID0) & M_CR4_0_DEVICE_ID0) + +#define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID1 0xa0c + +#define S_CR4_0_DEVICE_ID1 0 +#define M_CR4_0_DEVICE_ID1 0xffffU +#define V_CR4_0_DEVICE_ID1(x) ((x) << S_CR4_0_DEVICE_ID1) +#define G_CR4_0_DEVICE_ID1(x) (((x) >> S_CR4_0_DEVICE_ID1) & M_CR4_0_DEVICE_ID1) + +#define A_MAC_PORT_MTIP_CR4_0_SPEED_ABILITY 0xa10 + +#define S_50G_CAPABLE 5 +#define V_50G_CAPABLE(x) ((x) << S_50G_CAPABLE) +#define F_50G_CAPABLE V_50G_CAPABLE(1U) + +#define S_25G_CAPABLE 4 +#define V_25G_CAPABLE(x) ((x) << S_25G_CAPABLE) +#define F_25G_CAPABLE V_25G_CAPABLE(1U) + +#define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1 0xa14 +#define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2 0xa18 +#define A_MAC_PORT_MTIP_CR4_0_CONTROL_2 0xa1c + +#define S_T7_PCS_TYPE_SELECTION 0 +#define M_T7_PCS_TYPE_SELECTION 0xfU +#define V_T7_PCS_TYPE_SELECTION(x) ((x) << S_T7_PCS_TYPE_SELECTION) +#define G_T7_PCS_TYPE_SELECTION(x) (((x) >> S_T7_PCS_TYPE_SELECTION) & M_T7_PCS_TYPE_SELECTION) + +#define A_MAC_PORT_MTIP_CR4_0_STATUS_2 0xa20 + +#define S_50GBASE_R_CAPABLE 8 +#define V_50GBASE_R_CAPABLE(x) ((x) << S_50GBASE_R_CAPABLE) +#define F_50GBASE_R_CAPABLE V_50GBASE_R_CAPABLE(1U) + +#define S_25GBASE_R_CAPABLE 7 +#define V_25GBASE_R_CAPABLE(x) ((x) << S_25GBASE_R_CAPABLE) +#define F_25GBASE_R_CAPABLE V_25GBASE_R_CAPABLE(1U) + +#define A_MAC_PORT_MTIP_CR4_0_PKG_ID0 0xa38 +#define A_MAC_PORT_MTIP_CR4_0_PKG_ID1 0xa3c +#define A_MAC_PORT_MTIP_CR4_0_EEE_CTRL 0xa50 + +#define S_50GBASE_R_FW 14 +#define V_50GBASE_R_FW(x) ((x) << S_50GBASE_R_FW) +#define F_50GBASE_R_FW V_50GBASE_R_FW(1U) + +#define S_100GBASE_R_DS 13 +#define V_100GBASE_R_DS(x) ((x) << S_100GBASE_R_DS) +#define F_100GBASE_R_DS V_100GBASE_R_DS(1U) + +#define S_100GBASE_R_FW 12 +#define V_100GBASE_R_FW(x) ((x) << S_100GBASE_R_FW) +#define F_100GBASE_R_FW V_100GBASE_R_FW(1U) + +#define S_25GBASE_R_DS 11 +#define V_25GBASE_R_DS(x) ((x) << S_25GBASE_R_DS) +#define F_25GBASE_R_DS V_25GBASE_R_DS(1U) + +#define S_25GBASE_R_FW 10 +#define V_25GBASE_R_FW(x) ((x) << S_25GBASE_R_FW) +#define F_25GBASE_R_FW V_25GBASE_R_FW(1U) + +#define S_40GBASE_R_DS 9 +#define V_40GBASE_R_DS(x) ((x) << S_40GBASE_R_DS) +#define F_40GBASE_R_DS V_40GBASE_R_DS(1U) + +#define S_40GBASE_R_FW 8 +#define V_40GBASE_R_FW(x) ((x) << S_40GBASE_R_FW) +#define F_40GBASE_R_FW V_40GBASE_R_FW(1U) + +#define S_10GBASE_KE_EEE 6 +#define V_10GBASE_KE_EEE(x) ((x) << S_10GBASE_KE_EEE) +#define F_10GBASE_KE_EEE V_10GBASE_KE_EEE(1U) + +#define S_FAST_WAKE 1 +#define M_FAST_WAKE 0x1fU +#define V_FAST_WAKE(x) ((x) << S_FAST_WAKE) +#define G_FAST_WAKE(x) (((x) >> S_FAST_WAKE) & M_FAST_WAKE) + +#define S_DEEP_SLEEP 0 +#define V_DEEP_SLEEP(x) ((x) << S_DEEP_SLEEP) +#define F_DEEP_SLEEP V_DEEP_SLEEP(1U) + +#define A_MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER 0xa58 + +#define S_WAKE_ERROR_COUNTER 0 +#define M_WAKE_ERROR_COUNTER 0x1ffffU +#define V_WAKE_ERROR_COUNTER(x) ((x) << S_WAKE_ERROR_COUNTER) +#define G_WAKE_ERROR_COUNTER(x) (((x) >> S_WAKE_ERROR_COUNTER) & M_WAKE_ERROR_COUNTER) + +#define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1 0xa80 + +#define S_CR4_0_BR_BLOCK_LOCK 0 +#define V_CR4_0_BR_BLOCK_LOCK(x) ((x) << S_CR4_0_BR_BLOCK_LOCK) +#define F_CR4_0_BR_BLOCK_LOCK V_CR4_0_BR_BLOCK_LOCK(1U) + +#define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2 0xa84 +#define A_MAC_PORT_MTIP_CR4_0_SEED_A_0 0xa88 + +#define S_SEED_A_0 0 +#define M_SEED_A_0 0xffffU +#define V_SEED_A_0(x) ((x) << S_SEED_A_0) +#define G_SEED_A_0(x) (((x) >> S_SEED_A_0) & M_SEED_A_0) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_A_1 0xa8c + +#define S_SEED_A_1 0 +#define M_SEED_A_1 0xffffU +#define V_SEED_A_1(x) ((x) << S_SEED_A_1) +#define G_SEED_A_1(x) (((x) >> S_SEED_A_1) & M_SEED_A_1) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_A_2 0xa90 + +#define S_SEED_A_2 0 +#define M_SEED_A_2 0xffffU +#define V_SEED_A_2(x) ((x) << S_SEED_A_2) +#define G_SEED_A_2(x) (((x) >> S_SEED_A_2) & M_SEED_A_2) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_A_3 0xa94 + +#define S_SEED_A_3 0 +#define M_SEED_A_3 0xffffU +#define V_SEED_A_3(x) ((x) << S_SEED_A_3) +#define G_SEED_A_3(x) (((x) >> S_SEED_A_3) & M_SEED_A_3) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_B_0 0xa98 + +#define S_SEED_B_0 0 +#define M_SEED_B_0 0xffffU +#define V_SEED_B_0(x) ((x) << S_SEED_B_0) +#define G_SEED_B_0(x) (((x) >> S_SEED_B_0) & M_SEED_B_0) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_B_1 0xa9c + +#define S_SEED_B_1 0 +#define M_SEED_B_1 0xffffU +#define V_SEED_B_1(x) ((x) << S_SEED_B_1) +#define G_SEED_B_1(x) (((x) >> S_SEED_B_1) & M_SEED_B_1) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_B_2 0xaa0 + +#define S_SEED_B_2 0 +#define M_SEED_B_2 0xffffU +#define V_SEED_B_2(x) ((x) << S_SEED_B_2) +#define G_SEED_B_2(x) (((x) >> S_SEED_B_2) & M_SEED_B_2) + +#define A_MAC_PORT_MTIP_CR4_0_SEED_B_3 0xaa4 + +#define S_SEED_B_3 0 +#define M_SEED_B_3 0xffffU +#define V_SEED_B_3(x) ((x) << S_SEED_B_3) +#define G_SEED_B_3(x) (((x) >> S_SEED_B_3) & M_SEED_B_3) + +#define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL 0xaa8 + +#define S_TEST_PATTERN_40G 7 +#define V_TEST_PATTERN_40G(x) ((x) << S_TEST_PATTERN_40G) +#define F_TEST_PATTERN_40G V_TEST_PATTERN_40G(1U) + +#define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT 0xaac +#define A_MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT 0xab0 + +#define S_BASE_R_BER_HIGH_ORDER_CNT 0 +#define M_BASE_R_BER_HIGH_ORDER_CNT 0xffffU +#define V_BASE_R_BER_HIGH_ORDER_CNT(x) ((x) << S_BASE_R_BER_HIGH_ORDER_CNT) +#define G_BASE_R_BER_HIGH_ORDER_CNT(x) (((x) >> S_BASE_R_BER_HIGH_ORDER_CNT) & M_BASE_R_BER_HIGH_ORDER_CNT) + +#define A_MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT 0xab4 +#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1 0xac8 +#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2 0xacc +#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3 0xad0 +#define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4 0xad4 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0 0xad8 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1 0xadc +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2 0xae0 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3 0xae4 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4 0xae8 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5 0xaec +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6 0xaf0 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7 0xaf4 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8 0xaf8 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9 0xafc +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10 0xb00 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11 0xb04 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12 0xb08 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13 0xb0c +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14 0xb10 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15 0xb14 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16 0xb18 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17 0xb1c +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18 0xb20 +#define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19 0xb24 +#define A_MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING 0xb28 +#define A_MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING 0xb2c +#define A_MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING 0xb30 +#define A_MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING 0xb34 +#define A_MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING 0xb38 +#define A_MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING 0xb3c +#define A_MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING 0xb40 +#define A_MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING 0xb44 +#define A_MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING 0xb48 +#define A_MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING 0xb4c +#define A_MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING 0xb50 +#define A_MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING 0xb54 +#define A_MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING 0xb58 +#define A_MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING 0xb5c +#define A_MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING 0xb60 +#define A_MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING 0xb64 +#define A_MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING 0xb68 +#define A_MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING 0xb6c +#define A_MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING 0xb70 +#define A_MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING 0xb74 +#define A_MAC_PORT_MTIP_CR4_0_SCRATCH 0xb78 +#define A_MAC_PORT_MTIP_CR4_0_CORE_REVISION 0xb7c +#define A_MAC_PORT_MTIP_CR4_0_VL_INTVL 0xb80 + +#define S_VL_INTCL 0 +#define M_VL_INTCL 0xffffU +#define V_VL_INTCL(x) ((x) << S_VL_INTCL) +#define G_VL_INTCL(x) (((x) >> S_VL_INTCL) & M_VL_INTCL) + +#define A_MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH 0xb84 + +#define S_LANE6_LANE7 12 +#define M_LANE6_LANE7 0xfU +#define V_LANE6_LANE7(x) ((x) << S_LANE6_LANE7) +#define G_LANE6_LANE7(x) (((x) >> S_LANE6_LANE7) & M_LANE6_LANE7) + +#define S_LANE4_LANE5 8 +#define M_LANE4_LANE5 0xfU +#define V_LANE4_LANE5(x) ((x) << S_LANE4_LANE5) +#define G_LANE4_LANE5(x) (((x) >> S_LANE4_LANE5) & M_LANE4_LANE5) + +#define S_LANE2_LANE3 4 +#define M_LANE2_LANE3 0xfU +#define V_LANE2_LANE3(x) ((x) << S_LANE2_LANE3) +#define G_LANE2_LANE3(x) (((x) >> S_LANE2_LANE3) & M_LANE2_LANE3) + +#define S_LANE0_LANE1 0 +#define M_LANE0_LANE1 0xfU +#define V_LANE0_LANE1(x) ((x) << S_LANE0_LANE1) +#define G_LANE0_LANE1(x) (((x) >> S_LANE0_LANE1) & M_LANE0_LANE1) + +#define A_MAC_PORT_MTIP_CR4_0_VL0_0 0xb98 + +#define S_M1 8 +#define M_M1 0xffU +#define V_M1(x) ((x) << S_M1) +#define G_M1(x) (((x) >> S_M1) & M_M1) + +#define S_M0 0 +#define M_M0 0xffU +#define V_M0(x) ((x) << S_M0) +#define G_M0(x) (((x) >> S_M0) & M_M0) + +#define A_MAC_PORT_MTIP_CR4_0_VL0_1 0xb9c + +#define S_M2 0 +#define M_M2 0xffU +#define V_M2(x) ((x) << S_M2) +#define G_M2(x) (((x) >> S_M2) & M_M2) + +#define A_MAC_PORT_MTIP_CR4_0_VL1_0 0xba0 +#define A_MAC_PORT_MTIP_CR4_0_VL1_1 0xba4 +#define A_MAC_PORT_MTIP_CR4_0_VL2_0 0xba8 +#define A_MAC_PORT_MTIP_CR4_0_VL2_1 0xbac +#define A_MAC_PORT_MTIP_CR4_0_VL3_0 0xbb0 +#define A_MAC_PORT_MTIP_CR4_0_VL3_1 0xbb4 +#define A_MAC_PORT_MTIP_CR4_0_PCS_MODE 0xbb8 + +#define S_ST_DISABLE_MLD 9 +#define V_ST_DISABLE_MLD(x) ((x) << S_ST_DISABLE_MLD) +#define F_ST_DISABLE_MLD V_ST_DISABLE_MLD(1U) + +#define S_ST_EN_CLAUSE49 8 +#define V_ST_EN_CLAUSE49(x) ((x) << S_ST_EN_CLAUSE49) +#define F_ST_EN_CLAUSE49 V_ST_EN_CLAUSE49(1U) + +#define S_HI_BER25 2 +#define V_HI_BER25(x) ((x) << S_HI_BER25) +#define F_HI_BER25 V_HI_BER25(1U) + +#define S_DISABLE_MLD 1 +#define V_DISABLE_MLD(x) ((x) << S_DISABLE_MLD) +#define F_DISABLE_MLD V_DISABLE_MLD(1U) + +#define S_ENA_CLAUSE49 0 +#define V_ENA_CLAUSE49(x) ((x) << S_ENA_CLAUSE49) +#define F_ENA_CLAUSE49 V_ENA_CLAUSE49(1U) + +#define A_MAC_PORT_MTIP_CR4_0_VL4_0 0xc98 +#define A_MAC_PORT_MTIP_CR4_0_VL4_1 0xc9c +#define A_MAC_PORT_MTIP_CR4_0_VL5_0 0xca0 +#define A_MAC_PORT_MTIP_CR4_0_VL5_1 0xca4 +#define A_MAC_PORT_MTIP_CR4_0_VL6_0 0xca8 +#define A_MAC_PORT_MTIP_CR4_0_VL6_1 0xcac +#define A_MAC_PORT_MTIP_CR4_0_VL7_0 0xcb0 +#define A_MAC_PORT_MTIP_CR4_0_VL7_1 0xcb4 +#define A_MAC_PORT_MTIP_CR4_0_VL8_0 0xcb8 +#define A_MAC_PORT_MTIP_CR4_0_VL8_1 0xcbc +#define A_MAC_PORT_MTIP_CR4_0_VL9_0 0xcc0 +#define A_MAC_PORT_MTIP_CR4_0_VL9_1 0xcc4 +#define A_MAC_PORT_MTIP_CR4_0_VL10_0 0xcc8 +#define A_MAC_PORT_MTIP_CR4_0_VL10_1 0xccc +#define A_MAC_PORT_MTIP_CR4_0_VL11_0 0xcd0 +#define A_MAC_PORT_MTIP_CR4_0_VL11_1 0xcd4 +#define A_MAC_PORT_MTIP_CR4_0_VL12_0 0xcd8 +#define A_MAC_PORT_MTIP_CR4_0_VL12_1 0xcdc +#define A_MAC_PORT_MTIP_CR4_0_VL13_0 0xce0 +#define A_MAC_PORT_MTIP_CR4_0_VL13_1 0xce4 +#define A_MAC_PORT_MTIP_CR4_0_VL14_0 0xce8 +#define A_MAC_PORT_MTIP_CR4_0_VL14_1 0xcec +#define A_MAC_PORT_MTIP_CR4_0_VL15_0 0xcf0 +#define A_MAC_PORT_MTIP_CR4_0_VL15_1 0xcf4 +#define A_MAC_PORT_MTIP_CR4_0_VL16_0 0xcf8 +#define A_MAC_PORT_MTIP_CR4_0_VL16_1 0xcfc +#define A_MAC_PORT_MTIP_CR4_0_VL17_0 0xd00 +#define A_MAC_PORT_MTIP_CR4_0_VL17_1 0xd04 +#define A_MAC_PORT_MTIP_CR4_0_VL18_0 0xd08 +#define A_MAC_PORT_MTIP_CR4_0_VL18_1 0xd0c +#define A_MAC_PORT_MTIP_CR4_0_VL19_0 0xd10 +#define A_MAC_PORT_MTIP_CR4_0_VL19_1 0xd14 +#define A_MAC_PORT_MTIP_CR4_1_CONTROL_1 0x1000 +#define A_MAC_PORT_MTIP_CR4_1_STATUS_1 0x1004 + +#define S_CR4_RX_LINK_STATUS_1 2 +#define V_CR4_RX_LINK_STATUS_1(x) ((x) << S_CR4_RX_LINK_STATUS_1) +#define F_CR4_RX_LINK_STATUS_1 V_CR4_RX_LINK_STATUS_1(1U) + +#define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID0 0x1008 + +#define S_CR4_1_DEVICE_ID0 0 +#define M_CR4_1_DEVICE_ID0 0xffffU +#define V_CR4_1_DEVICE_ID0(x) ((x) << S_CR4_1_DEVICE_ID0) +#define G_CR4_1_DEVICE_ID0(x) (((x) >> S_CR4_1_DEVICE_ID0) & M_CR4_1_DEVICE_ID0) + +#define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID1 0x100c + +#define S_CR4_1_DEVICE_ID1 0 +#define M_CR4_1_DEVICE_ID1 0xffffU +#define V_CR4_1_DEVICE_ID1(x) ((x) << S_CR4_1_DEVICE_ID1) +#define G_CR4_1_DEVICE_ID1(x) (((x) >> S_CR4_1_DEVICE_ID1) & M_CR4_1_DEVICE_ID1) + +#define A_MAC_PORT_MTIP_CR4_1_SPEED_ABILITY 0x1010 +#define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1 0x1014 +#define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2 0x1018 +#define A_MAC_PORT_MTIP_CR4_1_CONTROL_2 0x101c +#define A_MAC_PORT_MTIP_CR4_1_STATUS_2 0x1020 +#define A_MAC_PORT_MTIP_CR4_1_PKG_ID0 0x1038 +#define A_MAC_PORT_MTIP_CR4_1_PKG_ID1 0x103c +#define A_MAC_PORT_MTIP_CR4_1_EEE_CTRL 0x1050 +#define A_MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER 0x1058 +#define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1 0x1080 + +#define S_CR4_1_BR_BLOCK_LOCK 0 +#define V_CR4_1_BR_BLOCK_LOCK(x) ((x) << S_CR4_1_BR_BLOCK_LOCK) +#define F_CR4_1_BR_BLOCK_LOCK V_CR4_1_BR_BLOCK_LOCK(1U) + +#define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2 0x1084 +#define A_MAC_PORT_MTIP_CR4_1_SEED_A_0 0x1088 +#define A_MAC_PORT_MTIP_CR4_1_SEED_A_1 0x108c +#define A_MAC_PORT_MTIP_CR4_1_SEED_A_2 0x1090 +#define A_MAC_PORT_MTIP_CR4_1_SEED_A_3 0x1094 +#define A_MAC_PORT_MTIP_CR4_1_SEED_B_0 0x1098 +#define A_MAC_PORT_MTIP_CR4_1_SEED_B_1 0x109c +#define A_MAC_PORT_MTIP_CR4_1_SEED_B_2 0x10a0 +#define A_MAC_PORT_MTIP_CR4_1_SEED_B_3 0x10a4 +#define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL 0x10a8 +#define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT 0x10ac +#define A_MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT 0x10b0 +#define A_MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT 0x10b4 +#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1 0x10c8 +#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2 0x10cc +#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3 0x10d0 +#define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4 0x10d4 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0 0x10d8 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1 0x10dc +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2 0x10e0 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3 0x10e4 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4 0x10e8 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5 0x10ec +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6 0x10f0 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7 0x10f4 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8 0x10f8 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9 0x10fc +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10 0x1100 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11 0x1104 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12 0x1108 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13 0x110c +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14 0x1110 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15 0x1114 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16 0x1118 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17 0x111c +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18 0x1120 +#define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19 0x1124 +#define A_MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING 0x1128 +#define A_MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING 0x112c +#define A_MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING 0x1130 +#define A_MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING 0x1134 +#define A_MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING 0x1138 +#define A_MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING 0x113c +#define A_MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING 0x1140 +#define A_MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING 0x1144 +#define A_MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING 0x1148 +#define A_MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING 0x114c +#define A_MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING 0x1150 +#define A_MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING 0x1154 +#define A_MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING 0x1158 +#define A_MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING 0x115c +#define A_MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING 0x1160 +#define A_MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING 0x1164 +#define A_MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING 0x1168 +#define A_MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING 0x116c +#define A_MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING 0x1170 +#define A_MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING 0x1174 +#define A_MAC_PORT_MTIP_CR4_1_SCRATCH 0x1178 +#define A_MAC_PORT_MTIP_CR4_1_CORE_REVISION 0x117c +#define A_MAC_PORT_MTIP_CR4_1_VL_INTVL 0x1180 +#define A_MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH 0x1184 +#define A_MAC_PORT_MTIP_CR4_1_VL0_0 0x1198 +#define A_MAC_PORT_MTIP_CR4_1_VL0_1 0x119c +#define A_MAC_PORT_MTIP_CR4_1_VL1_0 0x11a0 +#define A_MAC_PORT_MTIP_CR4_1_VL1_1 0x11a4 +#define A_MAC_PORT_MTIP_CR4_1_VL2_0 0x11a8 +#define A_MAC_PORT_MTIP_CR4_1_VL2_1 0x11ac +#define A_MAC_PORT_MTIP_CR4_1_VL3_0 0x11b0 +#define A_MAC_PORT_MTIP_CR4_1_VL3_1 0x11b4 +#define A_MAC_PORT_MTIP_CR4_1_PCS_MODE 0x11b8 +#define A_MAC_COMMON_CFG_0 0x38000 + +#define S_T7_RX_POLARITY_INV 24 +#define M_T7_RX_POLARITY_INV 0xffU +#define V_T7_RX_POLARITY_INV(x) ((x) << S_T7_RX_POLARITY_INV) +#define G_T7_RX_POLARITY_INV(x) (((x) >> S_T7_RX_POLARITY_INV) & M_T7_RX_POLARITY_INV) + +#define S_T7_TX_POLARITY_INV 16 +#define M_T7_TX_POLARITY_INV 0xffU +#define V_T7_TX_POLARITY_INV(x) ((x) << S_T7_TX_POLARITY_INV) +#define G_T7_TX_POLARITY_INV(x) (((x) >> S_T7_TX_POLARITY_INV) & M_T7_TX_POLARITY_INV) + +#define S_T7_DEBUG_PORT_SEL 14 +#define M_T7_DEBUG_PORT_SEL 0x3U +#define V_T7_DEBUG_PORT_SEL(x) ((x) << S_T7_DEBUG_PORT_SEL) +#define G_T7_DEBUG_PORT_SEL(x) (((x) >> S_T7_DEBUG_PORT_SEL) & M_T7_DEBUG_PORT_SEL) + +#define S_MAC_SEPTY_CTL 8 +#define M_MAC_SEPTY_CTL 0x3fU +#define V_MAC_SEPTY_CTL(x) ((x) << S_MAC_SEPTY_CTL) +#define G_MAC_SEPTY_CTL(x) (((x) >> S_MAC_SEPTY_CTL) & M_MAC_SEPTY_CTL) + +#define S_T7_DEBUG_TX_RX_SEL 7 +#define V_T7_DEBUG_TX_RX_SEL(x) ((x) << S_T7_DEBUG_TX_RX_SEL) +#define F_T7_DEBUG_TX_RX_SEL V_T7_DEBUG_TX_RX_SEL(1U) + +#define S_MAC_RDY_CTL 0 +#define M_MAC_RDY_CTL 0x3fU +#define V_MAC_RDY_CTL(x) ((x) << S_MAC_RDY_CTL) +#define G_MAC_RDY_CTL(x) (((x) >> S_MAC_RDY_CTL) & M_MAC_RDY_CTL) + +#define A_MAC_MTIP_RESET_CTRL_0 0x38004 + +#define S_RESET_F91_REF_CLK_I 31 +#define V_RESET_F91_REF_CLK_I(x) ((x) << S_RESET_F91_REF_CLK_I) +#define F_RESET_F91_REF_CLK_I V_RESET_F91_REF_CLK_I(1U) + +#define S_RESET_PCS000_REF_CLK_I 30 +#define V_RESET_PCS000_REF_CLK_I(x) ((x) << S_RESET_PCS000_REF_CLK_I) +#define F_RESET_PCS000_REF_CLK_I V_RESET_PCS000_REF_CLK_I(1U) + +#define S_RESET_REF_CLK_I 29 +#define V_RESET_REF_CLK_I(x) ((x) << S_RESET_REF_CLK_I) +#define F_RESET_REF_CLK_I V_RESET_REF_CLK_I(1U) + +#define S_RESET_SD_RX_CLK_I_0 28 +#define V_RESET_SD_RX_CLK_I_0(x) ((x) << S_RESET_SD_RX_CLK_I_0) +#define F_RESET_SD_RX_CLK_I_0 V_RESET_SD_RX_CLK_I_0(1U) + +#define S_RESET_SD_RX_CLK_I_1 27 +#define V_RESET_SD_RX_CLK_I_1(x) ((x) << S_RESET_SD_RX_CLK_I_1) +#define F_RESET_SD_RX_CLK_I_1 V_RESET_SD_RX_CLK_I_1(1U) + +#define S_RESET_SD_RX_CLK_I_2 26 +#define V_RESET_SD_RX_CLK_I_2(x) ((x) << S_RESET_SD_RX_CLK_I_2) +#define F_RESET_SD_RX_CLK_I_2 V_RESET_SD_RX_CLK_I_2(1U) + +#define S_RESET_SD_RX_CLK_I_3 25 +#define V_RESET_SD_RX_CLK_I_3(x) ((x) << S_RESET_SD_RX_CLK_I_3) +#define F_RESET_SD_RX_CLK_I_3 V_RESET_SD_RX_CLK_I_3(1U) + +#define S_RESET_SD_RX_CLK_I_4 24 +#define V_RESET_SD_RX_CLK_I_4(x) ((x) << S_RESET_SD_RX_CLK_I_4) +#define F_RESET_SD_RX_CLK_I_4 V_RESET_SD_RX_CLK_I_4(1U) + +#define S_RESET_SD_RX_CLK_I_5 23 +#define V_RESET_SD_RX_CLK_I_5(x) ((x) << S_RESET_SD_RX_CLK_I_5) +#define F_RESET_SD_RX_CLK_I_5 V_RESET_SD_RX_CLK_I_5(1U) + +#define S_RESET_SD_RX_CLK_I_6 22 +#define V_RESET_SD_RX_CLK_I_6(x) ((x) << S_RESET_SD_RX_CLK_I_6) +#define F_RESET_SD_RX_CLK_I_6 V_RESET_SD_RX_CLK_I_6(1U) + +#define S_RESET_SD_RX_CLK_I_7 21 +#define V_RESET_SD_RX_CLK_I_7(x) ((x) << S_RESET_SD_RX_CLK_I_7) +#define F_RESET_SD_RX_CLK_I_7 V_RESET_SD_RX_CLK_I_7(1U) + +#define S_RESET_SD_TX_CLK_I_0 20 +#define V_RESET_SD_TX_CLK_I_0(x) ((x) << S_RESET_SD_TX_CLK_I_0) +#define F_RESET_SD_TX_CLK_I_0 V_RESET_SD_TX_CLK_I_0(1U) + +#define S_RESET_SD_TX_CLK_I_1 19 +#define V_RESET_SD_TX_CLK_I_1(x) ((x) << S_RESET_SD_TX_CLK_I_1) +#define F_RESET_SD_TX_CLK_I_1 V_RESET_SD_TX_CLK_I_1(1U) + +#define S_RESET_SD_TX_CLK_I_2 18 +#define V_RESET_SD_TX_CLK_I_2(x) ((x) << S_RESET_SD_TX_CLK_I_2) +#define F_RESET_SD_TX_CLK_I_2 V_RESET_SD_TX_CLK_I_2(1U) + +#define S_RESET_SD_TX_CLK_I_3 17 +#define V_RESET_SD_TX_CLK_I_3(x) ((x) << S_RESET_SD_TX_CLK_I_3) +#define F_RESET_SD_TX_CLK_I_3 V_RESET_SD_TX_CLK_I_3(1U) + +#define S_RESET_SD_TX_CLK_I_4 16 +#define V_RESET_SD_TX_CLK_I_4(x) ((x) << S_RESET_SD_TX_CLK_I_4) +#define F_RESET_SD_TX_CLK_I_4 V_RESET_SD_TX_CLK_I_4(1U) + +#define S_RESET_SD_TX_CLK_I_5 15 +#define V_RESET_SD_TX_CLK_I_5(x) ((x) << S_RESET_SD_TX_CLK_I_5) +#define F_RESET_SD_TX_CLK_I_5 V_RESET_SD_TX_CLK_I_5(1U) + +#define S_RESET_SD_TX_CLK_I_6 14 +#define V_RESET_SD_TX_CLK_I_6(x) ((x) << S_RESET_SD_TX_CLK_I_6) +#define F_RESET_SD_TX_CLK_I_6 V_RESET_SD_TX_CLK_I_6(1U) + +#define S_RESET_SD_TX_CLK_I_7 13 +#define V_RESET_SD_TX_CLK_I_7(x) ((x) << S_RESET_SD_TX_CLK_I_7) +#define F_RESET_SD_TX_CLK_I_7 V_RESET_SD_TX_CLK_I_7(1U) + +#define S_RESET_XPCS_REF_CLK_I_0 12 +#define V_RESET_XPCS_REF_CLK_I_0(x) ((x) << S_RESET_XPCS_REF_CLK_I_0) +#define F_RESET_XPCS_REF_CLK_I_0 V_RESET_XPCS_REF_CLK_I_0(1U) + +#define S_RESET_XPCS_REF_CLK_I_1 11 +#define V_RESET_XPCS_REF_CLK_I_1(x) ((x) << S_RESET_XPCS_REF_CLK_I_1) +#define F_RESET_XPCS_REF_CLK_I_1 V_RESET_XPCS_REF_CLK_I_1(1U) + +#define S_RESET_FF_RX_CLK_0_I 9 +#define V_RESET_FF_RX_CLK_0_I(x) ((x) << S_RESET_FF_RX_CLK_0_I) +#define F_RESET_FF_RX_CLK_0_I V_RESET_FF_RX_CLK_0_I(1U) + +#define S_RESET_FF_TX_CLK_0_I 8 +#define V_RESET_FF_TX_CLK_0_I(x) ((x) << S_RESET_FF_TX_CLK_0_I) +#define F_RESET_FF_TX_CLK_0_I V_RESET_FF_TX_CLK_0_I(1U) + +#define S_RESET_RXCLK_0_I 7 +#define V_RESET_RXCLK_0_I(x) ((x) << S_RESET_RXCLK_0_I) +#define F_RESET_RXCLK_0_I V_RESET_RXCLK_0_I(1U) + +#define S_RESET_TXCLK_0_I 6 +#define V_RESET_TXCLK_0_I(x) ((x) << S_RESET_TXCLK_0_I) +#define F_RESET_TXCLK_0_I V_RESET_TXCLK_0_I(1U) + +#define S_RESET_FF_RX_CLK_1_I 5 +#define V_RESET_FF_RX_CLK_1_I(x) ((x) << S_RESET_FF_RX_CLK_1_I) +#define F_RESET_FF_RX_CLK_1_I V_RESET_FF_RX_CLK_1_I(1U) + +#define S_RESET_FF_TX_CLK_1_I 4 +#define V_RESET_FF_TX_CLK_1_I(x) ((x) << S_RESET_FF_TX_CLK_1_I) +#define F_RESET_FF_TX_CLK_1_I V_RESET_FF_TX_CLK_1_I(1U) + +#define S_RESET_RXCLK_1_I 3 +#define V_RESET_RXCLK_1_I(x) ((x) << S_RESET_RXCLK_1_I) +#define F_RESET_RXCLK_1_I V_RESET_RXCLK_1_I(1U) + +#define S_RESET_TXCLK_1_I 2 +#define V_RESET_TXCLK_1_I(x) ((x) << S_RESET_TXCLK_1_I) +#define F_RESET_TXCLK_1_I V_RESET_TXCLK_1_I(1U) + +#define S_XGMII_CLK_RESET_0 0 +#define V_XGMII_CLK_RESET_0(x) ((x) << S_XGMII_CLK_RESET_0) +#define F_XGMII_CLK_RESET_0 V_XGMII_CLK_RESET_0(1U) + +#define A_MAC_MTIP_RESET_CTRL_1 0x38008 + +#define S_RESET_FF_RX_CLK_2_I 31 +#define V_RESET_FF_RX_CLK_2_I(x) ((x) << S_RESET_FF_RX_CLK_2_I) +#define F_RESET_FF_RX_CLK_2_I V_RESET_FF_RX_CLK_2_I(1U) + +#define S_RESET_FF_TX_CLK_2_I 30 +#define V_RESET_FF_TX_CLK_2_I(x) ((x) << S_RESET_FF_TX_CLK_2_I) +#define F_RESET_FF_TX_CLK_2_I V_RESET_FF_TX_CLK_2_I(1U) + +#define S_RESET_RXCLK_2_I 29 +#define V_RESET_RXCLK_2_I(x) ((x) << S_RESET_RXCLK_2_I) +#define F_RESET_RXCLK_2_I V_RESET_RXCLK_2_I(1U) + +#define S_RESET_TXCLK_2_I 28 +#define V_RESET_TXCLK_2_I(x) ((x) << S_RESET_TXCLK_2_I) +#define F_RESET_TXCLK_2_I V_RESET_TXCLK_2_I(1U) + +#define S_RESET_FF_RX_CLK_3_I 27 +#define V_RESET_FF_RX_CLK_3_I(x) ((x) << S_RESET_FF_RX_CLK_3_I) +#define F_RESET_FF_RX_CLK_3_I V_RESET_FF_RX_CLK_3_I(1U) + +#define S_RESET_FF_TX_CLK_3_I 26 +#define V_RESET_FF_TX_CLK_3_I(x) ((x) << S_RESET_FF_TX_CLK_3_I) +#define F_RESET_FF_TX_CLK_3_I V_RESET_FF_TX_CLK_3_I(1U) + +#define S_RESET_RXCLK_3_I 25 +#define V_RESET_RXCLK_3_I(x) ((x) << S_RESET_RXCLK_3_I) +#define F_RESET_RXCLK_3_I V_RESET_RXCLK_3_I(1U) + +#define S_RESET_TXCLK_3_I 24 +#define V_RESET_TXCLK_3_I(x) ((x) << S_RESET_TXCLK_3_I) +#define F_RESET_TXCLK_3_I V_RESET_TXCLK_3_I(1U) + +#define S_RESET_FF_RX_CLK_4_I 23 +#define V_RESET_FF_RX_CLK_4_I(x) ((x) << S_RESET_FF_RX_CLK_4_I) +#define F_RESET_FF_RX_CLK_4_I V_RESET_FF_RX_CLK_4_I(1U) + +#define S_RESET_FF_TX_CLK_4_I 22 +#define V_RESET_FF_TX_CLK_4_I(x) ((x) << S_RESET_FF_TX_CLK_4_I) +#define F_RESET_FF_TX_CLK_4_I V_RESET_FF_TX_CLK_4_I(1U) + +#define S_RESET_RXCLK_4_I 21 +#define V_RESET_RXCLK_4_I(x) ((x) << S_RESET_RXCLK_4_I) +#define F_RESET_RXCLK_4_I V_RESET_RXCLK_4_I(1U) + +#define S_RESET_TXCLK_4_I 20 +#define V_RESET_TXCLK_4_I(x) ((x) << S_RESET_TXCLK_4_I) +#define F_RESET_TXCLK_4_I V_RESET_TXCLK_4_I(1U) + +#define S_RESET_FF_RX_CLK_5_I 19 +#define V_RESET_FF_RX_CLK_5_I(x) ((x) << S_RESET_FF_RX_CLK_5_I) +#define F_RESET_FF_RX_CLK_5_I V_RESET_FF_RX_CLK_5_I(1U) + +#define S_RESET_FF_TX_CLK_5_I 18 +#define V_RESET_FF_TX_CLK_5_I(x) ((x) << S_RESET_FF_TX_CLK_5_I) +#define F_RESET_FF_TX_CLK_5_I V_RESET_FF_TX_CLK_5_I(1U) + +#define S_RESET_RXCLK_5_I 17 +#define V_RESET_RXCLK_5_I(x) ((x) << S_RESET_RXCLK_5_I) +#define F_RESET_RXCLK_5_I V_RESET_RXCLK_5_I(1U) + +#define S_RESET_TXCLK_5_I 16 +#define V_RESET_TXCLK_5_I(x) ((x) << S_RESET_TXCLK_5_I) +#define F_RESET_TXCLK_5_I V_RESET_TXCLK_5_I(1U) + +#define S_RESET_SD_RX_CLK_AN_0_I 15 +#define V_RESET_SD_RX_CLK_AN_0_I(x) ((x) << S_RESET_SD_RX_CLK_AN_0_I) +#define F_RESET_SD_RX_CLK_AN_0_I V_RESET_SD_RX_CLK_AN_0_I(1U) + +#define S_RESET_SD_TX_CLK_AN_0_I 14 +#define V_RESET_SD_TX_CLK_AN_0_I(x) ((x) << S_RESET_SD_TX_CLK_AN_0_I) +#define F_RESET_SD_TX_CLK_AN_0_I V_RESET_SD_TX_CLK_AN_0_I(1U) + +#define S_RESET_SD_RX_CLK_AN_1_I 13 +#define V_RESET_SD_RX_CLK_AN_1_I(x) ((x) << S_RESET_SD_RX_CLK_AN_1_I) +#define F_RESET_SD_RX_CLK_AN_1_I V_RESET_SD_RX_CLK_AN_1_I(1U) + +#define S_RESET_SD_TX_CLK_AN_1_I 12 +#define V_RESET_SD_TX_CLK_AN_1_I(x) ((x) << S_RESET_SD_TX_CLK_AN_1_I) +#define F_RESET_SD_TX_CLK_AN_1_I V_RESET_SD_TX_CLK_AN_1_I(1U) + +#define S_RESET_SD_RX_CLK_AN_2_I 11 +#define V_RESET_SD_RX_CLK_AN_2_I(x) ((x) << S_RESET_SD_RX_CLK_AN_2_I) +#define F_RESET_SD_RX_CLK_AN_2_I V_RESET_SD_RX_CLK_AN_2_I(1U) + +#define S_RESET_SD_TX_CLK_AN_2_I 10 +#define V_RESET_SD_TX_CLK_AN_2_I(x) ((x) << S_RESET_SD_TX_CLK_AN_2_I) +#define F_RESET_SD_TX_CLK_AN_2_I V_RESET_SD_TX_CLK_AN_2_I(1U) + +#define S_RESET_SD_RX_CLK_AN_3_I 9 +#define V_RESET_SD_RX_CLK_AN_3_I(x) ((x) << S_RESET_SD_RX_CLK_AN_3_I) +#define F_RESET_SD_RX_CLK_AN_3_I V_RESET_SD_RX_CLK_AN_3_I(1U) + +#define S_RESET_SD_TX_CLK_AN_3_I 8 +#define V_RESET_SD_TX_CLK_AN_3_I(x) ((x) << S_RESET_SD_TX_CLK_AN_3_I) +#define F_RESET_SD_TX_CLK_AN_3_I V_RESET_SD_TX_CLK_AN_3_I(1U) + +#define S_RESET_SD_RX_CLK_AN_4_I 7 +#define V_RESET_SD_RX_CLK_AN_4_I(x) ((x) << S_RESET_SD_RX_CLK_AN_4_I) +#define F_RESET_SD_RX_CLK_AN_4_I V_RESET_SD_RX_CLK_AN_4_I(1U) + +#define S_RESET_SD_TX_CLK_AN_4_I 6 +#define V_RESET_SD_TX_CLK_AN_4_I(x) ((x) << S_RESET_SD_TX_CLK_AN_4_I) +#define F_RESET_SD_TX_CLK_AN_4_I V_RESET_SD_TX_CLK_AN_4_I(1U) + +#define S_RESET_SD_RX_CLK_AN_5_I 5 +#define V_RESET_SD_RX_CLK_AN_5_I(x) ((x) << S_RESET_SD_RX_CLK_AN_5_I) +#define F_RESET_SD_RX_CLK_AN_5_I V_RESET_SD_RX_CLK_AN_5_I(1U) + +#define S_RESET_SD_TX_CLK_AN_5_I 4 +#define V_RESET_SD_TX_CLK_AN_5_I(x) ((x) << S_RESET_SD_TX_CLK_AN_5_I) +#define F_RESET_SD_TX_CLK_AN_5_I V_RESET_SD_TX_CLK_AN_5_I(1U) + +#define S_RESET_SD_RX_CLK_AN_6_I 3 +#define V_RESET_SD_RX_CLK_AN_6_I(x) ((x) << S_RESET_SD_RX_CLK_AN_6_I) +#define F_RESET_SD_RX_CLK_AN_6_I V_RESET_SD_RX_CLK_AN_6_I(1U) + +#define S_RESET_SD_TX_CLK_AN_6_I 2 +#define V_RESET_SD_TX_CLK_AN_6_I(x) ((x) << S_RESET_SD_TX_CLK_AN_6_I) +#define F_RESET_SD_TX_CLK_AN_6_I V_RESET_SD_TX_CLK_AN_6_I(1U) + +#define S_RESET_SD_RX_CLK_AN_7_I 1 +#define V_RESET_SD_RX_CLK_AN_7_I(x) ((x) << S_RESET_SD_RX_CLK_AN_7_I) +#define F_RESET_SD_RX_CLK_AN_7_I V_RESET_SD_RX_CLK_AN_7_I(1U) + +#define S_RESET_SD_TX_CLK_AN_7_I 0 +#define V_RESET_SD_TX_CLK_AN_7_I(x) ((x) << S_RESET_SD_TX_CLK_AN_7_I) +#define F_RESET_SD_TX_CLK_AN_7_I V_RESET_SD_TX_CLK_AN_7_I(1U) + +#define A_MAC_MTIP_RESET_CTRL_2 0x3800c + +#define S_RESET_SGMII_TXCLK_I_3 31 +#define V_RESET_SGMII_TXCLK_I_3(x) ((x) << S_RESET_SGMII_TXCLK_I_3) +#define F_RESET_SGMII_TXCLK_I_3 V_RESET_SGMII_TXCLK_I_3(1U) + +#define S_RESET_SGMII_RXCLK_I_3 30 +#define V_RESET_SGMII_RXCLK_I_3(x) ((x) << S_RESET_SGMII_RXCLK_I_3) +#define F_RESET_SGMII_RXCLK_I_3 V_RESET_SGMII_RXCLK_I_3(1U) + +#define S_RESET_SGMII_TXCLK_I_2 29 +#define V_RESET_SGMII_TXCLK_I_2(x) ((x) << S_RESET_SGMII_TXCLK_I_2) +#define F_RESET_SGMII_TXCLK_I_2 V_RESET_SGMII_TXCLK_I_2(1U) + +#define S_RESET_SGMII_RXCLK_I_2 28 +#define V_RESET_SGMII_RXCLK_I_2(x) ((x) << S_RESET_SGMII_RXCLK_I_2) +#define F_RESET_SGMII_RXCLK_I_2 V_RESET_SGMII_RXCLK_I_2(1U) + +#define S_RESET_SGMII_TXCLK_I_1 27 +#define V_RESET_SGMII_TXCLK_I_1(x) ((x) << S_RESET_SGMII_TXCLK_I_1) +#define F_RESET_SGMII_TXCLK_I_1 V_RESET_SGMII_TXCLK_I_1(1U) + +#define S_RESET_SGMII_RXCLK_I_1 26 +#define V_RESET_SGMII_RXCLK_I_1(x) ((x) << S_RESET_SGMII_RXCLK_I_1) +#define F_RESET_SGMII_RXCLK_I_1 V_RESET_SGMII_RXCLK_I_1(1U) + +#define S_RESET_SGMII_TXCLK_I_0 25 +#define V_RESET_SGMII_TXCLK_I_0(x) ((x) << S_RESET_SGMII_TXCLK_I_0) +#define F_RESET_SGMII_TXCLK_I_0 V_RESET_SGMII_TXCLK_I_0(1U) + +#define S_RESET_SGMII_RXCLK_I_0 24 +#define V_RESET_SGMII_RXCLK_I_0(x) ((x) << S_RESET_SGMII_RXCLK_I_0) +#define F_RESET_SGMII_RXCLK_I_0 V_RESET_SGMII_RXCLK_I_0(1U) + +#define S_MTIPSD7TXRST 23 +#define V_MTIPSD7TXRST(x) ((x) << S_MTIPSD7TXRST) +#define F_MTIPSD7TXRST V_MTIPSD7TXRST(1U) + +#define S_MTIPSD6TXRST 22 +#define V_MTIPSD6TXRST(x) ((x) << S_MTIPSD6TXRST) +#define F_MTIPSD6TXRST V_MTIPSD6TXRST(1U) + +#define S_MTIPSD5TXRST 21 +#define V_MTIPSD5TXRST(x) ((x) << S_MTIPSD5TXRST) +#define F_MTIPSD5TXRST V_MTIPSD5TXRST(1U) + +#define S_MTIPSD4TXRST 20 +#define V_MTIPSD4TXRST(x) ((x) << S_MTIPSD4TXRST) +#define F_MTIPSD4TXRST V_MTIPSD4TXRST(1U) + +#define S_T7_MTIPSD3TXRST 19 +#define V_T7_MTIPSD3TXRST(x) ((x) << S_T7_MTIPSD3TXRST) +#define F_T7_MTIPSD3TXRST V_T7_MTIPSD3TXRST(1U) + +#define S_T7_MTIPSD2TXRST 18 +#define V_T7_MTIPSD2TXRST(x) ((x) << S_T7_MTIPSD2TXRST) +#define F_T7_MTIPSD2TXRST V_T7_MTIPSD2TXRST(1U) + +#define S_T7_MTIPSD1TXRST 17 +#define V_T7_MTIPSD1TXRST(x) ((x) << S_T7_MTIPSD1TXRST) +#define F_T7_MTIPSD1TXRST V_T7_MTIPSD1TXRST(1U) + +#define S_T7_MTIPSD0TXRST 16 +#define V_T7_MTIPSD0TXRST(x) ((x) << S_T7_MTIPSD0TXRST) +#define F_T7_MTIPSD0TXRST V_T7_MTIPSD0TXRST(1U) + +#define S_MTIPSD7RXRST 15 +#define V_MTIPSD7RXRST(x) ((x) << S_MTIPSD7RXRST) +#define F_MTIPSD7RXRST V_MTIPSD7RXRST(1U) + +#define S_MTIPSD6RXRST 14 +#define V_MTIPSD6RXRST(x) ((x) << S_MTIPSD6RXRST) +#define F_MTIPSD6RXRST V_MTIPSD6RXRST(1U) + +#define S_MTIPSD5RXRST 13 +#define V_MTIPSD5RXRST(x) ((x) << S_MTIPSD5RXRST) +#define F_MTIPSD5RXRST V_MTIPSD5RXRST(1U) + +#define S_MTIPSD4RXRST 12 +#define V_MTIPSD4RXRST(x) ((x) << S_MTIPSD4RXRST) +#define F_MTIPSD4RXRST V_MTIPSD4RXRST(1U) + +#define S_T7_MTIPSD3RXRST 11 +#define V_T7_MTIPSD3RXRST(x) ((x) << S_T7_MTIPSD3RXRST) +#define F_T7_MTIPSD3RXRST V_T7_MTIPSD3RXRST(1U) + +#define S_T7_MTIPSD2RXRST 10 +#define V_T7_MTIPSD2RXRST(x) ((x) << S_T7_MTIPSD2RXRST) +#define F_T7_MTIPSD2RXRST V_T7_MTIPSD2RXRST(1U) + +#define S_T7_MTIPSD1RXRST 9 +#define V_T7_MTIPSD1RXRST(x) ((x) << S_T7_MTIPSD1RXRST) +#define F_T7_MTIPSD1RXRST V_T7_MTIPSD1RXRST(1U) + +#define S_T7_MTIPSD0RXRST 8 +#define V_T7_MTIPSD0RXRST(x) ((x) << S_T7_MTIPSD0RXRST) +#define F_T7_MTIPSD0RXRST V_T7_MTIPSD0RXRST(1U) + +#define S_RESET_REG_CLK_AN_0_I 7 +#define V_RESET_REG_CLK_AN_0_I(x) ((x) << S_RESET_REG_CLK_AN_0_I) +#define F_RESET_REG_CLK_AN_0_I V_RESET_REG_CLK_AN_0_I(1U) + +#define S_RESET_REG_CLK_AN_1_I 6 +#define V_RESET_REG_CLK_AN_1_I(x) ((x) << S_RESET_REG_CLK_AN_1_I) +#define F_RESET_REG_CLK_AN_1_I V_RESET_REG_CLK_AN_1_I(1U) + +#define S_RESET_REG_CLK_AN_2_I 5 +#define V_RESET_REG_CLK_AN_2_I(x) ((x) << S_RESET_REG_CLK_AN_2_I) +#define F_RESET_REG_CLK_AN_2_I V_RESET_REG_CLK_AN_2_I(1U) + +#define S_RESET_REG_CLK_AN_3_I 4 +#define V_RESET_REG_CLK_AN_3_I(x) ((x) << S_RESET_REG_CLK_AN_3_I) +#define F_RESET_REG_CLK_AN_3_I V_RESET_REG_CLK_AN_3_I(1U) + +#define S_RESET_REG_CLK_AN_4_I 3 +#define V_RESET_REG_CLK_AN_4_I(x) ((x) << S_RESET_REG_CLK_AN_4_I) +#define F_RESET_REG_CLK_AN_4_I V_RESET_REG_CLK_AN_4_I(1U) + +#define S_RESET_REG_CLK_AN_5_I 2 +#define V_RESET_REG_CLK_AN_5_I(x) ((x) << S_RESET_REG_CLK_AN_5_I) +#define F_RESET_REG_CLK_AN_5_I V_RESET_REG_CLK_AN_5_I(1U) + +#define S_RESET_REG_CLK_AN_6_I 1 +#define V_RESET_REG_CLK_AN_6_I(x) ((x) << S_RESET_REG_CLK_AN_6_I) +#define F_RESET_REG_CLK_AN_6_I V_RESET_REG_CLK_AN_6_I(1U) + +#define S_RESET_REG_CLK_AN_7_I 0 +#define V_RESET_REG_CLK_AN_7_I(x) ((x) << S_RESET_REG_CLK_AN_7_I) +#define F_RESET_REG_CLK_AN_7_I V_RESET_REG_CLK_AN_7_I(1U) + +#define A_MAC_MTIP_CLK_CTRL_0 0x38010 + +#define S_F91_REF_CLK_I_G 31 +#define V_F91_REF_CLK_I_G(x) ((x) << S_F91_REF_CLK_I_G) +#define F_F91_REF_CLK_I_G V_F91_REF_CLK_I_G(1U) + +#define S_PCS000_REF_CLK_I_G 30 +#define V_PCS000_REF_CLK_I_G(x) ((x) << S_PCS000_REF_CLK_I_G) +#define F_PCS000_REF_CLK_I_G V_PCS000_REF_CLK_I_G(1U) + +#define S_REF_CLK_I_G 29 +#define V_REF_CLK_I_G(x) ((x) << S_REF_CLK_I_G) +#define F_REF_CLK_I_G V_REF_CLK_I_G(1U) + +#define S_SD_RX_CLK_I_0_G 28 +#define V_SD_RX_CLK_I_0_G(x) ((x) << S_SD_RX_CLK_I_0_G) +#define F_SD_RX_CLK_I_0_G V_SD_RX_CLK_I_0_G(1U) + +#define S_SD_RX_CLK_I_1_G 27 +#define V_SD_RX_CLK_I_1_G(x) ((x) << S_SD_RX_CLK_I_1_G) +#define F_SD_RX_CLK_I_1_G V_SD_RX_CLK_I_1_G(1U) + +#define S_SD_RX_CLK_I_2_G 26 +#define V_SD_RX_CLK_I_2_G(x) ((x) << S_SD_RX_CLK_I_2_G) +#define F_SD_RX_CLK_I_2_G V_SD_RX_CLK_I_2_G(1U) + +#define S_SD_RX_CLK_I_3_G 25 +#define V_SD_RX_CLK_I_3_G(x) ((x) << S_SD_RX_CLK_I_3_G) +#define F_SD_RX_CLK_I_3_G V_SD_RX_CLK_I_3_G(1U) + +#define S_SD_RX_CLK_I_4_G 24 +#define V_SD_RX_CLK_I_4_G(x) ((x) << S_SD_RX_CLK_I_4_G) +#define F_SD_RX_CLK_I_4_G V_SD_RX_CLK_I_4_G(1U) + +#define S_SD_RX_CLK_I_5_G 23 +#define V_SD_RX_CLK_I_5_G(x) ((x) << S_SD_RX_CLK_I_5_G) +#define F_SD_RX_CLK_I_5_G V_SD_RX_CLK_I_5_G(1U) + +#define S_SD_RX_CLK_I_6_G 22 +#define V_SD_RX_CLK_I_6_G(x) ((x) << S_SD_RX_CLK_I_6_G) +#define F_SD_RX_CLK_I_6_G V_SD_RX_CLK_I_6_G(1U) + +#define S_SD_RX_CLK_I_7_G 21 +#define V_SD_RX_CLK_I_7_G(x) ((x) << S_SD_RX_CLK_I_7_G) +#define F_SD_RX_CLK_I_7_G V_SD_RX_CLK_I_7_G(1U) + +#define S_SD_TX_CLK_I_0_G 20 +#define V_SD_TX_CLK_I_0_G(x) ((x) << S_SD_TX_CLK_I_0_G) +#define F_SD_TX_CLK_I_0_G V_SD_TX_CLK_I_0_G(1U) + +#define S_SD_TX_CLK_I_1_G 19 +#define V_SD_TX_CLK_I_1_G(x) ((x) << S_SD_TX_CLK_I_1_G) +#define F_SD_TX_CLK_I_1_G V_SD_TX_CLK_I_1_G(1U) + +#define S_SD_TX_CLK_I_2_G 18 +#define V_SD_TX_CLK_I_2_G(x) ((x) << S_SD_TX_CLK_I_2_G) +#define F_SD_TX_CLK_I_2_G V_SD_TX_CLK_I_2_G(1U) + +#define S_SD_TX_CLK_I_3_G 17 +#define V_SD_TX_CLK_I_3_G(x) ((x) << S_SD_TX_CLK_I_3_G) +#define F_SD_TX_CLK_I_3_G V_SD_TX_CLK_I_3_G(1U) + +#define S_SD_TX_CLK_I_4_G 16 +#define V_SD_TX_CLK_I_4_G(x) ((x) << S_SD_TX_CLK_I_4_G) +#define F_SD_TX_CLK_I_4_G V_SD_TX_CLK_I_4_G(1U) + +#define S_SD_TX_CLK_I_5_G 15 +#define V_SD_TX_CLK_I_5_G(x) ((x) << S_SD_TX_CLK_I_5_G) +#define F_SD_TX_CLK_I_5_G V_SD_TX_CLK_I_5_G(1U) + +#define S_SD_TX_CLK_I_6_G 14 +#define V_SD_TX_CLK_I_6_G(x) ((x) << S_SD_TX_CLK_I_6_G) +#define F_SD_TX_CLK_I_6_G V_SD_TX_CLK_I_6_G(1U) + +#define S_SD_TX_CLK_I_7_G 13 +#define V_SD_TX_CLK_I_7_G(x) ((x) << S_SD_TX_CLK_I_7_G) +#define F_SD_TX_CLK_I_7_G V_SD_TX_CLK_I_7_G(1U) + +#define S_XPCS_REF_CLK_I_0_G 12 +#define V_XPCS_REF_CLK_I_0_G(x) ((x) << S_XPCS_REF_CLK_I_0_G) +#define F_XPCS_REF_CLK_I_0_G V_XPCS_REF_CLK_I_0_G(1U) + +#define S_XPCS_REF_CLK_I_1_G 11 +#define V_XPCS_REF_CLK_I_1_G(x) ((x) << S_XPCS_REF_CLK_I_1_G) +#define F_XPCS_REF_CLK_I_1_G V_XPCS_REF_CLK_I_1_G(1U) + +#define S_REG_CLK_I_G 10 +#define V_REG_CLK_I_G(x) ((x) << S_REG_CLK_I_G) +#define F_REG_CLK_I_G V_REG_CLK_I_G(1U) + +#define S_FF_RX_CLK_0_I_G 9 +#define V_FF_RX_CLK_0_I_G(x) ((x) << S_FF_RX_CLK_0_I_G) +#define F_FF_RX_CLK_0_I_G V_FF_RX_CLK_0_I_G(1U) + +#define S_FF_TX_CLK_0_I_G 8 +#define V_FF_TX_CLK_0_I_G(x) ((x) << S_FF_TX_CLK_0_I_G) +#define F_FF_TX_CLK_0_I_G V_FF_TX_CLK_0_I_G(1U) + +#define S_RXCLK_0_I_G 7 +#define V_RXCLK_0_I_G(x) ((x) << S_RXCLK_0_I_G) +#define F_RXCLK_0_I_G V_RXCLK_0_I_G(1U) + +#define S_TXCLK_0_I_G 6 +#define V_TXCLK_0_I_G(x) ((x) << S_TXCLK_0_I_G) +#define F_TXCLK_0_I_G V_TXCLK_0_I_G(1U) + +#define S_FF_RX_CLK_1_I_G 5 +#define V_FF_RX_CLK_1_I_G(x) ((x) << S_FF_RX_CLK_1_I_G) +#define F_FF_RX_CLK_1_I_G V_FF_RX_CLK_1_I_G(1U) + +#define S_FF_TX_CLK_1_I_G 4 +#define V_FF_TX_CLK_1_I_G(x) ((x) << S_FF_TX_CLK_1_I_G) +#define F_FF_TX_CLK_1_I_G V_FF_TX_CLK_1_I_G(1U) + +#define S_RXCLK_1_I_G 3 +#define V_RXCLK_1_I_G(x) ((x) << S_RXCLK_1_I_G) +#define F_RXCLK_1_I_G V_RXCLK_1_I_G(1U) + +#define S_TXCLK_1_I_G 2 +#define V_TXCLK_1_I_G(x) ((x) << S_TXCLK_1_I_G) +#define F_TXCLK_1_I_G V_TXCLK_1_I_G(1U) + +#define A_MAC_MTIP_CLK_CTRL_1 0x38014 + +#define S_FF_RX_CLK_2_I_G 31 +#define V_FF_RX_CLK_2_I_G(x) ((x) << S_FF_RX_CLK_2_I_G) +#define F_FF_RX_CLK_2_I_G V_FF_RX_CLK_2_I_G(1U) + +#define S_FF_TX_CLK_2_I_G 30 +#define V_FF_TX_CLK_2_I_G(x) ((x) << S_FF_TX_CLK_2_I_G) +#define F_FF_TX_CLK_2_I_G V_FF_TX_CLK_2_I_G(1U) + +#define S_RXCLK_2_I_G 29 +#define V_RXCLK_2_I_G(x) ((x) << S_RXCLK_2_I_G) +#define F_RXCLK_2_I_G V_RXCLK_2_I_G(1U) + +#define S_TXCLK_2_I_G 28 +#define V_TXCLK_2_I_G(x) ((x) << S_TXCLK_2_I_G) +#define F_TXCLK_2_I_G V_TXCLK_2_I_G(1U) + +#define S_FF_RX_CLK_3_I_G 27 +#define V_FF_RX_CLK_3_I_G(x) ((x) << S_FF_RX_CLK_3_I_G) +#define F_FF_RX_CLK_3_I_G V_FF_RX_CLK_3_I_G(1U) + +#define S_FF_TX_CLK_3_I_G 26 +#define V_FF_TX_CLK_3_I_G(x) ((x) << S_FF_TX_CLK_3_I_G) +#define F_FF_TX_CLK_3_I_G V_FF_TX_CLK_3_I_G(1U) + +#define S_RXCLK_3_I_G 25 +#define V_RXCLK_3_I_G(x) ((x) << S_RXCLK_3_I_G) +#define F_RXCLK_3_I_G V_RXCLK_3_I_G(1U) + +#define S_TXCLK_3_I_G 24 +#define V_TXCLK_3_I_G(x) ((x) << S_TXCLK_3_I_G) +#define F_TXCLK_3_I_G V_TXCLK_3_I_G(1U) + +#define S_FF_RX_CLK_4_I_G 23 +#define V_FF_RX_CLK_4_I_G(x) ((x) << S_FF_RX_CLK_4_I_G) +#define F_FF_RX_CLK_4_I_G V_FF_RX_CLK_4_I_G(1U) + +#define S_FF_TX_CLK_4_I_G 22 +#define V_FF_TX_CLK_4_I_G(x) ((x) << S_FF_TX_CLK_4_I_G) +#define F_FF_TX_CLK_4_I_G V_FF_TX_CLK_4_I_G(1U) + +#define S_RXCLK_4_I_G 21 +#define V_RXCLK_4_I_G(x) ((x) << S_RXCLK_4_I_G) +#define F_RXCLK_4_I_G V_RXCLK_4_I_G(1U) + +#define S_TXCLK_4_I_G 20 +#define V_TXCLK_4_I_G(x) ((x) << S_TXCLK_4_I_G) +#define F_TXCLK_4_I_G V_TXCLK_4_I_G(1U) + +#define S_FF_RX_CLK_5_I_G 19 +#define V_FF_RX_CLK_5_I_G(x) ((x) << S_FF_RX_CLK_5_I_G) +#define F_FF_RX_CLK_5_I_G V_FF_RX_CLK_5_I_G(1U) + +#define S_FF_TX_CLK_5_I_G 18 +#define V_FF_TX_CLK_5_I_G(x) ((x) << S_FF_TX_CLK_5_I_G) +#define F_FF_TX_CLK_5_I_G V_FF_TX_CLK_5_I_G(1U) + +#define S_RXCLK_5_I_G 17 +#define V_RXCLK_5_I_G(x) ((x) << S_RXCLK_5_I_G) +#define F_RXCLK_5_I_G V_RXCLK_5_I_G(1U) + +#define S_TXCLK_5_I_G 16 +#define V_TXCLK_5_I_G(x) ((x) << S_TXCLK_5_I_G) +#define F_TXCLK_5_I_G V_TXCLK_5_I_G(1U) + +#define S_SD_RX_CLK_AN_0_I_G 15 +#define V_SD_RX_CLK_AN_0_I_G(x) ((x) << S_SD_RX_CLK_AN_0_I_G) +#define F_SD_RX_CLK_AN_0_I_G V_SD_RX_CLK_AN_0_I_G(1U) + +#define S_SD_TX_CLK_AN_0_I_G 14 +#define V_SD_TX_CLK_AN_0_I_G(x) ((x) << S_SD_TX_CLK_AN_0_I_G) +#define F_SD_TX_CLK_AN_0_I_G V_SD_TX_CLK_AN_0_I_G(1U) + +#define S_SD_RX_CLK_AN_1_I_G 13 +#define V_SD_RX_CLK_AN_1_I_G(x) ((x) << S_SD_RX_CLK_AN_1_I_G) +#define F_SD_RX_CLK_AN_1_I_G V_SD_RX_CLK_AN_1_I_G(1U) + +#define S_SD_TX_CLK_AN_1_I_G 12 +#define V_SD_TX_CLK_AN_1_I_G(x) ((x) << S_SD_TX_CLK_AN_1_I_G) +#define F_SD_TX_CLK_AN_1_I_G V_SD_TX_CLK_AN_1_I_G(1U) + +#define S_SD_RX_CLK_AN_2_I_G 11 +#define V_SD_RX_CLK_AN_2_I_G(x) ((x) << S_SD_RX_CLK_AN_2_I_G) +#define F_SD_RX_CLK_AN_2_I_G V_SD_RX_CLK_AN_2_I_G(1U) + +#define S_SD_TX_CLK_AN_2_I_G 10 +#define V_SD_TX_CLK_AN_2_I_G(x) ((x) << S_SD_TX_CLK_AN_2_I_G) +#define F_SD_TX_CLK_AN_2_I_G V_SD_TX_CLK_AN_2_I_G(1U) + +#define S_SD_RX_CLK_AN_3_I_G 9 +#define V_SD_RX_CLK_AN_3_I_G(x) ((x) << S_SD_RX_CLK_AN_3_I_G) +#define F_SD_RX_CLK_AN_3_I_G V_SD_RX_CLK_AN_3_I_G(1U) + +#define S_SD_TX_CLK_AN_3_I_G 8 +#define V_SD_TX_CLK_AN_3_I_G(x) ((x) << S_SD_TX_CLK_AN_3_I_G) +#define F_SD_TX_CLK_AN_3_I_G V_SD_TX_CLK_AN_3_I_G(1U) + +#define S_SD_RX_CLK_AN_4_I_G 7 +#define V_SD_RX_CLK_AN_4_I_G(x) ((x) << S_SD_RX_CLK_AN_4_I_G) +#define F_SD_RX_CLK_AN_4_I_G V_SD_RX_CLK_AN_4_I_G(1U) + +#define S_SD_TX_CLK_AN_4_I_G 6 +#define V_SD_TX_CLK_AN_4_I_G(x) ((x) << S_SD_TX_CLK_AN_4_I_G) +#define F_SD_TX_CLK_AN_4_I_G V_SD_TX_CLK_AN_4_I_G(1U) + +#define S_SD_RX_CLK_AN_5_I_G 5 +#define V_SD_RX_CLK_AN_5_I_G(x) ((x) << S_SD_RX_CLK_AN_5_I_G) +#define F_SD_RX_CLK_AN_5_I_G V_SD_RX_CLK_AN_5_I_G(1U) + +#define S_SD_TX_CLK_AN_5_I_G 4 +#define V_SD_TX_CLK_AN_5_I_G(x) ((x) << S_SD_TX_CLK_AN_5_I_G) +#define F_SD_TX_CLK_AN_5_I_G V_SD_TX_CLK_AN_5_I_G(1U) + +#define S_SD_RX_CLK_AN_6_I_G 3 +#define V_SD_RX_CLK_AN_6_I_G(x) ((x) << S_SD_RX_CLK_AN_6_I_G) +#define F_SD_RX_CLK_AN_6_I_G V_SD_RX_CLK_AN_6_I_G(1U) + +#define S_SD_TX_CLK_AN_6_I_G 2 +#define V_SD_TX_CLK_AN_6_I_G(x) ((x) << S_SD_TX_CLK_AN_6_I_G) +#define F_SD_TX_CLK_AN_6_I_G V_SD_TX_CLK_AN_6_I_G(1U) + +#define S_SD_RX_CLK_AN_7_I_G 1 +#define V_SD_RX_CLK_AN_7_I_G(x) ((x) << S_SD_RX_CLK_AN_7_I_G) +#define F_SD_RX_CLK_AN_7_I_G V_SD_RX_CLK_AN_7_I_G(1U) + +#define S_SD_TX_CLK_AN_7_I_G 0 +#define V_SD_TX_CLK_AN_7_I_G(x) ((x) << S_SD_TX_CLK_AN_7_I_G) +#define F_SD_TX_CLK_AN_7_I_G V_SD_TX_CLK_AN_7_I_G(1U) + +#define A_MAC_MTIP_CLK_CTRL_2 0x38018 + +#define S_SD_RX_CLK_0_G 31 +#define V_SD_RX_CLK_0_G(x) ((x) << S_SD_RX_CLK_0_G) +#define F_SD_RX_CLK_0_G V_SD_RX_CLK_0_G(1U) + +#define S_SD_RX_CLK_1_G 30 +#define V_SD_RX_CLK_1_G(x) ((x) << S_SD_RX_CLK_1_G) +#define F_SD_RX_CLK_1_G V_SD_RX_CLK_1_G(1U) + +#define S_SD_RX_CLK_2_G 29 +#define V_SD_RX_CLK_2_G(x) ((x) << S_SD_RX_CLK_2_G) +#define F_SD_RX_CLK_2_G V_SD_RX_CLK_2_G(1U) + +#define S_SD_RX_CLK_3_G 28 +#define V_SD_RX_CLK_3_G(x) ((x) << S_SD_RX_CLK_3_G) +#define F_SD_RX_CLK_3_G V_SD_RX_CLK_3_G(1U) + +#define S_SD_RX_CLK_4_G 27 +#define V_SD_RX_CLK_4_G(x) ((x) << S_SD_RX_CLK_4_G) +#define F_SD_RX_CLK_4_G V_SD_RX_CLK_4_G(1U) + +#define S_SD_RX_CLK_5_G 26 +#define V_SD_RX_CLK_5_G(x) ((x) << S_SD_RX_CLK_5_G) +#define F_SD_RX_CLK_5_G V_SD_RX_CLK_5_G(1U) + +#define S_SD_RX_CLK_6_G 25 +#define V_SD_RX_CLK_6_G(x) ((x) << S_SD_RX_CLK_6_G) +#define F_SD_RX_CLK_6_G V_SD_RX_CLK_6_G(1U) + +#define S_SD_RX_CLK_7_G 24 +#define V_SD_RX_CLK_7_G(x) ((x) << S_SD_RX_CLK_7_G) +#define F_SD_RX_CLK_7_G V_SD_RX_CLK_7_G(1U) + +#define S_SD_TX_CLK_0_G 23 +#define V_SD_TX_CLK_0_G(x) ((x) << S_SD_TX_CLK_0_G) +#define F_SD_TX_CLK_0_G V_SD_TX_CLK_0_G(1U) + +#define S_SD_TX_CLK_1_G 22 +#define V_SD_TX_CLK_1_G(x) ((x) << S_SD_TX_CLK_1_G) +#define F_SD_TX_CLK_1_G V_SD_TX_CLK_1_G(1U) + +#define S_SD_TX_CLK_2_G 21 +#define V_SD_TX_CLK_2_G(x) ((x) << S_SD_TX_CLK_2_G) +#define F_SD_TX_CLK_2_G V_SD_TX_CLK_2_G(1U) + +#define S_SD_TX_CLK_3_G 20 +#define V_SD_TX_CLK_3_G(x) ((x) << S_SD_TX_CLK_3_G) +#define F_SD_TX_CLK_3_G V_SD_TX_CLK_3_G(1U) + +#define S_SD_TX_CLK_4_G 19 +#define V_SD_TX_CLK_4_G(x) ((x) << S_SD_TX_CLK_4_G) +#define F_SD_TX_CLK_4_G V_SD_TX_CLK_4_G(1U) + +#define S_SD_TX_CLK_5_G 18 +#define V_SD_TX_CLK_5_G(x) ((x) << S_SD_TX_CLK_5_G) +#define F_SD_TX_CLK_5_G V_SD_TX_CLK_5_G(1U) + +#define S_SD_TX_CLK_6_G 17 +#define V_SD_TX_CLK_6_G(x) ((x) << S_SD_TX_CLK_6_G) +#define F_SD_TX_CLK_6_G V_SD_TX_CLK_6_G(1U) + +#define S_SD_TX_CLK_7_G 16 +#define V_SD_TX_CLK_7_G(x) ((x) << S_SD_TX_CLK_7_G) +#define F_SD_TX_CLK_7_G V_SD_TX_CLK_7_G(1U) + +#define S_SD_RX_CLK_AEC_0_G 15 +#define V_SD_RX_CLK_AEC_0_G(x) ((x) << S_SD_RX_CLK_AEC_0_G) +#define F_SD_RX_CLK_AEC_0_G V_SD_RX_CLK_AEC_0_G(1U) + +#define S_SD_RX_CLK_AEC_1_G 14 +#define V_SD_RX_CLK_AEC_1_G(x) ((x) << S_SD_RX_CLK_AEC_1_G) +#define F_SD_RX_CLK_AEC_1_G V_SD_RX_CLK_AEC_1_G(1U) + +#define S_SD_RX_CLK_AEC_2_G 13 +#define V_SD_RX_CLK_AEC_2_G(x) ((x) << S_SD_RX_CLK_AEC_2_G) +#define F_SD_RX_CLK_AEC_2_G V_SD_RX_CLK_AEC_2_G(1U) + +#define S_SD_RX_CLK_AEC_3_G 12 +#define V_SD_RX_CLK_AEC_3_G(x) ((x) << S_SD_RX_CLK_AEC_3_G) +#define F_SD_RX_CLK_AEC_3_G V_SD_RX_CLK_AEC_3_G(1U) + +#define S_SD_RX_CLK_AEC_4_G 11 +#define V_SD_RX_CLK_AEC_4_G(x) ((x) << S_SD_RX_CLK_AEC_4_G) +#define F_SD_RX_CLK_AEC_4_G V_SD_RX_CLK_AEC_4_G(1U) + +#define S_SD_RX_CLK_AEC_5_G 10 +#define V_SD_RX_CLK_AEC_5_G(x) ((x) << S_SD_RX_CLK_AEC_5_G) +#define F_SD_RX_CLK_AEC_5_G V_SD_RX_CLK_AEC_5_G(1U) + +#define S_SD_RX_CLK_AEC_6_G 9 +#define V_SD_RX_CLK_AEC_6_G(x) ((x) << S_SD_RX_CLK_AEC_6_G) +#define F_SD_RX_CLK_AEC_6_G V_SD_RX_CLK_AEC_6_G(1U) + +#define S_SD_RX_CLK_AEC_7_G 8 +#define V_SD_RX_CLK_AEC_7_G(x) ((x) << S_SD_RX_CLK_AEC_7_G) +#define F_SD_RX_CLK_AEC_7_G V_SD_RX_CLK_AEC_7_G(1U) + +#define S_SD_TX_CLK_AEC_0_G 7 +#define V_SD_TX_CLK_AEC_0_G(x) ((x) << S_SD_TX_CLK_AEC_0_G) +#define F_SD_TX_CLK_AEC_0_G V_SD_TX_CLK_AEC_0_G(1U) + +#define S_SD_TX_CLK_AEC_1_G 6 +#define V_SD_TX_CLK_AEC_1_G(x) ((x) << S_SD_TX_CLK_AEC_1_G) +#define F_SD_TX_CLK_AEC_1_G V_SD_TX_CLK_AEC_1_G(1U) + +#define S_SD_TX_CLK_AEC_2_G 5 +#define V_SD_TX_CLK_AEC_2_G(x) ((x) << S_SD_TX_CLK_AEC_2_G) +#define F_SD_TX_CLK_AEC_2_G V_SD_TX_CLK_AEC_2_G(1U) + +#define S_SD_TX_CLK_AEC_3_G 4 +#define V_SD_TX_CLK_AEC_3_G(x) ((x) << S_SD_TX_CLK_AEC_3_G) +#define F_SD_TX_CLK_AEC_3_G V_SD_TX_CLK_AEC_3_G(1U) + +#define S_SD_TX_CLK_AEC_4_G 3 +#define V_SD_TX_CLK_AEC_4_G(x) ((x) << S_SD_TX_CLK_AEC_4_G) +#define F_SD_TX_CLK_AEC_4_G V_SD_TX_CLK_AEC_4_G(1U) + +#define S_SD_TX_CLK_AEC_5_G 2 +#define V_SD_TX_CLK_AEC_5_G(x) ((x) << S_SD_TX_CLK_AEC_5_G) +#define F_SD_TX_CLK_AEC_5_G V_SD_TX_CLK_AEC_5_G(1U) + +#define S_SD_TX_CLK_AEC_6_G 1 +#define V_SD_TX_CLK_AEC_6_G(x) ((x) << S_SD_TX_CLK_AEC_6_G) +#define F_SD_TX_CLK_AEC_6_G V_SD_TX_CLK_AEC_6_G(1U) + +#define S_SD_TX_CLK_AEC_7_G 0 +#define V_SD_TX_CLK_AEC_7_G(x) ((x) << S_SD_TX_CLK_AEC_7_G) +#define F_SD_TX_CLK_AEC_7_G V_SD_TX_CLK_AEC_7_G(1U) + +#define A_MAC_MTIP_CLK_CTRL_3 0x3801c + +#define S_PCS_RX_CLK_0_G 31 +#define V_PCS_RX_CLK_0_G(x) ((x) << S_PCS_RX_CLK_0_G) +#define F_PCS_RX_CLK_0_G V_PCS_RX_CLK_0_G(1U) + +#define S_PCS_RX_CLK_1_G 30 +#define V_PCS_RX_CLK_1_G(x) ((x) << S_PCS_RX_CLK_1_G) +#define F_PCS_RX_CLK_1_G V_PCS_RX_CLK_1_G(1U) + +#define S_PCS_RX_CLK_2_G 29 +#define V_PCS_RX_CLK_2_G(x) ((x) << S_PCS_RX_CLK_2_G) +#define F_PCS_RX_CLK_2_G V_PCS_RX_CLK_2_G(1U) + +#define S_PCS_RX_CLK_3_G 28 +#define V_PCS_RX_CLK_3_G(x) ((x) << S_PCS_RX_CLK_3_G) +#define F_PCS_RX_CLK_3_G V_PCS_RX_CLK_3_G(1U) + +#define S_PCS_RX_CLK_4_G 27 +#define V_PCS_RX_CLK_4_G(x) ((x) << S_PCS_RX_CLK_4_G) +#define F_PCS_RX_CLK_4_G V_PCS_RX_CLK_4_G(1U) + +#define S_PCS_RX_CLK_5_G 26 +#define V_PCS_RX_CLK_5_G(x) ((x) << S_PCS_RX_CLK_5_G) +#define F_PCS_RX_CLK_5_G V_PCS_RX_CLK_5_G(1U) + +#define S_PCS_RX_CLK_6_G 25 +#define V_PCS_RX_CLK_6_G(x) ((x) << S_PCS_RX_CLK_6_G) +#define F_PCS_RX_CLK_6_G V_PCS_RX_CLK_6_G(1U) + +#define S_PCS_RX_CLK_7_G 24 +#define V_PCS_RX_CLK_7_G(x) ((x) << S_PCS_RX_CLK_7_G) +#define F_PCS_RX_CLK_7_G V_PCS_RX_CLK_7_G(1U) + +#define S_PCS_TX_CLK_0_G 23 +#define V_PCS_TX_CLK_0_G(x) ((x) << S_PCS_TX_CLK_0_G) +#define F_PCS_TX_CLK_0_G V_PCS_TX_CLK_0_G(1U) + +#define S_PCS_TX_CLK_1_G 22 +#define V_PCS_TX_CLK_1_G(x) ((x) << S_PCS_TX_CLK_1_G) +#define F_PCS_TX_CLK_1_G V_PCS_TX_CLK_1_G(1U) + +#define S_PCS_TX_CLK_2_G 21 +#define V_PCS_TX_CLK_2_G(x) ((x) << S_PCS_TX_CLK_2_G) +#define F_PCS_TX_CLK_2_G V_PCS_TX_CLK_2_G(1U) + +#define S_PCS_TX_CLK_3_G 20 +#define V_PCS_TX_CLK_3_G(x) ((x) << S_PCS_TX_CLK_3_G) +#define F_PCS_TX_CLK_3_G V_PCS_TX_CLK_3_G(1U) + +#define S_PCS_TX_CLK_4_G 19 +#define V_PCS_TX_CLK_4_G(x) ((x) << S_PCS_TX_CLK_4_G) +#define F_PCS_TX_CLK_4_G V_PCS_TX_CLK_4_G(1U) + +#define S_PCS_TX_CLK_5_G 18 +#define V_PCS_TX_CLK_5_G(x) ((x) << S_PCS_TX_CLK_5_G) +#define F_PCS_TX_CLK_5_G V_PCS_TX_CLK_5_G(1U) + +#define S_PCS_TX_CLK_6_G 17 +#define V_PCS_TX_CLK_6_G(x) ((x) << S_PCS_TX_CLK_6_G) +#define F_PCS_TX_CLK_6_G V_PCS_TX_CLK_6_G(1U) + +#define S_PCS_TX_CLK_7_G 16 +#define V_PCS_TX_CLK_7_G(x) ((x) << S_PCS_TX_CLK_7_G) +#define F_PCS_TX_CLK_7_G V_PCS_TX_CLK_7_G(1U) + +#define S_SD_RX_CLK_EN_0 15 +#define V_SD_RX_CLK_EN_0(x) ((x) << S_SD_RX_CLK_EN_0) +#define F_SD_RX_CLK_EN_0 V_SD_RX_CLK_EN_0(1U) + +#define S_SD_RX_CLK_EN_1 14 +#define V_SD_RX_CLK_EN_1(x) ((x) << S_SD_RX_CLK_EN_1) +#define F_SD_RX_CLK_EN_1 V_SD_RX_CLK_EN_1(1U) + +#define S_SD_RX_CLK_EN_2 13 +#define V_SD_RX_CLK_EN_2(x) ((x) << S_SD_RX_CLK_EN_2) +#define F_SD_RX_CLK_EN_2 V_SD_RX_CLK_EN_2(1U) + +#define S_SD_RX_CLK_EN_3 12 +#define V_SD_RX_CLK_EN_3(x) ((x) << S_SD_RX_CLK_EN_3) +#define F_SD_RX_CLK_EN_3 V_SD_RX_CLK_EN_3(1U) + +#define S_SD_RX_CLK_EN_4 11 +#define V_SD_RX_CLK_EN_4(x) ((x) << S_SD_RX_CLK_EN_4) +#define F_SD_RX_CLK_EN_4 V_SD_RX_CLK_EN_4(1U) + +#define S_SD_RX_CLK_EN_5 10 +#define V_SD_RX_CLK_EN_5(x) ((x) << S_SD_RX_CLK_EN_5) +#define F_SD_RX_CLK_EN_5 V_SD_RX_CLK_EN_5(1U) + +#define S_SD_RX_CLK_EN_6 9 +#define V_SD_RX_CLK_EN_6(x) ((x) << S_SD_RX_CLK_EN_6) +#define F_SD_RX_CLK_EN_6 V_SD_RX_CLK_EN_6(1U) + +#define S_SD_RX_CLK_EN_7 8 +#define V_SD_RX_CLK_EN_7(x) ((x) << S_SD_RX_CLK_EN_7) +#define F_SD_RX_CLK_EN_7 V_SD_RX_CLK_EN_7(1U) + +#define S_SD_TX_CLK_EN_0 7 +#define V_SD_TX_CLK_EN_0(x) ((x) << S_SD_TX_CLK_EN_0) +#define F_SD_TX_CLK_EN_0 V_SD_TX_CLK_EN_0(1U) + +#define S_SD_TX_CLK_EN_1 6 +#define V_SD_TX_CLK_EN_1(x) ((x) << S_SD_TX_CLK_EN_1) +#define F_SD_TX_CLK_EN_1 V_SD_TX_CLK_EN_1(1U) + +#define S_SD_TX_CLK_EN_2 5 +#define V_SD_TX_CLK_EN_2(x) ((x) << S_SD_TX_CLK_EN_2) +#define F_SD_TX_CLK_EN_2 V_SD_TX_CLK_EN_2(1U) + +#define S_SD_TX_CLK_EN_3 4 +#define V_SD_TX_CLK_EN_3(x) ((x) << S_SD_TX_CLK_EN_3) +#define F_SD_TX_CLK_EN_3 V_SD_TX_CLK_EN_3(1U) + +#define S_SD_TX_CLK_EN_4 3 +#define V_SD_TX_CLK_EN_4(x) ((x) << S_SD_TX_CLK_EN_4) +#define F_SD_TX_CLK_EN_4 V_SD_TX_CLK_EN_4(1U) + +#define S_SD_TX_CLK_EN_5 2 +#define V_SD_TX_CLK_EN_5(x) ((x) << S_SD_TX_CLK_EN_5) +#define F_SD_TX_CLK_EN_5 V_SD_TX_CLK_EN_5(1U) + +#define S_SD_TX_CLK_EN_6 1 +#define V_SD_TX_CLK_EN_6(x) ((x) << S_SD_TX_CLK_EN_6) +#define F_SD_TX_CLK_EN_6 V_SD_TX_CLK_EN_6(1U) + +#define S_SD_TX_CLK_EN_7 0 +#define V_SD_TX_CLK_EN_7(x) ((x) << S_SD_TX_CLK_EN_7) +#define F_SD_TX_CLK_EN_7 V_SD_TX_CLK_EN_7(1U) + +#define A_MAC_MTIP_CLK_CTRL_4 0x38020 + +#define S_SGMII_TX_CLK_0_G 7 +#define V_SGMII_TX_CLK_0_G(x) ((x) << S_SGMII_TX_CLK_0_G) +#define F_SGMII_TX_CLK_0_G V_SGMII_TX_CLK_0_G(1U) + +#define S_SGMII_TX_CLK_1_G 6 +#define V_SGMII_TX_CLK_1_G(x) ((x) << S_SGMII_TX_CLK_1_G) +#define F_SGMII_TX_CLK_1_G V_SGMII_TX_CLK_1_G(1U) + +#define S_SGMII_TX_CLK_2_G 5 +#define V_SGMII_TX_CLK_2_G(x) ((x) << S_SGMII_TX_CLK_2_G) +#define F_SGMII_TX_CLK_2_G V_SGMII_TX_CLK_2_G(1U) + +#define S_SGMII_TX_CLK_3_G 4 +#define V_SGMII_TX_CLK_3_G(x) ((x) << S_SGMII_TX_CLK_3_G) +#define F_SGMII_TX_CLK_3_G V_SGMII_TX_CLK_3_G(1U) + +#define S_SGMII_RX_CLK_0_G 3 +#define V_SGMII_RX_CLK_0_G(x) ((x) << S_SGMII_RX_CLK_0_G) +#define F_SGMII_RX_CLK_0_G V_SGMII_RX_CLK_0_G(1U) + +#define S_SGMII_RX_CLK_1_G 2 +#define V_SGMII_RX_CLK_1_G(x) ((x) << S_SGMII_RX_CLK_1_G) +#define F_SGMII_RX_CLK_1_G V_SGMII_RX_CLK_1_G(1U) + +#define S_SGMII_RX_CLK_2_G 1 +#define V_SGMII_RX_CLK_2_G(x) ((x) << S_SGMII_RX_CLK_2_G) +#define F_SGMII_RX_CLK_2_G V_SGMII_RX_CLK_2_G(1U) + +#define S_SGMII_RX_CLK_3_G 0 +#define V_SGMII_RX_CLK_3_G(x) ((x) << S_SGMII_RX_CLK_3_G) +#define F_SGMII_RX_CLK_3_G V_SGMII_RX_CLK_3_G(1U) + +#define A_MAC_PCS_CONFIG_0 0x38024 + +#define S_KP_MODE_IN 24 +#define M_KP_MODE_IN 0xffU +#define V_KP_MODE_IN(x) ((x) << S_KP_MODE_IN) +#define G_KP_MODE_IN(x) (((x) >> S_KP_MODE_IN) & M_KP_MODE_IN) + +#define S_FEC91_ENA_IN 16 +#define M_FEC91_ENA_IN 0xffU +#define V_FEC91_ENA_IN(x) ((x) << S_FEC91_ENA_IN) +#define G_FEC91_ENA_IN(x) (((x) >> S_FEC91_ENA_IN) & M_FEC91_ENA_IN) + +#define S_SD_8X 8 +#define M_SD_8X 0xffU +#define V_SD_8X(x) ((x) << S_SD_8X) +#define G_SD_8X(x) (((x) >> S_SD_8X) & M_SD_8X) + +#define S_SD_N2 0 +#define M_SD_N2 0xffU +#define V_SD_N2(x) ((x) << S_SD_N2) +#define G_SD_N2(x) (((x) >> S_SD_N2) & M_SD_N2) + +#define A_MAC_PCS_CONFIG_1 0x38028 + +#define S_FAST_1LANE_MODE 24 +#define M_FAST_1LANE_MODE 0xffU +#define V_FAST_1LANE_MODE(x) ((x) << S_FAST_1LANE_MODE) +#define G_FAST_1LANE_MODE(x) (((x) >> S_FAST_1LANE_MODE) & M_FAST_1LANE_MODE) + +#define S_PACER_10G 16 +#define M_PACER_10G 0xffU +#define V_PACER_10G(x) ((x) << S_PACER_10G) +#define G_PACER_10G(x) (((x) >> S_PACER_10G) & M_PACER_10G) + +#define S_PCS400_ENA_IN 14 +#define M_PCS400_ENA_IN 0x3U +#define V_PCS400_ENA_IN(x) ((x) << S_PCS400_ENA_IN) +#define G_PCS400_ENA_IN(x) (((x) >> S_PCS400_ENA_IN) & M_PCS400_ENA_IN) + +#define S_MODE40_ENA_IN4 13 +#define V_MODE40_ENA_IN4(x) ((x) << S_MODE40_ENA_IN4) +#define F_MODE40_ENA_IN4 V_MODE40_ENA_IN4(1U) + +#define S_MODE40_ENA_IN0 12 +#define V_MODE40_ENA_IN0(x) ((x) << S_MODE40_ENA_IN0) +#define F_MODE40_ENA_IN0 V_MODE40_ENA_IN0(1U) + +#define S_PCS100_ENA_IN6 11 +#define V_PCS100_ENA_IN6(x) ((x) << S_PCS100_ENA_IN6) +#define F_PCS100_ENA_IN6 V_PCS100_ENA_IN6(1U) + +#define S_PCS100_ENA_IN4 10 +#define V_PCS100_ENA_IN4(x) ((x) << S_PCS100_ENA_IN4) +#define F_PCS100_ENA_IN4 V_PCS100_ENA_IN4(1U) + +#define S_PCS100_ENA_IN2 9 +#define V_PCS100_ENA_IN2(x) ((x) << S_PCS100_ENA_IN2) +#define F_PCS100_ENA_IN2 V_PCS100_ENA_IN2(1U) + +#define S_PCS100_ENA_IN0 8 +#define V_PCS100_ENA_IN0(x) ((x) << S_PCS100_ENA_IN0) +#define F_PCS100_ENA_IN0 V_PCS100_ENA_IN0(1U) + +#define S_RXLAUI_ENA_IN6 7 +#define V_RXLAUI_ENA_IN6(x) ((x) << S_RXLAUI_ENA_IN6) +#define F_RXLAUI_ENA_IN6 V_RXLAUI_ENA_IN6(1U) + +#define S_RXLAUI_ENA_IN4 6 +#define V_RXLAUI_ENA_IN4(x) ((x) << S_RXLAUI_ENA_IN4) +#define F_RXLAUI_ENA_IN4 V_RXLAUI_ENA_IN4(1U) + +#define S_RXLAUI_ENA_IN2 5 +#define V_RXLAUI_ENA_IN2(x) ((x) << S_RXLAUI_ENA_IN2) +#define F_RXLAUI_ENA_IN2 V_RXLAUI_ENA_IN2(1U) + +#define S_RXLAUI_ENA_IN0 4 +#define V_RXLAUI_ENA_IN0(x) ((x) << S_RXLAUI_ENA_IN0) +#define F_RXLAUI_ENA_IN0 V_RXLAUI_ENA_IN0(1U) + +#define S_FEC91_LANE_IN6 3 +#define V_FEC91_LANE_IN6(x) ((x) << S_FEC91_LANE_IN6) +#define F_FEC91_LANE_IN6 V_FEC91_LANE_IN6(1U) + +#define S_FEC91_LANE_IN4 2 +#define V_FEC91_LANE_IN4(x) ((x) << S_FEC91_LANE_IN4) +#define F_FEC91_LANE_IN4 V_FEC91_LANE_IN4(1U) + +#define S_FEC91_LANE_IN2 1 +#define V_FEC91_LANE_IN2(x) ((x) << S_FEC91_LANE_IN2) +#define F_FEC91_LANE_IN2 V_FEC91_LANE_IN2(1U) + +#define S_FEC91_LANE_IN0 0 +#define V_FEC91_LANE_IN0(x) ((x) << S_FEC91_LANE_IN0) +#define F_FEC91_LANE_IN0 V_FEC91_LANE_IN0(1U) + +#define A_MAC_PCS_CONFIG_2 0x3802c + +#define S_SGPCS_EN_3 29 +#define V_SGPCS_EN_3(x) ((x) << S_SGPCS_EN_3) +#define F_SGPCS_EN_3 V_SGPCS_EN_3(1U) + +#define S_SGPCS_EN_2 28 +#define V_SGPCS_EN_2(x) ((x) << S_SGPCS_EN_2) +#define F_SGPCS_EN_2 V_SGPCS_EN_2(1U) + +#define S_SGPCS_EN_1 27 +#define V_SGPCS_EN_1(x) ((x) << S_SGPCS_EN_1) +#define F_SGPCS_EN_1 V_SGPCS_EN_1(1U) + +#define S_SGPCS_EN_0 26 +#define V_SGPCS_EN_0(x) ((x) << S_SGPCS_EN_0) +#define F_SGPCS_EN_0 V_SGPCS_EN_0(1U) + +#define S_CFG_CLOCK_RATE 22 +#define M_CFG_CLOCK_RATE 0xfU +#define V_CFG_CLOCK_RATE(x) ((x) << S_CFG_CLOCK_RATE) +#define G_CFG_CLOCK_RATE(x) (((x) >> S_CFG_CLOCK_RATE) & M_CFG_CLOCK_RATE) + +#define S_FEC_ERR_ENA 14 +#define M_FEC_ERR_ENA 0xffU +#define V_FEC_ERR_ENA(x) ((x) << S_FEC_ERR_ENA) +#define G_FEC_ERR_ENA(x) (((x) >> S_FEC_ERR_ENA) & M_FEC_ERR_ENA) + +#define S_FEC_ENA 6 +#define M_FEC_ENA 0xffU +#define V_FEC_ENA(x) ((x) << S_FEC_ENA) +#define G_FEC_ENA(x) (((x) >> S_FEC_ENA) & M_FEC_ENA) + +#define S_PCS001_TX_AM_SF 3 +#define M_PCS001_TX_AM_SF 0x7U +#define V_PCS001_TX_AM_SF(x) ((x) << S_PCS001_TX_AM_SF) +#define G_PCS001_TX_AM_SF(x) (((x) >> S_PCS001_TX_AM_SF) & M_PCS001_TX_AM_SF) + +#define S_PCS000_TX_AM_SF 0 +#define M_PCS000_TX_AM_SF 0x7U +#define V_PCS000_TX_AM_SF(x) ((x) << S_PCS000_TX_AM_SF) +#define G_PCS000_TX_AM_SF(x) (((x) >> S_PCS000_TX_AM_SF) & M_PCS000_TX_AM_SF) + +#define A_MAC_PCS_STATUS_0 0x38030 + +#define S_PCS000_ALIGN_LOCK 30 +#define M_PCS000_ALIGN_LOCK 0x3U +#define V_PCS000_ALIGN_LOCK(x) ((x) << S_PCS000_ALIGN_LOCK) +#define G_PCS000_ALIGN_LOCK(x) (((x) >> S_PCS000_ALIGN_LOCK) & M_PCS000_ALIGN_LOCK) + +#define S_PCS000_HI_SER 28 +#define M_PCS000_HI_SER 0x3U +#define V_PCS000_HI_SER(x) ((x) << S_PCS000_HI_SER) +#define G_PCS000_HI_SER(x) (((x) >> S_PCS000_HI_SER) & M_PCS000_HI_SER) + +#define S_BER_TIMER_DONE 20 +#define M_BER_TIMER_DONE 0xffU +#define V_BER_TIMER_DONE(x) ((x) << S_BER_TIMER_DONE) +#define G_BER_TIMER_DONE(x) (((x) >> S_BER_TIMER_DONE) & M_BER_TIMER_DONE) + +#define S_T7_AMPS_LOCK 4 +#define M_T7_AMPS_LOCK 0xffffU +#define V_T7_AMPS_LOCK(x) ((x) << S_T7_AMPS_LOCK) +#define G_T7_AMPS_LOCK(x) (((x) >> S_T7_AMPS_LOCK) & M_T7_AMPS_LOCK) + +#define S_T7_ALIGN_DONE 0 +#define M_T7_ALIGN_DONE 0xfU +#define V_T7_ALIGN_DONE(x) ((x) << S_T7_ALIGN_DONE) +#define G_T7_ALIGN_DONE(x) (((x) >> S_T7_ALIGN_DONE) & M_T7_ALIGN_DONE) + +#define A_MAC_PCS_STATUS_1 0x38034 +#define A_MAC_PCS_STATUS_2 0x38038 + +#define S_RSFEC_ALIGNED 24 +#define M_RSFEC_ALIGNED 0xffU +#define V_RSFEC_ALIGNED(x) ((x) << S_RSFEC_ALIGNED) +#define G_RSFEC_ALIGNED(x) (((x) >> S_RSFEC_ALIGNED) & M_RSFEC_ALIGNED) + +#define S_T7_FEC_LOCKED 8 +#define M_T7_FEC_LOCKED 0xffffU +#define V_T7_FEC_LOCKED(x) ((x) << S_T7_FEC_LOCKED) +#define G_T7_FEC_LOCKED(x) (((x) >> S_T7_FEC_LOCKED) & M_T7_FEC_LOCKED) + +#define S_T7_BLOCK_LOCK 0 +#define M_T7_BLOCK_LOCK 0xffU +#define V_T7_BLOCK_LOCK(x) ((x) << S_T7_BLOCK_LOCK) +#define G_T7_BLOCK_LOCK(x) (((x) >> S_T7_BLOCK_LOCK) & M_T7_BLOCK_LOCK) + +#define A_MAC_PCS_STATUS_3 0x3803c + +#define S_FEC_NCERR 16 +#define M_FEC_NCERR 0xffffU +#define V_FEC_NCERR(x) ((x) << S_FEC_NCERR) +#define G_FEC_NCERR(x) (((x) >> S_FEC_NCERR) & M_FEC_NCERR) + +#define S_FEC_CERR 0 +#define M_FEC_CERR 0xffffU +#define V_FEC_CERR(x) ((x) << S_FEC_CERR) +#define G_FEC_CERR(x) (((x) >> S_FEC_CERR) & M_FEC_CERR) + +#define A_MAC_PCS_STATUS_4 0x38040 + +#define S_MAC1_RES_SPEED 23 +#define M_MAC1_RES_SPEED 0xffU +#define V_MAC1_RES_SPEED(x) ((x) << S_MAC1_RES_SPEED) +#define G_MAC1_RES_SPEED(x) (((x) >> S_MAC1_RES_SPEED) & M_MAC1_RES_SPEED) + +#define S_MAC0_RES_SPEED 14 +#define M_MAC0_RES_SPEED 0xffU +#define V_MAC0_RES_SPEED(x) ((x) << S_MAC0_RES_SPEED) +#define G_MAC0_RES_SPEED(x) (((x) >> S_MAC0_RES_SPEED) & M_MAC0_RES_SPEED) + +#define S_PCS400_ENA_IN_REF 12 +#define M_PCS400_ENA_IN_REF 0x3U +#define V_PCS400_ENA_IN_REF(x) ((x) << S_PCS400_ENA_IN_REF) +#define G_PCS400_ENA_IN_REF(x) (((x) >> S_PCS400_ENA_IN_REF) & M_PCS400_ENA_IN_REF) + +#define S_PCS000_DEGRADE_SER 10 +#define M_PCS000_DEGRADE_SER 0x3U +#define V_PCS000_DEGRADE_SER(x) ((x) << S_PCS000_DEGRADE_SER) +#define G_PCS000_DEGRADE_SER(x) (((x) >> S_PCS000_DEGRADE_SER) & M_PCS000_DEGRADE_SER) + +#define S_P4X_SIGNAL_OK 8 +#define M_P4X_SIGNAL_OK 0x3U +#define V_P4X_SIGNAL_OK(x) ((x) << S_P4X_SIGNAL_OK) +#define G_P4X_SIGNAL_OK(x) (((x) >> S_P4X_SIGNAL_OK) & M_P4X_SIGNAL_OK) + +#define S_MODE200_IND_REF 7 +#define V_MODE200_IND_REF(x) ((x) << S_MODE200_IND_REF) +#define F_MODE200_IND_REF V_MODE200_IND_REF(1U) + +#define S_MODE200_8X26_IND_REF 6 +#define V_MODE200_8X26_IND_REF(x) ((x) << S_MODE200_8X26_IND_REF) +#define F_MODE200_8X26_IND_REF V_MODE200_8X26_IND_REF(1U) + +#define S_PCS001_RX_AM_SF 3 +#define M_PCS001_RX_AM_SF 0x7U +#define V_PCS001_RX_AM_SF(x) ((x) << S_PCS001_RX_AM_SF) +#define G_PCS001_RX_AM_SF(x) (((x) >> S_PCS001_RX_AM_SF) & M_PCS001_RX_AM_SF) + +#define S_PCS000_RX_AM_SF 0 +#define M_PCS000_RX_AM_SF 0x7U +#define V_PCS000_RX_AM_SF(x) ((x) << S_PCS000_RX_AM_SF) +#define G_PCS000_RX_AM_SF(x) (((x) >> S_PCS000_RX_AM_SF) & M_PCS000_RX_AM_SF) + +#define A_MAC_PCS_STATUS_5 0x38044 + +#define S_MAC5_RES_SPEED 24 +#define M_MAC5_RES_SPEED 0xffU +#define V_MAC5_RES_SPEED(x) ((x) << S_MAC5_RES_SPEED) +#define G_MAC5_RES_SPEED(x) (((x) >> S_MAC5_RES_SPEED) & M_MAC5_RES_SPEED) + +#define S_MAC4_RES_SPEED 16 +#define M_MAC4_RES_SPEED 0xffU +#define V_MAC4_RES_SPEED(x) ((x) << S_MAC4_RES_SPEED) +#define G_MAC4_RES_SPEED(x) (((x) >> S_MAC4_RES_SPEED) & M_MAC4_RES_SPEED) + +#define S_MAC3_RES_SPEED 8 +#define M_MAC3_RES_SPEED 0xffU +#define V_MAC3_RES_SPEED(x) ((x) << S_MAC3_RES_SPEED) +#define G_MAC3_RES_SPEED(x) (((x) >> S_MAC3_RES_SPEED) & M_MAC3_RES_SPEED) + +#define S_MAC2_RES_SPEED 0 +#define M_MAC2_RES_SPEED 0xffU +#define V_MAC2_RES_SPEED(x) ((x) << S_MAC2_RES_SPEED) +#define G_MAC2_RES_SPEED(x) (((x) >> S_MAC2_RES_SPEED) & M_MAC2_RES_SPEED) + +#define A_MAC_PCS_STATUS_6 0x38048 + +#define S_MARKER_INS_CNT_100_00 16 +#define M_MARKER_INS_CNT_100_00 0x7fffU +#define V_MARKER_INS_CNT_100_00(x) ((x) << S_MARKER_INS_CNT_100_00) +#define G_MARKER_INS_CNT_100_00(x) (((x) >> S_MARKER_INS_CNT_100_00) & M_MARKER_INS_CNT_100_00) + +#define S_MAC7_RES_SPEED 8 +#define M_MAC7_RES_SPEED 0xffU +#define V_MAC7_RES_SPEED(x) ((x) << S_MAC7_RES_SPEED) +#define G_MAC7_RES_SPEED(x) (((x) >> S_MAC7_RES_SPEED) & M_MAC7_RES_SPEED) + +#define S_MAC6_RES_SPEED 0 +#define M_MAC6_RES_SPEED 0xffU +#define V_MAC6_RES_SPEED(x) ((x) << S_MAC6_RES_SPEED) +#define G_MAC6_RES_SPEED(x) (((x) >> S_MAC6_RES_SPEED) & M_MAC6_RES_SPEED) + +#define A_MAC_PCS_STATUS_7 0x3804c + +#define S_PCS000_LINK_STATUS 30 +#define M_PCS000_LINK_STATUS 0x3U +#define V_PCS000_LINK_STATUS(x) ((x) << S_PCS000_LINK_STATUS) +#define G_PCS000_LINK_STATUS(x) (((x) >> S_PCS000_LINK_STATUS) & M_PCS000_LINK_STATUS) + +#define S_MARKER_INS_CNT_100_02 15 +#define M_MARKER_INS_CNT_100_02 0x7fffU +#define V_MARKER_INS_CNT_100_02(x) ((x) << S_MARKER_INS_CNT_100_02) +#define G_MARKER_INS_CNT_100_02(x) (((x) >> S_MARKER_INS_CNT_100_02) & M_MARKER_INS_CNT_100_02) + +#define S_MARKER_INS_CNT_100_01 0 +#define M_MARKER_INS_CNT_100_01 0x7fffU +#define V_MARKER_INS_CNT_100_01(x) ((x) << S_MARKER_INS_CNT_100_01) +#define G_MARKER_INS_CNT_100_01(x) (((x) >> S_MARKER_INS_CNT_100_01) & M_MARKER_INS_CNT_100_01) + +#define A_MAC_PCS_STATUS_8 0x38050 + +#define S_MARKER_INS_CNT_25_1 15 +#define M_MARKER_INS_CNT_25_1 0xffffU +#define V_MARKER_INS_CNT_25_1(x) ((x) << S_MARKER_INS_CNT_25_1) +#define G_MARKER_INS_CNT_25_1(x) (((x) >> S_MARKER_INS_CNT_25_1) & M_MARKER_INS_CNT_25_1) + +#define S_MARKER_INS_CNT_100_03 0 +#define M_MARKER_INS_CNT_100_03 0x7fffU +#define V_MARKER_INS_CNT_100_03(x) ((x) << S_MARKER_INS_CNT_100_03) +#define G_MARKER_INS_CNT_100_03(x) (((x) >> S_MARKER_INS_CNT_100_03) & M_MARKER_INS_CNT_100_03) + +#define A_MAC_PCS_STATUS_9 0x38054 + +#define S_MARKER_INS_CNT_25_5 16 +#define M_MARKER_INS_CNT_25_5 0xffffU +#define V_MARKER_INS_CNT_25_5(x) ((x) << S_MARKER_INS_CNT_25_5) +#define G_MARKER_INS_CNT_25_5(x) (((x) >> S_MARKER_INS_CNT_25_5) & M_MARKER_INS_CNT_25_5) + +#define S_MARKER_INS_CNT_25_3 0 +#define M_MARKER_INS_CNT_25_3 0xffffU +#define V_MARKER_INS_CNT_25_3(x) ((x) << S_MARKER_INS_CNT_25_3) +#define G_MARKER_INS_CNT_25_3(x) (((x) >> S_MARKER_INS_CNT_25_3) & M_MARKER_INS_CNT_25_3) + +#define A_MAC_PCS_STATUS_10 0x38058 + +#define S_MARKER_INS_CNT_25_50_2 16 +#define M_MARKER_INS_CNT_25_50_2 0xffffU +#define V_MARKER_INS_CNT_25_50_2(x) ((x) << S_MARKER_INS_CNT_25_50_2) +#define G_MARKER_INS_CNT_25_50_2(x) (((x) >> S_MARKER_INS_CNT_25_50_2) & M_MARKER_INS_CNT_25_50_2) + +#define S_MARKER_INS_CNT_25_50_0 0 +#define M_MARKER_INS_CNT_25_50_0 0xffffU +#define V_MARKER_INS_CNT_25_50_0(x) ((x) << S_MARKER_INS_CNT_25_50_0) +#define G_MARKER_INS_CNT_25_50_0(x) (((x) >> S_MARKER_INS_CNT_25_50_0) & M_MARKER_INS_CNT_25_50_0) + +#define A_MAC_PCS_STATUS_11 0x3805c + +#define S_MARKER_INS_CNT_25_50_6 16 +#define M_MARKER_INS_CNT_25_50_6 0xffffU +#define V_MARKER_INS_CNT_25_50_6(x) ((x) << S_MARKER_INS_CNT_25_50_6) +#define G_MARKER_INS_CNT_25_50_6(x) (((x) >> S_MARKER_INS_CNT_25_50_6) & M_MARKER_INS_CNT_25_50_6) + +#define S_MARKER_INS_CNT_25_50_4 0 +#define M_MARKER_INS_CNT_25_50_4 0xffffU +#define V_MARKER_INS_CNT_25_50_4(x) ((x) << S_MARKER_INS_CNT_25_50_4) +#define G_MARKER_INS_CNT_25_50_4(x) (((x) >> S_MARKER_INS_CNT_25_50_4) & M_MARKER_INS_CNT_25_50_4) + +#define A_MAC_PCS_STATUS_12 0x38060 + +#define S_T7_LINK_STATUS 24 +#define M_T7_LINK_STATUS 0xffU +#define V_T7_LINK_STATUS(x) ((x) << S_T7_LINK_STATUS) +#define G_T7_LINK_STATUS(x) (((x) >> S_T7_LINK_STATUS) & M_T7_LINK_STATUS) + +#define S_T7_HI_BER 16 +#define M_T7_HI_BER 0xffU +#define V_T7_HI_BER(x) ((x) << S_T7_HI_BER) +#define G_T7_HI_BER(x) (((x) >> S_T7_HI_BER) & M_T7_HI_BER) + +#define S_MARKER_INS_CNT_25_7 0 +#define M_MARKER_INS_CNT_25_7 0xffffU +#define V_MARKER_INS_CNT_25_7(x) ((x) << S_MARKER_INS_CNT_25_7) +#define G_MARKER_INS_CNT_25_7(x) (((x) >> S_MARKER_INS_CNT_25_7) & M_MARKER_INS_CNT_25_7) + +#define A_MAC_MAC200G400G_0_CONFIG_0 0x38064 +#define A_MAC_MAC200G400G_0_CONFIG_1 0x38068 + +#define S_FF_TX_CRC_OVR 11 +#define V_FF_TX_CRC_OVR(x) ((x) << S_FF_TX_CRC_OVR) +#define F_FF_TX_CRC_OVR V_FF_TX_CRC_OVR(1U) + +#define S_TX_SMHOLD 2 +#define V_TX_SMHOLD(x) ((x) << S_TX_SMHOLD) +#define F_TX_SMHOLD V_TX_SMHOLD(1U) + +#define A_MAC_MAC200G400G_0_CONFIG_2 0x3806c +#define A_MAC_MAC200G400G_0_CONFIG_3 0x38070 +#define A_MAC_MAC200G400G_0_CONFIG_4 0x38074 + +#define S_FRC_DELTA 0 +#define M_FRC_DELTA 0xffffU +#define V_FRC_DELTA(x) ((x) << S_FRC_DELTA) +#define G_FRC_DELTA(x) (((x) >> S_FRC_DELTA) & M_FRC_DELTA) + +#define A_MAC_MAC200G400G_0_STATUS 0x38078 + +#define S_T7_LOOP_ENA 4 +#define V_T7_LOOP_ENA(x) ((x) << S_T7_LOOP_ENA) +#define F_T7_LOOP_ENA V_T7_LOOP_ENA(1U) + +#define S_T7_LOC_FAULT 3 +#define V_T7_LOC_FAULT(x) ((x) << S_T7_LOC_FAULT) +#define F_T7_LOC_FAULT V_T7_LOC_FAULT(1U) + +#define S_FRM_DROP 2 +#define V_FRM_DROP(x) ((x) << S_FRM_DROP) +#define F_FRM_DROP V_FRM_DROP(1U) + +#define S_FF_TX_CREDIT 1 +#define V_FF_TX_CREDIT(x) ((x) << S_FF_TX_CREDIT) +#define F_FF_TX_CREDIT V_FF_TX_CREDIT(1U) + +#define A_MAC_MAC200G400G_1_CONFIG_0 0x3807c +#define A_MAC_MAC200G400G_1_CONFIG_1 0x38080 +#define A_MAC_MAC200G400G_1_CONFIG_2 0x38084 +#define A_MAC_MAC200G400G_1_CONFIG_3 0x38088 +#define A_MAC_MAC200G400G_1_CONFIG_4 0x3808c +#define A_MAC_MAC200G400G_1_STATUS 0x38090 +#define A_MAC_AN_CFG_0 0x38094 + +#define S_T7_AN_DATA_CTL 24 +#define M_T7_AN_DATA_CTL 0xffU +#define V_T7_AN_DATA_CTL(x) ((x) << S_T7_AN_DATA_CTL) +#define G_T7_AN_DATA_CTL(x) (((x) >> S_T7_AN_DATA_CTL) & M_T7_AN_DATA_CTL) + +#define S_T7_AN_ENA 16 +#define M_T7_AN_ENA 0xffU +#define V_T7_AN_ENA(x) ((x) << S_T7_AN_ENA) +#define G_T7_AN_ENA(x) (((x) >> S_T7_AN_ENA) & M_T7_AN_ENA) + +#define A_MAC_AN_CFG_1 0x38098 + +#define S_AN_DIS_TIMER_AN_7 7 +#define V_AN_DIS_TIMER_AN_7(x) ((x) << S_AN_DIS_TIMER_AN_7) +#define F_AN_DIS_TIMER_AN_7 V_AN_DIS_TIMER_AN_7(1U) + +#define S_AN_DIS_TIMER_AN_6 6 +#define V_AN_DIS_TIMER_AN_6(x) ((x) << S_AN_DIS_TIMER_AN_6) +#define F_AN_DIS_TIMER_AN_6 V_AN_DIS_TIMER_AN_6(1U) + +#define S_AN_DIS_TIMER_AN_5 5 +#define V_AN_DIS_TIMER_AN_5(x) ((x) << S_AN_DIS_TIMER_AN_5) +#define F_AN_DIS_TIMER_AN_5 V_AN_DIS_TIMER_AN_5(1U) + +#define S_AN_DIS_TIMER_AN_4 4 +#define V_AN_DIS_TIMER_AN_4(x) ((x) << S_AN_DIS_TIMER_AN_4) +#define F_AN_DIS_TIMER_AN_4 V_AN_DIS_TIMER_AN_4(1U) + +#define S_AN_DIS_TIMER_AN_3 3 +#define V_AN_DIS_TIMER_AN_3(x) ((x) << S_AN_DIS_TIMER_AN_3) +#define F_AN_DIS_TIMER_AN_3 V_AN_DIS_TIMER_AN_3(1U) + +#define S_AN_DIS_TIMER_AN_2 2 +#define V_AN_DIS_TIMER_AN_2(x) ((x) << S_AN_DIS_TIMER_AN_2) +#define F_AN_DIS_TIMER_AN_2 V_AN_DIS_TIMER_AN_2(1U) + +#define S_AN_DIS_TIMER_AN_1 1 +#define V_AN_DIS_TIMER_AN_1(x) ((x) << S_AN_DIS_TIMER_AN_1) +#define F_AN_DIS_TIMER_AN_1 V_AN_DIS_TIMER_AN_1(1U) + +#define S_AN_DIS_TIMER_AN_0 0 +#define V_AN_DIS_TIMER_AN_0(x) ((x) << S_AN_DIS_TIMER_AN_0) +#define F_AN_DIS_TIMER_AN_0 V_AN_DIS_TIMER_AN_0(1U) + +#define A_MAC_AN_SERDES25G_ENA 0x3809c + +#define S_AN_SD25_TX_ENA_7 15 +#define V_AN_SD25_TX_ENA_7(x) ((x) << S_AN_SD25_TX_ENA_7) +#define F_AN_SD25_TX_ENA_7 V_AN_SD25_TX_ENA_7(1U) + +#define S_AN_SD25_TX_ENA_6 14 +#define V_AN_SD25_TX_ENA_6(x) ((x) << S_AN_SD25_TX_ENA_6) +#define F_AN_SD25_TX_ENA_6 V_AN_SD25_TX_ENA_6(1U) + +#define S_AN_SD25_TX_ENA_5 13 +#define V_AN_SD25_TX_ENA_5(x) ((x) << S_AN_SD25_TX_ENA_5) +#define F_AN_SD25_TX_ENA_5 V_AN_SD25_TX_ENA_5(1U) + +#define S_AN_SD25_TX_ENA_4 12 +#define V_AN_SD25_TX_ENA_4(x) ((x) << S_AN_SD25_TX_ENA_4) +#define F_AN_SD25_TX_ENA_4 V_AN_SD25_TX_ENA_4(1U) + +#define S_AN_SD25_TX_ENA_3 11 +#define V_AN_SD25_TX_ENA_3(x) ((x) << S_AN_SD25_TX_ENA_3) +#define F_AN_SD25_TX_ENA_3 V_AN_SD25_TX_ENA_3(1U) + +#define S_AN_SD25_TX_ENA_2 10 +#define V_AN_SD25_TX_ENA_2(x) ((x) << S_AN_SD25_TX_ENA_2) +#define F_AN_SD25_TX_ENA_2 V_AN_SD25_TX_ENA_2(1U) + +#define S_AN_SD25_TX_ENA_1 9 +#define V_AN_SD25_TX_ENA_1(x) ((x) << S_AN_SD25_TX_ENA_1) +#define F_AN_SD25_TX_ENA_1 V_AN_SD25_TX_ENA_1(1U) + +#define S_AN_SD25_TX_ENA_0 8 +#define V_AN_SD25_TX_ENA_0(x) ((x) << S_AN_SD25_TX_ENA_0) +#define F_AN_SD25_TX_ENA_0 V_AN_SD25_TX_ENA_0(1U) + +#define S_AN_SD25_RX_ENA_7 7 +#define V_AN_SD25_RX_ENA_7(x) ((x) << S_AN_SD25_RX_ENA_7) +#define F_AN_SD25_RX_ENA_7 V_AN_SD25_RX_ENA_7(1U) + +#define S_AN_SD25_RX_ENA_6 6 +#define V_AN_SD25_RX_ENA_6(x) ((x) << S_AN_SD25_RX_ENA_6) +#define F_AN_SD25_RX_ENA_6 V_AN_SD25_RX_ENA_6(1U) + +#define S_AN_SD25_RX_ENA_5 5 +#define V_AN_SD25_RX_ENA_5(x) ((x) << S_AN_SD25_RX_ENA_5) +#define F_AN_SD25_RX_ENA_5 V_AN_SD25_RX_ENA_5(1U) + +#define S_AN_SD25_RX_ENA_4 4 +#define V_AN_SD25_RX_ENA_4(x) ((x) << S_AN_SD25_RX_ENA_4) +#define F_AN_SD25_RX_ENA_4 V_AN_SD25_RX_ENA_4(1U) + +#define S_AN_SD25_RX_ENA_3 3 +#define V_AN_SD25_RX_ENA_3(x) ((x) << S_AN_SD25_RX_ENA_3) +#define F_AN_SD25_RX_ENA_3 V_AN_SD25_RX_ENA_3(1U) + +#define S_AN_SD25_RX_ENA_2 2 +#define V_AN_SD25_RX_ENA_2(x) ((x) << S_AN_SD25_RX_ENA_2) +#define F_AN_SD25_RX_ENA_2 V_AN_SD25_RX_ENA_2(1U) + +#define S_AN_SD25_RX_ENA_1 1 +#define V_AN_SD25_RX_ENA_1(x) ((x) << S_AN_SD25_RX_ENA_1) +#define F_AN_SD25_RX_ENA_1 V_AN_SD25_RX_ENA_1(1U) + +#define S_AN_SD25_RX_ENA_0 0 +#define V_AN_SD25_RX_ENA_0(x) ((x) << S_AN_SD25_RX_ENA_0) +#define F_AN_SD25_RX_ENA_0 V_AN_SD25_RX_ENA_0(1U) + +#define A_MAC_PLL_CFG_0 0x380a0 + +#define S_USE_RX_CDR_CLK_FOR_TX 7 +#define V_USE_RX_CDR_CLK_FOR_TX(x) ((x) << S_USE_RX_CDR_CLK_FOR_TX) +#define F_USE_RX_CDR_CLK_FOR_TX V_USE_RX_CDR_CLK_FOR_TX(1U) + +#define S_HSSPLLSEL0 5 +#define M_HSSPLLSEL0 0x3U +#define V_HSSPLLSEL0(x) ((x) << S_HSSPLLSEL0) +#define G_HSSPLLSEL0(x) (((x) >> S_HSSPLLSEL0) & M_HSSPLLSEL0) + +#define S_HSSTXDIV2CLK_SEL0 3 +#define M_HSSTXDIV2CLK_SEL0 0x3U +#define V_HSSTXDIV2CLK_SEL0(x) ((x) << S_HSSTXDIV2CLK_SEL0) +#define G_HSSTXDIV2CLK_SEL0(x) (((x) >> S_HSSTXDIV2CLK_SEL0) & M_HSSTXDIV2CLK_SEL0) + +#define S_HSS_RESET0 2 +#define V_HSS_RESET0(x) ((x) << S_HSS_RESET0) +#define F_HSS_RESET0 V_HSS_RESET0(1U) + +#define S_APB_RESET0 1 +#define V_APB_RESET0(x) ((x) << S_APB_RESET0) +#define F_APB_RESET0 V_APB_RESET0(1U) + +#define S_HSSCLK32DIV2_RESET0 0 +#define V_HSSCLK32DIV2_RESET0(x) ((x) << S_HSSCLK32DIV2_RESET0) +#define F_HSSCLK32DIV2_RESET0 V_HSSCLK32DIV2_RESET0(1U) + +#define A_MAC_PLL_CFG_1 0x380a4 + +#define S_HSSPLLSEL1 5 +#define M_HSSPLLSEL1 0x3U +#define V_HSSPLLSEL1(x) ((x) << S_HSSPLLSEL1) +#define G_HSSPLLSEL1(x) (((x) >> S_HSSPLLSEL1) & M_HSSPLLSEL1) + +#define S_HSSTXDIV2CLK_SEL1 3 +#define M_HSSTXDIV2CLK_SEL1 0x3U +#define V_HSSTXDIV2CLK_SEL1(x) ((x) << S_HSSTXDIV2CLK_SEL1) +#define G_HSSTXDIV2CLK_SEL1(x) (((x) >> S_HSSTXDIV2CLK_SEL1) & M_HSSTXDIV2CLK_SEL1) + +#define S_HSS_RESET1 2 +#define V_HSS_RESET1(x) ((x) << S_HSS_RESET1) +#define F_HSS_RESET1 V_HSS_RESET1(1U) + +#define S_APB_RESET1 1 +#define V_APB_RESET1(x) ((x) << S_APB_RESET1) +#define F_APB_RESET1 V_APB_RESET1(1U) + +#define S_HSSCLK32DIV2_RESET1 0 +#define V_HSSCLK32DIV2_RESET1(x) ((x) << S_HSSCLK32DIV2_RESET1) +#define F_HSSCLK32DIV2_RESET1 V_HSSCLK32DIV2_RESET1(1U) + +#define A_MAC_PLL_CFG_2 0x380a8 + +#define S_HSSPLLSEL2 5 +#define M_HSSPLLSEL2 0x3U +#define V_HSSPLLSEL2(x) ((x) << S_HSSPLLSEL2) +#define G_HSSPLLSEL2(x) (((x) >> S_HSSPLLSEL2) & M_HSSPLLSEL2) + +#define S_HSSTXDIV2CLK_SEL2 3 +#define M_HSSTXDIV2CLK_SEL2 0x3U +#define V_HSSTXDIV2CLK_SEL2(x) ((x) << S_HSSTXDIV2CLK_SEL2) +#define G_HSSTXDIV2CLK_SEL2(x) (((x) >> S_HSSTXDIV2CLK_SEL2) & M_HSSTXDIV2CLK_SEL2) + +#define S_HSS_RESET2 2 +#define V_HSS_RESET2(x) ((x) << S_HSS_RESET2) +#define F_HSS_RESET2 V_HSS_RESET2(1U) + +#define S_APB_RESET2 1 +#define V_APB_RESET2(x) ((x) << S_APB_RESET2) +#define F_APB_RESET2 V_APB_RESET2(1U) + +#define S_HSSCLK32DIV2_RESET2 0 +#define V_HSSCLK32DIV2_RESET2(x) ((x) << S_HSSCLK32DIV2_RESET2) +#define F_HSSCLK32DIV2_RESET2 V_HSSCLK32DIV2_RESET2(1U) + +#define A_MAC_PLL_CFG_3 0x380ac + +#define S_HSSPLLSEL3 5 +#define M_HSSPLLSEL3 0x3U +#define V_HSSPLLSEL3(x) ((x) << S_HSSPLLSEL3) +#define G_HSSPLLSEL3(x) (((x) >> S_HSSPLLSEL3) & M_HSSPLLSEL3) + +#define S_HSSTXDIV2CLK_SEL3 3 +#define M_HSSTXDIV2CLK_SEL3 0x3U +#define V_HSSTXDIV2CLK_SEL3(x) ((x) << S_HSSTXDIV2CLK_SEL3) +#define G_HSSTXDIV2CLK_SEL3(x) (((x) >> S_HSSTXDIV2CLK_SEL3) & M_HSSTXDIV2CLK_SEL3) + +#define S_HSS_RESET3 2 +#define V_HSS_RESET3(x) ((x) << S_HSS_RESET3) +#define F_HSS_RESET3 V_HSS_RESET3(1U) + +#define S_APB_RESET3 1 +#define V_APB_RESET3(x) ((x) << S_APB_RESET3) +#define F_APB_RESET3 V_APB_RESET3(1U) + +#define S_HSSCLK32DIV2_RESET3 0 +#define V_HSSCLK32DIV2_RESET3(x) ((x) << S_HSSCLK32DIV2_RESET3) +#define F_HSSCLK32DIV2_RESET3 V_HSSCLK32DIV2_RESET3(1U) + +#define A_MAC_HSS_STATUS 0x380b0 + +#define S_TX_LANE_PLL_SEL_3 30 +#define M_TX_LANE_PLL_SEL_3 0x3U +#define V_TX_LANE_PLL_SEL_3(x) ((x) << S_TX_LANE_PLL_SEL_3) +#define G_TX_LANE_PLL_SEL_3(x) (((x) >> S_TX_LANE_PLL_SEL_3) & M_TX_LANE_PLL_SEL_3) + +#define S_TX_LANE_PLL_SEL_2 28 +#define M_TX_LANE_PLL_SEL_2 0x3U +#define V_TX_LANE_PLL_SEL_2(x) ((x) << S_TX_LANE_PLL_SEL_2) +#define G_TX_LANE_PLL_SEL_2(x) (((x) >> S_TX_LANE_PLL_SEL_2) & M_TX_LANE_PLL_SEL_2) + +#define S_TX_LANE_PLL_SEL_1 26 +#define M_TX_LANE_PLL_SEL_1 0x3U +#define V_TX_LANE_PLL_SEL_1(x) ((x) << S_TX_LANE_PLL_SEL_1) +#define G_TX_LANE_PLL_SEL_1(x) (((x) >> S_TX_LANE_PLL_SEL_1) & M_TX_LANE_PLL_SEL_1) + +#define S_TX_LANE_PLL_SEL_0 24 +#define M_TX_LANE_PLL_SEL_0 0x3U +#define V_TX_LANE_PLL_SEL_0(x) ((x) << S_TX_LANE_PLL_SEL_0) +#define G_TX_LANE_PLL_SEL_0(x) (((x) >> S_TX_LANE_PLL_SEL_0) & M_TX_LANE_PLL_SEL_0) + +#define S_HSSPLLLOCKB_HSS3 7 +#define V_HSSPLLLOCKB_HSS3(x) ((x) << S_HSSPLLLOCKB_HSS3) +#define F_HSSPLLLOCKB_HSS3 V_HSSPLLLOCKB_HSS3(1U) + +#define S_HSSPLLLOCKA_HSS3 6 +#define V_HSSPLLLOCKA_HSS3(x) ((x) << S_HSSPLLLOCKA_HSS3) +#define F_HSSPLLLOCKA_HSS3 V_HSSPLLLOCKA_HSS3(1U) + +#define S_HSSPLLLOCKB_HSS2 5 +#define V_HSSPLLLOCKB_HSS2(x) ((x) << S_HSSPLLLOCKB_HSS2) +#define F_HSSPLLLOCKB_HSS2 V_HSSPLLLOCKB_HSS2(1U) + +#define S_HSSPLLLOCKA_HSS2 4 +#define V_HSSPLLLOCKA_HSS2(x) ((x) << S_HSSPLLLOCKA_HSS2) +#define F_HSSPLLLOCKA_HSS2 V_HSSPLLLOCKA_HSS2(1U) + +#define S_HSSPLLLOCKB_HSS1 3 +#define V_HSSPLLLOCKB_HSS1(x) ((x) << S_HSSPLLLOCKB_HSS1) +#define F_HSSPLLLOCKB_HSS1 V_HSSPLLLOCKB_HSS1(1U) + +#define S_HSSPLLLOCKA_HSS1 2 +#define V_HSSPLLLOCKA_HSS1(x) ((x) << S_HSSPLLLOCKA_HSS1) +#define F_HSSPLLLOCKA_HSS1 V_HSSPLLLOCKA_HSS1(1U) + +#define S_HSSPLLLOCKB_HSS0 1 +#define V_HSSPLLLOCKB_HSS0(x) ((x) << S_HSSPLLLOCKB_HSS0) +#define F_HSSPLLLOCKB_HSS0 V_HSSPLLLOCKB_HSS0(1U) + +#define S_HSSPLLLOCKA_HSS0 0 +#define V_HSSPLLLOCKA_HSS0(x) ((x) << S_HSSPLLLOCKA_HSS0) +#define F_HSSPLLLOCKA_HSS0 V_HSSPLLLOCKA_HSS0(1U) + +#define A_MAC_HSS_SIGDET_STATUS 0x380b4 + +#define S_HSS3_SIGDET 6 +#define M_HSS3_SIGDET 0x3U +#define V_HSS3_SIGDET(x) ((x) << S_HSS3_SIGDET) +#define G_HSS3_SIGDET(x) (((x) >> S_HSS3_SIGDET) & M_HSS3_SIGDET) + +#define S_HSS2_SIGDET 4 +#define M_HSS2_SIGDET 0x3U +#define V_HSS2_SIGDET(x) ((x) << S_HSS2_SIGDET) +#define G_HSS2_SIGDET(x) (((x) >> S_HSS2_SIGDET) & M_HSS2_SIGDET) + +#define S_HSS1_SIGDET 2 +#define M_HSS1_SIGDET 0x3U +#define V_HSS1_SIGDET(x) ((x) << S_HSS1_SIGDET) +#define G_HSS1_SIGDET(x) (((x) >> S_HSS1_SIGDET) & M_HSS1_SIGDET) + +#define S_HSS0_SIGDET 0 +#define M_HSS0_SIGDET 0x3U +#define V_HSS0_SIGDET(x) ((x) << S_HSS0_SIGDET) +#define G_HSS0_SIGDET(x) (((x) >> S_HSS0_SIGDET) & M_HSS0_SIGDET) + +#define A_MAC_FPGA_CFG_0 0x380b8 +#define A_MAC_PMD_STATUS 0x380bc + +#define S_SIGNAL_DETECT 0 +#define M_SIGNAL_DETECT 0xffU +#define V_SIGNAL_DETECT(x) ((x) << S_SIGNAL_DETECT) +#define G_SIGNAL_DETECT(x) (((x) >> S_SIGNAL_DETECT) & M_SIGNAL_DETECT) + +#define A_MAC_PMD_AN_CONFIG0 0x380c0 + +#define S_AN3_RATE_SELECT 25 +#define M_AN3_RATE_SELECT 0x1fU +#define V_AN3_RATE_SELECT(x) ((x) << S_AN3_RATE_SELECT) +#define G_AN3_RATE_SELECT(x) (((x) >> S_AN3_RATE_SELECT) & M_AN3_RATE_SELECT) + +#define S_AN3_STATUS 24 +#define V_AN3_STATUS(x) ((x) << S_AN3_STATUS) +#define F_AN3_STATUS V_AN3_STATUS(1U) + +#define S_AN2_RATE_SELECT 17 +#define M_AN2_RATE_SELECT 0x1fU +#define V_AN2_RATE_SELECT(x) ((x) << S_AN2_RATE_SELECT) +#define G_AN2_RATE_SELECT(x) (((x) >> S_AN2_RATE_SELECT) & M_AN2_RATE_SELECT) + +#define S_AN2_STATUS 16 +#define V_AN2_STATUS(x) ((x) << S_AN2_STATUS) +#define F_AN2_STATUS V_AN2_STATUS(1U) + +#define S_AN1_RATE_SELECT 9 +#define M_AN1_RATE_SELECT 0x1fU +#define V_AN1_RATE_SELECT(x) ((x) << S_AN1_RATE_SELECT) +#define G_AN1_RATE_SELECT(x) (((x) >> S_AN1_RATE_SELECT) & M_AN1_RATE_SELECT) + +#define S_AN1_STATUS 8 +#define V_AN1_STATUS(x) ((x) << S_AN1_STATUS) +#define F_AN1_STATUS V_AN1_STATUS(1U) + +#define S_AN0_RATE_SELECT 1 +#define M_AN0_RATE_SELECT 0x1fU +#define V_AN0_RATE_SELECT(x) ((x) << S_AN0_RATE_SELECT) +#define G_AN0_RATE_SELECT(x) (((x) >> S_AN0_RATE_SELECT) & M_AN0_RATE_SELECT) + +#define S_AN0_STATUS 0 +#define V_AN0_STATUS(x) ((x) << S_AN0_STATUS) +#define F_AN0_STATUS V_AN0_STATUS(1U) + +#define A_MAC_PMD_AN_CONFIG1 0x380c4 + +#define S_AN7_RATE_SELECT 25 +#define M_AN7_RATE_SELECT 0x1fU +#define V_AN7_RATE_SELECT(x) ((x) << S_AN7_RATE_SELECT) +#define G_AN7_RATE_SELECT(x) (((x) >> S_AN7_RATE_SELECT) & M_AN7_RATE_SELECT) + +#define S_AN7_STATUS 24 +#define V_AN7_STATUS(x) ((x) << S_AN7_STATUS) +#define F_AN7_STATUS V_AN7_STATUS(1U) + +#define S_AN6_RATE_SELECT 17 +#define M_AN6_RATE_SELECT 0x1fU +#define V_AN6_RATE_SELECT(x) ((x) << S_AN6_RATE_SELECT) +#define G_AN6_RATE_SELECT(x) (((x) >> S_AN6_RATE_SELECT) & M_AN6_RATE_SELECT) + +#define S_AN6_STATUS 16 +#define V_AN6_STATUS(x) ((x) << S_AN6_STATUS) +#define F_AN6_STATUS V_AN6_STATUS(1U) + +#define S_AN5_RATE_SELECT 9 +#define M_AN5_RATE_SELECT 0x1fU +#define V_AN5_RATE_SELECT(x) ((x) << S_AN5_RATE_SELECT) +#define G_AN5_RATE_SELECT(x) (((x) >> S_AN5_RATE_SELECT) & M_AN5_RATE_SELECT) + +#define S_AN5_STATUS 8 +#define V_AN5_STATUS(x) ((x) << S_AN5_STATUS) +#define F_AN5_STATUS V_AN5_STATUS(1U) + +#define S_AN4_RATE_SELECT 1 +#define M_AN4_RATE_SELECT 0x1fU +#define V_AN4_RATE_SELECT(x) ((x) << S_AN4_RATE_SELECT) +#define G_AN4_RATE_SELECT(x) (((x) >> S_AN4_RATE_SELECT) & M_AN4_RATE_SELECT) + +#define S_AN4_STATUS 0 +#define V_AN4_STATUS(x) ((x) << S_AN4_STATUS) +#define F_AN4_STATUS V_AN4_STATUS(1U) + +#define A_MAC_INT_EN_CMN 0x380c8 + +#define S_HSS3PLL1_LOCK_LOST_INT_EN 21 +#define V_HSS3PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_EN) +#define F_HSS3PLL1_LOCK_LOST_INT_EN V_HSS3PLL1_LOCK_LOST_INT_EN(1U) + +#define S_HSS3PLL1_LOCK_INT_EN 20 +#define V_HSS3PLL1_LOCK_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_INT_EN) +#define F_HSS3PLL1_LOCK_INT_EN V_HSS3PLL1_LOCK_INT_EN(1U) + +#define S_HSS3PLL0_LOCK_LOST_INT_EN 19 +#define V_HSS3PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_EN) +#define F_HSS3PLL0_LOCK_LOST_INT_EN V_HSS3PLL0_LOCK_LOST_INT_EN(1U) + +#define S_HSS3PLL0_LOCK_INT_EN 18 +#define V_HSS3PLL0_LOCK_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_INT_EN) +#define F_HSS3PLL0_LOCK_INT_EN V_HSS3PLL0_LOCK_INT_EN(1U) + +#define S_HSS2PLL1_LOCK_LOST_INT_EN 17 +#define V_HSS2PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_LOST_INT_EN) +#define F_HSS2PLL1_LOCK_LOST_INT_EN V_HSS2PLL1_LOCK_LOST_INT_EN(1U) + +#define S_HSS2PLL1_LOCK_INT_EN 16 +#define V_HSS2PLL1_LOCK_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_INT_EN) +#define F_HSS2PLL1_LOCK_INT_EN V_HSS2PLL1_LOCK_INT_EN(1U) + +#define S_HSS2PLL0_LOCK_LOST_INT_EN 15 +#define V_HSS2PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_EN) +#define F_HSS2PLL0_LOCK_LOST_INT_EN V_HSS2PLL0_LOCK_LOST_INT_EN(1U) + +#define S_HSS2PLL0_LOCK_INT_EN 14 +#define V_HSS2PLL0_LOCK_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_INT_EN) +#define F_HSS2PLL0_LOCK_INT_EN V_HSS2PLL0_LOCK_INT_EN(1U) + +#define S_HSS1PLL1_LOCK_LOST_INT_EN 13 +#define V_HSS1PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_EN) +#define F_HSS1PLL1_LOCK_LOST_INT_EN V_HSS1PLL1_LOCK_LOST_INT_EN(1U) + +#define S_HSS1PLL1_LOCK_INT_EN 12 +#define V_HSS1PLL1_LOCK_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_INT_EN) +#define F_HSS1PLL1_LOCK_INT_EN V_HSS1PLL1_LOCK_INT_EN(1U) + +#define S_HSS1PLL0_LOCK_LOST_INT_EN 11 +#define V_HSS1PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_EN) +#define F_HSS1PLL0_LOCK_LOST_INT_EN V_HSS1PLL0_LOCK_LOST_INT_EN(1U) + +#define S_HSS1PLL0_LOCK_INT_EN 10 +#define V_HSS1PLL0_LOCK_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_INT_EN) +#define F_HSS1PLL0_LOCK_INT_EN V_HSS1PLL0_LOCK_INT_EN(1U) + +#define S_HSS0PLL1_LOCK_LOST_INT_EN 9 +#define V_HSS0PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_EN) +#define F_HSS0PLL1_LOCK_LOST_INT_EN V_HSS0PLL1_LOCK_LOST_INT_EN(1U) + +#define S_HSS0PLL1_LOCK_INT_EN 8 +#define V_HSS0PLL1_LOCK_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_INT_EN) +#define F_HSS0PLL1_LOCK_INT_EN V_HSS0PLL1_LOCK_INT_EN(1U) + +#define S_HSS0PLL0_LOCK_LOST_INT_EN 7 +#define V_HSS0PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_EN) +#define F_HSS0PLL0_LOCK_LOST_INT_EN V_HSS0PLL0_LOCK_LOST_INT_EN(1U) + +#define S_HSS0PLL0_LOCK_INT_EN 6 +#define V_HSS0PLL0_LOCK_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_INT_EN) +#define F_HSS0PLL0_LOCK_INT_EN V_HSS0PLL0_LOCK_INT_EN(1U) + +#define S_FLOCK_ASSERTED 5 +#define V_FLOCK_ASSERTED(x) ((x) << S_FLOCK_ASSERTED) +#define F_FLOCK_ASSERTED V_FLOCK_ASSERTED(1U) + +#define S_FLOCK_LOST 4 +#define V_FLOCK_LOST(x) ((x) << S_FLOCK_LOST) +#define F_FLOCK_LOST V_FLOCK_LOST(1U) + +#define S_PHASE_LOCK_ASSERTED 3 +#define V_PHASE_LOCK_ASSERTED(x) ((x) << S_PHASE_LOCK_ASSERTED) +#define F_PHASE_LOCK_ASSERTED V_PHASE_LOCK_ASSERTED(1U) + +#define S_PHASE_LOCK_LOST 2 +#define V_PHASE_LOCK_LOST(x) ((x) << S_PHASE_LOCK_LOST) +#define F_PHASE_LOCK_LOST V_PHASE_LOCK_LOST(1U) + +#define S_LOCK_ASSERTED 1 +#define V_LOCK_ASSERTED(x) ((x) << S_LOCK_ASSERTED) +#define F_LOCK_ASSERTED V_LOCK_ASSERTED(1U) + +#define S_LOCK_LOST 0 +#define V_LOCK_LOST(x) ((x) << S_LOCK_LOST) +#define F_LOCK_LOST V_LOCK_LOST(1U) + +#define A_MAC_INT_CAUSE_CMN 0x380cc + +#define S_HSS3PLL1_LOCK_LOST_INT_CAUSE 21 +#define V_HSS3PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_CAUSE) +#define F_HSS3PLL1_LOCK_LOST_INT_CAUSE V_HSS3PLL1_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS3PLL1_LOCK_INT_CAUSE 20 +#define V_HSS3PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_INT_CAUSE) +#define F_HSS3PLL1_LOCK_INT_CAUSE V_HSS3PLL1_LOCK_INT_CAUSE(1U) + +#define S_HSS3PLL0_LOCK_LOST_INT_CAUSE 19 +#define V_HSS3PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_CAUSE) +#define F_HSS3PLL0_LOCK_LOST_INT_CAUSE V_HSS3PLL0_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS3PLL0_LOCK_INT_CAUSE 18 +#define V_HSS3PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_INT_CAUSE) +#define F_HSS3PLL0_LOCK_INT_CAUSE V_HSS3PLL0_LOCK_INT_CAUSE(1U) + +#define S_HSS2PLL1_LOCK_LOST_CAUSE 17 +#define V_HSS2PLL1_LOCK_LOST_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_LOST_CAUSE) +#define F_HSS2PLL1_LOCK_LOST_CAUSE V_HSS2PLL1_LOCK_LOST_CAUSE(1U) + +#define S_HSS2PLL1_LOCK_INT_CAUSE 16 +#define V_HSS2PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_INT_CAUSE) +#define F_HSS2PLL1_LOCK_INT_CAUSE V_HSS2PLL1_LOCK_INT_CAUSE(1U) + +#define S_HSS2PLL0_LOCK_LOST_INT_CAUSE 15 +#define V_HSS2PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_CAUSE) +#define F_HSS2PLL0_LOCK_LOST_INT_CAUSE V_HSS2PLL0_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS2PLL0_LOCK_INT_CAUSE 14 +#define V_HSS2PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_INT_CAUSE) +#define F_HSS2PLL0_LOCK_INT_CAUSE V_HSS2PLL0_LOCK_INT_CAUSE(1U) + +#define S_HSS1PLL1_LOCK_LOST_INT_CAUSE 13 +#define V_HSS1PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_CAUSE) +#define F_HSS1PLL1_LOCK_LOST_INT_CAUSE V_HSS1PLL1_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS1PLL1_LOCK_INT_CAUSE 12 +#define V_HSS1PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_INT_CAUSE) +#define F_HSS1PLL1_LOCK_INT_CAUSE V_HSS1PLL1_LOCK_INT_CAUSE(1U) + +#define S_HSS1PLL0_LOCK_LOST_INT_CAUSE 11 +#define V_HSS1PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_CAUSE) +#define F_HSS1PLL0_LOCK_LOST_INT_CAUSE V_HSS1PLL0_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS1PLL0_LOCK_INT_CAUSE 10 +#define V_HSS1PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_INT_CAUSE) +#define F_HSS1PLL0_LOCK_INT_CAUSE V_HSS1PLL0_LOCK_INT_CAUSE(1U) + +#define S_HSS0PLL1_LOCK_LOST_INT_CAUSE 9 +#define V_HSS0PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_CAUSE) +#define F_HSS0PLL1_LOCK_LOST_INT_CAUSE V_HSS0PLL1_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS0PLL1_LOCK_INT_CAUSE 8 +#define V_HSS0PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_INT_CAUSE) +#define F_HSS0PLL1_LOCK_INT_CAUSE V_HSS0PLL1_LOCK_INT_CAUSE(1U) + +#define S_HSS0PLL0_LOCK_LOST_INT_CAUSE 7 +#define V_HSS0PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_CAUSE) +#define F_HSS0PLL0_LOCK_LOST_INT_CAUSE V_HSS0PLL0_LOCK_LOST_INT_CAUSE(1U) + +#define S_HSS0PLL0_LOCK_INT_CAUSE 6 +#define V_HSS0PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_INT_CAUSE) +#define F_HSS0PLL0_LOCK_INT_CAUSE V_HSS0PLL0_LOCK_INT_CAUSE(1U) + +#define A_MAC_PERR_INT_EN_MTIP 0x380d0 + +#define S_PERR_MAC0_TX 19 +#define V_PERR_MAC0_TX(x) ((x) << S_PERR_MAC0_TX) +#define F_PERR_MAC0_TX V_PERR_MAC0_TX(1U) + +#define S_PERR_MAC1_TX 18 +#define V_PERR_MAC1_TX(x) ((x) << S_PERR_MAC1_TX) +#define F_PERR_MAC1_TX V_PERR_MAC1_TX(1U) + +#define S_PERR_MAC2_TX 17 +#define V_PERR_MAC2_TX(x) ((x) << S_PERR_MAC2_TX) +#define F_PERR_MAC2_TX V_PERR_MAC2_TX(1U) + +#define S_PERR_MAC3_TX 16 +#define V_PERR_MAC3_TX(x) ((x) << S_PERR_MAC3_TX) +#define F_PERR_MAC3_TX V_PERR_MAC3_TX(1U) + +#define S_PERR_MAC4_TX 15 +#define V_PERR_MAC4_TX(x) ((x) << S_PERR_MAC4_TX) +#define F_PERR_MAC4_TX V_PERR_MAC4_TX(1U) + +#define S_PERR_MAC5_TX 14 +#define V_PERR_MAC5_TX(x) ((x) << S_PERR_MAC5_TX) +#define F_PERR_MAC5_TX V_PERR_MAC5_TX(1U) + +#define S_PERR_MAC0_RX 13 +#define V_PERR_MAC0_RX(x) ((x) << S_PERR_MAC0_RX) +#define F_PERR_MAC0_RX V_PERR_MAC0_RX(1U) + +#define S_PERR_MAC1_RX 12 +#define V_PERR_MAC1_RX(x) ((x) << S_PERR_MAC1_RX) +#define F_PERR_MAC1_RX V_PERR_MAC1_RX(1U) + +#define S_PERR_MAC2_RX 11 +#define V_PERR_MAC2_RX(x) ((x) << S_PERR_MAC2_RX) +#define F_PERR_MAC2_RX V_PERR_MAC2_RX(1U) + +#define S_PERR_MAC3_RX 10 +#define V_PERR_MAC3_RX(x) ((x) << S_PERR_MAC3_RX) +#define F_PERR_MAC3_RX V_PERR_MAC3_RX(1U) + +#define S_PERR_MAC4_RX 9 +#define V_PERR_MAC4_RX(x) ((x) << S_PERR_MAC4_RX) +#define F_PERR_MAC4_RX V_PERR_MAC4_RX(1U) + +#define S_PERR_MAC5_RX 8 +#define V_PERR_MAC5_RX(x) ((x) << S_PERR_MAC5_RX) +#define F_PERR_MAC5_RX V_PERR_MAC5_RX(1U) + +#define S_PERR_MAC_STAT2_RX 7 +#define V_PERR_MAC_STAT2_RX(x) ((x) << S_PERR_MAC_STAT2_RX) +#define F_PERR_MAC_STAT2_RX V_PERR_MAC_STAT2_RX(1U) + +#define S_PERR_MAC_STAT3_RX 6 +#define V_PERR_MAC_STAT3_RX(x) ((x) << S_PERR_MAC_STAT3_RX) +#define F_PERR_MAC_STAT3_RX V_PERR_MAC_STAT3_RX(1U) + +#define S_PERR_MAC_STAT4_RX 5 +#define V_PERR_MAC_STAT4_RX(x) ((x) << S_PERR_MAC_STAT4_RX) +#define F_PERR_MAC_STAT4_RX V_PERR_MAC_STAT4_RX(1U) + +#define S_PERR_MAC_STAT5_RX 4 +#define V_PERR_MAC_STAT5_RX(x) ((x) << S_PERR_MAC_STAT5_RX) +#define F_PERR_MAC_STAT5_RX V_PERR_MAC_STAT5_RX(1U) + +#define S_PERR_MAC_STAT2_TX 3 +#define V_PERR_MAC_STAT2_TX(x) ((x) << S_PERR_MAC_STAT2_TX) +#define F_PERR_MAC_STAT2_TX V_PERR_MAC_STAT2_TX(1U) + +#define S_PERR_MAC_STAT3_TX 2 +#define V_PERR_MAC_STAT3_TX(x) ((x) << S_PERR_MAC_STAT3_TX) +#define F_PERR_MAC_STAT3_TX V_PERR_MAC_STAT3_TX(1U) + +#define S_PERR_MAC_STAT4_TX 1 +#define V_PERR_MAC_STAT4_TX(x) ((x) << S_PERR_MAC_STAT4_TX) +#define F_PERR_MAC_STAT4_TX V_PERR_MAC_STAT4_TX(1U) + +#define S_PERR_MAC_STAT5_TX 0 +#define V_PERR_MAC_STAT5_TX(x) ((x) << S_PERR_MAC_STAT5_TX) +#define F_PERR_MAC_STAT5_TX V_PERR_MAC_STAT5_TX(1U) + +#define A_MAC_PERR_INT_CAUSE_MTIP 0x380d4 + +#define S_PERR_MAC_STAT_RX 7 +#define V_PERR_MAC_STAT_RX(x) ((x) << S_PERR_MAC_STAT_RX) +#define F_PERR_MAC_STAT_RX V_PERR_MAC_STAT_RX(1U) + +#define S_PERR_MAC_STAT_TX 3 +#define V_PERR_MAC_STAT_TX(x) ((x) << S_PERR_MAC_STAT_TX) +#define F_PERR_MAC_STAT_TX V_PERR_MAC_STAT_TX(1U) + +#define S_PERR_MAC_STAT_CAP 2 +#define V_PERR_MAC_STAT_CAP(x) ((x) << S_PERR_MAC_STAT_CAP) +#define F_PERR_MAC_STAT_CAP V_PERR_MAC_STAT_CAP(1U) + +#define A_MAC_PERR_ENABLE_MTIP 0x380d8 +#define A_MAC_PCS_1G_CONFIG_0 0x380dc + +#define S_SEQ_ENA_3 19 +#define V_SEQ_ENA_3(x) ((x) << S_SEQ_ENA_3) +#define F_SEQ_ENA_3 V_SEQ_ENA_3(1U) + +#define S_SEQ_ENA_2 18 +#define V_SEQ_ENA_2(x) ((x) << S_SEQ_ENA_2) +#define F_SEQ_ENA_2 V_SEQ_ENA_2(1U) + +#define S_SEQ_ENA_1 17 +#define V_SEQ_ENA_1(x) ((x) << S_SEQ_ENA_1) +#define F_SEQ_ENA_1 V_SEQ_ENA_1(1U) + +#define S_SEQ_ENA_0 16 +#define V_SEQ_ENA_0(x) ((x) << S_SEQ_ENA_0) +#define F_SEQ_ENA_0 V_SEQ_ENA_0(1U) + +#define S_TX_LANE_THRESH_3 12 +#define M_TX_LANE_THRESH_3 0xfU +#define V_TX_LANE_THRESH_3(x) ((x) << S_TX_LANE_THRESH_3) +#define G_TX_LANE_THRESH_3(x) (((x) >> S_TX_LANE_THRESH_3) & M_TX_LANE_THRESH_3) + +#define S_TX_LANE_THRESH_2 8 +#define M_TX_LANE_THRESH_2 0xfU +#define V_TX_LANE_THRESH_2(x) ((x) << S_TX_LANE_THRESH_2) +#define G_TX_LANE_THRESH_2(x) (((x) >> S_TX_LANE_THRESH_2) & M_TX_LANE_THRESH_2) + +#define S_TX_LANE_THRESH_1 4 +#define M_TX_LANE_THRESH_1 0xfU +#define V_TX_LANE_THRESH_1(x) ((x) << S_TX_LANE_THRESH_1) +#define G_TX_LANE_THRESH_1(x) (((x) >> S_TX_LANE_THRESH_1) & M_TX_LANE_THRESH_1) + +#define S_TX_LANE_THRESH_0 0 +#define M_TX_LANE_THRESH_0 0xfU +#define V_TX_LANE_THRESH_0(x) ((x) << S_TX_LANE_THRESH_0) +#define G_TX_LANE_THRESH_0(x) (((x) >> S_TX_LANE_THRESH_0) & M_TX_LANE_THRESH_0) + +#define A_MAC_PCS_1G_CONFIG_1 0x380e0 + +#define S_TX_LANE_CKMULT_3 9 +#define M_TX_LANE_CKMULT_3 0x7U +#define V_TX_LANE_CKMULT_3(x) ((x) << S_TX_LANE_CKMULT_3) +#define G_TX_LANE_CKMULT_3(x) (((x) >> S_TX_LANE_CKMULT_3) & M_TX_LANE_CKMULT_3) + +#define S_TX_LANE_CKMULT_2 6 +#define M_TX_LANE_CKMULT_2 0x7U +#define V_TX_LANE_CKMULT_2(x) ((x) << S_TX_LANE_CKMULT_2) +#define G_TX_LANE_CKMULT_2(x) (((x) >> S_TX_LANE_CKMULT_2) & M_TX_LANE_CKMULT_2) + +#define S_TX_LANE_CKMULT_1 3 +#define M_TX_LANE_CKMULT_1 0x7U +#define V_TX_LANE_CKMULT_1(x) ((x) << S_TX_LANE_CKMULT_1) +#define G_TX_LANE_CKMULT_1(x) (((x) >> S_TX_LANE_CKMULT_1) & M_TX_LANE_CKMULT_1) + +#define S_TX_LANE_CKMULT_0 0 +#define M_TX_LANE_CKMULT_0 0x7U +#define V_TX_LANE_CKMULT_0(x) ((x) << S_TX_LANE_CKMULT_0) +#define G_TX_LANE_CKMULT_0(x) (((x) >> S_TX_LANE_CKMULT_0) & M_TX_LANE_CKMULT_0) + +#define A_MAC_PTP_TIMER_RD0_LO 0x380e4 +#define A_MAC_PTP_TIMER_RD0_HI 0x380e8 +#define A_MAC_PTP_TIMER_RD1_LO 0x380ec +#define A_MAC_PTP_TIMER_RD1_HI 0x380f0 +#define A_MAC_PTP_TIMER_WR_LO 0x380f4 +#define A_MAC_PTP_TIMER_WR_HI 0x380f8 +#define A_MAC_PTP_TIMER_OFFSET_0 0x380fc +#define A_MAC_PTP_TIMER_OFFSET_1 0x38100 +#define A_MAC_PTP_TIMER_OFFSET_2 0x38104 +#define A_MAC_PTP_SUM_LO 0x38108 +#define A_MAC_PTP_SUM_HI 0x3810c +#define A_MAC_PTP_TIMER_INCR0 0x38110 +#define A_MAC_PTP_TIMER_INCR1 0x38114 +#define A_MAC_PTP_DRIFT_ADJUST_COUNT 0x38118 +#define A_MAC_PTP_OFFSET_ADJUST_FINE 0x3811c +#define A_MAC_PTP_OFFSET_ADJUST_TOTAL 0x38120 +#define A_MAC_PTP_CFG 0x38124 +#define A_MAC_PTP_PPS 0x38128 +#define A_MAC_PTP_SINGLE_ALARM 0x3812c +#define A_MAC_PTP_PERIODIC_ALARM 0x38130 +#define A_MAC_PTP_STATUS 0x38134 +#define A_MAC_STS_GPIO_SEL 0x38140 + +#define S_STSOUTSEL 1 +#define V_STSOUTSEL(x) ((x) << S_STSOUTSEL) +#define F_STSOUTSEL V_STSOUTSEL(1U) + +#define S_STSINSEL 0 +#define V_STSINSEL(x) ((x) << S_STSINSEL) +#define F_STSINSEL V_STSINSEL(1U) + +#define A_MAC_CERR_INT_EN_MTIP 0x38150 + +#define S_CERR_MAC0_TX 11 +#define V_CERR_MAC0_TX(x) ((x) << S_CERR_MAC0_TX) +#define F_CERR_MAC0_TX V_CERR_MAC0_TX(1U) + +#define S_CERR_MAC1_TX 10 +#define V_CERR_MAC1_TX(x) ((x) << S_CERR_MAC1_TX) +#define F_CERR_MAC1_TX V_CERR_MAC1_TX(1U) + +#define S_CERR_MAC2_TX 9 +#define V_CERR_MAC2_TX(x) ((x) << S_CERR_MAC2_TX) +#define F_CERR_MAC2_TX V_CERR_MAC2_TX(1U) + +#define S_CERR_MAC3_TX 8 +#define V_CERR_MAC3_TX(x) ((x) << S_CERR_MAC3_TX) +#define F_CERR_MAC3_TX V_CERR_MAC3_TX(1U) + +#define S_CERR_MAC4_TX 7 +#define V_CERR_MAC4_TX(x) ((x) << S_CERR_MAC4_TX) +#define F_CERR_MAC4_TX V_CERR_MAC4_TX(1U) + +#define S_CERR_MAC5_TX 6 +#define V_CERR_MAC5_TX(x) ((x) << S_CERR_MAC5_TX) +#define F_CERR_MAC5_TX V_CERR_MAC5_TX(1U) + +#define S_CERR_MAC0_RX 5 +#define V_CERR_MAC0_RX(x) ((x) << S_CERR_MAC0_RX) +#define F_CERR_MAC0_RX V_CERR_MAC0_RX(1U) + +#define S_CERR_MAC1_RX 4 +#define V_CERR_MAC1_RX(x) ((x) << S_CERR_MAC1_RX) +#define F_CERR_MAC1_RX V_CERR_MAC1_RX(1U) + +#define S_CERR_MAC2_RX 3 +#define V_CERR_MAC2_RX(x) ((x) << S_CERR_MAC2_RX) +#define F_CERR_MAC2_RX V_CERR_MAC2_RX(1U) + +#define S_CERR_MAC3_RX 2 +#define V_CERR_MAC3_RX(x) ((x) << S_CERR_MAC3_RX) +#define F_CERR_MAC3_RX V_CERR_MAC3_RX(1U) + +#define S_CERR_MAC4_RX 1 +#define V_CERR_MAC4_RX(x) ((x) << S_CERR_MAC4_RX) +#define F_CERR_MAC4_RX V_CERR_MAC4_RX(1U) + +#define S_CERR_MAC5_RX 0 +#define V_CERR_MAC5_RX(x) ((x) << S_CERR_MAC5_RX) +#define F_CERR_MAC5_RX V_CERR_MAC5_RX(1U) + +#define A_MAC_CERR_INT_CAUSE_MTIP 0x38154 +#define A_MAC_1G_PCS0_STATUS 0x38160 + +#define S_1G_PCS0_LOOPBACK 12 +#define V_1G_PCS0_LOOPBACK(x) ((x) << S_1G_PCS0_LOOPBACK) +#define F_1G_PCS0_LOOPBACK V_1G_PCS0_LOOPBACK(1U) + +#define S_1G_PCS0_LINK_STATUS 11 +#define V_1G_PCS0_LINK_STATUS(x) ((x) << S_1G_PCS0_LINK_STATUS) +#define F_1G_PCS0_LINK_STATUS V_1G_PCS0_LINK_STATUS(1U) + +#define S_1G_PCS0_RX_SYNC 10 +#define V_1G_PCS0_RX_SYNC(x) ((x) << S_1G_PCS0_RX_SYNC) +#define F_1G_PCS0_RX_SYNC V_1G_PCS0_RX_SYNC(1U) + +#define S_1G_PCS0_AN_DONE 9 +#define V_1G_PCS0_AN_DONE(x) ((x) << S_1G_PCS0_AN_DONE) +#define F_1G_PCS0_AN_DONE V_1G_PCS0_AN_DONE(1U) + +#define S_1G_PCS0_PGRCVD 8 +#define V_1G_PCS0_PGRCVD(x) ((x) << S_1G_PCS0_PGRCVD) +#define F_1G_PCS0_PGRCVD V_1G_PCS0_PGRCVD(1U) + +#define S_1G_PCS0_SPEED_SEL 6 +#define M_1G_PCS0_SPEED_SEL 0x3U +#define V_1G_PCS0_SPEED_SEL(x) ((x) << S_1G_PCS0_SPEED_SEL) +#define G_1G_PCS0_SPEED_SEL(x) (((x) >> S_1G_PCS0_SPEED_SEL) & M_1G_PCS0_SPEED_SEL) + +#define S_1G_PCS0_HALF_DUPLEX 5 +#define V_1G_PCS0_HALF_DUPLEX(x) ((x) << S_1G_PCS0_HALF_DUPLEX) +#define F_1G_PCS0_HALF_DUPLEX V_1G_PCS0_HALF_DUPLEX(1U) + +#define S_1G_PCS0_TX_MODE_QUIET 4 +#define V_1G_PCS0_TX_MODE_QUIET(x) ((x) << S_1G_PCS0_TX_MODE_QUIET) +#define F_1G_PCS0_TX_MODE_QUIET V_1G_PCS0_TX_MODE_QUIET(1U) + +#define S_1G_PCS0_TX_LPI_ACTIVE 3 +#define V_1G_PCS0_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_TX_LPI_ACTIVE) +#define F_1G_PCS0_TX_LPI_ACTIVE V_1G_PCS0_TX_LPI_ACTIVE(1U) + +#define S_1G_PCS0_RX_MODE_QUIET 2 +#define V_1G_PCS0_RX_MODE_QUIET(x) ((x) << S_1G_PCS0_RX_MODE_QUIET) +#define F_1G_PCS0_RX_MODE_QUIET V_1G_PCS0_RX_MODE_QUIET(1U) + +#define S_1G_PCS0_RX_LPI_ACTIVE 1 +#define V_1G_PCS0_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_RX_LPI_ACTIVE) +#define F_1G_PCS0_RX_LPI_ACTIVE V_1G_PCS0_RX_LPI_ACTIVE(1U) + +#define S_1G_PCS0_RX_WAKE_ERR 0 +#define V_1G_PCS0_RX_WAKE_ERR(x) ((x) << S_1G_PCS0_RX_WAKE_ERR) +#define F_1G_PCS0_RX_WAKE_ERR V_1G_PCS0_RX_WAKE_ERR(1U) + +#define A_MAC_1G_PCS1_STATUS 0x38164 + +#define S_1G_PCS1_LOOPBACK 12 +#define V_1G_PCS1_LOOPBACK(x) ((x) << S_1G_PCS1_LOOPBACK) +#define F_1G_PCS1_LOOPBACK V_1G_PCS1_LOOPBACK(1U) + +#define S_1G_PCS1_LINK_STATUS 11 +#define V_1G_PCS1_LINK_STATUS(x) ((x) << S_1G_PCS1_LINK_STATUS) +#define F_1G_PCS1_LINK_STATUS V_1G_PCS1_LINK_STATUS(1U) + +#define S_1G_PCS1_RX_SYNC 10 +#define V_1G_PCS1_RX_SYNC(x) ((x) << S_1G_PCS1_RX_SYNC) +#define F_1G_PCS1_RX_SYNC V_1G_PCS1_RX_SYNC(1U) + +#define S_1G_PCS1_AN_DONE 9 +#define V_1G_PCS1_AN_DONE(x) ((x) << S_1G_PCS1_AN_DONE) +#define F_1G_PCS1_AN_DONE V_1G_PCS1_AN_DONE(1U) + +#define S_1G_PCS1_PGRCVD 8 +#define V_1G_PCS1_PGRCVD(x) ((x) << S_1G_PCS1_PGRCVD) +#define F_1G_PCS1_PGRCVD V_1G_PCS1_PGRCVD(1U) + +#define S_1G_PCS1_SPEED_SEL 6 +#define M_1G_PCS1_SPEED_SEL 0x3U +#define V_1G_PCS1_SPEED_SEL(x) ((x) << S_1G_PCS1_SPEED_SEL) +#define G_1G_PCS1_SPEED_SEL(x) (((x) >> S_1G_PCS1_SPEED_SEL) & M_1G_PCS1_SPEED_SEL) + +#define S_1G_PCS1_HALF_DUPLEX 5 +#define V_1G_PCS1_HALF_DUPLEX(x) ((x) << S_1G_PCS1_HALF_DUPLEX) +#define F_1G_PCS1_HALF_DUPLEX V_1G_PCS1_HALF_DUPLEX(1U) + +#define S_1G_PCS1_TX_MODE_QUIET 4 +#define V_1G_PCS1_TX_MODE_QUIET(x) ((x) << S_1G_PCS1_TX_MODE_QUIET) +#define F_1G_PCS1_TX_MODE_QUIET V_1G_PCS1_TX_MODE_QUIET(1U) + +#define S_1G_PCS1_TX_LPI_ACTIVE 3 +#define V_1G_PCS1_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_TX_LPI_ACTIVE) +#define F_1G_PCS1_TX_LPI_ACTIVE V_1G_PCS1_TX_LPI_ACTIVE(1U) + +#define S_1G_PCS1_RX_MODE_QUIET 2 +#define V_1G_PCS1_RX_MODE_QUIET(x) ((x) << S_1G_PCS1_RX_MODE_QUIET) +#define F_1G_PCS1_RX_MODE_QUIET V_1G_PCS1_RX_MODE_QUIET(1U) + +#define S_1G_PCS1_RX_LPI_ACTIVE 1 +#define V_1G_PCS1_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_RX_LPI_ACTIVE) +#define F_1G_PCS1_RX_LPI_ACTIVE V_1G_PCS1_RX_LPI_ACTIVE(1U) + +#define S_1G_PCS1_RX_WAKE_ERR 0 +#define V_1G_PCS1_RX_WAKE_ERR(x) ((x) << S_1G_PCS1_RX_WAKE_ERR) +#define F_1G_PCS1_RX_WAKE_ERR V_1G_PCS1_RX_WAKE_ERR(1U) + +#define A_MAC_1G_PCS2_STATUS 0x38168 + +#define S_1G_PCS2_LOOPBACK 12 +#define V_1G_PCS2_LOOPBACK(x) ((x) << S_1G_PCS2_LOOPBACK) +#define F_1G_PCS2_LOOPBACK V_1G_PCS2_LOOPBACK(1U) + +#define S_1G_PCS2_LINK_STATUS 11 +#define V_1G_PCS2_LINK_STATUS(x) ((x) << S_1G_PCS2_LINK_STATUS) +#define F_1G_PCS2_LINK_STATUS V_1G_PCS2_LINK_STATUS(1U) + +#define S_1G_PCS2_RX_SYNC 10 +#define V_1G_PCS2_RX_SYNC(x) ((x) << S_1G_PCS2_RX_SYNC) +#define F_1G_PCS2_RX_SYNC V_1G_PCS2_RX_SYNC(1U) + +#define S_1G_PCS2_AN_DONE 9 +#define V_1G_PCS2_AN_DONE(x) ((x) << S_1G_PCS2_AN_DONE) +#define F_1G_PCS2_AN_DONE V_1G_PCS2_AN_DONE(1U) + +#define S_1G_PCS2_PGRCVD 8 +#define V_1G_PCS2_PGRCVD(x) ((x) << S_1G_PCS2_PGRCVD) +#define F_1G_PCS2_PGRCVD V_1G_PCS2_PGRCVD(1U) + +#define S_1G_PCS2_SPEED_SEL 6 +#define M_1G_PCS2_SPEED_SEL 0x3U +#define V_1G_PCS2_SPEED_SEL(x) ((x) << S_1G_PCS2_SPEED_SEL) +#define G_1G_PCS2_SPEED_SEL(x) (((x) >> S_1G_PCS2_SPEED_SEL) & M_1G_PCS2_SPEED_SEL) + +#define S_1G_PCS2_HALF_DUPLEX 5 +#define V_1G_PCS2_HALF_DUPLEX(x) ((x) << S_1G_PCS2_HALF_DUPLEX) +#define F_1G_PCS2_HALF_DUPLEX V_1G_PCS2_HALF_DUPLEX(1U) + +#define S_1G_PCS2_TX_MODE_QUIET 4 +#define V_1G_PCS2_TX_MODE_QUIET(x) ((x) << S_1G_PCS2_TX_MODE_QUIET) +#define F_1G_PCS2_TX_MODE_QUIET V_1G_PCS2_TX_MODE_QUIET(1U) + +#define S_1G_PCS2_TX_LPI_ACTIVE 3 +#define V_1G_PCS2_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_TX_LPI_ACTIVE) +#define F_1G_PCS2_TX_LPI_ACTIVE V_1G_PCS2_TX_LPI_ACTIVE(1U) + +#define S_1G_PCS2_RX_MODE_QUIET 2 +#define V_1G_PCS2_RX_MODE_QUIET(x) ((x) << S_1G_PCS2_RX_MODE_QUIET) +#define F_1G_PCS2_RX_MODE_QUIET V_1G_PCS2_RX_MODE_QUIET(1U) + +#define S_1G_PCS2_RX_LPI_ACTIVE 1 +#define V_1G_PCS2_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_RX_LPI_ACTIVE) +#define F_1G_PCS2_RX_LPI_ACTIVE V_1G_PCS2_RX_LPI_ACTIVE(1U) + +#define S_1G_PCS2_RX_WAKE_ERR 0 +#define V_1G_PCS2_RX_WAKE_ERR(x) ((x) << S_1G_PCS2_RX_WAKE_ERR) +#define F_1G_PCS2_RX_WAKE_ERR V_1G_PCS2_RX_WAKE_ERR(1U) + +#define A_MAC_1G_PCS3_STATUS 0x3816c + +#define S_1G_PCS3_LOOPBACK 12 +#define V_1G_PCS3_LOOPBACK(x) ((x) << S_1G_PCS3_LOOPBACK) +#define F_1G_PCS3_LOOPBACK V_1G_PCS3_LOOPBACK(1U) + +#define S_1G_PCS3_LINK_STATUS 11 +#define V_1G_PCS3_LINK_STATUS(x) ((x) << S_1G_PCS3_LINK_STATUS) +#define F_1G_PCS3_LINK_STATUS V_1G_PCS3_LINK_STATUS(1U) + +#define S_1G_PCS3_RX_SYNC 10 +#define V_1G_PCS3_RX_SYNC(x) ((x) << S_1G_PCS3_RX_SYNC) +#define F_1G_PCS3_RX_SYNC V_1G_PCS3_RX_SYNC(1U) + +#define S_1G_PCS3_AN_DONE 9 +#define V_1G_PCS3_AN_DONE(x) ((x) << S_1G_PCS3_AN_DONE) +#define F_1G_PCS3_AN_DONE V_1G_PCS3_AN_DONE(1U) + +#define S_1G_PCS3_PGRCVD 8 +#define V_1G_PCS3_PGRCVD(x) ((x) << S_1G_PCS3_PGRCVD) +#define F_1G_PCS3_PGRCVD V_1G_PCS3_PGRCVD(1U) + +#define S_1G_PCS3_SPEED_SEL 6 +#define M_1G_PCS3_SPEED_SEL 0x3U +#define V_1G_PCS3_SPEED_SEL(x) ((x) << S_1G_PCS3_SPEED_SEL) +#define G_1G_PCS3_SPEED_SEL(x) (((x) >> S_1G_PCS3_SPEED_SEL) & M_1G_PCS3_SPEED_SEL) + +#define S_1G_PCS3_HALF_DUPLEX 5 +#define V_1G_PCS3_HALF_DUPLEX(x) ((x) << S_1G_PCS3_HALF_DUPLEX) +#define F_1G_PCS3_HALF_DUPLEX V_1G_PCS3_HALF_DUPLEX(1U) + +#define S_1G_PCS3_TX_MODE_QUIET 4 +#define V_1G_PCS3_TX_MODE_QUIET(x) ((x) << S_1G_PCS3_TX_MODE_QUIET) +#define F_1G_PCS3_TX_MODE_QUIET V_1G_PCS3_TX_MODE_QUIET(1U) + +#define S_1G_PCS3_TX_LPI_ACTIVE 3 +#define V_1G_PCS3_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_TX_LPI_ACTIVE) +#define F_1G_PCS3_TX_LPI_ACTIVE V_1G_PCS3_TX_LPI_ACTIVE(1U) + +#define S_1G_PCS3_RX_MODE_QUIET 2 +#define V_1G_PCS3_RX_MODE_QUIET(x) ((x) << S_1G_PCS3_RX_MODE_QUIET) +#define F_1G_PCS3_RX_MODE_QUIET V_1G_PCS3_RX_MODE_QUIET(1U) + +#define S_1G_PCS3_RX_LPI_ACTIVE 1 +#define V_1G_PCS3_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_RX_LPI_ACTIVE) +#define F_1G_PCS3_RX_LPI_ACTIVE V_1G_PCS3_RX_LPI_ACTIVE(1U) + +#define S_1G_PCS3_RX_WAKE_ERR 0 +#define V_1G_PCS3_RX_WAKE_ERR(x) ((x) << S_1G_PCS3_RX_WAKE_ERR) +#define F_1G_PCS3_RX_WAKE_ERR V_1G_PCS3_RX_WAKE_ERR(1U) + +#define A_MAC_PCS_LPI_STATUS_0 0x38170 + +#define S_TX_LPI_STATE 0 +#define M_TX_LPI_STATE 0xffffffU +#define V_TX_LPI_STATE(x) ((x) << S_TX_LPI_STATE) +#define G_TX_LPI_STATE(x) (((x) >> S_TX_LPI_STATE) & M_TX_LPI_STATE) + +#define A_MAC_PCS_LPI_STATUS_1 0x38174 + +#define S_TX_LPI_MODE 0 +#define M_TX_LPI_MODE 0xffffU +#define V_TX_LPI_MODE(x) ((x) << S_TX_LPI_MODE) +#define G_TX_LPI_MODE(x) (((x) >> S_TX_LPI_MODE) & M_TX_LPI_MODE) + +#define A_MAC_PCS_LPI_STATUS_2 0x38178 + +#define S_RX_LPI_MODE 24 +#define M_RX_LPI_MODE 0xffU +#define V_RX_LPI_MODE(x) ((x) << S_RX_LPI_MODE) +#define G_RX_LPI_MODE(x) (((x) >> S_RX_LPI_MODE) & M_RX_LPI_MODE) + +#define S_RX_LPI_STATE 0 +#define M_RX_LPI_STATE 0xffffffU +#define V_RX_LPI_STATE(x) ((x) << S_RX_LPI_STATE) +#define G_RX_LPI_STATE(x) (((x) >> S_RX_LPI_STATE) & M_RX_LPI_STATE) + +#define A_MAC_PCS_LPI_STATUS_3 0x3817c + +#define S_T7_RX_LPI_ACTIVE 0 +#define M_T7_RX_LPI_ACTIVE 0xffU +#define V_T7_RX_LPI_ACTIVE(x) ((x) << S_T7_RX_LPI_ACTIVE) +#define G_T7_RX_LPI_ACTIVE(x) (((x) >> S_T7_RX_LPI_ACTIVE) & M_T7_RX_LPI_ACTIVE) + +#define A_MAC_TX0_CLK_DIV 0x38180 +#define A_MAC_TX1_CLK_DIV 0x38184 +#define A_MAC_TX2_CLK_DIV 0x38188 +#define A_MAC_TX3_CLK_DIV 0x3818c +#define A_MAC_TX4_CLK_DIV 0x38190 +#define A_MAC_TX5_CLK_DIV 0x38194 +#define A_MAC_TX6_CLK_DIV 0x38198 +#define A_MAC_TX7_CLK_DIV 0x3819c +#define A_MAC_RX0_CLK_DIV 0x381a0 +#define A_MAC_RX1_CLK_DIV 0x381a4 +#define A_MAC_RX2_CLK_DIV 0x381a8 +#define A_MAC_RX3_CLK_DIV 0x381ac +#define A_MAC_RX4_CLK_DIV 0x381b0 +#define A_MAC_RX5_CLK_DIV 0x381b4 +#define A_MAC_RX6_CLK_DIV 0x381b8 +#define A_MAC_RX7_CLK_DIV 0x381bc +#define A_MAC_SYNC_E_CDR_LANE_SEL 0x381c0 + +#define S_CML_MUX_SEL 11 +#define V_CML_MUX_SEL(x) ((x) << S_CML_MUX_SEL) +#define F_CML_MUX_SEL V_CML_MUX_SEL(1U) + +#define S_CMOS_OUT_EN 10 +#define V_CMOS_OUT_EN(x) ((x) << S_CMOS_OUT_EN) +#define F_CMOS_OUT_EN V_CMOS_OUT_EN(1U) + +#define S_CML_OUT_EN 9 +#define V_CML_OUT_EN(x) ((x) << S_CML_OUT_EN) +#define F_CML_OUT_EN V_CML_OUT_EN(1U) + +#define S_LOC_FAULT_PORT_SEL 6 +#define M_LOC_FAULT_PORT_SEL 0x3U +#define V_LOC_FAULT_PORT_SEL(x) ((x) << S_LOC_FAULT_PORT_SEL) +#define G_LOC_FAULT_PORT_SEL(x) (((x) >> S_LOC_FAULT_PORT_SEL) & M_LOC_FAULT_PORT_SEL) + +#define S_TX_CDR_LANE_SEL 3 +#define M_TX_CDR_LANE_SEL 0x7U +#define V_TX_CDR_LANE_SEL(x) ((x) << S_TX_CDR_LANE_SEL) +#define G_TX_CDR_LANE_SEL(x) (((x) >> S_TX_CDR_LANE_SEL) & M_TX_CDR_LANE_SEL) + +#define S_RX_CDR_LANE_SEL 0 +#define M_RX_CDR_LANE_SEL 0x7U +#define V_RX_CDR_LANE_SEL(x) ((x) << S_RX_CDR_LANE_SEL) +#define G_RX_CDR_LANE_SEL(x) (((x) >> S_RX_CDR_LANE_SEL) & M_RX_CDR_LANE_SEL) + +#define A_MAC_DEBUG_PL_IF_1 0x381c4 +#define A_MAC_SIGNAL_DETECT_CTRL 0x381f0 + +#define S_SIGNAL_DET_LN7 15 +#define V_SIGNAL_DET_LN7(x) ((x) << S_SIGNAL_DET_LN7) +#define F_SIGNAL_DET_LN7 V_SIGNAL_DET_LN7(1U) + +#define S_SIGNAL_DET_LN6 14 +#define V_SIGNAL_DET_LN6(x) ((x) << S_SIGNAL_DET_LN6) +#define F_SIGNAL_DET_LN6 V_SIGNAL_DET_LN6(1U) + +#define S_SIGNAL_DET_LN5 13 +#define V_SIGNAL_DET_LN5(x) ((x) << S_SIGNAL_DET_LN5) +#define F_SIGNAL_DET_LN5 V_SIGNAL_DET_LN5(1U) + +#define S_SIGNAL_DET_LN4 12 +#define V_SIGNAL_DET_LN4(x) ((x) << S_SIGNAL_DET_LN4) +#define F_SIGNAL_DET_LN4 V_SIGNAL_DET_LN4(1U) + +#define S_SIGNAL_DET_LN3 11 +#define V_SIGNAL_DET_LN3(x) ((x) << S_SIGNAL_DET_LN3) +#define F_SIGNAL_DET_LN3 V_SIGNAL_DET_LN3(1U) + +#define S_SIGNAL_DET_LN2 10 +#define V_SIGNAL_DET_LN2(x) ((x) << S_SIGNAL_DET_LN2) +#define F_SIGNAL_DET_LN2 V_SIGNAL_DET_LN2(1U) + +#define S_SIGNAL_DET_LN1 9 +#define V_SIGNAL_DET_LN1(x) ((x) << S_SIGNAL_DET_LN1) +#define F_SIGNAL_DET_LN1 V_SIGNAL_DET_LN1(1U) + +#define S_SIGNAL_DET_LN0 8 +#define V_SIGNAL_DET_LN0(x) ((x) << S_SIGNAL_DET_LN0) +#define F_SIGNAL_DET_LN0 V_SIGNAL_DET_LN0(1U) + +#define S_SIGDETCTRL_LN7 7 +#define V_SIGDETCTRL_LN7(x) ((x) << S_SIGDETCTRL_LN7) +#define F_SIGDETCTRL_LN7 V_SIGDETCTRL_LN7(1U) + +#define S_SIGDETCTRL_LN6 6 +#define V_SIGDETCTRL_LN6(x) ((x) << S_SIGDETCTRL_LN6) +#define F_SIGDETCTRL_LN6 V_SIGDETCTRL_LN6(1U) + +#define S_SIGDETCTRL_LN5 5 +#define V_SIGDETCTRL_LN5(x) ((x) << S_SIGDETCTRL_LN5) +#define F_SIGDETCTRL_LN5 V_SIGDETCTRL_LN5(1U) + +#define S_SIGDETCTRL_LN4 4 +#define V_SIGDETCTRL_LN4(x) ((x) << S_SIGDETCTRL_LN4) +#define F_SIGDETCTRL_LN4 V_SIGDETCTRL_LN4(1U) + +#define S_SIGDETCTRL_LN3 3 +#define V_SIGDETCTRL_LN3(x) ((x) << S_SIGDETCTRL_LN3) +#define F_SIGDETCTRL_LN3 V_SIGDETCTRL_LN3(1U) + +#define S_SIGDETCTRL_LN2 2 +#define V_SIGDETCTRL_LN2(x) ((x) << S_SIGDETCTRL_LN2) +#define F_SIGDETCTRL_LN2 V_SIGDETCTRL_LN2(1U) + +#define S_SIGDETCTRL_LN1 1 +#define V_SIGDETCTRL_LN1(x) ((x) << S_SIGDETCTRL_LN1) +#define F_SIGDETCTRL_LN1 V_SIGDETCTRL_LN1(1U) + +#define S_SIGDETCTRL_LN0 0 +#define V_SIGDETCTRL_LN0(x) ((x) << S_SIGDETCTRL_LN0) +#define F_SIGDETCTRL_LN0 V_SIGDETCTRL_LN0(1U) + +#define A_MAC_FPGA_STATUS_FRM_BOARD 0x381f4 + +#define S_SFP3_RX_LOS 15 +#define V_SFP3_RX_LOS(x) ((x) << S_SFP3_RX_LOS) +#define F_SFP3_RX_LOS V_SFP3_RX_LOS(1U) + +#define S_SFP3_TX_FAULT 14 +#define V_SFP3_TX_FAULT(x) ((x) << S_SFP3_TX_FAULT) +#define F_SFP3_TX_FAULT V_SFP3_TX_FAULT(1U) + +#define S_SFP3_MOD_PRES 13 +#define V_SFP3_MOD_PRES(x) ((x) << S_SFP3_MOD_PRES) +#define F_SFP3_MOD_PRES V_SFP3_MOD_PRES(1U) + +#define S_SFP2_RX_LOS 12 +#define V_SFP2_RX_LOS(x) ((x) << S_SFP2_RX_LOS) +#define F_SFP2_RX_LOS V_SFP2_RX_LOS(1U) + +#define S_SFP2_TX_FAULT 11 +#define V_SFP2_TX_FAULT(x) ((x) << S_SFP2_TX_FAULT) +#define F_SFP2_TX_FAULT V_SFP2_TX_FAULT(1U) + +#define S_SFP2_MOD_PRES 10 +#define V_SFP2_MOD_PRES(x) ((x) << S_SFP2_MOD_PRES) +#define F_SFP2_MOD_PRES V_SFP2_MOD_PRES(1U) + +#define S_SFP1_RX_LOS 9 +#define V_SFP1_RX_LOS(x) ((x) << S_SFP1_RX_LOS) +#define F_SFP1_RX_LOS V_SFP1_RX_LOS(1U) + +#define S_SFP1_TX_FAULT 8 +#define V_SFP1_TX_FAULT(x) ((x) << S_SFP1_TX_FAULT) +#define F_SFP1_TX_FAULT V_SFP1_TX_FAULT(1U) + +#define S_SFP1_MOD_PRES 7 +#define V_SFP1_MOD_PRES(x) ((x) << S_SFP1_MOD_PRES) +#define F_SFP1_MOD_PRES V_SFP1_MOD_PRES(1U) + +#define S_SFP0_RX_LOS 6 +#define V_SFP0_RX_LOS(x) ((x) << S_SFP0_RX_LOS) +#define F_SFP0_RX_LOS V_SFP0_RX_LOS(1U) + +#define S_SFP0_TX_FAULT 5 +#define V_SFP0_TX_FAULT(x) ((x) << S_SFP0_TX_FAULT) +#define F_SFP0_TX_FAULT V_SFP0_TX_FAULT(1U) + +#define S_SFP0_MOD_PRES 4 +#define V_SFP0_MOD_PRES(x) ((x) << S_SFP0_MOD_PRES) +#define F_SFP0_MOD_PRES V_SFP0_MOD_PRES(1U) + +#define S_QSFP1_INT_L 3 +#define V_QSFP1_INT_L(x) ((x) << S_QSFP1_INT_L) +#define F_QSFP1_INT_L V_QSFP1_INT_L(1U) + +#define S_QSFP1_MOD_PRES 2 +#define V_QSFP1_MOD_PRES(x) ((x) << S_QSFP1_MOD_PRES) +#define F_QSFP1_MOD_PRES V_QSFP1_MOD_PRES(1U) + +#define S_QSFP0_INT_L 1 +#define V_QSFP0_INT_L(x) ((x) << S_QSFP0_INT_L) +#define F_QSFP0_INT_L V_QSFP0_INT_L(1U) + +#define S_QSFP0_MOD_PRES 0 +#define V_QSFP0_MOD_PRES(x) ((x) << S_QSFP0_MOD_PRES) +#define F_QSFP0_MOD_PRES V_QSFP0_MOD_PRES(1U) + +#define A_MAC_FPGA_CONTROL_TO_BOARD 0x381f8 + +#define S_T7_1_LB_MODE 10 +#define M_T7_1_LB_MODE 0x3U +#define V_T7_1_LB_MODE(x) ((x) << S_T7_1_LB_MODE) +#define G_T7_1_LB_MODE(x) (((x) >> S_T7_1_LB_MODE) & M_T7_1_LB_MODE) + +#define S_SFP3_TX_DISABLE 9 +#define V_SFP3_TX_DISABLE(x) ((x) << S_SFP3_TX_DISABLE) +#define F_SFP3_TX_DISABLE V_SFP3_TX_DISABLE(1U) + +#define S_SFP2_TX_DISABLE 8 +#define V_SFP2_TX_DISABLE(x) ((x) << S_SFP2_TX_DISABLE) +#define F_SFP2_TX_DISABLE V_SFP2_TX_DISABLE(1U) + +#define S_SFP1_TX_DISABLE 7 +#define V_SFP1_TX_DISABLE(x) ((x) << S_SFP1_TX_DISABLE) +#define F_SFP1_TX_DISABLE V_SFP1_TX_DISABLE(1U) + +#define S_SFP0_TX_DISABLE 6 +#define V_SFP0_TX_DISABLE(x) ((x) << S_SFP0_TX_DISABLE) +#define F_SFP0_TX_DISABLE V_SFP0_TX_DISABLE(1U) + +#define S_QSFP1_LPMODE 5 +#define V_QSFP1_LPMODE(x) ((x) << S_QSFP1_LPMODE) +#define F_QSFP1_LPMODE V_QSFP1_LPMODE(1U) + +#define S_QSFP1_MODSEL_L 4 +#define V_QSFP1_MODSEL_L(x) ((x) << S_QSFP1_MODSEL_L) +#define F_QSFP1_MODSEL_L V_QSFP1_MODSEL_L(1U) + +#define S_QSFP1_RESET_L 3 +#define V_QSFP1_RESET_L(x) ((x) << S_QSFP1_RESET_L) +#define F_QSFP1_RESET_L V_QSFP1_RESET_L(1U) + +#define S_QSFP0_LPMODE 2 +#define V_QSFP0_LPMODE(x) ((x) << S_QSFP0_LPMODE) +#define F_QSFP0_LPMODE V_QSFP0_LPMODE(1U) + +#define S_QSFP0_MODSEL_L 1 +#define V_QSFP0_MODSEL_L(x) ((x) << S_QSFP0_MODSEL_L) +#define F_QSFP0_MODSEL_L V_QSFP0_MODSEL_L(1U) + +#define S_QSFP0_RESET_L 0 +#define V_QSFP0_RESET_L(x) ((x) << S_QSFP0_RESET_L) +#define F_QSFP0_RESET_L V_QSFP0_RESET_L(1U) + +#define A_MAC_FPGA_LINK_STATUS 0x381fc + +#define S_PORT3_FPGA_LINK_UP 3 +#define V_PORT3_FPGA_LINK_UP(x) ((x) << S_PORT3_FPGA_LINK_UP) +#define F_PORT3_FPGA_LINK_UP V_PORT3_FPGA_LINK_UP(1U) + +#define S_PORT2_FPGA_LINK_UP 2 +#define V_PORT2_FPGA_LINK_UP(x) ((x) << S_PORT2_FPGA_LINK_UP) +#define F_PORT2_FPGA_LINK_UP V_PORT2_FPGA_LINK_UP(1U) + +#define S_PORT1_FPGA_LINK_UP 1 +#define V_PORT1_FPGA_LINK_UP(x) ((x) << S_PORT1_FPGA_LINK_UP) +#define F_PORT1_FPGA_LINK_UP V_PORT1_FPGA_LINK_UP(1U) + +#define S_PORT0_FPGA_LINK_UP 0 +#define V_PORT0_FPGA_LINK_UP(x) ((x) << S_PORT0_FPGA_LINK_UP) +#define F_PORT0_FPGA_LINK_UP V_PORT0_FPGA_LINK_UP(1U) + +#define A_MAC_MTIP_MAC400G_0_MTIP_REVISION 0x38200 + +#define S_MTIP_REV_400G_0 0 +#define M_MTIP_REV_400G_0 0xffU +#define V_MTIP_REV_400G_0(x) ((x) << S_MTIP_REV_400G_0) +#define G_MTIP_REV_400G_0(x) (((x) >> S_MTIP_REV_400G_0) & M_MTIP_REV_400G_0) + +#define A_MAC_MTIP_MAC400G_0_MTIP_SCRATCH 0x38204 +#define A_MAC_MTIP_MAC400G_0_MTIP_COMMAND_CONFIG 0x38208 + +#define S_INV_LOOP 31 +#define V_INV_LOOP(x) ((x) << S_INV_LOOP) +#define F_INV_LOOP V_INV_LOOP(1U) + +#define S_TX_FLUSH_ENABLE_400G_0 22 +#define V_TX_FLUSH_ENABLE_400G_0(x) ((x) << S_TX_FLUSH_ENABLE_400G_0) +#define F_TX_FLUSH_ENABLE_400G_0 V_TX_FLUSH_ENABLE_400G_0(1U) + +#define S_PHY_LOOPBACK_EN_400G 10 +#define V_PHY_LOOPBACK_EN_400G(x) ((x) << S_PHY_LOOPBACK_EN_400G) +#define F_PHY_LOOPBACK_EN_400G V_PHY_LOOPBACK_EN_400G(1U) + +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_0 0x3820c +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1 0x38210 +#define A_MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH 0x38214 +#define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS 0x3821c +#define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS 0x38220 +#define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E 0x38224 +#define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_ALMOST_F_E 0x38228 +#define A_MAC_MTIP_MAC400G_0_MTIP_HASHTABLE_LOAD 0x3822c +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_STATUS 0x38240 +#define A_MAC_MTIP_MAC400G_0_MTIP_TX_IPG_LENGTH 0x38244 + +#define S_T7_IPG 19 +#define M_T7_IPG 0x1fffU +#define V_T7_IPG(x) ((x) << S_T7_IPG) +#define G_T7_IPG(x) (((x) >> S_T7_IPG) & M_T7_IPG) + +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA 0x38254 +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA 0x38258 +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA 0x3825c +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA 0x38260 +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38264 + +#define S_CL1_PAUSE_QUANTA_THRESH 16 +#define M_CL1_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL1_PAUSE_QUANTA_THRESH(x) ((x) << S_CL1_PAUSE_QUANTA_THRESH) +#define G_CL1_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL1_PAUSE_QUANTA_THRESH) & M_CL1_PAUSE_QUANTA_THRESH) + +#define S_CL0_PAUSE_QUANTA_THRESH 0 +#define M_CL0_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL0_PAUSE_QUANTA_THRESH(x) ((x) << S_CL0_PAUSE_QUANTA_THRESH) +#define G_CL0_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL0_PAUSE_QUANTA_THRESH) & M_CL0_PAUSE_QUANTA_THRESH) + +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38268 + +#define S_CL3_PAUSE_QUANTA_THRESH 16 +#define M_CL3_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL3_PAUSE_QUANTA_THRESH(x) ((x) << S_CL3_PAUSE_QUANTA_THRESH) +#define G_CL3_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL3_PAUSE_QUANTA_THRESH) & M_CL3_PAUSE_QUANTA_THRESH) + +#define S_CL2_PAUSE_QUANTA_THRESH 0 +#define M_CL2_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL2_PAUSE_QUANTA_THRESH(x) ((x) << S_CL2_PAUSE_QUANTA_THRESH) +#define G_CL2_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL2_PAUSE_QUANTA_THRESH) & M_CL2_PAUSE_QUANTA_THRESH) + +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3826c + +#define S_CL5_PAUSE_QUANTA_THRESH 16 +#define M_CL5_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL5_PAUSE_QUANTA_THRESH(x) ((x) << S_CL5_PAUSE_QUANTA_THRESH) +#define G_CL5_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL5_PAUSE_QUANTA_THRESH) & M_CL5_PAUSE_QUANTA_THRESH) + +#define S_CL4_PAUSE_QUANTA_THRESH 0 +#define M_CL4_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL4_PAUSE_QUANTA_THRESH(x) ((x) << S_CL4_PAUSE_QUANTA_THRESH) +#define G_CL4_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL4_PAUSE_QUANTA_THRESH) & M_CL4_PAUSE_QUANTA_THRESH) + +#define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38270 + +#define S_CL7_PAUSE_QUANTA_THRESH 16 +#define M_CL7_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL7_PAUSE_QUANTA_THRESH(x) ((x) << S_CL7_PAUSE_QUANTA_THRESH) +#define G_CL7_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL7_PAUSE_QUANTA_THRESH) & M_CL7_PAUSE_QUANTA_THRESH) + +#define S_CL6_PAUSE_QUANTA_THRESH 0 +#define M_CL6_PAUSE_QUANTA_THRESH 0xffffU +#define V_CL6_PAUSE_QUANTA_THRESH(x) ((x) << S_CL6_PAUSE_QUANTA_THRESH) +#define G_CL6_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL6_PAUSE_QUANTA_THRESH) & M_CL6_PAUSE_QUANTA_THRESH) + +#define A_MAC_MTIP_MAC400G_0_MTIP_RX_PAUSE_STATUS 0x38274 + +#define S_RX_PAUSE_STATUS 0 +#define M_RX_PAUSE_STATUS 0xffU +#define V_RX_PAUSE_STATUS(x) ((x) << S_RX_PAUSE_STATUS) +#define G_RX_PAUSE_STATUS(x) (((x) >> S_RX_PAUSE_STATUS) & M_RX_PAUSE_STATUS) + +#define A_MAC_MTIP_MAC400G_0_MTIP_TS_TIMESTAMP 0x3827c +#define A_MAC_MTIP_MAC400G_0_MTIP_XIF_MODE 0x38280 +#define A_MAC_MTIP_MAC400G_1_MTIP_REVISION 0x38300 + +#define S_MTIP_REV_400G_1 0 +#define M_MTIP_REV_400G_1 0xffU +#define V_MTIP_REV_400G_1(x) ((x) << S_MTIP_REV_400G_1) +#define G_MTIP_REV_400G_1(x) (((x) >> S_MTIP_REV_400G_1) & M_MTIP_REV_400G_1) + +#define A_MAC_MTIP_MAC400G_1_MTIP_SCRATCH 0x38304 +#define A_MAC_MTIP_MAC400G_1_MTIP_COMMAND_CONFIG 0x38308 + +#define S_TX_FLUSH_ENABLE_400G_1 22 +#define V_TX_FLUSH_ENABLE_400G_1(x) ((x) << S_TX_FLUSH_ENABLE_400G_1) +#define F_TX_FLUSH_ENABLE_400G_1 V_TX_FLUSH_ENABLE_400G_1(1U) + +#define S_PHY_LOOPBACK_EN_400G_1 10 +#define V_PHY_LOOPBACK_EN_400G_1(x) ((x) << S_PHY_LOOPBACK_EN_400G_1) +#define F_PHY_LOOPBACK_EN_400G_1 V_PHY_LOOPBACK_EN_400G_1(1U) + +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_0 0x3830c +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_1 0x38310 +#define A_MAC_MTIP_MAC400G_1_MTIP_FRM_LENGTH 0x38314 +#define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_SECTIONS 0x3831c +#define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_SECTIONS 0x38320 +#define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_ALMOST_F_E 0x38324 +#define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_ALMOST_F_E 0x38328 +#define A_MAC_MTIP_MAC400G_1_MTIP_HASHTABLE_LOAD 0x3832c + +#define S_ENABLE_MCAST_RX_400G_1 8 +#define V_ENABLE_MCAST_RX_400G_1(x) ((x) << S_ENABLE_MCAST_RX_400G_1) +#define F_ENABLE_MCAST_RX_400G_1 V_ENABLE_MCAST_RX_400G_1(1U) + +#define S_HASHTABLE_ADDR_400G_1 0 +#define M_HASHTABLE_ADDR_400G_1 0x3fU +#define V_HASHTABLE_ADDR_400G_1(x) ((x) << S_HASHTABLE_ADDR_400G_1) +#define G_HASHTABLE_ADDR_400G_1(x) (((x) >> S_HASHTABLE_ADDR_400G_1) & M_HASHTABLE_ADDR_400G_1) + +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_STATUS 0x38340 +#define A_MAC_MTIP_MAC400G_1_MTIP_TX_IPG_LENGTH 0x38344 +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA 0x38354 +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA 0x38358 +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA 0x3835c +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA 0x38360 +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38364 +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38368 +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3836c +#define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38370 +#define A_MAC_MTIP_MAC400G_1_MTIP_RX_PAUSE_STATUS 0x38374 +#define A_MAC_MTIP_MAC400G_1_MTIP_TS_TIMESTAMP 0x3837c +#define A_MAC_MTIP_MAC400G_1_MTIP_XIF_MODE 0x38380 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_1 0x38400 + +#define S_T7_SPEED_SELECTION 2 +#define V_T7_SPEED_SELECTION(x) ((x) << S_T7_SPEED_SELECTION) +#define F_T7_SPEED_SELECTION V_T7_SPEED_SELECTION(1U) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_1 0x38404 + +#define S_400G_RX_LINK_STATUS 2 +#define V_400G_RX_LINK_STATUS(x) ((x) << S_400G_RX_LINK_STATUS) +#define F_400G_RX_LINK_STATUS V_400G_RX_LINK_STATUS(1U) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID0 0x38408 + +#define S_400G_DEVICE_ID0_0 0 +#define M_400G_DEVICE_ID0_0 0xffffU +#define V_400G_DEVICE_ID0_0(x) ((x) << S_400G_DEVICE_ID0_0) +#define G_400G_DEVICE_ID0_0(x) (((x) >> S_400G_DEVICE_ID0_0) & M_400G_DEVICE_ID0_0) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID1 0x3840c + +#define S_400G_DEVICE_ID1_0 0 +#define M_400G_DEVICE_ID1_0 0xffffU +#define V_400G_DEVICE_ID1_0(x) ((x) << S_400G_DEVICE_ID1_0) +#define G_400G_DEVICE_ID1_0(x) (((x) >> S_400G_DEVICE_ID1_0) & M_400G_DEVICE_ID1_0) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_SPEED_ABILITY 0x38410 + +#define S_400G_CAPABLE_0 9 +#define V_400G_CAPABLE_0(x) ((x) << S_400G_CAPABLE_0) +#define F_400G_CAPABLE_0 V_400G_CAPABLE_0(1U) + +#define S_200G_CAPABLE_0 8 +#define V_200G_CAPABLE_0(x) ((x) << S_200G_CAPABLE_0) +#define F_200G_CAPABLE_0 V_200G_CAPABLE_0(1U) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG1 0x38414 + +#define S_DEVICE_PACKAGE 3 +#define V_DEVICE_PACKAGE(x) ((x) << S_DEVICE_PACKAGE) +#define F_DEVICE_PACKAGE V_DEVICE_PACKAGE(1U) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG2 0x38418 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_2 0x3841c + +#define S_400G_PCS_TYPE_SELECTION_0 0 +#define M_400G_PCS_TYPE_SELECTION_0 0xfU +#define V_400G_PCS_TYPE_SELECTION_0(x) ((x) << S_400G_PCS_TYPE_SELECTION_0) +#define G_400G_PCS_TYPE_SELECTION_0(x) (((x) >> S_400G_PCS_TYPE_SELECTION_0) & M_400G_PCS_TYPE_SELECTION_0) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_2 0x38420 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_3 0x38424 + +#define S_T7_DEVICE_PRESENT 2 +#define M_T7_DEVICE_PRESENT 0x3fffU +#define V_T7_DEVICE_PRESENT(x) ((x) << S_T7_DEVICE_PRESENT) +#define G_T7_DEVICE_PRESENT(x) (((x) >> S_T7_DEVICE_PRESENT) & M_T7_DEVICE_PRESENT) + +#define S_400GBASE_R 1 +#define V_400GBASE_R(x) ((x) << S_400GBASE_R) +#define F_400GBASE_R V_400GBASE_R(1U) + +#define S_200GBASE_R 0 +#define V_200GBASE_R(x) ((x) << S_200GBASE_R) +#define F_200GBASE_R V_200GBASE_R(1U) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID0 0x38438 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID1 0x3843c +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_1 0x38480 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_2 0x38484 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_CONTROL 0x384a8 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_ERR_CNT 0x384ac +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_BER_HIGH_ORDER_CNT 0x384b0 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x384b4 + +#define S_HIGH_ORDER 15 +#define V_HIGH_ORDER(x) ((x) << S_HIGH_ORDER) +#define F_HIGH_ORDER V_HIGH_ORDER(1U) + +#define S_ERROR_BLOCK_COUNTER 0 +#define M_ERROR_BLOCK_COUNTER 0x3fffU +#define V_ERROR_BLOCK_COUNTER(x) ((x) << S_ERROR_BLOCK_COUNTER) +#define G_ERROR_BLOCK_COUNTER(x) (((x) >> S_ERROR_BLOCK_COUNTER) & M_ERROR_BLOCK_COUNTER) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x384c8 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x384cc +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x384d0 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x384d4 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_0_MAPPING 0x384d8 + +#define S_T7_LANE_0_MAPPING 0 +#define M_T7_LANE_0_MAPPING 0xfU +#define V_T7_LANE_0_MAPPING(x) ((x) << S_T7_LANE_0_MAPPING) +#define G_T7_LANE_0_MAPPING(x) (((x) >> S_T7_LANE_0_MAPPING) & M_T7_LANE_0_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_1_MAPPING 0x384dc + +#define S_T7_LANE_1_MAPPING 0 +#define M_T7_LANE_1_MAPPING 0xfU +#define V_T7_LANE_1_MAPPING(x) ((x) << S_T7_LANE_1_MAPPING) +#define G_T7_LANE_1_MAPPING(x) (((x) >> S_T7_LANE_1_MAPPING) & M_T7_LANE_1_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_2_MAPPING 0x384e0 + +#define S_T7_LANE_2_MAPPING 0 +#define M_T7_LANE_2_MAPPING 0xfU +#define V_T7_LANE_2_MAPPING(x) ((x) << S_T7_LANE_2_MAPPING) +#define G_T7_LANE_2_MAPPING(x) (((x) >> S_T7_LANE_2_MAPPING) & M_T7_LANE_2_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_3_MAPPING 0x384e4 + +#define S_T7_LANE_3_MAPPING 0 +#define M_T7_LANE_3_MAPPING 0xfU +#define V_T7_LANE_3_MAPPING(x) ((x) << S_T7_LANE_3_MAPPING) +#define G_T7_LANE_3_MAPPING(x) (((x) >> S_T7_LANE_3_MAPPING) & M_T7_LANE_3_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_4_MAPPING 0x384e8 + +#define S_T7_LANE_4_MAPPING 0 +#define M_T7_LANE_4_MAPPING 0xfU +#define V_T7_LANE_4_MAPPING(x) ((x) << S_T7_LANE_4_MAPPING) +#define G_T7_LANE_4_MAPPING(x) (((x) >> S_T7_LANE_4_MAPPING) & M_T7_LANE_4_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_5_MAPPING 0x384ec + +#define S_T7_LANE_5_MAPPING 0 +#define M_T7_LANE_5_MAPPING 0xfU +#define V_T7_LANE_5_MAPPING(x) ((x) << S_T7_LANE_5_MAPPING) +#define G_T7_LANE_5_MAPPING(x) (((x) >> S_T7_LANE_5_MAPPING) & M_T7_LANE_5_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_6_MAPPING 0x384f0 + +#define S_T7_LANE_6_MAPPING 0 +#define M_T7_LANE_6_MAPPING 0xfU +#define V_T7_LANE_6_MAPPING(x) ((x) << S_T7_LANE_6_MAPPING) +#define G_T7_LANE_6_MAPPING(x) (((x) >> S_T7_LANE_6_MAPPING) & M_T7_LANE_6_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_7_MAPPING 0x384f4 + +#define S_T7_LANE_7_MAPPING 0 +#define M_T7_LANE_7_MAPPING 0xfU +#define V_T7_LANE_7_MAPPING(x) ((x) << S_T7_LANE_7_MAPPING) +#define G_T7_LANE_7_MAPPING(x) (((x) >> S_T7_LANE_7_MAPPING) & M_T7_LANE_7_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_8_MAPPING 0x384f8 + +#define S_T7_LANE_8_MAPPING 0 +#define M_T7_LANE_8_MAPPING 0xfU +#define V_T7_LANE_8_MAPPING(x) ((x) << S_T7_LANE_8_MAPPING) +#define G_T7_LANE_8_MAPPING(x) (((x) >> S_T7_LANE_8_MAPPING) & M_T7_LANE_8_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_9_MAPPING 0x384fc + +#define S_T7_LANE_9_MAPPING 0 +#define M_T7_LANE_9_MAPPING 0xfU +#define V_T7_LANE_9_MAPPING(x) ((x) << S_T7_LANE_9_MAPPING) +#define G_T7_LANE_9_MAPPING(x) (((x) >> S_T7_LANE_9_MAPPING) & M_T7_LANE_9_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_10_MAPPING 0x38500 + +#define S_T7_LANE_10_MAPPING 0 +#define M_T7_LANE_10_MAPPING 0xfU +#define V_T7_LANE_10_MAPPING(x) ((x) << S_T7_LANE_10_MAPPING) +#define G_T7_LANE_10_MAPPING(x) (((x) >> S_T7_LANE_10_MAPPING) & M_T7_LANE_10_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_11_MAPPING 0x38504 + +#define S_T7_LANE_11_MAPPING 0 +#define M_T7_LANE_11_MAPPING 0xfU +#define V_T7_LANE_11_MAPPING(x) ((x) << S_T7_LANE_11_MAPPING) +#define G_T7_LANE_11_MAPPING(x) (((x) >> S_T7_LANE_11_MAPPING) & M_T7_LANE_11_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_12_MAPPING 0x38508 + +#define S_T7_LANE_12_MAPPING 0 +#define M_T7_LANE_12_MAPPING 0xfU +#define V_T7_LANE_12_MAPPING(x) ((x) << S_T7_LANE_12_MAPPING) +#define G_T7_LANE_12_MAPPING(x) (((x) >> S_T7_LANE_12_MAPPING) & M_T7_LANE_12_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_13_MAPPING 0x3850c + +#define S_T7_LANE_13_MAPPING 0 +#define M_T7_LANE_13_MAPPING 0xfU +#define V_T7_LANE_13_MAPPING(x) ((x) << S_T7_LANE_13_MAPPING) +#define G_T7_LANE_13_MAPPING(x) (((x) >> S_T7_LANE_13_MAPPING) & M_T7_LANE_13_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_14_MAPPING 0x38510 + +#define S_T7_LANE_14_MAPPING 0 +#define M_T7_LANE_14_MAPPING 0xfU +#define V_T7_LANE_14_MAPPING(x) ((x) << S_T7_LANE_14_MAPPING) +#define G_T7_LANE_14_MAPPING(x) (((x) >> S_T7_LANE_14_MAPPING) & M_T7_LANE_14_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_15_MAPPING 0x38514 + +#define S_T7_LANE_15_MAPPING 0 +#define M_T7_LANE_15_MAPPING 0xfU +#define V_T7_LANE_15_MAPPING(x) ((x) << S_T7_LANE_15_MAPPING) +#define G_T7_LANE_15_MAPPING(x) (((x) >> S_T7_LANE_15_MAPPING) & M_T7_LANE_15_MAPPING) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_SCRATCH 0x38600 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CORE_REVISION 0x38604 +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_CL_INTVL 0x38608 + +#define S_T7_VL_INTVL 0 +#define M_T7_VL_INTVL 0xffffU +#define V_T7_VL_INTVL(x) ((x) << S_T7_VL_INTVL) +#define G_T7_VL_INTVL(x) (((x) >> S_T7_VL_INTVL) & M_T7_VL_INTVL) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_LANE_THRESH 0x3860c + +#define S_TX_LANE_THRESH 0 +#define M_TX_LANE_THRESH 0xfU +#define V_TX_LANE_THRESH(x) ((x) << S_TX_LANE_THRESH) +#define G_TX_LANE_THRESH(x) (((x) >> S_TX_LANE_THRESH) & M_TX_LANE_THRESH) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_CDMII_PACE 0x3861c + +#define S_TX_CDMII_PACE 0 +#define M_TX_CDMII_PACE 0xfU +#define V_TX_CDMII_PACE(x) ((x) << S_TX_CDMII_PACE) +#define G_TX_CDMII_PACE(x) (((x) >> S_TX_CDMII_PACE) & M_TX_CDMII_PACE) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_0 0x38620 + +#define S_AM_0 0 +#define M_AM_0 0xffffU +#define V_AM_0(x) ((x) << S_AM_0) +#define G_AM_0(x) (((x) >> S_AM_0) & M_AM_0) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_1 0x38624 + +#define S_AM_1 0 +#define M_AM_1 0xffffU +#define V_AM_1(x) ((x) << S_AM_1) +#define G_AM_1(x) (((x) >> S_AM_1) & M_AM_1) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO0 0x38800 + +#define S_DBGINFO0 0 +#define M_DBGINFO0 0xffffU +#define V_DBGINFO0(x) ((x) << S_DBGINFO0) +#define G_DBGINFO0(x) (((x) >> S_DBGINFO0) & M_DBGINFO0) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO1 0x38804 + +#define S_DBGINFO1 0 +#define M_DBGINFO1 0xffffU +#define V_DBGINFO1(x) ((x) << S_DBGINFO1) +#define G_DBGINFO1(x) (((x) >> S_DBGINFO1) & M_DBGINFO1) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO2 0x38808 + +#define S_DBGINFO2 0 +#define M_DBGINFO2 0xffffU +#define V_DBGINFO2(x) ((x) << S_DBGINFO2) +#define G_DBGINFO2(x) (((x) >> S_DBGINFO2) & M_DBGINFO2) + +#define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO3 0x3880c + +#define S_DBGINFO3 0 +#define M_DBGINFO3 0xffffU +#define V_DBGINFO3(x) ((x) << S_DBGINFO3) +#define G_DBGINFO3(x) (((x) >> S_DBGINFO3) & M_DBGINFO3) + +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_1 0x38900 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_1 0x38904 + +#define S_400G_RX_LINK_STATUS_1 2 +#define V_400G_RX_LINK_STATUS_1(x) ((x) << S_400G_RX_LINK_STATUS_1) +#define F_400G_RX_LINK_STATUS_1 V_400G_RX_LINK_STATUS_1(1U) + +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID0 0x38908 + +#define S_400G_DEVICE_ID0_1 0 +#define M_400G_DEVICE_ID0_1 0xffffU +#define V_400G_DEVICE_ID0_1(x) ((x) << S_400G_DEVICE_ID0_1) +#define G_400G_DEVICE_ID0_1(x) (((x) >> S_400G_DEVICE_ID0_1) & M_400G_DEVICE_ID0_1) + +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID1 0x3890c + +#define S_400G_DEVICE_ID1_1 0 +#define M_400G_DEVICE_ID1_1 0xffffU +#define V_400G_DEVICE_ID1_1(x) ((x) << S_400G_DEVICE_ID1_1) +#define G_400G_DEVICE_ID1_1(x) (((x) >> S_400G_DEVICE_ID1_1) & M_400G_DEVICE_ID1_1) + +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_SPEED_ABILITY 0x38910 + +#define S_400G_CAPABLE_1 9 +#define V_400G_CAPABLE_1(x) ((x) << S_400G_CAPABLE_1) +#define F_400G_CAPABLE_1 V_400G_CAPABLE_1(1U) + +#define S_200G_CAPABLE_1 8 +#define V_200G_CAPABLE_1(x) ((x) << S_200G_CAPABLE_1) +#define F_200G_CAPABLE_1 V_200G_CAPABLE_1(1U) + +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG1 0x38914 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG2 0x38918 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_2 0x3891c + +#define S_400G_PCS_TYPE_SELECTION_1 0 +#define M_400G_PCS_TYPE_SELECTION_1 0xfU +#define V_400G_PCS_TYPE_SELECTION_1(x) ((x) << S_400G_PCS_TYPE_SELECTION_1) +#define G_400G_PCS_TYPE_SELECTION_1(x) (((x) >> S_400G_PCS_TYPE_SELECTION_1) & M_400G_PCS_TYPE_SELECTION_1) + +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_2 0x38920 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_3 0x38924 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID0 0x38938 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID1 0x3893c +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_1 0x38980 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_2 0x38984 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_CONTROL 0x389a8 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_ERR_CNT 0x389ac +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_BER_HIGH_ORDER_CNT 0x389b0 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x389b4 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x389c8 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x389cc +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x389d0 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x389d4 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_0_MAPPING 0x389d8 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_1_MAPPING 0x389dc +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_2_MAPPING 0x389e0 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_3_MAPPING 0x389e4 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_4_MAPPING 0x389e8 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_5_MAPPING 0x389ec +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_6_MAPPING 0x389f0 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_7_MAPPING 0x389f4 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_8_MAPPING 0x389f8 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_9_MAPPING 0x389fc +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_10_MAPPING 0x38a00 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_11_MAPPING 0x38a04 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_12_MAPPING 0x38a08 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_13_MAPPING 0x38a0c +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_14_MAPPING 0x38a10 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_15_MAPPING 0x38a14 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_SCRATCH 0x38b00 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CORE_REVISION 0x38b04 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_CL_INTVL 0x38b08 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_LANE_THRESH 0x38b0c +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_CDMII_PACE 0x38b1c +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_0 0x38b20 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_1 0x38b24 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO0 0x38d00 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO1 0x38d04 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO2 0x38d08 +#define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO3 0x38d0c +#define A_MAC_MTIP_RS_FEC_CONTROL_0_0 0x38e00 + +#define S_TC_PAD_ALTER 10 +#define V_TC_PAD_ALTER(x) ((x) << S_TC_PAD_ALTER) +#define F_TC_PAD_ALTER V_TC_PAD_ALTER(1U) + +#define S_TC_PAD_VALUE 9 +#define V_TC_PAD_VALUE(x) ((x) << S_TC_PAD_VALUE) +#define F_TC_PAD_VALUE V_TC_PAD_VALUE(1U) + +#define S_KP_ENABLE 8 +#define V_KP_ENABLE(x) ((x) << S_KP_ENABLE) +#define F_KP_ENABLE V_KP_ENABLE(1U) + +#define S_AM16_COPY_DIS 3 +#define V_AM16_COPY_DIS(x) ((x) << S_AM16_COPY_DIS) +#define F_AM16_COPY_DIS V_AM16_COPY_DIS(1U) + +#define S_RS_FEC_DEGRADE_OPTION_ENA 2 +#define V_RS_FEC_DEGRADE_OPTION_ENA(x) ((x) << S_RS_FEC_DEGRADE_OPTION_ENA) +#define F_RS_FEC_DEGRADE_OPTION_ENA V_RS_FEC_DEGRADE_OPTION_ENA(1U) + +#define A_MAC_MTIP_RS_FEC_STATUS_0_0 0x38e04 + +#define S_FEC_STATUS_0_14 14 +#define V_FEC_STATUS_0_14(x) ((x) << S_FEC_STATUS_0_14) +#define F_FEC_STATUS_0_14 V_FEC_STATUS_0_14(1U) + +#define S_FEC_STATUS_0_11 8 +#define M_FEC_STATUS_0_11 0xfU +#define V_FEC_STATUS_0_11(x) ((x) << S_FEC_STATUS_0_11) +#define G_FEC_STATUS_0_11(x) (((x) >> S_FEC_STATUS_0_11) & M_FEC_STATUS_0_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED0_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED0_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED0_0 V_RS_FEC_DEGRADE_SER_RECEIVED0_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED0_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED0_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED0_1 V_RS_FEC_DEGRADE_SER_RECEIVED0_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED0_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED0_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED0_2 V_RS_FEC_DEGRADE_SER_RECEIVED0_2(1U) + +#define S_FEC_STATUS_0_4 4 +#define V_FEC_STATUS_0_4(x) ((x) << S_FEC_STATUS_0_4) +#define F_FEC_STATUS_0_4 V_FEC_STATUS_0_4(1U) + +#define S_FEC_STATUS_0_3 3 +#define V_FEC_STATUS_0_3(x) ((x) << S_FEC_STATUS_0_3) +#define F_FEC_STATUS_0_3 V_FEC_STATUS_0_3(1U) + +#define S_FEC_STATUS_0_2 2 +#define V_FEC_STATUS_0_2(x) ((x) << S_FEC_STATUS_0_2) +#define F_FEC_STATUS_0_2 V_FEC_STATUS_0_2(1U) + +#define S_FEC_STATUS_0_1 1 +#define V_FEC_STATUS_0_1(x) ((x) << S_FEC_STATUS_0_1) +#define F_FEC_STATUS_0_1 V_FEC_STATUS_0_1(1U) + +#define S_FEC_STATUS_0_0 0 +#define V_FEC_STATUS_0_0(x) ((x) << S_FEC_STATUS_0_0) +#define F_FEC_STATUS_0_0 V_FEC_STATUS_0_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_0 0x38e08 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_0 0x38e0c +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_0 0x38e10 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_0 0x38e14 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_0 0x38e18 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_0 0x38e1c + +#define S_DEC_TRESH 0 +#define M_DEC_TRESH 0x3fU +#define V_DEC_TRESH(x) ((x) << S_DEC_TRESH) +#define G_DEC_TRESH(x) (((x) >> S_DEC_TRESH) & M_DEC_TRESH) + +#define A_MAC_MTIP_RS_FEC_CONTROL_0_1 0x38e20 +#define A_MAC_MTIP_RS_FEC_STATUS_0_1 0x38e24 + +#define S_FEC_STATUS_1_14 14 +#define V_FEC_STATUS_1_14(x) ((x) << S_FEC_STATUS_1_14) +#define F_FEC_STATUS_1_14 V_FEC_STATUS_1_14(1U) + +#define S_FEC_STATUS_1_11 8 +#define M_FEC_STATUS_1_11 0xfU +#define V_FEC_STATUS_1_11(x) ((x) << S_FEC_STATUS_1_11) +#define G_FEC_STATUS_1_11(x) (((x) >> S_FEC_STATUS_1_11) & M_FEC_STATUS_1_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED1_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED1_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED1_0 V_RS_FEC_DEGRADE_SER_RECEIVED1_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED1_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED1_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED1_1 V_RS_FEC_DEGRADE_SER_RECEIVED1_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED1_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED1_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED1_2 V_RS_FEC_DEGRADE_SER_RECEIVED1_2(1U) + +#define S_FEC_STATUS_1_4 4 +#define V_FEC_STATUS_1_4(x) ((x) << S_FEC_STATUS_1_4) +#define F_FEC_STATUS_1_4 V_FEC_STATUS_1_4(1U) + +#define S_FEC_STATUS_1_3 3 +#define V_FEC_STATUS_1_3(x) ((x) << S_FEC_STATUS_1_3) +#define F_FEC_STATUS_1_3 V_FEC_STATUS_1_3(1U) + +#define S_FEC_STATUS_1_2 2 +#define V_FEC_STATUS_1_2(x) ((x) << S_FEC_STATUS_1_2) +#define F_FEC_STATUS_1_2 V_FEC_STATUS_1_2(1U) + +#define S_FEC_STATUS_1_1 1 +#define V_FEC_STATUS_1_1(x) ((x) << S_FEC_STATUS_1_1) +#define F_FEC_STATUS_1_1 V_FEC_STATUS_1_1(1U) + +#define S_FEC_STATUS_1_0 0 +#define V_FEC_STATUS_1_0(x) ((x) << S_FEC_STATUS_1_0) +#define F_FEC_STATUS_1_0 V_FEC_STATUS_1_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_1 0x38e28 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_1 0x38e2c +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_1 0x38e30 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_1 0x38e34 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_1 0x38e38 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_1 0x38e3c +#define A_MAC_MTIP_RS_FEC_CONTROL_0_2 0x38e40 +#define A_MAC_MTIP_RS_FEC_STATUS_0_2 0x38e44 + +#define S_FEC_STATUS_2_14 14 +#define V_FEC_STATUS_2_14(x) ((x) << S_FEC_STATUS_2_14) +#define F_FEC_STATUS_2_14 V_FEC_STATUS_2_14(1U) + +#define S_FEC_STATUS_2_11 8 +#define M_FEC_STATUS_2_11 0xfU +#define V_FEC_STATUS_2_11(x) ((x) << S_FEC_STATUS_2_11) +#define G_FEC_STATUS_2_11(x) (((x) >> S_FEC_STATUS_2_11) & M_FEC_STATUS_2_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED2_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED2_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED2_0 V_RS_FEC_DEGRADE_SER_RECEIVED2_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED2_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED2_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED2_1 V_RS_FEC_DEGRADE_SER_RECEIVED2_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED2_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED2_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED2_2 V_RS_FEC_DEGRADE_SER_RECEIVED2_2(1U) + +#define S_FEC_STATUS_2_4 4 +#define V_FEC_STATUS_2_4(x) ((x) << S_FEC_STATUS_2_4) +#define F_FEC_STATUS_2_4 V_FEC_STATUS_2_4(1U) + +#define S_FEC_STATUS_2_3 3 +#define V_FEC_STATUS_2_3(x) ((x) << S_FEC_STATUS_2_3) +#define F_FEC_STATUS_2_3 V_FEC_STATUS_2_3(1U) + +#define S_FEC_STATUS_2_2 2 +#define V_FEC_STATUS_2_2(x) ((x) << S_FEC_STATUS_2_2) +#define F_FEC_STATUS_2_2 V_FEC_STATUS_2_2(1U) + +#define S_FEC_STATUS_2_1 1 +#define V_FEC_STATUS_2_1(x) ((x) << S_FEC_STATUS_2_1) +#define F_FEC_STATUS_2_1 V_FEC_STATUS_2_1(1U) + +#define S_FEC_STATUS_2_0 0 +#define V_FEC_STATUS_2_0(x) ((x) << S_FEC_STATUS_2_0) +#define F_FEC_STATUS_2_0 V_FEC_STATUS_2_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_2 0x38e48 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_2 0x38e4c +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_2 0x38e50 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_2 0x38e54 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_2 0x38e58 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_2 0x38e5c +#define A_MAC_MTIP_RS_FEC_CONTROL_0_3 0x38e60 +#define A_MAC_MTIP_RS_FEC_STATUS_0_3 0x38e64 + +#define S_FEC_STATUS_3_14 14 +#define V_FEC_STATUS_3_14(x) ((x) << S_FEC_STATUS_3_14) +#define F_FEC_STATUS_3_14 V_FEC_STATUS_3_14(1U) + +#define S_FEC_STATUS_3_11 8 +#define M_FEC_STATUS_3_11 0xfU +#define V_FEC_STATUS_3_11(x) ((x) << S_FEC_STATUS_3_11) +#define G_FEC_STATUS_3_11(x) (((x) >> S_FEC_STATUS_3_11) & M_FEC_STATUS_3_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED3_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED3_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED3_0 V_RS_FEC_DEGRADE_SER_RECEIVED3_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED3_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED3_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED3_1 V_RS_FEC_DEGRADE_SER_RECEIVED3_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED3_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED3_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED3_2 V_RS_FEC_DEGRADE_SER_RECEIVED3_2(1U) + +#define S_FEC_STATUS_3_4 4 +#define V_FEC_STATUS_3_4(x) ((x) << S_FEC_STATUS_3_4) +#define F_FEC_STATUS_3_4 V_FEC_STATUS_3_4(1U) + +#define S_FEC_STATUS_3_3 3 +#define V_FEC_STATUS_3_3(x) ((x) << S_FEC_STATUS_3_3) +#define F_FEC_STATUS_3_3 V_FEC_STATUS_3_3(1U) + +#define S_FEC_STATUS_3_2 2 +#define V_FEC_STATUS_3_2(x) ((x) << S_FEC_STATUS_3_2) +#define F_FEC_STATUS_3_2 V_FEC_STATUS_3_2(1U) + +#define S_FEC_STATUS_3_1 1 +#define V_FEC_STATUS_3_1(x) ((x) << S_FEC_STATUS_3_1) +#define F_FEC_STATUS_3_1 V_FEC_STATUS_3_1(1U) + +#define S_FEC_STATUS_3_0 0 +#define V_FEC_STATUS_3_0(x) ((x) << S_FEC_STATUS_3_0) +#define F_FEC_STATUS_3_0 V_FEC_STATUS_3_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_3 0x38e68 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_3 0x38e6c +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_3 0x38e70 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_3 0x38e74 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_3 0x38e78 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_3 0x38e7c +#define A_MAC_MTIP_RS_FEC_CONTROL_0_4 0x38e80 +#define A_MAC_MTIP_RS_FEC_STATUS_0_4 0x38e84 + +#define S_FEC_STATUS_4_14 14 +#define V_FEC_STATUS_4_14(x) ((x) << S_FEC_STATUS_4_14) +#define F_FEC_STATUS_4_14 V_FEC_STATUS_4_14(1U) + +#define S_FEC_STATUS_4_11 8 +#define M_FEC_STATUS_4_11 0xfU +#define V_FEC_STATUS_4_11(x) ((x) << S_FEC_STATUS_4_11) +#define G_FEC_STATUS_4_11(x) (((x) >> S_FEC_STATUS_4_11) & M_FEC_STATUS_4_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED4_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED4_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED4_0 V_RS_FEC_DEGRADE_SER_RECEIVED4_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED4_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED4_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED4_1 V_RS_FEC_DEGRADE_SER_RECEIVED4_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED4_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED4_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED4_2 V_RS_FEC_DEGRADE_SER_RECEIVED4_2(1U) + +#define S_FEC_STATUS_4_4 4 +#define V_FEC_STATUS_4_4(x) ((x) << S_FEC_STATUS_4_4) +#define F_FEC_STATUS_4_4 V_FEC_STATUS_4_4(1U) + +#define S_FEC_STATUS_4_3 3 +#define V_FEC_STATUS_4_3(x) ((x) << S_FEC_STATUS_4_3) +#define F_FEC_STATUS_4_3 V_FEC_STATUS_4_3(1U) + +#define S_FEC_STATUS_4_2 2 +#define V_FEC_STATUS_4_2(x) ((x) << S_FEC_STATUS_4_2) +#define F_FEC_STATUS_4_2 V_FEC_STATUS_4_2(1U) + +#define S_FEC_STATUS_4_1 1 +#define V_FEC_STATUS_4_1(x) ((x) << S_FEC_STATUS_4_1) +#define F_FEC_STATUS_4_1 V_FEC_STATUS_4_1(1U) + +#define S_FEC_STATUS_4_0 0 +#define V_FEC_STATUS_4_0(x) ((x) << S_FEC_STATUS_4_0) +#define F_FEC_STATUS_4_0 V_FEC_STATUS_4_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_4 0x38e88 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_4 0x38e8c +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_4 0x38e90 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_4 0x38e94 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_4 0x38e98 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_4 0x38e9c +#define A_MAC_MTIP_RS_FEC_CONTROL_0_5 0x38ea0 +#define A_MAC_MTIP_RS_FEC_STATUS_0_5 0x38ea4 + +#define S_FEC_STATUS_5_14 14 +#define V_FEC_STATUS_5_14(x) ((x) << S_FEC_STATUS_5_14) +#define F_FEC_STATUS_5_14 V_FEC_STATUS_5_14(1U) + +#define S_FEC_STATUS_5_11 8 +#define M_FEC_STATUS_5_11 0xfU +#define V_FEC_STATUS_5_11(x) ((x) << S_FEC_STATUS_5_11) +#define G_FEC_STATUS_5_11(x) (((x) >> S_FEC_STATUS_5_11) & M_FEC_STATUS_5_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED5_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED5_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED5_0 V_RS_FEC_DEGRADE_SER_RECEIVED5_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED5_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED5_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED5_1 V_RS_FEC_DEGRADE_SER_RECEIVED5_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED5_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED5_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED5_2 V_RS_FEC_DEGRADE_SER_RECEIVED5_2(1U) + +#define S_FEC_STATUS_5_4 4 +#define V_FEC_STATUS_5_4(x) ((x) << S_FEC_STATUS_5_4) +#define F_FEC_STATUS_5_4 V_FEC_STATUS_5_4(1U) + +#define S_FEC_STATUS_5_3 3 +#define V_FEC_STATUS_5_3(x) ((x) << S_FEC_STATUS_5_3) +#define F_FEC_STATUS_5_3 V_FEC_STATUS_5_3(1U) + +#define S_FEC_STATUS_5_2 2 +#define V_FEC_STATUS_5_2(x) ((x) << S_FEC_STATUS_5_2) +#define F_FEC_STATUS_5_2 V_FEC_STATUS_5_2(1U) + +#define S_FEC_STATUS_5_1 1 +#define V_FEC_STATUS_5_1(x) ((x) << S_FEC_STATUS_5_1) +#define F_FEC_STATUS_5_1 V_FEC_STATUS_5_1(1U) + +#define S_FEC_STATUS_5_0 0 +#define V_FEC_STATUS_5_0(x) ((x) << S_FEC_STATUS_5_0) +#define F_FEC_STATUS_5_0 V_FEC_STATUS_5_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_5 0x38ea8 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_5 0x38eac +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_5 0x38eb0 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_5 0x38eb4 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_5 0x38eb8 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_5 0x38ebc +#define A_MAC_MTIP_RS_FEC_CONTROL_0_6 0x38ec0 +#define A_MAC_MTIP_RS_FEC_STATUS_0_6 0x38ec4 + +#define S_FEC_STATUS_6_14 14 +#define V_FEC_STATUS_6_14(x) ((x) << S_FEC_STATUS_6_14) +#define F_FEC_STATUS_6_14 V_FEC_STATUS_6_14(1U) + +#define S_FEC_STATUS_6_11 8 +#define M_FEC_STATUS_6_11 0xfU +#define V_FEC_STATUS_6_11(x) ((x) << S_FEC_STATUS_6_11) +#define G_FEC_STATUS_6_11(x) (((x) >> S_FEC_STATUS_6_11) & M_FEC_STATUS_6_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED6_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED6_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED6_0 V_RS_FEC_DEGRADE_SER_RECEIVED6_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED6_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED6_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED6_1 V_RS_FEC_DEGRADE_SER_RECEIVED6_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED6_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED6_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED6_2 V_RS_FEC_DEGRADE_SER_RECEIVED6_2(1U) + +#define S_FEC_STATUS_6_4 4 +#define V_FEC_STATUS_6_4(x) ((x) << S_FEC_STATUS_6_4) +#define F_FEC_STATUS_6_4 V_FEC_STATUS_6_4(1U) + +#define S_FEC_STATUS_6_3 3 +#define V_FEC_STATUS_6_3(x) ((x) << S_FEC_STATUS_6_3) +#define F_FEC_STATUS_6_3 V_FEC_STATUS_6_3(1U) + +#define S_FEC_STATUS_6_2 2 +#define V_FEC_STATUS_6_2(x) ((x) << S_FEC_STATUS_6_2) +#define F_FEC_STATUS_6_2 V_FEC_STATUS_6_2(1U) + +#define S_FEC_STATUS_6_1 1 +#define V_FEC_STATUS_6_1(x) ((x) << S_FEC_STATUS_6_1) +#define F_FEC_STATUS_6_1 V_FEC_STATUS_6_1(1U) + +#define S_FEC_STATUS_6_0 0 +#define V_FEC_STATUS_6_0(x) ((x) << S_FEC_STATUS_6_0) +#define F_FEC_STATUS_6_0 V_FEC_STATUS_6_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_6 0x38ec8 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_6 0x38ecc +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_6 0x38ed0 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_6 0x38ed4 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_6 0x38ed8 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_6 0x38edc +#define A_MAC_MTIP_RS_FEC_CONTROL_0_7 0x38ee0 +#define A_MAC_MTIP_RS_FEC_STATUS_0_7 0x38ee4 + +#define S_FEC_STATUS_7_14 14 +#define V_FEC_STATUS_7_14(x) ((x) << S_FEC_STATUS_7_14) +#define F_FEC_STATUS_7_14 V_FEC_STATUS_7_14(1U) + +#define S_FEC_STATUS_7_11 8 +#define M_FEC_STATUS_7_11 0xfU +#define V_FEC_STATUS_7_11(x) ((x) << S_FEC_STATUS_7_11) +#define G_FEC_STATUS_7_11(x) (((x) >> S_FEC_STATUS_7_11) & M_FEC_STATUS_7_11) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED7_0 7 +#define V_RS_FEC_DEGRADE_SER_RECEIVED7_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_0) +#define F_RS_FEC_DEGRADE_SER_RECEIVED7_0 V_RS_FEC_DEGRADE_SER_RECEIVED7_0(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED7_1 6 +#define V_RS_FEC_DEGRADE_SER_RECEIVED7_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_1) +#define F_RS_FEC_DEGRADE_SER_RECEIVED7_1 V_RS_FEC_DEGRADE_SER_RECEIVED7_1(1U) + +#define S_RS_FEC_DEGRADE_SER_RECEIVED7_2 5 +#define V_RS_FEC_DEGRADE_SER_RECEIVED7_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_2) +#define F_RS_FEC_DEGRADE_SER_RECEIVED7_2 V_RS_FEC_DEGRADE_SER_RECEIVED7_2(1U) + +#define S_FEC_STATUS_7_4 4 +#define V_FEC_STATUS_7_4(x) ((x) << S_FEC_STATUS_7_4) +#define F_FEC_STATUS_7_4 V_FEC_STATUS_7_4(1U) + +#define S_FEC_STATUS_7_3 3 +#define V_FEC_STATUS_7_3(x) ((x) << S_FEC_STATUS_7_3) +#define F_FEC_STATUS_7_3 V_FEC_STATUS_7_3(1U) + +#define S_FEC_STATUS_7_2 2 +#define V_FEC_STATUS_7_2(x) ((x) << S_FEC_STATUS_7_2) +#define F_FEC_STATUS_7_2 V_FEC_STATUS_7_2(1U) + +#define S_FEC_STATUS_7_1 1 +#define V_FEC_STATUS_7_1(x) ((x) << S_FEC_STATUS_7_1) +#define F_FEC_STATUS_7_1 V_FEC_STATUS_7_1(1U) + +#define S_FEC_STATUS_7_0 0 +#define V_FEC_STATUS_7_0(x) ((x) << S_FEC_STATUS_7_0) +#define F_FEC_STATUS_7_0 V_FEC_STATUS_7_0(1U) + +#define A_MAC_MTIP_RS_FEC_CCW_LO_0_7 0x38ee8 +#define A_MAC_MTIP_RS_FEC_CCW_HI_0_7 0x38eec +#define A_MAC_MTIP_RS_FEC_NCCW_LO_0_7 0x38ef0 +#define A_MAC_MTIP_RS_FEC_NCCW_HI_0_7 0x38ef4 +#define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_7 0x38ef8 +#define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_7 0x38efc +#define A_MAC_MTIP_RS_FEC_HISER_CW 0x38f00 + +#define S_HISER_CW 0 +#define M_HISER_CW 0xffffU +#define V_HISER_CW(x) ((x) << S_HISER_CW) +#define G_HISER_CW(x) (((x) >> S_HISER_CW) & M_HISER_CW) + +#define A_MAC_MTIP_RS_FEC_HISER_THRESH 0x38f04 + +#define S_HISER_THRESH 0 +#define M_HISER_THRESH 0xffffU +#define V_HISER_THRESH(x) ((x) << S_HISER_THRESH) +#define G_HISER_THRESH(x) (((x) >> S_HISER_THRESH) & M_HISER_THRESH) + +#define A_MAC_MTIP_RS_FEC_HISER_TIME 0x38f08 + +#define S_HISER_TIME 0 +#define M_HISER_TIME 0xffffU +#define V_HISER_TIME(x) ((x) << S_HISER_TIME) +#define G_HISER_TIME(x) (((x) >> S_HISER_TIME) & M_HISER_TIME) + +#define A_MAC_MTIP_RS_DEGRADE_SET_CW 0x38f10 + +#define S_DEGRADE_SET_CW 0 +#define M_DEGRADE_SET_CW 0xffffU +#define V_DEGRADE_SET_CW(x) ((x) << S_DEGRADE_SET_CW) +#define G_DEGRADE_SET_CW(x) (((x) >> S_DEGRADE_SET_CW) & M_DEGRADE_SET_CW) + +#define A_MAC_MTIP_RS_DEGRADE_SET_CW_HI 0x38f14 + +#define S_DEGRADE_SET_CW_HI 0 +#define M_DEGRADE_SET_CW_HI 0xffffU +#define V_DEGRADE_SET_CW_HI(x) ((x) << S_DEGRADE_SET_CW_HI) +#define G_DEGRADE_SET_CW_HI(x) (((x) >> S_DEGRADE_SET_CW_HI) & M_DEGRADE_SET_CW_HI) + +#define A_MAC_MTIP_RS_DEGRADE_SET_THRESH 0x38f18 + +#define S_DEGRADE_SET_THRESH 0 +#define M_DEGRADE_SET_THRESH 0xffffU +#define V_DEGRADE_SET_THRESH(x) ((x) << S_DEGRADE_SET_THRESH) +#define G_DEGRADE_SET_THRESH(x) (((x) >> S_DEGRADE_SET_THRESH) & M_DEGRADE_SET_THRESH) + +#define A_MAC_MTIP_RS_DEGRADE_SET_THRESH_HI 0x38f1c + +#define S_DEGRADE_SET_THRESH_HI 0 +#define M_DEGRADE_SET_THRESH_HI 0xffffU +#define V_DEGRADE_SET_THRESH_HI(x) ((x) << S_DEGRADE_SET_THRESH_HI) +#define G_DEGRADE_SET_THRESH_HI(x) (((x) >> S_DEGRADE_SET_THRESH_HI) & M_DEGRADE_SET_THRESH_HI) + +#define A_MAC_MTIP_RS_DEGRADE_CLEAR 0x38f20 + +#define S_DEGRADE_SET_CLEAR 0 +#define M_DEGRADE_SET_CLEAR 0xffffU +#define V_DEGRADE_SET_CLEAR(x) ((x) << S_DEGRADE_SET_CLEAR) +#define G_DEGRADE_SET_CLEAR(x) (((x) >> S_DEGRADE_SET_CLEAR) & M_DEGRADE_SET_CLEAR) + +#define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_HI 0x38f24 + +#define S_DEGRADE_SET_CLEAR_HI 0 +#define M_DEGRADE_SET_CLEAR_HI 0xffffU +#define V_DEGRADE_SET_CLEAR_HI(x) ((x) << S_DEGRADE_SET_CLEAR_HI) +#define G_DEGRADE_SET_CLEAR_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_HI) & M_DEGRADE_SET_CLEAR_HI) + +#define A_MAC_MTIP_RS_DEGRADE_CLEAR_THRESH 0x38f28 + +#define S_DEGRADE_SET_CLEAR_THRESH 0 +#define M_DEGRADE_SET_CLEAR_THRESH 0xffffU +#define V_DEGRADE_SET_CLEAR_THRESH(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH) +#define G_DEGRADE_SET_CLEAR_THRESH(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH) & M_DEGRADE_SET_CLEAR_THRESH) + +#define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_THRESH_HI 0x38f2c + +#define S_DEGRADE_SET_CLEAR_THRESH_HI 0 +#define M_DEGRADE_SET_CLEAR_THRESH_HI 0xffffU +#define V_DEGRADE_SET_CLEAR_THRESH_HI(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH_HI) +#define G_DEGRADE_SET_CLEAR_THRESH_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH_HI) & M_DEGRADE_SET_CLEAR_THRESH_HI) + +#define A_MAC_MTIP_RS_VL0_0 0x38f80 +#define A_MAC_MTIP_RS_VL0_1 0x38f84 +#define A_MAC_MTIP_RS_VL1_0 0x38f88 +#define A_MAC_MTIP_RS_VL1_1 0x38f8c +#define A_MAC_MTIP_RS_VL2_0 0x38f90 +#define A_MAC_MTIP_RS_VL2_1 0x38f94 +#define A_MAC_MTIP_RS_VL3_0 0x38f98 +#define A_MAC_MTIP_RS_VL3_1 0x38f9c +#define A_MAC_MTIP_RS_VL4_0 0x38fa0 +#define A_MAC_MTIP_RS_VL4_1 0x38fa4 +#define A_MAC_MTIP_RS_VL5_0 0x38fa8 +#define A_MAC_MTIP_RS_VL5_1 0x38fac +#define A_MAC_MTIP_RS_VL6_0 0x38fb0 +#define A_MAC_MTIP_RS_VL6_1 0x38fb4 +#define A_MAC_MTIP_RS_VL7_0 0x38fb8 +#define A_MAC_MTIP_RS_VL7_1 0x38fbc +#define A_MAC_MTIP_RS_VL8_0 0x38fc0 +#define A_MAC_MTIP_RS_VL8_1 0x38fc4 +#define A_MAC_MTIP_RS_VL9_0 0x38fc8 +#define A_MAC_MTIP_RS_VL9_1 0x38fcc +#define A_MAC_MTIP_RS_VL10_0 0x38fd0 +#define A_MAC_MTIP_RS_VL10_1 0x38fd4 +#define A_MAC_MTIP_RS_VL11_0 0x38fd8 +#define A_MAC_MTIP_RS_VL11_1 0x38fdc +#define A_MAC_MTIP_RS_VL12_0 0x38fe0 +#define A_MAC_MTIP_RS_VL12_1 0x38fe4 +#define A_MAC_MTIP_RS_VL13_0 0x38fe8 +#define A_MAC_MTIP_RS_VL13_1 0x38fec +#define A_MAC_MTIP_RS_VL14_0 0x38ff0 +#define A_MAC_MTIP_RS_VL14_1 0x38ff4 +#define A_MAC_MTIP_RS_VL15_0 0x38ff8 +#define A_MAC_MTIP_RS_VL15_1 0x38ffc +#define A_MAC_MTIP_RS_FEC_SYMBLERR0_LO 0x39000 +#define A_MAC_MTIP_RS_FEC_SYMBLERR0_HI 0x39004 +#define A_MAC_MTIP_RS_FEC_SYMBLERR1_LO 0x39008 +#define A_MAC_MTIP_RS_FEC_SYMBLERR1_HI 0x3900c +#define A_MAC_MTIP_RS_FEC_SYMBLERR2_LO 0x39010 +#define A_MAC_MTIP_RS_FEC_SYMBLERR2_HI 0x39014 +#define A_MAC_MTIP_RS_FEC_SYMBLERR3_LO 0x39018 +#define A_MAC_MTIP_RS_FEC_SYMBLERR3_HI 0x3901c +#define A_MAC_MTIP_RS_FEC_SYMBLERR4_LO 0x39020 + +#define S_RS_FEC_SYMBLERR4_LO 0 +#define V_RS_FEC_SYMBLERR4_LO(x) ((x) << S_RS_FEC_SYMBLERR4_LO) +#define F_RS_FEC_SYMBLERR4_LO V_RS_FEC_SYMBLERR4_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR4_HI 0x39024 + +#define S_RS_FEC_SYMBLERR4_HI 0 +#define V_RS_FEC_SYMBLERR4_HI(x) ((x) << S_RS_FEC_SYMBLERR4_HI) +#define F_RS_FEC_SYMBLERR4_HI V_RS_FEC_SYMBLERR4_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR5_LO 0x39028 + +#define S_RS_FEC_SYMBLERR5_LO 0 +#define V_RS_FEC_SYMBLERR5_LO(x) ((x) << S_RS_FEC_SYMBLERR5_LO) +#define F_RS_FEC_SYMBLERR5_LO V_RS_FEC_SYMBLERR5_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR5_HI 0x3902c + +#define S_RS_FEC_SYMBLERR5_HI 0 +#define V_RS_FEC_SYMBLERR5_HI(x) ((x) << S_RS_FEC_SYMBLERR5_HI) +#define F_RS_FEC_SYMBLERR5_HI V_RS_FEC_SYMBLERR5_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR6_LO 0x39030 + +#define S_RS_FEC_SYMBLERR6_LO 0 +#define V_RS_FEC_SYMBLERR6_LO(x) ((x) << S_RS_FEC_SYMBLERR6_LO) +#define F_RS_FEC_SYMBLERR6_LO V_RS_FEC_SYMBLERR6_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR6_HI 0x39034 + +#define S_RS_FEC_SYMBLERR6_HI 0 +#define V_RS_FEC_SYMBLERR6_HI(x) ((x) << S_RS_FEC_SYMBLERR6_HI) +#define F_RS_FEC_SYMBLERR6_HI V_RS_FEC_SYMBLERR6_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR7_LO 0x39038 + +#define S_RS_FEC_SYMBLERR7_LO 0 +#define V_RS_FEC_SYMBLERR7_LO(x) ((x) << S_RS_FEC_SYMBLERR7_LO) +#define F_RS_FEC_SYMBLERR7_LO V_RS_FEC_SYMBLERR7_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR7_HI 0x3903c + +#define S_RS_FEC_SYMBLERR7_HI 0 +#define V_RS_FEC_SYMBLERR7_HI(x) ((x) << S_RS_FEC_SYMBLERR7_HI) +#define F_RS_FEC_SYMBLERR7_HI V_RS_FEC_SYMBLERR7_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR8_LO 0x39040 + +#define S_RS_FEC_SYMBLERR8_LO 0 +#define V_RS_FEC_SYMBLERR8_LO(x) ((x) << S_RS_FEC_SYMBLERR8_LO) +#define F_RS_FEC_SYMBLERR8_LO V_RS_FEC_SYMBLERR8_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR8_HI 0x39044 + +#define S_RS_FEC_SYMBLERR8_HI 0 +#define V_RS_FEC_SYMBLERR8_HI(x) ((x) << S_RS_FEC_SYMBLERR8_HI) +#define F_RS_FEC_SYMBLERR8_HI V_RS_FEC_SYMBLERR8_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR9_LO 0x39048 + +#define S_RS_FEC_SYMBLERR9_LO 0 +#define V_RS_FEC_SYMBLERR9_LO(x) ((x) << S_RS_FEC_SYMBLERR9_LO) +#define F_RS_FEC_SYMBLERR9_LO V_RS_FEC_SYMBLERR9_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR9_HI 0x3904c + +#define S_RS_FEC_SYMBLERR9_HI 0 +#define V_RS_FEC_SYMBLERR9_HI(x) ((x) << S_RS_FEC_SYMBLERR9_HI) +#define F_RS_FEC_SYMBLERR9_HI V_RS_FEC_SYMBLERR9_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR10_LO 0x39050 + +#define S_RS_FEC_SYMBLERR10_LO 0 +#define V_RS_FEC_SYMBLERR10_LO(x) ((x) << S_RS_FEC_SYMBLERR10_LO) +#define F_RS_FEC_SYMBLERR10_LO V_RS_FEC_SYMBLERR10_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR10_HI 0x39054 + +#define S_RS_FEC_SYMBLERR10_HI 0 +#define V_RS_FEC_SYMBLERR10_HI(x) ((x) << S_RS_FEC_SYMBLERR10_HI) +#define F_RS_FEC_SYMBLERR10_HI V_RS_FEC_SYMBLERR10_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR11_LO 0x39058 + +#define S_RS_FEC_SYMBLERR11_LO 0 +#define V_RS_FEC_SYMBLERR11_LO(x) ((x) << S_RS_FEC_SYMBLERR11_LO) +#define F_RS_FEC_SYMBLERR11_LO V_RS_FEC_SYMBLERR11_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR11_HI 0x3905c + +#define S_RS_FEC_SYMBLERR11_HI 0 +#define V_RS_FEC_SYMBLERR11_HI(x) ((x) << S_RS_FEC_SYMBLERR11_HI) +#define F_RS_FEC_SYMBLERR11_HI V_RS_FEC_SYMBLERR11_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR12_LO 0x39060 + +#define S_RS_FEC_SYMBLERR12_LO 0 +#define V_RS_FEC_SYMBLERR12_LO(x) ((x) << S_RS_FEC_SYMBLERR12_LO) +#define F_RS_FEC_SYMBLERR12_LO V_RS_FEC_SYMBLERR12_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR12_HI 0x39064 + +#define S_RS_FEC_SYMBLERR12_HI 0 +#define V_RS_FEC_SYMBLERR12_HI(x) ((x) << S_RS_FEC_SYMBLERR12_HI) +#define F_RS_FEC_SYMBLERR12_HI V_RS_FEC_SYMBLERR12_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR13_LO 0x39068 + +#define S_RS_FEC_SYMBLERR13_LO 0 +#define V_RS_FEC_SYMBLERR13_LO(x) ((x) << S_RS_FEC_SYMBLERR13_LO) +#define F_RS_FEC_SYMBLERR13_LO V_RS_FEC_SYMBLERR13_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR13_HI 0x3906c + +#define S_RS_FEC_SYMBLERR13_HI 0 +#define V_RS_FEC_SYMBLERR13_HI(x) ((x) << S_RS_FEC_SYMBLERR13_HI) +#define F_RS_FEC_SYMBLERR13_HI V_RS_FEC_SYMBLERR13_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR14_LO 0x39070 + +#define S_RS_FEC_SYMBLERR14_LO 0 +#define V_RS_FEC_SYMBLERR14_LO(x) ((x) << S_RS_FEC_SYMBLERR14_LO) +#define F_RS_FEC_SYMBLERR14_LO V_RS_FEC_SYMBLERR14_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR14_HI 0x39074 + +#define S_RS_FEC_SYMBLERR14_HI 0 +#define V_RS_FEC_SYMBLERR14_HI(x) ((x) << S_RS_FEC_SYMBLERR14_HI) +#define F_RS_FEC_SYMBLERR14_HI V_RS_FEC_SYMBLERR14_HI(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR15_LO 0x39078 + +#define S_RS_FEC_SYMBLERR15_LO 0 +#define V_RS_FEC_SYMBLERR15_LO(x) ((x) << S_RS_FEC_SYMBLERR15_LO) +#define F_RS_FEC_SYMBLERR15_LO V_RS_FEC_SYMBLERR15_LO(1U) + +#define A_MAC_MTIP_RS_FEC_SYMBLERR15_HI 0x3907c + +#define S_RS_FEC_SYMBLERR15_HI 0 +#define V_RS_FEC_SYMBLERR15_HI(x) ((x) << S_RS_FEC_SYMBLERR15_HI) +#define F_RS_FEC_SYMBLERR15_HI V_RS_FEC_SYMBLERR15_HI(1U) + +#define A_MAC_MTIP_RS_FEC_VENDOR_CONTROL 0x39080 +#define A_MAC_MTIP_RS_FEC_VENDOR_INFO_1 0x39084 + +#define S_VENDOR_INFO_1_AMPS_LOCK 0 +#define V_VENDOR_INFO_1_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_1_AMPS_LOCK) +#define F_VENDOR_INFO_1_AMPS_LOCK V_VENDOR_INFO_1_AMPS_LOCK(1U) + +#define A_MAC_MTIP_RS_FEC_VENDOR_INFO_2 0x39088 + +#define S_VENDOR_INFO_2_AMPS_LOCK 0 +#define M_VENDOR_INFO_2_AMPS_LOCK 0xffffU +#define V_VENDOR_INFO_2_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_2_AMPS_LOCK) +#define G_VENDOR_INFO_2_AMPS_LOCK(x) (((x) >> S_VENDOR_INFO_2_AMPS_LOCK) & M_VENDOR_INFO_2_AMPS_LOCK) + +#define A_MAC_MTIP_RS_FEC_VENDOR_REVISION 0x3908c +#define A_MAC_MTIP_RS_FEC_VENDOR_ALIGN_STATUS 0x39090 + +#define S_RS_FEC_VENDOR_ALIGN_STATUS 0 +#define M_RS_FEC_VENDOR_ALIGN_STATUS 0xffffU +#define V_RS_FEC_VENDOR_ALIGN_STATUS(x) ((x) << S_RS_FEC_VENDOR_ALIGN_STATUS) +#define G_RS_FEC_VENDOR_ALIGN_STATUS(x) (((x) >> S_RS_FEC_VENDOR_ALIGN_STATUS) & M_RS_FEC_VENDOR_ALIGN_STATUS) + +#define A_MAC_MTIP_FEC74_FEC_ABILITY_0 0x39100 + +#define S_FEC74_FEC_ABILITY_0_B1 1 +#define V_FEC74_FEC_ABILITY_0_B1(x) ((x) << S_FEC74_FEC_ABILITY_0_B1) +#define F_FEC74_FEC_ABILITY_0_B1 V_FEC74_FEC_ABILITY_0_B1(1U) + +#define S_FEC74_FEC_ABILITY_0_B0 0 +#define V_FEC74_FEC_ABILITY_0_B0(x) ((x) << S_FEC74_FEC_ABILITY_0_B0) +#define F_FEC74_FEC_ABILITY_0_B0 V_FEC74_FEC_ABILITY_0_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_0 0x39104 + +#define S_FEC_ENABLE_ERROR_INDICATION 1 +#define V_FEC_ENABLE_ERROR_INDICATION(x) ((x) << S_FEC_ENABLE_ERROR_INDICATION) +#define F_FEC_ENABLE_ERROR_INDICATION V_FEC_ENABLE_ERROR_INDICATION(1U) + +#define S_T7_FEC_ENABLE 0 +#define V_T7_FEC_ENABLE(x) ((x) << S_T7_FEC_ENABLE) +#define F_T7_FEC_ENABLE V_T7_FEC_ENABLE(1U) + +#define A_MAC_MTIP_FEC74_FEC_STATUS_0 0x39108 + +#define S_FEC_LOCKED_1 1 +#define V_FEC_LOCKED_1(x) ((x) << S_FEC_LOCKED_1) +#define F_FEC_LOCKED_1 V_FEC_LOCKED_1(1U) + +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_0 0x3910c + +#define S_VL0_CCW_LO 0 +#define M_VL0_CCW_LO 0xffffU +#define V_VL0_CCW_LO(x) ((x) << S_VL0_CCW_LO) +#define G_VL0_CCW_LO(x) (((x) >> S_VL0_CCW_LO) & M_VL0_CCW_LO) + +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_0 0x39110 + +#define S_VL0_NCCW_LO 0 +#define M_VL0_NCCW_LO 0xffffU +#define V_VL0_NCCW_LO(x) ((x) << S_VL0_NCCW_LO) +#define G_VL0_NCCW_LO(x) (((x) >> S_VL0_NCCW_LO) & M_VL0_NCCW_LO) + +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_0 0x39114 + +#define S_VL1_CCW_LO 0 +#define M_VL1_CCW_LO 0xffffU +#define V_VL1_CCW_LO(x) ((x) << S_VL1_CCW_LO) +#define G_VL1_CCW_LO(x) (((x) >> S_VL1_CCW_LO) & M_VL1_CCW_LO) + +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_0 0x39118 + +#define S_VL1_NCCW_LO 0 +#define M_VL1_NCCW_LO 0xffffU +#define V_VL1_NCCW_LO(x) ((x) << S_VL1_NCCW_LO) +#define G_VL1_NCCW_LO(x) (((x) >> S_VL1_NCCW_LO) & M_VL1_NCCW_LO) + +#define A_MAC_MTIP_FEC74_COUNTER_HI_0 0x3911c + +#define S_COUNTER_HI 0 +#define M_COUNTER_HI 0xffffU +#define V_COUNTER_HI(x) ((x) << S_COUNTER_HI) +#define G_COUNTER_HI(x) (((x) >> S_COUNTER_HI) & M_COUNTER_HI) + +#define A_MAC_MTIP_FEC74_FEC_ABILITY_1 0x39120 + +#define S_FEC74_FEC_ABILITY_1_B1 1 +#define V_FEC74_FEC_ABILITY_1_B1(x) ((x) << S_FEC74_FEC_ABILITY_1_B1) +#define F_FEC74_FEC_ABILITY_1_B1 V_FEC74_FEC_ABILITY_1_B1(1U) + +#define S_FEC74_FEC_ABILITY_1_B0 0 +#define V_FEC74_FEC_ABILITY_1_B0(x) ((x) << S_FEC74_FEC_ABILITY_1_B0) +#define F_FEC74_FEC_ABILITY_1_B0 V_FEC74_FEC_ABILITY_1_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_1 0x39124 +#define A_MAC_MTIP_FEC74_FEC_STATUS_1 0x39128 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_1 0x3912c +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_1 0x39130 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_1 0x39134 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_1 0x39138 +#define A_MAC_MTIP_FEC74_COUNTER_HI_1 0x3913c +#define A_MAC_MTIP_FEC74_FEC_ABILITY_2 0x39140 + +#define S_FEC74_FEC_ABILITY_2_B1 1 +#define V_FEC74_FEC_ABILITY_2_B1(x) ((x) << S_FEC74_FEC_ABILITY_2_B1) +#define F_FEC74_FEC_ABILITY_2_B1 V_FEC74_FEC_ABILITY_2_B1(1U) + +#define S_FEC74_FEC_ABILITY_2_B0 0 +#define V_FEC74_FEC_ABILITY_2_B0(x) ((x) << S_FEC74_FEC_ABILITY_2_B0) +#define F_FEC74_FEC_ABILITY_2_B0 V_FEC74_FEC_ABILITY_2_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_2 0x39144 +#define A_MAC_MTIP_FEC74_FEC_STATUS_2 0x39148 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_2 0x3914c +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_2 0x39150 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_2 0x39154 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_2 0x39158 +#define A_MAC_MTIP_FEC74_COUNTER_HI_2 0x3915c +#define A_MAC_MTIP_FEC74_FEC_ABILITY_3 0x39160 + +#define S_FEC74_FEC_ABILITY_3_B1 1 +#define V_FEC74_FEC_ABILITY_3_B1(x) ((x) << S_FEC74_FEC_ABILITY_3_B1) +#define F_FEC74_FEC_ABILITY_3_B1 V_FEC74_FEC_ABILITY_3_B1(1U) + +#define S_FEC74_FEC_ABILITY_3_B0 0 +#define V_FEC74_FEC_ABILITY_3_B0(x) ((x) << S_FEC74_FEC_ABILITY_3_B0) +#define F_FEC74_FEC_ABILITY_3_B0 V_FEC74_FEC_ABILITY_3_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_3 0x39164 +#define A_MAC_MTIP_FEC74_FEC_STATUS_3 0x39168 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_3 0x3916c +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_3 0x39170 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_3 0x39174 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_3 0x39178 +#define A_MAC_MTIP_FEC74_COUNTER_HI_3 0x3917c +#define A_MAC_MTIP_FEC74_FEC_ABILITY_4 0x39180 + +#define S_FEC74_FEC_ABILITY_4_B1 1 +#define V_FEC74_FEC_ABILITY_4_B1(x) ((x) << S_FEC74_FEC_ABILITY_4_B1) +#define F_FEC74_FEC_ABILITY_4_B1 V_FEC74_FEC_ABILITY_4_B1(1U) + +#define S_FEC74_FEC_ABILITY_4_B0 0 +#define V_FEC74_FEC_ABILITY_4_B0(x) ((x) << S_FEC74_FEC_ABILITY_4_B0) +#define F_FEC74_FEC_ABILITY_4_B0 V_FEC74_FEC_ABILITY_4_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_4 0x39184 +#define A_MAC_MTIP_FEC74_FEC_STATUS_4 0x39188 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_4 0x3918c +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_4 0x39190 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_4 0x39194 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_4 0x39198 +#define A_MAC_MTIP_FEC74_COUNTER_HI_4 0x3919c +#define A_MAC_MTIP_FEC74_FEC_ABILITY_5 0x391a0 + +#define S_FEC74_FEC_ABILITY_5_B1 1 +#define V_FEC74_FEC_ABILITY_5_B1(x) ((x) << S_FEC74_FEC_ABILITY_5_B1) +#define F_FEC74_FEC_ABILITY_5_B1 V_FEC74_FEC_ABILITY_5_B1(1U) + +#define S_FEC74_FEC_ABILITY_5_B0 0 +#define V_FEC74_FEC_ABILITY_5_B0(x) ((x) << S_FEC74_FEC_ABILITY_5_B0) +#define F_FEC74_FEC_ABILITY_5_B0 V_FEC74_FEC_ABILITY_5_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_5 0x391a4 +#define A_MAC_MTIP_FEC74_FEC_STATUS_5 0x391a8 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_5 0x391ac +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_5 0x391b0 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_5 0x391b4 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_5 0x391b8 +#define A_MAC_MTIP_FEC74_COUNTER_HI_5 0x391bc +#define A_MAC_MTIP_FEC74_FEC_ABILITY_6 0x391c0 + +#define S_FEC74_FEC_ABILITY_6_B1 1 +#define V_FEC74_FEC_ABILITY_6_B1(x) ((x) << S_FEC74_FEC_ABILITY_6_B1) +#define F_FEC74_FEC_ABILITY_6_B1 V_FEC74_FEC_ABILITY_6_B1(1U) + +#define S_FEC74_FEC_ABILITY_6_B0 0 +#define V_FEC74_FEC_ABILITY_6_B0(x) ((x) << S_FEC74_FEC_ABILITY_6_B0) +#define F_FEC74_FEC_ABILITY_6_B0 V_FEC74_FEC_ABILITY_6_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_6 0x391c4 +#define A_MAC_MTIP_FEC74_FEC_STATUS_6 0x391c8 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_6 0x391cc +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_6 0x391d0 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_6 0x391d4 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_6 0x391d8 +#define A_MAC_MTIP_FEC74_COUNTER_HI_6 0x391dc +#define A_MAC_MTIP_FEC74_FEC_ABILITY_7 0x391e0 + +#define S_FEC74_FEC_ABILITY_7_B1 1 +#define V_FEC74_FEC_ABILITY_7_B1(x) ((x) << S_FEC74_FEC_ABILITY_7_B1) +#define F_FEC74_FEC_ABILITY_7_B1 V_FEC74_FEC_ABILITY_7_B1(1U) + +#define S_FEC74_FEC_ABILITY_7_B0 0 +#define V_FEC74_FEC_ABILITY_7_B0(x) ((x) << S_FEC74_FEC_ABILITY_7_B0) +#define F_FEC74_FEC_ABILITY_7_B0 V_FEC74_FEC_ABILITY_7_B0(1U) + +#define A_MAC_MTIP_FEC74_FEC_CONTROL_7 0x391e4 +#define A_MAC_MTIP_FEC74_FEC_STATUS_7 0x391e8 +#define A_MAC_MTIP_FEC74_VL0_CCW_LO_7 0x391ec +#define A_MAC_MTIP_FEC74_VL0_NCCW_LO_7 0x391f0 +#define A_MAC_MTIP_FEC74_VL1_CCW_LO_7 0x391f4 +#define A_MAC_MTIP_FEC74_VL1_NCCW_LO_7 0x391f8 +#define A_MAC_MTIP_FEC74_COUNTER_HI_7 0x391fc +#define A_MAC_BEAN0_CTL 0x39200 +#define A_MAC_BEAN0_STATUS 0x39204 +#define A_MAC_BEAN0_ABILITY_0 0x39208 + +#define S_BEAN0_REM_FAULT 13 +#define V_BEAN0_REM_FAULT(x) ((x) << S_BEAN0_REM_FAULT) +#define F_BEAN0_REM_FAULT V_BEAN0_REM_FAULT(1U) + +#define A_MAC_BEAN0_ABILITY_1 0x3920c +#define A_MAC_BEAN0_ABILITY_2 0x39210 + +#define S_BEAN0_AB_2_15_12 12 +#define M_BEAN0_AB_2_15_12 0xfU +#define V_BEAN0_AB_2_15_12(x) ((x) << S_BEAN0_AB_2_15_12) +#define G_BEAN0_AB_2_15_12(x) (((x) >> S_BEAN0_AB_2_15_12) & M_BEAN0_AB_2_15_12) + +#define S_BEAN0_AB_2_11_0 0 +#define M_BEAN0_AB_2_11_0 0xfffU +#define V_BEAN0_AB_2_11_0(x) ((x) << S_BEAN0_AB_2_11_0) +#define G_BEAN0_AB_2_11_0(x) (((x) >> S_BEAN0_AB_2_11_0) & M_BEAN0_AB_2_11_0) + +#define A_MAC_BEAN0_REM_ABILITY_0 0x39214 + +#define S_BEAN0_ABL_REM_FAULT 13 +#define V_BEAN0_ABL_REM_FAULT(x) ((x) << S_BEAN0_ABL_REM_FAULT) +#define F_BEAN0_ABL_REM_FAULT V_BEAN0_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN0_REM_ABILITY_1 0x39218 +#define A_MAC_BEAN0_REM_ABILITY_2 0x3921c + +#define S_BEAN0_REM_AB_15_12 12 +#define M_BEAN0_REM_AB_15_12 0xfU +#define V_BEAN0_REM_AB_15_12(x) ((x) << S_BEAN0_REM_AB_15_12) +#define G_BEAN0_REM_AB_15_12(x) (((x) >> S_BEAN0_REM_AB_15_12) & M_BEAN0_REM_AB_15_12) + +#define S_BEAN0_REM_AB_11_0 0 +#define M_BEAN0_REM_AB_11_0 0xfffU +#define V_BEAN0_REM_AB_11_0(x) ((x) << S_BEAN0_REM_AB_11_0) +#define G_BEAN0_REM_AB_11_0(x) (((x) >> S_BEAN0_REM_AB_11_0) & M_BEAN0_REM_AB_11_0) + +#define A_MAC_BEAN0_MS_COUNT 0x39220 +#define A_MAC_BEAN0_XNP_0 0x39224 +#define A_MAC_BEAN0_XNP_1 0x39228 +#define A_MAC_BEAN0_XNP_2 0x3922c +#define A_MAC_LP_BEAN0_XNP_0 0x39230 +#define A_MAC_LP_BEAN0_XNP_1 0x39234 +#define A_MAC_LP_BEAN0_XNP_2 0x39238 +#define A_MAC_BEAN0_ETH_STATUS 0x3923c + +#define S_5GKR 15 +#define V_5GKR(x) ((x) << S_5GKR) +#define F_5GKR V_5GKR(1U) + +#define S_2P5GKX 14 +#define V_2P5GKX(x) ((x) << S_2P5GKX) +#define F_2P5GKX V_2P5GKX(1U) + +#define S_25G_KR 13 +#define V_25G_KR(x) ((x) << S_25G_KR) +#define F_25G_KR V_25G_KR(1U) + +#define S_25G_KR_S 12 +#define V_25G_KR_S(x) ((x) << S_25G_KR_S) +#define F_25G_KR_S V_25G_KR_S(1U) + +#define S_RS_FEC 7 +#define V_RS_FEC(x) ((x) << S_RS_FEC) +#define F_RS_FEC V_RS_FEC(1U) + +#define S_FC_FEC 4 +#define V_FC_FEC(x) ((x) << S_FC_FEC) +#define F_FC_FEC V_FC_FEC(1U) + +#define A_MAC_BEAN0_ETH_STATUS_2 0x39240 + +#define S_RS_FEC_NEGOTIATED 6 +#define V_RS_FEC_NEGOTIATED(x) ((x) << S_RS_FEC_NEGOTIATED) +#define F_RS_FEC_NEGOTIATED V_RS_FEC_NEGOTIATED(1U) + +#define S_400GKR4CR4 5 +#define V_400GKR4CR4(x) ((x) << S_400GKR4CR4) +#define F_400GKR4CR4 V_400GKR4CR4(1U) + +#define S_200GKR2CR2 4 +#define V_200GKR2CR2(x) ((x) << S_200GKR2CR2) +#define F_200GKR2CR2 V_200GKR2CR2(1U) + +#define S_100GKR1CR1 3 +#define V_100GKR1CR1(x) ((x) << S_100GKR1CR1) +#define F_100GKR1CR1 V_100GKR1CR1(1U) + +#define S_200GKR4CR4 2 +#define V_200GKR4CR4(x) ((x) << S_200GKR4CR4) +#define F_200GKR4CR4 V_200GKR4CR4(1U) + +#define S_100GKR2CR2 1 +#define V_100GKR2CR2(x) ((x) << S_100GKR2CR2) +#define F_100GKR2CR2 V_100GKR2CR2(1U) + +#define S_50GKRCR 0 +#define V_50GKRCR(x) ((x) << S_50GKRCR) +#define F_50GKRCR V_50GKRCR(1U) + +#define A_MAC_BEAN1_CTL 0x39300 +#define A_MAC_BEAN1_STATUS 0x39304 +#define A_MAC_BEAN1_ABILITY_0 0x39308 + +#define S_BEAN1_REM_FAULT 13 +#define V_BEAN1_REM_FAULT(x) ((x) << S_BEAN1_REM_FAULT) +#define F_BEAN1_REM_FAULT V_BEAN1_REM_FAULT(1U) + +#define A_MAC_BEAN1_ABILITY_1 0x3930c +#define A_MAC_BEAN1_ABILITY_2 0x39310 + +#define S_BEAN1_AB_2_15_12 12 +#define M_BEAN1_AB_2_15_12 0xfU +#define V_BEAN1_AB_2_15_12(x) ((x) << S_BEAN1_AB_2_15_12) +#define G_BEAN1_AB_2_15_12(x) (((x) >> S_BEAN1_AB_2_15_12) & M_BEAN1_AB_2_15_12) + +#define S_BEAN1_AB_2_11_0 0 +#define M_BEAN1_AB_2_11_0 0xfffU +#define V_BEAN1_AB_2_11_0(x) ((x) << S_BEAN1_AB_2_11_0) +#define G_BEAN1_AB_2_11_0(x) (((x) >> S_BEAN1_AB_2_11_0) & M_BEAN1_AB_2_11_0) + +#define A_MAC_BEAN1_REM_ABILITY_0 0x39314 + +#define S_BEAN1_ABL_REM_FAULT 13 +#define V_BEAN1_ABL_REM_FAULT(x) ((x) << S_BEAN1_ABL_REM_FAULT) +#define F_BEAN1_ABL_REM_FAULT V_BEAN1_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN1_REM_ABILITY_1 0x39318 +#define A_MAC_BEAN1_REM_ABILITY_2 0x3931c + +#define S_BEAN1_REM_AB_15_12 12 +#define M_BEAN1_REM_AB_15_12 0xfU +#define V_BEAN1_REM_AB_15_12(x) ((x) << S_BEAN1_REM_AB_15_12) +#define G_BEAN1_REM_AB_15_12(x) (((x) >> S_BEAN1_REM_AB_15_12) & M_BEAN1_REM_AB_15_12) + +#define S_BEAN1_REM_AB_11_0 0 +#define M_BEAN1_REM_AB_11_0 0xfffU +#define V_BEAN1_REM_AB_11_0(x) ((x) << S_BEAN1_REM_AB_11_0) +#define G_BEAN1_REM_AB_11_0(x) (((x) >> S_BEAN1_REM_AB_11_0) & M_BEAN1_REM_AB_11_0) + +#define A_MAC_BEAN1_MS_COUNT 0x39320 +#define A_MAC_BEAN1_XNP_0 0x39324 +#define A_MAC_BEAN1_XNP_1 0x39328 +#define A_MAC_BEAN1_XNP_2 0x3932c +#define A_MAC_LP_BEAN1_XNP_0 0x39330 +#define A_MAC_LP_BEAN1_XNP_1 0x39334 +#define A_MAC_LP_BEAN1_XNP_2 0x39338 +#define A_MAC_BEAN1_ETH_STATUS 0x3933c +#define A_MAC_BEAN1_ETH_STATUS_2 0x39340 +#define A_MAC_BEAN2_CTL 0x39400 +#define A_MAC_BEAN2_STATUS 0x39404 +#define A_MAC_BEAN2_ABILITY_0 0x39408 + +#define S_BEAN2_REM_FAULT 13 +#define V_BEAN2_REM_FAULT(x) ((x) << S_BEAN2_REM_FAULT) +#define F_BEAN2_REM_FAULT V_BEAN2_REM_FAULT(1U) + +#define A_MAC_BEAN2_ABILITY_1 0x3940c +#define A_MAC_BEAN2_ABILITY_2 0x39410 + +#define S_BEAN2_AB_2_15_12 12 +#define M_BEAN2_AB_2_15_12 0xfU +#define V_BEAN2_AB_2_15_12(x) ((x) << S_BEAN2_AB_2_15_12) +#define G_BEAN2_AB_2_15_12(x) (((x) >> S_BEAN2_AB_2_15_12) & M_BEAN2_AB_2_15_12) + +#define S_BEAN2_AB_2_11_0 0 +#define M_BEAN2_AB_2_11_0 0xfffU +#define V_BEAN2_AB_2_11_0(x) ((x) << S_BEAN2_AB_2_11_0) +#define G_BEAN2_AB_2_11_0(x) (((x) >> S_BEAN2_AB_2_11_0) & M_BEAN2_AB_2_11_0) + +#define A_MAC_BEAN2_REM_ABILITY_0 0x39414 + +#define S_BEAN2_ABL_REM_FAULT 13 +#define V_BEAN2_ABL_REM_FAULT(x) ((x) << S_BEAN2_ABL_REM_FAULT) +#define F_BEAN2_ABL_REM_FAULT V_BEAN2_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN2_REM_ABILITY_1 0x39418 +#define A_MAC_BEAN2_REM_ABILITY_2 0x3941c + +#define S_BEAN2_REM_AB_15_12 12 +#define M_BEAN2_REM_AB_15_12 0xfU +#define V_BEAN2_REM_AB_15_12(x) ((x) << S_BEAN2_REM_AB_15_12) +#define G_BEAN2_REM_AB_15_12(x) (((x) >> S_BEAN2_REM_AB_15_12) & M_BEAN2_REM_AB_15_12) + +#define S_BEAN2_REM_AB_11_0 0 +#define M_BEAN2_REM_AB_11_0 0xfffU +#define V_BEAN2_REM_AB_11_0(x) ((x) << S_BEAN2_REM_AB_11_0) +#define G_BEAN2_REM_AB_11_0(x) (((x) >> S_BEAN2_REM_AB_11_0) & M_BEAN2_REM_AB_11_0) + +#define A_MAC_BEAN2_MS_COUNT 0x39420 +#define A_MAC_BEAN2_XNP_0 0x39424 +#define A_MAC_BEAN2_XNP_1 0x39428 +#define A_MAC_BEAN2_XNP_2 0x3942c +#define A_MAC_LP_BEAN2_XNP_0 0x39430 +#define A_MAC_LP_BEAN2_XNP_1 0x39434 +#define A_MAC_LP_BEAN2_XNP_2 0x39438 +#define A_MAC_BEAN2_ETH_STATUS 0x3943c +#define A_MAC_BEAN2_ETH_STATUS_2 0x39440 +#define A_MAC_BEAN3_CTL 0x39500 +#define A_MAC_BEAN3_STATUS 0x39504 +#define A_MAC_BEAN3_ABILITY_0 0x39508 + +#define S_BEAN3_REM_FAULT 13 +#define V_BEAN3_REM_FAULT(x) ((x) << S_BEAN3_REM_FAULT) +#define F_BEAN3_REM_FAULT V_BEAN3_REM_FAULT(1U) + +#define A_MAC_BEAN3_ABILITY_1 0x3950c +#define A_MAC_BEAN3_ABILITY_2 0x39510 + +#define S_BEAN3_AB_2_15_12 12 +#define M_BEAN3_AB_2_15_12 0xfU +#define V_BEAN3_AB_2_15_12(x) ((x) << S_BEAN3_AB_2_15_12) +#define G_BEAN3_AB_2_15_12(x) (((x) >> S_BEAN3_AB_2_15_12) & M_BEAN3_AB_2_15_12) + +#define S_BEAN3_AB_2_11_0 0 +#define M_BEAN3_AB_2_11_0 0xfffU +#define V_BEAN3_AB_2_11_0(x) ((x) << S_BEAN3_AB_2_11_0) +#define G_BEAN3_AB_2_11_0(x) (((x) >> S_BEAN3_AB_2_11_0) & M_BEAN3_AB_2_11_0) + +#define A_MAC_BEAN3_REM_ABILITY_0 0x39514 + +#define S_BEAN3_ABL_REM_FAULT 13 +#define V_BEAN3_ABL_REM_FAULT(x) ((x) << S_BEAN3_ABL_REM_FAULT) +#define F_BEAN3_ABL_REM_FAULT V_BEAN3_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN3_REM_ABILITY_1 0x39518 +#define A_MAC_BEAN3_REM_ABILITY_2 0x3951c + +#define S_BEAN3_REM_AB_15_12 12 +#define M_BEAN3_REM_AB_15_12 0xfU +#define V_BEAN3_REM_AB_15_12(x) ((x) << S_BEAN3_REM_AB_15_12) +#define G_BEAN3_REM_AB_15_12(x) (((x) >> S_BEAN3_REM_AB_15_12) & M_BEAN3_REM_AB_15_12) + +#define S_BEAN3_REM_AB_11_0 0 +#define M_BEAN3_REM_AB_11_0 0xfffU +#define V_BEAN3_REM_AB_11_0(x) ((x) << S_BEAN3_REM_AB_11_0) +#define G_BEAN3_REM_AB_11_0(x) (((x) >> S_BEAN3_REM_AB_11_0) & M_BEAN3_REM_AB_11_0) + +#define A_MAC_BEAN3_MS_COUNT 0x39520 +#define A_MAC_BEAN3_XNP_0 0x39524 +#define A_MAC_BEAN3_XNP_1 0x39528 +#define A_MAC_BEAN3_XNP_2 0x3952c +#define A_MAC_LP_BEAN3_XNP_0 0x39530 +#define A_MAC_LP_BEAN3_XNP_1 0x39534 +#define A_MAC_LP_BEAN3_XNP_2 0x39538 +#define A_MAC_BEAN3_ETH_STATUS 0x3953c +#define A_MAC_BEAN3_ETH_STATUS_2 0x39540 +#define A_MAC_BEAN4_CTL 0x39600 +#define A_MAC_BEAN4_STATUS 0x39604 +#define A_MAC_BEAN4_ABILITY_0 0x39608 + +#define S_BEAN4_REM_FAULT 13 +#define V_BEAN4_REM_FAULT(x) ((x) << S_BEAN4_REM_FAULT) +#define F_BEAN4_REM_FAULT V_BEAN4_REM_FAULT(1U) + +#define A_MAC_BEAN4_ABILITY_1 0x3960c +#define A_MAC_BEAN4_ABILITY_2 0x39610 + +#define S_BEAN4_AB_2_15_12 12 +#define M_BEAN4_AB_2_15_12 0xfU +#define V_BEAN4_AB_2_15_12(x) ((x) << S_BEAN4_AB_2_15_12) +#define G_BEAN4_AB_2_15_12(x) (((x) >> S_BEAN4_AB_2_15_12) & M_BEAN4_AB_2_15_12) + +#define S_BEAN4_AB_2_11_0 0 +#define M_BEAN4_AB_2_11_0 0xfffU +#define V_BEAN4_AB_2_11_0(x) ((x) << S_BEAN4_AB_2_11_0) +#define G_BEAN4_AB_2_11_0(x) (((x) >> S_BEAN4_AB_2_11_0) & M_BEAN4_AB_2_11_0) + +#define A_MAC_BEAN4_REM_ABILITY_0 0x39614 + +#define S_BEAN4_ABL_REM_FAULT 13 +#define V_BEAN4_ABL_REM_FAULT(x) ((x) << S_BEAN4_ABL_REM_FAULT) +#define F_BEAN4_ABL_REM_FAULT V_BEAN4_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN4_REM_ABILITY_1 0x39618 +#define A_MAC_BEAN4_REM_ABILITY_2 0x3961c + +#define S_BEAN4_REM_AB_15_12 12 +#define M_BEAN4_REM_AB_15_12 0xfU +#define V_BEAN4_REM_AB_15_12(x) ((x) << S_BEAN4_REM_AB_15_12) +#define G_BEAN4_REM_AB_15_12(x) (((x) >> S_BEAN4_REM_AB_15_12) & M_BEAN4_REM_AB_15_12) + +#define S_BEAN4_REM_AB_11_0 0 +#define M_BEAN4_REM_AB_11_0 0xfffU +#define V_BEAN4_REM_AB_11_0(x) ((x) << S_BEAN4_REM_AB_11_0) +#define G_BEAN4_REM_AB_11_0(x) (((x) >> S_BEAN4_REM_AB_11_0) & M_BEAN4_REM_AB_11_0) + +#define A_MAC_BEAN4_MS_COUNT 0x39620 +#define A_MAC_BEAN4_XNP_0 0x39624 +#define A_MAC_BEAN4_XNP_1 0x39628 +#define A_MAC_BEAN4_XNP_2 0x3962c +#define A_MAC_LP_BEAN4_XNP_0 0x39630 +#define A_MAC_LP_BEAN4_XNP_1 0x39634 +#define A_MAC_LP_BEAN4_XNP_2 0x39638 +#define A_MAC_BEAN4_ETH_STATUS 0x3963c +#define A_MAC_BEAN4_ETH_STATUS_2 0x39640 +#define A_MAC_BEAN5_CTL 0x39700 +#define A_MAC_BEAN5_STATUS 0x39704 +#define A_MAC_BEAN5_ABILITY_0 0x39708 + +#define S_BEAN5_REM_FAULT 13 +#define V_BEAN5_REM_FAULT(x) ((x) << S_BEAN5_REM_FAULT) +#define F_BEAN5_REM_FAULT V_BEAN5_REM_FAULT(1U) + +#define A_MAC_BEAN5_ABILITY_1 0x3970c +#define A_MAC_BEAN5_ABILITY_2 0x39710 + +#define S_BEAN5_AB_2_15_12 12 +#define M_BEAN5_AB_2_15_12 0xfU +#define V_BEAN5_AB_2_15_12(x) ((x) << S_BEAN5_AB_2_15_12) +#define G_BEAN5_AB_2_15_12(x) (((x) >> S_BEAN5_AB_2_15_12) & M_BEAN5_AB_2_15_12) + +#define S_BEAN5_AB_2_11_0 0 +#define M_BEAN5_AB_2_11_0 0xfffU +#define V_BEAN5_AB_2_11_0(x) ((x) << S_BEAN5_AB_2_11_0) +#define G_BEAN5_AB_2_11_0(x) (((x) >> S_BEAN5_AB_2_11_0) & M_BEAN5_AB_2_11_0) + +#define A_MAC_BEAN5_REM_ABILITY_0 0x39714 + +#define S_BEAN5_ABL_REM_FAULT 13 +#define V_BEAN5_ABL_REM_FAULT(x) ((x) << S_BEAN5_ABL_REM_FAULT) +#define F_BEAN5_ABL_REM_FAULT V_BEAN5_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN5_REM_ABILITY_1 0x39718 +#define A_MAC_BEAN5_REM_ABILITY_2 0x3971c + +#define S_BEAN5_REM_AB_15_12 12 +#define M_BEAN5_REM_AB_15_12 0xfU +#define V_BEAN5_REM_AB_15_12(x) ((x) << S_BEAN5_REM_AB_15_12) +#define G_BEAN5_REM_AB_15_12(x) (((x) >> S_BEAN5_REM_AB_15_12) & M_BEAN5_REM_AB_15_12) + +#define S_BEAN5_REM_AB_11_0 0 +#define M_BEAN5_REM_AB_11_0 0xfffU +#define V_BEAN5_REM_AB_11_0(x) ((x) << S_BEAN5_REM_AB_11_0) +#define G_BEAN5_REM_AB_11_0(x) (((x) >> S_BEAN5_REM_AB_11_0) & M_BEAN5_REM_AB_11_0) + +#define A_MAC_BEAN5_MS_COUNT 0x39720 +#define A_MAC_BEAN5_XNP_0 0x39724 +#define A_MAC_BEAN5_XNP_1 0x39728 +#define A_MAC_BEAN5_XNP_2 0x3972c +#define A_MAC_LP_BEAN5_XNP_0 0x39730 +#define A_MAC_LP_BEAN5_XNP_1 0x39734 +#define A_MAC_LP_BEAN5_XNP_2 0x39738 +#define A_MAC_BEAN5_ETH_STATUS 0x3973c +#define A_MAC_BEAN5_ETH_STATUS_2 0x39740 +#define A_MAC_BEAN6_CTL 0x39800 +#define A_MAC_BEAN6_STATUS 0x39804 +#define A_MAC_BEAN6_ABILITY_0 0x39808 + +#define S_BEAN6_REM_FAULT 13 +#define V_BEAN6_REM_FAULT(x) ((x) << S_BEAN6_REM_FAULT) +#define F_BEAN6_REM_FAULT V_BEAN6_REM_FAULT(1U) + +#define A_MAC_BEAN6_ABILITY_1 0x3980c +#define A_MAC_BEAN6_ABILITY_2 0x39810 + +#define S_BEAN6_AB_2_15_12 12 +#define M_BEAN6_AB_2_15_12 0xfU +#define V_BEAN6_AB_2_15_12(x) ((x) << S_BEAN6_AB_2_15_12) +#define G_BEAN6_AB_2_15_12(x) (((x) >> S_BEAN6_AB_2_15_12) & M_BEAN6_AB_2_15_12) + +#define S_BEAN6_AB_2_11_0 0 +#define M_BEAN6_AB_2_11_0 0xfffU +#define V_BEAN6_AB_2_11_0(x) ((x) << S_BEAN6_AB_2_11_0) +#define G_BEAN6_AB_2_11_0(x) (((x) >> S_BEAN6_AB_2_11_0) & M_BEAN6_AB_2_11_0) + +#define A_MAC_BEAN6_REM_ABILITY_0 0x39814 + +#define S_BEAN6_ABL_REM_FAULT 13 +#define V_BEAN6_ABL_REM_FAULT(x) ((x) << S_BEAN6_ABL_REM_FAULT) +#define F_BEAN6_ABL_REM_FAULT V_BEAN6_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN6_REM_ABILITY_1 0x39818 +#define A_MAC_BEAN6_REM_ABILITY_2 0x3981c + +#define S_BEAN6_REM_AB_15_12 12 +#define M_BEAN6_REM_AB_15_12 0xfU +#define V_BEAN6_REM_AB_15_12(x) ((x) << S_BEAN6_REM_AB_15_12) +#define G_BEAN6_REM_AB_15_12(x) (((x) >> S_BEAN6_REM_AB_15_12) & M_BEAN6_REM_AB_15_12) + +#define S_BEAN6_REM_AB_11_0 0 +#define M_BEAN6_REM_AB_11_0 0xfffU +#define V_BEAN6_REM_AB_11_0(x) ((x) << S_BEAN6_REM_AB_11_0) +#define G_BEAN6_REM_AB_11_0(x) (((x) >> S_BEAN6_REM_AB_11_0) & M_BEAN6_REM_AB_11_0) + +#define A_MAC_BEAN6_MS_COUNT 0x39820 +#define A_MAC_BEAN6_XNP_0 0x39824 +#define A_MAC_BEAN6_XNP_1 0x39828 +#define A_MAC_BEAN6_XNP_2 0x3982c +#define A_MAC_LP_BEAN6_XNP_0 0x39830 +#define A_MAC_LP_BEAN6_XNP_1 0x39834 +#define A_MAC_LP_BEAN6_XNP_2 0x39838 +#define A_MAC_BEAN6_ETH_STATUS 0x3983c +#define A_MAC_BEAN6_ETH_STATUS_2 0x39840 +#define A_MAC_BEAN7_CTL 0x39900 +#define A_MAC_BEAN7_STATUS 0x39904 +#define A_MAC_BEAN7_ABILITY_0 0x39908 + +#define S_BEAN7_REM_FAULT 13 +#define V_BEAN7_REM_FAULT(x) ((x) << S_BEAN7_REM_FAULT) +#define F_BEAN7_REM_FAULT V_BEAN7_REM_FAULT(1U) + +#define A_MAC_BEAN7_ABILITY_1 0x3990c +#define A_MAC_BEAN7_ABILITY_2 0x39910 + +#define S_BEAN7_AB_2_15_12 12 +#define M_BEAN7_AB_2_15_12 0xfU +#define V_BEAN7_AB_2_15_12(x) ((x) << S_BEAN7_AB_2_15_12) +#define G_BEAN7_AB_2_15_12(x) (((x) >> S_BEAN7_AB_2_15_12) & M_BEAN7_AB_2_15_12) + +#define S_BEAN7_AB_2_11_0 0 +#define M_BEAN7_AB_2_11_0 0xfffU +#define V_BEAN7_AB_2_11_0(x) ((x) << S_BEAN7_AB_2_11_0) +#define G_BEAN7_AB_2_11_0(x) (((x) >> S_BEAN7_AB_2_11_0) & M_BEAN7_AB_2_11_0) + +#define A_MAC_BEAN7_REM_ABILITY_0 0x39914 + +#define S_BEAN7_ABL_REM_FAULT 13 +#define V_BEAN7_ABL_REM_FAULT(x) ((x) << S_BEAN7_ABL_REM_FAULT) +#define F_BEAN7_ABL_REM_FAULT V_BEAN7_ABL_REM_FAULT(1U) + +#define A_MAC_BEAN7_REM_ABILITY_1 0x39918 +#define A_MAC_BEAN7_REM_ABILITY_2 0x3991c + +#define S_BEAN7_REM_AB_15_12 12 +#define M_BEAN7_REM_AB_15_12 0xfU +#define V_BEAN7_REM_AB_15_12(x) ((x) << S_BEAN7_REM_AB_15_12) +#define G_BEAN7_REM_AB_15_12(x) (((x) >> S_BEAN7_REM_AB_15_12) & M_BEAN7_REM_AB_15_12) + +#define S_BEAN7_REM_AB_11_0 0 +#define M_BEAN7_REM_AB_11_0 0xfffU +#define V_BEAN7_REM_AB_11_0(x) ((x) << S_BEAN7_REM_AB_11_0) +#define G_BEAN7_REM_AB_11_0(x) (((x) >> S_BEAN7_REM_AB_11_0) & M_BEAN7_REM_AB_11_0) + +#define A_MAC_BEAN7_MS_COUNT 0x39920 +#define A_MAC_BEAN7_XNP_0 0x39924 +#define A_MAC_BEAN7_XNP_1 0x39928 +#define A_MAC_BEAN7_XNP_2 0x3992c +#define A_MAC_LP_BEAN7_XNP_0 0x39930 +#define A_MAC_LP_BEAN7_XNP_1 0x39934 +#define A_MAC_LP_BEAN7_XNP_2 0x39938 +#define A_MAC_BEAN7_ETH_STATUS 0x3993c +#define A_MAC_BEAN7_ETH_STATUS_2 0x39940 +#define A_MAC_MTIP_ETHERSTATS_DATA_HI 0x39a00 +#define A_MAC_MTIP_ETHERSTATS_STATN_STATUS 0x39a04 +#define A_MAC_MTIP_ETHERSTATS_STATN_CONFIG 0x39a08 + +#define S_T7_RESET 31 +#define V_T7_RESET(x) ((x) << S_T7_RESET) +#define F_T7_RESET V_T7_RESET(1U) + +#define A_MAC_MTIP_ETHERSTATS_STATN_CONTROL 0x39a0c + +#define S_CMD_CLEAR_TX 31 +#define V_CMD_CLEAR_TX(x) ((x) << S_CMD_CLEAR_TX) +#define F_CMD_CLEAR_TX V_CMD_CLEAR_TX(1U) + +#define S_CMD_CLEAR_RX 30 +#define V_CMD_CLEAR_RX(x) ((x) << S_CMD_CLEAR_RX) +#define F_CMD_CLEAR_RX V_CMD_CLEAR_RX(1U) + +#define S_CLEAR_PRE 29 +#define V_CLEAR_PRE(x) ((x) << S_CLEAR_PRE) +#define F_CLEAR_PRE V_CLEAR_PRE(1U) + +#define S_CMD_CAPTURE_TX 28 +#define V_CMD_CAPTURE_TX(x) ((x) << S_CMD_CAPTURE_TX) +#define F_CMD_CAPTURE_TX V_CMD_CAPTURE_TX(1U) + +#define S_CMD_CAPTURE_RX 27 +#define V_CMD_CAPTURE_RX(x) ((x) << S_CMD_CAPTURE_RX) +#define F_CMD_CAPTURE_RX V_CMD_CAPTURE_RX(1U) + +#define S_PORTMASK 0 +#define M_PORTMASK 0xffU +#define V_PORTMASK(x) ((x) << S_PORTMASK) +#define G_PORTMASK(x) (((x) >> S_PORTMASK) & M_PORTMASK) + +#define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_LO 0x39a10 + +#define S_STATN_CLEARVALUE_LO 0 +#define V_STATN_CLEARVALUE_LO(x) ((x) << S_STATN_CLEARVALUE_LO) +#define F_STATN_CLEARVALUE_LO V_STATN_CLEARVALUE_LO(1U) + +#define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_HI 0x39a14 + +#define S_STATN_CLEARVALUE_HI 0 +#define V_STATN_CLEARVALUE_HI(x) ((x) << S_STATN_CLEARVALUE_HI) +#define F_STATN_CLEARVALUE_HI V_STATN_CLEARVALUE_HI(1U) + +#define A_MAC_MTIP_ETHERSTATS_DATA_HI_1 0x39a1c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_0 0x39a20 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_1 0x39a24 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_2 0x39a28 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_3 0x39a2c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_4 0x39a30 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_5 0x39a34 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_6 0x39a38 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_7 0x39a3c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_8 0x39a40 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_9 0x39a44 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_10 0x39a48 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_11 0x39a4c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_12 0x39a50 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_13 0x39a54 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_14 0x39a58 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_15 0x39a5c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_16 0x39a60 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_17 0x39a64 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_18 0x39a68 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_19 0x39a6c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_20 0x39a70 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_21 0x39a74 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_22 0x39a78 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_23 0x39a7c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_24 0x39a80 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_25 0x39a84 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_26 0x39a88 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_27 0x39a8c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_28 0x39a90 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_29 0x39a94 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_30 0x39a98 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_31 0x39a9c +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_32 0x39aa0 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_33 0x39aa4 +#define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_34 0x39aa8 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS 0x39b00 +#define A_MAC_MTIP_ETHERSTATS0_OCTETSRECEIVEDOK 0x39b04 +#define A_MAC_MTIP_ETHERSTATS0_AALIGNMENTERRORS 0x39b08 +#define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESRECEIVED 0x39b0c +#define A_MAC_MTIP_ETHERSTATS0_AFRAMETOOLONGERRORS 0x39b10 +#define A_MAC_MTIP_ETHERSTATS0_AINRANGELENGTHERRORS 0x39b14 +#define A_MAC_MTIP_ETHERSTATS0_AFRAMESRECEIVEDOK 0x39b18 +#define A_MAC_MTIP_ETHERSTATS0_AFRAMECHECKSEQUENCEERRORS 0x39b1c +#define A_MAC_MTIP_ETHERSTATS0_VLANRECEIVEDOK 0x39b20 +#define A_MAC_MTIP_ETHERSTATS0_IFINERRORS_RX 0x39b24 +#define A_MAC_MTIP_ETHERSTATS0_IFINUCASTPKTS_RX 0x39b28 +#define A_MAC_MTIP_ETHERSTATS0_IFINMULTICASTPKTS_RX 0x39b2c +#define A_MAC_MTIP_ETHERSTATS0_IFINBROADCASTPKTS_RX 0x39b30 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSDROPEVENTS_RX 0x39b34 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_RX 0x39b38 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSUNDERSIZEPKTS_RX 0x39b3c +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_RX 0x39b40 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_RX 0x39b44 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_RX 0x39b48 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_RX 0x39b4c +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39b50 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39b54 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39b58 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOVERSIZEPKTS_RX 0x39b5c +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSJABBERS_RX 0x39b60 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSFRAGMENTS_RX 0x39b64 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39b68 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39b6c +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39b70 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39b74 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39b78 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39b7c +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39b80 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39b84 +#define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESRECEIVED_RX 0x39b88 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS 0x39b8c +#define A_MAC_MTIP_ETHERSTATS1_OCTETSRECEIVEDOK 0x39b90 +#define A_MAC_MTIP_ETHERSTATS1_AALIGNMENTERRORS 0x39b94 +#define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESRECEIVED 0x39b98 +#define A_MAC_MTIP_ETHERSTATS1_AFRAMETOOLONGERRORS 0x39b9c +#define A_MAC_MTIP_ETHERSTATS1_AINRANGELENGTHERRORS 0x39ba0 +#define A_MAC_MTIP_ETHERSTATS1_AFRAMESRECEIVEDOK 0x39ba4 +#define A_MAC_MTIP_ETHERSTATS1_AFRAMECHECKSEQUENCEERRORS 0x39ba8 +#define A_MAC_MTIP_ETHERSTATS1_VLANRECEIVEDOK 0x39bac +#define A_MAC_MTIP_ETHERSTATS1_IFINERRORS_RX 0x39bb0 +#define A_MAC_MTIP_ETHERSTATS1_IFINUCASTPKTS_RX 0x39bb4 +#define A_MAC_MTIP_ETHERSTATS1_IFINMULTICASTPKTS_RX 0x39bb8 +#define A_MAC_MTIP_ETHERSTATS1_IFINBROADCASTPKTS_RX 0x39bbc +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSDROPEVENTS_RX 0x39bc0 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_RX 0x39bc4 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSUNDERSIZEPKTS_RX 0x39bc8 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_RX 0x39bcc +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_RX 0x39bd0 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_RX 0x39bd4 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_RX 0x39bd8 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39bdc +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39be0 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39be4 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOVERSIZEPKTS_RX 0x39be8 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSJABBERS_RX 0x39bec +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSFRAGMENTS_RX 0x39bf0 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39bf4 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39bf8 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39bfc +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c00 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c04 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c08 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c0c +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c10 +#define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESRECEIVED_RX 0x39c14 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS 0x39c18 +#define A_MAC_MTIP_ETHERSTATS2_OCTETSRECEIVEDOK 0x39c1c +#define A_MAC_MTIP_ETHERSTATS2_AALIGNMENTERRORS 0x39c20 +#define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESRECEIVED 0x39c24 +#define A_MAC_MTIP_ETHERSTATS2_AFRAMETOOLONGERRORS 0x39c28 +#define A_MAC_MTIP_ETHERSTATS2_AINRANGELENGTHERRORS 0x39c2c +#define A_MAC_MTIP_ETHERSTATS2_AFRAMESRECEIVEDOK 0x39c30 +#define A_MAC_MTIP_ETHERSTATS2_AFRAMECHECKSEQUENCEERRORS 0x39c34 +#define A_MAC_MTIP_ETHERSTATS2_VLANRECEIVEDOK 0x39c38 +#define A_MAC_MTIP_ETHERSTATS2_IFINERRORS_RX 0x39c3c +#define A_MAC_MTIP_ETHERSTATS2_IFINUCASTPKTS_RX 0x39c40 +#define A_MAC_MTIP_ETHERSTATS2_IFINMULTICASTPKTS_RX 0x39c44 +#define A_MAC_MTIP_ETHERSTATS2_IFINBROADCASTPKTS_RX 0x39c48 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSDROPEVENTS_RX 0x39c4c +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_RX 0x39c50 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSUNDERSIZEPKTS_RX 0x39c54 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_RX 0x39c58 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_RX 0x39c5c +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_RX 0x39c60 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_RX 0x39c64 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39c68 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39c6c +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39c70 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOVERSIZEPKTS_RX 0x39c74 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSJABBERS_RX 0x39c78 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSFRAGMENTS_RX 0x39c7c +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39c80 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39c84 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39c88 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c8c +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c90 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c94 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c98 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c9c +#define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESRECEIVED_RX 0x39ca0 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS 0x39ca4 +#define A_MAC_MTIP_ETHERSTATS3_OCTETSRECEIVEDOK 0x39ca8 +#define A_MAC_MTIP_ETHERSTATS3_AALIGNMENTERRORS 0x39cac +#define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESRECEIVED 0x39cb0 +#define A_MAC_MTIP_ETHERSTATS3_AFRAMETOOLONGERRORS 0x39cb4 +#define A_MAC_MTIP_ETHERSTATS3_AINRANGELENGTHERRORS 0x39cb8 +#define A_MAC_MTIP_ETHERSTATS3_AFRAMESRECEIVEDOK 0x39cbc +#define A_MAC_MTIP_ETHERSTATS3_AFRAMECHECKSEQUENCEERRORS 0x39cc0 +#define A_MAC_MTIP_ETHERSTATS3_VLANRECEIVEDOK 0x39cc4 +#define A_MAC_MTIP_ETHERSTATS3_IFINERRORS_RX 0x39cc8 +#define A_MAC_MTIP_ETHERSTATS3_IFINUCASTPKTS_RX 0x39ccc +#define A_MAC_MTIP_ETHERSTATS3_IFINMULTICASTPKTS_RX 0x39cd0 +#define A_MAC_MTIP_ETHERSTATS3_IFINBROADCASTPKTS_RX 0x39cd4 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSDROPEVENTS_RX 0x39cd8 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_RX 0x39cdc +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSUNDERSIZEPKTS_RX 0x39ce0 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_RX 0x39ce4 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_RX 0x39ce8 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_RX 0x39cec +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_RX 0x39cf0 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39cf4 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39cf8 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39cfc +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOVERSIZEPKTS_RX 0x39d00 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSJABBERS_RX 0x39d04 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSFRAGMENTS_RX 0x39d08 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39d0c +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39d10 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39d14 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39d18 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39d1c +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39d20 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39d24 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39d28 +#define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESRECEIVED_RX 0x39d2c +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS_TX 0x39d30 +#define A_MAC_MTIP_ETHERSTATS0_OCTETSTRANSMITTEDOK_TX 0x39d34 +#define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39d38 +#define A_MAC_MTIP_ETHERSTATS0_AFRAMESTRANSMITTEDOK_TX 0x39d3c +#define A_MAC_MTIP_ETHERSTATS0_VLANTRANSMITTEDOK_TX 0x39d40 +#define A_MAC_MTIP_ETHERSTATS0_IFOUTERRORS_TX 0x39d44 +#define A_MAC_MTIP_ETHERSTATS0_IFOUTUCASTPKTS_TX 0x39d48 +#define A_MAC_MTIP_ETHERSTATS0IFOUTMULTICASTPKTS_TX 0x39d4c +#define A_MAC_MTIP_ETHERSTATS0_IFOUTBROADCASTPKTS_TX 0x39d50 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_TX 0x39d54 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_TX 0x39d58 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_TX 0x39d5c +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_TX 0x39d60 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39d64 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39d68 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39d6c +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39d70 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39d74 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39d78 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39d7c +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39d80 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39d84 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39d88 +#define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39d8c +#define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESTRANSMITTED_TX 0x39d90 +#define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_TX 0x39d94 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS_TX 0x39d98 +#define A_MAC_MTIP_ETHERSTATS1_OCTETSTRANSMITTEDOK_TX 0x39d9c +#define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39da0 +#define A_MAC_MTIP_ETHERSTATS1_AFRAMESTRANSMITTEDOK_TX 0x39da4 +#define A_MAC_MTIP_ETHERSTATS1_VLANTRANSMITTEDOK_TX 0x39da8 +#define A_MAC_MTIP_ETHERSTATS1_IFOUTERRORS_TX 0x39dac +#define A_MAC_MTIP_ETHERSTATS1_IFOUTUCASTPKTS_TX 0x39db0 +#define A_MAC_MTIP_ETHERSTATS1IFOUTMULTICASTPKTS_TX 0x39db4 +#define A_MAC_MTIP_ETHERSTATS1_IFOUTBROADCASTPKTS_TX 0x39db8 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_TX 0x39dbc +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_TX 0x39dc0 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_TX 0x39dc4 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_TX 0x39dc8 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39dcc +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39dd0 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39dd4 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39dd8 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39ddc +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39de0 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39de4 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39de8 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39dec +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39df0 +#define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39df4 +#define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESTRANSMITTED_TX 0x39df8 +#define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_TX 0x39dfc +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS_TX 0x39e00 +#define A_MAC_MTIP_ETHERSTATS2_OCTETSTRANSMITTEDOK_TX 0x39e04 +#define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e08 +#define A_MAC_MTIP_ETHERSTATS2_AFRAMESTRANSMITTEDOK_TX 0x39e0c +#define A_MAC_MTIP_ETHERSTATS2_VLANTRANSMITTEDOK_TX 0x39e10 +#define A_MAC_MTIP_ETHERSTATS2_IFOUTERRORS_TX 0x39e14 +#define A_MAC_MTIP_ETHERSTATS2_IFOUTUCASTPKTS_TX 0x39e18 +#define A_MAC_MTIP_ETHERSTATS2IFOUTMULTICASTPKTS_TX 0x39e1c +#define A_MAC_MTIP_ETHERSTATS2_IFOUTBROADCASTPKTS_TX 0x39e20 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_TX 0x39e24 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e28 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e2c +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e30 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e34 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39e38 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39e3c +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39e40 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39e44 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39e48 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39e4c +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39e50 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39e54 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39e58 +#define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39e5c +#define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESTRANSMITTED_TX 0x39e60 +#define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_TX 0x39e64 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS_TX 0x39e68 +#define A_MAC_MTIP_ETHERSTATS3_OCTETSTRANSMITTEDOK_TX 0x39e6c +#define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e70 +#define A_MAC_MTIP_ETHERSTATS3_AFRAMESTRANSMITTEDOK_TX 0x39e74 +#define A_MAC_MTIP_ETHERSTATS3_VLANTRANSMITTEDOK_TX 0x39e78 +#define A_MAC_MTIP_ETHERSTATS3_IFOUTERRORS_TX 0x39e7c +#define A_MAC_MTIP_ETHERSTATS3_IFOUTUCASTPKTS_TX 0x39e80 +#define A_MAC_MTIP_ETHERSTATS3IFOUTMULTICASTPKTS_TX 0x39e84 +#define A_MAC_MTIP_ETHERSTATS3_IFOUTBROADCASTPKTS_TX 0x39e88 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_TX 0x39e8c +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e90 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e94 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e98 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e9c +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39ea0 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39ea4 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39ea8 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39eac +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39eb0 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39eb4 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39eb8 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39ebc +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39ec0 +#define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39ec4 +#define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESTRANSMITTED_TX 0x39ec8 +#define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_TX 0x39ecc +#define A_MAC_IOS_CTRL 0x3a000 + +#define S_SUB_BLOCK_SEL 28 +#define M_SUB_BLOCK_SEL 0x7U +#define V_SUB_BLOCK_SEL(x) ((x) << S_SUB_BLOCK_SEL) +#define G_SUB_BLOCK_SEL(x) (((x) >> S_SUB_BLOCK_SEL) & M_SUB_BLOCK_SEL) + +#define S_QUAD_BROADCAST_EN 24 +#define V_QUAD_BROADCAST_EN(x) ((x) << S_QUAD_BROADCAST_EN) +#define F_QUAD_BROADCAST_EN V_QUAD_BROADCAST_EN(1U) + +#define S_AUTO_INCR 20 +#define V_AUTO_INCR(x) ((x) << S_AUTO_INCR) +#define F_AUTO_INCR V_AUTO_INCR(1U) + +#define S_T7_2_ADDR 0 +#define M_T7_2_ADDR 0x7ffffU +#define V_T7_2_ADDR(x) ((x) << S_T7_2_ADDR) +#define G_T7_2_ADDR(x) (((x) >> S_T7_2_ADDR) & M_T7_2_ADDR) + +#define A_MAC_IOS_DATA 0x3a004 +#define A_MAC_IOS_BGR_RST 0x3a050 + +#define S_BGR_RSTN 0 +#define V_BGR_RSTN(x) ((x) << S_BGR_RSTN) +#define F_BGR_RSTN V_BGR_RSTN(1U) + +#define A_MAC_IOS_BGR_CFG 0x3a054 + +#define S_SOC_REFCLK_EN 0 +#define V_SOC_REFCLK_EN(x) ((x) << S_SOC_REFCLK_EN) +#define F_SOC_REFCLK_EN V_SOC_REFCLK_EN(1U) + +#define A_MAC_IOS_QUAD0_CFG 0x3a058 + +#define S_QUAD0_CH3_RSTN 5 +#define V_QUAD0_CH3_RSTN(x) ((x) << S_QUAD0_CH3_RSTN) +#define F_QUAD0_CH3_RSTN V_QUAD0_CH3_RSTN(1U) + +#define S_QUAD0_CH2_RSTN 4 +#define V_QUAD0_CH2_RSTN(x) ((x) << S_QUAD0_CH2_RSTN) +#define F_QUAD0_CH2_RSTN V_QUAD0_CH2_RSTN(1U) + +#define S_QUAD0_CH1_RSTN 3 +#define V_QUAD0_CH1_RSTN(x) ((x) << S_QUAD0_CH1_RSTN) +#define F_QUAD0_CH1_RSTN V_QUAD0_CH1_RSTN(1U) + +#define S_QUAD0_CH0_RSTN 2 +#define V_QUAD0_CH0_RSTN(x) ((x) << S_QUAD0_CH0_RSTN) +#define F_QUAD0_CH0_RSTN V_QUAD0_CH0_RSTN(1U) + +#define S_QUAD0_RSTN 1 +#define V_QUAD0_RSTN(x) ((x) << S_QUAD0_RSTN) +#define F_QUAD0_RSTN V_QUAD0_RSTN(1U) + +#define S_PLL0_RSTN 0 +#define V_PLL0_RSTN(x) ((x) << S_PLL0_RSTN) +#define F_PLL0_RSTN V_PLL0_RSTN(1U) + +#define A_MAC_IOS_QUAD1_CFG 0x3a05c + +#define S_QUAD1_CH3_RSTN 5 +#define V_QUAD1_CH3_RSTN(x) ((x) << S_QUAD1_CH3_RSTN) +#define F_QUAD1_CH3_RSTN V_QUAD1_CH3_RSTN(1U) + +#define S_QUAD1_CH2_RSTN 4 +#define V_QUAD1_CH2_RSTN(x) ((x) << S_QUAD1_CH2_RSTN) +#define F_QUAD1_CH2_RSTN V_QUAD1_CH2_RSTN(1U) + +#define S_QUAD1_CH1_RSTN 3 +#define V_QUAD1_CH1_RSTN(x) ((x) << S_QUAD1_CH1_RSTN) +#define F_QUAD1_CH1_RSTN V_QUAD1_CH1_RSTN(1U) + +#define S_QUAD1_CH0_RSTN 2 +#define V_QUAD1_CH0_RSTN(x) ((x) << S_QUAD1_CH0_RSTN) +#define F_QUAD1_CH0_RSTN V_QUAD1_CH0_RSTN(1U) + +#define S_QUAD1_RSTN 1 +#define V_QUAD1_RSTN(x) ((x) << S_QUAD1_RSTN) +#define F_QUAD1_RSTN V_QUAD1_RSTN(1U) + +#define S_PLL1_RSTN 0 +#define V_PLL1_RSTN(x) ((x) << S_PLL1_RSTN) +#define F_PLL1_RSTN V_PLL1_RSTN(1U) + +#define A_MAC_IOS_SCRATCHPAD0 0x3a060 +#define A_MAC_IOS_SCRATCHPAD1 0x3a064 +#define A_MAC_IOS_SCRATCHPAD2 0x3a068 +#define A_MAC_IOS_SCRATCHPAD3 0x3a06c + +#define S_DATA0 1 +#define M_DATA0 0x7fffffffU +#define V_DATA0(x) ((x) << S_DATA0) +#define G_DATA0(x) (((x) >> S_DATA0) & M_DATA0) + +#define S_I2C_MODE 0 +#define V_I2C_MODE(x) ((x) << S_I2C_MODE) +#define F_I2C_MODE V_I2C_MODE(1U) + +#define A_MAC_IOS_BGR_DBG_COUNTER 0x3a070 +#define A_MAC_IOS_QUAD0_DBG_COUNTER 0x3a074 +#define A_MAC_IOS_PLL0_DBG_COUNTER 0x3a078 +#define A_MAC_IOS_QUAD1_DBG_COUNTER 0x3a07c +#define A_MAC_IOS_PLL1_DBG_COUNTER 0x3a080 +#define A_MAC_IOS_DBG_CLK_CFG 0x3a084 + +#define S_DBG_CLK_MUX_GPIO 3 +#define V_DBG_CLK_MUX_GPIO(x) ((x) << S_DBG_CLK_MUX_GPIO) +#define F_DBG_CLK_MUX_GPIO V_DBG_CLK_MUX_GPIO(1U) + +#define S_DBG_CLK_MUX_SEL 0 +#define M_DBG_CLK_MUX_SEL 0x7U +#define V_DBG_CLK_MUX_SEL(x) ((x) << S_DBG_CLK_MUX_SEL) +#define G_DBG_CLK_MUX_SEL(x) (((x) >> S_DBG_CLK_MUX_SEL) & M_DBG_CLK_MUX_SEL) + +#define A_MAC_IOS_INTR_EN_QUAD0 0x3a090 + +#define S_Q0_MAILBOX_INT_ASSERT 24 +#define V_Q0_MAILBOX_INT_ASSERT(x) ((x) << S_Q0_MAILBOX_INT_ASSERT) +#define F_Q0_MAILBOX_INT_ASSERT V_Q0_MAILBOX_INT_ASSERT(1U) + +#define S_Q0_TRAINING_FAILURE_3_ASSERT 23 +#define V_Q0_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_3_ASSERT) +#define F_Q0_TRAINING_FAILURE_3_ASSERT V_Q0_TRAINING_FAILURE_3_ASSERT(1U) + +#define S_Q0_TRAINING_FAILURE_2_ASSERT 22 +#define V_Q0_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_2_ASSERT) +#define F_Q0_TRAINING_FAILURE_2_ASSERT V_Q0_TRAINING_FAILURE_2_ASSERT(1U) + +#define S_Q0_TRAINING_FAILURE_1_ASSERT 21 +#define V_Q0_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_1_ASSERT) +#define F_Q0_TRAINING_FAILURE_1_ASSERT V_Q0_TRAINING_FAILURE_1_ASSERT(1U) + +#define S_Q0_TRAINING_FAILURE_0_ASSERT 20 +#define V_Q0_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_0_ASSERT) +#define F_Q0_TRAINING_FAILURE_0_ASSERT V_Q0_TRAINING_FAILURE_0_ASSERT(1U) + +#define S_Q0_TRAINING_COMPLETE_3_ASSERT 19 +#define V_Q0_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_3_ASSERT) +#define F_Q0_TRAINING_COMPLETE_3_ASSERT V_Q0_TRAINING_COMPLETE_3_ASSERT(1U) + +#define S_Q0_TRAINING_COMPLETE_2_ASSERT 18 +#define V_Q0_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_2_ASSERT) +#define F_Q0_TRAINING_COMPLETE_2_ASSERT V_Q0_TRAINING_COMPLETE_2_ASSERT(1U) + +#define S_Q0_TRAINING_COMPLETE_1_ASSERT 17 +#define V_Q0_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_1_ASSERT) +#define F_Q0_TRAINING_COMPLETE_1_ASSERT V_Q0_TRAINING_COMPLETE_1_ASSERT(1U) + +#define S_Q0_TRAINING_COMPLETE_0_ASSERT 16 +#define V_Q0_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_0_ASSERT) +#define F_Q0_TRAINING_COMPLETE_0_ASSERT V_Q0_TRAINING_COMPLETE_0_ASSERT(1U) + +#define S_Q0_AN_TX_INT_3_ASSERT 15 +#define V_Q0_AN_TX_INT_3_ASSERT(x) ((x) << S_Q0_AN_TX_INT_3_ASSERT) +#define F_Q0_AN_TX_INT_3_ASSERT V_Q0_AN_TX_INT_3_ASSERT(1U) + +#define S_Q0_AN_TX_INT_2_ASSERT 14 +#define V_Q0_AN_TX_INT_2_ASSERT(x) ((x) << S_Q0_AN_TX_INT_2_ASSERT) +#define F_Q0_AN_TX_INT_2_ASSERT V_Q0_AN_TX_INT_2_ASSERT(1U) + +#define S_Q0_AN_TX_INT_1_ASSERT 13 +#define V_Q0_AN_TX_INT_1_ASSERT(x) ((x) << S_Q0_AN_TX_INT_1_ASSERT) +#define F_Q0_AN_TX_INT_1_ASSERT V_Q0_AN_TX_INT_1_ASSERT(1U) + +#define S_Q0_AN_TX_INT_0_ASSERT 12 +#define V_Q0_AN_TX_INT_0_ASSERT(x) ((x) << S_Q0_AN_TX_INT_0_ASSERT) +#define F_Q0_AN_TX_INT_0_ASSERT V_Q0_AN_TX_INT_0_ASSERT(1U) + +#define S_Q0_SIGNAL_DETECT_3_ASSERT 11 +#define V_Q0_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_3_ASSERT) +#define F_Q0_SIGNAL_DETECT_3_ASSERT V_Q0_SIGNAL_DETECT_3_ASSERT(1U) + +#define S_Q0_SIGNAL_DETECT_2_ASSERT 10 +#define V_Q0_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_2_ASSERT) +#define F_Q0_SIGNAL_DETECT_2_ASSERT V_Q0_SIGNAL_DETECT_2_ASSERT(1U) + +#define S_Q0_SIGNAL_DETECT_1_ASSERT 9 +#define V_Q0_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_1_ASSERT) +#define F_Q0_SIGNAL_DETECT_1_ASSERT V_Q0_SIGNAL_DETECT_1_ASSERT(1U) + +#define S_Q0_SIGNAL_DETECT_0_ASSERT 8 +#define V_Q0_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_0_ASSERT) +#define F_Q0_SIGNAL_DETECT_0_ASSERT V_Q0_SIGNAL_DETECT_0_ASSERT(1U) + +#define S_Q0_CDR_LOL_3_ASSERT 7 +#define V_Q0_CDR_LOL_3_ASSERT(x) ((x) << S_Q0_CDR_LOL_3_ASSERT) +#define F_Q0_CDR_LOL_3_ASSERT V_Q0_CDR_LOL_3_ASSERT(1U) + +#define S_Q0_CDR_LOL_2_ASSERT 6 +#define V_Q0_CDR_LOL_2_ASSERT(x) ((x) << S_Q0_CDR_LOL_2_ASSERT) +#define F_Q0_CDR_LOL_2_ASSERT V_Q0_CDR_LOL_2_ASSERT(1U) + +#define S_Q0_CDR_LOL_1_ASSERT 5 +#define V_Q0_CDR_LOL_1_ASSERT(x) ((x) << S_Q0_CDR_LOL_1_ASSERT) +#define F_Q0_CDR_LOL_1_ASSERT V_Q0_CDR_LOL_1_ASSERT(1U) + +#define S_Q0_CDR_LOL_0_ASSERT 4 +#define V_Q0_CDR_LOL_0_ASSERT(x) ((x) << S_Q0_CDR_LOL_0_ASSERT) +#define F_Q0_CDR_LOL_0_ASSERT V_Q0_CDR_LOL_0_ASSERT(1U) + +#define S_Q0_LOS_3_ASSERT 3 +#define V_Q0_LOS_3_ASSERT(x) ((x) << S_Q0_LOS_3_ASSERT) +#define F_Q0_LOS_3_ASSERT V_Q0_LOS_3_ASSERT(1U) + +#define S_Q0_LOS_2_ASSERT 2 +#define V_Q0_LOS_2_ASSERT(x) ((x) << S_Q0_LOS_2_ASSERT) +#define F_Q0_LOS_2_ASSERT V_Q0_LOS_2_ASSERT(1U) + +#define S_Q0_LOS_1_ASSERT 1 +#define V_Q0_LOS_1_ASSERT(x) ((x) << S_Q0_LOS_1_ASSERT) +#define F_Q0_LOS_1_ASSERT V_Q0_LOS_1_ASSERT(1U) + +#define S_Q0_LOS_0_ASSERT 0 +#define V_Q0_LOS_0_ASSERT(x) ((x) << S_Q0_LOS_0_ASSERT) +#define F_Q0_LOS_0_ASSERT V_Q0_LOS_0_ASSERT(1U) + +#define A_MAC_IOS_INTR_CAUSE_QUAD0 0x3a094 +#define A_MAC_IOS_INTR_EN_QUAD1 0x3a098 + +#define S_Q1_MAILBOX_INT_ASSERT 24 +#define V_Q1_MAILBOX_INT_ASSERT(x) ((x) << S_Q1_MAILBOX_INT_ASSERT) +#define F_Q1_MAILBOX_INT_ASSERT V_Q1_MAILBOX_INT_ASSERT(1U) + +#define S_Q1_TRAINING_FAILURE_3_ASSERT 23 +#define V_Q1_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_3_ASSERT) +#define F_Q1_TRAINING_FAILURE_3_ASSERT V_Q1_TRAINING_FAILURE_3_ASSERT(1U) + +#define S_Q1_TRAINING_FAILURE_2_ASSERT 22 +#define V_Q1_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_2_ASSERT) +#define F_Q1_TRAINING_FAILURE_2_ASSERT V_Q1_TRAINING_FAILURE_2_ASSERT(1U) + +#define S_Q1_TRAINING_FAILURE_1_ASSERT 21 +#define V_Q1_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_1_ASSERT) +#define F_Q1_TRAINING_FAILURE_1_ASSERT V_Q1_TRAINING_FAILURE_1_ASSERT(1U) + +#define S_Q1_TRAINING_FAILURE_0_ASSERT 20 +#define V_Q1_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_0_ASSERT) +#define F_Q1_TRAINING_FAILURE_0_ASSERT V_Q1_TRAINING_FAILURE_0_ASSERT(1U) + +#define S_Q1_TRAINING_COMPLETE_3_ASSERT 19 +#define V_Q1_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_3_ASSERT) +#define F_Q1_TRAINING_COMPLETE_3_ASSERT V_Q1_TRAINING_COMPLETE_3_ASSERT(1U) + +#define S_Q1_TRAINING_COMPLETE_2_ASSERT 18 +#define V_Q1_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_2_ASSERT) +#define F_Q1_TRAINING_COMPLETE_2_ASSERT V_Q1_TRAINING_COMPLETE_2_ASSERT(1U) + +#define S_Q1_TRAINING_COMPLETE_1_ASSERT 17 +#define V_Q1_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_1_ASSERT) +#define F_Q1_TRAINING_COMPLETE_1_ASSERT V_Q1_TRAINING_COMPLETE_1_ASSERT(1U) + +#define S_Q1_TRAINING_COMPLETE_0_ASSERT 16 +#define V_Q1_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_0_ASSERT) +#define F_Q1_TRAINING_COMPLETE_0_ASSERT V_Q1_TRAINING_COMPLETE_0_ASSERT(1U) + +#define S_Q1_AN_TX_INT_3_ASSERT 15 +#define V_Q1_AN_TX_INT_3_ASSERT(x) ((x) << S_Q1_AN_TX_INT_3_ASSERT) +#define F_Q1_AN_TX_INT_3_ASSERT V_Q1_AN_TX_INT_3_ASSERT(1U) + +#define S_Q1_AN_TX_INT_2_ASSERT 14 +#define V_Q1_AN_TX_INT_2_ASSERT(x) ((x) << S_Q1_AN_TX_INT_2_ASSERT) +#define F_Q1_AN_TX_INT_2_ASSERT V_Q1_AN_TX_INT_2_ASSERT(1U) + +#define S_Q1_AN_TX_INT_1_ASSERT 13 +#define V_Q1_AN_TX_INT_1_ASSERT(x) ((x) << S_Q1_AN_TX_INT_1_ASSERT) +#define F_Q1_AN_TX_INT_1_ASSERT V_Q1_AN_TX_INT_1_ASSERT(1U) + +#define S_Q1_AN_TX_INT_0_ASSERT 12 +#define V_Q1_AN_TX_INT_0_ASSERT(x) ((x) << S_Q1_AN_TX_INT_0_ASSERT) +#define F_Q1_AN_TX_INT_0_ASSERT V_Q1_AN_TX_INT_0_ASSERT(1U) + +#define S_Q1_SIGNAL_DETECT_3_ASSERT 11 +#define V_Q1_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_3_ASSERT) +#define F_Q1_SIGNAL_DETECT_3_ASSERT V_Q1_SIGNAL_DETECT_3_ASSERT(1U) + +#define S_Q1_SIGNAL_DETECT_2_ASSERT 10 +#define V_Q1_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_2_ASSERT) +#define F_Q1_SIGNAL_DETECT_2_ASSERT V_Q1_SIGNAL_DETECT_2_ASSERT(1U) + +#define S_Q1_SIGNAL_DETECT_1_ASSERT 9 +#define V_Q1_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_1_ASSERT) +#define F_Q1_SIGNAL_DETECT_1_ASSERT V_Q1_SIGNAL_DETECT_1_ASSERT(1U) + +#define S_Q1_SIGNAL_DETECT_0_ASSERT 8 +#define V_Q1_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_0_ASSERT) +#define F_Q1_SIGNAL_DETECT_0_ASSERT V_Q1_SIGNAL_DETECT_0_ASSERT(1U) + +#define S_Q1_CDR_LOL_3_ASSERT 7 +#define V_Q1_CDR_LOL_3_ASSERT(x) ((x) << S_Q1_CDR_LOL_3_ASSERT) +#define F_Q1_CDR_LOL_3_ASSERT V_Q1_CDR_LOL_3_ASSERT(1U) + +#define S_Q1_CDR_LOL_2_ASSERT 6 +#define V_Q1_CDR_LOL_2_ASSERT(x) ((x) << S_Q1_CDR_LOL_2_ASSERT) +#define F_Q1_CDR_LOL_2_ASSERT V_Q1_CDR_LOL_2_ASSERT(1U) + +#define S_Q1_CDR_LOL_1_ASSERT 5 +#define V_Q1_CDR_LOL_1_ASSERT(x) ((x) << S_Q1_CDR_LOL_1_ASSERT) +#define F_Q1_CDR_LOL_1_ASSERT V_Q1_CDR_LOL_1_ASSERT(1U) + +#define S_Q1_CDR_LOL_0_ASSERT 4 +#define V_Q1_CDR_LOL_0_ASSERT(x) ((x) << S_Q1_CDR_LOL_0_ASSERT) +#define F_Q1_CDR_LOL_0_ASSERT V_Q1_CDR_LOL_0_ASSERT(1U) + +#define S_Q1_LOS_3_ASSERT 3 +#define V_Q1_LOS_3_ASSERT(x) ((x) << S_Q1_LOS_3_ASSERT) +#define F_Q1_LOS_3_ASSERT V_Q1_LOS_3_ASSERT(1U) + +#define S_Q1_LOS_2_ASSERT 2 +#define V_Q1_LOS_2_ASSERT(x) ((x) << S_Q1_LOS_2_ASSERT) +#define F_Q1_LOS_2_ASSERT V_Q1_LOS_2_ASSERT(1U) + +#define S_Q1_LOS_1_ASSERT 1 +#define V_Q1_LOS_1_ASSERT(x) ((x) << S_Q1_LOS_1_ASSERT) +#define F_Q1_LOS_1_ASSERT V_Q1_LOS_1_ASSERT(1U) + +#define S_Q1_LOS_0_ASSERT 0 +#define V_Q1_LOS_0_ASSERT(x) ((x) << S_Q1_LOS_0_ASSERT) +#define F_Q1_LOS_0_ASSERT V_Q1_LOS_0_ASSERT(1U) + +#define A_MAC_IOS_INTR_CAUSE_QUAD1 0x3a09c +#define A_MAC_MTIP_PCS_1G_0_CONTROL 0x3e000 + +#define S_SPEED_SEL_1 13 +#define V_SPEED_SEL_1(x) ((x) << S_SPEED_SEL_1) +#define F_SPEED_SEL_1 V_SPEED_SEL_1(1U) + +#define S_AUTO_NEG_ENA 12 +#define V_AUTO_NEG_ENA(x) ((x) << S_AUTO_NEG_ENA) +#define F_AUTO_NEG_ENA V_AUTO_NEG_ENA(1U) + +#define S_T7_POWER_DOWN 11 +#define V_T7_POWER_DOWN(x) ((x) << S_T7_POWER_DOWN) +#define F_T7_POWER_DOWN V_T7_POWER_DOWN(1U) + +#define S_RESTART_AUTO_NEG 9 +#define V_RESTART_AUTO_NEG(x) ((x) << S_RESTART_AUTO_NEG) +#define F_RESTART_AUTO_NEG V_RESTART_AUTO_NEG(1U) + +#define S_SPEED_SEL_0 6 +#define V_SPEED_SEL_0(x) ((x) << S_SPEED_SEL_0) +#define F_SPEED_SEL_0 V_SPEED_SEL_0(1U) + +#define A_MAC_MTIP_PCS_1G_0_STATUS 0x3e004 + +#define S_100BASE_T4 15 +#define V_100BASE_T4(x) ((x) << S_100BASE_T4) +#define F_100BASE_T4 V_100BASE_T4(1U) + +#define S_100BASE_X_FULL_DUPLEX 14 +#define V_100BASE_X_FULL_DUPLEX(x) ((x) << S_100BASE_X_FULL_DUPLEX) +#define F_100BASE_X_FULL_DUPLEX V_100BASE_X_FULL_DUPLEX(1U) + +#define S_100BASE_X_HALF_DUPLEX 13 +#define V_100BASE_X_HALF_DUPLEX(x) ((x) << S_100BASE_X_HALF_DUPLEX) +#define F_100BASE_X_HALF_DUPLEX V_100BASE_X_HALF_DUPLEX(1U) + +#define S_10MBPS_FULL_DUPLEX 12 +#define V_10MBPS_FULL_DUPLEX(x) ((x) << S_10MBPS_FULL_DUPLEX) +#define F_10MBPS_FULL_DUPLEX V_10MBPS_FULL_DUPLEX(1U) + +#define S_10MBPS_HALF_DUPLEX 11 +#define V_10MBPS_HALF_DUPLEX(x) ((x) << S_10MBPS_HALF_DUPLEX) +#define F_10MBPS_HALF_DUPLEX V_10MBPS_HALF_DUPLEX(1U) + +#define S_100BASE_T2_HALF_DUPLEX1 10 +#define V_100BASE_T2_HALF_DUPLEX1(x) ((x) << S_100BASE_T2_HALF_DUPLEX1) +#define F_100BASE_T2_HALF_DUPLEX1 V_100BASE_T2_HALF_DUPLEX1(1U) + +#define S_100BASE_T2_HALF_DUPLEX0 9 +#define V_100BASE_T2_HALF_DUPLEX0(x) ((x) << S_100BASE_T2_HALF_DUPLEX0) +#define F_100BASE_T2_HALF_DUPLEX0 V_100BASE_T2_HALF_DUPLEX0(1U) + +#define S_T7_EXTENDED_STATUS 8 +#define V_T7_EXTENDED_STATUS(x) ((x) << S_T7_EXTENDED_STATUS) +#define F_T7_EXTENDED_STATUS V_T7_EXTENDED_STATUS(1U) + +#define S_AUTO_NEG_COMPLETE 5 +#define V_AUTO_NEG_COMPLETE(x) ((x) << S_AUTO_NEG_COMPLETE) +#define F_AUTO_NEG_COMPLETE V_AUTO_NEG_COMPLETE(1U) + +#define S_T7_REMOTE_FAULT 4 +#define V_T7_REMOTE_FAULT(x) ((x) << S_T7_REMOTE_FAULT) +#define F_T7_REMOTE_FAULT V_T7_REMOTE_FAULT(1U) + +#define S_AUTO_NEG_ABILITY 3 +#define V_AUTO_NEG_ABILITY(x) ((x) << S_AUTO_NEG_ABILITY) +#define F_AUTO_NEG_ABILITY V_AUTO_NEG_ABILITY(1U) + +#define S_JABBER_DETECT 1 +#define V_JABBER_DETECT(x) ((x) << S_JABBER_DETECT) +#define F_JABBER_DETECT V_JABBER_DETECT(1U) + +#define S_EXTENDED_CAPABILITY 0 +#define V_EXTENDED_CAPABILITY(x) ((x) << S_EXTENDED_CAPABILITY) +#define F_EXTENDED_CAPABILITY V_EXTENDED_CAPABILITY(1U) + +#define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_0 0x3e008 +#define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_1 0x3e00c +#define A_MAC_MTIP_PCS_1G_0_DEV_ABILITY 0x3e010 + +#define S_EEE_CLOCK_STOP_ENABLE 8 +#define V_EEE_CLOCK_STOP_ENABLE(x) ((x) << S_EEE_CLOCK_STOP_ENABLE) +#define F_EEE_CLOCK_STOP_ENABLE V_EEE_CLOCK_STOP_ENABLE(1U) + +#define A_MAC_MTIP_PCS_1G_0_PARTNER_ABILITY 0x3e014 + +#define S_COPPER_LINK_STATUS 15 +#define V_COPPER_LINK_STATUS(x) ((x) << S_COPPER_LINK_STATUS) +#define F_COPPER_LINK_STATUS V_COPPER_LINK_STATUS(1U) + +#define S_COPPER_DUPLEX_STATUS 12 +#define V_COPPER_DUPLEX_STATUS(x) ((x) << S_COPPER_DUPLEX_STATUS) +#define F_COPPER_DUPLEX_STATUS V_COPPER_DUPLEX_STATUS(1U) + +#define S_COPPER_SPEED 10 +#define M_COPPER_SPEED 0x3U +#define V_COPPER_SPEED(x) ((x) << S_COPPER_SPEED) +#define G_COPPER_SPEED(x) (((x) >> S_COPPER_SPEED) & M_COPPER_SPEED) + +#define S_EEE_CAPABILITY 9 +#define V_EEE_CAPABILITY(x) ((x) << S_EEE_CAPABILITY) +#define F_EEE_CAPABILITY V_EEE_CAPABILITY(1U) + +#define S_EEE_CLOCK_STOP_CAPABILITY 8 +#define V_EEE_CLOCK_STOP_CAPABILITY(x) ((x) << S_EEE_CLOCK_STOP_CAPABILITY) +#define F_EEE_CLOCK_STOP_CAPABILITY V_EEE_CLOCK_STOP_CAPABILITY(1U) + +#define A_MAC_MTIP_PCS_1G_0_AN_EXPANSION 0x3e018 +#define A_MAC_MTIP_PCS_1G_0_NP_TX 0x3e01c +#define A_MAC_MTIP_PCS_1G_0_LP_NP_RX 0x3e020 + +#define S_T7_DATA 0 +#define M_T7_DATA 0x7ffU +#define V_T7_DATA(x) ((x) << S_T7_DATA) +#define G_T7_DATA(x) (((x) >> S_T7_DATA) & M_T7_DATA) + +#define A_MAC_MTIP_PCS_1G_0_EXTENDED_STATUS 0x3e03c +#define A_MAC_MTIP_PCS_1G_0_SCRATCH 0x3e040 +#define A_MAC_MTIP_PCS_1G_0_REV 0x3e044 +#define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_0 0x3e048 + +#define S_LINK_TIMER_VAL 0 +#define M_LINK_TIMER_VAL 0xffffU +#define V_LINK_TIMER_VAL(x) ((x) << S_LINK_TIMER_VAL) +#define G_LINK_TIMER_VAL(x) (((x) >> S_LINK_TIMER_VAL) & M_LINK_TIMER_VAL) + +#define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_1 0x3e04c + +#define S_T7_LINK_TIMER_VAL 0 +#define M_T7_LINK_TIMER_VAL 0x1fU +#define V_T7_LINK_TIMER_VAL(x) ((x) << S_T7_LINK_TIMER_VAL) +#define G_T7_LINK_TIMER_VAL(x) (((x) >> S_T7_LINK_TIMER_VAL) & M_T7_LINK_TIMER_VAL) + +#define A_MAC_MTIP_PCS_1G_0_IF_MODE 0x3e050 +#define A_MAC_MTIP_PCS_1G_0_DEC_ERR_CNT 0x3e054 +#define A_MAC_MTIP_PCS_1G_0_VENDOR_CONTROL 0x3e058 + +#define S_SGPCS_ENA_ST 15 +#define V_SGPCS_ENA_ST(x) ((x) << S_SGPCS_ENA_ST) +#define F_SGPCS_ENA_ST V_SGPCS_ENA_ST(1U) + +#define S_T7_CFG_CLOCK_RATE 4 +#define M_T7_CFG_CLOCK_RATE 0xfU +#define V_T7_CFG_CLOCK_RATE(x) ((x) << S_T7_CFG_CLOCK_RATE) +#define G_T7_CFG_CLOCK_RATE(x) (((x) >> S_T7_CFG_CLOCK_RATE) & M_T7_CFG_CLOCK_RATE) + +#define S_SGPCS_ENA_R 0 +#define V_SGPCS_ENA_R(x) ((x) << S_SGPCS_ENA_R) +#define F_SGPCS_ENA_R V_SGPCS_ENA_R(1U) + +#define A_MAC_MTIP_PCS_1G_0_SD_BIT_SLIP 0x3e05c + +#define S_SD_BIT_SLIP 0 +#define M_SD_BIT_SLIP 0xfU +#define V_SD_BIT_SLIP(x) ((x) << S_SD_BIT_SLIP) +#define G_SD_BIT_SLIP(x) (((x) >> S_SD_BIT_SLIP) & M_SD_BIT_SLIP) + +#define A_MAC_MTIP_PCS_1G_1_CONTROL 0x3e100 +#define A_MAC_MTIP_PCS_1G_1_STATUS 0x3e104 +#define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_0 0x3e108 +#define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_1 0x3e10c +#define A_MAC_MTIP_PCS_1G_1_DEV_ABILITY 0x3e110 +#define A_MAC_MTIP_PCS_1G_1_PARTNER_ABILITY 0x3e114 +#define A_MAC_MTIP_PCS_1G_1_AN_EXPANSION 0x3e118 +#define A_MAC_MTIP_PCS_1G_1_NP_TX 0x3e11c +#define A_MAC_MTIP_PCS_1G_1_LP_NP_RX 0x3e120 +#define A_MAC_MTIP_PCS_1G_1_EXTENDED_STATUS 0x3e13c +#define A_MAC_MTIP_PCS_1G_1_SCRATCH 0x3e140 +#define A_MAC_MTIP_PCS_1G_1_REV 0x3e144 +#define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_0 0x3e148 +#define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_1 0x3e14c +#define A_MAC_MTIP_PCS_1G_1_IF_MODE 0x3e150 +#define A_MAC_MTIP_PCS_1G_1_DEC_ERR_CNT 0x3e154 +#define A_MAC_MTIP_PCS_1G_1_VENDOR_CONTROL 0x3e158 +#define A_MAC_MTIP_PCS_1G_1_SD_BIT_SLIP 0x3e15c +#define A_MAC_MTIP_PCS_1G_2_CONTROL 0x3e200 +#define A_MAC_MTIP_PCS_1G_2_STATUS 0x3e204 +#define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_0 0x3e208 +#define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_1 0x3e20c +#define A_MAC_MTIP_PCS_1G_2_DEV_ABILITY 0x3e210 +#define A_MAC_MTIP_PCS_1G_2_PARTNER_ABILITY 0x3e214 +#define A_MAC_MTIP_PCS_1G_2_AN_EXPANSION 0x3e218 +#define A_MAC_MTIP_PCS_1G_2_NP_TX 0x3e21c +#define A_MAC_MTIP_PCS_1G_2_LP_NP_RX 0x3e220 +#define A_MAC_MTIP_PCS_1G_2_EXTENDED_STATUS 0x3e23c +#define A_MAC_MTIP_PCS_1G_2_SCRATCH 0x3e240 +#define A_MAC_MTIP_PCS_1G_2_REV 0x3e244 +#define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_0 0x3e248 +#define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_1 0x3e24c +#define A_MAC_MTIP_PCS_1G_2_IF_MODE 0x3e250 +#define A_MAC_MTIP_PCS_1G_2_DEC_ERR_CNT 0x3e254 +#define A_MAC_MTIP_PCS_1G_2_VENDOR_CONTROL 0x3e258 +#define A_MAC_MTIP_PCS_1G_2_SD_BIT_SLIP 0x3e25c +#define A_MAC_MTIP_PCS_1G_3_CONTROL 0x3e300 +#define A_MAC_MTIP_PCS_1G_3_STATUS 0x3e304 +#define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_0 0x3e308 +#define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_1 0x3e30c +#define A_MAC_MTIP_PCS_1G_3_DEV_ABILITY 0x3e310 +#define A_MAC_MTIP_PCS_1G_3_PARTNER_ABILITY 0x3e314 +#define A_MAC_MTIP_PCS_1G_3_AN_EXPANSION 0x3e318 +#define A_MAC_MTIP_PCS_1G_3_NP_TX 0x3e31c +#define A_MAC_MTIP_PCS_1G_3_LP_NP_RX 0x3e320 +#define A_MAC_MTIP_PCS_1G_3_EXTENDED_STATUS 0x3e33c +#define A_MAC_MTIP_PCS_1G_3_SCRATCH 0x3e340 +#define A_MAC_MTIP_PCS_1G_3_REV 0x3e344 +#define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_0 0x3e348 +#define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_1 0x3e34c +#define A_MAC_MTIP_PCS_1G_3_IF_MODE 0x3e350 +#define A_MAC_MTIP_PCS_1G_3_DEC_ERR_CNT 0x3e354 +#define A_MAC_MTIP_PCS_1G_3_VENDOR_CONTROL 0x3e358 +#define A_MAC_MTIP_PCS_1G_3_SD_BIT_SLIP 0x3e35c +#define A_MAC_DPLL_CTRL_0 0x3f000 + +#define S_LOCAL_FAULT_OVRD 18 +#define V_LOCAL_FAULT_OVRD(x) ((x) << S_LOCAL_FAULT_OVRD) +#define F_LOCAL_FAULT_OVRD V_LOCAL_FAULT_OVRD(1U) + +#define S_LOCAL_FAULT_HOLD_EN 17 +#define V_LOCAL_FAULT_HOLD_EN(x) ((x) << S_LOCAL_FAULT_HOLD_EN) +#define F_LOCAL_FAULT_HOLD_EN V_LOCAL_FAULT_HOLD_EN(1U) + +#define S_DPLL_RST 16 +#define V_DPLL_RST(x) ((x) << S_DPLL_RST) +#define F_DPLL_RST V_DPLL_RST(1U) + +#define S_CNTOFFSET 0 +#define M_CNTOFFSET 0xffffU +#define V_CNTOFFSET(x) ((x) << S_CNTOFFSET) +#define G_CNTOFFSET(x) (((x) >> S_CNTOFFSET) & M_CNTOFFSET) + +#define A_MAC_DPLL_CTRL_1 0x3f004 + +#define S_DELAYK 0 +#define M_DELAYK 0xffffffU +#define V_DELAYK(x) ((x) << S_DELAYK) +#define G_DELAYK(x) (((x) >> S_DELAYK) & M_DELAYK) + +#define A_MAC_DPLL_CTRL_2 0x3f008 + +#define S_DIVFFB 16 +#define M_DIVFFB 0xffffU +#define V_DIVFFB(x) ((x) << S_DIVFFB) +#define G_DIVFFB(x) (((x) >> S_DIVFFB) & M_DIVFFB) + +#define S_DIVFIN 0 +#define M_DIVFIN 0xffffU +#define V_DIVFIN(x) ((x) << S_DIVFIN) +#define G_DIVFIN(x) (((x) >> S_DIVFIN) & M_DIVFIN) + +#define A_MAC_DPLL_CTRL_3 0x3f00c + +#define S_ISHIFT_HOLD 28 +#define M_ISHIFT_HOLD 0xfU +#define V_ISHIFT_HOLD(x) ((x) << S_ISHIFT_HOLD) +#define G_ISHIFT_HOLD(x) (((x) >> S_ISHIFT_HOLD) & M_ISHIFT_HOLD) + +#define S_ISHIFT 24 +#define M_ISHIFT 0xfU +#define V_ISHIFT(x) ((x) << S_ISHIFT) +#define G_ISHIFT(x) (((x) >> S_ISHIFT) & M_ISHIFT) + +#define S_INT_PRESET 12 +#define M_INT_PRESET 0xfffU +#define V_INT_PRESET(x) ((x) << S_INT_PRESET) +#define G_INT_PRESET(x) (((x) >> S_INT_PRESET) & M_INT_PRESET) + +#define S_FMI 4 +#define M_FMI 0xffU +#define V_FMI(x) ((x) << S_FMI) +#define G_FMI(x) (((x) >> S_FMI) & M_FMI) + +#define S_DPLL_PROGRAM 3 +#define V_DPLL_PROGRAM(x) ((x) << S_DPLL_PROGRAM) +#define F_DPLL_PROGRAM V_DPLL_PROGRAM(1U) + +#define S_PRESET_EN 2 +#define V_PRESET_EN(x) ((x) << S_PRESET_EN) +#define F_PRESET_EN V_PRESET_EN(1U) + +#define S_ONTARGETOV 1 +#define V_ONTARGETOV(x) ((x) << S_ONTARGETOV) +#define F_ONTARGETOV V_ONTARGETOV(1U) + +#define S_FDONLY 0 +#define V_FDONLY(x) ((x) << S_FDONLY) +#define F_FDONLY V_FDONLY(1U) + +#define A_MAC_DPLL_CTRL_4 0x3f010 + +#define S_FKI 24 +#define M_FKI 0x1fU +#define V_FKI(x) ((x) << S_FKI) +#define G_FKI(x) (((x) >> S_FKI) & M_FKI) + +#define S_FRAC_PRESET 0 +#define M_FRAC_PRESET 0xffffffU +#define V_FRAC_PRESET(x) ((x) << S_FRAC_PRESET) +#define G_FRAC_PRESET(x) (((x) >> S_FRAC_PRESET) & M_FRAC_PRESET) + +#define A_MAC_DPLL_CTRL_5 0x3f014 + +#define S_PH_STEP_CNT_HOLD 24 +#define M_PH_STEP_CNT_HOLD 0x1fU +#define V_PH_STEP_CNT_HOLD(x) ((x) << S_PH_STEP_CNT_HOLD) +#define G_PH_STEP_CNT_HOLD(x) (((x) >> S_PH_STEP_CNT_HOLD) & M_PH_STEP_CNT_HOLD) + +#define S_CFG_RESET 23 +#define V_CFG_RESET(x) ((x) << S_CFG_RESET) +#define F_CFG_RESET V_CFG_RESET(1U) + +#define S_PH_STEP_CNT 16 +#define M_PH_STEP_CNT 0x1fU +#define V_PH_STEP_CNT(x) ((x) << S_PH_STEP_CNT) +#define G_PH_STEP_CNT(x) (((x) >> S_PH_STEP_CNT) & M_PH_STEP_CNT) + +#define S_OTDLY 0 +#define M_OTDLY 0xffffU +#define V_OTDLY(x) ((x) << S_OTDLY) +#define G_OTDLY(x) (((x) >> S_OTDLY) & M_OTDLY) + +#define A_MAC_DPLL_CTRL_6 0x3f018 + +#define S_TARGETCNT 16 +#define M_TARGETCNT 0xffffU +#define V_TARGETCNT(x) ((x) << S_TARGETCNT) +#define G_TARGETCNT(x) (((x) >> S_TARGETCNT) & M_TARGETCNT) + +#define S_PKP 8 +#define M_PKP 0x1fU +#define V_PKP(x) ((x) << S_PKP) +#define G_PKP(x) (((x) >> S_PKP) & M_PKP) + +#define S_PMP 0 +#define M_PMP 0xffU +#define V_PMP(x) ((x) << S_PMP) +#define G_PMP(x) (((x) >> S_PMP) & M_PMP) + +#define A_MAC_DPLL_CTRL_7 0x3f01c +#define A_MAC_DPLL_STATUS_0 0x3f020 + +#define S_FRAC 0 +#define M_FRAC 0xffffffU +#define V_FRAC(x) ((x) << S_FRAC) +#define G_FRAC(x) (((x) >> S_FRAC) & M_FRAC) + +#define A_MAC_DPLL_STATUS_1 0x3f024 + +#define S_FRAC_PD_OUT 0 +#define M_FRAC_PD_OUT 0xffffffU +#define V_FRAC_PD_OUT(x) ((x) << S_FRAC_PD_OUT) +#define G_FRAC_PD_OUT(x) (((x) >> S_FRAC_PD_OUT) & M_FRAC_PD_OUT) + +#define A_MAC_DPLL_STATUS_2 0x3f028 + +#define S_INT 12 +#define M_INT 0xfffU +#define V_INT(x) ((x) << S_INT) +#define G_INT(x) (((x) >> S_INT) & M_INT) + +#define S_INT_PD_OUT 0 +#define M_INT_PD_OUT 0xfffU +#define V_INT_PD_OUT(x) ((x) << S_INT_PD_OUT) +#define G_INT_PD_OUT(x) (((x) >> S_INT_PD_OUT) & M_INT_PD_OUT) + +#define A_MAC_FRAC_N_PLL_CTRL_0 0x3f02c + +#define S_FRAC_N_DSKEWCALCNT 29 +#define M_FRAC_N_DSKEWCALCNT 0x7U +#define V_FRAC_N_DSKEWCALCNT(x) ((x) << S_FRAC_N_DSKEWCALCNT) +#define G_FRAC_N_DSKEWCALCNT(x) (((x) >> S_FRAC_N_DSKEWCALCNT) & M_FRAC_N_DSKEWCALCNT) + +#define S_PLLEN 28 +#define V_PLLEN(x) ((x) << S_PLLEN) +#define F_PLLEN V_PLLEN(1U) + +#define S_T7_BYPASS 24 +#define M_T7_BYPASS 0xfU +#define V_T7_BYPASS(x) ((x) << S_T7_BYPASS) +#define G_T7_BYPASS(x) (((x) >> S_T7_BYPASS) & M_T7_BYPASS) + +#define S_POSTDIV3A 21 +#define M_POSTDIV3A 0x7U +#define V_POSTDIV3A(x) ((x) << S_POSTDIV3A) +#define G_POSTDIV3A(x) (((x) >> S_POSTDIV3A) & M_POSTDIV3A) + +#define S_POSTDIV3B 18 +#define M_POSTDIV3B 0x7U +#define V_POSTDIV3B(x) ((x) << S_POSTDIV3B) +#define G_POSTDIV3B(x) (((x) >> S_POSTDIV3B) & M_POSTDIV3B) + +#define S_POSTDIV2A 15 +#define M_POSTDIV2A 0x7U +#define V_POSTDIV2A(x) ((x) << S_POSTDIV2A) +#define G_POSTDIV2A(x) (((x) >> S_POSTDIV2A) & M_POSTDIV2A) + +#define S_POSTDIV2B 12 +#define M_POSTDIV2B 0x7U +#define V_POSTDIV2B(x) ((x) << S_POSTDIV2B) +#define G_POSTDIV2B(x) (((x) >> S_POSTDIV2B) & M_POSTDIV2B) + +#define S_POSTDIV1A 9 +#define M_POSTDIV1A 0x7U +#define V_POSTDIV1A(x) ((x) << S_POSTDIV1A) +#define G_POSTDIV1A(x) (((x) >> S_POSTDIV1A) & M_POSTDIV1A) + +#define S_POSTDIV1B 6 +#define M_POSTDIV1B 0x7U +#define V_POSTDIV1B(x) ((x) << S_POSTDIV1B) +#define G_POSTDIV1B(x) (((x) >> S_POSTDIV1B) & M_POSTDIV1B) + +#define S_POSTDIV0A 3 +#define M_POSTDIV0A 0x7U +#define V_POSTDIV0A(x) ((x) << S_POSTDIV0A) +#define G_POSTDIV0A(x) (((x) >> S_POSTDIV0A) & M_POSTDIV0A) + +#define S_POSTDIV0B 0 +#define M_POSTDIV0B 0x7U +#define V_POSTDIV0B(x) ((x) << S_POSTDIV0B) +#define G_POSTDIV0B(x) (((x) >> S_POSTDIV0B) & M_POSTDIV0B) + +#define A_MAC_FRAC_N_PLL_CTRL_1 0x3f030 + +#define S_FRAC_N_FRAC_N_FOUTEN 28 +#define M_FRAC_N_FRAC_N_FOUTEN 0xfU +#define V_FRAC_N_FRAC_N_FOUTEN(x) ((x) << S_FRAC_N_FRAC_N_FOUTEN) +#define G_FRAC_N_FRAC_N_FOUTEN(x) (((x) >> S_FRAC_N_FRAC_N_FOUTEN) & M_FRAC_N_FRAC_N_FOUTEN) + +#define S_FRAC_N_DSKEWCALIN 16 +#define M_FRAC_N_DSKEWCALIN 0xfffU +#define V_FRAC_N_DSKEWCALIN(x) ((x) << S_FRAC_N_DSKEWCALIN) +#define G_FRAC_N_DSKEWCALIN(x) (((x) >> S_FRAC_N_DSKEWCALIN) & M_FRAC_N_DSKEWCALIN) + +#define S_FRAC_N_REFDIV 10 +#define M_FRAC_N_REFDIV 0x3fU +#define V_FRAC_N_REFDIV(x) ((x) << S_FRAC_N_REFDIV) +#define G_FRAC_N_REFDIV(x) (((x) >> S_FRAC_N_REFDIV) & M_FRAC_N_REFDIV) + +#define S_FRAC_N_DSMEN 9 +#define V_FRAC_N_DSMEN(x) ((x) << S_FRAC_N_DSMEN) +#define F_FRAC_N_DSMEN V_FRAC_N_DSMEN(1U) + +#define S_FRAC_N_PLLEN 8 +#define V_FRAC_N_PLLEN(x) ((x) << S_FRAC_N_PLLEN) +#define F_FRAC_N_PLLEN V_FRAC_N_PLLEN(1U) + +#define S_FRAC_N_DACEN 7 +#define V_FRAC_N_DACEN(x) ((x) << S_FRAC_N_DACEN) +#define F_FRAC_N_DACEN V_FRAC_N_DACEN(1U) + +#define S_FRAC_N_POSTDIV0PRE 6 +#define V_FRAC_N_POSTDIV0PRE(x) ((x) << S_FRAC_N_POSTDIV0PRE) +#define F_FRAC_N_POSTDIV0PRE V_FRAC_N_POSTDIV0PRE(1U) + +#define S_FRAC_N_DSKEWCALBYP 5 +#define V_FRAC_N_DSKEWCALBYP(x) ((x) << S_FRAC_N_DSKEWCALBYP) +#define F_FRAC_N_DSKEWCALBYP V_FRAC_N_DSKEWCALBYP(1U) + +#define S_FRAC_N_DSKEWFASTCAL 4 +#define V_FRAC_N_DSKEWFASTCAL(x) ((x) << S_FRAC_N_DSKEWFASTCAL) +#define F_FRAC_N_DSKEWFASTCAL V_FRAC_N_DSKEWFASTCAL(1U) + +#define S_FRAC_N_DSKEWCALEN 3 +#define V_FRAC_N_DSKEWCALEN(x) ((x) << S_FRAC_N_DSKEWCALEN) +#define F_FRAC_N_DSKEWCALEN V_FRAC_N_DSKEWCALEN(1U) + +#define S_FRAC_N_FREFCMLEN 2 +#define V_FRAC_N_FREFCMLEN(x) ((x) << S_FRAC_N_FREFCMLEN) +#define F_FRAC_N_FREFCMLEN V_FRAC_N_FREFCMLEN(1U) + +#define A_MAC_FRAC_N_PLL_STATUS_0 0x3f034 + +#define S_DSKEWCALLOCK 12 +#define V_DSKEWCALLOCK(x) ((x) << S_DSKEWCALLOCK) +#define F_DSKEWCALLOCK V_DSKEWCALLOCK(1U) + +#define S_DSKEWCALOUT 0 +#define M_DSKEWCALOUT 0xfffU +#define V_DSKEWCALOUT(x) ((x) << S_DSKEWCALOUT) +#define G_DSKEWCALOUT(x) (((x) >> S_DSKEWCALOUT) & M_DSKEWCALOUT) + +#define A_MAC_MTIP_PCS_STATUS_0 0x3f100 + +#define S_XLGMII7_TX_TSU 22 +#define M_XLGMII7_TX_TSU 0x3U +#define V_XLGMII7_TX_TSU(x) ((x) << S_XLGMII7_TX_TSU) +#define G_XLGMII7_TX_TSU(x) (((x) >> S_XLGMII7_TX_TSU) & M_XLGMII7_TX_TSU) + +#define S_XLGMII6_TX_TSU 20 +#define M_XLGMII6_TX_TSU 0x3U +#define V_XLGMII6_TX_TSU(x) ((x) << S_XLGMII6_TX_TSU) +#define G_XLGMII6_TX_TSU(x) (((x) >> S_XLGMII6_TX_TSU) & M_XLGMII6_TX_TSU) + +#define S_XLGMII5_TX_TSU 18 +#define M_XLGMII5_TX_TSU 0x3U +#define V_XLGMII5_TX_TSU(x) ((x) << S_XLGMII5_TX_TSU) +#define G_XLGMII5_TX_TSU(x) (((x) >> S_XLGMII5_TX_TSU) & M_XLGMII5_TX_TSU) + +#define S_XLGMII4_TX_TSU 16 +#define M_XLGMII4_TX_TSU 0x3U +#define V_XLGMII4_TX_TSU(x) ((x) << S_XLGMII4_TX_TSU) +#define G_XLGMII4_TX_TSU(x) (((x) >> S_XLGMII4_TX_TSU) & M_XLGMII4_TX_TSU) + +#define S_XLGMII3_TX_TSU 14 +#define M_XLGMII3_TX_TSU 0x3U +#define V_XLGMII3_TX_TSU(x) ((x) << S_XLGMII3_TX_TSU) +#define G_XLGMII3_TX_TSU(x) (((x) >> S_XLGMII3_TX_TSU) & M_XLGMII3_TX_TSU) + +#define S_XLGMII2_TX_TSU 12 +#define M_XLGMII2_TX_TSU 0x3U +#define V_XLGMII2_TX_TSU(x) ((x) << S_XLGMII2_TX_TSU) +#define G_XLGMII2_TX_TSU(x) (((x) >> S_XLGMII2_TX_TSU) & M_XLGMII2_TX_TSU) + +#define S_XLGMII1_TX_TSU 10 +#define M_XLGMII1_TX_TSU 0x3U +#define V_XLGMII1_TX_TSU(x) ((x) << S_XLGMII1_TX_TSU) +#define G_XLGMII1_TX_TSU(x) (((x) >> S_XLGMII1_TX_TSU) & M_XLGMII1_TX_TSU) + +#define S_XLGMII0_TX_TSU 8 +#define M_XLGMII0_TX_TSU 0x3U +#define V_XLGMII0_TX_TSU(x) ((x) << S_XLGMII0_TX_TSU) +#define G_XLGMII0_TX_TSU(x) (((x) >> S_XLGMII0_TX_TSU) & M_XLGMII0_TX_TSU) + +#define S_CGMII3_TX_TSU 6 +#define M_CGMII3_TX_TSU 0x3U +#define V_CGMII3_TX_TSU(x) ((x) << S_CGMII3_TX_TSU) +#define G_CGMII3_TX_TSU(x) (((x) >> S_CGMII3_TX_TSU) & M_CGMII3_TX_TSU) + +#define S_CGMII2_TX_TSU 4 +#define M_CGMII2_TX_TSU 0x3U +#define V_CGMII2_TX_TSU(x) ((x) << S_CGMII2_TX_TSU) +#define G_CGMII2_TX_TSU(x) (((x) >> S_CGMII2_TX_TSU) & M_CGMII2_TX_TSU) + +#define S_CGMII1_TX_TSU 2 +#define M_CGMII1_TX_TSU 0x3U +#define V_CGMII1_TX_TSU(x) ((x) << S_CGMII1_TX_TSU) +#define G_CGMII1_TX_TSU(x) (((x) >> S_CGMII1_TX_TSU) & M_CGMII1_TX_TSU) + +#define S_CGMII0_TX_TSU 0 +#define M_CGMII0_TX_TSU 0x3U +#define V_CGMII0_TX_TSU(x) ((x) << S_CGMII0_TX_TSU) +#define G_CGMII0_TX_TSU(x) (((x) >> S_CGMII0_TX_TSU) & M_CGMII0_TX_TSU) + +#define A_MAC_MTIP_PCS_STATUS_1 0x3f104 + +#define S_CDMII1_RX_TSU 26 +#define M_CDMII1_RX_TSU 0x3U +#define V_CDMII1_RX_TSU(x) ((x) << S_CDMII1_RX_TSU) +#define G_CDMII1_RX_TSU(x) (((x) >> S_CDMII1_RX_TSU) & M_CDMII1_RX_TSU) + +#define S_CDMII0_RX_TSU 24 +#define M_CDMII0_RX_TSU 0x3U +#define V_CDMII0_RX_TSU(x) ((x) << S_CDMII0_RX_TSU) +#define G_CDMII0_RX_TSU(x) (((x) >> S_CDMII0_RX_TSU) & M_CDMII0_RX_TSU) + +#define S_XLGMII7_RX_TSU 22 +#define M_XLGMII7_RX_TSU 0x3U +#define V_XLGMII7_RX_TSU(x) ((x) << S_XLGMII7_RX_TSU) +#define G_XLGMII7_RX_TSU(x) (((x) >> S_XLGMII7_RX_TSU) & M_XLGMII7_RX_TSU) + +#define S_XLGMII6_RX_TSU 20 +#define M_XLGMII6_RX_TSU 0x3U +#define V_XLGMII6_RX_TSU(x) ((x) << S_XLGMII6_RX_TSU) +#define G_XLGMII6_RX_TSU(x) (((x) >> S_XLGMII6_RX_TSU) & M_XLGMII6_RX_TSU) + +#define S_XLGMII5_RX_TSU 18 +#define M_XLGMII5_RX_TSU 0x3U +#define V_XLGMII5_RX_TSU(x) ((x) << S_XLGMII5_RX_TSU) +#define G_XLGMII5_RX_TSU(x) (((x) >> S_XLGMII5_RX_TSU) & M_XLGMII5_RX_TSU) + +#define S_XLGMII4_RX_TSU 16 +#define M_XLGMII4_RX_TSU 0x3U +#define V_XLGMII4_RX_TSU(x) ((x) << S_XLGMII4_RX_TSU) +#define G_XLGMII4_RX_TSU(x) (((x) >> S_XLGMII4_RX_TSU) & M_XLGMII4_RX_TSU) + +#define S_XLGMII3_RX_TSU 14 +#define M_XLGMII3_RX_TSU 0x3U +#define V_XLGMII3_RX_TSU(x) ((x) << S_XLGMII3_RX_TSU) +#define G_XLGMII3_RX_TSU(x) (((x) >> S_XLGMII3_RX_TSU) & M_XLGMII3_RX_TSU) + +#define S_XLGMII2_RX_TSU 12 +#define M_XLGMII2_RX_TSU 0x3U +#define V_XLGMII2_RX_TSU(x) ((x) << S_XLGMII2_RX_TSU) +#define G_XLGMII2_RX_TSU(x) (((x) >> S_XLGMII2_RX_TSU) & M_XLGMII2_RX_TSU) + +#define S_XLGMII1_RX_TSU 10 +#define M_XLGMII1_RX_TSU 0x3U +#define V_XLGMII1_RX_TSU(x) ((x) << S_XLGMII1_RX_TSU) +#define G_XLGMII1_RX_TSU(x) (((x) >> S_XLGMII1_RX_TSU) & M_XLGMII1_RX_TSU) + +#define S_XLGMII0_RX_TSU 8 +#define M_XLGMII0_RX_TSU 0x3U +#define V_XLGMII0_RX_TSU(x) ((x) << S_XLGMII0_RX_TSU) +#define G_XLGMII0_RX_TSU(x) (((x) >> S_XLGMII0_RX_TSU) & M_XLGMII0_RX_TSU) + +#define S_CGMII3_RX_TSU 6 +#define M_CGMII3_RX_TSU 0x3U +#define V_CGMII3_RX_TSU(x) ((x) << S_CGMII3_RX_TSU) +#define G_CGMII3_RX_TSU(x) (((x) >> S_CGMII3_RX_TSU) & M_CGMII3_RX_TSU) + +#define S_CGMII2_RX_TSU 4 +#define M_CGMII2_RX_TSU 0x3U +#define V_CGMII2_RX_TSU(x) ((x) << S_CGMII2_RX_TSU) +#define G_CGMII2_RX_TSU(x) (((x) >> S_CGMII2_RX_TSU) & M_CGMII2_RX_TSU) + +#define S_CGMII1_RX_TSU 2 +#define M_CGMII1_RX_TSU 0x3U +#define V_CGMII1_RX_TSU(x) ((x) << S_CGMII1_RX_TSU) +#define G_CGMII1_RX_TSU(x) (((x) >> S_CGMII1_RX_TSU) & M_CGMII1_RX_TSU) + +#define S_CGMII0_RX_TSU 0 +#define M_CGMII0_RX_TSU 0x3U +#define V_CGMII0_RX_TSU(x) ((x) << S_CGMII0_RX_TSU) +#define G_CGMII0_RX_TSU(x) (((x) >> S_CGMII0_RX_TSU) & M_CGMII0_RX_TSU) + +#define A_MAC_MTIP_PCS_STATUS_2 0x3f108 + +#define S_SD_BIT_SLIP_0 0 +#define M_SD_BIT_SLIP_0 0x3fffffffU +#define V_SD_BIT_SLIP_0(x) ((x) << S_SD_BIT_SLIP_0) +#define G_SD_BIT_SLIP_0(x) (((x) >> S_SD_BIT_SLIP_0) & M_SD_BIT_SLIP_0) + +#define A_MAC_MTIP_PCS_STATUS_3 0x3f10c + +#define S_SD_BIT_SLIP_1 0 +#define M_SD_BIT_SLIP_1 0x3ffffU +#define V_SD_BIT_SLIP_1(x) ((x) << S_SD_BIT_SLIP_1) +#define G_SD_BIT_SLIP_1(x) (((x) >> S_SD_BIT_SLIP_1) & M_SD_BIT_SLIP_1) + +#define A_MAC_MTIP_PCS_STATUS_4 0x3f110 + +#define S_TSU_RX_SD 0 +#define M_TSU_RX_SD 0xffffU +#define V_TSU_RX_SD(x) ((x) << S_TSU_RX_SD) +#define G_TSU_RX_SD(x) (((x) >> S_TSU_RX_SD) & M_TSU_RX_SD) + +#define A_MAC_MTIP_PCS_STATUS_5 0x3f114 + +#define S_RSFEC_XSTATS_STRB 0 +#define M_RSFEC_XSTATS_STRB 0xffffffU +#define V_RSFEC_XSTATS_STRB(x) ((x) << S_RSFEC_XSTATS_STRB) +#define G_RSFEC_XSTATS_STRB(x) (((x) >> S_RSFEC_XSTATS_STRB) & M_RSFEC_XSTATS_STRB) + +#define A_MAC_MTIP_PCS_STATUS_6 0x3f118 +#define A_MAC_MTIP_PCS_STATUS_7 0x3f11c +#define A_MAC_MTIP_MAC_10G_100G_STATUS_0 0x3f120 + +#define S_TSV_XON_STB_2 24 +#define M_TSV_XON_STB_2 0xffU +#define V_TSV_XON_STB_2(x) ((x) << S_TSV_XON_STB_2) +#define G_TSV_XON_STB_2(x) (((x) >> S_TSV_XON_STB_2) & M_TSV_XON_STB_2) + +#define S_TSV_XOFF_STB_2 16 +#define M_TSV_XOFF_STB_2 0xffU +#define V_TSV_XOFF_STB_2(x) ((x) << S_TSV_XOFF_STB_2) +#define G_TSV_XOFF_STB_2(x) (((x) >> S_TSV_XOFF_STB_2) & M_TSV_XOFF_STB_2) + +#define S_RSV_XON_STB_2 8 +#define M_RSV_XON_STB_2 0xffU +#define V_RSV_XON_STB_2(x) ((x) << S_RSV_XON_STB_2) +#define G_RSV_XON_STB_2(x) (((x) >> S_RSV_XON_STB_2) & M_RSV_XON_STB_2) + +#define S_RSV_XOFF_STB_2 0 +#define M_RSV_XOFF_STB_2 0xffU +#define V_RSV_XOFF_STB_2(x) ((x) << S_RSV_XOFF_STB_2) +#define G_RSV_XOFF_STB_2(x) (((x) >> S_RSV_XOFF_STB_2) & M_RSV_XOFF_STB_2) + +#define A_MAC_MTIP_MAC_10G_100G_STATUS_1 0x3f124 + +#define S_TSV_XON_STB_3 24 +#define M_TSV_XON_STB_3 0xffU +#define V_TSV_XON_STB_3(x) ((x) << S_TSV_XON_STB_3) +#define G_TSV_XON_STB_3(x) (((x) >> S_TSV_XON_STB_3) & M_TSV_XON_STB_3) + +#define S_TSV_XOFF_STB_3 16 +#define M_TSV_XOFF_STB_3 0xffU +#define V_TSV_XOFF_STB_3(x) ((x) << S_TSV_XOFF_STB_3) +#define G_TSV_XOFF_STB_3(x) (((x) >> S_TSV_XOFF_STB_3) & M_TSV_XOFF_STB_3) + +#define S_RSV_XON_STB_3 8 +#define M_RSV_XON_STB_3 0xffU +#define V_RSV_XON_STB_3(x) ((x) << S_RSV_XON_STB_3) +#define G_RSV_XON_STB_3(x) (((x) >> S_RSV_XON_STB_3) & M_RSV_XON_STB_3) + +#define S_RSV_XOFF_STB_3 0 +#define M_RSV_XOFF_STB_3 0xffU +#define V_RSV_XOFF_STB_3(x) ((x) << S_RSV_XOFF_STB_3) +#define G_RSV_XOFF_STB_3(x) (((x) >> S_RSV_XOFF_STB_3) & M_RSV_XOFF_STB_3) + +#define A_MAC_MTIP_MAC_10G_100G_STATUS_2 0x3f128 + +#define S_TSV_XON_STB_4 24 +#define M_TSV_XON_STB_4 0xffU +#define V_TSV_XON_STB_4(x) ((x) << S_TSV_XON_STB_4) +#define G_TSV_XON_STB_4(x) (((x) >> S_TSV_XON_STB_4) & M_TSV_XON_STB_4) + +#define S_TSV_XOFF_STB_4 16 +#define M_TSV_XOFF_STB_4 0xffU +#define V_TSV_XOFF_STB_4(x) ((x) << S_TSV_XOFF_STB_4) +#define G_TSV_XOFF_STB_4(x) (((x) >> S_TSV_XOFF_STB_4) & M_TSV_XOFF_STB_4) + +#define S_RSV_XON_STB_4 8 +#define M_RSV_XON_STB_4 0xffU +#define V_RSV_XON_STB_4(x) ((x) << S_RSV_XON_STB_4) +#define G_RSV_XON_STB_4(x) (((x) >> S_RSV_XON_STB_4) & M_RSV_XON_STB_4) + +#define S_RSV_XOFF_STB_4 0 +#define M_RSV_XOFF_STB_4 0xffU +#define V_RSV_XOFF_STB_4(x) ((x) << S_RSV_XOFF_STB_4) +#define G_RSV_XOFF_STB_4(x) (((x) >> S_RSV_XOFF_STB_4) & M_RSV_XOFF_STB_4) + +#define A_MAC_MTIP_MAC_10G_100G_STATUS_3 0x3f12c + +#define S_TSV_XON_STB_5 24 +#define M_TSV_XON_STB_5 0xffU +#define V_TSV_XON_STB_5(x) ((x) << S_TSV_XON_STB_5) +#define G_TSV_XON_STB_5(x) (((x) >> S_TSV_XON_STB_5) & M_TSV_XON_STB_5) + +#define S_TSV_XOFF_STB_5 16 +#define M_TSV_XOFF_STB_5 0xffU +#define V_TSV_XOFF_STB_5(x) ((x) << S_TSV_XOFF_STB_5) +#define G_TSV_XOFF_STB_5(x) (((x) >> S_TSV_XOFF_STB_5) & M_TSV_XOFF_STB_5) + +#define S_RSV_XON_STB_5 8 +#define M_RSV_XON_STB_5 0xffU +#define V_RSV_XON_STB_5(x) ((x) << S_RSV_XON_STB_5) +#define G_RSV_XON_STB_5(x) (((x) >> S_RSV_XON_STB_5) & M_RSV_XON_STB_5) + +#define S_RSV_XOFF_STB_5 0 +#define M_RSV_XOFF_STB_5 0xffU +#define V_RSV_XOFF_STB_5(x) ((x) << S_RSV_XOFF_STB_5) +#define G_RSV_XOFF_STB_5(x) (((x) >> S_RSV_XOFF_STB_5) & M_RSV_XOFF_STB_5) + +#define A_MAC_MTIP_MAC_10G_100G_STATUS_4 0x3f130 + +#define S_TX_SFD_O_5 19 +#define V_TX_SFD_O_5(x) ((x) << S_TX_SFD_O_5) +#define F_TX_SFD_O_5 V_TX_SFD_O_5(1U) + +#define S_TX_SFD_O_4 18 +#define V_TX_SFD_O_4(x) ((x) << S_TX_SFD_O_4) +#define F_TX_SFD_O_4 V_TX_SFD_O_4(1U) + +#define S_TX_SFD_O_3 17 +#define V_TX_SFD_O_3(x) ((x) << S_TX_SFD_O_3) +#define F_TX_SFD_O_3 V_TX_SFD_O_3(1U) + +#define S_TX_SFD_O_2 16 +#define V_TX_SFD_O_2(x) ((x) << S_TX_SFD_O_2) +#define F_TX_SFD_O_2 V_TX_SFD_O_2(1U) + +#define S_RX_SFD_O_5 15 +#define V_RX_SFD_O_5(x) ((x) << S_RX_SFD_O_5) +#define F_RX_SFD_O_5 V_RX_SFD_O_5(1U) + +#define S_RX_SFD_O_4 14 +#define V_RX_SFD_O_4(x) ((x) << S_RX_SFD_O_4) +#define F_RX_SFD_O_4 V_RX_SFD_O_4(1U) + +#define S_RX_SFD_O_3 13 +#define V_RX_SFD_O_3(x) ((x) << S_RX_SFD_O_3) +#define F_RX_SFD_O_3 V_RX_SFD_O_3(1U) + +#define S_RX_SFD_O_2 12 +#define V_RX_SFD_O_2(x) ((x) << S_RX_SFD_O_2) +#define F_RX_SFD_O_2 V_RX_SFD_O_2(1U) + +#define S_RX_SFD_SHIFT_O_5 11 +#define V_RX_SFD_SHIFT_O_5(x) ((x) << S_RX_SFD_SHIFT_O_5) +#define F_RX_SFD_SHIFT_O_5 V_RX_SFD_SHIFT_O_5(1U) + +#define S_RX_SFD_SHIFT_O_4 10 +#define V_RX_SFD_SHIFT_O_4(x) ((x) << S_RX_SFD_SHIFT_O_4) +#define F_RX_SFD_SHIFT_O_4 V_RX_SFD_SHIFT_O_4(1U) + +#define S_RX_SFD_SHIFT_O_3 9 +#define V_RX_SFD_SHIFT_O_3(x) ((x) << S_RX_SFD_SHIFT_O_3) +#define F_RX_SFD_SHIFT_O_3 V_RX_SFD_SHIFT_O_3(1U) + +#define S_RX_SFD_SHIFT_O_2 8 +#define V_RX_SFD_SHIFT_O_2(x) ((x) << S_RX_SFD_SHIFT_O_2) +#define F_RX_SFD_SHIFT_O_2 V_RX_SFD_SHIFT_O_2(1U) + +#define S_TX_SFD_SHIFT_O_5 7 +#define V_TX_SFD_SHIFT_O_5(x) ((x) << S_TX_SFD_SHIFT_O_5) +#define F_TX_SFD_SHIFT_O_5 V_TX_SFD_SHIFT_O_5(1U) + +#define S_TX_SFD_SHIFT_O_4 6 +#define V_TX_SFD_SHIFT_O_4(x) ((x) << S_TX_SFD_SHIFT_O_4) +#define F_TX_SFD_SHIFT_O_4 V_TX_SFD_SHIFT_O_4(1U) + +#define S_TX_SFD_SHIFT_O_3 5 +#define V_TX_SFD_SHIFT_O_3(x) ((x) << S_TX_SFD_SHIFT_O_3) +#define F_TX_SFD_SHIFT_O_3 V_TX_SFD_SHIFT_O_3(1U) + +#define S_TX_SFD_SHIFT_O_2 4 +#define V_TX_SFD_SHIFT_O_2(x) ((x) << S_TX_SFD_SHIFT_O_2) +#define F_TX_SFD_SHIFT_O_2 V_TX_SFD_SHIFT_O_2(1U) + +#define S_TS_SFD_ENA_5 3 +#define V_TS_SFD_ENA_5(x) ((x) << S_TS_SFD_ENA_5) +#define F_TS_SFD_ENA_5 V_TS_SFD_ENA_5(1U) + +#define S_TS_SFD_ENA_4 2 +#define V_TS_SFD_ENA_4(x) ((x) << S_TS_SFD_ENA_4) +#define F_TS_SFD_ENA_4 V_TS_SFD_ENA_4(1U) + +#define S_TS_SFD_ENA_3 1 +#define V_TS_SFD_ENA_3(x) ((x) << S_TS_SFD_ENA_3) +#define F_TS_SFD_ENA_3 V_TS_SFD_ENA_3(1U) + +#define S_TS_SFD_ENA_2 0 +#define V_TS_SFD_ENA_2(x) ((x) << S_TS_SFD_ENA_2) +#define F_TS_SFD_ENA_2 V_TS_SFD_ENA_2(1U) + +#define A_MAC_STS_CONFIG 0x3f200 + +#define S_STS_ENA 30 +#define V_STS_ENA(x) ((x) << S_STS_ENA) +#define F_STS_ENA V_STS_ENA(1U) + +#define S_N_PPS_ENA 29 +#define V_N_PPS_ENA(x) ((x) << S_N_PPS_ENA) +#define F_N_PPS_ENA V_N_PPS_ENA(1U) + +#define S_STS_RESET 28 +#define V_STS_RESET(x) ((x) << S_STS_RESET) +#define F_STS_RESET V_STS_RESET(1U) + +#define S_DEBOUNCE_CNT 0 +#define M_DEBOUNCE_CNT 0xfffffffU +#define V_DEBOUNCE_CNT(x) ((x) << S_DEBOUNCE_CNT) +#define G_DEBOUNCE_CNT(x) (((x) >> S_DEBOUNCE_CNT) & M_DEBOUNCE_CNT) + +#define A_MAC_STS_COUNTER 0x3f204 +#define A_MAC_STS_COUNT_1 0x3f208 +#define A_MAC_STS_COUNT_2 0x3f20c +#define A_MAC_STS_N_PPS_COUNT_HI 0x3f210 +#define A_MAC_STS_N_PPS_COUNT_LO 0x3f214 +#define A_MAC_STS_N_PPS_COUNTER 0x3f218 +#define A_MAC_BGR_PQ0_FIRMWARE_COMMON_0 0x4030 + +#define S_MAC_BGR_BGR_REG_APB_SEL 0 +#define V_MAC_BGR_BGR_REG_APB_SEL(x) ((x) << S_MAC_BGR_BGR_REG_APB_SEL) +#define F_MAC_BGR_BGR_REG_APB_SEL V_MAC_BGR_BGR_REG_APB_SEL(1U) + +#define A_MAC_BGR_TOP_DIG_CTRL1_REG_LSB 0x4430 + +#define S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS 15 +#define V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(x) ((x) << S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS) +#define F_MAC_BGR_BGR_REFCLK_CTRL_BYPASS V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(1U) + +#define S_MAC_BGR_BGR_COREREFCLK_SEL 14 +#define V_MAC_BGR_BGR_COREREFCLK_SEL(x) ((x) << S_MAC_BGR_BGR_COREREFCLK_SEL) +#define F_MAC_BGR_BGR_COREREFCLK_SEL V_MAC_BGR_BGR_COREREFCLK_SEL(1U) + +#define S_MAC_BGR_BGR_TEST_CLK_DIV 8 +#define M_MAC_BGR_BGR_TEST_CLK_DIV 0x7U +#define V_MAC_BGR_BGR_TEST_CLK_DIV(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_DIV) +#define G_MAC_BGR_BGR_TEST_CLK_DIV(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_DIV) & M_MAC_BGR_BGR_TEST_CLK_DIV) + +#define S_MAC_BGR_BGR_TEST_CLK_EN 7 +#define V_MAC_BGR_BGR_TEST_CLK_EN(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_EN) +#define F_MAC_BGR_BGR_TEST_CLK_EN V_MAC_BGR_BGR_TEST_CLK_EN(1U) + +#define S_MAC_BGR_BGR_TEST_CLK_BGRSEL 5 +#define M_MAC_BGR_BGR_TEST_CLK_BGRSEL 0x3U +#define V_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_BGRSEL) +#define G_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_BGRSEL) & M_MAC_BGR_BGR_TEST_CLK_BGRSEL) + +#define S_MAC_BGR_BGR_TEST_CLK_SEL 0 +#define M_MAC_BGR_BGR_TEST_CLK_SEL 0x1fU +#define V_MAC_BGR_BGR_TEST_CLK_SEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_SEL) +#define G_MAC_BGR_BGR_TEST_CLK_SEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_SEL) & M_MAC_BGR_BGR_TEST_CLK_SEL) + +#define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_0 0x6000 + +#define S_MAC_BGR_BGR_REG_PRG_EN 0 +#define V_MAC_BGR_BGR_REG_PRG_EN(x) ((x) << S_MAC_BGR_BGR_REG_PRG_EN) +#define F_MAC_BGR_BGR_REG_PRG_EN V_MAC_BGR_BGR_REG_PRG_EN(1U) + +#define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_1 0x6020 + +#define S_MAC_BGR_BGR_REG_GPO 0 +#define V_MAC_BGR_BGR_REG_GPO(x) ((x) << S_MAC_BGR_BGR_REG_GPO) +#define F_MAC_BGR_BGR_REG_GPO V_MAC_BGR_BGR_REG_GPO(1U) + +#define A_MAC_BGR_MGMT_SPINE_MACRO_PMA_0 0x40000 + +#define S_MAC_BGR_CUREFCLKSEL1 0 +#define M_MAC_BGR_CUREFCLKSEL1 0x3U +#define V_MAC_BGR_CUREFCLKSEL1(x) ((x) << S_MAC_BGR_CUREFCLKSEL1) +#define G_MAC_BGR_CUREFCLKSEL1(x) (((x) >> S_MAC_BGR_CUREFCLKSEL1) & M_MAC_BGR_CUREFCLKSEL1) + +#define A_MAC_BGR_REFCLK_CONTROL_1 0x40004 + +#define S_MAC_BGR_IM_CUREFCLKLR_EN 0 +#define V_MAC_BGR_IM_CUREFCLKLR_EN(x) ((x) << S_MAC_BGR_IM_CUREFCLKLR_EN) +#define F_MAC_BGR_IM_CUREFCLKLR_EN V_MAC_BGR_IM_CUREFCLKLR_EN(1U) + +#define A_MAC_BGR_REFCLK_CONTROL_2 0x40080 + +#define S_MAC_BGR_IM_REF_EN 0 +#define V_MAC_BGR_IM_REF_EN(x) ((x) << S_MAC_BGR_IM_REF_EN) +#define F_MAC_BGR_IM_REF_EN V_MAC_BGR_IM_REF_EN(1U) + +#define A_MAC_PLL0_PLL_TOP_CUPLL_LOCK 0x4438 + +#define S_MAC_PLL0_PLL2_LOCK_STATUS 2 +#define V_MAC_PLL0_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL2_LOCK_STATUS) +#define F_MAC_PLL0_PLL2_LOCK_STATUS V_MAC_PLL0_PLL2_LOCK_STATUS(1U) + +#define S_MAC_PLL0_PLL1_LOCK_STATUS 1 +#define V_MAC_PLL0_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL1_LOCK_STATUS) +#define F_MAC_PLL0_PLL1_LOCK_STATUS V_MAC_PLL0_PLL1_LOCK_STATUS(1U) + +#define S_MAC_PLL0_PLL0_LOCK_STATUS 0 +#define V_MAC_PLL0_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL0_LOCK_STATUS) +#define F_MAC_PLL0_PLL0_LOCK_STATUS V_MAC_PLL0_PLL0_LOCK_STATUS(1U) + +#define A_MAC_PLL0_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020 + +#define S_MAC_PLL0_PLL_PRG_EN 0 +#define M_MAC_PLL0_PLL_PRG_EN 0xfU +#define V_MAC_PLL0_PLL_PRG_EN(x) ((x) << S_MAC_PLL0_PLL_PRG_EN) +#define G_MAC_PLL0_PLL_PRG_EN(x) (((x) >> S_MAC_PLL0_PLL_PRG_EN) & M_MAC_PLL0_PLL_PRG_EN) + +#define A_MAC_PLL0_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00 + +#define S_MAC_PLL0_PMA_MACRO_SELECT 0 +#define M_MAC_PLL0_PMA_MACRO_SELECT 0x3ffU +#define V_MAC_PLL0_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL0_PMA_MACRO_SELECT) +#define G_MAC_PLL0_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL0_PMA_MACRO_SELECT) & M_MAC_PLL0_PMA_MACRO_SELECT) + +#define A_MAC_PLL1_PLL_TOP_CUPLL_LOCK 0x4438 + +#define S_MAC_PLL1_PLL2_LOCK_STATUS 2 +#define V_MAC_PLL1_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL2_LOCK_STATUS) +#define F_MAC_PLL1_PLL2_LOCK_STATUS V_MAC_PLL1_PLL2_LOCK_STATUS(1U) + +#define S_MAC_PLL1_PLL1_LOCK_STATUS 1 +#define V_MAC_PLL1_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL1_LOCK_STATUS) +#define F_MAC_PLL1_PLL1_LOCK_STATUS V_MAC_PLL1_PLL1_LOCK_STATUS(1U) + +#define S_MAC_PLL1_PLL0_LOCK_STATUS 0 +#define V_MAC_PLL1_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL0_LOCK_STATUS) +#define F_MAC_PLL1_PLL0_LOCK_STATUS V_MAC_PLL1_PLL0_LOCK_STATUS(1U) + +#define A_MAC_PLL1_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020 + +#define S_MAC_PLL1_PLL_PRG_EN 0 +#define M_MAC_PLL1_PLL_PRG_EN 0xfU +#define V_MAC_PLL1_PLL_PRG_EN(x) ((x) << S_MAC_PLL1_PLL_PRG_EN) +#define G_MAC_PLL1_PLL_PRG_EN(x) (((x) >> S_MAC_PLL1_PLL_PRG_EN) & M_MAC_PLL1_PLL_PRG_EN) + +#define A_MAC_PLL1_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00 + +#define S_MAC_PLL1_PMA_MACRO_SELECT 0 +#define M_MAC_PLL1_PMA_MACRO_SELECT 0x3ffU +#define V_MAC_PLL1_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL1_PMA_MACRO_SELECT) +#define G_MAC_PLL1_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL1_PMA_MACRO_SELECT) & M_MAC_PLL1_PMA_MACRO_SELECT) + +/* registers for module CRYPTO_0 */ +#define CRYPTO_0_BASE_ADDR 0x44000 + +#define A_TLS_TX_CH_CONFIG 0x44000 + +#define S_SMALL_LEN_THRESH 16 +#define M_SMALL_LEN_THRESH 0xffffU +#define V_SMALL_LEN_THRESH(x) ((x) << S_SMALL_LEN_THRESH) +#define G_SMALL_LEN_THRESH(x) (((x) >> S_SMALL_LEN_THRESH) & M_SMALL_LEN_THRESH) + +#define S_CIPH0_CTL_SEL 12 +#define M_CIPH0_CTL_SEL 0x7U +#define V_CIPH0_CTL_SEL(x) ((x) << S_CIPH0_CTL_SEL) +#define G_CIPH0_CTL_SEL(x) (((x) >> S_CIPH0_CTL_SEL) & M_CIPH0_CTL_SEL) + +#define S_CIPHN_CTL_SEL 9 +#define M_CIPHN_CTL_SEL 0x7U +#define V_CIPHN_CTL_SEL(x) ((x) << S_CIPHN_CTL_SEL) +#define G_CIPHN_CTL_SEL(x) (((x) >> S_CIPHN_CTL_SEL) & M_CIPHN_CTL_SEL) + +#define S_MAC_CTL_SEL 6 +#define M_MAC_CTL_SEL 0x7U +#define V_MAC_CTL_SEL(x) ((x) << S_MAC_CTL_SEL) +#define G_MAC_CTL_SEL(x) (((x) >> S_MAC_CTL_SEL) & M_MAC_CTL_SEL) + +#define S_CIPH0_XOR_SEL 5 +#define V_CIPH0_XOR_SEL(x) ((x) << S_CIPH0_XOR_SEL) +#define F_CIPH0_XOR_SEL V_CIPH0_XOR_SEL(1U) + +#define S_CIPHN_XOR_SEL 4 +#define V_CIPHN_XOR_SEL(x) ((x) << S_CIPHN_XOR_SEL) +#define F_CIPHN_XOR_SEL V_CIPHN_XOR_SEL(1U) + +#define S_MAC_XOR_SEL 3 +#define V_MAC_XOR_SEL(x) ((x) << S_MAC_XOR_SEL) +#define F_MAC_XOR_SEL V_MAC_XOR_SEL(1U) + +#define S_CIPH0_DP_SEL 2 +#define V_CIPH0_DP_SEL(x) ((x) << S_CIPH0_DP_SEL) +#define F_CIPH0_DP_SEL V_CIPH0_DP_SEL(1U) + +#define S_CIPHN_DP_SEL 1 +#define V_CIPHN_DP_SEL(x) ((x) << S_CIPHN_DP_SEL) +#define F_CIPHN_DP_SEL V_CIPHN_DP_SEL(1U) + +#define S_MAC_DP_SEL 0 +#define V_MAC_DP_SEL(x) ((x) << S_MAC_DP_SEL) +#define F_MAC_DP_SEL V_MAC_DP_SEL(1U) + +#define A_TLS_TX_CH_PERR_INJECT 0x44004 +#define A_TLS_TX_CH_INT_ENABLE 0x44008 + +#define S_KEYLENERR 3 +#define V_KEYLENERR(x) ((x) << S_KEYLENERR) +#define F_KEYLENERR V_KEYLENERR(1U) + +#define S_INTF1_PERR 2 +#define V_INTF1_PERR(x) ((x) << S_INTF1_PERR) +#define F_INTF1_PERR V_INTF1_PERR(1U) + +#define S_INTF0_PERR 1 +#define V_INTF0_PERR(x) ((x) << S_INTF0_PERR) +#define F_INTF0_PERR V_INTF0_PERR(1U) + +#define A_TLS_TX_CH_INT_CAUSE 0x4400c + +#define S_KEX_CERR 4 +#define V_KEX_CERR(x) ((x) << S_KEX_CERR) +#define F_KEX_CERR V_KEX_CERR(1U) + +#define A_TLS_TX_CH_PERR_ENABLE 0x44010 +#define A_TLS_TX_CH_DEBUG_FLAGS 0x44014 +#define A_TLS_TX_CH_HMACCTRL_CFG 0x44020 +#define A_TLS_TX_CH_ERR_RSP_HDR 0x44024 +#define A_TLS_TX_CH_HANG_TIMEOUT 0x44028 + +#define S_T7_TIMEOUT 0 +#define M_T7_TIMEOUT 0xffU +#define V_T7_TIMEOUT(x) ((x) << S_T7_TIMEOUT) +#define G_T7_TIMEOUT(x) (((x) >> S_T7_TIMEOUT) & M_T7_TIMEOUT) + +#define A_TLS_TX_CH_DBG_STEP_CTRL 0x44030 + +#define S_DBG_STEP_CTRL 1 +#define V_DBG_STEP_CTRL(x) ((x) << S_DBG_STEP_CTRL) +#define F_DBG_STEP_CTRL V_DBG_STEP_CTRL(1U) + +#define S_DBG_STEP_EN 0 +#define V_DBG_STEP_EN(x) ((x) << S_DBG_STEP_EN) +#define F_DBG_STEP_EN V_DBG_STEP_EN(1U) + +#define A_TLS_TX_DBG_SELL_DATA 0x44714 +#define A_TLS_TX_DBG_SELH_DATA 0x44718 +#define A_TLS_TX_DBG_SEL_CTRL 0x44730 +#define A_TLS_TX_GLOBAL_CONFIG 0x447c0 + +#define S_QUIC_EN 2 +#define V_QUIC_EN(x) ((x) << S_QUIC_EN) +#define F_QUIC_EN V_QUIC_EN(1U) + +#define S_IPSEC_IDX_UPD_EN 1 +#define V_IPSEC_IDX_UPD_EN(x) ((x) << S_IPSEC_IDX_UPD_EN) +#define F_IPSEC_IDX_UPD_EN V_IPSEC_IDX_UPD_EN(1U) + +#define S_IPSEC_IDX_CTL 0 +#define V_IPSEC_IDX_CTL(x) ((x) << S_IPSEC_IDX_CTL) +#define F_IPSEC_IDX_CTL V_IPSEC_IDX_CTL(1U) + +#define A_TLS_TX_CGEN 0x447f0 + +#define S_CHCGEN 0 +#define M_CHCGEN 0x3fU +#define V_CHCGEN(x) ((x) << S_CHCGEN) +#define G_CHCGEN(x) (((x) >> S_CHCGEN) & M_CHCGEN) + +#define A_TLS_TX_IND_ADDR 0x447f8 + +#define S_T7_3_ADDR 0 +#define M_T7_3_ADDR 0xfffU +#define V_T7_3_ADDR(x) ((x) << S_T7_3_ADDR) +#define G_T7_3_ADDR(x) (((x) >> S_T7_3_ADDR) & M_T7_3_ADDR) + +#define A_TLS_TX_IND_DATA 0x447fc +#define A_TLS_TX_CH_IND_ING_BYTE_CNT_LO 0x0 +#define A_TLS_TX_CH_IND_ING_BYTE_CNT_HI 0x1 +#define A_TLS_TX_CH_IND_ING_PKT_CNT 0x2 +#define A_TLS_TX_CH_IND_DISPATCH_PKT_CNT 0x4 +#define A_TLS_TX_CH_IND_ERROR_CNTS0 0x5 +#define A_TLS_TX_CH_IND_DEC_ERROR_CNTS 0x7 +#define A_TLS_TX_CH_IND_DBG_SPP_CFG 0x1f + +#define S_DIS_IF_ERR 11 +#define V_DIS_IF_ERR(x) ((x) << S_DIS_IF_ERR) +#define F_DIS_IF_ERR V_DIS_IF_ERR(1U) + +#define S_DIS_ERR_MSG 10 +#define V_DIS_ERR_MSG(x) ((x) << S_DIS_ERR_MSG) +#define F_DIS_ERR_MSG V_DIS_ERR_MSG(1U) + +#define S_DIS_BP_SEQF 9 +#define V_DIS_BP_SEQF(x) ((x) << S_DIS_BP_SEQF) +#define F_DIS_BP_SEQF V_DIS_BP_SEQF(1U) + +#define S_DIS_BP_LENF 8 +#define V_DIS_BP_LENF(x) ((x) << S_DIS_BP_LENF) +#define F_DIS_BP_LENF V_DIS_BP_LENF(1U) + +#define S_DIS_KEX_ERR 6 +#define V_DIS_KEX_ERR(x) ((x) << S_DIS_KEX_ERR) +#define F_DIS_KEX_ERR V_DIS_KEX_ERR(1U) + +#define S_CLR_STS 5 +#define V_CLR_STS(x) ((x) << S_CLR_STS) +#define F_CLR_STS V_CLR_STS(1U) + +#define S_TGL_CNT 4 +#define V_TGL_CNT(x) ((x) << S_TGL_CNT) +#define F_TGL_CNT V_TGL_CNT(1U) + +#define S_ENB_PAZ 3 +#define V_ENB_PAZ(x) ((x) << S_ENB_PAZ) +#define F_ENB_PAZ V_ENB_PAZ(1U) + +#define S_DIS_NOP 2 +#define V_DIS_NOP(x) ((x) << S_DIS_NOP) +#define F_DIS_NOP V_DIS_NOP(1U) + +#define S_DIS_CPL_ERR 1 +#define V_DIS_CPL_ERR(x) ((x) << S_DIS_CPL_ERR) +#define F_DIS_CPL_ERR V_DIS_CPL_ERR(1U) + +#define S_DIS_OFF_ERR 0 +#define V_DIS_OFF_ERR(x) ((x) << S_DIS_OFF_ERR) +#define F_DIS_OFF_ERR V_DIS_OFF_ERR(1U) + +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID0 0x20 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID1 0x21 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID2 0x22 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID3 0x23 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID4 0x24 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID5 0x25 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID6 0x26 +#define A_TLS_TX_CH_IND_DBG_SPP_PKTID7 0x27 +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W0 0x28 +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W1 0x29 +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W2 0x2a +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W3 0x2b +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W0 0x2c +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W1 0x2d +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W2 0x2e +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W3 0x2f +#define A_TLS_TX_CH_IND_DBG_SPP_SPR_ERR 0x30 +#define A_TLS_TX_CH_IND_DBG_SPP_SFO_BP 0x31 +#define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_M 0x32 +#define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_L 0x33 +#define A_TLS_TX_CH_IND_DBG_PKT_STAT 0x3f + +/* registers for module CRYPTO_1 */ +#define CRYPTO_1_BASE_ADDR 0x45000 + +/* registers for module CRYPTO_KEY */ +#define CRYPTO_KEY_BASE_ADDR 0x46000 + +#define A_CRYPTO_KEY_CONFIG 0x46000 + +#define S_ESNWIN 1 +#define M_ESNWIN 0x7U +#define V_ESNWIN(x) ((x) << S_ESNWIN) +#define G_ESNWIN(x) (((x) >> S_ESNWIN) & M_ESNWIN) + +#define S_INGKEY96 0 +#define V_INGKEY96(x) ((x) << S_INGKEY96) +#define F_INGKEY96 V_INGKEY96(1U) + +#define A_CRYPTO_KEY_RST 0x46004 + +#define S_CORE1RST 1 +#define V_CORE1RST(x) ((x) << S_CORE1RST) +#define F_CORE1RST V_CORE1RST(1U) + +#define S_CORE0RST 0 +#define V_CORE0RST(x) ((x) << S_CORE0RST) +#define F_CORE0RST V_CORE0RST(1U) + +#define A_CRYPTO_KEY_INT_ENABLE 0x46008 + +#define S_MA_FIFO_PERR 22 +#define V_MA_FIFO_PERR(x) ((x) << S_MA_FIFO_PERR) +#define F_MA_FIFO_PERR V_MA_FIFO_PERR(1U) + +#define S_MA_RSP_PERR 21 +#define V_MA_RSP_PERR(x) ((x) << S_MA_RSP_PERR) +#define F_MA_RSP_PERR V_MA_RSP_PERR(1U) + +#define S_ING_CACHE_DATA_PERR 19 +#define V_ING_CACHE_DATA_PERR(x) ((x) << S_ING_CACHE_DATA_PERR) +#define F_ING_CACHE_DATA_PERR V_ING_CACHE_DATA_PERR(1U) + +#define S_ING_CACHE_TAG_PERR 18 +#define V_ING_CACHE_TAG_PERR(x) ((x) << S_ING_CACHE_TAG_PERR) +#define F_ING_CACHE_TAG_PERR V_ING_CACHE_TAG_PERR(1U) + +#define S_LKP_KEY_REQ_PERR 17 +#define V_LKP_KEY_REQ_PERR(x) ((x) << S_LKP_KEY_REQ_PERR) +#define F_LKP_KEY_REQ_PERR V_LKP_KEY_REQ_PERR(1U) + +#define S_LKP_CLIP_TCAM_PERR 16 +#define V_LKP_CLIP_TCAM_PERR(x) ((x) << S_LKP_CLIP_TCAM_PERR) +#define F_LKP_CLIP_TCAM_PERR V_LKP_CLIP_TCAM_PERR(1U) + +#define S_LKP_MAIN_TCAM_PERR 15 +#define V_LKP_MAIN_TCAM_PERR(x) ((x) << S_LKP_MAIN_TCAM_PERR) +#define F_LKP_MAIN_TCAM_PERR V_LKP_MAIN_TCAM_PERR(1U) + +#define S_EGR_KEY_REQ_PERR 14 +#define V_EGR_KEY_REQ_PERR(x) ((x) << S_EGR_KEY_REQ_PERR) +#define F_EGR_KEY_REQ_PERR V_EGR_KEY_REQ_PERR(1U) + +#define S_EGR_CACHE_DATA_PERR 13 +#define V_EGR_CACHE_DATA_PERR(x) ((x) << S_EGR_CACHE_DATA_PERR) +#define F_EGR_CACHE_DATA_PERR V_EGR_CACHE_DATA_PERR(1U) + +#define S_EGR_CACHE_TAG_PERR 12 +#define V_EGR_CACHE_TAG_PERR(x) ((x) << S_EGR_CACHE_TAG_PERR) +#define F_EGR_CACHE_TAG_PERR V_EGR_CACHE_TAG_PERR(1U) + +#define S_CIM_PERR 11 +#define V_CIM_PERR(x) ((x) << S_CIM_PERR) +#define F_CIM_PERR V_CIM_PERR(1U) + +#define S_MA_INV_RSP_TAG 10 +#define V_MA_INV_RSP_TAG(x) ((x) << S_MA_INV_RSP_TAG) +#define F_MA_INV_RSP_TAG V_MA_INV_RSP_TAG(1U) + +#define S_ING_KEY_RANGE_ERR 9 +#define V_ING_KEY_RANGE_ERR(x) ((x) << S_ING_KEY_RANGE_ERR) +#define F_ING_KEY_RANGE_ERR V_ING_KEY_RANGE_ERR(1U) + +#define S_ING_MFIFO_OVFL 8 +#define V_ING_MFIFO_OVFL(x) ((x) << S_ING_MFIFO_OVFL) +#define F_ING_MFIFO_OVFL V_ING_MFIFO_OVFL(1U) + +#define S_LKP_REQ_OVFL 7 +#define V_LKP_REQ_OVFL(x) ((x) << S_LKP_REQ_OVFL) +#define F_LKP_REQ_OVFL V_LKP_REQ_OVFL(1U) + +#define S_EOK_WAIT_ERR 6 +#define V_EOK_WAIT_ERR(x) ((x) << S_EOK_WAIT_ERR) +#define F_EOK_WAIT_ERR V_EOK_WAIT_ERR(1U) + +#define S_EGR_KEY_RANGE_ERR 5 +#define V_EGR_KEY_RANGE_ERR(x) ((x) << S_EGR_KEY_RANGE_ERR) +#define F_EGR_KEY_RANGE_ERR V_EGR_KEY_RANGE_ERR(1U) + +#define S_EGR_MFIFO_OVFL 4 +#define V_EGR_MFIFO_OVFL(x) ((x) << S_EGR_MFIFO_OVFL) +#define F_EGR_MFIFO_OVFL V_EGR_MFIFO_OVFL(1U) + +#define S_SEQ_WRAP_HP_OVFL 3 +#define V_SEQ_WRAP_HP_OVFL(x) ((x) << S_SEQ_WRAP_HP_OVFL) +#define F_SEQ_WRAP_HP_OVFL V_SEQ_WRAP_HP_OVFL(1U) + +#define S_SEQ_WRAP_LP_OVFL 2 +#define V_SEQ_WRAP_LP_OVFL(x) ((x) << S_SEQ_WRAP_LP_OVFL) +#define F_SEQ_WRAP_LP_OVFL V_SEQ_WRAP_LP_OVFL(1U) + +#define S_EGR_SEQ_WRAP_HP 1 +#define V_EGR_SEQ_WRAP_HP(x) ((x) << S_EGR_SEQ_WRAP_HP) +#define F_EGR_SEQ_WRAP_HP V_EGR_SEQ_WRAP_HP(1U) + +#define S_EGR_SEQ_WRAP_LP 0 +#define V_EGR_SEQ_WRAP_LP(x) ((x) << S_EGR_SEQ_WRAP_LP) +#define F_EGR_SEQ_WRAP_LP V_EGR_SEQ_WRAP_LP(1U) + +#define A_CRYPTO_KEY_INT_CAUSE 0x4600c +#define A_CRYPTO_KEY_PERR_ENABLE 0x46010 +#define A_CRYPTO_KEY_EGR_SEQ_WRAP_LP_KEY_ID 0x46018 + +#define S_KEY_VALID 31 +#define V_KEY_VALID(x) ((x) << S_KEY_VALID) +#define F_KEY_VALID V_KEY_VALID(1U) + +#define S_KEY_ID 0 +#define M_KEY_ID 0x7fffffffU +#define V_KEY_ID(x) ((x) << S_KEY_ID) +#define G_KEY_ID(x) (((x) >> S_KEY_ID) & M_KEY_ID) + +#define A_CRYPTO_KEY_EGR_SEQ_WRAP_HP_KEY_ID 0x4601c +#define A_CRYPTO_KEY_TCAM_DATA0 0x46020 +#define A_CRYPTO_KEY_TCAM_DATA1 0x46024 +#define A_CRYPTO_KEY_TCAM_DATA2 0x46028 +#define A_CRYPTO_KEY_TCAM_DATA3 0x4602c +#define A_CRYPTO_KEY_TCAM_CTL 0x46030 + +#define S_SRCHMHIT 21 +#define V_SRCHMHIT(x) ((x) << S_SRCHMHIT) +#define F_SRCHMHIT V_SRCHMHIT(1U) + +#define S_T7_BUSY 20 +#define V_T7_BUSY(x) ((x) << S_T7_BUSY) +#define F_T7_BUSY V_T7_BUSY(1U) + +#define S_SRCHHIT 19 +#define V_SRCHHIT(x) ((x) << S_SRCHHIT) +#define F_SRCHHIT V_SRCHHIT(1U) + +#define S_IPVERSION 18 +#define V_IPVERSION(x) ((x) << S_IPVERSION) +#define F_IPVERSION V_IPVERSION(1U) + +#define S_BITSEL 17 +#define V_BITSEL(x) ((x) << S_BITSEL) +#define F_BITSEL V_BITSEL(1U) + +#define S_TCAMSEL 16 +#define V_TCAMSEL(x) ((x) << S_TCAMSEL) +#define F_TCAMSEL V_TCAMSEL(1U) + +#define S_CMDTYPE 14 +#define M_CMDTYPE 0x3U +#define V_CMDTYPE(x) ((x) << S_CMDTYPE) +#define G_CMDTYPE(x) (((x) >> S_CMDTYPE) & M_CMDTYPE) + +#define S_TCAMINDEX 0 +#define M_TCAMINDEX 0x3fffU +#define V_TCAMINDEX(x) ((x) << S_TCAMINDEX) +#define G_TCAMINDEX(x) (((x) >> S_TCAMINDEX) & M_TCAMINDEX) + +#define A_CRYPTO_KEY_TCAM_CONFIG 0x46034 + +#define S_T7_CLTCAMDEEPSLEEP_STAT 3 +#define V_T7_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_T7_CLTCAMDEEPSLEEP_STAT) +#define F_T7_CLTCAMDEEPSLEEP_STAT V_T7_CLTCAMDEEPSLEEP_STAT(1U) + +#define S_T7_TCAMDEEPSLEEP_STAT 2 +#define V_T7_TCAMDEEPSLEEP_STAT(x) ((x) << S_T7_TCAMDEEPSLEEP_STAT) +#define F_T7_TCAMDEEPSLEEP_STAT V_T7_TCAMDEEPSLEEP_STAT(1U) + +#define S_T7_CLTCAMDEEPSLEEP 1 +#define V_T7_CLTCAMDEEPSLEEP(x) ((x) << S_T7_CLTCAMDEEPSLEEP) +#define F_T7_CLTCAMDEEPSLEEP V_T7_CLTCAMDEEPSLEEP(1U) + +#define S_T7_TCAMDEEPSLEEP 0 +#define V_T7_TCAMDEEPSLEEP(x) ((x) << S_T7_TCAMDEEPSLEEP) +#define F_T7_TCAMDEEPSLEEP V_T7_TCAMDEEPSLEEP(1U) + +#define A_CRYPTO_KEY_TX_CMM_CONFIG 0x46040 +#define A_CRYPTO_KEY_TX_TNL_BASE 0x46044 +#define A_CRYPTO_KEY_TX_TRN_BASE 0x46048 +#define A_CRYPTO_KEY_TX_MAX_KEYS 0x4604c + +#define S_TNL_MAX 16 +#define M_TNL_MAX 0xffffU +#define V_TNL_MAX(x) ((x) << S_TNL_MAX) +#define G_TNL_MAX(x) (((x) >> S_TNL_MAX) & M_TNL_MAX) + +#define S_TRN_MAX 0 +#define M_TRN_MAX 0xffffU +#define V_TRN_MAX(x) ((x) << S_TRN_MAX) +#define G_TRN_MAX(x) (((x) >> S_TRN_MAX) & M_TRN_MAX) + +#define A_CRYPTO_KEY_TX_SEQ_STAT 0x46050 + +#define S_ESN 24 +#define V_ESN(x) ((x) << S_ESN) +#define F_ESN V_ESN(1U) + +#define S_SEQHI 20 +#define M_SEQHI 0xfU +#define V_SEQHI(x) ((x) << S_SEQHI) +#define G_SEQHI(x) (((x) >> S_SEQHI) & M_SEQHI) + +#define S_KEYID 0 +#define M_KEYID 0xfffffU +#define V_KEYID(x) ((x) << S_KEYID) +#define G_KEYID(x) (((x) >> S_KEYID) & M_KEYID) + +#define A_CRYPTO_KEY_RX_CMM_CONFIG 0x46060 +#define A_CRYPTO_KEY_RX_BASE 0x46064 +#define A_CRYPTO_KEY_RX_MAX_KEYS 0x46068 + +#define S_MAXKEYS 0 +#define M_MAXKEYS 0xffffU +#define V_MAXKEYS(x) ((x) << S_MAXKEYS) +#define G_MAXKEYS(x) (((x) >> S_MAXKEYS) & M_MAXKEYS) + +#define A_CRYPTO_KEY_CRYPTO_REVISION 0x4606c +#define A_CRYPTO_KEY_RX_SEQ_STAT 0x46070 +#define A_CRYPTO_KEY_TCAM_BIST_CTRL 0x46074 +#define A_CRYPTO_KEY_TCAM_BIST_CB_PASS 0x46078 +#define A_CRYPTO_KEY_TCAM_BIST_CB_BUSY 0x4607c +#define A_CRYPTO_KEY_DBG_SEL_CTRL 0x46080 + +#define S_SEL_OVR_EN 16 +#define V_SEL_OVR_EN(x) ((x) << S_SEL_OVR_EN) +#define F_SEL_OVR_EN V_SEL_OVR_EN(1U) + +#define S_T7_1_SELH 8 +#define M_T7_1_SELH 0xffU +#define V_T7_1_SELH(x) ((x) << S_T7_1_SELH) +#define G_T7_1_SELH(x) (((x) >> S_T7_1_SELH) & M_T7_1_SELH) + +#define S_T7_1_SELL 0 +#define M_T7_1_SELL 0xffU +#define V_T7_1_SELL(x) ((x) << S_T7_1_SELL) +#define G_T7_1_SELL(x) (((x) >> S_T7_1_SELL) & M_T7_1_SELL) + +#define A_CRYPTO_KEY_DBG_SELL_DATA 0x46084 +#define A_CRYPTO_KEY_DBG_SELH_DATA 0x46088 + +/* registers for module ARM */ +#define ARM_BASE_ADDR 0x47000 + +#define A_ARM_CPU_POR_RST 0x47000 + +#define S_CPUPORRSTN3 3 +#define V_CPUPORRSTN3(x) ((x) << S_CPUPORRSTN3) +#define F_CPUPORRSTN3 V_CPUPORRSTN3(1U) + +#define S_CPUPORRSTN2 2 +#define V_CPUPORRSTN2(x) ((x) << S_CPUPORRSTN2) +#define F_CPUPORRSTN2 V_CPUPORRSTN2(1U) + +#define S_CPUPORRSTN1 1 +#define V_CPUPORRSTN1(x) ((x) << S_CPUPORRSTN1) +#define F_CPUPORRSTN1 V_CPUPORRSTN1(1U) + +#define S_CPUPORRSTN0 0 +#define V_CPUPORRSTN0(x) ((x) << S_CPUPORRSTN0) +#define F_CPUPORRSTN0 V_CPUPORRSTN0(1U) + +#define A_ARM_CPU_CORE_RST 0x47004 + +#define S_CPUCORERSTN3 3 +#define V_CPUCORERSTN3(x) ((x) << S_CPUCORERSTN3) +#define F_CPUCORERSTN3 V_CPUCORERSTN3(1U) + +#define S_CPUCORERSTN2 2 +#define V_CPUCORERSTN2(x) ((x) << S_CPUCORERSTN2) +#define F_CPUCORERSTN2 V_CPUCORERSTN2(1U) + +#define S_CPUCORERSTN1 1 +#define V_CPUCORERSTN1(x) ((x) << S_CPUCORERSTN1) +#define F_CPUCORERSTN1 V_CPUCORERSTN1(1U) + +#define S_CPUCORERSTN0 0 +#define V_CPUCORERSTN0(x) ((x) << S_CPUCORERSTN0) +#define F_CPUCORERSTN0 V_CPUCORERSTN0(1U) + +#define A_ARM_CPU_WARM_RST_REQ 0x47008 + +#define S_CPUWARMRSTREQ3 3 +#define V_CPUWARMRSTREQ3(x) ((x) << S_CPUWARMRSTREQ3) +#define F_CPUWARMRSTREQ3 V_CPUWARMRSTREQ3(1U) + +#define S_CPUWARMRSTREQ2 2 +#define V_CPUWARMRSTREQ2(x) ((x) << S_CPUWARMRSTREQ2) +#define F_CPUWARMRSTREQ2 V_CPUWARMRSTREQ2(1U) + +#define S_CPUWARMRSTREQ1 1 +#define V_CPUWARMRSTREQ1(x) ((x) << S_CPUWARMRSTREQ1) +#define F_CPUWARMRSTREQ1 V_CPUWARMRSTREQ1(1U) + +#define S_CPUWARMRSTREQ0 0 +#define V_CPUWARMRSTREQ0(x) ((x) << S_CPUWARMRSTREQ0) +#define F_CPUWARMRSTREQ0 V_CPUWARMRSTREQ0(1U) + +#define A_ARM_CPU_L2_RST 0x4700c + +#define S_CPUL2RSTN 0 +#define V_CPUL2RSTN(x) ((x) << S_CPUL2RSTN) +#define F_CPUL2RSTN V_CPUL2RSTN(1U) + +#define A_ARM_CPU_L2_RST_DIS 0x47010 + +#define S_CPUL2RSTDISABLE 0 +#define V_CPUL2RSTDISABLE(x) ((x) << S_CPUL2RSTDISABLE) +#define F_CPUL2RSTDISABLE V_CPUL2RSTDISABLE(1U) + +#define A_ARM_CPU_PRESET_DBG 0x47014 + +#define S_CPUPRESETDBGN 0 +#define V_CPUPRESETDBGN(x) ((x) << S_CPUPRESETDBGN) +#define F_CPUPRESETDBGN V_CPUPRESETDBGN(1U) + +#define A_ARM_PL_DMA_AW_OFFSET 0x47018 + +#define S_PL_DMA_AW_OFFSET 0 +#define M_PL_DMA_AW_OFFSET 0x3fffffffU +#define V_PL_DMA_AW_OFFSET(x) ((x) << S_PL_DMA_AW_OFFSET) +#define G_PL_DMA_AW_OFFSET(x) (((x) >> S_PL_DMA_AW_OFFSET) & M_PL_DMA_AW_OFFSET) + +#define A_ARM_PL_DMA_AR_OFFSET 0x4701c + +#define S_PL_DMA_AR_OFFSET 0 +#define M_PL_DMA_AR_OFFSET 0x3fffffffU +#define V_PL_DMA_AR_OFFSET(x) ((x) << S_PL_DMA_AR_OFFSET) +#define G_PL_DMA_AR_OFFSET(x) (((x) >> S_PL_DMA_AR_OFFSET) & M_PL_DMA_AR_OFFSET) + +#define A_ARM_CPU_RESET_VECTOR_BASE_ADDR0 0x47020 +#define A_ARM_CPU_RESET_VECTOR_BASE_ADDR1 0x47024 + +#define S_CPURESETVECBA1 0 +#define M_CPURESETVECBA1 0x3ffU +#define V_CPURESETVECBA1(x) ((x) << S_CPURESETVECBA1) +#define G_CPURESETVECBA1(x) (((x) >> S_CPURESETVECBA1) & M_CPURESETVECBA1) + +#define A_ARM_CPU_PMU_EVENT 0x47028 + +#define S_CPUPMUEVENT 0 +#define M_CPUPMUEVENT 0x1ffffffU +#define V_CPUPMUEVENT(x) ((x) << S_CPUPMUEVENT) +#define G_CPUPMUEVENT(x) (((x) >> S_CPUPMUEVENT) & M_CPUPMUEVENT) + +#define A_ARM_DMA_RST 0x4702c + +#define S_DMA_PL_RST_N 0 +#define V_DMA_PL_RST_N(x) ((x) << S_DMA_PL_RST_N) +#define F_DMA_PL_RST_N V_DMA_PL_RST_N(1U) + +#define A_ARM_PLM_RID_CFG 0x4703c +#define A_ARM_PLM_EROM_CFG 0x47040 +#define A_ARM_PL_ARM_HDR_CFG 0x4704c +#define A_ARM_RC_INT_STATUS 0x4705c + +#define S_RC_INT_STATUS_REG 0 +#define M_RC_INT_STATUS_REG 0x3fU +#define V_RC_INT_STATUS_REG(x) ((x) << S_RC_INT_STATUS_REG) +#define G_RC_INT_STATUS_REG(x) (((x) >> S_RC_INT_STATUS_REG) & M_RC_INT_STATUS_REG) + +#define A_ARM_CPU_DBG_PWR_UP_REQ 0x47060 + +#define S_CPUDBGPWRUPREQ3 3 +#define V_CPUDBGPWRUPREQ3(x) ((x) << S_CPUDBGPWRUPREQ3) +#define F_CPUDBGPWRUPREQ3 V_CPUDBGPWRUPREQ3(1U) + +#define S_CPUDBGPWRUPREQ2 2 +#define V_CPUDBGPWRUPREQ2(x) ((x) << S_CPUDBGPWRUPREQ2) +#define F_CPUDBGPWRUPREQ2 V_CPUDBGPWRUPREQ2(1U) + +#define S_CPUDBGPWRUPREQ1 1 +#define V_CPUDBGPWRUPREQ1(x) ((x) << S_CPUDBGPWRUPREQ1) +#define F_CPUDBGPWRUPREQ1 V_CPUDBGPWRUPREQ1(1U) + +#define S_CPUDBGPWRUPREQ0 0 +#define V_CPUDBGPWRUPREQ0(x) ((x) << S_CPUDBGPWRUPREQ0) +#define F_CPUDBGPWRUPREQ0 V_CPUDBGPWRUPREQ0(1U) + +#define A_ARM_CPU_STANDBY_WFE_WFI 0x47064 + +#define S_CPUSTANDBYWFIL2 8 +#define V_CPUSTANDBYWFIL2(x) ((x) << S_CPUSTANDBYWFIL2) +#define F_CPUSTANDBYWFIL2 V_CPUSTANDBYWFIL2(1U) + +#define S_CPUSTANDBYWFI3 7 +#define V_CPUSTANDBYWFI3(x) ((x) << S_CPUSTANDBYWFI3) +#define F_CPUSTANDBYWFI3 V_CPUSTANDBYWFI3(1U) + +#define S_CPUSTANDBYWFI2 6 +#define V_CPUSTANDBYWFI2(x) ((x) << S_CPUSTANDBYWFI2) +#define F_CPUSTANDBYWFI2 V_CPUSTANDBYWFI2(1U) + +#define S_CPUSTANDBYWFI1 5 +#define V_CPUSTANDBYWFI1(x) ((x) << S_CPUSTANDBYWFI1) +#define F_CPUSTANDBYWFI1 V_CPUSTANDBYWFI1(1U) + +#define S_CPUSTANDBYWFI0 4 +#define V_CPUSTANDBYWFI0(x) ((x) << S_CPUSTANDBYWFI0) +#define F_CPUSTANDBYWFI0 V_CPUSTANDBYWFI0(1U) + +#define S_CPUSTANDBYWFE3 3 +#define V_CPUSTANDBYWFE3(x) ((x) << S_CPUSTANDBYWFE3) +#define F_CPUSTANDBYWFE3 V_CPUSTANDBYWFE3(1U) + +#define S_CPUSTANDBYWFE2 2 +#define V_CPUSTANDBYWFE2(x) ((x) << S_CPUSTANDBYWFE2) +#define F_CPUSTANDBYWFE2 V_CPUSTANDBYWFE2(1U) + +#define S_CPUSTANDBYWFE1 1 +#define V_CPUSTANDBYWFE1(x) ((x) << S_CPUSTANDBYWFE1) +#define F_CPUSTANDBYWFE1 V_CPUSTANDBYWFE1(1U) + +#define S_CPUSTANDBYWFE0 0 +#define V_CPUSTANDBYWFE0(x) ((x) << S_CPUSTANDBYWFE0) +#define F_CPUSTANDBYWFE0 V_CPUSTANDBYWFE0(1U) + +#define A_ARM_CPU_SMPEN 0x47068 + +#define S_CPUSMPEN3 3 +#define V_CPUSMPEN3(x) ((x) << S_CPUSMPEN3) +#define F_CPUSMPEN3 V_CPUSMPEN3(1U) + +#define S_CPUSMPEN2 2 +#define V_CPUSMPEN2(x) ((x) << S_CPUSMPEN2) +#define F_CPUSMPEN2 V_CPUSMPEN2(1U) + +#define S_CPUSMPEN1 1 +#define V_CPUSMPEN1(x) ((x) << S_CPUSMPEN1) +#define F_CPUSMPEN1 V_CPUSMPEN1(1U) + +#define S_CPUSMPEN0 0 +#define V_CPUSMPEN0(x) ((x) << S_CPUSMPEN0) +#define F_CPUSMPEN0 V_CPUSMPEN0(1U) + +#define A_ARM_CPU_QACTIVE 0x4706c + +#define S_CPUQACTIVE3 3 +#define V_CPUQACTIVE3(x) ((x) << S_CPUQACTIVE3) +#define F_CPUQACTIVE3 V_CPUQACTIVE3(1U) + +#define S_CPUQACTIVE2 2 +#define V_CPUQACTIVE2(x) ((x) << S_CPUQACTIVE2) +#define F_CPUQACTIVE2 V_CPUQACTIVE2(1U) + +#define S_CPUQACTIVE1 1 +#define V_CPUQACTIVE1(x) ((x) << S_CPUQACTIVE1) +#define F_CPUQACTIVE1 V_CPUQACTIVE1(1U) + +#define S_CPUQACTIVE0 0 +#define V_CPUQACTIVE0(x) ((x) << S_CPUQACTIVE0) +#define F_CPUQACTIVE0 V_CPUQACTIVE0(1U) + +#define A_ARM_CPU_QREQ 0x47070 + +#define S_CPUL2FLUSHREQ 5 +#define V_CPUL2FLUSHREQ(x) ((x) << S_CPUL2FLUSHREQ) +#define F_CPUL2FLUSHREQ V_CPUL2FLUSHREQ(1U) + +#define S_CPUL2QREQN 4 +#define V_CPUL2QREQN(x) ((x) << S_CPUL2QREQN) +#define F_CPUL2QREQN V_CPUL2QREQN(1U) + +#define S_CPUQREQ3N 3 +#define V_CPUQREQ3N(x) ((x) << S_CPUQREQ3N) +#define F_CPUQREQ3N V_CPUQREQ3N(1U) + +#define S_CPUQREQ2N 2 +#define V_CPUQREQ2N(x) ((x) << S_CPUQREQ2N) +#define F_CPUQREQ2N V_CPUQREQ2N(1U) + +#define S_CPUQREQ1N 1 +#define V_CPUQREQ1N(x) ((x) << S_CPUQREQ1N) +#define F_CPUQREQ1N V_CPUQREQ1N(1U) + +#define S_CPUQREQ0N 0 +#define V_CPUQREQ0N(x) ((x) << S_CPUQREQ0N) +#define F_CPUQREQ0N V_CPUQREQ0N(1U) + +#define A_ARM_CPU_QREQ_STATUS 0x47074 + +#define S_CPUL2FLUSHDONE 10 +#define V_CPUL2FLUSHDONE(x) ((x) << S_CPUL2FLUSHDONE) +#define F_CPUL2FLUSHDONE V_CPUL2FLUSHDONE(1U) + +#define S_CPUL2QDENY 9 +#define V_CPUL2QDENY(x) ((x) << S_CPUL2QDENY) +#define F_CPUL2QDENY V_CPUL2QDENY(1U) + +#define S_CPUL2QACCEPTN 8 +#define V_CPUL2QACCEPTN(x) ((x) << S_CPUL2QACCEPTN) +#define F_CPUL2QACCEPTN V_CPUL2QACCEPTN(1U) + +#define S_CPUQDENY3 7 +#define V_CPUQDENY3(x) ((x) << S_CPUQDENY3) +#define F_CPUQDENY3 V_CPUQDENY3(1U) + +#define S_CPUQDENY2 6 +#define V_CPUQDENY2(x) ((x) << S_CPUQDENY2) +#define F_CPUQDENY2 V_CPUQDENY2(1U) + +#define S_CPUQDENY1 5 +#define V_CPUQDENY1(x) ((x) << S_CPUQDENY1) +#define F_CPUQDENY1 V_CPUQDENY1(1U) + +#define S_CPUQDENY0 4 +#define V_CPUQDENY0(x) ((x) << S_CPUQDENY0) +#define F_CPUQDENY0 V_CPUQDENY0(1U) + +#define S_CPUQACCEPT3N 3 +#define V_CPUQACCEPT3N(x) ((x) << S_CPUQACCEPT3N) +#define F_CPUQACCEPT3N V_CPUQACCEPT3N(1U) + +#define S_CPUQACCEPT2N 2 +#define V_CPUQACCEPT2N(x) ((x) << S_CPUQACCEPT2N) +#define F_CPUQACCEPT2N V_CPUQACCEPT2N(1U) + +#define S_CPUQACCEPT1N 1 +#define V_CPUQACCEPT1N(x) ((x) << S_CPUQACCEPT1N) +#define F_CPUQACCEPT1N V_CPUQACCEPT1N(1U) + +#define S_CPUQACCEPT0N 0 +#define V_CPUQACCEPT0N(x) ((x) << S_CPUQACCEPT0N) +#define F_CPUQACCEPT0N V_CPUQACCEPT0N(1U) + +#define A_ARM_CPU_DBG_EN 0x47078 + +#define S_CPUDBGL1RSTDISABLE 28 +#define V_CPUDBGL1RSTDISABLE(x) ((x) << S_CPUDBGL1RSTDISABLE) +#define F_CPUDBGL1RSTDISABLE V_CPUDBGL1RSTDISABLE(1U) + +#define S_CPUDBGRSTREQ3 27 +#define V_CPUDBGRSTREQ3(x) ((x) << S_CPUDBGRSTREQ3) +#define F_CPUDBGRSTREQ3 V_CPUDBGRSTREQ3(1U) + +#define S_CPUDBGRSTREQ2 26 +#define V_CPUDBGRSTREQ2(x) ((x) << S_CPUDBGRSTREQ2) +#define F_CPUDBGRSTREQ2 V_CPUDBGRSTREQ2(1U) + +#define S_CPUDBGRSTREQ1 25 +#define V_CPUDBGRSTREQ1(x) ((x) << S_CPUDBGRSTREQ1) +#define F_CPUDBGRSTREQ1 V_CPUDBGRSTREQ1(1U) + +#define S_CPUDBGRSTREQ0 24 +#define V_CPUDBGRSTREQ0(x) ((x) << S_CPUDBGRSTREQ0) +#define F_CPUDBGRSTREQ0 V_CPUDBGRSTREQ0(1U) + +#define S_CPUDBGPWRDUP3 23 +#define V_CPUDBGPWRDUP3(x) ((x) << S_CPUDBGPWRDUP3) +#define F_CPUDBGPWRDUP3 V_CPUDBGPWRDUP3(1U) + +#define S_CPUDBGPWRDUP2 22 +#define V_CPUDBGPWRDUP2(x) ((x) << S_CPUDBGPWRDUP2) +#define F_CPUDBGPWRDUP2 V_CPUDBGPWRDUP2(1U) + +#define S_CPUDBGPWRDUP1 21 +#define V_CPUDBGPWRDUP1(x) ((x) << S_CPUDBGPWRDUP1) +#define F_CPUDBGPWRDUP1 V_CPUDBGPWRDUP1(1U) + +#define S_CPUDBGPWRDUP0 20 +#define V_CPUDBGPWRDUP0(x) ((x) << S_CPUDBGPWRDUP0) +#define F_CPUDBGPWRDUP0 V_CPUDBGPWRDUP0(1U) + +#define S_CPUEXTDBGREQ3 19 +#define V_CPUEXTDBGREQ3(x) ((x) << S_CPUEXTDBGREQ3) +#define F_CPUEXTDBGREQ3 V_CPUEXTDBGREQ3(1U) + +#define S_CPUEXTDBGREQ2 18 +#define V_CPUEXTDBGREQ2(x) ((x) << S_CPUEXTDBGREQ2) +#define F_CPUEXTDBGREQ2 V_CPUEXTDBGREQ2(1U) + +#define S_CPUEXTDBGREQ1 17 +#define V_CPUEXTDBGREQ1(x) ((x) << S_CPUEXTDBGREQ1) +#define F_CPUEXTDBGREQ1 V_CPUEXTDBGREQ1(1U) + +#define S_CPUEXTDBGREQ0 16 +#define V_CPUEXTDBGREQ0(x) ((x) << S_CPUEXTDBGREQ0) +#define F_CPUEXTDBGREQ0 V_CPUEXTDBGREQ0(1U) + +#define S_CPUSPNIDEN3 15 +#define V_CPUSPNIDEN3(x) ((x) << S_CPUSPNIDEN3) +#define F_CPUSPNIDEN3 V_CPUSPNIDEN3(1U) + +#define S_CPUSPNIDEN2 14 +#define V_CPUSPNIDEN2(x) ((x) << S_CPUSPNIDEN2) +#define F_CPUSPNIDEN2 V_CPUSPNIDEN2(1U) + +#define S_CPUSPNIDEN1 13 +#define V_CPUSPNIDEN1(x) ((x) << S_CPUSPNIDEN1) +#define F_CPUSPNIDEN1 V_CPUSPNIDEN1(1U) + +#define S_CPUSPNIDEN0 12 +#define V_CPUSPNIDEN0(x) ((x) << S_CPUSPNIDEN0) +#define F_CPUSPNIDEN0 V_CPUSPNIDEN0(1U) + +#define S_CPUSPDBGEN3 11 +#define V_CPUSPDBGEN3(x) ((x) << S_CPUSPDBGEN3) +#define F_CPUSPDBGEN3 V_CPUSPDBGEN3(1U) + +#define S_CPUSPDBGEN2 10 +#define V_CPUSPDBGEN2(x) ((x) << S_CPUSPDBGEN2) +#define F_CPUSPDBGEN2 V_CPUSPDBGEN2(1U) + +#define S_CPUSPDBGEN1 9 +#define V_CPUSPDBGEN1(x) ((x) << S_CPUSPDBGEN1) +#define F_CPUSPDBGEN1 V_CPUSPDBGEN1(1U) + +#define S_CPUSPDBGEN0 8 +#define V_CPUSPDBGEN0(x) ((x) << S_CPUSPDBGEN0) +#define F_CPUSPDBGEN0 V_CPUSPDBGEN0(1U) + +#define S_CPUNIDEN3 7 +#define V_CPUNIDEN3(x) ((x) << S_CPUNIDEN3) +#define F_CPUNIDEN3 V_CPUNIDEN3(1U) + +#define S_CPUNIDEN2 6 +#define V_CPUNIDEN2(x) ((x) << S_CPUNIDEN2) +#define F_CPUNIDEN2 V_CPUNIDEN2(1U) + +#define S_CPUNIDEN1 5 +#define V_CPUNIDEN1(x) ((x) << S_CPUNIDEN1) +#define F_CPUNIDEN1 V_CPUNIDEN1(1U) + +#define S_CPUNIDEN0 4 +#define V_CPUNIDEN0(x) ((x) << S_CPUNIDEN0) +#define F_CPUNIDEN0 V_CPUNIDEN0(1U) + +#define S_CPUDBGEN3 3 +#define V_CPUDBGEN3(x) ((x) << S_CPUDBGEN3) +#define F_CPUDBGEN3 V_CPUDBGEN3(1U) + +#define S_CPUDBGEN2 2 +#define V_CPUDBGEN2(x) ((x) << S_CPUDBGEN2) +#define F_CPUDBGEN2 V_CPUDBGEN2(1U) + +#define S_CPUDBGEN1 1 +#define V_CPUDBGEN1(x) ((x) << S_CPUDBGEN1) +#define F_CPUDBGEN1 V_CPUDBGEN1(1U) + +#define S_CPUDBGEN0 0 +#define V_CPUDBGEN0(x) ((x) << S_CPUDBGEN0) +#define F_CPUDBGEN0 V_CPUDBGEN0(1U) + +#define A_ARM_CPU_DBG_ACK 0x4707c + +#define S_CPUDBGNOPWRDWN3 11 +#define V_CPUDBGNOPWRDWN3(x) ((x) << S_CPUDBGNOPWRDWN3) +#define F_CPUDBGNOPWRDWN3 V_CPUDBGNOPWRDWN3(1U) + +#define S_CPUDBGNOPWRDWN2 10 +#define V_CPUDBGNOPWRDWN2(x) ((x) << S_CPUDBGNOPWRDWN2) +#define F_CPUDBGNOPWRDWN2 V_CPUDBGNOPWRDWN2(1U) + +#define S_CPUDBGNOPWRDWN1 9 +#define V_CPUDBGNOPWRDWN1(x) ((x) << S_CPUDBGNOPWRDWN1) +#define F_CPUDBGNOPWRDWN1 V_CPUDBGNOPWRDWN1(1U) + +#define S_CPUDBGNOPWRDWN0 8 +#define V_CPUDBGNOPWRDWN0(x) ((x) << S_CPUDBGNOPWRDWN0) +#define F_CPUDBGNOPWRDWN0 V_CPUDBGNOPWRDWN0(1U) + +#define S_CPUDGNRSTREQ3 7 +#define V_CPUDGNRSTREQ3(x) ((x) << S_CPUDGNRSTREQ3) +#define F_CPUDGNRSTREQ3 V_CPUDGNRSTREQ3(1U) + +#define S_CPUDGNRSTREQ2 6 +#define V_CPUDGNRSTREQ2(x) ((x) << S_CPUDGNRSTREQ2) +#define F_CPUDGNRSTREQ2 V_CPUDGNRSTREQ2(1U) + +#define S_CPUDGNRSTREQ1 5 +#define V_CPUDGNRSTREQ1(x) ((x) << S_CPUDGNRSTREQ1) +#define F_CPUDGNRSTREQ1 V_CPUDGNRSTREQ1(1U) + +#define S_CPUDGNRSTREQ0 4 +#define V_CPUDGNRSTREQ0(x) ((x) << S_CPUDGNRSTREQ0) +#define F_CPUDGNRSTREQ0 V_CPUDGNRSTREQ0(1U) + +#define S_CPUDBGACK3 3 +#define V_CPUDBGACK3(x) ((x) << S_CPUDBGACK3) +#define F_CPUDBGACK3 V_CPUDBGACK3(1U) + +#define S_CPUDBGACK2 2 +#define V_CPUDBGACK2(x) ((x) << S_CPUDBGACK2) +#define F_CPUDBGACK2 V_CPUDBGACK2(1U) + +#define S_CPUDBGACK1 1 +#define V_CPUDBGACK1(x) ((x) << S_CPUDBGACK1) +#define F_CPUDBGACK1 V_CPUDBGACK1(1U) + +#define S_CPUDBGACK0 0 +#define V_CPUDBGACK0(x) ((x) << S_CPUDBGACK0) +#define F_CPUDBGACK0 V_CPUDBGACK0(1U) + +#define A_ARM_CPU_PMU_SNAPSHOT_REQ 0x47080 + +#define S_CPUPMUSNAPSHOTREQ3 3 +#define V_CPUPMUSNAPSHOTREQ3(x) ((x) << S_CPUPMUSNAPSHOTREQ3) +#define F_CPUPMUSNAPSHOTREQ3 V_CPUPMUSNAPSHOTREQ3(1U) + +#define S_CPUPMUSNAPSHOTREQ2 2 +#define V_CPUPMUSNAPSHOTREQ2(x) ((x) << S_CPUPMUSNAPSHOTREQ2) +#define F_CPUPMUSNAPSHOTREQ2 V_CPUPMUSNAPSHOTREQ2(1U) + +#define S_CPUPMUSNAPSHOTREQ1 1 +#define V_CPUPMUSNAPSHOTREQ1(x) ((x) << S_CPUPMUSNAPSHOTREQ1) +#define F_CPUPMUSNAPSHOTREQ1 V_CPUPMUSNAPSHOTREQ1(1U) + +#define S_CPUPMUSNAPSHOTREQ0 0 +#define V_CPUPMUSNAPSHOTREQ0(x) ((x) << S_CPUPMUSNAPSHOTREQ0) +#define F_CPUPMUSNAPSHOTREQ0 V_CPUPMUSNAPSHOTREQ0(1U) + +#define A_ARM_CPU_PMU_SNAPSHOT_ACK 0x47084 + +#define S_CPUPMUSNAPSHOTACK3 3 +#define V_CPUPMUSNAPSHOTACK3(x) ((x) << S_CPUPMUSNAPSHOTACK3) +#define F_CPUPMUSNAPSHOTACK3 V_CPUPMUSNAPSHOTACK3(1U) + +#define S_CPUPMUSNAPSHOTACK2 2 +#define V_CPUPMUSNAPSHOTACK2(x) ((x) << S_CPUPMUSNAPSHOTACK2) +#define F_CPUPMUSNAPSHOTACK2 V_CPUPMUSNAPSHOTACK2(1U) + +#define S_CPUPMUSNAPSHOTACK1 1 +#define V_CPUPMUSNAPSHOTACK1(x) ((x) << S_CPUPMUSNAPSHOTACK1) +#define F_CPUPMUSNAPSHOTACK1 V_CPUPMUSNAPSHOTACK1(1U) + +#define S_CPUPMUSNAPSHOTACK0 0 +#define V_CPUPMUSNAPSHOTACK0(x) ((x) << S_CPUPMUSNAPSHOTACK0) +#define F_CPUPMUSNAPSHOTACK0 V_CPUPMUSNAPSHOTACK0(1U) + +#define A_ARM_EMMC_CTRL 0x47088 + +#define S_EMMC_DATA_P2 24 +#define M_EMMC_DATA_P2 0xffU +#define V_EMMC_DATA_P2(x) ((x) << S_EMMC_DATA_P2) +#define G_EMMC_DATA_P2(x) (((x) >> S_EMMC_DATA_P2) & M_EMMC_DATA_P2) + +#define S_EMMC_DATA_P1 16 +#define M_EMMC_DATA_P1 0xffU +#define V_EMMC_DATA_P1(x) ((x) << S_EMMC_DATA_P1) +#define G_EMMC_DATA_P1(x) (((x) >> S_EMMC_DATA_P1) & M_EMMC_DATA_P1) + +#define S_EMMC_CMD_P2 15 +#define V_EMMC_CMD_P2(x) ((x) << S_EMMC_CMD_P2) +#define F_EMMC_CMD_P2 V_EMMC_CMD_P2(1U) + +#define S_EMMC_CMD_P1 14 +#define V_EMMC_CMD_P1(x) ((x) << S_EMMC_CMD_P1) +#define F_EMMC_CMD_P1 V_EMMC_CMD_P1(1U) + +#define S_EMMC_RST_P2 13 +#define V_EMMC_RST_P2(x) ((x) << S_EMMC_RST_P2) +#define F_EMMC_RST_P2 V_EMMC_RST_P2(1U) + +#define S_EMMC_RST_P1 12 +#define V_EMMC_RST_P1(x) ((x) << S_EMMC_RST_P1) +#define F_EMMC_RST_P1 V_EMMC_RST_P1(1U) + +#define S_EMMC_GP_IN_P2 10 +#define M_EMMC_GP_IN_P2 0x3U +#define V_EMMC_GP_IN_P2(x) ((x) << S_EMMC_GP_IN_P2) +#define G_EMMC_GP_IN_P2(x) (((x) >> S_EMMC_GP_IN_P2) & M_EMMC_GP_IN_P2) + +#define S_EMMC_GP_IN_P1 8 +#define M_EMMC_GP_IN_P1 0x3U +#define V_EMMC_GP_IN_P1(x) ((x) << S_EMMC_GP_IN_P1) +#define G_EMMC_GP_IN_P1(x) (((x) >> S_EMMC_GP_IN_P1) & M_EMMC_GP_IN_P1) + +#define S_EMMC_CLK_SEL 0 +#define M_EMMC_CLK_SEL 0xffU +#define V_EMMC_CLK_SEL(x) ((x) << S_EMMC_CLK_SEL) +#define G_EMMC_CLK_SEL(x) (((x) >> S_EMMC_CLK_SEL) & M_EMMC_CLK_SEL) + +#define A_ARM_CPU_CFG_END_VINI_TE 0x4708c + +#define S_CPUSYSBARDISABLE 23 +#define V_CPUSYSBARDISABLE(x) ((x) << S_CPUSYSBARDISABLE) +#define F_CPUSYSBARDISABLE V_CPUSYSBARDISABLE(1U) + +#define S_CPUBROADCACHEMAIN 22 +#define V_CPUBROADCACHEMAIN(x) ((x) << S_CPUBROADCACHEMAIN) +#define F_CPUBROADCACHEMAIN V_CPUBROADCACHEMAIN(1U) + +#define S_CPUBROADOUTER 21 +#define V_CPUBROADOUTER(x) ((x) << S_CPUBROADOUTER) +#define F_CPUBROADOUTER V_CPUBROADOUTER(1U) + +#define S_CPUBROADINNER 20 +#define V_CPUBROADINNER(x) ((x) << S_CPUBROADINNER) +#define F_CPUBROADINNER V_CPUBROADINNER(1U) + +#define S_CPUCRYPTODISABLE3 19 +#define V_CPUCRYPTODISABLE3(x) ((x) << S_CPUCRYPTODISABLE3) +#define F_CPUCRYPTODISABLE3 V_CPUCRYPTODISABLE3(1U) + +#define S_CPUCRYPTODISABLE2 18 +#define V_CPUCRYPTODISABLE2(x) ((x) << S_CPUCRYPTODISABLE2) +#define F_CPUCRYPTODISABLE2 V_CPUCRYPTODISABLE2(1U) + +#define S_CPUCRYPTODISABLE1 17 +#define V_CPUCRYPTODISABLE1(x) ((x) << S_CPUCRYPTODISABLE1) +#define F_CPUCRYPTODISABLE1 V_CPUCRYPTODISABLE1(1U) + +#define S_CPUCRYPTODISABLE0 16 +#define V_CPUCRYPTODISABLE0(x) ((x) << S_CPUCRYPTODISABLE0) +#define F_CPUCRYPTODISABLE0 V_CPUCRYPTODISABLE0(1U) + +#define S_CPUAA64NAA323 15 +#define V_CPUAA64NAA323(x) ((x) << S_CPUAA64NAA323) +#define F_CPUAA64NAA323 V_CPUAA64NAA323(1U) + +#define S_CPUAA64NAA322 14 +#define V_CPUAA64NAA322(x) ((x) << S_CPUAA64NAA322) +#define F_CPUAA64NAA322 V_CPUAA64NAA322(1U) + +#define S_CPUAA64NAA321 13 +#define V_CPUAA64NAA321(x) ((x) << S_CPUAA64NAA321) +#define F_CPUAA64NAA321 V_CPUAA64NAA321(1U) + +#define S_CPUAA64NAA320 12 +#define V_CPUAA64NAA320(x) ((x) << S_CPUAA64NAA320) +#define F_CPUAA64NAA320 V_CPUAA64NAA320(1U) + +#define S_CPUCFGTE3 11 +#define V_CPUCFGTE3(x) ((x) << S_CPUCFGTE3) +#define F_CPUCFGTE3 V_CPUCFGTE3(1U) + +#define S_CPUCFGTE2 10 +#define V_CPUCFGTE2(x) ((x) << S_CPUCFGTE2) +#define F_CPUCFGTE2 V_CPUCFGTE2(1U) + +#define S_CPUCFGTE1 9 +#define V_CPUCFGTE1(x) ((x) << S_CPUCFGTE1) +#define F_CPUCFGTE1 V_CPUCFGTE1(1U) + +#define S_CPUCFGTE0 8 +#define V_CPUCFGTE0(x) ((x) << S_CPUCFGTE0) +#define F_CPUCFGTE0 V_CPUCFGTE0(1U) + +#define S_CPUVINIHI3 7 +#define V_CPUVINIHI3(x) ((x) << S_CPUVINIHI3) +#define F_CPUVINIHI3 V_CPUVINIHI3(1U) + +#define S_CPUVINIHI2 6 +#define V_CPUVINIHI2(x) ((x) << S_CPUVINIHI2) +#define F_CPUVINIHI2 V_CPUVINIHI2(1U) + +#define S_CPUVINIHI1 5 +#define V_CPUVINIHI1(x) ((x) << S_CPUVINIHI1) +#define F_CPUVINIHI1 V_CPUVINIHI1(1U) + +#define S_CPUVINIHI0 4 +#define V_CPUVINIHI0(x) ((x) << S_CPUVINIHI0) +#define F_CPUVINIHI0 V_CPUVINIHI0(1U) + +#define S_CPUCFGEND3 3 +#define V_CPUCFGEND3(x) ((x) << S_CPUCFGEND3) +#define F_CPUCFGEND3 V_CPUCFGEND3(1U) + +#define S_CPUCFGEND2 2 +#define V_CPUCFGEND2(x) ((x) << S_CPUCFGEND2) +#define F_CPUCFGEND2 V_CPUCFGEND2(1U) + +#define S_CPUCFGEND1 1 +#define V_CPUCFGEND1(x) ((x) << S_CPUCFGEND1) +#define F_CPUCFGEND1 V_CPUCFGEND1(1U) + +#define S_CPUCFGEND0 0 +#define V_CPUCFGEND0(x) ((x) << S_CPUCFGEND0) +#define F_CPUCFGEND0 V_CPUCFGEND0(1U) + +#define A_ARM_CPU_CP15_SDISABLE 0x47090 + +#define S_CPUCP15SDISABLE3 3 +#define V_CPUCP15SDISABLE3(x) ((x) << S_CPUCP15SDISABLE3) +#define F_CPUCP15SDISABLE3 V_CPUCP15SDISABLE3(1U) + +#define S_CPUCP15SDISABLE2 2 +#define V_CPUCP15SDISABLE2(x) ((x) << S_CPUCP15SDISABLE2) +#define F_CPUCP15SDISABLE2 V_CPUCP15SDISABLE2(1U) + +#define S_CPUCP15SDISABLE1 1 +#define V_CPUCP15SDISABLE1(x) ((x) << S_CPUCP15SDISABLE1) +#define F_CPUCP15SDISABLE1 V_CPUCP15SDISABLE1(1U) + +#define S_CPUCP15SDISABLE0 0 +#define V_CPUCP15SDISABLE0(x) ((x) << S_CPUCP15SDISABLE0) +#define F_CPUCP15SDISABLE0 V_CPUCP15SDISABLE0(1U) + +#define A_ARM_CPU_CLUSTER_ID_AFF 0x47094 + +#define S_CPUCLUSTERIDAFF2 8 +#define M_CPUCLUSTERIDAFF2 0xffU +#define V_CPUCLUSTERIDAFF2(x) ((x) << S_CPUCLUSTERIDAFF2) +#define G_CPUCLUSTERIDAFF2(x) (((x) >> S_CPUCLUSTERIDAFF2) & M_CPUCLUSTERIDAFF2) + +#define S_CPUCLUSTERIDAFF1 0 +#define M_CPUCLUSTERIDAFF1 0xffU +#define V_CPUCLUSTERIDAFF1(x) ((x) << S_CPUCLUSTERIDAFF1) +#define G_CPUCLUSTERIDAFF1(x) (((x) >> S_CPUCLUSTERIDAFF1) & M_CPUCLUSTERIDAFF1) + +#define A_ARM_CPU_CLK_CFG 0x47098 + +#define S_CPUACINACTIVEM 1 +#define V_CPUACINACTIVEM(x) ((x) << S_CPUACINACTIVEM) +#define F_CPUACINACTIVEM V_CPUACINACTIVEM(1U) + +#define S_CPUACLKENM 0 +#define V_CPUACLKENM(x) ((x) << S_CPUACLKENM) +#define F_CPUACLKENM V_CPUACLKENM(1U) + +#define A_ARM_NVME_DB_EMU_INT_CAUSE 0x4709c + +#define S_INVALID_BRESP 3 +#define V_INVALID_BRESP(x) ((x) << S_INVALID_BRESP) +#define F_INVALID_BRESP V_INVALID_BRESP(1U) + +#define S_DATA_LEN_OF 2 +#define V_DATA_LEN_OF(x) ((x) << S_DATA_LEN_OF) +#define F_DATA_LEN_OF V_DATA_LEN_OF(1U) + +#define S_INVALID_EMU_ADDR 1 +#define V_INVALID_EMU_ADDR(x) ((x) << S_INVALID_EMU_ADDR) +#define F_INVALID_EMU_ADDR V_INVALID_EMU_ADDR(1U) + +#define S_INVALID_AXI_ADDR_CFG 0 +#define V_INVALID_AXI_ADDR_CFG(x) ((x) << S_INVALID_AXI_ADDR_CFG) +#define F_INVALID_AXI_ADDR_CFG V_INVALID_AXI_ADDR_CFG(1U) + +#define A_ARM_CS_RST 0x470c0 + +#define S_ATCLKEN 9 +#define V_ATCLKEN(x) ((x) << S_ATCLKEN) +#define F_ATCLKEN V_ATCLKEN(1U) + +#define S_CXAPBICRSTN 8 +#define V_CXAPBICRSTN(x) ((x) << S_CXAPBICRSTN) +#define F_CXAPBICRSTN V_CXAPBICRSTN(1U) + +#define S_CSDBGEN 7 +#define V_CSDBGEN(x) ((x) << S_CSDBGEN) +#define F_CSDBGEN V_CSDBGEN(1U) + +#define S_JTAGNPOTRST 6 +#define V_JTAGNPOTRST(x) ((x) << S_JTAGNPOTRST) +#define F_JTAGNPOTRST V_JTAGNPOTRST(1U) + +#define S_JTAGNTRST 5 +#define V_JTAGNTRST(x) ((x) << S_JTAGNTRST) +#define F_JTAGNTRST V_JTAGNTRST(1U) + +#define S_PADDR31S0 4 +#define V_PADDR31S0(x) ((x) << S_PADDR31S0) +#define F_PADDR31S0 V_PADDR31S0(1U) + +#define S_CTICLKEN 3 +#define V_CTICLKEN(x) ((x) << S_CTICLKEN) +#define F_CTICLKEN V_CTICLKEN(1U) + +#define S_PCLKENDBG 2 +#define V_PCLKENDBG(x) ((x) << S_PCLKENDBG) +#define F_PCLKENDBG V_PCLKENDBG(1U) + +#define S_CPU_NIDEN 1 +#define V_CPU_NIDEN(x) ((x) << S_CPU_NIDEN) +#define F_CPU_NIDEN V_CPU_NIDEN(1U) + +#define S_CPU_DBGEN 0 +#define V_CPU_DBGEN(x) ((x) << S_CPU_DBGEN) +#define F_CPU_DBGEN V_CPU_DBGEN(1U) + +#define A_ARM_CS_ADDRL 0x470c4 +#define A_ARM_CS_ADDRH 0x470c8 +#define A_ARM_CS_DFT_CONTROL 0x470cc + +#define S_DFTMBISTADDR 5 +#define M_DFTMBISTADDR 0x7ffU +#define V_DFTMBISTADDR(x) ((x) << S_DFTMBISTADDR) +#define G_DFTMBISTADDR(x) (((x) >> S_DFTMBISTADDR) & M_DFTMBISTADDR) + +#define S_DFTMTESTON 3 +#define V_DFTMTESTON(x) ((x) << S_DFTMTESTON) +#define F_DFTMTESTON V_DFTMTESTON(1U) + +#define S_DFTMBISTCE 2 +#define V_DFTMBISTCE(x) ((x) << S_DFTMBISTCE) +#define F_DFTMBISTCE V_DFTMBISTCE(1U) + +#define S_DFTMBITWR 1 +#define V_DFTMBITWR(x) ((x) << S_DFTMBITWR) +#define F_DFTMBITWR V_DFTMBITWR(1U) + +#define S_DFTSE 0 +#define V_DFTSE(x) ((x) << S_DFTSE) +#define F_DFTSE V_DFTSE(1U) + +#define A_ARM_CS_DFT_IN 0x470d0 +#define A_ARM_CS_DFT_OUT 0x470d4 +#define A_ARM_CPU_EVENT_I 0x47100 + +#define S_CPUEVENTI 0 +#define V_CPUEVENTI(x) ((x) << S_CPUEVENTI) +#define F_CPUEVENTI V_CPUEVENTI(1U) + +#define A_ARM_CPU_EVENT_O 0x47104 + +#define S_CPUEVENTO 0 +#define V_CPUEVENTO(x) ((x) << S_CPUEVENTO) +#define F_CPUEVENTO V_CPUEVENTO(1U) + +#define A_ARM_CPU_CLR_EXMON_REQ 0x47108 + +#define S_CPUCLREXMONREQ 0 +#define V_CPUCLREXMONREQ(x) ((x) << S_CPUCLREXMONREQ) +#define F_CPUCLREXMONREQ V_CPUCLREXMONREQ(1U) + +#define A_ARM_CPU_CLR_EXMON_ACK 0x4710c + +#define S_CPUCLREXMONACK 0 +#define V_CPUCLREXMONACK(x) ((x) << S_CPUCLREXMONACK) +#define F_CPUCLREXMONACK V_CPUCLREXMONACK(1U) + +#define A_ARM_UART_MSTR_RXD 0x47110 +#define A_ARM_UART_MSTR_RXC 0x47114 + +#define S_UART_MSTR_RXC 0 +#define V_UART_MSTR_RXC(x) ((x) << S_UART_MSTR_RXC) +#define F_UART_MSTR_RXC V_UART_MSTR_RXC(1U) + +#define A_ARM_UART_MSTR_TXD 0x47118 +#define A_ARM_UART_MSTR_TXC 0x4711c + +#define S_T7_INT 1 +#define V_T7_INT(x) ((x) << S_T7_INT) +#define F_T7_INT V_T7_INT(1U) + +#define S_UART_MSTC_TXC 0 +#define V_UART_MSTC_TXC(x) ((x) << S_UART_MSTC_TXC) +#define F_UART_MSTC_TXC V_UART_MSTC_TXC(1U) + +#define A_ARM_UART_SLV_SEL 0x47120 + +#define S_UART_SLV_SEL 0 +#define V_UART_SLV_SEL(x) ((x) << S_UART_SLV_SEL) +#define F_UART_SLV_SEL V_UART_SLV_SEL(1U) + +#define A_ARM_CPU_PERIPH_BASE 0x47124 +#define A_ARM_PERR_INT_ENB2 0x47128 +#define A_ARM_PERR_ENABLE2 0x4712c +#define A_ARM_UART_CONFIG 0x47130 +#define A_ARM_UART_STAT 0x47134 + +#define S_RSV1 6 +#define M_RSV1 0x3ffffffU +#define V_RSV1(x) ((x) << S_RSV1) +#define G_RSV1(x) (((x) >> S_RSV1) & M_RSV1) + +#define S_RXFRMERR 5 +#define V_RXFRMERR(x) ((x) << S_RXFRMERR) +#define F_RXFRMERR V_RXFRMERR(1U) + +#define S_RXPARERR 4 +#define V_RXPARERR(x) ((x) << S_RXPARERR) +#define F_RXPARERR V_RXPARERR(1U) + +#define S_RXOVRN 3 +#define V_RXOVRN(x) ((x) << S_RXOVRN) +#define F_RXOVRN V_RXOVRN(1U) + +#define S_CTL_RXRDY 2 +#define V_CTL_RXRDY(x) ((x) << S_CTL_RXRDY) +#define F_CTL_RXRDY V_CTL_RXRDY(1U) + +#define S_TXOVRN 1 +#define V_TXOVRN(x) ((x) << S_TXOVRN) +#define F_TXOVRN V_TXOVRN(1U) + +#define S_CTL_TXRDY 0 +#define V_CTL_TXRDY(x) ((x) << S_CTL_TXRDY) +#define F_CTL_TXRDY V_CTL_TXRDY(1U) + +#define A_ARM_UART_TX_DATA 0x47138 + +#define S_TX_DATA 0 +#define M_TX_DATA 0xffU +#define V_TX_DATA(x) ((x) << S_TX_DATA) +#define G_TX_DATA(x) (((x) >> S_TX_DATA) & M_TX_DATA) + +#define A_ARM_UART_RX_DATA 0x4713c + +#define S_RX_DATA 0 +#define M_RX_DATA 0xffU +#define V_RX_DATA(x) ((x) << S_RX_DATA) +#define G_RX_DATA(x) (((x) >> S_RX_DATA) & M_RX_DATA) + +#define A_ARM_UART_DBG0 0x47140 +#define A_ARM_UART_DBG1 0x47144 +#define A_ARM_UART_DBG2 0x47148 +#define A_ARM_UART_DBG3 0x4714c +#define A_ARM_ARM_CPU_PC0 0x47150 +#define A_ARM_ARM_CPU_PC1 0x47154 +#define A_ARM_ARM_UART_INT_CAUSE 0x47158 + +#define S_RX_FIFO_NOT_EMPTY 1 +#define V_RX_FIFO_NOT_EMPTY(x) ((x) << S_RX_FIFO_NOT_EMPTY) +#define F_RX_FIFO_NOT_EMPTY V_RX_FIFO_NOT_EMPTY(1U) + +#define S_TX_FIFO_EMPTY 0 +#define V_TX_FIFO_EMPTY(x) ((x) << S_TX_FIFO_EMPTY) +#define F_TX_FIFO_EMPTY V_TX_FIFO_EMPTY(1U) + +#define A_ARM_ARM_UART_INT_EN 0x4715c + +#define S_RX_FIFO_INT_NOT_EMPTY 1 +#define V_RX_FIFO_INT_NOT_EMPTY(x) ((x) << S_RX_FIFO_INT_NOT_EMPTY) +#define F_RX_FIFO_INT_NOT_EMPTY V_RX_FIFO_INT_NOT_EMPTY(1U) + +#define S_TX_FIFO_INT_EMPTY 0 +#define V_TX_FIFO_INT_EMPTY(x) ((x) << S_TX_FIFO_INT_EMPTY) +#define F_TX_FIFO_INT_EMPTY V_TX_FIFO_INT_EMPTY(1U) + +#define A_ARM_ARM_UART_GPIO_SEL 0x47160 + +#define S_PC_SEL 1 +#define M_PC_SEL 0x7U +#define V_PC_SEL(x) ((x) << S_PC_SEL) +#define G_PC_SEL(x) (((x) >> S_PC_SEL) & M_PC_SEL) + +#define S_UART_GPIO_SEL 0 +#define V_UART_GPIO_SEL(x) ((x) << S_UART_GPIO_SEL) +#define F_UART_GPIO_SEL V_UART_GPIO_SEL(1U) + +#define A_ARM_ARM_SCRATCH_PAD0 0x47164 +#define A_ARM_ARM_SCRATCH_PAD1 0x47168 +#define A_ARM_ARM_SCRATCH_PAD2 0x4716c +#define A_ARM_PERR_INT_CAUSE0 0x47170 + +#define S_INIC_WRDATA_FIFO_PERR 31 +#define V_INIC_WRDATA_FIFO_PERR(x) ((x) << S_INIC_WRDATA_FIFO_PERR) +#define F_INIC_WRDATA_FIFO_PERR V_INIC_WRDATA_FIFO_PERR(1U) + +#define S_INIC_RDATA_FIFO_PERR 30 +#define V_INIC_RDATA_FIFO_PERR(x) ((x) << S_INIC_RDATA_FIFO_PERR) +#define F_INIC_RDATA_FIFO_PERR V_INIC_RDATA_FIFO_PERR(1U) + +#define S_MSI_MEM_PERR 29 +#define V_MSI_MEM_PERR(x) ((x) << S_MSI_MEM_PERR) +#define F_MSI_MEM_PERR V_MSI_MEM_PERR(1U) + +#define S_ARM_DB_SRAM_PERR 27 +#define M_ARM_DB_SRAM_PERR 0x3U +#define V_ARM_DB_SRAM_PERR(x) ((x) << S_ARM_DB_SRAM_PERR) +#define G_ARM_DB_SRAM_PERR(x) (((x) >> S_ARM_DB_SRAM_PERR) & M_ARM_DB_SRAM_PERR) + +#define S_EMMC_FIFOPARINT 26 +#define V_EMMC_FIFOPARINT(x) ((x) << S_EMMC_FIFOPARINT) +#define F_EMMC_FIFOPARINT V_EMMC_FIFOPARINT(1U) + +#define S_ICB_RAM_PERR 25 +#define V_ICB_RAM_PERR(x) ((x) << S_ICB_RAM_PERR) +#define F_ICB_RAM_PERR V_ICB_RAM_PERR(1U) + +#define S_MESS2AXI4_WRFIFO_PERR 24 +#define V_MESS2AXI4_WRFIFO_PERR(x) ((x) << S_MESS2AXI4_WRFIFO_PERR) +#define F_MESS2AXI4_WRFIFO_PERR V_MESS2AXI4_WRFIFO_PERR(1U) + +#define S_RC_WFIFO_OUTPERR 23 +#define V_RC_WFIFO_OUTPERR(x) ((x) << S_RC_WFIFO_OUTPERR) +#define F_RC_WFIFO_OUTPERR V_RC_WFIFO_OUTPERR(1U) + +#define S_RC_SRAM_PERR 21 +#define M_RC_SRAM_PERR 0x3U +#define V_RC_SRAM_PERR(x) ((x) << S_RC_SRAM_PERR) +#define G_RC_SRAM_PERR(x) (((x) >> S_RC_SRAM_PERR) & M_RC_SRAM_PERR) + +#define S_MSI_FIFO_PAR_ERR 20 +#define V_MSI_FIFO_PAR_ERR(x) ((x) << S_MSI_FIFO_PAR_ERR) +#define F_MSI_FIFO_PAR_ERR V_MSI_FIFO_PAR_ERR(1U) + +#define S_INIC2MA_INTFPERR 19 +#define V_INIC2MA_INTFPERR(x) ((x) << S_INIC2MA_INTFPERR) +#define F_INIC2MA_INTFPERR V_INIC2MA_INTFPERR(1U) + +#define S_RDATAFIFO0_PERR 18 +#define V_RDATAFIFO0_PERR(x) ((x) << S_RDATAFIFO0_PERR) +#define F_RDATAFIFO0_PERR V_RDATAFIFO0_PERR(1U) + +#define S_RDATAFIFO1_PERR 17 +#define V_RDATAFIFO1_PERR(x) ((x) << S_RDATAFIFO1_PERR) +#define F_RDATAFIFO1_PERR V_RDATAFIFO1_PERR(1U) + +#define S_WRDATAFIFO0_PERR 16 +#define V_WRDATAFIFO0_PERR(x) ((x) << S_WRDATAFIFO0_PERR) +#define F_WRDATAFIFO0_PERR V_WRDATAFIFO0_PERR(1U) + +#define S_WRDATAFIFO1_PERR 15 +#define V_WRDATAFIFO1_PERR(x) ((x) << S_WRDATAFIFO1_PERR) +#define F_WRDATAFIFO1_PERR V_WRDATAFIFO1_PERR(1U) + +#define S_WR512DATAFIFO0_PERR 14 +#define V_WR512DATAFIFO0_PERR(x) ((x) << S_WR512DATAFIFO0_PERR) +#define F_WR512DATAFIFO0_PERR V_WR512DATAFIFO0_PERR(1U) + +#define S_WR512DATAFIFO1_PERR 13 +#define V_WR512DATAFIFO1_PERR(x) ((x) << S_WR512DATAFIFO1_PERR) +#define F_WR512DATAFIFO1_PERR V_WR512DATAFIFO1_PERR(1U) + +#define S_ROBUFF_PARERR3 12 +#define V_ROBUFF_PARERR3(x) ((x) << S_ROBUFF_PARERR3) +#define F_ROBUFF_PARERR3 V_ROBUFF_PARERR3(1U) + +#define S_ROBUFF_PARERR2 11 +#define V_ROBUFF_PARERR2(x) ((x) << S_ROBUFF_PARERR2) +#define F_ROBUFF_PARERR2 V_ROBUFF_PARERR2(1U) + +#define S_ROBUFF_PARERR1 10 +#define V_ROBUFF_PARERR1(x) ((x) << S_ROBUFF_PARERR1) +#define F_ROBUFF_PARERR1 V_ROBUFF_PARERR1(1U) + +#define S_ROBUFF_PARERR0 9 +#define V_ROBUFF_PARERR0(x) ((x) << S_ROBUFF_PARERR0) +#define F_ROBUFF_PARERR0 V_ROBUFF_PARERR0(1U) + +#define S_MA2AXI_REQDATAPARERR 8 +#define V_MA2AXI_REQDATAPARERR(x) ((x) << S_MA2AXI_REQDATAPARERR) +#define F_MA2AXI_REQDATAPARERR V_MA2AXI_REQDATAPARERR(1U) + +#define S_MA2AXI_REQCTLPARERR 7 +#define V_MA2AXI_REQCTLPARERR(x) ((x) << S_MA2AXI_REQCTLPARERR) +#define F_MA2AXI_REQCTLPARERR V_MA2AXI_REQCTLPARERR(1U) + +#define S_MA_RSPPERR 6 +#define V_MA_RSPPERR(x) ((x) << S_MA_RSPPERR) +#define F_MA_RSPPERR V_MA_RSPPERR(1U) + +#define S_PCIE2MA_REQCTLPARERR 5 +#define V_PCIE2MA_REQCTLPARERR(x) ((x) << S_PCIE2MA_REQCTLPARERR) +#define F_PCIE2MA_REQCTLPARERR V_PCIE2MA_REQCTLPARERR(1U) + +#define S_PCIE2MA_REQDATAPARERR 4 +#define V_PCIE2MA_REQDATAPARERR(x) ((x) << S_PCIE2MA_REQDATAPARERR) +#define F_PCIE2MA_REQDATAPARERR V_PCIE2MA_REQDATAPARERR(1U) + +#define S_INIC2MA_REQCTLPARERR 3 +#define V_INIC2MA_REQCTLPARERR(x) ((x) << S_INIC2MA_REQCTLPARERR) +#define F_INIC2MA_REQCTLPARERR V_INIC2MA_REQCTLPARERR(1U) + +#define S_INIC2MA_REQDATAPARERR 2 +#define V_INIC2MA_REQDATAPARERR(x) ((x) << S_INIC2MA_REQDATAPARERR) +#define F_INIC2MA_REQDATAPARERR V_INIC2MA_REQDATAPARERR(1U) + +#define S_MA_RSPUE 1 +#define V_MA_RSPUE(x) ((x) << S_MA_RSPUE) +#define F_MA_RSPUE V_MA_RSPUE(1U) + +#define S_APB2PL_RSPDATAPERR 0 +#define V_APB2PL_RSPDATAPERR(x) ((x) << S_APB2PL_RSPDATAPERR) +#define F_APB2PL_RSPDATAPERR V_APB2PL_RSPDATAPERR(1U) + +#define A_ARM_PERR_INT_ENB0 0x47174 +#define A_ARM_SCRATCH_PAD3 0x47178 + +#define S_ECO_43187 31 +#define V_ECO_43187(x) ((x) << S_ECO_43187) +#define F_ECO_43187 V_ECO_43187(1U) + +#define S_TIMER_SEL 28 +#define M_TIMER_SEL 0x7U +#define V_TIMER_SEL(x) ((x) << S_TIMER_SEL) +#define G_TIMER_SEL(x) (((x) >> S_TIMER_SEL) & M_TIMER_SEL) + +#define S_TIMER 4 +#define M_TIMER 0xffffffU +#define V_TIMER(x) ((x) << S_TIMER) +#define G_TIMER(x) (((x) >> S_TIMER) & M_TIMER) + +#define S_T7_1_INT 0 +#define M_T7_1_INT 0x3U +#define V_T7_1_INT(x) ((x) << S_T7_1_INT) +#define G_T7_1_INT(x) (((x) >> S_T7_1_INT) & M_T7_1_INT) + +#define A_ARM_PERR_INT_CAUSE2 0x4717c + +#define S_INIC_WSTRB_FIFO_PERR 31 +#define V_INIC_WSTRB_FIFO_PERR(x) ((x) << S_INIC_WSTRB_FIFO_PERR) +#define F_INIC_WSTRB_FIFO_PERR V_INIC_WSTRB_FIFO_PERR(1U) + +#define S_INIC_BID_FIFO_PERR 30 +#define V_INIC_BID_FIFO_PERR(x) ((x) << S_INIC_BID_FIFO_PERR) +#define F_INIC_BID_FIFO_PERR V_INIC_BID_FIFO_PERR(1U) + +#define S_CC_SRAM_PKA_PERR 29 +#define V_CC_SRAM_PKA_PERR(x) ((x) << S_CC_SRAM_PKA_PERR) +#define F_CC_SRAM_PKA_PERR V_CC_SRAM_PKA_PERR(1U) + +#define S_CC_SRAM_SEC_PERR 28 +#define V_CC_SRAM_SEC_PERR(x) ((x) << S_CC_SRAM_SEC_PERR) +#define F_CC_SRAM_SEC_PERR V_CC_SRAM_SEC_PERR(1U) + +#define S_MESS2AXI4_PARERR 27 +#define V_MESS2AXI4_PARERR(x) ((x) << S_MESS2AXI4_PARERR) +#define F_MESS2AXI4_PARERR V_MESS2AXI4_PARERR(1U) + +#define S_CCI2INIC_INTF_PARERR 26 +#define V_CCI2INIC_INTF_PARERR(x) ((x) << S_CCI2INIC_INTF_PARERR) +#define F_CCI2INIC_INTF_PARERR V_CCI2INIC_INTF_PARERR(1U) + +#define A_ARM_MA2AXI_AW_ATTR 0x47180 + +#define S_AWLOCKR1 29 +#define V_AWLOCKR1(x) ((x) << S_AWLOCKR1) +#define F_AWLOCKR1 V_AWLOCKR1(1U) + +#define S_AWCACHER1 25 +#define M_AWCACHER1 0xfU +#define V_AWCACHER1(x) ((x) << S_AWCACHER1) +#define G_AWCACHER1(x) (((x) >> S_AWCACHER1) & M_AWCACHER1) + +#define S_AWPROTR1 21 +#define M_AWPROTR1 0xfU +#define V_AWPROTR1(x) ((x) << S_AWPROTR1) +#define G_AWPROTR1(x) (((x) >> S_AWPROTR1) & M_AWPROTR1) + +#define S_AWSNOOPR1 18 +#define M_AWSNOOPR1 0x7U +#define V_AWSNOOPR1(x) ((x) << S_AWSNOOPR1) +#define G_AWSNOOPR1(x) (((x) >> S_AWSNOOPR1) & M_AWSNOOPR1) + +#define S_AWDOMAINR1 16 +#define M_AWDOMAINR1 0x3U +#define V_AWDOMAINR1(x) ((x) << S_AWDOMAINR1) +#define G_AWDOMAINR1(x) (((x) >> S_AWDOMAINR1) & M_AWDOMAINR1) + +#define S_AWLOCKR0 13 +#define V_AWLOCKR0(x) ((x) << S_AWLOCKR0) +#define F_AWLOCKR0 V_AWLOCKR0(1U) + +#define S_AWCACHER0 9 +#define M_AWCACHER0 0xfU +#define V_AWCACHER0(x) ((x) << S_AWCACHER0) +#define G_AWCACHER0(x) (((x) >> S_AWCACHER0) & M_AWCACHER0) + +#define S_AWPROTR0 5 +#define M_AWPROTR0 0xfU +#define V_AWPROTR0(x) ((x) << S_AWPROTR0) +#define G_AWPROTR0(x) (((x) >> S_AWPROTR0) & M_AWPROTR0) + +#define S_AWSNOOPR0 2 +#define M_AWSNOOPR0 0x7U +#define V_AWSNOOPR0(x) ((x) << S_AWSNOOPR0) +#define G_AWSNOOPR0(x) (((x) >> S_AWSNOOPR0) & M_AWSNOOPR0) + +#define S_AWDOMAINR0 0 +#define M_AWDOMAINR0 0x3U +#define V_AWDOMAINR0(x) ((x) << S_AWDOMAINR0) +#define G_AWDOMAINR0(x) (((x) >> S_AWDOMAINR0) & M_AWDOMAINR0) + +#define A_ARM_MA2AXI_AR_ATTR 0x47184 + +#define S_ARLOCKR1 29 +#define V_ARLOCKR1(x) ((x) << S_ARLOCKR1) +#define F_ARLOCKR1 V_ARLOCKR1(1U) + +#define S_ARCACHER1 25 +#define M_ARCACHER1 0xfU +#define V_ARCACHER1(x) ((x) << S_ARCACHER1) +#define G_ARCACHER1(x) (((x) >> S_ARCACHER1) & M_ARCACHER1) + +#define S_ARPROTR1 21 +#define M_ARPROTR1 0xfU +#define V_ARPROTR1(x) ((x) << S_ARPROTR1) +#define G_ARPROTR1(x) (((x) >> S_ARPROTR1) & M_ARPROTR1) + +#define S_ARSNOOPR1 18 +#define M_ARSNOOPR1 0x7U +#define V_ARSNOOPR1(x) ((x) << S_ARSNOOPR1) +#define G_ARSNOOPR1(x) (((x) >> S_ARSNOOPR1) & M_ARSNOOPR1) + +#define S_ARDOMAINR1 16 +#define M_ARDOMAINR1 0x3U +#define V_ARDOMAINR1(x) ((x) << S_ARDOMAINR1) +#define G_ARDOMAINR1(x) (((x) >> S_ARDOMAINR1) & M_ARDOMAINR1) + +#define S_ARLOCKR0 13 +#define V_ARLOCKR0(x) ((x) << S_ARLOCKR0) +#define F_ARLOCKR0 V_ARLOCKR0(1U) + +#define S_ARCACHER0 9 +#define M_ARCACHER0 0xfU +#define V_ARCACHER0(x) ((x) << S_ARCACHER0) +#define G_ARCACHER0(x) (((x) >> S_ARCACHER0) & M_ARCACHER0) + +#define S_ARPROTR0 5 +#define M_ARPROTR0 0xfU +#define V_ARPROTR0(x) ((x) << S_ARPROTR0) +#define G_ARPROTR0(x) (((x) >> S_ARPROTR0) & M_ARPROTR0) + +#define S_ARSNOOPR0 2 +#define M_ARSNOOPR0 0x7U +#define V_ARSNOOPR0(x) ((x) << S_ARSNOOPR0) +#define G_ARSNOOPR0(x) (((x) >> S_ARSNOOPR0) & M_ARSNOOPR0) + +#define S_ARDOMAINR0 0 +#define M_ARDOMAINR0 0x3U +#define V_ARDOMAINR0(x) ((x) << S_ARDOMAINR0) +#define G_ARDOMAINR0(x) (((x) >> S_ARDOMAINR0) & M_ARDOMAINR0) + +#define A_ARM_MA2AXI_SNOOP_RGN 0x47188 + +#define S_SNOOP_END 16 +#define M_SNOOP_END 0xffffU +#define V_SNOOP_END(x) ((x) << S_SNOOP_END) +#define G_SNOOP_END(x) (((x) >> S_SNOOP_END) & M_SNOOP_END) + +#define S_SNOOP_START 0 +#define M_SNOOP_START 0xffffU +#define V_SNOOP_START(x) ((x) << S_SNOOP_START) +#define G_SNOOP_START(x) (((x) >> S_SNOOP_START) & M_SNOOP_START) + +#define A_ARM_PERIPHERAL_INT_CAUSE 0x4718c + +#define S_TIMER_INT 5 +#define V_TIMER_INT(x) ((x) << S_TIMER_INT) +#define F_TIMER_INT V_TIMER_INT(1U) + +#define S_NVME_INT 4 +#define V_NVME_INT(x) ((x) << S_NVME_INT) +#define F_NVME_INT V_NVME_INT(1U) + +#define S_EMMC_WAKEUP_INT 3 +#define V_EMMC_WAKEUP_INT(x) ((x) << S_EMMC_WAKEUP_INT) +#define F_EMMC_WAKEUP_INT V_EMMC_WAKEUP_INT(1U) + +#define S_EMMC_INT 2 +#define V_EMMC_INT(x) ((x) << S_EMMC_INT) +#define F_EMMC_INT V_EMMC_INT(1U) + +#define S_USB_MC_INT 1 +#define V_USB_MC_INT(x) ((x) << S_USB_MC_INT) +#define F_USB_MC_INT V_USB_MC_INT(1U) + +#define S_USB_DMA_INT 0 +#define V_USB_DMA_INT(x) ((x) << S_USB_DMA_INT) +#define F_USB_DMA_INT V_USB_DMA_INT(1U) + +#define A_ARM_SCRATCH_PAD4 0x47190 + +#define S_PAD4 15 +#define M_PAD4 0x1ffffU +#define V_PAD4(x) ((x) << S_PAD4) +#define G_PAD4(x) (((x) >> S_PAD4) & M_PAD4) + +#define S_ARM_DB_CNT 0 +#define M_ARM_DB_CNT 0x7fffU +#define V_ARM_DB_CNT(x) ((x) << S_ARM_DB_CNT) +#define G_ARM_DB_CNT(x) (((x) >> S_ARM_DB_CNT) & M_ARM_DB_CNT) + +#define A_ARM_SCRATCH_PAD5 0x47194 +#define A_ARM_SCRATCH_PAD6 0x47198 +#define A_ARM_SCRATCH_PAD7 0x4719c +#define A_ARM_NVME_DB_EMU_INDEX 0x471a0 +#define A_ARM_NVME_DB_EMU_REGION_CTL 0x471a4 + +#define S_WINDOW_EN 4 +#define V_WINDOW_EN(x) ((x) << S_WINDOW_EN) +#define F_WINDOW_EN V_WINDOW_EN(1U) + +#define S_RGN2_INT_EN 3 +#define V_RGN2_INT_EN(x) ((x) << S_RGN2_INT_EN) +#define F_RGN2_INT_EN V_RGN2_INT_EN(1U) + +#define S_RGN1_INT_EN 2 +#define V_RGN1_INT_EN(x) ((x) << S_RGN1_INT_EN) +#define F_RGN1_INT_EN V_RGN1_INT_EN(1U) + +#define S_QUEUE_EN 1 +#define V_QUEUE_EN(x) ((x) << S_QUEUE_EN) +#define F_QUEUE_EN V_QUEUE_EN(1U) + +#define S_RGN0_INT_EN 0 +#define V_RGN0_INT_EN(x) ((x) << S_RGN0_INT_EN) +#define F_RGN0_INT_EN V_RGN0_INT_EN(1U) + +#define A_ARM_NVME_DB_EMU_DEVICE_CTL 0x471a8 + +#define S_DEVICE_SIZE 8 +#define M_DEVICE_SIZE 0xfU +#define V_DEVICE_SIZE(x) ((x) << S_DEVICE_SIZE) +#define G_DEVICE_SIZE(x) (((x) >> S_DEVICE_SIZE) & M_DEVICE_SIZE) + +#define S_RGN1_SIZE 4 +#define M_RGN1_SIZE 0xfU +#define V_RGN1_SIZE(x) ((x) << S_RGN1_SIZE) +#define G_RGN1_SIZE(x) (((x) >> S_RGN1_SIZE) & M_RGN1_SIZE) + +#define S_RGN0_SIZE 0 +#define M_RGN0_SIZE 0xfU +#define V_RGN0_SIZE(x) ((x) << S_RGN0_SIZE) +#define G_RGN0_SIZE(x) (((x) >> S_RGN0_SIZE) & M_RGN0_SIZE) + +#define A_ARM_NVME_DB_EMU_WINDOW_START_ADDR 0x471b0 + +#define S_T7_4_ADDR 0 +#define M_T7_4_ADDR 0xfffffffU +#define V_T7_4_ADDR(x) ((x) << S_T7_4_ADDR) +#define G_T7_4_ADDR(x) (((x) >> S_T7_4_ADDR) & M_T7_4_ADDR) + +#define A_ARM_NVME_DB_EMU_WINDOW_END_ADDR 0x471b4 +#define A_ARM_NVME_DB_EMU_QBASE_ADDR 0x471b8 +#define A_ARM_NVME_DB_EMU_QUEUE_CID 0x471bc + +#define S_T7_CID 0 +#define M_T7_CID 0x1ffffU +#define V_T7_CID(x) ((x) << S_T7_CID) +#define G_T7_CID(x) (((x) >> S_T7_CID) & M_T7_CID) + +#define A_ARM_NVME_DB_EMU_QUEUE_CTL 0x471c0 + +#define S_INT_EN 27 +#define V_INT_EN(x) ((x) << S_INT_EN) +#define F_INT_EN V_INT_EN(1U) + +#define S_THRESHOLD 10 +#define M_THRESHOLD 0x1ffffU +#define V_THRESHOLD(x) ((x) << S_THRESHOLD) +#define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD) + +#define S_T7_1_SIZE 0 +#define M_T7_1_SIZE 0x3ffU +#define V_T7_1_SIZE(x) ((x) << S_T7_1_SIZE) +#define G_T7_1_SIZE(x) (((x) >> S_T7_1_SIZE) & M_T7_1_SIZE) + +#define A_ARM_NVME_DB_EMU_MSIX_ADDR_L 0x471c4 +#define A_ARM_NVME_DB_EMU_MSIX_ADDR_H 0x471c8 +#define A_ARM_NVME_DB_EMU_MSIX_OFFSET 0x471cc +#define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_L 0x471d0 +#define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_H 0x471d4 +#define A_ARM_NVME_DB_EMU_QUEUE_MSIX_OFFSET 0x471d8 +#define A_ARM_CERR_INT_CAUSE0 0x471dc + +#define S_WRDATA_FIFO0_CERR 31 +#define V_WRDATA_FIFO0_CERR(x) ((x) << S_WRDATA_FIFO0_CERR) +#define F_WRDATA_FIFO0_CERR V_WRDATA_FIFO0_CERR(1U) + +#define S_WRDATA_FIFO1_CERR 30 +#define V_WRDATA_FIFO1_CERR(x) ((x) << S_WRDATA_FIFO1_CERR) +#define F_WRDATA_FIFO1_CERR V_WRDATA_FIFO1_CERR(1U) + +#define S_WR512DATAFIFO0_CERR 29 +#define V_WR512DATAFIFO0_CERR(x) ((x) << S_WR512DATAFIFO0_CERR) +#define F_WR512DATAFIFO0_CERR V_WR512DATAFIFO0_CERR(1U) + +#define S_WR512DATAFIFO1_CERR 28 +#define V_WR512DATAFIFO1_CERR(x) ((x) << S_WR512DATAFIFO1_CERR) +#define F_WR512DATAFIFO1_CERR V_WR512DATAFIFO1_CERR(1U) + +#define S_RDATAFIFO0_CERR 27 +#define V_RDATAFIFO0_CERR(x) ((x) << S_RDATAFIFO0_CERR) +#define F_RDATAFIFO0_CERR V_RDATAFIFO0_CERR(1U) + +#define S_RDATAFIFO1_CERR 26 +#define V_RDATAFIFO1_CERR(x) ((x) << S_RDATAFIFO1_CERR) +#define F_RDATAFIFO1_CERR V_RDATAFIFO1_CERR(1U) + +#define S_ROBUFF_CORERR0 25 +#define V_ROBUFF_CORERR0(x) ((x) << S_ROBUFF_CORERR0) +#define F_ROBUFF_CORERR0 V_ROBUFF_CORERR0(1U) + +#define S_ROBUFF_CORERR1 24 +#define V_ROBUFF_CORERR1(x) ((x) << S_ROBUFF_CORERR1) +#define F_ROBUFF_CORERR1 V_ROBUFF_CORERR1(1U) + +#define S_ROBUFF_CORERR2 23 +#define V_ROBUFF_CORERR2(x) ((x) << S_ROBUFF_CORERR2) +#define F_ROBUFF_CORERR2 V_ROBUFF_CORERR2(1U) + +#define S_ROBUFF_CORERR3 22 +#define V_ROBUFF_CORERR3(x) ((x) << S_ROBUFF_CORERR3) +#define F_ROBUFF_CORERR3 V_ROBUFF_CORERR3(1U) + +#define S_MA2AXI_RSPDATACORERR 21 +#define V_MA2AXI_RSPDATACORERR(x) ((x) << S_MA2AXI_RSPDATACORERR) +#define F_MA2AXI_RSPDATACORERR V_MA2AXI_RSPDATACORERR(1U) + +#define S_RC_SRAM_CERR 19 +#define M_RC_SRAM_CERR 0x3U +#define V_RC_SRAM_CERR(x) ((x) << S_RC_SRAM_CERR) +#define G_RC_SRAM_CERR(x) (((x) >> S_RC_SRAM_CERR) & M_RC_SRAM_CERR) + +#define S_RC_WFIFO_OUTCERR 18 +#define V_RC_WFIFO_OUTCERR(x) ((x) << S_RC_WFIFO_OUTCERR) +#define F_RC_WFIFO_OUTCERR V_RC_WFIFO_OUTCERR(1U) + +#define S_RC_RSPFIFO_CERR 17 +#define V_RC_RSPFIFO_CERR(x) ((x) << S_RC_RSPFIFO_CERR) +#define F_RC_RSPFIFO_CERR V_RC_RSPFIFO_CERR(1U) + +#define S_MSI_MEM_CERR 16 +#define V_MSI_MEM_CERR(x) ((x) << S_MSI_MEM_CERR) +#define F_MSI_MEM_CERR V_MSI_MEM_CERR(1U) + +#define S_INIC_WRDATA_FIFO_CERR 15 +#define V_INIC_WRDATA_FIFO_CERR(x) ((x) << S_INIC_WRDATA_FIFO_CERR) +#define F_INIC_WRDATA_FIFO_CERR V_INIC_WRDATA_FIFO_CERR(1U) + +#define S_INIC_RDATAFIFO_CERR 14 +#define V_INIC_RDATAFIFO_CERR(x) ((x) << S_INIC_RDATAFIFO_CERR) +#define F_INIC_RDATAFIFO_CERR V_INIC_RDATAFIFO_CERR(1U) + +#define S_ARM_DB_SRAM_CERR 12 +#define M_ARM_DB_SRAM_CERR 0x3U +#define V_ARM_DB_SRAM_CERR(x) ((x) << S_ARM_DB_SRAM_CERR) +#define G_ARM_DB_SRAM_CERR(x) (((x) >> S_ARM_DB_SRAM_CERR) & M_ARM_DB_SRAM_CERR) + +#define S_ICB_RAM_CERR 11 +#define V_ICB_RAM_CERR(x) ((x) << S_ICB_RAM_CERR) +#define F_ICB_RAM_CERR V_ICB_RAM_CERR(1U) + +#define S_CC_SRAM_PKA_CERR 10 +#define V_CC_SRAM_PKA_CERR(x) ((x) << S_CC_SRAM_PKA_CERR) +#define F_CC_SRAM_PKA_CERR V_CC_SRAM_PKA_CERR(1U) + +#define S_CC_SRAM_SEC_CERR 9 +#define V_CC_SRAM_SEC_CERR(x) ((x) << S_CC_SRAM_SEC_CERR) +#define F_CC_SRAM_SEC_CERR V_CC_SRAM_SEC_CERR(1U) + +#define A_ARM_NVME_DB_EMU_QUEUE_CTL_2 0x471e0 + +#define S_INTERRUPT_CLEAR 0 +#define V_INTERRUPT_CLEAR(x) ((x) << S_INTERRUPT_CLEAR) +#define F_INTERRUPT_CLEAR V_INTERRUPT_CLEAR(1U) + +#define A_ARM_PERIPHERAL_INT_ENB 0x471e4 +#define A_ARM_CERR_INT_ENB0 0x471e8 +#define A_ARM_CPU_DBG_ROM_ADDR0 0x47200 + +#define S_CPUDBGROMADDR0 0 +#define M_CPUDBGROMADDR0 0xfffffU +#define V_CPUDBGROMADDR0(x) ((x) << S_CPUDBGROMADDR0) +#define G_CPUDBGROMADDR0(x) (((x) >> S_CPUDBGROMADDR0) & M_CPUDBGROMADDR0) + +#define A_ARM_CPU_DBG_ROM_ADDR1 0x47204 + +#define S_CPUDBGROMADDR1 0 +#define M_CPUDBGROMADDR1 0x3ffU +#define V_CPUDBGROMADDR1(x) ((x) << S_CPUDBGROMADDR1) +#define G_CPUDBGROMADDR1(x) (((x) >> S_CPUDBGROMADDR1) & M_CPUDBGROMADDR1) + +#define A_ARM_CPU_DBG_ROM_ADDR_VALID 0x47208 + +#define S_CPUDBGROMADDRVALID 0 +#define V_CPUDBGROMADDRVALID(x) ((x) << S_CPUDBGROMADDRVALID) +#define F_CPUDBGROMADDRVALID V_CPUDBGROMADDRVALID(1U) + +#define A_ARM_PERR_ENABLE0 0x4720c +#define A_ARM_SRAM2_WRITE_DATA3 0x47210 +#define A_ARM_SRAM2_READ_DATA3 0x4721c +#define A_ARM_CPU_DFT_CFG 0x47220 + +#define S_CPUMBISTREQ 11 +#define V_CPUMBISTREQ(x) ((x) << S_CPUMBISTREQ) +#define F_CPUMBISTREQ V_CPUMBISTREQ(1U) + +#define S_CPUMBISTRSTN 10 +#define V_CPUMBISTRSTN(x) ((x) << S_CPUMBISTRSTN) +#define F_CPUMBISTRSTN V_CPUMBISTRSTN(1U) + +#define S_CPUDFTDFTSE 9 +#define V_CPUDFTDFTSE(x) ((x) << S_CPUDFTDFTSE) +#define F_CPUDFTDFTSE V_CPUDFTDFTSE(1U) + +#define S_CPUDFTRSTDISABLE 8 +#define V_CPUDFTRSTDISABLE(x) ((x) << S_CPUDFTRSTDISABLE) +#define F_CPUDFTRSTDISABLE V_CPUDFTRSTDISABLE(1U) + +#define S_CPUDFTRAMDISABLE 7 +#define V_CPUDFTRAMDISABLE(x) ((x) << S_CPUDFTRAMDISABLE) +#define F_CPUDFTRAMDISABLE V_CPUDFTRAMDISABLE(1U) + +#define S_CPUDFTMCPDISABLE 6 +#define V_CPUDFTMCPDISABLE(x) ((x) << S_CPUDFTMCPDISABLE) +#define F_CPUDFTMCPDISABLE V_CPUDFTMCPDISABLE(1U) + +#define S_CPUDFTL2CLKDISABLE 5 +#define V_CPUDFTL2CLKDISABLE(x) ((x) << S_CPUDFTL2CLKDISABLE) +#define F_CPUDFTL2CLKDISABLE V_CPUDFTL2CLKDISABLE(1U) + +#define S_CPUDFTCLKDISABLE3 4 +#define V_CPUDFTCLKDISABLE3(x) ((x) << S_CPUDFTCLKDISABLE3) +#define F_CPUDFTCLKDISABLE3 V_CPUDFTCLKDISABLE3(1U) + +#define S_CPUDFTCLKDISABLE2 3 +#define V_CPUDFTCLKDISABLE2(x) ((x) << S_CPUDFTCLKDISABLE2) +#define F_CPUDFTCLKDISABLE2 V_CPUDFTCLKDISABLE2(1U) + +#define S_CPUDFTCLKDISABLE1 2 +#define V_CPUDFTCLKDISABLE1(x) ((x) << S_CPUDFTCLKDISABLE1) +#define F_CPUDFTCLKDISABLE1 V_CPUDFTCLKDISABLE1(1U) + +#define S_CPUDFTCLKDISABLE0 1 +#define V_CPUDFTCLKDISABLE0(x) ((x) << S_CPUDFTCLKDISABLE0) +#define F_CPUDFTCLKDISABLE0 V_CPUDFTCLKDISABLE0(1U) + +#define S_CPUDFTCLKBYPASS 0 +#define V_CPUDFTCLKBYPASS(x) ((x) << S_CPUDFTCLKBYPASS) +#define F_CPUDFTCLKBYPASS V_CPUDFTCLKBYPASS(1U) + +#define A_ARM_APB_CFG 0x47224 + +#define S_APB_CFG 0 +#define M_APB_CFG 0x3ffffU +#define V_APB_CFG(x) ((x) << S_APB_CFG) +#define G_APB_CFG(x) (((x) >> S_APB_CFG) & M_APB_CFG) + +#define A_ARM_EMMC_BUFS 0x47228 + +#define S_EMMC_BUFS_OEN 2 +#define M_EMMC_BUFS_OEN 0x3U +#define V_EMMC_BUFS_OEN(x) ((x) << S_EMMC_BUFS_OEN) +#define G_EMMC_BUFS_OEN(x) (((x) >> S_EMMC_BUFS_OEN) & M_EMMC_BUFS_OEN) + +#define S_EMMC_BUFS_I 0 +#define M_EMMC_BUFS_I 0x3U +#define V_EMMC_BUFS_I(x) ((x) << S_EMMC_BUFS_I) +#define G_EMMC_BUFS_I(x) (((x) >> S_EMMC_BUFS_I) & M_EMMC_BUFS_I) + +#define A_ARM_SWP_EN 0x4722c +#define A_ARM_ADB_PWR_DWN_REQ_N 0x47230 + +#define S_ADBPWRDWNREQN 0 +#define V_ADBPWRDWNREQN(x) ((x) << S_ADBPWRDWNREQN) +#define F_ADBPWRDWNREQN V_ADBPWRDWNREQN(1U) + +#define A_ARM_GIC_USER 0x47238 + +#define S_CPU_GIC_USER 0 +#define M_CPU_GIC_USER 0x7fU +#define V_CPU_GIC_USER(x) ((x) << S_CPU_GIC_USER) +#define G_CPU_GIC_USER(x) (((x) >> S_CPU_GIC_USER) & M_CPU_GIC_USER) + +#define A_ARM_DBPROC_SRAM_TH_ADDR 0x47240 + +#define S_DBPROC_TH_ADDR 0 +#define M_DBPROC_TH_ADDR 0x1ffU +#define V_DBPROC_TH_ADDR(x) ((x) << S_DBPROC_TH_ADDR) +#define G_DBPROC_TH_ADDR(x) (((x) >> S_DBPROC_TH_ADDR) & M_DBPROC_TH_ADDR) + +#define A_ARM_DBPROC_SRAM_TH_READ_DATA0 0x47244 +#define A_ARM_DBPROC_SRAM_TH_READ_DATA1 0x47248 +#define A_ARM_DBPROC_SRAM_TH_READ_DATA2 0x4724c +#define A_ARM_DBPROC_SRAM_TH_READ_DATA3 0x47250 +#define A_ARM_DBPROC_SRAM_TH_WR_DATA0 0x47254 +#define A_ARM_DBPROC_SRAM_TH_WR_DATA1 0x47258 +#define A_ARM_DBPROC_SRAM_TH_WR_DATA2 0x4725c +#define A_ARM_DBPROC_SRAM_TH_WR_DATA3 0x47260 +#define A_ARM_SWP_EN_2 0x47264 + +#define S_SWP_EN_2 0 +#define M_SWP_EN_2 0x3U +#define V_SWP_EN_2(x) ((x) << S_SWP_EN_2) +#define G_SWP_EN_2(x) (((x) >> S_SWP_EN_2) & M_SWP_EN_2) + +#define A_ARM_GIC_ERR 0x47268 + +#define S_ECC_FATAL 1 +#define V_ECC_FATAL(x) ((x) << S_ECC_FATAL) +#define F_ECC_FATAL V_ECC_FATAL(1U) + +#define S_AXIM_ERR 0 +#define V_AXIM_ERR(x) ((x) << S_AXIM_ERR) +#define F_AXIM_ERR V_AXIM_ERR(1U) + +#define A_ARM_CPU_STAT 0x4726c + +#define S_CPU_L2_QACTIVE 12 +#define V_CPU_L2_QACTIVE(x) ((x) << S_CPU_L2_QACTIVE) +#define F_CPU_L2_QACTIVE V_CPU_L2_QACTIVE(1U) + +#define S_WAKEUPM_O_ADB 11 +#define V_WAKEUPM_O_ADB(x) ((x) << S_WAKEUPM_O_ADB) +#define F_WAKEUPM_O_ADB V_WAKEUPM_O_ADB(1U) + +#define S_PWRQACTIVEM_ADB 10 +#define V_PWRQACTIVEM_ADB(x) ((x) << S_PWRQACTIVEM_ADB) +#define F_PWRQACTIVEM_ADB V_PWRQACTIVEM_ADB(1U) + +#define S_CLKQACTIVEM_ADB 9 +#define V_CLKQACTIVEM_ADB(x) ((x) << S_CLKQACTIVEM_ADB) +#define F_CLKQACTIVEM_ADB V_CLKQACTIVEM_ADB(1U) + +#define S_CLKQDENYM_ADB 8 +#define V_CLKQDENYM_ADB(x) ((x) << S_CLKQDENYM_ADB) +#define F_CLKQDENYM_ADB V_CLKQDENYM_ADB(1U) + +#define S_CLKQACCEPTNM_ADB 7 +#define V_CLKQACCEPTNM_ADB(x) ((x) << S_CLKQACCEPTNM_ADB) +#define F_CLKQACCEPTNM_ADB V_CLKQACCEPTNM_ADB(1U) + +#define S_WAKEUPS_O_ADB 6 +#define V_WAKEUPS_O_ADB(x) ((x) << S_WAKEUPS_O_ADB) +#define F_WAKEUPS_O_ADB V_WAKEUPS_O_ADB(1U) + +#define S_PWRQACTIVES_ADB 5 +#define V_PWRQACTIVES_ADB(x) ((x) << S_PWRQACTIVES_ADB) +#define F_PWRQACTIVES_ADB V_PWRQACTIVES_ADB(1U) + +#define S_CLKQACTIVES_ADB 4 +#define V_CLKQACTIVES_ADB(x) ((x) << S_CLKQACTIVES_ADB) +#define F_CLKQACTIVES_ADB V_CLKQACTIVES_ADB(1U) + +#define S_CLKQDENYS_ADB 3 +#define V_CLKQDENYS_ADB(x) ((x) << S_CLKQDENYS_ADB) +#define F_CLKQDENYS_ADB V_CLKQDENYS_ADB(1U) + +#define S_CLKQACCEPTNS_ADB 2 +#define V_CLKQACCEPTNS_ADB(x) ((x) << S_CLKQACCEPTNS_ADB) +#define F_CLKQACCEPTNS_ADB V_CLKQACCEPTNS_ADB(1U) + +#define S_PWRQDENYS_ADB 1 +#define V_PWRQDENYS_ADB(x) ((x) << S_PWRQDENYS_ADB) +#define F_PWRQDENYS_ADB V_PWRQDENYS_ADB(1U) + +#define S_PWRQACCEPTNS_ADB 0 +#define V_PWRQACCEPTNS_ADB(x) ((x) << S_PWRQACCEPTNS_ADB) +#define F_PWRQACCEPTNS_ADB V_PWRQACCEPTNS_ADB(1U) + +#define A_ARM_DEBUG_INT_WRITE_DATA 0x47270 + +#define S_DEBUG_INT_WRITE_DATA 0 +#define M_DEBUG_INT_WRITE_DATA 0xfffU +#define V_DEBUG_INT_WRITE_DATA(x) ((x) << S_DEBUG_INT_WRITE_DATA) +#define G_DEBUG_INT_WRITE_DATA(x) (((x) >> S_DEBUG_INT_WRITE_DATA) & M_DEBUG_INT_WRITE_DATA) + +#define A_ARM_DEBUG_INT_STAT 0x47274 + +#define S_DEBUG_INT_STATUS_REG 0 +#define M_DEBUG_INT_STATUS_REG 0xfffU +#define V_DEBUG_INT_STATUS_REG(x) ((x) << S_DEBUG_INT_STATUS_REG) +#define G_DEBUG_INT_STATUS_REG(x) (((x) >> S_DEBUG_INT_STATUS_REG) & M_DEBUG_INT_STATUS_REG) + +#define A_ARM_DEBUG_STAT 0x47278 + +#define S_ARM_DEBUG_STAT 0 +#define M_ARM_DEBUG_STAT 0x3fffU +#define V_ARM_DEBUG_STAT(x) ((x) << S_ARM_DEBUG_STAT) +#define G_ARM_DEBUG_STAT(x) (((x) >> S_ARM_DEBUG_STAT) & M_ARM_DEBUG_STAT) + +#define A_ARM_SIZE_STAT 0x4727c + +#define S_ARM_SIZE_STAT 0 +#define M_ARM_SIZE_STAT 0x3fffffffU +#define V_ARM_SIZE_STAT(x) ((x) << S_ARM_SIZE_STAT) +#define G_ARM_SIZE_STAT(x) (((x) >> S_ARM_SIZE_STAT) & M_ARM_SIZE_STAT) + +#define A_ARM_CCI_CFG0 0x47280 + +#define S_CCIBROADCASTCACHEMAINT 28 +#define M_CCIBROADCASTCACHEMAINT 0x7U +#define V_CCIBROADCASTCACHEMAINT(x) ((x) << S_CCIBROADCASTCACHEMAINT) +#define G_CCIBROADCASTCACHEMAINT(x) (((x) >> S_CCIBROADCASTCACHEMAINT) & M_CCIBROADCASTCACHEMAINT) + +#define S_CCISTRIPINGGRANULE 25 +#define M_CCISTRIPINGGRANULE 0x7U +#define V_CCISTRIPINGGRANULE(x) ((x) << S_CCISTRIPINGGRANULE) +#define G_CCISTRIPINGGRANULE(x) (((x) >> S_CCISTRIPINGGRANULE) & M_CCISTRIPINGGRANULE) + +#define S_CCIPERIPHBASE 0 +#define M_CCIPERIPHBASE 0x1ffffffU +#define V_CCIPERIPHBASE(x) ((x) << S_CCIPERIPHBASE) +#define G_CCIPERIPHBASE(x) (((x) >> S_CCIPERIPHBASE) & M_CCIPERIPHBASE) + +#define A_ARM_CCI_CFG1 0x47284 + +#define S_CCIDFTRSTDISABLE 18 +#define V_CCIDFTRSTDISABLE(x) ((x) << S_CCIDFTRSTDISABLE) +#define F_CCIDFTRSTDISABLE V_CCIDFTRSTDISABLE(1U) + +#define S_CCISPNIDEN 17 +#define V_CCISPNIDEN(x) ((x) << S_CCISPNIDEN) +#define F_CCISPNIDEN V_CCISPNIDEN(1U) + +#define S_CCINIDEN 16 +#define V_CCINIDEN(x) ((x) << S_CCINIDEN) +#define F_CCINIDEN V_CCINIDEN(1U) + +#define S_CCIACCHANNELN 11 +#define M_CCIACCHANNELN 0x1fU +#define V_CCIACCHANNELN(x) ((x) << S_CCIACCHANNELN) +#define G_CCIACCHANNELN(x) (((x) >> S_CCIACCHANNELN) & M_CCIACCHANNELN) + +#define S_CCIQOSOVERRIDE 6 +#define M_CCIQOSOVERRIDE 0x1fU +#define V_CCIQOSOVERRIDE(x) ((x) << S_CCIQOSOVERRIDE) +#define G_CCIQOSOVERRIDE(x) (((x) >> S_CCIQOSOVERRIDE) & M_CCIQOSOVERRIDE) + +#define S_CCIBUFFERABLEOVERRIDE 3 +#define M_CCIBUFFERABLEOVERRIDE 0x7U +#define V_CCIBUFFERABLEOVERRIDE(x) ((x) << S_CCIBUFFERABLEOVERRIDE) +#define G_CCIBUFFERABLEOVERRIDE(x) (((x) >> S_CCIBUFFERABLEOVERRIDE) & M_CCIBUFFERABLEOVERRIDE) + +#define S_CCIBARRIERTERMINATE 0 +#define M_CCIBARRIERTERMINATE 0x7U +#define V_CCIBARRIERTERMINATE(x) ((x) << S_CCIBARRIERTERMINATE) +#define G_CCIBARRIERTERMINATE(x) (((x) >> S_CCIBARRIERTERMINATE) & M_CCIBARRIERTERMINATE) + +#define A_ARM_CCI_CFG2 0x47288 + +#define S_CCIADDRMAP15 30 +#define M_CCIADDRMAP15 0x3U +#define V_CCIADDRMAP15(x) ((x) << S_CCIADDRMAP15) +#define G_CCIADDRMAP15(x) (((x) >> S_CCIADDRMAP15) & M_CCIADDRMAP15) + +#define S_CCIADDRMAP14 28 +#define M_CCIADDRMAP14 0x3U +#define V_CCIADDRMAP14(x) ((x) << S_CCIADDRMAP14) +#define G_CCIADDRMAP14(x) (((x) >> S_CCIADDRMAP14) & M_CCIADDRMAP14) + +#define S_CCIADDRMAP13 26 +#define M_CCIADDRMAP13 0x3U +#define V_CCIADDRMAP13(x) ((x) << S_CCIADDRMAP13) +#define G_CCIADDRMAP13(x) (((x) >> S_CCIADDRMAP13) & M_CCIADDRMAP13) + +#define S_CCIADDRMAP12 24 +#define M_CCIADDRMAP12 0x3U +#define V_CCIADDRMAP12(x) ((x) << S_CCIADDRMAP12) +#define G_CCIADDRMAP12(x) (((x) >> S_CCIADDRMAP12) & M_CCIADDRMAP12) + +#define S_CCIADDRMAP11 22 +#define M_CCIADDRMAP11 0x3U +#define V_CCIADDRMAP11(x) ((x) << S_CCIADDRMAP11) +#define G_CCIADDRMAP11(x) (((x) >> S_CCIADDRMAP11) & M_CCIADDRMAP11) + +#define S_CCIADDRMAP10 20 +#define M_CCIADDRMAP10 0x3U +#define V_CCIADDRMAP10(x) ((x) << S_CCIADDRMAP10) +#define G_CCIADDRMAP10(x) (((x) >> S_CCIADDRMAP10) & M_CCIADDRMAP10) + +#define S_CCIADDRMAP9 18 +#define M_CCIADDRMAP9 0x3U +#define V_CCIADDRMAP9(x) ((x) << S_CCIADDRMAP9) +#define G_CCIADDRMAP9(x) (((x) >> S_CCIADDRMAP9) & M_CCIADDRMAP9) + +#define S_CCIADDRMAP8 16 +#define M_CCIADDRMAP8 0x3U +#define V_CCIADDRMAP8(x) ((x) << S_CCIADDRMAP8) +#define G_CCIADDRMAP8(x) (((x) >> S_CCIADDRMAP8) & M_CCIADDRMAP8) + +#define S_CCIADDRMAP7 14 +#define M_CCIADDRMAP7 0x3U +#define V_CCIADDRMAP7(x) ((x) << S_CCIADDRMAP7) +#define G_CCIADDRMAP7(x) (((x) >> S_CCIADDRMAP7) & M_CCIADDRMAP7) + +#define S_CCIADDRMAP6 12 +#define M_CCIADDRMAP6 0x3U +#define V_CCIADDRMAP6(x) ((x) << S_CCIADDRMAP6) +#define G_CCIADDRMAP6(x) (((x) >> S_CCIADDRMAP6) & M_CCIADDRMAP6) + +#define S_CCIADDRMAP5 10 +#define M_CCIADDRMAP5 0x3U +#define V_CCIADDRMAP5(x) ((x) << S_CCIADDRMAP5) +#define G_CCIADDRMAP5(x) (((x) >> S_CCIADDRMAP5) & M_CCIADDRMAP5) + +#define S_CCIADDRMAP4 8 +#define M_CCIADDRMAP4 0x3U +#define V_CCIADDRMAP4(x) ((x) << S_CCIADDRMAP4) +#define G_CCIADDRMAP4(x) (((x) >> S_CCIADDRMAP4) & M_CCIADDRMAP4) + +#define S_CCIADDRMAP3 6 +#define M_CCIADDRMAP3 0x3U +#define V_CCIADDRMAP3(x) ((x) << S_CCIADDRMAP3) +#define G_CCIADDRMAP3(x) (((x) >> S_CCIADDRMAP3) & M_CCIADDRMAP3) + +#define S_CCIADDRMAP2 4 +#define M_CCIADDRMAP2 0x3U +#define V_CCIADDRMAP2(x) ((x) << S_CCIADDRMAP2) +#define G_CCIADDRMAP2(x) (((x) >> S_CCIADDRMAP2) & M_CCIADDRMAP2) + +#define S_CCIADDRMAP1 2 +#define M_CCIADDRMAP1 0x3U +#define V_CCIADDRMAP1(x) ((x) << S_CCIADDRMAP1) +#define G_CCIADDRMAP1(x) (((x) >> S_CCIADDRMAP1) & M_CCIADDRMAP1) + +#define S_CCIADDRMAP0 0 +#define M_CCIADDRMAP0 0x3U +#define V_CCIADDRMAP0(x) ((x) << S_CCIADDRMAP0) +#define G_CCIADDRMAP0(x) (((x) >> S_CCIADDRMAP0) & M_CCIADDRMAP0) + +#define A_ARM_CCI_STATUS 0x4728c + +#define S_CCICACTIVE 6 +#define V_CCICACTIVE(x) ((x) << S_CCICACTIVE) +#define F_CCICACTIVE V_CCICACTIVE(1U) + +#define S_CCICSYSACK 5 +#define V_CCICSYSACK(x) ((x) << S_CCICSYSACK) +#define F_CCICSYSACK V_CCICSYSACK(1U) + +#define S_CCINEVNTCNTOVERFLOW 0 +#define M_CCINEVNTCNTOVERFLOW 0x1fU +#define V_CCINEVNTCNTOVERFLOW(x) ((x) << S_CCINEVNTCNTOVERFLOW) +#define G_CCINEVNTCNTOVERFLOW(x) (((x) >> S_CCINEVNTCNTOVERFLOW) & M_CCINEVNTCNTOVERFLOW) + +#define A_ARM_CCIM_CCI_QVN_MASTER_CFG 0x47290 + +#define S_CCIVWREADYVN3M 20 +#define V_CCIVWREADYVN3M(x) ((x) << S_CCIVWREADYVN3M) +#define F_CCIVWREADYVN3M V_CCIVWREADYVN3M(1U) + +#define S_CCIVAWREADYVN3M 19 +#define V_CCIVAWREADYVN3M(x) ((x) << S_CCIVAWREADYVN3M) +#define F_CCIVAWREADYVN3M V_CCIVAWREADYVN3M(1U) + +#define S_CCIVARREADYVN3M 18 +#define V_CCIVARREADYVN3M(x) ((x) << S_CCIVARREADYVN3M) +#define F_CCIVARREADYVN3M V_CCIVARREADYVN3M(1U) + +#define S_CCIVWREADYVN2M 17 +#define V_CCIVWREADYVN2M(x) ((x) << S_CCIVWREADYVN2M) +#define F_CCIVWREADYVN2M V_CCIVWREADYVN2M(1U) + +#define S_CCIVAWREADYVN2M 16 +#define V_CCIVAWREADYVN2M(x) ((x) << S_CCIVAWREADYVN2M) +#define F_CCIVAWREADYVN2M V_CCIVAWREADYVN2M(1U) + +#define S_CCIVARREADYVN2M 15 +#define V_CCIVARREADYVN2M(x) ((x) << S_CCIVARREADYVN2M) +#define F_CCIVARREADYVN2M V_CCIVARREADYVN2M(1U) + +#define S_CCIVWREADYVN1M 14 +#define V_CCIVWREADYVN1M(x) ((x) << S_CCIVWREADYVN1M) +#define F_CCIVWREADYVN1M V_CCIVWREADYVN1M(1U) + +#define S_CCIVAWREADYVN1M 13 +#define V_CCIVAWREADYVN1M(x) ((x) << S_CCIVAWREADYVN1M) +#define F_CCIVAWREADYVN1M V_CCIVAWREADYVN1M(1U) + +#define S_CCIVARREADYVN1M 12 +#define V_CCIVARREADYVN1M(x) ((x) << S_CCIVARREADYVN1M) +#define F_CCIVARREADYVN1M V_CCIVARREADYVN1M(1U) + +#define S_CCIVWREADYVN0M 11 +#define V_CCIVWREADYVN0M(x) ((x) << S_CCIVWREADYVN0M) +#define F_CCIVWREADYVN0M V_CCIVWREADYVN0M(1U) + +#define S_CCIVAWREADYVN0M 10 +#define V_CCIVAWREADYVN0M(x) ((x) << S_CCIVAWREADYVN0M) +#define F_CCIVAWREADYVN0M V_CCIVAWREADYVN0M(1U) + +#define S_CCIVARREADYVN0M 9 +#define V_CCIVARREADYVN0M(x) ((x) << S_CCIVARREADYVN0M) +#define F_CCIVARREADYVN0M V_CCIVARREADYVN0M(1U) + +#define S_CCIQVNPREALLOCWM 5 +#define M_CCIQVNPREALLOCWM 0xfU +#define V_CCIQVNPREALLOCWM(x) ((x) << S_CCIQVNPREALLOCWM) +#define G_CCIQVNPREALLOCWM(x) (((x) >> S_CCIQVNPREALLOCWM) & M_CCIQVNPREALLOCWM) + +#define S_CCIQVNPREALLOCRM 1 +#define M_CCIQVNPREALLOCRM 0xfU +#define V_CCIQVNPREALLOCRM(x) ((x) << S_CCIQVNPREALLOCRM) +#define G_CCIQVNPREALLOCRM(x) (((x) >> S_CCIQVNPREALLOCRM) & M_CCIQVNPREALLOCRM) + +#define S_CCIQVNENABLEM 0 +#define V_CCIQVNENABLEM(x) ((x) << S_CCIQVNENABLEM) +#define F_CCIQVNENABLEM V_CCIQVNENABLEM(1U) + +#define A_ARM_CCIM_CCI_QVN_MASTER_STATUS 0x47294 + +#define S_CCIVWVALIDN3M 31 +#define V_CCIVWVALIDN3M(x) ((x) << S_CCIVWVALIDN3M) +#define F_CCIVWVALIDN3M V_CCIVWVALIDN3M(1U) + +#define S_CCIVAWVALIDN3M 30 +#define V_CCIVAWVALIDN3M(x) ((x) << S_CCIVAWVALIDN3M) +#define F_CCIVAWVALIDN3M V_CCIVAWVALIDN3M(1U) + +#define S_CCIVAWQOSN3M 29 +#define V_CCIVAWQOSN3M(x) ((x) << S_CCIVAWQOSN3M) +#define F_CCIVAWQOSN3M V_CCIVAWQOSN3M(1U) + +#define S_CCIVARVALIDN3M 28 +#define V_CCIVARVALIDN3M(x) ((x) << S_CCIVARVALIDN3M) +#define F_CCIVARVALIDN3M V_CCIVARVALIDN3M(1U) + +#define S_CCIVARQOSN3M 24 +#define M_CCIVARQOSN3M 0xfU +#define V_CCIVARQOSN3M(x) ((x) << S_CCIVARQOSN3M) +#define G_CCIVARQOSN3M(x) (((x) >> S_CCIVARQOSN3M) & M_CCIVARQOSN3M) + +#define S_CCIVWVALIDN2M 23 +#define V_CCIVWVALIDN2M(x) ((x) << S_CCIVWVALIDN2M) +#define F_CCIVWVALIDN2M V_CCIVWVALIDN2M(1U) + +#define S_CCIVAWVALIDN2M 22 +#define V_CCIVAWVALIDN2M(x) ((x) << S_CCIVAWVALIDN2M) +#define F_CCIVAWVALIDN2M V_CCIVAWVALIDN2M(1U) + +#define S_CCIVAWQOSN2M 21 +#define V_CCIVAWQOSN2M(x) ((x) << S_CCIVAWQOSN2M) +#define F_CCIVAWQOSN2M V_CCIVAWQOSN2M(1U) + +#define S_CCIVARVALIDN2M 20 +#define V_CCIVARVALIDN2M(x) ((x) << S_CCIVARVALIDN2M) +#define F_CCIVARVALIDN2M V_CCIVARVALIDN2M(1U) + +#define S_CCIVARQOSN2M 16 +#define M_CCIVARQOSN2M 0xfU +#define V_CCIVARQOSN2M(x) ((x) << S_CCIVARQOSN2M) +#define G_CCIVARQOSN2M(x) (((x) >> S_CCIVARQOSN2M) & M_CCIVARQOSN2M) + +#define S_CCIVWVALIDN1M 15 +#define V_CCIVWVALIDN1M(x) ((x) << S_CCIVWVALIDN1M) +#define F_CCIVWVALIDN1M V_CCIVWVALIDN1M(1U) + +#define S_CCIVAWVALIDN1M 14 +#define V_CCIVAWVALIDN1M(x) ((x) << S_CCIVAWVALIDN1M) +#define F_CCIVAWVALIDN1M V_CCIVAWVALIDN1M(1U) + +#define S_CCIVAWQOSN1M 13 +#define V_CCIVAWQOSN1M(x) ((x) << S_CCIVAWQOSN1M) +#define F_CCIVAWQOSN1M V_CCIVAWQOSN1M(1U) + +#define S_CCIVARVALIDN1M 12 +#define V_CCIVARVALIDN1M(x) ((x) << S_CCIVARVALIDN1M) +#define F_CCIVARVALIDN1M V_CCIVARVALIDN1M(1U) + +#define S_CCIVARQOSN1M 8 +#define M_CCIVARQOSN1M 0xfU +#define V_CCIVARQOSN1M(x) ((x) << S_CCIVARQOSN1M) +#define G_CCIVARQOSN1M(x) (((x) >> S_CCIVARQOSN1M) & M_CCIVARQOSN1M) + +#define S_CCIVWVALIDN0M 7 +#define V_CCIVWVALIDN0M(x) ((x) << S_CCIVWVALIDN0M) +#define F_CCIVWVALIDN0M V_CCIVWVALIDN0M(1U) + +#define S_CCIVAWVALIDN0M 6 +#define V_CCIVAWVALIDN0M(x) ((x) << S_CCIVAWVALIDN0M) +#define F_CCIVAWVALIDN0M V_CCIVAWVALIDN0M(1U) + +#define S_CCIVAWQOSN0M 5 +#define V_CCIVAWQOSN0M(x) ((x) << S_CCIVAWQOSN0M) +#define F_CCIVAWQOSN0M V_CCIVAWQOSN0M(1U) + +#define S_CCIVARVALIDN0M 4 +#define V_CCIVARVALIDN0M(x) ((x) << S_CCIVARVALIDN0M) +#define F_CCIVARVALIDN0M V_CCIVARVALIDN0M(1U) + +#define S_CCIVARQOSN0M 0 +#define M_CCIVARQOSN0M 0xfU +#define V_CCIVARQOSN0M(x) ((x) << S_CCIVARQOSN0M) +#define G_CCIVARQOSN0M(x) (((x) >> S_CCIVARQOSN0M) & M_CCIVARQOSN0M) + +#define A_ARM_CCIS_CCI_QVN_SLAVE_CFG 0x472d0 + +#define S_CCIQVNVNETS 0 +#define M_CCIQVNVNETS 0x3U +#define V_CCIQVNVNETS(x) ((x) << S_CCIQVNVNETS) +#define G_CCIQVNVNETS(x) (((x) >> S_CCIQVNVNETS) & M_CCIQVNVNETS) + +#define A_ARM_CCIS_CCI_QVN_SLAVE_STATUS 0x472d4 + +#define S_CCIEVNTAWQOS 4 +#define M_CCIEVNTAWQOS 0xfU +#define V_CCIEVNTAWQOS(x) ((x) << S_CCIEVNTAWQOS) +#define G_CCIEVNTAWQOS(x) (((x) >> S_CCIEVNTAWQOS) & M_CCIEVNTAWQOS) + +#define S_CCIEVNTARQOS 0 +#define M_CCIEVNTARQOS 0xfU +#define V_CCIEVNTARQOS(x) ((x) << S_CCIEVNTARQOS) +#define G_CCIEVNTARQOS(x) (((x) >> S_CCIEVNTARQOS) & M_CCIEVNTARQOS) + +#define A_ARM_CCI_EVNTBUS 0x47300 +#define A_ARM_CCI_RST_N 0x47318 + +#define S_CCIRSTN 0 +#define V_CCIRSTN(x) ((x) << S_CCIRSTN) +#define F_CCIRSTN V_CCIRSTN(1U) + +#define A_ARM_CCI_CSYREQ 0x4731c + +#define S_CCICSYSREQ 0 +#define V_CCICSYSREQ(x) ((x) << S_CCICSYSREQ) +#define F_CCICSYSREQ V_CCICSYSREQ(1U) + +#define A_ARM_CCI_TR_DEBUGS0 0x47320 + +#define S_CCIS0RCNT 24 +#define M_CCIS0RCNT 0xffU +#define V_CCIS0RCNT(x) ((x) << S_CCIS0RCNT) +#define G_CCIS0RCNT(x) (((x) >> S_CCIS0RCNT) & M_CCIS0RCNT) + +#define S_CCIS0ARCNT 16 +#define M_CCIS0ARCNT 0xffU +#define V_CCIS0ARCNT(x) ((x) << S_CCIS0ARCNT) +#define G_CCIS0ARCNT(x) (((x) >> S_CCIS0ARCNT) & M_CCIS0ARCNT) + +#define S_CCIS0WCNT 8 +#define M_CCIS0WCNT 0xffU +#define V_CCIS0WCNT(x) ((x) << S_CCIS0WCNT) +#define G_CCIS0WCNT(x) (((x) >> S_CCIS0WCNT) & M_CCIS0WCNT) + +#define S_CCIS0AWCNT 0 +#define M_CCIS0AWCNT 0xffU +#define V_CCIS0AWCNT(x) ((x) << S_CCIS0AWCNT) +#define G_CCIS0AWCNT(x) (((x) >> S_CCIS0AWCNT) & M_CCIS0AWCNT) + +#define A_ARM_CCI_TR_DEBUGS1 0x47324 + +#define S_CCIS1RCNT 24 +#define M_CCIS1RCNT 0xffU +#define V_CCIS1RCNT(x) ((x) << S_CCIS1RCNT) +#define G_CCIS1RCNT(x) (((x) >> S_CCIS1RCNT) & M_CCIS1RCNT) + +#define S_CCIS1ARCNT 16 +#define M_CCIS1ARCNT 0xffU +#define V_CCIS1ARCNT(x) ((x) << S_CCIS1ARCNT) +#define G_CCIS1ARCNT(x) (((x) >> S_CCIS1ARCNT) & M_CCIS1ARCNT) + +#define S_CCIS1WCNT 8 +#define M_CCIS1WCNT 0xffU +#define V_CCIS1WCNT(x) ((x) << S_CCIS1WCNT) +#define G_CCIS1WCNT(x) (((x) >> S_CCIS1WCNT) & M_CCIS1WCNT) + +#define S_CCIS1AWCNT 0 +#define M_CCIS1AWCNT 0xffU +#define V_CCIS1AWCNT(x) ((x) << S_CCIS1AWCNT) +#define G_CCIS1AWCNT(x) (((x) >> S_CCIS1AWCNT) & M_CCIS1AWCNT) + +#define A_ARM_CCI_TR_DEBUGS2 0x47328 + +#define S_CCIS2RCNT 24 +#define M_CCIS2RCNT 0xffU +#define V_CCIS2RCNT(x) ((x) << S_CCIS2RCNT) +#define G_CCIS2RCNT(x) (((x) >> S_CCIS2RCNT) & M_CCIS2RCNT) + +#define S_CCIS2ARCNT 16 +#define M_CCIS2ARCNT 0xffU +#define V_CCIS2ARCNT(x) ((x) << S_CCIS2ARCNT) +#define G_CCIS2ARCNT(x) (((x) >> S_CCIS2ARCNT) & M_CCIS2ARCNT) + +#define S_CCIS2WCNT 8 +#define M_CCIS2WCNT 0xffU +#define V_CCIS2WCNT(x) ((x) << S_CCIS2WCNT) +#define G_CCIS2WCNT(x) (((x) >> S_CCIS2WCNT) & M_CCIS2WCNT) + +#define S_CCIS2AWCNT 0 +#define M_CCIS2AWCNT 0xffU +#define V_CCIS2AWCNT(x) ((x) << S_CCIS2AWCNT) +#define G_CCIS2AWCNT(x) (((x) >> S_CCIS2AWCNT) & M_CCIS2AWCNT) + +#define A_ARM_CCI_TR_DEBUGS3 0x4732c + +#define S_CCIS3RCNT 24 +#define M_CCIS3RCNT 0xffU +#define V_CCIS3RCNT(x) ((x) << S_CCIS3RCNT) +#define G_CCIS3RCNT(x) (((x) >> S_CCIS3RCNT) & M_CCIS3RCNT) + +#define S_CCIS3ARCNT 16 +#define M_CCIS3ARCNT 0xffU +#define V_CCIS3ARCNT(x) ((x) << S_CCIS3ARCNT) +#define G_CCIS3ARCNT(x) (((x) >> S_CCIS3ARCNT) & M_CCIS3ARCNT) + +#define S_CCIS3WCNT 8 +#define M_CCIS3WCNT 0xffU +#define V_CCIS3WCNT(x) ((x) << S_CCIS3WCNT) +#define G_CCIS3WCNT(x) (((x) >> S_CCIS3WCNT) & M_CCIS3WCNT) + +#define S_CCIS3AWCNT 0 +#define M_CCIS3AWCNT 0xffU +#define V_CCIS3AWCNT(x) ((x) << S_CCIS3AWCNT) +#define G_CCIS3AWCNT(x) (((x) >> S_CCIS3AWCNT) & M_CCIS3AWCNT) + +#define A_ARM_CCI_TR_DEBUGS4 0x47330 + +#define S_CCIS4RCNT 24 +#define M_CCIS4RCNT 0xffU +#define V_CCIS4RCNT(x) ((x) << S_CCIS4RCNT) +#define G_CCIS4RCNT(x) (((x) >> S_CCIS4RCNT) & M_CCIS4RCNT) + +#define S_CCIS4ARCNT 16 +#define M_CCIS4ARCNT 0xffU +#define V_CCIS4ARCNT(x) ((x) << S_CCIS4ARCNT) +#define G_CCIS4ARCNT(x) (((x) >> S_CCIS4ARCNT) & M_CCIS4ARCNT) + +#define S_CCIS4WCNT 8 +#define M_CCIS4WCNT 0xffU +#define V_CCIS4WCNT(x) ((x) << S_CCIS4WCNT) +#define G_CCIS4WCNT(x) (((x) >> S_CCIS4WCNT) & M_CCIS4WCNT) + +#define S_CCIS4AWCNT 0 +#define M_CCIS4AWCNT 0xffU +#define V_CCIS4AWCNT(x) ((x) << S_CCIS4AWCNT) +#define G_CCIS4AWCNT(x) (((x) >> S_CCIS4AWCNT) & M_CCIS4AWCNT) + +#define A_ARM_CCI_TR_DEBUGS34 0x47334 + +#define S_CCIS4RSPCNT 24 +#define M_CCIS4RSPCNT 0xffU +#define V_CCIS4RSPCNT(x) ((x) << S_CCIS4RSPCNT) +#define G_CCIS4RSPCNT(x) (((x) >> S_CCIS4RSPCNT) & M_CCIS4RSPCNT) + +#define S_CCIS4ACCNT 16 +#define M_CCIS4ACCNT 0xffU +#define V_CCIS4ACCNT(x) ((x) << S_CCIS4ACCNT) +#define G_CCIS4ACCNT(x) (((x) >> S_CCIS4ACCNT) & M_CCIS4ACCNT) + +#define S_CCIS3RSPCNT 8 +#define M_CCIS3RSPCNT 0xffU +#define V_CCIS3RSPCNT(x) ((x) << S_CCIS3RSPCNT) +#define G_CCIS3RSPCNT(x) (((x) >> S_CCIS3RSPCNT) & M_CCIS3RSPCNT) + +#define S_CCIS3ACCNT 0 +#define M_CCIS3ACCNT 0xffU +#define V_CCIS3ACCNT(x) ((x) << S_CCIS3ACCNT) +#define G_CCIS3ACCNT(x) (((x) >> S_CCIS3ACCNT) & M_CCIS3ACCNT) + +#define A_ARM_CCI_TR_DEBUGM0 0x47338 + +#define S_CCIM0RCNT 24 +#define M_CCIM0RCNT 0xffU +#define V_CCIM0RCNT(x) ((x) << S_CCIM0RCNT) +#define G_CCIM0RCNT(x) (((x) >> S_CCIM0RCNT) & M_CCIM0RCNT) + +#define S_CCIM0ARCNT 16 +#define M_CCIM0ARCNT 0xffU +#define V_CCIM0ARCNT(x) ((x) << S_CCIM0ARCNT) +#define G_CCIM0ARCNT(x) (((x) >> S_CCIM0ARCNT) & M_CCIM0ARCNT) + +#define S_CCIM0WCNT 8 +#define M_CCIM0WCNT 0xffU +#define V_CCIM0WCNT(x) ((x) << S_CCIM0WCNT) +#define G_CCIM0WCNT(x) (((x) >> S_CCIM0WCNT) & M_CCIM0WCNT) + +#define S_CCIM0AWCNT 0 +#define M_CCIM0AWCNT 0xffU +#define V_CCIM0AWCNT(x) ((x) << S_CCIM0AWCNT) +#define G_CCIM0AWCNT(x) (((x) >> S_CCIM0AWCNT) & M_CCIM0AWCNT) + +#define A_ARM_CCI_TR_DEBUGM1 0x4733c + +#define S_CCIM1RCNT 24 +#define M_CCIM1RCNT 0xffU +#define V_CCIM1RCNT(x) ((x) << S_CCIM1RCNT) +#define G_CCIM1RCNT(x) (((x) >> S_CCIM1RCNT) & M_CCIM1RCNT) + +#define S_CCIM1ARCNT 16 +#define M_CCIM1ARCNT 0xffU +#define V_CCIM1ARCNT(x) ((x) << S_CCIM1ARCNT) +#define G_CCIM1ARCNT(x) (((x) >> S_CCIM1ARCNT) & M_CCIM1ARCNT) + +#define S_CCIM1WCNT 8 +#define M_CCIM1WCNT 0xffU +#define V_CCIM1WCNT(x) ((x) << S_CCIM1WCNT) +#define G_CCIM1WCNT(x) (((x) >> S_CCIM1WCNT) & M_CCIM1WCNT) + +#define S_CCIM1AWCNT 0 +#define M_CCIM1AWCNT 0xffU +#define V_CCIM1AWCNT(x) ((x) << S_CCIM1AWCNT) +#define G_CCIM1AWCNT(x) (((x) >> S_CCIM1AWCNT) & M_CCIM1AWCNT) + +#define A_ARM_CCI_TR_DEBUGM2 0x47340 + +#define S_CCIM2RCNT 24 +#define M_CCIM2RCNT 0xffU +#define V_CCIM2RCNT(x) ((x) << S_CCIM2RCNT) +#define G_CCIM2RCNT(x) (((x) >> S_CCIM2RCNT) & M_CCIM2RCNT) + +#define S_CCIM2ARCNT 16 +#define M_CCIM2ARCNT 0xffU +#define V_CCIM2ARCNT(x) ((x) << S_CCIM2ARCNT) +#define G_CCIM2ARCNT(x) (((x) >> S_CCIM2ARCNT) & M_CCIM2ARCNT) + +#define S_CCIM2WCNT 8 +#define M_CCIM2WCNT 0xffU +#define V_CCIM2WCNT(x) ((x) << S_CCIM2WCNT) +#define G_CCIM2WCNT(x) (((x) >> S_CCIM2WCNT) & M_CCIM2WCNT) + +#define S_CCIM2AWCNT 0 +#define M_CCIM2AWCNT 0xffU +#define V_CCIM2AWCNT(x) ((x) << S_CCIM2AWCNT) +#define G_CCIM2AWCNT(x) (((x) >> S_CCIM2AWCNT) & M_CCIM2AWCNT) + +#define A_ARM_MA_TR_DEBUG 0x47344 + +#define S_MA1_RD_CNT 24 +#define M_MA1_RD_CNT 0xffU +#define V_MA1_RD_CNT(x) ((x) << S_MA1_RD_CNT) +#define G_MA1_RD_CNT(x) (((x) >> S_MA1_RD_CNT) & M_MA1_RD_CNT) + +#define S_MA1_WR_CNT 16 +#define M_MA1_WR_CNT 0xffU +#define V_MA1_WR_CNT(x) ((x) << S_MA1_WR_CNT) +#define G_MA1_WR_CNT(x) (((x) >> S_MA1_WR_CNT) & M_MA1_WR_CNT) + +#define S_MA0_RD_CNT 8 +#define M_MA0_RD_CNT 0xffU +#define V_MA0_RD_CNT(x) ((x) << S_MA0_RD_CNT) +#define G_MA0_RD_CNT(x) (((x) >> S_MA0_RD_CNT) & M_MA0_RD_CNT) + +#define S_MA0_WR_CNT 0 +#define M_MA0_WR_CNT 0xffU +#define V_MA0_WR_CNT(x) ((x) << S_MA0_WR_CNT) +#define G_MA0_WR_CNT(x) (((x) >> S_MA0_WR_CNT) & M_MA0_WR_CNT) + +#define A_ARM_GP_INT 0x47348 + +#define S_GP_INT 0 +#define M_GP_INT 0xffU +#define V_GP_INT(x) ((x) << S_GP_INT) +#define G_GP_INT(x) (((x) >> S_GP_INT) & M_GP_INT) + +#define A_ARM_DMA_CFG0 0x47350 +#define A_ARM_DMA_CFG1 0x47354 + +#define S_DMABOOTPERIPHNS 16 +#define M_DMABOOTPERIPHNS 0x3ffU +#define V_DMABOOTPERIPHNS(x) ((x) << S_DMABOOTPERIPHNS) +#define G_DMABOOTPERIPHNS(x) (((x) >> S_DMABOOTPERIPHNS) & M_DMABOOTPERIPHNS) + +#define S_DMABOOTIRQNS 4 +#define M_DMABOOTIRQNS 0x3ffU +#define V_DMABOOTIRQNS(x) ((x) << S_DMABOOTIRQNS) +#define G_DMABOOTIRQNS(x) (((x) >> S_DMABOOTIRQNS) & M_DMABOOTIRQNS) + +#define S_DMABOOTMANAGERNS 1 +#define V_DMABOOTMANAGERNS(x) ((x) << S_DMABOOTMANAGERNS) +#define F_DMABOOTMANAGERNS V_DMABOOTMANAGERNS(1U) + +#define S_DMABOOTFROMPC 0 +#define V_DMABOOTFROMPC(x) ((x) << S_DMABOOTFROMPC) +#define F_DMABOOTFROMPC V_DMABOOTFROMPC(1U) + +#define A_ARM_ARM_CFG0 0x47380 + +#define S_MESSAGEBYPASS_DATA 2 +#define V_MESSAGEBYPASS_DATA(x) ((x) << S_MESSAGEBYPASS_DATA) +#define F_MESSAGEBYPASS_DATA V_MESSAGEBYPASS_DATA(1U) + +#define S_MESSAGEBYPASS 1 +#define V_MESSAGEBYPASS(x) ((x) << S_MESSAGEBYPASS) +#define F_MESSAGEBYPASS V_MESSAGEBYPASS(1U) + +#define S_PCIEBYPASS 0 +#define V_PCIEBYPASS(x) ((x) << S_PCIEBYPASS) +#define F_PCIEBYPASS V_PCIEBYPASS(1U) + +#define A_ARM_ARM_CFG1 0x47384 +#define A_ARM_ARM_CFG2 0x47390 +#define A_ARM_PCIE_MA_ADDR_REGION0 0x47400 + +#define S_ADDRREG0 0 +#define M_ADDRREG0 0xfffffffU +#define V_ADDRREG0(x) ((x) << S_ADDRREG0) +#define G_ADDRREG0(x) (((x) >> S_ADDRREG0) & M_ADDRREG0) + +#define A_ARM_PCIE_MA_ADDR_REGION1 0x47404 + +#define S_ADDRREG1 0 +#define M_ADDRREG1 0xfffffffU +#define V_ADDRREG1(x) ((x) << S_ADDRREG1) +#define G_ADDRREG1(x) (((x) >> S_ADDRREG1) & M_ADDRREG1) + +#define A_ARM_PCIE_MA_ADDR_REGION2 0x47408 + +#define S_ADDRREG2 0 +#define M_ADDRREG2 0xfffffffU +#define V_ADDRREG2(x) ((x) << S_ADDRREG2) +#define G_ADDRREG2(x) (((x) >> S_ADDRREG2) & M_ADDRREG2) + +#define A_ARM_PCIE_MA_ADDR_REGION3 0x4740c + +#define S_ADDRREG3 0 +#define M_ADDRREG3 0xfffffffU +#define V_ADDRREG3(x) ((x) << S_ADDRREG3) +#define G_ADDRREG3(x) (((x) >> S_ADDRREG3) & M_ADDRREG3) + +#define A_ARM_PCIE_MA_ADDR_REGION4 0x47410 + +#define S_ADDRREG4 0 +#define M_ADDRREG4 0xfffffffU +#define V_ADDRREG4(x) ((x) << S_ADDRREG4) +#define G_ADDRREG4(x) (((x) >> S_ADDRREG4) & M_ADDRREG4) + +#define A_ARM_PCIE_MA_ADDR_REGION5 0x47414 + +#define S_ADDRREG5 0 +#define M_ADDRREG5 0xfffffffU +#define V_ADDRREG5(x) ((x) << S_ADDRREG5) +#define G_ADDRREG5(x) (((x) >> S_ADDRREG5) & M_ADDRREG5) + +#define A_ARM_PCIE_MA_ADDR_REGION6 0x47418 + +#define S_ADDRREG6 0 +#define M_ADDRREG6 0xfffffffU +#define V_ADDRREG6(x) ((x) << S_ADDRREG6) +#define G_ADDRREG6(x) (((x) >> S_ADDRREG6) & M_ADDRREG6) + +#define A_ARM_PCIE_MA_ADDR_REGION7 0x4741c + +#define S_ADDRREG7 0 +#define M_ADDRREG7 0xfffffffU +#define V_ADDRREG7(x) ((x) << S_ADDRREG7) +#define G_ADDRREG7(x) (((x) >> S_ADDRREG7) & M_ADDRREG7) + +#define A_ARM_INTERRUPT_GEN 0x47420 + +#define S_INT_GEN 0 +#define M_INT_GEN 0x3U +#define V_INT_GEN(x) ((x) << S_INT_GEN) +#define G_INT_GEN(x) (((x) >> S_INT_GEN) & M_INT_GEN) + +#define A_ARM_INTERRUPT_CLEAR 0x47424 + +#define S_INT_CLEAR 0 +#define M_INT_CLEAR 0x3U +#define V_INT_CLEAR(x) ((x) << S_INT_CLEAR) +#define G_INT_CLEAR(x) (((x) >> S_INT_CLEAR) & M_INT_CLEAR) + +#define A_ARM_DEBUG_STATUS_0 0x47428 +#define A_ARM_DBPROC_CONTROL 0x4742c + +#define S_NO_OF_INTERRUPTS 0 +#define M_NO_OF_INTERRUPTS 0x3U +#define V_NO_OF_INTERRUPTS(x) ((x) << S_NO_OF_INTERRUPTS) +#define G_NO_OF_INTERRUPTS(x) (((x) >> S_NO_OF_INTERRUPTS) & M_NO_OF_INTERRUPTS) + +#define A_ARM_PERR_INT_CAUSE1 0x47430 + +#define S_ARWFIFO0_PERR 31 +#define V_ARWFIFO0_PERR(x) ((x) << S_ARWFIFO0_PERR) +#define F_ARWFIFO0_PERR V_ARWFIFO0_PERR(1U) + +#define S_ARWFIFO1_PERR 30 +#define V_ARWFIFO1_PERR(x) ((x) << S_ARWFIFO1_PERR) +#define F_ARWFIFO1_PERR V_ARWFIFO1_PERR(1U) + +#define S_ARWIDFIFO0_PERR 29 +#define V_ARWIDFIFO0_PERR(x) ((x) << S_ARWIDFIFO0_PERR) +#define F_ARWIDFIFO0_PERR V_ARWIDFIFO0_PERR(1U) + +#define S_ARWIDFIFO1_PERR 28 +#define V_ARWIDFIFO1_PERR(x) ((x) << S_ARWIDFIFO1_PERR) +#define F_ARWIDFIFO1_PERR V_ARWIDFIFO1_PERR(1U) + +#define S_ARIDFIFO0_PERR 27 +#define V_ARIDFIFO0_PERR(x) ((x) << S_ARIDFIFO0_PERR) +#define F_ARIDFIFO0_PERR V_ARIDFIFO0_PERR(1U) + +#define S_ARIDFIFO1_PERR 26 +#define V_ARIDFIFO1_PERR(x) ((x) << S_ARIDFIFO1_PERR) +#define F_ARIDFIFO1_PERR V_ARIDFIFO1_PERR(1U) + +#define S_RRSPADDR_FIFO0_PERR 25 +#define V_RRSPADDR_FIFO0_PERR(x) ((x) << S_RRSPADDR_FIFO0_PERR) +#define F_RRSPADDR_FIFO0_PERR V_RRSPADDR_FIFO0_PERR(1U) + +#define S_RRSPADDR_FIFO1_PERR 24 +#define V_RRSPADDR_FIFO1_PERR(x) ((x) << S_RRSPADDR_FIFO1_PERR) +#define F_RRSPADDR_FIFO1_PERR V_RRSPADDR_FIFO1_PERR(1U) + +#define S_WRSTRB_FIFO0_PERR 23 +#define V_WRSTRB_FIFO0_PERR(x) ((x) << S_WRSTRB_FIFO0_PERR) +#define F_WRSTRB_FIFO0_PERR V_WRSTRB_FIFO0_PERR(1U) + +#define S_WRSTRB_FIFO1_PERR 22 +#define V_WRSTRB_FIFO1_PERR(x) ((x) << S_WRSTRB_FIFO1_PERR) +#define F_WRSTRB_FIFO1_PERR V_WRSTRB_FIFO1_PERR(1U) + +#define S_MA2AXI_RSPDATAPARERR 21 +#define V_MA2AXI_RSPDATAPARERR(x) ((x) << S_MA2AXI_RSPDATAPARERR) +#define F_MA2AXI_RSPDATAPARERR V_MA2AXI_RSPDATAPARERR(1U) + +#define S_MA2AXI_DATA_PAR_ERR 20 +#define V_MA2AXI_DATA_PAR_ERR(x) ((x) << S_MA2AXI_DATA_PAR_ERR) +#define F_MA2AXI_DATA_PAR_ERR V_MA2AXI_DATA_PAR_ERR(1U) + +#define S_MA2AXI_WR_ORD_FIFO_PARERR 19 +#define V_MA2AXI_WR_ORD_FIFO_PARERR(x) ((x) << S_MA2AXI_WR_ORD_FIFO_PARERR) +#define F_MA2AXI_WR_ORD_FIFO_PARERR V_MA2AXI_WR_ORD_FIFO_PARERR(1U) + +#define S_NVME_DB_EMU_TRACKER_FIFO_PERR 18 +#define V_NVME_DB_EMU_TRACKER_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_TRACKER_FIFO_PERR) +#define F_NVME_DB_EMU_TRACKER_FIFO_PERR V_NVME_DB_EMU_TRACKER_FIFO_PERR(1U) + +#define S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR 17 +#define V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR) +#define F_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(1U) + +#define S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR 16 +#define V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR) +#define F_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(1U) + +#define S_NVME_DB_EMU_ID_FIFO0_PERR 15 +#define V_NVME_DB_EMU_ID_FIFO0_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO0_PERR) +#define F_NVME_DB_EMU_ID_FIFO0_PERR V_NVME_DB_EMU_ID_FIFO0_PERR(1U) + +#define S_NVME_DB_EMU_ID_FIFO1_PERR 14 +#define V_NVME_DB_EMU_ID_FIFO1_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO1_PERR) +#define F_NVME_DB_EMU_ID_FIFO1_PERR V_NVME_DB_EMU_ID_FIFO1_PERR(1U) + +#define S_RC_ARWFIFO_PERR 13 +#define V_RC_ARWFIFO_PERR(x) ((x) << S_RC_ARWFIFO_PERR) +#define F_RC_ARWFIFO_PERR V_RC_ARWFIFO_PERR(1U) + +#define S_RC_ARIDBURSTADDRFIFO_PERR 12 +#define V_RC_ARIDBURSTADDRFIFO_PERR(x) ((x) << S_RC_ARIDBURSTADDRFIFO_PERR) +#define F_RC_ARIDBURSTADDRFIFO_PERR V_RC_ARIDBURSTADDRFIFO_PERR(1U) + +#define S_RC_CFG_FIFO_PERR 11 +#define V_RC_CFG_FIFO_PERR(x) ((x) << S_RC_CFG_FIFO_PERR) +#define F_RC_CFG_FIFO_PERR V_RC_CFG_FIFO_PERR(1U) + +#define S_RC_RSPFIFO_PERR 10 +#define V_RC_RSPFIFO_PERR(x) ((x) << S_RC_RSPFIFO_PERR) +#define F_RC_RSPFIFO_PERR V_RC_RSPFIFO_PERR(1U) + +#define S_INIC_ARIDFIFO_PERR 9 +#define V_INIC_ARIDFIFO_PERR(x) ((x) << S_INIC_ARIDFIFO_PERR) +#define F_INIC_ARIDFIFO_PERR V_INIC_ARIDFIFO_PERR(1U) + +#define S_INIC_ARWFIFO_PERR 8 +#define V_INIC_ARWFIFO_PERR(x) ((x) << S_INIC_ARWFIFO_PERR) +#define F_INIC_ARWFIFO_PERR V_INIC_ARWFIFO_PERR(1U) + +#define S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR 7 +#define V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR) +#define F_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(1U) + +#define S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR 6 +#define V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR) +#define F_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(1U) + +#define S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR 5 +#define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR) +#define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(1U) + +#define S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR 4 +#define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR) +#define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(1U) + +#define S_ARM_MA_512B_ARB_FIFO_PERR 3 +#define V_ARM_MA_512B_ARB_FIFO_PERR(x) ((x) << S_ARM_MA_512B_ARB_FIFO_PERR) +#define F_ARM_MA_512B_ARB_FIFO_PERR V_ARM_MA_512B_ARB_FIFO_PERR(1U) + +#define S_PCIE_INIC_MA_ARB_FIFO_PERR 2 +#define V_PCIE_INIC_MA_ARB_FIFO_PERR(x) ((x) << S_PCIE_INIC_MA_ARB_FIFO_PERR) +#define F_PCIE_INIC_MA_ARB_FIFO_PERR V_PCIE_INIC_MA_ARB_FIFO_PERR(1U) + +#define S_PCIE_INIC_ARB_RSPPERR 1 +#define V_PCIE_INIC_ARB_RSPPERR(x) ((x) << S_PCIE_INIC_ARB_RSPPERR) +#define F_PCIE_INIC_ARB_RSPPERR V_PCIE_INIC_ARB_RSPPERR(1U) + +#define S_ITE_CACHE_PERR 0 +#define V_ITE_CACHE_PERR(x) ((x) << S_ITE_CACHE_PERR) +#define F_ITE_CACHE_PERR V_ITE_CACHE_PERR(1U) + +#define A_ARM_PERR_INT_ENB1 0x47434 +#define A_ARM_PERR_ENABLE1 0x47438 +#define A_ARM_DEBUG_STATUS_1 0x4743c +#define A_ARM_PCIE_MA_ADDR_REGION_DST 0x47440 + +#define S_ADDRREGDST 0 +#define M_ADDRREGDST 0x1ffU +#define V_ADDRREGDST(x) ((x) << S_ADDRREGDST) +#define G_ADDRREGDST(x) (((x) >> S_ADDRREGDST) & M_ADDRREGDST) + +#define A_ARM_ERR_INT_CAUSE0 0x47444 + +#define S_STRB0_ERROR 31 +#define V_STRB0_ERROR(x) ((x) << S_STRB0_ERROR) +#define F_STRB0_ERROR V_STRB0_ERROR(1U) + +#define S_STRB1_ERROR 30 +#define V_STRB1_ERROR(x) ((x) << S_STRB1_ERROR) +#define F_STRB1_ERROR V_STRB1_ERROR(1U) + +#define S_PCIE_INIC_MA_ARB_INV_RSP_TAG 29 +#define V_PCIE_INIC_MA_ARB_INV_RSP_TAG(x) ((x) << S_PCIE_INIC_MA_ARB_INV_RSP_TAG) +#define F_PCIE_INIC_MA_ARB_INV_RSP_TAG V_PCIE_INIC_MA_ARB_INV_RSP_TAG(1U) + +#define S_ERROR0_NOCMD_DATA 28 +#define V_ERROR0_NOCMD_DATA(x) ((x) << S_ERROR0_NOCMD_DATA) +#define F_ERROR0_NOCMD_DATA V_ERROR0_NOCMD_DATA(1U) + +#define S_ERROR1_NOCMD_DATA 27 +#define V_ERROR1_NOCMD_DATA(x) ((x) << S_ERROR1_NOCMD_DATA) +#define F_ERROR1_NOCMD_DATA V_ERROR1_NOCMD_DATA(1U) + +#define S_INIC_STRB_ERROR 26 +#define V_INIC_STRB_ERROR(x) ((x) << S_INIC_STRB_ERROR) +#define F_INIC_STRB_ERROR V_INIC_STRB_ERROR(1U) + +#define A_ARM_ERR_INT_ENB0 0x47448 +#define A_ARM_DEBUG_INDEX 0x47450 +#define A_ARM_DEBUG_DATA_HIGH 0x47454 +#define A_ARM_DEBUG_DATA_LOW 0x47458 +#define A_ARM_MSG_PCIE_MESSAGE2AXI_BA0 0x47500 +#define A_ARM_MSG_PCIE_MESSAGE2AXI_BA1 0x47504 + +#define S_BASEADDRESS 0 +#define M_BASEADDRESS 0x3U +#define V_BASEADDRESS(x) ((x) << S_BASEADDRESS) +#define G_BASEADDRESS(x) (((x) >> S_BASEADDRESS) & M_BASEADDRESS) + +#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG0 0x47508 + +#define S_WATERMARK 16 +#define M_WATERMARK 0x3ffU +#define V_WATERMARK(x) ((x) << S_WATERMARK) +#define G_WATERMARK(x) (((x) >> S_WATERMARK) & M_WATERMARK) + +#define S_SIZEMAX 0 +#define M_SIZEMAX 0x3ffU +#define V_SIZEMAX(x) ((x) << S_SIZEMAX) +#define G_SIZEMAX(x) (((x) >> S_SIZEMAX) & M_SIZEMAX) + +#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG1 0x4750c +#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG2 0x47510 + +#define S_CPUREADADDRESS 0 +#define M_CPUREADADDRESS 0x3ffU +#define V_CPUREADADDRESS(x) ((x) << S_CPUREADADDRESS) +#define G_CPUREADADDRESS(x) (((x) >> S_CPUREADADDRESS) & M_CPUREADADDRESS) + +#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG3 0x47514 + +#define S_CPUREADADDRESSVLD 0 +#define V_CPUREADADDRESSVLD(x) ((x) << S_CPUREADADDRESSVLD) +#define F_CPUREADADDRESSVLD V_CPUREADADDRESSVLD(1U) + +#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 0x47518 +#define A_ARM_APB2MSI_INTERRUPT_0_STATUS 0x47600 +#define A_ARM_APB2MSI_INTERRUPT_1_STATUS 0x47604 +#define A_ARM_APB2MSI_INTERRUPT_2_STATUS 0x47608 +#define A_ARM_APB2MSI_INTERRUPT_3_STATUS 0x4760c +#define A_ARM_APB2MSI_INTERRUPT_0_ENABLE 0x47610 +#define A_ARM_APB2MSI_INTERRUPT_1_ENABLE 0x47614 +#define A_ARM_APB2MSI_INTERRUPT_2_ENABLE 0x47618 +#define A_ARM_APB2MSI_INTERRUPT_3_ENABLE 0x4761c +#define A_ARM_APB2MSI_INTERRUPT_PRIORITY_LEVEL 0x47620 + +#define S_ARM_APB2MSI_INT_PRIORITY_LEVEL 0 +#define M_ARM_APB2MSI_INT_PRIORITY_LEVEL 0x7U +#define V_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) ((x) << S_ARM_APB2MSI_INT_PRIORITY_LEVEL) +#define G_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) (((x) >> S_ARM_APB2MSI_INT_PRIORITY_LEVEL) & M_ARM_APB2MSI_INT_PRIORITY_LEVEL) + +#define A_ARM_APB2MSI_MEM_READ_ADDR 0x47624 + +#define S_ARM_APB2MSI_MEM_READ_ADDR 0 +#define M_ARM_APB2MSI_MEM_READ_ADDR 0x7fU +#define V_ARM_APB2MSI_MEM_READ_ADDR(x) ((x) << S_ARM_APB2MSI_MEM_READ_ADDR) +#define G_ARM_APB2MSI_MEM_READ_ADDR(x) (((x) >> S_ARM_APB2MSI_MEM_READ_ADDR) & M_ARM_APB2MSI_MEM_READ_ADDR) + +#define A_ARM_MSI_MEMORY_DATA 0x47628 +#define A_ARM_MSI_MEMORY_ADDR 0x4762c +#define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG5 0x47630 + +#define S_CONFIGDONE 0 +#define V_CONFIGDONE(x) ((x) << S_CONFIGDONE) +#define F_CONFIGDONE V_CONFIGDONE(1U) + +#define A_ARM_AXI2MA_TIMERCNT 0x47640 +#define A_ARM_AXI2MA_TRTYPE 0x47644 + +#define S_ARMMA2AXI1ARTRTYPE 3 +#define V_ARMMA2AXI1ARTRTYPE(x) ((x) << S_ARMMA2AXI1ARTRTYPE) +#define F_ARMMA2AXI1ARTRTYPE V_ARMMA2AXI1ARTRTYPE(1U) + +#define S_ARMMA2AXI1AWTRTYPE 2 +#define V_ARMMA2AXI1AWTRTYPE(x) ((x) << S_ARMMA2AXI1AWTRTYPE) +#define F_ARMMA2AXI1AWTRTYPE V_ARMMA2AXI1AWTRTYPE(1U) + +#define S_ARMMA2AXI0ARTRTYPE 1 +#define V_ARMMA2AXI0ARTRTYPE(x) ((x) << S_ARMMA2AXI0ARTRTYPE) +#define F_ARMMA2AXI0ARTRTYPE V_ARMMA2AXI0ARTRTYPE(1U) + +#define S_ARMMA2AXI0AWTRTYPE 0 +#define V_ARMMA2AXI0AWTRTYPE(x) ((x) << S_ARMMA2AXI0AWTRTYPE) +#define F_ARMMA2AXI0AWTRTYPE V_ARMMA2AXI0AWTRTYPE(1U) + +#define A_ARM_AXI2PCIE_VENDOR 0x47660 + +#define S_T7_VENDORID 4 +#define M_T7_VENDORID 0xffffU +#define V_T7_VENDORID(x) ((x) << S_T7_VENDORID) +#define G_T7_VENDORID(x) (((x) >> S_T7_VENDORID) & M_T7_VENDORID) + +#define S_OBFFCODE 0 +#define M_OBFFCODE 0xfU +#define V_OBFFCODE(x) ((x) << S_OBFFCODE) +#define G_OBFFCODE(x) (((x) >> S_OBFFCODE) & M_OBFFCODE) + +#define A_ARM_AXI2PCIE_VENMSGHDR_DW3 0x47664 +#define A_ARM_CLUSTER_SEL 0x47668 + +#define S_ARM_CLUSTER_SEL 0 +#define V_ARM_CLUSTER_SEL(x) ((x) << S_ARM_CLUSTER_SEL) +#define F_ARM_CLUSTER_SEL V_ARM_CLUSTER_SEL(1U) + +#define A_ARM_PWRREQ_PERMIT_ADB 0x4766c + +#define S_PWRQ_PERMIT_DENY_SAR 1 +#define V_PWRQ_PERMIT_DENY_SAR(x) ((x) << S_PWRQ_PERMIT_DENY_SAR) +#define F_PWRQ_PERMIT_DENY_SAR V_PWRQ_PERMIT_DENY_SAR(1U) + +#define S_PWRQREQNS_ADB 0 +#define V_PWRQREQNS_ADB(x) ((x) << S_PWRQREQNS_ADB) +#define F_PWRQREQNS_ADB V_PWRQREQNS_ADB(1U) + +#define A_ARM_CLK_REQ_ADB 0x47670 + +#define S_CLKQREQNS_ADB 0 +#define V_CLKQREQNS_ADB(x) ((x) << S_CLKQREQNS_ADB) +#define F_CLKQREQNS_ADB V_CLKQREQNS_ADB(1U) + +#define A_ARM_WAKEUPM 0x47674 + +#define S_DFTRSTDISABLEM_ADB 2 +#define V_DFTRSTDISABLEM_ADB(x) ((x) << S_DFTRSTDISABLEM_ADB) +#define F_DFTRSTDISABLEM_ADB V_DFTRSTDISABLEM_ADB(1U) + +#define S_DFTRSTDISABLES_ADB 1 +#define V_DFTRSTDISABLES_ADB(x) ((x) << S_DFTRSTDISABLES_ADB) +#define F_DFTRSTDISABLES_ADB V_DFTRSTDISABLES_ADB(1U) + +#define S_WAKEUPM_I_ADB 0 +#define V_WAKEUPM_I_ADB(x) ((x) << S_WAKEUPM_I_ADB) +#define F_WAKEUPM_I_ADB V_WAKEUPM_I_ADB(1U) + +#define A_ARM_CC_APB_FILTERING 0x47678 + +#define S_CC_DFTSCANMODE 11 +#define V_CC_DFTSCANMODE(x) ((x) << S_CC_DFTSCANMODE) +#define F_CC_DFTSCANMODE V_CC_DFTSCANMODE(1U) + +#define S_CC_OTP_FILTERING_DISABLE 10 +#define V_CC_OTP_FILTERING_DISABLE(x) ((x) << S_CC_OTP_FILTERING_DISABLE) +#define F_CC_OTP_FILTERING_DISABLE V_CC_OTP_FILTERING_DISABLE(1U) + +#define S_CC_APB_FILTERING 0 +#define M_CC_APB_FILTERING 0x3ffU +#define V_CC_APB_FILTERING(x) ((x) << S_CC_APB_FILTERING) +#define G_CC_APB_FILTERING(x) (((x) >> S_CC_APB_FILTERING) & M_CC_APB_FILTERING) + +#define A_ARM_DCU_EN0 0x4767c +#define A_ARM_DCU_EN1 0x47680 +#define A_ARM_DCU_EN2 0x47684 +#define A_ARM_DCU_EN3 0x47688 +#define A_ARM_DCU_LOCK0 0x4768c +#define A_ARM_DCU_LOCK1 0x47690 +#define A_ARM_DCU_LOCK2 0x47694 +#define A_ARM_DCU_LOCK3 0x47698 +#define A_ARM_GPPC 0x4769c + +#define S_CC_SEC_DEBUG_RESET 24 +#define V_CC_SEC_DEBUG_RESET(x) ((x) << S_CC_SEC_DEBUG_RESET) +#define F_CC_SEC_DEBUG_RESET V_CC_SEC_DEBUG_RESET(1U) + +#define S_CC_DFTSE 23 +#define V_CC_DFTSE(x) ((x) << S_CC_DFTSE) +#define F_CC_DFTSE V_CC_DFTSE(1U) + +#define S_CC_DFTCGEN 22 +#define V_CC_DFTCGEN(x) ((x) << S_CC_DFTCGEN) +#define F_CC_DFTCGEN V_CC_DFTCGEN(1U) + +#define S_CC_DFTRAMHOLD 21 +#define V_CC_DFTRAMHOLD(x) ((x) << S_CC_DFTRAMHOLD) +#define F_CC_DFTRAMHOLD V_CC_DFTRAMHOLD(1U) + +#define S_CC_LOCK_BITS 12 +#define M_CC_LOCK_BITS 0x1ffU +#define V_CC_LOCK_BITS(x) ((x) << S_CC_LOCK_BITS) +#define G_CC_LOCK_BITS(x) (((x) >> S_CC_LOCK_BITS) & M_CC_LOCK_BITS) + +#define S_CC_LCS_IS_VALID 11 +#define V_CC_LCS_IS_VALID(x) ((x) << S_CC_LCS_IS_VALID) +#define F_CC_LCS_IS_VALID V_CC_LCS_IS_VALID(1U) + +#define S_CC_LCS 8 +#define M_CC_LCS 0x7U +#define V_CC_LCS(x) ((x) << S_CC_LCS) +#define G_CC_LCS(x) (((x) >> S_CC_LCS) & M_CC_LCS) + +#define S_CC_GPPC 0 +#define M_CC_GPPC 0xffU +#define V_CC_GPPC(x) ((x) << S_CC_GPPC) +#define G_CC_GPPC(x) (((x) >> S_CC_GPPC) & M_CC_GPPC) + +#define A_ARM_EMMC 0x47700 + +#define S_EMMC_CARD_CLK_EN 31 +#define V_EMMC_CARD_CLK_EN(x) ((x) << S_EMMC_CARD_CLK_EN) +#define F_EMMC_CARD_CLK_EN V_EMMC_CARD_CLK_EN(1U) + +#define S_EMMC_LED_CONTROL 30 +#define V_EMMC_LED_CONTROL(x) ((x) << S_EMMC_LED_CONTROL) +#define F_EMMC_LED_CONTROL V_EMMC_LED_CONTROL(1U) + +#define S_EMMC_UHS1_SWVOLT_EN 29 +#define V_EMMC_UHS1_SWVOLT_EN(x) ((x) << S_EMMC_UHS1_SWVOLT_EN) +#define F_EMMC_UHS1_SWVOLT_EN V_EMMC_UHS1_SWVOLT_EN(1U) + +#define S_EMMC_UHS1_DRV_STH 27 +#define M_EMMC_UHS1_DRV_STH 0x3U +#define V_EMMC_UHS1_DRV_STH(x) ((x) << S_EMMC_UHS1_DRV_STH) +#define G_EMMC_UHS1_DRV_STH(x) (((x) >> S_EMMC_UHS1_DRV_STH) & M_EMMC_UHS1_DRV_STH) + +#define S_EMMC_SD_VDD1_ON 26 +#define V_EMMC_SD_VDD1_ON(x) ((x) << S_EMMC_SD_VDD1_ON) +#define F_EMMC_SD_VDD1_ON V_EMMC_SD_VDD1_ON(1U) + +#define S_EMMC_SD_VDD1_SEL 23 +#define M_EMMC_SD_VDD1_SEL 0x7U +#define V_EMMC_SD_VDD1_SEL(x) ((x) << S_EMMC_SD_VDD1_SEL) +#define G_EMMC_SD_VDD1_SEL(x) (((x) >> S_EMMC_SD_VDD1_SEL) & M_EMMC_SD_VDD1_SEL) + +#define S_EMMC_INTCLK_EN 22 +#define V_EMMC_INTCLK_EN(x) ((x) << S_EMMC_INTCLK_EN) +#define F_EMMC_INTCLK_EN V_EMMC_INTCLK_EN(1U) + +#define S_EMMC_CARD_CLK_FREQ_SEL 12 +#define M_EMMC_CARD_CLK_FREQ_SEL 0x3ffU +#define V_EMMC_CARD_CLK_FREQ_SEL(x) ((x) << S_EMMC_CARD_CLK_FREQ_SEL) +#define G_EMMC_CARD_CLK_FREQ_SEL(x) (((x) >> S_EMMC_CARD_CLK_FREQ_SEL) & M_EMMC_CARD_CLK_FREQ_SEL) + +#define S_EMMC_CARD_CLK_GEN_SEL 11 +#define V_EMMC_CARD_CLK_GEN_SEL(x) ((x) << S_EMMC_CARD_CLK_GEN_SEL) +#define F_EMMC_CARD_CLK_GEN_SEL V_EMMC_CARD_CLK_GEN_SEL(1U) + +#define S_EMMC_CLK2CARD_ON 10 +#define V_EMMC_CLK2CARD_ON(x) ((x) << S_EMMC_CLK2CARD_ON) +#define F_EMMC_CLK2CARD_ON V_EMMC_CLK2CARD_ON(1U) + +#define S_EMMC_CARD_CLK_STABLE 9 +#define V_EMMC_CARD_CLK_STABLE(x) ((x) << S_EMMC_CARD_CLK_STABLE) +#define F_EMMC_CARD_CLK_STABLE V_EMMC_CARD_CLK_STABLE(1U) + +#define S_EMMC_INT_BCLK_STABLE 8 +#define V_EMMC_INT_BCLK_STABLE(x) ((x) << S_EMMC_INT_BCLK_STABLE) +#define F_EMMC_INT_BCLK_STABLE V_EMMC_INT_BCLK_STABLE(1U) + +#define S_EMMC_INT_ACLK_STABLE 7 +#define V_EMMC_INT_ACLK_STABLE(x) ((x) << S_EMMC_INT_ACLK_STABLE) +#define F_EMMC_INT_ACLK_STABLE V_EMMC_INT_ACLK_STABLE(1U) + +#define S_EMMC_INT_TMCLK_STABLE 6 +#define V_EMMC_INT_TMCLK_STABLE(x) ((x) << S_EMMC_INT_TMCLK_STABLE) +#define F_EMMC_INT_TMCLK_STABLE V_EMMC_INT_TMCLK_STABLE(1U) + +#define S_EMMC_HOST_REG_VOL_STABLE 5 +#define V_EMMC_HOST_REG_VOL_STABLE(x) ((x) << S_EMMC_HOST_REG_VOL_STABLE) +#define F_EMMC_HOST_REG_VOL_STABLE V_EMMC_HOST_REG_VOL_STABLE(1U) + +#define S_EMMC_CARD_DETECT_N 4 +#define V_EMMC_CARD_DETECT_N(x) ((x) << S_EMMC_CARD_DETECT_N) +#define F_EMMC_CARD_DETECT_N V_EMMC_CARD_DETECT_N(1U) + +#define S_EMMC_CARD_WRITE_PROT 3 +#define V_EMMC_CARD_WRITE_PROT(x) ((x) << S_EMMC_CARD_WRITE_PROT) +#define F_EMMC_CARD_WRITE_PROT V_EMMC_CARD_WRITE_PROT(1U) + +#define S_EMMC_GP_IN 2 +#define V_EMMC_GP_IN(x) ((x) << S_EMMC_GP_IN) +#define F_EMMC_GP_IN V_EMMC_GP_IN(1U) + +#define S_EMMC_TEST_SCAN_MODE 1 +#define V_EMMC_TEST_SCAN_MODE(x) ((x) << S_EMMC_TEST_SCAN_MODE) +#define F_EMMC_TEST_SCAN_MODE V_EMMC_TEST_SCAN_MODE(1U) + +#define S_EMMC_FIFOINJDATAERR 0 +#define V_EMMC_FIFOINJDATAERR(x) ((x) << S_EMMC_FIFOINJDATAERR) +#define F_EMMC_FIFOINJDATAERR V_EMMC_FIFOINJDATAERR(1U) + +#define A_ARM_WAKEUPS 0x47704 + +#define S_WAKEUPS_I_ADB 0 +#define V_WAKEUPS_I_ADB(x) ((x) << S_WAKEUPS_I_ADB) +#define F_WAKEUPS_I_ADB V_WAKEUPS_I_ADB(1U) + +#define A_ARM_CLKREQNM_ADB 0x47708 + +#define S_CLKQREQNM_ADB 0 +#define V_CLKQREQNM_ADB(x) ((x) << S_CLKQREQNM_ADB) +#define F_CLKQREQNM_ADB V_CLKQREQNM_ADB(1U) + +#define A_ARM_ATOMICDATA0_0 0x4770c +#define A_ARM_ATOMICDATA1_0 0x47710 +#define A_ARM_NVME_DB_EMU_INT_ENABLE 0x47740 +#define A_ARM_TCAM_WRITE_DATA 0x47744 + +#define S_TCAM_WRITE_DATA 0 +#define M_TCAM_WRITE_DATA 0x3fffffffU +#define V_TCAM_WRITE_DATA(x) ((x) << S_TCAM_WRITE_DATA) +#define G_TCAM_WRITE_DATA(x) (((x) >> S_TCAM_WRITE_DATA) & M_TCAM_WRITE_DATA) + +#define A_ARM_TCAM_WRITE_ADDR 0x47748 + +#define S_TCAM_WRITE_ADDR 0 +#define M_TCAM_WRITE_ADDR 0x1ffU +#define V_TCAM_WRITE_ADDR(x) ((x) << S_TCAM_WRITE_ADDR) +#define G_TCAM_WRITE_ADDR(x) (((x) >> S_TCAM_WRITE_ADDR) & M_TCAM_WRITE_ADDR) + +#define A_ARM_TCAM_READ_ADDR 0x4774c + +#define S_TCAM_READ_ADDR 0 +#define M_TCAM_READ_ADDR 0x1ffU +#define V_TCAM_READ_ADDR(x) ((x) << S_TCAM_READ_ADDR) +#define G_TCAM_READ_ADDR(x) (((x) >> S_TCAM_READ_ADDR) & M_TCAM_READ_ADDR) + +#define A_ARM_TCAM_CTL 0x47750 + +#define S_TCAMCBBUSY 6 +#define V_TCAMCBBUSY(x) ((x) << S_TCAMCBBUSY) +#define F_TCAMCBBUSY V_TCAMCBBUSY(1U) + +#define S_TCAMCBPASS 5 +#define V_TCAMCBPASS(x) ((x) << S_TCAMCBPASS) +#define F_TCAMCBPASS V_TCAMCBPASS(1U) + +#define S_TCAMCBSTART 4 +#define V_TCAMCBSTART(x) ((x) << S_TCAMCBSTART) +#define F_TCAMCBSTART V_TCAMCBSTART(1U) + +#define S_TCAMRSTCB 3 +#define V_TCAMRSTCB(x) ((x) << S_TCAMRSTCB) +#define F_TCAMRSTCB V_TCAMRSTCB(1U) + +#define S_TCAM_REQBITPOS 2 +#define V_TCAM_REQBITPOS(x) ((x) << S_TCAM_REQBITPOS) +#define F_TCAM_REQBITPOS V_TCAM_REQBITPOS(1U) + +#define S_TCAM_WRITE 1 +#define V_TCAM_WRITE(x) ((x) << S_TCAM_WRITE) +#define F_TCAM_WRITE V_TCAM_WRITE(1U) + +#define S_TCAM_ENABLE 0 +#define V_TCAM_ENABLE(x) ((x) << S_TCAM_ENABLE) +#define F_TCAM_ENABLE V_TCAM_ENABLE(1U) + +#define A_ARM_TCAM_READ_DATA 0x4775c + +#define S_TCAM_READ_DATA 0 +#define M_TCAM_READ_DATA 0x3fffffffU +#define V_TCAM_READ_DATA(x) ((x) << S_TCAM_READ_DATA) +#define G_TCAM_READ_DATA(x) (((x) >> S_TCAM_READ_DATA) & M_TCAM_READ_DATA) + +#define A_ARM_SRAM1_WRITE_DATA 0x47760 + +#define S_SRAM1_WRITE_DATA 0 +#define M_SRAM1_WRITE_DATA 0x7fffffU +#define V_SRAM1_WRITE_DATA(x) ((x) << S_SRAM1_WRITE_DATA) +#define G_SRAM1_WRITE_DATA(x) (((x) >> S_SRAM1_WRITE_DATA) & M_SRAM1_WRITE_DATA) + +#define A_ARM_SRAM1_WRITE_ADDR 0x47764 + +#define S_SRAM1_WRITE_ADDR 0 +#define M_SRAM1_WRITE_ADDR 0x1ffU +#define V_SRAM1_WRITE_ADDR(x) ((x) << S_SRAM1_WRITE_ADDR) +#define G_SRAM1_WRITE_ADDR(x) (((x) >> S_SRAM1_WRITE_ADDR) & M_SRAM1_WRITE_ADDR) + +#define A_ARM_SRAM1_READ_ADDR 0x47768 + +#define S_SRAM1_READ_ADDR 0 +#define M_SRAM1_READ_ADDR 0x1ffU +#define V_SRAM1_READ_ADDR(x) ((x) << S_SRAM1_READ_ADDR) +#define G_SRAM1_READ_ADDR(x) (((x) >> S_SRAM1_READ_ADDR) & M_SRAM1_READ_ADDR) + +#define A_ARM_SRAM1_CTL 0x4776c + +#define S_SRAM1_WRITE 1 +#define V_SRAM1_WRITE(x) ((x) << S_SRAM1_WRITE) +#define F_SRAM1_WRITE V_SRAM1_WRITE(1U) + +#define S_SRAM1_ENABLE 0 +#define V_SRAM1_ENABLE(x) ((x) << S_SRAM1_ENABLE) +#define F_SRAM1_ENABLE V_SRAM1_ENABLE(1U) + +#define A_ARM_SRAM1_READ_DATA 0x47770 + +#define S_SRAM1_READ_DATA 0 +#define M_SRAM1_READ_DATA 0x7fffffU +#define V_SRAM1_READ_DATA(x) ((x) << S_SRAM1_READ_DATA) +#define G_SRAM1_READ_DATA(x) (((x) >> S_SRAM1_READ_DATA) & M_SRAM1_READ_DATA) + +#define A_ARM_SRAM2_WRITE_DATA0 0x47774 +#define A_ARM_SRAM2_WRITE_DATA1 0x47778 +#define A_ARM_SRAM2_WRITE_DATA2 0x4777c +#define A_ARM_SRAM2_WRITE_ADDR 0x47780 + +#define S_SRAM2_WRITE_ADDR 0 +#define M_SRAM2_WRITE_ADDR 0x1fffU +#define V_SRAM2_WRITE_ADDR(x) ((x) << S_SRAM2_WRITE_ADDR) +#define G_SRAM2_WRITE_ADDR(x) (((x) >> S_SRAM2_WRITE_ADDR) & M_SRAM2_WRITE_ADDR) + +#define A_ARM_SRAM2_READ_ADDR 0x47784 + +#define S_SRAM2_READ_ADDR 0 +#define M_SRAM2_READ_ADDR 0x1fffU +#define V_SRAM2_READ_ADDR(x) ((x) << S_SRAM2_READ_ADDR) +#define G_SRAM2_READ_ADDR(x) (((x) >> S_SRAM2_READ_ADDR) & M_SRAM2_READ_ADDR) + +#define A_ARM_SRAM2_CTL 0x47788 + +#define S_SRAM2_WRITE 1 +#define V_SRAM2_WRITE(x) ((x) << S_SRAM2_WRITE) +#define F_SRAM2_WRITE V_SRAM2_WRITE(1U) + +#define S_SRAM2_ENABLE 0 +#define V_SRAM2_ENABLE(x) ((x) << S_SRAM2_ENABLE) +#define F_SRAM2_ENABLE V_SRAM2_ENABLE(1U) + +#define A_ARM_SRAM2_READ_DATA0 0x4778c +#define A_ARM_SRAM2_READ_DATA1 0x47790 +#define A_ARM_SRAM2_READ_DATA2 0x47794 +#define A_ARM_DBPROC_SRAM_CTL 0x47798 + +#define S_DBPROC_RD_EN 0 +#define V_DBPROC_RD_EN(x) ((x) << S_DBPROC_RD_EN) +#define F_DBPROC_RD_EN V_DBPROC_RD_EN(1U) + +#define A_ARM_DBPROC_SRAM_READ_ADDR 0x4779c + +#define S_DBPROC_RD_ADDR 0 +#define M_DBPROC_RD_ADDR 0x1ffU +#define V_DBPROC_RD_ADDR(x) ((x) << S_DBPROC_RD_ADDR) +#define G_DBPROC_RD_ADDR(x) (((x) >> S_DBPROC_RD_ADDR) & M_DBPROC_RD_ADDR) + +#define A_ARM_DBPROC_SRAM_READ_DATA0 0x477a0 +#define A_ARM_DBPROC_SRAM_READ_DATA1 0x477a4 +#define A_ARM_DBPROC_SRAM_READ_DATA2 0x477a8 +#define A_ARM_DBPROC_SRAM_READ_DATA3 0x477ac +#define A_ARM_ATOMICDATA0_1 0x477b0 +#define A_ARM_ATOMICDATA1_1 0x477b4 +#define A_ARM_SPIDEN 0x477b8 + +#define S_SPIDEN 0 +#define V_SPIDEN(x) ((x) << S_SPIDEN) +#define F_SPIDEN V_SPIDEN(1U) + +#define A_ARM_RC_INT_WRITE_DATA 0x477bc + +#define S_RC_INT_STATUS_WRITE_DATA 0 +#define M_RC_INT_STATUS_WRITE_DATA 0x3fU +#define V_RC_INT_STATUS_WRITE_DATA(x) ((x) << S_RC_INT_STATUS_WRITE_DATA) +#define G_RC_INT_STATUS_WRITE_DATA(x) (((x) >> S_RC_INT_STATUS_WRITE_DATA) & M_RC_INT_STATUS_WRITE_DATA) + +#define A_ARM_DFT_MBI 0x477c4 + +#define S_MBISTREQ 3 +#define V_MBISTREQ(x) ((x) << S_MBISTREQ) +#define F_MBISTREQ V_MBISTREQ(1U) + +#define S_MBISTRESETN 2 +#define V_MBISTRESETN(x) ((x) << S_MBISTRESETN) +#define F_MBISTRESETN V_MBISTRESETN(1U) + +#define S_DFTRAMHOLD 1 +#define V_DFTRAMHOLD(x) ((x) << S_DFTRAMHOLD) +#define F_DFTRAMHOLD V_DFTRAMHOLD(1U) + +#define S_DFTCGEN 0 +#define V_DFTCGEN(x) ((x) << S_DFTCGEN) +#define F_DFTCGEN V_DFTCGEN(1U) + +#define A_ARM_DBPROC_SRAM_TH_CTL 0x477c8 + +#define S_DBPROC_TH_WR_EN 1 +#define V_DBPROC_TH_WR_EN(x) ((x) << S_DBPROC_TH_WR_EN) +#define F_DBPROC_TH_WR_EN V_DBPROC_TH_WR_EN(1U) + +#define S_DBPROC_TH_RD_EN 0 +#define V_DBPROC_TH_RD_EN(x) ((x) << S_DBPROC_TH_RD_EN) +#define F_DBPROC_TH_RD_EN V_DBPROC_TH_RD_EN(1U) + +#define A_ARM_MBISTACK 0x477d4 + +#define S_MBISTACK 0 +#define V_MBISTACK(x) ((x) << S_MBISTACK) +#define F_MBISTACK V_MBISTACK(1U) + +#define A_ARM_MBISTADDR 0x477d8 + +#define S_MBISTADDR 0 +#define M_MBISTADDR 0xfffU +#define V_MBISTADDR(x) ((x) << S_MBISTADDR) +#define G_MBISTADDR(x) (((x) >> S_MBISTADDR) & M_MBISTADDR) + +#define A_ARM_MBISTREADEN 0x477dc + +#define S_MBISTREADEN 0 +#define V_MBISTREADEN(x) ((x) << S_MBISTREADEN) +#define F_MBISTREADEN V_MBISTREADEN(1U) + +#define A_ARM_MBISTWRITEEN 0x477e0 + +#define S_MBISTWRITEEN 0 +#define V_MBISTWRITEEN(x) ((x) << S_MBISTWRITEEN) +#define F_MBISTWRITEEN V_MBISTWRITEEN(1U) + +#define A_ARM_MBISTARRAY 0x477e4 + +#define S_MBISTARRAY 0 +#define M_MBISTARRAY 0x3U +#define V_MBISTARRAY(x) ((x) << S_MBISTARRAY) +#define G_MBISTARRAY(x) (((x) >> S_MBISTARRAY) & M_MBISTARRAY) + +#define A_ARM_MBISTCFG 0x477e8 + +#define S_MBISTCFG 0 +#define V_MBISTCFG(x) ((x) << S_MBISTCFG) +#define F_MBISTCFG V_MBISTCFG(1U) + +#define A_ARM_MBISTINDATA0 0x477ec +#define A_ARM_MBISTINDATA1 0x477f0 +#define A_ARM_MBISTOUTDATA1 0x477f4 +#define A_ARM_MBISTOUTDATA0 0x477f8 +#define A_ARM_NVME_DB_EMU_EN 0x477fc + +#define S_NVME_DB_EN 0 +#define V_NVME_DB_EN(x) ((x) << S_NVME_DB_EN) +#define F_NVME_DB_EN V_NVME_DB_EN(1U) + +/* registers for module MC_T70 */ +#define MC_T70_BASE_ADDR 0x48000 + +#define A_MC_IND_ADDR 0x48000 + +#define S_T7_AUTOINCR 30 +#define M_T7_AUTOINCR 0x3U +#define V_T7_AUTOINCR(x) ((x) << S_T7_AUTOINCR) +#define G_T7_AUTOINCR(x) (((x) >> S_T7_AUTOINCR) & M_T7_AUTOINCR) + +#define S_IND_ADDR_ADDR 0 +#define M_IND_ADDR_ADDR 0x1ffffffU +#define V_IND_ADDR_ADDR(x) ((x) << S_IND_ADDR_ADDR) +#define G_IND_ADDR_ADDR(x) (((x) >> S_IND_ADDR_ADDR) & M_IND_ADDR_ADDR) + +#define A_MC_IND_DATA 0x48004 +#define A_MC_DBG_CTL 0x48018 +#define A_MC_DBG_DATA 0x4801c +#define A_T7_MC_P_DDRPHY_RST_CTRL 0x49300 +#define A_T7_MC_P_PERFORMANCE_CTRL 0x49304 +#define A_T7_MC_P_ECC_CTRL 0x49308 + +#define S_BISTECCHBWCTL 7 +#define M_BISTECCHBWCTL 0x3U +#define V_BISTECCHBWCTL(x) ((x) << S_BISTECCHBWCTL) +#define G_BISTECCHBWCTL(x) (((x) >> S_BISTECCHBWCTL) & M_BISTECCHBWCTL) + +#define S_BISTTESTMODE 6 +#define V_BISTTESTMODE(x) ((x) << S_BISTTESTMODE) +#define F_BISTTESTMODE V_BISTTESTMODE(1U) + +#define S_RMW_CTL_CFG 4 +#define M_RMW_CTL_CFG 0x3U +#define V_RMW_CTL_CFG(x) ((x) << S_RMW_CTL_CFG) +#define G_RMW_CTL_CFG(x) (((x) >> S_RMW_CTL_CFG) & M_RMW_CTL_CFG) + +#define A_MC_P_DDRCTL_INT_ENABLE 0x4930c + +#define S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE 5 +#define V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE) +#define F_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(1U) + +#define S_HIF_RDATA_CRC_ERR_DCH1_ENABLE 4 +#define V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_DCH1_ENABLE) +#define F_HIF_RDATA_CRC_ERR_DCH1_ENABLE V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(1U) + +#define S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE 3 +#define V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE) +#define F_HIF_RDATA_ADDR_ERR_DCH1_ENABLE V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(1U) + +#define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE 2 +#define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE) +#define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(1U) + +#define S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE 1 +#define V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE) +#define F_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(1U) + +#define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE 0 +#define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE) +#define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(1U) + +#define A_MC_P_DDRCTL_INT_CAUSE 0x49310 + +#define S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE 25 +#define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE) +#define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U) + +#define S_WR_CRC_ERR_INTR_DCH1_CAUSE 24 +#define V_WR_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH1_CAUSE) +#define F_WR_CRC_ERR_INTR_DCH1_CAUSE V_WR_CRC_ERR_INTR_DCH1_CAUSE(1U) + +#define S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE 23 +#define V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE) +#define F_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U) + +#define S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE 22 +#define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE) +#define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U) + +#define S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE 21 +#define V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE) +#define F_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(1U) + +#define S_SWCMD_ERR_INTR_DCH1_CAUSE 20 +#define V_SWCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH1_CAUSE) +#define F_SWCMD_ERR_INTR_DCH1_CAUSE V_SWCMD_ERR_INTR_DCH1_CAUSE(1U) + +#define S_DUCMD_ERR_INTR_DCH1_CAUSE 19 +#define V_DUCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH1_CAUSE) +#define F_DUCMD_ERR_INTR_DCH1_CAUSE V_DUCMD_ERR_INTR_DCH1_CAUSE(1U) + +#define S_LCCMD_ERR_INTR_DCH1_CAUSE 18 +#define V_LCCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH1_CAUSE) +#define F_LCCMD_ERR_INTR_DCH1_CAUSE V_LCCMD_ERR_INTR_DCH1_CAUSE(1U) + +#define S_CTRLUPD_ERR_INTR_DCH1_CAUSE 17 +#define V_CTRLUPD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH1_CAUSE) +#define F_CTRLUPD_ERR_INTR_DCH1_CAUSE V_CTRLUPD_ERR_INTR_DCH1_CAUSE(1U) + +#define S_RFM_ALERT_INTR_DCH1_CAUSE 16 +#define V_RFM_ALERT_INTR_DCH1_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH1_CAUSE) +#define F_RFM_ALERT_INTR_DCH1_CAUSE V_RFM_ALERT_INTR_DCH1_CAUSE(1U) + +#define S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE 15 +#define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE) +#define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U) + +#define S_WR_CRC_ERR_INTR_DCH0_CAUSE 14 +#define V_WR_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH0_CAUSE) +#define F_WR_CRC_ERR_INTR_DCH0_CAUSE V_WR_CRC_ERR_INTR_DCH0_CAUSE(1U) + +#define S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE 13 +#define V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE) +#define F_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U) + +#define S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE 12 +#define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE) +#define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U) + +#define S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE 11 +#define V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE) +#define F_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(1U) + +#define S_SWCMD_ERR_INTR_DCH0_CAUSE 10 +#define V_SWCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH0_CAUSE) +#define F_SWCMD_ERR_INTR_DCH0_CAUSE V_SWCMD_ERR_INTR_DCH0_CAUSE(1U) + +#define S_DUCMD_ERR_INTR_DCH0_CAUSE 9 +#define V_DUCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH0_CAUSE) +#define F_DUCMD_ERR_INTR_DCH0_CAUSE V_DUCMD_ERR_INTR_DCH0_CAUSE(1U) + +#define S_LCCMD_ERR_INTR_DCH0_CAUSE 8 +#define V_LCCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH0_CAUSE) +#define F_LCCMD_ERR_INTR_DCH0_CAUSE V_LCCMD_ERR_INTR_DCH0_CAUSE(1U) + +#define S_CTRLUPD_ERR_INTR_DCH0_CAUSE 7 +#define V_CTRLUPD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH0_CAUSE) +#define F_CTRLUPD_ERR_INTR_DCH0_CAUSE V_CTRLUPD_ERR_INTR_DCH0_CAUSE(1U) + +#define S_RFM_ALERT_INTR_DCH0_CAUSE 6 +#define V_RFM_ALERT_INTR_DCH0_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH0_CAUSE) +#define F_RFM_ALERT_INTR_DCH0_CAUSE V_RFM_ALERT_INTR_DCH0_CAUSE(1U) + +#define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE 5 +#define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE) +#define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(1U) + +#define S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE 4 +#define V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE) +#define F_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(1U) + +#define S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE 3 +#define V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE) +#define F_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(1U) + +#define S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE 2 +#define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE) +#define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(1U) + +#define S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE 1 +#define V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE) +#define F_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(1U) + +#define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE 0 +#define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE) +#define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(1U) + +#define A_T7_MC_P_PAR_ENABLE 0x49314 + +#define S_HIF_WDATA_Q_PARERR_DCH1_ENABLE 13 +#define V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_ENABLE) +#define F_HIF_WDATA_Q_PARERR_DCH1_ENABLE V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(1U) + +#define S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE 12 +#define V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE) +#define F_DDRCTL_ECC_CE_PAR_DCH1_ENABLE V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(1U) + +#define S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE 11 +#define V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE) +#define F_DDRCTL_ECC_CE_PAR_DCH0_ENABLE V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(1U) + +#define S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE 10 +#define V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE) +#define F_DDRCTL_ECC_UE_PAR_DCH1_ENABLE V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(1U) + +#define S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE 9 +#define V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE) +#define F_DDRCTL_ECC_UE_PAR_DCH0_ENABLE V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(1U) + +#define S_WDATARAM_PARERR_DCH1_ENABLE 8 +#define V_WDATARAM_PARERR_DCH1_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH1_ENABLE) +#define F_WDATARAM_PARERR_DCH1_ENABLE V_WDATARAM_PARERR_DCH1_ENABLE(1U) + +#define S_WDATARAM_PARERR_DCH0_ENABLE 7 +#define V_WDATARAM_PARERR_DCH0_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH0_ENABLE) +#define F_WDATARAM_PARERR_DCH0_ENABLE V_WDATARAM_PARERR_DCH0_ENABLE(1U) + +#define S_BIST_ADDR_FIFO_PARERR_ENABLE 6 +#define V_BIST_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_ENABLE) +#define F_BIST_ADDR_FIFO_PARERR_ENABLE V_BIST_ADDR_FIFO_PARERR_ENABLE(1U) + +#define S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE 5 +#define V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE) +#define F_BIST_ERR_ADDR_FIFO_PARERR_ENABLE V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(1U) + +#define S_HIF_WDATA_Q_PARERR_DCH0_ENABLE 4 +#define V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_ENABLE) +#define F_HIF_WDATA_Q_PARERR_DCH0_ENABLE V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(1U) + +#define S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE 3 +#define V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE) +#define F_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(1U) + +#define S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE 2 +#define V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE) +#define F_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(1U) + +#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE 1 +#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE) +#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(1U) + +#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE 0 +#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE) +#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(1U) + +#define A_T7_MC_P_PAR_CAUSE 0x49318 + +#define S_HIF_WDATA_Q_PARERR_DCH1_CAUSE 13 +#define V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_CAUSE) +#define F_HIF_WDATA_Q_PARERR_DCH1_CAUSE V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(1U) + +#define S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE 12 +#define V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE) +#define F_DDRCTL_ECC_CE_PAR_DCH1_CAUSE V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(1U) + +#define S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE 11 +#define V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE) +#define F_DDRCTL_ECC_CE_PAR_DCH0_CAUSE V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(1U) + +#define S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE 10 +#define V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE) +#define F_DDRCTL_ECC_UE_PAR_DCH1_CAUSE V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(1U) + +#define S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE 9 +#define V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE) +#define F_DDRCTL_ECC_UE_PAR_DCH0_CAUSE V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(1U) + +#define S_WDATARAM_PARERR_DCH1_CAUSE 8 +#define V_WDATARAM_PARERR_DCH1_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH1_CAUSE) +#define F_WDATARAM_PARERR_DCH1_CAUSE V_WDATARAM_PARERR_DCH1_CAUSE(1U) + +#define S_WDATARAM_PARERR_DCH0_CAUSE 7 +#define V_WDATARAM_PARERR_DCH0_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH0_CAUSE) +#define F_WDATARAM_PARERR_DCH0_CAUSE V_WDATARAM_PARERR_DCH0_CAUSE(1U) + +#define S_BIST_ADDR_FIFO_PARERR_CAUSE 6 +#define V_BIST_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_CAUSE) +#define F_BIST_ADDR_FIFO_PARERR_CAUSE V_BIST_ADDR_FIFO_PARERR_CAUSE(1U) + +#define S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE 5 +#define V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE) +#define F_BIST_ERR_ADDR_FIFO_PARERR_CAUSE V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(1U) + +#define S_HIF_WDATA_Q_PARERR_DCH0_CAUSE 4 +#define V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_CAUSE) +#define F_HIF_WDATA_Q_PARERR_DCH0_CAUSE V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(1U) + +#define S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE 3 +#define V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE) +#define F_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(1U) + +#define S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE 2 +#define V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE) +#define F_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(1U) + +#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE 1 +#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE) +#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(1U) + +#define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE 0 +#define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE) +#define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(1U) + +#define A_T7_MC_P_INT_ENABLE 0x4931c + +#define S_DDRPHY_INT_ENABLE 4 +#define V_DDRPHY_INT_ENABLE(x) ((x) << S_DDRPHY_INT_ENABLE) +#define F_DDRPHY_INT_ENABLE V_DDRPHY_INT_ENABLE(1U) + +#define S_DDRCTL_INT_ENABLE 3 +#define V_DDRCTL_INT_ENABLE(x) ((x) << S_DDRCTL_INT_ENABLE) +#define F_DDRCTL_INT_ENABLE V_DDRCTL_INT_ENABLE(1U) + +#define S_T7_ECC_CE_INT_ENABLE 2 +#define V_T7_ECC_CE_INT_ENABLE(x) ((x) << S_T7_ECC_CE_INT_ENABLE) +#define F_T7_ECC_CE_INT_ENABLE V_T7_ECC_CE_INT_ENABLE(1U) + +#define S_T7_ECC_UE_INT_ENABLE 1 +#define V_T7_ECC_UE_INT_ENABLE(x) ((x) << S_T7_ECC_UE_INT_ENABLE) +#define F_T7_ECC_UE_INT_ENABLE V_T7_ECC_UE_INT_ENABLE(1U) + +#define A_T7_MC_P_INT_CAUSE 0x49320 + +#define S_DDRPHY_INT_CAUSE 4 +#define V_DDRPHY_INT_CAUSE(x) ((x) << S_DDRPHY_INT_CAUSE) +#define F_DDRPHY_INT_CAUSE V_DDRPHY_INT_CAUSE(1U) + +#define S_DDRCTL_INT_CAUSE 3 +#define V_DDRCTL_INT_CAUSE(x) ((x) << S_DDRCTL_INT_CAUSE) +#define F_DDRCTL_INT_CAUSE V_DDRCTL_INT_CAUSE(1U) + +#define S_T7_ECC_CE_INT_CAUSE 2 +#define V_T7_ECC_CE_INT_CAUSE(x) ((x) << S_T7_ECC_CE_INT_CAUSE) +#define F_T7_ECC_CE_INT_CAUSE V_T7_ECC_CE_INT_CAUSE(1U) + +#define S_T7_ECC_UE_INT_CAUSE 1 +#define V_T7_ECC_UE_INT_CAUSE(x) ((x) << S_T7_ECC_UE_INT_CAUSE) +#define F_T7_ECC_UE_INT_CAUSE V_T7_ECC_UE_INT_CAUSE(1U) + +#define A_MC_P_ECC_UE_INT_ENABLE 0x49324 + +#define S_BIST_RSP_SRAM_UERR_ENABLE 0 +#define V_BIST_RSP_SRAM_UERR_ENABLE(x) ((x) << S_BIST_RSP_SRAM_UERR_ENABLE) +#define F_BIST_RSP_SRAM_UERR_ENABLE V_BIST_RSP_SRAM_UERR_ENABLE(1U) + +#define A_MC_P_ECC_UE_INT_CAUSE 0x49328 + +#define S_BIST_RSP_SRAM_UERR_CAUSE 0 +#define V_BIST_RSP_SRAM_UERR_CAUSE(x) ((x) << S_BIST_RSP_SRAM_UERR_CAUSE) +#define F_BIST_RSP_SRAM_UERR_CAUSE V_BIST_RSP_SRAM_UERR_CAUSE(1U) + +#define A_T7_MC_P_ECC_STATUS 0x4932c +#define A_T7_MC_P_PHY_CTRL 0x49330 +#define A_T7_MC_P_STATIC_CFG_STATUS 0x49334 + +#define S_DFIFREQRATIO 27 +#define V_DFIFREQRATIO(x) ((x) << S_DFIFREQRATIO) +#define F_DFIFREQRATIO V_DFIFREQRATIO(1U) + +#define S_STATIC_DDR5_HBW_CHANNEL 3 +#define V_STATIC_DDR5_HBW_CHANNEL(x) ((x) << S_STATIC_DDR5_HBW_CHANNEL) +#define F_STATIC_DDR5_HBW_CHANNEL V_STATIC_DDR5_HBW_CHANNEL(1U) + +#define S_STATIC_DDR5_HBW 2 +#define V_STATIC_DDR5_HBW(x) ((x) << S_STATIC_DDR5_HBW) +#define F_STATIC_DDR5_HBW V_STATIC_DDR5_HBW(1U) + +#define S_T7_STATIC_WIDTH 1 +#define V_T7_STATIC_WIDTH(x) ((x) << S_T7_STATIC_WIDTH) +#define F_T7_STATIC_WIDTH V_T7_STATIC_WIDTH(1U) + +#define A_T7_MC_P_CORE_PCTL_STAT 0x49338 +#define A_T7_MC_P_DEBUG_CNT 0x4933c +#define A_T7_MC_CE_ERR_DATA_RDATA 0x49340 +#define A_T7_MC_UE_ERR_DATA_RDATA 0x49380 +#define A_T7_MC_CE_ADDR 0x493c0 +#define A_T7_MC_UE_ADDR 0x493c4 +#define A_T7_MC_P_DEEP_SLEEP 0x493c8 +#define A_T7_MC_P_FPGA_BONUS 0x493cc +#define A_T7_MC_P_DEBUG_CFG 0x493d0 +#define A_T7_MC_P_DEBUG_RPT 0x493d4 +#define A_T7_MC_P_PHY_ADR_CK_EN 0x493d8 +#define A_MC_P_WDATARAM_INIT 0x493dc + +#define S_ENABLE_DCH1 1 +#define V_ENABLE_DCH1(x) ((x) << S_ENABLE_DCH1) +#define F_ENABLE_DCH1 V_ENABLE_DCH1(1U) + +#define S_ENABLE_DCH0 0 +#define V_ENABLE_DCH0(x) ((x) << S_ENABLE_DCH0) +#define F_ENABLE_DCH0 V_ENABLE_DCH0(1U) + +#define A_T7_MC_CE_ERR_ECC_DATA0 0x493e0 +#define A_T7_MC_CE_ERR_ECC_DATA1 0x493e4 +#define A_T7_MC_UE_ERR_ECC_DATA0 0x493e8 +#define A_T7_MC_UE_ERR_ECC_DATA1 0x493ec +#define A_T7_MC_P_RMW_PRIO 0x493f0 +#define A_T7_MC_P_BIST_CMD 0x49400 + +#define S_FIFO_ERROR_FLAG 30 +#define V_FIFO_ERROR_FLAG(x) ((x) << S_FIFO_ERROR_FLAG) +#define F_FIFO_ERROR_FLAG V_FIFO_ERROR_FLAG(1U) + +#define A_T7_MC_P_BIST_CMD_ADDR 0x49404 + +#define S_T7_VALUE 0 +#define M_T7_VALUE 0x1fffffffU +#define V_T7_VALUE(x) ((x) << S_T7_VALUE) +#define G_T7_VALUE(x) (((x) >> S_T7_VALUE) & M_T7_VALUE) + +#define A_MC_P_BIST_NUM_BURST 0x49408 +#define A_T7_MC_P_BIST_DATA_PATTERN 0x4940c + +#define S_DATA_TYPE 0 +#define M_DATA_TYPE 0xfU +#define V_DATA_TYPE(x) ((x) << S_DATA_TYPE) +#define G_DATA_TYPE(x) (((x) >> S_DATA_TYPE) & M_DATA_TYPE) + +#define A_T7_MC_P_BIST_CRC_SEED 0x49410 +#define A_T7_MC_P_BIST_NUM_ERR 0x49460 +#define A_MC_P_BIST_ERR_ADDR 0x49464 + +#define S_ERROR_ADDR 0 +#define M_ERROR_ADDR 0x3fffffffU +#define V_ERROR_ADDR(x) ((x) << S_ERROR_ADDR) +#define G_ERROR_ADDR(x) (((x) >> S_ERROR_ADDR) & M_ERROR_ADDR) + +#define A_MC_P_BIST_USER_RWEDATA 0x49468 +#define A_MC_REGB_DDRC_CH0_SCHED0 0x10380 + +#define S_OPT_VPRW_SCH 31 +#define V_OPT_VPRW_SCH(x) ((x) << S_OPT_VPRW_SCH) +#define F_OPT_VPRW_SCH V_OPT_VPRW_SCH(1U) + +#define S_DIS_SPECULATIVE_ACT 30 +#define V_DIS_SPECULATIVE_ACT(x) ((x) << S_DIS_SPECULATIVE_ACT) +#define F_DIS_SPECULATIVE_ACT V_DIS_SPECULATIVE_ACT(1U) + +#define S_OPT_ACT_LAT 27 +#define V_OPT_ACT_LAT(x) ((x) << S_OPT_ACT_LAT) +#define F_OPT_ACT_LAT V_OPT_ACT_LAT(1U) + +#define S_LPR_NUM_ENTRIES 8 +#define M_LPR_NUM_ENTRIES 0x3fU +#define V_LPR_NUM_ENTRIES(x) ((x) << S_LPR_NUM_ENTRIES) +#define G_LPR_NUM_ENTRIES(x) (((x) >> S_LPR_NUM_ENTRIES) & M_LPR_NUM_ENTRIES) + +#define S_AUTOPRE_RMW 7 +#define V_AUTOPRE_RMW(x) ((x) << S_AUTOPRE_RMW) +#define F_AUTOPRE_RMW V_AUTOPRE_RMW(1U) + +#define S_DIS_OPT_NTT_BY_PRE 6 +#define V_DIS_OPT_NTT_BY_PRE(x) ((x) << S_DIS_OPT_NTT_BY_PRE) +#define F_DIS_OPT_NTT_BY_PRE V_DIS_OPT_NTT_BY_PRE(1U) + +#define S_DIS_OPT_NTT_BY_ACT 5 +#define V_DIS_OPT_NTT_BY_ACT(x) ((x) << S_DIS_OPT_NTT_BY_ACT) +#define F_DIS_OPT_NTT_BY_ACT V_DIS_OPT_NTT_BY_ACT(1U) + +#define S_OPT_WRCAM_FILL_LEVEL 4 +#define V_OPT_WRCAM_FILL_LEVEL(x) ((x) << S_OPT_WRCAM_FILL_LEVEL) +#define F_OPT_WRCAM_FILL_LEVEL V_OPT_WRCAM_FILL_LEVEL(1U) + +#define S_PAGECLOSE 2 +#define V_PAGECLOSE(x) ((x) << S_PAGECLOSE) +#define F_PAGECLOSE V_PAGECLOSE(1U) + +#define S_PREFER_WRITE 1 +#define V_PREFER_WRITE(x) ((x) << S_PREFER_WRITE) +#define F_PREFER_WRITE V_PREFER_WRITE(1U) + +#define A_MC_REGB_DDRC_CH0_ECCCFG0 0x10600 + +#define S_DIS_SCRUB 23 +#define V_DIS_SCRUB(x) ((x) << S_DIS_SCRUB) +#define F_DIS_SCRUB V_DIS_SCRUB(1U) + +#define S_ECC_TYPE 4 +#define M_ECC_TYPE 0x3U +#define V_ECC_TYPE(x) ((x) << S_ECC_TYPE) +#define G_ECC_TYPE(x) (((x) >> S_ECC_TYPE) & M_ECC_TYPE) + +#define S_TEST_MODE 3 +#define V_TEST_MODE(x) ((x) << S_TEST_MODE) +#define F_TEST_MODE V_TEST_MODE(1U) + +#define S_ECC_MODE 0 +#define M_ECC_MODE 0x7U +#define V_ECC_MODE(x) ((x) << S_ECC_MODE) +#define G_ECC_MODE(x) (((x) >> S_ECC_MODE) & M_ECC_MODE) + +#define A_MC_REGB_DDRC_CH0_ECCCFG1 0x10604 + +#define S_DATA_POISON_BIT 1 +#define V_DATA_POISON_BIT(x) ((x) << S_DATA_POISON_BIT) +#define F_DATA_POISON_BIT V_DATA_POISON_BIT(1U) + +#define S_DATA_POISON_EN 0 +#define V_DATA_POISON_EN(x) ((x) << S_DATA_POISON_EN) +#define F_DATA_POISON_EN V_DATA_POISON_EN(1U) + +#define A_MC_REGB_DDRC_CH0_ECCSTAT 0x10608 + +#define S_ECC_UNCORRECTED_ERR 16 +#define M_ECC_UNCORRECTED_ERR 0xffU +#define V_ECC_UNCORRECTED_ERR(x) ((x) << S_ECC_UNCORRECTED_ERR) +#define G_ECC_UNCORRECTED_ERR(x) (((x) >> S_ECC_UNCORRECTED_ERR) & M_ECC_UNCORRECTED_ERR) + +#define S_ECC_CORRECTED_ERR 8 +#define M_ECC_CORRECTED_ERR 0xffU +#define V_ECC_CORRECTED_ERR(x) ((x) << S_ECC_CORRECTED_ERR) +#define G_ECC_CORRECTED_ERR(x) (((x) >> S_ECC_CORRECTED_ERR) & M_ECC_CORRECTED_ERR) + +#define S_ECC_CORRECTED_BIT_NUM 0 +#define M_ECC_CORRECTED_BIT_NUM 0x7fU +#define V_ECC_CORRECTED_BIT_NUM(x) ((x) << S_ECC_CORRECTED_BIT_NUM) +#define G_ECC_CORRECTED_BIT_NUM(x) (((x) >> S_ECC_CORRECTED_BIT_NUM) & M_ECC_CORRECTED_BIT_NUM) + +#define A_MC_REGB_DDRC_CH0_ECCCTL 0x1060c + +#define S_ECC_UNCORRECTED_ERR_INTR_FORCE 17 +#define V_ECC_UNCORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_FORCE) +#define F_ECC_UNCORRECTED_ERR_INTR_FORCE V_ECC_UNCORRECTED_ERR_INTR_FORCE(1U) + +#define S_ECC_CORRECTED_ERR_INTR_FORCE 16 +#define V_ECC_CORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_CORRECTED_ERR_INTR_FORCE) +#define F_ECC_CORRECTED_ERR_INTR_FORCE V_ECC_CORRECTED_ERR_INTR_FORCE(1U) + +#define S_ECC_UNCORRECTED_ERR_INTR_EN 9 +#define V_ECC_UNCORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_EN) +#define F_ECC_UNCORRECTED_ERR_INTR_EN V_ECC_UNCORRECTED_ERR_INTR_EN(1U) + +#define S_ECC_CORRECTED_ERR_INTR_EN 8 +#define V_ECC_CORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_CORRECTED_ERR_INTR_EN) +#define F_ECC_CORRECTED_ERR_INTR_EN V_ECC_CORRECTED_ERR_INTR_EN(1U) + +#define S_ECC_UNCORR_ERR_CNT_CLR 3 +#define V_ECC_UNCORR_ERR_CNT_CLR(x) ((x) << S_ECC_UNCORR_ERR_CNT_CLR) +#define F_ECC_UNCORR_ERR_CNT_CLR V_ECC_UNCORR_ERR_CNT_CLR(1U) + +#define S_ECC_CORR_ERR_CNT_CLR 2 +#define V_ECC_CORR_ERR_CNT_CLR(x) ((x) << S_ECC_CORR_ERR_CNT_CLR) +#define F_ECC_CORR_ERR_CNT_CLR V_ECC_CORR_ERR_CNT_CLR(1U) + +#define S_ECC_UNCORRECTED_ERR_CLR 1 +#define V_ECC_UNCORRECTED_ERR_CLR(x) ((x) << S_ECC_UNCORRECTED_ERR_CLR) +#define F_ECC_UNCORRECTED_ERR_CLR V_ECC_UNCORRECTED_ERR_CLR(1U) + +#define S_ECC_CORRECTED_ERR_CLR 0 +#define V_ECC_CORRECTED_ERR_CLR(x) ((x) << S_ECC_CORRECTED_ERR_CLR) +#define F_ECC_CORRECTED_ERR_CLR V_ECC_CORRECTED_ERR_CLR(1U) + +#define A_MC_REGB_DDRC_CH0_ECCERRCNT 0x10610 + +#define S_ECC_UNCORR_ERR_CNT 16 +#define M_ECC_UNCORR_ERR_CNT 0xffffU +#define V_ECC_UNCORR_ERR_CNT(x) ((x) << S_ECC_UNCORR_ERR_CNT) +#define G_ECC_UNCORR_ERR_CNT(x) (((x) >> S_ECC_UNCORR_ERR_CNT) & M_ECC_UNCORR_ERR_CNT) + +#define S_ECC_CORR_ERR_CNT 0 +#define M_ECC_CORR_ERR_CNT 0xffffU +#define V_ECC_CORR_ERR_CNT(x) ((x) << S_ECC_CORR_ERR_CNT) +#define G_ECC_CORR_ERR_CNT(x) (((x) >> S_ECC_CORR_ERR_CNT) & M_ECC_CORR_ERR_CNT) + +#define A_MC_REGB_DDRC_CH0_ECCCADDR0 0x10614 + +#define S_ECC_CORR_RANK 24 +#define V_ECC_CORR_RANK(x) ((x) << S_ECC_CORR_RANK) +#define F_ECC_CORR_RANK V_ECC_CORR_RANK(1U) + +#define S_ECC_CORR_ROW 0 +#define M_ECC_CORR_ROW 0x3ffffU +#define V_ECC_CORR_ROW(x) ((x) << S_ECC_CORR_ROW) +#define G_ECC_CORR_ROW(x) (((x) >> S_ECC_CORR_ROW) & M_ECC_CORR_ROW) + +#define A_MC_REGB_DDRC_CH0_ECCCADDR1 0x10618 + +#define S_ECC_CORR_BG 24 +#define M_ECC_CORR_BG 0x7U +#define V_ECC_CORR_BG(x) ((x) << S_ECC_CORR_BG) +#define G_ECC_CORR_BG(x) (((x) >> S_ECC_CORR_BG) & M_ECC_CORR_BG) + +#define S_ECC_CORR_BANK 16 +#define M_ECC_CORR_BANK 0x3U +#define V_ECC_CORR_BANK(x) ((x) << S_ECC_CORR_BANK) +#define G_ECC_CORR_BANK(x) (((x) >> S_ECC_CORR_BANK) & M_ECC_CORR_BANK) + +#define S_ECC_CORR_COL 0 +#define M_ECC_CORR_COL 0x7ffU +#define V_ECC_CORR_COL(x) ((x) << S_ECC_CORR_COL) +#define G_ECC_CORR_COL(x) (((x) >> S_ECC_CORR_COL) & M_ECC_CORR_COL) + +#define A_MC_REGB_DDRC_CH0_ECCCSYN0 0x1061c +#define A_MC_REGB_DDRC_CH0_ECCCSYN1 0x10620 +#define A_MC_REGB_DDRC_CH0_ECCCSYN2 0x10624 + +#define S_CB_CORR_SYNDROME 16 +#define M_CB_CORR_SYNDROME 0xffU +#define V_CB_CORR_SYNDROME(x) ((x) << S_CB_CORR_SYNDROME) +#define G_CB_CORR_SYNDROME(x) (((x) >> S_CB_CORR_SYNDROME) & M_CB_CORR_SYNDROME) + +#define S_ECC_CORR_SYNDROMES_71_64 0 +#define M_ECC_CORR_SYNDROMES_71_64 0xffU +#define V_ECC_CORR_SYNDROMES_71_64(x) ((x) << S_ECC_CORR_SYNDROMES_71_64) +#define G_ECC_CORR_SYNDROMES_71_64(x) (((x) >> S_ECC_CORR_SYNDROMES_71_64) & M_ECC_CORR_SYNDROMES_71_64) + +#define A_MC_REGB_DDRC_CH0_ECCBITMASK0 0x10628 +#define A_MC_REGB_DDRC_CH0_ECCBITMASK1 0x1062c +#define A_MC_REGB_DDRC_CH0_ECCBITMASK2 0x10630 + +#define S_ECC_CORR_BIT_MASK_71_64 0 +#define M_ECC_CORR_BIT_MASK_71_64 0xffU +#define V_ECC_CORR_BIT_MASK_71_64(x) ((x) << S_ECC_CORR_BIT_MASK_71_64) +#define G_ECC_CORR_BIT_MASK_71_64(x) (((x) >> S_ECC_CORR_BIT_MASK_71_64) & M_ECC_CORR_BIT_MASK_71_64) + +#define A_MC_REGB_DDRC_CH0_ECCUADDR0 0x10634 + +#define S_ECC_UNCORR_RANK 24 +#define V_ECC_UNCORR_RANK(x) ((x) << S_ECC_UNCORR_RANK) +#define F_ECC_UNCORR_RANK V_ECC_UNCORR_RANK(1U) + +#define S_ECC_UNCORR_ROW 0 +#define M_ECC_UNCORR_ROW 0x3ffffU +#define V_ECC_UNCORR_ROW(x) ((x) << S_ECC_UNCORR_ROW) +#define G_ECC_UNCORR_ROW(x) (((x) >> S_ECC_UNCORR_ROW) & M_ECC_UNCORR_ROW) + +#define A_MC_REGB_DDRC_CH0_ECCUADDR1 0x10638 + +#define S_ECC_UNCORR_BG 24 +#define M_ECC_UNCORR_BG 0x7U +#define V_ECC_UNCORR_BG(x) ((x) << S_ECC_UNCORR_BG) +#define G_ECC_UNCORR_BG(x) (((x) >> S_ECC_UNCORR_BG) & M_ECC_UNCORR_BG) + +#define S_ECC_UNCORR_BANK 16 +#define M_ECC_UNCORR_BANK 0x3U +#define V_ECC_UNCORR_BANK(x) ((x) << S_ECC_UNCORR_BANK) +#define G_ECC_UNCORR_BANK(x) (((x) >> S_ECC_UNCORR_BANK) & M_ECC_UNCORR_BANK) + +#define S_ECC_UNCORR_COL 0 +#define M_ECC_UNCORR_COL 0x7ffU +#define V_ECC_UNCORR_COL(x) ((x) << S_ECC_UNCORR_COL) +#define G_ECC_UNCORR_COL(x) (((x) >> S_ECC_UNCORR_COL) & M_ECC_UNCORR_COL) + +#define A_MC_REGB_DDRC_CH0_ECCUSYN0 0x1063c +#define A_MC_REGB_DDRC_CH0_ECCUSYN1 0x10640 +#define A_MC_REGB_DDRC_CH0_ECCUSYN2 0x10644 + +#define S_CB_UNCORR_SYNDROME 16 +#define M_CB_UNCORR_SYNDROME 0xffU +#define V_CB_UNCORR_SYNDROME(x) ((x) << S_CB_UNCORR_SYNDROME) +#define G_CB_UNCORR_SYNDROME(x) (((x) >> S_CB_UNCORR_SYNDROME) & M_CB_UNCORR_SYNDROME) + +#define S_ECC_UNCORR_SYNDROMES_71_64 0 +#define M_ECC_UNCORR_SYNDROMES_71_64 0xffU +#define V_ECC_UNCORR_SYNDROMES_71_64(x) ((x) << S_ECC_UNCORR_SYNDROMES_71_64) +#define G_ECC_UNCORR_SYNDROMES_71_64(x) (((x) >> S_ECC_UNCORR_SYNDROMES_71_64) & M_ECC_UNCORR_SYNDROMES_71_64) + +#define A_MC_REGB_DDRC_CH0_ECCPOISONADDR0 0x10648 + +#define S_ECC_POISON_RANK 24 +#define V_ECC_POISON_RANK(x) ((x) << S_ECC_POISON_RANK) +#define F_ECC_POISON_RANK V_ECC_POISON_RANK(1U) + +#define S_ECC_POISON_COL 0 +#define M_ECC_POISON_COL 0xfffU +#define V_ECC_POISON_COL(x) ((x) << S_ECC_POISON_COL) +#define G_ECC_POISON_COL(x) (((x) >> S_ECC_POISON_COL) & M_ECC_POISON_COL) + +#define A_MC_REGB_DDRC_CH0_ECCPOISONADDR1 0x1064c + +#define S_ECC_POISON_BG 28 +#define M_ECC_POISON_BG 0x7U +#define V_ECC_POISON_BG(x) ((x) << S_ECC_POISON_BG) +#define G_ECC_POISON_BG(x) (((x) >> S_ECC_POISON_BG) & M_ECC_POISON_BG) + +#define S_ECC_POISON_BANK 24 +#define M_ECC_POISON_BANK 0x3U +#define V_ECC_POISON_BANK(x) ((x) << S_ECC_POISON_BANK) +#define G_ECC_POISON_BANK(x) (((x) >> S_ECC_POISON_BANK) & M_ECC_POISON_BANK) + +#define S_ECC_POISON_ROW 0 +#define M_ECC_POISON_ROW 0x3ffffU +#define V_ECC_POISON_ROW(x) ((x) << S_ECC_POISON_ROW) +#define G_ECC_POISON_ROW(x) (((x) >> S_ECC_POISON_ROW) & M_ECC_POISON_ROW) + +#define A_MC_REGB_DDRC_CH0_ECCPOISONPAT0 0x10658 +#define A_MC_REGB_DDRC_CH0_ECCPOISONPAT1 0x1065c +#define A_MC_REGB_DDRC_CH0_ECCPOISONPAT2 0x10660 + +#define S_ECC_POISON_DATA_71_64 0 +#define M_ECC_POISON_DATA_71_64 0xffU +#define V_ECC_POISON_DATA_71_64(x) ((x) << S_ECC_POISON_DATA_71_64) +#define G_ECC_POISON_DATA_71_64(x) (((x) >> S_ECC_POISON_DATA_71_64) & M_ECC_POISON_DATA_71_64) + +#define A_MC_REGB_DDRC_CH0_ECCCFG2 0x10668 + +#define S_FLIP_BIT_POS1 24 +#define M_FLIP_BIT_POS1 0x7fU +#define V_FLIP_BIT_POS1(x) ((x) << S_FLIP_BIT_POS1) +#define G_FLIP_BIT_POS1(x) (((x) >> S_FLIP_BIT_POS1) & M_FLIP_BIT_POS1) + +#define S_FLIP_BIT_POS0 16 +#define M_FLIP_BIT_POS0 0x7fU +#define V_FLIP_BIT_POS0(x) ((x) << S_FLIP_BIT_POS0) +#define G_FLIP_BIT_POS0(x) (((x) >> S_FLIP_BIT_POS0) & M_FLIP_BIT_POS0) + +#define A_MC_REGB_DDRC_CH1_ECCCTL 0x1160c +#define A_MC_REGB_DDRC_CH1_ECCERRCNT 0x11610 +#define A_MC_REGB_DDRC_CH1_ECCCADDR0 0x11614 +#define A_MC_REGB_DDRC_CH1_ECCCADDR1 0x11618 +#define A_MC_REGB_DDRC_CH1_ECCCSYN0 0x1161c +#define A_MC_REGB_DDRC_CH1_ECCCSYN1 0x11620 +#define A_MC_REGB_DDRC_CH1_ECCCSYN2 0x11624 +#define A_MC_REGB_DDRC_CH1_ECCBITMASK0 0x11628 +#define A_MC_REGB_DDRC_CH1_ECCBITMASK1 0x1162c +#define A_MC_REGB_DDRC_CH1_ECCBITMASK2 0x11630 +#define A_MC_REGB_DDRC_CH1_ECCUADDR0 0x11634 +#define A_MC_REGB_DDRC_CH1_ECCUADDR1 0x11638 +#define A_MC_REGB_DDRC_CH1_ECCUSYN0 0x1163c +#define A_MC_REGB_DDRC_CH1_ECCUSYN1 0x11640 +#define A_MC_REGB_DDRC_CH1_ECCUSYN2 0x11644 +#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTENABLE 0x20100 + +#define S_PHYSTICKYUNLOCKEN 15 +#define V_PHYSTICKYUNLOCKEN(x) ((x) << S_PHYSTICKYUNLOCKEN) +#define F_PHYSTICKYUNLOCKEN V_PHYSTICKYUNLOCKEN(1U) + +#define S_PHYBSIEN 14 +#define V_PHYBSIEN(x) ((x) << S_PHYBSIEN) +#define F_PHYBSIEN V_PHYBSIEN(1U) + +#define S_PHYANIBRCVERREN 13 +#define V_PHYANIBRCVERREN(x) ((x) << S_PHYANIBRCVERREN) +#define F_PHYANIBRCVERREN V_PHYANIBRCVERREN(1U) + +#define S_PHYD5ACSM1PARITYEN 12 +#define V_PHYD5ACSM1PARITYEN(x) ((x) << S_PHYD5ACSM1PARITYEN) +#define F_PHYD5ACSM1PARITYEN V_PHYD5ACSM1PARITYEN(1U) + +#define S_PHYD5ACSM0PARITYEN 11 +#define V_PHYD5ACSM0PARITYEN(x) ((x) << S_PHYD5ACSM0PARITYEN) +#define F_PHYD5ACSM0PARITYEN V_PHYD5ACSM0PARITYEN(1U) + +#define S_PHYRXFIFOCHECKEN 10 +#define V_PHYRXFIFOCHECKEN(x) ((x) << S_PHYRXFIFOCHECKEN) +#define F_PHYRXFIFOCHECKEN V_PHYRXFIFOCHECKEN(1U) + +#define S_PHYTXPPTEN 9 +#define V_PHYTXPPTEN(x) ((x) << S_PHYTXPPTEN) +#define F_PHYTXPPTEN V_PHYTXPPTEN(1U) + +#define S_PHYECCEN 8 +#define V_PHYECCEN(x) ((x) << S_PHYECCEN) +#define F_PHYECCEN V_PHYECCEN(1U) + +#define S_PHYFWRESERVEDEN 3 +#define M_PHYFWRESERVEDEN 0x1fU +#define V_PHYFWRESERVEDEN(x) ((x) << S_PHYFWRESERVEDEN) +#define G_PHYFWRESERVEDEN(x) (((x) >> S_PHYFWRESERVEDEN) & M_PHYFWRESERVEDEN) + +#define S_PHYTRNGFAILEN 2 +#define V_PHYTRNGFAILEN(x) ((x) << S_PHYTRNGFAILEN) +#define F_PHYTRNGFAILEN V_PHYTRNGFAILEN(1U) + +#define S_PHYINITCMPLTEN 1 +#define V_PHYINITCMPLTEN(x) ((x) << S_PHYINITCMPLTEN) +#define F_PHYINITCMPLTEN V_PHYINITCMPLTEN(1U) + +#define S_PHYTRNGCMPLTEN 0 +#define V_PHYTRNGCMPLTEN(x) ((x) << S_PHYTRNGCMPLTEN) +#define F_PHYTRNGCMPLTEN V_PHYTRNGCMPLTEN(1U) + +#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTFWCONTROL 0x20101 + +#define S_PHYFWRESERVEDFW 3 +#define M_PHYFWRESERVEDFW 0x1fU +#define V_PHYFWRESERVEDFW(x) ((x) << S_PHYFWRESERVEDFW) +#define G_PHYFWRESERVEDFW(x) (((x) >> S_PHYFWRESERVEDFW) & M_PHYFWRESERVEDFW) + +#define S_PHYTRNGFAILFW 2 +#define V_PHYTRNGFAILFW(x) ((x) << S_PHYTRNGFAILFW) +#define F_PHYTRNGFAILFW V_PHYTRNGFAILFW(1U) + +#define S_PHYINITCMPLTFW 1 +#define V_PHYINITCMPLTFW(x) ((x) << S_PHYINITCMPLTFW) +#define F_PHYINITCMPLTFW V_PHYINITCMPLTFW(1U) + +#define S_PHYTRNGCMPLTFW 0 +#define V_PHYTRNGCMPLTFW(x) ((x) << S_PHYTRNGCMPLTFW) +#define F_PHYTRNGCMPLTFW V_PHYTRNGCMPLTFW(1U) + +#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTMASK 0x20102 + +#define S_PHYSTICKYUNLOCKMSK 15 +#define V_PHYSTICKYUNLOCKMSK(x) ((x) << S_PHYSTICKYUNLOCKMSK) +#define F_PHYSTICKYUNLOCKMSK V_PHYSTICKYUNLOCKMSK(1U) + +#define S_PHYBSIMSK 14 +#define V_PHYBSIMSK(x) ((x) << S_PHYBSIMSK) +#define F_PHYBSIMSK V_PHYBSIMSK(1U) + +#define S_PHYANIBRCVERRMSK 13 +#define V_PHYANIBRCVERRMSK(x) ((x) << S_PHYANIBRCVERRMSK) +#define F_PHYANIBRCVERRMSK V_PHYANIBRCVERRMSK(1U) + +#define S_PHYD5ACSM1PARITYMSK 12 +#define V_PHYD5ACSM1PARITYMSK(x) ((x) << S_PHYD5ACSM1PARITYMSK) +#define F_PHYD5ACSM1PARITYMSK V_PHYD5ACSM1PARITYMSK(1U) + +#define S_PHYD5ACSM0PARITYMSK 11 +#define V_PHYD5ACSM0PARITYMSK(x) ((x) << S_PHYD5ACSM0PARITYMSK) +#define F_PHYD5ACSM0PARITYMSK V_PHYD5ACSM0PARITYMSK(1U) + +#define S_PHYRXFIFOCHECKMSK 10 +#define V_PHYRXFIFOCHECKMSK(x) ((x) << S_PHYRXFIFOCHECKMSK) +#define F_PHYRXFIFOCHECKMSK V_PHYRXFIFOCHECKMSK(1U) + +#define S_PHYTXPPTMSK 9 +#define V_PHYTXPPTMSK(x) ((x) << S_PHYTXPPTMSK) +#define F_PHYTXPPTMSK V_PHYTXPPTMSK(1U) + +#define S_PHYECCMSK 8 +#define V_PHYECCMSK(x) ((x) << S_PHYECCMSK) +#define F_PHYECCMSK V_PHYECCMSK(1U) + +#define S_PHYFWRESERVEDMSK 3 +#define M_PHYFWRESERVEDMSK 0x1fU +#define V_PHYFWRESERVEDMSK(x) ((x) << S_PHYFWRESERVEDMSK) +#define G_PHYFWRESERVEDMSK(x) (((x) >> S_PHYFWRESERVEDMSK) & M_PHYFWRESERVEDMSK) + +#define S_PHYTRNGFAILMSK 2 +#define V_PHYTRNGFAILMSK(x) ((x) << S_PHYTRNGFAILMSK) +#define F_PHYTRNGFAILMSK V_PHYTRNGFAILMSK(1U) + +#define S_PHYINITCMPLTMSK 1 +#define V_PHYINITCMPLTMSK(x) ((x) << S_PHYINITCMPLTMSK) +#define F_PHYINITCMPLTMSK V_PHYINITCMPLTMSK(1U) + +#define S_PHYTRNGCMPLTMSK 0 +#define V_PHYTRNGCMPLTMSK(x) ((x) << S_PHYTRNGCMPLTMSK) +#define F_PHYTRNGCMPLTMSK V_PHYTRNGCMPLTMSK(1U) + +#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTCLEAR 0x20103 + +#define S_PHYSTICKYUNLOCKCLR 15 +#define V_PHYSTICKYUNLOCKCLR(x) ((x) << S_PHYSTICKYUNLOCKCLR) +#define F_PHYSTICKYUNLOCKCLR V_PHYSTICKYUNLOCKCLR(1U) + +#define S_PHYBSICLR 14 +#define V_PHYBSICLR(x) ((x) << S_PHYBSICLR) +#define F_PHYBSICLR V_PHYBSICLR(1U) + +#define S_PHYANIBRCVERRCLR 13 +#define V_PHYANIBRCVERRCLR(x) ((x) << S_PHYANIBRCVERRCLR) +#define F_PHYANIBRCVERRCLR V_PHYANIBRCVERRCLR(1U) + +#define S_PHYD5ACSM1PARITYCLR 12 +#define V_PHYD5ACSM1PARITYCLR(x) ((x) << S_PHYD5ACSM1PARITYCLR) +#define F_PHYD5ACSM1PARITYCLR V_PHYD5ACSM1PARITYCLR(1U) + +#define S_PHYD5ACSM0PARITYCLR 11 +#define V_PHYD5ACSM0PARITYCLR(x) ((x) << S_PHYD5ACSM0PARITYCLR) +#define F_PHYD5ACSM0PARITYCLR V_PHYD5ACSM0PARITYCLR(1U) + +#define S_PHYRXFIFOCHECKCLR 10 +#define V_PHYRXFIFOCHECKCLR(x) ((x) << S_PHYRXFIFOCHECKCLR) +#define F_PHYRXFIFOCHECKCLR V_PHYRXFIFOCHECKCLR(1U) + +#define S_PHYTXPPTCLR 9 +#define V_PHYTXPPTCLR(x) ((x) << S_PHYTXPPTCLR) +#define F_PHYTXPPTCLR V_PHYTXPPTCLR(1U) + +#define S_PHYECCCLR 8 +#define V_PHYECCCLR(x) ((x) << S_PHYECCCLR) +#define F_PHYECCCLR V_PHYECCCLR(1U) + +#define S_PHYFWRESERVEDCLR 3 +#define M_PHYFWRESERVEDCLR 0x1fU +#define V_PHYFWRESERVEDCLR(x) ((x) << S_PHYFWRESERVEDCLR) +#define G_PHYFWRESERVEDCLR(x) (((x) >> S_PHYFWRESERVEDCLR) & M_PHYFWRESERVEDCLR) + +#define S_PHYTRNGFAILCLR 2 +#define V_PHYTRNGFAILCLR(x) ((x) << S_PHYTRNGFAILCLR) +#define F_PHYTRNGFAILCLR V_PHYTRNGFAILCLR(1U) + +#define S_PHYINITCMPLTCLR 1 +#define V_PHYINITCMPLTCLR(x) ((x) << S_PHYINITCMPLTCLR) +#define F_PHYINITCMPLTCLR V_PHYINITCMPLTCLR(1U) + +#define S_PHYTRNGCMPLTCLR 0 +#define V_PHYTRNGCMPLTCLR(x) ((x) << S_PHYTRNGCMPLTCLR) +#define F_PHYTRNGCMPLTCLR V_PHYTRNGCMPLTCLR(1U) + +#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTSTATUS 0x20104 + +#define S_PHYSTICKYUNLOCKERR 15 +#define V_PHYSTICKYUNLOCKERR(x) ((x) << S_PHYSTICKYUNLOCKERR) +#define F_PHYSTICKYUNLOCKERR V_PHYSTICKYUNLOCKERR(1U) + +#define S_PHYBSIINT 14 +#define V_PHYBSIINT(x) ((x) << S_PHYBSIINT) +#define F_PHYBSIINT V_PHYBSIINT(1U) + +#define S_PHYANIBRCVERR 13 +#define V_PHYANIBRCVERR(x) ((x) << S_PHYANIBRCVERR) +#define F_PHYANIBRCVERR V_PHYANIBRCVERR(1U) + +#define S_PHYD5ACSM1PARITYERR 12 +#define V_PHYD5ACSM1PARITYERR(x) ((x) << S_PHYD5ACSM1PARITYERR) +#define F_PHYD5ACSM1PARITYERR V_PHYD5ACSM1PARITYERR(1U) + +#define S_PHYD5ACSM0PARITYERR 11 +#define V_PHYD5ACSM0PARITYERR(x) ((x) << S_PHYD5ACSM0PARITYERR) +#define F_PHYD5ACSM0PARITYERR V_PHYD5ACSM0PARITYERR(1U) + +#define S_PHYRXFIFOCHECKERR 10 +#define V_PHYRXFIFOCHECKERR(x) ((x) << S_PHYRXFIFOCHECKERR) +#define F_PHYRXFIFOCHECKERR V_PHYRXFIFOCHECKERR(1U) + +#define S_PHYRXTXPPTERR 9 +#define V_PHYRXTXPPTERR(x) ((x) << S_PHYRXTXPPTERR) +#define F_PHYRXTXPPTERR V_PHYRXTXPPTERR(1U) + +#define S_PHYECCERR 8 +#define V_PHYECCERR(x) ((x) << S_PHYECCERR) +#define F_PHYECCERR V_PHYECCERR(1U) + +#define S_PHYFWRESERVED 3 +#define M_PHYFWRESERVED 0x1fU +#define V_PHYFWRESERVED(x) ((x) << S_PHYFWRESERVED) +#define G_PHYFWRESERVED(x) (((x) >> S_PHYFWRESERVED) & M_PHYFWRESERVED) + +#define S_PHYTRNGFAIL 2 +#define V_PHYTRNGFAIL(x) ((x) << S_PHYTRNGFAIL) +#define F_PHYTRNGFAIL V_PHYTRNGFAIL(1U) + +#define S_PHYINITCMPLT 1 +#define V_PHYINITCMPLT(x) ((x) << S_PHYINITCMPLT) +#define F_PHYINITCMPLT V_PHYINITCMPLT(1U) + +#define S_PHYTRNGCMPLT 0 +#define V_PHYTRNGCMPLT(x) ((x) << S_PHYTRNGCMPLT) +#define F_PHYTRNGCMPLT V_PHYTRNGCMPLT(1U) + +#define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTOVERRIDE 0x20107 + +#define S_PHYINTERRUPTOVERRIDE 0 +#define M_PHYINTERRUPTOVERRIDE 0xffffU +#define V_PHYINTERRUPTOVERRIDE(x) ((x) << S_PHYINTERRUPTOVERRIDE) +#define G_PHYINTERRUPTOVERRIDE(x) (((x) >> S_PHYINTERRUPTOVERRIDE) & M_PHYINTERRUPTOVERRIDE) + +/* registers for module MC_T71 */ +#define MC_T71_BASE_ADDR 0x58000 + +/* registers for module GCACHE */ +#define GCACHE_BASE_ADDR 0x51400 + +#define A_GCACHE_MODE_SEL0 0x51400 + +#define S_GC_MA_RSP 16 +#define V_GC_MA_RSP(x) ((x) << S_GC_MA_RSP) +#define F_GC_MA_RSP V_GC_MA_RSP(1U) + +#define A_GCACHE_MEMZONE0_REGION1 0x51404 + +#define S_REGION_EN1 18 +#define V_REGION_EN1(x) ((x) << S_REGION_EN1) +#define F_REGION_EN1 V_REGION_EN1(1U) + +#define S_EDC_REGION1 17 +#define V_EDC_REGION1(x) ((x) << S_EDC_REGION1) +#define F_EDC_REGION1 V_EDC_REGION1(1U) + +#define S_CACHE_REGION1 16 +#define V_CACHE_REGION1(x) ((x) << S_CACHE_REGION1) +#define F_CACHE_REGION1 V_CACHE_REGION1(1U) + +#define S_END1 0 +#define M_END1 0xffffU +#define V_END1(x) ((x) << S_END1) +#define G_END1(x) (((x) >> S_END1) & M_END1) + +#define A_GCACHE_MEMZONE0_REGION2 0x51408 + +#define S_REGION_EN2 18 +#define V_REGION_EN2(x) ((x) << S_REGION_EN2) +#define F_REGION_EN2 V_REGION_EN2(1U) + +#define S_EDC_REGION2 17 +#define V_EDC_REGION2(x) ((x) << S_EDC_REGION2) +#define F_EDC_REGION2 V_EDC_REGION2(1U) + +#define S_CACHE_REGION2 16 +#define V_CACHE_REGION2(x) ((x) << S_CACHE_REGION2) +#define F_CACHE_REGION2 V_CACHE_REGION2(1U) + +#define S_END2 0 +#define M_END2 0xffffU +#define V_END2(x) ((x) << S_END2) +#define G_END2(x) (((x) >> S_END2) & M_END2) + +#define A_GCACHE_MEMZONE0_REGION3 0x5140c + +#define S_REGION_EN3 18 +#define V_REGION_EN3(x) ((x) << S_REGION_EN3) +#define F_REGION_EN3 V_REGION_EN3(1U) + +#define S_EDC_REGION3 17 +#define V_EDC_REGION3(x) ((x) << S_EDC_REGION3) +#define F_EDC_REGION3 V_EDC_REGION3(1U) + +#define S_CACHE_REGION3 16 +#define V_CACHE_REGION3(x) ((x) << S_CACHE_REGION3) +#define F_CACHE_REGION3 V_CACHE_REGION3(1U) + +#define S_END3 0 +#define M_END3 0xffffU +#define V_END3(x) ((x) << S_END3) +#define G_END3(x) (((x) >> S_END3) & M_END3) + +#define A_GCACHE_MEMZONE0_REGION4 0x51410 + +#define S_REGION_EN4 18 +#define V_REGION_EN4(x) ((x) << S_REGION_EN4) +#define F_REGION_EN4 V_REGION_EN4(1U) + +#define S_EDC_REGION4 17 +#define V_EDC_REGION4(x) ((x) << S_EDC_REGION4) +#define F_EDC_REGION4 V_EDC_REGION4(1U) + +#define S_CACHE_REGION4 16 +#define V_CACHE_REGION4(x) ((x) << S_CACHE_REGION4) +#define F_CACHE_REGION4 V_CACHE_REGION4(1U) + +#define S_END4 0 +#define M_END4 0xffffU +#define V_END4(x) ((x) << S_END4) +#define G_END4(x) (((x) >> S_END4) & M_END4) + +#define A_GCACHE_MEMZONE0_REGION5 0x51414 + +#define S_REGION_EN5 18 +#define V_REGION_EN5(x) ((x) << S_REGION_EN5) +#define F_REGION_EN5 V_REGION_EN5(1U) + +#define S_EDC_REGION5 17 +#define V_EDC_REGION5(x) ((x) << S_EDC_REGION5) +#define F_EDC_REGION5 V_EDC_REGION5(1U) + +#define S_CACHE_REGION5 16 +#define V_CACHE_REGION5(x) ((x) << S_CACHE_REGION5) +#define F_CACHE_REGION5 V_CACHE_REGION5(1U) + +#define S_END5 0 +#define M_END5 0xffffU +#define V_END5(x) ((x) << S_END5) +#define G_END5(x) (((x) >> S_END5) & M_END5) + +#define A_GCACHE_MEMZONE0_REGION6 0x51418 + +#define S_REGION_EN6 18 +#define V_REGION_EN6(x) ((x) << S_REGION_EN6) +#define F_REGION_EN6 V_REGION_EN6(1U) + +#define S_EDC_REGION6 17 +#define V_EDC_REGION6(x) ((x) << S_EDC_REGION6) +#define F_EDC_REGION6 V_EDC_REGION6(1U) + +#define S_CACHE_REGION6 16 +#define V_CACHE_REGION6(x) ((x) << S_CACHE_REGION6) +#define F_CACHE_REGION6 V_CACHE_REGION6(1U) + +#define S_END6 0 +#define M_END6 0xffffU +#define V_END6(x) ((x) << S_END6) +#define G_END6(x) (((x) >> S_END6) & M_END6) + +#define A_GCACHE_MEMZONE0_REGION7 0x5141c + +#define S_REGION_EN7 18 +#define V_REGION_EN7(x) ((x) << S_REGION_EN7) +#define F_REGION_EN7 V_REGION_EN7(1U) + +#define S_EDC_REGION7 17 +#define V_EDC_REGION7(x) ((x) << S_EDC_REGION7) +#define F_EDC_REGION7 V_EDC_REGION7(1U) + +#define S_CACHE_REGION7 16 +#define V_CACHE_REGION7(x) ((x) << S_CACHE_REGION7) +#define F_CACHE_REGION7 V_CACHE_REGION7(1U) + +#define S_END7 0 +#define M_END7 0xffffU +#define V_END7(x) ((x) << S_END7) +#define G_END7(x) (((x) >> S_END7) & M_END7) + +#define A_GCACHE_MEMZONE0_REGION8 0x51420 + +#define S_REGION_EN8 18 +#define V_REGION_EN8(x) ((x) << S_REGION_EN8) +#define F_REGION_EN8 V_REGION_EN8(1U) + +#define S_EDC_REGION8 17 +#define V_EDC_REGION8(x) ((x) << S_EDC_REGION8) +#define F_EDC_REGION8 V_EDC_REGION8(1U) + +#define S_CACHE_REGION8 16 +#define V_CACHE_REGION8(x) ((x) << S_CACHE_REGION8) +#define F_CACHE_REGION8 V_CACHE_REGION8(1U) + +#define S_END8 0 +#define M_END8 0xffffU +#define V_END8(x) ((x) << S_END8) +#define G_END8(x) (((x) >> S_END8) & M_END8) + +#define A_GCACHE_REG0_BASE_MSB 0x51424 +#define A_GCACHE_MEMZONE0_REGION1_MSB 0x51428 + +#define S_START1 0 +#define M_START1 0xffffU +#define V_START1(x) ((x) << S_START1) +#define G_START1(x) (((x) >> S_START1) & M_START1) + +#define A_GCACHE_MEMZONE0_REGION2_MSB 0x5142c + +#define S_START2 0 +#define M_START2 0xffffU +#define V_START2(x) ((x) << S_START2) +#define G_START2(x) (((x) >> S_START2) & M_START2) + +#define A_GCACHE_MEMZONE0_REGION3_MSB 0x51430 + +#define S_START3 0 +#define M_START3 0xffffU +#define V_START3(x) ((x) << S_START3) +#define G_START3(x) (((x) >> S_START3) & M_START3) + +#define A_GCACHE_MEMZONE0_REGION4_MSB 0x51434 + +#define S_START4 0 +#define M_START4 0xffffU +#define V_START4(x) ((x) << S_START4) +#define G_START4(x) (((x) >> S_START4) & M_START4) + +#define A_GCACHE_MEMZONE0_REGION5_MSB 0x51438 + +#define S_START5 0 +#define M_START5 0xffffU +#define V_START5(x) ((x) << S_START5) +#define G_START5(x) (((x) >> S_START5) & M_START5) + +#define A_GCACHE_MEMZONE0_REGION6_MSB 0x5143c + +#define S_START6 0 +#define M_START6 0xffffU +#define V_START6(x) ((x) << S_START6) +#define G_START6(x) (((x) >> S_START6) & M_START6) + +#define A_GCACHE_MEMZONE0_REGION7_MSB 0x51440 + +#define S_START7 0 +#define M_START7 0xffffU +#define V_START7(x) ((x) << S_START7) +#define G_START7(x) (((x) >> S_START7) & M_START7) + +#define A_GCACHE_MEMZONE0_REGION8_MSB 0x51444 + +#define S_START8 0 +#define M_START8 0xffffU +#define V_START8(x) ((x) << S_START8) +#define G_START8(x) (((x) >> S_START8) & M_START8) + +#define A_GCACHE_MODE_SEL1 0x51448 +#define A_GCACHE_MEMZONE1_REGION1 0x5144c +#define A_GCACHE_MEMZONE1_REGION2 0x51450 +#define A_GCACHE_MEMZONE1_REGION3 0x51454 +#define A_GCACHE_MEMZONE1_REGION4 0x51458 +#define A_GCACHE_MEMZONE1_REGION5 0x5145c +#define A_GCACHE_MEMZONE1_REGION6 0x51460 +#define A_GCACHE_MEMZONE1_REGION7 0x51464 +#define A_GCACHE_MEMZONE1_REGION8 0x51468 +#define A_GCACHE_MEMZONE1_REGION1_MSB 0x5146c +#define A_GCACHE_MEMZONE1_REGION2_MSB 0x51470 +#define A_GCACHE_MEMZONE1_REGION3_MSB 0x51474 +#define A_GCACHE_MEMZONE1_REGION4_MSB 0x51478 +#define A_GCACHE_MEMZONE1_REGION5_MSB 0x5147c +#define A_GCACHE_MEMZONE1_REGION6_MSB 0x51480 +#define A_GCACHE_MEMZONE1_REGION7_MSB 0x51484 +#define A_GCACHE_MEMZONE1_REGION8_MSB 0x51488 +#define A_GCACHE_HMA_MC1_EN 0x5148c + +#define S_MC1_EN 1 +#define V_MC1_EN(x) ((x) << S_MC1_EN) +#define F_MC1_EN V_MC1_EN(1U) + +#define S_HMA_EN 0 +#define V_HMA_EN(x) ((x) << S_HMA_EN) +#define F_HMA_EN V_HMA_EN(1U) + +#define A_GCACHE_P_BIST_CMD 0x51490 +#define A_GCACHE_P_BIST_CMD_ADDR 0x51494 +#define A_GCACHE_P_BIST_CMD_LEN 0x51498 +#define A_GCACHE_P_BIST_DATA_PATTERN 0x5149c +#define A_GCACHE_P_BIST_USER_WDATA0 0x514a0 +#define A_GCACHE_P_BIST_USER_WDATA1 0x514a4 +#define A_GCACHE_P_BIST_USER_WDATA2 0x514a8 +#define A_GCACHE_P_BIST_NUM_ERR 0x514ac +#define A_GCACHE_P_BIST_ERR_FIRST_ADDR 0x514b0 +#define A_GCACHE_P_BIST_STATUS_RDATA 0x514b4 +#define A_GCACHE_P_BIST_CRC_SEED 0x514fc +#define A_GCACHE_CACHE_SIZE 0x51500 + +#define S_HMA_2MB 1 +#define V_HMA_2MB(x) ((x) << S_HMA_2MB) +#define F_HMA_2MB V_HMA_2MB(1U) + +#define S_MC0_2MB 0 +#define V_MC0_2MB(x) ((x) << S_MC0_2MB) +#define F_MC0_2MB V_MC0_2MB(1U) + +#define A_GCACHE_HINT_MAPPING 0x51504 + +#define S_CLIENT_HINT_EN 16 +#define M_CLIENT_HINT_EN 0x7fffU +#define V_CLIENT_HINT_EN(x) ((x) << S_CLIENT_HINT_EN) +#define G_CLIENT_HINT_EN(x) (((x) >> S_CLIENT_HINT_EN) & M_CLIENT_HINT_EN) + +#define S_HINT_ADDR_SPLIT_EN 8 +#define V_HINT_ADDR_SPLIT_EN(x) ((x) << S_HINT_ADDR_SPLIT_EN) +#define F_HINT_ADDR_SPLIT_EN V_HINT_ADDR_SPLIT_EN(1U) + +#define S_TP_HINT_HMA_MC 2 +#define V_TP_HINT_HMA_MC(x) ((x) << S_TP_HINT_HMA_MC) +#define F_TP_HINT_HMA_MC V_TP_HINT_HMA_MC(1U) + +#define S_CIM_HINT_HMA_MC 1 +#define V_CIM_HINT_HMA_MC(x) ((x) << S_CIM_HINT_HMA_MC) +#define F_CIM_HINT_HMA_MC V_CIM_HINT_HMA_MC(1U) + +#define S_LE_HINT_HMA_MC 0 +#define V_LE_HINT_HMA_MC(x) ((x) << S_LE_HINT_HMA_MC) +#define F_LE_HINT_HMA_MC V_LE_HINT_HMA_MC(1U) + +#define A_GCACHE_PERF_EN 0x51508 + +#define S_PERF_CLEAR_GC1 3 +#define V_PERF_CLEAR_GC1(x) ((x) << S_PERF_CLEAR_GC1) +#define F_PERF_CLEAR_GC1 V_PERF_CLEAR_GC1(1U) + +#define S_PERF_CLEAR_GC0 2 +#define V_PERF_CLEAR_GC0(x) ((x) << S_PERF_CLEAR_GC0) +#define F_PERF_CLEAR_GC0 V_PERF_CLEAR_GC0(1U) + +#define S_PERF_EN_GC1 1 +#define V_PERF_EN_GC1(x) ((x) << S_PERF_EN_GC1) +#define F_PERF_EN_GC1 V_PERF_EN_GC1(1U) + +#define S_PERF_EN_GC0 0 +#define V_PERF_EN_GC0(x) ((x) << S_PERF_EN_GC0) +#define F_PERF_EN_GC0 V_PERF_EN_GC0(1U) + +#define A_GCACHE_PERF_GC0_RD_HIT 0x5150c +#define A_GCACHE_PERF_GC1_RD_HIT 0x51510 +#define A_GCACHE_PERF_GC0_WR_HIT 0x51514 +#define A_GCACHE_PERF_GC1_WR_HIT 0x51518 +#define A_GCACHE_PERF_GC0_RD_MISS 0x5151c +#define A_GCACHE_PERF_GC1_RD_MISS 0x51520 +#define A_GCACHE_PERF_GC0_WR_MISS 0x51524 +#define A_GCACHE_PERF_GC1_WR_MISS 0x51528 +#define A_GCACHE_PERF_GC0_RD_REQ 0x5152c +#define A_GCACHE_PERF_GC1_RD_REQ 0x51530 +#define A_GCACHE_PERF_GC0_WR_REQ 0x51534 +#define A_GCACHE_PERF_GC1_WR_REQ 0x51538 +#define A_GCACHE_PAR_CAUSE 0x5153c + +#define S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE 27 +#define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE) +#define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U) + +#define S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE 26 +#define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE) +#define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U) + +#define S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE 25 +#define V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE) +#define F_GC1_WQDATA_FIFO_PERR_PAR_CAUSE V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(1U) + +#define S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE 24 +#define V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE) +#define F_GC0_WQDATA_FIFO_PERR_PAR_CAUSE V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(1U) + +#define S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE 23 +#define V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE) +#define F_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(1U) + +#define S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE 22 +#define V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE) +#define F_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(1U) + +#define S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE 21 +#define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE) +#define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U) + +#define S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE 20 +#define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE) +#define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U) + +#define S_GC1_RSP_PERR_PAR_CAUSE 19 +#define V_GC1_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC1_RSP_PERR_PAR_CAUSE) +#define F_GC1_RSP_PERR_PAR_CAUSE V_GC1_RSP_PERR_PAR_CAUSE(1U) + +#define S_GC0_RSP_PERR_PAR_CAUSE 18 +#define V_GC0_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC0_RSP_PERR_PAR_CAUSE) +#define F_GC0_RSP_PERR_PAR_CAUSE V_GC0_RSP_PERR_PAR_CAUSE(1U) + +#define S_GC1_LRU_UERR_PAR_CAUSE 17 +#define V_GC1_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_UERR_PAR_CAUSE) +#define F_GC1_LRU_UERR_PAR_CAUSE V_GC1_LRU_UERR_PAR_CAUSE(1U) + +#define S_GC0_LRU_UERR_PAR_CAUSE 16 +#define V_GC0_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_UERR_PAR_CAUSE) +#define F_GC0_LRU_UERR_PAR_CAUSE V_GC0_LRU_UERR_PAR_CAUSE(1U) + +#define S_GC1_TAG_UERR_PAR_CAUSE 15 +#define V_GC1_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_UERR_PAR_CAUSE) +#define F_GC1_TAG_UERR_PAR_CAUSE V_GC1_TAG_UERR_PAR_CAUSE(1U) + +#define S_GC0_TAG_UERR_PAR_CAUSE 14 +#define V_GC0_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_UERR_PAR_CAUSE) +#define F_GC0_TAG_UERR_PAR_CAUSE V_GC0_TAG_UERR_PAR_CAUSE(1U) + +#define S_GC1_LRU_CERR_PAR_CAUSE 13 +#define V_GC1_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_CERR_PAR_CAUSE) +#define F_GC1_LRU_CERR_PAR_CAUSE V_GC1_LRU_CERR_PAR_CAUSE(1U) + +#define S_GC0_LRU_CERR_PAR_CAUSE 12 +#define V_GC0_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_CERR_PAR_CAUSE) +#define F_GC0_LRU_CERR_PAR_CAUSE V_GC0_LRU_CERR_PAR_CAUSE(1U) + +#define S_GC1_TAG_CERR_PAR_CAUSE 11 +#define V_GC1_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_CERR_PAR_CAUSE) +#define F_GC1_TAG_CERR_PAR_CAUSE V_GC1_TAG_CERR_PAR_CAUSE(1U) + +#define S_GC0_TAG_CERR_PAR_CAUSE 10 +#define V_GC0_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_CERR_PAR_CAUSE) +#define F_GC0_TAG_CERR_PAR_CAUSE V_GC0_TAG_CERR_PAR_CAUSE(1U) + +#define S_GC1_CE_PAR_CAUSE 9 +#define V_GC1_CE_PAR_CAUSE(x) ((x) << S_GC1_CE_PAR_CAUSE) +#define F_GC1_CE_PAR_CAUSE V_GC1_CE_PAR_CAUSE(1U) + +#define S_GC0_CE_PAR_CAUSE 8 +#define V_GC0_CE_PAR_CAUSE(x) ((x) << S_GC0_CE_PAR_CAUSE) +#define F_GC0_CE_PAR_CAUSE V_GC0_CE_PAR_CAUSE(1U) + +#define S_GC1_UE_PAR_CAUSE 7 +#define V_GC1_UE_PAR_CAUSE(x) ((x) << S_GC1_UE_PAR_CAUSE) +#define F_GC1_UE_PAR_CAUSE V_GC1_UE_PAR_CAUSE(1U) + +#define S_GC0_UE_PAR_CAUSE 6 +#define V_GC0_UE_PAR_CAUSE(x) ((x) << S_GC0_UE_PAR_CAUSE) +#define F_GC0_UE_PAR_CAUSE V_GC0_UE_PAR_CAUSE(1U) + +#define S_GC1_CMD_PAR_CAUSE 5 +#define V_GC1_CMD_PAR_CAUSE(x) ((x) << S_GC1_CMD_PAR_CAUSE) +#define F_GC1_CMD_PAR_CAUSE V_GC1_CMD_PAR_CAUSE(1U) + +#define S_GC1_DATA_PAR_CAUSE 4 +#define V_GC1_DATA_PAR_CAUSE(x) ((x) << S_GC1_DATA_PAR_CAUSE) +#define F_GC1_DATA_PAR_CAUSE V_GC1_DATA_PAR_CAUSE(1U) + +#define S_GC0_CMD_PAR_CAUSE 3 +#define V_GC0_CMD_PAR_CAUSE(x) ((x) << S_GC0_CMD_PAR_CAUSE) +#define F_GC0_CMD_PAR_CAUSE V_GC0_CMD_PAR_CAUSE(1U) + +#define S_GC0_DATA_PAR_CAUSE 2 +#define V_GC0_DATA_PAR_CAUSE(x) ((x) << S_GC0_DATA_PAR_CAUSE) +#define F_GC0_DATA_PAR_CAUSE V_GC0_DATA_PAR_CAUSE(1U) + +#define S_ILLADDRACCESS1_PAR_CAUSE 1 +#define V_ILLADDRACCESS1_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS1_PAR_CAUSE) +#define F_ILLADDRACCESS1_PAR_CAUSE V_ILLADDRACCESS1_PAR_CAUSE(1U) + +#define S_ILLADDRACCESS0_PAR_CAUSE 0 +#define V_ILLADDRACCESS0_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS0_PAR_CAUSE) +#define F_ILLADDRACCESS0_PAR_CAUSE V_ILLADDRACCESS0_PAR_CAUSE(1U) + +#define A_GCACHE_PAR_ENABLE 0x51540 + +#define S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE 27 +#define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE) +#define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U) + +#define S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE 26 +#define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE) +#define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U) + +#define S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE 25 +#define V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE) +#define F_GC1_WQDATA_FIFO_PERR_PAR_ENABLE V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(1U) + +#define S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE 24 +#define V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE) +#define F_GC0_WQDATA_FIFO_PERR_PAR_ENABLE V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(1U) + +#define S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE 23 +#define V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE) +#define F_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(1U) + +#define S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE 22 +#define V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE) +#define F_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(1U) + +#define S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE 21 +#define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE) +#define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U) + +#define S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE 20 +#define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE) +#define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U) + +#define S_GC1_RSP_PERR_PAR_ENABLE 19 +#define V_GC1_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC1_RSP_PERR_PAR_ENABLE) +#define F_GC1_RSP_PERR_PAR_ENABLE V_GC1_RSP_PERR_PAR_ENABLE(1U) + +#define S_GC0_RSP_PERR_PAR_ENABLE 18 +#define V_GC0_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC0_RSP_PERR_PAR_ENABLE) +#define F_GC0_RSP_PERR_PAR_ENABLE V_GC0_RSP_PERR_PAR_ENABLE(1U) + +#define S_GC1_LRU_UERR_PAR_ENABLE 17 +#define V_GC1_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_UERR_PAR_ENABLE) +#define F_GC1_LRU_UERR_PAR_ENABLE V_GC1_LRU_UERR_PAR_ENABLE(1U) + +#define S_GC0_LRU_UERR_PAR_ENABLE 16 +#define V_GC0_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_UERR_PAR_ENABLE) +#define F_GC0_LRU_UERR_PAR_ENABLE V_GC0_LRU_UERR_PAR_ENABLE(1U) + +#define S_GC1_TAG_UERR_PAR_ENABLE 15 +#define V_GC1_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_UERR_PAR_ENABLE) +#define F_GC1_TAG_UERR_PAR_ENABLE V_GC1_TAG_UERR_PAR_ENABLE(1U) + +#define S_GC0_TAG_UERR_PAR_ENABLE 14 +#define V_GC0_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_UERR_PAR_ENABLE) +#define F_GC0_TAG_UERR_PAR_ENABLE V_GC0_TAG_UERR_PAR_ENABLE(1U) + +#define S_GC1_LRU_CERR_PAR_ENABLE 13 +#define V_GC1_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_CERR_PAR_ENABLE) +#define F_GC1_LRU_CERR_PAR_ENABLE V_GC1_LRU_CERR_PAR_ENABLE(1U) + +#define S_GC0_LRU_CERR_PAR_ENABLE 12 +#define V_GC0_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_CERR_PAR_ENABLE) +#define F_GC0_LRU_CERR_PAR_ENABLE V_GC0_LRU_CERR_PAR_ENABLE(1U) + +#define S_GC1_TAG_CERR_PAR_ENABLE 11 +#define V_GC1_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_CERR_PAR_ENABLE) +#define F_GC1_TAG_CERR_PAR_ENABLE V_GC1_TAG_CERR_PAR_ENABLE(1U) + +#define S_GC0_TAG_CERR_PAR_ENABLE 10 +#define V_GC0_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_CERR_PAR_ENABLE) +#define F_GC0_TAG_CERR_PAR_ENABLE V_GC0_TAG_CERR_PAR_ENABLE(1U) + +#define S_GC1_CE_PAR_ENABLE 9 +#define V_GC1_CE_PAR_ENABLE(x) ((x) << S_GC1_CE_PAR_ENABLE) +#define F_GC1_CE_PAR_ENABLE V_GC1_CE_PAR_ENABLE(1U) + +#define S_GC0_CE_PAR_ENABLE 8 +#define V_GC0_CE_PAR_ENABLE(x) ((x) << S_GC0_CE_PAR_ENABLE) +#define F_GC0_CE_PAR_ENABLE V_GC0_CE_PAR_ENABLE(1U) + +#define S_GC1_UE_PAR_ENABLE 7 +#define V_GC1_UE_PAR_ENABLE(x) ((x) << S_GC1_UE_PAR_ENABLE) +#define F_GC1_UE_PAR_ENABLE V_GC1_UE_PAR_ENABLE(1U) + +#define S_GC0_UE_PAR_ENABLE 6 +#define V_GC0_UE_PAR_ENABLE(x) ((x) << S_GC0_UE_PAR_ENABLE) +#define F_GC0_UE_PAR_ENABLE V_GC0_UE_PAR_ENABLE(1U) + +#define S_GC1_CMD_PAR_ENABLE 5 +#define V_GC1_CMD_PAR_ENABLE(x) ((x) << S_GC1_CMD_PAR_ENABLE) +#define F_GC1_CMD_PAR_ENABLE V_GC1_CMD_PAR_ENABLE(1U) + +#define S_GC1_DATA_PAR_ENABLE 4 +#define V_GC1_DATA_PAR_ENABLE(x) ((x) << S_GC1_DATA_PAR_ENABLE) +#define F_GC1_DATA_PAR_ENABLE V_GC1_DATA_PAR_ENABLE(1U) + +#define S_GC0_CMD_PAR_ENABLE 3 +#define V_GC0_CMD_PAR_ENABLE(x) ((x) << S_GC0_CMD_PAR_ENABLE) +#define F_GC0_CMD_PAR_ENABLE V_GC0_CMD_PAR_ENABLE(1U) + +#define S_GC0_DATA_PAR_ENABLE 2 +#define V_GC0_DATA_PAR_ENABLE(x) ((x) << S_GC0_DATA_PAR_ENABLE) +#define F_GC0_DATA_PAR_ENABLE V_GC0_DATA_PAR_ENABLE(1U) + +#define S_ILLADDRACCESS1_PAR_ENABLE 1 +#define V_ILLADDRACCESS1_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS1_PAR_ENABLE) +#define F_ILLADDRACCESS1_PAR_ENABLE V_ILLADDRACCESS1_PAR_ENABLE(1U) + +#define S_ILLADDRACCESS0_PAR_ENABLE 0 +#define V_ILLADDRACCESS0_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS0_PAR_ENABLE) +#define F_ILLADDRACCESS0_PAR_ENABLE V_ILLADDRACCESS0_PAR_ENABLE(1U) + +#define A_GCACHE_INT_ENABLE 0x51544 + +#define S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE 27 +#define V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE) +#define F_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U) + +#define S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE 26 +#define V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE) +#define F_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U) + +#define S_GC1_WQDATA_FIFO_PERR_INT_ENABLE 25 +#define V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_ENABLE) +#define F_GC1_WQDATA_FIFO_PERR_INT_ENABLE V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(1U) + +#define S_GC0_WQDATA_FIFO_PERR_INT_ENABLE 24 +#define V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_ENABLE) +#define F_GC0_WQDATA_FIFO_PERR_INT_ENABLE V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(1U) + +#define S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE 23 +#define V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE) +#define F_GC1_RDTAG_QUEUE_PERR_INT_ENABLE V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(1U) + +#define S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE 22 +#define V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE) +#define F_GC0_RDTAG_QUEUE_PERR_INT_ENABLE V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(1U) + +#define S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE 21 +#define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE) +#define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U) + +#define S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE 20 +#define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE) +#define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U) + +#define S_GC1_RSP_PERR_INT_ENABLE 19 +#define V_GC1_RSP_PERR_INT_ENABLE(x) ((x) << S_GC1_RSP_PERR_INT_ENABLE) +#define F_GC1_RSP_PERR_INT_ENABLE V_GC1_RSP_PERR_INT_ENABLE(1U) + +#define S_GC0_RSP_PERR_INT_ENABLE 18 +#define V_GC0_RSP_PERR_INT_ENABLE(x) ((x) << S_GC0_RSP_PERR_INT_ENABLE) +#define F_GC0_RSP_PERR_INT_ENABLE V_GC0_RSP_PERR_INT_ENABLE(1U) + +#define S_GC1_LRU_UERR_INT_ENABLE 17 +#define V_GC1_LRU_UERR_INT_ENABLE(x) ((x) << S_GC1_LRU_UERR_INT_ENABLE) +#define F_GC1_LRU_UERR_INT_ENABLE V_GC1_LRU_UERR_INT_ENABLE(1U) + +#define S_GC0_LRU_UERR_INT_ENABLE 16 +#define V_GC0_LRU_UERR_INT_ENABLE(x) ((x) << S_GC0_LRU_UERR_INT_ENABLE) +#define F_GC0_LRU_UERR_INT_ENABLE V_GC0_LRU_UERR_INT_ENABLE(1U) + +#define S_GC1_TAG_UERR_INT_ENABLE 15 +#define V_GC1_TAG_UERR_INT_ENABLE(x) ((x) << S_GC1_TAG_UERR_INT_ENABLE) +#define F_GC1_TAG_UERR_INT_ENABLE V_GC1_TAG_UERR_INT_ENABLE(1U) + +#define S_GC0_TAG_UERR_INT_ENABLE 14 +#define V_GC0_TAG_UERR_INT_ENABLE(x) ((x) << S_GC0_TAG_UERR_INT_ENABLE) +#define F_GC0_TAG_UERR_INT_ENABLE V_GC0_TAG_UERR_INT_ENABLE(1U) + +#define S_GC1_LRU_CERR_INT_ENABLE 13 +#define V_GC1_LRU_CERR_INT_ENABLE(x) ((x) << S_GC1_LRU_CERR_INT_ENABLE) +#define F_GC1_LRU_CERR_INT_ENABLE V_GC1_LRU_CERR_INT_ENABLE(1U) + +#define S_GC0_LRU_CERR_INT_ENABLE 12 +#define V_GC0_LRU_CERR_INT_ENABLE(x) ((x) << S_GC0_LRU_CERR_INT_ENABLE) +#define F_GC0_LRU_CERR_INT_ENABLE V_GC0_LRU_CERR_INT_ENABLE(1U) + +#define S_GC1_TAG_CERR_INT_ENABLE 11 +#define V_GC1_TAG_CERR_INT_ENABLE(x) ((x) << S_GC1_TAG_CERR_INT_ENABLE) +#define F_GC1_TAG_CERR_INT_ENABLE V_GC1_TAG_CERR_INT_ENABLE(1U) + +#define S_GC0_TAG_CERR_INT_ENABLE 10 +#define V_GC0_TAG_CERR_INT_ENABLE(x) ((x) << S_GC0_TAG_CERR_INT_ENABLE) +#define F_GC0_TAG_CERR_INT_ENABLE V_GC0_TAG_CERR_INT_ENABLE(1U) + +#define S_GC1_CE_INT_ENABLE 9 +#define V_GC1_CE_INT_ENABLE(x) ((x) << S_GC1_CE_INT_ENABLE) +#define F_GC1_CE_INT_ENABLE V_GC1_CE_INT_ENABLE(1U) + +#define S_GC0_CE_INT_ENABLE 8 +#define V_GC0_CE_INT_ENABLE(x) ((x) << S_GC0_CE_INT_ENABLE) +#define F_GC0_CE_INT_ENABLE V_GC0_CE_INT_ENABLE(1U) + +#define S_GC1_UE_INT_ENABLE 7 +#define V_GC1_UE_INT_ENABLE(x) ((x) << S_GC1_UE_INT_ENABLE) +#define F_GC1_UE_INT_ENABLE V_GC1_UE_INT_ENABLE(1U) + +#define S_GC0_UE_INT_ENABLE 6 +#define V_GC0_UE_INT_ENABLE(x) ((x) << S_GC0_UE_INT_ENABLE) +#define F_GC0_UE_INT_ENABLE V_GC0_UE_INT_ENABLE(1U) + +#define S_GC1_CMD_PAR_INT_ENABLE 5 +#define V_GC1_CMD_PAR_INT_ENABLE(x) ((x) << S_GC1_CMD_PAR_INT_ENABLE) +#define F_GC1_CMD_PAR_INT_ENABLE V_GC1_CMD_PAR_INT_ENABLE(1U) + +#define S_GC1_DATA_PAR_INT_ENABLE 4 +#define V_GC1_DATA_PAR_INT_ENABLE(x) ((x) << S_GC1_DATA_PAR_INT_ENABLE) +#define F_GC1_DATA_PAR_INT_ENABLE V_GC1_DATA_PAR_INT_ENABLE(1U) + +#define S_GC0_CMD_PAR_INT_ENABLE 3 +#define V_GC0_CMD_PAR_INT_ENABLE(x) ((x) << S_GC0_CMD_PAR_INT_ENABLE) +#define F_GC0_CMD_PAR_INT_ENABLE V_GC0_CMD_PAR_INT_ENABLE(1U) + +#define S_GC0_DATA_PAR_INT_ENABLE 2 +#define V_GC0_DATA_PAR_INT_ENABLE(x) ((x) << S_GC0_DATA_PAR_INT_ENABLE) +#define F_GC0_DATA_PAR_INT_ENABLE V_GC0_DATA_PAR_INT_ENABLE(1U) + +#define S_ILLADDRACCESS1_INT_ENABLE 1 +#define V_ILLADDRACCESS1_INT_ENABLE(x) ((x) << S_ILLADDRACCESS1_INT_ENABLE) +#define F_ILLADDRACCESS1_INT_ENABLE V_ILLADDRACCESS1_INT_ENABLE(1U) + +#define S_ILLADDRACCESS0_INT_ENABLE 0 +#define V_ILLADDRACCESS0_INT_ENABLE(x) ((x) << S_ILLADDRACCESS0_INT_ENABLE) +#define F_ILLADDRACCESS0_INT_ENABLE V_ILLADDRACCESS0_INT_ENABLE(1U) + +#define A_GCACHE_INT_CAUSE 0x51548 + +#define S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE 27 +#define V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE) +#define F_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U) + +#define S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE 26 +#define V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE) +#define F_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U) + +#define S_GC1_WQDATA_FIFO_PERR_INT_CAUSE 25 +#define V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_CAUSE) +#define F_GC1_WQDATA_FIFO_PERR_INT_CAUSE V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(1U) + +#define S_GC0_WQDATA_FIFO_PERR_INT_CAUSE 24 +#define V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_CAUSE) +#define F_GC0_WQDATA_FIFO_PERR_INT_CAUSE V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(1U) + +#define S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE 23 +#define V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE) +#define F_GC1_RDTAG_QUEUE_PERR_INT_CAUSE V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(1U) + +#define S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE 22 +#define V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE) +#define F_GC0_RDTAG_QUEUE_PERR_INT_CAUSE V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(1U) + +#define S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE 21 +#define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE) +#define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U) + +#define S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE 20 +#define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE) +#define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U) + +#define S_GC1_RSP_PERR_INT_CAUSE 19 +#define V_GC1_RSP_PERR_INT_CAUSE(x) ((x) << S_GC1_RSP_PERR_INT_CAUSE) +#define F_GC1_RSP_PERR_INT_CAUSE V_GC1_RSP_PERR_INT_CAUSE(1U) + +#define S_GC0_RSP_PERR_INT_CAUSE 18 +#define V_GC0_RSP_PERR_INT_CAUSE(x) ((x) << S_GC0_RSP_PERR_INT_CAUSE) +#define F_GC0_RSP_PERR_INT_CAUSE V_GC0_RSP_PERR_INT_CAUSE(1U) + +#define S_GC1_LRU_UERR_INT_CAUSE 17 +#define V_GC1_LRU_UERR_INT_CAUSE(x) ((x) << S_GC1_LRU_UERR_INT_CAUSE) +#define F_GC1_LRU_UERR_INT_CAUSE V_GC1_LRU_UERR_INT_CAUSE(1U) + +#define S_GC0_LRU_UERR_INT_CAUSE 16 +#define V_GC0_LRU_UERR_INT_CAUSE(x) ((x) << S_GC0_LRU_UERR_INT_CAUSE) +#define F_GC0_LRU_UERR_INT_CAUSE V_GC0_LRU_UERR_INT_CAUSE(1U) + +#define S_GC1_TAG_UERR_INT_CAUSE 15 +#define V_GC1_TAG_UERR_INT_CAUSE(x) ((x) << S_GC1_TAG_UERR_INT_CAUSE) +#define F_GC1_TAG_UERR_INT_CAUSE V_GC1_TAG_UERR_INT_CAUSE(1U) + +#define S_GC0_TAG_UERR_INT_CAUSE 14 +#define V_GC0_TAG_UERR_INT_CAUSE(x) ((x) << S_GC0_TAG_UERR_INT_CAUSE) +#define F_GC0_TAG_UERR_INT_CAUSE V_GC0_TAG_UERR_INT_CAUSE(1U) + +#define S_GC1_LRU_CERR_INT_CAUSE 13 +#define V_GC1_LRU_CERR_INT_CAUSE(x) ((x) << S_GC1_LRU_CERR_INT_CAUSE) +#define F_GC1_LRU_CERR_INT_CAUSE V_GC1_LRU_CERR_INT_CAUSE(1U) + +#define S_GC0_LRU_CERR_INT_CAUSE 12 +#define V_GC0_LRU_CERR_INT_CAUSE(x) ((x) << S_GC0_LRU_CERR_INT_CAUSE) +#define F_GC0_LRU_CERR_INT_CAUSE V_GC0_LRU_CERR_INT_CAUSE(1U) + +#define S_GC1_TAG_CERR_INT_CAUSE 11 +#define V_GC1_TAG_CERR_INT_CAUSE(x) ((x) << S_GC1_TAG_CERR_INT_CAUSE) +#define F_GC1_TAG_CERR_INT_CAUSE V_GC1_TAG_CERR_INT_CAUSE(1U) + +#define S_GC0_TAG_CERR_INT_CAUSE 10 +#define V_GC0_TAG_CERR_INT_CAUSE(x) ((x) << S_GC0_TAG_CERR_INT_CAUSE) +#define F_GC0_TAG_CERR_INT_CAUSE V_GC0_TAG_CERR_INT_CAUSE(1U) + +#define S_GC1_CE_INT_CAUSE 9 +#define V_GC1_CE_INT_CAUSE(x) ((x) << S_GC1_CE_INT_CAUSE) +#define F_GC1_CE_INT_CAUSE V_GC1_CE_INT_CAUSE(1U) + +#define S_GC0_CE_INT_CAUSE 8 +#define V_GC0_CE_INT_CAUSE(x) ((x) << S_GC0_CE_INT_CAUSE) +#define F_GC0_CE_INT_CAUSE V_GC0_CE_INT_CAUSE(1U) + +#define S_GC1_UE_INT_CAUSE 7 +#define V_GC1_UE_INT_CAUSE(x) ((x) << S_GC1_UE_INT_CAUSE) +#define F_GC1_UE_INT_CAUSE V_GC1_UE_INT_CAUSE(1U) + +#define S_GC0_UE_INT_CAUSE 6 +#define V_GC0_UE_INT_CAUSE(x) ((x) << S_GC0_UE_INT_CAUSE) +#define F_GC0_UE_INT_CAUSE V_GC0_UE_INT_CAUSE(1U) + +#define S_GC1_CMD_PAR_INT_CAUSE 5 +#define V_GC1_CMD_PAR_INT_CAUSE(x) ((x) << S_GC1_CMD_PAR_INT_CAUSE) +#define F_GC1_CMD_PAR_INT_CAUSE V_GC1_CMD_PAR_INT_CAUSE(1U) + +#define S_GC1_DATA_PAR_INT_CAUSE 4 +#define V_GC1_DATA_PAR_INT_CAUSE(x) ((x) << S_GC1_DATA_PAR_INT_CAUSE) +#define F_GC1_DATA_PAR_INT_CAUSE V_GC1_DATA_PAR_INT_CAUSE(1U) + +#define S_GC0_CMD_PAR_INT_CAUSE 3 +#define V_GC0_CMD_PAR_INT_CAUSE(x) ((x) << S_GC0_CMD_PAR_INT_CAUSE) +#define F_GC0_CMD_PAR_INT_CAUSE V_GC0_CMD_PAR_INT_CAUSE(1U) + +#define S_GC0_DATA_PAR_INT_CAUSE 2 +#define V_GC0_DATA_PAR_INT_CAUSE(x) ((x) << S_GC0_DATA_PAR_INT_CAUSE) +#define F_GC0_DATA_PAR_INT_CAUSE V_GC0_DATA_PAR_INT_CAUSE(1U) + +#define S_ILLADDRACCESS1_INT_CAUSE 1 +#define V_ILLADDRACCESS1_INT_CAUSE(x) ((x) << S_ILLADDRACCESS1_INT_CAUSE) +#define F_ILLADDRACCESS1_INT_CAUSE V_ILLADDRACCESS1_INT_CAUSE(1U) + +#define S_ILLADDRACCESS0_INT_CAUSE 0 +#define V_ILLADDRACCESS0_INT_CAUSE(x) ((x) << S_ILLADDRACCESS0_INT_CAUSE) +#define F_ILLADDRACCESS0_INT_CAUSE V_ILLADDRACCESS0_INT_CAUSE(1U) + +#define A_GCACHE_DBG_SEL_CTRL 0x51550 + +#define S_DBG_SEL_CTRLSEL_OVR_EN 31 +#define V_DBG_SEL_CTRLSEL_OVR_EN(x) ((x) << S_DBG_SEL_CTRLSEL_OVR_EN) +#define F_DBG_SEL_CTRLSEL_OVR_EN V_DBG_SEL_CTRLSEL_OVR_EN(1U) + +#define S_T7_DEBUG_HI 16 +#define V_T7_DEBUG_HI(x) ((x) << S_T7_DEBUG_HI) +#define F_T7_DEBUG_HI V_T7_DEBUG_HI(1U) + +#define S_DBG_SEL_CTRLSELH 8 +#define M_DBG_SEL_CTRLSELH 0xffU +#define V_DBG_SEL_CTRLSELH(x) ((x) << S_DBG_SEL_CTRLSELH) +#define G_DBG_SEL_CTRLSELH(x) (((x) >> S_DBG_SEL_CTRLSELH) & M_DBG_SEL_CTRLSELH) + +#define S_DBG_SEL_CTRLSELL 0 +#define M_DBG_SEL_CTRLSELL 0xffU +#define V_DBG_SEL_CTRLSELL(x) ((x) << S_DBG_SEL_CTRLSELL) +#define G_DBG_SEL_CTRLSELL(x) (((x) >> S_DBG_SEL_CTRLSELL) & M_DBG_SEL_CTRLSELL) + +#define A_GCACHE_LOCAL_DEBUG_RPT 0x51554 +#define A_GCACHE_DBG_ILL_ACC 0x5155c +#define A_GCACHE_DBG_ILL_ADDR0 0x51560 +#define A_GCACHE_DBG_ILL_ADDR1 0x51564 +#define A_GCACHE_GC0_DBG_ADDR_0_32 0x51568 +#define A_GCACHE_GC0_DBG_ADDR_32_32 0x5156c +#define A_GCACHE_GC0_DBG_ADDR_64_32 0x51570 +#define A_GCACHE_GC0_DBG_ADDR_96_32 0x51574 +#define A_GCACHE_GC0_DBG_ADDR_0_64 0x51578 +#define A_GCACHE_GC0_DBG_ADDR_64_64 0x5157c +#define A_GCACHE_GC0_DBG_ADDR_0_96 0x51580 +#define A_GCACHE_GC0_DBG_ADDR_32_96 0x51584 +#define A_GCACHE_GC1_DBG_ADDR_0_32 0x5158c +#define A_GCACHE_GC1_DBG_ADDR_32_32 0x51590 +#define A_GCACHE_GC1_DBG_ADDR_64_32 0x51594 +#define A_GCACHE_GC1_DBG_ADDR_96_32 0x51598 +#define A_GCACHE_GC1_DBG_ADDR_0_64 0x5159c +#define A_GCACHE_GC1_DBG_ADDR_64_64 0x515a0 +#define A_GCACHE_GC1_DBG_ADDR_0_96 0x515a4 +#define A_GCACHE_GC1_DBG_ADDR_32_96 0x515a8 +#define A_GCACHE_GC0_DBG_ADDR_32_64 0x515ac +#define A_GCACHE_GC1_DBG_ADDR_32_64 0x515b0 +#define A_GCACHE_PERF_GC0_EVICT 0x515b4 +#define A_GCACHE_PERF_GC1_EVICT 0x515b8 +#define A_GCACHE_PERF_GC0_CE_COUNT 0x515bc +#define A_GCACHE_PERF_GC1_CE_COUNT 0x515c0 +#define A_GCACHE_PERF_GC0_UE_COUNT 0x515c4 +#define A_GCACHE_PERF_GC1_UE_COUNT 0x515c8 +#define A_GCACHE_DBG_CTL 0x515f0 +#define A_GCACHE_DBG_DATA 0x515f4 |