aboutsummaryrefslogtreecommitdiff
path: root/sys/dev/rl/if_rlreg.h
diff options
context:
space:
mode:
Diffstat (limited to 'sys/dev/rl/if_rlreg.h')
-rw-r--r--sys/dev/rl/if_rlreg.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/sys/dev/rl/if_rlreg.h b/sys/dev/rl/if_rlreg.h
index 6339b12472b6..10e25fcb5373 100644
--- a/sys/dev/rl/if_rlreg.h
+++ b/sys/dev/rl/if_rlreg.h
@@ -31,7 +31,7 @@
*/
/*
- * RealTek 8129/8139 register offsets
+ * Realtek 8129/8139 register offsets
*/
#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
@@ -544,7 +544,7 @@
#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
/*
- * The RealTek doesn't use a fragment-based descriptor mechanism.
+ * The Realtek doesn't use a fragment-based descriptor mechanism.
* Instead, there are only four register sets, each of which represents
* one 'descriptor.' Basically, each TX descriptor is just a contiguous
* packet buffer (32-bit aligned!) and we place the buffer addresses in
@@ -801,7 +801,7 @@ struct rl_stats {
#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
/*
- * The number of bits reserved for MSS in RealTek controllers is
+ * The number of bits reserved for MSS in Realtek controllers is
* 11bits. This limits the maximum interface MTU size in TSO case
* as upper stack should not generate TCP segments with MSS greater
* than the limit.
@@ -985,12 +985,12 @@ struct rl_softc {
/*
* General constants that are fun to know.
*
- * RealTek PCI vendor ID
+ * Realtek PCI vendor ID
*/
#define RT_VENDORID 0x10EC
/*
- * RealTek chip device IDs.
+ * Realtek chip device IDs.
*/
#define RT_DEVICEID_2600 0x2600
#define RT_DEVICEID_8139D 0x8039