diff options
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/dec/clockvar.h | 62 | ||||
| -rw-r--r-- | sys/dev/dec/mc146818reg.h | 194 | ||||
| -rw-r--r-- | sys/dev/dec/mcclock.c | 141 | ||||
| -rw-r--r-- | sys/dev/dec/mcclockvar.h | 41 | ||||
| -rw-r--r-- | sys/dev/mc146818/mc146818reg.h | 194 |
5 files changed, 632 insertions, 0 deletions
diff --git a/sys/dev/dec/clockvar.h b/sys/dev/dec/clockvar.h new file mode 100644 index 000000000000..920d1627a830 --- /dev/null +++ b/sys/dev/dec/clockvar.h @@ -0,0 +1,62 @@ +/* $NetBSD: clockvar.h,v 1.4 1997/06/22 08:02:18 jonathan Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Definitions for cpu-independent clock handling for the alpha and pmax. + */ + +/* + * clocktime structure: + * + * structure passed to TOY clocks when setting them. broken out this + * way, so that the time_t -> field conversion can be shared. + */ +struct clocktime { + int year; /* year - 1900 */ + int mon; /* month (1 - 12) */ + int day; /* day (1 - 31) */ + int hour; /* hour (0 - 23) */ + int min; /* minute (0 - 59) */ + int sec; /* second (0 - 59) */ + int dow; /* day of week (0 - 6; 0 = Sunday) */ +}; + +/* + * clockfns structure: + * + * function switch used by chip-independent clock code, to access + * chip-dependent routines. + */ +struct clockfns { + void (*cf_init) __P((struct device *)); + void (*cf_get) __P((struct device *, time_t, struct clocktime *)); + void (*cf_set) __P((struct device *, struct clocktime *)); +}; + +void clockattach __P((device_t, const struct clockfns *)); diff --git a/sys/dev/dec/mc146818reg.h b/sys/dev/dec/mc146818reg.h new file mode 100644 index 000000000000..95c3ccfa5a29 --- /dev/null +++ b/sys/dev/dec/mc146818reg.h @@ -0,0 +1,194 @@ +/* $NetBSD: mc146818reg.h,v 1.2 1997/03/12 06:53:42 cgd Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Definitions for the Motorola MC146818A Real Time Clock. + * They also apply for the (compatible) Dallas Semicontuctor DS1287A RTC. + * + * Though there are undoubtedly other (better) sources, this material was + * culled from the DEC "KN121 System Module Programmer's Reference + * Information." + * + * The MC146818A has 16 registers. The first 10 contain time-of-year + * and alarm data. The rest contain various control and status bits. + * + * To read or write the registers, one writes the register number to + * the RTC's control port, then either reads from or writes the new + * data to the RTC's data port. Since the locations of these ports + * and the method used to access them can be machine-dependent, the + * low-level details of reading and writing the RTC's registers are + * handled by machine-specific functions. + * + * The time-of-year and alarm data can be expressed in either binary + * or BCD, and they are selected by a bit in register B. + * + * The "hour" time-of-year and alarm fields can either be expressed in + * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the + * hour fields can have the values: 1-12 and 81-92 (the latter being + * PM). If the 24-hour format is chosen, they can have the values + * 0-24. The hour format is selectable by a bit in register B. + * (XXX IS AM/PM MODE DESCRIPTION CORRECT?) + * + * It is assumed the if systems are going to use BCD (rather than + * binary) mode, or AM/PM hour format, they'll do the appropriate + * conversions in machine-dependent code. Also, if the clock is + * switched between BCD and binary mode, or between AM/PM mode and + * 24-hour mode, the time-of-day and alarm registers are NOT + * automatically reset; they must be reprogrammed with correct values. + */ + +/* + * The registers, and the bits within each register. + */ + +#define MC_SEC 0x0 /* Time of year: seconds (0-59) */ +#define MC_ASEC 0x1 /* Alarm: seconds */ +#define MC_MIN 0x2 /* Time of year: minutes (0-59) */ +#define MC_AMIN 0x3 /* Alarm: minutes */ +#define MC_HOUR 0x4 /* Time of year: hour (see above) */ +#define MC_AHOUR 0x5 /* Alarm: hour */ +#define MC_DOW 0x6 /* Time of year: day of week (1-7) */ +#define MC_DOM 0x7 /* Time of year: day of month (1-31) */ +#define MC_MONTH 0x8 /* Time of year: month (1-12) */ +#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */ + +#define MC_REGA 0xa /* Control register A */ + +#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ +#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ +#define MC_REGA_UIP 0x80 /* Update in progress; read only. */ + +#define MC_REGB 0xb /* Control register B */ + +#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */ +#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ +#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ +#define MC_REGB_SQWE 0x08 /* Square Wave Enable */ +#define MC_REGB_UIE 0x10 /* Update End interrupt enable */ +#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */ +#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */ +#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */ + +#define MC_REGC 0xc /* Control register C */ + +/* MC_REGC_UNUSED 0x0f UNUSED */ +#define MC_REGC_UF 0x10 /* Update End interrupt flag */ +#define MC_REGC_AF 0x20 /* Alarm interrupt flag */ +#define MC_REGC_PF 0x40 /* Periodic interrupt flag */ +#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */ + +#define MC_REGD 0xd /* Control register D */ + +/* MC_REGD_UNUSED 0x7f UNUSED */ +#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */ + + +#define MC_NREGS 0xe /* 14 registers; CMOS follows */ +#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ + +#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ +#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ + +/* + * Periodic Interrupt Rate Select constants (Control register A) + */ +#define MC_RATE_NONE 0x0 /* No periodic interrupt */ +#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ +#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ +#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ +#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ +#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ +#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ +#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ +#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ +#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ +#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ +#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ +#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ +#define MC_RATE_8_Hz 0xd /* 125 ms period */ +#define MC_RATE_4_Hz 0xe /* 250 ms period */ +#define MC_RATE_2_Hz 0xf /* 500 ms period */ + +/* + * Time base (divisor select) constants (Control register A) + */ +#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ +#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ +#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ +#define MC_BASE_NONE 0x60 /* actually, both of these reset */ +#define MC_BASE_RESET 0x70 + + +/* + * RTC register/NVRAM read and write functions -- machine-dependent. + * Appropriately manipulate RTC registers to get/put data values. + */ +u_int mc146818_read __P((void *sc, u_int reg)); +void mc146818_write __P((void *sc, u_int reg, u_int datum)); + +/* + * A collection of TOD/Alarm registers. + */ +typedef u_int mc_todregs[MC_NTODREGS]; + +/* + * Get all of the TOD/Alarm registers + * Must be called at splhigh(), and with the RTC properly set up. + */ +#define MC146818_GETTOD(sc, regs) \ + do { \ + int i; \ + \ + /* update in progress; spin loop */ \ + while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \ + ; \ + \ + /* read all of the tod/alarm regs */ \ + for (i = 0; i < MC_NTODREGS; i++) \ + (*regs)[i] = mc146818_read(sc, i); \ + } while (0); + +/* + * Set all of the TOD/Alarm registers + * Must be called at splhigh(), and with the RTC properly set up. + */ +#define MC146818_PUTTOD(sc, regs) \ + do { \ + int i; \ + \ + /* stop updates while setting */ \ + mc146818_write(sc, MC_REGB, \ + mc146818_read(sc, MC_REGB) | MC_REGB_SET); \ + \ + /* write all of the tod/alarm regs */ \ + for (i = 0; i < MC_NTODREGS; i++) \ + mc146818_write(sc, i, (*regs)[i]); \ + \ + /* reenable updates */ \ + mc146818_write(sc, MC_REGB, \ + mc146818_read(sc, MC_REGB) & ~MC_REGB_SET); \ + } while (0); diff --git a/sys/dev/dec/mcclock.c b/sys/dev/dec/mcclock.c new file mode 100644 index 000000000000..76e3805ef785 --- /dev/null +++ b/sys/dev/dec/mcclock.c @@ -0,0 +1,141 @@ +/* $Id$ */ +/* $NetBSD: mcclock.c,v 1.11 1998/04/19 07:50:25 jonathan Exp $ */ + +/* + * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <dev/dec/clockvar.h> +#include <dev/dec/mcclockvar.h> +#include <dev/dec/mc146818reg.h> + +/* + * XXX rate is machine-dependent. + */ +#ifdef __alpha__ +#define MC_DEFAULTRATE MC_RATE_1024_Hz +#endif +#ifdef __pmax__ +#define MC_DEFAULTRATE MC_RATE_256_Hz +#endif + + +void mcclock_init __P((struct device *)); +void mcclock_get __P((struct device *, time_t, struct clocktime *)); +void mcclock_set __P((struct device *, struct clocktime *)); + +const struct clockfns mcclock_clockfns = { + mcclock_init, mcclock_get, mcclock_set, +}; + +#define mc146818_write(dev, reg, datum) \ + (*(dev)->sc_busfns->mc_bf_write)(dev, reg, datum) +#define mc146818_read(dev, reg) \ + (*(dev)->sc_busfns->mc_bf_read)(dev, reg) + +void +mcclock_attach(sc, busfns) + struct mcclock_softc *sc; + const struct mcclock_busfns *busfns; +{ + sc->sc_busfns = busfns; + + /* Turn interrupts off, just in case. */ + mc146818_write(sc, MC_REGB, MC_REGB_BINARY | MC_REGB_24HR); + + clockattach(sc->sc_dev, &mcclock_clockfns); +} + +void +mcclock_init(dev) + device_t dev; +{ + struct mcclock_softc *sc = device_get_softc(dev); + + mc146818_write(sc, MC_REGA, MC_BASE_32_KHz | MC_DEFAULTRATE); + mc146818_write(sc, MC_REGB, + MC_REGB_PIE | MC_REGB_SQWE | MC_REGB_BINARY | MC_REGB_24HR); +} + +/* + * Get the time of day, based on the clock's value and/or the base value. + */ +void +mcclock_get(dev, base, ct) + struct device *dev; + time_t base; + struct clocktime *ct; +{ + struct mcclock_softc *sc = device_get_softc(dev); + mc_todregs regs; + int s; + + s = splclock(); + MC146818_GETTOD(sc, ®s) + splx(s); + + ct->sec = regs[MC_SEC]; + ct->min = regs[MC_MIN]; + ct->hour = regs[MC_HOUR]; + ct->dow = regs[MC_DOW]; + ct->day = regs[MC_DOM]; + ct->mon = regs[MC_MONTH]; + ct->year = regs[MC_YEAR]; +} + +/* + * Reset the TODR based on the time value. + */ +void +mcclock_set(dev, ct) + struct device *dev; + struct clocktime *ct; +{ + struct mcclock_softc *sc = device_get_softc(dev); + mc_todregs regs; + int s; + + s = splclock(); + MC146818_GETTOD(sc, ®s); + splx(s); + + regs[MC_SEC] = ct->sec; + regs[MC_MIN] = ct->min; + regs[MC_HOUR] = ct->hour; + regs[MC_DOW] = ct->dow; + regs[MC_DOM] = ct->day; + regs[MC_MONTH] = ct->mon; + regs[MC_YEAR] = ct->year; + + s = splclock(); + MC146818_PUTTOD(sc, ®s); + splx(s); +} diff --git a/sys/dev/dec/mcclockvar.h b/sys/dev/dec/mcclockvar.h new file mode 100644 index 000000000000..d2c0ac82e9bf --- /dev/null +++ b/sys/dev/dec/mcclockvar.h @@ -0,0 +1,41 @@ +/* $NetBSD: mcclockvar.h,v 1.4 1997/06/22 08:02:19 jonathan Exp $ */ + +/* + * Copyright (c) 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +struct mcclock_softc { + device_t sc_dev; + const struct mcclock_busfns *sc_busfns; +}; + +struct mcclock_busfns { + void (*mc_bf_write) __P((struct mcclock_softc *, u_int, u_int)); + u_int (*mc_bf_read) __P((struct mcclock_softc *, u_int)); +}; + +void mcclock_attach __P((struct mcclock_softc *, + const struct mcclock_busfns *)); diff --git a/sys/dev/mc146818/mc146818reg.h b/sys/dev/mc146818/mc146818reg.h new file mode 100644 index 000000000000..95c3ccfa5a29 --- /dev/null +++ b/sys/dev/mc146818/mc146818reg.h @@ -0,0 +1,194 @@ +/* $NetBSD: mc146818reg.h,v 1.2 1997/03/12 06:53:42 cgd Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Definitions for the Motorola MC146818A Real Time Clock. + * They also apply for the (compatible) Dallas Semicontuctor DS1287A RTC. + * + * Though there are undoubtedly other (better) sources, this material was + * culled from the DEC "KN121 System Module Programmer's Reference + * Information." + * + * The MC146818A has 16 registers. The first 10 contain time-of-year + * and alarm data. The rest contain various control and status bits. + * + * To read or write the registers, one writes the register number to + * the RTC's control port, then either reads from or writes the new + * data to the RTC's data port. Since the locations of these ports + * and the method used to access them can be machine-dependent, the + * low-level details of reading and writing the RTC's registers are + * handled by machine-specific functions. + * + * The time-of-year and alarm data can be expressed in either binary + * or BCD, and they are selected by a bit in register B. + * + * The "hour" time-of-year and alarm fields can either be expressed in + * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the + * hour fields can have the values: 1-12 and 81-92 (the latter being + * PM). If the 24-hour format is chosen, they can have the values + * 0-24. The hour format is selectable by a bit in register B. + * (XXX IS AM/PM MODE DESCRIPTION CORRECT?) + * + * It is assumed the if systems are going to use BCD (rather than + * binary) mode, or AM/PM hour format, they'll do the appropriate + * conversions in machine-dependent code. Also, if the clock is + * switched between BCD and binary mode, or between AM/PM mode and + * 24-hour mode, the time-of-day and alarm registers are NOT + * automatically reset; they must be reprogrammed with correct values. + */ + +/* + * The registers, and the bits within each register. + */ + +#define MC_SEC 0x0 /* Time of year: seconds (0-59) */ +#define MC_ASEC 0x1 /* Alarm: seconds */ +#define MC_MIN 0x2 /* Time of year: minutes (0-59) */ +#define MC_AMIN 0x3 /* Alarm: minutes */ +#define MC_HOUR 0x4 /* Time of year: hour (see above) */ +#define MC_AHOUR 0x5 /* Alarm: hour */ +#define MC_DOW 0x6 /* Time of year: day of week (1-7) */ +#define MC_DOM 0x7 /* Time of year: day of month (1-31) */ +#define MC_MONTH 0x8 /* Time of year: month (1-12) */ +#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */ + +#define MC_REGA 0xa /* Control register A */ + +#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ +#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ +#define MC_REGA_UIP 0x80 /* Update in progress; read only. */ + +#define MC_REGB 0xb /* Control register B */ + +#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */ +#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ +#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ +#define MC_REGB_SQWE 0x08 /* Square Wave Enable */ +#define MC_REGB_UIE 0x10 /* Update End interrupt enable */ +#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */ +#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */ +#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */ + +#define MC_REGC 0xc /* Control register C */ + +/* MC_REGC_UNUSED 0x0f UNUSED */ +#define MC_REGC_UF 0x10 /* Update End interrupt flag */ +#define MC_REGC_AF 0x20 /* Alarm interrupt flag */ +#define MC_REGC_PF 0x40 /* Periodic interrupt flag */ +#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */ + +#define MC_REGD 0xd /* Control register D */ + +/* MC_REGD_UNUSED 0x7f UNUSED */ +#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */ + + +#define MC_NREGS 0xe /* 14 registers; CMOS follows */ +#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ + +#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ +#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ + +/* + * Periodic Interrupt Rate Select constants (Control register A) + */ +#define MC_RATE_NONE 0x0 /* No periodic interrupt */ +#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ +#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ +#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ +#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ +#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ +#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ +#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ +#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ +#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ +#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ +#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ +#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ +#define MC_RATE_8_Hz 0xd /* 125 ms period */ +#define MC_RATE_4_Hz 0xe /* 250 ms period */ +#define MC_RATE_2_Hz 0xf /* 500 ms period */ + +/* + * Time base (divisor select) constants (Control register A) + */ +#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ +#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ +#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ +#define MC_BASE_NONE 0x60 /* actually, both of these reset */ +#define MC_BASE_RESET 0x70 + + +/* + * RTC register/NVRAM read and write functions -- machine-dependent. + * Appropriately manipulate RTC registers to get/put data values. + */ +u_int mc146818_read __P((void *sc, u_int reg)); +void mc146818_write __P((void *sc, u_int reg, u_int datum)); + +/* + * A collection of TOD/Alarm registers. + */ +typedef u_int mc_todregs[MC_NTODREGS]; + +/* + * Get all of the TOD/Alarm registers + * Must be called at splhigh(), and with the RTC properly set up. + */ +#define MC146818_GETTOD(sc, regs) \ + do { \ + int i; \ + \ + /* update in progress; spin loop */ \ + while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \ + ; \ + \ + /* read all of the tod/alarm regs */ \ + for (i = 0; i < MC_NTODREGS; i++) \ + (*regs)[i] = mc146818_read(sc, i); \ + } while (0); + +/* + * Set all of the TOD/Alarm registers + * Must be called at splhigh(), and with the RTC properly set up. + */ +#define MC146818_PUTTOD(sc, regs) \ + do { \ + int i; \ + \ + /* stop updates while setting */ \ + mc146818_write(sc, MC_REGB, \ + mc146818_read(sc, MC_REGB) | MC_REGB_SET); \ + \ + /* write all of the tod/alarm regs */ \ + for (i = 0; i < MC_NTODREGS; i++) \ + mc146818_write(sc, i, (*regs)[i]); \ + \ + /* reenable updates */ \ + mc146818_write(sc, MC_REGB, \ + mc146818_read(sc, MC_REGB) & ~MC_REGB_SET); \ + } while (0); |